1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/TargetParser.h" 31 #include <algorithm> 32 #include <memory> 33 34 using namespace clang; 35 36 //===----------------------------------------------------------------------===// 37 // Common code shared among targets. 38 //===----------------------------------------------------------------------===// 39 40 /// DefineStd - Define a macro name and standard variants. For example if 41 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 42 /// when in GNU mode. 43 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 44 const LangOptions &Opts) { 45 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 46 47 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 48 // in the user's namespace. 49 if (Opts.GNUMode) 50 Builder.defineMacro(MacroName); 51 52 // Define __unix. 53 Builder.defineMacro("__" + MacroName); 54 55 // Define __unix__. 56 Builder.defineMacro("__" + MacroName + "__"); 57 } 58 59 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 60 bool Tuning = true) { 61 Builder.defineMacro("__" + CPUName); 62 Builder.defineMacro("__" + CPUName + "__"); 63 if (Tuning) 64 Builder.defineMacro("__tune_" + CPUName + "__"); 65 } 66 67 //===----------------------------------------------------------------------===// 68 // Defines specific to certain operating systems. 69 //===----------------------------------------------------------------------===// 70 71 namespace { 72 template<typename TgtInfo> 73 class OSTargetInfo : public TgtInfo { 74 protected: 75 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 76 MacroBuilder &Builder) const=0; 77 public: 78 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 79 void getTargetDefines(const LangOptions &Opts, 80 MacroBuilder &Builder) const override { 81 TgtInfo::getTargetDefines(Opts, Builder); 82 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 83 } 84 85 }; 86 87 // CloudABI Target 88 template <typename Target> 89 class CloudABITargetInfo : public OSTargetInfo<Target> { 90 protected: 91 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 92 MacroBuilder &Builder) const override { 93 Builder.defineMacro("__CloudABI__"); 94 Builder.defineMacro("__ELF__"); 95 96 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 97 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 98 Builder.defineMacro("__STDC_UTF_16__"); 99 Builder.defineMacro("__STDC_UTF_32__"); 100 } 101 102 public: 103 CloudABITargetInfo(const llvm::Triple &Triple) 104 : OSTargetInfo<Target>(Triple) { 105 this->UserLabelPrefix = ""; 106 } 107 }; 108 109 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 110 const llvm::Triple &Triple, 111 StringRef &PlatformName, 112 VersionTuple &PlatformMinVersion) { 113 Builder.defineMacro("__APPLE_CC__", "6000"); 114 Builder.defineMacro("__APPLE__"); 115 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 116 // AddressSanitizer doesn't play well with source fortification, which is on 117 // by default on Darwin. 118 if (Opts.Sanitize.has(SanitizerKind::Address)) 119 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 120 121 if (!Opts.ObjCAutoRefCount) { 122 // __weak is always defined, for use in blocks and with objc pointers. 123 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 124 125 // Darwin defines __strong even in C mode (just to nothing). 126 if (Opts.getGC() != LangOptions::NonGC) 127 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 128 else 129 Builder.defineMacro("__strong", ""); 130 131 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 132 // allow this in C, since one might have block pointers in structs that 133 // are used in pure C code and in Objective-C ARC. 134 Builder.defineMacro("__unsafe_unretained", ""); 135 } 136 137 if (Opts.Static) 138 Builder.defineMacro("__STATIC__"); 139 else 140 Builder.defineMacro("__DYNAMIC__"); 141 142 if (Opts.POSIXThreads) 143 Builder.defineMacro("_REENTRANT"); 144 145 // Get the platform type and version number from the triple. 146 unsigned Maj, Min, Rev; 147 if (Triple.isMacOSX()) { 148 Triple.getMacOSXVersion(Maj, Min, Rev); 149 PlatformName = "macosx"; 150 } else { 151 Triple.getOSVersion(Maj, Min, Rev); 152 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 153 } 154 155 // If -target arch-pc-win32-macho option specified, we're 156 // generating code for Win32 ABI. No need to emit 157 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 158 if (PlatformName == "win32") { 159 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 160 return; 161 } 162 163 // Set the appropriate OS version define. 164 if (Triple.isiOS()) { 165 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 166 char Str[6]; 167 Str[0] = '0' + Maj; 168 Str[1] = '0' + (Min / 10); 169 Str[2] = '0' + (Min % 10); 170 Str[3] = '0' + (Rev / 10); 171 Str[4] = '0' + (Rev % 10); 172 Str[5] = '\0'; 173 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str); 174 } else if (Triple.isMacOSX()) { 175 // Note that the Driver allows versions which aren't representable in the 176 // define (because we only get a single digit for the minor and micro 177 // revision numbers). So, we limit them to the maximum representable 178 // version. 179 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 180 char Str[7]; 181 if (Maj < 10 || (Maj == 10 && Min < 10)) { 182 Str[0] = '0' + (Maj / 10); 183 Str[1] = '0' + (Maj % 10); 184 Str[2] = '0' + std::min(Min, 9U); 185 Str[3] = '0' + std::min(Rev, 9U); 186 Str[4] = '\0'; 187 } else { 188 // Handle versions > 10.9. 189 Str[0] = '0' + (Maj / 10); 190 Str[1] = '0' + (Maj % 10); 191 Str[2] = '0' + (Min / 10); 192 Str[3] = '0' + (Min % 10); 193 Str[4] = '0' + (Rev / 10); 194 Str[5] = '0' + (Rev % 10); 195 Str[6] = '\0'; 196 } 197 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 198 } 199 200 // Tell users about the kernel if there is one. 201 if (Triple.isOSDarwin()) 202 Builder.defineMacro("__MACH__"); 203 204 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 205 } 206 207 template<typename Target> 208 class DarwinTargetInfo : public OSTargetInfo<Target> { 209 protected: 210 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 211 MacroBuilder &Builder) const override { 212 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 213 this->PlatformMinVersion); 214 } 215 216 public: 217 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 218 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 219 this->MCountName = "\01mcount"; 220 } 221 222 std::string isValidSectionSpecifier(StringRef SR) const override { 223 // Let MCSectionMachO validate this. 224 StringRef Segment, Section; 225 unsigned TAA, StubSize; 226 bool HasTAA; 227 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 228 TAA, HasTAA, StubSize); 229 } 230 231 const char *getStaticInitSectionSpecifier() const override { 232 // FIXME: We should return 0 when building kexts. 233 return "__TEXT,__StaticInit,regular,pure_instructions"; 234 } 235 236 /// Darwin does not support protected visibility. Darwin's "default" 237 /// is very similar to ELF's "protected"; Darwin requires a "weak" 238 /// attribute on declarations that can be dynamically replaced. 239 bool hasProtectedVisibility() const override { 240 return false; 241 } 242 }; 243 244 245 // DragonFlyBSD Target 246 template<typename Target> 247 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 248 protected: 249 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 250 MacroBuilder &Builder) const override { 251 // DragonFly defines; list based off of gcc output 252 Builder.defineMacro("__DragonFly__"); 253 Builder.defineMacro("__DragonFly_cc_version", "100001"); 254 Builder.defineMacro("__ELF__"); 255 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 256 Builder.defineMacro("__tune_i386__"); 257 DefineStd(Builder, "unix", Opts); 258 } 259 public: 260 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 261 : OSTargetInfo<Target>(Triple) { 262 this->UserLabelPrefix = ""; 263 264 switch (Triple.getArch()) { 265 default: 266 case llvm::Triple::x86: 267 case llvm::Triple::x86_64: 268 this->MCountName = ".mcount"; 269 break; 270 } 271 } 272 }; 273 274 // FreeBSD Target 275 template<typename Target> 276 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 277 protected: 278 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 279 MacroBuilder &Builder) const override { 280 // FreeBSD defines; list based off of gcc output 281 282 unsigned Release = Triple.getOSMajorVersion(); 283 if (Release == 0U) 284 Release = 8; 285 286 Builder.defineMacro("__FreeBSD__", Twine(Release)); 287 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 288 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 289 DefineStd(Builder, "unix", Opts); 290 Builder.defineMacro("__ELF__"); 291 292 // On FreeBSD, wchar_t contains the number of the code point as 293 // used by the character set of the locale. These character sets are 294 // not necessarily a superset of ASCII. 295 // 296 // FIXME: This is wrong; the macro refers to the numerical values 297 // of wchar_t *literals*, which are not locale-dependent. However, 298 // FreeBSD systems apparently depend on us getting this wrong, and 299 // setting this to 1 is conforming even if all the basic source 300 // character literals have the same encoding as char and wchar_t. 301 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 302 } 303 public: 304 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 305 this->UserLabelPrefix = ""; 306 307 switch (Triple.getArch()) { 308 default: 309 case llvm::Triple::x86: 310 case llvm::Triple::x86_64: 311 this->MCountName = ".mcount"; 312 break; 313 case llvm::Triple::mips: 314 case llvm::Triple::mipsel: 315 case llvm::Triple::ppc: 316 case llvm::Triple::ppc64: 317 case llvm::Triple::ppc64le: 318 this->MCountName = "_mcount"; 319 break; 320 case llvm::Triple::arm: 321 this->MCountName = "__mcount"; 322 break; 323 } 324 } 325 }; 326 327 // GNU/kFreeBSD Target 328 template<typename Target> 329 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 330 protected: 331 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 332 MacroBuilder &Builder) const override { 333 // GNU/kFreeBSD defines; list based off of gcc output 334 335 DefineStd(Builder, "unix", Opts); 336 Builder.defineMacro("__FreeBSD_kernel__"); 337 Builder.defineMacro("__GLIBC__"); 338 Builder.defineMacro("__ELF__"); 339 if (Opts.POSIXThreads) 340 Builder.defineMacro("_REENTRANT"); 341 if (Opts.CPlusPlus) 342 Builder.defineMacro("_GNU_SOURCE"); 343 } 344 public: 345 KFreeBSDTargetInfo(const llvm::Triple &Triple) 346 : OSTargetInfo<Target>(Triple) { 347 this->UserLabelPrefix = ""; 348 } 349 }; 350 351 // Minix Target 352 template<typename Target> 353 class MinixTargetInfo : public OSTargetInfo<Target> { 354 protected: 355 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 356 MacroBuilder &Builder) const override { 357 // Minix defines 358 359 Builder.defineMacro("__minix", "3"); 360 Builder.defineMacro("_EM_WSIZE", "4"); 361 Builder.defineMacro("_EM_PSIZE", "4"); 362 Builder.defineMacro("_EM_SSIZE", "2"); 363 Builder.defineMacro("_EM_LSIZE", "4"); 364 Builder.defineMacro("_EM_FSIZE", "4"); 365 Builder.defineMacro("_EM_DSIZE", "8"); 366 Builder.defineMacro("__ELF__"); 367 DefineStd(Builder, "unix", Opts); 368 } 369 public: 370 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 371 this->UserLabelPrefix = ""; 372 } 373 }; 374 375 // Linux target 376 template<typename Target> 377 class LinuxTargetInfo : public OSTargetInfo<Target> { 378 protected: 379 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 380 MacroBuilder &Builder) const override { 381 // Linux defines; list based off of gcc output 382 DefineStd(Builder, "unix", Opts); 383 DefineStd(Builder, "linux", Opts); 384 Builder.defineMacro("__gnu_linux__"); 385 Builder.defineMacro("__ELF__"); 386 if (Triple.isAndroid()) { 387 Builder.defineMacro("__ANDROID__", "1"); 388 unsigned Maj, Min, Rev; 389 Triple.getEnvironmentVersion(Maj, Min, Rev); 390 this->PlatformName = "android"; 391 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 392 } 393 if (Opts.POSIXThreads) 394 Builder.defineMacro("_REENTRANT"); 395 if (Opts.CPlusPlus) 396 Builder.defineMacro("_GNU_SOURCE"); 397 } 398 public: 399 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 400 this->UserLabelPrefix = ""; 401 this->WIntType = TargetInfo::UnsignedInt; 402 403 switch (Triple.getArch()) { 404 default: 405 break; 406 case llvm::Triple::ppc: 407 case llvm::Triple::ppc64: 408 case llvm::Triple::ppc64le: 409 this->MCountName = "_mcount"; 410 break; 411 } 412 } 413 414 const char *getStaticInitSectionSpecifier() const override { 415 return ".text.startup"; 416 } 417 }; 418 419 // NetBSD Target 420 template<typename Target> 421 class NetBSDTargetInfo : public OSTargetInfo<Target> { 422 protected: 423 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 424 MacroBuilder &Builder) const override { 425 // NetBSD defines; list based off of gcc output 426 Builder.defineMacro("__NetBSD__"); 427 Builder.defineMacro("__unix__"); 428 Builder.defineMacro("__ELF__"); 429 if (Opts.POSIXThreads) 430 Builder.defineMacro("_POSIX_THREADS"); 431 432 switch (Triple.getArch()) { 433 default: 434 break; 435 case llvm::Triple::arm: 436 case llvm::Triple::armeb: 437 case llvm::Triple::thumb: 438 case llvm::Triple::thumbeb: 439 Builder.defineMacro("__ARM_DWARF_EH__"); 440 break; 441 } 442 } 443 public: 444 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 445 this->UserLabelPrefix = ""; 446 this->MCountName = "_mcount"; 447 } 448 }; 449 450 // OpenBSD Target 451 template<typename Target> 452 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 453 protected: 454 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 455 MacroBuilder &Builder) const override { 456 // OpenBSD defines; list based off of gcc output 457 458 Builder.defineMacro("__OpenBSD__"); 459 DefineStd(Builder, "unix", Opts); 460 Builder.defineMacro("__ELF__"); 461 if (Opts.POSIXThreads) 462 Builder.defineMacro("_REENTRANT"); 463 } 464 public: 465 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 466 this->UserLabelPrefix = ""; 467 this->TLSSupported = false; 468 469 switch (Triple.getArch()) { 470 default: 471 case llvm::Triple::x86: 472 case llvm::Triple::x86_64: 473 case llvm::Triple::arm: 474 case llvm::Triple::sparc: 475 this->MCountName = "__mcount"; 476 break; 477 case llvm::Triple::mips64: 478 case llvm::Triple::mips64el: 479 case llvm::Triple::ppc: 480 case llvm::Triple::sparcv9: 481 this->MCountName = "_mcount"; 482 break; 483 } 484 } 485 }; 486 487 // Bitrig Target 488 template<typename Target> 489 class BitrigTargetInfo : public OSTargetInfo<Target> { 490 protected: 491 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 492 MacroBuilder &Builder) const override { 493 // Bitrig defines; list based off of gcc output 494 495 Builder.defineMacro("__Bitrig__"); 496 DefineStd(Builder, "unix", Opts); 497 Builder.defineMacro("__ELF__"); 498 if (Opts.POSIXThreads) 499 Builder.defineMacro("_REENTRANT"); 500 501 switch (Triple.getArch()) { 502 default: 503 break; 504 case llvm::Triple::arm: 505 case llvm::Triple::armeb: 506 case llvm::Triple::thumb: 507 case llvm::Triple::thumbeb: 508 Builder.defineMacro("__ARM_DWARF_EH__"); 509 break; 510 } 511 } 512 public: 513 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 514 this->UserLabelPrefix = ""; 515 this->MCountName = "__mcount"; 516 } 517 }; 518 519 // PSP Target 520 template<typename Target> 521 class PSPTargetInfo : public OSTargetInfo<Target> { 522 protected: 523 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 524 MacroBuilder &Builder) const override { 525 // PSP defines; list based on the output of the pspdev gcc toolchain. 526 Builder.defineMacro("PSP"); 527 Builder.defineMacro("_PSP"); 528 Builder.defineMacro("__psp__"); 529 Builder.defineMacro("__ELF__"); 530 } 531 public: 532 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 533 this->UserLabelPrefix = ""; 534 } 535 }; 536 537 // PS3 PPU Target 538 template<typename Target> 539 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 540 protected: 541 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 542 MacroBuilder &Builder) const override { 543 // PS3 PPU defines. 544 Builder.defineMacro("__PPC__"); 545 Builder.defineMacro("__PPU__"); 546 Builder.defineMacro("__CELLOS_LV2__"); 547 Builder.defineMacro("__ELF__"); 548 Builder.defineMacro("__LP32__"); 549 Builder.defineMacro("_ARCH_PPC64"); 550 Builder.defineMacro("__powerpc64__"); 551 } 552 public: 553 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 554 this->UserLabelPrefix = ""; 555 this->LongWidth = this->LongAlign = 32; 556 this->PointerWidth = this->PointerAlign = 32; 557 this->IntMaxType = TargetInfo::SignedLongLong; 558 this->Int64Type = TargetInfo::SignedLongLong; 559 this->SizeType = TargetInfo::UnsignedInt; 560 this->DataLayoutString = "E-m:e-p:32:32-i64:64-n32:64"; 561 } 562 }; 563 564 template <typename Target> 565 class PS4OSTargetInfo : public OSTargetInfo<Target> { 566 protected: 567 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 568 MacroBuilder &Builder) const override { 569 Builder.defineMacro("__FreeBSD__", "9"); 570 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 571 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 572 DefineStd(Builder, "unix", Opts); 573 Builder.defineMacro("__ELF__"); 574 Builder.defineMacro("__PS4__"); 575 } 576 public: 577 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 578 this->WCharType = this->UnsignedShort; 579 580 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 581 this->MaxTLSAlign = 256; 582 this->UserLabelPrefix = ""; 583 584 switch (Triple.getArch()) { 585 default: 586 case llvm::Triple::x86_64: 587 this->MCountName = ".mcount"; 588 break; 589 } 590 } 591 }; 592 593 // Solaris target 594 template<typename Target> 595 class SolarisTargetInfo : public OSTargetInfo<Target> { 596 protected: 597 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 598 MacroBuilder &Builder) const override { 599 DefineStd(Builder, "sun", Opts); 600 DefineStd(Builder, "unix", Opts); 601 Builder.defineMacro("__ELF__"); 602 Builder.defineMacro("__svr4__"); 603 Builder.defineMacro("__SVR4"); 604 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 605 // newer, but to 500 for everything else. feature_test.h has a check to 606 // ensure that you are not using C99 with an old version of X/Open or C89 607 // with a new version. 608 if (Opts.C99) 609 Builder.defineMacro("_XOPEN_SOURCE", "600"); 610 else 611 Builder.defineMacro("_XOPEN_SOURCE", "500"); 612 if (Opts.CPlusPlus) 613 Builder.defineMacro("__C99FEATURES__"); 614 Builder.defineMacro("_LARGEFILE_SOURCE"); 615 Builder.defineMacro("_LARGEFILE64_SOURCE"); 616 Builder.defineMacro("__EXTENSIONS__"); 617 Builder.defineMacro("_REENTRANT"); 618 } 619 public: 620 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 621 this->UserLabelPrefix = ""; 622 this->WCharType = this->SignedInt; 623 // FIXME: WIntType should be SignedLong 624 } 625 }; 626 627 // Windows target 628 template<typename Target> 629 class WindowsTargetInfo : public OSTargetInfo<Target> { 630 protected: 631 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 632 MacroBuilder &Builder) const override { 633 Builder.defineMacro("_WIN32"); 634 } 635 void getVisualStudioDefines(const LangOptions &Opts, 636 MacroBuilder &Builder) const { 637 if (Opts.CPlusPlus) { 638 if (Opts.RTTIData) 639 Builder.defineMacro("_CPPRTTI"); 640 641 if (Opts.CXXExceptions) 642 Builder.defineMacro("_CPPUNWIND"); 643 } 644 645 if (Opts.Bool) 646 Builder.defineMacro("__BOOL_DEFINED"); 647 648 if (!Opts.CharIsSigned) 649 Builder.defineMacro("_CHAR_UNSIGNED"); 650 651 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 652 // but it works for now. 653 if (Opts.POSIXThreads) 654 Builder.defineMacro("_MT"); 655 656 if (Opts.MSCompatibilityVersion) { 657 Builder.defineMacro("_MSC_VER", 658 Twine(Opts.MSCompatibilityVersion / 100000)); 659 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 660 // FIXME We cannot encode the revision information into 32-bits 661 Builder.defineMacro("_MSC_BUILD", Twine(1)); 662 663 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 664 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 665 } 666 667 if (Opts.MicrosoftExt) { 668 Builder.defineMacro("_MSC_EXTENSIONS"); 669 670 if (Opts.CPlusPlus11) { 671 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 672 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 673 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 674 } 675 } 676 677 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 678 } 679 680 public: 681 WindowsTargetInfo(const llvm::Triple &Triple) 682 : OSTargetInfo<Target>(Triple) {} 683 }; 684 685 template <typename Target> 686 class NaClTargetInfo : public OSTargetInfo<Target> { 687 protected: 688 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 689 MacroBuilder &Builder) const override { 690 if (Opts.POSIXThreads) 691 Builder.defineMacro("_REENTRANT"); 692 if (Opts.CPlusPlus) 693 Builder.defineMacro("_GNU_SOURCE"); 694 695 DefineStd(Builder, "unix", Opts); 696 Builder.defineMacro("__ELF__"); 697 Builder.defineMacro("__native_client__"); 698 } 699 700 public: 701 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 702 this->UserLabelPrefix = ""; 703 this->LongAlign = 32; 704 this->LongWidth = 32; 705 this->PointerAlign = 32; 706 this->PointerWidth = 32; 707 this->IntMaxType = TargetInfo::SignedLongLong; 708 this->Int64Type = TargetInfo::SignedLongLong; 709 this->DoubleAlign = 64; 710 this->LongDoubleWidth = 64; 711 this->LongDoubleAlign = 64; 712 this->LongLongWidth = 64; 713 this->LongLongAlign = 64; 714 this->SizeType = TargetInfo::UnsignedInt; 715 this->PtrDiffType = TargetInfo::SignedInt; 716 this->IntPtrType = TargetInfo::SignedInt; 717 // RegParmMax is inherited from the underlying architecture 718 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 719 if (Triple.getArch() == llvm::Triple::arm) { 720 // Handled in ARM's setABI(). 721 } else if (Triple.getArch() == llvm::Triple::x86) { 722 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 723 } else if (Triple.getArch() == llvm::Triple::x86_64) { 724 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 725 } else if (Triple.getArch() == llvm::Triple::mipsel) { 726 // Handled on mips' setDataLayoutString. 727 } else { 728 assert(Triple.getArch() == llvm::Triple::le32); 729 this->DataLayoutString = "e-p:32:32-i64:64"; 730 } 731 } 732 }; 733 734 // WebAssembly target 735 template <typename Target> 736 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 737 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 738 MacroBuilder &Builder) const final { 739 // A common platform macro. 740 if (Opts.POSIXThreads) 741 Builder.defineMacro("_REENTRANT"); 742 // Follow g++ convention and predefine _GNU_SOURCE for C++. 743 if (Opts.CPlusPlus) 744 Builder.defineMacro("_GNU_SOURCE"); 745 } 746 747 // As an optimization, group static init code together in a section. 748 const char *getStaticInitSectionSpecifier() const final { 749 return ".text.__startup"; 750 } 751 752 public: 753 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple) 754 : OSTargetInfo<Target>(Triple) { 755 this->MCountName = "__mcount"; 756 this->UserLabelPrefix = ""; 757 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 758 } 759 }; 760 761 //===----------------------------------------------------------------------===// 762 // Specific target implementations. 763 //===----------------------------------------------------------------------===// 764 765 // PPC abstract base class 766 class PPCTargetInfo : public TargetInfo { 767 static const Builtin::Info BuiltinInfo[]; 768 static const char * const GCCRegNames[]; 769 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 770 std::string CPU; 771 772 // Target cpu features. 773 bool HasVSX; 774 bool HasP8Vector; 775 bool HasP8Crypto; 776 bool HasDirectMove; 777 bool HasQPX; 778 bool HasHTM; 779 bool HasBPERMD; 780 bool HasExtDiv; 781 782 protected: 783 std::string ABI; 784 785 public: 786 PPCTargetInfo(const llvm::Triple &Triple) 787 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 788 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 789 HasBPERMD(false), HasExtDiv(false) { 790 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 791 SimdDefaultAlign = 128; 792 LongDoubleWidth = LongDoubleAlign = 128; 793 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 794 } 795 796 /// \brief Flags for architecture specific defines. 797 typedef enum { 798 ArchDefineNone = 0, 799 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 800 ArchDefinePpcgr = 1 << 1, 801 ArchDefinePpcsq = 1 << 2, 802 ArchDefine440 = 1 << 3, 803 ArchDefine603 = 1 << 4, 804 ArchDefine604 = 1 << 5, 805 ArchDefinePwr4 = 1 << 6, 806 ArchDefinePwr5 = 1 << 7, 807 ArchDefinePwr5x = 1 << 8, 808 ArchDefinePwr6 = 1 << 9, 809 ArchDefinePwr6x = 1 << 10, 810 ArchDefinePwr7 = 1 << 11, 811 ArchDefinePwr8 = 1 << 12, 812 ArchDefineA2 = 1 << 13, 813 ArchDefineA2q = 1 << 14 814 } ArchDefineTypes; 815 816 // Note: GCC recognizes the following additional cpus: 817 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 818 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 819 // titan, rs64. 820 bool setCPU(const std::string &Name) override { 821 bool CPUKnown = llvm::StringSwitch<bool>(Name) 822 .Case("generic", true) 823 .Case("440", true) 824 .Case("450", true) 825 .Case("601", true) 826 .Case("602", true) 827 .Case("603", true) 828 .Case("603e", true) 829 .Case("603ev", true) 830 .Case("604", true) 831 .Case("604e", true) 832 .Case("620", true) 833 .Case("630", true) 834 .Case("g3", true) 835 .Case("7400", true) 836 .Case("g4", true) 837 .Case("7450", true) 838 .Case("g4+", true) 839 .Case("750", true) 840 .Case("970", true) 841 .Case("g5", true) 842 .Case("a2", true) 843 .Case("a2q", true) 844 .Case("e500mc", true) 845 .Case("e5500", true) 846 .Case("power3", true) 847 .Case("pwr3", true) 848 .Case("power4", true) 849 .Case("pwr4", true) 850 .Case("power5", true) 851 .Case("pwr5", true) 852 .Case("power5x", true) 853 .Case("pwr5x", true) 854 .Case("power6", true) 855 .Case("pwr6", true) 856 .Case("power6x", true) 857 .Case("pwr6x", true) 858 .Case("power7", true) 859 .Case("pwr7", true) 860 .Case("power8", true) 861 .Case("pwr8", true) 862 .Case("powerpc", true) 863 .Case("ppc", true) 864 .Case("powerpc64", true) 865 .Case("ppc64", true) 866 .Case("powerpc64le", true) 867 .Case("ppc64le", true) 868 .Default(false); 869 870 if (CPUKnown) 871 CPU = Name; 872 873 return CPUKnown; 874 } 875 876 877 StringRef getABI() const override { return ABI; } 878 879 void getTargetBuiltins(const Builtin::Info *&Records, 880 unsigned &NumRecords) const override { 881 Records = BuiltinInfo; 882 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 883 } 884 885 bool isCLZForZeroUndef() const override { return false; } 886 887 void getTargetDefines(const LangOptions &Opts, 888 MacroBuilder &Builder) const override; 889 890 bool 891 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 892 StringRef CPU, 893 const std::vector<std::string> &FeaturesVec) const override; 894 895 bool handleTargetFeatures(std::vector<std::string> &Features, 896 DiagnosticsEngine &Diags) override; 897 bool hasFeature(StringRef Feature) const override; 898 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 899 bool Enabled) const override; 900 901 void getGCCRegNames(const char * const *&Names, 902 unsigned &NumNames) const override; 903 void getGCCRegAliases(const GCCRegAlias *&Aliases, 904 unsigned &NumAliases) const override; 905 bool validateAsmConstraint(const char *&Name, 906 TargetInfo::ConstraintInfo &Info) const override { 907 switch (*Name) { 908 default: return false; 909 case 'O': // Zero 910 break; 911 case 'b': // Base register 912 case 'f': // Floating point register 913 Info.setAllowsRegister(); 914 break; 915 // FIXME: The following are added to allow parsing. 916 // I just took a guess at what the actions should be. 917 // Also, is more specific checking needed? I.e. specific registers? 918 case 'd': // Floating point register (containing 64-bit value) 919 case 'v': // Altivec vector register 920 Info.setAllowsRegister(); 921 break; 922 case 'w': 923 switch (Name[1]) { 924 case 'd':// VSX vector register to hold vector double data 925 case 'f':// VSX vector register to hold vector float data 926 case 's':// VSX vector register to hold scalar float data 927 case 'a':// Any VSX register 928 case 'c':// An individual CR bit 929 break; 930 default: 931 return false; 932 } 933 Info.setAllowsRegister(); 934 Name++; // Skip over 'w'. 935 break; 936 case 'h': // `MQ', `CTR', or `LINK' register 937 case 'q': // `MQ' register 938 case 'c': // `CTR' register 939 case 'l': // `LINK' register 940 case 'x': // `CR' register (condition register) number 0 941 case 'y': // `CR' register (condition register) 942 case 'z': // `XER[CA]' carry bit (part of the XER register) 943 Info.setAllowsRegister(); 944 break; 945 case 'I': // Signed 16-bit constant 946 case 'J': // Unsigned 16-bit constant shifted left 16 bits 947 // (use `L' instead for SImode constants) 948 case 'K': // Unsigned 16-bit constant 949 case 'L': // Signed 16-bit constant shifted left 16 bits 950 case 'M': // Constant larger than 31 951 case 'N': // Exact power of 2 952 case 'P': // Constant whose negation is a signed 16-bit constant 953 case 'G': // Floating point constant that can be loaded into a 954 // register with one instruction per word 955 case 'H': // Integer/Floating point constant that can be loaded 956 // into a register using three instructions 957 break; 958 case 'm': // Memory operand. Note that on PowerPC targets, m can 959 // include addresses that update the base register. It 960 // is therefore only safe to use `m' in an asm statement 961 // if that asm statement accesses the operand exactly once. 962 // The asm statement must also use `%U<opno>' as a 963 // placeholder for the "update" flag in the corresponding 964 // load or store instruction. For example: 965 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 966 // is correct but: 967 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 968 // is not. Use es rather than m if you don't want the base 969 // register to be updated. 970 case 'e': 971 if (Name[1] != 's') 972 return false; 973 // es: A "stable" memory operand; that is, one which does not 974 // include any automodification of the base register. Unlike 975 // `m', this constraint can be used in asm statements that 976 // might access the operand several times, or that might not 977 // access it at all. 978 Info.setAllowsMemory(); 979 Name++; // Skip over 'e'. 980 break; 981 case 'Q': // Memory operand that is an offset from a register (it is 982 // usually better to use `m' or `es' in asm statements) 983 case 'Z': // Memory operand that is an indexed or indirect from a 984 // register (it is usually better to use `m' or `es' in 985 // asm statements) 986 Info.setAllowsMemory(); 987 Info.setAllowsRegister(); 988 break; 989 case 'R': // AIX TOC entry 990 case 'a': // Address operand that is an indexed or indirect from a 991 // register (`p' is preferable for asm statements) 992 case 'S': // Constant suitable as a 64-bit mask operand 993 case 'T': // Constant suitable as a 32-bit mask operand 994 case 'U': // System V Release 4 small data area reference 995 case 't': // AND masks that can be performed by two rldic{l, r} 996 // instructions 997 case 'W': // Vector constant that does not require memory 998 case 'j': // Vector constant that is all zeros. 999 break; 1000 // End FIXME. 1001 } 1002 return true; 1003 } 1004 std::string convertConstraint(const char *&Constraint) const override { 1005 std::string R; 1006 switch (*Constraint) { 1007 case 'e': 1008 case 'w': 1009 // Two-character constraint; add "^" hint for later parsing. 1010 R = std::string("^") + std::string(Constraint, 2); 1011 Constraint++; 1012 break; 1013 default: 1014 return TargetInfo::convertConstraint(Constraint); 1015 } 1016 return R; 1017 } 1018 const char *getClobbers() const override { 1019 return ""; 1020 } 1021 int getEHDataRegisterNumber(unsigned RegNo) const override { 1022 if (RegNo == 0) return 3; 1023 if (RegNo == 1) return 4; 1024 return -1; 1025 } 1026 1027 bool hasSjLjLowering() const override { 1028 return true; 1029 } 1030 1031 bool useFloat128ManglingForLongDouble() const override { 1032 return LongDoubleWidth == 128 && 1033 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1034 getTriple().isOSBinFormatELF(); 1035 } 1036 }; 1037 1038 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1039 #define BUILTIN(ID, TYPE, ATTRS) \ 1040 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1041 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1042 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1043 #include "clang/Basic/BuiltinsPPC.def" 1044 }; 1045 1046 /// handleTargetFeatures - Perform initialization based on the user 1047 /// configured set of features. 1048 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1049 DiagnosticsEngine &Diags) { 1050 for (const auto &Feature : Features) { 1051 if (Feature == "+vsx") { 1052 HasVSX = true; 1053 } else if (Feature == "+bpermd") { 1054 HasBPERMD = true; 1055 } else if (Feature == "+extdiv") { 1056 HasExtDiv = true; 1057 } else if (Feature == "+power8-vector") { 1058 HasP8Vector = true; 1059 } else if (Feature == "+crypto") { 1060 HasP8Crypto = true; 1061 } else if (Feature == "+direct-move") { 1062 HasDirectMove = true; 1063 } else if (Feature == "+qpx") { 1064 HasQPX = true; 1065 } else if (Feature == "+htm") { 1066 HasHTM = true; 1067 } 1068 // TODO: Finish this list and add an assert that we've handled them 1069 // all. 1070 } 1071 1072 return true; 1073 } 1074 1075 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1076 /// #defines that are not tied to a specific subtarget. 1077 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1078 MacroBuilder &Builder) const { 1079 // Target identification. 1080 Builder.defineMacro("__ppc__"); 1081 Builder.defineMacro("__PPC__"); 1082 Builder.defineMacro("_ARCH_PPC"); 1083 Builder.defineMacro("__powerpc__"); 1084 Builder.defineMacro("__POWERPC__"); 1085 if (PointerWidth == 64) { 1086 Builder.defineMacro("_ARCH_PPC64"); 1087 Builder.defineMacro("__powerpc64__"); 1088 Builder.defineMacro("__ppc64__"); 1089 Builder.defineMacro("__PPC64__"); 1090 } 1091 1092 // Target properties. 1093 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1094 Builder.defineMacro("_LITTLE_ENDIAN"); 1095 } else { 1096 if (getTriple().getOS() != llvm::Triple::NetBSD && 1097 getTriple().getOS() != llvm::Triple::OpenBSD) 1098 Builder.defineMacro("_BIG_ENDIAN"); 1099 } 1100 1101 // ABI options. 1102 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1103 Builder.defineMacro("_CALL_ELF", "1"); 1104 if (ABI == "elfv2") 1105 Builder.defineMacro("_CALL_ELF", "2"); 1106 1107 // Subtarget options. 1108 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1109 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1110 1111 // FIXME: Should be controlled by command line option. 1112 if (LongDoubleWidth == 128) 1113 Builder.defineMacro("__LONG_DOUBLE_128__"); 1114 1115 if (Opts.AltiVec) { 1116 Builder.defineMacro("__VEC__", "10206"); 1117 Builder.defineMacro("__ALTIVEC__"); 1118 } 1119 1120 // CPU identification. 1121 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1122 .Case("440", ArchDefineName) 1123 .Case("450", ArchDefineName | ArchDefine440) 1124 .Case("601", ArchDefineName) 1125 .Case("602", ArchDefineName | ArchDefinePpcgr) 1126 .Case("603", ArchDefineName | ArchDefinePpcgr) 1127 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1128 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1129 .Case("604", ArchDefineName | ArchDefinePpcgr) 1130 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1131 .Case("620", ArchDefineName | ArchDefinePpcgr) 1132 .Case("630", ArchDefineName | ArchDefinePpcgr) 1133 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1134 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1135 .Case("750", ArchDefineName | ArchDefinePpcgr) 1136 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1137 | ArchDefinePpcsq) 1138 .Case("a2", ArchDefineA2) 1139 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1140 .Case("pwr3", ArchDefinePpcgr) 1141 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1142 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1143 | ArchDefinePpcsq) 1144 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1145 | ArchDefinePpcgr | ArchDefinePpcsq) 1146 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1147 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1148 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1149 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1150 | ArchDefinePpcsq) 1151 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1152 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1153 | ArchDefinePpcgr | ArchDefinePpcsq) 1154 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1155 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1156 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1157 .Case("power3", ArchDefinePpcgr) 1158 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1159 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1160 | ArchDefinePpcsq) 1161 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1162 | ArchDefinePpcgr | ArchDefinePpcsq) 1163 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1164 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1165 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1166 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1167 | ArchDefinePpcsq) 1168 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1169 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1170 | ArchDefinePpcgr | ArchDefinePpcsq) 1171 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1172 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1173 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1174 .Default(ArchDefineNone); 1175 1176 if (defs & ArchDefineName) 1177 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1178 if (defs & ArchDefinePpcgr) 1179 Builder.defineMacro("_ARCH_PPCGR"); 1180 if (defs & ArchDefinePpcsq) 1181 Builder.defineMacro("_ARCH_PPCSQ"); 1182 if (defs & ArchDefine440) 1183 Builder.defineMacro("_ARCH_440"); 1184 if (defs & ArchDefine603) 1185 Builder.defineMacro("_ARCH_603"); 1186 if (defs & ArchDefine604) 1187 Builder.defineMacro("_ARCH_604"); 1188 if (defs & ArchDefinePwr4) 1189 Builder.defineMacro("_ARCH_PWR4"); 1190 if (defs & ArchDefinePwr5) 1191 Builder.defineMacro("_ARCH_PWR5"); 1192 if (defs & ArchDefinePwr5x) 1193 Builder.defineMacro("_ARCH_PWR5X"); 1194 if (defs & ArchDefinePwr6) 1195 Builder.defineMacro("_ARCH_PWR6"); 1196 if (defs & ArchDefinePwr6x) 1197 Builder.defineMacro("_ARCH_PWR6X"); 1198 if (defs & ArchDefinePwr7) 1199 Builder.defineMacro("_ARCH_PWR7"); 1200 if (defs & ArchDefinePwr8) 1201 Builder.defineMacro("_ARCH_PWR8"); 1202 if (defs & ArchDefineA2) 1203 Builder.defineMacro("_ARCH_A2"); 1204 if (defs & ArchDefineA2q) { 1205 Builder.defineMacro("_ARCH_A2Q"); 1206 Builder.defineMacro("_ARCH_QP"); 1207 } 1208 1209 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1210 Builder.defineMacro("__bg__"); 1211 Builder.defineMacro("__THW_BLUEGENE__"); 1212 Builder.defineMacro("__bgq__"); 1213 Builder.defineMacro("__TOS_BGQ__"); 1214 } 1215 1216 if (HasVSX) 1217 Builder.defineMacro("__VSX__"); 1218 if (HasP8Vector) 1219 Builder.defineMacro("__POWER8_VECTOR__"); 1220 if (HasP8Crypto) 1221 Builder.defineMacro("__CRYPTO__"); 1222 if (HasHTM) 1223 Builder.defineMacro("__HTM__"); 1224 1225 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1226 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1227 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1228 if (PointerWidth == 64) 1229 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1230 1231 // FIXME: The following are not yet generated here by Clang, but are 1232 // generated by GCC: 1233 // 1234 // _SOFT_FLOAT_ 1235 // __RECIP_PRECISION__ 1236 // __APPLE_ALTIVEC__ 1237 // __RECIP__ 1238 // __RECIPF__ 1239 // __RSQRTE__ 1240 // __RSQRTEF__ 1241 // _SOFT_DOUBLE_ 1242 // __NO_LWSYNC__ 1243 // __HAVE_BSWAP__ 1244 // __LONGDOUBLE128 1245 // __CMODEL_MEDIUM__ 1246 // __CMODEL_LARGE__ 1247 // _CALL_SYSV 1248 // _CALL_DARWIN 1249 // __NO_FPRS__ 1250 } 1251 1252 // Handle explicit options being passed to the compiler here: if we've 1253 // explicitly turned off vsx and turned on power8-vector or direct-move then 1254 // go ahead and error since the customer has expressed a somewhat incompatible 1255 // set of options. 1256 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1257 const std::vector<std::string> &FeaturesVec) { 1258 1259 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1260 FeaturesVec.end()) { 1261 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1262 FeaturesVec.end()) { 1263 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1264 << "-mno-vsx"; 1265 return false; 1266 } 1267 1268 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1269 FeaturesVec.end()) { 1270 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1271 << "-mno-vsx"; 1272 return false; 1273 } 1274 } 1275 1276 return true; 1277 } 1278 1279 bool PPCTargetInfo::initFeatureMap( 1280 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1281 const std::vector<std::string> &FeaturesVec) const { 1282 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1283 .Case("7400", true) 1284 .Case("g4", true) 1285 .Case("7450", true) 1286 .Case("g4+", true) 1287 .Case("970", true) 1288 .Case("g5", true) 1289 .Case("pwr6", true) 1290 .Case("pwr7", true) 1291 .Case("pwr8", true) 1292 .Case("ppc64", true) 1293 .Case("ppc64le", true) 1294 .Default(false); 1295 1296 Features["qpx"] = (CPU == "a2q"); 1297 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1298 .Case("ppc64le", true) 1299 .Case("pwr8", true) 1300 .Default(false); 1301 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1302 .Case("ppc64le", true) 1303 .Case("pwr8", true) 1304 .Default(false); 1305 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1306 .Case("ppc64le", true) 1307 .Case("pwr8", true) 1308 .Case("pwr7", true) 1309 .Default(false); 1310 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1311 .Case("ppc64le", true) 1312 .Case("pwr8", true) 1313 .Case("pwr7", true) 1314 .Default(false); 1315 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1316 .Case("ppc64le", true) 1317 .Case("pwr8", true) 1318 .Default(false); 1319 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1320 .Case("ppc64le", true) 1321 .Case("pwr8", true) 1322 .Case("pwr7", true) 1323 .Default(false); 1324 1325 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1326 return false; 1327 1328 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1329 } 1330 1331 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1332 return llvm::StringSwitch<bool>(Feature) 1333 .Case("powerpc", true) 1334 .Case("vsx", HasVSX) 1335 .Case("power8-vector", HasP8Vector) 1336 .Case("crypto", HasP8Crypto) 1337 .Case("direct-move", HasDirectMove) 1338 .Case("qpx", HasQPX) 1339 .Case("htm", HasHTM) 1340 .Case("bpermd", HasBPERMD) 1341 .Case("extdiv", HasExtDiv) 1342 .Default(false); 1343 } 1344 1345 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1346 StringRef Name, bool Enabled) const { 1347 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1348 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1349 // incompatible options. 1350 if (Enabled) { 1351 if (Name == "vsx") { 1352 Features[Name] = true; 1353 } else if (Name == "direct-move") { 1354 Features[Name] = Features["vsx"] = true; 1355 } else if (Name == "power8-vector") { 1356 Features[Name] = Features["vsx"] = true; 1357 } else { 1358 Features[Name] = true; 1359 } 1360 } else { 1361 if (Name == "vsx") { 1362 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1363 false; 1364 } else { 1365 Features[Name] = false; 1366 } 1367 } 1368 } 1369 1370 const char * const PPCTargetInfo::GCCRegNames[] = { 1371 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1372 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1373 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1374 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1375 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1376 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1377 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1378 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1379 "mq", "lr", "ctr", "ap", 1380 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1381 "xer", 1382 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1383 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1384 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1385 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1386 "vrsave", "vscr", 1387 "spe_acc", "spefscr", 1388 "sfp" 1389 }; 1390 1391 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1392 unsigned &NumNames) const { 1393 Names = GCCRegNames; 1394 NumNames = llvm::array_lengthof(GCCRegNames); 1395 } 1396 1397 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1398 // While some of these aliases do map to different registers 1399 // they still share the same register name. 1400 { { "0" }, "r0" }, 1401 { { "1"}, "r1" }, 1402 { { "2" }, "r2" }, 1403 { { "3" }, "r3" }, 1404 { { "4" }, "r4" }, 1405 { { "5" }, "r5" }, 1406 { { "6" }, "r6" }, 1407 { { "7" }, "r7" }, 1408 { { "8" }, "r8" }, 1409 { { "9" }, "r9" }, 1410 { { "10" }, "r10" }, 1411 { { "11" }, "r11" }, 1412 { { "12" }, "r12" }, 1413 { { "13" }, "r13" }, 1414 { { "14" }, "r14" }, 1415 { { "15" }, "r15" }, 1416 { { "16" }, "r16" }, 1417 { { "17" }, "r17" }, 1418 { { "18" }, "r18" }, 1419 { { "19" }, "r19" }, 1420 { { "20" }, "r20" }, 1421 { { "21" }, "r21" }, 1422 { { "22" }, "r22" }, 1423 { { "23" }, "r23" }, 1424 { { "24" }, "r24" }, 1425 { { "25" }, "r25" }, 1426 { { "26" }, "r26" }, 1427 { { "27" }, "r27" }, 1428 { { "28" }, "r28" }, 1429 { { "29" }, "r29" }, 1430 { { "30" }, "r30" }, 1431 { { "31" }, "r31" }, 1432 { { "fr0" }, "f0" }, 1433 { { "fr1" }, "f1" }, 1434 { { "fr2" }, "f2" }, 1435 { { "fr3" }, "f3" }, 1436 { { "fr4" }, "f4" }, 1437 { { "fr5" }, "f5" }, 1438 { { "fr6" }, "f6" }, 1439 { { "fr7" }, "f7" }, 1440 { { "fr8" }, "f8" }, 1441 { { "fr9" }, "f9" }, 1442 { { "fr10" }, "f10" }, 1443 { { "fr11" }, "f11" }, 1444 { { "fr12" }, "f12" }, 1445 { { "fr13" }, "f13" }, 1446 { { "fr14" }, "f14" }, 1447 { { "fr15" }, "f15" }, 1448 { { "fr16" }, "f16" }, 1449 { { "fr17" }, "f17" }, 1450 { { "fr18" }, "f18" }, 1451 { { "fr19" }, "f19" }, 1452 { { "fr20" }, "f20" }, 1453 { { "fr21" }, "f21" }, 1454 { { "fr22" }, "f22" }, 1455 { { "fr23" }, "f23" }, 1456 { { "fr24" }, "f24" }, 1457 { { "fr25" }, "f25" }, 1458 { { "fr26" }, "f26" }, 1459 { { "fr27" }, "f27" }, 1460 { { "fr28" }, "f28" }, 1461 { { "fr29" }, "f29" }, 1462 { { "fr30" }, "f30" }, 1463 { { "fr31" }, "f31" }, 1464 { { "cc" }, "cr0" }, 1465 }; 1466 1467 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1468 unsigned &NumAliases) const { 1469 Aliases = GCCRegAliases; 1470 NumAliases = llvm::array_lengthof(GCCRegAliases); 1471 } 1472 1473 class PPC32TargetInfo : public PPCTargetInfo { 1474 public: 1475 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1476 DataLayoutString = "E-m:e-p:32:32-i64:64-n32"; 1477 1478 switch (getTriple().getOS()) { 1479 case llvm::Triple::Linux: 1480 case llvm::Triple::FreeBSD: 1481 case llvm::Triple::NetBSD: 1482 SizeType = UnsignedInt; 1483 PtrDiffType = SignedInt; 1484 IntPtrType = SignedInt; 1485 break; 1486 default: 1487 break; 1488 } 1489 1490 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1491 LongDoubleWidth = LongDoubleAlign = 64; 1492 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1493 } 1494 1495 // PPC32 supports atomics up to 4 bytes. 1496 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1497 } 1498 1499 BuiltinVaListKind getBuiltinVaListKind() const override { 1500 // This is the ELF definition, and is overridden by the Darwin sub-target 1501 return TargetInfo::PowerABIBuiltinVaList; 1502 } 1503 }; 1504 1505 // Note: ABI differences may eventually require us to have a separate 1506 // TargetInfo for little endian. 1507 class PPC64TargetInfo : public PPCTargetInfo { 1508 public: 1509 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1510 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1511 IntMaxType = SignedLong; 1512 Int64Type = SignedLong; 1513 1514 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1515 DataLayoutString = "e-m:e-i64:64-n32:64"; 1516 ABI = "elfv2"; 1517 } else { 1518 DataLayoutString = "E-m:e-i64:64-n32:64"; 1519 ABI = "elfv1"; 1520 } 1521 1522 switch (getTriple().getOS()) { 1523 case llvm::Triple::FreeBSD: 1524 LongDoubleWidth = LongDoubleAlign = 64; 1525 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1526 break; 1527 case llvm::Triple::NetBSD: 1528 IntMaxType = SignedLongLong; 1529 Int64Type = SignedLongLong; 1530 break; 1531 default: 1532 break; 1533 } 1534 1535 // PPC64 supports atomics up to 8 bytes. 1536 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1537 } 1538 BuiltinVaListKind getBuiltinVaListKind() const override { 1539 return TargetInfo::CharPtrBuiltinVaList; 1540 } 1541 // PPC64 Linux-specific ABI options. 1542 bool setABI(const std::string &Name) override { 1543 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1544 ABI = Name; 1545 return true; 1546 } 1547 return false; 1548 } 1549 }; 1550 1551 class DarwinPPC32TargetInfo : 1552 public DarwinTargetInfo<PPC32TargetInfo> { 1553 public: 1554 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1555 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1556 HasAlignMac68kSupport = true; 1557 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1558 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1559 LongLongAlign = 32; 1560 SuitableAlign = 128; 1561 DataLayoutString = "E-m:o-p:32:32-f64:32:64-n32"; 1562 } 1563 BuiltinVaListKind getBuiltinVaListKind() const override { 1564 return TargetInfo::CharPtrBuiltinVaList; 1565 } 1566 }; 1567 1568 class DarwinPPC64TargetInfo : 1569 public DarwinTargetInfo<PPC64TargetInfo> { 1570 public: 1571 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1572 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1573 HasAlignMac68kSupport = true; 1574 SuitableAlign = 128; 1575 DataLayoutString = "E-m:o-i64:64-n32:64"; 1576 } 1577 }; 1578 1579 static const unsigned NVPTXAddrSpaceMap[] = { 1580 1, // opencl_global 1581 3, // opencl_local 1582 4, // opencl_constant 1583 // FIXME: generic has to be added to the target 1584 0, // opencl_generic 1585 1, // cuda_device 1586 4, // cuda_constant 1587 3, // cuda_shared 1588 }; 1589 1590 class NVPTXTargetInfo : public TargetInfo { 1591 static const char *const GCCRegNames[]; 1592 static const Builtin::Info BuiltinInfo[]; 1593 1594 // The GPU profiles supported by the NVPTX backend 1595 enum GPUKind { 1596 GK_NONE, 1597 GK_SM20, 1598 GK_SM21, 1599 GK_SM30, 1600 GK_SM35, 1601 GK_SM37, 1602 } GPU; 1603 1604 public: 1605 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1606 BigEndian = false; 1607 TLSSupported = false; 1608 LongWidth = LongAlign = 64; 1609 AddrSpaceMap = &NVPTXAddrSpaceMap; 1610 UseAddrSpaceMapMangling = true; 1611 // Define available target features 1612 // These must be defined in sorted order! 1613 NoAsmVariants = true; 1614 // Set the default GPU to sm20 1615 GPU = GK_SM20; 1616 } 1617 void getTargetDefines(const LangOptions &Opts, 1618 MacroBuilder &Builder) const override { 1619 Builder.defineMacro("__PTX__"); 1620 Builder.defineMacro("__NVPTX__"); 1621 if (Opts.CUDAIsDevice) { 1622 // Set __CUDA_ARCH__ for the GPU specified. 1623 std::string CUDAArchCode; 1624 switch (GPU) { 1625 case GK_SM20: 1626 CUDAArchCode = "200"; 1627 break; 1628 case GK_SM21: 1629 CUDAArchCode = "210"; 1630 break; 1631 case GK_SM30: 1632 CUDAArchCode = "300"; 1633 break; 1634 case GK_SM35: 1635 CUDAArchCode = "350"; 1636 break; 1637 case GK_SM37: 1638 CUDAArchCode = "370"; 1639 break; 1640 default: 1641 llvm_unreachable("Unhandled target CPU"); 1642 } 1643 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1644 } 1645 } 1646 void getTargetBuiltins(const Builtin::Info *&Records, 1647 unsigned &NumRecords) const override { 1648 Records = BuiltinInfo; 1649 NumRecords = clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin; 1650 } 1651 bool hasFeature(StringRef Feature) const override { 1652 return Feature == "ptx" || Feature == "nvptx"; 1653 } 1654 1655 void getGCCRegNames(const char *const *&Names, 1656 unsigned &NumNames) const override; 1657 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1658 unsigned &NumAliases) const override { 1659 // No aliases. 1660 Aliases = nullptr; 1661 NumAliases = 0; 1662 } 1663 bool validateAsmConstraint(const char *&Name, 1664 TargetInfo::ConstraintInfo &Info) const override { 1665 switch (*Name) { 1666 default: 1667 return false; 1668 case 'c': 1669 case 'h': 1670 case 'r': 1671 case 'l': 1672 case 'f': 1673 case 'd': 1674 Info.setAllowsRegister(); 1675 return true; 1676 } 1677 } 1678 const char *getClobbers() const override { 1679 // FIXME: Is this really right? 1680 return ""; 1681 } 1682 BuiltinVaListKind getBuiltinVaListKind() const override { 1683 // FIXME: implement 1684 return TargetInfo::CharPtrBuiltinVaList; 1685 } 1686 bool setCPU(const std::string &Name) override { 1687 GPU = llvm::StringSwitch<GPUKind>(Name) 1688 .Case("sm_20", GK_SM20) 1689 .Case("sm_21", GK_SM21) 1690 .Case("sm_30", GK_SM30) 1691 .Case("sm_35", GK_SM35) 1692 .Case("sm_37", GK_SM37) 1693 .Default(GK_NONE); 1694 1695 return GPU != GK_NONE; 1696 } 1697 }; 1698 1699 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1700 #define BUILTIN(ID, TYPE, ATTRS) \ 1701 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1702 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1703 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1704 #include "clang/Basic/BuiltinsNVPTX.def" 1705 }; 1706 1707 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1708 1709 void NVPTXTargetInfo::getGCCRegNames(const char *const *&Names, 1710 unsigned &NumNames) const { 1711 Names = GCCRegNames; 1712 NumNames = llvm::array_lengthof(GCCRegNames); 1713 } 1714 1715 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1716 public: 1717 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1718 LongWidth = LongAlign = 32; 1719 PointerWidth = PointerAlign = 32; 1720 SizeType = TargetInfo::UnsignedInt; 1721 PtrDiffType = TargetInfo::SignedInt; 1722 IntPtrType = TargetInfo::SignedInt; 1723 DataLayoutString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1724 } 1725 }; 1726 1727 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1728 public: 1729 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1730 PointerWidth = PointerAlign = 64; 1731 SizeType = TargetInfo::UnsignedLong; 1732 PtrDiffType = TargetInfo::SignedLong; 1733 IntPtrType = TargetInfo::SignedLong; 1734 DataLayoutString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1735 } 1736 }; 1737 1738 static const unsigned AMDGPUAddrSpaceMap[] = { 1739 1, // opencl_global 1740 3, // opencl_local 1741 2, // opencl_constant 1742 4, // opencl_generic 1743 1, // cuda_device 1744 2, // cuda_constant 1745 3 // cuda_shared 1746 }; 1747 1748 // If you edit the description strings, make sure you update 1749 // getPointerWidthV(). 1750 1751 static const char *DataLayoutStringR600 = 1752 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1753 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1754 1755 static const char *DataLayoutStringR600DoubleOps = 1756 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1757 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1758 1759 static const char *DataLayoutStringSI = 1760 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1761 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1762 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1763 1764 class AMDGPUTargetInfo : public TargetInfo { 1765 static const Builtin::Info BuiltinInfo[]; 1766 static const char * const GCCRegNames[]; 1767 1768 /// \brief The GPU profiles supported by the AMDGPU target. 1769 enum GPUKind { 1770 GK_NONE, 1771 GK_R600, 1772 GK_R600_DOUBLE_OPS, 1773 GK_R700, 1774 GK_R700_DOUBLE_OPS, 1775 GK_EVERGREEN, 1776 GK_EVERGREEN_DOUBLE_OPS, 1777 GK_NORTHERN_ISLANDS, 1778 GK_CAYMAN, 1779 GK_SOUTHERN_ISLANDS, 1780 GK_SEA_ISLANDS, 1781 GK_VOLCANIC_ISLANDS 1782 } GPU; 1783 1784 bool hasFP64:1; 1785 bool hasFMAF:1; 1786 bool hasLDEXPF:1; 1787 1788 public: 1789 AMDGPUTargetInfo(const llvm::Triple &Triple) 1790 : TargetInfo(Triple) { 1791 1792 if (Triple.getArch() == llvm::Triple::amdgcn) { 1793 DataLayoutString = DataLayoutStringSI; 1794 GPU = GK_SOUTHERN_ISLANDS; 1795 hasFP64 = true; 1796 hasFMAF = true; 1797 hasLDEXPF = true; 1798 } else { 1799 DataLayoutString = DataLayoutStringR600; 1800 GPU = GK_R600; 1801 hasFP64 = false; 1802 hasFMAF = false; 1803 hasLDEXPF = false; 1804 } 1805 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1806 UseAddrSpaceMapMangling = true; 1807 } 1808 1809 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1810 if (GPU <= GK_CAYMAN) 1811 return 32; 1812 1813 switch(AddrSpace) { 1814 default: 1815 return 64; 1816 case 0: 1817 case 3: 1818 case 5: 1819 return 32; 1820 } 1821 } 1822 1823 const char * getClobbers() const override { 1824 return ""; 1825 } 1826 1827 void getGCCRegNames(const char * const *&Names, 1828 unsigned &NumNames) const override; 1829 1830 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1831 unsigned &NumAliases) const override { 1832 Aliases = nullptr; 1833 NumAliases = 0; 1834 } 1835 1836 bool validateAsmConstraint(const char *&Name, 1837 TargetInfo::ConstraintInfo &info) const override { 1838 return true; 1839 } 1840 1841 void getTargetBuiltins(const Builtin::Info *&Records, 1842 unsigned &NumRecords) const override { 1843 Records = BuiltinInfo; 1844 NumRecords = clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin; 1845 } 1846 1847 void getTargetDefines(const LangOptions &Opts, 1848 MacroBuilder &Builder) const override { 1849 Builder.defineMacro("__R600__"); 1850 if (hasFMAF) 1851 Builder.defineMacro("__HAS_FMAF__"); 1852 if (hasLDEXPF) 1853 Builder.defineMacro("__HAS_LDEXPF__"); 1854 if (hasFP64 && Opts.OpenCL) 1855 Builder.defineMacro("cl_khr_fp64"); 1856 if (Opts.OpenCL) { 1857 if (GPU >= GK_NORTHERN_ISLANDS) { 1858 Builder.defineMacro("cl_khr_byte_addressable_store"); 1859 Builder.defineMacro("cl_khr_global_int32_base_atomics"); 1860 Builder.defineMacro("cl_khr_global_int32_extended_atomics"); 1861 Builder.defineMacro("cl_khr_local_int32_base_atomics"); 1862 Builder.defineMacro("cl_khr_local_int32_extended_atomics"); 1863 } 1864 } 1865 } 1866 1867 BuiltinVaListKind getBuiltinVaListKind() const override { 1868 return TargetInfo::CharPtrBuiltinVaList; 1869 } 1870 1871 bool setCPU(const std::string &Name) override { 1872 GPU = llvm::StringSwitch<GPUKind>(Name) 1873 .Case("r600" , GK_R600) 1874 .Case("rv610", GK_R600) 1875 .Case("rv620", GK_R600) 1876 .Case("rv630", GK_R600) 1877 .Case("rv635", GK_R600) 1878 .Case("rs780", GK_R600) 1879 .Case("rs880", GK_R600) 1880 .Case("rv670", GK_R600_DOUBLE_OPS) 1881 .Case("rv710", GK_R700) 1882 .Case("rv730", GK_R700) 1883 .Case("rv740", GK_R700_DOUBLE_OPS) 1884 .Case("rv770", GK_R700_DOUBLE_OPS) 1885 .Case("palm", GK_EVERGREEN) 1886 .Case("cedar", GK_EVERGREEN) 1887 .Case("sumo", GK_EVERGREEN) 1888 .Case("sumo2", GK_EVERGREEN) 1889 .Case("redwood", GK_EVERGREEN) 1890 .Case("juniper", GK_EVERGREEN) 1891 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1892 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1893 .Case("barts", GK_NORTHERN_ISLANDS) 1894 .Case("turks", GK_NORTHERN_ISLANDS) 1895 .Case("caicos", GK_NORTHERN_ISLANDS) 1896 .Case("cayman", GK_CAYMAN) 1897 .Case("aruba", GK_CAYMAN) 1898 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1899 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1900 .Case("verde", GK_SOUTHERN_ISLANDS) 1901 .Case("oland", GK_SOUTHERN_ISLANDS) 1902 .Case("hainan", GK_SOUTHERN_ISLANDS) 1903 .Case("bonaire", GK_SEA_ISLANDS) 1904 .Case("kabini", GK_SEA_ISLANDS) 1905 .Case("kaveri", GK_SEA_ISLANDS) 1906 .Case("hawaii", GK_SEA_ISLANDS) 1907 .Case("mullins", GK_SEA_ISLANDS) 1908 .Case("tonga", GK_VOLCANIC_ISLANDS) 1909 .Case("iceland", GK_VOLCANIC_ISLANDS) 1910 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1911 .Default(GK_NONE); 1912 1913 if (GPU == GK_NONE) { 1914 return false; 1915 } 1916 1917 // Set the correct data layout 1918 switch (GPU) { 1919 case GK_NONE: 1920 case GK_R600: 1921 case GK_R700: 1922 case GK_EVERGREEN: 1923 case GK_NORTHERN_ISLANDS: 1924 DataLayoutString = DataLayoutStringR600; 1925 hasFP64 = false; 1926 hasFMAF = false; 1927 hasLDEXPF = false; 1928 break; 1929 case GK_R600_DOUBLE_OPS: 1930 case GK_R700_DOUBLE_OPS: 1931 case GK_EVERGREEN_DOUBLE_OPS: 1932 case GK_CAYMAN: 1933 DataLayoutString = DataLayoutStringR600DoubleOps; 1934 hasFP64 = true; 1935 hasFMAF = true; 1936 hasLDEXPF = false; 1937 break; 1938 case GK_SOUTHERN_ISLANDS: 1939 case GK_SEA_ISLANDS: 1940 case GK_VOLCANIC_ISLANDS: 1941 DataLayoutString = DataLayoutStringSI; 1942 hasFP64 = true; 1943 hasFMAF = true; 1944 hasLDEXPF = true; 1945 break; 1946 } 1947 1948 return true; 1949 } 1950 }; 1951 1952 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1953 #define BUILTIN(ID, TYPE, ATTRS) \ 1954 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1955 #include "clang/Basic/BuiltinsAMDGPU.def" 1956 }; 1957 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1958 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1959 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1960 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1961 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1962 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1963 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1964 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1965 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1966 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1967 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1968 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1969 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1970 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1971 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1972 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1973 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1974 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1975 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1976 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1977 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 1978 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 1979 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 1980 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 1981 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 1982 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 1983 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 1984 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 1985 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 1986 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 1987 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 1988 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 1989 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 1990 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 1991 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 1992 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 1993 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 1994 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 1995 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 1996 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 1997 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 1998 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 1999 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2000 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2001 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2002 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2003 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2004 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2005 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127" 2006 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi", 2007 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi" 2008 }; 2009 2010 void AMDGPUTargetInfo::getGCCRegNames(const char * const *&Names, 2011 unsigned &NumNames) const { 2012 Names = GCCRegNames; 2013 NumNames = llvm::array_lengthof(GCCRegNames); 2014 } 2015 2016 // Namespace for x86 abstract base class 2017 const Builtin::Info BuiltinInfo[] = { 2018 #define BUILTIN(ID, TYPE, ATTRS) \ 2019 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2020 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2021 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2022 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2023 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2024 #include "clang/Basic/BuiltinsX86.def" 2025 }; 2026 2027 static const char* const GCCRegNames[] = { 2028 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2029 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2030 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2031 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2032 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2033 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2034 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2035 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2036 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2037 }; 2038 2039 const TargetInfo::AddlRegName AddlRegNames[] = { 2040 { { "al", "ah", "eax", "rax" }, 0 }, 2041 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2042 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2043 { { "dl", "dh", "edx", "rdx" }, 1 }, 2044 { { "esi", "rsi" }, 4 }, 2045 { { "edi", "rdi" }, 5 }, 2046 { { "esp", "rsp" }, 7 }, 2047 { { "ebp", "rbp" }, 6 }, 2048 { { "r8d", "r8w", "r8b" }, 38 }, 2049 { { "r9d", "r9w", "r9b" }, 39 }, 2050 { { "r10d", "r10w", "r10b" }, 40 }, 2051 { { "r11d", "r11w", "r11b" }, 41 }, 2052 { { "r12d", "r12w", "r12b" }, 42 }, 2053 { { "r13d", "r13w", "r13b" }, 43 }, 2054 { { "r14d", "r14w", "r14b" }, 44 }, 2055 { { "r15d", "r15w", "r15b" }, 45 }, 2056 }; 2057 2058 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2059 // most of the implementation can be shared. 2060 class X86TargetInfo : public TargetInfo { 2061 enum X86SSEEnum { 2062 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2063 } SSELevel; 2064 enum MMX3DNowEnum { 2065 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2066 } MMX3DNowLevel; 2067 enum XOPEnum { 2068 NoXOP, 2069 SSE4A, 2070 FMA4, 2071 XOP 2072 } XOPLevel; 2073 2074 bool HasAES; 2075 bool HasPCLMUL; 2076 bool HasLZCNT; 2077 bool HasRDRND; 2078 bool HasFSGSBASE; 2079 bool HasBMI; 2080 bool HasBMI2; 2081 bool HasPOPCNT; 2082 bool HasRTM; 2083 bool HasPRFCHW; 2084 bool HasRDSEED; 2085 bool HasADX; 2086 bool HasTBM; 2087 bool HasFMA; 2088 bool HasF16C; 2089 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW, 2090 HasAVX512VL; 2091 bool HasSHA; 2092 bool HasCX16; 2093 2094 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2095 /// 2096 /// Each enumeration represents a particular CPU supported by Clang. These 2097 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2098 enum CPUKind { 2099 CK_Generic, 2100 2101 /// \name i386 2102 /// i386-generation processors. 2103 //@{ 2104 CK_i386, 2105 //@} 2106 2107 /// \name i486 2108 /// i486-generation processors. 2109 //@{ 2110 CK_i486, 2111 CK_WinChipC6, 2112 CK_WinChip2, 2113 CK_C3, 2114 //@} 2115 2116 /// \name i586 2117 /// i586-generation processors, P5 microarchitecture based. 2118 //@{ 2119 CK_i586, 2120 CK_Pentium, 2121 CK_PentiumMMX, 2122 //@} 2123 2124 /// \name i686 2125 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2126 //@{ 2127 CK_i686, 2128 CK_PentiumPro, 2129 CK_Pentium2, 2130 CK_Pentium3, 2131 CK_Pentium3M, 2132 CK_PentiumM, 2133 CK_C3_2, 2134 2135 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2136 /// Clang however has some logic to suport this. 2137 // FIXME: Warn, deprecate, and potentially remove this. 2138 CK_Yonah, 2139 //@} 2140 2141 /// \name Netburst 2142 /// Netburst microarchitecture based processors. 2143 //@{ 2144 CK_Pentium4, 2145 CK_Pentium4M, 2146 CK_Prescott, 2147 CK_Nocona, 2148 //@} 2149 2150 /// \name Core 2151 /// Core microarchitecture based processors. 2152 //@{ 2153 CK_Core2, 2154 2155 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2156 /// codename which GCC no longer accepts as an option to -march, but Clang 2157 /// has some logic for recognizing it. 2158 // FIXME: Warn, deprecate, and potentially remove this. 2159 CK_Penryn, 2160 //@} 2161 2162 /// \name Atom 2163 /// Atom processors 2164 //@{ 2165 CK_Bonnell, 2166 CK_Silvermont, 2167 //@} 2168 2169 /// \name Nehalem 2170 /// Nehalem microarchitecture based processors. 2171 CK_Nehalem, 2172 2173 /// \name Westmere 2174 /// Westmere microarchitecture based processors. 2175 CK_Westmere, 2176 2177 /// \name Sandy Bridge 2178 /// Sandy Bridge microarchitecture based processors. 2179 CK_SandyBridge, 2180 2181 /// \name Ivy Bridge 2182 /// Ivy Bridge microarchitecture based processors. 2183 CK_IvyBridge, 2184 2185 /// \name Haswell 2186 /// Haswell microarchitecture based processors. 2187 CK_Haswell, 2188 2189 /// \name Broadwell 2190 /// Broadwell microarchitecture based processors. 2191 CK_Broadwell, 2192 2193 /// \name Skylake 2194 /// Skylake microarchitecture based processors. 2195 CK_Skylake, 2196 2197 /// \name Knights Landing 2198 /// Knights Landing processor. 2199 CK_KNL, 2200 2201 /// \name K6 2202 /// K6 architecture processors. 2203 //@{ 2204 CK_K6, 2205 CK_K6_2, 2206 CK_K6_3, 2207 //@} 2208 2209 /// \name K7 2210 /// K7 architecture processors. 2211 //@{ 2212 CK_Athlon, 2213 CK_AthlonThunderbird, 2214 CK_Athlon4, 2215 CK_AthlonXP, 2216 CK_AthlonMP, 2217 //@} 2218 2219 /// \name K8 2220 /// K8 architecture processors. 2221 //@{ 2222 CK_Athlon64, 2223 CK_Athlon64SSE3, 2224 CK_AthlonFX, 2225 CK_K8, 2226 CK_K8SSE3, 2227 CK_Opteron, 2228 CK_OpteronSSE3, 2229 CK_AMDFAM10, 2230 //@} 2231 2232 /// \name Bobcat 2233 /// Bobcat architecture processors. 2234 //@{ 2235 CK_BTVER1, 2236 CK_BTVER2, 2237 //@} 2238 2239 /// \name Bulldozer 2240 /// Bulldozer architecture processors. 2241 //@{ 2242 CK_BDVER1, 2243 CK_BDVER2, 2244 CK_BDVER3, 2245 CK_BDVER4, 2246 //@} 2247 2248 /// This specification is deprecated and will be removed in the future. 2249 /// Users should prefer \see CK_K8. 2250 // FIXME: Warn on this when the CPU is set to it. 2251 //@{ 2252 CK_x86_64, 2253 //@} 2254 2255 /// \name Geode 2256 /// Geode processors. 2257 //@{ 2258 CK_Geode 2259 //@} 2260 } CPU; 2261 2262 CPUKind getCPUKind(StringRef CPU) const { 2263 return llvm::StringSwitch<CPUKind>(CPU) 2264 .Case("i386", CK_i386) 2265 .Case("i486", CK_i486) 2266 .Case("winchip-c6", CK_WinChipC6) 2267 .Case("winchip2", CK_WinChip2) 2268 .Case("c3", CK_C3) 2269 .Case("i586", CK_i586) 2270 .Case("pentium", CK_Pentium) 2271 .Case("pentium-mmx", CK_PentiumMMX) 2272 .Case("i686", CK_i686) 2273 .Case("pentiumpro", CK_PentiumPro) 2274 .Case("pentium2", CK_Pentium2) 2275 .Case("pentium3", CK_Pentium3) 2276 .Case("pentium3m", CK_Pentium3M) 2277 .Case("pentium-m", CK_PentiumM) 2278 .Case("c3-2", CK_C3_2) 2279 .Case("yonah", CK_Yonah) 2280 .Case("pentium4", CK_Pentium4) 2281 .Case("pentium4m", CK_Pentium4M) 2282 .Case("prescott", CK_Prescott) 2283 .Case("nocona", CK_Nocona) 2284 .Case("core2", CK_Core2) 2285 .Case("penryn", CK_Penryn) 2286 .Case("bonnell", CK_Bonnell) 2287 .Case("atom", CK_Bonnell) // Legacy name. 2288 .Case("silvermont", CK_Silvermont) 2289 .Case("slm", CK_Silvermont) // Legacy name. 2290 .Case("nehalem", CK_Nehalem) 2291 .Case("corei7", CK_Nehalem) // Legacy name. 2292 .Case("westmere", CK_Westmere) 2293 .Case("sandybridge", CK_SandyBridge) 2294 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2295 .Case("ivybridge", CK_IvyBridge) 2296 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2297 .Case("haswell", CK_Haswell) 2298 .Case("core-avx2", CK_Haswell) // Legacy name. 2299 .Case("broadwell", CK_Broadwell) 2300 .Case("skylake", CK_Skylake) 2301 .Case("skx", CK_Skylake) // Legacy name. 2302 .Case("knl", CK_KNL) 2303 .Case("k6", CK_K6) 2304 .Case("k6-2", CK_K6_2) 2305 .Case("k6-3", CK_K6_3) 2306 .Case("athlon", CK_Athlon) 2307 .Case("athlon-tbird", CK_AthlonThunderbird) 2308 .Case("athlon-4", CK_Athlon4) 2309 .Case("athlon-xp", CK_AthlonXP) 2310 .Case("athlon-mp", CK_AthlonMP) 2311 .Case("athlon64", CK_Athlon64) 2312 .Case("athlon64-sse3", CK_Athlon64SSE3) 2313 .Case("athlon-fx", CK_AthlonFX) 2314 .Case("k8", CK_K8) 2315 .Case("k8-sse3", CK_K8SSE3) 2316 .Case("opteron", CK_Opteron) 2317 .Case("opteron-sse3", CK_OpteronSSE3) 2318 .Case("barcelona", CK_AMDFAM10) 2319 .Case("amdfam10", CK_AMDFAM10) 2320 .Case("btver1", CK_BTVER1) 2321 .Case("btver2", CK_BTVER2) 2322 .Case("bdver1", CK_BDVER1) 2323 .Case("bdver2", CK_BDVER2) 2324 .Case("bdver3", CK_BDVER3) 2325 .Case("bdver4", CK_BDVER4) 2326 .Case("x86-64", CK_x86_64) 2327 .Case("geode", CK_Geode) 2328 .Default(CK_Generic); 2329 } 2330 2331 enum FPMathKind { 2332 FP_Default, 2333 FP_SSE, 2334 FP_387 2335 } FPMath; 2336 2337 public: 2338 X86TargetInfo(const llvm::Triple &Triple) 2339 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 2340 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 2341 HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false), 2342 HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false), 2343 HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false), 2344 HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false), 2345 HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false), 2346 HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) { 2347 BigEndian = false; 2348 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2349 } 2350 unsigned getFloatEvalMethod() const override { 2351 // X87 evaluates with 80 bits "long double" precision. 2352 return SSELevel == NoSSE ? 2 : 0; 2353 } 2354 void getTargetBuiltins(const Builtin::Info *&Records, 2355 unsigned &NumRecords) const override { 2356 Records = BuiltinInfo; 2357 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 2358 } 2359 void getGCCRegNames(const char * const *&Names, 2360 unsigned &NumNames) const override { 2361 Names = GCCRegNames; 2362 NumNames = llvm::array_lengthof(GCCRegNames); 2363 } 2364 void getGCCRegAliases(const GCCRegAlias *&Aliases, 2365 unsigned &NumAliases) const override { 2366 Aliases = nullptr; 2367 NumAliases = 0; 2368 } 2369 void getGCCAddlRegNames(const AddlRegName *&Names, 2370 unsigned &NumNames) const override { 2371 Names = AddlRegNames; 2372 NumNames = llvm::array_lengthof(AddlRegNames); 2373 } 2374 bool validateCpuSupports(StringRef Name) const override; 2375 bool validateAsmConstraint(const char *&Name, 2376 TargetInfo::ConstraintInfo &info) const override; 2377 2378 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2379 2380 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2381 2382 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2383 2384 std::string convertConstraint(const char *&Constraint) const override; 2385 const char *getClobbers() const override { 2386 return "~{dirflag},~{fpsr},~{flags}"; 2387 } 2388 void getTargetDefines(const LangOptions &Opts, 2389 MacroBuilder &Builder) const override; 2390 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2391 bool Enabled); 2392 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2393 bool Enabled); 2394 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2395 bool Enabled); 2396 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2397 StringRef Name, bool Enabled) const override { 2398 setFeatureEnabledImpl(Features, Name, Enabled); 2399 } 2400 // This exists purely to cut down on the number of virtual calls in 2401 // initFeatureMap which calls this repeatedly. 2402 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2403 StringRef Name, bool Enabled); 2404 bool 2405 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2406 StringRef CPU, 2407 const std::vector<std::string> &FeaturesVec) const override; 2408 bool hasFeature(StringRef Feature) const override; 2409 bool handleTargetFeatures(std::vector<std::string> &Features, 2410 DiagnosticsEngine &Diags) override; 2411 StringRef getABI() const override { 2412 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2413 return "avx512"; 2414 else if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2415 return "avx"; 2416 else if (getTriple().getArch() == llvm::Triple::x86 && 2417 MMX3DNowLevel == NoMMX3DNow) 2418 return "no-mmx"; 2419 return ""; 2420 } 2421 bool setCPU(const std::string &Name) override { 2422 CPU = getCPUKind(Name); 2423 2424 // Perform any per-CPU checks necessary to determine if this CPU is 2425 // acceptable. 2426 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2427 // invalid without explaining *why*. 2428 switch (CPU) { 2429 case CK_Generic: 2430 // No processor selected! 2431 return false; 2432 2433 case CK_i386: 2434 case CK_i486: 2435 case CK_WinChipC6: 2436 case CK_WinChip2: 2437 case CK_C3: 2438 case CK_i586: 2439 case CK_Pentium: 2440 case CK_PentiumMMX: 2441 case CK_i686: 2442 case CK_PentiumPro: 2443 case CK_Pentium2: 2444 case CK_Pentium3: 2445 case CK_Pentium3M: 2446 case CK_PentiumM: 2447 case CK_Yonah: 2448 case CK_C3_2: 2449 case CK_Pentium4: 2450 case CK_Pentium4M: 2451 case CK_Prescott: 2452 case CK_K6: 2453 case CK_K6_2: 2454 case CK_K6_3: 2455 case CK_Athlon: 2456 case CK_AthlonThunderbird: 2457 case CK_Athlon4: 2458 case CK_AthlonXP: 2459 case CK_AthlonMP: 2460 case CK_Geode: 2461 // Only accept certain architectures when compiling in 32-bit mode. 2462 if (getTriple().getArch() != llvm::Triple::x86) 2463 return false; 2464 2465 // Fallthrough 2466 case CK_Nocona: 2467 case CK_Core2: 2468 case CK_Penryn: 2469 case CK_Bonnell: 2470 case CK_Silvermont: 2471 case CK_Nehalem: 2472 case CK_Westmere: 2473 case CK_SandyBridge: 2474 case CK_IvyBridge: 2475 case CK_Haswell: 2476 case CK_Broadwell: 2477 case CK_Skylake: 2478 case CK_KNL: 2479 case CK_Athlon64: 2480 case CK_Athlon64SSE3: 2481 case CK_AthlonFX: 2482 case CK_K8: 2483 case CK_K8SSE3: 2484 case CK_Opteron: 2485 case CK_OpteronSSE3: 2486 case CK_AMDFAM10: 2487 case CK_BTVER1: 2488 case CK_BTVER2: 2489 case CK_BDVER1: 2490 case CK_BDVER2: 2491 case CK_BDVER3: 2492 case CK_BDVER4: 2493 case CK_x86_64: 2494 return true; 2495 } 2496 llvm_unreachable("Unhandled CPU kind"); 2497 } 2498 2499 bool setFPMath(StringRef Name) override; 2500 2501 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2502 // We accept all non-ARM calling conventions 2503 return (CC == CC_X86ThisCall || 2504 CC == CC_X86FastCall || 2505 CC == CC_X86StdCall || 2506 CC == CC_X86VectorCall || 2507 CC == CC_C || 2508 CC == CC_X86Pascal || 2509 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2510 } 2511 2512 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2513 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2514 } 2515 2516 bool hasSjLjLowering() const override { 2517 return true; 2518 } 2519 }; 2520 2521 bool X86TargetInfo::setFPMath(StringRef Name) { 2522 if (Name == "387") { 2523 FPMath = FP_387; 2524 return true; 2525 } 2526 if (Name == "sse") { 2527 FPMath = FP_SSE; 2528 return true; 2529 } 2530 return false; 2531 } 2532 2533 bool X86TargetInfo::initFeatureMap( 2534 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2535 const std::vector<std::string> &FeaturesVec) const { 2536 // FIXME: This *really* should not be here. 2537 // X86_64 always has SSE2. 2538 if (getTriple().getArch() == llvm::Triple::x86_64) 2539 setFeatureEnabledImpl(Features, "sse2", true); 2540 2541 switch (getCPUKind(CPU)) { 2542 case CK_Generic: 2543 case CK_i386: 2544 case CK_i486: 2545 case CK_i586: 2546 case CK_Pentium: 2547 case CK_i686: 2548 case CK_PentiumPro: 2549 break; 2550 case CK_PentiumMMX: 2551 case CK_Pentium2: 2552 case CK_K6: 2553 case CK_WinChipC6: 2554 setFeatureEnabledImpl(Features, "mmx", true); 2555 break; 2556 case CK_Pentium3: 2557 case CK_Pentium3M: 2558 case CK_C3_2: 2559 setFeatureEnabledImpl(Features, "sse", true); 2560 break; 2561 case CK_PentiumM: 2562 case CK_Pentium4: 2563 case CK_Pentium4M: 2564 case CK_x86_64: 2565 setFeatureEnabledImpl(Features, "sse2", true); 2566 break; 2567 case CK_Yonah: 2568 case CK_Prescott: 2569 case CK_Nocona: 2570 setFeatureEnabledImpl(Features, "sse3", true); 2571 setFeatureEnabledImpl(Features, "cx16", true); 2572 break; 2573 case CK_Core2: 2574 case CK_Bonnell: 2575 setFeatureEnabledImpl(Features, "ssse3", true); 2576 setFeatureEnabledImpl(Features, "cx16", true); 2577 break; 2578 case CK_Penryn: 2579 setFeatureEnabledImpl(Features, "sse4.1", true); 2580 setFeatureEnabledImpl(Features, "cx16", true); 2581 break; 2582 case CK_Skylake: 2583 setFeatureEnabledImpl(Features, "avx512f", true); 2584 setFeatureEnabledImpl(Features, "avx512cd", true); 2585 setFeatureEnabledImpl(Features, "avx512dq", true); 2586 setFeatureEnabledImpl(Features, "avx512bw", true); 2587 setFeatureEnabledImpl(Features, "avx512vl", true); 2588 // FALLTHROUGH 2589 case CK_Broadwell: 2590 setFeatureEnabledImpl(Features, "rdseed", true); 2591 setFeatureEnabledImpl(Features, "adx", true); 2592 // FALLTHROUGH 2593 case CK_Haswell: 2594 setFeatureEnabledImpl(Features, "avx2", true); 2595 setFeatureEnabledImpl(Features, "lzcnt", true); 2596 setFeatureEnabledImpl(Features, "bmi", true); 2597 setFeatureEnabledImpl(Features, "bmi2", true); 2598 setFeatureEnabledImpl(Features, "rtm", true); 2599 setFeatureEnabledImpl(Features, "fma", true); 2600 // FALLTHROUGH 2601 case CK_IvyBridge: 2602 setFeatureEnabledImpl(Features, "rdrnd", true); 2603 setFeatureEnabledImpl(Features, "f16c", true); 2604 setFeatureEnabledImpl(Features, "fsgsbase", true); 2605 // FALLTHROUGH 2606 case CK_SandyBridge: 2607 setFeatureEnabledImpl(Features, "avx", true); 2608 // FALLTHROUGH 2609 case CK_Westmere: 2610 case CK_Silvermont: 2611 setFeatureEnabledImpl(Features, "aes", true); 2612 setFeatureEnabledImpl(Features, "pclmul", true); 2613 // FALLTHROUGH 2614 case CK_Nehalem: 2615 setFeatureEnabledImpl(Features, "sse4.2", true); 2616 setFeatureEnabledImpl(Features, "cx16", true); 2617 break; 2618 case CK_KNL: 2619 setFeatureEnabledImpl(Features, "avx512f", true); 2620 setFeatureEnabledImpl(Features, "avx512cd", true); 2621 setFeatureEnabledImpl(Features, "avx512er", true); 2622 setFeatureEnabledImpl(Features, "avx512pf", true); 2623 setFeatureEnabledImpl(Features, "rdseed", true); 2624 setFeatureEnabledImpl(Features, "adx", true); 2625 setFeatureEnabledImpl(Features, "lzcnt", true); 2626 setFeatureEnabledImpl(Features, "bmi", true); 2627 setFeatureEnabledImpl(Features, "bmi2", true); 2628 setFeatureEnabledImpl(Features, "rtm", true); 2629 setFeatureEnabledImpl(Features, "fma", true); 2630 setFeatureEnabledImpl(Features, "rdrnd", true); 2631 setFeatureEnabledImpl(Features, "f16c", true); 2632 setFeatureEnabledImpl(Features, "fsgsbase", true); 2633 setFeatureEnabledImpl(Features, "aes", true); 2634 setFeatureEnabledImpl(Features, "pclmul", true); 2635 setFeatureEnabledImpl(Features, "cx16", true); 2636 break; 2637 case CK_K6_2: 2638 case CK_K6_3: 2639 case CK_WinChip2: 2640 case CK_C3: 2641 setFeatureEnabledImpl(Features, "3dnow", true); 2642 break; 2643 case CK_Athlon: 2644 case CK_AthlonThunderbird: 2645 case CK_Geode: 2646 setFeatureEnabledImpl(Features, "3dnowa", true); 2647 break; 2648 case CK_Athlon4: 2649 case CK_AthlonXP: 2650 case CK_AthlonMP: 2651 setFeatureEnabledImpl(Features, "sse", true); 2652 setFeatureEnabledImpl(Features, "3dnowa", true); 2653 break; 2654 case CK_K8: 2655 case CK_Opteron: 2656 case CK_Athlon64: 2657 case CK_AthlonFX: 2658 setFeatureEnabledImpl(Features, "sse2", true); 2659 setFeatureEnabledImpl(Features, "3dnowa", true); 2660 break; 2661 case CK_AMDFAM10: 2662 setFeatureEnabledImpl(Features, "sse4a", true); 2663 setFeatureEnabledImpl(Features, "lzcnt", true); 2664 setFeatureEnabledImpl(Features, "popcnt", true); 2665 // FALLTHROUGH 2666 case CK_K8SSE3: 2667 case CK_OpteronSSE3: 2668 case CK_Athlon64SSE3: 2669 setFeatureEnabledImpl(Features, "sse3", true); 2670 setFeatureEnabledImpl(Features, "3dnowa", true); 2671 break; 2672 case CK_BTVER2: 2673 setFeatureEnabledImpl(Features, "avx", true); 2674 setFeatureEnabledImpl(Features, "aes", true); 2675 setFeatureEnabledImpl(Features, "pclmul", true); 2676 setFeatureEnabledImpl(Features, "bmi", true); 2677 setFeatureEnabledImpl(Features, "f16c", true); 2678 // FALLTHROUGH 2679 case CK_BTVER1: 2680 setFeatureEnabledImpl(Features, "ssse3", true); 2681 setFeatureEnabledImpl(Features, "sse4a", true); 2682 setFeatureEnabledImpl(Features, "lzcnt", true); 2683 setFeatureEnabledImpl(Features, "popcnt", true); 2684 setFeatureEnabledImpl(Features, "prfchw", true); 2685 setFeatureEnabledImpl(Features, "cx16", true); 2686 break; 2687 case CK_BDVER4: 2688 setFeatureEnabledImpl(Features, "avx2", true); 2689 setFeatureEnabledImpl(Features, "bmi2", true); 2690 // FALLTHROUGH 2691 case CK_BDVER3: 2692 setFeatureEnabledImpl(Features, "fsgsbase", true); 2693 // FALLTHROUGH 2694 case CK_BDVER2: 2695 setFeatureEnabledImpl(Features, "bmi", true); 2696 setFeatureEnabledImpl(Features, "fma", true); 2697 setFeatureEnabledImpl(Features, "f16c", true); 2698 setFeatureEnabledImpl(Features, "tbm", true); 2699 // FALLTHROUGH 2700 case CK_BDVER1: 2701 // xop implies avx, sse4a and fma4. 2702 setFeatureEnabledImpl(Features, "xop", true); 2703 setFeatureEnabledImpl(Features, "lzcnt", true); 2704 setFeatureEnabledImpl(Features, "aes", true); 2705 setFeatureEnabledImpl(Features, "pclmul", true); 2706 setFeatureEnabledImpl(Features, "prfchw", true); 2707 setFeatureEnabledImpl(Features, "cx16", true); 2708 break; 2709 } 2710 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 2711 return false; 2712 2713 // Can't do this earlier because we need to be able to explicitly enable 2714 // or disable these features and the things that they depend upon. 2715 2716 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2717 auto I = Features.find("sse4.2"); 2718 if (I != Features.end() && I->getValue() == true && 2719 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 2720 FeaturesVec.end()) 2721 Features["popcnt"] = true; 2722 2723 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2724 I = Features.find("3dnow"); 2725 if (I != Features.end() && I->getValue() == true && 2726 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 2727 FeaturesVec.end()) 2728 Features["prfchw"] = true; 2729 2730 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2731 // then enable MMX. 2732 I = Features.find("sse"); 2733 if (I != Features.end() && I->getValue() == true && 2734 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 2735 FeaturesVec.end()) 2736 Features["mmx"] = true; 2737 2738 return true; 2739 } 2740 2741 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2742 X86SSEEnum Level, bool Enabled) { 2743 if (Enabled) { 2744 switch (Level) { 2745 case AVX512F: 2746 Features["avx512f"] = true; 2747 case AVX2: 2748 Features["avx2"] = true; 2749 case AVX: 2750 Features["avx"] = true; 2751 case SSE42: 2752 Features["sse4.2"] = true; 2753 case SSE41: 2754 Features["sse4.1"] = true; 2755 case SSSE3: 2756 Features["ssse3"] = true; 2757 case SSE3: 2758 Features["sse3"] = true; 2759 case SSE2: 2760 Features["sse2"] = true; 2761 case SSE1: 2762 Features["sse"] = true; 2763 case NoSSE: 2764 break; 2765 } 2766 return; 2767 } 2768 2769 switch (Level) { 2770 case NoSSE: 2771 case SSE1: 2772 Features["sse"] = false; 2773 case SSE2: 2774 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2775 Features["sha"] = false; 2776 case SSE3: 2777 Features["sse3"] = false; 2778 setXOPLevel(Features, NoXOP, false); 2779 case SSSE3: 2780 Features["ssse3"] = false; 2781 case SSE41: 2782 Features["sse4.1"] = false; 2783 case SSE42: 2784 Features["sse4.2"] = false; 2785 case AVX: 2786 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2787 setXOPLevel(Features, FMA4, false); 2788 case AVX2: 2789 Features["avx2"] = false; 2790 case AVX512F: 2791 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2792 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2793 Features["avx512vl"] = false; 2794 } 2795 } 2796 2797 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2798 MMX3DNowEnum Level, bool Enabled) { 2799 if (Enabled) { 2800 switch (Level) { 2801 case AMD3DNowAthlon: 2802 Features["3dnowa"] = true; 2803 case AMD3DNow: 2804 Features["3dnow"] = true; 2805 case MMX: 2806 Features["mmx"] = true; 2807 case NoMMX3DNow: 2808 break; 2809 } 2810 return; 2811 } 2812 2813 switch (Level) { 2814 case NoMMX3DNow: 2815 case MMX: 2816 Features["mmx"] = false; 2817 case AMD3DNow: 2818 Features["3dnow"] = false; 2819 case AMD3DNowAthlon: 2820 Features["3dnowa"] = false; 2821 } 2822 } 2823 2824 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2825 bool Enabled) { 2826 if (Enabled) { 2827 switch (Level) { 2828 case XOP: 2829 Features["xop"] = true; 2830 case FMA4: 2831 Features["fma4"] = true; 2832 setSSELevel(Features, AVX, true); 2833 case SSE4A: 2834 Features["sse4a"] = true; 2835 setSSELevel(Features, SSE3, true); 2836 case NoXOP: 2837 break; 2838 } 2839 return; 2840 } 2841 2842 switch (Level) { 2843 case NoXOP: 2844 case SSE4A: 2845 Features["sse4a"] = false; 2846 case FMA4: 2847 Features["fma4"] = false; 2848 case XOP: 2849 Features["xop"] = false; 2850 } 2851 } 2852 2853 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2854 StringRef Name, bool Enabled) { 2855 // This is a bit of a hack to deal with the sse4 target feature when used 2856 // as part of the target attribute. We handle sse4 correctly everywhere 2857 // else. See below for more information on how we handle the sse4 options. 2858 if (Name != "sse4") 2859 Features[Name] = Enabled; 2860 2861 if (Name == "mmx") { 2862 setMMXLevel(Features, MMX, Enabled); 2863 } else if (Name == "sse") { 2864 setSSELevel(Features, SSE1, Enabled); 2865 } else if (Name == "sse2") { 2866 setSSELevel(Features, SSE2, Enabled); 2867 } else if (Name == "sse3") { 2868 setSSELevel(Features, SSE3, Enabled); 2869 } else if (Name == "ssse3") { 2870 setSSELevel(Features, SSSE3, Enabled); 2871 } else if (Name == "sse4.2") { 2872 setSSELevel(Features, SSE42, Enabled); 2873 } else if (Name == "sse4.1") { 2874 setSSELevel(Features, SSE41, Enabled); 2875 } else if (Name == "3dnow") { 2876 setMMXLevel(Features, AMD3DNow, Enabled); 2877 } else if (Name == "3dnowa") { 2878 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2879 } else if (Name == "aes") { 2880 if (Enabled) 2881 setSSELevel(Features, SSE2, Enabled); 2882 } else if (Name == "pclmul") { 2883 if (Enabled) 2884 setSSELevel(Features, SSE2, Enabled); 2885 } else if (Name == "avx") { 2886 setSSELevel(Features, AVX, Enabled); 2887 } else if (Name == "avx2") { 2888 setSSELevel(Features, AVX2, Enabled); 2889 } else if (Name == "avx512f") { 2890 setSSELevel(Features, AVX512F, Enabled); 2891 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2892 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2893 if (Enabled) 2894 setSSELevel(Features, AVX512F, Enabled); 2895 } else if (Name == "fma") { 2896 if (Enabled) 2897 setSSELevel(Features, AVX, Enabled); 2898 } else if (Name == "fma4") { 2899 setXOPLevel(Features, FMA4, Enabled); 2900 } else if (Name == "xop") { 2901 setXOPLevel(Features, XOP, Enabled); 2902 } else if (Name == "sse4a") { 2903 setXOPLevel(Features, SSE4A, Enabled); 2904 } else if (Name == "f16c") { 2905 if (Enabled) 2906 setSSELevel(Features, AVX, Enabled); 2907 } else if (Name == "sha") { 2908 if (Enabled) 2909 setSSELevel(Features, SSE2, Enabled); 2910 } else if (Name == "sse4") { 2911 // We can get here via the __target__ attribute since that's not controlled 2912 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 2913 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 2914 // disabled. 2915 if (Enabled) 2916 setSSELevel(Features, SSE42, Enabled); 2917 else 2918 setSSELevel(Features, SSE41, Enabled); 2919 } 2920 } 2921 2922 /// handleTargetFeatures - Perform initialization based on the user 2923 /// configured set of features. 2924 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2925 DiagnosticsEngine &Diags) { 2926 for (const auto &Feature : Features) { 2927 if (Feature[0] != '+') 2928 continue; 2929 2930 if (Feature == "+aes") { 2931 HasAES = true; 2932 } else if (Feature == "+pclmul") { 2933 HasPCLMUL = true; 2934 } else if (Feature == "+lzcnt") { 2935 HasLZCNT = true; 2936 } else if (Feature == "+rdrnd") { 2937 HasRDRND = true; 2938 } else if (Feature == "+fsgsbase") { 2939 HasFSGSBASE = true; 2940 } else if (Feature == "+bmi") { 2941 HasBMI = true; 2942 } else if (Feature == "+bmi2") { 2943 HasBMI2 = true; 2944 } else if (Feature == "+popcnt") { 2945 HasPOPCNT = true; 2946 } else if (Feature == "+rtm") { 2947 HasRTM = true; 2948 } else if (Feature == "+prfchw") { 2949 HasPRFCHW = true; 2950 } else if (Feature == "+rdseed") { 2951 HasRDSEED = true; 2952 } else if (Feature == "+adx") { 2953 HasADX = true; 2954 } else if (Feature == "+tbm") { 2955 HasTBM = true; 2956 } else if (Feature == "+fma") { 2957 HasFMA = true; 2958 } else if (Feature == "+f16c") { 2959 HasF16C = true; 2960 } else if (Feature == "+avx512cd") { 2961 HasAVX512CD = true; 2962 } else if (Feature == "+avx512er") { 2963 HasAVX512ER = true; 2964 } else if (Feature == "+avx512pf") { 2965 HasAVX512PF = true; 2966 } else if (Feature == "+avx512dq") { 2967 HasAVX512DQ = true; 2968 } else if (Feature == "+avx512bw") { 2969 HasAVX512BW = true; 2970 } else if (Feature == "+avx512vl") { 2971 HasAVX512VL = true; 2972 } else if (Feature == "+sha") { 2973 HasSHA = true; 2974 } else if (Feature == "+cx16") { 2975 HasCX16 = true; 2976 } 2977 2978 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2979 .Case("+avx512f", AVX512F) 2980 .Case("+avx2", AVX2) 2981 .Case("+avx", AVX) 2982 .Case("+sse4.2", SSE42) 2983 .Case("+sse4.1", SSE41) 2984 .Case("+ssse3", SSSE3) 2985 .Case("+sse3", SSE3) 2986 .Case("+sse2", SSE2) 2987 .Case("+sse", SSE1) 2988 .Default(NoSSE); 2989 SSELevel = std::max(SSELevel, Level); 2990 2991 MMX3DNowEnum ThreeDNowLevel = 2992 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2993 .Case("+3dnowa", AMD3DNowAthlon) 2994 .Case("+3dnow", AMD3DNow) 2995 .Case("+mmx", MMX) 2996 .Default(NoMMX3DNow); 2997 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2998 2999 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3000 .Case("+xop", XOP) 3001 .Case("+fma4", FMA4) 3002 .Case("+sse4a", SSE4A) 3003 .Default(NoXOP); 3004 XOPLevel = std::max(XOPLevel, XLevel); 3005 } 3006 3007 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3008 // matches the selected sse level. 3009 if (FPMath == FP_SSE && SSELevel < SSE1) { 3010 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 3011 return false; 3012 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 3013 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 3014 return false; 3015 } 3016 3017 SimdDefaultAlign = 3018 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3019 return true; 3020 } 3021 3022 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3023 /// definitions for this particular subtarget. 3024 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3025 MacroBuilder &Builder) const { 3026 // Target identification. 3027 if (getTriple().getArch() == llvm::Triple::x86_64) { 3028 Builder.defineMacro("__amd64__"); 3029 Builder.defineMacro("__amd64"); 3030 Builder.defineMacro("__x86_64"); 3031 Builder.defineMacro("__x86_64__"); 3032 if (getTriple().getArchName() == "x86_64h") { 3033 Builder.defineMacro("__x86_64h"); 3034 Builder.defineMacro("__x86_64h__"); 3035 } 3036 } else { 3037 DefineStd(Builder, "i386", Opts); 3038 } 3039 3040 // Subtarget options. 3041 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3042 // truly should be based on -mtune options. 3043 switch (CPU) { 3044 case CK_Generic: 3045 break; 3046 case CK_i386: 3047 // The rest are coming from the i386 define above. 3048 Builder.defineMacro("__tune_i386__"); 3049 break; 3050 case CK_i486: 3051 case CK_WinChipC6: 3052 case CK_WinChip2: 3053 case CK_C3: 3054 defineCPUMacros(Builder, "i486"); 3055 break; 3056 case CK_PentiumMMX: 3057 Builder.defineMacro("__pentium_mmx__"); 3058 Builder.defineMacro("__tune_pentium_mmx__"); 3059 // Fallthrough 3060 case CK_i586: 3061 case CK_Pentium: 3062 defineCPUMacros(Builder, "i586"); 3063 defineCPUMacros(Builder, "pentium"); 3064 break; 3065 case CK_Pentium3: 3066 case CK_Pentium3M: 3067 case CK_PentiumM: 3068 Builder.defineMacro("__tune_pentium3__"); 3069 // Fallthrough 3070 case CK_Pentium2: 3071 case CK_C3_2: 3072 Builder.defineMacro("__tune_pentium2__"); 3073 // Fallthrough 3074 case CK_PentiumPro: 3075 Builder.defineMacro("__tune_i686__"); 3076 Builder.defineMacro("__tune_pentiumpro__"); 3077 // Fallthrough 3078 case CK_i686: 3079 Builder.defineMacro("__i686"); 3080 Builder.defineMacro("__i686__"); 3081 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3082 Builder.defineMacro("__pentiumpro"); 3083 Builder.defineMacro("__pentiumpro__"); 3084 break; 3085 case CK_Pentium4: 3086 case CK_Pentium4M: 3087 defineCPUMacros(Builder, "pentium4"); 3088 break; 3089 case CK_Yonah: 3090 case CK_Prescott: 3091 case CK_Nocona: 3092 defineCPUMacros(Builder, "nocona"); 3093 break; 3094 case CK_Core2: 3095 case CK_Penryn: 3096 defineCPUMacros(Builder, "core2"); 3097 break; 3098 case CK_Bonnell: 3099 defineCPUMacros(Builder, "atom"); 3100 break; 3101 case CK_Silvermont: 3102 defineCPUMacros(Builder, "slm"); 3103 break; 3104 case CK_Nehalem: 3105 case CK_Westmere: 3106 case CK_SandyBridge: 3107 case CK_IvyBridge: 3108 case CK_Haswell: 3109 case CK_Broadwell: 3110 // FIXME: Historically, we defined this legacy name, it would be nice to 3111 // remove it at some point. We've never exposed fine-grained names for 3112 // recent primary x86 CPUs, and we should keep it that way. 3113 defineCPUMacros(Builder, "corei7"); 3114 break; 3115 case CK_Skylake: 3116 // FIXME: Historically, we defined this legacy name, it would be nice to 3117 // remove it at some point. This is the only fine-grained CPU macro in the 3118 // main intel CPU line, and it would be better to not have these and force 3119 // people to use ISA macros. 3120 defineCPUMacros(Builder, "skx"); 3121 break; 3122 case CK_KNL: 3123 defineCPUMacros(Builder, "knl"); 3124 break; 3125 case CK_K6_2: 3126 Builder.defineMacro("__k6_2__"); 3127 Builder.defineMacro("__tune_k6_2__"); 3128 // Fallthrough 3129 case CK_K6_3: 3130 if (CPU != CK_K6_2) { // In case of fallthrough 3131 // FIXME: GCC may be enabling these in cases where some other k6 3132 // architecture is specified but -m3dnow is explicitly provided. The 3133 // exact semantics need to be determined and emulated here. 3134 Builder.defineMacro("__k6_3__"); 3135 Builder.defineMacro("__tune_k6_3__"); 3136 } 3137 // Fallthrough 3138 case CK_K6: 3139 defineCPUMacros(Builder, "k6"); 3140 break; 3141 case CK_Athlon: 3142 case CK_AthlonThunderbird: 3143 case CK_Athlon4: 3144 case CK_AthlonXP: 3145 case CK_AthlonMP: 3146 defineCPUMacros(Builder, "athlon"); 3147 if (SSELevel != NoSSE) { 3148 Builder.defineMacro("__athlon_sse__"); 3149 Builder.defineMacro("__tune_athlon_sse__"); 3150 } 3151 break; 3152 case CK_K8: 3153 case CK_K8SSE3: 3154 case CK_x86_64: 3155 case CK_Opteron: 3156 case CK_OpteronSSE3: 3157 case CK_Athlon64: 3158 case CK_Athlon64SSE3: 3159 case CK_AthlonFX: 3160 defineCPUMacros(Builder, "k8"); 3161 break; 3162 case CK_AMDFAM10: 3163 defineCPUMacros(Builder, "amdfam10"); 3164 break; 3165 case CK_BTVER1: 3166 defineCPUMacros(Builder, "btver1"); 3167 break; 3168 case CK_BTVER2: 3169 defineCPUMacros(Builder, "btver2"); 3170 break; 3171 case CK_BDVER1: 3172 defineCPUMacros(Builder, "bdver1"); 3173 break; 3174 case CK_BDVER2: 3175 defineCPUMacros(Builder, "bdver2"); 3176 break; 3177 case CK_BDVER3: 3178 defineCPUMacros(Builder, "bdver3"); 3179 break; 3180 case CK_BDVER4: 3181 defineCPUMacros(Builder, "bdver4"); 3182 break; 3183 case CK_Geode: 3184 defineCPUMacros(Builder, "geode"); 3185 break; 3186 } 3187 3188 // Target properties. 3189 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3190 3191 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3192 // functions in glibc header files that use FP Stack inline asm which the 3193 // backend can't deal with (PR879). 3194 Builder.defineMacro("__NO_MATH_INLINES"); 3195 3196 if (HasAES) 3197 Builder.defineMacro("__AES__"); 3198 3199 if (HasPCLMUL) 3200 Builder.defineMacro("__PCLMUL__"); 3201 3202 if (HasLZCNT) 3203 Builder.defineMacro("__LZCNT__"); 3204 3205 if (HasRDRND) 3206 Builder.defineMacro("__RDRND__"); 3207 3208 if (HasFSGSBASE) 3209 Builder.defineMacro("__FSGSBASE__"); 3210 3211 if (HasBMI) 3212 Builder.defineMacro("__BMI__"); 3213 3214 if (HasBMI2) 3215 Builder.defineMacro("__BMI2__"); 3216 3217 if (HasPOPCNT) 3218 Builder.defineMacro("__POPCNT__"); 3219 3220 if (HasRTM) 3221 Builder.defineMacro("__RTM__"); 3222 3223 if (HasPRFCHW) 3224 Builder.defineMacro("__PRFCHW__"); 3225 3226 if (HasRDSEED) 3227 Builder.defineMacro("__RDSEED__"); 3228 3229 if (HasADX) 3230 Builder.defineMacro("__ADX__"); 3231 3232 if (HasTBM) 3233 Builder.defineMacro("__TBM__"); 3234 3235 switch (XOPLevel) { 3236 case XOP: 3237 Builder.defineMacro("__XOP__"); 3238 case FMA4: 3239 Builder.defineMacro("__FMA4__"); 3240 case SSE4A: 3241 Builder.defineMacro("__SSE4A__"); 3242 case NoXOP: 3243 break; 3244 } 3245 3246 if (HasFMA) 3247 Builder.defineMacro("__FMA__"); 3248 3249 if (HasF16C) 3250 Builder.defineMacro("__F16C__"); 3251 3252 if (HasAVX512CD) 3253 Builder.defineMacro("__AVX512CD__"); 3254 if (HasAVX512ER) 3255 Builder.defineMacro("__AVX512ER__"); 3256 if (HasAVX512PF) 3257 Builder.defineMacro("__AVX512PF__"); 3258 if (HasAVX512DQ) 3259 Builder.defineMacro("__AVX512DQ__"); 3260 if (HasAVX512BW) 3261 Builder.defineMacro("__AVX512BW__"); 3262 if (HasAVX512VL) 3263 Builder.defineMacro("__AVX512VL__"); 3264 3265 if (HasSHA) 3266 Builder.defineMacro("__SHA__"); 3267 3268 if (HasCX16) 3269 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3270 3271 // Each case falls through to the previous one here. 3272 switch (SSELevel) { 3273 case AVX512F: 3274 Builder.defineMacro("__AVX512F__"); 3275 case AVX2: 3276 Builder.defineMacro("__AVX2__"); 3277 case AVX: 3278 Builder.defineMacro("__AVX__"); 3279 case SSE42: 3280 Builder.defineMacro("__SSE4_2__"); 3281 case SSE41: 3282 Builder.defineMacro("__SSE4_1__"); 3283 case SSSE3: 3284 Builder.defineMacro("__SSSE3__"); 3285 case SSE3: 3286 Builder.defineMacro("__SSE3__"); 3287 case SSE2: 3288 Builder.defineMacro("__SSE2__"); 3289 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3290 case SSE1: 3291 Builder.defineMacro("__SSE__"); 3292 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3293 case NoSSE: 3294 break; 3295 } 3296 3297 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3298 switch (SSELevel) { 3299 case AVX512F: 3300 case AVX2: 3301 case AVX: 3302 case SSE42: 3303 case SSE41: 3304 case SSSE3: 3305 case SSE3: 3306 case SSE2: 3307 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3308 break; 3309 case SSE1: 3310 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3311 break; 3312 default: 3313 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3314 } 3315 } 3316 3317 // Each case falls through to the previous one here. 3318 switch (MMX3DNowLevel) { 3319 case AMD3DNowAthlon: 3320 Builder.defineMacro("__3dNOW_A__"); 3321 case AMD3DNow: 3322 Builder.defineMacro("__3dNOW__"); 3323 case MMX: 3324 Builder.defineMacro("__MMX__"); 3325 case NoMMX3DNow: 3326 break; 3327 } 3328 3329 if (CPU >= CK_i486) { 3330 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3331 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3332 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3333 } 3334 if (CPU >= CK_i586) 3335 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3336 } 3337 3338 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3339 return llvm::StringSwitch<bool>(Feature) 3340 .Case("aes", HasAES) 3341 .Case("avx", SSELevel >= AVX) 3342 .Case("avx2", SSELevel >= AVX2) 3343 .Case("avx512f", SSELevel >= AVX512F) 3344 .Case("avx512cd", HasAVX512CD) 3345 .Case("avx512er", HasAVX512ER) 3346 .Case("avx512pf", HasAVX512PF) 3347 .Case("avx512dq", HasAVX512DQ) 3348 .Case("avx512bw", HasAVX512BW) 3349 .Case("avx512vl", HasAVX512VL) 3350 .Case("bmi", HasBMI) 3351 .Case("bmi2", HasBMI2) 3352 .Case("cx16", HasCX16) 3353 .Case("f16c", HasF16C) 3354 .Case("fma", HasFMA) 3355 .Case("fma4", XOPLevel >= FMA4) 3356 .Case("fsgsbase", HasFSGSBASE) 3357 .Case("lzcnt", HasLZCNT) 3358 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3359 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3360 .Case("mmx", MMX3DNowLevel >= MMX) 3361 .Case("pclmul", HasPCLMUL) 3362 .Case("popcnt", HasPOPCNT) 3363 .Case("prfchw", HasPRFCHW) 3364 .Case("rdrnd", HasRDRND) 3365 .Case("rdseed", HasRDSEED) 3366 .Case("rtm", HasRTM) 3367 .Case("sha", HasSHA) 3368 .Case("sse", SSELevel >= SSE1) 3369 .Case("sse2", SSELevel >= SSE2) 3370 .Case("sse3", SSELevel >= SSE3) 3371 .Case("ssse3", SSELevel >= SSSE3) 3372 .Case("sse4.1", SSELevel >= SSE41) 3373 .Case("sse4.2", SSELevel >= SSE42) 3374 .Case("sse4a", XOPLevel >= SSE4A) 3375 .Case("tbm", HasTBM) 3376 .Case("x86", true) 3377 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3378 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3379 .Case("xop", XOPLevel >= XOP) 3380 .Default(false); 3381 } 3382 3383 // We can't use a generic validation scheme for the features accepted here 3384 // versus subtarget features accepted in the target attribute because the 3385 // bitfield structure that's initialized in the runtime only supports the 3386 // below currently rather than the full range of subtarget features. (See 3387 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3388 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3389 return llvm::StringSwitch<bool>(FeatureStr) 3390 .Case("cmov", true) 3391 .Case("mmx", true) 3392 .Case("popcnt", true) 3393 .Case("sse", true) 3394 .Case("sse2", true) 3395 .Case("sse3", true) 3396 .Case("sse4.1", true) 3397 .Case("sse4.2", true) 3398 .Case("avx", true) 3399 .Case("avx2", true) 3400 .Case("sse4a", true) 3401 .Case("fma4", true) 3402 .Case("xop", true) 3403 .Case("fma", true) 3404 .Case("avx512f", true) 3405 .Case("bmi", true) 3406 .Case("bmi2", true) 3407 .Default(false); 3408 } 3409 3410 bool 3411 X86TargetInfo::validateAsmConstraint(const char *&Name, 3412 TargetInfo::ConstraintInfo &Info) const { 3413 switch (*Name) { 3414 default: return false; 3415 // Constant constraints. 3416 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3417 // instructions. 3418 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3419 // x86_64 instructions. 3420 case 's': 3421 Info.setRequiresImmediate(); 3422 return true; 3423 case 'I': 3424 Info.setRequiresImmediate(0, 31); 3425 return true; 3426 case 'J': 3427 Info.setRequiresImmediate(0, 63); 3428 return true; 3429 case 'K': 3430 Info.setRequiresImmediate(-128, 127); 3431 return true; 3432 case 'L': 3433 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3434 return true; 3435 case 'M': 3436 Info.setRequiresImmediate(0, 3); 3437 return true; 3438 case 'N': 3439 Info.setRequiresImmediate(0, 255); 3440 return true; 3441 case 'O': 3442 Info.setRequiresImmediate(0, 127); 3443 return true; 3444 // Register constraints. 3445 case 'Y': // 'Y' is the first character for several 2-character constraints. 3446 // Shift the pointer to the second character of the constraint. 3447 Name++; 3448 switch (*Name) { 3449 default: 3450 return false; 3451 case '0': // First SSE register. 3452 case 't': // Any SSE register, when SSE2 is enabled. 3453 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3454 case 'm': // Any MMX register, when inter-unit moves enabled. 3455 Info.setAllowsRegister(); 3456 return true; 3457 } 3458 case 'f': // Any x87 floating point stack register. 3459 // Constraint 'f' cannot be used for output operands. 3460 if (Info.ConstraintStr[0] == '=') 3461 return false; 3462 Info.setAllowsRegister(); 3463 return true; 3464 case 'a': // eax. 3465 case 'b': // ebx. 3466 case 'c': // ecx. 3467 case 'd': // edx. 3468 case 'S': // esi. 3469 case 'D': // edi. 3470 case 'A': // edx:eax. 3471 case 't': // Top of floating point stack. 3472 case 'u': // Second from top of floating point stack. 3473 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3474 case 'y': // Any MMX register. 3475 case 'x': // Any SSE register. 3476 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3477 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3478 case 'l': // "Index" registers: any general register that can be used as an 3479 // index in a base+index memory access. 3480 Info.setAllowsRegister(); 3481 return true; 3482 // Floating point constant constraints. 3483 case 'C': // SSE floating point constant. 3484 case 'G': // x87 floating point constant. 3485 return true; 3486 } 3487 } 3488 3489 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3490 unsigned Size) const { 3491 // Strip off constraint modifiers. 3492 while (Constraint[0] == '=' || 3493 Constraint[0] == '+' || 3494 Constraint[0] == '&') 3495 Constraint = Constraint.substr(1); 3496 3497 return validateOperandSize(Constraint, Size); 3498 } 3499 3500 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3501 unsigned Size) const { 3502 return validateOperandSize(Constraint, Size); 3503 } 3504 3505 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3506 unsigned Size) const { 3507 switch (Constraint[0]) { 3508 default: break; 3509 case 'y': 3510 return Size <= 64; 3511 case 'f': 3512 case 't': 3513 case 'u': 3514 return Size <= 128; 3515 case 'x': 3516 if (SSELevel >= AVX512F) 3517 // 512-bit zmm registers can be used if target supports AVX512F. 3518 return Size <= 512U; 3519 else if (SSELevel >= AVX) 3520 // 256-bit ymm registers can be used if target supports AVX. 3521 return Size <= 256U; 3522 return Size <= 128U; 3523 case 'Y': 3524 // 'Y' is the first character for several 2-character constraints. 3525 switch (Constraint[1]) { 3526 default: break; 3527 case 'm': 3528 // 'Ym' is synonymous with 'y'. 3529 return Size <= 64; 3530 case 'i': 3531 case 't': 3532 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3533 if (SSELevel >= AVX512F) 3534 return Size <= 512U; 3535 else if (SSELevel >= AVX) 3536 return Size <= 256U; 3537 return SSELevel >= SSE2 && Size <= 128U; 3538 } 3539 3540 } 3541 3542 return true; 3543 } 3544 3545 std::string 3546 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3547 switch (*Constraint) { 3548 case 'a': return std::string("{ax}"); 3549 case 'b': return std::string("{bx}"); 3550 case 'c': return std::string("{cx}"); 3551 case 'd': return std::string("{dx}"); 3552 case 'S': return std::string("{si}"); 3553 case 'D': return std::string("{di}"); 3554 case 'p': // address 3555 return std::string("im"); 3556 case 't': // top of floating point stack. 3557 return std::string("{st}"); 3558 case 'u': // second from top of floating point stack. 3559 return std::string("{st(1)}"); // second from top of floating point stack. 3560 default: 3561 return std::string(1, *Constraint); 3562 } 3563 } 3564 3565 // X86-32 generic target 3566 class X86_32TargetInfo : public X86TargetInfo { 3567 public: 3568 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3569 DoubleAlign = LongLongAlign = 32; 3570 LongDoubleWidth = 96; 3571 LongDoubleAlign = 32; 3572 SuitableAlign = 128; 3573 DataLayoutString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3574 SizeType = UnsignedInt; 3575 PtrDiffType = SignedInt; 3576 IntPtrType = SignedInt; 3577 RegParmMax = 3; 3578 3579 // Use fpret for all types. 3580 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3581 (1 << TargetInfo::Double) | 3582 (1 << TargetInfo::LongDouble)); 3583 3584 // x86-32 has atomics up to 8 bytes 3585 // FIXME: Check that we actually have cmpxchg8b before setting 3586 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3587 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3588 } 3589 BuiltinVaListKind getBuiltinVaListKind() const override { 3590 return TargetInfo::CharPtrBuiltinVaList; 3591 } 3592 3593 int getEHDataRegisterNumber(unsigned RegNo) const override { 3594 if (RegNo == 0) return 0; 3595 if (RegNo == 1) return 2; 3596 return -1; 3597 } 3598 bool validateOperandSize(StringRef Constraint, 3599 unsigned Size) const override { 3600 switch (Constraint[0]) { 3601 default: break; 3602 case 'R': 3603 case 'q': 3604 case 'Q': 3605 case 'a': 3606 case 'b': 3607 case 'c': 3608 case 'd': 3609 case 'S': 3610 case 'D': 3611 return Size <= 32; 3612 case 'A': 3613 return Size <= 64; 3614 } 3615 3616 return X86TargetInfo::validateOperandSize(Constraint, Size); 3617 } 3618 }; 3619 3620 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3621 public: 3622 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3623 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3624 3625 unsigned getFloatEvalMethod() const override { 3626 unsigned Major, Minor, Micro; 3627 getTriple().getOSVersion(Major, Minor, Micro); 3628 // New NetBSD uses the default rounding mode. 3629 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3630 return X86_32TargetInfo::getFloatEvalMethod(); 3631 // NetBSD before 6.99.26 defaults to "double" rounding. 3632 return 1; 3633 } 3634 }; 3635 3636 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3637 public: 3638 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3639 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3640 SizeType = UnsignedLong; 3641 IntPtrType = SignedLong; 3642 PtrDiffType = SignedLong; 3643 } 3644 }; 3645 3646 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3647 public: 3648 BitrigI386TargetInfo(const llvm::Triple &Triple) 3649 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3650 SizeType = UnsignedLong; 3651 IntPtrType = SignedLong; 3652 PtrDiffType = SignedLong; 3653 } 3654 }; 3655 3656 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3657 public: 3658 DarwinI386TargetInfo(const llvm::Triple &Triple) 3659 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3660 LongDoubleWidth = 128; 3661 LongDoubleAlign = 128; 3662 SuitableAlign = 128; 3663 SizeType = UnsignedLong; 3664 IntPtrType = SignedLong; 3665 DataLayoutString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3666 HasAlignMac68kSupport = true; 3667 } 3668 3669 bool handleTargetFeatures(std::vector<std::string> &Features, 3670 DiagnosticsEngine &Diags) override { 3671 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 3672 Diags)) 3673 return false; 3674 // We now know the features we have: we can decide how to align vectors. 3675 MaxVectorAlign = 3676 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3677 return true; 3678 } 3679 }; 3680 3681 // x86-32 Windows target 3682 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3683 public: 3684 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3685 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3686 WCharType = UnsignedShort; 3687 DoubleAlign = LongLongAlign = 64; 3688 bool IsWinCOFF = 3689 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3690 DataLayoutString = IsWinCOFF 3691 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3692 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3693 } 3694 void getTargetDefines(const LangOptions &Opts, 3695 MacroBuilder &Builder) const override { 3696 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3697 } 3698 }; 3699 3700 // x86-32 Windows Visual Studio target 3701 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3702 public: 3703 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3704 : WindowsX86_32TargetInfo(Triple) { 3705 LongDoubleWidth = LongDoubleAlign = 64; 3706 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3707 } 3708 void getTargetDefines(const LangOptions &Opts, 3709 MacroBuilder &Builder) const override { 3710 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3711 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3712 // The value of the following reflects processor type. 3713 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3714 // We lost the original triple, so we use the default. 3715 Builder.defineMacro("_M_IX86", "600"); 3716 } 3717 }; 3718 3719 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3720 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 3721 // supports __declspec natively under -fms-extensions, but we define a no-op 3722 // __declspec macro anyway for pre-processor compatibility. 3723 if (Opts.MicrosoftExt) 3724 Builder.defineMacro("__declspec", "__declspec"); 3725 else 3726 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3727 3728 if (!Opts.MicrosoftExt) { 3729 // Provide macros for all the calling convention keywords. Provide both 3730 // single and double underscore prefixed variants. These are available on 3731 // x64 as well as x86, even though they have no effect. 3732 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3733 for (const char *CC : CCs) { 3734 std::string GCCSpelling = "__attribute__((__"; 3735 GCCSpelling += CC; 3736 GCCSpelling += "__))"; 3737 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3738 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3739 } 3740 } 3741 } 3742 3743 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3744 Builder.defineMacro("__MSVCRT__"); 3745 Builder.defineMacro("__MINGW32__"); 3746 addCygMingDefines(Opts, Builder); 3747 } 3748 3749 // x86-32 MinGW target 3750 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3751 public: 3752 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3753 : WindowsX86_32TargetInfo(Triple) {} 3754 void getTargetDefines(const LangOptions &Opts, 3755 MacroBuilder &Builder) const override { 3756 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3757 DefineStd(Builder, "WIN32", Opts); 3758 DefineStd(Builder, "WINNT", Opts); 3759 Builder.defineMacro("_X86_"); 3760 addMinGWDefines(Opts, Builder); 3761 } 3762 }; 3763 3764 // x86-32 Cygwin target 3765 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3766 public: 3767 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3768 : X86_32TargetInfo(Triple) { 3769 TLSSupported = false; 3770 WCharType = UnsignedShort; 3771 DoubleAlign = LongLongAlign = 64; 3772 DataLayoutString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3773 } 3774 void getTargetDefines(const LangOptions &Opts, 3775 MacroBuilder &Builder) const override { 3776 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3777 Builder.defineMacro("_X86_"); 3778 Builder.defineMacro("__CYGWIN__"); 3779 Builder.defineMacro("__CYGWIN32__"); 3780 addCygMingDefines(Opts, Builder); 3781 DefineStd(Builder, "unix", Opts); 3782 if (Opts.CPlusPlus) 3783 Builder.defineMacro("_GNU_SOURCE"); 3784 } 3785 }; 3786 3787 // x86-32 Haiku target 3788 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3789 public: 3790 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3791 SizeType = UnsignedLong; 3792 IntPtrType = SignedLong; 3793 PtrDiffType = SignedLong; 3794 ProcessIDType = SignedLong; 3795 this->UserLabelPrefix = ""; 3796 this->TLSSupported = false; 3797 } 3798 void getTargetDefines(const LangOptions &Opts, 3799 MacroBuilder &Builder) const override { 3800 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3801 Builder.defineMacro("__INTEL__"); 3802 Builder.defineMacro("__HAIKU__"); 3803 } 3804 }; 3805 3806 // RTEMS Target 3807 template<typename Target> 3808 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3809 protected: 3810 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3811 MacroBuilder &Builder) const override { 3812 // RTEMS defines; list based off of gcc output 3813 3814 Builder.defineMacro("__rtems__"); 3815 Builder.defineMacro("__ELF__"); 3816 } 3817 3818 public: 3819 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3820 this->UserLabelPrefix = ""; 3821 3822 switch (Triple.getArch()) { 3823 default: 3824 case llvm::Triple::x86: 3825 // this->MCountName = ".mcount"; 3826 break; 3827 case llvm::Triple::mips: 3828 case llvm::Triple::mipsel: 3829 case llvm::Triple::ppc: 3830 case llvm::Triple::ppc64: 3831 case llvm::Triple::ppc64le: 3832 // this->MCountName = "_mcount"; 3833 break; 3834 case llvm::Triple::arm: 3835 // this->MCountName = "__mcount"; 3836 break; 3837 } 3838 } 3839 }; 3840 3841 // x86-32 RTEMS target 3842 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3843 public: 3844 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3845 SizeType = UnsignedLong; 3846 IntPtrType = SignedLong; 3847 PtrDiffType = SignedLong; 3848 this->UserLabelPrefix = ""; 3849 } 3850 void getTargetDefines(const LangOptions &Opts, 3851 MacroBuilder &Builder) const override { 3852 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3853 Builder.defineMacro("__INTEL__"); 3854 Builder.defineMacro("__rtems__"); 3855 } 3856 }; 3857 3858 // x86-64 generic target 3859 class X86_64TargetInfo : public X86TargetInfo { 3860 public: 3861 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3862 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3863 bool IsWinCOFF = 3864 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3865 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3866 LongDoubleWidth = 128; 3867 LongDoubleAlign = 128; 3868 LargeArrayMinWidth = 128; 3869 LargeArrayAlign = 128; 3870 SuitableAlign = 128; 3871 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3872 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3873 IntPtrType = IsX32 ? SignedInt : SignedLong; 3874 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3875 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3876 RegParmMax = 6; 3877 3878 // Pointers are 32-bit in x32. 3879 DataLayoutString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3880 : IsWinCOFF 3881 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 3882 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3883 3884 // Use fpret only for long double. 3885 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3886 3887 // Use fp2ret for _Complex long double. 3888 ComplexLongDoubleUsesFP2Ret = true; 3889 3890 // Make __builtin_ms_va_list available. 3891 HasBuiltinMSVaList = true; 3892 3893 // x86-64 has atomics up to 16 bytes. 3894 MaxAtomicPromoteWidth = 128; 3895 MaxAtomicInlineWidth = 128; 3896 } 3897 BuiltinVaListKind getBuiltinVaListKind() const override { 3898 return TargetInfo::X86_64ABIBuiltinVaList; 3899 } 3900 3901 int getEHDataRegisterNumber(unsigned RegNo) const override { 3902 if (RegNo == 0) return 0; 3903 if (RegNo == 1) return 1; 3904 return -1; 3905 } 3906 3907 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3908 return (CC == CC_C || 3909 CC == CC_X86VectorCall || 3910 CC == CC_IntelOclBicc || 3911 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3912 } 3913 3914 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3915 return CC_C; 3916 } 3917 3918 // for x32 we need it here explicitly 3919 bool hasInt128Type() const override { return true; } 3920 }; 3921 3922 // x86-64 Windows target 3923 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3924 public: 3925 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3926 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3927 WCharType = UnsignedShort; 3928 LongWidth = LongAlign = 32; 3929 DoubleAlign = LongLongAlign = 64; 3930 IntMaxType = SignedLongLong; 3931 Int64Type = SignedLongLong; 3932 SizeType = UnsignedLongLong; 3933 PtrDiffType = SignedLongLong; 3934 IntPtrType = SignedLongLong; 3935 this->UserLabelPrefix = ""; 3936 } 3937 3938 void getTargetDefines(const LangOptions &Opts, 3939 MacroBuilder &Builder) const override { 3940 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3941 Builder.defineMacro("_WIN64"); 3942 } 3943 3944 BuiltinVaListKind getBuiltinVaListKind() const override { 3945 return TargetInfo::CharPtrBuiltinVaList; 3946 } 3947 3948 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3949 switch (CC) { 3950 case CC_X86StdCall: 3951 case CC_X86ThisCall: 3952 case CC_X86FastCall: 3953 return CCCR_Ignore; 3954 case CC_C: 3955 case CC_X86VectorCall: 3956 case CC_IntelOclBicc: 3957 case CC_X86_64SysV: 3958 return CCCR_OK; 3959 default: 3960 return CCCR_Warning; 3961 } 3962 } 3963 }; 3964 3965 // x86-64 Windows Visual Studio target 3966 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 3967 public: 3968 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 3969 : WindowsX86_64TargetInfo(Triple) { 3970 LongDoubleWidth = LongDoubleAlign = 64; 3971 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3972 } 3973 void getTargetDefines(const LangOptions &Opts, 3974 MacroBuilder &Builder) const override { 3975 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3976 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3977 Builder.defineMacro("_M_X64", "100"); 3978 Builder.defineMacro("_M_AMD64", "100"); 3979 } 3980 }; 3981 3982 // x86-64 MinGW target 3983 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3984 public: 3985 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3986 : WindowsX86_64TargetInfo(Triple) {} 3987 void getTargetDefines(const LangOptions &Opts, 3988 MacroBuilder &Builder) const override { 3989 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3990 DefineStd(Builder, "WIN64", Opts); 3991 Builder.defineMacro("__MINGW64__"); 3992 addMinGWDefines(Opts, Builder); 3993 3994 // GCC defines this macro when it is using __gxx_personality_seh0. 3995 if (!Opts.SjLjExceptions) 3996 Builder.defineMacro("__SEH__"); 3997 } 3998 }; 3999 4000 // x86-64 Cygwin target 4001 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4002 public: 4003 CygwinX86_64TargetInfo(const llvm::Triple &Triple) 4004 : X86_64TargetInfo(Triple) { 4005 TLSSupported = false; 4006 WCharType = UnsignedShort; 4007 } 4008 void getTargetDefines(const LangOptions &Opts, 4009 MacroBuilder &Builder) const override { 4010 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4011 Builder.defineMacro("__x86_64__"); 4012 Builder.defineMacro("__CYGWIN__"); 4013 Builder.defineMacro("__CYGWIN64__"); 4014 addCygMingDefines(Opts, Builder); 4015 DefineStd(Builder, "unix", Opts); 4016 if (Opts.CPlusPlus) 4017 Builder.defineMacro("_GNU_SOURCE"); 4018 4019 // GCC defines this macro when it is using __gxx_personality_seh0. 4020 if (!Opts.SjLjExceptions) 4021 Builder.defineMacro("__SEH__"); 4022 } 4023 }; 4024 4025 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4026 public: 4027 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 4028 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 4029 Int64Type = SignedLongLong; 4030 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4031 llvm::Triple T = llvm::Triple(Triple); 4032 if (T.isiOS()) 4033 UseSignedCharForObjCBool = false; 4034 DataLayoutString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 4035 } 4036 4037 bool handleTargetFeatures(std::vector<std::string> &Features, 4038 DiagnosticsEngine &Diags) override { 4039 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4040 Diags)) 4041 return false; 4042 // We now know the features we have: we can decide how to align vectors. 4043 MaxVectorAlign = 4044 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4045 return true; 4046 } 4047 }; 4048 4049 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4050 public: 4051 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 4052 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 4053 IntMaxType = SignedLongLong; 4054 Int64Type = SignedLongLong; 4055 } 4056 }; 4057 4058 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4059 public: 4060 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 4061 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 4062 IntMaxType = SignedLongLong; 4063 Int64Type = SignedLongLong; 4064 } 4065 }; 4066 4067 class ARMTargetInfo : public TargetInfo { 4068 // Possible FPU choices. 4069 enum FPUMode { 4070 VFP2FPU = (1 << 0), 4071 VFP3FPU = (1 << 1), 4072 VFP4FPU = (1 << 2), 4073 NeonFPU = (1 << 3), 4074 FPARMV8 = (1 << 4) 4075 }; 4076 4077 // Possible HWDiv features. 4078 enum HWDivMode { 4079 HWDivThumb = (1 << 0), 4080 HWDivARM = (1 << 1) 4081 }; 4082 4083 static bool FPUModeIsVFP(FPUMode Mode) { 4084 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4085 } 4086 4087 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4088 static const char * const GCCRegNames[]; 4089 4090 std::string ABI, CPU; 4091 4092 StringRef CPUProfile; 4093 StringRef CPUAttr; 4094 4095 enum { 4096 FP_Default, 4097 FP_VFP, 4098 FP_Neon 4099 } FPMath; 4100 4101 unsigned ArchISA; 4102 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4103 unsigned ArchProfile; 4104 unsigned ArchVersion; 4105 4106 unsigned FPU : 5; 4107 4108 unsigned IsAAPCS : 1; 4109 unsigned HWDiv : 2; 4110 4111 // Initialized via features. 4112 unsigned SoftFloat : 1; 4113 unsigned SoftFloatABI : 1; 4114 4115 unsigned CRC : 1; 4116 unsigned Crypto : 1; 4117 unsigned DSP : 1; 4118 unsigned Unaligned : 1; 4119 4120 enum { 4121 LDREX_B = (1 << 0), /// byte (8-bit) 4122 LDREX_H = (1 << 1), /// half (16-bit) 4123 LDREX_W = (1 << 2), /// word (32-bit) 4124 LDREX_D = (1 << 3), /// double (64-bit) 4125 }; 4126 4127 uint32_t LDREX; 4128 4129 // ACLE 6.5.1 Hardware floating point 4130 enum { 4131 HW_FP_HP = (1 << 1), /// half (16-bit) 4132 HW_FP_SP = (1 << 2), /// single (32-bit) 4133 HW_FP_DP = (1 << 3), /// double (64-bit) 4134 }; 4135 uint32_t HW_FP; 4136 4137 static const Builtin::Info BuiltinInfo[]; 4138 4139 void setABIAAPCS() { 4140 IsAAPCS = true; 4141 4142 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4143 const llvm::Triple &T = getTriple(); 4144 4145 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4146 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4147 T.getOS() == llvm::Triple::Bitrig) 4148 SizeType = UnsignedLong; 4149 else 4150 SizeType = UnsignedInt; 4151 4152 switch (T.getOS()) { 4153 case llvm::Triple::NetBSD: 4154 WCharType = SignedInt; 4155 break; 4156 case llvm::Triple::Win32: 4157 WCharType = UnsignedShort; 4158 break; 4159 case llvm::Triple::Linux: 4160 default: 4161 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4162 WCharType = UnsignedInt; 4163 break; 4164 } 4165 4166 UseBitFieldTypeAlignment = true; 4167 4168 ZeroLengthBitfieldBoundary = 0; 4169 4170 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4171 // so set preferred for small types to 32. 4172 if (T.isOSBinFormatMachO()) { 4173 DataLayoutString = 4174 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4175 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4176 } else if (T.isOSWindows()) { 4177 assert(!BigEndian && "Windows on ARM does not support big endian"); 4178 DataLayoutString = "e" 4179 "-m:w" 4180 "-p:32:32" 4181 "-i64:64" 4182 "-v128:64:128" 4183 "-a:0:32" 4184 "-n32" 4185 "-S64"; 4186 } else if (T.isOSNaCl()) { 4187 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4188 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 4189 } else { 4190 DataLayoutString = 4191 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4192 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4193 } 4194 4195 // FIXME: Enumerated types are variable width in straight AAPCS. 4196 } 4197 4198 void setABIAPCS() { 4199 const llvm::Triple &T = getTriple(); 4200 4201 IsAAPCS = false; 4202 4203 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4204 4205 // size_t is unsigned int on FreeBSD. 4206 if (T.getOS() == llvm::Triple::FreeBSD) 4207 SizeType = UnsignedInt; 4208 else 4209 SizeType = UnsignedLong; 4210 4211 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4212 WCharType = SignedInt; 4213 4214 // Do not respect the alignment of bit-field types when laying out 4215 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4216 UseBitFieldTypeAlignment = false; 4217 4218 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4219 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4220 /// gcc. 4221 ZeroLengthBitfieldBoundary = 32; 4222 4223 if (T.isOSBinFormatMachO()) 4224 DataLayoutString = 4225 BigEndian 4226 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4227 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4228 else 4229 DataLayoutString = 4230 BigEndian 4231 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4232 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4233 4234 // FIXME: Override "preferred align" for double and long long. 4235 } 4236 4237 void setArchInfo() { 4238 StringRef ArchName = getTriple().getArchName(); 4239 4240 ArchISA = llvm::ARM::parseArchISA(ArchName); 4241 CPU = llvm::ARM::getDefaultCPU(ArchName); 4242 unsigned AK = llvm::ARM::parseArch(ArchName); 4243 if (AK != llvm::ARM::AK_INVALID) 4244 ArchKind = AK; 4245 setArchInfo(ArchKind); 4246 } 4247 4248 void setArchInfo(unsigned Kind) { 4249 StringRef SubArch; 4250 4251 // cache TargetParser info 4252 ArchKind = Kind; 4253 SubArch = llvm::ARM::getSubArch(ArchKind); 4254 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4255 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4256 4257 // cache CPU related strings 4258 CPUAttr = getCPUAttr(); 4259 CPUProfile = getCPUProfile(); 4260 } 4261 4262 void setAtomic() { 4263 // when triple does not specify a sub arch, 4264 // then we are not using inline atomics 4265 bool ShouldUseInlineAtomic = 4266 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4267 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4268 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4269 if (ArchProfile == llvm::ARM::PK_M) { 4270 MaxAtomicPromoteWidth = 32; 4271 if (ShouldUseInlineAtomic) 4272 MaxAtomicInlineWidth = 32; 4273 } 4274 else { 4275 MaxAtomicPromoteWidth = 64; 4276 if (ShouldUseInlineAtomic) 4277 MaxAtomicInlineWidth = 64; 4278 } 4279 } 4280 4281 bool isThumb() const { 4282 return (ArchISA == llvm::ARM::IK_THUMB); 4283 } 4284 4285 bool supportsThumb() const { 4286 return CPUAttr.count('T') || ArchVersion >= 6; 4287 } 4288 4289 bool supportsThumb2() const { 4290 return CPUAttr.equals("6T2") || ArchVersion >= 7; 4291 } 4292 4293 StringRef getCPUAttr() const { 4294 // For most sub-arches, the build attribute CPU name is enough. 4295 // For Cortex variants, it's slightly different. 4296 switch(ArchKind) { 4297 default: 4298 return llvm::ARM::getCPUAttr(ArchKind); 4299 case llvm::ARM::AK_ARMV6M: 4300 case llvm::ARM::AK_ARMV6SM: 4301 case llvm::ARM::AK_ARMV6HL: 4302 return "6M"; 4303 case llvm::ARM::AK_ARMV7S: 4304 return "7S"; 4305 case llvm::ARM::AK_ARMV7: 4306 case llvm::ARM::AK_ARMV7A: 4307 case llvm::ARM::AK_ARMV7L: 4308 case llvm::ARM::AK_ARMV7HL: 4309 return "7A"; 4310 case llvm::ARM::AK_ARMV7R: 4311 return "7R"; 4312 case llvm::ARM::AK_ARMV7M: 4313 return "7M"; 4314 case llvm::ARM::AK_ARMV7EM: 4315 return "7EM"; 4316 case llvm::ARM::AK_ARMV8A: 4317 return "8A"; 4318 case llvm::ARM::AK_ARMV8_1A: 4319 return "8_1A"; 4320 } 4321 } 4322 4323 StringRef getCPUProfile() const { 4324 switch(ArchProfile) { 4325 case llvm::ARM::PK_A: 4326 return "A"; 4327 case llvm::ARM::PK_R: 4328 return "R"; 4329 case llvm::ARM::PK_M: 4330 return "M"; 4331 default: 4332 return ""; 4333 } 4334 } 4335 4336 public: 4337 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4338 : TargetInfo(Triple), FPMath(FP_Default), 4339 IsAAPCS(true), LDREX(0), HW_FP(0) { 4340 BigEndian = IsBigEndian; 4341 4342 switch (getTriple().getOS()) { 4343 case llvm::Triple::NetBSD: 4344 PtrDiffType = SignedLong; 4345 break; 4346 default: 4347 PtrDiffType = SignedInt; 4348 break; 4349 } 4350 4351 // Cache arch related info. 4352 setArchInfo(); 4353 4354 // {} in inline assembly are neon specifiers, not assembly variant 4355 // specifiers. 4356 NoAsmVariants = true; 4357 4358 // FIXME: This duplicates code from the driver that sets the -target-abi 4359 // option - this code is used if -target-abi isn't passed and should 4360 // be unified in some way. 4361 if (Triple.isOSBinFormatMachO()) { 4362 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4363 // the frontend matches that. 4364 if (Triple.getEnvironment() == llvm::Triple::EABI || 4365 Triple.getOS() == llvm::Triple::UnknownOS || 4366 StringRef(CPU).startswith("cortex-m")) { 4367 setABI("aapcs"); 4368 } else { 4369 setABI("apcs-gnu"); 4370 } 4371 } else if (Triple.isOSWindows()) { 4372 // FIXME: this is invalid for WindowsCE 4373 setABI("aapcs"); 4374 } else { 4375 // Select the default based on the platform. 4376 switch (Triple.getEnvironment()) { 4377 case llvm::Triple::Android: 4378 case llvm::Triple::GNUEABI: 4379 case llvm::Triple::GNUEABIHF: 4380 setABI("aapcs-linux"); 4381 break; 4382 case llvm::Triple::EABIHF: 4383 case llvm::Triple::EABI: 4384 setABI("aapcs"); 4385 break; 4386 case llvm::Triple::GNU: 4387 setABI("apcs-gnu"); 4388 break; 4389 default: 4390 if (Triple.getOS() == llvm::Triple::NetBSD) 4391 setABI("apcs-gnu"); 4392 else 4393 setABI("aapcs"); 4394 break; 4395 } 4396 } 4397 4398 // ARM targets default to using the ARM C++ ABI. 4399 TheCXXABI.set(TargetCXXABI::GenericARM); 4400 4401 // ARM has atomics up to 8 bytes 4402 setAtomic(); 4403 4404 // Do force alignment of members that follow zero length bitfields. If 4405 // the alignment of the zero-length bitfield is greater than the member 4406 // that follows it, `bar', `bar' will be aligned as the type of the 4407 // zero length bitfield. 4408 UseZeroLengthBitfieldAlignment = true; 4409 } 4410 4411 StringRef getABI() const override { return ABI; } 4412 4413 bool setABI(const std::string &Name) override { 4414 ABI = Name; 4415 4416 // The defaults (above) are for AAPCS, check if we need to change them. 4417 // 4418 // FIXME: We need support for -meabi... we could just mangle it into the 4419 // name. 4420 if (Name == "apcs-gnu") { 4421 setABIAPCS(); 4422 return true; 4423 } 4424 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4425 setABIAAPCS(); 4426 return true; 4427 } 4428 return false; 4429 } 4430 4431 // FIXME: This should be based on Arch attributes, not CPU names. 4432 bool 4433 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4434 StringRef CPU, 4435 const std::vector<std::string> &FeaturesVec) const override { 4436 4437 std::vector<const char*> TargetFeatures; 4438 4439 // get default FPU features 4440 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU); 4441 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4442 4443 // get default Extension features 4444 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU); 4445 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4446 4447 for (const char *Feature : TargetFeatures) 4448 if (Feature[0] == '+') 4449 Features[Feature+1] = true; 4450 4451 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4452 } 4453 4454 bool handleTargetFeatures(std::vector<std::string> &Features, 4455 DiagnosticsEngine &Diags) override { 4456 FPU = 0; 4457 CRC = 0; 4458 Crypto = 0; 4459 DSP = 0; 4460 Unaligned = 1; 4461 SoftFloat = SoftFloatABI = false; 4462 HWDiv = 0; 4463 4464 // This does not diagnose illegal cases like having both 4465 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4466 uint32_t HW_FP_remove = 0; 4467 for (const auto &Feature : Features) { 4468 if (Feature == "+soft-float") { 4469 SoftFloat = true; 4470 } else if (Feature == "+soft-float-abi") { 4471 SoftFloatABI = true; 4472 } else if (Feature == "+vfp2") { 4473 FPU |= VFP2FPU; 4474 HW_FP |= HW_FP_SP | HW_FP_DP; 4475 } else if (Feature == "+vfp3") { 4476 FPU |= VFP3FPU; 4477 HW_FP |= HW_FP_SP | HW_FP_DP; 4478 } else if (Feature == "+vfp4") { 4479 FPU |= VFP4FPU; 4480 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4481 } else if (Feature == "+fp-armv8") { 4482 FPU |= FPARMV8; 4483 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4484 } else if (Feature == "+neon") { 4485 FPU |= NeonFPU; 4486 HW_FP |= HW_FP_SP | HW_FP_DP; 4487 } else if (Feature == "+hwdiv") { 4488 HWDiv |= HWDivThumb; 4489 } else if (Feature == "+hwdiv-arm") { 4490 HWDiv |= HWDivARM; 4491 } else if (Feature == "+crc") { 4492 CRC = 1; 4493 } else if (Feature == "+crypto") { 4494 Crypto = 1; 4495 } else if (Feature == "+t2dsp") { 4496 DSP = 1; 4497 } else if (Feature == "+fp-only-sp") { 4498 HW_FP_remove |= HW_FP_DP | HW_FP_HP; 4499 } else if (Feature == "+strict-align") { 4500 Unaligned = 0; 4501 } else if (Feature == "+fp16") { 4502 HW_FP |= HW_FP_HP; 4503 } 4504 } 4505 HW_FP &= ~HW_FP_remove; 4506 4507 switch (ArchVersion) { 4508 case 6: 4509 if (ArchProfile == llvm::ARM::PK_M) 4510 LDREX = 0; 4511 else if (ArchKind == llvm::ARM::AK_ARMV6K) 4512 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4513 else 4514 LDREX = LDREX_W; 4515 break; 4516 case 7: 4517 if (ArchProfile == llvm::ARM::PK_M) 4518 LDREX = LDREX_W | LDREX_H | LDREX_B ; 4519 else 4520 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4521 break; 4522 case 8: 4523 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4524 } 4525 4526 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4527 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4528 return false; 4529 } 4530 4531 if (FPMath == FP_Neon) 4532 Features.push_back("+neonfp"); 4533 else if (FPMath == FP_VFP) 4534 Features.push_back("-neonfp"); 4535 4536 // Remove front-end specific options which the backend handles differently. 4537 auto Feature = 4538 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4539 if (Feature != Features.end()) 4540 Features.erase(Feature); 4541 4542 return true; 4543 } 4544 4545 bool hasFeature(StringRef Feature) const override { 4546 return llvm::StringSwitch<bool>(Feature) 4547 .Case("arm", true) 4548 .Case("aarch32", true) 4549 .Case("softfloat", SoftFloat) 4550 .Case("thumb", isThumb()) 4551 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4552 .Case("hwdiv", HWDiv & HWDivThumb) 4553 .Case("hwdiv-arm", HWDiv & HWDivARM) 4554 .Default(false); 4555 } 4556 4557 bool setCPU(const std::string &Name) override { 4558 if (Name != "generic") 4559 setArchInfo(llvm::ARM::parseCPUArch(Name)); 4560 4561 if (ArchKind == llvm::ARM::AK_INVALID) 4562 return false; 4563 setAtomic(); 4564 CPU = Name; 4565 return true; 4566 } 4567 4568 bool setFPMath(StringRef Name) override; 4569 4570 void getTargetDefines(const LangOptions &Opts, 4571 MacroBuilder &Builder) const override { 4572 // Target identification. 4573 Builder.defineMacro("__arm"); 4574 Builder.defineMacro("__arm__"); 4575 4576 // Target properties. 4577 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4578 if (!CPUAttr.empty()) 4579 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 4580 4581 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4582 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4583 Builder.defineMacro("__ARM_ARCH", llvm::utostr(ArchVersion)); 4584 4585 if (ArchVersion >= 8) { 4586 // ACLE 6.5.7 Crypto Extension 4587 if (Crypto) 4588 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 4589 // ACLE 6.5.8 CRC32 Extension 4590 if (CRC) 4591 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 4592 // ACLE 6.5.10 Numeric Maximum and Minimum 4593 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 4594 // ACLE 6.5.9 Directed Rounding 4595 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 4596 } 4597 4598 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4599 // is not defined for the M-profile. 4600 // NOTE that the deffault profile is assumed to be 'A' 4601 if (CPUProfile.empty() || CPUProfile != "M") 4602 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4603 4604 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4605 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4606 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4607 if (supportsThumb2()) 4608 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4609 else if (supportsThumb()) 4610 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4611 4612 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4613 // instruction set such as ARM or Thumb. 4614 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4615 4616 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4617 4618 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4619 if (!CPUProfile.empty()) 4620 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4621 4622 // ACLE 6.4.3 Unaligned access supported in hardware 4623 if (Unaligned) 4624 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 4625 4626 // ACLE 6.4.4 LDREX/STREX 4627 if (LDREX) 4628 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 4629 4630 // ACLE 6.4.5 CLZ 4631 if (ArchVersion == 5 || 4632 (ArchVersion == 6 && CPUProfile != "M") || 4633 ArchVersion > 6) 4634 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 4635 4636 // ACLE 6.5.1 Hardware Floating Point 4637 if (HW_FP) 4638 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4639 4640 // ACLE predefines. 4641 Builder.defineMacro("__ARM_ACLE", "200"); 4642 4643 // FP16 support (we currently only support IEEE format). 4644 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 4645 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 4646 4647 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 4648 if (ArchVersion >= 7 && (CPUProfile != "M" || CPUAttr == "7EM")) 4649 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 4650 4651 // Subtarget options. 4652 4653 // FIXME: It's more complicated than this and we don't really support 4654 // interworking. 4655 // Windows on ARM does not "support" interworking 4656 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 4657 Builder.defineMacro("__THUMB_INTERWORK__"); 4658 4659 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4660 // Embedded targets on Darwin follow AAPCS, but not EABI. 4661 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4662 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4663 Builder.defineMacro("__ARM_EABI__"); 4664 Builder.defineMacro("__ARM_PCS", "1"); 4665 4666 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4667 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4668 } 4669 4670 if (SoftFloat) 4671 Builder.defineMacro("__SOFTFP__"); 4672 4673 if (CPU == "xscale") 4674 Builder.defineMacro("__XSCALE__"); 4675 4676 if (isThumb()) { 4677 Builder.defineMacro("__THUMBEL__"); 4678 Builder.defineMacro("__thumb__"); 4679 if (supportsThumb2()) 4680 Builder.defineMacro("__thumb2__"); 4681 } 4682 4683 // ACLE 6.4.9 32-bit SIMD instructions 4684 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 4685 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 4686 4687 // ACLE 6.4.10 Hardware Integer Divide 4688 if (((HWDiv & HWDivThumb) && isThumb()) || 4689 ((HWDiv & HWDivARM) && !isThumb())) { 4690 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 4691 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4692 } 4693 4694 // Note, this is always on in gcc, even though it doesn't make sense. 4695 Builder.defineMacro("__APCS_32__"); 4696 4697 if (FPUModeIsVFP((FPUMode) FPU)) { 4698 Builder.defineMacro("__VFP_FP__"); 4699 if (FPU & VFP2FPU) 4700 Builder.defineMacro("__ARM_VFPV2__"); 4701 if (FPU & VFP3FPU) 4702 Builder.defineMacro("__ARM_VFPV3__"); 4703 if (FPU & VFP4FPU) 4704 Builder.defineMacro("__ARM_VFPV4__"); 4705 } 4706 4707 // This only gets set when Neon instructions are actually available, unlike 4708 // the VFP define, hence the soft float and arch check. This is subtly 4709 // different from gcc, we follow the intent which was that it should be set 4710 // when Neon instructions are actually available. 4711 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 4712 Builder.defineMacro("__ARM_NEON", "1"); 4713 Builder.defineMacro("__ARM_NEON__"); 4714 // current AArch32 NEON implementations do not support double-precision 4715 // floating-point even when it is present in VFP. 4716 Builder.defineMacro("__ARM_NEON_FP", 4717 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 4718 } 4719 4720 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4721 Opts.ShortWChar ? "2" : "4"); 4722 4723 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4724 Opts.ShortEnums ? "1" : "4"); 4725 4726 if (ArchVersion >= 6 && CPUAttr != "6M") { 4727 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4728 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4729 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4730 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4731 } 4732 4733 // ACLE 6.4.7 DSP instructions 4734 if (DSP) { 4735 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 4736 } 4737 4738 // ACLE 6.4.8 Saturation instructions 4739 bool SAT = false; 4740 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 4741 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 4742 SAT = true; 4743 } 4744 4745 // ACLE 6.4.6 Q (saturation) flag 4746 if (DSP || SAT) 4747 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 4748 4749 if (Opts.UnsafeFPMath) 4750 Builder.defineMacro("__ARM_FP_FAST", "1"); 4751 } 4752 4753 void getTargetBuiltins(const Builtin::Info *&Records, 4754 unsigned &NumRecords) const override { 4755 Records = BuiltinInfo; 4756 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4757 } 4758 bool isCLZForZeroUndef() const override { return false; } 4759 BuiltinVaListKind getBuiltinVaListKind() const override { 4760 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4761 } 4762 void getGCCRegNames(const char * const *&Names, 4763 unsigned &NumNames) const override; 4764 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4765 unsigned &NumAliases) const override; 4766 bool validateAsmConstraint(const char *&Name, 4767 TargetInfo::ConstraintInfo &Info) const override { 4768 switch (*Name) { 4769 default: break; 4770 case 'l': // r0-r7 4771 case 'h': // r8-r15 4772 case 'w': // VFP Floating point register single precision 4773 case 'P': // VFP Floating point register double precision 4774 Info.setAllowsRegister(); 4775 return true; 4776 case 'I': 4777 case 'J': 4778 case 'K': 4779 case 'L': 4780 case 'M': 4781 // FIXME 4782 return true; 4783 case 'Q': // A memory address that is a single base register. 4784 Info.setAllowsMemory(); 4785 return true; 4786 case 'U': // a memory reference... 4787 switch (Name[1]) { 4788 case 'q': // ...ARMV4 ldrsb 4789 case 'v': // ...VFP load/store (reg+constant offset) 4790 case 'y': // ...iWMMXt load/store 4791 case 't': // address valid for load/store opaque types wider 4792 // than 128-bits 4793 case 'n': // valid address for Neon doubleword vector load/store 4794 case 'm': // valid address for Neon element and structure load/store 4795 case 's': // valid address for non-offset loads/stores of quad-word 4796 // values in four ARM registers 4797 Info.setAllowsMemory(); 4798 Name++; 4799 return true; 4800 } 4801 } 4802 return false; 4803 } 4804 std::string convertConstraint(const char *&Constraint) const override { 4805 std::string R; 4806 switch (*Constraint) { 4807 case 'U': // Two-character constraint; add "^" hint for later parsing. 4808 R = std::string("^") + std::string(Constraint, 2); 4809 Constraint++; 4810 break; 4811 case 'p': // 'p' should be translated to 'r' by default. 4812 R = std::string("r"); 4813 break; 4814 default: 4815 return std::string(1, *Constraint); 4816 } 4817 return R; 4818 } 4819 bool 4820 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4821 std::string &SuggestedModifier) const override { 4822 bool isOutput = (Constraint[0] == '='); 4823 bool isInOut = (Constraint[0] == '+'); 4824 4825 // Strip off constraint modifiers. 4826 while (Constraint[0] == '=' || 4827 Constraint[0] == '+' || 4828 Constraint[0] == '&') 4829 Constraint = Constraint.substr(1); 4830 4831 switch (Constraint[0]) { 4832 default: break; 4833 case 'r': { 4834 switch (Modifier) { 4835 default: 4836 return (isInOut || isOutput || Size <= 64); 4837 case 'q': 4838 // A register of size 32 cannot fit a vector type. 4839 return false; 4840 } 4841 } 4842 } 4843 4844 return true; 4845 } 4846 const char *getClobbers() const override { 4847 // FIXME: Is this really right? 4848 return ""; 4849 } 4850 4851 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4852 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4853 } 4854 4855 int getEHDataRegisterNumber(unsigned RegNo) const override { 4856 if (RegNo == 0) return 0; 4857 if (RegNo == 1) return 1; 4858 return -1; 4859 } 4860 4861 bool hasSjLjLowering() const override { 4862 return true; 4863 } 4864 }; 4865 4866 bool ARMTargetInfo::setFPMath(StringRef Name) { 4867 if (Name == "neon") { 4868 FPMath = FP_Neon; 4869 return true; 4870 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4871 Name == "vfp4") { 4872 FPMath = FP_VFP; 4873 return true; 4874 } 4875 return false; 4876 } 4877 4878 const char * const ARMTargetInfo::GCCRegNames[] = { 4879 // Integer registers 4880 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4881 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4882 4883 // Float registers 4884 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4885 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4886 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4887 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4888 4889 // Double registers 4890 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4891 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4892 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4893 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4894 4895 // Quad registers 4896 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4897 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4898 }; 4899 4900 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4901 unsigned &NumNames) const { 4902 Names = GCCRegNames; 4903 NumNames = llvm::array_lengthof(GCCRegNames); 4904 } 4905 4906 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4907 { { "a1" }, "r0" }, 4908 { { "a2" }, "r1" }, 4909 { { "a3" }, "r2" }, 4910 { { "a4" }, "r3" }, 4911 { { "v1" }, "r4" }, 4912 { { "v2" }, "r5" }, 4913 { { "v3" }, "r6" }, 4914 { { "v4" }, "r7" }, 4915 { { "v5" }, "r8" }, 4916 { { "v6", "rfp" }, "r9" }, 4917 { { "sl" }, "r10" }, 4918 { { "fp" }, "r11" }, 4919 { { "ip" }, "r12" }, 4920 { { "r13" }, "sp" }, 4921 { { "r14" }, "lr" }, 4922 { { "r15" }, "pc" }, 4923 // The S, D and Q registers overlap, but aren't really aliases; we 4924 // don't want to substitute one of these for a different-sized one. 4925 }; 4926 4927 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4928 unsigned &NumAliases) const { 4929 Aliases = GCCRegAliases; 4930 NumAliases = llvm::array_lengthof(GCCRegAliases); 4931 } 4932 4933 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4934 #define BUILTIN(ID, TYPE, ATTRS) \ 4935 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 4936 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 4937 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 4938 #include "clang/Basic/BuiltinsNEON.def" 4939 4940 #define BUILTIN(ID, TYPE, ATTRS) \ 4941 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 4942 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 4943 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 4944 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 4945 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 4946 #include "clang/Basic/BuiltinsARM.def" 4947 }; 4948 4949 class ARMleTargetInfo : public ARMTargetInfo { 4950 public: 4951 ARMleTargetInfo(const llvm::Triple &Triple) 4952 : ARMTargetInfo(Triple, false) { } 4953 void getTargetDefines(const LangOptions &Opts, 4954 MacroBuilder &Builder) const override { 4955 Builder.defineMacro("__ARMEL__"); 4956 ARMTargetInfo::getTargetDefines(Opts, Builder); 4957 } 4958 }; 4959 4960 class ARMbeTargetInfo : public ARMTargetInfo { 4961 public: 4962 ARMbeTargetInfo(const llvm::Triple &Triple) 4963 : ARMTargetInfo(Triple, true) { } 4964 void getTargetDefines(const LangOptions &Opts, 4965 MacroBuilder &Builder) const override { 4966 Builder.defineMacro("__ARMEB__"); 4967 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4968 ARMTargetInfo::getTargetDefines(Opts, Builder); 4969 } 4970 }; 4971 4972 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 4973 const llvm::Triple Triple; 4974 public: 4975 WindowsARMTargetInfo(const llvm::Triple &Triple) 4976 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 4977 TLSSupported = false; 4978 WCharType = UnsignedShort; 4979 SizeType = UnsignedInt; 4980 UserLabelPrefix = ""; 4981 } 4982 void getVisualStudioDefines(const LangOptions &Opts, 4983 MacroBuilder &Builder) const { 4984 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 4985 4986 // FIXME: this is invalid for WindowsCE 4987 Builder.defineMacro("_M_ARM_NT", "1"); 4988 Builder.defineMacro("_M_ARMT", "_M_ARM"); 4989 Builder.defineMacro("_M_THUMB", "_M_ARM"); 4990 4991 assert((Triple.getArch() == llvm::Triple::arm || 4992 Triple.getArch() == llvm::Triple::thumb) && 4993 "invalid architecture for Windows ARM target info"); 4994 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 4995 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 4996 4997 // TODO map the complete set of values 4998 // 31: VFPv3 40: VFPv4 4999 Builder.defineMacro("_M_ARM_FP", "31"); 5000 } 5001 BuiltinVaListKind getBuiltinVaListKind() const override { 5002 return TargetInfo::CharPtrBuiltinVaList; 5003 } 5004 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5005 switch (CC) { 5006 case CC_X86StdCall: 5007 case CC_X86ThisCall: 5008 case CC_X86FastCall: 5009 case CC_X86VectorCall: 5010 return CCCR_Ignore; 5011 case CC_C: 5012 return CCCR_OK; 5013 default: 5014 return CCCR_Warning; 5015 } 5016 } 5017 }; 5018 5019 // Windows ARM + Itanium C++ ABI Target 5020 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5021 public: 5022 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 5023 : WindowsARMTargetInfo(Triple) { 5024 TheCXXABI.set(TargetCXXABI::GenericARM); 5025 } 5026 5027 void getTargetDefines(const LangOptions &Opts, 5028 MacroBuilder &Builder) const override { 5029 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5030 5031 if (Opts.MSVCCompat) 5032 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5033 } 5034 }; 5035 5036 // Windows ARM, MS (C++) ABI 5037 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5038 public: 5039 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 5040 : WindowsARMTargetInfo(Triple) { 5041 TheCXXABI.set(TargetCXXABI::Microsoft); 5042 } 5043 5044 void getTargetDefines(const LangOptions &Opts, 5045 MacroBuilder &Builder) const override { 5046 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5047 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5048 } 5049 }; 5050 5051 // ARM MinGW target 5052 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5053 public: 5054 MinGWARMTargetInfo(const llvm::Triple &Triple) 5055 : WindowsARMTargetInfo(Triple) { 5056 TheCXXABI.set(TargetCXXABI::GenericARM); 5057 } 5058 5059 void getTargetDefines(const LangOptions &Opts, 5060 MacroBuilder &Builder) const override { 5061 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5062 DefineStd(Builder, "WIN32", Opts); 5063 DefineStd(Builder, "WINNT", Opts); 5064 Builder.defineMacro("_ARM_"); 5065 addMinGWDefines(Opts, Builder); 5066 } 5067 }; 5068 5069 // ARM Cygwin target 5070 class CygwinARMTargetInfo : public ARMleTargetInfo { 5071 public: 5072 CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) { 5073 TLSSupported = false; 5074 WCharType = UnsignedShort; 5075 DoubleAlign = LongLongAlign = 64; 5076 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 5077 } 5078 void getTargetDefines(const LangOptions &Opts, 5079 MacroBuilder &Builder) const override { 5080 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5081 Builder.defineMacro("_ARM_"); 5082 Builder.defineMacro("__CYGWIN__"); 5083 Builder.defineMacro("__CYGWIN32__"); 5084 DefineStd(Builder, "unix", Opts); 5085 if (Opts.CPlusPlus) 5086 Builder.defineMacro("_GNU_SOURCE"); 5087 } 5088 }; 5089 5090 class DarwinARMTargetInfo : 5091 public DarwinTargetInfo<ARMleTargetInfo> { 5092 protected: 5093 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5094 MacroBuilder &Builder) const override { 5095 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5096 } 5097 5098 public: 5099 DarwinARMTargetInfo(const llvm::Triple &Triple) 5100 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 5101 HasAlignMac68kSupport = true; 5102 // iOS always has 64-bit atomic instructions. 5103 // FIXME: This should be based off of the target features in 5104 // ARMleTargetInfo. 5105 MaxAtomicInlineWidth = 64; 5106 5107 // Darwin on iOS uses a variant of the ARM C++ ABI. 5108 TheCXXABI.set(TargetCXXABI::iOS); 5109 } 5110 }; 5111 5112 class AArch64TargetInfo : public TargetInfo { 5113 virtual void setDataLayoutString() = 0; 5114 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5115 static const char *const GCCRegNames[]; 5116 5117 enum FPUModeEnum { 5118 FPUMode, 5119 NeonMode 5120 }; 5121 5122 unsigned FPU; 5123 unsigned CRC; 5124 unsigned Crypto; 5125 unsigned Unaligned; 5126 5127 static const Builtin::Info BuiltinInfo[]; 5128 5129 std::string ABI; 5130 5131 public: 5132 AArch64TargetInfo(const llvm::Triple &Triple) 5133 : TargetInfo(Triple), ABI("aapcs") { 5134 5135 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5136 WCharType = SignedInt; 5137 5138 // NetBSD apparently prefers consistency across ARM targets to consistency 5139 // across 64-bit targets. 5140 Int64Type = SignedLongLong; 5141 IntMaxType = SignedLongLong; 5142 } else { 5143 WCharType = UnsignedInt; 5144 Int64Type = SignedLong; 5145 IntMaxType = SignedLong; 5146 } 5147 5148 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5149 MaxVectorAlign = 128; 5150 MaxAtomicInlineWidth = 128; 5151 MaxAtomicPromoteWidth = 128; 5152 5153 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5154 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5155 5156 // {} in inline assembly are neon specifiers, not assembly variant 5157 // specifiers. 5158 NoAsmVariants = true; 5159 5160 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5161 // contributes to the alignment of the containing aggregate in the same way 5162 // a plain (non bit-field) member of that type would, without exception for 5163 // zero-sized or anonymous bit-fields." 5164 UseBitFieldTypeAlignment = true; 5165 UseZeroLengthBitfieldAlignment = true; 5166 5167 // AArch64 targets default to using the ARM C++ ABI. 5168 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5169 } 5170 5171 StringRef getABI() const override { return ABI; } 5172 bool setABI(const std::string &Name) override { 5173 if (Name != "aapcs" && Name != "darwinpcs") 5174 return false; 5175 5176 ABI = Name; 5177 return true; 5178 } 5179 5180 bool setCPU(const std::string &Name) override { 5181 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5182 .Case("generic", true) 5183 .Cases("cortex-a53", "cortex-a57", "cortex-a72", true) 5184 .Case("cyclone", true) 5185 .Default(false); 5186 return CPUKnown; 5187 } 5188 5189 void getTargetDefines(const LangOptions &Opts, 5190 MacroBuilder &Builder) const override { 5191 // Target identification. 5192 Builder.defineMacro("__aarch64__"); 5193 5194 // Target properties. 5195 Builder.defineMacro("_LP64"); 5196 Builder.defineMacro("__LP64__"); 5197 5198 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5199 Builder.defineMacro("__ARM_ACLE", "200"); 5200 Builder.defineMacro("__ARM_ARCH", "8"); 5201 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5202 5203 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5204 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5205 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5206 5207 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5208 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5209 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5210 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5211 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5212 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5213 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5214 5215 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5216 5217 // 0xe implies support for half, single and double precision operations. 5218 Builder.defineMacro("__ARM_FP", "0xE"); 5219 5220 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5221 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5222 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5223 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5224 5225 if (Opts.UnsafeFPMath) 5226 Builder.defineMacro("__ARM_FP_FAST", "1"); 5227 5228 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5229 5230 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5231 Opts.ShortEnums ? "1" : "4"); 5232 5233 if (FPU == NeonMode) { 5234 Builder.defineMacro("__ARM_NEON", "1"); 5235 // 64-bit NEON supports half, single and double precision operations. 5236 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5237 } 5238 5239 if (CRC) 5240 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5241 5242 if (Crypto) 5243 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5244 5245 if (Unaligned) 5246 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5247 5248 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5249 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5250 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5251 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5252 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5253 } 5254 5255 void getTargetBuiltins(const Builtin::Info *&Records, 5256 unsigned &NumRecords) const override { 5257 Records = BuiltinInfo; 5258 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin; 5259 } 5260 5261 bool hasFeature(StringRef Feature) const override { 5262 return Feature == "aarch64" || 5263 Feature == "arm64" || 5264 Feature == "arm" || 5265 (Feature == "neon" && FPU == NeonMode); 5266 } 5267 5268 bool handleTargetFeatures(std::vector<std::string> &Features, 5269 DiagnosticsEngine &Diags) override { 5270 FPU = FPUMode; 5271 CRC = 0; 5272 Crypto = 0; 5273 Unaligned = 1; 5274 5275 for (const auto &Feature : Features) { 5276 if (Feature == "+neon") 5277 FPU = NeonMode; 5278 if (Feature == "+crc") 5279 CRC = 1; 5280 if (Feature == "+crypto") 5281 Crypto = 1; 5282 if (Feature == "+strict-align") 5283 Unaligned = 0; 5284 } 5285 5286 setDataLayoutString(); 5287 5288 return true; 5289 } 5290 5291 bool isCLZForZeroUndef() const override { return false; } 5292 5293 BuiltinVaListKind getBuiltinVaListKind() const override { 5294 return TargetInfo::AArch64ABIBuiltinVaList; 5295 } 5296 5297 void getGCCRegNames(const char *const *&Names, 5298 unsigned &NumNames) const override; 5299 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5300 unsigned &NumAliases) const override; 5301 5302 bool validateAsmConstraint(const char *&Name, 5303 TargetInfo::ConstraintInfo &Info) const override { 5304 switch (*Name) { 5305 default: 5306 return false; 5307 case 'w': // Floating point and SIMD registers (V0-V31) 5308 Info.setAllowsRegister(); 5309 return true; 5310 case 'I': // Constant that can be used with an ADD instruction 5311 case 'J': // Constant that can be used with a SUB instruction 5312 case 'K': // Constant that can be used with a 32-bit logical instruction 5313 case 'L': // Constant that can be used with a 64-bit logical instruction 5314 case 'M': // Constant that can be used as a 32-bit MOV immediate 5315 case 'N': // Constant that can be used as a 64-bit MOV immediate 5316 case 'Y': // Floating point constant zero 5317 case 'Z': // Integer constant zero 5318 return true; 5319 case 'Q': // A memory reference with base register and no offset 5320 Info.setAllowsMemory(); 5321 return true; 5322 case 'S': // A symbolic address 5323 Info.setAllowsRegister(); 5324 return true; 5325 case 'U': 5326 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5327 // Utf: A memory address suitable for ldp/stp in TF mode. 5328 // Usa: An absolute symbolic address. 5329 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5330 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5331 case 'z': // Zero register, wzr or xzr 5332 Info.setAllowsRegister(); 5333 return true; 5334 case 'x': // Floating point and SIMD registers (V0-V15) 5335 Info.setAllowsRegister(); 5336 return true; 5337 } 5338 return false; 5339 } 5340 5341 bool 5342 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5343 std::string &SuggestedModifier) const override { 5344 // Strip off constraint modifiers. 5345 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5346 Constraint = Constraint.substr(1); 5347 5348 switch (Constraint[0]) { 5349 default: 5350 return true; 5351 case 'z': 5352 case 'r': { 5353 switch (Modifier) { 5354 case 'x': 5355 case 'w': 5356 // For now assume that the person knows what they're 5357 // doing with the modifier. 5358 return true; 5359 default: 5360 // By default an 'r' constraint will be in the 'x' 5361 // registers. 5362 if (Size == 64) 5363 return true; 5364 5365 SuggestedModifier = "w"; 5366 return false; 5367 } 5368 } 5369 } 5370 } 5371 5372 const char *getClobbers() const override { return ""; } 5373 5374 int getEHDataRegisterNumber(unsigned RegNo) const override { 5375 if (RegNo == 0) 5376 return 0; 5377 if (RegNo == 1) 5378 return 1; 5379 return -1; 5380 } 5381 }; 5382 5383 const char *const AArch64TargetInfo::GCCRegNames[] = { 5384 // 32-bit Integer registers 5385 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5386 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5387 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5388 5389 // 64-bit Integer registers 5390 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5391 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5392 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5393 5394 // 32-bit floating point regsisters 5395 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5396 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5397 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5398 5399 // 64-bit floating point regsisters 5400 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5401 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5402 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5403 5404 // Vector registers 5405 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5406 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5407 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5408 }; 5409 5410 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names, 5411 unsigned &NumNames) const { 5412 Names = GCCRegNames; 5413 NumNames = llvm::array_lengthof(GCCRegNames); 5414 } 5415 5416 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5417 { { "w31" }, "wsp" }, 5418 { { "x29" }, "fp" }, 5419 { { "x30" }, "lr" }, 5420 { { "x31" }, "sp" }, 5421 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5422 // don't want to substitute one of these for a different-sized one. 5423 }; 5424 5425 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5426 unsigned &NumAliases) const { 5427 Aliases = GCCRegAliases; 5428 NumAliases = llvm::array_lengthof(GCCRegAliases); 5429 } 5430 5431 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5432 #define BUILTIN(ID, TYPE, ATTRS) \ 5433 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5434 #include "clang/Basic/BuiltinsNEON.def" 5435 5436 #define BUILTIN(ID, TYPE, ATTRS) \ 5437 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5438 #include "clang/Basic/BuiltinsAArch64.def" 5439 }; 5440 5441 class AArch64leTargetInfo : public AArch64TargetInfo { 5442 void setDataLayoutString() override { 5443 if (getTriple().isOSBinFormatMachO()) 5444 DataLayoutString = "e-m:o-i64:64-i128:128-n32:64-S128"; 5445 else 5446 DataLayoutString = "e-m:e-i64:64-i128:128-n32:64-S128"; 5447 } 5448 5449 public: 5450 AArch64leTargetInfo(const llvm::Triple &Triple) 5451 : AArch64TargetInfo(Triple) { 5452 BigEndian = false; 5453 } 5454 void getTargetDefines(const LangOptions &Opts, 5455 MacroBuilder &Builder) const override { 5456 Builder.defineMacro("__AARCH64EL__"); 5457 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5458 } 5459 }; 5460 5461 class AArch64beTargetInfo : public AArch64TargetInfo { 5462 void setDataLayoutString() override { 5463 assert(!getTriple().isOSBinFormatMachO()); 5464 DataLayoutString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5465 } 5466 5467 public: 5468 AArch64beTargetInfo(const llvm::Triple &Triple) 5469 : AArch64TargetInfo(Triple) { } 5470 void getTargetDefines(const LangOptions &Opts, 5471 MacroBuilder &Builder) const override { 5472 Builder.defineMacro("__AARCH64EB__"); 5473 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5474 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5475 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5476 } 5477 }; 5478 5479 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5480 protected: 5481 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5482 MacroBuilder &Builder) const override { 5483 Builder.defineMacro("__AARCH64_SIMD__"); 5484 Builder.defineMacro("__ARM64_ARCH_8__"); 5485 Builder.defineMacro("__ARM_NEON__"); 5486 Builder.defineMacro("__LITTLE_ENDIAN__"); 5487 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5488 Builder.defineMacro("__arm64", "1"); 5489 Builder.defineMacro("__arm64__", "1"); 5490 5491 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5492 } 5493 5494 public: 5495 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5496 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5497 Int64Type = SignedLongLong; 5498 WCharType = SignedInt; 5499 UseSignedCharForObjCBool = false; 5500 5501 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5502 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5503 5504 TheCXXABI.set(TargetCXXABI::iOS64); 5505 } 5506 5507 BuiltinVaListKind getBuiltinVaListKind() const override { 5508 return TargetInfo::CharPtrBuiltinVaList; 5509 } 5510 }; 5511 5512 // Hexagon abstract base class 5513 class HexagonTargetInfo : public TargetInfo { 5514 static const Builtin::Info BuiltinInfo[]; 5515 static const char * const GCCRegNames[]; 5516 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5517 std::string CPU; 5518 public: 5519 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5520 BigEndian = false; 5521 DataLayoutString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 5522 5523 // {} in inline assembly are packet specifiers, not assembly variant 5524 // specifiers. 5525 NoAsmVariants = true; 5526 } 5527 5528 void getTargetBuiltins(const Builtin::Info *&Records, 5529 unsigned &NumRecords) const override { 5530 Records = BuiltinInfo; 5531 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 5532 } 5533 5534 bool validateAsmConstraint(const char *&Name, 5535 TargetInfo::ConstraintInfo &Info) const override { 5536 return true; 5537 } 5538 5539 void getTargetDefines(const LangOptions &Opts, 5540 MacroBuilder &Builder) const override; 5541 5542 bool hasFeature(StringRef Feature) const override { 5543 return Feature == "hexagon"; 5544 } 5545 5546 BuiltinVaListKind getBuiltinVaListKind() const override { 5547 return TargetInfo::CharPtrBuiltinVaList; 5548 } 5549 void getGCCRegNames(const char * const *&Names, 5550 unsigned &NumNames) const override; 5551 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5552 unsigned &NumAliases) const override; 5553 const char *getClobbers() const override { 5554 return ""; 5555 } 5556 5557 static const char *getHexagonCPUSuffix(StringRef Name) { 5558 return llvm::StringSwitch<const char*>(Name) 5559 .Case("hexagonv4", "4") 5560 .Case("hexagonv5", "5") 5561 .Default(nullptr); 5562 } 5563 5564 bool setCPU(const std::string &Name) override { 5565 if (!getHexagonCPUSuffix(Name)) 5566 return false; 5567 5568 CPU = Name; 5569 return true; 5570 } 5571 }; 5572 5573 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5574 MacroBuilder &Builder) const { 5575 Builder.defineMacro("qdsp6"); 5576 Builder.defineMacro("__qdsp6", "1"); 5577 Builder.defineMacro("__qdsp6__", "1"); 5578 5579 Builder.defineMacro("hexagon"); 5580 Builder.defineMacro("__hexagon", "1"); 5581 Builder.defineMacro("__hexagon__", "1"); 5582 5583 if(CPU == "hexagonv1") { 5584 Builder.defineMacro("__HEXAGON_V1__"); 5585 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 5586 if(Opts.HexagonQdsp6Compat) { 5587 Builder.defineMacro("__QDSP6_V1__"); 5588 Builder.defineMacro("__QDSP6_ARCH__", "1"); 5589 } 5590 } 5591 else if(CPU == "hexagonv2") { 5592 Builder.defineMacro("__HEXAGON_V2__"); 5593 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 5594 if(Opts.HexagonQdsp6Compat) { 5595 Builder.defineMacro("__QDSP6_V2__"); 5596 Builder.defineMacro("__QDSP6_ARCH__", "2"); 5597 } 5598 } 5599 else if(CPU == "hexagonv3") { 5600 Builder.defineMacro("__HEXAGON_V3__"); 5601 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 5602 if(Opts.HexagonQdsp6Compat) { 5603 Builder.defineMacro("__QDSP6_V3__"); 5604 Builder.defineMacro("__QDSP6_ARCH__", "3"); 5605 } 5606 } 5607 else if(CPU == "hexagonv4") { 5608 Builder.defineMacro("__HEXAGON_V4__"); 5609 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5610 if(Opts.HexagonQdsp6Compat) { 5611 Builder.defineMacro("__QDSP6_V4__"); 5612 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5613 } 5614 } 5615 else if(CPU == "hexagonv5") { 5616 Builder.defineMacro("__HEXAGON_V5__"); 5617 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5618 if(Opts.HexagonQdsp6Compat) { 5619 Builder.defineMacro("__QDSP6_V5__"); 5620 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5621 } 5622 } 5623 } 5624 5625 const char * const HexagonTargetInfo::GCCRegNames[] = { 5626 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5627 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5628 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5629 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5630 "p0", "p1", "p2", "p3", 5631 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5632 }; 5633 5634 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 5635 unsigned &NumNames) const { 5636 Names = GCCRegNames; 5637 NumNames = llvm::array_lengthof(GCCRegNames); 5638 } 5639 5640 5641 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5642 { { "sp" }, "r29" }, 5643 { { "fp" }, "r30" }, 5644 { { "lr" }, "r31" }, 5645 }; 5646 5647 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5648 unsigned &NumAliases) const { 5649 Aliases = GCCRegAliases; 5650 NumAliases = llvm::array_lengthof(GCCRegAliases); 5651 } 5652 5653 5654 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5655 #define BUILTIN(ID, TYPE, ATTRS) \ 5656 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5657 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5658 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5659 #include "clang/Basic/BuiltinsHexagon.def" 5660 }; 5661 5662 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5663 class SparcTargetInfo : public TargetInfo { 5664 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5665 static const char * const GCCRegNames[]; 5666 bool SoftFloat; 5667 public: 5668 SparcTargetInfo(const llvm::Triple &Triple) 5669 : TargetInfo(Triple), SoftFloat(false) {} 5670 5671 bool handleTargetFeatures(std::vector<std::string> &Features, 5672 DiagnosticsEngine &Diags) override { 5673 // The backend doesn't actually handle soft float yet, but in case someone 5674 // is using the support for the front end continue to support it. 5675 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 5676 if (Feature != Features.end()) { 5677 SoftFloat = true; 5678 Features.erase(Feature); 5679 } 5680 return true; 5681 } 5682 void getTargetDefines(const LangOptions &Opts, 5683 MacroBuilder &Builder) const override { 5684 DefineStd(Builder, "sparc", Opts); 5685 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5686 5687 if (SoftFloat) 5688 Builder.defineMacro("SOFT_FLOAT", "1"); 5689 } 5690 5691 bool hasFeature(StringRef Feature) const override { 5692 return llvm::StringSwitch<bool>(Feature) 5693 .Case("softfloat", SoftFloat) 5694 .Case("sparc", true) 5695 .Default(false); 5696 } 5697 5698 void getTargetBuiltins(const Builtin::Info *&Records, 5699 unsigned &NumRecords) const override { 5700 // FIXME: Implement! 5701 } 5702 BuiltinVaListKind getBuiltinVaListKind() const override { 5703 return TargetInfo::VoidPtrBuiltinVaList; 5704 } 5705 void getGCCRegNames(const char * const *&Names, 5706 unsigned &NumNames) const override; 5707 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5708 unsigned &NumAliases) const override; 5709 bool validateAsmConstraint(const char *&Name, 5710 TargetInfo::ConstraintInfo &info) const override { 5711 // FIXME: Implement! 5712 switch (*Name) { 5713 case 'I': // Signed 13-bit constant 5714 case 'J': // Zero 5715 case 'K': // 32-bit constant with the low 12 bits clear 5716 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5717 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5718 case 'N': // Same as 'K' but zext (required for SIMode) 5719 case 'O': // The constant 4096 5720 return true; 5721 } 5722 return false; 5723 } 5724 const char *getClobbers() const override { 5725 // FIXME: Implement! 5726 return ""; 5727 } 5728 }; 5729 5730 const char * const SparcTargetInfo::GCCRegNames[] = { 5731 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5732 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5733 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5734 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5735 }; 5736 5737 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 5738 unsigned &NumNames) const { 5739 Names = GCCRegNames; 5740 NumNames = llvm::array_lengthof(GCCRegNames); 5741 } 5742 5743 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5744 { { "g0" }, "r0" }, 5745 { { "g1" }, "r1" }, 5746 { { "g2" }, "r2" }, 5747 { { "g3" }, "r3" }, 5748 { { "g4" }, "r4" }, 5749 { { "g5" }, "r5" }, 5750 { { "g6" }, "r6" }, 5751 { { "g7" }, "r7" }, 5752 { { "o0" }, "r8" }, 5753 { { "o1" }, "r9" }, 5754 { { "o2" }, "r10" }, 5755 { { "o3" }, "r11" }, 5756 { { "o4" }, "r12" }, 5757 { { "o5" }, "r13" }, 5758 { { "o6", "sp" }, "r14" }, 5759 { { "o7" }, "r15" }, 5760 { { "l0" }, "r16" }, 5761 { { "l1" }, "r17" }, 5762 { { "l2" }, "r18" }, 5763 { { "l3" }, "r19" }, 5764 { { "l4" }, "r20" }, 5765 { { "l5" }, "r21" }, 5766 { { "l6" }, "r22" }, 5767 { { "l7" }, "r23" }, 5768 { { "i0" }, "r24" }, 5769 { { "i1" }, "r25" }, 5770 { { "i2" }, "r26" }, 5771 { { "i3" }, "r27" }, 5772 { { "i4" }, "r28" }, 5773 { { "i5" }, "r29" }, 5774 { { "i6", "fp" }, "r30" }, 5775 { { "i7" }, "r31" }, 5776 }; 5777 5778 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5779 unsigned &NumAliases) const { 5780 Aliases = GCCRegAliases; 5781 NumAliases = llvm::array_lengthof(GCCRegAliases); 5782 } 5783 5784 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5785 class SparcV8TargetInfo : public SparcTargetInfo { 5786 public: 5787 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5788 DataLayoutString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5789 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 5790 switch (getTriple().getOS()) { 5791 default: 5792 SizeType = UnsignedInt; 5793 IntPtrType = SignedInt; 5794 PtrDiffType = SignedInt; 5795 break; 5796 case llvm::Triple::NetBSD: 5797 case llvm::Triple::OpenBSD: 5798 SizeType = UnsignedLong; 5799 IntPtrType = SignedLong; 5800 PtrDiffType = SignedLong; 5801 break; 5802 } 5803 } 5804 5805 void getTargetDefines(const LangOptions &Opts, 5806 MacroBuilder &Builder) const override { 5807 SparcTargetInfo::getTargetDefines(Opts, Builder); 5808 Builder.defineMacro("__sparcv8"); 5809 } 5810 }; 5811 5812 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 5813 class SparcV8elTargetInfo : public SparcV8TargetInfo { 5814 public: 5815 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 5816 DataLayoutString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5817 BigEndian = false; 5818 } 5819 }; 5820 5821 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 5822 class SparcV9TargetInfo : public SparcTargetInfo { 5823 public: 5824 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5825 // FIXME: Support Sparc quad-precision long double? 5826 DataLayoutString = "E-m:e-i64:64-n32:64-S128"; 5827 // This is an LP64 platform. 5828 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5829 5830 // OpenBSD uses long long for int64_t and intmax_t. 5831 if (getTriple().getOS() == llvm::Triple::OpenBSD) 5832 IntMaxType = SignedLongLong; 5833 else 5834 IntMaxType = SignedLong; 5835 Int64Type = IntMaxType; 5836 5837 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 5838 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 5839 LongDoubleWidth = 128; 5840 LongDoubleAlign = 128; 5841 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5842 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5843 } 5844 5845 void getTargetDefines(const LangOptions &Opts, 5846 MacroBuilder &Builder) const override { 5847 SparcTargetInfo::getTargetDefines(Opts, Builder); 5848 Builder.defineMacro("__sparcv9"); 5849 Builder.defineMacro("__arch64__"); 5850 // Solaris doesn't need these variants, but the BSDs do. 5851 if (getTriple().getOS() != llvm::Triple::Solaris) { 5852 Builder.defineMacro("__sparc64__"); 5853 Builder.defineMacro("__sparc_v9__"); 5854 Builder.defineMacro("__sparcv9__"); 5855 } 5856 } 5857 5858 bool setCPU(const std::string &Name) override { 5859 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5860 .Case("v9", true) 5861 .Case("ultrasparc", true) 5862 .Case("ultrasparc3", true) 5863 .Case("niagara", true) 5864 .Case("niagara2", true) 5865 .Case("niagara3", true) 5866 .Case("niagara4", true) 5867 .Default(false); 5868 5869 // No need to store the CPU yet. There aren't any CPU-specific 5870 // macros to define. 5871 return CPUKnown; 5872 } 5873 }; 5874 5875 class SystemZTargetInfo : public TargetInfo { 5876 static const Builtin::Info BuiltinInfo[]; 5877 static const char *const GCCRegNames[]; 5878 std::string CPU; 5879 bool HasTransactionalExecution; 5880 bool HasVector; 5881 5882 public: 5883 SystemZTargetInfo(const llvm::Triple &Triple) 5884 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 5885 HasVector(false) { 5886 IntMaxType = SignedLong; 5887 Int64Type = SignedLong; 5888 TLSSupported = true; 5889 IntWidth = IntAlign = 32; 5890 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5891 PointerWidth = PointerAlign = 64; 5892 LongDoubleWidth = 128; 5893 LongDoubleAlign = 64; 5894 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5895 DefaultAlignForAttributeAligned = 64; 5896 MinGlobalAlign = 16; 5897 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5898 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5899 } 5900 void getTargetDefines(const LangOptions &Opts, 5901 MacroBuilder &Builder) const override { 5902 Builder.defineMacro("__s390__"); 5903 Builder.defineMacro("__s390x__"); 5904 Builder.defineMacro("__zarch__"); 5905 Builder.defineMacro("__LONG_DOUBLE_128__"); 5906 if (HasTransactionalExecution) 5907 Builder.defineMacro("__HTM__"); 5908 if (Opts.ZVector) 5909 Builder.defineMacro("__VEC__", "10301"); 5910 } 5911 void getTargetBuiltins(const Builtin::Info *&Records, 5912 unsigned &NumRecords) const override { 5913 Records = BuiltinInfo; 5914 NumRecords = clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin; 5915 } 5916 5917 void getGCCRegNames(const char *const *&Names, 5918 unsigned &NumNames) const override; 5919 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5920 unsigned &NumAliases) const override { 5921 // No aliases. 5922 Aliases = nullptr; 5923 NumAliases = 0; 5924 } 5925 bool validateAsmConstraint(const char *&Name, 5926 TargetInfo::ConstraintInfo &info) const override; 5927 const char *getClobbers() const override { 5928 // FIXME: Is this really right? 5929 return ""; 5930 } 5931 BuiltinVaListKind getBuiltinVaListKind() const override { 5932 return TargetInfo::SystemZBuiltinVaList; 5933 } 5934 bool setCPU(const std::string &Name) override { 5935 CPU = Name; 5936 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5937 .Case("z10", true) 5938 .Case("z196", true) 5939 .Case("zEC12", true) 5940 .Case("z13", true) 5941 .Default(false); 5942 5943 return CPUKnown; 5944 } 5945 bool 5946 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5947 StringRef CPU, 5948 const std::vector<std::string> &FeaturesVec) const override { 5949 if (CPU == "zEC12") 5950 Features["transactional-execution"] = true; 5951 if (CPU == "z13") { 5952 Features["transactional-execution"] = true; 5953 Features["vector"] = true; 5954 } 5955 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5956 } 5957 5958 bool handleTargetFeatures(std::vector<std::string> &Features, 5959 DiagnosticsEngine &Diags) override { 5960 HasTransactionalExecution = false; 5961 for (const auto &Feature : Features) { 5962 if (Feature == "+transactional-execution") 5963 HasTransactionalExecution = true; 5964 else if (Feature == "+vector") 5965 HasVector = true; 5966 } 5967 // If we use the vector ABI, vector types are 64-bit aligned. 5968 if (HasVector) { 5969 MaxVectorAlign = 64; 5970 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 5971 "-v128:64-a:8:16-n32:64"; 5972 } 5973 return true; 5974 } 5975 5976 bool hasFeature(StringRef Feature) const override { 5977 return llvm::StringSwitch<bool>(Feature) 5978 .Case("systemz", true) 5979 .Case("htm", HasTransactionalExecution) 5980 .Case("vx", HasVector) 5981 .Default(false); 5982 } 5983 5984 StringRef getABI() const override { 5985 if (HasVector) 5986 return "vector"; 5987 return ""; 5988 } 5989 5990 bool useFloat128ManglingForLongDouble() const override { 5991 return true; 5992 } 5993 }; 5994 5995 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 5996 #define BUILTIN(ID, TYPE, ATTRS) \ 5997 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5998 #include "clang/Basic/BuiltinsSystemZ.def" 5999 }; 6000 6001 const char *const SystemZTargetInfo::GCCRegNames[] = { 6002 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6003 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6004 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6005 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6006 }; 6007 6008 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 6009 unsigned &NumNames) const { 6010 Names = GCCRegNames; 6011 NumNames = llvm::array_lengthof(GCCRegNames); 6012 } 6013 6014 bool SystemZTargetInfo:: 6015 validateAsmConstraint(const char *&Name, 6016 TargetInfo::ConstraintInfo &Info) const { 6017 switch (*Name) { 6018 default: 6019 return false; 6020 6021 case 'a': // Address register 6022 case 'd': // Data register (equivalent to 'r') 6023 case 'f': // Floating-point register 6024 Info.setAllowsRegister(); 6025 return true; 6026 6027 case 'I': // Unsigned 8-bit constant 6028 case 'J': // Unsigned 12-bit constant 6029 case 'K': // Signed 16-bit constant 6030 case 'L': // Signed 20-bit displacement (on all targets we support) 6031 case 'M': // 0x7fffffff 6032 return true; 6033 6034 case 'Q': // Memory with base and unsigned 12-bit displacement 6035 case 'R': // Likewise, plus an index 6036 case 'S': // Memory with base and signed 20-bit displacement 6037 case 'T': // Likewise, plus an index 6038 Info.setAllowsMemory(); 6039 return true; 6040 } 6041 } 6042 6043 class MSP430TargetInfo : public TargetInfo { 6044 static const char *const GCCRegNames[]; 6045 6046 public: 6047 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6048 BigEndian = false; 6049 TLSSupported = false; 6050 IntWidth = 16; 6051 IntAlign = 16; 6052 LongWidth = 32; 6053 LongLongWidth = 64; 6054 LongAlign = LongLongAlign = 16; 6055 PointerWidth = 16; 6056 PointerAlign = 16; 6057 SuitableAlign = 16; 6058 SizeType = UnsignedInt; 6059 IntMaxType = SignedLongLong; 6060 IntPtrType = SignedInt; 6061 PtrDiffType = SignedInt; 6062 SigAtomicType = SignedLong; 6063 DataLayoutString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 6064 } 6065 void getTargetDefines(const LangOptions &Opts, 6066 MacroBuilder &Builder) const override { 6067 Builder.defineMacro("MSP430"); 6068 Builder.defineMacro("__MSP430__"); 6069 // FIXME: defines for different 'flavours' of MCU 6070 } 6071 void getTargetBuiltins(const Builtin::Info *&Records, 6072 unsigned &NumRecords) const override { 6073 // FIXME: Implement. 6074 Records = nullptr; 6075 NumRecords = 0; 6076 } 6077 bool hasFeature(StringRef Feature) const override { 6078 return Feature == "msp430"; 6079 } 6080 void getGCCRegNames(const char *const *&Names, 6081 unsigned &NumNames) const override; 6082 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6083 unsigned &NumAliases) const override { 6084 // No aliases. 6085 Aliases = nullptr; 6086 NumAliases = 0; 6087 } 6088 bool validateAsmConstraint(const char *&Name, 6089 TargetInfo::ConstraintInfo &info) const override { 6090 // FIXME: implement 6091 switch (*Name) { 6092 case 'K': // the constant 1 6093 case 'L': // constant -1^20 .. 1^19 6094 case 'M': // constant 1-4: 6095 return true; 6096 } 6097 // No target constraints for now. 6098 return false; 6099 } 6100 const char *getClobbers() const override { 6101 // FIXME: Is this really right? 6102 return ""; 6103 } 6104 BuiltinVaListKind getBuiltinVaListKind() const override { 6105 // FIXME: implement 6106 return TargetInfo::CharPtrBuiltinVaList; 6107 } 6108 }; 6109 6110 const char *const MSP430TargetInfo::GCCRegNames[] = { 6111 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6112 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6113 6114 void MSP430TargetInfo::getGCCRegNames(const char *const *&Names, 6115 unsigned &NumNames) const { 6116 Names = GCCRegNames; 6117 NumNames = llvm::array_lengthof(GCCRegNames); 6118 } 6119 6120 // LLVM and Clang cannot be used directly to output native binaries for 6121 // target, but is used to compile C code to llvm bitcode with correct 6122 // type and alignment information. 6123 // 6124 // TCE uses the llvm bitcode as input and uses it for generating customized 6125 // target processor and program binary. TCE co-design environment is 6126 // publicly available in http://tce.cs.tut.fi 6127 6128 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6129 3, // opencl_global 6130 4, // opencl_local 6131 5, // opencl_constant 6132 // FIXME: generic has to be added to the target 6133 0, // opencl_generic 6134 0, // cuda_device 6135 0, // cuda_constant 6136 0 // cuda_shared 6137 }; 6138 6139 class TCETargetInfo : public TargetInfo { 6140 public: 6141 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6142 TLSSupported = false; 6143 IntWidth = 32; 6144 LongWidth = LongLongWidth = 32; 6145 PointerWidth = 32; 6146 IntAlign = 32; 6147 LongAlign = LongLongAlign = 32; 6148 PointerAlign = 32; 6149 SuitableAlign = 32; 6150 SizeType = UnsignedInt; 6151 IntMaxType = SignedLong; 6152 IntPtrType = SignedInt; 6153 PtrDiffType = SignedInt; 6154 FloatWidth = 32; 6155 FloatAlign = 32; 6156 DoubleWidth = 32; 6157 DoubleAlign = 32; 6158 LongDoubleWidth = 32; 6159 LongDoubleAlign = 32; 6160 FloatFormat = &llvm::APFloat::IEEEsingle; 6161 DoubleFormat = &llvm::APFloat::IEEEsingle; 6162 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6163 DataLayoutString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 6164 "-f64:32-v64:32-v128:32-a:0:32-n32"; 6165 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6166 UseAddrSpaceMapMangling = true; 6167 } 6168 6169 void getTargetDefines(const LangOptions &Opts, 6170 MacroBuilder &Builder) const override { 6171 DefineStd(Builder, "tce", Opts); 6172 Builder.defineMacro("__TCE__"); 6173 Builder.defineMacro("__TCE_V1__"); 6174 } 6175 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 6176 6177 void getTargetBuiltins(const Builtin::Info *&Records, 6178 unsigned &NumRecords) const override {} 6179 const char *getClobbers() const override { return ""; } 6180 BuiltinVaListKind getBuiltinVaListKind() const override { 6181 return TargetInfo::VoidPtrBuiltinVaList; 6182 } 6183 void getGCCRegNames(const char *const *&Names, 6184 unsigned &NumNames) const override {} 6185 bool validateAsmConstraint(const char *&Name, 6186 TargetInfo::ConstraintInfo &info) const override { 6187 return true; 6188 } 6189 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6190 unsigned &NumAliases) const override {} 6191 }; 6192 6193 class BPFTargetInfo : public TargetInfo { 6194 public: 6195 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6196 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6197 SizeType = UnsignedLong; 6198 PtrDiffType = SignedLong; 6199 IntPtrType = SignedLong; 6200 IntMaxType = SignedLong; 6201 Int64Type = SignedLong; 6202 RegParmMax = 5; 6203 if (Triple.getArch() == llvm::Triple::bpfeb) { 6204 BigEndian = true; 6205 DataLayoutString = "E-m:e-p:64:64-i64:64-n32:64-S128"; 6206 } else { 6207 BigEndian = false; 6208 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 6209 } 6210 MaxAtomicPromoteWidth = 64; 6211 MaxAtomicInlineWidth = 64; 6212 TLSSupported = false; 6213 } 6214 void getTargetDefines(const LangOptions &Opts, 6215 MacroBuilder &Builder) const override { 6216 DefineStd(Builder, "bpf", Opts); 6217 Builder.defineMacro("__BPF__"); 6218 } 6219 bool hasFeature(StringRef Feature) const override { 6220 return Feature == "bpf"; 6221 } 6222 6223 void getTargetBuiltins(const Builtin::Info *&Records, 6224 unsigned &NumRecords) const override {} 6225 const char *getClobbers() const override { 6226 return ""; 6227 } 6228 BuiltinVaListKind getBuiltinVaListKind() const override { 6229 return TargetInfo::VoidPtrBuiltinVaList; 6230 } 6231 void getGCCRegNames(const char * const *&Names, 6232 unsigned &NumNames) const override { 6233 Names = nullptr; 6234 NumNames = 0; 6235 } 6236 bool validateAsmConstraint(const char *&Name, 6237 TargetInfo::ConstraintInfo &info) const override { 6238 return true; 6239 } 6240 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6241 unsigned &NumAliases) const override { 6242 Aliases = nullptr; 6243 NumAliases = 0; 6244 } 6245 }; 6246 6247 class MipsTargetInfoBase : public TargetInfo { 6248 virtual void setDataLayoutString() = 0; 6249 6250 static const Builtin::Info BuiltinInfo[]; 6251 std::string CPU; 6252 bool IsMips16; 6253 bool IsMicromips; 6254 bool IsNan2008; 6255 bool IsSingleFloat; 6256 enum MipsFloatABI { 6257 HardFloat, SoftFloat 6258 } FloatABI; 6259 enum DspRevEnum { 6260 NoDSP, DSP1, DSP2 6261 } DspRev; 6262 bool HasMSA; 6263 6264 protected: 6265 bool HasFP64; 6266 std::string ABI; 6267 6268 public: 6269 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 6270 const std::string &CPUStr) 6271 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6272 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6273 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6274 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6275 } 6276 6277 bool isNaN2008Default() const { 6278 return CPU == "mips32r6" || CPU == "mips64r6"; 6279 } 6280 6281 bool isFP64Default() const { 6282 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6283 } 6284 6285 bool isNan2008() const override { 6286 return IsNan2008; 6287 } 6288 6289 StringRef getABI() const override { return ABI; } 6290 bool setCPU(const std::string &Name) override { 6291 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6292 getTriple().getArch() == llvm::Triple::mipsel; 6293 CPU = Name; 6294 return llvm::StringSwitch<bool>(Name) 6295 .Case("mips1", IsMips32) 6296 .Case("mips2", IsMips32) 6297 .Case("mips3", true) 6298 .Case("mips4", true) 6299 .Case("mips5", true) 6300 .Case("mips32", IsMips32) 6301 .Case("mips32r2", IsMips32) 6302 .Case("mips32r3", IsMips32) 6303 .Case("mips32r5", IsMips32) 6304 .Case("mips32r6", IsMips32) 6305 .Case("mips64", true) 6306 .Case("mips64r2", true) 6307 .Case("mips64r3", true) 6308 .Case("mips64r5", true) 6309 .Case("mips64r6", true) 6310 .Case("octeon", true) 6311 .Case("p5600", true) 6312 .Default(false); 6313 } 6314 const std::string& getCPU() const { return CPU; } 6315 bool 6316 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6317 StringRef CPU, 6318 const std::vector<std::string> &FeaturesVec) const override { 6319 if (CPU == "octeon") 6320 Features["mips64r2"] = Features["cnmips"] = true; 6321 else 6322 Features[CPU] = true; 6323 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6324 } 6325 6326 void getTargetDefines(const LangOptions &Opts, 6327 MacroBuilder &Builder) const override { 6328 Builder.defineMacro("__mips__"); 6329 Builder.defineMacro("_mips"); 6330 if (Opts.GNUMode) 6331 Builder.defineMacro("mips"); 6332 6333 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6334 6335 switch (FloatABI) { 6336 case HardFloat: 6337 Builder.defineMacro("__mips_hard_float", Twine(1)); 6338 break; 6339 case SoftFloat: 6340 Builder.defineMacro("__mips_soft_float", Twine(1)); 6341 break; 6342 } 6343 6344 if (IsSingleFloat) 6345 Builder.defineMacro("__mips_single_float", Twine(1)); 6346 6347 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6348 Builder.defineMacro("_MIPS_FPSET", 6349 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6350 6351 if (IsMips16) 6352 Builder.defineMacro("__mips16", Twine(1)); 6353 6354 if (IsMicromips) 6355 Builder.defineMacro("__mips_micromips", Twine(1)); 6356 6357 if (IsNan2008) 6358 Builder.defineMacro("__mips_nan2008", Twine(1)); 6359 6360 switch (DspRev) { 6361 default: 6362 break; 6363 case DSP1: 6364 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6365 Builder.defineMacro("__mips_dsp", Twine(1)); 6366 break; 6367 case DSP2: 6368 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6369 Builder.defineMacro("__mips_dspr2", Twine(1)); 6370 Builder.defineMacro("__mips_dsp", Twine(1)); 6371 break; 6372 } 6373 6374 if (HasMSA) 6375 Builder.defineMacro("__mips_msa", Twine(1)); 6376 6377 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6378 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6379 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6380 6381 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6382 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6383 } 6384 6385 void getTargetBuiltins(const Builtin::Info *&Records, 6386 unsigned &NumRecords) const override { 6387 Records = BuiltinInfo; 6388 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 6389 } 6390 bool hasFeature(StringRef Feature) const override { 6391 return llvm::StringSwitch<bool>(Feature) 6392 .Case("mips", true) 6393 .Case("fp64", HasFP64) 6394 .Default(false); 6395 } 6396 BuiltinVaListKind getBuiltinVaListKind() const override { 6397 return TargetInfo::VoidPtrBuiltinVaList; 6398 } 6399 void getGCCRegNames(const char * const *&Names, 6400 unsigned &NumNames) const override { 6401 static const char *const GCCRegNames[] = { 6402 // CPU register names 6403 // Must match second column of GCCRegAliases 6404 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6405 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6406 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6407 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6408 // Floating point register names 6409 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6410 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6411 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6412 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6413 // Hi/lo and condition register names 6414 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6415 "$fcc5","$fcc6","$fcc7", 6416 // MSA register names 6417 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6418 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6419 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6420 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6421 // MSA control register names 6422 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6423 "$msarequest", "$msamap", "$msaunmap" 6424 }; 6425 Names = GCCRegNames; 6426 NumNames = llvm::array_lengthof(GCCRegNames); 6427 } 6428 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6429 unsigned &NumAliases) const override = 0; 6430 bool validateAsmConstraint(const char *&Name, 6431 TargetInfo::ConstraintInfo &Info) const override { 6432 switch (*Name) { 6433 default: 6434 return false; 6435 case 'r': // CPU registers. 6436 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6437 case 'y': // Equivalent to "r", backward compatibility only. 6438 case 'f': // floating-point registers. 6439 case 'c': // $25 for indirect jumps 6440 case 'l': // lo register 6441 case 'x': // hilo register pair 6442 Info.setAllowsRegister(); 6443 return true; 6444 case 'I': // Signed 16-bit constant 6445 case 'J': // Integer 0 6446 case 'K': // Unsigned 16-bit constant 6447 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6448 case 'M': // Constants not loadable via lui, addiu, or ori 6449 case 'N': // Constant -1 to -65535 6450 case 'O': // A signed 15-bit constant 6451 case 'P': // A constant between 1 go 65535 6452 return true; 6453 case 'R': // An address that can be used in a non-macro load or store 6454 Info.setAllowsMemory(); 6455 return true; 6456 case 'Z': 6457 if (Name[1] == 'C') { // An address usable by ll, and sc. 6458 Info.setAllowsMemory(); 6459 Name++; // Skip over 'Z'. 6460 return true; 6461 } 6462 return false; 6463 } 6464 } 6465 6466 std::string convertConstraint(const char *&Constraint) const override { 6467 std::string R; 6468 switch (*Constraint) { 6469 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6470 if (Constraint[1] == 'C') { 6471 R = std::string("^") + std::string(Constraint, 2); 6472 Constraint++; 6473 return R; 6474 } 6475 break; 6476 } 6477 return TargetInfo::convertConstraint(Constraint); 6478 } 6479 6480 const char *getClobbers() const override { 6481 // In GCC, $1 is not widely used in generated code (it's used only in a few 6482 // specific situations), so there is no real need for users to add it to 6483 // the clobbers list if they want to use it in their inline assembly code. 6484 // 6485 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6486 // code generation, so using it in inline assembly without adding it to the 6487 // clobbers list can cause conflicts between the inline assembly code and 6488 // the surrounding generated code. 6489 // 6490 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6491 // operands, which will conflict with the ".set at" assembler option (which 6492 // we use only for inline assembly, in order to maintain compatibility with 6493 // GCC) and will also conflict with the user's usage of $1. 6494 // 6495 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6496 // register for generated code is to automatically clobber $1 for all inline 6497 // assembly code. 6498 // 6499 // FIXME: We should automatically clobber $1 only for inline assembly code 6500 // which actually uses it. This would allow LLVM to use $1 for inline 6501 // assembly operands if the user's assembly code doesn't use it. 6502 return "~{$1}"; 6503 } 6504 6505 bool handleTargetFeatures(std::vector<std::string> &Features, 6506 DiagnosticsEngine &Diags) override { 6507 IsMips16 = false; 6508 IsMicromips = false; 6509 IsNan2008 = isNaN2008Default(); 6510 IsSingleFloat = false; 6511 FloatABI = HardFloat; 6512 DspRev = NoDSP; 6513 HasFP64 = isFP64Default(); 6514 6515 for (const auto &Feature : Features) { 6516 if (Feature == "+single-float") 6517 IsSingleFloat = true; 6518 else if (Feature == "+soft-float") 6519 FloatABI = SoftFloat; 6520 else if (Feature == "+mips16") 6521 IsMips16 = true; 6522 else if (Feature == "+micromips") 6523 IsMicromips = true; 6524 else if (Feature == "+dsp") 6525 DspRev = std::max(DspRev, DSP1); 6526 else if (Feature == "+dspr2") 6527 DspRev = std::max(DspRev, DSP2); 6528 else if (Feature == "+msa") 6529 HasMSA = true; 6530 else if (Feature == "+fp64") 6531 HasFP64 = true; 6532 else if (Feature == "-fp64") 6533 HasFP64 = false; 6534 else if (Feature == "+nan2008") 6535 IsNan2008 = true; 6536 else if (Feature == "-nan2008") 6537 IsNan2008 = false; 6538 } 6539 6540 setDataLayoutString(); 6541 6542 return true; 6543 } 6544 6545 int getEHDataRegisterNumber(unsigned RegNo) const override { 6546 if (RegNo == 0) return 4; 6547 if (RegNo == 1) return 5; 6548 return -1; 6549 } 6550 6551 bool isCLZForZeroUndef() const override { return false; } 6552 }; 6553 6554 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 6555 #define BUILTIN(ID, TYPE, ATTRS) \ 6556 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6557 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6558 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6559 #include "clang/Basic/BuiltinsMips.def" 6560 }; 6561 6562 class Mips32TargetInfoBase : public MipsTargetInfoBase { 6563 public: 6564 Mips32TargetInfoBase(const llvm::Triple &Triple) 6565 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 6566 SizeType = UnsignedInt; 6567 PtrDiffType = SignedInt; 6568 Int64Type = SignedLongLong; 6569 IntMaxType = Int64Type; 6570 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 6571 } 6572 bool setABI(const std::string &Name) override { 6573 if (Name == "o32" || Name == "eabi") { 6574 ABI = Name; 6575 return true; 6576 } 6577 return false; 6578 } 6579 void getTargetDefines(const LangOptions &Opts, 6580 MacroBuilder &Builder) const override { 6581 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6582 6583 Builder.defineMacro("__mips", "32"); 6584 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 6585 6586 const std::string& CPUStr = getCPU(); 6587 if (CPUStr == "mips32") 6588 Builder.defineMacro("__mips_isa_rev", "1"); 6589 else if (CPUStr == "mips32r2") 6590 Builder.defineMacro("__mips_isa_rev", "2"); 6591 else if (CPUStr == "mips32r3") 6592 Builder.defineMacro("__mips_isa_rev", "3"); 6593 else if (CPUStr == "mips32r5") 6594 Builder.defineMacro("__mips_isa_rev", "5"); 6595 else if (CPUStr == "mips32r6") 6596 Builder.defineMacro("__mips_isa_rev", "6"); 6597 6598 if (ABI == "o32") { 6599 Builder.defineMacro("__mips_o32"); 6600 Builder.defineMacro("_ABIO32", "1"); 6601 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6602 } 6603 else if (ABI == "eabi") 6604 Builder.defineMacro("__mips_eabi"); 6605 else 6606 llvm_unreachable("Invalid ABI for Mips32."); 6607 } 6608 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6609 unsigned &NumAliases) const override { 6610 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6611 { { "at" }, "$1" }, 6612 { { "v0" }, "$2" }, 6613 { { "v1" }, "$3" }, 6614 { { "a0" }, "$4" }, 6615 { { "a1" }, "$5" }, 6616 { { "a2" }, "$6" }, 6617 { { "a3" }, "$7" }, 6618 { { "t0" }, "$8" }, 6619 { { "t1" }, "$9" }, 6620 { { "t2" }, "$10" }, 6621 { { "t3" }, "$11" }, 6622 { { "t4" }, "$12" }, 6623 { { "t5" }, "$13" }, 6624 { { "t6" }, "$14" }, 6625 { { "t7" }, "$15" }, 6626 { { "s0" }, "$16" }, 6627 { { "s1" }, "$17" }, 6628 { { "s2" }, "$18" }, 6629 { { "s3" }, "$19" }, 6630 { { "s4" }, "$20" }, 6631 { { "s5" }, "$21" }, 6632 { { "s6" }, "$22" }, 6633 { { "s7" }, "$23" }, 6634 { { "t8" }, "$24" }, 6635 { { "t9" }, "$25" }, 6636 { { "k0" }, "$26" }, 6637 { { "k1" }, "$27" }, 6638 { { "gp" }, "$28" }, 6639 { { "sp","$sp" }, "$29" }, 6640 { { "fp","$fp" }, "$30" }, 6641 { { "ra" }, "$31" } 6642 }; 6643 Aliases = GCCRegAliases; 6644 NumAliases = llvm::array_lengthof(GCCRegAliases); 6645 } 6646 }; 6647 6648 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6649 void setDataLayoutString() override { 6650 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6651 } 6652 6653 public: 6654 Mips32EBTargetInfo(const llvm::Triple &Triple) 6655 : Mips32TargetInfoBase(Triple) { 6656 } 6657 void getTargetDefines(const LangOptions &Opts, 6658 MacroBuilder &Builder) const override { 6659 DefineStd(Builder, "MIPSEB", Opts); 6660 Builder.defineMacro("_MIPSEB"); 6661 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6662 } 6663 }; 6664 6665 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6666 void setDataLayoutString() override { 6667 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6668 } 6669 6670 public: 6671 Mips32ELTargetInfo(const llvm::Triple &Triple) 6672 : Mips32TargetInfoBase(Triple) { 6673 BigEndian = false; 6674 } 6675 void getTargetDefines(const LangOptions &Opts, 6676 MacroBuilder &Builder) const override { 6677 DefineStd(Builder, "MIPSEL", Opts); 6678 Builder.defineMacro("_MIPSEL"); 6679 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6680 } 6681 }; 6682 6683 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6684 public: 6685 Mips64TargetInfoBase(const llvm::Triple &Triple) 6686 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6687 LongDoubleWidth = LongDoubleAlign = 128; 6688 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6689 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6690 LongDoubleWidth = LongDoubleAlign = 64; 6691 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6692 } 6693 setN64ABITypes(); 6694 SuitableAlign = 128; 6695 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6696 } 6697 6698 void setN64ABITypes() { 6699 LongWidth = LongAlign = 64; 6700 PointerWidth = PointerAlign = 64; 6701 SizeType = UnsignedLong; 6702 PtrDiffType = SignedLong; 6703 Int64Type = SignedLong; 6704 IntMaxType = Int64Type; 6705 } 6706 6707 void setN32ABITypes() { 6708 LongWidth = LongAlign = 32; 6709 PointerWidth = PointerAlign = 32; 6710 SizeType = UnsignedInt; 6711 PtrDiffType = SignedInt; 6712 Int64Type = SignedLongLong; 6713 IntMaxType = Int64Type; 6714 } 6715 6716 bool setABI(const std::string &Name) override { 6717 if (Name == "n32") { 6718 setN32ABITypes(); 6719 ABI = Name; 6720 return true; 6721 } 6722 if (Name == "n64") { 6723 setN64ABITypes(); 6724 ABI = Name; 6725 return true; 6726 } 6727 return false; 6728 } 6729 6730 void getTargetDefines(const LangOptions &Opts, 6731 MacroBuilder &Builder) const override { 6732 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6733 6734 Builder.defineMacro("__mips", "64"); 6735 Builder.defineMacro("__mips64"); 6736 Builder.defineMacro("__mips64__"); 6737 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 6738 6739 const std::string& CPUStr = getCPU(); 6740 if (CPUStr == "mips64") 6741 Builder.defineMacro("__mips_isa_rev", "1"); 6742 else if (CPUStr == "mips64r2") 6743 Builder.defineMacro("__mips_isa_rev", "2"); 6744 else if (CPUStr == "mips64r3") 6745 Builder.defineMacro("__mips_isa_rev", "3"); 6746 else if (CPUStr == "mips64r5") 6747 Builder.defineMacro("__mips_isa_rev", "5"); 6748 else if (CPUStr == "mips64r6") 6749 Builder.defineMacro("__mips_isa_rev", "6"); 6750 6751 if (ABI == "n32") { 6752 Builder.defineMacro("__mips_n32"); 6753 Builder.defineMacro("_ABIN32", "2"); 6754 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 6755 } 6756 else if (ABI == "n64") { 6757 Builder.defineMacro("__mips_n64"); 6758 Builder.defineMacro("_ABI64", "3"); 6759 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 6760 } 6761 else 6762 llvm_unreachable("Invalid ABI for Mips64."); 6763 } 6764 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6765 unsigned &NumAliases) const override { 6766 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6767 { { "at" }, "$1" }, 6768 { { "v0" }, "$2" }, 6769 { { "v1" }, "$3" }, 6770 { { "a0" }, "$4" }, 6771 { { "a1" }, "$5" }, 6772 { { "a2" }, "$6" }, 6773 { { "a3" }, "$7" }, 6774 { { "a4" }, "$8" }, 6775 { { "a5" }, "$9" }, 6776 { { "a6" }, "$10" }, 6777 { { "a7" }, "$11" }, 6778 { { "t0" }, "$12" }, 6779 { { "t1" }, "$13" }, 6780 { { "t2" }, "$14" }, 6781 { { "t3" }, "$15" }, 6782 { { "s0" }, "$16" }, 6783 { { "s1" }, "$17" }, 6784 { { "s2" }, "$18" }, 6785 { { "s3" }, "$19" }, 6786 { { "s4" }, "$20" }, 6787 { { "s5" }, "$21" }, 6788 { { "s6" }, "$22" }, 6789 { { "s7" }, "$23" }, 6790 { { "t8" }, "$24" }, 6791 { { "t9" }, "$25" }, 6792 { { "k0" }, "$26" }, 6793 { { "k1" }, "$27" }, 6794 { { "gp" }, "$28" }, 6795 { { "sp","$sp" }, "$29" }, 6796 { { "fp","$fp" }, "$30" }, 6797 { { "ra" }, "$31" } 6798 }; 6799 Aliases = GCCRegAliases; 6800 NumAliases = llvm::array_lengthof(GCCRegAliases); 6801 } 6802 6803 bool hasInt128Type() const override { return true; } 6804 }; 6805 6806 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 6807 void setDataLayoutString() override { 6808 if (ABI == "n32") 6809 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6810 else 6811 DataLayoutString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6812 6813 } 6814 6815 public: 6816 Mips64EBTargetInfo(const llvm::Triple &Triple) 6817 : Mips64TargetInfoBase(Triple) {} 6818 void getTargetDefines(const LangOptions &Opts, 6819 MacroBuilder &Builder) const override { 6820 DefineStd(Builder, "MIPSEB", Opts); 6821 Builder.defineMacro("_MIPSEB"); 6822 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6823 } 6824 }; 6825 6826 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 6827 void setDataLayoutString() override { 6828 if (ABI == "n32") 6829 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6830 else 6831 DataLayoutString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6832 } 6833 public: 6834 Mips64ELTargetInfo(const llvm::Triple &Triple) 6835 : Mips64TargetInfoBase(Triple) { 6836 // Default ABI is n64. 6837 BigEndian = false; 6838 } 6839 void getTargetDefines(const LangOptions &Opts, 6840 MacroBuilder &Builder) const override { 6841 DefineStd(Builder, "MIPSEL", Opts); 6842 Builder.defineMacro("_MIPSEL"); 6843 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6844 } 6845 }; 6846 6847 class PNaClTargetInfo : public TargetInfo { 6848 public: 6849 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6850 BigEndian = false; 6851 this->UserLabelPrefix = ""; 6852 this->LongAlign = 32; 6853 this->LongWidth = 32; 6854 this->PointerAlign = 32; 6855 this->PointerWidth = 32; 6856 this->IntMaxType = TargetInfo::SignedLongLong; 6857 this->Int64Type = TargetInfo::SignedLongLong; 6858 this->DoubleAlign = 64; 6859 this->LongDoubleWidth = 64; 6860 this->LongDoubleAlign = 64; 6861 this->SizeType = TargetInfo::UnsignedInt; 6862 this->PtrDiffType = TargetInfo::SignedInt; 6863 this->IntPtrType = TargetInfo::SignedInt; 6864 this->RegParmMax = 0; // Disallow regparm 6865 } 6866 6867 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 6868 Builder.defineMacro("__le32__"); 6869 Builder.defineMacro("__pnacl__"); 6870 } 6871 void getTargetDefines(const LangOptions &Opts, 6872 MacroBuilder &Builder) const override { 6873 getArchDefines(Opts, Builder); 6874 } 6875 bool hasFeature(StringRef Feature) const override { 6876 return Feature == "pnacl"; 6877 } 6878 void getTargetBuiltins(const Builtin::Info *&Records, 6879 unsigned &NumRecords) const override { 6880 } 6881 BuiltinVaListKind getBuiltinVaListKind() const override { 6882 return TargetInfo::PNaClABIBuiltinVaList; 6883 } 6884 void getGCCRegNames(const char * const *&Names, 6885 unsigned &NumNames) const override; 6886 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6887 unsigned &NumAliases) const override; 6888 bool validateAsmConstraint(const char *&Name, 6889 TargetInfo::ConstraintInfo &Info) const override { 6890 return false; 6891 } 6892 6893 const char *getClobbers() const override { 6894 return ""; 6895 } 6896 }; 6897 6898 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 6899 unsigned &NumNames) const { 6900 Names = nullptr; 6901 NumNames = 0; 6902 } 6903 6904 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 6905 unsigned &NumAliases) const { 6906 Aliases = nullptr; 6907 NumAliases = 0; 6908 } 6909 6910 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 6911 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 6912 public: 6913 NaClMips32ELTargetInfo(const llvm::Triple &Triple) : 6914 Mips32ELTargetInfo(Triple) { 6915 } 6916 6917 BuiltinVaListKind getBuiltinVaListKind() const override { 6918 return TargetInfo::PNaClABIBuiltinVaList; 6919 } 6920 }; 6921 6922 class Le64TargetInfo : public TargetInfo { 6923 static const Builtin::Info BuiltinInfo[]; 6924 6925 public: 6926 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6927 BigEndian = false; 6928 NoAsmVariants = true; 6929 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6930 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6931 DataLayoutString = "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 6932 } 6933 6934 void getTargetDefines(const LangOptions &Opts, 6935 MacroBuilder &Builder) const override { 6936 DefineStd(Builder, "unix", Opts); 6937 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 6938 Builder.defineMacro("__ELF__"); 6939 } 6940 void getTargetBuiltins(const Builtin::Info *&Records, 6941 unsigned &NumRecords) const override { 6942 Records = BuiltinInfo; 6943 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin; 6944 } 6945 BuiltinVaListKind getBuiltinVaListKind() const override { 6946 return TargetInfo::PNaClABIBuiltinVaList; 6947 } 6948 const char *getClobbers() const override { return ""; } 6949 void getGCCRegNames(const char *const *&Names, 6950 unsigned &NumNames) const override { 6951 Names = nullptr; 6952 NumNames = 0; 6953 } 6954 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6955 unsigned &NumAliases) const override { 6956 Aliases = nullptr; 6957 NumAliases = 0; 6958 } 6959 bool validateAsmConstraint(const char *&Name, 6960 TargetInfo::ConstraintInfo &Info) const override { 6961 return false; 6962 } 6963 6964 bool hasProtectedVisibility() const override { return false; } 6965 }; 6966 6967 class WebAssemblyTargetInfo : public TargetInfo { 6968 static const Builtin::Info BuiltinInfo[]; 6969 6970 enum SIMDEnum { 6971 NoSIMD, 6972 SIMD128, 6973 } SIMDLevel; 6974 6975 public: 6976 explicit WebAssemblyTargetInfo(const llvm::Triple &T) 6977 : TargetInfo(T), SIMDLevel(NoSIMD) { 6978 BigEndian = false; 6979 NoAsmVariants = true; 6980 SuitableAlign = 128; 6981 LargeArrayMinWidth = 128; 6982 LargeArrayAlign = 128; 6983 SimdDefaultAlign = 128; 6984 SigAtomicType = SignedLong; 6985 } 6986 6987 protected: 6988 void getTargetDefines(const LangOptions &Opts, 6989 MacroBuilder &Builder) const override { 6990 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 6991 if (SIMDLevel >= SIMD128) 6992 Builder.defineMacro("__wasm_simd128__"); 6993 } 6994 6995 private: 6996 bool 6997 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6998 StringRef CPU, 6999 const std::vector<std::string> &FeaturesVec) const override { 7000 if (CPU == "bleeding-edge") 7001 Features["simd128"] = true; 7002 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7003 } 7004 bool hasFeature(StringRef Feature) const final { 7005 return llvm::StringSwitch<bool>(Feature) 7006 .Case("simd128", SIMDLevel >= SIMD128) 7007 .Default(false); 7008 } 7009 bool handleTargetFeatures(std::vector<std::string> &Features, 7010 DiagnosticsEngine &Diags) final { 7011 for (const auto &Feature : Features) { 7012 if (Feature == "+simd128") { 7013 SIMDLevel = std::max(SIMDLevel, SIMD128); 7014 continue; 7015 } 7016 if (Feature == "-simd128") { 7017 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7018 continue; 7019 } 7020 7021 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7022 << "-target-feature"; 7023 return false; 7024 } 7025 return true; 7026 } 7027 bool setCPU(const std::string &Name) final { 7028 return llvm::StringSwitch<bool>(Name) 7029 .Case("mvp", true) 7030 .Case("bleeding-edge", true) 7031 .Case("generic", true) 7032 .Default(false); 7033 } 7034 void getTargetBuiltins(const Builtin::Info *&Records, 7035 unsigned &NumRecords) const final { 7036 Records = BuiltinInfo; 7037 NumRecords = clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin; 7038 } 7039 BuiltinVaListKind getBuiltinVaListKind() const final { 7040 // TODO: Implement va_list properly. 7041 return VoidPtrBuiltinVaList; 7042 } 7043 void getGCCRegNames(const char *const *&Names, 7044 unsigned &NumNames) const final { 7045 Names = nullptr; 7046 NumNames = 0; 7047 } 7048 void getGCCRegAliases(const GCCRegAlias *&Aliases, 7049 unsigned &NumAliases) const final { 7050 Aliases = nullptr; 7051 NumAliases = 0; 7052 } 7053 bool 7054 validateAsmConstraint(const char *&Name, 7055 TargetInfo::ConstraintInfo &Info) const final { 7056 return false; 7057 } 7058 const char *getClobbers() const final { return ""; } 7059 bool isCLZForZeroUndef() const final { return false; } 7060 bool hasInt128Type() const final { return true; } 7061 IntType getIntTypeByWidth(unsigned BitWidth, 7062 bool IsSigned) const final { 7063 // WebAssembly prefers long long for explicitly 64-bit integers. 7064 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7065 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7066 } 7067 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7068 bool IsSigned) const final { 7069 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7070 return BitWidth == 64 7071 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7072 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7073 } 7074 }; 7075 7076 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7077 #define BUILTIN(ID, TYPE, ATTRS) \ 7078 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7079 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7080 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7081 #include "clang/Basic/BuiltinsWebAssembly.def" 7082 }; 7083 7084 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7085 public: 7086 explicit WebAssembly32TargetInfo(const llvm::Triple &T) 7087 : WebAssemblyTargetInfo(T) { 7088 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7089 DataLayoutString = "e-p:32:32-i64:64-n32:64-S128"; 7090 } 7091 7092 protected: 7093 void getTargetDefines(const LangOptions &Opts, 7094 MacroBuilder &Builder) const override { 7095 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7096 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7097 } 7098 }; 7099 7100 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7101 public: 7102 explicit WebAssembly64TargetInfo(const llvm::Triple &T) 7103 : WebAssemblyTargetInfo(T) { 7104 LongAlign = LongWidth = 64; 7105 PointerAlign = PointerWidth = 64; 7106 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7107 DataLayoutString = "e-p:64:64-i64:64-n32:64-S128"; 7108 } 7109 7110 protected: 7111 void getTargetDefines(const LangOptions &Opts, 7112 MacroBuilder &Builder) const override { 7113 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7114 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7115 } 7116 }; 7117 7118 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7119 #define BUILTIN(ID, TYPE, ATTRS) \ 7120 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7121 #include "clang/Basic/BuiltinsLe64.def" 7122 }; 7123 7124 static const unsigned SPIRAddrSpaceMap[] = { 7125 1, // opencl_global 7126 3, // opencl_local 7127 2, // opencl_constant 7128 4, // opencl_generic 7129 0, // cuda_device 7130 0, // cuda_constant 7131 0 // cuda_shared 7132 }; 7133 class SPIRTargetInfo : public TargetInfo { 7134 public: 7135 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7136 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7137 "SPIR target must use unknown OS"); 7138 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7139 "SPIR target must use unknown environment type"); 7140 BigEndian = false; 7141 TLSSupported = false; 7142 LongWidth = LongAlign = 64; 7143 AddrSpaceMap = &SPIRAddrSpaceMap; 7144 UseAddrSpaceMapMangling = true; 7145 // Define available target features 7146 // These must be defined in sorted order! 7147 NoAsmVariants = true; 7148 } 7149 void getTargetDefines(const LangOptions &Opts, 7150 MacroBuilder &Builder) const override { 7151 DefineStd(Builder, "SPIR", Opts); 7152 } 7153 bool hasFeature(StringRef Feature) const override { 7154 return Feature == "spir"; 7155 } 7156 7157 void getTargetBuiltins(const Builtin::Info *&Records, 7158 unsigned &NumRecords) const override {} 7159 const char *getClobbers() const override { return ""; } 7160 void getGCCRegNames(const char *const *&Names, 7161 unsigned &NumNames) const override {} 7162 bool validateAsmConstraint(const char *&Name, 7163 TargetInfo::ConstraintInfo &info) const override { 7164 return true; 7165 } 7166 void getGCCRegAliases(const GCCRegAlias *&Aliases, 7167 unsigned &NumAliases) const override {} 7168 BuiltinVaListKind getBuiltinVaListKind() const override { 7169 return TargetInfo::VoidPtrBuiltinVaList; 7170 } 7171 7172 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7173 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK 7174 : CCCR_Warning; 7175 } 7176 7177 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7178 return CC_SpirFunction; 7179 } 7180 }; 7181 7182 class SPIR32TargetInfo : public SPIRTargetInfo { 7183 public: 7184 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7185 PointerWidth = PointerAlign = 32; 7186 SizeType = TargetInfo::UnsignedInt; 7187 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7188 DataLayoutString = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7189 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7190 } 7191 void getTargetDefines(const LangOptions &Opts, 7192 MacroBuilder &Builder) const override { 7193 DefineStd(Builder, "SPIR32", Opts); 7194 } 7195 }; 7196 7197 class SPIR64TargetInfo : public SPIRTargetInfo { 7198 public: 7199 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7200 PointerWidth = PointerAlign = 64; 7201 SizeType = TargetInfo::UnsignedLong; 7202 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7203 DataLayoutString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7204 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7205 } 7206 void getTargetDefines(const LangOptions &Opts, 7207 MacroBuilder &Builder) const override { 7208 DefineStd(Builder, "SPIR64", Opts); 7209 } 7210 }; 7211 7212 class XCoreTargetInfo : public TargetInfo { 7213 static const Builtin::Info BuiltinInfo[]; 7214 public: 7215 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7216 BigEndian = false; 7217 NoAsmVariants = true; 7218 LongLongAlign = 32; 7219 SuitableAlign = 32; 7220 DoubleAlign = LongDoubleAlign = 32; 7221 SizeType = UnsignedInt; 7222 PtrDiffType = SignedInt; 7223 IntPtrType = SignedInt; 7224 WCharType = UnsignedChar; 7225 WIntType = UnsignedInt; 7226 UseZeroLengthBitfieldAlignment = true; 7227 DataLayoutString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7228 "-f64:32-a:0:32-n32"; 7229 } 7230 void getTargetDefines(const LangOptions &Opts, 7231 MacroBuilder &Builder) const override { 7232 Builder.defineMacro("__XS1B__"); 7233 } 7234 void getTargetBuiltins(const Builtin::Info *&Records, 7235 unsigned &NumRecords) const override { 7236 Records = BuiltinInfo; 7237 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 7238 } 7239 BuiltinVaListKind getBuiltinVaListKind() const override { 7240 return TargetInfo::VoidPtrBuiltinVaList; 7241 } 7242 const char *getClobbers() const override { 7243 return ""; 7244 } 7245 void getGCCRegNames(const char * const *&Names, 7246 unsigned &NumNames) const override { 7247 static const char * const GCCRegNames[] = { 7248 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7249 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 7250 }; 7251 Names = GCCRegNames; 7252 NumNames = llvm::array_lengthof(GCCRegNames); 7253 } 7254 void getGCCRegAliases(const GCCRegAlias *&Aliases, 7255 unsigned &NumAliases) const override { 7256 Aliases = nullptr; 7257 NumAliases = 0; 7258 } 7259 bool validateAsmConstraint(const char *&Name, 7260 TargetInfo::ConstraintInfo &Info) const override { 7261 return false; 7262 } 7263 int getEHDataRegisterNumber(unsigned RegNo) const override { 7264 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7265 return (RegNo < 2)? RegNo : -1; 7266 } 7267 }; 7268 7269 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7270 #define BUILTIN(ID, TYPE, ATTRS) \ 7271 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7272 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7273 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7274 #include "clang/Basic/BuiltinsXCore.def" 7275 }; 7276 7277 // x86_32 Android target 7278 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7279 public: 7280 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 7281 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 7282 SuitableAlign = 32; 7283 LongDoubleWidth = 64; 7284 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7285 } 7286 }; 7287 7288 // x86_64 Android target 7289 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7290 public: 7291 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 7292 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 7293 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7294 } 7295 7296 bool useFloat128ManglingForLongDouble() const override { 7297 return true; 7298 } 7299 }; 7300 } // end anonymous namespace 7301 7302 //===----------------------------------------------------------------------===// 7303 // Driver code 7304 //===----------------------------------------------------------------------===// 7305 7306 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 7307 llvm::Triple::OSType os = Triple.getOS(); 7308 7309 switch (Triple.getArch()) { 7310 default: 7311 return nullptr; 7312 7313 case llvm::Triple::xcore: 7314 return new XCoreTargetInfo(Triple); 7315 7316 case llvm::Triple::hexagon: 7317 return new HexagonTargetInfo(Triple); 7318 7319 case llvm::Triple::aarch64: 7320 if (Triple.isOSDarwin()) 7321 return new DarwinAArch64TargetInfo(Triple); 7322 7323 switch (os) { 7324 case llvm::Triple::FreeBSD: 7325 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 7326 case llvm::Triple::Linux: 7327 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 7328 case llvm::Triple::NetBSD: 7329 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 7330 default: 7331 return new AArch64leTargetInfo(Triple); 7332 } 7333 7334 case llvm::Triple::aarch64_be: 7335 switch (os) { 7336 case llvm::Triple::FreeBSD: 7337 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 7338 case llvm::Triple::Linux: 7339 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 7340 case llvm::Triple::NetBSD: 7341 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 7342 default: 7343 return new AArch64beTargetInfo(Triple); 7344 } 7345 7346 case llvm::Triple::arm: 7347 case llvm::Triple::thumb: 7348 if (Triple.isOSBinFormatMachO()) 7349 return new DarwinARMTargetInfo(Triple); 7350 7351 switch (os) { 7352 case llvm::Triple::Linux: 7353 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 7354 case llvm::Triple::FreeBSD: 7355 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 7356 case llvm::Triple::NetBSD: 7357 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 7358 case llvm::Triple::OpenBSD: 7359 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 7360 case llvm::Triple::Bitrig: 7361 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 7362 case llvm::Triple::RTEMS: 7363 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 7364 case llvm::Triple::NaCl: 7365 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 7366 case llvm::Triple::Win32: 7367 switch (Triple.getEnvironment()) { 7368 case llvm::Triple::Cygnus: 7369 return new CygwinARMTargetInfo(Triple); 7370 case llvm::Triple::GNU: 7371 return new MinGWARMTargetInfo(Triple); 7372 case llvm::Triple::Itanium: 7373 return new ItaniumWindowsARMleTargetInfo(Triple); 7374 case llvm::Triple::MSVC: 7375 default: // Assume MSVC for unknown environments 7376 return new MicrosoftARMleTargetInfo(Triple); 7377 } 7378 default: 7379 return new ARMleTargetInfo(Triple); 7380 } 7381 7382 case llvm::Triple::armeb: 7383 case llvm::Triple::thumbeb: 7384 if (Triple.isOSDarwin()) 7385 return new DarwinARMTargetInfo(Triple); 7386 7387 switch (os) { 7388 case llvm::Triple::Linux: 7389 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 7390 case llvm::Triple::FreeBSD: 7391 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 7392 case llvm::Triple::NetBSD: 7393 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 7394 case llvm::Triple::OpenBSD: 7395 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 7396 case llvm::Triple::Bitrig: 7397 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 7398 case llvm::Triple::RTEMS: 7399 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 7400 case llvm::Triple::NaCl: 7401 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 7402 default: 7403 return new ARMbeTargetInfo(Triple); 7404 } 7405 7406 case llvm::Triple::bpfeb: 7407 case llvm::Triple::bpfel: 7408 return new BPFTargetInfo(Triple); 7409 7410 case llvm::Triple::msp430: 7411 return new MSP430TargetInfo(Triple); 7412 7413 case llvm::Triple::mips: 7414 switch (os) { 7415 case llvm::Triple::Linux: 7416 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 7417 case llvm::Triple::RTEMS: 7418 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 7419 case llvm::Triple::FreeBSD: 7420 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7421 case llvm::Triple::NetBSD: 7422 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7423 default: 7424 return new Mips32EBTargetInfo(Triple); 7425 } 7426 7427 case llvm::Triple::mipsel: 7428 switch (os) { 7429 case llvm::Triple::Linux: 7430 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 7431 case llvm::Triple::RTEMS: 7432 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 7433 case llvm::Triple::FreeBSD: 7434 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7435 case llvm::Triple::NetBSD: 7436 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7437 case llvm::Triple::NaCl: 7438 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple); 7439 default: 7440 return new Mips32ELTargetInfo(Triple); 7441 } 7442 7443 case llvm::Triple::mips64: 7444 switch (os) { 7445 case llvm::Triple::Linux: 7446 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 7447 case llvm::Triple::RTEMS: 7448 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 7449 case llvm::Triple::FreeBSD: 7450 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7451 case llvm::Triple::NetBSD: 7452 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7453 case llvm::Triple::OpenBSD: 7454 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7455 default: 7456 return new Mips64EBTargetInfo(Triple); 7457 } 7458 7459 case llvm::Triple::mips64el: 7460 switch (os) { 7461 case llvm::Triple::Linux: 7462 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 7463 case llvm::Triple::RTEMS: 7464 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 7465 case llvm::Triple::FreeBSD: 7466 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7467 case llvm::Triple::NetBSD: 7468 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7469 case llvm::Triple::OpenBSD: 7470 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7471 default: 7472 return new Mips64ELTargetInfo(Triple); 7473 } 7474 7475 case llvm::Triple::le32: 7476 switch (os) { 7477 case llvm::Triple::NaCl: 7478 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 7479 default: 7480 return nullptr; 7481 } 7482 7483 case llvm::Triple::le64: 7484 return new Le64TargetInfo(Triple); 7485 7486 case llvm::Triple::ppc: 7487 if (Triple.isOSDarwin()) 7488 return new DarwinPPC32TargetInfo(Triple); 7489 switch (os) { 7490 case llvm::Triple::Linux: 7491 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 7492 case llvm::Triple::FreeBSD: 7493 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 7494 case llvm::Triple::NetBSD: 7495 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 7496 case llvm::Triple::OpenBSD: 7497 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 7498 case llvm::Triple::RTEMS: 7499 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 7500 default: 7501 return new PPC32TargetInfo(Triple); 7502 } 7503 7504 case llvm::Triple::ppc64: 7505 if (Triple.isOSDarwin()) 7506 return new DarwinPPC64TargetInfo(Triple); 7507 switch (os) { 7508 case llvm::Triple::Linux: 7509 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7510 case llvm::Triple::Lv2: 7511 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 7512 case llvm::Triple::FreeBSD: 7513 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 7514 case llvm::Triple::NetBSD: 7515 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7516 default: 7517 return new PPC64TargetInfo(Triple); 7518 } 7519 7520 case llvm::Triple::ppc64le: 7521 switch (os) { 7522 case llvm::Triple::Linux: 7523 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7524 case llvm::Triple::NetBSD: 7525 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7526 default: 7527 return new PPC64TargetInfo(Triple); 7528 } 7529 7530 case llvm::Triple::nvptx: 7531 return new NVPTX32TargetInfo(Triple); 7532 case llvm::Triple::nvptx64: 7533 return new NVPTX64TargetInfo(Triple); 7534 7535 case llvm::Triple::amdgcn: 7536 case llvm::Triple::r600: 7537 return new AMDGPUTargetInfo(Triple); 7538 7539 case llvm::Triple::sparc: 7540 switch (os) { 7541 case llvm::Triple::Linux: 7542 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 7543 case llvm::Triple::Solaris: 7544 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple); 7545 case llvm::Triple::NetBSD: 7546 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 7547 case llvm::Triple::OpenBSD: 7548 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 7549 case llvm::Triple::RTEMS: 7550 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 7551 default: 7552 return new SparcV8TargetInfo(Triple); 7553 } 7554 7555 // The 'sparcel' architecture copies all the above cases except for Solaris. 7556 case llvm::Triple::sparcel: 7557 switch (os) { 7558 case llvm::Triple::Linux: 7559 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 7560 case llvm::Triple::NetBSD: 7561 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7562 case llvm::Triple::OpenBSD: 7563 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7564 case llvm::Triple::RTEMS: 7565 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 7566 default: 7567 return new SparcV8elTargetInfo(Triple); 7568 } 7569 7570 case llvm::Triple::sparcv9: 7571 switch (os) { 7572 case llvm::Triple::Linux: 7573 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 7574 case llvm::Triple::Solaris: 7575 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 7576 case llvm::Triple::NetBSD: 7577 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 7578 case llvm::Triple::OpenBSD: 7579 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 7580 case llvm::Triple::FreeBSD: 7581 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 7582 default: 7583 return new SparcV9TargetInfo(Triple); 7584 } 7585 7586 case llvm::Triple::systemz: 7587 switch (os) { 7588 case llvm::Triple::Linux: 7589 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 7590 default: 7591 return new SystemZTargetInfo(Triple); 7592 } 7593 7594 case llvm::Triple::tce: 7595 return new TCETargetInfo(Triple); 7596 7597 case llvm::Triple::x86: 7598 if (Triple.isOSDarwin()) 7599 return new DarwinI386TargetInfo(Triple); 7600 7601 switch (os) { 7602 case llvm::Triple::CloudABI: 7603 return new CloudABITargetInfo<X86_32TargetInfo>(Triple); 7604 case llvm::Triple::Linux: { 7605 switch (Triple.getEnvironment()) { 7606 default: 7607 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 7608 case llvm::Triple::Android: 7609 return new AndroidX86_32TargetInfo(Triple); 7610 } 7611 } 7612 case llvm::Triple::DragonFly: 7613 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 7614 case llvm::Triple::NetBSD: 7615 return new NetBSDI386TargetInfo(Triple); 7616 case llvm::Triple::OpenBSD: 7617 return new OpenBSDI386TargetInfo(Triple); 7618 case llvm::Triple::Bitrig: 7619 return new BitrigI386TargetInfo(Triple); 7620 case llvm::Triple::FreeBSD: 7621 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7622 case llvm::Triple::KFreeBSD: 7623 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7624 case llvm::Triple::Minix: 7625 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 7626 case llvm::Triple::Solaris: 7627 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 7628 case llvm::Triple::Win32: { 7629 switch (Triple.getEnvironment()) { 7630 case llvm::Triple::Cygnus: 7631 return new CygwinX86_32TargetInfo(Triple); 7632 case llvm::Triple::GNU: 7633 return new MinGWX86_32TargetInfo(Triple); 7634 case llvm::Triple::Itanium: 7635 case llvm::Triple::MSVC: 7636 default: // Assume MSVC for unknown environments 7637 return new MicrosoftX86_32TargetInfo(Triple); 7638 } 7639 } 7640 case llvm::Triple::Haiku: 7641 return new HaikuX86_32TargetInfo(Triple); 7642 case llvm::Triple::RTEMS: 7643 return new RTEMSX86_32TargetInfo(Triple); 7644 case llvm::Triple::NaCl: 7645 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 7646 default: 7647 return new X86_32TargetInfo(Triple); 7648 } 7649 7650 case llvm::Triple::x86_64: 7651 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 7652 return new DarwinX86_64TargetInfo(Triple); 7653 7654 switch (os) { 7655 case llvm::Triple::CloudABI: 7656 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 7657 case llvm::Triple::Linux: { 7658 switch (Triple.getEnvironment()) { 7659 default: 7660 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 7661 case llvm::Triple::Android: 7662 return new AndroidX86_64TargetInfo(Triple); 7663 } 7664 } 7665 case llvm::Triple::DragonFly: 7666 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 7667 case llvm::Triple::NetBSD: 7668 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 7669 case llvm::Triple::OpenBSD: 7670 return new OpenBSDX86_64TargetInfo(Triple); 7671 case llvm::Triple::Bitrig: 7672 return new BitrigX86_64TargetInfo(Triple); 7673 case llvm::Triple::FreeBSD: 7674 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7675 case llvm::Triple::KFreeBSD: 7676 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7677 case llvm::Triple::Solaris: 7678 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 7679 case llvm::Triple::Win32: { 7680 switch (Triple.getEnvironment()) { 7681 case llvm::Triple::Cygnus: 7682 return new CygwinX86_64TargetInfo(Triple); 7683 case llvm::Triple::GNU: 7684 return new MinGWX86_64TargetInfo(Triple); 7685 case llvm::Triple::MSVC: 7686 default: // Assume MSVC for unknown environments 7687 return new MicrosoftX86_64TargetInfo(Triple); 7688 } 7689 } 7690 case llvm::Triple::NaCl: 7691 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 7692 case llvm::Triple::PS4: 7693 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 7694 default: 7695 return new X86_64TargetInfo(Triple); 7696 } 7697 7698 case llvm::Triple::spir: { 7699 if (Triple.getOS() != llvm::Triple::UnknownOS || 7700 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7701 return nullptr; 7702 return new SPIR32TargetInfo(Triple); 7703 } 7704 case llvm::Triple::spir64: { 7705 if (Triple.getOS() != llvm::Triple::UnknownOS || 7706 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7707 return nullptr; 7708 return new SPIR64TargetInfo(Triple); 7709 } 7710 case llvm::Triple::wasm32: 7711 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 7712 return nullptr; 7713 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple); 7714 case llvm::Triple::wasm64: 7715 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 7716 return nullptr; 7717 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple); 7718 } 7719 } 7720 7721 /// CreateTargetInfo - Return the target info object for the specified target 7722 /// options. 7723 TargetInfo * 7724 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 7725 const std::shared_ptr<TargetOptions> &Opts) { 7726 llvm::Triple Triple(Opts->Triple); 7727 7728 // Construct the target 7729 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 7730 if (!Target) { 7731 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 7732 return nullptr; 7733 } 7734 Target->TargetOpts = Opts; 7735 7736 // Set the target CPU if specified. 7737 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 7738 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 7739 return nullptr; 7740 } 7741 7742 // Set the target ABI if specified. 7743 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 7744 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 7745 return nullptr; 7746 } 7747 7748 // Set the fp math unit. 7749 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 7750 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 7751 return nullptr; 7752 } 7753 7754 // Compute the default target features, we need the target to handle this 7755 // because features may have dependencies on one another. 7756 llvm::StringMap<bool> Features; 7757 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 7758 Opts->FeaturesAsWritten)) 7759 return nullptr; 7760 7761 // Add the features to the compile options. 7762 Opts->Features.clear(); 7763 for (const auto &F : Features) 7764 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 7765 7766 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 7767 return nullptr; 7768 7769 return Target.release(); 7770 } 7771