1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringRef.h" 25 #include "llvm/ADT/StringSwitch.h" 26 #include "llvm/ADT/Triple.h" 27 #include "llvm/IR/Type.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include <algorithm> 31 #include <memory> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 77 void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const override { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "6000"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 94 // AddressSanitizer doesn't play well with source fortification, which is on 95 // by default on Darwin. 96 if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0"); 97 98 if (!Opts.ObjCAutoRefCount) { 99 // __weak is always defined, for use in blocks and with objc pointers. 100 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 101 102 // Darwin defines __strong even in C mode (just to nothing). 103 if (Opts.getGC() != LangOptions::NonGC) 104 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 105 else 106 Builder.defineMacro("__strong", ""); 107 108 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 109 // allow this in C, since one might have block pointers in structs that 110 // are used in pure C code and in Objective-C ARC. 111 Builder.defineMacro("__unsafe_unretained", ""); 112 } 113 114 if (Opts.Static) 115 Builder.defineMacro("__STATIC__"); 116 else 117 Builder.defineMacro("__DYNAMIC__"); 118 119 if (Opts.POSIXThreads) 120 Builder.defineMacro("_REENTRANT"); 121 122 // Get the platform type and version number from the triple. 123 unsigned Maj, Min, Rev; 124 if (Triple.isMacOSX()) { 125 Triple.getMacOSXVersion(Maj, Min, Rev); 126 PlatformName = "macosx"; 127 } else { 128 Triple.getOSVersion(Maj, Min, Rev); 129 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 130 } 131 132 // If -target arch-pc-win32-macho option specified, we're 133 // generating code for Win32 ABI. No need to emit 134 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 135 if (PlatformName == "win32") { 136 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 137 return; 138 } 139 140 // Set the appropriate OS version define. 141 if (Triple.isiOS()) { 142 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 143 char Str[6]; 144 Str[0] = '0' + Maj; 145 Str[1] = '0' + (Min / 10); 146 Str[2] = '0' + (Min % 10); 147 Str[3] = '0' + (Rev / 10); 148 Str[4] = '0' + (Rev % 10); 149 Str[5] = '\0'; 150 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 151 Str); 152 } else if (Triple.isMacOSX()) { 153 // Note that the Driver allows versions which aren't representable in the 154 // define (because we only get a single digit for the minor and micro 155 // revision numbers). So, we limit them to the maximum representable 156 // version. 157 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 158 char Str[7]; 159 if (Maj < 10 || (Maj == 10 && Min < 10)) { 160 Str[0] = '0' + (Maj / 10); 161 Str[1] = '0' + (Maj % 10); 162 Str[2] = '0' + std::min(Min, 9U); 163 Str[3] = '0' + std::min(Rev, 9U); 164 Str[4] = '\0'; 165 } else { 166 // Handle versions > 10.9. 167 Str[0] = '0' + (Maj / 10); 168 Str[1] = '0' + (Maj % 10); 169 Str[2] = '0' + (Min / 10); 170 Str[3] = '0' + (Min % 10); 171 Str[4] = '0' + (Rev / 10); 172 Str[5] = '0' + (Rev % 10); 173 Str[6] = '\0'; 174 } 175 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 176 } 177 178 // Tell users about the kernel if there is one. 179 if (Triple.isOSDarwin()) 180 Builder.defineMacro("__MACH__"); 181 182 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 183 } 184 185 namespace { 186 template<typename Target> 187 class DarwinTargetInfo : public OSTargetInfo<Target> { 188 protected: 189 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 190 MacroBuilder &Builder) const override { 191 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 192 this->PlatformMinVersion); 193 } 194 195 public: 196 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 197 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 198 this->MCountName = "\01mcount"; 199 } 200 201 std::string isValidSectionSpecifier(StringRef SR) const override { 202 // Let MCSectionMachO validate this. 203 StringRef Segment, Section; 204 unsigned TAA, StubSize; 205 bool HasTAA; 206 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 207 TAA, HasTAA, StubSize); 208 } 209 210 const char *getStaticInitSectionSpecifier() const override { 211 // FIXME: We should return 0 when building kexts. 212 return "__TEXT,__StaticInit,regular,pure_instructions"; 213 } 214 215 /// Darwin does not support protected visibility. Darwin's "default" 216 /// is very similar to ELF's "protected"; Darwin requires a "weak" 217 /// attribute on declarations that can be dynamically replaced. 218 bool hasProtectedVisibility() const override { 219 return false; 220 } 221 }; 222 223 224 // DragonFlyBSD Target 225 template<typename Target> 226 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 227 protected: 228 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 229 MacroBuilder &Builder) const override { 230 // DragonFly defines; list based off of gcc output 231 Builder.defineMacro("__DragonFly__"); 232 Builder.defineMacro("__DragonFly_cc_version", "100001"); 233 Builder.defineMacro("__ELF__"); 234 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 235 Builder.defineMacro("__tune_i386__"); 236 DefineStd(Builder, "unix", Opts); 237 } 238 public: 239 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 240 : OSTargetInfo<Target>(Triple) { 241 this->UserLabelPrefix = ""; 242 243 switch (Triple.getArch()) { 244 default: 245 case llvm::Triple::x86: 246 case llvm::Triple::x86_64: 247 this->MCountName = ".mcount"; 248 break; 249 } 250 } 251 }; 252 253 // FreeBSD Target 254 template<typename Target> 255 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 256 protected: 257 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 258 MacroBuilder &Builder) const override { 259 // FreeBSD defines; list based off of gcc output 260 261 unsigned Release = Triple.getOSMajorVersion(); 262 if (Release == 0U) 263 Release = 8; 264 265 Builder.defineMacro("__FreeBSD__", Twine(Release)); 266 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 267 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 268 DefineStd(Builder, "unix", Opts); 269 Builder.defineMacro("__ELF__"); 270 271 // On FreeBSD, wchar_t contains the number of the code point as 272 // used by the character set of the locale. These character sets are 273 // not necessarily a superset of ASCII. 274 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 275 } 276 public: 277 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 278 this->UserLabelPrefix = ""; 279 280 switch (Triple.getArch()) { 281 default: 282 case llvm::Triple::x86: 283 case llvm::Triple::x86_64: 284 this->MCountName = ".mcount"; 285 break; 286 case llvm::Triple::mips: 287 case llvm::Triple::mipsel: 288 case llvm::Triple::ppc: 289 case llvm::Triple::ppc64: 290 case llvm::Triple::ppc64le: 291 this->MCountName = "_mcount"; 292 break; 293 case llvm::Triple::arm: 294 this->MCountName = "__mcount"; 295 break; 296 } 297 } 298 }; 299 300 // GNU/kFreeBSD Target 301 template<typename Target> 302 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 303 protected: 304 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 305 MacroBuilder &Builder) const override { 306 // GNU/kFreeBSD defines; list based off of gcc output 307 308 DefineStd(Builder, "unix", Opts); 309 Builder.defineMacro("__FreeBSD_kernel__"); 310 Builder.defineMacro("__GLIBC__"); 311 Builder.defineMacro("__ELF__"); 312 if (Opts.POSIXThreads) 313 Builder.defineMacro("_REENTRANT"); 314 if (Opts.CPlusPlus) 315 Builder.defineMacro("_GNU_SOURCE"); 316 } 317 public: 318 KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 319 this->UserLabelPrefix = ""; 320 } 321 }; 322 323 // Minix Target 324 template<typename Target> 325 class MinixTargetInfo : public OSTargetInfo<Target> { 326 protected: 327 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 328 MacroBuilder &Builder) const override { 329 // Minix defines 330 331 Builder.defineMacro("__minix", "3"); 332 Builder.defineMacro("_EM_WSIZE", "4"); 333 Builder.defineMacro("_EM_PSIZE", "4"); 334 Builder.defineMacro("_EM_SSIZE", "2"); 335 Builder.defineMacro("_EM_LSIZE", "4"); 336 Builder.defineMacro("_EM_FSIZE", "4"); 337 Builder.defineMacro("_EM_DSIZE", "8"); 338 Builder.defineMacro("__ELF__"); 339 DefineStd(Builder, "unix", Opts); 340 } 341 public: 342 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 343 this->UserLabelPrefix = ""; 344 } 345 }; 346 347 // Linux target 348 template<typename Target> 349 class LinuxTargetInfo : public OSTargetInfo<Target> { 350 protected: 351 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 352 MacroBuilder &Builder) const override { 353 // Linux defines; list based off of gcc output 354 DefineStd(Builder, "unix", Opts); 355 DefineStd(Builder, "linux", Opts); 356 Builder.defineMacro("__gnu_linux__"); 357 Builder.defineMacro("__ELF__"); 358 if (Triple.getEnvironment() == llvm::Triple::Android) 359 Builder.defineMacro("__ANDROID__", "1"); 360 if (Opts.POSIXThreads) 361 Builder.defineMacro("_REENTRANT"); 362 if (Opts.CPlusPlus) 363 Builder.defineMacro("_GNU_SOURCE"); 364 } 365 public: 366 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 367 this->UserLabelPrefix = ""; 368 this->WIntType = TargetInfo::UnsignedInt; 369 370 switch (Triple.getArch()) { 371 default: 372 break; 373 case llvm::Triple::ppc: 374 case llvm::Triple::ppc64: 375 case llvm::Triple::ppc64le: 376 this->MCountName = "_mcount"; 377 break; 378 } 379 } 380 381 const char *getStaticInitSectionSpecifier() const override { 382 return ".text.startup"; 383 } 384 }; 385 386 // NetBSD Target 387 template<typename Target> 388 class NetBSDTargetInfo : public OSTargetInfo<Target> { 389 protected: 390 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 391 MacroBuilder &Builder) const override { 392 // NetBSD defines; list based off of gcc output 393 Builder.defineMacro("__NetBSD__"); 394 Builder.defineMacro("__unix__"); 395 Builder.defineMacro("__ELF__"); 396 if (Opts.POSIXThreads) 397 Builder.defineMacro("_POSIX_THREADS"); 398 399 switch (Triple.getArch()) { 400 default: 401 break; 402 case llvm::Triple::arm: 403 case llvm::Triple::armeb: 404 case llvm::Triple::thumb: 405 case llvm::Triple::thumbeb: 406 Builder.defineMacro("__ARM_DWARF_EH__"); 407 break; 408 } 409 } 410 public: 411 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 412 this->UserLabelPrefix = ""; 413 } 414 }; 415 416 // OpenBSD Target 417 template<typename Target> 418 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 419 protected: 420 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 421 MacroBuilder &Builder) const override { 422 // OpenBSD defines; list based off of gcc output 423 424 Builder.defineMacro("__OpenBSD__"); 425 DefineStd(Builder, "unix", Opts); 426 Builder.defineMacro("__ELF__"); 427 if (Opts.POSIXThreads) 428 Builder.defineMacro("_REENTRANT"); 429 } 430 public: 431 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 432 this->UserLabelPrefix = ""; 433 this->TLSSupported = false; 434 435 switch (Triple.getArch()) { 436 default: 437 case llvm::Triple::x86: 438 case llvm::Triple::x86_64: 439 case llvm::Triple::arm: 440 case llvm::Triple::sparc: 441 this->MCountName = "__mcount"; 442 break; 443 case llvm::Triple::mips64: 444 case llvm::Triple::mips64el: 445 case llvm::Triple::ppc: 446 case llvm::Triple::sparcv9: 447 this->MCountName = "_mcount"; 448 break; 449 } 450 } 451 }; 452 453 // Bitrig Target 454 template<typename Target> 455 class BitrigTargetInfo : public OSTargetInfo<Target> { 456 protected: 457 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 458 MacroBuilder &Builder) const override { 459 // Bitrig defines; list based off of gcc output 460 461 Builder.defineMacro("__Bitrig__"); 462 DefineStd(Builder, "unix", Opts); 463 Builder.defineMacro("__ELF__"); 464 if (Opts.POSIXThreads) 465 Builder.defineMacro("_REENTRANT"); 466 } 467 public: 468 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 469 this->UserLabelPrefix = ""; 470 this->MCountName = "__mcount"; 471 } 472 }; 473 474 // PSP Target 475 template<typename Target> 476 class PSPTargetInfo : public OSTargetInfo<Target> { 477 protected: 478 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 479 MacroBuilder &Builder) const override { 480 // PSP defines; list based on the output of the pspdev gcc toolchain. 481 Builder.defineMacro("PSP"); 482 Builder.defineMacro("_PSP"); 483 Builder.defineMacro("__psp__"); 484 Builder.defineMacro("__ELF__"); 485 } 486 public: 487 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 488 this->UserLabelPrefix = ""; 489 } 490 }; 491 492 // PS3 PPU Target 493 template<typename Target> 494 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 495 protected: 496 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 497 MacroBuilder &Builder) const override { 498 // PS3 PPU defines. 499 Builder.defineMacro("__PPC__"); 500 Builder.defineMacro("__PPU__"); 501 Builder.defineMacro("__CELLOS_LV2__"); 502 Builder.defineMacro("__ELF__"); 503 Builder.defineMacro("__LP32__"); 504 Builder.defineMacro("_ARCH_PPC64"); 505 Builder.defineMacro("__powerpc64__"); 506 } 507 public: 508 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 509 this->UserLabelPrefix = ""; 510 this->LongWidth = this->LongAlign = 32; 511 this->PointerWidth = this->PointerAlign = 32; 512 this->IntMaxType = TargetInfo::SignedLongLong; 513 this->Int64Type = TargetInfo::SignedLongLong; 514 this->SizeType = TargetInfo::UnsignedInt; 515 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64"; 516 } 517 }; 518 519 // Solaris target 520 template<typename Target> 521 class SolarisTargetInfo : public OSTargetInfo<Target> { 522 protected: 523 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 524 MacroBuilder &Builder) const override { 525 DefineStd(Builder, "sun", Opts); 526 DefineStd(Builder, "unix", Opts); 527 Builder.defineMacro("__ELF__"); 528 Builder.defineMacro("__svr4__"); 529 Builder.defineMacro("__SVR4"); 530 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 531 // newer, but to 500 for everything else. feature_test.h has a check to 532 // ensure that you are not using C99 with an old version of X/Open or C89 533 // with a new version. 534 if (Opts.C99 || Opts.C11) 535 Builder.defineMacro("_XOPEN_SOURCE", "600"); 536 else 537 Builder.defineMacro("_XOPEN_SOURCE", "500"); 538 if (Opts.CPlusPlus) 539 Builder.defineMacro("__C99FEATURES__"); 540 Builder.defineMacro("_LARGEFILE_SOURCE"); 541 Builder.defineMacro("_LARGEFILE64_SOURCE"); 542 Builder.defineMacro("__EXTENSIONS__"); 543 Builder.defineMacro("_REENTRANT"); 544 } 545 public: 546 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 547 this->UserLabelPrefix = ""; 548 this->WCharType = this->SignedInt; 549 // FIXME: WIntType should be SignedLong 550 } 551 }; 552 553 // Windows target 554 template<typename Target> 555 class WindowsTargetInfo : public OSTargetInfo<Target> { 556 protected: 557 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 558 MacroBuilder &Builder) const override { 559 Builder.defineMacro("_WIN32"); 560 } 561 void getVisualStudioDefines(const LangOptions &Opts, 562 MacroBuilder &Builder) const { 563 if (Opts.CPlusPlus) { 564 if (Opts.RTTIData) 565 Builder.defineMacro("_CPPRTTI"); 566 567 if (Opts.Exceptions) 568 Builder.defineMacro("_CPPUNWIND"); 569 } 570 571 if (!Opts.CharIsSigned) 572 Builder.defineMacro("_CHAR_UNSIGNED"); 573 574 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 575 // but it works for now. 576 if (Opts.POSIXThreads) 577 Builder.defineMacro("_MT"); 578 579 if (Opts.MSCompatibilityVersion) { 580 Builder.defineMacro("_MSC_VER", 581 Twine(Opts.MSCompatibilityVersion / 100000)); 582 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 583 // FIXME We cannot encode the revision information into 32-bits 584 Builder.defineMacro("_MSC_BUILD", Twine(1)); 585 } 586 587 if (Opts.MicrosoftExt) { 588 Builder.defineMacro("_MSC_EXTENSIONS"); 589 590 if (Opts.CPlusPlus11) { 591 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 592 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 593 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 594 } 595 } 596 597 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 598 } 599 600 public: 601 WindowsTargetInfo(const llvm::Triple &Triple) 602 : OSTargetInfo<Target>(Triple) {} 603 }; 604 605 template <typename Target> 606 class NaClTargetInfo : public OSTargetInfo<Target> { 607 protected: 608 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 609 MacroBuilder &Builder) const override { 610 if (Opts.POSIXThreads) 611 Builder.defineMacro("_REENTRANT"); 612 if (Opts.CPlusPlus) 613 Builder.defineMacro("_GNU_SOURCE"); 614 615 DefineStd(Builder, "unix", Opts); 616 Builder.defineMacro("__ELF__"); 617 Builder.defineMacro("__native_client__"); 618 } 619 620 public: 621 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 622 this->UserLabelPrefix = ""; 623 this->LongAlign = 32; 624 this->LongWidth = 32; 625 this->PointerAlign = 32; 626 this->PointerWidth = 32; 627 this->IntMaxType = TargetInfo::SignedLongLong; 628 this->Int64Type = TargetInfo::SignedLongLong; 629 this->DoubleAlign = 64; 630 this->LongDoubleWidth = 64; 631 this->LongDoubleAlign = 64; 632 this->LongLongWidth = 64; 633 this->LongLongAlign = 64; 634 this->SizeType = TargetInfo::UnsignedInt; 635 this->PtrDiffType = TargetInfo::SignedInt; 636 this->IntPtrType = TargetInfo::SignedInt; 637 // RegParmMax is inherited from the underlying architecture 638 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 639 if (Triple.getArch() == llvm::Triple::arm) { 640 this->DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S128"; 641 } else if (Triple.getArch() == llvm::Triple::x86) { 642 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 643 } else if (Triple.getArch() == llvm::Triple::x86_64) { 644 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 645 } else if (Triple.getArch() == llvm::Triple::mipsel) { 646 // Handled on mips' setDescriptionString. 647 } else { 648 assert(Triple.getArch() == llvm::Triple::le32); 649 this->DescriptionString = "e-p:32:32-i64:64"; 650 } 651 } 652 typename Target::CallingConvCheckResult checkCallingConvention( 653 CallingConv CC) const override { 654 return CC == CC_PnaclCall ? Target::CCCR_OK : 655 Target::checkCallingConvention(CC); 656 } 657 }; 658 } // end anonymous namespace. 659 660 //===----------------------------------------------------------------------===// 661 // Specific target implementations. 662 //===----------------------------------------------------------------------===// 663 664 namespace { 665 // PPC abstract base class 666 class PPCTargetInfo : public TargetInfo { 667 static const Builtin::Info BuiltinInfo[]; 668 static const char * const GCCRegNames[]; 669 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 670 std::string CPU; 671 672 // Target cpu features. 673 bool HasVSX; 674 675 protected: 676 std::string ABI; 677 678 public: 679 PPCTargetInfo(const llvm::Triple &Triple) 680 : TargetInfo(Triple), HasVSX(false) { 681 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 682 LongDoubleWidth = LongDoubleAlign = 128; 683 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 684 } 685 686 /// \brief Flags for architecture specific defines. 687 typedef enum { 688 ArchDefineNone = 0, 689 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 690 ArchDefinePpcgr = 1 << 1, 691 ArchDefinePpcsq = 1 << 2, 692 ArchDefine440 = 1 << 3, 693 ArchDefine603 = 1 << 4, 694 ArchDefine604 = 1 << 5, 695 ArchDefinePwr4 = 1 << 6, 696 ArchDefinePwr5 = 1 << 7, 697 ArchDefinePwr5x = 1 << 8, 698 ArchDefinePwr6 = 1 << 9, 699 ArchDefinePwr6x = 1 << 10, 700 ArchDefinePwr7 = 1 << 11, 701 ArchDefinePwr8 = 1 << 12, 702 ArchDefineA2 = 1 << 13, 703 ArchDefineA2q = 1 << 14 704 } ArchDefineTypes; 705 706 // Note: GCC recognizes the following additional cpus: 707 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 708 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 709 // titan, rs64. 710 bool setCPU(const std::string &Name) override { 711 bool CPUKnown = llvm::StringSwitch<bool>(Name) 712 .Case("generic", true) 713 .Case("440", true) 714 .Case("450", true) 715 .Case("601", true) 716 .Case("602", true) 717 .Case("603", true) 718 .Case("603e", true) 719 .Case("603ev", true) 720 .Case("604", true) 721 .Case("604e", true) 722 .Case("620", true) 723 .Case("630", true) 724 .Case("g3", true) 725 .Case("7400", true) 726 .Case("g4", true) 727 .Case("7450", true) 728 .Case("g4+", true) 729 .Case("750", true) 730 .Case("970", true) 731 .Case("g5", true) 732 .Case("a2", true) 733 .Case("a2q", true) 734 .Case("e500mc", true) 735 .Case("e5500", true) 736 .Case("power3", true) 737 .Case("pwr3", true) 738 .Case("power4", true) 739 .Case("pwr4", true) 740 .Case("power5", true) 741 .Case("pwr5", true) 742 .Case("power5x", true) 743 .Case("pwr5x", true) 744 .Case("power6", true) 745 .Case("pwr6", true) 746 .Case("power6x", true) 747 .Case("pwr6x", true) 748 .Case("power7", true) 749 .Case("pwr7", true) 750 .Case("power8", true) 751 .Case("pwr8", true) 752 .Case("powerpc", true) 753 .Case("ppc", true) 754 .Case("powerpc64", true) 755 .Case("ppc64", true) 756 .Case("powerpc64le", true) 757 .Case("ppc64le", true) 758 .Default(false); 759 760 if (CPUKnown) 761 CPU = Name; 762 763 return CPUKnown; 764 } 765 766 767 StringRef getABI() const override { return ABI; } 768 769 void getTargetBuiltins(const Builtin::Info *&Records, 770 unsigned &NumRecords) const override { 771 Records = BuiltinInfo; 772 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 773 } 774 775 bool isCLZForZeroUndef() const override { return false; } 776 777 void getTargetDefines(const LangOptions &Opts, 778 MacroBuilder &Builder) const override; 779 780 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 781 782 bool handleTargetFeatures(std::vector<std::string> &Features, 783 DiagnosticsEngine &Diags) override; 784 bool hasFeature(StringRef Feature) const override; 785 786 void getGCCRegNames(const char * const *&Names, 787 unsigned &NumNames) const override; 788 void getGCCRegAliases(const GCCRegAlias *&Aliases, 789 unsigned &NumAliases) const override; 790 bool validateAsmConstraint(const char *&Name, 791 TargetInfo::ConstraintInfo &Info) const override { 792 switch (*Name) { 793 default: return false; 794 case 'O': // Zero 795 break; 796 case 'b': // Base register 797 case 'f': // Floating point register 798 Info.setAllowsRegister(); 799 break; 800 // FIXME: The following are added to allow parsing. 801 // I just took a guess at what the actions should be. 802 // Also, is more specific checking needed? I.e. specific registers? 803 case 'd': // Floating point register (containing 64-bit value) 804 case 'v': // Altivec vector register 805 Info.setAllowsRegister(); 806 break; 807 case 'w': 808 switch (Name[1]) { 809 case 'd':// VSX vector register to hold vector double data 810 case 'f':// VSX vector register to hold vector float data 811 case 's':// VSX vector register to hold scalar float data 812 case 'a':// Any VSX register 813 case 'c':// An individual CR bit 814 break; 815 default: 816 return false; 817 } 818 Info.setAllowsRegister(); 819 Name++; // Skip over 'w'. 820 break; 821 case 'h': // `MQ', `CTR', or `LINK' register 822 case 'q': // `MQ' register 823 case 'c': // `CTR' register 824 case 'l': // `LINK' register 825 case 'x': // `CR' register (condition register) number 0 826 case 'y': // `CR' register (condition register) 827 case 'z': // `XER[CA]' carry bit (part of the XER register) 828 Info.setAllowsRegister(); 829 break; 830 case 'I': // Signed 16-bit constant 831 case 'J': // Unsigned 16-bit constant shifted left 16 bits 832 // (use `L' instead for SImode constants) 833 case 'K': // Unsigned 16-bit constant 834 case 'L': // Signed 16-bit constant shifted left 16 bits 835 case 'M': // Constant larger than 31 836 case 'N': // Exact power of 2 837 case 'P': // Constant whose negation is a signed 16-bit constant 838 case 'G': // Floating point constant that can be loaded into a 839 // register with one instruction per word 840 case 'H': // Integer/Floating point constant that can be loaded 841 // into a register using three instructions 842 break; 843 case 'm': // Memory operand. Note that on PowerPC targets, m can 844 // include addresses that update the base register. It 845 // is therefore only safe to use `m' in an asm statement 846 // if that asm statement accesses the operand exactly once. 847 // The asm statement must also use `%U<opno>' as a 848 // placeholder for the "update" flag in the corresponding 849 // load or store instruction. For example: 850 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 851 // is correct but: 852 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 853 // is not. Use es rather than m if you don't want the base 854 // register to be updated. 855 case 'e': 856 if (Name[1] != 's') 857 return false; 858 // es: A "stable" memory operand; that is, one which does not 859 // include any automodification of the base register. Unlike 860 // `m', this constraint can be used in asm statements that 861 // might access the operand several times, or that might not 862 // access it at all. 863 Info.setAllowsMemory(); 864 Name++; // Skip over 'e'. 865 break; 866 case 'Q': // Memory operand that is an offset from a register (it is 867 // usually better to use `m' or `es' in asm statements) 868 case 'Z': // Memory operand that is an indexed or indirect from a 869 // register (it is usually better to use `m' or `es' in 870 // asm statements) 871 Info.setAllowsMemory(); 872 Info.setAllowsRegister(); 873 break; 874 case 'R': // AIX TOC entry 875 case 'a': // Address operand that is an indexed or indirect from a 876 // register (`p' is preferable for asm statements) 877 case 'S': // Constant suitable as a 64-bit mask operand 878 case 'T': // Constant suitable as a 32-bit mask operand 879 case 'U': // System V Release 4 small data area reference 880 case 't': // AND masks that can be performed by two rldic{l, r} 881 // instructions 882 case 'W': // Vector constant that does not require memory 883 case 'j': // Vector constant that is all zeros. 884 break; 885 // End FIXME. 886 } 887 return true; 888 } 889 std::string convertConstraint(const char *&Constraint) const override { 890 std::string R; 891 switch (*Constraint) { 892 case 'e': 893 case 'w': 894 // Two-character constraint; add "^" hint for later parsing. 895 R = std::string("^") + std::string(Constraint, 2); 896 Constraint++; 897 break; 898 default: 899 return TargetInfo::convertConstraint(Constraint); 900 } 901 return R; 902 } 903 const char *getClobbers() const override { 904 return ""; 905 } 906 int getEHDataRegisterNumber(unsigned RegNo) const override { 907 if (RegNo == 0) return 3; 908 if (RegNo == 1) return 4; 909 return -1; 910 } 911 }; 912 913 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 914 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 915 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 916 ALL_LANGUAGES }, 917 #include "clang/Basic/BuiltinsPPC.def" 918 }; 919 920 /// handleTargetFeatures - Perform initialization based on the user 921 /// configured set of features. 922 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 923 DiagnosticsEngine &Diags) { 924 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 925 // Ignore disabled features. 926 if (Features[i][0] == '-') 927 continue; 928 929 StringRef Feature = StringRef(Features[i]).substr(1); 930 931 if (Feature == "vsx") { 932 HasVSX = true; 933 continue; 934 } 935 936 // TODO: Finish this list and add an assert that we've handled them 937 // all. 938 } 939 940 return true; 941 } 942 943 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 944 /// #defines that are not tied to a specific subtarget. 945 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 946 MacroBuilder &Builder) const { 947 // Target identification. 948 Builder.defineMacro("__ppc__"); 949 Builder.defineMacro("__PPC__"); 950 Builder.defineMacro("_ARCH_PPC"); 951 Builder.defineMacro("__powerpc__"); 952 Builder.defineMacro("__POWERPC__"); 953 if (PointerWidth == 64) { 954 Builder.defineMacro("_ARCH_PPC64"); 955 Builder.defineMacro("__powerpc64__"); 956 Builder.defineMacro("__ppc64__"); 957 Builder.defineMacro("__PPC64__"); 958 } 959 960 // Target properties. 961 if (getTriple().getArch() == llvm::Triple::ppc64le) { 962 Builder.defineMacro("_LITTLE_ENDIAN"); 963 } else { 964 if (getTriple().getOS() != llvm::Triple::NetBSD && 965 getTriple().getOS() != llvm::Triple::OpenBSD) 966 Builder.defineMacro("_BIG_ENDIAN"); 967 } 968 969 // ABI options. 970 if (ABI == "elfv1") 971 Builder.defineMacro("_CALL_ELF", "1"); 972 if (ABI == "elfv2") 973 Builder.defineMacro("_CALL_ELF", "2"); 974 975 // Subtarget options. 976 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 977 Builder.defineMacro("__REGISTER_PREFIX__", ""); 978 979 // FIXME: Should be controlled by command line option. 980 if (LongDoubleWidth == 128) 981 Builder.defineMacro("__LONG_DOUBLE_128__"); 982 983 if (Opts.AltiVec) { 984 Builder.defineMacro("__VEC__", "10206"); 985 Builder.defineMacro("__ALTIVEC__"); 986 } 987 988 // CPU identification. 989 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 990 .Case("440", ArchDefineName) 991 .Case("450", ArchDefineName | ArchDefine440) 992 .Case("601", ArchDefineName) 993 .Case("602", ArchDefineName | ArchDefinePpcgr) 994 .Case("603", ArchDefineName | ArchDefinePpcgr) 995 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 996 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 997 .Case("604", ArchDefineName | ArchDefinePpcgr) 998 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 999 .Case("620", ArchDefineName | ArchDefinePpcgr) 1000 .Case("630", ArchDefineName | ArchDefinePpcgr) 1001 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1002 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1003 .Case("750", ArchDefineName | ArchDefinePpcgr) 1004 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1005 | ArchDefinePpcsq) 1006 .Case("a2", ArchDefineA2) 1007 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1008 .Case("pwr3", ArchDefinePpcgr) 1009 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1010 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1011 | ArchDefinePpcsq) 1012 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1013 | ArchDefinePpcgr | ArchDefinePpcsq) 1014 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1015 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1016 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1017 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1018 | ArchDefinePpcsq) 1019 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1020 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1021 | ArchDefinePpcgr | ArchDefinePpcsq) 1022 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1023 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1024 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1025 .Case("power3", ArchDefinePpcgr) 1026 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1027 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1028 | ArchDefinePpcsq) 1029 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1030 | ArchDefinePpcgr | ArchDefinePpcsq) 1031 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1032 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1033 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1034 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1035 | ArchDefinePpcsq) 1036 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1037 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1038 | ArchDefinePpcgr | ArchDefinePpcsq) 1039 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1040 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1041 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1042 .Default(ArchDefineNone); 1043 1044 if (defs & ArchDefineName) 1045 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1046 if (defs & ArchDefinePpcgr) 1047 Builder.defineMacro("_ARCH_PPCGR"); 1048 if (defs & ArchDefinePpcsq) 1049 Builder.defineMacro("_ARCH_PPCSQ"); 1050 if (defs & ArchDefine440) 1051 Builder.defineMacro("_ARCH_440"); 1052 if (defs & ArchDefine603) 1053 Builder.defineMacro("_ARCH_603"); 1054 if (defs & ArchDefine604) 1055 Builder.defineMacro("_ARCH_604"); 1056 if (defs & ArchDefinePwr4) 1057 Builder.defineMacro("_ARCH_PWR4"); 1058 if (defs & ArchDefinePwr5) 1059 Builder.defineMacro("_ARCH_PWR5"); 1060 if (defs & ArchDefinePwr5x) 1061 Builder.defineMacro("_ARCH_PWR5X"); 1062 if (defs & ArchDefinePwr6) 1063 Builder.defineMacro("_ARCH_PWR6"); 1064 if (defs & ArchDefinePwr6x) 1065 Builder.defineMacro("_ARCH_PWR6X"); 1066 if (defs & ArchDefinePwr7) 1067 Builder.defineMacro("_ARCH_PWR7"); 1068 if (defs & ArchDefinePwr8) 1069 Builder.defineMacro("_ARCH_PWR8"); 1070 if (defs & ArchDefineA2) 1071 Builder.defineMacro("_ARCH_A2"); 1072 if (defs & ArchDefineA2q) { 1073 Builder.defineMacro("_ARCH_A2Q"); 1074 Builder.defineMacro("_ARCH_QP"); 1075 } 1076 1077 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1078 Builder.defineMacro("__bg__"); 1079 Builder.defineMacro("__THW_BLUEGENE__"); 1080 Builder.defineMacro("__bgq__"); 1081 Builder.defineMacro("__TOS_BGQ__"); 1082 } 1083 1084 if (HasVSX) 1085 Builder.defineMacro("__VSX__"); 1086 1087 // FIXME: The following are not yet generated here by Clang, but are 1088 // generated by GCC: 1089 // 1090 // _SOFT_FLOAT_ 1091 // __RECIP_PRECISION__ 1092 // __APPLE_ALTIVEC__ 1093 // __RECIP__ 1094 // __RECIPF__ 1095 // __RSQRTE__ 1096 // __RSQRTEF__ 1097 // _SOFT_DOUBLE_ 1098 // __NO_LWSYNC__ 1099 // __HAVE_BSWAP__ 1100 // __LONGDOUBLE128 1101 // __CMODEL_MEDIUM__ 1102 // __CMODEL_LARGE__ 1103 // _CALL_SYSV 1104 // _CALL_DARWIN 1105 // __NO_FPRS__ 1106 } 1107 1108 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1109 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1110 .Case("7400", true) 1111 .Case("g4", true) 1112 .Case("7450", true) 1113 .Case("g4+", true) 1114 .Case("970", true) 1115 .Case("g5", true) 1116 .Case("pwr6", true) 1117 .Case("pwr7", true) 1118 .Case("pwr8", true) 1119 .Case("ppc64", true) 1120 .Case("ppc64le", true) 1121 .Default(false); 1122 1123 Features["qpx"] = (CPU == "a2q"); 1124 1125 if (!ABI.empty()) 1126 Features[ABI] = true; 1127 } 1128 1129 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1130 return Feature == "powerpc"; 1131 } 1132 1133 1134 const char * const PPCTargetInfo::GCCRegNames[] = { 1135 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1136 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1137 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1138 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1139 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1140 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1141 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1142 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1143 "mq", "lr", "ctr", "ap", 1144 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1145 "xer", 1146 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1147 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1148 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1149 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1150 "vrsave", "vscr", 1151 "spe_acc", "spefscr", 1152 "sfp" 1153 }; 1154 1155 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1156 unsigned &NumNames) const { 1157 Names = GCCRegNames; 1158 NumNames = llvm::array_lengthof(GCCRegNames); 1159 } 1160 1161 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1162 // While some of these aliases do map to different registers 1163 // they still share the same register name. 1164 { { "0" }, "r0" }, 1165 { { "1"}, "r1" }, 1166 { { "2" }, "r2" }, 1167 { { "3" }, "r3" }, 1168 { { "4" }, "r4" }, 1169 { { "5" }, "r5" }, 1170 { { "6" }, "r6" }, 1171 { { "7" }, "r7" }, 1172 { { "8" }, "r8" }, 1173 { { "9" }, "r9" }, 1174 { { "10" }, "r10" }, 1175 { { "11" }, "r11" }, 1176 { { "12" }, "r12" }, 1177 { { "13" }, "r13" }, 1178 { { "14" }, "r14" }, 1179 { { "15" }, "r15" }, 1180 { { "16" }, "r16" }, 1181 { { "17" }, "r17" }, 1182 { { "18" }, "r18" }, 1183 { { "19" }, "r19" }, 1184 { { "20" }, "r20" }, 1185 { { "21" }, "r21" }, 1186 { { "22" }, "r22" }, 1187 { { "23" }, "r23" }, 1188 { { "24" }, "r24" }, 1189 { { "25" }, "r25" }, 1190 { { "26" }, "r26" }, 1191 { { "27" }, "r27" }, 1192 { { "28" }, "r28" }, 1193 { { "29" }, "r29" }, 1194 { { "30" }, "r30" }, 1195 { { "31" }, "r31" }, 1196 { { "fr0" }, "f0" }, 1197 { { "fr1" }, "f1" }, 1198 { { "fr2" }, "f2" }, 1199 { { "fr3" }, "f3" }, 1200 { { "fr4" }, "f4" }, 1201 { { "fr5" }, "f5" }, 1202 { { "fr6" }, "f6" }, 1203 { { "fr7" }, "f7" }, 1204 { { "fr8" }, "f8" }, 1205 { { "fr9" }, "f9" }, 1206 { { "fr10" }, "f10" }, 1207 { { "fr11" }, "f11" }, 1208 { { "fr12" }, "f12" }, 1209 { { "fr13" }, "f13" }, 1210 { { "fr14" }, "f14" }, 1211 { { "fr15" }, "f15" }, 1212 { { "fr16" }, "f16" }, 1213 { { "fr17" }, "f17" }, 1214 { { "fr18" }, "f18" }, 1215 { { "fr19" }, "f19" }, 1216 { { "fr20" }, "f20" }, 1217 { { "fr21" }, "f21" }, 1218 { { "fr22" }, "f22" }, 1219 { { "fr23" }, "f23" }, 1220 { { "fr24" }, "f24" }, 1221 { { "fr25" }, "f25" }, 1222 { { "fr26" }, "f26" }, 1223 { { "fr27" }, "f27" }, 1224 { { "fr28" }, "f28" }, 1225 { { "fr29" }, "f29" }, 1226 { { "fr30" }, "f30" }, 1227 { { "fr31" }, "f31" }, 1228 { { "cc" }, "cr0" }, 1229 }; 1230 1231 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1232 unsigned &NumAliases) const { 1233 Aliases = GCCRegAliases; 1234 NumAliases = llvm::array_lengthof(GCCRegAliases); 1235 } 1236 } // end anonymous namespace. 1237 1238 namespace { 1239 class PPC32TargetInfo : public PPCTargetInfo { 1240 public: 1241 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1242 DescriptionString = "E-m:e-p:32:32-i64:64-n32"; 1243 1244 switch (getTriple().getOS()) { 1245 case llvm::Triple::Linux: 1246 case llvm::Triple::FreeBSD: 1247 case llvm::Triple::NetBSD: 1248 SizeType = UnsignedInt; 1249 PtrDiffType = SignedInt; 1250 IntPtrType = SignedInt; 1251 break; 1252 default: 1253 break; 1254 } 1255 1256 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1257 LongDoubleWidth = LongDoubleAlign = 64; 1258 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1259 } 1260 1261 // PPC32 supports atomics up to 4 bytes. 1262 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1263 } 1264 1265 BuiltinVaListKind getBuiltinVaListKind() const override { 1266 // This is the ELF definition, and is overridden by the Darwin sub-target 1267 return TargetInfo::PowerABIBuiltinVaList; 1268 } 1269 }; 1270 } // end anonymous namespace. 1271 1272 // Note: ABI differences may eventually require us to have a separate 1273 // TargetInfo for little endian. 1274 namespace { 1275 class PPC64TargetInfo : public PPCTargetInfo { 1276 public: 1277 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1278 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1279 IntMaxType = SignedLong; 1280 Int64Type = SignedLong; 1281 1282 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1283 LongDoubleWidth = LongDoubleAlign = 64; 1284 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1285 DescriptionString = "E-m:e-i64:64-n32:64"; 1286 } else { 1287 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1288 DescriptionString = "e-m:e-i64:64-n32:64"; 1289 ABI = "elfv2"; 1290 } else { 1291 DescriptionString = "E-m:e-i64:64-n32:64"; 1292 ABI = "elfv1"; 1293 } 1294 } 1295 1296 // PPC64 supports atomics up to 8 bytes. 1297 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1298 } 1299 BuiltinVaListKind getBuiltinVaListKind() const override { 1300 return TargetInfo::CharPtrBuiltinVaList; 1301 } 1302 // PPC64 Linux-specifc ABI options. 1303 bool setABI(const std::string &Name) override { 1304 if (Name == "elfv1" || Name == "elfv2") { 1305 ABI = Name; 1306 return true; 1307 } 1308 return false; 1309 } 1310 }; 1311 } // end anonymous namespace. 1312 1313 1314 namespace { 1315 class DarwinPPC32TargetInfo : 1316 public DarwinTargetInfo<PPC32TargetInfo> { 1317 public: 1318 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1319 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1320 HasAlignMac68kSupport = true; 1321 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1322 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1323 LongLongAlign = 32; 1324 SuitableAlign = 128; 1325 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; 1326 } 1327 BuiltinVaListKind getBuiltinVaListKind() const override { 1328 return TargetInfo::CharPtrBuiltinVaList; 1329 } 1330 }; 1331 1332 class DarwinPPC64TargetInfo : 1333 public DarwinTargetInfo<PPC64TargetInfo> { 1334 public: 1335 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1336 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1337 HasAlignMac68kSupport = true; 1338 SuitableAlign = 128; 1339 DescriptionString = "E-m:o-i64:64-n32:64"; 1340 } 1341 }; 1342 } // end anonymous namespace. 1343 1344 namespace { 1345 static const unsigned NVPTXAddrSpaceMap[] = { 1346 1, // opencl_global 1347 3, // opencl_local 1348 4, // opencl_constant 1349 1, // cuda_device 1350 4, // cuda_constant 1351 3, // cuda_shared 1352 }; 1353 class NVPTXTargetInfo : public TargetInfo { 1354 static const char * const GCCRegNames[]; 1355 static const Builtin::Info BuiltinInfo[]; 1356 public: 1357 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1358 BigEndian = false; 1359 TLSSupported = false; 1360 LongWidth = LongAlign = 64; 1361 AddrSpaceMap = &NVPTXAddrSpaceMap; 1362 UseAddrSpaceMapMangling = true; 1363 // Define available target features 1364 // These must be defined in sorted order! 1365 NoAsmVariants = true; 1366 } 1367 void getTargetDefines(const LangOptions &Opts, 1368 MacroBuilder &Builder) const override { 1369 Builder.defineMacro("__PTX__"); 1370 Builder.defineMacro("__NVPTX__"); 1371 } 1372 void getTargetBuiltins(const Builtin::Info *&Records, 1373 unsigned &NumRecords) const override { 1374 Records = BuiltinInfo; 1375 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1376 } 1377 bool hasFeature(StringRef Feature) const override { 1378 return Feature == "ptx" || Feature == "nvptx"; 1379 } 1380 1381 void getGCCRegNames(const char * const *&Names, 1382 unsigned &NumNames) const override; 1383 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1384 unsigned &NumAliases) const override { 1385 // No aliases. 1386 Aliases = nullptr; 1387 NumAliases = 0; 1388 } 1389 bool validateAsmConstraint(const char *&Name, 1390 TargetInfo::ConstraintInfo &Info) const override { 1391 switch (*Name) { 1392 default: return false; 1393 case 'c': 1394 case 'h': 1395 case 'r': 1396 case 'l': 1397 case 'f': 1398 case 'd': 1399 Info.setAllowsRegister(); 1400 return true; 1401 } 1402 } 1403 const char *getClobbers() const override { 1404 // FIXME: Is this really right? 1405 return ""; 1406 } 1407 BuiltinVaListKind getBuiltinVaListKind() const override { 1408 // FIXME: implement 1409 return TargetInfo::CharPtrBuiltinVaList; 1410 } 1411 bool setCPU(const std::string &Name) override { 1412 bool Valid = llvm::StringSwitch<bool>(Name) 1413 .Case("sm_20", true) 1414 .Case("sm_21", true) 1415 .Case("sm_30", true) 1416 .Case("sm_35", true) 1417 .Default(false); 1418 1419 return Valid; 1420 } 1421 }; 1422 1423 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1424 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1425 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1426 ALL_LANGUAGES }, 1427 #include "clang/Basic/BuiltinsNVPTX.def" 1428 }; 1429 1430 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1431 "r0" 1432 }; 1433 1434 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1435 unsigned &NumNames) const { 1436 Names = GCCRegNames; 1437 NumNames = llvm::array_lengthof(GCCRegNames); 1438 } 1439 1440 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1441 public: 1442 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1443 PointerWidth = PointerAlign = 32; 1444 SizeType = PtrDiffType = TargetInfo::UnsignedInt; 1445 IntPtrType = TargetInfo::SignedInt; 1446 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1447 } 1448 }; 1449 1450 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1451 public: 1452 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1453 PointerWidth = PointerAlign = 64; 1454 SizeType = PtrDiffType = TargetInfo::UnsignedLongLong; 1455 IntPtrType = TargetInfo::SignedLongLong; 1456 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1457 } 1458 }; 1459 } 1460 1461 namespace { 1462 1463 static const unsigned R600AddrSpaceMap[] = { 1464 1, // opencl_global 1465 3, // opencl_local 1466 2, // opencl_constant 1467 1, // cuda_device 1468 2, // cuda_constant 1469 3 // cuda_shared 1470 }; 1471 1472 // If you edit the description strings, make sure you update 1473 // getPointerWidthV(). 1474 1475 static const char *DescriptionStringR600 = 1476 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1477 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1478 1479 static const char *DescriptionStringR600DoubleOps = 1480 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1481 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1482 1483 static const char *DescriptionStringSI = 1484 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1485 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1486 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1487 1488 class R600TargetInfo : public TargetInfo { 1489 static const Builtin::Info BuiltinInfo[]; 1490 1491 /// \brief The GPU profiles supported by the R600 target. 1492 enum GPUKind { 1493 GK_NONE, 1494 GK_R600, 1495 GK_R600_DOUBLE_OPS, 1496 GK_R700, 1497 GK_R700_DOUBLE_OPS, 1498 GK_EVERGREEN, 1499 GK_EVERGREEN_DOUBLE_OPS, 1500 GK_NORTHERN_ISLANDS, 1501 GK_CAYMAN, 1502 GK_SOUTHERN_ISLANDS, 1503 GK_SEA_ISLANDS 1504 } GPU; 1505 1506 public: 1507 R600TargetInfo(const llvm::Triple &Triple) 1508 : TargetInfo(Triple), GPU(GK_R600) { 1509 DescriptionString = DescriptionStringR600; 1510 AddrSpaceMap = &R600AddrSpaceMap; 1511 UseAddrSpaceMapMangling = true; 1512 } 1513 1514 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1515 if (GPU <= GK_CAYMAN) 1516 return 32; 1517 1518 switch(AddrSpace) { 1519 default: 1520 return 64; 1521 case 0: 1522 case 3: 1523 case 5: 1524 return 32; 1525 } 1526 } 1527 1528 const char * getClobbers() const override { 1529 return ""; 1530 } 1531 1532 void getGCCRegNames(const char * const *&Names, 1533 unsigned &numNames) const override { 1534 Names = nullptr; 1535 numNames = 0; 1536 } 1537 1538 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1539 unsigned &NumAliases) const override { 1540 Aliases = nullptr; 1541 NumAliases = 0; 1542 } 1543 1544 bool validateAsmConstraint(const char *&Name, 1545 TargetInfo::ConstraintInfo &info) const override { 1546 return true; 1547 } 1548 1549 void getTargetBuiltins(const Builtin::Info *&Records, 1550 unsigned &NumRecords) const override { 1551 Records = BuiltinInfo; 1552 NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin; 1553 } 1554 1555 void getTargetDefines(const LangOptions &Opts, 1556 MacroBuilder &Builder) const override { 1557 Builder.defineMacro("__R600__"); 1558 } 1559 1560 BuiltinVaListKind getBuiltinVaListKind() const override { 1561 return TargetInfo::CharPtrBuiltinVaList; 1562 } 1563 1564 bool setCPU(const std::string &Name) override { 1565 GPU = llvm::StringSwitch<GPUKind>(Name) 1566 .Case("r600" , GK_R600) 1567 .Case("rv610", GK_R600) 1568 .Case("rv620", GK_R600) 1569 .Case("rv630", GK_R600) 1570 .Case("rv635", GK_R600) 1571 .Case("rs780", GK_R600) 1572 .Case("rs880", GK_R600) 1573 .Case("rv670", GK_R600_DOUBLE_OPS) 1574 .Case("rv710", GK_R700) 1575 .Case("rv730", GK_R700) 1576 .Case("rv740", GK_R700_DOUBLE_OPS) 1577 .Case("rv770", GK_R700_DOUBLE_OPS) 1578 .Case("palm", GK_EVERGREEN) 1579 .Case("cedar", GK_EVERGREEN) 1580 .Case("sumo", GK_EVERGREEN) 1581 .Case("sumo2", GK_EVERGREEN) 1582 .Case("redwood", GK_EVERGREEN) 1583 .Case("juniper", GK_EVERGREEN) 1584 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1585 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1586 .Case("barts", GK_NORTHERN_ISLANDS) 1587 .Case("turks", GK_NORTHERN_ISLANDS) 1588 .Case("caicos", GK_NORTHERN_ISLANDS) 1589 .Case("cayman", GK_CAYMAN) 1590 .Case("aruba", GK_CAYMAN) 1591 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1592 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1593 .Case("verde", GK_SOUTHERN_ISLANDS) 1594 .Case("oland", GK_SOUTHERN_ISLANDS) 1595 .Case("hainan", GK_SOUTHERN_ISLANDS) 1596 .Case("bonaire", GK_SEA_ISLANDS) 1597 .Case("kabini", GK_SEA_ISLANDS) 1598 .Case("kaveri", GK_SEA_ISLANDS) 1599 .Case("hawaii", GK_SEA_ISLANDS) 1600 .Case("mullins", GK_SEA_ISLANDS) 1601 .Default(GK_NONE); 1602 1603 if (GPU == GK_NONE) { 1604 return false; 1605 } 1606 1607 // Set the correct data layout 1608 switch (GPU) { 1609 case GK_NONE: 1610 case GK_R600: 1611 case GK_R700: 1612 case GK_EVERGREEN: 1613 case GK_NORTHERN_ISLANDS: 1614 DescriptionString = DescriptionStringR600; 1615 break; 1616 case GK_R600_DOUBLE_OPS: 1617 case GK_R700_DOUBLE_OPS: 1618 case GK_EVERGREEN_DOUBLE_OPS: 1619 case GK_CAYMAN: 1620 DescriptionString = DescriptionStringR600DoubleOps; 1621 break; 1622 case GK_SOUTHERN_ISLANDS: 1623 case GK_SEA_ISLANDS: 1624 DescriptionString = DescriptionStringSI; 1625 break; 1626 } 1627 1628 return true; 1629 } 1630 }; 1631 1632 const Builtin::Info R600TargetInfo::BuiltinInfo[] = { 1633 #define BUILTIN(ID, TYPE, ATTRS) \ 1634 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1635 #include "clang/Basic/BuiltinsR600.def" 1636 }; 1637 1638 } // end anonymous namespace 1639 1640 namespace { 1641 // Namespace for x86 abstract base class 1642 const Builtin::Info BuiltinInfo[] = { 1643 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1644 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1645 ALL_LANGUAGES }, 1646 #include "clang/Basic/BuiltinsX86.def" 1647 }; 1648 1649 static const char* const GCCRegNames[] = { 1650 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1651 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1652 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1653 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1654 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1655 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1656 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1657 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1658 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1659 }; 1660 1661 const TargetInfo::AddlRegName AddlRegNames[] = { 1662 { { "al", "ah", "eax", "rax" }, 0 }, 1663 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1664 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1665 { { "dl", "dh", "edx", "rdx" }, 1 }, 1666 { { "esi", "rsi" }, 4 }, 1667 { { "edi", "rdi" }, 5 }, 1668 { { "esp", "rsp" }, 7 }, 1669 { { "ebp", "rbp" }, 6 }, 1670 }; 1671 1672 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1673 // most of the implementation can be shared. 1674 class X86TargetInfo : public TargetInfo { 1675 enum X86SSEEnum { 1676 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1677 } SSELevel; 1678 enum MMX3DNowEnum { 1679 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1680 } MMX3DNowLevel; 1681 enum XOPEnum { 1682 NoXOP, 1683 SSE4A, 1684 FMA4, 1685 XOP 1686 } XOPLevel; 1687 1688 bool HasAES; 1689 bool HasPCLMUL; 1690 bool HasLZCNT; 1691 bool HasRDRND; 1692 bool HasBMI; 1693 bool HasBMI2; 1694 bool HasPOPCNT; 1695 bool HasRTM; 1696 bool HasPRFCHW; 1697 bool HasRDSEED; 1698 bool HasTBM; 1699 bool HasFMA; 1700 bool HasF16C; 1701 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW, HasAVX512VL; 1702 bool HasSHA; 1703 bool HasCX16; 1704 1705 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1706 /// 1707 /// Each enumeration represents a particular CPU supported by Clang. These 1708 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1709 enum CPUKind { 1710 CK_Generic, 1711 1712 /// \name i386 1713 /// i386-generation processors. 1714 //@{ 1715 CK_i386, 1716 //@} 1717 1718 /// \name i486 1719 /// i486-generation processors. 1720 //@{ 1721 CK_i486, 1722 CK_WinChipC6, 1723 CK_WinChip2, 1724 CK_C3, 1725 //@} 1726 1727 /// \name i586 1728 /// i586-generation processors, P5 microarchitecture based. 1729 //@{ 1730 CK_i586, 1731 CK_Pentium, 1732 CK_PentiumMMX, 1733 //@} 1734 1735 /// \name i686 1736 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1737 //@{ 1738 CK_i686, 1739 CK_PentiumPro, 1740 CK_Pentium2, 1741 CK_Pentium3, 1742 CK_Pentium3M, 1743 CK_PentiumM, 1744 CK_C3_2, 1745 1746 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1747 /// Clang however has some logic to suport this. 1748 // FIXME: Warn, deprecate, and potentially remove this. 1749 CK_Yonah, 1750 //@} 1751 1752 /// \name Netburst 1753 /// Netburst microarchitecture based processors. 1754 //@{ 1755 CK_Pentium4, 1756 CK_Pentium4M, 1757 CK_Prescott, 1758 CK_Nocona, 1759 //@} 1760 1761 /// \name Core 1762 /// Core microarchitecture based processors. 1763 //@{ 1764 CK_Core2, 1765 1766 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1767 /// codename which GCC no longer accepts as an option to -march, but Clang 1768 /// has some logic for recognizing it. 1769 // FIXME: Warn, deprecate, and potentially remove this. 1770 CK_Penryn, 1771 //@} 1772 1773 /// \name Atom 1774 /// Atom processors 1775 //@{ 1776 CK_Atom, 1777 CK_Silvermont, 1778 //@} 1779 1780 /// \name Nehalem 1781 /// Nehalem microarchitecture based processors. 1782 //@{ 1783 CK_Corei7, 1784 CK_Corei7AVX, 1785 CK_CoreAVXi, 1786 CK_CoreAVX2, 1787 //@} 1788 1789 /// \name Knights Landing 1790 /// Knights Landing processor. 1791 CK_KNL, 1792 1793 /// \name Skylake Server 1794 /// Skylake server processor. 1795 CK_SKX, 1796 1797 /// \name K6 1798 /// K6 architecture processors. 1799 //@{ 1800 CK_K6, 1801 CK_K6_2, 1802 CK_K6_3, 1803 //@} 1804 1805 /// \name K7 1806 /// K7 architecture processors. 1807 //@{ 1808 CK_Athlon, 1809 CK_AthlonThunderbird, 1810 CK_Athlon4, 1811 CK_AthlonXP, 1812 CK_AthlonMP, 1813 //@} 1814 1815 /// \name K8 1816 /// K8 architecture processors. 1817 //@{ 1818 CK_Athlon64, 1819 CK_Athlon64SSE3, 1820 CK_AthlonFX, 1821 CK_K8, 1822 CK_K8SSE3, 1823 CK_Opteron, 1824 CK_OpteronSSE3, 1825 CK_AMDFAM10, 1826 //@} 1827 1828 /// \name Bobcat 1829 /// Bobcat architecture processors. 1830 //@{ 1831 CK_BTVER1, 1832 CK_BTVER2, 1833 //@} 1834 1835 /// \name Bulldozer 1836 /// Bulldozer architecture processors. 1837 //@{ 1838 CK_BDVER1, 1839 CK_BDVER2, 1840 CK_BDVER3, 1841 CK_BDVER4, 1842 //@} 1843 1844 /// This specification is deprecated and will be removed in the future. 1845 /// Users should prefer \see CK_K8. 1846 // FIXME: Warn on this when the CPU is set to it. 1847 CK_x86_64, 1848 //@} 1849 1850 /// \name Geode 1851 /// Geode processors. 1852 //@{ 1853 CK_Geode 1854 //@} 1855 } CPU; 1856 1857 enum FPMathKind { 1858 FP_Default, 1859 FP_SSE, 1860 FP_387 1861 } FPMath; 1862 1863 public: 1864 X86TargetInfo(const llvm::Triple &Triple) 1865 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1866 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 1867 HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false), 1868 HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasTBM(false), 1869 HasFMA(false), HasF16C(false), HasAVX512CD(false), HasAVX512ER(false), 1870 HasAVX512PF(false), HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false), 1871 HasSHA(false), HasCX16(false), CPU(CK_Generic), 1872 FPMath(FP_Default) { 1873 BigEndian = false; 1874 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1875 } 1876 unsigned getFloatEvalMethod() const override { 1877 // X87 evaluates with 80 bits "long double" precision. 1878 return SSELevel == NoSSE ? 2 : 0; 1879 } 1880 void getTargetBuiltins(const Builtin::Info *&Records, 1881 unsigned &NumRecords) const override { 1882 Records = BuiltinInfo; 1883 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1884 } 1885 void getGCCRegNames(const char * const *&Names, 1886 unsigned &NumNames) const override { 1887 Names = GCCRegNames; 1888 NumNames = llvm::array_lengthof(GCCRegNames); 1889 } 1890 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1891 unsigned &NumAliases) const override { 1892 Aliases = nullptr; 1893 NumAliases = 0; 1894 } 1895 void getGCCAddlRegNames(const AddlRegName *&Names, 1896 unsigned &NumNames) const override { 1897 Names = AddlRegNames; 1898 NumNames = llvm::array_lengthof(AddlRegNames); 1899 } 1900 bool validateAsmConstraint(const char *&Name, 1901 TargetInfo::ConstraintInfo &info) const override; 1902 std::string convertConstraint(const char *&Constraint) const override; 1903 const char *getClobbers() const override { 1904 return "~{dirflag},~{fpsr},~{flags}"; 1905 } 1906 void getTargetDefines(const LangOptions &Opts, 1907 MacroBuilder &Builder) const override; 1908 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 1909 bool Enabled); 1910 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 1911 bool Enabled); 1912 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 1913 bool Enabled); 1914 void setFeatureEnabled(llvm::StringMap<bool> &Features, 1915 StringRef Name, bool Enabled) const override { 1916 setFeatureEnabledImpl(Features, Name, Enabled); 1917 } 1918 // This exists purely to cut down on the number of virtual calls in 1919 // getDefaultFeatures which calls this repeatedly. 1920 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 1921 StringRef Name, bool Enabled); 1922 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 1923 bool hasFeature(StringRef Feature) const override; 1924 bool handleTargetFeatures(std::vector<std::string> &Features, 1925 DiagnosticsEngine &Diags) override; 1926 StringRef getABI() const override { 1927 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 1928 return "avx"; 1929 else if (getTriple().getArch() == llvm::Triple::x86 && 1930 MMX3DNowLevel == NoMMX3DNow) 1931 return "no-mmx"; 1932 return ""; 1933 } 1934 bool setCPU(const std::string &Name) override { 1935 CPU = llvm::StringSwitch<CPUKind>(Name) 1936 .Case("i386", CK_i386) 1937 .Case("i486", CK_i486) 1938 .Case("winchip-c6", CK_WinChipC6) 1939 .Case("winchip2", CK_WinChip2) 1940 .Case("c3", CK_C3) 1941 .Case("i586", CK_i586) 1942 .Case("pentium", CK_Pentium) 1943 .Case("pentium-mmx", CK_PentiumMMX) 1944 .Case("i686", CK_i686) 1945 .Case("pentiumpro", CK_PentiumPro) 1946 .Case("pentium2", CK_Pentium2) 1947 .Case("pentium3", CK_Pentium3) 1948 .Case("pentium3m", CK_Pentium3M) 1949 .Case("pentium-m", CK_PentiumM) 1950 .Case("c3-2", CK_C3_2) 1951 .Case("yonah", CK_Yonah) 1952 .Case("pentium4", CK_Pentium4) 1953 .Case("pentium4m", CK_Pentium4M) 1954 .Case("prescott", CK_Prescott) 1955 .Case("nocona", CK_Nocona) 1956 .Case("core2", CK_Core2) 1957 .Case("penryn", CK_Penryn) 1958 .Case("atom", CK_Atom) 1959 .Case("slm", CK_Silvermont) 1960 .Case("corei7", CK_Corei7) 1961 .Case("corei7-avx", CK_Corei7AVX) 1962 .Case("core-avx-i", CK_CoreAVXi) 1963 .Case("core-avx2", CK_CoreAVX2) 1964 .Case("knl", CK_KNL) 1965 .Case("skx", CK_SKX) 1966 .Case("k6", CK_K6) 1967 .Case("k6-2", CK_K6_2) 1968 .Case("k6-3", CK_K6_3) 1969 .Case("athlon", CK_Athlon) 1970 .Case("athlon-tbird", CK_AthlonThunderbird) 1971 .Case("athlon-4", CK_Athlon4) 1972 .Case("athlon-xp", CK_AthlonXP) 1973 .Case("athlon-mp", CK_AthlonMP) 1974 .Case("athlon64", CK_Athlon64) 1975 .Case("athlon64-sse3", CK_Athlon64SSE3) 1976 .Case("athlon-fx", CK_AthlonFX) 1977 .Case("k8", CK_K8) 1978 .Case("k8-sse3", CK_K8SSE3) 1979 .Case("opteron", CK_Opteron) 1980 .Case("opteron-sse3", CK_OpteronSSE3) 1981 .Case("amdfam10", CK_AMDFAM10) 1982 .Case("btver1", CK_BTVER1) 1983 .Case("btver2", CK_BTVER2) 1984 .Case("bdver1", CK_BDVER1) 1985 .Case("bdver2", CK_BDVER2) 1986 .Case("bdver3", CK_BDVER3) 1987 .Case("bdver4", CK_BDVER4) 1988 .Case("x86-64", CK_x86_64) 1989 .Case("geode", CK_Geode) 1990 .Default(CK_Generic); 1991 1992 // Perform any per-CPU checks necessary to determine if this CPU is 1993 // acceptable. 1994 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1995 // invalid without explaining *why*. 1996 switch (CPU) { 1997 case CK_Generic: 1998 // No processor selected! 1999 return false; 2000 2001 case CK_i386: 2002 case CK_i486: 2003 case CK_WinChipC6: 2004 case CK_WinChip2: 2005 case CK_C3: 2006 case CK_i586: 2007 case CK_Pentium: 2008 case CK_PentiumMMX: 2009 case CK_i686: 2010 case CK_PentiumPro: 2011 case CK_Pentium2: 2012 case CK_Pentium3: 2013 case CK_Pentium3M: 2014 case CK_PentiumM: 2015 case CK_Yonah: 2016 case CK_C3_2: 2017 case CK_Pentium4: 2018 case CK_Pentium4M: 2019 case CK_Prescott: 2020 case CK_K6: 2021 case CK_K6_2: 2022 case CK_K6_3: 2023 case CK_Athlon: 2024 case CK_AthlonThunderbird: 2025 case CK_Athlon4: 2026 case CK_AthlonXP: 2027 case CK_AthlonMP: 2028 case CK_Geode: 2029 // Only accept certain architectures when compiling in 32-bit mode. 2030 if (getTriple().getArch() != llvm::Triple::x86) 2031 return false; 2032 2033 // Fallthrough 2034 case CK_Nocona: 2035 case CK_Core2: 2036 case CK_Penryn: 2037 case CK_Atom: 2038 case CK_Silvermont: 2039 case CK_Corei7: 2040 case CK_Corei7AVX: 2041 case CK_CoreAVXi: 2042 case CK_CoreAVX2: 2043 case CK_KNL: 2044 case CK_SKX: 2045 case CK_Athlon64: 2046 case CK_Athlon64SSE3: 2047 case CK_AthlonFX: 2048 case CK_K8: 2049 case CK_K8SSE3: 2050 case CK_Opteron: 2051 case CK_OpteronSSE3: 2052 case CK_AMDFAM10: 2053 case CK_BTVER1: 2054 case CK_BTVER2: 2055 case CK_BDVER1: 2056 case CK_BDVER2: 2057 case CK_BDVER3: 2058 case CK_BDVER4: 2059 case CK_x86_64: 2060 return true; 2061 } 2062 llvm_unreachable("Unhandled CPU kind"); 2063 } 2064 2065 bool setFPMath(StringRef Name) override; 2066 2067 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2068 // We accept all non-ARM calling conventions 2069 return (CC == CC_X86ThisCall || 2070 CC == CC_X86FastCall || 2071 CC == CC_X86StdCall || 2072 CC == CC_C || 2073 CC == CC_X86Pascal || 2074 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2075 } 2076 2077 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2078 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2079 } 2080 }; 2081 2082 bool X86TargetInfo::setFPMath(StringRef Name) { 2083 if (Name == "387") { 2084 FPMath = FP_387; 2085 return true; 2086 } 2087 if (Name == "sse") { 2088 FPMath = FP_SSE; 2089 return true; 2090 } 2091 return false; 2092 } 2093 2094 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2095 // FIXME: This *really* should not be here. 2096 2097 // X86_64 always has SSE2. 2098 if (getTriple().getArch() == llvm::Triple::x86_64) 2099 setFeatureEnabledImpl(Features, "sse2", true); 2100 2101 switch (CPU) { 2102 case CK_Generic: 2103 case CK_i386: 2104 case CK_i486: 2105 case CK_i586: 2106 case CK_Pentium: 2107 case CK_i686: 2108 case CK_PentiumPro: 2109 break; 2110 case CK_PentiumMMX: 2111 case CK_Pentium2: 2112 setFeatureEnabledImpl(Features, "mmx", true); 2113 break; 2114 case CK_Pentium3: 2115 case CK_Pentium3M: 2116 setFeatureEnabledImpl(Features, "sse", true); 2117 break; 2118 case CK_PentiumM: 2119 case CK_Pentium4: 2120 case CK_Pentium4M: 2121 case CK_x86_64: 2122 setFeatureEnabledImpl(Features, "sse2", true); 2123 break; 2124 case CK_Yonah: 2125 case CK_Prescott: 2126 case CK_Nocona: 2127 setFeatureEnabledImpl(Features, "sse3", true); 2128 setFeatureEnabledImpl(Features, "cx16", true); 2129 break; 2130 case CK_Core2: 2131 setFeatureEnabledImpl(Features, "ssse3", true); 2132 setFeatureEnabledImpl(Features, "cx16", true); 2133 break; 2134 case CK_Penryn: 2135 setFeatureEnabledImpl(Features, "sse4.1", true); 2136 setFeatureEnabledImpl(Features, "cx16", true); 2137 break; 2138 case CK_Atom: 2139 setFeatureEnabledImpl(Features, "ssse3", true); 2140 setFeatureEnabledImpl(Features, "cx16", true); 2141 break; 2142 case CK_Silvermont: 2143 setFeatureEnabledImpl(Features, "sse4.2", true); 2144 setFeatureEnabledImpl(Features, "aes", true); 2145 setFeatureEnabledImpl(Features, "cx16", true); 2146 setFeatureEnabledImpl(Features, "pclmul", true); 2147 break; 2148 case CK_Corei7: 2149 setFeatureEnabledImpl(Features, "sse4.2", true); 2150 setFeatureEnabledImpl(Features, "cx16", true); 2151 break; 2152 case CK_Corei7AVX: 2153 setFeatureEnabledImpl(Features, "avx", true); 2154 setFeatureEnabledImpl(Features, "aes", true); 2155 setFeatureEnabledImpl(Features, "cx16", true); 2156 setFeatureEnabledImpl(Features, "pclmul", true); 2157 break; 2158 case CK_CoreAVXi: 2159 setFeatureEnabledImpl(Features, "avx", true); 2160 setFeatureEnabledImpl(Features, "aes", true); 2161 setFeatureEnabledImpl(Features, "pclmul", true); 2162 setFeatureEnabledImpl(Features, "rdrnd", true); 2163 setFeatureEnabledImpl(Features, "f16c", true); 2164 break; 2165 case CK_CoreAVX2: 2166 setFeatureEnabledImpl(Features, "avx2", true); 2167 setFeatureEnabledImpl(Features, "aes", true); 2168 setFeatureEnabledImpl(Features, "pclmul", true); 2169 setFeatureEnabledImpl(Features, "lzcnt", true); 2170 setFeatureEnabledImpl(Features, "rdrnd", true); 2171 setFeatureEnabledImpl(Features, "f16c", true); 2172 setFeatureEnabledImpl(Features, "bmi", true); 2173 setFeatureEnabledImpl(Features, "bmi2", true); 2174 setFeatureEnabledImpl(Features, "rtm", true); 2175 setFeatureEnabledImpl(Features, "fma", true); 2176 setFeatureEnabledImpl(Features, "cx16", true); 2177 break; 2178 case CK_KNL: 2179 setFeatureEnabledImpl(Features, "avx512f", true); 2180 setFeatureEnabledImpl(Features, "avx512cd", true); 2181 setFeatureEnabledImpl(Features, "avx512er", true); 2182 setFeatureEnabledImpl(Features, "avx512pf", true); 2183 setFeatureEnabledImpl(Features, "aes", true); 2184 setFeatureEnabledImpl(Features, "pclmul", true); 2185 setFeatureEnabledImpl(Features, "lzcnt", true); 2186 setFeatureEnabledImpl(Features, "rdrnd", true); 2187 setFeatureEnabledImpl(Features, "f16c", true); 2188 setFeatureEnabledImpl(Features, "bmi", true); 2189 setFeatureEnabledImpl(Features, "bmi2", true); 2190 setFeatureEnabledImpl(Features, "rtm", true); 2191 setFeatureEnabledImpl(Features, "fma", true); 2192 break; 2193 case CK_SKX: 2194 setFeatureEnabledImpl(Features, "avx512f", true); 2195 setFeatureEnabledImpl(Features, "avx512cd", true); 2196 setFeatureEnabledImpl(Features, "avx512dq", true); 2197 setFeatureEnabledImpl(Features, "avx512bw", true); 2198 setFeatureEnabledImpl(Features, "avx512vl", true); 2199 setFeatureEnabledImpl(Features, "aes", true); 2200 setFeatureEnabledImpl(Features, "pclmul", true); 2201 setFeatureEnabledImpl(Features, "lzcnt", true); 2202 setFeatureEnabledImpl(Features, "rdrnd", true); 2203 setFeatureEnabledImpl(Features, "f16c", true); 2204 setFeatureEnabledImpl(Features, "bmi", true); 2205 setFeatureEnabledImpl(Features, "bmi2", true); 2206 setFeatureEnabledImpl(Features, "rtm", true); 2207 setFeatureEnabledImpl(Features, "fma", true); 2208 break; 2209 case CK_K6: 2210 case CK_WinChipC6: 2211 setFeatureEnabledImpl(Features, "mmx", true); 2212 break; 2213 case CK_K6_2: 2214 case CK_K6_3: 2215 case CK_WinChip2: 2216 case CK_C3: 2217 setFeatureEnabledImpl(Features, "3dnow", true); 2218 break; 2219 case CK_Athlon: 2220 case CK_AthlonThunderbird: 2221 case CK_Geode: 2222 setFeatureEnabledImpl(Features, "3dnowa", true); 2223 break; 2224 case CK_Athlon4: 2225 case CK_AthlonXP: 2226 case CK_AthlonMP: 2227 setFeatureEnabledImpl(Features, "sse", true); 2228 setFeatureEnabledImpl(Features, "3dnowa", true); 2229 break; 2230 case CK_K8: 2231 case CK_Opteron: 2232 case CK_Athlon64: 2233 case CK_AthlonFX: 2234 setFeatureEnabledImpl(Features, "sse2", true); 2235 setFeatureEnabledImpl(Features, "3dnowa", true); 2236 break; 2237 case CK_K8SSE3: 2238 case CK_OpteronSSE3: 2239 case CK_Athlon64SSE3: 2240 setFeatureEnabledImpl(Features, "sse3", true); 2241 setFeatureEnabledImpl(Features, "3dnowa", true); 2242 break; 2243 case CK_AMDFAM10: 2244 setFeatureEnabledImpl(Features, "sse3", true); 2245 setFeatureEnabledImpl(Features, "sse4a", true); 2246 setFeatureEnabledImpl(Features, "3dnowa", true); 2247 setFeatureEnabledImpl(Features, "lzcnt", true); 2248 setFeatureEnabledImpl(Features, "popcnt", true); 2249 break; 2250 case CK_BTVER1: 2251 setFeatureEnabledImpl(Features, "ssse3", true); 2252 setFeatureEnabledImpl(Features, "sse4a", true); 2253 setFeatureEnabledImpl(Features, "cx16", true); 2254 setFeatureEnabledImpl(Features, "lzcnt", true); 2255 setFeatureEnabledImpl(Features, "popcnt", true); 2256 setFeatureEnabledImpl(Features, "prfchw", true); 2257 break; 2258 case CK_BTVER2: 2259 setFeatureEnabledImpl(Features, "avx", true); 2260 setFeatureEnabledImpl(Features, "sse4a", true); 2261 setFeatureEnabledImpl(Features, "lzcnt", true); 2262 setFeatureEnabledImpl(Features, "aes", true); 2263 setFeatureEnabledImpl(Features, "pclmul", true); 2264 setFeatureEnabledImpl(Features, "prfchw", true); 2265 setFeatureEnabledImpl(Features, "bmi", true); 2266 setFeatureEnabledImpl(Features, "f16c", true); 2267 setFeatureEnabledImpl(Features, "cx16", true); 2268 break; 2269 case CK_BDVER1: 2270 setFeatureEnabledImpl(Features, "xop", true); 2271 setFeatureEnabledImpl(Features, "lzcnt", true); 2272 setFeatureEnabledImpl(Features, "aes", true); 2273 setFeatureEnabledImpl(Features, "pclmul", true); 2274 setFeatureEnabledImpl(Features, "prfchw", true); 2275 setFeatureEnabledImpl(Features, "cx16", true); 2276 break; 2277 case CK_BDVER4: 2278 setFeatureEnabledImpl(Features, "avx2", true); 2279 setFeatureEnabledImpl(Features, "bmi2", true); 2280 // FALLTHROUGH 2281 case CK_BDVER2: 2282 case CK_BDVER3: 2283 setFeatureEnabledImpl(Features, "xop", true); 2284 setFeatureEnabledImpl(Features, "lzcnt", true); 2285 setFeatureEnabledImpl(Features, "aes", true); 2286 setFeatureEnabledImpl(Features, "pclmul", true); 2287 setFeatureEnabledImpl(Features, "prfchw", true); 2288 setFeatureEnabledImpl(Features, "bmi", true); 2289 setFeatureEnabledImpl(Features, "fma", true); 2290 setFeatureEnabledImpl(Features, "f16c", true); 2291 setFeatureEnabledImpl(Features, "tbm", true); 2292 setFeatureEnabledImpl(Features, "cx16", true); 2293 break; 2294 case CK_C3_2: 2295 setFeatureEnabledImpl(Features, "sse", true); 2296 break; 2297 } 2298 } 2299 2300 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2301 X86SSEEnum Level, bool Enabled) { 2302 if (Enabled) { 2303 switch (Level) { 2304 case AVX512F: 2305 Features["avx512f"] = true; 2306 case AVX2: 2307 Features["avx2"] = true; 2308 case AVX: 2309 Features["avx"] = true; 2310 case SSE42: 2311 Features["sse4.2"] = true; 2312 case SSE41: 2313 Features["sse4.1"] = true; 2314 case SSSE3: 2315 Features["ssse3"] = true; 2316 case SSE3: 2317 Features["sse3"] = true; 2318 case SSE2: 2319 Features["sse2"] = true; 2320 case SSE1: 2321 Features["sse"] = true; 2322 case NoSSE: 2323 break; 2324 } 2325 return; 2326 } 2327 2328 switch (Level) { 2329 case NoSSE: 2330 case SSE1: 2331 Features["sse"] = false; 2332 case SSE2: 2333 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2334 Features["sha"] = false; 2335 case SSE3: 2336 Features["sse3"] = false; 2337 setXOPLevel(Features, NoXOP, false); 2338 case SSSE3: 2339 Features["ssse3"] = false; 2340 case SSE41: 2341 Features["sse4.1"] = false; 2342 case SSE42: 2343 Features["sse4.2"] = false; 2344 case AVX: 2345 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2346 setXOPLevel(Features, FMA4, false); 2347 case AVX2: 2348 Features["avx2"] = false; 2349 case AVX512F: 2350 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = Features["avx512pf"] = 2351 Features["avx512dq"] = Features["avx512bw"] = Features["avx512vl"] = false; 2352 } 2353 } 2354 2355 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2356 MMX3DNowEnum Level, bool Enabled) { 2357 if (Enabled) { 2358 switch (Level) { 2359 case AMD3DNowAthlon: 2360 Features["3dnowa"] = true; 2361 case AMD3DNow: 2362 Features["3dnow"] = true; 2363 case MMX: 2364 Features["mmx"] = true; 2365 case NoMMX3DNow: 2366 break; 2367 } 2368 return; 2369 } 2370 2371 switch (Level) { 2372 case NoMMX3DNow: 2373 case MMX: 2374 Features["mmx"] = false; 2375 case AMD3DNow: 2376 Features["3dnow"] = false; 2377 case AMD3DNowAthlon: 2378 Features["3dnowa"] = false; 2379 } 2380 } 2381 2382 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2383 bool Enabled) { 2384 if (Enabled) { 2385 switch (Level) { 2386 case XOP: 2387 Features["xop"] = true; 2388 case FMA4: 2389 Features["fma4"] = true; 2390 setSSELevel(Features, AVX, true); 2391 case SSE4A: 2392 Features["sse4a"] = true; 2393 setSSELevel(Features, SSE3, true); 2394 case NoXOP: 2395 break; 2396 } 2397 return; 2398 } 2399 2400 switch (Level) { 2401 case NoXOP: 2402 case SSE4A: 2403 Features["sse4a"] = false; 2404 case FMA4: 2405 Features["fma4"] = false; 2406 case XOP: 2407 Features["xop"] = false; 2408 } 2409 } 2410 2411 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2412 StringRef Name, bool Enabled) { 2413 // FIXME: This *really* should not be here. We need some way of translating 2414 // options into llvm subtarget features. 2415 if (Name == "sse4") 2416 Name = "sse4.2"; 2417 2418 Features[Name] = Enabled; 2419 2420 if (Name == "mmx") { 2421 setMMXLevel(Features, MMX, Enabled); 2422 } else if (Name == "sse") { 2423 setSSELevel(Features, SSE1, Enabled); 2424 } else if (Name == "sse2") { 2425 setSSELevel(Features, SSE2, Enabled); 2426 } else if (Name == "sse3") { 2427 setSSELevel(Features, SSE3, Enabled); 2428 } else if (Name == "ssse3") { 2429 setSSELevel(Features, SSSE3, Enabled); 2430 } else if (Name == "sse4.2") { 2431 setSSELevel(Features, SSE42, Enabled); 2432 } else if (Name == "sse4.1") { 2433 setSSELevel(Features, SSE41, Enabled); 2434 } else if (Name == "3dnow") { 2435 setMMXLevel(Features, AMD3DNow, Enabled); 2436 } else if (Name == "3dnowa") { 2437 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2438 } else if (Name == "aes") { 2439 if (Enabled) 2440 setSSELevel(Features, SSE2, Enabled); 2441 } else if (Name == "pclmul") { 2442 if (Enabled) 2443 setSSELevel(Features, SSE2, Enabled); 2444 } else if (Name == "avx") { 2445 setSSELevel(Features, AVX, Enabled); 2446 } else if (Name == "avx2") { 2447 setSSELevel(Features, AVX2, Enabled); 2448 } else if (Name == "avx512f") { 2449 setSSELevel(Features, AVX512F, Enabled); 2450 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2451 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2452 if (Enabled) 2453 setSSELevel(Features, AVX512F, Enabled); 2454 } else if (Name == "fma") { 2455 if (Enabled) 2456 setSSELevel(Features, AVX, Enabled); 2457 } else if (Name == "fma4") { 2458 setXOPLevel(Features, FMA4, Enabled); 2459 } else if (Name == "xop") { 2460 setXOPLevel(Features, XOP, Enabled); 2461 } else if (Name == "sse4a") { 2462 setXOPLevel(Features, SSE4A, Enabled); 2463 } else if (Name == "f16c") { 2464 if (Enabled) 2465 setSSELevel(Features, AVX, Enabled); 2466 } else if (Name == "sha") { 2467 if (Enabled) 2468 setSSELevel(Features, SSE2, Enabled); 2469 } 2470 } 2471 2472 /// handleTargetFeatures - Perform initialization based on the user 2473 /// configured set of features. 2474 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2475 DiagnosticsEngine &Diags) { 2476 // Remember the maximum enabled sselevel. 2477 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2478 // Ignore disabled features. 2479 if (Features[i][0] == '-') 2480 continue; 2481 2482 StringRef Feature = StringRef(Features[i]).substr(1); 2483 2484 if (Feature == "aes") { 2485 HasAES = true; 2486 continue; 2487 } 2488 2489 if (Feature == "pclmul") { 2490 HasPCLMUL = true; 2491 continue; 2492 } 2493 2494 if (Feature == "lzcnt") { 2495 HasLZCNT = true; 2496 continue; 2497 } 2498 2499 if (Feature == "rdrnd") { 2500 HasRDRND = true; 2501 continue; 2502 } 2503 2504 if (Feature == "bmi") { 2505 HasBMI = true; 2506 continue; 2507 } 2508 2509 if (Feature == "bmi2") { 2510 HasBMI2 = true; 2511 continue; 2512 } 2513 2514 if (Feature == "popcnt") { 2515 HasPOPCNT = true; 2516 continue; 2517 } 2518 2519 if (Feature == "rtm") { 2520 HasRTM = true; 2521 continue; 2522 } 2523 2524 if (Feature == "prfchw") { 2525 HasPRFCHW = true; 2526 continue; 2527 } 2528 2529 if (Feature == "rdseed") { 2530 HasRDSEED = true; 2531 continue; 2532 } 2533 2534 if (Feature == "tbm") { 2535 HasTBM = true; 2536 continue; 2537 } 2538 2539 if (Feature == "fma") { 2540 HasFMA = true; 2541 continue; 2542 } 2543 2544 if (Feature == "f16c") { 2545 HasF16C = true; 2546 continue; 2547 } 2548 2549 if (Feature == "avx512cd") { 2550 HasAVX512CD = true; 2551 continue; 2552 } 2553 2554 if (Feature == "avx512er") { 2555 HasAVX512ER = true; 2556 continue; 2557 } 2558 2559 if (Feature == "avx512pf") { 2560 HasAVX512PF = true; 2561 continue; 2562 } 2563 2564 if (Feature == "avx512dq") { 2565 HasAVX512DQ = true; 2566 continue; 2567 } 2568 2569 if (Feature == "avx512bw") { 2570 HasAVX512BW = true; 2571 continue; 2572 } 2573 2574 if (Feature == "avx512vl") { 2575 HasAVX512VL = true; 2576 continue; 2577 } 2578 2579 if (Feature == "sha") { 2580 HasSHA = true; 2581 continue; 2582 } 2583 2584 if (Feature == "cx16") { 2585 HasCX16 = true; 2586 continue; 2587 } 2588 2589 assert(Features[i][0] == '+' && "Invalid target feature!"); 2590 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2591 .Case("avx512f", AVX512F) 2592 .Case("avx2", AVX2) 2593 .Case("avx", AVX) 2594 .Case("sse4.2", SSE42) 2595 .Case("sse4.1", SSE41) 2596 .Case("ssse3", SSSE3) 2597 .Case("sse3", SSE3) 2598 .Case("sse2", SSE2) 2599 .Case("sse", SSE1) 2600 .Default(NoSSE); 2601 SSELevel = std::max(SSELevel, Level); 2602 2603 MMX3DNowEnum ThreeDNowLevel = 2604 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2605 .Case("3dnowa", AMD3DNowAthlon) 2606 .Case("3dnow", AMD3DNow) 2607 .Case("mmx", MMX) 2608 .Default(NoMMX3DNow); 2609 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2610 2611 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2612 .Case("xop", XOP) 2613 .Case("fma4", FMA4) 2614 .Case("sse4a", SSE4A) 2615 .Default(NoXOP); 2616 XOPLevel = std::max(XOPLevel, XLevel); 2617 } 2618 2619 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2620 // Can't do this earlier because we need to be able to explicitly enable 2621 // popcnt and still disable sse4.2. 2622 if (!HasPOPCNT && SSELevel >= SSE42 && 2623 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2624 HasPOPCNT = true; 2625 Features.push_back("+popcnt"); 2626 } 2627 2628 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2629 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2630 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2631 HasPRFCHW = true; 2632 Features.push_back("+prfchw"); 2633 } 2634 2635 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2636 // matches the selected sse level. 2637 if (FPMath == FP_SSE && SSELevel < SSE1) { 2638 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2639 return false; 2640 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2641 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2642 return false; 2643 } 2644 2645 // Don't tell the backend if we're turning off mmx; it will end up disabling 2646 // SSE, which we don't want. 2647 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2648 // then enable MMX. 2649 std::vector<std::string>::iterator it; 2650 it = std::find(Features.begin(), Features.end(), "-mmx"); 2651 if (it != Features.end()) 2652 Features.erase(it); 2653 else if (SSELevel > NoSSE) 2654 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2655 return true; 2656 } 2657 2658 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2659 /// definitions for this particular subtarget. 2660 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2661 MacroBuilder &Builder) const { 2662 // Target identification. 2663 if (getTriple().getArch() == llvm::Triple::x86_64) { 2664 Builder.defineMacro("__amd64__"); 2665 Builder.defineMacro("__amd64"); 2666 Builder.defineMacro("__x86_64"); 2667 Builder.defineMacro("__x86_64__"); 2668 if (getTriple().getArchName() == "x86_64h") { 2669 Builder.defineMacro("__x86_64h"); 2670 Builder.defineMacro("__x86_64h__"); 2671 } 2672 } else { 2673 DefineStd(Builder, "i386", Opts); 2674 } 2675 2676 // Subtarget options. 2677 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2678 // truly should be based on -mtune options. 2679 switch (CPU) { 2680 case CK_Generic: 2681 break; 2682 case CK_i386: 2683 // The rest are coming from the i386 define above. 2684 Builder.defineMacro("__tune_i386__"); 2685 break; 2686 case CK_i486: 2687 case CK_WinChipC6: 2688 case CK_WinChip2: 2689 case CK_C3: 2690 defineCPUMacros(Builder, "i486"); 2691 break; 2692 case CK_PentiumMMX: 2693 Builder.defineMacro("__pentium_mmx__"); 2694 Builder.defineMacro("__tune_pentium_mmx__"); 2695 // Fallthrough 2696 case CK_i586: 2697 case CK_Pentium: 2698 defineCPUMacros(Builder, "i586"); 2699 defineCPUMacros(Builder, "pentium"); 2700 break; 2701 case CK_Pentium3: 2702 case CK_Pentium3M: 2703 case CK_PentiumM: 2704 Builder.defineMacro("__tune_pentium3__"); 2705 // Fallthrough 2706 case CK_Pentium2: 2707 case CK_C3_2: 2708 Builder.defineMacro("__tune_pentium2__"); 2709 // Fallthrough 2710 case CK_PentiumPro: 2711 Builder.defineMacro("__tune_i686__"); 2712 Builder.defineMacro("__tune_pentiumpro__"); 2713 // Fallthrough 2714 case CK_i686: 2715 Builder.defineMacro("__i686"); 2716 Builder.defineMacro("__i686__"); 2717 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2718 Builder.defineMacro("__pentiumpro"); 2719 Builder.defineMacro("__pentiumpro__"); 2720 break; 2721 case CK_Pentium4: 2722 case CK_Pentium4M: 2723 defineCPUMacros(Builder, "pentium4"); 2724 break; 2725 case CK_Yonah: 2726 case CK_Prescott: 2727 case CK_Nocona: 2728 defineCPUMacros(Builder, "nocona"); 2729 break; 2730 case CK_Core2: 2731 case CK_Penryn: 2732 defineCPUMacros(Builder, "core2"); 2733 break; 2734 case CK_Atom: 2735 defineCPUMacros(Builder, "atom"); 2736 break; 2737 case CK_Silvermont: 2738 defineCPUMacros(Builder, "slm"); 2739 break; 2740 case CK_Corei7: 2741 case CK_Corei7AVX: 2742 case CK_CoreAVXi: 2743 case CK_CoreAVX2: 2744 defineCPUMacros(Builder, "corei7"); 2745 break; 2746 case CK_KNL: 2747 defineCPUMacros(Builder, "knl"); 2748 break; 2749 case CK_SKX: 2750 defineCPUMacros(Builder, "skx"); 2751 break; 2752 case CK_K6_2: 2753 Builder.defineMacro("__k6_2__"); 2754 Builder.defineMacro("__tune_k6_2__"); 2755 // Fallthrough 2756 case CK_K6_3: 2757 if (CPU != CK_K6_2) { // In case of fallthrough 2758 // FIXME: GCC may be enabling these in cases where some other k6 2759 // architecture is specified but -m3dnow is explicitly provided. The 2760 // exact semantics need to be determined and emulated here. 2761 Builder.defineMacro("__k6_3__"); 2762 Builder.defineMacro("__tune_k6_3__"); 2763 } 2764 // Fallthrough 2765 case CK_K6: 2766 defineCPUMacros(Builder, "k6"); 2767 break; 2768 case CK_Athlon: 2769 case CK_AthlonThunderbird: 2770 case CK_Athlon4: 2771 case CK_AthlonXP: 2772 case CK_AthlonMP: 2773 defineCPUMacros(Builder, "athlon"); 2774 if (SSELevel != NoSSE) { 2775 Builder.defineMacro("__athlon_sse__"); 2776 Builder.defineMacro("__tune_athlon_sse__"); 2777 } 2778 break; 2779 case CK_K8: 2780 case CK_K8SSE3: 2781 case CK_x86_64: 2782 case CK_Opteron: 2783 case CK_OpteronSSE3: 2784 case CK_Athlon64: 2785 case CK_Athlon64SSE3: 2786 case CK_AthlonFX: 2787 defineCPUMacros(Builder, "k8"); 2788 break; 2789 case CK_AMDFAM10: 2790 defineCPUMacros(Builder, "amdfam10"); 2791 break; 2792 case CK_BTVER1: 2793 defineCPUMacros(Builder, "btver1"); 2794 break; 2795 case CK_BTVER2: 2796 defineCPUMacros(Builder, "btver2"); 2797 break; 2798 case CK_BDVER1: 2799 defineCPUMacros(Builder, "bdver1"); 2800 break; 2801 case CK_BDVER2: 2802 defineCPUMacros(Builder, "bdver2"); 2803 break; 2804 case CK_BDVER3: 2805 defineCPUMacros(Builder, "bdver3"); 2806 break; 2807 case CK_BDVER4: 2808 defineCPUMacros(Builder, "bdver4"); 2809 break; 2810 case CK_Geode: 2811 defineCPUMacros(Builder, "geode"); 2812 break; 2813 } 2814 2815 // Target properties. 2816 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2817 2818 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2819 // functions in glibc header files that use FP Stack inline asm which the 2820 // backend can't deal with (PR879). 2821 Builder.defineMacro("__NO_MATH_INLINES"); 2822 2823 if (HasAES) 2824 Builder.defineMacro("__AES__"); 2825 2826 if (HasPCLMUL) 2827 Builder.defineMacro("__PCLMUL__"); 2828 2829 if (HasLZCNT) 2830 Builder.defineMacro("__LZCNT__"); 2831 2832 if (HasRDRND) 2833 Builder.defineMacro("__RDRND__"); 2834 2835 if (HasBMI) 2836 Builder.defineMacro("__BMI__"); 2837 2838 if (HasBMI2) 2839 Builder.defineMacro("__BMI2__"); 2840 2841 if (HasPOPCNT) 2842 Builder.defineMacro("__POPCNT__"); 2843 2844 if (HasRTM) 2845 Builder.defineMacro("__RTM__"); 2846 2847 if (HasPRFCHW) 2848 Builder.defineMacro("__PRFCHW__"); 2849 2850 if (HasRDSEED) 2851 Builder.defineMacro("__RDSEED__"); 2852 2853 if (HasTBM) 2854 Builder.defineMacro("__TBM__"); 2855 2856 switch (XOPLevel) { 2857 case XOP: 2858 Builder.defineMacro("__XOP__"); 2859 case FMA4: 2860 Builder.defineMacro("__FMA4__"); 2861 case SSE4A: 2862 Builder.defineMacro("__SSE4A__"); 2863 case NoXOP: 2864 break; 2865 } 2866 2867 if (HasFMA) 2868 Builder.defineMacro("__FMA__"); 2869 2870 if (HasF16C) 2871 Builder.defineMacro("__F16C__"); 2872 2873 if (HasAVX512CD) 2874 Builder.defineMacro("__AVX512CD__"); 2875 if (HasAVX512ER) 2876 Builder.defineMacro("__AVX512ER__"); 2877 if (HasAVX512PF) 2878 Builder.defineMacro("__AVX512PF__"); 2879 if (HasAVX512DQ) 2880 Builder.defineMacro("__AVX512DQ__"); 2881 if (HasAVX512BW) 2882 Builder.defineMacro("__AVX512BW__"); 2883 if (HasAVX512VL) 2884 Builder.defineMacro("__AVX512VL__"); 2885 2886 if (HasSHA) 2887 Builder.defineMacro("__SHA__"); 2888 2889 if (HasCX16) 2890 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 2891 2892 // Each case falls through to the previous one here. 2893 switch (SSELevel) { 2894 case AVX512F: 2895 Builder.defineMacro("__AVX512F__"); 2896 case AVX2: 2897 Builder.defineMacro("__AVX2__"); 2898 case AVX: 2899 Builder.defineMacro("__AVX__"); 2900 case SSE42: 2901 Builder.defineMacro("__SSE4_2__"); 2902 case SSE41: 2903 Builder.defineMacro("__SSE4_1__"); 2904 case SSSE3: 2905 Builder.defineMacro("__SSSE3__"); 2906 case SSE3: 2907 Builder.defineMacro("__SSE3__"); 2908 case SSE2: 2909 Builder.defineMacro("__SSE2__"); 2910 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2911 case SSE1: 2912 Builder.defineMacro("__SSE__"); 2913 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2914 case NoSSE: 2915 break; 2916 } 2917 2918 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 2919 switch (SSELevel) { 2920 case AVX512F: 2921 case AVX2: 2922 case AVX: 2923 case SSE42: 2924 case SSE41: 2925 case SSSE3: 2926 case SSE3: 2927 case SSE2: 2928 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2929 break; 2930 case SSE1: 2931 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2932 break; 2933 default: 2934 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2935 } 2936 } 2937 2938 // Each case falls through to the previous one here. 2939 switch (MMX3DNowLevel) { 2940 case AMD3DNowAthlon: 2941 Builder.defineMacro("__3dNOW_A__"); 2942 case AMD3DNow: 2943 Builder.defineMacro("__3dNOW__"); 2944 case MMX: 2945 Builder.defineMacro("__MMX__"); 2946 case NoMMX3DNow: 2947 break; 2948 } 2949 2950 if (CPU >= CK_i486) { 2951 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 2952 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 2953 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 2954 } 2955 if (CPU >= CK_i586) 2956 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 2957 } 2958 2959 bool X86TargetInfo::hasFeature(StringRef Feature) const { 2960 return llvm::StringSwitch<bool>(Feature) 2961 .Case("aes", HasAES) 2962 .Case("avx", SSELevel >= AVX) 2963 .Case("avx2", SSELevel >= AVX2) 2964 .Case("avx512f", SSELevel >= AVX512F) 2965 .Case("avx512cd", HasAVX512CD) 2966 .Case("avx512er", HasAVX512ER) 2967 .Case("avx512pf", HasAVX512PF) 2968 .Case("avx512dq", HasAVX512DQ) 2969 .Case("avx512bw", HasAVX512BW) 2970 .Case("avx512vl", HasAVX512VL) 2971 .Case("bmi", HasBMI) 2972 .Case("bmi2", HasBMI2) 2973 .Case("cx16", HasCX16) 2974 .Case("f16c", HasF16C) 2975 .Case("fma", HasFMA) 2976 .Case("fma4", XOPLevel >= FMA4) 2977 .Case("tbm", HasTBM) 2978 .Case("lzcnt", HasLZCNT) 2979 .Case("rdrnd", HasRDRND) 2980 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 2981 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 2982 .Case("mmx", MMX3DNowLevel >= MMX) 2983 .Case("pclmul", HasPCLMUL) 2984 .Case("popcnt", HasPOPCNT) 2985 .Case("rtm", HasRTM) 2986 .Case("prfchw", HasPRFCHW) 2987 .Case("rdseed", HasRDSEED) 2988 .Case("sha", HasSHA) 2989 .Case("sse", SSELevel >= SSE1) 2990 .Case("sse2", SSELevel >= SSE2) 2991 .Case("sse3", SSELevel >= SSE3) 2992 .Case("ssse3", SSELevel >= SSSE3) 2993 .Case("sse4.1", SSELevel >= SSE41) 2994 .Case("sse4.2", SSELevel >= SSE42) 2995 .Case("sse4a", XOPLevel >= SSE4A) 2996 .Case("x86", true) 2997 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 2998 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 2999 .Case("xop", XOPLevel >= XOP) 3000 .Default(false); 3001 } 3002 3003 bool 3004 X86TargetInfo::validateAsmConstraint(const char *&Name, 3005 TargetInfo::ConstraintInfo &Info) const { 3006 switch (*Name) { 3007 default: return false; 3008 case 'Y': // first letter of a pair: 3009 switch (*(Name+1)) { 3010 default: return false; 3011 case '0': // First SSE register. 3012 case 't': // Any SSE register, when SSE2 is enabled. 3013 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3014 case 'm': // any MMX register, when inter-unit moves enabled. 3015 break; // falls through to setAllowsRegister. 3016 } 3017 case 'f': // any x87 floating point stack register. 3018 // Constraint 'f' cannot be used for output operands. 3019 if (Info.ConstraintStr[0] == '=') 3020 return false; 3021 3022 Info.setAllowsRegister(); 3023 return true; 3024 case 'a': // eax. 3025 case 'b': // ebx. 3026 case 'c': // ecx. 3027 case 'd': // edx. 3028 case 'S': // esi. 3029 case 'D': // edi. 3030 case 'A': // edx:eax. 3031 case 't': // top of floating point stack. 3032 case 'u': // second from top of floating point stack. 3033 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3034 case 'y': // Any MMX register. 3035 case 'x': // Any SSE register. 3036 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3037 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3038 case 'l': // "Index" registers: any general register that can be used as an 3039 // index in a base+index memory access. 3040 Info.setAllowsRegister(); 3041 return true; 3042 case 'C': // SSE floating point constant. 3043 case 'G': // x87 floating point constant. 3044 case 'e': // 32-bit signed integer constant for use with zero-extending 3045 // x86_64 instructions. 3046 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3047 // x86_64 instructions. 3048 return true; 3049 } 3050 } 3051 3052 3053 std::string 3054 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3055 switch (*Constraint) { 3056 case 'a': return std::string("{ax}"); 3057 case 'b': return std::string("{bx}"); 3058 case 'c': return std::string("{cx}"); 3059 case 'd': return std::string("{dx}"); 3060 case 'S': return std::string("{si}"); 3061 case 'D': return std::string("{di}"); 3062 case 'p': // address 3063 return std::string("im"); 3064 case 't': // top of floating point stack. 3065 return std::string("{st}"); 3066 case 'u': // second from top of floating point stack. 3067 return std::string("{st(1)}"); // second from top of floating point stack. 3068 default: 3069 return std::string(1, *Constraint); 3070 } 3071 } 3072 } // end anonymous namespace 3073 3074 namespace { 3075 // X86-32 generic target 3076 class X86_32TargetInfo : public X86TargetInfo { 3077 public: 3078 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3079 DoubleAlign = LongLongAlign = 32; 3080 LongDoubleWidth = 96; 3081 LongDoubleAlign = 32; 3082 SuitableAlign = 128; 3083 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3084 SizeType = UnsignedInt; 3085 PtrDiffType = SignedInt; 3086 IntPtrType = SignedInt; 3087 RegParmMax = 3; 3088 3089 // Use fpret for all types. 3090 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3091 (1 << TargetInfo::Double) | 3092 (1 << TargetInfo::LongDouble)); 3093 3094 // x86-32 has atomics up to 8 bytes 3095 // FIXME: Check that we actually have cmpxchg8b before setting 3096 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3097 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3098 } 3099 BuiltinVaListKind getBuiltinVaListKind() const override { 3100 return TargetInfo::CharPtrBuiltinVaList; 3101 } 3102 3103 int getEHDataRegisterNumber(unsigned RegNo) const override { 3104 if (RegNo == 0) return 0; 3105 if (RegNo == 1) return 2; 3106 return -1; 3107 } 3108 bool validateInputSize(StringRef Constraint, 3109 unsigned Size) const override { 3110 switch (Constraint[0]) { 3111 default: break; 3112 case 'a': 3113 case 'b': 3114 case 'c': 3115 case 'd': 3116 return Size <= 32; 3117 } 3118 3119 return true; 3120 } 3121 }; 3122 } // end anonymous namespace 3123 3124 namespace { 3125 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3126 public: 3127 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3128 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3129 3130 unsigned getFloatEvalMethod() const override { 3131 unsigned Major, Minor, Micro; 3132 getTriple().getOSVersion(Major, Minor, Micro); 3133 // New NetBSD uses the default rounding mode. 3134 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3135 return X86_32TargetInfo::getFloatEvalMethod(); 3136 // NetBSD before 6.99.26 defaults to "double" rounding. 3137 return 1; 3138 } 3139 }; 3140 } // end anonymous namespace 3141 3142 namespace { 3143 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3144 public: 3145 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3146 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3147 SizeType = UnsignedLong; 3148 IntPtrType = SignedLong; 3149 PtrDiffType = SignedLong; 3150 } 3151 }; 3152 } // end anonymous namespace 3153 3154 namespace { 3155 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3156 public: 3157 BitrigI386TargetInfo(const llvm::Triple &Triple) 3158 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3159 SizeType = UnsignedLong; 3160 IntPtrType = SignedLong; 3161 PtrDiffType = SignedLong; 3162 } 3163 }; 3164 } // end anonymous namespace 3165 3166 namespace { 3167 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3168 public: 3169 DarwinI386TargetInfo(const llvm::Triple &Triple) 3170 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3171 LongDoubleWidth = 128; 3172 LongDoubleAlign = 128; 3173 SuitableAlign = 128; 3174 MaxVectorAlign = 256; 3175 SizeType = UnsignedLong; 3176 IntPtrType = SignedLong; 3177 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3178 HasAlignMac68kSupport = true; 3179 } 3180 3181 }; 3182 } // end anonymous namespace 3183 3184 namespace { 3185 // x86-32 Windows target 3186 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3187 public: 3188 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3189 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3190 WCharType = UnsignedShort; 3191 DoubleAlign = LongLongAlign = 64; 3192 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3193 } 3194 void getTargetDefines(const LangOptions &Opts, 3195 MacroBuilder &Builder) const override { 3196 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3197 } 3198 }; 3199 3200 // x86-32 Windows Visual Studio target 3201 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3202 public: 3203 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3204 : WindowsX86_32TargetInfo(Triple) { 3205 LongDoubleWidth = LongDoubleAlign = 64; 3206 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3207 } 3208 void getTargetDefines(const LangOptions &Opts, 3209 MacroBuilder &Builder) const override { 3210 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3211 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3212 // The value of the following reflects processor type. 3213 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3214 // We lost the original triple, so we use the default. 3215 Builder.defineMacro("_M_IX86", "600"); 3216 } 3217 }; 3218 } // end anonymous namespace 3219 3220 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3221 Builder.defineMacro("__MSVCRT__"); 3222 Builder.defineMacro("__MINGW32__"); 3223 3224 // Mingw defines __declspec(a) to __attribute__((a)). Clang supports 3225 // __declspec natively under -fms-extensions, but we define a no-op __declspec 3226 // macro anyway for pre-processor compatibility. 3227 if (Opts.MicrosoftExt) 3228 Builder.defineMacro("__declspec", "__declspec"); 3229 else 3230 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3231 3232 if (!Opts.MicrosoftExt) { 3233 // Provide macros for all the calling convention keywords. Provide both 3234 // single and double underscore prefixed variants. These are available on 3235 // x64 as well as x86, even though they have no effect. 3236 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3237 for (const char *CC : CCs) { 3238 std::string GCCSpelling = "__attribute__((__"; 3239 GCCSpelling += CC; 3240 GCCSpelling += "__))"; 3241 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3242 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3243 } 3244 } 3245 } 3246 3247 namespace { 3248 // x86-32 MinGW target 3249 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3250 public: 3251 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3252 : WindowsX86_32TargetInfo(Triple) {} 3253 void getTargetDefines(const LangOptions &Opts, 3254 MacroBuilder &Builder) const override { 3255 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3256 DefineStd(Builder, "WIN32", Opts); 3257 DefineStd(Builder, "WINNT", Opts); 3258 Builder.defineMacro("_X86_"); 3259 addMinGWDefines(Opts, Builder); 3260 } 3261 }; 3262 } // end anonymous namespace 3263 3264 namespace { 3265 // x86-32 Cygwin target 3266 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3267 public: 3268 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3269 : X86_32TargetInfo(Triple) { 3270 TLSSupported = false; 3271 WCharType = UnsignedShort; 3272 DoubleAlign = LongLongAlign = 64; 3273 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3274 } 3275 void getTargetDefines(const LangOptions &Opts, 3276 MacroBuilder &Builder) const override { 3277 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3278 Builder.defineMacro("_X86_"); 3279 Builder.defineMacro("__CYGWIN__"); 3280 Builder.defineMacro("__CYGWIN32__"); 3281 DefineStd(Builder, "unix", Opts); 3282 if (Opts.CPlusPlus) 3283 Builder.defineMacro("_GNU_SOURCE"); 3284 } 3285 }; 3286 } // end anonymous namespace 3287 3288 namespace { 3289 // x86-32 Haiku target 3290 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3291 public: 3292 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3293 SizeType = UnsignedLong; 3294 IntPtrType = SignedLong; 3295 PtrDiffType = SignedLong; 3296 ProcessIDType = SignedLong; 3297 this->UserLabelPrefix = ""; 3298 this->TLSSupported = false; 3299 } 3300 void getTargetDefines(const LangOptions &Opts, 3301 MacroBuilder &Builder) const override { 3302 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3303 Builder.defineMacro("__INTEL__"); 3304 Builder.defineMacro("__HAIKU__"); 3305 } 3306 }; 3307 } // end anonymous namespace 3308 3309 // RTEMS Target 3310 template<typename Target> 3311 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3312 protected: 3313 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3314 MacroBuilder &Builder) const override { 3315 // RTEMS defines; list based off of gcc output 3316 3317 Builder.defineMacro("__rtems__"); 3318 Builder.defineMacro("__ELF__"); 3319 } 3320 3321 public: 3322 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3323 this->UserLabelPrefix = ""; 3324 3325 switch (Triple.getArch()) { 3326 default: 3327 case llvm::Triple::x86: 3328 // this->MCountName = ".mcount"; 3329 break; 3330 case llvm::Triple::mips: 3331 case llvm::Triple::mipsel: 3332 case llvm::Triple::ppc: 3333 case llvm::Triple::ppc64: 3334 case llvm::Triple::ppc64le: 3335 // this->MCountName = "_mcount"; 3336 break; 3337 case llvm::Triple::arm: 3338 // this->MCountName = "__mcount"; 3339 break; 3340 } 3341 } 3342 }; 3343 3344 namespace { 3345 // x86-32 RTEMS target 3346 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3347 public: 3348 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3349 SizeType = UnsignedLong; 3350 IntPtrType = SignedLong; 3351 PtrDiffType = SignedLong; 3352 this->UserLabelPrefix = ""; 3353 } 3354 void getTargetDefines(const LangOptions &Opts, 3355 MacroBuilder &Builder) const override { 3356 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3357 Builder.defineMacro("__INTEL__"); 3358 Builder.defineMacro("__rtems__"); 3359 } 3360 }; 3361 } // end anonymous namespace 3362 3363 namespace { 3364 // x86-64 generic target 3365 class X86_64TargetInfo : public X86TargetInfo { 3366 public: 3367 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3368 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3369 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3370 LongDoubleWidth = 128; 3371 LongDoubleAlign = 128; 3372 LargeArrayMinWidth = 128; 3373 LargeArrayAlign = 128; 3374 SuitableAlign = 128; 3375 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3376 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3377 IntPtrType = IsX32 ? SignedInt : SignedLong; 3378 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3379 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3380 RegParmMax = 6; 3381 3382 DescriptionString = (IsX32) 3383 ? "e-m:e-" "p:32:32-" "i64:64-f80:128-n8:16:32:64-S128" 3384 : "e-m:e-" "i64:64-f80:128-n8:16:32:64-S128"; 3385 3386 // Use fpret only for long double. 3387 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3388 3389 // Use fp2ret for _Complex long double. 3390 ComplexLongDoubleUsesFP2Ret = true; 3391 3392 // x86-64 has atomics up to 16 bytes. 3393 MaxAtomicPromoteWidth = 128; 3394 MaxAtomicInlineWidth = 128; 3395 } 3396 BuiltinVaListKind getBuiltinVaListKind() const override { 3397 return TargetInfo::X86_64ABIBuiltinVaList; 3398 } 3399 3400 int getEHDataRegisterNumber(unsigned RegNo) const override { 3401 if (RegNo == 0) return 0; 3402 if (RegNo == 1) return 1; 3403 return -1; 3404 } 3405 3406 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3407 return (CC == CC_C || 3408 CC == CC_IntelOclBicc || 3409 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3410 } 3411 3412 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3413 return CC_C; 3414 } 3415 3416 // for x32 we need it here explicitly 3417 bool hasInt128Type() const override { return true; } 3418 }; 3419 } // end anonymous namespace 3420 3421 namespace { 3422 // x86-64 Windows target 3423 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3424 public: 3425 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3426 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3427 WCharType = UnsignedShort; 3428 LongWidth = LongAlign = 32; 3429 DoubleAlign = LongLongAlign = 64; 3430 IntMaxType = SignedLongLong; 3431 Int64Type = SignedLongLong; 3432 SizeType = UnsignedLongLong; 3433 PtrDiffType = SignedLongLong; 3434 IntPtrType = SignedLongLong; 3435 this->UserLabelPrefix = ""; 3436 } 3437 void getTargetDefines(const LangOptions &Opts, 3438 MacroBuilder &Builder) const override { 3439 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3440 Builder.defineMacro("_WIN64"); 3441 } 3442 BuiltinVaListKind getBuiltinVaListKind() const override { 3443 return TargetInfo::CharPtrBuiltinVaList; 3444 } 3445 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3446 return (CC == CC_C || 3447 CC == CC_IntelOclBicc || 3448 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning; 3449 } 3450 }; 3451 } // end anonymous namespace 3452 3453 namespace { 3454 // x86-64 Windows Visual Studio target 3455 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 3456 public: 3457 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 3458 : WindowsX86_64TargetInfo(Triple) { 3459 LongDoubleWidth = LongDoubleAlign = 64; 3460 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3461 } 3462 void getTargetDefines(const LangOptions &Opts, 3463 MacroBuilder &Builder) const override { 3464 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3465 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3466 Builder.defineMacro("_M_X64"); 3467 Builder.defineMacro("_M_AMD64"); 3468 } 3469 }; 3470 } // end anonymous namespace 3471 3472 namespace { 3473 // x86-64 MinGW target 3474 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3475 public: 3476 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3477 : WindowsX86_64TargetInfo(Triple) {} 3478 void getTargetDefines(const LangOptions &Opts, 3479 MacroBuilder &Builder) const override { 3480 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3481 DefineStd(Builder, "WIN64", Opts); 3482 Builder.defineMacro("__MINGW64__"); 3483 addMinGWDefines(Opts, Builder); 3484 } 3485 }; 3486 } // end anonymous namespace 3487 3488 namespace { 3489 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3490 public: 3491 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3492 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3493 Int64Type = SignedLongLong; 3494 MaxVectorAlign = 256; 3495 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 3496 llvm::Triple T = llvm::Triple(Triple); 3497 if (T.getOS() == llvm::Triple::IOS) 3498 UseSignedCharForObjCBool = false; 3499 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 3500 } 3501 }; 3502 } // end anonymous namespace 3503 3504 namespace { 3505 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3506 public: 3507 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3508 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3509 IntMaxType = SignedLongLong; 3510 Int64Type = SignedLongLong; 3511 } 3512 }; 3513 } // end anonymous namespace 3514 3515 namespace { 3516 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3517 public: 3518 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3519 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3520 IntMaxType = SignedLongLong; 3521 Int64Type = SignedLongLong; 3522 } 3523 }; 3524 } 3525 3526 3527 namespace { 3528 class ARMTargetInfo : public TargetInfo { 3529 // Possible FPU choices. 3530 enum FPUMode { 3531 VFP2FPU = (1 << 0), 3532 VFP3FPU = (1 << 1), 3533 VFP4FPU = (1 << 2), 3534 NeonFPU = (1 << 3), 3535 FPARMV8 = (1 << 4) 3536 }; 3537 3538 // Possible HWDiv features. 3539 enum HWDivMode { 3540 HWDivThumb = (1 << 0), 3541 HWDivARM = (1 << 1) 3542 }; 3543 3544 static bool FPUModeIsVFP(FPUMode Mode) { 3545 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 3546 } 3547 3548 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3549 static const char * const GCCRegNames[]; 3550 3551 std::string ABI, CPU; 3552 3553 enum { 3554 FP_Default, 3555 FP_VFP, 3556 FP_Neon 3557 } FPMath; 3558 3559 unsigned FPU : 5; 3560 3561 unsigned IsAAPCS : 1; 3562 unsigned IsThumb : 1; 3563 unsigned HWDiv : 2; 3564 3565 // Initialized via features. 3566 unsigned SoftFloat : 1; 3567 unsigned SoftFloatABI : 1; 3568 3569 unsigned CRC : 1; 3570 unsigned Crypto : 1; 3571 3572 static const Builtin::Info BuiltinInfo[]; 3573 3574 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3575 StringRef ArchName = T.getArchName(); 3576 if (T.getArch() == llvm::Triple::arm || 3577 T.getArch() == llvm::Triple::armeb) { 3578 StringRef VersionStr; 3579 if (ArchName.startswith("armv")) 3580 VersionStr = ArchName.substr(4, 1); 3581 else if (ArchName.startswith("armebv")) 3582 VersionStr = ArchName.substr(6, 1); 3583 else 3584 return false; 3585 unsigned Version; 3586 if (VersionStr.getAsInteger(10, Version)) 3587 return false; 3588 return Version >= 6; 3589 } 3590 assert(T.getArch() == llvm::Triple::thumb || 3591 T.getArch() == llvm::Triple::thumbeb); 3592 StringRef VersionStr; 3593 if (ArchName.startswith("thumbv")) 3594 VersionStr = ArchName.substr(6, 1); 3595 else if (ArchName.startswith("thumbebv")) 3596 VersionStr = ArchName.substr(8, 1); 3597 else 3598 return false; 3599 unsigned Version; 3600 if (VersionStr.getAsInteger(10, Version)) 3601 return false; 3602 return Version >= 7; 3603 } 3604 3605 void setABIAAPCS() { 3606 IsAAPCS = true; 3607 3608 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 3609 const llvm::Triple &T = getTriple(); 3610 3611 // size_t is unsigned long on MachO-derived environments and NetBSD. 3612 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD) 3613 SizeType = UnsignedLong; 3614 else 3615 SizeType = UnsignedInt; 3616 3617 switch (T.getOS()) { 3618 case llvm::Triple::NetBSD: 3619 WCharType = SignedInt; 3620 break; 3621 case llvm::Triple::Win32: 3622 WCharType = UnsignedShort; 3623 break; 3624 case llvm::Triple::Linux: 3625 default: 3626 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3627 WCharType = UnsignedInt; 3628 break; 3629 } 3630 3631 UseBitFieldTypeAlignment = true; 3632 3633 ZeroLengthBitfieldBoundary = 0; 3634 3635 if (IsThumb) { 3636 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3637 // so set preferred for small types to 32. 3638 if (T.isOSBinFormatMachO()) { 3639 DescriptionString = BigEndian ? 3640 "E-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3641 "v128:64:128-a:0:32-n32-S64" : 3642 "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3643 "v128:64:128-a:0:32-n32-S64"; 3644 } else if (T.isOSWindows()) { 3645 // FIXME: this is invalid for WindowsCE 3646 assert(!BigEndian && "Windows on ARM does not support big endian"); 3647 DescriptionString = "e" 3648 "-m:e" 3649 "-p:32:32" 3650 "-i1:8:32-i8:8:32-i16:16:32-i64:64" 3651 "-v128:64:128" 3652 "-a:0:32" 3653 "-n32" 3654 "-S64"; 3655 } else { 3656 DescriptionString = BigEndian ? 3657 "E-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3658 "v128:64:128-a:0:32-n32-S64" : 3659 "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3660 "v128:64:128-a:0:32-n32-S64"; 3661 } 3662 } else { 3663 if (T.isOSBinFormatMachO()) 3664 DescriptionString = BigEndian ? 3665 "E-m:o-p:32:32-i64:64-v128:64:128-n32-S64" : 3666 "e-m:o-p:32:32-i64:64-v128:64:128-n32-S64"; 3667 else 3668 DescriptionString = BigEndian ? 3669 "E-m:e-p:32:32-i64:64-v128:64:128-n32-S64" : 3670 "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64"; 3671 } 3672 3673 // FIXME: Enumerated types are variable width in straight AAPCS. 3674 } 3675 3676 void setABIAPCS() { 3677 const llvm::Triple &T = getTriple(); 3678 3679 IsAAPCS = false; 3680 3681 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 3682 3683 // size_t is unsigned int on FreeBSD. 3684 if (T.getOS() == llvm::Triple::FreeBSD) 3685 SizeType = UnsignedInt; 3686 else 3687 SizeType = UnsignedLong; 3688 3689 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 3690 WCharType = SignedInt; 3691 3692 // Do not respect the alignment of bit-field types when laying out 3693 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 3694 UseBitFieldTypeAlignment = false; 3695 3696 /// gcc forces the alignment to 4 bytes, regardless of the type of the 3697 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 3698 /// gcc. 3699 ZeroLengthBitfieldBoundary = 32; 3700 3701 if (IsThumb) { 3702 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3703 // so set preferred for small types to 32. 3704 if (T.isOSBinFormatMachO()) 3705 DescriptionString = BigEndian ? 3706 "E-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3707 "-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3708 "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3709 "-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3710 else 3711 DescriptionString = BigEndian ? 3712 "E-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3713 "-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3714 "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3715 "-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3716 } else { 3717 if (T.isOSBinFormatMachO()) 3718 DescriptionString = BigEndian ? 3719 "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3720 "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3721 else 3722 DescriptionString = BigEndian ? 3723 "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3724 "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3725 } 3726 3727 // FIXME: Override "preferred align" for double and long long. 3728 } 3729 3730 public: 3731 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 3732 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 3733 IsAAPCS(true) { 3734 BigEndian = IsBigEndian; 3735 3736 switch (getTriple().getOS()) { 3737 case llvm::Triple::NetBSD: 3738 PtrDiffType = SignedLong; 3739 break; 3740 default: 3741 PtrDiffType = SignedInt; 3742 break; 3743 } 3744 3745 // {} in inline assembly are neon specifiers, not assembly variant 3746 // specifiers. 3747 NoAsmVariants = true; 3748 3749 // FIXME: Should we just treat this as a feature? 3750 IsThumb = getTriple().getArchName().startswith("thumb"); 3751 3752 setABI("aapcs-linux"); 3753 3754 // ARM targets default to using the ARM C++ ABI. 3755 TheCXXABI.set(TargetCXXABI::GenericARM); 3756 3757 // ARM has atomics up to 8 bytes 3758 MaxAtomicPromoteWidth = 64; 3759 if (shouldUseInlineAtomic(getTriple())) 3760 MaxAtomicInlineWidth = 64; 3761 3762 // Do force alignment of members that follow zero length bitfields. If 3763 // the alignment of the zero-length bitfield is greater than the member 3764 // that follows it, `bar', `bar' will be aligned as the type of the 3765 // zero length bitfield. 3766 UseZeroLengthBitfieldAlignment = true; 3767 } 3768 StringRef getABI() const override { return ABI; } 3769 bool setABI(const std::string &Name) override { 3770 ABI = Name; 3771 3772 // The defaults (above) are for AAPCS, check if we need to change them. 3773 // 3774 // FIXME: We need support for -meabi... we could just mangle it into the 3775 // name. 3776 if (Name == "apcs-gnu") { 3777 setABIAPCS(); 3778 return true; 3779 } 3780 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 3781 setABIAAPCS(); 3782 return true; 3783 } 3784 return false; 3785 } 3786 3787 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 3788 if (IsAAPCS) 3789 Features["aapcs"] = true; 3790 else 3791 Features["apcs"] = true; 3792 3793 StringRef ArchName = getTriple().getArchName(); 3794 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 3795 Features["vfp2"] = true; 3796 else if (CPU == "cortex-a8" || CPU == "cortex-a9" || 3797 CPU == "cortex-a9-mp") { 3798 Features["vfp3"] = true; 3799 Features["neon"] = true; 3800 } 3801 else if (CPU == "cortex-a5") { 3802 Features["vfp4"] = true; 3803 Features["neon"] = true; 3804 } else if (CPU == "swift" || CPU == "cortex-a7" || 3805 CPU == "cortex-a12" || CPU == "cortex-a15" || 3806 CPU == "krait") { 3807 Features["vfp4"] = true; 3808 Features["neon"] = true; 3809 Features["hwdiv"] = true; 3810 Features["hwdiv-arm"] = true; 3811 } else if (CPU == "cyclone") { 3812 Features["v8fp"] = true; 3813 Features["neon"] = true; 3814 Features["hwdiv"] = true; 3815 Features["hwdiv-arm"] = true; 3816 } else if (CPU == "cortex-a53" || CPU == "cortex-a57") { 3817 Features["fp-armv8"] = true; 3818 Features["neon"] = true; 3819 Features["hwdiv"] = true; 3820 Features["hwdiv-arm"] = true; 3821 Features["crc"] = true; 3822 Features["crypto"] = true; 3823 } else if (CPU == "cortex-r5" || 3824 // Enable the hwdiv extension for all v8a AArch32 cores by 3825 // default. 3826 ArchName == "armv8a" || ArchName == "armv8" || 3827 ArchName == "armebv8a" || ArchName == "armebv8" || 3828 ArchName == "thumbv8a" || ArchName == "thumbv8" || 3829 ArchName == "thumbebv8a" || ArchName == "thumbebv8") { 3830 Features["hwdiv"] = true; 3831 Features["hwdiv-arm"] = true; 3832 } else if (CPU == "cortex-m3" || CPU == "cortex-m4") { 3833 Features["hwdiv"] = true; 3834 } 3835 } 3836 3837 bool handleTargetFeatures(std::vector<std::string> &Features, 3838 DiagnosticsEngine &Diags) override { 3839 FPU = 0; 3840 CRC = 0; 3841 Crypto = 0; 3842 SoftFloat = SoftFloatABI = false; 3843 HWDiv = 0; 3844 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3845 if (Features[i] == "+soft-float") 3846 SoftFloat = true; 3847 else if (Features[i] == "+soft-float-abi") 3848 SoftFloatABI = true; 3849 else if (Features[i] == "+vfp2") 3850 FPU |= VFP2FPU; 3851 else if (Features[i] == "+vfp3") 3852 FPU |= VFP3FPU; 3853 else if (Features[i] == "+vfp4") 3854 FPU |= VFP4FPU; 3855 else if (Features[i] == "+fp-armv8") 3856 FPU |= FPARMV8; 3857 else if (Features[i] == "+neon") 3858 FPU |= NeonFPU; 3859 else if (Features[i] == "+hwdiv") 3860 HWDiv |= HWDivThumb; 3861 else if (Features[i] == "+hwdiv-arm") 3862 HWDiv |= HWDivARM; 3863 else if (Features[i] == "+crc") 3864 CRC = 1; 3865 else if (Features[i] == "+crypto") 3866 Crypto = 1; 3867 } 3868 3869 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 3870 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 3871 return false; 3872 } 3873 3874 if (FPMath == FP_Neon) 3875 Features.push_back("+neonfp"); 3876 else if (FPMath == FP_VFP) 3877 Features.push_back("-neonfp"); 3878 3879 // Remove front-end specific options which the backend handles differently. 3880 std::vector<std::string>::iterator it; 3881 it = std::find(Features.begin(), Features.end(), "+soft-float"); 3882 if (it != Features.end()) 3883 Features.erase(it); 3884 it = std::find(Features.begin(), Features.end(), "+soft-float-abi"); 3885 if (it != Features.end()) 3886 Features.erase(it); 3887 return true; 3888 } 3889 3890 bool hasFeature(StringRef Feature) const override { 3891 return llvm::StringSwitch<bool>(Feature) 3892 .Case("arm", true) 3893 .Case("softfloat", SoftFloat) 3894 .Case("thumb", IsThumb) 3895 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 3896 .Case("hwdiv", HWDiv & HWDivThumb) 3897 .Case("hwdiv-arm", HWDiv & HWDivARM) 3898 .Default(false); 3899 } 3900 // FIXME: Should we actually have some table instead of these switches? 3901 static const char *getCPUDefineSuffix(StringRef Name) { 3902 return llvm::StringSwitch<const char*>(Name) 3903 .Cases("arm8", "arm810", "4") 3904 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") 3905 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 3906 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 3907 .Case("ep9312", "4T") 3908 .Cases("arm10tdmi", "arm1020t", "5T") 3909 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 3910 .Case("arm926ej-s", "5TEJ") 3911 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 3912 .Cases("xscale", "iwmmxt", "5TE") 3913 .Case("arm1136j-s", "6J") 3914 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 3915 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 3916 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 3917 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "cortex-a9-mp", "7A") 3918 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "7A") 3919 .Cases("cortex-r4", "cortex-r5", "7R") 3920 .Case("swift", "7S") 3921 .Case("cyclone", "8A") 3922 .Case("cortex-m3", "7M") 3923 .Case("cortex-m4", "7EM") 3924 .Case("cortex-m0", "6M") 3925 .Cases("cortex-a53", "cortex-a57", "8A") 3926 .Default(nullptr); 3927 } 3928 static const char *getCPUProfile(StringRef Name) { 3929 return llvm::StringSwitch<const char*>(Name) 3930 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A") 3931 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "A") 3932 .Cases("cortex-a53", "cortex-a57", "A") 3933 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M") 3934 .Cases("cortex-r4", "cortex-r5", "R") 3935 .Default(""); 3936 } 3937 bool setCPU(const std::string &Name) override { 3938 if (!getCPUDefineSuffix(Name)) 3939 return false; 3940 3941 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 3942 StringRef Profile = getCPUProfile(Name); 3943 if (Profile == "M" && MaxAtomicInlineWidth) { 3944 MaxAtomicPromoteWidth = 32; 3945 MaxAtomicInlineWidth = 32; 3946 } 3947 3948 CPU = Name; 3949 return true; 3950 } 3951 bool setFPMath(StringRef Name) override; 3952 bool supportsThumb(StringRef ArchName, StringRef CPUArch, 3953 unsigned CPUArchVer) const { 3954 return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) || 3955 (CPUArch.find('M') != StringRef::npos); 3956 } 3957 bool supportsThumb2(StringRef ArchName, StringRef CPUArch, 3958 unsigned CPUArchVer) const { 3959 // We check both CPUArchVer and ArchName because when only triple is 3960 // specified, the default CPU is arm1136j-s. 3961 return ArchName.endswith("v6t2") || ArchName.endswith("v7") || 3962 ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7; 3963 } 3964 void getTargetDefines(const LangOptions &Opts, 3965 MacroBuilder &Builder) const override { 3966 // Target identification. 3967 Builder.defineMacro("__arm"); 3968 Builder.defineMacro("__arm__"); 3969 3970 // Target properties. 3971 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3972 3973 StringRef CPUArch = getCPUDefineSuffix(CPU); 3974 unsigned int CPUArchVer; 3975 if(CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) { 3976 llvm_unreachable("Invalid char for architecture version number"); 3977 } 3978 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 3979 3980 // ACLE 6.4.1 ARM/Thumb instruction set architecture 3981 StringRef CPUProfile = getCPUProfile(CPU); 3982 StringRef ArchName = getTriple().getArchName(); 3983 3984 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 3985 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 3986 3987 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 3988 // is not defined for the M-profile. 3989 // NOTE that the deffault profile is assumed to be 'A' 3990 if (CPUProfile.empty() || CPUProfile != "M") 3991 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 3992 3993 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 3994 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 3995 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 3996 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 3997 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 3998 else if (supportsThumb(ArchName, CPUArch, CPUArchVer)) 3999 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4000 4001 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4002 // instruction set such as ARM or Thumb. 4003 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4004 4005 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4006 4007 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4008 if (!CPUProfile.empty()) 4009 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4010 4011 // ACLE predefines. 4012 Builder.defineMacro("__ARM_ACLE", "200"); 4013 4014 // Subtarget options. 4015 4016 // FIXME: It's more complicated than this and we don't really support 4017 // interworking. 4018 // Windows on ARM does not "support" interworking 4019 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows()) 4020 Builder.defineMacro("__THUMB_INTERWORK__"); 4021 4022 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4023 // Embedded targets on Darwin follow AAPCS, but not EABI. 4024 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4025 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4026 Builder.defineMacro("__ARM_EABI__"); 4027 Builder.defineMacro("__ARM_PCS", "1"); 4028 4029 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4030 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4031 } 4032 4033 if (SoftFloat) 4034 Builder.defineMacro("__SOFTFP__"); 4035 4036 if (CPU == "xscale") 4037 Builder.defineMacro("__XSCALE__"); 4038 4039 if (IsThumb) { 4040 Builder.defineMacro("__THUMBEL__"); 4041 Builder.defineMacro("__thumb__"); 4042 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4043 Builder.defineMacro("__thumb2__"); 4044 } 4045 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 4046 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4047 4048 // Note, this is always on in gcc, even though it doesn't make sense. 4049 Builder.defineMacro("__APCS_32__"); 4050 4051 if (FPUModeIsVFP((FPUMode) FPU)) { 4052 Builder.defineMacro("__VFP_FP__"); 4053 if (FPU & VFP2FPU) 4054 Builder.defineMacro("__ARM_VFPV2__"); 4055 if (FPU & VFP3FPU) 4056 Builder.defineMacro("__ARM_VFPV3__"); 4057 if (FPU & VFP4FPU) 4058 Builder.defineMacro("__ARM_VFPV4__"); 4059 } 4060 4061 // This only gets set when Neon instructions are actually available, unlike 4062 // the VFP define, hence the soft float and arch check. This is subtly 4063 // different from gcc, we follow the intent which was that it should be set 4064 // when Neon instructions are actually available. 4065 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) { 4066 Builder.defineMacro("__ARM_NEON"); 4067 Builder.defineMacro("__ARM_NEON__"); 4068 } 4069 4070 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4071 Opts.ShortWChar ? "2" : "4"); 4072 4073 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4074 Opts.ShortEnums ? "1" : "4"); 4075 4076 if (CRC) 4077 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4078 4079 if (Crypto) 4080 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4081 4082 if (CPUArchVer >= 6 && CPUArch != "6M") { 4083 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4084 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4085 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4086 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4087 } 4088 } 4089 void getTargetBuiltins(const Builtin::Info *&Records, 4090 unsigned &NumRecords) const override { 4091 Records = BuiltinInfo; 4092 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4093 } 4094 bool isCLZForZeroUndef() const override { return false; } 4095 BuiltinVaListKind getBuiltinVaListKind() const override { 4096 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4097 } 4098 void getGCCRegNames(const char * const *&Names, 4099 unsigned &NumNames) const override; 4100 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4101 unsigned &NumAliases) const override; 4102 bool validateAsmConstraint(const char *&Name, 4103 TargetInfo::ConstraintInfo &Info) const override { 4104 switch (*Name) { 4105 default: break; 4106 case 'l': // r0-r7 4107 case 'h': // r8-r15 4108 case 'w': // VFP Floating point register single precision 4109 case 'P': // VFP Floating point register double precision 4110 Info.setAllowsRegister(); 4111 return true; 4112 case 'Q': // A memory address that is a single base register. 4113 Info.setAllowsMemory(); 4114 return true; 4115 case 'U': // a memory reference... 4116 switch (Name[1]) { 4117 case 'q': // ...ARMV4 ldrsb 4118 case 'v': // ...VFP load/store (reg+constant offset) 4119 case 'y': // ...iWMMXt load/store 4120 case 't': // address valid for load/store opaque types wider 4121 // than 128-bits 4122 case 'n': // valid address for Neon doubleword vector load/store 4123 case 'm': // valid address for Neon element and structure load/store 4124 case 's': // valid address for non-offset loads/stores of quad-word 4125 // values in four ARM registers 4126 Info.setAllowsMemory(); 4127 Name++; 4128 return true; 4129 } 4130 } 4131 return false; 4132 } 4133 std::string convertConstraint(const char *&Constraint) const override { 4134 std::string R; 4135 switch (*Constraint) { 4136 case 'U': // Two-character constraint; add "^" hint for later parsing. 4137 R = std::string("^") + std::string(Constraint, 2); 4138 Constraint++; 4139 break; 4140 case 'p': // 'p' should be translated to 'r' by default. 4141 R = std::string("r"); 4142 break; 4143 default: 4144 return std::string(1, *Constraint); 4145 } 4146 return R; 4147 } 4148 bool 4149 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4150 std::string &SuggestedModifier) const override { 4151 bool isOutput = (Constraint[0] == '='); 4152 bool isInOut = (Constraint[0] == '+'); 4153 4154 // Strip off constraint modifiers. 4155 while (Constraint[0] == '=' || 4156 Constraint[0] == '+' || 4157 Constraint[0] == '&') 4158 Constraint = Constraint.substr(1); 4159 4160 switch (Constraint[0]) { 4161 default: break; 4162 case 'r': { 4163 switch (Modifier) { 4164 default: 4165 return (isInOut || isOutput || Size <= 64); 4166 case 'q': 4167 // A register of size 32 cannot fit a vector type. 4168 return false; 4169 } 4170 } 4171 } 4172 4173 return true; 4174 } 4175 const char *getClobbers() const override { 4176 // FIXME: Is this really right? 4177 return ""; 4178 } 4179 4180 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4181 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4182 } 4183 4184 int getEHDataRegisterNumber(unsigned RegNo) const override { 4185 if (RegNo == 0) return 0; 4186 if (RegNo == 1) return 1; 4187 return -1; 4188 } 4189 }; 4190 4191 bool ARMTargetInfo::setFPMath(StringRef Name) { 4192 if (Name == "neon") { 4193 FPMath = FP_Neon; 4194 return true; 4195 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4196 Name == "vfp4") { 4197 FPMath = FP_VFP; 4198 return true; 4199 } 4200 return false; 4201 } 4202 4203 const char * const ARMTargetInfo::GCCRegNames[] = { 4204 // Integer registers 4205 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4206 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4207 4208 // Float registers 4209 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4210 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4211 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4212 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4213 4214 // Double registers 4215 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4216 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4217 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4218 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4219 4220 // Quad registers 4221 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4222 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4223 }; 4224 4225 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4226 unsigned &NumNames) const { 4227 Names = GCCRegNames; 4228 NumNames = llvm::array_lengthof(GCCRegNames); 4229 } 4230 4231 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4232 { { "a1" }, "r0" }, 4233 { { "a2" }, "r1" }, 4234 { { "a3" }, "r2" }, 4235 { { "a4" }, "r3" }, 4236 { { "v1" }, "r4" }, 4237 { { "v2" }, "r5" }, 4238 { { "v3" }, "r6" }, 4239 { { "v4" }, "r7" }, 4240 { { "v5" }, "r8" }, 4241 { { "v6", "rfp" }, "r9" }, 4242 { { "sl" }, "r10" }, 4243 { { "fp" }, "r11" }, 4244 { { "ip" }, "r12" }, 4245 { { "r13" }, "sp" }, 4246 { { "r14" }, "lr" }, 4247 { { "r15" }, "pc" }, 4248 // The S, D and Q registers overlap, but aren't really aliases; we 4249 // don't want to substitute one of these for a different-sized one. 4250 }; 4251 4252 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4253 unsigned &NumAliases) const { 4254 Aliases = GCCRegAliases; 4255 NumAliases = llvm::array_lengthof(GCCRegAliases); 4256 } 4257 4258 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4259 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4260 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4261 ALL_LANGUAGES }, 4262 #include "clang/Basic/BuiltinsNEON.def" 4263 4264 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4265 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG }, 4266 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4267 ALL_LANGUAGES }, 4268 #include "clang/Basic/BuiltinsARM.def" 4269 }; 4270 4271 class ARMleTargetInfo : public ARMTargetInfo { 4272 public: 4273 ARMleTargetInfo(const llvm::Triple &Triple) 4274 : ARMTargetInfo(Triple, false) { } 4275 virtual void getTargetDefines(const LangOptions &Opts, 4276 MacroBuilder &Builder) const { 4277 Builder.defineMacro("__ARMEL__"); 4278 ARMTargetInfo::getTargetDefines(Opts, Builder); 4279 } 4280 }; 4281 4282 class ARMbeTargetInfo : public ARMTargetInfo { 4283 public: 4284 ARMbeTargetInfo(const llvm::Triple &Triple) 4285 : ARMTargetInfo(Triple, true) { } 4286 virtual void getTargetDefines(const LangOptions &Opts, 4287 MacroBuilder &Builder) const { 4288 Builder.defineMacro("__ARMEB__"); 4289 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4290 ARMTargetInfo::getTargetDefines(Opts, Builder); 4291 } 4292 }; 4293 } // end anonymous namespace. 4294 4295 namespace { 4296 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 4297 const llvm::Triple Triple; 4298 public: 4299 WindowsARMTargetInfo(const llvm::Triple &Triple) 4300 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 4301 TLSSupported = false; 4302 WCharType = UnsignedShort; 4303 SizeType = UnsignedInt; 4304 UserLabelPrefix = ""; 4305 } 4306 void getVisualStudioDefines(const LangOptions &Opts, 4307 MacroBuilder &Builder) const { 4308 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 4309 4310 // FIXME: this is invalid for WindowsCE 4311 Builder.defineMacro("_M_ARM_NT", "1"); 4312 Builder.defineMacro("_M_ARMT", "_M_ARM"); 4313 Builder.defineMacro("_M_THUMB", "_M_ARM"); 4314 4315 assert((Triple.getArch() == llvm::Triple::arm || 4316 Triple.getArch() == llvm::Triple::thumb) && 4317 "invalid architecture for Windows ARM target info"); 4318 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 4319 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 4320 4321 // TODO map the complete set of values 4322 // 31: VFPv3 40: VFPv4 4323 Builder.defineMacro("_M_ARM_FP", "31"); 4324 } 4325 BuiltinVaListKind getBuiltinVaListKind() const override { 4326 return TargetInfo::CharPtrBuiltinVaList; 4327 } 4328 }; 4329 4330 // Windows ARM + Itanium C++ ABI Target 4331 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 4332 public: 4333 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 4334 : WindowsARMTargetInfo(Triple) { 4335 TheCXXABI.set(TargetCXXABI::GenericARM); 4336 } 4337 4338 void getTargetDefines(const LangOptions &Opts, 4339 MacroBuilder &Builder) const override { 4340 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4341 4342 if (Opts.MSVCCompat) 4343 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4344 } 4345 }; 4346 4347 // Windows ARM, MS (C++) ABI 4348 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 4349 public: 4350 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 4351 : WindowsARMTargetInfo(Triple) { 4352 TheCXXABI.set(TargetCXXABI::Microsoft); 4353 } 4354 4355 void getTargetDefines(const LangOptions &Opts, 4356 MacroBuilder &Builder) const override { 4357 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4358 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4359 } 4360 }; 4361 } 4362 4363 4364 namespace { 4365 class DarwinARMTargetInfo : 4366 public DarwinTargetInfo<ARMleTargetInfo> { 4367 protected: 4368 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4369 MacroBuilder &Builder) const override { 4370 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4371 } 4372 4373 public: 4374 DarwinARMTargetInfo(const llvm::Triple &Triple) 4375 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 4376 HasAlignMac68kSupport = true; 4377 // iOS always has 64-bit atomic instructions. 4378 // FIXME: This should be based off of the target features in ARMleTargetInfo. 4379 MaxAtomicInlineWidth = 64; 4380 4381 // Darwin on iOS uses a variant of the ARM C++ ABI. 4382 TheCXXABI.set(TargetCXXABI::iOS); 4383 } 4384 }; 4385 } // end anonymous namespace. 4386 4387 4388 namespace { 4389 class AArch64TargetInfo : public TargetInfo { 4390 virtual void setDescriptionString() = 0; 4391 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4392 static const char *const GCCRegNames[]; 4393 4394 enum FPUModeEnum { 4395 FPUMode, 4396 NeonMode 4397 }; 4398 4399 unsigned FPU; 4400 unsigned CRC; 4401 unsigned Crypto; 4402 4403 static const Builtin::Info BuiltinInfo[]; 4404 4405 std::string ABI; 4406 4407 public: 4408 AArch64TargetInfo(const llvm::Triple &Triple) 4409 : TargetInfo(Triple), ABI("aapcs") { 4410 4411 if (getTriple().getOS() == llvm::Triple::NetBSD) { 4412 WCharType = SignedInt; 4413 4414 // NetBSD apparently prefers consistency across ARM targets to consistency 4415 // across 64-bit targets. 4416 Int64Type = SignedLongLong; 4417 IntMaxType = SignedLongLong; 4418 } else { 4419 WCharType = UnsignedInt; 4420 Int64Type = SignedLong; 4421 IntMaxType = SignedLong; 4422 } 4423 4424 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4425 MaxVectorAlign = 128; 4426 RegParmMax = 8; 4427 MaxAtomicInlineWidth = 128; 4428 MaxAtomicPromoteWidth = 128; 4429 4430 LongDoubleWidth = LongDoubleAlign = 128; 4431 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4432 4433 // {} in inline assembly are neon specifiers, not assembly variant 4434 // specifiers. 4435 NoAsmVariants = true; 4436 4437 // AArch64 targets default to using the ARM C++ ABI. 4438 TheCXXABI.set(TargetCXXABI::GenericAArch64); 4439 } 4440 4441 StringRef getABI() const override { return ABI; } 4442 virtual bool setABI(const std::string &Name) { 4443 if (Name != "aapcs" && Name != "darwinpcs") 4444 return false; 4445 4446 ABI = Name; 4447 return true; 4448 } 4449 4450 virtual bool setCPU(const std::string &Name) { 4451 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4452 .Case("generic", true) 4453 .Cases("cortex-a53", "cortex-a57", true) 4454 .Case("cyclone", true) 4455 .Default(false); 4456 return CPUKnown; 4457 } 4458 4459 virtual void getTargetDefines(const LangOptions &Opts, 4460 MacroBuilder &Builder) const { 4461 // Target identification. 4462 Builder.defineMacro("__aarch64__"); 4463 4464 // Target properties. 4465 Builder.defineMacro("_LP64"); 4466 Builder.defineMacro("__LP64__"); 4467 4468 // ACLE predefines. Many can only have one possible value on v8 AArch64. 4469 Builder.defineMacro("__ARM_ACLE", "200"); 4470 Builder.defineMacro("__ARM_ARCH", "8"); 4471 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 4472 4473 Builder.defineMacro("__ARM_64BIT_STATE"); 4474 Builder.defineMacro("__ARM_PCS_AAPCS64"); 4475 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 4476 4477 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 4478 Builder.defineMacro("__ARM_FEATURE_CLZ"); 4479 Builder.defineMacro("__ARM_FEATURE_FMA"); 4480 Builder.defineMacro("__ARM_FEATURE_DIV"); 4481 4482 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 4483 4484 // 0xe implies support for half, single and double precision operations. 4485 Builder.defineMacro("__ARM_FP", "0xe"); 4486 4487 // PCS specifies this for SysV variants, which is all we support. Other ABIs 4488 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 4489 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 4490 4491 if (Opts.FastMath || Opts.FiniteMathOnly) 4492 Builder.defineMacro("__ARM_FP_FAST"); 4493 4494 if ((Opts.C99 || Opts.C11) && !Opts.Freestanding) 4495 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 4496 4497 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 4498 4499 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4500 Opts.ShortEnums ? "1" : "4"); 4501 4502 if (FPU == NeonMode) { 4503 Builder.defineMacro("__ARM_NEON"); 4504 // 64-bit NEON supports half, single and double precision operations. 4505 Builder.defineMacro("__ARM_NEON_FP", "0xe"); 4506 } 4507 4508 if (CRC) 4509 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4510 4511 if (Crypto) 4512 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4513 } 4514 4515 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4516 unsigned &NumRecords) const { 4517 Records = BuiltinInfo; 4518 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin; 4519 } 4520 4521 virtual bool hasFeature(StringRef Feature) const { 4522 return Feature == "aarch64" || 4523 Feature == "arm64" || 4524 (Feature == "neon" && FPU == NeonMode); 4525 } 4526 4527 bool handleTargetFeatures(std::vector<std::string> &Features, 4528 DiagnosticsEngine &Diags) override { 4529 FPU = FPUMode; 4530 CRC = 0; 4531 Crypto = 0; 4532 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 4533 if (Features[i] == "+neon") 4534 FPU = NeonMode; 4535 if (Features[i] == "+crc") 4536 CRC = 1; 4537 if (Features[i] == "+crypto") 4538 Crypto = 1; 4539 } 4540 4541 setDescriptionString(); 4542 4543 return true; 4544 } 4545 4546 virtual bool isCLZForZeroUndef() const { return false; } 4547 4548 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4549 return TargetInfo::AArch64ABIBuiltinVaList; 4550 } 4551 4552 virtual void getGCCRegNames(const char *const *&Names, 4553 unsigned &NumNames) const; 4554 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4555 unsigned &NumAliases) const; 4556 4557 virtual bool validateAsmConstraint(const char *&Name, 4558 TargetInfo::ConstraintInfo &Info) const { 4559 switch (*Name) { 4560 default: 4561 return false; 4562 case 'w': // Floating point and SIMD registers (V0-V31) 4563 Info.setAllowsRegister(); 4564 return true; 4565 case 'I': // Constant that can be used with an ADD instruction 4566 case 'J': // Constant that can be used with a SUB instruction 4567 case 'K': // Constant that can be used with a 32-bit logical instruction 4568 case 'L': // Constant that can be used with a 64-bit logical instruction 4569 case 'M': // Constant that can be used as a 32-bit MOV immediate 4570 case 'N': // Constant that can be used as a 64-bit MOV immediate 4571 case 'Y': // Floating point constant zero 4572 case 'Z': // Integer constant zero 4573 return true; 4574 case 'Q': // A memory reference with base register and no offset 4575 Info.setAllowsMemory(); 4576 return true; 4577 case 'S': // A symbolic address 4578 Info.setAllowsRegister(); 4579 return true; 4580 case 'U': 4581 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be 4582 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be 4583 // Usa: An absolute symbolic address 4584 // Ush: The high part (bits 32:12) of a pc-relative symbolic address 4585 llvm_unreachable("FIXME: Unimplemented support for bizarre constraints"); 4586 case 'z': // Zero register, wzr or xzr 4587 Info.setAllowsRegister(); 4588 return true; 4589 case 'x': // Floating point and SIMD registers (V0-V15) 4590 Info.setAllowsRegister(); 4591 return true; 4592 } 4593 return false; 4594 } 4595 4596 bool 4597 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4598 std::string &SuggestedModifier) const override { 4599 // Strip off constraint modifiers. 4600 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 4601 Constraint = Constraint.substr(1); 4602 4603 switch (Constraint[0]) { 4604 default: 4605 return true; 4606 case 'z': 4607 case 'r': { 4608 switch (Modifier) { 4609 case 'x': 4610 case 'w': 4611 // For now assume that the person knows what they're 4612 // doing with the modifier. 4613 return true; 4614 default: 4615 // By default an 'r' constraint will be in the 'x' 4616 // registers. 4617 if (Size == 64) 4618 return true; 4619 4620 SuggestedModifier = "w"; 4621 return false; 4622 } 4623 } 4624 } 4625 } 4626 4627 virtual const char *getClobbers() const { return ""; } 4628 4629 int getEHDataRegisterNumber(unsigned RegNo) const { 4630 if (RegNo == 0) 4631 return 0; 4632 if (RegNo == 1) 4633 return 1; 4634 return -1; 4635 } 4636 }; 4637 4638 const char *const AArch64TargetInfo::GCCRegNames[] = { 4639 // 32-bit Integer registers 4640 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 4641 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 4642 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 4643 4644 // 64-bit Integer registers 4645 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 4646 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 4647 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 4648 4649 // 32-bit floating point regsisters 4650 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 4651 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 4652 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4653 4654 // 64-bit floating point regsisters 4655 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 4656 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 4657 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4658 4659 // Vector registers 4660 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 4661 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 4662 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 4663 }; 4664 4665 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names, 4666 unsigned &NumNames) const { 4667 Names = GCCRegNames; 4668 NumNames = llvm::array_lengthof(GCCRegNames); 4669 } 4670 4671 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 4672 { { "w31" }, "wsp" }, 4673 { { "x29" }, "fp" }, 4674 { { "x30" }, "lr" }, 4675 { { "x31" }, "sp" }, 4676 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 4677 // don't want to substitute one of these for a different-sized one. 4678 }; 4679 4680 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4681 unsigned &NumAliases) const { 4682 Aliases = GCCRegAliases; 4683 NumAliases = llvm::array_lengthof(GCCRegAliases); 4684 } 4685 4686 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 4687 #define BUILTIN(ID, TYPE, ATTRS) \ 4688 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4689 #include "clang/Basic/BuiltinsNEON.def" 4690 4691 #define BUILTIN(ID, TYPE, ATTRS) \ 4692 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4693 #include "clang/Basic/BuiltinsAArch64.def" 4694 }; 4695 4696 class AArch64leTargetInfo : public AArch64TargetInfo { 4697 void setDescriptionString() override { 4698 if (getTriple().isOSBinFormatMachO()) 4699 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128"; 4700 else 4701 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 4702 } 4703 4704 public: 4705 AArch64leTargetInfo(const llvm::Triple &Triple) 4706 : AArch64TargetInfo(Triple) { 4707 BigEndian = false; 4708 } 4709 void getTargetDefines(const LangOptions &Opts, 4710 MacroBuilder &Builder) const override { 4711 Builder.defineMacro("__AARCH64EL__"); 4712 AArch64TargetInfo::getTargetDefines(Opts, Builder); 4713 } 4714 }; 4715 4716 class AArch64beTargetInfo : public AArch64TargetInfo { 4717 void setDescriptionString() override { 4718 assert(!getTriple().isOSBinFormatMachO()); 4719 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128"; 4720 } 4721 4722 public: 4723 AArch64beTargetInfo(const llvm::Triple &Triple) 4724 : AArch64TargetInfo(Triple) { } 4725 void getTargetDefines(const LangOptions &Opts, 4726 MacroBuilder &Builder) const override { 4727 Builder.defineMacro("__AARCH64EB__"); 4728 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 4729 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4730 AArch64TargetInfo::getTargetDefines(Opts, Builder); 4731 } 4732 }; 4733 } // end anonymous namespace. 4734 4735 namespace { 4736 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 4737 protected: 4738 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4739 MacroBuilder &Builder) const override { 4740 Builder.defineMacro("__AARCH64_SIMD__"); 4741 Builder.defineMacro("__ARM64_ARCH_8__"); 4742 Builder.defineMacro("__ARM_NEON__"); 4743 Builder.defineMacro("__LITTLE_ENDIAN__"); 4744 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4745 Builder.defineMacro("__arm64", "1"); 4746 Builder.defineMacro("__arm64__", "1"); 4747 4748 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4749 } 4750 4751 public: 4752 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 4753 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 4754 Int64Type = SignedLongLong; 4755 WCharType = SignedInt; 4756 UseSignedCharForObjCBool = false; 4757 4758 LongDoubleWidth = LongDoubleAlign = 64; 4759 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4760 4761 TheCXXABI.set(TargetCXXABI::iOS64); 4762 } 4763 4764 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4765 return TargetInfo::CharPtrBuiltinVaList; 4766 } 4767 }; 4768 } // end anonymous namespace 4769 4770 namespace { 4771 // Hexagon abstract base class 4772 class HexagonTargetInfo : public TargetInfo { 4773 static const Builtin::Info BuiltinInfo[]; 4774 static const char * const GCCRegNames[]; 4775 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4776 std::string CPU; 4777 public: 4778 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4779 BigEndian = false; 4780 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 4781 4782 // {} in inline assembly are packet specifiers, not assembly variant 4783 // specifiers. 4784 NoAsmVariants = true; 4785 } 4786 4787 void getTargetBuiltins(const Builtin::Info *&Records, 4788 unsigned &NumRecords) const override { 4789 Records = BuiltinInfo; 4790 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 4791 } 4792 4793 bool validateAsmConstraint(const char *&Name, 4794 TargetInfo::ConstraintInfo &Info) const override { 4795 return true; 4796 } 4797 4798 void getTargetDefines(const LangOptions &Opts, 4799 MacroBuilder &Builder) const override; 4800 4801 bool hasFeature(StringRef Feature) const override { 4802 return Feature == "hexagon"; 4803 } 4804 4805 BuiltinVaListKind getBuiltinVaListKind() const override { 4806 return TargetInfo::CharPtrBuiltinVaList; 4807 } 4808 void getGCCRegNames(const char * const *&Names, 4809 unsigned &NumNames) const override; 4810 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4811 unsigned &NumAliases) const override; 4812 const char *getClobbers() const override { 4813 return ""; 4814 } 4815 4816 static const char *getHexagonCPUSuffix(StringRef Name) { 4817 return llvm::StringSwitch<const char*>(Name) 4818 .Case("hexagonv4", "4") 4819 .Case("hexagonv5", "5") 4820 .Default(nullptr); 4821 } 4822 4823 bool setCPU(const std::string &Name) override { 4824 if (!getHexagonCPUSuffix(Name)) 4825 return false; 4826 4827 CPU = Name; 4828 return true; 4829 } 4830 }; 4831 4832 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 4833 MacroBuilder &Builder) const { 4834 Builder.defineMacro("qdsp6"); 4835 Builder.defineMacro("__qdsp6", "1"); 4836 Builder.defineMacro("__qdsp6__", "1"); 4837 4838 Builder.defineMacro("hexagon"); 4839 Builder.defineMacro("__hexagon", "1"); 4840 Builder.defineMacro("__hexagon__", "1"); 4841 4842 if(CPU == "hexagonv1") { 4843 Builder.defineMacro("__HEXAGON_V1__"); 4844 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 4845 if(Opts.HexagonQdsp6Compat) { 4846 Builder.defineMacro("__QDSP6_V1__"); 4847 Builder.defineMacro("__QDSP6_ARCH__", "1"); 4848 } 4849 } 4850 else if(CPU == "hexagonv2") { 4851 Builder.defineMacro("__HEXAGON_V2__"); 4852 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 4853 if(Opts.HexagonQdsp6Compat) { 4854 Builder.defineMacro("__QDSP6_V2__"); 4855 Builder.defineMacro("__QDSP6_ARCH__", "2"); 4856 } 4857 } 4858 else if(CPU == "hexagonv3") { 4859 Builder.defineMacro("__HEXAGON_V3__"); 4860 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 4861 if(Opts.HexagonQdsp6Compat) { 4862 Builder.defineMacro("__QDSP6_V3__"); 4863 Builder.defineMacro("__QDSP6_ARCH__", "3"); 4864 } 4865 } 4866 else if(CPU == "hexagonv4") { 4867 Builder.defineMacro("__HEXAGON_V4__"); 4868 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 4869 if(Opts.HexagonQdsp6Compat) { 4870 Builder.defineMacro("__QDSP6_V4__"); 4871 Builder.defineMacro("__QDSP6_ARCH__", "4"); 4872 } 4873 } 4874 else if(CPU == "hexagonv5") { 4875 Builder.defineMacro("__HEXAGON_V5__"); 4876 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 4877 if(Opts.HexagonQdsp6Compat) { 4878 Builder.defineMacro("__QDSP6_V5__"); 4879 Builder.defineMacro("__QDSP6_ARCH__", "5"); 4880 } 4881 } 4882 } 4883 4884 const char * const HexagonTargetInfo::GCCRegNames[] = { 4885 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4886 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4887 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4888 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 4889 "p0", "p1", "p2", "p3", 4890 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 4891 }; 4892 4893 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 4894 unsigned &NumNames) const { 4895 Names = GCCRegNames; 4896 NumNames = llvm::array_lengthof(GCCRegNames); 4897 } 4898 4899 4900 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 4901 { { "sp" }, "r29" }, 4902 { { "fp" }, "r30" }, 4903 { { "lr" }, "r31" }, 4904 }; 4905 4906 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4907 unsigned &NumAliases) const { 4908 Aliases = GCCRegAliases; 4909 NumAliases = llvm::array_lengthof(GCCRegAliases); 4910 } 4911 4912 4913 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 4914 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4915 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4916 ALL_LANGUAGES }, 4917 #include "clang/Basic/BuiltinsHexagon.def" 4918 }; 4919 } 4920 4921 4922 namespace { 4923 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 4924 class SparcTargetInfo : public TargetInfo { 4925 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4926 static const char * const GCCRegNames[]; 4927 bool SoftFloat; 4928 public: 4929 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {} 4930 4931 bool handleTargetFeatures(std::vector<std::string> &Features, 4932 DiagnosticsEngine &Diags) override { 4933 SoftFloat = false; 4934 for (unsigned i = 0, e = Features.size(); i != e; ++i) 4935 if (Features[i] == "+soft-float") 4936 SoftFloat = true; 4937 return true; 4938 } 4939 void getTargetDefines(const LangOptions &Opts, 4940 MacroBuilder &Builder) const override { 4941 DefineStd(Builder, "sparc", Opts); 4942 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4943 4944 if (SoftFloat) 4945 Builder.defineMacro("SOFT_FLOAT", "1"); 4946 } 4947 4948 bool hasFeature(StringRef Feature) const override { 4949 return llvm::StringSwitch<bool>(Feature) 4950 .Case("softfloat", SoftFloat) 4951 .Case("sparc", true) 4952 .Default(false); 4953 } 4954 4955 void getTargetBuiltins(const Builtin::Info *&Records, 4956 unsigned &NumRecords) const override { 4957 // FIXME: Implement! 4958 } 4959 BuiltinVaListKind getBuiltinVaListKind() const override { 4960 return TargetInfo::VoidPtrBuiltinVaList; 4961 } 4962 void getGCCRegNames(const char * const *&Names, 4963 unsigned &NumNames) const override; 4964 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4965 unsigned &NumAliases) const override; 4966 bool validateAsmConstraint(const char *&Name, 4967 TargetInfo::ConstraintInfo &info) const override { 4968 // FIXME: Implement! 4969 return false; 4970 } 4971 const char *getClobbers() const override { 4972 // FIXME: Implement! 4973 return ""; 4974 } 4975 }; 4976 4977 const char * const SparcTargetInfo::GCCRegNames[] = { 4978 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4979 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4980 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4981 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 4982 }; 4983 4984 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 4985 unsigned &NumNames) const { 4986 Names = GCCRegNames; 4987 NumNames = llvm::array_lengthof(GCCRegNames); 4988 } 4989 4990 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 4991 { { "g0" }, "r0" }, 4992 { { "g1" }, "r1" }, 4993 { { "g2" }, "r2" }, 4994 { { "g3" }, "r3" }, 4995 { { "g4" }, "r4" }, 4996 { { "g5" }, "r5" }, 4997 { { "g6" }, "r6" }, 4998 { { "g7" }, "r7" }, 4999 { { "o0" }, "r8" }, 5000 { { "o1" }, "r9" }, 5001 { { "o2" }, "r10" }, 5002 { { "o3" }, "r11" }, 5003 { { "o4" }, "r12" }, 5004 { { "o5" }, "r13" }, 5005 { { "o6", "sp" }, "r14" }, 5006 { { "o7" }, "r15" }, 5007 { { "l0" }, "r16" }, 5008 { { "l1" }, "r17" }, 5009 { { "l2" }, "r18" }, 5010 { { "l3" }, "r19" }, 5011 { { "l4" }, "r20" }, 5012 { { "l5" }, "r21" }, 5013 { { "l6" }, "r22" }, 5014 { { "l7" }, "r23" }, 5015 { { "i0" }, "r24" }, 5016 { { "i1" }, "r25" }, 5017 { { "i2" }, "r26" }, 5018 { { "i3" }, "r27" }, 5019 { { "i4" }, "r28" }, 5020 { { "i5" }, "r29" }, 5021 { { "i6", "fp" }, "r30" }, 5022 { { "i7" }, "r31" }, 5023 }; 5024 5025 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5026 unsigned &NumAliases) const { 5027 Aliases = GCCRegAliases; 5028 NumAliases = llvm::array_lengthof(GCCRegAliases); 5029 } 5030 5031 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5032 class SparcV8TargetInfo : public SparcTargetInfo { 5033 public: 5034 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5035 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5036 } 5037 5038 void getTargetDefines(const LangOptions &Opts, 5039 MacroBuilder &Builder) const override { 5040 SparcTargetInfo::getTargetDefines(Opts, Builder); 5041 Builder.defineMacro("__sparcv8"); 5042 } 5043 }; 5044 5045 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 5046 class SparcV9TargetInfo : public SparcTargetInfo { 5047 public: 5048 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5049 // FIXME: Support Sparc quad-precision long double? 5050 DescriptionString = "E-m:e-i64:64-n32:64-S128"; 5051 // This is an LP64 platform. 5052 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5053 5054 // OpenBSD uses long long for int64_t and intmax_t. 5055 if (getTriple().getOS() == llvm::Triple::OpenBSD) 5056 IntMaxType = SignedLongLong; 5057 else 5058 IntMaxType = SignedLong; 5059 Int64Type = IntMaxType; 5060 5061 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 5062 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 5063 LongDoubleWidth = 128; 5064 LongDoubleAlign = 128; 5065 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5066 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5067 } 5068 5069 void getTargetDefines(const LangOptions &Opts, 5070 MacroBuilder &Builder) const override { 5071 SparcTargetInfo::getTargetDefines(Opts, Builder); 5072 Builder.defineMacro("__sparcv9"); 5073 Builder.defineMacro("__arch64__"); 5074 // Solaris doesn't need these variants, but the BSDs do. 5075 if (getTriple().getOS() != llvm::Triple::Solaris) { 5076 Builder.defineMacro("__sparc64__"); 5077 Builder.defineMacro("__sparc_v9__"); 5078 Builder.defineMacro("__sparcv9__"); 5079 } 5080 } 5081 5082 bool setCPU(const std::string &Name) override { 5083 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5084 .Case("v9", true) 5085 .Case("ultrasparc", true) 5086 .Case("ultrasparc3", true) 5087 .Case("niagara", true) 5088 .Case("niagara2", true) 5089 .Case("niagara3", true) 5090 .Case("niagara4", true) 5091 .Default(false); 5092 5093 // No need to store the CPU yet. There aren't any CPU-specific 5094 // macros to define. 5095 return CPUKnown; 5096 } 5097 }; 5098 5099 } // end anonymous namespace. 5100 5101 namespace { 5102 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 5103 public: 5104 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 5105 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 5106 SizeType = UnsignedInt; 5107 PtrDiffType = SignedInt; 5108 } 5109 }; 5110 } // end anonymous namespace. 5111 5112 namespace { 5113 class SystemZTargetInfo : public TargetInfo { 5114 static const char *const GCCRegNames[]; 5115 5116 public: 5117 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5118 TLSSupported = true; 5119 IntWidth = IntAlign = 32; 5120 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5121 PointerWidth = PointerAlign = 64; 5122 LongDoubleWidth = 128; 5123 LongDoubleAlign = 64; 5124 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5125 MinGlobalAlign = 16; 5126 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5127 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5128 } 5129 void getTargetDefines(const LangOptions &Opts, 5130 MacroBuilder &Builder) const override { 5131 Builder.defineMacro("__s390__"); 5132 Builder.defineMacro("__s390x__"); 5133 Builder.defineMacro("__zarch__"); 5134 Builder.defineMacro("__LONG_DOUBLE_128__"); 5135 } 5136 void getTargetBuiltins(const Builtin::Info *&Records, 5137 unsigned &NumRecords) const override { 5138 // FIXME: Implement. 5139 Records = nullptr; 5140 NumRecords = 0; 5141 } 5142 5143 void getGCCRegNames(const char *const *&Names, 5144 unsigned &NumNames) const override; 5145 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5146 unsigned &NumAliases) const override { 5147 // No aliases. 5148 Aliases = nullptr; 5149 NumAliases = 0; 5150 } 5151 bool validateAsmConstraint(const char *&Name, 5152 TargetInfo::ConstraintInfo &info) const override; 5153 const char *getClobbers() const override { 5154 // FIXME: Is this really right? 5155 return ""; 5156 } 5157 BuiltinVaListKind getBuiltinVaListKind() const override { 5158 return TargetInfo::SystemZBuiltinVaList; 5159 } 5160 bool setCPU(const std::string &Name) override { 5161 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5162 .Case("z10", true) 5163 .Case("z196", true) 5164 .Case("zEC12", true) 5165 .Default(false); 5166 5167 // No need to store the CPU yet. There aren't any CPU-specific 5168 // macros to define. 5169 return CPUKnown; 5170 } 5171 }; 5172 5173 const char *const SystemZTargetInfo::GCCRegNames[] = { 5174 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5175 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5176 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 5177 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 5178 }; 5179 5180 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 5181 unsigned &NumNames) const { 5182 Names = GCCRegNames; 5183 NumNames = llvm::array_lengthof(GCCRegNames); 5184 } 5185 5186 bool SystemZTargetInfo:: 5187 validateAsmConstraint(const char *&Name, 5188 TargetInfo::ConstraintInfo &Info) const { 5189 switch (*Name) { 5190 default: 5191 return false; 5192 5193 case 'a': // Address register 5194 case 'd': // Data register (equivalent to 'r') 5195 case 'f': // Floating-point register 5196 Info.setAllowsRegister(); 5197 return true; 5198 5199 case 'I': // Unsigned 8-bit constant 5200 case 'J': // Unsigned 12-bit constant 5201 case 'K': // Signed 16-bit constant 5202 case 'L': // Signed 20-bit displacement (on all targets we support) 5203 case 'M': // 0x7fffffff 5204 return true; 5205 5206 case 'Q': // Memory with base and unsigned 12-bit displacement 5207 case 'R': // Likewise, plus an index 5208 case 'S': // Memory with base and signed 20-bit displacement 5209 case 'T': // Likewise, plus an index 5210 Info.setAllowsMemory(); 5211 return true; 5212 } 5213 } 5214 } 5215 5216 namespace { 5217 class MSP430TargetInfo : public TargetInfo { 5218 static const char * const GCCRegNames[]; 5219 public: 5220 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5221 BigEndian = false; 5222 TLSSupported = false; 5223 IntWidth = 16; IntAlign = 16; 5224 LongWidth = 32; LongLongWidth = 64; 5225 LongAlign = LongLongAlign = 16; 5226 PointerWidth = 16; PointerAlign = 16; 5227 SuitableAlign = 16; 5228 SizeType = UnsignedInt; 5229 IntMaxType = SignedLongLong; 5230 IntPtrType = SignedInt; 5231 PtrDiffType = SignedInt; 5232 SigAtomicType = SignedLong; 5233 DescriptionString = "e-m:e-p:16:16-i32:16:32-n8:16"; 5234 } 5235 void getTargetDefines(const LangOptions &Opts, 5236 MacroBuilder &Builder) const override { 5237 Builder.defineMacro("MSP430"); 5238 Builder.defineMacro("__MSP430__"); 5239 // FIXME: defines for different 'flavours' of MCU 5240 } 5241 void getTargetBuiltins(const Builtin::Info *&Records, 5242 unsigned &NumRecords) const override { 5243 // FIXME: Implement. 5244 Records = nullptr; 5245 NumRecords = 0; 5246 } 5247 bool hasFeature(StringRef Feature) const override { 5248 return Feature == "msp430"; 5249 } 5250 void getGCCRegNames(const char * const *&Names, 5251 unsigned &NumNames) const override; 5252 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5253 unsigned &NumAliases) const override { 5254 // No aliases. 5255 Aliases = nullptr; 5256 NumAliases = 0; 5257 } 5258 bool validateAsmConstraint(const char *&Name, 5259 TargetInfo::ConstraintInfo &info) const override { 5260 // No target constraints for now. 5261 return false; 5262 } 5263 const char *getClobbers() const override { 5264 // FIXME: Is this really right? 5265 return ""; 5266 } 5267 BuiltinVaListKind getBuiltinVaListKind() const override { 5268 // FIXME: implement 5269 return TargetInfo::CharPtrBuiltinVaList; 5270 } 5271 }; 5272 5273 const char * const MSP430TargetInfo::GCCRegNames[] = { 5274 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5275 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 5276 }; 5277 5278 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 5279 unsigned &NumNames) const { 5280 Names = GCCRegNames; 5281 NumNames = llvm::array_lengthof(GCCRegNames); 5282 } 5283 } 5284 5285 namespace { 5286 5287 // LLVM and Clang cannot be used directly to output native binaries for 5288 // target, but is used to compile C code to llvm bitcode with correct 5289 // type and alignment information. 5290 // 5291 // TCE uses the llvm bitcode as input and uses it for generating customized 5292 // target processor and program binary. TCE co-design environment is 5293 // publicly available in http://tce.cs.tut.fi 5294 5295 static const unsigned TCEOpenCLAddrSpaceMap[] = { 5296 3, // opencl_global 5297 4, // opencl_local 5298 5, // opencl_constant 5299 0, // cuda_device 5300 0, // cuda_constant 5301 0 // cuda_shared 5302 }; 5303 5304 class TCETargetInfo : public TargetInfo{ 5305 public: 5306 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5307 TLSSupported = false; 5308 IntWidth = 32; 5309 LongWidth = LongLongWidth = 32; 5310 PointerWidth = 32; 5311 IntAlign = 32; 5312 LongAlign = LongLongAlign = 32; 5313 PointerAlign = 32; 5314 SuitableAlign = 32; 5315 SizeType = UnsignedInt; 5316 IntMaxType = SignedLong; 5317 IntPtrType = SignedInt; 5318 PtrDiffType = SignedInt; 5319 FloatWidth = 32; 5320 FloatAlign = 32; 5321 DoubleWidth = 32; 5322 DoubleAlign = 32; 5323 LongDoubleWidth = 32; 5324 LongDoubleAlign = 32; 5325 FloatFormat = &llvm::APFloat::IEEEsingle; 5326 DoubleFormat = &llvm::APFloat::IEEEsingle; 5327 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 5328 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 5329 "-f64:32-v64:32-v128:32-a:0:32-n32"; 5330 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 5331 UseAddrSpaceMapMangling = true; 5332 } 5333 5334 void getTargetDefines(const LangOptions &Opts, 5335 MacroBuilder &Builder) const override { 5336 DefineStd(Builder, "tce", Opts); 5337 Builder.defineMacro("__TCE__"); 5338 Builder.defineMacro("__TCE_V1__"); 5339 } 5340 bool hasFeature(StringRef Feature) const override { 5341 return Feature == "tce"; 5342 } 5343 5344 void getTargetBuiltins(const Builtin::Info *&Records, 5345 unsigned &NumRecords) const override {} 5346 const char *getClobbers() const override { 5347 return ""; 5348 } 5349 BuiltinVaListKind getBuiltinVaListKind() const override { 5350 return TargetInfo::VoidPtrBuiltinVaList; 5351 } 5352 void getGCCRegNames(const char * const *&Names, 5353 unsigned &NumNames) const override {} 5354 bool validateAsmConstraint(const char *&Name, 5355 TargetInfo::ConstraintInfo &info) const override{ 5356 return true; 5357 } 5358 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5359 unsigned &NumAliases) const override {} 5360 }; 5361 } 5362 5363 namespace { 5364 class MipsTargetInfoBase : public TargetInfo { 5365 virtual void setDescriptionString() = 0; 5366 5367 static const Builtin::Info BuiltinInfo[]; 5368 std::string CPU; 5369 bool IsMips16; 5370 bool IsMicromips; 5371 bool IsNan2008; 5372 bool IsSingleFloat; 5373 enum MipsFloatABI { 5374 HardFloat, SoftFloat 5375 } FloatABI; 5376 enum DspRevEnum { 5377 NoDSP, DSP1, DSP2 5378 } DspRev; 5379 bool HasMSA; 5380 5381 protected: 5382 bool HasFP64; 5383 std::string ABI; 5384 5385 public: 5386 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 5387 const std::string &CPUStr) 5388 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 5389 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 5390 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {} 5391 5392 bool isNaN2008Default() const { 5393 return CPU == "mips32r6" || CPU == "mips64r6"; 5394 } 5395 5396 bool isFP64Default() const { 5397 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 5398 } 5399 5400 StringRef getABI() const override { return ABI; } 5401 bool setCPU(const std::string &Name) override { 5402 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 5403 getTriple().getArch() == llvm::Triple::mipsel; 5404 CPU = Name; 5405 return llvm::StringSwitch<bool>(Name) 5406 .Case("mips1", IsMips32) 5407 .Case("mips2", IsMips32) 5408 .Case("mips3", true) 5409 .Case("mips4", true) 5410 .Case("mips5", true) 5411 .Case("mips32", IsMips32) 5412 .Case("mips32r2", IsMips32) 5413 .Case("mips32r6", IsMips32) 5414 .Case("mips64", true) 5415 .Case("mips64r2", true) 5416 .Case("mips64r6", true) 5417 .Case("octeon", true) 5418 .Default(false); 5419 } 5420 const std::string& getCPU() const { return CPU; } 5421 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5422 // The backend enables certain ABI's by default according to the 5423 // architecture. 5424 // Disable both possible defaults so that we don't end up with multiple 5425 // ABI's selected and trigger an assertion. 5426 Features["o32"] = false; 5427 Features["n64"] = false; 5428 5429 Features[ABI] = true; 5430 if (CPU == "octeon") 5431 Features["mips64r2"] = Features["cnmips"] = true; 5432 else 5433 Features[CPU] = true; 5434 } 5435 5436 void getTargetDefines(const LangOptions &Opts, 5437 MacroBuilder &Builder) const override { 5438 Builder.defineMacro("__mips__"); 5439 Builder.defineMacro("_mips"); 5440 if (Opts.GNUMode) 5441 Builder.defineMacro("mips"); 5442 5443 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5444 5445 switch (FloatABI) { 5446 case HardFloat: 5447 Builder.defineMacro("__mips_hard_float", Twine(1)); 5448 break; 5449 case SoftFloat: 5450 Builder.defineMacro("__mips_soft_float", Twine(1)); 5451 break; 5452 } 5453 5454 if (IsSingleFloat) 5455 Builder.defineMacro("__mips_single_float", Twine(1)); 5456 5457 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 5458 Builder.defineMacro("_MIPS_FPSET", 5459 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 5460 5461 if (IsMips16) 5462 Builder.defineMacro("__mips16", Twine(1)); 5463 5464 if (IsMicromips) 5465 Builder.defineMacro("__mips_micromips", Twine(1)); 5466 5467 if (IsNan2008) 5468 Builder.defineMacro("__mips_nan2008", Twine(1)); 5469 5470 switch (DspRev) { 5471 default: 5472 break; 5473 case DSP1: 5474 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 5475 Builder.defineMacro("__mips_dsp", Twine(1)); 5476 break; 5477 case DSP2: 5478 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 5479 Builder.defineMacro("__mips_dspr2", Twine(1)); 5480 Builder.defineMacro("__mips_dsp", Twine(1)); 5481 break; 5482 } 5483 5484 if (HasMSA) 5485 Builder.defineMacro("__mips_msa", Twine(1)); 5486 5487 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 5488 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 5489 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 5490 5491 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 5492 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 5493 } 5494 5495 void getTargetBuiltins(const Builtin::Info *&Records, 5496 unsigned &NumRecords) const override { 5497 Records = BuiltinInfo; 5498 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 5499 } 5500 bool hasFeature(StringRef Feature) const override { 5501 return llvm::StringSwitch<bool>(Feature) 5502 .Case("mips", true) 5503 .Case("fp64", HasFP64) 5504 .Default(false); 5505 } 5506 BuiltinVaListKind getBuiltinVaListKind() const override { 5507 return TargetInfo::VoidPtrBuiltinVaList; 5508 } 5509 void getGCCRegNames(const char * const *&Names, 5510 unsigned &NumNames) const override { 5511 static const char *const GCCRegNames[] = { 5512 // CPU register names 5513 // Must match second column of GCCRegAliases 5514 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 5515 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 5516 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 5517 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 5518 // Floating point register names 5519 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 5520 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 5521 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 5522 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 5523 // Hi/lo and condition register names 5524 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 5525 "$fcc5","$fcc6","$fcc7", 5526 // MSA register names 5527 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 5528 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 5529 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 5530 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 5531 // MSA control register names 5532 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 5533 "$msarequest", "$msamap", "$msaunmap" 5534 }; 5535 Names = GCCRegNames; 5536 NumNames = llvm::array_lengthof(GCCRegNames); 5537 } 5538 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5539 unsigned &NumAliases) const override = 0; 5540 bool validateAsmConstraint(const char *&Name, 5541 TargetInfo::ConstraintInfo &Info) const override { 5542 switch (*Name) { 5543 default: 5544 return false; 5545 5546 case 'r': // CPU registers. 5547 case 'd': // Equivalent to "r" unless generating MIPS16 code. 5548 case 'y': // Equivalent to "r", backward compatibility only. 5549 case 'f': // floating-point registers. 5550 case 'c': // $25 for indirect jumps 5551 case 'l': // lo register 5552 case 'x': // hilo register pair 5553 Info.setAllowsRegister(); 5554 return true; 5555 case 'R': // An address that can be used in a non-macro load or store 5556 Info.setAllowsMemory(); 5557 return true; 5558 } 5559 } 5560 5561 const char *getClobbers() const override { 5562 // FIXME: Implement! 5563 return ""; 5564 } 5565 5566 bool handleTargetFeatures(std::vector<std::string> &Features, 5567 DiagnosticsEngine &Diags) override { 5568 IsMips16 = false; 5569 IsMicromips = false; 5570 IsNan2008 = isNaN2008Default(); 5571 IsSingleFloat = false; 5572 FloatABI = HardFloat; 5573 DspRev = NoDSP; 5574 HasFP64 = isFP64Default(); 5575 5576 for (std::vector<std::string>::iterator it = Features.begin(), 5577 ie = Features.end(); it != ie; ++it) { 5578 if (*it == "+single-float") 5579 IsSingleFloat = true; 5580 else if (*it == "+soft-float") 5581 FloatABI = SoftFloat; 5582 else if (*it == "+mips16") 5583 IsMips16 = true; 5584 else if (*it == "+micromips") 5585 IsMicromips = true; 5586 else if (*it == "+dsp") 5587 DspRev = std::max(DspRev, DSP1); 5588 else if (*it == "+dspr2") 5589 DspRev = std::max(DspRev, DSP2); 5590 else if (*it == "+msa") 5591 HasMSA = true; 5592 else if (*it == "+fp64") 5593 HasFP64 = true; 5594 else if (*it == "-fp64") 5595 HasFP64 = false; 5596 else if (*it == "+nan2008") 5597 IsNan2008 = true; 5598 else if (*it == "-nan2008") 5599 IsNan2008 = false; 5600 } 5601 5602 // Remove front-end specific options. 5603 std::vector<std::string>::iterator it = 5604 std::find(Features.begin(), Features.end(), "+soft-float"); 5605 if (it != Features.end()) 5606 Features.erase(it); 5607 5608 setDescriptionString(); 5609 5610 return true; 5611 } 5612 5613 int getEHDataRegisterNumber(unsigned RegNo) const override { 5614 if (RegNo == 0) return 4; 5615 if (RegNo == 1) return 5; 5616 return -1; 5617 } 5618 5619 bool isCLZForZeroUndef() const override { return false; } 5620 }; 5621 5622 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 5623 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5624 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5625 ALL_LANGUAGES }, 5626 #include "clang/Basic/BuiltinsMips.def" 5627 }; 5628 5629 class Mips32TargetInfoBase : public MipsTargetInfoBase { 5630 public: 5631 Mips32TargetInfoBase(const llvm::Triple &Triple) 5632 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 5633 SizeType = UnsignedInt; 5634 PtrDiffType = SignedInt; 5635 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 5636 } 5637 bool setABI(const std::string &Name) override { 5638 if (Name == "o32" || Name == "eabi") { 5639 ABI = Name; 5640 return true; 5641 } 5642 return false; 5643 } 5644 void getTargetDefines(const LangOptions &Opts, 5645 MacroBuilder &Builder) const override { 5646 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5647 5648 Builder.defineMacro("__mips", "32"); 5649 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 5650 5651 const std::string& CPUStr = getCPU(); 5652 if (CPUStr == "mips32") 5653 Builder.defineMacro("__mips_isa_rev", "1"); 5654 else if (CPUStr == "mips32r2") 5655 Builder.defineMacro("__mips_isa_rev", "2"); 5656 5657 if (ABI == "o32") { 5658 Builder.defineMacro("__mips_o32"); 5659 Builder.defineMacro("_ABIO32", "1"); 5660 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 5661 } 5662 else if (ABI == "eabi") 5663 Builder.defineMacro("__mips_eabi"); 5664 else 5665 llvm_unreachable("Invalid ABI for Mips32."); 5666 } 5667 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5668 unsigned &NumAliases) const override { 5669 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5670 { { "at" }, "$1" }, 5671 { { "v0" }, "$2" }, 5672 { { "v1" }, "$3" }, 5673 { { "a0" }, "$4" }, 5674 { { "a1" }, "$5" }, 5675 { { "a2" }, "$6" }, 5676 { { "a3" }, "$7" }, 5677 { { "t0" }, "$8" }, 5678 { { "t1" }, "$9" }, 5679 { { "t2" }, "$10" }, 5680 { { "t3" }, "$11" }, 5681 { { "t4" }, "$12" }, 5682 { { "t5" }, "$13" }, 5683 { { "t6" }, "$14" }, 5684 { { "t7" }, "$15" }, 5685 { { "s0" }, "$16" }, 5686 { { "s1" }, "$17" }, 5687 { { "s2" }, "$18" }, 5688 { { "s3" }, "$19" }, 5689 { { "s4" }, "$20" }, 5690 { { "s5" }, "$21" }, 5691 { { "s6" }, "$22" }, 5692 { { "s7" }, "$23" }, 5693 { { "t8" }, "$24" }, 5694 { { "t9" }, "$25" }, 5695 { { "k0" }, "$26" }, 5696 { { "k1" }, "$27" }, 5697 { { "gp" }, "$28" }, 5698 { { "sp","$sp" }, "$29" }, 5699 { { "fp","$fp" }, "$30" }, 5700 { { "ra" }, "$31" } 5701 }; 5702 Aliases = GCCRegAliases; 5703 NumAliases = llvm::array_lengthof(GCCRegAliases); 5704 } 5705 }; 5706 5707 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 5708 void setDescriptionString() override { 5709 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5710 } 5711 5712 public: 5713 Mips32EBTargetInfo(const llvm::Triple &Triple) 5714 : Mips32TargetInfoBase(Triple) { 5715 } 5716 void getTargetDefines(const LangOptions &Opts, 5717 MacroBuilder &Builder) const override { 5718 DefineStd(Builder, "MIPSEB", Opts); 5719 Builder.defineMacro("_MIPSEB"); 5720 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5721 } 5722 }; 5723 5724 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 5725 void setDescriptionString() override { 5726 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5727 } 5728 5729 public: 5730 Mips32ELTargetInfo(const llvm::Triple &Triple) 5731 : Mips32TargetInfoBase(Triple) { 5732 BigEndian = false; 5733 } 5734 void getTargetDefines(const LangOptions &Opts, 5735 MacroBuilder &Builder) const override { 5736 DefineStd(Builder, "MIPSEL", Opts); 5737 Builder.defineMacro("_MIPSEL"); 5738 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5739 } 5740 }; 5741 5742 class Mips64TargetInfoBase : public MipsTargetInfoBase { 5743 public: 5744 Mips64TargetInfoBase(const llvm::Triple &Triple) 5745 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 5746 LongDoubleWidth = LongDoubleAlign = 128; 5747 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5748 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 5749 LongDoubleWidth = LongDoubleAlign = 64; 5750 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5751 } 5752 setN64ABITypes(); 5753 SuitableAlign = 128; 5754 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5755 } 5756 5757 void setN64ABITypes() { 5758 LongWidth = LongAlign = 64; 5759 PointerWidth = PointerAlign = 64; 5760 SizeType = UnsignedLong; 5761 PtrDiffType = SignedLong; 5762 } 5763 5764 void setN32ABITypes() { 5765 LongWidth = LongAlign = 32; 5766 PointerWidth = PointerAlign = 32; 5767 SizeType = UnsignedInt; 5768 PtrDiffType = SignedInt; 5769 } 5770 5771 bool setABI(const std::string &Name) override { 5772 if (Name == "n32") { 5773 setN32ABITypes(); 5774 ABI = Name; 5775 return true; 5776 } 5777 if (Name == "n64") { 5778 setN64ABITypes(); 5779 ABI = Name; 5780 return true; 5781 } 5782 return false; 5783 } 5784 5785 void getTargetDefines(const LangOptions &Opts, 5786 MacroBuilder &Builder) const override { 5787 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5788 5789 Builder.defineMacro("__mips", "64"); 5790 Builder.defineMacro("__mips64"); 5791 Builder.defineMacro("__mips64__"); 5792 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 5793 5794 const std::string& CPUStr = getCPU(); 5795 if (CPUStr == "mips64") 5796 Builder.defineMacro("__mips_isa_rev", "1"); 5797 else if (CPUStr == "mips64r2") 5798 Builder.defineMacro("__mips_isa_rev", "2"); 5799 5800 if (ABI == "n32") { 5801 Builder.defineMacro("__mips_n32"); 5802 Builder.defineMacro("_ABIN32", "2"); 5803 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 5804 } 5805 else if (ABI == "n64") { 5806 Builder.defineMacro("__mips_n64"); 5807 Builder.defineMacro("_ABI64", "3"); 5808 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 5809 } 5810 else 5811 llvm_unreachable("Invalid ABI for Mips64."); 5812 } 5813 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5814 unsigned &NumAliases) const override { 5815 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5816 { { "at" }, "$1" }, 5817 { { "v0" }, "$2" }, 5818 { { "v1" }, "$3" }, 5819 { { "a0" }, "$4" }, 5820 { { "a1" }, "$5" }, 5821 { { "a2" }, "$6" }, 5822 { { "a3" }, "$7" }, 5823 { { "a4" }, "$8" }, 5824 { { "a5" }, "$9" }, 5825 { { "a6" }, "$10" }, 5826 { { "a7" }, "$11" }, 5827 { { "t0" }, "$12" }, 5828 { { "t1" }, "$13" }, 5829 { { "t2" }, "$14" }, 5830 { { "t3" }, "$15" }, 5831 { { "s0" }, "$16" }, 5832 { { "s1" }, "$17" }, 5833 { { "s2" }, "$18" }, 5834 { { "s3" }, "$19" }, 5835 { { "s4" }, "$20" }, 5836 { { "s5" }, "$21" }, 5837 { { "s6" }, "$22" }, 5838 { { "s7" }, "$23" }, 5839 { { "t8" }, "$24" }, 5840 { { "t9" }, "$25" }, 5841 { { "k0" }, "$26" }, 5842 { { "k1" }, "$27" }, 5843 { { "gp" }, "$28" }, 5844 { { "sp","$sp" }, "$29" }, 5845 { { "fp","$fp" }, "$30" }, 5846 { { "ra" }, "$31" } 5847 }; 5848 Aliases = GCCRegAliases; 5849 NumAliases = llvm::array_lengthof(GCCRegAliases); 5850 } 5851 5852 bool hasInt128Type() const override { return true; } 5853 }; 5854 5855 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 5856 void setDescriptionString() override { 5857 if (ABI == "n32") 5858 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5859 else 5860 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5861 5862 } 5863 5864 public: 5865 Mips64EBTargetInfo(const llvm::Triple &Triple) 5866 : Mips64TargetInfoBase(Triple) {} 5867 void getTargetDefines(const LangOptions &Opts, 5868 MacroBuilder &Builder) const override { 5869 DefineStd(Builder, "MIPSEB", Opts); 5870 Builder.defineMacro("_MIPSEB"); 5871 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5872 } 5873 }; 5874 5875 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 5876 void setDescriptionString() override { 5877 if (ABI == "n32") 5878 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5879 else 5880 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5881 } 5882 public: 5883 Mips64ELTargetInfo(const llvm::Triple &Triple) 5884 : Mips64TargetInfoBase(Triple) { 5885 // Default ABI is n64. 5886 BigEndian = false; 5887 } 5888 void getTargetDefines(const LangOptions &Opts, 5889 MacroBuilder &Builder) const override { 5890 DefineStd(Builder, "MIPSEL", Opts); 5891 Builder.defineMacro("_MIPSEL"); 5892 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5893 } 5894 }; 5895 } // end anonymous namespace. 5896 5897 namespace { 5898 class PNaClTargetInfo : public TargetInfo { 5899 public: 5900 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5901 BigEndian = false; 5902 this->UserLabelPrefix = ""; 5903 this->LongAlign = 32; 5904 this->LongWidth = 32; 5905 this->PointerAlign = 32; 5906 this->PointerWidth = 32; 5907 this->IntMaxType = TargetInfo::SignedLongLong; 5908 this->Int64Type = TargetInfo::SignedLongLong; 5909 this->DoubleAlign = 64; 5910 this->LongDoubleWidth = 64; 5911 this->LongDoubleAlign = 64; 5912 this->SizeType = TargetInfo::UnsignedInt; 5913 this->PtrDiffType = TargetInfo::SignedInt; 5914 this->IntPtrType = TargetInfo::SignedInt; 5915 this->RegParmMax = 0; // Disallow regparm 5916 } 5917 5918 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5919 } 5920 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 5921 Builder.defineMacro("__le32__"); 5922 Builder.defineMacro("__pnacl__"); 5923 } 5924 void getTargetDefines(const LangOptions &Opts, 5925 MacroBuilder &Builder) const override { 5926 getArchDefines(Opts, Builder); 5927 } 5928 bool hasFeature(StringRef Feature) const override { 5929 return Feature == "pnacl"; 5930 } 5931 void getTargetBuiltins(const Builtin::Info *&Records, 5932 unsigned &NumRecords) const override { 5933 } 5934 BuiltinVaListKind getBuiltinVaListKind() const override { 5935 return TargetInfo::PNaClABIBuiltinVaList; 5936 } 5937 void getGCCRegNames(const char * const *&Names, 5938 unsigned &NumNames) const override; 5939 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5940 unsigned &NumAliases) const override; 5941 bool validateAsmConstraint(const char *&Name, 5942 TargetInfo::ConstraintInfo &Info) const override { 5943 return false; 5944 } 5945 5946 const char *getClobbers() const override { 5947 return ""; 5948 } 5949 }; 5950 5951 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 5952 unsigned &NumNames) const { 5953 Names = nullptr; 5954 NumNames = 0; 5955 } 5956 5957 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5958 unsigned &NumAliases) const { 5959 Aliases = nullptr; 5960 NumAliases = 0; 5961 } 5962 } // end anonymous namespace. 5963 5964 namespace { 5965 static const unsigned SPIRAddrSpaceMap[] = { 5966 1, // opencl_global 5967 3, // opencl_local 5968 2, // opencl_constant 5969 0, // cuda_device 5970 0, // cuda_constant 5971 0 // cuda_shared 5972 }; 5973 class SPIRTargetInfo : public TargetInfo { 5974 public: 5975 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5976 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 5977 "SPIR target must use unknown OS"); 5978 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 5979 "SPIR target must use unknown environment type"); 5980 BigEndian = false; 5981 TLSSupported = false; 5982 LongWidth = LongAlign = 64; 5983 AddrSpaceMap = &SPIRAddrSpaceMap; 5984 UseAddrSpaceMapMangling = true; 5985 // Define available target features 5986 // These must be defined in sorted order! 5987 NoAsmVariants = true; 5988 } 5989 void getTargetDefines(const LangOptions &Opts, 5990 MacroBuilder &Builder) const override { 5991 DefineStd(Builder, "SPIR", Opts); 5992 } 5993 bool hasFeature(StringRef Feature) const override { 5994 return Feature == "spir"; 5995 } 5996 5997 void getTargetBuiltins(const Builtin::Info *&Records, 5998 unsigned &NumRecords) const override {} 5999 const char *getClobbers() const override { 6000 return ""; 6001 } 6002 void getGCCRegNames(const char * const *&Names, 6003 unsigned &NumNames) const override {} 6004 bool validateAsmConstraint(const char *&Name, 6005 TargetInfo::ConstraintInfo &info) const override { 6006 return true; 6007 } 6008 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6009 unsigned &NumAliases) const override {} 6010 BuiltinVaListKind getBuiltinVaListKind() const override { 6011 return TargetInfo::VoidPtrBuiltinVaList; 6012 } 6013 }; 6014 6015 6016 class SPIR32TargetInfo : public SPIRTargetInfo { 6017 public: 6018 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6019 PointerWidth = PointerAlign = 32; 6020 SizeType = TargetInfo::UnsignedInt; 6021 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 6022 DescriptionString 6023 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 6024 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6025 } 6026 void getTargetDefines(const LangOptions &Opts, 6027 MacroBuilder &Builder) const override { 6028 DefineStd(Builder, "SPIR32", Opts); 6029 } 6030 }; 6031 6032 class SPIR64TargetInfo : public SPIRTargetInfo { 6033 public: 6034 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6035 PointerWidth = PointerAlign = 64; 6036 SizeType = TargetInfo::UnsignedLong; 6037 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 6038 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 6039 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6040 } 6041 void getTargetDefines(const LangOptions &Opts, 6042 MacroBuilder &Builder) const override { 6043 DefineStd(Builder, "SPIR64", Opts); 6044 } 6045 }; 6046 } 6047 6048 namespace { 6049 class XCoreTargetInfo : public TargetInfo { 6050 static const Builtin::Info BuiltinInfo[]; 6051 public: 6052 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6053 BigEndian = false; 6054 NoAsmVariants = true; 6055 LongLongAlign = 32; 6056 SuitableAlign = 32; 6057 DoubleAlign = LongDoubleAlign = 32; 6058 SizeType = UnsignedInt; 6059 PtrDiffType = SignedInt; 6060 IntPtrType = SignedInt; 6061 WCharType = UnsignedChar; 6062 WIntType = UnsignedInt; 6063 UseZeroLengthBitfieldAlignment = true; 6064 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 6065 "-f64:32-a:0:32-n32"; 6066 } 6067 void getTargetDefines(const LangOptions &Opts, 6068 MacroBuilder &Builder) const override { 6069 Builder.defineMacro("__XS1B__"); 6070 } 6071 void getTargetBuiltins(const Builtin::Info *&Records, 6072 unsigned &NumRecords) const override { 6073 Records = BuiltinInfo; 6074 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 6075 } 6076 BuiltinVaListKind getBuiltinVaListKind() const override { 6077 return TargetInfo::VoidPtrBuiltinVaList; 6078 } 6079 const char *getClobbers() const override { 6080 return ""; 6081 } 6082 void getGCCRegNames(const char * const *&Names, 6083 unsigned &NumNames) const override { 6084 static const char * const GCCRegNames[] = { 6085 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6086 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 6087 }; 6088 Names = GCCRegNames; 6089 NumNames = llvm::array_lengthof(GCCRegNames); 6090 } 6091 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6092 unsigned &NumAliases) const override { 6093 Aliases = nullptr; 6094 NumAliases = 0; 6095 } 6096 bool validateAsmConstraint(const char *&Name, 6097 TargetInfo::ConstraintInfo &Info) const override { 6098 return false; 6099 } 6100 int getEHDataRegisterNumber(unsigned RegNo) const override { 6101 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 6102 return (RegNo < 2)? RegNo : -1; 6103 } 6104 }; 6105 6106 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 6107 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6108 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 6109 ALL_LANGUAGES }, 6110 #include "clang/Basic/BuiltinsXCore.def" 6111 }; 6112 } // end anonymous namespace. 6113 6114 6115 //===----------------------------------------------------------------------===// 6116 // Driver code 6117 //===----------------------------------------------------------------------===// 6118 6119 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 6120 llvm::Triple::OSType os = Triple.getOS(); 6121 6122 switch (Triple.getArch()) { 6123 default: 6124 return nullptr; 6125 6126 case llvm::Triple::xcore: 6127 return new XCoreTargetInfo(Triple); 6128 6129 case llvm::Triple::hexagon: 6130 return new HexagonTargetInfo(Triple); 6131 6132 case llvm::Triple::aarch64: 6133 if (Triple.isOSDarwin()) 6134 return new DarwinAArch64TargetInfo(Triple); 6135 6136 switch (os) { 6137 case llvm::Triple::Linux: 6138 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 6139 case llvm::Triple::NetBSD: 6140 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 6141 default: 6142 return new AArch64leTargetInfo(Triple); 6143 } 6144 6145 case llvm::Triple::aarch64_be: 6146 switch (os) { 6147 case llvm::Triple::Linux: 6148 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 6149 case llvm::Triple::NetBSD: 6150 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 6151 default: 6152 return new AArch64beTargetInfo(Triple); 6153 } 6154 6155 case llvm::Triple::arm: 6156 case llvm::Triple::thumb: 6157 if (Triple.isOSBinFormatMachO()) 6158 return new DarwinARMTargetInfo(Triple); 6159 6160 switch (os) { 6161 case llvm::Triple::Linux: 6162 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 6163 case llvm::Triple::FreeBSD: 6164 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 6165 case llvm::Triple::NetBSD: 6166 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 6167 case llvm::Triple::OpenBSD: 6168 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 6169 case llvm::Triple::Bitrig: 6170 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 6171 case llvm::Triple::RTEMS: 6172 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 6173 case llvm::Triple::NaCl: 6174 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 6175 case llvm::Triple::Win32: 6176 switch (Triple.getEnvironment()) { 6177 default: 6178 return new ARMleTargetInfo(Triple); 6179 case llvm::Triple::Itanium: 6180 return new ItaniumWindowsARMleTargetInfo(Triple); 6181 case llvm::Triple::MSVC: 6182 return new MicrosoftARMleTargetInfo(Triple); 6183 } 6184 default: 6185 return new ARMleTargetInfo(Triple); 6186 } 6187 6188 case llvm::Triple::armeb: 6189 case llvm::Triple::thumbeb: 6190 if (Triple.isOSDarwin()) 6191 return new DarwinARMTargetInfo(Triple); 6192 6193 switch (os) { 6194 case llvm::Triple::Linux: 6195 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 6196 case llvm::Triple::FreeBSD: 6197 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 6198 case llvm::Triple::NetBSD: 6199 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 6200 case llvm::Triple::OpenBSD: 6201 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 6202 case llvm::Triple::Bitrig: 6203 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 6204 case llvm::Triple::RTEMS: 6205 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 6206 case llvm::Triple::NaCl: 6207 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 6208 default: 6209 return new ARMbeTargetInfo(Triple); 6210 } 6211 6212 case llvm::Triple::msp430: 6213 return new MSP430TargetInfo(Triple); 6214 6215 case llvm::Triple::mips: 6216 switch (os) { 6217 case llvm::Triple::Linux: 6218 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 6219 case llvm::Triple::RTEMS: 6220 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 6221 case llvm::Triple::FreeBSD: 6222 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6223 case llvm::Triple::NetBSD: 6224 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6225 default: 6226 return new Mips32EBTargetInfo(Triple); 6227 } 6228 6229 case llvm::Triple::mipsel: 6230 switch (os) { 6231 case llvm::Triple::Linux: 6232 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 6233 case llvm::Triple::RTEMS: 6234 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 6235 case llvm::Triple::FreeBSD: 6236 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6237 case llvm::Triple::NetBSD: 6238 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6239 case llvm::Triple::NaCl: 6240 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 6241 default: 6242 return new Mips32ELTargetInfo(Triple); 6243 } 6244 6245 case llvm::Triple::mips64: 6246 switch (os) { 6247 case llvm::Triple::Linux: 6248 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 6249 case llvm::Triple::RTEMS: 6250 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 6251 case llvm::Triple::FreeBSD: 6252 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6253 case llvm::Triple::NetBSD: 6254 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6255 case llvm::Triple::OpenBSD: 6256 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6257 default: 6258 return new Mips64EBTargetInfo(Triple); 6259 } 6260 6261 case llvm::Triple::mips64el: 6262 switch (os) { 6263 case llvm::Triple::Linux: 6264 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 6265 case llvm::Triple::RTEMS: 6266 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 6267 case llvm::Triple::FreeBSD: 6268 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6269 case llvm::Triple::NetBSD: 6270 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6271 case llvm::Triple::OpenBSD: 6272 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6273 default: 6274 return new Mips64ELTargetInfo(Triple); 6275 } 6276 6277 case llvm::Triple::le32: 6278 switch (os) { 6279 case llvm::Triple::NaCl: 6280 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 6281 default: 6282 return nullptr; 6283 } 6284 6285 case llvm::Triple::ppc: 6286 if (Triple.isOSDarwin()) 6287 return new DarwinPPC32TargetInfo(Triple); 6288 switch (os) { 6289 case llvm::Triple::Linux: 6290 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 6291 case llvm::Triple::FreeBSD: 6292 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 6293 case llvm::Triple::NetBSD: 6294 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 6295 case llvm::Triple::OpenBSD: 6296 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 6297 case llvm::Triple::RTEMS: 6298 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 6299 default: 6300 return new PPC32TargetInfo(Triple); 6301 } 6302 6303 case llvm::Triple::ppc64: 6304 if (Triple.isOSDarwin()) 6305 return new DarwinPPC64TargetInfo(Triple); 6306 switch (os) { 6307 case llvm::Triple::Linux: 6308 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6309 case llvm::Triple::Lv2: 6310 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 6311 case llvm::Triple::FreeBSD: 6312 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 6313 case llvm::Triple::NetBSD: 6314 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 6315 default: 6316 return new PPC64TargetInfo(Triple); 6317 } 6318 6319 case llvm::Triple::ppc64le: 6320 switch (os) { 6321 case llvm::Triple::Linux: 6322 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6323 default: 6324 return new PPC64TargetInfo(Triple); 6325 } 6326 6327 case llvm::Triple::nvptx: 6328 return new NVPTX32TargetInfo(Triple); 6329 case llvm::Triple::nvptx64: 6330 return new NVPTX64TargetInfo(Triple); 6331 6332 case llvm::Triple::r600: 6333 return new R600TargetInfo(Triple); 6334 6335 case llvm::Triple::sparc: 6336 switch (os) { 6337 case llvm::Triple::Linux: 6338 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 6339 case llvm::Triple::Solaris: 6340 return new SolarisSparcV8TargetInfo(Triple); 6341 case llvm::Triple::NetBSD: 6342 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 6343 case llvm::Triple::OpenBSD: 6344 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 6345 case llvm::Triple::RTEMS: 6346 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 6347 default: 6348 return new SparcV8TargetInfo(Triple); 6349 } 6350 6351 case llvm::Triple::sparcv9: 6352 switch (os) { 6353 case llvm::Triple::Linux: 6354 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 6355 case llvm::Triple::Solaris: 6356 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 6357 case llvm::Triple::NetBSD: 6358 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 6359 case llvm::Triple::OpenBSD: 6360 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 6361 case llvm::Triple::FreeBSD: 6362 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 6363 default: 6364 return new SparcV9TargetInfo(Triple); 6365 } 6366 6367 case llvm::Triple::systemz: 6368 switch (os) { 6369 case llvm::Triple::Linux: 6370 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 6371 default: 6372 return new SystemZTargetInfo(Triple); 6373 } 6374 6375 case llvm::Triple::tce: 6376 return new TCETargetInfo(Triple); 6377 6378 case llvm::Triple::x86: 6379 if (Triple.isOSDarwin()) 6380 return new DarwinI386TargetInfo(Triple); 6381 6382 switch (os) { 6383 case llvm::Triple::Linux: 6384 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 6385 case llvm::Triple::DragonFly: 6386 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 6387 case llvm::Triple::NetBSD: 6388 return new NetBSDI386TargetInfo(Triple); 6389 case llvm::Triple::OpenBSD: 6390 return new OpenBSDI386TargetInfo(Triple); 6391 case llvm::Triple::Bitrig: 6392 return new BitrigI386TargetInfo(Triple); 6393 case llvm::Triple::FreeBSD: 6394 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 6395 case llvm::Triple::KFreeBSD: 6396 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 6397 case llvm::Triple::Minix: 6398 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 6399 case llvm::Triple::Solaris: 6400 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 6401 case llvm::Triple::Win32: { 6402 switch (Triple.getEnvironment()) { 6403 default: 6404 return new X86_32TargetInfo(Triple); 6405 case llvm::Triple::Cygnus: 6406 return new CygwinX86_32TargetInfo(Triple); 6407 case llvm::Triple::GNU: 6408 return new MinGWX86_32TargetInfo(Triple); 6409 case llvm::Triple::Itanium: 6410 case llvm::Triple::MSVC: 6411 return new MicrosoftX86_32TargetInfo(Triple); 6412 } 6413 } 6414 case llvm::Triple::Haiku: 6415 return new HaikuX86_32TargetInfo(Triple); 6416 case llvm::Triple::RTEMS: 6417 return new RTEMSX86_32TargetInfo(Triple); 6418 case llvm::Triple::NaCl: 6419 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 6420 default: 6421 return new X86_32TargetInfo(Triple); 6422 } 6423 6424 case llvm::Triple::x86_64: 6425 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 6426 return new DarwinX86_64TargetInfo(Triple); 6427 6428 switch (os) { 6429 case llvm::Triple::Linux: 6430 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 6431 case llvm::Triple::DragonFly: 6432 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 6433 case llvm::Triple::NetBSD: 6434 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 6435 case llvm::Triple::OpenBSD: 6436 return new OpenBSDX86_64TargetInfo(Triple); 6437 case llvm::Triple::Bitrig: 6438 return new BitrigX86_64TargetInfo(Triple); 6439 case llvm::Triple::FreeBSD: 6440 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 6441 case llvm::Triple::KFreeBSD: 6442 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 6443 case llvm::Triple::Solaris: 6444 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 6445 case llvm::Triple::Win32: { 6446 switch (Triple.getEnvironment()) { 6447 default: 6448 return new X86_64TargetInfo(Triple); 6449 case llvm::Triple::GNU: 6450 return new MinGWX86_64TargetInfo(Triple); 6451 case llvm::Triple::MSVC: 6452 return new MicrosoftX86_64TargetInfo(Triple); 6453 } 6454 } 6455 case llvm::Triple::NaCl: 6456 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 6457 default: 6458 return new X86_64TargetInfo(Triple); 6459 } 6460 6461 case llvm::Triple::spir: { 6462 if (Triple.getOS() != llvm::Triple::UnknownOS || 6463 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 6464 return nullptr; 6465 return new SPIR32TargetInfo(Triple); 6466 } 6467 case llvm::Triple::spir64: { 6468 if (Triple.getOS() != llvm::Triple::UnknownOS || 6469 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 6470 return nullptr; 6471 return new SPIR64TargetInfo(Triple); 6472 } 6473 } 6474 } 6475 6476 /// CreateTargetInfo - Return the target info object for the specified target 6477 /// triple. 6478 TargetInfo * 6479 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 6480 const std::shared_ptr<TargetOptions> &Opts) { 6481 llvm::Triple Triple(Opts->Triple); 6482 6483 // Construct the target 6484 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 6485 if (!Target) { 6486 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 6487 return nullptr; 6488 } 6489 Target->TargetOpts = Opts; 6490 6491 // Set the target CPU if specified. 6492 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 6493 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 6494 return nullptr; 6495 } 6496 6497 // Set the target ABI if specified. 6498 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 6499 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 6500 return nullptr; 6501 } 6502 6503 // Set the fp math unit. 6504 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 6505 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 6506 return nullptr; 6507 } 6508 6509 // Compute the default target features, we need the target to handle this 6510 // because features may have dependencies on one another. 6511 llvm::StringMap<bool> Features; 6512 Target->getDefaultFeatures(Features); 6513 6514 // Apply the user specified deltas. 6515 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 6516 I < N; ++I) { 6517 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 6518 // Apply the feature via the target. 6519 bool Enabled = Name[0] == '+'; 6520 Target->setFeatureEnabled(Features, Name + 1, Enabled); 6521 } 6522 6523 // Add the features to the compile options. 6524 // 6525 // FIXME: If we are completely confident that we have the right set, we only 6526 // need to pass the minuses. 6527 Opts->Features.clear(); 6528 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 6529 ie = Features.end(); it != ie; ++it) 6530 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 6531 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 6532 return nullptr; 6533 6534 return Target.release(); 6535 } 6536