1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/IR/Type.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include <algorithm> 32 #include <memory> 33 using namespace clang; 34 35 //===----------------------------------------------------------------------===// 36 // Common code shared among targets. 37 //===----------------------------------------------------------------------===// 38 39 /// DefineStd - Define a macro name and standard variants. For example if 40 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 41 /// when in GNU mode. 42 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 43 const LangOptions &Opts) { 44 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 45 46 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 47 // in the user's namespace. 48 if (Opts.GNUMode) 49 Builder.defineMacro(MacroName); 50 51 // Define __unix. 52 Builder.defineMacro("__" + MacroName); 53 54 // Define __unix__. 55 Builder.defineMacro("__" + MacroName + "__"); 56 } 57 58 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 59 bool Tuning = true) { 60 Builder.defineMacro("__" + CPUName); 61 Builder.defineMacro("__" + CPUName + "__"); 62 if (Tuning) 63 Builder.defineMacro("__tune_" + CPUName + "__"); 64 } 65 66 //===----------------------------------------------------------------------===// 67 // Defines specific to certain operating systems. 68 //===----------------------------------------------------------------------===// 69 70 namespace { 71 template<typename TgtInfo> 72 class OSTargetInfo : public TgtInfo { 73 protected: 74 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 75 MacroBuilder &Builder) const=0; 76 public: 77 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 78 void getTargetDefines(const LangOptions &Opts, 79 MacroBuilder &Builder) const override { 80 TgtInfo::getTargetDefines(Opts, Builder); 81 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 82 } 83 84 }; 85 } // end anonymous namespace 86 87 88 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 89 const llvm::Triple &Triple, 90 StringRef &PlatformName, 91 VersionTuple &PlatformMinVersion) { 92 Builder.defineMacro("__APPLE_CC__", "6000"); 93 Builder.defineMacro("__APPLE__"); 94 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 95 // AddressSanitizer doesn't play well with source fortification, which is on 96 // by default on Darwin. 97 if (Opts.Sanitize.has(SanitizerKind::Address)) 98 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 99 100 if (!Opts.ObjCAutoRefCount) { 101 // __weak is always defined, for use in blocks and with objc pointers. 102 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 103 104 // Darwin defines __strong even in C mode (just to nothing). 105 if (Opts.getGC() != LangOptions::NonGC) 106 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 107 else 108 Builder.defineMacro("__strong", ""); 109 110 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 111 // allow this in C, since one might have block pointers in structs that 112 // are used in pure C code and in Objective-C ARC. 113 Builder.defineMacro("__unsafe_unretained", ""); 114 } 115 116 if (Opts.Static) 117 Builder.defineMacro("__STATIC__"); 118 else 119 Builder.defineMacro("__DYNAMIC__"); 120 121 if (Opts.POSIXThreads) 122 Builder.defineMacro("_REENTRANT"); 123 124 // Get the platform type and version number from the triple. 125 unsigned Maj, Min, Rev; 126 if (Triple.isMacOSX()) { 127 Triple.getMacOSXVersion(Maj, Min, Rev); 128 PlatformName = "macosx"; 129 } else { 130 Triple.getOSVersion(Maj, Min, Rev); 131 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 132 } 133 134 // If -target arch-pc-win32-macho option specified, we're 135 // generating code for Win32 ABI. No need to emit 136 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 137 if (PlatformName == "win32") { 138 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 139 return; 140 } 141 142 // Set the appropriate OS version define. 143 if (Triple.isiOS()) { 144 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 145 char Str[6]; 146 Str[0] = '0' + Maj; 147 Str[1] = '0' + (Min / 10); 148 Str[2] = '0' + (Min % 10); 149 Str[3] = '0' + (Rev / 10); 150 Str[4] = '0' + (Rev % 10); 151 Str[5] = '\0'; 152 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 153 Str); 154 } else if (Triple.isMacOSX()) { 155 // Note that the Driver allows versions which aren't representable in the 156 // define (because we only get a single digit for the minor and micro 157 // revision numbers). So, we limit them to the maximum representable 158 // version. 159 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 160 char Str[7]; 161 if (Maj < 10 || (Maj == 10 && Min < 10)) { 162 Str[0] = '0' + (Maj / 10); 163 Str[1] = '0' + (Maj % 10); 164 Str[2] = '0' + std::min(Min, 9U); 165 Str[3] = '0' + std::min(Rev, 9U); 166 Str[4] = '\0'; 167 } else { 168 // Handle versions > 10.9. 169 Str[0] = '0' + (Maj / 10); 170 Str[1] = '0' + (Maj % 10); 171 Str[2] = '0' + (Min / 10); 172 Str[3] = '0' + (Min % 10); 173 Str[4] = '0' + (Rev / 10); 174 Str[5] = '0' + (Rev % 10); 175 Str[6] = '\0'; 176 } 177 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 178 } 179 180 // Tell users about the kernel if there is one. 181 if (Triple.isOSDarwin()) 182 Builder.defineMacro("__MACH__"); 183 184 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 185 } 186 187 namespace { 188 template<typename Target> 189 class DarwinTargetInfo : public OSTargetInfo<Target> { 190 protected: 191 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 192 MacroBuilder &Builder) const override { 193 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 194 this->PlatformMinVersion); 195 } 196 197 public: 198 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 199 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 200 this->MCountName = "\01mcount"; 201 } 202 203 std::string isValidSectionSpecifier(StringRef SR) const override { 204 // Let MCSectionMachO validate this. 205 StringRef Segment, Section; 206 unsigned TAA, StubSize; 207 bool HasTAA; 208 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 209 TAA, HasTAA, StubSize); 210 } 211 212 const char *getStaticInitSectionSpecifier() const override { 213 // FIXME: We should return 0 when building kexts. 214 return "__TEXT,__StaticInit,regular,pure_instructions"; 215 } 216 217 /// Darwin does not support protected visibility. Darwin's "default" 218 /// is very similar to ELF's "protected"; Darwin requires a "weak" 219 /// attribute on declarations that can be dynamically replaced. 220 bool hasProtectedVisibility() const override { 221 return false; 222 } 223 }; 224 225 226 // DragonFlyBSD Target 227 template<typename Target> 228 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 229 protected: 230 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 231 MacroBuilder &Builder) const override { 232 // DragonFly defines; list based off of gcc output 233 Builder.defineMacro("__DragonFly__"); 234 Builder.defineMacro("__DragonFly_cc_version", "100001"); 235 Builder.defineMacro("__ELF__"); 236 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 237 Builder.defineMacro("__tune_i386__"); 238 DefineStd(Builder, "unix", Opts); 239 } 240 public: 241 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 242 : OSTargetInfo<Target>(Triple) { 243 this->UserLabelPrefix = ""; 244 245 switch (Triple.getArch()) { 246 default: 247 case llvm::Triple::x86: 248 case llvm::Triple::x86_64: 249 this->MCountName = ".mcount"; 250 break; 251 } 252 } 253 }; 254 255 // FreeBSD Target 256 template<typename Target> 257 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 258 protected: 259 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 260 MacroBuilder &Builder) const override { 261 // FreeBSD defines; list based off of gcc output 262 263 unsigned Release = Triple.getOSMajorVersion(); 264 if (Release == 0U) 265 Release = 8; 266 267 Builder.defineMacro("__FreeBSD__", Twine(Release)); 268 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 269 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 270 DefineStd(Builder, "unix", Opts); 271 Builder.defineMacro("__ELF__"); 272 273 // On FreeBSD, wchar_t contains the number of the code point as 274 // used by the character set of the locale. These character sets are 275 // not necessarily a superset of ASCII. 276 // 277 // FIXME: This is wrong; the macro refers to the numerical values 278 // of wchar_t *literals*, which are not locale-dependent. However, 279 // FreeBSD systems apparently depend on us getting this wrong, and 280 // setting this to 1 is conforming even if all the basic source 281 // character literals have the same encoding as char and wchar_t. 282 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 283 } 284 public: 285 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 286 this->UserLabelPrefix = ""; 287 288 switch (Triple.getArch()) { 289 default: 290 case llvm::Triple::x86: 291 case llvm::Triple::x86_64: 292 this->MCountName = ".mcount"; 293 break; 294 case llvm::Triple::mips: 295 case llvm::Triple::mipsel: 296 case llvm::Triple::ppc: 297 case llvm::Triple::ppc64: 298 case llvm::Triple::ppc64le: 299 this->MCountName = "_mcount"; 300 break; 301 case llvm::Triple::arm: 302 this->MCountName = "__mcount"; 303 break; 304 } 305 } 306 }; 307 308 // GNU/kFreeBSD Target 309 template<typename Target> 310 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 311 protected: 312 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 313 MacroBuilder &Builder) const override { 314 // GNU/kFreeBSD defines; list based off of gcc output 315 316 DefineStd(Builder, "unix", Opts); 317 Builder.defineMacro("__FreeBSD_kernel__"); 318 Builder.defineMacro("__GLIBC__"); 319 Builder.defineMacro("__ELF__"); 320 if (Opts.POSIXThreads) 321 Builder.defineMacro("_REENTRANT"); 322 if (Opts.CPlusPlus) 323 Builder.defineMacro("_GNU_SOURCE"); 324 } 325 public: 326 KFreeBSDTargetInfo(const llvm::Triple &Triple) 327 : OSTargetInfo<Target>(Triple) { 328 this->UserLabelPrefix = ""; 329 } 330 }; 331 332 // Minix Target 333 template<typename Target> 334 class MinixTargetInfo : public OSTargetInfo<Target> { 335 protected: 336 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 337 MacroBuilder &Builder) const override { 338 // Minix defines 339 340 Builder.defineMacro("__minix", "3"); 341 Builder.defineMacro("_EM_WSIZE", "4"); 342 Builder.defineMacro("_EM_PSIZE", "4"); 343 Builder.defineMacro("_EM_SSIZE", "2"); 344 Builder.defineMacro("_EM_LSIZE", "4"); 345 Builder.defineMacro("_EM_FSIZE", "4"); 346 Builder.defineMacro("_EM_DSIZE", "8"); 347 Builder.defineMacro("__ELF__"); 348 DefineStd(Builder, "unix", Opts); 349 } 350 public: 351 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 352 this->UserLabelPrefix = ""; 353 } 354 }; 355 356 // Linux target 357 template<typename Target> 358 class LinuxTargetInfo : public OSTargetInfo<Target> { 359 protected: 360 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 361 MacroBuilder &Builder) const override { 362 // Linux defines; list based off of gcc output 363 DefineStd(Builder, "unix", Opts); 364 DefineStd(Builder, "linux", Opts); 365 Builder.defineMacro("__gnu_linux__"); 366 Builder.defineMacro("__ELF__"); 367 if (Triple.getEnvironment() == llvm::Triple::Android) 368 Builder.defineMacro("__ANDROID__", "1"); 369 if (Opts.POSIXThreads) 370 Builder.defineMacro("_REENTRANT"); 371 if (Opts.CPlusPlus) 372 Builder.defineMacro("_GNU_SOURCE"); 373 } 374 public: 375 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 376 this->UserLabelPrefix = ""; 377 this->WIntType = TargetInfo::UnsignedInt; 378 379 switch (Triple.getArch()) { 380 default: 381 break; 382 case llvm::Triple::ppc: 383 case llvm::Triple::ppc64: 384 case llvm::Triple::ppc64le: 385 this->MCountName = "_mcount"; 386 break; 387 } 388 } 389 390 const char *getStaticInitSectionSpecifier() const override { 391 return ".text.startup"; 392 } 393 }; 394 395 // NetBSD Target 396 template<typename Target> 397 class NetBSDTargetInfo : public OSTargetInfo<Target> { 398 protected: 399 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 400 MacroBuilder &Builder) const override { 401 // NetBSD defines; list based off of gcc output 402 Builder.defineMacro("__NetBSD__"); 403 Builder.defineMacro("__unix__"); 404 Builder.defineMacro("__ELF__"); 405 if (Opts.POSIXThreads) 406 Builder.defineMacro("_POSIX_THREADS"); 407 408 switch (Triple.getArch()) { 409 default: 410 break; 411 case llvm::Triple::arm: 412 case llvm::Triple::armeb: 413 case llvm::Triple::thumb: 414 case llvm::Triple::thumbeb: 415 Builder.defineMacro("__ARM_DWARF_EH__"); 416 break; 417 } 418 } 419 public: 420 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 421 this->UserLabelPrefix = ""; 422 } 423 }; 424 425 // OpenBSD Target 426 template<typename Target> 427 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 428 protected: 429 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 430 MacroBuilder &Builder) const override { 431 // OpenBSD defines; list based off of gcc output 432 433 Builder.defineMacro("__OpenBSD__"); 434 DefineStd(Builder, "unix", Opts); 435 Builder.defineMacro("__ELF__"); 436 if (Opts.POSIXThreads) 437 Builder.defineMacro("_REENTRANT"); 438 } 439 public: 440 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 441 this->UserLabelPrefix = ""; 442 this->TLSSupported = false; 443 444 switch (Triple.getArch()) { 445 default: 446 case llvm::Triple::x86: 447 case llvm::Triple::x86_64: 448 case llvm::Triple::arm: 449 case llvm::Triple::sparc: 450 this->MCountName = "__mcount"; 451 break; 452 case llvm::Triple::mips64: 453 case llvm::Triple::mips64el: 454 case llvm::Triple::ppc: 455 case llvm::Triple::sparcv9: 456 this->MCountName = "_mcount"; 457 break; 458 } 459 } 460 }; 461 462 // Bitrig Target 463 template<typename Target> 464 class BitrigTargetInfo : public OSTargetInfo<Target> { 465 protected: 466 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 467 MacroBuilder &Builder) const override { 468 // Bitrig defines; list based off of gcc output 469 470 Builder.defineMacro("__Bitrig__"); 471 DefineStd(Builder, "unix", Opts); 472 Builder.defineMacro("__ELF__"); 473 if (Opts.POSIXThreads) 474 Builder.defineMacro("_REENTRANT"); 475 } 476 public: 477 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 478 this->UserLabelPrefix = ""; 479 this->MCountName = "__mcount"; 480 } 481 }; 482 483 // PSP Target 484 template<typename Target> 485 class PSPTargetInfo : public OSTargetInfo<Target> { 486 protected: 487 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 488 MacroBuilder &Builder) const override { 489 // PSP defines; list based on the output of the pspdev gcc toolchain. 490 Builder.defineMacro("PSP"); 491 Builder.defineMacro("_PSP"); 492 Builder.defineMacro("__psp__"); 493 Builder.defineMacro("__ELF__"); 494 } 495 public: 496 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 497 this->UserLabelPrefix = ""; 498 } 499 }; 500 501 // PS3 PPU Target 502 template<typename Target> 503 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 504 protected: 505 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 506 MacroBuilder &Builder) const override { 507 // PS3 PPU defines. 508 Builder.defineMacro("__PPC__"); 509 Builder.defineMacro("__PPU__"); 510 Builder.defineMacro("__CELLOS_LV2__"); 511 Builder.defineMacro("__ELF__"); 512 Builder.defineMacro("__LP32__"); 513 Builder.defineMacro("_ARCH_PPC64"); 514 Builder.defineMacro("__powerpc64__"); 515 } 516 public: 517 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 518 this->UserLabelPrefix = ""; 519 this->LongWidth = this->LongAlign = 32; 520 this->PointerWidth = this->PointerAlign = 32; 521 this->IntMaxType = TargetInfo::SignedLongLong; 522 this->Int64Type = TargetInfo::SignedLongLong; 523 this->SizeType = TargetInfo::UnsignedInt; 524 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64"; 525 } 526 }; 527 528 template <typename Target> 529 class PS4OSTargetInfo : public OSTargetInfo<Target> { 530 protected: 531 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 532 MacroBuilder &Builder) const override { 533 Builder.defineMacro("__FreeBSD__", "9"); 534 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 535 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 536 DefineStd(Builder, "unix", Opts); 537 Builder.defineMacro("__ELF__"); 538 Builder.defineMacro("__PS4__"); 539 } 540 public: 541 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 542 this->WCharType = this->UnsignedShort; 543 544 this->UserLabelPrefix = ""; 545 546 switch (Triple.getArch()) { 547 default: 548 case llvm::Triple::x86_64: 549 this->MCountName = ".mcount"; 550 break; 551 } 552 } 553 }; 554 555 // Solaris target 556 template<typename Target> 557 class SolarisTargetInfo : public OSTargetInfo<Target> { 558 protected: 559 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 560 MacroBuilder &Builder) const override { 561 DefineStd(Builder, "sun", Opts); 562 DefineStd(Builder, "unix", Opts); 563 Builder.defineMacro("__ELF__"); 564 Builder.defineMacro("__svr4__"); 565 Builder.defineMacro("__SVR4"); 566 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 567 // newer, but to 500 for everything else. feature_test.h has a check to 568 // ensure that you are not using C99 with an old version of X/Open or C89 569 // with a new version. 570 if (Opts.C99) 571 Builder.defineMacro("_XOPEN_SOURCE", "600"); 572 else 573 Builder.defineMacro("_XOPEN_SOURCE", "500"); 574 if (Opts.CPlusPlus) 575 Builder.defineMacro("__C99FEATURES__"); 576 Builder.defineMacro("_LARGEFILE_SOURCE"); 577 Builder.defineMacro("_LARGEFILE64_SOURCE"); 578 Builder.defineMacro("__EXTENSIONS__"); 579 Builder.defineMacro("_REENTRANT"); 580 } 581 public: 582 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 583 this->UserLabelPrefix = ""; 584 this->WCharType = this->SignedInt; 585 // FIXME: WIntType should be SignedLong 586 } 587 }; 588 589 // Windows target 590 template<typename Target> 591 class WindowsTargetInfo : public OSTargetInfo<Target> { 592 protected: 593 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 594 MacroBuilder &Builder) const override { 595 Builder.defineMacro("_WIN32"); 596 } 597 void getVisualStudioDefines(const LangOptions &Opts, 598 MacroBuilder &Builder) const { 599 if (Opts.CPlusPlus) { 600 if (Opts.RTTIData) 601 Builder.defineMacro("_CPPRTTI"); 602 603 if (Opts.CXXExceptions) 604 Builder.defineMacro("_CPPUNWIND"); 605 } 606 607 if (!Opts.CharIsSigned) 608 Builder.defineMacro("_CHAR_UNSIGNED"); 609 610 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 611 // but it works for now. 612 if (Opts.POSIXThreads) 613 Builder.defineMacro("_MT"); 614 615 if (Opts.MSCompatibilityVersion) { 616 Builder.defineMacro("_MSC_VER", 617 Twine(Opts.MSCompatibilityVersion / 100000)); 618 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 619 // FIXME We cannot encode the revision information into 32-bits 620 Builder.defineMacro("_MSC_BUILD", Twine(1)); 621 } 622 623 if (Opts.MicrosoftExt) { 624 Builder.defineMacro("_MSC_EXTENSIONS"); 625 626 if (Opts.CPlusPlus11) { 627 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 628 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 629 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 630 } 631 } 632 633 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 634 } 635 636 public: 637 WindowsTargetInfo(const llvm::Triple &Triple) 638 : OSTargetInfo<Target>(Triple) {} 639 }; 640 641 template <typename Target> 642 class NaClTargetInfo : public OSTargetInfo<Target> { 643 protected: 644 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 645 MacroBuilder &Builder) const override { 646 if (Opts.POSIXThreads) 647 Builder.defineMacro("_REENTRANT"); 648 if (Opts.CPlusPlus) 649 Builder.defineMacro("_GNU_SOURCE"); 650 651 DefineStd(Builder, "unix", Opts); 652 Builder.defineMacro("__ELF__"); 653 Builder.defineMacro("__native_client__"); 654 } 655 656 public: 657 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 658 this->UserLabelPrefix = ""; 659 this->LongAlign = 32; 660 this->LongWidth = 32; 661 this->PointerAlign = 32; 662 this->PointerWidth = 32; 663 this->IntMaxType = TargetInfo::SignedLongLong; 664 this->Int64Type = TargetInfo::SignedLongLong; 665 this->DoubleAlign = 64; 666 this->LongDoubleWidth = 64; 667 this->LongDoubleAlign = 64; 668 this->LongLongWidth = 64; 669 this->LongLongAlign = 64; 670 this->SizeType = TargetInfo::UnsignedInt; 671 this->PtrDiffType = TargetInfo::SignedInt; 672 this->IntPtrType = TargetInfo::SignedInt; 673 // RegParmMax is inherited from the underlying architecture 674 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 675 if (Triple.getArch() == llvm::Triple::arm) { 676 this->DescriptionString = 677 "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 678 } else if (Triple.getArch() == llvm::Triple::x86) { 679 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 680 } else if (Triple.getArch() == llvm::Triple::x86_64) { 681 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 682 } else if (Triple.getArch() == llvm::Triple::mipsel) { 683 // Handled on mips' setDescriptionString. 684 } else { 685 assert(Triple.getArch() == llvm::Triple::le32); 686 this->DescriptionString = "e-p:32:32-i64:64"; 687 } 688 } 689 }; 690 } // end anonymous namespace. 691 692 //===----------------------------------------------------------------------===// 693 // Specific target implementations. 694 //===----------------------------------------------------------------------===// 695 696 namespace { 697 // PPC abstract base class 698 class PPCTargetInfo : public TargetInfo { 699 static const Builtin::Info BuiltinInfo[]; 700 static const char * const GCCRegNames[]; 701 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 702 std::string CPU; 703 704 // Target cpu features. 705 bool HasVSX; 706 bool HasP8Vector; 707 708 protected: 709 std::string ABI; 710 711 public: 712 PPCTargetInfo(const llvm::Triple &Triple) 713 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false) { 714 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 715 LongDoubleWidth = LongDoubleAlign = 128; 716 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 717 } 718 719 /// \brief Flags for architecture specific defines. 720 typedef enum { 721 ArchDefineNone = 0, 722 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 723 ArchDefinePpcgr = 1 << 1, 724 ArchDefinePpcsq = 1 << 2, 725 ArchDefine440 = 1 << 3, 726 ArchDefine603 = 1 << 4, 727 ArchDefine604 = 1 << 5, 728 ArchDefinePwr4 = 1 << 6, 729 ArchDefinePwr5 = 1 << 7, 730 ArchDefinePwr5x = 1 << 8, 731 ArchDefinePwr6 = 1 << 9, 732 ArchDefinePwr6x = 1 << 10, 733 ArchDefinePwr7 = 1 << 11, 734 ArchDefinePwr8 = 1 << 12, 735 ArchDefineA2 = 1 << 13, 736 ArchDefineA2q = 1 << 14 737 } ArchDefineTypes; 738 739 // Note: GCC recognizes the following additional cpus: 740 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 741 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 742 // titan, rs64. 743 bool setCPU(const std::string &Name) override { 744 bool CPUKnown = llvm::StringSwitch<bool>(Name) 745 .Case("generic", true) 746 .Case("440", true) 747 .Case("450", true) 748 .Case("601", true) 749 .Case("602", true) 750 .Case("603", true) 751 .Case("603e", true) 752 .Case("603ev", true) 753 .Case("604", true) 754 .Case("604e", true) 755 .Case("620", true) 756 .Case("630", true) 757 .Case("g3", true) 758 .Case("7400", true) 759 .Case("g4", true) 760 .Case("7450", true) 761 .Case("g4+", true) 762 .Case("750", true) 763 .Case("970", true) 764 .Case("g5", true) 765 .Case("a2", true) 766 .Case("a2q", true) 767 .Case("e500mc", true) 768 .Case("e5500", true) 769 .Case("power3", true) 770 .Case("pwr3", true) 771 .Case("power4", true) 772 .Case("pwr4", true) 773 .Case("power5", true) 774 .Case("pwr5", true) 775 .Case("power5x", true) 776 .Case("pwr5x", true) 777 .Case("power6", true) 778 .Case("pwr6", true) 779 .Case("power6x", true) 780 .Case("pwr6x", true) 781 .Case("power7", true) 782 .Case("pwr7", true) 783 .Case("power8", true) 784 .Case("pwr8", true) 785 .Case("powerpc", true) 786 .Case("ppc", true) 787 .Case("powerpc64", true) 788 .Case("ppc64", true) 789 .Case("powerpc64le", true) 790 .Case("ppc64le", true) 791 .Default(false); 792 793 if (CPUKnown) 794 CPU = Name; 795 796 return CPUKnown; 797 } 798 799 800 StringRef getABI() const override { return ABI; } 801 802 void getTargetBuiltins(const Builtin::Info *&Records, 803 unsigned &NumRecords) const override { 804 Records = BuiltinInfo; 805 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 806 } 807 808 bool isCLZForZeroUndef() const override { return false; } 809 810 void getTargetDefines(const LangOptions &Opts, 811 MacroBuilder &Builder) const override; 812 813 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 814 815 bool handleTargetFeatures(std::vector<std::string> &Features, 816 DiagnosticsEngine &Diags) override; 817 bool hasFeature(StringRef Feature) const override; 818 819 void getGCCRegNames(const char * const *&Names, 820 unsigned &NumNames) const override; 821 void getGCCRegAliases(const GCCRegAlias *&Aliases, 822 unsigned &NumAliases) const override; 823 bool validateAsmConstraint(const char *&Name, 824 TargetInfo::ConstraintInfo &Info) const override { 825 switch (*Name) { 826 default: return false; 827 case 'O': // Zero 828 break; 829 case 'b': // Base register 830 case 'f': // Floating point register 831 Info.setAllowsRegister(); 832 break; 833 // FIXME: The following are added to allow parsing. 834 // I just took a guess at what the actions should be. 835 // Also, is more specific checking needed? I.e. specific registers? 836 case 'd': // Floating point register (containing 64-bit value) 837 case 'v': // Altivec vector register 838 Info.setAllowsRegister(); 839 break; 840 case 'w': 841 switch (Name[1]) { 842 case 'd':// VSX vector register to hold vector double data 843 case 'f':// VSX vector register to hold vector float data 844 case 's':// VSX vector register to hold scalar float data 845 case 'a':// Any VSX register 846 case 'c':// An individual CR bit 847 break; 848 default: 849 return false; 850 } 851 Info.setAllowsRegister(); 852 Name++; // Skip over 'w'. 853 break; 854 case 'h': // `MQ', `CTR', or `LINK' register 855 case 'q': // `MQ' register 856 case 'c': // `CTR' register 857 case 'l': // `LINK' register 858 case 'x': // `CR' register (condition register) number 0 859 case 'y': // `CR' register (condition register) 860 case 'z': // `XER[CA]' carry bit (part of the XER register) 861 Info.setAllowsRegister(); 862 break; 863 case 'I': // Signed 16-bit constant 864 case 'J': // Unsigned 16-bit constant shifted left 16 bits 865 // (use `L' instead for SImode constants) 866 case 'K': // Unsigned 16-bit constant 867 case 'L': // Signed 16-bit constant shifted left 16 bits 868 case 'M': // Constant larger than 31 869 case 'N': // Exact power of 2 870 case 'P': // Constant whose negation is a signed 16-bit constant 871 case 'G': // Floating point constant that can be loaded into a 872 // register with one instruction per word 873 case 'H': // Integer/Floating point constant that can be loaded 874 // into a register using three instructions 875 break; 876 case 'm': // Memory operand. Note that on PowerPC targets, m can 877 // include addresses that update the base register. It 878 // is therefore only safe to use `m' in an asm statement 879 // if that asm statement accesses the operand exactly once. 880 // The asm statement must also use `%U<opno>' as a 881 // placeholder for the "update" flag in the corresponding 882 // load or store instruction. For example: 883 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 884 // is correct but: 885 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 886 // is not. Use es rather than m if you don't want the base 887 // register to be updated. 888 case 'e': 889 if (Name[1] != 's') 890 return false; 891 // es: A "stable" memory operand; that is, one which does not 892 // include any automodification of the base register. Unlike 893 // `m', this constraint can be used in asm statements that 894 // might access the operand several times, or that might not 895 // access it at all. 896 Info.setAllowsMemory(); 897 Name++; // Skip over 'e'. 898 break; 899 case 'Q': // Memory operand that is an offset from a register (it is 900 // usually better to use `m' or `es' in asm statements) 901 case 'Z': // Memory operand that is an indexed or indirect from a 902 // register (it is usually better to use `m' or `es' in 903 // asm statements) 904 Info.setAllowsMemory(); 905 Info.setAllowsRegister(); 906 break; 907 case 'R': // AIX TOC entry 908 case 'a': // Address operand that is an indexed or indirect from a 909 // register (`p' is preferable for asm statements) 910 case 'S': // Constant suitable as a 64-bit mask operand 911 case 'T': // Constant suitable as a 32-bit mask operand 912 case 'U': // System V Release 4 small data area reference 913 case 't': // AND masks that can be performed by two rldic{l, r} 914 // instructions 915 case 'W': // Vector constant that does not require memory 916 case 'j': // Vector constant that is all zeros. 917 break; 918 // End FIXME. 919 } 920 return true; 921 } 922 std::string convertConstraint(const char *&Constraint) const override { 923 std::string R; 924 switch (*Constraint) { 925 case 'e': 926 case 'w': 927 // Two-character constraint; add "^" hint for later parsing. 928 R = std::string("^") + std::string(Constraint, 2); 929 Constraint++; 930 break; 931 default: 932 return TargetInfo::convertConstraint(Constraint); 933 } 934 return R; 935 } 936 const char *getClobbers() const override { 937 return ""; 938 } 939 int getEHDataRegisterNumber(unsigned RegNo) const override { 940 if (RegNo == 0) return 3; 941 if (RegNo == 1) return 4; 942 return -1; 943 } 944 }; 945 946 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 947 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 948 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 949 ALL_LANGUAGES }, 950 #include "clang/Basic/BuiltinsPPC.def" 951 }; 952 953 /// handleTargetFeatures - Perform initialization based on the user 954 /// configured set of features. 955 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 956 DiagnosticsEngine &Diags) { 957 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 958 // Ignore disabled features. 959 if (Features[i][0] == '-') 960 continue; 961 962 StringRef Feature = StringRef(Features[i]).substr(1); 963 964 if (Feature == "vsx") { 965 HasVSX = true; 966 continue; 967 } 968 969 if (Feature == "power8-vector") { 970 HasP8Vector = true; 971 continue; 972 } 973 974 // TODO: Finish this list and add an assert that we've handled them 975 // all. 976 } 977 978 return true; 979 } 980 981 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 982 /// #defines that are not tied to a specific subtarget. 983 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 984 MacroBuilder &Builder) const { 985 // Target identification. 986 Builder.defineMacro("__ppc__"); 987 Builder.defineMacro("__PPC__"); 988 Builder.defineMacro("_ARCH_PPC"); 989 Builder.defineMacro("__powerpc__"); 990 Builder.defineMacro("__POWERPC__"); 991 if (PointerWidth == 64) { 992 Builder.defineMacro("_ARCH_PPC64"); 993 Builder.defineMacro("__powerpc64__"); 994 Builder.defineMacro("__ppc64__"); 995 Builder.defineMacro("__PPC64__"); 996 } 997 998 // Target properties. 999 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1000 Builder.defineMacro("_LITTLE_ENDIAN"); 1001 } else { 1002 if (getTriple().getOS() != llvm::Triple::NetBSD && 1003 getTriple().getOS() != llvm::Triple::OpenBSD) 1004 Builder.defineMacro("_BIG_ENDIAN"); 1005 } 1006 1007 // ABI options. 1008 if (ABI == "elfv1") 1009 Builder.defineMacro("_CALL_ELF", "1"); 1010 if (ABI == "elfv2") 1011 Builder.defineMacro("_CALL_ELF", "2"); 1012 1013 // Subtarget options. 1014 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1015 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1016 1017 // FIXME: Should be controlled by command line option. 1018 if (LongDoubleWidth == 128) 1019 Builder.defineMacro("__LONG_DOUBLE_128__"); 1020 1021 if (Opts.AltiVec) { 1022 Builder.defineMacro("__VEC__", "10206"); 1023 Builder.defineMacro("__ALTIVEC__"); 1024 } 1025 1026 // CPU identification. 1027 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1028 .Case("440", ArchDefineName) 1029 .Case("450", ArchDefineName | ArchDefine440) 1030 .Case("601", ArchDefineName) 1031 .Case("602", ArchDefineName | ArchDefinePpcgr) 1032 .Case("603", ArchDefineName | ArchDefinePpcgr) 1033 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1034 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1035 .Case("604", ArchDefineName | ArchDefinePpcgr) 1036 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1037 .Case("620", ArchDefineName | ArchDefinePpcgr) 1038 .Case("630", ArchDefineName | ArchDefinePpcgr) 1039 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1040 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1041 .Case("750", ArchDefineName | ArchDefinePpcgr) 1042 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1043 | ArchDefinePpcsq) 1044 .Case("a2", ArchDefineA2) 1045 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1046 .Case("pwr3", ArchDefinePpcgr) 1047 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1048 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1049 | ArchDefinePpcsq) 1050 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1051 | ArchDefinePpcgr | ArchDefinePpcsq) 1052 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1053 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1054 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1055 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1056 | ArchDefinePpcsq) 1057 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1058 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1059 | ArchDefinePpcgr | ArchDefinePpcsq) 1060 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1061 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1062 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1063 .Case("power3", ArchDefinePpcgr) 1064 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1065 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1066 | ArchDefinePpcsq) 1067 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1068 | ArchDefinePpcgr | ArchDefinePpcsq) 1069 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1070 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1071 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1072 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1073 | ArchDefinePpcsq) 1074 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1075 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1076 | ArchDefinePpcgr | ArchDefinePpcsq) 1077 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1078 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1079 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1080 .Default(ArchDefineNone); 1081 1082 if (defs & ArchDefineName) 1083 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1084 if (defs & ArchDefinePpcgr) 1085 Builder.defineMacro("_ARCH_PPCGR"); 1086 if (defs & ArchDefinePpcsq) 1087 Builder.defineMacro("_ARCH_PPCSQ"); 1088 if (defs & ArchDefine440) 1089 Builder.defineMacro("_ARCH_440"); 1090 if (defs & ArchDefine603) 1091 Builder.defineMacro("_ARCH_603"); 1092 if (defs & ArchDefine604) 1093 Builder.defineMacro("_ARCH_604"); 1094 if (defs & ArchDefinePwr4) 1095 Builder.defineMacro("_ARCH_PWR4"); 1096 if (defs & ArchDefinePwr5) 1097 Builder.defineMacro("_ARCH_PWR5"); 1098 if (defs & ArchDefinePwr5x) 1099 Builder.defineMacro("_ARCH_PWR5X"); 1100 if (defs & ArchDefinePwr6) 1101 Builder.defineMacro("_ARCH_PWR6"); 1102 if (defs & ArchDefinePwr6x) 1103 Builder.defineMacro("_ARCH_PWR6X"); 1104 if (defs & ArchDefinePwr7) 1105 Builder.defineMacro("_ARCH_PWR7"); 1106 if (defs & ArchDefinePwr8) 1107 Builder.defineMacro("_ARCH_PWR8"); 1108 if (defs & ArchDefineA2) 1109 Builder.defineMacro("_ARCH_A2"); 1110 if (defs & ArchDefineA2q) { 1111 Builder.defineMacro("_ARCH_A2Q"); 1112 Builder.defineMacro("_ARCH_QP"); 1113 } 1114 1115 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1116 Builder.defineMacro("__bg__"); 1117 Builder.defineMacro("__THW_BLUEGENE__"); 1118 Builder.defineMacro("__bgq__"); 1119 Builder.defineMacro("__TOS_BGQ__"); 1120 } 1121 1122 if (HasVSX) 1123 Builder.defineMacro("__VSX__"); 1124 if (HasP8Vector) 1125 Builder.defineMacro("__POWER8_VECTOR__"); 1126 1127 // FIXME: The following are not yet generated here by Clang, but are 1128 // generated by GCC: 1129 // 1130 // _SOFT_FLOAT_ 1131 // __RECIP_PRECISION__ 1132 // __APPLE_ALTIVEC__ 1133 // __RECIP__ 1134 // __RECIPF__ 1135 // __RSQRTE__ 1136 // __RSQRTEF__ 1137 // _SOFT_DOUBLE_ 1138 // __NO_LWSYNC__ 1139 // __HAVE_BSWAP__ 1140 // __LONGDOUBLE128 1141 // __CMODEL_MEDIUM__ 1142 // __CMODEL_LARGE__ 1143 // _CALL_SYSV 1144 // _CALL_DARWIN 1145 // __NO_FPRS__ 1146 } 1147 1148 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1149 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1150 .Case("7400", true) 1151 .Case("g4", true) 1152 .Case("7450", true) 1153 .Case("g4+", true) 1154 .Case("970", true) 1155 .Case("g5", true) 1156 .Case("pwr6", true) 1157 .Case("pwr7", true) 1158 .Case("pwr8", true) 1159 .Case("ppc64", true) 1160 .Case("ppc64le", true) 1161 .Default(false); 1162 1163 Features["qpx"] = (CPU == "a2q"); 1164 1165 if (!ABI.empty()) 1166 Features[ABI] = true; 1167 } 1168 1169 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1170 return llvm::StringSwitch<bool>(Feature) 1171 .Case("powerpc", true) 1172 .Case("vsx", HasVSX) 1173 .Case("power8-vector", HasP8Vector) 1174 .Default(false); 1175 } 1176 1177 const char * const PPCTargetInfo::GCCRegNames[] = { 1178 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1179 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1180 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1181 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1182 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1183 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1184 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1185 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1186 "mq", "lr", "ctr", "ap", 1187 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1188 "xer", 1189 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1190 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1191 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1192 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1193 "vrsave", "vscr", 1194 "spe_acc", "spefscr", 1195 "sfp" 1196 }; 1197 1198 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1199 unsigned &NumNames) const { 1200 Names = GCCRegNames; 1201 NumNames = llvm::array_lengthof(GCCRegNames); 1202 } 1203 1204 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1205 // While some of these aliases do map to different registers 1206 // they still share the same register name. 1207 { { "0" }, "r0" }, 1208 { { "1"}, "r1" }, 1209 { { "2" }, "r2" }, 1210 { { "3" }, "r3" }, 1211 { { "4" }, "r4" }, 1212 { { "5" }, "r5" }, 1213 { { "6" }, "r6" }, 1214 { { "7" }, "r7" }, 1215 { { "8" }, "r8" }, 1216 { { "9" }, "r9" }, 1217 { { "10" }, "r10" }, 1218 { { "11" }, "r11" }, 1219 { { "12" }, "r12" }, 1220 { { "13" }, "r13" }, 1221 { { "14" }, "r14" }, 1222 { { "15" }, "r15" }, 1223 { { "16" }, "r16" }, 1224 { { "17" }, "r17" }, 1225 { { "18" }, "r18" }, 1226 { { "19" }, "r19" }, 1227 { { "20" }, "r20" }, 1228 { { "21" }, "r21" }, 1229 { { "22" }, "r22" }, 1230 { { "23" }, "r23" }, 1231 { { "24" }, "r24" }, 1232 { { "25" }, "r25" }, 1233 { { "26" }, "r26" }, 1234 { { "27" }, "r27" }, 1235 { { "28" }, "r28" }, 1236 { { "29" }, "r29" }, 1237 { { "30" }, "r30" }, 1238 { { "31" }, "r31" }, 1239 { { "fr0" }, "f0" }, 1240 { { "fr1" }, "f1" }, 1241 { { "fr2" }, "f2" }, 1242 { { "fr3" }, "f3" }, 1243 { { "fr4" }, "f4" }, 1244 { { "fr5" }, "f5" }, 1245 { { "fr6" }, "f6" }, 1246 { { "fr7" }, "f7" }, 1247 { { "fr8" }, "f8" }, 1248 { { "fr9" }, "f9" }, 1249 { { "fr10" }, "f10" }, 1250 { { "fr11" }, "f11" }, 1251 { { "fr12" }, "f12" }, 1252 { { "fr13" }, "f13" }, 1253 { { "fr14" }, "f14" }, 1254 { { "fr15" }, "f15" }, 1255 { { "fr16" }, "f16" }, 1256 { { "fr17" }, "f17" }, 1257 { { "fr18" }, "f18" }, 1258 { { "fr19" }, "f19" }, 1259 { { "fr20" }, "f20" }, 1260 { { "fr21" }, "f21" }, 1261 { { "fr22" }, "f22" }, 1262 { { "fr23" }, "f23" }, 1263 { { "fr24" }, "f24" }, 1264 { { "fr25" }, "f25" }, 1265 { { "fr26" }, "f26" }, 1266 { { "fr27" }, "f27" }, 1267 { { "fr28" }, "f28" }, 1268 { { "fr29" }, "f29" }, 1269 { { "fr30" }, "f30" }, 1270 { { "fr31" }, "f31" }, 1271 { { "cc" }, "cr0" }, 1272 }; 1273 1274 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1275 unsigned &NumAliases) const { 1276 Aliases = GCCRegAliases; 1277 NumAliases = llvm::array_lengthof(GCCRegAliases); 1278 } 1279 } // end anonymous namespace. 1280 1281 namespace { 1282 class PPC32TargetInfo : public PPCTargetInfo { 1283 public: 1284 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1285 DescriptionString = "E-m:e-p:32:32-i64:64-n32"; 1286 1287 switch (getTriple().getOS()) { 1288 case llvm::Triple::Linux: 1289 case llvm::Triple::FreeBSD: 1290 case llvm::Triple::NetBSD: 1291 SizeType = UnsignedInt; 1292 PtrDiffType = SignedInt; 1293 IntPtrType = SignedInt; 1294 break; 1295 default: 1296 break; 1297 } 1298 1299 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1300 LongDoubleWidth = LongDoubleAlign = 64; 1301 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1302 } 1303 1304 // PPC32 supports atomics up to 4 bytes. 1305 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1306 } 1307 1308 BuiltinVaListKind getBuiltinVaListKind() const override { 1309 // This is the ELF definition, and is overridden by the Darwin sub-target 1310 return TargetInfo::PowerABIBuiltinVaList; 1311 } 1312 }; 1313 } // end anonymous namespace. 1314 1315 // Note: ABI differences may eventually require us to have a separate 1316 // TargetInfo for little endian. 1317 namespace { 1318 class PPC64TargetInfo : public PPCTargetInfo { 1319 public: 1320 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1321 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1322 IntMaxType = SignedLong; 1323 Int64Type = SignedLong; 1324 1325 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1326 DescriptionString = "e-m:e-i64:64-n32:64"; 1327 ABI = "elfv2"; 1328 } else { 1329 DescriptionString = "E-m:e-i64:64-n32:64"; 1330 ABI = "elfv1"; 1331 } 1332 1333 switch (getTriple().getOS()) { 1334 case llvm::Triple::FreeBSD: 1335 LongDoubleWidth = LongDoubleAlign = 64; 1336 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1337 break; 1338 case llvm::Triple::NetBSD: 1339 IntMaxType = SignedLongLong; 1340 Int64Type = SignedLongLong; 1341 break; 1342 default: 1343 break; 1344 } 1345 1346 // PPC64 supports atomics up to 8 bytes. 1347 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1348 } 1349 BuiltinVaListKind getBuiltinVaListKind() const override { 1350 return TargetInfo::CharPtrBuiltinVaList; 1351 } 1352 // PPC64 Linux-specifc ABI options. 1353 bool setABI(const std::string &Name) override { 1354 if (Name == "elfv1" || Name == "elfv2") { 1355 ABI = Name; 1356 return true; 1357 } 1358 return false; 1359 } 1360 }; 1361 } // end anonymous namespace. 1362 1363 1364 namespace { 1365 class DarwinPPC32TargetInfo : 1366 public DarwinTargetInfo<PPC32TargetInfo> { 1367 public: 1368 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1369 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1370 HasAlignMac68kSupport = true; 1371 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1372 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1373 LongLongAlign = 32; 1374 SuitableAlign = 128; 1375 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; 1376 } 1377 BuiltinVaListKind getBuiltinVaListKind() const override { 1378 return TargetInfo::CharPtrBuiltinVaList; 1379 } 1380 }; 1381 1382 class DarwinPPC64TargetInfo : 1383 public DarwinTargetInfo<PPC64TargetInfo> { 1384 public: 1385 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1386 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1387 HasAlignMac68kSupport = true; 1388 SuitableAlign = 128; 1389 DescriptionString = "E-m:o-i64:64-n32:64"; 1390 } 1391 }; 1392 } // end anonymous namespace. 1393 1394 namespace { 1395 static const unsigned NVPTXAddrSpaceMap[] = { 1396 1, // opencl_global 1397 3, // opencl_local 1398 4, // opencl_constant 1399 // FIXME: generic has to be added to the target 1400 0, // opencl_generic 1401 1, // cuda_device 1402 4, // cuda_constant 1403 3, // cuda_shared 1404 }; 1405 class NVPTXTargetInfo : public TargetInfo { 1406 static const char * const GCCRegNames[]; 1407 static const Builtin::Info BuiltinInfo[]; 1408 1409 // The GPU profiles supported by the NVPTX backend 1410 enum GPUKind { 1411 GK_NONE, 1412 GK_SM20, 1413 GK_SM21, 1414 GK_SM30, 1415 GK_SM35, 1416 } GPU; 1417 1418 public: 1419 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1420 BigEndian = false; 1421 TLSSupported = false; 1422 LongWidth = LongAlign = 64; 1423 AddrSpaceMap = &NVPTXAddrSpaceMap; 1424 UseAddrSpaceMapMangling = true; 1425 // Define available target features 1426 // These must be defined in sorted order! 1427 NoAsmVariants = true; 1428 // Set the default GPU to sm20 1429 GPU = GK_SM20; 1430 } 1431 void getTargetDefines(const LangOptions &Opts, 1432 MacroBuilder &Builder) const override { 1433 Builder.defineMacro("__PTX__"); 1434 Builder.defineMacro("__NVPTX__"); 1435 if (Opts.CUDAIsDevice) { 1436 // Set __CUDA_ARCH__ for the GPU specified. 1437 std::string CUDAArchCode; 1438 switch (GPU) { 1439 case GK_SM20: 1440 CUDAArchCode = "200"; 1441 break; 1442 case GK_SM21: 1443 CUDAArchCode = "210"; 1444 break; 1445 case GK_SM30: 1446 CUDAArchCode = "300"; 1447 break; 1448 case GK_SM35: 1449 CUDAArchCode = "350"; 1450 break; 1451 default: 1452 llvm_unreachable("Unhandled target CPU"); 1453 } 1454 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1455 } 1456 } 1457 void getTargetBuiltins(const Builtin::Info *&Records, 1458 unsigned &NumRecords) const override { 1459 Records = BuiltinInfo; 1460 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1461 } 1462 bool hasFeature(StringRef Feature) const override { 1463 return Feature == "ptx" || Feature == "nvptx"; 1464 } 1465 1466 void getGCCRegNames(const char * const *&Names, 1467 unsigned &NumNames) const override; 1468 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1469 unsigned &NumAliases) const override { 1470 // No aliases. 1471 Aliases = nullptr; 1472 NumAliases = 0; 1473 } 1474 bool 1475 validateAsmConstraint(const char *&Name, 1476 TargetInfo::ConstraintInfo &Info) const override { 1477 switch (*Name) { 1478 default: return false; 1479 case 'c': 1480 case 'h': 1481 case 'r': 1482 case 'l': 1483 case 'f': 1484 case 'd': 1485 Info.setAllowsRegister(); 1486 return true; 1487 } 1488 } 1489 const char *getClobbers() const override { 1490 // FIXME: Is this really right? 1491 return ""; 1492 } 1493 BuiltinVaListKind getBuiltinVaListKind() const override { 1494 // FIXME: implement 1495 return TargetInfo::CharPtrBuiltinVaList; 1496 } 1497 bool setCPU(const std::string &Name) override { 1498 GPU = llvm::StringSwitch<GPUKind>(Name) 1499 .Case("sm_20", GK_SM20) 1500 .Case("sm_21", GK_SM21) 1501 .Case("sm_30", GK_SM30) 1502 .Case("sm_35", GK_SM35) 1503 .Default(GK_NONE); 1504 1505 return GPU != GK_NONE; 1506 } 1507 }; 1508 1509 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1510 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1511 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1512 ALL_LANGUAGES }, 1513 #include "clang/Basic/BuiltinsNVPTX.def" 1514 }; 1515 1516 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1517 "r0" 1518 }; 1519 1520 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1521 unsigned &NumNames) const { 1522 Names = GCCRegNames; 1523 NumNames = llvm::array_lengthof(GCCRegNames); 1524 } 1525 1526 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1527 public: 1528 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1529 PointerWidth = PointerAlign = 32; 1530 SizeType = PtrDiffType = TargetInfo::UnsignedInt; 1531 IntPtrType = TargetInfo::SignedInt; 1532 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1533 } 1534 }; 1535 1536 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1537 public: 1538 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1539 PointerWidth = PointerAlign = 64; 1540 SizeType = PtrDiffType = TargetInfo::UnsignedLongLong; 1541 IntPtrType = TargetInfo::SignedLongLong; 1542 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1543 } 1544 }; 1545 } 1546 1547 namespace { 1548 1549 static const unsigned R600AddrSpaceMap[] = { 1550 1, // opencl_global 1551 3, // opencl_local 1552 2, // opencl_constant 1553 4, // opencl_generic 1554 1, // cuda_device 1555 2, // cuda_constant 1556 3 // cuda_shared 1557 }; 1558 1559 // If you edit the description strings, make sure you update 1560 // getPointerWidthV(). 1561 1562 static const char *DescriptionStringR600 = 1563 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1564 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1565 1566 static const char *DescriptionStringR600DoubleOps = 1567 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1568 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1569 1570 static const char *DescriptionStringSI = 1571 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1572 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1573 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1574 1575 class R600TargetInfo : public TargetInfo { 1576 static const Builtin::Info BuiltinInfo[]; 1577 1578 /// \brief The GPU profiles supported by the R600 target. 1579 enum GPUKind { 1580 GK_NONE, 1581 GK_R600, 1582 GK_R600_DOUBLE_OPS, 1583 GK_R700, 1584 GK_R700_DOUBLE_OPS, 1585 GK_EVERGREEN, 1586 GK_EVERGREEN_DOUBLE_OPS, 1587 GK_NORTHERN_ISLANDS, 1588 GK_CAYMAN, 1589 GK_SOUTHERN_ISLANDS, 1590 GK_SEA_ISLANDS 1591 } GPU; 1592 1593 public: 1594 R600TargetInfo(const llvm::Triple &Triple) 1595 : TargetInfo(Triple) { 1596 1597 if (Triple.getArch() == llvm::Triple::amdgcn) { 1598 DescriptionString = DescriptionStringSI; 1599 GPU = GK_SOUTHERN_ISLANDS; 1600 } else { 1601 DescriptionString = DescriptionStringR600; 1602 GPU = GK_R600; 1603 } 1604 AddrSpaceMap = &R600AddrSpaceMap; 1605 UseAddrSpaceMapMangling = true; 1606 } 1607 1608 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1609 if (GPU <= GK_CAYMAN) 1610 return 32; 1611 1612 switch(AddrSpace) { 1613 default: 1614 return 64; 1615 case 0: 1616 case 3: 1617 case 5: 1618 return 32; 1619 } 1620 } 1621 1622 const char * getClobbers() const override { 1623 return ""; 1624 } 1625 1626 void getGCCRegNames(const char * const *&Names, 1627 unsigned &numNames) const override { 1628 Names = nullptr; 1629 numNames = 0; 1630 } 1631 1632 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1633 unsigned &NumAliases) const override { 1634 Aliases = nullptr; 1635 NumAliases = 0; 1636 } 1637 1638 bool validateAsmConstraint(const char *&Name, 1639 TargetInfo::ConstraintInfo &info) const override { 1640 return true; 1641 } 1642 1643 void getTargetBuiltins(const Builtin::Info *&Records, 1644 unsigned &NumRecords) const override { 1645 Records = BuiltinInfo; 1646 NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin; 1647 } 1648 1649 void getTargetDefines(const LangOptions &Opts, 1650 MacroBuilder &Builder) const override { 1651 Builder.defineMacro("__R600__"); 1652 } 1653 1654 BuiltinVaListKind getBuiltinVaListKind() const override { 1655 return TargetInfo::CharPtrBuiltinVaList; 1656 } 1657 1658 bool setCPU(const std::string &Name) override { 1659 GPU = llvm::StringSwitch<GPUKind>(Name) 1660 .Case("r600" , GK_R600) 1661 .Case("rv610", GK_R600) 1662 .Case("rv620", GK_R600) 1663 .Case("rv630", GK_R600) 1664 .Case("rv635", GK_R600) 1665 .Case("rs780", GK_R600) 1666 .Case("rs880", GK_R600) 1667 .Case("rv670", GK_R600_DOUBLE_OPS) 1668 .Case("rv710", GK_R700) 1669 .Case("rv730", GK_R700) 1670 .Case("rv740", GK_R700_DOUBLE_OPS) 1671 .Case("rv770", GK_R700_DOUBLE_OPS) 1672 .Case("palm", GK_EVERGREEN) 1673 .Case("cedar", GK_EVERGREEN) 1674 .Case("sumo", GK_EVERGREEN) 1675 .Case("sumo2", GK_EVERGREEN) 1676 .Case("redwood", GK_EVERGREEN) 1677 .Case("juniper", GK_EVERGREEN) 1678 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1679 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1680 .Case("barts", GK_NORTHERN_ISLANDS) 1681 .Case("turks", GK_NORTHERN_ISLANDS) 1682 .Case("caicos", GK_NORTHERN_ISLANDS) 1683 .Case("cayman", GK_CAYMAN) 1684 .Case("aruba", GK_CAYMAN) 1685 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1686 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1687 .Case("verde", GK_SOUTHERN_ISLANDS) 1688 .Case("oland", GK_SOUTHERN_ISLANDS) 1689 .Case("hainan", GK_SOUTHERN_ISLANDS) 1690 .Case("bonaire", GK_SEA_ISLANDS) 1691 .Case("kabini", GK_SEA_ISLANDS) 1692 .Case("kaveri", GK_SEA_ISLANDS) 1693 .Case("hawaii", GK_SEA_ISLANDS) 1694 .Case("mullins", GK_SEA_ISLANDS) 1695 .Default(GK_NONE); 1696 1697 if (GPU == GK_NONE) { 1698 return false; 1699 } 1700 1701 // Set the correct data layout 1702 switch (GPU) { 1703 case GK_NONE: 1704 case GK_R600: 1705 case GK_R700: 1706 case GK_EVERGREEN: 1707 case GK_NORTHERN_ISLANDS: 1708 DescriptionString = DescriptionStringR600; 1709 break; 1710 case GK_R600_DOUBLE_OPS: 1711 case GK_R700_DOUBLE_OPS: 1712 case GK_EVERGREEN_DOUBLE_OPS: 1713 case GK_CAYMAN: 1714 DescriptionString = DescriptionStringR600DoubleOps; 1715 break; 1716 case GK_SOUTHERN_ISLANDS: 1717 case GK_SEA_ISLANDS: 1718 DescriptionString = DescriptionStringSI; 1719 break; 1720 } 1721 1722 return true; 1723 } 1724 }; 1725 1726 const Builtin::Info R600TargetInfo::BuiltinInfo[] = { 1727 #define BUILTIN(ID, TYPE, ATTRS) \ 1728 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1729 #include "clang/Basic/BuiltinsR600.def" 1730 }; 1731 1732 } // end anonymous namespace 1733 1734 namespace { 1735 // Namespace for x86 abstract base class 1736 const Builtin::Info BuiltinInfo[] = { 1737 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1738 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1739 ALL_LANGUAGES }, 1740 #include "clang/Basic/BuiltinsX86.def" 1741 }; 1742 1743 static const char* const GCCRegNames[] = { 1744 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1745 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1746 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1747 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1748 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1749 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1750 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1751 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1752 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1753 }; 1754 1755 const TargetInfo::AddlRegName AddlRegNames[] = { 1756 { { "al", "ah", "eax", "rax" }, 0 }, 1757 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1758 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1759 { { "dl", "dh", "edx", "rdx" }, 1 }, 1760 { { "esi", "rsi" }, 4 }, 1761 { { "edi", "rdi" }, 5 }, 1762 { { "esp", "rsp" }, 7 }, 1763 { { "ebp", "rbp" }, 6 }, 1764 }; 1765 1766 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1767 // most of the implementation can be shared. 1768 class X86TargetInfo : public TargetInfo { 1769 enum X86SSEEnum { 1770 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1771 } SSELevel; 1772 enum MMX3DNowEnum { 1773 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1774 } MMX3DNowLevel; 1775 enum XOPEnum { 1776 NoXOP, 1777 SSE4A, 1778 FMA4, 1779 XOP 1780 } XOPLevel; 1781 1782 bool HasAES; 1783 bool HasPCLMUL; 1784 bool HasLZCNT; 1785 bool HasRDRND; 1786 bool HasFSGSBASE; 1787 bool HasBMI; 1788 bool HasBMI2; 1789 bool HasPOPCNT; 1790 bool HasRTM; 1791 bool HasPRFCHW; 1792 bool HasRDSEED; 1793 bool HasADX; 1794 bool HasTBM; 1795 bool HasFMA; 1796 bool HasF16C; 1797 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW, 1798 HasAVX512VL; 1799 bool HasSHA; 1800 bool HasCX16; 1801 1802 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1803 /// 1804 /// Each enumeration represents a particular CPU supported by Clang. These 1805 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1806 enum CPUKind { 1807 CK_Generic, 1808 1809 /// \name i386 1810 /// i386-generation processors. 1811 //@{ 1812 CK_i386, 1813 //@} 1814 1815 /// \name i486 1816 /// i486-generation processors. 1817 //@{ 1818 CK_i486, 1819 CK_WinChipC6, 1820 CK_WinChip2, 1821 CK_C3, 1822 //@} 1823 1824 /// \name i586 1825 /// i586-generation processors, P5 microarchitecture based. 1826 //@{ 1827 CK_i586, 1828 CK_Pentium, 1829 CK_PentiumMMX, 1830 //@} 1831 1832 /// \name i686 1833 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1834 //@{ 1835 CK_i686, 1836 CK_PentiumPro, 1837 CK_Pentium2, 1838 CK_Pentium3, 1839 CK_Pentium3M, 1840 CK_PentiumM, 1841 CK_C3_2, 1842 1843 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1844 /// Clang however has some logic to suport this. 1845 // FIXME: Warn, deprecate, and potentially remove this. 1846 CK_Yonah, 1847 //@} 1848 1849 /// \name Netburst 1850 /// Netburst microarchitecture based processors. 1851 //@{ 1852 CK_Pentium4, 1853 CK_Pentium4M, 1854 CK_Prescott, 1855 CK_Nocona, 1856 //@} 1857 1858 /// \name Core 1859 /// Core microarchitecture based processors. 1860 //@{ 1861 CK_Core2, 1862 1863 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1864 /// codename which GCC no longer accepts as an option to -march, but Clang 1865 /// has some logic for recognizing it. 1866 // FIXME: Warn, deprecate, and potentially remove this. 1867 CK_Penryn, 1868 //@} 1869 1870 /// \name Atom 1871 /// Atom processors 1872 //@{ 1873 CK_Bonnell, 1874 CK_Silvermont, 1875 //@} 1876 1877 /// \name Nehalem 1878 /// Nehalem microarchitecture based processors. 1879 CK_Nehalem, 1880 1881 /// \name Westmere 1882 /// Westmere microarchitecture based processors. 1883 CK_Westmere, 1884 1885 /// \name Sandy Bridge 1886 /// Sandy Bridge microarchitecture based processors. 1887 CK_SandyBridge, 1888 1889 /// \name Ivy Bridge 1890 /// Ivy Bridge microarchitecture based processors. 1891 CK_IvyBridge, 1892 1893 /// \name Haswell 1894 /// Haswell microarchitecture based processors. 1895 CK_Haswell, 1896 1897 /// \name Broadwell 1898 /// Broadwell microarchitecture based processors. 1899 CK_Broadwell, 1900 1901 /// \name Skylake 1902 /// Skylake microarchitecture based processors. 1903 CK_Skylake, 1904 1905 /// \name Knights Landing 1906 /// Knights Landing processor. 1907 CK_KNL, 1908 1909 /// \name K6 1910 /// K6 architecture processors. 1911 //@{ 1912 CK_K6, 1913 CK_K6_2, 1914 CK_K6_3, 1915 //@} 1916 1917 /// \name K7 1918 /// K7 architecture processors. 1919 //@{ 1920 CK_Athlon, 1921 CK_AthlonThunderbird, 1922 CK_Athlon4, 1923 CK_AthlonXP, 1924 CK_AthlonMP, 1925 //@} 1926 1927 /// \name K8 1928 /// K8 architecture processors. 1929 //@{ 1930 CK_Athlon64, 1931 CK_Athlon64SSE3, 1932 CK_AthlonFX, 1933 CK_K8, 1934 CK_K8SSE3, 1935 CK_Opteron, 1936 CK_OpteronSSE3, 1937 CK_AMDFAM10, 1938 //@} 1939 1940 /// \name Bobcat 1941 /// Bobcat architecture processors. 1942 //@{ 1943 CK_BTVER1, 1944 CK_BTVER2, 1945 //@} 1946 1947 /// \name Bulldozer 1948 /// Bulldozer architecture processors. 1949 //@{ 1950 CK_BDVER1, 1951 CK_BDVER2, 1952 CK_BDVER3, 1953 CK_BDVER4, 1954 //@} 1955 1956 /// This specification is deprecated and will be removed in the future. 1957 /// Users should prefer \see CK_K8. 1958 // FIXME: Warn on this when the CPU is set to it. 1959 //@{ 1960 CK_x86_64, 1961 //@} 1962 1963 /// \name Geode 1964 /// Geode processors. 1965 //@{ 1966 CK_Geode 1967 //@} 1968 } CPU; 1969 1970 enum FPMathKind { 1971 FP_Default, 1972 FP_SSE, 1973 FP_387 1974 } FPMath; 1975 1976 public: 1977 X86TargetInfo(const llvm::Triple &Triple) 1978 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1979 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 1980 HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false), 1981 HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false), 1982 HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false), 1983 HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false), 1984 HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false), 1985 HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) { 1986 BigEndian = false; 1987 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1988 } 1989 unsigned getFloatEvalMethod() const override { 1990 // X87 evaluates with 80 bits "long double" precision. 1991 return SSELevel == NoSSE ? 2 : 0; 1992 } 1993 void getTargetBuiltins(const Builtin::Info *&Records, 1994 unsigned &NumRecords) const override { 1995 Records = BuiltinInfo; 1996 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1997 } 1998 void getGCCRegNames(const char * const *&Names, 1999 unsigned &NumNames) const override { 2000 Names = GCCRegNames; 2001 NumNames = llvm::array_lengthof(GCCRegNames); 2002 } 2003 void getGCCRegAliases(const GCCRegAlias *&Aliases, 2004 unsigned &NumAliases) const override { 2005 Aliases = nullptr; 2006 NumAliases = 0; 2007 } 2008 void getGCCAddlRegNames(const AddlRegName *&Names, 2009 unsigned &NumNames) const override { 2010 Names = AddlRegNames; 2011 NumNames = llvm::array_lengthof(AddlRegNames); 2012 } 2013 bool validateAsmConstraint(const char *&Name, 2014 TargetInfo::ConstraintInfo &info) const override; 2015 2016 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2017 2018 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2019 2020 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2021 2022 std::string convertConstraint(const char *&Constraint) const override; 2023 const char *getClobbers() const override { 2024 return "~{dirflag},~{fpsr},~{flags}"; 2025 } 2026 void getTargetDefines(const LangOptions &Opts, 2027 MacroBuilder &Builder) const override; 2028 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2029 bool Enabled); 2030 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2031 bool Enabled); 2032 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2033 bool Enabled); 2034 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2035 StringRef Name, bool Enabled) const override { 2036 setFeatureEnabledImpl(Features, Name, Enabled); 2037 } 2038 // This exists purely to cut down on the number of virtual calls in 2039 // getDefaultFeatures which calls this repeatedly. 2040 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2041 StringRef Name, bool Enabled); 2042 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 2043 bool hasFeature(StringRef Feature) const override; 2044 bool handleTargetFeatures(std::vector<std::string> &Features, 2045 DiagnosticsEngine &Diags) override; 2046 StringRef getABI() const override { 2047 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2048 return "avx"; 2049 else if (getTriple().getArch() == llvm::Triple::x86 && 2050 MMX3DNowLevel == NoMMX3DNow) 2051 return "no-mmx"; 2052 return ""; 2053 } 2054 bool setCPU(const std::string &Name) override { 2055 CPU = llvm::StringSwitch<CPUKind>(Name) 2056 .Case("i386", CK_i386) 2057 .Case("i486", CK_i486) 2058 .Case("winchip-c6", CK_WinChipC6) 2059 .Case("winchip2", CK_WinChip2) 2060 .Case("c3", CK_C3) 2061 .Case("i586", CK_i586) 2062 .Case("pentium", CK_Pentium) 2063 .Case("pentium-mmx", CK_PentiumMMX) 2064 .Case("i686", CK_i686) 2065 .Case("pentiumpro", CK_PentiumPro) 2066 .Case("pentium2", CK_Pentium2) 2067 .Case("pentium3", CK_Pentium3) 2068 .Case("pentium3m", CK_Pentium3M) 2069 .Case("pentium-m", CK_PentiumM) 2070 .Case("c3-2", CK_C3_2) 2071 .Case("yonah", CK_Yonah) 2072 .Case("pentium4", CK_Pentium4) 2073 .Case("pentium4m", CK_Pentium4M) 2074 .Case("prescott", CK_Prescott) 2075 .Case("nocona", CK_Nocona) 2076 .Case("core2", CK_Core2) 2077 .Case("penryn", CK_Penryn) 2078 .Case("bonnell", CK_Bonnell) 2079 .Case("atom", CK_Bonnell) // Legacy name. 2080 .Case("silvermont", CK_Silvermont) 2081 .Case("slm", CK_Silvermont) // Legacy name. 2082 .Case("nehalem", CK_Nehalem) 2083 .Case("corei7", CK_Nehalem) // Legacy name. 2084 .Case("westmere", CK_Westmere) 2085 .Case("sandybridge", CK_SandyBridge) 2086 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2087 .Case("ivybridge", CK_IvyBridge) 2088 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2089 .Case("haswell", CK_Haswell) 2090 .Case("core-avx2", CK_Haswell) // Legacy name. 2091 .Case("broadwell", CK_Broadwell) 2092 .Case("skylake", CK_Skylake) 2093 .Case("skx", CK_Skylake) // Legacy name. 2094 .Case("knl", CK_KNL) 2095 .Case("k6", CK_K6) 2096 .Case("k6-2", CK_K6_2) 2097 .Case("k6-3", CK_K6_3) 2098 .Case("athlon", CK_Athlon) 2099 .Case("athlon-tbird", CK_AthlonThunderbird) 2100 .Case("athlon-4", CK_Athlon4) 2101 .Case("athlon-xp", CK_AthlonXP) 2102 .Case("athlon-mp", CK_AthlonMP) 2103 .Case("athlon64", CK_Athlon64) 2104 .Case("athlon64-sse3", CK_Athlon64SSE3) 2105 .Case("athlon-fx", CK_AthlonFX) 2106 .Case("k8", CK_K8) 2107 .Case("k8-sse3", CK_K8SSE3) 2108 .Case("opteron", CK_Opteron) 2109 .Case("opteron-sse3", CK_OpteronSSE3) 2110 .Case("barcelona", CK_AMDFAM10) 2111 .Case("amdfam10", CK_AMDFAM10) 2112 .Case("btver1", CK_BTVER1) 2113 .Case("btver2", CK_BTVER2) 2114 .Case("bdver1", CK_BDVER1) 2115 .Case("bdver2", CK_BDVER2) 2116 .Case("bdver3", CK_BDVER3) 2117 .Case("bdver4", CK_BDVER4) 2118 .Case("x86-64", CK_x86_64) 2119 .Case("geode", CK_Geode) 2120 .Default(CK_Generic); 2121 2122 // Perform any per-CPU checks necessary to determine if this CPU is 2123 // acceptable. 2124 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2125 // invalid without explaining *why*. 2126 switch (CPU) { 2127 case CK_Generic: 2128 // No processor selected! 2129 return false; 2130 2131 case CK_i386: 2132 case CK_i486: 2133 case CK_WinChipC6: 2134 case CK_WinChip2: 2135 case CK_C3: 2136 case CK_i586: 2137 case CK_Pentium: 2138 case CK_PentiumMMX: 2139 case CK_i686: 2140 case CK_PentiumPro: 2141 case CK_Pentium2: 2142 case CK_Pentium3: 2143 case CK_Pentium3M: 2144 case CK_PentiumM: 2145 case CK_Yonah: 2146 case CK_C3_2: 2147 case CK_Pentium4: 2148 case CK_Pentium4M: 2149 case CK_Prescott: 2150 case CK_K6: 2151 case CK_K6_2: 2152 case CK_K6_3: 2153 case CK_Athlon: 2154 case CK_AthlonThunderbird: 2155 case CK_Athlon4: 2156 case CK_AthlonXP: 2157 case CK_AthlonMP: 2158 case CK_Geode: 2159 // Only accept certain architectures when compiling in 32-bit mode. 2160 if (getTriple().getArch() != llvm::Triple::x86) 2161 return false; 2162 2163 // Fallthrough 2164 case CK_Nocona: 2165 case CK_Core2: 2166 case CK_Penryn: 2167 case CK_Bonnell: 2168 case CK_Silvermont: 2169 case CK_Nehalem: 2170 case CK_Westmere: 2171 case CK_SandyBridge: 2172 case CK_IvyBridge: 2173 case CK_Haswell: 2174 case CK_Broadwell: 2175 case CK_Skylake: 2176 case CK_KNL: 2177 case CK_Athlon64: 2178 case CK_Athlon64SSE3: 2179 case CK_AthlonFX: 2180 case CK_K8: 2181 case CK_K8SSE3: 2182 case CK_Opteron: 2183 case CK_OpteronSSE3: 2184 case CK_AMDFAM10: 2185 case CK_BTVER1: 2186 case CK_BTVER2: 2187 case CK_BDVER1: 2188 case CK_BDVER2: 2189 case CK_BDVER3: 2190 case CK_BDVER4: 2191 case CK_x86_64: 2192 return true; 2193 } 2194 llvm_unreachable("Unhandled CPU kind"); 2195 } 2196 2197 bool setFPMath(StringRef Name) override; 2198 2199 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2200 // We accept all non-ARM calling conventions 2201 return (CC == CC_X86ThisCall || 2202 CC == CC_X86FastCall || 2203 CC == CC_X86StdCall || 2204 CC == CC_X86VectorCall || 2205 CC == CC_C || 2206 CC == CC_X86Pascal || 2207 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2208 } 2209 2210 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2211 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2212 } 2213 }; 2214 2215 bool X86TargetInfo::setFPMath(StringRef Name) { 2216 if (Name == "387") { 2217 FPMath = FP_387; 2218 return true; 2219 } 2220 if (Name == "sse") { 2221 FPMath = FP_SSE; 2222 return true; 2223 } 2224 return false; 2225 } 2226 2227 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2228 // FIXME: This *really* should not be here. 2229 2230 // X86_64 always has SSE2. 2231 if (getTriple().getArch() == llvm::Triple::x86_64) 2232 setFeatureEnabledImpl(Features, "sse2", true); 2233 2234 switch (CPU) { 2235 case CK_Generic: 2236 case CK_i386: 2237 case CK_i486: 2238 case CK_i586: 2239 case CK_Pentium: 2240 case CK_i686: 2241 case CK_PentiumPro: 2242 break; 2243 case CK_PentiumMMX: 2244 case CK_Pentium2: 2245 case CK_K6: 2246 case CK_WinChipC6: 2247 setFeatureEnabledImpl(Features, "mmx", true); 2248 break; 2249 case CK_Pentium3: 2250 case CK_Pentium3M: 2251 case CK_C3_2: 2252 setFeatureEnabledImpl(Features, "sse", true); 2253 break; 2254 case CK_PentiumM: 2255 case CK_Pentium4: 2256 case CK_Pentium4M: 2257 case CK_x86_64: 2258 setFeatureEnabledImpl(Features, "sse2", true); 2259 break; 2260 case CK_Yonah: 2261 case CK_Prescott: 2262 case CK_Nocona: 2263 setFeatureEnabledImpl(Features, "sse3", true); 2264 setFeatureEnabledImpl(Features, "cx16", true); 2265 break; 2266 case CK_Core2: 2267 case CK_Bonnell: 2268 setFeatureEnabledImpl(Features, "ssse3", true); 2269 setFeatureEnabledImpl(Features, "cx16", true); 2270 break; 2271 case CK_Penryn: 2272 setFeatureEnabledImpl(Features, "sse4.1", true); 2273 setFeatureEnabledImpl(Features, "cx16", true); 2274 break; 2275 case CK_Skylake: 2276 setFeatureEnabledImpl(Features, "avx512f", true); 2277 setFeatureEnabledImpl(Features, "avx512cd", true); 2278 setFeatureEnabledImpl(Features, "avx512dq", true); 2279 setFeatureEnabledImpl(Features, "avx512bw", true); 2280 setFeatureEnabledImpl(Features, "avx512vl", true); 2281 // FALLTHROUGH 2282 case CK_Broadwell: 2283 setFeatureEnabledImpl(Features, "rdseed", true); 2284 setFeatureEnabledImpl(Features, "adx", true); 2285 // FALLTHROUGH 2286 case CK_Haswell: 2287 setFeatureEnabledImpl(Features, "avx2", true); 2288 setFeatureEnabledImpl(Features, "lzcnt", true); 2289 setFeatureEnabledImpl(Features, "bmi", true); 2290 setFeatureEnabledImpl(Features, "bmi2", true); 2291 setFeatureEnabledImpl(Features, "rtm", true); 2292 setFeatureEnabledImpl(Features, "fma", true); 2293 // FALLTHROUGH 2294 case CK_IvyBridge: 2295 setFeatureEnabledImpl(Features, "rdrnd", true); 2296 setFeatureEnabledImpl(Features, "f16c", true); 2297 setFeatureEnabledImpl(Features, "fsgsbase", true); 2298 // FALLTHROUGH 2299 case CK_SandyBridge: 2300 setFeatureEnabledImpl(Features, "avx", true); 2301 // FALLTHROUGH 2302 case CK_Westmere: 2303 case CK_Silvermont: 2304 setFeatureEnabledImpl(Features, "aes", true); 2305 setFeatureEnabledImpl(Features, "pclmul", true); 2306 // FALLTHROUGH 2307 case CK_Nehalem: 2308 setFeatureEnabledImpl(Features, "sse4.2", true); 2309 setFeatureEnabledImpl(Features, "cx16", true); 2310 break; 2311 case CK_KNL: 2312 setFeatureEnabledImpl(Features, "avx512f", true); 2313 setFeatureEnabledImpl(Features, "avx512cd", true); 2314 setFeatureEnabledImpl(Features, "avx512er", true); 2315 setFeatureEnabledImpl(Features, "avx512pf", true); 2316 setFeatureEnabledImpl(Features, "rdseed", true); 2317 setFeatureEnabledImpl(Features, "adx", true); 2318 setFeatureEnabledImpl(Features, "lzcnt", true); 2319 setFeatureEnabledImpl(Features, "bmi", true); 2320 setFeatureEnabledImpl(Features, "bmi2", true); 2321 setFeatureEnabledImpl(Features, "rtm", true); 2322 setFeatureEnabledImpl(Features, "fma", true); 2323 setFeatureEnabledImpl(Features, "rdrnd", true); 2324 setFeatureEnabledImpl(Features, "f16c", true); 2325 setFeatureEnabledImpl(Features, "fsgsbase", true); 2326 setFeatureEnabledImpl(Features, "aes", true); 2327 setFeatureEnabledImpl(Features, "pclmul", true); 2328 setFeatureEnabledImpl(Features, "cx16", true); 2329 break; 2330 case CK_K6_2: 2331 case CK_K6_3: 2332 case CK_WinChip2: 2333 case CK_C3: 2334 setFeatureEnabledImpl(Features, "3dnow", true); 2335 break; 2336 case CK_Athlon: 2337 case CK_AthlonThunderbird: 2338 case CK_Geode: 2339 setFeatureEnabledImpl(Features, "3dnowa", true); 2340 break; 2341 case CK_Athlon4: 2342 case CK_AthlonXP: 2343 case CK_AthlonMP: 2344 setFeatureEnabledImpl(Features, "sse", true); 2345 setFeatureEnabledImpl(Features, "3dnowa", true); 2346 break; 2347 case CK_K8: 2348 case CK_Opteron: 2349 case CK_Athlon64: 2350 case CK_AthlonFX: 2351 setFeatureEnabledImpl(Features, "sse2", true); 2352 setFeatureEnabledImpl(Features, "3dnowa", true); 2353 break; 2354 case CK_AMDFAM10: 2355 setFeatureEnabledImpl(Features, "sse4a", true); 2356 setFeatureEnabledImpl(Features, "lzcnt", true); 2357 setFeatureEnabledImpl(Features, "popcnt", true); 2358 // FALLTHROUGH 2359 case CK_K8SSE3: 2360 case CK_OpteronSSE3: 2361 case CK_Athlon64SSE3: 2362 setFeatureEnabledImpl(Features, "sse3", true); 2363 setFeatureEnabledImpl(Features, "3dnowa", true); 2364 break; 2365 case CK_BTVER2: 2366 setFeatureEnabledImpl(Features, "avx", true); 2367 setFeatureEnabledImpl(Features, "aes", true); 2368 setFeatureEnabledImpl(Features, "pclmul", true); 2369 setFeatureEnabledImpl(Features, "bmi", true); 2370 setFeatureEnabledImpl(Features, "f16c", true); 2371 // FALLTHROUGH 2372 case CK_BTVER1: 2373 setFeatureEnabledImpl(Features, "ssse3", true); 2374 setFeatureEnabledImpl(Features, "sse4a", true); 2375 setFeatureEnabledImpl(Features, "lzcnt", true); 2376 setFeatureEnabledImpl(Features, "popcnt", true); 2377 setFeatureEnabledImpl(Features, "prfchw", true); 2378 setFeatureEnabledImpl(Features, "cx16", true); 2379 break; 2380 case CK_BDVER4: 2381 setFeatureEnabledImpl(Features, "avx2", true); 2382 setFeatureEnabledImpl(Features, "bmi2", true); 2383 // FALLTHROUGH 2384 case CK_BDVER3: 2385 setFeatureEnabledImpl(Features, "fsgsbase", true); 2386 // FALLTHROUGH 2387 case CK_BDVER2: 2388 setFeatureEnabledImpl(Features, "bmi", true); 2389 setFeatureEnabledImpl(Features, "fma", true); 2390 setFeatureEnabledImpl(Features, "f16c", true); 2391 setFeatureEnabledImpl(Features, "tbm", true); 2392 // FALLTHROUGH 2393 case CK_BDVER1: 2394 // xop implies avx, sse4a and fma4. 2395 setFeatureEnabledImpl(Features, "xop", true); 2396 setFeatureEnabledImpl(Features, "lzcnt", true); 2397 setFeatureEnabledImpl(Features, "aes", true); 2398 setFeatureEnabledImpl(Features, "pclmul", true); 2399 setFeatureEnabledImpl(Features, "prfchw", true); 2400 setFeatureEnabledImpl(Features, "cx16", true); 2401 break; 2402 } 2403 } 2404 2405 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2406 X86SSEEnum Level, bool Enabled) { 2407 if (Enabled) { 2408 switch (Level) { 2409 case AVX512F: 2410 Features["avx512f"] = true; 2411 case AVX2: 2412 Features["avx2"] = true; 2413 case AVX: 2414 Features["avx"] = true; 2415 case SSE42: 2416 Features["sse4.2"] = true; 2417 case SSE41: 2418 Features["sse4.1"] = true; 2419 case SSSE3: 2420 Features["ssse3"] = true; 2421 case SSE3: 2422 Features["sse3"] = true; 2423 case SSE2: 2424 Features["sse2"] = true; 2425 case SSE1: 2426 Features["sse"] = true; 2427 case NoSSE: 2428 break; 2429 } 2430 return; 2431 } 2432 2433 switch (Level) { 2434 case NoSSE: 2435 case SSE1: 2436 Features["sse"] = false; 2437 case SSE2: 2438 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2439 Features["sha"] = false; 2440 case SSE3: 2441 Features["sse3"] = false; 2442 setXOPLevel(Features, NoXOP, false); 2443 case SSSE3: 2444 Features["ssse3"] = false; 2445 case SSE41: 2446 Features["sse4.1"] = false; 2447 case SSE42: 2448 Features["sse4.2"] = false; 2449 case AVX: 2450 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2451 setXOPLevel(Features, FMA4, false); 2452 case AVX2: 2453 Features["avx2"] = false; 2454 case AVX512F: 2455 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2456 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2457 Features["avx512vl"] = false; 2458 } 2459 } 2460 2461 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2462 MMX3DNowEnum Level, bool Enabled) { 2463 if (Enabled) { 2464 switch (Level) { 2465 case AMD3DNowAthlon: 2466 Features["3dnowa"] = true; 2467 case AMD3DNow: 2468 Features["3dnow"] = true; 2469 case MMX: 2470 Features["mmx"] = true; 2471 case NoMMX3DNow: 2472 break; 2473 } 2474 return; 2475 } 2476 2477 switch (Level) { 2478 case NoMMX3DNow: 2479 case MMX: 2480 Features["mmx"] = false; 2481 case AMD3DNow: 2482 Features["3dnow"] = false; 2483 case AMD3DNowAthlon: 2484 Features["3dnowa"] = false; 2485 } 2486 } 2487 2488 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2489 bool Enabled) { 2490 if (Enabled) { 2491 switch (Level) { 2492 case XOP: 2493 Features["xop"] = true; 2494 case FMA4: 2495 Features["fma4"] = true; 2496 setSSELevel(Features, AVX, true); 2497 case SSE4A: 2498 Features["sse4a"] = true; 2499 setSSELevel(Features, SSE3, true); 2500 case NoXOP: 2501 break; 2502 } 2503 return; 2504 } 2505 2506 switch (Level) { 2507 case NoXOP: 2508 case SSE4A: 2509 Features["sse4a"] = false; 2510 case FMA4: 2511 Features["fma4"] = false; 2512 case XOP: 2513 Features["xop"] = false; 2514 } 2515 } 2516 2517 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2518 StringRef Name, bool Enabled) { 2519 // FIXME: This *really* should not be here. We need some way of translating 2520 // options into llvm subtarget features. 2521 if (Name == "sse4") 2522 Name = "sse4.2"; 2523 2524 Features[Name] = Enabled; 2525 2526 if (Name == "mmx") { 2527 setMMXLevel(Features, MMX, Enabled); 2528 } else if (Name == "sse") { 2529 setSSELevel(Features, SSE1, Enabled); 2530 } else if (Name == "sse2") { 2531 setSSELevel(Features, SSE2, Enabled); 2532 } else if (Name == "sse3") { 2533 setSSELevel(Features, SSE3, Enabled); 2534 } else if (Name == "ssse3") { 2535 setSSELevel(Features, SSSE3, Enabled); 2536 } else if (Name == "sse4.2") { 2537 setSSELevel(Features, SSE42, Enabled); 2538 } else if (Name == "sse4.1") { 2539 setSSELevel(Features, SSE41, Enabled); 2540 } else if (Name == "3dnow") { 2541 setMMXLevel(Features, AMD3DNow, Enabled); 2542 } else if (Name == "3dnowa") { 2543 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2544 } else if (Name == "aes") { 2545 if (Enabled) 2546 setSSELevel(Features, SSE2, Enabled); 2547 } else if (Name == "pclmul") { 2548 if (Enabled) 2549 setSSELevel(Features, SSE2, Enabled); 2550 } else if (Name == "avx") { 2551 setSSELevel(Features, AVX, Enabled); 2552 } else if (Name == "avx2") { 2553 setSSELevel(Features, AVX2, Enabled); 2554 } else if (Name == "avx512f") { 2555 setSSELevel(Features, AVX512F, Enabled); 2556 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2557 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2558 if (Enabled) 2559 setSSELevel(Features, AVX512F, Enabled); 2560 } else if (Name == "fma") { 2561 if (Enabled) 2562 setSSELevel(Features, AVX, Enabled); 2563 } else if (Name == "fma4") { 2564 setXOPLevel(Features, FMA4, Enabled); 2565 } else if (Name == "xop") { 2566 setXOPLevel(Features, XOP, Enabled); 2567 } else if (Name == "sse4a") { 2568 setXOPLevel(Features, SSE4A, Enabled); 2569 } else if (Name == "f16c") { 2570 if (Enabled) 2571 setSSELevel(Features, AVX, Enabled); 2572 } else if (Name == "sha") { 2573 if (Enabled) 2574 setSSELevel(Features, SSE2, Enabled); 2575 } 2576 } 2577 2578 /// handleTargetFeatures - Perform initialization based on the user 2579 /// configured set of features. 2580 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2581 DiagnosticsEngine &Diags) { 2582 // Remember the maximum enabled sselevel. 2583 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2584 // Ignore disabled features. 2585 if (Features[i][0] == '-') 2586 continue; 2587 2588 StringRef Feature = StringRef(Features[i]).substr(1); 2589 2590 if (Feature == "aes") { 2591 HasAES = true; 2592 continue; 2593 } 2594 2595 if (Feature == "pclmul") { 2596 HasPCLMUL = true; 2597 continue; 2598 } 2599 2600 if (Feature == "lzcnt") { 2601 HasLZCNT = true; 2602 continue; 2603 } 2604 2605 if (Feature == "rdrnd") { 2606 HasRDRND = true; 2607 continue; 2608 } 2609 2610 if (Feature == "fsgsbase") { 2611 HasFSGSBASE = true; 2612 continue; 2613 } 2614 2615 if (Feature == "bmi") { 2616 HasBMI = true; 2617 continue; 2618 } 2619 2620 if (Feature == "bmi2") { 2621 HasBMI2 = true; 2622 continue; 2623 } 2624 2625 if (Feature == "popcnt") { 2626 HasPOPCNT = true; 2627 continue; 2628 } 2629 2630 if (Feature == "rtm") { 2631 HasRTM = true; 2632 continue; 2633 } 2634 2635 if (Feature == "prfchw") { 2636 HasPRFCHW = true; 2637 continue; 2638 } 2639 2640 if (Feature == "rdseed") { 2641 HasRDSEED = true; 2642 continue; 2643 } 2644 2645 if (Feature == "adx") { 2646 HasADX = true; 2647 continue; 2648 } 2649 2650 if (Feature == "tbm") { 2651 HasTBM = true; 2652 continue; 2653 } 2654 2655 if (Feature == "fma") { 2656 HasFMA = true; 2657 continue; 2658 } 2659 2660 if (Feature == "f16c") { 2661 HasF16C = true; 2662 continue; 2663 } 2664 2665 if (Feature == "avx512cd") { 2666 HasAVX512CD = true; 2667 continue; 2668 } 2669 2670 if (Feature == "avx512er") { 2671 HasAVX512ER = true; 2672 continue; 2673 } 2674 2675 if (Feature == "avx512pf") { 2676 HasAVX512PF = true; 2677 continue; 2678 } 2679 2680 if (Feature == "avx512dq") { 2681 HasAVX512DQ = true; 2682 continue; 2683 } 2684 2685 if (Feature == "avx512bw") { 2686 HasAVX512BW = true; 2687 continue; 2688 } 2689 2690 if (Feature == "avx512vl") { 2691 HasAVX512VL = true; 2692 continue; 2693 } 2694 2695 if (Feature == "sha") { 2696 HasSHA = true; 2697 continue; 2698 } 2699 2700 if (Feature == "cx16") { 2701 HasCX16 = true; 2702 continue; 2703 } 2704 2705 assert(Features[i][0] == '+' && "Invalid target feature!"); 2706 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2707 .Case("avx512f", AVX512F) 2708 .Case("avx2", AVX2) 2709 .Case("avx", AVX) 2710 .Case("sse4.2", SSE42) 2711 .Case("sse4.1", SSE41) 2712 .Case("ssse3", SSSE3) 2713 .Case("sse3", SSE3) 2714 .Case("sse2", SSE2) 2715 .Case("sse", SSE1) 2716 .Default(NoSSE); 2717 SSELevel = std::max(SSELevel, Level); 2718 2719 MMX3DNowEnum ThreeDNowLevel = 2720 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2721 .Case("3dnowa", AMD3DNowAthlon) 2722 .Case("3dnow", AMD3DNow) 2723 .Case("mmx", MMX) 2724 .Default(NoMMX3DNow); 2725 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2726 2727 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2728 .Case("xop", XOP) 2729 .Case("fma4", FMA4) 2730 .Case("sse4a", SSE4A) 2731 .Default(NoXOP); 2732 XOPLevel = std::max(XOPLevel, XLevel); 2733 } 2734 2735 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2736 // Can't do this earlier because we need to be able to explicitly enable 2737 // popcnt and still disable sse4.2. 2738 if (!HasPOPCNT && SSELevel >= SSE42 && 2739 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2740 HasPOPCNT = true; 2741 Features.push_back("+popcnt"); 2742 } 2743 2744 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2745 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2746 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2747 HasPRFCHW = true; 2748 Features.push_back("+prfchw"); 2749 } 2750 2751 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2752 // matches the selected sse level. 2753 if (FPMath == FP_SSE && SSELevel < SSE1) { 2754 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2755 return false; 2756 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2757 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2758 return false; 2759 } 2760 2761 // Don't tell the backend if we're turning off mmx; it will end up disabling 2762 // SSE, which we don't want. 2763 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2764 // then enable MMX. 2765 std::vector<std::string>::iterator it; 2766 it = std::find(Features.begin(), Features.end(), "-mmx"); 2767 if (it != Features.end()) 2768 Features.erase(it); 2769 else if (SSELevel > NoSSE) 2770 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2771 return true; 2772 } 2773 2774 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2775 /// definitions for this particular subtarget. 2776 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2777 MacroBuilder &Builder) const { 2778 // Target identification. 2779 if (getTriple().getArch() == llvm::Triple::x86_64) { 2780 Builder.defineMacro("__amd64__"); 2781 Builder.defineMacro("__amd64"); 2782 Builder.defineMacro("__x86_64"); 2783 Builder.defineMacro("__x86_64__"); 2784 if (getTriple().getArchName() == "x86_64h") { 2785 Builder.defineMacro("__x86_64h"); 2786 Builder.defineMacro("__x86_64h__"); 2787 } 2788 } else { 2789 DefineStd(Builder, "i386", Opts); 2790 } 2791 2792 // Subtarget options. 2793 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2794 // truly should be based on -mtune options. 2795 switch (CPU) { 2796 case CK_Generic: 2797 break; 2798 case CK_i386: 2799 // The rest are coming from the i386 define above. 2800 Builder.defineMacro("__tune_i386__"); 2801 break; 2802 case CK_i486: 2803 case CK_WinChipC6: 2804 case CK_WinChip2: 2805 case CK_C3: 2806 defineCPUMacros(Builder, "i486"); 2807 break; 2808 case CK_PentiumMMX: 2809 Builder.defineMacro("__pentium_mmx__"); 2810 Builder.defineMacro("__tune_pentium_mmx__"); 2811 // Fallthrough 2812 case CK_i586: 2813 case CK_Pentium: 2814 defineCPUMacros(Builder, "i586"); 2815 defineCPUMacros(Builder, "pentium"); 2816 break; 2817 case CK_Pentium3: 2818 case CK_Pentium3M: 2819 case CK_PentiumM: 2820 Builder.defineMacro("__tune_pentium3__"); 2821 // Fallthrough 2822 case CK_Pentium2: 2823 case CK_C3_2: 2824 Builder.defineMacro("__tune_pentium2__"); 2825 // Fallthrough 2826 case CK_PentiumPro: 2827 Builder.defineMacro("__tune_i686__"); 2828 Builder.defineMacro("__tune_pentiumpro__"); 2829 // Fallthrough 2830 case CK_i686: 2831 Builder.defineMacro("__i686"); 2832 Builder.defineMacro("__i686__"); 2833 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2834 Builder.defineMacro("__pentiumpro"); 2835 Builder.defineMacro("__pentiumpro__"); 2836 break; 2837 case CK_Pentium4: 2838 case CK_Pentium4M: 2839 defineCPUMacros(Builder, "pentium4"); 2840 break; 2841 case CK_Yonah: 2842 case CK_Prescott: 2843 case CK_Nocona: 2844 defineCPUMacros(Builder, "nocona"); 2845 break; 2846 case CK_Core2: 2847 case CK_Penryn: 2848 defineCPUMacros(Builder, "core2"); 2849 break; 2850 case CK_Bonnell: 2851 defineCPUMacros(Builder, "atom"); 2852 break; 2853 case CK_Silvermont: 2854 defineCPUMacros(Builder, "slm"); 2855 break; 2856 case CK_Nehalem: 2857 case CK_Westmere: 2858 case CK_SandyBridge: 2859 case CK_IvyBridge: 2860 case CK_Haswell: 2861 case CK_Broadwell: 2862 // FIXME: Historically, we defined this legacy name, it would be nice to 2863 // remove it at some point. We've never exposed fine-grained names for 2864 // recent primary x86 CPUs, and we should keep it that way. 2865 defineCPUMacros(Builder, "corei7"); 2866 break; 2867 case CK_Skylake: 2868 // FIXME: Historically, we defined this legacy name, it would be nice to 2869 // remove it at some point. This is the only fine-grained CPU macro in the 2870 // main intel CPU line, and it would be better to not have these and force 2871 // people to use ISA macros. 2872 defineCPUMacros(Builder, "skx"); 2873 break; 2874 case CK_KNL: 2875 defineCPUMacros(Builder, "knl"); 2876 break; 2877 case CK_K6_2: 2878 Builder.defineMacro("__k6_2__"); 2879 Builder.defineMacro("__tune_k6_2__"); 2880 // Fallthrough 2881 case CK_K6_3: 2882 if (CPU != CK_K6_2) { // In case of fallthrough 2883 // FIXME: GCC may be enabling these in cases where some other k6 2884 // architecture is specified but -m3dnow is explicitly provided. The 2885 // exact semantics need to be determined and emulated here. 2886 Builder.defineMacro("__k6_3__"); 2887 Builder.defineMacro("__tune_k6_3__"); 2888 } 2889 // Fallthrough 2890 case CK_K6: 2891 defineCPUMacros(Builder, "k6"); 2892 break; 2893 case CK_Athlon: 2894 case CK_AthlonThunderbird: 2895 case CK_Athlon4: 2896 case CK_AthlonXP: 2897 case CK_AthlonMP: 2898 defineCPUMacros(Builder, "athlon"); 2899 if (SSELevel != NoSSE) { 2900 Builder.defineMacro("__athlon_sse__"); 2901 Builder.defineMacro("__tune_athlon_sse__"); 2902 } 2903 break; 2904 case CK_K8: 2905 case CK_K8SSE3: 2906 case CK_x86_64: 2907 case CK_Opteron: 2908 case CK_OpteronSSE3: 2909 case CK_Athlon64: 2910 case CK_Athlon64SSE3: 2911 case CK_AthlonFX: 2912 defineCPUMacros(Builder, "k8"); 2913 break; 2914 case CK_AMDFAM10: 2915 defineCPUMacros(Builder, "amdfam10"); 2916 break; 2917 case CK_BTVER1: 2918 defineCPUMacros(Builder, "btver1"); 2919 break; 2920 case CK_BTVER2: 2921 defineCPUMacros(Builder, "btver2"); 2922 break; 2923 case CK_BDVER1: 2924 defineCPUMacros(Builder, "bdver1"); 2925 break; 2926 case CK_BDVER2: 2927 defineCPUMacros(Builder, "bdver2"); 2928 break; 2929 case CK_BDVER3: 2930 defineCPUMacros(Builder, "bdver3"); 2931 break; 2932 case CK_BDVER4: 2933 defineCPUMacros(Builder, "bdver4"); 2934 break; 2935 case CK_Geode: 2936 defineCPUMacros(Builder, "geode"); 2937 break; 2938 } 2939 2940 // Target properties. 2941 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2942 2943 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2944 // functions in glibc header files that use FP Stack inline asm which the 2945 // backend can't deal with (PR879). 2946 Builder.defineMacro("__NO_MATH_INLINES"); 2947 2948 if (HasAES) 2949 Builder.defineMacro("__AES__"); 2950 2951 if (HasPCLMUL) 2952 Builder.defineMacro("__PCLMUL__"); 2953 2954 if (HasLZCNT) 2955 Builder.defineMacro("__LZCNT__"); 2956 2957 if (HasRDRND) 2958 Builder.defineMacro("__RDRND__"); 2959 2960 if (HasFSGSBASE) 2961 Builder.defineMacro("__FSGSBASE__"); 2962 2963 if (HasBMI) 2964 Builder.defineMacro("__BMI__"); 2965 2966 if (HasBMI2) 2967 Builder.defineMacro("__BMI2__"); 2968 2969 if (HasPOPCNT) 2970 Builder.defineMacro("__POPCNT__"); 2971 2972 if (HasRTM) 2973 Builder.defineMacro("__RTM__"); 2974 2975 if (HasPRFCHW) 2976 Builder.defineMacro("__PRFCHW__"); 2977 2978 if (HasRDSEED) 2979 Builder.defineMacro("__RDSEED__"); 2980 2981 if (HasADX) 2982 Builder.defineMacro("__ADX__"); 2983 2984 if (HasTBM) 2985 Builder.defineMacro("__TBM__"); 2986 2987 switch (XOPLevel) { 2988 case XOP: 2989 Builder.defineMacro("__XOP__"); 2990 case FMA4: 2991 Builder.defineMacro("__FMA4__"); 2992 case SSE4A: 2993 Builder.defineMacro("__SSE4A__"); 2994 case NoXOP: 2995 break; 2996 } 2997 2998 if (HasFMA) 2999 Builder.defineMacro("__FMA__"); 3000 3001 if (HasF16C) 3002 Builder.defineMacro("__F16C__"); 3003 3004 if (HasAVX512CD) 3005 Builder.defineMacro("__AVX512CD__"); 3006 if (HasAVX512ER) 3007 Builder.defineMacro("__AVX512ER__"); 3008 if (HasAVX512PF) 3009 Builder.defineMacro("__AVX512PF__"); 3010 if (HasAVX512DQ) 3011 Builder.defineMacro("__AVX512DQ__"); 3012 if (HasAVX512BW) 3013 Builder.defineMacro("__AVX512BW__"); 3014 if (HasAVX512VL) 3015 Builder.defineMacro("__AVX512VL__"); 3016 3017 if (HasSHA) 3018 Builder.defineMacro("__SHA__"); 3019 3020 if (HasCX16) 3021 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3022 3023 // Each case falls through to the previous one here. 3024 switch (SSELevel) { 3025 case AVX512F: 3026 Builder.defineMacro("__AVX512F__"); 3027 case AVX2: 3028 Builder.defineMacro("__AVX2__"); 3029 case AVX: 3030 Builder.defineMacro("__AVX__"); 3031 case SSE42: 3032 Builder.defineMacro("__SSE4_2__"); 3033 case SSE41: 3034 Builder.defineMacro("__SSE4_1__"); 3035 case SSSE3: 3036 Builder.defineMacro("__SSSE3__"); 3037 case SSE3: 3038 Builder.defineMacro("__SSE3__"); 3039 case SSE2: 3040 Builder.defineMacro("__SSE2__"); 3041 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3042 case SSE1: 3043 Builder.defineMacro("__SSE__"); 3044 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3045 case NoSSE: 3046 break; 3047 } 3048 3049 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3050 switch (SSELevel) { 3051 case AVX512F: 3052 case AVX2: 3053 case AVX: 3054 case SSE42: 3055 case SSE41: 3056 case SSSE3: 3057 case SSE3: 3058 case SSE2: 3059 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3060 break; 3061 case SSE1: 3062 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3063 break; 3064 default: 3065 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3066 } 3067 } 3068 3069 // Each case falls through to the previous one here. 3070 switch (MMX3DNowLevel) { 3071 case AMD3DNowAthlon: 3072 Builder.defineMacro("__3dNOW_A__"); 3073 case AMD3DNow: 3074 Builder.defineMacro("__3dNOW__"); 3075 case MMX: 3076 Builder.defineMacro("__MMX__"); 3077 case NoMMX3DNow: 3078 break; 3079 } 3080 3081 if (CPU >= CK_i486) { 3082 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3083 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3084 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3085 } 3086 if (CPU >= CK_i586) 3087 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3088 } 3089 3090 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3091 return llvm::StringSwitch<bool>(Feature) 3092 .Case("aes", HasAES) 3093 .Case("avx", SSELevel >= AVX) 3094 .Case("avx2", SSELevel >= AVX2) 3095 .Case("avx512f", SSELevel >= AVX512F) 3096 .Case("avx512cd", HasAVX512CD) 3097 .Case("avx512er", HasAVX512ER) 3098 .Case("avx512pf", HasAVX512PF) 3099 .Case("avx512dq", HasAVX512DQ) 3100 .Case("avx512bw", HasAVX512BW) 3101 .Case("avx512vl", HasAVX512VL) 3102 .Case("bmi", HasBMI) 3103 .Case("bmi2", HasBMI2) 3104 .Case("cx16", HasCX16) 3105 .Case("f16c", HasF16C) 3106 .Case("fma", HasFMA) 3107 .Case("fma4", XOPLevel >= FMA4) 3108 .Case("fsgsbase", HasFSGSBASE) 3109 .Case("lzcnt", HasLZCNT) 3110 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3111 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3112 .Case("mmx", MMX3DNowLevel >= MMX) 3113 .Case("pclmul", HasPCLMUL) 3114 .Case("popcnt", HasPOPCNT) 3115 .Case("prfchw", HasPRFCHW) 3116 .Case("rdrnd", HasRDRND) 3117 .Case("rdseed", HasRDSEED) 3118 .Case("rtm", HasRTM) 3119 .Case("sha", HasSHA) 3120 .Case("sse", SSELevel >= SSE1) 3121 .Case("sse2", SSELevel >= SSE2) 3122 .Case("sse3", SSELevel >= SSE3) 3123 .Case("ssse3", SSELevel >= SSSE3) 3124 .Case("sse4.1", SSELevel >= SSE41) 3125 .Case("sse4.2", SSELevel >= SSE42) 3126 .Case("sse4a", XOPLevel >= SSE4A) 3127 .Case("tbm", HasTBM) 3128 .Case("x86", true) 3129 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3130 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3131 .Case("xop", XOPLevel >= XOP) 3132 .Default(false); 3133 } 3134 3135 bool 3136 X86TargetInfo::validateAsmConstraint(const char *&Name, 3137 TargetInfo::ConstraintInfo &Info) const { 3138 switch (*Name) { 3139 default: return false; 3140 case 'I': 3141 Info.setRequiresImmediate(0, 31); 3142 return true; 3143 case 'J': 3144 Info.setRequiresImmediate(0, 63); 3145 return true; 3146 case 'K': 3147 Info.setRequiresImmediate(-128, 127); 3148 return true; 3149 case 'L': 3150 // FIXME: properly analyze this constraint: 3151 // must be one of 0xff, 0xffff, or 0xffffffff 3152 return true; 3153 case 'M': 3154 Info.setRequiresImmediate(0, 3); 3155 return true; 3156 case 'N': 3157 Info.setRequiresImmediate(0, 255); 3158 return true; 3159 case 'O': 3160 Info.setRequiresImmediate(0, 127); 3161 return true; 3162 case 'Y': // first letter of a pair: 3163 switch (*(Name+1)) { 3164 default: return false; 3165 case '0': // First SSE register. 3166 case 't': // Any SSE register, when SSE2 is enabled. 3167 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3168 case 'm': // any MMX register, when inter-unit moves enabled. 3169 break; // falls through to setAllowsRegister. 3170 } 3171 case 'f': // any x87 floating point stack register. 3172 // Constraint 'f' cannot be used for output operands. 3173 if (Info.ConstraintStr[0] == '=') 3174 return false; 3175 3176 Info.setAllowsRegister(); 3177 return true; 3178 case 'a': // eax. 3179 case 'b': // ebx. 3180 case 'c': // ecx. 3181 case 'd': // edx. 3182 case 'S': // esi. 3183 case 'D': // edi. 3184 case 'A': // edx:eax. 3185 case 't': // top of floating point stack. 3186 case 'u': // second from top of floating point stack. 3187 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3188 case 'y': // Any MMX register. 3189 case 'x': // Any SSE register. 3190 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3191 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3192 case 'l': // "Index" registers: any general register that can be used as an 3193 // index in a base+index memory access. 3194 Info.setAllowsRegister(); 3195 return true; 3196 case 'C': // SSE floating point constant. 3197 case 'G': // x87 floating point constant. 3198 case 'e': // 32-bit signed integer constant for use with zero-extending 3199 // x86_64 instructions. 3200 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3201 // x86_64 instructions. 3202 return true; 3203 } 3204 } 3205 3206 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3207 unsigned Size) const { 3208 // Strip off constraint modifiers. 3209 while (Constraint[0] == '=' || 3210 Constraint[0] == '+' || 3211 Constraint[0] == '&') 3212 Constraint = Constraint.substr(1); 3213 3214 return validateOperandSize(Constraint, Size); 3215 } 3216 3217 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3218 unsigned Size) const { 3219 return validateOperandSize(Constraint, Size); 3220 } 3221 3222 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3223 unsigned Size) const { 3224 switch (Constraint[0]) { 3225 default: break; 3226 case 'y': 3227 return Size <= 64; 3228 case 'f': 3229 case 't': 3230 case 'u': 3231 return Size <= 128; 3232 case 'x': 3233 // 256-bit ymm registers can be used if target supports AVX. 3234 return Size <= (SSELevel >= AVX ? 256U : 128U); 3235 } 3236 3237 return true; 3238 } 3239 3240 std::string 3241 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3242 switch (*Constraint) { 3243 case 'a': return std::string("{ax}"); 3244 case 'b': return std::string("{bx}"); 3245 case 'c': return std::string("{cx}"); 3246 case 'd': return std::string("{dx}"); 3247 case 'S': return std::string("{si}"); 3248 case 'D': return std::string("{di}"); 3249 case 'p': // address 3250 return std::string("im"); 3251 case 't': // top of floating point stack. 3252 return std::string("{st}"); 3253 case 'u': // second from top of floating point stack. 3254 return std::string("{st(1)}"); // second from top of floating point stack. 3255 default: 3256 return std::string(1, *Constraint); 3257 } 3258 } 3259 } // end anonymous namespace 3260 3261 namespace { 3262 // X86-32 generic target 3263 class X86_32TargetInfo : public X86TargetInfo { 3264 public: 3265 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3266 DoubleAlign = LongLongAlign = 32; 3267 LongDoubleWidth = 96; 3268 LongDoubleAlign = 32; 3269 SuitableAlign = 128; 3270 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3271 SizeType = UnsignedInt; 3272 PtrDiffType = SignedInt; 3273 IntPtrType = SignedInt; 3274 RegParmMax = 3; 3275 3276 // Use fpret for all types. 3277 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3278 (1 << TargetInfo::Double) | 3279 (1 << TargetInfo::LongDouble)); 3280 3281 // x86-32 has atomics up to 8 bytes 3282 // FIXME: Check that we actually have cmpxchg8b before setting 3283 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3284 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3285 } 3286 BuiltinVaListKind getBuiltinVaListKind() const override { 3287 return TargetInfo::CharPtrBuiltinVaList; 3288 } 3289 3290 int getEHDataRegisterNumber(unsigned RegNo) const override { 3291 if (RegNo == 0) return 0; 3292 if (RegNo == 1) return 2; 3293 return -1; 3294 } 3295 bool validateOperandSize(StringRef Constraint, 3296 unsigned Size) const override { 3297 switch (Constraint[0]) { 3298 default: break; 3299 case 'R': 3300 case 'q': 3301 case 'Q': 3302 case 'a': 3303 case 'b': 3304 case 'c': 3305 case 'd': 3306 case 'S': 3307 case 'D': 3308 return Size <= 32; 3309 case 'A': 3310 return Size <= 64; 3311 } 3312 3313 return X86TargetInfo::validateOperandSize(Constraint, Size); 3314 } 3315 }; 3316 } // end anonymous namespace 3317 3318 namespace { 3319 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3320 public: 3321 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3322 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3323 3324 unsigned getFloatEvalMethod() const override { 3325 unsigned Major, Minor, Micro; 3326 getTriple().getOSVersion(Major, Minor, Micro); 3327 // New NetBSD uses the default rounding mode. 3328 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3329 return X86_32TargetInfo::getFloatEvalMethod(); 3330 // NetBSD before 6.99.26 defaults to "double" rounding. 3331 return 1; 3332 } 3333 }; 3334 } // end anonymous namespace 3335 3336 namespace { 3337 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3338 public: 3339 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3340 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3341 SizeType = UnsignedLong; 3342 IntPtrType = SignedLong; 3343 PtrDiffType = SignedLong; 3344 } 3345 }; 3346 } // end anonymous namespace 3347 3348 namespace { 3349 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3350 public: 3351 BitrigI386TargetInfo(const llvm::Triple &Triple) 3352 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3353 SizeType = UnsignedLong; 3354 IntPtrType = SignedLong; 3355 PtrDiffType = SignedLong; 3356 } 3357 }; 3358 } // end anonymous namespace 3359 3360 namespace { 3361 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3362 public: 3363 DarwinI386TargetInfo(const llvm::Triple &Triple) 3364 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3365 LongDoubleWidth = 128; 3366 LongDoubleAlign = 128; 3367 SuitableAlign = 128; 3368 MaxVectorAlign = 256; 3369 SizeType = UnsignedLong; 3370 IntPtrType = SignedLong; 3371 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3372 HasAlignMac68kSupport = true; 3373 } 3374 3375 }; 3376 } // end anonymous namespace 3377 3378 namespace { 3379 // x86-32 Windows target 3380 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3381 public: 3382 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3383 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3384 WCharType = UnsignedShort; 3385 DoubleAlign = LongLongAlign = 64; 3386 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3387 } 3388 void getTargetDefines(const LangOptions &Opts, 3389 MacroBuilder &Builder) const override { 3390 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3391 } 3392 }; 3393 3394 // x86-32 Windows Visual Studio target 3395 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3396 public: 3397 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3398 : WindowsX86_32TargetInfo(Triple) { 3399 LongDoubleWidth = LongDoubleAlign = 64; 3400 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3401 } 3402 void getTargetDefines(const LangOptions &Opts, 3403 MacroBuilder &Builder) const override { 3404 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3405 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3406 // The value of the following reflects processor type. 3407 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3408 // We lost the original triple, so we use the default. 3409 Builder.defineMacro("_M_IX86", "600"); 3410 } 3411 }; 3412 } // end anonymous namespace 3413 3414 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3415 Builder.defineMacro("__MSVCRT__"); 3416 Builder.defineMacro("__MINGW32__"); 3417 3418 // Mingw defines __declspec(a) to __attribute__((a)). Clang supports 3419 // __declspec natively under -fms-extensions, but we define a no-op __declspec 3420 // macro anyway for pre-processor compatibility. 3421 if (Opts.MicrosoftExt) 3422 Builder.defineMacro("__declspec", "__declspec"); 3423 else 3424 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3425 3426 if (!Opts.MicrosoftExt) { 3427 // Provide macros for all the calling convention keywords. Provide both 3428 // single and double underscore prefixed variants. These are available on 3429 // x64 as well as x86, even though they have no effect. 3430 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3431 for (const char *CC : CCs) { 3432 std::string GCCSpelling = "__attribute__((__"; 3433 GCCSpelling += CC; 3434 GCCSpelling += "__))"; 3435 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3436 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3437 } 3438 } 3439 } 3440 3441 namespace { 3442 // x86-32 MinGW target 3443 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3444 public: 3445 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3446 : WindowsX86_32TargetInfo(Triple) {} 3447 void getTargetDefines(const LangOptions &Opts, 3448 MacroBuilder &Builder) const override { 3449 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3450 DefineStd(Builder, "WIN32", Opts); 3451 DefineStd(Builder, "WINNT", Opts); 3452 Builder.defineMacro("_X86_"); 3453 addMinGWDefines(Opts, Builder); 3454 } 3455 }; 3456 } // end anonymous namespace 3457 3458 namespace { 3459 // x86-32 Cygwin target 3460 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3461 public: 3462 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3463 : X86_32TargetInfo(Triple) { 3464 TLSSupported = false; 3465 WCharType = UnsignedShort; 3466 DoubleAlign = LongLongAlign = 64; 3467 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3468 } 3469 void getTargetDefines(const LangOptions &Opts, 3470 MacroBuilder &Builder) const override { 3471 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3472 Builder.defineMacro("_X86_"); 3473 Builder.defineMacro("__CYGWIN__"); 3474 Builder.defineMacro("__CYGWIN32__"); 3475 DefineStd(Builder, "unix", Opts); 3476 if (Opts.CPlusPlus) 3477 Builder.defineMacro("_GNU_SOURCE"); 3478 } 3479 }; 3480 } // end anonymous namespace 3481 3482 namespace { 3483 // x86-32 Haiku target 3484 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3485 public: 3486 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3487 SizeType = UnsignedLong; 3488 IntPtrType = SignedLong; 3489 PtrDiffType = SignedLong; 3490 ProcessIDType = SignedLong; 3491 this->UserLabelPrefix = ""; 3492 this->TLSSupported = false; 3493 } 3494 void getTargetDefines(const LangOptions &Opts, 3495 MacroBuilder &Builder) const override { 3496 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3497 Builder.defineMacro("__INTEL__"); 3498 Builder.defineMacro("__HAIKU__"); 3499 } 3500 }; 3501 } // end anonymous namespace 3502 3503 // RTEMS Target 3504 template<typename Target> 3505 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3506 protected: 3507 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3508 MacroBuilder &Builder) const override { 3509 // RTEMS defines; list based off of gcc output 3510 3511 Builder.defineMacro("__rtems__"); 3512 Builder.defineMacro("__ELF__"); 3513 } 3514 3515 public: 3516 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3517 this->UserLabelPrefix = ""; 3518 3519 switch (Triple.getArch()) { 3520 default: 3521 case llvm::Triple::x86: 3522 // this->MCountName = ".mcount"; 3523 break; 3524 case llvm::Triple::mips: 3525 case llvm::Triple::mipsel: 3526 case llvm::Triple::ppc: 3527 case llvm::Triple::ppc64: 3528 case llvm::Triple::ppc64le: 3529 // this->MCountName = "_mcount"; 3530 break; 3531 case llvm::Triple::arm: 3532 // this->MCountName = "__mcount"; 3533 break; 3534 } 3535 } 3536 }; 3537 3538 namespace { 3539 // x86-32 RTEMS target 3540 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3541 public: 3542 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3543 SizeType = UnsignedLong; 3544 IntPtrType = SignedLong; 3545 PtrDiffType = SignedLong; 3546 this->UserLabelPrefix = ""; 3547 } 3548 void getTargetDefines(const LangOptions &Opts, 3549 MacroBuilder &Builder) const override { 3550 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3551 Builder.defineMacro("__INTEL__"); 3552 Builder.defineMacro("__rtems__"); 3553 } 3554 }; 3555 } // end anonymous namespace 3556 3557 namespace { 3558 // x86-64 generic target 3559 class X86_64TargetInfo : public X86TargetInfo { 3560 public: 3561 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3562 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3563 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3564 LongDoubleWidth = 128; 3565 LongDoubleAlign = 128; 3566 LargeArrayMinWidth = 128; 3567 LargeArrayAlign = 128; 3568 SuitableAlign = 128; 3569 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3570 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3571 IntPtrType = IsX32 ? SignedInt : SignedLong; 3572 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3573 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3574 RegParmMax = 6; 3575 3576 // Pointers are 32-bit in x32. 3577 DescriptionString = (IsX32) 3578 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3579 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3580 3581 // Use fpret only for long double. 3582 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3583 3584 // Use fp2ret for _Complex long double. 3585 ComplexLongDoubleUsesFP2Ret = true; 3586 3587 // x86-64 has atomics up to 16 bytes. 3588 MaxAtomicPromoteWidth = 128; 3589 MaxAtomicInlineWidth = 128; 3590 } 3591 BuiltinVaListKind getBuiltinVaListKind() const override { 3592 return TargetInfo::X86_64ABIBuiltinVaList; 3593 } 3594 3595 int getEHDataRegisterNumber(unsigned RegNo) const override { 3596 if (RegNo == 0) return 0; 3597 if (RegNo == 1) return 1; 3598 return -1; 3599 } 3600 3601 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3602 return (CC == CC_C || 3603 CC == CC_X86VectorCall || 3604 CC == CC_IntelOclBicc || 3605 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3606 } 3607 3608 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3609 return CC_C; 3610 } 3611 3612 // for x32 we need it here explicitly 3613 bool hasInt128Type() const override { return true; } 3614 }; 3615 } // end anonymous namespace 3616 3617 namespace { 3618 // x86-64 Windows target 3619 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3620 public: 3621 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3622 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3623 WCharType = UnsignedShort; 3624 LongWidth = LongAlign = 32; 3625 DoubleAlign = LongLongAlign = 64; 3626 IntMaxType = SignedLongLong; 3627 Int64Type = SignedLongLong; 3628 SizeType = UnsignedLongLong; 3629 PtrDiffType = SignedLongLong; 3630 IntPtrType = SignedLongLong; 3631 this->UserLabelPrefix = ""; 3632 } 3633 void getTargetDefines(const LangOptions &Opts, 3634 MacroBuilder &Builder) const override { 3635 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3636 Builder.defineMacro("_WIN64"); 3637 } 3638 BuiltinVaListKind getBuiltinVaListKind() const override { 3639 return TargetInfo::CharPtrBuiltinVaList; 3640 } 3641 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3642 return (CC == CC_C || 3643 CC == CC_X86VectorCall || 3644 CC == CC_IntelOclBicc || 3645 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning; 3646 } 3647 }; 3648 } // end anonymous namespace 3649 3650 namespace { 3651 // x86-64 Windows Visual Studio target 3652 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 3653 public: 3654 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 3655 : WindowsX86_64TargetInfo(Triple) { 3656 LongDoubleWidth = LongDoubleAlign = 64; 3657 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3658 } 3659 void getTargetDefines(const LangOptions &Opts, 3660 MacroBuilder &Builder) const override { 3661 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3662 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3663 Builder.defineMacro("_M_X64"); 3664 Builder.defineMacro("_M_AMD64"); 3665 } 3666 }; 3667 } // end anonymous namespace 3668 3669 namespace { 3670 // x86-64 MinGW target 3671 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3672 public: 3673 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3674 : WindowsX86_64TargetInfo(Triple) {} 3675 void getTargetDefines(const LangOptions &Opts, 3676 MacroBuilder &Builder) const override { 3677 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3678 DefineStd(Builder, "WIN64", Opts); 3679 Builder.defineMacro("__MINGW64__"); 3680 addMinGWDefines(Opts, Builder); 3681 3682 // GCC defines this macro when it is using __gxx_personality_seh0. 3683 if (!Opts.SjLjExceptions) 3684 Builder.defineMacro("__SEH__"); 3685 } 3686 }; 3687 } // end anonymous namespace 3688 3689 namespace { 3690 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3691 public: 3692 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3693 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3694 Int64Type = SignedLongLong; 3695 MaxVectorAlign = 256; 3696 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 3697 llvm::Triple T = llvm::Triple(Triple); 3698 if (T.isiOS()) 3699 UseSignedCharForObjCBool = false; 3700 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 3701 } 3702 }; 3703 } // end anonymous namespace 3704 3705 namespace { 3706 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3707 public: 3708 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3709 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3710 IntMaxType = SignedLongLong; 3711 Int64Type = SignedLongLong; 3712 } 3713 }; 3714 } // end anonymous namespace 3715 3716 namespace { 3717 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3718 public: 3719 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3720 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3721 IntMaxType = SignedLongLong; 3722 Int64Type = SignedLongLong; 3723 } 3724 }; 3725 } 3726 3727 3728 namespace { 3729 class ARMTargetInfo : public TargetInfo { 3730 // Possible FPU choices. 3731 enum FPUMode { 3732 VFP2FPU = (1 << 0), 3733 VFP3FPU = (1 << 1), 3734 VFP4FPU = (1 << 2), 3735 NeonFPU = (1 << 3), 3736 FPARMV8 = (1 << 4) 3737 }; 3738 3739 // Possible HWDiv features. 3740 enum HWDivMode { 3741 HWDivThumb = (1 << 0), 3742 HWDivARM = (1 << 1) 3743 }; 3744 3745 static bool FPUModeIsVFP(FPUMode Mode) { 3746 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 3747 } 3748 3749 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3750 static const char * const GCCRegNames[]; 3751 3752 std::string ABI, CPU; 3753 3754 enum { 3755 FP_Default, 3756 FP_VFP, 3757 FP_Neon 3758 } FPMath; 3759 3760 unsigned FPU : 5; 3761 3762 unsigned IsAAPCS : 1; 3763 unsigned IsThumb : 1; 3764 unsigned HWDiv : 2; 3765 3766 // Initialized via features. 3767 unsigned SoftFloat : 1; 3768 unsigned SoftFloatABI : 1; 3769 3770 unsigned CRC : 1; 3771 unsigned Crypto : 1; 3772 3773 // ACLE 6.5.1 Hardware floating point 3774 enum { 3775 HW_FP_HP = (1 << 1), /// half (16-bit) 3776 HW_FP_SP = (1 << 2), /// single (32-bit) 3777 HW_FP_DP = (1 << 3), /// double (64-bit) 3778 }; 3779 uint32_t HW_FP; 3780 3781 static const Builtin::Info BuiltinInfo[]; 3782 3783 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3784 StringRef ArchName = T.getArchName(); 3785 if (T.getArch() == llvm::Triple::arm || 3786 T.getArch() == llvm::Triple::armeb) { 3787 StringRef VersionStr; 3788 if (ArchName.startswith("armv")) 3789 VersionStr = ArchName.substr(4, 1); 3790 else if (ArchName.startswith("armebv")) 3791 VersionStr = ArchName.substr(6, 1); 3792 else 3793 return false; 3794 unsigned Version; 3795 if (VersionStr.getAsInteger(10, Version)) 3796 return false; 3797 return Version >= 6; 3798 } 3799 assert(T.getArch() == llvm::Triple::thumb || 3800 T.getArch() == llvm::Triple::thumbeb); 3801 StringRef VersionStr; 3802 if (ArchName.startswith("thumbv")) 3803 VersionStr = ArchName.substr(6, 1); 3804 else if (ArchName.startswith("thumbebv")) 3805 VersionStr = ArchName.substr(8, 1); 3806 else 3807 return false; 3808 unsigned Version; 3809 if (VersionStr.getAsInteger(10, Version)) 3810 return false; 3811 return Version >= 7; 3812 } 3813 3814 void setABIAAPCS() { 3815 IsAAPCS = true; 3816 3817 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 3818 const llvm::Triple &T = getTriple(); 3819 3820 // size_t is unsigned long on MachO-derived environments and NetBSD. 3821 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD) 3822 SizeType = UnsignedLong; 3823 else 3824 SizeType = UnsignedInt; 3825 3826 switch (T.getOS()) { 3827 case llvm::Triple::NetBSD: 3828 WCharType = SignedInt; 3829 break; 3830 case llvm::Triple::Win32: 3831 WCharType = UnsignedShort; 3832 break; 3833 case llvm::Triple::Linux: 3834 default: 3835 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3836 WCharType = UnsignedInt; 3837 break; 3838 } 3839 3840 UseBitFieldTypeAlignment = true; 3841 3842 ZeroLengthBitfieldBoundary = 0; 3843 3844 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3845 // so set preferred for small types to 32. 3846 if (T.isOSBinFormatMachO()) { 3847 DescriptionString = 3848 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 3849 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 3850 } else if (T.isOSWindows()) { 3851 // FIXME: this is invalid for WindowsCE 3852 assert(!BigEndian && "Windows on ARM does not support big endian"); 3853 DescriptionString = "e" 3854 "-m:e" 3855 "-p:32:32" 3856 "-i64:64" 3857 "-v128:64:128" 3858 "-a:0:32" 3859 "-n32" 3860 "-S64"; 3861 } else { 3862 DescriptionString = 3863 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 3864 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 3865 } 3866 3867 // FIXME: Enumerated types are variable width in straight AAPCS. 3868 } 3869 3870 void setABIAPCS() { 3871 const llvm::Triple &T = getTriple(); 3872 3873 IsAAPCS = false; 3874 3875 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 3876 3877 // size_t is unsigned int on FreeBSD. 3878 if (T.getOS() == llvm::Triple::FreeBSD) 3879 SizeType = UnsignedInt; 3880 else 3881 SizeType = UnsignedLong; 3882 3883 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 3884 WCharType = SignedInt; 3885 3886 // Do not respect the alignment of bit-field types when laying out 3887 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 3888 UseBitFieldTypeAlignment = false; 3889 3890 /// gcc forces the alignment to 4 bytes, regardless of the type of the 3891 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 3892 /// gcc. 3893 ZeroLengthBitfieldBoundary = 32; 3894 3895 if (T.isOSBinFormatMachO()) 3896 DescriptionString = 3897 BigEndian 3898 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 3899 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3900 else 3901 DescriptionString = 3902 BigEndian 3903 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 3904 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3905 3906 // FIXME: Override "preferred align" for double and long long. 3907 } 3908 3909 public: 3910 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 3911 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 3912 IsAAPCS(true), HW_FP(0) { 3913 BigEndian = IsBigEndian; 3914 3915 switch (getTriple().getOS()) { 3916 case llvm::Triple::NetBSD: 3917 PtrDiffType = SignedLong; 3918 break; 3919 default: 3920 PtrDiffType = SignedInt; 3921 break; 3922 } 3923 3924 // {} in inline assembly are neon specifiers, not assembly variant 3925 // specifiers. 3926 NoAsmVariants = true; 3927 3928 // FIXME: Should we just treat this as a feature? 3929 IsThumb = getTriple().getArchName().startswith("thumb"); 3930 3931 // FIXME: This duplicates code from the driver that sets the -target-abi 3932 // option - this code is used if -target-abi isn't passed and should 3933 // be unified in some way. 3934 if (Triple.isOSBinFormatMachO()) { 3935 // The backend is hardwired to assume AAPCS for M-class processors, ensure 3936 // the frontend matches that. 3937 if (Triple.getEnvironment() == llvm::Triple::EABI || 3938 Triple.getOS() == llvm::Triple::UnknownOS || 3939 StringRef(CPU).startswith("cortex-m")) { 3940 setABI("aapcs"); 3941 } else { 3942 setABI("apcs-gnu"); 3943 } 3944 } else if (Triple.isOSWindows()) { 3945 // FIXME: this is invalid for WindowsCE 3946 setABI("aapcs"); 3947 } else { 3948 // Select the default based on the platform. 3949 switch (Triple.getEnvironment()) { 3950 case llvm::Triple::Android: 3951 case llvm::Triple::GNUEABI: 3952 case llvm::Triple::GNUEABIHF: 3953 setABI("aapcs-linux"); 3954 break; 3955 case llvm::Triple::EABIHF: 3956 case llvm::Triple::EABI: 3957 setABI("aapcs"); 3958 break; 3959 case llvm::Triple::GNU: 3960 setABI("apcs-gnu"); 3961 break; 3962 default: 3963 if (Triple.getOS() == llvm::Triple::NetBSD) 3964 setABI("apcs-gnu"); 3965 else 3966 setABI("aapcs"); 3967 break; 3968 } 3969 } 3970 3971 // ARM targets default to using the ARM C++ ABI. 3972 TheCXXABI.set(TargetCXXABI::GenericARM); 3973 3974 // ARM has atomics up to 8 bytes 3975 MaxAtomicPromoteWidth = 64; 3976 if (shouldUseInlineAtomic(getTriple())) 3977 MaxAtomicInlineWidth = 64; 3978 3979 // Do force alignment of members that follow zero length bitfields. If 3980 // the alignment of the zero-length bitfield is greater than the member 3981 // that follows it, `bar', `bar' will be aligned as the type of the 3982 // zero length bitfield. 3983 UseZeroLengthBitfieldAlignment = true; 3984 } 3985 StringRef getABI() const override { return ABI; } 3986 bool setABI(const std::string &Name) override { 3987 ABI = Name; 3988 3989 // The defaults (above) are for AAPCS, check if we need to change them. 3990 // 3991 // FIXME: We need support for -meabi... we could just mangle it into the 3992 // name. 3993 if (Name == "apcs-gnu") { 3994 setABIAPCS(); 3995 return true; 3996 } 3997 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 3998 setABIAAPCS(); 3999 return true; 4000 } 4001 return false; 4002 } 4003 4004 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 4005 StringRef ArchName = getTriple().getArchName(); 4006 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 4007 Features["vfp2"] = true; 4008 else if (CPU == "cortex-a8" || CPU == "cortex-a9") { 4009 Features["vfp3"] = true; 4010 Features["neon"] = true; 4011 } 4012 else if (CPU == "cortex-a5") { 4013 Features["vfp4"] = true; 4014 Features["neon"] = true; 4015 } else if (CPU == "swift" || CPU == "cortex-a7" || 4016 CPU == "cortex-a12" || CPU == "cortex-a15" || 4017 CPU == "cortex-a17" || CPU == "krait") { 4018 Features["vfp4"] = true; 4019 Features["neon"] = true; 4020 Features["hwdiv"] = true; 4021 Features["hwdiv-arm"] = true; 4022 } else if (CPU == "cyclone") { 4023 Features["v8fp"] = true; 4024 Features["neon"] = true; 4025 Features["hwdiv"] = true; 4026 Features["hwdiv-arm"] = true; 4027 } else if (CPU == "cortex-a53" || CPU == "cortex-a57" || CPU == "cortex-a72") { 4028 Features["fp-armv8"] = true; 4029 Features["neon"] = true; 4030 Features["hwdiv"] = true; 4031 Features["hwdiv-arm"] = true; 4032 Features["crc"] = true; 4033 Features["crypto"] = true; 4034 } else if (CPU == "cortex-r5" || 4035 // Enable the hwdiv extension for all v8a AArch32 cores by 4036 // default. 4037 ArchName == "armv8a" || ArchName == "armv8" || 4038 ArchName == "armebv8a" || ArchName == "armebv8" || 4039 ArchName == "thumbv8a" || ArchName == "thumbv8" || 4040 ArchName == "thumbebv8a" || ArchName == "thumbebv8") { 4041 Features["hwdiv"] = true; 4042 Features["hwdiv-arm"] = true; 4043 } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7") { 4044 Features["hwdiv"] = true; 4045 } 4046 } 4047 4048 bool handleTargetFeatures(std::vector<std::string> &Features, 4049 DiagnosticsEngine &Diags) override { 4050 FPU = 0; 4051 CRC = 0; 4052 Crypto = 0; 4053 SoftFloat = SoftFloatABI = false; 4054 HWDiv = 0; 4055 4056 for (const auto &Feature : Features) { 4057 if (Feature == "+soft-float") { 4058 SoftFloat = true; 4059 } else if (Feature == "+soft-float-abi") { 4060 SoftFloatABI = true; 4061 } else if (Feature == "+vfp2") { 4062 FPU |= VFP2FPU; 4063 HW_FP = HW_FP_SP | HW_FP_DP; 4064 } else if (Feature == "+vfp3") { 4065 FPU |= VFP3FPU; 4066 HW_FP = HW_FP_SP | HW_FP_DP; 4067 } else if (Feature == "+vfp4") { 4068 FPU |= VFP4FPU; 4069 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP; 4070 } else if (Feature == "+fp-armv8") { 4071 FPU |= FPARMV8; 4072 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP; 4073 } else if (Feature == "+neon") { 4074 FPU |= NeonFPU; 4075 HW_FP = HW_FP_SP | HW_FP_DP; 4076 } else if (Feature == "+hwdiv") { 4077 HWDiv |= HWDivThumb; 4078 } else if (Feature == "+hwdiv-arm") { 4079 HWDiv |= HWDivARM; 4080 } else if (Feature == "+crc") { 4081 CRC = 1; 4082 } else if (Feature == "+crypto") { 4083 Crypto = 1; 4084 } else if (Feature == "+fp-only-sp") { 4085 HW_FP &= ~HW_FP_DP; 4086 } 4087 } 4088 4089 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4090 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4091 return false; 4092 } 4093 4094 if (FPMath == FP_Neon) 4095 Features.push_back("+neonfp"); 4096 else if (FPMath == FP_VFP) 4097 Features.push_back("-neonfp"); 4098 4099 // Remove front-end specific options which the backend handles differently. 4100 const StringRef FrontEndFeatures[] = { "+soft-float", "+soft-float-abi" }; 4101 for (const auto &FEFeature : FrontEndFeatures) { 4102 auto Feature = std::find(Features.begin(), Features.end(), FEFeature); 4103 if (Feature != Features.end()) 4104 Features.erase(Feature); 4105 } 4106 4107 return true; 4108 } 4109 4110 bool hasFeature(StringRef Feature) const override { 4111 return llvm::StringSwitch<bool>(Feature) 4112 .Case("arm", true) 4113 .Case("softfloat", SoftFloat) 4114 .Case("thumb", IsThumb) 4115 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4116 .Case("hwdiv", HWDiv & HWDivThumb) 4117 .Case("hwdiv-arm", HWDiv & HWDivARM) 4118 .Default(false); 4119 } 4120 // FIXME: Should we actually have some table instead of these switches? 4121 static const char *getCPUDefineSuffix(StringRef Name) { 4122 return llvm::StringSwitch<const char *>(Name) 4123 .Cases("arm8", "arm810", "4") 4124 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", 4125 "4") 4126 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 4127 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 4128 .Case("ep9312", "4T") 4129 .Cases("arm10tdmi", "arm1020t", "5T") 4130 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 4131 .Case("arm926ej-s", "5TEJ") 4132 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 4133 .Cases("xscale", "iwmmxt", "5TE") 4134 .Case("arm1136j-s", "6J") 4135 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 4136 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 4137 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 4138 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A") 4139 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait", 4140 "7A") 4141 .Cases("cortex-r4", "cortex-r5", "7R") 4142 .Case("swift", "7S") 4143 .Case("cyclone", "8A") 4144 .Case("cortex-m3", "7M") 4145 .Cases("cortex-m4", "cortex-m7", "7EM") 4146 .Case("cortex-m0", "6M") 4147 .Cases("cortex-a53", "cortex-a57", "cortex-a72", "8A") 4148 .Default(nullptr); 4149 } 4150 static const char *getCPUProfile(StringRef Name) { 4151 return llvm::StringSwitch<const char *>(Name) 4152 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A") 4153 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait", 4154 "A") 4155 .Cases("cortex-a53", "cortex-a57", "cortex-a72", "A") 4156 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m7", "M") 4157 .Cases("cortex-r4", "cortex-r5", "R") 4158 .Default(""); 4159 } 4160 bool setCPU(const std::string &Name) override { 4161 if (!getCPUDefineSuffix(Name)) 4162 return false; 4163 4164 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4165 StringRef Profile = getCPUProfile(Name); 4166 if (Profile == "M" && MaxAtomicInlineWidth) { 4167 MaxAtomicPromoteWidth = 32; 4168 MaxAtomicInlineWidth = 32; 4169 } 4170 4171 CPU = Name; 4172 return true; 4173 } 4174 bool setFPMath(StringRef Name) override; 4175 bool supportsThumb(StringRef ArchName, StringRef CPUArch, 4176 unsigned CPUArchVer) const { 4177 return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) || 4178 (CPUArch.find('M') != StringRef::npos); 4179 } 4180 bool supportsThumb2(StringRef ArchName, StringRef CPUArch, 4181 unsigned CPUArchVer) const { 4182 // We check both CPUArchVer and ArchName because when only triple is 4183 // specified, the default CPU is arm1136j-s. 4184 return ArchName.endswith("v6t2") || ArchName.endswith("v7") || 4185 ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7; 4186 } 4187 void getTargetDefines(const LangOptions &Opts, 4188 MacroBuilder &Builder) const override { 4189 // Target identification. 4190 Builder.defineMacro("__arm"); 4191 Builder.defineMacro("__arm__"); 4192 4193 // Target properties. 4194 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4195 4196 StringRef CPUArch = getCPUDefineSuffix(CPU); 4197 unsigned int CPUArchVer; 4198 if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) 4199 llvm_unreachable("Invalid char for architecture version number"); 4200 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 4201 4202 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4203 StringRef CPUProfile = getCPUProfile(CPU); 4204 StringRef ArchName = getTriple().getArchName(); 4205 4206 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4207 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 4208 if (CPUArch[0] >= '8') { 4209 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4210 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4211 } 4212 4213 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4214 // is not defined for the M-profile. 4215 // NOTE that the deffault profile is assumed to be 'A' 4216 if (CPUProfile.empty() || CPUProfile != "M") 4217 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4218 4219 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4220 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4221 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4222 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4223 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4224 else if (supportsThumb(ArchName, CPUArch, CPUArchVer)) 4225 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4226 4227 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4228 // instruction set such as ARM or Thumb. 4229 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4230 4231 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4232 4233 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4234 if (!CPUProfile.empty()) 4235 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4236 4237 // ACLE 6.5.1 Hardware Floating Point 4238 if (HW_FP) 4239 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4240 4241 // ACLE predefines. 4242 Builder.defineMacro("__ARM_ACLE", "200"); 4243 4244 // Subtarget options. 4245 4246 // FIXME: It's more complicated than this and we don't really support 4247 // interworking. 4248 // Windows on ARM does not "support" interworking 4249 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows()) 4250 Builder.defineMacro("__THUMB_INTERWORK__"); 4251 4252 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4253 // Embedded targets on Darwin follow AAPCS, but not EABI. 4254 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4255 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4256 Builder.defineMacro("__ARM_EABI__"); 4257 Builder.defineMacro("__ARM_PCS", "1"); 4258 4259 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4260 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4261 } 4262 4263 if (SoftFloat) 4264 Builder.defineMacro("__SOFTFP__"); 4265 4266 if (CPU == "xscale") 4267 Builder.defineMacro("__XSCALE__"); 4268 4269 if (IsThumb) { 4270 Builder.defineMacro("__THUMBEL__"); 4271 Builder.defineMacro("__thumb__"); 4272 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4273 Builder.defineMacro("__thumb2__"); 4274 } 4275 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 4276 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4277 4278 // Note, this is always on in gcc, even though it doesn't make sense. 4279 Builder.defineMacro("__APCS_32__"); 4280 4281 if (FPUModeIsVFP((FPUMode) FPU)) { 4282 Builder.defineMacro("__VFP_FP__"); 4283 if (FPU & VFP2FPU) 4284 Builder.defineMacro("__ARM_VFPV2__"); 4285 if (FPU & VFP3FPU) 4286 Builder.defineMacro("__ARM_VFPV3__"); 4287 if (FPU & VFP4FPU) 4288 Builder.defineMacro("__ARM_VFPV4__"); 4289 } 4290 4291 // This only gets set when Neon instructions are actually available, unlike 4292 // the VFP define, hence the soft float and arch check. This is subtly 4293 // different from gcc, we follow the intent which was that it should be set 4294 // when Neon instructions are actually available. 4295 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) { 4296 Builder.defineMacro("__ARM_NEON"); 4297 Builder.defineMacro("__ARM_NEON__"); 4298 } 4299 4300 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4301 Opts.ShortWChar ? "2" : "4"); 4302 4303 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4304 Opts.ShortEnums ? "1" : "4"); 4305 4306 if (CRC) 4307 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4308 4309 if (Crypto) 4310 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4311 4312 if (CPUArchVer >= 6 && CPUArch != "6M") { 4313 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4314 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4315 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4316 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4317 } 4318 4319 bool is5EOrAbove = (CPUArchVer >= 6 || 4320 (CPUArchVer == 5 && 4321 CPUArch.find('E') != StringRef::npos)); 4322 bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer)); 4323 if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch == "7EM")) 4324 Builder.defineMacro("__ARM_FEATURE_DSP"); 4325 } 4326 void getTargetBuiltins(const Builtin::Info *&Records, 4327 unsigned &NumRecords) const override { 4328 Records = BuiltinInfo; 4329 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4330 } 4331 bool isCLZForZeroUndef() const override { return false; } 4332 BuiltinVaListKind getBuiltinVaListKind() const override { 4333 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4334 } 4335 void getGCCRegNames(const char * const *&Names, 4336 unsigned &NumNames) const override; 4337 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4338 unsigned &NumAliases) const override; 4339 bool validateAsmConstraint(const char *&Name, 4340 TargetInfo::ConstraintInfo &Info) const override { 4341 switch (*Name) { 4342 default: break; 4343 case 'l': // r0-r7 4344 case 'h': // r8-r15 4345 case 'w': // VFP Floating point register single precision 4346 case 'P': // VFP Floating point register double precision 4347 Info.setAllowsRegister(); 4348 return true; 4349 case 'I': 4350 case 'J': 4351 case 'K': 4352 case 'L': 4353 case 'M': 4354 // FIXME 4355 return true; 4356 case 'Q': // A memory address that is a single base register. 4357 Info.setAllowsMemory(); 4358 return true; 4359 case 'U': // a memory reference... 4360 switch (Name[1]) { 4361 case 'q': // ...ARMV4 ldrsb 4362 case 'v': // ...VFP load/store (reg+constant offset) 4363 case 'y': // ...iWMMXt load/store 4364 case 't': // address valid for load/store opaque types wider 4365 // than 128-bits 4366 case 'n': // valid address for Neon doubleword vector load/store 4367 case 'm': // valid address for Neon element and structure load/store 4368 case 's': // valid address for non-offset loads/stores of quad-word 4369 // values in four ARM registers 4370 Info.setAllowsMemory(); 4371 Name++; 4372 return true; 4373 } 4374 } 4375 return false; 4376 } 4377 std::string convertConstraint(const char *&Constraint) const override { 4378 std::string R; 4379 switch (*Constraint) { 4380 case 'U': // Two-character constraint; add "^" hint for later parsing. 4381 R = std::string("^") + std::string(Constraint, 2); 4382 Constraint++; 4383 break; 4384 case 'p': // 'p' should be translated to 'r' by default. 4385 R = std::string("r"); 4386 break; 4387 default: 4388 return std::string(1, *Constraint); 4389 } 4390 return R; 4391 } 4392 bool 4393 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4394 std::string &SuggestedModifier) const override { 4395 bool isOutput = (Constraint[0] == '='); 4396 bool isInOut = (Constraint[0] == '+'); 4397 4398 // Strip off constraint modifiers. 4399 while (Constraint[0] == '=' || 4400 Constraint[0] == '+' || 4401 Constraint[0] == '&') 4402 Constraint = Constraint.substr(1); 4403 4404 switch (Constraint[0]) { 4405 default: break; 4406 case 'r': { 4407 switch (Modifier) { 4408 default: 4409 return (isInOut || isOutput || Size <= 64); 4410 case 'q': 4411 // A register of size 32 cannot fit a vector type. 4412 return false; 4413 } 4414 } 4415 } 4416 4417 return true; 4418 } 4419 const char *getClobbers() const override { 4420 // FIXME: Is this really right? 4421 return ""; 4422 } 4423 4424 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4425 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4426 } 4427 4428 int getEHDataRegisterNumber(unsigned RegNo) const override { 4429 if (RegNo == 0) return 0; 4430 if (RegNo == 1) return 1; 4431 return -1; 4432 } 4433 }; 4434 4435 bool ARMTargetInfo::setFPMath(StringRef Name) { 4436 if (Name == "neon") { 4437 FPMath = FP_Neon; 4438 return true; 4439 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4440 Name == "vfp4") { 4441 FPMath = FP_VFP; 4442 return true; 4443 } 4444 return false; 4445 } 4446 4447 const char * const ARMTargetInfo::GCCRegNames[] = { 4448 // Integer registers 4449 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4450 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4451 4452 // Float registers 4453 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4454 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4455 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4456 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4457 4458 // Double registers 4459 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4460 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4461 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4462 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4463 4464 // Quad registers 4465 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4466 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4467 }; 4468 4469 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4470 unsigned &NumNames) const { 4471 Names = GCCRegNames; 4472 NumNames = llvm::array_lengthof(GCCRegNames); 4473 } 4474 4475 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4476 { { "a1" }, "r0" }, 4477 { { "a2" }, "r1" }, 4478 { { "a3" }, "r2" }, 4479 { { "a4" }, "r3" }, 4480 { { "v1" }, "r4" }, 4481 { { "v2" }, "r5" }, 4482 { { "v3" }, "r6" }, 4483 { { "v4" }, "r7" }, 4484 { { "v5" }, "r8" }, 4485 { { "v6", "rfp" }, "r9" }, 4486 { { "sl" }, "r10" }, 4487 { { "fp" }, "r11" }, 4488 { { "ip" }, "r12" }, 4489 { { "r13" }, "sp" }, 4490 { { "r14" }, "lr" }, 4491 { { "r15" }, "pc" }, 4492 // The S, D and Q registers overlap, but aren't really aliases; we 4493 // don't want to substitute one of these for a different-sized one. 4494 }; 4495 4496 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4497 unsigned &NumAliases) const { 4498 Aliases = GCCRegAliases; 4499 NumAliases = llvm::array_lengthof(GCCRegAliases); 4500 } 4501 4502 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4503 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4504 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4505 ALL_LANGUAGES }, 4506 #include "clang/Basic/BuiltinsNEON.def" 4507 4508 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4509 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG }, 4510 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4511 ALL_LANGUAGES }, 4512 #include "clang/Basic/BuiltinsARM.def" 4513 }; 4514 4515 class ARMleTargetInfo : public ARMTargetInfo { 4516 public: 4517 ARMleTargetInfo(const llvm::Triple &Triple) 4518 : ARMTargetInfo(Triple, false) { } 4519 virtual void getTargetDefines(const LangOptions &Opts, 4520 MacroBuilder &Builder) const { 4521 Builder.defineMacro("__ARMEL__"); 4522 ARMTargetInfo::getTargetDefines(Opts, Builder); 4523 } 4524 }; 4525 4526 class ARMbeTargetInfo : public ARMTargetInfo { 4527 public: 4528 ARMbeTargetInfo(const llvm::Triple &Triple) 4529 : ARMTargetInfo(Triple, true) { } 4530 virtual void getTargetDefines(const LangOptions &Opts, 4531 MacroBuilder &Builder) const { 4532 Builder.defineMacro("__ARMEB__"); 4533 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4534 ARMTargetInfo::getTargetDefines(Opts, Builder); 4535 } 4536 }; 4537 } // end anonymous namespace. 4538 4539 namespace { 4540 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 4541 const llvm::Triple Triple; 4542 public: 4543 WindowsARMTargetInfo(const llvm::Triple &Triple) 4544 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 4545 TLSSupported = false; 4546 WCharType = UnsignedShort; 4547 SizeType = UnsignedInt; 4548 UserLabelPrefix = ""; 4549 } 4550 void getVisualStudioDefines(const LangOptions &Opts, 4551 MacroBuilder &Builder) const { 4552 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 4553 4554 // FIXME: this is invalid for WindowsCE 4555 Builder.defineMacro("_M_ARM_NT", "1"); 4556 Builder.defineMacro("_M_ARMT", "_M_ARM"); 4557 Builder.defineMacro("_M_THUMB", "_M_ARM"); 4558 4559 assert((Triple.getArch() == llvm::Triple::arm || 4560 Triple.getArch() == llvm::Triple::thumb) && 4561 "invalid architecture for Windows ARM target info"); 4562 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 4563 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 4564 4565 // TODO map the complete set of values 4566 // 31: VFPv3 40: VFPv4 4567 Builder.defineMacro("_M_ARM_FP", "31"); 4568 } 4569 BuiltinVaListKind getBuiltinVaListKind() const override { 4570 return TargetInfo::CharPtrBuiltinVaList; 4571 } 4572 }; 4573 4574 // Windows ARM + Itanium C++ ABI Target 4575 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 4576 public: 4577 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 4578 : WindowsARMTargetInfo(Triple) { 4579 TheCXXABI.set(TargetCXXABI::GenericARM); 4580 } 4581 4582 void getTargetDefines(const LangOptions &Opts, 4583 MacroBuilder &Builder) const override { 4584 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4585 4586 if (Opts.MSVCCompat) 4587 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4588 } 4589 }; 4590 4591 // Windows ARM, MS (C++) ABI 4592 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 4593 public: 4594 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 4595 : WindowsARMTargetInfo(Triple) { 4596 TheCXXABI.set(TargetCXXABI::Microsoft); 4597 } 4598 4599 void getTargetDefines(const LangOptions &Opts, 4600 MacroBuilder &Builder) const override { 4601 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4602 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4603 } 4604 }; 4605 } 4606 4607 4608 namespace { 4609 class DarwinARMTargetInfo : 4610 public DarwinTargetInfo<ARMleTargetInfo> { 4611 protected: 4612 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4613 MacroBuilder &Builder) const override { 4614 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4615 } 4616 4617 public: 4618 DarwinARMTargetInfo(const llvm::Triple &Triple) 4619 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 4620 HasAlignMac68kSupport = true; 4621 // iOS always has 64-bit atomic instructions. 4622 // FIXME: This should be based off of the target features in 4623 // ARMleTargetInfo. 4624 MaxAtomicInlineWidth = 64; 4625 4626 // Darwin on iOS uses a variant of the ARM C++ ABI. 4627 TheCXXABI.set(TargetCXXABI::iOS); 4628 } 4629 }; 4630 } // end anonymous namespace. 4631 4632 4633 namespace { 4634 class AArch64TargetInfo : public TargetInfo { 4635 virtual void setDescriptionString() = 0; 4636 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4637 static const char *const GCCRegNames[]; 4638 4639 enum FPUModeEnum { 4640 FPUMode, 4641 NeonMode 4642 }; 4643 4644 unsigned FPU; 4645 unsigned CRC; 4646 unsigned Crypto; 4647 4648 static const Builtin::Info BuiltinInfo[]; 4649 4650 std::string ABI; 4651 4652 public: 4653 AArch64TargetInfo(const llvm::Triple &Triple) 4654 : TargetInfo(Triple), ABI("aapcs") { 4655 4656 if (getTriple().getOS() == llvm::Triple::NetBSD) { 4657 WCharType = SignedInt; 4658 4659 // NetBSD apparently prefers consistency across ARM targets to consistency 4660 // across 64-bit targets. 4661 Int64Type = SignedLongLong; 4662 IntMaxType = SignedLongLong; 4663 } else { 4664 WCharType = UnsignedInt; 4665 Int64Type = SignedLong; 4666 IntMaxType = SignedLong; 4667 } 4668 4669 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4670 MaxVectorAlign = 128; 4671 RegParmMax = 8; 4672 MaxAtomicInlineWidth = 128; 4673 MaxAtomicPromoteWidth = 128; 4674 4675 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 4676 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4677 4678 // {} in inline assembly are neon specifiers, not assembly variant 4679 // specifiers. 4680 NoAsmVariants = true; 4681 4682 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 4683 // contributes to the alignment of the containing aggregate in the same way 4684 // a plain (non bit-field) member of that type would, without exception for 4685 // zero-sized or anonymous bit-fields." 4686 UseBitFieldTypeAlignment = true; 4687 UseZeroLengthBitfieldAlignment = true; 4688 4689 // AArch64 targets default to using the ARM C++ ABI. 4690 TheCXXABI.set(TargetCXXABI::GenericAArch64); 4691 } 4692 4693 StringRef getABI() const override { return ABI; } 4694 bool setABI(const std::string &Name) override { 4695 if (Name != "aapcs" && Name != "darwinpcs") 4696 return false; 4697 4698 ABI = Name; 4699 return true; 4700 } 4701 4702 bool setCPU(const std::string &Name) override { 4703 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4704 .Case("generic", true) 4705 .Cases("cortex-a53", "cortex-a57", "cortex-a72", true) 4706 .Case("cyclone", true) 4707 .Default(false); 4708 return CPUKnown; 4709 } 4710 4711 virtual void getTargetDefines(const LangOptions &Opts, 4712 MacroBuilder &Builder) const override { 4713 // Target identification. 4714 Builder.defineMacro("__aarch64__"); 4715 4716 // Target properties. 4717 Builder.defineMacro("_LP64"); 4718 Builder.defineMacro("__LP64__"); 4719 4720 // ACLE predefines. Many can only have one possible value on v8 AArch64. 4721 Builder.defineMacro("__ARM_ACLE", "200"); 4722 Builder.defineMacro("__ARM_ARCH", "8"); 4723 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 4724 4725 Builder.defineMacro("__ARM_64BIT_STATE"); 4726 Builder.defineMacro("__ARM_PCS_AAPCS64"); 4727 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 4728 4729 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 4730 Builder.defineMacro("__ARM_FEATURE_CLZ"); 4731 Builder.defineMacro("__ARM_FEATURE_FMA"); 4732 Builder.defineMacro("__ARM_FEATURE_DIV"); 4733 Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE 4734 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 4735 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4736 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4737 4738 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 4739 4740 // 0xe implies support for half, single and double precision operations. 4741 Builder.defineMacro("__ARM_FP", "0xe"); 4742 4743 // PCS specifies this for SysV variants, which is all we support. Other ABIs 4744 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 4745 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 4746 4747 if (Opts.FastMath || Opts.FiniteMathOnly) 4748 Builder.defineMacro("__ARM_FP_FAST"); 4749 4750 if (Opts.C99 && !Opts.Freestanding) 4751 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 4752 4753 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 4754 4755 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4756 Opts.ShortEnums ? "1" : "4"); 4757 4758 if (FPU == NeonMode) { 4759 Builder.defineMacro("__ARM_NEON"); 4760 // 64-bit NEON supports half, single and double precision operations. 4761 Builder.defineMacro("__ARM_NEON_FP", "0xe"); 4762 } 4763 4764 if (CRC) 4765 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4766 4767 if (Crypto) 4768 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4769 } 4770 4771 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4772 unsigned &NumRecords) const override { 4773 Records = BuiltinInfo; 4774 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin; 4775 } 4776 4777 bool hasFeature(StringRef Feature) const override { 4778 return Feature == "aarch64" || 4779 Feature == "arm64" || 4780 (Feature == "neon" && FPU == NeonMode); 4781 } 4782 4783 bool handleTargetFeatures(std::vector<std::string> &Features, 4784 DiagnosticsEngine &Diags) override { 4785 FPU = FPUMode; 4786 CRC = 0; 4787 Crypto = 0; 4788 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 4789 if (Features[i] == "+neon") 4790 FPU = NeonMode; 4791 if (Features[i] == "+crc") 4792 CRC = 1; 4793 if (Features[i] == "+crypto") 4794 Crypto = 1; 4795 } 4796 4797 setDescriptionString(); 4798 4799 return true; 4800 } 4801 4802 bool isCLZForZeroUndef() const override { return false; } 4803 4804 BuiltinVaListKind getBuiltinVaListKind() const override { 4805 return TargetInfo::AArch64ABIBuiltinVaList; 4806 } 4807 4808 virtual void getGCCRegNames(const char *const *&Names, 4809 unsigned &NumNames) const override; 4810 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4811 unsigned &NumAliases) const override; 4812 4813 virtual bool 4814 validateAsmConstraint(const char *&Name, 4815 TargetInfo::ConstraintInfo &Info) const override { 4816 switch (*Name) { 4817 default: 4818 return false; 4819 case 'w': // Floating point and SIMD registers (V0-V31) 4820 Info.setAllowsRegister(); 4821 return true; 4822 case 'I': // Constant that can be used with an ADD instruction 4823 case 'J': // Constant that can be used with a SUB instruction 4824 case 'K': // Constant that can be used with a 32-bit logical instruction 4825 case 'L': // Constant that can be used with a 64-bit logical instruction 4826 case 'M': // Constant that can be used as a 32-bit MOV immediate 4827 case 'N': // Constant that can be used as a 64-bit MOV immediate 4828 case 'Y': // Floating point constant zero 4829 case 'Z': // Integer constant zero 4830 return true; 4831 case 'Q': // A memory reference with base register and no offset 4832 Info.setAllowsMemory(); 4833 return true; 4834 case 'S': // A symbolic address 4835 Info.setAllowsRegister(); 4836 return true; 4837 case 'U': 4838 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 4839 // Utf: A memory address suitable for ldp/stp in TF mode. 4840 // Usa: An absolute symbolic address. 4841 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 4842 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 4843 case 'z': // Zero register, wzr or xzr 4844 Info.setAllowsRegister(); 4845 return true; 4846 case 'x': // Floating point and SIMD registers (V0-V15) 4847 Info.setAllowsRegister(); 4848 return true; 4849 } 4850 return false; 4851 } 4852 4853 bool 4854 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4855 std::string &SuggestedModifier) const override { 4856 // Strip off constraint modifiers. 4857 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 4858 Constraint = Constraint.substr(1); 4859 4860 switch (Constraint[0]) { 4861 default: 4862 return true; 4863 case 'z': 4864 case 'r': { 4865 switch (Modifier) { 4866 case 'x': 4867 case 'w': 4868 // For now assume that the person knows what they're 4869 // doing with the modifier. 4870 return true; 4871 default: 4872 // By default an 'r' constraint will be in the 'x' 4873 // registers. 4874 if (Size == 64) 4875 return true; 4876 4877 SuggestedModifier = "w"; 4878 return false; 4879 } 4880 } 4881 } 4882 } 4883 4884 const char *getClobbers() const override { return ""; } 4885 4886 int getEHDataRegisterNumber(unsigned RegNo) const override { 4887 if (RegNo == 0) 4888 return 0; 4889 if (RegNo == 1) 4890 return 1; 4891 return -1; 4892 } 4893 }; 4894 4895 const char *const AArch64TargetInfo::GCCRegNames[] = { 4896 // 32-bit Integer registers 4897 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 4898 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 4899 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 4900 4901 // 64-bit Integer registers 4902 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 4903 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 4904 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 4905 4906 // 32-bit floating point regsisters 4907 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 4908 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 4909 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4910 4911 // 64-bit floating point regsisters 4912 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 4913 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 4914 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4915 4916 // Vector registers 4917 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 4918 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 4919 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 4920 }; 4921 4922 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names, 4923 unsigned &NumNames) const { 4924 Names = GCCRegNames; 4925 NumNames = llvm::array_lengthof(GCCRegNames); 4926 } 4927 4928 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 4929 { { "w31" }, "wsp" }, 4930 { { "x29" }, "fp" }, 4931 { { "x30" }, "lr" }, 4932 { { "x31" }, "sp" }, 4933 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 4934 // don't want to substitute one of these for a different-sized one. 4935 }; 4936 4937 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4938 unsigned &NumAliases) const { 4939 Aliases = GCCRegAliases; 4940 NumAliases = llvm::array_lengthof(GCCRegAliases); 4941 } 4942 4943 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 4944 #define BUILTIN(ID, TYPE, ATTRS) \ 4945 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4946 #include "clang/Basic/BuiltinsNEON.def" 4947 4948 #define BUILTIN(ID, TYPE, ATTRS) \ 4949 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4950 #include "clang/Basic/BuiltinsAArch64.def" 4951 }; 4952 4953 class AArch64leTargetInfo : public AArch64TargetInfo { 4954 void setDescriptionString() override { 4955 if (getTriple().isOSBinFormatMachO()) 4956 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128"; 4957 else 4958 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 4959 } 4960 4961 public: 4962 AArch64leTargetInfo(const llvm::Triple &Triple) 4963 : AArch64TargetInfo(Triple) { 4964 BigEndian = false; 4965 } 4966 void getTargetDefines(const LangOptions &Opts, 4967 MacroBuilder &Builder) const override { 4968 Builder.defineMacro("__AARCH64EL__"); 4969 AArch64TargetInfo::getTargetDefines(Opts, Builder); 4970 } 4971 }; 4972 4973 class AArch64beTargetInfo : public AArch64TargetInfo { 4974 void setDescriptionString() override { 4975 assert(!getTriple().isOSBinFormatMachO()); 4976 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128"; 4977 } 4978 4979 public: 4980 AArch64beTargetInfo(const llvm::Triple &Triple) 4981 : AArch64TargetInfo(Triple) { } 4982 void getTargetDefines(const LangOptions &Opts, 4983 MacroBuilder &Builder) const override { 4984 Builder.defineMacro("__AARCH64EB__"); 4985 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 4986 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4987 AArch64TargetInfo::getTargetDefines(Opts, Builder); 4988 } 4989 }; 4990 } // end anonymous namespace. 4991 4992 namespace { 4993 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 4994 protected: 4995 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4996 MacroBuilder &Builder) const override { 4997 Builder.defineMacro("__AARCH64_SIMD__"); 4998 Builder.defineMacro("__ARM64_ARCH_8__"); 4999 Builder.defineMacro("__ARM_NEON__"); 5000 Builder.defineMacro("__LITTLE_ENDIAN__"); 5001 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5002 Builder.defineMacro("__arm64", "1"); 5003 Builder.defineMacro("__arm64__", "1"); 5004 5005 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5006 } 5007 5008 public: 5009 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5010 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5011 Int64Type = SignedLongLong; 5012 WCharType = SignedInt; 5013 UseSignedCharForObjCBool = false; 5014 5015 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5016 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5017 5018 TheCXXABI.set(TargetCXXABI::iOS64); 5019 } 5020 5021 BuiltinVaListKind getBuiltinVaListKind() const override { 5022 return TargetInfo::CharPtrBuiltinVaList; 5023 } 5024 }; 5025 } // end anonymous namespace 5026 5027 namespace { 5028 // Hexagon abstract base class 5029 class HexagonTargetInfo : public TargetInfo { 5030 static const Builtin::Info BuiltinInfo[]; 5031 static const char * const GCCRegNames[]; 5032 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5033 std::string CPU; 5034 public: 5035 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5036 BigEndian = false; 5037 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 5038 5039 // {} in inline assembly are packet specifiers, not assembly variant 5040 // specifiers. 5041 NoAsmVariants = true; 5042 } 5043 5044 void getTargetBuiltins(const Builtin::Info *&Records, 5045 unsigned &NumRecords) const override { 5046 Records = BuiltinInfo; 5047 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 5048 } 5049 5050 bool validateAsmConstraint(const char *&Name, 5051 TargetInfo::ConstraintInfo &Info) const override { 5052 return true; 5053 } 5054 5055 void getTargetDefines(const LangOptions &Opts, 5056 MacroBuilder &Builder) const override; 5057 5058 bool hasFeature(StringRef Feature) const override { 5059 return Feature == "hexagon"; 5060 } 5061 5062 BuiltinVaListKind getBuiltinVaListKind() const override { 5063 return TargetInfo::CharPtrBuiltinVaList; 5064 } 5065 void getGCCRegNames(const char * const *&Names, 5066 unsigned &NumNames) const override; 5067 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5068 unsigned &NumAliases) const override; 5069 const char *getClobbers() const override { 5070 return ""; 5071 } 5072 5073 static const char *getHexagonCPUSuffix(StringRef Name) { 5074 return llvm::StringSwitch<const char*>(Name) 5075 .Case("hexagonv4", "4") 5076 .Case("hexagonv5", "5") 5077 .Default(nullptr); 5078 } 5079 5080 bool setCPU(const std::string &Name) override { 5081 if (!getHexagonCPUSuffix(Name)) 5082 return false; 5083 5084 CPU = Name; 5085 return true; 5086 } 5087 }; 5088 5089 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5090 MacroBuilder &Builder) const { 5091 Builder.defineMacro("qdsp6"); 5092 Builder.defineMacro("__qdsp6", "1"); 5093 Builder.defineMacro("__qdsp6__", "1"); 5094 5095 Builder.defineMacro("hexagon"); 5096 Builder.defineMacro("__hexagon", "1"); 5097 Builder.defineMacro("__hexagon__", "1"); 5098 5099 if(CPU == "hexagonv1") { 5100 Builder.defineMacro("__HEXAGON_V1__"); 5101 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 5102 if(Opts.HexagonQdsp6Compat) { 5103 Builder.defineMacro("__QDSP6_V1__"); 5104 Builder.defineMacro("__QDSP6_ARCH__", "1"); 5105 } 5106 } 5107 else if(CPU == "hexagonv2") { 5108 Builder.defineMacro("__HEXAGON_V2__"); 5109 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 5110 if(Opts.HexagonQdsp6Compat) { 5111 Builder.defineMacro("__QDSP6_V2__"); 5112 Builder.defineMacro("__QDSP6_ARCH__", "2"); 5113 } 5114 } 5115 else if(CPU == "hexagonv3") { 5116 Builder.defineMacro("__HEXAGON_V3__"); 5117 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 5118 if(Opts.HexagonQdsp6Compat) { 5119 Builder.defineMacro("__QDSP6_V3__"); 5120 Builder.defineMacro("__QDSP6_ARCH__", "3"); 5121 } 5122 } 5123 else if(CPU == "hexagonv4") { 5124 Builder.defineMacro("__HEXAGON_V4__"); 5125 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5126 if(Opts.HexagonQdsp6Compat) { 5127 Builder.defineMacro("__QDSP6_V4__"); 5128 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5129 } 5130 } 5131 else if(CPU == "hexagonv5") { 5132 Builder.defineMacro("__HEXAGON_V5__"); 5133 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5134 if(Opts.HexagonQdsp6Compat) { 5135 Builder.defineMacro("__QDSP6_V5__"); 5136 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5137 } 5138 } 5139 } 5140 5141 const char * const HexagonTargetInfo::GCCRegNames[] = { 5142 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5143 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5144 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5145 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5146 "p0", "p1", "p2", "p3", 5147 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5148 }; 5149 5150 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 5151 unsigned &NumNames) const { 5152 Names = GCCRegNames; 5153 NumNames = llvm::array_lengthof(GCCRegNames); 5154 } 5155 5156 5157 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5158 { { "sp" }, "r29" }, 5159 { { "fp" }, "r30" }, 5160 { { "lr" }, "r31" }, 5161 }; 5162 5163 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5164 unsigned &NumAliases) const { 5165 Aliases = GCCRegAliases; 5166 NumAliases = llvm::array_lengthof(GCCRegAliases); 5167 } 5168 5169 5170 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5171 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5172 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5173 ALL_LANGUAGES }, 5174 #include "clang/Basic/BuiltinsHexagon.def" 5175 }; 5176 } 5177 5178 5179 namespace { 5180 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5181 class SparcTargetInfo : public TargetInfo { 5182 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5183 static const char * const GCCRegNames[]; 5184 bool SoftFloat; 5185 public: 5186 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {} 5187 5188 bool handleTargetFeatures(std::vector<std::string> &Features, 5189 DiagnosticsEngine &Diags) override { 5190 SoftFloat = false; 5191 for (unsigned i = 0, e = Features.size(); i != e; ++i) 5192 if (Features[i] == "+soft-float") 5193 SoftFloat = true; 5194 return true; 5195 } 5196 void getTargetDefines(const LangOptions &Opts, 5197 MacroBuilder &Builder) const override { 5198 DefineStd(Builder, "sparc", Opts); 5199 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5200 5201 if (SoftFloat) 5202 Builder.defineMacro("SOFT_FLOAT", "1"); 5203 } 5204 5205 bool hasFeature(StringRef Feature) const override { 5206 return llvm::StringSwitch<bool>(Feature) 5207 .Case("softfloat", SoftFloat) 5208 .Case("sparc", true) 5209 .Default(false); 5210 } 5211 5212 void getTargetBuiltins(const Builtin::Info *&Records, 5213 unsigned &NumRecords) const override { 5214 // FIXME: Implement! 5215 } 5216 BuiltinVaListKind getBuiltinVaListKind() const override { 5217 return TargetInfo::VoidPtrBuiltinVaList; 5218 } 5219 void getGCCRegNames(const char * const *&Names, 5220 unsigned &NumNames) const override; 5221 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5222 unsigned &NumAliases) const override; 5223 bool validateAsmConstraint(const char *&Name, 5224 TargetInfo::ConstraintInfo &info) const override { 5225 // FIXME: Implement! 5226 switch (*Name) { 5227 case 'I': // Signed 13-bit constant 5228 case 'J': // Zero 5229 case 'K': // 32-bit constant with the low 12 bits clear 5230 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5231 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5232 case 'N': // Same as 'K' but zext (required for SIMode) 5233 case 'O': // The constant 4096 5234 return true; 5235 } 5236 return false; 5237 } 5238 const char *getClobbers() const override { 5239 // FIXME: Implement! 5240 return ""; 5241 } 5242 }; 5243 5244 const char * const SparcTargetInfo::GCCRegNames[] = { 5245 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5246 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5247 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5248 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5249 }; 5250 5251 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 5252 unsigned &NumNames) const { 5253 Names = GCCRegNames; 5254 NumNames = llvm::array_lengthof(GCCRegNames); 5255 } 5256 5257 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5258 { { "g0" }, "r0" }, 5259 { { "g1" }, "r1" }, 5260 { { "g2" }, "r2" }, 5261 { { "g3" }, "r3" }, 5262 { { "g4" }, "r4" }, 5263 { { "g5" }, "r5" }, 5264 { { "g6" }, "r6" }, 5265 { { "g7" }, "r7" }, 5266 { { "o0" }, "r8" }, 5267 { { "o1" }, "r9" }, 5268 { { "o2" }, "r10" }, 5269 { { "o3" }, "r11" }, 5270 { { "o4" }, "r12" }, 5271 { { "o5" }, "r13" }, 5272 { { "o6", "sp" }, "r14" }, 5273 { { "o7" }, "r15" }, 5274 { { "l0" }, "r16" }, 5275 { { "l1" }, "r17" }, 5276 { { "l2" }, "r18" }, 5277 { { "l3" }, "r19" }, 5278 { { "l4" }, "r20" }, 5279 { { "l5" }, "r21" }, 5280 { { "l6" }, "r22" }, 5281 { { "l7" }, "r23" }, 5282 { { "i0" }, "r24" }, 5283 { { "i1" }, "r25" }, 5284 { { "i2" }, "r26" }, 5285 { { "i3" }, "r27" }, 5286 { { "i4" }, "r28" }, 5287 { { "i5" }, "r29" }, 5288 { { "i6", "fp" }, "r30" }, 5289 { { "i7" }, "r31" }, 5290 }; 5291 5292 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5293 unsigned &NumAliases) const { 5294 Aliases = GCCRegAliases; 5295 NumAliases = llvm::array_lengthof(GCCRegAliases); 5296 } 5297 5298 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5299 class SparcV8TargetInfo : public SparcTargetInfo { 5300 public: 5301 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5302 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5303 } 5304 5305 void getTargetDefines(const LangOptions &Opts, 5306 MacroBuilder &Builder) const override { 5307 SparcTargetInfo::getTargetDefines(Opts, Builder); 5308 Builder.defineMacro("__sparcv8"); 5309 } 5310 }; 5311 5312 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 5313 class SparcV9TargetInfo : public SparcTargetInfo { 5314 public: 5315 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5316 // FIXME: Support Sparc quad-precision long double? 5317 DescriptionString = "E-m:e-i64:64-n32:64-S128"; 5318 // This is an LP64 platform. 5319 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5320 5321 // OpenBSD uses long long for int64_t and intmax_t. 5322 if (getTriple().getOS() == llvm::Triple::OpenBSD) 5323 IntMaxType = SignedLongLong; 5324 else 5325 IntMaxType = SignedLong; 5326 Int64Type = IntMaxType; 5327 5328 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 5329 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 5330 LongDoubleWidth = 128; 5331 LongDoubleAlign = 128; 5332 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5333 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5334 } 5335 5336 void getTargetDefines(const LangOptions &Opts, 5337 MacroBuilder &Builder) const override { 5338 SparcTargetInfo::getTargetDefines(Opts, Builder); 5339 Builder.defineMacro("__sparcv9"); 5340 Builder.defineMacro("__arch64__"); 5341 // Solaris doesn't need these variants, but the BSDs do. 5342 if (getTriple().getOS() != llvm::Triple::Solaris) { 5343 Builder.defineMacro("__sparc64__"); 5344 Builder.defineMacro("__sparc_v9__"); 5345 Builder.defineMacro("__sparcv9__"); 5346 } 5347 } 5348 5349 bool setCPU(const std::string &Name) override { 5350 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5351 .Case("v9", true) 5352 .Case("ultrasparc", true) 5353 .Case("ultrasparc3", true) 5354 .Case("niagara", true) 5355 .Case("niagara2", true) 5356 .Case("niagara3", true) 5357 .Case("niagara4", true) 5358 .Default(false); 5359 5360 // No need to store the CPU yet. There aren't any CPU-specific 5361 // macros to define. 5362 return CPUKnown; 5363 } 5364 }; 5365 5366 } // end anonymous namespace. 5367 5368 namespace { 5369 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 5370 public: 5371 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 5372 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 5373 SizeType = UnsignedInt; 5374 PtrDiffType = SignedInt; 5375 } 5376 }; 5377 } // end anonymous namespace. 5378 5379 namespace { 5380 class SystemZTargetInfo : public TargetInfo { 5381 static const char *const GCCRegNames[]; 5382 5383 public: 5384 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5385 TLSSupported = true; 5386 IntWidth = IntAlign = 32; 5387 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5388 PointerWidth = PointerAlign = 64; 5389 LongDoubleWidth = 128; 5390 LongDoubleAlign = 64; 5391 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5392 MinGlobalAlign = 16; 5393 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5394 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5395 } 5396 void getTargetDefines(const LangOptions &Opts, 5397 MacroBuilder &Builder) const override { 5398 Builder.defineMacro("__s390__"); 5399 Builder.defineMacro("__s390x__"); 5400 Builder.defineMacro("__zarch__"); 5401 Builder.defineMacro("__LONG_DOUBLE_128__"); 5402 } 5403 void getTargetBuiltins(const Builtin::Info *&Records, 5404 unsigned &NumRecords) const override { 5405 // FIXME: Implement. 5406 Records = nullptr; 5407 NumRecords = 0; 5408 } 5409 5410 void getGCCRegNames(const char *const *&Names, 5411 unsigned &NumNames) const override; 5412 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5413 unsigned &NumAliases) const override { 5414 // No aliases. 5415 Aliases = nullptr; 5416 NumAliases = 0; 5417 } 5418 bool validateAsmConstraint(const char *&Name, 5419 TargetInfo::ConstraintInfo &info) const override; 5420 const char *getClobbers() const override { 5421 // FIXME: Is this really right? 5422 return ""; 5423 } 5424 BuiltinVaListKind getBuiltinVaListKind() const override { 5425 return TargetInfo::SystemZBuiltinVaList; 5426 } 5427 bool setCPU(const std::string &Name) override { 5428 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5429 .Case("z10", true) 5430 .Case("z196", true) 5431 .Case("zEC12", true) 5432 .Default(false); 5433 5434 // No need to store the CPU yet. There aren't any CPU-specific 5435 // macros to define. 5436 return CPUKnown; 5437 } 5438 }; 5439 5440 const char *const SystemZTargetInfo::GCCRegNames[] = { 5441 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5442 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5443 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 5444 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 5445 }; 5446 5447 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 5448 unsigned &NumNames) const { 5449 Names = GCCRegNames; 5450 NumNames = llvm::array_lengthof(GCCRegNames); 5451 } 5452 5453 bool SystemZTargetInfo:: 5454 validateAsmConstraint(const char *&Name, 5455 TargetInfo::ConstraintInfo &Info) const { 5456 switch (*Name) { 5457 default: 5458 return false; 5459 5460 case 'a': // Address register 5461 case 'd': // Data register (equivalent to 'r') 5462 case 'f': // Floating-point register 5463 Info.setAllowsRegister(); 5464 return true; 5465 5466 case 'I': // Unsigned 8-bit constant 5467 case 'J': // Unsigned 12-bit constant 5468 case 'K': // Signed 16-bit constant 5469 case 'L': // Signed 20-bit displacement (on all targets we support) 5470 case 'M': // 0x7fffffff 5471 return true; 5472 5473 case 'Q': // Memory with base and unsigned 12-bit displacement 5474 case 'R': // Likewise, plus an index 5475 case 'S': // Memory with base and signed 20-bit displacement 5476 case 'T': // Likewise, plus an index 5477 Info.setAllowsMemory(); 5478 return true; 5479 } 5480 } 5481 } 5482 5483 namespace { 5484 class MSP430TargetInfo : public TargetInfo { 5485 static const char * const GCCRegNames[]; 5486 public: 5487 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5488 BigEndian = false; 5489 TLSSupported = false; 5490 IntWidth = 16; IntAlign = 16; 5491 LongWidth = 32; LongLongWidth = 64; 5492 LongAlign = LongLongAlign = 16; 5493 PointerWidth = 16; PointerAlign = 16; 5494 SuitableAlign = 16; 5495 SizeType = UnsignedInt; 5496 IntMaxType = SignedLongLong; 5497 IntPtrType = SignedInt; 5498 PtrDiffType = SignedInt; 5499 SigAtomicType = SignedLong; 5500 DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 5501 } 5502 void getTargetDefines(const LangOptions &Opts, 5503 MacroBuilder &Builder) const override { 5504 Builder.defineMacro("MSP430"); 5505 Builder.defineMacro("__MSP430__"); 5506 // FIXME: defines for different 'flavours' of MCU 5507 } 5508 void getTargetBuiltins(const Builtin::Info *&Records, 5509 unsigned &NumRecords) const override { 5510 // FIXME: Implement. 5511 Records = nullptr; 5512 NumRecords = 0; 5513 } 5514 bool hasFeature(StringRef Feature) const override { 5515 return Feature == "msp430"; 5516 } 5517 void getGCCRegNames(const char * const *&Names, 5518 unsigned &NumNames) const override; 5519 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5520 unsigned &NumAliases) const override { 5521 // No aliases. 5522 Aliases = nullptr; 5523 NumAliases = 0; 5524 } 5525 bool 5526 validateAsmConstraint(const char *&Name, 5527 TargetInfo::ConstraintInfo &info) const override { 5528 // FIXME: implement 5529 switch (*Name) { 5530 case 'K': // the constant 1 5531 case 'L': // constant -1^20 .. 1^19 5532 case 'M': // constant 1-4: 5533 return true; 5534 } 5535 // No target constraints for now. 5536 return false; 5537 } 5538 const char *getClobbers() const override { 5539 // FIXME: Is this really right? 5540 return ""; 5541 } 5542 BuiltinVaListKind getBuiltinVaListKind() const override { 5543 // FIXME: implement 5544 return TargetInfo::CharPtrBuiltinVaList; 5545 } 5546 }; 5547 5548 const char * const MSP430TargetInfo::GCCRegNames[] = { 5549 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5550 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 5551 }; 5552 5553 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 5554 unsigned &NumNames) const { 5555 Names = GCCRegNames; 5556 NumNames = llvm::array_lengthof(GCCRegNames); 5557 } 5558 } 5559 5560 namespace { 5561 5562 // LLVM and Clang cannot be used directly to output native binaries for 5563 // target, but is used to compile C code to llvm bitcode with correct 5564 // type and alignment information. 5565 // 5566 // TCE uses the llvm bitcode as input and uses it for generating customized 5567 // target processor and program binary. TCE co-design environment is 5568 // publicly available in http://tce.cs.tut.fi 5569 5570 static const unsigned TCEOpenCLAddrSpaceMap[] = { 5571 3, // opencl_global 5572 4, // opencl_local 5573 5, // opencl_constant 5574 // FIXME: generic has to be added to the target 5575 0, // opencl_generic 5576 0, // cuda_device 5577 0, // cuda_constant 5578 0 // cuda_shared 5579 }; 5580 5581 class TCETargetInfo : public TargetInfo{ 5582 public: 5583 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5584 TLSSupported = false; 5585 IntWidth = 32; 5586 LongWidth = LongLongWidth = 32; 5587 PointerWidth = 32; 5588 IntAlign = 32; 5589 LongAlign = LongLongAlign = 32; 5590 PointerAlign = 32; 5591 SuitableAlign = 32; 5592 SizeType = UnsignedInt; 5593 IntMaxType = SignedLong; 5594 IntPtrType = SignedInt; 5595 PtrDiffType = SignedInt; 5596 FloatWidth = 32; 5597 FloatAlign = 32; 5598 DoubleWidth = 32; 5599 DoubleAlign = 32; 5600 LongDoubleWidth = 32; 5601 LongDoubleAlign = 32; 5602 FloatFormat = &llvm::APFloat::IEEEsingle; 5603 DoubleFormat = &llvm::APFloat::IEEEsingle; 5604 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 5605 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 5606 "-f64:32-v64:32-v128:32-a:0:32-n32"; 5607 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 5608 UseAddrSpaceMapMangling = true; 5609 } 5610 5611 void getTargetDefines(const LangOptions &Opts, 5612 MacroBuilder &Builder) const override { 5613 DefineStd(Builder, "tce", Opts); 5614 Builder.defineMacro("__TCE__"); 5615 Builder.defineMacro("__TCE_V1__"); 5616 } 5617 bool hasFeature(StringRef Feature) const override { 5618 return Feature == "tce"; 5619 } 5620 5621 void getTargetBuiltins(const Builtin::Info *&Records, 5622 unsigned &NumRecords) const override {} 5623 const char *getClobbers() const override { 5624 return ""; 5625 } 5626 BuiltinVaListKind getBuiltinVaListKind() const override { 5627 return TargetInfo::VoidPtrBuiltinVaList; 5628 } 5629 void getGCCRegNames(const char * const *&Names, 5630 unsigned &NumNames) const override {} 5631 bool validateAsmConstraint(const char *&Name, 5632 TargetInfo::ConstraintInfo &info) const override{ 5633 return true; 5634 } 5635 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5636 unsigned &NumAliases) const override {} 5637 }; 5638 } 5639 5640 namespace { 5641 class MipsTargetInfoBase : public TargetInfo { 5642 virtual void setDescriptionString() = 0; 5643 5644 static const Builtin::Info BuiltinInfo[]; 5645 std::string CPU; 5646 bool IsMips16; 5647 bool IsMicromips; 5648 bool IsNan2008; 5649 bool IsSingleFloat; 5650 enum MipsFloatABI { 5651 HardFloat, SoftFloat 5652 } FloatABI; 5653 enum DspRevEnum { 5654 NoDSP, DSP1, DSP2 5655 } DspRev; 5656 bool HasMSA; 5657 5658 protected: 5659 bool HasFP64; 5660 std::string ABI; 5661 5662 public: 5663 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 5664 const std::string &CPUStr) 5665 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 5666 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 5667 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {} 5668 5669 bool isNaN2008Default() const { 5670 return CPU == "mips32r6" || CPU == "mips64r6"; 5671 } 5672 5673 bool isFP64Default() const { 5674 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 5675 } 5676 5677 StringRef getABI() const override { return ABI; } 5678 bool setCPU(const std::string &Name) override { 5679 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 5680 getTriple().getArch() == llvm::Triple::mipsel; 5681 CPU = Name; 5682 return llvm::StringSwitch<bool>(Name) 5683 .Case("mips1", IsMips32) 5684 .Case("mips2", IsMips32) 5685 .Case("mips3", true) 5686 .Case("mips4", true) 5687 .Case("mips5", true) 5688 .Case("mips32", IsMips32) 5689 .Case("mips32r2", IsMips32) 5690 .Case("mips32r6", IsMips32) 5691 .Case("mips64", true) 5692 .Case("mips64r2", true) 5693 .Case("mips64r6", true) 5694 .Case("octeon", true) 5695 .Default(false); 5696 } 5697 const std::string& getCPU() const { return CPU; } 5698 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5699 if (CPU == "octeon") 5700 Features["mips64r2"] = Features["cnmips"] = true; 5701 else 5702 Features[CPU] = true; 5703 } 5704 5705 void getTargetDefines(const LangOptions &Opts, 5706 MacroBuilder &Builder) const override { 5707 Builder.defineMacro("__mips__"); 5708 Builder.defineMacro("_mips"); 5709 if (Opts.GNUMode) 5710 Builder.defineMacro("mips"); 5711 5712 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5713 5714 switch (FloatABI) { 5715 case HardFloat: 5716 Builder.defineMacro("__mips_hard_float", Twine(1)); 5717 break; 5718 case SoftFloat: 5719 Builder.defineMacro("__mips_soft_float", Twine(1)); 5720 break; 5721 } 5722 5723 if (IsSingleFloat) 5724 Builder.defineMacro("__mips_single_float", Twine(1)); 5725 5726 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 5727 Builder.defineMacro("_MIPS_FPSET", 5728 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 5729 5730 if (IsMips16) 5731 Builder.defineMacro("__mips16", Twine(1)); 5732 5733 if (IsMicromips) 5734 Builder.defineMacro("__mips_micromips", Twine(1)); 5735 5736 if (IsNan2008) 5737 Builder.defineMacro("__mips_nan2008", Twine(1)); 5738 5739 switch (DspRev) { 5740 default: 5741 break; 5742 case DSP1: 5743 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 5744 Builder.defineMacro("__mips_dsp", Twine(1)); 5745 break; 5746 case DSP2: 5747 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 5748 Builder.defineMacro("__mips_dspr2", Twine(1)); 5749 Builder.defineMacro("__mips_dsp", Twine(1)); 5750 break; 5751 } 5752 5753 if (HasMSA) 5754 Builder.defineMacro("__mips_msa", Twine(1)); 5755 5756 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 5757 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 5758 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 5759 5760 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 5761 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 5762 } 5763 5764 void getTargetBuiltins(const Builtin::Info *&Records, 5765 unsigned &NumRecords) const override { 5766 Records = BuiltinInfo; 5767 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 5768 } 5769 bool hasFeature(StringRef Feature) const override { 5770 return llvm::StringSwitch<bool>(Feature) 5771 .Case("mips", true) 5772 .Case("fp64", HasFP64) 5773 .Default(false); 5774 } 5775 BuiltinVaListKind getBuiltinVaListKind() const override { 5776 return TargetInfo::VoidPtrBuiltinVaList; 5777 } 5778 void getGCCRegNames(const char * const *&Names, 5779 unsigned &NumNames) const override { 5780 static const char *const GCCRegNames[] = { 5781 // CPU register names 5782 // Must match second column of GCCRegAliases 5783 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 5784 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 5785 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 5786 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 5787 // Floating point register names 5788 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 5789 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 5790 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 5791 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 5792 // Hi/lo and condition register names 5793 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 5794 "$fcc5","$fcc6","$fcc7", 5795 // MSA register names 5796 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 5797 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 5798 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 5799 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 5800 // MSA control register names 5801 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 5802 "$msarequest", "$msamap", "$msaunmap" 5803 }; 5804 Names = GCCRegNames; 5805 NumNames = llvm::array_lengthof(GCCRegNames); 5806 } 5807 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5808 unsigned &NumAliases) const override = 0; 5809 bool validateAsmConstraint(const char *&Name, 5810 TargetInfo::ConstraintInfo &Info) const override { 5811 switch (*Name) { 5812 default: 5813 return false; 5814 case 'r': // CPU registers. 5815 case 'd': // Equivalent to "r" unless generating MIPS16 code. 5816 case 'y': // Equivalent to "r", backward compatibility only. 5817 case 'f': // floating-point registers. 5818 case 'c': // $25 for indirect jumps 5819 case 'l': // lo register 5820 case 'x': // hilo register pair 5821 Info.setAllowsRegister(); 5822 return true; 5823 case 'I': // Signed 16-bit constant 5824 case 'J': // Integer 0 5825 case 'K': // Unsigned 16-bit constant 5826 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 5827 case 'M': // Constants not loadable via lui, addiu, or ori 5828 case 'N': // Constant -1 to -65535 5829 case 'O': // A signed 15-bit constant 5830 case 'P': // A constant between 1 go 65535 5831 return true; 5832 case 'R': // An address that can be used in a non-macro load or store 5833 Info.setAllowsMemory(); 5834 return true; 5835 } 5836 } 5837 5838 const char *getClobbers() const override { 5839 // In GCC, $1 is not widely used in generated code (it's used only in a few 5840 // specific situations), so there is no real need for users to add it to 5841 // the clobbers list if they want to use it in their inline assembly code. 5842 // 5843 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 5844 // code generation, so using it in inline assembly without adding it to the 5845 // clobbers list can cause conflicts between the inline assembly code and 5846 // the surrounding generated code. 5847 // 5848 // Another problem is that LLVM is allowed to choose $1 for inline assembly 5849 // operands, which will conflict with the ".set at" assembler option (which 5850 // we use only for inline assembly, in order to maintain compatibility with 5851 // GCC) and will also conflict with the user's usage of $1. 5852 // 5853 // The easiest way to avoid these conflicts and keep $1 as an allocatable 5854 // register for generated code is to automatically clobber $1 for all inline 5855 // assembly code. 5856 // 5857 // FIXME: We should automatically clobber $1 only for inline assembly code 5858 // which actually uses it. This would allow LLVM to use $1 for inline 5859 // assembly operands if the user's assembly code doesn't use it. 5860 return "~{$1}"; 5861 } 5862 5863 bool handleTargetFeatures(std::vector<std::string> &Features, 5864 DiagnosticsEngine &Diags) override { 5865 IsMips16 = false; 5866 IsMicromips = false; 5867 IsNan2008 = isNaN2008Default(); 5868 IsSingleFloat = false; 5869 FloatABI = HardFloat; 5870 DspRev = NoDSP; 5871 HasFP64 = isFP64Default(); 5872 5873 for (std::vector<std::string>::iterator it = Features.begin(), 5874 ie = Features.end(); it != ie; ++it) { 5875 if (*it == "+single-float") 5876 IsSingleFloat = true; 5877 else if (*it == "+soft-float") 5878 FloatABI = SoftFloat; 5879 else if (*it == "+mips16") 5880 IsMips16 = true; 5881 else if (*it == "+micromips") 5882 IsMicromips = true; 5883 else if (*it == "+dsp") 5884 DspRev = std::max(DspRev, DSP1); 5885 else if (*it == "+dspr2") 5886 DspRev = std::max(DspRev, DSP2); 5887 else if (*it == "+msa") 5888 HasMSA = true; 5889 else if (*it == "+fp64") 5890 HasFP64 = true; 5891 else if (*it == "-fp64") 5892 HasFP64 = false; 5893 else if (*it == "+nan2008") 5894 IsNan2008 = true; 5895 else if (*it == "-nan2008") 5896 IsNan2008 = false; 5897 } 5898 5899 // Remove front-end specific options. 5900 std::vector<std::string>::iterator it = 5901 std::find(Features.begin(), Features.end(), "+soft-float"); 5902 if (it != Features.end()) 5903 Features.erase(it); 5904 5905 setDescriptionString(); 5906 5907 return true; 5908 } 5909 5910 int getEHDataRegisterNumber(unsigned RegNo) const override { 5911 if (RegNo == 0) return 4; 5912 if (RegNo == 1) return 5; 5913 return -1; 5914 } 5915 5916 bool isCLZForZeroUndef() const override { return false; } 5917 }; 5918 5919 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 5920 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5921 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5922 ALL_LANGUAGES }, 5923 #include "clang/Basic/BuiltinsMips.def" 5924 }; 5925 5926 class Mips32TargetInfoBase : public MipsTargetInfoBase { 5927 public: 5928 Mips32TargetInfoBase(const llvm::Triple &Triple) 5929 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 5930 SizeType = UnsignedInt; 5931 PtrDiffType = SignedInt; 5932 Int64Type = SignedLongLong; 5933 IntMaxType = Int64Type; 5934 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 5935 } 5936 bool setABI(const std::string &Name) override { 5937 if (Name == "o32" || Name == "eabi") { 5938 ABI = Name; 5939 return true; 5940 } 5941 return false; 5942 } 5943 void getTargetDefines(const LangOptions &Opts, 5944 MacroBuilder &Builder) const override { 5945 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5946 5947 Builder.defineMacro("__mips", "32"); 5948 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 5949 5950 const std::string& CPUStr = getCPU(); 5951 if (CPUStr == "mips32") 5952 Builder.defineMacro("__mips_isa_rev", "1"); 5953 else if (CPUStr == "mips32r2") 5954 Builder.defineMacro("__mips_isa_rev", "2"); 5955 else if (CPUStr == "mips32r6") 5956 Builder.defineMacro("__mips_isa_rev", "6"); 5957 5958 if (ABI == "o32") { 5959 Builder.defineMacro("__mips_o32"); 5960 Builder.defineMacro("_ABIO32", "1"); 5961 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 5962 } 5963 else if (ABI == "eabi") 5964 Builder.defineMacro("__mips_eabi"); 5965 else 5966 llvm_unreachable("Invalid ABI for Mips32."); 5967 } 5968 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5969 unsigned &NumAliases) const override { 5970 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5971 { { "at" }, "$1" }, 5972 { { "v0" }, "$2" }, 5973 { { "v1" }, "$3" }, 5974 { { "a0" }, "$4" }, 5975 { { "a1" }, "$5" }, 5976 { { "a2" }, "$6" }, 5977 { { "a3" }, "$7" }, 5978 { { "t0" }, "$8" }, 5979 { { "t1" }, "$9" }, 5980 { { "t2" }, "$10" }, 5981 { { "t3" }, "$11" }, 5982 { { "t4" }, "$12" }, 5983 { { "t5" }, "$13" }, 5984 { { "t6" }, "$14" }, 5985 { { "t7" }, "$15" }, 5986 { { "s0" }, "$16" }, 5987 { { "s1" }, "$17" }, 5988 { { "s2" }, "$18" }, 5989 { { "s3" }, "$19" }, 5990 { { "s4" }, "$20" }, 5991 { { "s5" }, "$21" }, 5992 { { "s6" }, "$22" }, 5993 { { "s7" }, "$23" }, 5994 { { "t8" }, "$24" }, 5995 { { "t9" }, "$25" }, 5996 { { "k0" }, "$26" }, 5997 { { "k1" }, "$27" }, 5998 { { "gp" }, "$28" }, 5999 { { "sp","$sp" }, "$29" }, 6000 { { "fp","$fp" }, "$30" }, 6001 { { "ra" }, "$31" } 6002 }; 6003 Aliases = GCCRegAliases; 6004 NumAliases = llvm::array_lengthof(GCCRegAliases); 6005 } 6006 }; 6007 6008 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6009 void setDescriptionString() override { 6010 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6011 } 6012 6013 public: 6014 Mips32EBTargetInfo(const llvm::Triple &Triple) 6015 : Mips32TargetInfoBase(Triple) { 6016 } 6017 void getTargetDefines(const LangOptions &Opts, 6018 MacroBuilder &Builder) const override { 6019 DefineStd(Builder, "MIPSEB", Opts); 6020 Builder.defineMacro("_MIPSEB"); 6021 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6022 } 6023 }; 6024 6025 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6026 void setDescriptionString() override { 6027 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6028 } 6029 6030 public: 6031 Mips32ELTargetInfo(const llvm::Triple &Triple) 6032 : Mips32TargetInfoBase(Triple) { 6033 BigEndian = false; 6034 } 6035 void getTargetDefines(const LangOptions &Opts, 6036 MacroBuilder &Builder) const override { 6037 DefineStd(Builder, "MIPSEL", Opts); 6038 Builder.defineMacro("_MIPSEL"); 6039 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6040 } 6041 }; 6042 6043 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6044 public: 6045 Mips64TargetInfoBase(const llvm::Triple &Triple) 6046 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6047 LongDoubleWidth = LongDoubleAlign = 128; 6048 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6049 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6050 LongDoubleWidth = LongDoubleAlign = 64; 6051 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6052 } 6053 setN64ABITypes(); 6054 SuitableAlign = 128; 6055 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6056 } 6057 6058 void setN64ABITypes() { 6059 LongWidth = LongAlign = 64; 6060 PointerWidth = PointerAlign = 64; 6061 SizeType = UnsignedLong; 6062 PtrDiffType = SignedLong; 6063 Int64Type = SignedLong; 6064 IntMaxType = Int64Type; 6065 } 6066 6067 void setN32ABITypes() { 6068 LongWidth = LongAlign = 32; 6069 PointerWidth = PointerAlign = 32; 6070 SizeType = UnsignedInt; 6071 PtrDiffType = SignedInt; 6072 Int64Type = SignedLongLong; 6073 IntMaxType = Int64Type; 6074 } 6075 6076 bool setABI(const std::string &Name) override { 6077 if (Name == "n32") { 6078 setN32ABITypes(); 6079 ABI = Name; 6080 return true; 6081 } 6082 if (Name == "n64") { 6083 setN64ABITypes(); 6084 ABI = Name; 6085 return true; 6086 } 6087 return false; 6088 } 6089 6090 void getTargetDefines(const LangOptions &Opts, 6091 MacroBuilder &Builder) const override { 6092 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6093 6094 Builder.defineMacro("__mips", "64"); 6095 Builder.defineMacro("__mips64"); 6096 Builder.defineMacro("__mips64__"); 6097 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 6098 6099 const std::string& CPUStr = getCPU(); 6100 if (CPUStr == "mips64") 6101 Builder.defineMacro("__mips_isa_rev", "1"); 6102 else if (CPUStr == "mips64r2") 6103 Builder.defineMacro("__mips_isa_rev", "2"); 6104 else if (CPUStr == "mips64r6") 6105 Builder.defineMacro("__mips_isa_rev", "6"); 6106 6107 if (ABI == "n32") { 6108 Builder.defineMacro("__mips_n32"); 6109 Builder.defineMacro("_ABIN32", "2"); 6110 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 6111 } 6112 else if (ABI == "n64") { 6113 Builder.defineMacro("__mips_n64"); 6114 Builder.defineMacro("_ABI64", "3"); 6115 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 6116 } 6117 else 6118 llvm_unreachable("Invalid ABI for Mips64."); 6119 } 6120 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6121 unsigned &NumAliases) const override { 6122 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6123 { { "at" }, "$1" }, 6124 { { "v0" }, "$2" }, 6125 { { "v1" }, "$3" }, 6126 { { "a0" }, "$4" }, 6127 { { "a1" }, "$5" }, 6128 { { "a2" }, "$6" }, 6129 { { "a3" }, "$7" }, 6130 { { "a4" }, "$8" }, 6131 { { "a5" }, "$9" }, 6132 { { "a6" }, "$10" }, 6133 { { "a7" }, "$11" }, 6134 { { "t0" }, "$12" }, 6135 { { "t1" }, "$13" }, 6136 { { "t2" }, "$14" }, 6137 { { "t3" }, "$15" }, 6138 { { "s0" }, "$16" }, 6139 { { "s1" }, "$17" }, 6140 { { "s2" }, "$18" }, 6141 { { "s3" }, "$19" }, 6142 { { "s4" }, "$20" }, 6143 { { "s5" }, "$21" }, 6144 { { "s6" }, "$22" }, 6145 { { "s7" }, "$23" }, 6146 { { "t8" }, "$24" }, 6147 { { "t9" }, "$25" }, 6148 { { "k0" }, "$26" }, 6149 { { "k1" }, "$27" }, 6150 { { "gp" }, "$28" }, 6151 { { "sp","$sp" }, "$29" }, 6152 { { "fp","$fp" }, "$30" }, 6153 { { "ra" }, "$31" } 6154 }; 6155 Aliases = GCCRegAliases; 6156 NumAliases = llvm::array_lengthof(GCCRegAliases); 6157 } 6158 6159 bool hasInt128Type() const override { return true; } 6160 }; 6161 6162 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 6163 void setDescriptionString() override { 6164 if (ABI == "n32") 6165 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6166 else 6167 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6168 6169 } 6170 6171 public: 6172 Mips64EBTargetInfo(const llvm::Triple &Triple) 6173 : Mips64TargetInfoBase(Triple) {} 6174 void getTargetDefines(const LangOptions &Opts, 6175 MacroBuilder &Builder) const override { 6176 DefineStd(Builder, "MIPSEB", Opts); 6177 Builder.defineMacro("_MIPSEB"); 6178 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6179 } 6180 }; 6181 6182 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 6183 void setDescriptionString() override { 6184 if (ABI == "n32") 6185 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6186 else 6187 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6188 } 6189 public: 6190 Mips64ELTargetInfo(const llvm::Triple &Triple) 6191 : Mips64TargetInfoBase(Triple) { 6192 // Default ABI is n64. 6193 BigEndian = false; 6194 } 6195 void getTargetDefines(const LangOptions &Opts, 6196 MacroBuilder &Builder) const override { 6197 DefineStd(Builder, "MIPSEL", Opts); 6198 Builder.defineMacro("_MIPSEL"); 6199 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6200 } 6201 }; 6202 } // end anonymous namespace. 6203 6204 namespace { 6205 class PNaClTargetInfo : public TargetInfo { 6206 public: 6207 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6208 BigEndian = false; 6209 this->UserLabelPrefix = ""; 6210 this->LongAlign = 32; 6211 this->LongWidth = 32; 6212 this->PointerAlign = 32; 6213 this->PointerWidth = 32; 6214 this->IntMaxType = TargetInfo::SignedLongLong; 6215 this->Int64Type = TargetInfo::SignedLongLong; 6216 this->DoubleAlign = 64; 6217 this->LongDoubleWidth = 64; 6218 this->LongDoubleAlign = 64; 6219 this->SizeType = TargetInfo::UnsignedInt; 6220 this->PtrDiffType = TargetInfo::SignedInt; 6221 this->IntPtrType = TargetInfo::SignedInt; 6222 this->RegParmMax = 0; // Disallow regparm 6223 } 6224 6225 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 6226 } 6227 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 6228 Builder.defineMacro("__le32__"); 6229 Builder.defineMacro("__pnacl__"); 6230 } 6231 void getTargetDefines(const LangOptions &Opts, 6232 MacroBuilder &Builder) const override { 6233 getArchDefines(Opts, Builder); 6234 } 6235 bool hasFeature(StringRef Feature) const override { 6236 return Feature == "pnacl"; 6237 } 6238 void getTargetBuiltins(const Builtin::Info *&Records, 6239 unsigned &NumRecords) const override { 6240 } 6241 BuiltinVaListKind getBuiltinVaListKind() const override { 6242 return TargetInfo::PNaClABIBuiltinVaList; 6243 } 6244 void getGCCRegNames(const char * const *&Names, 6245 unsigned &NumNames) const override; 6246 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6247 unsigned &NumAliases) const override; 6248 bool validateAsmConstraint(const char *&Name, 6249 TargetInfo::ConstraintInfo &Info) const override { 6250 return false; 6251 } 6252 6253 const char *getClobbers() const override { 6254 return ""; 6255 } 6256 }; 6257 6258 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 6259 unsigned &NumNames) const { 6260 Names = nullptr; 6261 NumNames = 0; 6262 } 6263 6264 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 6265 unsigned &NumAliases) const { 6266 Aliases = nullptr; 6267 NumAliases = 0; 6268 } 6269 } // end anonymous namespace. 6270 6271 namespace { 6272 class Le64TargetInfo : public TargetInfo { 6273 static const Builtin::Info BuiltinInfo[]; 6274 6275 public: 6276 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6277 BigEndian = false; 6278 NoAsmVariants = true; 6279 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6280 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6281 DescriptionString = 6282 "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 6283 } 6284 6285 void getTargetDefines(const LangOptions &Opts, 6286 MacroBuilder &Builder) const override { 6287 DefineStd(Builder, "unix", Opts); 6288 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 6289 Builder.defineMacro("__ELF__"); 6290 } 6291 void getTargetBuiltins(const Builtin::Info *&Records, 6292 unsigned &NumRecords) const override { 6293 Records = BuiltinInfo; 6294 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin; 6295 } 6296 BuiltinVaListKind getBuiltinVaListKind() const override { 6297 return TargetInfo::PNaClABIBuiltinVaList; 6298 } 6299 const char *getClobbers() const override { return ""; } 6300 void getGCCRegNames(const char *const *&Names, 6301 unsigned &NumNames) const override { 6302 Names = nullptr; 6303 NumNames = 0; 6304 } 6305 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6306 unsigned &NumAliases) const override { 6307 Aliases = nullptr; 6308 NumAliases = 0; 6309 } 6310 bool validateAsmConstraint(const char *&Name, 6311 TargetInfo::ConstraintInfo &Info) const override { 6312 return false; 6313 } 6314 6315 bool hasProtectedVisibility() const override { return false; } 6316 }; 6317 } // end anonymous namespace. 6318 6319 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 6320 #define BUILTIN(ID, TYPE, ATTRS) \ 6321 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6322 #include "clang/Basic/BuiltinsLe64.def" 6323 }; 6324 6325 namespace { 6326 static const unsigned SPIRAddrSpaceMap[] = { 6327 1, // opencl_global 6328 3, // opencl_local 6329 2, // opencl_constant 6330 4, // opencl_generic 6331 0, // cuda_device 6332 0, // cuda_constant 6333 0 // cuda_shared 6334 }; 6335 class SPIRTargetInfo : public TargetInfo { 6336 public: 6337 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6338 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 6339 "SPIR target must use unknown OS"); 6340 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 6341 "SPIR target must use unknown environment type"); 6342 BigEndian = false; 6343 TLSSupported = false; 6344 LongWidth = LongAlign = 64; 6345 AddrSpaceMap = &SPIRAddrSpaceMap; 6346 UseAddrSpaceMapMangling = true; 6347 // Define available target features 6348 // These must be defined in sorted order! 6349 NoAsmVariants = true; 6350 } 6351 void getTargetDefines(const LangOptions &Opts, 6352 MacroBuilder &Builder) const override { 6353 DefineStd(Builder, "SPIR", Opts); 6354 } 6355 bool hasFeature(StringRef Feature) const override { 6356 return Feature == "spir"; 6357 } 6358 6359 void getTargetBuiltins(const Builtin::Info *&Records, 6360 unsigned &NumRecords) const override {} 6361 const char *getClobbers() const override { 6362 return ""; 6363 } 6364 void getGCCRegNames(const char * const *&Names, 6365 unsigned &NumNames) const override {} 6366 bool 6367 validateAsmConstraint(const char *&Name, 6368 TargetInfo::ConstraintInfo &info) const override { 6369 return true; 6370 } 6371 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6372 unsigned &NumAliases) const override {} 6373 BuiltinVaListKind getBuiltinVaListKind() const override { 6374 return TargetInfo::VoidPtrBuiltinVaList; 6375 } 6376 6377 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6378 return (CC == CC_SpirFunction || 6379 CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning; 6380 } 6381 6382 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 6383 return CC_SpirFunction; 6384 } 6385 }; 6386 6387 6388 class SPIR32TargetInfo : public SPIRTargetInfo { 6389 public: 6390 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6391 PointerWidth = PointerAlign = 32; 6392 SizeType = TargetInfo::UnsignedInt; 6393 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 6394 DescriptionString 6395 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 6396 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6397 } 6398 void getTargetDefines(const LangOptions &Opts, 6399 MacroBuilder &Builder) const override { 6400 DefineStd(Builder, "SPIR32", Opts); 6401 } 6402 }; 6403 6404 class SPIR64TargetInfo : public SPIRTargetInfo { 6405 public: 6406 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6407 PointerWidth = PointerAlign = 64; 6408 SizeType = TargetInfo::UnsignedLong; 6409 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 6410 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 6411 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6412 } 6413 void getTargetDefines(const LangOptions &Opts, 6414 MacroBuilder &Builder) const override { 6415 DefineStd(Builder, "SPIR64", Opts); 6416 } 6417 }; 6418 } 6419 6420 namespace { 6421 class XCoreTargetInfo : public TargetInfo { 6422 static const Builtin::Info BuiltinInfo[]; 6423 public: 6424 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6425 BigEndian = false; 6426 NoAsmVariants = true; 6427 LongLongAlign = 32; 6428 SuitableAlign = 32; 6429 DoubleAlign = LongDoubleAlign = 32; 6430 SizeType = UnsignedInt; 6431 PtrDiffType = SignedInt; 6432 IntPtrType = SignedInt; 6433 WCharType = UnsignedChar; 6434 WIntType = UnsignedInt; 6435 UseZeroLengthBitfieldAlignment = true; 6436 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 6437 "-f64:32-a:0:32-n32"; 6438 } 6439 void getTargetDefines(const LangOptions &Opts, 6440 MacroBuilder &Builder) const override { 6441 Builder.defineMacro("__XS1B__"); 6442 } 6443 void getTargetBuiltins(const Builtin::Info *&Records, 6444 unsigned &NumRecords) const override { 6445 Records = BuiltinInfo; 6446 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 6447 } 6448 BuiltinVaListKind getBuiltinVaListKind() const override { 6449 return TargetInfo::VoidPtrBuiltinVaList; 6450 } 6451 const char *getClobbers() const override { 6452 return ""; 6453 } 6454 void getGCCRegNames(const char * const *&Names, 6455 unsigned &NumNames) const override { 6456 static const char * const GCCRegNames[] = { 6457 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6458 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 6459 }; 6460 Names = GCCRegNames; 6461 NumNames = llvm::array_lengthof(GCCRegNames); 6462 } 6463 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6464 unsigned &NumAliases) const override { 6465 Aliases = nullptr; 6466 NumAliases = 0; 6467 } 6468 bool validateAsmConstraint(const char *&Name, 6469 TargetInfo::ConstraintInfo &Info) const override { 6470 return false; 6471 } 6472 int getEHDataRegisterNumber(unsigned RegNo) const override { 6473 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 6474 return (RegNo < 2)? RegNo : -1; 6475 } 6476 }; 6477 6478 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 6479 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6480 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 6481 ALL_LANGUAGES }, 6482 #include "clang/Basic/BuiltinsXCore.def" 6483 }; 6484 } // end anonymous namespace. 6485 6486 6487 //===----------------------------------------------------------------------===// 6488 // Driver code 6489 //===----------------------------------------------------------------------===// 6490 6491 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 6492 llvm::Triple::OSType os = Triple.getOS(); 6493 6494 switch (Triple.getArch()) { 6495 default: 6496 return nullptr; 6497 6498 case llvm::Triple::xcore: 6499 return new XCoreTargetInfo(Triple); 6500 6501 case llvm::Triple::hexagon: 6502 return new HexagonTargetInfo(Triple); 6503 6504 case llvm::Triple::aarch64: 6505 if (Triple.isOSDarwin()) 6506 return new DarwinAArch64TargetInfo(Triple); 6507 6508 switch (os) { 6509 case llvm::Triple::FreeBSD: 6510 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 6511 case llvm::Triple::Linux: 6512 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 6513 case llvm::Triple::NetBSD: 6514 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 6515 default: 6516 return new AArch64leTargetInfo(Triple); 6517 } 6518 6519 case llvm::Triple::aarch64_be: 6520 switch (os) { 6521 case llvm::Triple::FreeBSD: 6522 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 6523 case llvm::Triple::Linux: 6524 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 6525 case llvm::Triple::NetBSD: 6526 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 6527 default: 6528 return new AArch64beTargetInfo(Triple); 6529 } 6530 6531 case llvm::Triple::arm: 6532 case llvm::Triple::thumb: 6533 if (Triple.isOSBinFormatMachO()) 6534 return new DarwinARMTargetInfo(Triple); 6535 6536 switch (os) { 6537 case llvm::Triple::Linux: 6538 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 6539 case llvm::Triple::FreeBSD: 6540 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 6541 case llvm::Triple::NetBSD: 6542 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 6543 case llvm::Triple::OpenBSD: 6544 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 6545 case llvm::Triple::Bitrig: 6546 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 6547 case llvm::Triple::RTEMS: 6548 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 6549 case llvm::Triple::NaCl: 6550 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 6551 case llvm::Triple::Win32: 6552 switch (Triple.getEnvironment()) { 6553 default: 6554 return new ARMleTargetInfo(Triple); 6555 case llvm::Triple::Itanium: 6556 return new ItaniumWindowsARMleTargetInfo(Triple); 6557 case llvm::Triple::MSVC: 6558 return new MicrosoftARMleTargetInfo(Triple); 6559 } 6560 default: 6561 return new ARMleTargetInfo(Triple); 6562 } 6563 6564 case llvm::Triple::armeb: 6565 case llvm::Triple::thumbeb: 6566 if (Triple.isOSDarwin()) 6567 return new DarwinARMTargetInfo(Triple); 6568 6569 switch (os) { 6570 case llvm::Triple::Linux: 6571 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 6572 case llvm::Triple::FreeBSD: 6573 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 6574 case llvm::Triple::NetBSD: 6575 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 6576 case llvm::Triple::OpenBSD: 6577 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 6578 case llvm::Triple::Bitrig: 6579 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 6580 case llvm::Triple::RTEMS: 6581 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 6582 case llvm::Triple::NaCl: 6583 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 6584 default: 6585 return new ARMbeTargetInfo(Triple); 6586 } 6587 6588 case llvm::Triple::msp430: 6589 return new MSP430TargetInfo(Triple); 6590 6591 case llvm::Triple::mips: 6592 switch (os) { 6593 case llvm::Triple::Linux: 6594 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 6595 case llvm::Triple::RTEMS: 6596 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 6597 case llvm::Triple::FreeBSD: 6598 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6599 case llvm::Triple::NetBSD: 6600 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6601 default: 6602 return new Mips32EBTargetInfo(Triple); 6603 } 6604 6605 case llvm::Triple::mipsel: 6606 switch (os) { 6607 case llvm::Triple::Linux: 6608 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 6609 case llvm::Triple::RTEMS: 6610 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 6611 case llvm::Triple::FreeBSD: 6612 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6613 case llvm::Triple::NetBSD: 6614 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6615 case llvm::Triple::NaCl: 6616 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 6617 default: 6618 return new Mips32ELTargetInfo(Triple); 6619 } 6620 6621 case llvm::Triple::mips64: 6622 switch (os) { 6623 case llvm::Triple::Linux: 6624 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 6625 case llvm::Triple::RTEMS: 6626 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 6627 case llvm::Triple::FreeBSD: 6628 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6629 case llvm::Triple::NetBSD: 6630 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6631 case llvm::Triple::OpenBSD: 6632 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6633 default: 6634 return new Mips64EBTargetInfo(Triple); 6635 } 6636 6637 case llvm::Triple::mips64el: 6638 switch (os) { 6639 case llvm::Triple::Linux: 6640 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 6641 case llvm::Triple::RTEMS: 6642 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 6643 case llvm::Triple::FreeBSD: 6644 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6645 case llvm::Triple::NetBSD: 6646 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6647 case llvm::Triple::OpenBSD: 6648 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6649 default: 6650 return new Mips64ELTargetInfo(Triple); 6651 } 6652 6653 case llvm::Triple::le32: 6654 switch (os) { 6655 case llvm::Triple::NaCl: 6656 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 6657 default: 6658 return nullptr; 6659 } 6660 6661 case llvm::Triple::le64: 6662 return new Le64TargetInfo(Triple); 6663 6664 case llvm::Triple::ppc: 6665 if (Triple.isOSDarwin()) 6666 return new DarwinPPC32TargetInfo(Triple); 6667 switch (os) { 6668 case llvm::Triple::Linux: 6669 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 6670 case llvm::Triple::FreeBSD: 6671 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 6672 case llvm::Triple::NetBSD: 6673 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 6674 case llvm::Triple::OpenBSD: 6675 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 6676 case llvm::Triple::RTEMS: 6677 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 6678 default: 6679 return new PPC32TargetInfo(Triple); 6680 } 6681 6682 case llvm::Triple::ppc64: 6683 if (Triple.isOSDarwin()) 6684 return new DarwinPPC64TargetInfo(Triple); 6685 switch (os) { 6686 case llvm::Triple::Linux: 6687 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6688 case llvm::Triple::Lv2: 6689 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 6690 case llvm::Triple::FreeBSD: 6691 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 6692 case llvm::Triple::NetBSD: 6693 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 6694 default: 6695 return new PPC64TargetInfo(Triple); 6696 } 6697 6698 case llvm::Triple::ppc64le: 6699 switch (os) { 6700 case llvm::Triple::Linux: 6701 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6702 default: 6703 return new PPC64TargetInfo(Triple); 6704 } 6705 6706 case llvm::Triple::nvptx: 6707 return new NVPTX32TargetInfo(Triple); 6708 case llvm::Triple::nvptx64: 6709 return new NVPTX64TargetInfo(Triple); 6710 6711 case llvm::Triple::amdgcn: 6712 case llvm::Triple::r600: 6713 return new R600TargetInfo(Triple); 6714 6715 case llvm::Triple::sparc: 6716 switch (os) { 6717 case llvm::Triple::Linux: 6718 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 6719 case llvm::Triple::Solaris: 6720 return new SolarisSparcV8TargetInfo(Triple); 6721 case llvm::Triple::NetBSD: 6722 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 6723 case llvm::Triple::OpenBSD: 6724 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 6725 case llvm::Triple::RTEMS: 6726 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 6727 default: 6728 return new SparcV8TargetInfo(Triple); 6729 } 6730 6731 case llvm::Triple::sparcv9: 6732 switch (os) { 6733 case llvm::Triple::Linux: 6734 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 6735 case llvm::Triple::Solaris: 6736 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 6737 case llvm::Triple::NetBSD: 6738 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 6739 case llvm::Triple::OpenBSD: 6740 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 6741 case llvm::Triple::FreeBSD: 6742 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 6743 default: 6744 return new SparcV9TargetInfo(Triple); 6745 } 6746 6747 case llvm::Triple::systemz: 6748 switch (os) { 6749 case llvm::Triple::Linux: 6750 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 6751 default: 6752 return new SystemZTargetInfo(Triple); 6753 } 6754 6755 case llvm::Triple::tce: 6756 return new TCETargetInfo(Triple); 6757 6758 case llvm::Triple::x86: 6759 if (Triple.isOSDarwin()) 6760 return new DarwinI386TargetInfo(Triple); 6761 6762 switch (os) { 6763 case llvm::Triple::Linux: 6764 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 6765 case llvm::Triple::DragonFly: 6766 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 6767 case llvm::Triple::NetBSD: 6768 return new NetBSDI386TargetInfo(Triple); 6769 case llvm::Triple::OpenBSD: 6770 return new OpenBSDI386TargetInfo(Triple); 6771 case llvm::Triple::Bitrig: 6772 return new BitrigI386TargetInfo(Triple); 6773 case llvm::Triple::FreeBSD: 6774 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 6775 case llvm::Triple::KFreeBSD: 6776 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 6777 case llvm::Triple::Minix: 6778 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 6779 case llvm::Triple::Solaris: 6780 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 6781 case llvm::Triple::Win32: { 6782 switch (Triple.getEnvironment()) { 6783 default: 6784 return new X86_32TargetInfo(Triple); 6785 case llvm::Triple::Cygnus: 6786 return new CygwinX86_32TargetInfo(Triple); 6787 case llvm::Triple::GNU: 6788 return new MinGWX86_32TargetInfo(Triple); 6789 case llvm::Triple::Itanium: 6790 case llvm::Triple::MSVC: 6791 return new MicrosoftX86_32TargetInfo(Triple); 6792 } 6793 } 6794 case llvm::Triple::Haiku: 6795 return new HaikuX86_32TargetInfo(Triple); 6796 case llvm::Triple::RTEMS: 6797 return new RTEMSX86_32TargetInfo(Triple); 6798 case llvm::Triple::NaCl: 6799 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 6800 default: 6801 return new X86_32TargetInfo(Triple); 6802 } 6803 6804 case llvm::Triple::x86_64: 6805 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 6806 return new DarwinX86_64TargetInfo(Triple); 6807 6808 switch (os) { 6809 case llvm::Triple::Linux: 6810 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 6811 case llvm::Triple::DragonFly: 6812 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 6813 case llvm::Triple::NetBSD: 6814 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 6815 case llvm::Triple::OpenBSD: 6816 return new OpenBSDX86_64TargetInfo(Triple); 6817 case llvm::Triple::Bitrig: 6818 return new BitrigX86_64TargetInfo(Triple); 6819 case llvm::Triple::FreeBSD: 6820 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 6821 case llvm::Triple::KFreeBSD: 6822 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 6823 case llvm::Triple::Solaris: 6824 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 6825 case llvm::Triple::Win32: { 6826 switch (Triple.getEnvironment()) { 6827 default: 6828 return new X86_64TargetInfo(Triple); 6829 case llvm::Triple::GNU: 6830 return new MinGWX86_64TargetInfo(Triple); 6831 case llvm::Triple::MSVC: 6832 return new MicrosoftX86_64TargetInfo(Triple); 6833 } 6834 } 6835 case llvm::Triple::NaCl: 6836 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 6837 case llvm::Triple::PS4: 6838 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 6839 default: 6840 return new X86_64TargetInfo(Triple); 6841 } 6842 6843 case llvm::Triple::spir: { 6844 if (Triple.getOS() != llvm::Triple::UnknownOS || 6845 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 6846 return nullptr; 6847 return new SPIR32TargetInfo(Triple); 6848 } 6849 case llvm::Triple::spir64: { 6850 if (Triple.getOS() != llvm::Triple::UnknownOS || 6851 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 6852 return nullptr; 6853 return new SPIR64TargetInfo(Triple); 6854 } 6855 } 6856 } 6857 6858 /// CreateTargetInfo - Return the target info object for the specified target 6859 /// triple. 6860 TargetInfo * 6861 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 6862 const std::shared_ptr<TargetOptions> &Opts) { 6863 llvm::Triple Triple(Opts->Triple); 6864 6865 // Construct the target 6866 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 6867 if (!Target) { 6868 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 6869 return nullptr; 6870 } 6871 Target->TargetOpts = Opts; 6872 6873 // Set the target CPU if specified. 6874 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 6875 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 6876 return nullptr; 6877 } 6878 6879 // Set the target ABI if specified. 6880 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 6881 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 6882 return nullptr; 6883 } 6884 6885 // Set the fp math unit. 6886 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 6887 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 6888 return nullptr; 6889 } 6890 6891 // Compute the default target features, we need the target to handle this 6892 // because features may have dependencies on one another. 6893 llvm::StringMap<bool> Features; 6894 Target->getDefaultFeatures(Features); 6895 6896 // Apply the user specified deltas. 6897 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 6898 I < N; ++I) { 6899 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 6900 // Apply the feature via the target. 6901 bool Enabled = Name[0] == '+'; 6902 Target->setFeatureEnabled(Features, Name + 1, Enabled); 6903 } 6904 6905 // Add the features to the compile options. 6906 // 6907 // FIXME: If we are completely confident that we have the right set, we only 6908 // need to pass the minuses. 6909 Opts->Features.clear(); 6910 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 6911 ie = Features.end(); it != ie; ++it) 6912 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 6913 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 6914 return nullptr; 6915 6916 return Target.release(); 6917 } 6918