1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 115 const llvm::Triple &Triple, 116 StringRef &PlatformName, 117 VersionTuple &PlatformMinVersion) { 118 Builder.defineMacro("__APPLE_CC__", "6000"); 119 Builder.defineMacro("__APPLE__"); 120 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 121 // AddressSanitizer doesn't play well with source fortification, which is on 122 // by default on Darwin. 123 if (Opts.Sanitize.has(SanitizerKind::Address)) 124 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 125 126 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 127 if (!Opts.ObjC1) { 128 // __weak is always defined, for use in blocks and with objc pointers. 129 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 130 Builder.defineMacro("__strong", ""); 131 Builder.defineMacro("__unsafe_unretained", ""); 132 } 133 134 if (Opts.Static) 135 Builder.defineMacro("__STATIC__"); 136 else 137 Builder.defineMacro("__DYNAMIC__"); 138 139 if (Opts.POSIXThreads) 140 Builder.defineMacro("_REENTRANT"); 141 142 // Get the platform type and version number from the triple. 143 unsigned Maj, Min, Rev; 144 if (Triple.isMacOSX()) { 145 Triple.getMacOSXVersion(Maj, Min, Rev); 146 PlatformName = "macos"; 147 } else { 148 Triple.getOSVersion(Maj, Min, Rev); 149 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 150 } 151 152 // If -target arch-pc-win32-macho option specified, we're 153 // generating code for Win32 ABI. No need to emit 154 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 155 if (PlatformName == "win32") { 156 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 157 return; 158 } 159 160 // Set the appropriate OS version define. 161 if (Triple.isiOS()) { 162 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 163 char Str[7]; 164 if (Maj < 10) { 165 Str[0] = '0' + Maj; 166 Str[1] = '0' + (Min / 10); 167 Str[2] = '0' + (Min % 10); 168 Str[3] = '0' + (Rev / 10); 169 Str[4] = '0' + (Rev % 10); 170 Str[5] = '\0'; 171 } else { 172 // Handle versions >= 10. 173 Str[0] = '0' + (Maj / 10); 174 Str[1] = '0' + (Maj % 10); 175 Str[2] = '0' + (Min / 10); 176 Str[3] = '0' + (Min % 10); 177 Str[4] = '0' + (Rev / 10); 178 Str[5] = '0' + (Rev % 10); 179 Str[6] = '\0'; 180 } 181 if (Triple.isTvOS()) 182 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 183 else 184 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 185 Str); 186 187 } else if (Triple.isWatchOS()) { 188 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 189 char Str[6]; 190 Str[0] = '0' + Maj; 191 Str[1] = '0' + (Min / 10); 192 Str[2] = '0' + (Min % 10); 193 Str[3] = '0' + (Rev / 10); 194 Str[4] = '0' + (Rev % 10); 195 Str[5] = '\0'; 196 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 197 } else if (Triple.isMacOSX()) { 198 // Note that the Driver allows versions which aren't representable in the 199 // define (because we only get a single digit for the minor and micro 200 // revision numbers). So, we limit them to the maximum representable 201 // version. 202 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 203 char Str[7]; 204 if (Maj < 10 || (Maj == 10 && Min < 10)) { 205 Str[0] = '0' + (Maj / 10); 206 Str[1] = '0' + (Maj % 10); 207 Str[2] = '0' + std::min(Min, 9U); 208 Str[3] = '0' + std::min(Rev, 9U); 209 Str[4] = '\0'; 210 } else { 211 // Handle versions > 10.9. 212 Str[0] = '0' + (Maj / 10); 213 Str[1] = '0' + (Maj % 10); 214 Str[2] = '0' + (Min / 10); 215 Str[3] = '0' + (Min % 10); 216 Str[4] = '0' + (Rev / 10); 217 Str[5] = '0' + (Rev % 10); 218 Str[6] = '\0'; 219 } 220 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 221 } 222 223 // Tell users about the kernel if there is one. 224 if (Triple.isOSDarwin()) 225 Builder.defineMacro("__MACH__"); 226 227 // The Watch ABI uses Dwarf EH. 228 if(Triple.isWatchABI()) 229 Builder.defineMacro("__ARM_DWARF_EH__"); 230 231 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 232 } 233 234 template<typename Target> 235 class DarwinTargetInfo : public OSTargetInfo<Target> { 236 protected: 237 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 238 MacroBuilder &Builder) const override { 239 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 240 this->PlatformMinVersion); 241 } 242 243 public: 244 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 245 : OSTargetInfo<Target>(Triple, Opts) { 246 // By default, no TLS, and we whitelist permitted architecture/OS 247 // combinations. 248 this->TLSSupported = false; 249 250 if (Triple.isMacOSX()) 251 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 252 else if (Triple.isiOS()) { 253 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 254 if (Triple.getArch() == llvm::Triple::x86_64 || 255 Triple.getArch() == llvm::Triple::aarch64) 256 this->TLSSupported = !Triple.isOSVersionLT(8); 257 else if (Triple.getArch() == llvm::Triple::x86 || 258 Triple.getArch() == llvm::Triple::arm || 259 Triple.getArch() == llvm::Triple::thumb) 260 this->TLSSupported = !Triple.isOSVersionLT(9); 261 } else if (Triple.isWatchOS()) 262 this->TLSSupported = !Triple.isOSVersionLT(2); 263 264 this->MCountName = "\01mcount"; 265 } 266 267 std::string isValidSectionSpecifier(StringRef SR) const override { 268 // Let MCSectionMachO validate this. 269 StringRef Segment, Section; 270 unsigned TAA, StubSize; 271 bool HasTAA; 272 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 273 TAA, HasTAA, StubSize); 274 } 275 276 const char *getStaticInitSectionSpecifier() const override { 277 // FIXME: We should return 0 when building kexts. 278 return "__TEXT,__StaticInit,regular,pure_instructions"; 279 } 280 281 /// Darwin does not support protected visibility. Darwin's "default" 282 /// is very similar to ELF's "protected"; Darwin requires a "weak" 283 /// attribute on declarations that can be dynamically replaced. 284 bool hasProtectedVisibility() const override { 285 return false; 286 } 287 288 unsigned getExnObjectAlignment() const override { 289 // The alignment of an exception object is 8-bytes for darwin since 290 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 291 // and therefore doesn't guarantee 16-byte alignment. 292 return 64; 293 } 294 }; 295 296 297 // DragonFlyBSD Target 298 template<typename Target> 299 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 300 protected: 301 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 302 MacroBuilder &Builder) const override { 303 // DragonFly defines; list based off of gcc output 304 Builder.defineMacro("__DragonFly__"); 305 Builder.defineMacro("__DragonFly_cc_version", "100001"); 306 Builder.defineMacro("__ELF__"); 307 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 308 Builder.defineMacro("__tune_i386__"); 309 DefineStd(Builder, "unix", Opts); 310 } 311 public: 312 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 313 : OSTargetInfo<Target>(Triple, Opts) { 314 switch (Triple.getArch()) { 315 default: 316 case llvm::Triple::x86: 317 case llvm::Triple::x86_64: 318 this->MCountName = ".mcount"; 319 break; 320 } 321 } 322 }; 323 324 #ifndef FREEBSD_CC_VERSION 325 #define FREEBSD_CC_VERSION 0U 326 #endif 327 328 // FreeBSD Target 329 template<typename Target> 330 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 331 protected: 332 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 333 MacroBuilder &Builder) const override { 334 // FreeBSD defines; list based off of gcc output 335 336 unsigned Release = Triple.getOSMajorVersion(); 337 if (Release == 0U) 338 Release = 8U; 339 unsigned CCVersion = FREEBSD_CC_VERSION; 340 if (CCVersion == 0U) 341 CCVersion = Release * 100000U + 1U; 342 343 Builder.defineMacro("__FreeBSD__", Twine(Release)); 344 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 345 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 346 DefineStd(Builder, "unix", Opts); 347 Builder.defineMacro("__ELF__"); 348 349 // On FreeBSD, wchar_t contains the number of the code point as 350 // used by the character set of the locale. These character sets are 351 // not necessarily a superset of ASCII. 352 // 353 // FIXME: This is wrong; the macro refers to the numerical values 354 // of wchar_t *literals*, which are not locale-dependent. However, 355 // FreeBSD systems apparently depend on us getting this wrong, and 356 // setting this to 1 is conforming even if all the basic source 357 // character literals have the same encoding as char and wchar_t. 358 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 359 } 360 public: 361 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 362 : OSTargetInfo<Target>(Triple, Opts) { 363 switch (Triple.getArch()) { 364 default: 365 case llvm::Triple::x86: 366 case llvm::Triple::x86_64: 367 this->MCountName = ".mcount"; 368 break; 369 case llvm::Triple::mips: 370 case llvm::Triple::mipsel: 371 case llvm::Triple::ppc: 372 case llvm::Triple::ppc64: 373 case llvm::Triple::ppc64le: 374 this->MCountName = "_mcount"; 375 break; 376 case llvm::Triple::arm: 377 this->MCountName = "__mcount"; 378 break; 379 } 380 } 381 }; 382 383 // GNU/kFreeBSD Target 384 template<typename Target> 385 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 386 protected: 387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 388 MacroBuilder &Builder) const override { 389 // GNU/kFreeBSD defines; list based off of gcc output 390 391 DefineStd(Builder, "unix", Opts); 392 Builder.defineMacro("__FreeBSD_kernel__"); 393 Builder.defineMacro("__GLIBC__"); 394 Builder.defineMacro("__ELF__"); 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 if (Opts.CPlusPlus) 398 Builder.defineMacro("_GNU_SOURCE"); 399 } 400 public: 401 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 402 : OSTargetInfo<Target>(Triple, Opts) {} 403 }; 404 405 // Haiku Target 406 template<typename Target> 407 class HaikuTargetInfo : public OSTargetInfo<Target> { 408 protected: 409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 410 MacroBuilder &Builder) const override { 411 // Haiku defines; list based off of gcc output 412 Builder.defineMacro("__HAIKU__"); 413 Builder.defineMacro("__ELF__"); 414 DefineStd(Builder, "unix", Opts); 415 } 416 public: 417 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 418 : OSTargetInfo<Target>(Triple, Opts) { 419 this->SizeType = TargetInfo::UnsignedLong; 420 this->IntPtrType = TargetInfo::SignedLong; 421 this->PtrDiffType = TargetInfo::SignedLong; 422 this->ProcessIDType = TargetInfo::SignedLong; 423 this->TLSSupported = false; 424 425 } 426 }; 427 428 // Minix Target 429 template<typename Target> 430 class MinixTargetInfo : public OSTargetInfo<Target> { 431 protected: 432 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 433 MacroBuilder &Builder) const override { 434 // Minix defines 435 436 Builder.defineMacro("__minix", "3"); 437 Builder.defineMacro("_EM_WSIZE", "4"); 438 Builder.defineMacro("_EM_PSIZE", "4"); 439 Builder.defineMacro("_EM_SSIZE", "2"); 440 Builder.defineMacro("_EM_LSIZE", "4"); 441 Builder.defineMacro("_EM_FSIZE", "4"); 442 Builder.defineMacro("_EM_DSIZE", "8"); 443 Builder.defineMacro("__ELF__"); 444 DefineStd(Builder, "unix", Opts); 445 } 446 public: 447 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 448 : OSTargetInfo<Target>(Triple, Opts) {} 449 }; 450 451 // Linux target 452 template<typename Target> 453 class LinuxTargetInfo : public OSTargetInfo<Target> { 454 protected: 455 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 456 MacroBuilder &Builder) const override { 457 // Linux defines; list based off of gcc output 458 DefineStd(Builder, "unix", Opts); 459 DefineStd(Builder, "linux", Opts); 460 Builder.defineMacro("__gnu_linux__"); 461 Builder.defineMacro("__ELF__"); 462 if (Triple.isAndroid()) { 463 Builder.defineMacro("__ANDROID__", "1"); 464 unsigned Maj, Min, Rev; 465 Triple.getEnvironmentVersion(Maj, Min, Rev); 466 this->PlatformName = "android"; 467 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 468 } 469 if (Opts.POSIXThreads) 470 Builder.defineMacro("_REENTRANT"); 471 if (Opts.CPlusPlus) 472 Builder.defineMacro("_GNU_SOURCE"); 473 if (this->HasFloat128) 474 Builder.defineMacro("__FLOAT128__"); 475 } 476 public: 477 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 478 : OSTargetInfo<Target>(Triple, Opts) { 479 this->WIntType = TargetInfo::UnsignedInt; 480 481 switch (Triple.getArch()) { 482 default: 483 break; 484 case llvm::Triple::ppc: 485 case llvm::Triple::ppc64: 486 case llvm::Triple::ppc64le: 487 this->MCountName = "_mcount"; 488 break; 489 case llvm::Triple::x86: 490 case llvm::Triple::x86_64: 491 case llvm::Triple::systemz: 492 this->HasFloat128 = true; 493 break; 494 } 495 } 496 497 const char *getStaticInitSectionSpecifier() const override { 498 return ".text.startup"; 499 } 500 }; 501 502 // NetBSD Target 503 template<typename Target> 504 class NetBSDTargetInfo : public OSTargetInfo<Target> { 505 protected: 506 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 507 MacroBuilder &Builder) const override { 508 // NetBSD defines; list based off of gcc output 509 Builder.defineMacro("__NetBSD__"); 510 Builder.defineMacro("__unix__"); 511 Builder.defineMacro("__ELF__"); 512 if (Opts.POSIXThreads) 513 Builder.defineMacro("_POSIX_THREADS"); 514 515 switch (Triple.getArch()) { 516 default: 517 break; 518 case llvm::Triple::arm: 519 case llvm::Triple::armeb: 520 case llvm::Triple::thumb: 521 case llvm::Triple::thumbeb: 522 Builder.defineMacro("__ARM_DWARF_EH__"); 523 break; 524 } 525 } 526 public: 527 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 528 : OSTargetInfo<Target>(Triple, Opts) { 529 this->MCountName = "_mcount"; 530 } 531 }; 532 533 // OpenBSD Target 534 template<typename Target> 535 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 536 protected: 537 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 538 MacroBuilder &Builder) const override { 539 // OpenBSD defines; list based off of gcc output 540 541 Builder.defineMacro("__OpenBSD__"); 542 DefineStd(Builder, "unix", Opts); 543 Builder.defineMacro("__ELF__"); 544 if (Opts.POSIXThreads) 545 Builder.defineMacro("_REENTRANT"); 546 } 547 public: 548 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 549 : OSTargetInfo<Target>(Triple, Opts) { 550 this->TLSSupported = false; 551 552 switch (Triple.getArch()) { 553 default: 554 case llvm::Triple::x86: 555 case llvm::Triple::x86_64: 556 case llvm::Triple::arm: 557 case llvm::Triple::sparc: 558 this->MCountName = "__mcount"; 559 break; 560 case llvm::Triple::mips64: 561 case llvm::Triple::mips64el: 562 case llvm::Triple::ppc: 563 case llvm::Triple::sparcv9: 564 this->MCountName = "_mcount"; 565 break; 566 } 567 } 568 }; 569 570 // Bitrig Target 571 template<typename Target> 572 class BitrigTargetInfo : public OSTargetInfo<Target> { 573 protected: 574 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 575 MacroBuilder &Builder) const override { 576 // Bitrig defines; list based off of gcc output 577 578 Builder.defineMacro("__Bitrig__"); 579 DefineStd(Builder, "unix", Opts); 580 Builder.defineMacro("__ELF__"); 581 if (Opts.POSIXThreads) 582 Builder.defineMacro("_REENTRANT"); 583 584 switch (Triple.getArch()) { 585 default: 586 break; 587 case llvm::Triple::arm: 588 case llvm::Triple::armeb: 589 case llvm::Triple::thumb: 590 case llvm::Triple::thumbeb: 591 Builder.defineMacro("__ARM_DWARF_EH__"); 592 break; 593 } 594 } 595 public: 596 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 597 : OSTargetInfo<Target>(Triple, Opts) { 598 this->MCountName = "__mcount"; 599 } 600 }; 601 602 // PSP Target 603 template<typename Target> 604 class PSPTargetInfo : public OSTargetInfo<Target> { 605 protected: 606 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 607 MacroBuilder &Builder) const override { 608 // PSP defines; list based on the output of the pspdev gcc toolchain. 609 Builder.defineMacro("PSP"); 610 Builder.defineMacro("_PSP"); 611 Builder.defineMacro("__psp__"); 612 Builder.defineMacro("__ELF__"); 613 } 614 public: 615 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 616 }; 617 618 // PS3 PPU Target 619 template<typename Target> 620 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 621 protected: 622 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 623 MacroBuilder &Builder) const override { 624 // PS3 PPU defines. 625 Builder.defineMacro("__PPC__"); 626 Builder.defineMacro("__PPU__"); 627 Builder.defineMacro("__CELLOS_LV2__"); 628 Builder.defineMacro("__ELF__"); 629 Builder.defineMacro("__LP32__"); 630 Builder.defineMacro("_ARCH_PPC64"); 631 Builder.defineMacro("__powerpc64__"); 632 } 633 public: 634 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 635 : OSTargetInfo<Target>(Triple, Opts) { 636 this->LongWidth = this->LongAlign = 32; 637 this->PointerWidth = this->PointerAlign = 32; 638 this->IntMaxType = TargetInfo::SignedLongLong; 639 this->Int64Type = TargetInfo::SignedLongLong; 640 this->SizeType = TargetInfo::UnsignedInt; 641 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 642 } 643 }; 644 645 template <typename Target> 646 class PS4OSTargetInfo : public OSTargetInfo<Target> { 647 protected: 648 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 649 MacroBuilder &Builder) const override { 650 Builder.defineMacro("__FreeBSD__", "9"); 651 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 652 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 653 DefineStd(Builder, "unix", Opts); 654 Builder.defineMacro("__ELF__"); 655 Builder.defineMacro("__ORBIS__"); 656 } 657 public: 658 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 659 : OSTargetInfo<Target>(Triple, Opts) { 660 this->WCharType = this->UnsignedShort; 661 662 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 663 this->MaxTLSAlign = 256; 664 665 // On PS4, do not honor explicit bit field alignment, 666 // as in "__attribute__((aligned(2))) int b : 1;". 667 this->UseExplicitBitFieldAlignment = false; 668 669 switch (Triple.getArch()) { 670 default: 671 case llvm::Triple::x86_64: 672 this->MCountName = ".mcount"; 673 break; 674 } 675 } 676 }; 677 678 // Solaris target 679 template<typename Target> 680 class SolarisTargetInfo : public OSTargetInfo<Target> { 681 protected: 682 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 683 MacroBuilder &Builder) const override { 684 DefineStd(Builder, "sun", Opts); 685 DefineStd(Builder, "unix", Opts); 686 Builder.defineMacro("__ELF__"); 687 Builder.defineMacro("__svr4__"); 688 Builder.defineMacro("__SVR4"); 689 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 690 // newer, but to 500 for everything else. feature_test.h has a check to 691 // ensure that you are not using C99 with an old version of X/Open or C89 692 // with a new version. 693 if (Opts.C99) 694 Builder.defineMacro("_XOPEN_SOURCE", "600"); 695 else 696 Builder.defineMacro("_XOPEN_SOURCE", "500"); 697 if (Opts.CPlusPlus) 698 Builder.defineMacro("__C99FEATURES__"); 699 Builder.defineMacro("_LARGEFILE_SOURCE"); 700 Builder.defineMacro("_LARGEFILE64_SOURCE"); 701 Builder.defineMacro("__EXTENSIONS__"); 702 Builder.defineMacro("_REENTRANT"); 703 } 704 public: 705 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 706 : OSTargetInfo<Target>(Triple, Opts) { 707 this->WCharType = this->SignedInt; 708 // FIXME: WIntType should be SignedLong 709 } 710 }; 711 712 // Windows target 713 template<typename Target> 714 class WindowsTargetInfo : public OSTargetInfo<Target> { 715 protected: 716 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 717 MacroBuilder &Builder) const override { 718 Builder.defineMacro("_WIN32"); 719 } 720 void getVisualStudioDefines(const LangOptions &Opts, 721 MacroBuilder &Builder) const { 722 if (Opts.CPlusPlus) { 723 if (Opts.RTTIData) 724 Builder.defineMacro("_CPPRTTI"); 725 726 if (Opts.CXXExceptions) 727 Builder.defineMacro("_CPPUNWIND"); 728 } 729 730 if (Opts.Bool) 731 Builder.defineMacro("__BOOL_DEFINED"); 732 733 if (!Opts.CharIsSigned) 734 Builder.defineMacro("_CHAR_UNSIGNED"); 735 736 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 737 // but it works for now. 738 if (Opts.POSIXThreads) 739 Builder.defineMacro("_MT"); 740 741 if (Opts.MSCompatibilityVersion) { 742 Builder.defineMacro("_MSC_VER", 743 Twine(Opts.MSCompatibilityVersion / 100000)); 744 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 745 // FIXME We cannot encode the revision information into 32-bits 746 Builder.defineMacro("_MSC_BUILD", Twine(1)); 747 748 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 749 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 750 751 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 752 if (Opts.CPlusPlus1z) 753 Builder.defineMacro("_MSVC_LANG", "201403L"); 754 else if (Opts.CPlusPlus14) 755 Builder.defineMacro("_MSVC_LANG", "201402L"); 756 } 757 } 758 759 if (Opts.MicrosoftExt) { 760 Builder.defineMacro("_MSC_EXTENSIONS"); 761 762 if (Opts.CPlusPlus11) { 763 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 764 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 765 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 766 } 767 } 768 769 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 770 } 771 772 public: 773 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 774 : OSTargetInfo<Target>(Triple, Opts) {} 775 }; 776 777 template <typename Target> 778 class NaClTargetInfo : public OSTargetInfo<Target> { 779 protected: 780 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 781 MacroBuilder &Builder) const override { 782 if (Opts.POSIXThreads) 783 Builder.defineMacro("_REENTRANT"); 784 if (Opts.CPlusPlus) 785 Builder.defineMacro("_GNU_SOURCE"); 786 787 DefineStd(Builder, "unix", Opts); 788 Builder.defineMacro("__ELF__"); 789 Builder.defineMacro("__native_client__"); 790 } 791 792 public: 793 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 794 : OSTargetInfo<Target>(Triple, Opts) { 795 this->LongAlign = 32; 796 this->LongWidth = 32; 797 this->PointerAlign = 32; 798 this->PointerWidth = 32; 799 this->IntMaxType = TargetInfo::SignedLongLong; 800 this->Int64Type = TargetInfo::SignedLongLong; 801 this->DoubleAlign = 64; 802 this->LongDoubleWidth = 64; 803 this->LongDoubleAlign = 64; 804 this->LongLongWidth = 64; 805 this->LongLongAlign = 64; 806 this->SizeType = TargetInfo::UnsignedInt; 807 this->PtrDiffType = TargetInfo::SignedInt; 808 this->IntPtrType = TargetInfo::SignedInt; 809 // RegParmMax is inherited from the underlying architecture. 810 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 811 if (Triple.getArch() == llvm::Triple::arm) { 812 // Handled in ARM's setABI(). 813 } else if (Triple.getArch() == llvm::Triple::x86) { 814 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 815 } else if (Triple.getArch() == llvm::Triple::x86_64) { 816 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 817 } else if (Triple.getArch() == llvm::Triple::mipsel) { 818 // Handled on mips' setDataLayout. 819 } else { 820 assert(Triple.getArch() == llvm::Triple::le32); 821 this->resetDataLayout("e-p:32:32-i64:64"); 822 } 823 } 824 }; 825 826 // WebAssembly target 827 template <typename Target> 828 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 829 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 830 MacroBuilder &Builder) const final { 831 // A common platform macro. 832 if (Opts.POSIXThreads) 833 Builder.defineMacro("_REENTRANT"); 834 // Follow g++ convention and predefine _GNU_SOURCE for C++. 835 if (Opts.CPlusPlus) 836 Builder.defineMacro("_GNU_SOURCE"); 837 } 838 839 // As an optimization, group static init code together in a section. 840 const char *getStaticInitSectionSpecifier() const final { 841 return ".text.__startup"; 842 } 843 844 public: 845 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 846 const TargetOptions &Opts) 847 : OSTargetInfo<Target>(Triple, Opts) { 848 this->MCountName = "__mcount"; 849 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 850 } 851 }; 852 853 //===----------------------------------------------------------------------===// 854 // Specific target implementations. 855 //===----------------------------------------------------------------------===// 856 857 // PPC abstract base class 858 class PPCTargetInfo : public TargetInfo { 859 static const Builtin::Info BuiltinInfo[]; 860 static const char * const GCCRegNames[]; 861 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 862 std::string CPU; 863 864 // Target cpu features. 865 bool HasVSX; 866 bool HasP8Vector; 867 bool HasP8Crypto; 868 bool HasDirectMove; 869 bool HasQPX; 870 bool HasHTM; 871 bool HasBPERMD; 872 bool HasExtDiv; 873 874 protected: 875 std::string ABI; 876 877 public: 878 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 879 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 880 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 881 HasBPERMD(false), HasExtDiv(false) { 882 SimdDefaultAlign = 128; 883 LongDoubleWidth = LongDoubleAlign = 128; 884 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 885 } 886 887 /// \brief Flags for architecture specific defines. 888 typedef enum { 889 ArchDefineNone = 0, 890 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 891 ArchDefinePpcgr = 1 << 1, 892 ArchDefinePpcsq = 1 << 2, 893 ArchDefine440 = 1 << 3, 894 ArchDefine603 = 1 << 4, 895 ArchDefine604 = 1 << 5, 896 ArchDefinePwr4 = 1 << 6, 897 ArchDefinePwr5 = 1 << 7, 898 ArchDefinePwr5x = 1 << 8, 899 ArchDefinePwr6 = 1 << 9, 900 ArchDefinePwr6x = 1 << 10, 901 ArchDefinePwr7 = 1 << 11, 902 ArchDefinePwr8 = 1 << 12, 903 ArchDefinePwr9 = 1 << 13, 904 ArchDefineA2 = 1 << 14, 905 ArchDefineA2q = 1 << 15 906 } ArchDefineTypes; 907 908 // Note: GCC recognizes the following additional cpus: 909 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 910 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 911 // titan, rs64. 912 bool setCPU(const std::string &Name) override { 913 bool CPUKnown = llvm::StringSwitch<bool>(Name) 914 .Case("generic", true) 915 .Case("440", true) 916 .Case("450", true) 917 .Case("601", true) 918 .Case("602", true) 919 .Case("603", true) 920 .Case("603e", true) 921 .Case("603ev", true) 922 .Case("604", true) 923 .Case("604e", true) 924 .Case("620", true) 925 .Case("630", true) 926 .Case("g3", true) 927 .Case("7400", true) 928 .Case("g4", true) 929 .Case("7450", true) 930 .Case("g4+", true) 931 .Case("750", true) 932 .Case("970", true) 933 .Case("g5", true) 934 .Case("a2", true) 935 .Case("a2q", true) 936 .Case("e500mc", true) 937 .Case("e5500", true) 938 .Case("power3", true) 939 .Case("pwr3", true) 940 .Case("power4", true) 941 .Case("pwr4", true) 942 .Case("power5", true) 943 .Case("pwr5", true) 944 .Case("power5x", true) 945 .Case("pwr5x", true) 946 .Case("power6", true) 947 .Case("pwr6", true) 948 .Case("power6x", true) 949 .Case("pwr6x", true) 950 .Case("power7", true) 951 .Case("pwr7", true) 952 .Case("power8", true) 953 .Case("pwr8", true) 954 .Case("power9", true) 955 .Case("pwr9", true) 956 .Case("powerpc", true) 957 .Case("ppc", true) 958 .Case("powerpc64", true) 959 .Case("ppc64", true) 960 .Case("powerpc64le", true) 961 .Case("ppc64le", true) 962 .Default(false); 963 964 if (CPUKnown) 965 CPU = Name; 966 967 return CPUKnown; 968 } 969 970 971 StringRef getABI() const override { return ABI; } 972 973 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 974 return llvm::makeArrayRef(BuiltinInfo, 975 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 976 } 977 978 bool isCLZForZeroUndef() const override { return false; } 979 980 void getTargetDefines(const LangOptions &Opts, 981 MacroBuilder &Builder) const override; 982 983 bool 984 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 985 StringRef CPU, 986 const std::vector<std::string> &FeaturesVec) const override; 987 988 bool handleTargetFeatures(std::vector<std::string> &Features, 989 DiagnosticsEngine &Diags) override; 990 bool hasFeature(StringRef Feature) const override; 991 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 992 bool Enabled) const override; 993 994 ArrayRef<const char *> getGCCRegNames() const override; 995 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 996 bool validateAsmConstraint(const char *&Name, 997 TargetInfo::ConstraintInfo &Info) const override { 998 switch (*Name) { 999 default: return false; 1000 case 'O': // Zero 1001 break; 1002 case 'b': // Base register 1003 case 'f': // Floating point register 1004 Info.setAllowsRegister(); 1005 break; 1006 // FIXME: The following are added to allow parsing. 1007 // I just took a guess at what the actions should be. 1008 // Also, is more specific checking needed? I.e. specific registers? 1009 case 'd': // Floating point register (containing 64-bit value) 1010 case 'v': // Altivec vector register 1011 Info.setAllowsRegister(); 1012 break; 1013 case 'w': 1014 switch (Name[1]) { 1015 case 'd':// VSX vector register to hold vector double data 1016 case 'f':// VSX vector register to hold vector float data 1017 case 's':// VSX vector register to hold scalar float data 1018 case 'a':// Any VSX register 1019 case 'c':// An individual CR bit 1020 break; 1021 default: 1022 return false; 1023 } 1024 Info.setAllowsRegister(); 1025 Name++; // Skip over 'w'. 1026 break; 1027 case 'h': // `MQ', `CTR', or `LINK' register 1028 case 'q': // `MQ' register 1029 case 'c': // `CTR' register 1030 case 'l': // `LINK' register 1031 case 'x': // `CR' register (condition register) number 0 1032 case 'y': // `CR' register (condition register) 1033 case 'z': // `XER[CA]' carry bit (part of the XER register) 1034 Info.setAllowsRegister(); 1035 break; 1036 case 'I': // Signed 16-bit constant 1037 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1038 // (use `L' instead for SImode constants) 1039 case 'K': // Unsigned 16-bit constant 1040 case 'L': // Signed 16-bit constant shifted left 16 bits 1041 case 'M': // Constant larger than 31 1042 case 'N': // Exact power of 2 1043 case 'P': // Constant whose negation is a signed 16-bit constant 1044 case 'G': // Floating point constant that can be loaded into a 1045 // register with one instruction per word 1046 case 'H': // Integer/Floating point constant that can be loaded 1047 // into a register using three instructions 1048 break; 1049 case 'm': // Memory operand. Note that on PowerPC targets, m can 1050 // include addresses that update the base register. It 1051 // is therefore only safe to use `m' in an asm statement 1052 // if that asm statement accesses the operand exactly once. 1053 // The asm statement must also use `%U<opno>' as a 1054 // placeholder for the "update" flag in the corresponding 1055 // load or store instruction. For example: 1056 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1057 // is correct but: 1058 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1059 // is not. Use es rather than m if you don't want the base 1060 // register to be updated. 1061 case 'e': 1062 if (Name[1] != 's') 1063 return false; 1064 // es: A "stable" memory operand; that is, one which does not 1065 // include any automodification of the base register. Unlike 1066 // `m', this constraint can be used in asm statements that 1067 // might access the operand several times, or that might not 1068 // access it at all. 1069 Info.setAllowsMemory(); 1070 Name++; // Skip over 'e'. 1071 break; 1072 case 'Q': // Memory operand that is an offset from a register (it is 1073 // usually better to use `m' or `es' in asm statements) 1074 case 'Z': // Memory operand that is an indexed or indirect from a 1075 // register (it is usually better to use `m' or `es' in 1076 // asm statements) 1077 Info.setAllowsMemory(); 1078 Info.setAllowsRegister(); 1079 break; 1080 case 'R': // AIX TOC entry 1081 case 'a': // Address operand that is an indexed or indirect from a 1082 // register (`p' is preferable for asm statements) 1083 case 'S': // Constant suitable as a 64-bit mask operand 1084 case 'T': // Constant suitable as a 32-bit mask operand 1085 case 'U': // System V Release 4 small data area reference 1086 case 't': // AND masks that can be performed by two rldic{l, r} 1087 // instructions 1088 case 'W': // Vector constant that does not require memory 1089 case 'j': // Vector constant that is all zeros. 1090 break; 1091 // End FIXME. 1092 } 1093 return true; 1094 } 1095 std::string convertConstraint(const char *&Constraint) const override { 1096 std::string R; 1097 switch (*Constraint) { 1098 case 'e': 1099 case 'w': 1100 // Two-character constraint; add "^" hint for later parsing. 1101 R = std::string("^") + std::string(Constraint, 2); 1102 Constraint++; 1103 break; 1104 default: 1105 return TargetInfo::convertConstraint(Constraint); 1106 } 1107 return R; 1108 } 1109 const char *getClobbers() const override { 1110 return ""; 1111 } 1112 int getEHDataRegisterNumber(unsigned RegNo) const override { 1113 if (RegNo == 0) return 3; 1114 if (RegNo == 1) return 4; 1115 return -1; 1116 } 1117 1118 bool hasSjLjLowering() const override { 1119 return true; 1120 } 1121 1122 bool useFloat128ManglingForLongDouble() const override { 1123 return LongDoubleWidth == 128 && 1124 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1125 getTriple().isOSBinFormatELF(); 1126 } 1127 }; 1128 1129 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1130 #define BUILTIN(ID, TYPE, ATTRS) \ 1131 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1132 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1133 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1134 #include "clang/Basic/BuiltinsPPC.def" 1135 }; 1136 1137 /// handleTargetFeatures - Perform initialization based on the user 1138 /// configured set of features. 1139 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1140 DiagnosticsEngine &Diags) { 1141 for (const auto &Feature : Features) { 1142 if (Feature == "+vsx") { 1143 HasVSX = true; 1144 } else if (Feature == "+bpermd") { 1145 HasBPERMD = true; 1146 } else if (Feature == "+extdiv") { 1147 HasExtDiv = true; 1148 } else if (Feature == "+power8-vector") { 1149 HasP8Vector = true; 1150 } else if (Feature == "+crypto") { 1151 HasP8Crypto = true; 1152 } else if (Feature == "+direct-move") { 1153 HasDirectMove = true; 1154 } else if (Feature == "+qpx") { 1155 HasQPX = true; 1156 } else if (Feature == "+htm") { 1157 HasHTM = true; 1158 } else if (Feature == "+float128") { 1159 HasFloat128 = true; 1160 } 1161 // TODO: Finish this list and add an assert that we've handled them 1162 // all. 1163 } 1164 1165 return true; 1166 } 1167 1168 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1169 /// #defines that are not tied to a specific subtarget. 1170 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1171 MacroBuilder &Builder) const { 1172 // Target identification. 1173 Builder.defineMacro("__ppc__"); 1174 Builder.defineMacro("__PPC__"); 1175 Builder.defineMacro("_ARCH_PPC"); 1176 Builder.defineMacro("__powerpc__"); 1177 Builder.defineMacro("__POWERPC__"); 1178 if (PointerWidth == 64) { 1179 Builder.defineMacro("_ARCH_PPC64"); 1180 Builder.defineMacro("__powerpc64__"); 1181 Builder.defineMacro("__ppc64__"); 1182 Builder.defineMacro("__PPC64__"); 1183 } 1184 1185 // Target properties. 1186 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1187 Builder.defineMacro("_LITTLE_ENDIAN"); 1188 } else { 1189 if (getTriple().getOS() != llvm::Triple::NetBSD && 1190 getTriple().getOS() != llvm::Triple::OpenBSD) 1191 Builder.defineMacro("_BIG_ENDIAN"); 1192 } 1193 1194 // ABI options. 1195 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1196 Builder.defineMacro("_CALL_ELF", "1"); 1197 if (ABI == "elfv2") 1198 Builder.defineMacro("_CALL_ELF", "2"); 1199 1200 // Subtarget options. 1201 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1202 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1203 1204 // FIXME: Should be controlled by command line option. 1205 if (LongDoubleWidth == 128) 1206 Builder.defineMacro("__LONG_DOUBLE_128__"); 1207 1208 if (Opts.AltiVec) { 1209 Builder.defineMacro("__VEC__", "10206"); 1210 Builder.defineMacro("__ALTIVEC__"); 1211 } 1212 1213 // CPU identification. 1214 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1215 .Case("440", ArchDefineName) 1216 .Case("450", ArchDefineName | ArchDefine440) 1217 .Case("601", ArchDefineName) 1218 .Case("602", ArchDefineName | ArchDefinePpcgr) 1219 .Case("603", ArchDefineName | ArchDefinePpcgr) 1220 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1221 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1222 .Case("604", ArchDefineName | ArchDefinePpcgr) 1223 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1224 .Case("620", ArchDefineName | ArchDefinePpcgr) 1225 .Case("630", ArchDefineName | ArchDefinePpcgr) 1226 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1227 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1228 .Case("750", ArchDefineName | ArchDefinePpcgr) 1229 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1230 | ArchDefinePpcsq) 1231 .Case("a2", ArchDefineA2) 1232 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1233 .Case("pwr3", ArchDefinePpcgr) 1234 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1235 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1236 | ArchDefinePpcsq) 1237 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1238 | ArchDefinePpcgr | ArchDefinePpcsq) 1239 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1240 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1241 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1242 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1243 | ArchDefinePpcsq) 1244 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1245 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1246 | ArchDefinePpcgr | ArchDefinePpcsq) 1247 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1248 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1249 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1250 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 1251 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1252 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1253 | ArchDefinePpcsq) 1254 .Case("power3", ArchDefinePpcgr) 1255 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1256 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1257 | ArchDefinePpcsq) 1258 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1259 | ArchDefinePpcgr | ArchDefinePpcsq) 1260 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1261 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1262 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1263 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1264 | ArchDefinePpcsq) 1265 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1266 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1267 | ArchDefinePpcgr | ArchDefinePpcsq) 1268 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1269 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1270 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1271 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 1272 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1273 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1274 | ArchDefinePpcsq) 1275 .Default(ArchDefineNone); 1276 1277 if (defs & ArchDefineName) 1278 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1279 if (defs & ArchDefinePpcgr) 1280 Builder.defineMacro("_ARCH_PPCGR"); 1281 if (defs & ArchDefinePpcsq) 1282 Builder.defineMacro("_ARCH_PPCSQ"); 1283 if (defs & ArchDefine440) 1284 Builder.defineMacro("_ARCH_440"); 1285 if (defs & ArchDefine603) 1286 Builder.defineMacro("_ARCH_603"); 1287 if (defs & ArchDefine604) 1288 Builder.defineMacro("_ARCH_604"); 1289 if (defs & ArchDefinePwr4) 1290 Builder.defineMacro("_ARCH_PWR4"); 1291 if (defs & ArchDefinePwr5) 1292 Builder.defineMacro("_ARCH_PWR5"); 1293 if (defs & ArchDefinePwr5x) 1294 Builder.defineMacro("_ARCH_PWR5X"); 1295 if (defs & ArchDefinePwr6) 1296 Builder.defineMacro("_ARCH_PWR6"); 1297 if (defs & ArchDefinePwr6x) 1298 Builder.defineMacro("_ARCH_PWR6X"); 1299 if (defs & ArchDefinePwr7) 1300 Builder.defineMacro("_ARCH_PWR7"); 1301 if (defs & ArchDefinePwr8) 1302 Builder.defineMacro("_ARCH_PWR8"); 1303 if (defs & ArchDefinePwr9) 1304 Builder.defineMacro("_ARCH_PWR9"); 1305 if (defs & ArchDefineA2) 1306 Builder.defineMacro("_ARCH_A2"); 1307 if (defs & ArchDefineA2q) { 1308 Builder.defineMacro("_ARCH_A2Q"); 1309 Builder.defineMacro("_ARCH_QP"); 1310 } 1311 1312 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1313 Builder.defineMacro("__bg__"); 1314 Builder.defineMacro("__THW_BLUEGENE__"); 1315 Builder.defineMacro("__bgq__"); 1316 Builder.defineMacro("__TOS_BGQ__"); 1317 } 1318 1319 if (HasVSX) 1320 Builder.defineMacro("__VSX__"); 1321 if (HasP8Vector) 1322 Builder.defineMacro("__POWER8_VECTOR__"); 1323 if (HasP8Crypto) 1324 Builder.defineMacro("__CRYPTO__"); 1325 if (HasHTM) 1326 Builder.defineMacro("__HTM__"); 1327 if (HasFloat128) 1328 Builder.defineMacro("__FLOAT128__"); 1329 1330 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1331 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1332 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1333 if (PointerWidth == 64) 1334 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1335 1336 // FIXME: The following are not yet generated here by Clang, but are 1337 // generated by GCC: 1338 // 1339 // _SOFT_FLOAT_ 1340 // __RECIP_PRECISION__ 1341 // __APPLE_ALTIVEC__ 1342 // __RECIP__ 1343 // __RECIPF__ 1344 // __RSQRTE__ 1345 // __RSQRTEF__ 1346 // _SOFT_DOUBLE_ 1347 // __NO_LWSYNC__ 1348 // __HAVE_BSWAP__ 1349 // __LONGDOUBLE128 1350 // __CMODEL_MEDIUM__ 1351 // __CMODEL_LARGE__ 1352 // _CALL_SYSV 1353 // _CALL_DARWIN 1354 // __NO_FPRS__ 1355 } 1356 1357 // Handle explicit options being passed to the compiler here: if we've 1358 // explicitly turned off vsx and turned on power8-vector or direct-move then 1359 // go ahead and error since the customer has expressed a somewhat incompatible 1360 // set of options. 1361 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1362 const std::vector<std::string> &FeaturesVec) { 1363 1364 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1365 FeaturesVec.end()) { 1366 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1367 FeaturesVec.end()) { 1368 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1369 << "-mno-vsx"; 1370 return false; 1371 } 1372 1373 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1374 FeaturesVec.end()) { 1375 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1376 << "-mno-vsx"; 1377 return false; 1378 } 1379 1380 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1381 FeaturesVec.end()) { 1382 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1383 << "-mno-vsx"; 1384 return false; 1385 } 1386 } 1387 1388 return true; 1389 } 1390 1391 bool PPCTargetInfo::initFeatureMap( 1392 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1393 const std::vector<std::string> &FeaturesVec) const { 1394 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1395 .Case("7400", true) 1396 .Case("g4", true) 1397 .Case("7450", true) 1398 .Case("g4+", true) 1399 .Case("970", true) 1400 .Case("g5", true) 1401 .Case("pwr6", true) 1402 .Case("pwr7", true) 1403 .Case("pwr8", true) 1404 .Case("pwr9", true) 1405 .Case("ppc64", true) 1406 .Case("ppc64le", true) 1407 .Default(false); 1408 1409 Features["qpx"] = (CPU == "a2q"); 1410 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1411 .Case("ppc64le", true) 1412 .Case("pwr9", true) 1413 .Case("pwr8", true) 1414 .Default(false); 1415 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1416 .Case("ppc64le", true) 1417 .Case("pwr9", true) 1418 .Case("pwr8", true) 1419 .Default(false); 1420 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1421 .Case("ppc64le", true) 1422 .Case("pwr9", true) 1423 .Case("pwr8", true) 1424 .Case("pwr7", true) 1425 .Default(false); 1426 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1427 .Case("ppc64le", true) 1428 .Case("pwr9", true) 1429 .Case("pwr8", true) 1430 .Case("pwr7", true) 1431 .Default(false); 1432 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1433 .Case("ppc64le", true) 1434 .Case("pwr9", true) 1435 .Case("pwr8", true) 1436 .Default(false); 1437 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1438 .Case("ppc64le", true) 1439 .Case("pwr9", true) 1440 .Case("pwr8", true) 1441 .Case("pwr7", true) 1442 .Default(false); 1443 1444 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1445 return false; 1446 1447 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1448 } 1449 1450 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1451 return llvm::StringSwitch<bool>(Feature) 1452 .Case("powerpc", true) 1453 .Case("vsx", HasVSX) 1454 .Case("power8-vector", HasP8Vector) 1455 .Case("crypto", HasP8Crypto) 1456 .Case("direct-move", HasDirectMove) 1457 .Case("qpx", HasQPX) 1458 .Case("htm", HasHTM) 1459 .Case("bpermd", HasBPERMD) 1460 .Case("extdiv", HasExtDiv) 1461 .Case("float128", HasFloat128) 1462 .Default(false); 1463 } 1464 1465 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1466 StringRef Name, bool Enabled) const { 1467 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1468 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1469 // incompatible options. 1470 if (Enabled) { 1471 if (Name == "direct-move") { 1472 Features[Name] = Features["vsx"] = true; 1473 } else if (Name == "power8-vector") { 1474 Features[Name] = Features["vsx"] = true; 1475 } else if (Name == "float128") { 1476 Features[Name] = Features["vsx"] = true; 1477 } else { 1478 Features[Name] = true; 1479 } 1480 } else { 1481 if (Name == "vsx") { 1482 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1483 Features["float128"] = false; 1484 } else { 1485 Features[Name] = false; 1486 } 1487 } 1488 } 1489 1490 const char * const PPCTargetInfo::GCCRegNames[] = { 1491 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1492 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1493 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1494 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1495 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1496 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1497 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1498 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1499 "mq", "lr", "ctr", "ap", 1500 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1501 "xer", 1502 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1503 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1504 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1505 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1506 "vrsave", "vscr", 1507 "spe_acc", "spefscr", 1508 "sfp" 1509 }; 1510 1511 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1512 return llvm::makeArrayRef(GCCRegNames); 1513 } 1514 1515 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1516 // While some of these aliases do map to different registers 1517 // they still share the same register name. 1518 { { "0" }, "r0" }, 1519 { { "1"}, "r1" }, 1520 { { "2" }, "r2" }, 1521 { { "3" }, "r3" }, 1522 { { "4" }, "r4" }, 1523 { { "5" }, "r5" }, 1524 { { "6" }, "r6" }, 1525 { { "7" }, "r7" }, 1526 { { "8" }, "r8" }, 1527 { { "9" }, "r9" }, 1528 { { "10" }, "r10" }, 1529 { { "11" }, "r11" }, 1530 { { "12" }, "r12" }, 1531 { { "13" }, "r13" }, 1532 { { "14" }, "r14" }, 1533 { { "15" }, "r15" }, 1534 { { "16" }, "r16" }, 1535 { { "17" }, "r17" }, 1536 { { "18" }, "r18" }, 1537 { { "19" }, "r19" }, 1538 { { "20" }, "r20" }, 1539 { { "21" }, "r21" }, 1540 { { "22" }, "r22" }, 1541 { { "23" }, "r23" }, 1542 { { "24" }, "r24" }, 1543 { { "25" }, "r25" }, 1544 { { "26" }, "r26" }, 1545 { { "27" }, "r27" }, 1546 { { "28" }, "r28" }, 1547 { { "29" }, "r29" }, 1548 { { "30" }, "r30" }, 1549 { { "31" }, "r31" }, 1550 { { "fr0" }, "f0" }, 1551 { { "fr1" }, "f1" }, 1552 { { "fr2" }, "f2" }, 1553 { { "fr3" }, "f3" }, 1554 { { "fr4" }, "f4" }, 1555 { { "fr5" }, "f5" }, 1556 { { "fr6" }, "f6" }, 1557 { { "fr7" }, "f7" }, 1558 { { "fr8" }, "f8" }, 1559 { { "fr9" }, "f9" }, 1560 { { "fr10" }, "f10" }, 1561 { { "fr11" }, "f11" }, 1562 { { "fr12" }, "f12" }, 1563 { { "fr13" }, "f13" }, 1564 { { "fr14" }, "f14" }, 1565 { { "fr15" }, "f15" }, 1566 { { "fr16" }, "f16" }, 1567 { { "fr17" }, "f17" }, 1568 { { "fr18" }, "f18" }, 1569 { { "fr19" }, "f19" }, 1570 { { "fr20" }, "f20" }, 1571 { { "fr21" }, "f21" }, 1572 { { "fr22" }, "f22" }, 1573 { { "fr23" }, "f23" }, 1574 { { "fr24" }, "f24" }, 1575 { { "fr25" }, "f25" }, 1576 { { "fr26" }, "f26" }, 1577 { { "fr27" }, "f27" }, 1578 { { "fr28" }, "f28" }, 1579 { { "fr29" }, "f29" }, 1580 { { "fr30" }, "f30" }, 1581 { { "fr31" }, "f31" }, 1582 { { "cc" }, "cr0" }, 1583 }; 1584 1585 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1586 return llvm::makeArrayRef(GCCRegAliases); 1587 } 1588 1589 class PPC32TargetInfo : public PPCTargetInfo { 1590 public: 1591 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1592 : PPCTargetInfo(Triple, Opts) { 1593 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1594 1595 switch (getTriple().getOS()) { 1596 case llvm::Triple::Linux: 1597 case llvm::Triple::FreeBSD: 1598 case llvm::Triple::NetBSD: 1599 SizeType = UnsignedInt; 1600 PtrDiffType = SignedInt; 1601 IntPtrType = SignedInt; 1602 break; 1603 default: 1604 break; 1605 } 1606 1607 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1608 LongDoubleWidth = LongDoubleAlign = 64; 1609 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1610 } 1611 1612 // PPC32 supports atomics up to 4 bytes. 1613 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1614 } 1615 1616 BuiltinVaListKind getBuiltinVaListKind() const override { 1617 // This is the ELF definition, and is overridden by the Darwin sub-target 1618 return TargetInfo::PowerABIBuiltinVaList; 1619 } 1620 }; 1621 1622 // Note: ABI differences may eventually require us to have a separate 1623 // TargetInfo for little endian. 1624 class PPC64TargetInfo : public PPCTargetInfo { 1625 public: 1626 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1627 : PPCTargetInfo(Triple, Opts) { 1628 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1629 IntMaxType = SignedLong; 1630 Int64Type = SignedLong; 1631 1632 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1633 resetDataLayout("e-m:e-i64:64-n32:64"); 1634 ABI = "elfv2"; 1635 } else { 1636 resetDataLayout("E-m:e-i64:64-n32:64"); 1637 ABI = "elfv1"; 1638 } 1639 1640 switch (getTriple().getOS()) { 1641 case llvm::Triple::FreeBSD: 1642 LongDoubleWidth = LongDoubleAlign = 64; 1643 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1644 break; 1645 case llvm::Triple::NetBSD: 1646 IntMaxType = SignedLongLong; 1647 Int64Type = SignedLongLong; 1648 break; 1649 default: 1650 break; 1651 } 1652 1653 // PPC64 supports atomics up to 8 bytes. 1654 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1655 } 1656 BuiltinVaListKind getBuiltinVaListKind() const override { 1657 return TargetInfo::CharPtrBuiltinVaList; 1658 } 1659 // PPC64 Linux-specific ABI options. 1660 bool setABI(const std::string &Name) override { 1661 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1662 ABI = Name; 1663 return true; 1664 } 1665 return false; 1666 } 1667 }; 1668 1669 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1670 public: 1671 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1672 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1673 HasAlignMac68kSupport = true; 1674 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1675 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1676 LongLongAlign = 32; 1677 SuitableAlign = 128; 1678 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1679 } 1680 BuiltinVaListKind getBuiltinVaListKind() const override { 1681 return TargetInfo::CharPtrBuiltinVaList; 1682 } 1683 }; 1684 1685 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1686 public: 1687 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1688 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1689 HasAlignMac68kSupport = true; 1690 SuitableAlign = 128; 1691 resetDataLayout("E-m:o-i64:64-n32:64"); 1692 } 1693 }; 1694 1695 static const unsigned NVPTXAddrSpaceMap[] = { 1696 1, // opencl_global 1697 3, // opencl_local 1698 4, // opencl_constant 1699 // FIXME: generic has to be added to the target 1700 0, // opencl_generic 1701 1, // cuda_device 1702 4, // cuda_constant 1703 3, // cuda_shared 1704 }; 1705 1706 class NVPTXTargetInfo : public TargetInfo { 1707 static const char *const GCCRegNames[]; 1708 static const Builtin::Info BuiltinInfo[]; 1709 CudaArch GPU; 1710 1711 public: 1712 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1713 : TargetInfo(Triple) { 1714 TLSSupported = false; 1715 LongWidth = LongAlign = 64; 1716 AddrSpaceMap = &NVPTXAddrSpaceMap; 1717 UseAddrSpaceMapMangling = true; 1718 // Define available target features 1719 // These must be defined in sorted order! 1720 NoAsmVariants = true; 1721 GPU = CudaArch::SM_20; 1722 1723 // If possible, get a TargetInfo for our host triple, so we can match its 1724 // types. 1725 llvm::Triple HostTriple(Opts.HostTriple); 1726 if (HostTriple.isNVPTX()) 1727 return; 1728 std::unique_ptr<TargetInfo> HostTarget( 1729 AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1730 if (!HostTarget) { 1731 return; 1732 } 1733 1734 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1735 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1736 BoolWidth = HostTarget->getBoolWidth(); 1737 BoolAlign = HostTarget->getBoolAlign(); 1738 IntWidth = HostTarget->getIntWidth(); 1739 IntAlign = HostTarget->getIntAlign(); 1740 HalfWidth = HostTarget->getHalfWidth(); 1741 HalfAlign = HostTarget->getHalfAlign(); 1742 FloatWidth = HostTarget->getFloatWidth(); 1743 FloatAlign = HostTarget->getFloatAlign(); 1744 DoubleWidth = HostTarget->getDoubleWidth(); 1745 DoubleAlign = HostTarget->getDoubleAlign(); 1746 LongWidth = HostTarget->getLongWidth(); 1747 LongAlign = HostTarget->getLongAlign(); 1748 LongLongWidth = HostTarget->getLongLongWidth(); 1749 LongLongAlign = HostTarget->getLongLongAlign(); 1750 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1751 DefaultAlignForAttributeAligned = 1752 HostTarget->getDefaultAlignForAttributeAligned(); 1753 SizeType = HostTarget->getSizeType(); 1754 IntMaxType = HostTarget->getIntMaxType(); 1755 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1756 IntPtrType = HostTarget->getIntPtrType(); 1757 WCharType = HostTarget->getWCharType(); 1758 WIntType = HostTarget->getWIntType(); 1759 Char16Type = HostTarget->getChar16Type(); 1760 Char32Type = HostTarget->getChar32Type(); 1761 Int64Type = HostTarget->getInt64Type(); 1762 SigAtomicType = HostTarget->getSigAtomicType(); 1763 ProcessIDType = HostTarget->getProcessIDType(); 1764 1765 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1766 UseZeroLengthBitfieldAlignment = 1767 HostTarget->useZeroLengthBitfieldAlignment(); 1768 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1769 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1770 1771 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and 1772 // we need those macros to be identical on host and device, because (among 1773 // other things) they affect which standard library classes are defined, and 1774 // we need all classes to be defined on both the host and device. 1775 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth(); 1776 1777 // Properties intentionally not copied from host: 1778 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1779 // host/device boundary. 1780 // - SuitableAlign: Not visible across the host/device boundary, and may 1781 // correctly be different on host/device, e.g. if host has wider vector 1782 // types than device. 1783 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1784 // as its double type, but that's not necessarily true on the host. 1785 // TODO: nvcc emits a warning when using long double on device; we should 1786 // do the same. 1787 } 1788 void getTargetDefines(const LangOptions &Opts, 1789 MacroBuilder &Builder) const override { 1790 Builder.defineMacro("__PTX__"); 1791 Builder.defineMacro("__NVPTX__"); 1792 if (Opts.CUDAIsDevice) { 1793 // Set __CUDA_ARCH__ for the GPU specified. 1794 std::string CUDAArchCode = [this] { 1795 switch (GPU) { 1796 case CudaArch::UNKNOWN: 1797 assert(false && "No GPU arch when compiling CUDA device code."); 1798 return ""; 1799 case CudaArch::SM_20: 1800 return "200"; 1801 case CudaArch::SM_21: 1802 return "210"; 1803 case CudaArch::SM_30: 1804 return "300"; 1805 case CudaArch::SM_32: 1806 return "320"; 1807 case CudaArch::SM_35: 1808 return "350"; 1809 case CudaArch::SM_37: 1810 return "370"; 1811 case CudaArch::SM_50: 1812 return "500"; 1813 case CudaArch::SM_52: 1814 return "520"; 1815 case CudaArch::SM_53: 1816 return "530"; 1817 case CudaArch::SM_60: 1818 return "600"; 1819 case CudaArch::SM_61: 1820 return "610"; 1821 case CudaArch::SM_62: 1822 return "620"; 1823 } 1824 llvm_unreachable("unhandled CudaArch"); 1825 }(); 1826 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1827 } 1828 } 1829 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1830 return llvm::makeArrayRef(BuiltinInfo, 1831 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1832 } 1833 bool hasFeature(StringRef Feature) const override { 1834 return Feature == "ptx" || Feature == "nvptx"; 1835 } 1836 1837 ArrayRef<const char *> getGCCRegNames() const override; 1838 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1839 // No aliases. 1840 return None; 1841 } 1842 bool validateAsmConstraint(const char *&Name, 1843 TargetInfo::ConstraintInfo &Info) const override { 1844 switch (*Name) { 1845 default: 1846 return false; 1847 case 'c': 1848 case 'h': 1849 case 'r': 1850 case 'l': 1851 case 'f': 1852 case 'd': 1853 Info.setAllowsRegister(); 1854 return true; 1855 } 1856 } 1857 const char *getClobbers() const override { 1858 // FIXME: Is this really right? 1859 return ""; 1860 } 1861 BuiltinVaListKind getBuiltinVaListKind() const override { 1862 // FIXME: implement 1863 return TargetInfo::CharPtrBuiltinVaList; 1864 } 1865 bool setCPU(const std::string &Name) override { 1866 GPU = StringToCudaArch(Name); 1867 return GPU != CudaArch::UNKNOWN; 1868 } 1869 void setSupportedOpenCLOpts() override { 1870 auto &Opts = getSupportedOpenCLOpts(); 1871 Opts.cl_clang_storage_class_specifiers = 1; 1872 Opts.cl_khr_gl_sharing = 1; 1873 Opts.cl_khr_icd = 1; 1874 1875 Opts.cl_khr_fp64 = 1; 1876 Opts.cl_khr_byte_addressable_store = 1; 1877 Opts.cl_khr_global_int32_base_atomics = 1; 1878 Opts.cl_khr_global_int32_extended_atomics = 1; 1879 Opts.cl_khr_local_int32_base_atomics = 1; 1880 Opts.cl_khr_local_int32_extended_atomics = 1; 1881 } 1882 }; 1883 1884 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1885 #define BUILTIN(ID, TYPE, ATTRS) \ 1886 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1887 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1888 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1889 #include "clang/Basic/BuiltinsNVPTX.def" 1890 }; 1891 1892 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1893 1894 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1895 return llvm::makeArrayRef(GCCRegNames); 1896 } 1897 1898 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1899 public: 1900 NVPTX32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1901 : NVPTXTargetInfo(Triple, Opts) { 1902 LongWidth = LongAlign = 32; 1903 PointerWidth = PointerAlign = 32; 1904 SizeType = TargetInfo::UnsignedInt; 1905 PtrDiffType = TargetInfo::SignedInt; 1906 IntPtrType = TargetInfo::SignedInt; 1907 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1908 } 1909 }; 1910 1911 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1912 public: 1913 NVPTX64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1914 : NVPTXTargetInfo(Triple, Opts) { 1915 PointerWidth = PointerAlign = 64; 1916 SizeType = TargetInfo::UnsignedLong; 1917 PtrDiffType = TargetInfo::SignedLong; 1918 IntPtrType = TargetInfo::SignedLong; 1919 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1920 } 1921 }; 1922 1923 static const unsigned AMDGPUAddrSpaceMap[] = { 1924 1, // opencl_global 1925 3, // opencl_local 1926 2, // opencl_constant 1927 4, // opencl_generic 1928 1, // cuda_device 1929 2, // cuda_constant 1930 3 // cuda_shared 1931 }; 1932 1933 // If you edit the description strings, make sure you update 1934 // getPointerWidthV(). 1935 1936 static const char *const DataLayoutStringR600 = 1937 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1938 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1939 1940 static const char *const DataLayoutStringSI = 1941 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 1942 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1943 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1944 1945 class AMDGPUTargetInfo final : public TargetInfo { 1946 static const Builtin::Info BuiltinInfo[]; 1947 static const char * const GCCRegNames[]; 1948 1949 /// \brief The GPU profiles supported by the AMDGPU target. 1950 enum GPUKind { 1951 GK_NONE, 1952 GK_R600, 1953 GK_R600_DOUBLE_OPS, 1954 GK_R700, 1955 GK_R700_DOUBLE_OPS, 1956 GK_EVERGREEN, 1957 GK_EVERGREEN_DOUBLE_OPS, 1958 GK_NORTHERN_ISLANDS, 1959 GK_CAYMAN, 1960 GK_GFX6, 1961 GK_GFX7, 1962 GK_GFX8 1963 } GPU; 1964 1965 bool hasFP64:1; 1966 bool hasFMAF:1; 1967 bool hasLDEXPF:1; 1968 bool hasDenormSupport:1; 1969 1970 static bool isAMDGCN(const llvm::Triple &TT) { 1971 return TT.getArch() == llvm::Triple::amdgcn; 1972 } 1973 1974 public: 1975 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1976 : TargetInfo(Triple) , 1977 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600), 1978 hasFP64(false), 1979 hasFMAF(false), 1980 hasLDEXPF(false), 1981 hasDenormSupport(false){ 1982 if (getTriple().getArch() == llvm::Triple::amdgcn) { 1983 hasFP64 = true; 1984 hasFMAF = true; 1985 hasLDEXPF = true; 1986 } 1987 if (Opts.CPU == "fiji") 1988 hasDenormSupport = true; 1989 1990 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 1991 DataLayoutStringSI : DataLayoutStringR600); 1992 1993 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1994 UseAddrSpaceMapMangling = true; 1995 } 1996 1997 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1998 if (GPU <= GK_CAYMAN) 1999 return 32; 2000 2001 switch(AddrSpace) { 2002 default: 2003 return 64; 2004 case 0: 2005 case 3: 2006 case 5: 2007 return 32; 2008 } 2009 } 2010 2011 uint64_t getMaxPointerWidth() const override { 2012 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2013 } 2014 2015 const char * getClobbers() const override { 2016 return ""; 2017 } 2018 2019 ArrayRef<const char *> getGCCRegNames() const override; 2020 2021 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2022 return None; 2023 } 2024 2025 bool validateAsmConstraint(const char *&Name, 2026 TargetInfo::ConstraintInfo &Info) const override { 2027 switch (*Name) { 2028 default: break; 2029 case 'v': // vgpr 2030 case 's': // sgpr 2031 Info.setAllowsRegister(); 2032 return true; 2033 } 2034 return false; 2035 } 2036 2037 bool initFeatureMap(llvm::StringMap<bool> &Features, 2038 DiagnosticsEngine &Diags, StringRef CPU, 2039 const std::vector<std::string> &FeatureVec) const override; 2040 2041 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2042 TargetOptions &TargetOpts) const override { 2043 if (!hasDenormSupport) 2044 return; 2045 bool hasFP32Denormals = false; 2046 bool hasFP64Denormals = false; 2047 for (auto &I : TargetOpts.FeaturesAsWritten) { 2048 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2049 hasFP32Denormals = true; 2050 if (I == "+fp64-denormals" || I == "-fp64-denormals") 2051 hasFP64Denormals = true; 2052 } 2053 if (!hasFP32Denormals) 2054 TargetOpts.Features.push_back((Twine(CGOpts.FlushDenorm ? '-' : '+') + 2055 Twine("fp32-denormals")).str()); 2056 if (!hasFP64Denormals && hasFP64) 2057 TargetOpts.Features.push_back((Twine(CGOpts.FlushDenorm ? '-' : '+') + 2058 Twine("fp64-denormals")).str()); 2059 } 2060 2061 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2062 return llvm::makeArrayRef(BuiltinInfo, 2063 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2064 } 2065 2066 void getTargetDefines(const LangOptions &Opts, 2067 MacroBuilder &Builder) const override { 2068 if (getTriple().getArch() == llvm::Triple::amdgcn) 2069 Builder.defineMacro("__AMDGCN__"); 2070 else 2071 Builder.defineMacro("__R600__"); 2072 2073 if (hasFMAF) 2074 Builder.defineMacro("__HAS_FMAF__"); 2075 if (hasLDEXPF) 2076 Builder.defineMacro("__HAS_LDEXPF__"); 2077 if (hasFP64) 2078 Builder.defineMacro("__HAS_FP64__"); 2079 } 2080 2081 BuiltinVaListKind getBuiltinVaListKind() const override { 2082 return TargetInfo::CharPtrBuiltinVaList; 2083 } 2084 2085 static GPUKind parseR600Name(StringRef Name) { 2086 return llvm::StringSwitch<GPUKind>(Name) 2087 .Case("r600" , GK_R600) 2088 .Case("rv610", GK_R600) 2089 .Case("rv620", GK_R600) 2090 .Case("rv630", GK_R600) 2091 .Case("rv635", GK_R600) 2092 .Case("rs780", GK_R600) 2093 .Case("rs880", GK_R600) 2094 .Case("rv670", GK_R600_DOUBLE_OPS) 2095 .Case("rv710", GK_R700) 2096 .Case("rv730", GK_R700) 2097 .Case("rv740", GK_R700_DOUBLE_OPS) 2098 .Case("rv770", GK_R700_DOUBLE_OPS) 2099 .Case("palm", GK_EVERGREEN) 2100 .Case("cedar", GK_EVERGREEN) 2101 .Case("sumo", GK_EVERGREEN) 2102 .Case("sumo2", GK_EVERGREEN) 2103 .Case("redwood", GK_EVERGREEN) 2104 .Case("juniper", GK_EVERGREEN) 2105 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2106 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2107 .Case("barts", GK_NORTHERN_ISLANDS) 2108 .Case("turks", GK_NORTHERN_ISLANDS) 2109 .Case("caicos", GK_NORTHERN_ISLANDS) 2110 .Case("cayman", GK_CAYMAN) 2111 .Case("aruba", GK_CAYMAN) 2112 .Default(GK_NONE); 2113 } 2114 2115 static GPUKind parseAMDGCNName(StringRef Name) { 2116 return llvm::StringSwitch<GPUKind>(Name) 2117 .Case("tahiti", GK_GFX6) 2118 .Case("pitcairn", GK_GFX6) 2119 .Case("verde", GK_GFX6) 2120 .Case("oland", GK_GFX6) 2121 .Case("hainan", GK_GFX6) 2122 .Case("bonaire", GK_GFX7) 2123 .Case("kabini", GK_GFX7) 2124 .Case("kaveri", GK_GFX7) 2125 .Case("hawaii", GK_GFX7) 2126 .Case("mullins", GK_GFX7) 2127 .Case("tonga", GK_GFX8) 2128 .Case("iceland", GK_GFX8) 2129 .Case("carrizo", GK_GFX8) 2130 .Case("fiji", GK_GFX8) 2131 .Case("stoney", GK_GFX8) 2132 .Case("polaris10", GK_GFX8) 2133 .Case("polaris11", GK_GFX8) 2134 .Default(GK_NONE); 2135 } 2136 2137 bool setCPU(const std::string &Name) override { 2138 if (getTriple().getArch() == llvm::Triple::amdgcn) 2139 GPU = parseAMDGCNName(Name); 2140 else 2141 GPU = parseR600Name(Name); 2142 2143 return GPU != GK_NONE; 2144 } 2145 2146 void setSupportedOpenCLOpts() override { 2147 auto &Opts = getSupportedOpenCLOpts(); 2148 Opts.cl_clang_storage_class_specifiers = 1; 2149 Opts.cl_khr_icd = 1; 2150 2151 if (hasFP64) 2152 Opts.cl_khr_fp64 = 1; 2153 if (GPU >= GK_EVERGREEN) { 2154 Opts.cl_khr_byte_addressable_store = 1; 2155 Opts.cl_khr_global_int32_base_atomics = 1; 2156 Opts.cl_khr_global_int32_extended_atomics = 1; 2157 Opts.cl_khr_local_int32_base_atomics = 1; 2158 Opts.cl_khr_local_int32_extended_atomics = 1; 2159 } 2160 if (GPU >= GK_GFX6) { 2161 Opts.cl_khr_fp16 = 1; 2162 Opts.cl_khr_int64_base_atomics = 1; 2163 Opts.cl_khr_int64_extended_atomics = 1; 2164 Opts.cl_khr_mipmap_image = 1; 2165 Opts.cl_khr_subgroups = 1; 2166 Opts.cl_khr_3d_image_writes = 1; 2167 Opts.cl_amd_media_ops = 1; 2168 Opts.cl_amd_media_ops2 = 1; 2169 } 2170 } 2171 2172 LangAS::ID getOpenCLImageAddrSpace() const override { 2173 return LangAS::opencl_constant; 2174 } 2175 2176 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2177 switch (CC) { 2178 default: 2179 return CCCR_Warning; 2180 case CC_C: 2181 case CC_OpenCLKernel: 2182 return CCCR_OK; 2183 } 2184 } 2185 }; 2186 2187 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2188 #define BUILTIN(ID, TYPE, ATTRS) \ 2189 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2190 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2191 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2192 #include "clang/Basic/BuiltinsAMDGPU.def" 2193 }; 2194 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2195 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2196 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2197 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2198 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2199 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2200 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2201 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2202 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2203 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2204 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2205 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2206 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2207 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2208 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2209 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2210 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2211 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2212 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2213 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2214 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2215 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2216 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2217 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2218 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2219 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2220 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2221 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2222 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2223 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2224 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2225 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2226 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2227 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2228 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2229 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2230 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2231 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2232 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2233 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2234 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2235 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2236 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2237 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2238 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2239 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2240 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2241 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2242 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2243 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2244 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2245 }; 2246 2247 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2248 return llvm::makeArrayRef(GCCRegNames); 2249 } 2250 2251 bool AMDGPUTargetInfo::initFeatureMap( 2252 llvm::StringMap<bool> &Features, 2253 DiagnosticsEngine &Diags, StringRef CPU, 2254 const std::vector<std::string> &FeatureVec) const { 2255 2256 // XXX - What does the member GPU mean if device name string passed here? 2257 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2258 if (CPU.empty()) 2259 CPU = "tahiti"; 2260 2261 switch (parseAMDGCNName(CPU)) { 2262 case GK_GFX6: 2263 case GK_GFX7: 2264 break; 2265 2266 case GK_GFX8: 2267 Features["s-memrealtime"] = true; 2268 Features["16-bit-insts"] = true; 2269 break; 2270 2271 case GK_NONE: 2272 return false; 2273 default: 2274 llvm_unreachable("unhandled subtarget"); 2275 } 2276 } else { 2277 if (CPU.empty()) 2278 CPU = "r600"; 2279 2280 switch (parseR600Name(CPU)) { 2281 case GK_R600: 2282 case GK_R700: 2283 case GK_EVERGREEN: 2284 case GK_NORTHERN_ISLANDS: 2285 break; 2286 case GK_R600_DOUBLE_OPS: 2287 case GK_R700_DOUBLE_OPS: 2288 case GK_EVERGREEN_DOUBLE_OPS: 2289 case GK_CAYMAN: 2290 Features["fp64"] = true; 2291 break; 2292 case GK_NONE: 2293 return false; 2294 default: 2295 llvm_unreachable("unhandled subtarget"); 2296 } 2297 } 2298 2299 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2300 } 2301 2302 // Namespace for x86 abstract base class 2303 const Builtin::Info BuiltinInfo[] = { 2304 #define BUILTIN(ID, TYPE, ATTRS) \ 2305 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2306 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2307 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2308 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2309 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2310 #include "clang/Basic/BuiltinsX86.def" 2311 }; 2312 2313 static const char* const GCCRegNames[] = { 2314 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2315 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2316 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2317 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2318 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2319 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2320 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2321 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2322 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2323 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2324 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2325 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2326 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2327 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2328 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2329 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2330 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2331 }; 2332 2333 const TargetInfo::AddlRegName AddlRegNames[] = { 2334 { { "al", "ah", "eax", "rax" }, 0 }, 2335 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2336 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2337 { { "dl", "dh", "edx", "rdx" }, 1 }, 2338 { { "esi", "rsi" }, 4 }, 2339 { { "edi", "rdi" }, 5 }, 2340 { { "esp", "rsp" }, 7 }, 2341 { { "ebp", "rbp" }, 6 }, 2342 { { "r8d", "r8w", "r8b" }, 38 }, 2343 { { "r9d", "r9w", "r9b" }, 39 }, 2344 { { "r10d", "r10w", "r10b" }, 40 }, 2345 { { "r11d", "r11w", "r11b" }, 41 }, 2346 { { "r12d", "r12w", "r12b" }, 42 }, 2347 { { "r13d", "r13w", "r13b" }, 43 }, 2348 { { "r14d", "r14w", "r14b" }, 44 }, 2349 { { "r15d", "r15w", "r15b" }, 45 }, 2350 }; 2351 2352 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2353 // most of the implementation can be shared. 2354 class X86TargetInfo : public TargetInfo { 2355 enum X86SSEEnum { 2356 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2357 } SSELevel = NoSSE; 2358 enum MMX3DNowEnum { 2359 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2360 } MMX3DNowLevel = NoMMX3DNow; 2361 enum XOPEnum { 2362 NoXOP, 2363 SSE4A, 2364 FMA4, 2365 XOP 2366 } XOPLevel = NoXOP; 2367 2368 bool HasAES = false; 2369 bool HasPCLMUL = false; 2370 bool HasLZCNT = false; 2371 bool HasRDRND = false; 2372 bool HasFSGSBASE = false; 2373 bool HasBMI = false; 2374 bool HasBMI2 = false; 2375 bool HasPOPCNT = false; 2376 bool HasRTM = false; 2377 bool HasPRFCHW = false; 2378 bool HasRDSEED = false; 2379 bool HasADX = false; 2380 bool HasTBM = false; 2381 bool HasFMA = false; 2382 bool HasF16C = false; 2383 bool HasAVX512CD = false; 2384 bool HasAVX512ER = false; 2385 bool HasAVX512PF = false; 2386 bool HasAVX512DQ = false; 2387 bool HasAVX512BW = false; 2388 bool HasAVX512VL = false; 2389 bool HasAVX512VBMI = false; 2390 bool HasAVX512IFMA = false; 2391 bool HasSHA = false; 2392 bool HasMPX = false; 2393 bool HasSGX = false; 2394 bool HasCX16 = false; 2395 bool HasFXSR = false; 2396 bool HasXSAVE = false; 2397 bool HasXSAVEOPT = false; 2398 bool HasXSAVEC = false; 2399 bool HasXSAVES = false; 2400 bool HasMWAITX = false; 2401 bool HasPKU = false; 2402 bool HasCLFLUSHOPT = false; 2403 bool HasPCOMMIT = false; 2404 bool HasCLWB = false; 2405 bool HasUMIP = false; 2406 bool HasMOVBE = false; 2407 bool HasPREFETCHWT1 = false; 2408 2409 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2410 /// 2411 /// Each enumeration represents a particular CPU supported by Clang. These 2412 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2413 enum CPUKind { 2414 CK_Generic, 2415 2416 /// \name i386 2417 /// i386-generation processors. 2418 //@{ 2419 CK_i386, 2420 //@} 2421 2422 /// \name i486 2423 /// i486-generation processors. 2424 //@{ 2425 CK_i486, 2426 CK_WinChipC6, 2427 CK_WinChip2, 2428 CK_C3, 2429 //@} 2430 2431 /// \name i586 2432 /// i586-generation processors, P5 microarchitecture based. 2433 //@{ 2434 CK_i586, 2435 CK_Pentium, 2436 CK_PentiumMMX, 2437 //@} 2438 2439 /// \name i686 2440 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2441 //@{ 2442 CK_i686, 2443 CK_PentiumPro, 2444 CK_Pentium2, 2445 CK_Pentium3, 2446 CK_Pentium3M, 2447 CK_PentiumM, 2448 CK_C3_2, 2449 2450 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2451 /// Clang however has some logic to suport this. 2452 // FIXME: Warn, deprecate, and potentially remove this. 2453 CK_Yonah, 2454 //@} 2455 2456 /// \name Netburst 2457 /// Netburst microarchitecture based processors. 2458 //@{ 2459 CK_Pentium4, 2460 CK_Pentium4M, 2461 CK_Prescott, 2462 CK_Nocona, 2463 //@} 2464 2465 /// \name Core 2466 /// Core microarchitecture based processors. 2467 //@{ 2468 CK_Core2, 2469 2470 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2471 /// codename which GCC no longer accepts as an option to -march, but Clang 2472 /// has some logic for recognizing it. 2473 // FIXME: Warn, deprecate, and potentially remove this. 2474 CK_Penryn, 2475 //@} 2476 2477 /// \name Atom 2478 /// Atom processors 2479 //@{ 2480 CK_Bonnell, 2481 CK_Silvermont, 2482 //@} 2483 2484 /// \name Nehalem 2485 /// Nehalem microarchitecture based processors. 2486 CK_Nehalem, 2487 2488 /// \name Westmere 2489 /// Westmere microarchitecture based processors. 2490 CK_Westmere, 2491 2492 /// \name Sandy Bridge 2493 /// Sandy Bridge microarchitecture based processors. 2494 CK_SandyBridge, 2495 2496 /// \name Ivy Bridge 2497 /// Ivy Bridge microarchitecture based processors. 2498 CK_IvyBridge, 2499 2500 /// \name Haswell 2501 /// Haswell microarchitecture based processors. 2502 CK_Haswell, 2503 2504 /// \name Broadwell 2505 /// Broadwell microarchitecture based processors. 2506 CK_Broadwell, 2507 2508 /// \name Skylake Client 2509 /// Skylake client microarchitecture based processors. 2510 CK_SkylakeClient, 2511 2512 /// \name Skylake Server 2513 /// Skylake server microarchitecture based processors. 2514 CK_SkylakeServer, 2515 2516 /// \name Cannonlake Client 2517 /// Cannonlake client microarchitecture based processors. 2518 CK_Cannonlake, 2519 2520 /// \name Knights Landing 2521 /// Knights Landing processor. 2522 CK_KNL, 2523 2524 /// \name Lakemont 2525 /// Lakemont microarchitecture based processors. 2526 CK_Lakemont, 2527 2528 /// \name K6 2529 /// K6 architecture processors. 2530 //@{ 2531 CK_K6, 2532 CK_K6_2, 2533 CK_K6_3, 2534 //@} 2535 2536 /// \name K7 2537 /// K7 architecture processors. 2538 //@{ 2539 CK_Athlon, 2540 CK_AthlonThunderbird, 2541 CK_Athlon4, 2542 CK_AthlonXP, 2543 CK_AthlonMP, 2544 //@} 2545 2546 /// \name K8 2547 /// K8 architecture processors. 2548 //@{ 2549 CK_Athlon64, 2550 CK_Athlon64SSE3, 2551 CK_AthlonFX, 2552 CK_K8, 2553 CK_K8SSE3, 2554 CK_Opteron, 2555 CK_OpteronSSE3, 2556 CK_AMDFAM10, 2557 //@} 2558 2559 /// \name Bobcat 2560 /// Bobcat architecture processors. 2561 //@{ 2562 CK_BTVER1, 2563 CK_BTVER2, 2564 //@} 2565 2566 /// \name Bulldozer 2567 /// Bulldozer architecture processors. 2568 //@{ 2569 CK_BDVER1, 2570 CK_BDVER2, 2571 CK_BDVER3, 2572 CK_BDVER4, 2573 //@} 2574 2575 /// This specification is deprecated and will be removed in the future. 2576 /// Users should prefer \see CK_K8. 2577 // FIXME: Warn on this when the CPU is set to it. 2578 //@{ 2579 CK_x86_64, 2580 //@} 2581 2582 /// \name Geode 2583 /// Geode processors. 2584 //@{ 2585 CK_Geode 2586 //@} 2587 } CPU = CK_Generic; 2588 2589 CPUKind getCPUKind(StringRef CPU) const { 2590 return llvm::StringSwitch<CPUKind>(CPU) 2591 .Case("i386", CK_i386) 2592 .Case("i486", CK_i486) 2593 .Case("winchip-c6", CK_WinChipC6) 2594 .Case("winchip2", CK_WinChip2) 2595 .Case("c3", CK_C3) 2596 .Case("i586", CK_i586) 2597 .Case("pentium", CK_Pentium) 2598 .Case("pentium-mmx", CK_PentiumMMX) 2599 .Case("i686", CK_i686) 2600 .Case("pentiumpro", CK_PentiumPro) 2601 .Case("pentium2", CK_Pentium2) 2602 .Case("pentium3", CK_Pentium3) 2603 .Case("pentium3m", CK_Pentium3M) 2604 .Case("pentium-m", CK_PentiumM) 2605 .Case("c3-2", CK_C3_2) 2606 .Case("yonah", CK_Yonah) 2607 .Case("pentium4", CK_Pentium4) 2608 .Case("pentium4m", CK_Pentium4M) 2609 .Case("prescott", CK_Prescott) 2610 .Case("nocona", CK_Nocona) 2611 .Case("core2", CK_Core2) 2612 .Case("penryn", CK_Penryn) 2613 .Case("bonnell", CK_Bonnell) 2614 .Case("atom", CK_Bonnell) // Legacy name. 2615 .Case("silvermont", CK_Silvermont) 2616 .Case("slm", CK_Silvermont) // Legacy name. 2617 .Case("nehalem", CK_Nehalem) 2618 .Case("corei7", CK_Nehalem) // Legacy name. 2619 .Case("westmere", CK_Westmere) 2620 .Case("sandybridge", CK_SandyBridge) 2621 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2622 .Case("ivybridge", CK_IvyBridge) 2623 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2624 .Case("haswell", CK_Haswell) 2625 .Case("core-avx2", CK_Haswell) // Legacy name. 2626 .Case("broadwell", CK_Broadwell) 2627 .Case("skylake", CK_SkylakeClient) 2628 .Case("skylake-avx512", CK_SkylakeServer) 2629 .Case("skx", CK_SkylakeServer) // Legacy name. 2630 .Case("cannonlake", CK_Cannonlake) 2631 .Case("knl", CK_KNL) 2632 .Case("lakemont", CK_Lakemont) 2633 .Case("k6", CK_K6) 2634 .Case("k6-2", CK_K6_2) 2635 .Case("k6-3", CK_K6_3) 2636 .Case("athlon", CK_Athlon) 2637 .Case("athlon-tbird", CK_AthlonThunderbird) 2638 .Case("athlon-4", CK_Athlon4) 2639 .Case("athlon-xp", CK_AthlonXP) 2640 .Case("athlon-mp", CK_AthlonMP) 2641 .Case("athlon64", CK_Athlon64) 2642 .Case("athlon64-sse3", CK_Athlon64SSE3) 2643 .Case("athlon-fx", CK_AthlonFX) 2644 .Case("k8", CK_K8) 2645 .Case("k8-sse3", CK_K8SSE3) 2646 .Case("opteron", CK_Opteron) 2647 .Case("opteron-sse3", CK_OpteronSSE3) 2648 .Case("barcelona", CK_AMDFAM10) 2649 .Case("amdfam10", CK_AMDFAM10) 2650 .Case("btver1", CK_BTVER1) 2651 .Case("btver2", CK_BTVER2) 2652 .Case("bdver1", CK_BDVER1) 2653 .Case("bdver2", CK_BDVER2) 2654 .Case("bdver3", CK_BDVER3) 2655 .Case("bdver4", CK_BDVER4) 2656 .Case("x86-64", CK_x86_64) 2657 .Case("geode", CK_Geode) 2658 .Default(CK_Generic); 2659 } 2660 2661 enum FPMathKind { 2662 FP_Default, 2663 FP_SSE, 2664 FP_387 2665 } FPMath = FP_Default; 2666 2667 public: 2668 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2669 : TargetInfo(Triple) { 2670 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2671 } 2672 unsigned getFloatEvalMethod() const override { 2673 // X87 evaluates with 80 bits "long double" precision. 2674 return SSELevel == NoSSE ? 2 : 0; 2675 } 2676 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2677 return llvm::makeArrayRef(BuiltinInfo, 2678 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2679 } 2680 ArrayRef<const char *> getGCCRegNames() const override { 2681 return llvm::makeArrayRef(GCCRegNames); 2682 } 2683 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2684 return None; 2685 } 2686 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2687 return llvm::makeArrayRef(AddlRegNames); 2688 } 2689 bool validateCpuSupports(StringRef Name) const override; 2690 bool validateAsmConstraint(const char *&Name, 2691 TargetInfo::ConstraintInfo &info) const override; 2692 2693 bool validateGlobalRegisterVariable(StringRef RegName, 2694 unsigned RegSize, 2695 bool &HasSizeMismatch) const override { 2696 // esp and ebp are the only 32-bit registers the x86 backend can currently 2697 // handle. 2698 if (RegName.equals("esp") || RegName.equals("ebp")) { 2699 // Check that the register size is 32-bit. 2700 HasSizeMismatch = RegSize != 32; 2701 return true; 2702 } 2703 2704 return false; 2705 } 2706 2707 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2708 2709 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2710 2711 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2712 2713 std::string convertConstraint(const char *&Constraint) const override; 2714 const char *getClobbers() const override { 2715 return "~{dirflag},~{fpsr},~{flags}"; 2716 } 2717 void getTargetDefines(const LangOptions &Opts, 2718 MacroBuilder &Builder) const override; 2719 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2720 bool Enabled); 2721 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2722 bool Enabled); 2723 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2724 bool Enabled); 2725 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2726 StringRef Name, bool Enabled) const override { 2727 setFeatureEnabledImpl(Features, Name, Enabled); 2728 } 2729 // This exists purely to cut down on the number of virtual calls in 2730 // initFeatureMap which calls this repeatedly. 2731 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2732 StringRef Name, bool Enabled); 2733 bool 2734 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2735 StringRef CPU, 2736 const std::vector<std::string> &FeaturesVec) const override; 2737 bool hasFeature(StringRef Feature) const override; 2738 bool handleTargetFeatures(std::vector<std::string> &Features, 2739 DiagnosticsEngine &Diags) override; 2740 StringRef getABI() const override { 2741 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2742 return "avx512"; 2743 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2744 return "avx"; 2745 if (getTriple().getArch() == llvm::Triple::x86 && 2746 MMX3DNowLevel == NoMMX3DNow) 2747 return "no-mmx"; 2748 return ""; 2749 } 2750 bool setCPU(const std::string &Name) override { 2751 CPU = getCPUKind(Name); 2752 2753 // Perform any per-CPU checks necessary to determine if this CPU is 2754 // acceptable. 2755 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2756 // invalid without explaining *why*. 2757 switch (CPU) { 2758 case CK_Generic: 2759 // No processor selected! 2760 return false; 2761 2762 case CK_i386: 2763 case CK_i486: 2764 case CK_WinChipC6: 2765 case CK_WinChip2: 2766 case CK_C3: 2767 case CK_i586: 2768 case CK_Pentium: 2769 case CK_PentiumMMX: 2770 case CK_i686: 2771 case CK_PentiumPro: 2772 case CK_Pentium2: 2773 case CK_Pentium3: 2774 case CK_Pentium3M: 2775 case CK_PentiumM: 2776 case CK_Yonah: 2777 case CK_C3_2: 2778 case CK_Pentium4: 2779 case CK_Pentium4M: 2780 case CK_Lakemont: 2781 case CK_Prescott: 2782 case CK_K6: 2783 case CK_K6_2: 2784 case CK_K6_3: 2785 case CK_Athlon: 2786 case CK_AthlonThunderbird: 2787 case CK_Athlon4: 2788 case CK_AthlonXP: 2789 case CK_AthlonMP: 2790 case CK_Geode: 2791 // Only accept certain architectures when compiling in 32-bit mode. 2792 if (getTriple().getArch() != llvm::Triple::x86) 2793 return false; 2794 2795 // Fallthrough 2796 case CK_Nocona: 2797 case CK_Core2: 2798 case CK_Penryn: 2799 case CK_Bonnell: 2800 case CK_Silvermont: 2801 case CK_Nehalem: 2802 case CK_Westmere: 2803 case CK_SandyBridge: 2804 case CK_IvyBridge: 2805 case CK_Haswell: 2806 case CK_Broadwell: 2807 case CK_SkylakeClient: 2808 case CK_SkylakeServer: 2809 case CK_Cannonlake: 2810 case CK_KNL: 2811 case CK_Athlon64: 2812 case CK_Athlon64SSE3: 2813 case CK_AthlonFX: 2814 case CK_K8: 2815 case CK_K8SSE3: 2816 case CK_Opteron: 2817 case CK_OpteronSSE3: 2818 case CK_AMDFAM10: 2819 case CK_BTVER1: 2820 case CK_BTVER2: 2821 case CK_BDVER1: 2822 case CK_BDVER2: 2823 case CK_BDVER3: 2824 case CK_BDVER4: 2825 case CK_x86_64: 2826 return true; 2827 } 2828 llvm_unreachable("Unhandled CPU kind"); 2829 } 2830 2831 bool setFPMath(StringRef Name) override; 2832 2833 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2834 // Most of the non-ARM calling conventions are i386 conventions. 2835 switch (CC) { 2836 case CC_X86ThisCall: 2837 case CC_X86FastCall: 2838 case CC_X86StdCall: 2839 case CC_X86VectorCall: 2840 case CC_C: 2841 case CC_Swift: 2842 case CC_X86Pascal: 2843 case CC_IntelOclBicc: 2844 return CCCR_OK; 2845 default: 2846 return CCCR_Warning; 2847 } 2848 } 2849 2850 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2851 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2852 } 2853 2854 bool hasSjLjLowering() const override { 2855 return true; 2856 } 2857 2858 void setSupportedOpenCLOpts() override { 2859 getSupportedOpenCLOpts().setAll(); 2860 } 2861 }; 2862 2863 bool X86TargetInfo::setFPMath(StringRef Name) { 2864 if (Name == "387") { 2865 FPMath = FP_387; 2866 return true; 2867 } 2868 if (Name == "sse") { 2869 FPMath = FP_SSE; 2870 return true; 2871 } 2872 return false; 2873 } 2874 2875 bool X86TargetInfo::initFeatureMap( 2876 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2877 const std::vector<std::string> &FeaturesVec) const { 2878 // FIXME: This *really* should not be here. 2879 // X86_64 always has SSE2. 2880 if (getTriple().getArch() == llvm::Triple::x86_64) 2881 setFeatureEnabledImpl(Features, "sse2", true); 2882 2883 const CPUKind Kind = getCPUKind(CPU); 2884 2885 // Enable X87 for all X86 processors but Lakemont. 2886 if (Kind != CK_Lakemont) 2887 setFeatureEnabledImpl(Features, "x87", true); 2888 2889 switch (Kind) { 2890 case CK_Generic: 2891 case CK_i386: 2892 case CK_i486: 2893 case CK_i586: 2894 case CK_Pentium: 2895 case CK_i686: 2896 case CK_PentiumPro: 2897 case CK_Lakemont: 2898 break; 2899 case CK_PentiumMMX: 2900 case CK_Pentium2: 2901 case CK_K6: 2902 case CK_WinChipC6: 2903 setFeatureEnabledImpl(Features, "mmx", true); 2904 break; 2905 case CK_Pentium3: 2906 case CK_Pentium3M: 2907 case CK_C3_2: 2908 setFeatureEnabledImpl(Features, "sse", true); 2909 setFeatureEnabledImpl(Features, "fxsr", true); 2910 break; 2911 case CK_PentiumM: 2912 case CK_Pentium4: 2913 case CK_Pentium4M: 2914 case CK_x86_64: 2915 setFeatureEnabledImpl(Features, "sse2", true); 2916 setFeatureEnabledImpl(Features, "fxsr", true); 2917 break; 2918 case CK_Yonah: 2919 case CK_Prescott: 2920 case CK_Nocona: 2921 setFeatureEnabledImpl(Features, "sse3", true); 2922 setFeatureEnabledImpl(Features, "fxsr", true); 2923 setFeatureEnabledImpl(Features, "cx16", true); 2924 break; 2925 case CK_Core2: 2926 case CK_Bonnell: 2927 setFeatureEnabledImpl(Features, "ssse3", true); 2928 setFeatureEnabledImpl(Features, "fxsr", true); 2929 setFeatureEnabledImpl(Features, "cx16", true); 2930 break; 2931 case CK_Penryn: 2932 setFeatureEnabledImpl(Features, "sse4.1", true); 2933 setFeatureEnabledImpl(Features, "fxsr", true); 2934 setFeatureEnabledImpl(Features, "cx16", true); 2935 break; 2936 case CK_Cannonlake: 2937 setFeatureEnabledImpl(Features, "avx512ifma", true); 2938 setFeatureEnabledImpl(Features, "avx512vbmi", true); 2939 setFeatureEnabledImpl(Features, "sha", true); 2940 setFeatureEnabledImpl(Features, "umip", true); 2941 // FALLTHROUGH 2942 case CK_SkylakeServer: 2943 setFeatureEnabledImpl(Features, "avx512f", true); 2944 setFeatureEnabledImpl(Features, "avx512cd", true); 2945 setFeatureEnabledImpl(Features, "avx512dq", true); 2946 setFeatureEnabledImpl(Features, "avx512bw", true); 2947 setFeatureEnabledImpl(Features, "avx512vl", true); 2948 setFeatureEnabledImpl(Features, "pku", true); 2949 setFeatureEnabledImpl(Features, "pcommit", true); 2950 setFeatureEnabledImpl(Features, "clwb", true); 2951 // FALLTHROUGH 2952 case CK_SkylakeClient: 2953 setFeatureEnabledImpl(Features, "xsavec", true); 2954 setFeatureEnabledImpl(Features, "xsaves", true); 2955 setFeatureEnabledImpl(Features, "mpx", true); 2956 setFeatureEnabledImpl(Features, "sgx", true); 2957 setFeatureEnabledImpl(Features, "clflushopt", true); 2958 // FALLTHROUGH 2959 case CK_Broadwell: 2960 setFeatureEnabledImpl(Features, "rdseed", true); 2961 setFeatureEnabledImpl(Features, "adx", true); 2962 // FALLTHROUGH 2963 case CK_Haswell: 2964 setFeatureEnabledImpl(Features, "avx2", true); 2965 setFeatureEnabledImpl(Features, "lzcnt", true); 2966 setFeatureEnabledImpl(Features, "bmi", true); 2967 setFeatureEnabledImpl(Features, "bmi2", true); 2968 setFeatureEnabledImpl(Features, "rtm", true); 2969 setFeatureEnabledImpl(Features, "fma", true); 2970 setFeatureEnabledImpl(Features, "movbe", true); 2971 // FALLTHROUGH 2972 case CK_IvyBridge: 2973 setFeatureEnabledImpl(Features, "rdrnd", true); 2974 setFeatureEnabledImpl(Features, "f16c", true); 2975 setFeatureEnabledImpl(Features, "fsgsbase", true); 2976 // FALLTHROUGH 2977 case CK_SandyBridge: 2978 setFeatureEnabledImpl(Features, "avx", true); 2979 setFeatureEnabledImpl(Features, "xsave", true); 2980 setFeatureEnabledImpl(Features, "xsaveopt", true); 2981 // FALLTHROUGH 2982 case CK_Westmere: 2983 case CK_Silvermont: 2984 setFeatureEnabledImpl(Features, "aes", true); 2985 setFeatureEnabledImpl(Features, "pclmul", true); 2986 // FALLTHROUGH 2987 case CK_Nehalem: 2988 setFeatureEnabledImpl(Features, "sse4.2", true); 2989 setFeatureEnabledImpl(Features, "fxsr", true); 2990 setFeatureEnabledImpl(Features, "cx16", true); 2991 break; 2992 case CK_KNL: 2993 setFeatureEnabledImpl(Features, "avx512f", true); 2994 setFeatureEnabledImpl(Features, "avx512cd", true); 2995 setFeatureEnabledImpl(Features, "avx512er", true); 2996 setFeatureEnabledImpl(Features, "avx512pf", true); 2997 setFeatureEnabledImpl(Features, "prefetchwt1", true); 2998 setFeatureEnabledImpl(Features, "fxsr", true); 2999 setFeatureEnabledImpl(Features, "rdseed", true); 3000 setFeatureEnabledImpl(Features, "adx", true); 3001 setFeatureEnabledImpl(Features, "lzcnt", true); 3002 setFeatureEnabledImpl(Features, "bmi", true); 3003 setFeatureEnabledImpl(Features, "bmi2", true); 3004 setFeatureEnabledImpl(Features, "rtm", true); 3005 setFeatureEnabledImpl(Features, "fma", true); 3006 setFeatureEnabledImpl(Features, "rdrnd", true); 3007 setFeatureEnabledImpl(Features, "f16c", true); 3008 setFeatureEnabledImpl(Features, "fsgsbase", true); 3009 setFeatureEnabledImpl(Features, "aes", true); 3010 setFeatureEnabledImpl(Features, "pclmul", true); 3011 setFeatureEnabledImpl(Features, "cx16", true); 3012 setFeatureEnabledImpl(Features, "xsaveopt", true); 3013 setFeatureEnabledImpl(Features, "xsave", true); 3014 setFeatureEnabledImpl(Features, "movbe", true); 3015 break; 3016 case CK_K6_2: 3017 case CK_K6_3: 3018 case CK_WinChip2: 3019 case CK_C3: 3020 setFeatureEnabledImpl(Features, "3dnow", true); 3021 break; 3022 case CK_Athlon: 3023 case CK_AthlonThunderbird: 3024 case CK_Geode: 3025 setFeatureEnabledImpl(Features, "3dnowa", true); 3026 break; 3027 case CK_Athlon4: 3028 case CK_AthlonXP: 3029 case CK_AthlonMP: 3030 setFeatureEnabledImpl(Features, "sse", true); 3031 setFeatureEnabledImpl(Features, "3dnowa", true); 3032 setFeatureEnabledImpl(Features, "fxsr", true); 3033 break; 3034 case CK_K8: 3035 case CK_Opteron: 3036 case CK_Athlon64: 3037 case CK_AthlonFX: 3038 setFeatureEnabledImpl(Features, "sse2", true); 3039 setFeatureEnabledImpl(Features, "3dnowa", true); 3040 setFeatureEnabledImpl(Features, "fxsr", true); 3041 break; 3042 case CK_AMDFAM10: 3043 setFeatureEnabledImpl(Features, "sse4a", true); 3044 setFeatureEnabledImpl(Features, "lzcnt", true); 3045 setFeatureEnabledImpl(Features, "popcnt", true); 3046 // FALLTHROUGH 3047 case CK_K8SSE3: 3048 case CK_OpteronSSE3: 3049 case CK_Athlon64SSE3: 3050 setFeatureEnabledImpl(Features, "sse3", true); 3051 setFeatureEnabledImpl(Features, "3dnowa", true); 3052 setFeatureEnabledImpl(Features, "fxsr", true); 3053 break; 3054 case CK_BTVER2: 3055 setFeatureEnabledImpl(Features, "avx", true); 3056 setFeatureEnabledImpl(Features, "aes", true); 3057 setFeatureEnabledImpl(Features, "pclmul", true); 3058 setFeatureEnabledImpl(Features, "bmi", true); 3059 setFeatureEnabledImpl(Features, "f16c", true); 3060 setFeatureEnabledImpl(Features, "xsaveopt", true); 3061 // FALLTHROUGH 3062 case CK_BTVER1: 3063 setFeatureEnabledImpl(Features, "ssse3", true); 3064 setFeatureEnabledImpl(Features, "sse4a", true); 3065 setFeatureEnabledImpl(Features, "lzcnt", true); 3066 setFeatureEnabledImpl(Features, "popcnt", true); 3067 setFeatureEnabledImpl(Features, "prfchw", true); 3068 setFeatureEnabledImpl(Features, "cx16", true); 3069 setFeatureEnabledImpl(Features, "fxsr", true); 3070 break; 3071 case CK_BDVER4: 3072 setFeatureEnabledImpl(Features, "avx2", true); 3073 setFeatureEnabledImpl(Features, "bmi2", true); 3074 setFeatureEnabledImpl(Features, "mwaitx", true); 3075 // FALLTHROUGH 3076 case CK_BDVER3: 3077 setFeatureEnabledImpl(Features, "fsgsbase", true); 3078 setFeatureEnabledImpl(Features, "xsaveopt", true); 3079 // FALLTHROUGH 3080 case CK_BDVER2: 3081 setFeatureEnabledImpl(Features, "bmi", true); 3082 setFeatureEnabledImpl(Features, "fma", true); 3083 setFeatureEnabledImpl(Features, "f16c", true); 3084 setFeatureEnabledImpl(Features, "tbm", true); 3085 // FALLTHROUGH 3086 case CK_BDVER1: 3087 // xop implies avx, sse4a and fma4. 3088 setFeatureEnabledImpl(Features, "xop", true); 3089 setFeatureEnabledImpl(Features, "lzcnt", true); 3090 setFeatureEnabledImpl(Features, "aes", true); 3091 setFeatureEnabledImpl(Features, "pclmul", true); 3092 setFeatureEnabledImpl(Features, "prfchw", true); 3093 setFeatureEnabledImpl(Features, "cx16", true); 3094 setFeatureEnabledImpl(Features, "fxsr", true); 3095 setFeatureEnabledImpl(Features, "xsave", true); 3096 break; 3097 } 3098 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3099 return false; 3100 3101 // Can't do this earlier because we need to be able to explicitly enable 3102 // or disable these features and the things that they depend upon. 3103 3104 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3105 auto I = Features.find("sse4.2"); 3106 if (I != Features.end() && I->getValue() && 3107 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3108 FeaturesVec.end()) 3109 Features["popcnt"] = true; 3110 3111 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3112 I = Features.find("3dnow"); 3113 if (I != Features.end() && I->getValue() && 3114 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3115 FeaturesVec.end()) 3116 Features["prfchw"] = true; 3117 3118 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3119 // then enable MMX. 3120 I = Features.find("sse"); 3121 if (I != Features.end() && I->getValue() && 3122 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3123 FeaturesVec.end()) 3124 Features["mmx"] = true; 3125 3126 return true; 3127 } 3128 3129 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3130 X86SSEEnum Level, bool Enabled) { 3131 if (Enabled) { 3132 switch (Level) { 3133 case AVX512F: 3134 Features["avx512f"] = true; 3135 case AVX2: 3136 Features["avx2"] = true; 3137 case AVX: 3138 Features["avx"] = true; 3139 Features["xsave"] = true; 3140 case SSE42: 3141 Features["sse4.2"] = true; 3142 case SSE41: 3143 Features["sse4.1"] = true; 3144 case SSSE3: 3145 Features["ssse3"] = true; 3146 case SSE3: 3147 Features["sse3"] = true; 3148 case SSE2: 3149 Features["sse2"] = true; 3150 case SSE1: 3151 Features["sse"] = true; 3152 case NoSSE: 3153 break; 3154 } 3155 return; 3156 } 3157 3158 switch (Level) { 3159 case NoSSE: 3160 case SSE1: 3161 Features["sse"] = false; 3162 case SSE2: 3163 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3164 Features["sha"] = false; 3165 case SSE3: 3166 Features["sse3"] = false; 3167 setXOPLevel(Features, NoXOP, false); 3168 case SSSE3: 3169 Features["ssse3"] = false; 3170 case SSE41: 3171 Features["sse4.1"] = false; 3172 case SSE42: 3173 Features["sse4.2"] = false; 3174 case AVX: 3175 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3176 Features["xsaveopt"] = false; 3177 setXOPLevel(Features, FMA4, false); 3178 case AVX2: 3179 Features["avx2"] = false; 3180 case AVX512F: 3181 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3182 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3183 Features["avx512vl"] = Features["avx512vbmi"] = 3184 Features["avx512ifma"] = false; 3185 } 3186 } 3187 3188 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3189 MMX3DNowEnum Level, bool Enabled) { 3190 if (Enabled) { 3191 switch (Level) { 3192 case AMD3DNowAthlon: 3193 Features["3dnowa"] = true; 3194 case AMD3DNow: 3195 Features["3dnow"] = true; 3196 case MMX: 3197 Features["mmx"] = true; 3198 case NoMMX3DNow: 3199 break; 3200 } 3201 return; 3202 } 3203 3204 switch (Level) { 3205 case NoMMX3DNow: 3206 case MMX: 3207 Features["mmx"] = false; 3208 case AMD3DNow: 3209 Features["3dnow"] = false; 3210 case AMD3DNowAthlon: 3211 Features["3dnowa"] = false; 3212 } 3213 } 3214 3215 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3216 bool Enabled) { 3217 if (Enabled) { 3218 switch (Level) { 3219 case XOP: 3220 Features["xop"] = true; 3221 case FMA4: 3222 Features["fma4"] = true; 3223 setSSELevel(Features, AVX, true); 3224 case SSE4A: 3225 Features["sse4a"] = true; 3226 setSSELevel(Features, SSE3, true); 3227 case NoXOP: 3228 break; 3229 } 3230 return; 3231 } 3232 3233 switch (Level) { 3234 case NoXOP: 3235 case SSE4A: 3236 Features["sse4a"] = false; 3237 case FMA4: 3238 Features["fma4"] = false; 3239 case XOP: 3240 Features["xop"] = false; 3241 } 3242 } 3243 3244 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3245 StringRef Name, bool Enabled) { 3246 // This is a bit of a hack to deal with the sse4 target feature when used 3247 // as part of the target attribute. We handle sse4 correctly everywhere 3248 // else. See below for more information on how we handle the sse4 options. 3249 if (Name != "sse4") 3250 Features[Name] = Enabled; 3251 3252 if (Name == "mmx") { 3253 setMMXLevel(Features, MMX, Enabled); 3254 } else if (Name == "sse") { 3255 setSSELevel(Features, SSE1, Enabled); 3256 } else if (Name == "sse2") { 3257 setSSELevel(Features, SSE2, Enabled); 3258 } else if (Name == "sse3") { 3259 setSSELevel(Features, SSE3, Enabled); 3260 } else if (Name == "ssse3") { 3261 setSSELevel(Features, SSSE3, Enabled); 3262 } else if (Name == "sse4.2") { 3263 setSSELevel(Features, SSE42, Enabled); 3264 } else if (Name == "sse4.1") { 3265 setSSELevel(Features, SSE41, Enabled); 3266 } else if (Name == "3dnow") { 3267 setMMXLevel(Features, AMD3DNow, Enabled); 3268 } else if (Name == "3dnowa") { 3269 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3270 } else if (Name == "aes") { 3271 if (Enabled) 3272 setSSELevel(Features, SSE2, Enabled); 3273 } else if (Name == "pclmul") { 3274 if (Enabled) 3275 setSSELevel(Features, SSE2, Enabled); 3276 } else if (Name == "avx") { 3277 setSSELevel(Features, AVX, Enabled); 3278 } else if (Name == "avx2") { 3279 setSSELevel(Features, AVX2, Enabled); 3280 } else if (Name == "avx512f") { 3281 setSSELevel(Features, AVX512F, Enabled); 3282 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3283 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3284 Name == "avx512vbmi" || Name == "avx512ifma") { 3285 if (Enabled) 3286 setSSELevel(Features, AVX512F, Enabled); 3287 } else if (Name == "fma") { 3288 if (Enabled) 3289 setSSELevel(Features, AVX, Enabled); 3290 } else if (Name == "fma4") { 3291 setXOPLevel(Features, FMA4, Enabled); 3292 } else if (Name == "xop") { 3293 setXOPLevel(Features, XOP, Enabled); 3294 } else if (Name == "sse4a") { 3295 setXOPLevel(Features, SSE4A, Enabled); 3296 } else if (Name == "f16c") { 3297 if (Enabled) 3298 setSSELevel(Features, AVX, Enabled); 3299 } else if (Name == "sha") { 3300 if (Enabled) 3301 setSSELevel(Features, SSE2, Enabled); 3302 } else if (Name == "sse4") { 3303 // We can get here via the __target__ attribute since that's not controlled 3304 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3305 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3306 // disabled. 3307 if (Enabled) 3308 setSSELevel(Features, SSE42, Enabled); 3309 else 3310 setSSELevel(Features, SSE41, Enabled); 3311 } else if (Name == "xsave") { 3312 if (!Enabled) 3313 Features["xsaveopt"] = false; 3314 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3315 if (Enabled) 3316 Features["xsave"] = true; 3317 } 3318 } 3319 3320 /// handleTargetFeatures - Perform initialization based on the user 3321 /// configured set of features. 3322 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3323 DiagnosticsEngine &Diags) { 3324 for (const auto &Feature : Features) { 3325 if (Feature[0] != '+') 3326 continue; 3327 3328 if (Feature == "+aes") { 3329 HasAES = true; 3330 } else if (Feature == "+pclmul") { 3331 HasPCLMUL = true; 3332 } else if (Feature == "+lzcnt") { 3333 HasLZCNT = true; 3334 } else if (Feature == "+rdrnd") { 3335 HasRDRND = true; 3336 } else if (Feature == "+fsgsbase") { 3337 HasFSGSBASE = true; 3338 } else if (Feature == "+bmi") { 3339 HasBMI = true; 3340 } else if (Feature == "+bmi2") { 3341 HasBMI2 = true; 3342 } else if (Feature == "+popcnt") { 3343 HasPOPCNT = true; 3344 } else if (Feature == "+rtm") { 3345 HasRTM = true; 3346 } else if (Feature == "+prfchw") { 3347 HasPRFCHW = true; 3348 } else if (Feature == "+rdseed") { 3349 HasRDSEED = true; 3350 } else if (Feature == "+adx") { 3351 HasADX = true; 3352 } else if (Feature == "+tbm") { 3353 HasTBM = true; 3354 } else if (Feature == "+fma") { 3355 HasFMA = true; 3356 } else if (Feature == "+f16c") { 3357 HasF16C = true; 3358 } else if (Feature == "+avx512cd") { 3359 HasAVX512CD = true; 3360 } else if (Feature == "+avx512er") { 3361 HasAVX512ER = true; 3362 } else if (Feature == "+avx512pf") { 3363 HasAVX512PF = true; 3364 } else if (Feature == "+avx512dq") { 3365 HasAVX512DQ = true; 3366 } else if (Feature == "+avx512bw") { 3367 HasAVX512BW = true; 3368 } else if (Feature == "+avx512vl") { 3369 HasAVX512VL = true; 3370 } else if (Feature == "+avx512vbmi") { 3371 HasAVX512VBMI = true; 3372 } else if (Feature == "+avx512ifma") { 3373 HasAVX512IFMA = true; 3374 } else if (Feature == "+sha") { 3375 HasSHA = true; 3376 } else if (Feature == "+mpx") { 3377 HasMPX = true; 3378 } else if (Feature == "+movbe") { 3379 HasMOVBE = true; 3380 } else if (Feature == "+sgx") { 3381 HasSGX = true; 3382 } else if (Feature == "+cx16") { 3383 HasCX16 = true; 3384 } else if (Feature == "+fxsr") { 3385 HasFXSR = true; 3386 } else if (Feature == "+xsave") { 3387 HasXSAVE = true; 3388 } else if (Feature == "+xsaveopt") { 3389 HasXSAVEOPT = true; 3390 } else if (Feature == "+xsavec") { 3391 HasXSAVEC = true; 3392 } else if (Feature == "+xsaves") { 3393 HasXSAVES = true; 3394 } else if (Feature == "+mwaitx") { 3395 HasMWAITX = true; 3396 } else if (Feature == "+pku") { 3397 HasPKU = true; 3398 } else if (Feature == "+clflushopt") { 3399 HasCLFLUSHOPT = true; 3400 } else if (Feature == "+pcommit") { 3401 HasPCOMMIT = true; 3402 } else if (Feature == "+clwb") { 3403 HasCLWB = true; 3404 } else if (Feature == "+umip") { 3405 HasUMIP = true; 3406 } else if (Feature == "+prefetchwt1") { 3407 HasPREFETCHWT1 = true; 3408 } 3409 3410 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3411 .Case("+avx512f", AVX512F) 3412 .Case("+avx2", AVX2) 3413 .Case("+avx", AVX) 3414 .Case("+sse4.2", SSE42) 3415 .Case("+sse4.1", SSE41) 3416 .Case("+ssse3", SSSE3) 3417 .Case("+sse3", SSE3) 3418 .Case("+sse2", SSE2) 3419 .Case("+sse", SSE1) 3420 .Default(NoSSE); 3421 SSELevel = std::max(SSELevel, Level); 3422 3423 MMX3DNowEnum ThreeDNowLevel = 3424 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3425 .Case("+3dnowa", AMD3DNowAthlon) 3426 .Case("+3dnow", AMD3DNow) 3427 .Case("+mmx", MMX) 3428 .Default(NoMMX3DNow); 3429 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3430 3431 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3432 .Case("+xop", XOP) 3433 .Case("+fma4", FMA4) 3434 .Case("+sse4a", SSE4A) 3435 .Default(NoXOP); 3436 XOPLevel = std::max(XOPLevel, XLevel); 3437 } 3438 3439 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3440 // matches the selected sse level. 3441 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3442 (FPMath == FP_387 && SSELevel >= SSE1)) { 3443 Diags.Report(diag::err_target_unsupported_fpmath) << 3444 (FPMath == FP_SSE ? "sse" : "387"); 3445 return false; 3446 } 3447 3448 SimdDefaultAlign = 3449 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3450 return true; 3451 } 3452 3453 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3454 /// definitions for this particular subtarget. 3455 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3456 MacroBuilder &Builder) const { 3457 // Target identification. 3458 if (getTriple().getArch() == llvm::Triple::x86_64) { 3459 Builder.defineMacro("__amd64__"); 3460 Builder.defineMacro("__amd64"); 3461 Builder.defineMacro("__x86_64"); 3462 Builder.defineMacro("__x86_64__"); 3463 if (getTriple().getArchName() == "x86_64h") { 3464 Builder.defineMacro("__x86_64h"); 3465 Builder.defineMacro("__x86_64h__"); 3466 } 3467 } else { 3468 DefineStd(Builder, "i386", Opts); 3469 } 3470 3471 // Subtarget options. 3472 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3473 // truly should be based on -mtune options. 3474 switch (CPU) { 3475 case CK_Generic: 3476 break; 3477 case CK_i386: 3478 // The rest are coming from the i386 define above. 3479 Builder.defineMacro("__tune_i386__"); 3480 break; 3481 case CK_i486: 3482 case CK_WinChipC6: 3483 case CK_WinChip2: 3484 case CK_C3: 3485 defineCPUMacros(Builder, "i486"); 3486 break; 3487 case CK_PentiumMMX: 3488 Builder.defineMacro("__pentium_mmx__"); 3489 Builder.defineMacro("__tune_pentium_mmx__"); 3490 // Fallthrough 3491 case CK_i586: 3492 case CK_Pentium: 3493 defineCPUMacros(Builder, "i586"); 3494 defineCPUMacros(Builder, "pentium"); 3495 break; 3496 case CK_Pentium3: 3497 case CK_Pentium3M: 3498 case CK_PentiumM: 3499 Builder.defineMacro("__tune_pentium3__"); 3500 // Fallthrough 3501 case CK_Pentium2: 3502 case CK_C3_2: 3503 Builder.defineMacro("__tune_pentium2__"); 3504 // Fallthrough 3505 case CK_PentiumPro: 3506 Builder.defineMacro("__tune_i686__"); 3507 Builder.defineMacro("__tune_pentiumpro__"); 3508 // Fallthrough 3509 case CK_i686: 3510 Builder.defineMacro("__i686"); 3511 Builder.defineMacro("__i686__"); 3512 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3513 Builder.defineMacro("__pentiumpro"); 3514 Builder.defineMacro("__pentiumpro__"); 3515 break; 3516 case CK_Pentium4: 3517 case CK_Pentium4M: 3518 defineCPUMacros(Builder, "pentium4"); 3519 break; 3520 case CK_Yonah: 3521 case CK_Prescott: 3522 case CK_Nocona: 3523 defineCPUMacros(Builder, "nocona"); 3524 break; 3525 case CK_Core2: 3526 case CK_Penryn: 3527 defineCPUMacros(Builder, "core2"); 3528 break; 3529 case CK_Bonnell: 3530 defineCPUMacros(Builder, "atom"); 3531 break; 3532 case CK_Silvermont: 3533 defineCPUMacros(Builder, "slm"); 3534 break; 3535 case CK_Nehalem: 3536 case CK_Westmere: 3537 case CK_SandyBridge: 3538 case CK_IvyBridge: 3539 case CK_Haswell: 3540 case CK_Broadwell: 3541 case CK_SkylakeClient: 3542 // FIXME: Historically, we defined this legacy name, it would be nice to 3543 // remove it at some point. We've never exposed fine-grained names for 3544 // recent primary x86 CPUs, and we should keep it that way. 3545 defineCPUMacros(Builder, "corei7"); 3546 break; 3547 case CK_SkylakeServer: 3548 defineCPUMacros(Builder, "skx"); 3549 break; 3550 case CK_Cannonlake: 3551 break; 3552 case CK_KNL: 3553 defineCPUMacros(Builder, "knl"); 3554 break; 3555 case CK_Lakemont: 3556 Builder.defineMacro("__tune_lakemont__"); 3557 break; 3558 case CK_K6_2: 3559 Builder.defineMacro("__k6_2__"); 3560 Builder.defineMacro("__tune_k6_2__"); 3561 // Fallthrough 3562 case CK_K6_3: 3563 if (CPU != CK_K6_2) { // In case of fallthrough 3564 // FIXME: GCC may be enabling these in cases where some other k6 3565 // architecture is specified but -m3dnow is explicitly provided. The 3566 // exact semantics need to be determined and emulated here. 3567 Builder.defineMacro("__k6_3__"); 3568 Builder.defineMacro("__tune_k6_3__"); 3569 } 3570 // Fallthrough 3571 case CK_K6: 3572 defineCPUMacros(Builder, "k6"); 3573 break; 3574 case CK_Athlon: 3575 case CK_AthlonThunderbird: 3576 case CK_Athlon4: 3577 case CK_AthlonXP: 3578 case CK_AthlonMP: 3579 defineCPUMacros(Builder, "athlon"); 3580 if (SSELevel != NoSSE) { 3581 Builder.defineMacro("__athlon_sse__"); 3582 Builder.defineMacro("__tune_athlon_sse__"); 3583 } 3584 break; 3585 case CK_K8: 3586 case CK_K8SSE3: 3587 case CK_x86_64: 3588 case CK_Opteron: 3589 case CK_OpteronSSE3: 3590 case CK_Athlon64: 3591 case CK_Athlon64SSE3: 3592 case CK_AthlonFX: 3593 defineCPUMacros(Builder, "k8"); 3594 break; 3595 case CK_AMDFAM10: 3596 defineCPUMacros(Builder, "amdfam10"); 3597 break; 3598 case CK_BTVER1: 3599 defineCPUMacros(Builder, "btver1"); 3600 break; 3601 case CK_BTVER2: 3602 defineCPUMacros(Builder, "btver2"); 3603 break; 3604 case CK_BDVER1: 3605 defineCPUMacros(Builder, "bdver1"); 3606 break; 3607 case CK_BDVER2: 3608 defineCPUMacros(Builder, "bdver2"); 3609 break; 3610 case CK_BDVER3: 3611 defineCPUMacros(Builder, "bdver3"); 3612 break; 3613 case CK_BDVER4: 3614 defineCPUMacros(Builder, "bdver4"); 3615 break; 3616 case CK_Geode: 3617 defineCPUMacros(Builder, "geode"); 3618 break; 3619 } 3620 3621 // Target properties. 3622 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3623 3624 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3625 // functions in glibc header files that use FP Stack inline asm which the 3626 // backend can't deal with (PR879). 3627 Builder.defineMacro("__NO_MATH_INLINES"); 3628 3629 if (HasAES) 3630 Builder.defineMacro("__AES__"); 3631 3632 if (HasPCLMUL) 3633 Builder.defineMacro("__PCLMUL__"); 3634 3635 if (HasLZCNT) 3636 Builder.defineMacro("__LZCNT__"); 3637 3638 if (HasRDRND) 3639 Builder.defineMacro("__RDRND__"); 3640 3641 if (HasFSGSBASE) 3642 Builder.defineMacro("__FSGSBASE__"); 3643 3644 if (HasBMI) 3645 Builder.defineMacro("__BMI__"); 3646 3647 if (HasBMI2) 3648 Builder.defineMacro("__BMI2__"); 3649 3650 if (HasPOPCNT) 3651 Builder.defineMacro("__POPCNT__"); 3652 3653 if (HasRTM) 3654 Builder.defineMacro("__RTM__"); 3655 3656 if (HasPRFCHW) 3657 Builder.defineMacro("__PRFCHW__"); 3658 3659 if (HasRDSEED) 3660 Builder.defineMacro("__RDSEED__"); 3661 3662 if (HasADX) 3663 Builder.defineMacro("__ADX__"); 3664 3665 if (HasTBM) 3666 Builder.defineMacro("__TBM__"); 3667 3668 if (HasMWAITX) 3669 Builder.defineMacro("__MWAITX__"); 3670 3671 switch (XOPLevel) { 3672 case XOP: 3673 Builder.defineMacro("__XOP__"); 3674 case FMA4: 3675 Builder.defineMacro("__FMA4__"); 3676 case SSE4A: 3677 Builder.defineMacro("__SSE4A__"); 3678 case NoXOP: 3679 break; 3680 } 3681 3682 if (HasFMA) 3683 Builder.defineMacro("__FMA__"); 3684 3685 if (HasF16C) 3686 Builder.defineMacro("__F16C__"); 3687 3688 if (HasAVX512CD) 3689 Builder.defineMacro("__AVX512CD__"); 3690 if (HasAVX512ER) 3691 Builder.defineMacro("__AVX512ER__"); 3692 if (HasAVX512PF) 3693 Builder.defineMacro("__AVX512PF__"); 3694 if (HasAVX512DQ) 3695 Builder.defineMacro("__AVX512DQ__"); 3696 if (HasAVX512BW) 3697 Builder.defineMacro("__AVX512BW__"); 3698 if (HasAVX512VL) 3699 Builder.defineMacro("__AVX512VL__"); 3700 if (HasAVX512VBMI) 3701 Builder.defineMacro("__AVX512VBMI__"); 3702 if (HasAVX512IFMA) 3703 Builder.defineMacro("__AVX512IFMA__"); 3704 3705 if (HasSHA) 3706 Builder.defineMacro("__SHA__"); 3707 3708 if (HasFXSR) 3709 Builder.defineMacro("__FXSR__"); 3710 if (HasXSAVE) 3711 Builder.defineMacro("__XSAVE__"); 3712 if (HasXSAVEOPT) 3713 Builder.defineMacro("__XSAVEOPT__"); 3714 if (HasXSAVEC) 3715 Builder.defineMacro("__XSAVEC__"); 3716 if (HasXSAVES) 3717 Builder.defineMacro("__XSAVES__"); 3718 if (HasPKU) 3719 Builder.defineMacro("__PKU__"); 3720 if (HasCX16) 3721 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3722 3723 // Each case falls through to the previous one here. 3724 switch (SSELevel) { 3725 case AVX512F: 3726 Builder.defineMacro("__AVX512F__"); 3727 case AVX2: 3728 Builder.defineMacro("__AVX2__"); 3729 case AVX: 3730 Builder.defineMacro("__AVX__"); 3731 case SSE42: 3732 Builder.defineMacro("__SSE4_2__"); 3733 case SSE41: 3734 Builder.defineMacro("__SSE4_1__"); 3735 case SSSE3: 3736 Builder.defineMacro("__SSSE3__"); 3737 case SSE3: 3738 Builder.defineMacro("__SSE3__"); 3739 case SSE2: 3740 Builder.defineMacro("__SSE2__"); 3741 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3742 case SSE1: 3743 Builder.defineMacro("__SSE__"); 3744 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3745 case NoSSE: 3746 break; 3747 } 3748 3749 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3750 switch (SSELevel) { 3751 case AVX512F: 3752 case AVX2: 3753 case AVX: 3754 case SSE42: 3755 case SSE41: 3756 case SSSE3: 3757 case SSE3: 3758 case SSE2: 3759 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3760 break; 3761 case SSE1: 3762 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3763 break; 3764 default: 3765 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3766 } 3767 } 3768 3769 // Each case falls through to the previous one here. 3770 switch (MMX3DNowLevel) { 3771 case AMD3DNowAthlon: 3772 Builder.defineMacro("__3dNOW_A__"); 3773 case AMD3DNow: 3774 Builder.defineMacro("__3dNOW__"); 3775 case MMX: 3776 Builder.defineMacro("__MMX__"); 3777 case NoMMX3DNow: 3778 break; 3779 } 3780 3781 if (CPU >= CK_i486) { 3782 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3783 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3784 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3785 } 3786 if (CPU >= CK_i586) 3787 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3788 } 3789 3790 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3791 return llvm::StringSwitch<bool>(Feature) 3792 .Case("aes", HasAES) 3793 .Case("avx", SSELevel >= AVX) 3794 .Case("avx2", SSELevel >= AVX2) 3795 .Case("avx512f", SSELevel >= AVX512F) 3796 .Case("avx512cd", HasAVX512CD) 3797 .Case("avx512er", HasAVX512ER) 3798 .Case("avx512pf", HasAVX512PF) 3799 .Case("avx512dq", HasAVX512DQ) 3800 .Case("avx512bw", HasAVX512BW) 3801 .Case("avx512vl", HasAVX512VL) 3802 .Case("avx512vbmi", HasAVX512VBMI) 3803 .Case("avx512ifma", HasAVX512IFMA) 3804 .Case("bmi", HasBMI) 3805 .Case("bmi2", HasBMI2) 3806 .Case("clflushopt", HasCLFLUSHOPT) 3807 .Case("clwb", HasCLWB) 3808 .Case("cx16", HasCX16) 3809 .Case("f16c", HasF16C) 3810 .Case("fma", HasFMA) 3811 .Case("fma4", XOPLevel >= FMA4) 3812 .Case("fsgsbase", HasFSGSBASE) 3813 .Case("fxsr", HasFXSR) 3814 .Case("lzcnt", HasLZCNT) 3815 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3816 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3817 .Case("mmx", MMX3DNowLevel >= MMX) 3818 .Case("movbe", HasMOVBE) 3819 .Case("mpx", HasMPX) 3820 .Case("pclmul", HasPCLMUL) 3821 .Case("pcommit", HasPCOMMIT) 3822 .Case("pku", HasPKU) 3823 .Case("popcnt", HasPOPCNT) 3824 .Case("prefetchwt1", HasPREFETCHWT1) 3825 .Case("prfchw", HasPRFCHW) 3826 .Case("rdrnd", HasRDRND) 3827 .Case("rdseed", HasRDSEED) 3828 .Case("rtm", HasRTM) 3829 .Case("sgx", HasSGX) 3830 .Case("sha", HasSHA) 3831 .Case("sse", SSELevel >= SSE1) 3832 .Case("sse2", SSELevel >= SSE2) 3833 .Case("sse3", SSELevel >= SSE3) 3834 .Case("ssse3", SSELevel >= SSSE3) 3835 .Case("sse4.1", SSELevel >= SSE41) 3836 .Case("sse4.2", SSELevel >= SSE42) 3837 .Case("sse4a", XOPLevel >= SSE4A) 3838 .Case("tbm", HasTBM) 3839 .Case("umip", HasUMIP) 3840 .Case("x86", true) 3841 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3842 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3843 .Case("xop", XOPLevel >= XOP) 3844 .Case("xsave", HasXSAVE) 3845 .Case("xsavec", HasXSAVEC) 3846 .Case("xsaves", HasXSAVES) 3847 .Case("xsaveopt", HasXSAVEOPT) 3848 .Default(false); 3849 } 3850 3851 // We can't use a generic validation scheme for the features accepted here 3852 // versus subtarget features accepted in the target attribute because the 3853 // bitfield structure that's initialized in the runtime only supports the 3854 // below currently rather than the full range of subtarget features. (See 3855 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3856 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3857 return llvm::StringSwitch<bool>(FeatureStr) 3858 .Case("cmov", true) 3859 .Case("mmx", true) 3860 .Case("popcnt", true) 3861 .Case("sse", true) 3862 .Case("sse2", true) 3863 .Case("sse3", true) 3864 .Case("ssse3", true) 3865 .Case("sse4.1", true) 3866 .Case("sse4.2", true) 3867 .Case("avx", true) 3868 .Case("avx2", true) 3869 .Case("sse4a", true) 3870 .Case("fma4", true) 3871 .Case("xop", true) 3872 .Case("fma", true) 3873 .Case("avx512f", true) 3874 .Case("bmi", true) 3875 .Case("bmi2", true) 3876 .Case("aes", true) 3877 .Case("pclmul", true) 3878 .Case("avx512vl", true) 3879 .Case("avx512bw", true) 3880 .Case("avx512dq", true) 3881 .Case("avx512cd", true) 3882 .Case("avx512er", true) 3883 .Case("avx512pf", true) 3884 .Case("avx512vbmi", true) 3885 .Case("avx512ifma", true) 3886 .Default(false); 3887 } 3888 3889 bool 3890 X86TargetInfo::validateAsmConstraint(const char *&Name, 3891 TargetInfo::ConstraintInfo &Info) const { 3892 switch (*Name) { 3893 default: return false; 3894 // Constant constraints. 3895 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3896 // instructions. 3897 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3898 // x86_64 instructions. 3899 case 's': 3900 Info.setRequiresImmediate(); 3901 return true; 3902 case 'I': 3903 Info.setRequiresImmediate(0, 31); 3904 return true; 3905 case 'J': 3906 Info.setRequiresImmediate(0, 63); 3907 return true; 3908 case 'K': 3909 Info.setRequiresImmediate(-128, 127); 3910 return true; 3911 case 'L': 3912 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3913 return true; 3914 case 'M': 3915 Info.setRequiresImmediate(0, 3); 3916 return true; 3917 case 'N': 3918 Info.setRequiresImmediate(0, 255); 3919 return true; 3920 case 'O': 3921 Info.setRequiresImmediate(0, 127); 3922 return true; 3923 // Register constraints. 3924 case 'Y': // 'Y' is the first character for several 2-character constraints. 3925 // Shift the pointer to the second character of the constraint. 3926 Name++; 3927 switch (*Name) { 3928 default: 3929 return false; 3930 case '0': // First SSE register. 3931 case 't': // Any SSE register, when SSE2 is enabled. 3932 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3933 case 'm': // Any MMX register, when inter-unit moves enabled. 3934 Info.setAllowsRegister(); 3935 return true; 3936 } 3937 case 'f': // Any x87 floating point stack register. 3938 // Constraint 'f' cannot be used for output operands. 3939 if (Info.ConstraintStr[0] == '=') 3940 return false; 3941 Info.setAllowsRegister(); 3942 return true; 3943 case 'a': // eax. 3944 case 'b': // ebx. 3945 case 'c': // ecx. 3946 case 'd': // edx. 3947 case 'S': // esi. 3948 case 'D': // edi. 3949 case 'A': // edx:eax. 3950 case 't': // Top of floating point stack. 3951 case 'u': // Second from top of floating point stack. 3952 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3953 case 'y': // Any MMX register. 3954 case 'x': // Any SSE register. 3955 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3956 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3957 case 'l': // "Index" registers: any general register that can be used as an 3958 // index in a base+index memory access. 3959 Info.setAllowsRegister(); 3960 return true; 3961 // Floating point constant constraints. 3962 case 'C': // SSE floating point constant. 3963 case 'G': // x87 floating point constant. 3964 return true; 3965 } 3966 } 3967 3968 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3969 unsigned Size) const { 3970 // Strip off constraint modifiers. 3971 while (Constraint[0] == '=' || 3972 Constraint[0] == '+' || 3973 Constraint[0] == '&') 3974 Constraint = Constraint.substr(1); 3975 3976 return validateOperandSize(Constraint, Size); 3977 } 3978 3979 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3980 unsigned Size) const { 3981 return validateOperandSize(Constraint, Size); 3982 } 3983 3984 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3985 unsigned Size) const { 3986 switch (Constraint[0]) { 3987 default: break; 3988 case 'y': 3989 return Size <= 64; 3990 case 'f': 3991 case 't': 3992 case 'u': 3993 return Size <= 128; 3994 case 'x': 3995 if (SSELevel >= AVX512F) 3996 // 512-bit zmm registers can be used if target supports AVX512F. 3997 return Size <= 512U; 3998 else if (SSELevel >= AVX) 3999 // 256-bit ymm registers can be used if target supports AVX. 4000 return Size <= 256U; 4001 return Size <= 128U; 4002 case 'Y': 4003 // 'Y' is the first character for several 2-character constraints. 4004 switch (Constraint[1]) { 4005 default: break; 4006 case 'm': 4007 // 'Ym' is synonymous with 'y'. 4008 return Size <= 64; 4009 case 'i': 4010 case 't': 4011 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4012 if (SSELevel >= AVX512F) 4013 return Size <= 512U; 4014 else if (SSELevel >= AVX) 4015 return Size <= 256U; 4016 return SSELevel >= SSE2 && Size <= 128U; 4017 } 4018 4019 } 4020 4021 return true; 4022 } 4023 4024 std::string 4025 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4026 switch (*Constraint) { 4027 case 'a': return std::string("{ax}"); 4028 case 'b': return std::string("{bx}"); 4029 case 'c': return std::string("{cx}"); 4030 case 'd': return std::string("{dx}"); 4031 case 'S': return std::string("{si}"); 4032 case 'D': return std::string("{di}"); 4033 case 'p': // address 4034 return std::string("im"); 4035 case 't': // top of floating point stack. 4036 return std::string("{st}"); 4037 case 'u': // second from top of floating point stack. 4038 return std::string("{st(1)}"); // second from top of floating point stack. 4039 default: 4040 return std::string(1, *Constraint); 4041 } 4042 } 4043 4044 // X86-32 generic target 4045 class X86_32TargetInfo : public X86TargetInfo { 4046 public: 4047 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4048 : X86TargetInfo(Triple, Opts) { 4049 DoubleAlign = LongLongAlign = 32; 4050 LongDoubleWidth = 96; 4051 LongDoubleAlign = 32; 4052 SuitableAlign = 128; 4053 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4054 SizeType = UnsignedInt; 4055 PtrDiffType = SignedInt; 4056 IntPtrType = SignedInt; 4057 RegParmMax = 3; 4058 4059 // Use fpret for all types. 4060 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4061 (1 << TargetInfo::Double) | 4062 (1 << TargetInfo::LongDouble)); 4063 4064 // x86-32 has atomics up to 8 bytes 4065 // FIXME: Check that we actually have cmpxchg8b before setting 4066 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4067 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4068 } 4069 BuiltinVaListKind getBuiltinVaListKind() const override { 4070 return TargetInfo::CharPtrBuiltinVaList; 4071 } 4072 4073 int getEHDataRegisterNumber(unsigned RegNo) const override { 4074 if (RegNo == 0) return 0; 4075 if (RegNo == 1) return 2; 4076 return -1; 4077 } 4078 bool validateOperandSize(StringRef Constraint, 4079 unsigned Size) const override { 4080 switch (Constraint[0]) { 4081 default: break; 4082 case 'R': 4083 case 'q': 4084 case 'Q': 4085 case 'a': 4086 case 'b': 4087 case 'c': 4088 case 'd': 4089 case 'S': 4090 case 'D': 4091 return Size <= 32; 4092 case 'A': 4093 return Size <= 64; 4094 } 4095 4096 return X86TargetInfo::validateOperandSize(Constraint, Size); 4097 } 4098 }; 4099 4100 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4101 public: 4102 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4103 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4104 4105 unsigned getFloatEvalMethod() const override { 4106 unsigned Major, Minor, Micro; 4107 getTriple().getOSVersion(Major, Minor, Micro); 4108 // New NetBSD uses the default rounding mode. 4109 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4110 return X86_32TargetInfo::getFloatEvalMethod(); 4111 // NetBSD before 6.99.26 defaults to "double" rounding. 4112 return 1; 4113 } 4114 }; 4115 4116 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4117 public: 4118 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4119 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4120 SizeType = UnsignedLong; 4121 IntPtrType = SignedLong; 4122 PtrDiffType = SignedLong; 4123 } 4124 }; 4125 4126 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4127 public: 4128 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4129 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4130 SizeType = UnsignedLong; 4131 IntPtrType = SignedLong; 4132 PtrDiffType = SignedLong; 4133 } 4134 }; 4135 4136 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4137 public: 4138 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4139 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4140 LongDoubleWidth = 128; 4141 LongDoubleAlign = 128; 4142 SuitableAlign = 128; 4143 MaxVectorAlign = 256; 4144 // The watchOS simulator uses the builtin bool type for Objective-C. 4145 llvm::Triple T = llvm::Triple(Triple); 4146 if (T.isWatchOS()) 4147 UseSignedCharForObjCBool = false; 4148 SizeType = UnsignedLong; 4149 IntPtrType = SignedLong; 4150 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4151 HasAlignMac68kSupport = true; 4152 } 4153 4154 bool handleTargetFeatures(std::vector<std::string> &Features, 4155 DiagnosticsEngine &Diags) override { 4156 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4157 Diags)) 4158 return false; 4159 // We now know the features we have: we can decide how to align vectors. 4160 MaxVectorAlign = 4161 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4162 return true; 4163 } 4164 }; 4165 4166 // x86-32 Windows target 4167 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4168 public: 4169 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4170 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4171 WCharType = UnsignedShort; 4172 DoubleAlign = LongLongAlign = 64; 4173 bool IsWinCOFF = 4174 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4175 resetDataLayout(IsWinCOFF 4176 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4177 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4178 } 4179 void getTargetDefines(const LangOptions &Opts, 4180 MacroBuilder &Builder) const override { 4181 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4182 } 4183 }; 4184 4185 // x86-32 Windows Visual Studio target 4186 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4187 public: 4188 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4189 const TargetOptions &Opts) 4190 : WindowsX86_32TargetInfo(Triple, Opts) { 4191 LongDoubleWidth = LongDoubleAlign = 64; 4192 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4193 } 4194 void getTargetDefines(const LangOptions &Opts, 4195 MacroBuilder &Builder) const override { 4196 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4197 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4198 // The value of the following reflects processor type. 4199 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4200 // We lost the original triple, so we use the default. 4201 Builder.defineMacro("_M_IX86", "600"); 4202 } 4203 }; 4204 4205 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4206 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4207 // supports __declspec natively under -fms-extensions, but we define a no-op 4208 // __declspec macro anyway for pre-processor compatibility. 4209 if (Opts.MicrosoftExt) 4210 Builder.defineMacro("__declspec", "__declspec"); 4211 else 4212 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4213 4214 if (!Opts.MicrosoftExt) { 4215 // Provide macros for all the calling convention keywords. Provide both 4216 // single and double underscore prefixed variants. These are available on 4217 // x64 as well as x86, even though they have no effect. 4218 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4219 for (const char *CC : CCs) { 4220 std::string GCCSpelling = "__attribute__((__"; 4221 GCCSpelling += CC; 4222 GCCSpelling += "__))"; 4223 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4224 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4225 } 4226 } 4227 } 4228 4229 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4230 Builder.defineMacro("__MSVCRT__"); 4231 Builder.defineMacro("__MINGW32__"); 4232 addCygMingDefines(Opts, Builder); 4233 } 4234 4235 // x86-32 MinGW target 4236 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4237 public: 4238 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4239 : WindowsX86_32TargetInfo(Triple, Opts) {} 4240 void getTargetDefines(const LangOptions &Opts, 4241 MacroBuilder &Builder) const override { 4242 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4243 DefineStd(Builder, "WIN32", Opts); 4244 DefineStd(Builder, "WINNT", Opts); 4245 Builder.defineMacro("_X86_"); 4246 addMinGWDefines(Opts, Builder); 4247 } 4248 }; 4249 4250 // x86-32 Cygwin target 4251 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4252 public: 4253 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4254 : X86_32TargetInfo(Triple, Opts) { 4255 WCharType = UnsignedShort; 4256 DoubleAlign = LongLongAlign = 64; 4257 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4258 } 4259 void getTargetDefines(const LangOptions &Opts, 4260 MacroBuilder &Builder) const override { 4261 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4262 Builder.defineMacro("_X86_"); 4263 Builder.defineMacro("__CYGWIN__"); 4264 Builder.defineMacro("__CYGWIN32__"); 4265 addCygMingDefines(Opts, Builder); 4266 DefineStd(Builder, "unix", Opts); 4267 if (Opts.CPlusPlus) 4268 Builder.defineMacro("_GNU_SOURCE"); 4269 } 4270 }; 4271 4272 // x86-32 Haiku target 4273 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4274 public: 4275 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4276 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4277 } 4278 void getTargetDefines(const LangOptions &Opts, 4279 MacroBuilder &Builder) const override { 4280 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4281 Builder.defineMacro("__INTEL__"); 4282 } 4283 }; 4284 4285 // X86-32 MCU target 4286 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4287 public: 4288 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4289 : X86_32TargetInfo(Triple, Opts) { 4290 LongDoubleWidth = 64; 4291 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4292 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4293 WIntType = UnsignedInt; 4294 } 4295 4296 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4297 // On MCU we support only C calling convention. 4298 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4299 } 4300 4301 void getTargetDefines(const LangOptions &Opts, 4302 MacroBuilder &Builder) const override { 4303 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4304 Builder.defineMacro("__iamcu"); 4305 Builder.defineMacro("__iamcu__"); 4306 } 4307 4308 bool allowsLargerPreferedTypeAlignment() const override { 4309 return false; 4310 } 4311 }; 4312 4313 // RTEMS Target 4314 template<typename Target> 4315 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4316 protected: 4317 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4318 MacroBuilder &Builder) const override { 4319 // RTEMS defines; list based off of gcc output 4320 4321 Builder.defineMacro("__rtems__"); 4322 Builder.defineMacro("__ELF__"); 4323 } 4324 4325 public: 4326 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4327 : OSTargetInfo<Target>(Triple, Opts) { 4328 switch (Triple.getArch()) { 4329 default: 4330 case llvm::Triple::x86: 4331 // this->MCountName = ".mcount"; 4332 break; 4333 case llvm::Triple::mips: 4334 case llvm::Triple::mipsel: 4335 case llvm::Triple::ppc: 4336 case llvm::Triple::ppc64: 4337 case llvm::Triple::ppc64le: 4338 // this->MCountName = "_mcount"; 4339 break; 4340 case llvm::Triple::arm: 4341 // this->MCountName = "__mcount"; 4342 break; 4343 } 4344 } 4345 }; 4346 4347 // x86-32 RTEMS target 4348 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4349 public: 4350 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4351 : X86_32TargetInfo(Triple, Opts) { 4352 SizeType = UnsignedLong; 4353 IntPtrType = SignedLong; 4354 PtrDiffType = SignedLong; 4355 } 4356 void getTargetDefines(const LangOptions &Opts, 4357 MacroBuilder &Builder) const override { 4358 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4359 Builder.defineMacro("__INTEL__"); 4360 Builder.defineMacro("__rtems__"); 4361 } 4362 }; 4363 4364 // x86-64 generic target 4365 class X86_64TargetInfo : public X86TargetInfo { 4366 public: 4367 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4368 : X86TargetInfo(Triple, Opts) { 4369 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4370 bool IsWinCOFF = 4371 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4372 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4373 LongDoubleWidth = 128; 4374 LongDoubleAlign = 128; 4375 LargeArrayMinWidth = 128; 4376 LargeArrayAlign = 128; 4377 SuitableAlign = 128; 4378 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4379 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4380 IntPtrType = IsX32 ? SignedInt : SignedLong; 4381 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4382 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4383 RegParmMax = 6; 4384 4385 // Pointers are 32-bit in x32. 4386 resetDataLayout(IsX32 4387 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4388 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4389 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4390 4391 // Use fpret only for long double. 4392 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4393 4394 // Use fp2ret for _Complex long double. 4395 ComplexLongDoubleUsesFP2Ret = true; 4396 4397 // Make __builtin_ms_va_list available. 4398 HasBuiltinMSVaList = true; 4399 4400 // x86-64 has atomics up to 16 bytes. 4401 MaxAtomicPromoteWidth = 128; 4402 MaxAtomicInlineWidth = 128; 4403 } 4404 BuiltinVaListKind getBuiltinVaListKind() const override { 4405 return TargetInfo::X86_64ABIBuiltinVaList; 4406 } 4407 4408 int getEHDataRegisterNumber(unsigned RegNo) const override { 4409 if (RegNo == 0) return 0; 4410 if (RegNo == 1) return 1; 4411 return -1; 4412 } 4413 4414 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4415 switch (CC) { 4416 case CC_C: 4417 case CC_Swift: 4418 case CC_X86VectorCall: 4419 case CC_IntelOclBicc: 4420 case CC_X86_64Win64: 4421 case CC_PreserveMost: 4422 case CC_PreserveAll: 4423 return CCCR_OK; 4424 default: 4425 return CCCR_Warning; 4426 } 4427 } 4428 4429 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4430 return CC_C; 4431 } 4432 4433 // for x32 we need it here explicitly 4434 bool hasInt128Type() const override { return true; } 4435 unsigned getUnwindWordWidth() const override { return 64; } 4436 unsigned getRegisterWidth() const override { return 64; } 4437 4438 bool validateGlobalRegisterVariable(StringRef RegName, 4439 unsigned RegSize, 4440 bool &HasSizeMismatch) const override { 4441 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4442 // handle. 4443 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4444 // Check that the register size is 64-bit. 4445 HasSizeMismatch = RegSize != 64; 4446 return true; 4447 } 4448 4449 // Check if the register is a 32-bit register the backend can handle. 4450 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4451 HasSizeMismatch); 4452 } 4453 }; 4454 4455 // x86-64 Windows target 4456 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4457 public: 4458 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4459 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4460 WCharType = UnsignedShort; 4461 LongWidth = LongAlign = 32; 4462 DoubleAlign = LongLongAlign = 64; 4463 IntMaxType = SignedLongLong; 4464 Int64Type = SignedLongLong; 4465 SizeType = UnsignedLongLong; 4466 PtrDiffType = SignedLongLong; 4467 IntPtrType = SignedLongLong; 4468 } 4469 4470 void getTargetDefines(const LangOptions &Opts, 4471 MacroBuilder &Builder) const override { 4472 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4473 Builder.defineMacro("_WIN64"); 4474 } 4475 4476 BuiltinVaListKind getBuiltinVaListKind() const override { 4477 return TargetInfo::CharPtrBuiltinVaList; 4478 } 4479 4480 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4481 switch (CC) { 4482 case CC_X86StdCall: 4483 case CC_X86ThisCall: 4484 case CC_X86FastCall: 4485 return CCCR_Ignore; 4486 case CC_C: 4487 case CC_X86VectorCall: 4488 case CC_IntelOclBicc: 4489 case CC_X86_64SysV: 4490 return CCCR_OK; 4491 default: 4492 return CCCR_Warning; 4493 } 4494 } 4495 }; 4496 4497 // x86-64 Windows Visual Studio target 4498 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4499 public: 4500 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4501 const TargetOptions &Opts) 4502 : WindowsX86_64TargetInfo(Triple, Opts) { 4503 LongDoubleWidth = LongDoubleAlign = 64; 4504 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4505 } 4506 void getTargetDefines(const LangOptions &Opts, 4507 MacroBuilder &Builder) const override { 4508 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4509 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4510 Builder.defineMacro("_M_X64", "100"); 4511 Builder.defineMacro("_M_AMD64", "100"); 4512 } 4513 }; 4514 4515 // x86-64 MinGW target 4516 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4517 public: 4518 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4519 : WindowsX86_64TargetInfo(Triple, Opts) { 4520 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4521 // with x86 FP ops. Weird. 4522 LongDoubleWidth = LongDoubleAlign = 128; 4523 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4524 } 4525 4526 void getTargetDefines(const LangOptions &Opts, 4527 MacroBuilder &Builder) const override { 4528 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4529 DefineStd(Builder, "WIN64", Opts); 4530 Builder.defineMacro("__MINGW64__"); 4531 addMinGWDefines(Opts, Builder); 4532 4533 // GCC defines this macro when it is using __gxx_personality_seh0. 4534 if (!Opts.SjLjExceptions) 4535 Builder.defineMacro("__SEH__"); 4536 } 4537 }; 4538 4539 // x86-64 Cygwin target 4540 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4541 public: 4542 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4543 : X86_64TargetInfo(Triple, Opts) { 4544 TLSSupported = false; 4545 WCharType = UnsignedShort; 4546 } 4547 void getTargetDefines(const LangOptions &Opts, 4548 MacroBuilder &Builder) const override { 4549 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4550 Builder.defineMacro("__x86_64__"); 4551 Builder.defineMacro("__CYGWIN__"); 4552 Builder.defineMacro("__CYGWIN64__"); 4553 addCygMingDefines(Opts, Builder); 4554 DefineStd(Builder, "unix", Opts); 4555 if (Opts.CPlusPlus) 4556 Builder.defineMacro("_GNU_SOURCE"); 4557 4558 // GCC defines this macro when it is using __gxx_personality_seh0. 4559 if (!Opts.SjLjExceptions) 4560 Builder.defineMacro("__SEH__"); 4561 } 4562 }; 4563 4564 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4565 public: 4566 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4567 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4568 Int64Type = SignedLongLong; 4569 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4570 llvm::Triple T = llvm::Triple(Triple); 4571 if (T.isiOS()) 4572 UseSignedCharForObjCBool = false; 4573 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4574 } 4575 4576 bool handleTargetFeatures(std::vector<std::string> &Features, 4577 DiagnosticsEngine &Diags) override { 4578 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4579 Diags)) 4580 return false; 4581 // We now know the features we have: we can decide how to align vectors. 4582 MaxVectorAlign = 4583 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4584 return true; 4585 } 4586 }; 4587 4588 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4589 public: 4590 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4591 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4592 IntMaxType = SignedLongLong; 4593 Int64Type = SignedLongLong; 4594 } 4595 }; 4596 4597 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4598 public: 4599 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4600 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4601 IntMaxType = SignedLongLong; 4602 Int64Type = SignedLongLong; 4603 } 4604 }; 4605 4606 class ARMTargetInfo : public TargetInfo { 4607 // Possible FPU choices. 4608 enum FPUMode { 4609 VFP2FPU = (1 << 0), 4610 VFP3FPU = (1 << 1), 4611 VFP4FPU = (1 << 2), 4612 NeonFPU = (1 << 3), 4613 FPARMV8 = (1 << 4) 4614 }; 4615 4616 // Possible HWDiv features. 4617 enum HWDivMode { 4618 HWDivThumb = (1 << 0), 4619 HWDivARM = (1 << 1) 4620 }; 4621 4622 static bool FPUModeIsVFP(FPUMode Mode) { 4623 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4624 } 4625 4626 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4627 static const char * const GCCRegNames[]; 4628 4629 std::string ABI, CPU; 4630 4631 StringRef CPUProfile; 4632 StringRef CPUAttr; 4633 4634 enum { 4635 FP_Default, 4636 FP_VFP, 4637 FP_Neon 4638 } FPMath; 4639 4640 unsigned ArchISA; 4641 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4642 unsigned ArchProfile; 4643 unsigned ArchVersion; 4644 4645 unsigned FPU : 5; 4646 4647 unsigned IsAAPCS : 1; 4648 unsigned HWDiv : 2; 4649 4650 // Initialized via features. 4651 unsigned SoftFloat : 1; 4652 unsigned SoftFloatABI : 1; 4653 4654 unsigned CRC : 1; 4655 unsigned Crypto : 1; 4656 unsigned DSP : 1; 4657 unsigned Unaligned : 1; 4658 4659 enum { 4660 LDREX_B = (1 << 0), /// byte (8-bit) 4661 LDREX_H = (1 << 1), /// half (16-bit) 4662 LDREX_W = (1 << 2), /// word (32-bit) 4663 LDREX_D = (1 << 3), /// double (64-bit) 4664 }; 4665 4666 uint32_t LDREX; 4667 4668 // ACLE 6.5.1 Hardware floating point 4669 enum { 4670 HW_FP_HP = (1 << 1), /// half (16-bit) 4671 HW_FP_SP = (1 << 2), /// single (32-bit) 4672 HW_FP_DP = (1 << 3), /// double (64-bit) 4673 }; 4674 uint32_t HW_FP; 4675 4676 static const Builtin::Info BuiltinInfo[]; 4677 4678 void setABIAAPCS() { 4679 IsAAPCS = true; 4680 4681 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4682 const llvm::Triple &T = getTriple(); 4683 4684 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4685 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4686 T.getOS() == llvm::Triple::Bitrig) 4687 SizeType = UnsignedLong; 4688 else 4689 SizeType = UnsignedInt; 4690 4691 switch (T.getOS()) { 4692 case llvm::Triple::NetBSD: 4693 WCharType = SignedInt; 4694 break; 4695 case llvm::Triple::Win32: 4696 WCharType = UnsignedShort; 4697 break; 4698 case llvm::Triple::Linux: 4699 default: 4700 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4701 WCharType = UnsignedInt; 4702 break; 4703 } 4704 4705 UseBitFieldTypeAlignment = true; 4706 4707 ZeroLengthBitfieldBoundary = 0; 4708 4709 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4710 // so set preferred for small types to 32. 4711 if (T.isOSBinFormatMachO()) { 4712 resetDataLayout(BigEndian 4713 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4714 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4715 } else if (T.isOSWindows()) { 4716 assert(!BigEndian && "Windows on ARM does not support big endian"); 4717 resetDataLayout("e" 4718 "-m:w" 4719 "-p:32:32" 4720 "-i64:64" 4721 "-v128:64:128" 4722 "-a:0:32" 4723 "-n32" 4724 "-S64"); 4725 } else if (T.isOSNaCl()) { 4726 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4727 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4728 } else { 4729 resetDataLayout(BigEndian 4730 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4731 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4732 } 4733 4734 // FIXME: Enumerated types are variable width in straight AAPCS. 4735 } 4736 4737 void setABIAPCS(bool IsAAPCS16) { 4738 const llvm::Triple &T = getTriple(); 4739 4740 IsAAPCS = false; 4741 4742 if (IsAAPCS16) 4743 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4744 else 4745 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4746 4747 // size_t is unsigned int on FreeBSD. 4748 if (T.getOS() == llvm::Triple::FreeBSD) 4749 SizeType = UnsignedInt; 4750 else 4751 SizeType = UnsignedLong; 4752 4753 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4754 WCharType = SignedInt; 4755 4756 // Do not respect the alignment of bit-field types when laying out 4757 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4758 UseBitFieldTypeAlignment = false; 4759 4760 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4761 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4762 /// gcc. 4763 ZeroLengthBitfieldBoundary = 32; 4764 4765 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4766 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4767 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4768 } else if (T.isOSBinFormatMachO()) 4769 resetDataLayout( 4770 BigEndian 4771 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4772 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4773 else 4774 resetDataLayout( 4775 BigEndian 4776 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4777 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4778 4779 // FIXME: Override "preferred align" for double and long long. 4780 } 4781 4782 void setArchInfo() { 4783 StringRef ArchName = getTriple().getArchName(); 4784 4785 ArchISA = llvm::ARM::parseArchISA(ArchName); 4786 CPU = llvm::ARM::getDefaultCPU(ArchName); 4787 unsigned AK = llvm::ARM::parseArch(ArchName); 4788 if (AK != llvm::ARM::AK_INVALID) 4789 ArchKind = AK; 4790 setArchInfo(ArchKind); 4791 } 4792 4793 void setArchInfo(unsigned Kind) { 4794 StringRef SubArch; 4795 4796 // cache TargetParser info 4797 ArchKind = Kind; 4798 SubArch = llvm::ARM::getSubArch(ArchKind); 4799 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4800 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4801 4802 // cache CPU related strings 4803 CPUAttr = getCPUAttr(); 4804 CPUProfile = getCPUProfile(); 4805 } 4806 4807 void setAtomic() { 4808 // when triple does not specify a sub arch, 4809 // then we are not using inline atomics 4810 bool ShouldUseInlineAtomic = 4811 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4812 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4813 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4814 if (ArchProfile == llvm::ARM::PK_M) { 4815 MaxAtomicPromoteWidth = 32; 4816 if (ShouldUseInlineAtomic) 4817 MaxAtomicInlineWidth = 32; 4818 } 4819 else { 4820 MaxAtomicPromoteWidth = 64; 4821 if (ShouldUseInlineAtomic) 4822 MaxAtomicInlineWidth = 64; 4823 } 4824 } 4825 4826 bool isThumb() const { 4827 return (ArchISA == llvm::ARM::IK_THUMB); 4828 } 4829 4830 bool supportsThumb() const { 4831 return CPUAttr.count('T') || ArchVersion >= 6; 4832 } 4833 4834 bool supportsThumb2() const { 4835 return CPUAttr.equals("6T2") || 4836 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 4837 } 4838 4839 StringRef getCPUAttr() const { 4840 // For most sub-arches, the build attribute CPU name is enough. 4841 // For Cortex variants, it's slightly different. 4842 switch(ArchKind) { 4843 default: 4844 return llvm::ARM::getCPUAttr(ArchKind); 4845 case llvm::ARM::AK_ARMV6M: 4846 return "6M"; 4847 case llvm::ARM::AK_ARMV7S: 4848 return "7S"; 4849 case llvm::ARM::AK_ARMV7A: 4850 return "7A"; 4851 case llvm::ARM::AK_ARMV7R: 4852 return "7R"; 4853 case llvm::ARM::AK_ARMV7M: 4854 return "7M"; 4855 case llvm::ARM::AK_ARMV7EM: 4856 return "7EM"; 4857 case llvm::ARM::AK_ARMV8A: 4858 return "8A"; 4859 case llvm::ARM::AK_ARMV8_1A: 4860 return "8_1A"; 4861 case llvm::ARM::AK_ARMV8_2A: 4862 return "8_2A"; 4863 case llvm::ARM::AK_ARMV8MBaseline: 4864 return "8M_BASE"; 4865 case llvm::ARM::AK_ARMV8MMainline: 4866 return "8M_MAIN"; 4867 } 4868 } 4869 4870 StringRef getCPUProfile() const { 4871 switch(ArchProfile) { 4872 case llvm::ARM::PK_A: 4873 return "A"; 4874 case llvm::ARM::PK_R: 4875 return "R"; 4876 case llvm::ARM::PK_M: 4877 return "M"; 4878 default: 4879 return ""; 4880 } 4881 } 4882 4883 public: 4884 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4885 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 4886 HW_FP(0) { 4887 4888 switch (getTriple().getOS()) { 4889 case llvm::Triple::NetBSD: 4890 PtrDiffType = SignedLong; 4891 break; 4892 default: 4893 PtrDiffType = SignedInt; 4894 break; 4895 } 4896 4897 // Cache arch related info. 4898 setArchInfo(); 4899 4900 // {} in inline assembly are neon specifiers, not assembly variant 4901 // specifiers. 4902 NoAsmVariants = true; 4903 4904 // FIXME: This duplicates code from the driver that sets the -target-abi 4905 // option - this code is used if -target-abi isn't passed and should 4906 // be unified in some way. 4907 if (Triple.isOSBinFormatMachO()) { 4908 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4909 // the frontend matches that. 4910 if (Triple.getEnvironment() == llvm::Triple::EABI || 4911 Triple.getOS() == llvm::Triple::UnknownOS || 4912 ArchProfile == llvm::ARM::PK_M) { 4913 setABI("aapcs"); 4914 } else if (Triple.isWatchABI()) { 4915 setABI("aapcs16"); 4916 } else { 4917 setABI("apcs-gnu"); 4918 } 4919 } else if (Triple.isOSWindows()) { 4920 // FIXME: this is invalid for WindowsCE 4921 setABI("aapcs"); 4922 } else { 4923 // Select the default based on the platform. 4924 switch (Triple.getEnvironment()) { 4925 case llvm::Triple::Android: 4926 case llvm::Triple::GNUEABI: 4927 case llvm::Triple::GNUEABIHF: 4928 case llvm::Triple::MuslEABI: 4929 case llvm::Triple::MuslEABIHF: 4930 setABI("aapcs-linux"); 4931 break; 4932 case llvm::Triple::EABIHF: 4933 case llvm::Triple::EABI: 4934 setABI("aapcs"); 4935 break; 4936 case llvm::Triple::GNU: 4937 setABI("apcs-gnu"); 4938 break; 4939 default: 4940 if (Triple.getOS() == llvm::Triple::NetBSD) 4941 setABI("apcs-gnu"); 4942 else 4943 setABI("aapcs"); 4944 break; 4945 } 4946 } 4947 4948 // ARM targets default to using the ARM C++ ABI. 4949 TheCXXABI.set(TargetCXXABI::GenericARM); 4950 4951 // ARM has atomics up to 8 bytes 4952 setAtomic(); 4953 4954 // Do force alignment of members that follow zero length bitfields. If 4955 // the alignment of the zero-length bitfield is greater than the member 4956 // that follows it, `bar', `bar' will be aligned as the type of the 4957 // zero length bitfield. 4958 UseZeroLengthBitfieldAlignment = true; 4959 4960 if (Triple.getOS() == llvm::Triple::Linux || 4961 Triple.getOS() == llvm::Triple::UnknownOS) 4962 this->MCountName = 4963 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 4964 } 4965 4966 StringRef getABI() const override { return ABI; } 4967 4968 bool setABI(const std::string &Name) override { 4969 ABI = Name; 4970 4971 // The defaults (above) are for AAPCS, check if we need to change them. 4972 // 4973 // FIXME: We need support for -meabi... we could just mangle it into the 4974 // name. 4975 if (Name == "apcs-gnu" || Name == "aapcs16") { 4976 setABIAPCS(Name == "aapcs16"); 4977 return true; 4978 } 4979 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4980 setABIAAPCS(); 4981 return true; 4982 } 4983 return false; 4984 } 4985 4986 // FIXME: This should be based on Arch attributes, not CPU names. 4987 bool 4988 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4989 StringRef CPU, 4990 const std::vector<std::string> &FeaturesVec) const override { 4991 4992 std::vector<const char*> TargetFeatures; 4993 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4994 4995 // get default FPU features 4996 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4997 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4998 4999 // get default Extension features 5000 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 5001 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 5002 5003 for (const char *Feature : TargetFeatures) 5004 if (Feature[0] == '+') 5005 Features[Feature+1] = true; 5006 5007 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5008 } 5009 5010 bool handleTargetFeatures(std::vector<std::string> &Features, 5011 DiagnosticsEngine &Diags) override { 5012 FPU = 0; 5013 CRC = 0; 5014 Crypto = 0; 5015 DSP = 0; 5016 Unaligned = 1; 5017 SoftFloat = SoftFloatABI = false; 5018 HWDiv = 0; 5019 5020 // This does not diagnose illegal cases like having both 5021 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5022 uint32_t HW_FP_remove = 0; 5023 for (const auto &Feature : Features) { 5024 if (Feature == "+soft-float") { 5025 SoftFloat = true; 5026 } else if (Feature == "+soft-float-abi") { 5027 SoftFloatABI = true; 5028 } else if (Feature == "+vfp2") { 5029 FPU |= VFP2FPU; 5030 HW_FP |= HW_FP_SP | HW_FP_DP; 5031 } else if (Feature == "+vfp3") { 5032 FPU |= VFP3FPU; 5033 HW_FP |= HW_FP_SP | HW_FP_DP; 5034 } else if (Feature == "+vfp4") { 5035 FPU |= VFP4FPU; 5036 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5037 } else if (Feature == "+fp-armv8") { 5038 FPU |= FPARMV8; 5039 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5040 } else if (Feature == "+neon") { 5041 FPU |= NeonFPU; 5042 HW_FP |= HW_FP_SP | HW_FP_DP; 5043 } else if (Feature == "+hwdiv") { 5044 HWDiv |= HWDivThumb; 5045 } else if (Feature == "+hwdiv-arm") { 5046 HWDiv |= HWDivARM; 5047 } else if (Feature == "+crc") { 5048 CRC = 1; 5049 } else if (Feature == "+crypto") { 5050 Crypto = 1; 5051 } else if (Feature == "+dsp") { 5052 DSP = 1; 5053 } else if (Feature == "+fp-only-sp") { 5054 HW_FP_remove |= HW_FP_DP; 5055 } else if (Feature == "+strict-align") { 5056 Unaligned = 0; 5057 } else if (Feature == "+fp16") { 5058 HW_FP |= HW_FP_HP; 5059 } 5060 } 5061 HW_FP &= ~HW_FP_remove; 5062 5063 switch (ArchVersion) { 5064 case 6: 5065 if (ArchProfile == llvm::ARM::PK_M) 5066 LDREX = 0; 5067 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5068 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5069 else 5070 LDREX = LDREX_W; 5071 break; 5072 case 7: 5073 if (ArchProfile == llvm::ARM::PK_M) 5074 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5075 else 5076 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5077 break; 5078 case 8: 5079 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5080 } 5081 5082 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5083 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5084 return false; 5085 } 5086 5087 if (FPMath == FP_Neon) 5088 Features.push_back("+neonfp"); 5089 else if (FPMath == FP_VFP) 5090 Features.push_back("-neonfp"); 5091 5092 // Remove front-end specific options which the backend handles differently. 5093 auto Feature = 5094 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5095 if (Feature != Features.end()) 5096 Features.erase(Feature); 5097 5098 return true; 5099 } 5100 5101 bool hasFeature(StringRef Feature) const override { 5102 return llvm::StringSwitch<bool>(Feature) 5103 .Case("arm", true) 5104 .Case("aarch32", true) 5105 .Case("softfloat", SoftFloat) 5106 .Case("thumb", isThumb()) 5107 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5108 .Case("hwdiv", HWDiv & HWDivThumb) 5109 .Case("hwdiv-arm", HWDiv & HWDivARM) 5110 .Default(false); 5111 } 5112 5113 bool setCPU(const std::string &Name) override { 5114 if (Name != "generic") 5115 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5116 5117 if (ArchKind == llvm::ARM::AK_INVALID) 5118 return false; 5119 setAtomic(); 5120 CPU = Name; 5121 return true; 5122 } 5123 5124 bool setFPMath(StringRef Name) override; 5125 5126 void getTargetDefines(const LangOptions &Opts, 5127 MacroBuilder &Builder) const override { 5128 // Target identification. 5129 Builder.defineMacro("__arm"); 5130 Builder.defineMacro("__arm__"); 5131 // For bare-metal none-eabi. 5132 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5133 getTriple().getEnvironment() == llvm::Triple::EABI) 5134 Builder.defineMacro("__ELF__"); 5135 5136 // Target properties. 5137 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5138 5139 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5140 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5141 if (getTriple().isWatchABI()) 5142 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5143 5144 if (!CPUAttr.empty()) 5145 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5146 5147 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5148 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5149 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5150 5151 if (ArchVersion >= 8) { 5152 // ACLE 6.5.7 Crypto Extension 5153 if (Crypto) 5154 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5155 // ACLE 6.5.8 CRC32 Extension 5156 if (CRC) 5157 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5158 // ACLE 6.5.10 Numeric Maximum and Minimum 5159 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5160 // ACLE 6.5.9 Directed Rounding 5161 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5162 } 5163 5164 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5165 // is not defined for the M-profile. 5166 // NOTE that the default profile is assumed to be 'A' 5167 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5168 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5169 5170 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5171 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5172 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5173 // v7 and v8 architectures excluding v8-M Baseline. 5174 if (supportsThumb2()) 5175 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5176 else if (supportsThumb()) 5177 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5178 5179 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5180 // instruction set such as ARM or Thumb. 5181 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5182 5183 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5184 5185 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5186 if (!CPUProfile.empty()) 5187 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5188 5189 // ACLE 6.4.3 Unaligned access supported in hardware 5190 if (Unaligned) 5191 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5192 5193 // ACLE 6.4.4 LDREX/STREX 5194 if (LDREX) 5195 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5196 5197 // ACLE 6.4.5 CLZ 5198 if (ArchVersion == 5 || 5199 (ArchVersion == 6 && CPUProfile != "M") || 5200 ArchVersion > 6) 5201 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5202 5203 // ACLE 6.5.1 Hardware Floating Point 5204 if (HW_FP) 5205 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5206 5207 // ACLE predefines. 5208 Builder.defineMacro("__ARM_ACLE", "200"); 5209 5210 // FP16 support (we currently only support IEEE format). 5211 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5212 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5213 5214 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5215 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5216 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5217 5218 // Subtarget options. 5219 5220 // FIXME: It's more complicated than this and we don't really support 5221 // interworking. 5222 // Windows on ARM does not "support" interworking 5223 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5224 Builder.defineMacro("__THUMB_INTERWORK__"); 5225 5226 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5227 // Embedded targets on Darwin follow AAPCS, but not EABI. 5228 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5229 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5230 Builder.defineMacro("__ARM_EABI__"); 5231 Builder.defineMacro("__ARM_PCS", "1"); 5232 } 5233 5234 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5235 ABI == "aapcs16") 5236 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5237 5238 if (SoftFloat) 5239 Builder.defineMacro("__SOFTFP__"); 5240 5241 if (ArchKind == llvm::ARM::AK_XSCALE) 5242 Builder.defineMacro("__XSCALE__"); 5243 5244 if (isThumb()) { 5245 Builder.defineMacro("__THUMBEL__"); 5246 Builder.defineMacro("__thumb__"); 5247 if (supportsThumb2()) 5248 Builder.defineMacro("__thumb2__"); 5249 } 5250 5251 // ACLE 6.4.9 32-bit SIMD instructions 5252 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5253 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5254 5255 // ACLE 6.4.10 Hardware Integer Divide 5256 if (((HWDiv & HWDivThumb) && isThumb()) || 5257 ((HWDiv & HWDivARM) && !isThumb())) { 5258 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5259 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5260 } 5261 5262 // Note, this is always on in gcc, even though it doesn't make sense. 5263 Builder.defineMacro("__APCS_32__"); 5264 5265 if (FPUModeIsVFP((FPUMode) FPU)) { 5266 Builder.defineMacro("__VFP_FP__"); 5267 if (FPU & VFP2FPU) 5268 Builder.defineMacro("__ARM_VFPV2__"); 5269 if (FPU & VFP3FPU) 5270 Builder.defineMacro("__ARM_VFPV3__"); 5271 if (FPU & VFP4FPU) 5272 Builder.defineMacro("__ARM_VFPV4__"); 5273 } 5274 5275 // This only gets set when Neon instructions are actually available, unlike 5276 // the VFP define, hence the soft float and arch check. This is subtly 5277 // different from gcc, we follow the intent which was that it should be set 5278 // when Neon instructions are actually available. 5279 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5280 Builder.defineMacro("__ARM_NEON", "1"); 5281 Builder.defineMacro("__ARM_NEON__"); 5282 // current AArch32 NEON implementations do not support double-precision 5283 // floating-point even when it is present in VFP. 5284 Builder.defineMacro("__ARM_NEON_FP", 5285 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5286 } 5287 5288 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5289 Opts.ShortWChar ? "2" : "4"); 5290 5291 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5292 Opts.ShortEnums ? "1" : "4"); 5293 5294 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5295 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5296 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5297 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5298 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5299 } 5300 5301 // ACLE 6.4.7 DSP instructions 5302 if (DSP) { 5303 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5304 } 5305 5306 // ACLE 6.4.8 Saturation instructions 5307 bool SAT = false; 5308 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5309 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5310 SAT = true; 5311 } 5312 5313 // ACLE 6.4.6 Q (saturation) flag 5314 if (DSP || SAT) 5315 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5316 5317 if (Opts.UnsafeFPMath) 5318 Builder.defineMacro("__ARM_FP_FAST", "1"); 5319 5320 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5321 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5322 } 5323 5324 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5325 return llvm::makeArrayRef(BuiltinInfo, 5326 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5327 } 5328 bool isCLZForZeroUndef() const override { return false; } 5329 BuiltinVaListKind getBuiltinVaListKind() const override { 5330 return IsAAPCS 5331 ? AAPCSABIBuiltinVaList 5332 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5333 : TargetInfo::VoidPtrBuiltinVaList); 5334 } 5335 ArrayRef<const char *> getGCCRegNames() const override; 5336 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5337 bool validateAsmConstraint(const char *&Name, 5338 TargetInfo::ConstraintInfo &Info) const override { 5339 switch (*Name) { 5340 default: break; 5341 case 'l': // r0-r7 5342 case 'h': // r8-r15 5343 case 't': // VFP Floating point register single precision 5344 case 'w': // VFP Floating point register double precision 5345 Info.setAllowsRegister(); 5346 return true; 5347 case 'I': 5348 case 'J': 5349 case 'K': 5350 case 'L': 5351 case 'M': 5352 // FIXME 5353 return true; 5354 case 'Q': // A memory address that is a single base register. 5355 Info.setAllowsMemory(); 5356 return true; 5357 case 'U': // a memory reference... 5358 switch (Name[1]) { 5359 case 'q': // ...ARMV4 ldrsb 5360 case 'v': // ...VFP load/store (reg+constant offset) 5361 case 'y': // ...iWMMXt load/store 5362 case 't': // address valid for load/store opaque types wider 5363 // than 128-bits 5364 case 'n': // valid address for Neon doubleword vector load/store 5365 case 'm': // valid address for Neon element and structure load/store 5366 case 's': // valid address for non-offset loads/stores of quad-word 5367 // values in four ARM registers 5368 Info.setAllowsMemory(); 5369 Name++; 5370 return true; 5371 } 5372 } 5373 return false; 5374 } 5375 std::string convertConstraint(const char *&Constraint) const override { 5376 std::string R; 5377 switch (*Constraint) { 5378 case 'U': // Two-character constraint; add "^" hint for later parsing. 5379 R = std::string("^") + std::string(Constraint, 2); 5380 Constraint++; 5381 break; 5382 case 'p': // 'p' should be translated to 'r' by default. 5383 R = std::string("r"); 5384 break; 5385 default: 5386 return std::string(1, *Constraint); 5387 } 5388 return R; 5389 } 5390 bool 5391 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5392 std::string &SuggestedModifier) const override { 5393 bool isOutput = (Constraint[0] == '='); 5394 bool isInOut = (Constraint[0] == '+'); 5395 5396 // Strip off constraint modifiers. 5397 while (Constraint[0] == '=' || 5398 Constraint[0] == '+' || 5399 Constraint[0] == '&') 5400 Constraint = Constraint.substr(1); 5401 5402 switch (Constraint[0]) { 5403 default: break; 5404 case 'r': { 5405 switch (Modifier) { 5406 default: 5407 return (isInOut || isOutput || Size <= 64); 5408 case 'q': 5409 // A register of size 32 cannot fit a vector type. 5410 return false; 5411 } 5412 } 5413 } 5414 5415 return true; 5416 } 5417 const char *getClobbers() const override { 5418 // FIXME: Is this really right? 5419 return ""; 5420 } 5421 5422 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5423 switch (CC) { 5424 case CC_AAPCS: 5425 case CC_AAPCS_VFP: 5426 case CC_Swift: 5427 return CCCR_OK; 5428 default: 5429 return CCCR_Warning; 5430 } 5431 } 5432 5433 int getEHDataRegisterNumber(unsigned RegNo) const override { 5434 if (RegNo == 0) return 0; 5435 if (RegNo == 1) return 1; 5436 return -1; 5437 } 5438 5439 bool hasSjLjLowering() const override { 5440 return true; 5441 } 5442 }; 5443 5444 bool ARMTargetInfo::setFPMath(StringRef Name) { 5445 if (Name == "neon") { 5446 FPMath = FP_Neon; 5447 return true; 5448 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5449 Name == "vfp4") { 5450 FPMath = FP_VFP; 5451 return true; 5452 } 5453 return false; 5454 } 5455 5456 const char * const ARMTargetInfo::GCCRegNames[] = { 5457 // Integer registers 5458 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5459 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5460 5461 // Float registers 5462 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5463 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5464 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5465 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5466 5467 // Double registers 5468 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5469 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5470 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5471 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5472 5473 // Quad registers 5474 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5475 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5476 }; 5477 5478 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5479 return llvm::makeArrayRef(GCCRegNames); 5480 } 5481 5482 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5483 { { "a1" }, "r0" }, 5484 { { "a2" }, "r1" }, 5485 { { "a3" }, "r2" }, 5486 { { "a4" }, "r3" }, 5487 { { "v1" }, "r4" }, 5488 { { "v2" }, "r5" }, 5489 { { "v3" }, "r6" }, 5490 { { "v4" }, "r7" }, 5491 { { "v5" }, "r8" }, 5492 { { "v6", "rfp" }, "r9" }, 5493 { { "sl" }, "r10" }, 5494 { { "fp" }, "r11" }, 5495 { { "ip" }, "r12" }, 5496 { { "r13" }, "sp" }, 5497 { { "r14" }, "lr" }, 5498 { { "r15" }, "pc" }, 5499 // The S, D and Q registers overlap, but aren't really aliases; we 5500 // don't want to substitute one of these for a different-sized one. 5501 }; 5502 5503 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5504 return llvm::makeArrayRef(GCCRegAliases); 5505 } 5506 5507 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5508 #define BUILTIN(ID, TYPE, ATTRS) \ 5509 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5510 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5511 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5512 #include "clang/Basic/BuiltinsNEON.def" 5513 5514 #define BUILTIN(ID, TYPE, ATTRS) \ 5515 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5516 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5517 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5518 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5519 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5520 #include "clang/Basic/BuiltinsARM.def" 5521 }; 5522 5523 class ARMleTargetInfo : public ARMTargetInfo { 5524 public: 5525 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5526 : ARMTargetInfo(Triple, Opts) {} 5527 void getTargetDefines(const LangOptions &Opts, 5528 MacroBuilder &Builder) const override { 5529 Builder.defineMacro("__ARMEL__"); 5530 ARMTargetInfo::getTargetDefines(Opts, Builder); 5531 } 5532 }; 5533 5534 class ARMbeTargetInfo : public ARMTargetInfo { 5535 public: 5536 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5537 : ARMTargetInfo(Triple, Opts) {} 5538 void getTargetDefines(const LangOptions &Opts, 5539 MacroBuilder &Builder) const override { 5540 Builder.defineMacro("__ARMEB__"); 5541 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5542 ARMTargetInfo::getTargetDefines(Opts, Builder); 5543 } 5544 }; 5545 5546 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5547 const llvm::Triple Triple; 5548 public: 5549 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5550 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5551 WCharType = UnsignedShort; 5552 SizeType = UnsignedInt; 5553 } 5554 void getVisualStudioDefines(const LangOptions &Opts, 5555 MacroBuilder &Builder) const { 5556 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5557 5558 // FIXME: this is invalid for WindowsCE 5559 Builder.defineMacro("_M_ARM_NT", "1"); 5560 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5561 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5562 5563 assert((Triple.getArch() == llvm::Triple::arm || 5564 Triple.getArch() == llvm::Triple::thumb) && 5565 "invalid architecture for Windows ARM target info"); 5566 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5567 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5568 5569 // TODO map the complete set of values 5570 // 31: VFPv3 40: VFPv4 5571 Builder.defineMacro("_M_ARM_FP", "31"); 5572 } 5573 BuiltinVaListKind getBuiltinVaListKind() const override { 5574 return TargetInfo::CharPtrBuiltinVaList; 5575 } 5576 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5577 switch (CC) { 5578 case CC_X86StdCall: 5579 case CC_X86ThisCall: 5580 case CC_X86FastCall: 5581 case CC_X86VectorCall: 5582 return CCCR_Ignore; 5583 case CC_C: 5584 return CCCR_OK; 5585 default: 5586 return CCCR_Warning; 5587 } 5588 } 5589 }; 5590 5591 // Windows ARM + Itanium C++ ABI Target 5592 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5593 public: 5594 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5595 const TargetOptions &Opts) 5596 : WindowsARMTargetInfo(Triple, Opts) { 5597 TheCXXABI.set(TargetCXXABI::GenericARM); 5598 } 5599 5600 void getTargetDefines(const LangOptions &Opts, 5601 MacroBuilder &Builder) const override { 5602 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5603 5604 if (Opts.MSVCCompat) 5605 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5606 } 5607 }; 5608 5609 // Windows ARM, MS (C++) ABI 5610 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5611 public: 5612 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5613 const TargetOptions &Opts) 5614 : WindowsARMTargetInfo(Triple, Opts) { 5615 TheCXXABI.set(TargetCXXABI::Microsoft); 5616 } 5617 5618 void getTargetDefines(const LangOptions &Opts, 5619 MacroBuilder &Builder) const override { 5620 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5621 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5622 } 5623 }; 5624 5625 // ARM MinGW target 5626 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5627 public: 5628 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5629 : WindowsARMTargetInfo(Triple, Opts) { 5630 TheCXXABI.set(TargetCXXABI::GenericARM); 5631 } 5632 5633 void getTargetDefines(const LangOptions &Opts, 5634 MacroBuilder &Builder) const override { 5635 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5636 DefineStd(Builder, "WIN32", Opts); 5637 DefineStd(Builder, "WINNT", Opts); 5638 Builder.defineMacro("_ARM_"); 5639 addMinGWDefines(Opts, Builder); 5640 } 5641 }; 5642 5643 // ARM Cygwin target 5644 class CygwinARMTargetInfo : public ARMleTargetInfo { 5645 public: 5646 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5647 : ARMleTargetInfo(Triple, Opts) { 5648 TLSSupported = false; 5649 WCharType = UnsignedShort; 5650 DoubleAlign = LongLongAlign = 64; 5651 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5652 } 5653 void getTargetDefines(const LangOptions &Opts, 5654 MacroBuilder &Builder) const override { 5655 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5656 Builder.defineMacro("_ARM_"); 5657 Builder.defineMacro("__CYGWIN__"); 5658 Builder.defineMacro("__CYGWIN32__"); 5659 DefineStd(Builder, "unix", Opts); 5660 if (Opts.CPlusPlus) 5661 Builder.defineMacro("_GNU_SOURCE"); 5662 } 5663 }; 5664 5665 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 5666 protected: 5667 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5668 MacroBuilder &Builder) const override { 5669 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5670 } 5671 5672 public: 5673 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5674 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 5675 HasAlignMac68kSupport = true; 5676 // iOS always has 64-bit atomic instructions. 5677 // FIXME: This should be based off of the target features in 5678 // ARMleTargetInfo. 5679 MaxAtomicInlineWidth = 64; 5680 5681 if (Triple.isWatchABI()) { 5682 // Darwin on iOS uses a variant of the ARM C++ ABI. 5683 TheCXXABI.set(TargetCXXABI::WatchOS); 5684 5685 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5686 // size_t is long, it's a bit weird for it to be int. 5687 PtrDiffType = SignedLong; 5688 5689 // BOOL should be a real boolean on the new ABI 5690 UseSignedCharForObjCBool = false; 5691 } else 5692 TheCXXABI.set(TargetCXXABI::iOS); 5693 } 5694 }; 5695 5696 class AArch64TargetInfo : public TargetInfo { 5697 virtual void setDataLayout() = 0; 5698 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5699 static const char *const GCCRegNames[]; 5700 5701 enum FPUModeEnum { 5702 FPUMode, 5703 NeonMode 5704 }; 5705 5706 unsigned FPU; 5707 unsigned CRC; 5708 unsigned Crypto; 5709 unsigned Unaligned; 5710 unsigned V8_1A; 5711 5712 static const Builtin::Info BuiltinInfo[]; 5713 5714 std::string ABI; 5715 5716 public: 5717 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5718 : TargetInfo(Triple), ABI("aapcs") { 5719 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5720 WCharType = SignedInt; 5721 5722 // NetBSD apparently prefers consistency across ARM targets to consistency 5723 // across 64-bit targets. 5724 Int64Type = SignedLongLong; 5725 IntMaxType = SignedLongLong; 5726 } else { 5727 WCharType = UnsignedInt; 5728 Int64Type = SignedLong; 5729 IntMaxType = SignedLong; 5730 } 5731 5732 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5733 MaxVectorAlign = 128; 5734 MaxAtomicInlineWidth = 128; 5735 MaxAtomicPromoteWidth = 128; 5736 5737 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5738 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5739 5740 // {} in inline assembly are neon specifiers, not assembly variant 5741 // specifiers. 5742 NoAsmVariants = true; 5743 5744 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5745 // contributes to the alignment of the containing aggregate in the same way 5746 // a plain (non bit-field) member of that type would, without exception for 5747 // zero-sized or anonymous bit-fields." 5748 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5749 UseZeroLengthBitfieldAlignment = true; 5750 5751 // AArch64 targets default to using the ARM C++ ABI. 5752 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5753 5754 if (Triple.getOS() == llvm::Triple::Linux || 5755 Triple.getOS() == llvm::Triple::UnknownOS) 5756 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 5757 } 5758 5759 StringRef getABI() const override { return ABI; } 5760 bool setABI(const std::string &Name) override { 5761 if (Name != "aapcs" && Name != "darwinpcs") 5762 return false; 5763 5764 ABI = Name; 5765 return true; 5766 } 5767 5768 bool setCPU(const std::string &Name) override { 5769 return Name == "generic" || 5770 llvm::AArch64::parseCPUArch(Name) != 5771 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 5772 } 5773 5774 void getTargetDefines(const LangOptions &Opts, 5775 MacroBuilder &Builder) const override { 5776 // Target identification. 5777 Builder.defineMacro("__aarch64__"); 5778 5779 // Target properties. 5780 Builder.defineMacro("_LP64"); 5781 Builder.defineMacro("__LP64__"); 5782 5783 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5784 Builder.defineMacro("__ARM_ACLE", "200"); 5785 Builder.defineMacro("__ARM_ARCH", "8"); 5786 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5787 5788 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5789 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5790 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5791 5792 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5793 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5794 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5795 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5796 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5797 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5798 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5799 5800 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5801 5802 // 0xe implies support for half, single and double precision operations. 5803 Builder.defineMacro("__ARM_FP", "0xE"); 5804 5805 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5806 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5807 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5808 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5809 5810 if (Opts.UnsafeFPMath) 5811 Builder.defineMacro("__ARM_FP_FAST", "1"); 5812 5813 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5814 5815 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5816 Opts.ShortEnums ? "1" : "4"); 5817 5818 if (FPU == NeonMode) { 5819 Builder.defineMacro("__ARM_NEON", "1"); 5820 // 64-bit NEON supports half, single and double precision operations. 5821 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5822 } 5823 5824 if (CRC) 5825 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5826 5827 if (Crypto) 5828 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5829 5830 if (Unaligned) 5831 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5832 5833 if (V8_1A) 5834 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5835 5836 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5837 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5838 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5839 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5840 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5841 } 5842 5843 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5844 return llvm::makeArrayRef(BuiltinInfo, 5845 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5846 } 5847 5848 bool hasFeature(StringRef Feature) const override { 5849 return Feature == "aarch64" || 5850 Feature == "arm64" || 5851 Feature == "arm" || 5852 (Feature == "neon" && FPU == NeonMode); 5853 } 5854 5855 bool handleTargetFeatures(std::vector<std::string> &Features, 5856 DiagnosticsEngine &Diags) override { 5857 FPU = FPUMode; 5858 CRC = 0; 5859 Crypto = 0; 5860 Unaligned = 1; 5861 V8_1A = 0; 5862 5863 for (const auto &Feature : Features) { 5864 if (Feature == "+neon") 5865 FPU = NeonMode; 5866 if (Feature == "+crc") 5867 CRC = 1; 5868 if (Feature == "+crypto") 5869 Crypto = 1; 5870 if (Feature == "+strict-align") 5871 Unaligned = 0; 5872 if (Feature == "+v8.1a") 5873 V8_1A = 1; 5874 } 5875 5876 setDataLayout(); 5877 5878 return true; 5879 } 5880 5881 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5882 switch (CC) { 5883 case CC_C: 5884 case CC_Swift: 5885 case CC_PreserveMost: 5886 case CC_PreserveAll: 5887 return CCCR_OK; 5888 default: 5889 return CCCR_Warning; 5890 } 5891 } 5892 5893 bool isCLZForZeroUndef() const override { return false; } 5894 5895 BuiltinVaListKind getBuiltinVaListKind() const override { 5896 return TargetInfo::AArch64ABIBuiltinVaList; 5897 } 5898 5899 ArrayRef<const char *> getGCCRegNames() const override; 5900 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5901 5902 bool validateAsmConstraint(const char *&Name, 5903 TargetInfo::ConstraintInfo &Info) const override { 5904 switch (*Name) { 5905 default: 5906 return false; 5907 case 'w': // Floating point and SIMD registers (V0-V31) 5908 Info.setAllowsRegister(); 5909 return true; 5910 case 'I': // Constant that can be used with an ADD instruction 5911 case 'J': // Constant that can be used with a SUB instruction 5912 case 'K': // Constant that can be used with a 32-bit logical instruction 5913 case 'L': // Constant that can be used with a 64-bit logical instruction 5914 case 'M': // Constant that can be used as a 32-bit MOV immediate 5915 case 'N': // Constant that can be used as a 64-bit MOV immediate 5916 case 'Y': // Floating point constant zero 5917 case 'Z': // Integer constant zero 5918 return true; 5919 case 'Q': // A memory reference with base register and no offset 5920 Info.setAllowsMemory(); 5921 return true; 5922 case 'S': // A symbolic address 5923 Info.setAllowsRegister(); 5924 return true; 5925 case 'U': 5926 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5927 // Utf: A memory address suitable for ldp/stp in TF mode. 5928 // Usa: An absolute symbolic address. 5929 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5930 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5931 case 'z': // Zero register, wzr or xzr 5932 Info.setAllowsRegister(); 5933 return true; 5934 case 'x': // Floating point and SIMD registers (V0-V15) 5935 Info.setAllowsRegister(); 5936 return true; 5937 } 5938 return false; 5939 } 5940 5941 bool 5942 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5943 std::string &SuggestedModifier) const override { 5944 // Strip off constraint modifiers. 5945 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5946 Constraint = Constraint.substr(1); 5947 5948 switch (Constraint[0]) { 5949 default: 5950 return true; 5951 case 'z': 5952 case 'r': { 5953 switch (Modifier) { 5954 case 'x': 5955 case 'w': 5956 // For now assume that the person knows what they're 5957 // doing with the modifier. 5958 return true; 5959 default: 5960 // By default an 'r' constraint will be in the 'x' 5961 // registers. 5962 if (Size == 64) 5963 return true; 5964 5965 SuggestedModifier = "w"; 5966 return false; 5967 } 5968 } 5969 } 5970 } 5971 5972 const char *getClobbers() const override { return ""; } 5973 5974 int getEHDataRegisterNumber(unsigned RegNo) const override { 5975 if (RegNo == 0) 5976 return 0; 5977 if (RegNo == 1) 5978 return 1; 5979 return -1; 5980 } 5981 }; 5982 5983 const char *const AArch64TargetInfo::GCCRegNames[] = { 5984 // 32-bit Integer registers 5985 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5986 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5987 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5988 5989 // 64-bit Integer registers 5990 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5991 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5992 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5993 5994 // 32-bit floating point regsisters 5995 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5996 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5997 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5998 5999 // 64-bit floating point regsisters 6000 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 6001 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 6002 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6003 6004 // Vector registers 6005 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6006 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6007 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6008 }; 6009 6010 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6011 return llvm::makeArrayRef(GCCRegNames); 6012 } 6013 6014 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6015 { { "w31" }, "wsp" }, 6016 { { "x29" }, "fp" }, 6017 { { "x30" }, "lr" }, 6018 { { "x31" }, "sp" }, 6019 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6020 // don't want to substitute one of these for a different-sized one. 6021 }; 6022 6023 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6024 return llvm::makeArrayRef(GCCRegAliases); 6025 } 6026 6027 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6028 #define BUILTIN(ID, TYPE, ATTRS) \ 6029 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6030 #include "clang/Basic/BuiltinsNEON.def" 6031 6032 #define BUILTIN(ID, TYPE, ATTRS) \ 6033 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6034 #include "clang/Basic/BuiltinsAArch64.def" 6035 }; 6036 6037 class AArch64leTargetInfo : public AArch64TargetInfo { 6038 void setDataLayout() override { 6039 if (getTriple().isOSBinFormatMachO()) 6040 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6041 else 6042 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6043 } 6044 6045 public: 6046 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6047 : AArch64TargetInfo(Triple, Opts) { 6048 } 6049 void getTargetDefines(const LangOptions &Opts, 6050 MacroBuilder &Builder) const override { 6051 Builder.defineMacro("__AARCH64EL__"); 6052 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6053 } 6054 }; 6055 6056 class AArch64beTargetInfo : public AArch64TargetInfo { 6057 void setDataLayout() override { 6058 assert(!getTriple().isOSBinFormatMachO()); 6059 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6060 } 6061 6062 public: 6063 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6064 : AArch64TargetInfo(Triple, Opts) {} 6065 void getTargetDefines(const LangOptions &Opts, 6066 MacroBuilder &Builder) const override { 6067 Builder.defineMacro("__AARCH64EB__"); 6068 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6069 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6070 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6071 } 6072 }; 6073 6074 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6075 protected: 6076 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6077 MacroBuilder &Builder) const override { 6078 Builder.defineMacro("__AARCH64_SIMD__"); 6079 Builder.defineMacro("__ARM64_ARCH_8__"); 6080 Builder.defineMacro("__ARM_NEON__"); 6081 Builder.defineMacro("__LITTLE_ENDIAN__"); 6082 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6083 Builder.defineMacro("__arm64", "1"); 6084 Builder.defineMacro("__arm64__", "1"); 6085 6086 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6087 } 6088 6089 public: 6090 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6091 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6092 Int64Type = SignedLongLong; 6093 WCharType = SignedInt; 6094 UseSignedCharForObjCBool = false; 6095 6096 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6097 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6098 6099 TheCXXABI.set(TargetCXXABI::iOS64); 6100 } 6101 6102 BuiltinVaListKind getBuiltinVaListKind() const override { 6103 return TargetInfo::CharPtrBuiltinVaList; 6104 } 6105 }; 6106 6107 // Hexagon abstract base class 6108 class HexagonTargetInfo : public TargetInfo { 6109 static const Builtin::Info BuiltinInfo[]; 6110 static const char * const GCCRegNames[]; 6111 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6112 std::string CPU; 6113 bool HasHVX, HasHVXDouble; 6114 bool UseLongCalls; 6115 6116 public: 6117 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6118 : TargetInfo(Triple) { 6119 // Specify the vector alignment explicitly. For v512x1, the calculated 6120 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6121 // the required minimum of 64 bytes. 6122 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6123 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6124 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6125 SizeType = UnsignedInt; 6126 PtrDiffType = SignedInt; 6127 IntPtrType = SignedInt; 6128 6129 // {} in inline assembly are packet specifiers, not assembly variant 6130 // specifiers. 6131 NoAsmVariants = true; 6132 6133 LargeArrayMinWidth = 64; 6134 LargeArrayAlign = 64; 6135 UseBitFieldTypeAlignment = true; 6136 ZeroLengthBitfieldBoundary = 32; 6137 HasHVX = HasHVXDouble = false; 6138 UseLongCalls = false; 6139 } 6140 6141 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6142 return llvm::makeArrayRef(BuiltinInfo, 6143 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6144 } 6145 6146 bool validateAsmConstraint(const char *&Name, 6147 TargetInfo::ConstraintInfo &Info) const override { 6148 switch (*Name) { 6149 case 'v': 6150 case 'q': 6151 if (HasHVX) { 6152 Info.setAllowsRegister(); 6153 return true; 6154 } 6155 break; 6156 case 's': 6157 // Relocatable constant. 6158 return true; 6159 } 6160 return false; 6161 } 6162 6163 void getTargetDefines(const LangOptions &Opts, 6164 MacroBuilder &Builder) const override; 6165 6166 bool isCLZForZeroUndef() const override { return false; } 6167 6168 bool hasFeature(StringRef Feature) const override { 6169 return llvm::StringSwitch<bool>(Feature) 6170 .Case("hexagon", true) 6171 .Case("hvx", HasHVX) 6172 .Case("hvx-double", HasHVXDouble) 6173 .Case("long-calls", UseLongCalls) 6174 .Default(false); 6175 } 6176 6177 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6178 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6179 const override; 6180 6181 bool handleTargetFeatures(std::vector<std::string> &Features, 6182 DiagnosticsEngine &Diags) override; 6183 6184 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6185 bool Enabled) const override; 6186 6187 BuiltinVaListKind getBuiltinVaListKind() const override { 6188 return TargetInfo::CharPtrBuiltinVaList; 6189 } 6190 ArrayRef<const char *> getGCCRegNames() const override; 6191 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6192 const char *getClobbers() const override { 6193 return ""; 6194 } 6195 6196 static const char *getHexagonCPUSuffix(StringRef Name) { 6197 return llvm::StringSwitch<const char*>(Name) 6198 .Case("hexagonv4", "4") 6199 .Case("hexagonv5", "5") 6200 .Case("hexagonv55", "55") 6201 .Case("hexagonv60", "60") 6202 .Default(nullptr); 6203 } 6204 6205 bool setCPU(const std::string &Name) override { 6206 if (!getHexagonCPUSuffix(Name)) 6207 return false; 6208 CPU = Name; 6209 return true; 6210 } 6211 6212 int getEHDataRegisterNumber(unsigned RegNo) const override { 6213 return RegNo < 2 ? RegNo : -1; 6214 } 6215 }; 6216 6217 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6218 MacroBuilder &Builder) const { 6219 Builder.defineMacro("__qdsp6__", "1"); 6220 Builder.defineMacro("__hexagon__", "1"); 6221 6222 if (CPU == "hexagonv4") { 6223 Builder.defineMacro("__HEXAGON_V4__"); 6224 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6225 if (Opts.HexagonQdsp6Compat) { 6226 Builder.defineMacro("__QDSP6_V4__"); 6227 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6228 } 6229 } else if (CPU == "hexagonv5") { 6230 Builder.defineMacro("__HEXAGON_V5__"); 6231 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6232 if(Opts.HexagonQdsp6Compat) { 6233 Builder.defineMacro("__QDSP6_V5__"); 6234 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6235 } 6236 } else if (CPU == "hexagonv55") { 6237 Builder.defineMacro("__HEXAGON_V55__"); 6238 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6239 Builder.defineMacro("__QDSP6_V55__"); 6240 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6241 } else if (CPU == "hexagonv60") { 6242 Builder.defineMacro("__HEXAGON_V60__"); 6243 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6244 Builder.defineMacro("__QDSP6_V60__"); 6245 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6246 } 6247 6248 if (hasFeature("hvx")) { 6249 Builder.defineMacro("__HVX__"); 6250 if (hasFeature("hvx-double")) 6251 Builder.defineMacro("__HVXDBL__"); 6252 } 6253 } 6254 6255 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6256 DiagnosticsEngine &Diags, StringRef CPU, 6257 const std::vector<std::string> &FeaturesVec) const { 6258 // Default for v60: -hvx, -hvx-double. 6259 Features["hvx"] = false; 6260 Features["hvx-double"] = false; 6261 Features["long-calls"] = false; 6262 6263 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6264 } 6265 6266 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6267 DiagnosticsEngine &Diags) { 6268 for (auto &F : Features) { 6269 if (F == "+hvx") 6270 HasHVX = true; 6271 else if (F == "-hvx") 6272 HasHVX = HasHVXDouble = false; 6273 else if (F == "+hvx-double") 6274 HasHVX = HasHVXDouble = true; 6275 else if (F == "-hvx-double") 6276 HasHVXDouble = false; 6277 6278 if (F == "+long-calls") 6279 UseLongCalls = true; 6280 else if (F == "-long-calls") 6281 UseLongCalls = false; 6282 } 6283 return true; 6284 } 6285 6286 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 6287 StringRef Name, bool Enabled) const { 6288 if (Enabled) { 6289 if (Name == "hvx-double") 6290 Features["hvx"] = true; 6291 } else { 6292 if (Name == "hvx") 6293 Features["hvx-double"] = false; 6294 } 6295 Features[Name] = Enabled; 6296 } 6297 6298 const char *const HexagonTargetInfo::GCCRegNames[] = { 6299 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6300 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6301 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6302 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6303 "p0", "p1", "p2", "p3", 6304 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6305 }; 6306 6307 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6308 return llvm::makeArrayRef(GCCRegNames); 6309 } 6310 6311 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6312 { { "sp" }, "r29" }, 6313 { { "fp" }, "r30" }, 6314 { { "lr" }, "r31" }, 6315 }; 6316 6317 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6318 return llvm::makeArrayRef(GCCRegAliases); 6319 } 6320 6321 6322 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6323 #define BUILTIN(ID, TYPE, ATTRS) \ 6324 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6325 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6326 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6327 #include "clang/Basic/BuiltinsHexagon.def" 6328 }; 6329 6330 class LanaiTargetInfo : public TargetInfo { 6331 // Class for Lanai (32-bit). 6332 // The CPU profiles supported by the Lanai backend 6333 enum CPUKind { 6334 CK_NONE, 6335 CK_V11, 6336 } CPU; 6337 6338 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6339 static const char *const GCCRegNames[]; 6340 6341 public: 6342 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6343 : TargetInfo(Triple) { 6344 // Description string has to be kept in sync with backend. 6345 resetDataLayout("E" // Big endian 6346 "-m:e" // ELF name manging 6347 "-p:32:32" // 32 bit pointers, 32 bit aligned 6348 "-i64:64" // 64 bit integers, 64 bit aligned 6349 "-a:0:32" // 32 bit alignment of objects of aggregate type 6350 "-n32" // 32 bit native integer width 6351 "-S64" // 64 bit natural stack alignment 6352 ); 6353 6354 // Setting RegParmMax equal to what mregparm was set to in the old 6355 // toolchain 6356 RegParmMax = 4; 6357 6358 // Set the default CPU to V11 6359 CPU = CK_V11; 6360 6361 // Temporary approach to make everything at least word-aligned and allow for 6362 // safely casting between pointers with different alignment requirements. 6363 // TODO: Remove this when there are no more cast align warnings on the 6364 // firmware. 6365 MinGlobalAlign = 32; 6366 } 6367 6368 void getTargetDefines(const LangOptions &Opts, 6369 MacroBuilder &Builder) const override { 6370 // Define __lanai__ when building for target lanai. 6371 Builder.defineMacro("__lanai__"); 6372 6373 // Set define for the CPU specified. 6374 switch (CPU) { 6375 case CK_V11: 6376 Builder.defineMacro("__LANAI_V11__"); 6377 break; 6378 case CK_NONE: 6379 llvm_unreachable("Unhandled target CPU"); 6380 } 6381 } 6382 6383 bool setCPU(const std::string &Name) override { 6384 CPU = llvm::StringSwitch<CPUKind>(Name) 6385 .Case("v11", CK_V11) 6386 .Default(CK_NONE); 6387 6388 return CPU != CK_NONE; 6389 } 6390 6391 bool hasFeature(StringRef Feature) const override { 6392 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6393 } 6394 6395 ArrayRef<const char *> getGCCRegNames() const override; 6396 6397 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6398 6399 BuiltinVaListKind getBuiltinVaListKind() const override { 6400 return TargetInfo::VoidPtrBuiltinVaList; 6401 } 6402 6403 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6404 6405 bool validateAsmConstraint(const char *&Name, 6406 TargetInfo::ConstraintInfo &info) const override { 6407 return false; 6408 } 6409 6410 const char *getClobbers() const override { return ""; } 6411 }; 6412 6413 const char *const LanaiTargetInfo::GCCRegNames[] = { 6414 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6415 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6416 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6417 6418 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6419 return llvm::makeArrayRef(GCCRegNames); 6420 } 6421 6422 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6423 {{"pc"}, "r2"}, 6424 {{"sp"}, "r4"}, 6425 {{"fp"}, "r5"}, 6426 {{"rv"}, "r8"}, 6427 {{"rr1"}, "r10"}, 6428 {{"rr2"}, "r11"}, 6429 {{"rca"}, "r15"}, 6430 }; 6431 6432 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6433 return llvm::makeArrayRef(GCCRegAliases); 6434 } 6435 6436 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6437 class SparcTargetInfo : public TargetInfo { 6438 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6439 static const char * const GCCRegNames[]; 6440 bool SoftFloat; 6441 public: 6442 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6443 : TargetInfo(Triple), SoftFloat(false) {} 6444 6445 int getEHDataRegisterNumber(unsigned RegNo) const override { 6446 if (RegNo == 0) return 24; 6447 if (RegNo == 1) return 25; 6448 return -1; 6449 } 6450 6451 bool handleTargetFeatures(std::vector<std::string> &Features, 6452 DiagnosticsEngine &Diags) override { 6453 // Check if software floating point is enabled 6454 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6455 if (Feature != Features.end()) { 6456 SoftFloat = true; 6457 } 6458 return true; 6459 } 6460 void getTargetDefines(const LangOptions &Opts, 6461 MacroBuilder &Builder) const override { 6462 DefineStd(Builder, "sparc", Opts); 6463 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6464 6465 if (SoftFloat) 6466 Builder.defineMacro("SOFT_FLOAT", "1"); 6467 } 6468 6469 bool hasFeature(StringRef Feature) const override { 6470 return llvm::StringSwitch<bool>(Feature) 6471 .Case("softfloat", SoftFloat) 6472 .Case("sparc", true) 6473 .Default(false); 6474 } 6475 6476 bool hasSjLjLowering() const override { 6477 return true; 6478 } 6479 6480 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6481 // FIXME: Implement! 6482 return None; 6483 } 6484 BuiltinVaListKind getBuiltinVaListKind() const override { 6485 return TargetInfo::VoidPtrBuiltinVaList; 6486 } 6487 ArrayRef<const char *> getGCCRegNames() const override; 6488 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6489 bool validateAsmConstraint(const char *&Name, 6490 TargetInfo::ConstraintInfo &info) const override { 6491 // FIXME: Implement! 6492 switch (*Name) { 6493 case 'I': // Signed 13-bit constant 6494 case 'J': // Zero 6495 case 'K': // 32-bit constant with the low 12 bits clear 6496 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6497 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6498 case 'N': // Same as 'K' but zext (required for SIMode) 6499 case 'O': // The constant 4096 6500 return true; 6501 } 6502 return false; 6503 } 6504 const char *getClobbers() const override { 6505 // FIXME: Implement! 6506 return ""; 6507 } 6508 6509 // No Sparc V7 for now, the backend doesn't support it anyway. 6510 enum CPUKind { 6511 CK_GENERIC, 6512 CK_V8, 6513 CK_SUPERSPARC, 6514 CK_SPARCLITE, 6515 CK_F934, 6516 CK_HYPERSPARC, 6517 CK_SPARCLITE86X, 6518 CK_SPARCLET, 6519 CK_TSC701, 6520 CK_V9, 6521 CK_ULTRASPARC, 6522 CK_ULTRASPARC3, 6523 CK_NIAGARA, 6524 CK_NIAGARA2, 6525 CK_NIAGARA3, 6526 CK_NIAGARA4, 6527 CK_MYRIAD2100, 6528 CK_MYRIAD2150, 6529 CK_MYRIAD2450, 6530 CK_LEON2, 6531 CK_LEON2_AT697E, 6532 CK_LEON2_AT697F, 6533 CK_LEON3, 6534 CK_LEON3_UT699, 6535 CK_LEON3_GR712RC, 6536 CK_LEON4, 6537 CK_LEON4_GR740 6538 } CPU = CK_GENERIC; 6539 6540 enum CPUGeneration { 6541 CG_V8, 6542 CG_V9, 6543 }; 6544 6545 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6546 switch (Kind) { 6547 case CK_GENERIC: 6548 case CK_V8: 6549 case CK_SUPERSPARC: 6550 case CK_SPARCLITE: 6551 case CK_F934: 6552 case CK_HYPERSPARC: 6553 case CK_SPARCLITE86X: 6554 case CK_SPARCLET: 6555 case CK_TSC701: 6556 case CK_MYRIAD2100: 6557 case CK_MYRIAD2150: 6558 case CK_MYRIAD2450: 6559 case CK_LEON2: 6560 case CK_LEON2_AT697E: 6561 case CK_LEON2_AT697F: 6562 case CK_LEON3: 6563 case CK_LEON3_UT699: 6564 case CK_LEON3_GR712RC: 6565 case CK_LEON4: 6566 case CK_LEON4_GR740: 6567 return CG_V8; 6568 case CK_V9: 6569 case CK_ULTRASPARC: 6570 case CK_ULTRASPARC3: 6571 case CK_NIAGARA: 6572 case CK_NIAGARA2: 6573 case CK_NIAGARA3: 6574 case CK_NIAGARA4: 6575 return CG_V9; 6576 } 6577 llvm_unreachable("Unexpected CPU kind"); 6578 } 6579 6580 CPUKind getCPUKind(StringRef Name) const { 6581 return llvm::StringSwitch<CPUKind>(Name) 6582 .Case("v8", CK_V8) 6583 .Case("supersparc", CK_SUPERSPARC) 6584 .Case("sparclite", CK_SPARCLITE) 6585 .Case("f934", CK_F934) 6586 .Case("hypersparc", CK_HYPERSPARC) 6587 .Case("sparclite86x", CK_SPARCLITE86X) 6588 .Case("sparclet", CK_SPARCLET) 6589 .Case("tsc701", CK_TSC701) 6590 .Case("v9", CK_V9) 6591 .Case("ultrasparc", CK_ULTRASPARC) 6592 .Case("ultrasparc3", CK_ULTRASPARC3) 6593 .Case("niagara", CK_NIAGARA) 6594 .Case("niagara2", CK_NIAGARA2) 6595 .Case("niagara3", CK_NIAGARA3) 6596 .Case("niagara4", CK_NIAGARA4) 6597 .Case("ma2100", CK_MYRIAD2100) 6598 .Case("ma2150", CK_MYRIAD2150) 6599 .Case("ma2450", CK_MYRIAD2450) 6600 // FIXME: the myriad2[.n] spellings are obsolete, 6601 // but a grace period is needed to allow updating dependent builds. 6602 .Case("myriad2", CK_MYRIAD2100) 6603 .Case("myriad2.1", CK_MYRIAD2100) 6604 .Case("myriad2.2", CK_MYRIAD2150) 6605 .Case("leon2", CK_LEON2) 6606 .Case("at697e", CK_LEON2_AT697E) 6607 .Case("at697f", CK_LEON2_AT697F) 6608 .Case("leon3", CK_LEON3) 6609 .Case("ut699", CK_LEON3_UT699) 6610 .Case("gr712rc", CK_LEON3_GR712RC) 6611 .Case("leon4", CK_LEON4) 6612 .Case("gr740", CK_LEON4_GR740) 6613 .Default(CK_GENERIC); 6614 } 6615 6616 bool setCPU(const std::string &Name) override { 6617 CPU = getCPUKind(Name); 6618 return CPU != CK_GENERIC; 6619 } 6620 }; 6621 6622 const char * const SparcTargetInfo::GCCRegNames[] = { 6623 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6624 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6625 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6626 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6627 }; 6628 6629 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6630 return llvm::makeArrayRef(GCCRegNames); 6631 } 6632 6633 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6634 { { "g0" }, "r0" }, 6635 { { "g1" }, "r1" }, 6636 { { "g2" }, "r2" }, 6637 { { "g3" }, "r3" }, 6638 { { "g4" }, "r4" }, 6639 { { "g5" }, "r5" }, 6640 { { "g6" }, "r6" }, 6641 { { "g7" }, "r7" }, 6642 { { "o0" }, "r8" }, 6643 { { "o1" }, "r9" }, 6644 { { "o2" }, "r10" }, 6645 { { "o3" }, "r11" }, 6646 { { "o4" }, "r12" }, 6647 { { "o5" }, "r13" }, 6648 { { "o6", "sp" }, "r14" }, 6649 { { "o7" }, "r15" }, 6650 { { "l0" }, "r16" }, 6651 { { "l1" }, "r17" }, 6652 { { "l2" }, "r18" }, 6653 { { "l3" }, "r19" }, 6654 { { "l4" }, "r20" }, 6655 { { "l5" }, "r21" }, 6656 { { "l6" }, "r22" }, 6657 { { "l7" }, "r23" }, 6658 { { "i0" }, "r24" }, 6659 { { "i1" }, "r25" }, 6660 { { "i2" }, "r26" }, 6661 { { "i3" }, "r27" }, 6662 { { "i4" }, "r28" }, 6663 { { "i5" }, "r29" }, 6664 { { "i6", "fp" }, "r30" }, 6665 { { "i7" }, "r31" }, 6666 }; 6667 6668 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6669 return llvm::makeArrayRef(GCCRegAliases); 6670 } 6671 6672 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6673 class SparcV8TargetInfo : public SparcTargetInfo { 6674 public: 6675 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6676 : SparcTargetInfo(Triple, Opts) { 6677 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6678 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6679 switch (getTriple().getOS()) { 6680 default: 6681 SizeType = UnsignedInt; 6682 IntPtrType = SignedInt; 6683 PtrDiffType = SignedInt; 6684 break; 6685 case llvm::Triple::NetBSD: 6686 case llvm::Triple::OpenBSD: 6687 SizeType = UnsignedLong; 6688 IntPtrType = SignedLong; 6689 PtrDiffType = SignedLong; 6690 break; 6691 } 6692 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6693 } 6694 6695 void getTargetDefines(const LangOptions &Opts, 6696 MacroBuilder &Builder) const override { 6697 SparcTargetInfo::getTargetDefines(Opts, Builder); 6698 switch (getCPUGeneration(CPU)) { 6699 case CG_V8: 6700 Builder.defineMacro("__sparcv8"); 6701 if (getTriple().getOS() != llvm::Triple::Solaris) 6702 Builder.defineMacro("__sparcv8__"); 6703 break; 6704 case CG_V9: 6705 Builder.defineMacro("__sparcv9"); 6706 if (getTriple().getOS() != llvm::Triple::Solaris) { 6707 Builder.defineMacro("__sparcv9__"); 6708 Builder.defineMacro("__sparc_v9__"); 6709 } 6710 break; 6711 } 6712 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6713 std::string MyriadArchValue, Myriad2Value; 6714 Builder.defineMacro("__sparc_v8__"); 6715 Builder.defineMacro("__leon__"); 6716 switch (CPU) { 6717 case CK_MYRIAD2150: 6718 MyriadArchValue = "__ma2150"; 6719 Myriad2Value = "2"; 6720 break; 6721 case CK_MYRIAD2450: 6722 MyriadArchValue = "__ma2450"; 6723 Myriad2Value = "2"; 6724 break; 6725 default: 6726 MyriadArchValue = "__ma2100"; 6727 Myriad2Value = "1"; 6728 break; 6729 } 6730 Builder.defineMacro(MyriadArchValue, "1"); 6731 Builder.defineMacro(MyriadArchValue+"__", "1"); 6732 Builder.defineMacro("__myriad2__", Myriad2Value); 6733 Builder.defineMacro("__myriad2", Myriad2Value); 6734 } 6735 } 6736 6737 bool hasSjLjLowering() const override { 6738 return true; 6739 } 6740 }; 6741 6742 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6743 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6744 public: 6745 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6746 : SparcV8TargetInfo(Triple, Opts) { 6747 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6748 } 6749 }; 6750 6751 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6752 class SparcV9TargetInfo : public SparcTargetInfo { 6753 public: 6754 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6755 : SparcTargetInfo(Triple, Opts) { 6756 // FIXME: Support Sparc quad-precision long double? 6757 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6758 // This is an LP64 platform. 6759 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6760 6761 // OpenBSD uses long long for int64_t and intmax_t. 6762 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6763 IntMaxType = SignedLongLong; 6764 else 6765 IntMaxType = SignedLong; 6766 Int64Type = IntMaxType; 6767 6768 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6769 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6770 LongDoubleWidth = 128; 6771 LongDoubleAlign = 128; 6772 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6773 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6774 } 6775 6776 void getTargetDefines(const LangOptions &Opts, 6777 MacroBuilder &Builder) const override { 6778 SparcTargetInfo::getTargetDefines(Opts, Builder); 6779 Builder.defineMacro("__sparcv9"); 6780 Builder.defineMacro("__arch64__"); 6781 // Solaris doesn't need these variants, but the BSDs do. 6782 if (getTriple().getOS() != llvm::Triple::Solaris) { 6783 Builder.defineMacro("__sparc64__"); 6784 Builder.defineMacro("__sparc_v9__"); 6785 Builder.defineMacro("__sparcv9__"); 6786 } 6787 } 6788 6789 bool setCPU(const std::string &Name) override { 6790 if (!SparcTargetInfo::setCPU(Name)) 6791 return false; 6792 return getCPUGeneration(CPU) == CG_V9; 6793 } 6794 }; 6795 6796 class SystemZTargetInfo : public TargetInfo { 6797 static const Builtin::Info BuiltinInfo[]; 6798 static const char *const GCCRegNames[]; 6799 std::string CPU; 6800 bool HasTransactionalExecution; 6801 bool HasVector; 6802 6803 public: 6804 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6805 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6806 HasVector(false) { 6807 IntMaxType = SignedLong; 6808 Int64Type = SignedLong; 6809 TLSSupported = true; 6810 IntWidth = IntAlign = 32; 6811 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6812 PointerWidth = PointerAlign = 64; 6813 LongDoubleWidth = 128; 6814 LongDoubleAlign = 64; 6815 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6816 DefaultAlignForAttributeAligned = 64; 6817 MinGlobalAlign = 16; 6818 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 6819 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6820 } 6821 void getTargetDefines(const LangOptions &Opts, 6822 MacroBuilder &Builder) const override { 6823 Builder.defineMacro("__s390__"); 6824 Builder.defineMacro("__s390x__"); 6825 Builder.defineMacro("__zarch__"); 6826 Builder.defineMacro("__LONG_DOUBLE_128__"); 6827 6828 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6829 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6830 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6831 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6832 6833 if (HasTransactionalExecution) 6834 Builder.defineMacro("__HTM__"); 6835 if (Opts.ZVector) 6836 Builder.defineMacro("__VEC__", "10301"); 6837 } 6838 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6839 return llvm::makeArrayRef(BuiltinInfo, 6840 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6841 } 6842 6843 ArrayRef<const char *> getGCCRegNames() const override; 6844 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6845 // No aliases. 6846 return None; 6847 } 6848 bool validateAsmConstraint(const char *&Name, 6849 TargetInfo::ConstraintInfo &info) const override; 6850 const char *getClobbers() const override { 6851 // FIXME: Is this really right? 6852 return ""; 6853 } 6854 BuiltinVaListKind getBuiltinVaListKind() const override { 6855 return TargetInfo::SystemZBuiltinVaList; 6856 } 6857 bool setCPU(const std::string &Name) override { 6858 CPU = Name; 6859 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6860 .Case("z10", true) 6861 .Case("z196", true) 6862 .Case("zEC12", true) 6863 .Case("z13", true) 6864 .Default(false); 6865 6866 return CPUKnown; 6867 } 6868 bool 6869 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6870 StringRef CPU, 6871 const std::vector<std::string> &FeaturesVec) const override { 6872 if (CPU == "zEC12") 6873 Features["transactional-execution"] = true; 6874 if (CPU == "z13") { 6875 Features["transactional-execution"] = true; 6876 Features["vector"] = true; 6877 } 6878 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6879 } 6880 6881 bool handleTargetFeatures(std::vector<std::string> &Features, 6882 DiagnosticsEngine &Diags) override { 6883 HasTransactionalExecution = false; 6884 for (const auto &Feature : Features) { 6885 if (Feature == "+transactional-execution") 6886 HasTransactionalExecution = true; 6887 else if (Feature == "+vector") 6888 HasVector = true; 6889 } 6890 // If we use the vector ABI, vector types are 64-bit aligned. 6891 if (HasVector) { 6892 MaxVectorAlign = 64; 6893 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6894 "-v128:64-a:8:16-n32:64"); 6895 } 6896 return true; 6897 } 6898 6899 bool hasFeature(StringRef Feature) const override { 6900 return llvm::StringSwitch<bool>(Feature) 6901 .Case("systemz", true) 6902 .Case("htm", HasTransactionalExecution) 6903 .Case("vx", HasVector) 6904 .Default(false); 6905 } 6906 6907 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6908 switch (CC) { 6909 case CC_C: 6910 case CC_Swift: 6911 return CCCR_OK; 6912 default: 6913 return CCCR_Warning; 6914 } 6915 } 6916 6917 StringRef getABI() const override { 6918 if (HasVector) 6919 return "vector"; 6920 return ""; 6921 } 6922 6923 bool useFloat128ManglingForLongDouble() const override { 6924 return true; 6925 } 6926 }; 6927 6928 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6929 #define BUILTIN(ID, TYPE, ATTRS) \ 6930 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6931 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 6932 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 6933 #include "clang/Basic/BuiltinsSystemZ.def" 6934 }; 6935 6936 const char *const SystemZTargetInfo::GCCRegNames[] = { 6937 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6938 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6939 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6940 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6941 }; 6942 6943 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6944 return llvm::makeArrayRef(GCCRegNames); 6945 } 6946 6947 bool SystemZTargetInfo:: 6948 validateAsmConstraint(const char *&Name, 6949 TargetInfo::ConstraintInfo &Info) const { 6950 switch (*Name) { 6951 default: 6952 return false; 6953 6954 case 'a': // Address register 6955 case 'd': // Data register (equivalent to 'r') 6956 case 'f': // Floating-point register 6957 Info.setAllowsRegister(); 6958 return true; 6959 6960 case 'I': // Unsigned 8-bit constant 6961 case 'J': // Unsigned 12-bit constant 6962 case 'K': // Signed 16-bit constant 6963 case 'L': // Signed 20-bit displacement (on all targets we support) 6964 case 'M': // 0x7fffffff 6965 return true; 6966 6967 case 'Q': // Memory with base and unsigned 12-bit displacement 6968 case 'R': // Likewise, plus an index 6969 case 'S': // Memory with base and signed 20-bit displacement 6970 case 'T': // Likewise, plus an index 6971 Info.setAllowsMemory(); 6972 return true; 6973 } 6974 } 6975 6976 class MSP430TargetInfo : public TargetInfo { 6977 static const char *const GCCRegNames[]; 6978 6979 public: 6980 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6981 : TargetInfo(Triple) { 6982 TLSSupported = false; 6983 IntWidth = 16; 6984 IntAlign = 16; 6985 LongWidth = 32; 6986 LongLongWidth = 64; 6987 LongAlign = LongLongAlign = 16; 6988 PointerWidth = 16; 6989 PointerAlign = 16; 6990 SuitableAlign = 16; 6991 SizeType = UnsignedInt; 6992 IntMaxType = SignedLongLong; 6993 IntPtrType = SignedInt; 6994 PtrDiffType = SignedInt; 6995 SigAtomicType = SignedLong; 6996 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 6997 } 6998 void getTargetDefines(const LangOptions &Opts, 6999 MacroBuilder &Builder) const override { 7000 Builder.defineMacro("MSP430"); 7001 Builder.defineMacro("__MSP430__"); 7002 // FIXME: defines for different 'flavours' of MCU 7003 } 7004 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7005 // FIXME: Implement. 7006 return None; 7007 } 7008 bool hasFeature(StringRef Feature) const override { 7009 return Feature == "msp430"; 7010 } 7011 ArrayRef<const char *> getGCCRegNames() const override; 7012 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7013 // No aliases. 7014 return None; 7015 } 7016 bool validateAsmConstraint(const char *&Name, 7017 TargetInfo::ConstraintInfo &info) const override { 7018 // FIXME: implement 7019 switch (*Name) { 7020 case 'K': // the constant 1 7021 case 'L': // constant -1^20 .. 1^19 7022 case 'M': // constant 1-4: 7023 return true; 7024 } 7025 // No target constraints for now. 7026 return false; 7027 } 7028 const char *getClobbers() const override { 7029 // FIXME: Is this really right? 7030 return ""; 7031 } 7032 BuiltinVaListKind getBuiltinVaListKind() const override { 7033 // FIXME: implement 7034 return TargetInfo::CharPtrBuiltinVaList; 7035 } 7036 }; 7037 7038 const char *const MSP430TargetInfo::GCCRegNames[] = { 7039 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7040 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7041 7042 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7043 return llvm::makeArrayRef(GCCRegNames); 7044 } 7045 7046 // LLVM and Clang cannot be used directly to output native binaries for 7047 // target, but is used to compile C code to llvm bitcode with correct 7048 // type and alignment information. 7049 // 7050 // TCE uses the llvm bitcode as input and uses it for generating customized 7051 // target processor and program binary. TCE co-design environment is 7052 // publicly available in http://tce.cs.tut.fi 7053 7054 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7055 3, // opencl_global 7056 4, // opencl_local 7057 5, // opencl_constant 7058 // FIXME: generic has to be added to the target 7059 0, // opencl_generic 7060 0, // cuda_device 7061 0, // cuda_constant 7062 0 // cuda_shared 7063 }; 7064 7065 class TCETargetInfo : public TargetInfo { 7066 public: 7067 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7068 : TargetInfo(Triple) { 7069 TLSSupported = false; 7070 IntWidth = 32; 7071 LongWidth = LongLongWidth = 32; 7072 PointerWidth = 32; 7073 IntAlign = 32; 7074 LongAlign = LongLongAlign = 32; 7075 PointerAlign = 32; 7076 SuitableAlign = 32; 7077 SizeType = UnsignedInt; 7078 IntMaxType = SignedLong; 7079 IntPtrType = SignedInt; 7080 PtrDiffType = SignedInt; 7081 FloatWidth = 32; 7082 FloatAlign = 32; 7083 DoubleWidth = 32; 7084 DoubleAlign = 32; 7085 LongDoubleWidth = 32; 7086 LongDoubleAlign = 32; 7087 FloatFormat = &llvm::APFloat::IEEEsingle; 7088 DoubleFormat = &llvm::APFloat::IEEEsingle; 7089 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 7090 resetDataLayout("E-p:32:32-i8:8:32-i16:16:32-i64:32" 7091 "-f64:32-v64:32-v128:32-a:0:32-n32"); 7092 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7093 UseAddrSpaceMapMangling = true; 7094 } 7095 7096 void getTargetDefines(const LangOptions &Opts, 7097 MacroBuilder &Builder) const override { 7098 DefineStd(Builder, "tce", Opts); 7099 Builder.defineMacro("__TCE__"); 7100 Builder.defineMacro("__TCE_V1__"); 7101 } 7102 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7103 7104 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7105 const char *getClobbers() const override { return ""; } 7106 BuiltinVaListKind getBuiltinVaListKind() const override { 7107 return TargetInfo::VoidPtrBuiltinVaList; 7108 } 7109 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7110 bool validateAsmConstraint(const char *&Name, 7111 TargetInfo::ConstraintInfo &info) const override { 7112 return true; 7113 } 7114 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7115 return None; 7116 } 7117 }; 7118 7119 class BPFTargetInfo : public TargetInfo { 7120 public: 7121 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7122 : TargetInfo(Triple) { 7123 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7124 SizeType = UnsignedLong; 7125 PtrDiffType = SignedLong; 7126 IntPtrType = SignedLong; 7127 IntMaxType = SignedLong; 7128 Int64Type = SignedLong; 7129 RegParmMax = 5; 7130 if (Triple.getArch() == llvm::Triple::bpfeb) { 7131 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7132 } else { 7133 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7134 } 7135 MaxAtomicPromoteWidth = 64; 7136 MaxAtomicInlineWidth = 64; 7137 TLSSupported = false; 7138 } 7139 void getTargetDefines(const LangOptions &Opts, 7140 MacroBuilder &Builder) const override { 7141 DefineStd(Builder, "bpf", Opts); 7142 Builder.defineMacro("__BPF__"); 7143 } 7144 bool hasFeature(StringRef Feature) const override { 7145 return Feature == "bpf"; 7146 } 7147 7148 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7149 const char *getClobbers() const override { 7150 return ""; 7151 } 7152 BuiltinVaListKind getBuiltinVaListKind() const override { 7153 return TargetInfo::VoidPtrBuiltinVaList; 7154 } 7155 ArrayRef<const char *> getGCCRegNames() const override { 7156 return None; 7157 } 7158 bool validateAsmConstraint(const char *&Name, 7159 TargetInfo::ConstraintInfo &info) const override { 7160 return true; 7161 } 7162 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7163 return None; 7164 } 7165 }; 7166 7167 class MipsTargetInfo : public TargetInfo { 7168 void setDataLayout() { 7169 StringRef Layout; 7170 7171 if (ABI == "o32") 7172 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7173 else if (ABI == "n32") 7174 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7175 else if (ABI == "n64") 7176 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7177 else 7178 llvm_unreachable("Invalid ABI"); 7179 7180 if (BigEndian) 7181 resetDataLayout(("E-" + Layout).str()); 7182 else 7183 resetDataLayout(("e-" + Layout).str()); 7184 } 7185 7186 7187 static const Builtin::Info BuiltinInfo[]; 7188 std::string CPU; 7189 bool IsMips16; 7190 bool IsMicromips; 7191 bool IsNan2008; 7192 bool IsSingleFloat; 7193 enum MipsFloatABI { 7194 HardFloat, SoftFloat 7195 } FloatABI; 7196 enum DspRevEnum { 7197 NoDSP, DSP1, DSP2 7198 } DspRev; 7199 bool HasMSA; 7200 7201 protected: 7202 bool HasFP64; 7203 std::string ABI; 7204 7205 public: 7206 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7207 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7208 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 7209 DspRev(NoDSP), HasMSA(false), HasFP64(false) { 7210 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7211 7212 setABI((getTriple().getArch() == llvm::Triple::mips || 7213 getTriple().getArch() == llvm::Triple::mipsel) 7214 ? "o32" 7215 : "n64"); 7216 7217 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7218 } 7219 7220 bool isNaN2008Default() const { 7221 return CPU == "mips32r6" || CPU == "mips64r6"; 7222 } 7223 7224 bool isFP64Default() const { 7225 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7226 } 7227 7228 bool isNan2008() const override { 7229 return IsNan2008; 7230 } 7231 7232 bool processorSupportsGPR64() const { 7233 return llvm::StringSwitch<bool>(CPU) 7234 .Case("mips3", true) 7235 .Case("mips4", true) 7236 .Case("mips5", true) 7237 .Case("mips64", true) 7238 .Case("mips64r2", true) 7239 .Case("mips64r3", true) 7240 .Case("mips64r5", true) 7241 .Case("mips64r6", true) 7242 .Case("octeon", true) 7243 .Default(false); 7244 return false; 7245 } 7246 7247 StringRef getABI() const override { return ABI; } 7248 bool setABI(const std::string &Name) override { 7249 if (Name == "o32") { 7250 setO32ABITypes(); 7251 ABI = Name; 7252 return true; 7253 } 7254 7255 if (Name == "n32") { 7256 setN32ABITypes(); 7257 ABI = Name; 7258 return true; 7259 } 7260 if (Name == "n64") { 7261 setN64ABITypes(); 7262 ABI = Name; 7263 return true; 7264 } 7265 return false; 7266 } 7267 7268 void setO32ABITypes() { 7269 Int64Type = SignedLongLong; 7270 IntMaxType = Int64Type; 7271 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7272 LongDoubleWidth = LongDoubleAlign = 64; 7273 LongWidth = LongAlign = 32; 7274 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7275 PointerWidth = PointerAlign = 32; 7276 PtrDiffType = SignedInt; 7277 SizeType = UnsignedInt; 7278 SuitableAlign = 64; 7279 } 7280 7281 void setN32N64ABITypes() { 7282 LongDoubleWidth = LongDoubleAlign = 128; 7283 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7284 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7285 LongDoubleWidth = LongDoubleAlign = 64; 7286 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7287 } 7288 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7289 SuitableAlign = 128; 7290 } 7291 7292 void setN64ABITypes() { 7293 setN32N64ABITypes(); 7294 Int64Type = SignedLong; 7295 IntMaxType = Int64Type; 7296 LongWidth = LongAlign = 64; 7297 PointerWidth = PointerAlign = 64; 7298 PtrDiffType = SignedLong; 7299 SizeType = UnsignedLong; 7300 } 7301 7302 void setN32ABITypes() { 7303 setN32N64ABITypes(); 7304 Int64Type = SignedLongLong; 7305 IntMaxType = Int64Type; 7306 LongWidth = LongAlign = 32; 7307 PointerWidth = PointerAlign = 32; 7308 PtrDiffType = SignedInt; 7309 SizeType = UnsignedInt; 7310 } 7311 7312 bool setCPU(const std::string &Name) override { 7313 CPU = Name; 7314 return llvm::StringSwitch<bool>(Name) 7315 .Case("mips1", true) 7316 .Case("mips2", true) 7317 .Case("mips3", true) 7318 .Case("mips4", true) 7319 .Case("mips5", true) 7320 .Case("mips32", true) 7321 .Case("mips32r2", true) 7322 .Case("mips32r3", true) 7323 .Case("mips32r5", true) 7324 .Case("mips32r6", true) 7325 .Case("mips64", true) 7326 .Case("mips64r2", true) 7327 .Case("mips64r3", true) 7328 .Case("mips64r5", true) 7329 .Case("mips64r6", true) 7330 .Case("octeon", true) 7331 .Case("p5600", true) 7332 .Default(false); 7333 } 7334 const std::string& getCPU() const { return CPU; } 7335 bool 7336 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7337 StringRef CPU, 7338 const std::vector<std::string> &FeaturesVec) const override { 7339 if (CPU.empty()) 7340 CPU = getCPU(); 7341 if (CPU == "octeon") 7342 Features["mips64r2"] = Features["cnmips"] = true; 7343 else 7344 Features[CPU] = true; 7345 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7346 } 7347 7348 void getTargetDefines(const LangOptions &Opts, 7349 MacroBuilder &Builder) const override { 7350 if (BigEndian) { 7351 DefineStd(Builder, "MIPSEB", Opts); 7352 Builder.defineMacro("_MIPSEB"); 7353 } else { 7354 DefineStd(Builder, "MIPSEL", Opts); 7355 Builder.defineMacro("_MIPSEL"); 7356 } 7357 7358 Builder.defineMacro("__mips__"); 7359 Builder.defineMacro("_mips"); 7360 if (Opts.GNUMode) 7361 Builder.defineMacro("mips"); 7362 7363 if (ABI == "o32") { 7364 Builder.defineMacro("__mips", "32"); 7365 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7366 } else { 7367 Builder.defineMacro("__mips", "64"); 7368 Builder.defineMacro("__mips64"); 7369 Builder.defineMacro("__mips64__"); 7370 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7371 } 7372 7373 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7374 .Cases("mips32", "mips64", "1") 7375 .Cases("mips32r2", "mips64r2", "2") 7376 .Cases("mips32r3", "mips64r3", "3") 7377 .Cases("mips32r5", "mips64r5", "5") 7378 .Cases("mips32r6", "mips64r6", "6") 7379 .Default(""); 7380 if (!ISARev.empty()) 7381 Builder.defineMacro("__mips_isa_rev", ISARev); 7382 7383 if (ABI == "o32") { 7384 Builder.defineMacro("__mips_o32"); 7385 Builder.defineMacro("_ABIO32", "1"); 7386 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7387 } else if (ABI == "n32") { 7388 Builder.defineMacro("__mips_n32"); 7389 Builder.defineMacro("_ABIN32", "2"); 7390 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7391 } else if (ABI == "n64") { 7392 Builder.defineMacro("__mips_n64"); 7393 Builder.defineMacro("_ABI64", "3"); 7394 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7395 } else 7396 llvm_unreachable("Invalid ABI."); 7397 7398 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7399 7400 switch (FloatABI) { 7401 case HardFloat: 7402 Builder.defineMacro("__mips_hard_float", Twine(1)); 7403 break; 7404 case SoftFloat: 7405 Builder.defineMacro("__mips_soft_float", Twine(1)); 7406 break; 7407 } 7408 7409 if (IsSingleFloat) 7410 Builder.defineMacro("__mips_single_float", Twine(1)); 7411 7412 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7413 Builder.defineMacro("_MIPS_FPSET", 7414 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7415 7416 if (IsMips16) 7417 Builder.defineMacro("__mips16", Twine(1)); 7418 7419 if (IsMicromips) 7420 Builder.defineMacro("__mips_micromips", Twine(1)); 7421 7422 if (IsNan2008) 7423 Builder.defineMacro("__mips_nan2008", Twine(1)); 7424 7425 switch (DspRev) { 7426 default: 7427 break; 7428 case DSP1: 7429 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7430 Builder.defineMacro("__mips_dsp", Twine(1)); 7431 break; 7432 case DSP2: 7433 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7434 Builder.defineMacro("__mips_dspr2", Twine(1)); 7435 Builder.defineMacro("__mips_dsp", Twine(1)); 7436 break; 7437 } 7438 7439 if (HasMSA) 7440 Builder.defineMacro("__mips_msa", Twine(1)); 7441 7442 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7443 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7444 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7445 7446 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7447 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7448 7449 // These shouldn't be defined for MIPS-I but there's no need to check 7450 // for that since MIPS-I isn't supported. 7451 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7452 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7453 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7454 7455 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7456 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7457 // the instructions exist but using them violates the ABI since they 7458 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7459 if (ABI == "n32" || ABI == "n64") 7460 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7461 } 7462 7463 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7464 return llvm::makeArrayRef(BuiltinInfo, 7465 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7466 } 7467 bool hasFeature(StringRef Feature) const override { 7468 return llvm::StringSwitch<bool>(Feature) 7469 .Case("mips", true) 7470 .Case("fp64", HasFP64) 7471 .Default(false); 7472 } 7473 BuiltinVaListKind getBuiltinVaListKind() const override { 7474 return TargetInfo::VoidPtrBuiltinVaList; 7475 } 7476 ArrayRef<const char *> getGCCRegNames() const override { 7477 static const char *const GCCRegNames[] = { 7478 // CPU register names 7479 // Must match second column of GCCRegAliases 7480 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7481 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7482 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7483 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7484 // Floating point register names 7485 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7486 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7487 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7488 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7489 // Hi/lo and condition register names 7490 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7491 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7492 "$ac3hi","$ac3lo", 7493 // MSA register names 7494 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7495 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7496 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7497 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7498 // MSA control register names 7499 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7500 "$msarequest", "$msamap", "$msaunmap" 7501 }; 7502 return llvm::makeArrayRef(GCCRegNames); 7503 } 7504 bool validateAsmConstraint(const char *&Name, 7505 TargetInfo::ConstraintInfo &Info) const override { 7506 switch (*Name) { 7507 default: 7508 return false; 7509 case 'r': // CPU registers. 7510 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7511 case 'y': // Equivalent to "r", backward compatibility only. 7512 case 'f': // floating-point registers. 7513 case 'c': // $25 for indirect jumps 7514 case 'l': // lo register 7515 case 'x': // hilo register pair 7516 Info.setAllowsRegister(); 7517 return true; 7518 case 'I': // Signed 16-bit constant 7519 case 'J': // Integer 0 7520 case 'K': // Unsigned 16-bit constant 7521 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7522 case 'M': // Constants not loadable via lui, addiu, or ori 7523 case 'N': // Constant -1 to -65535 7524 case 'O': // A signed 15-bit constant 7525 case 'P': // A constant between 1 go 65535 7526 return true; 7527 case 'R': // An address that can be used in a non-macro load or store 7528 Info.setAllowsMemory(); 7529 return true; 7530 case 'Z': 7531 if (Name[1] == 'C') { // An address usable by ll, and sc. 7532 Info.setAllowsMemory(); 7533 Name++; // Skip over 'Z'. 7534 return true; 7535 } 7536 return false; 7537 } 7538 } 7539 7540 std::string convertConstraint(const char *&Constraint) const override { 7541 std::string R; 7542 switch (*Constraint) { 7543 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7544 if (Constraint[1] == 'C') { 7545 R = std::string("^") + std::string(Constraint, 2); 7546 Constraint++; 7547 return R; 7548 } 7549 break; 7550 } 7551 return TargetInfo::convertConstraint(Constraint); 7552 } 7553 7554 const char *getClobbers() const override { 7555 // In GCC, $1 is not widely used in generated code (it's used only in a few 7556 // specific situations), so there is no real need for users to add it to 7557 // the clobbers list if they want to use it in their inline assembly code. 7558 // 7559 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7560 // code generation, so using it in inline assembly without adding it to the 7561 // clobbers list can cause conflicts between the inline assembly code and 7562 // the surrounding generated code. 7563 // 7564 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7565 // operands, which will conflict with the ".set at" assembler option (which 7566 // we use only for inline assembly, in order to maintain compatibility with 7567 // GCC) and will also conflict with the user's usage of $1. 7568 // 7569 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7570 // register for generated code is to automatically clobber $1 for all inline 7571 // assembly code. 7572 // 7573 // FIXME: We should automatically clobber $1 only for inline assembly code 7574 // which actually uses it. This would allow LLVM to use $1 for inline 7575 // assembly operands if the user's assembly code doesn't use it. 7576 return "~{$1}"; 7577 } 7578 7579 bool handleTargetFeatures(std::vector<std::string> &Features, 7580 DiagnosticsEngine &Diags) override { 7581 IsMips16 = false; 7582 IsMicromips = false; 7583 IsNan2008 = isNaN2008Default(); 7584 IsSingleFloat = false; 7585 FloatABI = HardFloat; 7586 DspRev = NoDSP; 7587 HasFP64 = isFP64Default(); 7588 7589 for (const auto &Feature : Features) { 7590 if (Feature == "+single-float") 7591 IsSingleFloat = true; 7592 else if (Feature == "+soft-float") 7593 FloatABI = SoftFloat; 7594 else if (Feature == "+mips16") 7595 IsMips16 = true; 7596 else if (Feature == "+micromips") 7597 IsMicromips = true; 7598 else if (Feature == "+dsp") 7599 DspRev = std::max(DspRev, DSP1); 7600 else if (Feature == "+dspr2") 7601 DspRev = std::max(DspRev, DSP2); 7602 else if (Feature == "+msa") 7603 HasMSA = true; 7604 else if (Feature == "+fp64") 7605 HasFP64 = true; 7606 else if (Feature == "-fp64") 7607 HasFP64 = false; 7608 else if (Feature == "+nan2008") 7609 IsNan2008 = true; 7610 else if (Feature == "-nan2008") 7611 IsNan2008 = false; 7612 } 7613 7614 setDataLayout(); 7615 7616 return true; 7617 } 7618 7619 int getEHDataRegisterNumber(unsigned RegNo) const override { 7620 if (RegNo == 0) return 4; 7621 if (RegNo == 1) return 5; 7622 return -1; 7623 } 7624 7625 bool isCLZForZeroUndef() const override { return false; } 7626 7627 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7628 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 7629 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7630 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7631 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 7632 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 7633 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 7634 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7635 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7636 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7637 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7638 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7639 {{"ra"}, "$31"}}; 7640 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 7641 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7642 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7643 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 7644 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 7645 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 7646 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7647 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7648 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7649 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7650 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7651 {{"ra"}, "$31"}}; 7652 if (ABI == "o32") 7653 return llvm::makeArrayRef(O32RegAliases); 7654 return llvm::makeArrayRef(NewABIRegAliases); 7655 } 7656 7657 bool hasInt128Type() const override { 7658 return ABI == "n32" || ABI == "n64"; 7659 } 7660 7661 bool validateTarget(DiagnosticsEngine &Diags) const override { 7662 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 7663 // this yet. It's better to fail here than on the backend assertion. 7664 if (processorSupportsGPR64() && ABI == "o32") { 7665 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7666 return false; 7667 } 7668 7669 // 64-bit ABI's require 64-bit CPU's. 7670 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 7671 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7672 return false; 7673 } 7674 7675 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 7676 // can't handle this yet. It's better to fail here than on the 7677 // backend assertion. 7678 if ((getTriple().getArch() == llvm::Triple::mips64 || 7679 getTriple().getArch() == llvm::Triple::mips64el) && 7680 ABI == "o32") { 7681 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7682 << ABI << getTriple().str(); 7683 return false; 7684 } 7685 7686 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 7687 // can't handle this yet. It's better to fail here than on the 7688 // backend assertion. 7689 if ((getTriple().getArch() == llvm::Triple::mips || 7690 getTriple().getArch() == llvm::Triple::mipsel) && 7691 (ABI == "n32" || ABI == "n64")) { 7692 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7693 << ABI << getTriple().str(); 7694 return false; 7695 } 7696 7697 return true; 7698 } 7699 }; 7700 7701 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 7702 #define BUILTIN(ID, TYPE, ATTRS) \ 7703 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7704 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7705 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7706 #include "clang/Basic/BuiltinsMips.def" 7707 }; 7708 7709 class PNaClTargetInfo : public TargetInfo { 7710 public: 7711 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7712 : TargetInfo(Triple) { 7713 this->LongAlign = 32; 7714 this->LongWidth = 32; 7715 this->PointerAlign = 32; 7716 this->PointerWidth = 32; 7717 this->IntMaxType = TargetInfo::SignedLongLong; 7718 this->Int64Type = TargetInfo::SignedLongLong; 7719 this->DoubleAlign = 64; 7720 this->LongDoubleWidth = 64; 7721 this->LongDoubleAlign = 64; 7722 this->SizeType = TargetInfo::UnsignedInt; 7723 this->PtrDiffType = TargetInfo::SignedInt; 7724 this->IntPtrType = TargetInfo::SignedInt; 7725 this->RegParmMax = 0; // Disallow regparm 7726 } 7727 7728 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7729 Builder.defineMacro("__le32__"); 7730 Builder.defineMacro("__pnacl__"); 7731 } 7732 void getTargetDefines(const LangOptions &Opts, 7733 MacroBuilder &Builder) const override { 7734 getArchDefines(Opts, Builder); 7735 } 7736 bool hasFeature(StringRef Feature) const override { 7737 return Feature == "pnacl"; 7738 } 7739 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7740 BuiltinVaListKind getBuiltinVaListKind() const override { 7741 return TargetInfo::PNaClABIBuiltinVaList; 7742 } 7743 ArrayRef<const char *> getGCCRegNames() const override; 7744 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7745 bool validateAsmConstraint(const char *&Name, 7746 TargetInfo::ConstraintInfo &Info) const override { 7747 return false; 7748 } 7749 7750 const char *getClobbers() const override { 7751 return ""; 7752 } 7753 }; 7754 7755 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7756 return None; 7757 } 7758 7759 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7760 return None; 7761 } 7762 7763 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7764 class NaClMips32TargetInfo : public MipsTargetInfo { 7765 public: 7766 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7767 : MipsTargetInfo(Triple, Opts) {} 7768 7769 BuiltinVaListKind getBuiltinVaListKind() const override { 7770 return TargetInfo::PNaClABIBuiltinVaList; 7771 } 7772 }; 7773 7774 class Le64TargetInfo : public TargetInfo { 7775 static const Builtin::Info BuiltinInfo[]; 7776 7777 public: 7778 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7779 : TargetInfo(Triple) { 7780 NoAsmVariants = true; 7781 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7782 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7783 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 7784 } 7785 7786 void getTargetDefines(const LangOptions &Opts, 7787 MacroBuilder &Builder) const override { 7788 DefineStd(Builder, "unix", Opts); 7789 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7790 Builder.defineMacro("__ELF__"); 7791 } 7792 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7793 return llvm::makeArrayRef(BuiltinInfo, 7794 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7795 } 7796 BuiltinVaListKind getBuiltinVaListKind() const override { 7797 return TargetInfo::PNaClABIBuiltinVaList; 7798 } 7799 const char *getClobbers() const override { return ""; } 7800 ArrayRef<const char *> getGCCRegNames() const override { 7801 return None; 7802 } 7803 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7804 return None; 7805 } 7806 bool validateAsmConstraint(const char *&Name, 7807 TargetInfo::ConstraintInfo &Info) const override { 7808 return false; 7809 } 7810 7811 bool hasProtectedVisibility() const override { return false; } 7812 }; 7813 7814 class WebAssemblyTargetInfo : public TargetInfo { 7815 static const Builtin::Info BuiltinInfo[]; 7816 7817 enum SIMDEnum { 7818 NoSIMD, 7819 SIMD128, 7820 } SIMDLevel; 7821 7822 public: 7823 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 7824 : TargetInfo(T), SIMDLevel(NoSIMD) { 7825 NoAsmVariants = true; 7826 SuitableAlign = 128; 7827 LargeArrayMinWidth = 128; 7828 LargeArrayAlign = 128; 7829 SimdDefaultAlign = 128; 7830 SigAtomicType = SignedLong; 7831 LongDoubleWidth = LongDoubleAlign = 128; 7832 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7833 SizeType = UnsignedInt; 7834 PtrDiffType = SignedInt; 7835 IntPtrType = SignedInt; 7836 } 7837 7838 protected: 7839 void getTargetDefines(const LangOptions &Opts, 7840 MacroBuilder &Builder) const override { 7841 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7842 if (SIMDLevel >= SIMD128) 7843 Builder.defineMacro("__wasm_simd128__"); 7844 } 7845 7846 private: 7847 bool 7848 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7849 StringRef CPU, 7850 const std::vector<std::string> &FeaturesVec) const override { 7851 if (CPU == "bleeding-edge") 7852 Features["simd128"] = true; 7853 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7854 } 7855 bool hasFeature(StringRef Feature) const final { 7856 return llvm::StringSwitch<bool>(Feature) 7857 .Case("simd128", SIMDLevel >= SIMD128) 7858 .Default(false); 7859 } 7860 bool handleTargetFeatures(std::vector<std::string> &Features, 7861 DiagnosticsEngine &Diags) final { 7862 for (const auto &Feature : Features) { 7863 if (Feature == "+simd128") { 7864 SIMDLevel = std::max(SIMDLevel, SIMD128); 7865 continue; 7866 } 7867 if (Feature == "-simd128") { 7868 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7869 continue; 7870 } 7871 7872 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7873 << "-target-feature"; 7874 return false; 7875 } 7876 return true; 7877 } 7878 bool setCPU(const std::string &Name) final { 7879 return llvm::StringSwitch<bool>(Name) 7880 .Case("mvp", true) 7881 .Case("bleeding-edge", true) 7882 .Case("generic", true) 7883 .Default(false); 7884 } 7885 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7886 return llvm::makeArrayRef(BuiltinInfo, 7887 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7888 } 7889 BuiltinVaListKind getBuiltinVaListKind() const final { 7890 return VoidPtrBuiltinVaList; 7891 } 7892 ArrayRef<const char *> getGCCRegNames() const final { 7893 return None; 7894 } 7895 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7896 return None; 7897 } 7898 bool 7899 validateAsmConstraint(const char *&Name, 7900 TargetInfo::ConstraintInfo &Info) const final { 7901 return false; 7902 } 7903 const char *getClobbers() const final { return ""; } 7904 bool isCLZForZeroUndef() const final { return false; } 7905 bool hasInt128Type() const final { return true; } 7906 IntType getIntTypeByWidth(unsigned BitWidth, 7907 bool IsSigned) const final { 7908 // WebAssembly prefers long long for explicitly 64-bit integers. 7909 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7910 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7911 } 7912 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7913 bool IsSigned) const final { 7914 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7915 return BitWidth == 64 7916 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7917 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7918 } 7919 }; 7920 7921 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7922 #define BUILTIN(ID, TYPE, ATTRS) \ 7923 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7924 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7925 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7926 #include "clang/Basic/BuiltinsWebAssembly.def" 7927 }; 7928 7929 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7930 public: 7931 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 7932 const TargetOptions &Opts) 7933 : WebAssemblyTargetInfo(T, Opts) { 7934 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7935 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 7936 } 7937 7938 protected: 7939 void getTargetDefines(const LangOptions &Opts, 7940 MacroBuilder &Builder) const override { 7941 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7942 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7943 } 7944 }; 7945 7946 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7947 public: 7948 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 7949 const TargetOptions &Opts) 7950 : WebAssemblyTargetInfo(T, Opts) { 7951 LongAlign = LongWidth = 64; 7952 PointerAlign = PointerWidth = 64; 7953 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7954 SizeType = UnsignedLong; 7955 PtrDiffType = SignedLong; 7956 IntPtrType = SignedLong; 7957 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7958 } 7959 7960 protected: 7961 void getTargetDefines(const LangOptions &Opts, 7962 MacroBuilder &Builder) const override { 7963 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7964 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7965 } 7966 }; 7967 7968 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7969 #define BUILTIN(ID, TYPE, ATTRS) \ 7970 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7971 #include "clang/Basic/BuiltinsLe64.def" 7972 }; 7973 7974 static const unsigned SPIRAddrSpaceMap[] = { 7975 1, // opencl_global 7976 3, // opencl_local 7977 2, // opencl_constant 7978 4, // opencl_generic 7979 0, // cuda_device 7980 0, // cuda_constant 7981 0 // cuda_shared 7982 }; 7983 class SPIRTargetInfo : public TargetInfo { 7984 public: 7985 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7986 : TargetInfo(Triple) { 7987 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7988 "SPIR target must use unknown OS"); 7989 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7990 "SPIR target must use unknown environment type"); 7991 TLSSupported = false; 7992 LongWidth = LongAlign = 64; 7993 AddrSpaceMap = &SPIRAddrSpaceMap; 7994 UseAddrSpaceMapMangling = true; 7995 // Define available target features 7996 // These must be defined in sorted order! 7997 NoAsmVariants = true; 7998 } 7999 void getTargetDefines(const LangOptions &Opts, 8000 MacroBuilder &Builder) const override { 8001 DefineStd(Builder, "SPIR", Opts); 8002 } 8003 bool hasFeature(StringRef Feature) const override { 8004 return Feature == "spir"; 8005 } 8006 8007 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8008 const char *getClobbers() const override { return ""; } 8009 ArrayRef<const char *> getGCCRegNames() const override { return None; } 8010 bool validateAsmConstraint(const char *&Name, 8011 TargetInfo::ConstraintInfo &info) const override { 8012 return true; 8013 } 8014 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8015 return None; 8016 } 8017 BuiltinVaListKind getBuiltinVaListKind() const override { 8018 return TargetInfo::VoidPtrBuiltinVaList; 8019 } 8020 8021 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 8022 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 8023 : CCCR_Warning; 8024 } 8025 8026 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8027 return CC_SpirFunction; 8028 } 8029 8030 void setSupportedOpenCLOpts() override { 8031 // Assume all OpenCL extensions and optional core features are supported 8032 // for SPIR since it is a generic target. 8033 getSupportedOpenCLOpts().setAll(); 8034 } 8035 }; 8036 8037 class SPIR32TargetInfo : public SPIRTargetInfo { 8038 public: 8039 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8040 : SPIRTargetInfo(Triple, Opts) { 8041 PointerWidth = PointerAlign = 32; 8042 SizeType = TargetInfo::UnsignedInt; 8043 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8044 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8045 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8046 } 8047 void getTargetDefines(const LangOptions &Opts, 8048 MacroBuilder &Builder) const override { 8049 DefineStd(Builder, "SPIR32", Opts); 8050 } 8051 }; 8052 8053 class SPIR64TargetInfo : public SPIRTargetInfo { 8054 public: 8055 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8056 : SPIRTargetInfo(Triple, Opts) { 8057 PointerWidth = PointerAlign = 64; 8058 SizeType = TargetInfo::UnsignedLong; 8059 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8060 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8061 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8062 } 8063 void getTargetDefines(const LangOptions &Opts, 8064 MacroBuilder &Builder) const override { 8065 DefineStd(Builder, "SPIR64", Opts); 8066 } 8067 }; 8068 8069 class XCoreTargetInfo : public TargetInfo { 8070 static const Builtin::Info BuiltinInfo[]; 8071 public: 8072 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8073 : TargetInfo(Triple) { 8074 NoAsmVariants = true; 8075 LongLongAlign = 32; 8076 SuitableAlign = 32; 8077 DoubleAlign = LongDoubleAlign = 32; 8078 SizeType = UnsignedInt; 8079 PtrDiffType = SignedInt; 8080 IntPtrType = SignedInt; 8081 WCharType = UnsignedChar; 8082 WIntType = UnsignedInt; 8083 UseZeroLengthBitfieldAlignment = true; 8084 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8085 "-f64:32-a:0:32-n32"); 8086 } 8087 void getTargetDefines(const LangOptions &Opts, 8088 MacroBuilder &Builder) const override { 8089 Builder.defineMacro("__XS1B__"); 8090 } 8091 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8092 return llvm::makeArrayRef(BuiltinInfo, 8093 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8094 } 8095 BuiltinVaListKind getBuiltinVaListKind() const override { 8096 return TargetInfo::VoidPtrBuiltinVaList; 8097 } 8098 const char *getClobbers() const override { 8099 return ""; 8100 } 8101 ArrayRef<const char *> getGCCRegNames() const override { 8102 static const char * const GCCRegNames[] = { 8103 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8104 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8105 }; 8106 return llvm::makeArrayRef(GCCRegNames); 8107 } 8108 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8109 return None; 8110 } 8111 bool validateAsmConstraint(const char *&Name, 8112 TargetInfo::ConstraintInfo &Info) const override { 8113 return false; 8114 } 8115 int getEHDataRegisterNumber(unsigned RegNo) const override { 8116 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8117 return (RegNo < 2)? RegNo : -1; 8118 } 8119 bool allowsLargerPreferedTypeAlignment() const override { 8120 return false; 8121 } 8122 }; 8123 8124 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8125 #define BUILTIN(ID, TYPE, ATTRS) \ 8126 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8127 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8128 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8129 #include "clang/Basic/BuiltinsXCore.def" 8130 }; 8131 8132 // x86_32 Android target 8133 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8134 public: 8135 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8136 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8137 SuitableAlign = 32; 8138 LongDoubleWidth = 64; 8139 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 8140 } 8141 }; 8142 8143 // x86_64 Android target 8144 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8145 public: 8146 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8147 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8148 LongDoubleFormat = &llvm::APFloat::IEEEquad; 8149 } 8150 8151 bool useFloat128ManglingForLongDouble() const override { 8152 return true; 8153 } 8154 }; 8155 8156 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8157 class RenderScript32TargetInfo : public ARMleTargetInfo { 8158 public: 8159 RenderScript32TargetInfo(const llvm::Triple &Triple, 8160 const TargetOptions &Opts) 8161 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8162 Triple.getOSName(), 8163 Triple.getEnvironmentName()), 8164 Opts) { 8165 IsRenderScriptTarget = true; 8166 LongWidth = LongAlign = 64; 8167 } 8168 void getTargetDefines(const LangOptions &Opts, 8169 MacroBuilder &Builder) const override { 8170 Builder.defineMacro("__RENDERSCRIPT__"); 8171 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8172 } 8173 }; 8174 8175 // 64-bit RenderScript is aarch64 8176 class RenderScript64TargetInfo : public AArch64leTargetInfo { 8177 public: 8178 RenderScript64TargetInfo(const llvm::Triple &Triple, 8179 const TargetOptions &Opts) 8180 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 8181 Triple.getOSName(), 8182 Triple.getEnvironmentName()), 8183 Opts) { 8184 IsRenderScriptTarget = true; 8185 } 8186 8187 void getTargetDefines(const LangOptions &Opts, 8188 MacroBuilder &Builder) const override { 8189 Builder.defineMacro("__RENDERSCRIPT__"); 8190 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 8191 } 8192 }; 8193 8194 } // end anonymous namespace 8195 8196 //===----------------------------------------------------------------------===// 8197 // Driver code 8198 //===----------------------------------------------------------------------===// 8199 8200 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 8201 const TargetOptions &Opts) { 8202 llvm::Triple::OSType os = Triple.getOS(); 8203 8204 switch (Triple.getArch()) { 8205 default: 8206 return nullptr; 8207 8208 case llvm::Triple::xcore: 8209 return new XCoreTargetInfo(Triple, Opts); 8210 8211 case llvm::Triple::hexagon: 8212 return new HexagonTargetInfo(Triple, Opts); 8213 8214 case llvm::Triple::lanai: 8215 return new LanaiTargetInfo(Triple, Opts); 8216 8217 case llvm::Triple::aarch64: 8218 if (Triple.isOSDarwin()) 8219 return new DarwinAArch64TargetInfo(Triple, Opts); 8220 8221 switch (os) { 8222 case llvm::Triple::CloudABI: 8223 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 8224 case llvm::Triple::FreeBSD: 8225 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8226 case llvm::Triple::Linux: 8227 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8228 case llvm::Triple::NetBSD: 8229 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8230 default: 8231 return new AArch64leTargetInfo(Triple, Opts); 8232 } 8233 8234 case llvm::Triple::aarch64_be: 8235 switch (os) { 8236 case llvm::Triple::FreeBSD: 8237 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8238 case llvm::Triple::Linux: 8239 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8240 case llvm::Triple::NetBSD: 8241 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8242 default: 8243 return new AArch64beTargetInfo(Triple, Opts); 8244 } 8245 8246 case llvm::Triple::arm: 8247 case llvm::Triple::thumb: 8248 if (Triple.isOSBinFormatMachO()) 8249 return new DarwinARMTargetInfo(Triple, Opts); 8250 8251 switch (os) { 8252 case llvm::Triple::CloudABI: 8253 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts); 8254 case llvm::Triple::Linux: 8255 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 8256 case llvm::Triple::FreeBSD: 8257 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8258 case llvm::Triple::NetBSD: 8259 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8260 case llvm::Triple::OpenBSD: 8261 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8262 case llvm::Triple::Bitrig: 8263 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 8264 case llvm::Triple::RTEMS: 8265 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 8266 case llvm::Triple::NaCl: 8267 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 8268 case llvm::Triple::Win32: 8269 switch (Triple.getEnvironment()) { 8270 case llvm::Triple::Cygnus: 8271 return new CygwinARMTargetInfo(Triple, Opts); 8272 case llvm::Triple::GNU: 8273 return new MinGWARMTargetInfo(Triple, Opts); 8274 case llvm::Triple::Itanium: 8275 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 8276 case llvm::Triple::MSVC: 8277 default: // Assume MSVC for unknown environments 8278 return new MicrosoftARMleTargetInfo(Triple, Opts); 8279 } 8280 default: 8281 return new ARMleTargetInfo(Triple, Opts); 8282 } 8283 8284 case llvm::Triple::armeb: 8285 case llvm::Triple::thumbeb: 8286 if (Triple.isOSDarwin()) 8287 return new DarwinARMTargetInfo(Triple, Opts); 8288 8289 switch (os) { 8290 case llvm::Triple::Linux: 8291 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8292 case llvm::Triple::FreeBSD: 8293 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8294 case llvm::Triple::NetBSD: 8295 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8296 case llvm::Triple::OpenBSD: 8297 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8298 case llvm::Triple::Bitrig: 8299 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8300 case llvm::Triple::RTEMS: 8301 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8302 case llvm::Triple::NaCl: 8303 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8304 default: 8305 return new ARMbeTargetInfo(Triple, Opts); 8306 } 8307 8308 case llvm::Triple::bpfeb: 8309 case llvm::Triple::bpfel: 8310 return new BPFTargetInfo(Triple, Opts); 8311 8312 case llvm::Triple::msp430: 8313 return new MSP430TargetInfo(Triple, Opts); 8314 8315 case llvm::Triple::mips: 8316 switch (os) { 8317 case llvm::Triple::Linux: 8318 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8319 case llvm::Triple::RTEMS: 8320 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8321 case llvm::Triple::FreeBSD: 8322 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8323 case llvm::Triple::NetBSD: 8324 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8325 default: 8326 return new MipsTargetInfo(Triple, Opts); 8327 } 8328 8329 case llvm::Triple::mipsel: 8330 switch (os) { 8331 case llvm::Triple::Linux: 8332 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8333 case llvm::Triple::RTEMS: 8334 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8335 case llvm::Triple::FreeBSD: 8336 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8337 case llvm::Triple::NetBSD: 8338 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8339 case llvm::Triple::NaCl: 8340 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 8341 default: 8342 return new MipsTargetInfo(Triple, Opts); 8343 } 8344 8345 case llvm::Triple::mips64: 8346 switch (os) { 8347 case llvm::Triple::Linux: 8348 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8349 case llvm::Triple::RTEMS: 8350 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8351 case llvm::Triple::FreeBSD: 8352 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8353 case llvm::Triple::NetBSD: 8354 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8355 case llvm::Triple::OpenBSD: 8356 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8357 default: 8358 return new MipsTargetInfo(Triple, Opts); 8359 } 8360 8361 case llvm::Triple::mips64el: 8362 switch (os) { 8363 case llvm::Triple::Linux: 8364 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8365 case llvm::Triple::RTEMS: 8366 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8367 case llvm::Triple::FreeBSD: 8368 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8369 case llvm::Triple::NetBSD: 8370 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8371 case llvm::Triple::OpenBSD: 8372 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8373 default: 8374 return new MipsTargetInfo(Triple, Opts); 8375 } 8376 8377 case llvm::Triple::le32: 8378 switch (os) { 8379 case llvm::Triple::NaCl: 8380 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 8381 default: 8382 return nullptr; 8383 } 8384 8385 case llvm::Triple::le64: 8386 return new Le64TargetInfo(Triple, Opts); 8387 8388 case llvm::Triple::ppc: 8389 if (Triple.isOSDarwin()) 8390 return new DarwinPPC32TargetInfo(Triple, Opts); 8391 switch (os) { 8392 case llvm::Triple::Linux: 8393 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 8394 case llvm::Triple::FreeBSD: 8395 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8396 case llvm::Triple::NetBSD: 8397 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8398 case llvm::Triple::OpenBSD: 8399 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8400 case llvm::Triple::RTEMS: 8401 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 8402 default: 8403 return new PPC32TargetInfo(Triple, Opts); 8404 } 8405 8406 case llvm::Triple::ppc64: 8407 if (Triple.isOSDarwin()) 8408 return new DarwinPPC64TargetInfo(Triple, Opts); 8409 switch (os) { 8410 case llvm::Triple::Linux: 8411 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8412 case llvm::Triple::Lv2: 8413 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 8414 case llvm::Triple::FreeBSD: 8415 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8416 case llvm::Triple::NetBSD: 8417 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8418 default: 8419 return new PPC64TargetInfo(Triple, Opts); 8420 } 8421 8422 case llvm::Triple::ppc64le: 8423 switch (os) { 8424 case llvm::Triple::Linux: 8425 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8426 case llvm::Triple::NetBSD: 8427 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8428 default: 8429 return new PPC64TargetInfo(Triple, Opts); 8430 } 8431 8432 case llvm::Triple::nvptx: 8433 return new NVPTX32TargetInfo(Triple, Opts); 8434 case llvm::Triple::nvptx64: 8435 return new NVPTX64TargetInfo(Triple, Opts); 8436 8437 case llvm::Triple::amdgcn: 8438 case llvm::Triple::r600: 8439 return new AMDGPUTargetInfo(Triple, Opts); 8440 8441 case llvm::Triple::sparc: 8442 switch (os) { 8443 case llvm::Triple::Linux: 8444 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8445 case llvm::Triple::Solaris: 8446 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8447 case llvm::Triple::NetBSD: 8448 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8449 case llvm::Triple::OpenBSD: 8450 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8451 case llvm::Triple::RTEMS: 8452 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8453 default: 8454 return new SparcV8TargetInfo(Triple, Opts); 8455 } 8456 8457 // The 'sparcel' architecture copies all the above cases except for Solaris. 8458 case llvm::Triple::sparcel: 8459 switch (os) { 8460 case llvm::Triple::Linux: 8461 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8462 case llvm::Triple::NetBSD: 8463 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8464 case llvm::Triple::OpenBSD: 8465 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8466 case llvm::Triple::RTEMS: 8467 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8468 default: 8469 return new SparcV8elTargetInfo(Triple, Opts); 8470 } 8471 8472 case llvm::Triple::sparcv9: 8473 switch (os) { 8474 case llvm::Triple::Linux: 8475 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8476 case llvm::Triple::Solaris: 8477 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8478 case llvm::Triple::NetBSD: 8479 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8480 case llvm::Triple::OpenBSD: 8481 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8482 case llvm::Triple::FreeBSD: 8483 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8484 default: 8485 return new SparcV9TargetInfo(Triple, Opts); 8486 } 8487 8488 case llvm::Triple::systemz: 8489 switch (os) { 8490 case llvm::Triple::Linux: 8491 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 8492 default: 8493 return new SystemZTargetInfo(Triple, Opts); 8494 } 8495 8496 case llvm::Triple::tce: 8497 return new TCETargetInfo(Triple, Opts); 8498 8499 case llvm::Triple::x86: 8500 if (Triple.isOSDarwin()) 8501 return new DarwinI386TargetInfo(Triple, Opts); 8502 8503 switch (os) { 8504 case llvm::Triple::CloudABI: 8505 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 8506 case llvm::Triple::Linux: { 8507 switch (Triple.getEnvironment()) { 8508 default: 8509 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 8510 case llvm::Triple::Android: 8511 return new AndroidX86_32TargetInfo(Triple, Opts); 8512 } 8513 } 8514 case llvm::Triple::DragonFly: 8515 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8516 case llvm::Triple::NetBSD: 8517 return new NetBSDI386TargetInfo(Triple, Opts); 8518 case llvm::Triple::OpenBSD: 8519 return new OpenBSDI386TargetInfo(Triple, Opts); 8520 case llvm::Triple::Bitrig: 8521 return new BitrigI386TargetInfo(Triple, Opts); 8522 case llvm::Triple::FreeBSD: 8523 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8524 case llvm::Triple::KFreeBSD: 8525 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8526 case llvm::Triple::Minix: 8527 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 8528 case llvm::Triple::Solaris: 8529 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 8530 case llvm::Triple::Win32: { 8531 switch (Triple.getEnvironment()) { 8532 case llvm::Triple::Cygnus: 8533 return new CygwinX86_32TargetInfo(Triple, Opts); 8534 case llvm::Triple::GNU: 8535 return new MinGWX86_32TargetInfo(Triple, Opts); 8536 case llvm::Triple::Itanium: 8537 case llvm::Triple::MSVC: 8538 default: // Assume MSVC for unknown environments 8539 return new MicrosoftX86_32TargetInfo(Triple, Opts); 8540 } 8541 } 8542 case llvm::Triple::Haiku: 8543 return new HaikuX86_32TargetInfo(Triple, Opts); 8544 case llvm::Triple::RTEMS: 8545 return new RTEMSX86_32TargetInfo(Triple, Opts); 8546 case llvm::Triple::NaCl: 8547 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 8548 case llvm::Triple::ELFIAMCU: 8549 return new MCUX86_32TargetInfo(Triple, Opts); 8550 default: 8551 return new X86_32TargetInfo(Triple, Opts); 8552 } 8553 8554 case llvm::Triple::x86_64: 8555 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 8556 return new DarwinX86_64TargetInfo(Triple, Opts); 8557 8558 switch (os) { 8559 case llvm::Triple::CloudABI: 8560 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 8561 case llvm::Triple::Linux: { 8562 switch (Triple.getEnvironment()) { 8563 default: 8564 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 8565 case llvm::Triple::Android: 8566 return new AndroidX86_64TargetInfo(Triple, Opts); 8567 } 8568 } 8569 case llvm::Triple::DragonFly: 8570 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8571 case llvm::Triple::NetBSD: 8572 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8573 case llvm::Triple::OpenBSD: 8574 return new OpenBSDX86_64TargetInfo(Triple, Opts); 8575 case llvm::Triple::Bitrig: 8576 return new BitrigX86_64TargetInfo(Triple, Opts); 8577 case llvm::Triple::FreeBSD: 8578 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8579 case llvm::Triple::KFreeBSD: 8580 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8581 case llvm::Triple::Solaris: 8582 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 8583 case llvm::Triple::Win32: { 8584 switch (Triple.getEnvironment()) { 8585 case llvm::Triple::Cygnus: 8586 return new CygwinX86_64TargetInfo(Triple, Opts); 8587 case llvm::Triple::GNU: 8588 return new MinGWX86_64TargetInfo(Triple, Opts); 8589 case llvm::Triple::MSVC: 8590 default: // Assume MSVC for unknown environments 8591 return new MicrosoftX86_64TargetInfo(Triple, Opts); 8592 } 8593 } 8594 case llvm::Triple::Haiku: 8595 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 8596 case llvm::Triple::NaCl: 8597 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 8598 case llvm::Triple::PS4: 8599 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 8600 default: 8601 return new X86_64TargetInfo(Triple, Opts); 8602 } 8603 8604 case llvm::Triple::spir: { 8605 if (Triple.getOS() != llvm::Triple::UnknownOS || 8606 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8607 return nullptr; 8608 return new SPIR32TargetInfo(Triple, Opts); 8609 } 8610 case llvm::Triple::spir64: { 8611 if (Triple.getOS() != llvm::Triple::UnknownOS || 8612 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8613 return nullptr; 8614 return new SPIR64TargetInfo(Triple, Opts); 8615 } 8616 case llvm::Triple::wasm32: 8617 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8618 return nullptr; 8619 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 8620 case llvm::Triple::wasm64: 8621 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8622 return nullptr; 8623 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 8624 8625 case llvm::Triple::renderscript32: 8626 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 8627 case llvm::Triple::renderscript64: 8628 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 8629 } 8630 } 8631 8632 /// CreateTargetInfo - Return the target info object for the specified target 8633 /// options. 8634 TargetInfo * 8635 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8636 const std::shared_ptr<TargetOptions> &Opts) { 8637 llvm::Triple Triple(Opts->Triple); 8638 8639 // Construct the target 8640 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 8641 if (!Target) { 8642 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8643 return nullptr; 8644 } 8645 Target->TargetOpts = Opts; 8646 8647 // Set the target CPU if specified. 8648 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8649 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8650 return nullptr; 8651 } 8652 8653 // Set the target ABI if specified. 8654 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8655 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8656 return nullptr; 8657 } 8658 8659 // Set the fp math unit. 8660 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8661 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8662 return nullptr; 8663 } 8664 8665 // Compute the default target features, we need the target to handle this 8666 // because features may have dependencies on one another. 8667 llvm::StringMap<bool> Features; 8668 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8669 Opts->FeaturesAsWritten)) 8670 return nullptr; 8671 8672 // Add the features to the compile options. 8673 Opts->Features.clear(); 8674 for (const auto &F : Features) 8675 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8676 8677 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8678 return nullptr; 8679 8680 Target->setSupportedOpenCLOpts(); 8681 8682 if (!Target->validateTarget(Diags)) 8683 return nullptr; 8684 8685 return Target.release(); 8686 } 8687