1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "clang/Basic/Version.h" 23 #include "llvm/ADT/APFloat.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringExtras.h" 26 #include "llvm/ADT/StringRef.h" 27 #include "llvm/ADT/StringSwitch.h" 28 #include "llvm/ADT/Triple.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/TargetParser.h" 32 #include <algorithm> 33 #include <memory> 34 35 using namespace clang; 36 37 //===----------------------------------------------------------------------===// 38 // Common code shared among targets. 39 //===----------------------------------------------------------------------===// 40 41 /// DefineStd - Define a macro name and standard variants. For example if 42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 43 /// when in GNU mode. 44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 45 const LangOptions &Opts) { 46 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 47 48 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 49 // in the user's namespace. 50 if (Opts.GNUMode) 51 Builder.defineMacro(MacroName); 52 53 // Define __unix. 54 Builder.defineMacro("__" + MacroName); 55 56 // Define __unix__. 57 Builder.defineMacro("__" + MacroName + "__"); 58 } 59 60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 61 bool Tuning = true) { 62 Builder.defineMacro("__" + CPUName); 63 Builder.defineMacro("__" + CPUName + "__"); 64 if (Tuning) 65 Builder.defineMacro("__tune_" + CPUName + "__"); 66 } 67 68 //===----------------------------------------------------------------------===// 69 // Defines specific to certain operating systems. 70 //===----------------------------------------------------------------------===// 71 72 namespace { 73 template<typename TgtInfo> 74 class OSTargetInfo : public TgtInfo { 75 protected: 76 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 77 MacroBuilder &Builder) const=0; 78 public: 79 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 80 void getTargetDefines(const LangOptions &Opts, 81 MacroBuilder &Builder) const override { 82 TgtInfo::getTargetDefines(Opts, Builder); 83 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 84 } 85 86 }; 87 88 // CloudABI Target 89 template <typename Target> 90 class CloudABITargetInfo : public OSTargetInfo<Target> { 91 protected: 92 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 93 MacroBuilder &Builder) const override { 94 Builder.defineMacro("__CloudABI__"); 95 Builder.defineMacro("__ELF__"); 96 97 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 98 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 99 Builder.defineMacro("__STDC_UTF_16__"); 100 Builder.defineMacro("__STDC_UTF_32__"); 101 } 102 103 public: 104 CloudABITargetInfo(const llvm::Triple &Triple) 105 : OSTargetInfo<Target>(Triple) { 106 this->UserLabelPrefix = ""; 107 } 108 }; 109 110 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 111 const llvm::Triple &Triple, 112 StringRef &PlatformName, 113 VersionTuple &PlatformMinVersion) { 114 Builder.defineMacro("__APPLE_CC__", "6000"); 115 Builder.defineMacro("__APPLE__"); 116 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 117 // AddressSanitizer doesn't play well with source fortification, which is on 118 // by default on Darwin. 119 if (Opts.Sanitize.has(SanitizerKind::Address)) 120 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 121 122 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 123 if (!Opts.ObjC1) { 124 // __weak is always defined, for use in blocks and with objc pointers. 125 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 126 Builder.defineMacro("__strong", ""); 127 Builder.defineMacro("__unsafe_unretained", ""); 128 } 129 130 if (Opts.Static) 131 Builder.defineMacro("__STATIC__"); 132 else 133 Builder.defineMacro("__DYNAMIC__"); 134 135 if (Opts.POSIXThreads) 136 Builder.defineMacro("_REENTRANT"); 137 138 // Get the platform type and version number from the triple. 139 unsigned Maj, Min, Rev; 140 if (Triple.isMacOSX()) { 141 Triple.getMacOSXVersion(Maj, Min, Rev); 142 PlatformName = "macosx"; 143 } else { 144 Triple.getOSVersion(Maj, Min, Rev); 145 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 146 } 147 148 // If -target arch-pc-win32-macho option specified, we're 149 // generating code for Win32 ABI. No need to emit 150 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 151 if (PlatformName == "win32") { 152 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 153 return; 154 } 155 156 // Set the appropriate OS version define. 157 if (Triple.isiOS()) { 158 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 159 char Str[6]; 160 Str[0] = '0' + Maj; 161 Str[1] = '0' + (Min / 10); 162 Str[2] = '0' + (Min % 10); 163 Str[3] = '0' + (Rev / 10); 164 Str[4] = '0' + (Rev % 10); 165 Str[5] = '\0'; 166 if (Triple.isTvOS()) 167 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 168 else 169 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 170 Str); 171 172 } else if (Triple.isWatchOS()) { 173 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 174 char Str[6]; 175 Str[0] = '0' + Maj; 176 Str[1] = '0' + (Min / 10); 177 Str[2] = '0' + (Min % 10); 178 Str[3] = '0' + (Rev / 10); 179 Str[4] = '0' + (Rev % 10); 180 Str[5] = '\0'; 181 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 182 } else if (Triple.isMacOSX()) { 183 // Note that the Driver allows versions which aren't representable in the 184 // define (because we only get a single digit for the minor and micro 185 // revision numbers). So, we limit them to the maximum representable 186 // version. 187 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 188 char Str[7]; 189 if (Maj < 10 || (Maj == 10 && Min < 10)) { 190 Str[0] = '0' + (Maj / 10); 191 Str[1] = '0' + (Maj % 10); 192 Str[2] = '0' + std::min(Min, 9U); 193 Str[3] = '0' + std::min(Rev, 9U); 194 Str[4] = '\0'; 195 } else { 196 // Handle versions > 10.9. 197 Str[0] = '0' + (Maj / 10); 198 Str[1] = '0' + (Maj % 10); 199 Str[2] = '0' + (Min / 10); 200 Str[3] = '0' + (Min % 10); 201 Str[4] = '0' + (Rev / 10); 202 Str[5] = '0' + (Rev % 10); 203 Str[6] = '\0'; 204 } 205 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 206 } 207 208 // Tell users about the kernel if there is one. 209 if (Triple.isOSDarwin()) 210 Builder.defineMacro("__MACH__"); 211 212 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 213 } 214 215 template<typename Target> 216 class DarwinTargetInfo : public OSTargetInfo<Target> { 217 protected: 218 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 219 MacroBuilder &Builder) const override { 220 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 221 this->PlatformMinVersion); 222 } 223 224 public: 225 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 226 // By default, no TLS, and we whitelist permitted architecture/OS 227 // combinations. 228 this->TLSSupported = false; 229 230 if (Triple.isMacOSX()) 231 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 232 else if (Triple.isiOS()) { 233 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 234 if (Triple.getArch() == llvm::Triple::x86_64 || 235 Triple.getArch() == llvm::Triple::aarch64) 236 this->TLSSupported = !Triple.isOSVersionLT(8); 237 else if (Triple.getArch() == llvm::Triple::x86 || 238 Triple.getArch() == llvm::Triple::arm || 239 Triple.getArch() == llvm::Triple::thumb) 240 this->TLSSupported = !Triple.isOSVersionLT(9); 241 } else if (Triple.isWatchOS()) 242 this->TLSSupported = !Triple.isOSVersionLT(2); 243 244 this->MCountName = "\01mcount"; 245 } 246 247 std::string isValidSectionSpecifier(StringRef SR) const override { 248 // Let MCSectionMachO validate this. 249 StringRef Segment, Section; 250 unsigned TAA, StubSize; 251 bool HasTAA; 252 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 253 TAA, HasTAA, StubSize); 254 } 255 256 const char *getStaticInitSectionSpecifier() const override { 257 // FIXME: We should return 0 when building kexts. 258 return "__TEXT,__StaticInit,regular,pure_instructions"; 259 } 260 261 /// Darwin does not support protected visibility. Darwin's "default" 262 /// is very similar to ELF's "protected"; Darwin requires a "weak" 263 /// attribute on declarations that can be dynamically replaced. 264 bool hasProtectedVisibility() const override { 265 return false; 266 } 267 }; 268 269 270 // DragonFlyBSD Target 271 template<typename Target> 272 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 273 protected: 274 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 275 MacroBuilder &Builder) const override { 276 // DragonFly defines; list based off of gcc output 277 Builder.defineMacro("__DragonFly__"); 278 Builder.defineMacro("__DragonFly_cc_version", "100001"); 279 Builder.defineMacro("__ELF__"); 280 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 281 Builder.defineMacro("__tune_i386__"); 282 DefineStd(Builder, "unix", Opts); 283 } 284 public: 285 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 286 : OSTargetInfo<Target>(Triple) { 287 this->UserLabelPrefix = ""; 288 289 switch (Triple.getArch()) { 290 default: 291 case llvm::Triple::x86: 292 case llvm::Triple::x86_64: 293 this->MCountName = ".mcount"; 294 break; 295 } 296 } 297 }; 298 299 // FreeBSD Target 300 template<typename Target> 301 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 302 protected: 303 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 304 MacroBuilder &Builder) const override { 305 // FreeBSD defines; list based off of gcc output 306 307 unsigned Release = Triple.getOSMajorVersion(); 308 if (Release == 0U) 309 Release = 8; 310 311 Builder.defineMacro("__FreeBSD__", Twine(Release)); 312 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 313 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 314 DefineStd(Builder, "unix", Opts); 315 Builder.defineMacro("__ELF__"); 316 317 // On FreeBSD, wchar_t contains the number of the code point as 318 // used by the character set of the locale. These character sets are 319 // not necessarily a superset of ASCII. 320 // 321 // FIXME: This is wrong; the macro refers to the numerical values 322 // of wchar_t *literals*, which are not locale-dependent. However, 323 // FreeBSD systems apparently depend on us getting this wrong, and 324 // setting this to 1 is conforming even if all the basic source 325 // character literals have the same encoding as char and wchar_t. 326 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 327 } 328 public: 329 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 330 this->UserLabelPrefix = ""; 331 332 switch (Triple.getArch()) { 333 default: 334 case llvm::Triple::x86: 335 case llvm::Triple::x86_64: 336 this->MCountName = ".mcount"; 337 break; 338 case llvm::Triple::mips: 339 case llvm::Triple::mipsel: 340 case llvm::Triple::ppc: 341 case llvm::Triple::ppc64: 342 case llvm::Triple::ppc64le: 343 this->MCountName = "_mcount"; 344 break; 345 case llvm::Triple::arm: 346 this->MCountName = "__mcount"; 347 break; 348 } 349 } 350 }; 351 352 // GNU/kFreeBSD Target 353 template<typename Target> 354 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 355 protected: 356 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 357 MacroBuilder &Builder) const override { 358 // GNU/kFreeBSD defines; list based off of gcc output 359 360 DefineStd(Builder, "unix", Opts); 361 Builder.defineMacro("__FreeBSD_kernel__"); 362 Builder.defineMacro("__GLIBC__"); 363 Builder.defineMacro("__ELF__"); 364 if (Opts.POSIXThreads) 365 Builder.defineMacro("_REENTRANT"); 366 if (Opts.CPlusPlus) 367 Builder.defineMacro("_GNU_SOURCE"); 368 } 369 public: 370 KFreeBSDTargetInfo(const llvm::Triple &Triple) 371 : OSTargetInfo<Target>(Triple) { 372 this->UserLabelPrefix = ""; 373 } 374 }; 375 376 // Minix Target 377 template<typename Target> 378 class MinixTargetInfo : public OSTargetInfo<Target> { 379 protected: 380 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 381 MacroBuilder &Builder) const override { 382 // Minix defines 383 384 Builder.defineMacro("__minix", "3"); 385 Builder.defineMacro("_EM_WSIZE", "4"); 386 Builder.defineMacro("_EM_PSIZE", "4"); 387 Builder.defineMacro("_EM_SSIZE", "2"); 388 Builder.defineMacro("_EM_LSIZE", "4"); 389 Builder.defineMacro("_EM_FSIZE", "4"); 390 Builder.defineMacro("_EM_DSIZE", "8"); 391 Builder.defineMacro("__ELF__"); 392 DefineStd(Builder, "unix", Opts); 393 } 394 public: 395 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 396 this->UserLabelPrefix = ""; 397 } 398 }; 399 400 // Linux target 401 template<typename Target> 402 class LinuxTargetInfo : public OSTargetInfo<Target> { 403 protected: 404 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 405 MacroBuilder &Builder) const override { 406 // Linux defines; list based off of gcc output 407 DefineStd(Builder, "unix", Opts); 408 DefineStd(Builder, "linux", Opts); 409 Builder.defineMacro("__gnu_linux__"); 410 Builder.defineMacro("__ELF__"); 411 if (Triple.isAndroid()) { 412 Builder.defineMacro("__ANDROID__", "1"); 413 unsigned Maj, Min, Rev; 414 Triple.getEnvironmentVersion(Maj, Min, Rev); 415 this->PlatformName = "android"; 416 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 417 } 418 if (Opts.POSIXThreads) 419 Builder.defineMacro("_REENTRANT"); 420 if (Opts.CPlusPlus) 421 Builder.defineMacro("_GNU_SOURCE"); 422 } 423 public: 424 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 425 this->UserLabelPrefix = ""; 426 this->WIntType = TargetInfo::UnsignedInt; 427 428 switch (Triple.getArch()) { 429 default: 430 break; 431 case llvm::Triple::ppc: 432 case llvm::Triple::ppc64: 433 case llvm::Triple::ppc64le: 434 this->MCountName = "_mcount"; 435 break; 436 } 437 } 438 439 const char *getStaticInitSectionSpecifier() const override { 440 return ".text.startup"; 441 } 442 }; 443 444 // NetBSD Target 445 template<typename Target> 446 class NetBSDTargetInfo : public OSTargetInfo<Target> { 447 protected: 448 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 449 MacroBuilder &Builder) const override { 450 // NetBSD defines; list based off of gcc output 451 Builder.defineMacro("__NetBSD__"); 452 Builder.defineMacro("__unix__"); 453 Builder.defineMacro("__ELF__"); 454 if (Opts.POSIXThreads) 455 Builder.defineMacro("_POSIX_THREADS"); 456 457 switch (Triple.getArch()) { 458 default: 459 break; 460 case llvm::Triple::arm: 461 case llvm::Triple::armeb: 462 case llvm::Triple::thumb: 463 case llvm::Triple::thumbeb: 464 Builder.defineMacro("__ARM_DWARF_EH__"); 465 break; 466 } 467 } 468 public: 469 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 470 this->UserLabelPrefix = ""; 471 this->MCountName = "_mcount"; 472 } 473 }; 474 475 // OpenBSD Target 476 template<typename Target> 477 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 478 protected: 479 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 480 MacroBuilder &Builder) const override { 481 // OpenBSD defines; list based off of gcc output 482 483 Builder.defineMacro("__OpenBSD__"); 484 DefineStd(Builder, "unix", Opts); 485 Builder.defineMacro("__ELF__"); 486 if (Opts.POSIXThreads) 487 Builder.defineMacro("_REENTRANT"); 488 } 489 public: 490 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 491 this->UserLabelPrefix = ""; 492 this->TLSSupported = false; 493 494 switch (Triple.getArch()) { 495 default: 496 case llvm::Triple::x86: 497 case llvm::Triple::x86_64: 498 case llvm::Triple::arm: 499 case llvm::Triple::sparc: 500 this->MCountName = "__mcount"; 501 break; 502 case llvm::Triple::mips64: 503 case llvm::Triple::mips64el: 504 case llvm::Triple::ppc: 505 case llvm::Triple::sparcv9: 506 this->MCountName = "_mcount"; 507 break; 508 } 509 } 510 }; 511 512 // Bitrig Target 513 template<typename Target> 514 class BitrigTargetInfo : public OSTargetInfo<Target> { 515 protected: 516 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 517 MacroBuilder &Builder) const override { 518 // Bitrig defines; list based off of gcc output 519 520 Builder.defineMacro("__Bitrig__"); 521 DefineStd(Builder, "unix", Opts); 522 Builder.defineMacro("__ELF__"); 523 if (Opts.POSIXThreads) 524 Builder.defineMacro("_REENTRANT"); 525 526 switch (Triple.getArch()) { 527 default: 528 break; 529 case llvm::Triple::arm: 530 case llvm::Triple::armeb: 531 case llvm::Triple::thumb: 532 case llvm::Triple::thumbeb: 533 Builder.defineMacro("__ARM_DWARF_EH__"); 534 break; 535 } 536 } 537 public: 538 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 539 this->UserLabelPrefix = ""; 540 this->MCountName = "__mcount"; 541 } 542 }; 543 544 // PSP Target 545 template<typename Target> 546 class PSPTargetInfo : public OSTargetInfo<Target> { 547 protected: 548 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 549 MacroBuilder &Builder) const override { 550 // PSP defines; list based on the output of the pspdev gcc toolchain. 551 Builder.defineMacro("PSP"); 552 Builder.defineMacro("_PSP"); 553 Builder.defineMacro("__psp__"); 554 Builder.defineMacro("__ELF__"); 555 } 556 public: 557 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 558 this->UserLabelPrefix = ""; 559 } 560 }; 561 562 // PS3 PPU Target 563 template<typename Target> 564 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 565 protected: 566 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 567 MacroBuilder &Builder) const override { 568 // PS3 PPU defines. 569 Builder.defineMacro("__PPC__"); 570 Builder.defineMacro("__PPU__"); 571 Builder.defineMacro("__CELLOS_LV2__"); 572 Builder.defineMacro("__ELF__"); 573 Builder.defineMacro("__LP32__"); 574 Builder.defineMacro("_ARCH_PPC64"); 575 Builder.defineMacro("__powerpc64__"); 576 } 577 public: 578 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 579 this->UserLabelPrefix = ""; 580 this->LongWidth = this->LongAlign = 32; 581 this->PointerWidth = this->PointerAlign = 32; 582 this->IntMaxType = TargetInfo::SignedLongLong; 583 this->Int64Type = TargetInfo::SignedLongLong; 584 this->SizeType = TargetInfo::UnsignedInt; 585 this->DataLayoutString = "E-m:e-p:32:32-i64:64-n32:64"; 586 } 587 }; 588 589 template <typename Target> 590 class PS4OSTargetInfo : public OSTargetInfo<Target> { 591 protected: 592 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 593 MacroBuilder &Builder) const override { 594 Builder.defineMacro("__FreeBSD__", "9"); 595 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 596 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 597 DefineStd(Builder, "unix", Opts); 598 Builder.defineMacro("__ELF__"); 599 Builder.defineMacro("__PS4__"); 600 } 601 public: 602 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 603 this->WCharType = this->UnsignedShort; 604 605 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 606 this->MaxTLSAlign = 256; 607 this->UserLabelPrefix = ""; 608 609 // On PS4, do not honor explicit bit field alignment, 610 // as in "__attribute__((aligned(2))) int b : 1;". 611 this->UseExplicitBitFieldAlignment = false; 612 613 switch (Triple.getArch()) { 614 default: 615 case llvm::Triple::x86_64: 616 this->MCountName = ".mcount"; 617 break; 618 } 619 } 620 }; 621 622 // Solaris target 623 template<typename Target> 624 class SolarisTargetInfo : public OSTargetInfo<Target> { 625 protected: 626 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 627 MacroBuilder &Builder) const override { 628 DefineStd(Builder, "sun", Opts); 629 DefineStd(Builder, "unix", Opts); 630 Builder.defineMacro("__ELF__"); 631 Builder.defineMacro("__svr4__"); 632 Builder.defineMacro("__SVR4"); 633 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 634 // newer, but to 500 for everything else. feature_test.h has a check to 635 // ensure that you are not using C99 with an old version of X/Open or C89 636 // with a new version. 637 if (Opts.C99) 638 Builder.defineMacro("_XOPEN_SOURCE", "600"); 639 else 640 Builder.defineMacro("_XOPEN_SOURCE", "500"); 641 if (Opts.CPlusPlus) 642 Builder.defineMacro("__C99FEATURES__"); 643 Builder.defineMacro("_LARGEFILE_SOURCE"); 644 Builder.defineMacro("_LARGEFILE64_SOURCE"); 645 Builder.defineMacro("__EXTENSIONS__"); 646 Builder.defineMacro("_REENTRANT"); 647 } 648 public: 649 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 650 this->UserLabelPrefix = ""; 651 this->WCharType = this->SignedInt; 652 // FIXME: WIntType should be SignedLong 653 } 654 }; 655 656 // Windows target 657 template<typename Target> 658 class WindowsTargetInfo : public OSTargetInfo<Target> { 659 protected: 660 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 661 MacroBuilder &Builder) const override { 662 Builder.defineMacro("_WIN32"); 663 } 664 void getVisualStudioDefines(const LangOptions &Opts, 665 MacroBuilder &Builder) const { 666 if (Opts.CPlusPlus) { 667 if (Opts.RTTIData) 668 Builder.defineMacro("_CPPRTTI"); 669 670 if (Opts.CXXExceptions) 671 Builder.defineMacro("_CPPUNWIND"); 672 } 673 674 if (Opts.Bool) 675 Builder.defineMacro("__BOOL_DEFINED"); 676 677 if (!Opts.CharIsSigned) 678 Builder.defineMacro("_CHAR_UNSIGNED"); 679 680 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 681 // but it works for now. 682 if (Opts.POSIXThreads) 683 Builder.defineMacro("_MT"); 684 685 if (Opts.MSCompatibilityVersion) { 686 Builder.defineMacro("_MSC_VER", 687 Twine(Opts.MSCompatibilityVersion / 100000)); 688 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 689 // FIXME We cannot encode the revision information into 32-bits 690 Builder.defineMacro("_MSC_BUILD", Twine(1)); 691 692 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 693 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 694 } 695 696 if (Opts.MicrosoftExt) { 697 Builder.defineMacro("_MSC_EXTENSIONS"); 698 699 if (Opts.CPlusPlus11) { 700 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 701 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 702 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 703 } 704 } 705 706 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 707 } 708 709 public: 710 WindowsTargetInfo(const llvm::Triple &Triple) 711 : OSTargetInfo<Target>(Triple) {} 712 }; 713 714 template <typename Target> 715 class NaClTargetInfo : public OSTargetInfo<Target> { 716 protected: 717 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 718 MacroBuilder &Builder) const override { 719 if (Opts.POSIXThreads) 720 Builder.defineMacro("_REENTRANT"); 721 if (Opts.CPlusPlus) 722 Builder.defineMacro("_GNU_SOURCE"); 723 724 DefineStd(Builder, "unix", Opts); 725 Builder.defineMacro("__ELF__"); 726 Builder.defineMacro("__native_client__"); 727 } 728 729 public: 730 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 731 this->UserLabelPrefix = ""; 732 this->LongAlign = 32; 733 this->LongWidth = 32; 734 this->PointerAlign = 32; 735 this->PointerWidth = 32; 736 this->IntMaxType = TargetInfo::SignedLongLong; 737 this->Int64Type = TargetInfo::SignedLongLong; 738 this->DoubleAlign = 64; 739 this->LongDoubleWidth = 64; 740 this->LongDoubleAlign = 64; 741 this->LongLongWidth = 64; 742 this->LongLongAlign = 64; 743 this->SizeType = TargetInfo::UnsignedInt; 744 this->PtrDiffType = TargetInfo::SignedInt; 745 this->IntPtrType = TargetInfo::SignedInt; 746 // RegParmMax is inherited from the underlying architecture 747 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 748 if (Triple.getArch() == llvm::Triple::arm) { 749 // Handled in ARM's setABI(). 750 } else if (Triple.getArch() == llvm::Triple::x86) { 751 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 752 } else if (Triple.getArch() == llvm::Triple::x86_64) { 753 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 754 } else if (Triple.getArch() == llvm::Triple::mipsel) { 755 // Handled on mips' setDataLayoutString. 756 } else { 757 assert(Triple.getArch() == llvm::Triple::le32); 758 this->DataLayoutString = "e-p:32:32-i64:64"; 759 } 760 } 761 }; 762 763 // WebAssembly target 764 template <typename Target> 765 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 766 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 767 MacroBuilder &Builder) const final { 768 // A common platform macro. 769 if (Opts.POSIXThreads) 770 Builder.defineMacro("_REENTRANT"); 771 // Follow g++ convention and predefine _GNU_SOURCE for C++. 772 if (Opts.CPlusPlus) 773 Builder.defineMacro("_GNU_SOURCE"); 774 } 775 776 // As an optimization, group static init code together in a section. 777 const char *getStaticInitSectionSpecifier() const final { 778 return ".text.__startup"; 779 } 780 781 public: 782 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple) 783 : OSTargetInfo<Target>(Triple) { 784 this->MCountName = "__mcount"; 785 this->UserLabelPrefix = ""; 786 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 787 } 788 }; 789 790 //===----------------------------------------------------------------------===// 791 // Specific target implementations. 792 //===----------------------------------------------------------------------===// 793 794 // PPC abstract base class 795 class PPCTargetInfo : public TargetInfo { 796 static const Builtin::Info BuiltinInfo[]; 797 static const char * const GCCRegNames[]; 798 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 799 std::string CPU; 800 801 // Target cpu features. 802 bool HasVSX; 803 bool HasP8Vector; 804 bool HasP8Crypto; 805 bool HasDirectMove; 806 bool HasQPX; 807 bool HasHTM; 808 bool HasBPERMD; 809 bool HasExtDiv; 810 811 protected: 812 std::string ABI; 813 814 public: 815 PPCTargetInfo(const llvm::Triple &Triple) 816 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 817 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 818 HasBPERMD(false), HasExtDiv(false) { 819 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 820 SimdDefaultAlign = 128; 821 LongDoubleWidth = LongDoubleAlign = 128; 822 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 823 } 824 825 /// \brief Flags for architecture specific defines. 826 typedef enum { 827 ArchDefineNone = 0, 828 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 829 ArchDefinePpcgr = 1 << 1, 830 ArchDefinePpcsq = 1 << 2, 831 ArchDefine440 = 1 << 3, 832 ArchDefine603 = 1 << 4, 833 ArchDefine604 = 1 << 5, 834 ArchDefinePwr4 = 1 << 6, 835 ArchDefinePwr5 = 1 << 7, 836 ArchDefinePwr5x = 1 << 8, 837 ArchDefinePwr6 = 1 << 9, 838 ArchDefinePwr6x = 1 << 10, 839 ArchDefinePwr7 = 1 << 11, 840 ArchDefinePwr8 = 1 << 12, 841 ArchDefineA2 = 1 << 13, 842 ArchDefineA2q = 1 << 14 843 } ArchDefineTypes; 844 845 // Note: GCC recognizes the following additional cpus: 846 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 847 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 848 // titan, rs64. 849 bool setCPU(const std::string &Name) override { 850 bool CPUKnown = llvm::StringSwitch<bool>(Name) 851 .Case("generic", true) 852 .Case("440", true) 853 .Case("450", true) 854 .Case("601", true) 855 .Case("602", true) 856 .Case("603", true) 857 .Case("603e", true) 858 .Case("603ev", true) 859 .Case("604", true) 860 .Case("604e", true) 861 .Case("620", true) 862 .Case("630", true) 863 .Case("g3", true) 864 .Case("7400", true) 865 .Case("g4", true) 866 .Case("7450", true) 867 .Case("g4+", true) 868 .Case("750", true) 869 .Case("970", true) 870 .Case("g5", true) 871 .Case("a2", true) 872 .Case("a2q", true) 873 .Case("e500mc", true) 874 .Case("e5500", true) 875 .Case("power3", true) 876 .Case("pwr3", true) 877 .Case("power4", true) 878 .Case("pwr4", true) 879 .Case("power5", true) 880 .Case("pwr5", true) 881 .Case("power5x", true) 882 .Case("pwr5x", true) 883 .Case("power6", true) 884 .Case("pwr6", true) 885 .Case("power6x", true) 886 .Case("pwr6x", true) 887 .Case("power7", true) 888 .Case("pwr7", true) 889 .Case("power8", true) 890 .Case("pwr8", true) 891 .Case("powerpc", true) 892 .Case("ppc", true) 893 .Case("powerpc64", true) 894 .Case("ppc64", true) 895 .Case("powerpc64le", true) 896 .Case("ppc64le", true) 897 .Default(false); 898 899 if (CPUKnown) 900 CPU = Name; 901 902 return CPUKnown; 903 } 904 905 906 StringRef getABI() const override { return ABI; } 907 908 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 909 return llvm::makeArrayRef(BuiltinInfo, 910 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 911 } 912 913 bool isCLZForZeroUndef() const override { return false; } 914 915 void getTargetDefines(const LangOptions &Opts, 916 MacroBuilder &Builder) const override; 917 918 bool 919 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 920 StringRef CPU, 921 const std::vector<std::string> &FeaturesVec) const override; 922 923 bool handleTargetFeatures(std::vector<std::string> &Features, 924 DiagnosticsEngine &Diags) override; 925 bool hasFeature(StringRef Feature) const override; 926 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 927 bool Enabled) const override; 928 929 ArrayRef<const char *> getGCCRegNames() const override; 930 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 931 bool validateAsmConstraint(const char *&Name, 932 TargetInfo::ConstraintInfo &Info) const override { 933 switch (*Name) { 934 default: return false; 935 case 'O': // Zero 936 break; 937 case 'b': // Base register 938 case 'f': // Floating point register 939 Info.setAllowsRegister(); 940 break; 941 // FIXME: The following are added to allow parsing. 942 // I just took a guess at what the actions should be. 943 // Also, is more specific checking needed? I.e. specific registers? 944 case 'd': // Floating point register (containing 64-bit value) 945 case 'v': // Altivec vector register 946 Info.setAllowsRegister(); 947 break; 948 case 'w': 949 switch (Name[1]) { 950 case 'd':// VSX vector register to hold vector double data 951 case 'f':// VSX vector register to hold vector float data 952 case 's':// VSX vector register to hold scalar float data 953 case 'a':// Any VSX register 954 case 'c':// An individual CR bit 955 break; 956 default: 957 return false; 958 } 959 Info.setAllowsRegister(); 960 Name++; // Skip over 'w'. 961 break; 962 case 'h': // `MQ', `CTR', or `LINK' register 963 case 'q': // `MQ' register 964 case 'c': // `CTR' register 965 case 'l': // `LINK' register 966 case 'x': // `CR' register (condition register) number 0 967 case 'y': // `CR' register (condition register) 968 case 'z': // `XER[CA]' carry bit (part of the XER register) 969 Info.setAllowsRegister(); 970 break; 971 case 'I': // Signed 16-bit constant 972 case 'J': // Unsigned 16-bit constant shifted left 16 bits 973 // (use `L' instead for SImode constants) 974 case 'K': // Unsigned 16-bit constant 975 case 'L': // Signed 16-bit constant shifted left 16 bits 976 case 'M': // Constant larger than 31 977 case 'N': // Exact power of 2 978 case 'P': // Constant whose negation is a signed 16-bit constant 979 case 'G': // Floating point constant that can be loaded into a 980 // register with one instruction per word 981 case 'H': // Integer/Floating point constant that can be loaded 982 // into a register using three instructions 983 break; 984 case 'm': // Memory operand. Note that on PowerPC targets, m can 985 // include addresses that update the base register. It 986 // is therefore only safe to use `m' in an asm statement 987 // if that asm statement accesses the operand exactly once. 988 // The asm statement must also use `%U<opno>' as a 989 // placeholder for the "update" flag in the corresponding 990 // load or store instruction. For example: 991 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 992 // is correct but: 993 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 994 // is not. Use es rather than m if you don't want the base 995 // register to be updated. 996 case 'e': 997 if (Name[1] != 's') 998 return false; 999 // es: A "stable" memory operand; that is, one which does not 1000 // include any automodification of the base register. Unlike 1001 // `m', this constraint can be used in asm statements that 1002 // might access the operand several times, or that might not 1003 // access it at all. 1004 Info.setAllowsMemory(); 1005 Name++; // Skip over 'e'. 1006 break; 1007 case 'Q': // Memory operand that is an offset from a register (it is 1008 // usually better to use `m' or `es' in asm statements) 1009 case 'Z': // Memory operand that is an indexed or indirect from a 1010 // register (it is usually better to use `m' or `es' in 1011 // asm statements) 1012 Info.setAllowsMemory(); 1013 Info.setAllowsRegister(); 1014 break; 1015 case 'R': // AIX TOC entry 1016 case 'a': // Address operand that is an indexed or indirect from a 1017 // register (`p' is preferable for asm statements) 1018 case 'S': // Constant suitable as a 64-bit mask operand 1019 case 'T': // Constant suitable as a 32-bit mask operand 1020 case 'U': // System V Release 4 small data area reference 1021 case 't': // AND masks that can be performed by two rldic{l, r} 1022 // instructions 1023 case 'W': // Vector constant that does not require memory 1024 case 'j': // Vector constant that is all zeros. 1025 break; 1026 // End FIXME. 1027 } 1028 return true; 1029 } 1030 std::string convertConstraint(const char *&Constraint) const override { 1031 std::string R; 1032 switch (*Constraint) { 1033 case 'e': 1034 case 'w': 1035 // Two-character constraint; add "^" hint for later parsing. 1036 R = std::string("^") + std::string(Constraint, 2); 1037 Constraint++; 1038 break; 1039 default: 1040 return TargetInfo::convertConstraint(Constraint); 1041 } 1042 return R; 1043 } 1044 const char *getClobbers() const override { 1045 return ""; 1046 } 1047 int getEHDataRegisterNumber(unsigned RegNo) const override { 1048 if (RegNo == 0) return 3; 1049 if (RegNo == 1) return 4; 1050 return -1; 1051 } 1052 1053 bool hasSjLjLowering() const override { 1054 return true; 1055 } 1056 1057 bool useFloat128ManglingForLongDouble() const override { 1058 return LongDoubleWidth == 128 && 1059 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1060 getTriple().isOSBinFormatELF(); 1061 } 1062 }; 1063 1064 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1065 #define BUILTIN(ID, TYPE, ATTRS) \ 1066 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1067 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1068 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1069 #include "clang/Basic/BuiltinsPPC.def" 1070 }; 1071 1072 /// handleTargetFeatures - Perform initialization based on the user 1073 /// configured set of features. 1074 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1075 DiagnosticsEngine &Diags) { 1076 for (const auto &Feature : Features) { 1077 if (Feature == "+vsx") { 1078 HasVSX = true; 1079 } else if (Feature == "+bpermd") { 1080 HasBPERMD = true; 1081 } else if (Feature == "+extdiv") { 1082 HasExtDiv = true; 1083 } else if (Feature == "+power8-vector") { 1084 HasP8Vector = true; 1085 } else if (Feature == "+crypto") { 1086 HasP8Crypto = true; 1087 } else if (Feature == "+direct-move") { 1088 HasDirectMove = true; 1089 } else if (Feature == "+qpx") { 1090 HasQPX = true; 1091 } else if (Feature == "+htm") { 1092 HasHTM = true; 1093 } 1094 // TODO: Finish this list and add an assert that we've handled them 1095 // all. 1096 } 1097 1098 return true; 1099 } 1100 1101 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1102 /// #defines that are not tied to a specific subtarget. 1103 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1104 MacroBuilder &Builder) const { 1105 // Target identification. 1106 Builder.defineMacro("__ppc__"); 1107 Builder.defineMacro("__PPC__"); 1108 Builder.defineMacro("_ARCH_PPC"); 1109 Builder.defineMacro("__powerpc__"); 1110 Builder.defineMacro("__POWERPC__"); 1111 if (PointerWidth == 64) { 1112 Builder.defineMacro("_ARCH_PPC64"); 1113 Builder.defineMacro("__powerpc64__"); 1114 Builder.defineMacro("__ppc64__"); 1115 Builder.defineMacro("__PPC64__"); 1116 } 1117 1118 // Target properties. 1119 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1120 Builder.defineMacro("_LITTLE_ENDIAN"); 1121 } else { 1122 if (getTriple().getOS() != llvm::Triple::NetBSD && 1123 getTriple().getOS() != llvm::Triple::OpenBSD) 1124 Builder.defineMacro("_BIG_ENDIAN"); 1125 } 1126 1127 // ABI options. 1128 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1129 Builder.defineMacro("_CALL_ELF", "1"); 1130 if (ABI == "elfv2") 1131 Builder.defineMacro("_CALL_ELF", "2"); 1132 1133 // Subtarget options. 1134 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1135 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1136 1137 // FIXME: Should be controlled by command line option. 1138 if (LongDoubleWidth == 128) 1139 Builder.defineMacro("__LONG_DOUBLE_128__"); 1140 1141 if (Opts.AltiVec) { 1142 Builder.defineMacro("__VEC__", "10206"); 1143 Builder.defineMacro("__ALTIVEC__"); 1144 } 1145 1146 // CPU identification. 1147 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1148 .Case("440", ArchDefineName) 1149 .Case("450", ArchDefineName | ArchDefine440) 1150 .Case("601", ArchDefineName) 1151 .Case("602", ArchDefineName | ArchDefinePpcgr) 1152 .Case("603", ArchDefineName | ArchDefinePpcgr) 1153 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1154 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1155 .Case("604", ArchDefineName | ArchDefinePpcgr) 1156 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1157 .Case("620", ArchDefineName | ArchDefinePpcgr) 1158 .Case("630", ArchDefineName | ArchDefinePpcgr) 1159 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1160 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1161 .Case("750", ArchDefineName | ArchDefinePpcgr) 1162 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1163 | ArchDefinePpcsq) 1164 .Case("a2", ArchDefineA2) 1165 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1166 .Case("pwr3", ArchDefinePpcgr) 1167 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1168 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1169 | ArchDefinePpcsq) 1170 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1171 | ArchDefinePpcgr | ArchDefinePpcsq) 1172 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1173 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1174 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1175 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1176 | ArchDefinePpcsq) 1177 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1178 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1179 | ArchDefinePpcgr | ArchDefinePpcsq) 1180 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1181 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1182 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1183 .Case("power3", ArchDefinePpcgr) 1184 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1185 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1186 | ArchDefinePpcsq) 1187 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1188 | ArchDefinePpcgr | ArchDefinePpcsq) 1189 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1190 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1191 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1192 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1193 | ArchDefinePpcsq) 1194 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1195 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1196 | ArchDefinePpcgr | ArchDefinePpcsq) 1197 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1198 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1199 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1200 .Default(ArchDefineNone); 1201 1202 if (defs & ArchDefineName) 1203 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1204 if (defs & ArchDefinePpcgr) 1205 Builder.defineMacro("_ARCH_PPCGR"); 1206 if (defs & ArchDefinePpcsq) 1207 Builder.defineMacro("_ARCH_PPCSQ"); 1208 if (defs & ArchDefine440) 1209 Builder.defineMacro("_ARCH_440"); 1210 if (defs & ArchDefine603) 1211 Builder.defineMacro("_ARCH_603"); 1212 if (defs & ArchDefine604) 1213 Builder.defineMacro("_ARCH_604"); 1214 if (defs & ArchDefinePwr4) 1215 Builder.defineMacro("_ARCH_PWR4"); 1216 if (defs & ArchDefinePwr5) 1217 Builder.defineMacro("_ARCH_PWR5"); 1218 if (defs & ArchDefinePwr5x) 1219 Builder.defineMacro("_ARCH_PWR5X"); 1220 if (defs & ArchDefinePwr6) 1221 Builder.defineMacro("_ARCH_PWR6"); 1222 if (defs & ArchDefinePwr6x) 1223 Builder.defineMacro("_ARCH_PWR6X"); 1224 if (defs & ArchDefinePwr7) 1225 Builder.defineMacro("_ARCH_PWR7"); 1226 if (defs & ArchDefinePwr8) 1227 Builder.defineMacro("_ARCH_PWR8"); 1228 if (defs & ArchDefineA2) 1229 Builder.defineMacro("_ARCH_A2"); 1230 if (defs & ArchDefineA2q) { 1231 Builder.defineMacro("_ARCH_A2Q"); 1232 Builder.defineMacro("_ARCH_QP"); 1233 } 1234 1235 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1236 Builder.defineMacro("__bg__"); 1237 Builder.defineMacro("__THW_BLUEGENE__"); 1238 Builder.defineMacro("__bgq__"); 1239 Builder.defineMacro("__TOS_BGQ__"); 1240 } 1241 1242 if (HasVSX) 1243 Builder.defineMacro("__VSX__"); 1244 if (HasP8Vector) 1245 Builder.defineMacro("__POWER8_VECTOR__"); 1246 if (HasP8Crypto) 1247 Builder.defineMacro("__CRYPTO__"); 1248 if (HasHTM) 1249 Builder.defineMacro("__HTM__"); 1250 1251 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1252 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1253 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1254 if (PointerWidth == 64) 1255 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1256 1257 // FIXME: The following are not yet generated here by Clang, but are 1258 // generated by GCC: 1259 // 1260 // _SOFT_FLOAT_ 1261 // __RECIP_PRECISION__ 1262 // __APPLE_ALTIVEC__ 1263 // __RECIP__ 1264 // __RECIPF__ 1265 // __RSQRTE__ 1266 // __RSQRTEF__ 1267 // _SOFT_DOUBLE_ 1268 // __NO_LWSYNC__ 1269 // __HAVE_BSWAP__ 1270 // __LONGDOUBLE128 1271 // __CMODEL_MEDIUM__ 1272 // __CMODEL_LARGE__ 1273 // _CALL_SYSV 1274 // _CALL_DARWIN 1275 // __NO_FPRS__ 1276 } 1277 1278 // Handle explicit options being passed to the compiler here: if we've 1279 // explicitly turned off vsx and turned on power8-vector or direct-move then 1280 // go ahead and error since the customer has expressed a somewhat incompatible 1281 // set of options. 1282 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1283 const std::vector<std::string> &FeaturesVec) { 1284 1285 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1286 FeaturesVec.end()) { 1287 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1288 FeaturesVec.end()) { 1289 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1290 << "-mno-vsx"; 1291 return false; 1292 } 1293 1294 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1295 FeaturesVec.end()) { 1296 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1297 << "-mno-vsx"; 1298 return false; 1299 } 1300 } 1301 1302 return true; 1303 } 1304 1305 bool PPCTargetInfo::initFeatureMap( 1306 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1307 const std::vector<std::string> &FeaturesVec) const { 1308 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1309 .Case("7400", true) 1310 .Case("g4", true) 1311 .Case("7450", true) 1312 .Case("g4+", true) 1313 .Case("970", true) 1314 .Case("g5", true) 1315 .Case("pwr6", true) 1316 .Case("pwr7", true) 1317 .Case("pwr8", true) 1318 .Case("ppc64", true) 1319 .Case("ppc64le", true) 1320 .Default(false); 1321 1322 Features["qpx"] = (CPU == "a2q"); 1323 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1324 .Case("ppc64le", true) 1325 .Case("pwr8", true) 1326 .Default(false); 1327 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1328 .Case("ppc64le", true) 1329 .Case("pwr8", true) 1330 .Default(false); 1331 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1332 .Case("ppc64le", true) 1333 .Case("pwr8", true) 1334 .Case("pwr7", true) 1335 .Default(false); 1336 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1337 .Case("ppc64le", true) 1338 .Case("pwr8", true) 1339 .Case("pwr7", true) 1340 .Default(false); 1341 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1342 .Case("ppc64le", true) 1343 .Case("pwr8", true) 1344 .Default(false); 1345 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1346 .Case("ppc64le", true) 1347 .Case("pwr8", true) 1348 .Case("pwr7", true) 1349 .Default(false); 1350 1351 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1352 return false; 1353 1354 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1355 } 1356 1357 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1358 return llvm::StringSwitch<bool>(Feature) 1359 .Case("powerpc", true) 1360 .Case("vsx", HasVSX) 1361 .Case("power8-vector", HasP8Vector) 1362 .Case("crypto", HasP8Crypto) 1363 .Case("direct-move", HasDirectMove) 1364 .Case("qpx", HasQPX) 1365 .Case("htm", HasHTM) 1366 .Case("bpermd", HasBPERMD) 1367 .Case("extdiv", HasExtDiv) 1368 .Default(false); 1369 } 1370 1371 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1372 StringRef Name, bool Enabled) const { 1373 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1374 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1375 // incompatible options. 1376 if (Enabled) { 1377 if (Name == "vsx") { 1378 Features[Name] = true; 1379 } else if (Name == "direct-move") { 1380 Features[Name] = Features["vsx"] = true; 1381 } else if (Name == "power8-vector") { 1382 Features[Name] = Features["vsx"] = true; 1383 } else { 1384 Features[Name] = true; 1385 } 1386 } else { 1387 if (Name == "vsx") { 1388 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1389 false; 1390 } else { 1391 Features[Name] = false; 1392 } 1393 } 1394 } 1395 1396 const char * const PPCTargetInfo::GCCRegNames[] = { 1397 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1398 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1399 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1400 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1401 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1402 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1403 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1404 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1405 "mq", "lr", "ctr", "ap", 1406 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1407 "xer", 1408 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1409 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1410 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1411 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1412 "vrsave", "vscr", 1413 "spe_acc", "spefscr", 1414 "sfp" 1415 }; 1416 1417 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1418 return llvm::makeArrayRef(GCCRegNames); 1419 } 1420 1421 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1422 // While some of these aliases do map to different registers 1423 // they still share the same register name. 1424 { { "0" }, "r0" }, 1425 { { "1"}, "r1" }, 1426 { { "2" }, "r2" }, 1427 { { "3" }, "r3" }, 1428 { { "4" }, "r4" }, 1429 { { "5" }, "r5" }, 1430 { { "6" }, "r6" }, 1431 { { "7" }, "r7" }, 1432 { { "8" }, "r8" }, 1433 { { "9" }, "r9" }, 1434 { { "10" }, "r10" }, 1435 { { "11" }, "r11" }, 1436 { { "12" }, "r12" }, 1437 { { "13" }, "r13" }, 1438 { { "14" }, "r14" }, 1439 { { "15" }, "r15" }, 1440 { { "16" }, "r16" }, 1441 { { "17" }, "r17" }, 1442 { { "18" }, "r18" }, 1443 { { "19" }, "r19" }, 1444 { { "20" }, "r20" }, 1445 { { "21" }, "r21" }, 1446 { { "22" }, "r22" }, 1447 { { "23" }, "r23" }, 1448 { { "24" }, "r24" }, 1449 { { "25" }, "r25" }, 1450 { { "26" }, "r26" }, 1451 { { "27" }, "r27" }, 1452 { { "28" }, "r28" }, 1453 { { "29" }, "r29" }, 1454 { { "30" }, "r30" }, 1455 { { "31" }, "r31" }, 1456 { { "fr0" }, "f0" }, 1457 { { "fr1" }, "f1" }, 1458 { { "fr2" }, "f2" }, 1459 { { "fr3" }, "f3" }, 1460 { { "fr4" }, "f4" }, 1461 { { "fr5" }, "f5" }, 1462 { { "fr6" }, "f6" }, 1463 { { "fr7" }, "f7" }, 1464 { { "fr8" }, "f8" }, 1465 { { "fr9" }, "f9" }, 1466 { { "fr10" }, "f10" }, 1467 { { "fr11" }, "f11" }, 1468 { { "fr12" }, "f12" }, 1469 { { "fr13" }, "f13" }, 1470 { { "fr14" }, "f14" }, 1471 { { "fr15" }, "f15" }, 1472 { { "fr16" }, "f16" }, 1473 { { "fr17" }, "f17" }, 1474 { { "fr18" }, "f18" }, 1475 { { "fr19" }, "f19" }, 1476 { { "fr20" }, "f20" }, 1477 { { "fr21" }, "f21" }, 1478 { { "fr22" }, "f22" }, 1479 { { "fr23" }, "f23" }, 1480 { { "fr24" }, "f24" }, 1481 { { "fr25" }, "f25" }, 1482 { { "fr26" }, "f26" }, 1483 { { "fr27" }, "f27" }, 1484 { { "fr28" }, "f28" }, 1485 { { "fr29" }, "f29" }, 1486 { { "fr30" }, "f30" }, 1487 { { "fr31" }, "f31" }, 1488 { { "cc" }, "cr0" }, 1489 }; 1490 1491 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1492 return llvm::makeArrayRef(GCCRegAliases); 1493 } 1494 1495 class PPC32TargetInfo : public PPCTargetInfo { 1496 public: 1497 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1498 DataLayoutString = "E-m:e-p:32:32-i64:64-n32"; 1499 1500 switch (getTriple().getOS()) { 1501 case llvm::Triple::Linux: 1502 case llvm::Triple::FreeBSD: 1503 case llvm::Triple::NetBSD: 1504 SizeType = UnsignedInt; 1505 PtrDiffType = SignedInt; 1506 IntPtrType = SignedInt; 1507 break; 1508 default: 1509 break; 1510 } 1511 1512 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1513 LongDoubleWidth = LongDoubleAlign = 64; 1514 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1515 } 1516 1517 // PPC32 supports atomics up to 4 bytes. 1518 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1519 } 1520 1521 BuiltinVaListKind getBuiltinVaListKind() const override { 1522 // This is the ELF definition, and is overridden by the Darwin sub-target 1523 return TargetInfo::PowerABIBuiltinVaList; 1524 } 1525 }; 1526 1527 // Note: ABI differences may eventually require us to have a separate 1528 // TargetInfo for little endian. 1529 class PPC64TargetInfo : public PPCTargetInfo { 1530 public: 1531 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1532 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1533 IntMaxType = SignedLong; 1534 Int64Type = SignedLong; 1535 1536 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1537 DataLayoutString = "e-m:e-i64:64-n32:64"; 1538 ABI = "elfv2"; 1539 } else { 1540 DataLayoutString = "E-m:e-i64:64-n32:64"; 1541 ABI = "elfv1"; 1542 } 1543 1544 switch (getTriple().getOS()) { 1545 case llvm::Triple::FreeBSD: 1546 LongDoubleWidth = LongDoubleAlign = 64; 1547 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1548 break; 1549 case llvm::Triple::NetBSD: 1550 IntMaxType = SignedLongLong; 1551 Int64Type = SignedLongLong; 1552 break; 1553 default: 1554 break; 1555 } 1556 1557 // PPC64 supports atomics up to 8 bytes. 1558 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1559 } 1560 BuiltinVaListKind getBuiltinVaListKind() const override { 1561 return TargetInfo::CharPtrBuiltinVaList; 1562 } 1563 // PPC64 Linux-specific ABI options. 1564 bool setABI(const std::string &Name) override { 1565 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1566 ABI = Name; 1567 return true; 1568 } 1569 return false; 1570 } 1571 }; 1572 1573 class DarwinPPC32TargetInfo : 1574 public DarwinTargetInfo<PPC32TargetInfo> { 1575 public: 1576 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1577 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1578 HasAlignMac68kSupport = true; 1579 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1580 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1581 LongLongAlign = 32; 1582 SuitableAlign = 128; 1583 DataLayoutString = "E-m:o-p:32:32-f64:32:64-n32"; 1584 } 1585 BuiltinVaListKind getBuiltinVaListKind() const override { 1586 return TargetInfo::CharPtrBuiltinVaList; 1587 } 1588 }; 1589 1590 class DarwinPPC64TargetInfo : 1591 public DarwinTargetInfo<PPC64TargetInfo> { 1592 public: 1593 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1594 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1595 HasAlignMac68kSupport = true; 1596 SuitableAlign = 128; 1597 DataLayoutString = "E-m:o-i64:64-n32:64"; 1598 } 1599 }; 1600 1601 static const unsigned NVPTXAddrSpaceMap[] = { 1602 1, // opencl_global 1603 3, // opencl_local 1604 4, // opencl_constant 1605 // FIXME: generic has to be added to the target 1606 0, // opencl_generic 1607 1, // cuda_device 1608 4, // cuda_constant 1609 3, // cuda_shared 1610 }; 1611 1612 class NVPTXTargetInfo : public TargetInfo { 1613 static const char *const GCCRegNames[]; 1614 static const Builtin::Info BuiltinInfo[]; 1615 1616 // The GPU profiles supported by the NVPTX backend 1617 enum GPUKind { 1618 GK_NONE, 1619 GK_SM20, 1620 GK_SM21, 1621 GK_SM30, 1622 GK_SM35, 1623 GK_SM37, 1624 } GPU; 1625 1626 public: 1627 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1628 BigEndian = false; 1629 TLSSupported = false; 1630 LongWidth = LongAlign = 64; 1631 AddrSpaceMap = &NVPTXAddrSpaceMap; 1632 UseAddrSpaceMapMangling = true; 1633 // Define available target features 1634 // These must be defined in sorted order! 1635 NoAsmVariants = true; 1636 // Set the default GPU to sm20 1637 GPU = GK_SM20; 1638 } 1639 void getTargetDefines(const LangOptions &Opts, 1640 MacroBuilder &Builder) const override { 1641 Builder.defineMacro("__PTX__"); 1642 Builder.defineMacro("__NVPTX__"); 1643 if (Opts.CUDAIsDevice) { 1644 // Set __CUDA_ARCH__ for the GPU specified. 1645 std::string CUDAArchCode; 1646 switch (GPU) { 1647 case GK_SM20: 1648 CUDAArchCode = "200"; 1649 break; 1650 case GK_SM21: 1651 CUDAArchCode = "210"; 1652 break; 1653 case GK_SM30: 1654 CUDAArchCode = "300"; 1655 break; 1656 case GK_SM35: 1657 CUDAArchCode = "350"; 1658 break; 1659 case GK_SM37: 1660 CUDAArchCode = "370"; 1661 break; 1662 default: 1663 llvm_unreachable("Unhandled target CPU"); 1664 } 1665 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1666 } 1667 } 1668 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1669 return llvm::makeArrayRef(BuiltinInfo, 1670 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1671 } 1672 bool hasFeature(StringRef Feature) const override { 1673 return Feature == "ptx" || Feature == "nvptx"; 1674 } 1675 1676 ArrayRef<const char *> getGCCRegNames() const override; 1677 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1678 // No aliases. 1679 return None; 1680 } 1681 bool validateAsmConstraint(const char *&Name, 1682 TargetInfo::ConstraintInfo &Info) const override { 1683 switch (*Name) { 1684 default: 1685 return false; 1686 case 'c': 1687 case 'h': 1688 case 'r': 1689 case 'l': 1690 case 'f': 1691 case 'd': 1692 Info.setAllowsRegister(); 1693 return true; 1694 } 1695 } 1696 const char *getClobbers() const override { 1697 // FIXME: Is this really right? 1698 return ""; 1699 } 1700 BuiltinVaListKind getBuiltinVaListKind() const override { 1701 // FIXME: implement 1702 return TargetInfo::CharPtrBuiltinVaList; 1703 } 1704 bool setCPU(const std::string &Name) override { 1705 GPU = llvm::StringSwitch<GPUKind>(Name) 1706 .Case("sm_20", GK_SM20) 1707 .Case("sm_21", GK_SM21) 1708 .Case("sm_30", GK_SM30) 1709 .Case("sm_35", GK_SM35) 1710 .Case("sm_37", GK_SM37) 1711 .Default(GK_NONE); 1712 1713 return GPU != GK_NONE; 1714 } 1715 }; 1716 1717 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1718 #define BUILTIN(ID, TYPE, ATTRS) \ 1719 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1720 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1721 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1722 #include "clang/Basic/BuiltinsNVPTX.def" 1723 }; 1724 1725 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1726 1727 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1728 return llvm::makeArrayRef(GCCRegNames); 1729 } 1730 1731 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1732 public: 1733 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1734 LongWidth = LongAlign = 32; 1735 PointerWidth = PointerAlign = 32; 1736 SizeType = TargetInfo::UnsignedInt; 1737 PtrDiffType = TargetInfo::SignedInt; 1738 IntPtrType = TargetInfo::SignedInt; 1739 DataLayoutString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1740 } 1741 }; 1742 1743 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1744 public: 1745 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1746 PointerWidth = PointerAlign = 64; 1747 SizeType = TargetInfo::UnsignedLong; 1748 PtrDiffType = TargetInfo::SignedLong; 1749 IntPtrType = TargetInfo::SignedLong; 1750 DataLayoutString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1751 } 1752 }; 1753 1754 static const unsigned AMDGPUAddrSpaceMap[] = { 1755 1, // opencl_global 1756 3, // opencl_local 1757 2, // opencl_constant 1758 4, // opencl_generic 1759 1, // cuda_device 1760 2, // cuda_constant 1761 3 // cuda_shared 1762 }; 1763 1764 // If you edit the description strings, make sure you update 1765 // getPointerWidthV(). 1766 1767 static const char *const DataLayoutStringR600 = 1768 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1769 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1770 1771 static const char *const DataLayoutStringR600DoubleOps = 1772 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1773 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1774 1775 static const char *const DataLayoutStringSI = 1776 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1777 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1778 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1779 1780 class AMDGPUTargetInfo : public TargetInfo { 1781 static const Builtin::Info BuiltinInfo[]; 1782 static const char * const GCCRegNames[]; 1783 1784 /// \brief The GPU profiles supported by the AMDGPU target. 1785 enum GPUKind { 1786 GK_NONE, 1787 GK_R600, 1788 GK_R600_DOUBLE_OPS, 1789 GK_R700, 1790 GK_R700_DOUBLE_OPS, 1791 GK_EVERGREEN, 1792 GK_EVERGREEN_DOUBLE_OPS, 1793 GK_NORTHERN_ISLANDS, 1794 GK_CAYMAN, 1795 GK_SOUTHERN_ISLANDS, 1796 GK_SEA_ISLANDS, 1797 GK_VOLCANIC_ISLANDS 1798 } GPU; 1799 1800 bool hasFP64:1; 1801 bool hasFMAF:1; 1802 bool hasLDEXPF:1; 1803 1804 public: 1805 AMDGPUTargetInfo(const llvm::Triple &Triple) 1806 : TargetInfo(Triple) { 1807 1808 if (Triple.getArch() == llvm::Triple::amdgcn) { 1809 DataLayoutString = DataLayoutStringSI; 1810 GPU = GK_SOUTHERN_ISLANDS; 1811 hasFP64 = true; 1812 hasFMAF = true; 1813 hasLDEXPF = true; 1814 } else { 1815 DataLayoutString = DataLayoutStringR600; 1816 GPU = GK_R600; 1817 hasFP64 = false; 1818 hasFMAF = false; 1819 hasLDEXPF = false; 1820 } 1821 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1822 UseAddrSpaceMapMangling = true; 1823 } 1824 1825 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1826 if (GPU <= GK_CAYMAN) 1827 return 32; 1828 1829 switch(AddrSpace) { 1830 default: 1831 return 64; 1832 case 0: 1833 case 3: 1834 case 5: 1835 return 32; 1836 } 1837 } 1838 1839 const char * getClobbers() const override { 1840 return ""; 1841 } 1842 1843 ArrayRef<const char *> getGCCRegNames() const override; 1844 1845 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1846 return None; 1847 } 1848 1849 bool validateAsmConstraint(const char *&Name, 1850 TargetInfo::ConstraintInfo &Info) const override { 1851 switch (*Name) { 1852 default: break; 1853 case 'v': // vgpr 1854 case 's': // sgpr 1855 Info.setAllowsRegister(); 1856 return true; 1857 } 1858 return false; 1859 } 1860 1861 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1862 return llvm::makeArrayRef(BuiltinInfo, 1863 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 1864 } 1865 1866 void getTargetDefines(const LangOptions &Opts, 1867 MacroBuilder &Builder) const override { 1868 if (getTriple().getArch() == llvm::Triple::amdgcn) 1869 Builder.defineMacro("__AMDGCN__"); 1870 else 1871 Builder.defineMacro("__R600__"); 1872 1873 if (hasFMAF) 1874 Builder.defineMacro("__HAS_FMAF__"); 1875 if (hasLDEXPF) 1876 Builder.defineMacro("__HAS_LDEXPF__"); 1877 if (hasFP64 && Opts.OpenCL) 1878 Builder.defineMacro("cl_khr_fp64"); 1879 if (Opts.OpenCL) { 1880 if (GPU >= GK_NORTHERN_ISLANDS) { 1881 Builder.defineMacro("cl_khr_byte_addressable_store"); 1882 Builder.defineMacro("cl_khr_global_int32_base_atomics"); 1883 Builder.defineMacro("cl_khr_global_int32_extended_atomics"); 1884 Builder.defineMacro("cl_khr_local_int32_base_atomics"); 1885 Builder.defineMacro("cl_khr_local_int32_extended_atomics"); 1886 } 1887 } 1888 } 1889 1890 BuiltinVaListKind getBuiltinVaListKind() const override { 1891 return TargetInfo::CharPtrBuiltinVaList; 1892 } 1893 1894 bool setCPU(const std::string &Name) override { 1895 GPU = llvm::StringSwitch<GPUKind>(Name) 1896 .Case("r600" , GK_R600) 1897 .Case("rv610", GK_R600) 1898 .Case("rv620", GK_R600) 1899 .Case("rv630", GK_R600) 1900 .Case("rv635", GK_R600) 1901 .Case("rs780", GK_R600) 1902 .Case("rs880", GK_R600) 1903 .Case("rv670", GK_R600_DOUBLE_OPS) 1904 .Case("rv710", GK_R700) 1905 .Case("rv730", GK_R700) 1906 .Case("rv740", GK_R700_DOUBLE_OPS) 1907 .Case("rv770", GK_R700_DOUBLE_OPS) 1908 .Case("palm", GK_EVERGREEN) 1909 .Case("cedar", GK_EVERGREEN) 1910 .Case("sumo", GK_EVERGREEN) 1911 .Case("sumo2", GK_EVERGREEN) 1912 .Case("redwood", GK_EVERGREEN) 1913 .Case("juniper", GK_EVERGREEN) 1914 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1915 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1916 .Case("barts", GK_NORTHERN_ISLANDS) 1917 .Case("turks", GK_NORTHERN_ISLANDS) 1918 .Case("caicos", GK_NORTHERN_ISLANDS) 1919 .Case("cayman", GK_CAYMAN) 1920 .Case("aruba", GK_CAYMAN) 1921 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1922 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1923 .Case("verde", GK_SOUTHERN_ISLANDS) 1924 .Case("oland", GK_SOUTHERN_ISLANDS) 1925 .Case("hainan", GK_SOUTHERN_ISLANDS) 1926 .Case("bonaire", GK_SEA_ISLANDS) 1927 .Case("kabini", GK_SEA_ISLANDS) 1928 .Case("kaveri", GK_SEA_ISLANDS) 1929 .Case("hawaii", GK_SEA_ISLANDS) 1930 .Case("mullins", GK_SEA_ISLANDS) 1931 .Case("tonga", GK_VOLCANIC_ISLANDS) 1932 .Case("iceland", GK_VOLCANIC_ISLANDS) 1933 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1934 .Case("fiji", GK_VOLCANIC_ISLANDS) 1935 .Case("stoney", GK_VOLCANIC_ISLANDS) 1936 .Default(GK_NONE); 1937 1938 if (GPU == GK_NONE) { 1939 return false; 1940 } 1941 1942 // Set the correct data layout 1943 switch (GPU) { 1944 case GK_NONE: 1945 case GK_R600: 1946 case GK_R700: 1947 case GK_EVERGREEN: 1948 case GK_NORTHERN_ISLANDS: 1949 DataLayoutString = DataLayoutStringR600; 1950 hasFP64 = false; 1951 hasFMAF = false; 1952 hasLDEXPF = false; 1953 break; 1954 case GK_R600_DOUBLE_OPS: 1955 case GK_R700_DOUBLE_OPS: 1956 case GK_EVERGREEN_DOUBLE_OPS: 1957 case GK_CAYMAN: 1958 DataLayoutString = DataLayoutStringR600DoubleOps; 1959 hasFP64 = true; 1960 hasFMAF = true; 1961 hasLDEXPF = false; 1962 break; 1963 case GK_SOUTHERN_ISLANDS: 1964 case GK_SEA_ISLANDS: 1965 case GK_VOLCANIC_ISLANDS: 1966 DataLayoutString = DataLayoutStringSI; 1967 hasFP64 = true; 1968 hasFMAF = true; 1969 hasLDEXPF = true; 1970 break; 1971 } 1972 1973 return true; 1974 } 1975 }; 1976 1977 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1978 #define BUILTIN(ID, TYPE, ATTRS) \ 1979 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1980 #include "clang/Basic/BuiltinsAMDGPU.def" 1981 }; 1982 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1983 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1984 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1985 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1986 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1987 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1988 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1989 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1990 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1991 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1992 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1993 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1994 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1995 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1996 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1997 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1998 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1999 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2000 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2001 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2002 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2003 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2004 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2005 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2006 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2007 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2008 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2009 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2010 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2011 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2012 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2013 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2014 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2015 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2016 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2017 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2018 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2019 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2020 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2021 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2022 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2023 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2024 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2025 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2026 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2027 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2028 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2029 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2030 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127" 2031 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2032 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2033 }; 2034 2035 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2036 return llvm::makeArrayRef(GCCRegNames); 2037 } 2038 2039 // Namespace for x86 abstract base class 2040 const Builtin::Info BuiltinInfo[] = { 2041 #define BUILTIN(ID, TYPE, ATTRS) \ 2042 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2043 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2044 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2045 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2046 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2047 #include "clang/Basic/BuiltinsX86.def" 2048 }; 2049 2050 static const char* const GCCRegNames[] = { 2051 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2052 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2053 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2054 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2055 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2056 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2057 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2058 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2059 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2060 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2061 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2062 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2063 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2064 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2065 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2066 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2067 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2068 }; 2069 2070 const TargetInfo::AddlRegName AddlRegNames[] = { 2071 { { "al", "ah", "eax", "rax" }, 0 }, 2072 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2073 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2074 { { "dl", "dh", "edx", "rdx" }, 1 }, 2075 { { "esi", "rsi" }, 4 }, 2076 { { "edi", "rdi" }, 5 }, 2077 { { "esp", "rsp" }, 7 }, 2078 { { "ebp", "rbp" }, 6 }, 2079 { { "r8d", "r8w", "r8b" }, 38 }, 2080 { { "r9d", "r9w", "r9b" }, 39 }, 2081 { { "r10d", "r10w", "r10b" }, 40 }, 2082 { { "r11d", "r11w", "r11b" }, 41 }, 2083 { { "r12d", "r12w", "r12b" }, 42 }, 2084 { { "r13d", "r13w", "r13b" }, 43 }, 2085 { { "r14d", "r14w", "r14b" }, 44 }, 2086 { { "r15d", "r15w", "r15b" }, 45 }, 2087 }; 2088 2089 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2090 // most of the implementation can be shared. 2091 class X86TargetInfo : public TargetInfo { 2092 enum X86SSEEnum { 2093 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2094 } SSELevel = NoSSE; 2095 enum MMX3DNowEnum { 2096 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2097 } MMX3DNowLevel = NoMMX3DNow; 2098 enum XOPEnum { 2099 NoXOP, 2100 SSE4A, 2101 FMA4, 2102 XOP 2103 } XOPLevel = NoXOP; 2104 2105 bool HasAES = false; 2106 bool HasPCLMUL = false; 2107 bool HasLZCNT = false; 2108 bool HasRDRND = false; 2109 bool HasFSGSBASE = false; 2110 bool HasBMI = false; 2111 bool HasBMI2 = false; 2112 bool HasPOPCNT = false; 2113 bool HasRTM = false; 2114 bool HasPRFCHW = false; 2115 bool HasRDSEED = false; 2116 bool HasADX = false; 2117 bool HasTBM = false; 2118 bool HasFMA = false; 2119 bool HasF16C = false; 2120 bool HasAVX512CD = false; 2121 bool HasAVX512ER = false; 2122 bool HasAVX512PF = false; 2123 bool HasAVX512DQ = false; 2124 bool HasAVX512BW = false; 2125 bool HasAVX512VL = false; 2126 bool HasAVX512VBMI = false; 2127 bool HasAVX512IFMA = false; 2128 bool HasSHA = false; 2129 bool HasMPX = false; 2130 bool HasSGX = false; 2131 bool HasCX16 = false; 2132 bool HasFXSR = false; 2133 bool HasXSAVE = false; 2134 bool HasXSAVEOPT = false; 2135 bool HasXSAVEC = false; 2136 bool HasXSAVES = false; 2137 bool HasPKU = false; 2138 bool HasCLFLUSHOPT = false; 2139 bool HasPCOMMIT = false; 2140 bool HasCLWB = false; 2141 bool HasUMIP = false; 2142 bool HasMOVBE = false; 2143 bool HasPREFETCHWT1 = false; 2144 2145 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2146 /// 2147 /// Each enumeration represents a particular CPU supported by Clang. These 2148 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2149 enum CPUKind { 2150 CK_Generic, 2151 2152 /// \name i386 2153 /// i386-generation processors. 2154 //@{ 2155 CK_i386, 2156 //@} 2157 2158 /// \name i486 2159 /// i486-generation processors. 2160 //@{ 2161 CK_i486, 2162 CK_WinChipC6, 2163 CK_WinChip2, 2164 CK_C3, 2165 //@} 2166 2167 /// \name i586 2168 /// i586-generation processors, P5 microarchitecture based. 2169 //@{ 2170 CK_i586, 2171 CK_Pentium, 2172 CK_PentiumMMX, 2173 //@} 2174 2175 /// \name i686 2176 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2177 //@{ 2178 CK_i686, 2179 CK_PentiumPro, 2180 CK_Pentium2, 2181 CK_Pentium3, 2182 CK_Pentium3M, 2183 CK_PentiumM, 2184 CK_C3_2, 2185 2186 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2187 /// Clang however has some logic to suport this. 2188 // FIXME: Warn, deprecate, and potentially remove this. 2189 CK_Yonah, 2190 //@} 2191 2192 /// \name Netburst 2193 /// Netburst microarchitecture based processors. 2194 //@{ 2195 CK_Pentium4, 2196 CK_Pentium4M, 2197 CK_Prescott, 2198 CK_Nocona, 2199 //@} 2200 2201 /// \name Core 2202 /// Core microarchitecture based processors. 2203 //@{ 2204 CK_Core2, 2205 2206 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2207 /// codename which GCC no longer accepts as an option to -march, but Clang 2208 /// has some logic for recognizing it. 2209 // FIXME: Warn, deprecate, and potentially remove this. 2210 CK_Penryn, 2211 //@} 2212 2213 /// \name Atom 2214 /// Atom processors 2215 //@{ 2216 CK_Bonnell, 2217 CK_Silvermont, 2218 //@} 2219 2220 /// \name Nehalem 2221 /// Nehalem microarchitecture based processors. 2222 CK_Nehalem, 2223 2224 /// \name Westmere 2225 /// Westmere microarchitecture based processors. 2226 CK_Westmere, 2227 2228 /// \name Sandy Bridge 2229 /// Sandy Bridge microarchitecture based processors. 2230 CK_SandyBridge, 2231 2232 /// \name Ivy Bridge 2233 /// Ivy Bridge microarchitecture based processors. 2234 CK_IvyBridge, 2235 2236 /// \name Haswell 2237 /// Haswell microarchitecture based processors. 2238 CK_Haswell, 2239 2240 /// \name Broadwell 2241 /// Broadwell microarchitecture based processors. 2242 CK_Broadwell, 2243 2244 /// \name Skylake Client 2245 /// Skylake client microarchitecture based processors. 2246 CK_SkylakeClient, 2247 2248 /// \name Skylake Server 2249 /// Skylake server microarchitecture based processors. 2250 CK_SkylakeServer, 2251 2252 /// \name Cannonlake Client 2253 /// Cannonlake client microarchitecture based processors. 2254 CK_Cannonlake, 2255 2256 /// \name Knights Landing 2257 /// Knights Landing processor. 2258 CK_KNL, 2259 2260 /// \name K6 2261 /// K6 architecture processors. 2262 //@{ 2263 CK_K6, 2264 CK_K6_2, 2265 CK_K6_3, 2266 //@} 2267 2268 /// \name K7 2269 /// K7 architecture processors. 2270 //@{ 2271 CK_Athlon, 2272 CK_AthlonThunderbird, 2273 CK_Athlon4, 2274 CK_AthlonXP, 2275 CK_AthlonMP, 2276 //@} 2277 2278 /// \name K8 2279 /// K8 architecture processors. 2280 //@{ 2281 CK_Athlon64, 2282 CK_Athlon64SSE3, 2283 CK_AthlonFX, 2284 CK_K8, 2285 CK_K8SSE3, 2286 CK_Opteron, 2287 CK_OpteronSSE3, 2288 CK_AMDFAM10, 2289 //@} 2290 2291 /// \name Bobcat 2292 /// Bobcat architecture processors. 2293 //@{ 2294 CK_BTVER1, 2295 CK_BTVER2, 2296 //@} 2297 2298 /// \name Bulldozer 2299 /// Bulldozer architecture processors. 2300 //@{ 2301 CK_BDVER1, 2302 CK_BDVER2, 2303 CK_BDVER3, 2304 CK_BDVER4, 2305 //@} 2306 2307 /// This specification is deprecated and will be removed in the future. 2308 /// Users should prefer \see CK_K8. 2309 // FIXME: Warn on this when the CPU is set to it. 2310 //@{ 2311 CK_x86_64, 2312 //@} 2313 2314 /// \name Geode 2315 /// Geode processors. 2316 //@{ 2317 CK_Geode 2318 //@} 2319 } CPU = CK_Generic; 2320 2321 CPUKind getCPUKind(StringRef CPU) const { 2322 return llvm::StringSwitch<CPUKind>(CPU) 2323 .Case("i386", CK_i386) 2324 .Case("i486", CK_i486) 2325 .Case("winchip-c6", CK_WinChipC6) 2326 .Case("winchip2", CK_WinChip2) 2327 .Case("c3", CK_C3) 2328 .Case("i586", CK_i586) 2329 .Case("pentium", CK_Pentium) 2330 .Case("pentium-mmx", CK_PentiumMMX) 2331 .Case("i686", CK_i686) 2332 .Case("pentiumpro", CK_PentiumPro) 2333 .Case("pentium2", CK_Pentium2) 2334 .Case("pentium3", CK_Pentium3) 2335 .Case("pentium3m", CK_Pentium3M) 2336 .Case("pentium-m", CK_PentiumM) 2337 .Case("c3-2", CK_C3_2) 2338 .Case("yonah", CK_Yonah) 2339 .Case("pentium4", CK_Pentium4) 2340 .Case("pentium4m", CK_Pentium4M) 2341 .Case("prescott", CK_Prescott) 2342 .Case("nocona", CK_Nocona) 2343 .Case("core2", CK_Core2) 2344 .Case("penryn", CK_Penryn) 2345 .Case("bonnell", CK_Bonnell) 2346 .Case("atom", CK_Bonnell) // Legacy name. 2347 .Case("silvermont", CK_Silvermont) 2348 .Case("slm", CK_Silvermont) // Legacy name. 2349 .Case("nehalem", CK_Nehalem) 2350 .Case("corei7", CK_Nehalem) // Legacy name. 2351 .Case("westmere", CK_Westmere) 2352 .Case("sandybridge", CK_SandyBridge) 2353 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2354 .Case("ivybridge", CK_IvyBridge) 2355 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2356 .Case("haswell", CK_Haswell) 2357 .Case("core-avx2", CK_Haswell) // Legacy name. 2358 .Case("broadwell", CK_Broadwell) 2359 .Case("skylake", CK_SkylakeClient) 2360 .Case("skylake-avx512", CK_SkylakeServer) 2361 .Case("skx", CK_SkylakeServer) // Legacy name. 2362 .Case("cannonlake", CK_Cannonlake) 2363 .Case("knl", CK_KNL) 2364 .Case("k6", CK_K6) 2365 .Case("k6-2", CK_K6_2) 2366 .Case("k6-3", CK_K6_3) 2367 .Case("athlon", CK_Athlon) 2368 .Case("athlon-tbird", CK_AthlonThunderbird) 2369 .Case("athlon-4", CK_Athlon4) 2370 .Case("athlon-xp", CK_AthlonXP) 2371 .Case("athlon-mp", CK_AthlonMP) 2372 .Case("athlon64", CK_Athlon64) 2373 .Case("athlon64-sse3", CK_Athlon64SSE3) 2374 .Case("athlon-fx", CK_AthlonFX) 2375 .Case("k8", CK_K8) 2376 .Case("k8-sse3", CK_K8SSE3) 2377 .Case("opteron", CK_Opteron) 2378 .Case("opteron-sse3", CK_OpteronSSE3) 2379 .Case("barcelona", CK_AMDFAM10) 2380 .Case("amdfam10", CK_AMDFAM10) 2381 .Case("btver1", CK_BTVER1) 2382 .Case("btver2", CK_BTVER2) 2383 .Case("bdver1", CK_BDVER1) 2384 .Case("bdver2", CK_BDVER2) 2385 .Case("bdver3", CK_BDVER3) 2386 .Case("bdver4", CK_BDVER4) 2387 .Case("x86-64", CK_x86_64) 2388 .Case("geode", CK_Geode) 2389 .Default(CK_Generic); 2390 } 2391 2392 enum FPMathKind { 2393 FP_Default, 2394 FP_SSE, 2395 FP_387 2396 } FPMath = FP_Default; 2397 2398 public: 2399 X86TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 2400 BigEndian = false; 2401 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2402 } 2403 unsigned getFloatEvalMethod() const override { 2404 // X87 evaluates with 80 bits "long double" precision. 2405 return SSELevel == NoSSE ? 2 : 0; 2406 } 2407 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2408 return llvm::makeArrayRef(BuiltinInfo, 2409 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2410 } 2411 ArrayRef<const char *> getGCCRegNames() const override { 2412 return llvm::makeArrayRef(GCCRegNames); 2413 } 2414 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2415 return None; 2416 } 2417 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2418 return llvm::makeArrayRef(AddlRegNames); 2419 } 2420 bool validateCpuSupports(StringRef Name) const override; 2421 bool validateAsmConstraint(const char *&Name, 2422 TargetInfo::ConstraintInfo &info) const override; 2423 2424 bool validateGlobalRegisterVariable(StringRef RegName, 2425 unsigned RegSize, 2426 bool &HasSizeMismatch) const override { 2427 // esp and ebp are the only 32-bit registers the x86 backend can currently 2428 // handle. 2429 if (RegName.equals("esp") || RegName.equals("ebp")) { 2430 // Check that the register size is 32-bit. 2431 HasSizeMismatch = RegSize != 32; 2432 return true; 2433 } 2434 2435 return false; 2436 } 2437 2438 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2439 2440 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2441 2442 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2443 2444 std::string convertConstraint(const char *&Constraint) const override; 2445 const char *getClobbers() const override { 2446 return "~{dirflag},~{fpsr},~{flags}"; 2447 } 2448 void getTargetDefines(const LangOptions &Opts, 2449 MacroBuilder &Builder) const override; 2450 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2451 bool Enabled); 2452 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2453 bool Enabled); 2454 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2455 bool Enabled); 2456 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2457 StringRef Name, bool Enabled) const override { 2458 setFeatureEnabledImpl(Features, Name, Enabled); 2459 } 2460 // This exists purely to cut down on the number of virtual calls in 2461 // initFeatureMap which calls this repeatedly. 2462 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2463 StringRef Name, bool Enabled); 2464 bool 2465 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2466 StringRef CPU, 2467 const std::vector<std::string> &FeaturesVec) const override; 2468 bool hasFeature(StringRef Feature) const override; 2469 bool handleTargetFeatures(std::vector<std::string> &Features, 2470 DiagnosticsEngine &Diags) override; 2471 StringRef getABI() const override { 2472 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2473 return "avx512"; 2474 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2475 return "avx"; 2476 if (getTriple().getArch() == llvm::Triple::x86 && 2477 MMX3DNowLevel == NoMMX3DNow) 2478 return "no-mmx"; 2479 return ""; 2480 } 2481 bool setCPU(const std::string &Name) override { 2482 CPU = getCPUKind(Name); 2483 2484 // Perform any per-CPU checks necessary to determine if this CPU is 2485 // acceptable. 2486 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2487 // invalid without explaining *why*. 2488 switch (CPU) { 2489 case CK_Generic: 2490 // No processor selected! 2491 return false; 2492 2493 case CK_i386: 2494 case CK_i486: 2495 case CK_WinChipC6: 2496 case CK_WinChip2: 2497 case CK_C3: 2498 case CK_i586: 2499 case CK_Pentium: 2500 case CK_PentiumMMX: 2501 case CK_i686: 2502 case CK_PentiumPro: 2503 case CK_Pentium2: 2504 case CK_Pentium3: 2505 case CK_Pentium3M: 2506 case CK_PentiumM: 2507 case CK_Yonah: 2508 case CK_C3_2: 2509 case CK_Pentium4: 2510 case CK_Pentium4M: 2511 case CK_Prescott: 2512 case CK_K6: 2513 case CK_K6_2: 2514 case CK_K6_3: 2515 case CK_Athlon: 2516 case CK_AthlonThunderbird: 2517 case CK_Athlon4: 2518 case CK_AthlonXP: 2519 case CK_AthlonMP: 2520 case CK_Geode: 2521 // Only accept certain architectures when compiling in 32-bit mode. 2522 if (getTriple().getArch() != llvm::Triple::x86) 2523 return false; 2524 2525 // Fallthrough 2526 case CK_Nocona: 2527 case CK_Core2: 2528 case CK_Penryn: 2529 case CK_Bonnell: 2530 case CK_Silvermont: 2531 case CK_Nehalem: 2532 case CK_Westmere: 2533 case CK_SandyBridge: 2534 case CK_IvyBridge: 2535 case CK_Haswell: 2536 case CK_Broadwell: 2537 case CK_SkylakeClient: 2538 case CK_SkylakeServer: 2539 case CK_Cannonlake: 2540 case CK_KNL: 2541 case CK_Athlon64: 2542 case CK_Athlon64SSE3: 2543 case CK_AthlonFX: 2544 case CK_K8: 2545 case CK_K8SSE3: 2546 case CK_Opteron: 2547 case CK_OpteronSSE3: 2548 case CK_AMDFAM10: 2549 case CK_BTVER1: 2550 case CK_BTVER2: 2551 case CK_BDVER1: 2552 case CK_BDVER2: 2553 case CK_BDVER3: 2554 case CK_BDVER4: 2555 case CK_x86_64: 2556 return true; 2557 } 2558 llvm_unreachable("Unhandled CPU kind"); 2559 } 2560 2561 bool setFPMath(StringRef Name) override; 2562 2563 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2564 // We accept all non-ARM calling conventions 2565 return (CC == CC_X86ThisCall || 2566 CC == CC_X86FastCall || 2567 CC == CC_X86StdCall || 2568 CC == CC_X86VectorCall || 2569 CC == CC_C || 2570 CC == CC_X86Pascal || 2571 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2572 } 2573 2574 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2575 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2576 } 2577 2578 bool hasSjLjLowering() const override { 2579 return true; 2580 } 2581 }; 2582 2583 bool X86TargetInfo::setFPMath(StringRef Name) { 2584 if (Name == "387") { 2585 FPMath = FP_387; 2586 return true; 2587 } 2588 if (Name == "sse") { 2589 FPMath = FP_SSE; 2590 return true; 2591 } 2592 return false; 2593 } 2594 2595 bool X86TargetInfo::initFeatureMap( 2596 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2597 const std::vector<std::string> &FeaturesVec) const { 2598 // FIXME: This *really* should not be here. 2599 // X86_64 always has SSE2. 2600 if (getTriple().getArch() == llvm::Triple::x86_64) 2601 setFeatureEnabledImpl(Features, "sse2", true); 2602 2603 switch (getCPUKind(CPU)) { 2604 case CK_Generic: 2605 case CK_i386: 2606 case CK_i486: 2607 case CK_i586: 2608 case CK_Pentium: 2609 case CK_i686: 2610 case CK_PentiumPro: 2611 break; 2612 case CK_PentiumMMX: 2613 case CK_Pentium2: 2614 case CK_K6: 2615 case CK_WinChipC6: 2616 setFeatureEnabledImpl(Features, "mmx", true); 2617 break; 2618 case CK_Pentium3: 2619 case CK_Pentium3M: 2620 case CK_C3_2: 2621 setFeatureEnabledImpl(Features, "sse", true); 2622 setFeatureEnabledImpl(Features, "fxsr", true); 2623 break; 2624 case CK_PentiumM: 2625 case CK_Pentium4: 2626 case CK_Pentium4M: 2627 case CK_x86_64: 2628 setFeatureEnabledImpl(Features, "sse2", true); 2629 setFeatureEnabledImpl(Features, "fxsr", true); 2630 break; 2631 case CK_Yonah: 2632 case CK_Prescott: 2633 case CK_Nocona: 2634 setFeatureEnabledImpl(Features, "sse3", true); 2635 setFeatureEnabledImpl(Features, "fxsr", true); 2636 setFeatureEnabledImpl(Features, "cx16", true); 2637 break; 2638 case CK_Core2: 2639 case CK_Bonnell: 2640 setFeatureEnabledImpl(Features, "ssse3", true); 2641 setFeatureEnabledImpl(Features, "fxsr", true); 2642 setFeatureEnabledImpl(Features, "cx16", true); 2643 break; 2644 case CK_Penryn: 2645 setFeatureEnabledImpl(Features, "sse4.1", true); 2646 setFeatureEnabledImpl(Features, "fxsr", true); 2647 setFeatureEnabledImpl(Features, "cx16", true); 2648 break; 2649 case CK_Cannonlake: 2650 setFeatureEnabledImpl(Features, "avx512ifma", true); 2651 setFeatureEnabledImpl(Features, "avx512vbmi", true); 2652 setFeatureEnabledImpl(Features, "sha", true); 2653 setFeatureEnabledImpl(Features, "umip", true); 2654 // FALLTHROUGH 2655 case CK_SkylakeServer: 2656 setFeatureEnabledImpl(Features, "avx512f", true); 2657 setFeatureEnabledImpl(Features, "avx512cd", true); 2658 setFeatureEnabledImpl(Features, "avx512dq", true); 2659 setFeatureEnabledImpl(Features, "avx512bw", true); 2660 setFeatureEnabledImpl(Features, "avx512vl", true); 2661 setFeatureEnabledImpl(Features, "pku", true); 2662 setFeatureEnabledImpl(Features, "pcommit", true); 2663 setFeatureEnabledImpl(Features, "clwb", true); 2664 // FALLTHROUGH 2665 case CK_SkylakeClient: 2666 setFeatureEnabledImpl(Features, "xsavec", true); 2667 setFeatureEnabledImpl(Features, "xsaves", true); 2668 setFeatureEnabledImpl(Features, "mpx", true); 2669 setFeatureEnabledImpl(Features, "sgx", true); 2670 setFeatureEnabledImpl(Features, "clflushopt", true); 2671 // FALLTHROUGH 2672 case CK_Broadwell: 2673 setFeatureEnabledImpl(Features, "rdseed", true); 2674 setFeatureEnabledImpl(Features, "adx", true); 2675 // FALLTHROUGH 2676 case CK_Haswell: 2677 setFeatureEnabledImpl(Features, "avx2", true); 2678 setFeatureEnabledImpl(Features, "lzcnt", true); 2679 setFeatureEnabledImpl(Features, "bmi", true); 2680 setFeatureEnabledImpl(Features, "bmi2", true); 2681 setFeatureEnabledImpl(Features, "rtm", true); 2682 setFeatureEnabledImpl(Features, "fma", true); 2683 setFeatureEnabledImpl(Features, "movbe", true); 2684 // FALLTHROUGH 2685 case CK_IvyBridge: 2686 setFeatureEnabledImpl(Features, "rdrnd", true); 2687 setFeatureEnabledImpl(Features, "f16c", true); 2688 setFeatureEnabledImpl(Features, "fsgsbase", true); 2689 // FALLTHROUGH 2690 case CK_SandyBridge: 2691 setFeatureEnabledImpl(Features, "avx", true); 2692 setFeatureEnabledImpl(Features, "xsave", true); 2693 setFeatureEnabledImpl(Features, "xsaveopt", true); 2694 // FALLTHROUGH 2695 case CK_Westmere: 2696 case CK_Silvermont: 2697 setFeatureEnabledImpl(Features, "aes", true); 2698 setFeatureEnabledImpl(Features, "pclmul", true); 2699 // FALLTHROUGH 2700 case CK_Nehalem: 2701 setFeatureEnabledImpl(Features, "sse4.2", true); 2702 setFeatureEnabledImpl(Features, "fxsr", true); 2703 setFeatureEnabledImpl(Features, "cx16", true); 2704 break; 2705 case CK_KNL: 2706 setFeatureEnabledImpl(Features, "avx512f", true); 2707 setFeatureEnabledImpl(Features, "avx512cd", true); 2708 setFeatureEnabledImpl(Features, "avx512er", true); 2709 setFeatureEnabledImpl(Features, "avx512pf", true); 2710 setFeatureEnabledImpl(Features, "prefetchwt1", true); 2711 setFeatureEnabledImpl(Features, "fxsr", true); 2712 setFeatureEnabledImpl(Features, "rdseed", true); 2713 setFeatureEnabledImpl(Features, "adx", true); 2714 setFeatureEnabledImpl(Features, "lzcnt", true); 2715 setFeatureEnabledImpl(Features, "bmi", true); 2716 setFeatureEnabledImpl(Features, "bmi2", true); 2717 setFeatureEnabledImpl(Features, "rtm", true); 2718 setFeatureEnabledImpl(Features, "fma", true); 2719 setFeatureEnabledImpl(Features, "rdrnd", true); 2720 setFeatureEnabledImpl(Features, "f16c", true); 2721 setFeatureEnabledImpl(Features, "fsgsbase", true); 2722 setFeatureEnabledImpl(Features, "aes", true); 2723 setFeatureEnabledImpl(Features, "pclmul", true); 2724 setFeatureEnabledImpl(Features, "cx16", true); 2725 setFeatureEnabledImpl(Features, "xsaveopt", true); 2726 setFeatureEnabledImpl(Features, "xsave", true); 2727 setFeatureEnabledImpl(Features, "movbe", true); 2728 break; 2729 case CK_K6_2: 2730 case CK_K6_3: 2731 case CK_WinChip2: 2732 case CK_C3: 2733 setFeatureEnabledImpl(Features, "3dnow", true); 2734 break; 2735 case CK_Athlon: 2736 case CK_AthlonThunderbird: 2737 case CK_Geode: 2738 setFeatureEnabledImpl(Features, "3dnowa", true); 2739 break; 2740 case CK_Athlon4: 2741 case CK_AthlonXP: 2742 case CK_AthlonMP: 2743 setFeatureEnabledImpl(Features, "sse", true); 2744 setFeatureEnabledImpl(Features, "3dnowa", true); 2745 setFeatureEnabledImpl(Features, "fxsr", true); 2746 break; 2747 case CK_K8: 2748 case CK_Opteron: 2749 case CK_Athlon64: 2750 case CK_AthlonFX: 2751 setFeatureEnabledImpl(Features, "sse2", true); 2752 setFeatureEnabledImpl(Features, "3dnowa", true); 2753 setFeatureEnabledImpl(Features, "fxsr", true); 2754 break; 2755 case CK_AMDFAM10: 2756 setFeatureEnabledImpl(Features, "sse4a", true); 2757 setFeatureEnabledImpl(Features, "lzcnt", true); 2758 setFeatureEnabledImpl(Features, "popcnt", true); 2759 // FALLTHROUGH 2760 case CK_K8SSE3: 2761 case CK_OpteronSSE3: 2762 case CK_Athlon64SSE3: 2763 setFeatureEnabledImpl(Features, "sse3", true); 2764 setFeatureEnabledImpl(Features, "3dnowa", true); 2765 setFeatureEnabledImpl(Features, "fxsr", true); 2766 break; 2767 case CK_BTVER2: 2768 setFeatureEnabledImpl(Features, "avx", true); 2769 setFeatureEnabledImpl(Features, "aes", true); 2770 setFeatureEnabledImpl(Features, "pclmul", true); 2771 setFeatureEnabledImpl(Features, "bmi", true); 2772 setFeatureEnabledImpl(Features, "f16c", true); 2773 setFeatureEnabledImpl(Features, "xsaveopt", true); 2774 // FALLTHROUGH 2775 case CK_BTVER1: 2776 setFeatureEnabledImpl(Features, "ssse3", true); 2777 setFeatureEnabledImpl(Features, "sse4a", true); 2778 setFeatureEnabledImpl(Features, "lzcnt", true); 2779 setFeatureEnabledImpl(Features, "popcnt", true); 2780 setFeatureEnabledImpl(Features, "prfchw", true); 2781 setFeatureEnabledImpl(Features, "cx16", true); 2782 setFeatureEnabledImpl(Features, "fxsr", true); 2783 setFeatureEnabledImpl(Features, "xsave", true); 2784 break; 2785 case CK_BDVER4: 2786 setFeatureEnabledImpl(Features, "avx2", true); 2787 setFeatureEnabledImpl(Features, "bmi2", true); 2788 // FALLTHROUGH 2789 case CK_BDVER3: 2790 setFeatureEnabledImpl(Features, "fsgsbase", true); 2791 setFeatureEnabledImpl(Features, "xsaveopt", true); 2792 // FALLTHROUGH 2793 case CK_BDVER2: 2794 setFeatureEnabledImpl(Features, "bmi", true); 2795 setFeatureEnabledImpl(Features, "fma", true); 2796 setFeatureEnabledImpl(Features, "f16c", true); 2797 setFeatureEnabledImpl(Features, "tbm", true); 2798 // FALLTHROUGH 2799 case CK_BDVER1: 2800 // xop implies avx, sse4a and fma4. 2801 setFeatureEnabledImpl(Features, "xop", true); 2802 setFeatureEnabledImpl(Features, "lzcnt", true); 2803 setFeatureEnabledImpl(Features, "aes", true); 2804 setFeatureEnabledImpl(Features, "pclmul", true); 2805 setFeatureEnabledImpl(Features, "prfchw", true); 2806 setFeatureEnabledImpl(Features, "cx16", true); 2807 setFeatureEnabledImpl(Features, "fxsr", true); 2808 setFeatureEnabledImpl(Features, "xsave", true); 2809 break; 2810 } 2811 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 2812 return false; 2813 2814 // Can't do this earlier because we need to be able to explicitly enable 2815 // or disable these features and the things that they depend upon. 2816 2817 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2818 auto I = Features.find("sse4.2"); 2819 if (I != Features.end() && I->getValue() && 2820 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 2821 FeaturesVec.end()) 2822 Features["popcnt"] = true; 2823 2824 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2825 I = Features.find("3dnow"); 2826 if (I != Features.end() && I->getValue() && 2827 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 2828 FeaturesVec.end()) 2829 Features["prfchw"] = true; 2830 2831 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2832 // then enable MMX. 2833 I = Features.find("sse"); 2834 if (I != Features.end() && I->getValue() && 2835 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 2836 FeaturesVec.end()) 2837 Features["mmx"] = true; 2838 2839 return true; 2840 } 2841 2842 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2843 X86SSEEnum Level, bool Enabled) { 2844 if (Enabled) { 2845 switch (Level) { 2846 case AVX512F: 2847 Features["avx512f"] = true; 2848 case AVX2: 2849 Features["avx2"] = true; 2850 case AVX: 2851 Features["avx"] = true; 2852 Features["xsave"] = true; 2853 case SSE42: 2854 Features["sse4.2"] = true; 2855 case SSE41: 2856 Features["sse4.1"] = true; 2857 case SSSE3: 2858 Features["ssse3"] = true; 2859 case SSE3: 2860 Features["sse3"] = true; 2861 case SSE2: 2862 Features["sse2"] = true; 2863 case SSE1: 2864 Features["sse"] = true; 2865 case NoSSE: 2866 break; 2867 } 2868 return; 2869 } 2870 2871 switch (Level) { 2872 case NoSSE: 2873 case SSE1: 2874 Features["sse"] = false; 2875 case SSE2: 2876 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2877 Features["sha"] = false; 2878 case SSE3: 2879 Features["sse3"] = false; 2880 setXOPLevel(Features, NoXOP, false); 2881 case SSSE3: 2882 Features["ssse3"] = false; 2883 case SSE41: 2884 Features["sse4.1"] = false; 2885 case SSE42: 2886 Features["sse4.2"] = false; 2887 case AVX: 2888 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 2889 Features["xsaveopt"] = false; 2890 setXOPLevel(Features, FMA4, false); 2891 case AVX2: 2892 Features["avx2"] = false; 2893 case AVX512F: 2894 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2895 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2896 Features["avx512vl"] = Features["avx512vbmi"] = 2897 Features["avx512ifma"] = false; 2898 } 2899 } 2900 2901 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2902 MMX3DNowEnum Level, bool Enabled) { 2903 if (Enabled) { 2904 switch (Level) { 2905 case AMD3DNowAthlon: 2906 Features["3dnowa"] = true; 2907 case AMD3DNow: 2908 Features["3dnow"] = true; 2909 case MMX: 2910 Features["mmx"] = true; 2911 case NoMMX3DNow: 2912 break; 2913 } 2914 return; 2915 } 2916 2917 switch (Level) { 2918 case NoMMX3DNow: 2919 case MMX: 2920 Features["mmx"] = false; 2921 case AMD3DNow: 2922 Features["3dnow"] = false; 2923 case AMD3DNowAthlon: 2924 Features["3dnowa"] = false; 2925 } 2926 } 2927 2928 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2929 bool Enabled) { 2930 if (Enabled) { 2931 switch (Level) { 2932 case XOP: 2933 Features["xop"] = true; 2934 case FMA4: 2935 Features["fma4"] = true; 2936 setSSELevel(Features, AVX, true); 2937 case SSE4A: 2938 Features["sse4a"] = true; 2939 setSSELevel(Features, SSE3, true); 2940 case NoXOP: 2941 break; 2942 } 2943 return; 2944 } 2945 2946 switch (Level) { 2947 case NoXOP: 2948 case SSE4A: 2949 Features["sse4a"] = false; 2950 case FMA4: 2951 Features["fma4"] = false; 2952 case XOP: 2953 Features["xop"] = false; 2954 } 2955 } 2956 2957 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2958 StringRef Name, bool Enabled) { 2959 // This is a bit of a hack to deal with the sse4 target feature when used 2960 // as part of the target attribute. We handle sse4 correctly everywhere 2961 // else. See below for more information on how we handle the sse4 options. 2962 if (Name != "sse4") 2963 Features[Name] = Enabled; 2964 2965 if (Name == "mmx") { 2966 setMMXLevel(Features, MMX, Enabled); 2967 } else if (Name == "sse") { 2968 setSSELevel(Features, SSE1, Enabled); 2969 } else if (Name == "sse2") { 2970 setSSELevel(Features, SSE2, Enabled); 2971 } else if (Name == "sse3") { 2972 setSSELevel(Features, SSE3, Enabled); 2973 } else if (Name == "ssse3") { 2974 setSSELevel(Features, SSSE3, Enabled); 2975 } else if (Name == "sse4.2") { 2976 setSSELevel(Features, SSE42, Enabled); 2977 } else if (Name == "sse4.1") { 2978 setSSELevel(Features, SSE41, Enabled); 2979 } else if (Name == "3dnow") { 2980 setMMXLevel(Features, AMD3DNow, Enabled); 2981 } else if (Name == "3dnowa") { 2982 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2983 } else if (Name == "aes") { 2984 if (Enabled) 2985 setSSELevel(Features, SSE2, Enabled); 2986 } else if (Name == "pclmul") { 2987 if (Enabled) 2988 setSSELevel(Features, SSE2, Enabled); 2989 } else if (Name == "avx") { 2990 setSSELevel(Features, AVX, Enabled); 2991 } else if (Name == "avx2") { 2992 setSSELevel(Features, AVX2, Enabled); 2993 } else if (Name == "avx512f") { 2994 setSSELevel(Features, AVX512F, Enabled); 2995 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 2996 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 2997 Name == "avx512vbmi" || Name == "avx512ifma") { 2998 if (Enabled) 2999 setSSELevel(Features, AVX512F, Enabled); 3000 } else if (Name == "fma") { 3001 if (Enabled) 3002 setSSELevel(Features, AVX, Enabled); 3003 } else if (Name == "fma4") { 3004 setXOPLevel(Features, FMA4, Enabled); 3005 } else if (Name == "xop") { 3006 setXOPLevel(Features, XOP, Enabled); 3007 } else if (Name == "sse4a") { 3008 setXOPLevel(Features, SSE4A, Enabled); 3009 } else if (Name == "f16c") { 3010 if (Enabled) 3011 setSSELevel(Features, AVX, Enabled); 3012 } else if (Name == "sha") { 3013 if (Enabled) 3014 setSSELevel(Features, SSE2, Enabled); 3015 } else if (Name == "sse4") { 3016 // We can get here via the __target__ attribute since that's not controlled 3017 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3018 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3019 // disabled. 3020 if (Enabled) 3021 setSSELevel(Features, SSE42, Enabled); 3022 else 3023 setSSELevel(Features, SSE41, Enabled); 3024 } else if (Name == "xsave") { 3025 if (!Enabled) 3026 Features["xsaveopt"] = false; 3027 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3028 if (Enabled) 3029 Features["xsave"] = true; 3030 } 3031 } 3032 3033 /// handleTargetFeatures - Perform initialization based on the user 3034 /// configured set of features. 3035 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3036 DiagnosticsEngine &Diags) { 3037 for (const auto &Feature : Features) { 3038 if (Feature[0] != '+') 3039 continue; 3040 3041 if (Feature == "+aes") { 3042 HasAES = true; 3043 } else if (Feature == "+pclmul") { 3044 HasPCLMUL = true; 3045 } else if (Feature == "+lzcnt") { 3046 HasLZCNT = true; 3047 } else if (Feature == "+rdrnd") { 3048 HasRDRND = true; 3049 } else if (Feature == "+fsgsbase") { 3050 HasFSGSBASE = true; 3051 } else if (Feature == "+bmi") { 3052 HasBMI = true; 3053 } else if (Feature == "+bmi2") { 3054 HasBMI2 = true; 3055 } else if (Feature == "+popcnt") { 3056 HasPOPCNT = true; 3057 } else if (Feature == "+rtm") { 3058 HasRTM = true; 3059 } else if (Feature == "+prfchw") { 3060 HasPRFCHW = true; 3061 } else if (Feature == "+rdseed") { 3062 HasRDSEED = true; 3063 } else if (Feature == "+adx") { 3064 HasADX = true; 3065 } else if (Feature == "+tbm") { 3066 HasTBM = true; 3067 } else if (Feature == "+fma") { 3068 HasFMA = true; 3069 } else if (Feature == "+f16c") { 3070 HasF16C = true; 3071 } else if (Feature == "+avx512cd") { 3072 HasAVX512CD = true; 3073 } else if (Feature == "+avx512er") { 3074 HasAVX512ER = true; 3075 } else if (Feature == "+avx512pf") { 3076 HasAVX512PF = true; 3077 } else if (Feature == "+avx512dq") { 3078 HasAVX512DQ = true; 3079 } else if (Feature == "+avx512bw") { 3080 HasAVX512BW = true; 3081 } else if (Feature == "+avx512vl") { 3082 HasAVX512VL = true; 3083 } else if (Feature == "+avx512vbmi") { 3084 HasAVX512VBMI = true; 3085 } else if (Feature == "+avx512ifma") { 3086 HasAVX512IFMA = true; 3087 } else if (Feature == "+sha") { 3088 HasSHA = true; 3089 } else if (Feature == "+mpx") { 3090 HasMPX = true; 3091 } else if (Feature == "+movbe") { 3092 HasMOVBE = true; 3093 } else if (Feature == "+sgx") { 3094 HasSGX = true; 3095 } else if (Feature == "+cx16") { 3096 HasCX16 = true; 3097 } else if (Feature == "+fxsr") { 3098 HasFXSR = true; 3099 } else if (Feature == "+xsave") { 3100 HasXSAVE = true; 3101 } else if (Feature == "+xsaveopt") { 3102 HasXSAVEOPT = true; 3103 } else if (Feature == "+xsavec") { 3104 HasXSAVEC = true; 3105 } else if (Feature == "+xsaves") { 3106 HasXSAVES = true; 3107 } else if (Feature == "+pku") { 3108 HasPKU = true; 3109 } else if (Feature == "+clflushopt") { 3110 HasCLFLUSHOPT = true; 3111 } else if (Feature == "+pcommit") { 3112 HasPCOMMIT = true; 3113 } else if (Feature == "+clwb") { 3114 HasCLWB = true; 3115 } else if (Feature == "+umip") { 3116 HasUMIP = true; 3117 } else if (Feature == "+prefetchwt1") { 3118 HasPREFETCHWT1 = true; 3119 } 3120 3121 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3122 .Case("+avx512f", AVX512F) 3123 .Case("+avx2", AVX2) 3124 .Case("+avx", AVX) 3125 .Case("+sse4.2", SSE42) 3126 .Case("+sse4.1", SSE41) 3127 .Case("+ssse3", SSSE3) 3128 .Case("+sse3", SSE3) 3129 .Case("+sse2", SSE2) 3130 .Case("+sse", SSE1) 3131 .Default(NoSSE); 3132 SSELevel = std::max(SSELevel, Level); 3133 3134 MMX3DNowEnum ThreeDNowLevel = 3135 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3136 .Case("+3dnowa", AMD3DNowAthlon) 3137 .Case("+3dnow", AMD3DNow) 3138 .Case("+mmx", MMX) 3139 .Default(NoMMX3DNow); 3140 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3141 3142 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3143 .Case("+xop", XOP) 3144 .Case("+fma4", FMA4) 3145 .Case("+sse4a", SSE4A) 3146 .Default(NoXOP); 3147 XOPLevel = std::max(XOPLevel, XLevel); 3148 } 3149 3150 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3151 // matches the selected sse level. 3152 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3153 (FPMath == FP_387 && SSELevel >= SSE1)) { 3154 Diags.Report(diag::err_target_unsupported_fpmath) << 3155 (FPMath == FP_SSE ? "sse" : "387"); 3156 return false; 3157 } 3158 3159 SimdDefaultAlign = 3160 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3161 return true; 3162 } 3163 3164 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3165 /// definitions for this particular subtarget. 3166 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3167 MacroBuilder &Builder) const { 3168 // Target identification. 3169 if (getTriple().getArch() == llvm::Triple::x86_64) { 3170 Builder.defineMacro("__amd64__"); 3171 Builder.defineMacro("__amd64"); 3172 Builder.defineMacro("__x86_64"); 3173 Builder.defineMacro("__x86_64__"); 3174 if (getTriple().getArchName() == "x86_64h") { 3175 Builder.defineMacro("__x86_64h"); 3176 Builder.defineMacro("__x86_64h__"); 3177 } 3178 } else { 3179 DefineStd(Builder, "i386", Opts); 3180 } 3181 3182 // Subtarget options. 3183 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3184 // truly should be based on -mtune options. 3185 switch (CPU) { 3186 case CK_Generic: 3187 break; 3188 case CK_i386: 3189 // The rest are coming from the i386 define above. 3190 Builder.defineMacro("__tune_i386__"); 3191 break; 3192 case CK_i486: 3193 case CK_WinChipC6: 3194 case CK_WinChip2: 3195 case CK_C3: 3196 defineCPUMacros(Builder, "i486"); 3197 break; 3198 case CK_PentiumMMX: 3199 Builder.defineMacro("__pentium_mmx__"); 3200 Builder.defineMacro("__tune_pentium_mmx__"); 3201 // Fallthrough 3202 case CK_i586: 3203 case CK_Pentium: 3204 defineCPUMacros(Builder, "i586"); 3205 defineCPUMacros(Builder, "pentium"); 3206 break; 3207 case CK_Pentium3: 3208 case CK_Pentium3M: 3209 case CK_PentiumM: 3210 Builder.defineMacro("__tune_pentium3__"); 3211 // Fallthrough 3212 case CK_Pentium2: 3213 case CK_C3_2: 3214 Builder.defineMacro("__tune_pentium2__"); 3215 // Fallthrough 3216 case CK_PentiumPro: 3217 Builder.defineMacro("__tune_i686__"); 3218 Builder.defineMacro("__tune_pentiumpro__"); 3219 // Fallthrough 3220 case CK_i686: 3221 Builder.defineMacro("__i686"); 3222 Builder.defineMacro("__i686__"); 3223 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3224 Builder.defineMacro("__pentiumpro"); 3225 Builder.defineMacro("__pentiumpro__"); 3226 break; 3227 case CK_Pentium4: 3228 case CK_Pentium4M: 3229 defineCPUMacros(Builder, "pentium4"); 3230 break; 3231 case CK_Yonah: 3232 case CK_Prescott: 3233 case CK_Nocona: 3234 defineCPUMacros(Builder, "nocona"); 3235 break; 3236 case CK_Core2: 3237 case CK_Penryn: 3238 defineCPUMacros(Builder, "core2"); 3239 break; 3240 case CK_Bonnell: 3241 defineCPUMacros(Builder, "atom"); 3242 break; 3243 case CK_Silvermont: 3244 defineCPUMacros(Builder, "slm"); 3245 break; 3246 case CK_Nehalem: 3247 case CK_Westmere: 3248 case CK_SandyBridge: 3249 case CK_IvyBridge: 3250 case CK_Haswell: 3251 case CK_Broadwell: 3252 case CK_SkylakeClient: 3253 // FIXME: Historically, we defined this legacy name, it would be nice to 3254 // remove it at some point. We've never exposed fine-grained names for 3255 // recent primary x86 CPUs, and we should keep it that way. 3256 defineCPUMacros(Builder, "corei7"); 3257 break; 3258 case CK_SkylakeServer: 3259 defineCPUMacros(Builder, "skx"); 3260 break; 3261 case CK_Cannonlake: 3262 break; 3263 case CK_KNL: 3264 defineCPUMacros(Builder, "knl"); 3265 break; 3266 case CK_K6_2: 3267 Builder.defineMacro("__k6_2__"); 3268 Builder.defineMacro("__tune_k6_2__"); 3269 // Fallthrough 3270 case CK_K6_3: 3271 if (CPU != CK_K6_2) { // In case of fallthrough 3272 // FIXME: GCC may be enabling these in cases where some other k6 3273 // architecture is specified but -m3dnow is explicitly provided. The 3274 // exact semantics need to be determined and emulated here. 3275 Builder.defineMacro("__k6_3__"); 3276 Builder.defineMacro("__tune_k6_3__"); 3277 } 3278 // Fallthrough 3279 case CK_K6: 3280 defineCPUMacros(Builder, "k6"); 3281 break; 3282 case CK_Athlon: 3283 case CK_AthlonThunderbird: 3284 case CK_Athlon4: 3285 case CK_AthlonXP: 3286 case CK_AthlonMP: 3287 defineCPUMacros(Builder, "athlon"); 3288 if (SSELevel != NoSSE) { 3289 Builder.defineMacro("__athlon_sse__"); 3290 Builder.defineMacro("__tune_athlon_sse__"); 3291 } 3292 break; 3293 case CK_K8: 3294 case CK_K8SSE3: 3295 case CK_x86_64: 3296 case CK_Opteron: 3297 case CK_OpteronSSE3: 3298 case CK_Athlon64: 3299 case CK_Athlon64SSE3: 3300 case CK_AthlonFX: 3301 defineCPUMacros(Builder, "k8"); 3302 break; 3303 case CK_AMDFAM10: 3304 defineCPUMacros(Builder, "amdfam10"); 3305 break; 3306 case CK_BTVER1: 3307 defineCPUMacros(Builder, "btver1"); 3308 break; 3309 case CK_BTVER2: 3310 defineCPUMacros(Builder, "btver2"); 3311 break; 3312 case CK_BDVER1: 3313 defineCPUMacros(Builder, "bdver1"); 3314 break; 3315 case CK_BDVER2: 3316 defineCPUMacros(Builder, "bdver2"); 3317 break; 3318 case CK_BDVER3: 3319 defineCPUMacros(Builder, "bdver3"); 3320 break; 3321 case CK_BDVER4: 3322 defineCPUMacros(Builder, "bdver4"); 3323 break; 3324 case CK_Geode: 3325 defineCPUMacros(Builder, "geode"); 3326 break; 3327 } 3328 3329 // Target properties. 3330 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3331 3332 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3333 // functions in glibc header files that use FP Stack inline asm which the 3334 // backend can't deal with (PR879). 3335 Builder.defineMacro("__NO_MATH_INLINES"); 3336 3337 if (HasAES) 3338 Builder.defineMacro("__AES__"); 3339 3340 if (HasPCLMUL) 3341 Builder.defineMacro("__PCLMUL__"); 3342 3343 if (HasLZCNT) 3344 Builder.defineMacro("__LZCNT__"); 3345 3346 if (HasRDRND) 3347 Builder.defineMacro("__RDRND__"); 3348 3349 if (HasFSGSBASE) 3350 Builder.defineMacro("__FSGSBASE__"); 3351 3352 if (HasBMI) 3353 Builder.defineMacro("__BMI__"); 3354 3355 if (HasBMI2) 3356 Builder.defineMacro("__BMI2__"); 3357 3358 if (HasPOPCNT) 3359 Builder.defineMacro("__POPCNT__"); 3360 3361 if (HasRTM) 3362 Builder.defineMacro("__RTM__"); 3363 3364 if (HasPRFCHW) 3365 Builder.defineMacro("__PRFCHW__"); 3366 3367 if (HasRDSEED) 3368 Builder.defineMacro("__RDSEED__"); 3369 3370 if (HasADX) 3371 Builder.defineMacro("__ADX__"); 3372 3373 if (HasTBM) 3374 Builder.defineMacro("__TBM__"); 3375 3376 switch (XOPLevel) { 3377 case XOP: 3378 Builder.defineMacro("__XOP__"); 3379 case FMA4: 3380 Builder.defineMacro("__FMA4__"); 3381 case SSE4A: 3382 Builder.defineMacro("__SSE4A__"); 3383 case NoXOP: 3384 break; 3385 } 3386 3387 if (HasFMA) 3388 Builder.defineMacro("__FMA__"); 3389 3390 if (HasF16C) 3391 Builder.defineMacro("__F16C__"); 3392 3393 if (HasAVX512CD) 3394 Builder.defineMacro("__AVX512CD__"); 3395 if (HasAVX512ER) 3396 Builder.defineMacro("__AVX512ER__"); 3397 if (HasAVX512PF) 3398 Builder.defineMacro("__AVX512PF__"); 3399 if (HasAVX512DQ) 3400 Builder.defineMacro("__AVX512DQ__"); 3401 if (HasAVX512BW) 3402 Builder.defineMacro("__AVX512BW__"); 3403 if (HasAVX512VL) 3404 Builder.defineMacro("__AVX512VL__"); 3405 if (HasAVX512VBMI) 3406 Builder.defineMacro("__AVX512VBMI__"); 3407 if (HasAVX512IFMA) 3408 Builder.defineMacro("__AVX512IFMA__"); 3409 3410 if (HasSHA) 3411 Builder.defineMacro("__SHA__"); 3412 3413 if (HasFXSR) 3414 Builder.defineMacro("__FXSR__"); 3415 if (HasXSAVE) 3416 Builder.defineMacro("__XSAVE__"); 3417 if (HasXSAVEOPT) 3418 Builder.defineMacro("__XSAVEOPT__"); 3419 if (HasXSAVEC) 3420 Builder.defineMacro("__XSAVEC__"); 3421 if (HasXSAVES) 3422 Builder.defineMacro("__XSAVES__"); 3423 if (HasPKU) 3424 Builder.defineMacro("__PKU__"); 3425 if (HasCX16) 3426 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3427 3428 // Each case falls through to the previous one here. 3429 switch (SSELevel) { 3430 case AVX512F: 3431 Builder.defineMacro("__AVX512F__"); 3432 case AVX2: 3433 Builder.defineMacro("__AVX2__"); 3434 case AVX: 3435 Builder.defineMacro("__AVX__"); 3436 case SSE42: 3437 Builder.defineMacro("__SSE4_2__"); 3438 case SSE41: 3439 Builder.defineMacro("__SSE4_1__"); 3440 case SSSE3: 3441 Builder.defineMacro("__SSSE3__"); 3442 case SSE3: 3443 Builder.defineMacro("__SSE3__"); 3444 case SSE2: 3445 Builder.defineMacro("__SSE2__"); 3446 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3447 case SSE1: 3448 Builder.defineMacro("__SSE__"); 3449 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3450 case NoSSE: 3451 break; 3452 } 3453 3454 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3455 switch (SSELevel) { 3456 case AVX512F: 3457 case AVX2: 3458 case AVX: 3459 case SSE42: 3460 case SSE41: 3461 case SSSE3: 3462 case SSE3: 3463 case SSE2: 3464 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3465 break; 3466 case SSE1: 3467 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3468 break; 3469 default: 3470 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3471 } 3472 } 3473 3474 // Each case falls through to the previous one here. 3475 switch (MMX3DNowLevel) { 3476 case AMD3DNowAthlon: 3477 Builder.defineMacro("__3dNOW_A__"); 3478 case AMD3DNow: 3479 Builder.defineMacro("__3dNOW__"); 3480 case MMX: 3481 Builder.defineMacro("__MMX__"); 3482 case NoMMX3DNow: 3483 break; 3484 } 3485 3486 if (CPU >= CK_i486) { 3487 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3488 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3489 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3490 } 3491 if (CPU >= CK_i586) 3492 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3493 } 3494 3495 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3496 return llvm::StringSwitch<bool>(Feature) 3497 .Case("aes", HasAES) 3498 .Case("avx", SSELevel >= AVX) 3499 .Case("avx2", SSELevel >= AVX2) 3500 .Case("avx512f", SSELevel >= AVX512F) 3501 .Case("avx512cd", HasAVX512CD) 3502 .Case("avx512er", HasAVX512ER) 3503 .Case("avx512pf", HasAVX512PF) 3504 .Case("avx512dq", HasAVX512DQ) 3505 .Case("avx512bw", HasAVX512BW) 3506 .Case("avx512vl", HasAVX512VL) 3507 .Case("avx512vbmi", HasAVX512VBMI) 3508 .Case("avx512ifma", HasAVX512IFMA) 3509 .Case("bmi", HasBMI) 3510 .Case("bmi2", HasBMI2) 3511 .Case("clflushopt", HasCLFLUSHOPT) 3512 .Case("clwb", HasCLWB) 3513 .Case("cx16", HasCX16) 3514 .Case("f16c", HasF16C) 3515 .Case("fma", HasFMA) 3516 .Case("fma4", XOPLevel >= FMA4) 3517 .Case("fsgsbase", HasFSGSBASE) 3518 .Case("fxsr", HasFXSR) 3519 .Case("lzcnt", HasLZCNT) 3520 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3521 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3522 .Case("mmx", MMX3DNowLevel >= MMX) 3523 .Case("movbe", HasMOVBE) 3524 .Case("mpx", HasMPX) 3525 .Case("pclmul", HasPCLMUL) 3526 .Case("pcommit", HasPCOMMIT) 3527 .Case("pku", HasPKU) 3528 .Case("popcnt", HasPOPCNT) 3529 .Case("prefetchwt1", HasPREFETCHWT1) 3530 .Case("prfchw", HasPRFCHW) 3531 .Case("rdrnd", HasRDRND) 3532 .Case("rdseed", HasRDSEED) 3533 .Case("rtm", HasRTM) 3534 .Case("sgx", HasSGX) 3535 .Case("sha", HasSHA) 3536 .Case("sse", SSELevel >= SSE1) 3537 .Case("sse2", SSELevel >= SSE2) 3538 .Case("sse3", SSELevel >= SSE3) 3539 .Case("ssse3", SSELevel >= SSSE3) 3540 .Case("sse4.1", SSELevel >= SSE41) 3541 .Case("sse4.2", SSELevel >= SSE42) 3542 .Case("sse4a", XOPLevel >= SSE4A) 3543 .Case("tbm", HasTBM) 3544 .Case("umip", HasUMIP) 3545 .Case("x86", true) 3546 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3547 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3548 .Case("xop", XOPLevel >= XOP) 3549 .Case("xsave", HasXSAVE) 3550 .Case("xsavec", HasXSAVEC) 3551 .Case("xsaves", HasXSAVES) 3552 .Case("xsaveopt", HasXSAVEOPT) 3553 .Default(false); 3554 } 3555 3556 // We can't use a generic validation scheme for the features accepted here 3557 // versus subtarget features accepted in the target attribute because the 3558 // bitfield structure that's initialized in the runtime only supports the 3559 // below currently rather than the full range of subtarget features. (See 3560 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3561 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3562 return llvm::StringSwitch<bool>(FeatureStr) 3563 .Case("cmov", true) 3564 .Case("mmx", true) 3565 .Case("popcnt", true) 3566 .Case("sse", true) 3567 .Case("sse2", true) 3568 .Case("sse3", true) 3569 .Case("sse4.1", true) 3570 .Case("sse4.2", true) 3571 .Case("avx", true) 3572 .Case("avx2", true) 3573 .Case("sse4a", true) 3574 .Case("fma4", true) 3575 .Case("xop", true) 3576 .Case("fma", true) 3577 .Case("avx512f", true) 3578 .Case("bmi", true) 3579 .Case("bmi2", true) 3580 .Default(false); 3581 } 3582 3583 bool 3584 X86TargetInfo::validateAsmConstraint(const char *&Name, 3585 TargetInfo::ConstraintInfo &Info) const { 3586 switch (*Name) { 3587 default: return false; 3588 // Constant constraints. 3589 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3590 // instructions. 3591 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3592 // x86_64 instructions. 3593 case 's': 3594 Info.setRequiresImmediate(); 3595 return true; 3596 case 'I': 3597 Info.setRequiresImmediate(0, 31); 3598 return true; 3599 case 'J': 3600 Info.setRequiresImmediate(0, 63); 3601 return true; 3602 case 'K': 3603 Info.setRequiresImmediate(-128, 127); 3604 return true; 3605 case 'L': 3606 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3607 return true; 3608 case 'M': 3609 Info.setRequiresImmediate(0, 3); 3610 return true; 3611 case 'N': 3612 Info.setRequiresImmediate(0, 255); 3613 return true; 3614 case 'O': 3615 Info.setRequiresImmediate(0, 127); 3616 return true; 3617 // Register constraints. 3618 case 'Y': // 'Y' is the first character for several 2-character constraints. 3619 // Shift the pointer to the second character of the constraint. 3620 Name++; 3621 switch (*Name) { 3622 default: 3623 return false; 3624 case '0': // First SSE register. 3625 case 't': // Any SSE register, when SSE2 is enabled. 3626 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3627 case 'm': // Any MMX register, when inter-unit moves enabled. 3628 Info.setAllowsRegister(); 3629 return true; 3630 } 3631 case 'f': // Any x87 floating point stack register. 3632 // Constraint 'f' cannot be used for output operands. 3633 if (Info.ConstraintStr[0] == '=') 3634 return false; 3635 Info.setAllowsRegister(); 3636 return true; 3637 case 'a': // eax. 3638 case 'b': // ebx. 3639 case 'c': // ecx. 3640 case 'd': // edx. 3641 case 'S': // esi. 3642 case 'D': // edi. 3643 case 'A': // edx:eax. 3644 case 't': // Top of floating point stack. 3645 case 'u': // Second from top of floating point stack. 3646 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3647 case 'y': // Any MMX register. 3648 case 'x': // Any SSE register. 3649 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3650 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3651 case 'l': // "Index" registers: any general register that can be used as an 3652 // index in a base+index memory access. 3653 Info.setAllowsRegister(); 3654 return true; 3655 // Floating point constant constraints. 3656 case 'C': // SSE floating point constant. 3657 case 'G': // x87 floating point constant. 3658 return true; 3659 } 3660 } 3661 3662 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3663 unsigned Size) const { 3664 // Strip off constraint modifiers. 3665 while (Constraint[0] == '=' || 3666 Constraint[0] == '+' || 3667 Constraint[0] == '&') 3668 Constraint = Constraint.substr(1); 3669 3670 return validateOperandSize(Constraint, Size); 3671 } 3672 3673 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3674 unsigned Size) const { 3675 return validateOperandSize(Constraint, Size); 3676 } 3677 3678 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3679 unsigned Size) const { 3680 switch (Constraint[0]) { 3681 default: break; 3682 case 'y': 3683 return Size <= 64; 3684 case 'f': 3685 case 't': 3686 case 'u': 3687 return Size <= 128; 3688 case 'x': 3689 if (SSELevel >= AVX512F) 3690 // 512-bit zmm registers can be used if target supports AVX512F. 3691 return Size <= 512U; 3692 else if (SSELevel >= AVX) 3693 // 256-bit ymm registers can be used if target supports AVX. 3694 return Size <= 256U; 3695 return Size <= 128U; 3696 case 'Y': 3697 // 'Y' is the first character for several 2-character constraints. 3698 switch (Constraint[1]) { 3699 default: break; 3700 case 'm': 3701 // 'Ym' is synonymous with 'y'. 3702 return Size <= 64; 3703 case 'i': 3704 case 't': 3705 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3706 if (SSELevel >= AVX512F) 3707 return Size <= 512U; 3708 else if (SSELevel >= AVX) 3709 return Size <= 256U; 3710 return SSELevel >= SSE2 && Size <= 128U; 3711 } 3712 3713 } 3714 3715 return true; 3716 } 3717 3718 std::string 3719 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3720 switch (*Constraint) { 3721 case 'a': return std::string("{ax}"); 3722 case 'b': return std::string("{bx}"); 3723 case 'c': return std::string("{cx}"); 3724 case 'd': return std::string("{dx}"); 3725 case 'S': return std::string("{si}"); 3726 case 'D': return std::string("{di}"); 3727 case 'p': // address 3728 return std::string("im"); 3729 case 't': // top of floating point stack. 3730 return std::string("{st}"); 3731 case 'u': // second from top of floating point stack. 3732 return std::string("{st(1)}"); // second from top of floating point stack. 3733 default: 3734 return std::string(1, *Constraint); 3735 } 3736 } 3737 3738 // X86-32 generic target 3739 class X86_32TargetInfo : public X86TargetInfo { 3740 public: 3741 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3742 DoubleAlign = LongLongAlign = 32; 3743 LongDoubleWidth = 96; 3744 LongDoubleAlign = 32; 3745 SuitableAlign = 128; 3746 DataLayoutString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3747 SizeType = UnsignedInt; 3748 PtrDiffType = SignedInt; 3749 IntPtrType = SignedInt; 3750 RegParmMax = 3; 3751 3752 // Use fpret for all types. 3753 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3754 (1 << TargetInfo::Double) | 3755 (1 << TargetInfo::LongDouble)); 3756 3757 // x86-32 has atomics up to 8 bytes 3758 // FIXME: Check that we actually have cmpxchg8b before setting 3759 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3760 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3761 } 3762 BuiltinVaListKind getBuiltinVaListKind() const override { 3763 return TargetInfo::CharPtrBuiltinVaList; 3764 } 3765 3766 int getEHDataRegisterNumber(unsigned RegNo) const override { 3767 if (RegNo == 0) return 0; 3768 if (RegNo == 1) return 2; 3769 return -1; 3770 } 3771 bool validateOperandSize(StringRef Constraint, 3772 unsigned Size) const override { 3773 switch (Constraint[0]) { 3774 default: break; 3775 case 'R': 3776 case 'q': 3777 case 'Q': 3778 case 'a': 3779 case 'b': 3780 case 'c': 3781 case 'd': 3782 case 'S': 3783 case 'D': 3784 return Size <= 32; 3785 case 'A': 3786 return Size <= 64; 3787 } 3788 3789 return X86TargetInfo::validateOperandSize(Constraint, Size); 3790 } 3791 }; 3792 3793 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3794 public: 3795 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3796 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3797 3798 unsigned getFloatEvalMethod() const override { 3799 unsigned Major, Minor, Micro; 3800 getTriple().getOSVersion(Major, Minor, Micro); 3801 // New NetBSD uses the default rounding mode. 3802 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3803 return X86_32TargetInfo::getFloatEvalMethod(); 3804 // NetBSD before 6.99.26 defaults to "double" rounding. 3805 return 1; 3806 } 3807 }; 3808 3809 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3810 public: 3811 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3812 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3813 SizeType = UnsignedLong; 3814 IntPtrType = SignedLong; 3815 PtrDiffType = SignedLong; 3816 } 3817 }; 3818 3819 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3820 public: 3821 BitrigI386TargetInfo(const llvm::Triple &Triple) 3822 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3823 SizeType = UnsignedLong; 3824 IntPtrType = SignedLong; 3825 PtrDiffType = SignedLong; 3826 } 3827 }; 3828 3829 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3830 public: 3831 DarwinI386TargetInfo(const llvm::Triple &Triple) 3832 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3833 LongDoubleWidth = 128; 3834 LongDoubleAlign = 128; 3835 SuitableAlign = 128; 3836 MaxVectorAlign = 256; 3837 // The watchOS simulator uses the builtin bool type for Objective-C. 3838 llvm::Triple T = llvm::Triple(Triple); 3839 if (T.isWatchOS()) 3840 UseSignedCharForObjCBool = false; 3841 SizeType = UnsignedLong; 3842 IntPtrType = SignedLong; 3843 DataLayoutString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3844 HasAlignMac68kSupport = true; 3845 } 3846 3847 bool handleTargetFeatures(std::vector<std::string> &Features, 3848 DiagnosticsEngine &Diags) override { 3849 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 3850 Diags)) 3851 return false; 3852 // We now know the features we have: we can decide how to align vectors. 3853 MaxVectorAlign = 3854 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3855 return true; 3856 } 3857 }; 3858 3859 // x86-32 Windows target 3860 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3861 public: 3862 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3863 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3864 WCharType = UnsignedShort; 3865 DoubleAlign = LongLongAlign = 64; 3866 bool IsWinCOFF = 3867 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3868 DataLayoutString = IsWinCOFF 3869 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3870 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3871 } 3872 void getTargetDefines(const LangOptions &Opts, 3873 MacroBuilder &Builder) const override { 3874 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3875 } 3876 }; 3877 3878 // x86-32 Windows Visual Studio target 3879 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3880 public: 3881 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3882 : WindowsX86_32TargetInfo(Triple) { 3883 LongDoubleWidth = LongDoubleAlign = 64; 3884 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3885 } 3886 void getTargetDefines(const LangOptions &Opts, 3887 MacroBuilder &Builder) const override { 3888 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3889 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3890 // The value of the following reflects processor type. 3891 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3892 // We lost the original triple, so we use the default. 3893 Builder.defineMacro("_M_IX86", "600"); 3894 } 3895 }; 3896 3897 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3898 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 3899 // supports __declspec natively under -fms-extensions, but we define a no-op 3900 // __declspec macro anyway for pre-processor compatibility. 3901 if (Opts.MicrosoftExt) 3902 Builder.defineMacro("__declspec", "__declspec"); 3903 else 3904 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3905 3906 if (!Opts.MicrosoftExt) { 3907 // Provide macros for all the calling convention keywords. Provide both 3908 // single and double underscore prefixed variants. These are available on 3909 // x64 as well as x86, even though they have no effect. 3910 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3911 for (const char *CC : CCs) { 3912 std::string GCCSpelling = "__attribute__((__"; 3913 GCCSpelling += CC; 3914 GCCSpelling += "__))"; 3915 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3916 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3917 } 3918 } 3919 } 3920 3921 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3922 Builder.defineMacro("__MSVCRT__"); 3923 Builder.defineMacro("__MINGW32__"); 3924 addCygMingDefines(Opts, Builder); 3925 } 3926 3927 // x86-32 MinGW target 3928 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3929 public: 3930 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3931 : WindowsX86_32TargetInfo(Triple) {} 3932 void getTargetDefines(const LangOptions &Opts, 3933 MacroBuilder &Builder) const override { 3934 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3935 DefineStd(Builder, "WIN32", Opts); 3936 DefineStd(Builder, "WINNT", Opts); 3937 Builder.defineMacro("_X86_"); 3938 addMinGWDefines(Opts, Builder); 3939 } 3940 }; 3941 3942 // x86-32 Cygwin target 3943 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3944 public: 3945 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3946 : X86_32TargetInfo(Triple) { 3947 WCharType = UnsignedShort; 3948 DoubleAlign = LongLongAlign = 64; 3949 DataLayoutString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3950 } 3951 void getTargetDefines(const LangOptions &Opts, 3952 MacroBuilder &Builder) const override { 3953 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3954 Builder.defineMacro("_X86_"); 3955 Builder.defineMacro("__CYGWIN__"); 3956 Builder.defineMacro("__CYGWIN32__"); 3957 addCygMingDefines(Opts, Builder); 3958 DefineStd(Builder, "unix", Opts); 3959 if (Opts.CPlusPlus) 3960 Builder.defineMacro("_GNU_SOURCE"); 3961 } 3962 }; 3963 3964 // x86-32 Haiku target 3965 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3966 public: 3967 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3968 SizeType = UnsignedLong; 3969 IntPtrType = SignedLong; 3970 PtrDiffType = SignedLong; 3971 ProcessIDType = SignedLong; 3972 this->UserLabelPrefix = ""; 3973 this->TLSSupported = false; 3974 } 3975 void getTargetDefines(const LangOptions &Opts, 3976 MacroBuilder &Builder) const override { 3977 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3978 Builder.defineMacro("__INTEL__"); 3979 Builder.defineMacro("__HAIKU__"); 3980 } 3981 }; 3982 3983 // X86-32 MCU target 3984 class MCUX86_32TargetInfo : public X86_32TargetInfo { 3985 public: 3986 MCUX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3987 LongDoubleWidth = 64; 3988 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3989 DataLayoutString = 3990 "e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"; 3991 UserLabelPrefix = ""; 3992 WIntType = UnsignedInt; 3993 } 3994 3995 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3996 // On MCU we support only C calling convention. 3997 return CC == CC_C ? CCCR_OK : CCCR_Warning; 3998 } 3999 4000 void getTargetDefines(const LangOptions &Opts, 4001 MacroBuilder &Builder) const override { 4002 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4003 Builder.defineMacro("__iamcu"); 4004 Builder.defineMacro("__iamcu__"); 4005 } 4006 4007 bool allowsLargerPreferedTypeAlignment() const override { 4008 return false; 4009 } 4010 }; 4011 4012 // RTEMS Target 4013 template<typename Target> 4014 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4015 protected: 4016 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4017 MacroBuilder &Builder) const override { 4018 // RTEMS defines; list based off of gcc output 4019 4020 Builder.defineMacro("__rtems__"); 4021 Builder.defineMacro("__ELF__"); 4022 } 4023 4024 public: 4025 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 4026 this->UserLabelPrefix = ""; 4027 4028 switch (Triple.getArch()) { 4029 default: 4030 case llvm::Triple::x86: 4031 // this->MCountName = ".mcount"; 4032 break; 4033 case llvm::Triple::mips: 4034 case llvm::Triple::mipsel: 4035 case llvm::Triple::ppc: 4036 case llvm::Triple::ppc64: 4037 case llvm::Triple::ppc64le: 4038 // this->MCountName = "_mcount"; 4039 break; 4040 case llvm::Triple::arm: 4041 // this->MCountName = "__mcount"; 4042 break; 4043 } 4044 } 4045 }; 4046 4047 // x86-32 RTEMS target 4048 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4049 public: 4050 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 4051 SizeType = UnsignedLong; 4052 IntPtrType = SignedLong; 4053 PtrDiffType = SignedLong; 4054 this->UserLabelPrefix = ""; 4055 } 4056 void getTargetDefines(const LangOptions &Opts, 4057 MacroBuilder &Builder) const override { 4058 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4059 Builder.defineMacro("__INTEL__"); 4060 Builder.defineMacro("__rtems__"); 4061 } 4062 }; 4063 4064 // x86-64 generic target 4065 class X86_64TargetInfo : public X86TargetInfo { 4066 public: 4067 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 4068 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4069 bool IsWinCOFF = 4070 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4071 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4072 LongDoubleWidth = 128; 4073 LongDoubleAlign = 128; 4074 LargeArrayMinWidth = 128; 4075 LargeArrayAlign = 128; 4076 SuitableAlign = 128; 4077 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4078 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4079 IntPtrType = IsX32 ? SignedInt : SignedLong; 4080 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4081 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4082 RegParmMax = 6; 4083 4084 // Pointers are 32-bit in x32. 4085 DataLayoutString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4086 : IsWinCOFF 4087 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4088 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 4089 4090 // Use fpret only for long double. 4091 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4092 4093 // Use fp2ret for _Complex long double. 4094 ComplexLongDoubleUsesFP2Ret = true; 4095 4096 // Make __builtin_ms_va_list available. 4097 HasBuiltinMSVaList = true; 4098 4099 // x86-64 has atomics up to 16 bytes. 4100 MaxAtomicPromoteWidth = 128; 4101 MaxAtomicInlineWidth = 128; 4102 } 4103 BuiltinVaListKind getBuiltinVaListKind() const override { 4104 return TargetInfo::X86_64ABIBuiltinVaList; 4105 } 4106 4107 int getEHDataRegisterNumber(unsigned RegNo) const override { 4108 if (RegNo == 0) return 0; 4109 if (RegNo == 1) return 1; 4110 return -1; 4111 } 4112 4113 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4114 return (CC == CC_C || 4115 CC == CC_X86VectorCall || 4116 CC == CC_IntelOclBicc || 4117 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 4118 } 4119 4120 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4121 return CC_C; 4122 } 4123 4124 // for x32 we need it here explicitly 4125 bool hasInt128Type() const override { return true; } 4126 unsigned getUnwindWordWidth() const override { return 64; } 4127 unsigned getRegisterWidth() const override { return 64; } 4128 4129 bool validateGlobalRegisterVariable(StringRef RegName, 4130 unsigned RegSize, 4131 bool &HasSizeMismatch) const override { 4132 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4133 // handle. 4134 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4135 // Check that the register size is 64-bit. 4136 HasSizeMismatch = RegSize != 64; 4137 return true; 4138 } 4139 4140 // Check if the register is a 32-bit register the backend can handle. 4141 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4142 HasSizeMismatch); 4143 } 4144 }; 4145 4146 // x86-64 Windows target 4147 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4148 public: 4149 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 4150 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 4151 WCharType = UnsignedShort; 4152 LongWidth = LongAlign = 32; 4153 DoubleAlign = LongLongAlign = 64; 4154 IntMaxType = SignedLongLong; 4155 Int64Type = SignedLongLong; 4156 SizeType = UnsignedLongLong; 4157 PtrDiffType = SignedLongLong; 4158 IntPtrType = SignedLongLong; 4159 this->UserLabelPrefix = ""; 4160 } 4161 4162 void getTargetDefines(const LangOptions &Opts, 4163 MacroBuilder &Builder) const override { 4164 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4165 Builder.defineMacro("_WIN64"); 4166 } 4167 4168 BuiltinVaListKind getBuiltinVaListKind() const override { 4169 return TargetInfo::CharPtrBuiltinVaList; 4170 } 4171 4172 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4173 switch (CC) { 4174 case CC_X86StdCall: 4175 case CC_X86ThisCall: 4176 case CC_X86FastCall: 4177 return CCCR_Ignore; 4178 case CC_C: 4179 case CC_X86VectorCall: 4180 case CC_IntelOclBicc: 4181 case CC_X86_64SysV: 4182 return CCCR_OK; 4183 default: 4184 return CCCR_Warning; 4185 } 4186 } 4187 }; 4188 4189 // x86-64 Windows Visual Studio target 4190 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4191 public: 4192 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 4193 : WindowsX86_64TargetInfo(Triple) { 4194 LongDoubleWidth = LongDoubleAlign = 64; 4195 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4196 } 4197 void getTargetDefines(const LangOptions &Opts, 4198 MacroBuilder &Builder) const override { 4199 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4200 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4201 Builder.defineMacro("_M_X64", "100"); 4202 Builder.defineMacro("_M_AMD64", "100"); 4203 } 4204 }; 4205 4206 // x86-64 MinGW target 4207 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4208 public: 4209 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 4210 : WindowsX86_64TargetInfo(Triple) { 4211 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4212 // with x86 FP ops. Weird. 4213 LongDoubleWidth = LongDoubleAlign = 128; 4214 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4215 } 4216 4217 void getTargetDefines(const LangOptions &Opts, 4218 MacroBuilder &Builder) const override { 4219 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4220 DefineStd(Builder, "WIN64", Opts); 4221 Builder.defineMacro("__MINGW64__"); 4222 addMinGWDefines(Opts, Builder); 4223 4224 // GCC defines this macro when it is using __gxx_personality_seh0. 4225 if (!Opts.SjLjExceptions) 4226 Builder.defineMacro("__SEH__"); 4227 } 4228 }; 4229 4230 // x86-64 Cygwin target 4231 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4232 public: 4233 CygwinX86_64TargetInfo(const llvm::Triple &Triple) 4234 : X86_64TargetInfo(Triple) { 4235 TLSSupported = false; 4236 WCharType = UnsignedShort; 4237 UserLabelPrefix = ""; 4238 } 4239 void getTargetDefines(const LangOptions &Opts, 4240 MacroBuilder &Builder) const override { 4241 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4242 Builder.defineMacro("__x86_64__"); 4243 Builder.defineMacro("__CYGWIN__"); 4244 Builder.defineMacro("__CYGWIN64__"); 4245 addCygMingDefines(Opts, Builder); 4246 DefineStd(Builder, "unix", Opts); 4247 if (Opts.CPlusPlus) 4248 Builder.defineMacro("_GNU_SOURCE"); 4249 4250 // GCC defines this macro when it is using __gxx_personality_seh0. 4251 if (!Opts.SjLjExceptions) 4252 Builder.defineMacro("__SEH__"); 4253 } 4254 }; 4255 4256 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4257 public: 4258 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 4259 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 4260 Int64Type = SignedLongLong; 4261 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4262 llvm::Triple T = llvm::Triple(Triple); 4263 if (T.isiOS()) 4264 UseSignedCharForObjCBool = false; 4265 DataLayoutString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 4266 } 4267 4268 bool handleTargetFeatures(std::vector<std::string> &Features, 4269 DiagnosticsEngine &Diags) override { 4270 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4271 Diags)) 4272 return false; 4273 // We now know the features we have: we can decide how to align vectors. 4274 MaxVectorAlign = 4275 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4276 return true; 4277 } 4278 }; 4279 4280 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4281 public: 4282 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 4283 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 4284 IntMaxType = SignedLongLong; 4285 Int64Type = SignedLongLong; 4286 } 4287 }; 4288 4289 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4290 public: 4291 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 4292 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 4293 IntMaxType = SignedLongLong; 4294 Int64Type = SignedLongLong; 4295 } 4296 }; 4297 4298 class ARMTargetInfo : public TargetInfo { 4299 // Possible FPU choices. 4300 enum FPUMode { 4301 VFP2FPU = (1 << 0), 4302 VFP3FPU = (1 << 1), 4303 VFP4FPU = (1 << 2), 4304 NeonFPU = (1 << 3), 4305 FPARMV8 = (1 << 4) 4306 }; 4307 4308 // Possible HWDiv features. 4309 enum HWDivMode { 4310 HWDivThumb = (1 << 0), 4311 HWDivARM = (1 << 1) 4312 }; 4313 4314 static bool FPUModeIsVFP(FPUMode Mode) { 4315 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4316 } 4317 4318 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4319 static const char * const GCCRegNames[]; 4320 4321 std::string ABI, CPU; 4322 4323 StringRef CPUProfile; 4324 StringRef CPUAttr; 4325 4326 enum { 4327 FP_Default, 4328 FP_VFP, 4329 FP_Neon 4330 } FPMath; 4331 4332 unsigned ArchISA; 4333 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4334 unsigned ArchProfile; 4335 unsigned ArchVersion; 4336 4337 unsigned FPU : 5; 4338 4339 unsigned IsAAPCS : 1; 4340 unsigned HWDiv : 2; 4341 4342 // Initialized via features. 4343 unsigned SoftFloat : 1; 4344 unsigned SoftFloatABI : 1; 4345 4346 unsigned CRC : 1; 4347 unsigned Crypto : 1; 4348 unsigned DSP : 1; 4349 unsigned Unaligned : 1; 4350 4351 enum { 4352 LDREX_B = (1 << 0), /// byte (8-bit) 4353 LDREX_H = (1 << 1), /// half (16-bit) 4354 LDREX_W = (1 << 2), /// word (32-bit) 4355 LDREX_D = (1 << 3), /// double (64-bit) 4356 }; 4357 4358 uint32_t LDREX; 4359 4360 // ACLE 6.5.1 Hardware floating point 4361 enum { 4362 HW_FP_HP = (1 << 1), /// half (16-bit) 4363 HW_FP_SP = (1 << 2), /// single (32-bit) 4364 HW_FP_DP = (1 << 3), /// double (64-bit) 4365 }; 4366 uint32_t HW_FP; 4367 4368 static const Builtin::Info BuiltinInfo[]; 4369 4370 void setABIAAPCS() { 4371 IsAAPCS = true; 4372 4373 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4374 const llvm::Triple &T = getTriple(); 4375 4376 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4377 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4378 T.getOS() == llvm::Triple::Bitrig) 4379 SizeType = UnsignedLong; 4380 else 4381 SizeType = UnsignedInt; 4382 4383 switch (T.getOS()) { 4384 case llvm::Triple::NetBSD: 4385 WCharType = SignedInt; 4386 break; 4387 case llvm::Triple::Win32: 4388 WCharType = UnsignedShort; 4389 break; 4390 case llvm::Triple::Linux: 4391 default: 4392 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4393 WCharType = UnsignedInt; 4394 break; 4395 } 4396 4397 UseBitFieldTypeAlignment = true; 4398 4399 ZeroLengthBitfieldBoundary = 0; 4400 4401 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4402 // so set preferred for small types to 32. 4403 if (T.isOSBinFormatMachO()) { 4404 DataLayoutString = 4405 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4406 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4407 } else if (T.isOSWindows()) { 4408 assert(!BigEndian && "Windows on ARM does not support big endian"); 4409 DataLayoutString = "e" 4410 "-m:w" 4411 "-p:32:32" 4412 "-i64:64" 4413 "-v128:64:128" 4414 "-a:0:32" 4415 "-n32" 4416 "-S64"; 4417 } else if (T.isOSNaCl()) { 4418 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4419 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 4420 } else { 4421 DataLayoutString = 4422 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4423 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4424 } 4425 4426 // FIXME: Enumerated types are variable width in straight AAPCS. 4427 } 4428 4429 void setABIAPCS(bool IsAAPCS16) { 4430 const llvm::Triple &T = getTriple(); 4431 4432 IsAAPCS = false; 4433 4434 if (IsAAPCS16) 4435 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4436 else 4437 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4438 4439 // size_t is unsigned int on FreeBSD. 4440 if (T.getOS() == llvm::Triple::FreeBSD) 4441 SizeType = UnsignedInt; 4442 else 4443 SizeType = UnsignedLong; 4444 4445 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4446 WCharType = SignedInt; 4447 4448 // Do not respect the alignment of bit-field types when laying out 4449 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4450 UseBitFieldTypeAlignment = false; 4451 4452 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4453 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4454 /// gcc. 4455 ZeroLengthBitfieldBoundary = 32; 4456 4457 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4458 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4459 DataLayoutString = "e-m:o-p:32:32-i64:64-a:0:32-n32-S128"; 4460 } else if (T.isOSBinFormatMachO()) 4461 DataLayoutString = 4462 BigEndian 4463 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4464 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4465 else 4466 DataLayoutString = 4467 BigEndian 4468 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4469 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4470 4471 // FIXME: Override "preferred align" for double and long long. 4472 } 4473 4474 void setArchInfo() { 4475 StringRef ArchName = getTriple().getArchName(); 4476 4477 ArchISA = llvm::ARM::parseArchISA(ArchName); 4478 CPU = llvm::ARM::getDefaultCPU(ArchName); 4479 unsigned AK = llvm::ARM::parseArch(ArchName); 4480 if (AK != llvm::ARM::AK_INVALID) 4481 ArchKind = AK; 4482 setArchInfo(ArchKind); 4483 } 4484 4485 void setArchInfo(unsigned Kind) { 4486 StringRef SubArch; 4487 4488 // cache TargetParser info 4489 ArchKind = Kind; 4490 SubArch = llvm::ARM::getSubArch(ArchKind); 4491 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4492 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4493 4494 // cache CPU related strings 4495 CPUAttr = getCPUAttr(); 4496 CPUProfile = getCPUProfile(); 4497 } 4498 4499 void setAtomic() { 4500 // when triple does not specify a sub arch, 4501 // then we are not using inline atomics 4502 bool ShouldUseInlineAtomic = 4503 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4504 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4505 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4506 if (ArchProfile == llvm::ARM::PK_M) { 4507 MaxAtomicPromoteWidth = 32; 4508 if (ShouldUseInlineAtomic) 4509 MaxAtomicInlineWidth = 32; 4510 } 4511 else { 4512 MaxAtomicPromoteWidth = 64; 4513 if (ShouldUseInlineAtomic) 4514 MaxAtomicInlineWidth = 64; 4515 } 4516 } 4517 4518 bool isThumb() const { 4519 return (ArchISA == llvm::ARM::IK_THUMB); 4520 } 4521 4522 bool supportsThumb() const { 4523 return CPUAttr.count('T') || ArchVersion >= 6; 4524 } 4525 4526 bool supportsThumb2() const { 4527 return CPUAttr.equals("6T2") || ArchVersion >= 7; 4528 } 4529 4530 StringRef getCPUAttr() const { 4531 // For most sub-arches, the build attribute CPU name is enough. 4532 // For Cortex variants, it's slightly different. 4533 switch(ArchKind) { 4534 default: 4535 return llvm::ARM::getCPUAttr(ArchKind); 4536 case llvm::ARM::AK_ARMV6M: 4537 return "6M"; 4538 case llvm::ARM::AK_ARMV7S: 4539 return "7S"; 4540 case llvm::ARM::AK_ARMV7A: 4541 return "7A"; 4542 case llvm::ARM::AK_ARMV7R: 4543 return "7R"; 4544 case llvm::ARM::AK_ARMV7M: 4545 return "7M"; 4546 case llvm::ARM::AK_ARMV7EM: 4547 return "7EM"; 4548 case llvm::ARM::AK_ARMV8A: 4549 return "8A"; 4550 case llvm::ARM::AK_ARMV8_1A: 4551 return "8_1A"; 4552 case llvm::ARM::AK_ARMV8_2A: 4553 return "8_2A"; 4554 } 4555 } 4556 4557 StringRef getCPUProfile() const { 4558 switch(ArchProfile) { 4559 case llvm::ARM::PK_A: 4560 return "A"; 4561 case llvm::ARM::PK_R: 4562 return "R"; 4563 case llvm::ARM::PK_M: 4564 return "M"; 4565 default: 4566 return ""; 4567 } 4568 } 4569 4570 public: 4571 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4572 : TargetInfo(Triple), FPMath(FP_Default), 4573 IsAAPCS(true), LDREX(0), HW_FP(0) { 4574 BigEndian = IsBigEndian; 4575 4576 switch (getTriple().getOS()) { 4577 case llvm::Triple::NetBSD: 4578 PtrDiffType = SignedLong; 4579 break; 4580 default: 4581 PtrDiffType = SignedInt; 4582 break; 4583 } 4584 4585 // Cache arch related info. 4586 setArchInfo(); 4587 4588 // {} in inline assembly are neon specifiers, not assembly variant 4589 // specifiers. 4590 NoAsmVariants = true; 4591 4592 // FIXME: This duplicates code from the driver that sets the -target-abi 4593 // option - this code is used if -target-abi isn't passed and should 4594 // be unified in some way. 4595 if (Triple.isOSBinFormatMachO()) { 4596 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4597 // the frontend matches that. 4598 if (Triple.getEnvironment() == llvm::Triple::EABI || 4599 Triple.getOS() == llvm::Triple::UnknownOS || 4600 StringRef(CPU).startswith("cortex-m")) { 4601 setABI("aapcs"); 4602 } else if (Triple.isWatchABI()) { 4603 setABI("aapcs16"); 4604 } else { 4605 setABI("apcs-gnu"); 4606 } 4607 } else if (Triple.isOSWindows()) { 4608 // FIXME: this is invalid for WindowsCE 4609 setABI("aapcs"); 4610 } else { 4611 // Select the default based on the platform. 4612 switch (Triple.getEnvironment()) { 4613 case llvm::Triple::Android: 4614 case llvm::Triple::GNUEABI: 4615 case llvm::Triple::GNUEABIHF: 4616 setABI("aapcs-linux"); 4617 break; 4618 case llvm::Triple::EABIHF: 4619 case llvm::Triple::EABI: 4620 setABI("aapcs"); 4621 break; 4622 case llvm::Triple::GNU: 4623 setABI("apcs-gnu"); 4624 break; 4625 default: 4626 if (Triple.getOS() == llvm::Triple::NetBSD) 4627 setABI("apcs-gnu"); 4628 else 4629 setABI("aapcs"); 4630 break; 4631 } 4632 } 4633 4634 // ARM targets default to using the ARM C++ ABI. 4635 TheCXXABI.set(TargetCXXABI::GenericARM); 4636 4637 // ARM has atomics up to 8 bytes 4638 setAtomic(); 4639 4640 // Do force alignment of members that follow zero length bitfields. If 4641 // the alignment of the zero-length bitfield is greater than the member 4642 // that follows it, `bar', `bar' will be aligned as the type of the 4643 // zero length bitfield. 4644 UseZeroLengthBitfieldAlignment = true; 4645 } 4646 4647 StringRef getABI() const override { return ABI; } 4648 4649 bool setABI(const std::string &Name) override { 4650 ABI = Name; 4651 4652 // The defaults (above) are for AAPCS, check if we need to change them. 4653 // 4654 // FIXME: We need support for -meabi... we could just mangle it into the 4655 // name. 4656 if (Name == "apcs-gnu" || Name == "aapcs16") { 4657 setABIAPCS(Name == "aapcs16"); 4658 return true; 4659 } 4660 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4661 setABIAAPCS(); 4662 return true; 4663 } 4664 return false; 4665 } 4666 4667 // FIXME: This should be based on Arch attributes, not CPU names. 4668 bool 4669 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4670 StringRef CPU, 4671 const std::vector<std::string> &FeaturesVec) const override { 4672 4673 std::vector<const char*> TargetFeatures; 4674 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4675 4676 // get default FPU features 4677 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4678 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4679 4680 // get default Extension features 4681 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 4682 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4683 4684 for (const char *Feature : TargetFeatures) 4685 if (Feature[0] == '+') 4686 Features[Feature+1] = true; 4687 4688 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4689 } 4690 4691 bool handleTargetFeatures(std::vector<std::string> &Features, 4692 DiagnosticsEngine &Diags) override { 4693 FPU = 0; 4694 CRC = 0; 4695 Crypto = 0; 4696 DSP = 0; 4697 Unaligned = 1; 4698 SoftFloat = SoftFloatABI = false; 4699 HWDiv = 0; 4700 4701 // This does not diagnose illegal cases like having both 4702 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4703 uint32_t HW_FP_remove = 0; 4704 for (const auto &Feature : Features) { 4705 if (Feature == "+soft-float") { 4706 SoftFloat = true; 4707 } else if (Feature == "+soft-float-abi") { 4708 SoftFloatABI = true; 4709 } else if (Feature == "+vfp2") { 4710 FPU |= VFP2FPU; 4711 HW_FP |= HW_FP_SP | HW_FP_DP; 4712 } else if (Feature == "+vfp3") { 4713 FPU |= VFP3FPU; 4714 HW_FP |= HW_FP_SP | HW_FP_DP; 4715 } else if (Feature == "+vfp4") { 4716 FPU |= VFP4FPU; 4717 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4718 } else if (Feature == "+fp-armv8") { 4719 FPU |= FPARMV8; 4720 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4721 } else if (Feature == "+neon") { 4722 FPU |= NeonFPU; 4723 HW_FP |= HW_FP_SP | HW_FP_DP; 4724 } else if (Feature == "+hwdiv") { 4725 HWDiv |= HWDivThumb; 4726 } else if (Feature == "+hwdiv-arm") { 4727 HWDiv |= HWDivARM; 4728 } else if (Feature == "+crc") { 4729 CRC = 1; 4730 } else if (Feature == "+crypto") { 4731 Crypto = 1; 4732 } else if (Feature == "+dsp") { 4733 DSP = 1; 4734 } else if (Feature == "+fp-only-sp") { 4735 HW_FP_remove |= HW_FP_DP; 4736 } else if (Feature == "+strict-align") { 4737 Unaligned = 0; 4738 } else if (Feature == "+fp16") { 4739 HW_FP |= HW_FP_HP; 4740 } 4741 } 4742 HW_FP &= ~HW_FP_remove; 4743 4744 switch (ArchVersion) { 4745 case 6: 4746 if (ArchProfile == llvm::ARM::PK_M) 4747 LDREX = 0; 4748 else if (ArchKind == llvm::ARM::AK_ARMV6K) 4749 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4750 else 4751 LDREX = LDREX_W; 4752 break; 4753 case 7: 4754 if (ArchProfile == llvm::ARM::PK_M) 4755 LDREX = LDREX_W | LDREX_H | LDREX_B ; 4756 else 4757 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4758 break; 4759 case 8: 4760 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4761 } 4762 4763 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4764 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4765 return false; 4766 } 4767 4768 if (FPMath == FP_Neon) 4769 Features.push_back("+neonfp"); 4770 else if (FPMath == FP_VFP) 4771 Features.push_back("-neonfp"); 4772 4773 // Remove front-end specific options which the backend handles differently. 4774 auto Feature = 4775 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4776 if (Feature != Features.end()) 4777 Features.erase(Feature); 4778 4779 return true; 4780 } 4781 4782 bool hasFeature(StringRef Feature) const override { 4783 return llvm::StringSwitch<bool>(Feature) 4784 .Case("arm", true) 4785 .Case("aarch32", true) 4786 .Case("softfloat", SoftFloat) 4787 .Case("thumb", isThumb()) 4788 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4789 .Case("hwdiv", HWDiv & HWDivThumb) 4790 .Case("hwdiv-arm", HWDiv & HWDivARM) 4791 .Default(false); 4792 } 4793 4794 bool setCPU(const std::string &Name) override { 4795 if (Name != "generic") 4796 setArchInfo(llvm::ARM::parseCPUArch(Name)); 4797 4798 if (ArchKind == llvm::ARM::AK_INVALID) 4799 return false; 4800 setAtomic(); 4801 CPU = Name; 4802 return true; 4803 } 4804 4805 bool setFPMath(StringRef Name) override; 4806 4807 void getTargetDefines(const LangOptions &Opts, 4808 MacroBuilder &Builder) const override { 4809 // Target identification. 4810 Builder.defineMacro("__arm"); 4811 Builder.defineMacro("__arm__"); 4812 4813 // Target properties. 4814 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4815 4816 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 4817 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 4818 if (getTriple().isWatchABI()) 4819 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 4820 4821 if (!CPUAttr.empty()) 4822 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 4823 4824 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4825 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4826 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 4827 4828 if (ArchVersion >= 8) { 4829 // ACLE 6.5.7 Crypto Extension 4830 if (Crypto) 4831 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 4832 // ACLE 6.5.8 CRC32 Extension 4833 if (CRC) 4834 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 4835 // ACLE 6.5.10 Numeric Maximum and Minimum 4836 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 4837 // ACLE 6.5.9 Directed Rounding 4838 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 4839 } 4840 4841 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4842 // is not defined for the M-profile. 4843 // NOTE that the deffault profile is assumed to be 'A' 4844 if (CPUProfile.empty() || CPUProfile != "M") 4845 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4846 4847 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4848 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4849 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4850 if (supportsThumb2()) 4851 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4852 else if (supportsThumb()) 4853 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4854 4855 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4856 // instruction set such as ARM or Thumb. 4857 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4858 4859 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4860 4861 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4862 if (!CPUProfile.empty()) 4863 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4864 4865 // ACLE 6.4.3 Unaligned access supported in hardware 4866 if (Unaligned) 4867 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 4868 4869 // ACLE 6.4.4 LDREX/STREX 4870 if (LDREX) 4871 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 4872 4873 // ACLE 6.4.5 CLZ 4874 if (ArchVersion == 5 || 4875 (ArchVersion == 6 && CPUProfile != "M") || 4876 ArchVersion > 6) 4877 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 4878 4879 // ACLE 6.5.1 Hardware Floating Point 4880 if (HW_FP) 4881 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4882 4883 // ACLE predefines. 4884 Builder.defineMacro("__ARM_ACLE", "200"); 4885 4886 // FP16 support (we currently only support IEEE format). 4887 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 4888 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 4889 4890 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 4891 if (ArchVersion >= 7 && (CPUProfile != "M" || CPUAttr == "7EM")) 4892 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 4893 4894 // Subtarget options. 4895 4896 // FIXME: It's more complicated than this and we don't really support 4897 // interworking. 4898 // Windows on ARM does not "support" interworking 4899 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 4900 Builder.defineMacro("__THUMB_INTERWORK__"); 4901 4902 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4903 // Embedded targets on Darwin follow AAPCS, but not EABI. 4904 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4905 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4906 Builder.defineMacro("__ARM_EABI__"); 4907 Builder.defineMacro("__ARM_PCS", "1"); 4908 4909 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4910 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4911 } 4912 4913 if (SoftFloat) 4914 Builder.defineMacro("__SOFTFP__"); 4915 4916 if (CPU == "xscale") 4917 Builder.defineMacro("__XSCALE__"); 4918 4919 if (isThumb()) { 4920 Builder.defineMacro("__THUMBEL__"); 4921 Builder.defineMacro("__thumb__"); 4922 if (supportsThumb2()) 4923 Builder.defineMacro("__thumb2__"); 4924 } 4925 4926 // ACLE 6.4.9 32-bit SIMD instructions 4927 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 4928 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 4929 4930 // ACLE 6.4.10 Hardware Integer Divide 4931 if (((HWDiv & HWDivThumb) && isThumb()) || 4932 ((HWDiv & HWDivARM) && !isThumb())) { 4933 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 4934 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4935 } 4936 4937 // Note, this is always on in gcc, even though it doesn't make sense. 4938 Builder.defineMacro("__APCS_32__"); 4939 4940 if (FPUModeIsVFP((FPUMode) FPU)) { 4941 Builder.defineMacro("__VFP_FP__"); 4942 if (FPU & VFP2FPU) 4943 Builder.defineMacro("__ARM_VFPV2__"); 4944 if (FPU & VFP3FPU) 4945 Builder.defineMacro("__ARM_VFPV3__"); 4946 if (FPU & VFP4FPU) 4947 Builder.defineMacro("__ARM_VFPV4__"); 4948 } 4949 4950 // This only gets set when Neon instructions are actually available, unlike 4951 // the VFP define, hence the soft float and arch check. This is subtly 4952 // different from gcc, we follow the intent which was that it should be set 4953 // when Neon instructions are actually available. 4954 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 4955 Builder.defineMacro("__ARM_NEON", "1"); 4956 Builder.defineMacro("__ARM_NEON__"); 4957 // current AArch32 NEON implementations do not support double-precision 4958 // floating-point even when it is present in VFP. 4959 Builder.defineMacro("__ARM_NEON_FP", 4960 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 4961 } 4962 4963 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4964 Opts.ShortWChar ? "2" : "4"); 4965 4966 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4967 Opts.ShortEnums ? "1" : "4"); 4968 4969 if (ArchVersion >= 6 && CPUAttr != "6M") { 4970 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4971 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4972 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4973 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4974 } 4975 4976 // ACLE 6.4.7 DSP instructions 4977 if (DSP) { 4978 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 4979 } 4980 4981 // ACLE 6.4.8 Saturation instructions 4982 bool SAT = false; 4983 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 4984 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 4985 SAT = true; 4986 } 4987 4988 // ACLE 6.4.6 Q (saturation) flag 4989 if (DSP || SAT) 4990 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 4991 4992 if (Opts.UnsafeFPMath) 4993 Builder.defineMacro("__ARM_FP_FAST", "1"); 4994 4995 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 4996 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 4997 } 4998 4999 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5000 return llvm::makeArrayRef(BuiltinInfo, 5001 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5002 } 5003 bool isCLZForZeroUndef() const override { return false; } 5004 BuiltinVaListKind getBuiltinVaListKind() const override { 5005 return IsAAPCS 5006 ? AAPCSABIBuiltinVaList 5007 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5008 : TargetInfo::VoidPtrBuiltinVaList); 5009 } 5010 ArrayRef<const char *> getGCCRegNames() const override; 5011 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5012 bool validateAsmConstraint(const char *&Name, 5013 TargetInfo::ConstraintInfo &Info) const override { 5014 switch (*Name) { 5015 default: break; 5016 case 'l': // r0-r7 5017 case 'h': // r8-r15 5018 case 't': // VFP Floating point register single precision 5019 case 'w': // VFP Floating point register double precision 5020 Info.setAllowsRegister(); 5021 return true; 5022 case 'I': 5023 case 'J': 5024 case 'K': 5025 case 'L': 5026 case 'M': 5027 // FIXME 5028 return true; 5029 case 'Q': // A memory address that is a single base register. 5030 Info.setAllowsMemory(); 5031 return true; 5032 case 'U': // a memory reference... 5033 switch (Name[1]) { 5034 case 'q': // ...ARMV4 ldrsb 5035 case 'v': // ...VFP load/store (reg+constant offset) 5036 case 'y': // ...iWMMXt load/store 5037 case 't': // address valid for load/store opaque types wider 5038 // than 128-bits 5039 case 'n': // valid address for Neon doubleword vector load/store 5040 case 'm': // valid address for Neon element and structure load/store 5041 case 's': // valid address for non-offset loads/stores of quad-word 5042 // values in four ARM registers 5043 Info.setAllowsMemory(); 5044 Name++; 5045 return true; 5046 } 5047 } 5048 return false; 5049 } 5050 std::string convertConstraint(const char *&Constraint) const override { 5051 std::string R; 5052 switch (*Constraint) { 5053 case 'U': // Two-character constraint; add "^" hint for later parsing. 5054 R = std::string("^") + std::string(Constraint, 2); 5055 Constraint++; 5056 break; 5057 case 'p': // 'p' should be translated to 'r' by default. 5058 R = std::string("r"); 5059 break; 5060 default: 5061 return std::string(1, *Constraint); 5062 } 5063 return R; 5064 } 5065 bool 5066 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5067 std::string &SuggestedModifier) const override { 5068 bool isOutput = (Constraint[0] == '='); 5069 bool isInOut = (Constraint[0] == '+'); 5070 5071 // Strip off constraint modifiers. 5072 while (Constraint[0] == '=' || 5073 Constraint[0] == '+' || 5074 Constraint[0] == '&') 5075 Constraint = Constraint.substr(1); 5076 5077 switch (Constraint[0]) { 5078 default: break; 5079 case 'r': { 5080 switch (Modifier) { 5081 default: 5082 return (isInOut || isOutput || Size <= 64); 5083 case 'q': 5084 // A register of size 32 cannot fit a vector type. 5085 return false; 5086 } 5087 } 5088 } 5089 5090 return true; 5091 } 5092 const char *getClobbers() const override { 5093 // FIXME: Is this really right? 5094 return ""; 5095 } 5096 5097 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5098 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 5099 } 5100 5101 int getEHDataRegisterNumber(unsigned RegNo) const override { 5102 if (RegNo == 0) return 0; 5103 if (RegNo == 1) return 1; 5104 return -1; 5105 } 5106 5107 bool hasSjLjLowering() const override { 5108 return true; 5109 } 5110 }; 5111 5112 bool ARMTargetInfo::setFPMath(StringRef Name) { 5113 if (Name == "neon") { 5114 FPMath = FP_Neon; 5115 return true; 5116 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5117 Name == "vfp4") { 5118 FPMath = FP_VFP; 5119 return true; 5120 } 5121 return false; 5122 } 5123 5124 const char * const ARMTargetInfo::GCCRegNames[] = { 5125 // Integer registers 5126 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5127 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5128 5129 // Float registers 5130 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5131 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5132 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5133 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5134 5135 // Double registers 5136 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5137 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5138 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5139 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5140 5141 // Quad registers 5142 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5143 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5144 }; 5145 5146 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5147 return llvm::makeArrayRef(GCCRegNames); 5148 } 5149 5150 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5151 { { "a1" }, "r0" }, 5152 { { "a2" }, "r1" }, 5153 { { "a3" }, "r2" }, 5154 { { "a4" }, "r3" }, 5155 { { "v1" }, "r4" }, 5156 { { "v2" }, "r5" }, 5157 { { "v3" }, "r6" }, 5158 { { "v4" }, "r7" }, 5159 { { "v5" }, "r8" }, 5160 { { "v6", "rfp" }, "r9" }, 5161 { { "sl" }, "r10" }, 5162 { { "fp" }, "r11" }, 5163 { { "ip" }, "r12" }, 5164 { { "r13" }, "sp" }, 5165 { { "r14" }, "lr" }, 5166 { { "r15" }, "pc" }, 5167 // The S, D and Q registers overlap, but aren't really aliases; we 5168 // don't want to substitute one of these for a different-sized one. 5169 }; 5170 5171 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5172 return llvm::makeArrayRef(GCCRegAliases); 5173 } 5174 5175 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5176 #define BUILTIN(ID, TYPE, ATTRS) \ 5177 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5178 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5179 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5180 #include "clang/Basic/BuiltinsNEON.def" 5181 5182 #define BUILTIN(ID, TYPE, ATTRS) \ 5183 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5184 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5185 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5186 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5187 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5188 #include "clang/Basic/BuiltinsARM.def" 5189 }; 5190 5191 class ARMleTargetInfo : public ARMTargetInfo { 5192 public: 5193 ARMleTargetInfo(const llvm::Triple &Triple) 5194 : ARMTargetInfo(Triple, false) { } 5195 void getTargetDefines(const LangOptions &Opts, 5196 MacroBuilder &Builder) const override { 5197 Builder.defineMacro("__ARMEL__"); 5198 ARMTargetInfo::getTargetDefines(Opts, Builder); 5199 } 5200 }; 5201 5202 class ARMbeTargetInfo : public ARMTargetInfo { 5203 public: 5204 ARMbeTargetInfo(const llvm::Triple &Triple) 5205 : ARMTargetInfo(Triple, true) { } 5206 void getTargetDefines(const LangOptions &Opts, 5207 MacroBuilder &Builder) const override { 5208 Builder.defineMacro("__ARMEB__"); 5209 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5210 ARMTargetInfo::getTargetDefines(Opts, Builder); 5211 } 5212 }; 5213 5214 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5215 const llvm::Triple Triple; 5216 public: 5217 WindowsARMTargetInfo(const llvm::Triple &Triple) 5218 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 5219 WCharType = UnsignedShort; 5220 SizeType = UnsignedInt; 5221 UserLabelPrefix = ""; 5222 } 5223 void getVisualStudioDefines(const LangOptions &Opts, 5224 MacroBuilder &Builder) const { 5225 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5226 5227 // FIXME: this is invalid for WindowsCE 5228 Builder.defineMacro("_M_ARM_NT", "1"); 5229 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5230 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5231 5232 assert((Triple.getArch() == llvm::Triple::arm || 5233 Triple.getArch() == llvm::Triple::thumb) && 5234 "invalid architecture for Windows ARM target info"); 5235 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5236 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5237 5238 // TODO map the complete set of values 5239 // 31: VFPv3 40: VFPv4 5240 Builder.defineMacro("_M_ARM_FP", "31"); 5241 } 5242 BuiltinVaListKind getBuiltinVaListKind() const override { 5243 return TargetInfo::CharPtrBuiltinVaList; 5244 } 5245 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5246 switch (CC) { 5247 case CC_X86StdCall: 5248 case CC_X86ThisCall: 5249 case CC_X86FastCall: 5250 case CC_X86VectorCall: 5251 return CCCR_Ignore; 5252 case CC_C: 5253 return CCCR_OK; 5254 default: 5255 return CCCR_Warning; 5256 } 5257 } 5258 }; 5259 5260 // Windows ARM + Itanium C++ ABI Target 5261 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5262 public: 5263 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 5264 : WindowsARMTargetInfo(Triple) { 5265 TheCXXABI.set(TargetCXXABI::GenericARM); 5266 } 5267 5268 void getTargetDefines(const LangOptions &Opts, 5269 MacroBuilder &Builder) const override { 5270 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5271 5272 if (Opts.MSVCCompat) 5273 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5274 } 5275 }; 5276 5277 // Windows ARM, MS (C++) ABI 5278 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5279 public: 5280 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 5281 : WindowsARMTargetInfo(Triple) { 5282 TheCXXABI.set(TargetCXXABI::Microsoft); 5283 } 5284 5285 void getTargetDefines(const LangOptions &Opts, 5286 MacroBuilder &Builder) const override { 5287 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5288 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5289 } 5290 }; 5291 5292 // ARM MinGW target 5293 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5294 public: 5295 MinGWARMTargetInfo(const llvm::Triple &Triple) 5296 : WindowsARMTargetInfo(Triple) { 5297 TheCXXABI.set(TargetCXXABI::GenericARM); 5298 } 5299 5300 void getTargetDefines(const LangOptions &Opts, 5301 MacroBuilder &Builder) const override { 5302 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5303 DefineStd(Builder, "WIN32", Opts); 5304 DefineStd(Builder, "WINNT", Opts); 5305 Builder.defineMacro("_ARM_"); 5306 addMinGWDefines(Opts, Builder); 5307 } 5308 }; 5309 5310 // ARM Cygwin target 5311 class CygwinARMTargetInfo : public ARMleTargetInfo { 5312 public: 5313 CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) { 5314 TLSSupported = false; 5315 WCharType = UnsignedShort; 5316 DoubleAlign = LongLongAlign = 64; 5317 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 5318 } 5319 void getTargetDefines(const LangOptions &Opts, 5320 MacroBuilder &Builder) const override { 5321 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5322 Builder.defineMacro("_ARM_"); 5323 Builder.defineMacro("__CYGWIN__"); 5324 Builder.defineMacro("__CYGWIN32__"); 5325 DefineStd(Builder, "unix", Opts); 5326 if (Opts.CPlusPlus) 5327 Builder.defineMacro("_GNU_SOURCE"); 5328 } 5329 }; 5330 5331 class DarwinARMTargetInfo : 5332 public DarwinTargetInfo<ARMleTargetInfo> { 5333 protected: 5334 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5335 MacroBuilder &Builder) const override { 5336 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5337 } 5338 5339 public: 5340 DarwinARMTargetInfo(const llvm::Triple &Triple) 5341 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 5342 HasAlignMac68kSupport = true; 5343 // iOS always has 64-bit atomic instructions. 5344 // FIXME: This should be based off of the target features in 5345 // ARMleTargetInfo. 5346 MaxAtomicInlineWidth = 64; 5347 5348 if (Triple.isWatchABI()) { 5349 // Darwin on iOS uses a variant of the ARM C++ ABI. 5350 TheCXXABI.set(TargetCXXABI::WatchOS); 5351 5352 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5353 // size_t is long, it's a bit weird for it to be int. 5354 PtrDiffType = SignedLong; 5355 5356 // BOOL should be a real boolean on the new ABI 5357 UseSignedCharForObjCBool = false; 5358 } else 5359 TheCXXABI.set(TargetCXXABI::iOS); 5360 } 5361 }; 5362 5363 class AArch64TargetInfo : public TargetInfo { 5364 virtual void setDataLayoutString() = 0; 5365 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5366 static const char *const GCCRegNames[]; 5367 5368 enum FPUModeEnum { 5369 FPUMode, 5370 NeonMode 5371 }; 5372 5373 unsigned FPU; 5374 unsigned CRC; 5375 unsigned Crypto; 5376 unsigned Unaligned; 5377 unsigned V8_1A; 5378 5379 static const Builtin::Info BuiltinInfo[]; 5380 5381 std::string ABI; 5382 5383 public: 5384 AArch64TargetInfo(const llvm::Triple &Triple) 5385 : TargetInfo(Triple), ABI("aapcs") { 5386 5387 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5388 WCharType = SignedInt; 5389 5390 // NetBSD apparently prefers consistency across ARM targets to consistency 5391 // across 64-bit targets. 5392 Int64Type = SignedLongLong; 5393 IntMaxType = SignedLongLong; 5394 } else { 5395 WCharType = UnsignedInt; 5396 Int64Type = SignedLong; 5397 IntMaxType = SignedLong; 5398 } 5399 5400 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5401 MaxVectorAlign = 128; 5402 MaxAtomicInlineWidth = 128; 5403 MaxAtomicPromoteWidth = 128; 5404 5405 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5406 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5407 5408 // {} in inline assembly are neon specifiers, not assembly variant 5409 // specifiers. 5410 NoAsmVariants = true; 5411 5412 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5413 // contributes to the alignment of the containing aggregate in the same way 5414 // a plain (non bit-field) member of that type would, without exception for 5415 // zero-sized or anonymous bit-fields." 5416 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5417 UseZeroLengthBitfieldAlignment = true; 5418 5419 // AArch64 targets default to using the ARM C++ ABI. 5420 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5421 } 5422 5423 StringRef getABI() const override { return ABI; } 5424 bool setABI(const std::string &Name) override { 5425 if (Name != "aapcs" && Name != "darwinpcs") 5426 return false; 5427 5428 ABI = Name; 5429 return true; 5430 } 5431 5432 bool setCPU(const std::string &Name) override { 5433 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5434 .Case("generic", true) 5435 .Cases("cortex-a53", "cortex-a57", "cortex-a72", 5436 "cortex-a35", "exynos-m1", true) 5437 .Case("cyclone", true) 5438 .Case("kryo", true) 5439 .Default(false); 5440 return CPUKnown; 5441 } 5442 5443 void getTargetDefines(const LangOptions &Opts, 5444 MacroBuilder &Builder) const override { 5445 // Target identification. 5446 Builder.defineMacro("__aarch64__"); 5447 5448 // Target properties. 5449 Builder.defineMacro("_LP64"); 5450 Builder.defineMacro("__LP64__"); 5451 5452 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5453 Builder.defineMacro("__ARM_ACLE", "200"); 5454 Builder.defineMacro("__ARM_ARCH", "8"); 5455 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5456 5457 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5458 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5459 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5460 5461 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5462 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5463 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5464 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5465 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5466 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5467 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5468 5469 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5470 5471 // 0xe implies support for half, single and double precision operations. 5472 Builder.defineMacro("__ARM_FP", "0xE"); 5473 5474 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5475 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5476 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5477 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5478 5479 if (Opts.UnsafeFPMath) 5480 Builder.defineMacro("__ARM_FP_FAST", "1"); 5481 5482 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5483 5484 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5485 Opts.ShortEnums ? "1" : "4"); 5486 5487 if (FPU == NeonMode) { 5488 Builder.defineMacro("__ARM_NEON", "1"); 5489 // 64-bit NEON supports half, single and double precision operations. 5490 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5491 } 5492 5493 if (CRC) 5494 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5495 5496 if (Crypto) 5497 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5498 5499 if (Unaligned) 5500 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5501 5502 if (V8_1A) 5503 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5504 5505 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5506 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5507 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5508 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5509 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5510 } 5511 5512 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5513 return llvm::makeArrayRef(BuiltinInfo, 5514 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5515 } 5516 5517 bool hasFeature(StringRef Feature) const override { 5518 return Feature == "aarch64" || 5519 Feature == "arm64" || 5520 Feature == "arm" || 5521 (Feature == "neon" && FPU == NeonMode); 5522 } 5523 5524 bool handleTargetFeatures(std::vector<std::string> &Features, 5525 DiagnosticsEngine &Diags) override { 5526 FPU = FPUMode; 5527 CRC = 0; 5528 Crypto = 0; 5529 Unaligned = 1; 5530 V8_1A = 0; 5531 5532 for (const auto &Feature : Features) { 5533 if (Feature == "+neon") 5534 FPU = NeonMode; 5535 if (Feature == "+crc") 5536 CRC = 1; 5537 if (Feature == "+crypto") 5538 Crypto = 1; 5539 if (Feature == "+strict-align") 5540 Unaligned = 0; 5541 if (Feature == "+v8.1a") 5542 V8_1A = 1; 5543 } 5544 5545 setDataLayoutString(); 5546 5547 return true; 5548 } 5549 5550 bool isCLZForZeroUndef() const override { return false; } 5551 5552 BuiltinVaListKind getBuiltinVaListKind() const override { 5553 return TargetInfo::AArch64ABIBuiltinVaList; 5554 } 5555 5556 ArrayRef<const char *> getGCCRegNames() const override; 5557 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5558 5559 bool validateAsmConstraint(const char *&Name, 5560 TargetInfo::ConstraintInfo &Info) const override { 5561 switch (*Name) { 5562 default: 5563 return false; 5564 case 'w': // Floating point and SIMD registers (V0-V31) 5565 Info.setAllowsRegister(); 5566 return true; 5567 case 'I': // Constant that can be used with an ADD instruction 5568 case 'J': // Constant that can be used with a SUB instruction 5569 case 'K': // Constant that can be used with a 32-bit logical instruction 5570 case 'L': // Constant that can be used with a 64-bit logical instruction 5571 case 'M': // Constant that can be used as a 32-bit MOV immediate 5572 case 'N': // Constant that can be used as a 64-bit MOV immediate 5573 case 'Y': // Floating point constant zero 5574 case 'Z': // Integer constant zero 5575 return true; 5576 case 'Q': // A memory reference with base register and no offset 5577 Info.setAllowsMemory(); 5578 return true; 5579 case 'S': // A symbolic address 5580 Info.setAllowsRegister(); 5581 return true; 5582 case 'U': 5583 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5584 // Utf: A memory address suitable for ldp/stp in TF mode. 5585 // Usa: An absolute symbolic address. 5586 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5587 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5588 case 'z': // Zero register, wzr or xzr 5589 Info.setAllowsRegister(); 5590 return true; 5591 case 'x': // Floating point and SIMD registers (V0-V15) 5592 Info.setAllowsRegister(); 5593 return true; 5594 } 5595 return false; 5596 } 5597 5598 bool 5599 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5600 std::string &SuggestedModifier) const override { 5601 // Strip off constraint modifiers. 5602 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5603 Constraint = Constraint.substr(1); 5604 5605 switch (Constraint[0]) { 5606 default: 5607 return true; 5608 case 'z': 5609 case 'r': { 5610 switch (Modifier) { 5611 case 'x': 5612 case 'w': 5613 // For now assume that the person knows what they're 5614 // doing with the modifier. 5615 return true; 5616 default: 5617 // By default an 'r' constraint will be in the 'x' 5618 // registers. 5619 if (Size == 64) 5620 return true; 5621 5622 SuggestedModifier = "w"; 5623 return false; 5624 } 5625 } 5626 } 5627 } 5628 5629 const char *getClobbers() const override { return ""; } 5630 5631 int getEHDataRegisterNumber(unsigned RegNo) const override { 5632 if (RegNo == 0) 5633 return 0; 5634 if (RegNo == 1) 5635 return 1; 5636 return -1; 5637 } 5638 }; 5639 5640 const char *const AArch64TargetInfo::GCCRegNames[] = { 5641 // 32-bit Integer registers 5642 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5643 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5644 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5645 5646 // 64-bit Integer registers 5647 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5648 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5649 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5650 5651 // 32-bit floating point regsisters 5652 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5653 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5654 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5655 5656 // 64-bit floating point regsisters 5657 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5658 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5659 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5660 5661 // Vector registers 5662 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5663 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5664 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5665 }; 5666 5667 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 5668 return llvm::makeArrayRef(GCCRegNames); 5669 } 5670 5671 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5672 { { "w31" }, "wsp" }, 5673 { { "x29" }, "fp" }, 5674 { { "x30" }, "lr" }, 5675 { { "x31" }, "sp" }, 5676 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5677 // don't want to substitute one of these for a different-sized one. 5678 }; 5679 5680 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 5681 return llvm::makeArrayRef(GCCRegAliases); 5682 } 5683 5684 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5685 #define BUILTIN(ID, TYPE, ATTRS) \ 5686 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5687 #include "clang/Basic/BuiltinsNEON.def" 5688 5689 #define BUILTIN(ID, TYPE, ATTRS) \ 5690 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5691 #include "clang/Basic/BuiltinsAArch64.def" 5692 }; 5693 5694 class AArch64leTargetInfo : public AArch64TargetInfo { 5695 void setDataLayoutString() override { 5696 if (getTriple().isOSBinFormatMachO()) 5697 DataLayoutString = "e-m:o-i64:64-i128:128-n32:64-S128"; 5698 else 5699 DataLayoutString = "e-m:e-i64:64-i128:128-n32:64-S128"; 5700 } 5701 5702 public: 5703 AArch64leTargetInfo(const llvm::Triple &Triple) 5704 : AArch64TargetInfo(Triple) { 5705 BigEndian = false; 5706 } 5707 void getTargetDefines(const LangOptions &Opts, 5708 MacroBuilder &Builder) const override { 5709 Builder.defineMacro("__AARCH64EL__"); 5710 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5711 } 5712 }; 5713 5714 class AArch64beTargetInfo : public AArch64TargetInfo { 5715 void setDataLayoutString() override { 5716 assert(!getTriple().isOSBinFormatMachO()); 5717 DataLayoutString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5718 } 5719 5720 public: 5721 AArch64beTargetInfo(const llvm::Triple &Triple) 5722 : AArch64TargetInfo(Triple) { } 5723 void getTargetDefines(const LangOptions &Opts, 5724 MacroBuilder &Builder) const override { 5725 Builder.defineMacro("__AARCH64EB__"); 5726 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5727 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5728 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5729 } 5730 }; 5731 5732 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5733 protected: 5734 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5735 MacroBuilder &Builder) const override { 5736 Builder.defineMacro("__AARCH64_SIMD__"); 5737 Builder.defineMacro("__ARM64_ARCH_8__"); 5738 Builder.defineMacro("__ARM_NEON__"); 5739 Builder.defineMacro("__LITTLE_ENDIAN__"); 5740 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5741 Builder.defineMacro("__arm64", "1"); 5742 Builder.defineMacro("__arm64__", "1"); 5743 5744 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5745 } 5746 5747 public: 5748 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5749 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5750 Int64Type = SignedLongLong; 5751 WCharType = SignedInt; 5752 UseSignedCharForObjCBool = false; 5753 5754 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5755 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5756 5757 TheCXXABI.set(TargetCXXABI::iOS64); 5758 } 5759 5760 BuiltinVaListKind getBuiltinVaListKind() const override { 5761 return TargetInfo::CharPtrBuiltinVaList; 5762 } 5763 }; 5764 5765 // Hexagon abstract base class 5766 class HexagonTargetInfo : public TargetInfo { 5767 static const Builtin::Info BuiltinInfo[]; 5768 static const char * const GCCRegNames[]; 5769 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5770 std::string CPU; 5771 bool HasHVX, HasHVXDouble; 5772 5773 public: 5774 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5775 BigEndian = false; 5776 // Specify the vector alignment explicitly. For v512x1, the calculated 5777 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 5778 // the required minimum of 64 bytes. 5779 DataLayoutString = "e-m:e-p:32:32:32-a:0-n16:32-" 5780 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 5781 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"; 5782 SizeType = UnsignedInt; 5783 PtrDiffType = SignedInt; 5784 IntPtrType = SignedInt; 5785 5786 // {} in inline assembly are packet specifiers, not assembly variant 5787 // specifiers. 5788 NoAsmVariants = true; 5789 5790 LargeArrayMinWidth = 64; 5791 LargeArrayAlign = 64; 5792 UseBitFieldTypeAlignment = true; 5793 ZeroLengthBitfieldBoundary = 32; 5794 HasHVX = HasHVXDouble = false; 5795 } 5796 5797 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5798 return llvm::makeArrayRef(BuiltinInfo, 5799 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 5800 } 5801 5802 bool validateAsmConstraint(const char *&Name, 5803 TargetInfo::ConstraintInfo &Info) const override { 5804 return true; 5805 } 5806 5807 void getTargetDefines(const LangOptions &Opts, 5808 MacroBuilder &Builder) const override; 5809 5810 bool isCLZForZeroUndef() const override { return false; } 5811 5812 bool hasFeature(StringRef Feature) const override { 5813 return llvm::StringSwitch<bool>(Feature) 5814 .Case("hexagon", true) 5815 .Case("hvx", HasHVX) 5816 .Case("hvx-double", HasHVXDouble) 5817 .Default(false); 5818 } 5819 5820 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5821 StringRef CPU, const std::vector<std::string> &FeaturesVec) 5822 const override; 5823 5824 bool handleTargetFeatures(std::vector<std::string> &Features, 5825 DiagnosticsEngine &Diags) override; 5826 5827 BuiltinVaListKind getBuiltinVaListKind() const override { 5828 return TargetInfo::CharPtrBuiltinVaList; 5829 } 5830 ArrayRef<const char *> getGCCRegNames() const override; 5831 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5832 const char *getClobbers() const override { 5833 return ""; 5834 } 5835 5836 static const char *getHexagonCPUSuffix(StringRef Name) { 5837 return llvm::StringSwitch<const char*>(Name) 5838 .Case("hexagonv4", "4") 5839 .Case("hexagonv5", "5") 5840 .Case("hexagonv55", "55") 5841 .Case("hexagonv60", "60") 5842 .Default(nullptr); 5843 } 5844 5845 bool setCPU(const std::string &Name) override { 5846 if (!getHexagonCPUSuffix(Name)) 5847 return false; 5848 CPU = Name; 5849 return true; 5850 } 5851 5852 int getEHDataRegisterNumber(unsigned RegNo) const override { 5853 return RegNo < 2 ? RegNo : -1; 5854 } 5855 }; 5856 5857 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5858 MacroBuilder &Builder) const { 5859 Builder.defineMacro("__qdsp6__", "1"); 5860 Builder.defineMacro("__hexagon__", "1"); 5861 5862 if (CPU == "hexagonv4") { 5863 Builder.defineMacro("__HEXAGON_V4__"); 5864 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5865 if (Opts.HexagonQdsp6Compat) { 5866 Builder.defineMacro("__QDSP6_V4__"); 5867 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5868 } 5869 } else if (CPU == "hexagonv5") { 5870 Builder.defineMacro("__HEXAGON_V5__"); 5871 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5872 if(Opts.HexagonQdsp6Compat) { 5873 Builder.defineMacro("__QDSP6_V5__"); 5874 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5875 } 5876 } else if (CPU == "hexagonv60") { 5877 Builder.defineMacro("__HEXAGON_V60__"); 5878 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 5879 Builder.defineMacro("__QDSP6_V60__"); 5880 Builder.defineMacro("__QDSP6_ARCH__", "60"); 5881 } 5882 } 5883 5884 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 5885 DiagnosticsEngine &Diags) { 5886 for (auto &F : Features) { 5887 if (F == "+hvx") 5888 HasHVX = true; 5889 else if (F == "-hvx") 5890 HasHVX = HasHVXDouble = false; 5891 else if (F == "+hvx-double") 5892 HasHVX = HasHVXDouble = true; 5893 else if (F == "-hvx-double") 5894 HasHVXDouble = false; 5895 } 5896 return true; 5897 } 5898 5899 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 5900 DiagnosticsEngine &Diags, StringRef CPU, 5901 const std::vector<std::string> &FeaturesVec) const { 5902 // Default for v60: -hvx, -hvx-double. 5903 Features["hvx"] = false; 5904 Features["hvx-double"] = false; 5905 5906 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5907 } 5908 5909 5910 const char *const HexagonTargetInfo::GCCRegNames[] = { 5911 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5912 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5913 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5914 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5915 "p0", "p1", "p2", "p3", 5916 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5917 }; 5918 5919 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 5920 return llvm::makeArrayRef(GCCRegNames); 5921 } 5922 5923 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5924 { { "sp" }, "r29" }, 5925 { { "fp" }, "r30" }, 5926 { { "lr" }, "r31" }, 5927 }; 5928 5929 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 5930 return llvm::makeArrayRef(GCCRegAliases); 5931 } 5932 5933 5934 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5935 #define BUILTIN(ID, TYPE, ATTRS) \ 5936 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5937 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5938 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5939 #include "clang/Basic/BuiltinsHexagon.def" 5940 }; 5941 5942 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5943 class SparcTargetInfo : public TargetInfo { 5944 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5945 static const char * const GCCRegNames[]; 5946 bool SoftFloat; 5947 public: 5948 SparcTargetInfo(const llvm::Triple &Triple) 5949 : TargetInfo(Triple), SoftFloat(false) {} 5950 5951 bool handleTargetFeatures(std::vector<std::string> &Features, 5952 DiagnosticsEngine &Diags) override { 5953 // The backend doesn't actually handle soft float yet, but in case someone 5954 // is using the support for the front end continue to support it. 5955 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 5956 if (Feature != Features.end()) { 5957 SoftFloat = true; 5958 Features.erase(Feature); 5959 } 5960 return true; 5961 } 5962 void getTargetDefines(const LangOptions &Opts, 5963 MacroBuilder &Builder) const override { 5964 DefineStd(Builder, "sparc", Opts); 5965 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5966 5967 if (SoftFloat) 5968 Builder.defineMacro("SOFT_FLOAT", "1"); 5969 } 5970 5971 bool hasFeature(StringRef Feature) const override { 5972 return llvm::StringSwitch<bool>(Feature) 5973 .Case("softfloat", SoftFloat) 5974 .Case("sparc", true) 5975 .Default(false); 5976 } 5977 5978 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5979 // FIXME: Implement! 5980 return None; 5981 } 5982 BuiltinVaListKind getBuiltinVaListKind() const override { 5983 return TargetInfo::VoidPtrBuiltinVaList; 5984 } 5985 ArrayRef<const char *> getGCCRegNames() const override; 5986 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5987 bool validateAsmConstraint(const char *&Name, 5988 TargetInfo::ConstraintInfo &info) const override { 5989 // FIXME: Implement! 5990 switch (*Name) { 5991 case 'I': // Signed 13-bit constant 5992 case 'J': // Zero 5993 case 'K': // 32-bit constant with the low 12 bits clear 5994 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5995 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5996 case 'N': // Same as 'K' but zext (required for SIMode) 5997 case 'O': // The constant 4096 5998 return true; 5999 } 6000 return false; 6001 } 6002 const char *getClobbers() const override { 6003 // FIXME: Implement! 6004 return ""; 6005 } 6006 6007 // No Sparc V7 for now, the backend doesn't support it anyway. 6008 enum CPUKind { 6009 CK_GENERIC, 6010 CK_V8, 6011 CK_SUPERSPARC, 6012 CK_SPARCLITE, 6013 CK_F934, 6014 CK_HYPERSPARC, 6015 CK_SPARCLITE86X, 6016 CK_SPARCLET, 6017 CK_TSC701, 6018 CK_V9, 6019 CK_ULTRASPARC, 6020 CK_ULTRASPARC3, 6021 CK_NIAGARA, 6022 CK_NIAGARA2, 6023 CK_NIAGARA3, 6024 CK_NIAGARA4 6025 } CPU = CK_GENERIC; 6026 6027 enum CPUGeneration { 6028 CG_V8, 6029 CG_V9, 6030 }; 6031 6032 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6033 switch (Kind) { 6034 case CK_GENERIC: 6035 case CK_V8: 6036 case CK_SUPERSPARC: 6037 case CK_SPARCLITE: 6038 case CK_F934: 6039 case CK_HYPERSPARC: 6040 case CK_SPARCLITE86X: 6041 case CK_SPARCLET: 6042 case CK_TSC701: 6043 return CG_V8; 6044 case CK_V9: 6045 case CK_ULTRASPARC: 6046 case CK_ULTRASPARC3: 6047 case CK_NIAGARA: 6048 case CK_NIAGARA2: 6049 case CK_NIAGARA3: 6050 case CK_NIAGARA4: 6051 return CG_V9; 6052 } 6053 llvm_unreachable("Unexpected CPU kind"); 6054 } 6055 6056 CPUKind getCPUKind(StringRef Name) const { 6057 return llvm::StringSwitch<CPUKind>(Name) 6058 .Case("v8", CK_V8) 6059 .Case("supersparc", CK_SUPERSPARC) 6060 .Case("sparclite", CK_SPARCLITE) 6061 .Case("f934", CK_F934) 6062 .Case("hypersparc", CK_HYPERSPARC) 6063 .Case("sparclite86x", CK_SPARCLITE86X) 6064 .Case("sparclet", CK_SPARCLET) 6065 .Case("tsc701", CK_TSC701) 6066 .Case("v9", CK_V9) 6067 .Case("ultrasparc", CK_ULTRASPARC) 6068 .Case("ultrasparc3", CK_ULTRASPARC3) 6069 .Case("niagara", CK_NIAGARA) 6070 .Case("niagara2", CK_NIAGARA2) 6071 .Case("niagara3", CK_NIAGARA3) 6072 .Case("niagara4", CK_NIAGARA4) 6073 .Default(CK_GENERIC); 6074 } 6075 6076 bool setCPU(const std::string &Name) override { 6077 CPU = getCPUKind(Name); 6078 return CPU != CK_GENERIC; 6079 } 6080 }; 6081 6082 const char * const SparcTargetInfo::GCCRegNames[] = { 6083 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6084 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6085 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6086 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6087 }; 6088 6089 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6090 return llvm::makeArrayRef(GCCRegNames); 6091 } 6092 6093 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6094 { { "g0" }, "r0" }, 6095 { { "g1" }, "r1" }, 6096 { { "g2" }, "r2" }, 6097 { { "g3" }, "r3" }, 6098 { { "g4" }, "r4" }, 6099 { { "g5" }, "r5" }, 6100 { { "g6" }, "r6" }, 6101 { { "g7" }, "r7" }, 6102 { { "o0" }, "r8" }, 6103 { { "o1" }, "r9" }, 6104 { { "o2" }, "r10" }, 6105 { { "o3" }, "r11" }, 6106 { { "o4" }, "r12" }, 6107 { { "o5" }, "r13" }, 6108 { { "o6", "sp" }, "r14" }, 6109 { { "o7" }, "r15" }, 6110 { { "l0" }, "r16" }, 6111 { { "l1" }, "r17" }, 6112 { { "l2" }, "r18" }, 6113 { { "l3" }, "r19" }, 6114 { { "l4" }, "r20" }, 6115 { { "l5" }, "r21" }, 6116 { { "l6" }, "r22" }, 6117 { { "l7" }, "r23" }, 6118 { { "i0" }, "r24" }, 6119 { { "i1" }, "r25" }, 6120 { { "i2" }, "r26" }, 6121 { { "i3" }, "r27" }, 6122 { { "i4" }, "r28" }, 6123 { { "i5" }, "r29" }, 6124 { { "i6", "fp" }, "r30" }, 6125 { { "i7" }, "r31" }, 6126 }; 6127 6128 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6129 return llvm::makeArrayRef(GCCRegAliases); 6130 } 6131 6132 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6133 class SparcV8TargetInfo : public SparcTargetInfo { 6134 public: 6135 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 6136 DataLayoutString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 6137 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6138 switch (getTriple().getOS()) { 6139 default: 6140 SizeType = UnsignedInt; 6141 IntPtrType = SignedInt; 6142 PtrDiffType = SignedInt; 6143 break; 6144 case llvm::Triple::NetBSD: 6145 case llvm::Triple::OpenBSD: 6146 SizeType = UnsignedLong; 6147 IntPtrType = SignedLong; 6148 PtrDiffType = SignedLong; 6149 break; 6150 } 6151 } 6152 6153 void getTargetDefines(const LangOptions &Opts, 6154 MacroBuilder &Builder) const override { 6155 SparcTargetInfo::getTargetDefines(Opts, Builder); 6156 switch (getCPUGeneration(CPU)) { 6157 case CG_V8: 6158 Builder.defineMacro("__sparcv8"); 6159 if (getTriple().getOS() != llvm::Triple::Solaris) 6160 Builder.defineMacro("__sparcv8__"); 6161 break; 6162 case CG_V9: 6163 Builder.defineMacro("__sparcv9"); 6164 if (getTriple().getOS() != llvm::Triple::Solaris) { 6165 Builder.defineMacro("__sparcv9__"); 6166 Builder.defineMacro("__sparc_v9__"); 6167 } 6168 break; 6169 } 6170 } 6171 }; 6172 6173 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6174 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6175 public: 6176 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 6177 DataLayoutString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64"; 6178 BigEndian = false; 6179 } 6180 }; 6181 6182 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6183 class SparcV9TargetInfo : public SparcTargetInfo { 6184 public: 6185 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 6186 // FIXME: Support Sparc quad-precision long double? 6187 DataLayoutString = "E-m:e-i64:64-n32:64-S128"; 6188 // This is an LP64 platform. 6189 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6190 6191 // OpenBSD uses long long for int64_t and intmax_t. 6192 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6193 IntMaxType = SignedLongLong; 6194 else 6195 IntMaxType = SignedLong; 6196 Int64Type = IntMaxType; 6197 6198 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6199 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6200 LongDoubleWidth = 128; 6201 LongDoubleAlign = 128; 6202 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6203 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6204 } 6205 6206 void getTargetDefines(const LangOptions &Opts, 6207 MacroBuilder &Builder) const override { 6208 SparcTargetInfo::getTargetDefines(Opts, Builder); 6209 Builder.defineMacro("__sparcv9"); 6210 Builder.defineMacro("__arch64__"); 6211 // Solaris doesn't need these variants, but the BSDs do. 6212 if (getTriple().getOS() != llvm::Triple::Solaris) { 6213 Builder.defineMacro("__sparc64__"); 6214 Builder.defineMacro("__sparc_v9__"); 6215 Builder.defineMacro("__sparcv9__"); 6216 } 6217 } 6218 6219 bool setCPU(const std::string &Name) override { 6220 if (!SparcTargetInfo::setCPU(Name)) 6221 return false; 6222 return getCPUGeneration(CPU) == CG_V9; 6223 } 6224 }; 6225 6226 class SystemZTargetInfo : public TargetInfo { 6227 static const Builtin::Info BuiltinInfo[]; 6228 static const char *const GCCRegNames[]; 6229 std::string CPU; 6230 bool HasTransactionalExecution; 6231 bool HasVector; 6232 6233 public: 6234 SystemZTargetInfo(const llvm::Triple &Triple) 6235 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6236 HasVector(false) { 6237 IntMaxType = SignedLong; 6238 Int64Type = SignedLong; 6239 TLSSupported = true; 6240 IntWidth = IntAlign = 32; 6241 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6242 PointerWidth = PointerAlign = 64; 6243 LongDoubleWidth = 128; 6244 LongDoubleAlign = 64; 6245 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6246 DefaultAlignForAttributeAligned = 64; 6247 MinGlobalAlign = 16; 6248 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 6249 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6250 } 6251 void getTargetDefines(const LangOptions &Opts, 6252 MacroBuilder &Builder) const override { 6253 Builder.defineMacro("__s390__"); 6254 Builder.defineMacro("__s390x__"); 6255 Builder.defineMacro("__zarch__"); 6256 Builder.defineMacro("__LONG_DOUBLE_128__"); 6257 6258 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6259 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6260 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6261 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6262 6263 if (HasTransactionalExecution) 6264 Builder.defineMacro("__HTM__"); 6265 if (Opts.ZVector) 6266 Builder.defineMacro("__VEC__", "10301"); 6267 } 6268 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6269 return llvm::makeArrayRef(BuiltinInfo, 6270 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6271 } 6272 6273 ArrayRef<const char *> getGCCRegNames() const override; 6274 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6275 // No aliases. 6276 return None; 6277 } 6278 bool validateAsmConstraint(const char *&Name, 6279 TargetInfo::ConstraintInfo &info) const override; 6280 const char *getClobbers() const override { 6281 // FIXME: Is this really right? 6282 return ""; 6283 } 6284 BuiltinVaListKind getBuiltinVaListKind() const override { 6285 return TargetInfo::SystemZBuiltinVaList; 6286 } 6287 bool setCPU(const std::string &Name) override { 6288 CPU = Name; 6289 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6290 .Case("z10", true) 6291 .Case("z196", true) 6292 .Case("zEC12", true) 6293 .Case("z13", true) 6294 .Default(false); 6295 6296 return CPUKnown; 6297 } 6298 bool 6299 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6300 StringRef CPU, 6301 const std::vector<std::string> &FeaturesVec) const override { 6302 if (CPU == "zEC12") 6303 Features["transactional-execution"] = true; 6304 if (CPU == "z13") { 6305 Features["transactional-execution"] = true; 6306 Features["vector"] = true; 6307 } 6308 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6309 } 6310 6311 bool handleTargetFeatures(std::vector<std::string> &Features, 6312 DiagnosticsEngine &Diags) override { 6313 HasTransactionalExecution = false; 6314 for (const auto &Feature : Features) { 6315 if (Feature == "+transactional-execution") 6316 HasTransactionalExecution = true; 6317 else if (Feature == "+vector") 6318 HasVector = true; 6319 } 6320 // If we use the vector ABI, vector types are 64-bit aligned. 6321 if (HasVector) { 6322 MaxVectorAlign = 64; 6323 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6324 "-v128:64-a:8:16-n32:64"; 6325 } 6326 return true; 6327 } 6328 6329 bool hasFeature(StringRef Feature) const override { 6330 return llvm::StringSwitch<bool>(Feature) 6331 .Case("systemz", true) 6332 .Case("htm", HasTransactionalExecution) 6333 .Case("vx", HasVector) 6334 .Default(false); 6335 } 6336 6337 StringRef getABI() const override { 6338 if (HasVector) 6339 return "vector"; 6340 return ""; 6341 } 6342 6343 bool useFloat128ManglingForLongDouble() const override { 6344 return true; 6345 } 6346 }; 6347 6348 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6349 #define BUILTIN(ID, TYPE, ATTRS) \ 6350 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6351 #include "clang/Basic/BuiltinsSystemZ.def" 6352 }; 6353 6354 const char *const SystemZTargetInfo::GCCRegNames[] = { 6355 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6356 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6357 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6358 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6359 }; 6360 6361 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6362 return llvm::makeArrayRef(GCCRegNames); 6363 } 6364 6365 bool SystemZTargetInfo:: 6366 validateAsmConstraint(const char *&Name, 6367 TargetInfo::ConstraintInfo &Info) const { 6368 switch (*Name) { 6369 default: 6370 return false; 6371 6372 case 'a': // Address register 6373 case 'd': // Data register (equivalent to 'r') 6374 case 'f': // Floating-point register 6375 Info.setAllowsRegister(); 6376 return true; 6377 6378 case 'I': // Unsigned 8-bit constant 6379 case 'J': // Unsigned 12-bit constant 6380 case 'K': // Signed 16-bit constant 6381 case 'L': // Signed 20-bit displacement (on all targets we support) 6382 case 'M': // 0x7fffffff 6383 return true; 6384 6385 case 'Q': // Memory with base and unsigned 12-bit displacement 6386 case 'R': // Likewise, plus an index 6387 case 'S': // Memory with base and signed 20-bit displacement 6388 case 'T': // Likewise, plus an index 6389 Info.setAllowsMemory(); 6390 return true; 6391 } 6392 } 6393 6394 class MSP430TargetInfo : public TargetInfo { 6395 static const char *const GCCRegNames[]; 6396 6397 public: 6398 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6399 BigEndian = false; 6400 TLSSupported = false; 6401 IntWidth = 16; 6402 IntAlign = 16; 6403 LongWidth = 32; 6404 LongLongWidth = 64; 6405 LongAlign = LongLongAlign = 16; 6406 PointerWidth = 16; 6407 PointerAlign = 16; 6408 SuitableAlign = 16; 6409 SizeType = UnsignedInt; 6410 IntMaxType = SignedLongLong; 6411 IntPtrType = SignedInt; 6412 PtrDiffType = SignedInt; 6413 SigAtomicType = SignedLong; 6414 DataLayoutString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 6415 } 6416 void getTargetDefines(const LangOptions &Opts, 6417 MacroBuilder &Builder) const override { 6418 Builder.defineMacro("MSP430"); 6419 Builder.defineMacro("__MSP430__"); 6420 // FIXME: defines for different 'flavours' of MCU 6421 } 6422 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6423 // FIXME: Implement. 6424 return None; 6425 } 6426 bool hasFeature(StringRef Feature) const override { 6427 return Feature == "msp430"; 6428 } 6429 ArrayRef<const char *> getGCCRegNames() const override; 6430 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6431 // No aliases. 6432 return None; 6433 } 6434 bool validateAsmConstraint(const char *&Name, 6435 TargetInfo::ConstraintInfo &info) const override { 6436 // FIXME: implement 6437 switch (*Name) { 6438 case 'K': // the constant 1 6439 case 'L': // constant -1^20 .. 1^19 6440 case 'M': // constant 1-4: 6441 return true; 6442 } 6443 // No target constraints for now. 6444 return false; 6445 } 6446 const char *getClobbers() const override { 6447 // FIXME: Is this really right? 6448 return ""; 6449 } 6450 BuiltinVaListKind getBuiltinVaListKind() const override { 6451 // FIXME: implement 6452 return TargetInfo::CharPtrBuiltinVaList; 6453 } 6454 }; 6455 6456 const char *const MSP430TargetInfo::GCCRegNames[] = { 6457 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6458 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6459 6460 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 6461 return llvm::makeArrayRef(GCCRegNames); 6462 } 6463 6464 // LLVM and Clang cannot be used directly to output native binaries for 6465 // target, but is used to compile C code to llvm bitcode with correct 6466 // type and alignment information. 6467 // 6468 // TCE uses the llvm bitcode as input and uses it for generating customized 6469 // target processor and program binary. TCE co-design environment is 6470 // publicly available in http://tce.cs.tut.fi 6471 6472 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6473 3, // opencl_global 6474 4, // opencl_local 6475 5, // opencl_constant 6476 // FIXME: generic has to be added to the target 6477 0, // opencl_generic 6478 0, // cuda_device 6479 0, // cuda_constant 6480 0 // cuda_shared 6481 }; 6482 6483 class TCETargetInfo : public TargetInfo { 6484 public: 6485 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6486 TLSSupported = false; 6487 IntWidth = 32; 6488 LongWidth = LongLongWidth = 32; 6489 PointerWidth = 32; 6490 IntAlign = 32; 6491 LongAlign = LongLongAlign = 32; 6492 PointerAlign = 32; 6493 SuitableAlign = 32; 6494 SizeType = UnsignedInt; 6495 IntMaxType = SignedLong; 6496 IntPtrType = SignedInt; 6497 PtrDiffType = SignedInt; 6498 FloatWidth = 32; 6499 FloatAlign = 32; 6500 DoubleWidth = 32; 6501 DoubleAlign = 32; 6502 LongDoubleWidth = 32; 6503 LongDoubleAlign = 32; 6504 FloatFormat = &llvm::APFloat::IEEEsingle; 6505 DoubleFormat = &llvm::APFloat::IEEEsingle; 6506 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6507 DataLayoutString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 6508 "-f64:32-v64:32-v128:32-a:0:32-n32"; 6509 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6510 UseAddrSpaceMapMangling = true; 6511 } 6512 6513 void getTargetDefines(const LangOptions &Opts, 6514 MacroBuilder &Builder) const override { 6515 DefineStd(Builder, "tce", Opts); 6516 Builder.defineMacro("__TCE__"); 6517 Builder.defineMacro("__TCE_V1__"); 6518 } 6519 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 6520 6521 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6522 const char *getClobbers() const override { return ""; } 6523 BuiltinVaListKind getBuiltinVaListKind() const override { 6524 return TargetInfo::VoidPtrBuiltinVaList; 6525 } 6526 ArrayRef<const char *> getGCCRegNames() const override { return None; } 6527 bool validateAsmConstraint(const char *&Name, 6528 TargetInfo::ConstraintInfo &info) const override { 6529 return true; 6530 } 6531 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6532 return None; 6533 } 6534 }; 6535 6536 class BPFTargetInfo : public TargetInfo { 6537 public: 6538 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6539 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6540 SizeType = UnsignedLong; 6541 PtrDiffType = SignedLong; 6542 IntPtrType = SignedLong; 6543 IntMaxType = SignedLong; 6544 Int64Type = SignedLong; 6545 RegParmMax = 5; 6546 if (Triple.getArch() == llvm::Triple::bpfeb) { 6547 BigEndian = true; 6548 DataLayoutString = "E-m:e-p:64:64-i64:64-n32:64-S128"; 6549 } else { 6550 BigEndian = false; 6551 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 6552 } 6553 MaxAtomicPromoteWidth = 64; 6554 MaxAtomicInlineWidth = 64; 6555 TLSSupported = false; 6556 } 6557 void getTargetDefines(const LangOptions &Opts, 6558 MacroBuilder &Builder) const override { 6559 DefineStd(Builder, "bpf", Opts); 6560 Builder.defineMacro("__BPF__"); 6561 } 6562 bool hasFeature(StringRef Feature) const override { 6563 return Feature == "bpf"; 6564 } 6565 6566 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6567 const char *getClobbers() const override { 6568 return ""; 6569 } 6570 BuiltinVaListKind getBuiltinVaListKind() const override { 6571 return TargetInfo::VoidPtrBuiltinVaList; 6572 } 6573 ArrayRef<const char *> getGCCRegNames() const override { 6574 return None; 6575 } 6576 bool validateAsmConstraint(const char *&Name, 6577 TargetInfo::ConstraintInfo &info) const override { 6578 return true; 6579 } 6580 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6581 return None; 6582 } 6583 }; 6584 6585 class MipsTargetInfoBase : public TargetInfo { 6586 virtual void setDataLayoutString() = 0; 6587 6588 static const Builtin::Info BuiltinInfo[]; 6589 std::string CPU; 6590 bool IsMips16; 6591 bool IsMicromips; 6592 bool IsNan2008; 6593 bool IsSingleFloat; 6594 enum MipsFloatABI { 6595 HardFloat, SoftFloat 6596 } FloatABI; 6597 enum DspRevEnum { 6598 NoDSP, DSP1, DSP2 6599 } DspRev; 6600 bool HasMSA; 6601 6602 protected: 6603 bool HasFP64; 6604 std::string ABI; 6605 6606 public: 6607 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 6608 const std::string &CPUStr) 6609 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6610 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6611 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6612 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6613 } 6614 6615 bool isNaN2008Default() const { 6616 return CPU == "mips32r6" || CPU == "mips64r6"; 6617 } 6618 6619 bool isFP64Default() const { 6620 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6621 } 6622 6623 bool isNan2008() const override { 6624 return IsNan2008; 6625 } 6626 6627 StringRef getABI() const override { return ABI; } 6628 bool setCPU(const std::string &Name) override { 6629 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6630 getTriple().getArch() == llvm::Triple::mipsel; 6631 CPU = Name; 6632 return llvm::StringSwitch<bool>(Name) 6633 .Case("mips1", IsMips32) 6634 .Case("mips2", IsMips32) 6635 .Case("mips3", true) 6636 .Case("mips4", true) 6637 .Case("mips5", true) 6638 .Case("mips32", IsMips32) 6639 .Case("mips32r2", IsMips32) 6640 .Case("mips32r3", IsMips32) 6641 .Case("mips32r5", IsMips32) 6642 .Case("mips32r6", IsMips32) 6643 .Case("mips64", true) 6644 .Case("mips64r2", true) 6645 .Case("mips64r3", true) 6646 .Case("mips64r5", true) 6647 .Case("mips64r6", true) 6648 .Case("octeon", true) 6649 .Case("p5600", true) 6650 .Default(false); 6651 } 6652 const std::string& getCPU() const { return CPU; } 6653 bool 6654 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6655 StringRef CPU, 6656 const std::vector<std::string> &FeaturesVec) const override { 6657 if (CPU == "octeon") 6658 Features["mips64r2"] = Features["cnmips"] = true; 6659 else 6660 Features[CPU] = true; 6661 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6662 } 6663 6664 void getTargetDefines(const LangOptions &Opts, 6665 MacroBuilder &Builder) const override { 6666 Builder.defineMacro("__mips__"); 6667 Builder.defineMacro("_mips"); 6668 if (Opts.GNUMode) 6669 Builder.defineMacro("mips"); 6670 6671 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6672 6673 switch (FloatABI) { 6674 case HardFloat: 6675 Builder.defineMacro("__mips_hard_float", Twine(1)); 6676 break; 6677 case SoftFloat: 6678 Builder.defineMacro("__mips_soft_float", Twine(1)); 6679 break; 6680 } 6681 6682 if (IsSingleFloat) 6683 Builder.defineMacro("__mips_single_float", Twine(1)); 6684 6685 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6686 Builder.defineMacro("_MIPS_FPSET", 6687 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6688 6689 if (IsMips16) 6690 Builder.defineMacro("__mips16", Twine(1)); 6691 6692 if (IsMicromips) 6693 Builder.defineMacro("__mips_micromips", Twine(1)); 6694 6695 if (IsNan2008) 6696 Builder.defineMacro("__mips_nan2008", Twine(1)); 6697 6698 switch (DspRev) { 6699 default: 6700 break; 6701 case DSP1: 6702 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6703 Builder.defineMacro("__mips_dsp", Twine(1)); 6704 break; 6705 case DSP2: 6706 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6707 Builder.defineMacro("__mips_dspr2", Twine(1)); 6708 Builder.defineMacro("__mips_dsp", Twine(1)); 6709 break; 6710 } 6711 6712 if (HasMSA) 6713 Builder.defineMacro("__mips_msa", Twine(1)); 6714 6715 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6716 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6717 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6718 6719 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6720 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6721 6722 // These shouldn't be defined for MIPS-I but there's no need to check 6723 // for that since MIPS-I isn't supported. 6724 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6725 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6726 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6727 } 6728 6729 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6730 return llvm::makeArrayRef(BuiltinInfo, 6731 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 6732 } 6733 bool hasFeature(StringRef Feature) const override { 6734 return llvm::StringSwitch<bool>(Feature) 6735 .Case("mips", true) 6736 .Case("fp64", HasFP64) 6737 .Default(false); 6738 } 6739 BuiltinVaListKind getBuiltinVaListKind() const override { 6740 return TargetInfo::VoidPtrBuiltinVaList; 6741 } 6742 ArrayRef<const char *> getGCCRegNames() const override { 6743 static const char *const GCCRegNames[] = { 6744 // CPU register names 6745 // Must match second column of GCCRegAliases 6746 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6747 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6748 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6749 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6750 // Floating point register names 6751 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6752 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6753 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6754 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6755 // Hi/lo and condition register names 6756 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6757 "$fcc5","$fcc6","$fcc7", 6758 // MSA register names 6759 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6760 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6761 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6762 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6763 // MSA control register names 6764 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6765 "$msarequest", "$msamap", "$msaunmap" 6766 }; 6767 return llvm::makeArrayRef(GCCRegNames); 6768 } 6769 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override = 0; 6770 bool validateAsmConstraint(const char *&Name, 6771 TargetInfo::ConstraintInfo &Info) const override { 6772 switch (*Name) { 6773 default: 6774 return false; 6775 case 'r': // CPU registers. 6776 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6777 case 'y': // Equivalent to "r", backward compatibility only. 6778 case 'f': // floating-point registers. 6779 case 'c': // $25 for indirect jumps 6780 case 'l': // lo register 6781 case 'x': // hilo register pair 6782 Info.setAllowsRegister(); 6783 return true; 6784 case 'I': // Signed 16-bit constant 6785 case 'J': // Integer 0 6786 case 'K': // Unsigned 16-bit constant 6787 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6788 case 'M': // Constants not loadable via lui, addiu, or ori 6789 case 'N': // Constant -1 to -65535 6790 case 'O': // A signed 15-bit constant 6791 case 'P': // A constant between 1 go 65535 6792 return true; 6793 case 'R': // An address that can be used in a non-macro load or store 6794 Info.setAllowsMemory(); 6795 return true; 6796 case 'Z': 6797 if (Name[1] == 'C') { // An address usable by ll, and sc. 6798 Info.setAllowsMemory(); 6799 Name++; // Skip over 'Z'. 6800 return true; 6801 } 6802 return false; 6803 } 6804 } 6805 6806 std::string convertConstraint(const char *&Constraint) const override { 6807 std::string R; 6808 switch (*Constraint) { 6809 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6810 if (Constraint[1] == 'C') { 6811 R = std::string("^") + std::string(Constraint, 2); 6812 Constraint++; 6813 return R; 6814 } 6815 break; 6816 } 6817 return TargetInfo::convertConstraint(Constraint); 6818 } 6819 6820 const char *getClobbers() const override { 6821 // In GCC, $1 is not widely used in generated code (it's used only in a few 6822 // specific situations), so there is no real need for users to add it to 6823 // the clobbers list if they want to use it in their inline assembly code. 6824 // 6825 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6826 // code generation, so using it in inline assembly without adding it to the 6827 // clobbers list can cause conflicts between the inline assembly code and 6828 // the surrounding generated code. 6829 // 6830 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6831 // operands, which will conflict with the ".set at" assembler option (which 6832 // we use only for inline assembly, in order to maintain compatibility with 6833 // GCC) and will also conflict with the user's usage of $1. 6834 // 6835 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6836 // register for generated code is to automatically clobber $1 for all inline 6837 // assembly code. 6838 // 6839 // FIXME: We should automatically clobber $1 only for inline assembly code 6840 // which actually uses it. This would allow LLVM to use $1 for inline 6841 // assembly operands if the user's assembly code doesn't use it. 6842 return "~{$1}"; 6843 } 6844 6845 bool handleTargetFeatures(std::vector<std::string> &Features, 6846 DiagnosticsEngine &Diags) override { 6847 IsMips16 = false; 6848 IsMicromips = false; 6849 IsNan2008 = isNaN2008Default(); 6850 IsSingleFloat = false; 6851 FloatABI = HardFloat; 6852 DspRev = NoDSP; 6853 HasFP64 = isFP64Default(); 6854 6855 for (const auto &Feature : Features) { 6856 if (Feature == "+single-float") 6857 IsSingleFloat = true; 6858 else if (Feature == "+soft-float") 6859 FloatABI = SoftFloat; 6860 else if (Feature == "+mips16") 6861 IsMips16 = true; 6862 else if (Feature == "+micromips") 6863 IsMicromips = true; 6864 else if (Feature == "+dsp") 6865 DspRev = std::max(DspRev, DSP1); 6866 else if (Feature == "+dspr2") 6867 DspRev = std::max(DspRev, DSP2); 6868 else if (Feature == "+msa") 6869 HasMSA = true; 6870 else if (Feature == "+fp64") 6871 HasFP64 = true; 6872 else if (Feature == "-fp64") 6873 HasFP64 = false; 6874 else if (Feature == "+nan2008") 6875 IsNan2008 = true; 6876 else if (Feature == "-nan2008") 6877 IsNan2008 = false; 6878 } 6879 6880 setDataLayoutString(); 6881 6882 return true; 6883 } 6884 6885 int getEHDataRegisterNumber(unsigned RegNo) const override { 6886 if (RegNo == 0) return 4; 6887 if (RegNo == 1) return 5; 6888 return -1; 6889 } 6890 6891 bool isCLZForZeroUndef() const override { return false; } 6892 }; 6893 6894 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 6895 #define BUILTIN(ID, TYPE, ATTRS) \ 6896 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6897 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6898 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6899 #include "clang/Basic/BuiltinsMips.def" 6900 }; 6901 6902 class Mips32TargetInfoBase : public MipsTargetInfoBase { 6903 public: 6904 Mips32TargetInfoBase(const llvm::Triple &Triple) 6905 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 6906 SizeType = UnsignedInt; 6907 PtrDiffType = SignedInt; 6908 Int64Type = SignedLongLong; 6909 IntMaxType = Int64Type; 6910 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 6911 } 6912 bool setABI(const std::string &Name) override { 6913 if (Name == "o32" || Name == "eabi") { 6914 ABI = Name; 6915 return true; 6916 } 6917 return false; 6918 } 6919 void getTargetDefines(const LangOptions &Opts, 6920 MacroBuilder &Builder) const override { 6921 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6922 6923 Builder.defineMacro("__mips", "32"); 6924 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 6925 6926 const std::string& CPUStr = getCPU(); 6927 if (CPUStr == "mips32") 6928 Builder.defineMacro("__mips_isa_rev", "1"); 6929 else if (CPUStr == "mips32r2") 6930 Builder.defineMacro("__mips_isa_rev", "2"); 6931 else if (CPUStr == "mips32r3") 6932 Builder.defineMacro("__mips_isa_rev", "3"); 6933 else if (CPUStr == "mips32r5") 6934 Builder.defineMacro("__mips_isa_rev", "5"); 6935 else if (CPUStr == "mips32r6") 6936 Builder.defineMacro("__mips_isa_rev", "6"); 6937 6938 if (ABI == "o32") { 6939 Builder.defineMacro("__mips_o32"); 6940 Builder.defineMacro("_ABIO32", "1"); 6941 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6942 } 6943 else if (ABI == "eabi") 6944 Builder.defineMacro("__mips_eabi"); 6945 else 6946 llvm_unreachable("Invalid ABI for Mips32."); 6947 } 6948 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6949 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6950 { { "at" }, "$1" }, 6951 { { "v0" }, "$2" }, 6952 { { "v1" }, "$3" }, 6953 { { "a0" }, "$4" }, 6954 { { "a1" }, "$5" }, 6955 { { "a2" }, "$6" }, 6956 { { "a3" }, "$7" }, 6957 { { "t0" }, "$8" }, 6958 { { "t1" }, "$9" }, 6959 { { "t2" }, "$10" }, 6960 { { "t3" }, "$11" }, 6961 { { "t4" }, "$12" }, 6962 { { "t5" }, "$13" }, 6963 { { "t6" }, "$14" }, 6964 { { "t7" }, "$15" }, 6965 { { "s0" }, "$16" }, 6966 { { "s1" }, "$17" }, 6967 { { "s2" }, "$18" }, 6968 { { "s3" }, "$19" }, 6969 { { "s4" }, "$20" }, 6970 { { "s5" }, "$21" }, 6971 { { "s6" }, "$22" }, 6972 { { "s7" }, "$23" }, 6973 { { "t8" }, "$24" }, 6974 { { "t9" }, "$25" }, 6975 { { "k0" }, "$26" }, 6976 { { "k1" }, "$27" }, 6977 { { "gp" }, "$28" }, 6978 { { "sp","$sp" }, "$29" }, 6979 { { "fp","$fp" }, "$30" }, 6980 { { "ra" }, "$31" } 6981 }; 6982 return llvm::makeArrayRef(GCCRegAliases); 6983 } 6984 }; 6985 6986 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6987 void setDataLayoutString() override { 6988 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6989 } 6990 6991 public: 6992 Mips32EBTargetInfo(const llvm::Triple &Triple) 6993 : Mips32TargetInfoBase(Triple) { 6994 } 6995 void getTargetDefines(const LangOptions &Opts, 6996 MacroBuilder &Builder) const override { 6997 DefineStd(Builder, "MIPSEB", Opts); 6998 Builder.defineMacro("_MIPSEB"); 6999 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 7000 } 7001 }; 7002 7003 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 7004 void setDataLayoutString() override { 7005 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7006 } 7007 7008 public: 7009 Mips32ELTargetInfo(const llvm::Triple &Triple) 7010 : Mips32TargetInfoBase(Triple) { 7011 BigEndian = false; 7012 } 7013 void getTargetDefines(const LangOptions &Opts, 7014 MacroBuilder &Builder) const override { 7015 DefineStd(Builder, "MIPSEL", Opts); 7016 Builder.defineMacro("_MIPSEL"); 7017 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 7018 } 7019 }; 7020 7021 class Mips64TargetInfoBase : public MipsTargetInfoBase { 7022 public: 7023 Mips64TargetInfoBase(const llvm::Triple &Triple) 7024 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 7025 LongDoubleWidth = LongDoubleAlign = 128; 7026 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7027 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7028 LongDoubleWidth = LongDoubleAlign = 64; 7029 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7030 } 7031 setN64ABITypes(); 7032 SuitableAlign = 128; 7033 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7034 } 7035 7036 void setN64ABITypes() { 7037 LongWidth = LongAlign = 64; 7038 PointerWidth = PointerAlign = 64; 7039 SizeType = UnsignedLong; 7040 PtrDiffType = SignedLong; 7041 Int64Type = SignedLong; 7042 IntMaxType = Int64Type; 7043 } 7044 7045 void setN32ABITypes() { 7046 LongWidth = LongAlign = 32; 7047 PointerWidth = PointerAlign = 32; 7048 SizeType = UnsignedInt; 7049 PtrDiffType = SignedInt; 7050 Int64Type = SignedLongLong; 7051 IntMaxType = Int64Type; 7052 } 7053 7054 bool setABI(const std::string &Name) override { 7055 if (Name == "n32") { 7056 setN32ABITypes(); 7057 ABI = Name; 7058 return true; 7059 } 7060 if (Name == "n64") { 7061 setN64ABITypes(); 7062 ABI = Name; 7063 return true; 7064 } 7065 return false; 7066 } 7067 7068 void getTargetDefines(const LangOptions &Opts, 7069 MacroBuilder &Builder) const override { 7070 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 7071 7072 Builder.defineMacro("__mips", "64"); 7073 Builder.defineMacro("__mips64"); 7074 Builder.defineMacro("__mips64__"); 7075 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7076 7077 const std::string& CPUStr = getCPU(); 7078 if (CPUStr == "mips64") 7079 Builder.defineMacro("__mips_isa_rev", "1"); 7080 else if (CPUStr == "mips64r2") 7081 Builder.defineMacro("__mips_isa_rev", "2"); 7082 else if (CPUStr == "mips64r3") 7083 Builder.defineMacro("__mips_isa_rev", "3"); 7084 else if (CPUStr == "mips64r5") 7085 Builder.defineMacro("__mips_isa_rev", "5"); 7086 else if (CPUStr == "mips64r6") 7087 Builder.defineMacro("__mips_isa_rev", "6"); 7088 7089 if (ABI == "n32") { 7090 Builder.defineMacro("__mips_n32"); 7091 Builder.defineMacro("_ABIN32", "2"); 7092 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7093 } 7094 else if (ABI == "n64") { 7095 Builder.defineMacro("__mips_n64"); 7096 Builder.defineMacro("_ABI64", "3"); 7097 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7098 } 7099 else 7100 llvm_unreachable("Invalid ABI for Mips64."); 7101 7102 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7103 } 7104 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7105 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 7106 { { "at" }, "$1" }, 7107 { { "v0" }, "$2" }, 7108 { { "v1" }, "$3" }, 7109 { { "a0" }, "$4" }, 7110 { { "a1" }, "$5" }, 7111 { { "a2" }, "$6" }, 7112 { { "a3" }, "$7" }, 7113 { { "a4" }, "$8" }, 7114 { { "a5" }, "$9" }, 7115 { { "a6" }, "$10" }, 7116 { { "a7" }, "$11" }, 7117 { { "t0" }, "$12" }, 7118 { { "t1" }, "$13" }, 7119 { { "t2" }, "$14" }, 7120 { { "t3" }, "$15" }, 7121 { { "s0" }, "$16" }, 7122 { { "s1" }, "$17" }, 7123 { { "s2" }, "$18" }, 7124 { { "s3" }, "$19" }, 7125 { { "s4" }, "$20" }, 7126 { { "s5" }, "$21" }, 7127 { { "s6" }, "$22" }, 7128 { { "s7" }, "$23" }, 7129 { { "t8" }, "$24" }, 7130 { { "t9" }, "$25" }, 7131 { { "k0" }, "$26" }, 7132 { { "k1" }, "$27" }, 7133 { { "gp" }, "$28" }, 7134 { { "sp","$sp" }, "$29" }, 7135 { { "fp","$fp" }, "$30" }, 7136 { { "ra" }, "$31" } 7137 }; 7138 return llvm::makeArrayRef(GCCRegAliases); 7139 } 7140 7141 bool hasInt128Type() const override { return true; } 7142 }; 7143 7144 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 7145 void setDataLayoutString() override { 7146 if (ABI == "n32") 7147 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7148 else 7149 DataLayoutString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7150 7151 } 7152 7153 public: 7154 Mips64EBTargetInfo(const llvm::Triple &Triple) 7155 : Mips64TargetInfoBase(Triple) {} 7156 void getTargetDefines(const LangOptions &Opts, 7157 MacroBuilder &Builder) const override { 7158 DefineStd(Builder, "MIPSEB", Opts); 7159 Builder.defineMacro("_MIPSEB"); 7160 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7161 } 7162 }; 7163 7164 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 7165 void setDataLayoutString() override { 7166 if (ABI == "n32") 7167 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7168 else 7169 DataLayoutString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7170 } 7171 public: 7172 Mips64ELTargetInfo(const llvm::Triple &Triple) 7173 : Mips64TargetInfoBase(Triple) { 7174 // Default ABI is n64. 7175 BigEndian = false; 7176 } 7177 void getTargetDefines(const LangOptions &Opts, 7178 MacroBuilder &Builder) const override { 7179 DefineStd(Builder, "MIPSEL", Opts); 7180 Builder.defineMacro("_MIPSEL"); 7181 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7182 } 7183 }; 7184 7185 class PNaClTargetInfo : public TargetInfo { 7186 public: 7187 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7188 BigEndian = false; 7189 this->UserLabelPrefix = ""; 7190 this->LongAlign = 32; 7191 this->LongWidth = 32; 7192 this->PointerAlign = 32; 7193 this->PointerWidth = 32; 7194 this->IntMaxType = TargetInfo::SignedLongLong; 7195 this->Int64Type = TargetInfo::SignedLongLong; 7196 this->DoubleAlign = 64; 7197 this->LongDoubleWidth = 64; 7198 this->LongDoubleAlign = 64; 7199 this->SizeType = TargetInfo::UnsignedInt; 7200 this->PtrDiffType = TargetInfo::SignedInt; 7201 this->IntPtrType = TargetInfo::SignedInt; 7202 this->RegParmMax = 0; // Disallow regparm 7203 } 7204 7205 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7206 Builder.defineMacro("__le32__"); 7207 Builder.defineMacro("__pnacl__"); 7208 } 7209 void getTargetDefines(const LangOptions &Opts, 7210 MacroBuilder &Builder) const override { 7211 getArchDefines(Opts, Builder); 7212 } 7213 bool hasFeature(StringRef Feature) const override { 7214 return Feature == "pnacl"; 7215 } 7216 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7217 BuiltinVaListKind getBuiltinVaListKind() const override { 7218 return TargetInfo::PNaClABIBuiltinVaList; 7219 } 7220 ArrayRef<const char *> getGCCRegNames() const override; 7221 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7222 bool validateAsmConstraint(const char *&Name, 7223 TargetInfo::ConstraintInfo &Info) const override { 7224 return false; 7225 } 7226 7227 const char *getClobbers() const override { 7228 return ""; 7229 } 7230 }; 7231 7232 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7233 return None; 7234 } 7235 7236 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7237 return None; 7238 } 7239 7240 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7241 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 7242 public: 7243 NaClMips32ELTargetInfo(const llvm::Triple &Triple) : 7244 Mips32ELTargetInfo(Triple) { 7245 } 7246 7247 BuiltinVaListKind getBuiltinVaListKind() const override { 7248 return TargetInfo::PNaClABIBuiltinVaList; 7249 } 7250 }; 7251 7252 class Le64TargetInfo : public TargetInfo { 7253 static const Builtin::Info BuiltinInfo[]; 7254 7255 public: 7256 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7257 BigEndian = false; 7258 NoAsmVariants = true; 7259 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7260 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7261 DataLayoutString = "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 7262 } 7263 7264 void getTargetDefines(const LangOptions &Opts, 7265 MacroBuilder &Builder) const override { 7266 DefineStd(Builder, "unix", Opts); 7267 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7268 Builder.defineMacro("__ELF__"); 7269 } 7270 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7271 return llvm::makeArrayRef(BuiltinInfo, 7272 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7273 } 7274 BuiltinVaListKind getBuiltinVaListKind() const override { 7275 return TargetInfo::PNaClABIBuiltinVaList; 7276 } 7277 const char *getClobbers() const override { return ""; } 7278 ArrayRef<const char *> getGCCRegNames() const override { 7279 return None; 7280 } 7281 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7282 return None; 7283 } 7284 bool validateAsmConstraint(const char *&Name, 7285 TargetInfo::ConstraintInfo &Info) const override { 7286 return false; 7287 } 7288 7289 bool hasProtectedVisibility() const override { return false; } 7290 }; 7291 7292 class WebAssemblyTargetInfo : public TargetInfo { 7293 static const Builtin::Info BuiltinInfo[]; 7294 7295 enum SIMDEnum { 7296 NoSIMD, 7297 SIMD128, 7298 } SIMDLevel; 7299 7300 public: 7301 explicit WebAssemblyTargetInfo(const llvm::Triple &T) 7302 : TargetInfo(T), SIMDLevel(NoSIMD) { 7303 BigEndian = false; 7304 NoAsmVariants = true; 7305 SuitableAlign = 128; 7306 LargeArrayMinWidth = 128; 7307 LargeArrayAlign = 128; 7308 SimdDefaultAlign = 128; 7309 SigAtomicType = SignedLong; 7310 LongDoubleWidth = LongDoubleAlign = 128; 7311 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7312 } 7313 7314 protected: 7315 void getTargetDefines(const LangOptions &Opts, 7316 MacroBuilder &Builder) const override { 7317 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7318 if (SIMDLevel >= SIMD128) 7319 Builder.defineMacro("__wasm_simd128__"); 7320 } 7321 7322 private: 7323 bool 7324 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7325 StringRef CPU, 7326 const std::vector<std::string> &FeaturesVec) const override { 7327 if (CPU == "bleeding-edge") 7328 Features["simd128"] = true; 7329 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7330 } 7331 bool hasFeature(StringRef Feature) const final { 7332 return llvm::StringSwitch<bool>(Feature) 7333 .Case("simd128", SIMDLevel >= SIMD128) 7334 .Default(false); 7335 } 7336 bool handleTargetFeatures(std::vector<std::string> &Features, 7337 DiagnosticsEngine &Diags) final { 7338 for (const auto &Feature : Features) { 7339 if (Feature == "+simd128") { 7340 SIMDLevel = std::max(SIMDLevel, SIMD128); 7341 continue; 7342 } 7343 if (Feature == "-simd128") { 7344 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7345 continue; 7346 } 7347 7348 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7349 << "-target-feature"; 7350 return false; 7351 } 7352 return true; 7353 } 7354 bool setCPU(const std::string &Name) final { 7355 return llvm::StringSwitch<bool>(Name) 7356 .Case("mvp", true) 7357 .Case("bleeding-edge", true) 7358 .Case("generic", true) 7359 .Default(false); 7360 } 7361 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7362 return llvm::makeArrayRef(BuiltinInfo, 7363 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7364 } 7365 BuiltinVaListKind getBuiltinVaListKind() const final { 7366 return VoidPtrBuiltinVaList; 7367 } 7368 ArrayRef<const char *> getGCCRegNames() const final { 7369 return None; 7370 } 7371 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7372 return None; 7373 } 7374 bool 7375 validateAsmConstraint(const char *&Name, 7376 TargetInfo::ConstraintInfo &Info) const final { 7377 return false; 7378 } 7379 const char *getClobbers() const final { return ""; } 7380 bool isCLZForZeroUndef() const final { return false; } 7381 bool hasInt128Type() const final { return true; } 7382 IntType getIntTypeByWidth(unsigned BitWidth, 7383 bool IsSigned) const final { 7384 // WebAssembly prefers long long for explicitly 64-bit integers. 7385 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7386 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7387 } 7388 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7389 bool IsSigned) const final { 7390 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7391 return BitWidth == 64 7392 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7393 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7394 } 7395 }; 7396 7397 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7398 #define BUILTIN(ID, TYPE, ATTRS) \ 7399 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7400 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7401 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7402 #include "clang/Basic/BuiltinsWebAssembly.def" 7403 }; 7404 7405 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7406 public: 7407 explicit WebAssembly32TargetInfo(const llvm::Triple &T) 7408 : WebAssemblyTargetInfo(T) { 7409 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7410 DataLayoutString = "e-m:e-p:32:32-i64:64-n32:64-S128"; 7411 } 7412 7413 protected: 7414 void getTargetDefines(const LangOptions &Opts, 7415 MacroBuilder &Builder) const override { 7416 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7417 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7418 } 7419 }; 7420 7421 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7422 public: 7423 explicit WebAssembly64TargetInfo(const llvm::Triple &T) 7424 : WebAssemblyTargetInfo(T) { 7425 LongAlign = LongWidth = 64; 7426 PointerAlign = PointerWidth = 64; 7427 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7428 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 7429 } 7430 7431 protected: 7432 void getTargetDefines(const LangOptions &Opts, 7433 MacroBuilder &Builder) const override { 7434 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7435 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7436 } 7437 }; 7438 7439 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7440 #define BUILTIN(ID, TYPE, ATTRS) \ 7441 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7442 #include "clang/Basic/BuiltinsLe64.def" 7443 }; 7444 7445 static const unsigned SPIRAddrSpaceMap[] = { 7446 1, // opencl_global 7447 3, // opencl_local 7448 2, // opencl_constant 7449 4, // opencl_generic 7450 0, // cuda_device 7451 0, // cuda_constant 7452 0 // cuda_shared 7453 }; 7454 class SPIRTargetInfo : public TargetInfo { 7455 public: 7456 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7457 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7458 "SPIR target must use unknown OS"); 7459 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7460 "SPIR target must use unknown environment type"); 7461 BigEndian = false; 7462 TLSSupported = false; 7463 LongWidth = LongAlign = 64; 7464 AddrSpaceMap = &SPIRAddrSpaceMap; 7465 UseAddrSpaceMapMangling = true; 7466 // Define available target features 7467 // These must be defined in sorted order! 7468 NoAsmVariants = true; 7469 } 7470 void getTargetDefines(const LangOptions &Opts, 7471 MacroBuilder &Builder) const override { 7472 DefineStd(Builder, "SPIR", Opts); 7473 } 7474 bool hasFeature(StringRef Feature) const override { 7475 return Feature == "spir"; 7476 } 7477 7478 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7479 const char *getClobbers() const override { return ""; } 7480 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7481 bool validateAsmConstraint(const char *&Name, 7482 TargetInfo::ConstraintInfo &info) const override { 7483 return true; 7484 } 7485 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7486 return None; 7487 } 7488 BuiltinVaListKind getBuiltinVaListKind() const override { 7489 return TargetInfo::VoidPtrBuiltinVaList; 7490 } 7491 7492 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7493 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK 7494 : CCCR_Warning; 7495 } 7496 7497 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7498 return CC_SpirFunction; 7499 } 7500 }; 7501 7502 class SPIR32TargetInfo : public SPIRTargetInfo { 7503 public: 7504 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7505 PointerWidth = PointerAlign = 32; 7506 SizeType = TargetInfo::UnsignedInt; 7507 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7508 DataLayoutString = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7509 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7510 } 7511 void getTargetDefines(const LangOptions &Opts, 7512 MacroBuilder &Builder) const override { 7513 DefineStd(Builder, "SPIR32", Opts); 7514 } 7515 }; 7516 7517 class SPIR64TargetInfo : public SPIRTargetInfo { 7518 public: 7519 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7520 PointerWidth = PointerAlign = 64; 7521 SizeType = TargetInfo::UnsignedLong; 7522 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7523 DataLayoutString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7524 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7525 } 7526 void getTargetDefines(const LangOptions &Opts, 7527 MacroBuilder &Builder) const override { 7528 DefineStd(Builder, "SPIR64", Opts); 7529 } 7530 }; 7531 7532 class XCoreTargetInfo : public TargetInfo { 7533 static const Builtin::Info BuiltinInfo[]; 7534 public: 7535 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7536 BigEndian = false; 7537 NoAsmVariants = true; 7538 LongLongAlign = 32; 7539 SuitableAlign = 32; 7540 DoubleAlign = LongDoubleAlign = 32; 7541 SizeType = UnsignedInt; 7542 PtrDiffType = SignedInt; 7543 IntPtrType = SignedInt; 7544 WCharType = UnsignedChar; 7545 WIntType = UnsignedInt; 7546 UseZeroLengthBitfieldAlignment = true; 7547 DataLayoutString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7548 "-f64:32-a:0:32-n32"; 7549 } 7550 void getTargetDefines(const LangOptions &Opts, 7551 MacroBuilder &Builder) const override { 7552 Builder.defineMacro("__XS1B__"); 7553 } 7554 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7555 return llvm::makeArrayRef(BuiltinInfo, 7556 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 7557 } 7558 BuiltinVaListKind getBuiltinVaListKind() const override { 7559 return TargetInfo::VoidPtrBuiltinVaList; 7560 } 7561 const char *getClobbers() const override { 7562 return ""; 7563 } 7564 ArrayRef<const char *> getGCCRegNames() const override { 7565 static const char * const GCCRegNames[] = { 7566 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7567 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 7568 }; 7569 return llvm::makeArrayRef(GCCRegNames); 7570 } 7571 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7572 return None; 7573 } 7574 bool validateAsmConstraint(const char *&Name, 7575 TargetInfo::ConstraintInfo &Info) const override { 7576 return false; 7577 } 7578 int getEHDataRegisterNumber(unsigned RegNo) const override { 7579 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7580 return (RegNo < 2)? RegNo : -1; 7581 } 7582 bool allowsLargerPreferedTypeAlignment() const override { 7583 return false; 7584 } 7585 }; 7586 7587 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7588 #define BUILTIN(ID, TYPE, ATTRS) \ 7589 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7590 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7591 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7592 #include "clang/Basic/BuiltinsXCore.def" 7593 }; 7594 7595 // x86_32 Android target 7596 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7597 public: 7598 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 7599 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 7600 SuitableAlign = 32; 7601 LongDoubleWidth = 64; 7602 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7603 } 7604 }; 7605 7606 // x86_64 Android target 7607 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7608 public: 7609 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 7610 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 7611 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7612 } 7613 7614 bool useFloat128ManglingForLongDouble() const override { 7615 return true; 7616 } 7617 }; 7618 } // end anonymous namespace 7619 7620 //===----------------------------------------------------------------------===// 7621 // Driver code 7622 //===----------------------------------------------------------------------===// 7623 7624 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 7625 llvm::Triple::OSType os = Triple.getOS(); 7626 7627 switch (Triple.getArch()) { 7628 default: 7629 return nullptr; 7630 7631 case llvm::Triple::xcore: 7632 return new XCoreTargetInfo(Triple); 7633 7634 case llvm::Triple::hexagon: 7635 return new HexagonTargetInfo(Triple); 7636 7637 case llvm::Triple::aarch64: 7638 if (Triple.isOSDarwin()) 7639 return new DarwinAArch64TargetInfo(Triple); 7640 7641 switch (os) { 7642 case llvm::Triple::CloudABI: 7643 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple); 7644 case llvm::Triple::FreeBSD: 7645 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 7646 case llvm::Triple::Linux: 7647 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 7648 case llvm::Triple::NetBSD: 7649 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 7650 default: 7651 return new AArch64leTargetInfo(Triple); 7652 } 7653 7654 case llvm::Triple::aarch64_be: 7655 switch (os) { 7656 case llvm::Triple::FreeBSD: 7657 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 7658 case llvm::Triple::Linux: 7659 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 7660 case llvm::Triple::NetBSD: 7661 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 7662 default: 7663 return new AArch64beTargetInfo(Triple); 7664 } 7665 7666 case llvm::Triple::arm: 7667 case llvm::Triple::thumb: 7668 if (Triple.isOSBinFormatMachO()) 7669 return new DarwinARMTargetInfo(Triple); 7670 7671 switch (os) { 7672 case llvm::Triple::Linux: 7673 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 7674 case llvm::Triple::FreeBSD: 7675 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 7676 case llvm::Triple::NetBSD: 7677 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 7678 case llvm::Triple::OpenBSD: 7679 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 7680 case llvm::Triple::Bitrig: 7681 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 7682 case llvm::Triple::RTEMS: 7683 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 7684 case llvm::Triple::NaCl: 7685 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 7686 case llvm::Triple::Win32: 7687 switch (Triple.getEnvironment()) { 7688 case llvm::Triple::Cygnus: 7689 return new CygwinARMTargetInfo(Triple); 7690 case llvm::Triple::GNU: 7691 return new MinGWARMTargetInfo(Triple); 7692 case llvm::Triple::Itanium: 7693 return new ItaniumWindowsARMleTargetInfo(Triple); 7694 case llvm::Triple::MSVC: 7695 default: // Assume MSVC for unknown environments 7696 return new MicrosoftARMleTargetInfo(Triple); 7697 } 7698 default: 7699 return new ARMleTargetInfo(Triple); 7700 } 7701 7702 case llvm::Triple::armeb: 7703 case llvm::Triple::thumbeb: 7704 if (Triple.isOSDarwin()) 7705 return new DarwinARMTargetInfo(Triple); 7706 7707 switch (os) { 7708 case llvm::Triple::Linux: 7709 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 7710 case llvm::Triple::FreeBSD: 7711 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 7712 case llvm::Triple::NetBSD: 7713 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 7714 case llvm::Triple::OpenBSD: 7715 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 7716 case llvm::Triple::Bitrig: 7717 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 7718 case llvm::Triple::RTEMS: 7719 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 7720 case llvm::Triple::NaCl: 7721 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 7722 default: 7723 return new ARMbeTargetInfo(Triple); 7724 } 7725 7726 case llvm::Triple::bpfeb: 7727 case llvm::Triple::bpfel: 7728 return new BPFTargetInfo(Triple); 7729 7730 case llvm::Triple::msp430: 7731 return new MSP430TargetInfo(Triple); 7732 7733 case llvm::Triple::mips: 7734 switch (os) { 7735 case llvm::Triple::Linux: 7736 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 7737 case llvm::Triple::RTEMS: 7738 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 7739 case llvm::Triple::FreeBSD: 7740 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7741 case llvm::Triple::NetBSD: 7742 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7743 default: 7744 return new Mips32EBTargetInfo(Triple); 7745 } 7746 7747 case llvm::Triple::mipsel: 7748 switch (os) { 7749 case llvm::Triple::Linux: 7750 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 7751 case llvm::Triple::RTEMS: 7752 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 7753 case llvm::Triple::FreeBSD: 7754 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7755 case llvm::Triple::NetBSD: 7756 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7757 case llvm::Triple::NaCl: 7758 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple); 7759 default: 7760 return new Mips32ELTargetInfo(Triple); 7761 } 7762 7763 case llvm::Triple::mips64: 7764 switch (os) { 7765 case llvm::Triple::Linux: 7766 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 7767 case llvm::Triple::RTEMS: 7768 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 7769 case llvm::Triple::FreeBSD: 7770 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7771 case llvm::Triple::NetBSD: 7772 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7773 case llvm::Triple::OpenBSD: 7774 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7775 default: 7776 return new Mips64EBTargetInfo(Triple); 7777 } 7778 7779 case llvm::Triple::mips64el: 7780 switch (os) { 7781 case llvm::Triple::Linux: 7782 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 7783 case llvm::Triple::RTEMS: 7784 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 7785 case llvm::Triple::FreeBSD: 7786 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7787 case llvm::Triple::NetBSD: 7788 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7789 case llvm::Triple::OpenBSD: 7790 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7791 default: 7792 return new Mips64ELTargetInfo(Triple); 7793 } 7794 7795 case llvm::Triple::le32: 7796 switch (os) { 7797 case llvm::Triple::NaCl: 7798 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 7799 default: 7800 return nullptr; 7801 } 7802 7803 case llvm::Triple::le64: 7804 return new Le64TargetInfo(Triple); 7805 7806 case llvm::Triple::ppc: 7807 if (Triple.isOSDarwin()) 7808 return new DarwinPPC32TargetInfo(Triple); 7809 switch (os) { 7810 case llvm::Triple::Linux: 7811 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 7812 case llvm::Triple::FreeBSD: 7813 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 7814 case llvm::Triple::NetBSD: 7815 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 7816 case llvm::Triple::OpenBSD: 7817 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 7818 case llvm::Triple::RTEMS: 7819 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 7820 default: 7821 return new PPC32TargetInfo(Triple); 7822 } 7823 7824 case llvm::Triple::ppc64: 7825 if (Triple.isOSDarwin()) 7826 return new DarwinPPC64TargetInfo(Triple); 7827 switch (os) { 7828 case llvm::Triple::Linux: 7829 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7830 case llvm::Triple::Lv2: 7831 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 7832 case llvm::Triple::FreeBSD: 7833 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 7834 case llvm::Triple::NetBSD: 7835 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7836 default: 7837 return new PPC64TargetInfo(Triple); 7838 } 7839 7840 case llvm::Triple::ppc64le: 7841 switch (os) { 7842 case llvm::Triple::Linux: 7843 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7844 case llvm::Triple::NetBSD: 7845 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7846 default: 7847 return new PPC64TargetInfo(Triple); 7848 } 7849 7850 case llvm::Triple::nvptx: 7851 return new NVPTX32TargetInfo(Triple); 7852 case llvm::Triple::nvptx64: 7853 return new NVPTX64TargetInfo(Triple); 7854 7855 case llvm::Triple::amdgcn: 7856 case llvm::Triple::r600: 7857 return new AMDGPUTargetInfo(Triple); 7858 7859 case llvm::Triple::sparc: 7860 switch (os) { 7861 case llvm::Triple::Linux: 7862 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 7863 case llvm::Triple::Solaris: 7864 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple); 7865 case llvm::Triple::NetBSD: 7866 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 7867 case llvm::Triple::OpenBSD: 7868 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 7869 case llvm::Triple::RTEMS: 7870 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 7871 default: 7872 return new SparcV8TargetInfo(Triple); 7873 } 7874 7875 // The 'sparcel' architecture copies all the above cases except for Solaris. 7876 case llvm::Triple::sparcel: 7877 switch (os) { 7878 case llvm::Triple::Linux: 7879 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 7880 case llvm::Triple::NetBSD: 7881 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7882 case llvm::Triple::OpenBSD: 7883 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7884 case llvm::Triple::RTEMS: 7885 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 7886 default: 7887 return new SparcV8elTargetInfo(Triple); 7888 } 7889 7890 case llvm::Triple::sparcv9: 7891 switch (os) { 7892 case llvm::Triple::Linux: 7893 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 7894 case llvm::Triple::Solaris: 7895 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 7896 case llvm::Triple::NetBSD: 7897 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 7898 case llvm::Triple::OpenBSD: 7899 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 7900 case llvm::Triple::FreeBSD: 7901 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 7902 default: 7903 return new SparcV9TargetInfo(Triple); 7904 } 7905 7906 case llvm::Triple::systemz: 7907 switch (os) { 7908 case llvm::Triple::Linux: 7909 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 7910 default: 7911 return new SystemZTargetInfo(Triple); 7912 } 7913 7914 case llvm::Triple::tce: 7915 return new TCETargetInfo(Triple); 7916 7917 case llvm::Triple::x86: 7918 if (Triple.isOSDarwin()) 7919 return new DarwinI386TargetInfo(Triple); 7920 7921 switch (os) { 7922 case llvm::Triple::CloudABI: 7923 return new CloudABITargetInfo<X86_32TargetInfo>(Triple); 7924 case llvm::Triple::Linux: { 7925 switch (Triple.getEnvironment()) { 7926 default: 7927 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 7928 case llvm::Triple::Android: 7929 return new AndroidX86_32TargetInfo(Triple); 7930 } 7931 } 7932 case llvm::Triple::DragonFly: 7933 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 7934 case llvm::Triple::NetBSD: 7935 return new NetBSDI386TargetInfo(Triple); 7936 case llvm::Triple::OpenBSD: 7937 return new OpenBSDI386TargetInfo(Triple); 7938 case llvm::Triple::Bitrig: 7939 return new BitrigI386TargetInfo(Triple); 7940 case llvm::Triple::FreeBSD: 7941 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7942 case llvm::Triple::KFreeBSD: 7943 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7944 case llvm::Triple::Minix: 7945 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 7946 case llvm::Triple::Solaris: 7947 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 7948 case llvm::Triple::Win32: { 7949 switch (Triple.getEnvironment()) { 7950 case llvm::Triple::Cygnus: 7951 return new CygwinX86_32TargetInfo(Triple); 7952 case llvm::Triple::GNU: 7953 return new MinGWX86_32TargetInfo(Triple); 7954 case llvm::Triple::Itanium: 7955 case llvm::Triple::MSVC: 7956 default: // Assume MSVC for unknown environments 7957 return new MicrosoftX86_32TargetInfo(Triple); 7958 } 7959 } 7960 case llvm::Triple::Haiku: 7961 return new HaikuX86_32TargetInfo(Triple); 7962 case llvm::Triple::RTEMS: 7963 return new RTEMSX86_32TargetInfo(Triple); 7964 case llvm::Triple::NaCl: 7965 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 7966 case llvm::Triple::ELFIAMCU: 7967 return new MCUX86_32TargetInfo(Triple); 7968 default: 7969 return new X86_32TargetInfo(Triple); 7970 } 7971 7972 case llvm::Triple::x86_64: 7973 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 7974 return new DarwinX86_64TargetInfo(Triple); 7975 7976 switch (os) { 7977 case llvm::Triple::CloudABI: 7978 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 7979 case llvm::Triple::Linux: { 7980 switch (Triple.getEnvironment()) { 7981 default: 7982 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 7983 case llvm::Triple::Android: 7984 return new AndroidX86_64TargetInfo(Triple); 7985 } 7986 } 7987 case llvm::Triple::DragonFly: 7988 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 7989 case llvm::Triple::NetBSD: 7990 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 7991 case llvm::Triple::OpenBSD: 7992 return new OpenBSDX86_64TargetInfo(Triple); 7993 case llvm::Triple::Bitrig: 7994 return new BitrigX86_64TargetInfo(Triple); 7995 case llvm::Triple::FreeBSD: 7996 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7997 case llvm::Triple::KFreeBSD: 7998 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7999 case llvm::Triple::Solaris: 8000 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 8001 case llvm::Triple::Win32: { 8002 switch (Triple.getEnvironment()) { 8003 case llvm::Triple::Cygnus: 8004 return new CygwinX86_64TargetInfo(Triple); 8005 case llvm::Triple::GNU: 8006 return new MinGWX86_64TargetInfo(Triple); 8007 case llvm::Triple::MSVC: 8008 default: // Assume MSVC for unknown environments 8009 return new MicrosoftX86_64TargetInfo(Triple); 8010 } 8011 } 8012 case llvm::Triple::NaCl: 8013 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 8014 case llvm::Triple::PS4: 8015 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 8016 default: 8017 return new X86_64TargetInfo(Triple); 8018 } 8019 8020 case llvm::Triple::spir: { 8021 if (Triple.getOS() != llvm::Triple::UnknownOS || 8022 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8023 return nullptr; 8024 return new SPIR32TargetInfo(Triple); 8025 } 8026 case llvm::Triple::spir64: { 8027 if (Triple.getOS() != llvm::Triple::UnknownOS || 8028 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8029 return nullptr; 8030 return new SPIR64TargetInfo(Triple); 8031 } 8032 case llvm::Triple::wasm32: 8033 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8034 return nullptr; 8035 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple); 8036 case llvm::Triple::wasm64: 8037 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8038 return nullptr; 8039 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple); 8040 } 8041 } 8042 8043 /// CreateTargetInfo - Return the target info object for the specified target 8044 /// options. 8045 TargetInfo * 8046 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8047 const std::shared_ptr<TargetOptions> &Opts) { 8048 llvm::Triple Triple(Opts->Triple); 8049 8050 // Construct the target 8051 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 8052 if (!Target) { 8053 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8054 return nullptr; 8055 } 8056 Target->TargetOpts = Opts; 8057 8058 // Set the target CPU if specified. 8059 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8060 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8061 return nullptr; 8062 } 8063 8064 // Set the target ABI if specified. 8065 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8066 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8067 return nullptr; 8068 } 8069 8070 // Set the fp math unit. 8071 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8072 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8073 return nullptr; 8074 } 8075 8076 // Compute the default target features, we need the target to handle this 8077 // because features may have dependencies on one another. 8078 llvm::StringMap<bool> Features; 8079 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8080 Opts->FeaturesAsWritten)) 8081 return nullptr; 8082 8083 // Add the features to the compile options. 8084 Opts->Features.clear(); 8085 for (const auto &F : Features) 8086 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8087 8088 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8089 return nullptr; 8090 8091 return Target.release(); 8092 } 8093