1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "clang/Basic/Version.h" 23 #include "llvm/ADT/APFloat.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringExtras.h" 26 #include "llvm/ADT/StringRef.h" 27 #include "llvm/ADT/StringSwitch.h" 28 #include "llvm/ADT/Triple.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/TargetParser.h" 32 #include <algorithm> 33 #include <memory> 34 35 using namespace clang; 36 37 //===----------------------------------------------------------------------===// 38 // Common code shared among targets. 39 //===----------------------------------------------------------------------===// 40 41 /// DefineStd - Define a macro name and standard variants. For example if 42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 43 /// when in GNU mode. 44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 45 const LangOptions &Opts) { 46 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 47 48 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 49 // in the user's namespace. 50 if (Opts.GNUMode) 51 Builder.defineMacro(MacroName); 52 53 // Define __unix. 54 Builder.defineMacro("__" + MacroName); 55 56 // Define __unix__. 57 Builder.defineMacro("__" + MacroName + "__"); 58 } 59 60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 61 bool Tuning = true) { 62 Builder.defineMacro("__" + CPUName); 63 Builder.defineMacro("__" + CPUName + "__"); 64 if (Tuning) 65 Builder.defineMacro("__tune_" + CPUName + "__"); 66 } 67 68 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 69 const TargetOptions &Opts); 70 71 //===----------------------------------------------------------------------===// 72 // Defines specific to certain operating systems. 73 //===----------------------------------------------------------------------===// 74 75 namespace { 76 template<typename TgtInfo> 77 class OSTargetInfo : public TgtInfo { 78 protected: 79 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 80 MacroBuilder &Builder) const=0; 81 public: 82 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 83 : TgtInfo(Triple, Opts) {} 84 void getTargetDefines(const LangOptions &Opts, 85 MacroBuilder &Builder) const override { 86 TgtInfo::getTargetDefines(Opts, Builder); 87 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 88 } 89 90 }; 91 92 // CloudABI Target 93 template <typename Target> 94 class CloudABITargetInfo : public OSTargetInfo<Target> { 95 protected: 96 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 97 MacroBuilder &Builder) const override { 98 Builder.defineMacro("__CloudABI__"); 99 Builder.defineMacro("__ELF__"); 100 101 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 102 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 103 Builder.defineMacro("__STDC_UTF_16__"); 104 Builder.defineMacro("__STDC_UTF_32__"); 105 } 106 107 public: 108 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 109 : OSTargetInfo<Target>(Triple, Opts) {} 110 }; 111 112 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 113 const llvm::Triple &Triple, 114 StringRef &PlatformName, 115 VersionTuple &PlatformMinVersion) { 116 Builder.defineMacro("__APPLE_CC__", "6000"); 117 Builder.defineMacro("__APPLE__"); 118 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 119 // AddressSanitizer doesn't play well with source fortification, which is on 120 // by default on Darwin. 121 if (Opts.Sanitize.has(SanitizerKind::Address)) 122 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 123 124 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 125 if (!Opts.ObjC1) { 126 // __weak is always defined, for use in blocks and with objc pointers. 127 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 128 Builder.defineMacro("__strong", ""); 129 Builder.defineMacro("__unsafe_unretained", ""); 130 } 131 132 if (Opts.Static) 133 Builder.defineMacro("__STATIC__"); 134 else 135 Builder.defineMacro("__DYNAMIC__"); 136 137 if (Opts.POSIXThreads) 138 Builder.defineMacro("_REENTRANT"); 139 140 // Get the platform type and version number from the triple. 141 unsigned Maj, Min, Rev; 142 if (Triple.isMacOSX()) { 143 Triple.getMacOSXVersion(Maj, Min, Rev); 144 PlatformName = "macosx"; 145 } else { 146 Triple.getOSVersion(Maj, Min, Rev); 147 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 148 } 149 150 // If -target arch-pc-win32-macho option specified, we're 151 // generating code for Win32 ABI. No need to emit 152 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 153 if (PlatformName == "win32") { 154 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 155 return; 156 } 157 158 // Set the appropriate OS version define. 159 if (Triple.isiOS()) { 160 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 161 char Str[6]; 162 Str[0] = '0' + Maj; 163 Str[1] = '0' + (Min / 10); 164 Str[2] = '0' + (Min % 10); 165 Str[3] = '0' + (Rev / 10); 166 Str[4] = '0' + (Rev % 10); 167 Str[5] = '\0'; 168 if (Triple.isTvOS()) 169 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 170 else 171 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 172 Str); 173 174 } else if (Triple.isWatchOS()) { 175 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 176 char Str[6]; 177 Str[0] = '0' + Maj; 178 Str[1] = '0' + (Min / 10); 179 Str[2] = '0' + (Min % 10); 180 Str[3] = '0' + (Rev / 10); 181 Str[4] = '0' + (Rev % 10); 182 Str[5] = '\0'; 183 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 184 } else if (Triple.isMacOSX()) { 185 // Note that the Driver allows versions which aren't representable in the 186 // define (because we only get a single digit for the minor and micro 187 // revision numbers). So, we limit them to the maximum representable 188 // version. 189 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 190 char Str[7]; 191 if (Maj < 10 || (Maj == 10 && Min < 10)) { 192 Str[0] = '0' + (Maj / 10); 193 Str[1] = '0' + (Maj % 10); 194 Str[2] = '0' + std::min(Min, 9U); 195 Str[3] = '0' + std::min(Rev, 9U); 196 Str[4] = '\0'; 197 } else { 198 // Handle versions > 10.9. 199 Str[0] = '0' + (Maj / 10); 200 Str[1] = '0' + (Maj % 10); 201 Str[2] = '0' + (Min / 10); 202 Str[3] = '0' + (Min % 10); 203 Str[4] = '0' + (Rev / 10); 204 Str[5] = '0' + (Rev % 10); 205 Str[6] = '\0'; 206 } 207 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 208 } 209 210 // Tell users about the kernel if there is one. 211 if (Triple.isOSDarwin()) 212 Builder.defineMacro("__MACH__"); 213 214 // The Watch ABI uses Dwarf EH. 215 if(Triple.isWatchABI()) 216 Builder.defineMacro("__ARM_DWARF_EH__"); 217 218 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 219 } 220 221 template<typename Target> 222 class DarwinTargetInfo : public OSTargetInfo<Target> { 223 protected: 224 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 225 MacroBuilder &Builder) const override { 226 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 227 this->PlatformMinVersion); 228 } 229 230 public: 231 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 232 : OSTargetInfo<Target>(Triple, Opts) { 233 // By default, no TLS, and we whitelist permitted architecture/OS 234 // combinations. 235 this->TLSSupported = false; 236 237 if (Triple.isMacOSX()) 238 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 239 else if (Triple.isiOS()) { 240 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 241 if (Triple.getArch() == llvm::Triple::x86_64 || 242 Triple.getArch() == llvm::Triple::aarch64) 243 this->TLSSupported = !Triple.isOSVersionLT(8); 244 else if (Triple.getArch() == llvm::Triple::x86 || 245 Triple.getArch() == llvm::Triple::arm || 246 Triple.getArch() == llvm::Triple::thumb) 247 this->TLSSupported = !Triple.isOSVersionLT(9); 248 } else if (Triple.isWatchOS()) 249 this->TLSSupported = !Triple.isOSVersionLT(2); 250 251 this->MCountName = "\01mcount"; 252 } 253 254 std::string isValidSectionSpecifier(StringRef SR) const override { 255 // Let MCSectionMachO validate this. 256 StringRef Segment, Section; 257 unsigned TAA, StubSize; 258 bool HasTAA; 259 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 260 TAA, HasTAA, StubSize); 261 } 262 263 const char *getStaticInitSectionSpecifier() const override { 264 // FIXME: We should return 0 when building kexts. 265 return "__TEXT,__StaticInit,regular,pure_instructions"; 266 } 267 268 /// Darwin does not support protected visibility. Darwin's "default" 269 /// is very similar to ELF's "protected"; Darwin requires a "weak" 270 /// attribute on declarations that can be dynamically replaced. 271 bool hasProtectedVisibility() const override { 272 return false; 273 } 274 275 unsigned getExnObjectAlignment() const override { 276 // The alignment of an exception object is 8-bytes for darwin since 277 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 278 // and therefore doesn't guarantee 16-byte alignment. 279 return 64; 280 } 281 }; 282 283 284 // DragonFlyBSD Target 285 template<typename Target> 286 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 287 protected: 288 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 289 MacroBuilder &Builder) const override { 290 // DragonFly defines; list based off of gcc output 291 Builder.defineMacro("__DragonFly__"); 292 Builder.defineMacro("__DragonFly_cc_version", "100001"); 293 Builder.defineMacro("__ELF__"); 294 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 295 Builder.defineMacro("__tune_i386__"); 296 DefineStd(Builder, "unix", Opts); 297 } 298 public: 299 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 300 : OSTargetInfo<Target>(Triple, Opts) { 301 switch (Triple.getArch()) { 302 default: 303 case llvm::Triple::x86: 304 case llvm::Triple::x86_64: 305 this->MCountName = ".mcount"; 306 break; 307 } 308 } 309 }; 310 311 // FreeBSD Target 312 template<typename Target> 313 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 314 protected: 315 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 316 MacroBuilder &Builder) const override { 317 // FreeBSD defines; list based off of gcc output 318 319 unsigned Release = Triple.getOSMajorVersion(); 320 if (Release == 0U) 321 Release = 8; 322 323 Builder.defineMacro("__FreeBSD__", Twine(Release)); 324 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 325 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 326 DefineStd(Builder, "unix", Opts); 327 Builder.defineMacro("__ELF__"); 328 329 // On FreeBSD, wchar_t contains the number of the code point as 330 // used by the character set of the locale. These character sets are 331 // not necessarily a superset of ASCII. 332 // 333 // FIXME: This is wrong; the macro refers to the numerical values 334 // of wchar_t *literals*, which are not locale-dependent. However, 335 // FreeBSD systems apparently depend on us getting this wrong, and 336 // setting this to 1 is conforming even if all the basic source 337 // character literals have the same encoding as char and wchar_t. 338 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 339 } 340 public: 341 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 342 : OSTargetInfo<Target>(Triple, Opts) { 343 switch (Triple.getArch()) { 344 default: 345 case llvm::Triple::x86: 346 case llvm::Triple::x86_64: 347 this->MCountName = ".mcount"; 348 break; 349 case llvm::Triple::mips: 350 case llvm::Triple::mipsel: 351 case llvm::Triple::ppc: 352 case llvm::Triple::ppc64: 353 case llvm::Triple::ppc64le: 354 this->MCountName = "_mcount"; 355 break; 356 case llvm::Triple::arm: 357 this->MCountName = "__mcount"; 358 break; 359 } 360 } 361 }; 362 363 // GNU/kFreeBSD Target 364 template<typename Target> 365 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 366 protected: 367 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 368 MacroBuilder &Builder) const override { 369 // GNU/kFreeBSD defines; list based off of gcc output 370 371 DefineStd(Builder, "unix", Opts); 372 Builder.defineMacro("__FreeBSD_kernel__"); 373 Builder.defineMacro("__GLIBC__"); 374 Builder.defineMacro("__ELF__"); 375 if (Opts.POSIXThreads) 376 Builder.defineMacro("_REENTRANT"); 377 if (Opts.CPlusPlus) 378 Builder.defineMacro("_GNU_SOURCE"); 379 } 380 public: 381 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 382 : OSTargetInfo<Target>(Triple, Opts) {} 383 }; 384 385 // Haiku Target 386 template<typename Target> 387 class HaikuTargetInfo : public OSTargetInfo<Target> { 388 protected: 389 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 390 MacroBuilder &Builder) const override { 391 // Haiku defines; list based off of gcc output 392 Builder.defineMacro("__HAIKU__"); 393 Builder.defineMacro("__ELF__"); 394 DefineStd(Builder, "unix", Opts); 395 } 396 public: 397 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 398 : OSTargetInfo<Target>(Triple, Opts) { 399 this->SizeType = TargetInfo::UnsignedLong; 400 this->IntPtrType = TargetInfo::SignedLong; 401 this->PtrDiffType = TargetInfo::SignedLong; 402 this->ProcessIDType = TargetInfo::SignedLong; 403 this->TLSSupported = false; 404 405 } 406 }; 407 408 // Minix Target 409 template<typename Target> 410 class MinixTargetInfo : public OSTargetInfo<Target> { 411 protected: 412 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 413 MacroBuilder &Builder) const override { 414 // Minix defines 415 416 Builder.defineMacro("__minix", "3"); 417 Builder.defineMacro("_EM_WSIZE", "4"); 418 Builder.defineMacro("_EM_PSIZE", "4"); 419 Builder.defineMacro("_EM_SSIZE", "2"); 420 Builder.defineMacro("_EM_LSIZE", "4"); 421 Builder.defineMacro("_EM_FSIZE", "4"); 422 Builder.defineMacro("_EM_DSIZE", "8"); 423 Builder.defineMacro("__ELF__"); 424 DefineStd(Builder, "unix", Opts); 425 } 426 public: 427 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 428 : OSTargetInfo<Target>(Triple, Opts) {} 429 }; 430 431 // Linux target 432 template<typename Target> 433 class LinuxTargetInfo : public OSTargetInfo<Target> { 434 protected: 435 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 436 MacroBuilder &Builder) const override { 437 // Linux defines; list based off of gcc output 438 DefineStd(Builder, "unix", Opts); 439 DefineStd(Builder, "linux", Opts); 440 Builder.defineMacro("__gnu_linux__"); 441 Builder.defineMacro("__ELF__"); 442 if (Triple.isAndroid()) { 443 Builder.defineMacro("__ANDROID__", "1"); 444 unsigned Maj, Min, Rev; 445 Triple.getEnvironmentVersion(Maj, Min, Rev); 446 this->PlatformName = "android"; 447 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 448 } 449 if (Opts.POSIXThreads) 450 Builder.defineMacro("_REENTRANT"); 451 if (Opts.CPlusPlus) 452 Builder.defineMacro("_GNU_SOURCE"); 453 if (this->HasFloat128) 454 Builder.defineMacro("__FLOAT128__"); 455 } 456 public: 457 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 458 : OSTargetInfo<Target>(Triple, Opts) { 459 this->WIntType = TargetInfo::UnsignedInt; 460 461 switch (Triple.getArch()) { 462 default: 463 break; 464 case llvm::Triple::ppc: 465 case llvm::Triple::ppc64: 466 case llvm::Triple::ppc64le: 467 this->MCountName = "_mcount"; 468 break; 469 case llvm::Triple::x86: 470 case llvm::Triple::x86_64: 471 case llvm::Triple::systemz: 472 this->HasFloat128 = true; 473 break; 474 } 475 } 476 477 const char *getStaticInitSectionSpecifier() const override { 478 return ".text.startup"; 479 } 480 }; 481 482 // NetBSD Target 483 template<typename Target> 484 class NetBSDTargetInfo : public OSTargetInfo<Target> { 485 protected: 486 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 487 MacroBuilder &Builder) const override { 488 // NetBSD defines; list based off of gcc output 489 Builder.defineMacro("__NetBSD__"); 490 Builder.defineMacro("__unix__"); 491 Builder.defineMacro("__ELF__"); 492 if (Opts.POSIXThreads) 493 Builder.defineMacro("_POSIX_THREADS"); 494 495 switch (Triple.getArch()) { 496 default: 497 break; 498 case llvm::Triple::arm: 499 case llvm::Triple::armeb: 500 case llvm::Triple::thumb: 501 case llvm::Triple::thumbeb: 502 Builder.defineMacro("__ARM_DWARF_EH__"); 503 break; 504 } 505 } 506 public: 507 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 508 : OSTargetInfo<Target>(Triple, Opts) { 509 this->MCountName = "_mcount"; 510 } 511 }; 512 513 // OpenBSD Target 514 template<typename Target> 515 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 516 protected: 517 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 518 MacroBuilder &Builder) const override { 519 // OpenBSD defines; list based off of gcc output 520 521 Builder.defineMacro("__OpenBSD__"); 522 DefineStd(Builder, "unix", Opts); 523 Builder.defineMacro("__ELF__"); 524 if (Opts.POSIXThreads) 525 Builder.defineMacro("_REENTRANT"); 526 } 527 public: 528 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 529 : OSTargetInfo<Target>(Triple, Opts) { 530 this->TLSSupported = false; 531 532 switch (Triple.getArch()) { 533 default: 534 case llvm::Triple::x86: 535 case llvm::Triple::x86_64: 536 case llvm::Triple::arm: 537 case llvm::Triple::sparc: 538 this->MCountName = "__mcount"; 539 break; 540 case llvm::Triple::mips64: 541 case llvm::Triple::mips64el: 542 case llvm::Triple::ppc: 543 case llvm::Triple::sparcv9: 544 this->MCountName = "_mcount"; 545 break; 546 } 547 } 548 }; 549 550 // Bitrig Target 551 template<typename Target> 552 class BitrigTargetInfo : public OSTargetInfo<Target> { 553 protected: 554 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 555 MacroBuilder &Builder) const override { 556 // Bitrig defines; list based off of gcc output 557 558 Builder.defineMacro("__Bitrig__"); 559 DefineStd(Builder, "unix", Opts); 560 Builder.defineMacro("__ELF__"); 561 if (Opts.POSIXThreads) 562 Builder.defineMacro("_REENTRANT"); 563 564 switch (Triple.getArch()) { 565 default: 566 break; 567 case llvm::Triple::arm: 568 case llvm::Triple::armeb: 569 case llvm::Triple::thumb: 570 case llvm::Triple::thumbeb: 571 Builder.defineMacro("__ARM_DWARF_EH__"); 572 break; 573 } 574 } 575 public: 576 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 577 : OSTargetInfo<Target>(Triple, Opts) { 578 this->MCountName = "__mcount"; 579 } 580 }; 581 582 // PSP Target 583 template<typename Target> 584 class PSPTargetInfo : public OSTargetInfo<Target> { 585 protected: 586 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 587 MacroBuilder &Builder) const override { 588 // PSP defines; list based on the output of the pspdev gcc toolchain. 589 Builder.defineMacro("PSP"); 590 Builder.defineMacro("_PSP"); 591 Builder.defineMacro("__psp__"); 592 Builder.defineMacro("__ELF__"); 593 } 594 public: 595 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 596 }; 597 598 // PS3 PPU Target 599 template<typename Target> 600 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 601 protected: 602 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 603 MacroBuilder &Builder) const override { 604 // PS3 PPU defines. 605 Builder.defineMacro("__PPC__"); 606 Builder.defineMacro("__PPU__"); 607 Builder.defineMacro("__CELLOS_LV2__"); 608 Builder.defineMacro("__ELF__"); 609 Builder.defineMacro("__LP32__"); 610 Builder.defineMacro("_ARCH_PPC64"); 611 Builder.defineMacro("__powerpc64__"); 612 } 613 public: 614 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 615 : OSTargetInfo<Target>(Triple, Opts) { 616 this->LongWidth = this->LongAlign = 32; 617 this->PointerWidth = this->PointerAlign = 32; 618 this->IntMaxType = TargetInfo::SignedLongLong; 619 this->Int64Type = TargetInfo::SignedLongLong; 620 this->SizeType = TargetInfo::UnsignedInt; 621 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 622 } 623 }; 624 625 template <typename Target> 626 class PS4OSTargetInfo : public OSTargetInfo<Target> { 627 protected: 628 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 629 MacroBuilder &Builder) const override { 630 Builder.defineMacro("__FreeBSD__", "9"); 631 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 632 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 633 DefineStd(Builder, "unix", Opts); 634 Builder.defineMacro("__ELF__"); 635 Builder.defineMacro("__ORBIS__"); 636 } 637 public: 638 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 639 : OSTargetInfo<Target>(Triple, Opts) { 640 this->WCharType = this->UnsignedShort; 641 642 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 643 this->MaxTLSAlign = 256; 644 645 // On PS4, do not honor explicit bit field alignment, 646 // as in "__attribute__((aligned(2))) int b : 1;". 647 this->UseExplicitBitFieldAlignment = false; 648 649 switch (Triple.getArch()) { 650 default: 651 case llvm::Triple::x86_64: 652 this->MCountName = ".mcount"; 653 break; 654 } 655 } 656 }; 657 658 // Solaris target 659 template<typename Target> 660 class SolarisTargetInfo : public OSTargetInfo<Target> { 661 protected: 662 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 663 MacroBuilder &Builder) const override { 664 DefineStd(Builder, "sun", Opts); 665 DefineStd(Builder, "unix", Opts); 666 Builder.defineMacro("__ELF__"); 667 Builder.defineMacro("__svr4__"); 668 Builder.defineMacro("__SVR4"); 669 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 670 // newer, but to 500 for everything else. feature_test.h has a check to 671 // ensure that you are not using C99 with an old version of X/Open or C89 672 // with a new version. 673 if (Opts.C99) 674 Builder.defineMacro("_XOPEN_SOURCE", "600"); 675 else 676 Builder.defineMacro("_XOPEN_SOURCE", "500"); 677 if (Opts.CPlusPlus) 678 Builder.defineMacro("__C99FEATURES__"); 679 Builder.defineMacro("_LARGEFILE_SOURCE"); 680 Builder.defineMacro("_LARGEFILE64_SOURCE"); 681 Builder.defineMacro("__EXTENSIONS__"); 682 Builder.defineMacro("_REENTRANT"); 683 } 684 public: 685 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 686 : OSTargetInfo<Target>(Triple, Opts) { 687 this->WCharType = this->SignedInt; 688 // FIXME: WIntType should be SignedLong 689 } 690 }; 691 692 // Windows target 693 template<typename Target> 694 class WindowsTargetInfo : public OSTargetInfo<Target> { 695 protected: 696 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 697 MacroBuilder &Builder) const override { 698 Builder.defineMacro("_WIN32"); 699 } 700 void getVisualStudioDefines(const LangOptions &Opts, 701 MacroBuilder &Builder) const { 702 if (Opts.CPlusPlus) { 703 if (Opts.RTTIData) 704 Builder.defineMacro("_CPPRTTI"); 705 706 if (Opts.CXXExceptions) 707 Builder.defineMacro("_CPPUNWIND"); 708 } 709 710 if (Opts.Bool) 711 Builder.defineMacro("__BOOL_DEFINED"); 712 713 if (!Opts.CharIsSigned) 714 Builder.defineMacro("_CHAR_UNSIGNED"); 715 716 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 717 // but it works for now. 718 if (Opts.POSIXThreads) 719 Builder.defineMacro("_MT"); 720 721 if (Opts.MSCompatibilityVersion) { 722 Builder.defineMacro("_MSC_VER", 723 Twine(Opts.MSCompatibilityVersion / 100000)); 724 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 725 // FIXME We cannot encode the revision information into 32-bits 726 Builder.defineMacro("_MSC_BUILD", Twine(1)); 727 728 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 729 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 730 } 731 732 if (Opts.MicrosoftExt) { 733 Builder.defineMacro("_MSC_EXTENSIONS"); 734 735 if (Opts.CPlusPlus11) { 736 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 737 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 738 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 739 } 740 } 741 742 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 743 } 744 745 public: 746 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 747 : OSTargetInfo<Target>(Triple, Opts) {} 748 }; 749 750 template <typename Target> 751 class NaClTargetInfo : public OSTargetInfo<Target> { 752 protected: 753 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 754 MacroBuilder &Builder) const override { 755 if (Opts.POSIXThreads) 756 Builder.defineMacro("_REENTRANT"); 757 if (Opts.CPlusPlus) 758 Builder.defineMacro("_GNU_SOURCE"); 759 760 DefineStd(Builder, "unix", Opts); 761 Builder.defineMacro("__ELF__"); 762 Builder.defineMacro("__native_client__"); 763 } 764 765 public: 766 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 767 : OSTargetInfo<Target>(Triple, Opts) { 768 this->LongAlign = 32; 769 this->LongWidth = 32; 770 this->PointerAlign = 32; 771 this->PointerWidth = 32; 772 this->IntMaxType = TargetInfo::SignedLongLong; 773 this->Int64Type = TargetInfo::SignedLongLong; 774 this->DoubleAlign = 64; 775 this->LongDoubleWidth = 64; 776 this->LongDoubleAlign = 64; 777 this->LongLongWidth = 64; 778 this->LongLongAlign = 64; 779 this->SizeType = TargetInfo::UnsignedInt; 780 this->PtrDiffType = TargetInfo::SignedInt; 781 this->IntPtrType = TargetInfo::SignedInt; 782 // RegParmMax is inherited from the underlying architecture 783 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 784 if (Triple.getArch() == llvm::Triple::arm) { 785 // Handled in ARM's setABI(). 786 } else if (Triple.getArch() == llvm::Triple::x86) { 787 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 788 } else if (Triple.getArch() == llvm::Triple::x86_64) { 789 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 790 } else if (Triple.getArch() == llvm::Triple::mipsel) { 791 // Handled on mips' setDataLayout. 792 } else { 793 assert(Triple.getArch() == llvm::Triple::le32); 794 this->resetDataLayout("e-p:32:32-i64:64"); 795 } 796 } 797 }; 798 799 // WebAssembly target 800 template <typename Target> 801 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 802 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 803 MacroBuilder &Builder) const final { 804 // A common platform macro. 805 if (Opts.POSIXThreads) 806 Builder.defineMacro("_REENTRANT"); 807 // Follow g++ convention and predefine _GNU_SOURCE for C++. 808 if (Opts.CPlusPlus) 809 Builder.defineMacro("_GNU_SOURCE"); 810 } 811 812 // As an optimization, group static init code together in a section. 813 const char *getStaticInitSectionSpecifier() const final { 814 return ".text.__startup"; 815 } 816 817 public: 818 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 819 const TargetOptions &Opts) 820 : OSTargetInfo<Target>(Triple, Opts) { 821 this->MCountName = "__mcount"; 822 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 823 } 824 }; 825 826 //===----------------------------------------------------------------------===// 827 // Specific target implementations. 828 //===----------------------------------------------------------------------===// 829 830 // PPC abstract base class 831 class PPCTargetInfo : public TargetInfo { 832 static const Builtin::Info BuiltinInfo[]; 833 static const char * const GCCRegNames[]; 834 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 835 std::string CPU; 836 837 // Target cpu features. 838 bool HasVSX; 839 bool HasP8Vector; 840 bool HasP8Crypto; 841 bool HasDirectMove; 842 bool HasQPX; 843 bool HasHTM; 844 bool HasBPERMD; 845 bool HasExtDiv; 846 847 protected: 848 std::string ABI; 849 850 public: 851 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 852 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 853 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 854 HasBPERMD(false), HasExtDiv(false) { 855 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 856 SimdDefaultAlign = 128; 857 LongDoubleWidth = LongDoubleAlign = 128; 858 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 859 } 860 861 /// \brief Flags for architecture specific defines. 862 typedef enum { 863 ArchDefineNone = 0, 864 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 865 ArchDefinePpcgr = 1 << 1, 866 ArchDefinePpcsq = 1 << 2, 867 ArchDefine440 = 1 << 3, 868 ArchDefine603 = 1 << 4, 869 ArchDefine604 = 1 << 5, 870 ArchDefinePwr4 = 1 << 6, 871 ArchDefinePwr5 = 1 << 7, 872 ArchDefinePwr5x = 1 << 8, 873 ArchDefinePwr6 = 1 << 9, 874 ArchDefinePwr6x = 1 << 10, 875 ArchDefinePwr7 = 1 << 11, 876 ArchDefinePwr8 = 1 << 12, 877 ArchDefinePwr9 = 1 << 13, 878 ArchDefineA2 = 1 << 14, 879 ArchDefineA2q = 1 << 15 880 } ArchDefineTypes; 881 882 // Note: GCC recognizes the following additional cpus: 883 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 884 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 885 // titan, rs64. 886 bool setCPU(const std::string &Name) override { 887 bool CPUKnown = llvm::StringSwitch<bool>(Name) 888 .Case("generic", true) 889 .Case("440", true) 890 .Case("450", true) 891 .Case("601", true) 892 .Case("602", true) 893 .Case("603", true) 894 .Case("603e", true) 895 .Case("603ev", true) 896 .Case("604", true) 897 .Case("604e", true) 898 .Case("620", true) 899 .Case("630", true) 900 .Case("g3", true) 901 .Case("7400", true) 902 .Case("g4", true) 903 .Case("7450", true) 904 .Case("g4+", true) 905 .Case("750", true) 906 .Case("970", true) 907 .Case("g5", true) 908 .Case("a2", true) 909 .Case("a2q", true) 910 .Case("e500mc", true) 911 .Case("e5500", true) 912 .Case("power3", true) 913 .Case("pwr3", true) 914 .Case("power4", true) 915 .Case("pwr4", true) 916 .Case("power5", true) 917 .Case("pwr5", true) 918 .Case("power5x", true) 919 .Case("pwr5x", true) 920 .Case("power6", true) 921 .Case("pwr6", true) 922 .Case("power6x", true) 923 .Case("pwr6x", true) 924 .Case("power7", true) 925 .Case("pwr7", true) 926 .Case("power8", true) 927 .Case("pwr8", true) 928 .Case("power9", true) 929 .Case("pwr9", true) 930 .Case("powerpc", true) 931 .Case("ppc", true) 932 .Case("powerpc64", true) 933 .Case("ppc64", true) 934 .Case("powerpc64le", true) 935 .Case("ppc64le", true) 936 .Default(false); 937 938 if (CPUKnown) 939 CPU = Name; 940 941 return CPUKnown; 942 } 943 944 945 StringRef getABI() const override { return ABI; } 946 947 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 948 return llvm::makeArrayRef(BuiltinInfo, 949 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 950 } 951 952 bool isCLZForZeroUndef() const override { return false; } 953 954 void getTargetDefines(const LangOptions &Opts, 955 MacroBuilder &Builder) const override; 956 957 bool 958 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 959 StringRef CPU, 960 const std::vector<std::string> &FeaturesVec) const override; 961 962 bool handleTargetFeatures(std::vector<std::string> &Features, 963 DiagnosticsEngine &Diags) override; 964 bool hasFeature(StringRef Feature) const override; 965 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 966 bool Enabled) const override; 967 968 ArrayRef<const char *> getGCCRegNames() const override; 969 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 970 bool validateAsmConstraint(const char *&Name, 971 TargetInfo::ConstraintInfo &Info) const override { 972 switch (*Name) { 973 default: return false; 974 case 'O': // Zero 975 break; 976 case 'b': // Base register 977 case 'f': // Floating point register 978 Info.setAllowsRegister(); 979 break; 980 // FIXME: The following are added to allow parsing. 981 // I just took a guess at what the actions should be. 982 // Also, is more specific checking needed? I.e. specific registers? 983 case 'd': // Floating point register (containing 64-bit value) 984 case 'v': // Altivec vector register 985 Info.setAllowsRegister(); 986 break; 987 case 'w': 988 switch (Name[1]) { 989 case 'd':// VSX vector register to hold vector double data 990 case 'f':// VSX vector register to hold vector float data 991 case 's':// VSX vector register to hold scalar float data 992 case 'a':// Any VSX register 993 case 'c':// An individual CR bit 994 break; 995 default: 996 return false; 997 } 998 Info.setAllowsRegister(); 999 Name++; // Skip over 'w'. 1000 break; 1001 case 'h': // `MQ', `CTR', or `LINK' register 1002 case 'q': // `MQ' register 1003 case 'c': // `CTR' register 1004 case 'l': // `LINK' register 1005 case 'x': // `CR' register (condition register) number 0 1006 case 'y': // `CR' register (condition register) 1007 case 'z': // `XER[CA]' carry bit (part of the XER register) 1008 Info.setAllowsRegister(); 1009 break; 1010 case 'I': // Signed 16-bit constant 1011 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1012 // (use `L' instead for SImode constants) 1013 case 'K': // Unsigned 16-bit constant 1014 case 'L': // Signed 16-bit constant shifted left 16 bits 1015 case 'M': // Constant larger than 31 1016 case 'N': // Exact power of 2 1017 case 'P': // Constant whose negation is a signed 16-bit constant 1018 case 'G': // Floating point constant that can be loaded into a 1019 // register with one instruction per word 1020 case 'H': // Integer/Floating point constant that can be loaded 1021 // into a register using three instructions 1022 break; 1023 case 'm': // Memory operand. Note that on PowerPC targets, m can 1024 // include addresses that update the base register. It 1025 // is therefore only safe to use `m' in an asm statement 1026 // if that asm statement accesses the operand exactly once. 1027 // The asm statement must also use `%U<opno>' as a 1028 // placeholder for the "update" flag in the corresponding 1029 // load or store instruction. For example: 1030 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1031 // is correct but: 1032 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1033 // is not. Use es rather than m if you don't want the base 1034 // register to be updated. 1035 case 'e': 1036 if (Name[1] != 's') 1037 return false; 1038 // es: A "stable" memory operand; that is, one which does not 1039 // include any automodification of the base register. Unlike 1040 // `m', this constraint can be used in asm statements that 1041 // might access the operand several times, or that might not 1042 // access it at all. 1043 Info.setAllowsMemory(); 1044 Name++; // Skip over 'e'. 1045 break; 1046 case 'Q': // Memory operand that is an offset from a register (it is 1047 // usually better to use `m' or `es' in asm statements) 1048 case 'Z': // Memory operand that is an indexed or indirect from a 1049 // register (it is usually better to use `m' or `es' in 1050 // asm statements) 1051 Info.setAllowsMemory(); 1052 Info.setAllowsRegister(); 1053 break; 1054 case 'R': // AIX TOC entry 1055 case 'a': // Address operand that is an indexed or indirect from a 1056 // register (`p' is preferable for asm statements) 1057 case 'S': // Constant suitable as a 64-bit mask operand 1058 case 'T': // Constant suitable as a 32-bit mask operand 1059 case 'U': // System V Release 4 small data area reference 1060 case 't': // AND masks that can be performed by two rldic{l, r} 1061 // instructions 1062 case 'W': // Vector constant that does not require memory 1063 case 'j': // Vector constant that is all zeros. 1064 break; 1065 // End FIXME. 1066 } 1067 return true; 1068 } 1069 std::string convertConstraint(const char *&Constraint) const override { 1070 std::string R; 1071 switch (*Constraint) { 1072 case 'e': 1073 case 'w': 1074 // Two-character constraint; add "^" hint for later parsing. 1075 R = std::string("^") + std::string(Constraint, 2); 1076 Constraint++; 1077 break; 1078 default: 1079 return TargetInfo::convertConstraint(Constraint); 1080 } 1081 return R; 1082 } 1083 const char *getClobbers() const override { 1084 return ""; 1085 } 1086 int getEHDataRegisterNumber(unsigned RegNo) const override { 1087 if (RegNo == 0) return 3; 1088 if (RegNo == 1) return 4; 1089 return -1; 1090 } 1091 1092 bool hasSjLjLowering() const override { 1093 return true; 1094 } 1095 1096 bool useFloat128ManglingForLongDouble() const override { 1097 return LongDoubleWidth == 128 && 1098 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1099 getTriple().isOSBinFormatELF(); 1100 } 1101 }; 1102 1103 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1104 #define BUILTIN(ID, TYPE, ATTRS) \ 1105 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1106 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1107 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1108 #include "clang/Basic/BuiltinsPPC.def" 1109 }; 1110 1111 /// handleTargetFeatures - Perform initialization based on the user 1112 /// configured set of features. 1113 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1114 DiagnosticsEngine &Diags) { 1115 for (const auto &Feature : Features) { 1116 if (Feature == "+vsx") { 1117 HasVSX = true; 1118 } else if (Feature == "+bpermd") { 1119 HasBPERMD = true; 1120 } else if (Feature == "+extdiv") { 1121 HasExtDiv = true; 1122 } else if (Feature == "+power8-vector") { 1123 HasP8Vector = true; 1124 } else if (Feature == "+crypto") { 1125 HasP8Crypto = true; 1126 } else if (Feature == "+direct-move") { 1127 HasDirectMove = true; 1128 } else if (Feature == "+qpx") { 1129 HasQPX = true; 1130 } else if (Feature == "+htm") { 1131 HasHTM = true; 1132 } else if (Feature == "+float128") { 1133 HasFloat128 = true; 1134 } 1135 // TODO: Finish this list and add an assert that we've handled them 1136 // all. 1137 } 1138 1139 return true; 1140 } 1141 1142 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1143 /// #defines that are not tied to a specific subtarget. 1144 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1145 MacroBuilder &Builder) const { 1146 // Target identification. 1147 Builder.defineMacro("__ppc__"); 1148 Builder.defineMacro("__PPC__"); 1149 Builder.defineMacro("_ARCH_PPC"); 1150 Builder.defineMacro("__powerpc__"); 1151 Builder.defineMacro("__POWERPC__"); 1152 if (PointerWidth == 64) { 1153 Builder.defineMacro("_ARCH_PPC64"); 1154 Builder.defineMacro("__powerpc64__"); 1155 Builder.defineMacro("__ppc64__"); 1156 Builder.defineMacro("__PPC64__"); 1157 } 1158 1159 // Target properties. 1160 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1161 Builder.defineMacro("_LITTLE_ENDIAN"); 1162 } else { 1163 if (getTriple().getOS() != llvm::Triple::NetBSD && 1164 getTriple().getOS() != llvm::Triple::OpenBSD) 1165 Builder.defineMacro("_BIG_ENDIAN"); 1166 } 1167 1168 // ABI options. 1169 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1170 Builder.defineMacro("_CALL_ELF", "1"); 1171 if (ABI == "elfv2") 1172 Builder.defineMacro("_CALL_ELF", "2"); 1173 1174 // Subtarget options. 1175 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1176 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1177 1178 // FIXME: Should be controlled by command line option. 1179 if (LongDoubleWidth == 128) 1180 Builder.defineMacro("__LONG_DOUBLE_128__"); 1181 1182 if (Opts.AltiVec) { 1183 Builder.defineMacro("__VEC__", "10206"); 1184 Builder.defineMacro("__ALTIVEC__"); 1185 } 1186 1187 // CPU identification. 1188 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1189 .Case("440", ArchDefineName) 1190 .Case("450", ArchDefineName | ArchDefine440) 1191 .Case("601", ArchDefineName) 1192 .Case("602", ArchDefineName | ArchDefinePpcgr) 1193 .Case("603", ArchDefineName | ArchDefinePpcgr) 1194 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1195 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1196 .Case("604", ArchDefineName | ArchDefinePpcgr) 1197 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1198 .Case("620", ArchDefineName | ArchDefinePpcgr) 1199 .Case("630", ArchDefineName | ArchDefinePpcgr) 1200 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1201 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1202 .Case("750", ArchDefineName | ArchDefinePpcgr) 1203 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1204 | ArchDefinePpcsq) 1205 .Case("a2", ArchDefineA2) 1206 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1207 .Case("pwr3", ArchDefinePpcgr) 1208 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1209 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1210 | ArchDefinePpcsq) 1211 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1212 | ArchDefinePpcgr | ArchDefinePpcsq) 1213 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1214 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1215 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1216 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1217 | ArchDefinePpcsq) 1218 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1219 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1220 | ArchDefinePpcgr | ArchDefinePpcsq) 1221 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1222 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1223 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1224 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 1225 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1226 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1227 | ArchDefinePpcsq) 1228 .Case("power3", ArchDefinePpcgr) 1229 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1230 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1231 | ArchDefinePpcsq) 1232 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1233 | ArchDefinePpcgr | ArchDefinePpcsq) 1234 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1235 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1236 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1237 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1238 | ArchDefinePpcsq) 1239 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1240 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1241 | ArchDefinePpcgr | ArchDefinePpcsq) 1242 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1243 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1244 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1245 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 1246 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1247 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1248 | ArchDefinePpcsq) 1249 .Default(ArchDefineNone); 1250 1251 if (defs & ArchDefineName) 1252 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1253 if (defs & ArchDefinePpcgr) 1254 Builder.defineMacro("_ARCH_PPCGR"); 1255 if (defs & ArchDefinePpcsq) 1256 Builder.defineMacro("_ARCH_PPCSQ"); 1257 if (defs & ArchDefine440) 1258 Builder.defineMacro("_ARCH_440"); 1259 if (defs & ArchDefine603) 1260 Builder.defineMacro("_ARCH_603"); 1261 if (defs & ArchDefine604) 1262 Builder.defineMacro("_ARCH_604"); 1263 if (defs & ArchDefinePwr4) 1264 Builder.defineMacro("_ARCH_PWR4"); 1265 if (defs & ArchDefinePwr5) 1266 Builder.defineMacro("_ARCH_PWR5"); 1267 if (defs & ArchDefinePwr5x) 1268 Builder.defineMacro("_ARCH_PWR5X"); 1269 if (defs & ArchDefinePwr6) 1270 Builder.defineMacro("_ARCH_PWR6"); 1271 if (defs & ArchDefinePwr6x) 1272 Builder.defineMacro("_ARCH_PWR6X"); 1273 if (defs & ArchDefinePwr7) 1274 Builder.defineMacro("_ARCH_PWR7"); 1275 if (defs & ArchDefinePwr8) 1276 Builder.defineMacro("_ARCH_PWR8"); 1277 if (defs & ArchDefinePwr9) 1278 Builder.defineMacro("_ARCH_PWR9"); 1279 if (defs & ArchDefineA2) 1280 Builder.defineMacro("_ARCH_A2"); 1281 if (defs & ArchDefineA2q) { 1282 Builder.defineMacro("_ARCH_A2Q"); 1283 Builder.defineMacro("_ARCH_QP"); 1284 } 1285 1286 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1287 Builder.defineMacro("__bg__"); 1288 Builder.defineMacro("__THW_BLUEGENE__"); 1289 Builder.defineMacro("__bgq__"); 1290 Builder.defineMacro("__TOS_BGQ__"); 1291 } 1292 1293 if (HasVSX) 1294 Builder.defineMacro("__VSX__"); 1295 if (HasP8Vector) 1296 Builder.defineMacro("__POWER8_VECTOR__"); 1297 if (HasP8Crypto) 1298 Builder.defineMacro("__CRYPTO__"); 1299 if (HasHTM) 1300 Builder.defineMacro("__HTM__"); 1301 if (HasFloat128) 1302 Builder.defineMacro("__FLOAT128__"); 1303 1304 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1305 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1306 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1307 if (PointerWidth == 64) 1308 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1309 1310 // FIXME: The following are not yet generated here by Clang, but are 1311 // generated by GCC: 1312 // 1313 // _SOFT_FLOAT_ 1314 // __RECIP_PRECISION__ 1315 // __APPLE_ALTIVEC__ 1316 // __RECIP__ 1317 // __RECIPF__ 1318 // __RSQRTE__ 1319 // __RSQRTEF__ 1320 // _SOFT_DOUBLE_ 1321 // __NO_LWSYNC__ 1322 // __HAVE_BSWAP__ 1323 // __LONGDOUBLE128 1324 // __CMODEL_MEDIUM__ 1325 // __CMODEL_LARGE__ 1326 // _CALL_SYSV 1327 // _CALL_DARWIN 1328 // __NO_FPRS__ 1329 } 1330 1331 // Handle explicit options being passed to the compiler here: if we've 1332 // explicitly turned off vsx and turned on power8-vector or direct-move then 1333 // go ahead and error since the customer has expressed a somewhat incompatible 1334 // set of options. 1335 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1336 const std::vector<std::string> &FeaturesVec) { 1337 1338 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1339 FeaturesVec.end()) { 1340 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1341 FeaturesVec.end()) { 1342 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1343 << "-mno-vsx"; 1344 return false; 1345 } 1346 1347 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1348 FeaturesVec.end()) { 1349 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1350 << "-mno-vsx"; 1351 return false; 1352 } 1353 1354 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1355 FeaturesVec.end()) { 1356 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1357 << "-mno-vsx"; 1358 return false; 1359 } 1360 } 1361 1362 return true; 1363 } 1364 1365 bool PPCTargetInfo::initFeatureMap( 1366 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1367 const std::vector<std::string> &FeaturesVec) const { 1368 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1369 .Case("7400", true) 1370 .Case("g4", true) 1371 .Case("7450", true) 1372 .Case("g4+", true) 1373 .Case("970", true) 1374 .Case("g5", true) 1375 .Case("pwr6", true) 1376 .Case("pwr7", true) 1377 .Case("pwr8", true) 1378 .Case("pwr9", true) 1379 .Case("ppc64", true) 1380 .Case("ppc64le", true) 1381 .Default(false); 1382 1383 Features["qpx"] = (CPU == "a2q"); 1384 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1385 .Case("ppc64le", true) 1386 .Case("pwr9", true) 1387 .Case("pwr8", true) 1388 .Default(false); 1389 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1390 .Case("ppc64le", true) 1391 .Case("pwr9", true) 1392 .Case("pwr8", true) 1393 .Default(false); 1394 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1395 .Case("ppc64le", true) 1396 .Case("pwr9", true) 1397 .Case("pwr8", true) 1398 .Case("pwr7", true) 1399 .Default(false); 1400 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1401 .Case("ppc64le", true) 1402 .Case("pwr9", true) 1403 .Case("pwr8", true) 1404 .Case("pwr7", true) 1405 .Default(false); 1406 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1407 .Case("ppc64le", true) 1408 .Case("pwr9", true) 1409 .Case("pwr8", true) 1410 .Default(false); 1411 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1412 .Case("ppc64le", true) 1413 .Case("pwr9", true) 1414 .Case("pwr8", true) 1415 .Case("pwr7", true) 1416 .Default(false); 1417 1418 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1419 return false; 1420 1421 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1422 } 1423 1424 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1425 return llvm::StringSwitch<bool>(Feature) 1426 .Case("powerpc", true) 1427 .Case("vsx", HasVSX) 1428 .Case("power8-vector", HasP8Vector) 1429 .Case("crypto", HasP8Crypto) 1430 .Case("direct-move", HasDirectMove) 1431 .Case("qpx", HasQPX) 1432 .Case("htm", HasHTM) 1433 .Case("bpermd", HasBPERMD) 1434 .Case("extdiv", HasExtDiv) 1435 .Case("float128", HasFloat128) 1436 .Default(false); 1437 } 1438 1439 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1440 StringRef Name, bool Enabled) const { 1441 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1442 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1443 // incompatible options. 1444 if (Enabled) { 1445 if (Name == "direct-move") { 1446 Features[Name] = Features["vsx"] = true; 1447 } else if (Name == "power8-vector") { 1448 Features[Name] = Features["vsx"] = true; 1449 } else if (Name == "float128") { 1450 Features[Name] = Features["vsx"] = true; 1451 } else { 1452 Features[Name] = true; 1453 } 1454 } else { 1455 if (Name == "vsx") { 1456 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1457 Features["float128"] = false; 1458 } else { 1459 Features[Name] = false; 1460 } 1461 } 1462 } 1463 1464 const char * const PPCTargetInfo::GCCRegNames[] = { 1465 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1466 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1467 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1468 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1469 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1470 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1471 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1472 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1473 "mq", "lr", "ctr", "ap", 1474 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1475 "xer", 1476 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1477 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1478 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1479 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1480 "vrsave", "vscr", 1481 "spe_acc", "spefscr", 1482 "sfp" 1483 }; 1484 1485 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1486 return llvm::makeArrayRef(GCCRegNames); 1487 } 1488 1489 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1490 // While some of these aliases do map to different registers 1491 // they still share the same register name. 1492 { { "0" }, "r0" }, 1493 { { "1"}, "r1" }, 1494 { { "2" }, "r2" }, 1495 { { "3" }, "r3" }, 1496 { { "4" }, "r4" }, 1497 { { "5" }, "r5" }, 1498 { { "6" }, "r6" }, 1499 { { "7" }, "r7" }, 1500 { { "8" }, "r8" }, 1501 { { "9" }, "r9" }, 1502 { { "10" }, "r10" }, 1503 { { "11" }, "r11" }, 1504 { { "12" }, "r12" }, 1505 { { "13" }, "r13" }, 1506 { { "14" }, "r14" }, 1507 { { "15" }, "r15" }, 1508 { { "16" }, "r16" }, 1509 { { "17" }, "r17" }, 1510 { { "18" }, "r18" }, 1511 { { "19" }, "r19" }, 1512 { { "20" }, "r20" }, 1513 { { "21" }, "r21" }, 1514 { { "22" }, "r22" }, 1515 { { "23" }, "r23" }, 1516 { { "24" }, "r24" }, 1517 { { "25" }, "r25" }, 1518 { { "26" }, "r26" }, 1519 { { "27" }, "r27" }, 1520 { { "28" }, "r28" }, 1521 { { "29" }, "r29" }, 1522 { { "30" }, "r30" }, 1523 { { "31" }, "r31" }, 1524 { { "fr0" }, "f0" }, 1525 { { "fr1" }, "f1" }, 1526 { { "fr2" }, "f2" }, 1527 { { "fr3" }, "f3" }, 1528 { { "fr4" }, "f4" }, 1529 { { "fr5" }, "f5" }, 1530 { { "fr6" }, "f6" }, 1531 { { "fr7" }, "f7" }, 1532 { { "fr8" }, "f8" }, 1533 { { "fr9" }, "f9" }, 1534 { { "fr10" }, "f10" }, 1535 { { "fr11" }, "f11" }, 1536 { { "fr12" }, "f12" }, 1537 { { "fr13" }, "f13" }, 1538 { { "fr14" }, "f14" }, 1539 { { "fr15" }, "f15" }, 1540 { { "fr16" }, "f16" }, 1541 { { "fr17" }, "f17" }, 1542 { { "fr18" }, "f18" }, 1543 { { "fr19" }, "f19" }, 1544 { { "fr20" }, "f20" }, 1545 { { "fr21" }, "f21" }, 1546 { { "fr22" }, "f22" }, 1547 { { "fr23" }, "f23" }, 1548 { { "fr24" }, "f24" }, 1549 { { "fr25" }, "f25" }, 1550 { { "fr26" }, "f26" }, 1551 { { "fr27" }, "f27" }, 1552 { { "fr28" }, "f28" }, 1553 { { "fr29" }, "f29" }, 1554 { { "fr30" }, "f30" }, 1555 { { "fr31" }, "f31" }, 1556 { { "cc" }, "cr0" }, 1557 }; 1558 1559 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1560 return llvm::makeArrayRef(GCCRegAliases); 1561 } 1562 1563 class PPC32TargetInfo : public PPCTargetInfo { 1564 public: 1565 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1566 : PPCTargetInfo(Triple, Opts) { 1567 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1568 1569 switch (getTriple().getOS()) { 1570 case llvm::Triple::Linux: 1571 case llvm::Triple::FreeBSD: 1572 case llvm::Triple::NetBSD: 1573 SizeType = UnsignedInt; 1574 PtrDiffType = SignedInt; 1575 IntPtrType = SignedInt; 1576 break; 1577 default: 1578 break; 1579 } 1580 1581 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1582 LongDoubleWidth = LongDoubleAlign = 64; 1583 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1584 } 1585 1586 // PPC32 supports atomics up to 4 bytes. 1587 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1588 } 1589 1590 BuiltinVaListKind getBuiltinVaListKind() const override { 1591 // This is the ELF definition, and is overridden by the Darwin sub-target 1592 return TargetInfo::PowerABIBuiltinVaList; 1593 } 1594 }; 1595 1596 // Note: ABI differences may eventually require us to have a separate 1597 // TargetInfo for little endian. 1598 class PPC64TargetInfo : public PPCTargetInfo { 1599 public: 1600 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1601 : PPCTargetInfo(Triple, Opts) { 1602 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1603 IntMaxType = SignedLong; 1604 Int64Type = SignedLong; 1605 1606 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1607 resetDataLayout("e-m:e-i64:64-n32:64"); 1608 ABI = "elfv2"; 1609 } else { 1610 resetDataLayout("E-m:e-i64:64-n32:64"); 1611 ABI = "elfv1"; 1612 } 1613 1614 switch (getTriple().getOS()) { 1615 case llvm::Triple::FreeBSD: 1616 LongDoubleWidth = LongDoubleAlign = 64; 1617 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1618 break; 1619 case llvm::Triple::NetBSD: 1620 IntMaxType = SignedLongLong; 1621 Int64Type = SignedLongLong; 1622 break; 1623 default: 1624 break; 1625 } 1626 1627 // PPC64 supports atomics up to 8 bytes. 1628 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1629 } 1630 BuiltinVaListKind getBuiltinVaListKind() const override { 1631 return TargetInfo::CharPtrBuiltinVaList; 1632 } 1633 // PPC64 Linux-specific ABI options. 1634 bool setABI(const std::string &Name) override { 1635 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1636 ABI = Name; 1637 return true; 1638 } 1639 return false; 1640 } 1641 }; 1642 1643 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1644 public: 1645 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1646 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1647 HasAlignMac68kSupport = true; 1648 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1649 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1650 LongLongAlign = 32; 1651 SuitableAlign = 128; 1652 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1653 } 1654 BuiltinVaListKind getBuiltinVaListKind() const override { 1655 return TargetInfo::CharPtrBuiltinVaList; 1656 } 1657 }; 1658 1659 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1660 public: 1661 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1662 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1663 HasAlignMac68kSupport = true; 1664 SuitableAlign = 128; 1665 resetDataLayout("E-m:o-i64:64-n32:64"); 1666 } 1667 }; 1668 1669 static const unsigned NVPTXAddrSpaceMap[] = { 1670 1, // opencl_global 1671 3, // opencl_local 1672 4, // opencl_constant 1673 // FIXME: generic has to be added to the target 1674 0, // opencl_generic 1675 1, // cuda_device 1676 4, // cuda_constant 1677 3, // cuda_shared 1678 }; 1679 1680 class NVPTXTargetInfo : public TargetInfo { 1681 static const char *const GCCRegNames[]; 1682 static const Builtin::Info BuiltinInfo[]; 1683 1684 // The GPU profiles supported by the NVPTX backend 1685 enum GPUKind { 1686 GK_NONE, 1687 GK_SM20, 1688 GK_SM21, 1689 GK_SM30, 1690 GK_SM35, 1691 GK_SM37, 1692 } GPU; 1693 1694 public: 1695 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1696 : TargetInfo(Triple) { 1697 BigEndian = false; 1698 TLSSupported = false; 1699 LongWidth = LongAlign = 64; 1700 AddrSpaceMap = &NVPTXAddrSpaceMap; 1701 UseAddrSpaceMapMangling = true; 1702 // Define available target features 1703 // These must be defined in sorted order! 1704 NoAsmVariants = true; 1705 // Set the default GPU to sm20 1706 GPU = GK_SM20; 1707 1708 // If possible, get a TargetInfo for our host triple, so we can match its 1709 // types. 1710 llvm::Triple HostTriple(Opts.HostTriple); 1711 if (HostTriple.isNVPTX()) 1712 return; 1713 std::unique_ptr<TargetInfo> HostTarget( 1714 AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1715 if (!HostTarget) { 1716 return; 1717 } 1718 1719 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1720 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1721 BoolWidth = HostTarget->getBoolWidth(); 1722 BoolAlign = HostTarget->getBoolAlign(); 1723 IntWidth = HostTarget->getIntWidth(); 1724 IntAlign = HostTarget->getIntAlign(); 1725 HalfWidth = HostTarget->getHalfWidth(); 1726 HalfAlign = HostTarget->getHalfAlign(); 1727 FloatWidth = HostTarget->getFloatWidth(); 1728 FloatAlign = HostTarget->getFloatAlign(); 1729 DoubleWidth = HostTarget->getDoubleWidth(); 1730 DoubleAlign = HostTarget->getDoubleAlign(); 1731 LongWidth = HostTarget->getLongWidth(); 1732 LongAlign = HostTarget->getLongAlign(); 1733 LongLongWidth = HostTarget->getLongLongWidth(); 1734 LongLongAlign = HostTarget->getLongLongAlign(); 1735 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1736 DefaultAlignForAttributeAligned = 1737 HostTarget->getDefaultAlignForAttributeAligned(); 1738 SizeType = HostTarget->getSizeType(); 1739 IntMaxType = HostTarget->getIntMaxType(); 1740 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1741 IntPtrType = HostTarget->getIntPtrType(); 1742 WCharType = HostTarget->getWCharType(); 1743 WIntType = HostTarget->getWIntType(); 1744 Char16Type = HostTarget->getChar16Type(); 1745 Char32Type = HostTarget->getChar32Type(); 1746 Int64Type = HostTarget->getInt64Type(); 1747 SigAtomicType = HostTarget->getSigAtomicType(); 1748 ProcessIDType = HostTarget->getProcessIDType(); 1749 1750 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1751 UseZeroLengthBitfieldAlignment = 1752 HostTarget->useZeroLengthBitfieldAlignment(); 1753 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1754 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1755 1756 // Properties intentionally not copied from host: 1757 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1758 // host/device boundary. 1759 // - SuitableAlign: Not visible across the host/device boundary, and may 1760 // correctly be different on host/device, e.g. if host has wider vector 1761 // types than device. 1762 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1763 // as its double type, but that's not necessarily true on the host. 1764 // TODO: nvcc emits a warning when using long double on device; we should 1765 // do the same. 1766 } 1767 void getTargetDefines(const LangOptions &Opts, 1768 MacroBuilder &Builder) const override { 1769 Builder.defineMacro("__PTX__"); 1770 Builder.defineMacro("__NVPTX__"); 1771 if (Opts.CUDAIsDevice) { 1772 // Set __CUDA_ARCH__ for the GPU specified. 1773 std::string CUDAArchCode; 1774 switch (GPU) { 1775 case GK_SM20: 1776 CUDAArchCode = "200"; 1777 break; 1778 case GK_SM21: 1779 CUDAArchCode = "210"; 1780 break; 1781 case GK_SM30: 1782 CUDAArchCode = "300"; 1783 break; 1784 case GK_SM35: 1785 CUDAArchCode = "350"; 1786 break; 1787 case GK_SM37: 1788 CUDAArchCode = "370"; 1789 break; 1790 default: 1791 llvm_unreachable("Unhandled target CPU"); 1792 } 1793 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1794 } 1795 } 1796 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1797 return llvm::makeArrayRef(BuiltinInfo, 1798 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1799 } 1800 bool hasFeature(StringRef Feature) const override { 1801 return Feature == "ptx" || Feature == "nvptx"; 1802 } 1803 1804 ArrayRef<const char *> getGCCRegNames() const override; 1805 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1806 // No aliases. 1807 return None; 1808 } 1809 bool validateAsmConstraint(const char *&Name, 1810 TargetInfo::ConstraintInfo &Info) const override { 1811 switch (*Name) { 1812 default: 1813 return false; 1814 case 'c': 1815 case 'h': 1816 case 'r': 1817 case 'l': 1818 case 'f': 1819 case 'd': 1820 Info.setAllowsRegister(); 1821 return true; 1822 } 1823 } 1824 const char *getClobbers() const override { 1825 // FIXME: Is this really right? 1826 return ""; 1827 } 1828 BuiltinVaListKind getBuiltinVaListKind() const override { 1829 // FIXME: implement 1830 return TargetInfo::CharPtrBuiltinVaList; 1831 } 1832 bool setCPU(const std::string &Name) override { 1833 GPU = llvm::StringSwitch<GPUKind>(Name) 1834 .Case("sm_20", GK_SM20) 1835 .Case("sm_21", GK_SM21) 1836 .Case("sm_30", GK_SM30) 1837 .Case("sm_35", GK_SM35) 1838 .Case("sm_37", GK_SM37) 1839 .Default(GK_NONE); 1840 1841 return GPU != GK_NONE; 1842 } 1843 }; 1844 1845 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1846 #define BUILTIN(ID, TYPE, ATTRS) \ 1847 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1848 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1849 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1850 #include "clang/Basic/BuiltinsNVPTX.def" 1851 }; 1852 1853 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1854 1855 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1856 return llvm::makeArrayRef(GCCRegNames); 1857 } 1858 1859 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1860 public: 1861 NVPTX32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1862 : NVPTXTargetInfo(Triple, Opts) { 1863 LongWidth = LongAlign = 32; 1864 PointerWidth = PointerAlign = 32; 1865 SizeType = TargetInfo::UnsignedInt; 1866 PtrDiffType = TargetInfo::SignedInt; 1867 IntPtrType = TargetInfo::SignedInt; 1868 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1869 } 1870 }; 1871 1872 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1873 public: 1874 NVPTX64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1875 : NVPTXTargetInfo(Triple, Opts) { 1876 PointerWidth = PointerAlign = 64; 1877 SizeType = TargetInfo::UnsignedLong; 1878 PtrDiffType = TargetInfo::SignedLong; 1879 IntPtrType = TargetInfo::SignedLong; 1880 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1881 } 1882 }; 1883 1884 static const unsigned AMDGPUAddrSpaceMap[] = { 1885 1, // opencl_global 1886 3, // opencl_local 1887 2, // opencl_constant 1888 4, // opencl_generic 1889 1, // cuda_device 1890 2, // cuda_constant 1891 3 // cuda_shared 1892 }; 1893 1894 // If you edit the description strings, make sure you update 1895 // getPointerWidthV(). 1896 1897 static const char *const DataLayoutStringR600 = 1898 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1899 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1900 1901 static const char *const DataLayoutStringSI = 1902 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1903 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1904 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1905 1906 class AMDGPUTargetInfo : public TargetInfo { 1907 static const Builtin::Info BuiltinInfo[]; 1908 static const char * const GCCRegNames[]; 1909 1910 /// \brief The GPU profiles supported by the AMDGPU target. 1911 enum GPUKind { 1912 GK_NONE, 1913 GK_R600, 1914 GK_R600_DOUBLE_OPS, 1915 GK_R700, 1916 GK_R700_DOUBLE_OPS, 1917 GK_EVERGREEN, 1918 GK_EVERGREEN_DOUBLE_OPS, 1919 GK_NORTHERN_ISLANDS, 1920 GK_CAYMAN, 1921 GK_SOUTHERN_ISLANDS, 1922 GK_SEA_ISLANDS, 1923 GK_VOLCANIC_ISLANDS 1924 } GPU; 1925 1926 bool hasFP64:1; 1927 bool hasFMAF:1; 1928 bool hasLDEXPF:1; 1929 1930 public: 1931 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 1932 : TargetInfo(Triple) { 1933 if (Triple.getArch() == llvm::Triple::amdgcn) { 1934 resetDataLayout(DataLayoutStringSI); 1935 GPU = GK_SOUTHERN_ISLANDS; 1936 hasFP64 = true; 1937 hasFMAF = true; 1938 hasLDEXPF = true; 1939 } else { 1940 resetDataLayout(DataLayoutStringR600); 1941 GPU = GK_R600; 1942 hasFP64 = false; 1943 hasFMAF = false; 1944 hasLDEXPF = false; 1945 } 1946 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1947 UseAddrSpaceMapMangling = true; 1948 } 1949 1950 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1951 if (GPU <= GK_CAYMAN) 1952 return 32; 1953 1954 switch(AddrSpace) { 1955 default: 1956 return 64; 1957 case 0: 1958 case 3: 1959 case 5: 1960 return 32; 1961 } 1962 } 1963 1964 const char * getClobbers() const override { 1965 return ""; 1966 } 1967 1968 ArrayRef<const char *> getGCCRegNames() const override; 1969 1970 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1971 return None; 1972 } 1973 1974 bool validateAsmConstraint(const char *&Name, 1975 TargetInfo::ConstraintInfo &Info) const override { 1976 switch (*Name) { 1977 default: break; 1978 case 'v': // vgpr 1979 case 's': // sgpr 1980 Info.setAllowsRegister(); 1981 return true; 1982 } 1983 return false; 1984 } 1985 1986 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1987 return llvm::makeArrayRef(BuiltinInfo, 1988 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 1989 } 1990 1991 void getTargetDefines(const LangOptions &Opts, 1992 MacroBuilder &Builder) const override { 1993 if (getTriple().getArch() == llvm::Triple::amdgcn) 1994 Builder.defineMacro("__AMDGCN__"); 1995 else 1996 Builder.defineMacro("__R600__"); 1997 1998 if (hasFMAF) 1999 Builder.defineMacro("__HAS_FMAF__"); 2000 if (hasLDEXPF) 2001 Builder.defineMacro("__HAS_LDEXPF__"); 2002 } 2003 2004 BuiltinVaListKind getBuiltinVaListKind() const override { 2005 return TargetInfo::CharPtrBuiltinVaList; 2006 } 2007 2008 bool setCPU(const std::string &Name) override { 2009 GPU = llvm::StringSwitch<GPUKind>(Name) 2010 .Case("r600" , GK_R600) 2011 .Case("rv610", GK_R600) 2012 .Case("rv620", GK_R600) 2013 .Case("rv630", GK_R600) 2014 .Case("rv635", GK_R600) 2015 .Case("rs780", GK_R600) 2016 .Case("rs880", GK_R600) 2017 .Case("rv670", GK_R600_DOUBLE_OPS) 2018 .Case("rv710", GK_R700) 2019 .Case("rv730", GK_R700) 2020 .Case("rv740", GK_R700_DOUBLE_OPS) 2021 .Case("rv770", GK_R700_DOUBLE_OPS) 2022 .Case("palm", GK_EVERGREEN) 2023 .Case("cedar", GK_EVERGREEN) 2024 .Case("sumo", GK_EVERGREEN) 2025 .Case("sumo2", GK_EVERGREEN) 2026 .Case("redwood", GK_EVERGREEN) 2027 .Case("juniper", GK_EVERGREEN) 2028 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2029 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2030 .Case("barts", GK_NORTHERN_ISLANDS) 2031 .Case("turks", GK_NORTHERN_ISLANDS) 2032 .Case("caicos", GK_NORTHERN_ISLANDS) 2033 .Case("cayman", GK_CAYMAN) 2034 .Case("aruba", GK_CAYMAN) 2035 .Case("tahiti", GK_SOUTHERN_ISLANDS) 2036 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 2037 .Case("verde", GK_SOUTHERN_ISLANDS) 2038 .Case("oland", GK_SOUTHERN_ISLANDS) 2039 .Case("hainan", GK_SOUTHERN_ISLANDS) 2040 .Case("bonaire", GK_SEA_ISLANDS) 2041 .Case("kabini", GK_SEA_ISLANDS) 2042 .Case("kaveri", GK_SEA_ISLANDS) 2043 .Case("hawaii", GK_SEA_ISLANDS) 2044 .Case("mullins", GK_SEA_ISLANDS) 2045 .Case("tonga", GK_VOLCANIC_ISLANDS) 2046 .Case("iceland", GK_VOLCANIC_ISLANDS) 2047 .Case("carrizo", GK_VOLCANIC_ISLANDS) 2048 .Case("fiji", GK_VOLCANIC_ISLANDS) 2049 .Case("stoney", GK_VOLCANIC_ISLANDS) 2050 .Default(GK_NONE); 2051 2052 if (GPU == GK_NONE) { 2053 return false; 2054 } 2055 2056 // Set the correct data layout 2057 switch (GPU) { 2058 case GK_NONE: 2059 case GK_R600: 2060 case GK_R700: 2061 case GK_EVERGREEN: 2062 case GK_NORTHERN_ISLANDS: 2063 resetDataLayout(DataLayoutStringR600); 2064 hasFP64 = false; 2065 hasFMAF = false; 2066 hasLDEXPF = false; 2067 break; 2068 case GK_R600_DOUBLE_OPS: 2069 case GK_R700_DOUBLE_OPS: 2070 case GK_EVERGREEN_DOUBLE_OPS: 2071 case GK_CAYMAN: 2072 resetDataLayout(DataLayoutStringR600); 2073 hasFP64 = true; 2074 hasFMAF = true; 2075 hasLDEXPF = false; 2076 break; 2077 case GK_SOUTHERN_ISLANDS: 2078 case GK_SEA_ISLANDS: 2079 case GK_VOLCANIC_ISLANDS: 2080 resetDataLayout(DataLayoutStringSI); 2081 hasFP64 = true; 2082 hasFMAF = true; 2083 hasLDEXPF = true; 2084 break; 2085 } 2086 2087 return true; 2088 } 2089 2090 void setSupportedOpenCLOpts() override { 2091 auto &Opts = getSupportedOpenCLOpts(); 2092 Opts.cl_clang_storage_class_specifiers = 1; 2093 Opts.cl_khr_gl_sharing = 1; 2094 Opts.cl_khr_gl_event = 1; 2095 Opts.cl_khr_d3d10_sharing = 1; 2096 Opts.cl_khr_subgroups = 1; 2097 2098 if (hasFP64) 2099 Opts.cl_khr_fp64 = 1; 2100 if (GPU >= GK_NORTHERN_ISLANDS) { 2101 Opts.cl_khr_byte_addressable_store = 1; 2102 Opts.cl_khr_global_int32_base_atomics = 1; 2103 Opts.cl_khr_global_int32_extended_atomics = 1; 2104 Opts.cl_khr_local_int32_base_atomics = 1; 2105 Opts.cl_khr_local_int32_extended_atomics = 1; 2106 } 2107 if (GPU >= GK_SOUTHERN_ISLANDS) 2108 Opts.cl_khr_fp16 = 1; 2109 Opts.cl_khr_int64_base_atomics = 1; 2110 Opts.cl_khr_int64_extended_atomics = 1; 2111 Opts.cl_khr_3d_image_writes = 1; 2112 Opts.cl_khr_gl_msaa_sharing = 1; 2113 } 2114 }; 2115 2116 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2117 #define BUILTIN(ID, TYPE, ATTRS) \ 2118 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2119 #include "clang/Basic/BuiltinsAMDGPU.def" 2120 }; 2121 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2122 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2123 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2124 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2125 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2126 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2127 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2128 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2129 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2130 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2131 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2132 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2133 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2134 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2135 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2136 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2137 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2138 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2139 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2140 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2141 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2142 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2143 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2144 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2145 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2146 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2147 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2148 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2149 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2150 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2151 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2152 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2153 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2154 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2155 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2156 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2157 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2158 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2159 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2160 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2161 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2162 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2163 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2164 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2165 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2166 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2167 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2168 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2169 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2170 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2171 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2172 }; 2173 2174 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2175 return llvm::makeArrayRef(GCCRegNames); 2176 } 2177 2178 // Namespace for x86 abstract base class 2179 const Builtin::Info BuiltinInfo[] = { 2180 #define BUILTIN(ID, TYPE, ATTRS) \ 2181 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2182 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2183 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2184 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2185 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2186 #include "clang/Basic/BuiltinsX86.def" 2187 }; 2188 2189 static const char* const GCCRegNames[] = { 2190 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2191 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2192 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2193 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2194 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2195 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2196 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2197 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2198 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2199 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2200 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2201 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2202 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2203 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2204 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2205 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2206 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2207 }; 2208 2209 const TargetInfo::AddlRegName AddlRegNames[] = { 2210 { { "al", "ah", "eax", "rax" }, 0 }, 2211 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2212 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2213 { { "dl", "dh", "edx", "rdx" }, 1 }, 2214 { { "esi", "rsi" }, 4 }, 2215 { { "edi", "rdi" }, 5 }, 2216 { { "esp", "rsp" }, 7 }, 2217 { { "ebp", "rbp" }, 6 }, 2218 { { "r8d", "r8w", "r8b" }, 38 }, 2219 { { "r9d", "r9w", "r9b" }, 39 }, 2220 { { "r10d", "r10w", "r10b" }, 40 }, 2221 { { "r11d", "r11w", "r11b" }, 41 }, 2222 { { "r12d", "r12w", "r12b" }, 42 }, 2223 { { "r13d", "r13w", "r13b" }, 43 }, 2224 { { "r14d", "r14w", "r14b" }, 44 }, 2225 { { "r15d", "r15w", "r15b" }, 45 }, 2226 }; 2227 2228 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2229 // most of the implementation can be shared. 2230 class X86TargetInfo : public TargetInfo { 2231 enum X86SSEEnum { 2232 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2233 } SSELevel = NoSSE; 2234 enum MMX3DNowEnum { 2235 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2236 } MMX3DNowLevel = NoMMX3DNow; 2237 enum XOPEnum { 2238 NoXOP, 2239 SSE4A, 2240 FMA4, 2241 XOP 2242 } XOPLevel = NoXOP; 2243 2244 bool HasAES = false; 2245 bool HasPCLMUL = false; 2246 bool HasLZCNT = false; 2247 bool HasRDRND = false; 2248 bool HasFSGSBASE = false; 2249 bool HasBMI = false; 2250 bool HasBMI2 = false; 2251 bool HasPOPCNT = false; 2252 bool HasRTM = false; 2253 bool HasPRFCHW = false; 2254 bool HasRDSEED = false; 2255 bool HasADX = false; 2256 bool HasTBM = false; 2257 bool HasFMA = false; 2258 bool HasF16C = false; 2259 bool HasAVX512CD = false; 2260 bool HasAVX512ER = false; 2261 bool HasAVX512PF = false; 2262 bool HasAVX512DQ = false; 2263 bool HasAVX512BW = false; 2264 bool HasAVX512VL = false; 2265 bool HasAVX512VBMI = false; 2266 bool HasAVX512IFMA = false; 2267 bool HasSHA = false; 2268 bool HasMPX = false; 2269 bool HasSGX = false; 2270 bool HasCX16 = false; 2271 bool HasFXSR = false; 2272 bool HasXSAVE = false; 2273 bool HasXSAVEOPT = false; 2274 bool HasXSAVEC = false; 2275 bool HasXSAVES = false; 2276 bool HasPKU = false; 2277 bool HasCLFLUSHOPT = false; 2278 bool HasPCOMMIT = false; 2279 bool HasCLWB = false; 2280 bool HasUMIP = false; 2281 bool HasMOVBE = false; 2282 bool HasPREFETCHWT1 = false; 2283 2284 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2285 /// 2286 /// Each enumeration represents a particular CPU supported by Clang. These 2287 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2288 enum CPUKind { 2289 CK_Generic, 2290 2291 /// \name i386 2292 /// i386-generation processors. 2293 //@{ 2294 CK_i386, 2295 //@} 2296 2297 /// \name i486 2298 /// i486-generation processors. 2299 //@{ 2300 CK_i486, 2301 CK_WinChipC6, 2302 CK_WinChip2, 2303 CK_C3, 2304 //@} 2305 2306 /// \name i586 2307 /// i586-generation processors, P5 microarchitecture based. 2308 //@{ 2309 CK_i586, 2310 CK_Pentium, 2311 CK_PentiumMMX, 2312 //@} 2313 2314 /// \name i686 2315 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2316 //@{ 2317 CK_i686, 2318 CK_PentiumPro, 2319 CK_Pentium2, 2320 CK_Pentium3, 2321 CK_Pentium3M, 2322 CK_PentiumM, 2323 CK_C3_2, 2324 2325 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2326 /// Clang however has some logic to suport this. 2327 // FIXME: Warn, deprecate, and potentially remove this. 2328 CK_Yonah, 2329 //@} 2330 2331 /// \name Netburst 2332 /// Netburst microarchitecture based processors. 2333 //@{ 2334 CK_Pentium4, 2335 CK_Pentium4M, 2336 CK_Prescott, 2337 CK_Nocona, 2338 //@} 2339 2340 /// \name Core 2341 /// Core microarchitecture based processors. 2342 //@{ 2343 CK_Core2, 2344 2345 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2346 /// codename which GCC no longer accepts as an option to -march, but Clang 2347 /// has some logic for recognizing it. 2348 // FIXME: Warn, deprecate, and potentially remove this. 2349 CK_Penryn, 2350 //@} 2351 2352 /// \name Atom 2353 /// Atom processors 2354 //@{ 2355 CK_Bonnell, 2356 CK_Silvermont, 2357 //@} 2358 2359 /// \name Nehalem 2360 /// Nehalem microarchitecture based processors. 2361 CK_Nehalem, 2362 2363 /// \name Westmere 2364 /// Westmere microarchitecture based processors. 2365 CK_Westmere, 2366 2367 /// \name Sandy Bridge 2368 /// Sandy Bridge microarchitecture based processors. 2369 CK_SandyBridge, 2370 2371 /// \name Ivy Bridge 2372 /// Ivy Bridge microarchitecture based processors. 2373 CK_IvyBridge, 2374 2375 /// \name Haswell 2376 /// Haswell microarchitecture based processors. 2377 CK_Haswell, 2378 2379 /// \name Broadwell 2380 /// Broadwell microarchitecture based processors. 2381 CK_Broadwell, 2382 2383 /// \name Skylake Client 2384 /// Skylake client microarchitecture based processors. 2385 CK_SkylakeClient, 2386 2387 /// \name Skylake Server 2388 /// Skylake server microarchitecture based processors. 2389 CK_SkylakeServer, 2390 2391 /// \name Cannonlake Client 2392 /// Cannonlake client microarchitecture based processors. 2393 CK_Cannonlake, 2394 2395 /// \name Knights Landing 2396 /// Knights Landing processor. 2397 CK_KNL, 2398 2399 /// \name Lakemont 2400 /// Lakemont microarchitecture based processors. 2401 CK_Lakemont, 2402 2403 /// \name K6 2404 /// K6 architecture processors. 2405 //@{ 2406 CK_K6, 2407 CK_K6_2, 2408 CK_K6_3, 2409 //@} 2410 2411 /// \name K7 2412 /// K7 architecture processors. 2413 //@{ 2414 CK_Athlon, 2415 CK_AthlonThunderbird, 2416 CK_Athlon4, 2417 CK_AthlonXP, 2418 CK_AthlonMP, 2419 //@} 2420 2421 /// \name K8 2422 /// K8 architecture processors. 2423 //@{ 2424 CK_Athlon64, 2425 CK_Athlon64SSE3, 2426 CK_AthlonFX, 2427 CK_K8, 2428 CK_K8SSE3, 2429 CK_Opteron, 2430 CK_OpteronSSE3, 2431 CK_AMDFAM10, 2432 //@} 2433 2434 /// \name Bobcat 2435 /// Bobcat architecture processors. 2436 //@{ 2437 CK_BTVER1, 2438 CK_BTVER2, 2439 //@} 2440 2441 /// \name Bulldozer 2442 /// Bulldozer architecture processors. 2443 //@{ 2444 CK_BDVER1, 2445 CK_BDVER2, 2446 CK_BDVER3, 2447 CK_BDVER4, 2448 //@} 2449 2450 /// This specification is deprecated and will be removed in the future. 2451 /// Users should prefer \see CK_K8. 2452 // FIXME: Warn on this when the CPU is set to it. 2453 //@{ 2454 CK_x86_64, 2455 //@} 2456 2457 /// \name Geode 2458 /// Geode processors. 2459 //@{ 2460 CK_Geode 2461 //@} 2462 } CPU = CK_Generic; 2463 2464 CPUKind getCPUKind(StringRef CPU) const { 2465 return llvm::StringSwitch<CPUKind>(CPU) 2466 .Case("i386", CK_i386) 2467 .Case("i486", CK_i486) 2468 .Case("winchip-c6", CK_WinChipC6) 2469 .Case("winchip2", CK_WinChip2) 2470 .Case("c3", CK_C3) 2471 .Case("i586", CK_i586) 2472 .Case("pentium", CK_Pentium) 2473 .Case("pentium-mmx", CK_PentiumMMX) 2474 .Case("i686", CK_i686) 2475 .Case("pentiumpro", CK_PentiumPro) 2476 .Case("pentium2", CK_Pentium2) 2477 .Case("pentium3", CK_Pentium3) 2478 .Case("pentium3m", CK_Pentium3M) 2479 .Case("pentium-m", CK_PentiumM) 2480 .Case("c3-2", CK_C3_2) 2481 .Case("yonah", CK_Yonah) 2482 .Case("pentium4", CK_Pentium4) 2483 .Case("pentium4m", CK_Pentium4M) 2484 .Case("prescott", CK_Prescott) 2485 .Case("nocona", CK_Nocona) 2486 .Case("core2", CK_Core2) 2487 .Case("penryn", CK_Penryn) 2488 .Case("bonnell", CK_Bonnell) 2489 .Case("atom", CK_Bonnell) // Legacy name. 2490 .Case("silvermont", CK_Silvermont) 2491 .Case("slm", CK_Silvermont) // Legacy name. 2492 .Case("nehalem", CK_Nehalem) 2493 .Case("corei7", CK_Nehalem) // Legacy name. 2494 .Case("westmere", CK_Westmere) 2495 .Case("sandybridge", CK_SandyBridge) 2496 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2497 .Case("ivybridge", CK_IvyBridge) 2498 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2499 .Case("haswell", CK_Haswell) 2500 .Case("core-avx2", CK_Haswell) // Legacy name. 2501 .Case("broadwell", CK_Broadwell) 2502 .Case("skylake", CK_SkylakeClient) 2503 .Case("skylake-avx512", CK_SkylakeServer) 2504 .Case("skx", CK_SkylakeServer) // Legacy name. 2505 .Case("cannonlake", CK_Cannonlake) 2506 .Case("knl", CK_KNL) 2507 .Case("lakemont", CK_Lakemont) 2508 .Case("k6", CK_K6) 2509 .Case("k6-2", CK_K6_2) 2510 .Case("k6-3", CK_K6_3) 2511 .Case("athlon", CK_Athlon) 2512 .Case("athlon-tbird", CK_AthlonThunderbird) 2513 .Case("athlon-4", CK_Athlon4) 2514 .Case("athlon-xp", CK_AthlonXP) 2515 .Case("athlon-mp", CK_AthlonMP) 2516 .Case("athlon64", CK_Athlon64) 2517 .Case("athlon64-sse3", CK_Athlon64SSE3) 2518 .Case("athlon-fx", CK_AthlonFX) 2519 .Case("k8", CK_K8) 2520 .Case("k8-sse3", CK_K8SSE3) 2521 .Case("opteron", CK_Opteron) 2522 .Case("opteron-sse3", CK_OpteronSSE3) 2523 .Case("barcelona", CK_AMDFAM10) 2524 .Case("amdfam10", CK_AMDFAM10) 2525 .Case("btver1", CK_BTVER1) 2526 .Case("btver2", CK_BTVER2) 2527 .Case("bdver1", CK_BDVER1) 2528 .Case("bdver2", CK_BDVER2) 2529 .Case("bdver3", CK_BDVER3) 2530 .Case("bdver4", CK_BDVER4) 2531 .Case("x86-64", CK_x86_64) 2532 .Case("geode", CK_Geode) 2533 .Default(CK_Generic); 2534 } 2535 2536 enum FPMathKind { 2537 FP_Default, 2538 FP_SSE, 2539 FP_387 2540 } FPMath = FP_Default; 2541 2542 public: 2543 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2544 : TargetInfo(Triple) { 2545 BigEndian = false; 2546 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2547 } 2548 unsigned getFloatEvalMethod() const override { 2549 // X87 evaluates with 80 bits "long double" precision. 2550 return SSELevel == NoSSE ? 2 : 0; 2551 } 2552 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2553 return llvm::makeArrayRef(BuiltinInfo, 2554 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2555 } 2556 ArrayRef<const char *> getGCCRegNames() const override { 2557 return llvm::makeArrayRef(GCCRegNames); 2558 } 2559 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2560 return None; 2561 } 2562 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2563 return llvm::makeArrayRef(AddlRegNames); 2564 } 2565 bool validateCpuSupports(StringRef Name) const override; 2566 bool validateAsmConstraint(const char *&Name, 2567 TargetInfo::ConstraintInfo &info) const override; 2568 2569 bool validateGlobalRegisterVariable(StringRef RegName, 2570 unsigned RegSize, 2571 bool &HasSizeMismatch) const override { 2572 // esp and ebp are the only 32-bit registers the x86 backend can currently 2573 // handle. 2574 if (RegName.equals("esp") || RegName.equals("ebp")) { 2575 // Check that the register size is 32-bit. 2576 HasSizeMismatch = RegSize != 32; 2577 return true; 2578 } 2579 2580 return false; 2581 } 2582 2583 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2584 2585 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2586 2587 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2588 2589 std::string convertConstraint(const char *&Constraint) const override; 2590 const char *getClobbers() const override { 2591 return "~{dirflag},~{fpsr},~{flags}"; 2592 } 2593 void getTargetDefines(const LangOptions &Opts, 2594 MacroBuilder &Builder) const override; 2595 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2596 bool Enabled); 2597 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2598 bool Enabled); 2599 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2600 bool Enabled); 2601 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2602 StringRef Name, bool Enabled) const override { 2603 setFeatureEnabledImpl(Features, Name, Enabled); 2604 } 2605 // This exists purely to cut down on the number of virtual calls in 2606 // initFeatureMap which calls this repeatedly. 2607 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2608 StringRef Name, bool Enabled); 2609 bool 2610 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2611 StringRef CPU, 2612 const std::vector<std::string> &FeaturesVec) const override; 2613 bool hasFeature(StringRef Feature) const override; 2614 bool handleTargetFeatures(std::vector<std::string> &Features, 2615 DiagnosticsEngine &Diags) override; 2616 StringRef getABI() const override { 2617 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2618 return "avx512"; 2619 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2620 return "avx"; 2621 if (getTriple().getArch() == llvm::Triple::x86 && 2622 MMX3DNowLevel == NoMMX3DNow) 2623 return "no-mmx"; 2624 return ""; 2625 } 2626 bool setCPU(const std::string &Name) override { 2627 CPU = getCPUKind(Name); 2628 2629 // Perform any per-CPU checks necessary to determine if this CPU is 2630 // acceptable. 2631 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2632 // invalid without explaining *why*. 2633 switch (CPU) { 2634 case CK_Generic: 2635 // No processor selected! 2636 return false; 2637 2638 case CK_i386: 2639 case CK_i486: 2640 case CK_WinChipC6: 2641 case CK_WinChip2: 2642 case CK_C3: 2643 case CK_i586: 2644 case CK_Pentium: 2645 case CK_PentiumMMX: 2646 case CK_i686: 2647 case CK_PentiumPro: 2648 case CK_Pentium2: 2649 case CK_Pentium3: 2650 case CK_Pentium3M: 2651 case CK_PentiumM: 2652 case CK_Yonah: 2653 case CK_C3_2: 2654 case CK_Pentium4: 2655 case CK_Pentium4M: 2656 case CK_Lakemont: 2657 case CK_Prescott: 2658 case CK_K6: 2659 case CK_K6_2: 2660 case CK_K6_3: 2661 case CK_Athlon: 2662 case CK_AthlonThunderbird: 2663 case CK_Athlon4: 2664 case CK_AthlonXP: 2665 case CK_AthlonMP: 2666 case CK_Geode: 2667 // Only accept certain architectures when compiling in 32-bit mode. 2668 if (getTriple().getArch() != llvm::Triple::x86) 2669 return false; 2670 2671 // Fallthrough 2672 case CK_Nocona: 2673 case CK_Core2: 2674 case CK_Penryn: 2675 case CK_Bonnell: 2676 case CK_Silvermont: 2677 case CK_Nehalem: 2678 case CK_Westmere: 2679 case CK_SandyBridge: 2680 case CK_IvyBridge: 2681 case CK_Haswell: 2682 case CK_Broadwell: 2683 case CK_SkylakeClient: 2684 case CK_SkylakeServer: 2685 case CK_Cannonlake: 2686 case CK_KNL: 2687 case CK_Athlon64: 2688 case CK_Athlon64SSE3: 2689 case CK_AthlonFX: 2690 case CK_K8: 2691 case CK_K8SSE3: 2692 case CK_Opteron: 2693 case CK_OpteronSSE3: 2694 case CK_AMDFAM10: 2695 case CK_BTVER1: 2696 case CK_BTVER2: 2697 case CK_BDVER1: 2698 case CK_BDVER2: 2699 case CK_BDVER3: 2700 case CK_BDVER4: 2701 case CK_x86_64: 2702 return true; 2703 } 2704 llvm_unreachable("Unhandled CPU kind"); 2705 } 2706 2707 bool setFPMath(StringRef Name) override; 2708 2709 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2710 // Most of the non-ARM calling conventions are i386 conventions. 2711 switch (CC) { 2712 case CC_X86ThisCall: 2713 case CC_X86FastCall: 2714 case CC_X86StdCall: 2715 case CC_X86VectorCall: 2716 case CC_C: 2717 case CC_Swift: 2718 case CC_X86Pascal: 2719 case CC_IntelOclBicc: 2720 return CCCR_OK; 2721 default: 2722 return CCCR_Warning; 2723 } 2724 } 2725 2726 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2727 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2728 } 2729 2730 bool hasSjLjLowering() const override { 2731 return true; 2732 } 2733 2734 void setSupportedOpenCLOpts() override { 2735 getSupportedOpenCLOpts().setAll(); 2736 } 2737 }; 2738 2739 bool X86TargetInfo::setFPMath(StringRef Name) { 2740 if (Name == "387") { 2741 FPMath = FP_387; 2742 return true; 2743 } 2744 if (Name == "sse") { 2745 FPMath = FP_SSE; 2746 return true; 2747 } 2748 return false; 2749 } 2750 2751 bool X86TargetInfo::initFeatureMap( 2752 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2753 const std::vector<std::string> &FeaturesVec) const { 2754 // FIXME: This *really* should not be here. 2755 // X86_64 always has SSE2. 2756 if (getTriple().getArch() == llvm::Triple::x86_64) 2757 setFeatureEnabledImpl(Features, "sse2", true); 2758 2759 const CPUKind Kind = getCPUKind(CPU); 2760 2761 // Enable X87 for all X86 processors but Lakemont. 2762 if (Kind != CK_Lakemont) 2763 setFeatureEnabledImpl(Features, "x87", true); 2764 2765 switch (Kind) { 2766 case CK_Generic: 2767 case CK_i386: 2768 case CK_i486: 2769 case CK_i586: 2770 case CK_Pentium: 2771 case CK_i686: 2772 case CK_PentiumPro: 2773 case CK_Lakemont: 2774 break; 2775 case CK_PentiumMMX: 2776 case CK_Pentium2: 2777 case CK_K6: 2778 case CK_WinChipC6: 2779 setFeatureEnabledImpl(Features, "mmx", true); 2780 break; 2781 case CK_Pentium3: 2782 case CK_Pentium3M: 2783 case CK_C3_2: 2784 setFeatureEnabledImpl(Features, "sse", true); 2785 setFeatureEnabledImpl(Features, "fxsr", true); 2786 break; 2787 case CK_PentiumM: 2788 case CK_Pentium4: 2789 case CK_Pentium4M: 2790 case CK_x86_64: 2791 setFeatureEnabledImpl(Features, "sse2", true); 2792 setFeatureEnabledImpl(Features, "fxsr", true); 2793 break; 2794 case CK_Yonah: 2795 case CK_Prescott: 2796 case CK_Nocona: 2797 setFeatureEnabledImpl(Features, "sse3", true); 2798 setFeatureEnabledImpl(Features, "fxsr", true); 2799 setFeatureEnabledImpl(Features, "cx16", true); 2800 break; 2801 case CK_Core2: 2802 case CK_Bonnell: 2803 setFeatureEnabledImpl(Features, "ssse3", true); 2804 setFeatureEnabledImpl(Features, "fxsr", true); 2805 setFeatureEnabledImpl(Features, "cx16", true); 2806 break; 2807 case CK_Penryn: 2808 setFeatureEnabledImpl(Features, "sse4.1", true); 2809 setFeatureEnabledImpl(Features, "fxsr", true); 2810 setFeatureEnabledImpl(Features, "cx16", true); 2811 break; 2812 case CK_Cannonlake: 2813 setFeatureEnabledImpl(Features, "avx512ifma", true); 2814 setFeatureEnabledImpl(Features, "avx512vbmi", true); 2815 setFeatureEnabledImpl(Features, "sha", true); 2816 setFeatureEnabledImpl(Features, "umip", true); 2817 // FALLTHROUGH 2818 case CK_SkylakeServer: 2819 setFeatureEnabledImpl(Features, "avx512f", true); 2820 setFeatureEnabledImpl(Features, "avx512cd", true); 2821 setFeatureEnabledImpl(Features, "avx512dq", true); 2822 setFeatureEnabledImpl(Features, "avx512bw", true); 2823 setFeatureEnabledImpl(Features, "avx512vl", true); 2824 setFeatureEnabledImpl(Features, "pku", true); 2825 setFeatureEnabledImpl(Features, "pcommit", true); 2826 setFeatureEnabledImpl(Features, "clwb", true); 2827 // FALLTHROUGH 2828 case CK_SkylakeClient: 2829 setFeatureEnabledImpl(Features, "xsavec", true); 2830 setFeatureEnabledImpl(Features, "xsaves", true); 2831 setFeatureEnabledImpl(Features, "mpx", true); 2832 setFeatureEnabledImpl(Features, "sgx", true); 2833 setFeatureEnabledImpl(Features, "clflushopt", true); 2834 // FALLTHROUGH 2835 case CK_Broadwell: 2836 setFeatureEnabledImpl(Features, "rdseed", true); 2837 setFeatureEnabledImpl(Features, "adx", true); 2838 // FALLTHROUGH 2839 case CK_Haswell: 2840 setFeatureEnabledImpl(Features, "avx2", true); 2841 setFeatureEnabledImpl(Features, "lzcnt", true); 2842 setFeatureEnabledImpl(Features, "bmi", true); 2843 setFeatureEnabledImpl(Features, "bmi2", true); 2844 setFeatureEnabledImpl(Features, "rtm", true); 2845 setFeatureEnabledImpl(Features, "fma", true); 2846 setFeatureEnabledImpl(Features, "movbe", true); 2847 // FALLTHROUGH 2848 case CK_IvyBridge: 2849 setFeatureEnabledImpl(Features, "rdrnd", true); 2850 setFeatureEnabledImpl(Features, "f16c", true); 2851 setFeatureEnabledImpl(Features, "fsgsbase", true); 2852 // FALLTHROUGH 2853 case CK_SandyBridge: 2854 setFeatureEnabledImpl(Features, "avx", true); 2855 setFeatureEnabledImpl(Features, "xsave", true); 2856 setFeatureEnabledImpl(Features, "xsaveopt", true); 2857 // FALLTHROUGH 2858 case CK_Westmere: 2859 case CK_Silvermont: 2860 setFeatureEnabledImpl(Features, "aes", true); 2861 setFeatureEnabledImpl(Features, "pclmul", true); 2862 // FALLTHROUGH 2863 case CK_Nehalem: 2864 setFeatureEnabledImpl(Features, "sse4.2", true); 2865 setFeatureEnabledImpl(Features, "fxsr", true); 2866 setFeatureEnabledImpl(Features, "cx16", true); 2867 break; 2868 case CK_KNL: 2869 setFeatureEnabledImpl(Features, "avx512f", true); 2870 setFeatureEnabledImpl(Features, "avx512cd", true); 2871 setFeatureEnabledImpl(Features, "avx512er", true); 2872 setFeatureEnabledImpl(Features, "avx512pf", true); 2873 setFeatureEnabledImpl(Features, "prefetchwt1", true); 2874 setFeatureEnabledImpl(Features, "fxsr", true); 2875 setFeatureEnabledImpl(Features, "rdseed", true); 2876 setFeatureEnabledImpl(Features, "adx", true); 2877 setFeatureEnabledImpl(Features, "lzcnt", true); 2878 setFeatureEnabledImpl(Features, "bmi", true); 2879 setFeatureEnabledImpl(Features, "bmi2", true); 2880 setFeatureEnabledImpl(Features, "rtm", true); 2881 setFeatureEnabledImpl(Features, "fma", true); 2882 setFeatureEnabledImpl(Features, "rdrnd", true); 2883 setFeatureEnabledImpl(Features, "f16c", true); 2884 setFeatureEnabledImpl(Features, "fsgsbase", true); 2885 setFeatureEnabledImpl(Features, "aes", true); 2886 setFeatureEnabledImpl(Features, "pclmul", true); 2887 setFeatureEnabledImpl(Features, "cx16", true); 2888 setFeatureEnabledImpl(Features, "xsaveopt", true); 2889 setFeatureEnabledImpl(Features, "xsave", true); 2890 setFeatureEnabledImpl(Features, "movbe", true); 2891 break; 2892 case CK_K6_2: 2893 case CK_K6_3: 2894 case CK_WinChip2: 2895 case CK_C3: 2896 setFeatureEnabledImpl(Features, "3dnow", true); 2897 break; 2898 case CK_Athlon: 2899 case CK_AthlonThunderbird: 2900 case CK_Geode: 2901 setFeatureEnabledImpl(Features, "3dnowa", true); 2902 break; 2903 case CK_Athlon4: 2904 case CK_AthlonXP: 2905 case CK_AthlonMP: 2906 setFeatureEnabledImpl(Features, "sse", true); 2907 setFeatureEnabledImpl(Features, "3dnowa", true); 2908 setFeatureEnabledImpl(Features, "fxsr", true); 2909 break; 2910 case CK_K8: 2911 case CK_Opteron: 2912 case CK_Athlon64: 2913 case CK_AthlonFX: 2914 setFeatureEnabledImpl(Features, "sse2", true); 2915 setFeatureEnabledImpl(Features, "3dnowa", true); 2916 setFeatureEnabledImpl(Features, "fxsr", true); 2917 break; 2918 case CK_AMDFAM10: 2919 setFeatureEnabledImpl(Features, "sse4a", true); 2920 setFeatureEnabledImpl(Features, "lzcnt", true); 2921 setFeatureEnabledImpl(Features, "popcnt", true); 2922 // FALLTHROUGH 2923 case CK_K8SSE3: 2924 case CK_OpteronSSE3: 2925 case CK_Athlon64SSE3: 2926 setFeatureEnabledImpl(Features, "sse3", true); 2927 setFeatureEnabledImpl(Features, "3dnowa", true); 2928 setFeatureEnabledImpl(Features, "fxsr", true); 2929 break; 2930 case CK_BTVER2: 2931 setFeatureEnabledImpl(Features, "avx", true); 2932 setFeatureEnabledImpl(Features, "aes", true); 2933 setFeatureEnabledImpl(Features, "pclmul", true); 2934 setFeatureEnabledImpl(Features, "bmi", true); 2935 setFeatureEnabledImpl(Features, "f16c", true); 2936 setFeatureEnabledImpl(Features, "xsaveopt", true); 2937 // FALLTHROUGH 2938 case CK_BTVER1: 2939 setFeatureEnabledImpl(Features, "ssse3", true); 2940 setFeatureEnabledImpl(Features, "sse4a", true); 2941 setFeatureEnabledImpl(Features, "lzcnt", true); 2942 setFeatureEnabledImpl(Features, "popcnt", true); 2943 setFeatureEnabledImpl(Features, "prfchw", true); 2944 setFeatureEnabledImpl(Features, "cx16", true); 2945 setFeatureEnabledImpl(Features, "fxsr", true); 2946 break; 2947 case CK_BDVER4: 2948 setFeatureEnabledImpl(Features, "avx2", true); 2949 setFeatureEnabledImpl(Features, "bmi2", true); 2950 // FALLTHROUGH 2951 case CK_BDVER3: 2952 setFeatureEnabledImpl(Features, "fsgsbase", true); 2953 setFeatureEnabledImpl(Features, "xsaveopt", true); 2954 // FALLTHROUGH 2955 case CK_BDVER2: 2956 setFeatureEnabledImpl(Features, "bmi", true); 2957 setFeatureEnabledImpl(Features, "fma", true); 2958 setFeatureEnabledImpl(Features, "f16c", true); 2959 setFeatureEnabledImpl(Features, "tbm", true); 2960 // FALLTHROUGH 2961 case CK_BDVER1: 2962 // xop implies avx, sse4a and fma4. 2963 setFeatureEnabledImpl(Features, "xop", true); 2964 setFeatureEnabledImpl(Features, "lzcnt", true); 2965 setFeatureEnabledImpl(Features, "aes", true); 2966 setFeatureEnabledImpl(Features, "pclmul", true); 2967 setFeatureEnabledImpl(Features, "prfchw", true); 2968 setFeatureEnabledImpl(Features, "cx16", true); 2969 setFeatureEnabledImpl(Features, "fxsr", true); 2970 setFeatureEnabledImpl(Features, "xsave", true); 2971 break; 2972 } 2973 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 2974 return false; 2975 2976 // Can't do this earlier because we need to be able to explicitly enable 2977 // or disable these features and the things that they depend upon. 2978 2979 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2980 auto I = Features.find("sse4.2"); 2981 if (I != Features.end() && I->getValue() && 2982 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 2983 FeaturesVec.end()) 2984 Features["popcnt"] = true; 2985 2986 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2987 I = Features.find("3dnow"); 2988 if (I != Features.end() && I->getValue() && 2989 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 2990 FeaturesVec.end()) 2991 Features["prfchw"] = true; 2992 2993 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2994 // then enable MMX. 2995 I = Features.find("sse"); 2996 if (I != Features.end() && I->getValue() && 2997 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 2998 FeaturesVec.end()) 2999 Features["mmx"] = true; 3000 3001 return true; 3002 } 3003 3004 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3005 X86SSEEnum Level, bool Enabled) { 3006 if (Enabled) { 3007 switch (Level) { 3008 case AVX512F: 3009 Features["avx512f"] = true; 3010 case AVX2: 3011 Features["avx2"] = true; 3012 case AVX: 3013 Features["avx"] = true; 3014 Features["xsave"] = true; 3015 case SSE42: 3016 Features["sse4.2"] = true; 3017 case SSE41: 3018 Features["sse4.1"] = true; 3019 case SSSE3: 3020 Features["ssse3"] = true; 3021 case SSE3: 3022 Features["sse3"] = true; 3023 case SSE2: 3024 Features["sse2"] = true; 3025 case SSE1: 3026 Features["sse"] = true; 3027 case NoSSE: 3028 break; 3029 } 3030 return; 3031 } 3032 3033 switch (Level) { 3034 case NoSSE: 3035 case SSE1: 3036 Features["sse"] = false; 3037 case SSE2: 3038 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3039 Features["sha"] = false; 3040 case SSE3: 3041 Features["sse3"] = false; 3042 setXOPLevel(Features, NoXOP, false); 3043 case SSSE3: 3044 Features["ssse3"] = false; 3045 case SSE41: 3046 Features["sse4.1"] = false; 3047 case SSE42: 3048 Features["sse4.2"] = false; 3049 case AVX: 3050 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3051 Features["xsaveopt"] = false; 3052 setXOPLevel(Features, FMA4, false); 3053 case AVX2: 3054 Features["avx2"] = false; 3055 case AVX512F: 3056 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3057 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3058 Features["avx512vl"] = Features["avx512vbmi"] = 3059 Features["avx512ifma"] = false; 3060 } 3061 } 3062 3063 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3064 MMX3DNowEnum Level, bool Enabled) { 3065 if (Enabled) { 3066 switch (Level) { 3067 case AMD3DNowAthlon: 3068 Features["3dnowa"] = true; 3069 case AMD3DNow: 3070 Features["3dnow"] = true; 3071 case MMX: 3072 Features["mmx"] = true; 3073 case NoMMX3DNow: 3074 break; 3075 } 3076 return; 3077 } 3078 3079 switch (Level) { 3080 case NoMMX3DNow: 3081 case MMX: 3082 Features["mmx"] = false; 3083 case AMD3DNow: 3084 Features["3dnow"] = false; 3085 case AMD3DNowAthlon: 3086 Features["3dnowa"] = false; 3087 } 3088 } 3089 3090 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3091 bool Enabled) { 3092 if (Enabled) { 3093 switch (Level) { 3094 case XOP: 3095 Features["xop"] = true; 3096 case FMA4: 3097 Features["fma4"] = true; 3098 setSSELevel(Features, AVX, true); 3099 case SSE4A: 3100 Features["sse4a"] = true; 3101 setSSELevel(Features, SSE3, true); 3102 case NoXOP: 3103 break; 3104 } 3105 return; 3106 } 3107 3108 switch (Level) { 3109 case NoXOP: 3110 case SSE4A: 3111 Features["sse4a"] = false; 3112 case FMA4: 3113 Features["fma4"] = false; 3114 case XOP: 3115 Features["xop"] = false; 3116 } 3117 } 3118 3119 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3120 StringRef Name, bool Enabled) { 3121 // This is a bit of a hack to deal with the sse4 target feature when used 3122 // as part of the target attribute. We handle sse4 correctly everywhere 3123 // else. See below for more information on how we handle the sse4 options. 3124 if (Name != "sse4") 3125 Features[Name] = Enabled; 3126 3127 if (Name == "mmx") { 3128 setMMXLevel(Features, MMX, Enabled); 3129 } else if (Name == "sse") { 3130 setSSELevel(Features, SSE1, Enabled); 3131 } else if (Name == "sse2") { 3132 setSSELevel(Features, SSE2, Enabled); 3133 } else if (Name == "sse3") { 3134 setSSELevel(Features, SSE3, Enabled); 3135 } else if (Name == "ssse3") { 3136 setSSELevel(Features, SSSE3, Enabled); 3137 } else if (Name == "sse4.2") { 3138 setSSELevel(Features, SSE42, Enabled); 3139 } else if (Name == "sse4.1") { 3140 setSSELevel(Features, SSE41, Enabled); 3141 } else if (Name == "3dnow") { 3142 setMMXLevel(Features, AMD3DNow, Enabled); 3143 } else if (Name == "3dnowa") { 3144 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3145 } else if (Name == "aes") { 3146 if (Enabled) 3147 setSSELevel(Features, SSE2, Enabled); 3148 } else if (Name == "pclmul") { 3149 if (Enabled) 3150 setSSELevel(Features, SSE2, Enabled); 3151 } else if (Name == "avx") { 3152 setSSELevel(Features, AVX, Enabled); 3153 } else if (Name == "avx2") { 3154 setSSELevel(Features, AVX2, Enabled); 3155 } else if (Name == "avx512f") { 3156 setSSELevel(Features, AVX512F, Enabled); 3157 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3158 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3159 Name == "avx512vbmi" || Name == "avx512ifma") { 3160 if (Enabled) 3161 setSSELevel(Features, AVX512F, Enabled); 3162 } else if (Name == "fma") { 3163 if (Enabled) 3164 setSSELevel(Features, AVX, Enabled); 3165 } else if (Name == "fma4") { 3166 setXOPLevel(Features, FMA4, Enabled); 3167 } else if (Name == "xop") { 3168 setXOPLevel(Features, XOP, Enabled); 3169 } else if (Name == "sse4a") { 3170 setXOPLevel(Features, SSE4A, Enabled); 3171 } else if (Name == "f16c") { 3172 if (Enabled) 3173 setSSELevel(Features, AVX, Enabled); 3174 } else if (Name == "sha") { 3175 if (Enabled) 3176 setSSELevel(Features, SSE2, Enabled); 3177 } else if (Name == "sse4") { 3178 // We can get here via the __target__ attribute since that's not controlled 3179 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3180 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3181 // disabled. 3182 if (Enabled) 3183 setSSELevel(Features, SSE42, Enabled); 3184 else 3185 setSSELevel(Features, SSE41, Enabled); 3186 } else if (Name == "xsave") { 3187 if (!Enabled) 3188 Features["xsaveopt"] = false; 3189 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3190 if (Enabled) 3191 Features["xsave"] = true; 3192 } 3193 } 3194 3195 /// handleTargetFeatures - Perform initialization based on the user 3196 /// configured set of features. 3197 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3198 DiagnosticsEngine &Diags) { 3199 for (const auto &Feature : Features) { 3200 if (Feature[0] != '+') 3201 continue; 3202 3203 if (Feature == "+aes") { 3204 HasAES = true; 3205 } else if (Feature == "+pclmul") { 3206 HasPCLMUL = true; 3207 } else if (Feature == "+lzcnt") { 3208 HasLZCNT = true; 3209 } else if (Feature == "+rdrnd") { 3210 HasRDRND = true; 3211 } else if (Feature == "+fsgsbase") { 3212 HasFSGSBASE = true; 3213 } else if (Feature == "+bmi") { 3214 HasBMI = true; 3215 } else if (Feature == "+bmi2") { 3216 HasBMI2 = true; 3217 } else if (Feature == "+popcnt") { 3218 HasPOPCNT = true; 3219 } else if (Feature == "+rtm") { 3220 HasRTM = true; 3221 } else if (Feature == "+prfchw") { 3222 HasPRFCHW = true; 3223 } else if (Feature == "+rdseed") { 3224 HasRDSEED = true; 3225 } else if (Feature == "+adx") { 3226 HasADX = true; 3227 } else if (Feature == "+tbm") { 3228 HasTBM = true; 3229 } else if (Feature == "+fma") { 3230 HasFMA = true; 3231 } else if (Feature == "+f16c") { 3232 HasF16C = true; 3233 } else if (Feature == "+avx512cd") { 3234 HasAVX512CD = true; 3235 } else if (Feature == "+avx512er") { 3236 HasAVX512ER = true; 3237 } else if (Feature == "+avx512pf") { 3238 HasAVX512PF = true; 3239 } else if (Feature == "+avx512dq") { 3240 HasAVX512DQ = true; 3241 } else if (Feature == "+avx512bw") { 3242 HasAVX512BW = true; 3243 } else if (Feature == "+avx512vl") { 3244 HasAVX512VL = true; 3245 } else if (Feature == "+avx512vbmi") { 3246 HasAVX512VBMI = true; 3247 } else if (Feature == "+avx512ifma") { 3248 HasAVX512IFMA = true; 3249 } else if (Feature == "+sha") { 3250 HasSHA = true; 3251 } else if (Feature == "+mpx") { 3252 HasMPX = true; 3253 } else if (Feature == "+movbe") { 3254 HasMOVBE = true; 3255 } else if (Feature == "+sgx") { 3256 HasSGX = true; 3257 } else if (Feature == "+cx16") { 3258 HasCX16 = true; 3259 } else if (Feature == "+fxsr") { 3260 HasFXSR = true; 3261 } else if (Feature == "+xsave") { 3262 HasXSAVE = true; 3263 } else if (Feature == "+xsaveopt") { 3264 HasXSAVEOPT = true; 3265 } else if (Feature == "+xsavec") { 3266 HasXSAVEC = true; 3267 } else if (Feature == "+xsaves") { 3268 HasXSAVES = true; 3269 } else if (Feature == "+pku") { 3270 HasPKU = true; 3271 } else if (Feature == "+clflushopt") { 3272 HasCLFLUSHOPT = true; 3273 } else if (Feature == "+pcommit") { 3274 HasPCOMMIT = true; 3275 } else if (Feature == "+clwb") { 3276 HasCLWB = true; 3277 } else if (Feature == "+umip") { 3278 HasUMIP = true; 3279 } else if (Feature == "+prefetchwt1") { 3280 HasPREFETCHWT1 = true; 3281 } 3282 3283 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3284 .Case("+avx512f", AVX512F) 3285 .Case("+avx2", AVX2) 3286 .Case("+avx", AVX) 3287 .Case("+sse4.2", SSE42) 3288 .Case("+sse4.1", SSE41) 3289 .Case("+ssse3", SSSE3) 3290 .Case("+sse3", SSE3) 3291 .Case("+sse2", SSE2) 3292 .Case("+sse", SSE1) 3293 .Default(NoSSE); 3294 SSELevel = std::max(SSELevel, Level); 3295 3296 MMX3DNowEnum ThreeDNowLevel = 3297 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3298 .Case("+3dnowa", AMD3DNowAthlon) 3299 .Case("+3dnow", AMD3DNow) 3300 .Case("+mmx", MMX) 3301 .Default(NoMMX3DNow); 3302 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3303 3304 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3305 .Case("+xop", XOP) 3306 .Case("+fma4", FMA4) 3307 .Case("+sse4a", SSE4A) 3308 .Default(NoXOP); 3309 XOPLevel = std::max(XOPLevel, XLevel); 3310 } 3311 3312 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3313 // matches the selected sse level. 3314 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3315 (FPMath == FP_387 && SSELevel >= SSE1)) { 3316 Diags.Report(diag::err_target_unsupported_fpmath) << 3317 (FPMath == FP_SSE ? "sse" : "387"); 3318 return false; 3319 } 3320 3321 SimdDefaultAlign = 3322 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3323 return true; 3324 } 3325 3326 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3327 /// definitions for this particular subtarget. 3328 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3329 MacroBuilder &Builder) const { 3330 // Target identification. 3331 if (getTriple().getArch() == llvm::Triple::x86_64) { 3332 Builder.defineMacro("__amd64__"); 3333 Builder.defineMacro("__amd64"); 3334 Builder.defineMacro("__x86_64"); 3335 Builder.defineMacro("__x86_64__"); 3336 if (getTriple().getArchName() == "x86_64h") { 3337 Builder.defineMacro("__x86_64h"); 3338 Builder.defineMacro("__x86_64h__"); 3339 } 3340 } else { 3341 DefineStd(Builder, "i386", Opts); 3342 } 3343 3344 // Subtarget options. 3345 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3346 // truly should be based on -mtune options. 3347 switch (CPU) { 3348 case CK_Generic: 3349 break; 3350 case CK_i386: 3351 // The rest are coming from the i386 define above. 3352 Builder.defineMacro("__tune_i386__"); 3353 break; 3354 case CK_i486: 3355 case CK_WinChipC6: 3356 case CK_WinChip2: 3357 case CK_C3: 3358 defineCPUMacros(Builder, "i486"); 3359 break; 3360 case CK_PentiumMMX: 3361 Builder.defineMacro("__pentium_mmx__"); 3362 Builder.defineMacro("__tune_pentium_mmx__"); 3363 // Fallthrough 3364 case CK_i586: 3365 case CK_Pentium: 3366 defineCPUMacros(Builder, "i586"); 3367 defineCPUMacros(Builder, "pentium"); 3368 break; 3369 case CK_Pentium3: 3370 case CK_Pentium3M: 3371 case CK_PentiumM: 3372 Builder.defineMacro("__tune_pentium3__"); 3373 // Fallthrough 3374 case CK_Pentium2: 3375 case CK_C3_2: 3376 Builder.defineMacro("__tune_pentium2__"); 3377 // Fallthrough 3378 case CK_PentiumPro: 3379 Builder.defineMacro("__tune_i686__"); 3380 Builder.defineMacro("__tune_pentiumpro__"); 3381 // Fallthrough 3382 case CK_i686: 3383 Builder.defineMacro("__i686"); 3384 Builder.defineMacro("__i686__"); 3385 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3386 Builder.defineMacro("__pentiumpro"); 3387 Builder.defineMacro("__pentiumpro__"); 3388 break; 3389 case CK_Pentium4: 3390 case CK_Pentium4M: 3391 defineCPUMacros(Builder, "pentium4"); 3392 break; 3393 case CK_Yonah: 3394 case CK_Prescott: 3395 case CK_Nocona: 3396 defineCPUMacros(Builder, "nocona"); 3397 break; 3398 case CK_Core2: 3399 case CK_Penryn: 3400 defineCPUMacros(Builder, "core2"); 3401 break; 3402 case CK_Bonnell: 3403 defineCPUMacros(Builder, "atom"); 3404 break; 3405 case CK_Silvermont: 3406 defineCPUMacros(Builder, "slm"); 3407 break; 3408 case CK_Nehalem: 3409 case CK_Westmere: 3410 case CK_SandyBridge: 3411 case CK_IvyBridge: 3412 case CK_Haswell: 3413 case CK_Broadwell: 3414 case CK_SkylakeClient: 3415 // FIXME: Historically, we defined this legacy name, it would be nice to 3416 // remove it at some point. We've never exposed fine-grained names for 3417 // recent primary x86 CPUs, and we should keep it that way. 3418 defineCPUMacros(Builder, "corei7"); 3419 break; 3420 case CK_SkylakeServer: 3421 defineCPUMacros(Builder, "skx"); 3422 break; 3423 case CK_Cannonlake: 3424 break; 3425 case CK_KNL: 3426 defineCPUMacros(Builder, "knl"); 3427 break; 3428 case CK_Lakemont: 3429 Builder.defineMacro("__tune_lakemont__"); 3430 break; 3431 case CK_K6_2: 3432 Builder.defineMacro("__k6_2__"); 3433 Builder.defineMacro("__tune_k6_2__"); 3434 // Fallthrough 3435 case CK_K6_3: 3436 if (CPU != CK_K6_2) { // In case of fallthrough 3437 // FIXME: GCC may be enabling these in cases where some other k6 3438 // architecture is specified but -m3dnow is explicitly provided. The 3439 // exact semantics need to be determined and emulated here. 3440 Builder.defineMacro("__k6_3__"); 3441 Builder.defineMacro("__tune_k6_3__"); 3442 } 3443 // Fallthrough 3444 case CK_K6: 3445 defineCPUMacros(Builder, "k6"); 3446 break; 3447 case CK_Athlon: 3448 case CK_AthlonThunderbird: 3449 case CK_Athlon4: 3450 case CK_AthlonXP: 3451 case CK_AthlonMP: 3452 defineCPUMacros(Builder, "athlon"); 3453 if (SSELevel != NoSSE) { 3454 Builder.defineMacro("__athlon_sse__"); 3455 Builder.defineMacro("__tune_athlon_sse__"); 3456 } 3457 break; 3458 case CK_K8: 3459 case CK_K8SSE3: 3460 case CK_x86_64: 3461 case CK_Opteron: 3462 case CK_OpteronSSE3: 3463 case CK_Athlon64: 3464 case CK_Athlon64SSE3: 3465 case CK_AthlonFX: 3466 defineCPUMacros(Builder, "k8"); 3467 break; 3468 case CK_AMDFAM10: 3469 defineCPUMacros(Builder, "amdfam10"); 3470 break; 3471 case CK_BTVER1: 3472 defineCPUMacros(Builder, "btver1"); 3473 break; 3474 case CK_BTVER2: 3475 defineCPUMacros(Builder, "btver2"); 3476 break; 3477 case CK_BDVER1: 3478 defineCPUMacros(Builder, "bdver1"); 3479 break; 3480 case CK_BDVER2: 3481 defineCPUMacros(Builder, "bdver2"); 3482 break; 3483 case CK_BDVER3: 3484 defineCPUMacros(Builder, "bdver3"); 3485 break; 3486 case CK_BDVER4: 3487 defineCPUMacros(Builder, "bdver4"); 3488 break; 3489 case CK_Geode: 3490 defineCPUMacros(Builder, "geode"); 3491 break; 3492 } 3493 3494 // Target properties. 3495 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3496 3497 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3498 // functions in glibc header files that use FP Stack inline asm which the 3499 // backend can't deal with (PR879). 3500 Builder.defineMacro("__NO_MATH_INLINES"); 3501 3502 if (HasAES) 3503 Builder.defineMacro("__AES__"); 3504 3505 if (HasPCLMUL) 3506 Builder.defineMacro("__PCLMUL__"); 3507 3508 if (HasLZCNT) 3509 Builder.defineMacro("__LZCNT__"); 3510 3511 if (HasRDRND) 3512 Builder.defineMacro("__RDRND__"); 3513 3514 if (HasFSGSBASE) 3515 Builder.defineMacro("__FSGSBASE__"); 3516 3517 if (HasBMI) 3518 Builder.defineMacro("__BMI__"); 3519 3520 if (HasBMI2) 3521 Builder.defineMacro("__BMI2__"); 3522 3523 if (HasPOPCNT) 3524 Builder.defineMacro("__POPCNT__"); 3525 3526 if (HasRTM) 3527 Builder.defineMacro("__RTM__"); 3528 3529 if (HasPRFCHW) 3530 Builder.defineMacro("__PRFCHW__"); 3531 3532 if (HasRDSEED) 3533 Builder.defineMacro("__RDSEED__"); 3534 3535 if (HasADX) 3536 Builder.defineMacro("__ADX__"); 3537 3538 if (HasTBM) 3539 Builder.defineMacro("__TBM__"); 3540 3541 switch (XOPLevel) { 3542 case XOP: 3543 Builder.defineMacro("__XOP__"); 3544 case FMA4: 3545 Builder.defineMacro("__FMA4__"); 3546 case SSE4A: 3547 Builder.defineMacro("__SSE4A__"); 3548 case NoXOP: 3549 break; 3550 } 3551 3552 if (HasFMA) 3553 Builder.defineMacro("__FMA__"); 3554 3555 if (HasF16C) 3556 Builder.defineMacro("__F16C__"); 3557 3558 if (HasAVX512CD) 3559 Builder.defineMacro("__AVX512CD__"); 3560 if (HasAVX512ER) 3561 Builder.defineMacro("__AVX512ER__"); 3562 if (HasAVX512PF) 3563 Builder.defineMacro("__AVX512PF__"); 3564 if (HasAVX512DQ) 3565 Builder.defineMacro("__AVX512DQ__"); 3566 if (HasAVX512BW) 3567 Builder.defineMacro("__AVX512BW__"); 3568 if (HasAVX512VL) 3569 Builder.defineMacro("__AVX512VL__"); 3570 if (HasAVX512VBMI) 3571 Builder.defineMacro("__AVX512VBMI__"); 3572 if (HasAVX512IFMA) 3573 Builder.defineMacro("__AVX512IFMA__"); 3574 3575 if (HasSHA) 3576 Builder.defineMacro("__SHA__"); 3577 3578 if (HasFXSR) 3579 Builder.defineMacro("__FXSR__"); 3580 if (HasXSAVE) 3581 Builder.defineMacro("__XSAVE__"); 3582 if (HasXSAVEOPT) 3583 Builder.defineMacro("__XSAVEOPT__"); 3584 if (HasXSAVEC) 3585 Builder.defineMacro("__XSAVEC__"); 3586 if (HasXSAVES) 3587 Builder.defineMacro("__XSAVES__"); 3588 if (HasPKU) 3589 Builder.defineMacro("__PKU__"); 3590 if (HasCX16) 3591 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3592 3593 // Each case falls through to the previous one here. 3594 switch (SSELevel) { 3595 case AVX512F: 3596 Builder.defineMacro("__AVX512F__"); 3597 case AVX2: 3598 Builder.defineMacro("__AVX2__"); 3599 case AVX: 3600 Builder.defineMacro("__AVX__"); 3601 case SSE42: 3602 Builder.defineMacro("__SSE4_2__"); 3603 case SSE41: 3604 Builder.defineMacro("__SSE4_1__"); 3605 case SSSE3: 3606 Builder.defineMacro("__SSSE3__"); 3607 case SSE3: 3608 Builder.defineMacro("__SSE3__"); 3609 case SSE2: 3610 Builder.defineMacro("__SSE2__"); 3611 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3612 case SSE1: 3613 Builder.defineMacro("__SSE__"); 3614 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3615 case NoSSE: 3616 break; 3617 } 3618 3619 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3620 switch (SSELevel) { 3621 case AVX512F: 3622 case AVX2: 3623 case AVX: 3624 case SSE42: 3625 case SSE41: 3626 case SSSE3: 3627 case SSE3: 3628 case SSE2: 3629 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3630 break; 3631 case SSE1: 3632 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3633 break; 3634 default: 3635 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3636 } 3637 } 3638 3639 // Each case falls through to the previous one here. 3640 switch (MMX3DNowLevel) { 3641 case AMD3DNowAthlon: 3642 Builder.defineMacro("__3dNOW_A__"); 3643 case AMD3DNow: 3644 Builder.defineMacro("__3dNOW__"); 3645 case MMX: 3646 Builder.defineMacro("__MMX__"); 3647 case NoMMX3DNow: 3648 break; 3649 } 3650 3651 if (CPU >= CK_i486) { 3652 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3653 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3654 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3655 } 3656 if (CPU >= CK_i586) 3657 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3658 } 3659 3660 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3661 return llvm::StringSwitch<bool>(Feature) 3662 .Case("aes", HasAES) 3663 .Case("avx", SSELevel >= AVX) 3664 .Case("avx2", SSELevel >= AVX2) 3665 .Case("avx512f", SSELevel >= AVX512F) 3666 .Case("avx512cd", HasAVX512CD) 3667 .Case("avx512er", HasAVX512ER) 3668 .Case("avx512pf", HasAVX512PF) 3669 .Case("avx512dq", HasAVX512DQ) 3670 .Case("avx512bw", HasAVX512BW) 3671 .Case("avx512vl", HasAVX512VL) 3672 .Case("avx512vbmi", HasAVX512VBMI) 3673 .Case("avx512ifma", HasAVX512IFMA) 3674 .Case("bmi", HasBMI) 3675 .Case("bmi2", HasBMI2) 3676 .Case("clflushopt", HasCLFLUSHOPT) 3677 .Case("clwb", HasCLWB) 3678 .Case("cx16", HasCX16) 3679 .Case("f16c", HasF16C) 3680 .Case("fma", HasFMA) 3681 .Case("fma4", XOPLevel >= FMA4) 3682 .Case("fsgsbase", HasFSGSBASE) 3683 .Case("fxsr", HasFXSR) 3684 .Case("lzcnt", HasLZCNT) 3685 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3686 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3687 .Case("mmx", MMX3DNowLevel >= MMX) 3688 .Case("movbe", HasMOVBE) 3689 .Case("mpx", HasMPX) 3690 .Case("pclmul", HasPCLMUL) 3691 .Case("pcommit", HasPCOMMIT) 3692 .Case("pku", HasPKU) 3693 .Case("popcnt", HasPOPCNT) 3694 .Case("prefetchwt1", HasPREFETCHWT1) 3695 .Case("prfchw", HasPRFCHW) 3696 .Case("rdrnd", HasRDRND) 3697 .Case("rdseed", HasRDSEED) 3698 .Case("rtm", HasRTM) 3699 .Case("sgx", HasSGX) 3700 .Case("sha", HasSHA) 3701 .Case("sse", SSELevel >= SSE1) 3702 .Case("sse2", SSELevel >= SSE2) 3703 .Case("sse3", SSELevel >= SSE3) 3704 .Case("ssse3", SSELevel >= SSSE3) 3705 .Case("sse4.1", SSELevel >= SSE41) 3706 .Case("sse4.2", SSELevel >= SSE42) 3707 .Case("sse4a", XOPLevel >= SSE4A) 3708 .Case("tbm", HasTBM) 3709 .Case("umip", HasUMIP) 3710 .Case("x86", true) 3711 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3712 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3713 .Case("xop", XOPLevel >= XOP) 3714 .Case("xsave", HasXSAVE) 3715 .Case("xsavec", HasXSAVEC) 3716 .Case("xsaves", HasXSAVES) 3717 .Case("xsaveopt", HasXSAVEOPT) 3718 .Default(false); 3719 } 3720 3721 // We can't use a generic validation scheme for the features accepted here 3722 // versus subtarget features accepted in the target attribute because the 3723 // bitfield structure that's initialized in the runtime only supports the 3724 // below currently rather than the full range of subtarget features. (See 3725 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3726 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3727 return llvm::StringSwitch<bool>(FeatureStr) 3728 .Case("cmov", true) 3729 .Case("mmx", true) 3730 .Case("popcnt", true) 3731 .Case("sse", true) 3732 .Case("sse2", true) 3733 .Case("sse3", true) 3734 .Case("sse4.1", true) 3735 .Case("sse4.2", true) 3736 .Case("avx", true) 3737 .Case("avx2", true) 3738 .Case("sse4a", true) 3739 .Case("fma4", true) 3740 .Case("xop", true) 3741 .Case("fma", true) 3742 .Case("avx512f", true) 3743 .Case("bmi", true) 3744 .Case("bmi2", true) 3745 .Default(false); 3746 } 3747 3748 bool 3749 X86TargetInfo::validateAsmConstraint(const char *&Name, 3750 TargetInfo::ConstraintInfo &Info) const { 3751 switch (*Name) { 3752 default: return false; 3753 // Constant constraints. 3754 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3755 // instructions. 3756 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3757 // x86_64 instructions. 3758 case 's': 3759 Info.setRequiresImmediate(); 3760 return true; 3761 case 'I': 3762 Info.setRequiresImmediate(0, 31); 3763 return true; 3764 case 'J': 3765 Info.setRequiresImmediate(0, 63); 3766 return true; 3767 case 'K': 3768 Info.setRequiresImmediate(-128, 127); 3769 return true; 3770 case 'L': 3771 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3772 return true; 3773 case 'M': 3774 Info.setRequiresImmediate(0, 3); 3775 return true; 3776 case 'N': 3777 Info.setRequiresImmediate(0, 255); 3778 return true; 3779 case 'O': 3780 Info.setRequiresImmediate(0, 127); 3781 return true; 3782 // Register constraints. 3783 case 'Y': // 'Y' is the first character for several 2-character constraints. 3784 // Shift the pointer to the second character of the constraint. 3785 Name++; 3786 switch (*Name) { 3787 default: 3788 return false; 3789 case '0': // First SSE register. 3790 case 't': // Any SSE register, when SSE2 is enabled. 3791 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3792 case 'm': // Any MMX register, when inter-unit moves enabled. 3793 Info.setAllowsRegister(); 3794 return true; 3795 } 3796 case 'f': // Any x87 floating point stack register. 3797 // Constraint 'f' cannot be used for output operands. 3798 if (Info.ConstraintStr[0] == '=') 3799 return false; 3800 Info.setAllowsRegister(); 3801 return true; 3802 case 'a': // eax. 3803 case 'b': // ebx. 3804 case 'c': // ecx. 3805 case 'd': // edx. 3806 case 'S': // esi. 3807 case 'D': // edi. 3808 case 'A': // edx:eax. 3809 case 't': // Top of floating point stack. 3810 case 'u': // Second from top of floating point stack. 3811 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3812 case 'y': // Any MMX register. 3813 case 'x': // Any SSE register. 3814 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3815 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3816 case 'l': // "Index" registers: any general register that can be used as an 3817 // index in a base+index memory access. 3818 Info.setAllowsRegister(); 3819 return true; 3820 // Floating point constant constraints. 3821 case 'C': // SSE floating point constant. 3822 case 'G': // x87 floating point constant. 3823 return true; 3824 } 3825 } 3826 3827 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3828 unsigned Size) const { 3829 // Strip off constraint modifiers. 3830 while (Constraint[0] == '=' || 3831 Constraint[0] == '+' || 3832 Constraint[0] == '&') 3833 Constraint = Constraint.substr(1); 3834 3835 return validateOperandSize(Constraint, Size); 3836 } 3837 3838 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3839 unsigned Size) const { 3840 return validateOperandSize(Constraint, Size); 3841 } 3842 3843 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3844 unsigned Size) const { 3845 switch (Constraint[0]) { 3846 default: break; 3847 case 'y': 3848 return Size <= 64; 3849 case 'f': 3850 case 't': 3851 case 'u': 3852 return Size <= 128; 3853 case 'x': 3854 if (SSELevel >= AVX512F) 3855 // 512-bit zmm registers can be used if target supports AVX512F. 3856 return Size <= 512U; 3857 else if (SSELevel >= AVX) 3858 // 256-bit ymm registers can be used if target supports AVX. 3859 return Size <= 256U; 3860 return Size <= 128U; 3861 case 'Y': 3862 // 'Y' is the first character for several 2-character constraints. 3863 switch (Constraint[1]) { 3864 default: break; 3865 case 'm': 3866 // 'Ym' is synonymous with 'y'. 3867 return Size <= 64; 3868 case 'i': 3869 case 't': 3870 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3871 if (SSELevel >= AVX512F) 3872 return Size <= 512U; 3873 else if (SSELevel >= AVX) 3874 return Size <= 256U; 3875 return SSELevel >= SSE2 && Size <= 128U; 3876 } 3877 3878 } 3879 3880 return true; 3881 } 3882 3883 std::string 3884 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3885 switch (*Constraint) { 3886 case 'a': return std::string("{ax}"); 3887 case 'b': return std::string("{bx}"); 3888 case 'c': return std::string("{cx}"); 3889 case 'd': return std::string("{dx}"); 3890 case 'S': return std::string("{si}"); 3891 case 'D': return std::string("{di}"); 3892 case 'p': // address 3893 return std::string("im"); 3894 case 't': // top of floating point stack. 3895 return std::string("{st}"); 3896 case 'u': // second from top of floating point stack. 3897 return std::string("{st(1)}"); // second from top of floating point stack. 3898 default: 3899 return std::string(1, *Constraint); 3900 } 3901 } 3902 3903 // X86-32 generic target 3904 class X86_32TargetInfo : public X86TargetInfo { 3905 public: 3906 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3907 : X86TargetInfo(Triple, Opts) { 3908 DoubleAlign = LongLongAlign = 32; 3909 LongDoubleWidth = 96; 3910 LongDoubleAlign = 32; 3911 SuitableAlign = 128; 3912 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 3913 SizeType = UnsignedInt; 3914 PtrDiffType = SignedInt; 3915 IntPtrType = SignedInt; 3916 RegParmMax = 3; 3917 3918 // Use fpret for all types. 3919 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3920 (1 << TargetInfo::Double) | 3921 (1 << TargetInfo::LongDouble)); 3922 3923 // x86-32 has atomics up to 8 bytes 3924 // FIXME: Check that we actually have cmpxchg8b before setting 3925 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3926 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3927 } 3928 BuiltinVaListKind getBuiltinVaListKind() const override { 3929 return TargetInfo::CharPtrBuiltinVaList; 3930 } 3931 3932 int getEHDataRegisterNumber(unsigned RegNo) const override { 3933 if (RegNo == 0) return 0; 3934 if (RegNo == 1) return 2; 3935 return -1; 3936 } 3937 bool validateOperandSize(StringRef Constraint, 3938 unsigned Size) const override { 3939 switch (Constraint[0]) { 3940 default: break; 3941 case 'R': 3942 case 'q': 3943 case 'Q': 3944 case 'a': 3945 case 'b': 3946 case 'c': 3947 case 'd': 3948 case 'S': 3949 case 'D': 3950 return Size <= 32; 3951 case 'A': 3952 return Size <= 64; 3953 } 3954 3955 return X86TargetInfo::validateOperandSize(Constraint, Size); 3956 } 3957 }; 3958 3959 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3960 public: 3961 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3962 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 3963 3964 unsigned getFloatEvalMethod() const override { 3965 unsigned Major, Minor, Micro; 3966 getTriple().getOSVersion(Major, Minor, Micro); 3967 // New NetBSD uses the default rounding mode. 3968 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3969 return X86_32TargetInfo::getFloatEvalMethod(); 3970 // NetBSD before 6.99.26 defaults to "double" rounding. 3971 return 1; 3972 } 3973 }; 3974 3975 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3976 public: 3977 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3978 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 3979 SizeType = UnsignedLong; 3980 IntPtrType = SignedLong; 3981 PtrDiffType = SignedLong; 3982 } 3983 }; 3984 3985 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3986 public: 3987 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3988 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 3989 SizeType = UnsignedLong; 3990 IntPtrType = SignedLong; 3991 PtrDiffType = SignedLong; 3992 } 3993 }; 3994 3995 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3996 public: 3997 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3998 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 3999 LongDoubleWidth = 128; 4000 LongDoubleAlign = 128; 4001 SuitableAlign = 128; 4002 MaxVectorAlign = 256; 4003 // The watchOS simulator uses the builtin bool type for Objective-C. 4004 llvm::Triple T = llvm::Triple(Triple); 4005 if (T.isWatchOS()) 4006 UseSignedCharForObjCBool = false; 4007 SizeType = UnsignedLong; 4008 IntPtrType = SignedLong; 4009 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4010 HasAlignMac68kSupport = true; 4011 } 4012 4013 bool handleTargetFeatures(std::vector<std::string> &Features, 4014 DiagnosticsEngine &Diags) override { 4015 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4016 Diags)) 4017 return false; 4018 // We now know the features we have: we can decide how to align vectors. 4019 MaxVectorAlign = 4020 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4021 return true; 4022 } 4023 }; 4024 4025 // x86-32 Windows target 4026 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4027 public: 4028 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4029 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4030 WCharType = UnsignedShort; 4031 DoubleAlign = LongLongAlign = 64; 4032 bool IsWinCOFF = 4033 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4034 resetDataLayout(IsWinCOFF 4035 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4036 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4037 } 4038 void getTargetDefines(const LangOptions &Opts, 4039 MacroBuilder &Builder) const override { 4040 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4041 } 4042 }; 4043 4044 // x86-32 Windows Visual Studio target 4045 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4046 public: 4047 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4048 const TargetOptions &Opts) 4049 : WindowsX86_32TargetInfo(Triple, Opts) { 4050 LongDoubleWidth = LongDoubleAlign = 64; 4051 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4052 } 4053 void getTargetDefines(const LangOptions &Opts, 4054 MacroBuilder &Builder) const override { 4055 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4056 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4057 // The value of the following reflects processor type. 4058 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4059 // We lost the original triple, so we use the default. 4060 Builder.defineMacro("_M_IX86", "600"); 4061 } 4062 }; 4063 4064 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4065 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4066 // supports __declspec natively under -fms-extensions, but we define a no-op 4067 // __declspec macro anyway for pre-processor compatibility. 4068 if (Opts.MicrosoftExt) 4069 Builder.defineMacro("__declspec", "__declspec"); 4070 else 4071 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4072 4073 if (!Opts.MicrosoftExt) { 4074 // Provide macros for all the calling convention keywords. Provide both 4075 // single and double underscore prefixed variants. These are available on 4076 // x64 as well as x86, even though they have no effect. 4077 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4078 for (const char *CC : CCs) { 4079 std::string GCCSpelling = "__attribute__((__"; 4080 GCCSpelling += CC; 4081 GCCSpelling += "__))"; 4082 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4083 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4084 } 4085 } 4086 } 4087 4088 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4089 Builder.defineMacro("__MSVCRT__"); 4090 Builder.defineMacro("__MINGW32__"); 4091 addCygMingDefines(Opts, Builder); 4092 } 4093 4094 // x86-32 MinGW target 4095 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4096 public: 4097 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4098 : WindowsX86_32TargetInfo(Triple, Opts) {} 4099 void getTargetDefines(const LangOptions &Opts, 4100 MacroBuilder &Builder) const override { 4101 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4102 DefineStd(Builder, "WIN32", Opts); 4103 DefineStd(Builder, "WINNT", Opts); 4104 Builder.defineMacro("_X86_"); 4105 addMinGWDefines(Opts, Builder); 4106 } 4107 }; 4108 4109 // x86-32 Cygwin target 4110 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4111 public: 4112 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4113 : X86_32TargetInfo(Triple, Opts) { 4114 WCharType = UnsignedShort; 4115 DoubleAlign = LongLongAlign = 64; 4116 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4117 } 4118 void getTargetDefines(const LangOptions &Opts, 4119 MacroBuilder &Builder) const override { 4120 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4121 Builder.defineMacro("_X86_"); 4122 Builder.defineMacro("__CYGWIN__"); 4123 Builder.defineMacro("__CYGWIN32__"); 4124 addCygMingDefines(Opts, Builder); 4125 DefineStd(Builder, "unix", Opts); 4126 if (Opts.CPlusPlus) 4127 Builder.defineMacro("_GNU_SOURCE"); 4128 } 4129 }; 4130 4131 // x86-32 Haiku target 4132 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4133 public: 4134 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4135 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4136 } 4137 void getTargetDefines(const LangOptions &Opts, 4138 MacroBuilder &Builder) const override { 4139 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4140 Builder.defineMacro("__INTEL__"); 4141 } 4142 }; 4143 4144 // X86-32 MCU target 4145 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4146 public: 4147 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4148 : X86_32TargetInfo(Triple, Opts) { 4149 LongDoubleWidth = 64; 4150 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4151 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4152 WIntType = UnsignedInt; 4153 } 4154 4155 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4156 // On MCU we support only C calling convention. 4157 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4158 } 4159 4160 void getTargetDefines(const LangOptions &Opts, 4161 MacroBuilder &Builder) const override { 4162 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4163 Builder.defineMacro("__iamcu"); 4164 Builder.defineMacro("__iamcu__"); 4165 } 4166 4167 bool allowsLargerPreferedTypeAlignment() const override { 4168 return false; 4169 } 4170 }; 4171 4172 // RTEMS Target 4173 template<typename Target> 4174 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4175 protected: 4176 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4177 MacroBuilder &Builder) const override { 4178 // RTEMS defines; list based off of gcc output 4179 4180 Builder.defineMacro("__rtems__"); 4181 Builder.defineMacro("__ELF__"); 4182 } 4183 4184 public: 4185 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4186 : OSTargetInfo<Target>(Triple, Opts) { 4187 switch (Triple.getArch()) { 4188 default: 4189 case llvm::Triple::x86: 4190 // this->MCountName = ".mcount"; 4191 break; 4192 case llvm::Triple::mips: 4193 case llvm::Triple::mipsel: 4194 case llvm::Triple::ppc: 4195 case llvm::Triple::ppc64: 4196 case llvm::Triple::ppc64le: 4197 // this->MCountName = "_mcount"; 4198 break; 4199 case llvm::Triple::arm: 4200 // this->MCountName = "__mcount"; 4201 break; 4202 } 4203 } 4204 }; 4205 4206 // x86-32 RTEMS target 4207 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4208 public: 4209 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4210 : X86_32TargetInfo(Triple, Opts) { 4211 SizeType = UnsignedLong; 4212 IntPtrType = SignedLong; 4213 PtrDiffType = SignedLong; 4214 } 4215 void getTargetDefines(const LangOptions &Opts, 4216 MacroBuilder &Builder) const override { 4217 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4218 Builder.defineMacro("__INTEL__"); 4219 Builder.defineMacro("__rtems__"); 4220 } 4221 }; 4222 4223 // x86-64 generic target 4224 class X86_64TargetInfo : public X86TargetInfo { 4225 public: 4226 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4227 : X86TargetInfo(Triple, Opts) { 4228 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4229 bool IsWinCOFF = 4230 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4231 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4232 LongDoubleWidth = 128; 4233 LongDoubleAlign = 128; 4234 LargeArrayMinWidth = 128; 4235 LargeArrayAlign = 128; 4236 SuitableAlign = 128; 4237 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4238 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4239 IntPtrType = IsX32 ? SignedInt : SignedLong; 4240 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4241 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4242 RegParmMax = 6; 4243 4244 // Pointers are 32-bit in x32. 4245 resetDataLayout(IsX32 4246 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4247 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4248 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4249 4250 // Use fpret only for long double. 4251 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4252 4253 // Use fp2ret for _Complex long double. 4254 ComplexLongDoubleUsesFP2Ret = true; 4255 4256 // Make __builtin_ms_va_list available. 4257 HasBuiltinMSVaList = true; 4258 4259 // x86-64 has atomics up to 16 bytes. 4260 MaxAtomicPromoteWidth = 128; 4261 MaxAtomicInlineWidth = 128; 4262 } 4263 BuiltinVaListKind getBuiltinVaListKind() const override { 4264 return TargetInfo::X86_64ABIBuiltinVaList; 4265 } 4266 4267 int getEHDataRegisterNumber(unsigned RegNo) const override { 4268 if (RegNo == 0) return 0; 4269 if (RegNo == 1) return 1; 4270 return -1; 4271 } 4272 4273 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4274 switch (CC) { 4275 case CC_C: 4276 case CC_Swift: 4277 case CC_X86VectorCall: 4278 case CC_IntelOclBicc: 4279 case CC_X86_64Win64: 4280 case CC_PreserveMost: 4281 case CC_PreserveAll: 4282 return CCCR_OK; 4283 default: 4284 return CCCR_Warning; 4285 } 4286 } 4287 4288 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4289 return CC_C; 4290 } 4291 4292 // for x32 we need it here explicitly 4293 bool hasInt128Type() const override { return true; } 4294 unsigned getUnwindWordWidth() const override { return 64; } 4295 unsigned getRegisterWidth() const override { return 64; } 4296 4297 bool validateGlobalRegisterVariable(StringRef RegName, 4298 unsigned RegSize, 4299 bool &HasSizeMismatch) const override { 4300 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4301 // handle. 4302 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4303 // Check that the register size is 64-bit. 4304 HasSizeMismatch = RegSize != 64; 4305 return true; 4306 } 4307 4308 // Check if the register is a 32-bit register the backend can handle. 4309 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4310 HasSizeMismatch); 4311 } 4312 }; 4313 4314 // x86-64 Windows target 4315 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4316 public: 4317 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4318 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4319 WCharType = UnsignedShort; 4320 LongWidth = LongAlign = 32; 4321 DoubleAlign = LongLongAlign = 64; 4322 IntMaxType = SignedLongLong; 4323 Int64Type = SignedLongLong; 4324 SizeType = UnsignedLongLong; 4325 PtrDiffType = SignedLongLong; 4326 IntPtrType = SignedLongLong; 4327 } 4328 4329 void getTargetDefines(const LangOptions &Opts, 4330 MacroBuilder &Builder) const override { 4331 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4332 Builder.defineMacro("_WIN64"); 4333 } 4334 4335 BuiltinVaListKind getBuiltinVaListKind() const override { 4336 return TargetInfo::CharPtrBuiltinVaList; 4337 } 4338 4339 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4340 switch (CC) { 4341 case CC_X86StdCall: 4342 case CC_X86ThisCall: 4343 case CC_X86FastCall: 4344 return CCCR_Ignore; 4345 case CC_C: 4346 case CC_X86VectorCall: 4347 case CC_IntelOclBicc: 4348 case CC_X86_64SysV: 4349 return CCCR_OK; 4350 default: 4351 return CCCR_Warning; 4352 } 4353 } 4354 }; 4355 4356 // x86-64 Windows Visual Studio target 4357 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4358 public: 4359 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4360 const TargetOptions &Opts) 4361 : WindowsX86_64TargetInfo(Triple, Opts) { 4362 LongDoubleWidth = LongDoubleAlign = 64; 4363 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4364 } 4365 void getTargetDefines(const LangOptions &Opts, 4366 MacroBuilder &Builder) const override { 4367 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4368 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4369 Builder.defineMacro("_M_X64", "100"); 4370 Builder.defineMacro("_M_AMD64", "100"); 4371 } 4372 }; 4373 4374 // x86-64 MinGW target 4375 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4376 public: 4377 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4378 : WindowsX86_64TargetInfo(Triple, Opts) { 4379 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4380 // with x86 FP ops. Weird. 4381 LongDoubleWidth = LongDoubleAlign = 128; 4382 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4383 } 4384 4385 void getTargetDefines(const LangOptions &Opts, 4386 MacroBuilder &Builder) const override { 4387 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4388 DefineStd(Builder, "WIN64", Opts); 4389 Builder.defineMacro("__MINGW64__"); 4390 addMinGWDefines(Opts, Builder); 4391 4392 // GCC defines this macro when it is using __gxx_personality_seh0. 4393 if (!Opts.SjLjExceptions) 4394 Builder.defineMacro("__SEH__"); 4395 } 4396 }; 4397 4398 // x86-64 Cygwin target 4399 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4400 public: 4401 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4402 : X86_64TargetInfo(Triple, Opts) { 4403 TLSSupported = false; 4404 WCharType = UnsignedShort; 4405 } 4406 void getTargetDefines(const LangOptions &Opts, 4407 MacroBuilder &Builder) const override { 4408 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4409 Builder.defineMacro("__x86_64__"); 4410 Builder.defineMacro("__CYGWIN__"); 4411 Builder.defineMacro("__CYGWIN64__"); 4412 addCygMingDefines(Opts, Builder); 4413 DefineStd(Builder, "unix", Opts); 4414 if (Opts.CPlusPlus) 4415 Builder.defineMacro("_GNU_SOURCE"); 4416 4417 // GCC defines this macro when it is using __gxx_personality_seh0. 4418 if (!Opts.SjLjExceptions) 4419 Builder.defineMacro("__SEH__"); 4420 } 4421 }; 4422 4423 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4424 public: 4425 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4426 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4427 Int64Type = SignedLongLong; 4428 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4429 llvm::Triple T = llvm::Triple(Triple); 4430 if (T.isiOS()) 4431 UseSignedCharForObjCBool = false; 4432 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4433 } 4434 4435 bool handleTargetFeatures(std::vector<std::string> &Features, 4436 DiagnosticsEngine &Diags) override { 4437 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4438 Diags)) 4439 return false; 4440 // We now know the features we have: we can decide how to align vectors. 4441 MaxVectorAlign = 4442 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4443 return true; 4444 } 4445 }; 4446 4447 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4448 public: 4449 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4450 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4451 IntMaxType = SignedLongLong; 4452 Int64Type = SignedLongLong; 4453 } 4454 }; 4455 4456 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4457 public: 4458 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4459 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4460 IntMaxType = SignedLongLong; 4461 Int64Type = SignedLongLong; 4462 } 4463 }; 4464 4465 class ARMTargetInfo : public TargetInfo { 4466 // Possible FPU choices. 4467 enum FPUMode { 4468 VFP2FPU = (1 << 0), 4469 VFP3FPU = (1 << 1), 4470 VFP4FPU = (1 << 2), 4471 NeonFPU = (1 << 3), 4472 FPARMV8 = (1 << 4) 4473 }; 4474 4475 // Possible HWDiv features. 4476 enum HWDivMode { 4477 HWDivThumb = (1 << 0), 4478 HWDivARM = (1 << 1) 4479 }; 4480 4481 static bool FPUModeIsVFP(FPUMode Mode) { 4482 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4483 } 4484 4485 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4486 static const char * const GCCRegNames[]; 4487 4488 std::string ABI, CPU; 4489 4490 StringRef CPUProfile; 4491 StringRef CPUAttr; 4492 4493 enum { 4494 FP_Default, 4495 FP_VFP, 4496 FP_Neon 4497 } FPMath; 4498 4499 unsigned ArchISA; 4500 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4501 unsigned ArchProfile; 4502 unsigned ArchVersion; 4503 4504 unsigned FPU : 5; 4505 4506 unsigned IsAAPCS : 1; 4507 unsigned HWDiv : 2; 4508 4509 // Initialized via features. 4510 unsigned SoftFloat : 1; 4511 unsigned SoftFloatABI : 1; 4512 4513 unsigned CRC : 1; 4514 unsigned Crypto : 1; 4515 unsigned DSP : 1; 4516 unsigned Unaligned : 1; 4517 4518 enum { 4519 LDREX_B = (1 << 0), /// byte (8-bit) 4520 LDREX_H = (1 << 1), /// half (16-bit) 4521 LDREX_W = (1 << 2), /// word (32-bit) 4522 LDREX_D = (1 << 3), /// double (64-bit) 4523 }; 4524 4525 uint32_t LDREX; 4526 4527 // ACLE 6.5.1 Hardware floating point 4528 enum { 4529 HW_FP_HP = (1 << 1), /// half (16-bit) 4530 HW_FP_SP = (1 << 2), /// single (32-bit) 4531 HW_FP_DP = (1 << 3), /// double (64-bit) 4532 }; 4533 uint32_t HW_FP; 4534 4535 static const Builtin::Info BuiltinInfo[]; 4536 4537 void setABIAAPCS() { 4538 IsAAPCS = true; 4539 4540 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4541 const llvm::Triple &T = getTriple(); 4542 4543 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4544 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4545 T.getOS() == llvm::Triple::Bitrig) 4546 SizeType = UnsignedLong; 4547 else 4548 SizeType = UnsignedInt; 4549 4550 switch (T.getOS()) { 4551 case llvm::Triple::NetBSD: 4552 WCharType = SignedInt; 4553 break; 4554 case llvm::Triple::Win32: 4555 WCharType = UnsignedShort; 4556 break; 4557 case llvm::Triple::Linux: 4558 default: 4559 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4560 WCharType = UnsignedInt; 4561 break; 4562 } 4563 4564 UseBitFieldTypeAlignment = true; 4565 4566 ZeroLengthBitfieldBoundary = 0; 4567 4568 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4569 // so set preferred for small types to 32. 4570 if (T.isOSBinFormatMachO()) { 4571 resetDataLayout(BigEndian 4572 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4573 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4574 } else if (T.isOSWindows()) { 4575 assert(!BigEndian && "Windows on ARM does not support big endian"); 4576 resetDataLayout("e" 4577 "-m:w" 4578 "-p:32:32" 4579 "-i64:64" 4580 "-v128:64:128" 4581 "-a:0:32" 4582 "-n32" 4583 "-S64"); 4584 } else if (T.isOSNaCl()) { 4585 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4586 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4587 } else { 4588 resetDataLayout(BigEndian 4589 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4590 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4591 } 4592 4593 // FIXME: Enumerated types are variable width in straight AAPCS. 4594 } 4595 4596 void setABIAPCS(bool IsAAPCS16) { 4597 const llvm::Triple &T = getTriple(); 4598 4599 IsAAPCS = false; 4600 4601 if (IsAAPCS16) 4602 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4603 else 4604 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4605 4606 // size_t is unsigned int on FreeBSD. 4607 if (T.getOS() == llvm::Triple::FreeBSD) 4608 SizeType = UnsignedInt; 4609 else 4610 SizeType = UnsignedLong; 4611 4612 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4613 WCharType = SignedInt; 4614 4615 // Do not respect the alignment of bit-field types when laying out 4616 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4617 UseBitFieldTypeAlignment = false; 4618 4619 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4620 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4621 /// gcc. 4622 ZeroLengthBitfieldBoundary = 32; 4623 4624 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4625 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4626 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4627 } else if (T.isOSBinFormatMachO()) 4628 resetDataLayout( 4629 BigEndian 4630 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4631 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4632 else 4633 resetDataLayout( 4634 BigEndian 4635 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4636 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4637 4638 // FIXME: Override "preferred align" for double and long long. 4639 } 4640 4641 void setArchInfo() { 4642 StringRef ArchName = getTriple().getArchName(); 4643 4644 ArchISA = llvm::ARM::parseArchISA(ArchName); 4645 CPU = llvm::ARM::getDefaultCPU(ArchName); 4646 unsigned AK = llvm::ARM::parseArch(ArchName); 4647 if (AK != llvm::ARM::AK_INVALID) 4648 ArchKind = AK; 4649 setArchInfo(ArchKind); 4650 } 4651 4652 void setArchInfo(unsigned Kind) { 4653 StringRef SubArch; 4654 4655 // cache TargetParser info 4656 ArchKind = Kind; 4657 SubArch = llvm::ARM::getSubArch(ArchKind); 4658 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4659 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4660 4661 // cache CPU related strings 4662 CPUAttr = getCPUAttr(); 4663 CPUProfile = getCPUProfile(); 4664 } 4665 4666 void setAtomic() { 4667 // when triple does not specify a sub arch, 4668 // then we are not using inline atomics 4669 bool ShouldUseInlineAtomic = 4670 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4671 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4672 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4673 if (ArchProfile == llvm::ARM::PK_M) { 4674 MaxAtomicPromoteWidth = 32; 4675 if (ShouldUseInlineAtomic) 4676 MaxAtomicInlineWidth = 32; 4677 } 4678 else { 4679 MaxAtomicPromoteWidth = 64; 4680 if (ShouldUseInlineAtomic) 4681 MaxAtomicInlineWidth = 64; 4682 } 4683 } 4684 4685 bool isThumb() const { 4686 return (ArchISA == llvm::ARM::IK_THUMB); 4687 } 4688 4689 bool supportsThumb() const { 4690 return CPUAttr.count('T') || ArchVersion >= 6; 4691 } 4692 4693 bool supportsThumb2() const { 4694 return CPUAttr.equals("6T2") || 4695 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 4696 } 4697 4698 StringRef getCPUAttr() const { 4699 // For most sub-arches, the build attribute CPU name is enough. 4700 // For Cortex variants, it's slightly different. 4701 switch(ArchKind) { 4702 default: 4703 return llvm::ARM::getCPUAttr(ArchKind); 4704 case llvm::ARM::AK_ARMV6M: 4705 return "6M"; 4706 case llvm::ARM::AK_ARMV7S: 4707 return "7S"; 4708 case llvm::ARM::AK_ARMV7A: 4709 return "7A"; 4710 case llvm::ARM::AK_ARMV7R: 4711 return "7R"; 4712 case llvm::ARM::AK_ARMV7M: 4713 return "7M"; 4714 case llvm::ARM::AK_ARMV7EM: 4715 return "7EM"; 4716 case llvm::ARM::AK_ARMV8A: 4717 return "8A"; 4718 case llvm::ARM::AK_ARMV8_1A: 4719 return "8_1A"; 4720 case llvm::ARM::AK_ARMV8_2A: 4721 return "8_2A"; 4722 case llvm::ARM::AK_ARMV8MBaseline: 4723 return "8M_BASE"; 4724 case llvm::ARM::AK_ARMV8MMainline: 4725 return "8M_MAIN"; 4726 } 4727 } 4728 4729 StringRef getCPUProfile() const { 4730 switch(ArchProfile) { 4731 case llvm::ARM::PK_A: 4732 return "A"; 4733 case llvm::ARM::PK_R: 4734 return "R"; 4735 case llvm::ARM::PK_M: 4736 return "M"; 4737 default: 4738 return ""; 4739 } 4740 } 4741 4742 public: 4743 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 4744 bool IsBigEndian) 4745 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 4746 HW_FP(0) { 4747 BigEndian = IsBigEndian; 4748 4749 switch (getTriple().getOS()) { 4750 case llvm::Triple::NetBSD: 4751 PtrDiffType = SignedLong; 4752 break; 4753 default: 4754 PtrDiffType = SignedInt; 4755 break; 4756 } 4757 4758 // Cache arch related info. 4759 setArchInfo(); 4760 4761 // {} in inline assembly are neon specifiers, not assembly variant 4762 // specifiers. 4763 NoAsmVariants = true; 4764 4765 // FIXME: This duplicates code from the driver that sets the -target-abi 4766 // option - this code is used if -target-abi isn't passed and should 4767 // be unified in some way. 4768 if (Triple.isOSBinFormatMachO()) { 4769 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4770 // the frontend matches that. 4771 if (Triple.getEnvironment() == llvm::Triple::EABI || 4772 Triple.getOS() == llvm::Triple::UnknownOS || 4773 StringRef(CPU).startswith("cortex-m")) { 4774 setABI("aapcs"); 4775 } else if (Triple.isWatchABI()) { 4776 setABI("aapcs16"); 4777 } else { 4778 setABI("apcs-gnu"); 4779 } 4780 } else if (Triple.isOSWindows()) { 4781 // FIXME: this is invalid for WindowsCE 4782 setABI("aapcs"); 4783 } else { 4784 // Select the default based on the platform. 4785 switch (Triple.getEnvironment()) { 4786 case llvm::Triple::Android: 4787 case llvm::Triple::GNUEABI: 4788 case llvm::Triple::GNUEABIHF: 4789 setABI("aapcs-linux"); 4790 break; 4791 case llvm::Triple::EABIHF: 4792 case llvm::Triple::EABI: 4793 setABI("aapcs"); 4794 break; 4795 case llvm::Triple::GNU: 4796 setABI("apcs-gnu"); 4797 break; 4798 default: 4799 if (Triple.getOS() == llvm::Triple::NetBSD) 4800 setABI("apcs-gnu"); 4801 else 4802 setABI("aapcs"); 4803 break; 4804 } 4805 } 4806 4807 // ARM targets default to using the ARM C++ ABI. 4808 TheCXXABI.set(TargetCXXABI::GenericARM); 4809 4810 // ARM has atomics up to 8 bytes 4811 setAtomic(); 4812 4813 // Do force alignment of members that follow zero length bitfields. If 4814 // the alignment of the zero-length bitfield is greater than the member 4815 // that follows it, `bar', `bar' will be aligned as the type of the 4816 // zero length bitfield. 4817 UseZeroLengthBitfieldAlignment = true; 4818 4819 if (Triple.getOS() == llvm::Triple::Linux || 4820 Triple.getOS() == llvm::Triple::UnknownOS) 4821 this->MCountName = 4822 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 4823 } 4824 4825 StringRef getABI() const override { return ABI; } 4826 4827 bool setABI(const std::string &Name) override { 4828 ABI = Name; 4829 4830 // The defaults (above) are for AAPCS, check if we need to change them. 4831 // 4832 // FIXME: We need support for -meabi... we could just mangle it into the 4833 // name. 4834 if (Name == "apcs-gnu" || Name == "aapcs16") { 4835 setABIAPCS(Name == "aapcs16"); 4836 return true; 4837 } 4838 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4839 setABIAAPCS(); 4840 return true; 4841 } 4842 return false; 4843 } 4844 4845 // FIXME: This should be based on Arch attributes, not CPU names. 4846 bool 4847 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4848 StringRef CPU, 4849 const std::vector<std::string> &FeaturesVec) const override { 4850 4851 std::vector<const char*> TargetFeatures; 4852 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4853 4854 // get default FPU features 4855 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4856 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4857 4858 // get default Extension features 4859 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 4860 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4861 4862 for (const char *Feature : TargetFeatures) 4863 if (Feature[0] == '+') 4864 Features[Feature+1] = true; 4865 4866 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4867 } 4868 4869 bool handleTargetFeatures(std::vector<std::string> &Features, 4870 DiagnosticsEngine &Diags) override { 4871 FPU = 0; 4872 CRC = 0; 4873 Crypto = 0; 4874 DSP = 0; 4875 Unaligned = 1; 4876 SoftFloat = SoftFloatABI = false; 4877 HWDiv = 0; 4878 4879 // This does not diagnose illegal cases like having both 4880 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4881 uint32_t HW_FP_remove = 0; 4882 for (const auto &Feature : Features) { 4883 if (Feature == "+soft-float") { 4884 SoftFloat = true; 4885 } else if (Feature == "+soft-float-abi") { 4886 SoftFloatABI = true; 4887 } else if (Feature == "+vfp2") { 4888 FPU |= VFP2FPU; 4889 HW_FP |= HW_FP_SP | HW_FP_DP; 4890 } else if (Feature == "+vfp3") { 4891 FPU |= VFP3FPU; 4892 HW_FP |= HW_FP_SP | HW_FP_DP; 4893 } else if (Feature == "+vfp4") { 4894 FPU |= VFP4FPU; 4895 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4896 } else if (Feature == "+fp-armv8") { 4897 FPU |= FPARMV8; 4898 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4899 } else if (Feature == "+neon") { 4900 FPU |= NeonFPU; 4901 HW_FP |= HW_FP_SP | HW_FP_DP; 4902 } else if (Feature == "+hwdiv") { 4903 HWDiv |= HWDivThumb; 4904 } else if (Feature == "+hwdiv-arm") { 4905 HWDiv |= HWDivARM; 4906 } else if (Feature == "+crc") { 4907 CRC = 1; 4908 } else if (Feature == "+crypto") { 4909 Crypto = 1; 4910 } else if (Feature == "+dsp") { 4911 DSP = 1; 4912 } else if (Feature == "+fp-only-sp") { 4913 HW_FP_remove |= HW_FP_DP; 4914 } else if (Feature == "+strict-align") { 4915 Unaligned = 0; 4916 } else if (Feature == "+fp16") { 4917 HW_FP |= HW_FP_HP; 4918 } 4919 } 4920 HW_FP &= ~HW_FP_remove; 4921 4922 switch (ArchVersion) { 4923 case 6: 4924 if (ArchProfile == llvm::ARM::PK_M) 4925 LDREX = 0; 4926 else if (ArchKind == llvm::ARM::AK_ARMV6K) 4927 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4928 else 4929 LDREX = LDREX_W; 4930 break; 4931 case 7: 4932 if (ArchProfile == llvm::ARM::PK_M) 4933 LDREX = LDREX_W | LDREX_H | LDREX_B ; 4934 else 4935 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4936 break; 4937 case 8: 4938 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4939 } 4940 4941 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4942 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4943 return false; 4944 } 4945 4946 if (FPMath == FP_Neon) 4947 Features.push_back("+neonfp"); 4948 else if (FPMath == FP_VFP) 4949 Features.push_back("-neonfp"); 4950 4951 // Remove front-end specific options which the backend handles differently. 4952 auto Feature = 4953 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4954 if (Feature != Features.end()) 4955 Features.erase(Feature); 4956 4957 return true; 4958 } 4959 4960 bool hasFeature(StringRef Feature) const override { 4961 return llvm::StringSwitch<bool>(Feature) 4962 .Case("arm", true) 4963 .Case("aarch32", true) 4964 .Case("softfloat", SoftFloat) 4965 .Case("thumb", isThumb()) 4966 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4967 .Case("hwdiv", HWDiv & HWDivThumb) 4968 .Case("hwdiv-arm", HWDiv & HWDivARM) 4969 .Default(false); 4970 } 4971 4972 bool setCPU(const std::string &Name) override { 4973 if (Name != "generic") 4974 setArchInfo(llvm::ARM::parseCPUArch(Name)); 4975 4976 if (ArchKind == llvm::ARM::AK_INVALID) 4977 return false; 4978 setAtomic(); 4979 CPU = Name; 4980 return true; 4981 } 4982 4983 bool setFPMath(StringRef Name) override; 4984 4985 void getTargetDefines(const LangOptions &Opts, 4986 MacroBuilder &Builder) const override { 4987 // Target identification. 4988 Builder.defineMacro("__arm"); 4989 Builder.defineMacro("__arm__"); 4990 // For bare-metal none-eabi. 4991 if (getTriple().getOS() == llvm::Triple::UnknownOS && 4992 getTriple().getEnvironment() == llvm::Triple::EABI) 4993 Builder.defineMacro("__ELF__"); 4994 4995 // Target properties. 4996 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4997 4998 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 4999 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5000 if (getTriple().isWatchABI()) 5001 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5002 5003 if (!CPUAttr.empty()) 5004 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5005 5006 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5007 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5008 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5009 5010 if (ArchVersion >= 8) { 5011 // ACLE 6.5.7 Crypto Extension 5012 if (Crypto) 5013 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5014 // ACLE 6.5.8 CRC32 Extension 5015 if (CRC) 5016 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5017 // ACLE 6.5.10 Numeric Maximum and Minimum 5018 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5019 // ACLE 6.5.9 Directed Rounding 5020 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5021 } 5022 5023 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5024 // is not defined for the M-profile. 5025 // NOTE that the default profile is assumed to be 'A' 5026 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5027 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5028 5029 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5030 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5031 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5032 // v7 and v8 architectures excluding v8-M Baseline. 5033 if (supportsThumb2()) 5034 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5035 else if (supportsThumb()) 5036 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5037 5038 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5039 // instruction set such as ARM or Thumb. 5040 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5041 5042 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5043 5044 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5045 if (!CPUProfile.empty()) 5046 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5047 5048 // ACLE 6.4.3 Unaligned access supported in hardware 5049 if (Unaligned) 5050 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5051 5052 // ACLE 6.4.4 LDREX/STREX 5053 if (LDREX) 5054 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5055 5056 // ACLE 6.4.5 CLZ 5057 if (ArchVersion == 5 || 5058 (ArchVersion == 6 && CPUProfile != "M") || 5059 ArchVersion > 6) 5060 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5061 5062 // ACLE 6.5.1 Hardware Floating Point 5063 if (HW_FP) 5064 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5065 5066 // ACLE predefines. 5067 Builder.defineMacro("__ARM_ACLE", "200"); 5068 5069 // FP16 support (we currently only support IEEE format). 5070 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5071 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5072 5073 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5074 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5075 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5076 5077 // Subtarget options. 5078 5079 // FIXME: It's more complicated than this and we don't really support 5080 // interworking. 5081 // Windows on ARM does not "support" interworking 5082 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5083 Builder.defineMacro("__THUMB_INTERWORK__"); 5084 5085 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5086 // Embedded targets on Darwin follow AAPCS, but not EABI. 5087 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5088 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5089 Builder.defineMacro("__ARM_EABI__"); 5090 Builder.defineMacro("__ARM_PCS", "1"); 5091 } 5092 5093 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5094 ABI == "aapcs16") 5095 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5096 5097 if (SoftFloat) 5098 Builder.defineMacro("__SOFTFP__"); 5099 5100 if (CPU == "xscale") 5101 Builder.defineMacro("__XSCALE__"); 5102 5103 if (isThumb()) { 5104 Builder.defineMacro("__THUMBEL__"); 5105 Builder.defineMacro("__thumb__"); 5106 if (supportsThumb2()) 5107 Builder.defineMacro("__thumb2__"); 5108 } 5109 5110 // ACLE 6.4.9 32-bit SIMD instructions 5111 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5112 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5113 5114 // ACLE 6.4.10 Hardware Integer Divide 5115 if (((HWDiv & HWDivThumb) && isThumb()) || 5116 ((HWDiv & HWDivARM) && !isThumb())) { 5117 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5118 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5119 } 5120 5121 // Note, this is always on in gcc, even though it doesn't make sense. 5122 Builder.defineMacro("__APCS_32__"); 5123 5124 if (FPUModeIsVFP((FPUMode) FPU)) { 5125 Builder.defineMacro("__VFP_FP__"); 5126 if (FPU & VFP2FPU) 5127 Builder.defineMacro("__ARM_VFPV2__"); 5128 if (FPU & VFP3FPU) 5129 Builder.defineMacro("__ARM_VFPV3__"); 5130 if (FPU & VFP4FPU) 5131 Builder.defineMacro("__ARM_VFPV4__"); 5132 } 5133 5134 // This only gets set when Neon instructions are actually available, unlike 5135 // the VFP define, hence the soft float and arch check. This is subtly 5136 // different from gcc, we follow the intent which was that it should be set 5137 // when Neon instructions are actually available. 5138 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5139 Builder.defineMacro("__ARM_NEON", "1"); 5140 Builder.defineMacro("__ARM_NEON__"); 5141 // current AArch32 NEON implementations do not support double-precision 5142 // floating-point even when it is present in VFP. 5143 Builder.defineMacro("__ARM_NEON_FP", 5144 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5145 } 5146 5147 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5148 Opts.ShortWChar ? "2" : "4"); 5149 5150 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5151 Opts.ShortEnums ? "1" : "4"); 5152 5153 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5154 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5155 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5156 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5157 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5158 } 5159 5160 // ACLE 6.4.7 DSP instructions 5161 if (DSP) { 5162 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5163 } 5164 5165 // ACLE 6.4.8 Saturation instructions 5166 bool SAT = false; 5167 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5168 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5169 SAT = true; 5170 } 5171 5172 // ACLE 6.4.6 Q (saturation) flag 5173 if (DSP || SAT) 5174 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5175 5176 if (Opts.UnsafeFPMath) 5177 Builder.defineMacro("__ARM_FP_FAST", "1"); 5178 5179 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5180 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5181 } 5182 5183 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5184 return llvm::makeArrayRef(BuiltinInfo, 5185 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5186 } 5187 bool isCLZForZeroUndef() const override { return false; } 5188 BuiltinVaListKind getBuiltinVaListKind() const override { 5189 return IsAAPCS 5190 ? AAPCSABIBuiltinVaList 5191 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5192 : TargetInfo::VoidPtrBuiltinVaList); 5193 } 5194 ArrayRef<const char *> getGCCRegNames() const override; 5195 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5196 bool validateAsmConstraint(const char *&Name, 5197 TargetInfo::ConstraintInfo &Info) const override { 5198 switch (*Name) { 5199 default: break; 5200 case 'l': // r0-r7 5201 case 'h': // r8-r15 5202 case 't': // VFP Floating point register single precision 5203 case 'w': // VFP Floating point register double precision 5204 Info.setAllowsRegister(); 5205 return true; 5206 case 'I': 5207 case 'J': 5208 case 'K': 5209 case 'L': 5210 case 'M': 5211 // FIXME 5212 return true; 5213 case 'Q': // A memory address that is a single base register. 5214 Info.setAllowsMemory(); 5215 return true; 5216 case 'U': // a memory reference... 5217 switch (Name[1]) { 5218 case 'q': // ...ARMV4 ldrsb 5219 case 'v': // ...VFP load/store (reg+constant offset) 5220 case 'y': // ...iWMMXt load/store 5221 case 't': // address valid for load/store opaque types wider 5222 // than 128-bits 5223 case 'n': // valid address for Neon doubleword vector load/store 5224 case 'm': // valid address for Neon element and structure load/store 5225 case 's': // valid address for non-offset loads/stores of quad-word 5226 // values in four ARM registers 5227 Info.setAllowsMemory(); 5228 Name++; 5229 return true; 5230 } 5231 } 5232 return false; 5233 } 5234 std::string convertConstraint(const char *&Constraint) const override { 5235 std::string R; 5236 switch (*Constraint) { 5237 case 'U': // Two-character constraint; add "^" hint for later parsing. 5238 R = std::string("^") + std::string(Constraint, 2); 5239 Constraint++; 5240 break; 5241 case 'p': // 'p' should be translated to 'r' by default. 5242 R = std::string("r"); 5243 break; 5244 default: 5245 return std::string(1, *Constraint); 5246 } 5247 return R; 5248 } 5249 bool 5250 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5251 std::string &SuggestedModifier) const override { 5252 bool isOutput = (Constraint[0] == '='); 5253 bool isInOut = (Constraint[0] == '+'); 5254 5255 // Strip off constraint modifiers. 5256 while (Constraint[0] == '=' || 5257 Constraint[0] == '+' || 5258 Constraint[0] == '&') 5259 Constraint = Constraint.substr(1); 5260 5261 switch (Constraint[0]) { 5262 default: break; 5263 case 'r': { 5264 switch (Modifier) { 5265 default: 5266 return (isInOut || isOutput || Size <= 64); 5267 case 'q': 5268 // A register of size 32 cannot fit a vector type. 5269 return false; 5270 } 5271 } 5272 } 5273 5274 return true; 5275 } 5276 const char *getClobbers() const override { 5277 // FIXME: Is this really right? 5278 return ""; 5279 } 5280 5281 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5282 switch (CC) { 5283 case CC_AAPCS: 5284 case CC_AAPCS_VFP: 5285 case CC_Swift: 5286 return CCCR_OK; 5287 default: 5288 return CCCR_Warning; 5289 } 5290 } 5291 5292 int getEHDataRegisterNumber(unsigned RegNo) const override { 5293 if (RegNo == 0) return 0; 5294 if (RegNo == 1) return 1; 5295 return -1; 5296 } 5297 5298 bool hasSjLjLowering() const override { 5299 return true; 5300 } 5301 }; 5302 5303 bool ARMTargetInfo::setFPMath(StringRef Name) { 5304 if (Name == "neon") { 5305 FPMath = FP_Neon; 5306 return true; 5307 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5308 Name == "vfp4") { 5309 FPMath = FP_VFP; 5310 return true; 5311 } 5312 return false; 5313 } 5314 5315 const char * const ARMTargetInfo::GCCRegNames[] = { 5316 // Integer registers 5317 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5318 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5319 5320 // Float registers 5321 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5322 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5323 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5324 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5325 5326 // Double registers 5327 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5328 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5329 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5330 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5331 5332 // Quad registers 5333 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5334 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5335 }; 5336 5337 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5338 return llvm::makeArrayRef(GCCRegNames); 5339 } 5340 5341 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5342 { { "a1" }, "r0" }, 5343 { { "a2" }, "r1" }, 5344 { { "a3" }, "r2" }, 5345 { { "a4" }, "r3" }, 5346 { { "v1" }, "r4" }, 5347 { { "v2" }, "r5" }, 5348 { { "v3" }, "r6" }, 5349 { { "v4" }, "r7" }, 5350 { { "v5" }, "r8" }, 5351 { { "v6", "rfp" }, "r9" }, 5352 { { "sl" }, "r10" }, 5353 { { "fp" }, "r11" }, 5354 { { "ip" }, "r12" }, 5355 { { "r13" }, "sp" }, 5356 { { "r14" }, "lr" }, 5357 { { "r15" }, "pc" }, 5358 // The S, D and Q registers overlap, but aren't really aliases; we 5359 // don't want to substitute one of these for a different-sized one. 5360 }; 5361 5362 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5363 return llvm::makeArrayRef(GCCRegAliases); 5364 } 5365 5366 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5367 #define BUILTIN(ID, TYPE, ATTRS) \ 5368 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5369 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5370 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5371 #include "clang/Basic/BuiltinsNEON.def" 5372 5373 #define BUILTIN(ID, TYPE, ATTRS) \ 5374 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5375 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5376 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5377 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5378 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5379 #include "clang/Basic/BuiltinsARM.def" 5380 }; 5381 5382 class ARMleTargetInfo : public ARMTargetInfo { 5383 public: 5384 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5385 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/false) {} 5386 void getTargetDefines(const LangOptions &Opts, 5387 MacroBuilder &Builder) const override { 5388 Builder.defineMacro("__ARMEL__"); 5389 ARMTargetInfo::getTargetDefines(Opts, Builder); 5390 } 5391 }; 5392 5393 class ARMbeTargetInfo : public ARMTargetInfo { 5394 public: 5395 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5396 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/true) {} 5397 void getTargetDefines(const LangOptions &Opts, 5398 MacroBuilder &Builder) const override { 5399 Builder.defineMacro("__ARMEB__"); 5400 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5401 ARMTargetInfo::getTargetDefines(Opts, Builder); 5402 } 5403 }; 5404 5405 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5406 const llvm::Triple Triple; 5407 public: 5408 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5409 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5410 WCharType = UnsignedShort; 5411 SizeType = UnsignedInt; 5412 } 5413 void getVisualStudioDefines(const LangOptions &Opts, 5414 MacroBuilder &Builder) const { 5415 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5416 5417 // FIXME: this is invalid for WindowsCE 5418 Builder.defineMacro("_M_ARM_NT", "1"); 5419 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5420 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5421 5422 assert((Triple.getArch() == llvm::Triple::arm || 5423 Triple.getArch() == llvm::Triple::thumb) && 5424 "invalid architecture for Windows ARM target info"); 5425 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5426 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5427 5428 // TODO map the complete set of values 5429 // 31: VFPv3 40: VFPv4 5430 Builder.defineMacro("_M_ARM_FP", "31"); 5431 } 5432 BuiltinVaListKind getBuiltinVaListKind() const override { 5433 return TargetInfo::CharPtrBuiltinVaList; 5434 } 5435 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5436 switch (CC) { 5437 case CC_X86StdCall: 5438 case CC_X86ThisCall: 5439 case CC_X86FastCall: 5440 case CC_X86VectorCall: 5441 return CCCR_Ignore; 5442 case CC_C: 5443 return CCCR_OK; 5444 default: 5445 return CCCR_Warning; 5446 } 5447 } 5448 }; 5449 5450 // Windows ARM + Itanium C++ ABI Target 5451 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5452 public: 5453 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5454 const TargetOptions &Opts) 5455 : WindowsARMTargetInfo(Triple, Opts) { 5456 TheCXXABI.set(TargetCXXABI::GenericARM); 5457 } 5458 5459 void getTargetDefines(const LangOptions &Opts, 5460 MacroBuilder &Builder) const override { 5461 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5462 5463 if (Opts.MSVCCompat) 5464 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5465 } 5466 }; 5467 5468 // Windows ARM, MS (C++) ABI 5469 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5470 public: 5471 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5472 const TargetOptions &Opts) 5473 : WindowsARMTargetInfo(Triple, Opts) { 5474 TheCXXABI.set(TargetCXXABI::Microsoft); 5475 } 5476 5477 void getTargetDefines(const LangOptions &Opts, 5478 MacroBuilder &Builder) const override { 5479 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5480 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5481 } 5482 }; 5483 5484 // ARM MinGW target 5485 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5486 public: 5487 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5488 : WindowsARMTargetInfo(Triple, Opts) { 5489 TheCXXABI.set(TargetCXXABI::GenericARM); 5490 } 5491 5492 void getTargetDefines(const LangOptions &Opts, 5493 MacroBuilder &Builder) const override { 5494 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5495 DefineStd(Builder, "WIN32", Opts); 5496 DefineStd(Builder, "WINNT", Opts); 5497 Builder.defineMacro("_ARM_"); 5498 addMinGWDefines(Opts, Builder); 5499 } 5500 }; 5501 5502 // ARM Cygwin target 5503 class CygwinARMTargetInfo : public ARMleTargetInfo { 5504 public: 5505 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5506 : ARMleTargetInfo(Triple, Opts) { 5507 TLSSupported = false; 5508 WCharType = UnsignedShort; 5509 DoubleAlign = LongLongAlign = 64; 5510 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5511 } 5512 void getTargetDefines(const LangOptions &Opts, 5513 MacroBuilder &Builder) const override { 5514 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5515 Builder.defineMacro("_ARM_"); 5516 Builder.defineMacro("__CYGWIN__"); 5517 Builder.defineMacro("__CYGWIN32__"); 5518 DefineStd(Builder, "unix", Opts); 5519 if (Opts.CPlusPlus) 5520 Builder.defineMacro("_GNU_SOURCE"); 5521 } 5522 }; 5523 5524 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 5525 protected: 5526 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5527 MacroBuilder &Builder) const override { 5528 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5529 } 5530 5531 public: 5532 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5533 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 5534 HasAlignMac68kSupport = true; 5535 // iOS always has 64-bit atomic instructions. 5536 // FIXME: This should be based off of the target features in 5537 // ARMleTargetInfo. 5538 MaxAtomicInlineWidth = 64; 5539 5540 if (Triple.isWatchABI()) { 5541 // Darwin on iOS uses a variant of the ARM C++ ABI. 5542 TheCXXABI.set(TargetCXXABI::WatchOS); 5543 5544 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5545 // size_t is long, it's a bit weird for it to be int. 5546 PtrDiffType = SignedLong; 5547 5548 // BOOL should be a real boolean on the new ABI 5549 UseSignedCharForObjCBool = false; 5550 } else 5551 TheCXXABI.set(TargetCXXABI::iOS); 5552 } 5553 }; 5554 5555 class AArch64TargetInfo : public TargetInfo { 5556 virtual void setDataLayout() = 0; 5557 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5558 static const char *const GCCRegNames[]; 5559 5560 enum FPUModeEnum { 5561 FPUMode, 5562 NeonMode 5563 }; 5564 5565 unsigned FPU; 5566 unsigned CRC; 5567 unsigned Crypto; 5568 unsigned Unaligned; 5569 unsigned V8_1A; 5570 5571 static const Builtin::Info BuiltinInfo[]; 5572 5573 std::string ABI; 5574 5575 public: 5576 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5577 : TargetInfo(Triple), ABI("aapcs") { 5578 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5579 WCharType = SignedInt; 5580 5581 // NetBSD apparently prefers consistency across ARM targets to consistency 5582 // across 64-bit targets. 5583 Int64Type = SignedLongLong; 5584 IntMaxType = SignedLongLong; 5585 } else { 5586 WCharType = UnsignedInt; 5587 Int64Type = SignedLong; 5588 IntMaxType = SignedLong; 5589 } 5590 5591 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5592 MaxVectorAlign = 128; 5593 MaxAtomicInlineWidth = 128; 5594 MaxAtomicPromoteWidth = 128; 5595 5596 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5597 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5598 5599 // {} in inline assembly are neon specifiers, not assembly variant 5600 // specifiers. 5601 NoAsmVariants = true; 5602 5603 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5604 // contributes to the alignment of the containing aggregate in the same way 5605 // a plain (non bit-field) member of that type would, without exception for 5606 // zero-sized or anonymous bit-fields." 5607 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5608 UseZeroLengthBitfieldAlignment = true; 5609 5610 // AArch64 targets default to using the ARM C++ ABI. 5611 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5612 5613 if (Triple.getOS() == llvm::Triple::Linux || 5614 Triple.getOS() == llvm::Triple::UnknownOS) 5615 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 5616 } 5617 5618 StringRef getABI() const override { return ABI; } 5619 bool setABI(const std::string &Name) override { 5620 if (Name != "aapcs" && Name != "darwinpcs") 5621 return false; 5622 5623 ABI = Name; 5624 return true; 5625 } 5626 5627 bool setCPU(const std::string &Name) override { 5628 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5629 .Case("generic", true) 5630 .Cases("cortex-a53", "cortex-a57", "cortex-a72", 5631 "cortex-a35", "exynos-m1", true) 5632 .Case("cyclone", true) 5633 .Case("kryo", true) 5634 .Default(false); 5635 return CPUKnown; 5636 } 5637 5638 void getTargetDefines(const LangOptions &Opts, 5639 MacroBuilder &Builder) const override { 5640 // Target identification. 5641 Builder.defineMacro("__aarch64__"); 5642 5643 // Target properties. 5644 Builder.defineMacro("_LP64"); 5645 Builder.defineMacro("__LP64__"); 5646 5647 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5648 Builder.defineMacro("__ARM_ACLE", "200"); 5649 Builder.defineMacro("__ARM_ARCH", "8"); 5650 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5651 5652 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5653 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5654 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5655 5656 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5657 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5658 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5659 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5660 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5661 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5662 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5663 5664 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5665 5666 // 0xe implies support for half, single and double precision operations. 5667 Builder.defineMacro("__ARM_FP", "0xE"); 5668 5669 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5670 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5671 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5672 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5673 5674 if (Opts.UnsafeFPMath) 5675 Builder.defineMacro("__ARM_FP_FAST", "1"); 5676 5677 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5678 5679 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5680 Opts.ShortEnums ? "1" : "4"); 5681 5682 if (FPU == NeonMode) { 5683 Builder.defineMacro("__ARM_NEON", "1"); 5684 // 64-bit NEON supports half, single and double precision operations. 5685 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5686 } 5687 5688 if (CRC) 5689 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5690 5691 if (Crypto) 5692 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5693 5694 if (Unaligned) 5695 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5696 5697 if (V8_1A) 5698 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5699 5700 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5701 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5702 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5703 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5704 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5705 } 5706 5707 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5708 return llvm::makeArrayRef(BuiltinInfo, 5709 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5710 } 5711 5712 bool hasFeature(StringRef Feature) const override { 5713 return Feature == "aarch64" || 5714 Feature == "arm64" || 5715 Feature == "arm" || 5716 (Feature == "neon" && FPU == NeonMode); 5717 } 5718 5719 bool handleTargetFeatures(std::vector<std::string> &Features, 5720 DiagnosticsEngine &Diags) override { 5721 FPU = FPUMode; 5722 CRC = 0; 5723 Crypto = 0; 5724 Unaligned = 1; 5725 V8_1A = 0; 5726 5727 for (const auto &Feature : Features) { 5728 if (Feature == "+neon") 5729 FPU = NeonMode; 5730 if (Feature == "+crc") 5731 CRC = 1; 5732 if (Feature == "+crypto") 5733 Crypto = 1; 5734 if (Feature == "+strict-align") 5735 Unaligned = 0; 5736 if (Feature == "+v8.1a") 5737 V8_1A = 1; 5738 } 5739 5740 setDataLayout(); 5741 5742 return true; 5743 } 5744 5745 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5746 switch (CC) { 5747 case CC_C: 5748 case CC_Swift: 5749 case CC_PreserveMost: 5750 case CC_PreserveAll: 5751 return CCCR_OK; 5752 default: 5753 return CCCR_Warning; 5754 } 5755 } 5756 5757 bool isCLZForZeroUndef() const override { return false; } 5758 5759 BuiltinVaListKind getBuiltinVaListKind() const override { 5760 return TargetInfo::AArch64ABIBuiltinVaList; 5761 } 5762 5763 ArrayRef<const char *> getGCCRegNames() const override; 5764 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5765 5766 bool validateAsmConstraint(const char *&Name, 5767 TargetInfo::ConstraintInfo &Info) const override { 5768 switch (*Name) { 5769 default: 5770 return false; 5771 case 'w': // Floating point and SIMD registers (V0-V31) 5772 Info.setAllowsRegister(); 5773 return true; 5774 case 'I': // Constant that can be used with an ADD instruction 5775 case 'J': // Constant that can be used with a SUB instruction 5776 case 'K': // Constant that can be used with a 32-bit logical instruction 5777 case 'L': // Constant that can be used with a 64-bit logical instruction 5778 case 'M': // Constant that can be used as a 32-bit MOV immediate 5779 case 'N': // Constant that can be used as a 64-bit MOV immediate 5780 case 'Y': // Floating point constant zero 5781 case 'Z': // Integer constant zero 5782 return true; 5783 case 'Q': // A memory reference with base register and no offset 5784 Info.setAllowsMemory(); 5785 return true; 5786 case 'S': // A symbolic address 5787 Info.setAllowsRegister(); 5788 return true; 5789 case 'U': 5790 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5791 // Utf: A memory address suitable for ldp/stp in TF mode. 5792 // Usa: An absolute symbolic address. 5793 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5794 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5795 case 'z': // Zero register, wzr or xzr 5796 Info.setAllowsRegister(); 5797 return true; 5798 case 'x': // Floating point and SIMD registers (V0-V15) 5799 Info.setAllowsRegister(); 5800 return true; 5801 } 5802 return false; 5803 } 5804 5805 bool 5806 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5807 std::string &SuggestedModifier) const override { 5808 // Strip off constraint modifiers. 5809 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5810 Constraint = Constraint.substr(1); 5811 5812 switch (Constraint[0]) { 5813 default: 5814 return true; 5815 case 'z': 5816 case 'r': { 5817 switch (Modifier) { 5818 case 'x': 5819 case 'w': 5820 // For now assume that the person knows what they're 5821 // doing with the modifier. 5822 return true; 5823 default: 5824 // By default an 'r' constraint will be in the 'x' 5825 // registers. 5826 if (Size == 64) 5827 return true; 5828 5829 SuggestedModifier = "w"; 5830 return false; 5831 } 5832 } 5833 } 5834 } 5835 5836 const char *getClobbers() const override { return ""; } 5837 5838 int getEHDataRegisterNumber(unsigned RegNo) const override { 5839 if (RegNo == 0) 5840 return 0; 5841 if (RegNo == 1) 5842 return 1; 5843 return -1; 5844 } 5845 }; 5846 5847 const char *const AArch64TargetInfo::GCCRegNames[] = { 5848 // 32-bit Integer registers 5849 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5850 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5851 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5852 5853 // 64-bit Integer registers 5854 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5855 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5856 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5857 5858 // 32-bit floating point regsisters 5859 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5860 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5861 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5862 5863 // 64-bit floating point regsisters 5864 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5865 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5866 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5867 5868 // Vector registers 5869 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5870 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5871 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5872 }; 5873 5874 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 5875 return llvm::makeArrayRef(GCCRegNames); 5876 } 5877 5878 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5879 { { "w31" }, "wsp" }, 5880 { { "x29" }, "fp" }, 5881 { { "x30" }, "lr" }, 5882 { { "x31" }, "sp" }, 5883 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5884 // don't want to substitute one of these for a different-sized one. 5885 }; 5886 5887 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 5888 return llvm::makeArrayRef(GCCRegAliases); 5889 } 5890 5891 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5892 #define BUILTIN(ID, TYPE, ATTRS) \ 5893 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5894 #include "clang/Basic/BuiltinsNEON.def" 5895 5896 #define BUILTIN(ID, TYPE, ATTRS) \ 5897 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5898 #include "clang/Basic/BuiltinsAArch64.def" 5899 }; 5900 5901 class AArch64leTargetInfo : public AArch64TargetInfo { 5902 void setDataLayout() override { 5903 if (getTriple().isOSBinFormatMachO()) 5904 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 5905 else 5906 resetDataLayout("e-m:e-i64:64-i128:128-n32:64-S128"); 5907 } 5908 5909 public: 5910 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5911 : AArch64TargetInfo(Triple, Opts) { 5912 BigEndian = false; 5913 } 5914 void getTargetDefines(const LangOptions &Opts, 5915 MacroBuilder &Builder) const override { 5916 Builder.defineMacro("__AARCH64EL__"); 5917 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5918 } 5919 }; 5920 5921 class AArch64beTargetInfo : public AArch64TargetInfo { 5922 void setDataLayout() override { 5923 assert(!getTriple().isOSBinFormatMachO()); 5924 resetDataLayout("E-m:e-i64:64-i128:128-n32:64-S128"); 5925 } 5926 5927 public: 5928 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5929 : AArch64TargetInfo(Triple, Opts) {} 5930 void getTargetDefines(const LangOptions &Opts, 5931 MacroBuilder &Builder) const override { 5932 Builder.defineMacro("__AARCH64EB__"); 5933 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5934 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5935 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5936 } 5937 }; 5938 5939 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5940 protected: 5941 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5942 MacroBuilder &Builder) const override { 5943 Builder.defineMacro("__AARCH64_SIMD__"); 5944 Builder.defineMacro("__ARM64_ARCH_8__"); 5945 Builder.defineMacro("__ARM_NEON__"); 5946 Builder.defineMacro("__LITTLE_ENDIAN__"); 5947 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5948 Builder.defineMacro("__arm64", "1"); 5949 Builder.defineMacro("__arm64__", "1"); 5950 5951 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5952 } 5953 5954 public: 5955 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5956 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 5957 Int64Type = SignedLongLong; 5958 WCharType = SignedInt; 5959 UseSignedCharForObjCBool = false; 5960 5961 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5962 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5963 5964 TheCXXABI.set(TargetCXXABI::iOS64); 5965 } 5966 5967 BuiltinVaListKind getBuiltinVaListKind() const override { 5968 return TargetInfo::CharPtrBuiltinVaList; 5969 } 5970 }; 5971 5972 // Hexagon abstract base class 5973 class HexagonTargetInfo : public TargetInfo { 5974 static const Builtin::Info BuiltinInfo[]; 5975 static const char * const GCCRegNames[]; 5976 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5977 std::string CPU; 5978 bool HasHVX, HasHVXDouble; 5979 5980 public: 5981 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 5982 : TargetInfo(Triple) { 5983 BigEndian = false; 5984 // Specify the vector alignment explicitly. For v512x1, the calculated 5985 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 5986 // the required minimum of 64 bytes. 5987 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 5988 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 5989 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 5990 SizeType = UnsignedInt; 5991 PtrDiffType = SignedInt; 5992 IntPtrType = SignedInt; 5993 5994 // {} in inline assembly are packet specifiers, not assembly variant 5995 // specifiers. 5996 NoAsmVariants = true; 5997 5998 LargeArrayMinWidth = 64; 5999 LargeArrayAlign = 64; 6000 UseBitFieldTypeAlignment = true; 6001 ZeroLengthBitfieldBoundary = 32; 6002 HasHVX = HasHVXDouble = false; 6003 } 6004 6005 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6006 return llvm::makeArrayRef(BuiltinInfo, 6007 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6008 } 6009 6010 bool validateAsmConstraint(const char *&Name, 6011 TargetInfo::ConstraintInfo &Info) const override { 6012 return true; 6013 } 6014 6015 void getTargetDefines(const LangOptions &Opts, 6016 MacroBuilder &Builder) const override; 6017 6018 bool isCLZForZeroUndef() const override { return false; } 6019 6020 bool hasFeature(StringRef Feature) const override { 6021 return llvm::StringSwitch<bool>(Feature) 6022 .Case("hexagon", true) 6023 .Case("hvx", HasHVX) 6024 .Case("hvx-double", HasHVXDouble) 6025 .Default(false); 6026 } 6027 6028 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6029 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6030 const override; 6031 6032 bool handleTargetFeatures(std::vector<std::string> &Features, 6033 DiagnosticsEngine &Diags) override; 6034 6035 BuiltinVaListKind getBuiltinVaListKind() const override { 6036 return TargetInfo::CharPtrBuiltinVaList; 6037 } 6038 ArrayRef<const char *> getGCCRegNames() const override; 6039 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6040 const char *getClobbers() const override { 6041 return ""; 6042 } 6043 6044 static const char *getHexagonCPUSuffix(StringRef Name) { 6045 return llvm::StringSwitch<const char*>(Name) 6046 .Case("hexagonv4", "4") 6047 .Case("hexagonv5", "5") 6048 .Case("hexagonv55", "55") 6049 .Case("hexagonv60", "60") 6050 .Default(nullptr); 6051 } 6052 6053 bool setCPU(const std::string &Name) override { 6054 if (!getHexagonCPUSuffix(Name)) 6055 return false; 6056 CPU = Name; 6057 return true; 6058 } 6059 6060 int getEHDataRegisterNumber(unsigned RegNo) const override { 6061 return RegNo < 2 ? RegNo : -1; 6062 } 6063 }; 6064 6065 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6066 MacroBuilder &Builder) const { 6067 Builder.defineMacro("__qdsp6__", "1"); 6068 Builder.defineMacro("__hexagon__", "1"); 6069 6070 if (CPU == "hexagonv4") { 6071 Builder.defineMacro("__HEXAGON_V4__"); 6072 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6073 if (Opts.HexagonQdsp6Compat) { 6074 Builder.defineMacro("__QDSP6_V4__"); 6075 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6076 } 6077 } else if (CPU == "hexagonv5") { 6078 Builder.defineMacro("__HEXAGON_V5__"); 6079 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6080 if(Opts.HexagonQdsp6Compat) { 6081 Builder.defineMacro("__QDSP6_V5__"); 6082 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6083 } 6084 } else if (CPU == "hexagonv55") { 6085 Builder.defineMacro("__HEXAGON_V55__"); 6086 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6087 Builder.defineMacro("__QDSP6_V55__"); 6088 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6089 } else if (CPU == "hexagonv60") { 6090 Builder.defineMacro("__HEXAGON_V60__"); 6091 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6092 Builder.defineMacro("__QDSP6_V60__"); 6093 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6094 } 6095 6096 if (hasFeature("hvx")) { 6097 Builder.defineMacro("__HVX__"); 6098 if (hasFeature("hvx-double")) 6099 Builder.defineMacro("__HVXDBL__"); 6100 } 6101 } 6102 6103 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6104 DiagnosticsEngine &Diags) { 6105 for (auto &F : Features) { 6106 if (F == "+hvx") 6107 HasHVX = true; 6108 else if (F == "-hvx") 6109 HasHVX = HasHVXDouble = false; 6110 else if (F == "+hvx-double") 6111 HasHVX = HasHVXDouble = true; 6112 else if (F == "-hvx-double") 6113 HasHVXDouble = false; 6114 } 6115 return true; 6116 } 6117 6118 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6119 DiagnosticsEngine &Diags, StringRef CPU, 6120 const std::vector<std::string> &FeaturesVec) const { 6121 // Default for v60: -hvx, -hvx-double. 6122 Features["hvx"] = false; 6123 Features["hvx-double"] = false; 6124 6125 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6126 } 6127 6128 6129 const char *const HexagonTargetInfo::GCCRegNames[] = { 6130 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6131 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6132 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6133 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6134 "p0", "p1", "p2", "p3", 6135 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6136 }; 6137 6138 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6139 return llvm::makeArrayRef(GCCRegNames); 6140 } 6141 6142 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6143 { { "sp" }, "r29" }, 6144 { { "fp" }, "r30" }, 6145 { { "lr" }, "r31" }, 6146 }; 6147 6148 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6149 return llvm::makeArrayRef(GCCRegAliases); 6150 } 6151 6152 6153 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6154 #define BUILTIN(ID, TYPE, ATTRS) \ 6155 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6156 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6157 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6158 #include "clang/Basic/BuiltinsHexagon.def" 6159 }; 6160 6161 class LanaiTargetInfo : public TargetInfo { 6162 // Class for Lanai (32-bit). 6163 // The CPU profiles supported by the Lanai backend 6164 enum CPUKind { 6165 CK_NONE, 6166 CK_V11, 6167 } CPU; 6168 6169 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6170 static const char *const GCCRegNames[]; 6171 6172 public: 6173 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6174 : TargetInfo(Triple) { 6175 // Description string has to be kept in sync with backend. 6176 resetDataLayout("E" // Big endian 6177 "-m:e" // ELF name manging 6178 "-p:32:32" // 32 bit pointers, 32 bit aligned 6179 "-i64:64" // 64 bit integers, 64 bit aligned 6180 "-a:0:32" // 32 bit alignment of objects of aggregate type 6181 "-n32" // 32 bit native integer width 6182 "-S64" // 64 bit natural stack alignment 6183 ); 6184 6185 // Setting RegParmMax equal to what mregparm was set to in the old 6186 // toolchain 6187 RegParmMax = 4; 6188 6189 // Set the default CPU to V11 6190 CPU = CK_V11; 6191 6192 // Temporary approach to make everything at least word-aligned and allow for 6193 // safely casting between pointers with different alignment requirements. 6194 // TODO: Remove this when there are no more cast align warnings on the 6195 // firmware. 6196 MinGlobalAlign = 32; 6197 } 6198 6199 void getTargetDefines(const LangOptions &Opts, 6200 MacroBuilder &Builder) const override { 6201 // Define __lanai__ when building for target lanai. 6202 Builder.defineMacro("__lanai__"); 6203 6204 // Set define for the CPU specified. 6205 switch (CPU) { 6206 case CK_V11: 6207 Builder.defineMacro("__LANAI_V11__"); 6208 break; 6209 case CK_NONE: 6210 llvm_unreachable("Unhandled target CPU"); 6211 } 6212 } 6213 6214 bool setCPU(const std::string &Name) override { 6215 CPU = llvm::StringSwitch<CPUKind>(Name) 6216 .Case("v11", CK_V11) 6217 .Default(CK_NONE); 6218 6219 return CPU != CK_NONE; 6220 } 6221 6222 bool hasFeature(StringRef Feature) const override { 6223 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6224 } 6225 6226 ArrayRef<const char *> getGCCRegNames() const override; 6227 6228 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6229 6230 BuiltinVaListKind getBuiltinVaListKind() const override { 6231 return TargetInfo::VoidPtrBuiltinVaList; 6232 } 6233 6234 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6235 6236 bool validateAsmConstraint(const char *&Name, 6237 TargetInfo::ConstraintInfo &info) const override { 6238 return false; 6239 } 6240 6241 const char *getClobbers() const override { return ""; } 6242 }; 6243 6244 const char *const LanaiTargetInfo::GCCRegNames[] = { 6245 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6246 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6247 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6248 6249 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6250 return llvm::makeArrayRef(GCCRegNames); 6251 } 6252 6253 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6254 {{"pc"}, "r2"}, 6255 {{"sp"}, "r4"}, 6256 {{"fp"}, "r5"}, 6257 {{"rv"}, "r8"}, 6258 {{"rr1"}, "r10"}, 6259 {{"rr2"}, "r11"}, 6260 {{"rca"}, "r15"}, 6261 }; 6262 6263 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6264 return llvm::makeArrayRef(GCCRegAliases); 6265 } 6266 6267 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6268 class SparcTargetInfo : public TargetInfo { 6269 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6270 static const char * const GCCRegNames[]; 6271 bool SoftFloat; 6272 public: 6273 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6274 : TargetInfo(Triple), SoftFloat(false) {} 6275 6276 int getEHDataRegisterNumber(unsigned RegNo) const override { 6277 if (RegNo == 0) return 24; 6278 if (RegNo == 1) return 25; 6279 return -1; 6280 } 6281 6282 bool handleTargetFeatures(std::vector<std::string> &Features, 6283 DiagnosticsEngine &Diags) override { 6284 // The backend doesn't actually handle soft float yet, but in case someone 6285 // is using the support for the front end continue to support it. 6286 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6287 if (Feature != Features.end()) { 6288 SoftFloat = true; 6289 Features.erase(Feature); 6290 } 6291 return true; 6292 } 6293 void getTargetDefines(const LangOptions &Opts, 6294 MacroBuilder &Builder) const override { 6295 DefineStd(Builder, "sparc", Opts); 6296 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6297 6298 if (SoftFloat) 6299 Builder.defineMacro("SOFT_FLOAT", "1"); 6300 } 6301 6302 bool hasFeature(StringRef Feature) const override { 6303 return llvm::StringSwitch<bool>(Feature) 6304 .Case("softfloat", SoftFloat) 6305 .Case("sparc", true) 6306 .Default(false); 6307 } 6308 6309 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6310 // FIXME: Implement! 6311 return None; 6312 } 6313 BuiltinVaListKind getBuiltinVaListKind() const override { 6314 return TargetInfo::VoidPtrBuiltinVaList; 6315 } 6316 ArrayRef<const char *> getGCCRegNames() const override; 6317 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6318 bool validateAsmConstraint(const char *&Name, 6319 TargetInfo::ConstraintInfo &info) const override { 6320 // FIXME: Implement! 6321 switch (*Name) { 6322 case 'I': // Signed 13-bit constant 6323 case 'J': // Zero 6324 case 'K': // 32-bit constant with the low 12 bits clear 6325 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6326 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6327 case 'N': // Same as 'K' but zext (required for SIMode) 6328 case 'O': // The constant 4096 6329 return true; 6330 } 6331 return false; 6332 } 6333 const char *getClobbers() const override { 6334 // FIXME: Implement! 6335 return ""; 6336 } 6337 6338 // No Sparc V7 for now, the backend doesn't support it anyway. 6339 enum CPUKind { 6340 CK_GENERIC, 6341 CK_V8, 6342 CK_SUPERSPARC, 6343 CK_SPARCLITE, 6344 CK_F934, 6345 CK_HYPERSPARC, 6346 CK_SPARCLITE86X, 6347 CK_SPARCLET, 6348 CK_TSC701, 6349 CK_V9, 6350 CK_ULTRASPARC, 6351 CK_ULTRASPARC3, 6352 CK_NIAGARA, 6353 CK_NIAGARA2, 6354 CK_NIAGARA3, 6355 CK_NIAGARA4, 6356 CK_MYRIAD2_1, 6357 CK_MYRIAD2_2 6358 } CPU = CK_GENERIC; 6359 6360 enum CPUGeneration { 6361 CG_V8, 6362 CG_V9, 6363 }; 6364 6365 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6366 switch (Kind) { 6367 case CK_GENERIC: 6368 case CK_V8: 6369 case CK_SUPERSPARC: 6370 case CK_SPARCLITE: 6371 case CK_F934: 6372 case CK_HYPERSPARC: 6373 case CK_SPARCLITE86X: 6374 case CK_SPARCLET: 6375 case CK_TSC701: 6376 case CK_MYRIAD2_1: 6377 case CK_MYRIAD2_2: 6378 return CG_V8; 6379 case CK_V9: 6380 case CK_ULTRASPARC: 6381 case CK_ULTRASPARC3: 6382 case CK_NIAGARA: 6383 case CK_NIAGARA2: 6384 case CK_NIAGARA3: 6385 case CK_NIAGARA4: 6386 return CG_V9; 6387 } 6388 llvm_unreachable("Unexpected CPU kind"); 6389 } 6390 6391 CPUKind getCPUKind(StringRef Name) const { 6392 return llvm::StringSwitch<CPUKind>(Name) 6393 .Case("v8", CK_V8) 6394 .Case("supersparc", CK_SUPERSPARC) 6395 .Case("sparclite", CK_SPARCLITE) 6396 .Case("f934", CK_F934) 6397 .Case("hypersparc", CK_HYPERSPARC) 6398 .Case("sparclite86x", CK_SPARCLITE86X) 6399 .Case("sparclet", CK_SPARCLET) 6400 .Case("tsc701", CK_TSC701) 6401 .Case("v9", CK_V9) 6402 .Case("ultrasparc", CK_ULTRASPARC) 6403 .Case("ultrasparc3", CK_ULTRASPARC3) 6404 .Case("niagara", CK_NIAGARA) 6405 .Case("niagara2", CK_NIAGARA2) 6406 .Case("niagara3", CK_NIAGARA3) 6407 .Case("niagara4", CK_NIAGARA4) 6408 .Case("myriad2", CK_MYRIAD2_1) 6409 .Case("myriad2.1", CK_MYRIAD2_1) 6410 .Case("myriad2.2", CK_MYRIAD2_2) 6411 .Default(CK_GENERIC); 6412 } 6413 6414 bool setCPU(const std::string &Name) override { 6415 CPU = getCPUKind(Name); 6416 return CPU != CK_GENERIC; 6417 } 6418 }; 6419 6420 const char * const SparcTargetInfo::GCCRegNames[] = { 6421 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6422 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6423 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6424 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6425 }; 6426 6427 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6428 return llvm::makeArrayRef(GCCRegNames); 6429 } 6430 6431 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6432 { { "g0" }, "r0" }, 6433 { { "g1" }, "r1" }, 6434 { { "g2" }, "r2" }, 6435 { { "g3" }, "r3" }, 6436 { { "g4" }, "r4" }, 6437 { { "g5" }, "r5" }, 6438 { { "g6" }, "r6" }, 6439 { { "g7" }, "r7" }, 6440 { { "o0" }, "r8" }, 6441 { { "o1" }, "r9" }, 6442 { { "o2" }, "r10" }, 6443 { { "o3" }, "r11" }, 6444 { { "o4" }, "r12" }, 6445 { { "o5" }, "r13" }, 6446 { { "o6", "sp" }, "r14" }, 6447 { { "o7" }, "r15" }, 6448 { { "l0" }, "r16" }, 6449 { { "l1" }, "r17" }, 6450 { { "l2" }, "r18" }, 6451 { { "l3" }, "r19" }, 6452 { { "l4" }, "r20" }, 6453 { { "l5" }, "r21" }, 6454 { { "l6" }, "r22" }, 6455 { { "l7" }, "r23" }, 6456 { { "i0" }, "r24" }, 6457 { { "i1" }, "r25" }, 6458 { { "i2" }, "r26" }, 6459 { { "i3" }, "r27" }, 6460 { { "i4" }, "r28" }, 6461 { { "i5" }, "r29" }, 6462 { { "i6", "fp" }, "r30" }, 6463 { { "i7" }, "r31" }, 6464 }; 6465 6466 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6467 return llvm::makeArrayRef(GCCRegAliases); 6468 } 6469 6470 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6471 class SparcV8TargetInfo : public SparcTargetInfo { 6472 public: 6473 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6474 : SparcTargetInfo(Triple, Opts) { 6475 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6476 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6477 switch (getTriple().getOS()) { 6478 default: 6479 SizeType = UnsignedInt; 6480 IntPtrType = SignedInt; 6481 PtrDiffType = SignedInt; 6482 break; 6483 case llvm::Triple::NetBSD: 6484 case llvm::Triple::OpenBSD: 6485 SizeType = UnsignedLong; 6486 IntPtrType = SignedLong; 6487 PtrDiffType = SignedLong; 6488 break; 6489 } 6490 } 6491 6492 void getTargetDefines(const LangOptions &Opts, 6493 MacroBuilder &Builder) const override { 6494 SparcTargetInfo::getTargetDefines(Opts, Builder); 6495 switch (getCPUGeneration(CPU)) { 6496 case CG_V8: 6497 Builder.defineMacro("__sparcv8"); 6498 if (getTriple().getOS() != llvm::Triple::Solaris) 6499 Builder.defineMacro("__sparcv8__"); 6500 break; 6501 case CG_V9: 6502 Builder.defineMacro("__sparcv9"); 6503 if (getTriple().getOS() != llvm::Triple::Solaris) { 6504 Builder.defineMacro("__sparcv9__"); 6505 Builder.defineMacro("__sparc_v9__"); 6506 } 6507 break; 6508 } 6509 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6510 switch (CPU) { 6511 case CK_MYRIAD2_1: 6512 Builder.defineMacro("__myriad2", "1"); 6513 Builder.defineMacro("__myriad2__", "1"); 6514 break; 6515 case CK_MYRIAD2_2: 6516 Builder.defineMacro("__myriad2", "2"); 6517 Builder.defineMacro("__myriad2__", "2"); 6518 break; 6519 default: 6520 break; 6521 } 6522 } 6523 } 6524 6525 bool hasSjLjLowering() const override { 6526 return true; 6527 } 6528 }; 6529 6530 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6531 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6532 public: 6533 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6534 : SparcV8TargetInfo(Triple, Opts) { 6535 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6536 BigEndian = false; 6537 } 6538 }; 6539 6540 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6541 class SparcV9TargetInfo : public SparcTargetInfo { 6542 public: 6543 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6544 : SparcTargetInfo(Triple, Opts) { 6545 // FIXME: Support Sparc quad-precision long double? 6546 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6547 // This is an LP64 platform. 6548 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6549 6550 // OpenBSD uses long long for int64_t and intmax_t. 6551 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6552 IntMaxType = SignedLongLong; 6553 else 6554 IntMaxType = SignedLong; 6555 Int64Type = IntMaxType; 6556 6557 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6558 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6559 LongDoubleWidth = 128; 6560 LongDoubleAlign = 128; 6561 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6562 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6563 } 6564 6565 void getTargetDefines(const LangOptions &Opts, 6566 MacroBuilder &Builder) const override { 6567 SparcTargetInfo::getTargetDefines(Opts, Builder); 6568 Builder.defineMacro("__sparcv9"); 6569 Builder.defineMacro("__arch64__"); 6570 // Solaris doesn't need these variants, but the BSDs do. 6571 if (getTriple().getOS() != llvm::Triple::Solaris) { 6572 Builder.defineMacro("__sparc64__"); 6573 Builder.defineMacro("__sparc_v9__"); 6574 Builder.defineMacro("__sparcv9__"); 6575 } 6576 } 6577 6578 bool setCPU(const std::string &Name) override { 6579 if (!SparcTargetInfo::setCPU(Name)) 6580 return false; 6581 return getCPUGeneration(CPU) == CG_V9; 6582 } 6583 }; 6584 6585 class SystemZTargetInfo : public TargetInfo { 6586 static const Builtin::Info BuiltinInfo[]; 6587 static const char *const GCCRegNames[]; 6588 std::string CPU; 6589 bool HasTransactionalExecution; 6590 bool HasVector; 6591 6592 public: 6593 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6594 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6595 HasVector(false) { 6596 IntMaxType = SignedLong; 6597 Int64Type = SignedLong; 6598 TLSSupported = true; 6599 IntWidth = IntAlign = 32; 6600 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6601 PointerWidth = PointerAlign = 64; 6602 LongDoubleWidth = 128; 6603 LongDoubleAlign = 64; 6604 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6605 DefaultAlignForAttributeAligned = 64; 6606 MinGlobalAlign = 16; 6607 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 6608 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6609 } 6610 void getTargetDefines(const LangOptions &Opts, 6611 MacroBuilder &Builder) const override { 6612 Builder.defineMacro("__s390__"); 6613 Builder.defineMacro("__s390x__"); 6614 Builder.defineMacro("__zarch__"); 6615 Builder.defineMacro("__LONG_DOUBLE_128__"); 6616 6617 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6618 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6619 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6620 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6621 6622 if (HasTransactionalExecution) 6623 Builder.defineMacro("__HTM__"); 6624 if (Opts.ZVector) 6625 Builder.defineMacro("__VEC__", "10301"); 6626 } 6627 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6628 return llvm::makeArrayRef(BuiltinInfo, 6629 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6630 } 6631 6632 ArrayRef<const char *> getGCCRegNames() const override; 6633 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6634 // No aliases. 6635 return None; 6636 } 6637 bool validateAsmConstraint(const char *&Name, 6638 TargetInfo::ConstraintInfo &info) const override; 6639 const char *getClobbers() const override { 6640 // FIXME: Is this really right? 6641 return ""; 6642 } 6643 BuiltinVaListKind getBuiltinVaListKind() const override { 6644 return TargetInfo::SystemZBuiltinVaList; 6645 } 6646 bool setCPU(const std::string &Name) override { 6647 CPU = Name; 6648 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6649 .Case("z10", true) 6650 .Case("z196", true) 6651 .Case("zEC12", true) 6652 .Case("z13", true) 6653 .Default(false); 6654 6655 return CPUKnown; 6656 } 6657 bool 6658 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6659 StringRef CPU, 6660 const std::vector<std::string> &FeaturesVec) const override { 6661 if (CPU == "zEC12") 6662 Features["transactional-execution"] = true; 6663 if (CPU == "z13") { 6664 Features["transactional-execution"] = true; 6665 Features["vector"] = true; 6666 } 6667 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6668 } 6669 6670 bool handleTargetFeatures(std::vector<std::string> &Features, 6671 DiagnosticsEngine &Diags) override { 6672 HasTransactionalExecution = false; 6673 for (const auto &Feature : Features) { 6674 if (Feature == "+transactional-execution") 6675 HasTransactionalExecution = true; 6676 else if (Feature == "+vector") 6677 HasVector = true; 6678 } 6679 // If we use the vector ABI, vector types are 64-bit aligned. 6680 if (HasVector) { 6681 MaxVectorAlign = 64; 6682 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6683 "-v128:64-a:8:16-n32:64"); 6684 } 6685 return true; 6686 } 6687 6688 bool hasFeature(StringRef Feature) const override { 6689 return llvm::StringSwitch<bool>(Feature) 6690 .Case("systemz", true) 6691 .Case("htm", HasTransactionalExecution) 6692 .Case("vx", HasVector) 6693 .Default(false); 6694 } 6695 6696 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6697 switch (CC) { 6698 case CC_C: 6699 case CC_Swift: 6700 return CCCR_OK; 6701 default: 6702 return CCCR_Warning; 6703 } 6704 } 6705 6706 StringRef getABI() const override { 6707 if (HasVector) 6708 return "vector"; 6709 return ""; 6710 } 6711 6712 bool useFloat128ManglingForLongDouble() const override { 6713 return true; 6714 } 6715 }; 6716 6717 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6718 #define BUILTIN(ID, TYPE, ATTRS) \ 6719 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6720 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 6721 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 6722 #include "clang/Basic/BuiltinsSystemZ.def" 6723 }; 6724 6725 const char *const SystemZTargetInfo::GCCRegNames[] = { 6726 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6727 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6728 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6729 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6730 }; 6731 6732 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6733 return llvm::makeArrayRef(GCCRegNames); 6734 } 6735 6736 bool SystemZTargetInfo:: 6737 validateAsmConstraint(const char *&Name, 6738 TargetInfo::ConstraintInfo &Info) const { 6739 switch (*Name) { 6740 default: 6741 return false; 6742 6743 case 'a': // Address register 6744 case 'd': // Data register (equivalent to 'r') 6745 case 'f': // Floating-point register 6746 Info.setAllowsRegister(); 6747 return true; 6748 6749 case 'I': // Unsigned 8-bit constant 6750 case 'J': // Unsigned 12-bit constant 6751 case 'K': // Signed 16-bit constant 6752 case 'L': // Signed 20-bit displacement (on all targets we support) 6753 case 'M': // 0x7fffffff 6754 return true; 6755 6756 case 'Q': // Memory with base and unsigned 12-bit displacement 6757 case 'R': // Likewise, plus an index 6758 case 'S': // Memory with base and signed 20-bit displacement 6759 case 'T': // Likewise, plus an index 6760 Info.setAllowsMemory(); 6761 return true; 6762 } 6763 } 6764 6765 class MSP430TargetInfo : public TargetInfo { 6766 static const char *const GCCRegNames[]; 6767 6768 public: 6769 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6770 : TargetInfo(Triple) { 6771 BigEndian = false; 6772 TLSSupported = false; 6773 IntWidth = 16; 6774 IntAlign = 16; 6775 LongWidth = 32; 6776 LongLongWidth = 64; 6777 LongAlign = LongLongAlign = 16; 6778 PointerWidth = 16; 6779 PointerAlign = 16; 6780 SuitableAlign = 16; 6781 SizeType = UnsignedInt; 6782 IntMaxType = SignedLongLong; 6783 IntPtrType = SignedInt; 6784 PtrDiffType = SignedInt; 6785 SigAtomicType = SignedLong; 6786 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 6787 } 6788 void getTargetDefines(const LangOptions &Opts, 6789 MacroBuilder &Builder) const override { 6790 Builder.defineMacro("MSP430"); 6791 Builder.defineMacro("__MSP430__"); 6792 // FIXME: defines for different 'flavours' of MCU 6793 } 6794 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6795 // FIXME: Implement. 6796 return None; 6797 } 6798 bool hasFeature(StringRef Feature) const override { 6799 return Feature == "msp430"; 6800 } 6801 ArrayRef<const char *> getGCCRegNames() const override; 6802 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6803 // No aliases. 6804 return None; 6805 } 6806 bool validateAsmConstraint(const char *&Name, 6807 TargetInfo::ConstraintInfo &info) const override { 6808 // FIXME: implement 6809 switch (*Name) { 6810 case 'K': // the constant 1 6811 case 'L': // constant -1^20 .. 1^19 6812 case 'M': // constant 1-4: 6813 return true; 6814 } 6815 // No target constraints for now. 6816 return false; 6817 } 6818 const char *getClobbers() const override { 6819 // FIXME: Is this really right? 6820 return ""; 6821 } 6822 BuiltinVaListKind getBuiltinVaListKind() const override { 6823 // FIXME: implement 6824 return TargetInfo::CharPtrBuiltinVaList; 6825 } 6826 }; 6827 6828 const char *const MSP430TargetInfo::GCCRegNames[] = { 6829 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6830 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6831 6832 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 6833 return llvm::makeArrayRef(GCCRegNames); 6834 } 6835 6836 // LLVM and Clang cannot be used directly to output native binaries for 6837 // target, but is used to compile C code to llvm bitcode with correct 6838 // type and alignment information. 6839 // 6840 // TCE uses the llvm bitcode as input and uses it for generating customized 6841 // target processor and program binary. TCE co-design environment is 6842 // publicly available in http://tce.cs.tut.fi 6843 6844 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6845 3, // opencl_global 6846 4, // opencl_local 6847 5, // opencl_constant 6848 // FIXME: generic has to be added to the target 6849 0, // opencl_generic 6850 0, // cuda_device 6851 0, // cuda_constant 6852 0 // cuda_shared 6853 }; 6854 6855 class TCETargetInfo : public TargetInfo { 6856 public: 6857 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6858 : TargetInfo(Triple) { 6859 TLSSupported = false; 6860 IntWidth = 32; 6861 LongWidth = LongLongWidth = 32; 6862 PointerWidth = 32; 6863 IntAlign = 32; 6864 LongAlign = LongLongAlign = 32; 6865 PointerAlign = 32; 6866 SuitableAlign = 32; 6867 SizeType = UnsignedInt; 6868 IntMaxType = SignedLong; 6869 IntPtrType = SignedInt; 6870 PtrDiffType = SignedInt; 6871 FloatWidth = 32; 6872 FloatAlign = 32; 6873 DoubleWidth = 32; 6874 DoubleAlign = 32; 6875 LongDoubleWidth = 32; 6876 LongDoubleAlign = 32; 6877 FloatFormat = &llvm::APFloat::IEEEsingle; 6878 DoubleFormat = &llvm::APFloat::IEEEsingle; 6879 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6880 resetDataLayout("E-p:32:32-i8:8:32-i16:16:32-i64:32" 6881 "-f64:32-v64:32-v128:32-a:0:32-n32"); 6882 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6883 UseAddrSpaceMapMangling = true; 6884 } 6885 6886 void getTargetDefines(const LangOptions &Opts, 6887 MacroBuilder &Builder) const override { 6888 DefineStd(Builder, "tce", Opts); 6889 Builder.defineMacro("__TCE__"); 6890 Builder.defineMacro("__TCE_V1__"); 6891 } 6892 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 6893 6894 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6895 const char *getClobbers() const override { return ""; } 6896 BuiltinVaListKind getBuiltinVaListKind() const override { 6897 return TargetInfo::VoidPtrBuiltinVaList; 6898 } 6899 ArrayRef<const char *> getGCCRegNames() const override { return None; } 6900 bool validateAsmConstraint(const char *&Name, 6901 TargetInfo::ConstraintInfo &info) const override { 6902 return true; 6903 } 6904 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6905 return None; 6906 } 6907 }; 6908 6909 class BPFTargetInfo : public TargetInfo { 6910 public: 6911 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6912 : TargetInfo(Triple) { 6913 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6914 SizeType = UnsignedLong; 6915 PtrDiffType = SignedLong; 6916 IntPtrType = SignedLong; 6917 IntMaxType = SignedLong; 6918 Int64Type = SignedLong; 6919 RegParmMax = 5; 6920 if (Triple.getArch() == llvm::Triple::bpfeb) { 6921 BigEndian = true; 6922 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 6923 } else { 6924 BigEndian = false; 6925 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 6926 } 6927 MaxAtomicPromoteWidth = 64; 6928 MaxAtomicInlineWidth = 64; 6929 TLSSupported = false; 6930 } 6931 void getTargetDefines(const LangOptions &Opts, 6932 MacroBuilder &Builder) const override { 6933 DefineStd(Builder, "bpf", Opts); 6934 Builder.defineMacro("__BPF__"); 6935 } 6936 bool hasFeature(StringRef Feature) const override { 6937 return Feature == "bpf"; 6938 } 6939 6940 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6941 const char *getClobbers() const override { 6942 return ""; 6943 } 6944 BuiltinVaListKind getBuiltinVaListKind() const override { 6945 return TargetInfo::VoidPtrBuiltinVaList; 6946 } 6947 ArrayRef<const char *> getGCCRegNames() const override { 6948 return None; 6949 } 6950 bool validateAsmConstraint(const char *&Name, 6951 TargetInfo::ConstraintInfo &info) const override { 6952 return true; 6953 } 6954 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6955 return None; 6956 } 6957 }; 6958 6959 class MipsTargetInfoBase : public TargetInfo { 6960 virtual void setDataLayout() = 0; 6961 6962 static const Builtin::Info BuiltinInfo[]; 6963 std::string CPU; 6964 bool IsMips16; 6965 bool IsMicromips; 6966 bool IsNan2008; 6967 bool IsSingleFloat; 6968 enum MipsFloatABI { 6969 HardFloat, SoftFloat 6970 } FloatABI; 6971 enum DspRevEnum { 6972 NoDSP, DSP1, DSP2 6973 } DspRev; 6974 bool HasMSA; 6975 6976 protected: 6977 bool HasFP64; 6978 std::string ABI; 6979 6980 public: 6981 MipsTargetInfoBase(const llvm::Triple &Triple, const TargetOptions &, 6982 const std::string &ABIStr, const std::string &CPUStr) 6983 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6984 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6985 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6986 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6987 } 6988 6989 bool isNaN2008Default() const { 6990 return CPU == "mips32r6" || CPU == "mips64r6"; 6991 } 6992 6993 bool isFP64Default() const { 6994 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6995 } 6996 6997 bool isNan2008() const override { 6998 return IsNan2008; 6999 } 7000 7001 StringRef getABI() const override { return ABI; } 7002 bool setCPU(const std::string &Name) override { 7003 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 7004 getTriple().getArch() == llvm::Triple::mipsel; 7005 CPU = Name; 7006 return llvm::StringSwitch<bool>(Name) 7007 .Case("mips1", IsMips32) 7008 .Case("mips2", IsMips32) 7009 .Case("mips3", true) 7010 .Case("mips4", true) 7011 .Case("mips5", true) 7012 .Case("mips32", IsMips32) 7013 .Case("mips32r2", IsMips32) 7014 .Case("mips32r3", IsMips32) 7015 .Case("mips32r5", IsMips32) 7016 .Case("mips32r6", IsMips32) 7017 .Case("mips64", true) 7018 .Case("mips64r2", true) 7019 .Case("mips64r3", true) 7020 .Case("mips64r5", true) 7021 .Case("mips64r6", true) 7022 .Case("octeon", true) 7023 .Case("p5600", true) 7024 .Default(false); 7025 } 7026 const std::string& getCPU() const { return CPU; } 7027 bool 7028 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7029 StringRef CPU, 7030 const std::vector<std::string> &FeaturesVec) const override { 7031 if (CPU.empty()) 7032 CPU = getCPU(); 7033 if (CPU == "octeon") 7034 Features["mips64r2"] = Features["cnmips"] = true; 7035 else 7036 Features[CPU] = true; 7037 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7038 } 7039 7040 void getTargetDefines(const LangOptions &Opts, 7041 MacroBuilder &Builder) const override { 7042 Builder.defineMacro("__mips__"); 7043 Builder.defineMacro("_mips"); 7044 if (Opts.GNUMode) 7045 Builder.defineMacro("mips"); 7046 7047 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7048 7049 switch (FloatABI) { 7050 case HardFloat: 7051 Builder.defineMacro("__mips_hard_float", Twine(1)); 7052 break; 7053 case SoftFloat: 7054 Builder.defineMacro("__mips_soft_float", Twine(1)); 7055 break; 7056 } 7057 7058 if (IsSingleFloat) 7059 Builder.defineMacro("__mips_single_float", Twine(1)); 7060 7061 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7062 Builder.defineMacro("_MIPS_FPSET", 7063 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7064 7065 if (IsMips16) 7066 Builder.defineMacro("__mips16", Twine(1)); 7067 7068 if (IsMicromips) 7069 Builder.defineMacro("__mips_micromips", Twine(1)); 7070 7071 if (IsNan2008) 7072 Builder.defineMacro("__mips_nan2008", Twine(1)); 7073 7074 switch (DspRev) { 7075 default: 7076 break; 7077 case DSP1: 7078 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7079 Builder.defineMacro("__mips_dsp", Twine(1)); 7080 break; 7081 case DSP2: 7082 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7083 Builder.defineMacro("__mips_dspr2", Twine(1)); 7084 Builder.defineMacro("__mips_dsp", Twine(1)); 7085 break; 7086 } 7087 7088 if (HasMSA) 7089 Builder.defineMacro("__mips_msa", Twine(1)); 7090 7091 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7092 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7093 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7094 7095 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7096 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7097 7098 // These shouldn't be defined for MIPS-I but there's no need to check 7099 // for that since MIPS-I isn't supported. 7100 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7101 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7102 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7103 } 7104 7105 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7106 return llvm::makeArrayRef(BuiltinInfo, 7107 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7108 } 7109 bool hasFeature(StringRef Feature) const override { 7110 return llvm::StringSwitch<bool>(Feature) 7111 .Case("mips", true) 7112 .Case("fp64", HasFP64) 7113 .Default(false); 7114 } 7115 BuiltinVaListKind getBuiltinVaListKind() const override { 7116 return TargetInfo::VoidPtrBuiltinVaList; 7117 } 7118 ArrayRef<const char *> getGCCRegNames() const override { 7119 static const char *const GCCRegNames[] = { 7120 // CPU register names 7121 // Must match second column of GCCRegAliases 7122 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7123 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7124 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7125 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7126 // Floating point register names 7127 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7128 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7129 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7130 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7131 // Hi/lo and condition register names 7132 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7133 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7134 "$ac3hi","$ac3lo", 7135 // MSA register names 7136 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7137 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7138 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7139 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7140 // MSA control register names 7141 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7142 "$msarequest", "$msamap", "$msaunmap" 7143 }; 7144 return llvm::makeArrayRef(GCCRegNames); 7145 } 7146 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override = 0; 7147 bool validateAsmConstraint(const char *&Name, 7148 TargetInfo::ConstraintInfo &Info) const override { 7149 switch (*Name) { 7150 default: 7151 return false; 7152 case 'r': // CPU registers. 7153 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7154 case 'y': // Equivalent to "r", backward compatibility only. 7155 case 'f': // floating-point registers. 7156 case 'c': // $25 for indirect jumps 7157 case 'l': // lo register 7158 case 'x': // hilo register pair 7159 Info.setAllowsRegister(); 7160 return true; 7161 case 'I': // Signed 16-bit constant 7162 case 'J': // Integer 0 7163 case 'K': // Unsigned 16-bit constant 7164 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7165 case 'M': // Constants not loadable via lui, addiu, or ori 7166 case 'N': // Constant -1 to -65535 7167 case 'O': // A signed 15-bit constant 7168 case 'P': // A constant between 1 go 65535 7169 return true; 7170 case 'R': // An address that can be used in a non-macro load or store 7171 Info.setAllowsMemory(); 7172 return true; 7173 case 'Z': 7174 if (Name[1] == 'C') { // An address usable by ll, and sc. 7175 Info.setAllowsMemory(); 7176 Name++; // Skip over 'Z'. 7177 return true; 7178 } 7179 return false; 7180 } 7181 } 7182 7183 std::string convertConstraint(const char *&Constraint) const override { 7184 std::string R; 7185 switch (*Constraint) { 7186 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7187 if (Constraint[1] == 'C') { 7188 R = std::string("^") + std::string(Constraint, 2); 7189 Constraint++; 7190 return R; 7191 } 7192 break; 7193 } 7194 return TargetInfo::convertConstraint(Constraint); 7195 } 7196 7197 const char *getClobbers() const override { 7198 // In GCC, $1 is not widely used in generated code (it's used only in a few 7199 // specific situations), so there is no real need for users to add it to 7200 // the clobbers list if they want to use it in their inline assembly code. 7201 // 7202 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7203 // code generation, so using it in inline assembly without adding it to the 7204 // clobbers list can cause conflicts between the inline assembly code and 7205 // the surrounding generated code. 7206 // 7207 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7208 // operands, which will conflict with the ".set at" assembler option (which 7209 // we use only for inline assembly, in order to maintain compatibility with 7210 // GCC) and will also conflict with the user's usage of $1. 7211 // 7212 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7213 // register for generated code is to automatically clobber $1 for all inline 7214 // assembly code. 7215 // 7216 // FIXME: We should automatically clobber $1 only for inline assembly code 7217 // which actually uses it. This would allow LLVM to use $1 for inline 7218 // assembly operands if the user's assembly code doesn't use it. 7219 return "~{$1}"; 7220 } 7221 7222 bool handleTargetFeatures(std::vector<std::string> &Features, 7223 DiagnosticsEngine &Diags) override { 7224 IsMips16 = false; 7225 IsMicromips = false; 7226 IsNan2008 = isNaN2008Default(); 7227 IsSingleFloat = false; 7228 FloatABI = HardFloat; 7229 DspRev = NoDSP; 7230 HasFP64 = isFP64Default(); 7231 7232 for (const auto &Feature : Features) { 7233 if (Feature == "+single-float") 7234 IsSingleFloat = true; 7235 else if (Feature == "+soft-float") 7236 FloatABI = SoftFloat; 7237 else if (Feature == "+mips16") 7238 IsMips16 = true; 7239 else if (Feature == "+micromips") 7240 IsMicromips = true; 7241 else if (Feature == "+dsp") 7242 DspRev = std::max(DspRev, DSP1); 7243 else if (Feature == "+dspr2") 7244 DspRev = std::max(DspRev, DSP2); 7245 else if (Feature == "+msa") 7246 HasMSA = true; 7247 else if (Feature == "+fp64") 7248 HasFP64 = true; 7249 else if (Feature == "-fp64") 7250 HasFP64 = false; 7251 else if (Feature == "+nan2008") 7252 IsNan2008 = true; 7253 else if (Feature == "-nan2008") 7254 IsNan2008 = false; 7255 } 7256 7257 setDataLayout(); 7258 7259 return true; 7260 } 7261 7262 int getEHDataRegisterNumber(unsigned RegNo) const override { 7263 if (RegNo == 0) return 4; 7264 if (RegNo == 1) return 5; 7265 return -1; 7266 } 7267 7268 bool isCLZForZeroUndef() const override { return false; } 7269 }; 7270 7271 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 7272 #define BUILTIN(ID, TYPE, ATTRS) \ 7273 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7274 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7275 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7276 #include "clang/Basic/BuiltinsMips.def" 7277 }; 7278 7279 class Mips32TargetInfoBase : public MipsTargetInfoBase { 7280 public: 7281 Mips32TargetInfoBase(const llvm::Triple &Triple, const TargetOptions &Opts) 7282 : MipsTargetInfoBase(Triple, Opts, "o32", "mips32r2") { 7283 SizeType = UnsignedInt; 7284 PtrDiffType = SignedInt; 7285 Int64Type = SignedLongLong; 7286 IntMaxType = Int64Type; 7287 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7288 } 7289 bool setABI(const std::string &Name) override { 7290 if (Name == "o32" || Name == "eabi") { 7291 ABI = Name; 7292 return true; 7293 } 7294 return false; 7295 } 7296 void getTargetDefines(const LangOptions &Opts, 7297 MacroBuilder &Builder) const override { 7298 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 7299 7300 Builder.defineMacro("__mips", "32"); 7301 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7302 7303 const std::string& CPUStr = getCPU(); 7304 if (CPUStr == "mips32") 7305 Builder.defineMacro("__mips_isa_rev", "1"); 7306 else if (CPUStr == "mips32r2") 7307 Builder.defineMacro("__mips_isa_rev", "2"); 7308 else if (CPUStr == "mips32r3") 7309 Builder.defineMacro("__mips_isa_rev", "3"); 7310 else if (CPUStr == "mips32r5") 7311 Builder.defineMacro("__mips_isa_rev", "5"); 7312 else if (CPUStr == "mips32r6") 7313 Builder.defineMacro("__mips_isa_rev", "6"); 7314 7315 if (ABI == "o32") { 7316 Builder.defineMacro("__mips_o32"); 7317 Builder.defineMacro("_ABIO32", "1"); 7318 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7319 } 7320 else if (ABI == "eabi") 7321 Builder.defineMacro("__mips_eabi"); 7322 else 7323 llvm_unreachable("Invalid ABI for Mips32."); 7324 } 7325 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7326 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 7327 { { "at" }, "$1" }, 7328 { { "v0" }, "$2" }, 7329 { { "v1" }, "$3" }, 7330 { { "a0" }, "$4" }, 7331 { { "a1" }, "$5" }, 7332 { { "a2" }, "$6" }, 7333 { { "a3" }, "$7" }, 7334 { { "t0" }, "$8" }, 7335 { { "t1" }, "$9" }, 7336 { { "t2" }, "$10" }, 7337 { { "t3" }, "$11" }, 7338 { { "t4" }, "$12" }, 7339 { { "t5" }, "$13" }, 7340 { { "t6" }, "$14" }, 7341 { { "t7" }, "$15" }, 7342 { { "s0" }, "$16" }, 7343 { { "s1" }, "$17" }, 7344 { { "s2" }, "$18" }, 7345 { { "s3" }, "$19" }, 7346 { { "s4" }, "$20" }, 7347 { { "s5" }, "$21" }, 7348 { { "s6" }, "$22" }, 7349 { { "s7" }, "$23" }, 7350 { { "t8" }, "$24" }, 7351 { { "t9" }, "$25" }, 7352 { { "k0" }, "$26" }, 7353 { { "k1" }, "$27" }, 7354 { { "gp" }, "$28" }, 7355 { { "sp","$sp" }, "$29" }, 7356 { { "fp","$fp" }, "$30" }, 7357 { { "ra" }, "$31" } 7358 }; 7359 return llvm::makeArrayRef(GCCRegAliases); 7360 } 7361 }; 7362 7363 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 7364 void setDataLayout() override { 7365 resetDataLayout("E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"); 7366 } 7367 7368 public: 7369 Mips32EBTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7370 : Mips32TargetInfoBase(Triple, Opts) { 7371 } 7372 void getTargetDefines(const LangOptions &Opts, 7373 MacroBuilder &Builder) const override { 7374 DefineStd(Builder, "MIPSEB", Opts); 7375 Builder.defineMacro("_MIPSEB"); 7376 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 7377 } 7378 }; 7379 7380 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 7381 void setDataLayout() override { 7382 resetDataLayout("e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"); 7383 } 7384 7385 public: 7386 Mips32ELTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7387 : Mips32TargetInfoBase(Triple, Opts) { 7388 BigEndian = false; 7389 } 7390 void getTargetDefines(const LangOptions &Opts, 7391 MacroBuilder &Builder) const override { 7392 DefineStd(Builder, "MIPSEL", Opts); 7393 Builder.defineMacro("_MIPSEL"); 7394 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 7395 } 7396 }; 7397 7398 class Mips64TargetInfoBase : public MipsTargetInfoBase { 7399 public: 7400 Mips64TargetInfoBase(const llvm::Triple &Triple, const TargetOptions &Opts) 7401 : MipsTargetInfoBase(Triple, Opts, "n64", "mips64r2") { 7402 LongDoubleWidth = LongDoubleAlign = 128; 7403 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7404 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7405 LongDoubleWidth = LongDoubleAlign = 64; 7406 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7407 } 7408 setN64ABITypes(); 7409 SuitableAlign = 128; 7410 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7411 } 7412 7413 void setN64ABITypes() { 7414 LongWidth = LongAlign = 64; 7415 PointerWidth = PointerAlign = 64; 7416 SizeType = UnsignedLong; 7417 PtrDiffType = SignedLong; 7418 Int64Type = SignedLong; 7419 IntMaxType = Int64Type; 7420 } 7421 7422 void setN32ABITypes() { 7423 LongWidth = LongAlign = 32; 7424 PointerWidth = PointerAlign = 32; 7425 SizeType = UnsignedInt; 7426 PtrDiffType = SignedInt; 7427 Int64Type = SignedLongLong; 7428 IntMaxType = Int64Type; 7429 } 7430 7431 bool setABI(const std::string &Name) override { 7432 if (Name == "n32") { 7433 setN32ABITypes(); 7434 ABI = Name; 7435 return true; 7436 } 7437 if (Name == "n64") { 7438 setN64ABITypes(); 7439 ABI = Name; 7440 return true; 7441 } 7442 return false; 7443 } 7444 7445 void getTargetDefines(const LangOptions &Opts, 7446 MacroBuilder &Builder) const override { 7447 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 7448 7449 Builder.defineMacro("__mips", "64"); 7450 Builder.defineMacro("__mips64"); 7451 Builder.defineMacro("__mips64__"); 7452 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7453 7454 const std::string& CPUStr = getCPU(); 7455 if (CPUStr == "mips64") 7456 Builder.defineMacro("__mips_isa_rev", "1"); 7457 else if (CPUStr == "mips64r2") 7458 Builder.defineMacro("__mips_isa_rev", "2"); 7459 else if (CPUStr == "mips64r3") 7460 Builder.defineMacro("__mips_isa_rev", "3"); 7461 else if (CPUStr == "mips64r5") 7462 Builder.defineMacro("__mips_isa_rev", "5"); 7463 else if (CPUStr == "mips64r6") 7464 Builder.defineMacro("__mips_isa_rev", "6"); 7465 7466 if (ABI == "n32") { 7467 Builder.defineMacro("__mips_n32"); 7468 Builder.defineMacro("_ABIN32", "2"); 7469 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7470 } 7471 else if (ABI == "n64") { 7472 Builder.defineMacro("__mips_n64"); 7473 Builder.defineMacro("_ABI64", "3"); 7474 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7475 } 7476 else 7477 llvm_unreachable("Invalid ABI for Mips64."); 7478 7479 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7480 } 7481 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7482 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 7483 { { "at" }, "$1" }, 7484 { { "v0" }, "$2" }, 7485 { { "v1" }, "$3" }, 7486 { { "a0" }, "$4" }, 7487 { { "a1" }, "$5" }, 7488 { { "a2" }, "$6" }, 7489 { { "a3" }, "$7" }, 7490 { { "a4" }, "$8" }, 7491 { { "a5" }, "$9" }, 7492 { { "a6" }, "$10" }, 7493 { { "a7" }, "$11" }, 7494 { { "t0" }, "$12" }, 7495 { { "t1" }, "$13" }, 7496 { { "t2" }, "$14" }, 7497 { { "t3" }, "$15" }, 7498 { { "s0" }, "$16" }, 7499 { { "s1" }, "$17" }, 7500 { { "s2" }, "$18" }, 7501 { { "s3" }, "$19" }, 7502 { { "s4" }, "$20" }, 7503 { { "s5" }, "$21" }, 7504 { { "s6" }, "$22" }, 7505 { { "s7" }, "$23" }, 7506 { { "t8" }, "$24" }, 7507 { { "t9" }, "$25" }, 7508 { { "k0" }, "$26" }, 7509 { { "k1" }, "$27" }, 7510 { { "gp" }, "$28" }, 7511 { { "sp","$sp" }, "$29" }, 7512 { { "fp","$fp" }, "$30" }, 7513 { { "ra" }, "$31" } 7514 }; 7515 return llvm::makeArrayRef(GCCRegAliases); 7516 } 7517 7518 bool hasInt128Type() const override { return true; } 7519 }; 7520 7521 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 7522 void setDataLayout() override { 7523 if (ABI == "n32") 7524 resetDataLayout("E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7525 else 7526 resetDataLayout("E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7527 } 7528 7529 public: 7530 Mips64EBTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7531 : Mips64TargetInfoBase(Triple, Opts) {} 7532 void getTargetDefines(const LangOptions &Opts, 7533 MacroBuilder &Builder) const override { 7534 DefineStd(Builder, "MIPSEB", Opts); 7535 Builder.defineMacro("_MIPSEB"); 7536 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7537 } 7538 }; 7539 7540 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 7541 void setDataLayout() override { 7542 if (ABI == "n32") 7543 resetDataLayout("e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7544 else 7545 resetDataLayout("e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7546 } 7547 public: 7548 Mips64ELTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7549 : Mips64TargetInfoBase(Triple, Opts) { 7550 // Default ABI is n64. 7551 BigEndian = false; 7552 } 7553 void getTargetDefines(const LangOptions &Opts, 7554 MacroBuilder &Builder) const override { 7555 DefineStd(Builder, "MIPSEL", Opts); 7556 Builder.defineMacro("_MIPSEL"); 7557 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7558 } 7559 }; 7560 7561 class PNaClTargetInfo : public TargetInfo { 7562 public: 7563 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7564 : TargetInfo(Triple) { 7565 BigEndian = false; 7566 this->LongAlign = 32; 7567 this->LongWidth = 32; 7568 this->PointerAlign = 32; 7569 this->PointerWidth = 32; 7570 this->IntMaxType = TargetInfo::SignedLongLong; 7571 this->Int64Type = TargetInfo::SignedLongLong; 7572 this->DoubleAlign = 64; 7573 this->LongDoubleWidth = 64; 7574 this->LongDoubleAlign = 64; 7575 this->SizeType = TargetInfo::UnsignedInt; 7576 this->PtrDiffType = TargetInfo::SignedInt; 7577 this->IntPtrType = TargetInfo::SignedInt; 7578 this->RegParmMax = 0; // Disallow regparm 7579 } 7580 7581 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7582 Builder.defineMacro("__le32__"); 7583 Builder.defineMacro("__pnacl__"); 7584 } 7585 void getTargetDefines(const LangOptions &Opts, 7586 MacroBuilder &Builder) const override { 7587 getArchDefines(Opts, Builder); 7588 } 7589 bool hasFeature(StringRef Feature) const override { 7590 return Feature == "pnacl"; 7591 } 7592 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7593 BuiltinVaListKind getBuiltinVaListKind() const override { 7594 return TargetInfo::PNaClABIBuiltinVaList; 7595 } 7596 ArrayRef<const char *> getGCCRegNames() const override; 7597 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7598 bool validateAsmConstraint(const char *&Name, 7599 TargetInfo::ConstraintInfo &Info) const override { 7600 return false; 7601 } 7602 7603 const char *getClobbers() const override { 7604 return ""; 7605 } 7606 }; 7607 7608 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7609 return None; 7610 } 7611 7612 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7613 return None; 7614 } 7615 7616 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7617 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 7618 public: 7619 NaClMips32ELTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7620 : Mips32ELTargetInfo(Triple, Opts) {} 7621 7622 BuiltinVaListKind getBuiltinVaListKind() const override { 7623 return TargetInfo::PNaClABIBuiltinVaList; 7624 } 7625 }; 7626 7627 class Le64TargetInfo : public TargetInfo { 7628 static const Builtin::Info BuiltinInfo[]; 7629 7630 public: 7631 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7632 : TargetInfo(Triple) { 7633 BigEndian = false; 7634 NoAsmVariants = true; 7635 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7636 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7637 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 7638 } 7639 7640 void getTargetDefines(const LangOptions &Opts, 7641 MacroBuilder &Builder) const override { 7642 DefineStd(Builder, "unix", Opts); 7643 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7644 Builder.defineMacro("__ELF__"); 7645 } 7646 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7647 return llvm::makeArrayRef(BuiltinInfo, 7648 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7649 } 7650 BuiltinVaListKind getBuiltinVaListKind() const override { 7651 return TargetInfo::PNaClABIBuiltinVaList; 7652 } 7653 const char *getClobbers() const override { return ""; } 7654 ArrayRef<const char *> getGCCRegNames() const override { 7655 return None; 7656 } 7657 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7658 return None; 7659 } 7660 bool validateAsmConstraint(const char *&Name, 7661 TargetInfo::ConstraintInfo &Info) const override { 7662 return false; 7663 } 7664 7665 bool hasProtectedVisibility() const override { return false; } 7666 }; 7667 7668 class WebAssemblyTargetInfo : public TargetInfo { 7669 static const Builtin::Info BuiltinInfo[]; 7670 7671 enum SIMDEnum { 7672 NoSIMD, 7673 SIMD128, 7674 } SIMDLevel; 7675 7676 public: 7677 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 7678 : TargetInfo(T), SIMDLevel(NoSIMD) { 7679 BigEndian = false; 7680 NoAsmVariants = true; 7681 SuitableAlign = 128; 7682 LargeArrayMinWidth = 128; 7683 LargeArrayAlign = 128; 7684 SimdDefaultAlign = 128; 7685 SigAtomicType = SignedLong; 7686 LongDoubleWidth = LongDoubleAlign = 128; 7687 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7688 } 7689 7690 protected: 7691 void getTargetDefines(const LangOptions &Opts, 7692 MacroBuilder &Builder) const override { 7693 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7694 if (SIMDLevel >= SIMD128) 7695 Builder.defineMacro("__wasm_simd128__"); 7696 } 7697 7698 private: 7699 bool 7700 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7701 StringRef CPU, 7702 const std::vector<std::string> &FeaturesVec) const override { 7703 if (CPU == "bleeding-edge") 7704 Features["simd128"] = true; 7705 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7706 } 7707 bool hasFeature(StringRef Feature) const final { 7708 return llvm::StringSwitch<bool>(Feature) 7709 .Case("simd128", SIMDLevel >= SIMD128) 7710 .Default(false); 7711 } 7712 bool handleTargetFeatures(std::vector<std::string> &Features, 7713 DiagnosticsEngine &Diags) final { 7714 for (const auto &Feature : Features) { 7715 if (Feature == "+simd128") { 7716 SIMDLevel = std::max(SIMDLevel, SIMD128); 7717 continue; 7718 } 7719 if (Feature == "-simd128") { 7720 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7721 continue; 7722 } 7723 7724 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7725 << "-target-feature"; 7726 return false; 7727 } 7728 return true; 7729 } 7730 bool setCPU(const std::string &Name) final { 7731 return llvm::StringSwitch<bool>(Name) 7732 .Case("mvp", true) 7733 .Case("bleeding-edge", true) 7734 .Case("generic", true) 7735 .Default(false); 7736 } 7737 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7738 return llvm::makeArrayRef(BuiltinInfo, 7739 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7740 } 7741 BuiltinVaListKind getBuiltinVaListKind() const final { 7742 return VoidPtrBuiltinVaList; 7743 } 7744 ArrayRef<const char *> getGCCRegNames() const final { 7745 return None; 7746 } 7747 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7748 return None; 7749 } 7750 bool 7751 validateAsmConstraint(const char *&Name, 7752 TargetInfo::ConstraintInfo &Info) const final { 7753 return false; 7754 } 7755 const char *getClobbers() const final { return ""; } 7756 bool isCLZForZeroUndef() const final { return false; } 7757 bool hasInt128Type() const final { return true; } 7758 IntType getIntTypeByWidth(unsigned BitWidth, 7759 bool IsSigned) const final { 7760 // WebAssembly prefers long long for explicitly 64-bit integers. 7761 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7762 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7763 } 7764 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7765 bool IsSigned) const final { 7766 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7767 return BitWidth == 64 7768 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7769 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7770 } 7771 }; 7772 7773 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7774 #define BUILTIN(ID, TYPE, ATTRS) \ 7775 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7776 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7777 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7778 #include "clang/Basic/BuiltinsWebAssembly.def" 7779 }; 7780 7781 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7782 public: 7783 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 7784 const TargetOptions &Opts) 7785 : WebAssemblyTargetInfo(T, Opts) { 7786 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7787 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 7788 } 7789 7790 protected: 7791 void getTargetDefines(const LangOptions &Opts, 7792 MacroBuilder &Builder) const override { 7793 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7794 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7795 } 7796 }; 7797 7798 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7799 public: 7800 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 7801 const TargetOptions &Opts) 7802 : WebAssemblyTargetInfo(T, Opts) { 7803 LongAlign = LongWidth = 64; 7804 PointerAlign = PointerWidth = 64; 7805 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7806 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7807 } 7808 7809 protected: 7810 void getTargetDefines(const LangOptions &Opts, 7811 MacroBuilder &Builder) const override { 7812 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7813 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7814 } 7815 }; 7816 7817 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7818 #define BUILTIN(ID, TYPE, ATTRS) \ 7819 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7820 #include "clang/Basic/BuiltinsLe64.def" 7821 }; 7822 7823 static const unsigned SPIRAddrSpaceMap[] = { 7824 1, // opencl_global 7825 3, // opencl_local 7826 2, // opencl_constant 7827 4, // opencl_generic 7828 0, // cuda_device 7829 0, // cuda_constant 7830 0 // cuda_shared 7831 }; 7832 class SPIRTargetInfo : public TargetInfo { 7833 public: 7834 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7835 : TargetInfo(Triple) { 7836 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7837 "SPIR target must use unknown OS"); 7838 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7839 "SPIR target must use unknown environment type"); 7840 BigEndian = false; 7841 TLSSupported = false; 7842 LongWidth = LongAlign = 64; 7843 AddrSpaceMap = &SPIRAddrSpaceMap; 7844 UseAddrSpaceMapMangling = true; 7845 // Define available target features 7846 // These must be defined in sorted order! 7847 NoAsmVariants = true; 7848 } 7849 void getTargetDefines(const LangOptions &Opts, 7850 MacroBuilder &Builder) const override { 7851 DefineStd(Builder, "SPIR", Opts); 7852 } 7853 bool hasFeature(StringRef Feature) const override { 7854 return Feature == "spir"; 7855 } 7856 7857 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7858 const char *getClobbers() const override { return ""; } 7859 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7860 bool validateAsmConstraint(const char *&Name, 7861 TargetInfo::ConstraintInfo &info) const override { 7862 return true; 7863 } 7864 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7865 return None; 7866 } 7867 BuiltinVaListKind getBuiltinVaListKind() const override { 7868 return TargetInfo::VoidPtrBuiltinVaList; 7869 } 7870 7871 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7872 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK 7873 : CCCR_Warning; 7874 } 7875 7876 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7877 return CC_SpirFunction; 7878 } 7879 7880 void setSupportedOpenCLOpts() override { 7881 // Assume all OpenCL extensions and optional core features are supported 7882 // for SPIR since it is a generic target. 7883 getSupportedOpenCLOpts().setAll(); 7884 } 7885 }; 7886 7887 class SPIR32TargetInfo : public SPIRTargetInfo { 7888 public: 7889 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7890 : SPIRTargetInfo(Triple, Opts) { 7891 PointerWidth = PointerAlign = 32; 7892 SizeType = TargetInfo::UnsignedInt; 7893 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7894 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7895 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7896 } 7897 void getTargetDefines(const LangOptions &Opts, 7898 MacroBuilder &Builder) const override { 7899 DefineStd(Builder, "SPIR32", Opts); 7900 } 7901 }; 7902 7903 class SPIR64TargetInfo : public SPIRTargetInfo { 7904 public: 7905 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7906 : SPIRTargetInfo(Triple, Opts) { 7907 PointerWidth = PointerAlign = 64; 7908 SizeType = TargetInfo::UnsignedLong; 7909 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7910 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7911 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7912 } 7913 void getTargetDefines(const LangOptions &Opts, 7914 MacroBuilder &Builder) const override { 7915 DefineStd(Builder, "SPIR64", Opts); 7916 } 7917 }; 7918 7919 class XCoreTargetInfo : public TargetInfo { 7920 static const Builtin::Info BuiltinInfo[]; 7921 public: 7922 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7923 : TargetInfo(Triple) { 7924 BigEndian = false; 7925 NoAsmVariants = true; 7926 LongLongAlign = 32; 7927 SuitableAlign = 32; 7928 DoubleAlign = LongDoubleAlign = 32; 7929 SizeType = UnsignedInt; 7930 PtrDiffType = SignedInt; 7931 IntPtrType = SignedInt; 7932 WCharType = UnsignedChar; 7933 WIntType = UnsignedInt; 7934 UseZeroLengthBitfieldAlignment = true; 7935 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7936 "-f64:32-a:0:32-n32"); 7937 } 7938 void getTargetDefines(const LangOptions &Opts, 7939 MacroBuilder &Builder) const override { 7940 Builder.defineMacro("__XS1B__"); 7941 } 7942 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7943 return llvm::makeArrayRef(BuiltinInfo, 7944 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 7945 } 7946 BuiltinVaListKind getBuiltinVaListKind() const override { 7947 return TargetInfo::VoidPtrBuiltinVaList; 7948 } 7949 const char *getClobbers() const override { 7950 return ""; 7951 } 7952 ArrayRef<const char *> getGCCRegNames() const override { 7953 static const char * const GCCRegNames[] = { 7954 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7955 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 7956 }; 7957 return llvm::makeArrayRef(GCCRegNames); 7958 } 7959 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7960 return None; 7961 } 7962 bool validateAsmConstraint(const char *&Name, 7963 TargetInfo::ConstraintInfo &Info) const override { 7964 return false; 7965 } 7966 int getEHDataRegisterNumber(unsigned RegNo) const override { 7967 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7968 return (RegNo < 2)? RegNo : -1; 7969 } 7970 bool allowsLargerPreferedTypeAlignment() const override { 7971 return false; 7972 } 7973 }; 7974 7975 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7976 #define BUILTIN(ID, TYPE, ATTRS) \ 7977 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7978 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7979 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7980 #include "clang/Basic/BuiltinsXCore.def" 7981 }; 7982 7983 // x86_32 Android target 7984 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7985 public: 7986 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7987 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 7988 SuitableAlign = 32; 7989 LongDoubleWidth = 64; 7990 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7991 } 7992 }; 7993 7994 // x86_64 Android target 7995 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7996 public: 7997 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7998 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 7999 LongDoubleFormat = &llvm::APFloat::IEEEquad; 8000 } 8001 8002 bool useFloat128ManglingForLongDouble() const override { 8003 return true; 8004 } 8005 }; 8006 } // end anonymous namespace 8007 8008 //===----------------------------------------------------------------------===// 8009 // Driver code 8010 //===----------------------------------------------------------------------===// 8011 8012 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 8013 const TargetOptions &Opts) { 8014 llvm::Triple::OSType os = Triple.getOS(); 8015 8016 switch (Triple.getArch()) { 8017 default: 8018 return nullptr; 8019 8020 case llvm::Triple::xcore: 8021 return new XCoreTargetInfo(Triple, Opts); 8022 8023 case llvm::Triple::hexagon: 8024 return new HexagonTargetInfo(Triple, Opts); 8025 8026 case llvm::Triple::lanai: 8027 return new LanaiTargetInfo(Triple, Opts); 8028 8029 case llvm::Triple::aarch64: 8030 if (Triple.isOSDarwin()) 8031 return new DarwinAArch64TargetInfo(Triple, Opts); 8032 8033 switch (os) { 8034 case llvm::Triple::CloudABI: 8035 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 8036 case llvm::Triple::FreeBSD: 8037 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8038 case llvm::Triple::Linux: 8039 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8040 case llvm::Triple::NetBSD: 8041 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8042 default: 8043 return new AArch64leTargetInfo(Triple, Opts); 8044 } 8045 8046 case llvm::Triple::aarch64_be: 8047 switch (os) { 8048 case llvm::Triple::FreeBSD: 8049 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8050 case llvm::Triple::Linux: 8051 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8052 case llvm::Triple::NetBSD: 8053 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8054 default: 8055 return new AArch64beTargetInfo(Triple, Opts); 8056 } 8057 8058 case llvm::Triple::arm: 8059 case llvm::Triple::thumb: 8060 if (Triple.isOSBinFormatMachO()) 8061 return new DarwinARMTargetInfo(Triple, Opts); 8062 8063 switch (os) { 8064 case llvm::Triple::Linux: 8065 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 8066 case llvm::Triple::FreeBSD: 8067 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8068 case llvm::Triple::NetBSD: 8069 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8070 case llvm::Triple::OpenBSD: 8071 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8072 case llvm::Triple::Bitrig: 8073 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 8074 case llvm::Triple::RTEMS: 8075 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 8076 case llvm::Triple::NaCl: 8077 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 8078 case llvm::Triple::Win32: 8079 switch (Triple.getEnvironment()) { 8080 case llvm::Triple::Cygnus: 8081 return new CygwinARMTargetInfo(Triple, Opts); 8082 case llvm::Triple::GNU: 8083 return new MinGWARMTargetInfo(Triple, Opts); 8084 case llvm::Triple::Itanium: 8085 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 8086 case llvm::Triple::MSVC: 8087 default: // Assume MSVC for unknown environments 8088 return new MicrosoftARMleTargetInfo(Triple, Opts); 8089 } 8090 default: 8091 return new ARMleTargetInfo(Triple, Opts); 8092 } 8093 8094 case llvm::Triple::armeb: 8095 case llvm::Triple::thumbeb: 8096 if (Triple.isOSDarwin()) 8097 return new DarwinARMTargetInfo(Triple, Opts); 8098 8099 switch (os) { 8100 case llvm::Triple::Linux: 8101 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8102 case llvm::Triple::FreeBSD: 8103 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8104 case llvm::Triple::NetBSD: 8105 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8106 case llvm::Triple::OpenBSD: 8107 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8108 case llvm::Triple::Bitrig: 8109 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8110 case llvm::Triple::RTEMS: 8111 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8112 case llvm::Triple::NaCl: 8113 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8114 default: 8115 return new ARMbeTargetInfo(Triple, Opts); 8116 } 8117 8118 case llvm::Triple::bpfeb: 8119 case llvm::Triple::bpfel: 8120 return new BPFTargetInfo(Triple, Opts); 8121 8122 case llvm::Triple::msp430: 8123 return new MSP430TargetInfo(Triple, Opts); 8124 8125 case llvm::Triple::mips: 8126 switch (os) { 8127 case llvm::Triple::Linux: 8128 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple, Opts); 8129 case llvm::Triple::RTEMS: 8130 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple, Opts); 8131 case llvm::Triple::FreeBSD: 8132 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple, Opts); 8133 case llvm::Triple::NetBSD: 8134 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple, Opts); 8135 default: 8136 return new Mips32EBTargetInfo(Triple, Opts); 8137 } 8138 8139 case llvm::Triple::mipsel: 8140 switch (os) { 8141 case llvm::Triple::Linux: 8142 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple, Opts); 8143 case llvm::Triple::RTEMS: 8144 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple, Opts); 8145 case llvm::Triple::FreeBSD: 8146 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple, Opts); 8147 case llvm::Triple::NetBSD: 8148 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple, Opts); 8149 case llvm::Triple::NaCl: 8150 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple, Opts); 8151 default: 8152 return new Mips32ELTargetInfo(Triple, Opts); 8153 } 8154 8155 case llvm::Triple::mips64: 8156 switch (os) { 8157 case llvm::Triple::Linux: 8158 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 8159 case llvm::Triple::RTEMS: 8160 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 8161 case llvm::Triple::FreeBSD: 8162 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 8163 case llvm::Triple::NetBSD: 8164 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 8165 case llvm::Triple::OpenBSD: 8166 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 8167 default: 8168 return new Mips64EBTargetInfo(Triple, Opts); 8169 } 8170 8171 case llvm::Triple::mips64el: 8172 switch (os) { 8173 case llvm::Triple::Linux: 8174 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8175 case llvm::Triple::RTEMS: 8176 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8177 case llvm::Triple::FreeBSD: 8178 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8179 case llvm::Triple::NetBSD: 8180 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8181 case llvm::Triple::OpenBSD: 8182 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8183 default: 8184 return new Mips64ELTargetInfo(Triple, Opts); 8185 } 8186 8187 case llvm::Triple::le32: 8188 switch (os) { 8189 case llvm::Triple::NaCl: 8190 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 8191 default: 8192 return nullptr; 8193 } 8194 8195 case llvm::Triple::le64: 8196 return new Le64TargetInfo(Triple, Opts); 8197 8198 case llvm::Triple::ppc: 8199 if (Triple.isOSDarwin()) 8200 return new DarwinPPC32TargetInfo(Triple, Opts); 8201 switch (os) { 8202 case llvm::Triple::Linux: 8203 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 8204 case llvm::Triple::FreeBSD: 8205 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8206 case llvm::Triple::NetBSD: 8207 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8208 case llvm::Triple::OpenBSD: 8209 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8210 case llvm::Triple::RTEMS: 8211 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 8212 default: 8213 return new PPC32TargetInfo(Triple, Opts); 8214 } 8215 8216 case llvm::Triple::ppc64: 8217 if (Triple.isOSDarwin()) 8218 return new DarwinPPC64TargetInfo(Triple, Opts); 8219 switch (os) { 8220 case llvm::Triple::Linux: 8221 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8222 case llvm::Triple::Lv2: 8223 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 8224 case llvm::Triple::FreeBSD: 8225 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8226 case llvm::Triple::NetBSD: 8227 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8228 default: 8229 return new PPC64TargetInfo(Triple, Opts); 8230 } 8231 8232 case llvm::Triple::ppc64le: 8233 switch (os) { 8234 case llvm::Triple::Linux: 8235 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8236 case llvm::Triple::NetBSD: 8237 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8238 default: 8239 return new PPC64TargetInfo(Triple, Opts); 8240 } 8241 8242 case llvm::Triple::nvptx: 8243 return new NVPTX32TargetInfo(Triple, Opts); 8244 case llvm::Triple::nvptx64: 8245 return new NVPTX64TargetInfo(Triple, Opts); 8246 8247 case llvm::Triple::amdgcn: 8248 case llvm::Triple::r600: 8249 return new AMDGPUTargetInfo(Triple, Opts); 8250 8251 case llvm::Triple::sparc: 8252 switch (os) { 8253 case llvm::Triple::Linux: 8254 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8255 case llvm::Triple::Solaris: 8256 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8257 case llvm::Triple::NetBSD: 8258 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8259 case llvm::Triple::OpenBSD: 8260 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8261 case llvm::Triple::RTEMS: 8262 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8263 default: 8264 return new SparcV8TargetInfo(Triple, Opts); 8265 } 8266 8267 // The 'sparcel' architecture copies all the above cases except for Solaris. 8268 case llvm::Triple::sparcel: 8269 switch (os) { 8270 case llvm::Triple::Linux: 8271 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8272 case llvm::Triple::NetBSD: 8273 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8274 case llvm::Triple::OpenBSD: 8275 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8276 case llvm::Triple::RTEMS: 8277 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8278 default: 8279 return new SparcV8elTargetInfo(Triple, Opts); 8280 } 8281 8282 case llvm::Triple::sparcv9: 8283 switch (os) { 8284 case llvm::Triple::Linux: 8285 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8286 case llvm::Triple::Solaris: 8287 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8288 case llvm::Triple::NetBSD: 8289 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8290 case llvm::Triple::OpenBSD: 8291 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8292 case llvm::Triple::FreeBSD: 8293 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8294 default: 8295 return new SparcV9TargetInfo(Triple, Opts); 8296 } 8297 8298 case llvm::Triple::systemz: 8299 switch (os) { 8300 case llvm::Triple::Linux: 8301 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 8302 default: 8303 return new SystemZTargetInfo(Triple, Opts); 8304 } 8305 8306 case llvm::Triple::tce: 8307 return new TCETargetInfo(Triple, Opts); 8308 8309 case llvm::Triple::x86: 8310 if (Triple.isOSDarwin()) 8311 return new DarwinI386TargetInfo(Triple, Opts); 8312 8313 switch (os) { 8314 case llvm::Triple::CloudABI: 8315 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 8316 case llvm::Triple::Linux: { 8317 switch (Triple.getEnvironment()) { 8318 default: 8319 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 8320 case llvm::Triple::Android: 8321 return new AndroidX86_32TargetInfo(Triple, Opts); 8322 } 8323 } 8324 case llvm::Triple::DragonFly: 8325 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8326 case llvm::Triple::NetBSD: 8327 return new NetBSDI386TargetInfo(Triple, Opts); 8328 case llvm::Triple::OpenBSD: 8329 return new OpenBSDI386TargetInfo(Triple, Opts); 8330 case llvm::Triple::Bitrig: 8331 return new BitrigI386TargetInfo(Triple, Opts); 8332 case llvm::Triple::FreeBSD: 8333 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8334 case llvm::Triple::KFreeBSD: 8335 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8336 case llvm::Triple::Minix: 8337 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 8338 case llvm::Triple::Solaris: 8339 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 8340 case llvm::Triple::Win32: { 8341 switch (Triple.getEnvironment()) { 8342 case llvm::Triple::Cygnus: 8343 return new CygwinX86_32TargetInfo(Triple, Opts); 8344 case llvm::Triple::GNU: 8345 return new MinGWX86_32TargetInfo(Triple, Opts); 8346 case llvm::Triple::Itanium: 8347 case llvm::Triple::MSVC: 8348 default: // Assume MSVC for unknown environments 8349 return new MicrosoftX86_32TargetInfo(Triple, Opts); 8350 } 8351 } 8352 case llvm::Triple::Haiku: 8353 return new HaikuX86_32TargetInfo(Triple, Opts); 8354 case llvm::Triple::RTEMS: 8355 return new RTEMSX86_32TargetInfo(Triple, Opts); 8356 case llvm::Triple::NaCl: 8357 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 8358 case llvm::Triple::ELFIAMCU: 8359 return new MCUX86_32TargetInfo(Triple, Opts); 8360 default: 8361 return new X86_32TargetInfo(Triple, Opts); 8362 } 8363 8364 case llvm::Triple::x86_64: 8365 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 8366 return new DarwinX86_64TargetInfo(Triple, Opts); 8367 8368 switch (os) { 8369 case llvm::Triple::CloudABI: 8370 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 8371 case llvm::Triple::Linux: { 8372 switch (Triple.getEnvironment()) { 8373 default: 8374 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 8375 case llvm::Triple::Android: 8376 return new AndroidX86_64TargetInfo(Triple, Opts); 8377 } 8378 } 8379 case llvm::Triple::DragonFly: 8380 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8381 case llvm::Triple::NetBSD: 8382 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8383 case llvm::Triple::OpenBSD: 8384 return new OpenBSDX86_64TargetInfo(Triple, Opts); 8385 case llvm::Triple::Bitrig: 8386 return new BitrigX86_64TargetInfo(Triple, Opts); 8387 case llvm::Triple::FreeBSD: 8388 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8389 case llvm::Triple::KFreeBSD: 8390 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8391 case llvm::Triple::Solaris: 8392 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 8393 case llvm::Triple::Win32: { 8394 switch (Triple.getEnvironment()) { 8395 case llvm::Triple::Cygnus: 8396 return new CygwinX86_64TargetInfo(Triple, Opts); 8397 case llvm::Triple::GNU: 8398 return new MinGWX86_64TargetInfo(Triple, Opts); 8399 case llvm::Triple::MSVC: 8400 default: // Assume MSVC for unknown environments 8401 return new MicrosoftX86_64TargetInfo(Triple, Opts); 8402 } 8403 } 8404 case llvm::Triple::Haiku: 8405 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 8406 case llvm::Triple::NaCl: 8407 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 8408 case llvm::Triple::PS4: 8409 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 8410 default: 8411 return new X86_64TargetInfo(Triple, Opts); 8412 } 8413 8414 case llvm::Triple::spir: { 8415 if (Triple.getOS() != llvm::Triple::UnknownOS || 8416 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8417 return nullptr; 8418 return new SPIR32TargetInfo(Triple, Opts); 8419 } 8420 case llvm::Triple::spir64: { 8421 if (Triple.getOS() != llvm::Triple::UnknownOS || 8422 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8423 return nullptr; 8424 return new SPIR64TargetInfo(Triple, Opts); 8425 } 8426 case llvm::Triple::wasm32: 8427 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8428 return nullptr; 8429 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 8430 case llvm::Triple::wasm64: 8431 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8432 return nullptr; 8433 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 8434 } 8435 } 8436 8437 /// CreateTargetInfo - Return the target info object for the specified target 8438 /// options. 8439 TargetInfo * 8440 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8441 const std::shared_ptr<TargetOptions> &Opts) { 8442 llvm::Triple Triple(Opts->Triple); 8443 8444 // Construct the target 8445 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 8446 if (!Target) { 8447 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8448 return nullptr; 8449 } 8450 Target->TargetOpts = Opts; 8451 8452 // Set the target CPU if specified. 8453 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8454 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8455 return nullptr; 8456 } 8457 8458 // Set the target ABI if specified. 8459 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8460 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8461 return nullptr; 8462 } 8463 8464 // Set the fp math unit. 8465 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8466 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8467 return nullptr; 8468 } 8469 8470 // Compute the default target features, we need the target to handle this 8471 // because features may have dependencies on one another. 8472 llvm::StringMap<bool> Features; 8473 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8474 Opts->FeaturesAsWritten)) 8475 return nullptr; 8476 8477 // Add the features to the compile options. 8478 Opts->Features.clear(); 8479 for (const auto &F : Features) 8480 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8481 8482 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8483 return nullptr; 8484 8485 Target->setSupportedOpenCLOpts(); 8486 8487 return Target.release(); 8488 } 8489