1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 // Ananas target 115 template<typename Target> 116 class AnanasTargetInfo : public OSTargetInfo<Target> { 117 protected: 118 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 119 MacroBuilder &Builder) const override { 120 // Ananas defines 121 Builder.defineMacro("__Ananas__"); 122 Builder.defineMacro("__ELF__"); 123 } 124 public: 125 AnanasTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 126 : OSTargetInfo<Target>(Triple, Opts) {} 127 }; 128 129 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 130 const llvm::Triple &Triple, 131 StringRef &PlatformName, 132 VersionTuple &PlatformMinVersion) { 133 Builder.defineMacro("__APPLE_CC__", "6000"); 134 Builder.defineMacro("__APPLE__"); 135 Builder.defineMacro("__STDC_NO_THREADS__"); 136 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 137 // AddressSanitizer doesn't play well with source fortification, which is on 138 // by default on Darwin. 139 if (Opts.Sanitize.has(SanitizerKind::Address)) 140 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 141 142 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 143 if (!Opts.ObjC1) { 144 // __weak is always defined, for use in blocks and with objc pointers. 145 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 146 Builder.defineMacro("__strong", ""); 147 Builder.defineMacro("__unsafe_unretained", ""); 148 } 149 150 if (Opts.Static) 151 Builder.defineMacro("__STATIC__"); 152 else 153 Builder.defineMacro("__DYNAMIC__"); 154 155 if (Opts.POSIXThreads) 156 Builder.defineMacro("_REENTRANT"); 157 158 // Get the platform type and version number from the triple. 159 unsigned Maj, Min, Rev; 160 if (Triple.isMacOSX()) { 161 Triple.getMacOSXVersion(Maj, Min, Rev); 162 PlatformName = "macos"; 163 } else { 164 Triple.getOSVersion(Maj, Min, Rev); 165 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 166 } 167 168 // If -target arch-pc-win32-macho option specified, we're 169 // generating code for Win32 ABI. No need to emit 170 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 171 if (PlatformName == "win32") { 172 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 173 return; 174 } 175 176 // Set the appropriate OS version define. 177 if (Triple.isiOS()) { 178 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 179 char Str[7]; 180 if (Maj < 10) { 181 Str[0] = '0' + Maj; 182 Str[1] = '0' + (Min / 10); 183 Str[2] = '0' + (Min % 10); 184 Str[3] = '0' + (Rev / 10); 185 Str[4] = '0' + (Rev % 10); 186 Str[5] = '\0'; 187 } else { 188 // Handle versions >= 10. 189 Str[0] = '0' + (Maj / 10); 190 Str[1] = '0' + (Maj % 10); 191 Str[2] = '0' + (Min / 10); 192 Str[3] = '0' + (Min % 10); 193 Str[4] = '0' + (Rev / 10); 194 Str[5] = '0' + (Rev % 10); 195 Str[6] = '\0'; 196 } 197 if (Triple.isTvOS()) 198 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 199 else 200 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 201 Str); 202 203 } else if (Triple.isWatchOS()) { 204 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 205 char Str[6]; 206 Str[0] = '0' + Maj; 207 Str[1] = '0' + (Min / 10); 208 Str[2] = '0' + (Min % 10); 209 Str[3] = '0' + (Rev / 10); 210 Str[4] = '0' + (Rev % 10); 211 Str[5] = '\0'; 212 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 213 } else if (Triple.isMacOSX()) { 214 // Note that the Driver allows versions which aren't representable in the 215 // define (because we only get a single digit for the minor and micro 216 // revision numbers). So, we limit them to the maximum representable 217 // version. 218 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 219 char Str[7]; 220 if (Maj < 10 || (Maj == 10 && Min < 10)) { 221 Str[0] = '0' + (Maj / 10); 222 Str[1] = '0' + (Maj % 10); 223 Str[2] = '0' + std::min(Min, 9U); 224 Str[3] = '0' + std::min(Rev, 9U); 225 Str[4] = '\0'; 226 } else { 227 // Handle versions > 10.9. 228 Str[0] = '0' + (Maj / 10); 229 Str[1] = '0' + (Maj % 10); 230 Str[2] = '0' + (Min / 10); 231 Str[3] = '0' + (Min % 10); 232 Str[4] = '0' + (Rev / 10); 233 Str[5] = '0' + (Rev % 10); 234 Str[6] = '\0'; 235 } 236 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 237 } 238 239 // Tell users about the kernel if there is one. 240 if (Triple.isOSDarwin()) 241 Builder.defineMacro("__MACH__"); 242 243 // The Watch ABI uses Dwarf EH. 244 if(Triple.isWatchABI()) 245 Builder.defineMacro("__ARM_DWARF_EH__"); 246 247 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 248 } 249 250 template<typename Target> 251 class DarwinTargetInfo : public OSTargetInfo<Target> { 252 protected: 253 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 254 MacroBuilder &Builder) const override { 255 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 256 this->PlatformMinVersion); 257 } 258 259 public: 260 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 261 : OSTargetInfo<Target>(Triple, Opts) { 262 // By default, no TLS, and we whitelist permitted architecture/OS 263 // combinations. 264 this->TLSSupported = false; 265 266 if (Triple.isMacOSX()) 267 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 268 else if (Triple.isiOS()) { 269 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 270 if (Triple.getArch() == llvm::Triple::x86_64 || 271 Triple.getArch() == llvm::Triple::aarch64) 272 this->TLSSupported = !Triple.isOSVersionLT(8); 273 else if (Triple.getArch() == llvm::Triple::x86 || 274 Triple.getArch() == llvm::Triple::arm || 275 Triple.getArch() == llvm::Triple::thumb) 276 this->TLSSupported = !Triple.isOSVersionLT(9); 277 } else if (Triple.isWatchOS()) 278 this->TLSSupported = !Triple.isOSVersionLT(2); 279 280 this->MCountName = "\01mcount"; 281 } 282 283 std::string isValidSectionSpecifier(StringRef SR) const override { 284 // Let MCSectionMachO validate this. 285 StringRef Segment, Section; 286 unsigned TAA, StubSize; 287 bool HasTAA; 288 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 289 TAA, HasTAA, StubSize); 290 } 291 292 const char *getStaticInitSectionSpecifier() const override { 293 // FIXME: We should return 0 when building kexts. 294 return "__TEXT,__StaticInit,regular,pure_instructions"; 295 } 296 297 /// Darwin does not support protected visibility. Darwin's "default" 298 /// is very similar to ELF's "protected"; Darwin requires a "weak" 299 /// attribute on declarations that can be dynamically replaced. 300 bool hasProtectedVisibility() const override { 301 return false; 302 } 303 304 unsigned getExnObjectAlignment() const override { 305 // The alignment of an exception object is 8-bytes for darwin since 306 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 307 // and therefore doesn't guarantee 16-byte alignment. 308 return 64; 309 } 310 }; 311 312 313 // DragonFlyBSD Target 314 template<typename Target> 315 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 316 protected: 317 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 318 MacroBuilder &Builder) const override { 319 // DragonFly defines; list based off of gcc output 320 Builder.defineMacro("__DragonFly__"); 321 Builder.defineMacro("__DragonFly_cc_version", "100001"); 322 Builder.defineMacro("__ELF__"); 323 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 324 Builder.defineMacro("__tune_i386__"); 325 DefineStd(Builder, "unix", Opts); 326 } 327 public: 328 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 329 : OSTargetInfo<Target>(Triple, Opts) { 330 switch (Triple.getArch()) { 331 default: 332 case llvm::Triple::x86: 333 case llvm::Triple::x86_64: 334 this->MCountName = ".mcount"; 335 break; 336 } 337 } 338 }; 339 340 #ifndef FREEBSD_CC_VERSION 341 #define FREEBSD_CC_VERSION 0U 342 #endif 343 344 // FreeBSD Target 345 template<typename Target> 346 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 347 protected: 348 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 349 MacroBuilder &Builder) const override { 350 // FreeBSD defines; list based off of gcc output 351 352 unsigned Release = Triple.getOSMajorVersion(); 353 if (Release == 0U) 354 Release = 8U; 355 unsigned CCVersion = FREEBSD_CC_VERSION; 356 if (CCVersion == 0U) 357 CCVersion = Release * 100000U + 1U; 358 359 Builder.defineMacro("__FreeBSD__", Twine(Release)); 360 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 361 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 362 DefineStd(Builder, "unix", Opts); 363 Builder.defineMacro("__ELF__"); 364 365 // On FreeBSD, wchar_t contains the number of the code point as 366 // used by the character set of the locale. These character sets are 367 // not necessarily a superset of ASCII. 368 // 369 // FIXME: This is wrong; the macro refers to the numerical values 370 // of wchar_t *literals*, which are not locale-dependent. However, 371 // FreeBSD systems apparently depend on us getting this wrong, and 372 // setting this to 1 is conforming even if all the basic source 373 // character literals have the same encoding as char and wchar_t. 374 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 375 } 376 public: 377 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 378 : OSTargetInfo<Target>(Triple, Opts) { 379 switch (Triple.getArch()) { 380 default: 381 case llvm::Triple::x86: 382 case llvm::Triple::x86_64: 383 this->MCountName = ".mcount"; 384 break; 385 case llvm::Triple::mips: 386 case llvm::Triple::mipsel: 387 case llvm::Triple::ppc: 388 case llvm::Triple::ppc64: 389 case llvm::Triple::ppc64le: 390 this->MCountName = "_mcount"; 391 break; 392 case llvm::Triple::arm: 393 this->MCountName = "__mcount"; 394 break; 395 } 396 } 397 }; 398 399 // GNU/kFreeBSD Target 400 template<typename Target> 401 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 402 protected: 403 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 404 MacroBuilder &Builder) const override { 405 // GNU/kFreeBSD defines; list based off of gcc output 406 407 DefineStd(Builder, "unix", Opts); 408 Builder.defineMacro("__FreeBSD_kernel__"); 409 Builder.defineMacro("__GLIBC__"); 410 Builder.defineMacro("__ELF__"); 411 if (Opts.POSIXThreads) 412 Builder.defineMacro("_REENTRANT"); 413 if (Opts.CPlusPlus) 414 Builder.defineMacro("_GNU_SOURCE"); 415 } 416 public: 417 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 418 : OSTargetInfo<Target>(Triple, Opts) {} 419 }; 420 421 // Haiku Target 422 template<typename Target> 423 class HaikuTargetInfo : public OSTargetInfo<Target> { 424 protected: 425 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 426 MacroBuilder &Builder) const override { 427 // Haiku defines; list based off of gcc output 428 Builder.defineMacro("__HAIKU__"); 429 Builder.defineMacro("__ELF__"); 430 DefineStd(Builder, "unix", Opts); 431 } 432 public: 433 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 434 : OSTargetInfo<Target>(Triple, Opts) { 435 this->SizeType = TargetInfo::UnsignedLong; 436 this->IntPtrType = TargetInfo::SignedLong; 437 this->PtrDiffType = TargetInfo::SignedLong; 438 this->ProcessIDType = TargetInfo::SignedLong; 439 this->TLSSupported = false; 440 441 } 442 }; 443 444 // Minix Target 445 template<typename Target> 446 class MinixTargetInfo : public OSTargetInfo<Target> { 447 protected: 448 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 449 MacroBuilder &Builder) const override { 450 // Minix defines 451 452 Builder.defineMacro("__minix", "3"); 453 Builder.defineMacro("_EM_WSIZE", "4"); 454 Builder.defineMacro("_EM_PSIZE", "4"); 455 Builder.defineMacro("_EM_SSIZE", "2"); 456 Builder.defineMacro("_EM_LSIZE", "4"); 457 Builder.defineMacro("_EM_FSIZE", "4"); 458 Builder.defineMacro("_EM_DSIZE", "8"); 459 Builder.defineMacro("__ELF__"); 460 DefineStd(Builder, "unix", Opts); 461 } 462 public: 463 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 464 : OSTargetInfo<Target>(Triple, Opts) {} 465 }; 466 467 // Linux target 468 template<typename Target> 469 class LinuxTargetInfo : public OSTargetInfo<Target> { 470 protected: 471 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 472 MacroBuilder &Builder) const override { 473 // Linux defines; list based off of gcc output 474 DefineStd(Builder, "unix", Opts); 475 DefineStd(Builder, "linux", Opts); 476 Builder.defineMacro("__gnu_linux__"); 477 Builder.defineMacro("__ELF__"); 478 if (Triple.isAndroid()) { 479 Builder.defineMacro("__ANDROID__", "1"); 480 unsigned Maj, Min, Rev; 481 Triple.getEnvironmentVersion(Maj, Min, Rev); 482 this->PlatformName = "android"; 483 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 484 if (Maj) 485 Builder.defineMacro("__ANDROID_API__", Twine(Maj)); 486 } 487 if (Opts.POSIXThreads) 488 Builder.defineMacro("_REENTRANT"); 489 if (Opts.CPlusPlus) 490 Builder.defineMacro("_GNU_SOURCE"); 491 if (this->HasFloat128) 492 Builder.defineMacro("__FLOAT128__"); 493 } 494 public: 495 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 496 : OSTargetInfo<Target>(Triple, Opts) { 497 this->WIntType = TargetInfo::UnsignedInt; 498 499 switch (Triple.getArch()) { 500 default: 501 break; 502 case llvm::Triple::ppc: 503 case llvm::Triple::ppc64: 504 case llvm::Triple::ppc64le: 505 this->MCountName = "_mcount"; 506 break; 507 case llvm::Triple::x86: 508 case llvm::Triple::x86_64: 509 case llvm::Triple::systemz: 510 this->HasFloat128 = true; 511 break; 512 } 513 } 514 515 const char *getStaticInitSectionSpecifier() const override { 516 return ".text.startup"; 517 } 518 }; 519 520 // NetBSD Target 521 template<typename Target> 522 class NetBSDTargetInfo : public OSTargetInfo<Target> { 523 protected: 524 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 525 MacroBuilder &Builder) const override { 526 // NetBSD defines; list based off of gcc output 527 Builder.defineMacro("__NetBSD__"); 528 Builder.defineMacro("__unix__"); 529 Builder.defineMacro("__ELF__"); 530 if (Opts.POSIXThreads) 531 Builder.defineMacro("_REENTRANT"); 532 533 switch (Triple.getArch()) { 534 default: 535 break; 536 case llvm::Triple::arm: 537 case llvm::Triple::armeb: 538 case llvm::Triple::thumb: 539 case llvm::Triple::thumbeb: 540 Builder.defineMacro("__ARM_DWARF_EH__"); 541 break; 542 } 543 } 544 public: 545 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 546 : OSTargetInfo<Target>(Triple, Opts) { 547 this->MCountName = "_mcount"; 548 } 549 }; 550 551 // OpenBSD Target 552 template<typename Target> 553 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 554 protected: 555 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 556 MacroBuilder &Builder) const override { 557 // OpenBSD defines; list based off of gcc output 558 559 Builder.defineMacro("__OpenBSD__"); 560 DefineStd(Builder, "unix", Opts); 561 Builder.defineMacro("__ELF__"); 562 if (Opts.POSIXThreads) 563 Builder.defineMacro("_REENTRANT"); 564 if (this->HasFloat128) 565 Builder.defineMacro("__FLOAT128__"); 566 } 567 public: 568 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 569 : OSTargetInfo<Target>(Triple, Opts) { 570 this->TLSSupported = false; 571 572 switch (Triple.getArch()) { 573 case llvm::Triple::x86: 574 case llvm::Triple::x86_64: 575 this->HasFloat128 = true; 576 // FALLTHROUGH 577 default: 578 this->MCountName = "__mcount"; 579 break; 580 case llvm::Triple::mips64: 581 case llvm::Triple::mips64el: 582 case llvm::Triple::ppc: 583 case llvm::Triple::sparcv9: 584 this->MCountName = "_mcount"; 585 break; 586 } 587 } 588 }; 589 590 // Bitrig Target 591 template<typename Target> 592 class BitrigTargetInfo : public OSTargetInfo<Target> { 593 protected: 594 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 595 MacroBuilder &Builder) const override { 596 // Bitrig defines; list based off of gcc output 597 598 Builder.defineMacro("__Bitrig__"); 599 DefineStd(Builder, "unix", Opts); 600 Builder.defineMacro("__ELF__"); 601 if (Opts.POSIXThreads) 602 Builder.defineMacro("_REENTRANT"); 603 604 switch (Triple.getArch()) { 605 default: 606 break; 607 case llvm::Triple::arm: 608 case llvm::Triple::armeb: 609 case llvm::Triple::thumb: 610 case llvm::Triple::thumbeb: 611 Builder.defineMacro("__ARM_DWARF_EH__"); 612 break; 613 } 614 } 615 public: 616 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 617 : OSTargetInfo<Target>(Triple, Opts) { 618 this->MCountName = "__mcount"; 619 } 620 }; 621 622 // PSP Target 623 template<typename Target> 624 class PSPTargetInfo : public OSTargetInfo<Target> { 625 protected: 626 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 627 MacroBuilder &Builder) const override { 628 // PSP defines; list based on the output of the pspdev gcc toolchain. 629 Builder.defineMacro("PSP"); 630 Builder.defineMacro("_PSP"); 631 Builder.defineMacro("__psp__"); 632 Builder.defineMacro("__ELF__"); 633 } 634 public: 635 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 636 }; 637 638 // PS3 PPU Target 639 template<typename Target> 640 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 641 protected: 642 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 643 MacroBuilder &Builder) const override { 644 // PS3 PPU defines. 645 Builder.defineMacro("__PPC__"); 646 Builder.defineMacro("__PPU__"); 647 Builder.defineMacro("__CELLOS_LV2__"); 648 Builder.defineMacro("__ELF__"); 649 Builder.defineMacro("__LP32__"); 650 Builder.defineMacro("_ARCH_PPC64"); 651 Builder.defineMacro("__powerpc64__"); 652 } 653 public: 654 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 655 : OSTargetInfo<Target>(Triple, Opts) { 656 this->LongWidth = this->LongAlign = 32; 657 this->PointerWidth = this->PointerAlign = 32; 658 this->IntMaxType = TargetInfo::SignedLongLong; 659 this->Int64Type = TargetInfo::SignedLongLong; 660 this->SizeType = TargetInfo::UnsignedInt; 661 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 662 } 663 }; 664 665 template <typename Target> 666 class PS4OSTargetInfo : public OSTargetInfo<Target> { 667 protected: 668 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 669 MacroBuilder &Builder) const override { 670 Builder.defineMacro("__FreeBSD__", "9"); 671 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 672 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 673 DefineStd(Builder, "unix", Opts); 674 Builder.defineMacro("__ELF__"); 675 Builder.defineMacro("__ORBIS__"); 676 } 677 public: 678 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 679 : OSTargetInfo<Target>(Triple, Opts) { 680 this->WCharType = this->UnsignedShort; 681 682 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 683 this->MaxTLSAlign = 256; 684 685 // On PS4, do not honor explicit bit field alignment, 686 // as in "__attribute__((aligned(2))) int b : 1;". 687 this->UseExplicitBitFieldAlignment = false; 688 689 switch (Triple.getArch()) { 690 default: 691 case llvm::Triple::x86_64: 692 this->MCountName = ".mcount"; 693 break; 694 } 695 } 696 }; 697 698 // Solaris target 699 template<typename Target> 700 class SolarisTargetInfo : public OSTargetInfo<Target> { 701 protected: 702 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 703 MacroBuilder &Builder) const override { 704 DefineStd(Builder, "sun", Opts); 705 DefineStd(Builder, "unix", Opts); 706 Builder.defineMacro("__ELF__"); 707 Builder.defineMacro("__svr4__"); 708 Builder.defineMacro("__SVR4"); 709 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 710 // newer, but to 500 for everything else. feature_test.h has a check to 711 // ensure that you are not using C99 with an old version of X/Open or C89 712 // with a new version. 713 if (Opts.C99) 714 Builder.defineMacro("_XOPEN_SOURCE", "600"); 715 else 716 Builder.defineMacro("_XOPEN_SOURCE", "500"); 717 if (Opts.CPlusPlus) 718 Builder.defineMacro("__C99FEATURES__"); 719 Builder.defineMacro("_LARGEFILE_SOURCE"); 720 Builder.defineMacro("_LARGEFILE64_SOURCE"); 721 Builder.defineMacro("__EXTENSIONS__"); 722 Builder.defineMacro("_REENTRANT"); 723 } 724 public: 725 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 726 : OSTargetInfo<Target>(Triple, Opts) { 727 this->WCharType = this->SignedInt; 728 // FIXME: WIntType should be SignedLong 729 } 730 }; 731 732 // Windows target 733 template<typename Target> 734 class WindowsTargetInfo : public OSTargetInfo<Target> { 735 protected: 736 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 737 MacroBuilder &Builder) const override { 738 Builder.defineMacro("_WIN32"); 739 } 740 void getVisualStudioDefines(const LangOptions &Opts, 741 MacroBuilder &Builder) const { 742 if (Opts.CPlusPlus) { 743 if (Opts.RTTIData) 744 Builder.defineMacro("_CPPRTTI"); 745 746 if (Opts.CXXExceptions) 747 Builder.defineMacro("_CPPUNWIND"); 748 } 749 750 if (Opts.Bool) 751 Builder.defineMacro("__BOOL_DEFINED"); 752 753 if (!Opts.CharIsSigned) 754 Builder.defineMacro("_CHAR_UNSIGNED"); 755 756 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 757 // but it works for now. 758 if (Opts.POSIXThreads) 759 Builder.defineMacro("_MT"); 760 761 if (Opts.MSCompatibilityVersion) { 762 Builder.defineMacro("_MSC_VER", 763 Twine(Opts.MSCompatibilityVersion / 100000)); 764 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 765 // FIXME We cannot encode the revision information into 32-bits 766 Builder.defineMacro("_MSC_BUILD", Twine(1)); 767 768 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 769 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 770 771 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 772 if (Opts.CPlusPlus1z) 773 Builder.defineMacro("_MSVC_LANG", "201403L"); 774 else if (Opts.CPlusPlus14) 775 Builder.defineMacro("_MSVC_LANG", "201402L"); 776 } 777 } 778 779 if (Opts.MicrosoftExt) { 780 Builder.defineMacro("_MSC_EXTENSIONS"); 781 782 if (Opts.CPlusPlus11) { 783 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 784 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 785 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 786 } 787 } 788 789 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 790 } 791 792 public: 793 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 794 : OSTargetInfo<Target>(Triple, Opts) {} 795 }; 796 797 template <typename Target> 798 class NaClTargetInfo : public OSTargetInfo<Target> { 799 protected: 800 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 801 MacroBuilder &Builder) const override { 802 if (Opts.POSIXThreads) 803 Builder.defineMacro("_REENTRANT"); 804 if (Opts.CPlusPlus) 805 Builder.defineMacro("_GNU_SOURCE"); 806 807 DefineStd(Builder, "unix", Opts); 808 Builder.defineMacro("__ELF__"); 809 Builder.defineMacro("__native_client__"); 810 } 811 812 public: 813 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 814 : OSTargetInfo<Target>(Triple, Opts) { 815 this->LongAlign = 32; 816 this->LongWidth = 32; 817 this->PointerAlign = 32; 818 this->PointerWidth = 32; 819 this->IntMaxType = TargetInfo::SignedLongLong; 820 this->Int64Type = TargetInfo::SignedLongLong; 821 this->DoubleAlign = 64; 822 this->LongDoubleWidth = 64; 823 this->LongDoubleAlign = 64; 824 this->LongLongWidth = 64; 825 this->LongLongAlign = 64; 826 this->SizeType = TargetInfo::UnsignedInt; 827 this->PtrDiffType = TargetInfo::SignedInt; 828 this->IntPtrType = TargetInfo::SignedInt; 829 // RegParmMax is inherited from the underlying architecture. 830 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 831 if (Triple.getArch() == llvm::Triple::arm) { 832 // Handled in ARM's setABI(). 833 } else if (Triple.getArch() == llvm::Triple::x86) { 834 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 835 } else if (Triple.getArch() == llvm::Triple::x86_64) { 836 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 837 } else if (Triple.getArch() == llvm::Triple::mipsel) { 838 // Handled on mips' setDataLayout. 839 } else { 840 assert(Triple.getArch() == llvm::Triple::le32); 841 this->resetDataLayout("e-p:32:32-i64:64"); 842 } 843 } 844 }; 845 846 // Fuchsia Target 847 template<typename Target> 848 class FuchsiaTargetInfo : public OSTargetInfo<Target> { 849 protected: 850 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 851 MacroBuilder &Builder) const override { 852 Builder.defineMacro("__Fuchsia__"); 853 Builder.defineMacro("__ELF__"); 854 if (Opts.POSIXThreads) 855 Builder.defineMacro("_REENTRANT"); 856 // Required by the libc++ locale support. 857 if (Opts.CPlusPlus) 858 Builder.defineMacro("_GNU_SOURCE"); 859 } 860 public: 861 FuchsiaTargetInfo(const llvm::Triple &Triple, 862 const TargetOptions &Opts) 863 : OSTargetInfo<Target>(Triple, Opts) { 864 this->MCountName = "__mcount"; 865 } 866 }; 867 868 // WebAssembly target 869 template <typename Target> 870 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 871 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 872 MacroBuilder &Builder) const final { 873 // A common platform macro. 874 if (Opts.POSIXThreads) 875 Builder.defineMacro("_REENTRANT"); 876 // Follow g++ convention and predefine _GNU_SOURCE for C++. 877 if (Opts.CPlusPlus) 878 Builder.defineMacro("_GNU_SOURCE"); 879 } 880 881 // As an optimization, group static init code together in a section. 882 const char *getStaticInitSectionSpecifier() const final { 883 return ".text.__startup"; 884 } 885 886 public: 887 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 888 const TargetOptions &Opts) 889 : OSTargetInfo<Target>(Triple, Opts) { 890 this->MCountName = "__mcount"; 891 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 892 } 893 }; 894 895 //===----------------------------------------------------------------------===// 896 // Specific target implementations. 897 //===----------------------------------------------------------------------===// 898 899 // PPC abstract base class 900 class PPCTargetInfo : public TargetInfo { 901 static const Builtin::Info BuiltinInfo[]; 902 static const char * const GCCRegNames[]; 903 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 904 std::string CPU; 905 906 // Target cpu features. 907 bool HasAltivec; 908 bool HasVSX; 909 bool HasP8Vector; 910 bool HasP8Crypto; 911 bool HasDirectMove; 912 bool HasQPX; 913 bool HasHTM; 914 bool HasBPERMD; 915 bool HasExtDiv; 916 bool HasP9Vector; 917 918 protected: 919 std::string ABI; 920 921 public: 922 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 923 : TargetInfo(Triple), HasAltivec(false), HasVSX(false), HasP8Vector(false), 924 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 925 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) { 926 SuitableAlign = 128; 927 SimdDefaultAlign = 128; 928 LongDoubleWidth = LongDoubleAlign = 128; 929 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 930 } 931 932 /// \brief Flags for architecture specific defines. 933 typedef enum { 934 ArchDefineNone = 0, 935 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 936 ArchDefinePpcgr = 1 << 1, 937 ArchDefinePpcsq = 1 << 2, 938 ArchDefine440 = 1 << 3, 939 ArchDefine603 = 1 << 4, 940 ArchDefine604 = 1 << 5, 941 ArchDefinePwr4 = 1 << 6, 942 ArchDefinePwr5 = 1 << 7, 943 ArchDefinePwr5x = 1 << 8, 944 ArchDefinePwr6 = 1 << 9, 945 ArchDefinePwr6x = 1 << 10, 946 ArchDefinePwr7 = 1 << 11, 947 ArchDefinePwr8 = 1 << 12, 948 ArchDefinePwr9 = 1 << 13, 949 ArchDefineA2 = 1 << 14, 950 ArchDefineA2q = 1 << 15 951 } ArchDefineTypes; 952 953 // Set the language option for altivec based on our value. 954 void adjust(LangOptions &Opts) override { 955 if (HasAltivec) 956 Opts.AltiVec = 1; 957 TargetInfo::adjust(Opts); 958 } 959 960 // Note: GCC recognizes the following additional cpus: 961 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 962 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 963 // titan, rs64. 964 bool setCPU(const std::string &Name) override { 965 bool CPUKnown = llvm::StringSwitch<bool>(Name) 966 .Case("generic", true) 967 .Case("440", true) 968 .Case("450", true) 969 .Case("601", true) 970 .Case("602", true) 971 .Case("603", true) 972 .Case("603e", true) 973 .Case("603ev", true) 974 .Case("604", true) 975 .Case("604e", true) 976 .Case("620", true) 977 .Case("630", true) 978 .Case("g3", true) 979 .Case("7400", true) 980 .Case("g4", true) 981 .Case("7450", true) 982 .Case("g4+", true) 983 .Case("750", true) 984 .Case("970", true) 985 .Case("g5", true) 986 .Case("a2", true) 987 .Case("a2q", true) 988 .Case("e500mc", true) 989 .Case("e5500", true) 990 .Case("power3", true) 991 .Case("pwr3", true) 992 .Case("power4", true) 993 .Case("pwr4", true) 994 .Case("power5", true) 995 .Case("pwr5", true) 996 .Case("power5x", true) 997 .Case("pwr5x", true) 998 .Case("power6", true) 999 .Case("pwr6", true) 1000 .Case("power6x", true) 1001 .Case("pwr6x", true) 1002 .Case("power7", true) 1003 .Case("pwr7", true) 1004 .Case("power8", true) 1005 .Case("pwr8", true) 1006 .Case("power9", true) 1007 .Case("pwr9", true) 1008 .Case("powerpc", true) 1009 .Case("ppc", true) 1010 .Case("powerpc64", true) 1011 .Case("ppc64", true) 1012 .Case("powerpc64le", true) 1013 .Case("ppc64le", true) 1014 .Default(false); 1015 1016 if (CPUKnown) 1017 CPU = Name; 1018 1019 return CPUKnown; 1020 } 1021 1022 1023 StringRef getABI() const override { return ABI; } 1024 1025 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1026 return llvm::makeArrayRef(BuiltinInfo, 1027 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 1028 } 1029 1030 bool isCLZForZeroUndef() const override { return false; } 1031 1032 void getTargetDefines(const LangOptions &Opts, 1033 MacroBuilder &Builder) const override; 1034 1035 bool 1036 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1037 StringRef CPU, 1038 const std::vector<std::string> &FeaturesVec) const override; 1039 1040 bool handleTargetFeatures(std::vector<std::string> &Features, 1041 DiagnosticsEngine &Diags) override; 1042 bool hasFeature(StringRef Feature) const override; 1043 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 1044 bool Enabled) const override; 1045 1046 ArrayRef<const char *> getGCCRegNames() const override; 1047 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 1048 bool validateAsmConstraint(const char *&Name, 1049 TargetInfo::ConstraintInfo &Info) const override { 1050 switch (*Name) { 1051 default: return false; 1052 case 'O': // Zero 1053 break; 1054 case 'b': // Base register 1055 case 'f': // Floating point register 1056 Info.setAllowsRegister(); 1057 break; 1058 // FIXME: The following are added to allow parsing. 1059 // I just took a guess at what the actions should be. 1060 // Also, is more specific checking needed? I.e. specific registers? 1061 case 'd': // Floating point register (containing 64-bit value) 1062 case 'v': // Altivec vector register 1063 Info.setAllowsRegister(); 1064 break; 1065 case 'w': 1066 switch (Name[1]) { 1067 case 'd':// VSX vector register to hold vector double data 1068 case 'f':// VSX vector register to hold vector float data 1069 case 's':// VSX vector register to hold scalar float data 1070 case 'a':// Any VSX register 1071 case 'c':// An individual CR bit 1072 break; 1073 default: 1074 return false; 1075 } 1076 Info.setAllowsRegister(); 1077 Name++; // Skip over 'w'. 1078 break; 1079 case 'h': // `MQ', `CTR', or `LINK' register 1080 case 'q': // `MQ' register 1081 case 'c': // `CTR' register 1082 case 'l': // `LINK' register 1083 case 'x': // `CR' register (condition register) number 0 1084 case 'y': // `CR' register (condition register) 1085 case 'z': // `XER[CA]' carry bit (part of the XER register) 1086 Info.setAllowsRegister(); 1087 break; 1088 case 'I': // Signed 16-bit constant 1089 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1090 // (use `L' instead for SImode constants) 1091 case 'K': // Unsigned 16-bit constant 1092 case 'L': // Signed 16-bit constant shifted left 16 bits 1093 case 'M': // Constant larger than 31 1094 case 'N': // Exact power of 2 1095 case 'P': // Constant whose negation is a signed 16-bit constant 1096 case 'G': // Floating point constant that can be loaded into a 1097 // register with one instruction per word 1098 case 'H': // Integer/Floating point constant that can be loaded 1099 // into a register using three instructions 1100 break; 1101 case 'm': // Memory operand. Note that on PowerPC targets, m can 1102 // include addresses that update the base register. It 1103 // is therefore only safe to use `m' in an asm statement 1104 // if that asm statement accesses the operand exactly once. 1105 // The asm statement must also use `%U<opno>' as a 1106 // placeholder for the "update" flag in the corresponding 1107 // load or store instruction. For example: 1108 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1109 // is correct but: 1110 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1111 // is not. Use es rather than m if you don't want the base 1112 // register to be updated. 1113 case 'e': 1114 if (Name[1] != 's') 1115 return false; 1116 // es: A "stable" memory operand; that is, one which does not 1117 // include any automodification of the base register. Unlike 1118 // `m', this constraint can be used in asm statements that 1119 // might access the operand several times, or that might not 1120 // access it at all. 1121 Info.setAllowsMemory(); 1122 Name++; // Skip over 'e'. 1123 break; 1124 case 'Q': // Memory operand that is an offset from a register (it is 1125 // usually better to use `m' or `es' in asm statements) 1126 case 'Z': // Memory operand that is an indexed or indirect from a 1127 // register (it is usually better to use `m' or `es' in 1128 // asm statements) 1129 Info.setAllowsMemory(); 1130 Info.setAllowsRegister(); 1131 break; 1132 case 'R': // AIX TOC entry 1133 case 'a': // Address operand that is an indexed or indirect from a 1134 // register (`p' is preferable for asm statements) 1135 case 'S': // Constant suitable as a 64-bit mask operand 1136 case 'T': // Constant suitable as a 32-bit mask operand 1137 case 'U': // System V Release 4 small data area reference 1138 case 't': // AND masks that can be performed by two rldic{l, r} 1139 // instructions 1140 case 'W': // Vector constant that does not require memory 1141 case 'j': // Vector constant that is all zeros. 1142 break; 1143 // End FIXME. 1144 } 1145 return true; 1146 } 1147 std::string convertConstraint(const char *&Constraint) const override { 1148 std::string R; 1149 switch (*Constraint) { 1150 case 'e': 1151 case 'w': 1152 // Two-character constraint; add "^" hint for later parsing. 1153 R = std::string("^") + std::string(Constraint, 2); 1154 Constraint++; 1155 break; 1156 default: 1157 return TargetInfo::convertConstraint(Constraint); 1158 } 1159 return R; 1160 } 1161 const char *getClobbers() const override { 1162 return ""; 1163 } 1164 int getEHDataRegisterNumber(unsigned RegNo) const override { 1165 if (RegNo == 0) return 3; 1166 if (RegNo == 1) return 4; 1167 return -1; 1168 } 1169 1170 bool hasSjLjLowering() const override { 1171 return true; 1172 } 1173 1174 bool useFloat128ManglingForLongDouble() const override { 1175 return LongDoubleWidth == 128 && 1176 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() && 1177 getTriple().isOSBinFormatELF(); 1178 } 1179 }; 1180 1181 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1182 #define BUILTIN(ID, TYPE, ATTRS) \ 1183 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1184 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1185 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1186 #include "clang/Basic/BuiltinsPPC.def" 1187 }; 1188 1189 /// handleTargetFeatures - Perform initialization based on the user 1190 /// configured set of features. 1191 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1192 DiagnosticsEngine &Diags) { 1193 for (const auto &Feature : Features) { 1194 if (Feature == "+altivec") { 1195 HasAltivec = true; 1196 } else if (Feature == "+vsx") { 1197 HasVSX = true; 1198 } else if (Feature == "+bpermd") { 1199 HasBPERMD = true; 1200 } else if (Feature == "+extdiv") { 1201 HasExtDiv = true; 1202 } else if (Feature == "+power8-vector") { 1203 HasP8Vector = true; 1204 } else if (Feature == "+crypto") { 1205 HasP8Crypto = true; 1206 } else if (Feature == "+direct-move") { 1207 HasDirectMove = true; 1208 } else if (Feature == "+qpx") { 1209 HasQPX = true; 1210 } else if (Feature == "+htm") { 1211 HasHTM = true; 1212 } else if (Feature == "+float128") { 1213 HasFloat128 = true; 1214 } else if (Feature == "+power9-vector") { 1215 HasP9Vector = true; 1216 } 1217 // TODO: Finish this list and add an assert that we've handled them 1218 // all. 1219 } 1220 1221 return true; 1222 } 1223 1224 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1225 /// #defines that are not tied to a specific subtarget. 1226 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1227 MacroBuilder &Builder) const { 1228 // Target identification. 1229 Builder.defineMacro("__ppc__"); 1230 Builder.defineMacro("__PPC__"); 1231 Builder.defineMacro("_ARCH_PPC"); 1232 Builder.defineMacro("__powerpc__"); 1233 Builder.defineMacro("__POWERPC__"); 1234 if (PointerWidth == 64) { 1235 Builder.defineMacro("_ARCH_PPC64"); 1236 Builder.defineMacro("__powerpc64__"); 1237 Builder.defineMacro("__ppc64__"); 1238 Builder.defineMacro("__PPC64__"); 1239 } 1240 1241 // Target properties. 1242 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1243 Builder.defineMacro("_LITTLE_ENDIAN"); 1244 } else { 1245 if (getTriple().getOS() != llvm::Triple::NetBSD && 1246 getTriple().getOS() != llvm::Triple::OpenBSD) 1247 Builder.defineMacro("_BIG_ENDIAN"); 1248 } 1249 1250 // ABI options. 1251 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1252 Builder.defineMacro("_CALL_ELF", "1"); 1253 if (ABI == "elfv2") 1254 Builder.defineMacro("_CALL_ELF", "2"); 1255 1256 // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but 1257 // our suppport post-dates this and it should work on all 64-bit ppc linux 1258 // platforms. It is guaranteed to work on all elfv2 platforms. 1259 if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64) 1260 Builder.defineMacro("_CALL_LINUX", "1"); 1261 1262 // Subtarget options. 1263 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1264 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1265 1266 // FIXME: Should be controlled by command line option. 1267 if (LongDoubleWidth == 128) { 1268 Builder.defineMacro("__LONG_DOUBLE_128__"); 1269 Builder.defineMacro("__LONGDOUBLE128"); 1270 } 1271 1272 // Define this for elfv2 (64-bit only) or 64-bit darwin. 1273 if (ABI == "elfv2" || 1274 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64)) 1275 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16"); 1276 1277 // CPU identification. 1278 ArchDefineTypes defs = 1279 (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1280 .Case("440", ArchDefineName) 1281 .Case("450", ArchDefineName | ArchDefine440) 1282 .Case("601", ArchDefineName) 1283 .Case("602", ArchDefineName | ArchDefinePpcgr) 1284 .Case("603", ArchDefineName | ArchDefinePpcgr) 1285 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1286 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1287 .Case("604", ArchDefineName | ArchDefinePpcgr) 1288 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1289 .Case("620", ArchDefineName | ArchDefinePpcgr) 1290 .Case("630", ArchDefineName | ArchDefinePpcgr) 1291 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1292 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1293 .Case("750", ArchDefineName | ArchDefinePpcgr) 1294 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1295 ArchDefinePpcsq) 1296 .Case("a2", ArchDefineA2) 1297 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1298 .Case("pwr3", ArchDefinePpcgr) 1299 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1300 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1301 ArchDefinePpcsq) 1302 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 | 1303 ArchDefinePpcgr | ArchDefinePpcsq) 1304 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 | 1305 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1306 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x | 1307 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1308 ArchDefinePpcsq) 1309 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 | 1310 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1311 ArchDefinePpcgr | ArchDefinePpcsq) 1312 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x | 1313 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1314 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1315 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 | 1316 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1317 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1318 ArchDefinePpcsq) 1319 .Case("power3", ArchDefinePpcgr) 1320 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1321 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1322 ArchDefinePpcsq) 1323 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1324 ArchDefinePpcgr | ArchDefinePpcsq) 1325 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1326 ArchDefinePwr4 | ArchDefinePpcgr | 1327 ArchDefinePpcsq) 1328 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1329 ArchDefinePwr5 | ArchDefinePwr4 | 1330 ArchDefinePpcgr | ArchDefinePpcsq) 1331 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 | 1332 ArchDefinePwr5x | ArchDefinePwr5 | 1333 ArchDefinePwr4 | ArchDefinePpcgr | 1334 ArchDefinePpcsq) 1335 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1336 ArchDefinePwr6 | ArchDefinePwr5x | 1337 ArchDefinePwr5 | ArchDefinePwr4 | 1338 ArchDefinePpcgr | ArchDefinePpcsq) 1339 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 1340 ArchDefinePwr6x | ArchDefinePwr6 | 1341 ArchDefinePwr5x | ArchDefinePwr5 | 1342 ArchDefinePwr4 | ArchDefinePpcgr | 1343 ArchDefinePpcsq) 1344 // powerpc64le automatically defaults to at least power8. 1345 .Case("ppc64le", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1346 ArchDefinePwr6 | ArchDefinePwr5x | 1347 ArchDefinePwr5 | ArchDefinePwr4 | 1348 ArchDefinePpcgr | ArchDefinePpcsq) 1349 .Default(ArchDefineNone); 1350 1351 if (defs & ArchDefineName) 1352 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1353 if (defs & ArchDefinePpcgr) 1354 Builder.defineMacro("_ARCH_PPCGR"); 1355 if (defs & ArchDefinePpcsq) 1356 Builder.defineMacro("_ARCH_PPCSQ"); 1357 if (defs & ArchDefine440) 1358 Builder.defineMacro("_ARCH_440"); 1359 if (defs & ArchDefine603) 1360 Builder.defineMacro("_ARCH_603"); 1361 if (defs & ArchDefine604) 1362 Builder.defineMacro("_ARCH_604"); 1363 if (defs & ArchDefinePwr4) 1364 Builder.defineMacro("_ARCH_PWR4"); 1365 if (defs & ArchDefinePwr5) 1366 Builder.defineMacro("_ARCH_PWR5"); 1367 if (defs & ArchDefinePwr5x) 1368 Builder.defineMacro("_ARCH_PWR5X"); 1369 if (defs & ArchDefinePwr6) 1370 Builder.defineMacro("_ARCH_PWR6"); 1371 if (defs & ArchDefinePwr6x) 1372 Builder.defineMacro("_ARCH_PWR6X"); 1373 if (defs & ArchDefinePwr7) 1374 Builder.defineMacro("_ARCH_PWR7"); 1375 if (defs & ArchDefinePwr8) 1376 Builder.defineMacro("_ARCH_PWR8"); 1377 if (defs & ArchDefinePwr9) 1378 Builder.defineMacro("_ARCH_PWR9"); 1379 if (defs & ArchDefineA2) 1380 Builder.defineMacro("_ARCH_A2"); 1381 if (defs & ArchDefineA2q) { 1382 Builder.defineMacro("_ARCH_A2Q"); 1383 Builder.defineMacro("_ARCH_QP"); 1384 } 1385 1386 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1387 Builder.defineMacro("__bg__"); 1388 Builder.defineMacro("__THW_BLUEGENE__"); 1389 Builder.defineMacro("__bgq__"); 1390 Builder.defineMacro("__TOS_BGQ__"); 1391 } 1392 1393 if (HasAltivec) { 1394 Builder.defineMacro("__VEC__", "10206"); 1395 Builder.defineMacro("__ALTIVEC__"); 1396 } 1397 if (HasVSX) 1398 Builder.defineMacro("__VSX__"); 1399 if (HasP8Vector) 1400 Builder.defineMacro("__POWER8_VECTOR__"); 1401 if (HasP8Crypto) 1402 Builder.defineMacro("__CRYPTO__"); 1403 if (HasHTM) 1404 Builder.defineMacro("__HTM__"); 1405 if (HasFloat128) 1406 Builder.defineMacro("__FLOAT128__"); 1407 if (HasP9Vector) 1408 Builder.defineMacro("__POWER9_VECTOR__"); 1409 1410 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1411 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1412 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1413 if (PointerWidth == 64) 1414 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1415 1416 // We have support for the bswap intrinsics so we can define this. 1417 Builder.defineMacro("__HAVE_BSWAP__", "1"); 1418 1419 // FIXME: The following are not yet generated here by Clang, but are 1420 // generated by GCC: 1421 // 1422 // _SOFT_FLOAT_ 1423 // __RECIP_PRECISION__ 1424 // __APPLE_ALTIVEC__ 1425 // __RECIP__ 1426 // __RECIPF__ 1427 // __RSQRTE__ 1428 // __RSQRTEF__ 1429 // _SOFT_DOUBLE_ 1430 // __NO_LWSYNC__ 1431 // __CMODEL_MEDIUM__ 1432 // __CMODEL_LARGE__ 1433 // _CALL_SYSV 1434 // _CALL_DARWIN 1435 // __NO_FPRS__ 1436 } 1437 1438 // Handle explicit options being passed to the compiler here: if we've 1439 // explicitly turned off vsx and turned on any of: 1440 // - power8-vector 1441 // - direct-move 1442 // - float128 1443 // - power9-vector 1444 // then go ahead and error since the customer has expressed an incompatible 1445 // set of options. 1446 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1447 const std::vector<std::string> &FeaturesVec) { 1448 1449 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1450 FeaturesVec.end()) { 1451 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1452 FeaturesVec.end()) { 1453 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1454 << "-mno-vsx"; 1455 return false; 1456 } 1457 1458 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1459 FeaturesVec.end()) { 1460 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1461 << "-mno-vsx"; 1462 return false; 1463 } 1464 1465 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1466 FeaturesVec.end()) { 1467 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1468 << "-mno-vsx"; 1469 return false; 1470 } 1471 1472 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") != 1473 FeaturesVec.end()) { 1474 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector" 1475 << "-mno-vsx"; 1476 return false; 1477 } 1478 } 1479 1480 return true; 1481 } 1482 1483 bool PPCTargetInfo::initFeatureMap( 1484 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1485 const std::vector<std::string> &FeaturesVec) const { 1486 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1487 .Case("7400", true) 1488 .Case("g4", true) 1489 .Case("7450", true) 1490 .Case("g4+", true) 1491 .Case("970", true) 1492 .Case("g5", true) 1493 .Case("pwr6", true) 1494 .Case("pwr7", true) 1495 .Case("pwr8", true) 1496 .Case("pwr9", true) 1497 .Case("ppc64", true) 1498 .Case("ppc64le", true) 1499 .Default(false); 1500 1501 Features["qpx"] = (CPU == "a2q"); 1502 Features["power9-vector"] = (CPU == "pwr9"); 1503 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1504 .Case("ppc64le", true) 1505 .Case("pwr9", true) 1506 .Case("pwr8", true) 1507 .Default(false); 1508 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1509 .Case("ppc64le", true) 1510 .Case("pwr9", true) 1511 .Case("pwr8", true) 1512 .Default(false); 1513 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1514 .Case("ppc64le", true) 1515 .Case("pwr9", true) 1516 .Case("pwr8", true) 1517 .Case("pwr7", true) 1518 .Default(false); 1519 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1520 .Case("ppc64le", true) 1521 .Case("pwr9", true) 1522 .Case("pwr8", true) 1523 .Case("pwr7", true) 1524 .Default(false); 1525 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1526 .Case("ppc64le", true) 1527 .Case("pwr9", true) 1528 .Case("pwr8", true) 1529 .Default(false); 1530 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1531 .Case("ppc64le", true) 1532 .Case("pwr9", true) 1533 .Case("pwr8", true) 1534 .Case("pwr7", true) 1535 .Default(false); 1536 Features["htm"] = llvm::StringSwitch<bool>(CPU) 1537 .Case("ppc64le", true) 1538 .Case("pwr9", true) 1539 .Case("pwr8", true) 1540 .Default(false); 1541 1542 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1543 return false; 1544 1545 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1546 } 1547 1548 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1549 return llvm::StringSwitch<bool>(Feature) 1550 .Case("powerpc", true) 1551 .Case("altivec", HasAltivec) 1552 .Case("vsx", HasVSX) 1553 .Case("power8-vector", HasP8Vector) 1554 .Case("crypto", HasP8Crypto) 1555 .Case("direct-move", HasDirectMove) 1556 .Case("qpx", HasQPX) 1557 .Case("htm", HasHTM) 1558 .Case("bpermd", HasBPERMD) 1559 .Case("extdiv", HasExtDiv) 1560 .Case("float128", HasFloat128) 1561 .Case("power9-vector", HasP9Vector) 1562 .Default(false); 1563 } 1564 1565 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1566 StringRef Name, bool Enabled) const { 1567 if (Enabled) { 1568 // If we're enabling any of the vsx based features then enable vsx and 1569 // altivec. We'll diagnose any problems later. 1570 bool FeatureHasVSX = llvm::StringSwitch<bool>(Name) 1571 .Case("vsx", true) 1572 .Case("direct-move", true) 1573 .Case("power8-vector", true) 1574 .Case("power9-vector", true) 1575 .Case("float128", true) 1576 .Default(false); 1577 if (FeatureHasVSX) 1578 Features["vsx"] = Features["altivec"] = true; 1579 if (Name == "power9-vector") 1580 Features["power8-vector"] = true; 1581 Features[Name] = true; 1582 } else { 1583 // If we're disabling altivec or vsx go ahead and disable all of the vsx 1584 // features. 1585 if ((Name == "altivec") || (Name == "vsx")) 1586 Features["vsx"] = Features["direct-move"] = Features["power8-vector"] = 1587 Features["float128"] = Features["power9-vector"] = false; 1588 if (Name == "power8-vector") 1589 Features["power9-vector"] = false; 1590 Features[Name] = false; 1591 } 1592 } 1593 1594 const char * const PPCTargetInfo::GCCRegNames[] = { 1595 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1596 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1597 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1598 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1599 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1600 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1601 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1602 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1603 "mq", "lr", "ctr", "ap", 1604 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1605 "xer", 1606 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1607 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1608 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1609 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1610 "vrsave", "vscr", 1611 "spe_acc", "spefscr", 1612 "sfp" 1613 }; 1614 1615 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1616 return llvm::makeArrayRef(GCCRegNames); 1617 } 1618 1619 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1620 // While some of these aliases do map to different registers 1621 // they still share the same register name. 1622 { { "0" }, "r0" }, 1623 { { "1"}, "r1" }, 1624 { { "2" }, "r2" }, 1625 { { "3" }, "r3" }, 1626 { { "4" }, "r4" }, 1627 { { "5" }, "r5" }, 1628 { { "6" }, "r6" }, 1629 { { "7" }, "r7" }, 1630 { { "8" }, "r8" }, 1631 { { "9" }, "r9" }, 1632 { { "10" }, "r10" }, 1633 { { "11" }, "r11" }, 1634 { { "12" }, "r12" }, 1635 { { "13" }, "r13" }, 1636 { { "14" }, "r14" }, 1637 { { "15" }, "r15" }, 1638 { { "16" }, "r16" }, 1639 { { "17" }, "r17" }, 1640 { { "18" }, "r18" }, 1641 { { "19" }, "r19" }, 1642 { { "20" }, "r20" }, 1643 { { "21" }, "r21" }, 1644 { { "22" }, "r22" }, 1645 { { "23" }, "r23" }, 1646 { { "24" }, "r24" }, 1647 { { "25" }, "r25" }, 1648 { { "26" }, "r26" }, 1649 { { "27" }, "r27" }, 1650 { { "28" }, "r28" }, 1651 { { "29" }, "r29" }, 1652 { { "30" }, "r30" }, 1653 { { "31" }, "r31" }, 1654 { { "fr0" }, "f0" }, 1655 { { "fr1" }, "f1" }, 1656 { { "fr2" }, "f2" }, 1657 { { "fr3" }, "f3" }, 1658 { { "fr4" }, "f4" }, 1659 { { "fr5" }, "f5" }, 1660 { { "fr6" }, "f6" }, 1661 { { "fr7" }, "f7" }, 1662 { { "fr8" }, "f8" }, 1663 { { "fr9" }, "f9" }, 1664 { { "fr10" }, "f10" }, 1665 { { "fr11" }, "f11" }, 1666 { { "fr12" }, "f12" }, 1667 { { "fr13" }, "f13" }, 1668 { { "fr14" }, "f14" }, 1669 { { "fr15" }, "f15" }, 1670 { { "fr16" }, "f16" }, 1671 { { "fr17" }, "f17" }, 1672 { { "fr18" }, "f18" }, 1673 { { "fr19" }, "f19" }, 1674 { { "fr20" }, "f20" }, 1675 { { "fr21" }, "f21" }, 1676 { { "fr22" }, "f22" }, 1677 { { "fr23" }, "f23" }, 1678 { { "fr24" }, "f24" }, 1679 { { "fr25" }, "f25" }, 1680 { { "fr26" }, "f26" }, 1681 { { "fr27" }, "f27" }, 1682 { { "fr28" }, "f28" }, 1683 { { "fr29" }, "f29" }, 1684 { { "fr30" }, "f30" }, 1685 { { "fr31" }, "f31" }, 1686 { { "cc" }, "cr0" }, 1687 }; 1688 1689 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1690 return llvm::makeArrayRef(GCCRegAliases); 1691 } 1692 1693 class PPC32TargetInfo : public PPCTargetInfo { 1694 public: 1695 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1696 : PPCTargetInfo(Triple, Opts) { 1697 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1698 1699 switch (getTriple().getOS()) { 1700 case llvm::Triple::Linux: 1701 case llvm::Triple::FreeBSD: 1702 case llvm::Triple::NetBSD: 1703 SizeType = UnsignedInt; 1704 PtrDiffType = SignedInt; 1705 IntPtrType = SignedInt; 1706 break; 1707 default: 1708 break; 1709 } 1710 1711 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1712 LongDoubleWidth = LongDoubleAlign = 64; 1713 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1714 } 1715 1716 // PPC32 supports atomics up to 4 bytes. 1717 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1718 } 1719 1720 BuiltinVaListKind getBuiltinVaListKind() const override { 1721 // This is the ELF definition, and is overridden by the Darwin sub-target 1722 return TargetInfo::PowerABIBuiltinVaList; 1723 } 1724 }; 1725 1726 // Note: ABI differences may eventually require us to have a separate 1727 // TargetInfo for little endian. 1728 class PPC64TargetInfo : public PPCTargetInfo { 1729 public: 1730 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1731 : PPCTargetInfo(Triple, Opts) { 1732 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1733 IntMaxType = SignedLong; 1734 Int64Type = SignedLong; 1735 1736 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1737 resetDataLayout("e-m:e-i64:64-n32:64"); 1738 ABI = "elfv2"; 1739 } else { 1740 resetDataLayout("E-m:e-i64:64-n32:64"); 1741 ABI = "elfv1"; 1742 } 1743 1744 switch (getTriple().getOS()) { 1745 case llvm::Triple::FreeBSD: 1746 LongDoubleWidth = LongDoubleAlign = 64; 1747 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1748 break; 1749 case llvm::Triple::NetBSD: 1750 IntMaxType = SignedLongLong; 1751 Int64Type = SignedLongLong; 1752 break; 1753 default: 1754 break; 1755 } 1756 1757 // PPC64 supports atomics up to 8 bytes. 1758 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1759 } 1760 BuiltinVaListKind getBuiltinVaListKind() const override { 1761 return TargetInfo::CharPtrBuiltinVaList; 1762 } 1763 // PPC64 Linux-specific ABI options. 1764 bool setABI(const std::string &Name) override { 1765 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1766 ABI = Name; 1767 return true; 1768 } 1769 return false; 1770 } 1771 }; 1772 1773 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1774 public: 1775 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1776 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1777 HasAlignMac68kSupport = true; 1778 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1779 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1780 LongLongAlign = 32; 1781 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1782 } 1783 BuiltinVaListKind getBuiltinVaListKind() const override { 1784 return TargetInfo::CharPtrBuiltinVaList; 1785 } 1786 }; 1787 1788 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1789 public: 1790 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1791 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1792 HasAlignMac68kSupport = true; 1793 resetDataLayout("E-m:o-i64:64-n32:64"); 1794 } 1795 }; 1796 1797 static const unsigned NVPTXAddrSpaceMap[] = { 1798 0, // Default 1799 1, // opencl_global 1800 3, // opencl_local 1801 4, // opencl_constant 1802 // FIXME: generic has to be added to the target 1803 0, // opencl_generic 1804 1, // cuda_device 1805 4, // cuda_constant 1806 3, // cuda_shared 1807 }; 1808 1809 class NVPTXTargetInfo : public TargetInfo { 1810 static const char *const GCCRegNames[]; 1811 static const Builtin::Info BuiltinInfo[]; 1812 CudaArch GPU; 1813 std::unique_ptr<TargetInfo> HostTarget; 1814 1815 public: 1816 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 1817 unsigned TargetPointerWidth) 1818 : TargetInfo(Triple) { 1819 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) && 1820 "NVPTX only supports 32- and 64-bit modes."); 1821 1822 TLSSupported = false; 1823 AddrSpaceMap = &NVPTXAddrSpaceMap; 1824 UseAddrSpaceMapMangling = true; 1825 1826 // Define available target features 1827 // These must be defined in sorted order! 1828 NoAsmVariants = true; 1829 GPU = CudaArch::SM_20; 1830 1831 if (TargetPointerWidth == 32) 1832 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1833 else 1834 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1835 1836 // If possible, get a TargetInfo for our host triple, so we can match its 1837 // types. 1838 llvm::Triple HostTriple(Opts.HostTriple); 1839 if (!HostTriple.isNVPTX()) 1840 HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1841 1842 // If no host target, make some guesses about the data layout and return. 1843 if (!HostTarget) { 1844 LongWidth = LongAlign = TargetPointerWidth; 1845 PointerWidth = PointerAlign = TargetPointerWidth; 1846 switch (TargetPointerWidth) { 1847 case 32: 1848 SizeType = TargetInfo::UnsignedInt; 1849 PtrDiffType = TargetInfo::SignedInt; 1850 IntPtrType = TargetInfo::SignedInt; 1851 break; 1852 case 64: 1853 SizeType = TargetInfo::UnsignedLong; 1854 PtrDiffType = TargetInfo::SignedLong; 1855 IntPtrType = TargetInfo::SignedLong; 1856 break; 1857 default: 1858 llvm_unreachable("TargetPointerWidth must be 32 or 64"); 1859 } 1860 return; 1861 } 1862 1863 // Copy properties from host target. 1864 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1865 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1866 BoolWidth = HostTarget->getBoolWidth(); 1867 BoolAlign = HostTarget->getBoolAlign(); 1868 IntWidth = HostTarget->getIntWidth(); 1869 IntAlign = HostTarget->getIntAlign(); 1870 HalfWidth = HostTarget->getHalfWidth(); 1871 HalfAlign = HostTarget->getHalfAlign(); 1872 FloatWidth = HostTarget->getFloatWidth(); 1873 FloatAlign = HostTarget->getFloatAlign(); 1874 DoubleWidth = HostTarget->getDoubleWidth(); 1875 DoubleAlign = HostTarget->getDoubleAlign(); 1876 LongWidth = HostTarget->getLongWidth(); 1877 LongAlign = HostTarget->getLongAlign(); 1878 LongLongWidth = HostTarget->getLongLongWidth(); 1879 LongLongAlign = HostTarget->getLongLongAlign(); 1880 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1881 NewAlign = HostTarget->getNewAlign(); 1882 DefaultAlignForAttributeAligned = 1883 HostTarget->getDefaultAlignForAttributeAligned(); 1884 SizeType = HostTarget->getSizeType(); 1885 IntMaxType = HostTarget->getIntMaxType(); 1886 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1887 IntPtrType = HostTarget->getIntPtrType(); 1888 WCharType = HostTarget->getWCharType(); 1889 WIntType = HostTarget->getWIntType(); 1890 Char16Type = HostTarget->getChar16Type(); 1891 Char32Type = HostTarget->getChar32Type(); 1892 Int64Type = HostTarget->getInt64Type(); 1893 SigAtomicType = HostTarget->getSigAtomicType(); 1894 ProcessIDType = HostTarget->getProcessIDType(); 1895 1896 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1897 UseZeroLengthBitfieldAlignment = 1898 HostTarget->useZeroLengthBitfieldAlignment(); 1899 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1900 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1901 1902 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and 1903 // we need those macros to be identical on host and device, because (among 1904 // other things) they affect which standard library classes are defined, and 1905 // we need all classes to be defined on both the host and device. 1906 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth(); 1907 1908 // Properties intentionally not copied from host: 1909 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1910 // host/device boundary. 1911 // - SuitableAlign: Not visible across the host/device boundary, and may 1912 // correctly be different on host/device, e.g. if host has wider vector 1913 // types than device. 1914 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1915 // as its double type, but that's not necessarily true on the host. 1916 // TODO: nvcc emits a warning when using long double on device; we should 1917 // do the same. 1918 } 1919 void getTargetDefines(const LangOptions &Opts, 1920 MacroBuilder &Builder) const override { 1921 Builder.defineMacro("__PTX__"); 1922 Builder.defineMacro("__NVPTX__"); 1923 if (Opts.CUDAIsDevice) { 1924 // Set __CUDA_ARCH__ for the GPU specified. 1925 std::string CUDAArchCode = [this] { 1926 switch (GPU) { 1927 case CudaArch::UNKNOWN: 1928 assert(false && "No GPU arch when compiling CUDA device code."); 1929 return ""; 1930 case CudaArch::SM_20: 1931 return "200"; 1932 case CudaArch::SM_21: 1933 return "210"; 1934 case CudaArch::SM_30: 1935 return "300"; 1936 case CudaArch::SM_32: 1937 return "320"; 1938 case CudaArch::SM_35: 1939 return "350"; 1940 case CudaArch::SM_37: 1941 return "370"; 1942 case CudaArch::SM_50: 1943 return "500"; 1944 case CudaArch::SM_52: 1945 return "520"; 1946 case CudaArch::SM_53: 1947 return "530"; 1948 case CudaArch::SM_60: 1949 return "600"; 1950 case CudaArch::SM_61: 1951 return "610"; 1952 case CudaArch::SM_62: 1953 return "620"; 1954 } 1955 llvm_unreachable("unhandled CudaArch"); 1956 }(); 1957 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1958 } 1959 } 1960 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1961 return llvm::makeArrayRef(BuiltinInfo, 1962 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1963 } 1964 bool 1965 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1966 StringRef CPU, 1967 const std::vector<std::string> &FeaturesVec) const override { 1968 Features["satom"] = GPU >= CudaArch::SM_60; 1969 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1970 } 1971 1972 bool hasFeature(StringRef Feature) const override { 1973 return llvm::StringSwitch<bool>(Feature) 1974 .Cases("ptx", "nvptx", true) 1975 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope. 1976 .Default(false); 1977 } 1978 1979 ArrayRef<const char *> getGCCRegNames() const override; 1980 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1981 // No aliases. 1982 return None; 1983 } 1984 bool validateAsmConstraint(const char *&Name, 1985 TargetInfo::ConstraintInfo &Info) const override { 1986 switch (*Name) { 1987 default: 1988 return false; 1989 case 'c': 1990 case 'h': 1991 case 'r': 1992 case 'l': 1993 case 'f': 1994 case 'd': 1995 Info.setAllowsRegister(); 1996 return true; 1997 } 1998 } 1999 const char *getClobbers() const override { 2000 // FIXME: Is this really right? 2001 return ""; 2002 } 2003 BuiltinVaListKind getBuiltinVaListKind() const override { 2004 // FIXME: implement 2005 return TargetInfo::CharPtrBuiltinVaList; 2006 } 2007 bool setCPU(const std::string &Name) override { 2008 GPU = StringToCudaArch(Name); 2009 return GPU != CudaArch::UNKNOWN; 2010 } 2011 void setSupportedOpenCLOpts() override { 2012 auto &Opts = getSupportedOpenCLOpts(); 2013 Opts.support("cl_clang_storage_class_specifiers"); 2014 Opts.support("cl_khr_gl_sharing"); 2015 Opts.support("cl_khr_icd"); 2016 2017 Opts.support("cl_khr_fp64"); 2018 Opts.support("cl_khr_byte_addressable_store"); 2019 Opts.support("cl_khr_global_int32_base_atomics"); 2020 Opts.support("cl_khr_global_int32_extended_atomics"); 2021 Opts.support("cl_khr_local_int32_base_atomics"); 2022 Opts.support("cl_khr_local_int32_extended_atomics"); 2023 } 2024 2025 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2026 // CUDA compilations support all of the host's calling conventions. 2027 // 2028 // TODO: We should warn if you apply a non-default CC to anything other than 2029 // a host function. 2030 if (HostTarget) 2031 return HostTarget->checkCallingConvention(CC); 2032 return CCCR_Warning; 2033 } 2034 }; 2035 2036 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 2037 #define BUILTIN(ID, TYPE, ATTRS) \ 2038 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2039 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2040 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2041 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2042 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2043 #include "clang/Basic/BuiltinsNVPTX.def" 2044 }; 2045 2046 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 2047 2048 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 2049 return llvm::makeArrayRef(GCCRegNames); 2050 } 2051 2052 static const LangAS::Map AMDGPUPrivIsZeroDefIsGenMap = { 2053 4, // Default 2054 1, // opencl_global 2055 3, // opencl_local 2056 2, // opencl_constant 2057 4, // opencl_generic 2058 1, // cuda_device 2059 2, // cuda_constant 2060 3 // cuda_shared 2061 }; 2062 static const LangAS::Map AMDGPUGenIsZeroDefIsGenMap = { 2063 0, // Default 2064 1, // opencl_global 2065 3, // opencl_local 2066 2, // opencl_constant 2067 0, // opencl_generic 2068 1, // cuda_device 2069 2, // cuda_constant 2070 3 // cuda_shared 2071 }; 2072 static const LangAS::Map AMDGPUPrivIsZeroDefIsPrivMap = { 2073 0, // Default 2074 1, // opencl_global 2075 3, // opencl_local 2076 2, // opencl_constant 2077 4, // opencl_generic 2078 1, // cuda_device 2079 2, // cuda_constant 2080 3 // cuda_shared 2081 }; 2082 static const LangAS::Map AMDGPUGenIsZeroDefIsPrivMap = { 2083 5, // Default 2084 1, // opencl_global 2085 3, // opencl_local 2086 2, // opencl_constant 2087 0, // opencl_generic 2088 1, // cuda_device 2089 2, // cuda_constant 2090 3 // cuda_shared 2091 }; 2092 2093 // If you edit the description strings, make sure you update 2094 // getPointerWidthV(). 2095 2096 static const char *const DataLayoutStringR600 = 2097 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2098 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2099 2100 static const char *const DataLayoutStringSIPrivateIsZero = 2101 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 2102 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2103 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2104 2105 static const char *const DataLayoutStringSIGenericIsZero = 2106 "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32" 2107 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2108 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"; 2109 2110 class AMDGPUTargetInfo final : public TargetInfo { 2111 static const Builtin::Info BuiltinInfo[]; 2112 static const char * const GCCRegNames[]; 2113 2114 struct AddrSpace { 2115 unsigned Generic, Global, Local, Constant, Private; 2116 AddrSpace(bool IsGenericZero_ = false){ 2117 if (IsGenericZero_) { 2118 Generic = 0; 2119 Global = 1; 2120 Local = 3; 2121 Constant = 2; 2122 Private = 5; 2123 } else { 2124 Generic = 4; 2125 Global = 1; 2126 Local = 3; 2127 Constant = 2; 2128 Private = 0; 2129 } 2130 } 2131 }; 2132 2133 /// \brief The GPU profiles supported by the AMDGPU target. 2134 enum GPUKind { 2135 GK_NONE, 2136 GK_R600, 2137 GK_R600_DOUBLE_OPS, 2138 GK_R700, 2139 GK_R700_DOUBLE_OPS, 2140 GK_EVERGREEN, 2141 GK_EVERGREEN_DOUBLE_OPS, 2142 GK_NORTHERN_ISLANDS, 2143 GK_CAYMAN, 2144 GK_GFX6, 2145 GK_GFX7, 2146 GK_GFX8, 2147 GK_GFX9 2148 } GPU; 2149 2150 bool hasFP64:1; 2151 bool hasFMAF:1; 2152 bool hasLDEXPF:1; 2153 const AddrSpace AS; 2154 2155 static bool hasFullSpeedFMAF32(StringRef GPUName) { 2156 return parseAMDGCNName(GPUName) >= GK_GFX9; 2157 } 2158 2159 static bool isAMDGCN(const llvm::Triple &TT) { 2160 return TT.getArch() == llvm::Triple::amdgcn; 2161 } 2162 2163 static bool isGenericZero(const llvm::Triple &TT) { 2164 return TT.getEnvironmentName() == "amdgiz" || 2165 TT.getEnvironmentName() == "amdgizcl"; 2166 } 2167 public: 2168 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 2169 : TargetInfo(Triple) , 2170 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600), 2171 hasFP64(false), 2172 hasFMAF(false), 2173 hasLDEXPF(false), 2174 AS(isGenericZero(Triple)){ 2175 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2176 hasFP64 = true; 2177 hasFMAF = true; 2178 hasLDEXPF = true; 2179 } 2180 auto IsGenericZero = isGenericZero(Triple); 2181 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 2182 (IsGenericZero ? DataLayoutStringSIGenericIsZero : 2183 DataLayoutStringSIPrivateIsZero) 2184 : DataLayoutStringR600); 2185 assert(DataLayout->getAllocaAddrSpace() == AS.Private); 2186 2187 setAddressSpaceMap(Triple.getOS() == llvm::Triple::Mesa3D || 2188 Triple.getEnvironment() == llvm::Triple::OpenCL || 2189 Triple.getEnvironmentName() == "amdgizcl" || 2190 !isAMDGCN(Triple)); 2191 UseAddrSpaceMapMangling = true; 2192 2193 // Set pointer width and alignment for target address space 0. 2194 PointerWidth = PointerAlign = DataLayout->getPointerSizeInBits(); 2195 if (getMaxPointerWidth() == 64) { 2196 LongWidth = LongAlign = 64; 2197 SizeType = UnsignedLong; 2198 PtrDiffType = SignedLong; 2199 IntPtrType = SignedLong; 2200 } 2201 } 2202 2203 void setAddressSpaceMap(bool DefaultIsPrivate) { 2204 if (isGenericZero(getTriple())) { 2205 AddrSpaceMap = DefaultIsPrivate ? &AMDGPUGenIsZeroDefIsPrivMap 2206 : &AMDGPUGenIsZeroDefIsGenMap; 2207 } else { 2208 AddrSpaceMap = DefaultIsPrivate ? &AMDGPUPrivIsZeroDefIsPrivMap 2209 : &AMDGPUPrivIsZeroDefIsGenMap; 2210 } 2211 } 2212 2213 void adjust(LangOptions &Opts) override { 2214 TargetInfo::adjust(Opts); 2215 setAddressSpaceMap(Opts.OpenCL || !isAMDGCN(getTriple())); 2216 } 2217 2218 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 2219 if (GPU <= GK_CAYMAN) 2220 return 32; 2221 2222 if (AddrSpace == AS.Private || AddrSpace == AS.Local) { 2223 return 32; 2224 } 2225 return 64; 2226 } 2227 2228 uint64_t getPointerAlignV(unsigned AddrSpace) const override { 2229 return getPointerWidthV(AddrSpace); 2230 } 2231 2232 uint64_t getMaxPointerWidth() const override { 2233 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2234 } 2235 2236 const char * getClobbers() const override { 2237 return ""; 2238 } 2239 2240 ArrayRef<const char *> getGCCRegNames() const override; 2241 2242 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2243 return None; 2244 } 2245 2246 bool validateAsmConstraint(const char *&Name, 2247 TargetInfo::ConstraintInfo &Info) const override { 2248 switch (*Name) { 2249 default: break; 2250 case 'v': // vgpr 2251 case 's': // sgpr 2252 Info.setAllowsRegister(); 2253 return true; 2254 } 2255 return false; 2256 } 2257 2258 bool initFeatureMap(llvm::StringMap<bool> &Features, 2259 DiagnosticsEngine &Diags, StringRef CPU, 2260 const std::vector<std::string> &FeatureVec) const override; 2261 2262 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2263 TargetOptions &TargetOpts) const override { 2264 bool hasFP32Denormals = false; 2265 bool hasFP64Denormals = false; 2266 for (auto &I : TargetOpts.FeaturesAsWritten) { 2267 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2268 hasFP32Denormals = true; 2269 if (I == "+fp64-fp16-denormals" || I == "-fp64-fp16-denormals") 2270 hasFP64Denormals = true; 2271 } 2272 if (!hasFP32Denormals) 2273 TargetOpts.Features.push_back( 2274 (Twine(hasFullSpeedFMAF32(TargetOpts.CPU) && 2275 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str()); 2276 // Always do not flush fp64 or fp16 denorms. 2277 if (!hasFP64Denormals && hasFP64) 2278 TargetOpts.Features.push_back("+fp64-fp16-denormals"); 2279 } 2280 2281 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2282 return llvm::makeArrayRef(BuiltinInfo, 2283 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2284 } 2285 2286 void getTargetDefines(const LangOptions &Opts, 2287 MacroBuilder &Builder) const override { 2288 if (getTriple().getArch() == llvm::Triple::amdgcn) 2289 Builder.defineMacro("__AMDGCN__"); 2290 else 2291 Builder.defineMacro("__R600__"); 2292 2293 if (hasFMAF) 2294 Builder.defineMacro("__HAS_FMAF__"); 2295 if (hasLDEXPF) 2296 Builder.defineMacro("__HAS_LDEXPF__"); 2297 if (hasFP64) 2298 Builder.defineMacro("__HAS_FP64__"); 2299 } 2300 2301 BuiltinVaListKind getBuiltinVaListKind() const override { 2302 return TargetInfo::CharPtrBuiltinVaList; 2303 } 2304 2305 static GPUKind parseR600Name(StringRef Name) { 2306 return llvm::StringSwitch<GPUKind>(Name) 2307 .Case("r600" , GK_R600) 2308 .Case("rv610", GK_R600) 2309 .Case("rv620", GK_R600) 2310 .Case("rv630", GK_R600) 2311 .Case("rv635", GK_R600) 2312 .Case("rs780", GK_R600) 2313 .Case("rs880", GK_R600) 2314 .Case("rv670", GK_R600_DOUBLE_OPS) 2315 .Case("rv710", GK_R700) 2316 .Case("rv730", GK_R700) 2317 .Case("rv740", GK_R700_DOUBLE_OPS) 2318 .Case("rv770", GK_R700_DOUBLE_OPS) 2319 .Case("palm", GK_EVERGREEN) 2320 .Case("cedar", GK_EVERGREEN) 2321 .Case("sumo", GK_EVERGREEN) 2322 .Case("sumo2", GK_EVERGREEN) 2323 .Case("redwood", GK_EVERGREEN) 2324 .Case("juniper", GK_EVERGREEN) 2325 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2326 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2327 .Case("barts", GK_NORTHERN_ISLANDS) 2328 .Case("turks", GK_NORTHERN_ISLANDS) 2329 .Case("caicos", GK_NORTHERN_ISLANDS) 2330 .Case("cayman", GK_CAYMAN) 2331 .Case("aruba", GK_CAYMAN) 2332 .Default(GK_NONE); 2333 } 2334 2335 static GPUKind parseAMDGCNName(StringRef Name) { 2336 return llvm::StringSwitch<GPUKind>(Name) 2337 .Case("tahiti", GK_GFX6) 2338 .Case("pitcairn", GK_GFX6) 2339 .Case("verde", GK_GFX6) 2340 .Case("oland", GK_GFX6) 2341 .Case("hainan", GK_GFX6) 2342 .Case("bonaire", GK_GFX7) 2343 .Case("kabini", GK_GFX7) 2344 .Case("kaveri", GK_GFX7) 2345 .Case("hawaii", GK_GFX7) 2346 .Case("mullins", GK_GFX7) 2347 .Case("gfx700", GK_GFX7) 2348 .Case("gfx701", GK_GFX7) 2349 .Case("gfx702", GK_GFX7) 2350 .Case("tonga", GK_GFX8) 2351 .Case("iceland", GK_GFX8) 2352 .Case("carrizo", GK_GFX8) 2353 .Case("fiji", GK_GFX8) 2354 .Case("stoney", GK_GFX8) 2355 .Case("polaris10", GK_GFX8) 2356 .Case("polaris11", GK_GFX8) 2357 .Case("gfx800", GK_GFX8) 2358 .Case("gfx801", GK_GFX8) 2359 .Case("gfx802", GK_GFX8) 2360 .Case("gfx803", GK_GFX8) 2361 .Case("gfx804", GK_GFX8) 2362 .Case("gfx810", GK_GFX8) 2363 .Case("gfx900", GK_GFX9) 2364 .Case("gfx901", GK_GFX9) 2365 .Default(GK_NONE); 2366 } 2367 2368 bool setCPU(const std::string &Name) override { 2369 if (getTriple().getArch() == llvm::Triple::amdgcn) 2370 GPU = parseAMDGCNName(Name); 2371 else 2372 GPU = parseR600Name(Name); 2373 2374 return GPU != GK_NONE; 2375 } 2376 2377 void setSupportedOpenCLOpts() override { 2378 auto &Opts = getSupportedOpenCLOpts(); 2379 Opts.support("cl_clang_storage_class_specifiers"); 2380 Opts.support("cl_khr_icd"); 2381 2382 if (hasFP64) 2383 Opts.support("cl_khr_fp64"); 2384 if (GPU >= GK_EVERGREEN) { 2385 Opts.support("cl_khr_byte_addressable_store"); 2386 Opts.support("cl_khr_global_int32_base_atomics"); 2387 Opts.support("cl_khr_global_int32_extended_atomics"); 2388 Opts.support("cl_khr_local_int32_base_atomics"); 2389 Opts.support("cl_khr_local_int32_extended_atomics"); 2390 } 2391 if (GPU >= GK_GFX6) { 2392 Opts.support("cl_khr_fp16"); 2393 Opts.support("cl_khr_int64_base_atomics"); 2394 Opts.support("cl_khr_int64_extended_atomics"); 2395 Opts.support("cl_khr_mipmap_image"); 2396 Opts.support("cl_khr_subgroups"); 2397 Opts.support("cl_khr_3d_image_writes"); 2398 Opts.support("cl_amd_media_ops"); 2399 Opts.support("cl_amd_media_ops2"); 2400 } 2401 } 2402 2403 LangAS::ID getOpenCLImageAddrSpace() const override { 2404 return LangAS::opencl_constant; 2405 } 2406 2407 /// \returns Target specific vtbl ptr address space. 2408 unsigned getVtblPtrAddressSpace() const override { return AS.Constant; } 2409 2410 /// \returns If a target requires an address within a target specific address 2411 /// space \p AddressSpace to be converted in order to be used, then return the 2412 /// corresponding target specific DWARF address space. 2413 /// 2414 /// \returns Otherwise return None and no conversion will be emitted in the 2415 /// DWARF. 2416 Optional<unsigned> getDWARFAddressSpace( 2417 unsigned AddressSpace) const override { 2418 const unsigned DWARF_Private = 1; 2419 const unsigned DWARF_Local = 2; 2420 if (AddressSpace == AS.Private) { 2421 return DWARF_Private; 2422 } else if (AddressSpace == AS.Local) { 2423 return DWARF_Local; 2424 } else { 2425 return None; 2426 } 2427 } 2428 2429 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2430 switch (CC) { 2431 default: 2432 return CCCR_Warning; 2433 case CC_C: 2434 case CC_OpenCLKernel: 2435 return CCCR_OK; 2436 } 2437 } 2438 2439 // In amdgcn target the null pointer in global, constant, and generic 2440 // address space has value 0 but in private and local address space has 2441 // value ~0. 2442 uint64_t getNullPointerValue(unsigned AS) const override { 2443 return AS == LangAS::opencl_local ? ~0 : 0; 2444 } 2445 }; 2446 2447 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2448 #define BUILTIN(ID, TYPE, ATTRS) \ 2449 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2450 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2451 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2452 #include "clang/Basic/BuiltinsAMDGPU.def" 2453 }; 2454 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2455 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2456 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2457 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2458 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2459 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2460 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2461 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2462 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2463 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2464 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2465 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2466 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2467 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2468 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2469 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2470 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2471 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2472 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2473 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2474 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2475 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2476 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2477 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2478 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2479 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2480 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2481 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2482 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2483 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2484 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2485 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2486 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2487 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2488 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2489 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2490 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2491 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2492 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2493 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2494 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2495 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2496 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2497 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2498 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2499 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2500 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2501 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2502 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2503 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2504 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2505 }; 2506 2507 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2508 return llvm::makeArrayRef(GCCRegNames); 2509 } 2510 2511 bool AMDGPUTargetInfo::initFeatureMap( 2512 llvm::StringMap<bool> &Features, 2513 DiagnosticsEngine &Diags, StringRef CPU, 2514 const std::vector<std::string> &FeatureVec) const { 2515 2516 // XXX - What does the member GPU mean if device name string passed here? 2517 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2518 if (CPU.empty()) 2519 CPU = "tahiti"; 2520 2521 switch (parseAMDGCNName(CPU)) { 2522 case GK_GFX6: 2523 case GK_GFX7: 2524 break; 2525 2526 case GK_GFX9: 2527 Features["gfx9-insts"] = true; 2528 LLVM_FALLTHROUGH; 2529 case GK_GFX8: 2530 Features["s-memrealtime"] = true; 2531 Features["16-bit-insts"] = true; 2532 Features["dpp"] = true; 2533 break; 2534 2535 case GK_NONE: 2536 return false; 2537 default: 2538 llvm_unreachable("unhandled subtarget"); 2539 } 2540 } else { 2541 if (CPU.empty()) 2542 CPU = "r600"; 2543 2544 switch (parseR600Name(CPU)) { 2545 case GK_R600: 2546 case GK_R700: 2547 case GK_EVERGREEN: 2548 case GK_NORTHERN_ISLANDS: 2549 break; 2550 case GK_R600_DOUBLE_OPS: 2551 case GK_R700_DOUBLE_OPS: 2552 case GK_EVERGREEN_DOUBLE_OPS: 2553 case GK_CAYMAN: 2554 Features["fp64"] = true; 2555 break; 2556 case GK_NONE: 2557 return false; 2558 default: 2559 llvm_unreachable("unhandled subtarget"); 2560 } 2561 } 2562 2563 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2564 } 2565 2566 const Builtin::Info BuiltinInfoX86[] = { 2567 #define BUILTIN(ID, TYPE, ATTRS) \ 2568 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2569 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2570 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2571 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2572 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2573 #include "clang/Basic/BuiltinsX86.def" 2574 2575 #define BUILTIN(ID, TYPE, ATTRS) \ 2576 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2577 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2578 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2579 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2580 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2581 #include "clang/Basic/BuiltinsX86_64.def" 2582 }; 2583 2584 2585 static const char* const GCCRegNames[] = { 2586 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2587 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2588 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2589 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2590 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2591 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2592 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2593 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2594 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2595 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2596 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2597 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2598 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2599 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2600 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2601 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2602 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2603 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", 2604 }; 2605 2606 const TargetInfo::AddlRegName AddlRegNames[] = { 2607 { { "al", "ah", "eax", "rax" }, 0 }, 2608 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2609 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2610 { { "dl", "dh", "edx", "rdx" }, 1 }, 2611 { { "esi", "rsi" }, 4 }, 2612 { { "edi", "rdi" }, 5 }, 2613 { { "esp", "rsp" }, 7 }, 2614 { { "ebp", "rbp" }, 6 }, 2615 { { "r8d", "r8w", "r8b" }, 38 }, 2616 { { "r9d", "r9w", "r9b" }, 39 }, 2617 { { "r10d", "r10w", "r10b" }, 40 }, 2618 { { "r11d", "r11w", "r11b" }, 41 }, 2619 { { "r12d", "r12w", "r12b" }, 42 }, 2620 { { "r13d", "r13w", "r13b" }, 43 }, 2621 { { "r14d", "r14w", "r14b" }, 44 }, 2622 { { "r15d", "r15w", "r15b" }, 45 }, 2623 }; 2624 2625 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2626 // most of the implementation can be shared. 2627 class X86TargetInfo : public TargetInfo { 2628 enum X86SSEEnum { 2629 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2630 } SSELevel = NoSSE; 2631 enum MMX3DNowEnum { 2632 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2633 } MMX3DNowLevel = NoMMX3DNow; 2634 enum XOPEnum { 2635 NoXOP, 2636 SSE4A, 2637 FMA4, 2638 XOP 2639 } XOPLevel = NoXOP; 2640 2641 bool HasAES = false; 2642 bool HasPCLMUL = false; 2643 bool HasLZCNT = false; 2644 bool HasRDRND = false; 2645 bool HasFSGSBASE = false; 2646 bool HasBMI = false; 2647 bool HasBMI2 = false; 2648 bool HasPOPCNT = false; 2649 bool HasRTM = false; 2650 bool HasPRFCHW = false; 2651 bool HasRDSEED = false; 2652 bool HasADX = false; 2653 bool HasTBM = false; 2654 bool HasLWP = false; 2655 bool HasFMA = false; 2656 bool HasF16C = false; 2657 bool HasAVX512CD = false; 2658 bool HasAVX512VPOPCNTDQ = false; 2659 bool HasAVX512ER = false; 2660 bool HasAVX512PF = false; 2661 bool HasAVX512DQ = false; 2662 bool HasAVX512BW = false; 2663 bool HasAVX512VL = false; 2664 bool HasAVX512VBMI = false; 2665 bool HasAVX512IFMA = false; 2666 bool HasSHA = false; 2667 bool HasMPX = false; 2668 bool HasSGX = false; 2669 bool HasCX16 = false; 2670 bool HasFXSR = false; 2671 bool HasXSAVE = false; 2672 bool HasXSAVEOPT = false; 2673 bool HasXSAVEC = false; 2674 bool HasXSAVES = false; 2675 bool HasMWAITX = false; 2676 bool HasCLZERO = false; 2677 bool HasPKU = false; 2678 bool HasCLFLUSHOPT = false; 2679 bool HasCLWB = false; 2680 bool HasMOVBE = false; 2681 bool HasPREFETCHWT1 = false; 2682 2683 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2684 /// 2685 /// Each enumeration represents a particular CPU supported by Clang. These 2686 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2687 enum CPUKind { 2688 CK_Generic, 2689 2690 /// \name i386 2691 /// i386-generation processors. 2692 //@{ 2693 CK_i386, 2694 //@} 2695 2696 /// \name i486 2697 /// i486-generation processors. 2698 //@{ 2699 CK_i486, 2700 CK_WinChipC6, 2701 CK_WinChip2, 2702 CK_C3, 2703 //@} 2704 2705 /// \name i586 2706 /// i586-generation processors, P5 microarchitecture based. 2707 //@{ 2708 CK_i586, 2709 CK_Pentium, 2710 CK_PentiumMMX, 2711 //@} 2712 2713 /// \name i686 2714 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2715 //@{ 2716 CK_i686, 2717 CK_PentiumPro, 2718 CK_Pentium2, 2719 CK_Pentium3, 2720 CK_Pentium3M, 2721 CK_PentiumM, 2722 CK_C3_2, 2723 2724 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2725 /// Clang however has some logic to support this. 2726 // FIXME: Warn, deprecate, and potentially remove this. 2727 CK_Yonah, 2728 //@} 2729 2730 /// \name Netburst 2731 /// Netburst microarchitecture based processors. 2732 //@{ 2733 CK_Pentium4, 2734 CK_Pentium4M, 2735 CK_Prescott, 2736 CK_Nocona, 2737 //@} 2738 2739 /// \name Core 2740 /// Core microarchitecture based processors. 2741 //@{ 2742 CK_Core2, 2743 2744 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2745 /// codename which GCC no longer accepts as an option to -march, but Clang 2746 /// has some logic for recognizing it. 2747 // FIXME: Warn, deprecate, and potentially remove this. 2748 CK_Penryn, 2749 //@} 2750 2751 /// \name Atom 2752 /// Atom processors 2753 //@{ 2754 CK_Bonnell, 2755 CK_Silvermont, 2756 CK_Goldmont, 2757 //@} 2758 2759 /// \name Nehalem 2760 /// Nehalem microarchitecture based processors. 2761 CK_Nehalem, 2762 2763 /// \name Westmere 2764 /// Westmere microarchitecture based processors. 2765 CK_Westmere, 2766 2767 /// \name Sandy Bridge 2768 /// Sandy Bridge microarchitecture based processors. 2769 CK_SandyBridge, 2770 2771 /// \name Ivy Bridge 2772 /// Ivy Bridge microarchitecture based processors. 2773 CK_IvyBridge, 2774 2775 /// \name Haswell 2776 /// Haswell microarchitecture based processors. 2777 CK_Haswell, 2778 2779 /// \name Broadwell 2780 /// Broadwell microarchitecture based processors. 2781 CK_Broadwell, 2782 2783 /// \name Skylake Client 2784 /// Skylake client microarchitecture based processors. 2785 CK_SkylakeClient, 2786 2787 /// \name Skylake Server 2788 /// Skylake server microarchitecture based processors. 2789 CK_SkylakeServer, 2790 2791 /// \name Cannonlake Client 2792 /// Cannonlake client microarchitecture based processors. 2793 CK_Cannonlake, 2794 2795 /// \name Knights Landing 2796 /// Knights Landing processor. 2797 CK_KNL, 2798 2799 /// \name Lakemont 2800 /// Lakemont microarchitecture based processors. 2801 CK_Lakemont, 2802 2803 /// \name K6 2804 /// K6 architecture processors. 2805 //@{ 2806 CK_K6, 2807 CK_K6_2, 2808 CK_K6_3, 2809 //@} 2810 2811 /// \name K7 2812 /// K7 architecture processors. 2813 //@{ 2814 CK_Athlon, 2815 CK_AthlonThunderbird, 2816 CK_Athlon4, 2817 CK_AthlonXP, 2818 CK_AthlonMP, 2819 //@} 2820 2821 /// \name K8 2822 /// K8 architecture processors. 2823 //@{ 2824 CK_Athlon64, 2825 CK_Athlon64SSE3, 2826 CK_AthlonFX, 2827 CK_K8, 2828 CK_K8SSE3, 2829 CK_Opteron, 2830 CK_OpteronSSE3, 2831 CK_AMDFAM10, 2832 //@} 2833 2834 /// \name Bobcat 2835 /// Bobcat architecture processors. 2836 //@{ 2837 CK_BTVER1, 2838 CK_BTVER2, 2839 //@} 2840 2841 /// \name Bulldozer 2842 /// Bulldozer architecture processors. 2843 //@{ 2844 CK_BDVER1, 2845 CK_BDVER2, 2846 CK_BDVER3, 2847 CK_BDVER4, 2848 //@} 2849 2850 /// \name zen 2851 /// Zen architecture processors. 2852 //@{ 2853 CK_ZNVER1, 2854 //@} 2855 2856 /// This specification is deprecated and will be removed in the future. 2857 /// Users should prefer \see CK_K8. 2858 // FIXME: Warn on this when the CPU is set to it. 2859 //@{ 2860 CK_x86_64, 2861 //@} 2862 2863 /// \name Geode 2864 /// Geode processors. 2865 //@{ 2866 CK_Geode 2867 //@} 2868 } CPU = CK_Generic; 2869 2870 CPUKind getCPUKind(StringRef CPU) const { 2871 return llvm::StringSwitch<CPUKind>(CPU) 2872 .Case("i386", CK_i386) 2873 .Case("i486", CK_i486) 2874 .Case("winchip-c6", CK_WinChipC6) 2875 .Case("winchip2", CK_WinChip2) 2876 .Case("c3", CK_C3) 2877 .Case("i586", CK_i586) 2878 .Case("pentium", CK_Pentium) 2879 .Case("pentium-mmx", CK_PentiumMMX) 2880 .Case("i686", CK_i686) 2881 .Case("pentiumpro", CK_PentiumPro) 2882 .Case("pentium2", CK_Pentium2) 2883 .Case("pentium3", CK_Pentium3) 2884 .Case("pentium3m", CK_Pentium3M) 2885 .Case("pentium-m", CK_PentiumM) 2886 .Case("c3-2", CK_C3_2) 2887 .Case("yonah", CK_Yonah) 2888 .Case("pentium4", CK_Pentium4) 2889 .Case("pentium4m", CK_Pentium4M) 2890 .Case("prescott", CK_Prescott) 2891 .Case("nocona", CK_Nocona) 2892 .Case("core2", CK_Core2) 2893 .Case("penryn", CK_Penryn) 2894 .Case("bonnell", CK_Bonnell) 2895 .Case("atom", CK_Bonnell) // Legacy name. 2896 .Case("silvermont", CK_Silvermont) 2897 .Case("slm", CK_Silvermont) // Legacy name. 2898 .Case("goldmont", CK_Goldmont) 2899 .Case("nehalem", CK_Nehalem) 2900 .Case("corei7", CK_Nehalem) // Legacy name. 2901 .Case("westmere", CK_Westmere) 2902 .Case("sandybridge", CK_SandyBridge) 2903 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2904 .Case("ivybridge", CK_IvyBridge) 2905 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2906 .Case("haswell", CK_Haswell) 2907 .Case("core-avx2", CK_Haswell) // Legacy name. 2908 .Case("broadwell", CK_Broadwell) 2909 .Case("skylake", CK_SkylakeClient) 2910 .Case("skylake-avx512", CK_SkylakeServer) 2911 .Case("skx", CK_SkylakeServer) // Legacy name. 2912 .Case("cannonlake", CK_Cannonlake) 2913 .Case("knl", CK_KNL) 2914 .Case("lakemont", CK_Lakemont) 2915 .Case("k6", CK_K6) 2916 .Case("k6-2", CK_K6_2) 2917 .Case("k6-3", CK_K6_3) 2918 .Case("athlon", CK_Athlon) 2919 .Case("athlon-tbird", CK_AthlonThunderbird) 2920 .Case("athlon-4", CK_Athlon4) 2921 .Case("athlon-xp", CK_AthlonXP) 2922 .Case("athlon-mp", CK_AthlonMP) 2923 .Case("athlon64", CK_Athlon64) 2924 .Case("athlon64-sse3", CK_Athlon64SSE3) 2925 .Case("athlon-fx", CK_AthlonFX) 2926 .Case("k8", CK_K8) 2927 .Case("k8-sse3", CK_K8SSE3) 2928 .Case("opteron", CK_Opteron) 2929 .Case("opteron-sse3", CK_OpteronSSE3) 2930 .Case("barcelona", CK_AMDFAM10) 2931 .Case("amdfam10", CK_AMDFAM10) 2932 .Case("btver1", CK_BTVER1) 2933 .Case("btver2", CK_BTVER2) 2934 .Case("bdver1", CK_BDVER1) 2935 .Case("bdver2", CK_BDVER2) 2936 .Case("bdver3", CK_BDVER3) 2937 .Case("bdver4", CK_BDVER4) 2938 .Case("znver1", CK_ZNVER1) 2939 .Case("x86-64", CK_x86_64) 2940 .Case("geode", CK_Geode) 2941 .Default(CK_Generic); 2942 } 2943 2944 enum FPMathKind { 2945 FP_Default, 2946 FP_SSE, 2947 FP_387 2948 } FPMath = FP_Default; 2949 2950 public: 2951 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2952 : TargetInfo(Triple) { 2953 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 2954 } 2955 unsigned getFloatEvalMethod() const override { 2956 // X87 evaluates with 80 bits "long double" precision. 2957 return SSELevel == NoSSE ? 2 : 0; 2958 } 2959 ArrayRef<const char *> getGCCRegNames() const override { 2960 return llvm::makeArrayRef(GCCRegNames); 2961 } 2962 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2963 return None; 2964 } 2965 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2966 return llvm::makeArrayRef(AddlRegNames); 2967 } 2968 bool validateCpuSupports(StringRef Name) const override; 2969 bool validateAsmConstraint(const char *&Name, 2970 TargetInfo::ConstraintInfo &info) const override; 2971 2972 bool validateGlobalRegisterVariable(StringRef RegName, 2973 unsigned RegSize, 2974 bool &HasSizeMismatch) const override { 2975 // esp and ebp are the only 32-bit registers the x86 backend can currently 2976 // handle. 2977 if (RegName.equals("esp") || RegName.equals("ebp")) { 2978 // Check that the register size is 32-bit. 2979 HasSizeMismatch = RegSize != 32; 2980 return true; 2981 } 2982 2983 return false; 2984 } 2985 2986 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2987 2988 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2989 2990 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2991 2992 std::string convertConstraint(const char *&Constraint) const override; 2993 const char *getClobbers() const override { 2994 return "~{dirflag},~{fpsr},~{flags}"; 2995 } 2996 2997 StringRef getConstraintRegister(const StringRef &Constraint, 2998 const StringRef &Expression) const override { 2999 StringRef::iterator I, E; 3000 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) { 3001 if (isalpha(*I)) 3002 break; 3003 } 3004 if (I == E) 3005 return ""; 3006 switch (*I) { 3007 // For the register constraints, return the matching register name 3008 case 'a': 3009 return "ax"; 3010 case 'b': 3011 return "bx"; 3012 case 'c': 3013 return "cx"; 3014 case 'd': 3015 return "dx"; 3016 case 'S': 3017 return "si"; 3018 case 'D': 3019 return "di"; 3020 // In case the constraint is 'r' we need to return Expression 3021 case 'r': 3022 return Expression; 3023 default: 3024 // Default value if there is no constraint for the register 3025 return ""; 3026 } 3027 return ""; 3028 } 3029 3030 void getTargetDefines(const LangOptions &Opts, 3031 MacroBuilder &Builder) const override; 3032 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 3033 bool Enabled); 3034 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 3035 bool Enabled); 3036 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3037 bool Enabled); 3038 void setFeatureEnabled(llvm::StringMap<bool> &Features, 3039 StringRef Name, bool Enabled) const override { 3040 setFeatureEnabledImpl(Features, Name, Enabled); 3041 } 3042 // This exists purely to cut down on the number of virtual calls in 3043 // initFeatureMap which calls this repeatedly. 3044 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3045 StringRef Name, bool Enabled); 3046 bool 3047 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 3048 StringRef CPU, 3049 const std::vector<std::string> &FeaturesVec) const override; 3050 bool hasFeature(StringRef Feature) const override; 3051 bool handleTargetFeatures(std::vector<std::string> &Features, 3052 DiagnosticsEngine &Diags) override; 3053 StringRef getABI() const override { 3054 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 3055 return "avx512"; 3056 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 3057 return "avx"; 3058 if (getTriple().getArch() == llvm::Triple::x86 && 3059 MMX3DNowLevel == NoMMX3DNow) 3060 return "no-mmx"; 3061 return ""; 3062 } 3063 bool setCPU(const std::string &Name) override { 3064 CPU = getCPUKind(Name); 3065 3066 // Perform any per-CPU checks necessary to determine if this CPU is 3067 // acceptable. 3068 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 3069 // invalid without explaining *why*. 3070 switch (CPU) { 3071 case CK_Generic: 3072 // No processor selected! 3073 return false; 3074 3075 case CK_i386: 3076 case CK_i486: 3077 case CK_WinChipC6: 3078 case CK_WinChip2: 3079 case CK_C3: 3080 case CK_i586: 3081 case CK_Pentium: 3082 case CK_PentiumMMX: 3083 case CK_i686: 3084 case CK_PentiumPro: 3085 case CK_Pentium2: 3086 case CK_Pentium3: 3087 case CK_Pentium3M: 3088 case CK_PentiumM: 3089 case CK_Yonah: 3090 case CK_C3_2: 3091 case CK_Pentium4: 3092 case CK_Pentium4M: 3093 case CK_Lakemont: 3094 case CK_Prescott: 3095 case CK_K6: 3096 case CK_K6_2: 3097 case CK_K6_3: 3098 case CK_Athlon: 3099 case CK_AthlonThunderbird: 3100 case CK_Athlon4: 3101 case CK_AthlonXP: 3102 case CK_AthlonMP: 3103 case CK_Geode: 3104 // Only accept certain architectures when compiling in 32-bit mode. 3105 if (getTriple().getArch() != llvm::Triple::x86) 3106 return false; 3107 3108 // Fallthrough 3109 case CK_Nocona: 3110 case CK_Core2: 3111 case CK_Penryn: 3112 case CK_Bonnell: 3113 case CK_Silvermont: 3114 case CK_Goldmont: 3115 case CK_Nehalem: 3116 case CK_Westmere: 3117 case CK_SandyBridge: 3118 case CK_IvyBridge: 3119 case CK_Haswell: 3120 case CK_Broadwell: 3121 case CK_SkylakeClient: 3122 case CK_SkylakeServer: 3123 case CK_Cannonlake: 3124 case CK_KNL: 3125 case CK_Athlon64: 3126 case CK_Athlon64SSE3: 3127 case CK_AthlonFX: 3128 case CK_K8: 3129 case CK_K8SSE3: 3130 case CK_Opteron: 3131 case CK_OpteronSSE3: 3132 case CK_AMDFAM10: 3133 case CK_BTVER1: 3134 case CK_BTVER2: 3135 case CK_BDVER1: 3136 case CK_BDVER2: 3137 case CK_BDVER3: 3138 case CK_BDVER4: 3139 case CK_ZNVER1: 3140 case CK_x86_64: 3141 return true; 3142 } 3143 llvm_unreachable("Unhandled CPU kind"); 3144 } 3145 3146 bool setFPMath(StringRef Name) override; 3147 3148 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3149 // Most of the non-ARM calling conventions are i386 conventions. 3150 switch (CC) { 3151 case CC_X86ThisCall: 3152 case CC_X86FastCall: 3153 case CC_X86StdCall: 3154 case CC_X86VectorCall: 3155 case CC_X86RegCall: 3156 case CC_C: 3157 case CC_Swift: 3158 case CC_X86Pascal: 3159 case CC_IntelOclBicc: 3160 case CC_OpenCLKernel: 3161 return CCCR_OK; 3162 default: 3163 return CCCR_Warning; 3164 } 3165 } 3166 3167 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3168 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 3169 } 3170 3171 bool hasSjLjLowering() const override { 3172 return true; 3173 } 3174 3175 void setSupportedOpenCLOpts() override { 3176 getSupportedOpenCLOpts().supportAll(); 3177 } 3178 }; 3179 3180 bool X86TargetInfo::setFPMath(StringRef Name) { 3181 if (Name == "387") { 3182 FPMath = FP_387; 3183 return true; 3184 } 3185 if (Name == "sse") { 3186 FPMath = FP_SSE; 3187 return true; 3188 } 3189 return false; 3190 } 3191 3192 bool X86TargetInfo::initFeatureMap( 3193 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 3194 const std::vector<std::string> &FeaturesVec) const { 3195 // FIXME: This *really* should not be here. 3196 // X86_64 always has SSE2. 3197 if (getTriple().getArch() == llvm::Triple::x86_64) 3198 setFeatureEnabledImpl(Features, "sse2", true); 3199 3200 const CPUKind Kind = getCPUKind(CPU); 3201 3202 // Enable X87 for all X86 processors but Lakemont. 3203 if (Kind != CK_Lakemont) 3204 setFeatureEnabledImpl(Features, "x87", true); 3205 3206 switch (Kind) { 3207 case CK_Generic: 3208 case CK_i386: 3209 case CK_i486: 3210 case CK_i586: 3211 case CK_Pentium: 3212 case CK_i686: 3213 case CK_PentiumPro: 3214 case CK_Lakemont: 3215 break; 3216 case CK_PentiumMMX: 3217 case CK_Pentium2: 3218 case CK_K6: 3219 case CK_WinChipC6: 3220 setFeatureEnabledImpl(Features, "mmx", true); 3221 break; 3222 case CK_Pentium3: 3223 case CK_Pentium3M: 3224 case CK_C3_2: 3225 setFeatureEnabledImpl(Features, "sse", true); 3226 setFeatureEnabledImpl(Features, "fxsr", true); 3227 break; 3228 case CK_PentiumM: 3229 case CK_Pentium4: 3230 case CK_Pentium4M: 3231 case CK_x86_64: 3232 setFeatureEnabledImpl(Features, "sse2", true); 3233 setFeatureEnabledImpl(Features, "fxsr", true); 3234 break; 3235 case CK_Yonah: 3236 case CK_Prescott: 3237 case CK_Nocona: 3238 setFeatureEnabledImpl(Features, "sse3", true); 3239 setFeatureEnabledImpl(Features, "fxsr", true); 3240 setFeatureEnabledImpl(Features, "cx16", true); 3241 break; 3242 case CK_Core2: 3243 setFeatureEnabledImpl(Features, "ssse3", true); 3244 setFeatureEnabledImpl(Features, "fxsr", true); 3245 setFeatureEnabledImpl(Features, "cx16", true); 3246 break; 3247 case CK_Penryn: 3248 setFeatureEnabledImpl(Features, "sse4.1", true); 3249 setFeatureEnabledImpl(Features, "fxsr", true); 3250 setFeatureEnabledImpl(Features, "cx16", true); 3251 break; 3252 case CK_Cannonlake: 3253 setFeatureEnabledImpl(Features, "avx512ifma", true); 3254 setFeatureEnabledImpl(Features, "avx512vbmi", true); 3255 setFeatureEnabledImpl(Features, "sha", true); 3256 LLVM_FALLTHROUGH; 3257 case CK_SkylakeServer: 3258 setFeatureEnabledImpl(Features, "avx512f", true); 3259 setFeatureEnabledImpl(Features, "avx512cd", true); 3260 setFeatureEnabledImpl(Features, "avx512dq", true); 3261 setFeatureEnabledImpl(Features, "avx512bw", true); 3262 setFeatureEnabledImpl(Features, "avx512vl", true); 3263 setFeatureEnabledImpl(Features, "pku", true); 3264 setFeatureEnabledImpl(Features, "clwb", true); 3265 LLVM_FALLTHROUGH; 3266 case CK_SkylakeClient: 3267 setFeatureEnabledImpl(Features, "xsavec", true); 3268 setFeatureEnabledImpl(Features, "xsaves", true); 3269 setFeatureEnabledImpl(Features, "mpx", true); 3270 setFeatureEnabledImpl(Features, "sgx", true); 3271 setFeatureEnabledImpl(Features, "clflushopt", true); 3272 setFeatureEnabledImpl(Features, "rtm", true); 3273 LLVM_FALLTHROUGH; 3274 case CK_Broadwell: 3275 setFeatureEnabledImpl(Features, "rdseed", true); 3276 setFeatureEnabledImpl(Features, "adx", true); 3277 LLVM_FALLTHROUGH; 3278 case CK_Haswell: 3279 setFeatureEnabledImpl(Features, "avx2", true); 3280 setFeatureEnabledImpl(Features, "lzcnt", true); 3281 setFeatureEnabledImpl(Features, "bmi", true); 3282 setFeatureEnabledImpl(Features, "bmi2", true); 3283 setFeatureEnabledImpl(Features, "fma", true); 3284 setFeatureEnabledImpl(Features, "movbe", true); 3285 LLVM_FALLTHROUGH; 3286 case CK_IvyBridge: 3287 setFeatureEnabledImpl(Features, "rdrnd", true); 3288 setFeatureEnabledImpl(Features, "f16c", true); 3289 setFeatureEnabledImpl(Features, "fsgsbase", true); 3290 LLVM_FALLTHROUGH; 3291 case CK_SandyBridge: 3292 setFeatureEnabledImpl(Features, "avx", true); 3293 setFeatureEnabledImpl(Features, "xsave", true); 3294 setFeatureEnabledImpl(Features, "xsaveopt", true); 3295 LLVM_FALLTHROUGH; 3296 case CK_Westmere: 3297 setFeatureEnabledImpl(Features, "aes", true); 3298 setFeatureEnabledImpl(Features, "pclmul", true); 3299 LLVM_FALLTHROUGH; 3300 case CK_Nehalem: 3301 setFeatureEnabledImpl(Features, "sse4.2", true); 3302 setFeatureEnabledImpl(Features, "fxsr", true); 3303 setFeatureEnabledImpl(Features, "cx16", true); 3304 break; 3305 case CK_Goldmont: 3306 setFeatureEnabledImpl(Features, "sha", true); 3307 setFeatureEnabledImpl(Features, "rdrnd", true); 3308 setFeatureEnabledImpl(Features, "rdseed", true); 3309 setFeatureEnabledImpl(Features, "xsave", true); 3310 setFeatureEnabledImpl(Features, "xsaveopt", true); 3311 setFeatureEnabledImpl(Features, "xsavec", true); 3312 setFeatureEnabledImpl(Features, "xsaves", true); 3313 setFeatureEnabledImpl(Features, "clflushopt", true); 3314 setFeatureEnabledImpl(Features, "mpx", true); 3315 LLVM_FALLTHROUGH; 3316 case CK_Silvermont: 3317 setFeatureEnabledImpl(Features, "aes", true); 3318 setFeatureEnabledImpl(Features, "pclmul", true); 3319 setFeatureEnabledImpl(Features, "sse4.2", true); 3320 LLVM_FALLTHROUGH; 3321 case CK_Bonnell: 3322 setFeatureEnabledImpl(Features, "movbe", true); 3323 setFeatureEnabledImpl(Features, "ssse3", true); 3324 setFeatureEnabledImpl(Features, "fxsr", true); 3325 setFeatureEnabledImpl(Features, "cx16", true); 3326 break; 3327 case CK_KNL: 3328 setFeatureEnabledImpl(Features, "avx512f", true); 3329 setFeatureEnabledImpl(Features, "avx512cd", true); 3330 setFeatureEnabledImpl(Features, "avx512er", true); 3331 setFeatureEnabledImpl(Features, "avx512pf", true); 3332 setFeatureEnabledImpl(Features, "prefetchwt1", true); 3333 setFeatureEnabledImpl(Features, "fxsr", true); 3334 setFeatureEnabledImpl(Features, "rdseed", true); 3335 setFeatureEnabledImpl(Features, "adx", true); 3336 setFeatureEnabledImpl(Features, "lzcnt", true); 3337 setFeatureEnabledImpl(Features, "bmi", true); 3338 setFeatureEnabledImpl(Features, "bmi2", true); 3339 setFeatureEnabledImpl(Features, "rtm", true); 3340 setFeatureEnabledImpl(Features, "fma", true); 3341 setFeatureEnabledImpl(Features, "rdrnd", true); 3342 setFeatureEnabledImpl(Features, "f16c", true); 3343 setFeatureEnabledImpl(Features, "fsgsbase", true); 3344 setFeatureEnabledImpl(Features, "aes", true); 3345 setFeatureEnabledImpl(Features, "pclmul", true); 3346 setFeatureEnabledImpl(Features, "cx16", true); 3347 setFeatureEnabledImpl(Features, "xsaveopt", true); 3348 setFeatureEnabledImpl(Features, "xsave", true); 3349 setFeatureEnabledImpl(Features, "movbe", true); 3350 break; 3351 case CK_K6_2: 3352 case CK_K6_3: 3353 case CK_WinChip2: 3354 case CK_C3: 3355 setFeatureEnabledImpl(Features, "3dnow", true); 3356 break; 3357 case CK_Athlon: 3358 case CK_AthlonThunderbird: 3359 case CK_Geode: 3360 setFeatureEnabledImpl(Features, "3dnowa", true); 3361 break; 3362 case CK_Athlon4: 3363 case CK_AthlonXP: 3364 case CK_AthlonMP: 3365 setFeatureEnabledImpl(Features, "sse", true); 3366 setFeatureEnabledImpl(Features, "3dnowa", true); 3367 setFeatureEnabledImpl(Features, "fxsr", true); 3368 break; 3369 case CK_K8: 3370 case CK_Opteron: 3371 case CK_Athlon64: 3372 case CK_AthlonFX: 3373 setFeatureEnabledImpl(Features, "sse2", true); 3374 setFeatureEnabledImpl(Features, "3dnowa", true); 3375 setFeatureEnabledImpl(Features, "fxsr", true); 3376 break; 3377 case CK_AMDFAM10: 3378 setFeatureEnabledImpl(Features, "sse4a", true); 3379 setFeatureEnabledImpl(Features, "lzcnt", true); 3380 setFeatureEnabledImpl(Features, "popcnt", true); 3381 LLVM_FALLTHROUGH; 3382 case CK_K8SSE3: 3383 case CK_OpteronSSE3: 3384 case CK_Athlon64SSE3: 3385 setFeatureEnabledImpl(Features, "sse3", true); 3386 setFeatureEnabledImpl(Features, "3dnowa", true); 3387 setFeatureEnabledImpl(Features, "fxsr", true); 3388 break; 3389 case CK_BTVER2: 3390 setFeatureEnabledImpl(Features, "avx", true); 3391 setFeatureEnabledImpl(Features, "aes", true); 3392 setFeatureEnabledImpl(Features, "pclmul", true); 3393 setFeatureEnabledImpl(Features, "bmi", true); 3394 setFeatureEnabledImpl(Features, "f16c", true); 3395 setFeatureEnabledImpl(Features, "xsaveopt", true); 3396 LLVM_FALLTHROUGH; 3397 case CK_BTVER1: 3398 setFeatureEnabledImpl(Features, "ssse3", true); 3399 setFeatureEnabledImpl(Features, "sse4a", true); 3400 setFeatureEnabledImpl(Features, "lzcnt", true); 3401 setFeatureEnabledImpl(Features, "popcnt", true); 3402 setFeatureEnabledImpl(Features, "prfchw", true); 3403 setFeatureEnabledImpl(Features, "cx16", true); 3404 setFeatureEnabledImpl(Features, "fxsr", true); 3405 break; 3406 case CK_ZNVER1: 3407 setFeatureEnabledImpl(Features, "adx", true); 3408 setFeatureEnabledImpl(Features, "aes", true); 3409 setFeatureEnabledImpl(Features, "avx2", true); 3410 setFeatureEnabledImpl(Features, "bmi", true); 3411 setFeatureEnabledImpl(Features, "bmi2", true); 3412 setFeatureEnabledImpl(Features, "clflushopt", true); 3413 setFeatureEnabledImpl(Features, "clzero", true); 3414 setFeatureEnabledImpl(Features, "cx16", true); 3415 setFeatureEnabledImpl(Features, "f16c", true); 3416 setFeatureEnabledImpl(Features, "fma", true); 3417 setFeatureEnabledImpl(Features, "fsgsbase", true); 3418 setFeatureEnabledImpl(Features, "fxsr", true); 3419 setFeatureEnabledImpl(Features, "lzcnt", true); 3420 setFeatureEnabledImpl(Features, "mwaitx", true); 3421 setFeatureEnabledImpl(Features, "movbe", true); 3422 setFeatureEnabledImpl(Features, "pclmul", true); 3423 setFeatureEnabledImpl(Features, "popcnt", true); 3424 setFeatureEnabledImpl(Features, "prfchw", true); 3425 setFeatureEnabledImpl(Features, "rdrnd", true); 3426 setFeatureEnabledImpl(Features, "rdseed", true); 3427 setFeatureEnabledImpl(Features, "sha", true); 3428 setFeatureEnabledImpl(Features, "sse4a", true); 3429 setFeatureEnabledImpl(Features, "xsave", true); 3430 setFeatureEnabledImpl(Features, "xsavec", true); 3431 setFeatureEnabledImpl(Features, "xsaveopt", true); 3432 setFeatureEnabledImpl(Features, "xsaves", true); 3433 break; 3434 case CK_BDVER4: 3435 setFeatureEnabledImpl(Features, "avx2", true); 3436 setFeatureEnabledImpl(Features, "bmi2", true); 3437 setFeatureEnabledImpl(Features, "mwaitx", true); 3438 LLVM_FALLTHROUGH; 3439 case CK_BDVER3: 3440 setFeatureEnabledImpl(Features, "fsgsbase", true); 3441 setFeatureEnabledImpl(Features, "xsaveopt", true); 3442 LLVM_FALLTHROUGH; 3443 case CK_BDVER2: 3444 setFeatureEnabledImpl(Features, "bmi", true); 3445 setFeatureEnabledImpl(Features, "fma", true); 3446 setFeatureEnabledImpl(Features, "f16c", true); 3447 setFeatureEnabledImpl(Features, "tbm", true); 3448 LLVM_FALLTHROUGH; 3449 case CK_BDVER1: 3450 // xop implies avx, sse4a and fma4. 3451 setFeatureEnabledImpl(Features, "xop", true); 3452 setFeatureEnabledImpl(Features, "lwp", true); 3453 setFeatureEnabledImpl(Features, "lzcnt", true); 3454 setFeatureEnabledImpl(Features, "aes", true); 3455 setFeatureEnabledImpl(Features, "pclmul", true); 3456 setFeatureEnabledImpl(Features, "prfchw", true); 3457 setFeatureEnabledImpl(Features, "cx16", true); 3458 setFeatureEnabledImpl(Features, "fxsr", true); 3459 setFeatureEnabledImpl(Features, "xsave", true); 3460 break; 3461 } 3462 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3463 return false; 3464 3465 // Can't do this earlier because we need to be able to explicitly enable 3466 // or disable these features and the things that they depend upon. 3467 3468 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3469 auto I = Features.find("sse4.2"); 3470 if (I != Features.end() && I->getValue() && 3471 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3472 FeaturesVec.end()) 3473 Features["popcnt"] = true; 3474 3475 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3476 I = Features.find("3dnow"); 3477 if (I != Features.end() && I->getValue() && 3478 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3479 FeaturesVec.end()) 3480 Features["prfchw"] = true; 3481 3482 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3483 // then enable MMX. 3484 I = Features.find("sse"); 3485 if (I != Features.end() && I->getValue() && 3486 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3487 FeaturesVec.end()) 3488 Features["mmx"] = true; 3489 3490 return true; 3491 } 3492 3493 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3494 X86SSEEnum Level, bool Enabled) { 3495 if (Enabled) { 3496 switch (Level) { 3497 case AVX512F: 3498 Features["avx512f"] = true; 3499 LLVM_FALLTHROUGH; 3500 case AVX2: 3501 Features["avx2"] = true; 3502 LLVM_FALLTHROUGH; 3503 case AVX: 3504 Features["avx"] = true; 3505 Features["xsave"] = true; 3506 LLVM_FALLTHROUGH; 3507 case SSE42: 3508 Features["sse4.2"] = true; 3509 LLVM_FALLTHROUGH; 3510 case SSE41: 3511 Features["sse4.1"] = true; 3512 LLVM_FALLTHROUGH; 3513 case SSSE3: 3514 Features["ssse3"] = true; 3515 LLVM_FALLTHROUGH; 3516 case SSE3: 3517 Features["sse3"] = true; 3518 LLVM_FALLTHROUGH; 3519 case SSE2: 3520 Features["sse2"] = true; 3521 LLVM_FALLTHROUGH; 3522 case SSE1: 3523 Features["sse"] = true; 3524 LLVM_FALLTHROUGH; 3525 case NoSSE: 3526 break; 3527 } 3528 return; 3529 } 3530 3531 switch (Level) { 3532 case NoSSE: 3533 case SSE1: 3534 Features["sse"] = false; 3535 LLVM_FALLTHROUGH; 3536 case SSE2: 3537 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3538 Features["sha"] = false; 3539 LLVM_FALLTHROUGH; 3540 case SSE3: 3541 Features["sse3"] = false; 3542 setXOPLevel(Features, NoXOP, false); 3543 LLVM_FALLTHROUGH; 3544 case SSSE3: 3545 Features["ssse3"] = false; 3546 LLVM_FALLTHROUGH; 3547 case SSE41: 3548 Features["sse4.1"] = false; 3549 LLVM_FALLTHROUGH; 3550 case SSE42: 3551 Features["sse4.2"] = false; 3552 LLVM_FALLTHROUGH; 3553 case AVX: 3554 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3555 Features["xsaveopt"] = false; 3556 setXOPLevel(Features, FMA4, false); 3557 LLVM_FALLTHROUGH; 3558 case AVX2: 3559 Features["avx2"] = false; 3560 LLVM_FALLTHROUGH; 3561 case AVX512F: 3562 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3563 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3564 Features["avx512vl"] = Features["avx512vbmi"] = 3565 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false; 3566 break; 3567 } 3568 } 3569 3570 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3571 MMX3DNowEnum Level, bool Enabled) { 3572 if (Enabled) { 3573 switch (Level) { 3574 case AMD3DNowAthlon: 3575 Features["3dnowa"] = true; 3576 LLVM_FALLTHROUGH; 3577 case AMD3DNow: 3578 Features["3dnow"] = true; 3579 LLVM_FALLTHROUGH; 3580 case MMX: 3581 Features["mmx"] = true; 3582 LLVM_FALLTHROUGH; 3583 case NoMMX3DNow: 3584 break; 3585 } 3586 return; 3587 } 3588 3589 switch (Level) { 3590 case NoMMX3DNow: 3591 case MMX: 3592 Features["mmx"] = false; 3593 LLVM_FALLTHROUGH; 3594 case AMD3DNow: 3595 Features["3dnow"] = false; 3596 LLVM_FALLTHROUGH; 3597 case AMD3DNowAthlon: 3598 Features["3dnowa"] = false; 3599 break; 3600 } 3601 } 3602 3603 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3604 bool Enabled) { 3605 if (Enabled) { 3606 switch (Level) { 3607 case XOP: 3608 Features["xop"] = true; 3609 LLVM_FALLTHROUGH; 3610 case FMA4: 3611 Features["fma4"] = true; 3612 setSSELevel(Features, AVX, true); 3613 LLVM_FALLTHROUGH; 3614 case SSE4A: 3615 Features["sse4a"] = true; 3616 setSSELevel(Features, SSE3, true); 3617 LLVM_FALLTHROUGH; 3618 case NoXOP: 3619 break; 3620 } 3621 return; 3622 } 3623 3624 switch (Level) { 3625 case NoXOP: 3626 case SSE4A: 3627 Features["sse4a"] = false; 3628 LLVM_FALLTHROUGH; 3629 case FMA4: 3630 Features["fma4"] = false; 3631 LLVM_FALLTHROUGH; 3632 case XOP: 3633 Features["xop"] = false; 3634 break; 3635 } 3636 } 3637 3638 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3639 StringRef Name, bool Enabled) { 3640 // This is a bit of a hack to deal with the sse4 target feature when used 3641 // as part of the target attribute. We handle sse4 correctly everywhere 3642 // else. See below for more information on how we handle the sse4 options. 3643 if (Name != "sse4") 3644 Features[Name] = Enabled; 3645 3646 if (Name == "mmx") { 3647 setMMXLevel(Features, MMX, Enabled); 3648 } else if (Name == "sse") { 3649 setSSELevel(Features, SSE1, Enabled); 3650 } else if (Name == "sse2") { 3651 setSSELevel(Features, SSE2, Enabled); 3652 } else if (Name == "sse3") { 3653 setSSELevel(Features, SSE3, Enabled); 3654 } else if (Name == "ssse3") { 3655 setSSELevel(Features, SSSE3, Enabled); 3656 } else if (Name == "sse4.2") { 3657 setSSELevel(Features, SSE42, Enabled); 3658 } else if (Name == "sse4.1") { 3659 setSSELevel(Features, SSE41, Enabled); 3660 } else if (Name == "3dnow") { 3661 setMMXLevel(Features, AMD3DNow, Enabled); 3662 } else if (Name == "3dnowa") { 3663 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3664 } else if (Name == "aes") { 3665 if (Enabled) 3666 setSSELevel(Features, SSE2, Enabled); 3667 } else if (Name == "pclmul") { 3668 if (Enabled) 3669 setSSELevel(Features, SSE2, Enabled); 3670 } else if (Name == "avx") { 3671 setSSELevel(Features, AVX, Enabled); 3672 } else if (Name == "avx2") { 3673 setSSELevel(Features, AVX2, Enabled); 3674 } else if (Name == "avx512f") { 3675 setSSELevel(Features, AVX512F, Enabled); 3676 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3677 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3678 Name == "avx512vbmi" || Name == "avx512ifma" || 3679 Name == "avx512vpopcntdq") { 3680 if (Enabled) 3681 setSSELevel(Features, AVX512F, Enabled); 3682 // Enable BWI instruction if VBMI is being enabled. 3683 if (Name == "avx512vbmi" && Enabled) 3684 Features["avx512bw"] = true; 3685 // Also disable VBMI if BWI is being disabled. 3686 if (Name == "avx512bw" && !Enabled) 3687 Features["avx512vbmi"] = false; 3688 } else if (Name == "fma") { 3689 if (Enabled) 3690 setSSELevel(Features, AVX, Enabled); 3691 } else if (Name == "fma4") { 3692 setXOPLevel(Features, FMA4, Enabled); 3693 } else if (Name == "xop") { 3694 setXOPLevel(Features, XOP, Enabled); 3695 } else if (Name == "sse4a") { 3696 setXOPLevel(Features, SSE4A, Enabled); 3697 } else if (Name == "f16c") { 3698 if (Enabled) 3699 setSSELevel(Features, AVX, Enabled); 3700 } else if (Name == "sha") { 3701 if (Enabled) 3702 setSSELevel(Features, SSE2, Enabled); 3703 } else if (Name == "sse4") { 3704 // We can get here via the __target__ attribute since that's not controlled 3705 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3706 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3707 // disabled. 3708 if (Enabled) 3709 setSSELevel(Features, SSE42, Enabled); 3710 else 3711 setSSELevel(Features, SSE41, Enabled); 3712 } else if (Name == "xsave") { 3713 if (!Enabled) 3714 Features["xsaveopt"] = false; 3715 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3716 if (Enabled) 3717 Features["xsave"] = true; 3718 } 3719 } 3720 3721 /// handleTargetFeatures - Perform initialization based on the user 3722 /// configured set of features. 3723 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3724 DiagnosticsEngine &Diags) { 3725 for (const auto &Feature : Features) { 3726 if (Feature[0] != '+') 3727 continue; 3728 3729 if (Feature == "+aes") { 3730 HasAES = true; 3731 } else if (Feature == "+pclmul") { 3732 HasPCLMUL = true; 3733 } else if (Feature == "+lzcnt") { 3734 HasLZCNT = true; 3735 } else if (Feature == "+rdrnd") { 3736 HasRDRND = true; 3737 } else if (Feature == "+fsgsbase") { 3738 HasFSGSBASE = true; 3739 } else if (Feature == "+bmi") { 3740 HasBMI = true; 3741 } else if (Feature == "+bmi2") { 3742 HasBMI2 = true; 3743 } else if (Feature == "+popcnt") { 3744 HasPOPCNT = true; 3745 } else if (Feature == "+rtm") { 3746 HasRTM = true; 3747 } else if (Feature == "+prfchw") { 3748 HasPRFCHW = true; 3749 } else if (Feature == "+rdseed") { 3750 HasRDSEED = true; 3751 } else if (Feature == "+adx") { 3752 HasADX = true; 3753 } else if (Feature == "+tbm") { 3754 HasTBM = true; 3755 } else if (Feature == "+lwp") { 3756 HasLWP = true; 3757 } else if (Feature == "+fma") { 3758 HasFMA = true; 3759 } else if (Feature == "+f16c") { 3760 HasF16C = true; 3761 } else if (Feature == "+avx512cd") { 3762 HasAVX512CD = true; 3763 } else if (Feature == "+avx512vpopcntdq") { 3764 HasAVX512VPOPCNTDQ = true; 3765 } else if (Feature == "+avx512er") { 3766 HasAVX512ER = true; 3767 } else if (Feature == "+avx512pf") { 3768 HasAVX512PF = true; 3769 } else if (Feature == "+avx512dq") { 3770 HasAVX512DQ = true; 3771 } else if (Feature == "+avx512bw") { 3772 HasAVX512BW = true; 3773 } else if (Feature == "+avx512vl") { 3774 HasAVX512VL = true; 3775 } else if (Feature == "+avx512vbmi") { 3776 HasAVX512VBMI = true; 3777 } else if (Feature == "+avx512ifma") { 3778 HasAVX512IFMA = true; 3779 } else if (Feature == "+sha") { 3780 HasSHA = true; 3781 } else if (Feature == "+mpx") { 3782 HasMPX = true; 3783 } else if (Feature == "+movbe") { 3784 HasMOVBE = true; 3785 } else if (Feature == "+sgx") { 3786 HasSGX = true; 3787 } else if (Feature == "+cx16") { 3788 HasCX16 = true; 3789 } else if (Feature == "+fxsr") { 3790 HasFXSR = true; 3791 } else if (Feature == "+xsave") { 3792 HasXSAVE = true; 3793 } else if (Feature == "+xsaveopt") { 3794 HasXSAVEOPT = true; 3795 } else if (Feature == "+xsavec") { 3796 HasXSAVEC = true; 3797 } else if (Feature == "+xsaves") { 3798 HasXSAVES = true; 3799 } else if (Feature == "+mwaitx") { 3800 HasMWAITX = true; 3801 } else if (Feature == "+pku") { 3802 HasPKU = true; 3803 } else if (Feature == "+clflushopt") { 3804 HasCLFLUSHOPT = true; 3805 } else if (Feature == "+clwb") { 3806 HasCLWB = true; 3807 } else if (Feature == "+prefetchwt1") { 3808 HasPREFETCHWT1 = true; 3809 } else if (Feature == "+clzero") { 3810 HasCLZERO = true; 3811 } 3812 3813 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3814 .Case("+avx512f", AVX512F) 3815 .Case("+avx2", AVX2) 3816 .Case("+avx", AVX) 3817 .Case("+sse4.2", SSE42) 3818 .Case("+sse4.1", SSE41) 3819 .Case("+ssse3", SSSE3) 3820 .Case("+sse3", SSE3) 3821 .Case("+sse2", SSE2) 3822 .Case("+sse", SSE1) 3823 .Default(NoSSE); 3824 SSELevel = std::max(SSELevel, Level); 3825 3826 MMX3DNowEnum ThreeDNowLevel = 3827 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3828 .Case("+3dnowa", AMD3DNowAthlon) 3829 .Case("+3dnow", AMD3DNow) 3830 .Case("+mmx", MMX) 3831 .Default(NoMMX3DNow); 3832 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3833 3834 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3835 .Case("+xop", XOP) 3836 .Case("+fma4", FMA4) 3837 .Case("+sse4a", SSE4A) 3838 .Default(NoXOP); 3839 XOPLevel = std::max(XOPLevel, XLevel); 3840 } 3841 3842 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3843 // matches the selected sse level. 3844 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3845 (FPMath == FP_387 && SSELevel >= SSE1)) { 3846 Diags.Report(diag::err_target_unsupported_fpmath) << 3847 (FPMath == FP_SSE ? "sse" : "387"); 3848 return false; 3849 } 3850 3851 SimdDefaultAlign = 3852 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3853 return true; 3854 } 3855 3856 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3857 /// definitions for this particular subtarget. 3858 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3859 MacroBuilder &Builder) const { 3860 // Target identification. 3861 if (getTriple().getArch() == llvm::Triple::x86_64) { 3862 Builder.defineMacro("__amd64__"); 3863 Builder.defineMacro("__amd64"); 3864 Builder.defineMacro("__x86_64"); 3865 Builder.defineMacro("__x86_64__"); 3866 if (getTriple().getArchName() == "x86_64h") { 3867 Builder.defineMacro("__x86_64h"); 3868 Builder.defineMacro("__x86_64h__"); 3869 } 3870 } else { 3871 DefineStd(Builder, "i386", Opts); 3872 } 3873 3874 // Subtarget options. 3875 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3876 // truly should be based on -mtune options. 3877 switch (CPU) { 3878 case CK_Generic: 3879 break; 3880 case CK_i386: 3881 // The rest are coming from the i386 define above. 3882 Builder.defineMacro("__tune_i386__"); 3883 break; 3884 case CK_i486: 3885 case CK_WinChipC6: 3886 case CK_WinChip2: 3887 case CK_C3: 3888 defineCPUMacros(Builder, "i486"); 3889 break; 3890 case CK_PentiumMMX: 3891 Builder.defineMacro("__pentium_mmx__"); 3892 Builder.defineMacro("__tune_pentium_mmx__"); 3893 LLVM_FALLTHROUGH; 3894 case CK_i586: 3895 case CK_Pentium: 3896 defineCPUMacros(Builder, "i586"); 3897 defineCPUMacros(Builder, "pentium"); 3898 break; 3899 case CK_Pentium3: 3900 case CK_Pentium3M: 3901 case CK_PentiumM: 3902 Builder.defineMacro("__tune_pentium3__"); 3903 LLVM_FALLTHROUGH; 3904 case CK_Pentium2: 3905 case CK_C3_2: 3906 Builder.defineMacro("__tune_pentium2__"); 3907 LLVM_FALLTHROUGH; 3908 case CK_PentiumPro: 3909 Builder.defineMacro("__tune_i686__"); 3910 Builder.defineMacro("__tune_pentiumpro__"); 3911 LLVM_FALLTHROUGH; 3912 case CK_i686: 3913 Builder.defineMacro("__i686"); 3914 Builder.defineMacro("__i686__"); 3915 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3916 Builder.defineMacro("__pentiumpro"); 3917 Builder.defineMacro("__pentiumpro__"); 3918 break; 3919 case CK_Pentium4: 3920 case CK_Pentium4M: 3921 defineCPUMacros(Builder, "pentium4"); 3922 break; 3923 case CK_Yonah: 3924 case CK_Prescott: 3925 case CK_Nocona: 3926 defineCPUMacros(Builder, "nocona"); 3927 break; 3928 case CK_Core2: 3929 case CK_Penryn: 3930 defineCPUMacros(Builder, "core2"); 3931 break; 3932 case CK_Bonnell: 3933 defineCPUMacros(Builder, "atom"); 3934 break; 3935 case CK_Silvermont: 3936 defineCPUMacros(Builder, "slm"); 3937 break; 3938 case CK_Goldmont: 3939 defineCPUMacros(Builder, "goldmont"); 3940 break; 3941 case CK_Nehalem: 3942 case CK_Westmere: 3943 case CK_SandyBridge: 3944 case CK_IvyBridge: 3945 case CK_Haswell: 3946 case CK_Broadwell: 3947 case CK_SkylakeClient: 3948 // FIXME: Historically, we defined this legacy name, it would be nice to 3949 // remove it at some point. We've never exposed fine-grained names for 3950 // recent primary x86 CPUs, and we should keep it that way. 3951 defineCPUMacros(Builder, "corei7"); 3952 break; 3953 case CK_SkylakeServer: 3954 defineCPUMacros(Builder, "skx"); 3955 break; 3956 case CK_Cannonlake: 3957 break; 3958 case CK_KNL: 3959 defineCPUMacros(Builder, "knl"); 3960 break; 3961 case CK_Lakemont: 3962 Builder.defineMacro("__tune_lakemont__"); 3963 break; 3964 case CK_K6_2: 3965 Builder.defineMacro("__k6_2__"); 3966 Builder.defineMacro("__tune_k6_2__"); 3967 LLVM_FALLTHROUGH; 3968 case CK_K6_3: 3969 if (CPU != CK_K6_2) { // In case of fallthrough 3970 // FIXME: GCC may be enabling these in cases where some other k6 3971 // architecture is specified but -m3dnow is explicitly provided. The 3972 // exact semantics need to be determined and emulated here. 3973 Builder.defineMacro("__k6_3__"); 3974 Builder.defineMacro("__tune_k6_3__"); 3975 } 3976 LLVM_FALLTHROUGH; 3977 case CK_K6: 3978 defineCPUMacros(Builder, "k6"); 3979 break; 3980 case CK_Athlon: 3981 case CK_AthlonThunderbird: 3982 case CK_Athlon4: 3983 case CK_AthlonXP: 3984 case CK_AthlonMP: 3985 defineCPUMacros(Builder, "athlon"); 3986 if (SSELevel != NoSSE) { 3987 Builder.defineMacro("__athlon_sse__"); 3988 Builder.defineMacro("__tune_athlon_sse__"); 3989 } 3990 break; 3991 case CK_K8: 3992 case CK_K8SSE3: 3993 case CK_x86_64: 3994 case CK_Opteron: 3995 case CK_OpteronSSE3: 3996 case CK_Athlon64: 3997 case CK_Athlon64SSE3: 3998 case CK_AthlonFX: 3999 defineCPUMacros(Builder, "k8"); 4000 break; 4001 case CK_AMDFAM10: 4002 defineCPUMacros(Builder, "amdfam10"); 4003 break; 4004 case CK_BTVER1: 4005 defineCPUMacros(Builder, "btver1"); 4006 break; 4007 case CK_BTVER2: 4008 defineCPUMacros(Builder, "btver2"); 4009 break; 4010 case CK_BDVER1: 4011 defineCPUMacros(Builder, "bdver1"); 4012 break; 4013 case CK_BDVER2: 4014 defineCPUMacros(Builder, "bdver2"); 4015 break; 4016 case CK_BDVER3: 4017 defineCPUMacros(Builder, "bdver3"); 4018 break; 4019 case CK_BDVER4: 4020 defineCPUMacros(Builder, "bdver4"); 4021 break; 4022 case CK_ZNVER1: 4023 defineCPUMacros(Builder, "znver1"); 4024 break; 4025 case CK_Geode: 4026 defineCPUMacros(Builder, "geode"); 4027 break; 4028 } 4029 4030 // Target properties. 4031 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4032 4033 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 4034 // functions in glibc header files that use FP Stack inline asm which the 4035 // backend can't deal with (PR879). 4036 Builder.defineMacro("__NO_MATH_INLINES"); 4037 4038 if (HasAES) 4039 Builder.defineMacro("__AES__"); 4040 4041 if (HasPCLMUL) 4042 Builder.defineMacro("__PCLMUL__"); 4043 4044 if (HasLZCNT) 4045 Builder.defineMacro("__LZCNT__"); 4046 4047 if (HasRDRND) 4048 Builder.defineMacro("__RDRND__"); 4049 4050 if (HasFSGSBASE) 4051 Builder.defineMacro("__FSGSBASE__"); 4052 4053 if (HasBMI) 4054 Builder.defineMacro("__BMI__"); 4055 4056 if (HasBMI2) 4057 Builder.defineMacro("__BMI2__"); 4058 4059 if (HasPOPCNT) 4060 Builder.defineMacro("__POPCNT__"); 4061 4062 if (HasRTM) 4063 Builder.defineMacro("__RTM__"); 4064 4065 if (HasPRFCHW) 4066 Builder.defineMacro("__PRFCHW__"); 4067 4068 if (HasRDSEED) 4069 Builder.defineMacro("__RDSEED__"); 4070 4071 if (HasADX) 4072 Builder.defineMacro("__ADX__"); 4073 4074 if (HasTBM) 4075 Builder.defineMacro("__TBM__"); 4076 4077 if (HasLWP) 4078 Builder.defineMacro("__LWP__"); 4079 4080 if (HasMWAITX) 4081 Builder.defineMacro("__MWAITX__"); 4082 4083 switch (XOPLevel) { 4084 case XOP: 4085 Builder.defineMacro("__XOP__"); 4086 LLVM_FALLTHROUGH; 4087 case FMA4: 4088 Builder.defineMacro("__FMA4__"); 4089 LLVM_FALLTHROUGH; 4090 case SSE4A: 4091 Builder.defineMacro("__SSE4A__"); 4092 LLVM_FALLTHROUGH; 4093 case NoXOP: 4094 break; 4095 } 4096 4097 if (HasFMA) 4098 Builder.defineMacro("__FMA__"); 4099 4100 if (HasF16C) 4101 Builder.defineMacro("__F16C__"); 4102 4103 if (HasAVX512CD) 4104 Builder.defineMacro("__AVX512CD__"); 4105 if (HasAVX512VPOPCNTDQ) 4106 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 4107 if (HasAVX512ER) 4108 Builder.defineMacro("__AVX512ER__"); 4109 if (HasAVX512PF) 4110 Builder.defineMacro("__AVX512PF__"); 4111 if (HasAVX512DQ) 4112 Builder.defineMacro("__AVX512DQ__"); 4113 if (HasAVX512BW) 4114 Builder.defineMacro("__AVX512BW__"); 4115 if (HasAVX512VL) 4116 Builder.defineMacro("__AVX512VL__"); 4117 if (HasAVX512VBMI) 4118 Builder.defineMacro("__AVX512VBMI__"); 4119 if (HasAVX512IFMA) 4120 Builder.defineMacro("__AVX512IFMA__"); 4121 4122 if (HasSHA) 4123 Builder.defineMacro("__SHA__"); 4124 4125 if (HasFXSR) 4126 Builder.defineMacro("__FXSR__"); 4127 if (HasXSAVE) 4128 Builder.defineMacro("__XSAVE__"); 4129 if (HasXSAVEOPT) 4130 Builder.defineMacro("__XSAVEOPT__"); 4131 if (HasXSAVEC) 4132 Builder.defineMacro("__XSAVEC__"); 4133 if (HasXSAVES) 4134 Builder.defineMacro("__XSAVES__"); 4135 if (HasPKU) 4136 Builder.defineMacro("__PKU__"); 4137 if (HasCX16) 4138 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 4139 if (HasCLFLUSHOPT) 4140 Builder.defineMacro("__CLFLUSHOPT__"); 4141 if (HasCLWB) 4142 Builder.defineMacro("__CLWB__"); 4143 if (HasMPX) 4144 Builder.defineMacro("__MPX__"); 4145 if (HasSGX) 4146 Builder.defineMacro("__SGX__"); 4147 if (HasPREFETCHWT1) 4148 Builder.defineMacro("__PREFETCHWT1__"); 4149 if (HasCLZERO) 4150 Builder.defineMacro("__CLZERO__"); 4151 4152 // Each case falls through to the previous one here. 4153 switch (SSELevel) { 4154 case AVX512F: 4155 Builder.defineMacro("__AVX512F__"); 4156 LLVM_FALLTHROUGH; 4157 case AVX2: 4158 Builder.defineMacro("__AVX2__"); 4159 LLVM_FALLTHROUGH; 4160 case AVX: 4161 Builder.defineMacro("__AVX__"); 4162 LLVM_FALLTHROUGH; 4163 case SSE42: 4164 Builder.defineMacro("__SSE4_2__"); 4165 LLVM_FALLTHROUGH; 4166 case SSE41: 4167 Builder.defineMacro("__SSE4_1__"); 4168 LLVM_FALLTHROUGH; 4169 case SSSE3: 4170 Builder.defineMacro("__SSSE3__"); 4171 LLVM_FALLTHROUGH; 4172 case SSE3: 4173 Builder.defineMacro("__SSE3__"); 4174 LLVM_FALLTHROUGH; 4175 case SSE2: 4176 Builder.defineMacro("__SSE2__"); 4177 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 4178 LLVM_FALLTHROUGH; 4179 case SSE1: 4180 Builder.defineMacro("__SSE__"); 4181 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 4182 LLVM_FALLTHROUGH; 4183 case NoSSE: 4184 break; 4185 } 4186 4187 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 4188 switch (SSELevel) { 4189 case AVX512F: 4190 case AVX2: 4191 case AVX: 4192 case SSE42: 4193 case SSE41: 4194 case SSSE3: 4195 case SSE3: 4196 case SSE2: 4197 Builder.defineMacro("_M_IX86_FP", Twine(2)); 4198 break; 4199 case SSE1: 4200 Builder.defineMacro("_M_IX86_FP", Twine(1)); 4201 break; 4202 default: 4203 Builder.defineMacro("_M_IX86_FP", Twine(0)); 4204 break; 4205 } 4206 } 4207 4208 // Each case falls through to the previous one here. 4209 switch (MMX3DNowLevel) { 4210 case AMD3DNowAthlon: 4211 Builder.defineMacro("__3dNOW_A__"); 4212 LLVM_FALLTHROUGH; 4213 case AMD3DNow: 4214 Builder.defineMacro("__3dNOW__"); 4215 LLVM_FALLTHROUGH; 4216 case MMX: 4217 Builder.defineMacro("__MMX__"); 4218 LLVM_FALLTHROUGH; 4219 case NoMMX3DNow: 4220 break; 4221 } 4222 4223 if (CPU >= CK_i486) { 4224 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4225 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4226 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4227 } 4228 if (CPU >= CK_i586) 4229 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4230 4231 if (HasFloat128) 4232 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 4233 } 4234 4235 bool X86TargetInfo::hasFeature(StringRef Feature) const { 4236 return llvm::StringSwitch<bool>(Feature) 4237 .Case("aes", HasAES) 4238 .Case("avx", SSELevel >= AVX) 4239 .Case("avx2", SSELevel >= AVX2) 4240 .Case("avx512f", SSELevel >= AVX512F) 4241 .Case("avx512cd", HasAVX512CD) 4242 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 4243 .Case("avx512er", HasAVX512ER) 4244 .Case("avx512pf", HasAVX512PF) 4245 .Case("avx512dq", HasAVX512DQ) 4246 .Case("avx512bw", HasAVX512BW) 4247 .Case("avx512vl", HasAVX512VL) 4248 .Case("avx512vbmi", HasAVX512VBMI) 4249 .Case("avx512ifma", HasAVX512IFMA) 4250 .Case("bmi", HasBMI) 4251 .Case("bmi2", HasBMI2) 4252 .Case("clflushopt", HasCLFLUSHOPT) 4253 .Case("clwb", HasCLWB) 4254 .Case("clzero", HasCLZERO) 4255 .Case("cx16", HasCX16) 4256 .Case("f16c", HasF16C) 4257 .Case("fma", HasFMA) 4258 .Case("fma4", XOPLevel >= FMA4) 4259 .Case("fsgsbase", HasFSGSBASE) 4260 .Case("fxsr", HasFXSR) 4261 .Case("lzcnt", HasLZCNT) 4262 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 4263 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 4264 .Case("mmx", MMX3DNowLevel >= MMX) 4265 .Case("movbe", HasMOVBE) 4266 .Case("mpx", HasMPX) 4267 .Case("pclmul", HasPCLMUL) 4268 .Case("pku", HasPKU) 4269 .Case("popcnt", HasPOPCNT) 4270 .Case("prefetchwt1", HasPREFETCHWT1) 4271 .Case("prfchw", HasPRFCHW) 4272 .Case("rdrnd", HasRDRND) 4273 .Case("rdseed", HasRDSEED) 4274 .Case("rtm", HasRTM) 4275 .Case("sgx", HasSGX) 4276 .Case("sha", HasSHA) 4277 .Case("sse", SSELevel >= SSE1) 4278 .Case("sse2", SSELevel >= SSE2) 4279 .Case("sse3", SSELevel >= SSE3) 4280 .Case("ssse3", SSELevel >= SSSE3) 4281 .Case("sse4.1", SSELevel >= SSE41) 4282 .Case("sse4.2", SSELevel >= SSE42) 4283 .Case("sse4a", XOPLevel >= SSE4A) 4284 .Case("tbm", HasTBM) 4285 .Case("lwp", HasLWP) 4286 .Case("x86", true) 4287 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 4288 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 4289 .Case("xop", XOPLevel >= XOP) 4290 .Case("xsave", HasXSAVE) 4291 .Case("xsavec", HasXSAVEC) 4292 .Case("xsaves", HasXSAVES) 4293 .Case("xsaveopt", HasXSAVEOPT) 4294 .Default(false); 4295 } 4296 4297 // We can't use a generic validation scheme for the features accepted here 4298 // versus subtarget features accepted in the target attribute because the 4299 // bitfield structure that's initialized in the runtime only supports the 4300 // below currently rather than the full range of subtarget features. (See 4301 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 4302 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 4303 return llvm::StringSwitch<bool>(FeatureStr) 4304 .Case("cmov", true) 4305 .Case("mmx", true) 4306 .Case("popcnt", true) 4307 .Case("sse", true) 4308 .Case("sse2", true) 4309 .Case("sse3", true) 4310 .Case("ssse3", true) 4311 .Case("sse4.1", true) 4312 .Case("sse4.2", true) 4313 .Case("avx", true) 4314 .Case("avx2", true) 4315 .Case("sse4a", true) 4316 .Case("fma4", true) 4317 .Case("xop", true) 4318 .Case("fma", true) 4319 .Case("avx512f", true) 4320 .Case("bmi", true) 4321 .Case("bmi2", true) 4322 .Case("aes", true) 4323 .Case("pclmul", true) 4324 .Case("avx512vl", true) 4325 .Case("avx512bw", true) 4326 .Case("avx512dq", true) 4327 .Case("avx512cd", true) 4328 .Case("avx512vpopcntdq", true) 4329 .Case("avx512er", true) 4330 .Case("avx512pf", true) 4331 .Case("avx512vbmi", true) 4332 .Case("avx512ifma", true) 4333 .Default(false); 4334 } 4335 4336 bool 4337 X86TargetInfo::validateAsmConstraint(const char *&Name, 4338 TargetInfo::ConstraintInfo &Info) const { 4339 switch (*Name) { 4340 default: return false; 4341 // Constant constraints. 4342 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 4343 // instructions. 4344 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 4345 // x86_64 instructions. 4346 case 's': 4347 Info.setRequiresImmediate(); 4348 return true; 4349 case 'I': 4350 Info.setRequiresImmediate(0, 31); 4351 return true; 4352 case 'J': 4353 Info.setRequiresImmediate(0, 63); 4354 return true; 4355 case 'K': 4356 Info.setRequiresImmediate(-128, 127); 4357 return true; 4358 case 'L': 4359 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 4360 return true; 4361 case 'M': 4362 Info.setRequiresImmediate(0, 3); 4363 return true; 4364 case 'N': 4365 Info.setRequiresImmediate(0, 255); 4366 return true; 4367 case 'O': 4368 Info.setRequiresImmediate(0, 127); 4369 return true; 4370 // Register constraints. 4371 case 'Y': // 'Y' is the first character for several 2-character constraints. 4372 // Shift the pointer to the second character of the constraint. 4373 Name++; 4374 switch (*Name) { 4375 default: 4376 return false; 4377 case '0': // First SSE register. 4378 case 't': // Any SSE register, when SSE2 is enabled. 4379 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 4380 case 'm': // Any MMX register, when inter-unit moves enabled. 4381 case 'k': // AVX512 arch mask registers: k1-k7. 4382 Info.setAllowsRegister(); 4383 return true; 4384 } 4385 case 'f': // Any x87 floating point stack register. 4386 // Constraint 'f' cannot be used for output operands. 4387 if (Info.ConstraintStr[0] == '=') 4388 return false; 4389 Info.setAllowsRegister(); 4390 return true; 4391 case 'a': // eax. 4392 case 'b': // ebx. 4393 case 'c': // ecx. 4394 case 'd': // edx. 4395 case 'S': // esi. 4396 case 'D': // edi. 4397 case 'A': // edx:eax. 4398 case 't': // Top of floating point stack. 4399 case 'u': // Second from top of floating point stack. 4400 case 'q': // Any register accessible as [r]l: a, b, c, and d. 4401 case 'y': // Any MMX register. 4402 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 4403 case 'x': // Any SSE register. 4404 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 4405 // for intermideate k reg operations). 4406 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 4407 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 4408 case 'l': // "Index" registers: any general register that can be used as an 4409 // index in a base+index memory access. 4410 Info.setAllowsRegister(); 4411 return true; 4412 // Floating point constant constraints. 4413 case 'C': // SSE floating point constant. 4414 case 'G': // x87 floating point constant. 4415 return true; 4416 } 4417 } 4418 4419 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 4420 unsigned Size) const { 4421 // Strip off constraint modifiers. 4422 while (Constraint[0] == '=' || 4423 Constraint[0] == '+' || 4424 Constraint[0] == '&') 4425 Constraint = Constraint.substr(1); 4426 4427 return validateOperandSize(Constraint, Size); 4428 } 4429 4430 bool X86TargetInfo::validateInputSize(StringRef Constraint, 4431 unsigned Size) const { 4432 return validateOperandSize(Constraint, Size); 4433 } 4434 4435 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 4436 unsigned Size) const { 4437 switch (Constraint[0]) { 4438 default: break; 4439 case 'k': 4440 // Registers k0-k7 (AVX512) size limit is 64 bit. 4441 case 'y': 4442 return Size <= 64; 4443 case 'f': 4444 case 't': 4445 case 'u': 4446 return Size <= 128; 4447 case 'v': 4448 case 'x': 4449 if (SSELevel >= AVX512F) 4450 // 512-bit zmm registers can be used if target supports AVX512F. 4451 return Size <= 512U; 4452 else if (SSELevel >= AVX) 4453 // 256-bit ymm registers can be used if target supports AVX. 4454 return Size <= 256U; 4455 return Size <= 128U; 4456 case 'Y': 4457 // 'Y' is the first character for several 2-character constraints. 4458 switch (Constraint[1]) { 4459 default: break; 4460 case 'm': 4461 // 'Ym' is synonymous with 'y'. 4462 case 'k': 4463 return Size <= 64; 4464 case 'i': 4465 case 't': 4466 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4467 if (SSELevel >= AVX512F) 4468 return Size <= 512U; 4469 else if (SSELevel >= AVX) 4470 return Size <= 256U; 4471 return SSELevel >= SSE2 && Size <= 128U; 4472 } 4473 4474 } 4475 4476 return true; 4477 } 4478 4479 std::string 4480 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4481 switch (*Constraint) { 4482 case 'a': return std::string("{ax}"); 4483 case 'b': return std::string("{bx}"); 4484 case 'c': return std::string("{cx}"); 4485 case 'd': return std::string("{dx}"); 4486 case 'S': return std::string("{si}"); 4487 case 'D': return std::string("{di}"); 4488 case 'p': // address 4489 return std::string("im"); 4490 case 't': // top of floating point stack. 4491 return std::string("{st}"); 4492 case 'u': // second from top of floating point stack. 4493 return std::string("{st(1)}"); // second from top of floating point stack. 4494 case 'Y': 4495 switch (Constraint[1]) { 4496 default: 4497 // Break from inner switch and fall through (copy single char), 4498 // continue parsing after copying the current constraint into 4499 // the return string. 4500 break; 4501 case 'k': 4502 // "^" hints llvm that this is a 2 letter constraint. 4503 // "Constraint++" is used to promote the string iterator 4504 // to the next constraint. 4505 return std::string("^") + std::string(Constraint++, 2); 4506 } 4507 LLVM_FALLTHROUGH; 4508 default: 4509 return std::string(1, *Constraint); 4510 } 4511 } 4512 4513 // X86-32 generic target 4514 class X86_32TargetInfo : public X86TargetInfo { 4515 public: 4516 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4517 : X86TargetInfo(Triple, Opts) { 4518 DoubleAlign = LongLongAlign = 32; 4519 LongDoubleWidth = 96; 4520 LongDoubleAlign = 32; 4521 SuitableAlign = 128; 4522 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4523 SizeType = UnsignedInt; 4524 PtrDiffType = SignedInt; 4525 IntPtrType = SignedInt; 4526 RegParmMax = 3; 4527 4528 // Use fpret for all types. 4529 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4530 (1 << TargetInfo::Double) | 4531 (1 << TargetInfo::LongDouble)); 4532 4533 // x86-32 has atomics up to 8 bytes 4534 // FIXME: Check that we actually have cmpxchg8b before setting 4535 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4536 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4537 } 4538 BuiltinVaListKind getBuiltinVaListKind() const override { 4539 return TargetInfo::CharPtrBuiltinVaList; 4540 } 4541 4542 int getEHDataRegisterNumber(unsigned RegNo) const override { 4543 if (RegNo == 0) return 0; 4544 if (RegNo == 1) return 2; 4545 return -1; 4546 } 4547 bool validateOperandSize(StringRef Constraint, 4548 unsigned Size) const override { 4549 switch (Constraint[0]) { 4550 default: break; 4551 case 'R': 4552 case 'q': 4553 case 'Q': 4554 case 'a': 4555 case 'b': 4556 case 'c': 4557 case 'd': 4558 case 'S': 4559 case 'D': 4560 return Size <= 32; 4561 case 'A': 4562 return Size <= 64; 4563 } 4564 4565 return X86TargetInfo::validateOperandSize(Constraint, Size); 4566 } 4567 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4568 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 4569 Builtin::FirstTSBuiltin + 1); 4570 } 4571 }; 4572 4573 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4574 public: 4575 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4576 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4577 4578 unsigned getFloatEvalMethod() const override { 4579 unsigned Major, Minor, Micro; 4580 getTriple().getOSVersion(Major, Minor, Micro); 4581 // New NetBSD uses the default rounding mode. 4582 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4583 return X86_32TargetInfo::getFloatEvalMethod(); 4584 // NetBSD before 6.99.26 defaults to "double" rounding. 4585 return 1; 4586 } 4587 }; 4588 4589 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4590 public: 4591 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4592 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4593 SizeType = UnsignedLong; 4594 IntPtrType = SignedLong; 4595 PtrDiffType = SignedLong; 4596 } 4597 }; 4598 4599 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4600 public: 4601 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4602 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4603 SizeType = UnsignedLong; 4604 IntPtrType = SignedLong; 4605 PtrDiffType = SignedLong; 4606 } 4607 }; 4608 4609 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4610 public: 4611 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4612 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4613 LongDoubleWidth = 128; 4614 LongDoubleAlign = 128; 4615 SuitableAlign = 128; 4616 MaxVectorAlign = 256; 4617 // The watchOS simulator uses the builtin bool type for Objective-C. 4618 llvm::Triple T = llvm::Triple(Triple); 4619 if (T.isWatchOS()) 4620 UseSignedCharForObjCBool = false; 4621 SizeType = UnsignedLong; 4622 IntPtrType = SignedLong; 4623 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4624 HasAlignMac68kSupport = true; 4625 } 4626 4627 bool handleTargetFeatures(std::vector<std::string> &Features, 4628 DiagnosticsEngine &Diags) override { 4629 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4630 Diags)) 4631 return false; 4632 // We now know the features we have: we can decide how to align vectors. 4633 MaxVectorAlign = 4634 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4635 return true; 4636 } 4637 }; 4638 4639 // x86-32 Windows target 4640 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4641 public: 4642 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4643 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4644 WCharType = UnsignedShort; 4645 DoubleAlign = LongLongAlign = 64; 4646 bool IsWinCOFF = 4647 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4648 resetDataLayout(IsWinCOFF 4649 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4650 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4651 } 4652 void getTargetDefines(const LangOptions &Opts, 4653 MacroBuilder &Builder) const override { 4654 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4655 } 4656 }; 4657 4658 // x86-32 Windows Visual Studio target 4659 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4660 public: 4661 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4662 const TargetOptions &Opts) 4663 : WindowsX86_32TargetInfo(Triple, Opts) { 4664 LongDoubleWidth = LongDoubleAlign = 64; 4665 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4666 } 4667 void getTargetDefines(const LangOptions &Opts, 4668 MacroBuilder &Builder) const override { 4669 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4670 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4671 // The value of the following reflects processor type. 4672 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4673 // We lost the original triple, so we use the default. 4674 Builder.defineMacro("_M_IX86", "600"); 4675 } 4676 }; 4677 4678 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4679 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4680 // supports __declspec natively under -fms-extensions, but we define a no-op 4681 // __declspec macro anyway for pre-processor compatibility. 4682 if (Opts.MicrosoftExt) 4683 Builder.defineMacro("__declspec", "__declspec"); 4684 else 4685 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4686 4687 if (!Opts.MicrosoftExt) { 4688 // Provide macros for all the calling convention keywords. Provide both 4689 // single and double underscore prefixed variants. These are available on 4690 // x64 as well as x86, even though they have no effect. 4691 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4692 for (const char *CC : CCs) { 4693 std::string GCCSpelling = "__attribute__((__"; 4694 GCCSpelling += CC; 4695 GCCSpelling += "__))"; 4696 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4697 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4698 } 4699 } 4700 } 4701 4702 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4703 Builder.defineMacro("__MSVCRT__"); 4704 Builder.defineMacro("__MINGW32__"); 4705 addCygMingDefines(Opts, Builder); 4706 } 4707 4708 // x86-32 MinGW target 4709 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4710 public: 4711 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4712 : WindowsX86_32TargetInfo(Triple, Opts) { 4713 HasFloat128 = true; 4714 } 4715 void getTargetDefines(const LangOptions &Opts, 4716 MacroBuilder &Builder) const override { 4717 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4718 DefineStd(Builder, "WIN32", Opts); 4719 DefineStd(Builder, "WINNT", Opts); 4720 Builder.defineMacro("_X86_"); 4721 addMinGWDefines(Opts, Builder); 4722 } 4723 }; 4724 4725 // x86-32 Cygwin target 4726 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4727 public: 4728 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4729 : X86_32TargetInfo(Triple, Opts) { 4730 WCharType = UnsignedShort; 4731 DoubleAlign = LongLongAlign = 64; 4732 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4733 } 4734 void getTargetDefines(const LangOptions &Opts, 4735 MacroBuilder &Builder) const override { 4736 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4737 Builder.defineMacro("_X86_"); 4738 Builder.defineMacro("__CYGWIN__"); 4739 Builder.defineMacro("__CYGWIN32__"); 4740 addCygMingDefines(Opts, Builder); 4741 DefineStd(Builder, "unix", Opts); 4742 if (Opts.CPlusPlus) 4743 Builder.defineMacro("_GNU_SOURCE"); 4744 } 4745 }; 4746 4747 // x86-32 Haiku target 4748 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4749 public: 4750 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4751 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4752 } 4753 void getTargetDefines(const LangOptions &Opts, 4754 MacroBuilder &Builder) const override { 4755 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4756 Builder.defineMacro("__INTEL__"); 4757 } 4758 }; 4759 4760 // X86-32 MCU target 4761 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4762 public: 4763 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4764 : X86_32TargetInfo(Triple, Opts) { 4765 LongDoubleWidth = 64; 4766 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4767 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4768 WIntType = UnsignedInt; 4769 } 4770 4771 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4772 // On MCU we support only C calling convention. 4773 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4774 } 4775 4776 void getTargetDefines(const LangOptions &Opts, 4777 MacroBuilder &Builder) const override { 4778 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4779 Builder.defineMacro("__iamcu"); 4780 Builder.defineMacro("__iamcu__"); 4781 } 4782 4783 bool allowsLargerPreferedTypeAlignment() const override { 4784 return false; 4785 } 4786 }; 4787 4788 // RTEMS Target 4789 template<typename Target> 4790 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4791 protected: 4792 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4793 MacroBuilder &Builder) const override { 4794 // RTEMS defines; list based off of gcc output 4795 4796 Builder.defineMacro("__rtems__"); 4797 Builder.defineMacro("__ELF__"); 4798 } 4799 4800 public: 4801 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4802 : OSTargetInfo<Target>(Triple, Opts) { 4803 switch (Triple.getArch()) { 4804 default: 4805 case llvm::Triple::x86: 4806 // this->MCountName = ".mcount"; 4807 break; 4808 case llvm::Triple::mips: 4809 case llvm::Triple::mipsel: 4810 case llvm::Triple::ppc: 4811 case llvm::Triple::ppc64: 4812 case llvm::Triple::ppc64le: 4813 // this->MCountName = "_mcount"; 4814 break; 4815 case llvm::Triple::arm: 4816 // this->MCountName = "__mcount"; 4817 break; 4818 } 4819 } 4820 }; 4821 4822 // x86-32 RTEMS target 4823 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4824 public: 4825 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4826 : X86_32TargetInfo(Triple, Opts) { 4827 SizeType = UnsignedLong; 4828 IntPtrType = SignedLong; 4829 PtrDiffType = SignedLong; 4830 } 4831 void getTargetDefines(const LangOptions &Opts, 4832 MacroBuilder &Builder) const override { 4833 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4834 Builder.defineMacro("__INTEL__"); 4835 Builder.defineMacro("__rtems__"); 4836 } 4837 }; 4838 4839 // x86-64 generic target 4840 class X86_64TargetInfo : public X86TargetInfo { 4841 public: 4842 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4843 : X86TargetInfo(Triple, Opts) { 4844 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4845 bool IsWinCOFF = 4846 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4847 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4848 LongDoubleWidth = 128; 4849 LongDoubleAlign = 128; 4850 LargeArrayMinWidth = 128; 4851 LargeArrayAlign = 128; 4852 SuitableAlign = 128; 4853 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4854 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4855 IntPtrType = IsX32 ? SignedInt : SignedLong; 4856 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4857 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4858 RegParmMax = 6; 4859 4860 // Pointers are 32-bit in x32. 4861 resetDataLayout(IsX32 4862 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4863 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4864 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4865 4866 // Use fpret only for long double. 4867 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4868 4869 // Use fp2ret for _Complex long double. 4870 ComplexLongDoubleUsesFP2Ret = true; 4871 4872 // Make __builtin_ms_va_list available. 4873 HasBuiltinMSVaList = true; 4874 4875 // x86-64 has atomics up to 16 bytes. 4876 MaxAtomicPromoteWidth = 128; 4877 MaxAtomicInlineWidth = 128; 4878 } 4879 BuiltinVaListKind getBuiltinVaListKind() const override { 4880 return TargetInfo::X86_64ABIBuiltinVaList; 4881 } 4882 4883 int getEHDataRegisterNumber(unsigned RegNo) const override { 4884 if (RegNo == 0) return 0; 4885 if (RegNo == 1) return 1; 4886 return -1; 4887 } 4888 4889 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4890 switch (CC) { 4891 case CC_C: 4892 case CC_Swift: 4893 case CC_X86VectorCall: 4894 case CC_IntelOclBicc: 4895 case CC_X86_64Win64: 4896 case CC_PreserveMost: 4897 case CC_PreserveAll: 4898 case CC_X86RegCall: 4899 case CC_OpenCLKernel: 4900 return CCCR_OK; 4901 default: 4902 return CCCR_Warning; 4903 } 4904 } 4905 4906 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4907 return CC_C; 4908 } 4909 4910 // for x32 we need it here explicitly 4911 bool hasInt128Type() const override { return true; } 4912 unsigned getUnwindWordWidth() const override { return 64; } 4913 unsigned getRegisterWidth() const override { return 64; } 4914 4915 bool validateGlobalRegisterVariable(StringRef RegName, 4916 unsigned RegSize, 4917 bool &HasSizeMismatch) const override { 4918 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4919 // handle. 4920 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4921 // Check that the register size is 64-bit. 4922 HasSizeMismatch = RegSize != 64; 4923 return true; 4924 } 4925 4926 // Check if the register is a 32-bit register the backend can handle. 4927 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4928 HasSizeMismatch); 4929 } 4930 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4931 return llvm::makeArrayRef(BuiltinInfoX86, 4932 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 4933 } 4934 }; 4935 4936 // x86-64 Windows target 4937 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4938 public: 4939 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4940 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4941 WCharType = UnsignedShort; 4942 LongWidth = LongAlign = 32; 4943 DoubleAlign = LongLongAlign = 64; 4944 IntMaxType = SignedLongLong; 4945 Int64Type = SignedLongLong; 4946 SizeType = UnsignedLongLong; 4947 PtrDiffType = SignedLongLong; 4948 IntPtrType = SignedLongLong; 4949 } 4950 4951 void getTargetDefines(const LangOptions &Opts, 4952 MacroBuilder &Builder) const override { 4953 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4954 Builder.defineMacro("_WIN64"); 4955 } 4956 4957 BuiltinVaListKind getBuiltinVaListKind() const override { 4958 return TargetInfo::CharPtrBuiltinVaList; 4959 } 4960 4961 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4962 switch (CC) { 4963 case CC_X86StdCall: 4964 case CC_X86ThisCall: 4965 case CC_X86FastCall: 4966 return CCCR_Ignore; 4967 case CC_C: 4968 case CC_X86VectorCall: 4969 case CC_IntelOclBicc: 4970 case CC_X86_64SysV: 4971 case CC_Swift: 4972 case CC_X86RegCall: 4973 case CC_OpenCLKernel: 4974 return CCCR_OK; 4975 default: 4976 return CCCR_Warning; 4977 } 4978 } 4979 }; 4980 4981 // x86-64 Windows Visual Studio target 4982 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4983 public: 4984 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4985 const TargetOptions &Opts) 4986 : WindowsX86_64TargetInfo(Triple, Opts) { 4987 LongDoubleWidth = LongDoubleAlign = 64; 4988 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4989 } 4990 void getTargetDefines(const LangOptions &Opts, 4991 MacroBuilder &Builder) const override { 4992 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4993 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4994 Builder.defineMacro("_M_X64", "100"); 4995 Builder.defineMacro("_M_AMD64", "100"); 4996 } 4997 }; 4998 4999 // x86-64 MinGW target 5000 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 5001 public: 5002 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5003 : WindowsX86_64TargetInfo(Triple, Opts) { 5004 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 5005 // with x86 FP ops. Weird. 5006 LongDoubleWidth = LongDoubleAlign = 128; 5007 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 5008 HasFloat128 = true; 5009 } 5010 5011 void getTargetDefines(const LangOptions &Opts, 5012 MacroBuilder &Builder) const override { 5013 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 5014 DefineStd(Builder, "WIN64", Opts); 5015 Builder.defineMacro("__MINGW64__"); 5016 addMinGWDefines(Opts, Builder); 5017 5018 // GCC defines this macro when it is using __gxx_personality_seh0. 5019 if (!Opts.SjLjExceptions) 5020 Builder.defineMacro("__SEH__"); 5021 } 5022 }; 5023 5024 // x86-64 Cygwin target 5025 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 5026 public: 5027 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5028 : X86_64TargetInfo(Triple, Opts) { 5029 TLSSupported = false; 5030 WCharType = UnsignedShort; 5031 } 5032 void getTargetDefines(const LangOptions &Opts, 5033 MacroBuilder &Builder) const override { 5034 X86_64TargetInfo::getTargetDefines(Opts, Builder); 5035 Builder.defineMacro("__x86_64__"); 5036 Builder.defineMacro("__CYGWIN__"); 5037 Builder.defineMacro("__CYGWIN64__"); 5038 addCygMingDefines(Opts, Builder); 5039 DefineStd(Builder, "unix", Opts); 5040 if (Opts.CPlusPlus) 5041 Builder.defineMacro("_GNU_SOURCE"); 5042 5043 // GCC defines this macro when it is using __gxx_personality_seh0. 5044 if (!Opts.SjLjExceptions) 5045 Builder.defineMacro("__SEH__"); 5046 } 5047 }; 5048 5049 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 5050 public: 5051 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5052 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5053 Int64Type = SignedLongLong; 5054 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 5055 llvm::Triple T = llvm::Triple(Triple); 5056 if (T.isiOS()) 5057 UseSignedCharForObjCBool = false; 5058 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 5059 } 5060 5061 bool handleTargetFeatures(std::vector<std::string> &Features, 5062 DiagnosticsEngine &Diags) override { 5063 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 5064 Diags)) 5065 return false; 5066 // We now know the features we have: we can decide how to align vectors. 5067 MaxVectorAlign = 5068 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 5069 return true; 5070 } 5071 }; 5072 5073 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 5074 public: 5075 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5076 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5077 IntMaxType = SignedLongLong; 5078 Int64Type = SignedLongLong; 5079 } 5080 }; 5081 5082 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 5083 public: 5084 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5085 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5086 IntMaxType = SignedLongLong; 5087 Int64Type = SignedLongLong; 5088 } 5089 }; 5090 5091 class ARMTargetInfo : public TargetInfo { 5092 // Possible FPU choices. 5093 enum FPUMode { 5094 VFP2FPU = (1 << 0), 5095 VFP3FPU = (1 << 1), 5096 VFP4FPU = (1 << 2), 5097 NeonFPU = (1 << 3), 5098 FPARMV8 = (1 << 4) 5099 }; 5100 5101 // Possible HWDiv features. 5102 enum HWDivMode { 5103 HWDivThumb = (1 << 0), 5104 HWDivARM = (1 << 1) 5105 }; 5106 5107 static bool FPUModeIsVFP(FPUMode Mode) { 5108 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 5109 } 5110 5111 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5112 static const char * const GCCRegNames[]; 5113 5114 std::string ABI, CPU; 5115 5116 StringRef CPUProfile; 5117 StringRef CPUAttr; 5118 5119 enum { 5120 FP_Default, 5121 FP_VFP, 5122 FP_Neon 5123 } FPMath; 5124 5125 unsigned ArchISA; 5126 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 5127 unsigned ArchProfile; 5128 unsigned ArchVersion; 5129 5130 unsigned FPU : 5; 5131 5132 unsigned IsAAPCS : 1; 5133 unsigned HWDiv : 2; 5134 5135 // Initialized via features. 5136 unsigned SoftFloat : 1; 5137 unsigned SoftFloatABI : 1; 5138 5139 unsigned CRC : 1; 5140 unsigned Crypto : 1; 5141 unsigned DSP : 1; 5142 unsigned Unaligned : 1; 5143 5144 enum { 5145 LDREX_B = (1 << 0), /// byte (8-bit) 5146 LDREX_H = (1 << 1), /// half (16-bit) 5147 LDREX_W = (1 << 2), /// word (32-bit) 5148 LDREX_D = (1 << 3), /// double (64-bit) 5149 }; 5150 5151 uint32_t LDREX; 5152 5153 // ACLE 6.5.1 Hardware floating point 5154 enum { 5155 HW_FP_HP = (1 << 1), /// half (16-bit) 5156 HW_FP_SP = (1 << 2), /// single (32-bit) 5157 HW_FP_DP = (1 << 3), /// double (64-bit) 5158 }; 5159 uint32_t HW_FP; 5160 5161 static const Builtin::Info BuiltinInfo[]; 5162 5163 void setABIAAPCS() { 5164 IsAAPCS = true; 5165 5166 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5167 const llvm::Triple &T = getTriple(); 5168 5169 // size_t is unsigned long on MachO-derived environments, NetBSD, 5170 // OpenBSD and Bitrig. 5171 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 5172 T.getOS() == llvm::Triple::OpenBSD || 5173 T.getOS() == llvm::Triple::Bitrig) 5174 SizeType = UnsignedLong; 5175 else 5176 SizeType = UnsignedInt; 5177 5178 switch (T.getOS()) { 5179 case llvm::Triple::NetBSD: 5180 case llvm::Triple::OpenBSD: 5181 WCharType = SignedInt; 5182 break; 5183 case llvm::Triple::Win32: 5184 WCharType = UnsignedShort; 5185 break; 5186 case llvm::Triple::Linux: 5187 default: 5188 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 5189 WCharType = UnsignedInt; 5190 break; 5191 } 5192 5193 UseBitFieldTypeAlignment = true; 5194 5195 ZeroLengthBitfieldBoundary = 0; 5196 5197 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 5198 // so set preferred for small types to 32. 5199 if (T.isOSBinFormatMachO()) { 5200 resetDataLayout(BigEndian 5201 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5202 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5203 } else if (T.isOSWindows()) { 5204 assert(!BigEndian && "Windows on ARM does not support big endian"); 5205 resetDataLayout("e" 5206 "-m:w" 5207 "-p:32:32" 5208 "-i64:64" 5209 "-v128:64:128" 5210 "-a:0:32" 5211 "-n32" 5212 "-S64"); 5213 } else if (T.isOSNaCl()) { 5214 assert(!BigEndian && "NaCl on ARM does not support big endian"); 5215 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 5216 } else { 5217 resetDataLayout(BigEndian 5218 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5219 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5220 } 5221 5222 // FIXME: Enumerated types are variable width in straight AAPCS. 5223 } 5224 5225 void setABIAPCS(bool IsAAPCS16) { 5226 const llvm::Triple &T = getTriple(); 5227 5228 IsAAPCS = false; 5229 5230 if (IsAAPCS16) 5231 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5232 else 5233 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 5234 5235 // size_t is unsigned int on FreeBSD. 5236 if (T.getOS() == llvm::Triple::FreeBSD) 5237 SizeType = UnsignedInt; 5238 else 5239 SizeType = UnsignedLong; 5240 5241 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 5242 WCharType = SignedInt; 5243 5244 // Do not respect the alignment of bit-field types when laying out 5245 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 5246 UseBitFieldTypeAlignment = false; 5247 5248 /// gcc forces the alignment to 4 bytes, regardless of the type of the 5249 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 5250 /// gcc. 5251 ZeroLengthBitfieldBoundary = 32; 5252 5253 if (T.isOSBinFormatMachO() && IsAAPCS16) { 5254 assert(!BigEndian && "AAPCS16 does not support big-endian"); 5255 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 5256 } else if (T.isOSBinFormatMachO()) 5257 resetDataLayout( 5258 BigEndian 5259 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5260 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5261 else 5262 resetDataLayout( 5263 BigEndian 5264 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5265 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5266 5267 // FIXME: Override "preferred align" for double and long long. 5268 } 5269 5270 void setArchInfo() { 5271 StringRef ArchName = getTriple().getArchName(); 5272 5273 ArchISA = llvm::ARM::parseArchISA(ArchName); 5274 CPU = llvm::ARM::getDefaultCPU(ArchName); 5275 unsigned AK = llvm::ARM::parseArch(ArchName); 5276 if (AK != llvm::ARM::AK_INVALID) 5277 ArchKind = AK; 5278 setArchInfo(ArchKind); 5279 } 5280 5281 void setArchInfo(unsigned Kind) { 5282 StringRef SubArch; 5283 5284 // cache TargetParser info 5285 ArchKind = Kind; 5286 SubArch = llvm::ARM::getSubArch(ArchKind); 5287 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 5288 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 5289 5290 // cache CPU related strings 5291 CPUAttr = getCPUAttr(); 5292 CPUProfile = getCPUProfile(); 5293 } 5294 5295 void setAtomic() { 5296 // when triple does not specify a sub arch, 5297 // then we are not using inline atomics 5298 bool ShouldUseInlineAtomic = 5299 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 5300 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 5301 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 5302 if (ArchProfile == llvm::ARM::PK_M) { 5303 MaxAtomicPromoteWidth = 32; 5304 if (ShouldUseInlineAtomic) 5305 MaxAtomicInlineWidth = 32; 5306 } 5307 else { 5308 MaxAtomicPromoteWidth = 64; 5309 if (ShouldUseInlineAtomic) 5310 MaxAtomicInlineWidth = 64; 5311 } 5312 } 5313 5314 bool isThumb() const { 5315 return (ArchISA == llvm::ARM::IK_THUMB); 5316 } 5317 5318 bool supportsThumb() const { 5319 return CPUAttr.count('T') || ArchVersion >= 6; 5320 } 5321 5322 bool supportsThumb2() const { 5323 return CPUAttr.equals("6T2") || 5324 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 5325 } 5326 5327 StringRef getCPUAttr() const { 5328 // For most sub-arches, the build attribute CPU name is enough. 5329 // For Cortex variants, it's slightly different. 5330 switch(ArchKind) { 5331 default: 5332 return llvm::ARM::getCPUAttr(ArchKind); 5333 case llvm::ARM::AK_ARMV6M: 5334 return "6M"; 5335 case llvm::ARM::AK_ARMV7S: 5336 return "7S"; 5337 case llvm::ARM::AK_ARMV7A: 5338 return "7A"; 5339 case llvm::ARM::AK_ARMV7R: 5340 return "7R"; 5341 case llvm::ARM::AK_ARMV7M: 5342 return "7M"; 5343 case llvm::ARM::AK_ARMV7EM: 5344 return "7EM"; 5345 case llvm::ARM::AK_ARMV7VE: 5346 return "7VE"; 5347 case llvm::ARM::AK_ARMV8A: 5348 return "8A"; 5349 case llvm::ARM::AK_ARMV8_1A: 5350 return "8_1A"; 5351 case llvm::ARM::AK_ARMV8_2A: 5352 return "8_2A"; 5353 case llvm::ARM::AK_ARMV8MBaseline: 5354 return "8M_BASE"; 5355 case llvm::ARM::AK_ARMV8MMainline: 5356 return "8M_MAIN"; 5357 case llvm::ARM::AK_ARMV8R: 5358 return "8R"; 5359 } 5360 } 5361 5362 StringRef getCPUProfile() const { 5363 switch(ArchProfile) { 5364 case llvm::ARM::PK_A: 5365 return "A"; 5366 case llvm::ARM::PK_R: 5367 return "R"; 5368 case llvm::ARM::PK_M: 5369 return "M"; 5370 default: 5371 return ""; 5372 } 5373 } 5374 5375 public: 5376 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5377 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 5378 HW_FP(0) { 5379 5380 switch (getTriple().getOS()) { 5381 case llvm::Triple::NetBSD: 5382 case llvm::Triple::OpenBSD: 5383 PtrDiffType = SignedLong; 5384 break; 5385 default: 5386 PtrDiffType = SignedInt; 5387 break; 5388 } 5389 5390 // Cache arch related info. 5391 setArchInfo(); 5392 5393 // {} in inline assembly are neon specifiers, not assembly variant 5394 // specifiers. 5395 NoAsmVariants = true; 5396 5397 // FIXME: This duplicates code from the driver that sets the -target-abi 5398 // option - this code is used if -target-abi isn't passed and should 5399 // be unified in some way. 5400 if (Triple.isOSBinFormatMachO()) { 5401 // The backend is hardwired to assume AAPCS for M-class processors, ensure 5402 // the frontend matches that. 5403 if (Triple.getEnvironment() == llvm::Triple::EABI || 5404 Triple.getOS() == llvm::Triple::UnknownOS || 5405 ArchProfile == llvm::ARM::PK_M) { 5406 setABI("aapcs"); 5407 } else if (Triple.isWatchABI()) { 5408 setABI("aapcs16"); 5409 } else { 5410 setABI("apcs-gnu"); 5411 } 5412 } else if (Triple.isOSWindows()) { 5413 // FIXME: this is invalid for WindowsCE 5414 setABI("aapcs"); 5415 } else { 5416 // Select the default based on the platform. 5417 switch (Triple.getEnvironment()) { 5418 case llvm::Triple::Android: 5419 case llvm::Triple::GNUEABI: 5420 case llvm::Triple::GNUEABIHF: 5421 case llvm::Triple::MuslEABI: 5422 case llvm::Triple::MuslEABIHF: 5423 setABI("aapcs-linux"); 5424 break; 5425 case llvm::Triple::EABIHF: 5426 case llvm::Triple::EABI: 5427 setABI("aapcs"); 5428 break; 5429 case llvm::Triple::GNU: 5430 setABI("apcs-gnu"); 5431 break; 5432 default: 5433 if (Triple.getOS() == llvm::Triple::NetBSD) 5434 setABI("apcs-gnu"); 5435 else if (Triple.getOS() == llvm::Triple::OpenBSD) 5436 setABI("aapcs-linux"); 5437 else 5438 setABI("aapcs"); 5439 break; 5440 } 5441 } 5442 5443 // ARM targets default to using the ARM C++ ABI. 5444 TheCXXABI.set(TargetCXXABI::GenericARM); 5445 5446 // ARM has atomics up to 8 bytes 5447 setAtomic(); 5448 5449 // Maximum alignment for ARM NEON data types should be 64-bits (AAPCS) 5450 if (IsAAPCS && (Triple.getEnvironment() != llvm::Triple::Android)) 5451 MaxVectorAlign = 64; 5452 5453 // Do force alignment of members that follow zero length bitfields. If 5454 // the alignment of the zero-length bitfield is greater than the member 5455 // that follows it, `bar', `bar' will be aligned as the type of the 5456 // zero length bitfield. 5457 UseZeroLengthBitfieldAlignment = true; 5458 5459 if (Triple.getOS() == llvm::Triple::Linux || 5460 Triple.getOS() == llvm::Triple::UnknownOS) 5461 this->MCountName = 5462 Opts.EABIVersion == llvm::EABI::GNU ? "\01__gnu_mcount_nc" : "\01mcount"; 5463 } 5464 5465 StringRef getABI() const override { return ABI; } 5466 5467 bool setABI(const std::string &Name) override { 5468 ABI = Name; 5469 5470 // The defaults (above) are for AAPCS, check if we need to change them. 5471 // 5472 // FIXME: We need support for -meabi... we could just mangle it into the 5473 // name. 5474 if (Name == "apcs-gnu" || Name == "aapcs16") { 5475 setABIAPCS(Name == "aapcs16"); 5476 return true; 5477 } 5478 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 5479 setABIAAPCS(); 5480 return true; 5481 } 5482 return false; 5483 } 5484 5485 // FIXME: This should be based on Arch attributes, not CPU names. 5486 bool 5487 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5488 StringRef CPU, 5489 const std::vector<std::string> &FeaturesVec) const override { 5490 5491 std::vector<StringRef> TargetFeatures; 5492 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 5493 5494 // get default FPU features 5495 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 5496 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 5497 5498 // get default Extension features 5499 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 5500 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 5501 5502 for (auto Feature : TargetFeatures) 5503 if (Feature[0] == '+') 5504 Features[Feature.drop_front(1)] = true; 5505 5506 // Enable or disable thumb-mode explicitly per function to enable mixed 5507 // ARM and Thumb code generation. 5508 if (isThumb()) 5509 Features["thumb-mode"] = true; 5510 else 5511 Features["thumb-mode"] = false; 5512 5513 // Convert user-provided arm and thumb GNU target attributes to 5514 // [-|+]thumb-mode target features respectively. 5515 std::vector<std::string> UpdatedFeaturesVec(FeaturesVec); 5516 for (auto &Feature : UpdatedFeaturesVec) { 5517 if (Feature.compare("+arm") == 0) 5518 Feature = "-thumb-mode"; 5519 else if (Feature.compare("+thumb") == 0) 5520 Feature = "+thumb-mode"; 5521 } 5522 5523 return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec); 5524 } 5525 5526 bool handleTargetFeatures(std::vector<std::string> &Features, 5527 DiagnosticsEngine &Diags) override { 5528 FPU = 0; 5529 CRC = 0; 5530 Crypto = 0; 5531 DSP = 0; 5532 Unaligned = 1; 5533 SoftFloat = SoftFloatABI = false; 5534 HWDiv = 0; 5535 5536 // This does not diagnose illegal cases like having both 5537 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5538 uint32_t HW_FP_remove = 0; 5539 for (const auto &Feature : Features) { 5540 if (Feature == "+soft-float") { 5541 SoftFloat = true; 5542 } else if (Feature == "+soft-float-abi") { 5543 SoftFloatABI = true; 5544 } else if (Feature == "+vfp2") { 5545 FPU |= VFP2FPU; 5546 HW_FP |= HW_FP_SP | HW_FP_DP; 5547 } else if (Feature == "+vfp3") { 5548 FPU |= VFP3FPU; 5549 HW_FP |= HW_FP_SP | HW_FP_DP; 5550 } else if (Feature == "+vfp4") { 5551 FPU |= VFP4FPU; 5552 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5553 } else if (Feature == "+fp-armv8") { 5554 FPU |= FPARMV8; 5555 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5556 } else if (Feature == "+neon") { 5557 FPU |= NeonFPU; 5558 HW_FP |= HW_FP_SP | HW_FP_DP; 5559 } else if (Feature == "+hwdiv") { 5560 HWDiv |= HWDivThumb; 5561 } else if (Feature == "+hwdiv-arm") { 5562 HWDiv |= HWDivARM; 5563 } else if (Feature == "+crc") { 5564 CRC = 1; 5565 } else if (Feature == "+crypto") { 5566 Crypto = 1; 5567 } else if (Feature == "+dsp") { 5568 DSP = 1; 5569 } else if (Feature == "+fp-only-sp") { 5570 HW_FP_remove |= HW_FP_DP; 5571 } else if (Feature == "+strict-align") { 5572 Unaligned = 0; 5573 } else if (Feature == "+fp16") { 5574 HW_FP |= HW_FP_HP; 5575 } 5576 } 5577 HW_FP &= ~HW_FP_remove; 5578 5579 switch (ArchVersion) { 5580 case 6: 5581 if (ArchProfile == llvm::ARM::PK_M) 5582 LDREX = 0; 5583 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5584 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5585 else 5586 LDREX = LDREX_W; 5587 break; 5588 case 7: 5589 if (ArchProfile == llvm::ARM::PK_M) 5590 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5591 else 5592 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5593 break; 5594 case 8: 5595 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5596 } 5597 5598 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5599 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5600 return false; 5601 } 5602 5603 if (FPMath == FP_Neon) 5604 Features.push_back("+neonfp"); 5605 else if (FPMath == FP_VFP) 5606 Features.push_back("-neonfp"); 5607 5608 // Remove front-end specific options which the backend handles differently. 5609 auto Feature = 5610 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5611 if (Feature != Features.end()) 5612 Features.erase(Feature); 5613 5614 return true; 5615 } 5616 5617 bool hasFeature(StringRef Feature) const override { 5618 return llvm::StringSwitch<bool>(Feature) 5619 .Case("arm", true) 5620 .Case("aarch32", true) 5621 .Case("softfloat", SoftFloat) 5622 .Case("thumb", isThumb()) 5623 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5624 .Case("vfp", FPU && !SoftFloat) 5625 .Case("hwdiv", HWDiv & HWDivThumb) 5626 .Case("hwdiv-arm", HWDiv & HWDivARM) 5627 .Default(false); 5628 } 5629 5630 bool setCPU(const std::string &Name) override { 5631 if (Name != "generic") 5632 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5633 5634 if (ArchKind == llvm::ARM::AK_INVALID) 5635 return false; 5636 setAtomic(); 5637 CPU = Name; 5638 return true; 5639 } 5640 5641 bool setFPMath(StringRef Name) override; 5642 5643 void getTargetDefinesARMV81A(const LangOptions &Opts, 5644 MacroBuilder &Builder) const { 5645 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5646 } 5647 5648 void getTargetDefinesARMV82A(const LangOptions &Opts, 5649 MacroBuilder &Builder) const { 5650 // Also include the ARMv8.1-A defines 5651 getTargetDefinesARMV81A(Opts, Builder); 5652 } 5653 5654 void getTargetDefines(const LangOptions &Opts, 5655 MacroBuilder &Builder) const override { 5656 // Target identification. 5657 Builder.defineMacro("__arm"); 5658 Builder.defineMacro("__arm__"); 5659 // For bare-metal none-eabi. 5660 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5661 (getTriple().getEnvironment() == llvm::Triple::EABI || 5662 getTriple().getEnvironment() == llvm::Triple::EABIHF)) 5663 Builder.defineMacro("__ELF__"); 5664 5665 5666 // Target properties. 5667 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5668 5669 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5670 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5671 if (getTriple().isWatchABI()) 5672 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5673 5674 if (!CPUAttr.empty()) 5675 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5676 5677 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5678 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5679 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5680 5681 if (ArchVersion >= 8) { 5682 // ACLE 6.5.7 Crypto Extension 5683 if (Crypto) 5684 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5685 // ACLE 6.5.8 CRC32 Extension 5686 if (CRC) 5687 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5688 // ACLE 6.5.10 Numeric Maximum and Minimum 5689 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5690 // ACLE 6.5.9 Directed Rounding 5691 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5692 } 5693 5694 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5695 // is not defined for the M-profile. 5696 // NOTE that the default profile is assumed to be 'A' 5697 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5698 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5699 5700 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5701 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5702 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5703 // v7 and v8 architectures excluding v8-M Baseline. 5704 if (supportsThumb2()) 5705 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5706 else if (supportsThumb()) 5707 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5708 5709 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5710 // instruction set such as ARM or Thumb. 5711 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5712 5713 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5714 5715 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5716 if (!CPUProfile.empty()) 5717 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5718 5719 // ACLE 6.4.3 Unaligned access supported in hardware 5720 if (Unaligned) 5721 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5722 5723 // ACLE 6.4.4 LDREX/STREX 5724 if (LDREX) 5725 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5726 5727 // ACLE 6.4.5 CLZ 5728 if (ArchVersion == 5 || 5729 (ArchVersion == 6 && CPUProfile != "M") || 5730 ArchVersion > 6) 5731 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5732 5733 // ACLE 6.5.1 Hardware Floating Point 5734 if (HW_FP) 5735 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5736 5737 // ACLE predefines. 5738 Builder.defineMacro("__ARM_ACLE", "200"); 5739 5740 // FP16 support (we currently only support IEEE format). 5741 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5742 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5743 5744 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5745 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5746 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5747 5748 // Subtarget options. 5749 5750 // FIXME: It's more complicated than this and we don't really support 5751 // interworking. 5752 // Windows on ARM does not "support" interworking 5753 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5754 Builder.defineMacro("__THUMB_INTERWORK__"); 5755 5756 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5757 // Embedded targets on Darwin follow AAPCS, but not EABI. 5758 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5759 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5760 Builder.defineMacro("__ARM_EABI__"); 5761 Builder.defineMacro("__ARM_PCS", "1"); 5762 } 5763 5764 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5765 ABI == "aapcs16") 5766 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5767 5768 if (SoftFloat) 5769 Builder.defineMacro("__SOFTFP__"); 5770 5771 if (ArchKind == llvm::ARM::AK_XSCALE) 5772 Builder.defineMacro("__XSCALE__"); 5773 5774 if (isThumb()) { 5775 Builder.defineMacro("__THUMBEL__"); 5776 Builder.defineMacro("__thumb__"); 5777 if (supportsThumb2()) 5778 Builder.defineMacro("__thumb2__"); 5779 } 5780 5781 // ACLE 6.4.9 32-bit SIMD instructions 5782 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5783 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5784 5785 // ACLE 6.4.10 Hardware Integer Divide 5786 if (((HWDiv & HWDivThumb) && isThumb()) || 5787 ((HWDiv & HWDivARM) && !isThumb())) { 5788 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5789 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5790 } 5791 5792 // Note, this is always on in gcc, even though it doesn't make sense. 5793 Builder.defineMacro("__APCS_32__"); 5794 5795 if (FPUModeIsVFP((FPUMode) FPU)) { 5796 Builder.defineMacro("__VFP_FP__"); 5797 if (FPU & VFP2FPU) 5798 Builder.defineMacro("__ARM_VFPV2__"); 5799 if (FPU & VFP3FPU) 5800 Builder.defineMacro("__ARM_VFPV3__"); 5801 if (FPU & VFP4FPU) 5802 Builder.defineMacro("__ARM_VFPV4__"); 5803 if (FPU & FPARMV8) 5804 Builder.defineMacro("__ARM_FPV5__"); 5805 } 5806 5807 // This only gets set when Neon instructions are actually available, unlike 5808 // the VFP define, hence the soft float and arch check. This is subtly 5809 // different from gcc, we follow the intent which was that it should be set 5810 // when Neon instructions are actually available. 5811 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5812 Builder.defineMacro("__ARM_NEON", "1"); 5813 Builder.defineMacro("__ARM_NEON__"); 5814 // current AArch32 NEON implementations do not support double-precision 5815 // floating-point even when it is present in VFP. 5816 Builder.defineMacro("__ARM_NEON_FP", 5817 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5818 } 5819 5820 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5821 Opts.ShortWChar ? "2" : "4"); 5822 5823 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5824 Opts.ShortEnums ? "1" : "4"); 5825 5826 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5827 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5828 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5829 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5830 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5831 } 5832 5833 // ACLE 6.4.7 DSP instructions 5834 if (DSP) { 5835 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5836 } 5837 5838 // ACLE 6.4.8 Saturation instructions 5839 bool SAT = false; 5840 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5841 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5842 SAT = true; 5843 } 5844 5845 // ACLE 6.4.6 Q (saturation) flag 5846 if (DSP || SAT) 5847 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5848 5849 if (Opts.UnsafeFPMath) 5850 Builder.defineMacro("__ARM_FP_FAST", "1"); 5851 5852 switch(ArchKind) { 5853 default: break; 5854 case llvm::ARM::AK_ARMV8_1A: 5855 getTargetDefinesARMV81A(Opts, Builder); 5856 break; 5857 case llvm::ARM::AK_ARMV8_2A: 5858 getTargetDefinesARMV82A(Opts, Builder); 5859 break; 5860 } 5861 } 5862 5863 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5864 return llvm::makeArrayRef(BuiltinInfo, 5865 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5866 } 5867 bool isCLZForZeroUndef() const override { return false; } 5868 BuiltinVaListKind getBuiltinVaListKind() const override { 5869 return IsAAPCS 5870 ? AAPCSABIBuiltinVaList 5871 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5872 : TargetInfo::VoidPtrBuiltinVaList); 5873 } 5874 ArrayRef<const char *> getGCCRegNames() const override; 5875 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5876 bool validateAsmConstraint(const char *&Name, 5877 TargetInfo::ConstraintInfo &Info) const override { 5878 switch (*Name) { 5879 default: break; 5880 case 'l': // r0-r7 5881 case 'h': // r8-r15 5882 case 't': // VFP Floating point register single precision 5883 case 'w': // VFP Floating point register double precision 5884 Info.setAllowsRegister(); 5885 return true; 5886 case 'I': 5887 case 'J': 5888 case 'K': 5889 case 'L': 5890 case 'M': 5891 // FIXME 5892 return true; 5893 case 'Q': // A memory address that is a single base register. 5894 Info.setAllowsMemory(); 5895 return true; 5896 case 'U': // a memory reference... 5897 switch (Name[1]) { 5898 case 'q': // ...ARMV4 ldrsb 5899 case 'v': // ...VFP load/store (reg+constant offset) 5900 case 'y': // ...iWMMXt load/store 5901 case 't': // address valid for load/store opaque types wider 5902 // than 128-bits 5903 case 'n': // valid address for Neon doubleword vector load/store 5904 case 'm': // valid address for Neon element and structure load/store 5905 case 's': // valid address for non-offset loads/stores of quad-word 5906 // values in four ARM registers 5907 Info.setAllowsMemory(); 5908 Name++; 5909 return true; 5910 } 5911 } 5912 return false; 5913 } 5914 std::string convertConstraint(const char *&Constraint) const override { 5915 std::string R; 5916 switch (*Constraint) { 5917 case 'U': // Two-character constraint; add "^" hint for later parsing. 5918 R = std::string("^") + std::string(Constraint, 2); 5919 Constraint++; 5920 break; 5921 case 'p': // 'p' should be translated to 'r' by default. 5922 R = std::string("r"); 5923 break; 5924 default: 5925 return std::string(1, *Constraint); 5926 } 5927 return R; 5928 } 5929 bool 5930 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5931 std::string &SuggestedModifier) const override { 5932 bool isOutput = (Constraint[0] == '='); 5933 bool isInOut = (Constraint[0] == '+'); 5934 5935 // Strip off constraint modifiers. 5936 while (Constraint[0] == '=' || 5937 Constraint[0] == '+' || 5938 Constraint[0] == '&') 5939 Constraint = Constraint.substr(1); 5940 5941 switch (Constraint[0]) { 5942 default: break; 5943 case 'r': { 5944 switch (Modifier) { 5945 default: 5946 return (isInOut || isOutput || Size <= 64); 5947 case 'q': 5948 // A register of size 32 cannot fit a vector type. 5949 return false; 5950 } 5951 } 5952 } 5953 5954 return true; 5955 } 5956 const char *getClobbers() const override { 5957 // FIXME: Is this really right? 5958 return ""; 5959 } 5960 5961 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5962 switch (CC) { 5963 case CC_AAPCS: 5964 case CC_AAPCS_VFP: 5965 case CC_Swift: 5966 case CC_OpenCLKernel: 5967 return CCCR_OK; 5968 default: 5969 return CCCR_Warning; 5970 } 5971 } 5972 5973 int getEHDataRegisterNumber(unsigned RegNo) const override { 5974 if (RegNo == 0) return 0; 5975 if (RegNo == 1) return 1; 5976 return -1; 5977 } 5978 5979 bool hasSjLjLowering() const override { 5980 return true; 5981 } 5982 }; 5983 5984 bool ARMTargetInfo::setFPMath(StringRef Name) { 5985 if (Name == "neon") { 5986 FPMath = FP_Neon; 5987 return true; 5988 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5989 Name == "vfp4") { 5990 FPMath = FP_VFP; 5991 return true; 5992 } 5993 return false; 5994 } 5995 5996 const char * const ARMTargetInfo::GCCRegNames[] = { 5997 // Integer registers 5998 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5999 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 6000 6001 // Float registers 6002 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 6003 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 6004 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 6005 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6006 6007 // Double registers 6008 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 6009 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 6010 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 6011 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6012 6013 // Quad registers 6014 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 6015 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 6016 }; 6017 6018 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 6019 return llvm::makeArrayRef(GCCRegNames); 6020 } 6021 6022 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 6023 { { "a1" }, "r0" }, 6024 { { "a2" }, "r1" }, 6025 { { "a3" }, "r2" }, 6026 { { "a4" }, "r3" }, 6027 { { "v1" }, "r4" }, 6028 { { "v2" }, "r5" }, 6029 { { "v3" }, "r6" }, 6030 { { "v4" }, "r7" }, 6031 { { "v5" }, "r8" }, 6032 { { "v6", "rfp" }, "r9" }, 6033 { { "sl" }, "r10" }, 6034 { { "fp" }, "r11" }, 6035 { { "ip" }, "r12" }, 6036 { { "r13" }, "sp" }, 6037 { { "r14" }, "lr" }, 6038 { { "r15" }, "pc" }, 6039 // The S, D and Q registers overlap, but aren't really aliases; we 6040 // don't want to substitute one of these for a different-sized one. 6041 }; 6042 6043 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 6044 return llvm::makeArrayRef(GCCRegAliases); 6045 } 6046 6047 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 6048 #define BUILTIN(ID, TYPE, ATTRS) \ 6049 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6050 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6051 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6052 #include "clang/Basic/BuiltinsNEON.def" 6053 6054 #define BUILTIN(ID, TYPE, ATTRS) \ 6055 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6056 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 6057 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 6058 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6059 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6060 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 6061 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 6062 #include "clang/Basic/BuiltinsARM.def" 6063 }; 6064 6065 class ARMleTargetInfo : public ARMTargetInfo { 6066 public: 6067 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6068 : ARMTargetInfo(Triple, Opts) {} 6069 void getTargetDefines(const LangOptions &Opts, 6070 MacroBuilder &Builder) const override { 6071 Builder.defineMacro("__ARMEL__"); 6072 ARMTargetInfo::getTargetDefines(Opts, Builder); 6073 } 6074 }; 6075 6076 class ARMbeTargetInfo : public ARMTargetInfo { 6077 public: 6078 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6079 : ARMTargetInfo(Triple, Opts) {} 6080 void getTargetDefines(const LangOptions &Opts, 6081 MacroBuilder &Builder) const override { 6082 Builder.defineMacro("__ARMEB__"); 6083 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6084 ARMTargetInfo::getTargetDefines(Opts, Builder); 6085 } 6086 }; 6087 6088 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 6089 const llvm::Triple Triple; 6090 public: 6091 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6092 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 6093 WCharType = UnsignedShort; 6094 SizeType = UnsignedInt; 6095 } 6096 void getVisualStudioDefines(const LangOptions &Opts, 6097 MacroBuilder &Builder) const { 6098 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 6099 6100 // FIXME: this is invalid for WindowsCE 6101 Builder.defineMacro("_M_ARM_NT", "1"); 6102 Builder.defineMacro("_M_ARMT", "_M_ARM"); 6103 Builder.defineMacro("_M_THUMB", "_M_ARM"); 6104 6105 assert((Triple.getArch() == llvm::Triple::arm || 6106 Triple.getArch() == llvm::Triple::thumb) && 6107 "invalid architecture for Windows ARM target info"); 6108 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 6109 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 6110 6111 // TODO map the complete set of values 6112 // 31: VFPv3 40: VFPv4 6113 Builder.defineMacro("_M_ARM_FP", "31"); 6114 } 6115 BuiltinVaListKind getBuiltinVaListKind() const override { 6116 return TargetInfo::CharPtrBuiltinVaList; 6117 } 6118 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6119 switch (CC) { 6120 case CC_X86StdCall: 6121 case CC_X86ThisCall: 6122 case CC_X86FastCall: 6123 case CC_X86VectorCall: 6124 return CCCR_Ignore; 6125 case CC_C: 6126 case CC_OpenCLKernel: 6127 return CCCR_OK; 6128 default: 6129 return CCCR_Warning; 6130 } 6131 } 6132 }; 6133 6134 // Windows ARM + Itanium C++ ABI Target 6135 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 6136 public: 6137 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 6138 const TargetOptions &Opts) 6139 : WindowsARMTargetInfo(Triple, Opts) { 6140 TheCXXABI.set(TargetCXXABI::GenericARM); 6141 } 6142 6143 void getTargetDefines(const LangOptions &Opts, 6144 MacroBuilder &Builder) const override { 6145 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6146 6147 if (Opts.MSVCCompat) 6148 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 6149 } 6150 }; 6151 6152 // Windows ARM, MS (C++) ABI 6153 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 6154 public: 6155 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 6156 const TargetOptions &Opts) 6157 : WindowsARMTargetInfo(Triple, Opts) { 6158 TheCXXABI.set(TargetCXXABI::Microsoft); 6159 } 6160 6161 void getTargetDefines(const LangOptions &Opts, 6162 MacroBuilder &Builder) const override { 6163 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6164 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 6165 } 6166 }; 6167 6168 // ARM MinGW target 6169 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 6170 public: 6171 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6172 : WindowsARMTargetInfo(Triple, Opts) { 6173 TheCXXABI.set(TargetCXXABI::GenericARM); 6174 } 6175 6176 void getTargetDefines(const LangOptions &Opts, 6177 MacroBuilder &Builder) const override { 6178 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6179 DefineStd(Builder, "WIN32", Opts); 6180 DefineStd(Builder, "WINNT", Opts); 6181 Builder.defineMacro("_ARM_"); 6182 addMinGWDefines(Opts, Builder); 6183 } 6184 }; 6185 6186 // ARM Cygwin target 6187 class CygwinARMTargetInfo : public ARMleTargetInfo { 6188 public: 6189 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6190 : ARMleTargetInfo(Triple, Opts) { 6191 TLSSupported = false; 6192 WCharType = UnsignedShort; 6193 DoubleAlign = LongLongAlign = 64; 6194 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 6195 } 6196 void getTargetDefines(const LangOptions &Opts, 6197 MacroBuilder &Builder) const override { 6198 ARMleTargetInfo::getTargetDefines(Opts, Builder); 6199 Builder.defineMacro("_ARM_"); 6200 Builder.defineMacro("__CYGWIN__"); 6201 Builder.defineMacro("__CYGWIN32__"); 6202 DefineStd(Builder, "unix", Opts); 6203 if (Opts.CPlusPlus) 6204 Builder.defineMacro("_GNU_SOURCE"); 6205 } 6206 }; 6207 6208 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 6209 protected: 6210 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6211 MacroBuilder &Builder) const override { 6212 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6213 } 6214 6215 public: 6216 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6217 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 6218 HasAlignMac68kSupport = true; 6219 // iOS always has 64-bit atomic instructions. 6220 // FIXME: This should be based off of the target features in 6221 // ARMleTargetInfo. 6222 MaxAtomicInlineWidth = 64; 6223 6224 if (Triple.isWatchABI()) { 6225 // Darwin on iOS uses a variant of the ARM C++ ABI. 6226 TheCXXABI.set(TargetCXXABI::WatchOS); 6227 6228 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 6229 // size_t is long, it's a bit weird for it to be int. 6230 PtrDiffType = SignedLong; 6231 6232 // BOOL should be a real boolean on the new ABI 6233 UseSignedCharForObjCBool = false; 6234 } else 6235 TheCXXABI.set(TargetCXXABI::iOS); 6236 } 6237 }; 6238 6239 class AArch64TargetInfo : public TargetInfo { 6240 virtual void setDataLayout() = 0; 6241 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6242 static const char *const GCCRegNames[]; 6243 6244 enum FPUModeEnum { 6245 FPUMode, 6246 NeonMode 6247 }; 6248 6249 unsigned FPU; 6250 unsigned CRC; 6251 unsigned Crypto; 6252 unsigned Unaligned; 6253 unsigned HasFullFP16; 6254 llvm::AArch64::ArchKind ArchKind; 6255 6256 static const Builtin::Info BuiltinInfo[]; 6257 6258 std::string ABI; 6259 6260 public: 6261 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6262 : TargetInfo(Triple), ABI("aapcs") { 6263 if (getTriple().getOS() == llvm::Triple::NetBSD || 6264 getTriple().getOS() == llvm::Triple::OpenBSD) { 6265 WCharType = SignedInt; 6266 6267 // NetBSD apparently prefers consistency across ARM targets to consistency 6268 // across 64-bit targets. 6269 Int64Type = SignedLongLong; 6270 IntMaxType = SignedLongLong; 6271 } else { 6272 WCharType = UnsignedInt; 6273 Int64Type = SignedLong; 6274 IntMaxType = SignedLong; 6275 } 6276 6277 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6278 MaxVectorAlign = 128; 6279 MaxAtomicInlineWidth = 128; 6280 MaxAtomicPromoteWidth = 128; 6281 6282 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 6283 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 6284 6285 // {} in inline assembly are neon specifiers, not assembly variant 6286 // specifiers. 6287 NoAsmVariants = true; 6288 6289 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 6290 // contributes to the alignment of the containing aggregate in the same way 6291 // a plain (non bit-field) member of that type would, without exception for 6292 // zero-sized or anonymous bit-fields." 6293 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 6294 UseZeroLengthBitfieldAlignment = true; 6295 6296 // AArch64 targets default to using the ARM C++ ABI. 6297 TheCXXABI.set(TargetCXXABI::GenericAArch64); 6298 6299 if (Triple.getOS() == llvm::Triple::Linux) 6300 this->MCountName = "\01_mcount"; 6301 else if (Triple.getOS() == llvm::Triple::UnknownOS) 6302 this->MCountName = Opts.EABIVersion == llvm::EABI::GNU ? "\01_mcount" : "mcount"; 6303 } 6304 6305 StringRef getABI() const override { return ABI; } 6306 bool setABI(const std::string &Name) override { 6307 if (Name != "aapcs" && Name != "darwinpcs") 6308 return false; 6309 6310 ABI = Name; 6311 return true; 6312 } 6313 6314 bool setCPU(const std::string &Name) override { 6315 return Name == "generic" || 6316 llvm::AArch64::parseCPUArch(Name) != 6317 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 6318 } 6319 6320 void getTargetDefinesARMV81A(const LangOptions &Opts, 6321 MacroBuilder &Builder) const { 6322 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 6323 } 6324 6325 void getTargetDefinesARMV82A(const LangOptions &Opts, 6326 MacroBuilder &Builder) const { 6327 // Also include the ARMv8.1 defines 6328 getTargetDefinesARMV81A(Opts, Builder); 6329 } 6330 6331 void getTargetDefines(const LangOptions &Opts, 6332 MacroBuilder &Builder) const override { 6333 // Target identification. 6334 Builder.defineMacro("__aarch64__"); 6335 // For bare-metal none-eabi. 6336 if (getTriple().getOS() == llvm::Triple::UnknownOS && 6337 (getTriple().getEnvironment() == llvm::Triple::EABI || 6338 getTriple().getEnvironment() == llvm::Triple::EABIHF)) 6339 Builder.defineMacro("__ELF__"); 6340 6341 // Target properties. 6342 Builder.defineMacro("_LP64"); 6343 Builder.defineMacro("__LP64__"); 6344 6345 // ACLE predefines. Many can only have one possible value on v8 AArch64. 6346 Builder.defineMacro("__ARM_ACLE", "200"); 6347 Builder.defineMacro("__ARM_ARCH", "8"); 6348 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 6349 6350 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 6351 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 6352 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 6353 6354 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 6355 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 6356 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 6357 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 6358 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 6359 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 6360 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 6361 6362 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 6363 6364 // 0xe implies support for half, single and double precision operations. 6365 Builder.defineMacro("__ARM_FP", "0xE"); 6366 6367 // PCS specifies this for SysV variants, which is all we support. Other ABIs 6368 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 6369 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 6370 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 6371 6372 if (Opts.UnsafeFPMath) 6373 Builder.defineMacro("__ARM_FP_FAST", "1"); 6374 6375 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 6376 6377 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 6378 Opts.ShortEnums ? "1" : "4"); 6379 6380 if (FPU == NeonMode) { 6381 Builder.defineMacro("__ARM_NEON", "1"); 6382 // 64-bit NEON supports half, single and double precision operations. 6383 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 6384 } 6385 6386 if (CRC) 6387 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 6388 6389 if (Crypto) 6390 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 6391 6392 if (Unaligned) 6393 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 6394 6395 switch(ArchKind) { 6396 default: break; 6397 case llvm::AArch64::ArchKind::AK_ARMV8_1A: 6398 getTargetDefinesARMV81A(Opts, Builder); 6399 break; 6400 case llvm::AArch64::ArchKind::AK_ARMV8_2A: 6401 getTargetDefinesARMV82A(Opts, Builder); 6402 break; 6403 } 6404 6405 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 6406 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6407 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6408 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6409 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6410 } 6411 6412 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6413 return llvm::makeArrayRef(BuiltinInfo, 6414 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 6415 } 6416 6417 bool hasFeature(StringRef Feature) const override { 6418 return Feature == "aarch64" || 6419 Feature == "arm64" || 6420 Feature == "arm" || 6421 (Feature == "neon" && FPU == NeonMode); 6422 } 6423 6424 bool handleTargetFeatures(std::vector<std::string> &Features, 6425 DiagnosticsEngine &Diags) override { 6426 FPU = FPUMode; 6427 CRC = 0; 6428 Crypto = 0; 6429 Unaligned = 1; 6430 HasFullFP16 = 0; 6431 ArchKind = llvm::AArch64::ArchKind::AK_ARMV8A; 6432 6433 for (const auto &Feature : Features) { 6434 if (Feature == "+neon") 6435 FPU = NeonMode; 6436 if (Feature == "+crc") 6437 CRC = 1; 6438 if (Feature == "+crypto") 6439 Crypto = 1; 6440 if (Feature == "+strict-align") 6441 Unaligned = 0; 6442 if (Feature == "+v8.1a") 6443 ArchKind = llvm::AArch64::ArchKind::AK_ARMV8_1A; 6444 if (Feature == "+v8.2a") 6445 ArchKind = llvm::AArch64::ArchKind::AK_ARMV8_2A; 6446 if (Feature == "+fullfp16") 6447 HasFullFP16 = 1; 6448 } 6449 6450 setDataLayout(); 6451 6452 return true; 6453 } 6454 6455 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6456 switch (CC) { 6457 case CC_C: 6458 case CC_Swift: 6459 case CC_PreserveMost: 6460 case CC_PreserveAll: 6461 case CC_OpenCLKernel: 6462 return CCCR_OK; 6463 default: 6464 return CCCR_Warning; 6465 } 6466 } 6467 6468 bool isCLZForZeroUndef() const override { return false; } 6469 6470 BuiltinVaListKind getBuiltinVaListKind() const override { 6471 return TargetInfo::AArch64ABIBuiltinVaList; 6472 } 6473 6474 ArrayRef<const char *> getGCCRegNames() const override; 6475 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6476 6477 bool validateAsmConstraint(const char *&Name, 6478 TargetInfo::ConstraintInfo &Info) const override { 6479 switch (*Name) { 6480 default: 6481 return false; 6482 case 'w': // Floating point and SIMD registers (V0-V31) 6483 Info.setAllowsRegister(); 6484 return true; 6485 case 'I': // Constant that can be used with an ADD instruction 6486 case 'J': // Constant that can be used with a SUB instruction 6487 case 'K': // Constant that can be used with a 32-bit logical instruction 6488 case 'L': // Constant that can be used with a 64-bit logical instruction 6489 case 'M': // Constant that can be used as a 32-bit MOV immediate 6490 case 'N': // Constant that can be used as a 64-bit MOV immediate 6491 case 'Y': // Floating point constant zero 6492 case 'Z': // Integer constant zero 6493 return true; 6494 case 'Q': // A memory reference with base register and no offset 6495 Info.setAllowsMemory(); 6496 return true; 6497 case 'S': // A symbolic address 6498 Info.setAllowsRegister(); 6499 return true; 6500 case 'U': 6501 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 6502 // Utf: A memory address suitable for ldp/stp in TF mode. 6503 // Usa: An absolute symbolic address. 6504 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 6505 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 6506 case 'z': // Zero register, wzr or xzr 6507 Info.setAllowsRegister(); 6508 return true; 6509 case 'x': // Floating point and SIMD registers (V0-V15) 6510 Info.setAllowsRegister(); 6511 return true; 6512 } 6513 return false; 6514 } 6515 6516 bool 6517 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 6518 std::string &SuggestedModifier) const override { 6519 // Strip off constraint modifiers. 6520 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 6521 Constraint = Constraint.substr(1); 6522 6523 switch (Constraint[0]) { 6524 default: 6525 return true; 6526 case 'z': 6527 case 'r': { 6528 switch (Modifier) { 6529 case 'x': 6530 case 'w': 6531 // For now assume that the person knows what they're 6532 // doing with the modifier. 6533 return true; 6534 default: 6535 // By default an 'r' constraint will be in the 'x' 6536 // registers. 6537 if (Size == 64) 6538 return true; 6539 6540 SuggestedModifier = "w"; 6541 return false; 6542 } 6543 } 6544 } 6545 } 6546 6547 const char *getClobbers() const override { return ""; } 6548 6549 int getEHDataRegisterNumber(unsigned RegNo) const override { 6550 if (RegNo == 0) 6551 return 0; 6552 if (RegNo == 1) 6553 return 1; 6554 return -1; 6555 } 6556 }; 6557 6558 const char *const AArch64TargetInfo::GCCRegNames[] = { 6559 // 32-bit Integer registers 6560 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 6561 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 6562 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 6563 6564 // 64-bit Integer registers 6565 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 6566 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 6567 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 6568 6569 // 32-bit floating point regsisters 6570 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 6571 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 6572 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6573 6574 // 64-bit floating point regsisters 6575 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 6576 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 6577 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6578 6579 // Vector registers 6580 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6581 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6582 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6583 }; 6584 6585 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6586 return llvm::makeArrayRef(GCCRegNames); 6587 } 6588 6589 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6590 { { "w31" }, "wsp" }, 6591 { { "x29" }, "fp" }, 6592 { { "x30" }, "lr" }, 6593 { { "x31" }, "sp" }, 6594 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6595 // don't want to substitute one of these for a different-sized one. 6596 }; 6597 6598 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6599 return llvm::makeArrayRef(GCCRegAliases); 6600 } 6601 6602 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6603 #define BUILTIN(ID, TYPE, ATTRS) \ 6604 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6605 #include "clang/Basic/BuiltinsNEON.def" 6606 6607 #define BUILTIN(ID, TYPE, ATTRS) \ 6608 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6609 #include "clang/Basic/BuiltinsAArch64.def" 6610 }; 6611 6612 class AArch64leTargetInfo : public AArch64TargetInfo { 6613 void setDataLayout() override { 6614 if (getTriple().isOSBinFormatMachO()) 6615 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6616 else 6617 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6618 } 6619 6620 public: 6621 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6622 : AArch64TargetInfo(Triple, Opts) { 6623 } 6624 void getTargetDefines(const LangOptions &Opts, 6625 MacroBuilder &Builder) const override { 6626 Builder.defineMacro("__AARCH64EL__"); 6627 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6628 } 6629 }; 6630 6631 class MicrosoftARM64TargetInfo 6632 : public WindowsTargetInfo<AArch64leTargetInfo> { 6633 const llvm::Triple Triple; 6634 6635 public: 6636 MicrosoftARM64TargetInfo(const llvm::Triple &Triple, 6637 const TargetOptions &Opts) 6638 : WindowsTargetInfo<AArch64leTargetInfo>(Triple, Opts), Triple(Triple) { 6639 WCharType = UnsignedShort; 6640 SizeType = UnsignedLongLong; 6641 TheCXXABI.set(TargetCXXABI::Microsoft); 6642 } 6643 6644 void setDataLayout() override { 6645 resetDataLayout("e-m:w-i64:64-i128:128-n32:64-S128"); 6646 } 6647 6648 void getVisualStudioDefines(const LangOptions &Opts, 6649 MacroBuilder &Builder) const { 6650 WindowsTargetInfo<AArch64leTargetInfo>::getVisualStudioDefines(Opts, 6651 Builder); 6652 Builder.defineMacro("_WIN32", "1"); 6653 Builder.defineMacro("_WIN64", "1"); 6654 Builder.defineMacro("_M_ARM64", "1"); 6655 } 6656 6657 void getTargetDefines(const LangOptions &Opts, 6658 MacroBuilder &Builder) const override { 6659 WindowsTargetInfo::getTargetDefines(Opts, Builder); 6660 getVisualStudioDefines(Opts, Builder); 6661 } 6662 6663 BuiltinVaListKind getBuiltinVaListKind() const override { 6664 return TargetInfo::CharPtrBuiltinVaList; 6665 } 6666 }; 6667 6668 class AArch64beTargetInfo : public AArch64TargetInfo { 6669 void setDataLayout() override { 6670 assert(!getTriple().isOSBinFormatMachO()); 6671 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6672 } 6673 6674 public: 6675 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6676 : AArch64TargetInfo(Triple, Opts) {} 6677 void getTargetDefines(const LangOptions &Opts, 6678 MacroBuilder &Builder) const override { 6679 Builder.defineMacro("__AARCH64EB__"); 6680 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6681 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6682 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6683 } 6684 }; 6685 6686 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6687 protected: 6688 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6689 MacroBuilder &Builder) const override { 6690 Builder.defineMacro("__AARCH64_SIMD__"); 6691 Builder.defineMacro("__ARM64_ARCH_8__"); 6692 Builder.defineMacro("__ARM_NEON__"); 6693 Builder.defineMacro("__LITTLE_ENDIAN__"); 6694 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6695 Builder.defineMacro("__arm64", "1"); 6696 Builder.defineMacro("__arm64__", "1"); 6697 6698 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6699 } 6700 6701 public: 6702 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6703 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6704 Int64Type = SignedLongLong; 6705 WCharType = SignedInt; 6706 UseSignedCharForObjCBool = false; 6707 6708 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6709 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 6710 6711 TheCXXABI.set(TargetCXXABI::iOS64); 6712 } 6713 6714 BuiltinVaListKind getBuiltinVaListKind() const override { 6715 return TargetInfo::CharPtrBuiltinVaList; 6716 } 6717 }; 6718 6719 // Hexagon abstract base class 6720 class HexagonTargetInfo : public TargetInfo { 6721 static const Builtin::Info BuiltinInfo[]; 6722 static const char * const GCCRegNames[]; 6723 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6724 std::string CPU; 6725 bool HasHVX, HasHVXDouble; 6726 bool UseLongCalls; 6727 6728 public: 6729 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6730 : TargetInfo(Triple) { 6731 // Specify the vector alignment explicitly. For v512x1, the calculated 6732 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6733 // the required minimum of 64 bytes. 6734 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6735 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6736 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6737 SizeType = UnsignedInt; 6738 PtrDiffType = SignedInt; 6739 IntPtrType = SignedInt; 6740 6741 // {} in inline assembly are packet specifiers, not assembly variant 6742 // specifiers. 6743 NoAsmVariants = true; 6744 6745 LargeArrayMinWidth = 64; 6746 LargeArrayAlign = 64; 6747 UseBitFieldTypeAlignment = true; 6748 ZeroLengthBitfieldBoundary = 32; 6749 HasHVX = HasHVXDouble = false; 6750 UseLongCalls = false; 6751 } 6752 6753 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6754 return llvm::makeArrayRef(BuiltinInfo, 6755 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6756 } 6757 6758 bool validateAsmConstraint(const char *&Name, 6759 TargetInfo::ConstraintInfo &Info) const override { 6760 switch (*Name) { 6761 case 'v': 6762 case 'q': 6763 if (HasHVX) { 6764 Info.setAllowsRegister(); 6765 return true; 6766 } 6767 break; 6768 case 's': 6769 // Relocatable constant. 6770 return true; 6771 } 6772 return false; 6773 } 6774 6775 void getTargetDefines(const LangOptions &Opts, 6776 MacroBuilder &Builder) const override; 6777 6778 bool isCLZForZeroUndef() const override { return false; } 6779 6780 bool hasFeature(StringRef Feature) const override { 6781 return llvm::StringSwitch<bool>(Feature) 6782 .Case("hexagon", true) 6783 .Case("hvx", HasHVX) 6784 .Case("hvx-double", HasHVXDouble) 6785 .Case("long-calls", UseLongCalls) 6786 .Default(false); 6787 } 6788 6789 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6790 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6791 const override; 6792 6793 bool handleTargetFeatures(std::vector<std::string> &Features, 6794 DiagnosticsEngine &Diags) override; 6795 6796 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6797 bool Enabled) const override; 6798 6799 BuiltinVaListKind getBuiltinVaListKind() const override { 6800 return TargetInfo::CharPtrBuiltinVaList; 6801 } 6802 ArrayRef<const char *> getGCCRegNames() const override; 6803 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6804 const char *getClobbers() const override { 6805 return ""; 6806 } 6807 6808 static const char *getHexagonCPUSuffix(StringRef Name) { 6809 return llvm::StringSwitch<const char*>(Name) 6810 .Case("hexagonv4", "4") 6811 .Case("hexagonv5", "5") 6812 .Case("hexagonv55", "55") 6813 .Case("hexagonv60", "60") 6814 .Case("hexagonv62", "62") 6815 .Default(nullptr); 6816 } 6817 6818 bool setCPU(const std::string &Name) override { 6819 if (!getHexagonCPUSuffix(Name)) 6820 return false; 6821 CPU = Name; 6822 return true; 6823 } 6824 6825 int getEHDataRegisterNumber(unsigned RegNo) const override { 6826 return RegNo < 2 ? RegNo : -1; 6827 } 6828 }; 6829 6830 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6831 MacroBuilder &Builder) const { 6832 Builder.defineMacro("__qdsp6__", "1"); 6833 Builder.defineMacro("__hexagon__", "1"); 6834 6835 if (CPU == "hexagonv4") { 6836 Builder.defineMacro("__HEXAGON_V4__"); 6837 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6838 if (Opts.HexagonQdsp6Compat) { 6839 Builder.defineMacro("__QDSP6_V4__"); 6840 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6841 } 6842 } else if (CPU == "hexagonv5") { 6843 Builder.defineMacro("__HEXAGON_V5__"); 6844 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6845 if(Opts.HexagonQdsp6Compat) { 6846 Builder.defineMacro("__QDSP6_V5__"); 6847 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6848 } 6849 } else if (CPU == "hexagonv55") { 6850 Builder.defineMacro("__HEXAGON_V55__"); 6851 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6852 Builder.defineMacro("__QDSP6_V55__"); 6853 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6854 } else if (CPU == "hexagonv60") { 6855 Builder.defineMacro("__HEXAGON_V60__"); 6856 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6857 Builder.defineMacro("__QDSP6_V60__"); 6858 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6859 } else if (CPU == "hexagonv62") { 6860 Builder.defineMacro("__HEXAGON_V62__"); 6861 Builder.defineMacro("__HEXAGON_ARCH__", "62"); 6862 } 6863 6864 if (hasFeature("hvx")) { 6865 Builder.defineMacro("__HVX__"); 6866 if (hasFeature("hvx-double")) 6867 Builder.defineMacro("__HVXDBL__"); 6868 } 6869 } 6870 6871 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6872 DiagnosticsEngine &Diags, StringRef CPU, 6873 const std::vector<std::string> &FeaturesVec) const { 6874 // Default for v60: -hvx, -hvx-double. 6875 Features["hvx"] = false; 6876 Features["hvx-double"] = false; 6877 Features["long-calls"] = false; 6878 6879 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6880 } 6881 6882 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6883 DiagnosticsEngine &Diags) { 6884 for (auto &F : Features) { 6885 if (F == "+hvx") 6886 HasHVX = true; 6887 else if (F == "-hvx") 6888 HasHVX = HasHVXDouble = false; 6889 else if (F == "+hvx-double") 6890 HasHVX = HasHVXDouble = true; 6891 else if (F == "-hvx-double") 6892 HasHVXDouble = false; 6893 6894 if (F == "+long-calls") 6895 UseLongCalls = true; 6896 else if (F == "-long-calls") 6897 UseLongCalls = false; 6898 } 6899 return true; 6900 } 6901 6902 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 6903 StringRef Name, bool Enabled) const { 6904 if (Enabled) { 6905 if (Name == "hvx-double") 6906 Features["hvx"] = true; 6907 } else { 6908 if (Name == "hvx") 6909 Features["hvx-double"] = false; 6910 } 6911 Features[Name] = Enabled; 6912 } 6913 6914 const char *const HexagonTargetInfo::GCCRegNames[] = { 6915 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6916 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6917 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6918 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6919 "p0", "p1", "p2", "p3", 6920 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6921 }; 6922 6923 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6924 return llvm::makeArrayRef(GCCRegNames); 6925 } 6926 6927 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6928 { { "sp" }, "r29" }, 6929 { { "fp" }, "r30" }, 6930 { { "lr" }, "r31" }, 6931 }; 6932 6933 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6934 return llvm::makeArrayRef(GCCRegAliases); 6935 } 6936 6937 6938 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6939 #define BUILTIN(ID, TYPE, ATTRS) \ 6940 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6941 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6942 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6943 #include "clang/Basic/BuiltinsHexagon.def" 6944 }; 6945 6946 class LanaiTargetInfo : public TargetInfo { 6947 // Class for Lanai (32-bit). 6948 // The CPU profiles supported by the Lanai backend 6949 enum CPUKind { 6950 CK_NONE, 6951 CK_V11, 6952 } CPU; 6953 6954 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6955 static const char *const GCCRegNames[]; 6956 6957 public: 6958 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6959 : TargetInfo(Triple) { 6960 // Description string has to be kept in sync with backend. 6961 resetDataLayout("E" // Big endian 6962 "-m:e" // ELF name manging 6963 "-p:32:32" // 32 bit pointers, 32 bit aligned 6964 "-i64:64" // 64 bit integers, 64 bit aligned 6965 "-a:0:32" // 32 bit alignment of objects of aggregate type 6966 "-n32" // 32 bit native integer width 6967 "-S64" // 64 bit natural stack alignment 6968 ); 6969 6970 // Setting RegParmMax equal to what mregparm was set to in the old 6971 // toolchain 6972 RegParmMax = 4; 6973 6974 // Set the default CPU to V11 6975 CPU = CK_V11; 6976 6977 // Temporary approach to make everything at least word-aligned and allow for 6978 // safely casting between pointers with different alignment requirements. 6979 // TODO: Remove this when there are no more cast align warnings on the 6980 // firmware. 6981 MinGlobalAlign = 32; 6982 } 6983 6984 void getTargetDefines(const LangOptions &Opts, 6985 MacroBuilder &Builder) const override { 6986 // Define __lanai__ when building for target lanai. 6987 Builder.defineMacro("__lanai__"); 6988 6989 // Set define for the CPU specified. 6990 switch (CPU) { 6991 case CK_V11: 6992 Builder.defineMacro("__LANAI_V11__"); 6993 break; 6994 case CK_NONE: 6995 llvm_unreachable("Unhandled target CPU"); 6996 } 6997 } 6998 6999 bool setCPU(const std::string &Name) override { 7000 CPU = llvm::StringSwitch<CPUKind>(Name) 7001 .Case("v11", CK_V11) 7002 .Default(CK_NONE); 7003 7004 return CPU != CK_NONE; 7005 } 7006 7007 bool hasFeature(StringRef Feature) const override { 7008 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 7009 } 7010 7011 ArrayRef<const char *> getGCCRegNames() const override; 7012 7013 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7014 7015 BuiltinVaListKind getBuiltinVaListKind() const override { 7016 return TargetInfo::VoidPtrBuiltinVaList; 7017 } 7018 7019 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7020 7021 bool validateAsmConstraint(const char *&Name, 7022 TargetInfo::ConstraintInfo &info) const override { 7023 return false; 7024 } 7025 7026 const char *getClobbers() const override { return ""; } 7027 }; 7028 7029 const char *const LanaiTargetInfo::GCCRegNames[] = { 7030 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 7031 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 7032 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 7033 7034 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 7035 return llvm::makeArrayRef(GCCRegNames); 7036 } 7037 7038 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 7039 {{"pc"}, "r2"}, 7040 {{"sp"}, "r4"}, 7041 {{"fp"}, "r5"}, 7042 {{"rv"}, "r8"}, 7043 {{"rr1"}, "r10"}, 7044 {{"rr2"}, "r11"}, 7045 {{"rca"}, "r15"}, 7046 }; 7047 7048 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 7049 return llvm::makeArrayRef(GCCRegAliases); 7050 } 7051 7052 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 7053 class SparcTargetInfo : public TargetInfo { 7054 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 7055 static const char * const GCCRegNames[]; 7056 bool SoftFloat; 7057 public: 7058 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7059 : TargetInfo(Triple), SoftFloat(false) {} 7060 7061 int getEHDataRegisterNumber(unsigned RegNo) const override { 7062 if (RegNo == 0) return 24; 7063 if (RegNo == 1) return 25; 7064 return -1; 7065 } 7066 7067 bool handleTargetFeatures(std::vector<std::string> &Features, 7068 DiagnosticsEngine &Diags) override { 7069 // Check if software floating point is enabled 7070 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 7071 if (Feature != Features.end()) { 7072 SoftFloat = true; 7073 } 7074 return true; 7075 } 7076 void getTargetDefines(const LangOptions &Opts, 7077 MacroBuilder &Builder) const override { 7078 DefineStd(Builder, "sparc", Opts); 7079 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7080 7081 if (SoftFloat) 7082 Builder.defineMacro("SOFT_FLOAT", "1"); 7083 } 7084 7085 bool hasFeature(StringRef Feature) const override { 7086 return llvm::StringSwitch<bool>(Feature) 7087 .Case("softfloat", SoftFloat) 7088 .Case("sparc", true) 7089 .Default(false); 7090 } 7091 7092 bool hasSjLjLowering() const override { 7093 return true; 7094 } 7095 7096 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7097 // FIXME: Implement! 7098 return None; 7099 } 7100 BuiltinVaListKind getBuiltinVaListKind() const override { 7101 return TargetInfo::VoidPtrBuiltinVaList; 7102 } 7103 ArrayRef<const char *> getGCCRegNames() const override; 7104 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7105 bool validateAsmConstraint(const char *&Name, 7106 TargetInfo::ConstraintInfo &info) const override { 7107 // FIXME: Implement! 7108 switch (*Name) { 7109 case 'I': // Signed 13-bit constant 7110 case 'J': // Zero 7111 case 'K': // 32-bit constant with the low 12 bits clear 7112 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 7113 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 7114 case 'N': // Same as 'K' but zext (required for SIMode) 7115 case 'O': // The constant 4096 7116 return true; 7117 7118 case 'f': 7119 case 'e': 7120 info.setAllowsRegister(); 7121 return true; 7122 } 7123 return false; 7124 } 7125 const char *getClobbers() const override { 7126 // FIXME: Implement! 7127 return ""; 7128 } 7129 7130 // No Sparc V7 for now, the backend doesn't support it anyway. 7131 enum CPUKind { 7132 CK_GENERIC, 7133 CK_V8, 7134 CK_SUPERSPARC, 7135 CK_SPARCLITE, 7136 CK_F934, 7137 CK_HYPERSPARC, 7138 CK_SPARCLITE86X, 7139 CK_SPARCLET, 7140 CK_TSC701, 7141 CK_V9, 7142 CK_ULTRASPARC, 7143 CK_ULTRASPARC3, 7144 CK_NIAGARA, 7145 CK_NIAGARA2, 7146 CK_NIAGARA3, 7147 CK_NIAGARA4, 7148 CK_MYRIAD2100, 7149 CK_MYRIAD2150, 7150 CK_MYRIAD2450, 7151 CK_LEON2, 7152 CK_LEON2_AT697E, 7153 CK_LEON2_AT697F, 7154 CK_LEON3, 7155 CK_LEON3_UT699, 7156 CK_LEON3_GR712RC, 7157 CK_LEON4, 7158 CK_LEON4_GR740 7159 } CPU = CK_GENERIC; 7160 7161 enum CPUGeneration { 7162 CG_V8, 7163 CG_V9, 7164 }; 7165 7166 CPUGeneration getCPUGeneration(CPUKind Kind) const { 7167 switch (Kind) { 7168 case CK_GENERIC: 7169 case CK_V8: 7170 case CK_SUPERSPARC: 7171 case CK_SPARCLITE: 7172 case CK_F934: 7173 case CK_HYPERSPARC: 7174 case CK_SPARCLITE86X: 7175 case CK_SPARCLET: 7176 case CK_TSC701: 7177 case CK_MYRIAD2100: 7178 case CK_MYRIAD2150: 7179 case CK_MYRIAD2450: 7180 case CK_LEON2: 7181 case CK_LEON2_AT697E: 7182 case CK_LEON2_AT697F: 7183 case CK_LEON3: 7184 case CK_LEON3_UT699: 7185 case CK_LEON3_GR712RC: 7186 case CK_LEON4: 7187 case CK_LEON4_GR740: 7188 return CG_V8; 7189 case CK_V9: 7190 case CK_ULTRASPARC: 7191 case CK_ULTRASPARC3: 7192 case CK_NIAGARA: 7193 case CK_NIAGARA2: 7194 case CK_NIAGARA3: 7195 case CK_NIAGARA4: 7196 return CG_V9; 7197 } 7198 llvm_unreachable("Unexpected CPU kind"); 7199 } 7200 7201 CPUKind getCPUKind(StringRef Name) const { 7202 return llvm::StringSwitch<CPUKind>(Name) 7203 .Case("v8", CK_V8) 7204 .Case("supersparc", CK_SUPERSPARC) 7205 .Case("sparclite", CK_SPARCLITE) 7206 .Case("f934", CK_F934) 7207 .Case("hypersparc", CK_HYPERSPARC) 7208 .Case("sparclite86x", CK_SPARCLITE86X) 7209 .Case("sparclet", CK_SPARCLET) 7210 .Case("tsc701", CK_TSC701) 7211 .Case("v9", CK_V9) 7212 .Case("ultrasparc", CK_ULTRASPARC) 7213 .Case("ultrasparc3", CK_ULTRASPARC3) 7214 .Case("niagara", CK_NIAGARA) 7215 .Case("niagara2", CK_NIAGARA2) 7216 .Case("niagara3", CK_NIAGARA3) 7217 .Case("niagara4", CK_NIAGARA4) 7218 .Case("ma2100", CK_MYRIAD2100) 7219 .Case("ma2150", CK_MYRIAD2150) 7220 .Case("ma2450", CK_MYRIAD2450) 7221 // FIXME: the myriad2[.n] spellings are obsolete, 7222 // but a grace period is needed to allow updating dependent builds. 7223 .Case("myriad2", CK_MYRIAD2100) 7224 .Case("myriad2.1", CK_MYRIAD2100) 7225 .Case("myriad2.2", CK_MYRIAD2150) 7226 .Case("leon2", CK_LEON2) 7227 .Case("at697e", CK_LEON2_AT697E) 7228 .Case("at697f", CK_LEON2_AT697F) 7229 .Case("leon3", CK_LEON3) 7230 .Case("ut699", CK_LEON3_UT699) 7231 .Case("gr712rc", CK_LEON3_GR712RC) 7232 .Case("leon4", CK_LEON4) 7233 .Case("gr740", CK_LEON4_GR740) 7234 .Default(CK_GENERIC); 7235 } 7236 7237 bool setCPU(const std::string &Name) override { 7238 CPU = getCPUKind(Name); 7239 return CPU != CK_GENERIC; 7240 } 7241 }; 7242 7243 const char * const SparcTargetInfo::GCCRegNames[] = { 7244 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7245 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7246 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 7247 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 7248 }; 7249 7250 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 7251 return llvm::makeArrayRef(GCCRegNames); 7252 } 7253 7254 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 7255 { { "g0" }, "r0" }, 7256 { { "g1" }, "r1" }, 7257 { { "g2" }, "r2" }, 7258 { { "g3" }, "r3" }, 7259 { { "g4" }, "r4" }, 7260 { { "g5" }, "r5" }, 7261 { { "g6" }, "r6" }, 7262 { { "g7" }, "r7" }, 7263 { { "o0" }, "r8" }, 7264 { { "o1" }, "r9" }, 7265 { { "o2" }, "r10" }, 7266 { { "o3" }, "r11" }, 7267 { { "o4" }, "r12" }, 7268 { { "o5" }, "r13" }, 7269 { { "o6", "sp" }, "r14" }, 7270 { { "o7" }, "r15" }, 7271 { { "l0" }, "r16" }, 7272 { { "l1" }, "r17" }, 7273 { { "l2" }, "r18" }, 7274 { { "l3" }, "r19" }, 7275 { { "l4" }, "r20" }, 7276 { { "l5" }, "r21" }, 7277 { { "l6" }, "r22" }, 7278 { { "l7" }, "r23" }, 7279 { { "i0" }, "r24" }, 7280 { { "i1" }, "r25" }, 7281 { { "i2" }, "r26" }, 7282 { { "i3" }, "r27" }, 7283 { { "i4" }, "r28" }, 7284 { { "i5" }, "r29" }, 7285 { { "i6", "fp" }, "r30" }, 7286 { { "i7" }, "r31" }, 7287 }; 7288 7289 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 7290 return llvm::makeArrayRef(GCCRegAliases); 7291 } 7292 7293 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 7294 class SparcV8TargetInfo : public SparcTargetInfo { 7295 public: 7296 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7297 : SparcTargetInfo(Triple, Opts) { 7298 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7299 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 7300 switch (getTriple().getOS()) { 7301 default: 7302 SizeType = UnsignedInt; 7303 IntPtrType = SignedInt; 7304 PtrDiffType = SignedInt; 7305 break; 7306 case llvm::Triple::NetBSD: 7307 case llvm::Triple::OpenBSD: 7308 SizeType = UnsignedLong; 7309 IntPtrType = SignedLong; 7310 PtrDiffType = SignedLong; 7311 break; 7312 } 7313 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops 7314 // on up to 64 bits. 7315 MaxAtomicPromoteWidth = 64; 7316 MaxAtomicInlineWidth = 32; 7317 } 7318 7319 void getTargetDefines(const LangOptions &Opts, 7320 MacroBuilder &Builder) const override { 7321 SparcTargetInfo::getTargetDefines(Opts, Builder); 7322 switch (getCPUGeneration(CPU)) { 7323 case CG_V8: 7324 Builder.defineMacro("__sparcv8"); 7325 if (getTriple().getOS() != llvm::Triple::Solaris) 7326 Builder.defineMacro("__sparcv8__"); 7327 break; 7328 case CG_V9: 7329 Builder.defineMacro("__sparcv9"); 7330 if (getTriple().getOS() != llvm::Triple::Solaris) { 7331 Builder.defineMacro("__sparcv9__"); 7332 Builder.defineMacro("__sparc_v9__"); 7333 } 7334 break; 7335 } 7336 if (getTriple().getVendor() == llvm::Triple::Myriad) { 7337 std::string MyriadArchValue, Myriad2Value; 7338 Builder.defineMacro("__sparc_v8__"); 7339 Builder.defineMacro("__leon__"); 7340 switch (CPU) { 7341 case CK_MYRIAD2150: 7342 MyriadArchValue = "__ma2150"; 7343 Myriad2Value = "2"; 7344 break; 7345 case CK_MYRIAD2450: 7346 MyriadArchValue = "__ma2450"; 7347 Myriad2Value = "2"; 7348 break; 7349 default: 7350 MyriadArchValue = "__ma2100"; 7351 Myriad2Value = "1"; 7352 break; 7353 } 7354 Builder.defineMacro(MyriadArchValue, "1"); 7355 Builder.defineMacro(MyriadArchValue+"__", "1"); 7356 Builder.defineMacro("__myriad2__", Myriad2Value); 7357 Builder.defineMacro("__myriad2", Myriad2Value); 7358 } 7359 } 7360 7361 bool hasSjLjLowering() const override { 7362 return true; 7363 } 7364 }; 7365 7366 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 7367 class SparcV8elTargetInfo : public SparcV8TargetInfo { 7368 public: 7369 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7370 : SparcV8TargetInfo(Triple, Opts) { 7371 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7372 } 7373 }; 7374 7375 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 7376 class SparcV9TargetInfo : public SparcTargetInfo { 7377 public: 7378 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7379 : SparcTargetInfo(Triple, Opts) { 7380 // FIXME: Support Sparc quad-precision long double? 7381 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 7382 // This is an LP64 platform. 7383 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7384 7385 // OpenBSD uses long long for int64_t and intmax_t. 7386 if (getTriple().getOS() == llvm::Triple::OpenBSD) 7387 IntMaxType = SignedLongLong; 7388 else 7389 IntMaxType = SignedLong; 7390 Int64Type = IntMaxType; 7391 7392 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 7393 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 7394 LongDoubleWidth = 128; 7395 LongDoubleAlign = 128; 7396 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7397 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7398 } 7399 7400 void getTargetDefines(const LangOptions &Opts, 7401 MacroBuilder &Builder) const override { 7402 SparcTargetInfo::getTargetDefines(Opts, Builder); 7403 Builder.defineMacro("__sparcv9"); 7404 Builder.defineMacro("__arch64__"); 7405 // Solaris doesn't need these variants, but the BSDs do. 7406 if (getTriple().getOS() != llvm::Triple::Solaris) { 7407 Builder.defineMacro("__sparc64__"); 7408 Builder.defineMacro("__sparc_v9__"); 7409 Builder.defineMacro("__sparcv9__"); 7410 } 7411 } 7412 7413 bool setCPU(const std::string &Name) override { 7414 if (!SparcTargetInfo::setCPU(Name)) 7415 return false; 7416 return getCPUGeneration(CPU) == CG_V9; 7417 } 7418 }; 7419 7420 class SystemZTargetInfo : public TargetInfo { 7421 static const Builtin::Info BuiltinInfo[]; 7422 static const char *const GCCRegNames[]; 7423 std::string CPU; 7424 int ISARevision; 7425 bool HasTransactionalExecution; 7426 bool HasVector; 7427 7428 public: 7429 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7430 : TargetInfo(Triple), CPU("z10"), ISARevision(8), 7431 HasTransactionalExecution(false), HasVector(false) { 7432 IntMaxType = SignedLong; 7433 Int64Type = SignedLong; 7434 TLSSupported = true; 7435 IntWidth = IntAlign = 32; 7436 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 7437 PointerWidth = PointerAlign = 64; 7438 LongDoubleWidth = 128; 7439 LongDoubleAlign = 64; 7440 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7441 DefaultAlignForAttributeAligned = 64; 7442 MinGlobalAlign = 16; 7443 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 7444 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7445 } 7446 void getTargetDefines(const LangOptions &Opts, 7447 MacroBuilder &Builder) const override { 7448 Builder.defineMacro("__s390__"); 7449 Builder.defineMacro("__s390x__"); 7450 Builder.defineMacro("__zarch__"); 7451 Builder.defineMacro("__LONG_DOUBLE_128__"); 7452 7453 Builder.defineMacro("__ARCH__", Twine(ISARevision)); 7454 7455 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7456 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7457 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7458 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7459 7460 if (HasTransactionalExecution) 7461 Builder.defineMacro("__HTM__"); 7462 if (HasVector) 7463 Builder.defineMacro("__VX__"); 7464 if (Opts.ZVector) 7465 Builder.defineMacro("__VEC__", "10301"); 7466 } 7467 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7468 return llvm::makeArrayRef(BuiltinInfo, 7469 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 7470 } 7471 7472 ArrayRef<const char *> getGCCRegNames() const override; 7473 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7474 // No aliases. 7475 return None; 7476 } 7477 bool validateAsmConstraint(const char *&Name, 7478 TargetInfo::ConstraintInfo &info) const override; 7479 const char *getClobbers() const override { 7480 // FIXME: Is this really right? 7481 return ""; 7482 } 7483 BuiltinVaListKind getBuiltinVaListKind() const override { 7484 return TargetInfo::SystemZBuiltinVaList; 7485 } 7486 int getISARevision(const StringRef &Name) const { 7487 return llvm::StringSwitch<int>(Name) 7488 .Cases("arch8", "z10", 8) 7489 .Cases("arch9", "z196", 9) 7490 .Cases("arch10", "zEC12", 10) 7491 .Cases("arch11", "z13", 11) 7492 .Default(-1); 7493 } 7494 bool setCPU(const std::string &Name) override { 7495 CPU = Name; 7496 ISARevision = getISARevision(CPU); 7497 return ISARevision != -1; 7498 } 7499 bool 7500 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7501 StringRef CPU, 7502 const std::vector<std::string> &FeaturesVec) const override { 7503 int ISARevision = getISARevision(CPU); 7504 if (ISARevision >= 10) 7505 Features["transactional-execution"] = true; 7506 if (ISARevision >= 11) 7507 Features["vector"] = true; 7508 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7509 } 7510 7511 bool handleTargetFeatures(std::vector<std::string> &Features, 7512 DiagnosticsEngine &Diags) override { 7513 HasTransactionalExecution = false; 7514 HasVector = false; 7515 for (const auto &Feature : Features) { 7516 if (Feature == "+transactional-execution") 7517 HasTransactionalExecution = true; 7518 else if (Feature == "+vector") 7519 HasVector = true; 7520 } 7521 // If we use the vector ABI, vector types are 64-bit aligned. 7522 if (HasVector) { 7523 MaxVectorAlign = 64; 7524 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 7525 "-v128:64-a:8:16-n32:64"); 7526 } 7527 return true; 7528 } 7529 7530 bool hasFeature(StringRef Feature) const override { 7531 return llvm::StringSwitch<bool>(Feature) 7532 .Case("systemz", true) 7533 .Case("arch8", ISARevision >= 8) 7534 .Case("arch9", ISARevision >= 9) 7535 .Case("arch10", ISARevision >= 10) 7536 .Case("arch11", ISARevision >= 11) 7537 .Case("htm", HasTransactionalExecution) 7538 .Case("vx", HasVector) 7539 .Default(false); 7540 } 7541 7542 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7543 switch (CC) { 7544 case CC_C: 7545 case CC_Swift: 7546 case CC_OpenCLKernel: 7547 return CCCR_OK; 7548 default: 7549 return CCCR_Warning; 7550 } 7551 } 7552 7553 StringRef getABI() const override { 7554 if (HasVector) 7555 return "vector"; 7556 return ""; 7557 } 7558 7559 bool useFloat128ManglingForLongDouble() const override { 7560 return true; 7561 } 7562 }; 7563 7564 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 7565 #define BUILTIN(ID, TYPE, ATTRS) \ 7566 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7567 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7568 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 7569 #include "clang/Basic/BuiltinsSystemZ.def" 7570 }; 7571 7572 const char *const SystemZTargetInfo::GCCRegNames[] = { 7573 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7574 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7575 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 7576 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 7577 }; 7578 7579 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 7580 return llvm::makeArrayRef(GCCRegNames); 7581 } 7582 7583 bool SystemZTargetInfo:: 7584 validateAsmConstraint(const char *&Name, 7585 TargetInfo::ConstraintInfo &Info) const { 7586 switch (*Name) { 7587 default: 7588 return false; 7589 7590 case 'a': // Address register 7591 case 'd': // Data register (equivalent to 'r') 7592 case 'f': // Floating-point register 7593 Info.setAllowsRegister(); 7594 return true; 7595 7596 case 'I': // Unsigned 8-bit constant 7597 case 'J': // Unsigned 12-bit constant 7598 case 'K': // Signed 16-bit constant 7599 case 'L': // Signed 20-bit displacement (on all targets we support) 7600 case 'M': // 0x7fffffff 7601 return true; 7602 7603 case 'Q': // Memory with base and unsigned 12-bit displacement 7604 case 'R': // Likewise, plus an index 7605 case 'S': // Memory with base and signed 20-bit displacement 7606 case 'T': // Likewise, plus an index 7607 Info.setAllowsMemory(); 7608 return true; 7609 } 7610 } 7611 7612 class MSP430TargetInfo : public TargetInfo { 7613 static const char *const GCCRegNames[]; 7614 7615 public: 7616 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7617 : TargetInfo(Triple) { 7618 TLSSupported = false; 7619 IntWidth = 16; 7620 IntAlign = 16; 7621 LongWidth = 32; 7622 LongLongWidth = 64; 7623 LongAlign = LongLongAlign = 16; 7624 PointerWidth = 16; 7625 PointerAlign = 16; 7626 SuitableAlign = 16; 7627 SizeType = UnsignedInt; 7628 IntMaxType = SignedLongLong; 7629 IntPtrType = SignedInt; 7630 PtrDiffType = SignedInt; 7631 SigAtomicType = SignedLong; 7632 resetDataLayout("e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16"); 7633 } 7634 void getTargetDefines(const LangOptions &Opts, 7635 MacroBuilder &Builder) const override { 7636 Builder.defineMacro("MSP430"); 7637 Builder.defineMacro("__MSP430__"); 7638 // FIXME: defines for different 'flavours' of MCU 7639 } 7640 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7641 // FIXME: Implement. 7642 return None; 7643 } 7644 bool hasFeature(StringRef Feature) const override { 7645 return Feature == "msp430"; 7646 } 7647 ArrayRef<const char *> getGCCRegNames() const override; 7648 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7649 // No aliases. 7650 return None; 7651 } 7652 bool validateAsmConstraint(const char *&Name, 7653 TargetInfo::ConstraintInfo &info) const override { 7654 // FIXME: implement 7655 switch (*Name) { 7656 case 'K': // the constant 1 7657 case 'L': // constant -1^20 .. 1^19 7658 case 'M': // constant 1-4: 7659 return true; 7660 } 7661 // No target constraints for now. 7662 return false; 7663 } 7664 const char *getClobbers() const override { 7665 // FIXME: Is this really right? 7666 return ""; 7667 } 7668 BuiltinVaListKind getBuiltinVaListKind() const override { 7669 // FIXME: implement 7670 return TargetInfo::CharPtrBuiltinVaList; 7671 } 7672 }; 7673 7674 const char *const MSP430TargetInfo::GCCRegNames[] = { 7675 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7676 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7677 7678 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7679 return llvm::makeArrayRef(GCCRegNames); 7680 } 7681 7682 // LLVM and Clang cannot be used directly to output native binaries for 7683 // target, but is used to compile C code to llvm bitcode with correct 7684 // type and alignment information. 7685 // 7686 // TCE uses the llvm bitcode as input and uses it for generating customized 7687 // target processor and program binary. TCE co-design environment is 7688 // publicly available in http://tce.cs.tut.fi 7689 7690 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7691 0, // Default 7692 3, // opencl_global 7693 4, // opencl_local 7694 5, // opencl_constant 7695 // FIXME: generic has to be added to the target 7696 0, // opencl_generic 7697 0, // cuda_device 7698 0, // cuda_constant 7699 0 // cuda_shared 7700 }; 7701 7702 class TCETargetInfo : public TargetInfo { 7703 public: 7704 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7705 : TargetInfo(Triple) { 7706 TLSSupported = false; 7707 IntWidth = 32; 7708 LongWidth = LongLongWidth = 32; 7709 PointerWidth = 32; 7710 IntAlign = 32; 7711 LongAlign = LongLongAlign = 32; 7712 PointerAlign = 32; 7713 SuitableAlign = 32; 7714 SizeType = UnsignedInt; 7715 IntMaxType = SignedLong; 7716 IntPtrType = SignedInt; 7717 PtrDiffType = SignedInt; 7718 FloatWidth = 32; 7719 FloatAlign = 32; 7720 DoubleWidth = 32; 7721 DoubleAlign = 32; 7722 LongDoubleWidth = 32; 7723 LongDoubleAlign = 32; 7724 FloatFormat = &llvm::APFloat::IEEEsingle(); 7725 DoubleFormat = &llvm::APFloat::IEEEsingle(); 7726 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 7727 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-" 7728 "i16:16:32-i32:32:32-i64:32:32-" 7729 "f32:32:32-f64:32:32-v64:32:32-" 7730 "v128:32:32-v256:32:32-v512:32:32-" 7731 "v1024:32:32-a0:0:32-n32"); 7732 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7733 UseAddrSpaceMapMangling = true; 7734 } 7735 7736 void getTargetDefines(const LangOptions &Opts, 7737 MacroBuilder &Builder) const override { 7738 DefineStd(Builder, "tce", Opts); 7739 Builder.defineMacro("__TCE__"); 7740 Builder.defineMacro("__TCE_V1__"); 7741 } 7742 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7743 7744 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7745 const char *getClobbers() const override { return ""; } 7746 BuiltinVaListKind getBuiltinVaListKind() const override { 7747 return TargetInfo::VoidPtrBuiltinVaList; 7748 } 7749 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7750 bool validateAsmConstraint(const char *&Name, 7751 TargetInfo::ConstraintInfo &info) const override { 7752 return true; 7753 } 7754 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7755 return None; 7756 } 7757 }; 7758 7759 class TCELETargetInfo : public TCETargetInfo { 7760 public: 7761 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7762 : TCETargetInfo(Triple, Opts) { 7763 BigEndian = false; 7764 7765 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-" 7766 "i16:16:32-i32:32:32-i64:32:32-" 7767 "f32:32:32-f64:32:32-v64:32:32-" 7768 "v128:32:32-v256:32:32-v512:32:32-" 7769 "v1024:32:32-a0:0:32-n32"); 7770 7771 } 7772 7773 virtual void getTargetDefines(const LangOptions &Opts, 7774 MacroBuilder &Builder) const { 7775 DefineStd(Builder, "tcele", Opts); 7776 Builder.defineMacro("__TCE__"); 7777 Builder.defineMacro("__TCE_V1__"); 7778 Builder.defineMacro("__TCELE__"); 7779 Builder.defineMacro("__TCELE_V1__"); 7780 } 7781 7782 }; 7783 7784 class BPFTargetInfo : public TargetInfo { 7785 public: 7786 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7787 : TargetInfo(Triple) { 7788 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7789 SizeType = UnsignedLong; 7790 PtrDiffType = SignedLong; 7791 IntPtrType = SignedLong; 7792 IntMaxType = SignedLong; 7793 Int64Type = SignedLong; 7794 RegParmMax = 5; 7795 if (Triple.getArch() == llvm::Triple::bpfeb) { 7796 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7797 } else { 7798 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7799 } 7800 MaxAtomicPromoteWidth = 64; 7801 MaxAtomicInlineWidth = 64; 7802 TLSSupported = false; 7803 } 7804 void getTargetDefines(const LangOptions &Opts, 7805 MacroBuilder &Builder) const override { 7806 DefineStd(Builder, "bpf", Opts); 7807 Builder.defineMacro("__BPF__"); 7808 } 7809 bool hasFeature(StringRef Feature) const override { 7810 return Feature == "bpf"; 7811 } 7812 7813 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7814 const char *getClobbers() const override { 7815 return ""; 7816 } 7817 BuiltinVaListKind getBuiltinVaListKind() const override { 7818 return TargetInfo::VoidPtrBuiltinVaList; 7819 } 7820 ArrayRef<const char *> getGCCRegNames() const override { 7821 return None; 7822 } 7823 bool validateAsmConstraint(const char *&Name, 7824 TargetInfo::ConstraintInfo &info) const override { 7825 return true; 7826 } 7827 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7828 return None; 7829 } 7830 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7831 switch (CC) { 7832 default: 7833 return CCCR_Warning; 7834 case CC_C: 7835 case CC_OpenCLKernel: 7836 return CCCR_OK; 7837 } 7838 } 7839 }; 7840 7841 class Nios2TargetInfo : public TargetInfo { 7842 void setDataLayout() { 7843 if (BigEndian) 7844 resetDataLayout("E-p:32:32:32-i8:8:32-i16:16:32-n32"); 7845 else 7846 resetDataLayout("e-p:32:32:32-i8:8:32-i16:16:32-n32"); 7847 } 7848 7849 static const Builtin::Info BuiltinInfo[]; 7850 std::string CPU; 7851 std::string ABI; 7852 7853 public: 7854 Nios2TargetInfo(const llvm::Triple &triple, const TargetOptions &opts) 7855 : TargetInfo(triple), CPU(opts.CPU), ABI(opts.ABI) { 7856 SizeType = UnsignedInt; 7857 PtrDiffType = SignedInt; 7858 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7859 setDataLayout(); 7860 } 7861 7862 StringRef getABI() const override { return ABI; } 7863 bool setABI(const std::string &Name) override { 7864 if (Name == "o32" || Name == "eabi") { 7865 ABI = Name; 7866 return true; 7867 } 7868 return false; 7869 } 7870 7871 bool setCPU(const std::string &Name) override { 7872 if (Name == "nios2r1" || Name == "nios2r2") { 7873 CPU = Name; 7874 return true; 7875 } 7876 return false; 7877 } 7878 7879 void getTargetDefines(const LangOptions &Opts, 7880 MacroBuilder &Builder) const override { 7881 DefineStd(Builder, "nios2", Opts); 7882 DefineStd(Builder, "NIOS2", Opts); 7883 7884 Builder.defineMacro("__nios2"); 7885 Builder.defineMacro("__NIOS2"); 7886 Builder.defineMacro("__nios2__"); 7887 Builder.defineMacro("__NIOS2__"); 7888 } 7889 7890 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7891 return llvm::makeArrayRef(BuiltinInfo, clang::Nios2::LastTSBuiltin - 7892 Builtin::FirstTSBuiltin); 7893 } 7894 7895 bool isFeatureSupportedByCPU(StringRef Feature, StringRef CPU) const { 7896 const bool isR2 = CPU == "nios2r2"; 7897 return llvm::StringSwitch<bool>(Feature) 7898 .Case("nios2r2mandatory", isR2) 7899 .Case("nios2r2bmx", isR2) 7900 .Case("nios2r2mpx", isR2) 7901 .Case("nios2r2cdx", isR2) 7902 .Default(false); 7903 } 7904 7905 bool initFeatureMap(llvm::StringMap<bool> &Features, 7906 DiagnosticsEngine &Diags, StringRef CPU, 7907 const std::vector<std::string> &FeatureVec) const override { 7908 static const char *allFeatures[] = { 7909 "nios2r2mandatory", "nios2r2bmx", "nios2r2mpx", "nios2r2cdx" 7910 }; 7911 for (const char *feature : allFeatures) { 7912 Features[feature] = isFeatureSupportedByCPU(feature, CPU); 7913 } 7914 return true; 7915 } 7916 7917 bool hasFeature(StringRef Feature) const override { 7918 return isFeatureSupportedByCPU(Feature, CPU); 7919 } 7920 7921 BuiltinVaListKind getBuiltinVaListKind() const override { 7922 return TargetInfo::VoidPtrBuiltinVaList; 7923 } 7924 7925 ArrayRef<const char *> getGCCRegNames() const override { 7926 static const char *const GCCRegNames[] = { 7927 // CPU register names 7928 // Must match second column of GCCRegAliases 7929 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 7930 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", 7931 "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", 7932 "r31", 7933 // Floating point register names 7934 "ctl0", "ctl1", "ctl2", "ctl3", "ctl4", "ctl5", "ctl6", "ctl7", "ctl8", 7935 "ctl9", "ctl10", "ctl11", "ctl12", "ctl13", "ctl14", "ctl15" 7936 }; 7937 return llvm::makeArrayRef(GCCRegNames); 7938 } 7939 7940 bool validateAsmConstraint(const char *&Name, 7941 TargetInfo::ConstraintInfo &Info) const override { 7942 switch (*Name) { 7943 default: 7944 return false; 7945 7946 case 'r': // CPU registers. 7947 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7948 case 'y': // Equivalent to "r", backwards compatibility only. 7949 case 'f': // floating-point registers. 7950 case 'c': // $25 for indirect jumps 7951 case 'l': // lo register 7952 case 'x': // hilo register pair 7953 Info.setAllowsRegister(); 7954 return true; 7955 } 7956 } 7957 7958 const char *getClobbers() const override { return ""; } 7959 7960 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7961 static const TargetInfo::GCCRegAlias aliases[] = { 7962 {{"zero"}, "r0"}, {{"at"}, "r1"}, {{"et"}, "r24"}, 7963 {{"bt"}, "r25"}, {{"gp"}, "r26"}, {{"sp"}, "r27"}, 7964 {{"fp"}, "r28"}, {{"ea"}, "r29"}, {{"ba"}, "r30"}, 7965 {{"ra"}, "r31"}, {{"status"}, "ctl0"}, {{"estatus"}, "ctl1"}, 7966 {{"bstatus"}, "ctl2"}, {{"ienable"}, "ctl3"}, {{"ipending"}, "ctl4"}, 7967 {{"cpuid"}, "ctl5"}, {{"exception"}, "ctl7"}, {{"pteaddr"}, "ctl8"}, 7968 {{"tlbacc"}, "ctl9"}, {{"tlbmisc"}, "ctl10"}, {{"badaddr"}, "ctl12"}, 7969 {{"config"}, "ctl13"}, {{"mpubase"}, "ctl14"}, {{"mpuacc"}, "ctl15"}, 7970 }; 7971 return llvm::makeArrayRef(aliases); 7972 } 7973 }; 7974 7975 const Builtin::Info Nios2TargetInfo::BuiltinInfo[] = { 7976 #define BUILTIN(ID, TYPE, ATTRS) \ 7977 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 7978 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7979 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 7980 #include "clang/Basic/BuiltinsNios2.def" 7981 }; 7982 7983 class MipsTargetInfo : public TargetInfo { 7984 void setDataLayout() { 7985 StringRef Layout; 7986 7987 if (ABI == "o32") 7988 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7989 else if (ABI == "n32") 7990 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7991 else if (ABI == "n64") 7992 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7993 else 7994 llvm_unreachable("Invalid ABI"); 7995 7996 if (BigEndian) 7997 resetDataLayout(("E-" + Layout).str()); 7998 else 7999 resetDataLayout(("e-" + Layout).str()); 8000 } 8001 8002 8003 static const Builtin::Info BuiltinInfo[]; 8004 std::string CPU; 8005 bool IsMips16; 8006 bool IsMicromips; 8007 bool IsNan2008; 8008 bool IsSingleFloat; 8009 bool IsNoABICalls; 8010 bool CanUseBSDABICalls; 8011 enum MipsFloatABI { 8012 HardFloat, SoftFloat 8013 } FloatABI; 8014 enum DspRevEnum { 8015 NoDSP, DSP1, DSP2 8016 } DspRev; 8017 bool HasMSA; 8018 bool DisableMadd4; 8019 8020 protected: 8021 bool HasFP64; 8022 std::string ABI; 8023 8024 public: 8025 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8026 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 8027 IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false), 8028 CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP), 8029 HasMSA(false), DisableMadd4(false), HasFP64(false) { 8030 TheCXXABI.set(TargetCXXABI::GenericMIPS); 8031 8032 setABI((getTriple().getArch() == llvm::Triple::mips || 8033 getTriple().getArch() == llvm::Triple::mipsel) 8034 ? "o32" 8035 : "n64"); 8036 8037 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 8038 8039 CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD || 8040 Triple.getOS() == llvm::Triple::OpenBSD; 8041 } 8042 8043 bool isNaN2008Default() const { 8044 return CPU == "mips32r6" || CPU == "mips64r6"; 8045 } 8046 8047 bool isFP64Default() const { 8048 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 8049 } 8050 8051 bool isNan2008() const override { 8052 return IsNan2008; 8053 } 8054 8055 bool processorSupportsGPR64() const { 8056 return llvm::StringSwitch<bool>(CPU) 8057 .Case("mips3", true) 8058 .Case("mips4", true) 8059 .Case("mips5", true) 8060 .Case("mips64", true) 8061 .Case("mips64r2", true) 8062 .Case("mips64r3", true) 8063 .Case("mips64r5", true) 8064 .Case("mips64r6", true) 8065 .Case("octeon", true) 8066 .Default(false); 8067 return false; 8068 } 8069 8070 StringRef getABI() const override { return ABI; } 8071 bool setABI(const std::string &Name) override { 8072 if (Name == "o32") { 8073 setO32ABITypes(); 8074 ABI = Name; 8075 return true; 8076 } 8077 8078 if (Name == "n32") { 8079 setN32ABITypes(); 8080 ABI = Name; 8081 return true; 8082 } 8083 if (Name == "n64") { 8084 setN64ABITypes(); 8085 ABI = Name; 8086 return true; 8087 } 8088 return false; 8089 } 8090 8091 void setO32ABITypes() { 8092 Int64Type = SignedLongLong; 8093 IntMaxType = Int64Type; 8094 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8095 LongDoubleWidth = LongDoubleAlign = 64; 8096 LongWidth = LongAlign = 32; 8097 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 8098 PointerWidth = PointerAlign = 32; 8099 PtrDiffType = SignedInt; 8100 SizeType = UnsignedInt; 8101 SuitableAlign = 64; 8102 } 8103 8104 void setN32N64ABITypes() { 8105 LongDoubleWidth = LongDoubleAlign = 128; 8106 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8107 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 8108 LongDoubleWidth = LongDoubleAlign = 64; 8109 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8110 } 8111 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8112 SuitableAlign = 128; 8113 } 8114 8115 void setN64ABITypes() { 8116 setN32N64ABITypes(); 8117 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 8118 Int64Type = SignedLongLong; 8119 } else { 8120 Int64Type = SignedLong; 8121 } 8122 IntMaxType = Int64Type; 8123 LongWidth = LongAlign = 64; 8124 PointerWidth = PointerAlign = 64; 8125 PtrDiffType = SignedLong; 8126 SizeType = UnsignedLong; 8127 } 8128 8129 void setN32ABITypes() { 8130 setN32N64ABITypes(); 8131 Int64Type = SignedLongLong; 8132 IntMaxType = Int64Type; 8133 LongWidth = LongAlign = 32; 8134 PointerWidth = PointerAlign = 32; 8135 PtrDiffType = SignedInt; 8136 SizeType = UnsignedInt; 8137 } 8138 8139 bool setCPU(const std::string &Name) override { 8140 CPU = Name; 8141 return llvm::StringSwitch<bool>(Name) 8142 .Case("mips1", true) 8143 .Case("mips2", true) 8144 .Case("mips3", true) 8145 .Case("mips4", true) 8146 .Case("mips5", true) 8147 .Case("mips32", true) 8148 .Case("mips32r2", true) 8149 .Case("mips32r3", true) 8150 .Case("mips32r5", true) 8151 .Case("mips32r6", true) 8152 .Case("mips64", true) 8153 .Case("mips64r2", true) 8154 .Case("mips64r3", true) 8155 .Case("mips64r5", true) 8156 .Case("mips64r6", true) 8157 .Case("octeon", true) 8158 .Case("p5600", true) 8159 .Default(false); 8160 } 8161 const std::string& getCPU() const { return CPU; } 8162 bool 8163 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 8164 StringRef CPU, 8165 const std::vector<std::string> &FeaturesVec) const override { 8166 if (CPU.empty()) 8167 CPU = getCPU(); 8168 if (CPU == "octeon") 8169 Features["mips64r2"] = Features["cnmips"] = true; 8170 else 8171 Features[CPU] = true; 8172 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 8173 } 8174 8175 void getTargetDefines(const LangOptions &Opts, 8176 MacroBuilder &Builder) const override { 8177 if (BigEndian) { 8178 DefineStd(Builder, "MIPSEB", Opts); 8179 Builder.defineMacro("_MIPSEB"); 8180 } else { 8181 DefineStd(Builder, "MIPSEL", Opts); 8182 Builder.defineMacro("_MIPSEL"); 8183 } 8184 8185 Builder.defineMacro("__mips__"); 8186 Builder.defineMacro("_mips"); 8187 if (Opts.GNUMode) 8188 Builder.defineMacro("mips"); 8189 8190 if (ABI == "o32") { 8191 Builder.defineMacro("__mips", "32"); 8192 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 8193 } else { 8194 Builder.defineMacro("__mips", "64"); 8195 Builder.defineMacro("__mips64"); 8196 Builder.defineMacro("__mips64__"); 8197 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 8198 } 8199 8200 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 8201 .Cases("mips32", "mips64", "1") 8202 .Cases("mips32r2", "mips64r2", "2") 8203 .Cases("mips32r3", "mips64r3", "3") 8204 .Cases("mips32r5", "mips64r5", "5") 8205 .Cases("mips32r6", "mips64r6", "6") 8206 .Default(""); 8207 if (!ISARev.empty()) 8208 Builder.defineMacro("__mips_isa_rev", ISARev); 8209 8210 if (ABI == "o32") { 8211 Builder.defineMacro("__mips_o32"); 8212 Builder.defineMacro("_ABIO32", "1"); 8213 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 8214 } else if (ABI == "n32") { 8215 Builder.defineMacro("__mips_n32"); 8216 Builder.defineMacro("_ABIN32", "2"); 8217 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 8218 } else if (ABI == "n64") { 8219 Builder.defineMacro("__mips_n64"); 8220 Builder.defineMacro("_ABI64", "3"); 8221 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 8222 } else 8223 llvm_unreachable("Invalid ABI."); 8224 8225 if (!IsNoABICalls) { 8226 Builder.defineMacro("__mips_abicalls"); 8227 if (CanUseBSDABICalls) 8228 Builder.defineMacro("__ABICALLS__"); 8229 } 8230 8231 Builder.defineMacro("__REGISTER_PREFIX__", ""); 8232 8233 switch (FloatABI) { 8234 case HardFloat: 8235 Builder.defineMacro("__mips_hard_float", Twine(1)); 8236 break; 8237 case SoftFloat: 8238 Builder.defineMacro("__mips_soft_float", Twine(1)); 8239 break; 8240 } 8241 8242 if (IsSingleFloat) 8243 Builder.defineMacro("__mips_single_float", Twine(1)); 8244 8245 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 8246 Builder.defineMacro("_MIPS_FPSET", 8247 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 8248 8249 if (IsMips16) 8250 Builder.defineMacro("__mips16", Twine(1)); 8251 8252 if (IsMicromips) 8253 Builder.defineMacro("__mips_micromips", Twine(1)); 8254 8255 if (IsNan2008) 8256 Builder.defineMacro("__mips_nan2008", Twine(1)); 8257 8258 switch (DspRev) { 8259 default: 8260 break; 8261 case DSP1: 8262 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 8263 Builder.defineMacro("__mips_dsp", Twine(1)); 8264 break; 8265 case DSP2: 8266 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 8267 Builder.defineMacro("__mips_dspr2", Twine(1)); 8268 Builder.defineMacro("__mips_dsp", Twine(1)); 8269 break; 8270 } 8271 8272 if (HasMSA) 8273 Builder.defineMacro("__mips_msa", Twine(1)); 8274 8275 if (DisableMadd4) 8276 Builder.defineMacro("__mips_no_madd4", Twine(1)); 8277 8278 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 8279 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 8280 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 8281 8282 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 8283 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 8284 8285 // These shouldn't be defined for MIPS-I but there's no need to check 8286 // for that since MIPS-I isn't supported. 8287 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 8288 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 8289 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 8290 8291 // 32-bit MIPS processors don't have the necessary lld/scd instructions 8292 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 8293 // the instructions exist but using them violates the ABI since they 8294 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 8295 if (ABI == "n32" || ABI == "n64") 8296 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 8297 } 8298 8299 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8300 return llvm::makeArrayRef(BuiltinInfo, 8301 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 8302 } 8303 bool hasFeature(StringRef Feature) const override { 8304 return llvm::StringSwitch<bool>(Feature) 8305 .Case("mips", true) 8306 .Case("fp64", HasFP64) 8307 .Default(false); 8308 } 8309 BuiltinVaListKind getBuiltinVaListKind() const override { 8310 return TargetInfo::VoidPtrBuiltinVaList; 8311 } 8312 ArrayRef<const char *> getGCCRegNames() const override { 8313 static const char *const GCCRegNames[] = { 8314 // CPU register names 8315 // Must match second column of GCCRegAliases 8316 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 8317 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 8318 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 8319 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 8320 // Floating point register names 8321 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 8322 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 8323 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 8324 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 8325 // Hi/lo and condition register names 8326 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 8327 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 8328 "$ac3hi","$ac3lo", 8329 // MSA register names 8330 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 8331 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 8332 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 8333 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 8334 // MSA control register names 8335 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 8336 "$msarequest", "$msamap", "$msaunmap" 8337 }; 8338 return llvm::makeArrayRef(GCCRegNames); 8339 } 8340 bool validateAsmConstraint(const char *&Name, 8341 TargetInfo::ConstraintInfo &Info) const override { 8342 switch (*Name) { 8343 default: 8344 return false; 8345 case 'r': // CPU registers. 8346 case 'd': // Equivalent to "r" unless generating MIPS16 code. 8347 case 'y': // Equivalent to "r", backward compatibility only. 8348 case 'f': // floating-point registers. 8349 case 'c': // $25 for indirect jumps 8350 case 'l': // lo register 8351 case 'x': // hilo register pair 8352 Info.setAllowsRegister(); 8353 return true; 8354 case 'I': // Signed 16-bit constant 8355 case 'J': // Integer 0 8356 case 'K': // Unsigned 16-bit constant 8357 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 8358 case 'M': // Constants not loadable via lui, addiu, or ori 8359 case 'N': // Constant -1 to -65535 8360 case 'O': // A signed 15-bit constant 8361 case 'P': // A constant between 1 go 65535 8362 return true; 8363 case 'R': // An address that can be used in a non-macro load or store 8364 Info.setAllowsMemory(); 8365 return true; 8366 case 'Z': 8367 if (Name[1] == 'C') { // An address usable by ll, and sc. 8368 Info.setAllowsMemory(); 8369 Name++; // Skip over 'Z'. 8370 return true; 8371 } 8372 return false; 8373 } 8374 } 8375 8376 std::string convertConstraint(const char *&Constraint) const override { 8377 std::string R; 8378 switch (*Constraint) { 8379 case 'Z': // Two-character constraint; add "^" hint for later parsing. 8380 if (Constraint[1] == 'C') { 8381 R = std::string("^") + std::string(Constraint, 2); 8382 Constraint++; 8383 return R; 8384 } 8385 break; 8386 } 8387 return TargetInfo::convertConstraint(Constraint); 8388 } 8389 8390 const char *getClobbers() const override { 8391 // In GCC, $1 is not widely used in generated code (it's used only in a few 8392 // specific situations), so there is no real need for users to add it to 8393 // the clobbers list if they want to use it in their inline assembly code. 8394 // 8395 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 8396 // code generation, so using it in inline assembly without adding it to the 8397 // clobbers list can cause conflicts between the inline assembly code and 8398 // the surrounding generated code. 8399 // 8400 // Another problem is that LLVM is allowed to choose $1 for inline assembly 8401 // operands, which will conflict with the ".set at" assembler option (which 8402 // we use only for inline assembly, in order to maintain compatibility with 8403 // GCC) and will also conflict with the user's usage of $1. 8404 // 8405 // The easiest way to avoid these conflicts and keep $1 as an allocatable 8406 // register for generated code is to automatically clobber $1 for all inline 8407 // assembly code. 8408 // 8409 // FIXME: We should automatically clobber $1 only for inline assembly code 8410 // which actually uses it. This would allow LLVM to use $1 for inline 8411 // assembly operands if the user's assembly code doesn't use it. 8412 return "~{$1}"; 8413 } 8414 8415 bool handleTargetFeatures(std::vector<std::string> &Features, 8416 DiagnosticsEngine &Diags) override { 8417 IsMips16 = false; 8418 IsMicromips = false; 8419 IsNan2008 = isNaN2008Default(); 8420 IsSingleFloat = false; 8421 FloatABI = HardFloat; 8422 DspRev = NoDSP; 8423 HasFP64 = isFP64Default(); 8424 8425 for (const auto &Feature : Features) { 8426 if (Feature == "+single-float") 8427 IsSingleFloat = true; 8428 else if (Feature == "+soft-float") 8429 FloatABI = SoftFloat; 8430 else if (Feature == "+mips16") 8431 IsMips16 = true; 8432 else if (Feature == "+micromips") 8433 IsMicromips = true; 8434 else if (Feature == "+dsp") 8435 DspRev = std::max(DspRev, DSP1); 8436 else if (Feature == "+dspr2") 8437 DspRev = std::max(DspRev, DSP2); 8438 else if (Feature == "+msa") 8439 HasMSA = true; 8440 else if (Feature == "+nomadd4") 8441 DisableMadd4 = true; 8442 else if (Feature == "+fp64") 8443 HasFP64 = true; 8444 else if (Feature == "-fp64") 8445 HasFP64 = false; 8446 else if (Feature == "+nan2008") 8447 IsNan2008 = true; 8448 else if (Feature == "-nan2008") 8449 IsNan2008 = false; 8450 else if (Feature == "+noabicalls") 8451 IsNoABICalls = true; 8452 } 8453 8454 setDataLayout(); 8455 8456 return true; 8457 } 8458 8459 int getEHDataRegisterNumber(unsigned RegNo) const override { 8460 if (RegNo == 0) return 4; 8461 if (RegNo == 1) return 5; 8462 return -1; 8463 } 8464 8465 bool isCLZForZeroUndef() const override { return false; } 8466 8467 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8468 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 8469 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8470 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8471 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 8472 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 8473 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 8474 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8475 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8476 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8477 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8478 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8479 {{"ra"}, "$31"}}; 8480 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 8481 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8482 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8483 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 8484 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 8485 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 8486 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8487 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8488 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8489 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8490 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8491 {{"ra"}, "$31"}}; 8492 if (ABI == "o32") 8493 return llvm::makeArrayRef(O32RegAliases); 8494 return llvm::makeArrayRef(NewABIRegAliases); 8495 } 8496 8497 bool hasInt128Type() const override { 8498 return ABI == "n32" || ABI == "n64"; 8499 } 8500 8501 bool validateTarget(DiagnosticsEngine &Diags) const override { 8502 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 8503 // this yet. It's better to fail here than on the backend assertion. 8504 if (processorSupportsGPR64() && ABI == "o32") { 8505 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8506 return false; 8507 } 8508 8509 // 64-bit ABI's require 64-bit CPU's. 8510 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 8511 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8512 return false; 8513 } 8514 8515 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 8516 // can't handle this yet. It's better to fail here than on the 8517 // backend assertion. 8518 if ((getTriple().getArch() == llvm::Triple::mips64 || 8519 getTriple().getArch() == llvm::Triple::mips64el) && 8520 ABI == "o32") { 8521 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8522 << ABI << getTriple().str(); 8523 return false; 8524 } 8525 8526 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 8527 // can't handle this yet. It's better to fail here than on the 8528 // backend assertion. 8529 if ((getTriple().getArch() == llvm::Triple::mips || 8530 getTriple().getArch() == llvm::Triple::mipsel) && 8531 (ABI == "n32" || ABI == "n64")) { 8532 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8533 << ABI << getTriple().str(); 8534 return false; 8535 } 8536 8537 return true; 8538 } 8539 }; 8540 8541 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 8542 #define BUILTIN(ID, TYPE, ATTRS) \ 8543 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8544 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8545 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8546 #include "clang/Basic/BuiltinsMips.def" 8547 }; 8548 8549 class PNaClTargetInfo : public TargetInfo { 8550 public: 8551 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8552 : TargetInfo(Triple) { 8553 this->LongAlign = 32; 8554 this->LongWidth = 32; 8555 this->PointerAlign = 32; 8556 this->PointerWidth = 32; 8557 this->IntMaxType = TargetInfo::SignedLongLong; 8558 this->Int64Type = TargetInfo::SignedLongLong; 8559 this->DoubleAlign = 64; 8560 this->LongDoubleWidth = 64; 8561 this->LongDoubleAlign = 64; 8562 this->SizeType = TargetInfo::UnsignedInt; 8563 this->PtrDiffType = TargetInfo::SignedInt; 8564 this->IntPtrType = TargetInfo::SignedInt; 8565 this->RegParmMax = 0; // Disallow regparm 8566 } 8567 8568 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 8569 Builder.defineMacro("__le32__"); 8570 Builder.defineMacro("__pnacl__"); 8571 } 8572 void getTargetDefines(const LangOptions &Opts, 8573 MacroBuilder &Builder) const override { 8574 getArchDefines(Opts, Builder); 8575 } 8576 bool hasFeature(StringRef Feature) const override { 8577 return Feature == "pnacl"; 8578 } 8579 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8580 BuiltinVaListKind getBuiltinVaListKind() const override { 8581 return TargetInfo::PNaClABIBuiltinVaList; 8582 } 8583 ArrayRef<const char *> getGCCRegNames() const override; 8584 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 8585 bool validateAsmConstraint(const char *&Name, 8586 TargetInfo::ConstraintInfo &Info) const override { 8587 return false; 8588 } 8589 8590 const char *getClobbers() const override { 8591 return ""; 8592 } 8593 }; 8594 8595 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 8596 return None; 8597 } 8598 8599 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 8600 return None; 8601 } 8602 8603 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 8604 class NaClMips32TargetInfo : public MipsTargetInfo { 8605 public: 8606 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8607 : MipsTargetInfo(Triple, Opts) {} 8608 8609 BuiltinVaListKind getBuiltinVaListKind() const override { 8610 return TargetInfo::PNaClABIBuiltinVaList; 8611 } 8612 }; 8613 8614 class Le64TargetInfo : public TargetInfo { 8615 static const Builtin::Info BuiltinInfo[]; 8616 8617 public: 8618 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8619 : TargetInfo(Triple) { 8620 NoAsmVariants = true; 8621 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 8622 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8623 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 8624 } 8625 8626 void getTargetDefines(const LangOptions &Opts, 8627 MacroBuilder &Builder) const override { 8628 DefineStd(Builder, "unix", Opts); 8629 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 8630 Builder.defineMacro("__ELF__"); 8631 } 8632 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8633 return llvm::makeArrayRef(BuiltinInfo, 8634 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 8635 } 8636 BuiltinVaListKind getBuiltinVaListKind() const override { 8637 return TargetInfo::PNaClABIBuiltinVaList; 8638 } 8639 const char *getClobbers() const override { return ""; } 8640 ArrayRef<const char *> getGCCRegNames() const override { 8641 return None; 8642 } 8643 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8644 return None; 8645 } 8646 bool validateAsmConstraint(const char *&Name, 8647 TargetInfo::ConstraintInfo &Info) const override { 8648 return false; 8649 } 8650 8651 bool hasProtectedVisibility() const override { return false; } 8652 }; 8653 8654 class WebAssemblyTargetInfo : public TargetInfo { 8655 static const Builtin::Info BuiltinInfo[]; 8656 8657 enum SIMDEnum { 8658 NoSIMD, 8659 SIMD128, 8660 } SIMDLevel; 8661 8662 public: 8663 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 8664 : TargetInfo(T), SIMDLevel(NoSIMD) { 8665 NoAsmVariants = true; 8666 SuitableAlign = 128; 8667 LargeArrayMinWidth = 128; 8668 LargeArrayAlign = 128; 8669 SimdDefaultAlign = 128; 8670 SigAtomicType = SignedLong; 8671 LongDoubleWidth = LongDoubleAlign = 128; 8672 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8673 SizeType = UnsignedInt; 8674 PtrDiffType = SignedInt; 8675 IntPtrType = SignedInt; 8676 } 8677 8678 protected: 8679 void getTargetDefines(const LangOptions &Opts, 8680 MacroBuilder &Builder) const override { 8681 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 8682 if (SIMDLevel >= SIMD128) 8683 Builder.defineMacro("__wasm_simd128__"); 8684 } 8685 8686 private: 8687 bool 8688 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 8689 StringRef CPU, 8690 const std::vector<std::string> &FeaturesVec) const override { 8691 if (CPU == "bleeding-edge") 8692 Features["simd128"] = true; 8693 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 8694 } 8695 bool hasFeature(StringRef Feature) const final { 8696 return llvm::StringSwitch<bool>(Feature) 8697 .Case("simd128", SIMDLevel >= SIMD128) 8698 .Default(false); 8699 } 8700 bool handleTargetFeatures(std::vector<std::string> &Features, 8701 DiagnosticsEngine &Diags) final { 8702 for (const auto &Feature : Features) { 8703 if (Feature == "+simd128") { 8704 SIMDLevel = std::max(SIMDLevel, SIMD128); 8705 continue; 8706 } 8707 if (Feature == "-simd128") { 8708 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 8709 continue; 8710 } 8711 8712 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 8713 << "-target-feature"; 8714 return false; 8715 } 8716 return true; 8717 } 8718 bool setCPU(const std::string &Name) final { 8719 return llvm::StringSwitch<bool>(Name) 8720 .Case("mvp", true) 8721 .Case("bleeding-edge", true) 8722 .Case("generic", true) 8723 .Default(false); 8724 } 8725 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 8726 return llvm::makeArrayRef(BuiltinInfo, 8727 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 8728 } 8729 BuiltinVaListKind getBuiltinVaListKind() const final { 8730 return VoidPtrBuiltinVaList; 8731 } 8732 ArrayRef<const char *> getGCCRegNames() const final { 8733 return None; 8734 } 8735 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 8736 return None; 8737 } 8738 bool 8739 validateAsmConstraint(const char *&Name, 8740 TargetInfo::ConstraintInfo &Info) const final { 8741 return false; 8742 } 8743 const char *getClobbers() const final { return ""; } 8744 bool isCLZForZeroUndef() const final { return false; } 8745 bool hasInt128Type() const final { return true; } 8746 IntType getIntTypeByWidth(unsigned BitWidth, 8747 bool IsSigned) const final { 8748 // WebAssembly prefers long long for explicitly 64-bit integers. 8749 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8750 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8751 } 8752 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8753 bool IsSigned) const final { 8754 // WebAssembly uses long long for int_least64_t and int_fast64_t. 8755 return BitWidth == 64 8756 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8757 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 8758 } 8759 }; 8760 8761 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 8762 #define BUILTIN(ID, TYPE, ATTRS) \ 8763 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8764 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8765 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8766 #include "clang/Basic/BuiltinsWebAssembly.def" 8767 }; 8768 8769 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 8770 public: 8771 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 8772 const TargetOptions &Opts) 8773 : WebAssemblyTargetInfo(T, Opts) { 8774 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8775 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 8776 } 8777 8778 protected: 8779 void getTargetDefines(const LangOptions &Opts, 8780 MacroBuilder &Builder) const override { 8781 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8782 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 8783 } 8784 }; 8785 8786 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 8787 public: 8788 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 8789 const TargetOptions &Opts) 8790 : WebAssemblyTargetInfo(T, Opts) { 8791 LongAlign = LongWidth = 64; 8792 PointerAlign = PointerWidth = 64; 8793 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8794 SizeType = UnsignedLong; 8795 PtrDiffType = SignedLong; 8796 IntPtrType = SignedLong; 8797 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 8798 } 8799 8800 protected: 8801 void getTargetDefines(const LangOptions &Opts, 8802 MacroBuilder &Builder) const override { 8803 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8804 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 8805 } 8806 }; 8807 8808 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 8809 #define BUILTIN(ID, TYPE, ATTRS) \ 8810 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8811 #include "clang/Basic/BuiltinsLe64.def" 8812 }; 8813 8814 static const unsigned SPIRAddrSpaceMap[] = { 8815 0, // Default 8816 1, // opencl_global 8817 3, // opencl_local 8818 2, // opencl_constant 8819 4, // opencl_generic 8820 0, // cuda_device 8821 0, // cuda_constant 8822 0 // cuda_shared 8823 }; 8824 class SPIRTargetInfo : public TargetInfo { 8825 public: 8826 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8827 : TargetInfo(Triple) { 8828 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 8829 "SPIR target must use unknown OS"); 8830 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 8831 "SPIR target must use unknown environment type"); 8832 TLSSupported = false; 8833 LongWidth = LongAlign = 64; 8834 AddrSpaceMap = &SPIRAddrSpaceMap; 8835 UseAddrSpaceMapMangling = true; 8836 // Define available target features 8837 // These must be defined in sorted order! 8838 NoAsmVariants = true; 8839 } 8840 void getTargetDefines(const LangOptions &Opts, 8841 MacroBuilder &Builder) const override { 8842 DefineStd(Builder, "SPIR", Opts); 8843 } 8844 bool hasFeature(StringRef Feature) const override { 8845 return Feature == "spir"; 8846 } 8847 8848 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8849 const char *getClobbers() const override { return ""; } 8850 ArrayRef<const char *> getGCCRegNames() const override { return None; } 8851 bool validateAsmConstraint(const char *&Name, 8852 TargetInfo::ConstraintInfo &info) const override { 8853 return true; 8854 } 8855 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8856 return None; 8857 } 8858 BuiltinVaListKind getBuiltinVaListKind() const override { 8859 return TargetInfo::VoidPtrBuiltinVaList; 8860 } 8861 8862 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 8863 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 8864 : CCCR_Warning; 8865 } 8866 8867 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8868 return CC_SpirFunction; 8869 } 8870 8871 void setSupportedOpenCLOpts() override { 8872 // Assume all OpenCL extensions and optional core features are supported 8873 // for SPIR since it is a generic target. 8874 getSupportedOpenCLOpts().supportAll(); 8875 } 8876 }; 8877 8878 class SPIR32TargetInfo : public SPIRTargetInfo { 8879 public: 8880 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8881 : SPIRTargetInfo(Triple, Opts) { 8882 PointerWidth = PointerAlign = 32; 8883 SizeType = TargetInfo::UnsignedInt; 8884 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8885 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8886 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8887 } 8888 void getTargetDefines(const LangOptions &Opts, 8889 MacroBuilder &Builder) const override { 8890 DefineStd(Builder, "SPIR32", Opts); 8891 } 8892 }; 8893 8894 class SPIR64TargetInfo : public SPIRTargetInfo { 8895 public: 8896 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8897 : SPIRTargetInfo(Triple, Opts) { 8898 PointerWidth = PointerAlign = 64; 8899 SizeType = TargetInfo::UnsignedLong; 8900 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8901 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8902 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8903 } 8904 void getTargetDefines(const LangOptions &Opts, 8905 MacroBuilder &Builder) const override { 8906 DefineStd(Builder, "SPIR64", Opts); 8907 } 8908 }; 8909 8910 class XCoreTargetInfo : public TargetInfo { 8911 static const Builtin::Info BuiltinInfo[]; 8912 public: 8913 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8914 : TargetInfo(Triple) { 8915 NoAsmVariants = true; 8916 LongLongAlign = 32; 8917 SuitableAlign = 32; 8918 DoubleAlign = LongDoubleAlign = 32; 8919 SizeType = UnsignedInt; 8920 PtrDiffType = SignedInt; 8921 IntPtrType = SignedInt; 8922 WCharType = UnsignedChar; 8923 WIntType = UnsignedInt; 8924 UseZeroLengthBitfieldAlignment = true; 8925 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8926 "-f64:32-a:0:32-n32"); 8927 } 8928 void getTargetDefines(const LangOptions &Opts, 8929 MacroBuilder &Builder) const override { 8930 Builder.defineMacro("__XS1B__"); 8931 } 8932 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8933 return llvm::makeArrayRef(BuiltinInfo, 8934 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8935 } 8936 BuiltinVaListKind getBuiltinVaListKind() const override { 8937 return TargetInfo::VoidPtrBuiltinVaList; 8938 } 8939 const char *getClobbers() const override { 8940 return ""; 8941 } 8942 ArrayRef<const char *> getGCCRegNames() const override { 8943 static const char * const GCCRegNames[] = { 8944 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8945 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8946 }; 8947 return llvm::makeArrayRef(GCCRegNames); 8948 } 8949 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8950 return None; 8951 } 8952 bool validateAsmConstraint(const char *&Name, 8953 TargetInfo::ConstraintInfo &Info) const override { 8954 return false; 8955 } 8956 int getEHDataRegisterNumber(unsigned RegNo) const override { 8957 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8958 return (RegNo < 2)? RegNo : -1; 8959 } 8960 bool allowsLargerPreferedTypeAlignment() const override { 8961 return false; 8962 } 8963 }; 8964 8965 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8966 #define BUILTIN(ID, TYPE, ATTRS) \ 8967 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8968 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8969 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8970 #include "clang/Basic/BuiltinsXCore.def" 8971 }; 8972 8973 // x86_32 Android target 8974 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8975 public: 8976 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8977 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8978 SuitableAlign = 32; 8979 LongDoubleWidth = 64; 8980 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8981 } 8982 }; 8983 8984 // x86_64 Android target 8985 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8986 public: 8987 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8988 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8989 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8990 } 8991 8992 bool useFloat128ManglingForLongDouble() const override { 8993 return true; 8994 } 8995 }; 8996 8997 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8998 class RenderScript32TargetInfo : public ARMleTargetInfo { 8999 public: 9000 RenderScript32TargetInfo(const llvm::Triple &Triple, 9001 const TargetOptions &Opts) 9002 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 9003 Triple.getOSName(), 9004 Triple.getEnvironmentName()), 9005 Opts) { 9006 IsRenderScriptTarget = true; 9007 LongWidth = LongAlign = 64; 9008 } 9009 void getTargetDefines(const LangOptions &Opts, 9010 MacroBuilder &Builder) const override { 9011 Builder.defineMacro("__RENDERSCRIPT__"); 9012 ARMleTargetInfo::getTargetDefines(Opts, Builder); 9013 } 9014 }; 9015 9016 // 64-bit RenderScript is aarch64 9017 class RenderScript64TargetInfo : public AArch64leTargetInfo { 9018 public: 9019 RenderScript64TargetInfo(const llvm::Triple &Triple, 9020 const TargetOptions &Opts) 9021 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 9022 Triple.getOSName(), 9023 Triple.getEnvironmentName()), 9024 Opts) { 9025 IsRenderScriptTarget = true; 9026 } 9027 9028 void getTargetDefines(const LangOptions &Opts, 9029 MacroBuilder &Builder) const override { 9030 Builder.defineMacro("__RENDERSCRIPT__"); 9031 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 9032 } 9033 }; 9034 9035 /// Information about a specific microcontroller. 9036 struct MCUInfo { 9037 const char *Name; 9038 const char *DefineName; 9039 }; 9040 9041 // This list should be kept up-to-date with AVRDevices.td in LLVM. 9042 static ArrayRef<MCUInfo> AVRMcus = { 9043 { "at90s1200", "__AVR_AT90S1200__" }, 9044 { "attiny11", "__AVR_ATtiny11__" }, 9045 { "attiny12", "__AVR_ATtiny12__" }, 9046 { "attiny15", "__AVR_ATtiny15__" }, 9047 { "attiny28", "__AVR_ATtiny28__" }, 9048 { "at90s2313", "__AVR_AT90S2313__" }, 9049 { "at90s2323", "__AVR_AT90S2323__" }, 9050 { "at90s2333", "__AVR_AT90S2333__" }, 9051 { "at90s2343", "__AVR_AT90S2343__" }, 9052 { "attiny22", "__AVR_ATtiny22__" }, 9053 { "attiny26", "__AVR_ATtiny26__" }, 9054 { "at86rf401", "__AVR_AT86RF401__" }, 9055 { "at90s4414", "__AVR_AT90S4414__" }, 9056 { "at90s4433", "__AVR_AT90S4433__" }, 9057 { "at90s4434", "__AVR_AT90S4434__" }, 9058 { "at90s8515", "__AVR_AT90S8515__" }, 9059 { "at90c8534", "__AVR_AT90c8534__" }, 9060 { "at90s8535", "__AVR_AT90S8535__" }, 9061 { "ata5272", "__AVR_ATA5272__" }, 9062 { "attiny13", "__AVR_ATtiny13__" }, 9063 { "attiny13a", "__AVR_ATtiny13A__" }, 9064 { "attiny2313", "__AVR_ATtiny2313__" }, 9065 { "attiny2313a", "__AVR_ATtiny2313A__" }, 9066 { "attiny24", "__AVR_ATtiny24__" }, 9067 { "attiny24a", "__AVR_ATtiny24A__" }, 9068 { "attiny4313", "__AVR_ATtiny4313__" }, 9069 { "attiny44", "__AVR_ATtiny44__" }, 9070 { "attiny44a", "__AVR_ATtiny44A__" }, 9071 { "attiny84", "__AVR_ATtiny84__" }, 9072 { "attiny84a", "__AVR_ATtiny84A__" }, 9073 { "attiny25", "__AVR_ATtiny25__" }, 9074 { "attiny45", "__AVR_ATtiny45__" }, 9075 { "attiny85", "__AVR_ATtiny85__" }, 9076 { "attiny261", "__AVR_ATtiny261__" }, 9077 { "attiny261a", "__AVR_ATtiny261A__" }, 9078 { "attiny461", "__AVR_ATtiny461__" }, 9079 { "attiny461a", "__AVR_ATtiny461A__" }, 9080 { "attiny861", "__AVR_ATtiny861__" }, 9081 { "attiny861a", "__AVR_ATtiny861A__" }, 9082 { "attiny87", "__AVR_ATtiny87__" }, 9083 { "attiny43u", "__AVR_ATtiny43U__" }, 9084 { "attiny48", "__AVR_ATtiny48__" }, 9085 { "attiny88", "__AVR_ATtiny88__" }, 9086 { "attiny828", "__AVR_ATtiny828__" }, 9087 { "at43usb355", "__AVR_AT43USB355__" }, 9088 { "at76c711", "__AVR_AT76C711__" }, 9089 { "atmega103", "__AVR_ATmega103__" }, 9090 { "at43usb320", "__AVR_AT43USB320__" }, 9091 { "attiny167", "__AVR_ATtiny167__" }, 9092 { "at90usb82", "__AVR_AT90USB82__" }, 9093 { "at90usb162", "__AVR_AT90USB162__" }, 9094 { "ata5505", "__AVR_ATA5505__" }, 9095 { "atmega8u2", "__AVR_ATmega8U2__" }, 9096 { "atmega16u2", "__AVR_ATmega16U2__" }, 9097 { "atmega32u2", "__AVR_ATmega32U2__" }, 9098 { "attiny1634", "__AVR_ATtiny1634__" }, 9099 { "atmega8", "__AVR_ATmega8__" }, 9100 { "ata6289", "__AVR_ATA6289__" }, 9101 { "atmega8a", "__AVR_ATmega8A__" }, 9102 { "ata6285", "__AVR_ATA6285__" }, 9103 { "ata6286", "__AVR_ATA6286__" }, 9104 { "atmega48", "__AVR_ATmega48__" }, 9105 { "atmega48a", "__AVR_ATmega48A__" }, 9106 { "atmega48pa", "__AVR_ATmega48PA__" }, 9107 { "atmega48p", "__AVR_ATmega48P__" }, 9108 { "atmega88", "__AVR_ATmega88__" }, 9109 { "atmega88a", "__AVR_ATmega88A__" }, 9110 { "atmega88p", "__AVR_ATmega88P__" }, 9111 { "atmega88pa", "__AVR_ATmega88PA__" }, 9112 { "atmega8515", "__AVR_ATmega8515__" }, 9113 { "atmega8535", "__AVR_ATmega8535__" }, 9114 { "atmega8hva", "__AVR_ATmega8HVA__" }, 9115 { "at90pwm1", "__AVR_AT90PWM1__" }, 9116 { "at90pwm2", "__AVR_AT90PWM2__" }, 9117 { "at90pwm2b", "__AVR_AT90PWM2B__" }, 9118 { "at90pwm3", "__AVR_AT90PWM3__" }, 9119 { "at90pwm3b", "__AVR_AT90PWM3B__" }, 9120 { "at90pwm81", "__AVR_AT90PWM81__" }, 9121 { "ata5790", "__AVR_ATA5790__" }, 9122 { "ata5795", "__AVR_ATA5795__" }, 9123 { "atmega16", "__AVR_ATmega16__" }, 9124 { "atmega16a", "__AVR_ATmega16A__" }, 9125 { "atmega161", "__AVR_ATmega161__" }, 9126 { "atmega162", "__AVR_ATmega162__" }, 9127 { "atmega163", "__AVR_ATmega163__" }, 9128 { "atmega164a", "__AVR_ATmega164A__" }, 9129 { "atmega164p", "__AVR_ATmega164P__" }, 9130 { "atmega164pa", "__AVR_ATmega164PA__" }, 9131 { "atmega165", "__AVR_ATmega165__" }, 9132 { "atmega165a", "__AVR_ATmega165A__" }, 9133 { "atmega165p", "__AVR_ATmega165P__" }, 9134 { "atmega165pa", "__AVR_ATmega165PA__" }, 9135 { "atmega168", "__AVR_ATmega168__" }, 9136 { "atmega168a", "__AVR_ATmega168A__" }, 9137 { "atmega168p", "__AVR_ATmega168P__" }, 9138 { "atmega168pa", "__AVR_ATmega168PA__" }, 9139 { "atmega169", "__AVR_ATmega169__" }, 9140 { "atmega169a", "__AVR_ATmega169A__" }, 9141 { "atmega169p", "__AVR_ATmega169P__" }, 9142 { "atmega169pa", "__AVR_ATmega169PA__" }, 9143 { "atmega32", "__AVR_ATmega32__" }, 9144 { "atmega32a", "__AVR_ATmega32A__" }, 9145 { "atmega323", "__AVR_ATmega323__" }, 9146 { "atmega324a", "__AVR_ATmega324A__" }, 9147 { "atmega324p", "__AVR_ATmega324P__" }, 9148 { "atmega324pa", "__AVR_ATmega324PA__" }, 9149 { "atmega325", "__AVR_ATmega325__" }, 9150 { "atmega325a", "__AVR_ATmega325A__" }, 9151 { "atmega325p", "__AVR_ATmega325P__" }, 9152 { "atmega325pa", "__AVR_ATmega325PA__" }, 9153 { "atmega3250", "__AVR_ATmega3250__" }, 9154 { "atmega3250a", "__AVR_ATmega3250A__" }, 9155 { "atmega3250p", "__AVR_ATmega3250P__" }, 9156 { "atmega3250pa", "__AVR_ATmega3250PA__" }, 9157 { "atmega328", "__AVR_ATmega328__" }, 9158 { "atmega328p", "__AVR_ATmega328P__" }, 9159 { "atmega329", "__AVR_ATmega329__" }, 9160 { "atmega329a", "__AVR_ATmega329A__" }, 9161 { "atmega329p", "__AVR_ATmega329P__" }, 9162 { "atmega329pa", "__AVR_ATmega329PA__" }, 9163 { "atmega3290", "__AVR_ATmega3290__" }, 9164 { "atmega3290a", "__AVR_ATmega3290A__" }, 9165 { "atmega3290p", "__AVR_ATmega3290P__" }, 9166 { "atmega3290pa", "__AVR_ATmega3290PA__" }, 9167 { "atmega406", "__AVR_ATmega406__" }, 9168 { "atmega64", "__AVR_ATmega64__" }, 9169 { "atmega64a", "__AVR_ATmega64A__" }, 9170 { "atmega640", "__AVR_ATmega640__" }, 9171 { "atmega644", "__AVR_ATmega644__" }, 9172 { "atmega644a", "__AVR_ATmega644A__" }, 9173 { "atmega644p", "__AVR_ATmega644P__" }, 9174 { "atmega644pa", "__AVR_ATmega644PA__" }, 9175 { "atmega645", "__AVR_ATmega645__" }, 9176 { "atmega645a", "__AVR_ATmega645A__" }, 9177 { "atmega645p", "__AVR_ATmega645P__" }, 9178 { "atmega649", "__AVR_ATmega649__" }, 9179 { "atmega649a", "__AVR_ATmega649A__" }, 9180 { "atmega649p", "__AVR_ATmega649P__" }, 9181 { "atmega6450", "__AVR_ATmega6450__" }, 9182 { "atmega6450a", "__AVR_ATmega6450A__" }, 9183 { "atmega6450p", "__AVR_ATmega6450P__" }, 9184 { "atmega6490", "__AVR_ATmega6490__" }, 9185 { "atmega6490a", "__AVR_ATmega6490A__" }, 9186 { "atmega6490p", "__AVR_ATmega6490P__" }, 9187 { "atmega64rfr2", "__AVR_ATmega64RFR2__" }, 9188 { "atmega644rfr2", "__AVR_ATmega644RFR2__" }, 9189 { "atmega16hva", "__AVR_ATmega16HVA__" }, 9190 { "atmega16hva2", "__AVR_ATmega16HVA2__" }, 9191 { "atmega16hvb", "__AVR_ATmega16HVB__" }, 9192 { "atmega16hvbrevb", "__AVR_ATmega16HVBREVB__" }, 9193 { "atmega32hvb", "__AVR_ATmega32HVB__" }, 9194 { "atmega32hvbrevb", "__AVR_ATmega32HVBREVB__" }, 9195 { "atmega64hve", "__AVR_ATmega64HVE__" }, 9196 { "at90can32", "__AVR_AT90CAN32__" }, 9197 { "at90can64", "__AVR_AT90CAN64__" }, 9198 { "at90pwm161", "__AVR_AT90PWM161__" }, 9199 { "at90pwm216", "__AVR_AT90PWM216__" }, 9200 { "at90pwm316", "__AVR_AT90PWM316__" }, 9201 { "atmega32c1", "__AVR_ATmega32C1__" }, 9202 { "atmega64c1", "__AVR_ATmega64C1__" }, 9203 { "atmega16m1", "__AVR_ATmega16M1__" }, 9204 { "atmega32m1", "__AVR_ATmega32M1__" }, 9205 { "atmega64m1", "__AVR_ATmega64M1__" }, 9206 { "atmega16u4", "__AVR_ATmega16U4__" }, 9207 { "atmega32u4", "__AVR_ATmega32U4__" }, 9208 { "atmega32u6", "__AVR_ATmega32U6__" }, 9209 { "at90usb646", "__AVR_AT90USB646__" }, 9210 { "at90usb647", "__AVR_AT90USB647__" }, 9211 { "at90scr100", "__AVR_AT90SCR100__" }, 9212 { "at94k", "__AVR_AT94K__" }, 9213 { "m3000", "__AVR_AT000__" }, 9214 { "atmega128", "__AVR_ATmega128__" }, 9215 { "atmega128a", "__AVR_ATmega128A__" }, 9216 { "atmega1280", "__AVR_ATmega1280__" }, 9217 { "atmega1281", "__AVR_ATmega1281__" }, 9218 { "atmega1284", "__AVR_ATmega1284__" }, 9219 { "atmega1284p", "__AVR_ATmega1284P__" }, 9220 { "atmega128rfa1", "__AVR_ATmega128RFA1__" }, 9221 { "atmega128rfr2", "__AVR_ATmega128RFR2__" }, 9222 { "atmega1284rfr2", "__AVR_ATmega1284RFR2__" }, 9223 { "at90can128", "__AVR_AT90CAN128__" }, 9224 { "at90usb1286", "__AVR_AT90USB1286__" }, 9225 { "at90usb1287", "__AVR_AT90USB1287__" }, 9226 { "atmega2560", "__AVR_ATmega2560__" }, 9227 { "atmega2561", "__AVR_ATmega2561__" }, 9228 { "atmega256rfr2", "__AVR_ATmega256RFR2__" }, 9229 { "atmega2564rfr2", "__AVR_ATmega2564RFR2__" }, 9230 { "atxmega16a4", "__AVR_ATxmega16A4__" }, 9231 { "atxmega16a4u", "__AVR_ATxmega16a4U__" }, 9232 { "atxmega16c4", "__AVR_ATxmega16C4__" }, 9233 { "atxmega16d4", "__AVR_ATxmega16D4__" }, 9234 { "atxmega32a4", "__AVR_ATxmega32A4__" }, 9235 { "atxmega32a4u", "__AVR_ATxmega32A4U__" }, 9236 { "atxmega32c4", "__AVR_ATxmega32C4__" }, 9237 { "atxmega32d4", "__AVR_ATxmega32D4__" }, 9238 { "atxmega32e5", "__AVR_ATxmega32E5__" }, 9239 { "atxmega16e5", "__AVR_ATxmega16E5__" }, 9240 { "atxmega8e5", "__AVR_ATxmega8E5__" }, 9241 { "atxmega32x1", "__AVR_ATxmega32X1__" }, 9242 { "atxmega64a3", "__AVR_ATxmega64A3__" }, 9243 { "atxmega64a3u", "__AVR_ATxmega64A3U__" }, 9244 { "atxmega64a4u", "__AVR_ATxmega64A4U__" }, 9245 { "atxmega64b1", "__AVR_ATxmega64B1__" }, 9246 { "atxmega64b3", "__AVR_ATxmega64B3__" }, 9247 { "atxmega64c3", "__AVR_ATxmega64C3__" }, 9248 { "atxmega64d3", "__AVR_ATxmega64D3__" }, 9249 { "atxmega64d4", "__AVR_ATxmega64D4__" }, 9250 { "atxmega64a1", "__AVR_ATxmega64A1__" }, 9251 { "atxmega64a1u", "__AVR_ATxmega64A1U__" }, 9252 { "atxmega128a3", "__AVR_ATxmega128A3__" }, 9253 { "atxmega128a3u", "__AVR_ATxmega128A3U__" }, 9254 { "atxmega128b1", "__AVR_ATxmega128B1__" }, 9255 { "atxmega128b3", "__AVR_ATxmega128B3__" }, 9256 { "atxmega128c3", "__AVR_ATxmega128C3__" }, 9257 { "atxmega128d3", "__AVR_ATxmega128D3__" }, 9258 { "atxmega128d4", "__AVR_ATxmega128D4__" }, 9259 { "atxmega192a3", "__AVR_ATxmega192A3__" }, 9260 { "atxmega192a3u", "__AVR_ATxmega192A3U__" }, 9261 { "atxmega192c3", "__AVR_ATxmega192C3__" }, 9262 { "atxmega192d3", "__AVR_ATxmega192D3__" }, 9263 { "atxmega256a3", "__AVR_ATxmega256A3__" }, 9264 { "atxmega256a3u", "__AVR_ATxmega256A3U__" }, 9265 { "atxmega256a3b", "__AVR_ATxmega256A3B__" }, 9266 { "atxmega256a3bu", "__AVR_ATxmega256A3BU__" }, 9267 { "atxmega256c3", "__AVR_ATxmega256C3__" }, 9268 { "atxmega256d3", "__AVR_ATxmega256D3__" }, 9269 { "atxmega384c3", "__AVR_ATxmega384C3__" }, 9270 { "atxmega384d3", "__AVR_ATxmega384D3__" }, 9271 { "atxmega128a1", "__AVR_ATxmega128A1__" }, 9272 { "atxmega128a1u", "__AVR_ATxmega128A1U__" }, 9273 { "atxmega128a4u", "__AVR_ATxmega128a4U__" }, 9274 { "attiny4", "__AVR_ATtiny4__" }, 9275 { "attiny5", "__AVR_ATtiny5__" }, 9276 { "attiny9", "__AVR_ATtiny9__" }, 9277 { "attiny10", "__AVR_ATtiny10__" }, 9278 { "attiny20", "__AVR_ATtiny20__" }, 9279 { "attiny40", "__AVR_ATtiny40__" }, 9280 { "attiny102", "__AVR_ATtiny102__" }, 9281 { "attiny104", "__AVR_ATtiny104__" }, 9282 }; 9283 9284 // AVR Target 9285 class AVRTargetInfo : public TargetInfo { 9286 public: 9287 AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 9288 : TargetInfo(Triple) { 9289 TLSSupported = false; 9290 PointerWidth = 16; 9291 PointerAlign = 8; 9292 IntWidth = 16; 9293 IntAlign = 8; 9294 LongWidth = 32; 9295 LongAlign = 8; 9296 LongLongWidth = 64; 9297 LongLongAlign = 8; 9298 SuitableAlign = 8; 9299 DefaultAlignForAttributeAligned = 8; 9300 HalfWidth = 16; 9301 HalfAlign = 8; 9302 FloatWidth = 32; 9303 FloatAlign = 8; 9304 DoubleWidth = 32; 9305 DoubleAlign = 8; 9306 DoubleFormat = &llvm::APFloat::IEEEsingle(); 9307 LongDoubleWidth = 32; 9308 LongDoubleAlign = 8; 9309 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 9310 SizeType = UnsignedInt; 9311 PtrDiffType = SignedInt; 9312 IntPtrType = SignedInt; 9313 Char16Type = UnsignedInt; 9314 WCharType = SignedInt; 9315 WIntType = SignedInt; 9316 Char32Type = UnsignedLong; 9317 SigAtomicType = SignedChar; 9318 resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64" 9319 "-f32:32:32-f64:64:64-n8"); 9320 } 9321 9322 void getTargetDefines(const LangOptions &Opts, 9323 MacroBuilder &Builder) const override { 9324 Builder.defineMacro("AVR"); 9325 Builder.defineMacro("__AVR"); 9326 Builder.defineMacro("__AVR__"); 9327 9328 if (!this->CPU.empty()) { 9329 auto It = std::find_if(AVRMcus.begin(), AVRMcus.end(), 9330 [&](const MCUInfo &Info) { return Info.Name == this->CPU; }); 9331 9332 if (It != AVRMcus.end()) 9333 Builder.defineMacro(It->DefineName); 9334 } 9335 } 9336 9337 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 9338 return None; 9339 } 9340 9341 BuiltinVaListKind getBuiltinVaListKind() const override { 9342 return TargetInfo::VoidPtrBuiltinVaList; 9343 } 9344 9345 const char *getClobbers() const override { 9346 return ""; 9347 } 9348 9349 ArrayRef<const char *> getGCCRegNames() const override { 9350 static const char * const GCCRegNames[] = { 9351 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 9352 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 9353 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 9354 "r24", "r25", "X", "Y", "Z", "SP" 9355 }; 9356 return llvm::makeArrayRef(GCCRegNames); 9357 } 9358 9359 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 9360 return None; 9361 } 9362 9363 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 9364 static const TargetInfo::AddlRegName AddlRegNames[] = { 9365 { { "r26", "r27"}, 26 }, 9366 { { "r28", "r29"}, 27 }, 9367 { { "r30", "r31"}, 28 }, 9368 { { "SPL", "SPH"}, 29 }, 9369 }; 9370 return llvm::makeArrayRef(AddlRegNames); 9371 } 9372 9373 bool validateAsmConstraint(const char *&Name, 9374 TargetInfo::ConstraintInfo &Info) const override { 9375 // There aren't any multi-character AVR specific constraints. 9376 if (StringRef(Name).size() > 1) return false; 9377 9378 switch (*Name) { 9379 default: return false; 9380 case 'a': // Simple upper registers 9381 case 'b': // Base pointer registers pairs 9382 case 'd': // Upper register 9383 case 'l': // Lower registers 9384 case 'e': // Pointer register pairs 9385 case 'q': // Stack pointer register 9386 case 'r': // Any register 9387 case 'w': // Special upper register pairs 9388 case 't': // Temporary register 9389 case 'x': case 'X': // Pointer register pair X 9390 case 'y': case 'Y': // Pointer register pair Y 9391 case 'z': case 'Z': // Pointer register pair Z 9392 Info.setAllowsRegister(); 9393 return true; 9394 case 'I': // 6-bit positive integer constant 9395 Info.setRequiresImmediate(0, 63); 9396 return true; 9397 case 'J': // 6-bit negative integer constant 9398 Info.setRequiresImmediate(-63, 0); 9399 return true; 9400 case 'K': // Integer constant (Range: 2) 9401 Info.setRequiresImmediate(2); 9402 return true; 9403 case 'L': // Integer constant (Range: 0) 9404 Info.setRequiresImmediate(0); 9405 return true; 9406 case 'M': // 8-bit integer constant 9407 Info.setRequiresImmediate(0, 0xff); 9408 return true; 9409 case 'N': // Integer constant (Range: -1) 9410 Info.setRequiresImmediate(-1); 9411 return true; 9412 case 'O': // Integer constant (Range: 8, 16, 24) 9413 Info.setRequiresImmediate({8, 16, 24}); 9414 return true; 9415 case 'P': // Integer constant (Range: 1) 9416 Info.setRequiresImmediate(1); 9417 return true; 9418 case 'R': // Integer constant (Range: -6 to 5) 9419 Info.setRequiresImmediate(-6, 5); 9420 return true; 9421 case 'G': // Floating point constant 9422 case 'Q': // A memory address based on Y or Z pointer with displacement. 9423 return true; 9424 } 9425 9426 return false; 9427 } 9428 9429 IntType getIntTypeByWidth(unsigned BitWidth, 9430 bool IsSigned) const final { 9431 // AVR prefers int for 16-bit integers. 9432 return BitWidth == 16 ? (IsSigned ? SignedInt : UnsignedInt) 9433 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 9434 } 9435 9436 IntType getLeastIntTypeByWidth(unsigned BitWidth, 9437 bool IsSigned) const final { 9438 // AVR uses int for int_least16_t and int_fast16_t. 9439 return BitWidth == 16 9440 ? (IsSigned ? SignedInt : UnsignedInt) 9441 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 9442 } 9443 9444 bool setCPU(const std::string &Name) override { 9445 bool IsFamily = llvm::StringSwitch<bool>(Name) 9446 .Case("avr1", true) 9447 .Case("avr2", true) 9448 .Case("avr25", true) 9449 .Case("avr3", true) 9450 .Case("avr31", true) 9451 .Case("avr35", true) 9452 .Case("avr4", true) 9453 .Case("avr5", true) 9454 .Case("avr51", true) 9455 .Case("avr6", true) 9456 .Case("avrxmega1", true) 9457 .Case("avrxmega2", true) 9458 .Case("avrxmega3", true) 9459 .Case("avrxmega4", true) 9460 .Case("avrxmega5", true) 9461 .Case("avrxmega6", true) 9462 .Case("avrxmega7", true) 9463 .Case("avrtiny", true) 9464 .Default(false); 9465 9466 if (IsFamily) this->CPU = Name; 9467 9468 bool IsMCU = std::find_if(AVRMcus.begin(), AVRMcus.end(), 9469 [&](const MCUInfo &Info) { return Info.Name == Name; }) != AVRMcus.end(); 9470 9471 if (IsMCU) this->CPU = Name; 9472 9473 return IsFamily || IsMCU; 9474 } 9475 9476 protected: 9477 std::string CPU; 9478 }; 9479 9480 } // end anonymous namespace 9481 9482 //===----------------------------------------------------------------------===// 9483 // Driver code 9484 //===----------------------------------------------------------------------===// 9485 9486 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 9487 const TargetOptions &Opts) { 9488 llvm::Triple::OSType os = Triple.getOS(); 9489 9490 switch (Triple.getArch()) { 9491 default: 9492 return nullptr; 9493 9494 case llvm::Triple::xcore: 9495 return new XCoreTargetInfo(Triple, Opts); 9496 9497 case llvm::Triple::hexagon: 9498 return new HexagonTargetInfo(Triple, Opts); 9499 9500 case llvm::Triple::lanai: 9501 return new LanaiTargetInfo(Triple, Opts); 9502 9503 case llvm::Triple::aarch64: 9504 if (Triple.isOSDarwin()) 9505 return new DarwinAArch64TargetInfo(Triple, Opts); 9506 9507 switch (os) { 9508 case llvm::Triple::CloudABI: 9509 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 9510 case llvm::Triple::FreeBSD: 9511 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9512 case llvm::Triple::Fuchsia: 9513 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9514 case llvm::Triple::Linux: 9515 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9516 case llvm::Triple::NetBSD: 9517 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9518 case llvm::Triple::OpenBSD: 9519 return new OpenBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9520 case llvm::Triple::Win32: 9521 return new MicrosoftARM64TargetInfo(Triple, Opts); 9522 default: 9523 return new AArch64leTargetInfo(Triple, Opts); 9524 } 9525 9526 case llvm::Triple::aarch64_be: 9527 switch (os) { 9528 case llvm::Triple::FreeBSD: 9529 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9530 case llvm::Triple::Fuchsia: 9531 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9532 case llvm::Triple::Linux: 9533 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9534 case llvm::Triple::NetBSD: 9535 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9536 default: 9537 return new AArch64beTargetInfo(Triple, Opts); 9538 } 9539 9540 case llvm::Triple::arm: 9541 case llvm::Triple::thumb: 9542 if (Triple.isOSBinFormatMachO()) 9543 return new DarwinARMTargetInfo(Triple, Opts); 9544 9545 switch (os) { 9546 case llvm::Triple::CloudABI: 9547 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts); 9548 case llvm::Triple::Linux: 9549 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 9550 case llvm::Triple::FreeBSD: 9551 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9552 case llvm::Triple::NetBSD: 9553 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9554 case llvm::Triple::OpenBSD: 9555 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9556 case llvm::Triple::Bitrig: 9557 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 9558 case llvm::Triple::RTEMS: 9559 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 9560 case llvm::Triple::NaCl: 9561 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 9562 case llvm::Triple::Win32: 9563 switch (Triple.getEnvironment()) { 9564 case llvm::Triple::Cygnus: 9565 return new CygwinARMTargetInfo(Triple, Opts); 9566 case llvm::Triple::GNU: 9567 return new MinGWARMTargetInfo(Triple, Opts); 9568 case llvm::Triple::Itanium: 9569 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 9570 case llvm::Triple::MSVC: 9571 default: // Assume MSVC for unknown environments 9572 return new MicrosoftARMleTargetInfo(Triple, Opts); 9573 } 9574 default: 9575 return new ARMleTargetInfo(Triple, Opts); 9576 } 9577 9578 case llvm::Triple::armeb: 9579 case llvm::Triple::thumbeb: 9580 if (Triple.isOSDarwin()) 9581 return new DarwinARMTargetInfo(Triple, Opts); 9582 9583 switch (os) { 9584 case llvm::Triple::Linux: 9585 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9586 case llvm::Triple::FreeBSD: 9587 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9588 case llvm::Triple::NetBSD: 9589 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9590 case llvm::Triple::OpenBSD: 9591 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9592 case llvm::Triple::Bitrig: 9593 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9594 case llvm::Triple::RTEMS: 9595 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9596 case llvm::Triple::NaCl: 9597 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9598 default: 9599 return new ARMbeTargetInfo(Triple, Opts); 9600 } 9601 9602 case llvm::Triple::avr: 9603 return new AVRTargetInfo(Triple, Opts); 9604 case llvm::Triple::bpfeb: 9605 case llvm::Triple::bpfel: 9606 return new BPFTargetInfo(Triple, Opts); 9607 9608 case llvm::Triple::msp430: 9609 return new MSP430TargetInfo(Triple, Opts); 9610 9611 case llvm::Triple::nios2: 9612 return new LinuxTargetInfo<Nios2TargetInfo>(Triple, Opts); 9613 9614 case llvm::Triple::mips: 9615 switch (os) { 9616 case llvm::Triple::Linux: 9617 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9618 case llvm::Triple::RTEMS: 9619 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9620 case llvm::Triple::FreeBSD: 9621 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9622 case llvm::Triple::NetBSD: 9623 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9624 default: 9625 return new MipsTargetInfo(Triple, Opts); 9626 } 9627 9628 case llvm::Triple::mipsel: 9629 switch (os) { 9630 case llvm::Triple::Linux: 9631 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9632 case llvm::Triple::RTEMS: 9633 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9634 case llvm::Triple::FreeBSD: 9635 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9636 case llvm::Triple::NetBSD: 9637 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9638 case llvm::Triple::NaCl: 9639 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 9640 default: 9641 return new MipsTargetInfo(Triple, Opts); 9642 } 9643 9644 case llvm::Triple::mips64: 9645 switch (os) { 9646 case llvm::Triple::Linux: 9647 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9648 case llvm::Triple::RTEMS: 9649 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9650 case llvm::Triple::FreeBSD: 9651 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9652 case llvm::Triple::NetBSD: 9653 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9654 case llvm::Triple::OpenBSD: 9655 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9656 default: 9657 return new MipsTargetInfo(Triple, Opts); 9658 } 9659 9660 case llvm::Triple::mips64el: 9661 switch (os) { 9662 case llvm::Triple::Linux: 9663 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9664 case llvm::Triple::RTEMS: 9665 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9666 case llvm::Triple::FreeBSD: 9667 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9668 case llvm::Triple::NetBSD: 9669 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9670 case llvm::Triple::OpenBSD: 9671 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9672 default: 9673 return new MipsTargetInfo(Triple, Opts); 9674 } 9675 9676 case llvm::Triple::le32: 9677 switch (os) { 9678 case llvm::Triple::NaCl: 9679 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 9680 default: 9681 return nullptr; 9682 } 9683 9684 case llvm::Triple::le64: 9685 return new Le64TargetInfo(Triple, Opts); 9686 9687 case llvm::Triple::ppc: 9688 if (Triple.isOSDarwin()) 9689 return new DarwinPPC32TargetInfo(Triple, Opts); 9690 switch (os) { 9691 case llvm::Triple::Linux: 9692 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 9693 case llvm::Triple::FreeBSD: 9694 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9695 case llvm::Triple::NetBSD: 9696 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9697 case llvm::Triple::OpenBSD: 9698 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9699 case llvm::Triple::RTEMS: 9700 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 9701 default: 9702 return new PPC32TargetInfo(Triple, Opts); 9703 } 9704 9705 case llvm::Triple::ppc64: 9706 if (Triple.isOSDarwin()) 9707 return new DarwinPPC64TargetInfo(Triple, Opts); 9708 switch (os) { 9709 case llvm::Triple::Linux: 9710 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9711 case llvm::Triple::Lv2: 9712 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 9713 case llvm::Triple::FreeBSD: 9714 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9715 case llvm::Triple::NetBSD: 9716 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9717 default: 9718 return new PPC64TargetInfo(Triple, Opts); 9719 } 9720 9721 case llvm::Triple::ppc64le: 9722 switch (os) { 9723 case llvm::Triple::Linux: 9724 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9725 case llvm::Triple::NetBSD: 9726 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9727 default: 9728 return new PPC64TargetInfo(Triple, Opts); 9729 } 9730 9731 case llvm::Triple::nvptx: 9732 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/32); 9733 case llvm::Triple::nvptx64: 9734 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64); 9735 9736 case llvm::Triple::amdgcn: 9737 case llvm::Triple::r600: 9738 return new AMDGPUTargetInfo(Triple, Opts); 9739 9740 case llvm::Triple::sparc: 9741 switch (os) { 9742 case llvm::Triple::Linux: 9743 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9744 case llvm::Triple::Solaris: 9745 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9746 case llvm::Triple::NetBSD: 9747 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9748 case llvm::Triple::OpenBSD: 9749 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9750 case llvm::Triple::RTEMS: 9751 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9752 default: 9753 return new SparcV8TargetInfo(Triple, Opts); 9754 } 9755 9756 // The 'sparcel' architecture copies all the above cases except for Solaris. 9757 case llvm::Triple::sparcel: 9758 switch (os) { 9759 case llvm::Triple::Linux: 9760 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9761 case llvm::Triple::NetBSD: 9762 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9763 case llvm::Triple::OpenBSD: 9764 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9765 case llvm::Triple::RTEMS: 9766 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9767 default: 9768 return new SparcV8elTargetInfo(Triple, Opts); 9769 } 9770 9771 case llvm::Triple::sparcv9: 9772 switch (os) { 9773 case llvm::Triple::Linux: 9774 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9775 case llvm::Triple::Solaris: 9776 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9777 case llvm::Triple::NetBSD: 9778 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9779 case llvm::Triple::OpenBSD: 9780 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9781 case llvm::Triple::FreeBSD: 9782 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9783 default: 9784 return new SparcV9TargetInfo(Triple, Opts); 9785 } 9786 9787 case llvm::Triple::systemz: 9788 switch (os) { 9789 case llvm::Triple::Linux: 9790 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 9791 default: 9792 return new SystemZTargetInfo(Triple, Opts); 9793 } 9794 9795 case llvm::Triple::tce: 9796 return new TCETargetInfo(Triple, Opts); 9797 9798 case llvm::Triple::tcele: 9799 return new TCELETargetInfo(Triple, Opts); 9800 9801 case llvm::Triple::x86: 9802 if (Triple.isOSDarwin()) 9803 return new DarwinI386TargetInfo(Triple, Opts); 9804 9805 switch (os) { 9806 case llvm::Triple::Ananas: 9807 return new AnanasTargetInfo<X86_32TargetInfo>(Triple, Opts); 9808 case llvm::Triple::CloudABI: 9809 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 9810 case llvm::Triple::Linux: { 9811 switch (Triple.getEnvironment()) { 9812 default: 9813 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 9814 case llvm::Triple::Android: 9815 return new AndroidX86_32TargetInfo(Triple, Opts); 9816 } 9817 } 9818 case llvm::Triple::DragonFly: 9819 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9820 case llvm::Triple::NetBSD: 9821 return new NetBSDI386TargetInfo(Triple, Opts); 9822 case llvm::Triple::OpenBSD: 9823 return new OpenBSDI386TargetInfo(Triple, Opts); 9824 case llvm::Triple::Bitrig: 9825 return new BitrigI386TargetInfo(Triple, Opts); 9826 case llvm::Triple::FreeBSD: 9827 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9828 case llvm::Triple::KFreeBSD: 9829 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9830 case llvm::Triple::Minix: 9831 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 9832 case llvm::Triple::Solaris: 9833 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 9834 case llvm::Triple::Win32: { 9835 switch (Triple.getEnvironment()) { 9836 case llvm::Triple::Cygnus: 9837 return new CygwinX86_32TargetInfo(Triple, Opts); 9838 case llvm::Triple::GNU: 9839 return new MinGWX86_32TargetInfo(Triple, Opts); 9840 case llvm::Triple::Itanium: 9841 case llvm::Triple::MSVC: 9842 default: // Assume MSVC for unknown environments 9843 return new MicrosoftX86_32TargetInfo(Triple, Opts); 9844 } 9845 } 9846 case llvm::Triple::Haiku: 9847 return new HaikuX86_32TargetInfo(Triple, Opts); 9848 case llvm::Triple::RTEMS: 9849 return new RTEMSX86_32TargetInfo(Triple, Opts); 9850 case llvm::Triple::NaCl: 9851 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 9852 case llvm::Triple::ELFIAMCU: 9853 return new MCUX86_32TargetInfo(Triple, Opts); 9854 default: 9855 return new X86_32TargetInfo(Triple, Opts); 9856 } 9857 9858 case llvm::Triple::x86_64: 9859 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 9860 return new DarwinX86_64TargetInfo(Triple, Opts); 9861 9862 switch (os) { 9863 case llvm::Triple::Ananas: 9864 return new AnanasTargetInfo<X86_64TargetInfo>(Triple, Opts); 9865 case llvm::Triple::CloudABI: 9866 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 9867 case llvm::Triple::Linux: { 9868 switch (Triple.getEnvironment()) { 9869 default: 9870 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 9871 case llvm::Triple::Android: 9872 return new AndroidX86_64TargetInfo(Triple, Opts); 9873 } 9874 } 9875 case llvm::Triple::DragonFly: 9876 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9877 case llvm::Triple::NetBSD: 9878 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9879 case llvm::Triple::OpenBSD: 9880 return new OpenBSDX86_64TargetInfo(Triple, Opts); 9881 case llvm::Triple::Bitrig: 9882 return new BitrigX86_64TargetInfo(Triple, Opts); 9883 case llvm::Triple::FreeBSD: 9884 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9885 case llvm::Triple::Fuchsia: 9886 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts); 9887 case llvm::Triple::KFreeBSD: 9888 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9889 case llvm::Triple::Solaris: 9890 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 9891 case llvm::Triple::Win32: { 9892 switch (Triple.getEnvironment()) { 9893 case llvm::Triple::Cygnus: 9894 return new CygwinX86_64TargetInfo(Triple, Opts); 9895 case llvm::Triple::GNU: 9896 return new MinGWX86_64TargetInfo(Triple, Opts); 9897 case llvm::Triple::MSVC: 9898 default: // Assume MSVC for unknown environments 9899 return new MicrosoftX86_64TargetInfo(Triple, Opts); 9900 } 9901 } 9902 case llvm::Triple::Haiku: 9903 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 9904 case llvm::Triple::NaCl: 9905 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 9906 case llvm::Triple::PS4: 9907 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 9908 default: 9909 return new X86_64TargetInfo(Triple, Opts); 9910 } 9911 9912 case llvm::Triple::spir: { 9913 if (Triple.getOS() != llvm::Triple::UnknownOS || 9914 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9915 return nullptr; 9916 return new SPIR32TargetInfo(Triple, Opts); 9917 } 9918 case llvm::Triple::spir64: { 9919 if (Triple.getOS() != llvm::Triple::UnknownOS || 9920 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9921 return nullptr; 9922 return new SPIR64TargetInfo(Triple, Opts); 9923 } 9924 case llvm::Triple::wasm32: 9925 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9926 Triple.getVendor() != llvm::Triple::UnknownVendor || 9927 Triple.getOS() != llvm::Triple::UnknownOS || 9928 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9929 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9930 return nullptr; 9931 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 9932 case llvm::Triple::wasm64: 9933 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9934 Triple.getVendor() != llvm::Triple::UnknownVendor || 9935 Triple.getOS() != llvm::Triple::UnknownOS || 9936 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9937 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9938 return nullptr; 9939 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 9940 9941 case llvm::Triple::renderscript32: 9942 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 9943 case llvm::Triple::renderscript64: 9944 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 9945 } 9946 } 9947 9948 /// CreateTargetInfo - Return the target info object for the specified target 9949 /// options. 9950 TargetInfo * 9951 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 9952 const std::shared_ptr<TargetOptions> &Opts) { 9953 llvm::Triple Triple(Opts->Triple); 9954 9955 // Construct the target 9956 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 9957 if (!Target) { 9958 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 9959 return nullptr; 9960 } 9961 Target->TargetOpts = Opts; 9962 9963 // Set the target CPU if specified. 9964 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 9965 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 9966 return nullptr; 9967 } 9968 9969 // Set the target ABI if specified. 9970 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 9971 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 9972 return nullptr; 9973 } 9974 9975 // Set the fp math unit. 9976 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 9977 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 9978 return nullptr; 9979 } 9980 9981 // Compute the default target features, we need the target to handle this 9982 // because features may have dependencies on one another. 9983 llvm::StringMap<bool> Features; 9984 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 9985 Opts->FeaturesAsWritten)) 9986 return nullptr; 9987 9988 // Add the features to the compile options. 9989 Opts->Features.clear(); 9990 for (const auto &F : Features) 9991 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 9992 9993 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 9994 return nullptr; 9995 9996 Target->setSupportedOpenCLOpts(); 9997 Target->setOpenCLExtensionOpts(); 9998 9999 if (!Target->validateTarget(Diags)) 10000 return nullptr; 10001 10002 return Target.release(); 10003 } 10004