1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 115 const llvm::Triple &Triple, 116 StringRef &PlatformName, 117 VersionTuple &PlatformMinVersion) { 118 Builder.defineMacro("__APPLE_CC__", "6000"); 119 Builder.defineMacro("__APPLE__"); 120 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 121 // AddressSanitizer doesn't play well with source fortification, which is on 122 // by default on Darwin. 123 if (Opts.Sanitize.has(SanitizerKind::Address)) 124 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 125 126 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 127 if (!Opts.ObjC1) { 128 // __weak is always defined, for use in blocks and with objc pointers. 129 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 130 Builder.defineMacro("__strong", ""); 131 Builder.defineMacro("__unsafe_unretained", ""); 132 } 133 134 if (Opts.Static) 135 Builder.defineMacro("__STATIC__"); 136 else 137 Builder.defineMacro("__DYNAMIC__"); 138 139 if (Opts.POSIXThreads) 140 Builder.defineMacro("_REENTRANT"); 141 142 // Get the platform type and version number from the triple. 143 unsigned Maj, Min, Rev; 144 if (Triple.isMacOSX()) { 145 Triple.getMacOSXVersion(Maj, Min, Rev); 146 PlatformName = "macos"; 147 } else { 148 Triple.getOSVersion(Maj, Min, Rev); 149 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 150 } 151 152 // If -target arch-pc-win32-macho option specified, we're 153 // generating code for Win32 ABI. No need to emit 154 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 155 if (PlatformName == "win32") { 156 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 157 return; 158 } 159 160 // Set the appropriate OS version define. 161 if (Triple.isiOS()) { 162 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 163 char Str[7]; 164 if (Maj < 10) { 165 Str[0] = '0' + Maj; 166 Str[1] = '0' + (Min / 10); 167 Str[2] = '0' + (Min % 10); 168 Str[3] = '0' + (Rev / 10); 169 Str[4] = '0' + (Rev % 10); 170 Str[5] = '\0'; 171 } else { 172 // Handle versions >= 10. 173 Str[0] = '0' + (Maj / 10); 174 Str[1] = '0' + (Maj % 10); 175 Str[2] = '0' + (Min / 10); 176 Str[3] = '0' + (Min % 10); 177 Str[4] = '0' + (Rev / 10); 178 Str[5] = '0' + (Rev % 10); 179 Str[6] = '\0'; 180 } 181 if (Triple.isTvOS()) 182 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 183 else 184 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 185 Str); 186 187 } else if (Triple.isWatchOS()) { 188 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 189 char Str[6]; 190 Str[0] = '0' + Maj; 191 Str[1] = '0' + (Min / 10); 192 Str[2] = '0' + (Min % 10); 193 Str[3] = '0' + (Rev / 10); 194 Str[4] = '0' + (Rev % 10); 195 Str[5] = '\0'; 196 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 197 } else if (Triple.isMacOSX()) { 198 // Note that the Driver allows versions which aren't representable in the 199 // define (because we only get a single digit for the minor and micro 200 // revision numbers). So, we limit them to the maximum representable 201 // version. 202 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 203 char Str[7]; 204 if (Maj < 10 || (Maj == 10 && Min < 10)) { 205 Str[0] = '0' + (Maj / 10); 206 Str[1] = '0' + (Maj % 10); 207 Str[2] = '0' + std::min(Min, 9U); 208 Str[3] = '0' + std::min(Rev, 9U); 209 Str[4] = '\0'; 210 } else { 211 // Handle versions > 10.9. 212 Str[0] = '0' + (Maj / 10); 213 Str[1] = '0' + (Maj % 10); 214 Str[2] = '0' + (Min / 10); 215 Str[3] = '0' + (Min % 10); 216 Str[4] = '0' + (Rev / 10); 217 Str[5] = '0' + (Rev % 10); 218 Str[6] = '\0'; 219 } 220 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 221 } 222 223 // Tell users about the kernel if there is one. 224 if (Triple.isOSDarwin()) 225 Builder.defineMacro("__MACH__"); 226 227 // The Watch ABI uses Dwarf EH. 228 if(Triple.isWatchABI()) 229 Builder.defineMacro("__ARM_DWARF_EH__"); 230 231 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 232 } 233 234 template<typename Target> 235 class DarwinTargetInfo : public OSTargetInfo<Target> { 236 protected: 237 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 238 MacroBuilder &Builder) const override { 239 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 240 this->PlatformMinVersion); 241 } 242 243 public: 244 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 245 : OSTargetInfo<Target>(Triple, Opts) { 246 // By default, no TLS, and we whitelist permitted architecture/OS 247 // combinations. 248 this->TLSSupported = false; 249 250 if (Triple.isMacOSX()) 251 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 252 else if (Triple.isiOS()) { 253 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 254 if (Triple.getArch() == llvm::Triple::x86_64 || 255 Triple.getArch() == llvm::Triple::aarch64) 256 this->TLSSupported = !Triple.isOSVersionLT(8); 257 else if (Triple.getArch() == llvm::Triple::x86 || 258 Triple.getArch() == llvm::Triple::arm || 259 Triple.getArch() == llvm::Triple::thumb) 260 this->TLSSupported = !Triple.isOSVersionLT(9); 261 } else if (Triple.isWatchOS()) 262 this->TLSSupported = !Triple.isOSVersionLT(2); 263 264 this->MCountName = "\01mcount"; 265 } 266 267 std::string isValidSectionSpecifier(StringRef SR) const override { 268 // Let MCSectionMachO validate this. 269 StringRef Segment, Section; 270 unsigned TAA, StubSize; 271 bool HasTAA; 272 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 273 TAA, HasTAA, StubSize); 274 } 275 276 const char *getStaticInitSectionSpecifier() const override { 277 // FIXME: We should return 0 when building kexts. 278 return "__TEXT,__StaticInit,regular,pure_instructions"; 279 } 280 281 /// Darwin does not support protected visibility. Darwin's "default" 282 /// is very similar to ELF's "protected"; Darwin requires a "weak" 283 /// attribute on declarations that can be dynamically replaced. 284 bool hasProtectedVisibility() const override { 285 return false; 286 } 287 288 unsigned getExnObjectAlignment() const override { 289 // The alignment of an exception object is 8-bytes for darwin since 290 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 291 // and therefore doesn't guarantee 16-byte alignment. 292 return 64; 293 } 294 }; 295 296 297 // DragonFlyBSD Target 298 template<typename Target> 299 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 300 protected: 301 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 302 MacroBuilder &Builder) const override { 303 // DragonFly defines; list based off of gcc output 304 Builder.defineMacro("__DragonFly__"); 305 Builder.defineMacro("__DragonFly_cc_version", "100001"); 306 Builder.defineMacro("__ELF__"); 307 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 308 Builder.defineMacro("__tune_i386__"); 309 DefineStd(Builder, "unix", Opts); 310 } 311 public: 312 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 313 : OSTargetInfo<Target>(Triple, Opts) { 314 switch (Triple.getArch()) { 315 default: 316 case llvm::Triple::x86: 317 case llvm::Triple::x86_64: 318 this->MCountName = ".mcount"; 319 break; 320 } 321 } 322 }; 323 324 #ifndef FREEBSD_CC_VERSION 325 #define FREEBSD_CC_VERSION 0U 326 #endif 327 328 // FreeBSD Target 329 template<typename Target> 330 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 331 protected: 332 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 333 MacroBuilder &Builder) const override { 334 // FreeBSD defines; list based off of gcc output 335 336 unsigned Release = Triple.getOSMajorVersion(); 337 if (Release == 0U) 338 Release = 8U; 339 unsigned CCVersion = FREEBSD_CC_VERSION; 340 if (CCVersion == 0U) 341 CCVersion = Release * 100000U + 1U; 342 343 Builder.defineMacro("__FreeBSD__", Twine(Release)); 344 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 345 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 346 DefineStd(Builder, "unix", Opts); 347 Builder.defineMacro("__ELF__"); 348 349 // On FreeBSD, wchar_t contains the number of the code point as 350 // used by the character set of the locale. These character sets are 351 // not necessarily a superset of ASCII. 352 // 353 // FIXME: This is wrong; the macro refers to the numerical values 354 // of wchar_t *literals*, which are not locale-dependent. However, 355 // FreeBSD systems apparently depend on us getting this wrong, and 356 // setting this to 1 is conforming even if all the basic source 357 // character literals have the same encoding as char and wchar_t. 358 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 359 } 360 public: 361 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 362 : OSTargetInfo<Target>(Triple, Opts) { 363 switch (Triple.getArch()) { 364 default: 365 case llvm::Triple::x86: 366 case llvm::Triple::x86_64: 367 this->MCountName = ".mcount"; 368 break; 369 case llvm::Triple::mips: 370 case llvm::Triple::mipsel: 371 case llvm::Triple::ppc: 372 case llvm::Triple::ppc64: 373 case llvm::Triple::ppc64le: 374 this->MCountName = "_mcount"; 375 break; 376 case llvm::Triple::arm: 377 this->MCountName = "__mcount"; 378 break; 379 } 380 } 381 }; 382 383 // GNU/kFreeBSD Target 384 template<typename Target> 385 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 386 protected: 387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 388 MacroBuilder &Builder) const override { 389 // GNU/kFreeBSD defines; list based off of gcc output 390 391 DefineStd(Builder, "unix", Opts); 392 Builder.defineMacro("__FreeBSD_kernel__"); 393 Builder.defineMacro("__GLIBC__"); 394 Builder.defineMacro("__ELF__"); 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 if (Opts.CPlusPlus) 398 Builder.defineMacro("_GNU_SOURCE"); 399 } 400 public: 401 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 402 : OSTargetInfo<Target>(Triple, Opts) {} 403 }; 404 405 // Haiku Target 406 template<typename Target> 407 class HaikuTargetInfo : public OSTargetInfo<Target> { 408 protected: 409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 410 MacroBuilder &Builder) const override { 411 // Haiku defines; list based off of gcc output 412 Builder.defineMacro("__HAIKU__"); 413 Builder.defineMacro("__ELF__"); 414 DefineStd(Builder, "unix", Opts); 415 } 416 public: 417 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 418 : OSTargetInfo<Target>(Triple, Opts) { 419 this->SizeType = TargetInfo::UnsignedLong; 420 this->IntPtrType = TargetInfo::SignedLong; 421 this->PtrDiffType = TargetInfo::SignedLong; 422 this->ProcessIDType = TargetInfo::SignedLong; 423 this->TLSSupported = false; 424 425 } 426 }; 427 428 // Minix Target 429 template<typename Target> 430 class MinixTargetInfo : public OSTargetInfo<Target> { 431 protected: 432 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 433 MacroBuilder &Builder) const override { 434 // Minix defines 435 436 Builder.defineMacro("__minix", "3"); 437 Builder.defineMacro("_EM_WSIZE", "4"); 438 Builder.defineMacro("_EM_PSIZE", "4"); 439 Builder.defineMacro("_EM_SSIZE", "2"); 440 Builder.defineMacro("_EM_LSIZE", "4"); 441 Builder.defineMacro("_EM_FSIZE", "4"); 442 Builder.defineMacro("_EM_DSIZE", "8"); 443 Builder.defineMacro("__ELF__"); 444 DefineStd(Builder, "unix", Opts); 445 } 446 public: 447 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 448 : OSTargetInfo<Target>(Triple, Opts) {} 449 }; 450 451 // Linux target 452 template<typename Target> 453 class LinuxTargetInfo : public OSTargetInfo<Target> { 454 protected: 455 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 456 MacroBuilder &Builder) const override { 457 // Linux defines; list based off of gcc output 458 DefineStd(Builder, "unix", Opts); 459 DefineStd(Builder, "linux", Opts); 460 Builder.defineMacro("__gnu_linux__"); 461 Builder.defineMacro("__ELF__"); 462 if (Triple.isAndroid()) { 463 Builder.defineMacro("__ANDROID__", "1"); 464 unsigned Maj, Min, Rev; 465 Triple.getEnvironmentVersion(Maj, Min, Rev); 466 this->PlatformName = "android"; 467 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 468 } 469 if (Opts.POSIXThreads) 470 Builder.defineMacro("_REENTRANT"); 471 if (Opts.CPlusPlus) 472 Builder.defineMacro("_GNU_SOURCE"); 473 if (this->HasFloat128) 474 Builder.defineMacro("__FLOAT128__"); 475 } 476 public: 477 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 478 : OSTargetInfo<Target>(Triple, Opts) { 479 this->WIntType = TargetInfo::UnsignedInt; 480 481 switch (Triple.getArch()) { 482 default: 483 break; 484 case llvm::Triple::ppc: 485 case llvm::Triple::ppc64: 486 case llvm::Triple::ppc64le: 487 this->MCountName = "_mcount"; 488 break; 489 case llvm::Triple::x86: 490 case llvm::Triple::x86_64: 491 case llvm::Triple::systemz: 492 this->HasFloat128 = true; 493 break; 494 } 495 } 496 497 const char *getStaticInitSectionSpecifier() const override { 498 return ".text.startup"; 499 } 500 }; 501 502 // NetBSD Target 503 template<typename Target> 504 class NetBSDTargetInfo : public OSTargetInfo<Target> { 505 protected: 506 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 507 MacroBuilder &Builder) const override { 508 // NetBSD defines; list based off of gcc output 509 Builder.defineMacro("__NetBSD__"); 510 Builder.defineMacro("__unix__"); 511 Builder.defineMacro("__ELF__"); 512 if (Opts.POSIXThreads) 513 Builder.defineMacro("_POSIX_THREADS"); 514 515 switch (Triple.getArch()) { 516 default: 517 break; 518 case llvm::Triple::arm: 519 case llvm::Triple::armeb: 520 case llvm::Triple::thumb: 521 case llvm::Triple::thumbeb: 522 Builder.defineMacro("__ARM_DWARF_EH__"); 523 break; 524 } 525 } 526 public: 527 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 528 : OSTargetInfo<Target>(Triple, Opts) { 529 this->MCountName = "_mcount"; 530 } 531 }; 532 533 // OpenBSD Target 534 template<typename Target> 535 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 536 protected: 537 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 538 MacroBuilder &Builder) const override { 539 // OpenBSD defines; list based off of gcc output 540 541 Builder.defineMacro("__OpenBSD__"); 542 DefineStd(Builder, "unix", Opts); 543 Builder.defineMacro("__ELF__"); 544 if (Opts.POSIXThreads) 545 Builder.defineMacro("_REENTRANT"); 546 } 547 public: 548 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 549 : OSTargetInfo<Target>(Triple, Opts) { 550 this->TLSSupported = false; 551 552 switch (Triple.getArch()) { 553 default: 554 case llvm::Triple::x86: 555 case llvm::Triple::x86_64: 556 case llvm::Triple::arm: 557 case llvm::Triple::sparc: 558 this->MCountName = "__mcount"; 559 break; 560 case llvm::Triple::mips64: 561 case llvm::Triple::mips64el: 562 case llvm::Triple::ppc: 563 case llvm::Triple::sparcv9: 564 this->MCountName = "_mcount"; 565 break; 566 } 567 } 568 }; 569 570 // Bitrig Target 571 template<typename Target> 572 class BitrigTargetInfo : public OSTargetInfo<Target> { 573 protected: 574 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 575 MacroBuilder &Builder) const override { 576 // Bitrig defines; list based off of gcc output 577 578 Builder.defineMacro("__Bitrig__"); 579 DefineStd(Builder, "unix", Opts); 580 Builder.defineMacro("__ELF__"); 581 if (Opts.POSIXThreads) 582 Builder.defineMacro("_REENTRANT"); 583 584 switch (Triple.getArch()) { 585 default: 586 break; 587 case llvm::Triple::arm: 588 case llvm::Triple::armeb: 589 case llvm::Triple::thumb: 590 case llvm::Triple::thumbeb: 591 Builder.defineMacro("__ARM_DWARF_EH__"); 592 break; 593 } 594 } 595 public: 596 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 597 : OSTargetInfo<Target>(Triple, Opts) { 598 this->MCountName = "__mcount"; 599 } 600 }; 601 602 // PSP Target 603 template<typename Target> 604 class PSPTargetInfo : public OSTargetInfo<Target> { 605 protected: 606 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 607 MacroBuilder &Builder) const override { 608 // PSP defines; list based on the output of the pspdev gcc toolchain. 609 Builder.defineMacro("PSP"); 610 Builder.defineMacro("_PSP"); 611 Builder.defineMacro("__psp__"); 612 Builder.defineMacro("__ELF__"); 613 } 614 public: 615 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 616 }; 617 618 // PS3 PPU Target 619 template<typename Target> 620 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 621 protected: 622 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 623 MacroBuilder &Builder) const override { 624 // PS3 PPU defines. 625 Builder.defineMacro("__PPC__"); 626 Builder.defineMacro("__PPU__"); 627 Builder.defineMacro("__CELLOS_LV2__"); 628 Builder.defineMacro("__ELF__"); 629 Builder.defineMacro("__LP32__"); 630 Builder.defineMacro("_ARCH_PPC64"); 631 Builder.defineMacro("__powerpc64__"); 632 } 633 public: 634 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 635 : OSTargetInfo<Target>(Triple, Opts) { 636 this->LongWidth = this->LongAlign = 32; 637 this->PointerWidth = this->PointerAlign = 32; 638 this->IntMaxType = TargetInfo::SignedLongLong; 639 this->Int64Type = TargetInfo::SignedLongLong; 640 this->SizeType = TargetInfo::UnsignedInt; 641 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 642 } 643 }; 644 645 template <typename Target> 646 class PS4OSTargetInfo : public OSTargetInfo<Target> { 647 protected: 648 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 649 MacroBuilder &Builder) const override { 650 Builder.defineMacro("__FreeBSD__", "9"); 651 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 652 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 653 DefineStd(Builder, "unix", Opts); 654 Builder.defineMacro("__ELF__"); 655 Builder.defineMacro("__ORBIS__"); 656 } 657 public: 658 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 659 : OSTargetInfo<Target>(Triple, Opts) { 660 this->WCharType = this->UnsignedShort; 661 662 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 663 this->MaxTLSAlign = 256; 664 665 // On PS4, do not honor explicit bit field alignment, 666 // as in "__attribute__((aligned(2))) int b : 1;". 667 this->UseExplicitBitFieldAlignment = false; 668 669 switch (Triple.getArch()) { 670 default: 671 case llvm::Triple::x86_64: 672 this->MCountName = ".mcount"; 673 break; 674 } 675 } 676 }; 677 678 // Solaris target 679 template<typename Target> 680 class SolarisTargetInfo : public OSTargetInfo<Target> { 681 protected: 682 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 683 MacroBuilder &Builder) const override { 684 DefineStd(Builder, "sun", Opts); 685 DefineStd(Builder, "unix", Opts); 686 Builder.defineMacro("__ELF__"); 687 Builder.defineMacro("__svr4__"); 688 Builder.defineMacro("__SVR4"); 689 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 690 // newer, but to 500 for everything else. feature_test.h has a check to 691 // ensure that you are not using C99 with an old version of X/Open or C89 692 // with a new version. 693 if (Opts.C99) 694 Builder.defineMacro("_XOPEN_SOURCE", "600"); 695 else 696 Builder.defineMacro("_XOPEN_SOURCE", "500"); 697 if (Opts.CPlusPlus) 698 Builder.defineMacro("__C99FEATURES__"); 699 Builder.defineMacro("_LARGEFILE_SOURCE"); 700 Builder.defineMacro("_LARGEFILE64_SOURCE"); 701 Builder.defineMacro("__EXTENSIONS__"); 702 Builder.defineMacro("_REENTRANT"); 703 } 704 public: 705 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 706 : OSTargetInfo<Target>(Triple, Opts) { 707 this->WCharType = this->SignedInt; 708 // FIXME: WIntType should be SignedLong 709 } 710 }; 711 712 // Windows target 713 template<typename Target> 714 class WindowsTargetInfo : public OSTargetInfo<Target> { 715 protected: 716 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 717 MacroBuilder &Builder) const override { 718 Builder.defineMacro("_WIN32"); 719 } 720 void getVisualStudioDefines(const LangOptions &Opts, 721 MacroBuilder &Builder) const { 722 if (Opts.CPlusPlus) { 723 if (Opts.RTTIData) 724 Builder.defineMacro("_CPPRTTI"); 725 726 if (Opts.CXXExceptions) 727 Builder.defineMacro("_CPPUNWIND"); 728 } 729 730 if (Opts.Bool) 731 Builder.defineMacro("__BOOL_DEFINED"); 732 733 if (!Opts.CharIsSigned) 734 Builder.defineMacro("_CHAR_UNSIGNED"); 735 736 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 737 // but it works for now. 738 if (Opts.POSIXThreads) 739 Builder.defineMacro("_MT"); 740 741 if (Opts.MSCompatibilityVersion) { 742 Builder.defineMacro("_MSC_VER", 743 Twine(Opts.MSCompatibilityVersion / 100000)); 744 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 745 // FIXME We cannot encode the revision information into 32-bits 746 Builder.defineMacro("_MSC_BUILD", Twine(1)); 747 748 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 749 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 750 751 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 752 if (Opts.CPlusPlus1z) 753 Builder.defineMacro("_MSVC_LANG", "201403L"); 754 else if (Opts.CPlusPlus14) 755 Builder.defineMacro("_MSVC_LANG", "201402L"); 756 } 757 } 758 759 if (Opts.MicrosoftExt) { 760 Builder.defineMacro("_MSC_EXTENSIONS"); 761 762 if (Opts.CPlusPlus11) { 763 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 764 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 765 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 766 } 767 } 768 769 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 770 } 771 772 public: 773 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 774 : OSTargetInfo<Target>(Triple, Opts) {} 775 }; 776 777 template <typename Target> 778 class NaClTargetInfo : public OSTargetInfo<Target> { 779 protected: 780 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 781 MacroBuilder &Builder) const override { 782 if (Opts.POSIXThreads) 783 Builder.defineMacro("_REENTRANT"); 784 if (Opts.CPlusPlus) 785 Builder.defineMacro("_GNU_SOURCE"); 786 787 DefineStd(Builder, "unix", Opts); 788 Builder.defineMacro("__ELF__"); 789 Builder.defineMacro("__native_client__"); 790 } 791 792 public: 793 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 794 : OSTargetInfo<Target>(Triple, Opts) { 795 this->LongAlign = 32; 796 this->LongWidth = 32; 797 this->PointerAlign = 32; 798 this->PointerWidth = 32; 799 this->IntMaxType = TargetInfo::SignedLongLong; 800 this->Int64Type = TargetInfo::SignedLongLong; 801 this->DoubleAlign = 64; 802 this->LongDoubleWidth = 64; 803 this->LongDoubleAlign = 64; 804 this->LongLongWidth = 64; 805 this->LongLongAlign = 64; 806 this->SizeType = TargetInfo::UnsignedInt; 807 this->PtrDiffType = TargetInfo::SignedInt; 808 this->IntPtrType = TargetInfo::SignedInt; 809 // RegParmMax is inherited from the underlying architecture. 810 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 811 if (Triple.getArch() == llvm::Triple::arm) { 812 // Handled in ARM's setABI(). 813 } else if (Triple.getArch() == llvm::Triple::x86) { 814 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 815 } else if (Triple.getArch() == llvm::Triple::x86_64) { 816 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 817 } else if (Triple.getArch() == llvm::Triple::mipsel) { 818 // Handled on mips' setDataLayout. 819 } else { 820 assert(Triple.getArch() == llvm::Triple::le32); 821 this->resetDataLayout("e-p:32:32-i64:64"); 822 } 823 } 824 }; 825 826 // WebAssembly target 827 template <typename Target> 828 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 829 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 830 MacroBuilder &Builder) const final { 831 // A common platform macro. 832 if (Opts.POSIXThreads) 833 Builder.defineMacro("_REENTRANT"); 834 // Follow g++ convention and predefine _GNU_SOURCE for C++. 835 if (Opts.CPlusPlus) 836 Builder.defineMacro("_GNU_SOURCE"); 837 } 838 839 // As an optimization, group static init code together in a section. 840 const char *getStaticInitSectionSpecifier() const final { 841 return ".text.__startup"; 842 } 843 844 public: 845 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 846 const TargetOptions &Opts) 847 : OSTargetInfo<Target>(Triple, Opts) { 848 this->MCountName = "__mcount"; 849 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 850 } 851 }; 852 853 //===----------------------------------------------------------------------===// 854 // Specific target implementations. 855 //===----------------------------------------------------------------------===// 856 857 // PPC abstract base class 858 class PPCTargetInfo : public TargetInfo { 859 static const Builtin::Info BuiltinInfo[]; 860 static const char * const GCCRegNames[]; 861 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 862 std::string CPU; 863 864 // Target cpu features. 865 bool HasVSX; 866 bool HasP8Vector; 867 bool HasP8Crypto; 868 bool HasDirectMove; 869 bool HasQPX; 870 bool HasHTM; 871 bool HasBPERMD; 872 bool HasExtDiv; 873 874 protected: 875 std::string ABI; 876 877 public: 878 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 879 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 880 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 881 HasBPERMD(false), HasExtDiv(false) { 882 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 883 SimdDefaultAlign = 128; 884 LongDoubleWidth = LongDoubleAlign = 128; 885 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 886 } 887 888 /// \brief Flags for architecture specific defines. 889 typedef enum { 890 ArchDefineNone = 0, 891 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 892 ArchDefinePpcgr = 1 << 1, 893 ArchDefinePpcsq = 1 << 2, 894 ArchDefine440 = 1 << 3, 895 ArchDefine603 = 1 << 4, 896 ArchDefine604 = 1 << 5, 897 ArchDefinePwr4 = 1 << 6, 898 ArchDefinePwr5 = 1 << 7, 899 ArchDefinePwr5x = 1 << 8, 900 ArchDefinePwr6 = 1 << 9, 901 ArchDefinePwr6x = 1 << 10, 902 ArchDefinePwr7 = 1 << 11, 903 ArchDefinePwr8 = 1 << 12, 904 ArchDefinePwr9 = 1 << 13, 905 ArchDefineA2 = 1 << 14, 906 ArchDefineA2q = 1 << 15 907 } ArchDefineTypes; 908 909 // Note: GCC recognizes the following additional cpus: 910 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 911 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 912 // titan, rs64. 913 bool setCPU(const std::string &Name) override { 914 bool CPUKnown = llvm::StringSwitch<bool>(Name) 915 .Case("generic", true) 916 .Case("440", true) 917 .Case("450", true) 918 .Case("601", true) 919 .Case("602", true) 920 .Case("603", true) 921 .Case("603e", true) 922 .Case("603ev", true) 923 .Case("604", true) 924 .Case("604e", true) 925 .Case("620", true) 926 .Case("630", true) 927 .Case("g3", true) 928 .Case("7400", true) 929 .Case("g4", true) 930 .Case("7450", true) 931 .Case("g4+", true) 932 .Case("750", true) 933 .Case("970", true) 934 .Case("g5", true) 935 .Case("a2", true) 936 .Case("a2q", true) 937 .Case("e500mc", true) 938 .Case("e5500", true) 939 .Case("power3", true) 940 .Case("pwr3", true) 941 .Case("power4", true) 942 .Case("pwr4", true) 943 .Case("power5", true) 944 .Case("pwr5", true) 945 .Case("power5x", true) 946 .Case("pwr5x", true) 947 .Case("power6", true) 948 .Case("pwr6", true) 949 .Case("power6x", true) 950 .Case("pwr6x", true) 951 .Case("power7", true) 952 .Case("pwr7", true) 953 .Case("power8", true) 954 .Case("pwr8", true) 955 .Case("power9", true) 956 .Case("pwr9", true) 957 .Case("powerpc", true) 958 .Case("ppc", true) 959 .Case("powerpc64", true) 960 .Case("ppc64", true) 961 .Case("powerpc64le", true) 962 .Case("ppc64le", true) 963 .Default(false); 964 965 if (CPUKnown) 966 CPU = Name; 967 968 return CPUKnown; 969 } 970 971 972 StringRef getABI() const override { return ABI; } 973 974 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 975 return llvm::makeArrayRef(BuiltinInfo, 976 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 977 } 978 979 bool isCLZForZeroUndef() const override { return false; } 980 981 void getTargetDefines(const LangOptions &Opts, 982 MacroBuilder &Builder) const override; 983 984 bool 985 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 986 StringRef CPU, 987 const std::vector<std::string> &FeaturesVec) const override; 988 989 bool handleTargetFeatures(std::vector<std::string> &Features, 990 DiagnosticsEngine &Diags) override; 991 bool hasFeature(StringRef Feature) const override; 992 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 993 bool Enabled) const override; 994 995 ArrayRef<const char *> getGCCRegNames() const override; 996 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 997 bool validateAsmConstraint(const char *&Name, 998 TargetInfo::ConstraintInfo &Info) const override { 999 switch (*Name) { 1000 default: return false; 1001 case 'O': // Zero 1002 break; 1003 case 'b': // Base register 1004 case 'f': // Floating point register 1005 Info.setAllowsRegister(); 1006 break; 1007 // FIXME: The following are added to allow parsing. 1008 // I just took a guess at what the actions should be. 1009 // Also, is more specific checking needed? I.e. specific registers? 1010 case 'd': // Floating point register (containing 64-bit value) 1011 case 'v': // Altivec vector register 1012 Info.setAllowsRegister(); 1013 break; 1014 case 'w': 1015 switch (Name[1]) { 1016 case 'd':// VSX vector register to hold vector double data 1017 case 'f':// VSX vector register to hold vector float data 1018 case 's':// VSX vector register to hold scalar float data 1019 case 'a':// Any VSX register 1020 case 'c':// An individual CR bit 1021 break; 1022 default: 1023 return false; 1024 } 1025 Info.setAllowsRegister(); 1026 Name++; // Skip over 'w'. 1027 break; 1028 case 'h': // `MQ', `CTR', or `LINK' register 1029 case 'q': // `MQ' register 1030 case 'c': // `CTR' register 1031 case 'l': // `LINK' register 1032 case 'x': // `CR' register (condition register) number 0 1033 case 'y': // `CR' register (condition register) 1034 case 'z': // `XER[CA]' carry bit (part of the XER register) 1035 Info.setAllowsRegister(); 1036 break; 1037 case 'I': // Signed 16-bit constant 1038 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1039 // (use `L' instead for SImode constants) 1040 case 'K': // Unsigned 16-bit constant 1041 case 'L': // Signed 16-bit constant shifted left 16 bits 1042 case 'M': // Constant larger than 31 1043 case 'N': // Exact power of 2 1044 case 'P': // Constant whose negation is a signed 16-bit constant 1045 case 'G': // Floating point constant that can be loaded into a 1046 // register with one instruction per word 1047 case 'H': // Integer/Floating point constant that can be loaded 1048 // into a register using three instructions 1049 break; 1050 case 'm': // Memory operand. Note that on PowerPC targets, m can 1051 // include addresses that update the base register. It 1052 // is therefore only safe to use `m' in an asm statement 1053 // if that asm statement accesses the operand exactly once. 1054 // The asm statement must also use `%U<opno>' as a 1055 // placeholder for the "update" flag in the corresponding 1056 // load or store instruction. For example: 1057 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1058 // is correct but: 1059 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1060 // is not. Use es rather than m if you don't want the base 1061 // register to be updated. 1062 case 'e': 1063 if (Name[1] != 's') 1064 return false; 1065 // es: A "stable" memory operand; that is, one which does not 1066 // include any automodification of the base register. Unlike 1067 // `m', this constraint can be used in asm statements that 1068 // might access the operand several times, or that might not 1069 // access it at all. 1070 Info.setAllowsMemory(); 1071 Name++; // Skip over 'e'. 1072 break; 1073 case 'Q': // Memory operand that is an offset from a register (it is 1074 // usually better to use `m' or `es' in asm statements) 1075 case 'Z': // Memory operand that is an indexed or indirect from a 1076 // register (it is usually better to use `m' or `es' in 1077 // asm statements) 1078 Info.setAllowsMemory(); 1079 Info.setAllowsRegister(); 1080 break; 1081 case 'R': // AIX TOC entry 1082 case 'a': // Address operand that is an indexed or indirect from a 1083 // register (`p' is preferable for asm statements) 1084 case 'S': // Constant suitable as a 64-bit mask operand 1085 case 'T': // Constant suitable as a 32-bit mask operand 1086 case 'U': // System V Release 4 small data area reference 1087 case 't': // AND masks that can be performed by two rldic{l, r} 1088 // instructions 1089 case 'W': // Vector constant that does not require memory 1090 case 'j': // Vector constant that is all zeros. 1091 break; 1092 // End FIXME. 1093 } 1094 return true; 1095 } 1096 std::string convertConstraint(const char *&Constraint) const override { 1097 std::string R; 1098 switch (*Constraint) { 1099 case 'e': 1100 case 'w': 1101 // Two-character constraint; add "^" hint for later parsing. 1102 R = std::string("^") + std::string(Constraint, 2); 1103 Constraint++; 1104 break; 1105 default: 1106 return TargetInfo::convertConstraint(Constraint); 1107 } 1108 return R; 1109 } 1110 const char *getClobbers() const override { 1111 return ""; 1112 } 1113 int getEHDataRegisterNumber(unsigned RegNo) const override { 1114 if (RegNo == 0) return 3; 1115 if (RegNo == 1) return 4; 1116 return -1; 1117 } 1118 1119 bool hasSjLjLowering() const override { 1120 return true; 1121 } 1122 1123 bool useFloat128ManglingForLongDouble() const override { 1124 return LongDoubleWidth == 128 && 1125 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1126 getTriple().isOSBinFormatELF(); 1127 } 1128 }; 1129 1130 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1131 #define BUILTIN(ID, TYPE, ATTRS) \ 1132 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1133 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1134 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1135 #include "clang/Basic/BuiltinsPPC.def" 1136 }; 1137 1138 /// handleTargetFeatures - Perform initialization based on the user 1139 /// configured set of features. 1140 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1141 DiagnosticsEngine &Diags) { 1142 for (const auto &Feature : Features) { 1143 if (Feature == "+vsx") { 1144 HasVSX = true; 1145 } else if (Feature == "+bpermd") { 1146 HasBPERMD = true; 1147 } else if (Feature == "+extdiv") { 1148 HasExtDiv = true; 1149 } else if (Feature == "+power8-vector") { 1150 HasP8Vector = true; 1151 } else if (Feature == "+crypto") { 1152 HasP8Crypto = true; 1153 } else if (Feature == "+direct-move") { 1154 HasDirectMove = true; 1155 } else if (Feature == "+qpx") { 1156 HasQPX = true; 1157 } else if (Feature == "+htm") { 1158 HasHTM = true; 1159 } else if (Feature == "+float128") { 1160 HasFloat128 = true; 1161 } 1162 // TODO: Finish this list and add an assert that we've handled them 1163 // all. 1164 } 1165 1166 return true; 1167 } 1168 1169 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1170 /// #defines that are not tied to a specific subtarget. 1171 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1172 MacroBuilder &Builder) const { 1173 // Target identification. 1174 Builder.defineMacro("__ppc__"); 1175 Builder.defineMacro("__PPC__"); 1176 Builder.defineMacro("_ARCH_PPC"); 1177 Builder.defineMacro("__powerpc__"); 1178 Builder.defineMacro("__POWERPC__"); 1179 if (PointerWidth == 64) { 1180 Builder.defineMacro("_ARCH_PPC64"); 1181 Builder.defineMacro("__powerpc64__"); 1182 Builder.defineMacro("__ppc64__"); 1183 Builder.defineMacro("__PPC64__"); 1184 } 1185 1186 // Target properties. 1187 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1188 Builder.defineMacro("_LITTLE_ENDIAN"); 1189 } else { 1190 if (getTriple().getOS() != llvm::Triple::NetBSD && 1191 getTriple().getOS() != llvm::Triple::OpenBSD) 1192 Builder.defineMacro("_BIG_ENDIAN"); 1193 } 1194 1195 // ABI options. 1196 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1197 Builder.defineMacro("_CALL_ELF", "1"); 1198 if (ABI == "elfv2") 1199 Builder.defineMacro("_CALL_ELF", "2"); 1200 1201 // Subtarget options. 1202 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1203 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1204 1205 // FIXME: Should be controlled by command line option. 1206 if (LongDoubleWidth == 128) 1207 Builder.defineMacro("__LONG_DOUBLE_128__"); 1208 1209 if (Opts.AltiVec) { 1210 Builder.defineMacro("__VEC__", "10206"); 1211 Builder.defineMacro("__ALTIVEC__"); 1212 } 1213 1214 // CPU identification. 1215 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1216 .Case("440", ArchDefineName) 1217 .Case("450", ArchDefineName | ArchDefine440) 1218 .Case("601", ArchDefineName) 1219 .Case("602", ArchDefineName | ArchDefinePpcgr) 1220 .Case("603", ArchDefineName | ArchDefinePpcgr) 1221 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1222 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1223 .Case("604", ArchDefineName | ArchDefinePpcgr) 1224 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1225 .Case("620", ArchDefineName | ArchDefinePpcgr) 1226 .Case("630", ArchDefineName | ArchDefinePpcgr) 1227 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1228 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1229 .Case("750", ArchDefineName | ArchDefinePpcgr) 1230 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1231 | ArchDefinePpcsq) 1232 .Case("a2", ArchDefineA2) 1233 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1234 .Case("pwr3", ArchDefinePpcgr) 1235 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1236 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1237 | ArchDefinePpcsq) 1238 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1239 | ArchDefinePpcgr | ArchDefinePpcsq) 1240 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1241 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1242 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1243 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1244 | ArchDefinePpcsq) 1245 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1246 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1247 | ArchDefinePpcgr | ArchDefinePpcsq) 1248 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1249 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1250 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1251 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 1252 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1253 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1254 | ArchDefinePpcsq) 1255 .Case("power3", ArchDefinePpcgr) 1256 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1257 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1258 | ArchDefinePpcsq) 1259 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1260 | ArchDefinePpcgr | ArchDefinePpcsq) 1261 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1262 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1263 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1264 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1265 | ArchDefinePpcsq) 1266 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1267 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1268 | ArchDefinePpcgr | ArchDefinePpcsq) 1269 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1270 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1271 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1272 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 1273 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1274 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1275 | ArchDefinePpcsq) 1276 .Default(ArchDefineNone); 1277 1278 if (defs & ArchDefineName) 1279 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1280 if (defs & ArchDefinePpcgr) 1281 Builder.defineMacro("_ARCH_PPCGR"); 1282 if (defs & ArchDefinePpcsq) 1283 Builder.defineMacro("_ARCH_PPCSQ"); 1284 if (defs & ArchDefine440) 1285 Builder.defineMacro("_ARCH_440"); 1286 if (defs & ArchDefine603) 1287 Builder.defineMacro("_ARCH_603"); 1288 if (defs & ArchDefine604) 1289 Builder.defineMacro("_ARCH_604"); 1290 if (defs & ArchDefinePwr4) 1291 Builder.defineMacro("_ARCH_PWR4"); 1292 if (defs & ArchDefinePwr5) 1293 Builder.defineMacro("_ARCH_PWR5"); 1294 if (defs & ArchDefinePwr5x) 1295 Builder.defineMacro("_ARCH_PWR5X"); 1296 if (defs & ArchDefinePwr6) 1297 Builder.defineMacro("_ARCH_PWR6"); 1298 if (defs & ArchDefinePwr6x) 1299 Builder.defineMacro("_ARCH_PWR6X"); 1300 if (defs & ArchDefinePwr7) 1301 Builder.defineMacro("_ARCH_PWR7"); 1302 if (defs & ArchDefinePwr8) 1303 Builder.defineMacro("_ARCH_PWR8"); 1304 if (defs & ArchDefinePwr9) 1305 Builder.defineMacro("_ARCH_PWR9"); 1306 if (defs & ArchDefineA2) 1307 Builder.defineMacro("_ARCH_A2"); 1308 if (defs & ArchDefineA2q) { 1309 Builder.defineMacro("_ARCH_A2Q"); 1310 Builder.defineMacro("_ARCH_QP"); 1311 } 1312 1313 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1314 Builder.defineMacro("__bg__"); 1315 Builder.defineMacro("__THW_BLUEGENE__"); 1316 Builder.defineMacro("__bgq__"); 1317 Builder.defineMacro("__TOS_BGQ__"); 1318 } 1319 1320 if (HasVSX) 1321 Builder.defineMacro("__VSX__"); 1322 if (HasP8Vector) 1323 Builder.defineMacro("__POWER8_VECTOR__"); 1324 if (HasP8Crypto) 1325 Builder.defineMacro("__CRYPTO__"); 1326 if (HasHTM) 1327 Builder.defineMacro("__HTM__"); 1328 if (HasFloat128) 1329 Builder.defineMacro("__FLOAT128__"); 1330 1331 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1332 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1333 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1334 if (PointerWidth == 64) 1335 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1336 1337 // FIXME: The following are not yet generated here by Clang, but are 1338 // generated by GCC: 1339 // 1340 // _SOFT_FLOAT_ 1341 // __RECIP_PRECISION__ 1342 // __APPLE_ALTIVEC__ 1343 // __RECIP__ 1344 // __RECIPF__ 1345 // __RSQRTE__ 1346 // __RSQRTEF__ 1347 // _SOFT_DOUBLE_ 1348 // __NO_LWSYNC__ 1349 // __HAVE_BSWAP__ 1350 // __LONGDOUBLE128 1351 // __CMODEL_MEDIUM__ 1352 // __CMODEL_LARGE__ 1353 // _CALL_SYSV 1354 // _CALL_DARWIN 1355 // __NO_FPRS__ 1356 } 1357 1358 // Handle explicit options being passed to the compiler here: if we've 1359 // explicitly turned off vsx and turned on power8-vector or direct-move then 1360 // go ahead and error since the customer has expressed a somewhat incompatible 1361 // set of options. 1362 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1363 const std::vector<std::string> &FeaturesVec) { 1364 1365 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1366 FeaturesVec.end()) { 1367 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1368 FeaturesVec.end()) { 1369 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1370 << "-mno-vsx"; 1371 return false; 1372 } 1373 1374 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1375 FeaturesVec.end()) { 1376 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1377 << "-mno-vsx"; 1378 return false; 1379 } 1380 1381 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1382 FeaturesVec.end()) { 1383 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1384 << "-mno-vsx"; 1385 return false; 1386 } 1387 } 1388 1389 return true; 1390 } 1391 1392 bool PPCTargetInfo::initFeatureMap( 1393 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1394 const std::vector<std::string> &FeaturesVec) const { 1395 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1396 .Case("7400", true) 1397 .Case("g4", true) 1398 .Case("7450", true) 1399 .Case("g4+", true) 1400 .Case("970", true) 1401 .Case("g5", true) 1402 .Case("pwr6", true) 1403 .Case("pwr7", true) 1404 .Case("pwr8", true) 1405 .Case("pwr9", true) 1406 .Case("ppc64", true) 1407 .Case("ppc64le", true) 1408 .Default(false); 1409 1410 Features["qpx"] = (CPU == "a2q"); 1411 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1412 .Case("ppc64le", true) 1413 .Case("pwr9", true) 1414 .Case("pwr8", true) 1415 .Default(false); 1416 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1417 .Case("ppc64le", true) 1418 .Case("pwr9", true) 1419 .Case("pwr8", true) 1420 .Default(false); 1421 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1422 .Case("ppc64le", true) 1423 .Case("pwr9", true) 1424 .Case("pwr8", true) 1425 .Case("pwr7", true) 1426 .Default(false); 1427 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1428 .Case("ppc64le", true) 1429 .Case("pwr9", true) 1430 .Case("pwr8", true) 1431 .Case("pwr7", true) 1432 .Default(false); 1433 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1434 .Case("ppc64le", true) 1435 .Case("pwr9", true) 1436 .Case("pwr8", true) 1437 .Default(false); 1438 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1439 .Case("ppc64le", true) 1440 .Case("pwr9", true) 1441 .Case("pwr8", true) 1442 .Case("pwr7", true) 1443 .Default(false); 1444 1445 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1446 return false; 1447 1448 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1449 } 1450 1451 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1452 return llvm::StringSwitch<bool>(Feature) 1453 .Case("powerpc", true) 1454 .Case("vsx", HasVSX) 1455 .Case("power8-vector", HasP8Vector) 1456 .Case("crypto", HasP8Crypto) 1457 .Case("direct-move", HasDirectMove) 1458 .Case("qpx", HasQPX) 1459 .Case("htm", HasHTM) 1460 .Case("bpermd", HasBPERMD) 1461 .Case("extdiv", HasExtDiv) 1462 .Case("float128", HasFloat128) 1463 .Default(false); 1464 } 1465 1466 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1467 StringRef Name, bool Enabled) const { 1468 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1469 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1470 // incompatible options. 1471 if (Enabled) { 1472 if (Name == "direct-move") { 1473 Features[Name] = Features["vsx"] = true; 1474 } else if (Name == "power8-vector") { 1475 Features[Name] = Features["vsx"] = true; 1476 } else if (Name == "float128") { 1477 Features[Name] = Features["vsx"] = true; 1478 } else { 1479 Features[Name] = true; 1480 } 1481 } else { 1482 if (Name == "vsx") { 1483 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1484 Features["float128"] = false; 1485 } else { 1486 Features[Name] = false; 1487 } 1488 } 1489 } 1490 1491 const char * const PPCTargetInfo::GCCRegNames[] = { 1492 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1493 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1494 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1495 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1496 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1497 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1498 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1499 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1500 "mq", "lr", "ctr", "ap", 1501 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1502 "xer", 1503 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1504 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1505 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1506 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1507 "vrsave", "vscr", 1508 "spe_acc", "spefscr", 1509 "sfp" 1510 }; 1511 1512 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1513 return llvm::makeArrayRef(GCCRegNames); 1514 } 1515 1516 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1517 // While some of these aliases do map to different registers 1518 // they still share the same register name. 1519 { { "0" }, "r0" }, 1520 { { "1"}, "r1" }, 1521 { { "2" }, "r2" }, 1522 { { "3" }, "r3" }, 1523 { { "4" }, "r4" }, 1524 { { "5" }, "r5" }, 1525 { { "6" }, "r6" }, 1526 { { "7" }, "r7" }, 1527 { { "8" }, "r8" }, 1528 { { "9" }, "r9" }, 1529 { { "10" }, "r10" }, 1530 { { "11" }, "r11" }, 1531 { { "12" }, "r12" }, 1532 { { "13" }, "r13" }, 1533 { { "14" }, "r14" }, 1534 { { "15" }, "r15" }, 1535 { { "16" }, "r16" }, 1536 { { "17" }, "r17" }, 1537 { { "18" }, "r18" }, 1538 { { "19" }, "r19" }, 1539 { { "20" }, "r20" }, 1540 { { "21" }, "r21" }, 1541 { { "22" }, "r22" }, 1542 { { "23" }, "r23" }, 1543 { { "24" }, "r24" }, 1544 { { "25" }, "r25" }, 1545 { { "26" }, "r26" }, 1546 { { "27" }, "r27" }, 1547 { { "28" }, "r28" }, 1548 { { "29" }, "r29" }, 1549 { { "30" }, "r30" }, 1550 { { "31" }, "r31" }, 1551 { { "fr0" }, "f0" }, 1552 { { "fr1" }, "f1" }, 1553 { { "fr2" }, "f2" }, 1554 { { "fr3" }, "f3" }, 1555 { { "fr4" }, "f4" }, 1556 { { "fr5" }, "f5" }, 1557 { { "fr6" }, "f6" }, 1558 { { "fr7" }, "f7" }, 1559 { { "fr8" }, "f8" }, 1560 { { "fr9" }, "f9" }, 1561 { { "fr10" }, "f10" }, 1562 { { "fr11" }, "f11" }, 1563 { { "fr12" }, "f12" }, 1564 { { "fr13" }, "f13" }, 1565 { { "fr14" }, "f14" }, 1566 { { "fr15" }, "f15" }, 1567 { { "fr16" }, "f16" }, 1568 { { "fr17" }, "f17" }, 1569 { { "fr18" }, "f18" }, 1570 { { "fr19" }, "f19" }, 1571 { { "fr20" }, "f20" }, 1572 { { "fr21" }, "f21" }, 1573 { { "fr22" }, "f22" }, 1574 { { "fr23" }, "f23" }, 1575 { { "fr24" }, "f24" }, 1576 { { "fr25" }, "f25" }, 1577 { { "fr26" }, "f26" }, 1578 { { "fr27" }, "f27" }, 1579 { { "fr28" }, "f28" }, 1580 { { "fr29" }, "f29" }, 1581 { { "fr30" }, "f30" }, 1582 { { "fr31" }, "f31" }, 1583 { { "cc" }, "cr0" }, 1584 }; 1585 1586 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1587 return llvm::makeArrayRef(GCCRegAliases); 1588 } 1589 1590 class PPC32TargetInfo : public PPCTargetInfo { 1591 public: 1592 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1593 : PPCTargetInfo(Triple, Opts) { 1594 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1595 1596 switch (getTriple().getOS()) { 1597 case llvm::Triple::Linux: 1598 case llvm::Triple::FreeBSD: 1599 case llvm::Triple::NetBSD: 1600 SizeType = UnsignedInt; 1601 PtrDiffType = SignedInt; 1602 IntPtrType = SignedInt; 1603 break; 1604 default: 1605 break; 1606 } 1607 1608 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1609 LongDoubleWidth = LongDoubleAlign = 64; 1610 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1611 } 1612 1613 // PPC32 supports atomics up to 4 bytes. 1614 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1615 } 1616 1617 BuiltinVaListKind getBuiltinVaListKind() const override { 1618 // This is the ELF definition, and is overridden by the Darwin sub-target 1619 return TargetInfo::PowerABIBuiltinVaList; 1620 } 1621 }; 1622 1623 // Note: ABI differences may eventually require us to have a separate 1624 // TargetInfo for little endian. 1625 class PPC64TargetInfo : public PPCTargetInfo { 1626 public: 1627 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1628 : PPCTargetInfo(Triple, Opts) { 1629 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1630 IntMaxType = SignedLong; 1631 Int64Type = SignedLong; 1632 1633 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1634 resetDataLayout("e-m:e-i64:64-n32:64"); 1635 ABI = "elfv2"; 1636 } else { 1637 resetDataLayout("E-m:e-i64:64-n32:64"); 1638 ABI = "elfv1"; 1639 } 1640 1641 switch (getTriple().getOS()) { 1642 case llvm::Triple::FreeBSD: 1643 LongDoubleWidth = LongDoubleAlign = 64; 1644 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1645 break; 1646 case llvm::Triple::NetBSD: 1647 IntMaxType = SignedLongLong; 1648 Int64Type = SignedLongLong; 1649 break; 1650 default: 1651 break; 1652 } 1653 1654 // PPC64 supports atomics up to 8 bytes. 1655 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1656 } 1657 BuiltinVaListKind getBuiltinVaListKind() const override { 1658 return TargetInfo::CharPtrBuiltinVaList; 1659 } 1660 // PPC64 Linux-specific ABI options. 1661 bool setABI(const std::string &Name) override { 1662 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1663 ABI = Name; 1664 return true; 1665 } 1666 return false; 1667 } 1668 }; 1669 1670 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1671 public: 1672 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1673 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1674 HasAlignMac68kSupport = true; 1675 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1676 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1677 LongLongAlign = 32; 1678 SuitableAlign = 128; 1679 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1680 } 1681 BuiltinVaListKind getBuiltinVaListKind() const override { 1682 return TargetInfo::CharPtrBuiltinVaList; 1683 } 1684 }; 1685 1686 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1687 public: 1688 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1689 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1690 HasAlignMac68kSupport = true; 1691 SuitableAlign = 128; 1692 resetDataLayout("E-m:o-i64:64-n32:64"); 1693 } 1694 }; 1695 1696 static const unsigned NVPTXAddrSpaceMap[] = { 1697 1, // opencl_global 1698 3, // opencl_local 1699 4, // opencl_constant 1700 // FIXME: generic has to be added to the target 1701 0, // opencl_generic 1702 1, // cuda_device 1703 4, // cuda_constant 1704 3, // cuda_shared 1705 }; 1706 1707 class NVPTXTargetInfo : public TargetInfo { 1708 static const char *const GCCRegNames[]; 1709 static const Builtin::Info BuiltinInfo[]; 1710 CudaArch GPU; 1711 1712 public: 1713 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1714 : TargetInfo(Triple) { 1715 BigEndian = false; 1716 TLSSupported = false; 1717 LongWidth = LongAlign = 64; 1718 AddrSpaceMap = &NVPTXAddrSpaceMap; 1719 UseAddrSpaceMapMangling = true; 1720 // Define available target features 1721 // These must be defined in sorted order! 1722 NoAsmVariants = true; 1723 GPU = CudaArch::SM_20; 1724 1725 // If possible, get a TargetInfo for our host triple, so we can match its 1726 // types. 1727 llvm::Triple HostTriple(Opts.HostTriple); 1728 if (HostTriple.isNVPTX()) 1729 return; 1730 std::unique_ptr<TargetInfo> HostTarget( 1731 AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1732 if (!HostTarget) { 1733 return; 1734 } 1735 1736 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1737 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1738 BoolWidth = HostTarget->getBoolWidth(); 1739 BoolAlign = HostTarget->getBoolAlign(); 1740 IntWidth = HostTarget->getIntWidth(); 1741 IntAlign = HostTarget->getIntAlign(); 1742 HalfWidth = HostTarget->getHalfWidth(); 1743 HalfAlign = HostTarget->getHalfAlign(); 1744 FloatWidth = HostTarget->getFloatWidth(); 1745 FloatAlign = HostTarget->getFloatAlign(); 1746 DoubleWidth = HostTarget->getDoubleWidth(); 1747 DoubleAlign = HostTarget->getDoubleAlign(); 1748 LongWidth = HostTarget->getLongWidth(); 1749 LongAlign = HostTarget->getLongAlign(); 1750 LongLongWidth = HostTarget->getLongLongWidth(); 1751 LongLongAlign = HostTarget->getLongLongAlign(); 1752 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1753 DefaultAlignForAttributeAligned = 1754 HostTarget->getDefaultAlignForAttributeAligned(); 1755 SizeType = HostTarget->getSizeType(); 1756 IntMaxType = HostTarget->getIntMaxType(); 1757 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1758 IntPtrType = HostTarget->getIntPtrType(); 1759 WCharType = HostTarget->getWCharType(); 1760 WIntType = HostTarget->getWIntType(); 1761 Char16Type = HostTarget->getChar16Type(); 1762 Char32Type = HostTarget->getChar32Type(); 1763 Int64Type = HostTarget->getInt64Type(); 1764 SigAtomicType = HostTarget->getSigAtomicType(); 1765 ProcessIDType = HostTarget->getProcessIDType(); 1766 1767 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1768 UseZeroLengthBitfieldAlignment = 1769 HostTarget->useZeroLengthBitfieldAlignment(); 1770 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1771 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1772 1773 // Properties intentionally not copied from host: 1774 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1775 // host/device boundary. 1776 // - SuitableAlign: Not visible across the host/device boundary, and may 1777 // correctly be different on host/device, e.g. if host has wider vector 1778 // types than device. 1779 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1780 // as its double type, but that's not necessarily true on the host. 1781 // TODO: nvcc emits a warning when using long double on device; we should 1782 // do the same. 1783 } 1784 void getTargetDefines(const LangOptions &Opts, 1785 MacroBuilder &Builder) const override { 1786 Builder.defineMacro("__PTX__"); 1787 Builder.defineMacro("__NVPTX__"); 1788 if (Opts.CUDAIsDevice) { 1789 // Set __CUDA_ARCH__ for the GPU specified. 1790 std::string CUDAArchCode = [this] { 1791 switch (GPU) { 1792 case CudaArch::UNKNOWN: 1793 assert(false && "No GPU arch when compiling CUDA device code."); 1794 return ""; 1795 case CudaArch::SM_20: 1796 return "200"; 1797 case CudaArch::SM_21: 1798 return "210"; 1799 case CudaArch::SM_30: 1800 return "300"; 1801 case CudaArch::SM_32: 1802 return "320"; 1803 case CudaArch::SM_35: 1804 return "350"; 1805 case CudaArch::SM_37: 1806 return "370"; 1807 case CudaArch::SM_50: 1808 return "500"; 1809 case CudaArch::SM_52: 1810 return "520"; 1811 case CudaArch::SM_53: 1812 return "530"; 1813 case CudaArch::SM_60: 1814 return "600"; 1815 case CudaArch::SM_61: 1816 return "610"; 1817 case CudaArch::SM_62: 1818 return "620"; 1819 } 1820 llvm_unreachable("unhandled CudaArch"); 1821 }(); 1822 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1823 } 1824 } 1825 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1826 return llvm::makeArrayRef(BuiltinInfo, 1827 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1828 } 1829 bool hasFeature(StringRef Feature) const override { 1830 return Feature == "ptx" || Feature == "nvptx"; 1831 } 1832 1833 ArrayRef<const char *> getGCCRegNames() const override; 1834 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1835 // No aliases. 1836 return None; 1837 } 1838 bool validateAsmConstraint(const char *&Name, 1839 TargetInfo::ConstraintInfo &Info) const override { 1840 switch (*Name) { 1841 default: 1842 return false; 1843 case 'c': 1844 case 'h': 1845 case 'r': 1846 case 'l': 1847 case 'f': 1848 case 'd': 1849 Info.setAllowsRegister(); 1850 return true; 1851 } 1852 } 1853 const char *getClobbers() const override { 1854 // FIXME: Is this really right? 1855 return ""; 1856 } 1857 BuiltinVaListKind getBuiltinVaListKind() const override { 1858 // FIXME: implement 1859 return TargetInfo::CharPtrBuiltinVaList; 1860 } 1861 bool setCPU(const std::string &Name) override { 1862 GPU = StringToCudaArch(Name); 1863 return GPU != CudaArch::UNKNOWN; 1864 } 1865 void setSupportedOpenCLOpts() override { 1866 auto &Opts = getSupportedOpenCLOpts(); 1867 Opts.cl_clang_storage_class_specifiers = 1; 1868 Opts.cl_khr_gl_sharing = 1; 1869 Opts.cl_khr_icd = 1; 1870 1871 Opts.cl_khr_fp64 = 1; 1872 Opts.cl_khr_byte_addressable_store = 1; 1873 Opts.cl_khr_global_int32_base_atomics = 1; 1874 Opts.cl_khr_global_int32_extended_atomics = 1; 1875 Opts.cl_khr_local_int32_base_atomics = 1; 1876 Opts.cl_khr_local_int32_extended_atomics = 1; 1877 } 1878 }; 1879 1880 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1881 #define BUILTIN(ID, TYPE, ATTRS) \ 1882 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1883 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1884 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1885 #include "clang/Basic/BuiltinsNVPTX.def" 1886 }; 1887 1888 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1889 1890 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1891 return llvm::makeArrayRef(GCCRegNames); 1892 } 1893 1894 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1895 public: 1896 NVPTX32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1897 : NVPTXTargetInfo(Triple, Opts) { 1898 LongWidth = LongAlign = 32; 1899 PointerWidth = PointerAlign = 32; 1900 SizeType = TargetInfo::UnsignedInt; 1901 PtrDiffType = TargetInfo::SignedInt; 1902 IntPtrType = TargetInfo::SignedInt; 1903 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1904 } 1905 }; 1906 1907 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1908 public: 1909 NVPTX64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1910 : NVPTXTargetInfo(Triple, Opts) { 1911 PointerWidth = PointerAlign = 64; 1912 SizeType = TargetInfo::UnsignedLong; 1913 PtrDiffType = TargetInfo::SignedLong; 1914 IntPtrType = TargetInfo::SignedLong; 1915 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1916 } 1917 }; 1918 1919 static const unsigned AMDGPUAddrSpaceMap[] = { 1920 1, // opencl_global 1921 3, // opencl_local 1922 2, // opencl_constant 1923 4, // opencl_generic 1924 1, // cuda_device 1925 2, // cuda_constant 1926 3 // cuda_shared 1927 }; 1928 1929 // If you edit the description strings, make sure you update 1930 // getPointerWidthV(). 1931 1932 static const char *const DataLayoutStringR600 = 1933 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1934 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1935 1936 static const char *const DataLayoutStringSI = 1937 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 1938 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1939 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1940 1941 class AMDGPUTargetInfo final : public TargetInfo { 1942 static const Builtin::Info BuiltinInfo[]; 1943 static const char * const GCCRegNames[]; 1944 1945 /// \brief The GPU profiles supported by the AMDGPU target. 1946 enum GPUKind { 1947 GK_NONE, 1948 GK_R600, 1949 GK_R600_DOUBLE_OPS, 1950 GK_R700, 1951 GK_R700_DOUBLE_OPS, 1952 GK_EVERGREEN, 1953 GK_EVERGREEN_DOUBLE_OPS, 1954 GK_NORTHERN_ISLANDS, 1955 GK_CAYMAN, 1956 GK_SOUTHERN_ISLANDS, 1957 GK_SEA_ISLANDS, 1958 GK_VOLCANIC_ISLANDS 1959 } GPU; 1960 1961 bool hasFP64:1; 1962 bool hasFMAF:1; 1963 bool hasLDEXPF:1; 1964 bool hasDenormSupport:1; 1965 1966 static bool isAMDGCN(const llvm::Triple &TT) { 1967 return TT.getArch() == llvm::Triple::amdgcn; 1968 } 1969 1970 public: 1971 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1972 : TargetInfo(Triple) , 1973 GPU(isAMDGCN(Triple) ? GK_SOUTHERN_ISLANDS : GK_R600), 1974 hasFP64(false), 1975 hasFMAF(false), 1976 hasLDEXPF(false), 1977 hasDenormSupport(false){ 1978 if (getTriple().getArch() == llvm::Triple::amdgcn) { 1979 hasFP64 = true; 1980 hasFMAF = true; 1981 hasLDEXPF = true; 1982 } 1983 if (Opts.CPU == "fiji") 1984 hasDenormSupport = true; 1985 1986 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 1987 DataLayoutStringSI : DataLayoutStringR600); 1988 1989 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1990 UseAddrSpaceMapMangling = true; 1991 } 1992 1993 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1994 if (GPU <= GK_CAYMAN) 1995 return 32; 1996 1997 switch(AddrSpace) { 1998 default: 1999 return 64; 2000 case 0: 2001 case 3: 2002 case 5: 2003 return 32; 2004 } 2005 } 2006 2007 uint64_t getMaxPointerWidth() const override { 2008 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2009 } 2010 2011 const char * getClobbers() const override { 2012 return ""; 2013 } 2014 2015 ArrayRef<const char *> getGCCRegNames() const override; 2016 2017 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2018 return None; 2019 } 2020 2021 bool validateAsmConstraint(const char *&Name, 2022 TargetInfo::ConstraintInfo &Info) const override { 2023 switch (*Name) { 2024 default: break; 2025 case 'v': // vgpr 2026 case 's': // sgpr 2027 Info.setAllowsRegister(); 2028 return true; 2029 } 2030 return false; 2031 } 2032 2033 bool initFeatureMap(llvm::StringMap<bool> &Features, 2034 DiagnosticsEngine &Diags, StringRef CPU, 2035 const std::vector<std::string> &FeatureVec) const override; 2036 2037 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2038 TargetOptions &TargetOpts) const override { 2039 if (!hasDenormSupport) 2040 return; 2041 bool hasFP32Denormals = false; 2042 bool hasFP64Denormals = false; 2043 for (auto &I : TargetOpts.FeaturesAsWritten) { 2044 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2045 hasFP32Denormals = true; 2046 if (I == "+fp64-denormals" || I == "-fp64-denormals") 2047 hasFP64Denormals = true; 2048 } 2049 if (!hasFP32Denormals) 2050 TargetOpts.Features.push_back((Twine(CGOpts.FlushDenorm ? '-' : '+') + 2051 Twine("fp32-denormals")).str()); 2052 if (!hasFP64Denormals && hasFP64) 2053 TargetOpts.Features.push_back((Twine(CGOpts.FlushDenorm ? '-' : '+') + 2054 Twine("fp64-denormals")).str()); 2055 } 2056 2057 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2058 return llvm::makeArrayRef(BuiltinInfo, 2059 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2060 } 2061 2062 void getTargetDefines(const LangOptions &Opts, 2063 MacroBuilder &Builder) const override { 2064 if (getTriple().getArch() == llvm::Triple::amdgcn) 2065 Builder.defineMacro("__AMDGCN__"); 2066 else 2067 Builder.defineMacro("__R600__"); 2068 2069 if (hasFMAF) 2070 Builder.defineMacro("__HAS_FMAF__"); 2071 if (hasLDEXPF) 2072 Builder.defineMacro("__HAS_LDEXPF__"); 2073 if (hasFP64) 2074 Builder.defineMacro("__HAS_FP64__"); 2075 } 2076 2077 BuiltinVaListKind getBuiltinVaListKind() const override { 2078 return TargetInfo::CharPtrBuiltinVaList; 2079 } 2080 2081 static GPUKind parseR600Name(StringRef Name) { 2082 return llvm::StringSwitch<GPUKind>(Name) 2083 .Case("r600" , GK_R600) 2084 .Case("rv610", GK_R600) 2085 .Case("rv620", GK_R600) 2086 .Case("rv630", GK_R600) 2087 .Case("rv635", GK_R600) 2088 .Case("rs780", GK_R600) 2089 .Case("rs880", GK_R600) 2090 .Case("rv670", GK_R600_DOUBLE_OPS) 2091 .Case("rv710", GK_R700) 2092 .Case("rv730", GK_R700) 2093 .Case("rv740", GK_R700_DOUBLE_OPS) 2094 .Case("rv770", GK_R700_DOUBLE_OPS) 2095 .Case("palm", GK_EVERGREEN) 2096 .Case("cedar", GK_EVERGREEN) 2097 .Case("sumo", GK_EVERGREEN) 2098 .Case("sumo2", GK_EVERGREEN) 2099 .Case("redwood", GK_EVERGREEN) 2100 .Case("juniper", GK_EVERGREEN) 2101 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2102 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2103 .Case("barts", GK_NORTHERN_ISLANDS) 2104 .Case("turks", GK_NORTHERN_ISLANDS) 2105 .Case("caicos", GK_NORTHERN_ISLANDS) 2106 .Case("cayman", GK_CAYMAN) 2107 .Case("aruba", GK_CAYMAN) 2108 .Default(GK_NONE); 2109 } 2110 2111 static GPUKind parseAMDGCNName(StringRef Name) { 2112 return llvm::StringSwitch<GPUKind>(Name) 2113 .Case("tahiti", GK_SOUTHERN_ISLANDS) 2114 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 2115 .Case("verde", GK_SOUTHERN_ISLANDS) 2116 .Case("oland", GK_SOUTHERN_ISLANDS) 2117 .Case("hainan", GK_SOUTHERN_ISLANDS) 2118 .Case("bonaire", GK_SEA_ISLANDS) 2119 .Case("kabini", GK_SEA_ISLANDS) 2120 .Case("kaveri", GK_SEA_ISLANDS) 2121 .Case("hawaii", GK_SEA_ISLANDS) 2122 .Case("mullins", GK_SEA_ISLANDS) 2123 .Case("tonga", GK_VOLCANIC_ISLANDS) 2124 .Case("iceland", GK_VOLCANIC_ISLANDS) 2125 .Case("carrizo", GK_VOLCANIC_ISLANDS) 2126 .Case("fiji", GK_VOLCANIC_ISLANDS) 2127 .Case("stoney", GK_VOLCANIC_ISLANDS) 2128 .Case("polaris10", GK_VOLCANIC_ISLANDS) 2129 .Case("polaris11", GK_VOLCANIC_ISLANDS) 2130 .Default(GK_NONE); 2131 } 2132 2133 bool setCPU(const std::string &Name) override { 2134 if (getTriple().getArch() == llvm::Triple::amdgcn) 2135 GPU = parseAMDGCNName(Name); 2136 else 2137 GPU = parseR600Name(Name); 2138 2139 return GPU != GK_NONE; 2140 } 2141 2142 void setSupportedOpenCLOpts() override { 2143 auto &Opts = getSupportedOpenCLOpts(); 2144 Opts.cl_clang_storage_class_specifiers = 1; 2145 Opts.cl_khr_icd = 1; 2146 2147 if (hasFP64) 2148 Opts.cl_khr_fp64 = 1; 2149 if (GPU >= GK_EVERGREEN) { 2150 Opts.cl_khr_byte_addressable_store = 1; 2151 Opts.cl_khr_global_int32_base_atomics = 1; 2152 Opts.cl_khr_global_int32_extended_atomics = 1; 2153 Opts.cl_khr_local_int32_base_atomics = 1; 2154 Opts.cl_khr_local_int32_extended_atomics = 1; 2155 } 2156 if (GPU >= GK_SOUTHERN_ISLANDS) { 2157 Opts.cl_khr_fp16 = 1; 2158 Opts.cl_khr_int64_base_atomics = 1; 2159 Opts.cl_khr_int64_extended_atomics = 1; 2160 Opts.cl_khr_mipmap_image = 1; 2161 Opts.cl_khr_subgroups = 1; 2162 Opts.cl_khr_3d_image_writes = 1; 2163 Opts.cl_amd_media_ops = 1; 2164 Opts.cl_amd_media_ops2 = 1; 2165 } 2166 } 2167 2168 LangAS::ID getOpenCLImageAddrSpace() const override { 2169 return LangAS::opencl_constant; 2170 } 2171 2172 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2173 switch (CC) { 2174 default: 2175 return CCCR_Warning; 2176 case CC_C: 2177 case CC_OpenCLKernel: 2178 return CCCR_OK; 2179 } 2180 } 2181 }; 2182 2183 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2184 #define BUILTIN(ID, TYPE, ATTRS) \ 2185 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2186 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2187 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2188 #include "clang/Basic/BuiltinsAMDGPU.def" 2189 }; 2190 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2191 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2192 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2193 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2194 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2195 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2196 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2197 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2198 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2199 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2200 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2201 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2202 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2203 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2204 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2205 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2206 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2207 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2208 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2209 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2210 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2211 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2212 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2213 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2214 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2215 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2216 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2217 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2218 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2219 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2220 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2221 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2222 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2223 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2224 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2225 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2226 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2227 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2228 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2229 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2230 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2231 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2232 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2233 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2234 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2235 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2236 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2237 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2238 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2239 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2240 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2241 }; 2242 2243 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2244 return llvm::makeArrayRef(GCCRegNames); 2245 } 2246 2247 bool AMDGPUTargetInfo::initFeatureMap( 2248 llvm::StringMap<bool> &Features, 2249 DiagnosticsEngine &Diags, StringRef CPU, 2250 const std::vector<std::string> &FeatureVec) const { 2251 2252 // XXX - What does the member GPU mean if device name string passed here? 2253 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2254 if (CPU.empty()) 2255 CPU = "tahiti"; 2256 2257 switch (parseAMDGCNName(CPU)) { 2258 case GK_SOUTHERN_ISLANDS: 2259 case GK_SEA_ISLANDS: 2260 break; 2261 2262 case GK_VOLCANIC_ISLANDS: 2263 Features["s-memrealtime"] = true; 2264 Features["16-bit-insts"] = true; 2265 break; 2266 2267 case GK_NONE: 2268 return false; 2269 default: 2270 llvm_unreachable("unhandled subtarget"); 2271 } 2272 } else { 2273 if (CPU.empty()) 2274 CPU = "r600"; 2275 2276 switch (parseR600Name(CPU)) { 2277 case GK_R600: 2278 case GK_R700: 2279 case GK_EVERGREEN: 2280 case GK_NORTHERN_ISLANDS: 2281 break; 2282 case GK_R600_DOUBLE_OPS: 2283 case GK_R700_DOUBLE_OPS: 2284 case GK_EVERGREEN_DOUBLE_OPS: 2285 case GK_CAYMAN: 2286 Features["fp64"] = true; 2287 break; 2288 case GK_NONE: 2289 return false; 2290 default: 2291 llvm_unreachable("unhandled subtarget"); 2292 } 2293 } 2294 2295 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2296 } 2297 2298 // Namespace for x86 abstract base class 2299 const Builtin::Info BuiltinInfo[] = { 2300 #define BUILTIN(ID, TYPE, ATTRS) \ 2301 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2302 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2303 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2304 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2305 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2306 #include "clang/Basic/BuiltinsX86.def" 2307 }; 2308 2309 static const char* const GCCRegNames[] = { 2310 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2311 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2312 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2313 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2314 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2315 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2316 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2317 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2318 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2319 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2320 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2321 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2322 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2323 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2324 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2325 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2326 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2327 }; 2328 2329 const TargetInfo::AddlRegName AddlRegNames[] = { 2330 { { "al", "ah", "eax", "rax" }, 0 }, 2331 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2332 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2333 { { "dl", "dh", "edx", "rdx" }, 1 }, 2334 { { "esi", "rsi" }, 4 }, 2335 { { "edi", "rdi" }, 5 }, 2336 { { "esp", "rsp" }, 7 }, 2337 { { "ebp", "rbp" }, 6 }, 2338 { { "r8d", "r8w", "r8b" }, 38 }, 2339 { { "r9d", "r9w", "r9b" }, 39 }, 2340 { { "r10d", "r10w", "r10b" }, 40 }, 2341 { { "r11d", "r11w", "r11b" }, 41 }, 2342 { { "r12d", "r12w", "r12b" }, 42 }, 2343 { { "r13d", "r13w", "r13b" }, 43 }, 2344 { { "r14d", "r14w", "r14b" }, 44 }, 2345 { { "r15d", "r15w", "r15b" }, 45 }, 2346 }; 2347 2348 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2349 // most of the implementation can be shared. 2350 class X86TargetInfo : public TargetInfo { 2351 enum X86SSEEnum { 2352 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2353 } SSELevel = NoSSE; 2354 enum MMX3DNowEnum { 2355 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2356 } MMX3DNowLevel = NoMMX3DNow; 2357 enum XOPEnum { 2358 NoXOP, 2359 SSE4A, 2360 FMA4, 2361 XOP 2362 } XOPLevel = NoXOP; 2363 2364 bool HasAES = false; 2365 bool HasPCLMUL = false; 2366 bool HasLZCNT = false; 2367 bool HasRDRND = false; 2368 bool HasFSGSBASE = false; 2369 bool HasBMI = false; 2370 bool HasBMI2 = false; 2371 bool HasPOPCNT = false; 2372 bool HasRTM = false; 2373 bool HasPRFCHW = false; 2374 bool HasRDSEED = false; 2375 bool HasADX = false; 2376 bool HasTBM = false; 2377 bool HasFMA = false; 2378 bool HasF16C = false; 2379 bool HasAVX512CD = false; 2380 bool HasAVX512ER = false; 2381 bool HasAVX512PF = false; 2382 bool HasAVX512DQ = false; 2383 bool HasAVX512BW = false; 2384 bool HasAVX512VL = false; 2385 bool HasAVX512VBMI = false; 2386 bool HasAVX512IFMA = false; 2387 bool HasSHA = false; 2388 bool HasMPX = false; 2389 bool HasSGX = false; 2390 bool HasCX16 = false; 2391 bool HasFXSR = false; 2392 bool HasXSAVE = false; 2393 bool HasXSAVEOPT = false; 2394 bool HasXSAVEC = false; 2395 bool HasXSAVES = false; 2396 bool HasMWAITX = false; 2397 bool HasPKU = false; 2398 bool HasCLFLUSHOPT = false; 2399 bool HasPCOMMIT = false; 2400 bool HasCLWB = false; 2401 bool HasUMIP = false; 2402 bool HasMOVBE = false; 2403 bool HasPREFETCHWT1 = false; 2404 2405 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2406 /// 2407 /// Each enumeration represents a particular CPU supported by Clang. These 2408 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2409 enum CPUKind { 2410 CK_Generic, 2411 2412 /// \name i386 2413 /// i386-generation processors. 2414 //@{ 2415 CK_i386, 2416 //@} 2417 2418 /// \name i486 2419 /// i486-generation processors. 2420 //@{ 2421 CK_i486, 2422 CK_WinChipC6, 2423 CK_WinChip2, 2424 CK_C3, 2425 //@} 2426 2427 /// \name i586 2428 /// i586-generation processors, P5 microarchitecture based. 2429 //@{ 2430 CK_i586, 2431 CK_Pentium, 2432 CK_PentiumMMX, 2433 //@} 2434 2435 /// \name i686 2436 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2437 //@{ 2438 CK_i686, 2439 CK_PentiumPro, 2440 CK_Pentium2, 2441 CK_Pentium3, 2442 CK_Pentium3M, 2443 CK_PentiumM, 2444 CK_C3_2, 2445 2446 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2447 /// Clang however has some logic to suport this. 2448 // FIXME: Warn, deprecate, and potentially remove this. 2449 CK_Yonah, 2450 //@} 2451 2452 /// \name Netburst 2453 /// Netburst microarchitecture based processors. 2454 //@{ 2455 CK_Pentium4, 2456 CK_Pentium4M, 2457 CK_Prescott, 2458 CK_Nocona, 2459 //@} 2460 2461 /// \name Core 2462 /// Core microarchitecture based processors. 2463 //@{ 2464 CK_Core2, 2465 2466 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2467 /// codename which GCC no longer accepts as an option to -march, but Clang 2468 /// has some logic for recognizing it. 2469 // FIXME: Warn, deprecate, and potentially remove this. 2470 CK_Penryn, 2471 //@} 2472 2473 /// \name Atom 2474 /// Atom processors 2475 //@{ 2476 CK_Bonnell, 2477 CK_Silvermont, 2478 //@} 2479 2480 /// \name Nehalem 2481 /// Nehalem microarchitecture based processors. 2482 CK_Nehalem, 2483 2484 /// \name Westmere 2485 /// Westmere microarchitecture based processors. 2486 CK_Westmere, 2487 2488 /// \name Sandy Bridge 2489 /// Sandy Bridge microarchitecture based processors. 2490 CK_SandyBridge, 2491 2492 /// \name Ivy Bridge 2493 /// Ivy Bridge microarchitecture based processors. 2494 CK_IvyBridge, 2495 2496 /// \name Haswell 2497 /// Haswell microarchitecture based processors. 2498 CK_Haswell, 2499 2500 /// \name Broadwell 2501 /// Broadwell microarchitecture based processors. 2502 CK_Broadwell, 2503 2504 /// \name Skylake Client 2505 /// Skylake client microarchitecture based processors. 2506 CK_SkylakeClient, 2507 2508 /// \name Skylake Server 2509 /// Skylake server microarchitecture based processors. 2510 CK_SkylakeServer, 2511 2512 /// \name Cannonlake Client 2513 /// Cannonlake client microarchitecture based processors. 2514 CK_Cannonlake, 2515 2516 /// \name Knights Landing 2517 /// Knights Landing processor. 2518 CK_KNL, 2519 2520 /// \name Lakemont 2521 /// Lakemont microarchitecture based processors. 2522 CK_Lakemont, 2523 2524 /// \name K6 2525 /// K6 architecture processors. 2526 //@{ 2527 CK_K6, 2528 CK_K6_2, 2529 CK_K6_3, 2530 //@} 2531 2532 /// \name K7 2533 /// K7 architecture processors. 2534 //@{ 2535 CK_Athlon, 2536 CK_AthlonThunderbird, 2537 CK_Athlon4, 2538 CK_AthlonXP, 2539 CK_AthlonMP, 2540 //@} 2541 2542 /// \name K8 2543 /// K8 architecture processors. 2544 //@{ 2545 CK_Athlon64, 2546 CK_Athlon64SSE3, 2547 CK_AthlonFX, 2548 CK_K8, 2549 CK_K8SSE3, 2550 CK_Opteron, 2551 CK_OpteronSSE3, 2552 CK_AMDFAM10, 2553 //@} 2554 2555 /// \name Bobcat 2556 /// Bobcat architecture processors. 2557 //@{ 2558 CK_BTVER1, 2559 CK_BTVER2, 2560 //@} 2561 2562 /// \name Bulldozer 2563 /// Bulldozer architecture processors. 2564 //@{ 2565 CK_BDVER1, 2566 CK_BDVER2, 2567 CK_BDVER3, 2568 CK_BDVER4, 2569 //@} 2570 2571 /// This specification is deprecated and will be removed in the future. 2572 /// Users should prefer \see CK_K8. 2573 // FIXME: Warn on this when the CPU is set to it. 2574 //@{ 2575 CK_x86_64, 2576 //@} 2577 2578 /// \name Geode 2579 /// Geode processors. 2580 //@{ 2581 CK_Geode 2582 //@} 2583 } CPU = CK_Generic; 2584 2585 CPUKind getCPUKind(StringRef CPU) const { 2586 return llvm::StringSwitch<CPUKind>(CPU) 2587 .Case("i386", CK_i386) 2588 .Case("i486", CK_i486) 2589 .Case("winchip-c6", CK_WinChipC6) 2590 .Case("winchip2", CK_WinChip2) 2591 .Case("c3", CK_C3) 2592 .Case("i586", CK_i586) 2593 .Case("pentium", CK_Pentium) 2594 .Case("pentium-mmx", CK_PentiumMMX) 2595 .Case("i686", CK_i686) 2596 .Case("pentiumpro", CK_PentiumPro) 2597 .Case("pentium2", CK_Pentium2) 2598 .Case("pentium3", CK_Pentium3) 2599 .Case("pentium3m", CK_Pentium3M) 2600 .Case("pentium-m", CK_PentiumM) 2601 .Case("c3-2", CK_C3_2) 2602 .Case("yonah", CK_Yonah) 2603 .Case("pentium4", CK_Pentium4) 2604 .Case("pentium4m", CK_Pentium4M) 2605 .Case("prescott", CK_Prescott) 2606 .Case("nocona", CK_Nocona) 2607 .Case("core2", CK_Core2) 2608 .Case("penryn", CK_Penryn) 2609 .Case("bonnell", CK_Bonnell) 2610 .Case("atom", CK_Bonnell) // Legacy name. 2611 .Case("silvermont", CK_Silvermont) 2612 .Case("slm", CK_Silvermont) // Legacy name. 2613 .Case("nehalem", CK_Nehalem) 2614 .Case("corei7", CK_Nehalem) // Legacy name. 2615 .Case("westmere", CK_Westmere) 2616 .Case("sandybridge", CK_SandyBridge) 2617 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2618 .Case("ivybridge", CK_IvyBridge) 2619 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2620 .Case("haswell", CK_Haswell) 2621 .Case("core-avx2", CK_Haswell) // Legacy name. 2622 .Case("broadwell", CK_Broadwell) 2623 .Case("skylake", CK_SkylakeClient) 2624 .Case("skylake-avx512", CK_SkylakeServer) 2625 .Case("skx", CK_SkylakeServer) // Legacy name. 2626 .Case("cannonlake", CK_Cannonlake) 2627 .Case("knl", CK_KNL) 2628 .Case("lakemont", CK_Lakemont) 2629 .Case("k6", CK_K6) 2630 .Case("k6-2", CK_K6_2) 2631 .Case("k6-3", CK_K6_3) 2632 .Case("athlon", CK_Athlon) 2633 .Case("athlon-tbird", CK_AthlonThunderbird) 2634 .Case("athlon-4", CK_Athlon4) 2635 .Case("athlon-xp", CK_AthlonXP) 2636 .Case("athlon-mp", CK_AthlonMP) 2637 .Case("athlon64", CK_Athlon64) 2638 .Case("athlon64-sse3", CK_Athlon64SSE3) 2639 .Case("athlon-fx", CK_AthlonFX) 2640 .Case("k8", CK_K8) 2641 .Case("k8-sse3", CK_K8SSE3) 2642 .Case("opteron", CK_Opteron) 2643 .Case("opteron-sse3", CK_OpteronSSE3) 2644 .Case("barcelona", CK_AMDFAM10) 2645 .Case("amdfam10", CK_AMDFAM10) 2646 .Case("btver1", CK_BTVER1) 2647 .Case("btver2", CK_BTVER2) 2648 .Case("bdver1", CK_BDVER1) 2649 .Case("bdver2", CK_BDVER2) 2650 .Case("bdver3", CK_BDVER3) 2651 .Case("bdver4", CK_BDVER4) 2652 .Case("x86-64", CK_x86_64) 2653 .Case("geode", CK_Geode) 2654 .Default(CK_Generic); 2655 } 2656 2657 enum FPMathKind { 2658 FP_Default, 2659 FP_SSE, 2660 FP_387 2661 } FPMath = FP_Default; 2662 2663 public: 2664 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2665 : TargetInfo(Triple) { 2666 BigEndian = false; 2667 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2668 } 2669 unsigned getFloatEvalMethod() const override { 2670 // X87 evaluates with 80 bits "long double" precision. 2671 return SSELevel == NoSSE ? 2 : 0; 2672 } 2673 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2674 return llvm::makeArrayRef(BuiltinInfo, 2675 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2676 } 2677 ArrayRef<const char *> getGCCRegNames() const override { 2678 return llvm::makeArrayRef(GCCRegNames); 2679 } 2680 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2681 return None; 2682 } 2683 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2684 return llvm::makeArrayRef(AddlRegNames); 2685 } 2686 bool validateCpuSupports(StringRef Name) const override; 2687 bool validateAsmConstraint(const char *&Name, 2688 TargetInfo::ConstraintInfo &info) const override; 2689 2690 bool validateGlobalRegisterVariable(StringRef RegName, 2691 unsigned RegSize, 2692 bool &HasSizeMismatch) const override { 2693 // esp and ebp are the only 32-bit registers the x86 backend can currently 2694 // handle. 2695 if (RegName.equals("esp") || RegName.equals("ebp")) { 2696 // Check that the register size is 32-bit. 2697 HasSizeMismatch = RegSize != 32; 2698 return true; 2699 } 2700 2701 return false; 2702 } 2703 2704 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2705 2706 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2707 2708 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2709 2710 std::string convertConstraint(const char *&Constraint) const override; 2711 const char *getClobbers() const override { 2712 return "~{dirflag},~{fpsr},~{flags}"; 2713 } 2714 void getTargetDefines(const LangOptions &Opts, 2715 MacroBuilder &Builder) const override; 2716 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2717 bool Enabled); 2718 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2719 bool Enabled); 2720 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2721 bool Enabled); 2722 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2723 StringRef Name, bool Enabled) const override { 2724 setFeatureEnabledImpl(Features, Name, Enabled); 2725 } 2726 // This exists purely to cut down on the number of virtual calls in 2727 // initFeatureMap which calls this repeatedly. 2728 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2729 StringRef Name, bool Enabled); 2730 bool 2731 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2732 StringRef CPU, 2733 const std::vector<std::string> &FeaturesVec) const override; 2734 bool hasFeature(StringRef Feature) const override; 2735 bool handleTargetFeatures(std::vector<std::string> &Features, 2736 DiagnosticsEngine &Diags) override; 2737 StringRef getABI() const override { 2738 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2739 return "avx512"; 2740 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2741 return "avx"; 2742 if (getTriple().getArch() == llvm::Triple::x86 && 2743 MMX3DNowLevel == NoMMX3DNow) 2744 return "no-mmx"; 2745 return ""; 2746 } 2747 bool setCPU(const std::string &Name) override { 2748 CPU = getCPUKind(Name); 2749 2750 // Perform any per-CPU checks necessary to determine if this CPU is 2751 // acceptable. 2752 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2753 // invalid without explaining *why*. 2754 switch (CPU) { 2755 case CK_Generic: 2756 // No processor selected! 2757 return false; 2758 2759 case CK_i386: 2760 case CK_i486: 2761 case CK_WinChipC6: 2762 case CK_WinChip2: 2763 case CK_C3: 2764 case CK_i586: 2765 case CK_Pentium: 2766 case CK_PentiumMMX: 2767 case CK_i686: 2768 case CK_PentiumPro: 2769 case CK_Pentium2: 2770 case CK_Pentium3: 2771 case CK_Pentium3M: 2772 case CK_PentiumM: 2773 case CK_Yonah: 2774 case CK_C3_2: 2775 case CK_Pentium4: 2776 case CK_Pentium4M: 2777 case CK_Lakemont: 2778 case CK_Prescott: 2779 case CK_K6: 2780 case CK_K6_2: 2781 case CK_K6_3: 2782 case CK_Athlon: 2783 case CK_AthlonThunderbird: 2784 case CK_Athlon4: 2785 case CK_AthlonXP: 2786 case CK_AthlonMP: 2787 case CK_Geode: 2788 // Only accept certain architectures when compiling in 32-bit mode. 2789 if (getTriple().getArch() != llvm::Triple::x86) 2790 return false; 2791 2792 // Fallthrough 2793 case CK_Nocona: 2794 case CK_Core2: 2795 case CK_Penryn: 2796 case CK_Bonnell: 2797 case CK_Silvermont: 2798 case CK_Nehalem: 2799 case CK_Westmere: 2800 case CK_SandyBridge: 2801 case CK_IvyBridge: 2802 case CK_Haswell: 2803 case CK_Broadwell: 2804 case CK_SkylakeClient: 2805 case CK_SkylakeServer: 2806 case CK_Cannonlake: 2807 case CK_KNL: 2808 case CK_Athlon64: 2809 case CK_Athlon64SSE3: 2810 case CK_AthlonFX: 2811 case CK_K8: 2812 case CK_K8SSE3: 2813 case CK_Opteron: 2814 case CK_OpteronSSE3: 2815 case CK_AMDFAM10: 2816 case CK_BTVER1: 2817 case CK_BTVER2: 2818 case CK_BDVER1: 2819 case CK_BDVER2: 2820 case CK_BDVER3: 2821 case CK_BDVER4: 2822 case CK_x86_64: 2823 return true; 2824 } 2825 llvm_unreachable("Unhandled CPU kind"); 2826 } 2827 2828 bool setFPMath(StringRef Name) override; 2829 2830 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2831 // Most of the non-ARM calling conventions are i386 conventions. 2832 switch (CC) { 2833 case CC_X86ThisCall: 2834 case CC_X86FastCall: 2835 case CC_X86StdCall: 2836 case CC_X86VectorCall: 2837 case CC_C: 2838 case CC_Swift: 2839 case CC_X86Pascal: 2840 case CC_IntelOclBicc: 2841 return CCCR_OK; 2842 default: 2843 return CCCR_Warning; 2844 } 2845 } 2846 2847 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2848 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2849 } 2850 2851 bool hasSjLjLowering() const override { 2852 return true; 2853 } 2854 2855 void setSupportedOpenCLOpts() override { 2856 getSupportedOpenCLOpts().setAll(); 2857 } 2858 }; 2859 2860 bool X86TargetInfo::setFPMath(StringRef Name) { 2861 if (Name == "387") { 2862 FPMath = FP_387; 2863 return true; 2864 } 2865 if (Name == "sse") { 2866 FPMath = FP_SSE; 2867 return true; 2868 } 2869 return false; 2870 } 2871 2872 bool X86TargetInfo::initFeatureMap( 2873 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2874 const std::vector<std::string> &FeaturesVec) const { 2875 // FIXME: This *really* should not be here. 2876 // X86_64 always has SSE2. 2877 if (getTriple().getArch() == llvm::Triple::x86_64) 2878 setFeatureEnabledImpl(Features, "sse2", true); 2879 2880 const CPUKind Kind = getCPUKind(CPU); 2881 2882 // Enable X87 for all X86 processors but Lakemont. 2883 if (Kind != CK_Lakemont) 2884 setFeatureEnabledImpl(Features, "x87", true); 2885 2886 switch (Kind) { 2887 case CK_Generic: 2888 case CK_i386: 2889 case CK_i486: 2890 case CK_i586: 2891 case CK_Pentium: 2892 case CK_i686: 2893 case CK_PentiumPro: 2894 case CK_Lakemont: 2895 break; 2896 case CK_PentiumMMX: 2897 case CK_Pentium2: 2898 case CK_K6: 2899 case CK_WinChipC6: 2900 setFeatureEnabledImpl(Features, "mmx", true); 2901 break; 2902 case CK_Pentium3: 2903 case CK_Pentium3M: 2904 case CK_C3_2: 2905 setFeatureEnabledImpl(Features, "sse", true); 2906 setFeatureEnabledImpl(Features, "fxsr", true); 2907 break; 2908 case CK_PentiumM: 2909 case CK_Pentium4: 2910 case CK_Pentium4M: 2911 case CK_x86_64: 2912 setFeatureEnabledImpl(Features, "sse2", true); 2913 setFeatureEnabledImpl(Features, "fxsr", true); 2914 break; 2915 case CK_Yonah: 2916 case CK_Prescott: 2917 case CK_Nocona: 2918 setFeatureEnabledImpl(Features, "sse3", true); 2919 setFeatureEnabledImpl(Features, "fxsr", true); 2920 setFeatureEnabledImpl(Features, "cx16", true); 2921 break; 2922 case CK_Core2: 2923 case CK_Bonnell: 2924 setFeatureEnabledImpl(Features, "ssse3", true); 2925 setFeatureEnabledImpl(Features, "fxsr", true); 2926 setFeatureEnabledImpl(Features, "cx16", true); 2927 break; 2928 case CK_Penryn: 2929 setFeatureEnabledImpl(Features, "sse4.1", true); 2930 setFeatureEnabledImpl(Features, "fxsr", true); 2931 setFeatureEnabledImpl(Features, "cx16", true); 2932 break; 2933 case CK_Cannonlake: 2934 setFeatureEnabledImpl(Features, "avx512ifma", true); 2935 setFeatureEnabledImpl(Features, "avx512vbmi", true); 2936 setFeatureEnabledImpl(Features, "sha", true); 2937 setFeatureEnabledImpl(Features, "umip", true); 2938 // FALLTHROUGH 2939 case CK_SkylakeServer: 2940 setFeatureEnabledImpl(Features, "avx512f", true); 2941 setFeatureEnabledImpl(Features, "avx512cd", true); 2942 setFeatureEnabledImpl(Features, "avx512dq", true); 2943 setFeatureEnabledImpl(Features, "avx512bw", true); 2944 setFeatureEnabledImpl(Features, "avx512vl", true); 2945 setFeatureEnabledImpl(Features, "pku", true); 2946 setFeatureEnabledImpl(Features, "pcommit", true); 2947 setFeatureEnabledImpl(Features, "clwb", true); 2948 // FALLTHROUGH 2949 case CK_SkylakeClient: 2950 setFeatureEnabledImpl(Features, "xsavec", true); 2951 setFeatureEnabledImpl(Features, "xsaves", true); 2952 setFeatureEnabledImpl(Features, "mpx", true); 2953 setFeatureEnabledImpl(Features, "sgx", true); 2954 setFeatureEnabledImpl(Features, "clflushopt", true); 2955 // FALLTHROUGH 2956 case CK_Broadwell: 2957 setFeatureEnabledImpl(Features, "rdseed", true); 2958 setFeatureEnabledImpl(Features, "adx", true); 2959 // FALLTHROUGH 2960 case CK_Haswell: 2961 setFeatureEnabledImpl(Features, "avx2", true); 2962 setFeatureEnabledImpl(Features, "lzcnt", true); 2963 setFeatureEnabledImpl(Features, "bmi", true); 2964 setFeatureEnabledImpl(Features, "bmi2", true); 2965 setFeatureEnabledImpl(Features, "rtm", true); 2966 setFeatureEnabledImpl(Features, "fma", true); 2967 setFeatureEnabledImpl(Features, "movbe", true); 2968 // FALLTHROUGH 2969 case CK_IvyBridge: 2970 setFeatureEnabledImpl(Features, "rdrnd", true); 2971 setFeatureEnabledImpl(Features, "f16c", true); 2972 setFeatureEnabledImpl(Features, "fsgsbase", true); 2973 // FALLTHROUGH 2974 case CK_SandyBridge: 2975 setFeatureEnabledImpl(Features, "avx", true); 2976 setFeatureEnabledImpl(Features, "xsave", true); 2977 setFeatureEnabledImpl(Features, "xsaveopt", true); 2978 // FALLTHROUGH 2979 case CK_Westmere: 2980 case CK_Silvermont: 2981 setFeatureEnabledImpl(Features, "aes", true); 2982 setFeatureEnabledImpl(Features, "pclmul", true); 2983 // FALLTHROUGH 2984 case CK_Nehalem: 2985 setFeatureEnabledImpl(Features, "sse4.2", true); 2986 setFeatureEnabledImpl(Features, "fxsr", true); 2987 setFeatureEnabledImpl(Features, "cx16", true); 2988 break; 2989 case CK_KNL: 2990 setFeatureEnabledImpl(Features, "avx512f", true); 2991 setFeatureEnabledImpl(Features, "avx512cd", true); 2992 setFeatureEnabledImpl(Features, "avx512er", true); 2993 setFeatureEnabledImpl(Features, "avx512pf", true); 2994 setFeatureEnabledImpl(Features, "prefetchwt1", true); 2995 setFeatureEnabledImpl(Features, "fxsr", true); 2996 setFeatureEnabledImpl(Features, "rdseed", true); 2997 setFeatureEnabledImpl(Features, "adx", true); 2998 setFeatureEnabledImpl(Features, "lzcnt", true); 2999 setFeatureEnabledImpl(Features, "bmi", true); 3000 setFeatureEnabledImpl(Features, "bmi2", true); 3001 setFeatureEnabledImpl(Features, "rtm", true); 3002 setFeatureEnabledImpl(Features, "fma", true); 3003 setFeatureEnabledImpl(Features, "rdrnd", true); 3004 setFeatureEnabledImpl(Features, "f16c", true); 3005 setFeatureEnabledImpl(Features, "fsgsbase", true); 3006 setFeatureEnabledImpl(Features, "aes", true); 3007 setFeatureEnabledImpl(Features, "pclmul", true); 3008 setFeatureEnabledImpl(Features, "cx16", true); 3009 setFeatureEnabledImpl(Features, "xsaveopt", true); 3010 setFeatureEnabledImpl(Features, "xsave", true); 3011 setFeatureEnabledImpl(Features, "movbe", true); 3012 break; 3013 case CK_K6_2: 3014 case CK_K6_3: 3015 case CK_WinChip2: 3016 case CK_C3: 3017 setFeatureEnabledImpl(Features, "3dnow", true); 3018 break; 3019 case CK_Athlon: 3020 case CK_AthlonThunderbird: 3021 case CK_Geode: 3022 setFeatureEnabledImpl(Features, "3dnowa", true); 3023 break; 3024 case CK_Athlon4: 3025 case CK_AthlonXP: 3026 case CK_AthlonMP: 3027 setFeatureEnabledImpl(Features, "sse", true); 3028 setFeatureEnabledImpl(Features, "3dnowa", true); 3029 setFeatureEnabledImpl(Features, "fxsr", true); 3030 break; 3031 case CK_K8: 3032 case CK_Opteron: 3033 case CK_Athlon64: 3034 case CK_AthlonFX: 3035 setFeatureEnabledImpl(Features, "sse2", true); 3036 setFeatureEnabledImpl(Features, "3dnowa", true); 3037 setFeatureEnabledImpl(Features, "fxsr", true); 3038 break; 3039 case CK_AMDFAM10: 3040 setFeatureEnabledImpl(Features, "sse4a", true); 3041 setFeatureEnabledImpl(Features, "lzcnt", true); 3042 setFeatureEnabledImpl(Features, "popcnt", true); 3043 // FALLTHROUGH 3044 case CK_K8SSE3: 3045 case CK_OpteronSSE3: 3046 case CK_Athlon64SSE3: 3047 setFeatureEnabledImpl(Features, "sse3", true); 3048 setFeatureEnabledImpl(Features, "3dnowa", true); 3049 setFeatureEnabledImpl(Features, "fxsr", true); 3050 break; 3051 case CK_BTVER2: 3052 setFeatureEnabledImpl(Features, "avx", true); 3053 setFeatureEnabledImpl(Features, "aes", true); 3054 setFeatureEnabledImpl(Features, "pclmul", true); 3055 setFeatureEnabledImpl(Features, "bmi", true); 3056 setFeatureEnabledImpl(Features, "f16c", true); 3057 setFeatureEnabledImpl(Features, "xsaveopt", true); 3058 // FALLTHROUGH 3059 case CK_BTVER1: 3060 setFeatureEnabledImpl(Features, "ssse3", true); 3061 setFeatureEnabledImpl(Features, "sse4a", true); 3062 setFeatureEnabledImpl(Features, "lzcnt", true); 3063 setFeatureEnabledImpl(Features, "popcnt", true); 3064 setFeatureEnabledImpl(Features, "prfchw", true); 3065 setFeatureEnabledImpl(Features, "cx16", true); 3066 setFeatureEnabledImpl(Features, "fxsr", true); 3067 break; 3068 case CK_BDVER4: 3069 setFeatureEnabledImpl(Features, "avx2", true); 3070 setFeatureEnabledImpl(Features, "bmi2", true); 3071 setFeatureEnabledImpl(Features, "mwaitx", true); 3072 // FALLTHROUGH 3073 case CK_BDVER3: 3074 setFeatureEnabledImpl(Features, "fsgsbase", true); 3075 setFeatureEnabledImpl(Features, "xsaveopt", true); 3076 // FALLTHROUGH 3077 case CK_BDVER2: 3078 setFeatureEnabledImpl(Features, "bmi", true); 3079 setFeatureEnabledImpl(Features, "fma", true); 3080 setFeatureEnabledImpl(Features, "f16c", true); 3081 setFeatureEnabledImpl(Features, "tbm", true); 3082 // FALLTHROUGH 3083 case CK_BDVER1: 3084 // xop implies avx, sse4a and fma4. 3085 setFeatureEnabledImpl(Features, "xop", true); 3086 setFeatureEnabledImpl(Features, "lzcnt", true); 3087 setFeatureEnabledImpl(Features, "aes", true); 3088 setFeatureEnabledImpl(Features, "pclmul", true); 3089 setFeatureEnabledImpl(Features, "prfchw", true); 3090 setFeatureEnabledImpl(Features, "cx16", true); 3091 setFeatureEnabledImpl(Features, "fxsr", true); 3092 setFeatureEnabledImpl(Features, "xsave", true); 3093 break; 3094 } 3095 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3096 return false; 3097 3098 // Can't do this earlier because we need to be able to explicitly enable 3099 // or disable these features and the things that they depend upon. 3100 3101 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3102 auto I = Features.find("sse4.2"); 3103 if (I != Features.end() && I->getValue() && 3104 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3105 FeaturesVec.end()) 3106 Features["popcnt"] = true; 3107 3108 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3109 I = Features.find("3dnow"); 3110 if (I != Features.end() && I->getValue() && 3111 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3112 FeaturesVec.end()) 3113 Features["prfchw"] = true; 3114 3115 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3116 // then enable MMX. 3117 I = Features.find("sse"); 3118 if (I != Features.end() && I->getValue() && 3119 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3120 FeaturesVec.end()) 3121 Features["mmx"] = true; 3122 3123 return true; 3124 } 3125 3126 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3127 X86SSEEnum Level, bool Enabled) { 3128 if (Enabled) { 3129 switch (Level) { 3130 case AVX512F: 3131 Features["avx512f"] = true; 3132 case AVX2: 3133 Features["avx2"] = true; 3134 case AVX: 3135 Features["avx"] = true; 3136 Features["xsave"] = true; 3137 case SSE42: 3138 Features["sse4.2"] = true; 3139 case SSE41: 3140 Features["sse4.1"] = true; 3141 case SSSE3: 3142 Features["ssse3"] = true; 3143 case SSE3: 3144 Features["sse3"] = true; 3145 case SSE2: 3146 Features["sse2"] = true; 3147 case SSE1: 3148 Features["sse"] = true; 3149 case NoSSE: 3150 break; 3151 } 3152 return; 3153 } 3154 3155 switch (Level) { 3156 case NoSSE: 3157 case SSE1: 3158 Features["sse"] = false; 3159 case SSE2: 3160 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3161 Features["sha"] = false; 3162 case SSE3: 3163 Features["sse3"] = false; 3164 setXOPLevel(Features, NoXOP, false); 3165 case SSSE3: 3166 Features["ssse3"] = false; 3167 case SSE41: 3168 Features["sse4.1"] = false; 3169 case SSE42: 3170 Features["sse4.2"] = false; 3171 case AVX: 3172 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3173 Features["xsaveopt"] = false; 3174 setXOPLevel(Features, FMA4, false); 3175 case AVX2: 3176 Features["avx2"] = false; 3177 case AVX512F: 3178 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3179 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3180 Features["avx512vl"] = Features["avx512vbmi"] = 3181 Features["avx512ifma"] = false; 3182 } 3183 } 3184 3185 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3186 MMX3DNowEnum Level, bool Enabled) { 3187 if (Enabled) { 3188 switch (Level) { 3189 case AMD3DNowAthlon: 3190 Features["3dnowa"] = true; 3191 case AMD3DNow: 3192 Features["3dnow"] = true; 3193 case MMX: 3194 Features["mmx"] = true; 3195 case NoMMX3DNow: 3196 break; 3197 } 3198 return; 3199 } 3200 3201 switch (Level) { 3202 case NoMMX3DNow: 3203 case MMX: 3204 Features["mmx"] = false; 3205 case AMD3DNow: 3206 Features["3dnow"] = false; 3207 case AMD3DNowAthlon: 3208 Features["3dnowa"] = false; 3209 } 3210 } 3211 3212 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3213 bool Enabled) { 3214 if (Enabled) { 3215 switch (Level) { 3216 case XOP: 3217 Features["xop"] = true; 3218 case FMA4: 3219 Features["fma4"] = true; 3220 setSSELevel(Features, AVX, true); 3221 case SSE4A: 3222 Features["sse4a"] = true; 3223 setSSELevel(Features, SSE3, true); 3224 case NoXOP: 3225 break; 3226 } 3227 return; 3228 } 3229 3230 switch (Level) { 3231 case NoXOP: 3232 case SSE4A: 3233 Features["sse4a"] = false; 3234 case FMA4: 3235 Features["fma4"] = false; 3236 case XOP: 3237 Features["xop"] = false; 3238 } 3239 } 3240 3241 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3242 StringRef Name, bool Enabled) { 3243 // This is a bit of a hack to deal with the sse4 target feature when used 3244 // as part of the target attribute. We handle sse4 correctly everywhere 3245 // else. See below for more information on how we handle the sse4 options. 3246 if (Name != "sse4") 3247 Features[Name] = Enabled; 3248 3249 if (Name == "mmx") { 3250 setMMXLevel(Features, MMX, Enabled); 3251 } else if (Name == "sse") { 3252 setSSELevel(Features, SSE1, Enabled); 3253 } else if (Name == "sse2") { 3254 setSSELevel(Features, SSE2, Enabled); 3255 } else if (Name == "sse3") { 3256 setSSELevel(Features, SSE3, Enabled); 3257 } else if (Name == "ssse3") { 3258 setSSELevel(Features, SSSE3, Enabled); 3259 } else if (Name == "sse4.2") { 3260 setSSELevel(Features, SSE42, Enabled); 3261 } else if (Name == "sse4.1") { 3262 setSSELevel(Features, SSE41, Enabled); 3263 } else if (Name == "3dnow") { 3264 setMMXLevel(Features, AMD3DNow, Enabled); 3265 } else if (Name == "3dnowa") { 3266 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3267 } else if (Name == "aes") { 3268 if (Enabled) 3269 setSSELevel(Features, SSE2, Enabled); 3270 } else if (Name == "pclmul") { 3271 if (Enabled) 3272 setSSELevel(Features, SSE2, Enabled); 3273 } else if (Name == "avx") { 3274 setSSELevel(Features, AVX, Enabled); 3275 } else if (Name == "avx2") { 3276 setSSELevel(Features, AVX2, Enabled); 3277 } else if (Name == "avx512f") { 3278 setSSELevel(Features, AVX512F, Enabled); 3279 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3280 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3281 Name == "avx512vbmi" || Name == "avx512ifma") { 3282 if (Enabled) 3283 setSSELevel(Features, AVX512F, Enabled); 3284 } else if (Name == "fma") { 3285 if (Enabled) 3286 setSSELevel(Features, AVX, Enabled); 3287 } else if (Name == "fma4") { 3288 setXOPLevel(Features, FMA4, Enabled); 3289 } else if (Name == "xop") { 3290 setXOPLevel(Features, XOP, Enabled); 3291 } else if (Name == "sse4a") { 3292 setXOPLevel(Features, SSE4A, Enabled); 3293 } else if (Name == "f16c") { 3294 if (Enabled) 3295 setSSELevel(Features, AVX, Enabled); 3296 } else if (Name == "sha") { 3297 if (Enabled) 3298 setSSELevel(Features, SSE2, Enabled); 3299 } else if (Name == "sse4") { 3300 // We can get here via the __target__ attribute since that's not controlled 3301 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3302 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3303 // disabled. 3304 if (Enabled) 3305 setSSELevel(Features, SSE42, Enabled); 3306 else 3307 setSSELevel(Features, SSE41, Enabled); 3308 } else if (Name == "xsave") { 3309 if (!Enabled) 3310 Features["xsaveopt"] = false; 3311 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3312 if (Enabled) 3313 Features["xsave"] = true; 3314 } 3315 } 3316 3317 /// handleTargetFeatures - Perform initialization based on the user 3318 /// configured set of features. 3319 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3320 DiagnosticsEngine &Diags) { 3321 for (const auto &Feature : Features) { 3322 if (Feature[0] != '+') 3323 continue; 3324 3325 if (Feature == "+aes") { 3326 HasAES = true; 3327 } else if (Feature == "+pclmul") { 3328 HasPCLMUL = true; 3329 } else if (Feature == "+lzcnt") { 3330 HasLZCNT = true; 3331 } else if (Feature == "+rdrnd") { 3332 HasRDRND = true; 3333 } else if (Feature == "+fsgsbase") { 3334 HasFSGSBASE = true; 3335 } else if (Feature == "+bmi") { 3336 HasBMI = true; 3337 } else if (Feature == "+bmi2") { 3338 HasBMI2 = true; 3339 } else if (Feature == "+popcnt") { 3340 HasPOPCNT = true; 3341 } else if (Feature == "+rtm") { 3342 HasRTM = true; 3343 } else if (Feature == "+prfchw") { 3344 HasPRFCHW = true; 3345 } else if (Feature == "+rdseed") { 3346 HasRDSEED = true; 3347 } else if (Feature == "+adx") { 3348 HasADX = true; 3349 } else if (Feature == "+tbm") { 3350 HasTBM = true; 3351 } else if (Feature == "+fma") { 3352 HasFMA = true; 3353 } else if (Feature == "+f16c") { 3354 HasF16C = true; 3355 } else if (Feature == "+avx512cd") { 3356 HasAVX512CD = true; 3357 } else if (Feature == "+avx512er") { 3358 HasAVX512ER = true; 3359 } else if (Feature == "+avx512pf") { 3360 HasAVX512PF = true; 3361 } else if (Feature == "+avx512dq") { 3362 HasAVX512DQ = true; 3363 } else if (Feature == "+avx512bw") { 3364 HasAVX512BW = true; 3365 } else if (Feature == "+avx512vl") { 3366 HasAVX512VL = true; 3367 } else if (Feature == "+avx512vbmi") { 3368 HasAVX512VBMI = true; 3369 } else if (Feature == "+avx512ifma") { 3370 HasAVX512IFMA = true; 3371 } else if (Feature == "+sha") { 3372 HasSHA = true; 3373 } else if (Feature == "+mpx") { 3374 HasMPX = true; 3375 } else if (Feature == "+movbe") { 3376 HasMOVBE = true; 3377 } else if (Feature == "+sgx") { 3378 HasSGX = true; 3379 } else if (Feature == "+cx16") { 3380 HasCX16 = true; 3381 } else if (Feature == "+fxsr") { 3382 HasFXSR = true; 3383 } else if (Feature == "+xsave") { 3384 HasXSAVE = true; 3385 } else if (Feature == "+xsaveopt") { 3386 HasXSAVEOPT = true; 3387 } else if (Feature == "+xsavec") { 3388 HasXSAVEC = true; 3389 } else if (Feature == "+xsaves") { 3390 HasXSAVES = true; 3391 } else if (Feature == "+mwaitx") { 3392 HasMWAITX = true; 3393 } else if (Feature == "+pku") { 3394 HasPKU = true; 3395 } else if (Feature == "+clflushopt") { 3396 HasCLFLUSHOPT = true; 3397 } else if (Feature == "+pcommit") { 3398 HasPCOMMIT = true; 3399 } else if (Feature == "+clwb") { 3400 HasCLWB = true; 3401 } else if (Feature == "+umip") { 3402 HasUMIP = true; 3403 } else if (Feature == "+prefetchwt1") { 3404 HasPREFETCHWT1 = true; 3405 } 3406 3407 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3408 .Case("+avx512f", AVX512F) 3409 .Case("+avx2", AVX2) 3410 .Case("+avx", AVX) 3411 .Case("+sse4.2", SSE42) 3412 .Case("+sse4.1", SSE41) 3413 .Case("+ssse3", SSSE3) 3414 .Case("+sse3", SSE3) 3415 .Case("+sse2", SSE2) 3416 .Case("+sse", SSE1) 3417 .Default(NoSSE); 3418 SSELevel = std::max(SSELevel, Level); 3419 3420 MMX3DNowEnum ThreeDNowLevel = 3421 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3422 .Case("+3dnowa", AMD3DNowAthlon) 3423 .Case("+3dnow", AMD3DNow) 3424 .Case("+mmx", MMX) 3425 .Default(NoMMX3DNow); 3426 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3427 3428 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3429 .Case("+xop", XOP) 3430 .Case("+fma4", FMA4) 3431 .Case("+sse4a", SSE4A) 3432 .Default(NoXOP); 3433 XOPLevel = std::max(XOPLevel, XLevel); 3434 } 3435 3436 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3437 // matches the selected sse level. 3438 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3439 (FPMath == FP_387 && SSELevel >= SSE1)) { 3440 Diags.Report(diag::err_target_unsupported_fpmath) << 3441 (FPMath == FP_SSE ? "sse" : "387"); 3442 return false; 3443 } 3444 3445 SimdDefaultAlign = 3446 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3447 return true; 3448 } 3449 3450 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3451 /// definitions for this particular subtarget. 3452 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3453 MacroBuilder &Builder) const { 3454 // Target identification. 3455 if (getTriple().getArch() == llvm::Triple::x86_64) { 3456 Builder.defineMacro("__amd64__"); 3457 Builder.defineMacro("__amd64"); 3458 Builder.defineMacro("__x86_64"); 3459 Builder.defineMacro("__x86_64__"); 3460 if (getTriple().getArchName() == "x86_64h") { 3461 Builder.defineMacro("__x86_64h"); 3462 Builder.defineMacro("__x86_64h__"); 3463 } 3464 } else { 3465 DefineStd(Builder, "i386", Opts); 3466 } 3467 3468 // Subtarget options. 3469 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3470 // truly should be based on -mtune options. 3471 switch (CPU) { 3472 case CK_Generic: 3473 break; 3474 case CK_i386: 3475 // The rest are coming from the i386 define above. 3476 Builder.defineMacro("__tune_i386__"); 3477 break; 3478 case CK_i486: 3479 case CK_WinChipC6: 3480 case CK_WinChip2: 3481 case CK_C3: 3482 defineCPUMacros(Builder, "i486"); 3483 break; 3484 case CK_PentiumMMX: 3485 Builder.defineMacro("__pentium_mmx__"); 3486 Builder.defineMacro("__tune_pentium_mmx__"); 3487 // Fallthrough 3488 case CK_i586: 3489 case CK_Pentium: 3490 defineCPUMacros(Builder, "i586"); 3491 defineCPUMacros(Builder, "pentium"); 3492 break; 3493 case CK_Pentium3: 3494 case CK_Pentium3M: 3495 case CK_PentiumM: 3496 Builder.defineMacro("__tune_pentium3__"); 3497 // Fallthrough 3498 case CK_Pentium2: 3499 case CK_C3_2: 3500 Builder.defineMacro("__tune_pentium2__"); 3501 // Fallthrough 3502 case CK_PentiumPro: 3503 Builder.defineMacro("__tune_i686__"); 3504 Builder.defineMacro("__tune_pentiumpro__"); 3505 // Fallthrough 3506 case CK_i686: 3507 Builder.defineMacro("__i686"); 3508 Builder.defineMacro("__i686__"); 3509 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3510 Builder.defineMacro("__pentiumpro"); 3511 Builder.defineMacro("__pentiumpro__"); 3512 break; 3513 case CK_Pentium4: 3514 case CK_Pentium4M: 3515 defineCPUMacros(Builder, "pentium4"); 3516 break; 3517 case CK_Yonah: 3518 case CK_Prescott: 3519 case CK_Nocona: 3520 defineCPUMacros(Builder, "nocona"); 3521 break; 3522 case CK_Core2: 3523 case CK_Penryn: 3524 defineCPUMacros(Builder, "core2"); 3525 break; 3526 case CK_Bonnell: 3527 defineCPUMacros(Builder, "atom"); 3528 break; 3529 case CK_Silvermont: 3530 defineCPUMacros(Builder, "slm"); 3531 break; 3532 case CK_Nehalem: 3533 case CK_Westmere: 3534 case CK_SandyBridge: 3535 case CK_IvyBridge: 3536 case CK_Haswell: 3537 case CK_Broadwell: 3538 case CK_SkylakeClient: 3539 // FIXME: Historically, we defined this legacy name, it would be nice to 3540 // remove it at some point. We've never exposed fine-grained names for 3541 // recent primary x86 CPUs, and we should keep it that way. 3542 defineCPUMacros(Builder, "corei7"); 3543 break; 3544 case CK_SkylakeServer: 3545 defineCPUMacros(Builder, "skx"); 3546 break; 3547 case CK_Cannonlake: 3548 break; 3549 case CK_KNL: 3550 defineCPUMacros(Builder, "knl"); 3551 break; 3552 case CK_Lakemont: 3553 Builder.defineMacro("__tune_lakemont__"); 3554 break; 3555 case CK_K6_2: 3556 Builder.defineMacro("__k6_2__"); 3557 Builder.defineMacro("__tune_k6_2__"); 3558 // Fallthrough 3559 case CK_K6_3: 3560 if (CPU != CK_K6_2) { // In case of fallthrough 3561 // FIXME: GCC may be enabling these in cases where some other k6 3562 // architecture is specified but -m3dnow is explicitly provided. The 3563 // exact semantics need to be determined and emulated here. 3564 Builder.defineMacro("__k6_3__"); 3565 Builder.defineMacro("__tune_k6_3__"); 3566 } 3567 // Fallthrough 3568 case CK_K6: 3569 defineCPUMacros(Builder, "k6"); 3570 break; 3571 case CK_Athlon: 3572 case CK_AthlonThunderbird: 3573 case CK_Athlon4: 3574 case CK_AthlonXP: 3575 case CK_AthlonMP: 3576 defineCPUMacros(Builder, "athlon"); 3577 if (SSELevel != NoSSE) { 3578 Builder.defineMacro("__athlon_sse__"); 3579 Builder.defineMacro("__tune_athlon_sse__"); 3580 } 3581 break; 3582 case CK_K8: 3583 case CK_K8SSE3: 3584 case CK_x86_64: 3585 case CK_Opteron: 3586 case CK_OpteronSSE3: 3587 case CK_Athlon64: 3588 case CK_Athlon64SSE3: 3589 case CK_AthlonFX: 3590 defineCPUMacros(Builder, "k8"); 3591 break; 3592 case CK_AMDFAM10: 3593 defineCPUMacros(Builder, "amdfam10"); 3594 break; 3595 case CK_BTVER1: 3596 defineCPUMacros(Builder, "btver1"); 3597 break; 3598 case CK_BTVER2: 3599 defineCPUMacros(Builder, "btver2"); 3600 break; 3601 case CK_BDVER1: 3602 defineCPUMacros(Builder, "bdver1"); 3603 break; 3604 case CK_BDVER2: 3605 defineCPUMacros(Builder, "bdver2"); 3606 break; 3607 case CK_BDVER3: 3608 defineCPUMacros(Builder, "bdver3"); 3609 break; 3610 case CK_BDVER4: 3611 defineCPUMacros(Builder, "bdver4"); 3612 break; 3613 case CK_Geode: 3614 defineCPUMacros(Builder, "geode"); 3615 break; 3616 } 3617 3618 // Target properties. 3619 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3620 3621 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3622 // functions in glibc header files that use FP Stack inline asm which the 3623 // backend can't deal with (PR879). 3624 Builder.defineMacro("__NO_MATH_INLINES"); 3625 3626 if (HasAES) 3627 Builder.defineMacro("__AES__"); 3628 3629 if (HasPCLMUL) 3630 Builder.defineMacro("__PCLMUL__"); 3631 3632 if (HasLZCNT) 3633 Builder.defineMacro("__LZCNT__"); 3634 3635 if (HasRDRND) 3636 Builder.defineMacro("__RDRND__"); 3637 3638 if (HasFSGSBASE) 3639 Builder.defineMacro("__FSGSBASE__"); 3640 3641 if (HasBMI) 3642 Builder.defineMacro("__BMI__"); 3643 3644 if (HasBMI2) 3645 Builder.defineMacro("__BMI2__"); 3646 3647 if (HasPOPCNT) 3648 Builder.defineMacro("__POPCNT__"); 3649 3650 if (HasRTM) 3651 Builder.defineMacro("__RTM__"); 3652 3653 if (HasPRFCHW) 3654 Builder.defineMacro("__PRFCHW__"); 3655 3656 if (HasRDSEED) 3657 Builder.defineMacro("__RDSEED__"); 3658 3659 if (HasADX) 3660 Builder.defineMacro("__ADX__"); 3661 3662 if (HasTBM) 3663 Builder.defineMacro("__TBM__"); 3664 3665 if (HasMWAITX) 3666 Builder.defineMacro("__MWAITX__"); 3667 3668 switch (XOPLevel) { 3669 case XOP: 3670 Builder.defineMacro("__XOP__"); 3671 case FMA4: 3672 Builder.defineMacro("__FMA4__"); 3673 case SSE4A: 3674 Builder.defineMacro("__SSE4A__"); 3675 case NoXOP: 3676 break; 3677 } 3678 3679 if (HasFMA) 3680 Builder.defineMacro("__FMA__"); 3681 3682 if (HasF16C) 3683 Builder.defineMacro("__F16C__"); 3684 3685 if (HasAVX512CD) 3686 Builder.defineMacro("__AVX512CD__"); 3687 if (HasAVX512ER) 3688 Builder.defineMacro("__AVX512ER__"); 3689 if (HasAVX512PF) 3690 Builder.defineMacro("__AVX512PF__"); 3691 if (HasAVX512DQ) 3692 Builder.defineMacro("__AVX512DQ__"); 3693 if (HasAVX512BW) 3694 Builder.defineMacro("__AVX512BW__"); 3695 if (HasAVX512VL) 3696 Builder.defineMacro("__AVX512VL__"); 3697 if (HasAVX512VBMI) 3698 Builder.defineMacro("__AVX512VBMI__"); 3699 if (HasAVX512IFMA) 3700 Builder.defineMacro("__AVX512IFMA__"); 3701 3702 if (HasSHA) 3703 Builder.defineMacro("__SHA__"); 3704 3705 if (HasFXSR) 3706 Builder.defineMacro("__FXSR__"); 3707 if (HasXSAVE) 3708 Builder.defineMacro("__XSAVE__"); 3709 if (HasXSAVEOPT) 3710 Builder.defineMacro("__XSAVEOPT__"); 3711 if (HasXSAVEC) 3712 Builder.defineMacro("__XSAVEC__"); 3713 if (HasXSAVES) 3714 Builder.defineMacro("__XSAVES__"); 3715 if (HasPKU) 3716 Builder.defineMacro("__PKU__"); 3717 if (HasCX16) 3718 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3719 3720 // Each case falls through to the previous one here. 3721 switch (SSELevel) { 3722 case AVX512F: 3723 Builder.defineMacro("__AVX512F__"); 3724 case AVX2: 3725 Builder.defineMacro("__AVX2__"); 3726 case AVX: 3727 Builder.defineMacro("__AVX__"); 3728 case SSE42: 3729 Builder.defineMacro("__SSE4_2__"); 3730 case SSE41: 3731 Builder.defineMacro("__SSE4_1__"); 3732 case SSSE3: 3733 Builder.defineMacro("__SSSE3__"); 3734 case SSE3: 3735 Builder.defineMacro("__SSE3__"); 3736 case SSE2: 3737 Builder.defineMacro("__SSE2__"); 3738 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3739 case SSE1: 3740 Builder.defineMacro("__SSE__"); 3741 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3742 case NoSSE: 3743 break; 3744 } 3745 3746 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3747 switch (SSELevel) { 3748 case AVX512F: 3749 case AVX2: 3750 case AVX: 3751 case SSE42: 3752 case SSE41: 3753 case SSSE3: 3754 case SSE3: 3755 case SSE2: 3756 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3757 break; 3758 case SSE1: 3759 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3760 break; 3761 default: 3762 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3763 } 3764 } 3765 3766 // Each case falls through to the previous one here. 3767 switch (MMX3DNowLevel) { 3768 case AMD3DNowAthlon: 3769 Builder.defineMacro("__3dNOW_A__"); 3770 case AMD3DNow: 3771 Builder.defineMacro("__3dNOW__"); 3772 case MMX: 3773 Builder.defineMacro("__MMX__"); 3774 case NoMMX3DNow: 3775 break; 3776 } 3777 3778 if (CPU >= CK_i486) { 3779 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3780 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3781 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3782 } 3783 if (CPU >= CK_i586) 3784 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3785 } 3786 3787 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3788 return llvm::StringSwitch<bool>(Feature) 3789 .Case("aes", HasAES) 3790 .Case("avx", SSELevel >= AVX) 3791 .Case("avx2", SSELevel >= AVX2) 3792 .Case("avx512f", SSELevel >= AVX512F) 3793 .Case("avx512cd", HasAVX512CD) 3794 .Case("avx512er", HasAVX512ER) 3795 .Case("avx512pf", HasAVX512PF) 3796 .Case("avx512dq", HasAVX512DQ) 3797 .Case("avx512bw", HasAVX512BW) 3798 .Case("avx512vl", HasAVX512VL) 3799 .Case("avx512vbmi", HasAVX512VBMI) 3800 .Case("avx512ifma", HasAVX512IFMA) 3801 .Case("bmi", HasBMI) 3802 .Case("bmi2", HasBMI2) 3803 .Case("clflushopt", HasCLFLUSHOPT) 3804 .Case("clwb", HasCLWB) 3805 .Case("cx16", HasCX16) 3806 .Case("f16c", HasF16C) 3807 .Case("fma", HasFMA) 3808 .Case("fma4", XOPLevel >= FMA4) 3809 .Case("fsgsbase", HasFSGSBASE) 3810 .Case("fxsr", HasFXSR) 3811 .Case("lzcnt", HasLZCNT) 3812 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3813 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3814 .Case("mmx", MMX3DNowLevel >= MMX) 3815 .Case("movbe", HasMOVBE) 3816 .Case("mpx", HasMPX) 3817 .Case("pclmul", HasPCLMUL) 3818 .Case("pcommit", HasPCOMMIT) 3819 .Case("pku", HasPKU) 3820 .Case("popcnt", HasPOPCNT) 3821 .Case("prefetchwt1", HasPREFETCHWT1) 3822 .Case("prfchw", HasPRFCHW) 3823 .Case("rdrnd", HasRDRND) 3824 .Case("rdseed", HasRDSEED) 3825 .Case("rtm", HasRTM) 3826 .Case("sgx", HasSGX) 3827 .Case("sha", HasSHA) 3828 .Case("sse", SSELevel >= SSE1) 3829 .Case("sse2", SSELevel >= SSE2) 3830 .Case("sse3", SSELevel >= SSE3) 3831 .Case("ssse3", SSELevel >= SSSE3) 3832 .Case("sse4.1", SSELevel >= SSE41) 3833 .Case("sse4.2", SSELevel >= SSE42) 3834 .Case("sse4a", XOPLevel >= SSE4A) 3835 .Case("tbm", HasTBM) 3836 .Case("umip", HasUMIP) 3837 .Case("x86", true) 3838 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3839 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3840 .Case("xop", XOPLevel >= XOP) 3841 .Case("xsave", HasXSAVE) 3842 .Case("xsavec", HasXSAVEC) 3843 .Case("xsaves", HasXSAVES) 3844 .Case("xsaveopt", HasXSAVEOPT) 3845 .Default(false); 3846 } 3847 3848 // We can't use a generic validation scheme for the features accepted here 3849 // versus subtarget features accepted in the target attribute because the 3850 // bitfield structure that's initialized in the runtime only supports the 3851 // below currently rather than the full range of subtarget features. (See 3852 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3853 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3854 return llvm::StringSwitch<bool>(FeatureStr) 3855 .Case("cmov", true) 3856 .Case("mmx", true) 3857 .Case("popcnt", true) 3858 .Case("sse", true) 3859 .Case("sse2", true) 3860 .Case("sse3", true) 3861 .Case("ssse3", true) 3862 .Case("sse4.1", true) 3863 .Case("sse4.2", true) 3864 .Case("avx", true) 3865 .Case("avx2", true) 3866 .Case("sse4a", true) 3867 .Case("fma4", true) 3868 .Case("xop", true) 3869 .Case("fma", true) 3870 .Case("avx512f", true) 3871 .Case("bmi", true) 3872 .Case("bmi2", true) 3873 .Case("aes", true) 3874 .Case("pclmul", true) 3875 .Case("avx512vl", true) 3876 .Case("avx512bw", true) 3877 .Case("avx512dq", true) 3878 .Case("avx512cd", true) 3879 .Case("avx512er", true) 3880 .Case("avx512pf", true) 3881 .Case("avx512vbmi", true) 3882 .Case("avx512ifma", true) 3883 .Default(false); 3884 } 3885 3886 bool 3887 X86TargetInfo::validateAsmConstraint(const char *&Name, 3888 TargetInfo::ConstraintInfo &Info) const { 3889 switch (*Name) { 3890 default: return false; 3891 // Constant constraints. 3892 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3893 // instructions. 3894 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3895 // x86_64 instructions. 3896 case 's': 3897 Info.setRequiresImmediate(); 3898 return true; 3899 case 'I': 3900 Info.setRequiresImmediate(0, 31); 3901 return true; 3902 case 'J': 3903 Info.setRequiresImmediate(0, 63); 3904 return true; 3905 case 'K': 3906 Info.setRequiresImmediate(-128, 127); 3907 return true; 3908 case 'L': 3909 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3910 return true; 3911 case 'M': 3912 Info.setRequiresImmediate(0, 3); 3913 return true; 3914 case 'N': 3915 Info.setRequiresImmediate(0, 255); 3916 return true; 3917 case 'O': 3918 Info.setRequiresImmediate(0, 127); 3919 return true; 3920 // Register constraints. 3921 case 'Y': // 'Y' is the first character for several 2-character constraints. 3922 // Shift the pointer to the second character of the constraint. 3923 Name++; 3924 switch (*Name) { 3925 default: 3926 return false; 3927 case '0': // First SSE register. 3928 case 't': // Any SSE register, when SSE2 is enabled. 3929 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3930 case 'm': // Any MMX register, when inter-unit moves enabled. 3931 Info.setAllowsRegister(); 3932 return true; 3933 } 3934 case 'f': // Any x87 floating point stack register. 3935 // Constraint 'f' cannot be used for output operands. 3936 if (Info.ConstraintStr[0] == '=') 3937 return false; 3938 Info.setAllowsRegister(); 3939 return true; 3940 case 'a': // eax. 3941 case 'b': // ebx. 3942 case 'c': // ecx. 3943 case 'd': // edx. 3944 case 'S': // esi. 3945 case 'D': // edi. 3946 case 'A': // edx:eax. 3947 case 't': // Top of floating point stack. 3948 case 'u': // Second from top of floating point stack. 3949 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3950 case 'y': // Any MMX register. 3951 case 'x': // Any SSE register. 3952 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3953 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3954 case 'l': // "Index" registers: any general register that can be used as an 3955 // index in a base+index memory access. 3956 Info.setAllowsRegister(); 3957 return true; 3958 // Floating point constant constraints. 3959 case 'C': // SSE floating point constant. 3960 case 'G': // x87 floating point constant. 3961 return true; 3962 } 3963 } 3964 3965 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3966 unsigned Size) const { 3967 // Strip off constraint modifiers. 3968 while (Constraint[0] == '=' || 3969 Constraint[0] == '+' || 3970 Constraint[0] == '&') 3971 Constraint = Constraint.substr(1); 3972 3973 return validateOperandSize(Constraint, Size); 3974 } 3975 3976 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3977 unsigned Size) const { 3978 return validateOperandSize(Constraint, Size); 3979 } 3980 3981 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3982 unsigned Size) const { 3983 switch (Constraint[0]) { 3984 default: break; 3985 case 'y': 3986 return Size <= 64; 3987 case 'f': 3988 case 't': 3989 case 'u': 3990 return Size <= 128; 3991 case 'x': 3992 if (SSELevel >= AVX512F) 3993 // 512-bit zmm registers can be used if target supports AVX512F. 3994 return Size <= 512U; 3995 else if (SSELevel >= AVX) 3996 // 256-bit ymm registers can be used if target supports AVX. 3997 return Size <= 256U; 3998 return Size <= 128U; 3999 case 'Y': 4000 // 'Y' is the first character for several 2-character constraints. 4001 switch (Constraint[1]) { 4002 default: break; 4003 case 'm': 4004 // 'Ym' is synonymous with 'y'. 4005 return Size <= 64; 4006 case 'i': 4007 case 't': 4008 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4009 if (SSELevel >= AVX512F) 4010 return Size <= 512U; 4011 else if (SSELevel >= AVX) 4012 return Size <= 256U; 4013 return SSELevel >= SSE2 && Size <= 128U; 4014 } 4015 4016 } 4017 4018 return true; 4019 } 4020 4021 std::string 4022 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4023 switch (*Constraint) { 4024 case 'a': return std::string("{ax}"); 4025 case 'b': return std::string("{bx}"); 4026 case 'c': return std::string("{cx}"); 4027 case 'd': return std::string("{dx}"); 4028 case 'S': return std::string("{si}"); 4029 case 'D': return std::string("{di}"); 4030 case 'p': // address 4031 return std::string("im"); 4032 case 't': // top of floating point stack. 4033 return std::string("{st}"); 4034 case 'u': // second from top of floating point stack. 4035 return std::string("{st(1)}"); // second from top of floating point stack. 4036 default: 4037 return std::string(1, *Constraint); 4038 } 4039 } 4040 4041 // X86-32 generic target 4042 class X86_32TargetInfo : public X86TargetInfo { 4043 public: 4044 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4045 : X86TargetInfo(Triple, Opts) { 4046 DoubleAlign = LongLongAlign = 32; 4047 LongDoubleWidth = 96; 4048 LongDoubleAlign = 32; 4049 SuitableAlign = 128; 4050 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4051 SizeType = UnsignedInt; 4052 PtrDiffType = SignedInt; 4053 IntPtrType = SignedInt; 4054 RegParmMax = 3; 4055 4056 // Use fpret for all types. 4057 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4058 (1 << TargetInfo::Double) | 4059 (1 << TargetInfo::LongDouble)); 4060 4061 // x86-32 has atomics up to 8 bytes 4062 // FIXME: Check that we actually have cmpxchg8b before setting 4063 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4064 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4065 } 4066 BuiltinVaListKind getBuiltinVaListKind() const override { 4067 return TargetInfo::CharPtrBuiltinVaList; 4068 } 4069 4070 int getEHDataRegisterNumber(unsigned RegNo) const override { 4071 if (RegNo == 0) return 0; 4072 if (RegNo == 1) return 2; 4073 return -1; 4074 } 4075 bool validateOperandSize(StringRef Constraint, 4076 unsigned Size) const override { 4077 switch (Constraint[0]) { 4078 default: break; 4079 case 'R': 4080 case 'q': 4081 case 'Q': 4082 case 'a': 4083 case 'b': 4084 case 'c': 4085 case 'd': 4086 case 'S': 4087 case 'D': 4088 return Size <= 32; 4089 case 'A': 4090 return Size <= 64; 4091 } 4092 4093 return X86TargetInfo::validateOperandSize(Constraint, Size); 4094 } 4095 }; 4096 4097 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4098 public: 4099 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4100 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4101 4102 unsigned getFloatEvalMethod() const override { 4103 unsigned Major, Minor, Micro; 4104 getTriple().getOSVersion(Major, Minor, Micro); 4105 // New NetBSD uses the default rounding mode. 4106 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4107 return X86_32TargetInfo::getFloatEvalMethod(); 4108 // NetBSD before 6.99.26 defaults to "double" rounding. 4109 return 1; 4110 } 4111 }; 4112 4113 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4114 public: 4115 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4116 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4117 SizeType = UnsignedLong; 4118 IntPtrType = SignedLong; 4119 PtrDiffType = SignedLong; 4120 } 4121 }; 4122 4123 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4124 public: 4125 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4126 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4127 SizeType = UnsignedLong; 4128 IntPtrType = SignedLong; 4129 PtrDiffType = SignedLong; 4130 } 4131 }; 4132 4133 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4134 public: 4135 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4136 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4137 LongDoubleWidth = 128; 4138 LongDoubleAlign = 128; 4139 SuitableAlign = 128; 4140 MaxVectorAlign = 256; 4141 // The watchOS simulator uses the builtin bool type for Objective-C. 4142 llvm::Triple T = llvm::Triple(Triple); 4143 if (T.isWatchOS()) 4144 UseSignedCharForObjCBool = false; 4145 SizeType = UnsignedLong; 4146 IntPtrType = SignedLong; 4147 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4148 HasAlignMac68kSupport = true; 4149 } 4150 4151 bool handleTargetFeatures(std::vector<std::string> &Features, 4152 DiagnosticsEngine &Diags) override { 4153 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4154 Diags)) 4155 return false; 4156 // We now know the features we have: we can decide how to align vectors. 4157 MaxVectorAlign = 4158 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4159 return true; 4160 } 4161 }; 4162 4163 // x86-32 Windows target 4164 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4165 public: 4166 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4167 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4168 WCharType = UnsignedShort; 4169 DoubleAlign = LongLongAlign = 64; 4170 bool IsWinCOFF = 4171 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4172 resetDataLayout(IsWinCOFF 4173 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4174 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4175 } 4176 void getTargetDefines(const LangOptions &Opts, 4177 MacroBuilder &Builder) const override { 4178 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4179 } 4180 }; 4181 4182 // x86-32 Windows Visual Studio target 4183 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4184 public: 4185 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4186 const TargetOptions &Opts) 4187 : WindowsX86_32TargetInfo(Triple, Opts) { 4188 LongDoubleWidth = LongDoubleAlign = 64; 4189 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4190 } 4191 void getTargetDefines(const LangOptions &Opts, 4192 MacroBuilder &Builder) const override { 4193 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4194 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4195 // The value of the following reflects processor type. 4196 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4197 // We lost the original triple, so we use the default. 4198 Builder.defineMacro("_M_IX86", "600"); 4199 } 4200 }; 4201 4202 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4203 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4204 // supports __declspec natively under -fms-extensions, but we define a no-op 4205 // __declspec macro anyway for pre-processor compatibility. 4206 if (Opts.MicrosoftExt) 4207 Builder.defineMacro("__declspec", "__declspec"); 4208 else 4209 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4210 4211 if (!Opts.MicrosoftExt) { 4212 // Provide macros for all the calling convention keywords. Provide both 4213 // single and double underscore prefixed variants. These are available on 4214 // x64 as well as x86, even though they have no effect. 4215 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4216 for (const char *CC : CCs) { 4217 std::string GCCSpelling = "__attribute__((__"; 4218 GCCSpelling += CC; 4219 GCCSpelling += "__))"; 4220 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4221 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4222 } 4223 } 4224 } 4225 4226 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4227 Builder.defineMacro("__MSVCRT__"); 4228 Builder.defineMacro("__MINGW32__"); 4229 addCygMingDefines(Opts, Builder); 4230 } 4231 4232 // x86-32 MinGW target 4233 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4234 public: 4235 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4236 : WindowsX86_32TargetInfo(Triple, Opts) {} 4237 void getTargetDefines(const LangOptions &Opts, 4238 MacroBuilder &Builder) const override { 4239 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4240 DefineStd(Builder, "WIN32", Opts); 4241 DefineStd(Builder, "WINNT", Opts); 4242 Builder.defineMacro("_X86_"); 4243 addMinGWDefines(Opts, Builder); 4244 } 4245 }; 4246 4247 // x86-32 Cygwin target 4248 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4249 public: 4250 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4251 : X86_32TargetInfo(Triple, Opts) { 4252 WCharType = UnsignedShort; 4253 DoubleAlign = LongLongAlign = 64; 4254 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4255 } 4256 void getTargetDefines(const LangOptions &Opts, 4257 MacroBuilder &Builder) const override { 4258 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4259 Builder.defineMacro("_X86_"); 4260 Builder.defineMacro("__CYGWIN__"); 4261 Builder.defineMacro("__CYGWIN32__"); 4262 addCygMingDefines(Opts, Builder); 4263 DefineStd(Builder, "unix", Opts); 4264 if (Opts.CPlusPlus) 4265 Builder.defineMacro("_GNU_SOURCE"); 4266 } 4267 }; 4268 4269 // x86-32 Haiku target 4270 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4271 public: 4272 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4273 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4274 } 4275 void getTargetDefines(const LangOptions &Opts, 4276 MacroBuilder &Builder) const override { 4277 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4278 Builder.defineMacro("__INTEL__"); 4279 } 4280 }; 4281 4282 // X86-32 MCU target 4283 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4284 public: 4285 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4286 : X86_32TargetInfo(Triple, Opts) { 4287 LongDoubleWidth = 64; 4288 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4289 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4290 WIntType = UnsignedInt; 4291 } 4292 4293 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4294 // On MCU we support only C calling convention. 4295 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4296 } 4297 4298 void getTargetDefines(const LangOptions &Opts, 4299 MacroBuilder &Builder) const override { 4300 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4301 Builder.defineMacro("__iamcu"); 4302 Builder.defineMacro("__iamcu__"); 4303 } 4304 4305 bool allowsLargerPreferedTypeAlignment() const override { 4306 return false; 4307 } 4308 }; 4309 4310 // RTEMS Target 4311 template<typename Target> 4312 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4313 protected: 4314 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4315 MacroBuilder &Builder) const override { 4316 // RTEMS defines; list based off of gcc output 4317 4318 Builder.defineMacro("__rtems__"); 4319 Builder.defineMacro("__ELF__"); 4320 } 4321 4322 public: 4323 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4324 : OSTargetInfo<Target>(Triple, Opts) { 4325 switch (Triple.getArch()) { 4326 default: 4327 case llvm::Triple::x86: 4328 // this->MCountName = ".mcount"; 4329 break; 4330 case llvm::Triple::mips: 4331 case llvm::Triple::mipsel: 4332 case llvm::Triple::ppc: 4333 case llvm::Triple::ppc64: 4334 case llvm::Triple::ppc64le: 4335 // this->MCountName = "_mcount"; 4336 break; 4337 case llvm::Triple::arm: 4338 // this->MCountName = "__mcount"; 4339 break; 4340 } 4341 } 4342 }; 4343 4344 // x86-32 RTEMS target 4345 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4346 public: 4347 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4348 : X86_32TargetInfo(Triple, Opts) { 4349 SizeType = UnsignedLong; 4350 IntPtrType = SignedLong; 4351 PtrDiffType = SignedLong; 4352 } 4353 void getTargetDefines(const LangOptions &Opts, 4354 MacroBuilder &Builder) const override { 4355 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4356 Builder.defineMacro("__INTEL__"); 4357 Builder.defineMacro("__rtems__"); 4358 } 4359 }; 4360 4361 // x86-64 generic target 4362 class X86_64TargetInfo : public X86TargetInfo { 4363 public: 4364 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4365 : X86TargetInfo(Triple, Opts) { 4366 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4367 bool IsWinCOFF = 4368 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4369 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4370 LongDoubleWidth = 128; 4371 LongDoubleAlign = 128; 4372 LargeArrayMinWidth = 128; 4373 LargeArrayAlign = 128; 4374 SuitableAlign = 128; 4375 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4376 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4377 IntPtrType = IsX32 ? SignedInt : SignedLong; 4378 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4379 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4380 RegParmMax = 6; 4381 4382 // Pointers are 32-bit in x32. 4383 resetDataLayout(IsX32 4384 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4385 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4386 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4387 4388 // Use fpret only for long double. 4389 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4390 4391 // Use fp2ret for _Complex long double. 4392 ComplexLongDoubleUsesFP2Ret = true; 4393 4394 // Make __builtin_ms_va_list available. 4395 HasBuiltinMSVaList = true; 4396 4397 // x86-64 has atomics up to 16 bytes. 4398 MaxAtomicPromoteWidth = 128; 4399 MaxAtomicInlineWidth = 128; 4400 } 4401 BuiltinVaListKind getBuiltinVaListKind() const override { 4402 return TargetInfo::X86_64ABIBuiltinVaList; 4403 } 4404 4405 int getEHDataRegisterNumber(unsigned RegNo) const override { 4406 if (RegNo == 0) return 0; 4407 if (RegNo == 1) return 1; 4408 return -1; 4409 } 4410 4411 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4412 switch (CC) { 4413 case CC_C: 4414 case CC_Swift: 4415 case CC_X86VectorCall: 4416 case CC_IntelOclBicc: 4417 case CC_X86_64Win64: 4418 case CC_PreserveMost: 4419 case CC_PreserveAll: 4420 return CCCR_OK; 4421 default: 4422 return CCCR_Warning; 4423 } 4424 } 4425 4426 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4427 return CC_C; 4428 } 4429 4430 // for x32 we need it here explicitly 4431 bool hasInt128Type() const override { return true; } 4432 unsigned getUnwindWordWidth() const override { return 64; } 4433 unsigned getRegisterWidth() const override { return 64; } 4434 4435 bool validateGlobalRegisterVariable(StringRef RegName, 4436 unsigned RegSize, 4437 bool &HasSizeMismatch) const override { 4438 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4439 // handle. 4440 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4441 // Check that the register size is 64-bit. 4442 HasSizeMismatch = RegSize != 64; 4443 return true; 4444 } 4445 4446 // Check if the register is a 32-bit register the backend can handle. 4447 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4448 HasSizeMismatch); 4449 } 4450 }; 4451 4452 // x86-64 Windows target 4453 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4454 public: 4455 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4456 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4457 WCharType = UnsignedShort; 4458 LongWidth = LongAlign = 32; 4459 DoubleAlign = LongLongAlign = 64; 4460 IntMaxType = SignedLongLong; 4461 Int64Type = SignedLongLong; 4462 SizeType = UnsignedLongLong; 4463 PtrDiffType = SignedLongLong; 4464 IntPtrType = SignedLongLong; 4465 } 4466 4467 void getTargetDefines(const LangOptions &Opts, 4468 MacroBuilder &Builder) const override { 4469 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4470 Builder.defineMacro("_WIN64"); 4471 } 4472 4473 BuiltinVaListKind getBuiltinVaListKind() const override { 4474 return TargetInfo::CharPtrBuiltinVaList; 4475 } 4476 4477 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4478 switch (CC) { 4479 case CC_X86StdCall: 4480 case CC_X86ThisCall: 4481 case CC_X86FastCall: 4482 return CCCR_Ignore; 4483 case CC_C: 4484 case CC_X86VectorCall: 4485 case CC_IntelOclBicc: 4486 case CC_X86_64SysV: 4487 return CCCR_OK; 4488 default: 4489 return CCCR_Warning; 4490 } 4491 } 4492 }; 4493 4494 // x86-64 Windows Visual Studio target 4495 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4496 public: 4497 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4498 const TargetOptions &Opts) 4499 : WindowsX86_64TargetInfo(Triple, Opts) { 4500 LongDoubleWidth = LongDoubleAlign = 64; 4501 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4502 } 4503 void getTargetDefines(const LangOptions &Opts, 4504 MacroBuilder &Builder) const override { 4505 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4506 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4507 Builder.defineMacro("_M_X64", "100"); 4508 Builder.defineMacro("_M_AMD64", "100"); 4509 } 4510 }; 4511 4512 // x86-64 MinGW target 4513 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4514 public: 4515 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4516 : WindowsX86_64TargetInfo(Triple, Opts) { 4517 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4518 // with x86 FP ops. Weird. 4519 LongDoubleWidth = LongDoubleAlign = 128; 4520 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4521 } 4522 4523 void getTargetDefines(const LangOptions &Opts, 4524 MacroBuilder &Builder) const override { 4525 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4526 DefineStd(Builder, "WIN64", Opts); 4527 Builder.defineMacro("__MINGW64__"); 4528 addMinGWDefines(Opts, Builder); 4529 4530 // GCC defines this macro when it is using __gxx_personality_seh0. 4531 if (!Opts.SjLjExceptions) 4532 Builder.defineMacro("__SEH__"); 4533 } 4534 }; 4535 4536 // x86-64 Cygwin target 4537 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4538 public: 4539 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4540 : X86_64TargetInfo(Triple, Opts) { 4541 TLSSupported = false; 4542 WCharType = UnsignedShort; 4543 } 4544 void getTargetDefines(const LangOptions &Opts, 4545 MacroBuilder &Builder) const override { 4546 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4547 Builder.defineMacro("__x86_64__"); 4548 Builder.defineMacro("__CYGWIN__"); 4549 Builder.defineMacro("__CYGWIN64__"); 4550 addCygMingDefines(Opts, Builder); 4551 DefineStd(Builder, "unix", Opts); 4552 if (Opts.CPlusPlus) 4553 Builder.defineMacro("_GNU_SOURCE"); 4554 4555 // GCC defines this macro when it is using __gxx_personality_seh0. 4556 if (!Opts.SjLjExceptions) 4557 Builder.defineMacro("__SEH__"); 4558 } 4559 }; 4560 4561 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4562 public: 4563 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4564 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4565 Int64Type = SignedLongLong; 4566 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4567 llvm::Triple T = llvm::Triple(Triple); 4568 if (T.isiOS()) 4569 UseSignedCharForObjCBool = false; 4570 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4571 } 4572 4573 bool handleTargetFeatures(std::vector<std::string> &Features, 4574 DiagnosticsEngine &Diags) override { 4575 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4576 Diags)) 4577 return false; 4578 // We now know the features we have: we can decide how to align vectors. 4579 MaxVectorAlign = 4580 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4581 return true; 4582 } 4583 }; 4584 4585 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4586 public: 4587 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4588 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4589 IntMaxType = SignedLongLong; 4590 Int64Type = SignedLongLong; 4591 } 4592 }; 4593 4594 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4595 public: 4596 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4597 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4598 IntMaxType = SignedLongLong; 4599 Int64Type = SignedLongLong; 4600 } 4601 }; 4602 4603 class ARMTargetInfo : public TargetInfo { 4604 // Possible FPU choices. 4605 enum FPUMode { 4606 VFP2FPU = (1 << 0), 4607 VFP3FPU = (1 << 1), 4608 VFP4FPU = (1 << 2), 4609 NeonFPU = (1 << 3), 4610 FPARMV8 = (1 << 4) 4611 }; 4612 4613 // Possible HWDiv features. 4614 enum HWDivMode { 4615 HWDivThumb = (1 << 0), 4616 HWDivARM = (1 << 1) 4617 }; 4618 4619 static bool FPUModeIsVFP(FPUMode Mode) { 4620 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4621 } 4622 4623 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4624 static const char * const GCCRegNames[]; 4625 4626 std::string ABI, CPU; 4627 4628 StringRef CPUProfile; 4629 StringRef CPUAttr; 4630 4631 enum { 4632 FP_Default, 4633 FP_VFP, 4634 FP_Neon 4635 } FPMath; 4636 4637 unsigned ArchISA; 4638 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4639 unsigned ArchProfile; 4640 unsigned ArchVersion; 4641 4642 unsigned FPU : 5; 4643 4644 unsigned IsAAPCS : 1; 4645 unsigned HWDiv : 2; 4646 4647 // Initialized via features. 4648 unsigned SoftFloat : 1; 4649 unsigned SoftFloatABI : 1; 4650 4651 unsigned CRC : 1; 4652 unsigned Crypto : 1; 4653 unsigned DSP : 1; 4654 unsigned Unaligned : 1; 4655 4656 enum { 4657 LDREX_B = (1 << 0), /// byte (8-bit) 4658 LDREX_H = (1 << 1), /// half (16-bit) 4659 LDREX_W = (1 << 2), /// word (32-bit) 4660 LDREX_D = (1 << 3), /// double (64-bit) 4661 }; 4662 4663 uint32_t LDREX; 4664 4665 // ACLE 6.5.1 Hardware floating point 4666 enum { 4667 HW_FP_HP = (1 << 1), /// half (16-bit) 4668 HW_FP_SP = (1 << 2), /// single (32-bit) 4669 HW_FP_DP = (1 << 3), /// double (64-bit) 4670 }; 4671 uint32_t HW_FP; 4672 4673 static const Builtin::Info BuiltinInfo[]; 4674 4675 void setABIAAPCS() { 4676 IsAAPCS = true; 4677 4678 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4679 const llvm::Triple &T = getTriple(); 4680 4681 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4682 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4683 T.getOS() == llvm::Triple::Bitrig) 4684 SizeType = UnsignedLong; 4685 else 4686 SizeType = UnsignedInt; 4687 4688 switch (T.getOS()) { 4689 case llvm::Triple::NetBSD: 4690 WCharType = SignedInt; 4691 break; 4692 case llvm::Triple::Win32: 4693 WCharType = UnsignedShort; 4694 break; 4695 case llvm::Triple::Linux: 4696 default: 4697 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4698 WCharType = UnsignedInt; 4699 break; 4700 } 4701 4702 UseBitFieldTypeAlignment = true; 4703 4704 ZeroLengthBitfieldBoundary = 0; 4705 4706 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4707 // so set preferred for small types to 32. 4708 if (T.isOSBinFormatMachO()) { 4709 resetDataLayout(BigEndian 4710 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4711 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4712 } else if (T.isOSWindows()) { 4713 assert(!BigEndian && "Windows on ARM does not support big endian"); 4714 resetDataLayout("e" 4715 "-m:w" 4716 "-p:32:32" 4717 "-i64:64" 4718 "-v128:64:128" 4719 "-a:0:32" 4720 "-n32" 4721 "-S64"); 4722 } else if (T.isOSNaCl()) { 4723 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4724 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4725 } else { 4726 resetDataLayout(BigEndian 4727 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4728 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4729 } 4730 4731 // FIXME: Enumerated types are variable width in straight AAPCS. 4732 } 4733 4734 void setABIAPCS(bool IsAAPCS16) { 4735 const llvm::Triple &T = getTriple(); 4736 4737 IsAAPCS = false; 4738 4739 if (IsAAPCS16) 4740 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4741 else 4742 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4743 4744 // size_t is unsigned int on FreeBSD. 4745 if (T.getOS() == llvm::Triple::FreeBSD) 4746 SizeType = UnsignedInt; 4747 else 4748 SizeType = UnsignedLong; 4749 4750 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4751 WCharType = SignedInt; 4752 4753 // Do not respect the alignment of bit-field types when laying out 4754 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4755 UseBitFieldTypeAlignment = false; 4756 4757 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4758 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4759 /// gcc. 4760 ZeroLengthBitfieldBoundary = 32; 4761 4762 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4763 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4764 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4765 } else if (T.isOSBinFormatMachO()) 4766 resetDataLayout( 4767 BigEndian 4768 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4769 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4770 else 4771 resetDataLayout( 4772 BigEndian 4773 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4774 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4775 4776 // FIXME: Override "preferred align" for double and long long. 4777 } 4778 4779 void setArchInfo() { 4780 StringRef ArchName = getTriple().getArchName(); 4781 4782 ArchISA = llvm::ARM::parseArchISA(ArchName); 4783 CPU = llvm::ARM::getDefaultCPU(ArchName); 4784 unsigned AK = llvm::ARM::parseArch(ArchName); 4785 if (AK != llvm::ARM::AK_INVALID) 4786 ArchKind = AK; 4787 setArchInfo(ArchKind); 4788 } 4789 4790 void setArchInfo(unsigned Kind) { 4791 StringRef SubArch; 4792 4793 // cache TargetParser info 4794 ArchKind = Kind; 4795 SubArch = llvm::ARM::getSubArch(ArchKind); 4796 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4797 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4798 4799 // cache CPU related strings 4800 CPUAttr = getCPUAttr(); 4801 CPUProfile = getCPUProfile(); 4802 } 4803 4804 void setAtomic() { 4805 // when triple does not specify a sub arch, 4806 // then we are not using inline atomics 4807 bool ShouldUseInlineAtomic = 4808 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4809 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4810 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4811 if (ArchProfile == llvm::ARM::PK_M) { 4812 MaxAtomicPromoteWidth = 32; 4813 if (ShouldUseInlineAtomic) 4814 MaxAtomicInlineWidth = 32; 4815 } 4816 else { 4817 MaxAtomicPromoteWidth = 64; 4818 if (ShouldUseInlineAtomic) 4819 MaxAtomicInlineWidth = 64; 4820 } 4821 } 4822 4823 bool isThumb() const { 4824 return (ArchISA == llvm::ARM::IK_THUMB); 4825 } 4826 4827 bool supportsThumb() const { 4828 return CPUAttr.count('T') || ArchVersion >= 6; 4829 } 4830 4831 bool supportsThumb2() const { 4832 return CPUAttr.equals("6T2") || 4833 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 4834 } 4835 4836 StringRef getCPUAttr() const { 4837 // For most sub-arches, the build attribute CPU name is enough. 4838 // For Cortex variants, it's slightly different. 4839 switch(ArchKind) { 4840 default: 4841 return llvm::ARM::getCPUAttr(ArchKind); 4842 case llvm::ARM::AK_ARMV6M: 4843 return "6M"; 4844 case llvm::ARM::AK_ARMV7S: 4845 return "7S"; 4846 case llvm::ARM::AK_ARMV7A: 4847 return "7A"; 4848 case llvm::ARM::AK_ARMV7R: 4849 return "7R"; 4850 case llvm::ARM::AK_ARMV7M: 4851 return "7M"; 4852 case llvm::ARM::AK_ARMV7EM: 4853 return "7EM"; 4854 case llvm::ARM::AK_ARMV8A: 4855 return "8A"; 4856 case llvm::ARM::AK_ARMV8_1A: 4857 return "8_1A"; 4858 case llvm::ARM::AK_ARMV8_2A: 4859 return "8_2A"; 4860 case llvm::ARM::AK_ARMV8MBaseline: 4861 return "8M_BASE"; 4862 case llvm::ARM::AK_ARMV8MMainline: 4863 return "8M_MAIN"; 4864 } 4865 } 4866 4867 StringRef getCPUProfile() const { 4868 switch(ArchProfile) { 4869 case llvm::ARM::PK_A: 4870 return "A"; 4871 case llvm::ARM::PK_R: 4872 return "R"; 4873 case llvm::ARM::PK_M: 4874 return "M"; 4875 default: 4876 return ""; 4877 } 4878 } 4879 4880 public: 4881 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 4882 bool IsBigEndian) 4883 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 4884 HW_FP(0) { 4885 BigEndian = IsBigEndian; 4886 4887 switch (getTriple().getOS()) { 4888 case llvm::Triple::NetBSD: 4889 PtrDiffType = SignedLong; 4890 break; 4891 default: 4892 PtrDiffType = SignedInt; 4893 break; 4894 } 4895 4896 // Cache arch related info. 4897 setArchInfo(); 4898 4899 // {} in inline assembly are neon specifiers, not assembly variant 4900 // specifiers. 4901 NoAsmVariants = true; 4902 4903 // FIXME: This duplicates code from the driver that sets the -target-abi 4904 // option - this code is used if -target-abi isn't passed and should 4905 // be unified in some way. 4906 if (Triple.isOSBinFormatMachO()) { 4907 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4908 // the frontend matches that. 4909 if (Triple.getEnvironment() == llvm::Triple::EABI || 4910 Triple.getOS() == llvm::Triple::UnknownOS || 4911 ArchProfile == llvm::ARM::PK_M) { 4912 setABI("aapcs"); 4913 } else if (Triple.isWatchABI()) { 4914 setABI("aapcs16"); 4915 } else { 4916 setABI("apcs-gnu"); 4917 } 4918 } else if (Triple.isOSWindows()) { 4919 // FIXME: this is invalid for WindowsCE 4920 setABI("aapcs"); 4921 } else { 4922 // Select the default based on the platform. 4923 switch (Triple.getEnvironment()) { 4924 case llvm::Triple::Android: 4925 case llvm::Triple::GNUEABI: 4926 case llvm::Triple::GNUEABIHF: 4927 case llvm::Triple::MuslEABI: 4928 case llvm::Triple::MuslEABIHF: 4929 setABI("aapcs-linux"); 4930 break; 4931 case llvm::Triple::EABIHF: 4932 case llvm::Triple::EABI: 4933 setABI("aapcs"); 4934 break; 4935 case llvm::Triple::GNU: 4936 setABI("apcs-gnu"); 4937 break; 4938 default: 4939 if (Triple.getOS() == llvm::Triple::NetBSD) 4940 setABI("apcs-gnu"); 4941 else 4942 setABI("aapcs"); 4943 break; 4944 } 4945 } 4946 4947 // ARM targets default to using the ARM C++ ABI. 4948 TheCXXABI.set(TargetCXXABI::GenericARM); 4949 4950 // ARM has atomics up to 8 bytes 4951 setAtomic(); 4952 4953 // Do force alignment of members that follow zero length bitfields. If 4954 // the alignment of the zero-length bitfield is greater than the member 4955 // that follows it, `bar', `bar' will be aligned as the type of the 4956 // zero length bitfield. 4957 UseZeroLengthBitfieldAlignment = true; 4958 4959 if (Triple.getOS() == llvm::Triple::Linux || 4960 Triple.getOS() == llvm::Triple::UnknownOS) 4961 this->MCountName = 4962 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 4963 } 4964 4965 StringRef getABI() const override { return ABI; } 4966 4967 bool setABI(const std::string &Name) override { 4968 ABI = Name; 4969 4970 // The defaults (above) are for AAPCS, check if we need to change them. 4971 // 4972 // FIXME: We need support for -meabi... we could just mangle it into the 4973 // name. 4974 if (Name == "apcs-gnu" || Name == "aapcs16") { 4975 setABIAPCS(Name == "aapcs16"); 4976 return true; 4977 } 4978 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4979 setABIAAPCS(); 4980 return true; 4981 } 4982 return false; 4983 } 4984 4985 // FIXME: This should be based on Arch attributes, not CPU names. 4986 bool 4987 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4988 StringRef CPU, 4989 const std::vector<std::string> &FeaturesVec) const override { 4990 4991 std::vector<const char*> TargetFeatures; 4992 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4993 4994 // get default FPU features 4995 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4996 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4997 4998 // get default Extension features 4999 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 5000 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 5001 5002 for (const char *Feature : TargetFeatures) 5003 if (Feature[0] == '+') 5004 Features[Feature+1] = true; 5005 5006 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5007 } 5008 5009 bool handleTargetFeatures(std::vector<std::string> &Features, 5010 DiagnosticsEngine &Diags) override { 5011 FPU = 0; 5012 CRC = 0; 5013 Crypto = 0; 5014 DSP = 0; 5015 Unaligned = 1; 5016 SoftFloat = SoftFloatABI = false; 5017 HWDiv = 0; 5018 5019 // This does not diagnose illegal cases like having both 5020 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5021 uint32_t HW_FP_remove = 0; 5022 for (const auto &Feature : Features) { 5023 if (Feature == "+soft-float") { 5024 SoftFloat = true; 5025 } else if (Feature == "+soft-float-abi") { 5026 SoftFloatABI = true; 5027 } else if (Feature == "+vfp2") { 5028 FPU |= VFP2FPU; 5029 HW_FP |= HW_FP_SP | HW_FP_DP; 5030 } else if (Feature == "+vfp3") { 5031 FPU |= VFP3FPU; 5032 HW_FP |= HW_FP_SP | HW_FP_DP; 5033 } else if (Feature == "+vfp4") { 5034 FPU |= VFP4FPU; 5035 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5036 } else if (Feature == "+fp-armv8") { 5037 FPU |= FPARMV8; 5038 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5039 } else if (Feature == "+neon") { 5040 FPU |= NeonFPU; 5041 HW_FP |= HW_FP_SP | HW_FP_DP; 5042 } else if (Feature == "+hwdiv") { 5043 HWDiv |= HWDivThumb; 5044 } else if (Feature == "+hwdiv-arm") { 5045 HWDiv |= HWDivARM; 5046 } else if (Feature == "+crc") { 5047 CRC = 1; 5048 } else if (Feature == "+crypto") { 5049 Crypto = 1; 5050 } else if (Feature == "+dsp") { 5051 DSP = 1; 5052 } else if (Feature == "+fp-only-sp") { 5053 HW_FP_remove |= HW_FP_DP; 5054 } else if (Feature == "+strict-align") { 5055 Unaligned = 0; 5056 } else if (Feature == "+fp16") { 5057 HW_FP |= HW_FP_HP; 5058 } 5059 } 5060 HW_FP &= ~HW_FP_remove; 5061 5062 switch (ArchVersion) { 5063 case 6: 5064 if (ArchProfile == llvm::ARM::PK_M) 5065 LDREX = 0; 5066 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5067 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5068 else 5069 LDREX = LDREX_W; 5070 break; 5071 case 7: 5072 if (ArchProfile == llvm::ARM::PK_M) 5073 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5074 else 5075 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5076 break; 5077 case 8: 5078 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5079 } 5080 5081 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5082 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5083 return false; 5084 } 5085 5086 if (FPMath == FP_Neon) 5087 Features.push_back("+neonfp"); 5088 else if (FPMath == FP_VFP) 5089 Features.push_back("-neonfp"); 5090 5091 // Remove front-end specific options which the backend handles differently. 5092 auto Feature = 5093 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5094 if (Feature != Features.end()) 5095 Features.erase(Feature); 5096 5097 return true; 5098 } 5099 5100 bool hasFeature(StringRef Feature) const override { 5101 return llvm::StringSwitch<bool>(Feature) 5102 .Case("arm", true) 5103 .Case("aarch32", true) 5104 .Case("softfloat", SoftFloat) 5105 .Case("thumb", isThumb()) 5106 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5107 .Case("hwdiv", HWDiv & HWDivThumb) 5108 .Case("hwdiv-arm", HWDiv & HWDivARM) 5109 .Default(false); 5110 } 5111 5112 bool setCPU(const std::string &Name) override { 5113 if (Name != "generic") 5114 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5115 5116 if (ArchKind == llvm::ARM::AK_INVALID) 5117 return false; 5118 setAtomic(); 5119 CPU = Name; 5120 return true; 5121 } 5122 5123 bool setFPMath(StringRef Name) override; 5124 5125 void getTargetDefines(const LangOptions &Opts, 5126 MacroBuilder &Builder) const override { 5127 // Target identification. 5128 Builder.defineMacro("__arm"); 5129 Builder.defineMacro("__arm__"); 5130 // For bare-metal none-eabi. 5131 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5132 getTriple().getEnvironment() == llvm::Triple::EABI) 5133 Builder.defineMacro("__ELF__"); 5134 5135 // Target properties. 5136 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5137 5138 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5139 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5140 if (getTriple().isWatchABI()) 5141 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5142 5143 if (!CPUAttr.empty()) 5144 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5145 5146 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5147 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5148 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5149 5150 if (ArchVersion >= 8) { 5151 // ACLE 6.5.7 Crypto Extension 5152 if (Crypto) 5153 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5154 // ACLE 6.5.8 CRC32 Extension 5155 if (CRC) 5156 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5157 // ACLE 6.5.10 Numeric Maximum and Minimum 5158 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5159 // ACLE 6.5.9 Directed Rounding 5160 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5161 } 5162 5163 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5164 // is not defined for the M-profile. 5165 // NOTE that the default profile is assumed to be 'A' 5166 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5167 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5168 5169 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5170 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5171 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5172 // v7 and v8 architectures excluding v8-M Baseline. 5173 if (supportsThumb2()) 5174 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5175 else if (supportsThumb()) 5176 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5177 5178 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5179 // instruction set such as ARM or Thumb. 5180 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5181 5182 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5183 5184 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5185 if (!CPUProfile.empty()) 5186 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5187 5188 // ACLE 6.4.3 Unaligned access supported in hardware 5189 if (Unaligned) 5190 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5191 5192 // ACLE 6.4.4 LDREX/STREX 5193 if (LDREX) 5194 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5195 5196 // ACLE 6.4.5 CLZ 5197 if (ArchVersion == 5 || 5198 (ArchVersion == 6 && CPUProfile != "M") || 5199 ArchVersion > 6) 5200 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5201 5202 // ACLE 6.5.1 Hardware Floating Point 5203 if (HW_FP) 5204 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5205 5206 // ACLE predefines. 5207 Builder.defineMacro("__ARM_ACLE", "200"); 5208 5209 // FP16 support (we currently only support IEEE format). 5210 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5211 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5212 5213 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5214 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5215 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5216 5217 // Subtarget options. 5218 5219 // FIXME: It's more complicated than this and we don't really support 5220 // interworking. 5221 // Windows on ARM does not "support" interworking 5222 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5223 Builder.defineMacro("__THUMB_INTERWORK__"); 5224 5225 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5226 // Embedded targets on Darwin follow AAPCS, but not EABI. 5227 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5228 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5229 Builder.defineMacro("__ARM_EABI__"); 5230 Builder.defineMacro("__ARM_PCS", "1"); 5231 } 5232 5233 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5234 ABI == "aapcs16") 5235 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5236 5237 if (SoftFloat) 5238 Builder.defineMacro("__SOFTFP__"); 5239 5240 if (ArchKind == llvm::ARM::AK_XSCALE) 5241 Builder.defineMacro("__XSCALE__"); 5242 5243 if (isThumb()) { 5244 Builder.defineMacro("__THUMBEL__"); 5245 Builder.defineMacro("__thumb__"); 5246 if (supportsThumb2()) 5247 Builder.defineMacro("__thumb2__"); 5248 } 5249 5250 // ACLE 6.4.9 32-bit SIMD instructions 5251 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5252 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5253 5254 // ACLE 6.4.10 Hardware Integer Divide 5255 if (((HWDiv & HWDivThumb) && isThumb()) || 5256 ((HWDiv & HWDivARM) && !isThumb())) { 5257 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5258 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5259 } 5260 5261 // Note, this is always on in gcc, even though it doesn't make sense. 5262 Builder.defineMacro("__APCS_32__"); 5263 5264 if (FPUModeIsVFP((FPUMode) FPU)) { 5265 Builder.defineMacro("__VFP_FP__"); 5266 if (FPU & VFP2FPU) 5267 Builder.defineMacro("__ARM_VFPV2__"); 5268 if (FPU & VFP3FPU) 5269 Builder.defineMacro("__ARM_VFPV3__"); 5270 if (FPU & VFP4FPU) 5271 Builder.defineMacro("__ARM_VFPV4__"); 5272 } 5273 5274 // This only gets set when Neon instructions are actually available, unlike 5275 // the VFP define, hence the soft float and arch check. This is subtly 5276 // different from gcc, we follow the intent which was that it should be set 5277 // when Neon instructions are actually available. 5278 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5279 Builder.defineMacro("__ARM_NEON", "1"); 5280 Builder.defineMacro("__ARM_NEON__"); 5281 // current AArch32 NEON implementations do not support double-precision 5282 // floating-point even when it is present in VFP. 5283 Builder.defineMacro("__ARM_NEON_FP", 5284 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5285 } 5286 5287 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5288 Opts.ShortWChar ? "2" : "4"); 5289 5290 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5291 Opts.ShortEnums ? "1" : "4"); 5292 5293 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5294 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5295 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5296 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5297 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5298 } 5299 5300 // ACLE 6.4.7 DSP instructions 5301 if (DSP) { 5302 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5303 } 5304 5305 // ACLE 6.4.8 Saturation instructions 5306 bool SAT = false; 5307 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5308 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5309 SAT = true; 5310 } 5311 5312 // ACLE 6.4.6 Q (saturation) flag 5313 if (DSP || SAT) 5314 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5315 5316 if (Opts.UnsafeFPMath) 5317 Builder.defineMacro("__ARM_FP_FAST", "1"); 5318 5319 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5320 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5321 } 5322 5323 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5324 return llvm::makeArrayRef(BuiltinInfo, 5325 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5326 } 5327 bool isCLZForZeroUndef() const override { return false; } 5328 BuiltinVaListKind getBuiltinVaListKind() const override { 5329 return IsAAPCS 5330 ? AAPCSABIBuiltinVaList 5331 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5332 : TargetInfo::VoidPtrBuiltinVaList); 5333 } 5334 ArrayRef<const char *> getGCCRegNames() const override; 5335 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5336 bool validateAsmConstraint(const char *&Name, 5337 TargetInfo::ConstraintInfo &Info) const override { 5338 switch (*Name) { 5339 default: break; 5340 case 'l': // r0-r7 5341 case 'h': // r8-r15 5342 case 't': // VFP Floating point register single precision 5343 case 'w': // VFP Floating point register double precision 5344 Info.setAllowsRegister(); 5345 return true; 5346 case 'I': 5347 case 'J': 5348 case 'K': 5349 case 'L': 5350 case 'M': 5351 // FIXME 5352 return true; 5353 case 'Q': // A memory address that is a single base register. 5354 Info.setAllowsMemory(); 5355 return true; 5356 case 'U': // a memory reference... 5357 switch (Name[1]) { 5358 case 'q': // ...ARMV4 ldrsb 5359 case 'v': // ...VFP load/store (reg+constant offset) 5360 case 'y': // ...iWMMXt load/store 5361 case 't': // address valid for load/store opaque types wider 5362 // than 128-bits 5363 case 'n': // valid address for Neon doubleword vector load/store 5364 case 'm': // valid address for Neon element and structure load/store 5365 case 's': // valid address for non-offset loads/stores of quad-word 5366 // values in four ARM registers 5367 Info.setAllowsMemory(); 5368 Name++; 5369 return true; 5370 } 5371 } 5372 return false; 5373 } 5374 std::string convertConstraint(const char *&Constraint) const override { 5375 std::string R; 5376 switch (*Constraint) { 5377 case 'U': // Two-character constraint; add "^" hint for later parsing. 5378 R = std::string("^") + std::string(Constraint, 2); 5379 Constraint++; 5380 break; 5381 case 'p': // 'p' should be translated to 'r' by default. 5382 R = std::string("r"); 5383 break; 5384 default: 5385 return std::string(1, *Constraint); 5386 } 5387 return R; 5388 } 5389 bool 5390 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5391 std::string &SuggestedModifier) const override { 5392 bool isOutput = (Constraint[0] == '='); 5393 bool isInOut = (Constraint[0] == '+'); 5394 5395 // Strip off constraint modifiers. 5396 while (Constraint[0] == '=' || 5397 Constraint[0] == '+' || 5398 Constraint[0] == '&') 5399 Constraint = Constraint.substr(1); 5400 5401 switch (Constraint[0]) { 5402 default: break; 5403 case 'r': { 5404 switch (Modifier) { 5405 default: 5406 return (isInOut || isOutput || Size <= 64); 5407 case 'q': 5408 // A register of size 32 cannot fit a vector type. 5409 return false; 5410 } 5411 } 5412 } 5413 5414 return true; 5415 } 5416 const char *getClobbers() const override { 5417 // FIXME: Is this really right? 5418 return ""; 5419 } 5420 5421 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5422 switch (CC) { 5423 case CC_AAPCS: 5424 case CC_AAPCS_VFP: 5425 case CC_Swift: 5426 return CCCR_OK; 5427 default: 5428 return CCCR_Warning; 5429 } 5430 } 5431 5432 int getEHDataRegisterNumber(unsigned RegNo) const override { 5433 if (RegNo == 0) return 0; 5434 if (RegNo == 1) return 1; 5435 return -1; 5436 } 5437 5438 bool hasSjLjLowering() const override { 5439 return true; 5440 } 5441 }; 5442 5443 bool ARMTargetInfo::setFPMath(StringRef Name) { 5444 if (Name == "neon") { 5445 FPMath = FP_Neon; 5446 return true; 5447 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5448 Name == "vfp4") { 5449 FPMath = FP_VFP; 5450 return true; 5451 } 5452 return false; 5453 } 5454 5455 const char * const ARMTargetInfo::GCCRegNames[] = { 5456 // Integer registers 5457 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5458 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5459 5460 // Float registers 5461 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5462 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5463 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5464 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5465 5466 // Double registers 5467 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5468 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5469 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5470 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5471 5472 // Quad registers 5473 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5474 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5475 }; 5476 5477 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5478 return llvm::makeArrayRef(GCCRegNames); 5479 } 5480 5481 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5482 { { "a1" }, "r0" }, 5483 { { "a2" }, "r1" }, 5484 { { "a3" }, "r2" }, 5485 { { "a4" }, "r3" }, 5486 { { "v1" }, "r4" }, 5487 { { "v2" }, "r5" }, 5488 { { "v3" }, "r6" }, 5489 { { "v4" }, "r7" }, 5490 { { "v5" }, "r8" }, 5491 { { "v6", "rfp" }, "r9" }, 5492 { { "sl" }, "r10" }, 5493 { { "fp" }, "r11" }, 5494 { { "ip" }, "r12" }, 5495 { { "r13" }, "sp" }, 5496 { { "r14" }, "lr" }, 5497 { { "r15" }, "pc" }, 5498 // The S, D and Q registers overlap, but aren't really aliases; we 5499 // don't want to substitute one of these for a different-sized one. 5500 }; 5501 5502 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5503 return llvm::makeArrayRef(GCCRegAliases); 5504 } 5505 5506 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5507 #define BUILTIN(ID, TYPE, ATTRS) \ 5508 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5509 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5510 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5511 #include "clang/Basic/BuiltinsNEON.def" 5512 5513 #define BUILTIN(ID, TYPE, ATTRS) \ 5514 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5515 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5516 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5517 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5518 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5519 #include "clang/Basic/BuiltinsARM.def" 5520 }; 5521 5522 class ARMleTargetInfo : public ARMTargetInfo { 5523 public: 5524 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5525 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/false) {} 5526 void getTargetDefines(const LangOptions &Opts, 5527 MacroBuilder &Builder) const override { 5528 Builder.defineMacro("__ARMEL__"); 5529 ARMTargetInfo::getTargetDefines(Opts, Builder); 5530 } 5531 }; 5532 5533 class ARMbeTargetInfo : public ARMTargetInfo { 5534 public: 5535 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5536 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/true) {} 5537 void getTargetDefines(const LangOptions &Opts, 5538 MacroBuilder &Builder) const override { 5539 Builder.defineMacro("__ARMEB__"); 5540 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5541 ARMTargetInfo::getTargetDefines(Opts, Builder); 5542 } 5543 }; 5544 5545 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5546 const llvm::Triple Triple; 5547 public: 5548 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5549 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5550 WCharType = UnsignedShort; 5551 SizeType = UnsignedInt; 5552 } 5553 void getVisualStudioDefines(const LangOptions &Opts, 5554 MacroBuilder &Builder) const { 5555 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5556 5557 // FIXME: this is invalid for WindowsCE 5558 Builder.defineMacro("_M_ARM_NT", "1"); 5559 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5560 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5561 5562 assert((Triple.getArch() == llvm::Triple::arm || 5563 Triple.getArch() == llvm::Triple::thumb) && 5564 "invalid architecture for Windows ARM target info"); 5565 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5566 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5567 5568 // TODO map the complete set of values 5569 // 31: VFPv3 40: VFPv4 5570 Builder.defineMacro("_M_ARM_FP", "31"); 5571 } 5572 BuiltinVaListKind getBuiltinVaListKind() const override { 5573 return TargetInfo::CharPtrBuiltinVaList; 5574 } 5575 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5576 switch (CC) { 5577 case CC_X86StdCall: 5578 case CC_X86ThisCall: 5579 case CC_X86FastCall: 5580 case CC_X86VectorCall: 5581 return CCCR_Ignore; 5582 case CC_C: 5583 return CCCR_OK; 5584 default: 5585 return CCCR_Warning; 5586 } 5587 } 5588 }; 5589 5590 // Windows ARM + Itanium C++ ABI Target 5591 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5592 public: 5593 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5594 const TargetOptions &Opts) 5595 : WindowsARMTargetInfo(Triple, Opts) { 5596 TheCXXABI.set(TargetCXXABI::GenericARM); 5597 } 5598 5599 void getTargetDefines(const LangOptions &Opts, 5600 MacroBuilder &Builder) const override { 5601 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5602 5603 if (Opts.MSVCCompat) 5604 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5605 } 5606 }; 5607 5608 // Windows ARM, MS (C++) ABI 5609 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5610 public: 5611 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5612 const TargetOptions &Opts) 5613 : WindowsARMTargetInfo(Triple, Opts) { 5614 TheCXXABI.set(TargetCXXABI::Microsoft); 5615 } 5616 5617 void getTargetDefines(const LangOptions &Opts, 5618 MacroBuilder &Builder) const override { 5619 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5620 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5621 } 5622 }; 5623 5624 // ARM MinGW target 5625 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5626 public: 5627 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5628 : WindowsARMTargetInfo(Triple, Opts) { 5629 TheCXXABI.set(TargetCXXABI::GenericARM); 5630 } 5631 5632 void getTargetDefines(const LangOptions &Opts, 5633 MacroBuilder &Builder) const override { 5634 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5635 DefineStd(Builder, "WIN32", Opts); 5636 DefineStd(Builder, "WINNT", Opts); 5637 Builder.defineMacro("_ARM_"); 5638 addMinGWDefines(Opts, Builder); 5639 } 5640 }; 5641 5642 // ARM Cygwin target 5643 class CygwinARMTargetInfo : public ARMleTargetInfo { 5644 public: 5645 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5646 : ARMleTargetInfo(Triple, Opts) { 5647 TLSSupported = false; 5648 WCharType = UnsignedShort; 5649 DoubleAlign = LongLongAlign = 64; 5650 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5651 } 5652 void getTargetDefines(const LangOptions &Opts, 5653 MacroBuilder &Builder) const override { 5654 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5655 Builder.defineMacro("_ARM_"); 5656 Builder.defineMacro("__CYGWIN__"); 5657 Builder.defineMacro("__CYGWIN32__"); 5658 DefineStd(Builder, "unix", Opts); 5659 if (Opts.CPlusPlus) 5660 Builder.defineMacro("_GNU_SOURCE"); 5661 } 5662 }; 5663 5664 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 5665 protected: 5666 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5667 MacroBuilder &Builder) const override { 5668 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5669 } 5670 5671 public: 5672 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5673 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 5674 HasAlignMac68kSupport = true; 5675 // iOS always has 64-bit atomic instructions. 5676 // FIXME: This should be based off of the target features in 5677 // ARMleTargetInfo. 5678 MaxAtomicInlineWidth = 64; 5679 5680 if (Triple.isWatchABI()) { 5681 // Darwin on iOS uses a variant of the ARM C++ ABI. 5682 TheCXXABI.set(TargetCXXABI::WatchOS); 5683 5684 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5685 // size_t is long, it's a bit weird for it to be int. 5686 PtrDiffType = SignedLong; 5687 5688 // BOOL should be a real boolean on the new ABI 5689 UseSignedCharForObjCBool = false; 5690 } else 5691 TheCXXABI.set(TargetCXXABI::iOS); 5692 } 5693 }; 5694 5695 class AArch64TargetInfo : public TargetInfo { 5696 virtual void setDataLayout() = 0; 5697 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5698 static const char *const GCCRegNames[]; 5699 5700 enum FPUModeEnum { 5701 FPUMode, 5702 NeonMode 5703 }; 5704 5705 unsigned FPU; 5706 unsigned CRC; 5707 unsigned Crypto; 5708 unsigned Unaligned; 5709 unsigned V8_1A; 5710 5711 static const Builtin::Info BuiltinInfo[]; 5712 5713 std::string ABI; 5714 5715 public: 5716 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5717 : TargetInfo(Triple), ABI("aapcs") { 5718 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5719 WCharType = SignedInt; 5720 5721 // NetBSD apparently prefers consistency across ARM targets to consistency 5722 // across 64-bit targets. 5723 Int64Type = SignedLongLong; 5724 IntMaxType = SignedLongLong; 5725 } else { 5726 WCharType = UnsignedInt; 5727 Int64Type = SignedLong; 5728 IntMaxType = SignedLong; 5729 } 5730 5731 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5732 MaxVectorAlign = 128; 5733 MaxAtomicInlineWidth = 128; 5734 MaxAtomicPromoteWidth = 128; 5735 5736 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5737 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5738 5739 // {} in inline assembly are neon specifiers, not assembly variant 5740 // specifiers. 5741 NoAsmVariants = true; 5742 5743 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5744 // contributes to the alignment of the containing aggregate in the same way 5745 // a plain (non bit-field) member of that type would, without exception for 5746 // zero-sized or anonymous bit-fields." 5747 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5748 UseZeroLengthBitfieldAlignment = true; 5749 5750 // AArch64 targets default to using the ARM C++ ABI. 5751 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5752 5753 if (Triple.getOS() == llvm::Triple::Linux || 5754 Triple.getOS() == llvm::Triple::UnknownOS) 5755 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 5756 } 5757 5758 StringRef getABI() const override { return ABI; } 5759 bool setABI(const std::string &Name) override { 5760 if (Name != "aapcs" && Name != "darwinpcs") 5761 return false; 5762 5763 ABI = Name; 5764 return true; 5765 } 5766 5767 bool setCPU(const std::string &Name) override { 5768 return Name == "generic" || 5769 llvm::AArch64::parseCPUArch(Name) != 5770 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 5771 } 5772 5773 void getTargetDefines(const LangOptions &Opts, 5774 MacroBuilder &Builder) const override { 5775 // Target identification. 5776 Builder.defineMacro("__aarch64__"); 5777 5778 // Target properties. 5779 Builder.defineMacro("_LP64"); 5780 Builder.defineMacro("__LP64__"); 5781 5782 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5783 Builder.defineMacro("__ARM_ACLE", "200"); 5784 Builder.defineMacro("__ARM_ARCH", "8"); 5785 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5786 5787 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5788 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5789 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5790 5791 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5792 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5793 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5794 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5795 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5796 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5797 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5798 5799 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5800 5801 // 0xe implies support for half, single and double precision operations. 5802 Builder.defineMacro("__ARM_FP", "0xE"); 5803 5804 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5805 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5806 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5807 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5808 5809 if (Opts.UnsafeFPMath) 5810 Builder.defineMacro("__ARM_FP_FAST", "1"); 5811 5812 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5813 5814 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5815 Opts.ShortEnums ? "1" : "4"); 5816 5817 if (FPU == NeonMode) { 5818 Builder.defineMacro("__ARM_NEON", "1"); 5819 // 64-bit NEON supports half, single and double precision operations. 5820 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5821 } 5822 5823 if (CRC) 5824 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5825 5826 if (Crypto) 5827 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5828 5829 if (Unaligned) 5830 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5831 5832 if (V8_1A) 5833 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5834 5835 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5836 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5837 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5838 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5839 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5840 } 5841 5842 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5843 return llvm::makeArrayRef(BuiltinInfo, 5844 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5845 } 5846 5847 bool hasFeature(StringRef Feature) const override { 5848 return Feature == "aarch64" || 5849 Feature == "arm64" || 5850 Feature == "arm" || 5851 (Feature == "neon" && FPU == NeonMode); 5852 } 5853 5854 bool handleTargetFeatures(std::vector<std::string> &Features, 5855 DiagnosticsEngine &Diags) override { 5856 FPU = FPUMode; 5857 CRC = 0; 5858 Crypto = 0; 5859 Unaligned = 1; 5860 V8_1A = 0; 5861 5862 for (const auto &Feature : Features) { 5863 if (Feature == "+neon") 5864 FPU = NeonMode; 5865 if (Feature == "+crc") 5866 CRC = 1; 5867 if (Feature == "+crypto") 5868 Crypto = 1; 5869 if (Feature == "+strict-align") 5870 Unaligned = 0; 5871 if (Feature == "+v8.1a") 5872 V8_1A = 1; 5873 } 5874 5875 setDataLayout(); 5876 5877 return true; 5878 } 5879 5880 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5881 switch (CC) { 5882 case CC_C: 5883 case CC_Swift: 5884 case CC_PreserveMost: 5885 case CC_PreserveAll: 5886 return CCCR_OK; 5887 default: 5888 return CCCR_Warning; 5889 } 5890 } 5891 5892 bool isCLZForZeroUndef() const override { return false; } 5893 5894 BuiltinVaListKind getBuiltinVaListKind() const override { 5895 return TargetInfo::AArch64ABIBuiltinVaList; 5896 } 5897 5898 ArrayRef<const char *> getGCCRegNames() const override; 5899 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5900 5901 bool validateAsmConstraint(const char *&Name, 5902 TargetInfo::ConstraintInfo &Info) const override { 5903 switch (*Name) { 5904 default: 5905 return false; 5906 case 'w': // Floating point and SIMD registers (V0-V31) 5907 Info.setAllowsRegister(); 5908 return true; 5909 case 'I': // Constant that can be used with an ADD instruction 5910 case 'J': // Constant that can be used with a SUB instruction 5911 case 'K': // Constant that can be used with a 32-bit logical instruction 5912 case 'L': // Constant that can be used with a 64-bit logical instruction 5913 case 'M': // Constant that can be used as a 32-bit MOV immediate 5914 case 'N': // Constant that can be used as a 64-bit MOV immediate 5915 case 'Y': // Floating point constant zero 5916 case 'Z': // Integer constant zero 5917 return true; 5918 case 'Q': // A memory reference with base register and no offset 5919 Info.setAllowsMemory(); 5920 return true; 5921 case 'S': // A symbolic address 5922 Info.setAllowsRegister(); 5923 return true; 5924 case 'U': 5925 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5926 // Utf: A memory address suitable for ldp/stp in TF mode. 5927 // Usa: An absolute symbolic address. 5928 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5929 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5930 case 'z': // Zero register, wzr or xzr 5931 Info.setAllowsRegister(); 5932 return true; 5933 case 'x': // Floating point and SIMD registers (V0-V15) 5934 Info.setAllowsRegister(); 5935 return true; 5936 } 5937 return false; 5938 } 5939 5940 bool 5941 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5942 std::string &SuggestedModifier) const override { 5943 // Strip off constraint modifiers. 5944 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5945 Constraint = Constraint.substr(1); 5946 5947 switch (Constraint[0]) { 5948 default: 5949 return true; 5950 case 'z': 5951 case 'r': { 5952 switch (Modifier) { 5953 case 'x': 5954 case 'w': 5955 // For now assume that the person knows what they're 5956 // doing with the modifier. 5957 return true; 5958 default: 5959 // By default an 'r' constraint will be in the 'x' 5960 // registers. 5961 if (Size == 64) 5962 return true; 5963 5964 SuggestedModifier = "w"; 5965 return false; 5966 } 5967 } 5968 } 5969 } 5970 5971 const char *getClobbers() const override { return ""; } 5972 5973 int getEHDataRegisterNumber(unsigned RegNo) const override { 5974 if (RegNo == 0) 5975 return 0; 5976 if (RegNo == 1) 5977 return 1; 5978 return -1; 5979 } 5980 }; 5981 5982 const char *const AArch64TargetInfo::GCCRegNames[] = { 5983 // 32-bit Integer registers 5984 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5985 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5986 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5987 5988 // 64-bit Integer registers 5989 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5990 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5991 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5992 5993 // 32-bit floating point regsisters 5994 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5995 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5996 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5997 5998 // 64-bit floating point regsisters 5999 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 6000 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 6001 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6002 6003 // Vector registers 6004 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6005 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6006 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6007 }; 6008 6009 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6010 return llvm::makeArrayRef(GCCRegNames); 6011 } 6012 6013 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6014 { { "w31" }, "wsp" }, 6015 { { "x29" }, "fp" }, 6016 { { "x30" }, "lr" }, 6017 { { "x31" }, "sp" }, 6018 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6019 // don't want to substitute one of these for a different-sized one. 6020 }; 6021 6022 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6023 return llvm::makeArrayRef(GCCRegAliases); 6024 } 6025 6026 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6027 #define BUILTIN(ID, TYPE, ATTRS) \ 6028 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6029 #include "clang/Basic/BuiltinsNEON.def" 6030 6031 #define BUILTIN(ID, TYPE, ATTRS) \ 6032 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6033 #include "clang/Basic/BuiltinsAArch64.def" 6034 }; 6035 6036 class AArch64leTargetInfo : public AArch64TargetInfo { 6037 void setDataLayout() override { 6038 if (getTriple().isOSBinFormatMachO()) 6039 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6040 else 6041 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6042 } 6043 6044 public: 6045 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6046 : AArch64TargetInfo(Triple, Opts) { 6047 BigEndian = false; 6048 } 6049 void getTargetDefines(const LangOptions &Opts, 6050 MacroBuilder &Builder) const override { 6051 Builder.defineMacro("__AARCH64EL__"); 6052 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6053 } 6054 }; 6055 6056 class AArch64beTargetInfo : public AArch64TargetInfo { 6057 void setDataLayout() override { 6058 assert(!getTriple().isOSBinFormatMachO()); 6059 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6060 } 6061 6062 public: 6063 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6064 : AArch64TargetInfo(Triple, Opts) {} 6065 void getTargetDefines(const LangOptions &Opts, 6066 MacroBuilder &Builder) const override { 6067 Builder.defineMacro("__AARCH64EB__"); 6068 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6069 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6070 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6071 } 6072 }; 6073 6074 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6075 protected: 6076 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6077 MacroBuilder &Builder) const override { 6078 Builder.defineMacro("__AARCH64_SIMD__"); 6079 Builder.defineMacro("__ARM64_ARCH_8__"); 6080 Builder.defineMacro("__ARM_NEON__"); 6081 Builder.defineMacro("__LITTLE_ENDIAN__"); 6082 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6083 Builder.defineMacro("__arm64", "1"); 6084 Builder.defineMacro("__arm64__", "1"); 6085 6086 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6087 } 6088 6089 public: 6090 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6091 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6092 Int64Type = SignedLongLong; 6093 WCharType = SignedInt; 6094 UseSignedCharForObjCBool = false; 6095 6096 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6097 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6098 6099 TheCXXABI.set(TargetCXXABI::iOS64); 6100 } 6101 6102 BuiltinVaListKind getBuiltinVaListKind() const override { 6103 return TargetInfo::CharPtrBuiltinVaList; 6104 } 6105 }; 6106 6107 // Hexagon abstract base class 6108 class HexagonTargetInfo : public TargetInfo { 6109 static const Builtin::Info BuiltinInfo[]; 6110 static const char * const GCCRegNames[]; 6111 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6112 std::string CPU; 6113 bool HasHVX, HasHVXDouble; 6114 bool UseLongCalls; 6115 6116 public: 6117 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6118 : TargetInfo(Triple) { 6119 BigEndian = false; 6120 // Specify the vector alignment explicitly. For v512x1, the calculated 6121 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6122 // the required minimum of 64 bytes. 6123 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6124 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6125 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6126 SizeType = UnsignedInt; 6127 PtrDiffType = SignedInt; 6128 IntPtrType = SignedInt; 6129 6130 // {} in inline assembly are packet specifiers, not assembly variant 6131 // specifiers. 6132 NoAsmVariants = true; 6133 6134 LargeArrayMinWidth = 64; 6135 LargeArrayAlign = 64; 6136 UseBitFieldTypeAlignment = true; 6137 ZeroLengthBitfieldBoundary = 32; 6138 HasHVX = HasHVXDouble = false; 6139 UseLongCalls = false; 6140 } 6141 6142 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6143 return llvm::makeArrayRef(BuiltinInfo, 6144 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6145 } 6146 6147 bool validateAsmConstraint(const char *&Name, 6148 TargetInfo::ConstraintInfo &Info) const override { 6149 switch (*Name) { 6150 case 'v': 6151 case 'q': 6152 if (HasHVX) { 6153 Info.setAllowsRegister(); 6154 return true; 6155 } 6156 break; 6157 case 's': 6158 // Relocatable constant. 6159 return true; 6160 } 6161 return false; 6162 } 6163 6164 void getTargetDefines(const LangOptions &Opts, 6165 MacroBuilder &Builder) const override; 6166 6167 bool isCLZForZeroUndef() const override { return false; } 6168 6169 bool hasFeature(StringRef Feature) const override { 6170 return llvm::StringSwitch<bool>(Feature) 6171 .Case("hexagon", true) 6172 .Case("hvx", HasHVX) 6173 .Case("hvx-double", HasHVXDouble) 6174 .Case("long-calls", UseLongCalls) 6175 .Default(false); 6176 } 6177 6178 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6179 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6180 const override; 6181 6182 bool handleTargetFeatures(std::vector<std::string> &Features, 6183 DiagnosticsEngine &Diags) override; 6184 6185 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6186 bool Enabled) const override; 6187 6188 BuiltinVaListKind getBuiltinVaListKind() const override { 6189 return TargetInfo::CharPtrBuiltinVaList; 6190 } 6191 ArrayRef<const char *> getGCCRegNames() const override; 6192 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6193 const char *getClobbers() const override { 6194 return ""; 6195 } 6196 6197 static const char *getHexagonCPUSuffix(StringRef Name) { 6198 return llvm::StringSwitch<const char*>(Name) 6199 .Case("hexagonv4", "4") 6200 .Case("hexagonv5", "5") 6201 .Case("hexagonv55", "55") 6202 .Case("hexagonv60", "60") 6203 .Default(nullptr); 6204 } 6205 6206 bool setCPU(const std::string &Name) override { 6207 if (!getHexagonCPUSuffix(Name)) 6208 return false; 6209 CPU = Name; 6210 return true; 6211 } 6212 6213 int getEHDataRegisterNumber(unsigned RegNo) const override { 6214 return RegNo < 2 ? RegNo : -1; 6215 } 6216 }; 6217 6218 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6219 MacroBuilder &Builder) const { 6220 Builder.defineMacro("__qdsp6__", "1"); 6221 Builder.defineMacro("__hexagon__", "1"); 6222 6223 if (CPU == "hexagonv4") { 6224 Builder.defineMacro("__HEXAGON_V4__"); 6225 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6226 if (Opts.HexagonQdsp6Compat) { 6227 Builder.defineMacro("__QDSP6_V4__"); 6228 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6229 } 6230 } else if (CPU == "hexagonv5") { 6231 Builder.defineMacro("__HEXAGON_V5__"); 6232 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6233 if(Opts.HexagonQdsp6Compat) { 6234 Builder.defineMacro("__QDSP6_V5__"); 6235 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6236 } 6237 } else if (CPU == "hexagonv55") { 6238 Builder.defineMacro("__HEXAGON_V55__"); 6239 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6240 Builder.defineMacro("__QDSP6_V55__"); 6241 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6242 } else if (CPU == "hexagonv60") { 6243 Builder.defineMacro("__HEXAGON_V60__"); 6244 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6245 Builder.defineMacro("__QDSP6_V60__"); 6246 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6247 } 6248 6249 if (hasFeature("hvx")) { 6250 Builder.defineMacro("__HVX__"); 6251 if (hasFeature("hvx-double")) 6252 Builder.defineMacro("__HVXDBL__"); 6253 } 6254 } 6255 6256 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6257 DiagnosticsEngine &Diags, StringRef CPU, 6258 const std::vector<std::string> &FeaturesVec) const { 6259 // Default for v60: -hvx, -hvx-double. 6260 Features["hvx"] = false; 6261 Features["hvx-double"] = false; 6262 Features["long-calls"] = false; 6263 6264 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6265 } 6266 6267 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6268 DiagnosticsEngine &Diags) { 6269 for (auto &F : Features) { 6270 if (F == "+hvx") 6271 HasHVX = true; 6272 else if (F == "-hvx") 6273 HasHVX = HasHVXDouble = false; 6274 else if (F == "+hvx-double") 6275 HasHVX = HasHVXDouble = true; 6276 else if (F == "-hvx-double") 6277 HasHVXDouble = false; 6278 6279 if (F == "+long-calls") 6280 UseLongCalls = true; 6281 else if (F == "-long-calls") 6282 UseLongCalls = false; 6283 } 6284 return true; 6285 } 6286 6287 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 6288 StringRef Name, bool Enabled) const { 6289 if (Enabled) { 6290 if (Name == "hvx-double") 6291 Features["hvx"] = true; 6292 } else { 6293 if (Name == "hvx") 6294 Features["hvx-double"] = false; 6295 } 6296 Features[Name] = Enabled; 6297 } 6298 6299 const char *const HexagonTargetInfo::GCCRegNames[] = { 6300 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6301 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6302 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6303 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6304 "p0", "p1", "p2", "p3", 6305 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6306 }; 6307 6308 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6309 return llvm::makeArrayRef(GCCRegNames); 6310 } 6311 6312 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6313 { { "sp" }, "r29" }, 6314 { { "fp" }, "r30" }, 6315 { { "lr" }, "r31" }, 6316 }; 6317 6318 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6319 return llvm::makeArrayRef(GCCRegAliases); 6320 } 6321 6322 6323 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6324 #define BUILTIN(ID, TYPE, ATTRS) \ 6325 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6326 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6327 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6328 #include "clang/Basic/BuiltinsHexagon.def" 6329 }; 6330 6331 class LanaiTargetInfo : public TargetInfo { 6332 // Class for Lanai (32-bit). 6333 // The CPU profiles supported by the Lanai backend 6334 enum CPUKind { 6335 CK_NONE, 6336 CK_V11, 6337 } CPU; 6338 6339 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6340 static const char *const GCCRegNames[]; 6341 6342 public: 6343 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6344 : TargetInfo(Triple) { 6345 // Description string has to be kept in sync with backend. 6346 resetDataLayout("E" // Big endian 6347 "-m:e" // ELF name manging 6348 "-p:32:32" // 32 bit pointers, 32 bit aligned 6349 "-i64:64" // 64 bit integers, 64 bit aligned 6350 "-a:0:32" // 32 bit alignment of objects of aggregate type 6351 "-n32" // 32 bit native integer width 6352 "-S64" // 64 bit natural stack alignment 6353 ); 6354 6355 // Setting RegParmMax equal to what mregparm was set to in the old 6356 // toolchain 6357 RegParmMax = 4; 6358 6359 // Set the default CPU to V11 6360 CPU = CK_V11; 6361 6362 // Temporary approach to make everything at least word-aligned and allow for 6363 // safely casting between pointers with different alignment requirements. 6364 // TODO: Remove this when there are no more cast align warnings on the 6365 // firmware. 6366 MinGlobalAlign = 32; 6367 } 6368 6369 void getTargetDefines(const LangOptions &Opts, 6370 MacroBuilder &Builder) const override { 6371 // Define __lanai__ when building for target lanai. 6372 Builder.defineMacro("__lanai__"); 6373 6374 // Set define for the CPU specified. 6375 switch (CPU) { 6376 case CK_V11: 6377 Builder.defineMacro("__LANAI_V11__"); 6378 break; 6379 case CK_NONE: 6380 llvm_unreachable("Unhandled target CPU"); 6381 } 6382 } 6383 6384 bool setCPU(const std::string &Name) override { 6385 CPU = llvm::StringSwitch<CPUKind>(Name) 6386 .Case("v11", CK_V11) 6387 .Default(CK_NONE); 6388 6389 return CPU != CK_NONE; 6390 } 6391 6392 bool hasFeature(StringRef Feature) const override { 6393 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6394 } 6395 6396 ArrayRef<const char *> getGCCRegNames() const override; 6397 6398 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6399 6400 BuiltinVaListKind getBuiltinVaListKind() const override { 6401 return TargetInfo::VoidPtrBuiltinVaList; 6402 } 6403 6404 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6405 6406 bool validateAsmConstraint(const char *&Name, 6407 TargetInfo::ConstraintInfo &info) const override { 6408 return false; 6409 } 6410 6411 const char *getClobbers() const override { return ""; } 6412 }; 6413 6414 const char *const LanaiTargetInfo::GCCRegNames[] = { 6415 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6416 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6417 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6418 6419 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6420 return llvm::makeArrayRef(GCCRegNames); 6421 } 6422 6423 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6424 {{"pc"}, "r2"}, 6425 {{"sp"}, "r4"}, 6426 {{"fp"}, "r5"}, 6427 {{"rv"}, "r8"}, 6428 {{"rr1"}, "r10"}, 6429 {{"rr2"}, "r11"}, 6430 {{"rca"}, "r15"}, 6431 }; 6432 6433 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6434 return llvm::makeArrayRef(GCCRegAliases); 6435 } 6436 6437 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6438 class SparcTargetInfo : public TargetInfo { 6439 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6440 static const char * const GCCRegNames[]; 6441 bool SoftFloat; 6442 public: 6443 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6444 : TargetInfo(Triple), SoftFloat(false) {} 6445 6446 int getEHDataRegisterNumber(unsigned RegNo) const override { 6447 if (RegNo == 0) return 24; 6448 if (RegNo == 1) return 25; 6449 return -1; 6450 } 6451 6452 bool handleTargetFeatures(std::vector<std::string> &Features, 6453 DiagnosticsEngine &Diags) override { 6454 // Check if software floating point is enabled 6455 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6456 if (Feature != Features.end()) { 6457 SoftFloat = true; 6458 } 6459 return true; 6460 } 6461 void getTargetDefines(const LangOptions &Opts, 6462 MacroBuilder &Builder) const override { 6463 DefineStd(Builder, "sparc", Opts); 6464 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6465 6466 if (SoftFloat) 6467 Builder.defineMacro("SOFT_FLOAT", "1"); 6468 } 6469 6470 bool hasFeature(StringRef Feature) const override { 6471 return llvm::StringSwitch<bool>(Feature) 6472 .Case("softfloat", SoftFloat) 6473 .Case("sparc", true) 6474 .Default(false); 6475 } 6476 6477 bool hasSjLjLowering() const override { 6478 return true; 6479 } 6480 6481 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6482 // FIXME: Implement! 6483 return None; 6484 } 6485 BuiltinVaListKind getBuiltinVaListKind() const override { 6486 return TargetInfo::VoidPtrBuiltinVaList; 6487 } 6488 ArrayRef<const char *> getGCCRegNames() const override; 6489 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6490 bool validateAsmConstraint(const char *&Name, 6491 TargetInfo::ConstraintInfo &info) const override { 6492 // FIXME: Implement! 6493 switch (*Name) { 6494 case 'I': // Signed 13-bit constant 6495 case 'J': // Zero 6496 case 'K': // 32-bit constant with the low 12 bits clear 6497 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6498 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6499 case 'N': // Same as 'K' but zext (required for SIMode) 6500 case 'O': // The constant 4096 6501 return true; 6502 } 6503 return false; 6504 } 6505 const char *getClobbers() const override { 6506 // FIXME: Implement! 6507 return ""; 6508 } 6509 6510 // No Sparc V7 for now, the backend doesn't support it anyway. 6511 enum CPUKind { 6512 CK_GENERIC, 6513 CK_V8, 6514 CK_SUPERSPARC, 6515 CK_SPARCLITE, 6516 CK_F934, 6517 CK_HYPERSPARC, 6518 CK_SPARCLITE86X, 6519 CK_SPARCLET, 6520 CK_TSC701, 6521 CK_V9, 6522 CK_ULTRASPARC, 6523 CK_ULTRASPARC3, 6524 CK_NIAGARA, 6525 CK_NIAGARA2, 6526 CK_NIAGARA3, 6527 CK_NIAGARA4, 6528 CK_MYRIAD2100, 6529 CK_MYRIAD2150, 6530 CK_MYRIAD2450, 6531 CK_LEON2, 6532 CK_LEON2_AT697E, 6533 CK_LEON2_AT697F, 6534 CK_LEON3, 6535 CK_LEON3_UT699, 6536 CK_LEON3_GR712RC, 6537 CK_LEON4, 6538 CK_LEON4_GR740 6539 } CPU = CK_GENERIC; 6540 6541 enum CPUGeneration { 6542 CG_V8, 6543 CG_V9, 6544 }; 6545 6546 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6547 switch (Kind) { 6548 case CK_GENERIC: 6549 case CK_V8: 6550 case CK_SUPERSPARC: 6551 case CK_SPARCLITE: 6552 case CK_F934: 6553 case CK_HYPERSPARC: 6554 case CK_SPARCLITE86X: 6555 case CK_SPARCLET: 6556 case CK_TSC701: 6557 case CK_MYRIAD2100: 6558 case CK_MYRIAD2150: 6559 case CK_MYRIAD2450: 6560 case CK_LEON2: 6561 case CK_LEON2_AT697E: 6562 case CK_LEON2_AT697F: 6563 case CK_LEON3: 6564 case CK_LEON3_UT699: 6565 case CK_LEON3_GR712RC: 6566 case CK_LEON4: 6567 case CK_LEON4_GR740: 6568 return CG_V8; 6569 case CK_V9: 6570 case CK_ULTRASPARC: 6571 case CK_ULTRASPARC3: 6572 case CK_NIAGARA: 6573 case CK_NIAGARA2: 6574 case CK_NIAGARA3: 6575 case CK_NIAGARA4: 6576 return CG_V9; 6577 } 6578 llvm_unreachable("Unexpected CPU kind"); 6579 } 6580 6581 CPUKind getCPUKind(StringRef Name) const { 6582 return llvm::StringSwitch<CPUKind>(Name) 6583 .Case("v8", CK_V8) 6584 .Case("supersparc", CK_SUPERSPARC) 6585 .Case("sparclite", CK_SPARCLITE) 6586 .Case("f934", CK_F934) 6587 .Case("hypersparc", CK_HYPERSPARC) 6588 .Case("sparclite86x", CK_SPARCLITE86X) 6589 .Case("sparclet", CK_SPARCLET) 6590 .Case("tsc701", CK_TSC701) 6591 .Case("v9", CK_V9) 6592 .Case("ultrasparc", CK_ULTRASPARC) 6593 .Case("ultrasparc3", CK_ULTRASPARC3) 6594 .Case("niagara", CK_NIAGARA) 6595 .Case("niagara2", CK_NIAGARA2) 6596 .Case("niagara3", CK_NIAGARA3) 6597 .Case("niagara4", CK_NIAGARA4) 6598 .Case("ma2100", CK_MYRIAD2100) 6599 .Case("ma2150", CK_MYRIAD2150) 6600 .Case("ma2450", CK_MYRIAD2450) 6601 // FIXME: the myriad2[.n] spellings are obsolete, 6602 // but a grace period is needed to allow updating dependent builds. 6603 .Case("myriad2", CK_MYRIAD2100) 6604 .Case("myriad2.1", CK_MYRIAD2100) 6605 .Case("myriad2.2", CK_MYRIAD2150) 6606 .Case("leon2", CK_LEON2) 6607 .Case("at697e", CK_LEON2_AT697E) 6608 .Case("at697f", CK_LEON2_AT697F) 6609 .Case("leon3", CK_LEON3) 6610 .Case("ut699", CK_LEON3_UT699) 6611 .Case("gr712rc", CK_LEON3_GR712RC) 6612 .Case("leon4", CK_LEON4) 6613 .Case("gr740", CK_LEON4_GR740) 6614 .Default(CK_GENERIC); 6615 } 6616 6617 bool setCPU(const std::string &Name) override { 6618 CPU = getCPUKind(Name); 6619 return CPU != CK_GENERIC; 6620 } 6621 }; 6622 6623 const char * const SparcTargetInfo::GCCRegNames[] = { 6624 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6625 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6626 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6627 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6628 }; 6629 6630 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6631 return llvm::makeArrayRef(GCCRegNames); 6632 } 6633 6634 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6635 { { "g0" }, "r0" }, 6636 { { "g1" }, "r1" }, 6637 { { "g2" }, "r2" }, 6638 { { "g3" }, "r3" }, 6639 { { "g4" }, "r4" }, 6640 { { "g5" }, "r5" }, 6641 { { "g6" }, "r6" }, 6642 { { "g7" }, "r7" }, 6643 { { "o0" }, "r8" }, 6644 { { "o1" }, "r9" }, 6645 { { "o2" }, "r10" }, 6646 { { "o3" }, "r11" }, 6647 { { "o4" }, "r12" }, 6648 { { "o5" }, "r13" }, 6649 { { "o6", "sp" }, "r14" }, 6650 { { "o7" }, "r15" }, 6651 { { "l0" }, "r16" }, 6652 { { "l1" }, "r17" }, 6653 { { "l2" }, "r18" }, 6654 { { "l3" }, "r19" }, 6655 { { "l4" }, "r20" }, 6656 { { "l5" }, "r21" }, 6657 { { "l6" }, "r22" }, 6658 { { "l7" }, "r23" }, 6659 { { "i0" }, "r24" }, 6660 { { "i1" }, "r25" }, 6661 { { "i2" }, "r26" }, 6662 { { "i3" }, "r27" }, 6663 { { "i4" }, "r28" }, 6664 { { "i5" }, "r29" }, 6665 { { "i6", "fp" }, "r30" }, 6666 { { "i7" }, "r31" }, 6667 }; 6668 6669 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6670 return llvm::makeArrayRef(GCCRegAliases); 6671 } 6672 6673 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6674 class SparcV8TargetInfo : public SparcTargetInfo { 6675 public: 6676 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6677 : SparcTargetInfo(Triple, Opts) { 6678 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6679 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6680 switch (getTriple().getOS()) { 6681 default: 6682 SizeType = UnsignedInt; 6683 IntPtrType = SignedInt; 6684 PtrDiffType = SignedInt; 6685 break; 6686 case llvm::Triple::NetBSD: 6687 case llvm::Triple::OpenBSD: 6688 SizeType = UnsignedLong; 6689 IntPtrType = SignedLong; 6690 PtrDiffType = SignedLong; 6691 break; 6692 } 6693 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6694 } 6695 6696 void getTargetDefines(const LangOptions &Opts, 6697 MacroBuilder &Builder) const override { 6698 SparcTargetInfo::getTargetDefines(Opts, Builder); 6699 switch (getCPUGeneration(CPU)) { 6700 case CG_V8: 6701 Builder.defineMacro("__sparcv8"); 6702 if (getTriple().getOS() != llvm::Triple::Solaris) 6703 Builder.defineMacro("__sparcv8__"); 6704 break; 6705 case CG_V9: 6706 Builder.defineMacro("__sparcv9"); 6707 if (getTriple().getOS() != llvm::Triple::Solaris) { 6708 Builder.defineMacro("__sparcv9__"); 6709 Builder.defineMacro("__sparc_v9__"); 6710 } 6711 break; 6712 } 6713 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6714 std::string MyriadArchValue, Myriad2Value; 6715 Builder.defineMacro("__sparc_v8__"); 6716 Builder.defineMacro("__leon__"); 6717 switch (CPU) { 6718 case CK_MYRIAD2150: 6719 MyriadArchValue = "__ma2150"; 6720 Myriad2Value = "2"; 6721 break; 6722 case CK_MYRIAD2450: 6723 MyriadArchValue = "__ma2450"; 6724 Myriad2Value = "2"; 6725 break; 6726 default: 6727 MyriadArchValue = "__ma2100"; 6728 Myriad2Value = "1"; 6729 break; 6730 } 6731 Builder.defineMacro(MyriadArchValue, "1"); 6732 Builder.defineMacro(MyriadArchValue+"__", "1"); 6733 Builder.defineMacro("__myriad2__", Myriad2Value); 6734 Builder.defineMacro("__myriad2", Myriad2Value); 6735 } 6736 } 6737 6738 bool hasSjLjLowering() const override { 6739 return true; 6740 } 6741 }; 6742 6743 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6744 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6745 public: 6746 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6747 : SparcV8TargetInfo(Triple, Opts) { 6748 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6749 BigEndian = false; 6750 } 6751 }; 6752 6753 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6754 class SparcV9TargetInfo : public SparcTargetInfo { 6755 public: 6756 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6757 : SparcTargetInfo(Triple, Opts) { 6758 // FIXME: Support Sparc quad-precision long double? 6759 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6760 // This is an LP64 platform. 6761 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6762 6763 // OpenBSD uses long long for int64_t and intmax_t. 6764 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6765 IntMaxType = SignedLongLong; 6766 else 6767 IntMaxType = SignedLong; 6768 Int64Type = IntMaxType; 6769 6770 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6771 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6772 LongDoubleWidth = 128; 6773 LongDoubleAlign = 128; 6774 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6775 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6776 } 6777 6778 void getTargetDefines(const LangOptions &Opts, 6779 MacroBuilder &Builder) const override { 6780 SparcTargetInfo::getTargetDefines(Opts, Builder); 6781 Builder.defineMacro("__sparcv9"); 6782 Builder.defineMacro("__arch64__"); 6783 // Solaris doesn't need these variants, but the BSDs do. 6784 if (getTriple().getOS() != llvm::Triple::Solaris) { 6785 Builder.defineMacro("__sparc64__"); 6786 Builder.defineMacro("__sparc_v9__"); 6787 Builder.defineMacro("__sparcv9__"); 6788 } 6789 } 6790 6791 bool setCPU(const std::string &Name) override { 6792 if (!SparcTargetInfo::setCPU(Name)) 6793 return false; 6794 return getCPUGeneration(CPU) == CG_V9; 6795 } 6796 }; 6797 6798 class SystemZTargetInfo : public TargetInfo { 6799 static const Builtin::Info BuiltinInfo[]; 6800 static const char *const GCCRegNames[]; 6801 std::string CPU; 6802 bool HasTransactionalExecution; 6803 bool HasVector; 6804 6805 public: 6806 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6807 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6808 HasVector(false) { 6809 IntMaxType = SignedLong; 6810 Int64Type = SignedLong; 6811 TLSSupported = true; 6812 IntWidth = IntAlign = 32; 6813 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6814 PointerWidth = PointerAlign = 64; 6815 LongDoubleWidth = 128; 6816 LongDoubleAlign = 64; 6817 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6818 DefaultAlignForAttributeAligned = 64; 6819 MinGlobalAlign = 16; 6820 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 6821 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6822 } 6823 void getTargetDefines(const LangOptions &Opts, 6824 MacroBuilder &Builder) const override { 6825 Builder.defineMacro("__s390__"); 6826 Builder.defineMacro("__s390x__"); 6827 Builder.defineMacro("__zarch__"); 6828 Builder.defineMacro("__LONG_DOUBLE_128__"); 6829 6830 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6831 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6832 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6833 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6834 6835 if (HasTransactionalExecution) 6836 Builder.defineMacro("__HTM__"); 6837 if (Opts.ZVector) 6838 Builder.defineMacro("__VEC__", "10301"); 6839 } 6840 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6841 return llvm::makeArrayRef(BuiltinInfo, 6842 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6843 } 6844 6845 ArrayRef<const char *> getGCCRegNames() const override; 6846 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6847 // No aliases. 6848 return None; 6849 } 6850 bool validateAsmConstraint(const char *&Name, 6851 TargetInfo::ConstraintInfo &info) const override; 6852 const char *getClobbers() const override { 6853 // FIXME: Is this really right? 6854 return ""; 6855 } 6856 BuiltinVaListKind getBuiltinVaListKind() const override { 6857 return TargetInfo::SystemZBuiltinVaList; 6858 } 6859 bool setCPU(const std::string &Name) override { 6860 CPU = Name; 6861 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6862 .Case("z10", true) 6863 .Case("z196", true) 6864 .Case("zEC12", true) 6865 .Case("z13", true) 6866 .Default(false); 6867 6868 return CPUKnown; 6869 } 6870 bool 6871 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6872 StringRef CPU, 6873 const std::vector<std::string> &FeaturesVec) const override { 6874 if (CPU == "zEC12") 6875 Features["transactional-execution"] = true; 6876 if (CPU == "z13") { 6877 Features["transactional-execution"] = true; 6878 Features["vector"] = true; 6879 } 6880 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6881 } 6882 6883 bool handleTargetFeatures(std::vector<std::string> &Features, 6884 DiagnosticsEngine &Diags) override { 6885 HasTransactionalExecution = false; 6886 for (const auto &Feature : Features) { 6887 if (Feature == "+transactional-execution") 6888 HasTransactionalExecution = true; 6889 else if (Feature == "+vector") 6890 HasVector = true; 6891 } 6892 // If we use the vector ABI, vector types are 64-bit aligned. 6893 if (HasVector) { 6894 MaxVectorAlign = 64; 6895 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6896 "-v128:64-a:8:16-n32:64"); 6897 } 6898 return true; 6899 } 6900 6901 bool hasFeature(StringRef Feature) const override { 6902 return llvm::StringSwitch<bool>(Feature) 6903 .Case("systemz", true) 6904 .Case("htm", HasTransactionalExecution) 6905 .Case("vx", HasVector) 6906 .Default(false); 6907 } 6908 6909 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6910 switch (CC) { 6911 case CC_C: 6912 case CC_Swift: 6913 return CCCR_OK; 6914 default: 6915 return CCCR_Warning; 6916 } 6917 } 6918 6919 StringRef getABI() const override { 6920 if (HasVector) 6921 return "vector"; 6922 return ""; 6923 } 6924 6925 bool useFloat128ManglingForLongDouble() const override { 6926 return true; 6927 } 6928 }; 6929 6930 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6931 #define BUILTIN(ID, TYPE, ATTRS) \ 6932 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6933 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 6934 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 6935 #include "clang/Basic/BuiltinsSystemZ.def" 6936 }; 6937 6938 const char *const SystemZTargetInfo::GCCRegNames[] = { 6939 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6940 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6941 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6942 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6943 }; 6944 6945 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6946 return llvm::makeArrayRef(GCCRegNames); 6947 } 6948 6949 bool SystemZTargetInfo:: 6950 validateAsmConstraint(const char *&Name, 6951 TargetInfo::ConstraintInfo &Info) const { 6952 switch (*Name) { 6953 default: 6954 return false; 6955 6956 case 'a': // Address register 6957 case 'd': // Data register (equivalent to 'r') 6958 case 'f': // Floating-point register 6959 Info.setAllowsRegister(); 6960 return true; 6961 6962 case 'I': // Unsigned 8-bit constant 6963 case 'J': // Unsigned 12-bit constant 6964 case 'K': // Signed 16-bit constant 6965 case 'L': // Signed 20-bit displacement (on all targets we support) 6966 case 'M': // 0x7fffffff 6967 return true; 6968 6969 case 'Q': // Memory with base and unsigned 12-bit displacement 6970 case 'R': // Likewise, plus an index 6971 case 'S': // Memory with base and signed 20-bit displacement 6972 case 'T': // Likewise, plus an index 6973 Info.setAllowsMemory(); 6974 return true; 6975 } 6976 } 6977 6978 class MSP430TargetInfo : public TargetInfo { 6979 static const char *const GCCRegNames[]; 6980 6981 public: 6982 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6983 : TargetInfo(Triple) { 6984 BigEndian = false; 6985 TLSSupported = false; 6986 IntWidth = 16; 6987 IntAlign = 16; 6988 LongWidth = 32; 6989 LongLongWidth = 64; 6990 LongAlign = LongLongAlign = 16; 6991 PointerWidth = 16; 6992 PointerAlign = 16; 6993 SuitableAlign = 16; 6994 SizeType = UnsignedInt; 6995 IntMaxType = SignedLongLong; 6996 IntPtrType = SignedInt; 6997 PtrDiffType = SignedInt; 6998 SigAtomicType = SignedLong; 6999 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 7000 } 7001 void getTargetDefines(const LangOptions &Opts, 7002 MacroBuilder &Builder) const override { 7003 Builder.defineMacro("MSP430"); 7004 Builder.defineMacro("__MSP430__"); 7005 // FIXME: defines for different 'flavours' of MCU 7006 } 7007 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7008 // FIXME: Implement. 7009 return None; 7010 } 7011 bool hasFeature(StringRef Feature) const override { 7012 return Feature == "msp430"; 7013 } 7014 ArrayRef<const char *> getGCCRegNames() const override; 7015 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7016 // No aliases. 7017 return None; 7018 } 7019 bool validateAsmConstraint(const char *&Name, 7020 TargetInfo::ConstraintInfo &info) const override { 7021 // FIXME: implement 7022 switch (*Name) { 7023 case 'K': // the constant 1 7024 case 'L': // constant -1^20 .. 1^19 7025 case 'M': // constant 1-4: 7026 return true; 7027 } 7028 // No target constraints for now. 7029 return false; 7030 } 7031 const char *getClobbers() const override { 7032 // FIXME: Is this really right? 7033 return ""; 7034 } 7035 BuiltinVaListKind getBuiltinVaListKind() const override { 7036 // FIXME: implement 7037 return TargetInfo::CharPtrBuiltinVaList; 7038 } 7039 }; 7040 7041 const char *const MSP430TargetInfo::GCCRegNames[] = { 7042 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7043 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7044 7045 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7046 return llvm::makeArrayRef(GCCRegNames); 7047 } 7048 7049 // LLVM and Clang cannot be used directly to output native binaries for 7050 // target, but is used to compile C code to llvm bitcode with correct 7051 // type and alignment information. 7052 // 7053 // TCE uses the llvm bitcode as input and uses it for generating customized 7054 // target processor and program binary. TCE co-design environment is 7055 // publicly available in http://tce.cs.tut.fi 7056 7057 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7058 3, // opencl_global 7059 4, // opencl_local 7060 5, // opencl_constant 7061 // FIXME: generic has to be added to the target 7062 0, // opencl_generic 7063 0, // cuda_device 7064 0, // cuda_constant 7065 0 // cuda_shared 7066 }; 7067 7068 class TCETargetInfo : public TargetInfo { 7069 public: 7070 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7071 : TargetInfo(Triple) { 7072 TLSSupported = false; 7073 IntWidth = 32; 7074 LongWidth = LongLongWidth = 32; 7075 PointerWidth = 32; 7076 IntAlign = 32; 7077 LongAlign = LongLongAlign = 32; 7078 PointerAlign = 32; 7079 SuitableAlign = 32; 7080 SizeType = UnsignedInt; 7081 IntMaxType = SignedLong; 7082 IntPtrType = SignedInt; 7083 PtrDiffType = SignedInt; 7084 FloatWidth = 32; 7085 FloatAlign = 32; 7086 DoubleWidth = 32; 7087 DoubleAlign = 32; 7088 LongDoubleWidth = 32; 7089 LongDoubleAlign = 32; 7090 FloatFormat = &llvm::APFloat::IEEEsingle; 7091 DoubleFormat = &llvm::APFloat::IEEEsingle; 7092 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 7093 resetDataLayout("E-p:32:32-i8:8:32-i16:16:32-i64:32" 7094 "-f64:32-v64:32-v128:32-a:0:32-n32"); 7095 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7096 UseAddrSpaceMapMangling = true; 7097 } 7098 7099 void getTargetDefines(const LangOptions &Opts, 7100 MacroBuilder &Builder) const override { 7101 DefineStd(Builder, "tce", Opts); 7102 Builder.defineMacro("__TCE__"); 7103 Builder.defineMacro("__TCE_V1__"); 7104 } 7105 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7106 7107 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7108 const char *getClobbers() const override { return ""; } 7109 BuiltinVaListKind getBuiltinVaListKind() const override { 7110 return TargetInfo::VoidPtrBuiltinVaList; 7111 } 7112 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7113 bool validateAsmConstraint(const char *&Name, 7114 TargetInfo::ConstraintInfo &info) const override { 7115 return true; 7116 } 7117 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7118 return None; 7119 } 7120 }; 7121 7122 class BPFTargetInfo : public TargetInfo { 7123 public: 7124 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7125 : TargetInfo(Triple) { 7126 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7127 SizeType = UnsignedLong; 7128 PtrDiffType = SignedLong; 7129 IntPtrType = SignedLong; 7130 IntMaxType = SignedLong; 7131 Int64Type = SignedLong; 7132 RegParmMax = 5; 7133 if (Triple.getArch() == llvm::Triple::bpfeb) { 7134 BigEndian = true; 7135 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7136 } else { 7137 BigEndian = false; 7138 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7139 } 7140 MaxAtomicPromoteWidth = 64; 7141 MaxAtomicInlineWidth = 64; 7142 TLSSupported = false; 7143 } 7144 void getTargetDefines(const LangOptions &Opts, 7145 MacroBuilder &Builder) const override { 7146 DefineStd(Builder, "bpf", Opts); 7147 Builder.defineMacro("__BPF__"); 7148 } 7149 bool hasFeature(StringRef Feature) const override { 7150 return Feature == "bpf"; 7151 } 7152 7153 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7154 const char *getClobbers() const override { 7155 return ""; 7156 } 7157 BuiltinVaListKind getBuiltinVaListKind() const override { 7158 return TargetInfo::VoidPtrBuiltinVaList; 7159 } 7160 ArrayRef<const char *> getGCCRegNames() const override { 7161 return None; 7162 } 7163 bool validateAsmConstraint(const char *&Name, 7164 TargetInfo::ConstraintInfo &info) const override { 7165 return true; 7166 } 7167 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7168 return None; 7169 } 7170 }; 7171 7172 class MipsTargetInfo : public TargetInfo { 7173 void setDataLayout() { 7174 StringRef Layout; 7175 7176 if (ABI == "o32") 7177 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7178 else if (ABI == "n32") 7179 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7180 else if (ABI == "n64") 7181 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7182 else 7183 llvm_unreachable("Invalid ABI"); 7184 7185 if (BigEndian) 7186 resetDataLayout(("E-" + Layout).str()); 7187 else 7188 resetDataLayout(("e-" + Layout).str()); 7189 } 7190 7191 7192 static const Builtin::Info BuiltinInfo[]; 7193 std::string CPU; 7194 bool IsMips16; 7195 bool IsMicromips; 7196 bool IsNan2008; 7197 bool IsSingleFloat; 7198 enum MipsFloatABI { 7199 HardFloat, SoftFloat 7200 } FloatABI; 7201 enum DspRevEnum { 7202 NoDSP, DSP1, DSP2 7203 } DspRev; 7204 bool HasMSA; 7205 7206 protected: 7207 bool HasFP64; 7208 std::string ABI; 7209 7210 public: 7211 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7212 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7213 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 7214 DspRev(NoDSP), HasMSA(false), HasFP64(false) { 7215 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7216 BigEndian = getTriple().getArch() == llvm::Triple::mips || 7217 getTriple().getArch() == llvm::Triple::mips64; 7218 7219 setABI((getTriple().getArch() == llvm::Triple::mips || 7220 getTriple().getArch() == llvm::Triple::mipsel) 7221 ? "o32" 7222 : "n64"); 7223 7224 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7225 } 7226 7227 bool isNaN2008Default() const { 7228 return CPU == "mips32r6" || CPU == "mips64r6"; 7229 } 7230 7231 bool isFP64Default() const { 7232 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7233 } 7234 7235 bool isNan2008() const override { 7236 return IsNan2008; 7237 } 7238 7239 bool processorSupportsGPR64() const { 7240 return llvm::StringSwitch<bool>(CPU) 7241 .Case("mips3", true) 7242 .Case("mips4", true) 7243 .Case("mips5", true) 7244 .Case("mips64", true) 7245 .Case("mips64r2", true) 7246 .Case("mips64r3", true) 7247 .Case("mips64r5", true) 7248 .Case("mips64r6", true) 7249 .Case("octeon", true) 7250 .Default(false); 7251 return false; 7252 } 7253 7254 StringRef getABI() const override { return ABI; } 7255 bool setABI(const std::string &Name) override { 7256 if (Name == "o32") { 7257 setO32ABITypes(); 7258 ABI = Name; 7259 return true; 7260 } 7261 7262 if (Name == "n32") { 7263 setN32ABITypes(); 7264 ABI = Name; 7265 return true; 7266 } 7267 if (Name == "n64") { 7268 setN64ABITypes(); 7269 ABI = Name; 7270 return true; 7271 } 7272 return false; 7273 } 7274 7275 void setO32ABITypes() { 7276 Int64Type = SignedLongLong; 7277 IntMaxType = Int64Type; 7278 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7279 LongDoubleWidth = LongDoubleAlign = 64; 7280 LongWidth = LongAlign = 32; 7281 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7282 PointerWidth = PointerAlign = 32; 7283 PtrDiffType = SignedInt; 7284 SizeType = UnsignedInt; 7285 SuitableAlign = 64; 7286 } 7287 7288 void setN32N64ABITypes() { 7289 LongDoubleWidth = LongDoubleAlign = 128; 7290 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7291 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7292 LongDoubleWidth = LongDoubleAlign = 64; 7293 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7294 } 7295 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7296 SuitableAlign = 128; 7297 } 7298 7299 void setN64ABITypes() { 7300 setN32N64ABITypes(); 7301 Int64Type = SignedLong; 7302 IntMaxType = Int64Type; 7303 LongWidth = LongAlign = 64; 7304 PointerWidth = PointerAlign = 64; 7305 PtrDiffType = SignedLong; 7306 SizeType = UnsignedLong; 7307 } 7308 7309 void setN32ABITypes() { 7310 setN32N64ABITypes(); 7311 Int64Type = SignedLongLong; 7312 IntMaxType = Int64Type; 7313 LongWidth = LongAlign = 32; 7314 PointerWidth = PointerAlign = 32; 7315 PtrDiffType = SignedInt; 7316 SizeType = UnsignedInt; 7317 } 7318 7319 bool setCPU(const std::string &Name) override { 7320 CPU = Name; 7321 return llvm::StringSwitch<bool>(Name) 7322 .Case("mips1", true) 7323 .Case("mips2", true) 7324 .Case("mips3", true) 7325 .Case("mips4", true) 7326 .Case("mips5", true) 7327 .Case("mips32", true) 7328 .Case("mips32r2", true) 7329 .Case("mips32r3", true) 7330 .Case("mips32r5", true) 7331 .Case("mips32r6", true) 7332 .Case("mips64", true) 7333 .Case("mips64r2", true) 7334 .Case("mips64r3", true) 7335 .Case("mips64r5", true) 7336 .Case("mips64r6", true) 7337 .Case("octeon", true) 7338 .Case("p5600", true) 7339 .Default(false); 7340 } 7341 const std::string& getCPU() const { return CPU; } 7342 bool 7343 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7344 StringRef CPU, 7345 const std::vector<std::string> &FeaturesVec) const override { 7346 if (CPU.empty()) 7347 CPU = getCPU(); 7348 if (CPU == "octeon") 7349 Features["mips64r2"] = Features["cnmips"] = true; 7350 else 7351 Features[CPU] = true; 7352 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7353 } 7354 7355 void getTargetDefines(const LangOptions &Opts, 7356 MacroBuilder &Builder) const override { 7357 if (BigEndian) { 7358 DefineStd(Builder, "MIPSEB", Opts); 7359 Builder.defineMacro("_MIPSEB"); 7360 } else { 7361 DefineStd(Builder, "MIPSEL", Opts); 7362 Builder.defineMacro("_MIPSEL"); 7363 } 7364 7365 Builder.defineMacro("__mips__"); 7366 Builder.defineMacro("_mips"); 7367 if (Opts.GNUMode) 7368 Builder.defineMacro("mips"); 7369 7370 if (ABI == "o32") { 7371 Builder.defineMacro("__mips", "32"); 7372 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7373 } else { 7374 Builder.defineMacro("__mips", "64"); 7375 Builder.defineMacro("__mips64"); 7376 Builder.defineMacro("__mips64__"); 7377 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7378 } 7379 7380 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7381 .Cases("mips32", "mips64", "1") 7382 .Cases("mips32r2", "mips64r2", "2") 7383 .Cases("mips32r3", "mips64r3", "3") 7384 .Cases("mips32r5", "mips64r5", "5") 7385 .Cases("mips32r6", "mips64r6", "6") 7386 .Default(""); 7387 if (!ISARev.empty()) 7388 Builder.defineMacro("__mips_isa_rev", ISARev); 7389 7390 if (ABI == "o32") { 7391 Builder.defineMacro("__mips_o32"); 7392 Builder.defineMacro("_ABIO32", "1"); 7393 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7394 } else if (ABI == "n32") { 7395 Builder.defineMacro("__mips_n32"); 7396 Builder.defineMacro("_ABIN32", "2"); 7397 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7398 } else if (ABI == "n64") { 7399 Builder.defineMacro("__mips_n64"); 7400 Builder.defineMacro("_ABI64", "3"); 7401 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7402 } else 7403 llvm_unreachable("Invalid ABI."); 7404 7405 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7406 7407 switch (FloatABI) { 7408 case HardFloat: 7409 Builder.defineMacro("__mips_hard_float", Twine(1)); 7410 break; 7411 case SoftFloat: 7412 Builder.defineMacro("__mips_soft_float", Twine(1)); 7413 break; 7414 } 7415 7416 if (IsSingleFloat) 7417 Builder.defineMacro("__mips_single_float", Twine(1)); 7418 7419 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7420 Builder.defineMacro("_MIPS_FPSET", 7421 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7422 7423 if (IsMips16) 7424 Builder.defineMacro("__mips16", Twine(1)); 7425 7426 if (IsMicromips) 7427 Builder.defineMacro("__mips_micromips", Twine(1)); 7428 7429 if (IsNan2008) 7430 Builder.defineMacro("__mips_nan2008", Twine(1)); 7431 7432 switch (DspRev) { 7433 default: 7434 break; 7435 case DSP1: 7436 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7437 Builder.defineMacro("__mips_dsp", Twine(1)); 7438 break; 7439 case DSP2: 7440 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7441 Builder.defineMacro("__mips_dspr2", Twine(1)); 7442 Builder.defineMacro("__mips_dsp", Twine(1)); 7443 break; 7444 } 7445 7446 if (HasMSA) 7447 Builder.defineMacro("__mips_msa", Twine(1)); 7448 7449 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7450 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7451 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7452 7453 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7454 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7455 7456 // These shouldn't be defined for MIPS-I but there's no need to check 7457 // for that since MIPS-I isn't supported. 7458 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7459 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7460 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7461 7462 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7463 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7464 // the instructions exist but using them violates the ABI since they 7465 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7466 if (ABI == "n32" || ABI == "n64") 7467 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7468 } 7469 7470 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7471 return llvm::makeArrayRef(BuiltinInfo, 7472 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7473 } 7474 bool hasFeature(StringRef Feature) const override { 7475 return llvm::StringSwitch<bool>(Feature) 7476 .Case("mips", true) 7477 .Case("fp64", HasFP64) 7478 .Default(false); 7479 } 7480 BuiltinVaListKind getBuiltinVaListKind() const override { 7481 return TargetInfo::VoidPtrBuiltinVaList; 7482 } 7483 ArrayRef<const char *> getGCCRegNames() const override { 7484 static const char *const GCCRegNames[] = { 7485 // CPU register names 7486 // Must match second column of GCCRegAliases 7487 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7488 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7489 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7490 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7491 // Floating point register names 7492 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7493 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7494 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7495 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7496 // Hi/lo and condition register names 7497 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7498 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7499 "$ac3hi","$ac3lo", 7500 // MSA register names 7501 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7502 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7503 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7504 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7505 // MSA control register names 7506 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7507 "$msarequest", "$msamap", "$msaunmap" 7508 }; 7509 return llvm::makeArrayRef(GCCRegNames); 7510 } 7511 bool validateAsmConstraint(const char *&Name, 7512 TargetInfo::ConstraintInfo &Info) const override { 7513 switch (*Name) { 7514 default: 7515 return false; 7516 case 'r': // CPU registers. 7517 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7518 case 'y': // Equivalent to "r", backward compatibility only. 7519 case 'f': // floating-point registers. 7520 case 'c': // $25 for indirect jumps 7521 case 'l': // lo register 7522 case 'x': // hilo register pair 7523 Info.setAllowsRegister(); 7524 return true; 7525 case 'I': // Signed 16-bit constant 7526 case 'J': // Integer 0 7527 case 'K': // Unsigned 16-bit constant 7528 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7529 case 'M': // Constants not loadable via lui, addiu, or ori 7530 case 'N': // Constant -1 to -65535 7531 case 'O': // A signed 15-bit constant 7532 case 'P': // A constant between 1 go 65535 7533 return true; 7534 case 'R': // An address that can be used in a non-macro load or store 7535 Info.setAllowsMemory(); 7536 return true; 7537 case 'Z': 7538 if (Name[1] == 'C') { // An address usable by ll, and sc. 7539 Info.setAllowsMemory(); 7540 Name++; // Skip over 'Z'. 7541 return true; 7542 } 7543 return false; 7544 } 7545 } 7546 7547 std::string convertConstraint(const char *&Constraint) const override { 7548 std::string R; 7549 switch (*Constraint) { 7550 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7551 if (Constraint[1] == 'C') { 7552 R = std::string("^") + std::string(Constraint, 2); 7553 Constraint++; 7554 return R; 7555 } 7556 break; 7557 } 7558 return TargetInfo::convertConstraint(Constraint); 7559 } 7560 7561 const char *getClobbers() const override { 7562 // In GCC, $1 is not widely used in generated code (it's used only in a few 7563 // specific situations), so there is no real need for users to add it to 7564 // the clobbers list if they want to use it in their inline assembly code. 7565 // 7566 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7567 // code generation, so using it in inline assembly without adding it to the 7568 // clobbers list can cause conflicts between the inline assembly code and 7569 // the surrounding generated code. 7570 // 7571 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7572 // operands, which will conflict with the ".set at" assembler option (which 7573 // we use only for inline assembly, in order to maintain compatibility with 7574 // GCC) and will also conflict with the user's usage of $1. 7575 // 7576 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7577 // register for generated code is to automatically clobber $1 for all inline 7578 // assembly code. 7579 // 7580 // FIXME: We should automatically clobber $1 only for inline assembly code 7581 // which actually uses it. This would allow LLVM to use $1 for inline 7582 // assembly operands if the user's assembly code doesn't use it. 7583 return "~{$1}"; 7584 } 7585 7586 bool handleTargetFeatures(std::vector<std::string> &Features, 7587 DiagnosticsEngine &Diags) override { 7588 IsMips16 = false; 7589 IsMicromips = false; 7590 IsNan2008 = isNaN2008Default(); 7591 IsSingleFloat = false; 7592 FloatABI = HardFloat; 7593 DspRev = NoDSP; 7594 HasFP64 = isFP64Default(); 7595 7596 for (const auto &Feature : Features) { 7597 if (Feature == "+single-float") 7598 IsSingleFloat = true; 7599 else if (Feature == "+soft-float") 7600 FloatABI = SoftFloat; 7601 else if (Feature == "+mips16") 7602 IsMips16 = true; 7603 else if (Feature == "+micromips") 7604 IsMicromips = true; 7605 else if (Feature == "+dsp") 7606 DspRev = std::max(DspRev, DSP1); 7607 else if (Feature == "+dspr2") 7608 DspRev = std::max(DspRev, DSP2); 7609 else if (Feature == "+msa") 7610 HasMSA = true; 7611 else if (Feature == "+fp64") 7612 HasFP64 = true; 7613 else if (Feature == "-fp64") 7614 HasFP64 = false; 7615 else if (Feature == "+nan2008") 7616 IsNan2008 = true; 7617 else if (Feature == "-nan2008") 7618 IsNan2008 = false; 7619 } 7620 7621 setDataLayout(); 7622 7623 return true; 7624 } 7625 7626 int getEHDataRegisterNumber(unsigned RegNo) const override { 7627 if (RegNo == 0) return 4; 7628 if (RegNo == 1) return 5; 7629 return -1; 7630 } 7631 7632 bool isCLZForZeroUndef() const override { return false; } 7633 7634 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7635 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 7636 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7637 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7638 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 7639 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 7640 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 7641 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7642 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7643 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7644 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7645 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7646 {{"ra"}, "$31"}}; 7647 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 7648 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7649 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7650 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 7651 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 7652 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 7653 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7654 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7655 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7656 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7657 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7658 {{"ra"}, "$31"}}; 7659 if (ABI == "o32") 7660 return llvm::makeArrayRef(O32RegAliases); 7661 return llvm::makeArrayRef(NewABIRegAliases); 7662 } 7663 7664 bool hasInt128Type() const override { 7665 return ABI == "n32" || ABI == "n64"; 7666 } 7667 7668 bool validateTarget(DiagnosticsEngine &Diags) const override { 7669 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 7670 // this yet. It's better to fail here than on the backend assertion. 7671 if (processorSupportsGPR64() && ABI == "o32") { 7672 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7673 return false; 7674 } 7675 7676 // 64-bit ABI's require 64-bit CPU's. 7677 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 7678 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7679 return false; 7680 } 7681 7682 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 7683 // can't handle this yet. It's better to fail here than on the 7684 // backend assertion. 7685 if ((getTriple().getArch() == llvm::Triple::mips64 || 7686 getTriple().getArch() == llvm::Triple::mips64el) && 7687 ABI == "o32") { 7688 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7689 << ABI << getTriple().str(); 7690 return false; 7691 } 7692 7693 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 7694 // can't handle this yet. It's better to fail here than on the 7695 // backend assertion. 7696 if ((getTriple().getArch() == llvm::Triple::mips || 7697 getTriple().getArch() == llvm::Triple::mipsel) && 7698 (ABI == "n32" || ABI == "n64")) { 7699 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7700 << ABI << getTriple().str(); 7701 return false; 7702 } 7703 7704 return true; 7705 } 7706 }; 7707 7708 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 7709 #define BUILTIN(ID, TYPE, ATTRS) \ 7710 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7711 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7712 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7713 #include "clang/Basic/BuiltinsMips.def" 7714 }; 7715 7716 class PNaClTargetInfo : public TargetInfo { 7717 public: 7718 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7719 : TargetInfo(Triple) { 7720 BigEndian = false; 7721 this->LongAlign = 32; 7722 this->LongWidth = 32; 7723 this->PointerAlign = 32; 7724 this->PointerWidth = 32; 7725 this->IntMaxType = TargetInfo::SignedLongLong; 7726 this->Int64Type = TargetInfo::SignedLongLong; 7727 this->DoubleAlign = 64; 7728 this->LongDoubleWidth = 64; 7729 this->LongDoubleAlign = 64; 7730 this->SizeType = TargetInfo::UnsignedInt; 7731 this->PtrDiffType = TargetInfo::SignedInt; 7732 this->IntPtrType = TargetInfo::SignedInt; 7733 this->RegParmMax = 0; // Disallow regparm 7734 } 7735 7736 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7737 Builder.defineMacro("__le32__"); 7738 Builder.defineMacro("__pnacl__"); 7739 } 7740 void getTargetDefines(const LangOptions &Opts, 7741 MacroBuilder &Builder) const override { 7742 getArchDefines(Opts, Builder); 7743 } 7744 bool hasFeature(StringRef Feature) const override { 7745 return Feature == "pnacl"; 7746 } 7747 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7748 BuiltinVaListKind getBuiltinVaListKind() const override { 7749 return TargetInfo::PNaClABIBuiltinVaList; 7750 } 7751 ArrayRef<const char *> getGCCRegNames() const override; 7752 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7753 bool validateAsmConstraint(const char *&Name, 7754 TargetInfo::ConstraintInfo &Info) const override { 7755 return false; 7756 } 7757 7758 const char *getClobbers() const override { 7759 return ""; 7760 } 7761 }; 7762 7763 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7764 return None; 7765 } 7766 7767 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7768 return None; 7769 } 7770 7771 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7772 class NaClMips32TargetInfo : public MipsTargetInfo { 7773 public: 7774 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7775 : MipsTargetInfo(Triple, Opts) {} 7776 7777 BuiltinVaListKind getBuiltinVaListKind() const override { 7778 return TargetInfo::PNaClABIBuiltinVaList; 7779 } 7780 }; 7781 7782 class Le64TargetInfo : public TargetInfo { 7783 static const Builtin::Info BuiltinInfo[]; 7784 7785 public: 7786 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7787 : TargetInfo(Triple) { 7788 BigEndian = false; 7789 NoAsmVariants = true; 7790 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7791 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7792 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 7793 } 7794 7795 void getTargetDefines(const LangOptions &Opts, 7796 MacroBuilder &Builder) const override { 7797 DefineStd(Builder, "unix", Opts); 7798 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7799 Builder.defineMacro("__ELF__"); 7800 } 7801 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7802 return llvm::makeArrayRef(BuiltinInfo, 7803 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7804 } 7805 BuiltinVaListKind getBuiltinVaListKind() const override { 7806 return TargetInfo::PNaClABIBuiltinVaList; 7807 } 7808 const char *getClobbers() const override { return ""; } 7809 ArrayRef<const char *> getGCCRegNames() const override { 7810 return None; 7811 } 7812 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7813 return None; 7814 } 7815 bool validateAsmConstraint(const char *&Name, 7816 TargetInfo::ConstraintInfo &Info) const override { 7817 return false; 7818 } 7819 7820 bool hasProtectedVisibility() const override { return false; } 7821 }; 7822 7823 class WebAssemblyTargetInfo : public TargetInfo { 7824 static const Builtin::Info BuiltinInfo[]; 7825 7826 enum SIMDEnum { 7827 NoSIMD, 7828 SIMD128, 7829 } SIMDLevel; 7830 7831 public: 7832 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 7833 : TargetInfo(T), SIMDLevel(NoSIMD) { 7834 BigEndian = false; 7835 NoAsmVariants = true; 7836 SuitableAlign = 128; 7837 LargeArrayMinWidth = 128; 7838 LargeArrayAlign = 128; 7839 SimdDefaultAlign = 128; 7840 SigAtomicType = SignedLong; 7841 LongDoubleWidth = LongDoubleAlign = 128; 7842 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7843 } 7844 7845 protected: 7846 void getTargetDefines(const LangOptions &Opts, 7847 MacroBuilder &Builder) const override { 7848 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7849 if (SIMDLevel >= SIMD128) 7850 Builder.defineMacro("__wasm_simd128__"); 7851 } 7852 7853 private: 7854 bool 7855 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7856 StringRef CPU, 7857 const std::vector<std::string> &FeaturesVec) const override { 7858 if (CPU == "bleeding-edge") 7859 Features["simd128"] = true; 7860 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7861 } 7862 bool hasFeature(StringRef Feature) const final { 7863 return llvm::StringSwitch<bool>(Feature) 7864 .Case("simd128", SIMDLevel >= SIMD128) 7865 .Default(false); 7866 } 7867 bool handleTargetFeatures(std::vector<std::string> &Features, 7868 DiagnosticsEngine &Diags) final { 7869 for (const auto &Feature : Features) { 7870 if (Feature == "+simd128") { 7871 SIMDLevel = std::max(SIMDLevel, SIMD128); 7872 continue; 7873 } 7874 if (Feature == "-simd128") { 7875 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7876 continue; 7877 } 7878 7879 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7880 << "-target-feature"; 7881 return false; 7882 } 7883 return true; 7884 } 7885 bool setCPU(const std::string &Name) final { 7886 return llvm::StringSwitch<bool>(Name) 7887 .Case("mvp", true) 7888 .Case("bleeding-edge", true) 7889 .Case("generic", true) 7890 .Default(false); 7891 } 7892 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7893 return llvm::makeArrayRef(BuiltinInfo, 7894 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7895 } 7896 BuiltinVaListKind getBuiltinVaListKind() const final { 7897 return VoidPtrBuiltinVaList; 7898 } 7899 ArrayRef<const char *> getGCCRegNames() const final { 7900 return None; 7901 } 7902 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7903 return None; 7904 } 7905 bool 7906 validateAsmConstraint(const char *&Name, 7907 TargetInfo::ConstraintInfo &Info) const final { 7908 return false; 7909 } 7910 const char *getClobbers() const final { return ""; } 7911 bool isCLZForZeroUndef() const final { return false; } 7912 bool hasInt128Type() const final { return true; } 7913 IntType getIntTypeByWidth(unsigned BitWidth, 7914 bool IsSigned) const final { 7915 // WebAssembly prefers long long for explicitly 64-bit integers. 7916 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7917 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7918 } 7919 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7920 bool IsSigned) const final { 7921 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7922 return BitWidth == 64 7923 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7924 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7925 } 7926 }; 7927 7928 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7929 #define BUILTIN(ID, TYPE, ATTRS) \ 7930 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7931 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7932 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7933 #include "clang/Basic/BuiltinsWebAssembly.def" 7934 }; 7935 7936 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7937 public: 7938 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 7939 const TargetOptions &Opts) 7940 : WebAssemblyTargetInfo(T, Opts) { 7941 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7942 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 7943 } 7944 7945 protected: 7946 void getTargetDefines(const LangOptions &Opts, 7947 MacroBuilder &Builder) const override { 7948 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7949 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7950 } 7951 }; 7952 7953 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7954 public: 7955 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 7956 const TargetOptions &Opts) 7957 : WebAssemblyTargetInfo(T, Opts) { 7958 LongAlign = LongWidth = 64; 7959 PointerAlign = PointerWidth = 64; 7960 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7961 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7962 } 7963 7964 protected: 7965 void getTargetDefines(const LangOptions &Opts, 7966 MacroBuilder &Builder) const override { 7967 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7968 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7969 } 7970 }; 7971 7972 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7973 #define BUILTIN(ID, TYPE, ATTRS) \ 7974 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7975 #include "clang/Basic/BuiltinsLe64.def" 7976 }; 7977 7978 static const unsigned SPIRAddrSpaceMap[] = { 7979 1, // opencl_global 7980 3, // opencl_local 7981 2, // opencl_constant 7982 4, // opencl_generic 7983 0, // cuda_device 7984 0, // cuda_constant 7985 0 // cuda_shared 7986 }; 7987 class SPIRTargetInfo : public TargetInfo { 7988 public: 7989 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7990 : TargetInfo(Triple) { 7991 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7992 "SPIR target must use unknown OS"); 7993 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7994 "SPIR target must use unknown environment type"); 7995 BigEndian = false; 7996 TLSSupported = false; 7997 LongWidth = LongAlign = 64; 7998 AddrSpaceMap = &SPIRAddrSpaceMap; 7999 UseAddrSpaceMapMangling = true; 8000 // Define available target features 8001 // These must be defined in sorted order! 8002 NoAsmVariants = true; 8003 } 8004 void getTargetDefines(const LangOptions &Opts, 8005 MacroBuilder &Builder) const override { 8006 DefineStd(Builder, "SPIR", Opts); 8007 } 8008 bool hasFeature(StringRef Feature) const override { 8009 return Feature == "spir"; 8010 } 8011 8012 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8013 const char *getClobbers() const override { return ""; } 8014 ArrayRef<const char *> getGCCRegNames() const override { return None; } 8015 bool validateAsmConstraint(const char *&Name, 8016 TargetInfo::ConstraintInfo &info) const override { 8017 return true; 8018 } 8019 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8020 return None; 8021 } 8022 BuiltinVaListKind getBuiltinVaListKind() const override { 8023 return TargetInfo::VoidPtrBuiltinVaList; 8024 } 8025 8026 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 8027 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 8028 : CCCR_Warning; 8029 } 8030 8031 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8032 return CC_SpirFunction; 8033 } 8034 8035 void setSupportedOpenCLOpts() override { 8036 // Assume all OpenCL extensions and optional core features are supported 8037 // for SPIR since it is a generic target. 8038 getSupportedOpenCLOpts().setAll(); 8039 } 8040 }; 8041 8042 class SPIR32TargetInfo : public SPIRTargetInfo { 8043 public: 8044 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8045 : SPIRTargetInfo(Triple, Opts) { 8046 PointerWidth = PointerAlign = 32; 8047 SizeType = TargetInfo::UnsignedInt; 8048 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8049 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8050 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8051 } 8052 void getTargetDefines(const LangOptions &Opts, 8053 MacroBuilder &Builder) const override { 8054 DefineStd(Builder, "SPIR32", Opts); 8055 } 8056 }; 8057 8058 class SPIR64TargetInfo : public SPIRTargetInfo { 8059 public: 8060 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8061 : SPIRTargetInfo(Triple, Opts) { 8062 PointerWidth = PointerAlign = 64; 8063 SizeType = TargetInfo::UnsignedLong; 8064 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8065 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8066 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8067 } 8068 void getTargetDefines(const LangOptions &Opts, 8069 MacroBuilder &Builder) const override { 8070 DefineStd(Builder, "SPIR64", Opts); 8071 } 8072 }; 8073 8074 class XCoreTargetInfo : public TargetInfo { 8075 static const Builtin::Info BuiltinInfo[]; 8076 public: 8077 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8078 : TargetInfo(Triple) { 8079 BigEndian = false; 8080 NoAsmVariants = true; 8081 LongLongAlign = 32; 8082 SuitableAlign = 32; 8083 DoubleAlign = LongDoubleAlign = 32; 8084 SizeType = UnsignedInt; 8085 PtrDiffType = SignedInt; 8086 IntPtrType = SignedInt; 8087 WCharType = UnsignedChar; 8088 WIntType = UnsignedInt; 8089 UseZeroLengthBitfieldAlignment = true; 8090 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8091 "-f64:32-a:0:32-n32"); 8092 } 8093 void getTargetDefines(const LangOptions &Opts, 8094 MacroBuilder &Builder) const override { 8095 Builder.defineMacro("__XS1B__"); 8096 } 8097 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8098 return llvm::makeArrayRef(BuiltinInfo, 8099 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8100 } 8101 BuiltinVaListKind getBuiltinVaListKind() const override { 8102 return TargetInfo::VoidPtrBuiltinVaList; 8103 } 8104 const char *getClobbers() const override { 8105 return ""; 8106 } 8107 ArrayRef<const char *> getGCCRegNames() const override { 8108 static const char * const GCCRegNames[] = { 8109 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8110 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8111 }; 8112 return llvm::makeArrayRef(GCCRegNames); 8113 } 8114 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8115 return None; 8116 } 8117 bool validateAsmConstraint(const char *&Name, 8118 TargetInfo::ConstraintInfo &Info) const override { 8119 return false; 8120 } 8121 int getEHDataRegisterNumber(unsigned RegNo) const override { 8122 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8123 return (RegNo < 2)? RegNo : -1; 8124 } 8125 bool allowsLargerPreferedTypeAlignment() const override { 8126 return false; 8127 } 8128 }; 8129 8130 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8131 #define BUILTIN(ID, TYPE, ATTRS) \ 8132 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8133 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8134 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8135 #include "clang/Basic/BuiltinsXCore.def" 8136 }; 8137 8138 // x86_32 Android target 8139 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8140 public: 8141 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8142 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8143 SuitableAlign = 32; 8144 LongDoubleWidth = 64; 8145 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 8146 } 8147 }; 8148 8149 // x86_64 Android target 8150 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8151 public: 8152 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8153 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8154 LongDoubleFormat = &llvm::APFloat::IEEEquad; 8155 } 8156 8157 bool useFloat128ManglingForLongDouble() const override { 8158 return true; 8159 } 8160 }; 8161 8162 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8163 class RenderScript32TargetInfo : public ARMleTargetInfo { 8164 public: 8165 RenderScript32TargetInfo(const llvm::Triple &Triple, 8166 const TargetOptions &Opts) 8167 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8168 Triple.getOSName(), 8169 Triple.getEnvironmentName()), 8170 Opts) { 8171 IsRenderScriptTarget = true; 8172 LongWidth = LongAlign = 64; 8173 } 8174 void getTargetDefines(const LangOptions &Opts, 8175 MacroBuilder &Builder) const override { 8176 Builder.defineMacro("__RENDERSCRIPT__"); 8177 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8178 } 8179 }; 8180 8181 // 64-bit RenderScript is aarch64 8182 class RenderScript64TargetInfo : public AArch64leTargetInfo { 8183 public: 8184 RenderScript64TargetInfo(const llvm::Triple &Triple, 8185 const TargetOptions &Opts) 8186 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 8187 Triple.getOSName(), 8188 Triple.getEnvironmentName()), 8189 Opts) { 8190 IsRenderScriptTarget = true; 8191 } 8192 8193 void getTargetDefines(const LangOptions &Opts, 8194 MacroBuilder &Builder) const override { 8195 Builder.defineMacro("__RENDERSCRIPT__"); 8196 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 8197 } 8198 }; 8199 8200 } // end anonymous namespace 8201 8202 //===----------------------------------------------------------------------===// 8203 // Driver code 8204 //===----------------------------------------------------------------------===// 8205 8206 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 8207 const TargetOptions &Opts) { 8208 llvm::Triple::OSType os = Triple.getOS(); 8209 8210 switch (Triple.getArch()) { 8211 default: 8212 return nullptr; 8213 8214 case llvm::Triple::xcore: 8215 return new XCoreTargetInfo(Triple, Opts); 8216 8217 case llvm::Triple::hexagon: 8218 return new HexagonTargetInfo(Triple, Opts); 8219 8220 case llvm::Triple::lanai: 8221 return new LanaiTargetInfo(Triple, Opts); 8222 8223 case llvm::Triple::aarch64: 8224 if (Triple.isOSDarwin()) 8225 return new DarwinAArch64TargetInfo(Triple, Opts); 8226 8227 switch (os) { 8228 case llvm::Triple::CloudABI: 8229 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 8230 case llvm::Triple::FreeBSD: 8231 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8232 case llvm::Triple::Linux: 8233 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8234 case llvm::Triple::NetBSD: 8235 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8236 default: 8237 return new AArch64leTargetInfo(Triple, Opts); 8238 } 8239 8240 case llvm::Triple::aarch64_be: 8241 switch (os) { 8242 case llvm::Triple::FreeBSD: 8243 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8244 case llvm::Triple::Linux: 8245 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8246 case llvm::Triple::NetBSD: 8247 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8248 default: 8249 return new AArch64beTargetInfo(Triple, Opts); 8250 } 8251 8252 case llvm::Triple::arm: 8253 case llvm::Triple::thumb: 8254 if (Triple.isOSBinFormatMachO()) 8255 return new DarwinARMTargetInfo(Triple, Opts); 8256 8257 switch (os) { 8258 case llvm::Triple::Linux: 8259 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 8260 case llvm::Triple::FreeBSD: 8261 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8262 case llvm::Triple::NetBSD: 8263 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8264 case llvm::Triple::OpenBSD: 8265 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8266 case llvm::Triple::Bitrig: 8267 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 8268 case llvm::Triple::RTEMS: 8269 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 8270 case llvm::Triple::NaCl: 8271 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 8272 case llvm::Triple::Win32: 8273 switch (Triple.getEnvironment()) { 8274 case llvm::Triple::Cygnus: 8275 return new CygwinARMTargetInfo(Triple, Opts); 8276 case llvm::Triple::GNU: 8277 return new MinGWARMTargetInfo(Triple, Opts); 8278 case llvm::Triple::Itanium: 8279 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 8280 case llvm::Triple::MSVC: 8281 default: // Assume MSVC for unknown environments 8282 return new MicrosoftARMleTargetInfo(Triple, Opts); 8283 } 8284 default: 8285 return new ARMleTargetInfo(Triple, Opts); 8286 } 8287 8288 case llvm::Triple::armeb: 8289 case llvm::Triple::thumbeb: 8290 if (Triple.isOSDarwin()) 8291 return new DarwinARMTargetInfo(Triple, Opts); 8292 8293 switch (os) { 8294 case llvm::Triple::Linux: 8295 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8296 case llvm::Triple::FreeBSD: 8297 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8298 case llvm::Triple::NetBSD: 8299 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8300 case llvm::Triple::OpenBSD: 8301 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8302 case llvm::Triple::Bitrig: 8303 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8304 case llvm::Triple::RTEMS: 8305 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8306 case llvm::Triple::NaCl: 8307 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8308 default: 8309 return new ARMbeTargetInfo(Triple, Opts); 8310 } 8311 8312 case llvm::Triple::bpfeb: 8313 case llvm::Triple::bpfel: 8314 return new BPFTargetInfo(Triple, Opts); 8315 8316 case llvm::Triple::msp430: 8317 return new MSP430TargetInfo(Triple, Opts); 8318 8319 case llvm::Triple::mips: 8320 switch (os) { 8321 case llvm::Triple::Linux: 8322 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8323 case llvm::Triple::RTEMS: 8324 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8325 case llvm::Triple::FreeBSD: 8326 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8327 case llvm::Triple::NetBSD: 8328 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8329 default: 8330 return new MipsTargetInfo(Triple, Opts); 8331 } 8332 8333 case llvm::Triple::mipsel: 8334 switch (os) { 8335 case llvm::Triple::Linux: 8336 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8337 case llvm::Triple::RTEMS: 8338 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8339 case llvm::Triple::FreeBSD: 8340 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8341 case llvm::Triple::NetBSD: 8342 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8343 case llvm::Triple::NaCl: 8344 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 8345 default: 8346 return new MipsTargetInfo(Triple, Opts); 8347 } 8348 8349 case llvm::Triple::mips64: 8350 switch (os) { 8351 case llvm::Triple::Linux: 8352 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8353 case llvm::Triple::RTEMS: 8354 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8355 case llvm::Triple::FreeBSD: 8356 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8357 case llvm::Triple::NetBSD: 8358 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8359 case llvm::Triple::OpenBSD: 8360 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8361 default: 8362 return new MipsTargetInfo(Triple, Opts); 8363 } 8364 8365 case llvm::Triple::mips64el: 8366 switch (os) { 8367 case llvm::Triple::Linux: 8368 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8369 case llvm::Triple::RTEMS: 8370 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8371 case llvm::Triple::FreeBSD: 8372 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8373 case llvm::Triple::NetBSD: 8374 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8375 case llvm::Triple::OpenBSD: 8376 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8377 default: 8378 return new MipsTargetInfo(Triple, Opts); 8379 } 8380 8381 case llvm::Triple::le32: 8382 switch (os) { 8383 case llvm::Triple::NaCl: 8384 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 8385 default: 8386 return nullptr; 8387 } 8388 8389 case llvm::Triple::le64: 8390 return new Le64TargetInfo(Triple, Opts); 8391 8392 case llvm::Triple::ppc: 8393 if (Triple.isOSDarwin()) 8394 return new DarwinPPC32TargetInfo(Triple, Opts); 8395 switch (os) { 8396 case llvm::Triple::Linux: 8397 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 8398 case llvm::Triple::FreeBSD: 8399 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8400 case llvm::Triple::NetBSD: 8401 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8402 case llvm::Triple::OpenBSD: 8403 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8404 case llvm::Triple::RTEMS: 8405 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 8406 default: 8407 return new PPC32TargetInfo(Triple, Opts); 8408 } 8409 8410 case llvm::Triple::ppc64: 8411 if (Triple.isOSDarwin()) 8412 return new DarwinPPC64TargetInfo(Triple, Opts); 8413 switch (os) { 8414 case llvm::Triple::Linux: 8415 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8416 case llvm::Triple::Lv2: 8417 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 8418 case llvm::Triple::FreeBSD: 8419 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8420 case llvm::Triple::NetBSD: 8421 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8422 default: 8423 return new PPC64TargetInfo(Triple, Opts); 8424 } 8425 8426 case llvm::Triple::ppc64le: 8427 switch (os) { 8428 case llvm::Triple::Linux: 8429 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8430 case llvm::Triple::NetBSD: 8431 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8432 default: 8433 return new PPC64TargetInfo(Triple, Opts); 8434 } 8435 8436 case llvm::Triple::nvptx: 8437 return new NVPTX32TargetInfo(Triple, Opts); 8438 case llvm::Triple::nvptx64: 8439 return new NVPTX64TargetInfo(Triple, Opts); 8440 8441 case llvm::Triple::amdgcn: 8442 case llvm::Triple::r600: 8443 return new AMDGPUTargetInfo(Triple, Opts); 8444 8445 case llvm::Triple::sparc: 8446 switch (os) { 8447 case llvm::Triple::Linux: 8448 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8449 case llvm::Triple::Solaris: 8450 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8451 case llvm::Triple::NetBSD: 8452 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8453 case llvm::Triple::OpenBSD: 8454 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8455 case llvm::Triple::RTEMS: 8456 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8457 default: 8458 return new SparcV8TargetInfo(Triple, Opts); 8459 } 8460 8461 // The 'sparcel' architecture copies all the above cases except for Solaris. 8462 case llvm::Triple::sparcel: 8463 switch (os) { 8464 case llvm::Triple::Linux: 8465 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8466 case llvm::Triple::NetBSD: 8467 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8468 case llvm::Triple::OpenBSD: 8469 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8470 case llvm::Triple::RTEMS: 8471 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8472 default: 8473 return new SparcV8elTargetInfo(Triple, Opts); 8474 } 8475 8476 case llvm::Triple::sparcv9: 8477 switch (os) { 8478 case llvm::Triple::Linux: 8479 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8480 case llvm::Triple::Solaris: 8481 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8482 case llvm::Triple::NetBSD: 8483 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8484 case llvm::Triple::OpenBSD: 8485 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8486 case llvm::Triple::FreeBSD: 8487 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8488 default: 8489 return new SparcV9TargetInfo(Triple, Opts); 8490 } 8491 8492 case llvm::Triple::systemz: 8493 switch (os) { 8494 case llvm::Triple::Linux: 8495 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 8496 default: 8497 return new SystemZTargetInfo(Triple, Opts); 8498 } 8499 8500 case llvm::Triple::tce: 8501 return new TCETargetInfo(Triple, Opts); 8502 8503 case llvm::Triple::x86: 8504 if (Triple.isOSDarwin()) 8505 return new DarwinI386TargetInfo(Triple, Opts); 8506 8507 switch (os) { 8508 case llvm::Triple::CloudABI: 8509 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 8510 case llvm::Triple::Linux: { 8511 switch (Triple.getEnvironment()) { 8512 default: 8513 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 8514 case llvm::Triple::Android: 8515 return new AndroidX86_32TargetInfo(Triple, Opts); 8516 } 8517 } 8518 case llvm::Triple::DragonFly: 8519 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8520 case llvm::Triple::NetBSD: 8521 return new NetBSDI386TargetInfo(Triple, Opts); 8522 case llvm::Triple::OpenBSD: 8523 return new OpenBSDI386TargetInfo(Triple, Opts); 8524 case llvm::Triple::Bitrig: 8525 return new BitrigI386TargetInfo(Triple, Opts); 8526 case llvm::Triple::FreeBSD: 8527 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8528 case llvm::Triple::KFreeBSD: 8529 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8530 case llvm::Triple::Minix: 8531 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 8532 case llvm::Triple::Solaris: 8533 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 8534 case llvm::Triple::Win32: { 8535 switch (Triple.getEnvironment()) { 8536 case llvm::Triple::Cygnus: 8537 return new CygwinX86_32TargetInfo(Triple, Opts); 8538 case llvm::Triple::GNU: 8539 return new MinGWX86_32TargetInfo(Triple, Opts); 8540 case llvm::Triple::Itanium: 8541 case llvm::Triple::MSVC: 8542 default: // Assume MSVC for unknown environments 8543 return new MicrosoftX86_32TargetInfo(Triple, Opts); 8544 } 8545 } 8546 case llvm::Triple::Haiku: 8547 return new HaikuX86_32TargetInfo(Triple, Opts); 8548 case llvm::Triple::RTEMS: 8549 return new RTEMSX86_32TargetInfo(Triple, Opts); 8550 case llvm::Triple::NaCl: 8551 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 8552 case llvm::Triple::ELFIAMCU: 8553 return new MCUX86_32TargetInfo(Triple, Opts); 8554 default: 8555 return new X86_32TargetInfo(Triple, Opts); 8556 } 8557 8558 case llvm::Triple::x86_64: 8559 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 8560 return new DarwinX86_64TargetInfo(Triple, Opts); 8561 8562 switch (os) { 8563 case llvm::Triple::CloudABI: 8564 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 8565 case llvm::Triple::Linux: { 8566 switch (Triple.getEnvironment()) { 8567 default: 8568 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 8569 case llvm::Triple::Android: 8570 return new AndroidX86_64TargetInfo(Triple, Opts); 8571 } 8572 } 8573 case llvm::Triple::DragonFly: 8574 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8575 case llvm::Triple::NetBSD: 8576 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8577 case llvm::Triple::OpenBSD: 8578 return new OpenBSDX86_64TargetInfo(Triple, Opts); 8579 case llvm::Triple::Bitrig: 8580 return new BitrigX86_64TargetInfo(Triple, Opts); 8581 case llvm::Triple::FreeBSD: 8582 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8583 case llvm::Triple::KFreeBSD: 8584 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8585 case llvm::Triple::Solaris: 8586 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 8587 case llvm::Triple::Win32: { 8588 switch (Triple.getEnvironment()) { 8589 case llvm::Triple::Cygnus: 8590 return new CygwinX86_64TargetInfo(Triple, Opts); 8591 case llvm::Triple::GNU: 8592 return new MinGWX86_64TargetInfo(Triple, Opts); 8593 case llvm::Triple::MSVC: 8594 default: // Assume MSVC for unknown environments 8595 return new MicrosoftX86_64TargetInfo(Triple, Opts); 8596 } 8597 } 8598 case llvm::Triple::Haiku: 8599 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 8600 case llvm::Triple::NaCl: 8601 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 8602 case llvm::Triple::PS4: 8603 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 8604 default: 8605 return new X86_64TargetInfo(Triple, Opts); 8606 } 8607 8608 case llvm::Triple::spir: { 8609 if (Triple.getOS() != llvm::Triple::UnknownOS || 8610 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8611 return nullptr; 8612 return new SPIR32TargetInfo(Triple, Opts); 8613 } 8614 case llvm::Triple::spir64: { 8615 if (Triple.getOS() != llvm::Triple::UnknownOS || 8616 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8617 return nullptr; 8618 return new SPIR64TargetInfo(Triple, Opts); 8619 } 8620 case llvm::Triple::wasm32: 8621 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8622 return nullptr; 8623 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 8624 case llvm::Triple::wasm64: 8625 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8626 return nullptr; 8627 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 8628 8629 case llvm::Triple::renderscript32: 8630 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 8631 case llvm::Triple::renderscript64: 8632 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 8633 } 8634 } 8635 8636 /// CreateTargetInfo - Return the target info object for the specified target 8637 /// options. 8638 TargetInfo * 8639 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8640 const std::shared_ptr<TargetOptions> &Opts) { 8641 llvm::Triple Triple(Opts->Triple); 8642 8643 // Construct the target 8644 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 8645 if (!Target) { 8646 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8647 return nullptr; 8648 } 8649 Target->TargetOpts = Opts; 8650 8651 // Set the target CPU if specified. 8652 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8653 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8654 return nullptr; 8655 } 8656 8657 // Set the target ABI if specified. 8658 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8659 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8660 return nullptr; 8661 } 8662 8663 // Set the fp math unit. 8664 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8665 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8666 return nullptr; 8667 } 8668 8669 // Compute the default target features, we need the target to handle this 8670 // because features may have dependencies on one another. 8671 llvm::StringMap<bool> Features; 8672 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8673 Opts->FeaturesAsWritten)) 8674 return nullptr; 8675 8676 // Add the features to the compile options. 8677 Opts->Features.clear(); 8678 for (const auto &F : Features) 8679 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8680 8681 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8682 return nullptr; 8683 8684 Target->setSupportedOpenCLOpts(); 8685 8686 if (!Target->validateTarget(Diags)) 8687 return nullptr; 8688 8689 return Target.release(); 8690 } 8691