1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/TargetParser.h" 31 #include <algorithm> 32 #include <memory> 33 using namespace clang; 34 35 //===----------------------------------------------------------------------===// 36 // Common code shared among targets. 37 //===----------------------------------------------------------------------===// 38 39 /// DefineStd - Define a macro name and standard variants. For example if 40 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 41 /// when in GNU mode. 42 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 43 const LangOptions &Opts) { 44 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 45 46 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 47 // in the user's namespace. 48 if (Opts.GNUMode) 49 Builder.defineMacro(MacroName); 50 51 // Define __unix. 52 Builder.defineMacro("__" + MacroName); 53 54 // Define __unix__. 55 Builder.defineMacro("__" + MacroName + "__"); 56 } 57 58 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 59 bool Tuning = true) { 60 Builder.defineMacro("__" + CPUName); 61 Builder.defineMacro("__" + CPUName + "__"); 62 if (Tuning) 63 Builder.defineMacro("__tune_" + CPUName + "__"); 64 } 65 66 //===----------------------------------------------------------------------===// 67 // Defines specific to certain operating systems. 68 //===----------------------------------------------------------------------===// 69 70 namespace { 71 template<typename TgtInfo> 72 class OSTargetInfo : public TgtInfo { 73 protected: 74 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 75 MacroBuilder &Builder) const=0; 76 public: 77 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 78 void getTargetDefines(const LangOptions &Opts, 79 MacroBuilder &Builder) const override { 80 TgtInfo::getTargetDefines(Opts, Builder); 81 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 82 } 83 84 }; 85 } // end anonymous namespace 86 87 88 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 89 const llvm::Triple &Triple, 90 StringRef &PlatformName, 91 VersionTuple &PlatformMinVersion) { 92 Builder.defineMacro("__APPLE_CC__", "6000"); 93 Builder.defineMacro("__APPLE__"); 94 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 95 // AddressSanitizer doesn't play well with source fortification, which is on 96 // by default on Darwin. 97 if (Opts.Sanitize.has(SanitizerKind::Address)) 98 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 99 100 if (!Opts.ObjCAutoRefCount) { 101 // __weak is always defined, for use in blocks and with objc pointers. 102 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 103 104 // Darwin defines __strong even in C mode (just to nothing). 105 if (Opts.getGC() != LangOptions::NonGC) 106 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 107 else 108 Builder.defineMacro("__strong", ""); 109 110 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 111 // allow this in C, since one might have block pointers in structs that 112 // are used in pure C code and in Objective-C ARC. 113 Builder.defineMacro("__unsafe_unretained", ""); 114 } 115 116 if (Opts.Static) 117 Builder.defineMacro("__STATIC__"); 118 else 119 Builder.defineMacro("__DYNAMIC__"); 120 121 if (Opts.POSIXThreads) 122 Builder.defineMacro("_REENTRANT"); 123 124 // Get the platform type and version number from the triple. 125 unsigned Maj, Min, Rev; 126 if (Triple.isMacOSX()) { 127 Triple.getMacOSXVersion(Maj, Min, Rev); 128 PlatformName = "macosx"; 129 } else { 130 Triple.getOSVersion(Maj, Min, Rev); 131 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 132 } 133 134 // If -target arch-pc-win32-macho option specified, we're 135 // generating code for Win32 ABI. No need to emit 136 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 137 if (PlatformName == "win32") { 138 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 139 return; 140 } 141 142 // Set the appropriate OS version define. 143 if (Triple.isiOS()) { 144 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 145 char Str[6]; 146 Str[0] = '0' + Maj; 147 Str[1] = '0' + (Min / 10); 148 Str[2] = '0' + (Min % 10); 149 Str[3] = '0' + (Rev / 10); 150 Str[4] = '0' + (Rev % 10); 151 Str[5] = '\0'; 152 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 153 Str); 154 } else if (Triple.isMacOSX()) { 155 // Note that the Driver allows versions which aren't representable in the 156 // define (because we only get a single digit for the minor and micro 157 // revision numbers). So, we limit them to the maximum representable 158 // version. 159 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 160 char Str[7]; 161 if (Maj < 10 || (Maj == 10 && Min < 10)) { 162 Str[0] = '0' + (Maj / 10); 163 Str[1] = '0' + (Maj % 10); 164 Str[2] = '0' + std::min(Min, 9U); 165 Str[3] = '0' + std::min(Rev, 9U); 166 Str[4] = '\0'; 167 } else { 168 // Handle versions > 10.9. 169 Str[0] = '0' + (Maj / 10); 170 Str[1] = '0' + (Maj % 10); 171 Str[2] = '0' + (Min / 10); 172 Str[3] = '0' + (Min % 10); 173 Str[4] = '0' + (Rev / 10); 174 Str[5] = '0' + (Rev % 10); 175 Str[6] = '\0'; 176 } 177 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 178 } 179 180 // Tell users about the kernel if there is one. 181 if (Triple.isOSDarwin()) 182 Builder.defineMacro("__MACH__"); 183 184 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 185 } 186 187 namespace { 188 // CloudABI Target 189 template <typename Target> 190 class CloudABITargetInfo : public OSTargetInfo<Target> { 191 protected: 192 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 193 MacroBuilder &Builder) const override { 194 Builder.defineMacro("__CloudABI__"); 195 Builder.defineMacro("__ELF__"); 196 197 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 198 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 199 Builder.defineMacro("__STDC_UTF_16__"); 200 Builder.defineMacro("__STDC_UTF_32__"); 201 } 202 203 public: 204 CloudABITargetInfo(const llvm::Triple &Triple) 205 : OSTargetInfo<Target>(Triple) { 206 this->UserLabelPrefix = ""; 207 } 208 }; 209 210 template<typename Target> 211 class DarwinTargetInfo : public OSTargetInfo<Target> { 212 protected: 213 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 214 MacroBuilder &Builder) const override { 215 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 216 this->PlatformMinVersion); 217 } 218 219 public: 220 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 221 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 222 this->MCountName = "\01mcount"; 223 } 224 225 std::string isValidSectionSpecifier(StringRef SR) const override { 226 // Let MCSectionMachO validate this. 227 StringRef Segment, Section; 228 unsigned TAA, StubSize; 229 bool HasTAA; 230 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 231 TAA, HasTAA, StubSize); 232 } 233 234 const char *getStaticInitSectionSpecifier() const override { 235 // FIXME: We should return 0 when building kexts. 236 return "__TEXT,__StaticInit,regular,pure_instructions"; 237 } 238 239 /// Darwin does not support protected visibility. Darwin's "default" 240 /// is very similar to ELF's "protected"; Darwin requires a "weak" 241 /// attribute on declarations that can be dynamically replaced. 242 bool hasProtectedVisibility() const override { 243 return false; 244 } 245 }; 246 247 248 // DragonFlyBSD Target 249 template<typename Target> 250 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 251 protected: 252 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 253 MacroBuilder &Builder) const override { 254 // DragonFly defines; list based off of gcc output 255 Builder.defineMacro("__DragonFly__"); 256 Builder.defineMacro("__DragonFly_cc_version", "100001"); 257 Builder.defineMacro("__ELF__"); 258 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 259 Builder.defineMacro("__tune_i386__"); 260 DefineStd(Builder, "unix", Opts); 261 } 262 public: 263 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 264 : OSTargetInfo<Target>(Triple) { 265 this->UserLabelPrefix = ""; 266 267 switch (Triple.getArch()) { 268 default: 269 case llvm::Triple::x86: 270 case llvm::Triple::x86_64: 271 this->MCountName = ".mcount"; 272 break; 273 } 274 } 275 }; 276 277 // FreeBSD Target 278 template<typename Target> 279 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 280 protected: 281 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 282 MacroBuilder &Builder) const override { 283 // FreeBSD defines; list based off of gcc output 284 285 unsigned Release = Triple.getOSMajorVersion(); 286 if (Release == 0U) 287 Release = 8; 288 289 Builder.defineMacro("__FreeBSD__", Twine(Release)); 290 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 291 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 292 DefineStd(Builder, "unix", Opts); 293 Builder.defineMacro("__ELF__"); 294 295 // On FreeBSD, wchar_t contains the number of the code point as 296 // used by the character set of the locale. These character sets are 297 // not necessarily a superset of ASCII. 298 // 299 // FIXME: This is wrong; the macro refers to the numerical values 300 // of wchar_t *literals*, which are not locale-dependent. However, 301 // FreeBSD systems apparently depend on us getting this wrong, and 302 // setting this to 1 is conforming even if all the basic source 303 // character literals have the same encoding as char and wchar_t. 304 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 305 } 306 public: 307 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 308 this->UserLabelPrefix = ""; 309 310 switch (Triple.getArch()) { 311 default: 312 case llvm::Triple::x86: 313 case llvm::Triple::x86_64: 314 this->MCountName = ".mcount"; 315 break; 316 case llvm::Triple::mips: 317 case llvm::Triple::mipsel: 318 case llvm::Triple::ppc: 319 case llvm::Triple::ppc64: 320 case llvm::Triple::ppc64le: 321 this->MCountName = "_mcount"; 322 break; 323 case llvm::Triple::arm: 324 this->MCountName = "__mcount"; 325 break; 326 } 327 } 328 }; 329 330 // GNU/kFreeBSD Target 331 template<typename Target> 332 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 333 protected: 334 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 335 MacroBuilder &Builder) const override { 336 // GNU/kFreeBSD defines; list based off of gcc output 337 338 DefineStd(Builder, "unix", Opts); 339 Builder.defineMacro("__FreeBSD_kernel__"); 340 Builder.defineMacro("__GLIBC__"); 341 Builder.defineMacro("__ELF__"); 342 if (Opts.POSIXThreads) 343 Builder.defineMacro("_REENTRANT"); 344 if (Opts.CPlusPlus) 345 Builder.defineMacro("_GNU_SOURCE"); 346 } 347 public: 348 KFreeBSDTargetInfo(const llvm::Triple &Triple) 349 : OSTargetInfo<Target>(Triple) { 350 this->UserLabelPrefix = ""; 351 } 352 }; 353 354 // Minix Target 355 template<typename Target> 356 class MinixTargetInfo : public OSTargetInfo<Target> { 357 protected: 358 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 359 MacroBuilder &Builder) const override { 360 // Minix defines 361 362 Builder.defineMacro("__minix", "3"); 363 Builder.defineMacro("_EM_WSIZE", "4"); 364 Builder.defineMacro("_EM_PSIZE", "4"); 365 Builder.defineMacro("_EM_SSIZE", "2"); 366 Builder.defineMacro("_EM_LSIZE", "4"); 367 Builder.defineMacro("_EM_FSIZE", "4"); 368 Builder.defineMacro("_EM_DSIZE", "8"); 369 Builder.defineMacro("__ELF__"); 370 DefineStd(Builder, "unix", Opts); 371 } 372 public: 373 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 374 this->UserLabelPrefix = ""; 375 } 376 }; 377 378 // Linux target 379 template<typename Target> 380 class LinuxTargetInfo : public OSTargetInfo<Target> { 381 protected: 382 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 383 MacroBuilder &Builder) const override { 384 // Linux defines; list based off of gcc output 385 DefineStd(Builder, "unix", Opts); 386 DefineStd(Builder, "linux", Opts); 387 Builder.defineMacro("__gnu_linux__"); 388 Builder.defineMacro("__ELF__"); 389 if (Triple.getEnvironment() == llvm::Triple::Android) { 390 Builder.defineMacro("__ANDROID__", "1"); 391 unsigned Maj, Min, Rev; 392 Triple.getOSVersion(Maj, Min, Rev); 393 this->PlatformName = "android"; 394 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 395 } 396 if (Opts.POSIXThreads) 397 Builder.defineMacro("_REENTRANT"); 398 if (Opts.CPlusPlus) 399 Builder.defineMacro("_GNU_SOURCE"); 400 } 401 public: 402 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 403 this->UserLabelPrefix = ""; 404 this->WIntType = TargetInfo::UnsignedInt; 405 406 switch (Triple.getArch()) { 407 default: 408 break; 409 case llvm::Triple::ppc: 410 case llvm::Triple::ppc64: 411 case llvm::Triple::ppc64le: 412 this->MCountName = "_mcount"; 413 break; 414 } 415 } 416 417 const char *getStaticInitSectionSpecifier() const override { 418 return ".text.startup"; 419 } 420 }; 421 422 // NetBSD Target 423 template<typename Target> 424 class NetBSDTargetInfo : public OSTargetInfo<Target> { 425 protected: 426 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 427 MacroBuilder &Builder) const override { 428 // NetBSD defines; list based off of gcc output 429 Builder.defineMacro("__NetBSD__"); 430 Builder.defineMacro("__unix__"); 431 Builder.defineMacro("__ELF__"); 432 if (Opts.POSIXThreads) 433 Builder.defineMacro("_POSIX_THREADS"); 434 435 switch (Triple.getArch()) { 436 default: 437 break; 438 case llvm::Triple::arm: 439 case llvm::Triple::armeb: 440 case llvm::Triple::thumb: 441 case llvm::Triple::thumbeb: 442 Builder.defineMacro("__ARM_DWARF_EH__"); 443 break; 444 } 445 } 446 public: 447 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 448 this->UserLabelPrefix = ""; 449 this->MCountName = "_mcount"; 450 } 451 }; 452 453 // OpenBSD Target 454 template<typename Target> 455 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 456 protected: 457 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 458 MacroBuilder &Builder) const override { 459 // OpenBSD defines; list based off of gcc output 460 461 Builder.defineMacro("__OpenBSD__"); 462 DefineStd(Builder, "unix", Opts); 463 Builder.defineMacro("__ELF__"); 464 if (Opts.POSIXThreads) 465 Builder.defineMacro("_REENTRANT"); 466 } 467 public: 468 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 469 this->UserLabelPrefix = ""; 470 this->TLSSupported = false; 471 472 switch (Triple.getArch()) { 473 default: 474 case llvm::Triple::x86: 475 case llvm::Triple::x86_64: 476 case llvm::Triple::arm: 477 case llvm::Triple::sparc: 478 this->MCountName = "__mcount"; 479 break; 480 case llvm::Triple::mips64: 481 case llvm::Triple::mips64el: 482 case llvm::Triple::ppc: 483 case llvm::Triple::sparcv9: 484 this->MCountName = "_mcount"; 485 break; 486 } 487 } 488 }; 489 490 // Bitrig Target 491 template<typename Target> 492 class BitrigTargetInfo : public OSTargetInfo<Target> { 493 protected: 494 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 495 MacroBuilder &Builder) const override { 496 // Bitrig defines; list based off of gcc output 497 498 Builder.defineMacro("__Bitrig__"); 499 DefineStd(Builder, "unix", Opts); 500 Builder.defineMacro("__ELF__"); 501 if (Opts.POSIXThreads) 502 Builder.defineMacro("_REENTRANT"); 503 504 switch (Triple.getArch()) { 505 default: 506 break; 507 case llvm::Triple::arm: 508 case llvm::Triple::armeb: 509 case llvm::Triple::thumb: 510 case llvm::Triple::thumbeb: 511 Builder.defineMacro("__ARM_DWARF_EH__"); 512 break; 513 } 514 } 515 public: 516 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 517 this->UserLabelPrefix = ""; 518 this->MCountName = "__mcount"; 519 } 520 }; 521 522 // PSP Target 523 template<typename Target> 524 class PSPTargetInfo : public OSTargetInfo<Target> { 525 protected: 526 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 527 MacroBuilder &Builder) const override { 528 // PSP defines; list based on the output of the pspdev gcc toolchain. 529 Builder.defineMacro("PSP"); 530 Builder.defineMacro("_PSP"); 531 Builder.defineMacro("__psp__"); 532 Builder.defineMacro("__ELF__"); 533 } 534 public: 535 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 536 this->UserLabelPrefix = ""; 537 } 538 }; 539 540 // PS3 PPU Target 541 template<typename Target> 542 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 543 protected: 544 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 545 MacroBuilder &Builder) const override { 546 // PS3 PPU defines. 547 Builder.defineMacro("__PPC__"); 548 Builder.defineMacro("__PPU__"); 549 Builder.defineMacro("__CELLOS_LV2__"); 550 Builder.defineMacro("__ELF__"); 551 Builder.defineMacro("__LP32__"); 552 Builder.defineMacro("_ARCH_PPC64"); 553 Builder.defineMacro("__powerpc64__"); 554 } 555 public: 556 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 557 this->UserLabelPrefix = ""; 558 this->LongWidth = this->LongAlign = 32; 559 this->PointerWidth = this->PointerAlign = 32; 560 this->IntMaxType = TargetInfo::SignedLongLong; 561 this->Int64Type = TargetInfo::SignedLongLong; 562 this->SizeType = TargetInfo::UnsignedInt; 563 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64"; 564 } 565 }; 566 567 template <typename Target> 568 class PS4OSTargetInfo : public OSTargetInfo<Target> { 569 protected: 570 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 571 MacroBuilder &Builder) const override { 572 Builder.defineMacro("__FreeBSD__", "9"); 573 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 574 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 575 DefineStd(Builder, "unix", Opts); 576 Builder.defineMacro("__ELF__"); 577 Builder.defineMacro("__PS4__"); 578 } 579 public: 580 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 581 this->WCharType = this->UnsignedShort; 582 583 this->UserLabelPrefix = ""; 584 585 switch (Triple.getArch()) { 586 default: 587 case llvm::Triple::x86_64: 588 this->MCountName = ".mcount"; 589 break; 590 } 591 } 592 }; 593 594 // Solaris target 595 template<typename Target> 596 class SolarisTargetInfo : public OSTargetInfo<Target> { 597 protected: 598 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 599 MacroBuilder &Builder) const override { 600 DefineStd(Builder, "sun", Opts); 601 DefineStd(Builder, "unix", Opts); 602 Builder.defineMacro("__ELF__"); 603 Builder.defineMacro("__svr4__"); 604 Builder.defineMacro("__SVR4"); 605 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 606 // newer, but to 500 for everything else. feature_test.h has a check to 607 // ensure that you are not using C99 with an old version of X/Open or C89 608 // with a new version. 609 if (Opts.C99) 610 Builder.defineMacro("_XOPEN_SOURCE", "600"); 611 else 612 Builder.defineMacro("_XOPEN_SOURCE", "500"); 613 if (Opts.CPlusPlus) 614 Builder.defineMacro("__C99FEATURES__"); 615 Builder.defineMacro("_LARGEFILE_SOURCE"); 616 Builder.defineMacro("_LARGEFILE64_SOURCE"); 617 Builder.defineMacro("__EXTENSIONS__"); 618 Builder.defineMacro("_REENTRANT"); 619 } 620 public: 621 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 622 this->UserLabelPrefix = ""; 623 this->WCharType = this->SignedInt; 624 // FIXME: WIntType should be SignedLong 625 } 626 }; 627 628 // Windows target 629 template<typename Target> 630 class WindowsTargetInfo : public OSTargetInfo<Target> { 631 protected: 632 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 633 MacroBuilder &Builder) const override { 634 Builder.defineMacro("_WIN32"); 635 } 636 void getVisualStudioDefines(const LangOptions &Opts, 637 MacroBuilder &Builder) const { 638 if (Opts.CPlusPlus) { 639 if (Opts.RTTIData) 640 Builder.defineMacro("_CPPRTTI"); 641 642 if (Opts.CXXExceptions) 643 Builder.defineMacro("_CPPUNWIND"); 644 } 645 646 if (!Opts.CharIsSigned) 647 Builder.defineMacro("_CHAR_UNSIGNED"); 648 649 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 650 // but it works for now. 651 if (Opts.POSIXThreads) 652 Builder.defineMacro("_MT"); 653 654 if (Opts.MSCompatibilityVersion) { 655 Builder.defineMacro("_MSC_VER", 656 Twine(Opts.MSCompatibilityVersion / 100000)); 657 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 658 // FIXME We cannot encode the revision information into 32-bits 659 Builder.defineMacro("_MSC_BUILD", Twine(1)); 660 661 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 662 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 663 } 664 665 if (Opts.MicrosoftExt) { 666 Builder.defineMacro("_MSC_EXTENSIONS"); 667 668 if (Opts.CPlusPlus11) { 669 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 670 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 671 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 672 } 673 } 674 675 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 676 } 677 678 public: 679 WindowsTargetInfo(const llvm::Triple &Triple) 680 : OSTargetInfo<Target>(Triple) {} 681 }; 682 683 template <typename Target> 684 class NaClTargetInfo : public OSTargetInfo<Target> { 685 protected: 686 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 687 MacroBuilder &Builder) const override { 688 if (Opts.POSIXThreads) 689 Builder.defineMacro("_REENTRANT"); 690 if (Opts.CPlusPlus) 691 Builder.defineMacro("_GNU_SOURCE"); 692 693 DefineStd(Builder, "unix", Opts); 694 Builder.defineMacro("__ELF__"); 695 Builder.defineMacro("__native_client__"); 696 } 697 698 public: 699 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 700 this->UserLabelPrefix = ""; 701 this->LongAlign = 32; 702 this->LongWidth = 32; 703 this->PointerAlign = 32; 704 this->PointerWidth = 32; 705 this->IntMaxType = TargetInfo::SignedLongLong; 706 this->Int64Type = TargetInfo::SignedLongLong; 707 this->DoubleAlign = 64; 708 this->LongDoubleWidth = 64; 709 this->LongDoubleAlign = 64; 710 this->LongLongWidth = 64; 711 this->LongLongAlign = 64; 712 this->SizeType = TargetInfo::UnsignedInt; 713 this->PtrDiffType = TargetInfo::SignedInt; 714 this->IntPtrType = TargetInfo::SignedInt; 715 // RegParmMax is inherited from the underlying architecture 716 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 717 if (Triple.getArch() == llvm::Triple::arm) { 718 // Handled in ARM's setABI(). 719 } else if (Triple.getArch() == llvm::Triple::x86) { 720 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 721 } else if (Triple.getArch() == llvm::Triple::x86_64) { 722 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 723 } else if (Triple.getArch() == llvm::Triple::mipsel) { 724 // Handled on mips' setDescriptionString. 725 } else { 726 assert(Triple.getArch() == llvm::Triple::le32); 727 this->DescriptionString = "e-p:32:32-i64:64"; 728 } 729 } 730 }; 731 732 //===----------------------------------------------------------------------===// 733 // Specific target implementations. 734 //===----------------------------------------------------------------------===// 735 736 // PPC abstract base class 737 class PPCTargetInfo : public TargetInfo { 738 static const Builtin::Info BuiltinInfo[]; 739 static const char * const GCCRegNames[]; 740 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 741 std::string CPU; 742 743 // Target cpu features. 744 bool HasVSX; 745 bool HasP8Vector; 746 bool HasP8Crypto; 747 bool HasDirectMove; 748 bool HasQPX; 749 bool HasHTM; 750 bool HasBPERMD; 751 bool HasExtDiv; 752 753 protected: 754 std::string ABI; 755 756 public: 757 PPCTargetInfo(const llvm::Triple &Triple) 758 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 759 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 760 HasBPERMD(false), HasExtDiv(false) { 761 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 762 LongDoubleWidth = LongDoubleAlign = 128; 763 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 764 } 765 766 /// \brief Flags for architecture specific defines. 767 typedef enum { 768 ArchDefineNone = 0, 769 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 770 ArchDefinePpcgr = 1 << 1, 771 ArchDefinePpcsq = 1 << 2, 772 ArchDefine440 = 1 << 3, 773 ArchDefine603 = 1 << 4, 774 ArchDefine604 = 1 << 5, 775 ArchDefinePwr4 = 1 << 6, 776 ArchDefinePwr5 = 1 << 7, 777 ArchDefinePwr5x = 1 << 8, 778 ArchDefinePwr6 = 1 << 9, 779 ArchDefinePwr6x = 1 << 10, 780 ArchDefinePwr7 = 1 << 11, 781 ArchDefinePwr8 = 1 << 12, 782 ArchDefineA2 = 1 << 13, 783 ArchDefineA2q = 1 << 14 784 } ArchDefineTypes; 785 786 // Note: GCC recognizes the following additional cpus: 787 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 788 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 789 // titan, rs64. 790 bool setCPU(const std::string &Name) override { 791 bool CPUKnown = llvm::StringSwitch<bool>(Name) 792 .Case("generic", true) 793 .Case("440", true) 794 .Case("450", true) 795 .Case("601", true) 796 .Case("602", true) 797 .Case("603", true) 798 .Case("603e", true) 799 .Case("603ev", true) 800 .Case("604", true) 801 .Case("604e", true) 802 .Case("620", true) 803 .Case("630", true) 804 .Case("g3", true) 805 .Case("7400", true) 806 .Case("g4", true) 807 .Case("7450", true) 808 .Case("g4+", true) 809 .Case("750", true) 810 .Case("970", true) 811 .Case("g5", true) 812 .Case("a2", true) 813 .Case("a2q", true) 814 .Case("e500mc", true) 815 .Case("e5500", true) 816 .Case("power3", true) 817 .Case("pwr3", true) 818 .Case("power4", true) 819 .Case("pwr4", true) 820 .Case("power5", true) 821 .Case("pwr5", true) 822 .Case("power5x", true) 823 .Case("pwr5x", true) 824 .Case("power6", true) 825 .Case("pwr6", true) 826 .Case("power6x", true) 827 .Case("pwr6x", true) 828 .Case("power7", true) 829 .Case("pwr7", true) 830 .Case("power8", true) 831 .Case("pwr8", true) 832 .Case("powerpc", true) 833 .Case("ppc", true) 834 .Case("powerpc64", true) 835 .Case("ppc64", true) 836 .Case("powerpc64le", true) 837 .Case("ppc64le", true) 838 .Default(false); 839 840 if (CPUKnown) 841 CPU = Name; 842 843 return CPUKnown; 844 } 845 846 847 StringRef getABI() const override { return ABI; } 848 849 void getTargetBuiltins(const Builtin::Info *&Records, 850 unsigned &NumRecords) const override { 851 Records = BuiltinInfo; 852 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 853 } 854 855 bool isCLZForZeroUndef() const override { return false; } 856 857 void getTargetDefines(const LangOptions &Opts, 858 MacroBuilder &Builder) const override; 859 860 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 861 862 bool handleTargetFeatures(std::vector<std::string> &Features, 863 DiagnosticsEngine &Diags) override; 864 bool hasFeature(StringRef Feature) const override; 865 866 void getGCCRegNames(const char * const *&Names, 867 unsigned &NumNames) const override; 868 void getGCCRegAliases(const GCCRegAlias *&Aliases, 869 unsigned &NumAliases) const override; 870 bool validateAsmConstraint(const char *&Name, 871 TargetInfo::ConstraintInfo &Info) const override { 872 switch (*Name) { 873 default: return false; 874 case 'O': // Zero 875 break; 876 case 'b': // Base register 877 case 'f': // Floating point register 878 Info.setAllowsRegister(); 879 break; 880 // FIXME: The following are added to allow parsing. 881 // I just took a guess at what the actions should be. 882 // Also, is more specific checking needed? I.e. specific registers? 883 case 'd': // Floating point register (containing 64-bit value) 884 case 'v': // Altivec vector register 885 Info.setAllowsRegister(); 886 break; 887 case 'w': 888 switch (Name[1]) { 889 case 'd':// VSX vector register to hold vector double data 890 case 'f':// VSX vector register to hold vector float data 891 case 's':// VSX vector register to hold scalar float data 892 case 'a':// Any VSX register 893 case 'c':// An individual CR bit 894 break; 895 default: 896 return false; 897 } 898 Info.setAllowsRegister(); 899 Name++; // Skip over 'w'. 900 break; 901 case 'h': // `MQ', `CTR', or `LINK' register 902 case 'q': // `MQ' register 903 case 'c': // `CTR' register 904 case 'l': // `LINK' register 905 case 'x': // `CR' register (condition register) number 0 906 case 'y': // `CR' register (condition register) 907 case 'z': // `XER[CA]' carry bit (part of the XER register) 908 Info.setAllowsRegister(); 909 break; 910 case 'I': // Signed 16-bit constant 911 case 'J': // Unsigned 16-bit constant shifted left 16 bits 912 // (use `L' instead for SImode constants) 913 case 'K': // Unsigned 16-bit constant 914 case 'L': // Signed 16-bit constant shifted left 16 bits 915 case 'M': // Constant larger than 31 916 case 'N': // Exact power of 2 917 case 'P': // Constant whose negation is a signed 16-bit constant 918 case 'G': // Floating point constant that can be loaded into a 919 // register with one instruction per word 920 case 'H': // Integer/Floating point constant that can be loaded 921 // into a register using three instructions 922 break; 923 case 'm': // Memory operand. Note that on PowerPC targets, m can 924 // include addresses that update the base register. It 925 // is therefore only safe to use `m' in an asm statement 926 // if that asm statement accesses the operand exactly once. 927 // The asm statement must also use `%U<opno>' as a 928 // placeholder for the "update" flag in the corresponding 929 // load or store instruction. For example: 930 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 931 // is correct but: 932 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 933 // is not. Use es rather than m if you don't want the base 934 // register to be updated. 935 case 'e': 936 if (Name[1] != 's') 937 return false; 938 // es: A "stable" memory operand; that is, one which does not 939 // include any automodification of the base register. Unlike 940 // `m', this constraint can be used in asm statements that 941 // might access the operand several times, or that might not 942 // access it at all. 943 Info.setAllowsMemory(); 944 Name++; // Skip over 'e'. 945 break; 946 case 'Q': // Memory operand that is an offset from a register (it is 947 // usually better to use `m' or `es' in asm statements) 948 case 'Z': // Memory operand that is an indexed or indirect from a 949 // register (it is usually better to use `m' or `es' in 950 // asm statements) 951 Info.setAllowsMemory(); 952 Info.setAllowsRegister(); 953 break; 954 case 'R': // AIX TOC entry 955 case 'a': // Address operand that is an indexed or indirect from a 956 // register (`p' is preferable for asm statements) 957 case 'S': // Constant suitable as a 64-bit mask operand 958 case 'T': // Constant suitable as a 32-bit mask operand 959 case 'U': // System V Release 4 small data area reference 960 case 't': // AND masks that can be performed by two rldic{l, r} 961 // instructions 962 case 'W': // Vector constant that does not require memory 963 case 'j': // Vector constant that is all zeros. 964 break; 965 // End FIXME. 966 } 967 return true; 968 } 969 std::string convertConstraint(const char *&Constraint) const override { 970 std::string R; 971 switch (*Constraint) { 972 case 'e': 973 case 'w': 974 // Two-character constraint; add "^" hint for later parsing. 975 R = std::string("^") + std::string(Constraint, 2); 976 Constraint++; 977 break; 978 default: 979 return TargetInfo::convertConstraint(Constraint); 980 } 981 return R; 982 } 983 const char *getClobbers() const override { 984 return ""; 985 } 986 int getEHDataRegisterNumber(unsigned RegNo) const override { 987 if (RegNo == 0) return 3; 988 if (RegNo == 1) return 4; 989 return -1; 990 } 991 992 bool hasSjLjLowering() const override { 993 return true; 994 } 995 }; 996 997 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 998 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 999 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1000 ALL_LANGUAGES }, 1001 #include "clang/Basic/BuiltinsPPC.def" 1002 }; 1003 1004 /// handleTargetFeatures - Perform initialization based on the user 1005 /// configured set of features. 1006 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1007 DiagnosticsEngine &Diags) { 1008 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 1009 // Ignore disabled features. 1010 if (Features[i][0] == '-') 1011 continue; 1012 1013 StringRef Feature = StringRef(Features[i]).substr(1); 1014 1015 if (Feature == "vsx") { 1016 HasVSX = true; 1017 continue; 1018 } 1019 1020 if (Feature == "bpermd") { 1021 HasBPERMD = true; 1022 continue; 1023 } 1024 1025 if (Feature == "extdiv") { 1026 HasExtDiv = true; 1027 continue; 1028 } 1029 1030 if (Feature == "power8-vector") { 1031 HasP8Vector = true; 1032 HasVSX = true; 1033 continue; 1034 } 1035 1036 if (Feature == "crypto") { 1037 HasP8Crypto = true; 1038 continue; 1039 } 1040 1041 if (Feature == "direct-move") { 1042 HasDirectMove = true; 1043 HasVSX = true; 1044 continue; 1045 } 1046 1047 if (Feature == "qpx") { 1048 HasQPX = true; 1049 continue; 1050 } 1051 1052 if (Feature == "htm") { 1053 HasHTM = true; 1054 continue; 1055 } 1056 1057 // TODO: Finish this list and add an assert that we've handled them 1058 // all. 1059 } 1060 1061 return true; 1062 } 1063 1064 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1065 /// #defines that are not tied to a specific subtarget. 1066 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1067 MacroBuilder &Builder) const { 1068 // Target identification. 1069 Builder.defineMacro("__ppc__"); 1070 Builder.defineMacro("__PPC__"); 1071 Builder.defineMacro("_ARCH_PPC"); 1072 Builder.defineMacro("__powerpc__"); 1073 Builder.defineMacro("__POWERPC__"); 1074 if (PointerWidth == 64) { 1075 Builder.defineMacro("_ARCH_PPC64"); 1076 Builder.defineMacro("__powerpc64__"); 1077 Builder.defineMacro("__ppc64__"); 1078 Builder.defineMacro("__PPC64__"); 1079 } 1080 1081 // Target properties. 1082 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1083 Builder.defineMacro("_LITTLE_ENDIAN"); 1084 } else { 1085 if (getTriple().getOS() != llvm::Triple::NetBSD && 1086 getTriple().getOS() != llvm::Triple::OpenBSD) 1087 Builder.defineMacro("_BIG_ENDIAN"); 1088 } 1089 1090 // ABI options. 1091 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1092 Builder.defineMacro("_CALL_ELF", "1"); 1093 if (ABI == "elfv2") 1094 Builder.defineMacro("_CALL_ELF", "2"); 1095 1096 // Subtarget options. 1097 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1098 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1099 1100 // FIXME: Should be controlled by command line option. 1101 if (LongDoubleWidth == 128) 1102 Builder.defineMacro("__LONG_DOUBLE_128__"); 1103 1104 if (Opts.AltiVec) { 1105 Builder.defineMacro("__VEC__", "10206"); 1106 Builder.defineMacro("__ALTIVEC__"); 1107 } 1108 1109 // CPU identification. 1110 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1111 .Case("440", ArchDefineName) 1112 .Case("450", ArchDefineName | ArchDefine440) 1113 .Case("601", ArchDefineName) 1114 .Case("602", ArchDefineName | ArchDefinePpcgr) 1115 .Case("603", ArchDefineName | ArchDefinePpcgr) 1116 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1117 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1118 .Case("604", ArchDefineName | ArchDefinePpcgr) 1119 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1120 .Case("620", ArchDefineName | ArchDefinePpcgr) 1121 .Case("630", ArchDefineName | ArchDefinePpcgr) 1122 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1123 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1124 .Case("750", ArchDefineName | ArchDefinePpcgr) 1125 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1126 | ArchDefinePpcsq) 1127 .Case("a2", ArchDefineA2) 1128 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1129 .Case("pwr3", ArchDefinePpcgr) 1130 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1131 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1132 | ArchDefinePpcsq) 1133 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1134 | ArchDefinePpcgr | ArchDefinePpcsq) 1135 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1136 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1137 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1138 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1139 | ArchDefinePpcsq) 1140 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1141 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1142 | ArchDefinePpcgr | ArchDefinePpcsq) 1143 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1144 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1145 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1146 .Case("power3", ArchDefinePpcgr) 1147 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1148 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1149 | ArchDefinePpcsq) 1150 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1151 | ArchDefinePpcgr | ArchDefinePpcsq) 1152 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1153 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1154 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1155 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1156 | ArchDefinePpcsq) 1157 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1158 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1159 | ArchDefinePpcgr | ArchDefinePpcsq) 1160 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1161 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1162 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1163 .Default(ArchDefineNone); 1164 1165 if (defs & ArchDefineName) 1166 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1167 if (defs & ArchDefinePpcgr) 1168 Builder.defineMacro("_ARCH_PPCGR"); 1169 if (defs & ArchDefinePpcsq) 1170 Builder.defineMacro("_ARCH_PPCSQ"); 1171 if (defs & ArchDefine440) 1172 Builder.defineMacro("_ARCH_440"); 1173 if (defs & ArchDefine603) 1174 Builder.defineMacro("_ARCH_603"); 1175 if (defs & ArchDefine604) 1176 Builder.defineMacro("_ARCH_604"); 1177 if (defs & ArchDefinePwr4) 1178 Builder.defineMacro("_ARCH_PWR4"); 1179 if (defs & ArchDefinePwr5) 1180 Builder.defineMacro("_ARCH_PWR5"); 1181 if (defs & ArchDefinePwr5x) 1182 Builder.defineMacro("_ARCH_PWR5X"); 1183 if (defs & ArchDefinePwr6) 1184 Builder.defineMacro("_ARCH_PWR6"); 1185 if (defs & ArchDefinePwr6x) 1186 Builder.defineMacro("_ARCH_PWR6X"); 1187 if (defs & ArchDefinePwr7) 1188 Builder.defineMacro("_ARCH_PWR7"); 1189 if (defs & ArchDefinePwr8) 1190 Builder.defineMacro("_ARCH_PWR8"); 1191 if (defs & ArchDefineA2) 1192 Builder.defineMacro("_ARCH_A2"); 1193 if (defs & ArchDefineA2q) { 1194 Builder.defineMacro("_ARCH_A2Q"); 1195 Builder.defineMacro("_ARCH_QP"); 1196 } 1197 1198 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1199 Builder.defineMacro("__bg__"); 1200 Builder.defineMacro("__THW_BLUEGENE__"); 1201 Builder.defineMacro("__bgq__"); 1202 Builder.defineMacro("__TOS_BGQ__"); 1203 } 1204 1205 if (HasVSX) 1206 Builder.defineMacro("__VSX__"); 1207 if (HasP8Vector) 1208 Builder.defineMacro("__POWER8_VECTOR__"); 1209 if (HasP8Crypto) 1210 Builder.defineMacro("__CRYPTO__"); 1211 if (HasHTM) 1212 Builder.defineMacro("__HTM__"); 1213 if (getTriple().getArch() == llvm::Triple::ppc64le || 1214 (defs & ArchDefinePwr8) || (CPU == "pwr8")) { 1215 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1216 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1217 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1218 if (PointerWidth == 64) 1219 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1220 } 1221 1222 // FIXME: The following are not yet generated here by Clang, but are 1223 // generated by GCC: 1224 // 1225 // _SOFT_FLOAT_ 1226 // __RECIP_PRECISION__ 1227 // __APPLE_ALTIVEC__ 1228 // __RECIP__ 1229 // __RECIPF__ 1230 // __RSQRTE__ 1231 // __RSQRTEF__ 1232 // _SOFT_DOUBLE_ 1233 // __NO_LWSYNC__ 1234 // __HAVE_BSWAP__ 1235 // __LONGDOUBLE128 1236 // __CMODEL_MEDIUM__ 1237 // __CMODEL_LARGE__ 1238 // _CALL_SYSV 1239 // _CALL_DARWIN 1240 // __NO_FPRS__ 1241 } 1242 1243 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1244 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1245 .Case("7400", true) 1246 .Case("g4", true) 1247 .Case("7450", true) 1248 .Case("g4+", true) 1249 .Case("970", true) 1250 .Case("g5", true) 1251 .Case("pwr6", true) 1252 .Case("pwr7", true) 1253 .Case("pwr8", true) 1254 .Case("ppc64", true) 1255 .Case("ppc64le", true) 1256 .Default(false); 1257 1258 Features["qpx"] = (CPU == "a2q"); 1259 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1260 .Case("ppc64le", true) 1261 .Case("pwr8", true) 1262 .Default(false); 1263 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1264 .Case("ppc64le", true) 1265 .Case("pwr8", true) 1266 .Default(false); 1267 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1268 .Case("ppc64le", true) 1269 .Case("pwr8", true) 1270 .Case("pwr7", true) 1271 .Default(false); 1272 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1273 .Case("ppc64le", true) 1274 .Case("pwr8", true) 1275 .Case("pwr7", true) 1276 .Default(false); 1277 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1278 .Case("ppc64le", true) 1279 .Case("pwr8", true) 1280 .Default(false); 1281 } 1282 1283 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1284 return llvm::StringSwitch<bool>(Feature) 1285 .Case("powerpc", true) 1286 .Case("vsx", HasVSX) 1287 .Case("power8-vector", HasP8Vector) 1288 .Case("crypto", HasP8Crypto) 1289 .Case("direct-move", HasDirectMove) 1290 .Case("qpx", HasQPX) 1291 .Case("htm", HasHTM) 1292 .Case("bpermd", HasBPERMD) 1293 .Case("extdiv", HasExtDiv) 1294 .Default(false); 1295 } 1296 1297 const char * const PPCTargetInfo::GCCRegNames[] = { 1298 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1299 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1300 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1301 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1302 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1303 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1304 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1305 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1306 "mq", "lr", "ctr", "ap", 1307 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1308 "xer", 1309 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1310 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1311 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1312 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1313 "vrsave", "vscr", 1314 "spe_acc", "spefscr", 1315 "sfp" 1316 }; 1317 1318 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1319 unsigned &NumNames) const { 1320 Names = GCCRegNames; 1321 NumNames = llvm::array_lengthof(GCCRegNames); 1322 } 1323 1324 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1325 // While some of these aliases do map to different registers 1326 // they still share the same register name. 1327 { { "0" }, "r0" }, 1328 { { "1"}, "r1" }, 1329 { { "2" }, "r2" }, 1330 { { "3" }, "r3" }, 1331 { { "4" }, "r4" }, 1332 { { "5" }, "r5" }, 1333 { { "6" }, "r6" }, 1334 { { "7" }, "r7" }, 1335 { { "8" }, "r8" }, 1336 { { "9" }, "r9" }, 1337 { { "10" }, "r10" }, 1338 { { "11" }, "r11" }, 1339 { { "12" }, "r12" }, 1340 { { "13" }, "r13" }, 1341 { { "14" }, "r14" }, 1342 { { "15" }, "r15" }, 1343 { { "16" }, "r16" }, 1344 { { "17" }, "r17" }, 1345 { { "18" }, "r18" }, 1346 { { "19" }, "r19" }, 1347 { { "20" }, "r20" }, 1348 { { "21" }, "r21" }, 1349 { { "22" }, "r22" }, 1350 { { "23" }, "r23" }, 1351 { { "24" }, "r24" }, 1352 { { "25" }, "r25" }, 1353 { { "26" }, "r26" }, 1354 { { "27" }, "r27" }, 1355 { { "28" }, "r28" }, 1356 { { "29" }, "r29" }, 1357 { { "30" }, "r30" }, 1358 { { "31" }, "r31" }, 1359 { { "fr0" }, "f0" }, 1360 { { "fr1" }, "f1" }, 1361 { { "fr2" }, "f2" }, 1362 { { "fr3" }, "f3" }, 1363 { { "fr4" }, "f4" }, 1364 { { "fr5" }, "f5" }, 1365 { { "fr6" }, "f6" }, 1366 { { "fr7" }, "f7" }, 1367 { { "fr8" }, "f8" }, 1368 { { "fr9" }, "f9" }, 1369 { { "fr10" }, "f10" }, 1370 { { "fr11" }, "f11" }, 1371 { { "fr12" }, "f12" }, 1372 { { "fr13" }, "f13" }, 1373 { { "fr14" }, "f14" }, 1374 { { "fr15" }, "f15" }, 1375 { { "fr16" }, "f16" }, 1376 { { "fr17" }, "f17" }, 1377 { { "fr18" }, "f18" }, 1378 { { "fr19" }, "f19" }, 1379 { { "fr20" }, "f20" }, 1380 { { "fr21" }, "f21" }, 1381 { { "fr22" }, "f22" }, 1382 { { "fr23" }, "f23" }, 1383 { { "fr24" }, "f24" }, 1384 { { "fr25" }, "f25" }, 1385 { { "fr26" }, "f26" }, 1386 { { "fr27" }, "f27" }, 1387 { { "fr28" }, "f28" }, 1388 { { "fr29" }, "f29" }, 1389 { { "fr30" }, "f30" }, 1390 { { "fr31" }, "f31" }, 1391 { { "cc" }, "cr0" }, 1392 }; 1393 1394 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1395 unsigned &NumAliases) const { 1396 Aliases = GCCRegAliases; 1397 NumAliases = llvm::array_lengthof(GCCRegAliases); 1398 } 1399 1400 class PPC32TargetInfo : public PPCTargetInfo { 1401 public: 1402 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1403 DescriptionString = "E-m:e-p:32:32-i64:64-n32"; 1404 1405 switch (getTriple().getOS()) { 1406 case llvm::Triple::Linux: 1407 case llvm::Triple::FreeBSD: 1408 case llvm::Triple::NetBSD: 1409 SizeType = UnsignedInt; 1410 PtrDiffType = SignedInt; 1411 IntPtrType = SignedInt; 1412 break; 1413 default: 1414 break; 1415 } 1416 1417 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1418 LongDoubleWidth = LongDoubleAlign = 64; 1419 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1420 } 1421 1422 // PPC32 supports atomics up to 4 bytes. 1423 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1424 } 1425 1426 BuiltinVaListKind getBuiltinVaListKind() const override { 1427 // This is the ELF definition, and is overridden by the Darwin sub-target 1428 return TargetInfo::PowerABIBuiltinVaList; 1429 } 1430 }; 1431 1432 // Note: ABI differences may eventually require us to have a separate 1433 // TargetInfo for little endian. 1434 class PPC64TargetInfo : public PPCTargetInfo { 1435 public: 1436 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1437 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1438 IntMaxType = SignedLong; 1439 Int64Type = SignedLong; 1440 1441 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1442 DescriptionString = "e-m:e-i64:64-n32:64"; 1443 ABI = "elfv2"; 1444 } else { 1445 DescriptionString = "E-m:e-i64:64-n32:64"; 1446 ABI = "elfv1"; 1447 } 1448 1449 switch (getTriple().getOS()) { 1450 case llvm::Triple::FreeBSD: 1451 LongDoubleWidth = LongDoubleAlign = 64; 1452 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1453 break; 1454 case llvm::Triple::NetBSD: 1455 IntMaxType = SignedLongLong; 1456 Int64Type = SignedLongLong; 1457 break; 1458 default: 1459 break; 1460 } 1461 1462 // PPC64 supports atomics up to 8 bytes. 1463 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1464 } 1465 BuiltinVaListKind getBuiltinVaListKind() const override { 1466 return TargetInfo::CharPtrBuiltinVaList; 1467 } 1468 // PPC64 Linux-specifc ABI options. 1469 bool setABI(const std::string &Name) override { 1470 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1471 ABI = Name; 1472 return true; 1473 } 1474 return false; 1475 } 1476 }; 1477 1478 class DarwinPPC32TargetInfo : 1479 public DarwinTargetInfo<PPC32TargetInfo> { 1480 public: 1481 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1482 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1483 HasAlignMac68kSupport = true; 1484 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1485 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1486 LongLongAlign = 32; 1487 SuitableAlign = 128; 1488 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; 1489 } 1490 BuiltinVaListKind getBuiltinVaListKind() const override { 1491 return TargetInfo::CharPtrBuiltinVaList; 1492 } 1493 }; 1494 1495 class DarwinPPC64TargetInfo : 1496 public DarwinTargetInfo<PPC64TargetInfo> { 1497 public: 1498 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1499 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1500 HasAlignMac68kSupport = true; 1501 SuitableAlign = 128; 1502 DescriptionString = "E-m:o-i64:64-n32:64"; 1503 } 1504 }; 1505 1506 static const unsigned NVPTXAddrSpaceMap[] = { 1507 1, // opencl_global 1508 3, // opencl_local 1509 4, // opencl_constant 1510 // FIXME: generic has to be added to the target 1511 0, // opencl_generic 1512 1, // cuda_device 1513 4, // cuda_constant 1514 3, // cuda_shared 1515 }; 1516 class NVPTXTargetInfo : public TargetInfo { 1517 static const char * const GCCRegNames[]; 1518 static const Builtin::Info BuiltinInfo[]; 1519 1520 // The GPU profiles supported by the NVPTX backend 1521 enum GPUKind { 1522 GK_NONE, 1523 GK_SM20, 1524 GK_SM21, 1525 GK_SM30, 1526 GK_SM35, 1527 GK_SM37, 1528 } GPU; 1529 1530 public: 1531 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1532 BigEndian = false; 1533 TLSSupported = false; 1534 LongWidth = LongAlign = 64; 1535 AddrSpaceMap = &NVPTXAddrSpaceMap; 1536 UseAddrSpaceMapMangling = true; 1537 // Define available target features 1538 // These must be defined in sorted order! 1539 NoAsmVariants = true; 1540 // Set the default GPU to sm20 1541 GPU = GK_SM20; 1542 } 1543 void getTargetDefines(const LangOptions &Opts, 1544 MacroBuilder &Builder) const override { 1545 Builder.defineMacro("__PTX__"); 1546 Builder.defineMacro("__NVPTX__"); 1547 if (Opts.CUDAIsDevice) { 1548 // Set __CUDA_ARCH__ for the GPU specified. 1549 std::string CUDAArchCode; 1550 switch (GPU) { 1551 case GK_SM20: 1552 CUDAArchCode = "200"; 1553 break; 1554 case GK_SM21: 1555 CUDAArchCode = "210"; 1556 break; 1557 case GK_SM30: 1558 CUDAArchCode = "300"; 1559 break; 1560 case GK_SM35: 1561 CUDAArchCode = "350"; 1562 break; 1563 case GK_SM37: 1564 CUDAArchCode = "370"; 1565 break; 1566 default: 1567 llvm_unreachable("Unhandled target CPU"); 1568 } 1569 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1570 } 1571 } 1572 void getTargetBuiltins(const Builtin::Info *&Records, 1573 unsigned &NumRecords) const override { 1574 Records = BuiltinInfo; 1575 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1576 } 1577 bool hasFeature(StringRef Feature) const override { 1578 return Feature == "ptx" || Feature == "nvptx"; 1579 } 1580 1581 void getGCCRegNames(const char * const *&Names, 1582 unsigned &NumNames) const override; 1583 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1584 unsigned &NumAliases) const override { 1585 // No aliases. 1586 Aliases = nullptr; 1587 NumAliases = 0; 1588 } 1589 bool 1590 validateAsmConstraint(const char *&Name, 1591 TargetInfo::ConstraintInfo &Info) const override { 1592 switch (*Name) { 1593 default: return false; 1594 case 'c': 1595 case 'h': 1596 case 'r': 1597 case 'l': 1598 case 'f': 1599 case 'd': 1600 Info.setAllowsRegister(); 1601 return true; 1602 } 1603 } 1604 const char *getClobbers() const override { 1605 // FIXME: Is this really right? 1606 return ""; 1607 } 1608 BuiltinVaListKind getBuiltinVaListKind() const override { 1609 // FIXME: implement 1610 return TargetInfo::CharPtrBuiltinVaList; 1611 } 1612 bool setCPU(const std::string &Name) override { 1613 GPU = llvm::StringSwitch<GPUKind>(Name) 1614 .Case("sm_20", GK_SM20) 1615 .Case("sm_21", GK_SM21) 1616 .Case("sm_30", GK_SM30) 1617 .Case("sm_35", GK_SM35) 1618 .Case("sm_37", GK_SM37) 1619 .Default(GK_NONE); 1620 1621 return GPU != GK_NONE; 1622 } 1623 }; 1624 1625 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1626 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1627 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1628 ALL_LANGUAGES }, 1629 #include "clang/Basic/BuiltinsNVPTX.def" 1630 }; 1631 1632 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1633 "r0" 1634 }; 1635 1636 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1637 unsigned &NumNames) const { 1638 Names = GCCRegNames; 1639 NumNames = llvm::array_lengthof(GCCRegNames); 1640 } 1641 1642 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1643 public: 1644 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1645 PointerWidth = PointerAlign = 32; 1646 SizeType = TargetInfo::UnsignedInt; 1647 PtrDiffType = TargetInfo::SignedInt; 1648 IntPtrType = TargetInfo::SignedInt; 1649 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1650 } 1651 }; 1652 1653 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1654 public: 1655 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1656 PointerWidth = PointerAlign = 64; 1657 SizeType = TargetInfo::UnsignedLong; 1658 PtrDiffType = TargetInfo::SignedLong; 1659 IntPtrType = TargetInfo::SignedLong; 1660 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1661 } 1662 }; 1663 1664 static const unsigned R600AddrSpaceMap[] = { 1665 1, // opencl_global 1666 3, // opencl_local 1667 2, // opencl_constant 1668 4, // opencl_generic 1669 1, // cuda_device 1670 2, // cuda_constant 1671 3 // cuda_shared 1672 }; 1673 1674 // If you edit the description strings, make sure you update 1675 // getPointerWidthV(). 1676 1677 static const char *DescriptionStringR600 = 1678 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1679 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1680 1681 static const char *DescriptionStringR600DoubleOps = 1682 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1683 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1684 1685 static const char *DescriptionStringSI = 1686 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1687 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1688 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1689 1690 class R600TargetInfo : public TargetInfo { 1691 static const Builtin::Info BuiltinInfo[]; 1692 static const char * const GCCRegNames[]; 1693 1694 /// \brief The GPU profiles supported by the R600 target. 1695 enum GPUKind { 1696 GK_NONE, 1697 GK_R600, 1698 GK_R600_DOUBLE_OPS, 1699 GK_R700, 1700 GK_R700_DOUBLE_OPS, 1701 GK_EVERGREEN, 1702 GK_EVERGREEN_DOUBLE_OPS, 1703 GK_NORTHERN_ISLANDS, 1704 GK_CAYMAN, 1705 GK_SOUTHERN_ISLANDS, 1706 GK_SEA_ISLANDS 1707 } GPU; 1708 1709 bool hasFP64:1; 1710 bool hasFMAF:1; 1711 bool hasLDEXPF:1; 1712 1713 public: 1714 R600TargetInfo(const llvm::Triple &Triple) 1715 : TargetInfo(Triple) { 1716 1717 if (Triple.getArch() == llvm::Triple::amdgcn) { 1718 DescriptionString = DescriptionStringSI; 1719 GPU = GK_SOUTHERN_ISLANDS; 1720 hasFP64 = true; 1721 hasFMAF = true; 1722 hasLDEXPF = true; 1723 } else { 1724 DescriptionString = DescriptionStringR600; 1725 GPU = GK_R600; 1726 hasFP64 = false; 1727 hasFMAF = false; 1728 hasLDEXPF = false; 1729 } 1730 AddrSpaceMap = &R600AddrSpaceMap; 1731 UseAddrSpaceMapMangling = true; 1732 } 1733 1734 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1735 if (GPU <= GK_CAYMAN) 1736 return 32; 1737 1738 switch(AddrSpace) { 1739 default: 1740 return 64; 1741 case 0: 1742 case 3: 1743 case 5: 1744 return 32; 1745 } 1746 } 1747 1748 const char * getClobbers() const override { 1749 return ""; 1750 } 1751 1752 void getGCCRegNames(const char * const *&Names, 1753 unsigned &NumNames) const override; 1754 1755 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1756 unsigned &NumAliases) const override { 1757 Aliases = nullptr; 1758 NumAliases = 0; 1759 } 1760 1761 bool validateAsmConstraint(const char *&Name, 1762 TargetInfo::ConstraintInfo &info) const override { 1763 return true; 1764 } 1765 1766 void getTargetBuiltins(const Builtin::Info *&Records, 1767 unsigned &NumRecords) const override { 1768 Records = BuiltinInfo; 1769 NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin; 1770 } 1771 1772 void getTargetDefines(const LangOptions &Opts, 1773 MacroBuilder &Builder) const override { 1774 Builder.defineMacro("__R600__"); 1775 if (hasFMAF) 1776 Builder.defineMacro("__HAS_FMAF__"); 1777 if (hasLDEXPF) 1778 Builder.defineMacro("__HAS_LDEXPF__"); 1779 if (hasFP64 && Opts.OpenCL) { 1780 Builder.defineMacro("cl_khr_fp64"); 1781 } 1782 } 1783 1784 BuiltinVaListKind getBuiltinVaListKind() const override { 1785 return TargetInfo::CharPtrBuiltinVaList; 1786 } 1787 1788 bool setCPU(const std::string &Name) override { 1789 GPU = llvm::StringSwitch<GPUKind>(Name) 1790 .Case("r600" , GK_R600) 1791 .Case("rv610", GK_R600) 1792 .Case("rv620", GK_R600) 1793 .Case("rv630", GK_R600) 1794 .Case("rv635", GK_R600) 1795 .Case("rs780", GK_R600) 1796 .Case("rs880", GK_R600) 1797 .Case("rv670", GK_R600_DOUBLE_OPS) 1798 .Case("rv710", GK_R700) 1799 .Case("rv730", GK_R700) 1800 .Case("rv740", GK_R700_DOUBLE_OPS) 1801 .Case("rv770", GK_R700_DOUBLE_OPS) 1802 .Case("palm", GK_EVERGREEN) 1803 .Case("cedar", GK_EVERGREEN) 1804 .Case("sumo", GK_EVERGREEN) 1805 .Case("sumo2", GK_EVERGREEN) 1806 .Case("redwood", GK_EVERGREEN) 1807 .Case("juniper", GK_EVERGREEN) 1808 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1809 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1810 .Case("barts", GK_NORTHERN_ISLANDS) 1811 .Case("turks", GK_NORTHERN_ISLANDS) 1812 .Case("caicos", GK_NORTHERN_ISLANDS) 1813 .Case("cayman", GK_CAYMAN) 1814 .Case("aruba", GK_CAYMAN) 1815 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1816 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1817 .Case("verde", GK_SOUTHERN_ISLANDS) 1818 .Case("oland", GK_SOUTHERN_ISLANDS) 1819 .Case("hainan", GK_SOUTHERN_ISLANDS) 1820 .Case("bonaire", GK_SEA_ISLANDS) 1821 .Case("kabini", GK_SEA_ISLANDS) 1822 .Case("kaveri", GK_SEA_ISLANDS) 1823 .Case("hawaii", GK_SEA_ISLANDS) 1824 .Case("mullins", GK_SEA_ISLANDS) 1825 .Default(GK_NONE); 1826 1827 if (GPU == GK_NONE) { 1828 return false; 1829 } 1830 1831 // Set the correct data layout 1832 switch (GPU) { 1833 case GK_NONE: 1834 case GK_R600: 1835 case GK_R700: 1836 case GK_EVERGREEN: 1837 case GK_NORTHERN_ISLANDS: 1838 DescriptionString = DescriptionStringR600; 1839 hasFP64 = false; 1840 hasFMAF = false; 1841 hasLDEXPF = false; 1842 break; 1843 case GK_R600_DOUBLE_OPS: 1844 case GK_R700_DOUBLE_OPS: 1845 case GK_EVERGREEN_DOUBLE_OPS: 1846 case GK_CAYMAN: 1847 DescriptionString = DescriptionStringR600DoubleOps; 1848 hasFP64 = true; 1849 hasFMAF = true; 1850 hasLDEXPF = false; 1851 break; 1852 case GK_SOUTHERN_ISLANDS: 1853 case GK_SEA_ISLANDS: 1854 DescriptionString = DescriptionStringSI; 1855 hasFP64 = true; 1856 hasFMAF = true; 1857 hasLDEXPF = true; 1858 break; 1859 } 1860 1861 return true; 1862 } 1863 }; 1864 1865 const Builtin::Info R600TargetInfo::BuiltinInfo[] = { 1866 #define BUILTIN(ID, TYPE, ATTRS) \ 1867 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1868 #include "clang/Basic/BuiltinsR600.def" 1869 }; 1870 const char * const R600TargetInfo::GCCRegNames[] = { 1871 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1872 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1873 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1874 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1875 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1876 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1877 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1878 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1879 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1880 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1881 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1882 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1883 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1884 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1885 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1886 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1887 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1888 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1889 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1890 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 1891 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 1892 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 1893 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 1894 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 1895 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 1896 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 1897 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 1898 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 1899 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 1900 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 1901 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 1902 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 1903 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 1904 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 1905 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 1906 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 1907 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 1908 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 1909 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 1910 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 1911 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 1912 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 1913 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 1914 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 1915 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 1916 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 1917 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 1918 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127" 1919 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi", 1920 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi" 1921 }; 1922 1923 void R600TargetInfo::getGCCRegNames(const char * const *&Names, 1924 unsigned &NumNames) const { 1925 Names = GCCRegNames; 1926 NumNames = llvm::array_lengthof(GCCRegNames); 1927 } 1928 1929 // Namespace for x86 abstract base class 1930 const Builtin::Info BuiltinInfo[] = { 1931 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1932 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1933 ALL_LANGUAGES }, 1934 #include "clang/Basic/BuiltinsX86.def" 1935 }; 1936 1937 static const char* const GCCRegNames[] = { 1938 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1939 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1940 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1941 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1942 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1943 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1944 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1945 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1946 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1947 }; 1948 1949 const TargetInfo::AddlRegName AddlRegNames[] = { 1950 { { "al", "ah", "eax", "rax" }, 0 }, 1951 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1952 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1953 { { "dl", "dh", "edx", "rdx" }, 1 }, 1954 { { "esi", "rsi" }, 4 }, 1955 { { "edi", "rdi" }, 5 }, 1956 { { "esp", "rsp" }, 7 }, 1957 { { "ebp", "rbp" }, 6 }, 1958 }; 1959 1960 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1961 // most of the implementation can be shared. 1962 class X86TargetInfo : public TargetInfo { 1963 enum X86SSEEnum { 1964 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1965 } SSELevel; 1966 enum MMX3DNowEnum { 1967 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1968 } MMX3DNowLevel; 1969 enum XOPEnum { 1970 NoXOP, 1971 SSE4A, 1972 FMA4, 1973 XOP 1974 } XOPLevel; 1975 1976 bool HasAES; 1977 bool HasPCLMUL; 1978 bool HasLZCNT; 1979 bool HasRDRND; 1980 bool HasFSGSBASE; 1981 bool HasBMI; 1982 bool HasBMI2; 1983 bool HasPOPCNT; 1984 bool HasRTM; 1985 bool HasPRFCHW; 1986 bool HasRDSEED; 1987 bool HasADX; 1988 bool HasTBM; 1989 bool HasFMA; 1990 bool HasF16C; 1991 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW, 1992 HasAVX512VL; 1993 bool HasSHA; 1994 bool HasCX16; 1995 1996 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1997 /// 1998 /// Each enumeration represents a particular CPU supported by Clang. These 1999 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2000 enum CPUKind { 2001 CK_Generic, 2002 2003 /// \name i386 2004 /// i386-generation processors. 2005 //@{ 2006 CK_i386, 2007 //@} 2008 2009 /// \name i486 2010 /// i486-generation processors. 2011 //@{ 2012 CK_i486, 2013 CK_WinChipC6, 2014 CK_WinChip2, 2015 CK_C3, 2016 //@} 2017 2018 /// \name i586 2019 /// i586-generation processors, P5 microarchitecture based. 2020 //@{ 2021 CK_i586, 2022 CK_Pentium, 2023 CK_PentiumMMX, 2024 //@} 2025 2026 /// \name i686 2027 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2028 //@{ 2029 CK_i686, 2030 CK_PentiumPro, 2031 CK_Pentium2, 2032 CK_Pentium3, 2033 CK_Pentium3M, 2034 CK_PentiumM, 2035 CK_C3_2, 2036 2037 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2038 /// Clang however has some logic to suport this. 2039 // FIXME: Warn, deprecate, and potentially remove this. 2040 CK_Yonah, 2041 //@} 2042 2043 /// \name Netburst 2044 /// Netburst microarchitecture based processors. 2045 //@{ 2046 CK_Pentium4, 2047 CK_Pentium4M, 2048 CK_Prescott, 2049 CK_Nocona, 2050 //@} 2051 2052 /// \name Core 2053 /// Core microarchitecture based processors. 2054 //@{ 2055 CK_Core2, 2056 2057 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2058 /// codename which GCC no longer accepts as an option to -march, but Clang 2059 /// has some logic for recognizing it. 2060 // FIXME: Warn, deprecate, and potentially remove this. 2061 CK_Penryn, 2062 //@} 2063 2064 /// \name Atom 2065 /// Atom processors 2066 //@{ 2067 CK_Bonnell, 2068 CK_Silvermont, 2069 //@} 2070 2071 /// \name Nehalem 2072 /// Nehalem microarchitecture based processors. 2073 CK_Nehalem, 2074 2075 /// \name Westmere 2076 /// Westmere microarchitecture based processors. 2077 CK_Westmere, 2078 2079 /// \name Sandy Bridge 2080 /// Sandy Bridge microarchitecture based processors. 2081 CK_SandyBridge, 2082 2083 /// \name Ivy Bridge 2084 /// Ivy Bridge microarchitecture based processors. 2085 CK_IvyBridge, 2086 2087 /// \name Haswell 2088 /// Haswell microarchitecture based processors. 2089 CK_Haswell, 2090 2091 /// \name Broadwell 2092 /// Broadwell microarchitecture based processors. 2093 CK_Broadwell, 2094 2095 /// \name Skylake 2096 /// Skylake microarchitecture based processors. 2097 CK_Skylake, 2098 2099 /// \name Knights Landing 2100 /// Knights Landing processor. 2101 CK_KNL, 2102 2103 /// \name K6 2104 /// K6 architecture processors. 2105 //@{ 2106 CK_K6, 2107 CK_K6_2, 2108 CK_K6_3, 2109 //@} 2110 2111 /// \name K7 2112 /// K7 architecture processors. 2113 //@{ 2114 CK_Athlon, 2115 CK_AthlonThunderbird, 2116 CK_Athlon4, 2117 CK_AthlonXP, 2118 CK_AthlonMP, 2119 //@} 2120 2121 /// \name K8 2122 /// K8 architecture processors. 2123 //@{ 2124 CK_Athlon64, 2125 CK_Athlon64SSE3, 2126 CK_AthlonFX, 2127 CK_K8, 2128 CK_K8SSE3, 2129 CK_Opteron, 2130 CK_OpteronSSE3, 2131 CK_AMDFAM10, 2132 //@} 2133 2134 /// \name Bobcat 2135 /// Bobcat architecture processors. 2136 //@{ 2137 CK_BTVER1, 2138 CK_BTVER2, 2139 //@} 2140 2141 /// \name Bulldozer 2142 /// Bulldozer architecture processors. 2143 //@{ 2144 CK_BDVER1, 2145 CK_BDVER2, 2146 CK_BDVER3, 2147 CK_BDVER4, 2148 //@} 2149 2150 /// This specification is deprecated and will be removed in the future. 2151 /// Users should prefer \see CK_K8. 2152 // FIXME: Warn on this when the CPU is set to it. 2153 //@{ 2154 CK_x86_64, 2155 //@} 2156 2157 /// \name Geode 2158 /// Geode processors. 2159 //@{ 2160 CK_Geode 2161 //@} 2162 } CPU; 2163 2164 enum FPMathKind { 2165 FP_Default, 2166 FP_SSE, 2167 FP_387 2168 } FPMath; 2169 2170 public: 2171 X86TargetInfo(const llvm::Triple &Triple) 2172 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 2173 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 2174 HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false), 2175 HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false), 2176 HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false), 2177 HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false), 2178 HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false), 2179 HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) { 2180 BigEndian = false; 2181 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2182 } 2183 unsigned getFloatEvalMethod() const override { 2184 // X87 evaluates with 80 bits "long double" precision. 2185 return SSELevel == NoSSE ? 2 : 0; 2186 } 2187 void getTargetBuiltins(const Builtin::Info *&Records, 2188 unsigned &NumRecords) const override { 2189 Records = BuiltinInfo; 2190 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 2191 } 2192 void getGCCRegNames(const char * const *&Names, 2193 unsigned &NumNames) const override { 2194 Names = GCCRegNames; 2195 NumNames = llvm::array_lengthof(GCCRegNames); 2196 } 2197 void getGCCRegAliases(const GCCRegAlias *&Aliases, 2198 unsigned &NumAliases) const override { 2199 Aliases = nullptr; 2200 NumAliases = 0; 2201 } 2202 void getGCCAddlRegNames(const AddlRegName *&Names, 2203 unsigned &NumNames) const override { 2204 Names = AddlRegNames; 2205 NumNames = llvm::array_lengthof(AddlRegNames); 2206 } 2207 bool validateAsmConstraint(const char *&Name, 2208 TargetInfo::ConstraintInfo &info) const override; 2209 2210 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2211 2212 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2213 2214 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2215 2216 std::string convertConstraint(const char *&Constraint) const override; 2217 const char *getClobbers() const override { 2218 return "~{dirflag},~{fpsr},~{flags}"; 2219 } 2220 void getTargetDefines(const LangOptions &Opts, 2221 MacroBuilder &Builder) const override; 2222 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2223 bool Enabled); 2224 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2225 bool Enabled); 2226 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2227 bool Enabled); 2228 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2229 StringRef Name, bool Enabled) const override { 2230 setFeatureEnabledImpl(Features, Name, Enabled); 2231 } 2232 // This exists purely to cut down on the number of virtual calls in 2233 // getDefaultFeatures which calls this repeatedly. 2234 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2235 StringRef Name, bool Enabled); 2236 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 2237 bool hasFeature(StringRef Feature) const override; 2238 bool handleTargetFeatures(std::vector<std::string> &Features, 2239 DiagnosticsEngine &Diags) override; 2240 StringRef getABI() const override { 2241 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2242 return "avx"; 2243 else if (getTriple().getArch() == llvm::Triple::x86 && 2244 MMX3DNowLevel == NoMMX3DNow) 2245 return "no-mmx"; 2246 return ""; 2247 } 2248 bool setCPU(const std::string &Name) override { 2249 CPU = llvm::StringSwitch<CPUKind>(Name) 2250 .Case("i386", CK_i386) 2251 .Case("i486", CK_i486) 2252 .Case("winchip-c6", CK_WinChipC6) 2253 .Case("winchip2", CK_WinChip2) 2254 .Case("c3", CK_C3) 2255 .Case("i586", CK_i586) 2256 .Case("pentium", CK_Pentium) 2257 .Case("pentium-mmx", CK_PentiumMMX) 2258 .Case("i686", CK_i686) 2259 .Case("pentiumpro", CK_PentiumPro) 2260 .Case("pentium2", CK_Pentium2) 2261 .Case("pentium3", CK_Pentium3) 2262 .Case("pentium3m", CK_Pentium3M) 2263 .Case("pentium-m", CK_PentiumM) 2264 .Case("c3-2", CK_C3_2) 2265 .Case("yonah", CK_Yonah) 2266 .Case("pentium4", CK_Pentium4) 2267 .Case("pentium4m", CK_Pentium4M) 2268 .Case("prescott", CK_Prescott) 2269 .Case("nocona", CK_Nocona) 2270 .Case("core2", CK_Core2) 2271 .Case("penryn", CK_Penryn) 2272 .Case("bonnell", CK_Bonnell) 2273 .Case("atom", CK_Bonnell) // Legacy name. 2274 .Case("silvermont", CK_Silvermont) 2275 .Case("slm", CK_Silvermont) // Legacy name. 2276 .Case("nehalem", CK_Nehalem) 2277 .Case("corei7", CK_Nehalem) // Legacy name. 2278 .Case("westmere", CK_Westmere) 2279 .Case("sandybridge", CK_SandyBridge) 2280 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2281 .Case("ivybridge", CK_IvyBridge) 2282 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2283 .Case("haswell", CK_Haswell) 2284 .Case("core-avx2", CK_Haswell) // Legacy name. 2285 .Case("broadwell", CK_Broadwell) 2286 .Case("skylake", CK_Skylake) 2287 .Case("skx", CK_Skylake) // Legacy name. 2288 .Case("knl", CK_KNL) 2289 .Case("k6", CK_K6) 2290 .Case("k6-2", CK_K6_2) 2291 .Case("k6-3", CK_K6_3) 2292 .Case("athlon", CK_Athlon) 2293 .Case("athlon-tbird", CK_AthlonThunderbird) 2294 .Case("athlon-4", CK_Athlon4) 2295 .Case("athlon-xp", CK_AthlonXP) 2296 .Case("athlon-mp", CK_AthlonMP) 2297 .Case("athlon64", CK_Athlon64) 2298 .Case("athlon64-sse3", CK_Athlon64SSE3) 2299 .Case("athlon-fx", CK_AthlonFX) 2300 .Case("k8", CK_K8) 2301 .Case("k8-sse3", CK_K8SSE3) 2302 .Case("opteron", CK_Opteron) 2303 .Case("opteron-sse3", CK_OpteronSSE3) 2304 .Case("barcelona", CK_AMDFAM10) 2305 .Case("amdfam10", CK_AMDFAM10) 2306 .Case("btver1", CK_BTVER1) 2307 .Case("btver2", CK_BTVER2) 2308 .Case("bdver1", CK_BDVER1) 2309 .Case("bdver2", CK_BDVER2) 2310 .Case("bdver3", CK_BDVER3) 2311 .Case("bdver4", CK_BDVER4) 2312 .Case("x86-64", CK_x86_64) 2313 .Case("geode", CK_Geode) 2314 .Default(CK_Generic); 2315 2316 // Perform any per-CPU checks necessary to determine if this CPU is 2317 // acceptable. 2318 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2319 // invalid without explaining *why*. 2320 switch (CPU) { 2321 case CK_Generic: 2322 // No processor selected! 2323 return false; 2324 2325 case CK_i386: 2326 case CK_i486: 2327 case CK_WinChipC6: 2328 case CK_WinChip2: 2329 case CK_C3: 2330 case CK_i586: 2331 case CK_Pentium: 2332 case CK_PentiumMMX: 2333 case CK_i686: 2334 case CK_PentiumPro: 2335 case CK_Pentium2: 2336 case CK_Pentium3: 2337 case CK_Pentium3M: 2338 case CK_PentiumM: 2339 case CK_Yonah: 2340 case CK_C3_2: 2341 case CK_Pentium4: 2342 case CK_Pentium4M: 2343 case CK_Prescott: 2344 case CK_K6: 2345 case CK_K6_2: 2346 case CK_K6_3: 2347 case CK_Athlon: 2348 case CK_AthlonThunderbird: 2349 case CK_Athlon4: 2350 case CK_AthlonXP: 2351 case CK_AthlonMP: 2352 case CK_Geode: 2353 // Only accept certain architectures when compiling in 32-bit mode. 2354 if (getTriple().getArch() != llvm::Triple::x86) 2355 return false; 2356 2357 // Fallthrough 2358 case CK_Nocona: 2359 case CK_Core2: 2360 case CK_Penryn: 2361 case CK_Bonnell: 2362 case CK_Silvermont: 2363 case CK_Nehalem: 2364 case CK_Westmere: 2365 case CK_SandyBridge: 2366 case CK_IvyBridge: 2367 case CK_Haswell: 2368 case CK_Broadwell: 2369 case CK_Skylake: 2370 case CK_KNL: 2371 case CK_Athlon64: 2372 case CK_Athlon64SSE3: 2373 case CK_AthlonFX: 2374 case CK_K8: 2375 case CK_K8SSE3: 2376 case CK_Opteron: 2377 case CK_OpteronSSE3: 2378 case CK_AMDFAM10: 2379 case CK_BTVER1: 2380 case CK_BTVER2: 2381 case CK_BDVER1: 2382 case CK_BDVER2: 2383 case CK_BDVER3: 2384 case CK_BDVER4: 2385 case CK_x86_64: 2386 return true; 2387 } 2388 llvm_unreachable("Unhandled CPU kind"); 2389 } 2390 2391 bool setFPMath(StringRef Name) override; 2392 2393 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2394 // We accept all non-ARM calling conventions 2395 return (CC == CC_X86ThisCall || 2396 CC == CC_X86FastCall || 2397 CC == CC_X86StdCall || 2398 CC == CC_X86VectorCall || 2399 CC == CC_C || 2400 CC == CC_X86Pascal || 2401 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2402 } 2403 2404 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2405 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2406 } 2407 2408 bool hasSjLjLowering() const override { 2409 return true; 2410 } 2411 }; 2412 2413 bool X86TargetInfo::setFPMath(StringRef Name) { 2414 if (Name == "387") { 2415 FPMath = FP_387; 2416 return true; 2417 } 2418 if (Name == "sse") { 2419 FPMath = FP_SSE; 2420 return true; 2421 } 2422 return false; 2423 } 2424 2425 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2426 // FIXME: This *really* should not be here. 2427 2428 // X86_64 always has SSE2. 2429 if (getTriple().getArch() == llvm::Triple::x86_64) 2430 setFeatureEnabledImpl(Features, "sse2", true); 2431 2432 switch (CPU) { 2433 case CK_Generic: 2434 case CK_i386: 2435 case CK_i486: 2436 case CK_i586: 2437 case CK_Pentium: 2438 case CK_i686: 2439 case CK_PentiumPro: 2440 break; 2441 case CK_PentiumMMX: 2442 case CK_Pentium2: 2443 case CK_K6: 2444 case CK_WinChipC6: 2445 setFeatureEnabledImpl(Features, "mmx", true); 2446 break; 2447 case CK_Pentium3: 2448 case CK_Pentium3M: 2449 case CK_C3_2: 2450 setFeatureEnabledImpl(Features, "sse", true); 2451 break; 2452 case CK_PentiumM: 2453 case CK_Pentium4: 2454 case CK_Pentium4M: 2455 case CK_x86_64: 2456 setFeatureEnabledImpl(Features, "sse2", true); 2457 break; 2458 case CK_Yonah: 2459 case CK_Prescott: 2460 case CK_Nocona: 2461 setFeatureEnabledImpl(Features, "sse3", true); 2462 setFeatureEnabledImpl(Features, "cx16", true); 2463 break; 2464 case CK_Core2: 2465 case CK_Bonnell: 2466 setFeatureEnabledImpl(Features, "ssse3", true); 2467 setFeatureEnabledImpl(Features, "cx16", true); 2468 break; 2469 case CK_Penryn: 2470 setFeatureEnabledImpl(Features, "sse4.1", true); 2471 setFeatureEnabledImpl(Features, "cx16", true); 2472 break; 2473 case CK_Skylake: 2474 setFeatureEnabledImpl(Features, "avx512f", true); 2475 setFeatureEnabledImpl(Features, "avx512cd", true); 2476 setFeatureEnabledImpl(Features, "avx512dq", true); 2477 setFeatureEnabledImpl(Features, "avx512bw", true); 2478 setFeatureEnabledImpl(Features, "avx512vl", true); 2479 // FALLTHROUGH 2480 case CK_Broadwell: 2481 setFeatureEnabledImpl(Features, "rdseed", true); 2482 setFeatureEnabledImpl(Features, "adx", true); 2483 // FALLTHROUGH 2484 case CK_Haswell: 2485 setFeatureEnabledImpl(Features, "avx2", true); 2486 setFeatureEnabledImpl(Features, "lzcnt", true); 2487 setFeatureEnabledImpl(Features, "bmi", true); 2488 setFeatureEnabledImpl(Features, "bmi2", true); 2489 setFeatureEnabledImpl(Features, "rtm", true); 2490 setFeatureEnabledImpl(Features, "fma", true); 2491 // FALLTHROUGH 2492 case CK_IvyBridge: 2493 setFeatureEnabledImpl(Features, "rdrnd", true); 2494 setFeatureEnabledImpl(Features, "f16c", true); 2495 setFeatureEnabledImpl(Features, "fsgsbase", true); 2496 // FALLTHROUGH 2497 case CK_SandyBridge: 2498 setFeatureEnabledImpl(Features, "avx", true); 2499 // FALLTHROUGH 2500 case CK_Westmere: 2501 case CK_Silvermont: 2502 setFeatureEnabledImpl(Features, "aes", true); 2503 setFeatureEnabledImpl(Features, "pclmul", true); 2504 // FALLTHROUGH 2505 case CK_Nehalem: 2506 setFeatureEnabledImpl(Features, "sse4.2", true); 2507 setFeatureEnabledImpl(Features, "cx16", true); 2508 break; 2509 case CK_KNL: 2510 setFeatureEnabledImpl(Features, "avx512f", true); 2511 setFeatureEnabledImpl(Features, "avx512cd", true); 2512 setFeatureEnabledImpl(Features, "avx512er", true); 2513 setFeatureEnabledImpl(Features, "avx512pf", true); 2514 setFeatureEnabledImpl(Features, "rdseed", true); 2515 setFeatureEnabledImpl(Features, "adx", true); 2516 setFeatureEnabledImpl(Features, "lzcnt", true); 2517 setFeatureEnabledImpl(Features, "bmi", true); 2518 setFeatureEnabledImpl(Features, "bmi2", true); 2519 setFeatureEnabledImpl(Features, "rtm", true); 2520 setFeatureEnabledImpl(Features, "fma", true); 2521 setFeatureEnabledImpl(Features, "rdrnd", true); 2522 setFeatureEnabledImpl(Features, "f16c", true); 2523 setFeatureEnabledImpl(Features, "fsgsbase", true); 2524 setFeatureEnabledImpl(Features, "aes", true); 2525 setFeatureEnabledImpl(Features, "pclmul", true); 2526 setFeatureEnabledImpl(Features, "cx16", true); 2527 break; 2528 case CK_K6_2: 2529 case CK_K6_3: 2530 case CK_WinChip2: 2531 case CK_C3: 2532 setFeatureEnabledImpl(Features, "3dnow", true); 2533 break; 2534 case CK_Athlon: 2535 case CK_AthlonThunderbird: 2536 case CK_Geode: 2537 setFeatureEnabledImpl(Features, "3dnowa", true); 2538 break; 2539 case CK_Athlon4: 2540 case CK_AthlonXP: 2541 case CK_AthlonMP: 2542 setFeatureEnabledImpl(Features, "sse", true); 2543 setFeatureEnabledImpl(Features, "3dnowa", true); 2544 break; 2545 case CK_K8: 2546 case CK_Opteron: 2547 case CK_Athlon64: 2548 case CK_AthlonFX: 2549 setFeatureEnabledImpl(Features, "sse2", true); 2550 setFeatureEnabledImpl(Features, "3dnowa", true); 2551 break; 2552 case CK_AMDFAM10: 2553 setFeatureEnabledImpl(Features, "sse4a", true); 2554 setFeatureEnabledImpl(Features, "lzcnt", true); 2555 setFeatureEnabledImpl(Features, "popcnt", true); 2556 // FALLTHROUGH 2557 case CK_K8SSE3: 2558 case CK_OpteronSSE3: 2559 case CK_Athlon64SSE3: 2560 setFeatureEnabledImpl(Features, "sse3", true); 2561 setFeatureEnabledImpl(Features, "3dnowa", true); 2562 break; 2563 case CK_BTVER2: 2564 setFeatureEnabledImpl(Features, "avx", true); 2565 setFeatureEnabledImpl(Features, "aes", true); 2566 setFeatureEnabledImpl(Features, "pclmul", true); 2567 setFeatureEnabledImpl(Features, "bmi", true); 2568 setFeatureEnabledImpl(Features, "f16c", true); 2569 // FALLTHROUGH 2570 case CK_BTVER1: 2571 setFeatureEnabledImpl(Features, "ssse3", true); 2572 setFeatureEnabledImpl(Features, "sse4a", true); 2573 setFeatureEnabledImpl(Features, "lzcnt", true); 2574 setFeatureEnabledImpl(Features, "popcnt", true); 2575 setFeatureEnabledImpl(Features, "prfchw", true); 2576 setFeatureEnabledImpl(Features, "cx16", true); 2577 break; 2578 case CK_BDVER4: 2579 setFeatureEnabledImpl(Features, "avx2", true); 2580 setFeatureEnabledImpl(Features, "bmi2", true); 2581 // FALLTHROUGH 2582 case CK_BDVER3: 2583 setFeatureEnabledImpl(Features, "fsgsbase", true); 2584 // FALLTHROUGH 2585 case CK_BDVER2: 2586 setFeatureEnabledImpl(Features, "bmi", true); 2587 setFeatureEnabledImpl(Features, "fma", true); 2588 setFeatureEnabledImpl(Features, "f16c", true); 2589 setFeatureEnabledImpl(Features, "tbm", true); 2590 // FALLTHROUGH 2591 case CK_BDVER1: 2592 // xop implies avx, sse4a and fma4. 2593 setFeatureEnabledImpl(Features, "xop", true); 2594 setFeatureEnabledImpl(Features, "lzcnt", true); 2595 setFeatureEnabledImpl(Features, "aes", true); 2596 setFeatureEnabledImpl(Features, "pclmul", true); 2597 setFeatureEnabledImpl(Features, "prfchw", true); 2598 setFeatureEnabledImpl(Features, "cx16", true); 2599 break; 2600 } 2601 } 2602 2603 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2604 X86SSEEnum Level, bool Enabled) { 2605 if (Enabled) { 2606 switch (Level) { 2607 case AVX512F: 2608 Features["avx512f"] = true; 2609 case AVX2: 2610 Features["avx2"] = true; 2611 case AVX: 2612 Features["avx"] = true; 2613 case SSE42: 2614 Features["sse4.2"] = true; 2615 case SSE41: 2616 Features["sse4.1"] = true; 2617 case SSSE3: 2618 Features["ssse3"] = true; 2619 case SSE3: 2620 Features["sse3"] = true; 2621 case SSE2: 2622 Features["sse2"] = true; 2623 case SSE1: 2624 Features["sse"] = true; 2625 case NoSSE: 2626 break; 2627 } 2628 return; 2629 } 2630 2631 switch (Level) { 2632 case NoSSE: 2633 case SSE1: 2634 Features["sse"] = false; 2635 case SSE2: 2636 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2637 Features["sha"] = false; 2638 case SSE3: 2639 Features["sse3"] = false; 2640 setXOPLevel(Features, NoXOP, false); 2641 case SSSE3: 2642 Features["ssse3"] = false; 2643 case SSE41: 2644 Features["sse4.1"] = false; 2645 case SSE42: 2646 Features["sse4.2"] = false; 2647 case AVX: 2648 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2649 setXOPLevel(Features, FMA4, false); 2650 case AVX2: 2651 Features["avx2"] = false; 2652 case AVX512F: 2653 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2654 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2655 Features["avx512vl"] = false; 2656 } 2657 } 2658 2659 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2660 MMX3DNowEnum Level, bool Enabled) { 2661 if (Enabled) { 2662 switch (Level) { 2663 case AMD3DNowAthlon: 2664 Features["3dnowa"] = true; 2665 case AMD3DNow: 2666 Features["3dnow"] = true; 2667 case MMX: 2668 Features["mmx"] = true; 2669 case NoMMX3DNow: 2670 break; 2671 } 2672 return; 2673 } 2674 2675 switch (Level) { 2676 case NoMMX3DNow: 2677 case MMX: 2678 Features["mmx"] = false; 2679 case AMD3DNow: 2680 Features["3dnow"] = false; 2681 case AMD3DNowAthlon: 2682 Features["3dnowa"] = false; 2683 } 2684 } 2685 2686 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2687 bool Enabled) { 2688 if (Enabled) { 2689 switch (Level) { 2690 case XOP: 2691 Features["xop"] = true; 2692 case FMA4: 2693 Features["fma4"] = true; 2694 setSSELevel(Features, AVX, true); 2695 case SSE4A: 2696 Features["sse4a"] = true; 2697 setSSELevel(Features, SSE3, true); 2698 case NoXOP: 2699 break; 2700 } 2701 return; 2702 } 2703 2704 switch (Level) { 2705 case NoXOP: 2706 case SSE4A: 2707 Features["sse4a"] = false; 2708 case FMA4: 2709 Features["fma4"] = false; 2710 case XOP: 2711 Features["xop"] = false; 2712 } 2713 } 2714 2715 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2716 StringRef Name, bool Enabled) { 2717 Features[Name] = Enabled; 2718 2719 if (Name == "mmx") { 2720 setMMXLevel(Features, MMX, Enabled); 2721 } else if (Name == "sse") { 2722 setSSELevel(Features, SSE1, Enabled); 2723 } else if (Name == "sse2") { 2724 setSSELevel(Features, SSE2, Enabled); 2725 } else if (Name == "sse3") { 2726 setSSELevel(Features, SSE3, Enabled); 2727 } else if (Name == "ssse3") { 2728 setSSELevel(Features, SSSE3, Enabled); 2729 } else if (Name == "sse4.2") { 2730 setSSELevel(Features, SSE42, Enabled); 2731 } else if (Name == "sse4.1") { 2732 setSSELevel(Features, SSE41, Enabled); 2733 } else if (Name == "3dnow") { 2734 setMMXLevel(Features, AMD3DNow, Enabled); 2735 } else if (Name == "3dnowa") { 2736 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2737 } else if (Name == "aes") { 2738 if (Enabled) 2739 setSSELevel(Features, SSE2, Enabled); 2740 } else if (Name == "pclmul") { 2741 if (Enabled) 2742 setSSELevel(Features, SSE2, Enabled); 2743 } else if (Name == "avx") { 2744 setSSELevel(Features, AVX, Enabled); 2745 } else if (Name == "avx2") { 2746 setSSELevel(Features, AVX2, Enabled); 2747 } else if (Name == "avx512f") { 2748 setSSELevel(Features, AVX512F, Enabled); 2749 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2750 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2751 if (Enabled) 2752 setSSELevel(Features, AVX512F, Enabled); 2753 } else if (Name == "fma") { 2754 if (Enabled) 2755 setSSELevel(Features, AVX, Enabled); 2756 } else if (Name == "fma4") { 2757 setXOPLevel(Features, FMA4, Enabled); 2758 } else if (Name == "xop") { 2759 setXOPLevel(Features, XOP, Enabled); 2760 } else if (Name == "sse4a") { 2761 setXOPLevel(Features, SSE4A, Enabled); 2762 } else if (Name == "f16c") { 2763 if (Enabled) 2764 setSSELevel(Features, AVX, Enabled); 2765 } else if (Name == "sha") { 2766 if (Enabled) 2767 setSSELevel(Features, SSE2, Enabled); 2768 } 2769 } 2770 2771 /// handleTargetFeatures - Perform initialization based on the user 2772 /// configured set of features. 2773 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2774 DiagnosticsEngine &Diags) { 2775 // Remember the maximum enabled sselevel. 2776 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2777 // Ignore disabled features. 2778 if (Features[i][0] == '-') 2779 continue; 2780 2781 StringRef Feature = StringRef(Features[i]).substr(1); 2782 2783 if (Feature == "aes") { 2784 HasAES = true; 2785 continue; 2786 } 2787 2788 if (Feature == "pclmul") { 2789 HasPCLMUL = true; 2790 continue; 2791 } 2792 2793 if (Feature == "lzcnt") { 2794 HasLZCNT = true; 2795 continue; 2796 } 2797 2798 if (Feature == "rdrnd") { 2799 HasRDRND = true; 2800 continue; 2801 } 2802 2803 if (Feature == "fsgsbase") { 2804 HasFSGSBASE = true; 2805 continue; 2806 } 2807 2808 if (Feature == "bmi") { 2809 HasBMI = true; 2810 continue; 2811 } 2812 2813 if (Feature == "bmi2") { 2814 HasBMI2 = true; 2815 continue; 2816 } 2817 2818 if (Feature == "popcnt") { 2819 HasPOPCNT = true; 2820 continue; 2821 } 2822 2823 if (Feature == "rtm") { 2824 HasRTM = true; 2825 continue; 2826 } 2827 2828 if (Feature == "prfchw") { 2829 HasPRFCHW = true; 2830 continue; 2831 } 2832 2833 if (Feature == "rdseed") { 2834 HasRDSEED = true; 2835 continue; 2836 } 2837 2838 if (Feature == "adx") { 2839 HasADX = true; 2840 continue; 2841 } 2842 2843 if (Feature == "tbm") { 2844 HasTBM = true; 2845 continue; 2846 } 2847 2848 if (Feature == "fma") { 2849 HasFMA = true; 2850 continue; 2851 } 2852 2853 if (Feature == "f16c") { 2854 HasF16C = true; 2855 continue; 2856 } 2857 2858 if (Feature == "avx512cd") { 2859 HasAVX512CD = true; 2860 continue; 2861 } 2862 2863 if (Feature == "avx512er") { 2864 HasAVX512ER = true; 2865 continue; 2866 } 2867 2868 if (Feature == "avx512pf") { 2869 HasAVX512PF = true; 2870 continue; 2871 } 2872 2873 if (Feature == "avx512dq") { 2874 HasAVX512DQ = true; 2875 continue; 2876 } 2877 2878 if (Feature == "avx512bw") { 2879 HasAVX512BW = true; 2880 continue; 2881 } 2882 2883 if (Feature == "avx512vl") { 2884 HasAVX512VL = true; 2885 continue; 2886 } 2887 2888 if (Feature == "sha") { 2889 HasSHA = true; 2890 continue; 2891 } 2892 2893 if (Feature == "cx16") { 2894 HasCX16 = true; 2895 continue; 2896 } 2897 2898 assert(Features[i][0] == '+' && "Invalid target feature!"); 2899 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2900 .Case("avx512f", AVX512F) 2901 .Case("avx2", AVX2) 2902 .Case("avx", AVX) 2903 .Case("sse4.2", SSE42) 2904 .Case("sse4.1", SSE41) 2905 .Case("ssse3", SSSE3) 2906 .Case("sse3", SSE3) 2907 .Case("sse2", SSE2) 2908 .Case("sse", SSE1) 2909 .Default(NoSSE); 2910 SSELevel = std::max(SSELevel, Level); 2911 2912 MMX3DNowEnum ThreeDNowLevel = 2913 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2914 .Case("3dnowa", AMD3DNowAthlon) 2915 .Case("3dnow", AMD3DNow) 2916 .Case("mmx", MMX) 2917 .Default(NoMMX3DNow); 2918 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2919 2920 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2921 .Case("xop", XOP) 2922 .Case("fma4", FMA4) 2923 .Case("sse4a", SSE4A) 2924 .Default(NoXOP); 2925 XOPLevel = std::max(XOPLevel, XLevel); 2926 } 2927 2928 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2929 // Can't do this earlier because we need to be able to explicitly enable 2930 // popcnt and still disable sse4.2. 2931 if (!HasPOPCNT && SSELevel >= SSE42 && 2932 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2933 HasPOPCNT = true; 2934 Features.push_back("+popcnt"); 2935 } 2936 2937 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2938 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2939 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2940 HasPRFCHW = true; 2941 Features.push_back("+prfchw"); 2942 } 2943 2944 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2945 // matches the selected sse level. 2946 if (FPMath == FP_SSE && SSELevel < SSE1) { 2947 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2948 return false; 2949 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2950 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2951 return false; 2952 } 2953 2954 // Don't tell the backend if we're turning off mmx; it will end up disabling 2955 // SSE, which we don't want. 2956 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2957 // then enable MMX. 2958 std::vector<std::string>::iterator it; 2959 it = std::find(Features.begin(), Features.end(), "-mmx"); 2960 if (it != Features.end()) 2961 Features.erase(it); 2962 else if (SSELevel > NoSSE) 2963 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2964 return true; 2965 } 2966 2967 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2968 /// definitions for this particular subtarget. 2969 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2970 MacroBuilder &Builder) const { 2971 // Target identification. 2972 if (getTriple().getArch() == llvm::Triple::x86_64) { 2973 Builder.defineMacro("__amd64__"); 2974 Builder.defineMacro("__amd64"); 2975 Builder.defineMacro("__x86_64"); 2976 Builder.defineMacro("__x86_64__"); 2977 if (getTriple().getArchName() == "x86_64h") { 2978 Builder.defineMacro("__x86_64h"); 2979 Builder.defineMacro("__x86_64h__"); 2980 } 2981 } else { 2982 DefineStd(Builder, "i386", Opts); 2983 } 2984 2985 // Subtarget options. 2986 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2987 // truly should be based on -mtune options. 2988 switch (CPU) { 2989 case CK_Generic: 2990 break; 2991 case CK_i386: 2992 // The rest are coming from the i386 define above. 2993 Builder.defineMacro("__tune_i386__"); 2994 break; 2995 case CK_i486: 2996 case CK_WinChipC6: 2997 case CK_WinChip2: 2998 case CK_C3: 2999 defineCPUMacros(Builder, "i486"); 3000 break; 3001 case CK_PentiumMMX: 3002 Builder.defineMacro("__pentium_mmx__"); 3003 Builder.defineMacro("__tune_pentium_mmx__"); 3004 // Fallthrough 3005 case CK_i586: 3006 case CK_Pentium: 3007 defineCPUMacros(Builder, "i586"); 3008 defineCPUMacros(Builder, "pentium"); 3009 break; 3010 case CK_Pentium3: 3011 case CK_Pentium3M: 3012 case CK_PentiumM: 3013 Builder.defineMacro("__tune_pentium3__"); 3014 // Fallthrough 3015 case CK_Pentium2: 3016 case CK_C3_2: 3017 Builder.defineMacro("__tune_pentium2__"); 3018 // Fallthrough 3019 case CK_PentiumPro: 3020 Builder.defineMacro("__tune_i686__"); 3021 Builder.defineMacro("__tune_pentiumpro__"); 3022 // Fallthrough 3023 case CK_i686: 3024 Builder.defineMacro("__i686"); 3025 Builder.defineMacro("__i686__"); 3026 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3027 Builder.defineMacro("__pentiumpro"); 3028 Builder.defineMacro("__pentiumpro__"); 3029 break; 3030 case CK_Pentium4: 3031 case CK_Pentium4M: 3032 defineCPUMacros(Builder, "pentium4"); 3033 break; 3034 case CK_Yonah: 3035 case CK_Prescott: 3036 case CK_Nocona: 3037 defineCPUMacros(Builder, "nocona"); 3038 break; 3039 case CK_Core2: 3040 case CK_Penryn: 3041 defineCPUMacros(Builder, "core2"); 3042 break; 3043 case CK_Bonnell: 3044 defineCPUMacros(Builder, "atom"); 3045 break; 3046 case CK_Silvermont: 3047 defineCPUMacros(Builder, "slm"); 3048 break; 3049 case CK_Nehalem: 3050 case CK_Westmere: 3051 case CK_SandyBridge: 3052 case CK_IvyBridge: 3053 case CK_Haswell: 3054 case CK_Broadwell: 3055 // FIXME: Historically, we defined this legacy name, it would be nice to 3056 // remove it at some point. We've never exposed fine-grained names for 3057 // recent primary x86 CPUs, and we should keep it that way. 3058 defineCPUMacros(Builder, "corei7"); 3059 break; 3060 case CK_Skylake: 3061 // FIXME: Historically, we defined this legacy name, it would be nice to 3062 // remove it at some point. This is the only fine-grained CPU macro in the 3063 // main intel CPU line, and it would be better to not have these and force 3064 // people to use ISA macros. 3065 defineCPUMacros(Builder, "skx"); 3066 break; 3067 case CK_KNL: 3068 defineCPUMacros(Builder, "knl"); 3069 break; 3070 case CK_K6_2: 3071 Builder.defineMacro("__k6_2__"); 3072 Builder.defineMacro("__tune_k6_2__"); 3073 // Fallthrough 3074 case CK_K6_3: 3075 if (CPU != CK_K6_2) { // In case of fallthrough 3076 // FIXME: GCC may be enabling these in cases where some other k6 3077 // architecture is specified but -m3dnow is explicitly provided. The 3078 // exact semantics need to be determined and emulated here. 3079 Builder.defineMacro("__k6_3__"); 3080 Builder.defineMacro("__tune_k6_3__"); 3081 } 3082 // Fallthrough 3083 case CK_K6: 3084 defineCPUMacros(Builder, "k6"); 3085 break; 3086 case CK_Athlon: 3087 case CK_AthlonThunderbird: 3088 case CK_Athlon4: 3089 case CK_AthlonXP: 3090 case CK_AthlonMP: 3091 defineCPUMacros(Builder, "athlon"); 3092 if (SSELevel != NoSSE) { 3093 Builder.defineMacro("__athlon_sse__"); 3094 Builder.defineMacro("__tune_athlon_sse__"); 3095 } 3096 break; 3097 case CK_K8: 3098 case CK_K8SSE3: 3099 case CK_x86_64: 3100 case CK_Opteron: 3101 case CK_OpteronSSE3: 3102 case CK_Athlon64: 3103 case CK_Athlon64SSE3: 3104 case CK_AthlonFX: 3105 defineCPUMacros(Builder, "k8"); 3106 break; 3107 case CK_AMDFAM10: 3108 defineCPUMacros(Builder, "amdfam10"); 3109 break; 3110 case CK_BTVER1: 3111 defineCPUMacros(Builder, "btver1"); 3112 break; 3113 case CK_BTVER2: 3114 defineCPUMacros(Builder, "btver2"); 3115 break; 3116 case CK_BDVER1: 3117 defineCPUMacros(Builder, "bdver1"); 3118 break; 3119 case CK_BDVER2: 3120 defineCPUMacros(Builder, "bdver2"); 3121 break; 3122 case CK_BDVER3: 3123 defineCPUMacros(Builder, "bdver3"); 3124 break; 3125 case CK_BDVER4: 3126 defineCPUMacros(Builder, "bdver4"); 3127 break; 3128 case CK_Geode: 3129 defineCPUMacros(Builder, "geode"); 3130 break; 3131 } 3132 3133 // Target properties. 3134 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3135 3136 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3137 // functions in glibc header files that use FP Stack inline asm which the 3138 // backend can't deal with (PR879). 3139 Builder.defineMacro("__NO_MATH_INLINES"); 3140 3141 if (HasAES) 3142 Builder.defineMacro("__AES__"); 3143 3144 if (HasPCLMUL) 3145 Builder.defineMacro("__PCLMUL__"); 3146 3147 if (HasLZCNT) 3148 Builder.defineMacro("__LZCNT__"); 3149 3150 if (HasRDRND) 3151 Builder.defineMacro("__RDRND__"); 3152 3153 if (HasFSGSBASE) 3154 Builder.defineMacro("__FSGSBASE__"); 3155 3156 if (HasBMI) 3157 Builder.defineMacro("__BMI__"); 3158 3159 if (HasBMI2) 3160 Builder.defineMacro("__BMI2__"); 3161 3162 if (HasPOPCNT) 3163 Builder.defineMacro("__POPCNT__"); 3164 3165 if (HasRTM) 3166 Builder.defineMacro("__RTM__"); 3167 3168 if (HasPRFCHW) 3169 Builder.defineMacro("__PRFCHW__"); 3170 3171 if (HasRDSEED) 3172 Builder.defineMacro("__RDSEED__"); 3173 3174 if (HasADX) 3175 Builder.defineMacro("__ADX__"); 3176 3177 if (HasTBM) 3178 Builder.defineMacro("__TBM__"); 3179 3180 switch (XOPLevel) { 3181 case XOP: 3182 Builder.defineMacro("__XOP__"); 3183 case FMA4: 3184 Builder.defineMacro("__FMA4__"); 3185 case SSE4A: 3186 Builder.defineMacro("__SSE4A__"); 3187 case NoXOP: 3188 break; 3189 } 3190 3191 if (HasFMA) 3192 Builder.defineMacro("__FMA__"); 3193 3194 if (HasF16C) 3195 Builder.defineMacro("__F16C__"); 3196 3197 if (HasAVX512CD) 3198 Builder.defineMacro("__AVX512CD__"); 3199 if (HasAVX512ER) 3200 Builder.defineMacro("__AVX512ER__"); 3201 if (HasAVX512PF) 3202 Builder.defineMacro("__AVX512PF__"); 3203 if (HasAVX512DQ) 3204 Builder.defineMacro("__AVX512DQ__"); 3205 if (HasAVX512BW) 3206 Builder.defineMacro("__AVX512BW__"); 3207 if (HasAVX512VL) 3208 Builder.defineMacro("__AVX512VL__"); 3209 3210 if (HasSHA) 3211 Builder.defineMacro("__SHA__"); 3212 3213 if (HasCX16) 3214 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3215 3216 // Each case falls through to the previous one here. 3217 switch (SSELevel) { 3218 case AVX512F: 3219 Builder.defineMacro("__AVX512F__"); 3220 case AVX2: 3221 Builder.defineMacro("__AVX2__"); 3222 case AVX: 3223 Builder.defineMacro("__AVX__"); 3224 case SSE42: 3225 Builder.defineMacro("__SSE4_2__"); 3226 case SSE41: 3227 Builder.defineMacro("__SSE4_1__"); 3228 case SSSE3: 3229 Builder.defineMacro("__SSSE3__"); 3230 case SSE3: 3231 Builder.defineMacro("__SSE3__"); 3232 case SSE2: 3233 Builder.defineMacro("__SSE2__"); 3234 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3235 case SSE1: 3236 Builder.defineMacro("__SSE__"); 3237 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3238 case NoSSE: 3239 break; 3240 } 3241 3242 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3243 switch (SSELevel) { 3244 case AVX512F: 3245 case AVX2: 3246 case AVX: 3247 case SSE42: 3248 case SSE41: 3249 case SSSE3: 3250 case SSE3: 3251 case SSE2: 3252 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3253 break; 3254 case SSE1: 3255 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3256 break; 3257 default: 3258 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3259 } 3260 } 3261 3262 // Each case falls through to the previous one here. 3263 switch (MMX3DNowLevel) { 3264 case AMD3DNowAthlon: 3265 Builder.defineMacro("__3dNOW_A__"); 3266 case AMD3DNow: 3267 Builder.defineMacro("__3dNOW__"); 3268 case MMX: 3269 Builder.defineMacro("__MMX__"); 3270 case NoMMX3DNow: 3271 break; 3272 } 3273 3274 if (CPU >= CK_i486) { 3275 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3276 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3277 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3278 } 3279 if (CPU >= CK_i586) 3280 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3281 } 3282 3283 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3284 return llvm::StringSwitch<bool>(Feature) 3285 .Case("aes", HasAES) 3286 .Case("avx", SSELevel >= AVX) 3287 .Case("avx2", SSELevel >= AVX2) 3288 .Case("avx512f", SSELevel >= AVX512F) 3289 .Case("avx512cd", HasAVX512CD) 3290 .Case("avx512er", HasAVX512ER) 3291 .Case("avx512pf", HasAVX512PF) 3292 .Case("avx512dq", HasAVX512DQ) 3293 .Case("avx512bw", HasAVX512BW) 3294 .Case("avx512vl", HasAVX512VL) 3295 .Case("bmi", HasBMI) 3296 .Case("bmi2", HasBMI2) 3297 .Case("cx16", HasCX16) 3298 .Case("f16c", HasF16C) 3299 .Case("fma", HasFMA) 3300 .Case("fma4", XOPLevel >= FMA4) 3301 .Case("fsgsbase", HasFSGSBASE) 3302 .Case("lzcnt", HasLZCNT) 3303 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3304 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3305 .Case("mmx", MMX3DNowLevel >= MMX) 3306 .Case("pclmul", HasPCLMUL) 3307 .Case("popcnt", HasPOPCNT) 3308 .Case("prfchw", HasPRFCHW) 3309 .Case("rdrnd", HasRDRND) 3310 .Case("rdseed", HasRDSEED) 3311 .Case("rtm", HasRTM) 3312 .Case("sha", HasSHA) 3313 .Case("sse", SSELevel >= SSE1) 3314 .Case("sse2", SSELevel >= SSE2) 3315 .Case("sse3", SSELevel >= SSE3) 3316 .Case("ssse3", SSELevel >= SSSE3) 3317 .Case("sse4.1", SSELevel >= SSE41) 3318 .Case("sse4.2", SSELevel >= SSE42) 3319 .Case("sse4a", XOPLevel >= SSE4A) 3320 .Case("tbm", HasTBM) 3321 .Case("x86", true) 3322 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3323 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3324 .Case("xop", XOPLevel >= XOP) 3325 .Default(false); 3326 } 3327 3328 bool 3329 X86TargetInfo::validateAsmConstraint(const char *&Name, 3330 TargetInfo::ConstraintInfo &Info) const { 3331 switch (*Name) { 3332 default: return false; 3333 case 'I': 3334 Info.setRequiresImmediate(0, 31); 3335 return true; 3336 case 'J': 3337 Info.setRequiresImmediate(0, 63); 3338 return true; 3339 case 'K': 3340 Info.setRequiresImmediate(-128, 127); 3341 return true; 3342 case 'L': 3343 // FIXME: properly analyze this constraint: 3344 // must be one of 0xff, 0xffff, or 0xffffffff 3345 return true; 3346 case 'M': 3347 Info.setRequiresImmediate(0, 3); 3348 return true; 3349 case 'N': 3350 Info.setRequiresImmediate(0, 255); 3351 return true; 3352 case 'O': 3353 Info.setRequiresImmediate(0, 127); 3354 return true; 3355 case 'Y': // first letter of a pair: 3356 switch (*(Name+1)) { 3357 default: return false; 3358 case '0': // First SSE register. 3359 case 't': // Any SSE register, when SSE2 is enabled. 3360 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3361 case 'm': // any MMX register, when inter-unit moves enabled. 3362 break; // falls through to setAllowsRegister. 3363 } 3364 case 'f': // any x87 floating point stack register. 3365 // Constraint 'f' cannot be used for output operands. 3366 if (Info.ConstraintStr[0] == '=') 3367 return false; 3368 3369 Info.setAllowsRegister(); 3370 return true; 3371 case 'a': // eax. 3372 case 'b': // ebx. 3373 case 'c': // ecx. 3374 case 'd': // edx. 3375 case 'S': // esi. 3376 case 'D': // edi. 3377 case 'A': // edx:eax. 3378 case 't': // top of floating point stack. 3379 case 'u': // second from top of floating point stack. 3380 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3381 case 'y': // Any MMX register. 3382 case 'x': // Any SSE register. 3383 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3384 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3385 case 'l': // "Index" registers: any general register that can be used as an 3386 // index in a base+index memory access. 3387 Info.setAllowsRegister(); 3388 return true; 3389 case 'C': // SSE floating point constant. 3390 case 'G': // x87 floating point constant. 3391 case 'e': // 32-bit signed integer constant for use with zero-extending 3392 // x86_64 instructions. 3393 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3394 // x86_64 instructions. 3395 return true; 3396 } 3397 } 3398 3399 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3400 unsigned Size) const { 3401 // Strip off constraint modifiers. 3402 while (Constraint[0] == '=' || 3403 Constraint[0] == '+' || 3404 Constraint[0] == '&') 3405 Constraint = Constraint.substr(1); 3406 3407 return validateOperandSize(Constraint, Size); 3408 } 3409 3410 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3411 unsigned Size) const { 3412 return validateOperandSize(Constraint, Size); 3413 } 3414 3415 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3416 unsigned Size) const { 3417 switch (Constraint[0]) { 3418 default: break; 3419 case 'y': 3420 return Size <= 64; 3421 case 'f': 3422 case 't': 3423 case 'u': 3424 return Size <= 128; 3425 case 'x': 3426 // 256-bit ymm registers can be used if target supports AVX. 3427 return Size <= (SSELevel >= AVX ? 256U : 128U); 3428 } 3429 3430 return true; 3431 } 3432 3433 std::string 3434 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3435 switch (*Constraint) { 3436 case 'a': return std::string("{ax}"); 3437 case 'b': return std::string("{bx}"); 3438 case 'c': return std::string("{cx}"); 3439 case 'd': return std::string("{dx}"); 3440 case 'S': return std::string("{si}"); 3441 case 'D': return std::string("{di}"); 3442 case 'p': // address 3443 return std::string("im"); 3444 case 't': // top of floating point stack. 3445 return std::string("{st}"); 3446 case 'u': // second from top of floating point stack. 3447 return std::string("{st(1)}"); // second from top of floating point stack. 3448 default: 3449 return std::string(1, *Constraint); 3450 } 3451 } 3452 3453 // X86-32 generic target 3454 class X86_32TargetInfo : public X86TargetInfo { 3455 public: 3456 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3457 DoubleAlign = LongLongAlign = 32; 3458 LongDoubleWidth = 96; 3459 LongDoubleAlign = 32; 3460 SuitableAlign = 128; 3461 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3462 SizeType = UnsignedInt; 3463 PtrDiffType = SignedInt; 3464 IntPtrType = SignedInt; 3465 RegParmMax = 3; 3466 3467 // Use fpret for all types. 3468 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3469 (1 << TargetInfo::Double) | 3470 (1 << TargetInfo::LongDouble)); 3471 3472 // x86-32 has atomics up to 8 bytes 3473 // FIXME: Check that we actually have cmpxchg8b before setting 3474 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3475 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3476 } 3477 BuiltinVaListKind getBuiltinVaListKind() const override { 3478 return TargetInfo::CharPtrBuiltinVaList; 3479 } 3480 3481 int getEHDataRegisterNumber(unsigned RegNo) const override { 3482 if (RegNo == 0) return 0; 3483 if (RegNo == 1) return 2; 3484 return -1; 3485 } 3486 bool validateOperandSize(StringRef Constraint, 3487 unsigned Size) const override { 3488 switch (Constraint[0]) { 3489 default: break; 3490 case 'R': 3491 case 'q': 3492 case 'Q': 3493 case 'a': 3494 case 'b': 3495 case 'c': 3496 case 'd': 3497 case 'S': 3498 case 'D': 3499 return Size <= 32; 3500 case 'A': 3501 return Size <= 64; 3502 } 3503 3504 return X86TargetInfo::validateOperandSize(Constraint, Size); 3505 } 3506 }; 3507 3508 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3509 public: 3510 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3511 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3512 3513 unsigned getFloatEvalMethod() const override { 3514 unsigned Major, Minor, Micro; 3515 getTriple().getOSVersion(Major, Minor, Micro); 3516 // New NetBSD uses the default rounding mode. 3517 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3518 return X86_32TargetInfo::getFloatEvalMethod(); 3519 // NetBSD before 6.99.26 defaults to "double" rounding. 3520 return 1; 3521 } 3522 }; 3523 3524 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3525 public: 3526 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3527 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3528 SizeType = UnsignedLong; 3529 IntPtrType = SignedLong; 3530 PtrDiffType = SignedLong; 3531 } 3532 }; 3533 3534 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3535 public: 3536 BitrigI386TargetInfo(const llvm::Triple &Triple) 3537 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3538 SizeType = UnsignedLong; 3539 IntPtrType = SignedLong; 3540 PtrDiffType = SignedLong; 3541 } 3542 }; 3543 3544 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3545 public: 3546 DarwinI386TargetInfo(const llvm::Triple &Triple) 3547 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3548 LongDoubleWidth = 128; 3549 LongDoubleAlign = 128; 3550 SuitableAlign = 128; 3551 MaxVectorAlign = 256; 3552 SizeType = UnsignedLong; 3553 IntPtrType = SignedLong; 3554 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3555 HasAlignMac68kSupport = true; 3556 } 3557 3558 }; 3559 3560 // x86-32 Windows target 3561 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3562 public: 3563 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3564 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3565 WCharType = UnsignedShort; 3566 DoubleAlign = LongLongAlign = 64; 3567 bool IsWinCOFF = 3568 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3569 DescriptionString = IsWinCOFF 3570 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3571 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3572 } 3573 void getTargetDefines(const LangOptions &Opts, 3574 MacroBuilder &Builder) const override { 3575 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3576 } 3577 }; 3578 3579 // x86-32 Windows Visual Studio target 3580 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3581 public: 3582 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3583 : WindowsX86_32TargetInfo(Triple) { 3584 LongDoubleWidth = LongDoubleAlign = 64; 3585 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3586 } 3587 void getTargetDefines(const LangOptions &Opts, 3588 MacroBuilder &Builder) const override { 3589 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3590 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3591 // The value of the following reflects processor type. 3592 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3593 // We lost the original triple, so we use the default. 3594 Builder.defineMacro("_M_IX86", "600"); 3595 } 3596 }; 3597 } // end anonymous namespace 3598 3599 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3600 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang supports 3601 // __declspec natively under -fms-extensions, but we define a no-op __declspec 3602 // macro anyway for pre-processor compatibility. 3603 if (Opts.MicrosoftExt) 3604 Builder.defineMacro("__declspec", "__declspec"); 3605 else 3606 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3607 3608 if (!Opts.MicrosoftExt) { 3609 // Provide macros for all the calling convention keywords. Provide both 3610 // single and double underscore prefixed variants. These are available on 3611 // x64 as well as x86, even though they have no effect. 3612 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3613 for (const char *CC : CCs) { 3614 std::string GCCSpelling = "__attribute__((__"; 3615 GCCSpelling += CC; 3616 GCCSpelling += "__))"; 3617 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3618 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3619 } 3620 } 3621 } 3622 3623 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3624 Builder.defineMacro("__MSVCRT__"); 3625 Builder.defineMacro("__MINGW32__"); 3626 addCygMingDefines(Opts, Builder); 3627 } 3628 3629 namespace { 3630 // x86-32 MinGW target 3631 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3632 public: 3633 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3634 : WindowsX86_32TargetInfo(Triple) {} 3635 void getTargetDefines(const LangOptions &Opts, 3636 MacroBuilder &Builder) const override { 3637 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3638 DefineStd(Builder, "WIN32", Opts); 3639 DefineStd(Builder, "WINNT", Opts); 3640 Builder.defineMacro("_X86_"); 3641 addMinGWDefines(Opts, Builder); 3642 } 3643 }; 3644 3645 // x86-32 Cygwin target 3646 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3647 public: 3648 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3649 : X86_32TargetInfo(Triple) { 3650 TLSSupported = false; 3651 WCharType = UnsignedShort; 3652 DoubleAlign = LongLongAlign = 64; 3653 DescriptionString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3654 } 3655 void getTargetDefines(const LangOptions &Opts, 3656 MacroBuilder &Builder) const override { 3657 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3658 Builder.defineMacro("_X86_"); 3659 Builder.defineMacro("__CYGWIN__"); 3660 Builder.defineMacro("__CYGWIN32__"); 3661 addCygMingDefines(Opts, Builder); 3662 DefineStd(Builder, "unix", Opts); 3663 if (Opts.CPlusPlus) 3664 Builder.defineMacro("_GNU_SOURCE"); 3665 } 3666 }; 3667 3668 // x86-32 Haiku target 3669 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3670 public: 3671 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3672 SizeType = UnsignedLong; 3673 IntPtrType = SignedLong; 3674 PtrDiffType = SignedLong; 3675 ProcessIDType = SignedLong; 3676 this->UserLabelPrefix = ""; 3677 this->TLSSupported = false; 3678 } 3679 void getTargetDefines(const LangOptions &Opts, 3680 MacroBuilder &Builder) const override { 3681 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3682 Builder.defineMacro("__INTEL__"); 3683 Builder.defineMacro("__HAIKU__"); 3684 } 3685 }; 3686 3687 // RTEMS Target 3688 template<typename Target> 3689 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3690 protected: 3691 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3692 MacroBuilder &Builder) const override { 3693 // RTEMS defines; list based off of gcc output 3694 3695 Builder.defineMacro("__rtems__"); 3696 Builder.defineMacro("__ELF__"); 3697 } 3698 3699 public: 3700 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3701 this->UserLabelPrefix = ""; 3702 3703 switch (Triple.getArch()) { 3704 default: 3705 case llvm::Triple::x86: 3706 // this->MCountName = ".mcount"; 3707 break; 3708 case llvm::Triple::mips: 3709 case llvm::Triple::mipsel: 3710 case llvm::Triple::ppc: 3711 case llvm::Triple::ppc64: 3712 case llvm::Triple::ppc64le: 3713 // this->MCountName = "_mcount"; 3714 break; 3715 case llvm::Triple::arm: 3716 // this->MCountName = "__mcount"; 3717 break; 3718 } 3719 } 3720 }; 3721 3722 // x86-32 RTEMS target 3723 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3724 public: 3725 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3726 SizeType = UnsignedLong; 3727 IntPtrType = SignedLong; 3728 PtrDiffType = SignedLong; 3729 this->UserLabelPrefix = ""; 3730 } 3731 void getTargetDefines(const LangOptions &Opts, 3732 MacroBuilder &Builder) const override { 3733 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3734 Builder.defineMacro("__INTEL__"); 3735 Builder.defineMacro("__rtems__"); 3736 } 3737 }; 3738 3739 // x86-64 generic target 3740 class X86_64TargetInfo : public X86TargetInfo { 3741 public: 3742 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3743 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3744 bool IsWinCOFF = 3745 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3746 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3747 LongDoubleWidth = 128; 3748 LongDoubleAlign = 128; 3749 LargeArrayMinWidth = 128; 3750 LargeArrayAlign = 128; 3751 SuitableAlign = 128; 3752 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3753 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3754 IntPtrType = IsX32 ? SignedInt : SignedLong; 3755 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3756 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3757 RegParmMax = 6; 3758 3759 // Pointers are 32-bit in x32. 3760 DescriptionString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3761 : IsWinCOFF 3762 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 3763 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3764 3765 // Use fpret only for long double. 3766 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3767 3768 // Use fp2ret for _Complex long double. 3769 ComplexLongDoubleUsesFP2Ret = true; 3770 3771 // x86-64 has atomics up to 16 bytes. 3772 MaxAtomicPromoteWidth = 128; 3773 MaxAtomicInlineWidth = 128; 3774 } 3775 BuiltinVaListKind getBuiltinVaListKind() const override { 3776 return TargetInfo::X86_64ABIBuiltinVaList; 3777 } 3778 3779 int getEHDataRegisterNumber(unsigned RegNo) const override { 3780 if (RegNo == 0) return 0; 3781 if (RegNo == 1) return 1; 3782 return -1; 3783 } 3784 3785 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3786 return (CC == CC_C || 3787 CC == CC_X86VectorCall || 3788 CC == CC_IntelOclBicc || 3789 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3790 } 3791 3792 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3793 return CC_C; 3794 } 3795 3796 // for x32 we need it here explicitly 3797 bool hasInt128Type() const override { return true; } 3798 }; 3799 3800 // x86-64 Windows target 3801 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3802 public: 3803 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3804 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3805 WCharType = UnsignedShort; 3806 LongWidth = LongAlign = 32; 3807 DoubleAlign = LongLongAlign = 64; 3808 IntMaxType = SignedLongLong; 3809 Int64Type = SignedLongLong; 3810 SizeType = UnsignedLongLong; 3811 PtrDiffType = SignedLongLong; 3812 IntPtrType = SignedLongLong; 3813 this->UserLabelPrefix = ""; 3814 } 3815 3816 void getTargetDefines(const LangOptions &Opts, 3817 MacroBuilder &Builder) const override { 3818 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3819 Builder.defineMacro("_WIN64"); 3820 } 3821 3822 BuiltinVaListKind getBuiltinVaListKind() const override { 3823 return TargetInfo::CharPtrBuiltinVaList; 3824 } 3825 3826 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3827 switch (CC) { 3828 case CC_X86StdCall: 3829 case CC_X86ThisCall: 3830 case CC_X86FastCall: 3831 return CCCR_Ignore; 3832 case CC_C: 3833 case CC_X86VectorCall: 3834 case CC_IntelOclBicc: 3835 case CC_X86_64SysV: 3836 return CCCR_OK; 3837 default: 3838 return CCCR_Warning; 3839 } 3840 } 3841 }; 3842 3843 // x86-64 Windows Visual Studio target 3844 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 3845 public: 3846 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 3847 : WindowsX86_64TargetInfo(Triple) { 3848 LongDoubleWidth = LongDoubleAlign = 64; 3849 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3850 } 3851 void getTargetDefines(const LangOptions &Opts, 3852 MacroBuilder &Builder) const override { 3853 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3854 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3855 Builder.defineMacro("_M_X64"); 3856 Builder.defineMacro("_M_AMD64"); 3857 } 3858 }; 3859 3860 // x86-64 MinGW target 3861 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3862 public: 3863 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3864 : WindowsX86_64TargetInfo(Triple) {} 3865 void getTargetDefines(const LangOptions &Opts, 3866 MacroBuilder &Builder) const override { 3867 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3868 DefineStd(Builder, "WIN64", Opts); 3869 Builder.defineMacro("__MINGW64__"); 3870 addMinGWDefines(Opts, Builder); 3871 3872 // GCC defines this macro when it is using __gxx_personality_seh0. 3873 if (!Opts.SjLjExceptions) 3874 Builder.defineMacro("__SEH__"); 3875 } 3876 }; 3877 3878 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3879 public: 3880 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3881 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3882 Int64Type = SignedLongLong; 3883 MaxVectorAlign = 256; 3884 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 3885 llvm::Triple T = llvm::Triple(Triple); 3886 if (T.isiOS()) 3887 UseSignedCharForObjCBool = false; 3888 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 3889 } 3890 }; 3891 3892 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3893 public: 3894 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3895 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3896 IntMaxType = SignedLongLong; 3897 Int64Type = SignedLongLong; 3898 } 3899 }; 3900 3901 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3902 public: 3903 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3904 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3905 IntMaxType = SignedLongLong; 3906 Int64Type = SignedLongLong; 3907 } 3908 }; 3909 3910 class ARMTargetInfo : public TargetInfo { 3911 // Possible FPU choices. 3912 enum FPUMode { 3913 VFP2FPU = (1 << 0), 3914 VFP3FPU = (1 << 1), 3915 VFP4FPU = (1 << 2), 3916 NeonFPU = (1 << 3), 3917 FPARMV8 = (1 << 4) 3918 }; 3919 3920 // Possible HWDiv features. 3921 enum HWDivMode { 3922 HWDivThumb = (1 << 0), 3923 HWDivARM = (1 << 1) 3924 }; 3925 3926 static bool FPUModeIsVFP(FPUMode Mode) { 3927 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 3928 } 3929 3930 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3931 static const char * const GCCRegNames[]; 3932 3933 std::string ABI, CPU; 3934 3935 enum { 3936 FP_Default, 3937 FP_VFP, 3938 FP_Neon 3939 } FPMath; 3940 3941 unsigned FPU : 5; 3942 3943 unsigned IsAAPCS : 1; 3944 unsigned IsThumb : 1; 3945 unsigned HWDiv : 2; 3946 3947 // Initialized via features. 3948 unsigned SoftFloat : 1; 3949 unsigned SoftFloatABI : 1; 3950 3951 unsigned CRC : 1; 3952 unsigned Crypto : 1; 3953 3954 // ACLE 6.5.1 Hardware floating point 3955 enum { 3956 HW_FP_HP = (1 << 1), /// half (16-bit) 3957 HW_FP_SP = (1 << 2), /// single (32-bit) 3958 HW_FP_DP = (1 << 3), /// double (64-bit) 3959 }; 3960 uint32_t HW_FP; 3961 3962 static const Builtin::Info BuiltinInfo[]; 3963 3964 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3965 StringRef ArchName = T.getArchName(); 3966 if (T.getArch() == llvm::Triple::arm || 3967 T.getArch() == llvm::Triple::armeb) { 3968 StringRef VersionStr; 3969 if (ArchName.startswith("armv")) 3970 VersionStr = ArchName.substr(4, 1); 3971 else if (ArchName.startswith("armebv")) 3972 VersionStr = ArchName.substr(6, 1); 3973 else 3974 return false; 3975 unsigned Version; 3976 if (VersionStr.getAsInteger(10, Version)) 3977 return false; 3978 return Version >= 6; 3979 } 3980 assert(T.getArch() == llvm::Triple::thumb || 3981 T.getArch() == llvm::Triple::thumbeb); 3982 StringRef VersionStr; 3983 if (ArchName.startswith("thumbv")) 3984 VersionStr = ArchName.substr(6, 1); 3985 else if (ArchName.startswith("thumbebv")) 3986 VersionStr = ArchName.substr(8, 1); 3987 else 3988 return false; 3989 unsigned Version; 3990 if (VersionStr.getAsInteger(10, Version)) 3991 return false; 3992 return Version >= 7; 3993 } 3994 3995 void setABIAAPCS() { 3996 IsAAPCS = true; 3997 3998 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 3999 const llvm::Triple &T = getTriple(); 4000 4001 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4002 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4003 T.getOS() == llvm::Triple::Bitrig) 4004 SizeType = UnsignedLong; 4005 else 4006 SizeType = UnsignedInt; 4007 4008 switch (T.getOS()) { 4009 case llvm::Triple::NetBSD: 4010 WCharType = SignedInt; 4011 break; 4012 case llvm::Triple::Win32: 4013 WCharType = UnsignedShort; 4014 break; 4015 case llvm::Triple::Linux: 4016 default: 4017 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4018 WCharType = UnsignedInt; 4019 break; 4020 } 4021 4022 UseBitFieldTypeAlignment = true; 4023 4024 ZeroLengthBitfieldBoundary = 0; 4025 4026 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4027 // so set preferred for small types to 32. 4028 if (T.isOSBinFormatMachO()) { 4029 DescriptionString = 4030 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4031 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4032 } else if (T.isOSWindows()) { 4033 assert(!BigEndian && "Windows on ARM does not support big endian"); 4034 DescriptionString = "e" 4035 "-m:w" 4036 "-p:32:32" 4037 "-i64:64" 4038 "-v128:64:128" 4039 "-a:0:32" 4040 "-n32" 4041 "-S64"; 4042 } else if (T.isOSNaCl()) { 4043 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4044 DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 4045 } else { 4046 DescriptionString = 4047 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4048 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4049 } 4050 4051 // FIXME: Enumerated types are variable width in straight AAPCS. 4052 } 4053 4054 void setABIAPCS() { 4055 const llvm::Triple &T = getTriple(); 4056 4057 IsAAPCS = false; 4058 4059 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4060 4061 // size_t is unsigned int on FreeBSD. 4062 if (T.getOS() == llvm::Triple::FreeBSD) 4063 SizeType = UnsignedInt; 4064 else 4065 SizeType = UnsignedLong; 4066 4067 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4068 WCharType = SignedInt; 4069 4070 // Do not respect the alignment of bit-field types when laying out 4071 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4072 UseBitFieldTypeAlignment = false; 4073 4074 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4075 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4076 /// gcc. 4077 ZeroLengthBitfieldBoundary = 32; 4078 4079 if (T.isOSBinFormatMachO()) 4080 DescriptionString = 4081 BigEndian 4082 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4083 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4084 else 4085 DescriptionString = 4086 BigEndian 4087 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4088 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4089 4090 // FIXME: Override "preferred align" for double and long long. 4091 } 4092 4093 public: 4094 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4095 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 4096 IsAAPCS(true), HW_FP(0) { 4097 BigEndian = IsBigEndian; 4098 4099 switch (getTriple().getOS()) { 4100 case llvm::Triple::NetBSD: 4101 PtrDiffType = SignedLong; 4102 break; 4103 default: 4104 PtrDiffType = SignedInt; 4105 break; 4106 } 4107 4108 // {} in inline assembly are neon specifiers, not assembly variant 4109 // specifiers. 4110 NoAsmVariants = true; 4111 4112 // FIXME: Should we just treat this as a feature? 4113 IsThumb = getTriple().getArchName().startswith("thumb"); 4114 4115 // FIXME: This duplicates code from the driver that sets the -target-abi 4116 // option - this code is used if -target-abi isn't passed and should 4117 // be unified in some way. 4118 if (Triple.isOSBinFormatMachO()) { 4119 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4120 // the frontend matches that. 4121 if (Triple.getEnvironment() == llvm::Triple::EABI || 4122 Triple.getOS() == llvm::Triple::UnknownOS || 4123 StringRef(CPU).startswith("cortex-m")) { 4124 setABI("aapcs"); 4125 } else { 4126 setABI("apcs-gnu"); 4127 } 4128 } else if (Triple.isOSWindows()) { 4129 // FIXME: this is invalid for WindowsCE 4130 setABI("aapcs"); 4131 } else { 4132 // Select the default based on the platform. 4133 switch (Triple.getEnvironment()) { 4134 case llvm::Triple::Android: 4135 case llvm::Triple::GNUEABI: 4136 case llvm::Triple::GNUEABIHF: 4137 setABI("aapcs-linux"); 4138 break; 4139 case llvm::Triple::EABIHF: 4140 case llvm::Triple::EABI: 4141 setABI("aapcs"); 4142 break; 4143 case llvm::Triple::GNU: 4144 setABI("apcs-gnu"); 4145 break; 4146 default: 4147 if (Triple.getOS() == llvm::Triple::NetBSD) 4148 setABI("apcs-gnu"); 4149 else 4150 setABI("aapcs"); 4151 break; 4152 } 4153 } 4154 4155 // ARM targets default to using the ARM C++ ABI. 4156 TheCXXABI.set(TargetCXXABI::GenericARM); 4157 4158 // ARM has atomics up to 8 bytes 4159 MaxAtomicPromoteWidth = 64; 4160 if (shouldUseInlineAtomic(getTriple())) 4161 MaxAtomicInlineWidth = 64; 4162 4163 // Do force alignment of members that follow zero length bitfields. If 4164 // the alignment of the zero-length bitfield is greater than the member 4165 // that follows it, `bar', `bar' will be aligned as the type of the 4166 // zero length bitfield. 4167 UseZeroLengthBitfieldAlignment = true; 4168 } 4169 StringRef getABI() const override { return ABI; } 4170 bool setABI(const std::string &Name) override { 4171 ABI = Name; 4172 4173 // The defaults (above) are for AAPCS, check if we need to change them. 4174 // 4175 // FIXME: We need support for -meabi... we could just mangle it into the 4176 // name. 4177 if (Name == "apcs-gnu") { 4178 setABIAPCS(); 4179 return true; 4180 } 4181 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4182 setABIAAPCS(); 4183 return true; 4184 } 4185 return false; 4186 } 4187 4188 // FIXME: This should be based on Arch attributes, not CPU names. 4189 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 4190 StringRef ArchName = getTriple().getArchName(); 4191 unsigned ArchKind = 4192 llvm::ARMTargetParser::parseArch( 4193 llvm::ARMTargetParser::getCanonicalArchName(ArchName)); 4194 bool IsV8 = (ArchKind == llvm::ARM::AK_ARMV8A || 4195 ArchKind == llvm::ARM::AK_ARMV8_1A); 4196 4197 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 4198 Features["vfp2"] = true; 4199 else if (CPU == "cortex-a8" || CPU == "cortex-a9") { 4200 Features["vfp3"] = true; 4201 Features["neon"] = true; 4202 } 4203 else if (CPU == "cortex-a5") { 4204 Features["vfp4"] = true; 4205 Features["neon"] = true; 4206 } else if (CPU == "swift" || CPU == "cortex-a7" || 4207 CPU == "cortex-a12" || CPU == "cortex-a15" || 4208 CPU == "cortex-a17" || CPU == "krait") { 4209 Features["vfp4"] = true; 4210 Features["neon"] = true; 4211 Features["hwdiv"] = true; 4212 Features["hwdiv-arm"] = true; 4213 } else if (CPU == "cyclone" || CPU == "cortex-a53" || CPU == "cortex-a57" || 4214 CPU == "cortex-a72") { 4215 Features["fp-armv8"] = true; 4216 Features["neon"] = true; 4217 Features["hwdiv"] = true; 4218 Features["hwdiv-arm"] = true; 4219 Features["crc"] = true; 4220 Features["crypto"] = true; 4221 } else if (CPU == "cortex-r5" || CPU == "cortex-r7" || IsV8) { 4222 Features["hwdiv"] = true; 4223 Features["hwdiv-arm"] = true; 4224 } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" || 4225 CPU == "sc300" || CPU == "cortex-r4" || CPU == "cortex-r4f") { 4226 Features["hwdiv"] = true; 4227 } 4228 } 4229 4230 bool handleTargetFeatures(std::vector<std::string> &Features, 4231 DiagnosticsEngine &Diags) override { 4232 FPU = 0; 4233 CRC = 0; 4234 Crypto = 0; 4235 SoftFloat = SoftFloatABI = false; 4236 HWDiv = 0; 4237 4238 for (const auto &Feature : Features) { 4239 if (Feature == "+soft-float") { 4240 SoftFloat = true; 4241 } else if (Feature == "+soft-float-abi") { 4242 SoftFloatABI = true; 4243 } else if (Feature == "+vfp2") { 4244 FPU |= VFP2FPU; 4245 HW_FP = HW_FP_SP | HW_FP_DP; 4246 } else if (Feature == "+vfp3") { 4247 FPU |= VFP3FPU; 4248 HW_FP = HW_FP_SP | HW_FP_DP; 4249 } else if (Feature == "+vfp4") { 4250 FPU |= VFP4FPU; 4251 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP; 4252 } else if (Feature == "+fp-armv8") { 4253 FPU |= FPARMV8; 4254 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP; 4255 } else if (Feature == "+neon") { 4256 FPU |= NeonFPU; 4257 HW_FP = HW_FP_SP | HW_FP_DP; 4258 } else if (Feature == "+hwdiv") { 4259 HWDiv |= HWDivThumb; 4260 } else if (Feature == "+hwdiv-arm") { 4261 HWDiv |= HWDivARM; 4262 } else if (Feature == "+crc") { 4263 CRC = 1; 4264 } else if (Feature == "+crypto") { 4265 Crypto = 1; 4266 } else if (Feature == "+fp-only-sp") { 4267 HW_FP &= ~HW_FP_DP; 4268 } 4269 } 4270 4271 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4272 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4273 return false; 4274 } 4275 4276 if (FPMath == FP_Neon) 4277 Features.push_back("+neonfp"); 4278 else if (FPMath == FP_VFP) 4279 Features.push_back("-neonfp"); 4280 4281 // Remove front-end specific options which the backend handles differently. 4282 auto Feature = 4283 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4284 if (Feature != Features.end()) 4285 Features.erase(Feature); 4286 4287 return true; 4288 } 4289 4290 bool hasFeature(StringRef Feature) const override { 4291 return llvm::StringSwitch<bool>(Feature) 4292 .Case("arm", true) 4293 .Case("softfloat", SoftFloat) 4294 .Case("thumb", IsThumb) 4295 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4296 .Case("hwdiv", HWDiv & HWDivThumb) 4297 .Case("hwdiv-arm", HWDiv & HWDivARM) 4298 .Default(false); 4299 } 4300 const char *getCPUDefineSuffix(StringRef Name) const { 4301 if(Name == "generic") { 4302 auto subarch = getTriple().getSubArch(); 4303 switch (subarch) { 4304 case llvm::Triple::SubArchType::ARMSubArch_v8_1a: 4305 return "8_1A"; 4306 default: 4307 break; 4308 } 4309 } 4310 4311 unsigned ArchKind = llvm::ARMTargetParser::parseCPUArch(Name); 4312 if (ArchKind == llvm::ARM::AK_INVALID) 4313 return ""; 4314 4315 // For most sub-arches, the build attribute CPU name is enough. 4316 // For Cortex variants, it's slightly different. 4317 switch(ArchKind) { 4318 default: 4319 return llvm::ARMTargetParser::getCPUAttr(ArchKind); 4320 case llvm::ARM::AK_ARMV6M: 4321 case llvm::ARM::AK_ARMV6SM: 4322 return "6M"; 4323 case llvm::ARM::AK_ARMV7: 4324 case llvm::ARM::AK_ARMV7A: 4325 case llvm::ARM::AK_ARMV7S: 4326 return "7A"; 4327 case llvm::ARM::AK_ARMV7R: 4328 return "7R"; 4329 case llvm::ARM::AK_ARMV7M: 4330 return "7M"; 4331 case llvm::ARM::AK_ARMV7EM: 4332 return "7EM"; 4333 case llvm::ARM::AK_ARMV8A: 4334 return "8A"; 4335 case llvm::ARM::AK_ARMV8_1A: 4336 return "8_1A"; 4337 } 4338 } 4339 const char *getCPUProfile(StringRef Name) const { 4340 if(Name == "generic") { 4341 auto subarch = getTriple().getSubArch(); 4342 switch (subarch) { 4343 case llvm::Triple::SubArchType::ARMSubArch_v8_1a: 4344 return "A"; 4345 default: 4346 break; 4347 } 4348 } 4349 4350 unsigned CPUArch = llvm::ARMTargetParser::parseCPUArch(Name); 4351 if (CPUArch == llvm::ARM::AK_INVALID) 4352 return ""; 4353 4354 StringRef ArchName = llvm::ARMTargetParser::getArchName(CPUArch); 4355 switch(llvm::ARMTargetParser::parseArchProfile(ArchName)) { 4356 case llvm::ARM::PK_A: 4357 return "A"; 4358 case llvm::ARM::PK_R: 4359 return "R"; 4360 case llvm::ARM::PK_M: 4361 return "M"; 4362 default: 4363 return ""; 4364 } 4365 } 4366 bool setCPU(const std::string &Name) override { 4367 if (!getCPUDefineSuffix(Name)) 4368 return false; 4369 4370 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4371 StringRef Profile = getCPUProfile(Name); 4372 if (Profile == "M" && MaxAtomicInlineWidth) { 4373 MaxAtomicPromoteWidth = 32; 4374 MaxAtomicInlineWidth = 32; 4375 } 4376 4377 CPU = Name; 4378 return true; 4379 } 4380 bool setFPMath(StringRef Name) override; 4381 bool supportsThumb(StringRef ArchName, StringRef CPUArch, 4382 unsigned CPUArchVer) const { 4383 return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) || 4384 (CPUArch.find('M') != StringRef::npos); 4385 } 4386 bool supportsThumb2(StringRef ArchName, StringRef CPUArch, 4387 unsigned CPUArchVer) const { 4388 // We check both CPUArchVer and ArchName because when only triple is 4389 // specified, the default CPU is arm1136j-s. 4390 return ArchName.endswith("v6t2") || ArchName.endswith("v7") || 4391 ArchName.endswith("v8.1a") || 4392 ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7; 4393 } 4394 void getTargetDefines(const LangOptions &Opts, 4395 MacroBuilder &Builder) const override { 4396 // Target identification. 4397 Builder.defineMacro("__arm"); 4398 Builder.defineMacro("__arm__"); 4399 4400 // Target properties. 4401 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4402 4403 StringRef CPUArch = getCPUDefineSuffix(CPU); 4404 unsigned int CPUArchVer; 4405 if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) 4406 llvm_unreachable("Invalid char for architecture version number"); 4407 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 4408 4409 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4410 StringRef CPUProfile = getCPUProfile(CPU); 4411 StringRef ArchName = getTriple().getArchName(); 4412 4413 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4414 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 4415 if (CPUArch[0] >= '8') { 4416 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4417 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4418 } 4419 4420 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4421 // is not defined for the M-profile. 4422 // NOTE that the deffault profile is assumed to be 'A' 4423 if (CPUProfile.empty() || CPUProfile != "M") 4424 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4425 4426 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4427 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4428 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4429 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4430 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4431 else if (supportsThumb(ArchName, CPUArch, CPUArchVer)) 4432 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4433 4434 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4435 // instruction set such as ARM or Thumb. 4436 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4437 4438 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4439 4440 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4441 if (!CPUProfile.empty()) 4442 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4443 4444 // ACLE 6.5.1 Hardware Floating Point 4445 if (HW_FP) 4446 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4447 4448 // ACLE predefines. 4449 Builder.defineMacro("__ARM_ACLE", "200"); 4450 4451 // Subtarget options. 4452 4453 // FIXME: It's more complicated than this and we don't really support 4454 // interworking. 4455 // Windows on ARM does not "support" interworking 4456 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows()) 4457 Builder.defineMacro("__THUMB_INTERWORK__"); 4458 4459 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4460 // Embedded targets on Darwin follow AAPCS, but not EABI. 4461 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4462 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4463 Builder.defineMacro("__ARM_EABI__"); 4464 Builder.defineMacro("__ARM_PCS", "1"); 4465 4466 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4467 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4468 } 4469 4470 if (SoftFloat) 4471 Builder.defineMacro("__SOFTFP__"); 4472 4473 if (CPU == "xscale") 4474 Builder.defineMacro("__XSCALE__"); 4475 4476 if (IsThumb) { 4477 Builder.defineMacro("__THUMBEL__"); 4478 Builder.defineMacro("__thumb__"); 4479 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4480 Builder.defineMacro("__thumb2__"); 4481 } 4482 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 4483 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4484 4485 // Note, this is always on in gcc, even though it doesn't make sense. 4486 Builder.defineMacro("__APCS_32__"); 4487 4488 if (FPUModeIsVFP((FPUMode) FPU)) { 4489 Builder.defineMacro("__VFP_FP__"); 4490 if (FPU & VFP2FPU) 4491 Builder.defineMacro("__ARM_VFPV2__"); 4492 if (FPU & VFP3FPU) 4493 Builder.defineMacro("__ARM_VFPV3__"); 4494 if (FPU & VFP4FPU) 4495 Builder.defineMacro("__ARM_VFPV4__"); 4496 } 4497 4498 // This only gets set when Neon instructions are actually available, unlike 4499 // the VFP define, hence the soft float and arch check. This is subtly 4500 // different from gcc, we follow the intent which was that it should be set 4501 // when Neon instructions are actually available. 4502 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) { 4503 Builder.defineMacro("__ARM_NEON"); 4504 Builder.defineMacro("__ARM_NEON__"); 4505 } 4506 4507 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4508 Opts.ShortWChar ? "2" : "4"); 4509 4510 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4511 Opts.ShortEnums ? "1" : "4"); 4512 4513 if (CRC) 4514 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4515 4516 if (Crypto) 4517 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4518 4519 if (CPUArchVer >= 6 && CPUArch != "6M") { 4520 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4521 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4522 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4523 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4524 } 4525 4526 bool is5EOrAbove = (CPUArchVer >= 6 || 4527 (CPUArchVer == 5 && 4528 CPUArch.find('E') != StringRef::npos)); 4529 bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer)); 4530 if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch == "7EM")) 4531 Builder.defineMacro("__ARM_FEATURE_DSP"); 4532 } 4533 void getTargetBuiltins(const Builtin::Info *&Records, 4534 unsigned &NumRecords) const override { 4535 Records = BuiltinInfo; 4536 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4537 } 4538 bool isCLZForZeroUndef() const override { return false; } 4539 BuiltinVaListKind getBuiltinVaListKind() const override { 4540 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4541 } 4542 void getGCCRegNames(const char * const *&Names, 4543 unsigned &NumNames) const override; 4544 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4545 unsigned &NumAliases) const override; 4546 bool validateAsmConstraint(const char *&Name, 4547 TargetInfo::ConstraintInfo &Info) const override { 4548 switch (*Name) { 4549 default: break; 4550 case 'l': // r0-r7 4551 case 'h': // r8-r15 4552 case 'w': // VFP Floating point register single precision 4553 case 'P': // VFP Floating point register double precision 4554 Info.setAllowsRegister(); 4555 return true; 4556 case 'I': 4557 case 'J': 4558 case 'K': 4559 case 'L': 4560 case 'M': 4561 // FIXME 4562 return true; 4563 case 'Q': // A memory address that is a single base register. 4564 Info.setAllowsMemory(); 4565 return true; 4566 case 'U': // a memory reference... 4567 switch (Name[1]) { 4568 case 'q': // ...ARMV4 ldrsb 4569 case 'v': // ...VFP load/store (reg+constant offset) 4570 case 'y': // ...iWMMXt load/store 4571 case 't': // address valid for load/store opaque types wider 4572 // than 128-bits 4573 case 'n': // valid address for Neon doubleword vector load/store 4574 case 'm': // valid address for Neon element and structure load/store 4575 case 's': // valid address for non-offset loads/stores of quad-word 4576 // values in four ARM registers 4577 Info.setAllowsMemory(); 4578 Name++; 4579 return true; 4580 } 4581 } 4582 return false; 4583 } 4584 std::string convertConstraint(const char *&Constraint) const override { 4585 std::string R; 4586 switch (*Constraint) { 4587 case 'U': // Two-character constraint; add "^" hint for later parsing. 4588 R = std::string("^") + std::string(Constraint, 2); 4589 Constraint++; 4590 break; 4591 case 'p': // 'p' should be translated to 'r' by default. 4592 R = std::string("r"); 4593 break; 4594 default: 4595 return std::string(1, *Constraint); 4596 } 4597 return R; 4598 } 4599 bool 4600 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4601 std::string &SuggestedModifier) const override { 4602 bool isOutput = (Constraint[0] == '='); 4603 bool isInOut = (Constraint[0] == '+'); 4604 4605 // Strip off constraint modifiers. 4606 while (Constraint[0] == '=' || 4607 Constraint[0] == '+' || 4608 Constraint[0] == '&') 4609 Constraint = Constraint.substr(1); 4610 4611 switch (Constraint[0]) { 4612 default: break; 4613 case 'r': { 4614 switch (Modifier) { 4615 default: 4616 return (isInOut || isOutput || Size <= 64); 4617 case 'q': 4618 // A register of size 32 cannot fit a vector type. 4619 return false; 4620 } 4621 } 4622 } 4623 4624 return true; 4625 } 4626 const char *getClobbers() const override { 4627 // FIXME: Is this really right? 4628 return ""; 4629 } 4630 4631 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4632 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4633 } 4634 4635 int getEHDataRegisterNumber(unsigned RegNo) const override { 4636 if (RegNo == 0) return 0; 4637 if (RegNo == 1) return 1; 4638 return -1; 4639 } 4640 }; 4641 4642 bool ARMTargetInfo::setFPMath(StringRef Name) { 4643 if (Name == "neon") { 4644 FPMath = FP_Neon; 4645 return true; 4646 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4647 Name == "vfp4") { 4648 FPMath = FP_VFP; 4649 return true; 4650 } 4651 return false; 4652 } 4653 4654 const char * const ARMTargetInfo::GCCRegNames[] = { 4655 // Integer registers 4656 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4657 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4658 4659 // Float registers 4660 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4661 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4662 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4663 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4664 4665 // Double registers 4666 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4667 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4668 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4669 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4670 4671 // Quad registers 4672 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4673 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4674 }; 4675 4676 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4677 unsigned &NumNames) const { 4678 Names = GCCRegNames; 4679 NumNames = llvm::array_lengthof(GCCRegNames); 4680 } 4681 4682 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4683 { { "a1" }, "r0" }, 4684 { { "a2" }, "r1" }, 4685 { { "a3" }, "r2" }, 4686 { { "a4" }, "r3" }, 4687 { { "v1" }, "r4" }, 4688 { { "v2" }, "r5" }, 4689 { { "v3" }, "r6" }, 4690 { { "v4" }, "r7" }, 4691 { { "v5" }, "r8" }, 4692 { { "v6", "rfp" }, "r9" }, 4693 { { "sl" }, "r10" }, 4694 { { "fp" }, "r11" }, 4695 { { "ip" }, "r12" }, 4696 { { "r13" }, "sp" }, 4697 { { "r14" }, "lr" }, 4698 { { "r15" }, "pc" }, 4699 // The S, D and Q registers overlap, but aren't really aliases; we 4700 // don't want to substitute one of these for a different-sized one. 4701 }; 4702 4703 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4704 unsigned &NumAliases) const { 4705 Aliases = GCCRegAliases; 4706 NumAliases = llvm::array_lengthof(GCCRegAliases); 4707 } 4708 4709 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4710 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4711 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4712 ALL_LANGUAGES }, 4713 #include "clang/Basic/BuiltinsNEON.def" 4714 4715 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4716 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG }, 4717 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4718 ALL_LANGUAGES }, 4719 #include "clang/Basic/BuiltinsARM.def" 4720 }; 4721 4722 class ARMleTargetInfo : public ARMTargetInfo { 4723 public: 4724 ARMleTargetInfo(const llvm::Triple &Triple) 4725 : ARMTargetInfo(Triple, false) { } 4726 void getTargetDefines(const LangOptions &Opts, 4727 MacroBuilder &Builder) const override { 4728 Builder.defineMacro("__ARMEL__"); 4729 ARMTargetInfo::getTargetDefines(Opts, Builder); 4730 } 4731 }; 4732 4733 class ARMbeTargetInfo : public ARMTargetInfo { 4734 public: 4735 ARMbeTargetInfo(const llvm::Triple &Triple) 4736 : ARMTargetInfo(Triple, true) { } 4737 void getTargetDefines(const LangOptions &Opts, 4738 MacroBuilder &Builder) const override { 4739 Builder.defineMacro("__ARMEB__"); 4740 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4741 ARMTargetInfo::getTargetDefines(Opts, Builder); 4742 } 4743 }; 4744 4745 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 4746 const llvm::Triple Triple; 4747 public: 4748 WindowsARMTargetInfo(const llvm::Triple &Triple) 4749 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 4750 TLSSupported = false; 4751 WCharType = UnsignedShort; 4752 SizeType = UnsignedInt; 4753 UserLabelPrefix = ""; 4754 } 4755 void getVisualStudioDefines(const LangOptions &Opts, 4756 MacroBuilder &Builder) const { 4757 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 4758 4759 // FIXME: this is invalid for WindowsCE 4760 Builder.defineMacro("_M_ARM_NT", "1"); 4761 Builder.defineMacro("_M_ARMT", "_M_ARM"); 4762 Builder.defineMacro("_M_THUMB", "_M_ARM"); 4763 4764 assert((Triple.getArch() == llvm::Triple::arm || 4765 Triple.getArch() == llvm::Triple::thumb) && 4766 "invalid architecture for Windows ARM target info"); 4767 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 4768 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 4769 4770 // TODO map the complete set of values 4771 // 31: VFPv3 40: VFPv4 4772 Builder.defineMacro("_M_ARM_FP", "31"); 4773 } 4774 BuiltinVaListKind getBuiltinVaListKind() const override { 4775 return TargetInfo::CharPtrBuiltinVaList; 4776 } 4777 }; 4778 4779 // Windows ARM + Itanium C++ ABI Target 4780 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 4781 public: 4782 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 4783 : WindowsARMTargetInfo(Triple) { 4784 TheCXXABI.set(TargetCXXABI::GenericARM); 4785 } 4786 4787 void getTargetDefines(const LangOptions &Opts, 4788 MacroBuilder &Builder) const override { 4789 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4790 4791 if (Opts.MSVCCompat) 4792 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4793 } 4794 }; 4795 4796 // Windows ARM, MS (C++) ABI 4797 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 4798 public: 4799 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 4800 : WindowsARMTargetInfo(Triple) { 4801 TheCXXABI.set(TargetCXXABI::Microsoft); 4802 } 4803 4804 void getTargetDefines(const LangOptions &Opts, 4805 MacroBuilder &Builder) const override { 4806 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4807 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4808 } 4809 }; 4810 4811 class DarwinARMTargetInfo : 4812 public DarwinTargetInfo<ARMleTargetInfo> { 4813 protected: 4814 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4815 MacroBuilder &Builder) const override { 4816 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4817 } 4818 4819 public: 4820 DarwinARMTargetInfo(const llvm::Triple &Triple) 4821 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 4822 HasAlignMac68kSupport = true; 4823 // iOS always has 64-bit atomic instructions. 4824 // FIXME: This should be based off of the target features in 4825 // ARMleTargetInfo. 4826 MaxAtomicInlineWidth = 64; 4827 4828 // Darwin on iOS uses a variant of the ARM C++ ABI. 4829 TheCXXABI.set(TargetCXXABI::iOS); 4830 } 4831 }; 4832 4833 class AArch64TargetInfo : public TargetInfo { 4834 virtual void setDescriptionString() = 0; 4835 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4836 static const char *const GCCRegNames[]; 4837 4838 enum FPUModeEnum { 4839 FPUMode, 4840 NeonMode 4841 }; 4842 4843 unsigned FPU; 4844 unsigned CRC; 4845 unsigned Crypto; 4846 4847 static const Builtin::Info BuiltinInfo[]; 4848 4849 std::string ABI; 4850 4851 public: 4852 AArch64TargetInfo(const llvm::Triple &Triple) 4853 : TargetInfo(Triple), ABI("aapcs") { 4854 4855 if (getTriple().getOS() == llvm::Triple::NetBSD) { 4856 WCharType = SignedInt; 4857 4858 // NetBSD apparently prefers consistency across ARM targets to consistency 4859 // across 64-bit targets. 4860 Int64Type = SignedLongLong; 4861 IntMaxType = SignedLongLong; 4862 } else { 4863 WCharType = UnsignedInt; 4864 Int64Type = SignedLong; 4865 IntMaxType = SignedLong; 4866 } 4867 4868 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4869 MaxVectorAlign = 128; 4870 RegParmMax = 8; 4871 MaxAtomicInlineWidth = 128; 4872 MaxAtomicPromoteWidth = 128; 4873 4874 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 4875 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4876 4877 // {} in inline assembly are neon specifiers, not assembly variant 4878 // specifiers. 4879 NoAsmVariants = true; 4880 4881 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 4882 // contributes to the alignment of the containing aggregate in the same way 4883 // a plain (non bit-field) member of that type would, without exception for 4884 // zero-sized or anonymous bit-fields." 4885 UseBitFieldTypeAlignment = true; 4886 UseZeroLengthBitfieldAlignment = true; 4887 4888 // AArch64 targets default to using the ARM C++ ABI. 4889 TheCXXABI.set(TargetCXXABI::GenericAArch64); 4890 } 4891 4892 StringRef getABI() const override { return ABI; } 4893 bool setABI(const std::string &Name) override { 4894 if (Name != "aapcs" && Name != "darwinpcs") 4895 return false; 4896 4897 ABI = Name; 4898 return true; 4899 } 4900 4901 bool setCPU(const std::string &Name) override { 4902 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4903 .Case("generic", true) 4904 .Cases("cortex-a53", "cortex-a57", "cortex-a72", true) 4905 .Case("cyclone", true) 4906 .Default(false); 4907 return CPUKnown; 4908 } 4909 4910 void getTargetDefines(const LangOptions &Opts, 4911 MacroBuilder &Builder) const override { 4912 // Target identification. 4913 Builder.defineMacro("__aarch64__"); 4914 4915 // Target properties. 4916 Builder.defineMacro("_LP64"); 4917 Builder.defineMacro("__LP64__"); 4918 4919 // ACLE predefines. Many can only have one possible value on v8 AArch64. 4920 Builder.defineMacro("__ARM_ACLE", "200"); 4921 Builder.defineMacro("__ARM_ARCH", "8"); 4922 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 4923 4924 Builder.defineMacro("__ARM_64BIT_STATE"); 4925 Builder.defineMacro("__ARM_PCS_AAPCS64"); 4926 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 4927 4928 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 4929 Builder.defineMacro("__ARM_FEATURE_CLZ"); 4930 Builder.defineMacro("__ARM_FEATURE_FMA"); 4931 Builder.defineMacro("__ARM_FEATURE_DIV"); 4932 Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE 4933 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 4934 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4935 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4936 4937 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 4938 4939 // 0xe implies support for half, single and double precision operations. 4940 Builder.defineMacro("__ARM_FP", "0xe"); 4941 4942 // PCS specifies this for SysV variants, which is all we support. Other ABIs 4943 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 4944 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 4945 4946 if (Opts.FastMath || Opts.FiniteMathOnly) 4947 Builder.defineMacro("__ARM_FP_FAST"); 4948 4949 if (Opts.C99 && !Opts.Freestanding) 4950 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 4951 4952 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 4953 4954 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4955 Opts.ShortEnums ? "1" : "4"); 4956 4957 if (FPU == NeonMode) { 4958 Builder.defineMacro("__ARM_NEON"); 4959 // 64-bit NEON supports half, single and double precision operations. 4960 Builder.defineMacro("__ARM_NEON_FP", "0xe"); 4961 } 4962 4963 if (CRC) 4964 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4965 4966 if (Crypto) 4967 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4968 4969 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 4970 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4971 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4972 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4973 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4974 } 4975 4976 void getTargetBuiltins(const Builtin::Info *&Records, 4977 unsigned &NumRecords) const override { 4978 Records = BuiltinInfo; 4979 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin; 4980 } 4981 4982 bool hasFeature(StringRef Feature) const override { 4983 return Feature == "aarch64" || 4984 Feature == "arm64" || 4985 (Feature == "neon" && FPU == NeonMode); 4986 } 4987 4988 bool handleTargetFeatures(std::vector<std::string> &Features, 4989 DiagnosticsEngine &Diags) override { 4990 FPU = FPUMode; 4991 CRC = 0; 4992 Crypto = 0; 4993 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 4994 if (Features[i] == "+neon") 4995 FPU = NeonMode; 4996 if (Features[i] == "+crc") 4997 CRC = 1; 4998 if (Features[i] == "+crypto") 4999 Crypto = 1; 5000 } 5001 5002 setDescriptionString(); 5003 5004 return true; 5005 } 5006 5007 bool isCLZForZeroUndef() const override { return false; } 5008 5009 BuiltinVaListKind getBuiltinVaListKind() const override { 5010 return TargetInfo::AArch64ABIBuiltinVaList; 5011 } 5012 5013 void getGCCRegNames(const char *const *&Names, 5014 unsigned &NumNames) const override; 5015 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5016 unsigned &NumAliases) const override; 5017 5018 bool validateAsmConstraint(const char *&Name, 5019 TargetInfo::ConstraintInfo &Info) const override { 5020 switch (*Name) { 5021 default: 5022 return false; 5023 case 'w': // Floating point and SIMD registers (V0-V31) 5024 Info.setAllowsRegister(); 5025 return true; 5026 case 'I': // Constant that can be used with an ADD instruction 5027 case 'J': // Constant that can be used with a SUB instruction 5028 case 'K': // Constant that can be used with a 32-bit logical instruction 5029 case 'L': // Constant that can be used with a 64-bit logical instruction 5030 case 'M': // Constant that can be used as a 32-bit MOV immediate 5031 case 'N': // Constant that can be used as a 64-bit MOV immediate 5032 case 'Y': // Floating point constant zero 5033 case 'Z': // Integer constant zero 5034 return true; 5035 case 'Q': // A memory reference with base register and no offset 5036 Info.setAllowsMemory(); 5037 return true; 5038 case 'S': // A symbolic address 5039 Info.setAllowsRegister(); 5040 return true; 5041 case 'U': 5042 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5043 // Utf: A memory address suitable for ldp/stp in TF mode. 5044 // Usa: An absolute symbolic address. 5045 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5046 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5047 case 'z': // Zero register, wzr or xzr 5048 Info.setAllowsRegister(); 5049 return true; 5050 case 'x': // Floating point and SIMD registers (V0-V15) 5051 Info.setAllowsRegister(); 5052 return true; 5053 } 5054 return false; 5055 } 5056 5057 bool 5058 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5059 std::string &SuggestedModifier) const override { 5060 // Strip off constraint modifiers. 5061 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5062 Constraint = Constraint.substr(1); 5063 5064 switch (Constraint[0]) { 5065 default: 5066 return true; 5067 case 'z': 5068 case 'r': { 5069 switch (Modifier) { 5070 case 'x': 5071 case 'w': 5072 // For now assume that the person knows what they're 5073 // doing with the modifier. 5074 return true; 5075 default: 5076 // By default an 'r' constraint will be in the 'x' 5077 // registers. 5078 if (Size == 64) 5079 return true; 5080 5081 SuggestedModifier = "w"; 5082 return false; 5083 } 5084 } 5085 } 5086 } 5087 5088 const char *getClobbers() const override { return ""; } 5089 5090 int getEHDataRegisterNumber(unsigned RegNo) const override { 5091 if (RegNo == 0) 5092 return 0; 5093 if (RegNo == 1) 5094 return 1; 5095 return -1; 5096 } 5097 }; 5098 5099 const char *const AArch64TargetInfo::GCCRegNames[] = { 5100 // 32-bit Integer registers 5101 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5102 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5103 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5104 5105 // 64-bit Integer registers 5106 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5107 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5108 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5109 5110 // 32-bit floating point regsisters 5111 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5112 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5113 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5114 5115 // 64-bit floating point regsisters 5116 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5117 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5118 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5119 5120 // Vector registers 5121 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5122 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5123 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5124 }; 5125 5126 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names, 5127 unsigned &NumNames) const { 5128 Names = GCCRegNames; 5129 NumNames = llvm::array_lengthof(GCCRegNames); 5130 } 5131 5132 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5133 { { "w31" }, "wsp" }, 5134 { { "x29" }, "fp" }, 5135 { { "x30" }, "lr" }, 5136 { { "x31" }, "sp" }, 5137 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5138 // don't want to substitute one of these for a different-sized one. 5139 }; 5140 5141 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5142 unsigned &NumAliases) const { 5143 Aliases = GCCRegAliases; 5144 NumAliases = llvm::array_lengthof(GCCRegAliases); 5145 } 5146 5147 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5148 #define BUILTIN(ID, TYPE, ATTRS) \ 5149 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5150 #include "clang/Basic/BuiltinsNEON.def" 5151 5152 #define BUILTIN(ID, TYPE, ATTRS) \ 5153 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5154 #include "clang/Basic/BuiltinsAArch64.def" 5155 }; 5156 5157 class AArch64leTargetInfo : public AArch64TargetInfo { 5158 void setDescriptionString() override { 5159 if (getTriple().isOSBinFormatMachO()) 5160 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128"; 5161 else 5162 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 5163 } 5164 5165 public: 5166 AArch64leTargetInfo(const llvm::Triple &Triple) 5167 : AArch64TargetInfo(Triple) { 5168 BigEndian = false; 5169 } 5170 void getTargetDefines(const LangOptions &Opts, 5171 MacroBuilder &Builder) const override { 5172 Builder.defineMacro("__AARCH64EL__"); 5173 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5174 } 5175 }; 5176 5177 class AArch64beTargetInfo : public AArch64TargetInfo { 5178 void setDescriptionString() override { 5179 assert(!getTriple().isOSBinFormatMachO()); 5180 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5181 } 5182 5183 public: 5184 AArch64beTargetInfo(const llvm::Triple &Triple) 5185 : AArch64TargetInfo(Triple) { } 5186 void getTargetDefines(const LangOptions &Opts, 5187 MacroBuilder &Builder) const override { 5188 Builder.defineMacro("__AARCH64EB__"); 5189 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5190 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5191 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5192 } 5193 }; 5194 5195 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5196 protected: 5197 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5198 MacroBuilder &Builder) const override { 5199 Builder.defineMacro("__AARCH64_SIMD__"); 5200 Builder.defineMacro("__ARM64_ARCH_8__"); 5201 Builder.defineMacro("__ARM_NEON__"); 5202 Builder.defineMacro("__LITTLE_ENDIAN__"); 5203 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5204 Builder.defineMacro("__arm64", "1"); 5205 Builder.defineMacro("__arm64__", "1"); 5206 5207 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5208 } 5209 5210 public: 5211 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5212 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5213 Int64Type = SignedLongLong; 5214 WCharType = SignedInt; 5215 UseSignedCharForObjCBool = false; 5216 5217 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5218 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5219 5220 TheCXXABI.set(TargetCXXABI::iOS64); 5221 } 5222 5223 BuiltinVaListKind getBuiltinVaListKind() const override { 5224 return TargetInfo::CharPtrBuiltinVaList; 5225 } 5226 }; 5227 5228 // Hexagon abstract base class 5229 class HexagonTargetInfo : public TargetInfo { 5230 static const Builtin::Info BuiltinInfo[]; 5231 static const char * const GCCRegNames[]; 5232 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5233 std::string CPU; 5234 public: 5235 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5236 BigEndian = false; 5237 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 5238 5239 // {} in inline assembly are packet specifiers, not assembly variant 5240 // specifiers. 5241 NoAsmVariants = true; 5242 } 5243 5244 void getTargetBuiltins(const Builtin::Info *&Records, 5245 unsigned &NumRecords) const override { 5246 Records = BuiltinInfo; 5247 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 5248 } 5249 5250 bool validateAsmConstraint(const char *&Name, 5251 TargetInfo::ConstraintInfo &Info) const override { 5252 return true; 5253 } 5254 5255 void getTargetDefines(const LangOptions &Opts, 5256 MacroBuilder &Builder) const override; 5257 5258 bool hasFeature(StringRef Feature) const override { 5259 return Feature == "hexagon"; 5260 } 5261 5262 BuiltinVaListKind getBuiltinVaListKind() const override { 5263 return TargetInfo::CharPtrBuiltinVaList; 5264 } 5265 void getGCCRegNames(const char * const *&Names, 5266 unsigned &NumNames) const override; 5267 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5268 unsigned &NumAliases) const override; 5269 const char *getClobbers() const override { 5270 return ""; 5271 } 5272 5273 static const char *getHexagonCPUSuffix(StringRef Name) { 5274 return llvm::StringSwitch<const char*>(Name) 5275 .Case("hexagonv4", "4") 5276 .Case("hexagonv5", "5") 5277 .Default(nullptr); 5278 } 5279 5280 bool setCPU(const std::string &Name) override { 5281 if (!getHexagonCPUSuffix(Name)) 5282 return false; 5283 5284 CPU = Name; 5285 return true; 5286 } 5287 }; 5288 5289 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5290 MacroBuilder &Builder) const { 5291 Builder.defineMacro("qdsp6"); 5292 Builder.defineMacro("__qdsp6", "1"); 5293 Builder.defineMacro("__qdsp6__", "1"); 5294 5295 Builder.defineMacro("hexagon"); 5296 Builder.defineMacro("__hexagon", "1"); 5297 Builder.defineMacro("__hexagon__", "1"); 5298 5299 if(CPU == "hexagonv1") { 5300 Builder.defineMacro("__HEXAGON_V1__"); 5301 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 5302 if(Opts.HexagonQdsp6Compat) { 5303 Builder.defineMacro("__QDSP6_V1__"); 5304 Builder.defineMacro("__QDSP6_ARCH__", "1"); 5305 } 5306 } 5307 else if(CPU == "hexagonv2") { 5308 Builder.defineMacro("__HEXAGON_V2__"); 5309 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 5310 if(Opts.HexagonQdsp6Compat) { 5311 Builder.defineMacro("__QDSP6_V2__"); 5312 Builder.defineMacro("__QDSP6_ARCH__", "2"); 5313 } 5314 } 5315 else if(CPU == "hexagonv3") { 5316 Builder.defineMacro("__HEXAGON_V3__"); 5317 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 5318 if(Opts.HexagonQdsp6Compat) { 5319 Builder.defineMacro("__QDSP6_V3__"); 5320 Builder.defineMacro("__QDSP6_ARCH__", "3"); 5321 } 5322 } 5323 else if(CPU == "hexagonv4") { 5324 Builder.defineMacro("__HEXAGON_V4__"); 5325 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5326 if(Opts.HexagonQdsp6Compat) { 5327 Builder.defineMacro("__QDSP6_V4__"); 5328 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5329 } 5330 } 5331 else if(CPU == "hexagonv5") { 5332 Builder.defineMacro("__HEXAGON_V5__"); 5333 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5334 if(Opts.HexagonQdsp6Compat) { 5335 Builder.defineMacro("__QDSP6_V5__"); 5336 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5337 } 5338 } 5339 } 5340 5341 const char * const HexagonTargetInfo::GCCRegNames[] = { 5342 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5343 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5344 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5345 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5346 "p0", "p1", "p2", "p3", 5347 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5348 }; 5349 5350 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 5351 unsigned &NumNames) const { 5352 Names = GCCRegNames; 5353 NumNames = llvm::array_lengthof(GCCRegNames); 5354 } 5355 5356 5357 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5358 { { "sp" }, "r29" }, 5359 { { "fp" }, "r30" }, 5360 { { "lr" }, "r31" }, 5361 }; 5362 5363 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5364 unsigned &NumAliases) const { 5365 Aliases = GCCRegAliases; 5366 NumAliases = llvm::array_lengthof(GCCRegAliases); 5367 } 5368 5369 5370 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5371 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5372 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5373 ALL_LANGUAGES }, 5374 #include "clang/Basic/BuiltinsHexagon.def" 5375 }; 5376 5377 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5378 class SparcTargetInfo : public TargetInfo { 5379 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5380 static const char * const GCCRegNames[]; 5381 bool SoftFloat; 5382 public: 5383 SparcTargetInfo(const llvm::Triple &Triple) 5384 : TargetInfo(Triple), SoftFloat(false) {} 5385 5386 bool handleTargetFeatures(std::vector<std::string> &Features, 5387 DiagnosticsEngine &Diags) override { 5388 // The backend doesn't actually handle soft float yet, but in case someone 5389 // is using the support for the front end continue to support it. 5390 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 5391 if (Feature != Features.end()) { 5392 SoftFloat = true; 5393 Features.erase(Feature); 5394 } 5395 return true; 5396 } 5397 void getTargetDefines(const LangOptions &Opts, 5398 MacroBuilder &Builder) const override { 5399 DefineStd(Builder, "sparc", Opts); 5400 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5401 5402 if (SoftFloat) 5403 Builder.defineMacro("SOFT_FLOAT", "1"); 5404 } 5405 5406 bool hasFeature(StringRef Feature) const override { 5407 return llvm::StringSwitch<bool>(Feature) 5408 .Case("softfloat", SoftFloat) 5409 .Case("sparc", true) 5410 .Default(false); 5411 } 5412 5413 void getTargetBuiltins(const Builtin::Info *&Records, 5414 unsigned &NumRecords) const override { 5415 // FIXME: Implement! 5416 } 5417 BuiltinVaListKind getBuiltinVaListKind() const override { 5418 return TargetInfo::VoidPtrBuiltinVaList; 5419 } 5420 void getGCCRegNames(const char * const *&Names, 5421 unsigned &NumNames) const override; 5422 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5423 unsigned &NumAliases) const override; 5424 bool validateAsmConstraint(const char *&Name, 5425 TargetInfo::ConstraintInfo &info) const override { 5426 // FIXME: Implement! 5427 switch (*Name) { 5428 case 'I': // Signed 13-bit constant 5429 case 'J': // Zero 5430 case 'K': // 32-bit constant with the low 12 bits clear 5431 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5432 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5433 case 'N': // Same as 'K' but zext (required for SIMode) 5434 case 'O': // The constant 4096 5435 return true; 5436 } 5437 return false; 5438 } 5439 const char *getClobbers() const override { 5440 // FIXME: Implement! 5441 return ""; 5442 } 5443 }; 5444 5445 const char * const SparcTargetInfo::GCCRegNames[] = { 5446 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5447 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5448 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5449 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5450 }; 5451 5452 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 5453 unsigned &NumNames) const { 5454 Names = GCCRegNames; 5455 NumNames = llvm::array_lengthof(GCCRegNames); 5456 } 5457 5458 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5459 { { "g0" }, "r0" }, 5460 { { "g1" }, "r1" }, 5461 { { "g2" }, "r2" }, 5462 { { "g3" }, "r3" }, 5463 { { "g4" }, "r4" }, 5464 { { "g5" }, "r5" }, 5465 { { "g6" }, "r6" }, 5466 { { "g7" }, "r7" }, 5467 { { "o0" }, "r8" }, 5468 { { "o1" }, "r9" }, 5469 { { "o2" }, "r10" }, 5470 { { "o3" }, "r11" }, 5471 { { "o4" }, "r12" }, 5472 { { "o5" }, "r13" }, 5473 { { "o6", "sp" }, "r14" }, 5474 { { "o7" }, "r15" }, 5475 { { "l0" }, "r16" }, 5476 { { "l1" }, "r17" }, 5477 { { "l2" }, "r18" }, 5478 { { "l3" }, "r19" }, 5479 { { "l4" }, "r20" }, 5480 { { "l5" }, "r21" }, 5481 { { "l6" }, "r22" }, 5482 { { "l7" }, "r23" }, 5483 { { "i0" }, "r24" }, 5484 { { "i1" }, "r25" }, 5485 { { "i2" }, "r26" }, 5486 { { "i3" }, "r27" }, 5487 { { "i4" }, "r28" }, 5488 { { "i5" }, "r29" }, 5489 { { "i6", "fp" }, "r30" }, 5490 { { "i7" }, "r31" }, 5491 }; 5492 5493 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5494 unsigned &NumAliases) const { 5495 Aliases = GCCRegAliases; 5496 NumAliases = llvm::array_lengthof(GCCRegAliases); 5497 } 5498 5499 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5500 class SparcV8TargetInfo : public SparcTargetInfo { 5501 public: 5502 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5503 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5504 } 5505 5506 void getTargetDefines(const LangOptions &Opts, 5507 MacroBuilder &Builder) const override { 5508 SparcTargetInfo::getTargetDefines(Opts, Builder); 5509 Builder.defineMacro("__sparcv8"); 5510 } 5511 }; 5512 5513 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 5514 class SparcV8elTargetInfo : public SparcV8TargetInfo { 5515 public: 5516 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 5517 DescriptionString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5518 BigEndian = false; 5519 } 5520 }; 5521 5522 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 5523 class SparcV9TargetInfo : public SparcTargetInfo { 5524 public: 5525 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5526 // FIXME: Support Sparc quad-precision long double? 5527 DescriptionString = "E-m:e-i64:64-n32:64-S128"; 5528 // This is an LP64 platform. 5529 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5530 5531 // OpenBSD uses long long for int64_t and intmax_t. 5532 if (getTriple().getOS() == llvm::Triple::OpenBSD) 5533 IntMaxType = SignedLongLong; 5534 else 5535 IntMaxType = SignedLong; 5536 Int64Type = IntMaxType; 5537 5538 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 5539 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 5540 LongDoubleWidth = 128; 5541 LongDoubleAlign = 128; 5542 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5543 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5544 } 5545 5546 void getTargetDefines(const LangOptions &Opts, 5547 MacroBuilder &Builder) const override { 5548 SparcTargetInfo::getTargetDefines(Opts, Builder); 5549 Builder.defineMacro("__sparcv9"); 5550 Builder.defineMacro("__arch64__"); 5551 // Solaris doesn't need these variants, but the BSDs do. 5552 if (getTriple().getOS() != llvm::Triple::Solaris) { 5553 Builder.defineMacro("__sparc64__"); 5554 Builder.defineMacro("__sparc_v9__"); 5555 Builder.defineMacro("__sparcv9__"); 5556 } 5557 } 5558 5559 bool setCPU(const std::string &Name) override { 5560 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5561 .Case("v9", true) 5562 .Case("ultrasparc", true) 5563 .Case("ultrasparc3", true) 5564 .Case("niagara", true) 5565 .Case("niagara2", true) 5566 .Case("niagara3", true) 5567 .Case("niagara4", true) 5568 .Default(false); 5569 5570 // No need to store the CPU yet. There aren't any CPU-specific 5571 // macros to define. 5572 return CPUKnown; 5573 } 5574 }; 5575 5576 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 5577 public: 5578 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 5579 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 5580 SizeType = UnsignedInt; 5581 PtrDiffType = SignedInt; 5582 } 5583 }; 5584 5585 class SystemZTargetInfo : public TargetInfo { 5586 static const Builtin::Info BuiltinInfo[]; 5587 static const char *const GCCRegNames[]; 5588 std::string CPU; 5589 bool HasTransactionalExecution; 5590 bool HasVector; 5591 5592 public: 5593 SystemZTargetInfo(const llvm::Triple &Triple) 5594 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), HasVector(false) { 5595 IntMaxType = SignedLong; 5596 Int64Type = SignedLong; 5597 TLSSupported = true; 5598 IntWidth = IntAlign = 32; 5599 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5600 PointerWidth = PointerAlign = 64; 5601 LongDoubleWidth = 128; 5602 LongDoubleAlign = 64; 5603 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5604 DefaultAlignForAttributeAligned = 64; 5605 MinGlobalAlign = 16; 5606 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5607 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5608 } 5609 void getTargetDefines(const LangOptions &Opts, 5610 MacroBuilder &Builder) const override { 5611 Builder.defineMacro("__s390__"); 5612 Builder.defineMacro("__s390x__"); 5613 Builder.defineMacro("__zarch__"); 5614 Builder.defineMacro("__LONG_DOUBLE_128__"); 5615 if (HasTransactionalExecution) 5616 Builder.defineMacro("__HTM__"); 5617 } 5618 void getTargetBuiltins(const Builtin::Info *&Records, 5619 unsigned &NumRecords) const override { 5620 Records = BuiltinInfo; 5621 NumRecords = clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin; 5622 } 5623 5624 void getGCCRegNames(const char *const *&Names, 5625 unsigned &NumNames) const override; 5626 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5627 unsigned &NumAliases) const override { 5628 // No aliases. 5629 Aliases = nullptr; 5630 NumAliases = 0; 5631 } 5632 bool validateAsmConstraint(const char *&Name, 5633 TargetInfo::ConstraintInfo &info) const override; 5634 const char *getClobbers() const override { 5635 // FIXME: Is this really right? 5636 return ""; 5637 } 5638 BuiltinVaListKind getBuiltinVaListKind() const override { 5639 return TargetInfo::SystemZBuiltinVaList; 5640 } 5641 bool setCPU(const std::string &Name) override { 5642 CPU = Name; 5643 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5644 .Case("z10", true) 5645 .Case("z196", true) 5646 .Case("zEC12", true) 5647 .Case("z13", true) 5648 .Default(false); 5649 5650 return CPUKnown; 5651 } 5652 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5653 if (CPU == "zEC12") 5654 Features["transactional-execution"] = true; 5655 if (CPU == "z13") { 5656 Features["transactional-execution"] = true; 5657 Features["vector"] = true; 5658 } 5659 } 5660 5661 bool handleTargetFeatures(std::vector<std::string> &Features, 5662 DiagnosticsEngine &Diags) override { 5663 HasTransactionalExecution = false; 5664 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 5665 if (Features[i] == "+transactional-execution") 5666 HasTransactionalExecution = true; 5667 if (Features[i] == "+vector") 5668 HasVector = true; 5669 } 5670 // If we use the vector ABI, vector types are 64-bit aligned. 5671 if (HasVector) { 5672 MaxVectorAlign = 64; 5673 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 5674 "-v128:64-a:8:16-n32:64"; 5675 } 5676 return true; 5677 } 5678 5679 bool hasFeature(StringRef Feature) const override { 5680 return llvm::StringSwitch<bool>(Feature) 5681 .Case("systemz", true) 5682 .Case("htm", HasTransactionalExecution) 5683 .Case("vx", HasVector) 5684 .Default(false); 5685 } 5686 5687 StringRef getABI() const override { 5688 if (HasVector) 5689 return "vector"; 5690 return ""; 5691 } 5692 }; 5693 5694 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 5695 #define BUILTIN(ID, TYPE, ATTRS) \ 5696 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5697 #include "clang/Basic/BuiltinsSystemZ.def" 5698 }; 5699 5700 const char *const SystemZTargetInfo::GCCRegNames[] = { 5701 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5702 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5703 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 5704 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 5705 }; 5706 5707 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 5708 unsigned &NumNames) const { 5709 Names = GCCRegNames; 5710 NumNames = llvm::array_lengthof(GCCRegNames); 5711 } 5712 5713 bool SystemZTargetInfo:: 5714 validateAsmConstraint(const char *&Name, 5715 TargetInfo::ConstraintInfo &Info) const { 5716 switch (*Name) { 5717 default: 5718 return false; 5719 5720 case 'a': // Address register 5721 case 'd': // Data register (equivalent to 'r') 5722 case 'f': // Floating-point register 5723 Info.setAllowsRegister(); 5724 return true; 5725 5726 case 'I': // Unsigned 8-bit constant 5727 case 'J': // Unsigned 12-bit constant 5728 case 'K': // Signed 16-bit constant 5729 case 'L': // Signed 20-bit displacement (on all targets we support) 5730 case 'M': // 0x7fffffff 5731 return true; 5732 5733 case 'Q': // Memory with base and unsigned 12-bit displacement 5734 case 'R': // Likewise, plus an index 5735 case 'S': // Memory with base and signed 20-bit displacement 5736 case 'T': // Likewise, plus an index 5737 Info.setAllowsMemory(); 5738 return true; 5739 } 5740 } 5741 5742 class MSP430TargetInfo : public TargetInfo { 5743 static const char * const GCCRegNames[]; 5744 public: 5745 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5746 BigEndian = false; 5747 TLSSupported = false; 5748 IntWidth = 16; IntAlign = 16; 5749 LongWidth = 32; LongLongWidth = 64; 5750 LongAlign = LongLongAlign = 16; 5751 PointerWidth = 16; PointerAlign = 16; 5752 SuitableAlign = 16; 5753 SizeType = UnsignedInt; 5754 IntMaxType = SignedLongLong; 5755 IntPtrType = SignedInt; 5756 PtrDiffType = SignedInt; 5757 SigAtomicType = SignedLong; 5758 DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 5759 } 5760 void getTargetDefines(const LangOptions &Opts, 5761 MacroBuilder &Builder) const override { 5762 Builder.defineMacro("MSP430"); 5763 Builder.defineMacro("__MSP430__"); 5764 // FIXME: defines for different 'flavours' of MCU 5765 } 5766 void getTargetBuiltins(const Builtin::Info *&Records, 5767 unsigned &NumRecords) const override { 5768 // FIXME: Implement. 5769 Records = nullptr; 5770 NumRecords = 0; 5771 } 5772 bool hasFeature(StringRef Feature) const override { 5773 return Feature == "msp430"; 5774 } 5775 void getGCCRegNames(const char * const *&Names, 5776 unsigned &NumNames) const override; 5777 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5778 unsigned &NumAliases) const override { 5779 // No aliases. 5780 Aliases = nullptr; 5781 NumAliases = 0; 5782 } 5783 bool 5784 validateAsmConstraint(const char *&Name, 5785 TargetInfo::ConstraintInfo &info) const override { 5786 // FIXME: implement 5787 switch (*Name) { 5788 case 'K': // the constant 1 5789 case 'L': // constant -1^20 .. 1^19 5790 case 'M': // constant 1-4: 5791 return true; 5792 } 5793 // No target constraints for now. 5794 return false; 5795 } 5796 const char *getClobbers() const override { 5797 // FIXME: Is this really right? 5798 return ""; 5799 } 5800 BuiltinVaListKind getBuiltinVaListKind() const override { 5801 // FIXME: implement 5802 return TargetInfo::CharPtrBuiltinVaList; 5803 } 5804 }; 5805 5806 const char * const MSP430TargetInfo::GCCRegNames[] = { 5807 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5808 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 5809 }; 5810 5811 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 5812 unsigned &NumNames) const { 5813 Names = GCCRegNames; 5814 NumNames = llvm::array_lengthof(GCCRegNames); 5815 } 5816 5817 // LLVM and Clang cannot be used directly to output native binaries for 5818 // target, but is used to compile C code to llvm bitcode with correct 5819 // type and alignment information. 5820 // 5821 // TCE uses the llvm bitcode as input and uses it for generating customized 5822 // target processor and program binary. TCE co-design environment is 5823 // publicly available in http://tce.cs.tut.fi 5824 5825 static const unsigned TCEOpenCLAddrSpaceMap[] = { 5826 3, // opencl_global 5827 4, // opencl_local 5828 5, // opencl_constant 5829 // FIXME: generic has to be added to the target 5830 0, // opencl_generic 5831 0, // cuda_device 5832 0, // cuda_constant 5833 0 // cuda_shared 5834 }; 5835 5836 class TCETargetInfo : public TargetInfo{ 5837 public: 5838 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5839 TLSSupported = false; 5840 IntWidth = 32; 5841 LongWidth = LongLongWidth = 32; 5842 PointerWidth = 32; 5843 IntAlign = 32; 5844 LongAlign = LongLongAlign = 32; 5845 PointerAlign = 32; 5846 SuitableAlign = 32; 5847 SizeType = UnsignedInt; 5848 IntMaxType = SignedLong; 5849 IntPtrType = SignedInt; 5850 PtrDiffType = SignedInt; 5851 FloatWidth = 32; 5852 FloatAlign = 32; 5853 DoubleWidth = 32; 5854 DoubleAlign = 32; 5855 LongDoubleWidth = 32; 5856 LongDoubleAlign = 32; 5857 FloatFormat = &llvm::APFloat::IEEEsingle; 5858 DoubleFormat = &llvm::APFloat::IEEEsingle; 5859 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 5860 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 5861 "-f64:32-v64:32-v128:32-a:0:32-n32"; 5862 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 5863 UseAddrSpaceMapMangling = true; 5864 } 5865 5866 void getTargetDefines(const LangOptions &Opts, 5867 MacroBuilder &Builder) const override { 5868 DefineStd(Builder, "tce", Opts); 5869 Builder.defineMacro("__TCE__"); 5870 Builder.defineMacro("__TCE_V1__"); 5871 } 5872 bool hasFeature(StringRef Feature) const override { 5873 return Feature == "tce"; 5874 } 5875 5876 void getTargetBuiltins(const Builtin::Info *&Records, 5877 unsigned &NumRecords) const override {} 5878 const char *getClobbers() const override { 5879 return ""; 5880 } 5881 BuiltinVaListKind getBuiltinVaListKind() const override { 5882 return TargetInfo::VoidPtrBuiltinVaList; 5883 } 5884 void getGCCRegNames(const char * const *&Names, 5885 unsigned &NumNames) const override {} 5886 bool validateAsmConstraint(const char *&Name, 5887 TargetInfo::ConstraintInfo &info) const override{ 5888 return true; 5889 } 5890 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5891 unsigned &NumAliases) const override {} 5892 }; 5893 5894 class MipsTargetInfoBase : public TargetInfo { 5895 virtual void setDescriptionString() = 0; 5896 5897 static const Builtin::Info BuiltinInfo[]; 5898 std::string CPU; 5899 bool IsMips16; 5900 bool IsMicromips; 5901 bool IsNan2008; 5902 bool IsSingleFloat; 5903 enum MipsFloatABI { 5904 HardFloat, SoftFloat 5905 } FloatABI; 5906 enum DspRevEnum { 5907 NoDSP, DSP1, DSP2 5908 } DspRev; 5909 bool HasMSA; 5910 5911 protected: 5912 bool HasFP64; 5913 std::string ABI; 5914 5915 public: 5916 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 5917 const std::string &CPUStr) 5918 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 5919 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 5920 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 5921 TheCXXABI.set(TargetCXXABI::GenericMIPS); 5922 } 5923 5924 bool isNaN2008Default() const { 5925 return CPU == "mips32r6" || CPU == "mips64r6"; 5926 } 5927 5928 bool isFP64Default() const { 5929 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 5930 } 5931 5932 bool isNan2008() const override { 5933 return IsNan2008; 5934 } 5935 5936 StringRef getABI() const override { return ABI; } 5937 bool setCPU(const std::string &Name) override { 5938 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 5939 getTriple().getArch() == llvm::Triple::mipsel; 5940 CPU = Name; 5941 return llvm::StringSwitch<bool>(Name) 5942 .Case("mips1", IsMips32) 5943 .Case("mips2", IsMips32) 5944 .Case("mips3", true) 5945 .Case("mips4", true) 5946 .Case("mips5", true) 5947 .Case("mips32", IsMips32) 5948 .Case("mips32r2", IsMips32) 5949 .Case("mips32r3", IsMips32) 5950 .Case("mips32r5", IsMips32) 5951 .Case("mips32r6", IsMips32) 5952 .Case("mips64", true) 5953 .Case("mips64r2", true) 5954 .Case("mips64r3", true) 5955 .Case("mips64r5", true) 5956 .Case("mips64r6", true) 5957 .Case("octeon", true) 5958 .Default(false); 5959 } 5960 const std::string& getCPU() const { return CPU; } 5961 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5962 if (CPU == "octeon") 5963 Features["mips64r2"] = Features["cnmips"] = true; 5964 else 5965 Features[CPU] = true; 5966 } 5967 5968 void getTargetDefines(const LangOptions &Opts, 5969 MacroBuilder &Builder) const override { 5970 Builder.defineMacro("__mips__"); 5971 Builder.defineMacro("_mips"); 5972 if (Opts.GNUMode) 5973 Builder.defineMacro("mips"); 5974 5975 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5976 5977 switch (FloatABI) { 5978 case HardFloat: 5979 Builder.defineMacro("__mips_hard_float", Twine(1)); 5980 break; 5981 case SoftFloat: 5982 Builder.defineMacro("__mips_soft_float", Twine(1)); 5983 break; 5984 } 5985 5986 if (IsSingleFloat) 5987 Builder.defineMacro("__mips_single_float", Twine(1)); 5988 5989 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 5990 Builder.defineMacro("_MIPS_FPSET", 5991 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 5992 5993 if (IsMips16) 5994 Builder.defineMacro("__mips16", Twine(1)); 5995 5996 if (IsMicromips) 5997 Builder.defineMacro("__mips_micromips", Twine(1)); 5998 5999 if (IsNan2008) 6000 Builder.defineMacro("__mips_nan2008", Twine(1)); 6001 6002 switch (DspRev) { 6003 default: 6004 break; 6005 case DSP1: 6006 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6007 Builder.defineMacro("__mips_dsp", Twine(1)); 6008 break; 6009 case DSP2: 6010 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6011 Builder.defineMacro("__mips_dspr2", Twine(1)); 6012 Builder.defineMacro("__mips_dsp", Twine(1)); 6013 break; 6014 } 6015 6016 if (HasMSA) 6017 Builder.defineMacro("__mips_msa", Twine(1)); 6018 6019 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6020 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6021 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6022 6023 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6024 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6025 } 6026 6027 void getTargetBuiltins(const Builtin::Info *&Records, 6028 unsigned &NumRecords) const override { 6029 Records = BuiltinInfo; 6030 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 6031 } 6032 bool hasFeature(StringRef Feature) const override { 6033 return llvm::StringSwitch<bool>(Feature) 6034 .Case("mips", true) 6035 .Case("fp64", HasFP64) 6036 .Default(false); 6037 } 6038 BuiltinVaListKind getBuiltinVaListKind() const override { 6039 return TargetInfo::VoidPtrBuiltinVaList; 6040 } 6041 void getGCCRegNames(const char * const *&Names, 6042 unsigned &NumNames) const override { 6043 static const char *const GCCRegNames[] = { 6044 // CPU register names 6045 // Must match second column of GCCRegAliases 6046 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6047 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6048 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6049 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6050 // Floating point register names 6051 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6052 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6053 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6054 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6055 // Hi/lo and condition register names 6056 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6057 "$fcc5","$fcc6","$fcc7", 6058 // MSA register names 6059 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6060 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6061 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6062 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6063 // MSA control register names 6064 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6065 "$msarequest", "$msamap", "$msaunmap" 6066 }; 6067 Names = GCCRegNames; 6068 NumNames = llvm::array_lengthof(GCCRegNames); 6069 } 6070 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6071 unsigned &NumAliases) const override = 0; 6072 bool validateAsmConstraint(const char *&Name, 6073 TargetInfo::ConstraintInfo &Info) const override { 6074 switch (*Name) { 6075 default: 6076 return false; 6077 case 'r': // CPU registers. 6078 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6079 case 'y': // Equivalent to "r", backward compatibility only. 6080 case 'f': // floating-point registers. 6081 case 'c': // $25 for indirect jumps 6082 case 'l': // lo register 6083 case 'x': // hilo register pair 6084 Info.setAllowsRegister(); 6085 return true; 6086 case 'I': // Signed 16-bit constant 6087 case 'J': // Integer 0 6088 case 'K': // Unsigned 16-bit constant 6089 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6090 case 'M': // Constants not loadable via lui, addiu, or ori 6091 case 'N': // Constant -1 to -65535 6092 case 'O': // A signed 15-bit constant 6093 case 'P': // A constant between 1 go 65535 6094 return true; 6095 case 'R': // An address that can be used in a non-macro load or store 6096 Info.setAllowsMemory(); 6097 return true; 6098 case 'Z': 6099 if (Name[1] == 'C') { // An address usable by ll, and sc. 6100 Info.setAllowsMemory(); 6101 Name++; // Skip over 'Z'. 6102 return true; 6103 } 6104 return false; 6105 } 6106 } 6107 6108 std::string convertConstraint(const char *&Constraint) const override { 6109 std::string R; 6110 switch (*Constraint) { 6111 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6112 if (Constraint[1] == 'C') { 6113 R = std::string("^") + std::string(Constraint, 2); 6114 Constraint++; 6115 return R; 6116 } 6117 break; 6118 } 6119 return TargetInfo::convertConstraint(Constraint); 6120 } 6121 6122 const char *getClobbers() const override { 6123 // In GCC, $1 is not widely used in generated code (it's used only in a few 6124 // specific situations), so there is no real need for users to add it to 6125 // the clobbers list if they want to use it in their inline assembly code. 6126 // 6127 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6128 // code generation, so using it in inline assembly without adding it to the 6129 // clobbers list can cause conflicts between the inline assembly code and 6130 // the surrounding generated code. 6131 // 6132 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6133 // operands, which will conflict with the ".set at" assembler option (which 6134 // we use only for inline assembly, in order to maintain compatibility with 6135 // GCC) and will also conflict with the user's usage of $1. 6136 // 6137 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6138 // register for generated code is to automatically clobber $1 for all inline 6139 // assembly code. 6140 // 6141 // FIXME: We should automatically clobber $1 only for inline assembly code 6142 // which actually uses it. This would allow LLVM to use $1 for inline 6143 // assembly operands if the user's assembly code doesn't use it. 6144 return "~{$1}"; 6145 } 6146 6147 bool handleTargetFeatures(std::vector<std::string> &Features, 6148 DiagnosticsEngine &Diags) override { 6149 IsMips16 = false; 6150 IsMicromips = false; 6151 IsNan2008 = isNaN2008Default(); 6152 IsSingleFloat = false; 6153 FloatABI = HardFloat; 6154 DspRev = NoDSP; 6155 HasFP64 = isFP64Default(); 6156 6157 for (std::vector<std::string>::iterator it = Features.begin(), 6158 ie = Features.end(); it != ie; ++it) { 6159 if (*it == "+single-float") 6160 IsSingleFloat = true; 6161 else if (*it == "+soft-float") 6162 FloatABI = SoftFloat; 6163 else if (*it == "+mips16") 6164 IsMips16 = true; 6165 else if (*it == "+micromips") 6166 IsMicromips = true; 6167 else if (*it == "+dsp") 6168 DspRev = std::max(DspRev, DSP1); 6169 else if (*it == "+dspr2") 6170 DspRev = std::max(DspRev, DSP2); 6171 else if (*it == "+msa") 6172 HasMSA = true; 6173 else if (*it == "+fp64") 6174 HasFP64 = true; 6175 else if (*it == "-fp64") 6176 HasFP64 = false; 6177 else if (*it == "+nan2008") 6178 IsNan2008 = true; 6179 else if (*it == "-nan2008") 6180 IsNan2008 = false; 6181 } 6182 6183 setDescriptionString(); 6184 6185 return true; 6186 } 6187 6188 int getEHDataRegisterNumber(unsigned RegNo) const override { 6189 if (RegNo == 0) return 4; 6190 if (RegNo == 1) return 5; 6191 return -1; 6192 } 6193 6194 bool isCLZForZeroUndef() const override { return false; } 6195 }; 6196 6197 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 6198 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6199 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 6200 ALL_LANGUAGES }, 6201 #include "clang/Basic/BuiltinsMips.def" 6202 }; 6203 6204 class Mips32TargetInfoBase : public MipsTargetInfoBase { 6205 public: 6206 Mips32TargetInfoBase(const llvm::Triple &Triple) 6207 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 6208 SizeType = UnsignedInt; 6209 PtrDiffType = SignedInt; 6210 Int64Type = SignedLongLong; 6211 IntMaxType = Int64Type; 6212 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 6213 } 6214 bool setABI(const std::string &Name) override { 6215 if (Name == "o32" || Name == "eabi") { 6216 ABI = Name; 6217 return true; 6218 } 6219 return false; 6220 } 6221 void getTargetDefines(const LangOptions &Opts, 6222 MacroBuilder &Builder) const override { 6223 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6224 6225 Builder.defineMacro("__mips", "32"); 6226 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 6227 6228 const std::string& CPUStr = getCPU(); 6229 if (CPUStr == "mips32") 6230 Builder.defineMacro("__mips_isa_rev", "1"); 6231 else if (CPUStr == "mips32r2") 6232 Builder.defineMacro("__mips_isa_rev", "2"); 6233 else if (CPUStr == "mips32r3") 6234 Builder.defineMacro("__mips_isa_rev", "3"); 6235 else if (CPUStr == "mips32r5") 6236 Builder.defineMacro("__mips_isa_rev", "5"); 6237 else if (CPUStr == "mips32r6") 6238 Builder.defineMacro("__mips_isa_rev", "6"); 6239 6240 if (ABI == "o32") { 6241 Builder.defineMacro("__mips_o32"); 6242 Builder.defineMacro("_ABIO32", "1"); 6243 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6244 } 6245 else if (ABI == "eabi") 6246 Builder.defineMacro("__mips_eabi"); 6247 else 6248 llvm_unreachable("Invalid ABI for Mips32."); 6249 } 6250 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6251 unsigned &NumAliases) const override { 6252 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6253 { { "at" }, "$1" }, 6254 { { "v0" }, "$2" }, 6255 { { "v1" }, "$3" }, 6256 { { "a0" }, "$4" }, 6257 { { "a1" }, "$5" }, 6258 { { "a2" }, "$6" }, 6259 { { "a3" }, "$7" }, 6260 { { "t0" }, "$8" }, 6261 { { "t1" }, "$9" }, 6262 { { "t2" }, "$10" }, 6263 { { "t3" }, "$11" }, 6264 { { "t4" }, "$12" }, 6265 { { "t5" }, "$13" }, 6266 { { "t6" }, "$14" }, 6267 { { "t7" }, "$15" }, 6268 { { "s0" }, "$16" }, 6269 { { "s1" }, "$17" }, 6270 { { "s2" }, "$18" }, 6271 { { "s3" }, "$19" }, 6272 { { "s4" }, "$20" }, 6273 { { "s5" }, "$21" }, 6274 { { "s6" }, "$22" }, 6275 { { "s7" }, "$23" }, 6276 { { "t8" }, "$24" }, 6277 { { "t9" }, "$25" }, 6278 { { "k0" }, "$26" }, 6279 { { "k1" }, "$27" }, 6280 { { "gp" }, "$28" }, 6281 { { "sp","$sp" }, "$29" }, 6282 { { "fp","$fp" }, "$30" }, 6283 { { "ra" }, "$31" } 6284 }; 6285 Aliases = GCCRegAliases; 6286 NumAliases = llvm::array_lengthof(GCCRegAliases); 6287 } 6288 }; 6289 6290 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6291 void setDescriptionString() override { 6292 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6293 } 6294 6295 public: 6296 Mips32EBTargetInfo(const llvm::Triple &Triple) 6297 : Mips32TargetInfoBase(Triple) { 6298 } 6299 void getTargetDefines(const LangOptions &Opts, 6300 MacroBuilder &Builder) const override { 6301 DefineStd(Builder, "MIPSEB", Opts); 6302 Builder.defineMacro("_MIPSEB"); 6303 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6304 } 6305 }; 6306 6307 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6308 void setDescriptionString() override { 6309 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6310 } 6311 6312 public: 6313 Mips32ELTargetInfo(const llvm::Triple &Triple) 6314 : Mips32TargetInfoBase(Triple) { 6315 BigEndian = false; 6316 } 6317 void getTargetDefines(const LangOptions &Opts, 6318 MacroBuilder &Builder) const override { 6319 DefineStd(Builder, "MIPSEL", Opts); 6320 Builder.defineMacro("_MIPSEL"); 6321 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6322 } 6323 }; 6324 6325 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6326 public: 6327 Mips64TargetInfoBase(const llvm::Triple &Triple) 6328 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6329 LongDoubleWidth = LongDoubleAlign = 128; 6330 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6331 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6332 LongDoubleWidth = LongDoubleAlign = 64; 6333 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6334 } 6335 setN64ABITypes(); 6336 SuitableAlign = 128; 6337 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6338 } 6339 6340 void setN64ABITypes() { 6341 LongWidth = LongAlign = 64; 6342 PointerWidth = PointerAlign = 64; 6343 SizeType = UnsignedLong; 6344 PtrDiffType = SignedLong; 6345 Int64Type = SignedLong; 6346 IntMaxType = Int64Type; 6347 } 6348 6349 void setN32ABITypes() { 6350 LongWidth = LongAlign = 32; 6351 PointerWidth = PointerAlign = 32; 6352 SizeType = UnsignedInt; 6353 PtrDiffType = SignedInt; 6354 Int64Type = SignedLongLong; 6355 IntMaxType = Int64Type; 6356 } 6357 6358 bool setABI(const std::string &Name) override { 6359 if (Name == "n32") { 6360 setN32ABITypes(); 6361 ABI = Name; 6362 return true; 6363 } 6364 if (Name == "n64") { 6365 setN64ABITypes(); 6366 ABI = Name; 6367 return true; 6368 } 6369 return false; 6370 } 6371 6372 void getTargetDefines(const LangOptions &Opts, 6373 MacroBuilder &Builder) const override { 6374 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6375 6376 Builder.defineMacro("__mips", "64"); 6377 Builder.defineMacro("__mips64"); 6378 Builder.defineMacro("__mips64__"); 6379 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 6380 6381 const std::string& CPUStr = getCPU(); 6382 if (CPUStr == "mips64") 6383 Builder.defineMacro("__mips_isa_rev", "1"); 6384 else if (CPUStr == "mips64r2") 6385 Builder.defineMacro("__mips_isa_rev", "2"); 6386 else if (CPUStr == "mips64r3") 6387 Builder.defineMacro("__mips_isa_rev", "3"); 6388 else if (CPUStr == "mips64r5") 6389 Builder.defineMacro("__mips_isa_rev", "5"); 6390 else if (CPUStr == "mips64r6") 6391 Builder.defineMacro("__mips_isa_rev", "6"); 6392 6393 if (ABI == "n32") { 6394 Builder.defineMacro("__mips_n32"); 6395 Builder.defineMacro("_ABIN32", "2"); 6396 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 6397 } 6398 else if (ABI == "n64") { 6399 Builder.defineMacro("__mips_n64"); 6400 Builder.defineMacro("_ABI64", "3"); 6401 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 6402 } 6403 else 6404 llvm_unreachable("Invalid ABI for Mips64."); 6405 } 6406 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6407 unsigned &NumAliases) const override { 6408 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6409 { { "at" }, "$1" }, 6410 { { "v0" }, "$2" }, 6411 { { "v1" }, "$3" }, 6412 { { "a0" }, "$4" }, 6413 { { "a1" }, "$5" }, 6414 { { "a2" }, "$6" }, 6415 { { "a3" }, "$7" }, 6416 { { "a4" }, "$8" }, 6417 { { "a5" }, "$9" }, 6418 { { "a6" }, "$10" }, 6419 { { "a7" }, "$11" }, 6420 { { "t0" }, "$12" }, 6421 { { "t1" }, "$13" }, 6422 { { "t2" }, "$14" }, 6423 { { "t3" }, "$15" }, 6424 { { "s0" }, "$16" }, 6425 { { "s1" }, "$17" }, 6426 { { "s2" }, "$18" }, 6427 { { "s3" }, "$19" }, 6428 { { "s4" }, "$20" }, 6429 { { "s5" }, "$21" }, 6430 { { "s6" }, "$22" }, 6431 { { "s7" }, "$23" }, 6432 { { "t8" }, "$24" }, 6433 { { "t9" }, "$25" }, 6434 { { "k0" }, "$26" }, 6435 { { "k1" }, "$27" }, 6436 { { "gp" }, "$28" }, 6437 { { "sp","$sp" }, "$29" }, 6438 { { "fp","$fp" }, "$30" }, 6439 { { "ra" }, "$31" } 6440 }; 6441 Aliases = GCCRegAliases; 6442 NumAliases = llvm::array_lengthof(GCCRegAliases); 6443 } 6444 6445 bool hasInt128Type() const override { return true; } 6446 }; 6447 6448 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 6449 void setDescriptionString() override { 6450 if (ABI == "n32") 6451 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6452 else 6453 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6454 6455 } 6456 6457 public: 6458 Mips64EBTargetInfo(const llvm::Triple &Triple) 6459 : Mips64TargetInfoBase(Triple) {} 6460 void getTargetDefines(const LangOptions &Opts, 6461 MacroBuilder &Builder) const override { 6462 DefineStd(Builder, "MIPSEB", Opts); 6463 Builder.defineMacro("_MIPSEB"); 6464 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6465 } 6466 }; 6467 6468 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 6469 void setDescriptionString() override { 6470 if (ABI == "n32") 6471 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6472 else 6473 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6474 } 6475 public: 6476 Mips64ELTargetInfo(const llvm::Triple &Triple) 6477 : Mips64TargetInfoBase(Triple) { 6478 // Default ABI is n64. 6479 BigEndian = false; 6480 } 6481 void getTargetDefines(const LangOptions &Opts, 6482 MacroBuilder &Builder) const override { 6483 DefineStd(Builder, "MIPSEL", Opts); 6484 Builder.defineMacro("_MIPSEL"); 6485 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6486 } 6487 }; 6488 6489 class PNaClTargetInfo : public TargetInfo { 6490 public: 6491 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6492 BigEndian = false; 6493 this->UserLabelPrefix = ""; 6494 this->LongAlign = 32; 6495 this->LongWidth = 32; 6496 this->PointerAlign = 32; 6497 this->PointerWidth = 32; 6498 this->IntMaxType = TargetInfo::SignedLongLong; 6499 this->Int64Type = TargetInfo::SignedLongLong; 6500 this->DoubleAlign = 64; 6501 this->LongDoubleWidth = 64; 6502 this->LongDoubleAlign = 64; 6503 this->SizeType = TargetInfo::UnsignedInt; 6504 this->PtrDiffType = TargetInfo::SignedInt; 6505 this->IntPtrType = TargetInfo::SignedInt; 6506 this->RegParmMax = 0; // Disallow regparm 6507 } 6508 6509 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 6510 } 6511 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 6512 Builder.defineMacro("__le32__"); 6513 Builder.defineMacro("__pnacl__"); 6514 } 6515 void getTargetDefines(const LangOptions &Opts, 6516 MacroBuilder &Builder) const override { 6517 getArchDefines(Opts, Builder); 6518 } 6519 bool hasFeature(StringRef Feature) const override { 6520 return Feature == "pnacl"; 6521 } 6522 void getTargetBuiltins(const Builtin::Info *&Records, 6523 unsigned &NumRecords) const override { 6524 } 6525 BuiltinVaListKind getBuiltinVaListKind() const override { 6526 return TargetInfo::PNaClABIBuiltinVaList; 6527 } 6528 void getGCCRegNames(const char * const *&Names, 6529 unsigned &NumNames) const override; 6530 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6531 unsigned &NumAliases) const override; 6532 bool validateAsmConstraint(const char *&Name, 6533 TargetInfo::ConstraintInfo &Info) const override { 6534 return false; 6535 } 6536 6537 const char *getClobbers() const override { 6538 return ""; 6539 } 6540 }; 6541 6542 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 6543 unsigned &NumNames) const { 6544 Names = nullptr; 6545 NumNames = 0; 6546 } 6547 6548 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 6549 unsigned &NumAliases) const { 6550 Aliases = nullptr; 6551 NumAliases = 0; 6552 } 6553 6554 class Le64TargetInfo : public TargetInfo { 6555 static const Builtin::Info BuiltinInfo[]; 6556 6557 public: 6558 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6559 BigEndian = false; 6560 NoAsmVariants = true; 6561 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6562 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6563 DescriptionString = 6564 "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 6565 } 6566 6567 void getTargetDefines(const LangOptions &Opts, 6568 MacroBuilder &Builder) const override { 6569 DefineStd(Builder, "unix", Opts); 6570 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 6571 Builder.defineMacro("__ELF__"); 6572 } 6573 void getTargetBuiltins(const Builtin::Info *&Records, 6574 unsigned &NumRecords) const override { 6575 Records = BuiltinInfo; 6576 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin; 6577 } 6578 BuiltinVaListKind getBuiltinVaListKind() const override { 6579 return TargetInfo::PNaClABIBuiltinVaList; 6580 } 6581 const char *getClobbers() const override { return ""; } 6582 void getGCCRegNames(const char *const *&Names, 6583 unsigned &NumNames) const override { 6584 Names = nullptr; 6585 NumNames = 0; 6586 } 6587 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6588 unsigned &NumAliases) const override { 6589 Aliases = nullptr; 6590 NumAliases = 0; 6591 } 6592 bool validateAsmConstraint(const char *&Name, 6593 TargetInfo::ConstraintInfo &Info) const override { 6594 return false; 6595 } 6596 6597 bool hasProtectedVisibility() const override { return false; } 6598 }; 6599 } // end anonymous namespace. 6600 6601 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 6602 #define BUILTIN(ID, TYPE, ATTRS) \ 6603 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6604 #include "clang/Basic/BuiltinsLe64.def" 6605 }; 6606 6607 namespace { 6608 static const unsigned SPIRAddrSpaceMap[] = { 6609 1, // opencl_global 6610 3, // opencl_local 6611 2, // opencl_constant 6612 4, // opencl_generic 6613 0, // cuda_device 6614 0, // cuda_constant 6615 0 // cuda_shared 6616 }; 6617 class SPIRTargetInfo : public TargetInfo { 6618 public: 6619 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6620 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 6621 "SPIR target must use unknown OS"); 6622 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 6623 "SPIR target must use unknown environment type"); 6624 BigEndian = false; 6625 TLSSupported = false; 6626 LongWidth = LongAlign = 64; 6627 AddrSpaceMap = &SPIRAddrSpaceMap; 6628 UseAddrSpaceMapMangling = true; 6629 // Define available target features 6630 // These must be defined in sorted order! 6631 NoAsmVariants = true; 6632 } 6633 void getTargetDefines(const LangOptions &Opts, 6634 MacroBuilder &Builder) const override { 6635 DefineStd(Builder, "SPIR", Opts); 6636 } 6637 bool hasFeature(StringRef Feature) const override { 6638 return Feature == "spir"; 6639 } 6640 6641 void getTargetBuiltins(const Builtin::Info *&Records, 6642 unsigned &NumRecords) const override {} 6643 const char *getClobbers() const override { 6644 return ""; 6645 } 6646 void getGCCRegNames(const char * const *&Names, 6647 unsigned &NumNames) const override {} 6648 bool 6649 validateAsmConstraint(const char *&Name, 6650 TargetInfo::ConstraintInfo &info) const override { 6651 return true; 6652 } 6653 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6654 unsigned &NumAliases) const override {} 6655 BuiltinVaListKind getBuiltinVaListKind() const override { 6656 return TargetInfo::VoidPtrBuiltinVaList; 6657 } 6658 6659 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6660 return (CC == CC_SpirFunction || 6661 CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning; 6662 } 6663 6664 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 6665 return CC_SpirFunction; 6666 } 6667 }; 6668 6669 6670 class SPIR32TargetInfo : public SPIRTargetInfo { 6671 public: 6672 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6673 PointerWidth = PointerAlign = 32; 6674 SizeType = TargetInfo::UnsignedInt; 6675 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 6676 DescriptionString 6677 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 6678 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6679 } 6680 void getTargetDefines(const LangOptions &Opts, 6681 MacroBuilder &Builder) const override { 6682 DefineStd(Builder, "SPIR32", Opts); 6683 } 6684 }; 6685 6686 class SPIR64TargetInfo : public SPIRTargetInfo { 6687 public: 6688 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6689 PointerWidth = PointerAlign = 64; 6690 SizeType = TargetInfo::UnsignedLong; 6691 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 6692 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 6693 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6694 } 6695 void getTargetDefines(const LangOptions &Opts, 6696 MacroBuilder &Builder) const override { 6697 DefineStd(Builder, "SPIR64", Opts); 6698 } 6699 }; 6700 6701 class XCoreTargetInfo : public TargetInfo { 6702 static const Builtin::Info BuiltinInfo[]; 6703 public: 6704 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6705 BigEndian = false; 6706 NoAsmVariants = true; 6707 LongLongAlign = 32; 6708 SuitableAlign = 32; 6709 DoubleAlign = LongDoubleAlign = 32; 6710 SizeType = UnsignedInt; 6711 PtrDiffType = SignedInt; 6712 IntPtrType = SignedInt; 6713 WCharType = UnsignedChar; 6714 WIntType = UnsignedInt; 6715 UseZeroLengthBitfieldAlignment = true; 6716 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 6717 "-f64:32-a:0:32-n32"; 6718 } 6719 void getTargetDefines(const LangOptions &Opts, 6720 MacroBuilder &Builder) const override { 6721 Builder.defineMacro("__XS1B__"); 6722 } 6723 void getTargetBuiltins(const Builtin::Info *&Records, 6724 unsigned &NumRecords) const override { 6725 Records = BuiltinInfo; 6726 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 6727 } 6728 BuiltinVaListKind getBuiltinVaListKind() const override { 6729 return TargetInfo::VoidPtrBuiltinVaList; 6730 } 6731 const char *getClobbers() const override { 6732 return ""; 6733 } 6734 void getGCCRegNames(const char * const *&Names, 6735 unsigned &NumNames) const override { 6736 static const char * const GCCRegNames[] = { 6737 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6738 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 6739 }; 6740 Names = GCCRegNames; 6741 NumNames = llvm::array_lengthof(GCCRegNames); 6742 } 6743 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6744 unsigned &NumAliases) const override { 6745 Aliases = nullptr; 6746 NumAliases = 0; 6747 } 6748 bool validateAsmConstraint(const char *&Name, 6749 TargetInfo::ConstraintInfo &Info) const override { 6750 return false; 6751 } 6752 int getEHDataRegisterNumber(unsigned RegNo) const override { 6753 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 6754 return (RegNo < 2)? RegNo : -1; 6755 } 6756 }; 6757 6758 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 6759 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6760 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 6761 ALL_LANGUAGES }, 6762 #include "clang/Basic/BuiltinsXCore.def" 6763 }; 6764 } // end anonymous namespace. 6765 6766 namespace { 6767 // x86_32 Android target 6768 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 6769 public: 6770 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 6771 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 6772 SuitableAlign = 32; 6773 LongDoubleWidth = 64; 6774 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6775 } 6776 }; 6777 } // end anonymous namespace 6778 6779 namespace { 6780 // x86_64 Android target 6781 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 6782 public: 6783 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 6784 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 6785 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6786 } 6787 }; 6788 } // end anonymous namespace 6789 6790 6791 //===----------------------------------------------------------------------===// 6792 // Driver code 6793 //===----------------------------------------------------------------------===// 6794 6795 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 6796 llvm::Triple::OSType os = Triple.getOS(); 6797 6798 switch (Triple.getArch()) { 6799 default: 6800 return nullptr; 6801 6802 case llvm::Triple::xcore: 6803 return new XCoreTargetInfo(Triple); 6804 6805 case llvm::Triple::hexagon: 6806 return new HexagonTargetInfo(Triple); 6807 6808 case llvm::Triple::aarch64: 6809 if (Triple.isOSDarwin()) 6810 return new DarwinAArch64TargetInfo(Triple); 6811 6812 switch (os) { 6813 case llvm::Triple::FreeBSD: 6814 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 6815 case llvm::Triple::Linux: 6816 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 6817 case llvm::Triple::NetBSD: 6818 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 6819 default: 6820 return new AArch64leTargetInfo(Triple); 6821 } 6822 6823 case llvm::Triple::aarch64_be: 6824 switch (os) { 6825 case llvm::Triple::FreeBSD: 6826 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 6827 case llvm::Triple::Linux: 6828 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 6829 case llvm::Triple::NetBSD: 6830 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 6831 default: 6832 return new AArch64beTargetInfo(Triple); 6833 } 6834 6835 case llvm::Triple::arm: 6836 case llvm::Triple::thumb: 6837 if (Triple.isOSBinFormatMachO()) 6838 return new DarwinARMTargetInfo(Triple); 6839 6840 switch (os) { 6841 case llvm::Triple::Linux: 6842 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 6843 case llvm::Triple::FreeBSD: 6844 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 6845 case llvm::Triple::NetBSD: 6846 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 6847 case llvm::Triple::OpenBSD: 6848 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 6849 case llvm::Triple::Bitrig: 6850 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 6851 case llvm::Triple::RTEMS: 6852 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 6853 case llvm::Triple::NaCl: 6854 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 6855 case llvm::Triple::Win32: 6856 switch (Triple.getEnvironment()) { 6857 default: 6858 return new ARMleTargetInfo(Triple); 6859 case llvm::Triple::Itanium: 6860 return new ItaniumWindowsARMleTargetInfo(Triple); 6861 case llvm::Triple::MSVC: 6862 return new MicrosoftARMleTargetInfo(Triple); 6863 } 6864 default: 6865 return new ARMleTargetInfo(Triple); 6866 } 6867 6868 case llvm::Triple::armeb: 6869 case llvm::Triple::thumbeb: 6870 if (Triple.isOSDarwin()) 6871 return new DarwinARMTargetInfo(Triple); 6872 6873 switch (os) { 6874 case llvm::Triple::Linux: 6875 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 6876 case llvm::Triple::FreeBSD: 6877 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 6878 case llvm::Triple::NetBSD: 6879 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 6880 case llvm::Triple::OpenBSD: 6881 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 6882 case llvm::Triple::Bitrig: 6883 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 6884 case llvm::Triple::RTEMS: 6885 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 6886 case llvm::Triple::NaCl: 6887 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 6888 default: 6889 return new ARMbeTargetInfo(Triple); 6890 } 6891 6892 case llvm::Triple::msp430: 6893 return new MSP430TargetInfo(Triple); 6894 6895 case llvm::Triple::mips: 6896 switch (os) { 6897 case llvm::Triple::Linux: 6898 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 6899 case llvm::Triple::RTEMS: 6900 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 6901 case llvm::Triple::FreeBSD: 6902 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6903 case llvm::Triple::NetBSD: 6904 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6905 default: 6906 return new Mips32EBTargetInfo(Triple); 6907 } 6908 6909 case llvm::Triple::mipsel: 6910 switch (os) { 6911 case llvm::Triple::Linux: 6912 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 6913 case llvm::Triple::RTEMS: 6914 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 6915 case llvm::Triple::FreeBSD: 6916 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6917 case llvm::Triple::NetBSD: 6918 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6919 case llvm::Triple::NaCl: 6920 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 6921 default: 6922 return new Mips32ELTargetInfo(Triple); 6923 } 6924 6925 case llvm::Triple::mips64: 6926 switch (os) { 6927 case llvm::Triple::Linux: 6928 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 6929 case llvm::Triple::RTEMS: 6930 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 6931 case llvm::Triple::FreeBSD: 6932 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6933 case llvm::Triple::NetBSD: 6934 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6935 case llvm::Triple::OpenBSD: 6936 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6937 default: 6938 return new Mips64EBTargetInfo(Triple); 6939 } 6940 6941 case llvm::Triple::mips64el: 6942 switch (os) { 6943 case llvm::Triple::Linux: 6944 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 6945 case llvm::Triple::RTEMS: 6946 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 6947 case llvm::Triple::FreeBSD: 6948 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6949 case llvm::Triple::NetBSD: 6950 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6951 case llvm::Triple::OpenBSD: 6952 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6953 default: 6954 return new Mips64ELTargetInfo(Triple); 6955 } 6956 6957 case llvm::Triple::le32: 6958 switch (os) { 6959 case llvm::Triple::NaCl: 6960 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 6961 default: 6962 return nullptr; 6963 } 6964 6965 case llvm::Triple::le64: 6966 return new Le64TargetInfo(Triple); 6967 6968 case llvm::Triple::ppc: 6969 if (Triple.isOSDarwin()) 6970 return new DarwinPPC32TargetInfo(Triple); 6971 switch (os) { 6972 case llvm::Triple::Linux: 6973 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 6974 case llvm::Triple::FreeBSD: 6975 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 6976 case llvm::Triple::NetBSD: 6977 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 6978 case llvm::Triple::OpenBSD: 6979 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 6980 case llvm::Triple::RTEMS: 6981 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 6982 default: 6983 return new PPC32TargetInfo(Triple); 6984 } 6985 6986 case llvm::Triple::ppc64: 6987 if (Triple.isOSDarwin()) 6988 return new DarwinPPC64TargetInfo(Triple); 6989 switch (os) { 6990 case llvm::Triple::Linux: 6991 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6992 case llvm::Triple::Lv2: 6993 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 6994 case llvm::Triple::FreeBSD: 6995 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 6996 case llvm::Triple::NetBSD: 6997 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 6998 default: 6999 return new PPC64TargetInfo(Triple); 7000 } 7001 7002 case llvm::Triple::ppc64le: 7003 switch (os) { 7004 case llvm::Triple::Linux: 7005 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7006 case llvm::Triple::NetBSD: 7007 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7008 default: 7009 return new PPC64TargetInfo(Triple); 7010 } 7011 7012 case llvm::Triple::nvptx: 7013 return new NVPTX32TargetInfo(Triple); 7014 case llvm::Triple::nvptx64: 7015 return new NVPTX64TargetInfo(Triple); 7016 7017 case llvm::Triple::amdgcn: 7018 case llvm::Triple::r600: 7019 return new R600TargetInfo(Triple); 7020 7021 case llvm::Triple::sparc: 7022 switch (os) { 7023 case llvm::Triple::Linux: 7024 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 7025 case llvm::Triple::Solaris: 7026 return new SolarisSparcV8TargetInfo(Triple); 7027 case llvm::Triple::NetBSD: 7028 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 7029 case llvm::Triple::OpenBSD: 7030 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 7031 case llvm::Triple::RTEMS: 7032 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 7033 default: 7034 return new SparcV8TargetInfo(Triple); 7035 } 7036 7037 // The 'sparcel' architecture copies all the above cases except for Solaris. 7038 case llvm::Triple::sparcel: 7039 switch (os) { 7040 case llvm::Triple::Linux: 7041 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 7042 case llvm::Triple::NetBSD: 7043 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7044 case llvm::Triple::OpenBSD: 7045 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7046 case llvm::Triple::RTEMS: 7047 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 7048 default: 7049 return new SparcV8elTargetInfo(Triple); 7050 } 7051 7052 case llvm::Triple::sparcv9: 7053 switch (os) { 7054 case llvm::Triple::Linux: 7055 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 7056 case llvm::Triple::Solaris: 7057 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 7058 case llvm::Triple::NetBSD: 7059 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 7060 case llvm::Triple::OpenBSD: 7061 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 7062 case llvm::Triple::FreeBSD: 7063 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 7064 default: 7065 return new SparcV9TargetInfo(Triple); 7066 } 7067 7068 case llvm::Triple::systemz: 7069 switch (os) { 7070 case llvm::Triple::Linux: 7071 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 7072 default: 7073 return new SystemZTargetInfo(Triple); 7074 } 7075 7076 case llvm::Triple::tce: 7077 return new TCETargetInfo(Triple); 7078 7079 case llvm::Triple::x86: 7080 if (Triple.isOSDarwin()) 7081 return new DarwinI386TargetInfo(Triple); 7082 7083 switch (os) { 7084 case llvm::Triple::Linux: { 7085 switch (Triple.getEnvironment()) { 7086 default: 7087 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 7088 case llvm::Triple::Android: 7089 return new AndroidX86_32TargetInfo(Triple); 7090 } 7091 } 7092 case llvm::Triple::DragonFly: 7093 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 7094 case llvm::Triple::NetBSD: 7095 return new NetBSDI386TargetInfo(Triple); 7096 case llvm::Triple::OpenBSD: 7097 return new OpenBSDI386TargetInfo(Triple); 7098 case llvm::Triple::Bitrig: 7099 return new BitrigI386TargetInfo(Triple); 7100 case llvm::Triple::FreeBSD: 7101 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7102 case llvm::Triple::KFreeBSD: 7103 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7104 case llvm::Triple::Minix: 7105 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 7106 case llvm::Triple::Solaris: 7107 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 7108 case llvm::Triple::Win32: { 7109 switch (Triple.getEnvironment()) { 7110 default: 7111 return new X86_32TargetInfo(Triple); 7112 case llvm::Triple::Cygnus: 7113 return new CygwinX86_32TargetInfo(Triple); 7114 case llvm::Triple::GNU: 7115 return new MinGWX86_32TargetInfo(Triple); 7116 case llvm::Triple::Itanium: 7117 case llvm::Triple::MSVC: 7118 return new MicrosoftX86_32TargetInfo(Triple); 7119 } 7120 } 7121 case llvm::Triple::Haiku: 7122 return new HaikuX86_32TargetInfo(Triple); 7123 case llvm::Triple::RTEMS: 7124 return new RTEMSX86_32TargetInfo(Triple); 7125 case llvm::Triple::NaCl: 7126 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 7127 default: 7128 return new X86_32TargetInfo(Triple); 7129 } 7130 7131 case llvm::Triple::x86_64: 7132 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 7133 return new DarwinX86_64TargetInfo(Triple); 7134 7135 switch (os) { 7136 case llvm::Triple::CloudABI: 7137 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 7138 case llvm::Triple::Linux: { 7139 switch (Triple.getEnvironment()) { 7140 default: 7141 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 7142 case llvm::Triple::Android: 7143 return new AndroidX86_64TargetInfo(Triple); 7144 } 7145 } 7146 case llvm::Triple::DragonFly: 7147 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 7148 case llvm::Triple::NetBSD: 7149 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 7150 case llvm::Triple::OpenBSD: 7151 return new OpenBSDX86_64TargetInfo(Triple); 7152 case llvm::Triple::Bitrig: 7153 return new BitrigX86_64TargetInfo(Triple); 7154 case llvm::Triple::FreeBSD: 7155 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7156 case llvm::Triple::KFreeBSD: 7157 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7158 case llvm::Triple::Solaris: 7159 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 7160 case llvm::Triple::Win32: { 7161 switch (Triple.getEnvironment()) { 7162 default: 7163 return new X86_64TargetInfo(Triple); 7164 case llvm::Triple::GNU: 7165 return new MinGWX86_64TargetInfo(Triple); 7166 case llvm::Triple::MSVC: 7167 return new MicrosoftX86_64TargetInfo(Triple); 7168 } 7169 } 7170 case llvm::Triple::NaCl: 7171 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 7172 case llvm::Triple::PS4: 7173 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 7174 default: 7175 return new X86_64TargetInfo(Triple); 7176 } 7177 7178 case llvm::Triple::spir: { 7179 if (Triple.getOS() != llvm::Triple::UnknownOS || 7180 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7181 return nullptr; 7182 return new SPIR32TargetInfo(Triple); 7183 } 7184 case llvm::Triple::spir64: { 7185 if (Triple.getOS() != llvm::Triple::UnknownOS || 7186 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7187 return nullptr; 7188 return new SPIR64TargetInfo(Triple); 7189 } 7190 } 7191 } 7192 7193 /// CreateTargetInfo - Return the target info object for the specified target 7194 /// triple. 7195 TargetInfo * 7196 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 7197 const std::shared_ptr<TargetOptions> &Opts) { 7198 llvm::Triple Triple(Opts->Triple); 7199 7200 // Construct the target 7201 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 7202 if (!Target) { 7203 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 7204 return nullptr; 7205 } 7206 Target->TargetOpts = Opts; 7207 7208 // Set the target CPU if specified. 7209 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 7210 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 7211 return nullptr; 7212 } 7213 7214 // Set the target ABI if specified. 7215 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 7216 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 7217 return nullptr; 7218 } 7219 7220 // Set the fp math unit. 7221 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 7222 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 7223 return nullptr; 7224 } 7225 7226 // Compute the default target features, we need the target to handle this 7227 // because features may have dependencies on one another. 7228 llvm::StringMap<bool> Features; 7229 Target->getDefaultFeatures(Features); 7230 7231 // Apply the user specified deltas. 7232 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 7233 I < N; ++I) { 7234 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 7235 // Apply the feature via the target. 7236 bool Enabled = Name[0] == '+'; 7237 Target->setFeatureEnabled(Features, Name + 1, Enabled); 7238 } 7239 7240 // Add the features to the compile options. 7241 // 7242 // FIXME: If we are completely confident that we have the right set, we only 7243 // need to pass the minuses. 7244 Opts->Features.clear(); 7245 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 7246 ie = Features.end(); it != ie; ++it) 7247 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 7248 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 7249 return nullptr; 7250 7251 return Target.release(); 7252 } 7253