1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "clang/Basic/Version.h" 23 #include "llvm/ADT/APFloat.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringExtras.h" 26 #include "llvm/ADT/StringRef.h" 27 #include "llvm/ADT/StringSwitch.h" 28 #include "llvm/ADT/Triple.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/TargetParser.h" 32 #include <algorithm> 33 #include <memory> 34 35 using namespace clang; 36 37 //===----------------------------------------------------------------------===// 38 // Common code shared among targets. 39 //===----------------------------------------------------------------------===// 40 41 /// DefineStd - Define a macro name and standard variants. For example if 42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 43 /// when in GNU mode. 44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 45 const LangOptions &Opts) { 46 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 47 48 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 49 // in the user's namespace. 50 if (Opts.GNUMode) 51 Builder.defineMacro(MacroName); 52 53 // Define __unix. 54 Builder.defineMacro("__" + MacroName); 55 56 // Define __unix__. 57 Builder.defineMacro("__" + MacroName + "__"); 58 } 59 60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 61 bool Tuning = true) { 62 Builder.defineMacro("__" + CPUName); 63 Builder.defineMacro("__" + CPUName + "__"); 64 if (Tuning) 65 Builder.defineMacro("__tune_" + CPUName + "__"); 66 } 67 68 //===----------------------------------------------------------------------===// 69 // Defines specific to certain operating systems. 70 //===----------------------------------------------------------------------===// 71 72 namespace { 73 template<typename TgtInfo> 74 class OSTargetInfo : public TgtInfo { 75 protected: 76 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 77 MacroBuilder &Builder) const=0; 78 public: 79 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 80 void getTargetDefines(const LangOptions &Opts, 81 MacroBuilder &Builder) const override { 82 TgtInfo::getTargetDefines(Opts, Builder); 83 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 84 } 85 86 }; 87 88 // CloudABI Target 89 template <typename Target> 90 class CloudABITargetInfo : public OSTargetInfo<Target> { 91 protected: 92 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 93 MacroBuilder &Builder) const override { 94 Builder.defineMacro("__CloudABI__"); 95 Builder.defineMacro("__ELF__"); 96 97 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 98 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 99 Builder.defineMacro("__STDC_UTF_16__"); 100 Builder.defineMacro("__STDC_UTF_32__"); 101 } 102 103 public: 104 CloudABITargetInfo(const llvm::Triple &Triple) 105 : OSTargetInfo<Target>(Triple) { 106 this->UserLabelPrefix = ""; 107 } 108 }; 109 110 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 111 const llvm::Triple &Triple, 112 StringRef &PlatformName, 113 VersionTuple &PlatformMinVersion) { 114 Builder.defineMacro("__APPLE_CC__", "6000"); 115 Builder.defineMacro("__APPLE__"); 116 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 117 // AddressSanitizer doesn't play well with source fortification, which is on 118 // by default on Darwin. 119 if (Opts.Sanitize.has(SanitizerKind::Address)) 120 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 121 122 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 123 if (!Opts.ObjC1) { 124 // __weak is always defined, for use in blocks and with objc pointers. 125 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 126 Builder.defineMacro("__strong", ""); 127 Builder.defineMacro("__unsafe_unretained", ""); 128 } 129 130 if (Opts.Static) 131 Builder.defineMacro("__STATIC__"); 132 else 133 Builder.defineMacro("__DYNAMIC__"); 134 135 if (Opts.POSIXThreads) 136 Builder.defineMacro("_REENTRANT"); 137 138 // Get the platform type and version number from the triple. 139 unsigned Maj, Min, Rev; 140 if (Triple.isMacOSX()) { 141 Triple.getMacOSXVersion(Maj, Min, Rev); 142 PlatformName = "macosx"; 143 } else { 144 Triple.getOSVersion(Maj, Min, Rev); 145 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 146 } 147 148 // If -target arch-pc-win32-macho option specified, we're 149 // generating code for Win32 ABI. No need to emit 150 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 151 if (PlatformName == "win32") { 152 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 153 return; 154 } 155 156 // Set the appropriate OS version define. 157 if (Triple.isiOS()) { 158 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 159 char Str[6]; 160 Str[0] = '0' + Maj; 161 Str[1] = '0' + (Min / 10); 162 Str[2] = '0' + (Min % 10); 163 Str[3] = '0' + (Rev / 10); 164 Str[4] = '0' + (Rev % 10); 165 Str[5] = '\0'; 166 if (Triple.isTvOS()) 167 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 168 else 169 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 170 Str); 171 172 } else if (Triple.isWatchOS()) { 173 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 174 char Str[6]; 175 Str[0] = '0' + Maj; 176 Str[1] = '0' + (Min / 10); 177 Str[2] = '0' + (Min % 10); 178 Str[3] = '0' + (Rev / 10); 179 Str[4] = '0' + (Rev % 10); 180 Str[5] = '\0'; 181 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 182 } else if (Triple.isMacOSX()) { 183 // Note that the Driver allows versions which aren't representable in the 184 // define (because we only get a single digit for the minor and micro 185 // revision numbers). So, we limit them to the maximum representable 186 // version. 187 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 188 char Str[7]; 189 if (Maj < 10 || (Maj == 10 && Min < 10)) { 190 Str[0] = '0' + (Maj / 10); 191 Str[1] = '0' + (Maj % 10); 192 Str[2] = '0' + std::min(Min, 9U); 193 Str[3] = '0' + std::min(Rev, 9U); 194 Str[4] = '\0'; 195 } else { 196 // Handle versions > 10.9. 197 Str[0] = '0' + (Maj / 10); 198 Str[1] = '0' + (Maj % 10); 199 Str[2] = '0' + (Min / 10); 200 Str[3] = '0' + (Min % 10); 201 Str[4] = '0' + (Rev / 10); 202 Str[5] = '0' + (Rev % 10); 203 Str[6] = '\0'; 204 } 205 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 206 } 207 208 // Tell users about the kernel if there is one. 209 if (Triple.isOSDarwin()) 210 Builder.defineMacro("__MACH__"); 211 212 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 213 } 214 215 template<typename Target> 216 class DarwinTargetInfo : public OSTargetInfo<Target> { 217 protected: 218 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 219 MacroBuilder &Builder) const override { 220 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 221 this->PlatformMinVersion); 222 } 223 224 public: 225 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 226 // By default, no TLS, and we whitelist permitted architecture/OS 227 // combinations. 228 this->TLSSupported = false; 229 230 if (Triple.isMacOSX()) 231 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 232 else if (Triple.isiOS()) { 233 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 234 if (Triple.getArch() == llvm::Triple::x86_64 || 235 Triple.getArch() == llvm::Triple::aarch64) 236 this->TLSSupported = !Triple.isOSVersionLT(8); 237 else if (Triple.getArch() == llvm::Triple::x86 || 238 Triple.getArch() == llvm::Triple::arm || 239 Triple.getArch() == llvm::Triple::thumb) 240 this->TLSSupported = !Triple.isOSVersionLT(9); 241 } else if (Triple.isWatchOS()) 242 this->TLSSupported = !Triple.isOSVersionLT(2); 243 244 this->MCountName = "\01mcount"; 245 } 246 247 std::string isValidSectionSpecifier(StringRef SR) const override { 248 // Let MCSectionMachO validate this. 249 StringRef Segment, Section; 250 unsigned TAA, StubSize; 251 bool HasTAA; 252 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 253 TAA, HasTAA, StubSize); 254 } 255 256 const char *getStaticInitSectionSpecifier() const override { 257 // FIXME: We should return 0 when building kexts. 258 return "__TEXT,__StaticInit,regular,pure_instructions"; 259 } 260 261 /// Darwin does not support protected visibility. Darwin's "default" 262 /// is very similar to ELF's "protected"; Darwin requires a "weak" 263 /// attribute on declarations that can be dynamically replaced. 264 bool hasProtectedVisibility() const override { 265 return false; 266 } 267 }; 268 269 270 // DragonFlyBSD Target 271 template<typename Target> 272 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 273 protected: 274 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 275 MacroBuilder &Builder) const override { 276 // DragonFly defines; list based off of gcc output 277 Builder.defineMacro("__DragonFly__"); 278 Builder.defineMacro("__DragonFly_cc_version", "100001"); 279 Builder.defineMacro("__ELF__"); 280 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 281 Builder.defineMacro("__tune_i386__"); 282 DefineStd(Builder, "unix", Opts); 283 } 284 public: 285 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 286 : OSTargetInfo<Target>(Triple) { 287 this->UserLabelPrefix = ""; 288 289 switch (Triple.getArch()) { 290 default: 291 case llvm::Triple::x86: 292 case llvm::Triple::x86_64: 293 this->MCountName = ".mcount"; 294 break; 295 } 296 } 297 }; 298 299 // FreeBSD Target 300 template<typename Target> 301 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 302 protected: 303 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 304 MacroBuilder &Builder) const override { 305 // FreeBSD defines; list based off of gcc output 306 307 unsigned Release = Triple.getOSMajorVersion(); 308 if (Release == 0U) 309 Release = 8; 310 311 Builder.defineMacro("__FreeBSD__", Twine(Release)); 312 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 313 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 314 DefineStd(Builder, "unix", Opts); 315 Builder.defineMacro("__ELF__"); 316 317 // On FreeBSD, wchar_t contains the number of the code point as 318 // used by the character set of the locale. These character sets are 319 // not necessarily a superset of ASCII. 320 // 321 // FIXME: This is wrong; the macro refers to the numerical values 322 // of wchar_t *literals*, which are not locale-dependent. However, 323 // FreeBSD systems apparently depend on us getting this wrong, and 324 // setting this to 1 is conforming even if all the basic source 325 // character literals have the same encoding as char and wchar_t. 326 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 327 } 328 public: 329 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 330 this->UserLabelPrefix = ""; 331 332 switch (Triple.getArch()) { 333 default: 334 case llvm::Triple::x86: 335 case llvm::Triple::x86_64: 336 this->MCountName = ".mcount"; 337 break; 338 case llvm::Triple::mips: 339 case llvm::Triple::mipsel: 340 case llvm::Triple::ppc: 341 case llvm::Triple::ppc64: 342 case llvm::Triple::ppc64le: 343 this->MCountName = "_mcount"; 344 break; 345 case llvm::Triple::arm: 346 this->MCountName = "__mcount"; 347 break; 348 } 349 } 350 }; 351 352 // GNU/kFreeBSD Target 353 template<typename Target> 354 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 355 protected: 356 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 357 MacroBuilder &Builder) const override { 358 // GNU/kFreeBSD defines; list based off of gcc output 359 360 DefineStd(Builder, "unix", Opts); 361 Builder.defineMacro("__FreeBSD_kernel__"); 362 Builder.defineMacro("__GLIBC__"); 363 Builder.defineMacro("__ELF__"); 364 if (Opts.POSIXThreads) 365 Builder.defineMacro("_REENTRANT"); 366 if (Opts.CPlusPlus) 367 Builder.defineMacro("_GNU_SOURCE"); 368 } 369 public: 370 KFreeBSDTargetInfo(const llvm::Triple &Triple) 371 : OSTargetInfo<Target>(Triple) { 372 this->UserLabelPrefix = ""; 373 } 374 }; 375 376 // Minix Target 377 template<typename Target> 378 class MinixTargetInfo : public OSTargetInfo<Target> { 379 protected: 380 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 381 MacroBuilder &Builder) const override { 382 // Minix defines 383 384 Builder.defineMacro("__minix", "3"); 385 Builder.defineMacro("_EM_WSIZE", "4"); 386 Builder.defineMacro("_EM_PSIZE", "4"); 387 Builder.defineMacro("_EM_SSIZE", "2"); 388 Builder.defineMacro("_EM_LSIZE", "4"); 389 Builder.defineMacro("_EM_FSIZE", "4"); 390 Builder.defineMacro("_EM_DSIZE", "8"); 391 Builder.defineMacro("__ELF__"); 392 DefineStd(Builder, "unix", Opts); 393 } 394 public: 395 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 396 this->UserLabelPrefix = ""; 397 } 398 }; 399 400 // Linux target 401 template<typename Target> 402 class LinuxTargetInfo : public OSTargetInfo<Target> { 403 protected: 404 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 405 MacroBuilder &Builder) const override { 406 // Linux defines; list based off of gcc output 407 DefineStd(Builder, "unix", Opts); 408 DefineStd(Builder, "linux", Opts); 409 Builder.defineMacro("__gnu_linux__"); 410 Builder.defineMacro("__ELF__"); 411 if (Triple.isAndroid()) { 412 Builder.defineMacro("__ANDROID__", "1"); 413 unsigned Maj, Min, Rev; 414 Triple.getEnvironmentVersion(Maj, Min, Rev); 415 this->PlatformName = "android"; 416 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 417 } 418 if (Opts.POSIXThreads) 419 Builder.defineMacro("_REENTRANT"); 420 if (Opts.CPlusPlus) 421 Builder.defineMacro("_GNU_SOURCE"); 422 } 423 public: 424 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 425 this->UserLabelPrefix = ""; 426 this->WIntType = TargetInfo::UnsignedInt; 427 428 switch (Triple.getArch()) { 429 default: 430 break; 431 case llvm::Triple::ppc: 432 case llvm::Triple::ppc64: 433 case llvm::Triple::ppc64le: 434 this->MCountName = "_mcount"; 435 break; 436 } 437 } 438 439 const char *getStaticInitSectionSpecifier() const override { 440 return ".text.startup"; 441 } 442 }; 443 444 // NetBSD Target 445 template<typename Target> 446 class NetBSDTargetInfo : public OSTargetInfo<Target> { 447 protected: 448 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 449 MacroBuilder &Builder) const override { 450 // NetBSD defines; list based off of gcc output 451 Builder.defineMacro("__NetBSD__"); 452 Builder.defineMacro("__unix__"); 453 Builder.defineMacro("__ELF__"); 454 if (Opts.POSIXThreads) 455 Builder.defineMacro("_POSIX_THREADS"); 456 457 switch (Triple.getArch()) { 458 default: 459 break; 460 case llvm::Triple::arm: 461 case llvm::Triple::armeb: 462 case llvm::Triple::thumb: 463 case llvm::Triple::thumbeb: 464 Builder.defineMacro("__ARM_DWARF_EH__"); 465 break; 466 } 467 } 468 public: 469 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 470 this->UserLabelPrefix = ""; 471 this->MCountName = "_mcount"; 472 } 473 }; 474 475 // OpenBSD Target 476 template<typename Target> 477 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 478 protected: 479 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 480 MacroBuilder &Builder) const override { 481 // OpenBSD defines; list based off of gcc output 482 483 Builder.defineMacro("__OpenBSD__"); 484 DefineStd(Builder, "unix", Opts); 485 Builder.defineMacro("__ELF__"); 486 if (Opts.POSIXThreads) 487 Builder.defineMacro("_REENTRANT"); 488 } 489 public: 490 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 491 this->UserLabelPrefix = ""; 492 this->TLSSupported = false; 493 494 switch (Triple.getArch()) { 495 default: 496 case llvm::Triple::x86: 497 case llvm::Triple::x86_64: 498 case llvm::Triple::arm: 499 case llvm::Triple::sparc: 500 this->MCountName = "__mcount"; 501 break; 502 case llvm::Triple::mips64: 503 case llvm::Triple::mips64el: 504 case llvm::Triple::ppc: 505 case llvm::Triple::sparcv9: 506 this->MCountName = "_mcount"; 507 break; 508 } 509 } 510 }; 511 512 // Bitrig Target 513 template<typename Target> 514 class BitrigTargetInfo : public OSTargetInfo<Target> { 515 protected: 516 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 517 MacroBuilder &Builder) const override { 518 // Bitrig defines; list based off of gcc output 519 520 Builder.defineMacro("__Bitrig__"); 521 DefineStd(Builder, "unix", Opts); 522 Builder.defineMacro("__ELF__"); 523 if (Opts.POSIXThreads) 524 Builder.defineMacro("_REENTRANT"); 525 526 switch (Triple.getArch()) { 527 default: 528 break; 529 case llvm::Triple::arm: 530 case llvm::Triple::armeb: 531 case llvm::Triple::thumb: 532 case llvm::Triple::thumbeb: 533 Builder.defineMacro("__ARM_DWARF_EH__"); 534 break; 535 } 536 } 537 public: 538 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 539 this->UserLabelPrefix = ""; 540 this->MCountName = "__mcount"; 541 } 542 }; 543 544 // PSP Target 545 template<typename Target> 546 class PSPTargetInfo : public OSTargetInfo<Target> { 547 protected: 548 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 549 MacroBuilder &Builder) const override { 550 // PSP defines; list based on the output of the pspdev gcc toolchain. 551 Builder.defineMacro("PSP"); 552 Builder.defineMacro("_PSP"); 553 Builder.defineMacro("__psp__"); 554 Builder.defineMacro("__ELF__"); 555 } 556 public: 557 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 558 this->UserLabelPrefix = ""; 559 } 560 }; 561 562 // PS3 PPU Target 563 template<typename Target> 564 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 565 protected: 566 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 567 MacroBuilder &Builder) const override { 568 // PS3 PPU defines. 569 Builder.defineMacro("__PPC__"); 570 Builder.defineMacro("__PPU__"); 571 Builder.defineMacro("__CELLOS_LV2__"); 572 Builder.defineMacro("__ELF__"); 573 Builder.defineMacro("__LP32__"); 574 Builder.defineMacro("_ARCH_PPC64"); 575 Builder.defineMacro("__powerpc64__"); 576 } 577 public: 578 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 579 this->UserLabelPrefix = ""; 580 this->LongWidth = this->LongAlign = 32; 581 this->PointerWidth = this->PointerAlign = 32; 582 this->IntMaxType = TargetInfo::SignedLongLong; 583 this->Int64Type = TargetInfo::SignedLongLong; 584 this->SizeType = TargetInfo::UnsignedInt; 585 this->DataLayoutString = "E-m:e-p:32:32-i64:64-n32:64"; 586 } 587 }; 588 589 template <typename Target> 590 class PS4OSTargetInfo : public OSTargetInfo<Target> { 591 protected: 592 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 593 MacroBuilder &Builder) const override { 594 Builder.defineMacro("__FreeBSD__", "9"); 595 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 596 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 597 DefineStd(Builder, "unix", Opts); 598 Builder.defineMacro("__ELF__"); 599 Builder.defineMacro("__PS4__"); 600 } 601 public: 602 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 603 this->WCharType = this->UnsignedShort; 604 605 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 606 this->MaxTLSAlign = 256; 607 this->UserLabelPrefix = ""; 608 609 switch (Triple.getArch()) { 610 default: 611 case llvm::Triple::x86_64: 612 this->MCountName = ".mcount"; 613 break; 614 } 615 } 616 }; 617 618 // Solaris target 619 template<typename Target> 620 class SolarisTargetInfo : public OSTargetInfo<Target> { 621 protected: 622 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 623 MacroBuilder &Builder) const override { 624 DefineStd(Builder, "sun", Opts); 625 DefineStd(Builder, "unix", Opts); 626 Builder.defineMacro("__ELF__"); 627 Builder.defineMacro("__svr4__"); 628 Builder.defineMacro("__SVR4"); 629 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 630 // newer, but to 500 for everything else. feature_test.h has a check to 631 // ensure that you are not using C99 with an old version of X/Open or C89 632 // with a new version. 633 if (Opts.C99) 634 Builder.defineMacro("_XOPEN_SOURCE", "600"); 635 else 636 Builder.defineMacro("_XOPEN_SOURCE", "500"); 637 if (Opts.CPlusPlus) 638 Builder.defineMacro("__C99FEATURES__"); 639 Builder.defineMacro("_LARGEFILE_SOURCE"); 640 Builder.defineMacro("_LARGEFILE64_SOURCE"); 641 Builder.defineMacro("__EXTENSIONS__"); 642 Builder.defineMacro("_REENTRANT"); 643 } 644 public: 645 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 646 this->UserLabelPrefix = ""; 647 this->WCharType = this->SignedInt; 648 // FIXME: WIntType should be SignedLong 649 } 650 }; 651 652 // Windows target 653 template<typename Target> 654 class WindowsTargetInfo : public OSTargetInfo<Target> { 655 protected: 656 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 657 MacroBuilder &Builder) const override { 658 Builder.defineMacro("_WIN32"); 659 } 660 void getVisualStudioDefines(const LangOptions &Opts, 661 MacroBuilder &Builder) const { 662 if (Opts.CPlusPlus) { 663 if (Opts.RTTIData) 664 Builder.defineMacro("_CPPRTTI"); 665 666 if (Opts.CXXExceptions) 667 Builder.defineMacro("_CPPUNWIND"); 668 } 669 670 if (Opts.Bool) 671 Builder.defineMacro("__BOOL_DEFINED"); 672 673 if (!Opts.CharIsSigned) 674 Builder.defineMacro("_CHAR_UNSIGNED"); 675 676 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 677 // but it works for now. 678 if (Opts.POSIXThreads) 679 Builder.defineMacro("_MT"); 680 681 if (Opts.MSCompatibilityVersion) { 682 Builder.defineMacro("_MSC_VER", 683 Twine(Opts.MSCompatibilityVersion / 100000)); 684 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 685 // FIXME We cannot encode the revision information into 32-bits 686 Builder.defineMacro("_MSC_BUILD", Twine(1)); 687 688 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 689 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 690 } 691 692 if (Opts.MicrosoftExt) { 693 Builder.defineMacro("_MSC_EXTENSIONS"); 694 695 if (Opts.CPlusPlus11) { 696 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 697 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 698 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 699 } 700 } 701 702 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 703 } 704 705 public: 706 WindowsTargetInfo(const llvm::Triple &Triple) 707 : OSTargetInfo<Target>(Triple) {} 708 }; 709 710 template <typename Target> 711 class NaClTargetInfo : public OSTargetInfo<Target> { 712 protected: 713 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 714 MacroBuilder &Builder) const override { 715 if (Opts.POSIXThreads) 716 Builder.defineMacro("_REENTRANT"); 717 if (Opts.CPlusPlus) 718 Builder.defineMacro("_GNU_SOURCE"); 719 720 DefineStd(Builder, "unix", Opts); 721 Builder.defineMacro("__ELF__"); 722 Builder.defineMacro("__native_client__"); 723 } 724 725 public: 726 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 727 this->UserLabelPrefix = ""; 728 this->LongAlign = 32; 729 this->LongWidth = 32; 730 this->PointerAlign = 32; 731 this->PointerWidth = 32; 732 this->IntMaxType = TargetInfo::SignedLongLong; 733 this->Int64Type = TargetInfo::SignedLongLong; 734 this->DoubleAlign = 64; 735 this->LongDoubleWidth = 64; 736 this->LongDoubleAlign = 64; 737 this->LongLongWidth = 64; 738 this->LongLongAlign = 64; 739 this->SizeType = TargetInfo::UnsignedInt; 740 this->PtrDiffType = TargetInfo::SignedInt; 741 this->IntPtrType = TargetInfo::SignedInt; 742 // RegParmMax is inherited from the underlying architecture 743 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 744 if (Triple.getArch() == llvm::Triple::arm) { 745 // Handled in ARM's setABI(). 746 } else if (Triple.getArch() == llvm::Triple::x86) { 747 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 748 } else if (Triple.getArch() == llvm::Triple::x86_64) { 749 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 750 } else if (Triple.getArch() == llvm::Triple::mipsel) { 751 // Handled on mips' setDataLayoutString. 752 } else { 753 assert(Triple.getArch() == llvm::Triple::le32); 754 this->DataLayoutString = "e-p:32:32-i64:64"; 755 } 756 } 757 }; 758 759 // WebAssembly target 760 template <typename Target> 761 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 762 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 763 MacroBuilder &Builder) const final { 764 // A common platform macro. 765 if (Opts.POSIXThreads) 766 Builder.defineMacro("_REENTRANT"); 767 // Follow g++ convention and predefine _GNU_SOURCE for C++. 768 if (Opts.CPlusPlus) 769 Builder.defineMacro("_GNU_SOURCE"); 770 } 771 772 // As an optimization, group static init code together in a section. 773 const char *getStaticInitSectionSpecifier() const final { 774 return ".text.__startup"; 775 } 776 777 public: 778 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple) 779 : OSTargetInfo<Target>(Triple) { 780 this->MCountName = "__mcount"; 781 this->UserLabelPrefix = ""; 782 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 783 } 784 }; 785 786 //===----------------------------------------------------------------------===// 787 // Specific target implementations. 788 //===----------------------------------------------------------------------===// 789 790 // PPC abstract base class 791 class PPCTargetInfo : public TargetInfo { 792 static const Builtin::Info BuiltinInfo[]; 793 static const char * const GCCRegNames[]; 794 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 795 std::string CPU; 796 797 // Target cpu features. 798 bool HasVSX; 799 bool HasP8Vector; 800 bool HasP8Crypto; 801 bool HasDirectMove; 802 bool HasQPX; 803 bool HasHTM; 804 bool HasBPERMD; 805 bool HasExtDiv; 806 807 protected: 808 std::string ABI; 809 810 public: 811 PPCTargetInfo(const llvm::Triple &Triple) 812 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 813 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 814 HasBPERMD(false), HasExtDiv(false) { 815 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 816 SimdDefaultAlign = 128; 817 LongDoubleWidth = LongDoubleAlign = 128; 818 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 819 } 820 821 /// \brief Flags for architecture specific defines. 822 typedef enum { 823 ArchDefineNone = 0, 824 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 825 ArchDefinePpcgr = 1 << 1, 826 ArchDefinePpcsq = 1 << 2, 827 ArchDefine440 = 1 << 3, 828 ArchDefine603 = 1 << 4, 829 ArchDefine604 = 1 << 5, 830 ArchDefinePwr4 = 1 << 6, 831 ArchDefinePwr5 = 1 << 7, 832 ArchDefinePwr5x = 1 << 8, 833 ArchDefinePwr6 = 1 << 9, 834 ArchDefinePwr6x = 1 << 10, 835 ArchDefinePwr7 = 1 << 11, 836 ArchDefinePwr8 = 1 << 12, 837 ArchDefineA2 = 1 << 13, 838 ArchDefineA2q = 1 << 14 839 } ArchDefineTypes; 840 841 // Note: GCC recognizes the following additional cpus: 842 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 843 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 844 // titan, rs64. 845 bool setCPU(const std::string &Name) override { 846 bool CPUKnown = llvm::StringSwitch<bool>(Name) 847 .Case("generic", true) 848 .Case("440", true) 849 .Case("450", true) 850 .Case("601", true) 851 .Case("602", true) 852 .Case("603", true) 853 .Case("603e", true) 854 .Case("603ev", true) 855 .Case("604", true) 856 .Case("604e", true) 857 .Case("620", true) 858 .Case("630", true) 859 .Case("g3", true) 860 .Case("7400", true) 861 .Case("g4", true) 862 .Case("7450", true) 863 .Case("g4+", true) 864 .Case("750", true) 865 .Case("970", true) 866 .Case("g5", true) 867 .Case("a2", true) 868 .Case("a2q", true) 869 .Case("e500mc", true) 870 .Case("e5500", true) 871 .Case("power3", true) 872 .Case("pwr3", true) 873 .Case("power4", true) 874 .Case("pwr4", true) 875 .Case("power5", true) 876 .Case("pwr5", true) 877 .Case("power5x", true) 878 .Case("pwr5x", true) 879 .Case("power6", true) 880 .Case("pwr6", true) 881 .Case("power6x", true) 882 .Case("pwr6x", true) 883 .Case("power7", true) 884 .Case("pwr7", true) 885 .Case("power8", true) 886 .Case("pwr8", true) 887 .Case("powerpc", true) 888 .Case("ppc", true) 889 .Case("powerpc64", true) 890 .Case("ppc64", true) 891 .Case("powerpc64le", true) 892 .Case("ppc64le", true) 893 .Default(false); 894 895 if (CPUKnown) 896 CPU = Name; 897 898 return CPUKnown; 899 } 900 901 902 StringRef getABI() const override { return ABI; } 903 904 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 905 return llvm::makeArrayRef(BuiltinInfo, 906 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 907 } 908 909 bool isCLZForZeroUndef() const override { return false; } 910 911 void getTargetDefines(const LangOptions &Opts, 912 MacroBuilder &Builder) const override; 913 914 bool 915 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 916 StringRef CPU, 917 const std::vector<std::string> &FeaturesVec) const override; 918 919 bool handleTargetFeatures(std::vector<std::string> &Features, 920 DiagnosticsEngine &Diags) override; 921 bool hasFeature(StringRef Feature) const override; 922 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 923 bool Enabled) const override; 924 925 ArrayRef<const char *> getGCCRegNames() const override; 926 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 927 bool validateAsmConstraint(const char *&Name, 928 TargetInfo::ConstraintInfo &Info) const override { 929 switch (*Name) { 930 default: return false; 931 case 'O': // Zero 932 break; 933 case 'b': // Base register 934 case 'f': // Floating point register 935 Info.setAllowsRegister(); 936 break; 937 // FIXME: The following are added to allow parsing. 938 // I just took a guess at what the actions should be. 939 // Also, is more specific checking needed? I.e. specific registers? 940 case 'd': // Floating point register (containing 64-bit value) 941 case 'v': // Altivec vector register 942 Info.setAllowsRegister(); 943 break; 944 case 'w': 945 switch (Name[1]) { 946 case 'd':// VSX vector register to hold vector double data 947 case 'f':// VSX vector register to hold vector float data 948 case 's':// VSX vector register to hold scalar float data 949 case 'a':// Any VSX register 950 case 'c':// An individual CR bit 951 break; 952 default: 953 return false; 954 } 955 Info.setAllowsRegister(); 956 Name++; // Skip over 'w'. 957 break; 958 case 'h': // `MQ', `CTR', or `LINK' register 959 case 'q': // `MQ' register 960 case 'c': // `CTR' register 961 case 'l': // `LINK' register 962 case 'x': // `CR' register (condition register) number 0 963 case 'y': // `CR' register (condition register) 964 case 'z': // `XER[CA]' carry bit (part of the XER register) 965 Info.setAllowsRegister(); 966 break; 967 case 'I': // Signed 16-bit constant 968 case 'J': // Unsigned 16-bit constant shifted left 16 bits 969 // (use `L' instead for SImode constants) 970 case 'K': // Unsigned 16-bit constant 971 case 'L': // Signed 16-bit constant shifted left 16 bits 972 case 'M': // Constant larger than 31 973 case 'N': // Exact power of 2 974 case 'P': // Constant whose negation is a signed 16-bit constant 975 case 'G': // Floating point constant that can be loaded into a 976 // register with one instruction per word 977 case 'H': // Integer/Floating point constant that can be loaded 978 // into a register using three instructions 979 break; 980 case 'm': // Memory operand. Note that on PowerPC targets, m can 981 // include addresses that update the base register. It 982 // is therefore only safe to use `m' in an asm statement 983 // if that asm statement accesses the operand exactly once. 984 // The asm statement must also use `%U<opno>' as a 985 // placeholder for the "update" flag in the corresponding 986 // load or store instruction. For example: 987 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 988 // is correct but: 989 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 990 // is not. Use es rather than m if you don't want the base 991 // register to be updated. 992 case 'e': 993 if (Name[1] != 's') 994 return false; 995 // es: A "stable" memory operand; that is, one which does not 996 // include any automodification of the base register. Unlike 997 // `m', this constraint can be used in asm statements that 998 // might access the operand several times, or that might not 999 // access it at all. 1000 Info.setAllowsMemory(); 1001 Name++; // Skip over 'e'. 1002 break; 1003 case 'Q': // Memory operand that is an offset from a register (it is 1004 // usually better to use `m' or `es' in asm statements) 1005 case 'Z': // Memory operand that is an indexed or indirect from a 1006 // register (it is usually better to use `m' or `es' in 1007 // asm statements) 1008 Info.setAllowsMemory(); 1009 Info.setAllowsRegister(); 1010 break; 1011 case 'R': // AIX TOC entry 1012 case 'a': // Address operand that is an indexed or indirect from a 1013 // register (`p' is preferable for asm statements) 1014 case 'S': // Constant suitable as a 64-bit mask operand 1015 case 'T': // Constant suitable as a 32-bit mask operand 1016 case 'U': // System V Release 4 small data area reference 1017 case 't': // AND masks that can be performed by two rldic{l, r} 1018 // instructions 1019 case 'W': // Vector constant that does not require memory 1020 case 'j': // Vector constant that is all zeros. 1021 break; 1022 // End FIXME. 1023 } 1024 return true; 1025 } 1026 std::string convertConstraint(const char *&Constraint) const override { 1027 std::string R; 1028 switch (*Constraint) { 1029 case 'e': 1030 case 'w': 1031 // Two-character constraint; add "^" hint for later parsing. 1032 R = std::string("^") + std::string(Constraint, 2); 1033 Constraint++; 1034 break; 1035 default: 1036 return TargetInfo::convertConstraint(Constraint); 1037 } 1038 return R; 1039 } 1040 const char *getClobbers() const override { 1041 return ""; 1042 } 1043 int getEHDataRegisterNumber(unsigned RegNo) const override { 1044 if (RegNo == 0) return 3; 1045 if (RegNo == 1) return 4; 1046 return -1; 1047 } 1048 1049 bool hasSjLjLowering() const override { 1050 return true; 1051 } 1052 1053 bool useFloat128ManglingForLongDouble() const override { 1054 return LongDoubleWidth == 128 && 1055 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1056 getTriple().isOSBinFormatELF(); 1057 } 1058 }; 1059 1060 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1061 #define BUILTIN(ID, TYPE, ATTRS) \ 1062 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1063 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1064 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1065 #include "clang/Basic/BuiltinsPPC.def" 1066 }; 1067 1068 /// handleTargetFeatures - Perform initialization based on the user 1069 /// configured set of features. 1070 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1071 DiagnosticsEngine &Diags) { 1072 for (const auto &Feature : Features) { 1073 if (Feature == "+vsx") { 1074 HasVSX = true; 1075 } else if (Feature == "+bpermd") { 1076 HasBPERMD = true; 1077 } else if (Feature == "+extdiv") { 1078 HasExtDiv = true; 1079 } else if (Feature == "+power8-vector") { 1080 HasP8Vector = true; 1081 } else if (Feature == "+crypto") { 1082 HasP8Crypto = true; 1083 } else if (Feature == "+direct-move") { 1084 HasDirectMove = true; 1085 } else if (Feature == "+qpx") { 1086 HasQPX = true; 1087 } else if (Feature == "+htm") { 1088 HasHTM = true; 1089 } 1090 // TODO: Finish this list and add an assert that we've handled them 1091 // all. 1092 } 1093 1094 return true; 1095 } 1096 1097 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1098 /// #defines that are not tied to a specific subtarget. 1099 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1100 MacroBuilder &Builder) const { 1101 // Target identification. 1102 Builder.defineMacro("__ppc__"); 1103 Builder.defineMacro("__PPC__"); 1104 Builder.defineMacro("_ARCH_PPC"); 1105 Builder.defineMacro("__powerpc__"); 1106 Builder.defineMacro("__POWERPC__"); 1107 if (PointerWidth == 64) { 1108 Builder.defineMacro("_ARCH_PPC64"); 1109 Builder.defineMacro("__powerpc64__"); 1110 Builder.defineMacro("__ppc64__"); 1111 Builder.defineMacro("__PPC64__"); 1112 } 1113 1114 // Target properties. 1115 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1116 Builder.defineMacro("_LITTLE_ENDIAN"); 1117 } else { 1118 if (getTriple().getOS() != llvm::Triple::NetBSD && 1119 getTriple().getOS() != llvm::Triple::OpenBSD) 1120 Builder.defineMacro("_BIG_ENDIAN"); 1121 } 1122 1123 // ABI options. 1124 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1125 Builder.defineMacro("_CALL_ELF", "1"); 1126 if (ABI == "elfv2") 1127 Builder.defineMacro("_CALL_ELF", "2"); 1128 1129 // Subtarget options. 1130 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1131 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1132 1133 // FIXME: Should be controlled by command line option. 1134 if (LongDoubleWidth == 128) 1135 Builder.defineMacro("__LONG_DOUBLE_128__"); 1136 1137 if (Opts.AltiVec) { 1138 Builder.defineMacro("__VEC__", "10206"); 1139 Builder.defineMacro("__ALTIVEC__"); 1140 } 1141 1142 // CPU identification. 1143 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1144 .Case("440", ArchDefineName) 1145 .Case("450", ArchDefineName | ArchDefine440) 1146 .Case("601", ArchDefineName) 1147 .Case("602", ArchDefineName | ArchDefinePpcgr) 1148 .Case("603", ArchDefineName | ArchDefinePpcgr) 1149 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1150 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1151 .Case("604", ArchDefineName | ArchDefinePpcgr) 1152 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1153 .Case("620", ArchDefineName | ArchDefinePpcgr) 1154 .Case("630", ArchDefineName | ArchDefinePpcgr) 1155 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1156 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1157 .Case("750", ArchDefineName | ArchDefinePpcgr) 1158 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1159 | ArchDefinePpcsq) 1160 .Case("a2", ArchDefineA2) 1161 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1162 .Case("pwr3", ArchDefinePpcgr) 1163 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1164 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1165 | ArchDefinePpcsq) 1166 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1167 | ArchDefinePpcgr | ArchDefinePpcsq) 1168 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1169 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1170 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1171 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1172 | ArchDefinePpcsq) 1173 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1174 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1175 | ArchDefinePpcgr | ArchDefinePpcsq) 1176 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1177 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1178 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1179 .Case("power3", ArchDefinePpcgr) 1180 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1181 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1182 | ArchDefinePpcsq) 1183 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1184 | ArchDefinePpcgr | ArchDefinePpcsq) 1185 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1186 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1187 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1188 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1189 | ArchDefinePpcsq) 1190 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1191 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1192 | ArchDefinePpcgr | ArchDefinePpcsq) 1193 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1194 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1195 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1196 .Default(ArchDefineNone); 1197 1198 if (defs & ArchDefineName) 1199 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1200 if (defs & ArchDefinePpcgr) 1201 Builder.defineMacro("_ARCH_PPCGR"); 1202 if (defs & ArchDefinePpcsq) 1203 Builder.defineMacro("_ARCH_PPCSQ"); 1204 if (defs & ArchDefine440) 1205 Builder.defineMacro("_ARCH_440"); 1206 if (defs & ArchDefine603) 1207 Builder.defineMacro("_ARCH_603"); 1208 if (defs & ArchDefine604) 1209 Builder.defineMacro("_ARCH_604"); 1210 if (defs & ArchDefinePwr4) 1211 Builder.defineMacro("_ARCH_PWR4"); 1212 if (defs & ArchDefinePwr5) 1213 Builder.defineMacro("_ARCH_PWR5"); 1214 if (defs & ArchDefinePwr5x) 1215 Builder.defineMacro("_ARCH_PWR5X"); 1216 if (defs & ArchDefinePwr6) 1217 Builder.defineMacro("_ARCH_PWR6"); 1218 if (defs & ArchDefinePwr6x) 1219 Builder.defineMacro("_ARCH_PWR6X"); 1220 if (defs & ArchDefinePwr7) 1221 Builder.defineMacro("_ARCH_PWR7"); 1222 if (defs & ArchDefinePwr8) 1223 Builder.defineMacro("_ARCH_PWR8"); 1224 if (defs & ArchDefineA2) 1225 Builder.defineMacro("_ARCH_A2"); 1226 if (defs & ArchDefineA2q) { 1227 Builder.defineMacro("_ARCH_A2Q"); 1228 Builder.defineMacro("_ARCH_QP"); 1229 } 1230 1231 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1232 Builder.defineMacro("__bg__"); 1233 Builder.defineMacro("__THW_BLUEGENE__"); 1234 Builder.defineMacro("__bgq__"); 1235 Builder.defineMacro("__TOS_BGQ__"); 1236 } 1237 1238 if (HasVSX) 1239 Builder.defineMacro("__VSX__"); 1240 if (HasP8Vector) 1241 Builder.defineMacro("__POWER8_VECTOR__"); 1242 if (HasP8Crypto) 1243 Builder.defineMacro("__CRYPTO__"); 1244 if (HasHTM) 1245 Builder.defineMacro("__HTM__"); 1246 1247 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1248 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1249 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1250 if (PointerWidth == 64) 1251 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1252 1253 // FIXME: The following are not yet generated here by Clang, but are 1254 // generated by GCC: 1255 // 1256 // _SOFT_FLOAT_ 1257 // __RECIP_PRECISION__ 1258 // __APPLE_ALTIVEC__ 1259 // __RECIP__ 1260 // __RECIPF__ 1261 // __RSQRTE__ 1262 // __RSQRTEF__ 1263 // _SOFT_DOUBLE_ 1264 // __NO_LWSYNC__ 1265 // __HAVE_BSWAP__ 1266 // __LONGDOUBLE128 1267 // __CMODEL_MEDIUM__ 1268 // __CMODEL_LARGE__ 1269 // _CALL_SYSV 1270 // _CALL_DARWIN 1271 // __NO_FPRS__ 1272 } 1273 1274 // Handle explicit options being passed to the compiler here: if we've 1275 // explicitly turned off vsx and turned on power8-vector or direct-move then 1276 // go ahead and error since the customer has expressed a somewhat incompatible 1277 // set of options. 1278 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1279 const std::vector<std::string> &FeaturesVec) { 1280 1281 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1282 FeaturesVec.end()) { 1283 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1284 FeaturesVec.end()) { 1285 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1286 << "-mno-vsx"; 1287 return false; 1288 } 1289 1290 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1291 FeaturesVec.end()) { 1292 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1293 << "-mno-vsx"; 1294 return false; 1295 } 1296 } 1297 1298 return true; 1299 } 1300 1301 bool PPCTargetInfo::initFeatureMap( 1302 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1303 const std::vector<std::string> &FeaturesVec) const { 1304 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1305 .Case("7400", true) 1306 .Case("g4", true) 1307 .Case("7450", true) 1308 .Case("g4+", true) 1309 .Case("970", true) 1310 .Case("g5", true) 1311 .Case("pwr6", true) 1312 .Case("pwr7", true) 1313 .Case("pwr8", true) 1314 .Case("ppc64", true) 1315 .Case("ppc64le", true) 1316 .Default(false); 1317 1318 Features["qpx"] = (CPU == "a2q"); 1319 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1320 .Case("ppc64le", true) 1321 .Case("pwr8", true) 1322 .Default(false); 1323 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1324 .Case("ppc64le", true) 1325 .Case("pwr8", true) 1326 .Default(false); 1327 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1328 .Case("ppc64le", true) 1329 .Case("pwr8", true) 1330 .Case("pwr7", true) 1331 .Default(false); 1332 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1333 .Case("ppc64le", true) 1334 .Case("pwr8", true) 1335 .Case("pwr7", true) 1336 .Default(false); 1337 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1338 .Case("ppc64le", true) 1339 .Case("pwr8", true) 1340 .Default(false); 1341 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1342 .Case("ppc64le", true) 1343 .Case("pwr8", true) 1344 .Case("pwr7", true) 1345 .Default(false); 1346 1347 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1348 return false; 1349 1350 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1351 } 1352 1353 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1354 return llvm::StringSwitch<bool>(Feature) 1355 .Case("powerpc", true) 1356 .Case("vsx", HasVSX) 1357 .Case("power8-vector", HasP8Vector) 1358 .Case("crypto", HasP8Crypto) 1359 .Case("direct-move", HasDirectMove) 1360 .Case("qpx", HasQPX) 1361 .Case("htm", HasHTM) 1362 .Case("bpermd", HasBPERMD) 1363 .Case("extdiv", HasExtDiv) 1364 .Default(false); 1365 } 1366 1367 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1368 StringRef Name, bool Enabled) const { 1369 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1370 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1371 // incompatible options. 1372 if (Enabled) { 1373 if (Name == "vsx") { 1374 Features[Name] = true; 1375 } else if (Name == "direct-move") { 1376 Features[Name] = Features["vsx"] = true; 1377 } else if (Name == "power8-vector") { 1378 Features[Name] = Features["vsx"] = true; 1379 } else { 1380 Features[Name] = true; 1381 } 1382 } else { 1383 if (Name == "vsx") { 1384 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1385 false; 1386 } else { 1387 Features[Name] = false; 1388 } 1389 } 1390 } 1391 1392 const char * const PPCTargetInfo::GCCRegNames[] = { 1393 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1394 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1395 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1396 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1397 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1398 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1399 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1400 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1401 "mq", "lr", "ctr", "ap", 1402 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1403 "xer", 1404 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1405 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1406 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1407 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1408 "vrsave", "vscr", 1409 "spe_acc", "spefscr", 1410 "sfp" 1411 }; 1412 1413 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1414 return llvm::makeArrayRef(GCCRegNames); 1415 } 1416 1417 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1418 // While some of these aliases do map to different registers 1419 // they still share the same register name. 1420 { { "0" }, "r0" }, 1421 { { "1"}, "r1" }, 1422 { { "2" }, "r2" }, 1423 { { "3" }, "r3" }, 1424 { { "4" }, "r4" }, 1425 { { "5" }, "r5" }, 1426 { { "6" }, "r6" }, 1427 { { "7" }, "r7" }, 1428 { { "8" }, "r8" }, 1429 { { "9" }, "r9" }, 1430 { { "10" }, "r10" }, 1431 { { "11" }, "r11" }, 1432 { { "12" }, "r12" }, 1433 { { "13" }, "r13" }, 1434 { { "14" }, "r14" }, 1435 { { "15" }, "r15" }, 1436 { { "16" }, "r16" }, 1437 { { "17" }, "r17" }, 1438 { { "18" }, "r18" }, 1439 { { "19" }, "r19" }, 1440 { { "20" }, "r20" }, 1441 { { "21" }, "r21" }, 1442 { { "22" }, "r22" }, 1443 { { "23" }, "r23" }, 1444 { { "24" }, "r24" }, 1445 { { "25" }, "r25" }, 1446 { { "26" }, "r26" }, 1447 { { "27" }, "r27" }, 1448 { { "28" }, "r28" }, 1449 { { "29" }, "r29" }, 1450 { { "30" }, "r30" }, 1451 { { "31" }, "r31" }, 1452 { { "fr0" }, "f0" }, 1453 { { "fr1" }, "f1" }, 1454 { { "fr2" }, "f2" }, 1455 { { "fr3" }, "f3" }, 1456 { { "fr4" }, "f4" }, 1457 { { "fr5" }, "f5" }, 1458 { { "fr6" }, "f6" }, 1459 { { "fr7" }, "f7" }, 1460 { { "fr8" }, "f8" }, 1461 { { "fr9" }, "f9" }, 1462 { { "fr10" }, "f10" }, 1463 { { "fr11" }, "f11" }, 1464 { { "fr12" }, "f12" }, 1465 { { "fr13" }, "f13" }, 1466 { { "fr14" }, "f14" }, 1467 { { "fr15" }, "f15" }, 1468 { { "fr16" }, "f16" }, 1469 { { "fr17" }, "f17" }, 1470 { { "fr18" }, "f18" }, 1471 { { "fr19" }, "f19" }, 1472 { { "fr20" }, "f20" }, 1473 { { "fr21" }, "f21" }, 1474 { { "fr22" }, "f22" }, 1475 { { "fr23" }, "f23" }, 1476 { { "fr24" }, "f24" }, 1477 { { "fr25" }, "f25" }, 1478 { { "fr26" }, "f26" }, 1479 { { "fr27" }, "f27" }, 1480 { { "fr28" }, "f28" }, 1481 { { "fr29" }, "f29" }, 1482 { { "fr30" }, "f30" }, 1483 { { "fr31" }, "f31" }, 1484 { { "cc" }, "cr0" }, 1485 }; 1486 1487 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1488 return llvm::makeArrayRef(GCCRegAliases); 1489 } 1490 1491 class PPC32TargetInfo : public PPCTargetInfo { 1492 public: 1493 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1494 DataLayoutString = "E-m:e-p:32:32-i64:64-n32"; 1495 1496 switch (getTriple().getOS()) { 1497 case llvm::Triple::Linux: 1498 case llvm::Triple::FreeBSD: 1499 case llvm::Triple::NetBSD: 1500 SizeType = UnsignedInt; 1501 PtrDiffType = SignedInt; 1502 IntPtrType = SignedInt; 1503 break; 1504 default: 1505 break; 1506 } 1507 1508 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1509 LongDoubleWidth = LongDoubleAlign = 64; 1510 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1511 } 1512 1513 // PPC32 supports atomics up to 4 bytes. 1514 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1515 } 1516 1517 BuiltinVaListKind getBuiltinVaListKind() const override { 1518 // This is the ELF definition, and is overridden by the Darwin sub-target 1519 return TargetInfo::PowerABIBuiltinVaList; 1520 } 1521 }; 1522 1523 // Note: ABI differences may eventually require us to have a separate 1524 // TargetInfo for little endian. 1525 class PPC64TargetInfo : public PPCTargetInfo { 1526 public: 1527 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1528 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1529 IntMaxType = SignedLong; 1530 Int64Type = SignedLong; 1531 1532 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1533 DataLayoutString = "e-m:e-i64:64-n32:64"; 1534 ABI = "elfv2"; 1535 } else { 1536 DataLayoutString = "E-m:e-i64:64-n32:64"; 1537 ABI = "elfv1"; 1538 } 1539 1540 switch (getTriple().getOS()) { 1541 case llvm::Triple::FreeBSD: 1542 LongDoubleWidth = LongDoubleAlign = 64; 1543 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1544 break; 1545 case llvm::Triple::NetBSD: 1546 IntMaxType = SignedLongLong; 1547 Int64Type = SignedLongLong; 1548 break; 1549 default: 1550 break; 1551 } 1552 1553 // PPC64 supports atomics up to 8 bytes. 1554 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1555 } 1556 BuiltinVaListKind getBuiltinVaListKind() const override { 1557 return TargetInfo::CharPtrBuiltinVaList; 1558 } 1559 // PPC64 Linux-specific ABI options. 1560 bool setABI(const std::string &Name) override { 1561 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1562 ABI = Name; 1563 return true; 1564 } 1565 return false; 1566 } 1567 }; 1568 1569 class DarwinPPC32TargetInfo : 1570 public DarwinTargetInfo<PPC32TargetInfo> { 1571 public: 1572 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1573 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1574 HasAlignMac68kSupport = true; 1575 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1576 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1577 LongLongAlign = 32; 1578 SuitableAlign = 128; 1579 DataLayoutString = "E-m:o-p:32:32-f64:32:64-n32"; 1580 } 1581 BuiltinVaListKind getBuiltinVaListKind() const override { 1582 return TargetInfo::CharPtrBuiltinVaList; 1583 } 1584 }; 1585 1586 class DarwinPPC64TargetInfo : 1587 public DarwinTargetInfo<PPC64TargetInfo> { 1588 public: 1589 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1590 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1591 HasAlignMac68kSupport = true; 1592 SuitableAlign = 128; 1593 DataLayoutString = "E-m:o-i64:64-n32:64"; 1594 } 1595 }; 1596 1597 static const unsigned NVPTXAddrSpaceMap[] = { 1598 1, // opencl_global 1599 3, // opencl_local 1600 4, // opencl_constant 1601 // FIXME: generic has to be added to the target 1602 0, // opencl_generic 1603 1, // cuda_device 1604 4, // cuda_constant 1605 3, // cuda_shared 1606 }; 1607 1608 class NVPTXTargetInfo : public TargetInfo { 1609 static const char *const GCCRegNames[]; 1610 static const Builtin::Info BuiltinInfo[]; 1611 1612 // The GPU profiles supported by the NVPTX backend 1613 enum GPUKind { 1614 GK_NONE, 1615 GK_SM20, 1616 GK_SM21, 1617 GK_SM30, 1618 GK_SM35, 1619 GK_SM37, 1620 } GPU; 1621 1622 public: 1623 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1624 BigEndian = false; 1625 TLSSupported = false; 1626 LongWidth = LongAlign = 64; 1627 AddrSpaceMap = &NVPTXAddrSpaceMap; 1628 UseAddrSpaceMapMangling = true; 1629 // Define available target features 1630 // These must be defined in sorted order! 1631 NoAsmVariants = true; 1632 // Set the default GPU to sm20 1633 GPU = GK_SM20; 1634 } 1635 void getTargetDefines(const LangOptions &Opts, 1636 MacroBuilder &Builder) const override { 1637 Builder.defineMacro("__PTX__"); 1638 Builder.defineMacro("__NVPTX__"); 1639 if (Opts.CUDAIsDevice) { 1640 // Set __CUDA_ARCH__ for the GPU specified. 1641 std::string CUDAArchCode; 1642 switch (GPU) { 1643 case GK_SM20: 1644 CUDAArchCode = "200"; 1645 break; 1646 case GK_SM21: 1647 CUDAArchCode = "210"; 1648 break; 1649 case GK_SM30: 1650 CUDAArchCode = "300"; 1651 break; 1652 case GK_SM35: 1653 CUDAArchCode = "350"; 1654 break; 1655 case GK_SM37: 1656 CUDAArchCode = "370"; 1657 break; 1658 default: 1659 llvm_unreachable("Unhandled target CPU"); 1660 } 1661 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1662 } 1663 } 1664 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1665 return llvm::makeArrayRef(BuiltinInfo, 1666 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1667 } 1668 bool hasFeature(StringRef Feature) const override { 1669 return Feature == "ptx" || Feature == "nvptx"; 1670 } 1671 1672 ArrayRef<const char *> getGCCRegNames() const override; 1673 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1674 // No aliases. 1675 return None; 1676 } 1677 bool validateAsmConstraint(const char *&Name, 1678 TargetInfo::ConstraintInfo &Info) const override { 1679 switch (*Name) { 1680 default: 1681 return false; 1682 case 'c': 1683 case 'h': 1684 case 'r': 1685 case 'l': 1686 case 'f': 1687 case 'd': 1688 Info.setAllowsRegister(); 1689 return true; 1690 } 1691 } 1692 const char *getClobbers() const override { 1693 // FIXME: Is this really right? 1694 return ""; 1695 } 1696 BuiltinVaListKind getBuiltinVaListKind() const override { 1697 // FIXME: implement 1698 return TargetInfo::CharPtrBuiltinVaList; 1699 } 1700 bool setCPU(const std::string &Name) override { 1701 GPU = llvm::StringSwitch<GPUKind>(Name) 1702 .Case("sm_20", GK_SM20) 1703 .Case("sm_21", GK_SM21) 1704 .Case("sm_30", GK_SM30) 1705 .Case("sm_35", GK_SM35) 1706 .Case("sm_37", GK_SM37) 1707 .Default(GK_NONE); 1708 1709 return GPU != GK_NONE; 1710 } 1711 }; 1712 1713 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1714 #define BUILTIN(ID, TYPE, ATTRS) \ 1715 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1716 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1717 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1718 #include "clang/Basic/BuiltinsNVPTX.def" 1719 }; 1720 1721 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1722 1723 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1724 return llvm::makeArrayRef(GCCRegNames); 1725 } 1726 1727 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1728 public: 1729 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1730 LongWidth = LongAlign = 32; 1731 PointerWidth = PointerAlign = 32; 1732 SizeType = TargetInfo::UnsignedInt; 1733 PtrDiffType = TargetInfo::SignedInt; 1734 IntPtrType = TargetInfo::SignedInt; 1735 DataLayoutString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1736 } 1737 }; 1738 1739 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1740 public: 1741 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1742 PointerWidth = PointerAlign = 64; 1743 SizeType = TargetInfo::UnsignedLong; 1744 PtrDiffType = TargetInfo::SignedLong; 1745 IntPtrType = TargetInfo::SignedLong; 1746 DataLayoutString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1747 } 1748 }; 1749 1750 static const unsigned AMDGPUAddrSpaceMap[] = { 1751 1, // opencl_global 1752 3, // opencl_local 1753 2, // opencl_constant 1754 4, // opencl_generic 1755 1, // cuda_device 1756 2, // cuda_constant 1757 3 // cuda_shared 1758 }; 1759 1760 // If you edit the description strings, make sure you update 1761 // getPointerWidthV(). 1762 1763 static const char *const DataLayoutStringR600 = 1764 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1765 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1766 1767 static const char *const DataLayoutStringR600DoubleOps = 1768 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1769 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1770 1771 static const char *const DataLayoutStringSI = 1772 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1773 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1774 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1775 1776 class AMDGPUTargetInfo : public TargetInfo { 1777 static const Builtin::Info BuiltinInfo[]; 1778 static const char * const GCCRegNames[]; 1779 1780 /// \brief The GPU profiles supported by the AMDGPU target. 1781 enum GPUKind { 1782 GK_NONE, 1783 GK_R600, 1784 GK_R600_DOUBLE_OPS, 1785 GK_R700, 1786 GK_R700_DOUBLE_OPS, 1787 GK_EVERGREEN, 1788 GK_EVERGREEN_DOUBLE_OPS, 1789 GK_NORTHERN_ISLANDS, 1790 GK_CAYMAN, 1791 GK_SOUTHERN_ISLANDS, 1792 GK_SEA_ISLANDS, 1793 GK_VOLCANIC_ISLANDS 1794 } GPU; 1795 1796 bool hasFP64:1; 1797 bool hasFMAF:1; 1798 bool hasLDEXPF:1; 1799 1800 public: 1801 AMDGPUTargetInfo(const llvm::Triple &Triple) 1802 : TargetInfo(Triple) { 1803 1804 if (Triple.getArch() == llvm::Triple::amdgcn) { 1805 DataLayoutString = DataLayoutStringSI; 1806 GPU = GK_SOUTHERN_ISLANDS; 1807 hasFP64 = true; 1808 hasFMAF = true; 1809 hasLDEXPF = true; 1810 } else { 1811 DataLayoutString = DataLayoutStringR600; 1812 GPU = GK_R600; 1813 hasFP64 = false; 1814 hasFMAF = false; 1815 hasLDEXPF = false; 1816 } 1817 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1818 UseAddrSpaceMapMangling = true; 1819 } 1820 1821 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1822 if (GPU <= GK_CAYMAN) 1823 return 32; 1824 1825 switch(AddrSpace) { 1826 default: 1827 return 64; 1828 case 0: 1829 case 3: 1830 case 5: 1831 return 32; 1832 } 1833 } 1834 1835 const char * getClobbers() const override { 1836 return ""; 1837 } 1838 1839 ArrayRef<const char *> getGCCRegNames() const override; 1840 1841 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1842 return None; 1843 } 1844 1845 bool validateAsmConstraint(const char *&Name, 1846 TargetInfo::ConstraintInfo &Info) const override { 1847 switch (*Name) { 1848 default: break; 1849 case 'v': // vgpr 1850 case 's': // sgpr 1851 Info.setAllowsRegister(); 1852 return true; 1853 } 1854 return false; 1855 } 1856 1857 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1858 return llvm::makeArrayRef(BuiltinInfo, 1859 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 1860 } 1861 1862 void getTargetDefines(const LangOptions &Opts, 1863 MacroBuilder &Builder) const override { 1864 Builder.defineMacro("__R600__"); 1865 if (hasFMAF) 1866 Builder.defineMacro("__HAS_FMAF__"); 1867 if (hasLDEXPF) 1868 Builder.defineMacro("__HAS_LDEXPF__"); 1869 if (hasFP64 && Opts.OpenCL) 1870 Builder.defineMacro("cl_khr_fp64"); 1871 if (Opts.OpenCL) { 1872 if (GPU >= GK_NORTHERN_ISLANDS) { 1873 Builder.defineMacro("cl_khr_byte_addressable_store"); 1874 Builder.defineMacro("cl_khr_global_int32_base_atomics"); 1875 Builder.defineMacro("cl_khr_global_int32_extended_atomics"); 1876 Builder.defineMacro("cl_khr_local_int32_base_atomics"); 1877 Builder.defineMacro("cl_khr_local_int32_extended_atomics"); 1878 } 1879 } 1880 } 1881 1882 BuiltinVaListKind getBuiltinVaListKind() const override { 1883 return TargetInfo::CharPtrBuiltinVaList; 1884 } 1885 1886 bool setCPU(const std::string &Name) override { 1887 GPU = llvm::StringSwitch<GPUKind>(Name) 1888 .Case("r600" , GK_R600) 1889 .Case("rv610", GK_R600) 1890 .Case("rv620", GK_R600) 1891 .Case("rv630", GK_R600) 1892 .Case("rv635", GK_R600) 1893 .Case("rs780", GK_R600) 1894 .Case("rs880", GK_R600) 1895 .Case("rv670", GK_R600_DOUBLE_OPS) 1896 .Case("rv710", GK_R700) 1897 .Case("rv730", GK_R700) 1898 .Case("rv740", GK_R700_DOUBLE_OPS) 1899 .Case("rv770", GK_R700_DOUBLE_OPS) 1900 .Case("palm", GK_EVERGREEN) 1901 .Case("cedar", GK_EVERGREEN) 1902 .Case("sumo", GK_EVERGREEN) 1903 .Case("sumo2", GK_EVERGREEN) 1904 .Case("redwood", GK_EVERGREEN) 1905 .Case("juniper", GK_EVERGREEN) 1906 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1907 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1908 .Case("barts", GK_NORTHERN_ISLANDS) 1909 .Case("turks", GK_NORTHERN_ISLANDS) 1910 .Case("caicos", GK_NORTHERN_ISLANDS) 1911 .Case("cayman", GK_CAYMAN) 1912 .Case("aruba", GK_CAYMAN) 1913 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1914 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1915 .Case("verde", GK_SOUTHERN_ISLANDS) 1916 .Case("oland", GK_SOUTHERN_ISLANDS) 1917 .Case("hainan", GK_SOUTHERN_ISLANDS) 1918 .Case("bonaire", GK_SEA_ISLANDS) 1919 .Case("kabini", GK_SEA_ISLANDS) 1920 .Case("kaveri", GK_SEA_ISLANDS) 1921 .Case("hawaii", GK_SEA_ISLANDS) 1922 .Case("mullins", GK_SEA_ISLANDS) 1923 .Case("tonga", GK_VOLCANIC_ISLANDS) 1924 .Case("iceland", GK_VOLCANIC_ISLANDS) 1925 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1926 .Default(GK_NONE); 1927 1928 if (GPU == GK_NONE) { 1929 return false; 1930 } 1931 1932 // Set the correct data layout 1933 switch (GPU) { 1934 case GK_NONE: 1935 case GK_R600: 1936 case GK_R700: 1937 case GK_EVERGREEN: 1938 case GK_NORTHERN_ISLANDS: 1939 DataLayoutString = DataLayoutStringR600; 1940 hasFP64 = false; 1941 hasFMAF = false; 1942 hasLDEXPF = false; 1943 break; 1944 case GK_R600_DOUBLE_OPS: 1945 case GK_R700_DOUBLE_OPS: 1946 case GK_EVERGREEN_DOUBLE_OPS: 1947 case GK_CAYMAN: 1948 DataLayoutString = DataLayoutStringR600DoubleOps; 1949 hasFP64 = true; 1950 hasFMAF = true; 1951 hasLDEXPF = false; 1952 break; 1953 case GK_SOUTHERN_ISLANDS: 1954 case GK_SEA_ISLANDS: 1955 case GK_VOLCANIC_ISLANDS: 1956 DataLayoutString = DataLayoutStringSI; 1957 hasFP64 = true; 1958 hasFMAF = true; 1959 hasLDEXPF = true; 1960 break; 1961 } 1962 1963 return true; 1964 } 1965 }; 1966 1967 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1968 #define BUILTIN(ID, TYPE, ATTRS) \ 1969 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1970 #include "clang/Basic/BuiltinsAMDGPU.def" 1971 }; 1972 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1973 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1974 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1975 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1976 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1977 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1978 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1979 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1980 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1981 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1982 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1983 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1984 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1985 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1986 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1987 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1988 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1989 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1990 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1991 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1992 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 1993 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 1994 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 1995 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 1996 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 1997 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 1998 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 1999 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2000 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2001 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2002 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2003 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2004 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2005 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2006 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2007 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2008 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2009 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2010 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2011 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2012 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2013 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2014 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2015 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2016 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2017 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2018 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2019 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2020 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127" 2021 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi", 2022 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi" 2023 }; 2024 2025 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2026 return llvm::makeArrayRef(GCCRegNames); 2027 } 2028 2029 // Namespace for x86 abstract base class 2030 const Builtin::Info BuiltinInfo[] = { 2031 #define BUILTIN(ID, TYPE, ATTRS) \ 2032 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2033 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2034 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2035 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2036 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2037 #include "clang/Basic/BuiltinsX86.def" 2038 }; 2039 2040 static const char* const GCCRegNames[] = { 2041 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2042 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2043 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2044 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2045 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2046 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2047 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2048 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2049 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2050 }; 2051 2052 const TargetInfo::AddlRegName AddlRegNames[] = { 2053 { { "al", "ah", "eax", "rax" }, 0 }, 2054 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2055 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2056 { { "dl", "dh", "edx", "rdx" }, 1 }, 2057 { { "esi", "rsi" }, 4 }, 2058 { { "edi", "rdi" }, 5 }, 2059 { { "esp", "rsp" }, 7 }, 2060 { { "ebp", "rbp" }, 6 }, 2061 { { "r8d", "r8w", "r8b" }, 38 }, 2062 { { "r9d", "r9w", "r9b" }, 39 }, 2063 { { "r10d", "r10w", "r10b" }, 40 }, 2064 { { "r11d", "r11w", "r11b" }, 41 }, 2065 { { "r12d", "r12w", "r12b" }, 42 }, 2066 { { "r13d", "r13w", "r13b" }, 43 }, 2067 { { "r14d", "r14w", "r14b" }, 44 }, 2068 { { "r15d", "r15w", "r15b" }, 45 }, 2069 }; 2070 2071 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2072 // most of the implementation can be shared. 2073 class X86TargetInfo : public TargetInfo { 2074 enum X86SSEEnum { 2075 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2076 } SSELevel = NoSSE; 2077 enum MMX3DNowEnum { 2078 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2079 } MMX3DNowLevel = NoMMX3DNow; 2080 enum XOPEnum { 2081 NoXOP, 2082 SSE4A, 2083 FMA4, 2084 XOP 2085 } XOPLevel = NoXOP; 2086 2087 bool HasAES = false; 2088 bool HasPCLMUL = false; 2089 bool HasLZCNT = false; 2090 bool HasRDRND = false; 2091 bool HasFSGSBASE = false; 2092 bool HasBMI = false; 2093 bool HasBMI2 = false; 2094 bool HasPOPCNT = false; 2095 bool HasRTM = false; 2096 bool HasPRFCHW = false; 2097 bool HasRDSEED = false; 2098 bool HasADX = false; 2099 bool HasTBM = false; 2100 bool HasFMA = false; 2101 bool HasF16C = false; 2102 bool HasAVX512CD = false; 2103 bool HasAVX512ER = false; 2104 bool HasAVX512PF = false; 2105 bool HasAVX512DQ = false; 2106 bool HasAVX512BW = false; 2107 bool HasAVX512VL = false; 2108 bool HasSHA = false; 2109 bool HasCX16 = false; 2110 bool HasFXSR = false; 2111 bool HasXSAVE = false; 2112 bool HasXSAVEOPT = false; 2113 bool HasXSAVEC = false; 2114 bool HasXSAVES = false; 2115 bool HasPKU = false; 2116 2117 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2118 /// 2119 /// Each enumeration represents a particular CPU supported by Clang. These 2120 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2121 enum CPUKind { 2122 CK_Generic, 2123 2124 /// \name i386 2125 /// i386-generation processors. 2126 //@{ 2127 CK_i386, 2128 //@} 2129 2130 /// \name i486 2131 /// i486-generation processors. 2132 //@{ 2133 CK_i486, 2134 CK_WinChipC6, 2135 CK_WinChip2, 2136 CK_C3, 2137 //@} 2138 2139 /// \name i586 2140 /// i586-generation processors, P5 microarchitecture based. 2141 //@{ 2142 CK_i586, 2143 CK_Pentium, 2144 CK_PentiumMMX, 2145 //@} 2146 2147 /// \name i686 2148 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2149 //@{ 2150 CK_i686, 2151 CK_PentiumPro, 2152 CK_Pentium2, 2153 CK_Pentium3, 2154 CK_Pentium3M, 2155 CK_PentiumM, 2156 CK_C3_2, 2157 2158 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2159 /// Clang however has some logic to suport this. 2160 // FIXME: Warn, deprecate, and potentially remove this. 2161 CK_Yonah, 2162 //@} 2163 2164 /// \name Netburst 2165 /// Netburst microarchitecture based processors. 2166 //@{ 2167 CK_Pentium4, 2168 CK_Pentium4M, 2169 CK_Prescott, 2170 CK_Nocona, 2171 //@} 2172 2173 /// \name Core 2174 /// Core microarchitecture based processors. 2175 //@{ 2176 CK_Core2, 2177 2178 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2179 /// codename which GCC no longer accepts as an option to -march, but Clang 2180 /// has some logic for recognizing it. 2181 // FIXME: Warn, deprecate, and potentially remove this. 2182 CK_Penryn, 2183 //@} 2184 2185 /// \name Atom 2186 /// Atom processors 2187 //@{ 2188 CK_Bonnell, 2189 CK_Silvermont, 2190 //@} 2191 2192 /// \name Nehalem 2193 /// Nehalem microarchitecture based processors. 2194 CK_Nehalem, 2195 2196 /// \name Westmere 2197 /// Westmere microarchitecture based processors. 2198 CK_Westmere, 2199 2200 /// \name Sandy Bridge 2201 /// Sandy Bridge microarchitecture based processors. 2202 CK_SandyBridge, 2203 2204 /// \name Ivy Bridge 2205 /// Ivy Bridge microarchitecture based processors. 2206 CK_IvyBridge, 2207 2208 /// \name Haswell 2209 /// Haswell microarchitecture based processors. 2210 CK_Haswell, 2211 2212 /// \name Broadwell 2213 /// Broadwell microarchitecture based processors. 2214 CK_Broadwell, 2215 2216 /// \name Skylake 2217 /// Skylake microarchitecture based processors. 2218 CK_Skylake, 2219 2220 /// \name Knights Landing 2221 /// Knights Landing processor. 2222 CK_KNL, 2223 2224 /// \name K6 2225 /// K6 architecture processors. 2226 //@{ 2227 CK_K6, 2228 CK_K6_2, 2229 CK_K6_3, 2230 //@} 2231 2232 /// \name K7 2233 /// K7 architecture processors. 2234 //@{ 2235 CK_Athlon, 2236 CK_AthlonThunderbird, 2237 CK_Athlon4, 2238 CK_AthlonXP, 2239 CK_AthlonMP, 2240 //@} 2241 2242 /// \name K8 2243 /// K8 architecture processors. 2244 //@{ 2245 CK_Athlon64, 2246 CK_Athlon64SSE3, 2247 CK_AthlonFX, 2248 CK_K8, 2249 CK_K8SSE3, 2250 CK_Opteron, 2251 CK_OpteronSSE3, 2252 CK_AMDFAM10, 2253 //@} 2254 2255 /// \name Bobcat 2256 /// Bobcat architecture processors. 2257 //@{ 2258 CK_BTVER1, 2259 CK_BTVER2, 2260 //@} 2261 2262 /// \name Bulldozer 2263 /// Bulldozer architecture processors. 2264 //@{ 2265 CK_BDVER1, 2266 CK_BDVER2, 2267 CK_BDVER3, 2268 CK_BDVER4, 2269 //@} 2270 2271 /// This specification is deprecated and will be removed in the future. 2272 /// Users should prefer \see CK_K8. 2273 // FIXME: Warn on this when the CPU is set to it. 2274 //@{ 2275 CK_x86_64, 2276 //@} 2277 2278 /// \name Geode 2279 /// Geode processors. 2280 //@{ 2281 CK_Geode 2282 //@} 2283 } CPU = CK_Generic; 2284 2285 CPUKind getCPUKind(StringRef CPU) const { 2286 return llvm::StringSwitch<CPUKind>(CPU) 2287 .Case("i386", CK_i386) 2288 .Case("i486", CK_i486) 2289 .Case("winchip-c6", CK_WinChipC6) 2290 .Case("winchip2", CK_WinChip2) 2291 .Case("c3", CK_C3) 2292 .Case("i586", CK_i586) 2293 .Case("pentium", CK_Pentium) 2294 .Case("pentium-mmx", CK_PentiumMMX) 2295 .Case("i686", CK_i686) 2296 .Case("pentiumpro", CK_PentiumPro) 2297 .Case("pentium2", CK_Pentium2) 2298 .Case("pentium3", CK_Pentium3) 2299 .Case("pentium3m", CK_Pentium3M) 2300 .Case("pentium-m", CK_PentiumM) 2301 .Case("c3-2", CK_C3_2) 2302 .Case("yonah", CK_Yonah) 2303 .Case("pentium4", CK_Pentium4) 2304 .Case("pentium4m", CK_Pentium4M) 2305 .Case("prescott", CK_Prescott) 2306 .Case("nocona", CK_Nocona) 2307 .Case("core2", CK_Core2) 2308 .Case("penryn", CK_Penryn) 2309 .Case("bonnell", CK_Bonnell) 2310 .Case("atom", CK_Bonnell) // Legacy name. 2311 .Case("silvermont", CK_Silvermont) 2312 .Case("slm", CK_Silvermont) // Legacy name. 2313 .Case("nehalem", CK_Nehalem) 2314 .Case("corei7", CK_Nehalem) // Legacy name. 2315 .Case("westmere", CK_Westmere) 2316 .Case("sandybridge", CK_SandyBridge) 2317 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2318 .Case("ivybridge", CK_IvyBridge) 2319 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2320 .Case("haswell", CK_Haswell) 2321 .Case("core-avx2", CK_Haswell) // Legacy name. 2322 .Case("broadwell", CK_Broadwell) 2323 .Case("skylake", CK_Skylake) 2324 .Case("skx", CK_Skylake) // Legacy name. 2325 .Case("knl", CK_KNL) 2326 .Case("k6", CK_K6) 2327 .Case("k6-2", CK_K6_2) 2328 .Case("k6-3", CK_K6_3) 2329 .Case("athlon", CK_Athlon) 2330 .Case("athlon-tbird", CK_AthlonThunderbird) 2331 .Case("athlon-4", CK_Athlon4) 2332 .Case("athlon-xp", CK_AthlonXP) 2333 .Case("athlon-mp", CK_AthlonMP) 2334 .Case("athlon64", CK_Athlon64) 2335 .Case("athlon64-sse3", CK_Athlon64SSE3) 2336 .Case("athlon-fx", CK_AthlonFX) 2337 .Case("k8", CK_K8) 2338 .Case("k8-sse3", CK_K8SSE3) 2339 .Case("opteron", CK_Opteron) 2340 .Case("opteron-sse3", CK_OpteronSSE3) 2341 .Case("barcelona", CK_AMDFAM10) 2342 .Case("amdfam10", CK_AMDFAM10) 2343 .Case("btver1", CK_BTVER1) 2344 .Case("btver2", CK_BTVER2) 2345 .Case("bdver1", CK_BDVER1) 2346 .Case("bdver2", CK_BDVER2) 2347 .Case("bdver3", CK_BDVER3) 2348 .Case("bdver4", CK_BDVER4) 2349 .Case("x86-64", CK_x86_64) 2350 .Case("geode", CK_Geode) 2351 .Default(CK_Generic); 2352 } 2353 2354 enum FPMathKind { 2355 FP_Default, 2356 FP_SSE, 2357 FP_387 2358 } FPMath = FP_Default; 2359 2360 public: 2361 X86TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 2362 BigEndian = false; 2363 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2364 } 2365 unsigned getFloatEvalMethod() const override { 2366 // X87 evaluates with 80 bits "long double" precision. 2367 return SSELevel == NoSSE ? 2 : 0; 2368 } 2369 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2370 return llvm::makeArrayRef(BuiltinInfo, 2371 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2372 } 2373 ArrayRef<const char *> getGCCRegNames() const override { 2374 return llvm::makeArrayRef(GCCRegNames); 2375 } 2376 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2377 return None; 2378 } 2379 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2380 return llvm::makeArrayRef(AddlRegNames); 2381 } 2382 bool validateCpuSupports(StringRef Name) const override; 2383 bool validateAsmConstraint(const char *&Name, 2384 TargetInfo::ConstraintInfo &info) const override; 2385 2386 bool validateGlobalRegisterVariable(StringRef RegName, 2387 unsigned RegSize, 2388 bool &HasSizeMismatch) const override { 2389 // esp and ebp are the only 32-bit registers the x86 backend can currently 2390 // handle. 2391 if (RegName.equals("esp") || RegName.equals("ebp")) { 2392 // Check that the register size is 32-bit. 2393 HasSizeMismatch = RegSize != 32; 2394 return true; 2395 } 2396 2397 return false; 2398 } 2399 2400 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2401 2402 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2403 2404 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2405 2406 std::string convertConstraint(const char *&Constraint) const override; 2407 const char *getClobbers() const override { 2408 return "~{dirflag},~{fpsr},~{flags}"; 2409 } 2410 void getTargetDefines(const LangOptions &Opts, 2411 MacroBuilder &Builder) const override; 2412 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2413 bool Enabled); 2414 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2415 bool Enabled); 2416 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2417 bool Enabled); 2418 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2419 StringRef Name, bool Enabled) const override { 2420 setFeatureEnabledImpl(Features, Name, Enabled); 2421 } 2422 // This exists purely to cut down on the number of virtual calls in 2423 // initFeatureMap which calls this repeatedly. 2424 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2425 StringRef Name, bool Enabled); 2426 bool 2427 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2428 StringRef CPU, 2429 const std::vector<std::string> &FeaturesVec) const override; 2430 bool hasFeature(StringRef Feature) const override; 2431 bool handleTargetFeatures(std::vector<std::string> &Features, 2432 DiagnosticsEngine &Diags) override; 2433 StringRef getABI() const override { 2434 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2435 return "avx512"; 2436 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2437 return "avx"; 2438 if (getTriple().getArch() == llvm::Triple::x86 && 2439 MMX3DNowLevel == NoMMX3DNow) 2440 return "no-mmx"; 2441 return ""; 2442 } 2443 bool setCPU(const std::string &Name) override { 2444 CPU = getCPUKind(Name); 2445 2446 // Perform any per-CPU checks necessary to determine if this CPU is 2447 // acceptable. 2448 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2449 // invalid without explaining *why*. 2450 switch (CPU) { 2451 case CK_Generic: 2452 // No processor selected! 2453 return false; 2454 2455 case CK_i386: 2456 case CK_i486: 2457 case CK_WinChipC6: 2458 case CK_WinChip2: 2459 case CK_C3: 2460 case CK_i586: 2461 case CK_Pentium: 2462 case CK_PentiumMMX: 2463 case CK_i686: 2464 case CK_PentiumPro: 2465 case CK_Pentium2: 2466 case CK_Pentium3: 2467 case CK_Pentium3M: 2468 case CK_PentiumM: 2469 case CK_Yonah: 2470 case CK_C3_2: 2471 case CK_Pentium4: 2472 case CK_Pentium4M: 2473 case CK_Prescott: 2474 case CK_K6: 2475 case CK_K6_2: 2476 case CK_K6_3: 2477 case CK_Athlon: 2478 case CK_AthlonThunderbird: 2479 case CK_Athlon4: 2480 case CK_AthlonXP: 2481 case CK_AthlonMP: 2482 case CK_Geode: 2483 // Only accept certain architectures when compiling in 32-bit mode. 2484 if (getTriple().getArch() != llvm::Triple::x86) 2485 return false; 2486 2487 // Fallthrough 2488 case CK_Nocona: 2489 case CK_Core2: 2490 case CK_Penryn: 2491 case CK_Bonnell: 2492 case CK_Silvermont: 2493 case CK_Nehalem: 2494 case CK_Westmere: 2495 case CK_SandyBridge: 2496 case CK_IvyBridge: 2497 case CK_Haswell: 2498 case CK_Broadwell: 2499 case CK_Skylake: 2500 case CK_KNL: 2501 case CK_Athlon64: 2502 case CK_Athlon64SSE3: 2503 case CK_AthlonFX: 2504 case CK_K8: 2505 case CK_K8SSE3: 2506 case CK_Opteron: 2507 case CK_OpteronSSE3: 2508 case CK_AMDFAM10: 2509 case CK_BTVER1: 2510 case CK_BTVER2: 2511 case CK_BDVER1: 2512 case CK_BDVER2: 2513 case CK_BDVER3: 2514 case CK_BDVER4: 2515 case CK_x86_64: 2516 return true; 2517 } 2518 llvm_unreachable("Unhandled CPU kind"); 2519 } 2520 2521 bool setFPMath(StringRef Name) override; 2522 2523 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2524 // We accept all non-ARM calling conventions 2525 return (CC == CC_X86ThisCall || 2526 CC == CC_X86FastCall || 2527 CC == CC_X86StdCall || 2528 CC == CC_X86VectorCall || 2529 CC == CC_C || 2530 CC == CC_X86Pascal || 2531 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2532 } 2533 2534 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2535 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2536 } 2537 2538 bool hasSjLjLowering() const override { 2539 return true; 2540 } 2541 }; 2542 2543 bool X86TargetInfo::setFPMath(StringRef Name) { 2544 if (Name == "387") { 2545 FPMath = FP_387; 2546 return true; 2547 } 2548 if (Name == "sse") { 2549 FPMath = FP_SSE; 2550 return true; 2551 } 2552 return false; 2553 } 2554 2555 bool X86TargetInfo::initFeatureMap( 2556 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2557 const std::vector<std::string> &FeaturesVec) const { 2558 // FIXME: This *really* should not be here. 2559 // X86_64 always has SSE2. 2560 if (getTriple().getArch() == llvm::Triple::x86_64) 2561 setFeatureEnabledImpl(Features, "sse2", true); 2562 2563 switch (getCPUKind(CPU)) { 2564 case CK_Generic: 2565 case CK_i386: 2566 case CK_i486: 2567 case CK_i586: 2568 case CK_Pentium: 2569 case CK_i686: 2570 case CK_PentiumPro: 2571 break; 2572 case CK_PentiumMMX: 2573 case CK_Pentium2: 2574 case CK_K6: 2575 case CK_WinChipC6: 2576 setFeatureEnabledImpl(Features, "mmx", true); 2577 break; 2578 case CK_Pentium3: 2579 case CK_Pentium3M: 2580 case CK_C3_2: 2581 setFeatureEnabledImpl(Features, "sse", true); 2582 setFeatureEnabledImpl(Features, "fxsr", true); 2583 break; 2584 case CK_PentiumM: 2585 case CK_Pentium4: 2586 case CK_Pentium4M: 2587 case CK_x86_64: 2588 setFeatureEnabledImpl(Features, "sse2", true); 2589 setFeatureEnabledImpl(Features, "fxsr", true); 2590 break; 2591 case CK_Yonah: 2592 case CK_Prescott: 2593 case CK_Nocona: 2594 setFeatureEnabledImpl(Features, "sse3", true); 2595 setFeatureEnabledImpl(Features, "fxsr", true); 2596 setFeatureEnabledImpl(Features, "cx16", true); 2597 break; 2598 case CK_Core2: 2599 case CK_Bonnell: 2600 setFeatureEnabledImpl(Features, "ssse3", true); 2601 setFeatureEnabledImpl(Features, "fxsr", true); 2602 setFeatureEnabledImpl(Features, "cx16", true); 2603 break; 2604 case CK_Penryn: 2605 setFeatureEnabledImpl(Features, "sse4.1", true); 2606 setFeatureEnabledImpl(Features, "fxsr", true); 2607 setFeatureEnabledImpl(Features, "cx16", true); 2608 break; 2609 case CK_Skylake: 2610 setFeatureEnabledImpl(Features, "avx512f", true); 2611 setFeatureEnabledImpl(Features, "avx512cd", true); 2612 setFeatureEnabledImpl(Features, "avx512dq", true); 2613 setFeatureEnabledImpl(Features, "avx512bw", true); 2614 setFeatureEnabledImpl(Features, "avx512vl", true); 2615 setFeatureEnabledImpl(Features, "xsavec", true); 2616 setFeatureEnabledImpl(Features, "xsaves", true); 2617 setFeatureEnabledImpl(Features, "pku", true); 2618 // FALLTHROUGH 2619 case CK_Broadwell: 2620 setFeatureEnabledImpl(Features, "rdseed", true); 2621 setFeatureEnabledImpl(Features, "adx", true); 2622 // FALLTHROUGH 2623 case CK_Haswell: 2624 setFeatureEnabledImpl(Features, "avx2", true); 2625 setFeatureEnabledImpl(Features, "lzcnt", true); 2626 setFeatureEnabledImpl(Features, "bmi", true); 2627 setFeatureEnabledImpl(Features, "bmi2", true); 2628 setFeatureEnabledImpl(Features, "rtm", true); 2629 setFeatureEnabledImpl(Features, "fma", true); 2630 // FALLTHROUGH 2631 case CK_IvyBridge: 2632 setFeatureEnabledImpl(Features, "rdrnd", true); 2633 setFeatureEnabledImpl(Features, "f16c", true); 2634 setFeatureEnabledImpl(Features, "fsgsbase", true); 2635 // FALLTHROUGH 2636 case CK_SandyBridge: 2637 setFeatureEnabledImpl(Features, "avx", true); 2638 setFeatureEnabledImpl(Features, "xsave", true); 2639 setFeatureEnabledImpl(Features, "xsaveopt", true); 2640 // FALLTHROUGH 2641 case CK_Westmere: 2642 case CK_Silvermont: 2643 setFeatureEnabledImpl(Features, "aes", true); 2644 setFeatureEnabledImpl(Features, "pclmul", true); 2645 // FALLTHROUGH 2646 case CK_Nehalem: 2647 setFeatureEnabledImpl(Features, "sse4.2", true); 2648 setFeatureEnabledImpl(Features, "fxsr", true); 2649 setFeatureEnabledImpl(Features, "cx16", true); 2650 break; 2651 case CK_KNL: 2652 setFeatureEnabledImpl(Features, "avx512f", true); 2653 setFeatureEnabledImpl(Features, "avx512cd", true); 2654 setFeatureEnabledImpl(Features, "avx512er", true); 2655 setFeatureEnabledImpl(Features, "avx512pf", true); 2656 setFeatureEnabledImpl(Features, "fxsr", true); 2657 setFeatureEnabledImpl(Features, "rdseed", true); 2658 setFeatureEnabledImpl(Features, "adx", true); 2659 setFeatureEnabledImpl(Features, "lzcnt", true); 2660 setFeatureEnabledImpl(Features, "bmi", true); 2661 setFeatureEnabledImpl(Features, "bmi2", true); 2662 setFeatureEnabledImpl(Features, "rtm", true); 2663 setFeatureEnabledImpl(Features, "fma", true); 2664 setFeatureEnabledImpl(Features, "rdrnd", true); 2665 setFeatureEnabledImpl(Features, "f16c", true); 2666 setFeatureEnabledImpl(Features, "fsgsbase", true); 2667 setFeatureEnabledImpl(Features, "aes", true); 2668 setFeatureEnabledImpl(Features, "pclmul", true); 2669 setFeatureEnabledImpl(Features, "cx16", true); 2670 setFeatureEnabledImpl(Features, "xsaveopt", true); 2671 setFeatureEnabledImpl(Features, "xsave", true); 2672 break; 2673 case CK_K6_2: 2674 case CK_K6_3: 2675 case CK_WinChip2: 2676 case CK_C3: 2677 setFeatureEnabledImpl(Features, "3dnow", true); 2678 break; 2679 case CK_Athlon: 2680 case CK_AthlonThunderbird: 2681 case CK_Geode: 2682 setFeatureEnabledImpl(Features, "3dnowa", true); 2683 break; 2684 case CK_Athlon4: 2685 case CK_AthlonXP: 2686 case CK_AthlonMP: 2687 setFeatureEnabledImpl(Features, "sse", true); 2688 setFeatureEnabledImpl(Features, "3dnowa", true); 2689 setFeatureEnabledImpl(Features, "fxsr", true); 2690 break; 2691 case CK_K8: 2692 case CK_Opteron: 2693 case CK_Athlon64: 2694 case CK_AthlonFX: 2695 setFeatureEnabledImpl(Features, "sse2", true); 2696 setFeatureEnabledImpl(Features, "3dnowa", true); 2697 setFeatureEnabledImpl(Features, "fxsr", true); 2698 break; 2699 case CK_AMDFAM10: 2700 setFeatureEnabledImpl(Features, "sse4a", true); 2701 setFeatureEnabledImpl(Features, "lzcnt", true); 2702 setFeatureEnabledImpl(Features, "popcnt", true); 2703 // FALLTHROUGH 2704 case CK_K8SSE3: 2705 case CK_OpteronSSE3: 2706 case CK_Athlon64SSE3: 2707 setFeatureEnabledImpl(Features, "sse3", true); 2708 setFeatureEnabledImpl(Features, "3dnowa", true); 2709 setFeatureEnabledImpl(Features, "fxsr", true); 2710 break; 2711 case CK_BTVER2: 2712 setFeatureEnabledImpl(Features, "avx", true); 2713 setFeatureEnabledImpl(Features, "aes", true); 2714 setFeatureEnabledImpl(Features, "pclmul", true); 2715 setFeatureEnabledImpl(Features, "bmi", true); 2716 setFeatureEnabledImpl(Features, "f16c", true); 2717 setFeatureEnabledImpl(Features, "xsaveopt", true); 2718 // FALLTHROUGH 2719 case CK_BTVER1: 2720 setFeatureEnabledImpl(Features, "ssse3", true); 2721 setFeatureEnabledImpl(Features, "sse4a", true); 2722 setFeatureEnabledImpl(Features, "lzcnt", true); 2723 setFeatureEnabledImpl(Features, "popcnt", true); 2724 setFeatureEnabledImpl(Features, "prfchw", true); 2725 setFeatureEnabledImpl(Features, "cx16", true); 2726 setFeatureEnabledImpl(Features, "fxsr", true); 2727 setFeatureEnabledImpl(Features, "xsave", true); 2728 break; 2729 case CK_BDVER4: 2730 setFeatureEnabledImpl(Features, "avx2", true); 2731 setFeatureEnabledImpl(Features, "bmi2", true); 2732 // FALLTHROUGH 2733 case CK_BDVER3: 2734 setFeatureEnabledImpl(Features, "fsgsbase", true); 2735 setFeatureEnabledImpl(Features, "xsaveopt", true); 2736 // FALLTHROUGH 2737 case CK_BDVER2: 2738 setFeatureEnabledImpl(Features, "bmi", true); 2739 setFeatureEnabledImpl(Features, "fma", true); 2740 setFeatureEnabledImpl(Features, "f16c", true); 2741 setFeatureEnabledImpl(Features, "tbm", true); 2742 // FALLTHROUGH 2743 case CK_BDVER1: 2744 // xop implies avx, sse4a and fma4. 2745 setFeatureEnabledImpl(Features, "xop", true); 2746 setFeatureEnabledImpl(Features, "lzcnt", true); 2747 setFeatureEnabledImpl(Features, "aes", true); 2748 setFeatureEnabledImpl(Features, "pclmul", true); 2749 setFeatureEnabledImpl(Features, "prfchw", true); 2750 setFeatureEnabledImpl(Features, "cx16", true); 2751 setFeatureEnabledImpl(Features, "fxsr", true); 2752 setFeatureEnabledImpl(Features, "xsave", true); 2753 break; 2754 } 2755 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 2756 return false; 2757 2758 // Can't do this earlier because we need to be able to explicitly enable 2759 // or disable these features and the things that they depend upon. 2760 2761 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2762 auto I = Features.find("sse4.2"); 2763 if (I != Features.end() && I->getValue() && 2764 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 2765 FeaturesVec.end()) 2766 Features["popcnt"] = true; 2767 2768 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2769 I = Features.find("3dnow"); 2770 if (I != Features.end() && I->getValue() && 2771 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 2772 FeaturesVec.end()) 2773 Features["prfchw"] = true; 2774 2775 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2776 // then enable MMX. 2777 I = Features.find("sse"); 2778 if (I != Features.end() && I->getValue() && 2779 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 2780 FeaturesVec.end()) 2781 Features["mmx"] = true; 2782 2783 return true; 2784 } 2785 2786 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2787 X86SSEEnum Level, bool Enabled) { 2788 if (Enabled) { 2789 switch (Level) { 2790 case AVX512F: 2791 Features["avx512f"] = true; 2792 case AVX2: 2793 Features["avx2"] = true; 2794 case AVX: 2795 Features["avx"] = true; 2796 Features["xsave"] = true; 2797 case SSE42: 2798 Features["sse4.2"] = true; 2799 case SSE41: 2800 Features["sse4.1"] = true; 2801 case SSSE3: 2802 Features["ssse3"] = true; 2803 case SSE3: 2804 Features["sse3"] = true; 2805 case SSE2: 2806 Features["sse2"] = true; 2807 case SSE1: 2808 Features["sse"] = true; 2809 case NoSSE: 2810 break; 2811 } 2812 return; 2813 } 2814 2815 switch (Level) { 2816 case NoSSE: 2817 case SSE1: 2818 Features["sse"] = false; 2819 case SSE2: 2820 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2821 Features["sha"] = false; 2822 case SSE3: 2823 Features["sse3"] = false; 2824 setXOPLevel(Features, NoXOP, false); 2825 case SSSE3: 2826 Features["ssse3"] = false; 2827 case SSE41: 2828 Features["sse4.1"] = false; 2829 case SSE42: 2830 Features["sse4.2"] = false; 2831 case AVX: 2832 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 2833 Features["xsaveopt"] = false; 2834 setXOPLevel(Features, FMA4, false); 2835 case AVX2: 2836 Features["avx2"] = false; 2837 case AVX512F: 2838 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2839 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2840 Features["avx512vl"] = false; 2841 } 2842 } 2843 2844 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2845 MMX3DNowEnum Level, bool Enabled) { 2846 if (Enabled) { 2847 switch (Level) { 2848 case AMD3DNowAthlon: 2849 Features["3dnowa"] = true; 2850 case AMD3DNow: 2851 Features["3dnow"] = true; 2852 case MMX: 2853 Features["mmx"] = true; 2854 case NoMMX3DNow: 2855 break; 2856 } 2857 return; 2858 } 2859 2860 switch (Level) { 2861 case NoMMX3DNow: 2862 case MMX: 2863 Features["mmx"] = false; 2864 case AMD3DNow: 2865 Features["3dnow"] = false; 2866 case AMD3DNowAthlon: 2867 Features["3dnowa"] = false; 2868 } 2869 } 2870 2871 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2872 bool Enabled) { 2873 if (Enabled) { 2874 switch (Level) { 2875 case XOP: 2876 Features["xop"] = true; 2877 case FMA4: 2878 Features["fma4"] = true; 2879 setSSELevel(Features, AVX, true); 2880 case SSE4A: 2881 Features["sse4a"] = true; 2882 setSSELevel(Features, SSE3, true); 2883 case NoXOP: 2884 break; 2885 } 2886 return; 2887 } 2888 2889 switch (Level) { 2890 case NoXOP: 2891 case SSE4A: 2892 Features["sse4a"] = false; 2893 case FMA4: 2894 Features["fma4"] = false; 2895 case XOP: 2896 Features["xop"] = false; 2897 } 2898 } 2899 2900 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2901 StringRef Name, bool Enabled) { 2902 // This is a bit of a hack to deal with the sse4 target feature when used 2903 // as part of the target attribute. We handle sse4 correctly everywhere 2904 // else. See below for more information on how we handle the sse4 options. 2905 if (Name != "sse4") 2906 Features[Name] = Enabled; 2907 2908 if (Name == "mmx") { 2909 setMMXLevel(Features, MMX, Enabled); 2910 } else if (Name == "sse") { 2911 setSSELevel(Features, SSE1, Enabled); 2912 } else if (Name == "sse2") { 2913 setSSELevel(Features, SSE2, Enabled); 2914 } else if (Name == "sse3") { 2915 setSSELevel(Features, SSE3, Enabled); 2916 } else if (Name == "ssse3") { 2917 setSSELevel(Features, SSSE3, Enabled); 2918 } else if (Name == "sse4.2") { 2919 setSSELevel(Features, SSE42, Enabled); 2920 } else if (Name == "sse4.1") { 2921 setSSELevel(Features, SSE41, Enabled); 2922 } else if (Name == "3dnow") { 2923 setMMXLevel(Features, AMD3DNow, Enabled); 2924 } else if (Name == "3dnowa") { 2925 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2926 } else if (Name == "aes") { 2927 if (Enabled) 2928 setSSELevel(Features, SSE2, Enabled); 2929 } else if (Name == "pclmul") { 2930 if (Enabled) 2931 setSSELevel(Features, SSE2, Enabled); 2932 } else if (Name == "avx") { 2933 setSSELevel(Features, AVX, Enabled); 2934 } else if (Name == "avx2") { 2935 setSSELevel(Features, AVX2, Enabled); 2936 } else if (Name == "avx512f") { 2937 setSSELevel(Features, AVX512F, Enabled); 2938 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2939 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2940 if (Enabled) 2941 setSSELevel(Features, AVX512F, Enabled); 2942 } else if (Name == "fma") { 2943 if (Enabled) 2944 setSSELevel(Features, AVX, Enabled); 2945 } else if (Name == "fma4") { 2946 setXOPLevel(Features, FMA4, Enabled); 2947 } else if (Name == "xop") { 2948 setXOPLevel(Features, XOP, Enabled); 2949 } else if (Name == "sse4a") { 2950 setXOPLevel(Features, SSE4A, Enabled); 2951 } else if (Name == "f16c") { 2952 if (Enabled) 2953 setSSELevel(Features, AVX, Enabled); 2954 } else if (Name == "sha") { 2955 if (Enabled) 2956 setSSELevel(Features, SSE2, Enabled); 2957 } else if (Name == "sse4") { 2958 // We can get here via the __target__ attribute since that's not controlled 2959 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 2960 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 2961 // disabled. 2962 if (Enabled) 2963 setSSELevel(Features, SSE42, Enabled); 2964 else 2965 setSSELevel(Features, SSE41, Enabled); 2966 } else if (Name == "xsave") { 2967 if (Enabled) 2968 setSSELevel(Features, AVX, Enabled); 2969 else 2970 Features["xsaveopt"] = false; 2971 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 2972 if (Enabled) { 2973 Features["xsave"] = true; 2974 setSSELevel(Features, AVX, Enabled); 2975 } 2976 } 2977 } 2978 2979 /// handleTargetFeatures - Perform initialization based on the user 2980 /// configured set of features. 2981 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2982 DiagnosticsEngine &Diags) { 2983 for (const auto &Feature : Features) { 2984 if (Feature[0] != '+') 2985 continue; 2986 2987 if (Feature == "+aes") { 2988 HasAES = true; 2989 } else if (Feature == "+pclmul") { 2990 HasPCLMUL = true; 2991 } else if (Feature == "+lzcnt") { 2992 HasLZCNT = true; 2993 } else if (Feature == "+rdrnd") { 2994 HasRDRND = true; 2995 } else if (Feature == "+fsgsbase") { 2996 HasFSGSBASE = true; 2997 } else if (Feature == "+bmi") { 2998 HasBMI = true; 2999 } else if (Feature == "+bmi2") { 3000 HasBMI2 = true; 3001 } else if (Feature == "+popcnt") { 3002 HasPOPCNT = true; 3003 } else if (Feature == "+rtm") { 3004 HasRTM = true; 3005 } else if (Feature == "+prfchw") { 3006 HasPRFCHW = true; 3007 } else if (Feature == "+rdseed") { 3008 HasRDSEED = true; 3009 } else if (Feature == "+adx") { 3010 HasADX = true; 3011 } else if (Feature == "+tbm") { 3012 HasTBM = true; 3013 } else if (Feature == "+fma") { 3014 HasFMA = true; 3015 } else if (Feature == "+f16c") { 3016 HasF16C = true; 3017 } else if (Feature == "+avx512cd") { 3018 HasAVX512CD = true; 3019 } else if (Feature == "+avx512er") { 3020 HasAVX512ER = true; 3021 } else if (Feature == "+avx512pf") { 3022 HasAVX512PF = true; 3023 } else if (Feature == "+avx512dq") { 3024 HasAVX512DQ = true; 3025 } else if (Feature == "+avx512bw") { 3026 HasAVX512BW = true; 3027 } else if (Feature == "+avx512vl") { 3028 HasAVX512VL = true; 3029 } else if (Feature == "+sha") { 3030 HasSHA = true; 3031 } else if (Feature == "+cx16") { 3032 HasCX16 = true; 3033 } else if (Feature == "+fxsr") { 3034 HasFXSR = true; 3035 } else if (Feature == "+xsave") { 3036 HasXSAVE = true; 3037 } else if (Feature == "+xsaveopt") { 3038 HasXSAVEOPT = true; 3039 } else if (Feature == "+xsavec") { 3040 HasXSAVEC = true; 3041 } else if (Feature == "+xsaves") { 3042 HasXSAVES = true; 3043 } else if (Feature == "+pku") { 3044 HasPKU = true; 3045 } 3046 3047 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3048 .Case("+avx512f", AVX512F) 3049 .Case("+avx2", AVX2) 3050 .Case("+avx", AVX) 3051 .Case("+sse4.2", SSE42) 3052 .Case("+sse4.1", SSE41) 3053 .Case("+ssse3", SSSE3) 3054 .Case("+sse3", SSE3) 3055 .Case("+sse2", SSE2) 3056 .Case("+sse", SSE1) 3057 .Default(NoSSE); 3058 SSELevel = std::max(SSELevel, Level); 3059 3060 MMX3DNowEnum ThreeDNowLevel = 3061 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3062 .Case("+3dnowa", AMD3DNowAthlon) 3063 .Case("+3dnow", AMD3DNow) 3064 .Case("+mmx", MMX) 3065 .Default(NoMMX3DNow); 3066 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3067 3068 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3069 .Case("+xop", XOP) 3070 .Case("+fma4", FMA4) 3071 .Case("+sse4a", SSE4A) 3072 .Default(NoXOP); 3073 XOPLevel = std::max(XOPLevel, XLevel); 3074 } 3075 3076 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3077 // matches the selected sse level. 3078 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3079 (FPMath == FP_387 && SSELevel >= SSE1)) { 3080 Diags.Report(diag::err_target_unsupported_fpmath) << 3081 (FPMath == FP_SSE ? "sse" : "387"); 3082 return false; 3083 } 3084 3085 SimdDefaultAlign = 3086 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3087 return true; 3088 } 3089 3090 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3091 /// definitions for this particular subtarget. 3092 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3093 MacroBuilder &Builder) const { 3094 // Target identification. 3095 if (getTriple().getArch() == llvm::Triple::x86_64) { 3096 Builder.defineMacro("__amd64__"); 3097 Builder.defineMacro("__amd64"); 3098 Builder.defineMacro("__x86_64"); 3099 Builder.defineMacro("__x86_64__"); 3100 if (getTriple().getArchName() == "x86_64h") { 3101 Builder.defineMacro("__x86_64h"); 3102 Builder.defineMacro("__x86_64h__"); 3103 } 3104 } else { 3105 DefineStd(Builder, "i386", Opts); 3106 } 3107 3108 // Subtarget options. 3109 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3110 // truly should be based on -mtune options. 3111 switch (CPU) { 3112 case CK_Generic: 3113 break; 3114 case CK_i386: 3115 // The rest are coming from the i386 define above. 3116 Builder.defineMacro("__tune_i386__"); 3117 break; 3118 case CK_i486: 3119 case CK_WinChipC6: 3120 case CK_WinChip2: 3121 case CK_C3: 3122 defineCPUMacros(Builder, "i486"); 3123 break; 3124 case CK_PentiumMMX: 3125 Builder.defineMacro("__pentium_mmx__"); 3126 Builder.defineMacro("__tune_pentium_mmx__"); 3127 // Fallthrough 3128 case CK_i586: 3129 case CK_Pentium: 3130 defineCPUMacros(Builder, "i586"); 3131 defineCPUMacros(Builder, "pentium"); 3132 break; 3133 case CK_Pentium3: 3134 case CK_Pentium3M: 3135 case CK_PentiumM: 3136 Builder.defineMacro("__tune_pentium3__"); 3137 // Fallthrough 3138 case CK_Pentium2: 3139 case CK_C3_2: 3140 Builder.defineMacro("__tune_pentium2__"); 3141 // Fallthrough 3142 case CK_PentiumPro: 3143 Builder.defineMacro("__tune_i686__"); 3144 Builder.defineMacro("__tune_pentiumpro__"); 3145 // Fallthrough 3146 case CK_i686: 3147 Builder.defineMacro("__i686"); 3148 Builder.defineMacro("__i686__"); 3149 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3150 Builder.defineMacro("__pentiumpro"); 3151 Builder.defineMacro("__pentiumpro__"); 3152 break; 3153 case CK_Pentium4: 3154 case CK_Pentium4M: 3155 defineCPUMacros(Builder, "pentium4"); 3156 break; 3157 case CK_Yonah: 3158 case CK_Prescott: 3159 case CK_Nocona: 3160 defineCPUMacros(Builder, "nocona"); 3161 break; 3162 case CK_Core2: 3163 case CK_Penryn: 3164 defineCPUMacros(Builder, "core2"); 3165 break; 3166 case CK_Bonnell: 3167 defineCPUMacros(Builder, "atom"); 3168 break; 3169 case CK_Silvermont: 3170 defineCPUMacros(Builder, "slm"); 3171 break; 3172 case CK_Nehalem: 3173 case CK_Westmere: 3174 case CK_SandyBridge: 3175 case CK_IvyBridge: 3176 case CK_Haswell: 3177 case CK_Broadwell: 3178 // FIXME: Historically, we defined this legacy name, it would be nice to 3179 // remove it at some point. We've never exposed fine-grained names for 3180 // recent primary x86 CPUs, and we should keep it that way. 3181 defineCPUMacros(Builder, "corei7"); 3182 break; 3183 case CK_Skylake: 3184 // FIXME: Historically, we defined this legacy name, it would be nice to 3185 // remove it at some point. This is the only fine-grained CPU macro in the 3186 // main intel CPU line, and it would be better to not have these and force 3187 // people to use ISA macros. 3188 defineCPUMacros(Builder, "skx"); 3189 break; 3190 case CK_KNL: 3191 defineCPUMacros(Builder, "knl"); 3192 break; 3193 case CK_K6_2: 3194 Builder.defineMacro("__k6_2__"); 3195 Builder.defineMacro("__tune_k6_2__"); 3196 // Fallthrough 3197 case CK_K6_3: 3198 if (CPU != CK_K6_2) { // In case of fallthrough 3199 // FIXME: GCC may be enabling these in cases where some other k6 3200 // architecture is specified but -m3dnow is explicitly provided. The 3201 // exact semantics need to be determined and emulated here. 3202 Builder.defineMacro("__k6_3__"); 3203 Builder.defineMacro("__tune_k6_3__"); 3204 } 3205 // Fallthrough 3206 case CK_K6: 3207 defineCPUMacros(Builder, "k6"); 3208 break; 3209 case CK_Athlon: 3210 case CK_AthlonThunderbird: 3211 case CK_Athlon4: 3212 case CK_AthlonXP: 3213 case CK_AthlonMP: 3214 defineCPUMacros(Builder, "athlon"); 3215 if (SSELevel != NoSSE) { 3216 Builder.defineMacro("__athlon_sse__"); 3217 Builder.defineMacro("__tune_athlon_sse__"); 3218 } 3219 break; 3220 case CK_K8: 3221 case CK_K8SSE3: 3222 case CK_x86_64: 3223 case CK_Opteron: 3224 case CK_OpteronSSE3: 3225 case CK_Athlon64: 3226 case CK_Athlon64SSE3: 3227 case CK_AthlonFX: 3228 defineCPUMacros(Builder, "k8"); 3229 break; 3230 case CK_AMDFAM10: 3231 defineCPUMacros(Builder, "amdfam10"); 3232 break; 3233 case CK_BTVER1: 3234 defineCPUMacros(Builder, "btver1"); 3235 break; 3236 case CK_BTVER2: 3237 defineCPUMacros(Builder, "btver2"); 3238 break; 3239 case CK_BDVER1: 3240 defineCPUMacros(Builder, "bdver1"); 3241 break; 3242 case CK_BDVER2: 3243 defineCPUMacros(Builder, "bdver2"); 3244 break; 3245 case CK_BDVER3: 3246 defineCPUMacros(Builder, "bdver3"); 3247 break; 3248 case CK_BDVER4: 3249 defineCPUMacros(Builder, "bdver4"); 3250 break; 3251 case CK_Geode: 3252 defineCPUMacros(Builder, "geode"); 3253 break; 3254 } 3255 3256 // Target properties. 3257 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3258 3259 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3260 // functions in glibc header files that use FP Stack inline asm which the 3261 // backend can't deal with (PR879). 3262 Builder.defineMacro("__NO_MATH_INLINES"); 3263 3264 if (HasAES) 3265 Builder.defineMacro("__AES__"); 3266 3267 if (HasPCLMUL) 3268 Builder.defineMacro("__PCLMUL__"); 3269 3270 if (HasLZCNT) 3271 Builder.defineMacro("__LZCNT__"); 3272 3273 if (HasRDRND) 3274 Builder.defineMacro("__RDRND__"); 3275 3276 if (HasFSGSBASE) 3277 Builder.defineMacro("__FSGSBASE__"); 3278 3279 if (HasBMI) 3280 Builder.defineMacro("__BMI__"); 3281 3282 if (HasBMI2) 3283 Builder.defineMacro("__BMI2__"); 3284 3285 if (HasPOPCNT) 3286 Builder.defineMacro("__POPCNT__"); 3287 3288 if (HasRTM) 3289 Builder.defineMacro("__RTM__"); 3290 3291 if (HasPRFCHW) 3292 Builder.defineMacro("__PRFCHW__"); 3293 3294 if (HasRDSEED) 3295 Builder.defineMacro("__RDSEED__"); 3296 3297 if (HasADX) 3298 Builder.defineMacro("__ADX__"); 3299 3300 if (HasTBM) 3301 Builder.defineMacro("__TBM__"); 3302 3303 switch (XOPLevel) { 3304 case XOP: 3305 Builder.defineMacro("__XOP__"); 3306 case FMA4: 3307 Builder.defineMacro("__FMA4__"); 3308 case SSE4A: 3309 Builder.defineMacro("__SSE4A__"); 3310 case NoXOP: 3311 break; 3312 } 3313 3314 if (HasFMA) 3315 Builder.defineMacro("__FMA__"); 3316 3317 if (HasF16C) 3318 Builder.defineMacro("__F16C__"); 3319 3320 if (HasAVX512CD) 3321 Builder.defineMacro("__AVX512CD__"); 3322 if (HasAVX512ER) 3323 Builder.defineMacro("__AVX512ER__"); 3324 if (HasAVX512PF) 3325 Builder.defineMacro("__AVX512PF__"); 3326 if (HasAVX512DQ) 3327 Builder.defineMacro("__AVX512DQ__"); 3328 if (HasAVX512BW) 3329 Builder.defineMacro("__AVX512BW__"); 3330 if (HasAVX512VL) 3331 Builder.defineMacro("__AVX512VL__"); 3332 3333 if (HasSHA) 3334 Builder.defineMacro("__SHA__"); 3335 3336 if (HasFXSR) 3337 Builder.defineMacro("__FXSR__"); 3338 if (HasXSAVE) 3339 Builder.defineMacro("__XSAVE__"); 3340 if (HasXSAVEOPT) 3341 Builder.defineMacro("__XSAVEOPT__"); 3342 if (HasXSAVEC) 3343 Builder.defineMacro("__XSAVEC__"); 3344 if (HasXSAVES) 3345 Builder.defineMacro("__XSAVES__"); 3346 if (HasPKU) 3347 Builder.defineMacro("__PKU__"); 3348 if (HasCX16) 3349 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3350 3351 // Each case falls through to the previous one here. 3352 switch (SSELevel) { 3353 case AVX512F: 3354 Builder.defineMacro("__AVX512F__"); 3355 case AVX2: 3356 Builder.defineMacro("__AVX2__"); 3357 case AVX: 3358 Builder.defineMacro("__AVX__"); 3359 case SSE42: 3360 Builder.defineMacro("__SSE4_2__"); 3361 case SSE41: 3362 Builder.defineMacro("__SSE4_1__"); 3363 case SSSE3: 3364 Builder.defineMacro("__SSSE3__"); 3365 case SSE3: 3366 Builder.defineMacro("__SSE3__"); 3367 case SSE2: 3368 Builder.defineMacro("__SSE2__"); 3369 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3370 case SSE1: 3371 Builder.defineMacro("__SSE__"); 3372 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3373 case NoSSE: 3374 break; 3375 } 3376 3377 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3378 switch (SSELevel) { 3379 case AVX512F: 3380 case AVX2: 3381 case AVX: 3382 case SSE42: 3383 case SSE41: 3384 case SSSE3: 3385 case SSE3: 3386 case SSE2: 3387 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3388 break; 3389 case SSE1: 3390 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3391 break; 3392 default: 3393 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3394 } 3395 } 3396 3397 // Each case falls through to the previous one here. 3398 switch (MMX3DNowLevel) { 3399 case AMD3DNowAthlon: 3400 Builder.defineMacro("__3dNOW_A__"); 3401 case AMD3DNow: 3402 Builder.defineMacro("__3dNOW__"); 3403 case MMX: 3404 Builder.defineMacro("__MMX__"); 3405 case NoMMX3DNow: 3406 break; 3407 } 3408 3409 if (CPU >= CK_i486) { 3410 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3411 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3412 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3413 } 3414 if (CPU >= CK_i586) 3415 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3416 } 3417 3418 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3419 return llvm::StringSwitch<bool>(Feature) 3420 .Case("aes", HasAES) 3421 .Case("avx", SSELevel >= AVX) 3422 .Case("avx2", SSELevel >= AVX2) 3423 .Case("avx512f", SSELevel >= AVX512F) 3424 .Case("avx512cd", HasAVX512CD) 3425 .Case("avx512er", HasAVX512ER) 3426 .Case("avx512pf", HasAVX512PF) 3427 .Case("avx512dq", HasAVX512DQ) 3428 .Case("avx512bw", HasAVX512BW) 3429 .Case("avx512vl", HasAVX512VL) 3430 .Case("bmi", HasBMI) 3431 .Case("bmi2", HasBMI2) 3432 .Case("cx16", HasCX16) 3433 .Case("f16c", HasF16C) 3434 .Case("fma", HasFMA) 3435 .Case("fma4", XOPLevel >= FMA4) 3436 .Case("fsgsbase", HasFSGSBASE) 3437 .Case("fxsr", HasFXSR) 3438 .Case("lzcnt", HasLZCNT) 3439 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3440 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3441 .Case("mmx", MMX3DNowLevel >= MMX) 3442 .Case("pclmul", HasPCLMUL) 3443 .Case("popcnt", HasPOPCNT) 3444 .Case("prfchw", HasPRFCHW) 3445 .Case("rdrnd", HasRDRND) 3446 .Case("rdseed", HasRDSEED) 3447 .Case("rtm", HasRTM) 3448 .Case("sha", HasSHA) 3449 .Case("sse", SSELevel >= SSE1) 3450 .Case("sse2", SSELevel >= SSE2) 3451 .Case("sse3", SSELevel >= SSE3) 3452 .Case("ssse3", SSELevel >= SSSE3) 3453 .Case("sse4.1", SSELevel >= SSE41) 3454 .Case("sse4.2", SSELevel >= SSE42) 3455 .Case("sse4a", XOPLevel >= SSE4A) 3456 .Case("tbm", HasTBM) 3457 .Case("x86", true) 3458 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3459 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3460 .Case("xop", XOPLevel >= XOP) 3461 .Case("xsave", HasXSAVE) 3462 .Case("xsavec", HasXSAVEC) 3463 .Case("xsaves", HasXSAVES) 3464 .Case("xsaveopt", HasXSAVEOPT) 3465 .Case("pku", HasPKU) 3466 .Default(false); 3467 } 3468 3469 // We can't use a generic validation scheme for the features accepted here 3470 // versus subtarget features accepted in the target attribute because the 3471 // bitfield structure that's initialized in the runtime only supports the 3472 // below currently rather than the full range of subtarget features. (See 3473 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3474 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3475 return llvm::StringSwitch<bool>(FeatureStr) 3476 .Case("cmov", true) 3477 .Case("mmx", true) 3478 .Case("popcnt", true) 3479 .Case("sse", true) 3480 .Case("sse2", true) 3481 .Case("sse3", true) 3482 .Case("sse4.1", true) 3483 .Case("sse4.2", true) 3484 .Case("avx", true) 3485 .Case("avx2", true) 3486 .Case("sse4a", true) 3487 .Case("fma4", true) 3488 .Case("xop", true) 3489 .Case("fma", true) 3490 .Case("avx512f", true) 3491 .Case("bmi", true) 3492 .Case("bmi2", true) 3493 .Default(false); 3494 } 3495 3496 bool 3497 X86TargetInfo::validateAsmConstraint(const char *&Name, 3498 TargetInfo::ConstraintInfo &Info) const { 3499 switch (*Name) { 3500 default: return false; 3501 // Constant constraints. 3502 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3503 // instructions. 3504 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3505 // x86_64 instructions. 3506 case 's': 3507 Info.setRequiresImmediate(); 3508 return true; 3509 case 'I': 3510 Info.setRequiresImmediate(0, 31); 3511 return true; 3512 case 'J': 3513 Info.setRequiresImmediate(0, 63); 3514 return true; 3515 case 'K': 3516 Info.setRequiresImmediate(-128, 127); 3517 return true; 3518 case 'L': 3519 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3520 return true; 3521 case 'M': 3522 Info.setRequiresImmediate(0, 3); 3523 return true; 3524 case 'N': 3525 Info.setRequiresImmediate(0, 255); 3526 return true; 3527 case 'O': 3528 Info.setRequiresImmediate(0, 127); 3529 return true; 3530 // Register constraints. 3531 case 'Y': // 'Y' is the first character for several 2-character constraints. 3532 // Shift the pointer to the second character of the constraint. 3533 Name++; 3534 switch (*Name) { 3535 default: 3536 return false; 3537 case '0': // First SSE register. 3538 case 't': // Any SSE register, when SSE2 is enabled. 3539 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3540 case 'm': // Any MMX register, when inter-unit moves enabled. 3541 Info.setAllowsRegister(); 3542 return true; 3543 } 3544 case 'f': // Any x87 floating point stack register. 3545 // Constraint 'f' cannot be used for output operands. 3546 if (Info.ConstraintStr[0] == '=') 3547 return false; 3548 Info.setAllowsRegister(); 3549 return true; 3550 case 'a': // eax. 3551 case 'b': // ebx. 3552 case 'c': // ecx. 3553 case 'd': // edx. 3554 case 'S': // esi. 3555 case 'D': // edi. 3556 case 'A': // edx:eax. 3557 case 't': // Top of floating point stack. 3558 case 'u': // Second from top of floating point stack. 3559 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3560 case 'y': // Any MMX register. 3561 case 'x': // Any SSE register. 3562 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3563 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3564 case 'l': // "Index" registers: any general register that can be used as an 3565 // index in a base+index memory access. 3566 Info.setAllowsRegister(); 3567 return true; 3568 // Floating point constant constraints. 3569 case 'C': // SSE floating point constant. 3570 case 'G': // x87 floating point constant. 3571 return true; 3572 } 3573 } 3574 3575 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3576 unsigned Size) const { 3577 // Strip off constraint modifiers. 3578 while (Constraint[0] == '=' || 3579 Constraint[0] == '+' || 3580 Constraint[0] == '&') 3581 Constraint = Constraint.substr(1); 3582 3583 return validateOperandSize(Constraint, Size); 3584 } 3585 3586 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3587 unsigned Size) const { 3588 return validateOperandSize(Constraint, Size); 3589 } 3590 3591 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3592 unsigned Size) const { 3593 switch (Constraint[0]) { 3594 default: break; 3595 case 'y': 3596 return Size <= 64; 3597 case 'f': 3598 case 't': 3599 case 'u': 3600 return Size <= 128; 3601 case 'x': 3602 if (SSELevel >= AVX512F) 3603 // 512-bit zmm registers can be used if target supports AVX512F. 3604 return Size <= 512U; 3605 else if (SSELevel >= AVX) 3606 // 256-bit ymm registers can be used if target supports AVX. 3607 return Size <= 256U; 3608 return Size <= 128U; 3609 case 'Y': 3610 // 'Y' is the first character for several 2-character constraints. 3611 switch (Constraint[1]) { 3612 default: break; 3613 case 'm': 3614 // 'Ym' is synonymous with 'y'. 3615 return Size <= 64; 3616 case 'i': 3617 case 't': 3618 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3619 if (SSELevel >= AVX512F) 3620 return Size <= 512U; 3621 else if (SSELevel >= AVX) 3622 return Size <= 256U; 3623 return SSELevel >= SSE2 && Size <= 128U; 3624 } 3625 3626 } 3627 3628 return true; 3629 } 3630 3631 std::string 3632 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3633 switch (*Constraint) { 3634 case 'a': return std::string("{ax}"); 3635 case 'b': return std::string("{bx}"); 3636 case 'c': return std::string("{cx}"); 3637 case 'd': return std::string("{dx}"); 3638 case 'S': return std::string("{si}"); 3639 case 'D': return std::string("{di}"); 3640 case 'p': // address 3641 return std::string("im"); 3642 case 't': // top of floating point stack. 3643 return std::string("{st}"); 3644 case 'u': // second from top of floating point stack. 3645 return std::string("{st(1)}"); // second from top of floating point stack. 3646 default: 3647 return std::string(1, *Constraint); 3648 } 3649 } 3650 3651 // X86-32 generic target 3652 class X86_32TargetInfo : public X86TargetInfo { 3653 public: 3654 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3655 DoubleAlign = LongLongAlign = 32; 3656 LongDoubleWidth = 96; 3657 LongDoubleAlign = 32; 3658 SuitableAlign = 128; 3659 DataLayoutString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3660 SizeType = UnsignedInt; 3661 PtrDiffType = SignedInt; 3662 IntPtrType = SignedInt; 3663 RegParmMax = 3; 3664 3665 // Use fpret for all types. 3666 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3667 (1 << TargetInfo::Double) | 3668 (1 << TargetInfo::LongDouble)); 3669 3670 // x86-32 has atomics up to 8 bytes 3671 // FIXME: Check that we actually have cmpxchg8b before setting 3672 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3673 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3674 } 3675 BuiltinVaListKind getBuiltinVaListKind() const override { 3676 return TargetInfo::CharPtrBuiltinVaList; 3677 } 3678 3679 int getEHDataRegisterNumber(unsigned RegNo) const override { 3680 if (RegNo == 0) return 0; 3681 if (RegNo == 1) return 2; 3682 return -1; 3683 } 3684 bool validateOperandSize(StringRef Constraint, 3685 unsigned Size) const override { 3686 switch (Constraint[0]) { 3687 default: break; 3688 case 'R': 3689 case 'q': 3690 case 'Q': 3691 case 'a': 3692 case 'b': 3693 case 'c': 3694 case 'd': 3695 case 'S': 3696 case 'D': 3697 return Size <= 32; 3698 case 'A': 3699 return Size <= 64; 3700 } 3701 3702 return X86TargetInfo::validateOperandSize(Constraint, Size); 3703 } 3704 }; 3705 3706 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3707 public: 3708 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3709 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3710 3711 unsigned getFloatEvalMethod() const override { 3712 unsigned Major, Minor, Micro; 3713 getTriple().getOSVersion(Major, Minor, Micro); 3714 // New NetBSD uses the default rounding mode. 3715 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3716 return X86_32TargetInfo::getFloatEvalMethod(); 3717 // NetBSD before 6.99.26 defaults to "double" rounding. 3718 return 1; 3719 } 3720 }; 3721 3722 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3723 public: 3724 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3725 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3726 SizeType = UnsignedLong; 3727 IntPtrType = SignedLong; 3728 PtrDiffType = SignedLong; 3729 } 3730 }; 3731 3732 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3733 public: 3734 BitrigI386TargetInfo(const llvm::Triple &Triple) 3735 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3736 SizeType = UnsignedLong; 3737 IntPtrType = SignedLong; 3738 PtrDiffType = SignedLong; 3739 } 3740 }; 3741 3742 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3743 public: 3744 DarwinI386TargetInfo(const llvm::Triple &Triple) 3745 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3746 LongDoubleWidth = 128; 3747 LongDoubleAlign = 128; 3748 SuitableAlign = 128; 3749 MaxVectorAlign = 256; 3750 // The watchOS simulator uses the builtin bool type for Objective-C. 3751 llvm::Triple T = llvm::Triple(Triple); 3752 if (T.isWatchOS()) 3753 UseSignedCharForObjCBool = false; 3754 SizeType = UnsignedLong; 3755 IntPtrType = SignedLong; 3756 DataLayoutString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3757 HasAlignMac68kSupport = true; 3758 } 3759 3760 bool handleTargetFeatures(std::vector<std::string> &Features, 3761 DiagnosticsEngine &Diags) override { 3762 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 3763 Diags)) 3764 return false; 3765 // We now know the features we have: we can decide how to align vectors. 3766 MaxVectorAlign = 3767 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3768 return true; 3769 } 3770 }; 3771 3772 // x86-32 Windows target 3773 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3774 public: 3775 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3776 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3777 WCharType = UnsignedShort; 3778 DoubleAlign = LongLongAlign = 64; 3779 bool IsWinCOFF = 3780 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3781 DataLayoutString = IsWinCOFF 3782 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3783 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3784 } 3785 void getTargetDefines(const LangOptions &Opts, 3786 MacroBuilder &Builder) const override { 3787 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3788 } 3789 }; 3790 3791 // x86-32 Windows Visual Studio target 3792 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3793 public: 3794 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3795 : WindowsX86_32TargetInfo(Triple) { 3796 LongDoubleWidth = LongDoubleAlign = 64; 3797 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3798 } 3799 void getTargetDefines(const LangOptions &Opts, 3800 MacroBuilder &Builder) const override { 3801 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3802 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3803 // The value of the following reflects processor type. 3804 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3805 // We lost the original triple, so we use the default. 3806 Builder.defineMacro("_M_IX86", "600"); 3807 } 3808 }; 3809 3810 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3811 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 3812 // supports __declspec natively under -fms-extensions, but we define a no-op 3813 // __declspec macro anyway for pre-processor compatibility. 3814 if (Opts.MicrosoftExt) 3815 Builder.defineMacro("__declspec", "__declspec"); 3816 else 3817 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3818 3819 if (!Opts.MicrosoftExt) { 3820 // Provide macros for all the calling convention keywords. Provide both 3821 // single and double underscore prefixed variants. These are available on 3822 // x64 as well as x86, even though they have no effect. 3823 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3824 for (const char *CC : CCs) { 3825 std::string GCCSpelling = "__attribute__((__"; 3826 GCCSpelling += CC; 3827 GCCSpelling += "__))"; 3828 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3829 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3830 } 3831 } 3832 } 3833 3834 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3835 Builder.defineMacro("__MSVCRT__"); 3836 Builder.defineMacro("__MINGW32__"); 3837 addCygMingDefines(Opts, Builder); 3838 } 3839 3840 // x86-32 MinGW target 3841 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3842 public: 3843 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3844 : WindowsX86_32TargetInfo(Triple) {} 3845 void getTargetDefines(const LangOptions &Opts, 3846 MacroBuilder &Builder) const override { 3847 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3848 DefineStd(Builder, "WIN32", Opts); 3849 DefineStd(Builder, "WINNT", Opts); 3850 Builder.defineMacro("_X86_"); 3851 addMinGWDefines(Opts, Builder); 3852 } 3853 }; 3854 3855 // x86-32 Cygwin target 3856 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3857 public: 3858 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3859 : X86_32TargetInfo(Triple) { 3860 WCharType = UnsignedShort; 3861 DoubleAlign = LongLongAlign = 64; 3862 DataLayoutString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3863 } 3864 void getTargetDefines(const LangOptions &Opts, 3865 MacroBuilder &Builder) const override { 3866 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3867 Builder.defineMacro("_X86_"); 3868 Builder.defineMacro("__CYGWIN__"); 3869 Builder.defineMacro("__CYGWIN32__"); 3870 addCygMingDefines(Opts, Builder); 3871 DefineStd(Builder, "unix", Opts); 3872 if (Opts.CPlusPlus) 3873 Builder.defineMacro("_GNU_SOURCE"); 3874 } 3875 }; 3876 3877 // x86-32 Haiku target 3878 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3879 public: 3880 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3881 SizeType = UnsignedLong; 3882 IntPtrType = SignedLong; 3883 PtrDiffType = SignedLong; 3884 ProcessIDType = SignedLong; 3885 this->UserLabelPrefix = ""; 3886 this->TLSSupported = false; 3887 } 3888 void getTargetDefines(const LangOptions &Opts, 3889 MacroBuilder &Builder) const override { 3890 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3891 Builder.defineMacro("__INTEL__"); 3892 Builder.defineMacro("__HAIKU__"); 3893 } 3894 }; 3895 3896 // X86-32 MCU target 3897 class MCUX86_32TargetInfo : public X86_32TargetInfo { 3898 public: 3899 MCUX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3900 LongDoubleWidth = 64; 3901 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3902 UserLabelPrefix = ""; 3903 } 3904 3905 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3906 // On MCU we support only C calling convention. 3907 return CC == CC_C ? CCCR_OK : CCCR_Warning; 3908 } 3909 3910 void getTargetDefines(const LangOptions &Opts, 3911 MacroBuilder &Builder) const override { 3912 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3913 Builder.defineMacro("__iamcu"); 3914 Builder.defineMacro("__iamcu__"); 3915 } 3916 }; 3917 3918 // RTEMS Target 3919 template<typename Target> 3920 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3921 protected: 3922 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3923 MacroBuilder &Builder) const override { 3924 // RTEMS defines; list based off of gcc output 3925 3926 Builder.defineMacro("__rtems__"); 3927 Builder.defineMacro("__ELF__"); 3928 } 3929 3930 public: 3931 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3932 this->UserLabelPrefix = ""; 3933 3934 switch (Triple.getArch()) { 3935 default: 3936 case llvm::Triple::x86: 3937 // this->MCountName = ".mcount"; 3938 break; 3939 case llvm::Triple::mips: 3940 case llvm::Triple::mipsel: 3941 case llvm::Triple::ppc: 3942 case llvm::Triple::ppc64: 3943 case llvm::Triple::ppc64le: 3944 // this->MCountName = "_mcount"; 3945 break; 3946 case llvm::Triple::arm: 3947 // this->MCountName = "__mcount"; 3948 break; 3949 } 3950 } 3951 }; 3952 3953 // x86-32 RTEMS target 3954 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3955 public: 3956 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3957 SizeType = UnsignedLong; 3958 IntPtrType = SignedLong; 3959 PtrDiffType = SignedLong; 3960 this->UserLabelPrefix = ""; 3961 } 3962 void getTargetDefines(const LangOptions &Opts, 3963 MacroBuilder &Builder) const override { 3964 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3965 Builder.defineMacro("__INTEL__"); 3966 Builder.defineMacro("__rtems__"); 3967 } 3968 }; 3969 3970 // x86-64 generic target 3971 class X86_64TargetInfo : public X86TargetInfo { 3972 public: 3973 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3974 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3975 bool IsWinCOFF = 3976 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3977 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3978 LongDoubleWidth = 128; 3979 LongDoubleAlign = 128; 3980 LargeArrayMinWidth = 128; 3981 LargeArrayAlign = 128; 3982 SuitableAlign = 128; 3983 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3984 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3985 IntPtrType = IsX32 ? SignedInt : SignedLong; 3986 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3987 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3988 RegParmMax = 6; 3989 3990 // Pointers are 32-bit in x32. 3991 DataLayoutString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3992 : IsWinCOFF 3993 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 3994 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3995 3996 // Use fpret only for long double. 3997 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3998 3999 // Use fp2ret for _Complex long double. 4000 ComplexLongDoubleUsesFP2Ret = true; 4001 4002 // Make __builtin_ms_va_list available. 4003 HasBuiltinMSVaList = true; 4004 4005 // x86-64 has atomics up to 16 bytes. 4006 MaxAtomicPromoteWidth = 128; 4007 MaxAtomicInlineWidth = 128; 4008 } 4009 BuiltinVaListKind getBuiltinVaListKind() const override { 4010 return TargetInfo::X86_64ABIBuiltinVaList; 4011 } 4012 4013 int getEHDataRegisterNumber(unsigned RegNo) const override { 4014 if (RegNo == 0) return 0; 4015 if (RegNo == 1) return 1; 4016 return -1; 4017 } 4018 4019 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4020 return (CC == CC_C || 4021 CC == CC_X86VectorCall || 4022 CC == CC_IntelOclBicc || 4023 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 4024 } 4025 4026 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4027 return CC_C; 4028 } 4029 4030 // for x32 we need it here explicitly 4031 bool hasInt128Type() const override { return true; } 4032 4033 bool validateGlobalRegisterVariable(StringRef RegName, 4034 unsigned RegSize, 4035 bool &HasSizeMismatch) const override { 4036 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4037 // handle. 4038 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4039 // Check that the register size is 64-bit. 4040 HasSizeMismatch = RegSize != 64; 4041 return true; 4042 } 4043 4044 // Check if the register is a 32-bit register the backend can handle. 4045 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4046 HasSizeMismatch); 4047 } 4048 }; 4049 4050 // x86-64 Windows target 4051 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4052 public: 4053 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 4054 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 4055 WCharType = UnsignedShort; 4056 LongWidth = LongAlign = 32; 4057 DoubleAlign = LongLongAlign = 64; 4058 IntMaxType = SignedLongLong; 4059 Int64Type = SignedLongLong; 4060 SizeType = UnsignedLongLong; 4061 PtrDiffType = SignedLongLong; 4062 IntPtrType = SignedLongLong; 4063 this->UserLabelPrefix = ""; 4064 } 4065 4066 void getTargetDefines(const LangOptions &Opts, 4067 MacroBuilder &Builder) const override { 4068 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4069 Builder.defineMacro("_WIN64"); 4070 } 4071 4072 BuiltinVaListKind getBuiltinVaListKind() const override { 4073 return TargetInfo::CharPtrBuiltinVaList; 4074 } 4075 4076 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4077 switch (CC) { 4078 case CC_X86StdCall: 4079 case CC_X86ThisCall: 4080 case CC_X86FastCall: 4081 return CCCR_Ignore; 4082 case CC_C: 4083 case CC_X86VectorCall: 4084 case CC_IntelOclBicc: 4085 case CC_X86_64SysV: 4086 return CCCR_OK; 4087 default: 4088 return CCCR_Warning; 4089 } 4090 } 4091 }; 4092 4093 // x86-64 Windows Visual Studio target 4094 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4095 public: 4096 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 4097 : WindowsX86_64TargetInfo(Triple) { 4098 LongDoubleWidth = LongDoubleAlign = 64; 4099 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4100 } 4101 void getTargetDefines(const LangOptions &Opts, 4102 MacroBuilder &Builder) const override { 4103 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4104 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4105 Builder.defineMacro("_M_X64", "100"); 4106 Builder.defineMacro("_M_AMD64", "100"); 4107 } 4108 }; 4109 4110 // x86-64 MinGW target 4111 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4112 public: 4113 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 4114 : WindowsX86_64TargetInfo(Triple) { 4115 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4116 // with x86 FP ops. Weird. 4117 LongDoubleWidth = LongDoubleAlign = 128; 4118 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4119 } 4120 4121 void getTargetDefines(const LangOptions &Opts, 4122 MacroBuilder &Builder) const override { 4123 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4124 DefineStd(Builder, "WIN64", Opts); 4125 Builder.defineMacro("__MINGW64__"); 4126 addMinGWDefines(Opts, Builder); 4127 4128 // GCC defines this macro when it is using __gxx_personality_seh0. 4129 if (!Opts.SjLjExceptions) 4130 Builder.defineMacro("__SEH__"); 4131 } 4132 }; 4133 4134 // x86-64 Cygwin target 4135 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4136 public: 4137 CygwinX86_64TargetInfo(const llvm::Triple &Triple) 4138 : X86_64TargetInfo(Triple) { 4139 TLSSupported = false; 4140 WCharType = UnsignedShort; 4141 } 4142 void getTargetDefines(const LangOptions &Opts, 4143 MacroBuilder &Builder) const override { 4144 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4145 Builder.defineMacro("__x86_64__"); 4146 Builder.defineMacro("__CYGWIN__"); 4147 Builder.defineMacro("__CYGWIN64__"); 4148 addCygMingDefines(Opts, Builder); 4149 DefineStd(Builder, "unix", Opts); 4150 if (Opts.CPlusPlus) 4151 Builder.defineMacro("_GNU_SOURCE"); 4152 4153 // GCC defines this macro when it is using __gxx_personality_seh0. 4154 if (!Opts.SjLjExceptions) 4155 Builder.defineMacro("__SEH__"); 4156 } 4157 }; 4158 4159 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4160 public: 4161 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 4162 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 4163 Int64Type = SignedLongLong; 4164 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4165 llvm::Triple T = llvm::Triple(Triple); 4166 if (T.isiOS()) 4167 UseSignedCharForObjCBool = false; 4168 DataLayoutString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 4169 } 4170 4171 bool handleTargetFeatures(std::vector<std::string> &Features, 4172 DiagnosticsEngine &Diags) override { 4173 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4174 Diags)) 4175 return false; 4176 // We now know the features we have: we can decide how to align vectors. 4177 MaxVectorAlign = 4178 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4179 return true; 4180 } 4181 }; 4182 4183 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4184 public: 4185 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 4186 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 4187 IntMaxType = SignedLongLong; 4188 Int64Type = SignedLongLong; 4189 } 4190 }; 4191 4192 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4193 public: 4194 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 4195 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 4196 IntMaxType = SignedLongLong; 4197 Int64Type = SignedLongLong; 4198 } 4199 }; 4200 4201 class ARMTargetInfo : public TargetInfo { 4202 // Possible FPU choices. 4203 enum FPUMode { 4204 VFP2FPU = (1 << 0), 4205 VFP3FPU = (1 << 1), 4206 VFP4FPU = (1 << 2), 4207 NeonFPU = (1 << 3), 4208 FPARMV8 = (1 << 4) 4209 }; 4210 4211 // Possible HWDiv features. 4212 enum HWDivMode { 4213 HWDivThumb = (1 << 0), 4214 HWDivARM = (1 << 1) 4215 }; 4216 4217 static bool FPUModeIsVFP(FPUMode Mode) { 4218 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4219 } 4220 4221 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4222 static const char * const GCCRegNames[]; 4223 4224 std::string ABI, CPU; 4225 4226 StringRef CPUProfile; 4227 StringRef CPUAttr; 4228 4229 enum { 4230 FP_Default, 4231 FP_VFP, 4232 FP_Neon 4233 } FPMath; 4234 4235 unsigned ArchISA; 4236 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4237 unsigned ArchProfile; 4238 unsigned ArchVersion; 4239 4240 unsigned FPU : 5; 4241 4242 unsigned IsAAPCS : 1; 4243 unsigned HWDiv : 2; 4244 4245 // Initialized via features. 4246 unsigned SoftFloat : 1; 4247 unsigned SoftFloatABI : 1; 4248 4249 unsigned CRC : 1; 4250 unsigned Crypto : 1; 4251 unsigned DSP : 1; 4252 unsigned Unaligned : 1; 4253 4254 enum { 4255 LDREX_B = (1 << 0), /// byte (8-bit) 4256 LDREX_H = (1 << 1), /// half (16-bit) 4257 LDREX_W = (1 << 2), /// word (32-bit) 4258 LDREX_D = (1 << 3), /// double (64-bit) 4259 }; 4260 4261 uint32_t LDREX; 4262 4263 // ACLE 6.5.1 Hardware floating point 4264 enum { 4265 HW_FP_HP = (1 << 1), /// half (16-bit) 4266 HW_FP_SP = (1 << 2), /// single (32-bit) 4267 HW_FP_DP = (1 << 3), /// double (64-bit) 4268 }; 4269 uint32_t HW_FP; 4270 4271 static const Builtin::Info BuiltinInfo[]; 4272 4273 void setABIAAPCS() { 4274 IsAAPCS = true; 4275 4276 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4277 const llvm::Triple &T = getTriple(); 4278 4279 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4280 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4281 T.getOS() == llvm::Triple::Bitrig) 4282 SizeType = UnsignedLong; 4283 else 4284 SizeType = UnsignedInt; 4285 4286 switch (T.getOS()) { 4287 case llvm::Triple::NetBSD: 4288 WCharType = SignedInt; 4289 break; 4290 case llvm::Triple::Win32: 4291 WCharType = UnsignedShort; 4292 break; 4293 case llvm::Triple::Linux: 4294 default: 4295 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4296 WCharType = UnsignedInt; 4297 break; 4298 } 4299 4300 UseBitFieldTypeAlignment = true; 4301 4302 ZeroLengthBitfieldBoundary = 0; 4303 4304 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4305 // so set preferred for small types to 32. 4306 if (T.isOSBinFormatMachO()) { 4307 DataLayoutString = 4308 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4309 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4310 } else if (T.isOSWindows()) { 4311 assert(!BigEndian && "Windows on ARM does not support big endian"); 4312 DataLayoutString = "e" 4313 "-m:w" 4314 "-p:32:32" 4315 "-i64:64" 4316 "-v128:64:128" 4317 "-a:0:32" 4318 "-n32" 4319 "-S64"; 4320 } else if (T.isOSNaCl()) { 4321 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4322 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 4323 } else { 4324 DataLayoutString = 4325 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4326 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4327 } 4328 4329 // FIXME: Enumerated types are variable width in straight AAPCS. 4330 } 4331 4332 void setABIAPCS(bool IsAAPCS16) { 4333 const llvm::Triple &T = getTriple(); 4334 4335 IsAAPCS = false; 4336 4337 if (IsAAPCS16) 4338 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4339 else 4340 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4341 4342 // size_t is unsigned int on FreeBSD. 4343 if (T.getOS() == llvm::Triple::FreeBSD) 4344 SizeType = UnsignedInt; 4345 else 4346 SizeType = UnsignedLong; 4347 4348 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4349 WCharType = SignedInt; 4350 4351 // Do not respect the alignment of bit-field types when laying out 4352 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4353 UseBitFieldTypeAlignment = false; 4354 4355 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4356 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4357 /// gcc. 4358 ZeroLengthBitfieldBoundary = 32; 4359 4360 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4361 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4362 DataLayoutString = "e-m:o-p:32:32-i64:64-a:0:32-n32-S128"; 4363 } else if (T.isOSBinFormatMachO()) 4364 DataLayoutString = 4365 BigEndian 4366 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4367 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4368 else 4369 DataLayoutString = 4370 BigEndian 4371 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4372 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4373 4374 // FIXME: Override "preferred align" for double and long long. 4375 } 4376 4377 void setArchInfo() { 4378 StringRef ArchName = getTriple().getArchName(); 4379 4380 ArchISA = llvm::ARM::parseArchISA(ArchName); 4381 CPU = llvm::ARM::getDefaultCPU(ArchName); 4382 unsigned AK = llvm::ARM::parseArch(ArchName); 4383 if (AK != llvm::ARM::AK_INVALID) 4384 ArchKind = AK; 4385 setArchInfo(ArchKind); 4386 } 4387 4388 void setArchInfo(unsigned Kind) { 4389 StringRef SubArch; 4390 4391 // cache TargetParser info 4392 ArchKind = Kind; 4393 SubArch = llvm::ARM::getSubArch(ArchKind); 4394 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4395 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4396 4397 // cache CPU related strings 4398 CPUAttr = getCPUAttr(); 4399 CPUProfile = getCPUProfile(); 4400 } 4401 4402 void setAtomic() { 4403 // when triple does not specify a sub arch, 4404 // then we are not using inline atomics 4405 bool ShouldUseInlineAtomic = 4406 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4407 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4408 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4409 if (ArchProfile == llvm::ARM::PK_M) { 4410 MaxAtomicPromoteWidth = 32; 4411 if (ShouldUseInlineAtomic) 4412 MaxAtomicInlineWidth = 32; 4413 } 4414 else { 4415 MaxAtomicPromoteWidth = 64; 4416 if (ShouldUseInlineAtomic) 4417 MaxAtomicInlineWidth = 64; 4418 } 4419 } 4420 4421 bool isThumb() const { 4422 return (ArchISA == llvm::ARM::IK_THUMB); 4423 } 4424 4425 bool supportsThumb() const { 4426 return CPUAttr.count('T') || ArchVersion >= 6; 4427 } 4428 4429 bool supportsThumb2() const { 4430 return CPUAttr.equals("6T2") || ArchVersion >= 7; 4431 } 4432 4433 StringRef getCPUAttr() const { 4434 // For most sub-arches, the build attribute CPU name is enough. 4435 // For Cortex variants, it's slightly different. 4436 switch(ArchKind) { 4437 default: 4438 return llvm::ARM::getCPUAttr(ArchKind); 4439 case llvm::ARM::AK_ARMV6M: 4440 return "6M"; 4441 case llvm::ARM::AK_ARMV7S: 4442 return "7S"; 4443 case llvm::ARM::AK_ARMV7A: 4444 return "7A"; 4445 case llvm::ARM::AK_ARMV7R: 4446 return "7R"; 4447 case llvm::ARM::AK_ARMV7M: 4448 return "7M"; 4449 case llvm::ARM::AK_ARMV7EM: 4450 return "7EM"; 4451 case llvm::ARM::AK_ARMV8A: 4452 return "8A"; 4453 case llvm::ARM::AK_ARMV8_1A: 4454 return "8_1A"; 4455 } 4456 } 4457 4458 StringRef getCPUProfile() const { 4459 switch(ArchProfile) { 4460 case llvm::ARM::PK_A: 4461 return "A"; 4462 case llvm::ARM::PK_R: 4463 return "R"; 4464 case llvm::ARM::PK_M: 4465 return "M"; 4466 default: 4467 return ""; 4468 } 4469 } 4470 4471 public: 4472 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4473 : TargetInfo(Triple), FPMath(FP_Default), 4474 IsAAPCS(true), LDREX(0), HW_FP(0) { 4475 BigEndian = IsBigEndian; 4476 4477 switch (getTriple().getOS()) { 4478 case llvm::Triple::NetBSD: 4479 PtrDiffType = SignedLong; 4480 break; 4481 default: 4482 PtrDiffType = SignedInt; 4483 break; 4484 } 4485 4486 // Cache arch related info. 4487 setArchInfo(); 4488 4489 // {} in inline assembly are neon specifiers, not assembly variant 4490 // specifiers. 4491 NoAsmVariants = true; 4492 4493 // FIXME: This duplicates code from the driver that sets the -target-abi 4494 // option - this code is used if -target-abi isn't passed and should 4495 // be unified in some way. 4496 if (Triple.isOSBinFormatMachO()) { 4497 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4498 // the frontend matches that. 4499 if (Triple.getEnvironment() == llvm::Triple::EABI || 4500 Triple.getOS() == llvm::Triple::UnknownOS || 4501 StringRef(CPU).startswith("cortex-m")) { 4502 setABI("aapcs"); 4503 } else if (Triple.isWatchABI()) { 4504 setABI("aapcs16"); 4505 } else { 4506 setABI("apcs-gnu"); 4507 } 4508 } else if (Triple.isOSWindows()) { 4509 // FIXME: this is invalid for WindowsCE 4510 setABI("aapcs"); 4511 } else { 4512 // Select the default based on the platform. 4513 switch (Triple.getEnvironment()) { 4514 case llvm::Triple::Android: 4515 case llvm::Triple::GNUEABI: 4516 case llvm::Triple::GNUEABIHF: 4517 setABI("aapcs-linux"); 4518 break; 4519 case llvm::Triple::EABIHF: 4520 case llvm::Triple::EABI: 4521 setABI("aapcs"); 4522 break; 4523 case llvm::Triple::GNU: 4524 setABI("apcs-gnu"); 4525 break; 4526 default: 4527 if (Triple.getOS() == llvm::Triple::NetBSD) 4528 setABI("apcs-gnu"); 4529 else 4530 setABI("aapcs"); 4531 break; 4532 } 4533 } 4534 4535 // ARM targets default to using the ARM C++ ABI. 4536 TheCXXABI.set(TargetCXXABI::GenericARM); 4537 4538 // ARM has atomics up to 8 bytes 4539 setAtomic(); 4540 4541 // Do force alignment of members that follow zero length bitfields. If 4542 // the alignment of the zero-length bitfield is greater than the member 4543 // that follows it, `bar', `bar' will be aligned as the type of the 4544 // zero length bitfield. 4545 UseZeroLengthBitfieldAlignment = true; 4546 } 4547 4548 StringRef getABI() const override { return ABI; } 4549 4550 bool setABI(const std::string &Name) override { 4551 ABI = Name; 4552 4553 // The defaults (above) are for AAPCS, check if we need to change them. 4554 // 4555 // FIXME: We need support for -meabi... we could just mangle it into the 4556 // name. 4557 if (Name == "apcs-gnu" || Name == "aapcs16") { 4558 setABIAPCS(Name == "aapcs16"); 4559 return true; 4560 } 4561 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4562 setABIAAPCS(); 4563 return true; 4564 } 4565 return false; 4566 } 4567 4568 // FIXME: This should be based on Arch attributes, not CPU names. 4569 bool 4570 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4571 StringRef CPU, 4572 const std::vector<std::string> &FeaturesVec) const override { 4573 4574 std::vector<const char*> TargetFeatures; 4575 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4576 4577 // get default FPU features 4578 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4579 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4580 4581 // get default Extension features 4582 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 4583 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4584 4585 for (const char *Feature : TargetFeatures) 4586 if (Feature[0] == '+') 4587 Features[Feature+1] = true; 4588 4589 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4590 } 4591 4592 bool handleTargetFeatures(std::vector<std::string> &Features, 4593 DiagnosticsEngine &Diags) override { 4594 FPU = 0; 4595 CRC = 0; 4596 Crypto = 0; 4597 DSP = 0; 4598 Unaligned = 1; 4599 SoftFloat = SoftFloatABI = false; 4600 HWDiv = 0; 4601 4602 // This does not diagnose illegal cases like having both 4603 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4604 uint32_t HW_FP_remove = 0; 4605 for (const auto &Feature : Features) { 4606 if (Feature == "+soft-float") { 4607 SoftFloat = true; 4608 } else if (Feature == "+soft-float-abi") { 4609 SoftFloatABI = true; 4610 } else if (Feature == "+vfp2") { 4611 FPU |= VFP2FPU; 4612 HW_FP |= HW_FP_SP | HW_FP_DP; 4613 } else if (Feature == "+vfp3") { 4614 FPU |= VFP3FPU; 4615 HW_FP |= HW_FP_SP | HW_FP_DP; 4616 } else if (Feature == "+vfp4") { 4617 FPU |= VFP4FPU; 4618 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4619 } else if (Feature == "+fp-armv8") { 4620 FPU |= FPARMV8; 4621 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4622 } else if (Feature == "+neon") { 4623 FPU |= NeonFPU; 4624 HW_FP |= HW_FP_SP | HW_FP_DP; 4625 } else if (Feature == "+hwdiv") { 4626 HWDiv |= HWDivThumb; 4627 } else if (Feature == "+hwdiv-arm") { 4628 HWDiv |= HWDivARM; 4629 } else if (Feature == "+crc") { 4630 CRC = 1; 4631 } else if (Feature == "+crypto") { 4632 Crypto = 1; 4633 } else if (Feature == "+dsp") { 4634 DSP = 1; 4635 } else if (Feature == "+fp-only-sp") { 4636 HW_FP_remove |= HW_FP_DP; 4637 } else if (Feature == "+strict-align") { 4638 Unaligned = 0; 4639 } else if (Feature == "+fp16") { 4640 HW_FP |= HW_FP_HP; 4641 } 4642 } 4643 HW_FP &= ~HW_FP_remove; 4644 4645 switch (ArchVersion) { 4646 case 6: 4647 if (ArchProfile == llvm::ARM::PK_M) 4648 LDREX = 0; 4649 else if (ArchKind == llvm::ARM::AK_ARMV6K) 4650 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4651 else 4652 LDREX = LDREX_W; 4653 break; 4654 case 7: 4655 if (ArchProfile == llvm::ARM::PK_M) 4656 LDREX = LDREX_W | LDREX_H | LDREX_B ; 4657 else 4658 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4659 break; 4660 case 8: 4661 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4662 } 4663 4664 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4665 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4666 return false; 4667 } 4668 4669 if (FPMath == FP_Neon) 4670 Features.push_back("+neonfp"); 4671 else if (FPMath == FP_VFP) 4672 Features.push_back("-neonfp"); 4673 4674 // Remove front-end specific options which the backend handles differently. 4675 auto Feature = 4676 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4677 if (Feature != Features.end()) 4678 Features.erase(Feature); 4679 4680 return true; 4681 } 4682 4683 bool hasFeature(StringRef Feature) const override { 4684 return llvm::StringSwitch<bool>(Feature) 4685 .Case("arm", true) 4686 .Case("aarch32", true) 4687 .Case("softfloat", SoftFloat) 4688 .Case("thumb", isThumb()) 4689 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4690 .Case("hwdiv", HWDiv & HWDivThumb) 4691 .Case("hwdiv-arm", HWDiv & HWDivARM) 4692 .Default(false); 4693 } 4694 4695 bool setCPU(const std::string &Name) override { 4696 if (Name != "generic") 4697 setArchInfo(llvm::ARM::parseCPUArch(Name)); 4698 4699 if (ArchKind == llvm::ARM::AK_INVALID) 4700 return false; 4701 setAtomic(); 4702 CPU = Name; 4703 return true; 4704 } 4705 4706 bool setFPMath(StringRef Name) override; 4707 4708 void getTargetDefines(const LangOptions &Opts, 4709 MacroBuilder &Builder) const override { 4710 // Target identification. 4711 Builder.defineMacro("__arm"); 4712 Builder.defineMacro("__arm__"); 4713 4714 // Target properties. 4715 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4716 4717 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 4718 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 4719 if (getTriple().isWatchABI()) 4720 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 4721 4722 if (!CPUAttr.empty()) 4723 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 4724 4725 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4726 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4727 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 4728 4729 if (ArchVersion >= 8) { 4730 // ACLE 6.5.7 Crypto Extension 4731 if (Crypto) 4732 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 4733 // ACLE 6.5.8 CRC32 Extension 4734 if (CRC) 4735 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 4736 // ACLE 6.5.10 Numeric Maximum and Minimum 4737 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 4738 // ACLE 6.5.9 Directed Rounding 4739 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 4740 } 4741 4742 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4743 // is not defined for the M-profile. 4744 // NOTE that the deffault profile is assumed to be 'A' 4745 if (CPUProfile.empty() || CPUProfile != "M") 4746 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4747 4748 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4749 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4750 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4751 if (supportsThumb2()) 4752 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4753 else if (supportsThumb()) 4754 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4755 4756 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4757 // instruction set such as ARM or Thumb. 4758 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4759 4760 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4761 4762 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4763 if (!CPUProfile.empty()) 4764 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4765 4766 // ACLE 6.4.3 Unaligned access supported in hardware 4767 if (Unaligned) 4768 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 4769 4770 // ACLE 6.4.4 LDREX/STREX 4771 if (LDREX) 4772 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 4773 4774 // ACLE 6.4.5 CLZ 4775 if (ArchVersion == 5 || 4776 (ArchVersion == 6 && CPUProfile != "M") || 4777 ArchVersion > 6) 4778 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 4779 4780 // ACLE 6.5.1 Hardware Floating Point 4781 if (HW_FP) 4782 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4783 4784 // ACLE predefines. 4785 Builder.defineMacro("__ARM_ACLE", "200"); 4786 4787 // FP16 support (we currently only support IEEE format). 4788 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 4789 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 4790 4791 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 4792 if (ArchVersion >= 7 && (CPUProfile != "M" || CPUAttr == "7EM")) 4793 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 4794 4795 // Subtarget options. 4796 4797 // FIXME: It's more complicated than this and we don't really support 4798 // interworking. 4799 // Windows on ARM does not "support" interworking 4800 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 4801 Builder.defineMacro("__THUMB_INTERWORK__"); 4802 4803 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4804 // Embedded targets on Darwin follow AAPCS, but not EABI. 4805 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4806 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4807 Builder.defineMacro("__ARM_EABI__"); 4808 Builder.defineMacro("__ARM_PCS", "1"); 4809 4810 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4811 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4812 } 4813 4814 if (SoftFloat) 4815 Builder.defineMacro("__SOFTFP__"); 4816 4817 if (CPU == "xscale") 4818 Builder.defineMacro("__XSCALE__"); 4819 4820 if (isThumb()) { 4821 Builder.defineMacro("__THUMBEL__"); 4822 Builder.defineMacro("__thumb__"); 4823 if (supportsThumb2()) 4824 Builder.defineMacro("__thumb2__"); 4825 } 4826 4827 // ACLE 6.4.9 32-bit SIMD instructions 4828 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 4829 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 4830 4831 // ACLE 6.4.10 Hardware Integer Divide 4832 if (((HWDiv & HWDivThumb) && isThumb()) || 4833 ((HWDiv & HWDivARM) && !isThumb())) { 4834 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 4835 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4836 } 4837 4838 // Note, this is always on in gcc, even though it doesn't make sense. 4839 Builder.defineMacro("__APCS_32__"); 4840 4841 if (FPUModeIsVFP((FPUMode) FPU)) { 4842 Builder.defineMacro("__VFP_FP__"); 4843 if (FPU & VFP2FPU) 4844 Builder.defineMacro("__ARM_VFPV2__"); 4845 if (FPU & VFP3FPU) 4846 Builder.defineMacro("__ARM_VFPV3__"); 4847 if (FPU & VFP4FPU) 4848 Builder.defineMacro("__ARM_VFPV4__"); 4849 } 4850 4851 // This only gets set when Neon instructions are actually available, unlike 4852 // the VFP define, hence the soft float and arch check. This is subtly 4853 // different from gcc, we follow the intent which was that it should be set 4854 // when Neon instructions are actually available. 4855 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 4856 Builder.defineMacro("__ARM_NEON", "1"); 4857 Builder.defineMacro("__ARM_NEON__"); 4858 // current AArch32 NEON implementations do not support double-precision 4859 // floating-point even when it is present in VFP. 4860 Builder.defineMacro("__ARM_NEON_FP", 4861 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 4862 } 4863 4864 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4865 Opts.ShortWChar ? "2" : "4"); 4866 4867 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4868 Opts.ShortEnums ? "1" : "4"); 4869 4870 if (ArchVersion >= 6 && CPUAttr != "6M") { 4871 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4872 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4873 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4874 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4875 } 4876 4877 // ACLE 6.4.7 DSP instructions 4878 if (DSP) { 4879 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 4880 } 4881 4882 // ACLE 6.4.8 Saturation instructions 4883 bool SAT = false; 4884 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 4885 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 4886 SAT = true; 4887 } 4888 4889 // ACLE 6.4.6 Q (saturation) flag 4890 if (DSP || SAT) 4891 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 4892 4893 if (Opts.UnsafeFPMath) 4894 Builder.defineMacro("__ARM_FP_FAST", "1"); 4895 4896 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 4897 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 4898 } 4899 4900 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4901 return llvm::makeArrayRef(BuiltinInfo, 4902 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 4903 } 4904 bool isCLZForZeroUndef() const override { return false; } 4905 BuiltinVaListKind getBuiltinVaListKind() const override { 4906 return IsAAPCS 4907 ? AAPCSABIBuiltinVaList 4908 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 4909 : TargetInfo::VoidPtrBuiltinVaList); 4910 } 4911 ArrayRef<const char *> getGCCRegNames() const override; 4912 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 4913 bool validateAsmConstraint(const char *&Name, 4914 TargetInfo::ConstraintInfo &Info) const override { 4915 switch (*Name) { 4916 default: break; 4917 case 'l': // r0-r7 4918 case 'h': // r8-r15 4919 case 'w': // VFP Floating point register single precision 4920 case 'P': // VFP Floating point register double precision 4921 Info.setAllowsRegister(); 4922 return true; 4923 case 'I': 4924 case 'J': 4925 case 'K': 4926 case 'L': 4927 case 'M': 4928 // FIXME 4929 return true; 4930 case 'Q': // A memory address that is a single base register. 4931 Info.setAllowsMemory(); 4932 return true; 4933 case 'U': // a memory reference... 4934 switch (Name[1]) { 4935 case 'q': // ...ARMV4 ldrsb 4936 case 'v': // ...VFP load/store (reg+constant offset) 4937 case 'y': // ...iWMMXt load/store 4938 case 't': // address valid for load/store opaque types wider 4939 // than 128-bits 4940 case 'n': // valid address for Neon doubleword vector load/store 4941 case 'm': // valid address for Neon element and structure load/store 4942 case 's': // valid address for non-offset loads/stores of quad-word 4943 // values in four ARM registers 4944 Info.setAllowsMemory(); 4945 Name++; 4946 return true; 4947 } 4948 } 4949 return false; 4950 } 4951 std::string convertConstraint(const char *&Constraint) const override { 4952 std::string R; 4953 switch (*Constraint) { 4954 case 'U': // Two-character constraint; add "^" hint for later parsing. 4955 R = std::string("^") + std::string(Constraint, 2); 4956 Constraint++; 4957 break; 4958 case 'p': // 'p' should be translated to 'r' by default. 4959 R = std::string("r"); 4960 break; 4961 default: 4962 return std::string(1, *Constraint); 4963 } 4964 return R; 4965 } 4966 bool 4967 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4968 std::string &SuggestedModifier) const override { 4969 bool isOutput = (Constraint[0] == '='); 4970 bool isInOut = (Constraint[0] == '+'); 4971 4972 // Strip off constraint modifiers. 4973 while (Constraint[0] == '=' || 4974 Constraint[0] == '+' || 4975 Constraint[0] == '&') 4976 Constraint = Constraint.substr(1); 4977 4978 switch (Constraint[0]) { 4979 default: break; 4980 case 'r': { 4981 switch (Modifier) { 4982 default: 4983 return (isInOut || isOutput || Size <= 64); 4984 case 'q': 4985 // A register of size 32 cannot fit a vector type. 4986 return false; 4987 } 4988 } 4989 } 4990 4991 return true; 4992 } 4993 const char *getClobbers() const override { 4994 // FIXME: Is this really right? 4995 return ""; 4996 } 4997 4998 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4999 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 5000 } 5001 5002 int getEHDataRegisterNumber(unsigned RegNo) const override { 5003 if (RegNo == 0) return 0; 5004 if (RegNo == 1) return 1; 5005 return -1; 5006 } 5007 5008 bool hasSjLjLowering() const override { 5009 return true; 5010 } 5011 }; 5012 5013 bool ARMTargetInfo::setFPMath(StringRef Name) { 5014 if (Name == "neon") { 5015 FPMath = FP_Neon; 5016 return true; 5017 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5018 Name == "vfp4") { 5019 FPMath = FP_VFP; 5020 return true; 5021 } 5022 return false; 5023 } 5024 5025 const char * const ARMTargetInfo::GCCRegNames[] = { 5026 // Integer registers 5027 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5028 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5029 5030 // Float registers 5031 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5032 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5033 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5034 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5035 5036 // Double registers 5037 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5038 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5039 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5040 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5041 5042 // Quad registers 5043 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5044 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5045 }; 5046 5047 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5048 return llvm::makeArrayRef(GCCRegNames); 5049 } 5050 5051 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5052 { { "a1" }, "r0" }, 5053 { { "a2" }, "r1" }, 5054 { { "a3" }, "r2" }, 5055 { { "a4" }, "r3" }, 5056 { { "v1" }, "r4" }, 5057 { { "v2" }, "r5" }, 5058 { { "v3" }, "r6" }, 5059 { { "v4" }, "r7" }, 5060 { { "v5" }, "r8" }, 5061 { { "v6", "rfp" }, "r9" }, 5062 { { "sl" }, "r10" }, 5063 { { "fp" }, "r11" }, 5064 { { "ip" }, "r12" }, 5065 { { "r13" }, "sp" }, 5066 { { "r14" }, "lr" }, 5067 { { "r15" }, "pc" }, 5068 // The S, D and Q registers overlap, but aren't really aliases; we 5069 // don't want to substitute one of these for a different-sized one. 5070 }; 5071 5072 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5073 return llvm::makeArrayRef(GCCRegAliases); 5074 } 5075 5076 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5077 #define BUILTIN(ID, TYPE, ATTRS) \ 5078 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5079 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5080 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5081 #include "clang/Basic/BuiltinsNEON.def" 5082 5083 #define BUILTIN(ID, TYPE, ATTRS) \ 5084 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5085 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5086 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5087 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5088 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5089 #include "clang/Basic/BuiltinsARM.def" 5090 }; 5091 5092 class ARMleTargetInfo : public ARMTargetInfo { 5093 public: 5094 ARMleTargetInfo(const llvm::Triple &Triple) 5095 : ARMTargetInfo(Triple, false) { } 5096 void getTargetDefines(const LangOptions &Opts, 5097 MacroBuilder &Builder) const override { 5098 Builder.defineMacro("__ARMEL__"); 5099 ARMTargetInfo::getTargetDefines(Opts, Builder); 5100 } 5101 }; 5102 5103 class ARMbeTargetInfo : public ARMTargetInfo { 5104 public: 5105 ARMbeTargetInfo(const llvm::Triple &Triple) 5106 : ARMTargetInfo(Triple, true) { } 5107 void getTargetDefines(const LangOptions &Opts, 5108 MacroBuilder &Builder) const override { 5109 Builder.defineMacro("__ARMEB__"); 5110 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5111 ARMTargetInfo::getTargetDefines(Opts, Builder); 5112 } 5113 }; 5114 5115 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5116 const llvm::Triple Triple; 5117 public: 5118 WindowsARMTargetInfo(const llvm::Triple &Triple) 5119 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 5120 TLSSupported = false; 5121 WCharType = UnsignedShort; 5122 SizeType = UnsignedInt; 5123 UserLabelPrefix = ""; 5124 } 5125 void getVisualStudioDefines(const LangOptions &Opts, 5126 MacroBuilder &Builder) const { 5127 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5128 5129 // FIXME: this is invalid for WindowsCE 5130 Builder.defineMacro("_M_ARM_NT", "1"); 5131 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5132 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5133 5134 assert((Triple.getArch() == llvm::Triple::arm || 5135 Triple.getArch() == llvm::Triple::thumb) && 5136 "invalid architecture for Windows ARM target info"); 5137 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5138 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5139 5140 // TODO map the complete set of values 5141 // 31: VFPv3 40: VFPv4 5142 Builder.defineMacro("_M_ARM_FP", "31"); 5143 } 5144 BuiltinVaListKind getBuiltinVaListKind() const override { 5145 return TargetInfo::CharPtrBuiltinVaList; 5146 } 5147 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5148 switch (CC) { 5149 case CC_X86StdCall: 5150 case CC_X86ThisCall: 5151 case CC_X86FastCall: 5152 case CC_X86VectorCall: 5153 return CCCR_Ignore; 5154 case CC_C: 5155 return CCCR_OK; 5156 default: 5157 return CCCR_Warning; 5158 } 5159 } 5160 }; 5161 5162 // Windows ARM + Itanium C++ ABI Target 5163 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5164 public: 5165 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 5166 : WindowsARMTargetInfo(Triple) { 5167 TheCXXABI.set(TargetCXXABI::GenericARM); 5168 } 5169 5170 void getTargetDefines(const LangOptions &Opts, 5171 MacroBuilder &Builder) const override { 5172 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5173 5174 if (Opts.MSVCCompat) 5175 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5176 } 5177 }; 5178 5179 // Windows ARM, MS (C++) ABI 5180 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5181 public: 5182 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 5183 : WindowsARMTargetInfo(Triple) { 5184 TheCXXABI.set(TargetCXXABI::Microsoft); 5185 } 5186 5187 void getTargetDefines(const LangOptions &Opts, 5188 MacroBuilder &Builder) const override { 5189 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5190 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5191 } 5192 }; 5193 5194 // ARM MinGW target 5195 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5196 public: 5197 MinGWARMTargetInfo(const llvm::Triple &Triple) 5198 : WindowsARMTargetInfo(Triple) { 5199 TheCXXABI.set(TargetCXXABI::GenericARM); 5200 } 5201 5202 void getTargetDefines(const LangOptions &Opts, 5203 MacroBuilder &Builder) const override { 5204 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5205 DefineStd(Builder, "WIN32", Opts); 5206 DefineStd(Builder, "WINNT", Opts); 5207 Builder.defineMacro("_ARM_"); 5208 addMinGWDefines(Opts, Builder); 5209 } 5210 }; 5211 5212 // ARM Cygwin target 5213 class CygwinARMTargetInfo : public ARMleTargetInfo { 5214 public: 5215 CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) { 5216 TLSSupported = false; 5217 WCharType = UnsignedShort; 5218 DoubleAlign = LongLongAlign = 64; 5219 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 5220 } 5221 void getTargetDefines(const LangOptions &Opts, 5222 MacroBuilder &Builder) const override { 5223 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5224 Builder.defineMacro("_ARM_"); 5225 Builder.defineMacro("__CYGWIN__"); 5226 Builder.defineMacro("__CYGWIN32__"); 5227 DefineStd(Builder, "unix", Opts); 5228 if (Opts.CPlusPlus) 5229 Builder.defineMacro("_GNU_SOURCE"); 5230 } 5231 }; 5232 5233 class DarwinARMTargetInfo : 5234 public DarwinTargetInfo<ARMleTargetInfo> { 5235 protected: 5236 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5237 MacroBuilder &Builder) const override { 5238 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5239 } 5240 5241 public: 5242 DarwinARMTargetInfo(const llvm::Triple &Triple) 5243 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 5244 HasAlignMac68kSupport = true; 5245 // iOS always has 64-bit atomic instructions. 5246 // FIXME: This should be based off of the target features in 5247 // ARMleTargetInfo. 5248 MaxAtomicInlineWidth = 64; 5249 5250 if (Triple.isWatchABI()) { 5251 // Darwin on iOS uses a variant of the ARM C++ ABI. 5252 TheCXXABI.set(TargetCXXABI::WatchOS); 5253 5254 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5255 // size_t is long, it's a bit weird for it to be int. 5256 PtrDiffType = SignedLong; 5257 5258 // BOOL should be a real boolean on the new ABI 5259 UseSignedCharForObjCBool = false; 5260 } else 5261 TheCXXABI.set(TargetCXXABI::iOS); 5262 } 5263 }; 5264 5265 class AArch64TargetInfo : public TargetInfo { 5266 virtual void setDataLayoutString() = 0; 5267 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5268 static const char *const GCCRegNames[]; 5269 5270 enum FPUModeEnum { 5271 FPUMode, 5272 NeonMode 5273 }; 5274 5275 unsigned FPU; 5276 unsigned CRC; 5277 unsigned Crypto; 5278 unsigned Unaligned; 5279 unsigned V8_1A; 5280 5281 static const Builtin::Info BuiltinInfo[]; 5282 5283 std::string ABI; 5284 5285 public: 5286 AArch64TargetInfo(const llvm::Triple &Triple) 5287 : TargetInfo(Triple), ABI("aapcs") { 5288 5289 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5290 WCharType = SignedInt; 5291 5292 // NetBSD apparently prefers consistency across ARM targets to consistency 5293 // across 64-bit targets. 5294 Int64Type = SignedLongLong; 5295 IntMaxType = SignedLongLong; 5296 } else { 5297 WCharType = UnsignedInt; 5298 Int64Type = SignedLong; 5299 IntMaxType = SignedLong; 5300 } 5301 5302 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5303 MaxVectorAlign = 128; 5304 MaxAtomicInlineWidth = 128; 5305 MaxAtomicPromoteWidth = 128; 5306 5307 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5308 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5309 5310 // {} in inline assembly are neon specifiers, not assembly variant 5311 // specifiers. 5312 NoAsmVariants = true; 5313 5314 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5315 // contributes to the alignment of the containing aggregate in the same way 5316 // a plain (non bit-field) member of that type would, without exception for 5317 // zero-sized or anonymous bit-fields." 5318 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5319 UseZeroLengthBitfieldAlignment = true; 5320 5321 // AArch64 targets default to using the ARM C++ ABI. 5322 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5323 } 5324 5325 StringRef getABI() const override { return ABI; } 5326 bool setABI(const std::string &Name) override { 5327 if (Name != "aapcs" && Name != "darwinpcs") 5328 return false; 5329 5330 ABI = Name; 5331 return true; 5332 } 5333 5334 bool setCPU(const std::string &Name) override { 5335 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5336 .Case("generic", true) 5337 .Cases("cortex-a53", "cortex-a57", "cortex-a72", 5338 "cortex-a35", "exynos-m1", true) 5339 .Case("cyclone", true) 5340 .Default(false); 5341 return CPUKnown; 5342 } 5343 5344 void getTargetDefines(const LangOptions &Opts, 5345 MacroBuilder &Builder) const override { 5346 // Target identification. 5347 Builder.defineMacro("__aarch64__"); 5348 5349 // Target properties. 5350 Builder.defineMacro("_LP64"); 5351 Builder.defineMacro("__LP64__"); 5352 5353 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5354 Builder.defineMacro("__ARM_ACLE", "200"); 5355 Builder.defineMacro("__ARM_ARCH", "8"); 5356 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5357 5358 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5359 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5360 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5361 5362 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5363 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5364 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5365 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5366 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5367 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5368 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5369 5370 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5371 5372 // 0xe implies support for half, single and double precision operations. 5373 Builder.defineMacro("__ARM_FP", "0xE"); 5374 5375 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5376 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5377 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5378 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5379 5380 if (Opts.UnsafeFPMath) 5381 Builder.defineMacro("__ARM_FP_FAST", "1"); 5382 5383 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5384 5385 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5386 Opts.ShortEnums ? "1" : "4"); 5387 5388 if (FPU == NeonMode) { 5389 Builder.defineMacro("__ARM_NEON", "1"); 5390 // 64-bit NEON supports half, single and double precision operations. 5391 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5392 } 5393 5394 if (CRC) 5395 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5396 5397 if (Crypto) 5398 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5399 5400 if (Unaligned) 5401 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5402 5403 if (V8_1A) 5404 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5405 5406 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5407 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5408 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5409 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5410 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5411 } 5412 5413 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5414 return llvm::makeArrayRef(BuiltinInfo, 5415 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5416 } 5417 5418 bool hasFeature(StringRef Feature) const override { 5419 return Feature == "aarch64" || 5420 Feature == "arm64" || 5421 Feature == "arm" || 5422 (Feature == "neon" && FPU == NeonMode); 5423 } 5424 5425 bool handleTargetFeatures(std::vector<std::string> &Features, 5426 DiagnosticsEngine &Diags) override { 5427 FPU = FPUMode; 5428 CRC = 0; 5429 Crypto = 0; 5430 Unaligned = 1; 5431 V8_1A = 0; 5432 5433 for (const auto &Feature : Features) { 5434 if (Feature == "+neon") 5435 FPU = NeonMode; 5436 if (Feature == "+crc") 5437 CRC = 1; 5438 if (Feature == "+crypto") 5439 Crypto = 1; 5440 if (Feature == "+strict-align") 5441 Unaligned = 0; 5442 if (Feature == "+v8.1a") 5443 V8_1A = 1; 5444 } 5445 5446 setDataLayoutString(); 5447 5448 return true; 5449 } 5450 5451 bool isCLZForZeroUndef() const override { return false; } 5452 5453 BuiltinVaListKind getBuiltinVaListKind() const override { 5454 return TargetInfo::AArch64ABIBuiltinVaList; 5455 } 5456 5457 ArrayRef<const char *> getGCCRegNames() const override; 5458 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5459 5460 bool validateAsmConstraint(const char *&Name, 5461 TargetInfo::ConstraintInfo &Info) const override { 5462 switch (*Name) { 5463 default: 5464 return false; 5465 case 'w': // Floating point and SIMD registers (V0-V31) 5466 Info.setAllowsRegister(); 5467 return true; 5468 case 'I': // Constant that can be used with an ADD instruction 5469 case 'J': // Constant that can be used with a SUB instruction 5470 case 'K': // Constant that can be used with a 32-bit logical instruction 5471 case 'L': // Constant that can be used with a 64-bit logical instruction 5472 case 'M': // Constant that can be used as a 32-bit MOV immediate 5473 case 'N': // Constant that can be used as a 64-bit MOV immediate 5474 case 'Y': // Floating point constant zero 5475 case 'Z': // Integer constant zero 5476 return true; 5477 case 'Q': // A memory reference with base register and no offset 5478 Info.setAllowsMemory(); 5479 return true; 5480 case 'S': // A symbolic address 5481 Info.setAllowsRegister(); 5482 return true; 5483 case 'U': 5484 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5485 // Utf: A memory address suitable for ldp/stp in TF mode. 5486 // Usa: An absolute symbolic address. 5487 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5488 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5489 case 'z': // Zero register, wzr or xzr 5490 Info.setAllowsRegister(); 5491 return true; 5492 case 'x': // Floating point and SIMD registers (V0-V15) 5493 Info.setAllowsRegister(); 5494 return true; 5495 } 5496 return false; 5497 } 5498 5499 bool 5500 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5501 std::string &SuggestedModifier) const override { 5502 // Strip off constraint modifiers. 5503 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5504 Constraint = Constraint.substr(1); 5505 5506 switch (Constraint[0]) { 5507 default: 5508 return true; 5509 case 'z': 5510 case 'r': { 5511 switch (Modifier) { 5512 case 'x': 5513 case 'w': 5514 // For now assume that the person knows what they're 5515 // doing with the modifier. 5516 return true; 5517 default: 5518 // By default an 'r' constraint will be in the 'x' 5519 // registers. 5520 if (Size == 64) 5521 return true; 5522 5523 SuggestedModifier = "w"; 5524 return false; 5525 } 5526 } 5527 } 5528 } 5529 5530 const char *getClobbers() const override { return ""; } 5531 5532 int getEHDataRegisterNumber(unsigned RegNo) const override { 5533 if (RegNo == 0) 5534 return 0; 5535 if (RegNo == 1) 5536 return 1; 5537 return -1; 5538 } 5539 }; 5540 5541 const char *const AArch64TargetInfo::GCCRegNames[] = { 5542 // 32-bit Integer registers 5543 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5544 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5545 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5546 5547 // 64-bit Integer registers 5548 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5549 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5550 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5551 5552 // 32-bit floating point regsisters 5553 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5554 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5555 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5556 5557 // 64-bit floating point regsisters 5558 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5559 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5560 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5561 5562 // Vector registers 5563 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5564 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5565 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5566 }; 5567 5568 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 5569 return llvm::makeArrayRef(GCCRegNames); 5570 } 5571 5572 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5573 { { "w31" }, "wsp" }, 5574 { { "x29" }, "fp" }, 5575 { { "x30" }, "lr" }, 5576 { { "x31" }, "sp" }, 5577 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5578 // don't want to substitute one of these for a different-sized one. 5579 }; 5580 5581 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 5582 return llvm::makeArrayRef(GCCRegAliases); 5583 } 5584 5585 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5586 #define BUILTIN(ID, TYPE, ATTRS) \ 5587 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5588 #include "clang/Basic/BuiltinsNEON.def" 5589 5590 #define BUILTIN(ID, TYPE, ATTRS) \ 5591 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5592 #include "clang/Basic/BuiltinsAArch64.def" 5593 }; 5594 5595 class AArch64leTargetInfo : public AArch64TargetInfo { 5596 void setDataLayoutString() override { 5597 if (getTriple().isOSBinFormatMachO()) 5598 DataLayoutString = "e-m:o-i64:64-i128:128-n32:64-S128"; 5599 else 5600 DataLayoutString = "e-m:e-i64:64-i128:128-n32:64-S128"; 5601 } 5602 5603 public: 5604 AArch64leTargetInfo(const llvm::Triple &Triple) 5605 : AArch64TargetInfo(Triple) { 5606 BigEndian = false; 5607 } 5608 void getTargetDefines(const LangOptions &Opts, 5609 MacroBuilder &Builder) const override { 5610 Builder.defineMacro("__AARCH64EL__"); 5611 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5612 } 5613 }; 5614 5615 class AArch64beTargetInfo : public AArch64TargetInfo { 5616 void setDataLayoutString() override { 5617 assert(!getTriple().isOSBinFormatMachO()); 5618 DataLayoutString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5619 } 5620 5621 public: 5622 AArch64beTargetInfo(const llvm::Triple &Triple) 5623 : AArch64TargetInfo(Triple) { } 5624 void getTargetDefines(const LangOptions &Opts, 5625 MacroBuilder &Builder) const override { 5626 Builder.defineMacro("__AARCH64EB__"); 5627 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5628 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5629 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5630 } 5631 }; 5632 5633 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5634 protected: 5635 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5636 MacroBuilder &Builder) const override { 5637 Builder.defineMacro("__AARCH64_SIMD__"); 5638 Builder.defineMacro("__ARM64_ARCH_8__"); 5639 Builder.defineMacro("__ARM_NEON__"); 5640 Builder.defineMacro("__LITTLE_ENDIAN__"); 5641 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5642 Builder.defineMacro("__arm64", "1"); 5643 Builder.defineMacro("__arm64__", "1"); 5644 5645 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5646 } 5647 5648 public: 5649 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5650 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5651 Int64Type = SignedLongLong; 5652 WCharType = SignedInt; 5653 UseSignedCharForObjCBool = false; 5654 5655 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5656 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5657 5658 TheCXXABI.set(TargetCXXABI::iOS64); 5659 } 5660 5661 BuiltinVaListKind getBuiltinVaListKind() const override { 5662 return TargetInfo::CharPtrBuiltinVaList; 5663 } 5664 }; 5665 5666 // Hexagon abstract base class 5667 class HexagonTargetInfo : public TargetInfo { 5668 static const Builtin::Info BuiltinInfo[]; 5669 static const char * const GCCRegNames[]; 5670 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5671 std::string CPU; 5672 bool HasHVX, HasHVXDouble; 5673 5674 public: 5675 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5676 BigEndian = false; 5677 DataLayoutString = "e-m:e-p:32:32:32-" 5678 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-" 5679 "f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32"; 5680 SizeType = UnsignedInt; 5681 PtrDiffType = SignedInt; 5682 IntPtrType = SignedInt; 5683 5684 // {} in inline assembly are packet specifiers, not assembly variant 5685 // specifiers. 5686 NoAsmVariants = true; 5687 5688 LargeArrayMinWidth = 64; 5689 LargeArrayAlign = 64; 5690 UseBitFieldTypeAlignment = true; 5691 ZeroLengthBitfieldBoundary = 32; 5692 HasHVX = HasHVXDouble = false; 5693 } 5694 5695 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5696 return llvm::makeArrayRef(BuiltinInfo, 5697 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 5698 } 5699 5700 bool validateAsmConstraint(const char *&Name, 5701 TargetInfo::ConstraintInfo &Info) const override { 5702 return true; 5703 } 5704 5705 void getTargetDefines(const LangOptions &Opts, 5706 MacroBuilder &Builder) const override; 5707 5708 bool isCLZForZeroUndef() const override { return false; } 5709 5710 bool hasFeature(StringRef Feature) const override { 5711 return llvm::StringSwitch<bool>(Feature) 5712 .Case("hexagon", true) 5713 .Case("hvx", HasHVX) 5714 .Case("hvx-double", HasHVXDouble) 5715 .Default(false); 5716 } 5717 5718 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5719 StringRef CPU, const std::vector<std::string> &FeaturesVec) 5720 const override; 5721 5722 bool handleTargetFeatures(std::vector<std::string> &Features, 5723 DiagnosticsEngine &Diags) override; 5724 5725 BuiltinVaListKind getBuiltinVaListKind() const override { 5726 return TargetInfo::CharPtrBuiltinVaList; 5727 } 5728 ArrayRef<const char *> getGCCRegNames() const override; 5729 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5730 const char *getClobbers() const override { 5731 return ""; 5732 } 5733 5734 static const char *getHexagonCPUSuffix(StringRef Name) { 5735 return llvm::StringSwitch<const char*>(Name) 5736 .Case("hexagonv4", "4") 5737 .Case("hexagonv5", "5") 5738 .Case("hexagonv55", "55") 5739 .Case("hexagonv60", "60") 5740 .Default(nullptr); 5741 } 5742 5743 bool setCPU(const std::string &Name) override { 5744 if (!getHexagonCPUSuffix(Name)) 5745 return false; 5746 CPU = Name; 5747 return true; 5748 } 5749 5750 int getEHDataRegisterNumber(unsigned RegNo) const override { 5751 return RegNo < 2 ? RegNo : -1; 5752 } 5753 }; 5754 5755 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5756 MacroBuilder &Builder) const { 5757 Builder.defineMacro("__qdsp6__", "1"); 5758 Builder.defineMacro("__hexagon__", "1"); 5759 5760 if (CPU == "hexagonv4") { 5761 Builder.defineMacro("__HEXAGON_V4__"); 5762 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5763 if (Opts.HexagonQdsp6Compat) { 5764 Builder.defineMacro("__QDSP6_V4__"); 5765 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5766 } 5767 } else if (CPU == "hexagonv5") { 5768 Builder.defineMacro("__HEXAGON_V5__"); 5769 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5770 if(Opts.HexagonQdsp6Compat) { 5771 Builder.defineMacro("__QDSP6_V5__"); 5772 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5773 } 5774 } else if (CPU == "hexagonv60") { 5775 Builder.defineMacro("__HEXAGON_V60__"); 5776 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 5777 Builder.defineMacro("__QDSP6_V60__"); 5778 Builder.defineMacro("__QDSP6_ARCH__", "60"); 5779 } 5780 } 5781 5782 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 5783 DiagnosticsEngine &Diags) { 5784 for (auto &F : Features) { 5785 if (F == "+hvx") 5786 HasHVX = true; 5787 else if (F == "-hvx") 5788 HasHVX = HasHVXDouble = false; 5789 else if (F == "+hvx-double") 5790 HasHVX = HasHVXDouble = true; 5791 else if (F == "-hvx-double") 5792 HasHVXDouble = false; 5793 } 5794 return true; 5795 } 5796 5797 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 5798 DiagnosticsEngine &Diags, StringRef CPU, 5799 const std::vector<std::string> &FeaturesVec) const { 5800 // Default for v60: -hvx, -hvx-double. 5801 Features["hvx"] = false; 5802 Features["hvx-double"] = false; 5803 5804 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5805 } 5806 5807 5808 const char *const HexagonTargetInfo::GCCRegNames[] = { 5809 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5810 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5811 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5812 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5813 "p0", "p1", "p2", "p3", 5814 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5815 }; 5816 5817 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 5818 return llvm::makeArrayRef(GCCRegNames); 5819 } 5820 5821 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5822 { { "sp" }, "r29" }, 5823 { { "fp" }, "r30" }, 5824 { { "lr" }, "r31" }, 5825 }; 5826 5827 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 5828 return llvm::makeArrayRef(GCCRegAliases); 5829 } 5830 5831 5832 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5833 #define BUILTIN(ID, TYPE, ATTRS) \ 5834 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5835 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5836 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5837 #include "clang/Basic/BuiltinsHexagon.def" 5838 }; 5839 5840 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5841 class SparcTargetInfo : public TargetInfo { 5842 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5843 static const char * const GCCRegNames[]; 5844 bool SoftFloat; 5845 public: 5846 SparcTargetInfo(const llvm::Triple &Triple) 5847 : TargetInfo(Triple), SoftFloat(false) {} 5848 5849 bool handleTargetFeatures(std::vector<std::string> &Features, 5850 DiagnosticsEngine &Diags) override { 5851 // The backend doesn't actually handle soft float yet, but in case someone 5852 // is using the support for the front end continue to support it. 5853 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 5854 if (Feature != Features.end()) { 5855 SoftFloat = true; 5856 Features.erase(Feature); 5857 } 5858 return true; 5859 } 5860 void getTargetDefines(const LangOptions &Opts, 5861 MacroBuilder &Builder) const override { 5862 DefineStd(Builder, "sparc", Opts); 5863 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5864 5865 if (SoftFloat) 5866 Builder.defineMacro("SOFT_FLOAT", "1"); 5867 } 5868 5869 bool hasFeature(StringRef Feature) const override { 5870 return llvm::StringSwitch<bool>(Feature) 5871 .Case("softfloat", SoftFloat) 5872 .Case("sparc", true) 5873 .Default(false); 5874 } 5875 5876 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5877 // FIXME: Implement! 5878 return None; 5879 } 5880 BuiltinVaListKind getBuiltinVaListKind() const override { 5881 return TargetInfo::VoidPtrBuiltinVaList; 5882 } 5883 ArrayRef<const char *> getGCCRegNames() const override; 5884 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5885 bool validateAsmConstraint(const char *&Name, 5886 TargetInfo::ConstraintInfo &info) const override { 5887 // FIXME: Implement! 5888 switch (*Name) { 5889 case 'I': // Signed 13-bit constant 5890 case 'J': // Zero 5891 case 'K': // 32-bit constant with the low 12 bits clear 5892 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5893 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5894 case 'N': // Same as 'K' but zext (required for SIMode) 5895 case 'O': // The constant 4096 5896 return true; 5897 } 5898 return false; 5899 } 5900 const char *getClobbers() const override { 5901 // FIXME: Implement! 5902 return ""; 5903 } 5904 5905 // No Sparc V7 for now, the backend doesn't support it anyway. 5906 enum CPUKind { 5907 CK_GENERIC, 5908 CK_V8, 5909 CK_SUPERSPARC, 5910 CK_SPARCLITE, 5911 CK_F934, 5912 CK_HYPERSPARC, 5913 CK_SPARCLITE86X, 5914 CK_SPARCLET, 5915 CK_TSC701, 5916 CK_V9, 5917 CK_ULTRASPARC, 5918 CK_ULTRASPARC3, 5919 CK_NIAGARA, 5920 CK_NIAGARA2, 5921 CK_NIAGARA3, 5922 CK_NIAGARA4 5923 } CPU = CK_GENERIC; 5924 5925 enum CPUGeneration { 5926 CG_V8, 5927 CG_V9, 5928 }; 5929 5930 CPUGeneration getCPUGeneration(CPUKind Kind) const { 5931 switch (Kind) { 5932 case CK_GENERIC: 5933 case CK_V8: 5934 case CK_SUPERSPARC: 5935 case CK_SPARCLITE: 5936 case CK_F934: 5937 case CK_HYPERSPARC: 5938 case CK_SPARCLITE86X: 5939 case CK_SPARCLET: 5940 case CK_TSC701: 5941 return CG_V8; 5942 case CK_V9: 5943 case CK_ULTRASPARC: 5944 case CK_ULTRASPARC3: 5945 case CK_NIAGARA: 5946 case CK_NIAGARA2: 5947 case CK_NIAGARA3: 5948 case CK_NIAGARA4: 5949 return CG_V9; 5950 } 5951 llvm_unreachable("Unexpected CPU kind"); 5952 } 5953 5954 CPUKind getCPUKind(StringRef Name) const { 5955 return llvm::StringSwitch<CPUKind>(Name) 5956 .Case("v8", CK_V8) 5957 .Case("supersparc", CK_SUPERSPARC) 5958 .Case("sparclite", CK_SPARCLITE) 5959 .Case("f934", CK_F934) 5960 .Case("hypersparc", CK_HYPERSPARC) 5961 .Case("sparclite86x", CK_SPARCLITE86X) 5962 .Case("sparclet", CK_SPARCLET) 5963 .Case("tsc701", CK_TSC701) 5964 .Case("v9", CK_V9) 5965 .Case("ultrasparc", CK_ULTRASPARC) 5966 .Case("ultrasparc3", CK_ULTRASPARC3) 5967 .Case("niagara", CK_NIAGARA) 5968 .Case("niagara2", CK_NIAGARA2) 5969 .Case("niagara3", CK_NIAGARA3) 5970 .Case("niagara4", CK_NIAGARA4) 5971 .Default(CK_GENERIC); 5972 } 5973 5974 bool setCPU(const std::string &Name) override { 5975 CPU = getCPUKind(Name); 5976 return CPU != CK_GENERIC; 5977 } 5978 }; 5979 5980 const char * const SparcTargetInfo::GCCRegNames[] = { 5981 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5982 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5983 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5984 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5985 }; 5986 5987 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 5988 return llvm::makeArrayRef(GCCRegNames); 5989 } 5990 5991 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5992 { { "g0" }, "r0" }, 5993 { { "g1" }, "r1" }, 5994 { { "g2" }, "r2" }, 5995 { { "g3" }, "r3" }, 5996 { { "g4" }, "r4" }, 5997 { { "g5" }, "r5" }, 5998 { { "g6" }, "r6" }, 5999 { { "g7" }, "r7" }, 6000 { { "o0" }, "r8" }, 6001 { { "o1" }, "r9" }, 6002 { { "o2" }, "r10" }, 6003 { { "o3" }, "r11" }, 6004 { { "o4" }, "r12" }, 6005 { { "o5" }, "r13" }, 6006 { { "o6", "sp" }, "r14" }, 6007 { { "o7" }, "r15" }, 6008 { { "l0" }, "r16" }, 6009 { { "l1" }, "r17" }, 6010 { { "l2" }, "r18" }, 6011 { { "l3" }, "r19" }, 6012 { { "l4" }, "r20" }, 6013 { { "l5" }, "r21" }, 6014 { { "l6" }, "r22" }, 6015 { { "l7" }, "r23" }, 6016 { { "i0" }, "r24" }, 6017 { { "i1" }, "r25" }, 6018 { { "i2" }, "r26" }, 6019 { { "i3" }, "r27" }, 6020 { { "i4" }, "r28" }, 6021 { { "i5" }, "r29" }, 6022 { { "i6", "fp" }, "r30" }, 6023 { { "i7" }, "r31" }, 6024 }; 6025 6026 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6027 return llvm::makeArrayRef(GCCRegAliases); 6028 } 6029 6030 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6031 class SparcV8TargetInfo : public SparcTargetInfo { 6032 public: 6033 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 6034 DataLayoutString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 6035 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6036 switch (getTriple().getOS()) { 6037 default: 6038 SizeType = UnsignedInt; 6039 IntPtrType = SignedInt; 6040 PtrDiffType = SignedInt; 6041 break; 6042 case llvm::Triple::NetBSD: 6043 case llvm::Triple::OpenBSD: 6044 SizeType = UnsignedLong; 6045 IntPtrType = SignedLong; 6046 PtrDiffType = SignedLong; 6047 break; 6048 } 6049 } 6050 6051 void getTargetDefines(const LangOptions &Opts, 6052 MacroBuilder &Builder) const override { 6053 SparcTargetInfo::getTargetDefines(Opts, Builder); 6054 switch (getCPUGeneration(CPU)) { 6055 case CG_V8: 6056 Builder.defineMacro("__sparcv8"); 6057 if (getTriple().getOS() != llvm::Triple::Solaris) 6058 Builder.defineMacro("__sparcv8__"); 6059 break; 6060 case CG_V9: 6061 Builder.defineMacro("__sparcv9"); 6062 if (getTriple().getOS() != llvm::Triple::Solaris) { 6063 Builder.defineMacro("__sparcv9__"); 6064 Builder.defineMacro("__sparc_v9__"); 6065 } 6066 break; 6067 } 6068 } 6069 }; 6070 6071 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6072 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6073 public: 6074 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 6075 DataLayoutString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64"; 6076 BigEndian = false; 6077 } 6078 }; 6079 6080 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6081 class SparcV9TargetInfo : public SparcTargetInfo { 6082 public: 6083 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 6084 // FIXME: Support Sparc quad-precision long double? 6085 DataLayoutString = "E-m:e-i64:64-n32:64-S128"; 6086 // This is an LP64 platform. 6087 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6088 6089 // OpenBSD uses long long for int64_t and intmax_t. 6090 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6091 IntMaxType = SignedLongLong; 6092 else 6093 IntMaxType = SignedLong; 6094 Int64Type = IntMaxType; 6095 6096 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6097 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6098 LongDoubleWidth = 128; 6099 LongDoubleAlign = 128; 6100 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6101 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6102 } 6103 6104 void getTargetDefines(const LangOptions &Opts, 6105 MacroBuilder &Builder) const override { 6106 SparcTargetInfo::getTargetDefines(Opts, Builder); 6107 Builder.defineMacro("__sparcv9"); 6108 Builder.defineMacro("__arch64__"); 6109 // Solaris doesn't need these variants, but the BSDs do. 6110 if (getTriple().getOS() != llvm::Triple::Solaris) { 6111 Builder.defineMacro("__sparc64__"); 6112 Builder.defineMacro("__sparc_v9__"); 6113 Builder.defineMacro("__sparcv9__"); 6114 } 6115 } 6116 6117 bool setCPU(const std::string &Name) override { 6118 if (!SparcTargetInfo::setCPU(Name)) 6119 return false; 6120 return getCPUGeneration(CPU) == CG_V9; 6121 } 6122 }; 6123 6124 class SystemZTargetInfo : public TargetInfo { 6125 static const Builtin::Info BuiltinInfo[]; 6126 static const char *const GCCRegNames[]; 6127 std::string CPU; 6128 bool HasTransactionalExecution; 6129 bool HasVector; 6130 6131 public: 6132 SystemZTargetInfo(const llvm::Triple &Triple) 6133 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6134 HasVector(false) { 6135 IntMaxType = SignedLong; 6136 Int64Type = SignedLong; 6137 TLSSupported = true; 6138 IntWidth = IntAlign = 32; 6139 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6140 PointerWidth = PointerAlign = 64; 6141 LongDoubleWidth = 128; 6142 LongDoubleAlign = 64; 6143 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6144 DefaultAlignForAttributeAligned = 64; 6145 MinGlobalAlign = 16; 6146 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 6147 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6148 } 6149 void getTargetDefines(const LangOptions &Opts, 6150 MacroBuilder &Builder) const override { 6151 Builder.defineMacro("__s390__"); 6152 Builder.defineMacro("__s390x__"); 6153 Builder.defineMacro("__zarch__"); 6154 Builder.defineMacro("__LONG_DOUBLE_128__"); 6155 if (HasTransactionalExecution) 6156 Builder.defineMacro("__HTM__"); 6157 if (Opts.ZVector) 6158 Builder.defineMacro("__VEC__", "10301"); 6159 } 6160 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6161 return llvm::makeArrayRef(BuiltinInfo, 6162 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6163 } 6164 6165 ArrayRef<const char *> getGCCRegNames() const override; 6166 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6167 // No aliases. 6168 return None; 6169 } 6170 bool validateAsmConstraint(const char *&Name, 6171 TargetInfo::ConstraintInfo &info) const override; 6172 const char *getClobbers() const override { 6173 // FIXME: Is this really right? 6174 return ""; 6175 } 6176 BuiltinVaListKind getBuiltinVaListKind() const override { 6177 return TargetInfo::SystemZBuiltinVaList; 6178 } 6179 bool setCPU(const std::string &Name) override { 6180 CPU = Name; 6181 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6182 .Case("z10", true) 6183 .Case("z196", true) 6184 .Case("zEC12", true) 6185 .Case("z13", true) 6186 .Default(false); 6187 6188 return CPUKnown; 6189 } 6190 bool 6191 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6192 StringRef CPU, 6193 const std::vector<std::string> &FeaturesVec) const override { 6194 if (CPU == "zEC12") 6195 Features["transactional-execution"] = true; 6196 if (CPU == "z13") { 6197 Features["transactional-execution"] = true; 6198 Features["vector"] = true; 6199 } 6200 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6201 } 6202 6203 bool handleTargetFeatures(std::vector<std::string> &Features, 6204 DiagnosticsEngine &Diags) override { 6205 HasTransactionalExecution = false; 6206 for (const auto &Feature : Features) { 6207 if (Feature == "+transactional-execution") 6208 HasTransactionalExecution = true; 6209 else if (Feature == "+vector") 6210 HasVector = true; 6211 } 6212 // If we use the vector ABI, vector types are 64-bit aligned. 6213 if (HasVector) { 6214 MaxVectorAlign = 64; 6215 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6216 "-v128:64-a:8:16-n32:64"; 6217 } 6218 return true; 6219 } 6220 6221 bool hasFeature(StringRef Feature) const override { 6222 return llvm::StringSwitch<bool>(Feature) 6223 .Case("systemz", true) 6224 .Case("htm", HasTransactionalExecution) 6225 .Case("vx", HasVector) 6226 .Default(false); 6227 } 6228 6229 StringRef getABI() const override { 6230 if (HasVector) 6231 return "vector"; 6232 return ""; 6233 } 6234 6235 bool useFloat128ManglingForLongDouble() const override { 6236 return true; 6237 } 6238 }; 6239 6240 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6241 #define BUILTIN(ID, TYPE, ATTRS) \ 6242 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6243 #include "clang/Basic/BuiltinsSystemZ.def" 6244 }; 6245 6246 const char *const SystemZTargetInfo::GCCRegNames[] = { 6247 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6248 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6249 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6250 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6251 }; 6252 6253 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6254 return llvm::makeArrayRef(GCCRegNames); 6255 } 6256 6257 bool SystemZTargetInfo:: 6258 validateAsmConstraint(const char *&Name, 6259 TargetInfo::ConstraintInfo &Info) const { 6260 switch (*Name) { 6261 default: 6262 return false; 6263 6264 case 'a': // Address register 6265 case 'd': // Data register (equivalent to 'r') 6266 case 'f': // Floating-point register 6267 Info.setAllowsRegister(); 6268 return true; 6269 6270 case 'I': // Unsigned 8-bit constant 6271 case 'J': // Unsigned 12-bit constant 6272 case 'K': // Signed 16-bit constant 6273 case 'L': // Signed 20-bit displacement (on all targets we support) 6274 case 'M': // 0x7fffffff 6275 return true; 6276 6277 case 'Q': // Memory with base and unsigned 12-bit displacement 6278 case 'R': // Likewise, plus an index 6279 case 'S': // Memory with base and signed 20-bit displacement 6280 case 'T': // Likewise, plus an index 6281 Info.setAllowsMemory(); 6282 return true; 6283 } 6284 } 6285 6286 class MSP430TargetInfo : public TargetInfo { 6287 static const char *const GCCRegNames[]; 6288 6289 public: 6290 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6291 BigEndian = false; 6292 TLSSupported = false; 6293 IntWidth = 16; 6294 IntAlign = 16; 6295 LongWidth = 32; 6296 LongLongWidth = 64; 6297 LongAlign = LongLongAlign = 16; 6298 PointerWidth = 16; 6299 PointerAlign = 16; 6300 SuitableAlign = 16; 6301 SizeType = UnsignedInt; 6302 IntMaxType = SignedLongLong; 6303 IntPtrType = SignedInt; 6304 PtrDiffType = SignedInt; 6305 SigAtomicType = SignedLong; 6306 DataLayoutString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 6307 } 6308 void getTargetDefines(const LangOptions &Opts, 6309 MacroBuilder &Builder) const override { 6310 Builder.defineMacro("MSP430"); 6311 Builder.defineMacro("__MSP430__"); 6312 // FIXME: defines for different 'flavours' of MCU 6313 } 6314 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6315 // FIXME: Implement. 6316 return None; 6317 } 6318 bool hasFeature(StringRef Feature) const override { 6319 return Feature == "msp430"; 6320 } 6321 ArrayRef<const char *> getGCCRegNames() const override; 6322 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6323 // No aliases. 6324 return None; 6325 } 6326 bool validateAsmConstraint(const char *&Name, 6327 TargetInfo::ConstraintInfo &info) const override { 6328 // FIXME: implement 6329 switch (*Name) { 6330 case 'K': // the constant 1 6331 case 'L': // constant -1^20 .. 1^19 6332 case 'M': // constant 1-4: 6333 return true; 6334 } 6335 // No target constraints for now. 6336 return false; 6337 } 6338 const char *getClobbers() const override { 6339 // FIXME: Is this really right? 6340 return ""; 6341 } 6342 BuiltinVaListKind getBuiltinVaListKind() const override { 6343 // FIXME: implement 6344 return TargetInfo::CharPtrBuiltinVaList; 6345 } 6346 }; 6347 6348 const char *const MSP430TargetInfo::GCCRegNames[] = { 6349 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6350 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6351 6352 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 6353 return llvm::makeArrayRef(GCCRegNames); 6354 } 6355 6356 // LLVM and Clang cannot be used directly to output native binaries for 6357 // target, but is used to compile C code to llvm bitcode with correct 6358 // type and alignment information. 6359 // 6360 // TCE uses the llvm bitcode as input and uses it for generating customized 6361 // target processor and program binary. TCE co-design environment is 6362 // publicly available in http://tce.cs.tut.fi 6363 6364 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6365 3, // opencl_global 6366 4, // opencl_local 6367 5, // opencl_constant 6368 // FIXME: generic has to be added to the target 6369 0, // opencl_generic 6370 0, // cuda_device 6371 0, // cuda_constant 6372 0 // cuda_shared 6373 }; 6374 6375 class TCETargetInfo : public TargetInfo { 6376 public: 6377 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6378 TLSSupported = false; 6379 IntWidth = 32; 6380 LongWidth = LongLongWidth = 32; 6381 PointerWidth = 32; 6382 IntAlign = 32; 6383 LongAlign = LongLongAlign = 32; 6384 PointerAlign = 32; 6385 SuitableAlign = 32; 6386 SizeType = UnsignedInt; 6387 IntMaxType = SignedLong; 6388 IntPtrType = SignedInt; 6389 PtrDiffType = SignedInt; 6390 FloatWidth = 32; 6391 FloatAlign = 32; 6392 DoubleWidth = 32; 6393 DoubleAlign = 32; 6394 LongDoubleWidth = 32; 6395 LongDoubleAlign = 32; 6396 FloatFormat = &llvm::APFloat::IEEEsingle; 6397 DoubleFormat = &llvm::APFloat::IEEEsingle; 6398 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6399 DataLayoutString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 6400 "-f64:32-v64:32-v128:32-a:0:32-n32"; 6401 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6402 UseAddrSpaceMapMangling = true; 6403 } 6404 6405 void getTargetDefines(const LangOptions &Opts, 6406 MacroBuilder &Builder) const override { 6407 DefineStd(Builder, "tce", Opts); 6408 Builder.defineMacro("__TCE__"); 6409 Builder.defineMacro("__TCE_V1__"); 6410 } 6411 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 6412 6413 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6414 const char *getClobbers() const override { return ""; } 6415 BuiltinVaListKind getBuiltinVaListKind() const override { 6416 return TargetInfo::VoidPtrBuiltinVaList; 6417 } 6418 ArrayRef<const char *> getGCCRegNames() const override { return None; } 6419 bool validateAsmConstraint(const char *&Name, 6420 TargetInfo::ConstraintInfo &info) const override { 6421 return true; 6422 } 6423 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6424 return None; 6425 } 6426 }; 6427 6428 class BPFTargetInfo : public TargetInfo { 6429 public: 6430 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6431 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6432 SizeType = UnsignedLong; 6433 PtrDiffType = SignedLong; 6434 IntPtrType = SignedLong; 6435 IntMaxType = SignedLong; 6436 Int64Type = SignedLong; 6437 RegParmMax = 5; 6438 if (Triple.getArch() == llvm::Triple::bpfeb) { 6439 BigEndian = true; 6440 DataLayoutString = "E-m:e-p:64:64-i64:64-n32:64-S128"; 6441 } else { 6442 BigEndian = false; 6443 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 6444 } 6445 MaxAtomicPromoteWidth = 64; 6446 MaxAtomicInlineWidth = 64; 6447 TLSSupported = false; 6448 } 6449 void getTargetDefines(const LangOptions &Opts, 6450 MacroBuilder &Builder) const override { 6451 DefineStd(Builder, "bpf", Opts); 6452 Builder.defineMacro("__BPF__"); 6453 } 6454 bool hasFeature(StringRef Feature) const override { 6455 return Feature == "bpf"; 6456 } 6457 6458 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6459 const char *getClobbers() const override { 6460 return ""; 6461 } 6462 BuiltinVaListKind getBuiltinVaListKind() const override { 6463 return TargetInfo::VoidPtrBuiltinVaList; 6464 } 6465 ArrayRef<const char *> getGCCRegNames() const override { 6466 return None; 6467 } 6468 bool validateAsmConstraint(const char *&Name, 6469 TargetInfo::ConstraintInfo &info) const override { 6470 return true; 6471 } 6472 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6473 return None; 6474 } 6475 }; 6476 6477 class MipsTargetInfoBase : public TargetInfo { 6478 virtual void setDataLayoutString() = 0; 6479 6480 static const Builtin::Info BuiltinInfo[]; 6481 std::string CPU; 6482 bool IsMips16; 6483 bool IsMicromips; 6484 bool IsNan2008; 6485 bool IsSingleFloat; 6486 enum MipsFloatABI { 6487 HardFloat, SoftFloat 6488 } FloatABI; 6489 enum DspRevEnum { 6490 NoDSP, DSP1, DSP2 6491 } DspRev; 6492 bool HasMSA; 6493 6494 protected: 6495 bool HasFP64; 6496 std::string ABI; 6497 6498 public: 6499 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 6500 const std::string &CPUStr) 6501 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6502 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6503 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6504 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6505 } 6506 6507 bool isNaN2008Default() const { 6508 return CPU == "mips32r6" || CPU == "mips64r6"; 6509 } 6510 6511 bool isFP64Default() const { 6512 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6513 } 6514 6515 bool isNan2008() const override { 6516 return IsNan2008; 6517 } 6518 6519 StringRef getABI() const override { return ABI; } 6520 bool setCPU(const std::string &Name) override { 6521 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6522 getTriple().getArch() == llvm::Triple::mipsel; 6523 CPU = Name; 6524 return llvm::StringSwitch<bool>(Name) 6525 .Case("mips1", IsMips32) 6526 .Case("mips2", IsMips32) 6527 .Case("mips3", true) 6528 .Case("mips4", true) 6529 .Case("mips5", true) 6530 .Case("mips32", IsMips32) 6531 .Case("mips32r2", IsMips32) 6532 .Case("mips32r3", IsMips32) 6533 .Case("mips32r5", IsMips32) 6534 .Case("mips32r6", IsMips32) 6535 .Case("mips64", true) 6536 .Case("mips64r2", true) 6537 .Case("mips64r3", true) 6538 .Case("mips64r5", true) 6539 .Case("mips64r6", true) 6540 .Case("octeon", true) 6541 .Case("p5600", true) 6542 .Default(false); 6543 } 6544 const std::string& getCPU() const { return CPU; } 6545 bool 6546 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6547 StringRef CPU, 6548 const std::vector<std::string> &FeaturesVec) const override { 6549 if (CPU == "octeon") 6550 Features["mips64r2"] = Features["cnmips"] = true; 6551 else 6552 Features[CPU] = true; 6553 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6554 } 6555 6556 void getTargetDefines(const LangOptions &Opts, 6557 MacroBuilder &Builder) const override { 6558 Builder.defineMacro("__mips__"); 6559 Builder.defineMacro("_mips"); 6560 if (Opts.GNUMode) 6561 Builder.defineMacro("mips"); 6562 6563 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6564 6565 switch (FloatABI) { 6566 case HardFloat: 6567 Builder.defineMacro("__mips_hard_float", Twine(1)); 6568 break; 6569 case SoftFloat: 6570 Builder.defineMacro("__mips_soft_float", Twine(1)); 6571 break; 6572 } 6573 6574 if (IsSingleFloat) 6575 Builder.defineMacro("__mips_single_float", Twine(1)); 6576 6577 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6578 Builder.defineMacro("_MIPS_FPSET", 6579 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6580 6581 if (IsMips16) 6582 Builder.defineMacro("__mips16", Twine(1)); 6583 6584 if (IsMicromips) 6585 Builder.defineMacro("__mips_micromips", Twine(1)); 6586 6587 if (IsNan2008) 6588 Builder.defineMacro("__mips_nan2008", Twine(1)); 6589 6590 switch (DspRev) { 6591 default: 6592 break; 6593 case DSP1: 6594 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6595 Builder.defineMacro("__mips_dsp", Twine(1)); 6596 break; 6597 case DSP2: 6598 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6599 Builder.defineMacro("__mips_dspr2", Twine(1)); 6600 Builder.defineMacro("__mips_dsp", Twine(1)); 6601 break; 6602 } 6603 6604 if (HasMSA) 6605 Builder.defineMacro("__mips_msa", Twine(1)); 6606 6607 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6608 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6609 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6610 6611 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6612 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6613 6614 // These shouldn't be defined for MIPS-I but there's no need to check 6615 // for that since MIPS-I isn't supported. 6616 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6617 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6618 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6619 } 6620 6621 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6622 return llvm::makeArrayRef(BuiltinInfo, 6623 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 6624 } 6625 bool hasFeature(StringRef Feature) const override { 6626 return llvm::StringSwitch<bool>(Feature) 6627 .Case("mips", true) 6628 .Case("fp64", HasFP64) 6629 .Default(false); 6630 } 6631 BuiltinVaListKind getBuiltinVaListKind() const override { 6632 return TargetInfo::VoidPtrBuiltinVaList; 6633 } 6634 ArrayRef<const char *> getGCCRegNames() const override { 6635 static const char *const GCCRegNames[] = { 6636 // CPU register names 6637 // Must match second column of GCCRegAliases 6638 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6639 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6640 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6641 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6642 // Floating point register names 6643 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6644 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6645 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6646 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6647 // Hi/lo and condition register names 6648 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6649 "$fcc5","$fcc6","$fcc7", 6650 // MSA register names 6651 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6652 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6653 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6654 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6655 // MSA control register names 6656 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6657 "$msarequest", "$msamap", "$msaunmap" 6658 }; 6659 return llvm::makeArrayRef(GCCRegNames); 6660 } 6661 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override = 0; 6662 bool validateAsmConstraint(const char *&Name, 6663 TargetInfo::ConstraintInfo &Info) const override { 6664 switch (*Name) { 6665 default: 6666 return false; 6667 case 'r': // CPU registers. 6668 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6669 case 'y': // Equivalent to "r", backward compatibility only. 6670 case 'f': // floating-point registers. 6671 case 'c': // $25 for indirect jumps 6672 case 'l': // lo register 6673 case 'x': // hilo register pair 6674 Info.setAllowsRegister(); 6675 return true; 6676 case 'I': // Signed 16-bit constant 6677 case 'J': // Integer 0 6678 case 'K': // Unsigned 16-bit constant 6679 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6680 case 'M': // Constants not loadable via lui, addiu, or ori 6681 case 'N': // Constant -1 to -65535 6682 case 'O': // A signed 15-bit constant 6683 case 'P': // A constant between 1 go 65535 6684 return true; 6685 case 'R': // An address that can be used in a non-macro load or store 6686 Info.setAllowsMemory(); 6687 return true; 6688 case 'Z': 6689 if (Name[1] == 'C') { // An address usable by ll, and sc. 6690 Info.setAllowsMemory(); 6691 Name++; // Skip over 'Z'. 6692 return true; 6693 } 6694 return false; 6695 } 6696 } 6697 6698 std::string convertConstraint(const char *&Constraint) const override { 6699 std::string R; 6700 switch (*Constraint) { 6701 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6702 if (Constraint[1] == 'C') { 6703 R = std::string("^") + std::string(Constraint, 2); 6704 Constraint++; 6705 return R; 6706 } 6707 break; 6708 } 6709 return TargetInfo::convertConstraint(Constraint); 6710 } 6711 6712 const char *getClobbers() const override { 6713 // In GCC, $1 is not widely used in generated code (it's used only in a few 6714 // specific situations), so there is no real need for users to add it to 6715 // the clobbers list if they want to use it in their inline assembly code. 6716 // 6717 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6718 // code generation, so using it in inline assembly without adding it to the 6719 // clobbers list can cause conflicts between the inline assembly code and 6720 // the surrounding generated code. 6721 // 6722 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6723 // operands, which will conflict with the ".set at" assembler option (which 6724 // we use only for inline assembly, in order to maintain compatibility with 6725 // GCC) and will also conflict with the user's usage of $1. 6726 // 6727 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6728 // register for generated code is to automatically clobber $1 for all inline 6729 // assembly code. 6730 // 6731 // FIXME: We should automatically clobber $1 only for inline assembly code 6732 // which actually uses it. This would allow LLVM to use $1 for inline 6733 // assembly operands if the user's assembly code doesn't use it. 6734 return "~{$1}"; 6735 } 6736 6737 bool handleTargetFeatures(std::vector<std::string> &Features, 6738 DiagnosticsEngine &Diags) override { 6739 IsMips16 = false; 6740 IsMicromips = false; 6741 IsNan2008 = isNaN2008Default(); 6742 IsSingleFloat = false; 6743 FloatABI = HardFloat; 6744 DspRev = NoDSP; 6745 HasFP64 = isFP64Default(); 6746 6747 for (const auto &Feature : Features) { 6748 if (Feature == "+single-float") 6749 IsSingleFloat = true; 6750 else if (Feature == "+soft-float") 6751 FloatABI = SoftFloat; 6752 else if (Feature == "+mips16") 6753 IsMips16 = true; 6754 else if (Feature == "+micromips") 6755 IsMicromips = true; 6756 else if (Feature == "+dsp") 6757 DspRev = std::max(DspRev, DSP1); 6758 else if (Feature == "+dspr2") 6759 DspRev = std::max(DspRev, DSP2); 6760 else if (Feature == "+msa") 6761 HasMSA = true; 6762 else if (Feature == "+fp64") 6763 HasFP64 = true; 6764 else if (Feature == "-fp64") 6765 HasFP64 = false; 6766 else if (Feature == "+nan2008") 6767 IsNan2008 = true; 6768 else if (Feature == "-nan2008") 6769 IsNan2008 = false; 6770 } 6771 6772 setDataLayoutString(); 6773 6774 return true; 6775 } 6776 6777 int getEHDataRegisterNumber(unsigned RegNo) const override { 6778 if (RegNo == 0) return 4; 6779 if (RegNo == 1) return 5; 6780 return -1; 6781 } 6782 6783 bool isCLZForZeroUndef() const override { return false; } 6784 }; 6785 6786 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 6787 #define BUILTIN(ID, TYPE, ATTRS) \ 6788 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6789 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6790 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6791 #include "clang/Basic/BuiltinsMips.def" 6792 }; 6793 6794 class Mips32TargetInfoBase : public MipsTargetInfoBase { 6795 public: 6796 Mips32TargetInfoBase(const llvm::Triple &Triple) 6797 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 6798 SizeType = UnsignedInt; 6799 PtrDiffType = SignedInt; 6800 Int64Type = SignedLongLong; 6801 IntMaxType = Int64Type; 6802 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 6803 } 6804 bool setABI(const std::string &Name) override { 6805 if (Name == "o32" || Name == "eabi") { 6806 ABI = Name; 6807 return true; 6808 } 6809 return false; 6810 } 6811 void getTargetDefines(const LangOptions &Opts, 6812 MacroBuilder &Builder) const override { 6813 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6814 6815 Builder.defineMacro("__mips", "32"); 6816 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 6817 6818 const std::string& CPUStr = getCPU(); 6819 if (CPUStr == "mips32") 6820 Builder.defineMacro("__mips_isa_rev", "1"); 6821 else if (CPUStr == "mips32r2") 6822 Builder.defineMacro("__mips_isa_rev", "2"); 6823 else if (CPUStr == "mips32r3") 6824 Builder.defineMacro("__mips_isa_rev", "3"); 6825 else if (CPUStr == "mips32r5") 6826 Builder.defineMacro("__mips_isa_rev", "5"); 6827 else if (CPUStr == "mips32r6") 6828 Builder.defineMacro("__mips_isa_rev", "6"); 6829 6830 if (ABI == "o32") { 6831 Builder.defineMacro("__mips_o32"); 6832 Builder.defineMacro("_ABIO32", "1"); 6833 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6834 } 6835 else if (ABI == "eabi") 6836 Builder.defineMacro("__mips_eabi"); 6837 else 6838 llvm_unreachable("Invalid ABI for Mips32."); 6839 } 6840 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6841 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6842 { { "at" }, "$1" }, 6843 { { "v0" }, "$2" }, 6844 { { "v1" }, "$3" }, 6845 { { "a0" }, "$4" }, 6846 { { "a1" }, "$5" }, 6847 { { "a2" }, "$6" }, 6848 { { "a3" }, "$7" }, 6849 { { "t0" }, "$8" }, 6850 { { "t1" }, "$9" }, 6851 { { "t2" }, "$10" }, 6852 { { "t3" }, "$11" }, 6853 { { "t4" }, "$12" }, 6854 { { "t5" }, "$13" }, 6855 { { "t6" }, "$14" }, 6856 { { "t7" }, "$15" }, 6857 { { "s0" }, "$16" }, 6858 { { "s1" }, "$17" }, 6859 { { "s2" }, "$18" }, 6860 { { "s3" }, "$19" }, 6861 { { "s4" }, "$20" }, 6862 { { "s5" }, "$21" }, 6863 { { "s6" }, "$22" }, 6864 { { "s7" }, "$23" }, 6865 { { "t8" }, "$24" }, 6866 { { "t9" }, "$25" }, 6867 { { "k0" }, "$26" }, 6868 { { "k1" }, "$27" }, 6869 { { "gp" }, "$28" }, 6870 { { "sp","$sp" }, "$29" }, 6871 { { "fp","$fp" }, "$30" }, 6872 { { "ra" }, "$31" } 6873 }; 6874 return llvm::makeArrayRef(GCCRegAliases); 6875 } 6876 }; 6877 6878 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6879 void setDataLayoutString() override { 6880 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6881 } 6882 6883 public: 6884 Mips32EBTargetInfo(const llvm::Triple &Triple) 6885 : Mips32TargetInfoBase(Triple) { 6886 } 6887 void getTargetDefines(const LangOptions &Opts, 6888 MacroBuilder &Builder) const override { 6889 DefineStd(Builder, "MIPSEB", Opts); 6890 Builder.defineMacro("_MIPSEB"); 6891 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6892 } 6893 }; 6894 6895 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6896 void setDataLayoutString() override { 6897 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6898 } 6899 6900 public: 6901 Mips32ELTargetInfo(const llvm::Triple &Triple) 6902 : Mips32TargetInfoBase(Triple) { 6903 BigEndian = false; 6904 } 6905 void getTargetDefines(const LangOptions &Opts, 6906 MacroBuilder &Builder) const override { 6907 DefineStd(Builder, "MIPSEL", Opts); 6908 Builder.defineMacro("_MIPSEL"); 6909 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6910 } 6911 }; 6912 6913 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6914 public: 6915 Mips64TargetInfoBase(const llvm::Triple &Triple) 6916 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6917 LongDoubleWidth = LongDoubleAlign = 128; 6918 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6919 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6920 LongDoubleWidth = LongDoubleAlign = 64; 6921 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6922 } 6923 setN64ABITypes(); 6924 SuitableAlign = 128; 6925 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6926 } 6927 6928 void setN64ABITypes() { 6929 LongWidth = LongAlign = 64; 6930 PointerWidth = PointerAlign = 64; 6931 SizeType = UnsignedLong; 6932 PtrDiffType = SignedLong; 6933 Int64Type = SignedLong; 6934 IntMaxType = Int64Type; 6935 } 6936 6937 void setN32ABITypes() { 6938 LongWidth = LongAlign = 32; 6939 PointerWidth = PointerAlign = 32; 6940 SizeType = UnsignedInt; 6941 PtrDiffType = SignedInt; 6942 Int64Type = SignedLongLong; 6943 IntMaxType = Int64Type; 6944 } 6945 6946 bool setABI(const std::string &Name) override { 6947 if (Name == "n32") { 6948 setN32ABITypes(); 6949 ABI = Name; 6950 return true; 6951 } 6952 if (Name == "n64") { 6953 setN64ABITypes(); 6954 ABI = Name; 6955 return true; 6956 } 6957 return false; 6958 } 6959 6960 void getTargetDefines(const LangOptions &Opts, 6961 MacroBuilder &Builder) const override { 6962 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6963 6964 Builder.defineMacro("__mips", "64"); 6965 Builder.defineMacro("__mips64"); 6966 Builder.defineMacro("__mips64__"); 6967 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 6968 6969 const std::string& CPUStr = getCPU(); 6970 if (CPUStr == "mips64") 6971 Builder.defineMacro("__mips_isa_rev", "1"); 6972 else if (CPUStr == "mips64r2") 6973 Builder.defineMacro("__mips_isa_rev", "2"); 6974 else if (CPUStr == "mips64r3") 6975 Builder.defineMacro("__mips_isa_rev", "3"); 6976 else if (CPUStr == "mips64r5") 6977 Builder.defineMacro("__mips_isa_rev", "5"); 6978 else if (CPUStr == "mips64r6") 6979 Builder.defineMacro("__mips_isa_rev", "6"); 6980 6981 if (ABI == "n32") { 6982 Builder.defineMacro("__mips_n32"); 6983 Builder.defineMacro("_ABIN32", "2"); 6984 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 6985 } 6986 else if (ABI == "n64") { 6987 Builder.defineMacro("__mips_n64"); 6988 Builder.defineMacro("_ABI64", "3"); 6989 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 6990 } 6991 else 6992 llvm_unreachable("Invalid ABI for Mips64."); 6993 6994 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6995 } 6996 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6997 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6998 { { "at" }, "$1" }, 6999 { { "v0" }, "$2" }, 7000 { { "v1" }, "$3" }, 7001 { { "a0" }, "$4" }, 7002 { { "a1" }, "$5" }, 7003 { { "a2" }, "$6" }, 7004 { { "a3" }, "$7" }, 7005 { { "a4" }, "$8" }, 7006 { { "a5" }, "$9" }, 7007 { { "a6" }, "$10" }, 7008 { { "a7" }, "$11" }, 7009 { { "t0" }, "$12" }, 7010 { { "t1" }, "$13" }, 7011 { { "t2" }, "$14" }, 7012 { { "t3" }, "$15" }, 7013 { { "s0" }, "$16" }, 7014 { { "s1" }, "$17" }, 7015 { { "s2" }, "$18" }, 7016 { { "s3" }, "$19" }, 7017 { { "s4" }, "$20" }, 7018 { { "s5" }, "$21" }, 7019 { { "s6" }, "$22" }, 7020 { { "s7" }, "$23" }, 7021 { { "t8" }, "$24" }, 7022 { { "t9" }, "$25" }, 7023 { { "k0" }, "$26" }, 7024 { { "k1" }, "$27" }, 7025 { { "gp" }, "$28" }, 7026 { { "sp","$sp" }, "$29" }, 7027 { { "fp","$fp" }, "$30" }, 7028 { { "ra" }, "$31" } 7029 }; 7030 return llvm::makeArrayRef(GCCRegAliases); 7031 } 7032 7033 bool hasInt128Type() const override { return true; } 7034 }; 7035 7036 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 7037 void setDataLayoutString() override { 7038 if (ABI == "n32") 7039 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7040 else 7041 DataLayoutString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7042 7043 } 7044 7045 public: 7046 Mips64EBTargetInfo(const llvm::Triple &Triple) 7047 : Mips64TargetInfoBase(Triple) {} 7048 void getTargetDefines(const LangOptions &Opts, 7049 MacroBuilder &Builder) const override { 7050 DefineStd(Builder, "MIPSEB", Opts); 7051 Builder.defineMacro("_MIPSEB"); 7052 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7053 } 7054 }; 7055 7056 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 7057 void setDataLayoutString() override { 7058 if (ABI == "n32") 7059 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7060 else 7061 DataLayoutString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7062 } 7063 public: 7064 Mips64ELTargetInfo(const llvm::Triple &Triple) 7065 : Mips64TargetInfoBase(Triple) { 7066 // Default ABI is n64. 7067 BigEndian = false; 7068 } 7069 void getTargetDefines(const LangOptions &Opts, 7070 MacroBuilder &Builder) const override { 7071 DefineStd(Builder, "MIPSEL", Opts); 7072 Builder.defineMacro("_MIPSEL"); 7073 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7074 } 7075 }; 7076 7077 class PNaClTargetInfo : public TargetInfo { 7078 public: 7079 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7080 BigEndian = false; 7081 this->UserLabelPrefix = ""; 7082 this->LongAlign = 32; 7083 this->LongWidth = 32; 7084 this->PointerAlign = 32; 7085 this->PointerWidth = 32; 7086 this->IntMaxType = TargetInfo::SignedLongLong; 7087 this->Int64Type = TargetInfo::SignedLongLong; 7088 this->DoubleAlign = 64; 7089 this->LongDoubleWidth = 64; 7090 this->LongDoubleAlign = 64; 7091 this->SizeType = TargetInfo::UnsignedInt; 7092 this->PtrDiffType = TargetInfo::SignedInt; 7093 this->IntPtrType = TargetInfo::SignedInt; 7094 this->RegParmMax = 0; // Disallow regparm 7095 } 7096 7097 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7098 Builder.defineMacro("__le32__"); 7099 Builder.defineMacro("__pnacl__"); 7100 } 7101 void getTargetDefines(const LangOptions &Opts, 7102 MacroBuilder &Builder) const override { 7103 getArchDefines(Opts, Builder); 7104 } 7105 bool hasFeature(StringRef Feature) const override { 7106 return Feature == "pnacl"; 7107 } 7108 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7109 BuiltinVaListKind getBuiltinVaListKind() const override { 7110 return TargetInfo::PNaClABIBuiltinVaList; 7111 } 7112 ArrayRef<const char *> getGCCRegNames() const override; 7113 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7114 bool validateAsmConstraint(const char *&Name, 7115 TargetInfo::ConstraintInfo &Info) const override { 7116 return false; 7117 } 7118 7119 const char *getClobbers() const override { 7120 return ""; 7121 } 7122 }; 7123 7124 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7125 return None; 7126 } 7127 7128 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7129 return None; 7130 } 7131 7132 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7133 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 7134 public: 7135 NaClMips32ELTargetInfo(const llvm::Triple &Triple) : 7136 Mips32ELTargetInfo(Triple) { 7137 } 7138 7139 BuiltinVaListKind getBuiltinVaListKind() const override { 7140 return TargetInfo::PNaClABIBuiltinVaList; 7141 } 7142 }; 7143 7144 class Le64TargetInfo : public TargetInfo { 7145 static const Builtin::Info BuiltinInfo[]; 7146 7147 public: 7148 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7149 BigEndian = false; 7150 NoAsmVariants = true; 7151 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7152 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7153 DataLayoutString = "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 7154 } 7155 7156 void getTargetDefines(const LangOptions &Opts, 7157 MacroBuilder &Builder) const override { 7158 DefineStd(Builder, "unix", Opts); 7159 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7160 Builder.defineMacro("__ELF__"); 7161 } 7162 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7163 return llvm::makeArrayRef(BuiltinInfo, 7164 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7165 } 7166 BuiltinVaListKind getBuiltinVaListKind() const override { 7167 return TargetInfo::PNaClABIBuiltinVaList; 7168 } 7169 const char *getClobbers() const override { return ""; } 7170 ArrayRef<const char *> getGCCRegNames() const override { 7171 return None; 7172 } 7173 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7174 return None; 7175 } 7176 bool validateAsmConstraint(const char *&Name, 7177 TargetInfo::ConstraintInfo &Info) const override { 7178 return false; 7179 } 7180 7181 bool hasProtectedVisibility() const override { return false; } 7182 }; 7183 7184 class WebAssemblyTargetInfo : public TargetInfo { 7185 static const Builtin::Info BuiltinInfo[]; 7186 7187 enum SIMDEnum { 7188 NoSIMD, 7189 SIMD128, 7190 } SIMDLevel; 7191 7192 public: 7193 explicit WebAssemblyTargetInfo(const llvm::Triple &T) 7194 : TargetInfo(T), SIMDLevel(NoSIMD) { 7195 BigEndian = false; 7196 NoAsmVariants = true; 7197 SuitableAlign = 128; 7198 LargeArrayMinWidth = 128; 7199 LargeArrayAlign = 128; 7200 SimdDefaultAlign = 128; 7201 SigAtomicType = SignedLong; 7202 LongDoubleWidth = LongDoubleAlign = 128; 7203 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7204 } 7205 7206 protected: 7207 void getTargetDefines(const LangOptions &Opts, 7208 MacroBuilder &Builder) const override { 7209 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7210 if (SIMDLevel >= SIMD128) 7211 Builder.defineMacro("__wasm_simd128__"); 7212 } 7213 7214 private: 7215 bool 7216 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7217 StringRef CPU, 7218 const std::vector<std::string> &FeaturesVec) const override { 7219 if (CPU == "bleeding-edge") 7220 Features["simd128"] = true; 7221 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7222 } 7223 bool hasFeature(StringRef Feature) const final { 7224 return llvm::StringSwitch<bool>(Feature) 7225 .Case("simd128", SIMDLevel >= SIMD128) 7226 .Default(false); 7227 } 7228 bool handleTargetFeatures(std::vector<std::string> &Features, 7229 DiagnosticsEngine &Diags) final { 7230 for (const auto &Feature : Features) { 7231 if (Feature == "+simd128") { 7232 SIMDLevel = std::max(SIMDLevel, SIMD128); 7233 continue; 7234 } 7235 if (Feature == "-simd128") { 7236 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7237 continue; 7238 } 7239 7240 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7241 << "-target-feature"; 7242 return false; 7243 } 7244 return true; 7245 } 7246 bool setCPU(const std::string &Name) final { 7247 return llvm::StringSwitch<bool>(Name) 7248 .Case("mvp", true) 7249 .Case("bleeding-edge", true) 7250 .Case("generic", true) 7251 .Default(false); 7252 } 7253 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7254 return llvm::makeArrayRef(BuiltinInfo, 7255 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7256 } 7257 BuiltinVaListKind getBuiltinVaListKind() const final { 7258 return VoidPtrBuiltinVaList; 7259 } 7260 ArrayRef<const char *> getGCCRegNames() const final { 7261 return None; 7262 } 7263 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7264 return None; 7265 } 7266 bool 7267 validateAsmConstraint(const char *&Name, 7268 TargetInfo::ConstraintInfo &Info) const final { 7269 return false; 7270 } 7271 const char *getClobbers() const final { return ""; } 7272 bool isCLZForZeroUndef() const final { return false; } 7273 bool hasInt128Type() const final { return true; } 7274 IntType getIntTypeByWidth(unsigned BitWidth, 7275 bool IsSigned) const final { 7276 // WebAssembly prefers long long for explicitly 64-bit integers. 7277 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7278 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7279 } 7280 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7281 bool IsSigned) const final { 7282 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7283 return BitWidth == 64 7284 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7285 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7286 } 7287 }; 7288 7289 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7290 #define BUILTIN(ID, TYPE, ATTRS) \ 7291 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7292 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7293 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7294 #include "clang/Basic/BuiltinsWebAssembly.def" 7295 }; 7296 7297 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7298 public: 7299 explicit WebAssembly32TargetInfo(const llvm::Triple &T) 7300 : WebAssemblyTargetInfo(T) { 7301 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7302 DataLayoutString = "e-m:e-p:32:32-i64:64-n32:64-S128"; 7303 } 7304 7305 protected: 7306 void getTargetDefines(const LangOptions &Opts, 7307 MacroBuilder &Builder) const override { 7308 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7309 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7310 } 7311 }; 7312 7313 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7314 public: 7315 explicit WebAssembly64TargetInfo(const llvm::Triple &T) 7316 : WebAssemblyTargetInfo(T) { 7317 LongAlign = LongWidth = 64; 7318 PointerAlign = PointerWidth = 64; 7319 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7320 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 7321 } 7322 7323 protected: 7324 void getTargetDefines(const LangOptions &Opts, 7325 MacroBuilder &Builder) const override { 7326 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7327 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7328 } 7329 }; 7330 7331 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7332 #define BUILTIN(ID, TYPE, ATTRS) \ 7333 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7334 #include "clang/Basic/BuiltinsLe64.def" 7335 }; 7336 7337 static const unsigned SPIRAddrSpaceMap[] = { 7338 1, // opencl_global 7339 3, // opencl_local 7340 2, // opencl_constant 7341 4, // opencl_generic 7342 0, // cuda_device 7343 0, // cuda_constant 7344 0 // cuda_shared 7345 }; 7346 class SPIRTargetInfo : public TargetInfo { 7347 public: 7348 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7349 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7350 "SPIR target must use unknown OS"); 7351 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7352 "SPIR target must use unknown environment type"); 7353 BigEndian = false; 7354 TLSSupported = false; 7355 LongWidth = LongAlign = 64; 7356 AddrSpaceMap = &SPIRAddrSpaceMap; 7357 UseAddrSpaceMapMangling = true; 7358 // Define available target features 7359 // These must be defined in sorted order! 7360 NoAsmVariants = true; 7361 } 7362 void getTargetDefines(const LangOptions &Opts, 7363 MacroBuilder &Builder) const override { 7364 DefineStd(Builder, "SPIR", Opts); 7365 } 7366 bool hasFeature(StringRef Feature) const override { 7367 return Feature == "spir"; 7368 } 7369 7370 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7371 const char *getClobbers() const override { return ""; } 7372 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7373 bool validateAsmConstraint(const char *&Name, 7374 TargetInfo::ConstraintInfo &info) const override { 7375 return true; 7376 } 7377 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7378 return None; 7379 } 7380 BuiltinVaListKind getBuiltinVaListKind() const override { 7381 return TargetInfo::VoidPtrBuiltinVaList; 7382 } 7383 7384 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7385 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK 7386 : CCCR_Warning; 7387 } 7388 7389 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7390 return CC_SpirFunction; 7391 } 7392 }; 7393 7394 class SPIR32TargetInfo : public SPIRTargetInfo { 7395 public: 7396 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7397 PointerWidth = PointerAlign = 32; 7398 SizeType = TargetInfo::UnsignedInt; 7399 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7400 DataLayoutString = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7401 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7402 } 7403 void getTargetDefines(const LangOptions &Opts, 7404 MacroBuilder &Builder) const override { 7405 DefineStd(Builder, "SPIR32", Opts); 7406 } 7407 }; 7408 7409 class SPIR64TargetInfo : public SPIRTargetInfo { 7410 public: 7411 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7412 PointerWidth = PointerAlign = 64; 7413 SizeType = TargetInfo::UnsignedLong; 7414 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7415 DataLayoutString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7416 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7417 } 7418 void getTargetDefines(const LangOptions &Opts, 7419 MacroBuilder &Builder) const override { 7420 DefineStd(Builder, "SPIR64", Opts); 7421 } 7422 }; 7423 7424 class XCoreTargetInfo : public TargetInfo { 7425 static const Builtin::Info BuiltinInfo[]; 7426 public: 7427 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7428 BigEndian = false; 7429 NoAsmVariants = true; 7430 LongLongAlign = 32; 7431 SuitableAlign = 32; 7432 DoubleAlign = LongDoubleAlign = 32; 7433 SizeType = UnsignedInt; 7434 PtrDiffType = SignedInt; 7435 IntPtrType = SignedInt; 7436 WCharType = UnsignedChar; 7437 WIntType = UnsignedInt; 7438 UseZeroLengthBitfieldAlignment = true; 7439 DataLayoutString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7440 "-f64:32-a:0:32-n32"; 7441 } 7442 void getTargetDefines(const LangOptions &Opts, 7443 MacroBuilder &Builder) const override { 7444 Builder.defineMacro("__XS1B__"); 7445 } 7446 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7447 return llvm::makeArrayRef(BuiltinInfo, 7448 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 7449 } 7450 BuiltinVaListKind getBuiltinVaListKind() const override { 7451 return TargetInfo::VoidPtrBuiltinVaList; 7452 } 7453 const char *getClobbers() const override { 7454 return ""; 7455 } 7456 ArrayRef<const char *> getGCCRegNames() const override { 7457 static const char * const GCCRegNames[] = { 7458 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7459 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 7460 }; 7461 return llvm::makeArrayRef(GCCRegNames); 7462 } 7463 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7464 return None; 7465 } 7466 bool validateAsmConstraint(const char *&Name, 7467 TargetInfo::ConstraintInfo &Info) const override { 7468 return false; 7469 } 7470 int getEHDataRegisterNumber(unsigned RegNo) const override { 7471 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7472 return (RegNo < 2)? RegNo : -1; 7473 } 7474 }; 7475 7476 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7477 #define BUILTIN(ID, TYPE, ATTRS) \ 7478 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7479 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7480 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7481 #include "clang/Basic/BuiltinsXCore.def" 7482 }; 7483 7484 // x86_32 Android target 7485 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7486 public: 7487 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 7488 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 7489 SuitableAlign = 32; 7490 LongDoubleWidth = 64; 7491 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7492 } 7493 }; 7494 7495 // x86_64 Android target 7496 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7497 public: 7498 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 7499 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 7500 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7501 } 7502 7503 bool useFloat128ManglingForLongDouble() const override { 7504 return true; 7505 } 7506 }; 7507 } // end anonymous namespace 7508 7509 //===----------------------------------------------------------------------===// 7510 // Driver code 7511 //===----------------------------------------------------------------------===// 7512 7513 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 7514 llvm::Triple::OSType os = Triple.getOS(); 7515 7516 switch (Triple.getArch()) { 7517 default: 7518 return nullptr; 7519 7520 case llvm::Triple::xcore: 7521 return new XCoreTargetInfo(Triple); 7522 7523 case llvm::Triple::hexagon: 7524 return new HexagonTargetInfo(Triple); 7525 7526 case llvm::Triple::aarch64: 7527 if (Triple.isOSDarwin()) 7528 return new DarwinAArch64TargetInfo(Triple); 7529 7530 switch (os) { 7531 case llvm::Triple::CloudABI: 7532 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple); 7533 case llvm::Triple::FreeBSD: 7534 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 7535 case llvm::Triple::Linux: 7536 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 7537 case llvm::Triple::NetBSD: 7538 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 7539 default: 7540 return new AArch64leTargetInfo(Triple); 7541 } 7542 7543 case llvm::Triple::aarch64_be: 7544 switch (os) { 7545 case llvm::Triple::FreeBSD: 7546 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 7547 case llvm::Triple::Linux: 7548 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 7549 case llvm::Triple::NetBSD: 7550 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 7551 default: 7552 return new AArch64beTargetInfo(Triple); 7553 } 7554 7555 case llvm::Triple::arm: 7556 case llvm::Triple::thumb: 7557 if (Triple.isOSBinFormatMachO()) 7558 return new DarwinARMTargetInfo(Triple); 7559 7560 switch (os) { 7561 case llvm::Triple::Linux: 7562 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 7563 case llvm::Triple::FreeBSD: 7564 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 7565 case llvm::Triple::NetBSD: 7566 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 7567 case llvm::Triple::OpenBSD: 7568 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 7569 case llvm::Triple::Bitrig: 7570 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 7571 case llvm::Triple::RTEMS: 7572 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 7573 case llvm::Triple::NaCl: 7574 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 7575 case llvm::Triple::Win32: 7576 switch (Triple.getEnvironment()) { 7577 case llvm::Triple::Cygnus: 7578 return new CygwinARMTargetInfo(Triple); 7579 case llvm::Triple::GNU: 7580 return new MinGWARMTargetInfo(Triple); 7581 case llvm::Triple::Itanium: 7582 return new ItaniumWindowsARMleTargetInfo(Triple); 7583 case llvm::Triple::MSVC: 7584 default: // Assume MSVC for unknown environments 7585 return new MicrosoftARMleTargetInfo(Triple); 7586 } 7587 default: 7588 return new ARMleTargetInfo(Triple); 7589 } 7590 7591 case llvm::Triple::armeb: 7592 case llvm::Triple::thumbeb: 7593 if (Triple.isOSDarwin()) 7594 return new DarwinARMTargetInfo(Triple); 7595 7596 switch (os) { 7597 case llvm::Triple::Linux: 7598 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 7599 case llvm::Triple::FreeBSD: 7600 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 7601 case llvm::Triple::NetBSD: 7602 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 7603 case llvm::Triple::OpenBSD: 7604 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 7605 case llvm::Triple::Bitrig: 7606 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 7607 case llvm::Triple::RTEMS: 7608 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 7609 case llvm::Triple::NaCl: 7610 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 7611 default: 7612 return new ARMbeTargetInfo(Triple); 7613 } 7614 7615 case llvm::Triple::bpfeb: 7616 case llvm::Triple::bpfel: 7617 return new BPFTargetInfo(Triple); 7618 7619 case llvm::Triple::msp430: 7620 return new MSP430TargetInfo(Triple); 7621 7622 case llvm::Triple::mips: 7623 switch (os) { 7624 case llvm::Triple::Linux: 7625 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 7626 case llvm::Triple::RTEMS: 7627 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 7628 case llvm::Triple::FreeBSD: 7629 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7630 case llvm::Triple::NetBSD: 7631 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7632 default: 7633 return new Mips32EBTargetInfo(Triple); 7634 } 7635 7636 case llvm::Triple::mipsel: 7637 switch (os) { 7638 case llvm::Triple::Linux: 7639 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 7640 case llvm::Triple::RTEMS: 7641 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 7642 case llvm::Triple::FreeBSD: 7643 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7644 case llvm::Triple::NetBSD: 7645 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7646 case llvm::Triple::NaCl: 7647 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple); 7648 default: 7649 return new Mips32ELTargetInfo(Triple); 7650 } 7651 7652 case llvm::Triple::mips64: 7653 switch (os) { 7654 case llvm::Triple::Linux: 7655 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 7656 case llvm::Triple::RTEMS: 7657 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 7658 case llvm::Triple::FreeBSD: 7659 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7660 case llvm::Triple::NetBSD: 7661 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7662 case llvm::Triple::OpenBSD: 7663 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7664 default: 7665 return new Mips64EBTargetInfo(Triple); 7666 } 7667 7668 case llvm::Triple::mips64el: 7669 switch (os) { 7670 case llvm::Triple::Linux: 7671 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 7672 case llvm::Triple::RTEMS: 7673 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 7674 case llvm::Triple::FreeBSD: 7675 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7676 case llvm::Triple::NetBSD: 7677 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7678 case llvm::Triple::OpenBSD: 7679 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7680 default: 7681 return new Mips64ELTargetInfo(Triple); 7682 } 7683 7684 case llvm::Triple::le32: 7685 switch (os) { 7686 case llvm::Triple::NaCl: 7687 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 7688 default: 7689 return nullptr; 7690 } 7691 7692 case llvm::Triple::le64: 7693 return new Le64TargetInfo(Triple); 7694 7695 case llvm::Triple::ppc: 7696 if (Triple.isOSDarwin()) 7697 return new DarwinPPC32TargetInfo(Triple); 7698 switch (os) { 7699 case llvm::Triple::Linux: 7700 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 7701 case llvm::Triple::FreeBSD: 7702 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 7703 case llvm::Triple::NetBSD: 7704 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 7705 case llvm::Triple::OpenBSD: 7706 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 7707 case llvm::Triple::RTEMS: 7708 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 7709 default: 7710 return new PPC32TargetInfo(Triple); 7711 } 7712 7713 case llvm::Triple::ppc64: 7714 if (Triple.isOSDarwin()) 7715 return new DarwinPPC64TargetInfo(Triple); 7716 switch (os) { 7717 case llvm::Triple::Linux: 7718 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7719 case llvm::Triple::Lv2: 7720 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 7721 case llvm::Triple::FreeBSD: 7722 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 7723 case llvm::Triple::NetBSD: 7724 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7725 default: 7726 return new PPC64TargetInfo(Triple); 7727 } 7728 7729 case llvm::Triple::ppc64le: 7730 switch (os) { 7731 case llvm::Triple::Linux: 7732 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7733 case llvm::Triple::NetBSD: 7734 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7735 default: 7736 return new PPC64TargetInfo(Triple); 7737 } 7738 7739 case llvm::Triple::nvptx: 7740 return new NVPTX32TargetInfo(Triple); 7741 case llvm::Triple::nvptx64: 7742 return new NVPTX64TargetInfo(Triple); 7743 7744 case llvm::Triple::amdgcn: 7745 case llvm::Triple::r600: 7746 return new AMDGPUTargetInfo(Triple); 7747 7748 case llvm::Triple::sparc: 7749 switch (os) { 7750 case llvm::Triple::Linux: 7751 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 7752 case llvm::Triple::Solaris: 7753 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple); 7754 case llvm::Triple::NetBSD: 7755 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 7756 case llvm::Triple::OpenBSD: 7757 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 7758 case llvm::Triple::RTEMS: 7759 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 7760 default: 7761 return new SparcV8TargetInfo(Triple); 7762 } 7763 7764 // The 'sparcel' architecture copies all the above cases except for Solaris. 7765 case llvm::Triple::sparcel: 7766 switch (os) { 7767 case llvm::Triple::Linux: 7768 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 7769 case llvm::Triple::NetBSD: 7770 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7771 case llvm::Triple::OpenBSD: 7772 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7773 case llvm::Triple::RTEMS: 7774 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 7775 default: 7776 return new SparcV8elTargetInfo(Triple); 7777 } 7778 7779 case llvm::Triple::sparcv9: 7780 switch (os) { 7781 case llvm::Triple::Linux: 7782 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 7783 case llvm::Triple::Solaris: 7784 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 7785 case llvm::Triple::NetBSD: 7786 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 7787 case llvm::Triple::OpenBSD: 7788 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 7789 case llvm::Triple::FreeBSD: 7790 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 7791 default: 7792 return new SparcV9TargetInfo(Triple); 7793 } 7794 7795 case llvm::Triple::systemz: 7796 switch (os) { 7797 case llvm::Triple::Linux: 7798 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 7799 default: 7800 return new SystemZTargetInfo(Triple); 7801 } 7802 7803 case llvm::Triple::tce: 7804 return new TCETargetInfo(Triple); 7805 7806 case llvm::Triple::x86: 7807 if (Triple.isOSDarwin()) 7808 return new DarwinI386TargetInfo(Triple); 7809 7810 switch (os) { 7811 case llvm::Triple::CloudABI: 7812 return new CloudABITargetInfo<X86_32TargetInfo>(Triple); 7813 case llvm::Triple::Linux: { 7814 switch (Triple.getEnvironment()) { 7815 default: 7816 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 7817 case llvm::Triple::Android: 7818 return new AndroidX86_32TargetInfo(Triple); 7819 } 7820 } 7821 case llvm::Triple::DragonFly: 7822 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 7823 case llvm::Triple::NetBSD: 7824 return new NetBSDI386TargetInfo(Triple); 7825 case llvm::Triple::OpenBSD: 7826 return new OpenBSDI386TargetInfo(Triple); 7827 case llvm::Triple::Bitrig: 7828 return new BitrigI386TargetInfo(Triple); 7829 case llvm::Triple::FreeBSD: 7830 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7831 case llvm::Triple::KFreeBSD: 7832 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7833 case llvm::Triple::Minix: 7834 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 7835 case llvm::Triple::Solaris: 7836 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 7837 case llvm::Triple::Win32: { 7838 switch (Triple.getEnvironment()) { 7839 case llvm::Triple::Cygnus: 7840 return new CygwinX86_32TargetInfo(Triple); 7841 case llvm::Triple::GNU: 7842 return new MinGWX86_32TargetInfo(Triple); 7843 case llvm::Triple::Itanium: 7844 case llvm::Triple::MSVC: 7845 default: // Assume MSVC for unknown environments 7846 return new MicrosoftX86_32TargetInfo(Triple); 7847 } 7848 } 7849 case llvm::Triple::Haiku: 7850 return new HaikuX86_32TargetInfo(Triple); 7851 case llvm::Triple::RTEMS: 7852 return new RTEMSX86_32TargetInfo(Triple); 7853 case llvm::Triple::NaCl: 7854 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 7855 case llvm::Triple::ELFIAMCU: 7856 return new MCUX86_32TargetInfo(Triple); 7857 default: 7858 return new X86_32TargetInfo(Triple); 7859 } 7860 7861 case llvm::Triple::x86_64: 7862 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 7863 return new DarwinX86_64TargetInfo(Triple); 7864 7865 switch (os) { 7866 case llvm::Triple::CloudABI: 7867 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 7868 case llvm::Triple::Linux: { 7869 switch (Triple.getEnvironment()) { 7870 default: 7871 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 7872 case llvm::Triple::Android: 7873 return new AndroidX86_64TargetInfo(Triple); 7874 } 7875 } 7876 case llvm::Triple::DragonFly: 7877 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 7878 case llvm::Triple::NetBSD: 7879 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 7880 case llvm::Triple::OpenBSD: 7881 return new OpenBSDX86_64TargetInfo(Triple); 7882 case llvm::Triple::Bitrig: 7883 return new BitrigX86_64TargetInfo(Triple); 7884 case llvm::Triple::FreeBSD: 7885 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7886 case llvm::Triple::KFreeBSD: 7887 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7888 case llvm::Triple::Solaris: 7889 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 7890 case llvm::Triple::Win32: { 7891 switch (Triple.getEnvironment()) { 7892 case llvm::Triple::Cygnus: 7893 return new CygwinX86_64TargetInfo(Triple); 7894 case llvm::Triple::GNU: 7895 return new MinGWX86_64TargetInfo(Triple); 7896 case llvm::Triple::MSVC: 7897 default: // Assume MSVC for unknown environments 7898 return new MicrosoftX86_64TargetInfo(Triple); 7899 } 7900 } 7901 case llvm::Triple::NaCl: 7902 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 7903 case llvm::Triple::PS4: 7904 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 7905 default: 7906 return new X86_64TargetInfo(Triple); 7907 } 7908 7909 case llvm::Triple::spir: { 7910 if (Triple.getOS() != llvm::Triple::UnknownOS || 7911 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7912 return nullptr; 7913 return new SPIR32TargetInfo(Triple); 7914 } 7915 case llvm::Triple::spir64: { 7916 if (Triple.getOS() != llvm::Triple::UnknownOS || 7917 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7918 return nullptr; 7919 return new SPIR64TargetInfo(Triple); 7920 } 7921 case llvm::Triple::wasm32: 7922 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 7923 return nullptr; 7924 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple); 7925 case llvm::Triple::wasm64: 7926 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 7927 return nullptr; 7928 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple); 7929 } 7930 } 7931 7932 /// CreateTargetInfo - Return the target info object for the specified target 7933 /// options. 7934 TargetInfo * 7935 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 7936 const std::shared_ptr<TargetOptions> &Opts) { 7937 llvm::Triple Triple(Opts->Triple); 7938 7939 // Construct the target 7940 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 7941 if (!Target) { 7942 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 7943 return nullptr; 7944 } 7945 Target->TargetOpts = Opts; 7946 7947 // Set the target CPU if specified. 7948 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 7949 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 7950 return nullptr; 7951 } 7952 7953 // Set the target ABI if specified. 7954 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 7955 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 7956 return nullptr; 7957 } 7958 7959 // Set the fp math unit. 7960 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 7961 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 7962 return nullptr; 7963 } 7964 7965 // Compute the default target features, we need the target to handle this 7966 // because features may have dependencies on one another. 7967 llvm::StringMap<bool> Features; 7968 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 7969 Opts->FeaturesAsWritten)) 7970 return nullptr; 7971 7972 // Add the features to the compile options. 7973 Opts->Features.clear(); 7974 for (const auto &F : Features) 7975 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 7976 7977 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 7978 return nullptr; 7979 7980 return Target.release(); 7981 } 7982