1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 // Ananas target 115 template<typename Target> 116 class AnanasTargetInfo : public OSTargetInfo<Target> { 117 protected: 118 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 119 MacroBuilder &Builder) const override { 120 // Ananas defines 121 Builder.defineMacro("__Ananas__"); 122 Builder.defineMacro("__ELF__"); 123 } 124 public: 125 AnanasTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 126 : OSTargetInfo<Target>(Triple, Opts) {} 127 }; 128 129 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 130 const llvm::Triple &Triple, 131 StringRef &PlatformName, 132 VersionTuple &PlatformMinVersion) { 133 Builder.defineMacro("__APPLE_CC__", "6000"); 134 Builder.defineMacro("__APPLE__"); 135 Builder.defineMacro("__STDC_NO_THREADS__"); 136 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 137 // AddressSanitizer doesn't play well with source fortification, which is on 138 // by default on Darwin. 139 if (Opts.Sanitize.has(SanitizerKind::Address)) 140 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 141 142 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 143 if (!Opts.ObjC1) { 144 // __weak is always defined, for use in blocks and with objc pointers. 145 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 146 Builder.defineMacro("__strong", ""); 147 Builder.defineMacro("__unsafe_unretained", ""); 148 } 149 150 if (Opts.Static) 151 Builder.defineMacro("__STATIC__"); 152 else 153 Builder.defineMacro("__DYNAMIC__"); 154 155 if (Opts.POSIXThreads) 156 Builder.defineMacro("_REENTRANT"); 157 158 // Get the platform type and version number from the triple. 159 unsigned Maj, Min, Rev; 160 if (Triple.isMacOSX()) { 161 Triple.getMacOSXVersion(Maj, Min, Rev); 162 PlatformName = "macos"; 163 } else { 164 Triple.getOSVersion(Maj, Min, Rev); 165 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 166 } 167 168 // If -target arch-pc-win32-macho option specified, we're 169 // generating code for Win32 ABI. No need to emit 170 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 171 if (PlatformName == "win32") { 172 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 173 return; 174 } 175 176 // Set the appropriate OS version define. 177 if (Triple.isiOS()) { 178 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 179 char Str[7]; 180 if (Maj < 10) { 181 Str[0] = '0' + Maj; 182 Str[1] = '0' + (Min / 10); 183 Str[2] = '0' + (Min % 10); 184 Str[3] = '0' + (Rev / 10); 185 Str[4] = '0' + (Rev % 10); 186 Str[5] = '\0'; 187 } else { 188 // Handle versions >= 10. 189 Str[0] = '0' + (Maj / 10); 190 Str[1] = '0' + (Maj % 10); 191 Str[2] = '0' + (Min / 10); 192 Str[3] = '0' + (Min % 10); 193 Str[4] = '0' + (Rev / 10); 194 Str[5] = '0' + (Rev % 10); 195 Str[6] = '\0'; 196 } 197 if (Triple.isTvOS()) 198 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 199 else 200 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 201 Str); 202 203 } else if (Triple.isWatchOS()) { 204 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 205 char Str[6]; 206 Str[0] = '0' + Maj; 207 Str[1] = '0' + (Min / 10); 208 Str[2] = '0' + (Min % 10); 209 Str[3] = '0' + (Rev / 10); 210 Str[4] = '0' + (Rev % 10); 211 Str[5] = '\0'; 212 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 213 } else if (Triple.isMacOSX()) { 214 // Note that the Driver allows versions which aren't representable in the 215 // define (because we only get a single digit for the minor and micro 216 // revision numbers). So, we limit them to the maximum representable 217 // version. 218 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 219 char Str[7]; 220 if (Maj < 10 || (Maj == 10 && Min < 10)) { 221 Str[0] = '0' + (Maj / 10); 222 Str[1] = '0' + (Maj % 10); 223 Str[2] = '0' + std::min(Min, 9U); 224 Str[3] = '0' + std::min(Rev, 9U); 225 Str[4] = '\0'; 226 } else { 227 // Handle versions > 10.9. 228 Str[0] = '0' + (Maj / 10); 229 Str[1] = '0' + (Maj % 10); 230 Str[2] = '0' + (Min / 10); 231 Str[3] = '0' + (Min % 10); 232 Str[4] = '0' + (Rev / 10); 233 Str[5] = '0' + (Rev % 10); 234 Str[6] = '\0'; 235 } 236 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 237 } 238 239 // Tell users about the kernel if there is one. 240 if (Triple.isOSDarwin()) 241 Builder.defineMacro("__MACH__"); 242 243 // The Watch ABI uses Dwarf EH. 244 if(Triple.isWatchABI()) 245 Builder.defineMacro("__ARM_DWARF_EH__"); 246 247 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 248 } 249 250 template<typename Target> 251 class DarwinTargetInfo : public OSTargetInfo<Target> { 252 protected: 253 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 254 MacroBuilder &Builder) const override { 255 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 256 this->PlatformMinVersion); 257 } 258 259 public: 260 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 261 : OSTargetInfo<Target>(Triple, Opts) { 262 // By default, no TLS, and we whitelist permitted architecture/OS 263 // combinations. 264 this->TLSSupported = false; 265 266 if (Triple.isMacOSX()) 267 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 268 else if (Triple.isiOS()) { 269 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 270 if (Triple.getArch() == llvm::Triple::x86_64 || 271 Triple.getArch() == llvm::Triple::aarch64) 272 this->TLSSupported = !Triple.isOSVersionLT(8); 273 else if (Triple.getArch() == llvm::Triple::x86 || 274 Triple.getArch() == llvm::Triple::arm || 275 Triple.getArch() == llvm::Triple::thumb) 276 this->TLSSupported = !Triple.isOSVersionLT(9); 277 } else if (Triple.isWatchOS()) 278 this->TLSSupported = !Triple.isOSVersionLT(2); 279 280 this->MCountName = "\01mcount"; 281 } 282 283 std::string isValidSectionSpecifier(StringRef SR) const override { 284 // Let MCSectionMachO validate this. 285 StringRef Segment, Section; 286 unsigned TAA, StubSize; 287 bool HasTAA; 288 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 289 TAA, HasTAA, StubSize); 290 } 291 292 const char *getStaticInitSectionSpecifier() const override { 293 // FIXME: We should return 0 when building kexts. 294 return "__TEXT,__StaticInit,regular,pure_instructions"; 295 } 296 297 /// Darwin does not support protected visibility. Darwin's "default" 298 /// is very similar to ELF's "protected"; Darwin requires a "weak" 299 /// attribute on declarations that can be dynamically replaced. 300 bool hasProtectedVisibility() const override { 301 return false; 302 } 303 304 unsigned getExnObjectAlignment() const override { 305 // The alignment of an exception object is 8-bytes for darwin since 306 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 307 // and therefore doesn't guarantee 16-byte alignment. 308 return 64; 309 } 310 }; 311 312 313 // DragonFlyBSD Target 314 template<typename Target> 315 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 316 protected: 317 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 318 MacroBuilder &Builder) const override { 319 // DragonFly defines; list based off of gcc output 320 Builder.defineMacro("__DragonFly__"); 321 Builder.defineMacro("__DragonFly_cc_version", "100001"); 322 Builder.defineMacro("__ELF__"); 323 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 324 Builder.defineMacro("__tune_i386__"); 325 DefineStd(Builder, "unix", Opts); 326 } 327 public: 328 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 329 : OSTargetInfo<Target>(Triple, Opts) { 330 switch (Triple.getArch()) { 331 default: 332 case llvm::Triple::x86: 333 case llvm::Triple::x86_64: 334 this->MCountName = ".mcount"; 335 break; 336 } 337 } 338 }; 339 340 #ifndef FREEBSD_CC_VERSION 341 #define FREEBSD_CC_VERSION 0U 342 #endif 343 344 // FreeBSD Target 345 template<typename Target> 346 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 347 protected: 348 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 349 MacroBuilder &Builder) const override { 350 // FreeBSD defines; list based off of gcc output 351 352 unsigned Release = Triple.getOSMajorVersion(); 353 if (Release == 0U) 354 Release = 8U; 355 unsigned CCVersion = FREEBSD_CC_VERSION; 356 if (CCVersion == 0U) 357 CCVersion = Release * 100000U + 1U; 358 359 Builder.defineMacro("__FreeBSD__", Twine(Release)); 360 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 361 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 362 DefineStd(Builder, "unix", Opts); 363 Builder.defineMacro("__ELF__"); 364 365 // On FreeBSD, wchar_t contains the number of the code point as 366 // used by the character set of the locale. These character sets are 367 // not necessarily a superset of ASCII. 368 // 369 // FIXME: This is wrong; the macro refers to the numerical values 370 // of wchar_t *literals*, which are not locale-dependent. However, 371 // FreeBSD systems apparently depend on us getting this wrong, and 372 // setting this to 1 is conforming even if all the basic source 373 // character literals have the same encoding as char and wchar_t. 374 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 375 } 376 public: 377 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 378 : OSTargetInfo<Target>(Triple, Opts) { 379 switch (Triple.getArch()) { 380 default: 381 case llvm::Triple::x86: 382 case llvm::Triple::x86_64: 383 this->MCountName = ".mcount"; 384 break; 385 case llvm::Triple::mips: 386 case llvm::Triple::mipsel: 387 case llvm::Triple::ppc: 388 case llvm::Triple::ppc64: 389 case llvm::Triple::ppc64le: 390 this->MCountName = "_mcount"; 391 break; 392 case llvm::Triple::arm: 393 this->MCountName = "__mcount"; 394 break; 395 } 396 } 397 }; 398 399 // GNU/kFreeBSD Target 400 template<typename Target> 401 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 402 protected: 403 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 404 MacroBuilder &Builder) const override { 405 // GNU/kFreeBSD defines; list based off of gcc output 406 407 DefineStd(Builder, "unix", Opts); 408 Builder.defineMacro("__FreeBSD_kernel__"); 409 Builder.defineMacro("__GLIBC__"); 410 Builder.defineMacro("__ELF__"); 411 if (Opts.POSIXThreads) 412 Builder.defineMacro("_REENTRANT"); 413 if (Opts.CPlusPlus) 414 Builder.defineMacro("_GNU_SOURCE"); 415 } 416 public: 417 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 418 : OSTargetInfo<Target>(Triple, Opts) {} 419 }; 420 421 // Haiku Target 422 template<typename Target> 423 class HaikuTargetInfo : public OSTargetInfo<Target> { 424 protected: 425 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 426 MacroBuilder &Builder) const override { 427 // Haiku defines; list based off of gcc output 428 Builder.defineMacro("__HAIKU__"); 429 Builder.defineMacro("__ELF__"); 430 DefineStd(Builder, "unix", Opts); 431 } 432 public: 433 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 434 : OSTargetInfo<Target>(Triple, Opts) { 435 this->SizeType = TargetInfo::UnsignedLong; 436 this->IntPtrType = TargetInfo::SignedLong; 437 this->PtrDiffType = TargetInfo::SignedLong; 438 this->ProcessIDType = TargetInfo::SignedLong; 439 this->TLSSupported = false; 440 441 } 442 }; 443 444 // Minix Target 445 template<typename Target> 446 class MinixTargetInfo : public OSTargetInfo<Target> { 447 protected: 448 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 449 MacroBuilder &Builder) const override { 450 // Minix defines 451 452 Builder.defineMacro("__minix", "3"); 453 Builder.defineMacro("_EM_WSIZE", "4"); 454 Builder.defineMacro("_EM_PSIZE", "4"); 455 Builder.defineMacro("_EM_SSIZE", "2"); 456 Builder.defineMacro("_EM_LSIZE", "4"); 457 Builder.defineMacro("_EM_FSIZE", "4"); 458 Builder.defineMacro("_EM_DSIZE", "8"); 459 Builder.defineMacro("__ELF__"); 460 DefineStd(Builder, "unix", Opts); 461 } 462 public: 463 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 464 : OSTargetInfo<Target>(Triple, Opts) {} 465 }; 466 467 // Linux target 468 template<typename Target> 469 class LinuxTargetInfo : public OSTargetInfo<Target> { 470 protected: 471 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 472 MacroBuilder &Builder) const override { 473 // Linux defines; list based off of gcc output 474 DefineStd(Builder, "unix", Opts); 475 DefineStd(Builder, "linux", Opts); 476 Builder.defineMacro("__gnu_linux__"); 477 Builder.defineMacro("__ELF__"); 478 if (Triple.isAndroid()) { 479 Builder.defineMacro("__ANDROID__", "1"); 480 unsigned Maj, Min, Rev; 481 Triple.getEnvironmentVersion(Maj, Min, Rev); 482 this->PlatformName = "android"; 483 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 484 if (Maj) 485 Builder.defineMacro("__ANDROID_API__", Twine(Maj)); 486 } 487 if (Opts.POSIXThreads) 488 Builder.defineMacro("_REENTRANT"); 489 if (Opts.CPlusPlus) 490 Builder.defineMacro("_GNU_SOURCE"); 491 if (this->HasFloat128) 492 Builder.defineMacro("__FLOAT128__"); 493 } 494 public: 495 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 496 : OSTargetInfo<Target>(Triple, Opts) { 497 this->WIntType = TargetInfo::UnsignedInt; 498 499 switch (Triple.getArch()) { 500 default: 501 break; 502 case llvm::Triple::ppc: 503 case llvm::Triple::ppc64: 504 case llvm::Triple::ppc64le: 505 this->MCountName = "_mcount"; 506 break; 507 case llvm::Triple::x86: 508 case llvm::Triple::x86_64: 509 case llvm::Triple::systemz: 510 this->HasFloat128 = true; 511 break; 512 } 513 } 514 515 const char *getStaticInitSectionSpecifier() const override { 516 return ".text.startup"; 517 } 518 }; 519 520 // NetBSD Target 521 template<typename Target> 522 class NetBSDTargetInfo : public OSTargetInfo<Target> { 523 protected: 524 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 525 MacroBuilder &Builder) const override { 526 // NetBSD defines; list based off of gcc output 527 Builder.defineMacro("__NetBSD__"); 528 Builder.defineMacro("__unix__"); 529 Builder.defineMacro("__ELF__"); 530 if (Opts.POSIXThreads) 531 Builder.defineMacro("_REENTRANT"); 532 533 switch (Triple.getArch()) { 534 default: 535 break; 536 case llvm::Triple::arm: 537 case llvm::Triple::armeb: 538 case llvm::Triple::thumb: 539 case llvm::Triple::thumbeb: 540 Builder.defineMacro("__ARM_DWARF_EH__"); 541 break; 542 } 543 } 544 public: 545 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 546 : OSTargetInfo<Target>(Triple, Opts) { 547 this->MCountName = "_mcount"; 548 } 549 }; 550 551 // OpenBSD Target 552 template<typename Target> 553 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 554 protected: 555 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 556 MacroBuilder &Builder) const override { 557 // OpenBSD defines; list based off of gcc output 558 559 Builder.defineMacro("__OpenBSD__"); 560 DefineStd(Builder, "unix", Opts); 561 Builder.defineMacro("__ELF__"); 562 if (Opts.POSIXThreads) 563 Builder.defineMacro("_REENTRANT"); 564 if (this->HasFloat128) 565 Builder.defineMacro("__FLOAT128__"); 566 } 567 public: 568 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 569 : OSTargetInfo<Target>(Triple, Opts) { 570 this->TLSSupported = false; 571 572 switch (Triple.getArch()) { 573 case llvm::Triple::x86: 574 case llvm::Triple::x86_64: 575 this->HasFloat128 = true; 576 // FALLTHROUGH 577 default: 578 this->MCountName = "__mcount"; 579 break; 580 case llvm::Triple::mips64: 581 case llvm::Triple::mips64el: 582 case llvm::Triple::ppc: 583 case llvm::Triple::sparcv9: 584 this->MCountName = "_mcount"; 585 break; 586 } 587 } 588 }; 589 590 // Bitrig Target 591 template<typename Target> 592 class BitrigTargetInfo : public OSTargetInfo<Target> { 593 protected: 594 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 595 MacroBuilder &Builder) const override { 596 // Bitrig defines; list based off of gcc output 597 598 Builder.defineMacro("__Bitrig__"); 599 DefineStd(Builder, "unix", Opts); 600 Builder.defineMacro("__ELF__"); 601 if (Opts.POSIXThreads) 602 Builder.defineMacro("_REENTRANT"); 603 604 switch (Triple.getArch()) { 605 default: 606 break; 607 case llvm::Triple::arm: 608 case llvm::Triple::armeb: 609 case llvm::Triple::thumb: 610 case llvm::Triple::thumbeb: 611 Builder.defineMacro("__ARM_DWARF_EH__"); 612 break; 613 } 614 } 615 public: 616 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 617 : OSTargetInfo<Target>(Triple, Opts) { 618 this->MCountName = "__mcount"; 619 } 620 }; 621 622 // PSP Target 623 template<typename Target> 624 class PSPTargetInfo : public OSTargetInfo<Target> { 625 protected: 626 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 627 MacroBuilder &Builder) const override { 628 // PSP defines; list based on the output of the pspdev gcc toolchain. 629 Builder.defineMacro("PSP"); 630 Builder.defineMacro("_PSP"); 631 Builder.defineMacro("__psp__"); 632 Builder.defineMacro("__ELF__"); 633 } 634 public: 635 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 636 }; 637 638 // PS3 PPU Target 639 template<typename Target> 640 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 641 protected: 642 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 643 MacroBuilder &Builder) const override { 644 // PS3 PPU defines. 645 Builder.defineMacro("__PPC__"); 646 Builder.defineMacro("__PPU__"); 647 Builder.defineMacro("__CELLOS_LV2__"); 648 Builder.defineMacro("__ELF__"); 649 Builder.defineMacro("__LP32__"); 650 Builder.defineMacro("_ARCH_PPC64"); 651 Builder.defineMacro("__powerpc64__"); 652 } 653 public: 654 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 655 : OSTargetInfo<Target>(Triple, Opts) { 656 this->LongWidth = this->LongAlign = 32; 657 this->PointerWidth = this->PointerAlign = 32; 658 this->IntMaxType = TargetInfo::SignedLongLong; 659 this->Int64Type = TargetInfo::SignedLongLong; 660 this->SizeType = TargetInfo::UnsignedInt; 661 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 662 } 663 }; 664 665 template <typename Target> 666 class PS4OSTargetInfo : public OSTargetInfo<Target> { 667 protected: 668 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 669 MacroBuilder &Builder) const override { 670 Builder.defineMacro("__FreeBSD__", "9"); 671 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 672 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 673 DefineStd(Builder, "unix", Opts); 674 Builder.defineMacro("__ELF__"); 675 Builder.defineMacro("__ORBIS__"); 676 } 677 public: 678 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 679 : OSTargetInfo<Target>(Triple, Opts) { 680 this->WCharType = this->UnsignedShort; 681 682 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 683 this->MaxTLSAlign = 256; 684 685 // On PS4, do not honor explicit bit field alignment, 686 // as in "__attribute__((aligned(2))) int b : 1;". 687 this->UseExplicitBitFieldAlignment = false; 688 689 switch (Triple.getArch()) { 690 default: 691 case llvm::Triple::x86_64: 692 this->MCountName = ".mcount"; 693 break; 694 } 695 } 696 }; 697 698 // Solaris target 699 template<typename Target> 700 class SolarisTargetInfo : public OSTargetInfo<Target> { 701 protected: 702 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 703 MacroBuilder &Builder) const override { 704 DefineStd(Builder, "sun", Opts); 705 DefineStd(Builder, "unix", Opts); 706 Builder.defineMacro("__ELF__"); 707 Builder.defineMacro("__svr4__"); 708 Builder.defineMacro("__SVR4"); 709 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 710 // newer, but to 500 for everything else. feature_test.h has a check to 711 // ensure that you are not using C99 with an old version of X/Open or C89 712 // with a new version. 713 if (Opts.C99) 714 Builder.defineMacro("_XOPEN_SOURCE", "600"); 715 else 716 Builder.defineMacro("_XOPEN_SOURCE", "500"); 717 if (Opts.CPlusPlus) 718 Builder.defineMacro("__C99FEATURES__"); 719 Builder.defineMacro("_LARGEFILE_SOURCE"); 720 Builder.defineMacro("_LARGEFILE64_SOURCE"); 721 Builder.defineMacro("__EXTENSIONS__"); 722 Builder.defineMacro("_REENTRANT"); 723 } 724 public: 725 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 726 : OSTargetInfo<Target>(Triple, Opts) { 727 this->WCharType = this->SignedInt; 728 // FIXME: WIntType should be SignedLong 729 } 730 }; 731 732 // Windows target 733 template<typename Target> 734 class WindowsTargetInfo : public OSTargetInfo<Target> { 735 protected: 736 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 737 MacroBuilder &Builder) const override { 738 Builder.defineMacro("_WIN32"); 739 } 740 void getVisualStudioDefines(const LangOptions &Opts, 741 MacroBuilder &Builder) const { 742 if (Opts.CPlusPlus) { 743 if (Opts.RTTIData) 744 Builder.defineMacro("_CPPRTTI"); 745 746 if (Opts.CXXExceptions) 747 Builder.defineMacro("_CPPUNWIND"); 748 } 749 750 if (Opts.Bool) 751 Builder.defineMacro("__BOOL_DEFINED"); 752 753 if (!Opts.CharIsSigned) 754 Builder.defineMacro("_CHAR_UNSIGNED"); 755 756 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 757 // but it works for now. 758 if (Opts.POSIXThreads) 759 Builder.defineMacro("_MT"); 760 761 if (Opts.MSCompatibilityVersion) { 762 Builder.defineMacro("_MSC_VER", 763 Twine(Opts.MSCompatibilityVersion / 100000)); 764 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 765 // FIXME We cannot encode the revision information into 32-bits 766 Builder.defineMacro("_MSC_BUILD", Twine(1)); 767 768 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 769 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 770 771 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 772 if (Opts.CPlusPlus1z) 773 Builder.defineMacro("_MSVC_LANG", "201403L"); 774 else if (Opts.CPlusPlus14) 775 Builder.defineMacro("_MSVC_LANG", "201402L"); 776 } 777 } 778 779 if (Opts.MicrosoftExt) { 780 Builder.defineMacro("_MSC_EXTENSIONS"); 781 782 if (Opts.CPlusPlus11) { 783 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 784 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 785 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 786 } 787 } 788 789 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 790 } 791 792 public: 793 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 794 : OSTargetInfo<Target>(Triple, Opts) {} 795 }; 796 797 template <typename Target> 798 class NaClTargetInfo : public OSTargetInfo<Target> { 799 protected: 800 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 801 MacroBuilder &Builder) const override { 802 if (Opts.POSIXThreads) 803 Builder.defineMacro("_REENTRANT"); 804 if (Opts.CPlusPlus) 805 Builder.defineMacro("_GNU_SOURCE"); 806 807 DefineStd(Builder, "unix", Opts); 808 Builder.defineMacro("__ELF__"); 809 Builder.defineMacro("__native_client__"); 810 } 811 812 public: 813 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 814 : OSTargetInfo<Target>(Triple, Opts) { 815 this->LongAlign = 32; 816 this->LongWidth = 32; 817 this->PointerAlign = 32; 818 this->PointerWidth = 32; 819 this->IntMaxType = TargetInfo::SignedLongLong; 820 this->Int64Type = TargetInfo::SignedLongLong; 821 this->DoubleAlign = 64; 822 this->LongDoubleWidth = 64; 823 this->LongDoubleAlign = 64; 824 this->LongLongWidth = 64; 825 this->LongLongAlign = 64; 826 this->SizeType = TargetInfo::UnsignedInt; 827 this->PtrDiffType = TargetInfo::SignedInt; 828 this->IntPtrType = TargetInfo::SignedInt; 829 // RegParmMax is inherited from the underlying architecture. 830 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 831 if (Triple.getArch() == llvm::Triple::arm) { 832 // Handled in ARM's setABI(). 833 } else if (Triple.getArch() == llvm::Triple::x86) { 834 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 835 } else if (Triple.getArch() == llvm::Triple::x86_64) { 836 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 837 } else if (Triple.getArch() == llvm::Triple::mipsel) { 838 // Handled on mips' setDataLayout. 839 } else { 840 assert(Triple.getArch() == llvm::Triple::le32); 841 this->resetDataLayout("e-p:32:32-i64:64"); 842 } 843 } 844 }; 845 846 // Fuchsia Target 847 template<typename Target> 848 class FuchsiaTargetInfo : public OSTargetInfo<Target> { 849 protected: 850 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 851 MacroBuilder &Builder) const override { 852 Builder.defineMacro("__Fuchsia__"); 853 Builder.defineMacro("__ELF__"); 854 if (Opts.POSIXThreads) 855 Builder.defineMacro("_REENTRANT"); 856 // Required by the libc++ locale support. 857 if (Opts.CPlusPlus) 858 Builder.defineMacro("_GNU_SOURCE"); 859 } 860 public: 861 FuchsiaTargetInfo(const llvm::Triple &Triple, 862 const TargetOptions &Opts) 863 : OSTargetInfo<Target>(Triple, Opts) { 864 this->MCountName = "__mcount"; 865 } 866 }; 867 868 // WebAssembly target 869 template <typename Target> 870 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 871 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 872 MacroBuilder &Builder) const final { 873 // A common platform macro. 874 if (Opts.POSIXThreads) 875 Builder.defineMacro("_REENTRANT"); 876 // Follow g++ convention and predefine _GNU_SOURCE for C++. 877 if (Opts.CPlusPlus) 878 Builder.defineMacro("_GNU_SOURCE"); 879 } 880 881 // As an optimization, group static init code together in a section. 882 const char *getStaticInitSectionSpecifier() const final { 883 return ".text.__startup"; 884 } 885 886 public: 887 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 888 const TargetOptions &Opts) 889 : OSTargetInfo<Target>(Triple, Opts) { 890 this->MCountName = "__mcount"; 891 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 892 } 893 }; 894 895 //===----------------------------------------------------------------------===// 896 // Specific target implementations. 897 //===----------------------------------------------------------------------===// 898 899 // PPC abstract base class 900 class PPCTargetInfo : public TargetInfo { 901 static const Builtin::Info BuiltinInfo[]; 902 static const char * const GCCRegNames[]; 903 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 904 std::string CPU; 905 906 // Target cpu features. 907 bool HasAltivec; 908 bool HasVSX; 909 bool HasP8Vector; 910 bool HasP8Crypto; 911 bool HasDirectMove; 912 bool HasQPX; 913 bool HasHTM; 914 bool HasBPERMD; 915 bool HasExtDiv; 916 bool HasP9Vector; 917 918 protected: 919 std::string ABI; 920 921 public: 922 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 923 : TargetInfo(Triple), HasAltivec(false), HasVSX(false), HasP8Vector(false), 924 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 925 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) { 926 SuitableAlign = 128; 927 SimdDefaultAlign = 128; 928 LongDoubleWidth = LongDoubleAlign = 128; 929 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 930 } 931 932 /// \brief Flags for architecture specific defines. 933 typedef enum { 934 ArchDefineNone = 0, 935 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 936 ArchDefinePpcgr = 1 << 1, 937 ArchDefinePpcsq = 1 << 2, 938 ArchDefine440 = 1 << 3, 939 ArchDefine603 = 1 << 4, 940 ArchDefine604 = 1 << 5, 941 ArchDefinePwr4 = 1 << 6, 942 ArchDefinePwr5 = 1 << 7, 943 ArchDefinePwr5x = 1 << 8, 944 ArchDefinePwr6 = 1 << 9, 945 ArchDefinePwr6x = 1 << 10, 946 ArchDefinePwr7 = 1 << 11, 947 ArchDefinePwr8 = 1 << 12, 948 ArchDefinePwr9 = 1 << 13, 949 ArchDefineA2 = 1 << 14, 950 ArchDefineA2q = 1 << 15 951 } ArchDefineTypes; 952 953 // Set the language option for altivec based on our value. 954 void adjust(LangOptions &Opts) override { 955 if (HasAltivec) 956 Opts.AltiVec = 1; 957 TargetInfo::adjust(Opts); 958 } 959 960 // Note: GCC recognizes the following additional cpus: 961 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 962 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 963 // titan, rs64. 964 bool setCPU(const std::string &Name) override { 965 bool CPUKnown = llvm::StringSwitch<bool>(Name) 966 .Case("generic", true) 967 .Case("440", true) 968 .Case("450", true) 969 .Case("601", true) 970 .Case("602", true) 971 .Case("603", true) 972 .Case("603e", true) 973 .Case("603ev", true) 974 .Case("604", true) 975 .Case("604e", true) 976 .Case("620", true) 977 .Case("630", true) 978 .Case("g3", true) 979 .Case("7400", true) 980 .Case("g4", true) 981 .Case("7450", true) 982 .Case("g4+", true) 983 .Case("750", true) 984 .Case("970", true) 985 .Case("g5", true) 986 .Case("a2", true) 987 .Case("a2q", true) 988 .Case("e500mc", true) 989 .Case("e5500", true) 990 .Case("power3", true) 991 .Case("pwr3", true) 992 .Case("power4", true) 993 .Case("pwr4", true) 994 .Case("power5", true) 995 .Case("pwr5", true) 996 .Case("power5x", true) 997 .Case("pwr5x", true) 998 .Case("power6", true) 999 .Case("pwr6", true) 1000 .Case("power6x", true) 1001 .Case("pwr6x", true) 1002 .Case("power7", true) 1003 .Case("pwr7", true) 1004 .Case("power8", true) 1005 .Case("pwr8", true) 1006 .Case("power9", true) 1007 .Case("pwr9", true) 1008 .Case("powerpc", true) 1009 .Case("ppc", true) 1010 .Case("powerpc64", true) 1011 .Case("ppc64", true) 1012 .Case("powerpc64le", true) 1013 .Case("ppc64le", true) 1014 .Default(false); 1015 1016 if (CPUKnown) 1017 CPU = Name; 1018 1019 return CPUKnown; 1020 } 1021 1022 1023 StringRef getABI() const override { return ABI; } 1024 1025 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1026 return llvm::makeArrayRef(BuiltinInfo, 1027 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 1028 } 1029 1030 bool isCLZForZeroUndef() const override { return false; } 1031 1032 void getTargetDefines(const LangOptions &Opts, 1033 MacroBuilder &Builder) const override; 1034 1035 bool 1036 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1037 StringRef CPU, 1038 const std::vector<std::string> &FeaturesVec) const override; 1039 1040 bool handleTargetFeatures(std::vector<std::string> &Features, 1041 DiagnosticsEngine &Diags) override; 1042 bool hasFeature(StringRef Feature) const override; 1043 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 1044 bool Enabled) const override; 1045 1046 ArrayRef<const char *> getGCCRegNames() const override; 1047 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 1048 bool validateAsmConstraint(const char *&Name, 1049 TargetInfo::ConstraintInfo &Info) const override { 1050 switch (*Name) { 1051 default: return false; 1052 case 'O': // Zero 1053 break; 1054 case 'b': // Base register 1055 case 'f': // Floating point register 1056 Info.setAllowsRegister(); 1057 break; 1058 // FIXME: The following are added to allow parsing. 1059 // I just took a guess at what the actions should be. 1060 // Also, is more specific checking needed? I.e. specific registers? 1061 case 'd': // Floating point register (containing 64-bit value) 1062 case 'v': // Altivec vector register 1063 Info.setAllowsRegister(); 1064 break; 1065 case 'w': 1066 switch (Name[1]) { 1067 case 'd':// VSX vector register to hold vector double data 1068 case 'f':// VSX vector register to hold vector float data 1069 case 's':// VSX vector register to hold scalar float data 1070 case 'a':// Any VSX register 1071 case 'c':// An individual CR bit 1072 break; 1073 default: 1074 return false; 1075 } 1076 Info.setAllowsRegister(); 1077 Name++; // Skip over 'w'. 1078 break; 1079 case 'h': // `MQ', `CTR', or `LINK' register 1080 case 'q': // `MQ' register 1081 case 'c': // `CTR' register 1082 case 'l': // `LINK' register 1083 case 'x': // `CR' register (condition register) number 0 1084 case 'y': // `CR' register (condition register) 1085 case 'z': // `XER[CA]' carry bit (part of the XER register) 1086 Info.setAllowsRegister(); 1087 break; 1088 case 'I': // Signed 16-bit constant 1089 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1090 // (use `L' instead for SImode constants) 1091 case 'K': // Unsigned 16-bit constant 1092 case 'L': // Signed 16-bit constant shifted left 16 bits 1093 case 'M': // Constant larger than 31 1094 case 'N': // Exact power of 2 1095 case 'P': // Constant whose negation is a signed 16-bit constant 1096 case 'G': // Floating point constant that can be loaded into a 1097 // register with one instruction per word 1098 case 'H': // Integer/Floating point constant that can be loaded 1099 // into a register using three instructions 1100 break; 1101 case 'm': // Memory operand. Note that on PowerPC targets, m can 1102 // include addresses that update the base register. It 1103 // is therefore only safe to use `m' in an asm statement 1104 // if that asm statement accesses the operand exactly once. 1105 // The asm statement must also use `%U<opno>' as a 1106 // placeholder for the "update" flag in the corresponding 1107 // load or store instruction. For example: 1108 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1109 // is correct but: 1110 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1111 // is not. Use es rather than m if you don't want the base 1112 // register to be updated. 1113 case 'e': 1114 if (Name[1] != 's') 1115 return false; 1116 // es: A "stable" memory operand; that is, one which does not 1117 // include any automodification of the base register. Unlike 1118 // `m', this constraint can be used in asm statements that 1119 // might access the operand several times, or that might not 1120 // access it at all. 1121 Info.setAllowsMemory(); 1122 Name++; // Skip over 'e'. 1123 break; 1124 case 'Q': // Memory operand that is an offset from a register (it is 1125 // usually better to use `m' or `es' in asm statements) 1126 case 'Z': // Memory operand that is an indexed or indirect from a 1127 // register (it is usually better to use `m' or `es' in 1128 // asm statements) 1129 Info.setAllowsMemory(); 1130 Info.setAllowsRegister(); 1131 break; 1132 case 'R': // AIX TOC entry 1133 case 'a': // Address operand that is an indexed or indirect from a 1134 // register (`p' is preferable for asm statements) 1135 case 'S': // Constant suitable as a 64-bit mask operand 1136 case 'T': // Constant suitable as a 32-bit mask operand 1137 case 'U': // System V Release 4 small data area reference 1138 case 't': // AND masks that can be performed by two rldic{l, r} 1139 // instructions 1140 case 'W': // Vector constant that does not require memory 1141 case 'j': // Vector constant that is all zeros. 1142 break; 1143 // End FIXME. 1144 } 1145 return true; 1146 } 1147 std::string convertConstraint(const char *&Constraint) const override { 1148 std::string R; 1149 switch (*Constraint) { 1150 case 'e': 1151 case 'w': 1152 // Two-character constraint; add "^" hint for later parsing. 1153 R = std::string("^") + std::string(Constraint, 2); 1154 Constraint++; 1155 break; 1156 default: 1157 return TargetInfo::convertConstraint(Constraint); 1158 } 1159 return R; 1160 } 1161 const char *getClobbers() const override { 1162 return ""; 1163 } 1164 int getEHDataRegisterNumber(unsigned RegNo) const override { 1165 if (RegNo == 0) return 3; 1166 if (RegNo == 1) return 4; 1167 return -1; 1168 } 1169 1170 bool hasSjLjLowering() const override { 1171 return true; 1172 } 1173 1174 bool useFloat128ManglingForLongDouble() const override { 1175 return LongDoubleWidth == 128 && 1176 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() && 1177 getTriple().isOSBinFormatELF(); 1178 } 1179 }; 1180 1181 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1182 #define BUILTIN(ID, TYPE, ATTRS) \ 1183 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1184 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1185 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1186 #include "clang/Basic/BuiltinsPPC.def" 1187 }; 1188 1189 /// handleTargetFeatures - Perform initialization based on the user 1190 /// configured set of features. 1191 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1192 DiagnosticsEngine &Diags) { 1193 for (const auto &Feature : Features) { 1194 if (Feature == "+altivec") { 1195 HasAltivec = true; 1196 } else if (Feature == "+vsx") { 1197 HasVSX = true; 1198 } else if (Feature == "+bpermd") { 1199 HasBPERMD = true; 1200 } else if (Feature == "+extdiv") { 1201 HasExtDiv = true; 1202 } else if (Feature == "+power8-vector") { 1203 HasP8Vector = true; 1204 } else if (Feature == "+crypto") { 1205 HasP8Crypto = true; 1206 } else if (Feature == "+direct-move") { 1207 HasDirectMove = true; 1208 } else if (Feature == "+qpx") { 1209 HasQPX = true; 1210 } else if (Feature == "+htm") { 1211 HasHTM = true; 1212 } else if (Feature == "+float128") { 1213 HasFloat128 = true; 1214 } else if (Feature == "+power9-vector") { 1215 HasP9Vector = true; 1216 } 1217 // TODO: Finish this list and add an assert that we've handled them 1218 // all. 1219 } 1220 1221 return true; 1222 } 1223 1224 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1225 /// #defines that are not tied to a specific subtarget. 1226 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1227 MacroBuilder &Builder) const { 1228 // Target identification. 1229 Builder.defineMacro("__ppc__"); 1230 Builder.defineMacro("__PPC__"); 1231 Builder.defineMacro("_ARCH_PPC"); 1232 Builder.defineMacro("__powerpc__"); 1233 Builder.defineMacro("__POWERPC__"); 1234 if (PointerWidth == 64) { 1235 Builder.defineMacro("_ARCH_PPC64"); 1236 Builder.defineMacro("__powerpc64__"); 1237 Builder.defineMacro("__ppc64__"); 1238 Builder.defineMacro("__PPC64__"); 1239 } 1240 1241 // Target properties. 1242 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1243 Builder.defineMacro("_LITTLE_ENDIAN"); 1244 } else { 1245 if (getTriple().getOS() != llvm::Triple::NetBSD && 1246 getTriple().getOS() != llvm::Triple::OpenBSD) 1247 Builder.defineMacro("_BIG_ENDIAN"); 1248 } 1249 1250 // ABI options. 1251 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1252 Builder.defineMacro("_CALL_ELF", "1"); 1253 if (ABI == "elfv2") 1254 Builder.defineMacro("_CALL_ELF", "2"); 1255 1256 // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but 1257 // our suppport post-dates this and it should work on all 64-bit ppc linux 1258 // platforms. It is guaranteed to work on all elfv2 platforms. 1259 if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64) 1260 Builder.defineMacro("_CALL_LINUX", "1"); 1261 1262 // Subtarget options. 1263 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1264 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1265 1266 // FIXME: Should be controlled by command line option. 1267 if (LongDoubleWidth == 128) { 1268 Builder.defineMacro("__LONG_DOUBLE_128__"); 1269 Builder.defineMacro("__LONGDOUBLE128"); 1270 } 1271 1272 // Define this for elfv2 (64-bit only) or 64-bit darwin. 1273 if (ABI == "elfv2" || 1274 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64)) 1275 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16"); 1276 1277 // CPU identification. 1278 ArchDefineTypes defs = 1279 (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1280 .Case("440", ArchDefineName) 1281 .Case("450", ArchDefineName | ArchDefine440) 1282 .Case("601", ArchDefineName) 1283 .Case("602", ArchDefineName | ArchDefinePpcgr) 1284 .Case("603", ArchDefineName | ArchDefinePpcgr) 1285 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1286 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1287 .Case("604", ArchDefineName | ArchDefinePpcgr) 1288 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1289 .Case("620", ArchDefineName | ArchDefinePpcgr) 1290 .Case("630", ArchDefineName | ArchDefinePpcgr) 1291 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1292 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1293 .Case("750", ArchDefineName | ArchDefinePpcgr) 1294 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1295 ArchDefinePpcsq) 1296 .Case("a2", ArchDefineA2) 1297 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1298 .Case("pwr3", ArchDefinePpcgr) 1299 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1300 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1301 ArchDefinePpcsq) 1302 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 | 1303 ArchDefinePpcgr | ArchDefinePpcsq) 1304 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 | 1305 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1306 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x | 1307 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1308 ArchDefinePpcsq) 1309 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 | 1310 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1311 ArchDefinePpcgr | ArchDefinePpcsq) 1312 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x | 1313 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1314 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1315 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 | 1316 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1317 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1318 ArchDefinePpcsq) 1319 .Case("power3", ArchDefinePpcgr) 1320 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1321 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1322 ArchDefinePpcsq) 1323 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1324 ArchDefinePpcgr | ArchDefinePpcsq) 1325 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1326 ArchDefinePwr4 | ArchDefinePpcgr | 1327 ArchDefinePpcsq) 1328 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1329 ArchDefinePwr5 | ArchDefinePwr4 | 1330 ArchDefinePpcgr | ArchDefinePpcsq) 1331 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 | 1332 ArchDefinePwr5x | ArchDefinePwr5 | 1333 ArchDefinePwr4 | ArchDefinePpcgr | 1334 ArchDefinePpcsq) 1335 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1336 ArchDefinePwr6 | ArchDefinePwr5x | 1337 ArchDefinePwr5 | ArchDefinePwr4 | 1338 ArchDefinePpcgr | ArchDefinePpcsq) 1339 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 1340 ArchDefinePwr6x | ArchDefinePwr6 | 1341 ArchDefinePwr5x | ArchDefinePwr5 | 1342 ArchDefinePwr4 | ArchDefinePpcgr | 1343 ArchDefinePpcsq) 1344 // powerpc64le automatically defaults to at least power8. 1345 .Case("ppc64le", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1346 ArchDefinePwr6 | ArchDefinePwr5x | 1347 ArchDefinePwr5 | ArchDefinePwr4 | 1348 ArchDefinePpcgr | ArchDefinePpcsq) 1349 .Default(ArchDefineNone); 1350 1351 if (defs & ArchDefineName) 1352 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1353 if (defs & ArchDefinePpcgr) 1354 Builder.defineMacro("_ARCH_PPCGR"); 1355 if (defs & ArchDefinePpcsq) 1356 Builder.defineMacro("_ARCH_PPCSQ"); 1357 if (defs & ArchDefine440) 1358 Builder.defineMacro("_ARCH_440"); 1359 if (defs & ArchDefine603) 1360 Builder.defineMacro("_ARCH_603"); 1361 if (defs & ArchDefine604) 1362 Builder.defineMacro("_ARCH_604"); 1363 if (defs & ArchDefinePwr4) 1364 Builder.defineMacro("_ARCH_PWR4"); 1365 if (defs & ArchDefinePwr5) 1366 Builder.defineMacro("_ARCH_PWR5"); 1367 if (defs & ArchDefinePwr5x) 1368 Builder.defineMacro("_ARCH_PWR5X"); 1369 if (defs & ArchDefinePwr6) 1370 Builder.defineMacro("_ARCH_PWR6"); 1371 if (defs & ArchDefinePwr6x) 1372 Builder.defineMacro("_ARCH_PWR6X"); 1373 if (defs & ArchDefinePwr7) 1374 Builder.defineMacro("_ARCH_PWR7"); 1375 if (defs & ArchDefinePwr8) 1376 Builder.defineMacro("_ARCH_PWR8"); 1377 if (defs & ArchDefinePwr9) 1378 Builder.defineMacro("_ARCH_PWR9"); 1379 if (defs & ArchDefineA2) 1380 Builder.defineMacro("_ARCH_A2"); 1381 if (defs & ArchDefineA2q) { 1382 Builder.defineMacro("_ARCH_A2Q"); 1383 Builder.defineMacro("_ARCH_QP"); 1384 } 1385 1386 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1387 Builder.defineMacro("__bg__"); 1388 Builder.defineMacro("__THW_BLUEGENE__"); 1389 Builder.defineMacro("__bgq__"); 1390 Builder.defineMacro("__TOS_BGQ__"); 1391 } 1392 1393 if (HasAltivec) { 1394 Builder.defineMacro("__VEC__", "10206"); 1395 Builder.defineMacro("__ALTIVEC__"); 1396 } 1397 if (HasVSX) 1398 Builder.defineMacro("__VSX__"); 1399 if (HasP8Vector) 1400 Builder.defineMacro("__POWER8_VECTOR__"); 1401 if (HasP8Crypto) 1402 Builder.defineMacro("__CRYPTO__"); 1403 if (HasHTM) 1404 Builder.defineMacro("__HTM__"); 1405 if (HasFloat128) 1406 Builder.defineMacro("__FLOAT128__"); 1407 if (HasP9Vector) 1408 Builder.defineMacro("__POWER9_VECTOR__"); 1409 1410 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1411 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1412 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1413 if (PointerWidth == 64) 1414 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1415 1416 // We have support for the bswap intrinsics so we can define this. 1417 Builder.defineMacro("__HAVE_BSWAP__", "1"); 1418 1419 // FIXME: The following are not yet generated here by Clang, but are 1420 // generated by GCC: 1421 // 1422 // _SOFT_FLOAT_ 1423 // __RECIP_PRECISION__ 1424 // __APPLE_ALTIVEC__ 1425 // __RECIP__ 1426 // __RECIPF__ 1427 // __RSQRTE__ 1428 // __RSQRTEF__ 1429 // _SOFT_DOUBLE_ 1430 // __NO_LWSYNC__ 1431 // __CMODEL_MEDIUM__ 1432 // __CMODEL_LARGE__ 1433 // _CALL_SYSV 1434 // _CALL_DARWIN 1435 // __NO_FPRS__ 1436 } 1437 1438 // Handle explicit options being passed to the compiler here: if we've 1439 // explicitly turned off vsx and turned on any of: 1440 // - power8-vector 1441 // - direct-move 1442 // - float128 1443 // - power9-vector 1444 // then go ahead and error since the customer has expressed an incompatible 1445 // set of options. 1446 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1447 const std::vector<std::string> &FeaturesVec) { 1448 1449 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1450 FeaturesVec.end()) { 1451 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1452 FeaturesVec.end()) { 1453 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1454 << "-mno-vsx"; 1455 return false; 1456 } 1457 1458 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1459 FeaturesVec.end()) { 1460 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1461 << "-mno-vsx"; 1462 return false; 1463 } 1464 1465 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1466 FeaturesVec.end()) { 1467 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1468 << "-mno-vsx"; 1469 return false; 1470 } 1471 1472 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") != 1473 FeaturesVec.end()) { 1474 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector" 1475 << "-mno-vsx"; 1476 return false; 1477 } 1478 } 1479 1480 return true; 1481 } 1482 1483 bool PPCTargetInfo::initFeatureMap( 1484 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1485 const std::vector<std::string> &FeaturesVec) const { 1486 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1487 .Case("7400", true) 1488 .Case("g4", true) 1489 .Case("7450", true) 1490 .Case("g4+", true) 1491 .Case("970", true) 1492 .Case("g5", true) 1493 .Case("pwr6", true) 1494 .Case("pwr7", true) 1495 .Case("pwr8", true) 1496 .Case("pwr9", true) 1497 .Case("ppc64", true) 1498 .Case("ppc64le", true) 1499 .Default(false); 1500 1501 Features["qpx"] = (CPU == "a2q"); 1502 Features["power9-vector"] = (CPU == "pwr9"); 1503 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1504 .Case("ppc64le", true) 1505 .Case("pwr9", true) 1506 .Case("pwr8", true) 1507 .Default(false); 1508 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1509 .Case("ppc64le", true) 1510 .Case("pwr9", true) 1511 .Case("pwr8", true) 1512 .Default(false); 1513 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1514 .Case("ppc64le", true) 1515 .Case("pwr9", true) 1516 .Case("pwr8", true) 1517 .Case("pwr7", true) 1518 .Default(false); 1519 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1520 .Case("ppc64le", true) 1521 .Case("pwr9", true) 1522 .Case("pwr8", true) 1523 .Case("pwr7", true) 1524 .Default(false); 1525 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1526 .Case("ppc64le", true) 1527 .Case("pwr9", true) 1528 .Case("pwr8", true) 1529 .Default(false); 1530 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1531 .Case("ppc64le", true) 1532 .Case("pwr9", true) 1533 .Case("pwr8", true) 1534 .Case("pwr7", true) 1535 .Default(false); 1536 Features["htm"] = llvm::StringSwitch<bool>(CPU) 1537 .Case("ppc64le", true) 1538 .Case("pwr9", true) 1539 .Case("pwr8", true) 1540 .Default(false); 1541 1542 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1543 return false; 1544 1545 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1546 } 1547 1548 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1549 return llvm::StringSwitch<bool>(Feature) 1550 .Case("powerpc", true) 1551 .Case("altivec", HasAltivec) 1552 .Case("vsx", HasVSX) 1553 .Case("power8-vector", HasP8Vector) 1554 .Case("crypto", HasP8Crypto) 1555 .Case("direct-move", HasDirectMove) 1556 .Case("qpx", HasQPX) 1557 .Case("htm", HasHTM) 1558 .Case("bpermd", HasBPERMD) 1559 .Case("extdiv", HasExtDiv) 1560 .Case("float128", HasFloat128) 1561 .Case("power9-vector", HasP9Vector) 1562 .Default(false); 1563 } 1564 1565 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1566 StringRef Name, bool Enabled) const { 1567 if (Enabled) { 1568 // If we're enabling any of the vsx based features then enable vsx and 1569 // altivec. We'll diagnose any problems later. 1570 bool FeatureHasVSX = llvm::StringSwitch<bool>(Name) 1571 .Case("vsx", true) 1572 .Case("direct-move", true) 1573 .Case("power8-vector", true) 1574 .Case("power9-vector", true) 1575 .Case("float128", true) 1576 .Default(false); 1577 if (FeatureHasVSX) 1578 Features["vsx"] = Features["altivec"] = true; 1579 if (Name == "power9-vector") 1580 Features["power8-vector"] = true; 1581 Features[Name] = true; 1582 } else { 1583 // If we're disabling altivec or vsx go ahead and disable all of the vsx 1584 // features. 1585 if ((Name == "altivec") || (Name == "vsx")) 1586 Features["vsx"] = Features["direct-move"] = Features["power8-vector"] = 1587 Features["float128"] = Features["power9-vector"] = false; 1588 if (Name == "power8-vector") 1589 Features["power9-vector"] = false; 1590 Features[Name] = false; 1591 } 1592 } 1593 1594 const char * const PPCTargetInfo::GCCRegNames[] = { 1595 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1596 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1597 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1598 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1599 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1600 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1601 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1602 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1603 "mq", "lr", "ctr", "ap", 1604 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1605 "xer", 1606 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1607 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1608 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1609 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1610 "vrsave", "vscr", 1611 "spe_acc", "spefscr", 1612 "sfp" 1613 }; 1614 1615 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1616 return llvm::makeArrayRef(GCCRegNames); 1617 } 1618 1619 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1620 // While some of these aliases do map to different registers 1621 // they still share the same register name. 1622 { { "0" }, "r0" }, 1623 { { "1"}, "r1" }, 1624 { { "2" }, "r2" }, 1625 { { "3" }, "r3" }, 1626 { { "4" }, "r4" }, 1627 { { "5" }, "r5" }, 1628 { { "6" }, "r6" }, 1629 { { "7" }, "r7" }, 1630 { { "8" }, "r8" }, 1631 { { "9" }, "r9" }, 1632 { { "10" }, "r10" }, 1633 { { "11" }, "r11" }, 1634 { { "12" }, "r12" }, 1635 { { "13" }, "r13" }, 1636 { { "14" }, "r14" }, 1637 { { "15" }, "r15" }, 1638 { { "16" }, "r16" }, 1639 { { "17" }, "r17" }, 1640 { { "18" }, "r18" }, 1641 { { "19" }, "r19" }, 1642 { { "20" }, "r20" }, 1643 { { "21" }, "r21" }, 1644 { { "22" }, "r22" }, 1645 { { "23" }, "r23" }, 1646 { { "24" }, "r24" }, 1647 { { "25" }, "r25" }, 1648 { { "26" }, "r26" }, 1649 { { "27" }, "r27" }, 1650 { { "28" }, "r28" }, 1651 { { "29" }, "r29" }, 1652 { { "30" }, "r30" }, 1653 { { "31" }, "r31" }, 1654 { { "fr0" }, "f0" }, 1655 { { "fr1" }, "f1" }, 1656 { { "fr2" }, "f2" }, 1657 { { "fr3" }, "f3" }, 1658 { { "fr4" }, "f4" }, 1659 { { "fr5" }, "f5" }, 1660 { { "fr6" }, "f6" }, 1661 { { "fr7" }, "f7" }, 1662 { { "fr8" }, "f8" }, 1663 { { "fr9" }, "f9" }, 1664 { { "fr10" }, "f10" }, 1665 { { "fr11" }, "f11" }, 1666 { { "fr12" }, "f12" }, 1667 { { "fr13" }, "f13" }, 1668 { { "fr14" }, "f14" }, 1669 { { "fr15" }, "f15" }, 1670 { { "fr16" }, "f16" }, 1671 { { "fr17" }, "f17" }, 1672 { { "fr18" }, "f18" }, 1673 { { "fr19" }, "f19" }, 1674 { { "fr20" }, "f20" }, 1675 { { "fr21" }, "f21" }, 1676 { { "fr22" }, "f22" }, 1677 { { "fr23" }, "f23" }, 1678 { { "fr24" }, "f24" }, 1679 { { "fr25" }, "f25" }, 1680 { { "fr26" }, "f26" }, 1681 { { "fr27" }, "f27" }, 1682 { { "fr28" }, "f28" }, 1683 { { "fr29" }, "f29" }, 1684 { { "fr30" }, "f30" }, 1685 { { "fr31" }, "f31" }, 1686 { { "cc" }, "cr0" }, 1687 }; 1688 1689 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1690 return llvm::makeArrayRef(GCCRegAliases); 1691 } 1692 1693 class PPC32TargetInfo : public PPCTargetInfo { 1694 public: 1695 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1696 : PPCTargetInfo(Triple, Opts) { 1697 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1698 1699 switch (getTriple().getOS()) { 1700 case llvm::Triple::Linux: 1701 case llvm::Triple::FreeBSD: 1702 case llvm::Triple::NetBSD: 1703 SizeType = UnsignedInt; 1704 PtrDiffType = SignedInt; 1705 IntPtrType = SignedInt; 1706 break; 1707 default: 1708 break; 1709 } 1710 1711 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1712 LongDoubleWidth = LongDoubleAlign = 64; 1713 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1714 } 1715 1716 // PPC32 supports atomics up to 4 bytes. 1717 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1718 } 1719 1720 BuiltinVaListKind getBuiltinVaListKind() const override { 1721 // This is the ELF definition, and is overridden by the Darwin sub-target 1722 return TargetInfo::PowerABIBuiltinVaList; 1723 } 1724 }; 1725 1726 // Note: ABI differences may eventually require us to have a separate 1727 // TargetInfo for little endian. 1728 class PPC64TargetInfo : public PPCTargetInfo { 1729 public: 1730 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1731 : PPCTargetInfo(Triple, Opts) { 1732 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1733 IntMaxType = SignedLong; 1734 Int64Type = SignedLong; 1735 1736 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1737 resetDataLayout("e-m:e-i64:64-n32:64"); 1738 ABI = "elfv2"; 1739 } else { 1740 resetDataLayout("E-m:e-i64:64-n32:64"); 1741 ABI = "elfv1"; 1742 } 1743 1744 switch (getTriple().getOS()) { 1745 case llvm::Triple::FreeBSD: 1746 LongDoubleWidth = LongDoubleAlign = 64; 1747 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1748 break; 1749 case llvm::Triple::NetBSD: 1750 IntMaxType = SignedLongLong; 1751 Int64Type = SignedLongLong; 1752 break; 1753 default: 1754 break; 1755 } 1756 1757 // PPC64 supports atomics up to 8 bytes. 1758 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1759 } 1760 BuiltinVaListKind getBuiltinVaListKind() const override { 1761 return TargetInfo::CharPtrBuiltinVaList; 1762 } 1763 // PPC64 Linux-specific ABI options. 1764 bool setABI(const std::string &Name) override { 1765 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1766 ABI = Name; 1767 return true; 1768 } 1769 return false; 1770 } 1771 }; 1772 1773 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1774 public: 1775 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1776 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1777 HasAlignMac68kSupport = true; 1778 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1779 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1780 LongLongAlign = 32; 1781 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1782 } 1783 BuiltinVaListKind getBuiltinVaListKind() const override { 1784 return TargetInfo::CharPtrBuiltinVaList; 1785 } 1786 }; 1787 1788 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1789 public: 1790 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1791 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1792 HasAlignMac68kSupport = true; 1793 resetDataLayout("E-m:o-i64:64-n32:64"); 1794 } 1795 }; 1796 1797 static const unsigned NVPTXAddrSpaceMap[] = { 1798 0, // Default 1799 1, // opencl_global 1800 3, // opencl_local 1801 4, // opencl_constant 1802 // FIXME: generic has to be added to the target 1803 0, // opencl_generic 1804 1, // cuda_device 1805 4, // cuda_constant 1806 3, // cuda_shared 1807 }; 1808 1809 class NVPTXTargetInfo : public TargetInfo { 1810 static const char *const GCCRegNames[]; 1811 static const Builtin::Info BuiltinInfo[]; 1812 CudaArch GPU; 1813 std::unique_ptr<TargetInfo> HostTarget; 1814 1815 public: 1816 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 1817 unsigned TargetPointerWidth) 1818 : TargetInfo(Triple) { 1819 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) && 1820 "NVPTX only supports 32- and 64-bit modes."); 1821 1822 TLSSupported = false; 1823 AddrSpaceMap = &NVPTXAddrSpaceMap; 1824 UseAddrSpaceMapMangling = true; 1825 1826 // Define available target features 1827 // These must be defined in sorted order! 1828 NoAsmVariants = true; 1829 GPU = CudaArch::SM_20; 1830 1831 if (TargetPointerWidth == 32) 1832 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1833 else 1834 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1835 1836 // If possible, get a TargetInfo for our host triple, so we can match its 1837 // types. 1838 llvm::Triple HostTriple(Opts.HostTriple); 1839 if (!HostTriple.isNVPTX()) 1840 HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1841 1842 // If no host target, make some guesses about the data layout and return. 1843 if (!HostTarget) { 1844 LongWidth = LongAlign = TargetPointerWidth; 1845 PointerWidth = PointerAlign = TargetPointerWidth; 1846 switch (TargetPointerWidth) { 1847 case 32: 1848 SizeType = TargetInfo::UnsignedInt; 1849 PtrDiffType = TargetInfo::SignedInt; 1850 IntPtrType = TargetInfo::SignedInt; 1851 break; 1852 case 64: 1853 SizeType = TargetInfo::UnsignedLong; 1854 PtrDiffType = TargetInfo::SignedLong; 1855 IntPtrType = TargetInfo::SignedLong; 1856 break; 1857 default: 1858 llvm_unreachable("TargetPointerWidth must be 32 or 64"); 1859 } 1860 return; 1861 } 1862 1863 // Copy properties from host target. 1864 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1865 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1866 BoolWidth = HostTarget->getBoolWidth(); 1867 BoolAlign = HostTarget->getBoolAlign(); 1868 IntWidth = HostTarget->getIntWidth(); 1869 IntAlign = HostTarget->getIntAlign(); 1870 HalfWidth = HostTarget->getHalfWidth(); 1871 HalfAlign = HostTarget->getHalfAlign(); 1872 FloatWidth = HostTarget->getFloatWidth(); 1873 FloatAlign = HostTarget->getFloatAlign(); 1874 DoubleWidth = HostTarget->getDoubleWidth(); 1875 DoubleAlign = HostTarget->getDoubleAlign(); 1876 LongWidth = HostTarget->getLongWidth(); 1877 LongAlign = HostTarget->getLongAlign(); 1878 LongLongWidth = HostTarget->getLongLongWidth(); 1879 LongLongAlign = HostTarget->getLongLongAlign(); 1880 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1881 NewAlign = HostTarget->getNewAlign(); 1882 DefaultAlignForAttributeAligned = 1883 HostTarget->getDefaultAlignForAttributeAligned(); 1884 SizeType = HostTarget->getSizeType(); 1885 IntMaxType = HostTarget->getIntMaxType(); 1886 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1887 IntPtrType = HostTarget->getIntPtrType(); 1888 WCharType = HostTarget->getWCharType(); 1889 WIntType = HostTarget->getWIntType(); 1890 Char16Type = HostTarget->getChar16Type(); 1891 Char32Type = HostTarget->getChar32Type(); 1892 Int64Type = HostTarget->getInt64Type(); 1893 SigAtomicType = HostTarget->getSigAtomicType(); 1894 ProcessIDType = HostTarget->getProcessIDType(); 1895 1896 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1897 UseZeroLengthBitfieldAlignment = 1898 HostTarget->useZeroLengthBitfieldAlignment(); 1899 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1900 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1901 1902 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and 1903 // we need those macros to be identical on host and device, because (among 1904 // other things) they affect which standard library classes are defined, and 1905 // we need all classes to be defined on both the host and device. 1906 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth(); 1907 1908 // Properties intentionally not copied from host: 1909 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1910 // host/device boundary. 1911 // - SuitableAlign: Not visible across the host/device boundary, and may 1912 // correctly be different on host/device, e.g. if host has wider vector 1913 // types than device. 1914 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1915 // as its double type, but that's not necessarily true on the host. 1916 // TODO: nvcc emits a warning when using long double on device; we should 1917 // do the same. 1918 } 1919 void getTargetDefines(const LangOptions &Opts, 1920 MacroBuilder &Builder) const override { 1921 Builder.defineMacro("__PTX__"); 1922 Builder.defineMacro("__NVPTX__"); 1923 if (Opts.CUDAIsDevice) { 1924 // Set __CUDA_ARCH__ for the GPU specified. 1925 std::string CUDAArchCode = [this] { 1926 switch (GPU) { 1927 case CudaArch::UNKNOWN: 1928 assert(false && "No GPU arch when compiling CUDA device code."); 1929 return ""; 1930 case CudaArch::SM_20: 1931 return "200"; 1932 case CudaArch::SM_21: 1933 return "210"; 1934 case CudaArch::SM_30: 1935 return "300"; 1936 case CudaArch::SM_32: 1937 return "320"; 1938 case CudaArch::SM_35: 1939 return "350"; 1940 case CudaArch::SM_37: 1941 return "370"; 1942 case CudaArch::SM_50: 1943 return "500"; 1944 case CudaArch::SM_52: 1945 return "520"; 1946 case CudaArch::SM_53: 1947 return "530"; 1948 case CudaArch::SM_60: 1949 return "600"; 1950 case CudaArch::SM_61: 1951 return "610"; 1952 case CudaArch::SM_62: 1953 return "620"; 1954 } 1955 llvm_unreachable("unhandled CudaArch"); 1956 }(); 1957 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1958 } 1959 } 1960 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1961 return llvm::makeArrayRef(BuiltinInfo, 1962 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1963 } 1964 bool 1965 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1966 StringRef CPU, 1967 const std::vector<std::string> &FeaturesVec) const override { 1968 Features["satom"] = GPU >= CudaArch::SM_60; 1969 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1970 } 1971 1972 bool hasFeature(StringRef Feature) const override { 1973 return llvm::StringSwitch<bool>(Feature) 1974 .Cases("ptx", "nvptx", true) 1975 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope. 1976 .Default(false); 1977 } 1978 1979 ArrayRef<const char *> getGCCRegNames() const override; 1980 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1981 // No aliases. 1982 return None; 1983 } 1984 bool validateAsmConstraint(const char *&Name, 1985 TargetInfo::ConstraintInfo &Info) const override { 1986 switch (*Name) { 1987 default: 1988 return false; 1989 case 'c': 1990 case 'h': 1991 case 'r': 1992 case 'l': 1993 case 'f': 1994 case 'd': 1995 Info.setAllowsRegister(); 1996 return true; 1997 } 1998 } 1999 const char *getClobbers() const override { 2000 // FIXME: Is this really right? 2001 return ""; 2002 } 2003 BuiltinVaListKind getBuiltinVaListKind() const override { 2004 // FIXME: implement 2005 return TargetInfo::CharPtrBuiltinVaList; 2006 } 2007 bool setCPU(const std::string &Name) override { 2008 GPU = StringToCudaArch(Name); 2009 return GPU != CudaArch::UNKNOWN; 2010 } 2011 void setSupportedOpenCLOpts() override { 2012 auto &Opts = getSupportedOpenCLOpts(); 2013 Opts.support("cl_clang_storage_class_specifiers"); 2014 Opts.support("cl_khr_gl_sharing"); 2015 Opts.support("cl_khr_icd"); 2016 2017 Opts.support("cl_khr_fp64"); 2018 Opts.support("cl_khr_byte_addressable_store"); 2019 Opts.support("cl_khr_global_int32_base_atomics"); 2020 Opts.support("cl_khr_global_int32_extended_atomics"); 2021 Opts.support("cl_khr_local_int32_base_atomics"); 2022 Opts.support("cl_khr_local_int32_extended_atomics"); 2023 } 2024 2025 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2026 // CUDA compilations support all of the host's calling conventions. 2027 // 2028 // TODO: We should warn if you apply a non-default CC to anything other than 2029 // a host function. 2030 if (HostTarget) 2031 return HostTarget->checkCallingConvention(CC); 2032 return CCCR_Warning; 2033 } 2034 }; 2035 2036 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 2037 #define BUILTIN(ID, TYPE, ATTRS) \ 2038 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2039 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2040 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2041 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2042 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2043 #include "clang/Basic/BuiltinsNVPTX.def" 2044 }; 2045 2046 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 2047 2048 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 2049 return llvm::makeArrayRef(GCCRegNames); 2050 } 2051 2052 static const LangAS::Map AMDGPUNonOpenCLPrivateIsZeroMap = { 2053 4, // Default 2054 1, // opencl_global 2055 3, // opencl_local 2056 2, // opencl_constant 2057 4, // opencl_generic 2058 1, // cuda_device 2059 2, // cuda_constant 2060 3 // cuda_shared 2061 }; 2062 static const LangAS::Map AMDGPUNonOpenCLGenericIsZeroMap = { 2063 0, // Default 2064 1, // opencl_global 2065 3, // opencl_local 2066 2, // opencl_constant 2067 0, // opencl_generic 2068 1, // cuda_device 2069 2, // cuda_constant 2070 3 // cuda_shared 2071 }; 2072 static const LangAS::Map AMDGPUOpenCLPrivateIsZeroMap = { 2073 0, // Default 2074 1, // opencl_global 2075 3, // opencl_local 2076 2, // opencl_constant 2077 4, // opencl_generic 2078 1, // cuda_device 2079 2, // cuda_constant 2080 3 // cuda_shared 2081 }; 2082 static const LangAS::Map AMDGPUOpenCLGenericIsZeroMap = { 2083 5, // Default 2084 1, // opencl_global 2085 3, // opencl_local 2086 2, // opencl_constant 2087 0, // opencl_generic 2088 1, // cuda_device 2089 2, // cuda_constant 2090 3 // cuda_shared 2091 }; 2092 2093 // If you edit the description strings, make sure you update 2094 // getPointerWidthV(). 2095 2096 static const char *const DataLayoutStringR600 = 2097 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2098 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2099 2100 static const char *const DataLayoutStringSIPrivateIsZero = 2101 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 2102 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2103 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2104 2105 static const char *const DataLayoutStringSIGenericIsZero = 2106 "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32" 2107 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2108 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"; 2109 2110 class AMDGPUTargetInfo final : public TargetInfo { 2111 static const Builtin::Info BuiltinInfo[]; 2112 static const char * const GCCRegNames[]; 2113 2114 struct AddrSpace { 2115 unsigned Generic, Global, Local, Constant, Private; 2116 AddrSpace(bool IsGenericZero_ = false){ 2117 if (IsGenericZero_) { 2118 Generic = 0; 2119 Global = 1; 2120 Local = 3; 2121 Constant = 2; 2122 Private = 5; 2123 } else { 2124 Generic = 4; 2125 Global = 1; 2126 Local = 3; 2127 Constant = 2; 2128 Private = 0; 2129 } 2130 } 2131 }; 2132 2133 /// \brief The GPU profiles supported by the AMDGPU target. 2134 enum GPUKind { 2135 GK_NONE, 2136 GK_R600, 2137 GK_R600_DOUBLE_OPS, 2138 GK_R700, 2139 GK_R700_DOUBLE_OPS, 2140 GK_EVERGREEN, 2141 GK_EVERGREEN_DOUBLE_OPS, 2142 GK_NORTHERN_ISLANDS, 2143 GK_CAYMAN, 2144 GK_GFX6, 2145 GK_GFX7, 2146 GK_GFX8, 2147 GK_GFX9 2148 } GPU; 2149 2150 bool hasFP64:1; 2151 bool hasFMAF:1; 2152 bool hasLDEXPF:1; 2153 const AddrSpace AS; 2154 2155 static bool hasFullSpeedFMAF32(StringRef GPUName) { 2156 return parseAMDGCNName(GPUName) >= GK_GFX9; 2157 } 2158 2159 static bool isAMDGCN(const llvm::Triple &TT) { 2160 return TT.getArch() == llvm::Triple::amdgcn; 2161 } 2162 2163 static bool isGenericZero(const llvm::Triple &TT) { 2164 return TT.getEnvironmentName() == "amdgiz" || 2165 TT.getEnvironmentName() == "amdgizcl"; 2166 } 2167 public: 2168 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 2169 : TargetInfo(Triple) , 2170 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600), 2171 hasFP64(false), 2172 hasFMAF(false), 2173 hasLDEXPF(false), 2174 AS(isGenericZero(Triple)){ 2175 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2176 hasFP64 = true; 2177 hasFMAF = true; 2178 hasLDEXPF = true; 2179 } 2180 auto IsGenericZero = isGenericZero(Triple); 2181 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 2182 (IsGenericZero ? DataLayoutStringSIGenericIsZero : 2183 DataLayoutStringSIPrivateIsZero) 2184 : DataLayoutStringR600); 2185 assert(DataLayout->getAllocaAddrSpace() == AS.Private); 2186 2187 UseAddrSpaceMapMangling = true; 2188 } 2189 2190 void adjust(LangOptions &Opts) override { 2191 TargetInfo::adjust(Opts); 2192 if (isGenericZero(getTriple())) { 2193 AddrSpaceMap = Opts.OpenCL ? &AMDGPUOpenCLGenericIsZeroMap 2194 : &AMDGPUNonOpenCLGenericIsZeroMap; 2195 } else { 2196 AddrSpaceMap = Opts.OpenCL ? &AMDGPUOpenCLPrivateIsZeroMap 2197 : &AMDGPUNonOpenCLPrivateIsZeroMap; 2198 } 2199 } 2200 2201 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 2202 if (GPU <= GK_CAYMAN) 2203 return 32; 2204 2205 if (AddrSpace == AS.Private || AddrSpace == AS.Local) { 2206 return 32; 2207 } 2208 return 64; 2209 } 2210 2211 uint64_t getMaxPointerWidth() const override { 2212 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2213 } 2214 2215 const char * getClobbers() const override { 2216 return ""; 2217 } 2218 2219 ArrayRef<const char *> getGCCRegNames() const override; 2220 2221 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2222 return None; 2223 } 2224 2225 bool validateAsmConstraint(const char *&Name, 2226 TargetInfo::ConstraintInfo &Info) const override { 2227 switch (*Name) { 2228 default: break; 2229 case 'v': // vgpr 2230 case 's': // sgpr 2231 Info.setAllowsRegister(); 2232 return true; 2233 } 2234 return false; 2235 } 2236 2237 bool initFeatureMap(llvm::StringMap<bool> &Features, 2238 DiagnosticsEngine &Diags, StringRef CPU, 2239 const std::vector<std::string> &FeatureVec) const override; 2240 2241 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2242 TargetOptions &TargetOpts) const override { 2243 bool hasFP32Denormals = false; 2244 bool hasFP64Denormals = false; 2245 for (auto &I : TargetOpts.FeaturesAsWritten) { 2246 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2247 hasFP32Denormals = true; 2248 if (I == "+fp64-fp16-denormals" || I == "-fp64-fp16-denormals") 2249 hasFP64Denormals = true; 2250 } 2251 if (!hasFP32Denormals) 2252 TargetOpts.Features.push_back( 2253 (Twine(hasFullSpeedFMAF32(TargetOpts.CPU) && 2254 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str()); 2255 // Always do not flush fp64 or fp16 denorms. 2256 if (!hasFP64Denormals && hasFP64) 2257 TargetOpts.Features.push_back("+fp64-fp16-denormals"); 2258 } 2259 2260 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2261 return llvm::makeArrayRef(BuiltinInfo, 2262 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2263 } 2264 2265 void getTargetDefines(const LangOptions &Opts, 2266 MacroBuilder &Builder) const override { 2267 if (getTriple().getArch() == llvm::Triple::amdgcn) 2268 Builder.defineMacro("__AMDGCN__"); 2269 else 2270 Builder.defineMacro("__R600__"); 2271 2272 if (hasFMAF) 2273 Builder.defineMacro("__HAS_FMAF__"); 2274 if (hasLDEXPF) 2275 Builder.defineMacro("__HAS_LDEXPF__"); 2276 if (hasFP64) 2277 Builder.defineMacro("__HAS_FP64__"); 2278 } 2279 2280 BuiltinVaListKind getBuiltinVaListKind() const override { 2281 return TargetInfo::CharPtrBuiltinVaList; 2282 } 2283 2284 static GPUKind parseR600Name(StringRef Name) { 2285 return llvm::StringSwitch<GPUKind>(Name) 2286 .Case("r600" , GK_R600) 2287 .Case("rv610", GK_R600) 2288 .Case("rv620", GK_R600) 2289 .Case("rv630", GK_R600) 2290 .Case("rv635", GK_R600) 2291 .Case("rs780", GK_R600) 2292 .Case("rs880", GK_R600) 2293 .Case("rv670", GK_R600_DOUBLE_OPS) 2294 .Case("rv710", GK_R700) 2295 .Case("rv730", GK_R700) 2296 .Case("rv740", GK_R700_DOUBLE_OPS) 2297 .Case("rv770", GK_R700_DOUBLE_OPS) 2298 .Case("palm", GK_EVERGREEN) 2299 .Case("cedar", GK_EVERGREEN) 2300 .Case("sumo", GK_EVERGREEN) 2301 .Case("sumo2", GK_EVERGREEN) 2302 .Case("redwood", GK_EVERGREEN) 2303 .Case("juniper", GK_EVERGREEN) 2304 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2305 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2306 .Case("barts", GK_NORTHERN_ISLANDS) 2307 .Case("turks", GK_NORTHERN_ISLANDS) 2308 .Case("caicos", GK_NORTHERN_ISLANDS) 2309 .Case("cayman", GK_CAYMAN) 2310 .Case("aruba", GK_CAYMAN) 2311 .Default(GK_NONE); 2312 } 2313 2314 static GPUKind parseAMDGCNName(StringRef Name) { 2315 return llvm::StringSwitch<GPUKind>(Name) 2316 .Case("tahiti", GK_GFX6) 2317 .Case("pitcairn", GK_GFX6) 2318 .Case("verde", GK_GFX6) 2319 .Case("oland", GK_GFX6) 2320 .Case("hainan", GK_GFX6) 2321 .Case("bonaire", GK_GFX7) 2322 .Case("kabini", GK_GFX7) 2323 .Case("kaveri", GK_GFX7) 2324 .Case("hawaii", GK_GFX7) 2325 .Case("mullins", GK_GFX7) 2326 .Case("gfx700", GK_GFX7) 2327 .Case("gfx701", GK_GFX7) 2328 .Case("gfx702", GK_GFX7) 2329 .Case("tonga", GK_GFX8) 2330 .Case("iceland", GK_GFX8) 2331 .Case("carrizo", GK_GFX8) 2332 .Case("fiji", GK_GFX8) 2333 .Case("stoney", GK_GFX8) 2334 .Case("polaris10", GK_GFX8) 2335 .Case("polaris11", GK_GFX8) 2336 .Case("gfx800", GK_GFX8) 2337 .Case("gfx801", GK_GFX8) 2338 .Case("gfx802", GK_GFX8) 2339 .Case("gfx803", GK_GFX8) 2340 .Case("gfx804", GK_GFX8) 2341 .Case("gfx810", GK_GFX8) 2342 .Case("gfx900", GK_GFX9) 2343 .Case("gfx901", GK_GFX9) 2344 .Default(GK_NONE); 2345 } 2346 2347 bool setCPU(const std::string &Name) override { 2348 if (getTriple().getArch() == llvm::Triple::amdgcn) 2349 GPU = parseAMDGCNName(Name); 2350 else 2351 GPU = parseR600Name(Name); 2352 2353 return GPU != GK_NONE; 2354 } 2355 2356 void setSupportedOpenCLOpts() override { 2357 auto &Opts = getSupportedOpenCLOpts(); 2358 Opts.support("cl_clang_storage_class_specifiers"); 2359 Opts.support("cl_khr_icd"); 2360 2361 if (hasFP64) 2362 Opts.support("cl_khr_fp64"); 2363 if (GPU >= GK_EVERGREEN) { 2364 Opts.support("cl_khr_byte_addressable_store"); 2365 Opts.support("cl_khr_global_int32_base_atomics"); 2366 Opts.support("cl_khr_global_int32_extended_atomics"); 2367 Opts.support("cl_khr_local_int32_base_atomics"); 2368 Opts.support("cl_khr_local_int32_extended_atomics"); 2369 } 2370 if (GPU >= GK_GFX6) { 2371 Opts.support("cl_khr_fp16"); 2372 Opts.support("cl_khr_int64_base_atomics"); 2373 Opts.support("cl_khr_int64_extended_atomics"); 2374 Opts.support("cl_khr_mipmap_image"); 2375 Opts.support("cl_khr_subgroups"); 2376 Opts.support("cl_khr_3d_image_writes"); 2377 Opts.support("cl_amd_media_ops"); 2378 Opts.support("cl_amd_media_ops2"); 2379 } 2380 } 2381 2382 LangAS::ID getOpenCLImageAddrSpace() const override { 2383 return LangAS::opencl_constant; 2384 } 2385 2386 /// \returns Target specific vtbl ptr address space. 2387 unsigned getVtblPtrAddressSpace() const override { 2388 // \todo: We currently have address spaces defined in AMDGPU Backend. It 2389 // would be nice if we could use it here instead of using bare numbers (same 2390 // applies to getDWARFAddressSpace). 2391 return 2; // constant. 2392 } 2393 2394 /// \returns If a target requires an address within a target specific address 2395 /// space \p AddressSpace to be converted in order to be used, then return the 2396 /// corresponding target specific DWARF address space. 2397 /// 2398 /// \returns Otherwise return None and no conversion will be emitted in the 2399 /// DWARF. 2400 Optional<unsigned> getDWARFAddressSpace( 2401 unsigned AddressSpace) const override { 2402 const unsigned DWARF_Private = 1; 2403 const unsigned DWARF_Local = 2; 2404 if (AddressSpace == AS.Private) { 2405 return DWARF_Private; 2406 } else if (AddressSpace == AS.Local) { 2407 return DWARF_Local; 2408 } else { 2409 return None; 2410 } 2411 } 2412 2413 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2414 switch (CC) { 2415 default: 2416 return CCCR_Warning; 2417 case CC_C: 2418 case CC_OpenCLKernel: 2419 return CCCR_OK; 2420 } 2421 } 2422 2423 // In amdgcn target the null pointer in global, constant, and generic 2424 // address space has value 0 but in private and local address space has 2425 // value ~0. 2426 uint64_t getNullPointerValue(unsigned AS) const override { 2427 return AS == LangAS::opencl_local ? ~0 : 0; 2428 } 2429 }; 2430 2431 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2432 #define BUILTIN(ID, TYPE, ATTRS) \ 2433 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2434 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2435 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2436 #include "clang/Basic/BuiltinsAMDGPU.def" 2437 }; 2438 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2439 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2440 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2441 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2442 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2443 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2444 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2445 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2446 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2447 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2448 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2449 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2450 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2451 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2452 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2453 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2454 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2455 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2456 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2457 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2458 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2459 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2460 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2461 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2462 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2463 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2464 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2465 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2466 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2467 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2468 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2469 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2470 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2471 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2472 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2473 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2474 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2475 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2476 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2477 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2478 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2479 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2480 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2481 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2482 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2483 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2484 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2485 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2486 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2487 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2488 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2489 }; 2490 2491 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2492 return llvm::makeArrayRef(GCCRegNames); 2493 } 2494 2495 bool AMDGPUTargetInfo::initFeatureMap( 2496 llvm::StringMap<bool> &Features, 2497 DiagnosticsEngine &Diags, StringRef CPU, 2498 const std::vector<std::string> &FeatureVec) const { 2499 2500 // XXX - What does the member GPU mean if device name string passed here? 2501 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2502 if (CPU.empty()) 2503 CPU = "tahiti"; 2504 2505 switch (parseAMDGCNName(CPU)) { 2506 case GK_GFX6: 2507 case GK_GFX7: 2508 break; 2509 2510 case GK_GFX9: 2511 Features["gfx9-insts"] = true; 2512 LLVM_FALLTHROUGH; 2513 case GK_GFX8: 2514 Features["s-memrealtime"] = true; 2515 Features["16-bit-insts"] = true; 2516 Features["dpp"] = true; 2517 break; 2518 2519 case GK_NONE: 2520 return false; 2521 default: 2522 llvm_unreachable("unhandled subtarget"); 2523 } 2524 } else { 2525 if (CPU.empty()) 2526 CPU = "r600"; 2527 2528 switch (parseR600Name(CPU)) { 2529 case GK_R600: 2530 case GK_R700: 2531 case GK_EVERGREEN: 2532 case GK_NORTHERN_ISLANDS: 2533 break; 2534 case GK_R600_DOUBLE_OPS: 2535 case GK_R700_DOUBLE_OPS: 2536 case GK_EVERGREEN_DOUBLE_OPS: 2537 case GK_CAYMAN: 2538 Features["fp64"] = true; 2539 break; 2540 case GK_NONE: 2541 return false; 2542 default: 2543 llvm_unreachable("unhandled subtarget"); 2544 } 2545 } 2546 2547 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2548 } 2549 2550 const Builtin::Info BuiltinInfoX86[] = { 2551 #define BUILTIN(ID, TYPE, ATTRS) \ 2552 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2553 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2554 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2555 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2556 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2557 #include "clang/Basic/BuiltinsX86.def" 2558 2559 #define BUILTIN(ID, TYPE, ATTRS) \ 2560 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2561 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2562 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2563 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2564 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2565 #include "clang/Basic/BuiltinsX86_64.def" 2566 }; 2567 2568 2569 static const char* const GCCRegNames[] = { 2570 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2571 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2572 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2573 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2574 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2575 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2576 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2577 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2578 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2579 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2580 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2581 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2582 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2583 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2584 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2585 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2586 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2587 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", 2588 }; 2589 2590 const TargetInfo::AddlRegName AddlRegNames[] = { 2591 { { "al", "ah", "eax", "rax" }, 0 }, 2592 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2593 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2594 { { "dl", "dh", "edx", "rdx" }, 1 }, 2595 { { "esi", "rsi" }, 4 }, 2596 { { "edi", "rdi" }, 5 }, 2597 { { "esp", "rsp" }, 7 }, 2598 { { "ebp", "rbp" }, 6 }, 2599 { { "r8d", "r8w", "r8b" }, 38 }, 2600 { { "r9d", "r9w", "r9b" }, 39 }, 2601 { { "r10d", "r10w", "r10b" }, 40 }, 2602 { { "r11d", "r11w", "r11b" }, 41 }, 2603 { { "r12d", "r12w", "r12b" }, 42 }, 2604 { { "r13d", "r13w", "r13b" }, 43 }, 2605 { { "r14d", "r14w", "r14b" }, 44 }, 2606 { { "r15d", "r15w", "r15b" }, 45 }, 2607 }; 2608 2609 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2610 // most of the implementation can be shared. 2611 class X86TargetInfo : public TargetInfo { 2612 enum X86SSEEnum { 2613 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2614 } SSELevel = NoSSE; 2615 enum MMX3DNowEnum { 2616 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2617 } MMX3DNowLevel = NoMMX3DNow; 2618 enum XOPEnum { 2619 NoXOP, 2620 SSE4A, 2621 FMA4, 2622 XOP 2623 } XOPLevel = NoXOP; 2624 2625 bool HasAES = false; 2626 bool HasPCLMUL = false; 2627 bool HasLZCNT = false; 2628 bool HasRDRND = false; 2629 bool HasFSGSBASE = false; 2630 bool HasBMI = false; 2631 bool HasBMI2 = false; 2632 bool HasPOPCNT = false; 2633 bool HasRTM = false; 2634 bool HasPRFCHW = false; 2635 bool HasRDSEED = false; 2636 bool HasADX = false; 2637 bool HasTBM = false; 2638 bool HasLWP = false; 2639 bool HasFMA = false; 2640 bool HasF16C = false; 2641 bool HasAVX512CD = false; 2642 bool HasAVX512VPOPCNTDQ = false; 2643 bool HasAVX512ER = false; 2644 bool HasAVX512PF = false; 2645 bool HasAVX512DQ = false; 2646 bool HasAVX512BW = false; 2647 bool HasAVX512VL = false; 2648 bool HasAVX512VBMI = false; 2649 bool HasAVX512IFMA = false; 2650 bool HasSHA = false; 2651 bool HasMPX = false; 2652 bool HasSGX = false; 2653 bool HasCX16 = false; 2654 bool HasFXSR = false; 2655 bool HasXSAVE = false; 2656 bool HasXSAVEOPT = false; 2657 bool HasXSAVEC = false; 2658 bool HasXSAVES = false; 2659 bool HasMWAITX = false; 2660 bool HasCLZERO = false; 2661 bool HasPKU = false; 2662 bool HasCLFLUSHOPT = false; 2663 bool HasCLWB = false; 2664 bool HasMOVBE = false; 2665 bool HasPREFETCHWT1 = false; 2666 2667 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2668 /// 2669 /// Each enumeration represents a particular CPU supported by Clang. These 2670 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2671 enum CPUKind { 2672 CK_Generic, 2673 2674 /// \name i386 2675 /// i386-generation processors. 2676 //@{ 2677 CK_i386, 2678 //@} 2679 2680 /// \name i486 2681 /// i486-generation processors. 2682 //@{ 2683 CK_i486, 2684 CK_WinChipC6, 2685 CK_WinChip2, 2686 CK_C3, 2687 //@} 2688 2689 /// \name i586 2690 /// i586-generation processors, P5 microarchitecture based. 2691 //@{ 2692 CK_i586, 2693 CK_Pentium, 2694 CK_PentiumMMX, 2695 //@} 2696 2697 /// \name i686 2698 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2699 //@{ 2700 CK_i686, 2701 CK_PentiumPro, 2702 CK_Pentium2, 2703 CK_Pentium3, 2704 CK_Pentium3M, 2705 CK_PentiumM, 2706 CK_C3_2, 2707 2708 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2709 /// Clang however has some logic to suport this. 2710 // FIXME: Warn, deprecate, and potentially remove this. 2711 CK_Yonah, 2712 //@} 2713 2714 /// \name Netburst 2715 /// Netburst microarchitecture based processors. 2716 //@{ 2717 CK_Pentium4, 2718 CK_Pentium4M, 2719 CK_Prescott, 2720 CK_Nocona, 2721 //@} 2722 2723 /// \name Core 2724 /// Core microarchitecture based processors. 2725 //@{ 2726 CK_Core2, 2727 2728 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2729 /// codename which GCC no longer accepts as an option to -march, but Clang 2730 /// has some logic for recognizing it. 2731 // FIXME: Warn, deprecate, and potentially remove this. 2732 CK_Penryn, 2733 //@} 2734 2735 /// \name Atom 2736 /// Atom processors 2737 //@{ 2738 CK_Bonnell, 2739 CK_Silvermont, 2740 CK_Goldmont, 2741 //@} 2742 2743 /// \name Nehalem 2744 /// Nehalem microarchitecture based processors. 2745 CK_Nehalem, 2746 2747 /// \name Westmere 2748 /// Westmere microarchitecture based processors. 2749 CK_Westmere, 2750 2751 /// \name Sandy Bridge 2752 /// Sandy Bridge microarchitecture based processors. 2753 CK_SandyBridge, 2754 2755 /// \name Ivy Bridge 2756 /// Ivy Bridge microarchitecture based processors. 2757 CK_IvyBridge, 2758 2759 /// \name Haswell 2760 /// Haswell microarchitecture based processors. 2761 CK_Haswell, 2762 2763 /// \name Broadwell 2764 /// Broadwell microarchitecture based processors. 2765 CK_Broadwell, 2766 2767 /// \name Skylake Client 2768 /// Skylake client microarchitecture based processors. 2769 CK_SkylakeClient, 2770 2771 /// \name Skylake Server 2772 /// Skylake server microarchitecture based processors. 2773 CK_SkylakeServer, 2774 2775 /// \name Cannonlake Client 2776 /// Cannonlake client microarchitecture based processors. 2777 CK_Cannonlake, 2778 2779 /// \name Knights Landing 2780 /// Knights Landing processor. 2781 CK_KNL, 2782 2783 /// \name Lakemont 2784 /// Lakemont microarchitecture based processors. 2785 CK_Lakemont, 2786 2787 /// \name K6 2788 /// K6 architecture processors. 2789 //@{ 2790 CK_K6, 2791 CK_K6_2, 2792 CK_K6_3, 2793 //@} 2794 2795 /// \name K7 2796 /// K7 architecture processors. 2797 //@{ 2798 CK_Athlon, 2799 CK_AthlonThunderbird, 2800 CK_Athlon4, 2801 CK_AthlonXP, 2802 CK_AthlonMP, 2803 //@} 2804 2805 /// \name K8 2806 /// K8 architecture processors. 2807 //@{ 2808 CK_Athlon64, 2809 CK_Athlon64SSE3, 2810 CK_AthlonFX, 2811 CK_K8, 2812 CK_K8SSE3, 2813 CK_Opteron, 2814 CK_OpteronSSE3, 2815 CK_AMDFAM10, 2816 //@} 2817 2818 /// \name Bobcat 2819 /// Bobcat architecture processors. 2820 //@{ 2821 CK_BTVER1, 2822 CK_BTVER2, 2823 //@} 2824 2825 /// \name Bulldozer 2826 /// Bulldozer architecture processors. 2827 //@{ 2828 CK_BDVER1, 2829 CK_BDVER2, 2830 CK_BDVER3, 2831 CK_BDVER4, 2832 //@} 2833 2834 /// \name zen 2835 /// Zen architecture processors. 2836 //@{ 2837 CK_ZNVER1, 2838 //@} 2839 2840 /// This specification is deprecated and will be removed in the future. 2841 /// Users should prefer \see CK_K8. 2842 // FIXME: Warn on this when the CPU is set to it. 2843 //@{ 2844 CK_x86_64, 2845 //@} 2846 2847 /// \name Geode 2848 /// Geode processors. 2849 //@{ 2850 CK_Geode 2851 //@} 2852 } CPU = CK_Generic; 2853 2854 CPUKind getCPUKind(StringRef CPU) const { 2855 return llvm::StringSwitch<CPUKind>(CPU) 2856 .Case("i386", CK_i386) 2857 .Case("i486", CK_i486) 2858 .Case("winchip-c6", CK_WinChipC6) 2859 .Case("winchip2", CK_WinChip2) 2860 .Case("c3", CK_C3) 2861 .Case("i586", CK_i586) 2862 .Case("pentium", CK_Pentium) 2863 .Case("pentium-mmx", CK_PentiumMMX) 2864 .Case("i686", CK_i686) 2865 .Case("pentiumpro", CK_PentiumPro) 2866 .Case("pentium2", CK_Pentium2) 2867 .Case("pentium3", CK_Pentium3) 2868 .Case("pentium3m", CK_Pentium3M) 2869 .Case("pentium-m", CK_PentiumM) 2870 .Case("c3-2", CK_C3_2) 2871 .Case("yonah", CK_Yonah) 2872 .Case("pentium4", CK_Pentium4) 2873 .Case("pentium4m", CK_Pentium4M) 2874 .Case("prescott", CK_Prescott) 2875 .Case("nocona", CK_Nocona) 2876 .Case("core2", CK_Core2) 2877 .Case("penryn", CK_Penryn) 2878 .Case("bonnell", CK_Bonnell) 2879 .Case("atom", CK_Bonnell) // Legacy name. 2880 .Case("silvermont", CK_Silvermont) 2881 .Case("slm", CK_Silvermont) // Legacy name. 2882 .Case("goldmont", CK_Goldmont) 2883 .Case("nehalem", CK_Nehalem) 2884 .Case("corei7", CK_Nehalem) // Legacy name. 2885 .Case("westmere", CK_Westmere) 2886 .Case("sandybridge", CK_SandyBridge) 2887 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2888 .Case("ivybridge", CK_IvyBridge) 2889 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2890 .Case("haswell", CK_Haswell) 2891 .Case("core-avx2", CK_Haswell) // Legacy name. 2892 .Case("broadwell", CK_Broadwell) 2893 .Case("skylake", CK_SkylakeClient) 2894 .Case("skylake-avx512", CK_SkylakeServer) 2895 .Case("skx", CK_SkylakeServer) // Legacy name. 2896 .Case("cannonlake", CK_Cannonlake) 2897 .Case("knl", CK_KNL) 2898 .Case("lakemont", CK_Lakemont) 2899 .Case("k6", CK_K6) 2900 .Case("k6-2", CK_K6_2) 2901 .Case("k6-3", CK_K6_3) 2902 .Case("athlon", CK_Athlon) 2903 .Case("athlon-tbird", CK_AthlonThunderbird) 2904 .Case("athlon-4", CK_Athlon4) 2905 .Case("athlon-xp", CK_AthlonXP) 2906 .Case("athlon-mp", CK_AthlonMP) 2907 .Case("athlon64", CK_Athlon64) 2908 .Case("athlon64-sse3", CK_Athlon64SSE3) 2909 .Case("athlon-fx", CK_AthlonFX) 2910 .Case("k8", CK_K8) 2911 .Case("k8-sse3", CK_K8SSE3) 2912 .Case("opteron", CK_Opteron) 2913 .Case("opteron-sse3", CK_OpteronSSE3) 2914 .Case("barcelona", CK_AMDFAM10) 2915 .Case("amdfam10", CK_AMDFAM10) 2916 .Case("btver1", CK_BTVER1) 2917 .Case("btver2", CK_BTVER2) 2918 .Case("bdver1", CK_BDVER1) 2919 .Case("bdver2", CK_BDVER2) 2920 .Case("bdver3", CK_BDVER3) 2921 .Case("bdver4", CK_BDVER4) 2922 .Case("znver1", CK_ZNVER1) 2923 .Case("x86-64", CK_x86_64) 2924 .Case("geode", CK_Geode) 2925 .Default(CK_Generic); 2926 } 2927 2928 enum FPMathKind { 2929 FP_Default, 2930 FP_SSE, 2931 FP_387 2932 } FPMath = FP_Default; 2933 2934 public: 2935 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2936 : TargetInfo(Triple) { 2937 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 2938 } 2939 unsigned getFloatEvalMethod() const override { 2940 // X87 evaluates with 80 bits "long double" precision. 2941 return SSELevel == NoSSE ? 2 : 0; 2942 } 2943 ArrayRef<const char *> getGCCRegNames() const override { 2944 return llvm::makeArrayRef(GCCRegNames); 2945 } 2946 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2947 return None; 2948 } 2949 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2950 return llvm::makeArrayRef(AddlRegNames); 2951 } 2952 bool validateCpuSupports(StringRef Name) const override; 2953 bool validateAsmConstraint(const char *&Name, 2954 TargetInfo::ConstraintInfo &info) const override; 2955 2956 bool validateGlobalRegisterVariable(StringRef RegName, 2957 unsigned RegSize, 2958 bool &HasSizeMismatch) const override { 2959 // esp and ebp are the only 32-bit registers the x86 backend can currently 2960 // handle. 2961 if (RegName.equals("esp") || RegName.equals("ebp")) { 2962 // Check that the register size is 32-bit. 2963 HasSizeMismatch = RegSize != 32; 2964 return true; 2965 } 2966 2967 return false; 2968 } 2969 2970 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2971 2972 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2973 2974 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2975 2976 std::string convertConstraint(const char *&Constraint) const override; 2977 const char *getClobbers() const override { 2978 return "~{dirflag},~{fpsr},~{flags}"; 2979 } 2980 2981 StringRef getConstraintRegister(const StringRef &Constraint, 2982 const StringRef &Expression) const override { 2983 StringRef::iterator I, E; 2984 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) { 2985 if (isalpha(*I)) 2986 break; 2987 } 2988 if (I == E) 2989 return ""; 2990 switch (*I) { 2991 // For the register constraints, return the matching register name 2992 case 'a': 2993 return "ax"; 2994 case 'b': 2995 return "bx"; 2996 case 'c': 2997 return "cx"; 2998 case 'd': 2999 return "dx"; 3000 case 'S': 3001 return "si"; 3002 case 'D': 3003 return "di"; 3004 // In case the constraint is 'r' we need to return Expression 3005 case 'r': 3006 return Expression; 3007 default: 3008 // Default value if there is no constraint for the register 3009 return ""; 3010 } 3011 return ""; 3012 } 3013 3014 void getTargetDefines(const LangOptions &Opts, 3015 MacroBuilder &Builder) const override; 3016 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 3017 bool Enabled); 3018 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 3019 bool Enabled); 3020 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3021 bool Enabled); 3022 void setFeatureEnabled(llvm::StringMap<bool> &Features, 3023 StringRef Name, bool Enabled) const override { 3024 setFeatureEnabledImpl(Features, Name, Enabled); 3025 } 3026 // This exists purely to cut down on the number of virtual calls in 3027 // initFeatureMap which calls this repeatedly. 3028 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3029 StringRef Name, bool Enabled); 3030 bool 3031 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 3032 StringRef CPU, 3033 const std::vector<std::string> &FeaturesVec) const override; 3034 bool hasFeature(StringRef Feature) const override; 3035 bool handleTargetFeatures(std::vector<std::string> &Features, 3036 DiagnosticsEngine &Diags) override; 3037 StringRef getABI() const override { 3038 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 3039 return "avx512"; 3040 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 3041 return "avx"; 3042 if (getTriple().getArch() == llvm::Triple::x86 && 3043 MMX3DNowLevel == NoMMX3DNow) 3044 return "no-mmx"; 3045 return ""; 3046 } 3047 bool setCPU(const std::string &Name) override { 3048 CPU = getCPUKind(Name); 3049 3050 // Perform any per-CPU checks necessary to determine if this CPU is 3051 // acceptable. 3052 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 3053 // invalid without explaining *why*. 3054 switch (CPU) { 3055 case CK_Generic: 3056 // No processor selected! 3057 return false; 3058 3059 case CK_i386: 3060 case CK_i486: 3061 case CK_WinChipC6: 3062 case CK_WinChip2: 3063 case CK_C3: 3064 case CK_i586: 3065 case CK_Pentium: 3066 case CK_PentiumMMX: 3067 case CK_i686: 3068 case CK_PentiumPro: 3069 case CK_Pentium2: 3070 case CK_Pentium3: 3071 case CK_Pentium3M: 3072 case CK_PentiumM: 3073 case CK_Yonah: 3074 case CK_C3_2: 3075 case CK_Pentium4: 3076 case CK_Pentium4M: 3077 case CK_Lakemont: 3078 case CK_Prescott: 3079 case CK_K6: 3080 case CK_K6_2: 3081 case CK_K6_3: 3082 case CK_Athlon: 3083 case CK_AthlonThunderbird: 3084 case CK_Athlon4: 3085 case CK_AthlonXP: 3086 case CK_AthlonMP: 3087 case CK_Geode: 3088 // Only accept certain architectures when compiling in 32-bit mode. 3089 if (getTriple().getArch() != llvm::Triple::x86) 3090 return false; 3091 3092 // Fallthrough 3093 case CK_Nocona: 3094 case CK_Core2: 3095 case CK_Penryn: 3096 case CK_Bonnell: 3097 case CK_Silvermont: 3098 case CK_Goldmont: 3099 case CK_Nehalem: 3100 case CK_Westmere: 3101 case CK_SandyBridge: 3102 case CK_IvyBridge: 3103 case CK_Haswell: 3104 case CK_Broadwell: 3105 case CK_SkylakeClient: 3106 case CK_SkylakeServer: 3107 case CK_Cannonlake: 3108 case CK_KNL: 3109 case CK_Athlon64: 3110 case CK_Athlon64SSE3: 3111 case CK_AthlonFX: 3112 case CK_K8: 3113 case CK_K8SSE3: 3114 case CK_Opteron: 3115 case CK_OpteronSSE3: 3116 case CK_AMDFAM10: 3117 case CK_BTVER1: 3118 case CK_BTVER2: 3119 case CK_BDVER1: 3120 case CK_BDVER2: 3121 case CK_BDVER3: 3122 case CK_BDVER4: 3123 case CK_ZNVER1: 3124 case CK_x86_64: 3125 return true; 3126 } 3127 llvm_unreachable("Unhandled CPU kind"); 3128 } 3129 3130 bool setFPMath(StringRef Name) override; 3131 3132 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3133 // Most of the non-ARM calling conventions are i386 conventions. 3134 switch (CC) { 3135 case CC_X86ThisCall: 3136 case CC_X86FastCall: 3137 case CC_X86StdCall: 3138 case CC_X86VectorCall: 3139 case CC_X86RegCall: 3140 case CC_C: 3141 case CC_Swift: 3142 case CC_X86Pascal: 3143 case CC_IntelOclBicc: 3144 case CC_OpenCLKernel: 3145 return CCCR_OK; 3146 default: 3147 return CCCR_Warning; 3148 } 3149 } 3150 3151 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3152 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 3153 } 3154 3155 bool hasSjLjLowering() const override { 3156 return true; 3157 } 3158 3159 void setSupportedOpenCLOpts() override { 3160 getSupportedOpenCLOpts().supportAll(); 3161 } 3162 }; 3163 3164 bool X86TargetInfo::setFPMath(StringRef Name) { 3165 if (Name == "387") { 3166 FPMath = FP_387; 3167 return true; 3168 } 3169 if (Name == "sse") { 3170 FPMath = FP_SSE; 3171 return true; 3172 } 3173 return false; 3174 } 3175 3176 bool X86TargetInfo::initFeatureMap( 3177 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 3178 const std::vector<std::string> &FeaturesVec) const { 3179 // FIXME: This *really* should not be here. 3180 // X86_64 always has SSE2. 3181 if (getTriple().getArch() == llvm::Triple::x86_64) 3182 setFeatureEnabledImpl(Features, "sse2", true); 3183 3184 const CPUKind Kind = getCPUKind(CPU); 3185 3186 // Enable X87 for all X86 processors but Lakemont. 3187 if (Kind != CK_Lakemont) 3188 setFeatureEnabledImpl(Features, "x87", true); 3189 3190 switch (Kind) { 3191 case CK_Generic: 3192 case CK_i386: 3193 case CK_i486: 3194 case CK_i586: 3195 case CK_Pentium: 3196 case CK_i686: 3197 case CK_PentiumPro: 3198 case CK_Lakemont: 3199 break; 3200 case CK_PentiumMMX: 3201 case CK_Pentium2: 3202 case CK_K6: 3203 case CK_WinChipC6: 3204 setFeatureEnabledImpl(Features, "mmx", true); 3205 break; 3206 case CK_Pentium3: 3207 case CK_Pentium3M: 3208 case CK_C3_2: 3209 setFeatureEnabledImpl(Features, "sse", true); 3210 setFeatureEnabledImpl(Features, "fxsr", true); 3211 break; 3212 case CK_PentiumM: 3213 case CK_Pentium4: 3214 case CK_Pentium4M: 3215 case CK_x86_64: 3216 setFeatureEnabledImpl(Features, "sse2", true); 3217 setFeatureEnabledImpl(Features, "fxsr", true); 3218 break; 3219 case CK_Yonah: 3220 case CK_Prescott: 3221 case CK_Nocona: 3222 setFeatureEnabledImpl(Features, "sse3", true); 3223 setFeatureEnabledImpl(Features, "fxsr", true); 3224 setFeatureEnabledImpl(Features, "cx16", true); 3225 break; 3226 case CK_Core2: 3227 setFeatureEnabledImpl(Features, "ssse3", true); 3228 setFeatureEnabledImpl(Features, "fxsr", true); 3229 setFeatureEnabledImpl(Features, "cx16", true); 3230 break; 3231 case CK_Penryn: 3232 setFeatureEnabledImpl(Features, "sse4.1", true); 3233 setFeatureEnabledImpl(Features, "fxsr", true); 3234 setFeatureEnabledImpl(Features, "cx16", true); 3235 break; 3236 case CK_Cannonlake: 3237 setFeatureEnabledImpl(Features, "avx512ifma", true); 3238 setFeatureEnabledImpl(Features, "avx512vbmi", true); 3239 setFeatureEnabledImpl(Features, "sha", true); 3240 LLVM_FALLTHROUGH; 3241 case CK_SkylakeServer: 3242 setFeatureEnabledImpl(Features, "avx512f", true); 3243 setFeatureEnabledImpl(Features, "avx512cd", true); 3244 setFeatureEnabledImpl(Features, "avx512dq", true); 3245 setFeatureEnabledImpl(Features, "avx512bw", true); 3246 setFeatureEnabledImpl(Features, "avx512vl", true); 3247 setFeatureEnabledImpl(Features, "pku", true); 3248 setFeatureEnabledImpl(Features, "clwb", true); 3249 LLVM_FALLTHROUGH; 3250 case CK_SkylakeClient: 3251 setFeatureEnabledImpl(Features, "xsavec", true); 3252 setFeatureEnabledImpl(Features, "xsaves", true); 3253 setFeatureEnabledImpl(Features, "mpx", true); 3254 setFeatureEnabledImpl(Features, "sgx", true); 3255 setFeatureEnabledImpl(Features, "clflushopt", true); 3256 setFeatureEnabledImpl(Features, "rtm", true); 3257 LLVM_FALLTHROUGH; 3258 case CK_Broadwell: 3259 setFeatureEnabledImpl(Features, "rdseed", true); 3260 setFeatureEnabledImpl(Features, "adx", true); 3261 LLVM_FALLTHROUGH; 3262 case CK_Haswell: 3263 setFeatureEnabledImpl(Features, "avx2", true); 3264 setFeatureEnabledImpl(Features, "lzcnt", true); 3265 setFeatureEnabledImpl(Features, "bmi", true); 3266 setFeatureEnabledImpl(Features, "bmi2", true); 3267 setFeatureEnabledImpl(Features, "fma", true); 3268 setFeatureEnabledImpl(Features, "movbe", true); 3269 LLVM_FALLTHROUGH; 3270 case CK_IvyBridge: 3271 setFeatureEnabledImpl(Features, "rdrnd", true); 3272 setFeatureEnabledImpl(Features, "f16c", true); 3273 setFeatureEnabledImpl(Features, "fsgsbase", true); 3274 LLVM_FALLTHROUGH; 3275 case CK_SandyBridge: 3276 setFeatureEnabledImpl(Features, "avx", true); 3277 setFeatureEnabledImpl(Features, "xsave", true); 3278 setFeatureEnabledImpl(Features, "xsaveopt", true); 3279 LLVM_FALLTHROUGH; 3280 case CK_Westmere: 3281 setFeatureEnabledImpl(Features, "aes", true); 3282 setFeatureEnabledImpl(Features, "pclmul", true); 3283 LLVM_FALLTHROUGH; 3284 case CK_Nehalem: 3285 setFeatureEnabledImpl(Features, "sse4.2", true); 3286 setFeatureEnabledImpl(Features, "fxsr", true); 3287 setFeatureEnabledImpl(Features, "cx16", true); 3288 break; 3289 case CK_Goldmont: 3290 setFeatureEnabledImpl(Features, "sha", true); 3291 setFeatureEnabledImpl(Features, "rdrnd", true); 3292 setFeatureEnabledImpl(Features, "rdseed", true); 3293 setFeatureEnabledImpl(Features, "xsave", true); 3294 setFeatureEnabledImpl(Features, "xsaveopt", true); 3295 setFeatureEnabledImpl(Features, "xsavec", true); 3296 setFeatureEnabledImpl(Features, "xsaves", true); 3297 setFeatureEnabledImpl(Features, "clflushopt", true); 3298 setFeatureEnabledImpl(Features, "mpx", true); 3299 LLVM_FALLTHROUGH; 3300 case CK_Silvermont: 3301 setFeatureEnabledImpl(Features, "aes", true); 3302 setFeatureEnabledImpl(Features, "pclmul", true); 3303 setFeatureEnabledImpl(Features, "sse4.2", true); 3304 LLVM_FALLTHROUGH; 3305 case CK_Bonnell: 3306 setFeatureEnabledImpl(Features, "movbe", true); 3307 setFeatureEnabledImpl(Features, "ssse3", true); 3308 setFeatureEnabledImpl(Features, "fxsr", true); 3309 setFeatureEnabledImpl(Features, "cx16", true); 3310 break; 3311 case CK_KNL: 3312 setFeatureEnabledImpl(Features, "avx512f", true); 3313 setFeatureEnabledImpl(Features, "avx512cd", true); 3314 setFeatureEnabledImpl(Features, "avx512er", true); 3315 setFeatureEnabledImpl(Features, "avx512pf", true); 3316 setFeatureEnabledImpl(Features, "prefetchwt1", true); 3317 setFeatureEnabledImpl(Features, "fxsr", true); 3318 setFeatureEnabledImpl(Features, "rdseed", true); 3319 setFeatureEnabledImpl(Features, "adx", true); 3320 setFeatureEnabledImpl(Features, "lzcnt", true); 3321 setFeatureEnabledImpl(Features, "bmi", true); 3322 setFeatureEnabledImpl(Features, "bmi2", true); 3323 setFeatureEnabledImpl(Features, "rtm", true); 3324 setFeatureEnabledImpl(Features, "fma", true); 3325 setFeatureEnabledImpl(Features, "rdrnd", true); 3326 setFeatureEnabledImpl(Features, "f16c", true); 3327 setFeatureEnabledImpl(Features, "fsgsbase", true); 3328 setFeatureEnabledImpl(Features, "aes", true); 3329 setFeatureEnabledImpl(Features, "pclmul", true); 3330 setFeatureEnabledImpl(Features, "cx16", true); 3331 setFeatureEnabledImpl(Features, "xsaveopt", true); 3332 setFeatureEnabledImpl(Features, "xsave", true); 3333 setFeatureEnabledImpl(Features, "movbe", true); 3334 break; 3335 case CK_K6_2: 3336 case CK_K6_3: 3337 case CK_WinChip2: 3338 case CK_C3: 3339 setFeatureEnabledImpl(Features, "3dnow", true); 3340 break; 3341 case CK_Athlon: 3342 case CK_AthlonThunderbird: 3343 case CK_Geode: 3344 setFeatureEnabledImpl(Features, "3dnowa", true); 3345 break; 3346 case CK_Athlon4: 3347 case CK_AthlonXP: 3348 case CK_AthlonMP: 3349 setFeatureEnabledImpl(Features, "sse", true); 3350 setFeatureEnabledImpl(Features, "3dnowa", true); 3351 setFeatureEnabledImpl(Features, "fxsr", true); 3352 break; 3353 case CK_K8: 3354 case CK_Opteron: 3355 case CK_Athlon64: 3356 case CK_AthlonFX: 3357 setFeatureEnabledImpl(Features, "sse2", true); 3358 setFeatureEnabledImpl(Features, "3dnowa", true); 3359 setFeatureEnabledImpl(Features, "fxsr", true); 3360 break; 3361 case CK_AMDFAM10: 3362 setFeatureEnabledImpl(Features, "sse4a", true); 3363 setFeatureEnabledImpl(Features, "lzcnt", true); 3364 setFeatureEnabledImpl(Features, "popcnt", true); 3365 LLVM_FALLTHROUGH; 3366 case CK_K8SSE3: 3367 case CK_OpteronSSE3: 3368 case CK_Athlon64SSE3: 3369 setFeatureEnabledImpl(Features, "sse3", true); 3370 setFeatureEnabledImpl(Features, "3dnowa", true); 3371 setFeatureEnabledImpl(Features, "fxsr", true); 3372 break; 3373 case CK_BTVER2: 3374 setFeatureEnabledImpl(Features, "avx", true); 3375 setFeatureEnabledImpl(Features, "aes", true); 3376 setFeatureEnabledImpl(Features, "pclmul", true); 3377 setFeatureEnabledImpl(Features, "bmi", true); 3378 setFeatureEnabledImpl(Features, "f16c", true); 3379 setFeatureEnabledImpl(Features, "xsaveopt", true); 3380 LLVM_FALLTHROUGH; 3381 case CK_BTVER1: 3382 setFeatureEnabledImpl(Features, "ssse3", true); 3383 setFeatureEnabledImpl(Features, "sse4a", true); 3384 setFeatureEnabledImpl(Features, "lzcnt", true); 3385 setFeatureEnabledImpl(Features, "popcnt", true); 3386 setFeatureEnabledImpl(Features, "prfchw", true); 3387 setFeatureEnabledImpl(Features, "cx16", true); 3388 setFeatureEnabledImpl(Features, "fxsr", true); 3389 break; 3390 case CK_ZNVER1: 3391 setFeatureEnabledImpl(Features, "adx", true); 3392 setFeatureEnabledImpl(Features, "aes", true); 3393 setFeatureEnabledImpl(Features, "avx2", true); 3394 setFeatureEnabledImpl(Features, "bmi", true); 3395 setFeatureEnabledImpl(Features, "bmi2", true); 3396 setFeatureEnabledImpl(Features, "clflushopt", true); 3397 setFeatureEnabledImpl(Features, "clzero", true); 3398 setFeatureEnabledImpl(Features, "cx16", true); 3399 setFeatureEnabledImpl(Features, "f16c", true); 3400 setFeatureEnabledImpl(Features, "fma", true); 3401 setFeatureEnabledImpl(Features, "fsgsbase", true); 3402 setFeatureEnabledImpl(Features, "fxsr", true); 3403 setFeatureEnabledImpl(Features, "lzcnt", true); 3404 setFeatureEnabledImpl(Features, "mwaitx", true); 3405 setFeatureEnabledImpl(Features, "movbe", true); 3406 setFeatureEnabledImpl(Features, "pclmul", true); 3407 setFeatureEnabledImpl(Features, "popcnt", true); 3408 setFeatureEnabledImpl(Features, "prfchw", true); 3409 setFeatureEnabledImpl(Features, "rdrnd", true); 3410 setFeatureEnabledImpl(Features, "rdseed", true); 3411 setFeatureEnabledImpl(Features, "sha", true); 3412 setFeatureEnabledImpl(Features, "sse4a", true); 3413 setFeatureEnabledImpl(Features, "xsave", true); 3414 setFeatureEnabledImpl(Features, "xsavec", true); 3415 setFeatureEnabledImpl(Features, "xsaveopt", true); 3416 setFeatureEnabledImpl(Features, "xsaves", true); 3417 break; 3418 case CK_BDVER4: 3419 setFeatureEnabledImpl(Features, "avx2", true); 3420 setFeatureEnabledImpl(Features, "bmi2", true); 3421 setFeatureEnabledImpl(Features, "mwaitx", true); 3422 LLVM_FALLTHROUGH; 3423 case CK_BDVER3: 3424 setFeatureEnabledImpl(Features, "fsgsbase", true); 3425 setFeatureEnabledImpl(Features, "xsaveopt", true); 3426 LLVM_FALLTHROUGH; 3427 case CK_BDVER2: 3428 setFeatureEnabledImpl(Features, "bmi", true); 3429 setFeatureEnabledImpl(Features, "fma", true); 3430 setFeatureEnabledImpl(Features, "f16c", true); 3431 setFeatureEnabledImpl(Features, "tbm", true); 3432 LLVM_FALLTHROUGH; 3433 case CK_BDVER1: 3434 // xop implies avx, sse4a and fma4. 3435 setFeatureEnabledImpl(Features, "xop", true); 3436 setFeatureEnabledImpl(Features, "lwp", true); 3437 setFeatureEnabledImpl(Features, "lzcnt", true); 3438 setFeatureEnabledImpl(Features, "aes", true); 3439 setFeatureEnabledImpl(Features, "pclmul", true); 3440 setFeatureEnabledImpl(Features, "prfchw", true); 3441 setFeatureEnabledImpl(Features, "cx16", true); 3442 setFeatureEnabledImpl(Features, "fxsr", true); 3443 setFeatureEnabledImpl(Features, "xsave", true); 3444 break; 3445 } 3446 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3447 return false; 3448 3449 // Can't do this earlier because we need to be able to explicitly enable 3450 // or disable these features and the things that they depend upon. 3451 3452 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3453 auto I = Features.find("sse4.2"); 3454 if (I != Features.end() && I->getValue() && 3455 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3456 FeaturesVec.end()) 3457 Features["popcnt"] = true; 3458 3459 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3460 I = Features.find("3dnow"); 3461 if (I != Features.end() && I->getValue() && 3462 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3463 FeaturesVec.end()) 3464 Features["prfchw"] = true; 3465 3466 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3467 // then enable MMX. 3468 I = Features.find("sse"); 3469 if (I != Features.end() && I->getValue() && 3470 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3471 FeaturesVec.end()) 3472 Features["mmx"] = true; 3473 3474 return true; 3475 } 3476 3477 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3478 X86SSEEnum Level, bool Enabled) { 3479 if (Enabled) { 3480 switch (Level) { 3481 case AVX512F: 3482 Features["avx512f"] = true; 3483 LLVM_FALLTHROUGH; 3484 case AVX2: 3485 Features["avx2"] = true; 3486 LLVM_FALLTHROUGH; 3487 case AVX: 3488 Features["avx"] = true; 3489 Features["xsave"] = true; 3490 LLVM_FALLTHROUGH; 3491 case SSE42: 3492 Features["sse4.2"] = true; 3493 LLVM_FALLTHROUGH; 3494 case SSE41: 3495 Features["sse4.1"] = true; 3496 LLVM_FALLTHROUGH; 3497 case SSSE3: 3498 Features["ssse3"] = true; 3499 LLVM_FALLTHROUGH; 3500 case SSE3: 3501 Features["sse3"] = true; 3502 LLVM_FALLTHROUGH; 3503 case SSE2: 3504 Features["sse2"] = true; 3505 LLVM_FALLTHROUGH; 3506 case SSE1: 3507 Features["sse"] = true; 3508 LLVM_FALLTHROUGH; 3509 case NoSSE: 3510 break; 3511 } 3512 return; 3513 } 3514 3515 switch (Level) { 3516 case NoSSE: 3517 case SSE1: 3518 Features["sse"] = false; 3519 LLVM_FALLTHROUGH; 3520 case SSE2: 3521 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3522 Features["sha"] = false; 3523 LLVM_FALLTHROUGH; 3524 case SSE3: 3525 Features["sse3"] = false; 3526 setXOPLevel(Features, NoXOP, false); 3527 LLVM_FALLTHROUGH; 3528 case SSSE3: 3529 Features["ssse3"] = false; 3530 LLVM_FALLTHROUGH; 3531 case SSE41: 3532 Features["sse4.1"] = false; 3533 LLVM_FALLTHROUGH; 3534 case SSE42: 3535 Features["sse4.2"] = false; 3536 LLVM_FALLTHROUGH; 3537 case AVX: 3538 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3539 Features["xsaveopt"] = false; 3540 setXOPLevel(Features, FMA4, false); 3541 LLVM_FALLTHROUGH; 3542 case AVX2: 3543 Features["avx2"] = false; 3544 LLVM_FALLTHROUGH; 3545 case AVX512F: 3546 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3547 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3548 Features["avx512vl"] = Features["avx512vbmi"] = 3549 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false; 3550 break; 3551 } 3552 } 3553 3554 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3555 MMX3DNowEnum Level, bool Enabled) { 3556 if (Enabled) { 3557 switch (Level) { 3558 case AMD3DNowAthlon: 3559 Features["3dnowa"] = true; 3560 LLVM_FALLTHROUGH; 3561 case AMD3DNow: 3562 Features["3dnow"] = true; 3563 LLVM_FALLTHROUGH; 3564 case MMX: 3565 Features["mmx"] = true; 3566 LLVM_FALLTHROUGH; 3567 case NoMMX3DNow: 3568 break; 3569 } 3570 return; 3571 } 3572 3573 switch (Level) { 3574 case NoMMX3DNow: 3575 case MMX: 3576 Features["mmx"] = false; 3577 LLVM_FALLTHROUGH; 3578 case AMD3DNow: 3579 Features["3dnow"] = false; 3580 LLVM_FALLTHROUGH; 3581 case AMD3DNowAthlon: 3582 Features["3dnowa"] = false; 3583 break; 3584 } 3585 } 3586 3587 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3588 bool Enabled) { 3589 if (Enabled) { 3590 switch (Level) { 3591 case XOP: 3592 Features["xop"] = true; 3593 LLVM_FALLTHROUGH; 3594 case FMA4: 3595 Features["fma4"] = true; 3596 setSSELevel(Features, AVX, true); 3597 LLVM_FALLTHROUGH; 3598 case SSE4A: 3599 Features["sse4a"] = true; 3600 setSSELevel(Features, SSE3, true); 3601 LLVM_FALLTHROUGH; 3602 case NoXOP: 3603 break; 3604 } 3605 return; 3606 } 3607 3608 switch (Level) { 3609 case NoXOP: 3610 case SSE4A: 3611 Features["sse4a"] = false; 3612 LLVM_FALLTHROUGH; 3613 case FMA4: 3614 Features["fma4"] = false; 3615 LLVM_FALLTHROUGH; 3616 case XOP: 3617 Features["xop"] = false; 3618 break; 3619 } 3620 } 3621 3622 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3623 StringRef Name, bool Enabled) { 3624 // This is a bit of a hack to deal with the sse4 target feature when used 3625 // as part of the target attribute. We handle sse4 correctly everywhere 3626 // else. See below for more information on how we handle the sse4 options. 3627 if (Name != "sse4") 3628 Features[Name] = Enabled; 3629 3630 if (Name == "mmx") { 3631 setMMXLevel(Features, MMX, Enabled); 3632 } else if (Name == "sse") { 3633 setSSELevel(Features, SSE1, Enabled); 3634 } else if (Name == "sse2") { 3635 setSSELevel(Features, SSE2, Enabled); 3636 } else if (Name == "sse3") { 3637 setSSELevel(Features, SSE3, Enabled); 3638 } else if (Name == "ssse3") { 3639 setSSELevel(Features, SSSE3, Enabled); 3640 } else if (Name == "sse4.2") { 3641 setSSELevel(Features, SSE42, Enabled); 3642 } else if (Name == "sse4.1") { 3643 setSSELevel(Features, SSE41, Enabled); 3644 } else if (Name == "3dnow") { 3645 setMMXLevel(Features, AMD3DNow, Enabled); 3646 } else if (Name == "3dnowa") { 3647 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3648 } else if (Name == "aes") { 3649 if (Enabled) 3650 setSSELevel(Features, SSE2, Enabled); 3651 } else if (Name == "pclmul") { 3652 if (Enabled) 3653 setSSELevel(Features, SSE2, Enabled); 3654 } else if (Name == "avx") { 3655 setSSELevel(Features, AVX, Enabled); 3656 } else if (Name == "avx2") { 3657 setSSELevel(Features, AVX2, Enabled); 3658 } else if (Name == "avx512f") { 3659 setSSELevel(Features, AVX512F, Enabled); 3660 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3661 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3662 Name == "avx512vbmi" || Name == "avx512ifma" || 3663 Name == "avx512vpopcntdq") { 3664 if (Enabled) 3665 setSSELevel(Features, AVX512F, Enabled); 3666 // Enable BWI instruction if VBMI is being enabled. 3667 if (Name == "avx512vbmi" && Enabled) 3668 Features["avx512bw"] = true; 3669 // Also disable VBMI if BWI is being disabled. 3670 if (Name == "avx512bw" && !Enabled) 3671 Features["avx512vbmi"] = false; 3672 } else if (Name == "fma") { 3673 if (Enabled) 3674 setSSELevel(Features, AVX, Enabled); 3675 } else if (Name == "fma4") { 3676 setXOPLevel(Features, FMA4, Enabled); 3677 } else if (Name == "xop") { 3678 setXOPLevel(Features, XOP, Enabled); 3679 } else if (Name == "sse4a") { 3680 setXOPLevel(Features, SSE4A, Enabled); 3681 } else if (Name == "f16c") { 3682 if (Enabled) 3683 setSSELevel(Features, AVX, Enabled); 3684 } else if (Name == "sha") { 3685 if (Enabled) 3686 setSSELevel(Features, SSE2, Enabled); 3687 } else if (Name == "sse4") { 3688 // We can get here via the __target__ attribute since that's not controlled 3689 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3690 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3691 // disabled. 3692 if (Enabled) 3693 setSSELevel(Features, SSE42, Enabled); 3694 else 3695 setSSELevel(Features, SSE41, Enabled); 3696 } else if (Name == "xsave") { 3697 if (!Enabled) 3698 Features["xsaveopt"] = false; 3699 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3700 if (Enabled) 3701 Features["xsave"] = true; 3702 } 3703 } 3704 3705 /// handleTargetFeatures - Perform initialization based on the user 3706 /// configured set of features. 3707 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3708 DiagnosticsEngine &Diags) { 3709 for (const auto &Feature : Features) { 3710 if (Feature[0] != '+') 3711 continue; 3712 3713 if (Feature == "+aes") { 3714 HasAES = true; 3715 } else if (Feature == "+pclmul") { 3716 HasPCLMUL = true; 3717 } else if (Feature == "+lzcnt") { 3718 HasLZCNT = true; 3719 } else if (Feature == "+rdrnd") { 3720 HasRDRND = true; 3721 } else if (Feature == "+fsgsbase") { 3722 HasFSGSBASE = true; 3723 } else if (Feature == "+bmi") { 3724 HasBMI = true; 3725 } else if (Feature == "+bmi2") { 3726 HasBMI2 = true; 3727 } else if (Feature == "+popcnt") { 3728 HasPOPCNT = true; 3729 } else if (Feature == "+rtm") { 3730 HasRTM = true; 3731 } else if (Feature == "+prfchw") { 3732 HasPRFCHW = true; 3733 } else if (Feature == "+rdseed") { 3734 HasRDSEED = true; 3735 } else if (Feature == "+adx") { 3736 HasADX = true; 3737 } else if (Feature == "+tbm") { 3738 HasTBM = true; 3739 } else if (Feature == "+lwp") { 3740 HasLWP = true; 3741 } else if (Feature == "+fma") { 3742 HasFMA = true; 3743 } else if (Feature == "+f16c") { 3744 HasF16C = true; 3745 } else if (Feature == "+avx512cd") { 3746 HasAVX512CD = true; 3747 } else if (Feature == "+avx512vpopcntdq") { 3748 HasAVX512VPOPCNTDQ = true; 3749 } else if (Feature == "+avx512er") { 3750 HasAVX512ER = true; 3751 } else if (Feature == "+avx512pf") { 3752 HasAVX512PF = true; 3753 } else if (Feature == "+avx512dq") { 3754 HasAVX512DQ = true; 3755 } else if (Feature == "+avx512bw") { 3756 HasAVX512BW = true; 3757 } else if (Feature == "+avx512vl") { 3758 HasAVX512VL = true; 3759 } else if (Feature == "+avx512vbmi") { 3760 HasAVX512VBMI = true; 3761 } else if (Feature == "+avx512ifma") { 3762 HasAVX512IFMA = true; 3763 } else if (Feature == "+sha") { 3764 HasSHA = true; 3765 } else if (Feature == "+mpx") { 3766 HasMPX = true; 3767 } else if (Feature == "+movbe") { 3768 HasMOVBE = true; 3769 } else if (Feature == "+sgx") { 3770 HasSGX = true; 3771 } else if (Feature == "+cx16") { 3772 HasCX16 = true; 3773 } else if (Feature == "+fxsr") { 3774 HasFXSR = true; 3775 } else if (Feature == "+xsave") { 3776 HasXSAVE = true; 3777 } else if (Feature == "+xsaveopt") { 3778 HasXSAVEOPT = true; 3779 } else if (Feature == "+xsavec") { 3780 HasXSAVEC = true; 3781 } else if (Feature == "+xsaves") { 3782 HasXSAVES = true; 3783 } else if (Feature == "+mwaitx") { 3784 HasMWAITX = true; 3785 } else if (Feature == "+pku") { 3786 HasPKU = true; 3787 } else if (Feature == "+clflushopt") { 3788 HasCLFLUSHOPT = true; 3789 } else if (Feature == "+clwb") { 3790 HasCLWB = true; 3791 } else if (Feature == "+prefetchwt1") { 3792 HasPREFETCHWT1 = true; 3793 } else if (Feature == "+clzero") { 3794 HasCLZERO = true; 3795 } 3796 3797 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3798 .Case("+avx512f", AVX512F) 3799 .Case("+avx2", AVX2) 3800 .Case("+avx", AVX) 3801 .Case("+sse4.2", SSE42) 3802 .Case("+sse4.1", SSE41) 3803 .Case("+ssse3", SSSE3) 3804 .Case("+sse3", SSE3) 3805 .Case("+sse2", SSE2) 3806 .Case("+sse", SSE1) 3807 .Default(NoSSE); 3808 SSELevel = std::max(SSELevel, Level); 3809 3810 MMX3DNowEnum ThreeDNowLevel = 3811 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3812 .Case("+3dnowa", AMD3DNowAthlon) 3813 .Case("+3dnow", AMD3DNow) 3814 .Case("+mmx", MMX) 3815 .Default(NoMMX3DNow); 3816 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3817 3818 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3819 .Case("+xop", XOP) 3820 .Case("+fma4", FMA4) 3821 .Case("+sse4a", SSE4A) 3822 .Default(NoXOP); 3823 XOPLevel = std::max(XOPLevel, XLevel); 3824 } 3825 3826 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3827 // matches the selected sse level. 3828 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3829 (FPMath == FP_387 && SSELevel >= SSE1)) { 3830 Diags.Report(diag::err_target_unsupported_fpmath) << 3831 (FPMath == FP_SSE ? "sse" : "387"); 3832 return false; 3833 } 3834 3835 SimdDefaultAlign = 3836 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3837 return true; 3838 } 3839 3840 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3841 /// definitions for this particular subtarget. 3842 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3843 MacroBuilder &Builder) const { 3844 // Target identification. 3845 if (getTriple().getArch() == llvm::Triple::x86_64) { 3846 Builder.defineMacro("__amd64__"); 3847 Builder.defineMacro("__amd64"); 3848 Builder.defineMacro("__x86_64"); 3849 Builder.defineMacro("__x86_64__"); 3850 if (getTriple().getArchName() == "x86_64h") { 3851 Builder.defineMacro("__x86_64h"); 3852 Builder.defineMacro("__x86_64h__"); 3853 } 3854 } else { 3855 DefineStd(Builder, "i386", Opts); 3856 } 3857 3858 // Subtarget options. 3859 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3860 // truly should be based on -mtune options. 3861 switch (CPU) { 3862 case CK_Generic: 3863 break; 3864 case CK_i386: 3865 // The rest are coming from the i386 define above. 3866 Builder.defineMacro("__tune_i386__"); 3867 break; 3868 case CK_i486: 3869 case CK_WinChipC6: 3870 case CK_WinChip2: 3871 case CK_C3: 3872 defineCPUMacros(Builder, "i486"); 3873 break; 3874 case CK_PentiumMMX: 3875 Builder.defineMacro("__pentium_mmx__"); 3876 Builder.defineMacro("__tune_pentium_mmx__"); 3877 // Fallthrough 3878 case CK_i586: 3879 case CK_Pentium: 3880 defineCPUMacros(Builder, "i586"); 3881 defineCPUMacros(Builder, "pentium"); 3882 break; 3883 case CK_Pentium3: 3884 case CK_Pentium3M: 3885 case CK_PentiumM: 3886 Builder.defineMacro("__tune_pentium3__"); 3887 // Fallthrough 3888 case CK_Pentium2: 3889 case CK_C3_2: 3890 Builder.defineMacro("__tune_pentium2__"); 3891 // Fallthrough 3892 case CK_PentiumPro: 3893 Builder.defineMacro("__tune_i686__"); 3894 Builder.defineMacro("__tune_pentiumpro__"); 3895 // Fallthrough 3896 case CK_i686: 3897 Builder.defineMacro("__i686"); 3898 Builder.defineMacro("__i686__"); 3899 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3900 Builder.defineMacro("__pentiumpro"); 3901 Builder.defineMacro("__pentiumpro__"); 3902 break; 3903 case CK_Pentium4: 3904 case CK_Pentium4M: 3905 defineCPUMacros(Builder, "pentium4"); 3906 break; 3907 case CK_Yonah: 3908 case CK_Prescott: 3909 case CK_Nocona: 3910 defineCPUMacros(Builder, "nocona"); 3911 break; 3912 case CK_Core2: 3913 case CK_Penryn: 3914 defineCPUMacros(Builder, "core2"); 3915 break; 3916 case CK_Bonnell: 3917 defineCPUMacros(Builder, "atom"); 3918 break; 3919 case CK_Silvermont: 3920 defineCPUMacros(Builder, "slm"); 3921 break; 3922 case CK_Goldmont: 3923 defineCPUMacros(Builder, "goldmont"); 3924 break; 3925 case CK_Nehalem: 3926 case CK_Westmere: 3927 case CK_SandyBridge: 3928 case CK_IvyBridge: 3929 case CK_Haswell: 3930 case CK_Broadwell: 3931 case CK_SkylakeClient: 3932 // FIXME: Historically, we defined this legacy name, it would be nice to 3933 // remove it at some point. We've never exposed fine-grained names for 3934 // recent primary x86 CPUs, and we should keep it that way. 3935 defineCPUMacros(Builder, "corei7"); 3936 break; 3937 case CK_SkylakeServer: 3938 defineCPUMacros(Builder, "skx"); 3939 break; 3940 case CK_Cannonlake: 3941 break; 3942 case CK_KNL: 3943 defineCPUMacros(Builder, "knl"); 3944 break; 3945 case CK_Lakemont: 3946 Builder.defineMacro("__tune_lakemont__"); 3947 break; 3948 case CK_K6_2: 3949 Builder.defineMacro("__k6_2__"); 3950 Builder.defineMacro("__tune_k6_2__"); 3951 // Fallthrough 3952 case CK_K6_3: 3953 if (CPU != CK_K6_2) { // In case of fallthrough 3954 // FIXME: GCC may be enabling these in cases where some other k6 3955 // architecture is specified but -m3dnow is explicitly provided. The 3956 // exact semantics need to be determined and emulated here. 3957 Builder.defineMacro("__k6_3__"); 3958 Builder.defineMacro("__tune_k6_3__"); 3959 } 3960 // Fallthrough 3961 case CK_K6: 3962 defineCPUMacros(Builder, "k6"); 3963 break; 3964 case CK_Athlon: 3965 case CK_AthlonThunderbird: 3966 case CK_Athlon4: 3967 case CK_AthlonXP: 3968 case CK_AthlonMP: 3969 defineCPUMacros(Builder, "athlon"); 3970 if (SSELevel != NoSSE) { 3971 Builder.defineMacro("__athlon_sse__"); 3972 Builder.defineMacro("__tune_athlon_sse__"); 3973 } 3974 break; 3975 case CK_K8: 3976 case CK_K8SSE3: 3977 case CK_x86_64: 3978 case CK_Opteron: 3979 case CK_OpteronSSE3: 3980 case CK_Athlon64: 3981 case CK_Athlon64SSE3: 3982 case CK_AthlonFX: 3983 defineCPUMacros(Builder, "k8"); 3984 break; 3985 case CK_AMDFAM10: 3986 defineCPUMacros(Builder, "amdfam10"); 3987 break; 3988 case CK_BTVER1: 3989 defineCPUMacros(Builder, "btver1"); 3990 break; 3991 case CK_BTVER2: 3992 defineCPUMacros(Builder, "btver2"); 3993 break; 3994 case CK_BDVER1: 3995 defineCPUMacros(Builder, "bdver1"); 3996 break; 3997 case CK_BDVER2: 3998 defineCPUMacros(Builder, "bdver2"); 3999 break; 4000 case CK_BDVER3: 4001 defineCPUMacros(Builder, "bdver3"); 4002 break; 4003 case CK_BDVER4: 4004 defineCPUMacros(Builder, "bdver4"); 4005 break; 4006 case CK_ZNVER1: 4007 defineCPUMacros(Builder, "znver1"); 4008 break; 4009 case CK_Geode: 4010 defineCPUMacros(Builder, "geode"); 4011 break; 4012 } 4013 4014 // Target properties. 4015 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4016 4017 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 4018 // functions in glibc header files that use FP Stack inline asm which the 4019 // backend can't deal with (PR879). 4020 Builder.defineMacro("__NO_MATH_INLINES"); 4021 4022 if (HasAES) 4023 Builder.defineMacro("__AES__"); 4024 4025 if (HasPCLMUL) 4026 Builder.defineMacro("__PCLMUL__"); 4027 4028 if (HasLZCNT) 4029 Builder.defineMacro("__LZCNT__"); 4030 4031 if (HasRDRND) 4032 Builder.defineMacro("__RDRND__"); 4033 4034 if (HasFSGSBASE) 4035 Builder.defineMacro("__FSGSBASE__"); 4036 4037 if (HasBMI) 4038 Builder.defineMacro("__BMI__"); 4039 4040 if (HasBMI2) 4041 Builder.defineMacro("__BMI2__"); 4042 4043 if (HasPOPCNT) 4044 Builder.defineMacro("__POPCNT__"); 4045 4046 if (HasRTM) 4047 Builder.defineMacro("__RTM__"); 4048 4049 if (HasPRFCHW) 4050 Builder.defineMacro("__PRFCHW__"); 4051 4052 if (HasRDSEED) 4053 Builder.defineMacro("__RDSEED__"); 4054 4055 if (HasADX) 4056 Builder.defineMacro("__ADX__"); 4057 4058 if (HasTBM) 4059 Builder.defineMacro("__TBM__"); 4060 4061 if (HasLWP) 4062 Builder.defineMacro("__LWP__"); 4063 4064 if (HasMWAITX) 4065 Builder.defineMacro("__MWAITX__"); 4066 4067 switch (XOPLevel) { 4068 case XOP: 4069 Builder.defineMacro("__XOP__"); 4070 LLVM_FALLTHROUGH; 4071 case FMA4: 4072 Builder.defineMacro("__FMA4__"); 4073 LLVM_FALLTHROUGH; 4074 case SSE4A: 4075 Builder.defineMacro("__SSE4A__"); 4076 LLVM_FALLTHROUGH; 4077 case NoXOP: 4078 break; 4079 } 4080 4081 if (HasFMA) 4082 Builder.defineMacro("__FMA__"); 4083 4084 if (HasF16C) 4085 Builder.defineMacro("__F16C__"); 4086 4087 if (HasAVX512CD) 4088 Builder.defineMacro("__AVX512CD__"); 4089 if (HasAVX512VPOPCNTDQ) 4090 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 4091 if (HasAVX512ER) 4092 Builder.defineMacro("__AVX512ER__"); 4093 if (HasAVX512PF) 4094 Builder.defineMacro("__AVX512PF__"); 4095 if (HasAVX512DQ) 4096 Builder.defineMacro("__AVX512DQ__"); 4097 if (HasAVX512BW) 4098 Builder.defineMacro("__AVX512BW__"); 4099 if (HasAVX512VL) 4100 Builder.defineMacro("__AVX512VL__"); 4101 if (HasAVX512VBMI) 4102 Builder.defineMacro("__AVX512VBMI__"); 4103 if (HasAVX512IFMA) 4104 Builder.defineMacro("__AVX512IFMA__"); 4105 4106 if (HasSHA) 4107 Builder.defineMacro("__SHA__"); 4108 4109 if (HasFXSR) 4110 Builder.defineMacro("__FXSR__"); 4111 if (HasXSAVE) 4112 Builder.defineMacro("__XSAVE__"); 4113 if (HasXSAVEOPT) 4114 Builder.defineMacro("__XSAVEOPT__"); 4115 if (HasXSAVEC) 4116 Builder.defineMacro("__XSAVEC__"); 4117 if (HasXSAVES) 4118 Builder.defineMacro("__XSAVES__"); 4119 if (HasPKU) 4120 Builder.defineMacro("__PKU__"); 4121 if (HasCX16) 4122 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 4123 if (HasCLFLUSHOPT) 4124 Builder.defineMacro("__CLFLUSHOPT__"); 4125 if (HasCLWB) 4126 Builder.defineMacro("__CLWB__"); 4127 if (HasMPX) 4128 Builder.defineMacro("__MPX__"); 4129 if (HasSGX) 4130 Builder.defineMacro("__SGX__"); 4131 if (HasPREFETCHWT1) 4132 Builder.defineMacro("__PREFETCHWT1__"); 4133 if (HasCLZERO) 4134 Builder.defineMacro("__CLZERO__"); 4135 4136 // Each case falls through to the previous one here. 4137 switch (SSELevel) { 4138 case AVX512F: 4139 Builder.defineMacro("__AVX512F__"); 4140 LLVM_FALLTHROUGH; 4141 case AVX2: 4142 Builder.defineMacro("__AVX2__"); 4143 LLVM_FALLTHROUGH; 4144 case AVX: 4145 Builder.defineMacro("__AVX__"); 4146 LLVM_FALLTHROUGH; 4147 case SSE42: 4148 Builder.defineMacro("__SSE4_2__"); 4149 LLVM_FALLTHROUGH; 4150 case SSE41: 4151 Builder.defineMacro("__SSE4_1__"); 4152 LLVM_FALLTHROUGH; 4153 case SSSE3: 4154 Builder.defineMacro("__SSSE3__"); 4155 LLVM_FALLTHROUGH; 4156 case SSE3: 4157 Builder.defineMacro("__SSE3__"); 4158 LLVM_FALLTHROUGH; 4159 case SSE2: 4160 Builder.defineMacro("__SSE2__"); 4161 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 4162 LLVM_FALLTHROUGH; 4163 case SSE1: 4164 Builder.defineMacro("__SSE__"); 4165 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 4166 LLVM_FALLTHROUGH; 4167 case NoSSE: 4168 break; 4169 } 4170 4171 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 4172 switch (SSELevel) { 4173 case AVX512F: 4174 case AVX2: 4175 case AVX: 4176 case SSE42: 4177 case SSE41: 4178 case SSSE3: 4179 case SSE3: 4180 case SSE2: 4181 Builder.defineMacro("_M_IX86_FP", Twine(2)); 4182 break; 4183 case SSE1: 4184 Builder.defineMacro("_M_IX86_FP", Twine(1)); 4185 break; 4186 default: 4187 Builder.defineMacro("_M_IX86_FP", Twine(0)); 4188 break; 4189 } 4190 } 4191 4192 // Each case falls through to the previous one here. 4193 switch (MMX3DNowLevel) { 4194 case AMD3DNowAthlon: 4195 Builder.defineMacro("__3dNOW_A__"); 4196 LLVM_FALLTHROUGH; 4197 case AMD3DNow: 4198 Builder.defineMacro("__3dNOW__"); 4199 LLVM_FALLTHROUGH; 4200 case MMX: 4201 Builder.defineMacro("__MMX__"); 4202 LLVM_FALLTHROUGH; 4203 case NoMMX3DNow: 4204 break; 4205 } 4206 4207 if (CPU >= CK_i486) { 4208 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4209 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4210 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4211 } 4212 if (CPU >= CK_i586) 4213 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4214 4215 if (HasFloat128) 4216 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 4217 } 4218 4219 bool X86TargetInfo::hasFeature(StringRef Feature) const { 4220 return llvm::StringSwitch<bool>(Feature) 4221 .Case("aes", HasAES) 4222 .Case("avx", SSELevel >= AVX) 4223 .Case("avx2", SSELevel >= AVX2) 4224 .Case("avx512f", SSELevel >= AVX512F) 4225 .Case("avx512cd", HasAVX512CD) 4226 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 4227 .Case("avx512er", HasAVX512ER) 4228 .Case("avx512pf", HasAVX512PF) 4229 .Case("avx512dq", HasAVX512DQ) 4230 .Case("avx512bw", HasAVX512BW) 4231 .Case("avx512vl", HasAVX512VL) 4232 .Case("avx512vbmi", HasAVX512VBMI) 4233 .Case("avx512ifma", HasAVX512IFMA) 4234 .Case("bmi", HasBMI) 4235 .Case("bmi2", HasBMI2) 4236 .Case("clflushopt", HasCLFLUSHOPT) 4237 .Case("clwb", HasCLWB) 4238 .Case("clzero", HasCLZERO) 4239 .Case("cx16", HasCX16) 4240 .Case("f16c", HasF16C) 4241 .Case("fma", HasFMA) 4242 .Case("fma4", XOPLevel >= FMA4) 4243 .Case("fsgsbase", HasFSGSBASE) 4244 .Case("fxsr", HasFXSR) 4245 .Case("lzcnt", HasLZCNT) 4246 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 4247 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 4248 .Case("mmx", MMX3DNowLevel >= MMX) 4249 .Case("movbe", HasMOVBE) 4250 .Case("mpx", HasMPX) 4251 .Case("pclmul", HasPCLMUL) 4252 .Case("pku", HasPKU) 4253 .Case("popcnt", HasPOPCNT) 4254 .Case("prefetchwt1", HasPREFETCHWT1) 4255 .Case("prfchw", HasPRFCHW) 4256 .Case("rdrnd", HasRDRND) 4257 .Case("rdseed", HasRDSEED) 4258 .Case("rtm", HasRTM) 4259 .Case("sgx", HasSGX) 4260 .Case("sha", HasSHA) 4261 .Case("sse", SSELevel >= SSE1) 4262 .Case("sse2", SSELevel >= SSE2) 4263 .Case("sse3", SSELevel >= SSE3) 4264 .Case("ssse3", SSELevel >= SSSE3) 4265 .Case("sse4.1", SSELevel >= SSE41) 4266 .Case("sse4.2", SSELevel >= SSE42) 4267 .Case("sse4a", XOPLevel >= SSE4A) 4268 .Case("tbm", HasTBM) 4269 .Case("lwp", HasLWP) 4270 .Case("x86", true) 4271 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 4272 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 4273 .Case("xop", XOPLevel >= XOP) 4274 .Case("xsave", HasXSAVE) 4275 .Case("xsavec", HasXSAVEC) 4276 .Case("xsaves", HasXSAVES) 4277 .Case("xsaveopt", HasXSAVEOPT) 4278 .Default(false); 4279 } 4280 4281 // We can't use a generic validation scheme for the features accepted here 4282 // versus subtarget features accepted in the target attribute because the 4283 // bitfield structure that's initialized in the runtime only supports the 4284 // below currently rather than the full range of subtarget features. (See 4285 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 4286 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 4287 return llvm::StringSwitch<bool>(FeatureStr) 4288 .Case("cmov", true) 4289 .Case("mmx", true) 4290 .Case("popcnt", true) 4291 .Case("sse", true) 4292 .Case("sse2", true) 4293 .Case("sse3", true) 4294 .Case("ssse3", true) 4295 .Case("sse4.1", true) 4296 .Case("sse4.2", true) 4297 .Case("avx", true) 4298 .Case("avx2", true) 4299 .Case("sse4a", true) 4300 .Case("fma4", true) 4301 .Case("xop", true) 4302 .Case("fma", true) 4303 .Case("avx512f", true) 4304 .Case("bmi", true) 4305 .Case("bmi2", true) 4306 .Case("aes", true) 4307 .Case("pclmul", true) 4308 .Case("avx512vl", true) 4309 .Case("avx512bw", true) 4310 .Case("avx512dq", true) 4311 .Case("avx512cd", true) 4312 .Case("avx512vpopcntdq", true) 4313 .Case("avx512er", true) 4314 .Case("avx512pf", true) 4315 .Case("avx512vbmi", true) 4316 .Case("avx512ifma", true) 4317 .Default(false); 4318 } 4319 4320 bool 4321 X86TargetInfo::validateAsmConstraint(const char *&Name, 4322 TargetInfo::ConstraintInfo &Info) const { 4323 switch (*Name) { 4324 default: return false; 4325 // Constant constraints. 4326 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 4327 // instructions. 4328 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 4329 // x86_64 instructions. 4330 case 's': 4331 Info.setRequiresImmediate(); 4332 return true; 4333 case 'I': 4334 Info.setRequiresImmediate(0, 31); 4335 return true; 4336 case 'J': 4337 Info.setRequiresImmediate(0, 63); 4338 return true; 4339 case 'K': 4340 Info.setRequiresImmediate(-128, 127); 4341 return true; 4342 case 'L': 4343 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 4344 return true; 4345 case 'M': 4346 Info.setRequiresImmediate(0, 3); 4347 return true; 4348 case 'N': 4349 Info.setRequiresImmediate(0, 255); 4350 return true; 4351 case 'O': 4352 Info.setRequiresImmediate(0, 127); 4353 return true; 4354 // Register constraints. 4355 case 'Y': // 'Y' is the first character for several 2-character constraints. 4356 // Shift the pointer to the second character of the constraint. 4357 Name++; 4358 switch (*Name) { 4359 default: 4360 return false; 4361 case '0': // First SSE register. 4362 case 't': // Any SSE register, when SSE2 is enabled. 4363 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 4364 case 'm': // Any MMX register, when inter-unit moves enabled. 4365 case 'k': // AVX512 arch mask registers: k1-k7. 4366 Info.setAllowsRegister(); 4367 return true; 4368 } 4369 case 'f': // Any x87 floating point stack register. 4370 // Constraint 'f' cannot be used for output operands. 4371 if (Info.ConstraintStr[0] == '=') 4372 return false; 4373 Info.setAllowsRegister(); 4374 return true; 4375 case 'a': // eax. 4376 case 'b': // ebx. 4377 case 'c': // ecx. 4378 case 'd': // edx. 4379 case 'S': // esi. 4380 case 'D': // edi. 4381 case 'A': // edx:eax. 4382 case 't': // Top of floating point stack. 4383 case 'u': // Second from top of floating point stack. 4384 case 'q': // Any register accessible as [r]l: a, b, c, and d. 4385 case 'y': // Any MMX register. 4386 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 4387 case 'x': // Any SSE register. 4388 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 4389 // for intermideate k reg operations). 4390 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 4391 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 4392 case 'l': // "Index" registers: any general register that can be used as an 4393 // index in a base+index memory access. 4394 Info.setAllowsRegister(); 4395 return true; 4396 // Floating point constant constraints. 4397 case 'C': // SSE floating point constant. 4398 case 'G': // x87 floating point constant. 4399 return true; 4400 } 4401 } 4402 4403 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 4404 unsigned Size) const { 4405 // Strip off constraint modifiers. 4406 while (Constraint[0] == '=' || 4407 Constraint[0] == '+' || 4408 Constraint[0] == '&') 4409 Constraint = Constraint.substr(1); 4410 4411 return validateOperandSize(Constraint, Size); 4412 } 4413 4414 bool X86TargetInfo::validateInputSize(StringRef Constraint, 4415 unsigned Size) const { 4416 return validateOperandSize(Constraint, Size); 4417 } 4418 4419 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 4420 unsigned Size) const { 4421 switch (Constraint[0]) { 4422 default: break; 4423 case 'k': 4424 // Registers k0-k7 (AVX512) size limit is 64 bit. 4425 case 'y': 4426 return Size <= 64; 4427 case 'f': 4428 case 't': 4429 case 'u': 4430 return Size <= 128; 4431 case 'v': 4432 case 'x': 4433 if (SSELevel >= AVX512F) 4434 // 512-bit zmm registers can be used if target supports AVX512F. 4435 return Size <= 512U; 4436 else if (SSELevel >= AVX) 4437 // 256-bit ymm registers can be used if target supports AVX. 4438 return Size <= 256U; 4439 return Size <= 128U; 4440 case 'Y': 4441 // 'Y' is the first character for several 2-character constraints. 4442 switch (Constraint[1]) { 4443 default: break; 4444 case 'm': 4445 // 'Ym' is synonymous with 'y'. 4446 case 'k': 4447 return Size <= 64; 4448 case 'i': 4449 case 't': 4450 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4451 if (SSELevel >= AVX512F) 4452 return Size <= 512U; 4453 else if (SSELevel >= AVX) 4454 return Size <= 256U; 4455 return SSELevel >= SSE2 && Size <= 128U; 4456 } 4457 4458 } 4459 4460 return true; 4461 } 4462 4463 std::string 4464 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4465 switch (*Constraint) { 4466 case 'a': return std::string("{ax}"); 4467 case 'b': return std::string("{bx}"); 4468 case 'c': return std::string("{cx}"); 4469 case 'd': return std::string("{dx}"); 4470 case 'S': return std::string("{si}"); 4471 case 'D': return std::string("{di}"); 4472 case 'p': // address 4473 return std::string("im"); 4474 case 't': // top of floating point stack. 4475 return std::string("{st}"); 4476 case 'u': // second from top of floating point stack. 4477 return std::string("{st(1)}"); // second from top of floating point stack. 4478 case 'Y': 4479 switch (Constraint[1]) { 4480 default: 4481 // Break from inner switch and fall through (copy single char), 4482 // continue parsing after copying the current constraint into 4483 // the return string. 4484 break; 4485 case 'k': 4486 // "^" hints llvm that this is a 2 letter constraint. 4487 // "Constraint++" is used to promote the string iterator 4488 // to the next constraint. 4489 return std::string("^") + std::string(Constraint++, 2); 4490 } 4491 LLVM_FALLTHROUGH; 4492 default: 4493 return std::string(1, *Constraint); 4494 } 4495 } 4496 4497 // X86-32 generic target 4498 class X86_32TargetInfo : public X86TargetInfo { 4499 public: 4500 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4501 : X86TargetInfo(Triple, Opts) { 4502 DoubleAlign = LongLongAlign = 32; 4503 LongDoubleWidth = 96; 4504 LongDoubleAlign = 32; 4505 SuitableAlign = 128; 4506 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4507 SizeType = UnsignedInt; 4508 PtrDiffType = SignedInt; 4509 IntPtrType = SignedInt; 4510 RegParmMax = 3; 4511 4512 // Use fpret for all types. 4513 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4514 (1 << TargetInfo::Double) | 4515 (1 << TargetInfo::LongDouble)); 4516 4517 // x86-32 has atomics up to 8 bytes 4518 // FIXME: Check that we actually have cmpxchg8b before setting 4519 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4520 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4521 } 4522 BuiltinVaListKind getBuiltinVaListKind() const override { 4523 return TargetInfo::CharPtrBuiltinVaList; 4524 } 4525 4526 int getEHDataRegisterNumber(unsigned RegNo) const override { 4527 if (RegNo == 0) return 0; 4528 if (RegNo == 1) return 2; 4529 return -1; 4530 } 4531 bool validateOperandSize(StringRef Constraint, 4532 unsigned Size) const override { 4533 switch (Constraint[0]) { 4534 default: break; 4535 case 'R': 4536 case 'q': 4537 case 'Q': 4538 case 'a': 4539 case 'b': 4540 case 'c': 4541 case 'd': 4542 case 'S': 4543 case 'D': 4544 return Size <= 32; 4545 case 'A': 4546 return Size <= 64; 4547 } 4548 4549 return X86TargetInfo::validateOperandSize(Constraint, Size); 4550 } 4551 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4552 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 4553 Builtin::FirstTSBuiltin + 1); 4554 } 4555 }; 4556 4557 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4558 public: 4559 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4560 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4561 4562 unsigned getFloatEvalMethod() const override { 4563 unsigned Major, Minor, Micro; 4564 getTriple().getOSVersion(Major, Minor, Micro); 4565 // New NetBSD uses the default rounding mode. 4566 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4567 return X86_32TargetInfo::getFloatEvalMethod(); 4568 // NetBSD before 6.99.26 defaults to "double" rounding. 4569 return 1; 4570 } 4571 }; 4572 4573 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4574 public: 4575 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4576 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4577 SizeType = UnsignedLong; 4578 IntPtrType = SignedLong; 4579 PtrDiffType = SignedLong; 4580 } 4581 }; 4582 4583 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4584 public: 4585 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4586 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4587 SizeType = UnsignedLong; 4588 IntPtrType = SignedLong; 4589 PtrDiffType = SignedLong; 4590 } 4591 }; 4592 4593 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4594 public: 4595 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4596 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4597 LongDoubleWidth = 128; 4598 LongDoubleAlign = 128; 4599 SuitableAlign = 128; 4600 MaxVectorAlign = 256; 4601 // The watchOS simulator uses the builtin bool type for Objective-C. 4602 llvm::Triple T = llvm::Triple(Triple); 4603 if (T.isWatchOS()) 4604 UseSignedCharForObjCBool = false; 4605 SizeType = UnsignedLong; 4606 IntPtrType = SignedLong; 4607 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4608 HasAlignMac68kSupport = true; 4609 } 4610 4611 bool handleTargetFeatures(std::vector<std::string> &Features, 4612 DiagnosticsEngine &Diags) override { 4613 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4614 Diags)) 4615 return false; 4616 // We now know the features we have: we can decide how to align vectors. 4617 MaxVectorAlign = 4618 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4619 return true; 4620 } 4621 }; 4622 4623 // x86-32 Windows target 4624 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4625 public: 4626 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4627 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4628 WCharType = UnsignedShort; 4629 DoubleAlign = LongLongAlign = 64; 4630 bool IsWinCOFF = 4631 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4632 resetDataLayout(IsWinCOFF 4633 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4634 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4635 } 4636 void getTargetDefines(const LangOptions &Opts, 4637 MacroBuilder &Builder) const override { 4638 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4639 } 4640 }; 4641 4642 // x86-32 Windows Visual Studio target 4643 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4644 public: 4645 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4646 const TargetOptions &Opts) 4647 : WindowsX86_32TargetInfo(Triple, Opts) { 4648 LongDoubleWidth = LongDoubleAlign = 64; 4649 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4650 } 4651 void getTargetDefines(const LangOptions &Opts, 4652 MacroBuilder &Builder) const override { 4653 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4654 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4655 // The value of the following reflects processor type. 4656 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4657 // We lost the original triple, so we use the default. 4658 Builder.defineMacro("_M_IX86", "600"); 4659 } 4660 }; 4661 4662 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4663 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4664 // supports __declspec natively under -fms-extensions, but we define a no-op 4665 // __declspec macro anyway for pre-processor compatibility. 4666 if (Opts.MicrosoftExt) 4667 Builder.defineMacro("__declspec", "__declspec"); 4668 else 4669 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4670 4671 if (!Opts.MicrosoftExt) { 4672 // Provide macros for all the calling convention keywords. Provide both 4673 // single and double underscore prefixed variants. These are available on 4674 // x64 as well as x86, even though they have no effect. 4675 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4676 for (const char *CC : CCs) { 4677 std::string GCCSpelling = "__attribute__((__"; 4678 GCCSpelling += CC; 4679 GCCSpelling += "__))"; 4680 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4681 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4682 } 4683 } 4684 } 4685 4686 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4687 Builder.defineMacro("__MSVCRT__"); 4688 Builder.defineMacro("__MINGW32__"); 4689 addCygMingDefines(Opts, Builder); 4690 } 4691 4692 // x86-32 MinGW target 4693 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4694 public: 4695 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4696 : WindowsX86_32TargetInfo(Triple, Opts) { 4697 HasFloat128 = true; 4698 } 4699 void getTargetDefines(const LangOptions &Opts, 4700 MacroBuilder &Builder) const override { 4701 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4702 DefineStd(Builder, "WIN32", Opts); 4703 DefineStd(Builder, "WINNT", Opts); 4704 Builder.defineMacro("_X86_"); 4705 addMinGWDefines(Opts, Builder); 4706 } 4707 }; 4708 4709 // x86-32 Cygwin target 4710 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4711 public: 4712 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4713 : X86_32TargetInfo(Triple, Opts) { 4714 WCharType = UnsignedShort; 4715 DoubleAlign = LongLongAlign = 64; 4716 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4717 } 4718 void getTargetDefines(const LangOptions &Opts, 4719 MacroBuilder &Builder) const override { 4720 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4721 Builder.defineMacro("_X86_"); 4722 Builder.defineMacro("__CYGWIN__"); 4723 Builder.defineMacro("__CYGWIN32__"); 4724 addCygMingDefines(Opts, Builder); 4725 DefineStd(Builder, "unix", Opts); 4726 if (Opts.CPlusPlus) 4727 Builder.defineMacro("_GNU_SOURCE"); 4728 } 4729 }; 4730 4731 // x86-32 Haiku target 4732 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4733 public: 4734 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4735 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4736 } 4737 void getTargetDefines(const LangOptions &Opts, 4738 MacroBuilder &Builder) const override { 4739 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4740 Builder.defineMacro("__INTEL__"); 4741 } 4742 }; 4743 4744 // X86-32 MCU target 4745 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4746 public: 4747 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4748 : X86_32TargetInfo(Triple, Opts) { 4749 LongDoubleWidth = 64; 4750 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4751 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4752 WIntType = UnsignedInt; 4753 } 4754 4755 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4756 // On MCU we support only C calling convention. 4757 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4758 } 4759 4760 void getTargetDefines(const LangOptions &Opts, 4761 MacroBuilder &Builder) const override { 4762 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4763 Builder.defineMacro("__iamcu"); 4764 Builder.defineMacro("__iamcu__"); 4765 } 4766 4767 bool allowsLargerPreferedTypeAlignment() const override { 4768 return false; 4769 } 4770 }; 4771 4772 // RTEMS Target 4773 template<typename Target> 4774 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4775 protected: 4776 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4777 MacroBuilder &Builder) const override { 4778 // RTEMS defines; list based off of gcc output 4779 4780 Builder.defineMacro("__rtems__"); 4781 Builder.defineMacro("__ELF__"); 4782 } 4783 4784 public: 4785 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4786 : OSTargetInfo<Target>(Triple, Opts) { 4787 switch (Triple.getArch()) { 4788 default: 4789 case llvm::Triple::x86: 4790 // this->MCountName = ".mcount"; 4791 break; 4792 case llvm::Triple::mips: 4793 case llvm::Triple::mipsel: 4794 case llvm::Triple::ppc: 4795 case llvm::Triple::ppc64: 4796 case llvm::Triple::ppc64le: 4797 // this->MCountName = "_mcount"; 4798 break; 4799 case llvm::Triple::arm: 4800 // this->MCountName = "__mcount"; 4801 break; 4802 } 4803 } 4804 }; 4805 4806 // x86-32 RTEMS target 4807 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4808 public: 4809 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4810 : X86_32TargetInfo(Triple, Opts) { 4811 SizeType = UnsignedLong; 4812 IntPtrType = SignedLong; 4813 PtrDiffType = SignedLong; 4814 } 4815 void getTargetDefines(const LangOptions &Opts, 4816 MacroBuilder &Builder) const override { 4817 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4818 Builder.defineMacro("__INTEL__"); 4819 Builder.defineMacro("__rtems__"); 4820 } 4821 }; 4822 4823 // x86-64 generic target 4824 class X86_64TargetInfo : public X86TargetInfo { 4825 public: 4826 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4827 : X86TargetInfo(Triple, Opts) { 4828 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4829 bool IsWinCOFF = 4830 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4831 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4832 LongDoubleWidth = 128; 4833 LongDoubleAlign = 128; 4834 LargeArrayMinWidth = 128; 4835 LargeArrayAlign = 128; 4836 SuitableAlign = 128; 4837 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4838 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4839 IntPtrType = IsX32 ? SignedInt : SignedLong; 4840 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4841 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4842 RegParmMax = 6; 4843 4844 // Pointers are 32-bit in x32. 4845 resetDataLayout(IsX32 4846 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4847 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4848 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4849 4850 // Use fpret only for long double. 4851 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4852 4853 // Use fp2ret for _Complex long double. 4854 ComplexLongDoubleUsesFP2Ret = true; 4855 4856 // Make __builtin_ms_va_list available. 4857 HasBuiltinMSVaList = true; 4858 4859 // x86-64 has atomics up to 16 bytes. 4860 MaxAtomicPromoteWidth = 128; 4861 MaxAtomicInlineWidth = 128; 4862 } 4863 BuiltinVaListKind getBuiltinVaListKind() const override { 4864 return TargetInfo::X86_64ABIBuiltinVaList; 4865 } 4866 4867 int getEHDataRegisterNumber(unsigned RegNo) const override { 4868 if (RegNo == 0) return 0; 4869 if (RegNo == 1) return 1; 4870 return -1; 4871 } 4872 4873 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4874 switch (CC) { 4875 case CC_C: 4876 case CC_Swift: 4877 case CC_X86VectorCall: 4878 case CC_IntelOclBicc: 4879 case CC_X86_64Win64: 4880 case CC_PreserveMost: 4881 case CC_PreserveAll: 4882 case CC_X86RegCall: 4883 case CC_OpenCLKernel: 4884 return CCCR_OK; 4885 default: 4886 return CCCR_Warning; 4887 } 4888 } 4889 4890 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4891 return CC_C; 4892 } 4893 4894 // for x32 we need it here explicitly 4895 bool hasInt128Type() const override { return true; } 4896 unsigned getUnwindWordWidth() const override { return 64; } 4897 unsigned getRegisterWidth() const override { return 64; } 4898 4899 bool validateGlobalRegisterVariable(StringRef RegName, 4900 unsigned RegSize, 4901 bool &HasSizeMismatch) const override { 4902 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4903 // handle. 4904 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4905 // Check that the register size is 64-bit. 4906 HasSizeMismatch = RegSize != 64; 4907 return true; 4908 } 4909 4910 // Check if the register is a 32-bit register the backend can handle. 4911 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4912 HasSizeMismatch); 4913 } 4914 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4915 return llvm::makeArrayRef(BuiltinInfoX86, 4916 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 4917 } 4918 }; 4919 4920 // x86-64 Windows target 4921 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4922 public: 4923 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4924 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4925 WCharType = UnsignedShort; 4926 LongWidth = LongAlign = 32; 4927 DoubleAlign = LongLongAlign = 64; 4928 IntMaxType = SignedLongLong; 4929 Int64Type = SignedLongLong; 4930 SizeType = UnsignedLongLong; 4931 PtrDiffType = SignedLongLong; 4932 IntPtrType = SignedLongLong; 4933 } 4934 4935 void getTargetDefines(const LangOptions &Opts, 4936 MacroBuilder &Builder) const override { 4937 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4938 Builder.defineMacro("_WIN64"); 4939 } 4940 4941 BuiltinVaListKind getBuiltinVaListKind() const override { 4942 return TargetInfo::CharPtrBuiltinVaList; 4943 } 4944 4945 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4946 switch (CC) { 4947 case CC_X86StdCall: 4948 case CC_X86ThisCall: 4949 case CC_X86FastCall: 4950 return CCCR_Ignore; 4951 case CC_C: 4952 case CC_X86VectorCall: 4953 case CC_IntelOclBicc: 4954 case CC_X86_64SysV: 4955 case CC_Swift: 4956 case CC_X86RegCall: 4957 case CC_OpenCLKernel: 4958 return CCCR_OK; 4959 default: 4960 return CCCR_Warning; 4961 } 4962 } 4963 }; 4964 4965 // x86-64 Windows Visual Studio target 4966 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4967 public: 4968 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4969 const TargetOptions &Opts) 4970 : WindowsX86_64TargetInfo(Triple, Opts) { 4971 LongDoubleWidth = LongDoubleAlign = 64; 4972 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4973 } 4974 void getTargetDefines(const LangOptions &Opts, 4975 MacroBuilder &Builder) const override { 4976 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4977 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4978 Builder.defineMacro("_M_X64", "100"); 4979 Builder.defineMacro("_M_AMD64", "100"); 4980 } 4981 }; 4982 4983 // x86-64 MinGW target 4984 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4985 public: 4986 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4987 : WindowsX86_64TargetInfo(Triple, Opts) { 4988 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4989 // with x86 FP ops. Weird. 4990 LongDoubleWidth = LongDoubleAlign = 128; 4991 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 4992 HasFloat128 = true; 4993 } 4994 4995 void getTargetDefines(const LangOptions &Opts, 4996 MacroBuilder &Builder) const override { 4997 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4998 DefineStd(Builder, "WIN64", Opts); 4999 Builder.defineMacro("__MINGW64__"); 5000 addMinGWDefines(Opts, Builder); 5001 5002 // GCC defines this macro when it is using __gxx_personality_seh0. 5003 if (!Opts.SjLjExceptions) 5004 Builder.defineMacro("__SEH__"); 5005 } 5006 }; 5007 5008 // x86-64 Cygwin target 5009 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 5010 public: 5011 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5012 : X86_64TargetInfo(Triple, Opts) { 5013 TLSSupported = false; 5014 WCharType = UnsignedShort; 5015 } 5016 void getTargetDefines(const LangOptions &Opts, 5017 MacroBuilder &Builder) const override { 5018 X86_64TargetInfo::getTargetDefines(Opts, Builder); 5019 Builder.defineMacro("__x86_64__"); 5020 Builder.defineMacro("__CYGWIN__"); 5021 Builder.defineMacro("__CYGWIN64__"); 5022 addCygMingDefines(Opts, Builder); 5023 DefineStd(Builder, "unix", Opts); 5024 if (Opts.CPlusPlus) 5025 Builder.defineMacro("_GNU_SOURCE"); 5026 5027 // GCC defines this macro when it is using __gxx_personality_seh0. 5028 if (!Opts.SjLjExceptions) 5029 Builder.defineMacro("__SEH__"); 5030 } 5031 }; 5032 5033 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 5034 public: 5035 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5036 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5037 Int64Type = SignedLongLong; 5038 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 5039 llvm::Triple T = llvm::Triple(Triple); 5040 if (T.isiOS()) 5041 UseSignedCharForObjCBool = false; 5042 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 5043 } 5044 5045 bool handleTargetFeatures(std::vector<std::string> &Features, 5046 DiagnosticsEngine &Diags) override { 5047 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 5048 Diags)) 5049 return false; 5050 // We now know the features we have: we can decide how to align vectors. 5051 MaxVectorAlign = 5052 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 5053 return true; 5054 } 5055 }; 5056 5057 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 5058 public: 5059 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5060 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5061 IntMaxType = SignedLongLong; 5062 Int64Type = SignedLongLong; 5063 } 5064 }; 5065 5066 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 5067 public: 5068 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5069 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5070 IntMaxType = SignedLongLong; 5071 Int64Type = SignedLongLong; 5072 } 5073 }; 5074 5075 class ARMTargetInfo : public TargetInfo { 5076 // Possible FPU choices. 5077 enum FPUMode { 5078 VFP2FPU = (1 << 0), 5079 VFP3FPU = (1 << 1), 5080 VFP4FPU = (1 << 2), 5081 NeonFPU = (1 << 3), 5082 FPARMV8 = (1 << 4) 5083 }; 5084 5085 // Possible HWDiv features. 5086 enum HWDivMode { 5087 HWDivThumb = (1 << 0), 5088 HWDivARM = (1 << 1) 5089 }; 5090 5091 static bool FPUModeIsVFP(FPUMode Mode) { 5092 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 5093 } 5094 5095 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5096 static const char * const GCCRegNames[]; 5097 5098 std::string ABI, CPU; 5099 5100 StringRef CPUProfile; 5101 StringRef CPUAttr; 5102 5103 enum { 5104 FP_Default, 5105 FP_VFP, 5106 FP_Neon 5107 } FPMath; 5108 5109 unsigned ArchISA; 5110 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 5111 unsigned ArchProfile; 5112 unsigned ArchVersion; 5113 5114 unsigned FPU : 5; 5115 5116 unsigned IsAAPCS : 1; 5117 unsigned HWDiv : 2; 5118 5119 // Initialized via features. 5120 unsigned SoftFloat : 1; 5121 unsigned SoftFloatABI : 1; 5122 5123 unsigned CRC : 1; 5124 unsigned Crypto : 1; 5125 unsigned DSP : 1; 5126 unsigned Unaligned : 1; 5127 5128 enum { 5129 LDREX_B = (1 << 0), /// byte (8-bit) 5130 LDREX_H = (1 << 1), /// half (16-bit) 5131 LDREX_W = (1 << 2), /// word (32-bit) 5132 LDREX_D = (1 << 3), /// double (64-bit) 5133 }; 5134 5135 uint32_t LDREX; 5136 5137 // ACLE 6.5.1 Hardware floating point 5138 enum { 5139 HW_FP_HP = (1 << 1), /// half (16-bit) 5140 HW_FP_SP = (1 << 2), /// single (32-bit) 5141 HW_FP_DP = (1 << 3), /// double (64-bit) 5142 }; 5143 uint32_t HW_FP; 5144 5145 static const Builtin::Info BuiltinInfo[]; 5146 5147 void setABIAAPCS() { 5148 IsAAPCS = true; 5149 5150 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5151 const llvm::Triple &T = getTriple(); 5152 5153 // size_t is unsigned long on MachO-derived environments, NetBSD, 5154 // OpenBSD and Bitrig. 5155 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 5156 T.getOS() == llvm::Triple::OpenBSD || 5157 T.getOS() == llvm::Triple::Bitrig) 5158 SizeType = UnsignedLong; 5159 else 5160 SizeType = UnsignedInt; 5161 5162 switch (T.getOS()) { 5163 case llvm::Triple::NetBSD: 5164 case llvm::Triple::OpenBSD: 5165 WCharType = SignedInt; 5166 break; 5167 case llvm::Triple::Win32: 5168 WCharType = UnsignedShort; 5169 break; 5170 case llvm::Triple::Linux: 5171 default: 5172 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 5173 WCharType = UnsignedInt; 5174 break; 5175 } 5176 5177 UseBitFieldTypeAlignment = true; 5178 5179 ZeroLengthBitfieldBoundary = 0; 5180 5181 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 5182 // so set preferred for small types to 32. 5183 if (T.isOSBinFormatMachO()) { 5184 resetDataLayout(BigEndian 5185 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5186 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5187 } else if (T.isOSWindows()) { 5188 assert(!BigEndian && "Windows on ARM does not support big endian"); 5189 resetDataLayout("e" 5190 "-m:w" 5191 "-p:32:32" 5192 "-i64:64" 5193 "-v128:64:128" 5194 "-a:0:32" 5195 "-n32" 5196 "-S64"); 5197 } else if (T.isOSNaCl()) { 5198 assert(!BigEndian && "NaCl on ARM does not support big endian"); 5199 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 5200 } else { 5201 resetDataLayout(BigEndian 5202 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5203 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5204 } 5205 5206 // FIXME: Enumerated types are variable width in straight AAPCS. 5207 } 5208 5209 void setABIAPCS(bool IsAAPCS16) { 5210 const llvm::Triple &T = getTriple(); 5211 5212 IsAAPCS = false; 5213 5214 if (IsAAPCS16) 5215 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5216 else 5217 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 5218 5219 // size_t is unsigned int on FreeBSD. 5220 if (T.getOS() == llvm::Triple::FreeBSD) 5221 SizeType = UnsignedInt; 5222 else 5223 SizeType = UnsignedLong; 5224 5225 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 5226 WCharType = SignedInt; 5227 5228 // Do not respect the alignment of bit-field types when laying out 5229 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 5230 UseBitFieldTypeAlignment = false; 5231 5232 /// gcc forces the alignment to 4 bytes, regardless of the type of the 5233 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 5234 /// gcc. 5235 ZeroLengthBitfieldBoundary = 32; 5236 5237 if (T.isOSBinFormatMachO() && IsAAPCS16) { 5238 assert(!BigEndian && "AAPCS16 does not support big-endian"); 5239 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 5240 } else if (T.isOSBinFormatMachO()) 5241 resetDataLayout( 5242 BigEndian 5243 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5244 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5245 else 5246 resetDataLayout( 5247 BigEndian 5248 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5249 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5250 5251 // FIXME: Override "preferred align" for double and long long. 5252 } 5253 5254 void setArchInfo() { 5255 StringRef ArchName = getTriple().getArchName(); 5256 5257 ArchISA = llvm::ARM::parseArchISA(ArchName); 5258 CPU = llvm::ARM::getDefaultCPU(ArchName); 5259 unsigned AK = llvm::ARM::parseArch(ArchName); 5260 if (AK != llvm::ARM::AK_INVALID) 5261 ArchKind = AK; 5262 setArchInfo(ArchKind); 5263 } 5264 5265 void setArchInfo(unsigned Kind) { 5266 StringRef SubArch; 5267 5268 // cache TargetParser info 5269 ArchKind = Kind; 5270 SubArch = llvm::ARM::getSubArch(ArchKind); 5271 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 5272 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 5273 5274 // cache CPU related strings 5275 CPUAttr = getCPUAttr(); 5276 CPUProfile = getCPUProfile(); 5277 } 5278 5279 void setAtomic() { 5280 // when triple does not specify a sub arch, 5281 // then we are not using inline atomics 5282 bool ShouldUseInlineAtomic = 5283 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 5284 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 5285 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 5286 if (ArchProfile == llvm::ARM::PK_M) { 5287 MaxAtomicPromoteWidth = 32; 5288 if (ShouldUseInlineAtomic) 5289 MaxAtomicInlineWidth = 32; 5290 } 5291 else { 5292 MaxAtomicPromoteWidth = 64; 5293 if (ShouldUseInlineAtomic) 5294 MaxAtomicInlineWidth = 64; 5295 } 5296 } 5297 5298 bool isThumb() const { 5299 return (ArchISA == llvm::ARM::IK_THUMB); 5300 } 5301 5302 bool supportsThumb() const { 5303 return CPUAttr.count('T') || ArchVersion >= 6; 5304 } 5305 5306 bool supportsThumb2() const { 5307 return CPUAttr.equals("6T2") || 5308 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 5309 } 5310 5311 StringRef getCPUAttr() const { 5312 // For most sub-arches, the build attribute CPU name is enough. 5313 // For Cortex variants, it's slightly different. 5314 switch(ArchKind) { 5315 default: 5316 return llvm::ARM::getCPUAttr(ArchKind); 5317 case llvm::ARM::AK_ARMV6M: 5318 return "6M"; 5319 case llvm::ARM::AK_ARMV7S: 5320 return "7S"; 5321 case llvm::ARM::AK_ARMV7A: 5322 return "7A"; 5323 case llvm::ARM::AK_ARMV7R: 5324 return "7R"; 5325 case llvm::ARM::AK_ARMV7M: 5326 return "7M"; 5327 case llvm::ARM::AK_ARMV7EM: 5328 return "7EM"; 5329 case llvm::ARM::AK_ARMV7VE: 5330 return "7VE"; 5331 case llvm::ARM::AK_ARMV8A: 5332 return "8A"; 5333 case llvm::ARM::AK_ARMV8_1A: 5334 return "8_1A"; 5335 case llvm::ARM::AK_ARMV8_2A: 5336 return "8_2A"; 5337 case llvm::ARM::AK_ARMV8MBaseline: 5338 return "8M_BASE"; 5339 case llvm::ARM::AK_ARMV8MMainline: 5340 return "8M_MAIN"; 5341 case llvm::ARM::AK_ARMV8R: 5342 return "8R"; 5343 } 5344 } 5345 5346 StringRef getCPUProfile() const { 5347 switch(ArchProfile) { 5348 case llvm::ARM::PK_A: 5349 return "A"; 5350 case llvm::ARM::PK_R: 5351 return "R"; 5352 case llvm::ARM::PK_M: 5353 return "M"; 5354 default: 5355 return ""; 5356 } 5357 } 5358 5359 public: 5360 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5361 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 5362 HW_FP(0) { 5363 5364 switch (getTriple().getOS()) { 5365 case llvm::Triple::NetBSD: 5366 case llvm::Triple::OpenBSD: 5367 PtrDiffType = SignedLong; 5368 break; 5369 default: 5370 PtrDiffType = SignedInt; 5371 break; 5372 } 5373 5374 // Cache arch related info. 5375 setArchInfo(); 5376 5377 // {} in inline assembly are neon specifiers, not assembly variant 5378 // specifiers. 5379 NoAsmVariants = true; 5380 5381 // FIXME: This duplicates code from the driver that sets the -target-abi 5382 // option - this code is used if -target-abi isn't passed and should 5383 // be unified in some way. 5384 if (Triple.isOSBinFormatMachO()) { 5385 // The backend is hardwired to assume AAPCS for M-class processors, ensure 5386 // the frontend matches that. 5387 if (Triple.getEnvironment() == llvm::Triple::EABI || 5388 Triple.getOS() == llvm::Triple::UnknownOS || 5389 ArchProfile == llvm::ARM::PK_M) { 5390 setABI("aapcs"); 5391 } else if (Triple.isWatchABI()) { 5392 setABI("aapcs16"); 5393 } else { 5394 setABI("apcs-gnu"); 5395 } 5396 } else if (Triple.isOSWindows()) { 5397 // FIXME: this is invalid for WindowsCE 5398 setABI("aapcs"); 5399 } else { 5400 // Select the default based on the platform. 5401 switch (Triple.getEnvironment()) { 5402 case llvm::Triple::Android: 5403 case llvm::Triple::GNUEABI: 5404 case llvm::Triple::GNUEABIHF: 5405 case llvm::Triple::MuslEABI: 5406 case llvm::Triple::MuslEABIHF: 5407 setABI("aapcs-linux"); 5408 break; 5409 case llvm::Triple::EABIHF: 5410 case llvm::Triple::EABI: 5411 setABI("aapcs"); 5412 break; 5413 case llvm::Triple::GNU: 5414 setABI("apcs-gnu"); 5415 break; 5416 default: 5417 if (Triple.getOS() == llvm::Triple::NetBSD) 5418 setABI("apcs-gnu"); 5419 else if (Triple.getOS() == llvm::Triple::OpenBSD) 5420 setABI("aapcs-linux"); 5421 else 5422 setABI("aapcs"); 5423 break; 5424 } 5425 } 5426 5427 // ARM targets default to using the ARM C++ ABI. 5428 TheCXXABI.set(TargetCXXABI::GenericARM); 5429 5430 // ARM has atomics up to 8 bytes 5431 setAtomic(); 5432 5433 // Maximum alignment for ARM NEON data types should be 64-bits (AAPCS) 5434 if (IsAAPCS && (Triple.getEnvironment() != llvm::Triple::Android)) 5435 MaxVectorAlign = 64; 5436 5437 // Do force alignment of members that follow zero length bitfields. If 5438 // the alignment of the zero-length bitfield is greater than the member 5439 // that follows it, `bar', `bar' will be aligned as the type of the 5440 // zero length bitfield. 5441 UseZeroLengthBitfieldAlignment = true; 5442 5443 if (Triple.getOS() == llvm::Triple::Linux || 5444 Triple.getOS() == llvm::Triple::UnknownOS) 5445 this->MCountName = 5446 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 5447 } 5448 5449 StringRef getABI() const override { return ABI; } 5450 5451 bool setABI(const std::string &Name) override { 5452 ABI = Name; 5453 5454 // The defaults (above) are for AAPCS, check if we need to change them. 5455 // 5456 // FIXME: We need support for -meabi... we could just mangle it into the 5457 // name. 5458 if (Name == "apcs-gnu" || Name == "aapcs16") { 5459 setABIAPCS(Name == "aapcs16"); 5460 return true; 5461 } 5462 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 5463 setABIAAPCS(); 5464 return true; 5465 } 5466 return false; 5467 } 5468 5469 // FIXME: This should be based on Arch attributes, not CPU names. 5470 bool 5471 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5472 StringRef CPU, 5473 const std::vector<std::string> &FeaturesVec) const override { 5474 5475 std::vector<StringRef> TargetFeatures; 5476 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 5477 5478 // get default FPU features 5479 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 5480 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 5481 5482 // get default Extension features 5483 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 5484 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 5485 5486 for (auto Feature : TargetFeatures) 5487 if (Feature[0] == '+') 5488 Features[Feature.drop_front(1)] = true; 5489 5490 // Enable or disable thumb-mode explicitly per function to enable mixed 5491 // ARM and Thumb code generation. 5492 if (isThumb()) 5493 Features["thumb-mode"] = true; 5494 else 5495 Features["thumb-mode"] = false; 5496 5497 // Convert user-provided arm and thumb GNU target attributes to 5498 // [-|+]thumb-mode target features respectively. 5499 std::vector<std::string> UpdatedFeaturesVec(FeaturesVec); 5500 for (auto &Feature : UpdatedFeaturesVec) { 5501 if (Feature.compare("+arm") == 0) 5502 Feature = "-thumb-mode"; 5503 else if (Feature.compare("+thumb") == 0) 5504 Feature = "+thumb-mode"; 5505 } 5506 5507 return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec); 5508 } 5509 5510 bool handleTargetFeatures(std::vector<std::string> &Features, 5511 DiagnosticsEngine &Diags) override { 5512 FPU = 0; 5513 CRC = 0; 5514 Crypto = 0; 5515 DSP = 0; 5516 Unaligned = 1; 5517 SoftFloat = SoftFloatABI = false; 5518 HWDiv = 0; 5519 5520 // This does not diagnose illegal cases like having both 5521 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5522 uint32_t HW_FP_remove = 0; 5523 for (const auto &Feature : Features) { 5524 if (Feature == "+soft-float") { 5525 SoftFloat = true; 5526 } else if (Feature == "+soft-float-abi") { 5527 SoftFloatABI = true; 5528 } else if (Feature == "+vfp2") { 5529 FPU |= VFP2FPU; 5530 HW_FP |= HW_FP_SP | HW_FP_DP; 5531 } else if (Feature == "+vfp3") { 5532 FPU |= VFP3FPU; 5533 HW_FP |= HW_FP_SP | HW_FP_DP; 5534 } else if (Feature == "+vfp4") { 5535 FPU |= VFP4FPU; 5536 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5537 } else if (Feature == "+fp-armv8") { 5538 FPU |= FPARMV8; 5539 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5540 } else if (Feature == "+neon") { 5541 FPU |= NeonFPU; 5542 HW_FP |= HW_FP_SP | HW_FP_DP; 5543 } else if (Feature == "+hwdiv") { 5544 HWDiv |= HWDivThumb; 5545 } else if (Feature == "+hwdiv-arm") { 5546 HWDiv |= HWDivARM; 5547 } else if (Feature == "+crc") { 5548 CRC = 1; 5549 } else if (Feature == "+crypto") { 5550 Crypto = 1; 5551 } else if (Feature == "+dsp") { 5552 DSP = 1; 5553 } else if (Feature == "+fp-only-sp") { 5554 HW_FP_remove |= HW_FP_DP; 5555 } else if (Feature == "+strict-align") { 5556 Unaligned = 0; 5557 } else if (Feature == "+fp16") { 5558 HW_FP |= HW_FP_HP; 5559 } 5560 } 5561 HW_FP &= ~HW_FP_remove; 5562 5563 switch (ArchVersion) { 5564 case 6: 5565 if (ArchProfile == llvm::ARM::PK_M) 5566 LDREX = 0; 5567 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5568 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5569 else 5570 LDREX = LDREX_W; 5571 break; 5572 case 7: 5573 if (ArchProfile == llvm::ARM::PK_M) 5574 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5575 else 5576 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5577 break; 5578 case 8: 5579 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5580 } 5581 5582 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5583 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5584 return false; 5585 } 5586 5587 if (FPMath == FP_Neon) 5588 Features.push_back("+neonfp"); 5589 else if (FPMath == FP_VFP) 5590 Features.push_back("-neonfp"); 5591 5592 // Remove front-end specific options which the backend handles differently. 5593 auto Feature = 5594 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5595 if (Feature != Features.end()) 5596 Features.erase(Feature); 5597 5598 return true; 5599 } 5600 5601 bool hasFeature(StringRef Feature) const override { 5602 return llvm::StringSwitch<bool>(Feature) 5603 .Case("arm", true) 5604 .Case("aarch32", true) 5605 .Case("softfloat", SoftFloat) 5606 .Case("thumb", isThumb()) 5607 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5608 .Case("vfp", FPU && !SoftFloat) 5609 .Case("hwdiv", HWDiv & HWDivThumb) 5610 .Case("hwdiv-arm", HWDiv & HWDivARM) 5611 .Default(false); 5612 } 5613 5614 bool setCPU(const std::string &Name) override { 5615 if (Name != "generic") 5616 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5617 5618 if (ArchKind == llvm::ARM::AK_INVALID) 5619 return false; 5620 setAtomic(); 5621 CPU = Name; 5622 return true; 5623 } 5624 5625 bool setFPMath(StringRef Name) override; 5626 5627 void getTargetDefinesARMV81A(const LangOptions &Opts, 5628 MacroBuilder &Builder) const { 5629 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5630 } 5631 5632 void getTargetDefinesARMV82A(const LangOptions &Opts, 5633 MacroBuilder &Builder) const { 5634 // Also include the ARMv8.1-A defines 5635 getTargetDefinesARMV81A(Opts, Builder); 5636 } 5637 5638 void getTargetDefines(const LangOptions &Opts, 5639 MacroBuilder &Builder) const override { 5640 // Target identification. 5641 Builder.defineMacro("__arm"); 5642 Builder.defineMacro("__arm__"); 5643 // For bare-metal none-eabi. 5644 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5645 (getTriple().getEnvironment() == llvm::Triple::EABI || 5646 getTriple().getEnvironment() == llvm::Triple::EABIHF)) 5647 Builder.defineMacro("__ELF__"); 5648 5649 5650 // Target properties. 5651 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5652 5653 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5654 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5655 if (getTriple().isWatchABI()) 5656 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5657 5658 if (!CPUAttr.empty()) 5659 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5660 5661 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5662 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5663 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5664 5665 if (ArchVersion >= 8) { 5666 // ACLE 6.5.7 Crypto Extension 5667 if (Crypto) 5668 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5669 // ACLE 6.5.8 CRC32 Extension 5670 if (CRC) 5671 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5672 // ACLE 6.5.10 Numeric Maximum and Minimum 5673 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5674 // ACLE 6.5.9 Directed Rounding 5675 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5676 } 5677 5678 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5679 // is not defined for the M-profile. 5680 // NOTE that the default profile is assumed to be 'A' 5681 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5682 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5683 5684 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5685 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5686 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5687 // v7 and v8 architectures excluding v8-M Baseline. 5688 if (supportsThumb2()) 5689 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5690 else if (supportsThumb()) 5691 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5692 5693 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5694 // instruction set such as ARM or Thumb. 5695 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5696 5697 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5698 5699 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5700 if (!CPUProfile.empty()) 5701 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5702 5703 // ACLE 6.4.3 Unaligned access supported in hardware 5704 if (Unaligned) 5705 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5706 5707 // ACLE 6.4.4 LDREX/STREX 5708 if (LDREX) 5709 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5710 5711 // ACLE 6.4.5 CLZ 5712 if (ArchVersion == 5 || 5713 (ArchVersion == 6 && CPUProfile != "M") || 5714 ArchVersion > 6) 5715 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5716 5717 // ACLE 6.5.1 Hardware Floating Point 5718 if (HW_FP) 5719 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5720 5721 // ACLE predefines. 5722 Builder.defineMacro("__ARM_ACLE", "200"); 5723 5724 // FP16 support (we currently only support IEEE format). 5725 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5726 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5727 5728 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5729 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5730 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5731 5732 // Subtarget options. 5733 5734 // FIXME: It's more complicated than this and we don't really support 5735 // interworking. 5736 // Windows on ARM does not "support" interworking 5737 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5738 Builder.defineMacro("__THUMB_INTERWORK__"); 5739 5740 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5741 // Embedded targets on Darwin follow AAPCS, but not EABI. 5742 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5743 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5744 Builder.defineMacro("__ARM_EABI__"); 5745 Builder.defineMacro("__ARM_PCS", "1"); 5746 } 5747 5748 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5749 ABI == "aapcs16") 5750 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5751 5752 if (SoftFloat) 5753 Builder.defineMacro("__SOFTFP__"); 5754 5755 if (ArchKind == llvm::ARM::AK_XSCALE) 5756 Builder.defineMacro("__XSCALE__"); 5757 5758 if (isThumb()) { 5759 Builder.defineMacro("__THUMBEL__"); 5760 Builder.defineMacro("__thumb__"); 5761 if (supportsThumb2()) 5762 Builder.defineMacro("__thumb2__"); 5763 } 5764 5765 // ACLE 6.4.9 32-bit SIMD instructions 5766 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5767 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5768 5769 // ACLE 6.4.10 Hardware Integer Divide 5770 if (((HWDiv & HWDivThumb) && isThumb()) || 5771 ((HWDiv & HWDivARM) && !isThumb())) { 5772 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5773 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5774 } 5775 5776 // Note, this is always on in gcc, even though it doesn't make sense. 5777 Builder.defineMacro("__APCS_32__"); 5778 5779 if (FPUModeIsVFP((FPUMode) FPU)) { 5780 Builder.defineMacro("__VFP_FP__"); 5781 if (FPU & VFP2FPU) 5782 Builder.defineMacro("__ARM_VFPV2__"); 5783 if (FPU & VFP3FPU) 5784 Builder.defineMacro("__ARM_VFPV3__"); 5785 if (FPU & VFP4FPU) 5786 Builder.defineMacro("__ARM_VFPV4__"); 5787 if (FPU & FPARMV8) 5788 Builder.defineMacro("__ARM_FPV5__"); 5789 } 5790 5791 // This only gets set when Neon instructions are actually available, unlike 5792 // the VFP define, hence the soft float and arch check. This is subtly 5793 // different from gcc, we follow the intent which was that it should be set 5794 // when Neon instructions are actually available. 5795 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5796 Builder.defineMacro("__ARM_NEON", "1"); 5797 Builder.defineMacro("__ARM_NEON__"); 5798 // current AArch32 NEON implementations do not support double-precision 5799 // floating-point even when it is present in VFP. 5800 Builder.defineMacro("__ARM_NEON_FP", 5801 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5802 } 5803 5804 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5805 Opts.ShortWChar ? "2" : "4"); 5806 5807 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5808 Opts.ShortEnums ? "1" : "4"); 5809 5810 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5811 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5812 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5813 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5814 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5815 } 5816 5817 // ACLE 6.4.7 DSP instructions 5818 if (DSP) { 5819 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5820 } 5821 5822 // ACLE 6.4.8 Saturation instructions 5823 bool SAT = false; 5824 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5825 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5826 SAT = true; 5827 } 5828 5829 // ACLE 6.4.6 Q (saturation) flag 5830 if (DSP || SAT) 5831 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5832 5833 if (Opts.UnsafeFPMath) 5834 Builder.defineMacro("__ARM_FP_FAST", "1"); 5835 5836 switch(ArchKind) { 5837 default: break; 5838 case llvm::ARM::AK_ARMV8_1A: 5839 getTargetDefinesARMV81A(Opts, Builder); 5840 break; 5841 case llvm::ARM::AK_ARMV8_2A: 5842 getTargetDefinesARMV82A(Opts, Builder); 5843 break; 5844 } 5845 } 5846 5847 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5848 return llvm::makeArrayRef(BuiltinInfo, 5849 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5850 } 5851 bool isCLZForZeroUndef() const override { return false; } 5852 BuiltinVaListKind getBuiltinVaListKind() const override { 5853 return IsAAPCS 5854 ? AAPCSABIBuiltinVaList 5855 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5856 : TargetInfo::VoidPtrBuiltinVaList); 5857 } 5858 ArrayRef<const char *> getGCCRegNames() const override; 5859 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5860 bool validateAsmConstraint(const char *&Name, 5861 TargetInfo::ConstraintInfo &Info) const override { 5862 switch (*Name) { 5863 default: break; 5864 case 'l': // r0-r7 5865 case 'h': // r8-r15 5866 case 't': // VFP Floating point register single precision 5867 case 'w': // VFP Floating point register double precision 5868 Info.setAllowsRegister(); 5869 return true; 5870 case 'I': 5871 case 'J': 5872 case 'K': 5873 case 'L': 5874 case 'M': 5875 // FIXME 5876 return true; 5877 case 'Q': // A memory address that is a single base register. 5878 Info.setAllowsMemory(); 5879 return true; 5880 case 'U': // a memory reference... 5881 switch (Name[1]) { 5882 case 'q': // ...ARMV4 ldrsb 5883 case 'v': // ...VFP load/store (reg+constant offset) 5884 case 'y': // ...iWMMXt load/store 5885 case 't': // address valid for load/store opaque types wider 5886 // than 128-bits 5887 case 'n': // valid address for Neon doubleword vector load/store 5888 case 'm': // valid address for Neon element and structure load/store 5889 case 's': // valid address for non-offset loads/stores of quad-word 5890 // values in four ARM registers 5891 Info.setAllowsMemory(); 5892 Name++; 5893 return true; 5894 } 5895 } 5896 return false; 5897 } 5898 std::string convertConstraint(const char *&Constraint) const override { 5899 std::string R; 5900 switch (*Constraint) { 5901 case 'U': // Two-character constraint; add "^" hint for later parsing. 5902 R = std::string("^") + std::string(Constraint, 2); 5903 Constraint++; 5904 break; 5905 case 'p': // 'p' should be translated to 'r' by default. 5906 R = std::string("r"); 5907 break; 5908 default: 5909 return std::string(1, *Constraint); 5910 } 5911 return R; 5912 } 5913 bool 5914 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5915 std::string &SuggestedModifier) const override { 5916 bool isOutput = (Constraint[0] == '='); 5917 bool isInOut = (Constraint[0] == '+'); 5918 5919 // Strip off constraint modifiers. 5920 while (Constraint[0] == '=' || 5921 Constraint[0] == '+' || 5922 Constraint[0] == '&') 5923 Constraint = Constraint.substr(1); 5924 5925 switch (Constraint[0]) { 5926 default: break; 5927 case 'r': { 5928 switch (Modifier) { 5929 default: 5930 return (isInOut || isOutput || Size <= 64); 5931 case 'q': 5932 // A register of size 32 cannot fit a vector type. 5933 return false; 5934 } 5935 } 5936 } 5937 5938 return true; 5939 } 5940 const char *getClobbers() const override { 5941 // FIXME: Is this really right? 5942 return ""; 5943 } 5944 5945 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5946 switch (CC) { 5947 case CC_AAPCS: 5948 case CC_AAPCS_VFP: 5949 case CC_Swift: 5950 case CC_OpenCLKernel: 5951 return CCCR_OK; 5952 default: 5953 return CCCR_Warning; 5954 } 5955 } 5956 5957 int getEHDataRegisterNumber(unsigned RegNo) const override { 5958 if (RegNo == 0) return 0; 5959 if (RegNo == 1) return 1; 5960 return -1; 5961 } 5962 5963 bool hasSjLjLowering() const override { 5964 return true; 5965 } 5966 }; 5967 5968 bool ARMTargetInfo::setFPMath(StringRef Name) { 5969 if (Name == "neon") { 5970 FPMath = FP_Neon; 5971 return true; 5972 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5973 Name == "vfp4") { 5974 FPMath = FP_VFP; 5975 return true; 5976 } 5977 return false; 5978 } 5979 5980 const char * const ARMTargetInfo::GCCRegNames[] = { 5981 // Integer registers 5982 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5983 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5984 5985 // Float registers 5986 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5987 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5988 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5989 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5990 5991 // Double registers 5992 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5993 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5994 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5995 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5996 5997 // Quad registers 5998 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5999 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 6000 }; 6001 6002 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 6003 return llvm::makeArrayRef(GCCRegNames); 6004 } 6005 6006 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 6007 { { "a1" }, "r0" }, 6008 { { "a2" }, "r1" }, 6009 { { "a3" }, "r2" }, 6010 { { "a4" }, "r3" }, 6011 { { "v1" }, "r4" }, 6012 { { "v2" }, "r5" }, 6013 { { "v3" }, "r6" }, 6014 { { "v4" }, "r7" }, 6015 { { "v5" }, "r8" }, 6016 { { "v6", "rfp" }, "r9" }, 6017 { { "sl" }, "r10" }, 6018 { { "fp" }, "r11" }, 6019 { { "ip" }, "r12" }, 6020 { { "r13" }, "sp" }, 6021 { { "r14" }, "lr" }, 6022 { { "r15" }, "pc" }, 6023 // The S, D and Q registers overlap, but aren't really aliases; we 6024 // don't want to substitute one of these for a different-sized one. 6025 }; 6026 6027 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 6028 return llvm::makeArrayRef(GCCRegAliases); 6029 } 6030 6031 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 6032 #define BUILTIN(ID, TYPE, ATTRS) \ 6033 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6034 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6035 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6036 #include "clang/Basic/BuiltinsNEON.def" 6037 6038 #define BUILTIN(ID, TYPE, ATTRS) \ 6039 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6040 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 6041 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 6042 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6043 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6044 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 6045 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 6046 #include "clang/Basic/BuiltinsARM.def" 6047 }; 6048 6049 class ARMleTargetInfo : public ARMTargetInfo { 6050 public: 6051 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6052 : ARMTargetInfo(Triple, Opts) {} 6053 void getTargetDefines(const LangOptions &Opts, 6054 MacroBuilder &Builder) const override { 6055 Builder.defineMacro("__ARMEL__"); 6056 ARMTargetInfo::getTargetDefines(Opts, Builder); 6057 } 6058 }; 6059 6060 class ARMbeTargetInfo : public ARMTargetInfo { 6061 public: 6062 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6063 : ARMTargetInfo(Triple, Opts) {} 6064 void getTargetDefines(const LangOptions &Opts, 6065 MacroBuilder &Builder) const override { 6066 Builder.defineMacro("__ARMEB__"); 6067 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6068 ARMTargetInfo::getTargetDefines(Opts, Builder); 6069 } 6070 }; 6071 6072 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 6073 const llvm::Triple Triple; 6074 public: 6075 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6076 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 6077 WCharType = UnsignedShort; 6078 SizeType = UnsignedInt; 6079 } 6080 void getVisualStudioDefines(const LangOptions &Opts, 6081 MacroBuilder &Builder) const { 6082 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 6083 6084 // FIXME: this is invalid for WindowsCE 6085 Builder.defineMacro("_M_ARM_NT", "1"); 6086 Builder.defineMacro("_M_ARMT", "_M_ARM"); 6087 Builder.defineMacro("_M_THUMB", "_M_ARM"); 6088 6089 assert((Triple.getArch() == llvm::Triple::arm || 6090 Triple.getArch() == llvm::Triple::thumb) && 6091 "invalid architecture for Windows ARM target info"); 6092 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 6093 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 6094 6095 // TODO map the complete set of values 6096 // 31: VFPv3 40: VFPv4 6097 Builder.defineMacro("_M_ARM_FP", "31"); 6098 } 6099 BuiltinVaListKind getBuiltinVaListKind() const override { 6100 return TargetInfo::CharPtrBuiltinVaList; 6101 } 6102 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6103 switch (CC) { 6104 case CC_X86StdCall: 6105 case CC_X86ThisCall: 6106 case CC_X86FastCall: 6107 case CC_X86VectorCall: 6108 return CCCR_Ignore; 6109 case CC_C: 6110 case CC_OpenCLKernel: 6111 return CCCR_OK; 6112 default: 6113 return CCCR_Warning; 6114 } 6115 } 6116 }; 6117 6118 // Windows ARM + Itanium C++ ABI Target 6119 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 6120 public: 6121 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 6122 const TargetOptions &Opts) 6123 : WindowsARMTargetInfo(Triple, Opts) { 6124 TheCXXABI.set(TargetCXXABI::GenericARM); 6125 } 6126 6127 void getTargetDefines(const LangOptions &Opts, 6128 MacroBuilder &Builder) const override { 6129 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6130 6131 if (Opts.MSVCCompat) 6132 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 6133 } 6134 }; 6135 6136 // Windows ARM, MS (C++) ABI 6137 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 6138 public: 6139 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 6140 const TargetOptions &Opts) 6141 : WindowsARMTargetInfo(Triple, Opts) { 6142 TheCXXABI.set(TargetCXXABI::Microsoft); 6143 } 6144 6145 void getTargetDefines(const LangOptions &Opts, 6146 MacroBuilder &Builder) const override { 6147 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6148 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 6149 } 6150 }; 6151 6152 // ARM MinGW target 6153 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 6154 public: 6155 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6156 : WindowsARMTargetInfo(Triple, Opts) { 6157 TheCXXABI.set(TargetCXXABI::GenericARM); 6158 } 6159 6160 void getTargetDefines(const LangOptions &Opts, 6161 MacroBuilder &Builder) const override { 6162 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6163 DefineStd(Builder, "WIN32", Opts); 6164 DefineStd(Builder, "WINNT", Opts); 6165 Builder.defineMacro("_ARM_"); 6166 addMinGWDefines(Opts, Builder); 6167 } 6168 }; 6169 6170 // ARM Cygwin target 6171 class CygwinARMTargetInfo : public ARMleTargetInfo { 6172 public: 6173 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6174 : ARMleTargetInfo(Triple, Opts) { 6175 TLSSupported = false; 6176 WCharType = UnsignedShort; 6177 DoubleAlign = LongLongAlign = 64; 6178 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 6179 } 6180 void getTargetDefines(const LangOptions &Opts, 6181 MacroBuilder &Builder) const override { 6182 ARMleTargetInfo::getTargetDefines(Opts, Builder); 6183 Builder.defineMacro("_ARM_"); 6184 Builder.defineMacro("__CYGWIN__"); 6185 Builder.defineMacro("__CYGWIN32__"); 6186 DefineStd(Builder, "unix", Opts); 6187 if (Opts.CPlusPlus) 6188 Builder.defineMacro("_GNU_SOURCE"); 6189 } 6190 }; 6191 6192 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 6193 protected: 6194 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6195 MacroBuilder &Builder) const override { 6196 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6197 } 6198 6199 public: 6200 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6201 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 6202 HasAlignMac68kSupport = true; 6203 // iOS always has 64-bit atomic instructions. 6204 // FIXME: This should be based off of the target features in 6205 // ARMleTargetInfo. 6206 MaxAtomicInlineWidth = 64; 6207 6208 if (Triple.isWatchABI()) { 6209 // Darwin on iOS uses a variant of the ARM C++ ABI. 6210 TheCXXABI.set(TargetCXXABI::WatchOS); 6211 6212 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 6213 // size_t is long, it's a bit weird for it to be int. 6214 PtrDiffType = SignedLong; 6215 6216 // BOOL should be a real boolean on the new ABI 6217 UseSignedCharForObjCBool = false; 6218 } else 6219 TheCXXABI.set(TargetCXXABI::iOS); 6220 } 6221 }; 6222 6223 class AArch64TargetInfo : public TargetInfo { 6224 virtual void setDataLayout() = 0; 6225 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6226 static const char *const GCCRegNames[]; 6227 6228 enum FPUModeEnum { 6229 FPUMode, 6230 NeonMode 6231 }; 6232 6233 unsigned FPU; 6234 unsigned CRC; 6235 unsigned Crypto; 6236 unsigned Unaligned; 6237 unsigned HasFullFP16; 6238 llvm::AArch64::ArchKind ArchKind; 6239 6240 static const Builtin::Info BuiltinInfo[]; 6241 6242 std::string ABI; 6243 6244 public: 6245 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6246 : TargetInfo(Triple), ABI("aapcs") { 6247 if (getTriple().getOS() == llvm::Triple::NetBSD || 6248 getTriple().getOS() == llvm::Triple::OpenBSD) { 6249 WCharType = SignedInt; 6250 6251 // NetBSD apparently prefers consistency across ARM targets to consistency 6252 // across 64-bit targets. 6253 Int64Type = SignedLongLong; 6254 IntMaxType = SignedLongLong; 6255 } else { 6256 WCharType = UnsignedInt; 6257 Int64Type = SignedLong; 6258 IntMaxType = SignedLong; 6259 } 6260 6261 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6262 MaxVectorAlign = 128; 6263 MaxAtomicInlineWidth = 128; 6264 MaxAtomicPromoteWidth = 128; 6265 6266 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 6267 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 6268 6269 // {} in inline assembly are neon specifiers, not assembly variant 6270 // specifiers. 6271 NoAsmVariants = true; 6272 6273 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 6274 // contributes to the alignment of the containing aggregate in the same way 6275 // a plain (non bit-field) member of that type would, without exception for 6276 // zero-sized or anonymous bit-fields." 6277 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 6278 UseZeroLengthBitfieldAlignment = true; 6279 6280 // AArch64 targets default to using the ARM C++ ABI. 6281 TheCXXABI.set(TargetCXXABI::GenericAArch64); 6282 6283 if (Triple.getOS() == llvm::Triple::Linux) 6284 this->MCountName = "\01_mcount"; 6285 else if (Triple.getOS() == llvm::Triple::UnknownOS) 6286 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 6287 } 6288 6289 StringRef getABI() const override { return ABI; } 6290 bool setABI(const std::string &Name) override { 6291 if (Name != "aapcs" && Name != "darwinpcs") 6292 return false; 6293 6294 ABI = Name; 6295 return true; 6296 } 6297 6298 bool setCPU(const std::string &Name) override { 6299 return Name == "generic" || 6300 llvm::AArch64::parseCPUArch(Name) != 6301 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 6302 } 6303 6304 void getTargetDefinesARMV81A(const LangOptions &Opts, 6305 MacroBuilder &Builder) const { 6306 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 6307 } 6308 6309 void getTargetDefinesARMV82A(const LangOptions &Opts, 6310 MacroBuilder &Builder) const { 6311 // Also include the ARMv8.1 defines 6312 getTargetDefinesARMV81A(Opts, Builder); 6313 6314 if (FPU == NeonMode && HasFullFP16) 6315 Builder.defineMacro("__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", "1"); 6316 } 6317 6318 void getTargetDefines(const LangOptions &Opts, 6319 MacroBuilder &Builder) const override { 6320 // Target identification. 6321 Builder.defineMacro("__aarch64__"); 6322 // For bare-metal none-eabi. 6323 if (getTriple().getOS() == llvm::Triple::UnknownOS && 6324 (getTriple().getEnvironment() == llvm::Triple::EABI || 6325 getTriple().getEnvironment() == llvm::Triple::EABIHF)) 6326 Builder.defineMacro("__ELF__"); 6327 6328 // Target properties. 6329 Builder.defineMacro("_LP64"); 6330 Builder.defineMacro("__LP64__"); 6331 6332 // ACLE predefines. Many can only have one possible value on v8 AArch64. 6333 Builder.defineMacro("__ARM_ACLE", "200"); 6334 Builder.defineMacro("__ARM_ARCH", "8"); 6335 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 6336 6337 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 6338 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 6339 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 6340 6341 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 6342 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 6343 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 6344 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 6345 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 6346 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 6347 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 6348 6349 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 6350 6351 // 0xe implies support for half, single and double precision operations. 6352 Builder.defineMacro("__ARM_FP", "0xE"); 6353 6354 // PCS specifies this for SysV variants, which is all we support. Other ABIs 6355 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 6356 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 6357 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 6358 6359 if (Opts.UnsafeFPMath) 6360 Builder.defineMacro("__ARM_FP_FAST", "1"); 6361 6362 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 6363 6364 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 6365 Opts.ShortEnums ? "1" : "4"); 6366 6367 if (FPU == NeonMode) { 6368 Builder.defineMacro("__ARM_NEON", "1"); 6369 // 64-bit NEON supports half, single and double precision operations. 6370 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 6371 } 6372 6373 if (CRC) 6374 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 6375 6376 if (Crypto) 6377 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 6378 6379 if (Unaligned) 6380 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 6381 6382 switch(ArchKind) { 6383 default: break; 6384 case llvm::AArch64::ArchKind::AK_ARMV8_1A: 6385 getTargetDefinesARMV81A(Opts, Builder); 6386 break; 6387 case llvm::AArch64::ArchKind::AK_ARMV8_2A: 6388 getTargetDefinesARMV82A(Opts, Builder); 6389 break; 6390 } 6391 6392 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 6393 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6394 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6395 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6396 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6397 } 6398 6399 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6400 return llvm::makeArrayRef(BuiltinInfo, 6401 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 6402 } 6403 6404 bool hasFeature(StringRef Feature) const override { 6405 return Feature == "aarch64" || 6406 Feature == "arm64" || 6407 Feature == "arm" || 6408 (Feature == "neon" && FPU == NeonMode); 6409 } 6410 6411 bool handleTargetFeatures(std::vector<std::string> &Features, 6412 DiagnosticsEngine &Diags) override { 6413 FPU = FPUMode; 6414 CRC = 0; 6415 Crypto = 0; 6416 Unaligned = 1; 6417 HasFullFP16 = 0; 6418 ArchKind = llvm::AArch64::ArchKind::AK_ARMV8A; 6419 6420 for (const auto &Feature : Features) { 6421 if (Feature == "+neon") 6422 FPU = NeonMode; 6423 if (Feature == "+crc") 6424 CRC = 1; 6425 if (Feature == "+crypto") 6426 Crypto = 1; 6427 if (Feature == "+strict-align") 6428 Unaligned = 0; 6429 if (Feature == "+v8.1a") 6430 ArchKind = llvm::AArch64::ArchKind::AK_ARMV8_1A; 6431 if (Feature == "+v8.2a") 6432 ArchKind = llvm::AArch64::ArchKind::AK_ARMV8_2A; 6433 if (Feature == "+fullfp16") 6434 HasFullFP16 = 1; 6435 } 6436 6437 setDataLayout(); 6438 6439 return true; 6440 } 6441 6442 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6443 switch (CC) { 6444 case CC_C: 6445 case CC_Swift: 6446 case CC_PreserveMost: 6447 case CC_PreserveAll: 6448 case CC_OpenCLKernel: 6449 return CCCR_OK; 6450 default: 6451 return CCCR_Warning; 6452 } 6453 } 6454 6455 bool isCLZForZeroUndef() const override { return false; } 6456 6457 BuiltinVaListKind getBuiltinVaListKind() const override { 6458 return TargetInfo::AArch64ABIBuiltinVaList; 6459 } 6460 6461 ArrayRef<const char *> getGCCRegNames() const override; 6462 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6463 6464 bool validateAsmConstraint(const char *&Name, 6465 TargetInfo::ConstraintInfo &Info) const override { 6466 switch (*Name) { 6467 default: 6468 return false; 6469 case 'w': // Floating point and SIMD registers (V0-V31) 6470 Info.setAllowsRegister(); 6471 return true; 6472 case 'I': // Constant that can be used with an ADD instruction 6473 case 'J': // Constant that can be used with a SUB instruction 6474 case 'K': // Constant that can be used with a 32-bit logical instruction 6475 case 'L': // Constant that can be used with a 64-bit logical instruction 6476 case 'M': // Constant that can be used as a 32-bit MOV immediate 6477 case 'N': // Constant that can be used as a 64-bit MOV immediate 6478 case 'Y': // Floating point constant zero 6479 case 'Z': // Integer constant zero 6480 return true; 6481 case 'Q': // A memory reference with base register and no offset 6482 Info.setAllowsMemory(); 6483 return true; 6484 case 'S': // A symbolic address 6485 Info.setAllowsRegister(); 6486 return true; 6487 case 'U': 6488 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 6489 // Utf: A memory address suitable for ldp/stp in TF mode. 6490 // Usa: An absolute symbolic address. 6491 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 6492 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 6493 case 'z': // Zero register, wzr or xzr 6494 Info.setAllowsRegister(); 6495 return true; 6496 case 'x': // Floating point and SIMD registers (V0-V15) 6497 Info.setAllowsRegister(); 6498 return true; 6499 } 6500 return false; 6501 } 6502 6503 bool 6504 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 6505 std::string &SuggestedModifier) const override { 6506 // Strip off constraint modifiers. 6507 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 6508 Constraint = Constraint.substr(1); 6509 6510 switch (Constraint[0]) { 6511 default: 6512 return true; 6513 case 'z': 6514 case 'r': { 6515 switch (Modifier) { 6516 case 'x': 6517 case 'w': 6518 // For now assume that the person knows what they're 6519 // doing with the modifier. 6520 return true; 6521 default: 6522 // By default an 'r' constraint will be in the 'x' 6523 // registers. 6524 if (Size == 64) 6525 return true; 6526 6527 SuggestedModifier = "w"; 6528 return false; 6529 } 6530 } 6531 } 6532 } 6533 6534 const char *getClobbers() const override { return ""; } 6535 6536 int getEHDataRegisterNumber(unsigned RegNo) const override { 6537 if (RegNo == 0) 6538 return 0; 6539 if (RegNo == 1) 6540 return 1; 6541 return -1; 6542 } 6543 }; 6544 6545 const char *const AArch64TargetInfo::GCCRegNames[] = { 6546 // 32-bit Integer registers 6547 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 6548 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 6549 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 6550 6551 // 64-bit Integer registers 6552 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 6553 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 6554 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 6555 6556 // 32-bit floating point regsisters 6557 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 6558 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 6559 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6560 6561 // 64-bit floating point regsisters 6562 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 6563 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 6564 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6565 6566 // Vector registers 6567 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6568 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6569 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6570 }; 6571 6572 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6573 return llvm::makeArrayRef(GCCRegNames); 6574 } 6575 6576 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6577 { { "w31" }, "wsp" }, 6578 { { "x29" }, "fp" }, 6579 { { "x30" }, "lr" }, 6580 { { "x31" }, "sp" }, 6581 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6582 // don't want to substitute one of these for a different-sized one. 6583 }; 6584 6585 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6586 return llvm::makeArrayRef(GCCRegAliases); 6587 } 6588 6589 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6590 #define BUILTIN(ID, TYPE, ATTRS) \ 6591 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6592 #include "clang/Basic/BuiltinsNEON.def" 6593 6594 #define BUILTIN(ID, TYPE, ATTRS) \ 6595 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6596 #include "clang/Basic/BuiltinsAArch64.def" 6597 }; 6598 6599 class AArch64leTargetInfo : public AArch64TargetInfo { 6600 void setDataLayout() override { 6601 if (getTriple().isOSBinFormatMachO()) 6602 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6603 else 6604 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6605 } 6606 6607 public: 6608 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6609 : AArch64TargetInfo(Triple, Opts) { 6610 } 6611 void getTargetDefines(const LangOptions &Opts, 6612 MacroBuilder &Builder) const override { 6613 Builder.defineMacro("__AARCH64EL__"); 6614 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6615 } 6616 }; 6617 6618 class MicrosoftARM64TargetInfo 6619 : public WindowsTargetInfo<AArch64leTargetInfo> { 6620 const llvm::Triple Triple; 6621 6622 public: 6623 MicrosoftARM64TargetInfo(const llvm::Triple &Triple, 6624 const TargetOptions &Opts) 6625 : WindowsTargetInfo<AArch64leTargetInfo>(Triple, Opts), Triple(Triple) { 6626 WCharType = UnsignedShort; 6627 SizeType = UnsignedLongLong; 6628 TheCXXABI.set(TargetCXXABI::Microsoft); 6629 } 6630 6631 void setDataLayout() override { 6632 resetDataLayout("e-m:w-i64:64-i128:128-n32:64-S128"); 6633 } 6634 6635 void getVisualStudioDefines(const LangOptions &Opts, 6636 MacroBuilder &Builder) const { 6637 WindowsTargetInfo<AArch64leTargetInfo>::getVisualStudioDefines(Opts, 6638 Builder); 6639 Builder.defineMacro("_WIN32", "1"); 6640 Builder.defineMacro("_WIN64", "1"); 6641 Builder.defineMacro("_M_ARM64", "1"); 6642 } 6643 6644 void getTargetDefines(const LangOptions &Opts, 6645 MacroBuilder &Builder) const override { 6646 WindowsTargetInfo::getTargetDefines(Opts, Builder); 6647 getVisualStudioDefines(Opts, Builder); 6648 } 6649 6650 BuiltinVaListKind getBuiltinVaListKind() const override { 6651 return TargetInfo::CharPtrBuiltinVaList; 6652 } 6653 }; 6654 6655 class AArch64beTargetInfo : public AArch64TargetInfo { 6656 void setDataLayout() override { 6657 assert(!getTriple().isOSBinFormatMachO()); 6658 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6659 } 6660 6661 public: 6662 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6663 : AArch64TargetInfo(Triple, Opts) {} 6664 void getTargetDefines(const LangOptions &Opts, 6665 MacroBuilder &Builder) const override { 6666 Builder.defineMacro("__AARCH64EB__"); 6667 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6668 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6669 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6670 } 6671 }; 6672 6673 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6674 protected: 6675 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6676 MacroBuilder &Builder) const override { 6677 Builder.defineMacro("__AARCH64_SIMD__"); 6678 Builder.defineMacro("__ARM64_ARCH_8__"); 6679 Builder.defineMacro("__ARM_NEON__"); 6680 Builder.defineMacro("__LITTLE_ENDIAN__"); 6681 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6682 Builder.defineMacro("__arm64", "1"); 6683 Builder.defineMacro("__arm64__", "1"); 6684 6685 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6686 } 6687 6688 public: 6689 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6690 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6691 Int64Type = SignedLongLong; 6692 WCharType = SignedInt; 6693 UseSignedCharForObjCBool = false; 6694 6695 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6696 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 6697 6698 TheCXXABI.set(TargetCXXABI::iOS64); 6699 } 6700 6701 BuiltinVaListKind getBuiltinVaListKind() const override { 6702 return TargetInfo::CharPtrBuiltinVaList; 6703 } 6704 }; 6705 6706 // Hexagon abstract base class 6707 class HexagonTargetInfo : public TargetInfo { 6708 static const Builtin::Info BuiltinInfo[]; 6709 static const char * const GCCRegNames[]; 6710 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6711 std::string CPU; 6712 bool HasHVX, HasHVXDouble; 6713 bool UseLongCalls; 6714 6715 public: 6716 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6717 : TargetInfo(Triple) { 6718 // Specify the vector alignment explicitly. For v512x1, the calculated 6719 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6720 // the required minimum of 64 bytes. 6721 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6722 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6723 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6724 SizeType = UnsignedInt; 6725 PtrDiffType = SignedInt; 6726 IntPtrType = SignedInt; 6727 6728 // {} in inline assembly are packet specifiers, not assembly variant 6729 // specifiers. 6730 NoAsmVariants = true; 6731 6732 LargeArrayMinWidth = 64; 6733 LargeArrayAlign = 64; 6734 UseBitFieldTypeAlignment = true; 6735 ZeroLengthBitfieldBoundary = 32; 6736 HasHVX = HasHVXDouble = false; 6737 UseLongCalls = false; 6738 } 6739 6740 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6741 return llvm::makeArrayRef(BuiltinInfo, 6742 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6743 } 6744 6745 bool validateAsmConstraint(const char *&Name, 6746 TargetInfo::ConstraintInfo &Info) const override { 6747 switch (*Name) { 6748 case 'v': 6749 case 'q': 6750 if (HasHVX) { 6751 Info.setAllowsRegister(); 6752 return true; 6753 } 6754 break; 6755 case 's': 6756 // Relocatable constant. 6757 return true; 6758 } 6759 return false; 6760 } 6761 6762 void getTargetDefines(const LangOptions &Opts, 6763 MacroBuilder &Builder) const override; 6764 6765 bool isCLZForZeroUndef() const override { return false; } 6766 6767 bool hasFeature(StringRef Feature) const override { 6768 return llvm::StringSwitch<bool>(Feature) 6769 .Case("hexagon", true) 6770 .Case("hvx", HasHVX) 6771 .Case("hvx-double", HasHVXDouble) 6772 .Case("long-calls", UseLongCalls) 6773 .Default(false); 6774 } 6775 6776 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6777 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6778 const override; 6779 6780 bool handleTargetFeatures(std::vector<std::string> &Features, 6781 DiagnosticsEngine &Diags) override; 6782 6783 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6784 bool Enabled) const override; 6785 6786 BuiltinVaListKind getBuiltinVaListKind() const override { 6787 return TargetInfo::CharPtrBuiltinVaList; 6788 } 6789 ArrayRef<const char *> getGCCRegNames() const override; 6790 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6791 const char *getClobbers() const override { 6792 return ""; 6793 } 6794 6795 static const char *getHexagonCPUSuffix(StringRef Name) { 6796 return llvm::StringSwitch<const char*>(Name) 6797 .Case("hexagonv4", "4") 6798 .Case("hexagonv5", "5") 6799 .Case("hexagonv55", "55") 6800 .Case("hexagonv60", "60") 6801 .Case("hexagonv62", "62") 6802 .Default(nullptr); 6803 } 6804 6805 bool setCPU(const std::string &Name) override { 6806 if (!getHexagonCPUSuffix(Name)) 6807 return false; 6808 CPU = Name; 6809 return true; 6810 } 6811 6812 int getEHDataRegisterNumber(unsigned RegNo) const override { 6813 return RegNo < 2 ? RegNo : -1; 6814 } 6815 }; 6816 6817 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6818 MacroBuilder &Builder) const { 6819 Builder.defineMacro("__qdsp6__", "1"); 6820 Builder.defineMacro("__hexagon__", "1"); 6821 6822 if (CPU == "hexagonv4") { 6823 Builder.defineMacro("__HEXAGON_V4__"); 6824 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6825 if (Opts.HexagonQdsp6Compat) { 6826 Builder.defineMacro("__QDSP6_V4__"); 6827 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6828 } 6829 } else if (CPU == "hexagonv5") { 6830 Builder.defineMacro("__HEXAGON_V5__"); 6831 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6832 if(Opts.HexagonQdsp6Compat) { 6833 Builder.defineMacro("__QDSP6_V5__"); 6834 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6835 } 6836 } else if (CPU == "hexagonv55") { 6837 Builder.defineMacro("__HEXAGON_V55__"); 6838 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6839 Builder.defineMacro("__QDSP6_V55__"); 6840 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6841 } else if (CPU == "hexagonv60") { 6842 Builder.defineMacro("__HEXAGON_V60__"); 6843 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6844 Builder.defineMacro("__QDSP6_V60__"); 6845 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6846 } else if (CPU == "hexagonv62") { 6847 Builder.defineMacro("__HEXAGON_V62__"); 6848 Builder.defineMacro("__HEXAGON_ARCH__", "62"); 6849 } 6850 6851 if (hasFeature("hvx")) { 6852 Builder.defineMacro("__HVX__"); 6853 if (hasFeature("hvx-double")) 6854 Builder.defineMacro("__HVXDBL__"); 6855 } 6856 } 6857 6858 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6859 DiagnosticsEngine &Diags, StringRef CPU, 6860 const std::vector<std::string> &FeaturesVec) const { 6861 // Default for v60: -hvx, -hvx-double. 6862 Features["hvx"] = false; 6863 Features["hvx-double"] = false; 6864 Features["long-calls"] = false; 6865 6866 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6867 } 6868 6869 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6870 DiagnosticsEngine &Diags) { 6871 for (auto &F : Features) { 6872 if (F == "+hvx") 6873 HasHVX = true; 6874 else if (F == "-hvx") 6875 HasHVX = HasHVXDouble = false; 6876 else if (F == "+hvx-double") 6877 HasHVX = HasHVXDouble = true; 6878 else if (F == "-hvx-double") 6879 HasHVXDouble = false; 6880 6881 if (F == "+long-calls") 6882 UseLongCalls = true; 6883 else if (F == "-long-calls") 6884 UseLongCalls = false; 6885 } 6886 return true; 6887 } 6888 6889 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 6890 StringRef Name, bool Enabled) const { 6891 if (Enabled) { 6892 if (Name == "hvx-double") 6893 Features["hvx"] = true; 6894 } else { 6895 if (Name == "hvx") 6896 Features["hvx-double"] = false; 6897 } 6898 Features[Name] = Enabled; 6899 } 6900 6901 const char *const HexagonTargetInfo::GCCRegNames[] = { 6902 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6903 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6904 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6905 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6906 "p0", "p1", "p2", "p3", 6907 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6908 }; 6909 6910 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6911 return llvm::makeArrayRef(GCCRegNames); 6912 } 6913 6914 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6915 { { "sp" }, "r29" }, 6916 { { "fp" }, "r30" }, 6917 { { "lr" }, "r31" }, 6918 }; 6919 6920 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6921 return llvm::makeArrayRef(GCCRegAliases); 6922 } 6923 6924 6925 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6926 #define BUILTIN(ID, TYPE, ATTRS) \ 6927 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6928 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6929 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6930 #include "clang/Basic/BuiltinsHexagon.def" 6931 }; 6932 6933 class LanaiTargetInfo : public TargetInfo { 6934 // Class for Lanai (32-bit). 6935 // The CPU profiles supported by the Lanai backend 6936 enum CPUKind { 6937 CK_NONE, 6938 CK_V11, 6939 } CPU; 6940 6941 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6942 static const char *const GCCRegNames[]; 6943 6944 public: 6945 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6946 : TargetInfo(Triple) { 6947 // Description string has to be kept in sync with backend. 6948 resetDataLayout("E" // Big endian 6949 "-m:e" // ELF name manging 6950 "-p:32:32" // 32 bit pointers, 32 bit aligned 6951 "-i64:64" // 64 bit integers, 64 bit aligned 6952 "-a:0:32" // 32 bit alignment of objects of aggregate type 6953 "-n32" // 32 bit native integer width 6954 "-S64" // 64 bit natural stack alignment 6955 ); 6956 6957 // Setting RegParmMax equal to what mregparm was set to in the old 6958 // toolchain 6959 RegParmMax = 4; 6960 6961 // Set the default CPU to V11 6962 CPU = CK_V11; 6963 6964 // Temporary approach to make everything at least word-aligned and allow for 6965 // safely casting between pointers with different alignment requirements. 6966 // TODO: Remove this when there are no more cast align warnings on the 6967 // firmware. 6968 MinGlobalAlign = 32; 6969 } 6970 6971 void getTargetDefines(const LangOptions &Opts, 6972 MacroBuilder &Builder) const override { 6973 // Define __lanai__ when building for target lanai. 6974 Builder.defineMacro("__lanai__"); 6975 6976 // Set define for the CPU specified. 6977 switch (CPU) { 6978 case CK_V11: 6979 Builder.defineMacro("__LANAI_V11__"); 6980 break; 6981 case CK_NONE: 6982 llvm_unreachable("Unhandled target CPU"); 6983 } 6984 } 6985 6986 bool setCPU(const std::string &Name) override { 6987 CPU = llvm::StringSwitch<CPUKind>(Name) 6988 .Case("v11", CK_V11) 6989 .Default(CK_NONE); 6990 6991 return CPU != CK_NONE; 6992 } 6993 6994 bool hasFeature(StringRef Feature) const override { 6995 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6996 } 6997 6998 ArrayRef<const char *> getGCCRegNames() const override; 6999 7000 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7001 7002 BuiltinVaListKind getBuiltinVaListKind() const override { 7003 return TargetInfo::VoidPtrBuiltinVaList; 7004 } 7005 7006 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7007 7008 bool validateAsmConstraint(const char *&Name, 7009 TargetInfo::ConstraintInfo &info) const override { 7010 return false; 7011 } 7012 7013 const char *getClobbers() const override { return ""; } 7014 }; 7015 7016 const char *const LanaiTargetInfo::GCCRegNames[] = { 7017 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 7018 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 7019 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 7020 7021 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 7022 return llvm::makeArrayRef(GCCRegNames); 7023 } 7024 7025 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 7026 {{"pc"}, "r2"}, 7027 {{"sp"}, "r4"}, 7028 {{"fp"}, "r5"}, 7029 {{"rv"}, "r8"}, 7030 {{"rr1"}, "r10"}, 7031 {{"rr2"}, "r11"}, 7032 {{"rca"}, "r15"}, 7033 }; 7034 7035 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 7036 return llvm::makeArrayRef(GCCRegAliases); 7037 } 7038 7039 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 7040 class SparcTargetInfo : public TargetInfo { 7041 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 7042 static const char * const GCCRegNames[]; 7043 bool SoftFloat; 7044 public: 7045 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7046 : TargetInfo(Triple), SoftFloat(false) {} 7047 7048 int getEHDataRegisterNumber(unsigned RegNo) const override { 7049 if (RegNo == 0) return 24; 7050 if (RegNo == 1) return 25; 7051 return -1; 7052 } 7053 7054 bool handleTargetFeatures(std::vector<std::string> &Features, 7055 DiagnosticsEngine &Diags) override { 7056 // Check if software floating point is enabled 7057 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 7058 if (Feature != Features.end()) { 7059 SoftFloat = true; 7060 } 7061 return true; 7062 } 7063 void getTargetDefines(const LangOptions &Opts, 7064 MacroBuilder &Builder) const override { 7065 DefineStd(Builder, "sparc", Opts); 7066 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7067 7068 if (SoftFloat) 7069 Builder.defineMacro("SOFT_FLOAT", "1"); 7070 } 7071 7072 bool hasFeature(StringRef Feature) const override { 7073 return llvm::StringSwitch<bool>(Feature) 7074 .Case("softfloat", SoftFloat) 7075 .Case("sparc", true) 7076 .Default(false); 7077 } 7078 7079 bool hasSjLjLowering() const override { 7080 return true; 7081 } 7082 7083 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7084 // FIXME: Implement! 7085 return None; 7086 } 7087 BuiltinVaListKind getBuiltinVaListKind() const override { 7088 return TargetInfo::VoidPtrBuiltinVaList; 7089 } 7090 ArrayRef<const char *> getGCCRegNames() const override; 7091 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7092 bool validateAsmConstraint(const char *&Name, 7093 TargetInfo::ConstraintInfo &info) const override { 7094 // FIXME: Implement! 7095 switch (*Name) { 7096 case 'I': // Signed 13-bit constant 7097 case 'J': // Zero 7098 case 'K': // 32-bit constant with the low 12 bits clear 7099 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 7100 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 7101 case 'N': // Same as 'K' but zext (required for SIMode) 7102 case 'O': // The constant 4096 7103 return true; 7104 7105 case 'f': 7106 case 'e': 7107 info.setAllowsRegister(); 7108 return true; 7109 } 7110 return false; 7111 } 7112 const char *getClobbers() const override { 7113 // FIXME: Implement! 7114 return ""; 7115 } 7116 7117 // No Sparc V7 for now, the backend doesn't support it anyway. 7118 enum CPUKind { 7119 CK_GENERIC, 7120 CK_V8, 7121 CK_SUPERSPARC, 7122 CK_SPARCLITE, 7123 CK_F934, 7124 CK_HYPERSPARC, 7125 CK_SPARCLITE86X, 7126 CK_SPARCLET, 7127 CK_TSC701, 7128 CK_V9, 7129 CK_ULTRASPARC, 7130 CK_ULTRASPARC3, 7131 CK_NIAGARA, 7132 CK_NIAGARA2, 7133 CK_NIAGARA3, 7134 CK_NIAGARA4, 7135 CK_MYRIAD2100, 7136 CK_MYRIAD2150, 7137 CK_MYRIAD2450, 7138 CK_LEON2, 7139 CK_LEON2_AT697E, 7140 CK_LEON2_AT697F, 7141 CK_LEON3, 7142 CK_LEON3_UT699, 7143 CK_LEON3_GR712RC, 7144 CK_LEON4, 7145 CK_LEON4_GR740 7146 } CPU = CK_GENERIC; 7147 7148 enum CPUGeneration { 7149 CG_V8, 7150 CG_V9, 7151 }; 7152 7153 CPUGeneration getCPUGeneration(CPUKind Kind) const { 7154 switch (Kind) { 7155 case CK_GENERIC: 7156 case CK_V8: 7157 case CK_SUPERSPARC: 7158 case CK_SPARCLITE: 7159 case CK_F934: 7160 case CK_HYPERSPARC: 7161 case CK_SPARCLITE86X: 7162 case CK_SPARCLET: 7163 case CK_TSC701: 7164 case CK_MYRIAD2100: 7165 case CK_MYRIAD2150: 7166 case CK_MYRIAD2450: 7167 case CK_LEON2: 7168 case CK_LEON2_AT697E: 7169 case CK_LEON2_AT697F: 7170 case CK_LEON3: 7171 case CK_LEON3_UT699: 7172 case CK_LEON3_GR712RC: 7173 case CK_LEON4: 7174 case CK_LEON4_GR740: 7175 return CG_V8; 7176 case CK_V9: 7177 case CK_ULTRASPARC: 7178 case CK_ULTRASPARC3: 7179 case CK_NIAGARA: 7180 case CK_NIAGARA2: 7181 case CK_NIAGARA3: 7182 case CK_NIAGARA4: 7183 return CG_V9; 7184 } 7185 llvm_unreachable("Unexpected CPU kind"); 7186 } 7187 7188 CPUKind getCPUKind(StringRef Name) const { 7189 return llvm::StringSwitch<CPUKind>(Name) 7190 .Case("v8", CK_V8) 7191 .Case("supersparc", CK_SUPERSPARC) 7192 .Case("sparclite", CK_SPARCLITE) 7193 .Case("f934", CK_F934) 7194 .Case("hypersparc", CK_HYPERSPARC) 7195 .Case("sparclite86x", CK_SPARCLITE86X) 7196 .Case("sparclet", CK_SPARCLET) 7197 .Case("tsc701", CK_TSC701) 7198 .Case("v9", CK_V9) 7199 .Case("ultrasparc", CK_ULTRASPARC) 7200 .Case("ultrasparc3", CK_ULTRASPARC3) 7201 .Case("niagara", CK_NIAGARA) 7202 .Case("niagara2", CK_NIAGARA2) 7203 .Case("niagara3", CK_NIAGARA3) 7204 .Case("niagara4", CK_NIAGARA4) 7205 .Case("ma2100", CK_MYRIAD2100) 7206 .Case("ma2150", CK_MYRIAD2150) 7207 .Case("ma2450", CK_MYRIAD2450) 7208 // FIXME: the myriad2[.n] spellings are obsolete, 7209 // but a grace period is needed to allow updating dependent builds. 7210 .Case("myriad2", CK_MYRIAD2100) 7211 .Case("myriad2.1", CK_MYRIAD2100) 7212 .Case("myriad2.2", CK_MYRIAD2150) 7213 .Case("leon2", CK_LEON2) 7214 .Case("at697e", CK_LEON2_AT697E) 7215 .Case("at697f", CK_LEON2_AT697F) 7216 .Case("leon3", CK_LEON3) 7217 .Case("ut699", CK_LEON3_UT699) 7218 .Case("gr712rc", CK_LEON3_GR712RC) 7219 .Case("leon4", CK_LEON4) 7220 .Case("gr740", CK_LEON4_GR740) 7221 .Default(CK_GENERIC); 7222 } 7223 7224 bool setCPU(const std::string &Name) override { 7225 CPU = getCPUKind(Name); 7226 return CPU != CK_GENERIC; 7227 } 7228 }; 7229 7230 const char * const SparcTargetInfo::GCCRegNames[] = { 7231 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7232 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7233 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 7234 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 7235 }; 7236 7237 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 7238 return llvm::makeArrayRef(GCCRegNames); 7239 } 7240 7241 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 7242 { { "g0" }, "r0" }, 7243 { { "g1" }, "r1" }, 7244 { { "g2" }, "r2" }, 7245 { { "g3" }, "r3" }, 7246 { { "g4" }, "r4" }, 7247 { { "g5" }, "r5" }, 7248 { { "g6" }, "r6" }, 7249 { { "g7" }, "r7" }, 7250 { { "o0" }, "r8" }, 7251 { { "o1" }, "r9" }, 7252 { { "o2" }, "r10" }, 7253 { { "o3" }, "r11" }, 7254 { { "o4" }, "r12" }, 7255 { { "o5" }, "r13" }, 7256 { { "o6", "sp" }, "r14" }, 7257 { { "o7" }, "r15" }, 7258 { { "l0" }, "r16" }, 7259 { { "l1" }, "r17" }, 7260 { { "l2" }, "r18" }, 7261 { { "l3" }, "r19" }, 7262 { { "l4" }, "r20" }, 7263 { { "l5" }, "r21" }, 7264 { { "l6" }, "r22" }, 7265 { { "l7" }, "r23" }, 7266 { { "i0" }, "r24" }, 7267 { { "i1" }, "r25" }, 7268 { { "i2" }, "r26" }, 7269 { { "i3" }, "r27" }, 7270 { { "i4" }, "r28" }, 7271 { { "i5" }, "r29" }, 7272 { { "i6", "fp" }, "r30" }, 7273 { { "i7" }, "r31" }, 7274 }; 7275 7276 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 7277 return llvm::makeArrayRef(GCCRegAliases); 7278 } 7279 7280 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 7281 class SparcV8TargetInfo : public SparcTargetInfo { 7282 public: 7283 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7284 : SparcTargetInfo(Triple, Opts) { 7285 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7286 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 7287 switch (getTriple().getOS()) { 7288 default: 7289 SizeType = UnsignedInt; 7290 IntPtrType = SignedInt; 7291 PtrDiffType = SignedInt; 7292 break; 7293 case llvm::Triple::NetBSD: 7294 case llvm::Triple::OpenBSD: 7295 SizeType = UnsignedLong; 7296 IntPtrType = SignedLong; 7297 PtrDiffType = SignedLong; 7298 break; 7299 } 7300 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops 7301 // on up to 64 bits. 7302 MaxAtomicPromoteWidth = 64; 7303 MaxAtomicInlineWidth = 32; 7304 } 7305 7306 void getTargetDefines(const LangOptions &Opts, 7307 MacroBuilder &Builder) const override { 7308 SparcTargetInfo::getTargetDefines(Opts, Builder); 7309 switch (getCPUGeneration(CPU)) { 7310 case CG_V8: 7311 Builder.defineMacro("__sparcv8"); 7312 if (getTriple().getOS() != llvm::Triple::Solaris) 7313 Builder.defineMacro("__sparcv8__"); 7314 break; 7315 case CG_V9: 7316 Builder.defineMacro("__sparcv9"); 7317 if (getTriple().getOS() != llvm::Triple::Solaris) { 7318 Builder.defineMacro("__sparcv9__"); 7319 Builder.defineMacro("__sparc_v9__"); 7320 } 7321 break; 7322 } 7323 if (getTriple().getVendor() == llvm::Triple::Myriad) { 7324 std::string MyriadArchValue, Myriad2Value; 7325 Builder.defineMacro("__sparc_v8__"); 7326 Builder.defineMacro("__leon__"); 7327 switch (CPU) { 7328 case CK_MYRIAD2150: 7329 MyriadArchValue = "__ma2150"; 7330 Myriad2Value = "2"; 7331 break; 7332 case CK_MYRIAD2450: 7333 MyriadArchValue = "__ma2450"; 7334 Myriad2Value = "2"; 7335 break; 7336 default: 7337 MyriadArchValue = "__ma2100"; 7338 Myriad2Value = "1"; 7339 break; 7340 } 7341 Builder.defineMacro(MyriadArchValue, "1"); 7342 Builder.defineMacro(MyriadArchValue+"__", "1"); 7343 Builder.defineMacro("__myriad2__", Myriad2Value); 7344 Builder.defineMacro("__myriad2", Myriad2Value); 7345 } 7346 } 7347 7348 bool hasSjLjLowering() const override { 7349 return true; 7350 } 7351 }; 7352 7353 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 7354 class SparcV8elTargetInfo : public SparcV8TargetInfo { 7355 public: 7356 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7357 : SparcV8TargetInfo(Triple, Opts) { 7358 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7359 } 7360 }; 7361 7362 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 7363 class SparcV9TargetInfo : public SparcTargetInfo { 7364 public: 7365 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7366 : SparcTargetInfo(Triple, Opts) { 7367 // FIXME: Support Sparc quad-precision long double? 7368 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 7369 // This is an LP64 platform. 7370 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7371 7372 // OpenBSD uses long long for int64_t and intmax_t. 7373 if (getTriple().getOS() == llvm::Triple::OpenBSD) 7374 IntMaxType = SignedLongLong; 7375 else 7376 IntMaxType = SignedLong; 7377 Int64Type = IntMaxType; 7378 7379 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 7380 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 7381 LongDoubleWidth = 128; 7382 LongDoubleAlign = 128; 7383 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7384 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7385 } 7386 7387 void getTargetDefines(const LangOptions &Opts, 7388 MacroBuilder &Builder) const override { 7389 SparcTargetInfo::getTargetDefines(Opts, Builder); 7390 Builder.defineMacro("__sparcv9"); 7391 Builder.defineMacro("__arch64__"); 7392 // Solaris doesn't need these variants, but the BSDs do. 7393 if (getTriple().getOS() != llvm::Triple::Solaris) { 7394 Builder.defineMacro("__sparc64__"); 7395 Builder.defineMacro("__sparc_v9__"); 7396 Builder.defineMacro("__sparcv9__"); 7397 } 7398 } 7399 7400 bool setCPU(const std::string &Name) override { 7401 if (!SparcTargetInfo::setCPU(Name)) 7402 return false; 7403 return getCPUGeneration(CPU) == CG_V9; 7404 } 7405 }; 7406 7407 class SystemZTargetInfo : public TargetInfo { 7408 static const Builtin::Info BuiltinInfo[]; 7409 static const char *const GCCRegNames[]; 7410 std::string CPU; 7411 bool HasTransactionalExecution; 7412 bool HasVector; 7413 7414 public: 7415 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7416 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 7417 HasVector(false) { 7418 IntMaxType = SignedLong; 7419 Int64Type = SignedLong; 7420 TLSSupported = true; 7421 IntWidth = IntAlign = 32; 7422 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 7423 PointerWidth = PointerAlign = 64; 7424 LongDoubleWidth = 128; 7425 LongDoubleAlign = 64; 7426 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7427 DefaultAlignForAttributeAligned = 64; 7428 MinGlobalAlign = 16; 7429 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 7430 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7431 } 7432 void getTargetDefines(const LangOptions &Opts, 7433 MacroBuilder &Builder) const override { 7434 Builder.defineMacro("__s390__"); 7435 Builder.defineMacro("__s390x__"); 7436 Builder.defineMacro("__zarch__"); 7437 Builder.defineMacro("__LONG_DOUBLE_128__"); 7438 7439 const std::string ISARev = llvm::StringSwitch<std::string>(CPU) 7440 .Cases("arch8", "z10", "8") 7441 .Cases("arch9", "z196", "9") 7442 .Cases("arch10", "zEC12", "10") 7443 .Cases("arch11", "z13", "11") 7444 .Default(""); 7445 if (!ISARev.empty()) 7446 Builder.defineMacro("__ARCH__", ISARev); 7447 7448 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7449 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7450 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7451 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7452 7453 if (HasTransactionalExecution) 7454 Builder.defineMacro("__HTM__"); 7455 if (HasVector) 7456 Builder.defineMacro("__VX__"); 7457 if (Opts.ZVector) 7458 Builder.defineMacro("__VEC__", "10301"); 7459 } 7460 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7461 return llvm::makeArrayRef(BuiltinInfo, 7462 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 7463 } 7464 7465 ArrayRef<const char *> getGCCRegNames() const override; 7466 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7467 // No aliases. 7468 return None; 7469 } 7470 bool validateAsmConstraint(const char *&Name, 7471 TargetInfo::ConstraintInfo &info) const override; 7472 const char *getClobbers() const override { 7473 // FIXME: Is this really right? 7474 return ""; 7475 } 7476 BuiltinVaListKind getBuiltinVaListKind() const override { 7477 return TargetInfo::SystemZBuiltinVaList; 7478 } 7479 bool setCPU(const std::string &Name) override { 7480 CPU = Name; 7481 bool CPUKnown = llvm::StringSwitch<bool>(Name) 7482 .Case("z10", true) 7483 .Case("arch8", true) 7484 .Case("z196", true) 7485 .Case("arch9", true) 7486 .Case("zEC12", true) 7487 .Case("arch10", true) 7488 .Case("z13", true) 7489 .Case("arch11", true) 7490 .Default(false); 7491 7492 return CPUKnown; 7493 } 7494 bool 7495 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7496 StringRef CPU, 7497 const std::vector<std::string> &FeaturesVec) const override { 7498 if (CPU == "zEC12" || CPU == "arch10") 7499 Features["transactional-execution"] = true; 7500 if (CPU == "z13" || CPU == "arch11") { 7501 Features["transactional-execution"] = true; 7502 Features["vector"] = true; 7503 } 7504 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7505 } 7506 7507 bool handleTargetFeatures(std::vector<std::string> &Features, 7508 DiagnosticsEngine &Diags) override { 7509 HasTransactionalExecution = false; 7510 for (const auto &Feature : Features) { 7511 if (Feature == "+transactional-execution") 7512 HasTransactionalExecution = true; 7513 else if (Feature == "+vector") 7514 HasVector = true; 7515 } 7516 // If we use the vector ABI, vector types are 64-bit aligned. 7517 if (HasVector) { 7518 MaxVectorAlign = 64; 7519 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 7520 "-v128:64-a:8:16-n32:64"); 7521 } 7522 return true; 7523 } 7524 7525 bool hasFeature(StringRef Feature) const override { 7526 return llvm::StringSwitch<bool>(Feature) 7527 .Case("systemz", true) 7528 .Case("htm", HasTransactionalExecution) 7529 .Case("vx", HasVector) 7530 .Default(false); 7531 } 7532 7533 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7534 switch (CC) { 7535 case CC_C: 7536 case CC_Swift: 7537 case CC_OpenCLKernel: 7538 return CCCR_OK; 7539 default: 7540 return CCCR_Warning; 7541 } 7542 } 7543 7544 StringRef getABI() const override { 7545 if (HasVector) 7546 return "vector"; 7547 return ""; 7548 } 7549 7550 bool useFloat128ManglingForLongDouble() const override { 7551 return true; 7552 } 7553 }; 7554 7555 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 7556 #define BUILTIN(ID, TYPE, ATTRS) \ 7557 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7558 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7559 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 7560 #include "clang/Basic/BuiltinsSystemZ.def" 7561 }; 7562 7563 const char *const SystemZTargetInfo::GCCRegNames[] = { 7564 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7565 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7566 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 7567 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 7568 }; 7569 7570 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 7571 return llvm::makeArrayRef(GCCRegNames); 7572 } 7573 7574 bool SystemZTargetInfo:: 7575 validateAsmConstraint(const char *&Name, 7576 TargetInfo::ConstraintInfo &Info) const { 7577 switch (*Name) { 7578 default: 7579 return false; 7580 7581 case 'a': // Address register 7582 case 'd': // Data register (equivalent to 'r') 7583 case 'f': // Floating-point register 7584 Info.setAllowsRegister(); 7585 return true; 7586 7587 case 'I': // Unsigned 8-bit constant 7588 case 'J': // Unsigned 12-bit constant 7589 case 'K': // Signed 16-bit constant 7590 case 'L': // Signed 20-bit displacement (on all targets we support) 7591 case 'M': // 0x7fffffff 7592 return true; 7593 7594 case 'Q': // Memory with base and unsigned 12-bit displacement 7595 case 'R': // Likewise, plus an index 7596 case 'S': // Memory with base and signed 20-bit displacement 7597 case 'T': // Likewise, plus an index 7598 Info.setAllowsMemory(); 7599 return true; 7600 } 7601 } 7602 7603 class MSP430TargetInfo : public TargetInfo { 7604 static const char *const GCCRegNames[]; 7605 7606 public: 7607 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7608 : TargetInfo(Triple) { 7609 TLSSupported = false; 7610 IntWidth = 16; 7611 IntAlign = 16; 7612 LongWidth = 32; 7613 LongLongWidth = 64; 7614 LongAlign = LongLongAlign = 16; 7615 PointerWidth = 16; 7616 PointerAlign = 16; 7617 SuitableAlign = 16; 7618 SizeType = UnsignedInt; 7619 IntMaxType = SignedLongLong; 7620 IntPtrType = SignedInt; 7621 PtrDiffType = SignedInt; 7622 SigAtomicType = SignedLong; 7623 resetDataLayout("e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16"); 7624 } 7625 void getTargetDefines(const LangOptions &Opts, 7626 MacroBuilder &Builder) const override { 7627 Builder.defineMacro("MSP430"); 7628 Builder.defineMacro("__MSP430__"); 7629 // FIXME: defines for different 'flavours' of MCU 7630 } 7631 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7632 // FIXME: Implement. 7633 return None; 7634 } 7635 bool hasFeature(StringRef Feature) const override { 7636 return Feature == "msp430"; 7637 } 7638 ArrayRef<const char *> getGCCRegNames() const override; 7639 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7640 // No aliases. 7641 return None; 7642 } 7643 bool validateAsmConstraint(const char *&Name, 7644 TargetInfo::ConstraintInfo &info) const override { 7645 // FIXME: implement 7646 switch (*Name) { 7647 case 'K': // the constant 1 7648 case 'L': // constant -1^20 .. 1^19 7649 case 'M': // constant 1-4: 7650 return true; 7651 } 7652 // No target constraints for now. 7653 return false; 7654 } 7655 const char *getClobbers() const override { 7656 // FIXME: Is this really right? 7657 return ""; 7658 } 7659 BuiltinVaListKind getBuiltinVaListKind() const override { 7660 // FIXME: implement 7661 return TargetInfo::CharPtrBuiltinVaList; 7662 } 7663 }; 7664 7665 const char *const MSP430TargetInfo::GCCRegNames[] = { 7666 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7667 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7668 7669 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7670 return llvm::makeArrayRef(GCCRegNames); 7671 } 7672 7673 // LLVM and Clang cannot be used directly to output native binaries for 7674 // target, but is used to compile C code to llvm bitcode with correct 7675 // type and alignment information. 7676 // 7677 // TCE uses the llvm bitcode as input and uses it for generating customized 7678 // target processor and program binary. TCE co-design environment is 7679 // publicly available in http://tce.cs.tut.fi 7680 7681 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7682 0, // Default 7683 3, // opencl_global 7684 4, // opencl_local 7685 5, // opencl_constant 7686 // FIXME: generic has to be added to the target 7687 0, // opencl_generic 7688 0, // cuda_device 7689 0, // cuda_constant 7690 0 // cuda_shared 7691 }; 7692 7693 class TCETargetInfo : public TargetInfo { 7694 public: 7695 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7696 : TargetInfo(Triple) { 7697 TLSSupported = false; 7698 IntWidth = 32; 7699 LongWidth = LongLongWidth = 32; 7700 PointerWidth = 32; 7701 IntAlign = 32; 7702 LongAlign = LongLongAlign = 32; 7703 PointerAlign = 32; 7704 SuitableAlign = 32; 7705 SizeType = UnsignedInt; 7706 IntMaxType = SignedLong; 7707 IntPtrType = SignedInt; 7708 PtrDiffType = SignedInt; 7709 FloatWidth = 32; 7710 FloatAlign = 32; 7711 DoubleWidth = 32; 7712 DoubleAlign = 32; 7713 LongDoubleWidth = 32; 7714 LongDoubleAlign = 32; 7715 FloatFormat = &llvm::APFloat::IEEEsingle(); 7716 DoubleFormat = &llvm::APFloat::IEEEsingle(); 7717 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 7718 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-" 7719 "i16:16:32-i32:32:32-i64:32:32-" 7720 "f32:32:32-f64:32:32-v64:32:32-" 7721 "v128:32:32-v256:32:32-v512:32:32-" 7722 "v1024:32:32-a0:0:32-n32"); 7723 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7724 UseAddrSpaceMapMangling = true; 7725 } 7726 7727 void getTargetDefines(const LangOptions &Opts, 7728 MacroBuilder &Builder) const override { 7729 DefineStd(Builder, "tce", Opts); 7730 Builder.defineMacro("__TCE__"); 7731 Builder.defineMacro("__TCE_V1__"); 7732 } 7733 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7734 7735 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7736 const char *getClobbers() const override { return ""; } 7737 BuiltinVaListKind getBuiltinVaListKind() const override { 7738 return TargetInfo::VoidPtrBuiltinVaList; 7739 } 7740 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7741 bool validateAsmConstraint(const char *&Name, 7742 TargetInfo::ConstraintInfo &info) const override { 7743 return true; 7744 } 7745 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7746 return None; 7747 } 7748 }; 7749 7750 class TCELETargetInfo : public TCETargetInfo { 7751 public: 7752 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7753 : TCETargetInfo(Triple, Opts) { 7754 BigEndian = false; 7755 7756 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-" 7757 "i16:16:32-i32:32:32-i64:32:32-" 7758 "f32:32:32-f64:32:32-v64:32:32-" 7759 "v128:32:32-v256:32:32-v512:32:32-" 7760 "v1024:32:32-a0:0:32-n32"); 7761 7762 } 7763 7764 virtual void getTargetDefines(const LangOptions &Opts, 7765 MacroBuilder &Builder) const { 7766 DefineStd(Builder, "tcele", Opts); 7767 Builder.defineMacro("__TCE__"); 7768 Builder.defineMacro("__TCE_V1__"); 7769 Builder.defineMacro("__TCELE__"); 7770 Builder.defineMacro("__TCELE_V1__"); 7771 } 7772 7773 }; 7774 7775 class BPFTargetInfo : public TargetInfo { 7776 public: 7777 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7778 : TargetInfo(Triple) { 7779 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7780 SizeType = UnsignedLong; 7781 PtrDiffType = SignedLong; 7782 IntPtrType = SignedLong; 7783 IntMaxType = SignedLong; 7784 Int64Type = SignedLong; 7785 RegParmMax = 5; 7786 if (Triple.getArch() == llvm::Triple::bpfeb) { 7787 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7788 } else { 7789 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7790 } 7791 MaxAtomicPromoteWidth = 64; 7792 MaxAtomicInlineWidth = 64; 7793 TLSSupported = false; 7794 } 7795 void getTargetDefines(const LangOptions &Opts, 7796 MacroBuilder &Builder) const override { 7797 DefineStd(Builder, "bpf", Opts); 7798 Builder.defineMacro("__BPF__"); 7799 } 7800 bool hasFeature(StringRef Feature) const override { 7801 return Feature == "bpf"; 7802 } 7803 7804 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7805 const char *getClobbers() const override { 7806 return ""; 7807 } 7808 BuiltinVaListKind getBuiltinVaListKind() const override { 7809 return TargetInfo::VoidPtrBuiltinVaList; 7810 } 7811 ArrayRef<const char *> getGCCRegNames() const override { 7812 return None; 7813 } 7814 bool validateAsmConstraint(const char *&Name, 7815 TargetInfo::ConstraintInfo &info) const override { 7816 return true; 7817 } 7818 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7819 return None; 7820 } 7821 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7822 switch (CC) { 7823 default: 7824 return CCCR_Warning; 7825 case CC_C: 7826 case CC_OpenCLKernel: 7827 return CCCR_OK; 7828 } 7829 } 7830 }; 7831 7832 class Nios2TargetInfo : public TargetInfo { 7833 void setDataLayout() { 7834 if (BigEndian) 7835 resetDataLayout("E-p:32:32:32-i8:8:32-i16:16:32-n32"); 7836 else 7837 resetDataLayout("e-p:32:32:32-i8:8:32-i16:16:32-n32"); 7838 } 7839 7840 static const Builtin::Info BuiltinInfo[]; 7841 std::string CPU; 7842 std::string ABI; 7843 7844 public: 7845 Nios2TargetInfo(const llvm::Triple &triple, const TargetOptions &opts) 7846 : TargetInfo(triple), CPU(opts.CPU), ABI(opts.ABI) { 7847 SizeType = UnsignedInt; 7848 PtrDiffType = SignedInt; 7849 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7850 setDataLayout(); 7851 } 7852 7853 StringRef getABI() const override { return ABI; } 7854 bool setABI(const std::string &Name) override { 7855 if (Name == "o32" || Name == "eabi") { 7856 ABI = Name; 7857 return true; 7858 } 7859 return false; 7860 } 7861 7862 bool setCPU(const std::string &Name) override { 7863 if (Name == "nios2r1" || Name == "nios2r2") { 7864 CPU = Name; 7865 return true; 7866 } 7867 return false; 7868 } 7869 7870 void getTargetDefines(const LangOptions &Opts, 7871 MacroBuilder &Builder) const override { 7872 DefineStd(Builder, "nios2", Opts); 7873 DefineStd(Builder, "NIOS2", Opts); 7874 7875 Builder.defineMacro("__nios2"); 7876 Builder.defineMacro("__NIOS2"); 7877 Builder.defineMacro("__nios2__"); 7878 Builder.defineMacro("__NIOS2__"); 7879 } 7880 7881 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7882 return llvm::makeArrayRef(BuiltinInfo, clang::Nios2::LastTSBuiltin - 7883 Builtin::FirstTSBuiltin); 7884 } 7885 7886 bool isFeatureSupportedByCPU(StringRef Feature, StringRef CPU) const { 7887 const bool isR2 = CPU == "nios2r2"; 7888 return llvm::StringSwitch<bool>(Feature) 7889 .Case("nios2r2mandatory", isR2) 7890 .Case("nios2r2bmx", isR2) 7891 .Case("nios2r2mpx", isR2) 7892 .Case("nios2r2cdx", isR2) 7893 .Default(false); 7894 } 7895 7896 bool initFeatureMap(llvm::StringMap<bool> &Features, 7897 DiagnosticsEngine &Diags, StringRef CPU, 7898 const std::vector<std::string> &FeatureVec) const override { 7899 static const char *allFeatures[] = { 7900 "nios2r2mandatory", "nios2r2bmx", "nios2r2mpx", "nios2r2cdx" 7901 }; 7902 for (const char *feature : allFeatures) { 7903 Features[feature] = isFeatureSupportedByCPU(feature, CPU); 7904 } 7905 return true; 7906 } 7907 7908 bool hasFeature(StringRef Feature) const override { 7909 return isFeatureSupportedByCPU(Feature, CPU); 7910 } 7911 7912 BuiltinVaListKind getBuiltinVaListKind() const override { 7913 return TargetInfo::VoidPtrBuiltinVaList; 7914 } 7915 7916 ArrayRef<const char *> getGCCRegNames() const override { 7917 static const char *const GCCRegNames[] = { 7918 // CPU register names 7919 // Must match second column of GCCRegAliases 7920 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 7921 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", 7922 "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", 7923 "r31", 7924 // Floating point register names 7925 "ctl0", "ctl1", "ctl2", "ctl3", "ctl4", "ctl5", "ctl6", "ctl7", "ctl8", 7926 "ctl9", "ctl10", "ctl11", "ctl12", "ctl13", "ctl14", "ctl15" 7927 }; 7928 return llvm::makeArrayRef(GCCRegNames); 7929 } 7930 7931 bool validateAsmConstraint(const char *&Name, 7932 TargetInfo::ConstraintInfo &Info) const override { 7933 switch (*Name) { 7934 default: 7935 return false; 7936 7937 case 'r': // CPU registers. 7938 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7939 case 'y': // Equivalent to "r", backwards compatibility only. 7940 case 'f': // floating-point registers. 7941 case 'c': // $25 for indirect jumps 7942 case 'l': // lo register 7943 case 'x': // hilo register pair 7944 Info.setAllowsRegister(); 7945 return true; 7946 } 7947 } 7948 7949 const char *getClobbers() const override { return ""; } 7950 7951 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7952 static const TargetInfo::GCCRegAlias aliases[] = { 7953 {{"zero"}, "r0"}, {{"at"}, "r1"}, {{"et"}, "r24"}, 7954 {{"bt"}, "r25"}, {{"gp"}, "r26"}, {{"sp"}, "r27"}, 7955 {{"fp"}, "r28"}, {{"ea"}, "r29"}, {{"ba"}, "r30"}, 7956 {{"ra"}, "r31"}, {{"status"}, "ctl0"}, {{"estatus"}, "ctl1"}, 7957 {{"bstatus"}, "ctl2"}, {{"ienable"}, "ctl3"}, {{"ipending"}, "ctl4"}, 7958 {{"cpuid"}, "ctl5"}, {{"exception"}, "ctl7"}, {{"pteaddr"}, "ctl8"}, 7959 {{"tlbacc"}, "ctl9"}, {{"tlbmisc"}, "ctl10"}, {{"badaddr"}, "ctl12"}, 7960 {{"config"}, "ctl13"}, {{"mpubase"}, "ctl14"}, {{"mpuacc"}, "ctl15"}, 7961 }; 7962 return llvm::makeArrayRef(aliases); 7963 } 7964 }; 7965 7966 const Builtin::Info Nios2TargetInfo::BuiltinInfo[] = { 7967 #define BUILTIN(ID, TYPE, ATTRS) \ 7968 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 7969 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7970 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 7971 #include "clang/Basic/BuiltinsNios2.def" 7972 }; 7973 7974 class MipsTargetInfo : public TargetInfo { 7975 void setDataLayout() { 7976 StringRef Layout; 7977 7978 if (ABI == "o32") 7979 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7980 else if (ABI == "n32") 7981 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7982 else if (ABI == "n64") 7983 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7984 else 7985 llvm_unreachable("Invalid ABI"); 7986 7987 if (BigEndian) 7988 resetDataLayout(("E-" + Layout).str()); 7989 else 7990 resetDataLayout(("e-" + Layout).str()); 7991 } 7992 7993 7994 static const Builtin::Info BuiltinInfo[]; 7995 std::string CPU; 7996 bool IsMips16; 7997 bool IsMicromips; 7998 bool IsNan2008; 7999 bool IsSingleFloat; 8000 bool IsNoABICalls; 8001 bool CanUseBSDABICalls; 8002 enum MipsFloatABI { 8003 HardFloat, SoftFloat 8004 } FloatABI; 8005 enum DspRevEnum { 8006 NoDSP, DSP1, DSP2 8007 } DspRev; 8008 bool HasMSA; 8009 bool DisableMadd4; 8010 8011 protected: 8012 bool HasFP64; 8013 std::string ABI; 8014 8015 public: 8016 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8017 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 8018 IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false), 8019 CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP), 8020 HasMSA(false), DisableMadd4(false), HasFP64(false) { 8021 TheCXXABI.set(TargetCXXABI::GenericMIPS); 8022 8023 setABI((getTriple().getArch() == llvm::Triple::mips || 8024 getTriple().getArch() == llvm::Triple::mipsel) 8025 ? "o32" 8026 : "n64"); 8027 8028 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 8029 8030 CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD || 8031 Triple.getOS() == llvm::Triple::OpenBSD; 8032 } 8033 8034 bool isNaN2008Default() const { 8035 return CPU == "mips32r6" || CPU == "mips64r6"; 8036 } 8037 8038 bool isFP64Default() const { 8039 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 8040 } 8041 8042 bool isNan2008() const override { 8043 return IsNan2008; 8044 } 8045 8046 bool processorSupportsGPR64() const { 8047 return llvm::StringSwitch<bool>(CPU) 8048 .Case("mips3", true) 8049 .Case("mips4", true) 8050 .Case("mips5", true) 8051 .Case("mips64", true) 8052 .Case("mips64r2", true) 8053 .Case("mips64r3", true) 8054 .Case("mips64r5", true) 8055 .Case("mips64r6", true) 8056 .Case("octeon", true) 8057 .Default(false); 8058 return false; 8059 } 8060 8061 StringRef getABI() const override { return ABI; } 8062 bool setABI(const std::string &Name) override { 8063 if (Name == "o32") { 8064 setO32ABITypes(); 8065 ABI = Name; 8066 return true; 8067 } 8068 8069 if (Name == "n32") { 8070 setN32ABITypes(); 8071 ABI = Name; 8072 return true; 8073 } 8074 if (Name == "n64") { 8075 setN64ABITypes(); 8076 ABI = Name; 8077 return true; 8078 } 8079 return false; 8080 } 8081 8082 void setO32ABITypes() { 8083 Int64Type = SignedLongLong; 8084 IntMaxType = Int64Type; 8085 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8086 LongDoubleWidth = LongDoubleAlign = 64; 8087 LongWidth = LongAlign = 32; 8088 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 8089 PointerWidth = PointerAlign = 32; 8090 PtrDiffType = SignedInt; 8091 SizeType = UnsignedInt; 8092 SuitableAlign = 64; 8093 } 8094 8095 void setN32N64ABITypes() { 8096 LongDoubleWidth = LongDoubleAlign = 128; 8097 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8098 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 8099 LongDoubleWidth = LongDoubleAlign = 64; 8100 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8101 } 8102 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8103 SuitableAlign = 128; 8104 } 8105 8106 void setN64ABITypes() { 8107 setN32N64ABITypes(); 8108 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 8109 Int64Type = SignedLongLong; 8110 } else { 8111 Int64Type = SignedLong; 8112 } 8113 IntMaxType = Int64Type; 8114 LongWidth = LongAlign = 64; 8115 PointerWidth = PointerAlign = 64; 8116 PtrDiffType = SignedLong; 8117 SizeType = UnsignedLong; 8118 } 8119 8120 void setN32ABITypes() { 8121 setN32N64ABITypes(); 8122 Int64Type = SignedLongLong; 8123 IntMaxType = Int64Type; 8124 LongWidth = LongAlign = 32; 8125 PointerWidth = PointerAlign = 32; 8126 PtrDiffType = SignedInt; 8127 SizeType = UnsignedInt; 8128 } 8129 8130 bool setCPU(const std::string &Name) override { 8131 CPU = Name; 8132 return llvm::StringSwitch<bool>(Name) 8133 .Case("mips1", true) 8134 .Case("mips2", true) 8135 .Case("mips3", true) 8136 .Case("mips4", true) 8137 .Case("mips5", true) 8138 .Case("mips32", true) 8139 .Case("mips32r2", true) 8140 .Case("mips32r3", true) 8141 .Case("mips32r5", true) 8142 .Case("mips32r6", true) 8143 .Case("mips64", true) 8144 .Case("mips64r2", true) 8145 .Case("mips64r3", true) 8146 .Case("mips64r5", true) 8147 .Case("mips64r6", true) 8148 .Case("octeon", true) 8149 .Case("p5600", true) 8150 .Default(false); 8151 } 8152 const std::string& getCPU() const { return CPU; } 8153 bool 8154 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 8155 StringRef CPU, 8156 const std::vector<std::string> &FeaturesVec) const override { 8157 if (CPU.empty()) 8158 CPU = getCPU(); 8159 if (CPU == "octeon") 8160 Features["mips64r2"] = Features["cnmips"] = true; 8161 else 8162 Features[CPU] = true; 8163 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 8164 } 8165 8166 void getTargetDefines(const LangOptions &Opts, 8167 MacroBuilder &Builder) const override { 8168 if (BigEndian) { 8169 DefineStd(Builder, "MIPSEB", Opts); 8170 Builder.defineMacro("_MIPSEB"); 8171 } else { 8172 DefineStd(Builder, "MIPSEL", Opts); 8173 Builder.defineMacro("_MIPSEL"); 8174 } 8175 8176 Builder.defineMacro("__mips__"); 8177 Builder.defineMacro("_mips"); 8178 if (Opts.GNUMode) 8179 Builder.defineMacro("mips"); 8180 8181 if (ABI == "o32") { 8182 Builder.defineMacro("__mips", "32"); 8183 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 8184 } else { 8185 Builder.defineMacro("__mips", "64"); 8186 Builder.defineMacro("__mips64"); 8187 Builder.defineMacro("__mips64__"); 8188 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 8189 } 8190 8191 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 8192 .Cases("mips32", "mips64", "1") 8193 .Cases("mips32r2", "mips64r2", "2") 8194 .Cases("mips32r3", "mips64r3", "3") 8195 .Cases("mips32r5", "mips64r5", "5") 8196 .Cases("mips32r6", "mips64r6", "6") 8197 .Default(""); 8198 if (!ISARev.empty()) 8199 Builder.defineMacro("__mips_isa_rev", ISARev); 8200 8201 if (ABI == "o32") { 8202 Builder.defineMacro("__mips_o32"); 8203 Builder.defineMacro("_ABIO32", "1"); 8204 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 8205 } else if (ABI == "n32") { 8206 Builder.defineMacro("__mips_n32"); 8207 Builder.defineMacro("_ABIN32", "2"); 8208 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 8209 } else if (ABI == "n64") { 8210 Builder.defineMacro("__mips_n64"); 8211 Builder.defineMacro("_ABI64", "3"); 8212 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 8213 } else 8214 llvm_unreachable("Invalid ABI."); 8215 8216 if (!IsNoABICalls) { 8217 Builder.defineMacro("__mips_abicalls"); 8218 if (CanUseBSDABICalls) 8219 Builder.defineMacro("__ABICALLS__"); 8220 } 8221 8222 Builder.defineMacro("__REGISTER_PREFIX__", ""); 8223 8224 switch (FloatABI) { 8225 case HardFloat: 8226 Builder.defineMacro("__mips_hard_float", Twine(1)); 8227 break; 8228 case SoftFloat: 8229 Builder.defineMacro("__mips_soft_float", Twine(1)); 8230 break; 8231 } 8232 8233 if (IsSingleFloat) 8234 Builder.defineMacro("__mips_single_float", Twine(1)); 8235 8236 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 8237 Builder.defineMacro("_MIPS_FPSET", 8238 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 8239 8240 if (IsMips16) 8241 Builder.defineMacro("__mips16", Twine(1)); 8242 8243 if (IsMicromips) 8244 Builder.defineMacro("__mips_micromips", Twine(1)); 8245 8246 if (IsNan2008) 8247 Builder.defineMacro("__mips_nan2008", Twine(1)); 8248 8249 switch (DspRev) { 8250 default: 8251 break; 8252 case DSP1: 8253 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 8254 Builder.defineMacro("__mips_dsp", Twine(1)); 8255 break; 8256 case DSP2: 8257 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 8258 Builder.defineMacro("__mips_dspr2", Twine(1)); 8259 Builder.defineMacro("__mips_dsp", Twine(1)); 8260 break; 8261 } 8262 8263 if (HasMSA) 8264 Builder.defineMacro("__mips_msa", Twine(1)); 8265 8266 if (DisableMadd4) 8267 Builder.defineMacro("__mips_no_madd4", Twine(1)); 8268 8269 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 8270 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 8271 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 8272 8273 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 8274 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 8275 8276 // These shouldn't be defined for MIPS-I but there's no need to check 8277 // for that since MIPS-I isn't supported. 8278 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 8279 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 8280 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 8281 8282 // 32-bit MIPS processors don't have the necessary lld/scd instructions 8283 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 8284 // the instructions exist but using them violates the ABI since they 8285 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 8286 if (ABI == "n32" || ABI == "n64") 8287 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 8288 } 8289 8290 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8291 return llvm::makeArrayRef(BuiltinInfo, 8292 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 8293 } 8294 bool hasFeature(StringRef Feature) const override { 8295 return llvm::StringSwitch<bool>(Feature) 8296 .Case("mips", true) 8297 .Case("fp64", HasFP64) 8298 .Default(false); 8299 } 8300 BuiltinVaListKind getBuiltinVaListKind() const override { 8301 return TargetInfo::VoidPtrBuiltinVaList; 8302 } 8303 ArrayRef<const char *> getGCCRegNames() const override { 8304 static const char *const GCCRegNames[] = { 8305 // CPU register names 8306 // Must match second column of GCCRegAliases 8307 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 8308 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 8309 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 8310 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 8311 // Floating point register names 8312 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 8313 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 8314 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 8315 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 8316 // Hi/lo and condition register names 8317 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 8318 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 8319 "$ac3hi","$ac3lo", 8320 // MSA register names 8321 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 8322 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 8323 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 8324 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 8325 // MSA control register names 8326 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 8327 "$msarequest", "$msamap", "$msaunmap" 8328 }; 8329 return llvm::makeArrayRef(GCCRegNames); 8330 } 8331 bool validateAsmConstraint(const char *&Name, 8332 TargetInfo::ConstraintInfo &Info) const override { 8333 switch (*Name) { 8334 default: 8335 return false; 8336 case 'r': // CPU registers. 8337 case 'd': // Equivalent to "r" unless generating MIPS16 code. 8338 case 'y': // Equivalent to "r", backward compatibility only. 8339 case 'f': // floating-point registers. 8340 case 'c': // $25 for indirect jumps 8341 case 'l': // lo register 8342 case 'x': // hilo register pair 8343 Info.setAllowsRegister(); 8344 return true; 8345 case 'I': // Signed 16-bit constant 8346 case 'J': // Integer 0 8347 case 'K': // Unsigned 16-bit constant 8348 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 8349 case 'M': // Constants not loadable via lui, addiu, or ori 8350 case 'N': // Constant -1 to -65535 8351 case 'O': // A signed 15-bit constant 8352 case 'P': // A constant between 1 go 65535 8353 return true; 8354 case 'R': // An address that can be used in a non-macro load or store 8355 Info.setAllowsMemory(); 8356 return true; 8357 case 'Z': 8358 if (Name[1] == 'C') { // An address usable by ll, and sc. 8359 Info.setAllowsMemory(); 8360 Name++; // Skip over 'Z'. 8361 return true; 8362 } 8363 return false; 8364 } 8365 } 8366 8367 std::string convertConstraint(const char *&Constraint) const override { 8368 std::string R; 8369 switch (*Constraint) { 8370 case 'Z': // Two-character constraint; add "^" hint for later parsing. 8371 if (Constraint[1] == 'C') { 8372 R = std::string("^") + std::string(Constraint, 2); 8373 Constraint++; 8374 return R; 8375 } 8376 break; 8377 } 8378 return TargetInfo::convertConstraint(Constraint); 8379 } 8380 8381 const char *getClobbers() const override { 8382 // In GCC, $1 is not widely used in generated code (it's used only in a few 8383 // specific situations), so there is no real need for users to add it to 8384 // the clobbers list if they want to use it in their inline assembly code. 8385 // 8386 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 8387 // code generation, so using it in inline assembly without adding it to the 8388 // clobbers list can cause conflicts between the inline assembly code and 8389 // the surrounding generated code. 8390 // 8391 // Another problem is that LLVM is allowed to choose $1 for inline assembly 8392 // operands, which will conflict with the ".set at" assembler option (which 8393 // we use only for inline assembly, in order to maintain compatibility with 8394 // GCC) and will also conflict with the user's usage of $1. 8395 // 8396 // The easiest way to avoid these conflicts and keep $1 as an allocatable 8397 // register for generated code is to automatically clobber $1 for all inline 8398 // assembly code. 8399 // 8400 // FIXME: We should automatically clobber $1 only for inline assembly code 8401 // which actually uses it. This would allow LLVM to use $1 for inline 8402 // assembly operands if the user's assembly code doesn't use it. 8403 return "~{$1}"; 8404 } 8405 8406 bool handleTargetFeatures(std::vector<std::string> &Features, 8407 DiagnosticsEngine &Diags) override { 8408 IsMips16 = false; 8409 IsMicromips = false; 8410 IsNan2008 = isNaN2008Default(); 8411 IsSingleFloat = false; 8412 FloatABI = HardFloat; 8413 DspRev = NoDSP; 8414 HasFP64 = isFP64Default(); 8415 8416 for (const auto &Feature : Features) { 8417 if (Feature == "+single-float") 8418 IsSingleFloat = true; 8419 else if (Feature == "+soft-float") 8420 FloatABI = SoftFloat; 8421 else if (Feature == "+mips16") 8422 IsMips16 = true; 8423 else if (Feature == "+micromips") 8424 IsMicromips = true; 8425 else if (Feature == "+dsp") 8426 DspRev = std::max(DspRev, DSP1); 8427 else if (Feature == "+dspr2") 8428 DspRev = std::max(DspRev, DSP2); 8429 else if (Feature == "+msa") 8430 HasMSA = true; 8431 else if (Feature == "+nomadd4") 8432 DisableMadd4 = true; 8433 else if (Feature == "+fp64") 8434 HasFP64 = true; 8435 else if (Feature == "-fp64") 8436 HasFP64 = false; 8437 else if (Feature == "+nan2008") 8438 IsNan2008 = true; 8439 else if (Feature == "-nan2008") 8440 IsNan2008 = false; 8441 else if (Feature == "+noabicalls") 8442 IsNoABICalls = true; 8443 } 8444 8445 setDataLayout(); 8446 8447 return true; 8448 } 8449 8450 int getEHDataRegisterNumber(unsigned RegNo) const override { 8451 if (RegNo == 0) return 4; 8452 if (RegNo == 1) return 5; 8453 return -1; 8454 } 8455 8456 bool isCLZForZeroUndef() const override { return false; } 8457 8458 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8459 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 8460 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8461 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8462 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 8463 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 8464 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 8465 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8466 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8467 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8468 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8469 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8470 {{"ra"}, "$31"}}; 8471 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 8472 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8473 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8474 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 8475 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 8476 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 8477 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8478 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8479 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8480 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8481 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8482 {{"ra"}, "$31"}}; 8483 if (ABI == "o32") 8484 return llvm::makeArrayRef(O32RegAliases); 8485 return llvm::makeArrayRef(NewABIRegAliases); 8486 } 8487 8488 bool hasInt128Type() const override { 8489 return ABI == "n32" || ABI == "n64"; 8490 } 8491 8492 bool validateTarget(DiagnosticsEngine &Diags) const override { 8493 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 8494 // this yet. It's better to fail here than on the backend assertion. 8495 if (processorSupportsGPR64() && ABI == "o32") { 8496 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8497 return false; 8498 } 8499 8500 // 64-bit ABI's require 64-bit CPU's. 8501 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 8502 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8503 return false; 8504 } 8505 8506 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 8507 // can't handle this yet. It's better to fail here than on the 8508 // backend assertion. 8509 if ((getTriple().getArch() == llvm::Triple::mips64 || 8510 getTriple().getArch() == llvm::Triple::mips64el) && 8511 ABI == "o32") { 8512 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8513 << ABI << getTriple().str(); 8514 return false; 8515 } 8516 8517 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 8518 // can't handle this yet. It's better to fail here than on the 8519 // backend assertion. 8520 if ((getTriple().getArch() == llvm::Triple::mips || 8521 getTriple().getArch() == llvm::Triple::mipsel) && 8522 (ABI == "n32" || ABI == "n64")) { 8523 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8524 << ABI << getTriple().str(); 8525 return false; 8526 } 8527 8528 return true; 8529 } 8530 }; 8531 8532 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 8533 #define BUILTIN(ID, TYPE, ATTRS) \ 8534 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8535 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8536 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8537 #include "clang/Basic/BuiltinsMips.def" 8538 }; 8539 8540 class PNaClTargetInfo : public TargetInfo { 8541 public: 8542 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8543 : TargetInfo(Triple) { 8544 this->LongAlign = 32; 8545 this->LongWidth = 32; 8546 this->PointerAlign = 32; 8547 this->PointerWidth = 32; 8548 this->IntMaxType = TargetInfo::SignedLongLong; 8549 this->Int64Type = TargetInfo::SignedLongLong; 8550 this->DoubleAlign = 64; 8551 this->LongDoubleWidth = 64; 8552 this->LongDoubleAlign = 64; 8553 this->SizeType = TargetInfo::UnsignedInt; 8554 this->PtrDiffType = TargetInfo::SignedInt; 8555 this->IntPtrType = TargetInfo::SignedInt; 8556 this->RegParmMax = 0; // Disallow regparm 8557 } 8558 8559 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 8560 Builder.defineMacro("__le32__"); 8561 Builder.defineMacro("__pnacl__"); 8562 } 8563 void getTargetDefines(const LangOptions &Opts, 8564 MacroBuilder &Builder) const override { 8565 getArchDefines(Opts, Builder); 8566 } 8567 bool hasFeature(StringRef Feature) const override { 8568 return Feature == "pnacl"; 8569 } 8570 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8571 BuiltinVaListKind getBuiltinVaListKind() const override { 8572 return TargetInfo::PNaClABIBuiltinVaList; 8573 } 8574 ArrayRef<const char *> getGCCRegNames() const override; 8575 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 8576 bool validateAsmConstraint(const char *&Name, 8577 TargetInfo::ConstraintInfo &Info) const override { 8578 return false; 8579 } 8580 8581 const char *getClobbers() const override { 8582 return ""; 8583 } 8584 }; 8585 8586 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 8587 return None; 8588 } 8589 8590 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 8591 return None; 8592 } 8593 8594 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 8595 class NaClMips32TargetInfo : public MipsTargetInfo { 8596 public: 8597 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8598 : MipsTargetInfo(Triple, Opts) {} 8599 8600 BuiltinVaListKind getBuiltinVaListKind() const override { 8601 return TargetInfo::PNaClABIBuiltinVaList; 8602 } 8603 }; 8604 8605 class Le64TargetInfo : public TargetInfo { 8606 static const Builtin::Info BuiltinInfo[]; 8607 8608 public: 8609 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8610 : TargetInfo(Triple) { 8611 NoAsmVariants = true; 8612 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 8613 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8614 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 8615 } 8616 8617 void getTargetDefines(const LangOptions &Opts, 8618 MacroBuilder &Builder) const override { 8619 DefineStd(Builder, "unix", Opts); 8620 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 8621 Builder.defineMacro("__ELF__"); 8622 } 8623 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8624 return llvm::makeArrayRef(BuiltinInfo, 8625 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 8626 } 8627 BuiltinVaListKind getBuiltinVaListKind() const override { 8628 return TargetInfo::PNaClABIBuiltinVaList; 8629 } 8630 const char *getClobbers() const override { return ""; } 8631 ArrayRef<const char *> getGCCRegNames() const override { 8632 return None; 8633 } 8634 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8635 return None; 8636 } 8637 bool validateAsmConstraint(const char *&Name, 8638 TargetInfo::ConstraintInfo &Info) const override { 8639 return false; 8640 } 8641 8642 bool hasProtectedVisibility() const override { return false; } 8643 }; 8644 8645 class WebAssemblyTargetInfo : public TargetInfo { 8646 static const Builtin::Info BuiltinInfo[]; 8647 8648 enum SIMDEnum { 8649 NoSIMD, 8650 SIMD128, 8651 } SIMDLevel; 8652 8653 public: 8654 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 8655 : TargetInfo(T), SIMDLevel(NoSIMD) { 8656 NoAsmVariants = true; 8657 SuitableAlign = 128; 8658 LargeArrayMinWidth = 128; 8659 LargeArrayAlign = 128; 8660 SimdDefaultAlign = 128; 8661 SigAtomicType = SignedLong; 8662 LongDoubleWidth = LongDoubleAlign = 128; 8663 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8664 SizeType = UnsignedInt; 8665 PtrDiffType = SignedInt; 8666 IntPtrType = SignedInt; 8667 } 8668 8669 protected: 8670 void getTargetDefines(const LangOptions &Opts, 8671 MacroBuilder &Builder) const override { 8672 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 8673 if (SIMDLevel >= SIMD128) 8674 Builder.defineMacro("__wasm_simd128__"); 8675 } 8676 8677 private: 8678 bool 8679 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 8680 StringRef CPU, 8681 const std::vector<std::string> &FeaturesVec) const override { 8682 if (CPU == "bleeding-edge") 8683 Features["simd128"] = true; 8684 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 8685 } 8686 bool hasFeature(StringRef Feature) const final { 8687 return llvm::StringSwitch<bool>(Feature) 8688 .Case("simd128", SIMDLevel >= SIMD128) 8689 .Default(false); 8690 } 8691 bool handleTargetFeatures(std::vector<std::string> &Features, 8692 DiagnosticsEngine &Diags) final { 8693 for (const auto &Feature : Features) { 8694 if (Feature == "+simd128") { 8695 SIMDLevel = std::max(SIMDLevel, SIMD128); 8696 continue; 8697 } 8698 if (Feature == "-simd128") { 8699 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 8700 continue; 8701 } 8702 8703 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 8704 << "-target-feature"; 8705 return false; 8706 } 8707 return true; 8708 } 8709 bool setCPU(const std::string &Name) final { 8710 return llvm::StringSwitch<bool>(Name) 8711 .Case("mvp", true) 8712 .Case("bleeding-edge", true) 8713 .Case("generic", true) 8714 .Default(false); 8715 } 8716 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 8717 return llvm::makeArrayRef(BuiltinInfo, 8718 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 8719 } 8720 BuiltinVaListKind getBuiltinVaListKind() const final { 8721 return VoidPtrBuiltinVaList; 8722 } 8723 ArrayRef<const char *> getGCCRegNames() const final { 8724 return None; 8725 } 8726 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 8727 return None; 8728 } 8729 bool 8730 validateAsmConstraint(const char *&Name, 8731 TargetInfo::ConstraintInfo &Info) const final { 8732 return false; 8733 } 8734 const char *getClobbers() const final { return ""; } 8735 bool isCLZForZeroUndef() const final { return false; } 8736 bool hasInt128Type() const final { return true; } 8737 IntType getIntTypeByWidth(unsigned BitWidth, 8738 bool IsSigned) const final { 8739 // WebAssembly prefers long long for explicitly 64-bit integers. 8740 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8741 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8742 } 8743 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8744 bool IsSigned) const final { 8745 // WebAssembly uses long long for int_least64_t and int_fast64_t. 8746 return BitWidth == 64 8747 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8748 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 8749 } 8750 }; 8751 8752 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 8753 #define BUILTIN(ID, TYPE, ATTRS) \ 8754 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8755 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8756 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8757 #include "clang/Basic/BuiltinsWebAssembly.def" 8758 }; 8759 8760 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 8761 public: 8762 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 8763 const TargetOptions &Opts) 8764 : WebAssemblyTargetInfo(T, Opts) { 8765 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8766 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 8767 } 8768 8769 protected: 8770 void getTargetDefines(const LangOptions &Opts, 8771 MacroBuilder &Builder) const override { 8772 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8773 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 8774 } 8775 }; 8776 8777 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 8778 public: 8779 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 8780 const TargetOptions &Opts) 8781 : WebAssemblyTargetInfo(T, Opts) { 8782 LongAlign = LongWidth = 64; 8783 PointerAlign = PointerWidth = 64; 8784 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8785 SizeType = UnsignedLong; 8786 PtrDiffType = SignedLong; 8787 IntPtrType = SignedLong; 8788 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 8789 } 8790 8791 protected: 8792 void getTargetDefines(const LangOptions &Opts, 8793 MacroBuilder &Builder) const override { 8794 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8795 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 8796 } 8797 }; 8798 8799 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 8800 #define BUILTIN(ID, TYPE, ATTRS) \ 8801 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8802 #include "clang/Basic/BuiltinsLe64.def" 8803 }; 8804 8805 static const unsigned SPIRAddrSpaceMap[] = { 8806 0, // Default 8807 1, // opencl_global 8808 3, // opencl_local 8809 2, // opencl_constant 8810 4, // opencl_generic 8811 0, // cuda_device 8812 0, // cuda_constant 8813 0 // cuda_shared 8814 }; 8815 class SPIRTargetInfo : public TargetInfo { 8816 public: 8817 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8818 : TargetInfo(Triple) { 8819 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 8820 "SPIR target must use unknown OS"); 8821 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 8822 "SPIR target must use unknown environment type"); 8823 TLSSupported = false; 8824 LongWidth = LongAlign = 64; 8825 AddrSpaceMap = &SPIRAddrSpaceMap; 8826 UseAddrSpaceMapMangling = true; 8827 // Define available target features 8828 // These must be defined in sorted order! 8829 NoAsmVariants = true; 8830 } 8831 void getTargetDefines(const LangOptions &Opts, 8832 MacroBuilder &Builder) const override { 8833 DefineStd(Builder, "SPIR", Opts); 8834 } 8835 bool hasFeature(StringRef Feature) const override { 8836 return Feature == "spir"; 8837 } 8838 8839 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8840 const char *getClobbers() const override { return ""; } 8841 ArrayRef<const char *> getGCCRegNames() const override { return None; } 8842 bool validateAsmConstraint(const char *&Name, 8843 TargetInfo::ConstraintInfo &info) const override { 8844 return true; 8845 } 8846 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8847 return None; 8848 } 8849 BuiltinVaListKind getBuiltinVaListKind() const override { 8850 return TargetInfo::VoidPtrBuiltinVaList; 8851 } 8852 8853 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 8854 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 8855 : CCCR_Warning; 8856 } 8857 8858 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8859 return CC_SpirFunction; 8860 } 8861 8862 void setSupportedOpenCLOpts() override { 8863 // Assume all OpenCL extensions and optional core features are supported 8864 // for SPIR since it is a generic target. 8865 getSupportedOpenCLOpts().supportAll(); 8866 } 8867 }; 8868 8869 class SPIR32TargetInfo : public SPIRTargetInfo { 8870 public: 8871 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8872 : SPIRTargetInfo(Triple, Opts) { 8873 PointerWidth = PointerAlign = 32; 8874 SizeType = TargetInfo::UnsignedInt; 8875 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8876 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8877 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8878 } 8879 void getTargetDefines(const LangOptions &Opts, 8880 MacroBuilder &Builder) const override { 8881 DefineStd(Builder, "SPIR32", Opts); 8882 } 8883 }; 8884 8885 class SPIR64TargetInfo : public SPIRTargetInfo { 8886 public: 8887 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8888 : SPIRTargetInfo(Triple, Opts) { 8889 PointerWidth = PointerAlign = 64; 8890 SizeType = TargetInfo::UnsignedLong; 8891 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8892 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8893 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8894 } 8895 void getTargetDefines(const LangOptions &Opts, 8896 MacroBuilder &Builder) const override { 8897 DefineStd(Builder, "SPIR64", Opts); 8898 } 8899 }; 8900 8901 class XCoreTargetInfo : public TargetInfo { 8902 static const Builtin::Info BuiltinInfo[]; 8903 public: 8904 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8905 : TargetInfo(Triple) { 8906 NoAsmVariants = true; 8907 LongLongAlign = 32; 8908 SuitableAlign = 32; 8909 DoubleAlign = LongDoubleAlign = 32; 8910 SizeType = UnsignedInt; 8911 PtrDiffType = SignedInt; 8912 IntPtrType = SignedInt; 8913 WCharType = UnsignedChar; 8914 WIntType = UnsignedInt; 8915 UseZeroLengthBitfieldAlignment = true; 8916 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8917 "-f64:32-a:0:32-n32"); 8918 } 8919 void getTargetDefines(const LangOptions &Opts, 8920 MacroBuilder &Builder) const override { 8921 Builder.defineMacro("__XS1B__"); 8922 } 8923 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8924 return llvm::makeArrayRef(BuiltinInfo, 8925 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8926 } 8927 BuiltinVaListKind getBuiltinVaListKind() const override { 8928 return TargetInfo::VoidPtrBuiltinVaList; 8929 } 8930 const char *getClobbers() const override { 8931 return ""; 8932 } 8933 ArrayRef<const char *> getGCCRegNames() const override { 8934 static const char * const GCCRegNames[] = { 8935 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8936 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8937 }; 8938 return llvm::makeArrayRef(GCCRegNames); 8939 } 8940 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8941 return None; 8942 } 8943 bool validateAsmConstraint(const char *&Name, 8944 TargetInfo::ConstraintInfo &Info) const override { 8945 return false; 8946 } 8947 int getEHDataRegisterNumber(unsigned RegNo) const override { 8948 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8949 return (RegNo < 2)? RegNo : -1; 8950 } 8951 bool allowsLargerPreferedTypeAlignment() const override { 8952 return false; 8953 } 8954 }; 8955 8956 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8957 #define BUILTIN(ID, TYPE, ATTRS) \ 8958 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8959 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8960 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8961 #include "clang/Basic/BuiltinsXCore.def" 8962 }; 8963 8964 // x86_32 Android target 8965 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8966 public: 8967 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8968 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8969 SuitableAlign = 32; 8970 LongDoubleWidth = 64; 8971 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8972 } 8973 }; 8974 8975 // x86_64 Android target 8976 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8977 public: 8978 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8979 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8980 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8981 } 8982 8983 bool useFloat128ManglingForLongDouble() const override { 8984 return true; 8985 } 8986 }; 8987 8988 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8989 class RenderScript32TargetInfo : public ARMleTargetInfo { 8990 public: 8991 RenderScript32TargetInfo(const llvm::Triple &Triple, 8992 const TargetOptions &Opts) 8993 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8994 Triple.getOSName(), 8995 Triple.getEnvironmentName()), 8996 Opts) { 8997 IsRenderScriptTarget = true; 8998 LongWidth = LongAlign = 64; 8999 } 9000 void getTargetDefines(const LangOptions &Opts, 9001 MacroBuilder &Builder) const override { 9002 Builder.defineMacro("__RENDERSCRIPT__"); 9003 ARMleTargetInfo::getTargetDefines(Opts, Builder); 9004 } 9005 }; 9006 9007 // 64-bit RenderScript is aarch64 9008 class RenderScript64TargetInfo : public AArch64leTargetInfo { 9009 public: 9010 RenderScript64TargetInfo(const llvm::Triple &Triple, 9011 const TargetOptions &Opts) 9012 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 9013 Triple.getOSName(), 9014 Triple.getEnvironmentName()), 9015 Opts) { 9016 IsRenderScriptTarget = true; 9017 } 9018 9019 void getTargetDefines(const LangOptions &Opts, 9020 MacroBuilder &Builder) const override { 9021 Builder.defineMacro("__RENDERSCRIPT__"); 9022 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 9023 } 9024 }; 9025 9026 /// Information about a specific microcontroller. 9027 struct MCUInfo { 9028 const char *Name; 9029 const char *DefineName; 9030 }; 9031 9032 // This list should be kept up-to-date with AVRDevices.td in LLVM. 9033 static ArrayRef<MCUInfo> AVRMcus = { 9034 { "at90s1200", "__AVR_AT90S1200__" }, 9035 { "attiny11", "__AVR_ATtiny11__" }, 9036 { "attiny12", "__AVR_ATtiny12__" }, 9037 { "attiny15", "__AVR_ATtiny15__" }, 9038 { "attiny28", "__AVR_ATtiny28__" }, 9039 { "at90s2313", "__AVR_AT90S2313__" }, 9040 { "at90s2323", "__AVR_AT90S2323__" }, 9041 { "at90s2333", "__AVR_AT90S2333__" }, 9042 { "at90s2343", "__AVR_AT90S2343__" }, 9043 { "attiny22", "__AVR_ATtiny22__" }, 9044 { "attiny26", "__AVR_ATtiny26__" }, 9045 { "at86rf401", "__AVR_AT86RF401__" }, 9046 { "at90s4414", "__AVR_AT90S4414__" }, 9047 { "at90s4433", "__AVR_AT90S4433__" }, 9048 { "at90s4434", "__AVR_AT90S4434__" }, 9049 { "at90s8515", "__AVR_AT90S8515__" }, 9050 { "at90c8534", "__AVR_AT90c8534__" }, 9051 { "at90s8535", "__AVR_AT90S8535__" }, 9052 { "ata5272", "__AVR_ATA5272__" }, 9053 { "attiny13", "__AVR_ATtiny13__" }, 9054 { "attiny13a", "__AVR_ATtiny13A__" }, 9055 { "attiny2313", "__AVR_ATtiny2313__" }, 9056 { "attiny2313a", "__AVR_ATtiny2313A__" }, 9057 { "attiny24", "__AVR_ATtiny24__" }, 9058 { "attiny24a", "__AVR_ATtiny24A__" }, 9059 { "attiny4313", "__AVR_ATtiny4313__" }, 9060 { "attiny44", "__AVR_ATtiny44__" }, 9061 { "attiny44a", "__AVR_ATtiny44A__" }, 9062 { "attiny84", "__AVR_ATtiny84__" }, 9063 { "attiny84a", "__AVR_ATtiny84A__" }, 9064 { "attiny25", "__AVR_ATtiny25__" }, 9065 { "attiny45", "__AVR_ATtiny45__" }, 9066 { "attiny85", "__AVR_ATtiny85__" }, 9067 { "attiny261", "__AVR_ATtiny261__" }, 9068 { "attiny261a", "__AVR_ATtiny261A__" }, 9069 { "attiny461", "__AVR_ATtiny461__" }, 9070 { "attiny461a", "__AVR_ATtiny461A__" }, 9071 { "attiny861", "__AVR_ATtiny861__" }, 9072 { "attiny861a", "__AVR_ATtiny861A__" }, 9073 { "attiny87", "__AVR_ATtiny87__" }, 9074 { "attiny43u", "__AVR_ATtiny43U__" }, 9075 { "attiny48", "__AVR_ATtiny48__" }, 9076 { "attiny88", "__AVR_ATtiny88__" }, 9077 { "attiny828", "__AVR_ATtiny828__" }, 9078 { "at43usb355", "__AVR_AT43USB355__" }, 9079 { "at76c711", "__AVR_AT76C711__" }, 9080 { "atmega103", "__AVR_ATmega103__" }, 9081 { "at43usb320", "__AVR_AT43USB320__" }, 9082 { "attiny167", "__AVR_ATtiny167__" }, 9083 { "at90usb82", "__AVR_AT90USB82__" }, 9084 { "at90usb162", "__AVR_AT90USB162__" }, 9085 { "ata5505", "__AVR_ATA5505__" }, 9086 { "atmega8u2", "__AVR_ATmega8U2__" }, 9087 { "atmega16u2", "__AVR_ATmega16U2__" }, 9088 { "atmega32u2", "__AVR_ATmega32U2__" }, 9089 { "attiny1634", "__AVR_ATtiny1634__" }, 9090 { "atmega8", "__AVR_ATmega8__" }, 9091 { "ata6289", "__AVR_ATA6289__" }, 9092 { "atmega8a", "__AVR_ATmega8A__" }, 9093 { "ata6285", "__AVR_ATA6285__" }, 9094 { "ata6286", "__AVR_ATA6286__" }, 9095 { "atmega48", "__AVR_ATmega48__" }, 9096 { "atmega48a", "__AVR_ATmega48A__" }, 9097 { "atmega48pa", "__AVR_ATmega48PA__" }, 9098 { "atmega48p", "__AVR_ATmega48P__" }, 9099 { "atmega88", "__AVR_ATmega88__" }, 9100 { "atmega88a", "__AVR_ATmega88A__" }, 9101 { "atmega88p", "__AVR_ATmega88P__" }, 9102 { "atmega88pa", "__AVR_ATmega88PA__" }, 9103 { "atmega8515", "__AVR_ATmega8515__" }, 9104 { "atmega8535", "__AVR_ATmega8535__" }, 9105 { "atmega8hva", "__AVR_ATmega8HVA__" }, 9106 { "at90pwm1", "__AVR_AT90PWM1__" }, 9107 { "at90pwm2", "__AVR_AT90PWM2__" }, 9108 { "at90pwm2b", "__AVR_AT90PWM2B__" }, 9109 { "at90pwm3", "__AVR_AT90PWM3__" }, 9110 { "at90pwm3b", "__AVR_AT90PWM3B__" }, 9111 { "at90pwm81", "__AVR_AT90PWM81__" }, 9112 { "ata5790", "__AVR_ATA5790__" }, 9113 { "ata5795", "__AVR_ATA5795__" }, 9114 { "atmega16", "__AVR_ATmega16__" }, 9115 { "atmega16a", "__AVR_ATmega16A__" }, 9116 { "atmega161", "__AVR_ATmega161__" }, 9117 { "atmega162", "__AVR_ATmega162__" }, 9118 { "atmega163", "__AVR_ATmega163__" }, 9119 { "atmega164a", "__AVR_ATmega164A__" }, 9120 { "atmega164p", "__AVR_ATmega164P__" }, 9121 { "atmega164pa", "__AVR_ATmega164PA__" }, 9122 { "atmega165", "__AVR_ATmega165__" }, 9123 { "atmega165a", "__AVR_ATmega165A__" }, 9124 { "atmega165p", "__AVR_ATmega165P__" }, 9125 { "atmega165pa", "__AVR_ATmega165PA__" }, 9126 { "atmega168", "__AVR_ATmega168__" }, 9127 { "atmega168a", "__AVR_ATmega168A__" }, 9128 { "atmega168p", "__AVR_ATmega168P__" }, 9129 { "atmega168pa", "__AVR_ATmega168PA__" }, 9130 { "atmega169", "__AVR_ATmega169__" }, 9131 { "atmega169a", "__AVR_ATmega169A__" }, 9132 { "atmega169p", "__AVR_ATmega169P__" }, 9133 { "atmega169pa", "__AVR_ATmega169PA__" }, 9134 { "atmega32", "__AVR_ATmega32__" }, 9135 { "atmega32a", "__AVR_ATmega32A__" }, 9136 { "atmega323", "__AVR_ATmega323__" }, 9137 { "atmega324a", "__AVR_ATmega324A__" }, 9138 { "atmega324p", "__AVR_ATmega324P__" }, 9139 { "atmega324pa", "__AVR_ATmega324PA__" }, 9140 { "atmega325", "__AVR_ATmega325__" }, 9141 { "atmega325a", "__AVR_ATmega325A__" }, 9142 { "atmega325p", "__AVR_ATmega325P__" }, 9143 { "atmega325pa", "__AVR_ATmega325PA__" }, 9144 { "atmega3250", "__AVR_ATmega3250__" }, 9145 { "atmega3250a", "__AVR_ATmega3250A__" }, 9146 { "atmega3250p", "__AVR_ATmega3250P__" }, 9147 { "atmega3250pa", "__AVR_ATmega3250PA__" }, 9148 { "atmega328", "__AVR_ATmega328__" }, 9149 { "atmega328p", "__AVR_ATmega328P__" }, 9150 { "atmega329", "__AVR_ATmega329__" }, 9151 { "atmega329a", "__AVR_ATmega329A__" }, 9152 { "atmega329p", "__AVR_ATmega329P__" }, 9153 { "atmega329pa", "__AVR_ATmega329PA__" }, 9154 { "atmega3290", "__AVR_ATmega3290__" }, 9155 { "atmega3290a", "__AVR_ATmega3290A__" }, 9156 { "atmega3290p", "__AVR_ATmega3290P__" }, 9157 { "atmega3290pa", "__AVR_ATmega3290PA__" }, 9158 { "atmega406", "__AVR_ATmega406__" }, 9159 { "atmega64", "__AVR_ATmega64__" }, 9160 { "atmega64a", "__AVR_ATmega64A__" }, 9161 { "atmega640", "__AVR_ATmega640__" }, 9162 { "atmega644", "__AVR_ATmega644__" }, 9163 { "atmega644a", "__AVR_ATmega644A__" }, 9164 { "atmega644p", "__AVR_ATmega644P__" }, 9165 { "atmega644pa", "__AVR_ATmega644PA__" }, 9166 { "atmega645", "__AVR_ATmega645__" }, 9167 { "atmega645a", "__AVR_ATmega645A__" }, 9168 { "atmega645p", "__AVR_ATmega645P__" }, 9169 { "atmega649", "__AVR_ATmega649__" }, 9170 { "atmega649a", "__AVR_ATmega649A__" }, 9171 { "atmega649p", "__AVR_ATmega649P__" }, 9172 { "atmega6450", "__AVR_ATmega6450__" }, 9173 { "atmega6450a", "__AVR_ATmega6450A__" }, 9174 { "atmega6450p", "__AVR_ATmega6450P__" }, 9175 { "atmega6490", "__AVR_ATmega6490__" }, 9176 { "atmega6490a", "__AVR_ATmega6490A__" }, 9177 { "atmega6490p", "__AVR_ATmega6490P__" }, 9178 { "atmega64rfr2", "__AVR_ATmega64RFR2__" }, 9179 { "atmega644rfr2", "__AVR_ATmega644RFR2__" }, 9180 { "atmega16hva", "__AVR_ATmega16HVA__" }, 9181 { "atmega16hva2", "__AVR_ATmega16HVA2__" }, 9182 { "atmega16hvb", "__AVR_ATmega16HVB__" }, 9183 { "atmega16hvbrevb", "__AVR_ATmega16HVBREVB__" }, 9184 { "atmega32hvb", "__AVR_ATmega32HVB__" }, 9185 { "atmega32hvbrevb", "__AVR_ATmega32HVBREVB__" }, 9186 { "atmega64hve", "__AVR_ATmega64HVE__" }, 9187 { "at90can32", "__AVR_AT90CAN32__" }, 9188 { "at90can64", "__AVR_AT90CAN64__" }, 9189 { "at90pwm161", "__AVR_AT90PWM161__" }, 9190 { "at90pwm216", "__AVR_AT90PWM216__" }, 9191 { "at90pwm316", "__AVR_AT90PWM316__" }, 9192 { "atmega32c1", "__AVR_ATmega32C1__" }, 9193 { "atmega64c1", "__AVR_ATmega64C1__" }, 9194 { "atmega16m1", "__AVR_ATmega16M1__" }, 9195 { "atmega32m1", "__AVR_ATmega32M1__" }, 9196 { "atmega64m1", "__AVR_ATmega64M1__" }, 9197 { "atmega16u4", "__AVR_ATmega16U4__" }, 9198 { "atmega32u4", "__AVR_ATmega32U4__" }, 9199 { "atmega32u6", "__AVR_ATmega32U6__" }, 9200 { "at90usb646", "__AVR_AT90USB646__" }, 9201 { "at90usb647", "__AVR_AT90USB647__" }, 9202 { "at90scr100", "__AVR_AT90SCR100__" }, 9203 { "at94k", "__AVR_AT94K__" }, 9204 { "m3000", "__AVR_AT000__" }, 9205 { "atmega128", "__AVR_ATmega128__" }, 9206 { "atmega128a", "__AVR_ATmega128A__" }, 9207 { "atmega1280", "__AVR_ATmega1280__" }, 9208 { "atmega1281", "__AVR_ATmega1281__" }, 9209 { "atmega1284", "__AVR_ATmega1284__" }, 9210 { "atmega1284p", "__AVR_ATmega1284P__" }, 9211 { "atmega128rfa1", "__AVR_ATmega128RFA1__" }, 9212 { "atmega128rfr2", "__AVR_ATmega128RFR2__" }, 9213 { "atmega1284rfr2", "__AVR_ATmega1284RFR2__" }, 9214 { "at90can128", "__AVR_AT90CAN128__" }, 9215 { "at90usb1286", "__AVR_AT90USB1286__" }, 9216 { "at90usb1287", "__AVR_AT90USB1287__" }, 9217 { "atmega2560", "__AVR_ATmega2560__" }, 9218 { "atmega2561", "__AVR_ATmega2561__" }, 9219 { "atmega256rfr2", "__AVR_ATmega256RFR2__" }, 9220 { "atmega2564rfr2", "__AVR_ATmega2564RFR2__" }, 9221 { "atxmega16a4", "__AVR_ATxmega16A4__" }, 9222 { "atxmega16a4u", "__AVR_ATxmega16a4U__" }, 9223 { "atxmega16c4", "__AVR_ATxmega16C4__" }, 9224 { "atxmega16d4", "__AVR_ATxmega16D4__" }, 9225 { "atxmega32a4", "__AVR_ATxmega32A4__" }, 9226 { "atxmega32a4u", "__AVR_ATxmega32A4U__" }, 9227 { "atxmega32c4", "__AVR_ATxmega32C4__" }, 9228 { "atxmega32d4", "__AVR_ATxmega32D4__" }, 9229 { "atxmega32e5", "__AVR_ATxmega32E5__" }, 9230 { "atxmega16e5", "__AVR_ATxmega16E5__" }, 9231 { "atxmega8e5", "__AVR_ATxmega8E5__" }, 9232 { "atxmega32x1", "__AVR_ATxmega32X1__" }, 9233 { "atxmega64a3", "__AVR_ATxmega64A3__" }, 9234 { "atxmega64a3u", "__AVR_ATxmega64A3U__" }, 9235 { "atxmega64a4u", "__AVR_ATxmega64A4U__" }, 9236 { "atxmega64b1", "__AVR_ATxmega64B1__" }, 9237 { "atxmega64b3", "__AVR_ATxmega64B3__" }, 9238 { "atxmega64c3", "__AVR_ATxmega64C3__" }, 9239 { "atxmega64d3", "__AVR_ATxmega64D3__" }, 9240 { "atxmega64d4", "__AVR_ATxmega64D4__" }, 9241 { "atxmega64a1", "__AVR_ATxmega64A1__" }, 9242 { "atxmega64a1u", "__AVR_ATxmega64A1U__" }, 9243 { "atxmega128a3", "__AVR_ATxmega128A3__" }, 9244 { "atxmega128a3u", "__AVR_ATxmega128A3U__" }, 9245 { "atxmega128b1", "__AVR_ATxmega128B1__" }, 9246 { "atxmega128b3", "__AVR_ATxmega128B3__" }, 9247 { "atxmega128c3", "__AVR_ATxmega128C3__" }, 9248 { "atxmega128d3", "__AVR_ATxmega128D3__" }, 9249 { "atxmega128d4", "__AVR_ATxmega128D4__" }, 9250 { "atxmega192a3", "__AVR_ATxmega192A3__" }, 9251 { "atxmega192a3u", "__AVR_ATxmega192A3U__" }, 9252 { "atxmega192c3", "__AVR_ATxmega192C3__" }, 9253 { "atxmega192d3", "__AVR_ATxmega192D3__" }, 9254 { "atxmega256a3", "__AVR_ATxmega256A3__" }, 9255 { "atxmega256a3u", "__AVR_ATxmega256A3U__" }, 9256 { "atxmega256a3b", "__AVR_ATxmega256A3B__" }, 9257 { "atxmega256a3bu", "__AVR_ATxmega256A3BU__" }, 9258 { "atxmega256c3", "__AVR_ATxmega256C3__" }, 9259 { "atxmega256d3", "__AVR_ATxmega256D3__" }, 9260 { "atxmega384c3", "__AVR_ATxmega384C3__" }, 9261 { "atxmega384d3", "__AVR_ATxmega384D3__" }, 9262 { "atxmega128a1", "__AVR_ATxmega128A1__" }, 9263 { "atxmega128a1u", "__AVR_ATxmega128A1U__" }, 9264 { "atxmega128a4u", "__AVR_ATxmega128a4U__" }, 9265 { "attiny4", "__AVR_ATtiny4__" }, 9266 { "attiny5", "__AVR_ATtiny5__" }, 9267 { "attiny9", "__AVR_ATtiny9__" }, 9268 { "attiny10", "__AVR_ATtiny10__" }, 9269 { "attiny20", "__AVR_ATtiny20__" }, 9270 { "attiny40", "__AVR_ATtiny40__" }, 9271 { "attiny102", "__AVR_ATtiny102__" }, 9272 { "attiny104", "__AVR_ATtiny104__" }, 9273 }; 9274 9275 // AVR Target 9276 class AVRTargetInfo : public TargetInfo { 9277 public: 9278 AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 9279 : TargetInfo(Triple) { 9280 TLSSupported = false; 9281 PointerWidth = 16; 9282 PointerAlign = 8; 9283 IntWidth = 16; 9284 IntAlign = 8; 9285 LongWidth = 32; 9286 LongAlign = 8; 9287 LongLongWidth = 64; 9288 LongLongAlign = 8; 9289 SuitableAlign = 8; 9290 DefaultAlignForAttributeAligned = 8; 9291 HalfWidth = 16; 9292 HalfAlign = 8; 9293 FloatWidth = 32; 9294 FloatAlign = 8; 9295 DoubleWidth = 32; 9296 DoubleAlign = 8; 9297 DoubleFormat = &llvm::APFloat::IEEEsingle(); 9298 LongDoubleWidth = 32; 9299 LongDoubleAlign = 8; 9300 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 9301 SizeType = UnsignedInt; 9302 PtrDiffType = SignedInt; 9303 IntPtrType = SignedInt; 9304 Char16Type = UnsignedInt; 9305 WCharType = SignedInt; 9306 WIntType = SignedInt; 9307 Char32Type = UnsignedLong; 9308 SigAtomicType = SignedChar; 9309 resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64" 9310 "-f32:32:32-f64:64:64-n8"); 9311 } 9312 9313 void getTargetDefines(const LangOptions &Opts, 9314 MacroBuilder &Builder) const override { 9315 Builder.defineMacro("AVR"); 9316 Builder.defineMacro("__AVR"); 9317 Builder.defineMacro("__AVR__"); 9318 9319 if (!this->CPU.empty()) { 9320 auto It = std::find_if(AVRMcus.begin(), AVRMcus.end(), 9321 [&](const MCUInfo &Info) { return Info.Name == this->CPU; }); 9322 9323 if (It != AVRMcus.end()) 9324 Builder.defineMacro(It->DefineName); 9325 } 9326 } 9327 9328 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 9329 return None; 9330 } 9331 9332 BuiltinVaListKind getBuiltinVaListKind() const override { 9333 return TargetInfo::VoidPtrBuiltinVaList; 9334 } 9335 9336 const char *getClobbers() const override { 9337 return ""; 9338 } 9339 9340 ArrayRef<const char *> getGCCRegNames() const override { 9341 static const char * const GCCRegNames[] = { 9342 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 9343 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 9344 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 9345 "r24", "r25", "X", "Y", "Z", "SP" 9346 }; 9347 return llvm::makeArrayRef(GCCRegNames); 9348 } 9349 9350 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 9351 return None; 9352 } 9353 9354 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 9355 static const TargetInfo::AddlRegName AddlRegNames[] = { 9356 { { "r26", "r27"}, 26 }, 9357 { { "r28", "r29"}, 27 }, 9358 { { "r30", "r31"}, 28 }, 9359 { { "SPL", "SPH"}, 29 }, 9360 }; 9361 return llvm::makeArrayRef(AddlRegNames); 9362 } 9363 9364 bool validateAsmConstraint(const char *&Name, 9365 TargetInfo::ConstraintInfo &Info) const override { 9366 // There aren't any multi-character AVR specific constraints. 9367 if (StringRef(Name).size() > 1) return false; 9368 9369 switch (*Name) { 9370 default: return false; 9371 case 'a': // Simple upper registers 9372 case 'b': // Base pointer registers pairs 9373 case 'd': // Upper register 9374 case 'l': // Lower registers 9375 case 'e': // Pointer register pairs 9376 case 'q': // Stack pointer register 9377 case 'r': // Any register 9378 case 'w': // Special upper register pairs 9379 case 't': // Temporary register 9380 case 'x': case 'X': // Pointer register pair X 9381 case 'y': case 'Y': // Pointer register pair Y 9382 case 'z': case 'Z': // Pointer register pair Z 9383 Info.setAllowsRegister(); 9384 return true; 9385 case 'I': // 6-bit positive integer constant 9386 Info.setRequiresImmediate(0, 63); 9387 return true; 9388 case 'J': // 6-bit negative integer constant 9389 Info.setRequiresImmediate(-63, 0); 9390 return true; 9391 case 'K': // Integer constant (Range: 2) 9392 Info.setRequiresImmediate(2); 9393 return true; 9394 case 'L': // Integer constant (Range: 0) 9395 Info.setRequiresImmediate(0); 9396 return true; 9397 case 'M': // 8-bit integer constant 9398 Info.setRequiresImmediate(0, 0xff); 9399 return true; 9400 case 'N': // Integer constant (Range: -1) 9401 Info.setRequiresImmediate(-1); 9402 return true; 9403 case 'O': // Integer constant (Range: 8, 16, 24) 9404 Info.setRequiresImmediate({8, 16, 24}); 9405 return true; 9406 case 'P': // Integer constant (Range: 1) 9407 Info.setRequiresImmediate(1); 9408 return true; 9409 case 'R': // Integer constant (Range: -6 to 5) 9410 Info.setRequiresImmediate(-6, 5); 9411 return true; 9412 case 'G': // Floating point constant 9413 case 'Q': // A memory address based on Y or Z pointer with displacement. 9414 return true; 9415 } 9416 9417 return false; 9418 } 9419 9420 IntType getIntTypeByWidth(unsigned BitWidth, 9421 bool IsSigned) const final { 9422 // AVR prefers int for 16-bit integers. 9423 return BitWidth == 16 ? (IsSigned ? SignedInt : UnsignedInt) 9424 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 9425 } 9426 9427 IntType getLeastIntTypeByWidth(unsigned BitWidth, 9428 bool IsSigned) const final { 9429 // AVR uses int for int_least16_t and int_fast16_t. 9430 return BitWidth == 16 9431 ? (IsSigned ? SignedInt : UnsignedInt) 9432 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 9433 } 9434 9435 bool setCPU(const std::string &Name) override { 9436 bool IsFamily = llvm::StringSwitch<bool>(Name) 9437 .Case("avr1", true) 9438 .Case("avr2", true) 9439 .Case("avr25", true) 9440 .Case("avr3", true) 9441 .Case("avr31", true) 9442 .Case("avr35", true) 9443 .Case("avr4", true) 9444 .Case("avr5", true) 9445 .Case("avr51", true) 9446 .Case("avr6", true) 9447 .Case("avrxmega1", true) 9448 .Case("avrxmega2", true) 9449 .Case("avrxmega3", true) 9450 .Case("avrxmega4", true) 9451 .Case("avrxmega5", true) 9452 .Case("avrxmega6", true) 9453 .Case("avrxmega7", true) 9454 .Case("avrtiny", true) 9455 .Default(false); 9456 9457 if (IsFamily) this->CPU = Name; 9458 9459 bool IsMCU = std::find_if(AVRMcus.begin(), AVRMcus.end(), 9460 [&](const MCUInfo &Info) { return Info.Name == Name; }) != AVRMcus.end(); 9461 9462 if (IsMCU) this->CPU = Name; 9463 9464 return IsFamily || IsMCU; 9465 } 9466 9467 protected: 9468 std::string CPU; 9469 }; 9470 9471 } // end anonymous namespace 9472 9473 //===----------------------------------------------------------------------===// 9474 // Driver code 9475 //===----------------------------------------------------------------------===// 9476 9477 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 9478 const TargetOptions &Opts) { 9479 llvm::Triple::OSType os = Triple.getOS(); 9480 9481 switch (Triple.getArch()) { 9482 default: 9483 return nullptr; 9484 9485 case llvm::Triple::xcore: 9486 return new XCoreTargetInfo(Triple, Opts); 9487 9488 case llvm::Triple::hexagon: 9489 return new HexagonTargetInfo(Triple, Opts); 9490 9491 case llvm::Triple::lanai: 9492 return new LanaiTargetInfo(Triple, Opts); 9493 9494 case llvm::Triple::aarch64: 9495 if (Triple.isOSDarwin()) 9496 return new DarwinAArch64TargetInfo(Triple, Opts); 9497 9498 switch (os) { 9499 case llvm::Triple::CloudABI: 9500 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 9501 case llvm::Triple::FreeBSD: 9502 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9503 case llvm::Triple::Fuchsia: 9504 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9505 case llvm::Triple::Linux: 9506 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9507 case llvm::Triple::NetBSD: 9508 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9509 case llvm::Triple::OpenBSD: 9510 return new OpenBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9511 case llvm::Triple::Win32: 9512 return new MicrosoftARM64TargetInfo(Triple, Opts); 9513 default: 9514 return new AArch64leTargetInfo(Triple, Opts); 9515 } 9516 9517 case llvm::Triple::aarch64_be: 9518 switch (os) { 9519 case llvm::Triple::FreeBSD: 9520 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9521 case llvm::Triple::Fuchsia: 9522 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9523 case llvm::Triple::Linux: 9524 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9525 case llvm::Triple::NetBSD: 9526 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9527 default: 9528 return new AArch64beTargetInfo(Triple, Opts); 9529 } 9530 9531 case llvm::Triple::arm: 9532 case llvm::Triple::thumb: 9533 if (Triple.isOSBinFormatMachO()) 9534 return new DarwinARMTargetInfo(Triple, Opts); 9535 9536 switch (os) { 9537 case llvm::Triple::CloudABI: 9538 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts); 9539 case llvm::Triple::Linux: 9540 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 9541 case llvm::Triple::FreeBSD: 9542 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9543 case llvm::Triple::NetBSD: 9544 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9545 case llvm::Triple::OpenBSD: 9546 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9547 case llvm::Triple::Bitrig: 9548 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 9549 case llvm::Triple::RTEMS: 9550 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 9551 case llvm::Triple::NaCl: 9552 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 9553 case llvm::Triple::Win32: 9554 switch (Triple.getEnvironment()) { 9555 case llvm::Triple::Cygnus: 9556 return new CygwinARMTargetInfo(Triple, Opts); 9557 case llvm::Triple::GNU: 9558 return new MinGWARMTargetInfo(Triple, Opts); 9559 case llvm::Triple::Itanium: 9560 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 9561 case llvm::Triple::MSVC: 9562 default: // Assume MSVC for unknown environments 9563 return new MicrosoftARMleTargetInfo(Triple, Opts); 9564 } 9565 default: 9566 return new ARMleTargetInfo(Triple, Opts); 9567 } 9568 9569 case llvm::Triple::armeb: 9570 case llvm::Triple::thumbeb: 9571 if (Triple.isOSDarwin()) 9572 return new DarwinARMTargetInfo(Triple, Opts); 9573 9574 switch (os) { 9575 case llvm::Triple::Linux: 9576 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9577 case llvm::Triple::FreeBSD: 9578 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9579 case llvm::Triple::NetBSD: 9580 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9581 case llvm::Triple::OpenBSD: 9582 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9583 case llvm::Triple::Bitrig: 9584 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9585 case llvm::Triple::RTEMS: 9586 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9587 case llvm::Triple::NaCl: 9588 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9589 default: 9590 return new ARMbeTargetInfo(Triple, Opts); 9591 } 9592 9593 case llvm::Triple::avr: 9594 return new AVRTargetInfo(Triple, Opts); 9595 case llvm::Triple::bpfeb: 9596 case llvm::Triple::bpfel: 9597 return new BPFTargetInfo(Triple, Opts); 9598 9599 case llvm::Triple::msp430: 9600 return new MSP430TargetInfo(Triple, Opts); 9601 9602 case llvm::Triple::nios2: 9603 return new LinuxTargetInfo<Nios2TargetInfo>(Triple, Opts); 9604 9605 case llvm::Triple::mips: 9606 switch (os) { 9607 case llvm::Triple::Linux: 9608 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9609 case llvm::Triple::RTEMS: 9610 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9611 case llvm::Triple::FreeBSD: 9612 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9613 case llvm::Triple::NetBSD: 9614 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9615 default: 9616 return new MipsTargetInfo(Triple, Opts); 9617 } 9618 9619 case llvm::Triple::mipsel: 9620 switch (os) { 9621 case llvm::Triple::Linux: 9622 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9623 case llvm::Triple::RTEMS: 9624 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9625 case llvm::Triple::FreeBSD: 9626 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9627 case llvm::Triple::NetBSD: 9628 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9629 case llvm::Triple::NaCl: 9630 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 9631 default: 9632 return new MipsTargetInfo(Triple, Opts); 9633 } 9634 9635 case llvm::Triple::mips64: 9636 switch (os) { 9637 case llvm::Triple::Linux: 9638 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9639 case llvm::Triple::RTEMS: 9640 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9641 case llvm::Triple::FreeBSD: 9642 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9643 case llvm::Triple::NetBSD: 9644 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9645 case llvm::Triple::OpenBSD: 9646 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9647 default: 9648 return new MipsTargetInfo(Triple, Opts); 9649 } 9650 9651 case llvm::Triple::mips64el: 9652 switch (os) { 9653 case llvm::Triple::Linux: 9654 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9655 case llvm::Triple::RTEMS: 9656 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9657 case llvm::Triple::FreeBSD: 9658 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9659 case llvm::Triple::NetBSD: 9660 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9661 case llvm::Triple::OpenBSD: 9662 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9663 default: 9664 return new MipsTargetInfo(Triple, Opts); 9665 } 9666 9667 case llvm::Triple::le32: 9668 switch (os) { 9669 case llvm::Triple::NaCl: 9670 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 9671 default: 9672 return nullptr; 9673 } 9674 9675 case llvm::Triple::le64: 9676 return new Le64TargetInfo(Triple, Opts); 9677 9678 case llvm::Triple::ppc: 9679 if (Triple.isOSDarwin()) 9680 return new DarwinPPC32TargetInfo(Triple, Opts); 9681 switch (os) { 9682 case llvm::Triple::Linux: 9683 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 9684 case llvm::Triple::FreeBSD: 9685 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9686 case llvm::Triple::NetBSD: 9687 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9688 case llvm::Triple::OpenBSD: 9689 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9690 case llvm::Triple::RTEMS: 9691 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 9692 default: 9693 return new PPC32TargetInfo(Triple, Opts); 9694 } 9695 9696 case llvm::Triple::ppc64: 9697 if (Triple.isOSDarwin()) 9698 return new DarwinPPC64TargetInfo(Triple, Opts); 9699 switch (os) { 9700 case llvm::Triple::Linux: 9701 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9702 case llvm::Triple::Lv2: 9703 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 9704 case llvm::Triple::FreeBSD: 9705 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9706 case llvm::Triple::NetBSD: 9707 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9708 default: 9709 return new PPC64TargetInfo(Triple, Opts); 9710 } 9711 9712 case llvm::Triple::ppc64le: 9713 switch (os) { 9714 case llvm::Triple::Linux: 9715 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9716 case llvm::Triple::NetBSD: 9717 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9718 default: 9719 return new PPC64TargetInfo(Triple, Opts); 9720 } 9721 9722 case llvm::Triple::nvptx: 9723 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/32); 9724 case llvm::Triple::nvptx64: 9725 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64); 9726 9727 case llvm::Triple::amdgcn: 9728 case llvm::Triple::r600: 9729 return new AMDGPUTargetInfo(Triple, Opts); 9730 9731 case llvm::Triple::sparc: 9732 switch (os) { 9733 case llvm::Triple::Linux: 9734 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9735 case llvm::Triple::Solaris: 9736 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9737 case llvm::Triple::NetBSD: 9738 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9739 case llvm::Triple::OpenBSD: 9740 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9741 case llvm::Triple::RTEMS: 9742 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9743 default: 9744 return new SparcV8TargetInfo(Triple, Opts); 9745 } 9746 9747 // The 'sparcel' architecture copies all the above cases except for Solaris. 9748 case llvm::Triple::sparcel: 9749 switch (os) { 9750 case llvm::Triple::Linux: 9751 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9752 case llvm::Triple::NetBSD: 9753 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9754 case llvm::Triple::OpenBSD: 9755 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9756 case llvm::Triple::RTEMS: 9757 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9758 default: 9759 return new SparcV8elTargetInfo(Triple, Opts); 9760 } 9761 9762 case llvm::Triple::sparcv9: 9763 switch (os) { 9764 case llvm::Triple::Linux: 9765 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9766 case llvm::Triple::Solaris: 9767 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9768 case llvm::Triple::NetBSD: 9769 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9770 case llvm::Triple::OpenBSD: 9771 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9772 case llvm::Triple::FreeBSD: 9773 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9774 default: 9775 return new SparcV9TargetInfo(Triple, Opts); 9776 } 9777 9778 case llvm::Triple::systemz: 9779 switch (os) { 9780 case llvm::Triple::Linux: 9781 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 9782 default: 9783 return new SystemZTargetInfo(Triple, Opts); 9784 } 9785 9786 case llvm::Triple::tce: 9787 return new TCETargetInfo(Triple, Opts); 9788 9789 case llvm::Triple::tcele: 9790 return new TCELETargetInfo(Triple, Opts); 9791 9792 case llvm::Triple::x86: 9793 if (Triple.isOSDarwin()) 9794 return new DarwinI386TargetInfo(Triple, Opts); 9795 9796 switch (os) { 9797 case llvm::Triple::Ananas: 9798 return new AnanasTargetInfo<X86_32TargetInfo>(Triple, Opts); 9799 case llvm::Triple::CloudABI: 9800 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 9801 case llvm::Triple::Linux: { 9802 switch (Triple.getEnvironment()) { 9803 default: 9804 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 9805 case llvm::Triple::Android: 9806 return new AndroidX86_32TargetInfo(Triple, Opts); 9807 } 9808 } 9809 case llvm::Triple::DragonFly: 9810 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9811 case llvm::Triple::NetBSD: 9812 return new NetBSDI386TargetInfo(Triple, Opts); 9813 case llvm::Triple::OpenBSD: 9814 return new OpenBSDI386TargetInfo(Triple, Opts); 9815 case llvm::Triple::Bitrig: 9816 return new BitrigI386TargetInfo(Triple, Opts); 9817 case llvm::Triple::FreeBSD: 9818 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9819 case llvm::Triple::KFreeBSD: 9820 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9821 case llvm::Triple::Minix: 9822 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 9823 case llvm::Triple::Solaris: 9824 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 9825 case llvm::Triple::Win32: { 9826 switch (Triple.getEnvironment()) { 9827 case llvm::Triple::Cygnus: 9828 return new CygwinX86_32TargetInfo(Triple, Opts); 9829 case llvm::Triple::GNU: 9830 return new MinGWX86_32TargetInfo(Triple, Opts); 9831 case llvm::Triple::Itanium: 9832 case llvm::Triple::MSVC: 9833 default: // Assume MSVC for unknown environments 9834 return new MicrosoftX86_32TargetInfo(Triple, Opts); 9835 } 9836 } 9837 case llvm::Triple::Haiku: 9838 return new HaikuX86_32TargetInfo(Triple, Opts); 9839 case llvm::Triple::RTEMS: 9840 return new RTEMSX86_32TargetInfo(Triple, Opts); 9841 case llvm::Triple::NaCl: 9842 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 9843 case llvm::Triple::ELFIAMCU: 9844 return new MCUX86_32TargetInfo(Triple, Opts); 9845 default: 9846 return new X86_32TargetInfo(Triple, Opts); 9847 } 9848 9849 case llvm::Triple::x86_64: 9850 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 9851 return new DarwinX86_64TargetInfo(Triple, Opts); 9852 9853 switch (os) { 9854 case llvm::Triple::Ananas: 9855 return new AnanasTargetInfo<X86_64TargetInfo>(Triple, Opts); 9856 case llvm::Triple::CloudABI: 9857 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 9858 case llvm::Triple::Linux: { 9859 switch (Triple.getEnvironment()) { 9860 default: 9861 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 9862 case llvm::Triple::Android: 9863 return new AndroidX86_64TargetInfo(Triple, Opts); 9864 } 9865 } 9866 case llvm::Triple::DragonFly: 9867 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9868 case llvm::Triple::NetBSD: 9869 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9870 case llvm::Triple::OpenBSD: 9871 return new OpenBSDX86_64TargetInfo(Triple, Opts); 9872 case llvm::Triple::Bitrig: 9873 return new BitrigX86_64TargetInfo(Triple, Opts); 9874 case llvm::Triple::FreeBSD: 9875 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9876 case llvm::Triple::Fuchsia: 9877 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts); 9878 case llvm::Triple::KFreeBSD: 9879 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9880 case llvm::Triple::Solaris: 9881 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 9882 case llvm::Triple::Win32: { 9883 switch (Triple.getEnvironment()) { 9884 case llvm::Triple::Cygnus: 9885 return new CygwinX86_64TargetInfo(Triple, Opts); 9886 case llvm::Triple::GNU: 9887 return new MinGWX86_64TargetInfo(Triple, Opts); 9888 case llvm::Triple::MSVC: 9889 default: // Assume MSVC for unknown environments 9890 return new MicrosoftX86_64TargetInfo(Triple, Opts); 9891 } 9892 } 9893 case llvm::Triple::Haiku: 9894 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 9895 case llvm::Triple::NaCl: 9896 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 9897 case llvm::Triple::PS4: 9898 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 9899 default: 9900 return new X86_64TargetInfo(Triple, Opts); 9901 } 9902 9903 case llvm::Triple::spir: { 9904 if (Triple.getOS() != llvm::Triple::UnknownOS || 9905 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9906 return nullptr; 9907 return new SPIR32TargetInfo(Triple, Opts); 9908 } 9909 case llvm::Triple::spir64: { 9910 if (Triple.getOS() != llvm::Triple::UnknownOS || 9911 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9912 return nullptr; 9913 return new SPIR64TargetInfo(Triple, Opts); 9914 } 9915 case llvm::Triple::wasm32: 9916 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9917 Triple.getVendor() != llvm::Triple::UnknownVendor || 9918 Triple.getOS() != llvm::Triple::UnknownOS || 9919 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9920 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9921 return nullptr; 9922 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 9923 case llvm::Triple::wasm64: 9924 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9925 Triple.getVendor() != llvm::Triple::UnknownVendor || 9926 Triple.getOS() != llvm::Triple::UnknownOS || 9927 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9928 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9929 return nullptr; 9930 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 9931 9932 case llvm::Triple::renderscript32: 9933 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 9934 case llvm::Triple::renderscript64: 9935 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 9936 } 9937 } 9938 9939 /// CreateTargetInfo - Return the target info object for the specified target 9940 /// options. 9941 TargetInfo * 9942 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 9943 const std::shared_ptr<TargetOptions> &Opts) { 9944 llvm::Triple Triple(Opts->Triple); 9945 9946 // Construct the target 9947 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 9948 if (!Target) { 9949 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 9950 return nullptr; 9951 } 9952 Target->TargetOpts = Opts; 9953 9954 // Set the target CPU if specified. 9955 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 9956 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 9957 return nullptr; 9958 } 9959 9960 // Set the target ABI if specified. 9961 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 9962 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 9963 return nullptr; 9964 } 9965 9966 // Set the fp math unit. 9967 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 9968 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 9969 return nullptr; 9970 } 9971 9972 // Compute the default target features, we need the target to handle this 9973 // because features may have dependencies on one another. 9974 llvm::StringMap<bool> Features; 9975 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 9976 Opts->FeaturesAsWritten)) 9977 return nullptr; 9978 9979 // Add the features to the compile options. 9980 Opts->Features.clear(); 9981 for (const auto &F : Features) 9982 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 9983 9984 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 9985 return nullptr; 9986 9987 Target->setSupportedOpenCLOpts(); 9988 Target->setOpenCLExtensionOpts(); 9989 9990 if (!Target->validateTarget(Diags)) 9991 return nullptr; 9992 9993 return Target.release(); 9994 } 9995