1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "clang/Basic/Version.h" 23 #include "llvm/ADT/APFloat.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringExtras.h" 26 #include "llvm/ADT/StringRef.h" 27 #include "llvm/ADT/StringSwitch.h" 28 #include "llvm/ADT/Triple.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/TargetParser.h" 32 #include <algorithm> 33 #include <memory> 34 35 using namespace clang; 36 37 //===----------------------------------------------------------------------===// 38 // Common code shared among targets. 39 //===----------------------------------------------------------------------===// 40 41 /// DefineStd - Define a macro name and standard variants. For example if 42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 43 /// when in GNU mode. 44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 45 const LangOptions &Opts) { 46 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 47 48 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 49 // in the user's namespace. 50 if (Opts.GNUMode) 51 Builder.defineMacro(MacroName); 52 53 // Define __unix. 54 Builder.defineMacro("__" + MacroName); 55 56 // Define __unix__. 57 Builder.defineMacro("__" + MacroName + "__"); 58 } 59 60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 61 bool Tuning = true) { 62 Builder.defineMacro("__" + CPUName); 63 Builder.defineMacro("__" + CPUName + "__"); 64 if (Tuning) 65 Builder.defineMacro("__tune_" + CPUName + "__"); 66 } 67 68 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 69 const TargetOptions &Opts); 70 71 //===----------------------------------------------------------------------===// 72 // Defines specific to certain operating systems. 73 //===----------------------------------------------------------------------===// 74 75 namespace { 76 template<typename TgtInfo> 77 class OSTargetInfo : public TgtInfo { 78 protected: 79 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 80 MacroBuilder &Builder) const=0; 81 public: 82 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 83 : TgtInfo(Triple, Opts) {} 84 void getTargetDefines(const LangOptions &Opts, 85 MacroBuilder &Builder) const override { 86 TgtInfo::getTargetDefines(Opts, Builder); 87 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 88 } 89 90 }; 91 92 // CloudABI Target 93 template <typename Target> 94 class CloudABITargetInfo : public OSTargetInfo<Target> { 95 protected: 96 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 97 MacroBuilder &Builder) const override { 98 Builder.defineMacro("__CloudABI__"); 99 Builder.defineMacro("__ELF__"); 100 101 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 102 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 103 Builder.defineMacro("__STDC_UTF_16__"); 104 Builder.defineMacro("__STDC_UTF_32__"); 105 } 106 107 public: 108 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 109 : OSTargetInfo<Target>(Triple, Opts) {} 110 }; 111 112 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 113 const llvm::Triple &Triple, 114 StringRef &PlatformName, 115 VersionTuple &PlatformMinVersion) { 116 Builder.defineMacro("__APPLE_CC__", "6000"); 117 Builder.defineMacro("__APPLE__"); 118 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 119 // AddressSanitizer doesn't play well with source fortification, which is on 120 // by default on Darwin. 121 if (Opts.Sanitize.has(SanitizerKind::Address)) 122 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 123 124 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 125 if (!Opts.ObjC1) { 126 // __weak is always defined, for use in blocks and with objc pointers. 127 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 128 Builder.defineMacro("__strong", ""); 129 Builder.defineMacro("__unsafe_unretained", ""); 130 } 131 132 if (Opts.Static) 133 Builder.defineMacro("__STATIC__"); 134 else 135 Builder.defineMacro("__DYNAMIC__"); 136 137 if (Opts.POSIXThreads) 138 Builder.defineMacro("_REENTRANT"); 139 140 // Get the platform type and version number from the triple. 141 unsigned Maj, Min, Rev; 142 if (Triple.isMacOSX()) { 143 Triple.getMacOSXVersion(Maj, Min, Rev); 144 PlatformName = "macosx"; 145 } else { 146 Triple.getOSVersion(Maj, Min, Rev); 147 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 148 } 149 150 // If -target arch-pc-win32-macho option specified, we're 151 // generating code for Win32 ABI. No need to emit 152 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 153 if (PlatformName == "win32") { 154 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 155 return; 156 } 157 158 // Set the appropriate OS version define. 159 if (Triple.isiOS()) { 160 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 161 char Str[6]; 162 Str[0] = '0' + Maj; 163 Str[1] = '0' + (Min / 10); 164 Str[2] = '0' + (Min % 10); 165 Str[3] = '0' + (Rev / 10); 166 Str[4] = '0' + (Rev % 10); 167 Str[5] = '\0'; 168 if (Triple.isTvOS()) 169 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 170 else 171 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 172 Str); 173 174 } else if (Triple.isWatchOS()) { 175 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 176 char Str[6]; 177 Str[0] = '0' + Maj; 178 Str[1] = '0' + (Min / 10); 179 Str[2] = '0' + (Min % 10); 180 Str[3] = '0' + (Rev / 10); 181 Str[4] = '0' + (Rev % 10); 182 Str[5] = '\0'; 183 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 184 } else if (Triple.isMacOSX()) { 185 // Note that the Driver allows versions which aren't representable in the 186 // define (because we only get a single digit for the minor and micro 187 // revision numbers). So, we limit them to the maximum representable 188 // version. 189 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 190 char Str[7]; 191 if (Maj < 10 || (Maj == 10 && Min < 10)) { 192 Str[0] = '0' + (Maj / 10); 193 Str[1] = '0' + (Maj % 10); 194 Str[2] = '0' + std::min(Min, 9U); 195 Str[3] = '0' + std::min(Rev, 9U); 196 Str[4] = '\0'; 197 } else { 198 // Handle versions > 10.9. 199 Str[0] = '0' + (Maj / 10); 200 Str[1] = '0' + (Maj % 10); 201 Str[2] = '0' + (Min / 10); 202 Str[3] = '0' + (Min % 10); 203 Str[4] = '0' + (Rev / 10); 204 Str[5] = '0' + (Rev % 10); 205 Str[6] = '\0'; 206 } 207 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 208 } 209 210 // Tell users about the kernel if there is one. 211 if (Triple.isOSDarwin()) 212 Builder.defineMacro("__MACH__"); 213 214 // The Watch ABI uses Dwarf EH. 215 if(Triple.isWatchABI()) 216 Builder.defineMacro("__ARM_DWARF_EH__"); 217 218 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 219 } 220 221 template<typename Target> 222 class DarwinTargetInfo : public OSTargetInfo<Target> { 223 protected: 224 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 225 MacroBuilder &Builder) const override { 226 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 227 this->PlatformMinVersion); 228 } 229 230 public: 231 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 232 : OSTargetInfo<Target>(Triple, Opts) { 233 // By default, no TLS, and we whitelist permitted architecture/OS 234 // combinations. 235 this->TLSSupported = false; 236 237 if (Triple.isMacOSX()) 238 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 239 else if (Triple.isiOS()) { 240 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 241 if (Triple.getArch() == llvm::Triple::x86_64 || 242 Triple.getArch() == llvm::Triple::aarch64) 243 this->TLSSupported = !Triple.isOSVersionLT(8); 244 else if (Triple.getArch() == llvm::Triple::x86 || 245 Triple.getArch() == llvm::Triple::arm || 246 Triple.getArch() == llvm::Triple::thumb) 247 this->TLSSupported = !Triple.isOSVersionLT(9); 248 } else if (Triple.isWatchOS()) 249 this->TLSSupported = !Triple.isOSVersionLT(2); 250 251 this->MCountName = "\01mcount"; 252 } 253 254 std::string isValidSectionSpecifier(StringRef SR) const override { 255 // Let MCSectionMachO validate this. 256 StringRef Segment, Section; 257 unsigned TAA, StubSize; 258 bool HasTAA; 259 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 260 TAA, HasTAA, StubSize); 261 } 262 263 const char *getStaticInitSectionSpecifier() const override { 264 // FIXME: We should return 0 when building kexts. 265 return "__TEXT,__StaticInit,regular,pure_instructions"; 266 } 267 268 /// Darwin does not support protected visibility. Darwin's "default" 269 /// is very similar to ELF's "protected"; Darwin requires a "weak" 270 /// attribute on declarations that can be dynamically replaced. 271 bool hasProtectedVisibility() const override { 272 return false; 273 } 274 275 unsigned getExnObjectAlignment() const override { 276 // The alignment of an exception object is 8-bytes for darwin since 277 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 278 // and therefore doesn't guarantee 16-byte alignment. 279 return 64; 280 } 281 }; 282 283 284 // DragonFlyBSD Target 285 template<typename Target> 286 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 287 protected: 288 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 289 MacroBuilder &Builder) const override { 290 // DragonFly defines; list based off of gcc output 291 Builder.defineMacro("__DragonFly__"); 292 Builder.defineMacro("__DragonFly_cc_version", "100001"); 293 Builder.defineMacro("__ELF__"); 294 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 295 Builder.defineMacro("__tune_i386__"); 296 DefineStd(Builder, "unix", Opts); 297 } 298 public: 299 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 300 : OSTargetInfo<Target>(Triple, Opts) { 301 switch (Triple.getArch()) { 302 default: 303 case llvm::Triple::x86: 304 case llvm::Triple::x86_64: 305 this->MCountName = ".mcount"; 306 break; 307 } 308 } 309 }; 310 311 #ifndef FREEBSD_CC_VERSION 312 #define FREEBSD_CC_VERSION 0U 313 #endif 314 315 // FreeBSD Target 316 template<typename Target> 317 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 318 protected: 319 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 320 MacroBuilder &Builder) const override { 321 // FreeBSD defines; list based off of gcc output 322 323 unsigned Release = Triple.getOSMajorVersion(); 324 if (Release == 0U) 325 Release = 8U; 326 unsigned CCVersion = FREEBSD_CC_VERSION; 327 if (CCVersion == 0U) 328 CCVersion = Release * 100000U + 1U; 329 330 Builder.defineMacro("__FreeBSD__", Twine(Release)); 331 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 332 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 333 DefineStd(Builder, "unix", Opts); 334 Builder.defineMacro("__ELF__"); 335 336 // On FreeBSD, wchar_t contains the number of the code point as 337 // used by the character set of the locale. These character sets are 338 // not necessarily a superset of ASCII. 339 // 340 // FIXME: This is wrong; the macro refers to the numerical values 341 // of wchar_t *literals*, which are not locale-dependent. However, 342 // FreeBSD systems apparently depend on us getting this wrong, and 343 // setting this to 1 is conforming even if all the basic source 344 // character literals have the same encoding as char and wchar_t. 345 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 346 } 347 public: 348 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 349 : OSTargetInfo<Target>(Triple, Opts) { 350 switch (Triple.getArch()) { 351 default: 352 case llvm::Triple::x86: 353 case llvm::Triple::x86_64: 354 this->MCountName = ".mcount"; 355 break; 356 case llvm::Triple::mips: 357 case llvm::Triple::mipsel: 358 case llvm::Triple::ppc: 359 case llvm::Triple::ppc64: 360 case llvm::Triple::ppc64le: 361 this->MCountName = "_mcount"; 362 break; 363 case llvm::Triple::arm: 364 this->MCountName = "__mcount"; 365 break; 366 } 367 } 368 }; 369 370 // GNU/kFreeBSD Target 371 template<typename Target> 372 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 373 protected: 374 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 375 MacroBuilder &Builder) const override { 376 // GNU/kFreeBSD defines; list based off of gcc output 377 378 DefineStd(Builder, "unix", Opts); 379 Builder.defineMacro("__FreeBSD_kernel__"); 380 Builder.defineMacro("__GLIBC__"); 381 Builder.defineMacro("__ELF__"); 382 if (Opts.POSIXThreads) 383 Builder.defineMacro("_REENTRANT"); 384 if (Opts.CPlusPlus) 385 Builder.defineMacro("_GNU_SOURCE"); 386 } 387 public: 388 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 389 : OSTargetInfo<Target>(Triple, Opts) {} 390 }; 391 392 // Haiku Target 393 template<typename Target> 394 class HaikuTargetInfo : public OSTargetInfo<Target> { 395 protected: 396 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 397 MacroBuilder &Builder) const override { 398 // Haiku defines; list based off of gcc output 399 Builder.defineMacro("__HAIKU__"); 400 Builder.defineMacro("__ELF__"); 401 DefineStd(Builder, "unix", Opts); 402 } 403 public: 404 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 405 : OSTargetInfo<Target>(Triple, Opts) { 406 this->SizeType = TargetInfo::UnsignedLong; 407 this->IntPtrType = TargetInfo::SignedLong; 408 this->PtrDiffType = TargetInfo::SignedLong; 409 this->ProcessIDType = TargetInfo::SignedLong; 410 this->TLSSupported = false; 411 412 } 413 }; 414 415 // Minix Target 416 template<typename Target> 417 class MinixTargetInfo : public OSTargetInfo<Target> { 418 protected: 419 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 420 MacroBuilder &Builder) const override { 421 // Minix defines 422 423 Builder.defineMacro("__minix", "3"); 424 Builder.defineMacro("_EM_WSIZE", "4"); 425 Builder.defineMacro("_EM_PSIZE", "4"); 426 Builder.defineMacro("_EM_SSIZE", "2"); 427 Builder.defineMacro("_EM_LSIZE", "4"); 428 Builder.defineMacro("_EM_FSIZE", "4"); 429 Builder.defineMacro("_EM_DSIZE", "8"); 430 Builder.defineMacro("__ELF__"); 431 DefineStd(Builder, "unix", Opts); 432 } 433 public: 434 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 435 : OSTargetInfo<Target>(Triple, Opts) {} 436 }; 437 438 // Linux target 439 template<typename Target> 440 class LinuxTargetInfo : public OSTargetInfo<Target> { 441 protected: 442 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 443 MacroBuilder &Builder) const override { 444 // Linux defines; list based off of gcc output 445 DefineStd(Builder, "unix", Opts); 446 DefineStd(Builder, "linux", Opts); 447 Builder.defineMacro("__gnu_linux__"); 448 Builder.defineMacro("__ELF__"); 449 if (Triple.isAndroid()) { 450 Builder.defineMacro("__ANDROID__", "1"); 451 unsigned Maj, Min, Rev; 452 Triple.getEnvironmentVersion(Maj, Min, Rev); 453 this->PlatformName = "android"; 454 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 455 } 456 if (Opts.POSIXThreads) 457 Builder.defineMacro("_REENTRANT"); 458 if (Opts.CPlusPlus) 459 Builder.defineMacro("_GNU_SOURCE"); 460 if (this->HasFloat128) 461 Builder.defineMacro("__FLOAT128__"); 462 } 463 public: 464 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 465 : OSTargetInfo<Target>(Triple, Opts) { 466 this->WIntType = TargetInfo::UnsignedInt; 467 468 switch (Triple.getArch()) { 469 default: 470 break; 471 case llvm::Triple::ppc: 472 case llvm::Triple::ppc64: 473 case llvm::Triple::ppc64le: 474 this->MCountName = "_mcount"; 475 break; 476 case llvm::Triple::x86: 477 case llvm::Triple::x86_64: 478 case llvm::Triple::systemz: 479 this->HasFloat128 = true; 480 break; 481 } 482 } 483 484 const char *getStaticInitSectionSpecifier() const override { 485 return ".text.startup"; 486 } 487 }; 488 489 // NetBSD Target 490 template<typename Target> 491 class NetBSDTargetInfo : public OSTargetInfo<Target> { 492 protected: 493 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 494 MacroBuilder &Builder) const override { 495 // NetBSD defines; list based off of gcc output 496 Builder.defineMacro("__NetBSD__"); 497 Builder.defineMacro("__unix__"); 498 Builder.defineMacro("__ELF__"); 499 if (Opts.POSIXThreads) 500 Builder.defineMacro("_POSIX_THREADS"); 501 502 switch (Triple.getArch()) { 503 default: 504 break; 505 case llvm::Triple::arm: 506 case llvm::Triple::armeb: 507 case llvm::Triple::thumb: 508 case llvm::Triple::thumbeb: 509 Builder.defineMacro("__ARM_DWARF_EH__"); 510 break; 511 } 512 } 513 public: 514 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 515 : OSTargetInfo<Target>(Triple, Opts) { 516 this->MCountName = "_mcount"; 517 } 518 }; 519 520 // OpenBSD Target 521 template<typename Target> 522 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 523 protected: 524 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 525 MacroBuilder &Builder) const override { 526 // OpenBSD defines; list based off of gcc output 527 528 Builder.defineMacro("__OpenBSD__"); 529 DefineStd(Builder, "unix", Opts); 530 Builder.defineMacro("__ELF__"); 531 if (Opts.POSIXThreads) 532 Builder.defineMacro("_REENTRANT"); 533 } 534 public: 535 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 536 : OSTargetInfo<Target>(Triple, Opts) { 537 this->TLSSupported = false; 538 539 switch (Triple.getArch()) { 540 default: 541 case llvm::Triple::x86: 542 case llvm::Triple::x86_64: 543 case llvm::Triple::arm: 544 case llvm::Triple::sparc: 545 this->MCountName = "__mcount"; 546 break; 547 case llvm::Triple::mips64: 548 case llvm::Triple::mips64el: 549 case llvm::Triple::ppc: 550 case llvm::Triple::sparcv9: 551 this->MCountName = "_mcount"; 552 break; 553 } 554 } 555 }; 556 557 // Bitrig Target 558 template<typename Target> 559 class BitrigTargetInfo : public OSTargetInfo<Target> { 560 protected: 561 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 562 MacroBuilder &Builder) const override { 563 // Bitrig defines; list based off of gcc output 564 565 Builder.defineMacro("__Bitrig__"); 566 DefineStd(Builder, "unix", Opts); 567 Builder.defineMacro("__ELF__"); 568 if (Opts.POSIXThreads) 569 Builder.defineMacro("_REENTRANT"); 570 571 switch (Triple.getArch()) { 572 default: 573 break; 574 case llvm::Triple::arm: 575 case llvm::Triple::armeb: 576 case llvm::Triple::thumb: 577 case llvm::Triple::thumbeb: 578 Builder.defineMacro("__ARM_DWARF_EH__"); 579 break; 580 } 581 } 582 public: 583 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 584 : OSTargetInfo<Target>(Triple, Opts) { 585 this->MCountName = "__mcount"; 586 } 587 }; 588 589 // PSP Target 590 template<typename Target> 591 class PSPTargetInfo : public OSTargetInfo<Target> { 592 protected: 593 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 594 MacroBuilder &Builder) const override { 595 // PSP defines; list based on the output of the pspdev gcc toolchain. 596 Builder.defineMacro("PSP"); 597 Builder.defineMacro("_PSP"); 598 Builder.defineMacro("__psp__"); 599 Builder.defineMacro("__ELF__"); 600 } 601 public: 602 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 603 }; 604 605 // PS3 PPU Target 606 template<typename Target> 607 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 608 protected: 609 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 610 MacroBuilder &Builder) const override { 611 // PS3 PPU defines. 612 Builder.defineMacro("__PPC__"); 613 Builder.defineMacro("__PPU__"); 614 Builder.defineMacro("__CELLOS_LV2__"); 615 Builder.defineMacro("__ELF__"); 616 Builder.defineMacro("__LP32__"); 617 Builder.defineMacro("_ARCH_PPC64"); 618 Builder.defineMacro("__powerpc64__"); 619 } 620 public: 621 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 622 : OSTargetInfo<Target>(Triple, Opts) { 623 this->LongWidth = this->LongAlign = 32; 624 this->PointerWidth = this->PointerAlign = 32; 625 this->IntMaxType = TargetInfo::SignedLongLong; 626 this->Int64Type = TargetInfo::SignedLongLong; 627 this->SizeType = TargetInfo::UnsignedInt; 628 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 629 } 630 }; 631 632 template <typename Target> 633 class PS4OSTargetInfo : public OSTargetInfo<Target> { 634 protected: 635 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 636 MacroBuilder &Builder) const override { 637 Builder.defineMacro("__FreeBSD__", "9"); 638 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 639 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 640 DefineStd(Builder, "unix", Opts); 641 Builder.defineMacro("__ELF__"); 642 Builder.defineMacro("__ORBIS__"); 643 } 644 public: 645 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 646 : OSTargetInfo<Target>(Triple, Opts) { 647 this->WCharType = this->UnsignedShort; 648 649 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 650 this->MaxTLSAlign = 256; 651 652 // On PS4, do not honor explicit bit field alignment, 653 // as in "__attribute__((aligned(2))) int b : 1;". 654 this->UseExplicitBitFieldAlignment = false; 655 656 switch (Triple.getArch()) { 657 default: 658 case llvm::Triple::x86_64: 659 this->MCountName = ".mcount"; 660 break; 661 } 662 } 663 }; 664 665 // Solaris target 666 template<typename Target> 667 class SolarisTargetInfo : public OSTargetInfo<Target> { 668 protected: 669 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 670 MacroBuilder &Builder) const override { 671 DefineStd(Builder, "sun", Opts); 672 DefineStd(Builder, "unix", Opts); 673 Builder.defineMacro("__ELF__"); 674 Builder.defineMacro("__svr4__"); 675 Builder.defineMacro("__SVR4"); 676 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 677 // newer, but to 500 for everything else. feature_test.h has a check to 678 // ensure that you are not using C99 with an old version of X/Open or C89 679 // with a new version. 680 if (Opts.C99) 681 Builder.defineMacro("_XOPEN_SOURCE", "600"); 682 else 683 Builder.defineMacro("_XOPEN_SOURCE", "500"); 684 if (Opts.CPlusPlus) 685 Builder.defineMacro("__C99FEATURES__"); 686 Builder.defineMacro("_LARGEFILE_SOURCE"); 687 Builder.defineMacro("_LARGEFILE64_SOURCE"); 688 Builder.defineMacro("__EXTENSIONS__"); 689 Builder.defineMacro("_REENTRANT"); 690 } 691 public: 692 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 693 : OSTargetInfo<Target>(Triple, Opts) { 694 this->WCharType = this->SignedInt; 695 // FIXME: WIntType should be SignedLong 696 } 697 }; 698 699 // Windows target 700 template<typename Target> 701 class WindowsTargetInfo : public OSTargetInfo<Target> { 702 protected: 703 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 704 MacroBuilder &Builder) const override { 705 Builder.defineMacro("_WIN32"); 706 } 707 void getVisualStudioDefines(const LangOptions &Opts, 708 MacroBuilder &Builder) const { 709 if (Opts.CPlusPlus) { 710 if (Opts.RTTIData) 711 Builder.defineMacro("_CPPRTTI"); 712 713 if (Opts.CXXExceptions) 714 Builder.defineMacro("_CPPUNWIND"); 715 } 716 717 if (Opts.Bool) 718 Builder.defineMacro("__BOOL_DEFINED"); 719 720 if (!Opts.CharIsSigned) 721 Builder.defineMacro("_CHAR_UNSIGNED"); 722 723 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 724 // but it works for now. 725 if (Opts.POSIXThreads) 726 Builder.defineMacro("_MT"); 727 728 if (Opts.MSCompatibilityVersion) { 729 Builder.defineMacro("_MSC_VER", 730 Twine(Opts.MSCompatibilityVersion / 100000)); 731 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 732 // FIXME We cannot encode the revision information into 32-bits 733 Builder.defineMacro("_MSC_BUILD", Twine(1)); 734 735 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 736 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 737 } 738 739 if (Opts.MicrosoftExt) { 740 Builder.defineMacro("_MSC_EXTENSIONS"); 741 742 if (Opts.CPlusPlus11) { 743 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 744 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 745 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 746 } 747 } 748 749 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 750 } 751 752 public: 753 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 754 : OSTargetInfo<Target>(Triple, Opts) {} 755 }; 756 757 template <typename Target> 758 class NaClTargetInfo : public OSTargetInfo<Target> { 759 protected: 760 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 761 MacroBuilder &Builder) const override { 762 if (Opts.POSIXThreads) 763 Builder.defineMacro("_REENTRANT"); 764 if (Opts.CPlusPlus) 765 Builder.defineMacro("_GNU_SOURCE"); 766 767 DefineStd(Builder, "unix", Opts); 768 Builder.defineMacro("__ELF__"); 769 Builder.defineMacro("__native_client__"); 770 } 771 772 public: 773 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 774 : OSTargetInfo<Target>(Triple, Opts) { 775 this->LongAlign = 32; 776 this->LongWidth = 32; 777 this->PointerAlign = 32; 778 this->PointerWidth = 32; 779 this->IntMaxType = TargetInfo::SignedLongLong; 780 this->Int64Type = TargetInfo::SignedLongLong; 781 this->DoubleAlign = 64; 782 this->LongDoubleWidth = 64; 783 this->LongDoubleAlign = 64; 784 this->LongLongWidth = 64; 785 this->LongLongAlign = 64; 786 this->SizeType = TargetInfo::UnsignedInt; 787 this->PtrDiffType = TargetInfo::SignedInt; 788 this->IntPtrType = TargetInfo::SignedInt; 789 // RegParmMax is inherited from the underlying architecture 790 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 791 if (Triple.getArch() == llvm::Triple::arm) { 792 // Handled in ARM's setABI(). 793 } else if (Triple.getArch() == llvm::Triple::x86) { 794 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 795 } else if (Triple.getArch() == llvm::Triple::x86_64) { 796 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 797 } else if (Triple.getArch() == llvm::Triple::mipsel) { 798 // Handled on mips' setDataLayout. 799 } else { 800 assert(Triple.getArch() == llvm::Triple::le32); 801 this->resetDataLayout("e-p:32:32-i64:64"); 802 } 803 } 804 }; 805 806 // WebAssembly target 807 template <typename Target> 808 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 809 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 810 MacroBuilder &Builder) const final { 811 // A common platform macro. 812 if (Opts.POSIXThreads) 813 Builder.defineMacro("_REENTRANT"); 814 // Follow g++ convention and predefine _GNU_SOURCE for C++. 815 if (Opts.CPlusPlus) 816 Builder.defineMacro("_GNU_SOURCE"); 817 } 818 819 // As an optimization, group static init code together in a section. 820 const char *getStaticInitSectionSpecifier() const final { 821 return ".text.__startup"; 822 } 823 824 public: 825 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 826 const TargetOptions &Opts) 827 : OSTargetInfo<Target>(Triple, Opts) { 828 this->MCountName = "__mcount"; 829 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 830 } 831 }; 832 833 //===----------------------------------------------------------------------===// 834 // Specific target implementations. 835 //===----------------------------------------------------------------------===// 836 837 // PPC abstract base class 838 class PPCTargetInfo : public TargetInfo { 839 static const Builtin::Info BuiltinInfo[]; 840 static const char * const GCCRegNames[]; 841 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 842 std::string CPU; 843 844 // Target cpu features. 845 bool HasVSX; 846 bool HasP8Vector; 847 bool HasP8Crypto; 848 bool HasDirectMove; 849 bool HasQPX; 850 bool HasHTM; 851 bool HasBPERMD; 852 bool HasExtDiv; 853 854 protected: 855 std::string ABI; 856 857 public: 858 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 859 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 860 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 861 HasBPERMD(false), HasExtDiv(false) { 862 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 863 SimdDefaultAlign = 128; 864 LongDoubleWidth = LongDoubleAlign = 128; 865 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 866 } 867 868 /// \brief Flags for architecture specific defines. 869 typedef enum { 870 ArchDefineNone = 0, 871 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 872 ArchDefinePpcgr = 1 << 1, 873 ArchDefinePpcsq = 1 << 2, 874 ArchDefine440 = 1 << 3, 875 ArchDefine603 = 1 << 4, 876 ArchDefine604 = 1 << 5, 877 ArchDefinePwr4 = 1 << 6, 878 ArchDefinePwr5 = 1 << 7, 879 ArchDefinePwr5x = 1 << 8, 880 ArchDefinePwr6 = 1 << 9, 881 ArchDefinePwr6x = 1 << 10, 882 ArchDefinePwr7 = 1 << 11, 883 ArchDefinePwr8 = 1 << 12, 884 ArchDefinePwr9 = 1 << 13, 885 ArchDefineA2 = 1 << 14, 886 ArchDefineA2q = 1 << 15 887 } ArchDefineTypes; 888 889 // Note: GCC recognizes the following additional cpus: 890 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 891 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 892 // titan, rs64. 893 bool setCPU(const std::string &Name) override { 894 bool CPUKnown = llvm::StringSwitch<bool>(Name) 895 .Case("generic", true) 896 .Case("440", true) 897 .Case("450", true) 898 .Case("601", true) 899 .Case("602", true) 900 .Case("603", true) 901 .Case("603e", true) 902 .Case("603ev", true) 903 .Case("604", true) 904 .Case("604e", true) 905 .Case("620", true) 906 .Case("630", true) 907 .Case("g3", true) 908 .Case("7400", true) 909 .Case("g4", true) 910 .Case("7450", true) 911 .Case("g4+", true) 912 .Case("750", true) 913 .Case("970", true) 914 .Case("g5", true) 915 .Case("a2", true) 916 .Case("a2q", true) 917 .Case("e500mc", true) 918 .Case("e5500", true) 919 .Case("power3", true) 920 .Case("pwr3", true) 921 .Case("power4", true) 922 .Case("pwr4", true) 923 .Case("power5", true) 924 .Case("pwr5", true) 925 .Case("power5x", true) 926 .Case("pwr5x", true) 927 .Case("power6", true) 928 .Case("pwr6", true) 929 .Case("power6x", true) 930 .Case("pwr6x", true) 931 .Case("power7", true) 932 .Case("pwr7", true) 933 .Case("power8", true) 934 .Case("pwr8", true) 935 .Case("power9", true) 936 .Case("pwr9", true) 937 .Case("powerpc", true) 938 .Case("ppc", true) 939 .Case("powerpc64", true) 940 .Case("ppc64", true) 941 .Case("powerpc64le", true) 942 .Case("ppc64le", true) 943 .Default(false); 944 945 if (CPUKnown) 946 CPU = Name; 947 948 return CPUKnown; 949 } 950 951 952 StringRef getABI() const override { return ABI; } 953 954 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 955 return llvm::makeArrayRef(BuiltinInfo, 956 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 957 } 958 959 bool isCLZForZeroUndef() const override { return false; } 960 961 void getTargetDefines(const LangOptions &Opts, 962 MacroBuilder &Builder) const override; 963 964 bool 965 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 966 StringRef CPU, 967 const std::vector<std::string> &FeaturesVec) const override; 968 969 bool handleTargetFeatures(std::vector<std::string> &Features, 970 DiagnosticsEngine &Diags) override; 971 bool hasFeature(StringRef Feature) const override; 972 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 973 bool Enabled) const override; 974 975 ArrayRef<const char *> getGCCRegNames() const override; 976 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 977 bool validateAsmConstraint(const char *&Name, 978 TargetInfo::ConstraintInfo &Info) const override { 979 switch (*Name) { 980 default: return false; 981 case 'O': // Zero 982 break; 983 case 'b': // Base register 984 case 'f': // Floating point register 985 Info.setAllowsRegister(); 986 break; 987 // FIXME: The following are added to allow parsing. 988 // I just took a guess at what the actions should be. 989 // Also, is more specific checking needed? I.e. specific registers? 990 case 'd': // Floating point register (containing 64-bit value) 991 case 'v': // Altivec vector register 992 Info.setAllowsRegister(); 993 break; 994 case 'w': 995 switch (Name[1]) { 996 case 'd':// VSX vector register to hold vector double data 997 case 'f':// VSX vector register to hold vector float data 998 case 's':// VSX vector register to hold scalar float data 999 case 'a':// Any VSX register 1000 case 'c':// An individual CR bit 1001 break; 1002 default: 1003 return false; 1004 } 1005 Info.setAllowsRegister(); 1006 Name++; // Skip over 'w'. 1007 break; 1008 case 'h': // `MQ', `CTR', or `LINK' register 1009 case 'q': // `MQ' register 1010 case 'c': // `CTR' register 1011 case 'l': // `LINK' register 1012 case 'x': // `CR' register (condition register) number 0 1013 case 'y': // `CR' register (condition register) 1014 case 'z': // `XER[CA]' carry bit (part of the XER register) 1015 Info.setAllowsRegister(); 1016 break; 1017 case 'I': // Signed 16-bit constant 1018 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1019 // (use `L' instead for SImode constants) 1020 case 'K': // Unsigned 16-bit constant 1021 case 'L': // Signed 16-bit constant shifted left 16 bits 1022 case 'M': // Constant larger than 31 1023 case 'N': // Exact power of 2 1024 case 'P': // Constant whose negation is a signed 16-bit constant 1025 case 'G': // Floating point constant that can be loaded into a 1026 // register with one instruction per word 1027 case 'H': // Integer/Floating point constant that can be loaded 1028 // into a register using three instructions 1029 break; 1030 case 'm': // Memory operand. Note that on PowerPC targets, m can 1031 // include addresses that update the base register. It 1032 // is therefore only safe to use `m' in an asm statement 1033 // if that asm statement accesses the operand exactly once. 1034 // The asm statement must also use `%U<opno>' as a 1035 // placeholder for the "update" flag in the corresponding 1036 // load or store instruction. For example: 1037 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1038 // is correct but: 1039 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1040 // is not. Use es rather than m if you don't want the base 1041 // register to be updated. 1042 case 'e': 1043 if (Name[1] != 's') 1044 return false; 1045 // es: A "stable" memory operand; that is, one which does not 1046 // include any automodification of the base register. Unlike 1047 // `m', this constraint can be used in asm statements that 1048 // might access the operand several times, or that might not 1049 // access it at all. 1050 Info.setAllowsMemory(); 1051 Name++; // Skip over 'e'. 1052 break; 1053 case 'Q': // Memory operand that is an offset from a register (it is 1054 // usually better to use `m' or `es' in asm statements) 1055 case 'Z': // Memory operand that is an indexed or indirect from a 1056 // register (it is usually better to use `m' or `es' in 1057 // asm statements) 1058 Info.setAllowsMemory(); 1059 Info.setAllowsRegister(); 1060 break; 1061 case 'R': // AIX TOC entry 1062 case 'a': // Address operand that is an indexed or indirect from a 1063 // register (`p' is preferable for asm statements) 1064 case 'S': // Constant suitable as a 64-bit mask operand 1065 case 'T': // Constant suitable as a 32-bit mask operand 1066 case 'U': // System V Release 4 small data area reference 1067 case 't': // AND masks that can be performed by two rldic{l, r} 1068 // instructions 1069 case 'W': // Vector constant that does not require memory 1070 case 'j': // Vector constant that is all zeros. 1071 break; 1072 // End FIXME. 1073 } 1074 return true; 1075 } 1076 std::string convertConstraint(const char *&Constraint) const override { 1077 std::string R; 1078 switch (*Constraint) { 1079 case 'e': 1080 case 'w': 1081 // Two-character constraint; add "^" hint for later parsing. 1082 R = std::string("^") + std::string(Constraint, 2); 1083 Constraint++; 1084 break; 1085 default: 1086 return TargetInfo::convertConstraint(Constraint); 1087 } 1088 return R; 1089 } 1090 const char *getClobbers() const override { 1091 return ""; 1092 } 1093 int getEHDataRegisterNumber(unsigned RegNo) const override { 1094 if (RegNo == 0) return 3; 1095 if (RegNo == 1) return 4; 1096 return -1; 1097 } 1098 1099 bool hasSjLjLowering() const override { 1100 return true; 1101 } 1102 1103 bool useFloat128ManglingForLongDouble() const override { 1104 return LongDoubleWidth == 128 && 1105 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1106 getTriple().isOSBinFormatELF(); 1107 } 1108 }; 1109 1110 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1111 #define BUILTIN(ID, TYPE, ATTRS) \ 1112 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1113 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1114 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1115 #include "clang/Basic/BuiltinsPPC.def" 1116 }; 1117 1118 /// handleTargetFeatures - Perform initialization based on the user 1119 /// configured set of features. 1120 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1121 DiagnosticsEngine &Diags) { 1122 for (const auto &Feature : Features) { 1123 if (Feature == "+vsx") { 1124 HasVSX = true; 1125 } else if (Feature == "+bpermd") { 1126 HasBPERMD = true; 1127 } else if (Feature == "+extdiv") { 1128 HasExtDiv = true; 1129 } else if (Feature == "+power8-vector") { 1130 HasP8Vector = true; 1131 } else if (Feature == "+crypto") { 1132 HasP8Crypto = true; 1133 } else if (Feature == "+direct-move") { 1134 HasDirectMove = true; 1135 } else if (Feature == "+qpx") { 1136 HasQPX = true; 1137 } else if (Feature == "+htm") { 1138 HasHTM = true; 1139 } else if (Feature == "+float128") { 1140 HasFloat128 = true; 1141 } 1142 // TODO: Finish this list and add an assert that we've handled them 1143 // all. 1144 } 1145 1146 return true; 1147 } 1148 1149 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1150 /// #defines that are not tied to a specific subtarget. 1151 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1152 MacroBuilder &Builder) const { 1153 // Target identification. 1154 Builder.defineMacro("__ppc__"); 1155 Builder.defineMacro("__PPC__"); 1156 Builder.defineMacro("_ARCH_PPC"); 1157 Builder.defineMacro("__powerpc__"); 1158 Builder.defineMacro("__POWERPC__"); 1159 if (PointerWidth == 64) { 1160 Builder.defineMacro("_ARCH_PPC64"); 1161 Builder.defineMacro("__powerpc64__"); 1162 Builder.defineMacro("__ppc64__"); 1163 Builder.defineMacro("__PPC64__"); 1164 } 1165 1166 // Target properties. 1167 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1168 Builder.defineMacro("_LITTLE_ENDIAN"); 1169 } else { 1170 if (getTriple().getOS() != llvm::Triple::NetBSD && 1171 getTriple().getOS() != llvm::Triple::OpenBSD) 1172 Builder.defineMacro("_BIG_ENDIAN"); 1173 } 1174 1175 // ABI options. 1176 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1177 Builder.defineMacro("_CALL_ELF", "1"); 1178 if (ABI == "elfv2") 1179 Builder.defineMacro("_CALL_ELF", "2"); 1180 1181 // Subtarget options. 1182 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1183 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1184 1185 // FIXME: Should be controlled by command line option. 1186 if (LongDoubleWidth == 128) 1187 Builder.defineMacro("__LONG_DOUBLE_128__"); 1188 1189 if (Opts.AltiVec) { 1190 Builder.defineMacro("__VEC__", "10206"); 1191 Builder.defineMacro("__ALTIVEC__"); 1192 } 1193 1194 // CPU identification. 1195 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1196 .Case("440", ArchDefineName) 1197 .Case("450", ArchDefineName | ArchDefine440) 1198 .Case("601", ArchDefineName) 1199 .Case("602", ArchDefineName | ArchDefinePpcgr) 1200 .Case("603", ArchDefineName | ArchDefinePpcgr) 1201 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1202 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1203 .Case("604", ArchDefineName | ArchDefinePpcgr) 1204 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1205 .Case("620", ArchDefineName | ArchDefinePpcgr) 1206 .Case("630", ArchDefineName | ArchDefinePpcgr) 1207 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1208 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1209 .Case("750", ArchDefineName | ArchDefinePpcgr) 1210 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1211 | ArchDefinePpcsq) 1212 .Case("a2", ArchDefineA2) 1213 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1214 .Case("pwr3", ArchDefinePpcgr) 1215 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1216 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1217 | ArchDefinePpcsq) 1218 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1219 | ArchDefinePpcgr | ArchDefinePpcsq) 1220 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1221 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1222 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1223 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1224 | ArchDefinePpcsq) 1225 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1226 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1227 | ArchDefinePpcgr | ArchDefinePpcsq) 1228 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1229 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1230 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1231 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 1232 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1233 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1234 | ArchDefinePpcsq) 1235 .Case("power3", ArchDefinePpcgr) 1236 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1237 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1238 | ArchDefinePpcsq) 1239 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1240 | ArchDefinePpcgr | ArchDefinePpcsq) 1241 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1242 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1243 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1244 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1245 | ArchDefinePpcsq) 1246 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1247 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1248 | ArchDefinePpcgr | ArchDefinePpcsq) 1249 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1250 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1251 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1252 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 1253 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1254 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1255 | ArchDefinePpcsq) 1256 .Default(ArchDefineNone); 1257 1258 if (defs & ArchDefineName) 1259 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1260 if (defs & ArchDefinePpcgr) 1261 Builder.defineMacro("_ARCH_PPCGR"); 1262 if (defs & ArchDefinePpcsq) 1263 Builder.defineMacro("_ARCH_PPCSQ"); 1264 if (defs & ArchDefine440) 1265 Builder.defineMacro("_ARCH_440"); 1266 if (defs & ArchDefine603) 1267 Builder.defineMacro("_ARCH_603"); 1268 if (defs & ArchDefine604) 1269 Builder.defineMacro("_ARCH_604"); 1270 if (defs & ArchDefinePwr4) 1271 Builder.defineMacro("_ARCH_PWR4"); 1272 if (defs & ArchDefinePwr5) 1273 Builder.defineMacro("_ARCH_PWR5"); 1274 if (defs & ArchDefinePwr5x) 1275 Builder.defineMacro("_ARCH_PWR5X"); 1276 if (defs & ArchDefinePwr6) 1277 Builder.defineMacro("_ARCH_PWR6"); 1278 if (defs & ArchDefinePwr6x) 1279 Builder.defineMacro("_ARCH_PWR6X"); 1280 if (defs & ArchDefinePwr7) 1281 Builder.defineMacro("_ARCH_PWR7"); 1282 if (defs & ArchDefinePwr8) 1283 Builder.defineMacro("_ARCH_PWR8"); 1284 if (defs & ArchDefinePwr9) 1285 Builder.defineMacro("_ARCH_PWR9"); 1286 if (defs & ArchDefineA2) 1287 Builder.defineMacro("_ARCH_A2"); 1288 if (defs & ArchDefineA2q) { 1289 Builder.defineMacro("_ARCH_A2Q"); 1290 Builder.defineMacro("_ARCH_QP"); 1291 } 1292 1293 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1294 Builder.defineMacro("__bg__"); 1295 Builder.defineMacro("__THW_BLUEGENE__"); 1296 Builder.defineMacro("__bgq__"); 1297 Builder.defineMacro("__TOS_BGQ__"); 1298 } 1299 1300 if (HasVSX) 1301 Builder.defineMacro("__VSX__"); 1302 if (HasP8Vector) 1303 Builder.defineMacro("__POWER8_VECTOR__"); 1304 if (HasP8Crypto) 1305 Builder.defineMacro("__CRYPTO__"); 1306 if (HasHTM) 1307 Builder.defineMacro("__HTM__"); 1308 if (HasFloat128) 1309 Builder.defineMacro("__FLOAT128__"); 1310 1311 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1312 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1313 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1314 if (PointerWidth == 64) 1315 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1316 1317 // FIXME: The following are not yet generated here by Clang, but are 1318 // generated by GCC: 1319 // 1320 // _SOFT_FLOAT_ 1321 // __RECIP_PRECISION__ 1322 // __APPLE_ALTIVEC__ 1323 // __RECIP__ 1324 // __RECIPF__ 1325 // __RSQRTE__ 1326 // __RSQRTEF__ 1327 // _SOFT_DOUBLE_ 1328 // __NO_LWSYNC__ 1329 // __HAVE_BSWAP__ 1330 // __LONGDOUBLE128 1331 // __CMODEL_MEDIUM__ 1332 // __CMODEL_LARGE__ 1333 // _CALL_SYSV 1334 // _CALL_DARWIN 1335 // __NO_FPRS__ 1336 } 1337 1338 // Handle explicit options being passed to the compiler here: if we've 1339 // explicitly turned off vsx and turned on power8-vector or direct-move then 1340 // go ahead and error since the customer has expressed a somewhat incompatible 1341 // set of options. 1342 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1343 const std::vector<std::string> &FeaturesVec) { 1344 1345 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1346 FeaturesVec.end()) { 1347 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1348 FeaturesVec.end()) { 1349 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1350 << "-mno-vsx"; 1351 return false; 1352 } 1353 1354 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1355 FeaturesVec.end()) { 1356 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1357 << "-mno-vsx"; 1358 return false; 1359 } 1360 1361 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1362 FeaturesVec.end()) { 1363 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1364 << "-mno-vsx"; 1365 return false; 1366 } 1367 } 1368 1369 return true; 1370 } 1371 1372 bool PPCTargetInfo::initFeatureMap( 1373 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1374 const std::vector<std::string> &FeaturesVec) const { 1375 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1376 .Case("7400", true) 1377 .Case("g4", true) 1378 .Case("7450", true) 1379 .Case("g4+", true) 1380 .Case("970", true) 1381 .Case("g5", true) 1382 .Case("pwr6", true) 1383 .Case("pwr7", true) 1384 .Case("pwr8", true) 1385 .Case("pwr9", true) 1386 .Case("ppc64", true) 1387 .Case("ppc64le", true) 1388 .Default(false); 1389 1390 Features["qpx"] = (CPU == "a2q"); 1391 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1392 .Case("ppc64le", true) 1393 .Case("pwr9", true) 1394 .Case("pwr8", true) 1395 .Default(false); 1396 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1397 .Case("ppc64le", true) 1398 .Case("pwr9", true) 1399 .Case("pwr8", true) 1400 .Default(false); 1401 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1402 .Case("ppc64le", true) 1403 .Case("pwr9", true) 1404 .Case("pwr8", true) 1405 .Case("pwr7", true) 1406 .Default(false); 1407 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1408 .Case("ppc64le", true) 1409 .Case("pwr9", true) 1410 .Case("pwr8", true) 1411 .Case("pwr7", true) 1412 .Default(false); 1413 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1414 .Case("ppc64le", true) 1415 .Case("pwr9", true) 1416 .Case("pwr8", true) 1417 .Default(false); 1418 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1419 .Case("ppc64le", true) 1420 .Case("pwr9", true) 1421 .Case("pwr8", true) 1422 .Case("pwr7", true) 1423 .Default(false); 1424 1425 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1426 return false; 1427 1428 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1429 } 1430 1431 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1432 return llvm::StringSwitch<bool>(Feature) 1433 .Case("powerpc", true) 1434 .Case("vsx", HasVSX) 1435 .Case("power8-vector", HasP8Vector) 1436 .Case("crypto", HasP8Crypto) 1437 .Case("direct-move", HasDirectMove) 1438 .Case("qpx", HasQPX) 1439 .Case("htm", HasHTM) 1440 .Case("bpermd", HasBPERMD) 1441 .Case("extdiv", HasExtDiv) 1442 .Case("float128", HasFloat128) 1443 .Default(false); 1444 } 1445 1446 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1447 StringRef Name, bool Enabled) const { 1448 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1449 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1450 // incompatible options. 1451 if (Enabled) { 1452 if (Name == "direct-move") { 1453 Features[Name] = Features["vsx"] = true; 1454 } else if (Name == "power8-vector") { 1455 Features[Name] = Features["vsx"] = true; 1456 } else if (Name == "float128") { 1457 Features[Name] = Features["vsx"] = true; 1458 } else { 1459 Features[Name] = true; 1460 } 1461 } else { 1462 if (Name == "vsx") { 1463 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1464 Features["float128"] = false; 1465 } else { 1466 Features[Name] = false; 1467 } 1468 } 1469 } 1470 1471 const char * const PPCTargetInfo::GCCRegNames[] = { 1472 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1473 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1474 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1475 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1476 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1477 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1478 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1479 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1480 "mq", "lr", "ctr", "ap", 1481 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1482 "xer", 1483 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1484 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1485 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1486 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1487 "vrsave", "vscr", 1488 "spe_acc", "spefscr", 1489 "sfp" 1490 }; 1491 1492 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1493 return llvm::makeArrayRef(GCCRegNames); 1494 } 1495 1496 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1497 // While some of these aliases do map to different registers 1498 // they still share the same register name. 1499 { { "0" }, "r0" }, 1500 { { "1"}, "r1" }, 1501 { { "2" }, "r2" }, 1502 { { "3" }, "r3" }, 1503 { { "4" }, "r4" }, 1504 { { "5" }, "r5" }, 1505 { { "6" }, "r6" }, 1506 { { "7" }, "r7" }, 1507 { { "8" }, "r8" }, 1508 { { "9" }, "r9" }, 1509 { { "10" }, "r10" }, 1510 { { "11" }, "r11" }, 1511 { { "12" }, "r12" }, 1512 { { "13" }, "r13" }, 1513 { { "14" }, "r14" }, 1514 { { "15" }, "r15" }, 1515 { { "16" }, "r16" }, 1516 { { "17" }, "r17" }, 1517 { { "18" }, "r18" }, 1518 { { "19" }, "r19" }, 1519 { { "20" }, "r20" }, 1520 { { "21" }, "r21" }, 1521 { { "22" }, "r22" }, 1522 { { "23" }, "r23" }, 1523 { { "24" }, "r24" }, 1524 { { "25" }, "r25" }, 1525 { { "26" }, "r26" }, 1526 { { "27" }, "r27" }, 1527 { { "28" }, "r28" }, 1528 { { "29" }, "r29" }, 1529 { { "30" }, "r30" }, 1530 { { "31" }, "r31" }, 1531 { { "fr0" }, "f0" }, 1532 { { "fr1" }, "f1" }, 1533 { { "fr2" }, "f2" }, 1534 { { "fr3" }, "f3" }, 1535 { { "fr4" }, "f4" }, 1536 { { "fr5" }, "f5" }, 1537 { { "fr6" }, "f6" }, 1538 { { "fr7" }, "f7" }, 1539 { { "fr8" }, "f8" }, 1540 { { "fr9" }, "f9" }, 1541 { { "fr10" }, "f10" }, 1542 { { "fr11" }, "f11" }, 1543 { { "fr12" }, "f12" }, 1544 { { "fr13" }, "f13" }, 1545 { { "fr14" }, "f14" }, 1546 { { "fr15" }, "f15" }, 1547 { { "fr16" }, "f16" }, 1548 { { "fr17" }, "f17" }, 1549 { { "fr18" }, "f18" }, 1550 { { "fr19" }, "f19" }, 1551 { { "fr20" }, "f20" }, 1552 { { "fr21" }, "f21" }, 1553 { { "fr22" }, "f22" }, 1554 { { "fr23" }, "f23" }, 1555 { { "fr24" }, "f24" }, 1556 { { "fr25" }, "f25" }, 1557 { { "fr26" }, "f26" }, 1558 { { "fr27" }, "f27" }, 1559 { { "fr28" }, "f28" }, 1560 { { "fr29" }, "f29" }, 1561 { { "fr30" }, "f30" }, 1562 { { "fr31" }, "f31" }, 1563 { { "cc" }, "cr0" }, 1564 }; 1565 1566 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1567 return llvm::makeArrayRef(GCCRegAliases); 1568 } 1569 1570 class PPC32TargetInfo : public PPCTargetInfo { 1571 public: 1572 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1573 : PPCTargetInfo(Triple, Opts) { 1574 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1575 1576 switch (getTriple().getOS()) { 1577 case llvm::Triple::Linux: 1578 case llvm::Triple::FreeBSD: 1579 case llvm::Triple::NetBSD: 1580 SizeType = UnsignedInt; 1581 PtrDiffType = SignedInt; 1582 IntPtrType = SignedInt; 1583 break; 1584 default: 1585 break; 1586 } 1587 1588 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1589 LongDoubleWidth = LongDoubleAlign = 64; 1590 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1591 } 1592 1593 // PPC32 supports atomics up to 4 bytes. 1594 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1595 } 1596 1597 BuiltinVaListKind getBuiltinVaListKind() const override { 1598 // This is the ELF definition, and is overridden by the Darwin sub-target 1599 return TargetInfo::PowerABIBuiltinVaList; 1600 } 1601 }; 1602 1603 // Note: ABI differences may eventually require us to have a separate 1604 // TargetInfo for little endian. 1605 class PPC64TargetInfo : public PPCTargetInfo { 1606 public: 1607 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1608 : PPCTargetInfo(Triple, Opts) { 1609 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1610 IntMaxType = SignedLong; 1611 Int64Type = SignedLong; 1612 1613 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1614 resetDataLayout("e-m:e-i64:64-n32:64"); 1615 ABI = "elfv2"; 1616 } else { 1617 resetDataLayout("E-m:e-i64:64-n32:64"); 1618 ABI = "elfv1"; 1619 } 1620 1621 switch (getTriple().getOS()) { 1622 case llvm::Triple::FreeBSD: 1623 LongDoubleWidth = LongDoubleAlign = 64; 1624 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1625 break; 1626 case llvm::Triple::NetBSD: 1627 IntMaxType = SignedLongLong; 1628 Int64Type = SignedLongLong; 1629 break; 1630 default: 1631 break; 1632 } 1633 1634 // PPC64 supports atomics up to 8 bytes. 1635 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1636 } 1637 BuiltinVaListKind getBuiltinVaListKind() const override { 1638 return TargetInfo::CharPtrBuiltinVaList; 1639 } 1640 // PPC64 Linux-specific ABI options. 1641 bool setABI(const std::string &Name) override { 1642 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1643 ABI = Name; 1644 return true; 1645 } 1646 return false; 1647 } 1648 }; 1649 1650 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1651 public: 1652 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1653 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1654 HasAlignMac68kSupport = true; 1655 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1656 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1657 LongLongAlign = 32; 1658 SuitableAlign = 128; 1659 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1660 } 1661 BuiltinVaListKind getBuiltinVaListKind() const override { 1662 return TargetInfo::CharPtrBuiltinVaList; 1663 } 1664 }; 1665 1666 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1667 public: 1668 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1669 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1670 HasAlignMac68kSupport = true; 1671 SuitableAlign = 128; 1672 resetDataLayout("E-m:o-i64:64-n32:64"); 1673 } 1674 }; 1675 1676 static const unsigned NVPTXAddrSpaceMap[] = { 1677 1, // opencl_global 1678 3, // opencl_local 1679 4, // opencl_constant 1680 // FIXME: generic has to be added to the target 1681 0, // opencl_generic 1682 1, // cuda_device 1683 4, // cuda_constant 1684 3, // cuda_shared 1685 }; 1686 1687 class NVPTXTargetInfo : public TargetInfo { 1688 static const char *const GCCRegNames[]; 1689 static const Builtin::Info BuiltinInfo[]; 1690 1691 // The GPU profiles supported by the NVPTX backend 1692 enum GPUKind { 1693 GK_NONE, 1694 GK_SM20, 1695 GK_SM21, 1696 GK_SM30, 1697 GK_SM35, 1698 GK_SM37, 1699 GK_SM50, 1700 GK_SM52, 1701 GK_SM53, 1702 } GPU; 1703 1704 public: 1705 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1706 : TargetInfo(Triple) { 1707 BigEndian = false; 1708 TLSSupported = false; 1709 LongWidth = LongAlign = 64; 1710 AddrSpaceMap = &NVPTXAddrSpaceMap; 1711 UseAddrSpaceMapMangling = true; 1712 // Define available target features 1713 // These must be defined in sorted order! 1714 NoAsmVariants = true; 1715 // Set the default GPU to sm20 1716 GPU = GK_SM20; 1717 1718 // If possible, get a TargetInfo for our host triple, so we can match its 1719 // types. 1720 llvm::Triple HostTriple(Opts.HostTriple); 1721 if (HostTriple.isNVPTX()) 1722 return; 1723 std::unique_ptr<TargetInfo> HostTarget( 1724 AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1725 if (!HostTarget) { 1726 return; 1727 } 1728 1729 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1730 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1731 BoolWidth = HostTarget->getBoolWidth(); 1732 BoolAlign = HostTarget->getBoolAlign(); 1733 IntWidth = HostTarget->getIntWidth(); 1734 IntAlign = HostTarget->getIntAlign(); 1735 HalfWidth = HostTarget->getHalfWidth(); 1736 HalfAlign = HostTarget->getHalfAlign(); 1737 FloatWidth = HostTarget->getFloatWidth(); 1738 FloatAlign = HostTarget->getFloatAlign(); 1739 DoubleWidth = HostTarget->getDoubleWidth(); 1740 DoubleAlign = HostTarget->getDoubleAlign(); 1741 LongWidth = HostTarget->getLongWidth(); 1742 LongAlign = HostTarget->getLongAlign(); 1743 LongLongWidth = HostTarget->getLongLongWidth(); 1744 LongLongAlign = HostTarget->getLongLongAlign(); 1745 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1746 DefaultAlignForAttributeAligned = 1747 HostTarget->getDefaultAlignForAttributeAligned(); 1748 SizeType = HostTarget->getSizeType(); 1749 IntMaxType = HostTarget->getIntMaxType(); 1750 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1751 IntPtrType = HostTarget->getIntPtrType(); 1752 WCharType = HostTarget->getWCharType(); 1753 WIntType = HostTarget->getWIntType(); 1754 Char16Type = HostTarget->getChar16Type(); 1755 Char32Type = HostTarget->getChar32Type(); 1756 Int64Type = HostTarget->getInt64Type(); 1757 SigAtomicType = HostTarget->getSigAtomicType(); 1758 ProcessIDType = HostTarget->getProcessIDType(); 1759 1760 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1761 UseZeroLengthBitfieldAlignment = 1762 HostTarget->useZeroLengthBitfieldAlignment(); 1763 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1764 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1765 1766 // Properties intentionally not copied from host: 1767 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1768 // host/device boundary. 1769 // - SuitableAlign: Not visible across the host/device boundary, and may 1770 // correctly be different on host/device, e.g. if host has wider vector 1771 // types than device. 1772 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1773 // as its double type, but that's not necessarily true on the host. 1774 // TODO: nvcc emits a warning when using long double on device; we should 1775 // do the same. 1776 } 1777 void getTargetDefines(const LangOptions &Opts, 1778 MacroBuilder &Builder) const override { 1779 Builder.defineMacro("__PTX__"); 1780 Builder.defineMacro("__NVPTX__"); 1781 if (Opts.CUDAIsDevice) { 1782 // Set __CUDA_ARCH__ for the GPU specified. 1783 std::string CUDAArchCode; 1784 switch (GPU) { 1785 case GK_SM20: 1786 CUDAArchCode = "200"; 1787 break; 1788 case GK_SM21: 1789 CUDAArchCode = "210"; 1790 break; 1791 case GK_SM30: 1792 CUDAArchCode = "300"; 1793 break; 1794 case GK_SM35: 1795 CUDAArchCode = "350"; 1796 break; 1797 case GK_SM37: 1798 CUDAArchCode = "370"; 1799 break; 1800 case GK_SM50: 1801 CUDAArchCode = "500"; 1802 break; 1803 case GK_SM52: 1804 CUDAArchCode = "520"; 1805 break; 1806 case GK_SM53: 1807 CUDAArchCode = "530"; 1808 break; 1809 default: 1810 llvm_unreachable("Unhandled target CPU"); 1811 } 1812 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1813 } 1814 } 1815 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1816 return llvm::makeArrayRef(BuiltinInfo, 1817 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1818 } 1819 bool hasFeature(StringRef Feature) const override { 1820 return Feature == "ptx" || Feature == "nvptx"; 1821 } 1822 1823 ArrayRef<const char *> getGCCRegNames() const override; 1824 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1825 // No aliases. 1826 return None; 1827 } 1828 bool validateAsmConstraint(const char *&Name, 1829 TargetInfo::ConstraintInfo &Info) const override { 1830 switch (*Name) { 1831 default: 1832 return false; 1833 case 'c': 1834 case 'h': 1835 case 'r': 1836 case 'l': 1837 case 'f': 1838 case 'd': 1839 Info.setAllowsRegister(); 1840 return true; 1841 } 1842 } 1843 const char *getClobbers() const override { 1844 // FIXME: Is this really right? 1845 return ""; 1846 } 1847 BuiltinVaListKind getBuiltinVaListKind() const override { 1848 // FIXME: implement 1849 return TargetInfo::CharPtrBuiltinVaList; 1850 } 1851 bool setCPU(const std::string &Name) override { 1852 GPU = llvm::StringSwitch<GPUKind>(Name) 1853 .Case("sm_20", GK_SM20) 1854 .Case("sm_21", GK_SM21) 1855 .Case("sm_30", GK_SM30) 1856 .Case("sm_35", GK_SM35) 1857 .Case("sm_37", GK_SM37) 1858 .Case("sm_50", GK_SM50) 1859 .Case("sm_52", GK_SM52) 1860 .Case("sm_53", GK_SM53) 1861 .Default(GK_NONE); 1862 1863 return GPU != GK_NONE; 1864 } 1865 }; 1866 1867 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1868 #define BUILTIN(ID, TYPE, ATTRS) \ 1869 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1870 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1871 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1872 #include "clang/Basic/BuiltinsNVPTX.def" 1873 }; 1874 1875 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1876 1877 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1878 return llvm::makeArrayRef(GCCRegNames); 1879 } 1880 1881 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1882 public: 1883 NVPTX32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1884 : NVPTXTargetInfo(Triple, Opts) { 1885 LongWidth = LongAlign = 32; 1886 PointerWidth = PointerAlign = 32; 1887 SizeType = TargetInfo::UnsignedInt; 1888 PtrDiffType = TargetInfo::SignedInt; 1889 IntPtrType = TargetInfo::SignedInt; 1890 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1891 } 1892 }; 1893 1894 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1895 public: 1896 NVPTX64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1897 : NVPTXTargetInfo(Triple, Opts) { 1898 PointerWidth = PointerAlign = 64; 1899 SizeType = TargetInfo::UnsignedLong; 1900 PtrDiffType = TargetInfo::SignedLong; 1901 IntPtrType = TargetInfo::SignedLong; 1902 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1903 } 1904 }; 1905 1906 static const unsigned AMDGPUAddrSpaceMap[] = { 1907 1, // opencl_global 1908 3, // opencl_local 1909 2, // opencl_constant 1910 4, // opencl_generic 1911 1, // cuda_device 1912 2, // cuda_constant 1913 3 // cuda_shared 1914 }; 1915 1916 // If you edit the description strings, make sure you update 1917 // getPointerWidthV(). 1918 1919 static const char *const DataLayoutStringR600 = 1920 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1921 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1922 1923 static const char *const DataLayoutStringSI = 1924 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 1925 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1926 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1927 1928 class AMDGPUTargetInfo final : public TargetInfo { 1929 static const Builtin::Info BuiltinInfo[]; 1930 static const char * const GCCRegNames[]; 1931 1932 /// \brief The GPU profiles supported by the AMDGPU target. 1933 enum GPUKind { 1934 GK_NONE, 1935 GK_R600, 1936 GK_R600_DOUBLE_OPS, 1937 GK_R700, 1938 GK_R700_DOUBLE_OPS, 1939 GK_EVERGREEN, 1940 GK_EVERGREEN_DOUBLE_OPS, 1941 GK_NORTHERN_ISLANDS, 1942 GK_CAYMAN, 1943 GK_SOUTHERN_ISLANDS, 1944 GK_SEA_ISLANDS, 1945 GK_VOLCANIC_ISLANDS 1946 } GPU; 1947 1948 bool hasFP64:1; 1949 bool hasFMAF:1; 1950 bool hasLDEXPF:1; 1951 1952 static bool isAMDGCN(const llvm::Triple &TT) { 1953 return TT.getArch() == llvm::Triple::amdgcn; 1954 } 1955 1956 public: 1957 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 1958 : TargetInfo(Triple) , 1959 GPU(isAMDGCN(Triple) ? GK_SOUTHERN_ISLANDS : GK_R600), 1960 hasFP64(false), 1961 hasFMAF(false), 1962 hasLDEXPF(false) { 1963 if (getTriple().getArch() == llvm::Triple::amdgcn) { 1964 hasFP64 = true; 1965 hasFMAF = true; 1966 hasLDEXPF = true; 1967 } 1968 1969 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 1970 DataLayoutStringSI : DataLayoutStringR600); 1971 1972 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1973 UseAddrSpaceMapMangling = true; 1974 } 1975 1976 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1977 if (GPU <= GK_CAYMAN) 1978 return 32; 1979 1980 switch(AddrSpace) { 1981 default: 1982 return 64; 1983 case 0: 1984 case 3: 1985 case 5: 1986 return 32; 1987 } 1988 } 1989 1990 const char * getClobbers() const override { 1991 return ""; 1992 } 1993 1994 ArrayRef<const char *> getGCCRegNames() const override; 1995 1996 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1997 return None; 1998 } 1999 2000 bool validateAsmConstraint(const char *&Name, 2001 TargetInfo::ConstraintInfo &Info) const override { 2002 switch (*Name) { 2003 default: break; 2004 case 'v': // vgpr 2005 case 's': // sgpr 2006 Info.setAllowsRegister(); 2007 return true; 2008 } 2009 return false; 2010 } 2011 2012 bool initFeatureMap(llvm::StringMap<bool> &Features, 2013 DiagnosticsEngine &Diags, StringRef CPU, 2014 const std::vector<std::string> &FeatureVec) const override; 2015 2016 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2017 return llvm::makeArrayRef(BuiltinInfo, 2018 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2019 } 2020 2021 void getTargetDefines(const LangOptions &Opts, 2022 MacroBuilder &Builder) const override { 2023 if (getTriple().getArch() == llvm::Triple::amdgcn) 2024 Builder.defineMacro("__AMDGCN__"); 2025 else 2026 Builder.defineMacro("__R600__"); 2027 2028 if (hasFMAF) 2029 Builder.defineMacro("__HAS_FMAF__"); 2030 if (hasLDEXPF) 2031 Builder.defineMacro("__HAS_LDEXPF__"); 2032 } 2033 2034 BuiltinVaListKind getBuiltinVaListKind() const override { 2035 return TargetInfo::CharPtrBuiltinVaList; 2036 } 2037 2038 static GPUKind parseR600Name(StringRef Name) { 2039 return llvm::StringSwitch<GPUKind>(Name) 2040 .Case("r600" , GK_R600) 2041 .Case("rv610", GK_R600) 2042 .Case("rv620", GK_R600) 2043 .Case("rv630", GK_R600) 2044 .Case("rv635", GK_R600) 2045 .Case("rs780", GK_R600) 2046 .Case("rs880", GK_R600) 2047 .Case("rv670", GK_R600_DOUBLE_OPS) 2048 .Case("rv710", GK_R700) 2049 .Case("rv730", GK_R700) 2050 .Case("rv740", GK_R700_DOUBLE_OPS) 2051 .Case("rv770", GK_R700_DOUBLE_OPS) 2052 .Case("palm", GK_EVERGREEN) 2053 .Case("cedar", GK_EVERGREEN) 2054 .Case("sumo", GK_EVERGREEN) 2055 .Case("sumo2", GK_EVERGREEN) 2056 .Case("redwood", GK_EVERGREEN) 2057 .Case("juniper", GK_EVERGREEN) 2058 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2059 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2060 .Case("barts", GK_NORTHERN_ISLANDS) 2061 .Case("turks", GK_NORTHERN_ISLANDS) 2062 .Case("caicos", GK_NORTHERN_ISLANDS) 2063 .Case("cayman", GK_CAYMAN) 2064 .Case("aruba", GK_CAYMAN) 2065 .Default(GK_NONE); 2066 } 2067 2068 static GPUKind parseAMDGCNName(StringRef Name) { 2069 return llvm::StringSwitch<GPUKind>(Name) 2070 .Case("tahiti", GK_SOUTHERN_ISLANDS) 2071 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 2072 .Case("verde", GK_SOUTHERN_ISLANDS) 2073 .Case("oland", GK_SOUTHERN_ISLANDS) 2074 .Case("hainan", GK_SOUTHERN_ISLANDS) 2075 .Case("bonaire", GK_SEA_ISLANDS) 2076 .Case("kabini", GK_SEA_ISLANDS) 2077 .Case("kaveri", GK_SEA_ISLANDS) 2078 .Case("hawaii", GK_SEA_ISLANDS) 2079 .Case("mullins", GK_SEA_ISLANDS) 2080 .Case("tonga", GK_VOLCANIC_ISLANDS) 2081 .Case("iceland", GK_VOLCANIC_ISLANDS) 2082 .Case("carrizo", GK_VOLCANIC_ISLANDS) 2083 .Case("fiji", GK_VOLCANIC_ISLANDS) 2084 .Case("stoney", GK_VOLCANIC_ISLANDS) 2085 .Default(GK_NONE); 2086 } 2087 2088 bool setCPU(const std::string &Name) override { 2089 if (getTriple().getArch() == llvm::Triple::amdgcn) 2090 GPU = parseAMDGCNName(Name); 2091 else 2092 GPU = parseR600Name(Name); 2093 2094 return GPU != GK_NONE; 2095 } 2096 2097 void setSupportedOpenCLOpts() override { 2098 auto &Opts = getSupportedOpenCLOpts(); 2099 Opts.cl_clang_storage_class_specifiers = 1; 2100 Opts.cl_khr_gl_sharing = 1; 2101 Opts.cl_khr_gl_event = 1; 2102 Opts.cl_khr_d3d10_sharing = 1; 2103 Opts.cl_khr_subgroups = 1; 2104 2105 if (hasFP64) 2106 Opts.cl_khr_fp64 = 1; 2107 if (GPU >= GK_NORTHERN_ISLANDS) { 2108 Opts.cl_khr_byte_addressable_store = 1; 2109 Opts.cl_khr_global_int32_base_atomics = 1; 2110 Opts.cl_khr_global_int32_extended_atomics = 1; 2111 Opts.cl_khr_local_int32_base_atomics = 1; 2112 Opts.cl_khr_local_int32_extended_atomics = 1; 2113 } 2114 if (GPU >= GK_SOUTHERN_ISLANDS) 2115 Opts.cl_khr_fp16 = 1; 2116 Opts.cl_khr_int64_base_atomics = 1; 2117 Opts.cl_khr_int64_extended_atomics = 1; 2118 Opts.cl_khr_3d_image_writes = 1; 2119 Opts.cl_khr_gl_msaa_sharing = 1; 2120 } 2121 }; 2122 2123 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2124 #define BUILTIN(ID, TYPE, ATTRS) \ 2125 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2126 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2127 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2128 #include "clang/Basic/BuiltinsAMDGPU.def" 2129 }; 2130 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2131 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2132 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2133 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2134 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2135 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2136 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2137 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2138 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2139 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2140 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2141 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2142 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2143 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2144 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2145 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2146 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2147 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2148 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2149 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2150 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2151 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2152 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2153 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2154 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2155 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2156 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2157 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2158 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2159 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2160 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2161 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2162 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2163 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2164 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2165 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2166 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2167 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2168 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2169 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2170 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2171 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2172 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2173 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2174 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2175 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2176 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2177 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2178 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2179 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2180 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2181 }; 2182 2183 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2184 return llvm::makeArrayRef(GCCRegNames); 2185 } 2186 2187 bool AMDGPUTargetInfo::initFeatureMap( 2188 llvm::StringMap<bool> &Features, 2189 DiagnosticsEngine &Diags, StringRef CPU, 2190 const std::vector<std::string> &FeatureVec) const { 2191 2192 // XXX - What does the member GPU mean if device name string passed here? 2193 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2194 if (CPU.empty()) 2195 CPU = "tahiti"; 2196 2197 switch (parseAMDGCNName(CPU)) { 2198 case GK_SOUTHERN_ISLANDS: 2199 case GK_SEA_ISLANDS: 2200 break; 2201 2202 case GK_VOLCANIC_ISLANDS: 2203 Features["s-memrealtime"] = true; 2204 Features["16-bit-insts"] = true; 2205 break; 2206 2207 case GK_NONE: 2208 return false; 2209 default: 2210 llvm_unreachable("unhandled subtarget"); 2211 } 2212 } else { 2213 if (CPU.empty()) 2214 CPU = "r600"; 2215 2216 switch (parseR600Name(CPU)) { 2217 case GK_R600: 2218 case GK_R700: 2219 case GK_EVERGREEN: 2220 case GK_NORTHERN_ISLANDS: 2221 break; 2222 case GK_R600_DOUBLE_OPS: 2223 case GK_R700_DOUBLE_OPS: 2224 case GK_EVERGREEN_DOUBLE_OPS: 2225 case GK_CAYMAN: 2226 Features["fp64"] = true; 2227 break; 2228 case GK_NONE: 2229 return false; 2230 default: 2231 llvm_unreachable("unhandled subtarget"); 2232 } 2233 } 2234 2235 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2236 } 2237 2238 // Namespace for x86 abstract base class 2239 const Builtin::Info BuiltinInfo[] = { 2240 #define BUILTIN(ID, TYPE, ATTRS) \ 2241 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2242 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2243 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2244 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2245 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2246 #include "clang/Basic/BuiltinsX86.def" 2247 }; 2248 2249 static const char* const GCCRegNames[] = { 2250 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2251 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2252 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2253 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2254 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2255 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2256 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2257 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2258 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2259 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2260 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2261 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2262 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2263 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2264 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2265 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2266 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2267 }; 2268 2269 const TargetInfo::AddlRegName AddlRegNames[] = { 2270 { { "al", "ah", "eax", "rax" }, 0 }, 2271 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2272 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2273 { { "dl", "dh", "edx", "rdx" }, 1 }, 2274 { { "esi", "rsi" }, 4 }, 2275 { { "edi", "rdi" }, 5 }, 2276 { { "esp", "rsp" }, 7 }, 2277 { { "ebp", "rbp" }, 6 }, 2278 { { "r8d", "r8w", "r8b" }, 38 }, 2279 { { "r9d", "r9w", "r9b" }, 39 }, 2280 { { "r10d", "r10w", "r10b" }, 40 }, 2281 { { "r11d", "r11w", "r11b" }, 41 }, 2282 { { "r12d", "r12w", "r12b" }, 42 }, 2283 { { "r13d", "r13w", "r13b" }, 43 }, 2284 { { "r14d", "r14w", "r14b" }, 44 }, 2285 { { "r15d", "r15w", "r15b" }, 45 }, 2286 }; 2287 2288 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2289 // most of the implementation can be shared. 2290 class X86TargetInfo : public TargetInfo { 2291 enum X86SSEEnum { 2292 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2293 } SSELevel = NoSSE; 2294 enum MMX3DNowEnum { 2295 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2296 } MMX3DNowLevel = NoMMX3DNow; 2297 enum XOPEnum { 2298 NoXOP, 2299 SSE4A, 2300 FMA4, 2301 XOP 2302 } XOPLevel = NoXOP; 2303 2304 bool HasAES = false; 2305 bool HasPCLMUL = false; 2306 bool HasLZCNT = false; 2307 bool HasRDRND = false; 2308 bool HasFSGSBASE = false; 2309 bool HasBMI = false; 2310 bool HasBMI2 = false; 2311 bool HasPOPCNT = false; 2312 bool HasRTM = false; 2313 bool HasPRFCHW = false; 2314 bool HasRDSEED = false; 2315 bool HasADX = false; 2316 bool HasTBM = false; 2317 bool HasFMA = false; 2318 bool HasF16C = false; 2319 bool HasAVX512CD = false; 2320 bool HasAVX512ER = false; 2321 bool HasAVX512PF = false; 2322 bool HasAVX512DQ = false; 2323 bool HasAVX512BW = false; 2324 bool HasAVX512VL = false; 2325 bool HasAVX512VBMI = false; 2326 bool HasAVX512IFMA = false; 2327 bool HasSHA = false; 2328 bool HasMPX = false; 2329 bool HasSGX = false; 2330 bool HasCX16 = false; 2331 bool HasFXSR = false; 2332 bool HasXSAVE = false; 2333 bool HasXSAVEOPT = false; 2334 bool HasXSAVEC = false; 2335 bool HasXSAVES = false; 2336 bool HasMWAITX = false; 2337 bool HasPKU = false; 2338 bool HasCLFLUSHOPT = false; 2339 bool HasPCOMMIT = false; 2340 bool HasCLWB = false; 2341 bool HasUMIP = false; 2342 bool HasMOVBE = false; 2343 bool HasPREFETCHWT1 = false; 2344 2345 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2346 /// 2347 /// Each enumeration represents a particular CPU supported by Clang. These 2348 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2349 enum CPUKind { 2350 CK_Generic, 2351 2352 /// \name i386 2353 /// i386-generation processors. 2354 //@{ 2355 CK_i386, 2356 //@} 2357 2358 /// \name i486 2359 /// i486-generation processors. 2360 //@{ 2361 CK_i486, 2362 CK_WinChipC6, 2363 CK_WinChip2, 2364 CK_C3, 2365 //@} 2366 2367 /// \name i586 2368 /// i586-generation processors, P5 microarchitecture based. 2369 //@{ 2370 CK_i586, 2371 CK_Pentium, 2372 CK_PentiumMMX, 2373 //@} 2374 2375 /// \name i686 2376 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2377 //@{ 2378 CK_i686, 2379 CK_PentiumPro, 2380 CK_Pentium2, 2381 CK_Pentium3, 2382 CK_Pentium3M, 2383 CK_PentiumM, 2384 CK_C3_2, 2385 2386 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2387 /// Clang however has some logic to suport this. 2388 // FIXME: Warn, deprecate, and potentially remove this. 2389 CK_Yonah, 2390 //@} 2391 2392 /// \name Netburst 2393 /// Netburst microarchitecture based processors. 2394 //@{ 2395 CK_Pentium4, 2396 CK_Pentium4M, 2397 CK_Prescott, 2398 CK_Nocona, 2399 //@} 2400 2401 /// \name Core 2402 /// Core microarchitecture based processors. 2403 //@{ 2404 CK_Core2, 2405 2406 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2407 /// codename which GCC no longer accepts as an option to -march, but Clang 2408 /// has some logic for recognizing it. 2409 // FIXME: Warn, deprecate, and potentially remove this. 2410 CK_Penryn, 2411 //@} 2412 2413 /// \name Atom 2414 /// Atom processors 2415 //@{ 2416 CK_Bonnell, 2417 CK_Silvermont, 2418 //@} 2419 2420 /// \name Nehalem 2421 /// Nehalem microarchitecture based processors. 2422 CK_Nehalem, 2423 2424 /// \name Westmere 2425 /// Westmere microarchitecture based processors. 2426 CK_Westmere, 2427 2428 /// \name Sandy Bridge 2429 /// Sandy Bridge microarchitecture based processors. 2430 CK_SandyBridge, 2431 2432 /// \name Ivy Bridge 2433 /// Ivy Bridge microarchitecture based processors. 2434 CK_IvyBridge, 2435 2436 /// \name Haswell 2437 /// Haswell microarchitecture based processors. 2438 CK_Haswell, 2439 2440 /// \name Broadwell 2441 /// Broadwell microarchitecture based processors. 2442 CK_Broadwell, 2443 2444 /// \name Skylake Client 2445 /// Skylake client microarchitecture based processors. 2446 CK_SkylakeClient, 2447 2448 /// \name Skylake Server 2449 /// Skylake server microarchitecture based processors. 2450 CK_SkylakeServer, 2451 2452 /// \name Cannonlake Client 2453 /// Cannonlake client microarchitecture based processors. 2454 CK_Cannonlake, 2455 2456 /// \name Knights Landing 2457 /// Knights Landing processor. 2458 CK_KNL, 2459 2460 /// \name Lakemont 2461 /// Lakemont microarchitecture based processors. 2462 CK_Lakemont, 2463 2464 /// \name K6 2465 /// K6 architecture processors. 2466 //@{ 2467 CK_K6, 2468 CK_K6_2, 2469 CK_K6_3, 2470 //@} 2471 2472 /// \name K7 2473 /// K7 architecture processors. 2474 //@{ 2475 CK_Athlon, 2476 CK_AthlonThunderbird, 2477 CK_Athlon4, 2478 CK_AthlonXP, 2479 CK_AthlonMP, 2480 //@} 2481 2482 /// \name K8 2483 /// K8 architecture processors. 2484 //@{ 2485 CK_Athlon64, 2486 CK_Athlon64SSE3, 2487 CK_AthlonFX, 2488 CK_K8, 2489 CK_K8SSE3, 2490 CK_Opteron, 2491 CK_OpteronSSE3, 2492 CK_AMDFAM10, 2493 //@} 2494 2495 /// \name Bobcat 2496 /// Bobcat architecture processors. 2497 //@{ 2498 CK_BTVER1, 2499 CK_BTVER2, 2500 //@} 2501 2502 /// \name Bulldozer 2503 /// Bulldozer architecture processors. 2504 //@{ 2505 CK_BDVER1, 2506 CK_BDVER2, 2507 CK_BDVER3, 2508 CK_BDVER4, 2509 //@} 2510 2511 /// This specification is deprecated and will be removed in the future. 2512 /// Users should prefer \see CK_K8. 2513 // FIXME: Warn on this when the CPU is set to it. 2514 //@{ 2515 CK_x86_64, 2516 //@} 2517 2518 /// \name Geode 2519 /// Geode processors. 2520 //@{ 2521 CK_Geode 2522 //@} 2523 } CPU = CK_Generic; 2524 2525 CPUKind getCPUKind(StringRef CPU) const { 2526 return llvm::StringSwitch<CPUKind>(CPU) 2527 .Case("i386", CK_i386) 2528 .Case("i486", CK_i486) 2529 .Case("winchip-c6", CK_WinChipC6) 2530 .Case("winchip2", CK_WinChip2) 2531 .Case("c3", CK_C3) 2532 .Case("i586", CK_i586) 2533 .Case("pentium", CK_Pentium) 2534 .Case("pentium-mmx", CK_PentiumMMX) 2535 .Case("i686", CK_i686) 2536 .Case("pentiumpro", CK_PentiumPro) 2537 .Case("pentium2", CK_Pentium2) 2538 .Case("pentium3", CK_Pentium3) 2539 .Case("pentium3m", CK_Pentium3M) 2540 .Case("pentium-m", CK_PentiumM) 2541 .Case("c3-2", CK_C3_2) 2542 .Case("yonah", CK_Yonah) 2543 .Case("pentium4", CK_Pentium4) 2544 .Case("pentium4m", CK_Pentium4M) 2545 .Case("prescott", CK_Prescott) 2546 .Case("nocona", CK_Nocona) 2547 .Case("core2", CK_Core2) 2548 .Case("penryn", CK_Penryn) 2549 .Case("bonnell", CK_Bonnell) 2550 .Case("atom", CK_Bonnell) // Legacy name. 2551 .Case("silvermont", CK_Silvermont) 2552 .Case("slm", CK_Silvermont) // Legacy name. 2553 .Case("nehalem", CK_Nehalem) 2554 .Case("corei7", CK_Nehalem) // Legacy name. 2555 .Case("westmere", CK_Westmere) 2556 .Case("sandybridge", CK_SandyBridge) 2557 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2558 .Case("ivybridge", CK_IvyBridge) 2559 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2560 .Case("haswell", CK_Haswell) 2561 .Case("core-avx2", CK_Haswell) // Legacy name. 2562 .Case("broadwell", CK_Broadwell) 2563 .Case("skylake", CK_SkylakeClient) 2564 .Case("skylake-avx512", CK_SkylakeServer) 2565 .Case("skx", CK_SkylakeServer) // Legacy name. 2566 .Case("cannonlake", CK_Cannonlake) 2567 .Case("knl", CK_KNL) 2568 .Case("lakemont", CK_Lakemont) 2569 .Case("k6", CK_K6) 2570 .Case("k6-2", CK_K6_2) 2571 .Case("k6-3", CK_K6_3) 2572 .Case("athlon", CK_Athlon) 2573 .Case("athlon-tbird", CK_AthlonThunderbird) 2574 .Case("athlon-4", CK_Athlon4) 2575 .Case("athlon-xp", CK_AthlonXP) 2576 .Case("athlon-mp", CK_AthlonMP) 2577 .Case("athlon64", CK_Athlon64) 2578 .Case("athlon64-sse3", CK_Athlon64SSE3) 2579 .Case("athlon-fx", CK_AthlonFX) 2580 .Case("k8", CK_K8) 2581 .Case("k8-sse3", CK_K8SSE3) 2582 .Case("opteron", CK_Opteron) 2583 .Case("opteron-sse3", CK_OpteronSSE3) 2584 .Case("barcelona", CK_AMDFAM10) 2585 .Case("amdfam10", CK_AMDFAM10) 2586 .Case("btver1", CK_BTVER1) 2587 .Case("btver2", CK_BTVER2) 2588 .Case("bdver1", CK_BDVER1) 2589 .Case("bdver2", CK_BDVER2) 2590 .Case("bdver3", CK_BDVER3) 2591 .Case("bdver4", CK_BDVER4) 2592 .Case("x86-64", CK_x86_64) 2593 .Case("geode", CK_Geode) 2594 .Default(CK_Generic); 2595 } 2596 2597 enum FPMathKind { 2598 FP_Default, 2599 FP_SSE, 2600 FP_387 2601 } FPMath = FP_Default; 2602 2603 public: 2604 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2605 : TargetInfo(Triple) { 2606 BigEndian = false; 2607 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2608 } 2609 unsigned getFloatEvalMethod() const override { 2610 // X87 evaluates with 80 bits "long double" precision. 2611 return SSELevel == NoSSE ? 2 : 0; 2612 } 2613 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2614 return llvm::makeArrayRef(BuiltinInfo, 2615 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2616 } 2617 ArrayRef<const char *> getGCCRegNames() const override { 2618 return llvm::makeArrayRef(GCCRegNames); 2619 } 2620 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2621 return None; 2622 } 2623 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2624 return llvm::makeArrayRef(AddlRegNames); 2625 } 2626 bool validateCpuSupports(StringRef Name) const override; 2627 bool validateAsmConstraint(const char *&Name, 2628 TargetInfo::ConstraintInfo &info) const override; 2629 2630 bool validateGlobalRegisterVariable(StringRef RegName, 2631 unsigned RegSize, 2632 bool &HasSizeMismatch) const override { 2633 // esp and ebp are the only 32-bit registers the x86 backend can currently 2634 // handle. 2635 if (RegName.equals("esp") || RegName.equals("ebp")) { 2636 // Check that the register size is 32-bit. 2637 HasSizeMismatch = RegSize != 32; 2638 return true; 2639 } 2640 2641 return false; 2642 } 2643 2644 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2645 2646 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2647 2648 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2649 2650 std::string convertConstraint(const char *&Constraint) const override; 2651 const char *getClobbers() const override { 2652 return "~{dirflag},~{fpsr},~{flags}"; 2653 } 2654 void getTargetDefines(const LangOptions &Opts, 2655 MacroBuilder &Builder) const override; 2656 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2657 bool Enabled); 2658 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2659 bool Enabled); 2660 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2661 bool Enabled); 2662 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2663 StringRef Name, bool Enabled) const override { 2664 setFeatureEnabledImpl(Features, Name, Enabled); 2665 } 2666 // This exists purely to cut down on the number of virtual calls in 2667 // initFeatureMap which calls this repeatedly. 2668 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2669 StringRef Name, bool Enabled); 2670 bool 2671 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2672 StringRef CPU, 2673 const std::vector<std::string> &FeaturesVec) const override; 2674 bool hasFeature(StringRef Feature) const override; 2675 bool handleTargetFeatures(std::vector<std::string> &Features, 2676 DiagnosticsEngine &Diags) override; 2677 StringRef getABI() const override { 2678 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2679 return "avx512"; 2680 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2681 return "avx"; 2682 if (getTriple().getArch() == llvm::Triple::x86 && 2683 MMX3DNowLevel == NoMMX3DNow) 2684 return "no-mmx"; 2685 return ""; 2686 } 2687 bool setCPU(const std::string &Name) override { 2688 CPU = getCPUKind(Name); 2689 2690 // Perform any per-CPU checks necessary to determine if this CPU is 2691 // acceptable. 2692 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2693 // invalid without explaining *why*. 2694 switch (CPU) { 2695 case CK_Generic: 2696 // No processor selected! 2697 return false; 2698 2699 case CK_i386: 2700 case CK_i486: 2701 case CK_WinChipC6: 2702 case CK_WinChip2: 2703 case CK_C3: 2704 case CK_i586: 2705 case CK_Pentium: 2706 case CK_PentiumMMX: 2707 case CK_i686: 2708 case CK_PentiumPro: 2709 case CK_Pentium2: 2710 case CK_Pentium3: 2711 case CK_Pentium3M: 2712 case CK_PentiumM: 2713 case CK_Yonah: 2714 case CK_C3_2: 2715 case CK_Pentium4: 2716 case CK_Pentium4M: 2717 case CK_Lakemont: 2718 case CK_Prescott: 2719 case CK_K6: 2720 case CK_K6_2: 2721 case CK_K6_3: 2722 case CK_Athlon: 2723 case CK_AthlonThunderbird: 2724 case CK_Athlon4: 2725 case CK_AthlonXP: 2726 case CK_AthlonMP: 2727 case CK_Geode: 2728 // Only accept certain architectures when compiling in 32-bit mode. 2729 if (getTriple().getArch() != llvm::Triple::x86) 2730 return false; 2731 2732 // Fallthrough 2733 case CK_Nocona: 2734 case CK_Core2: 2735 case CK_Penryn: 2736 case CK_Bonnell: 2737 case CK_Silvermont: 2738 case CK_Nehalem: 2739 case CK_Westmere: 2740 case CK_SandyBridge: 2741 case CK_IvyBridge: 2742 case CK_Haswell: 2743 case CK_Broadwell: 2744 case CK_SkylakeClient: 2745 case CK_SkylakeServer: 2746 case CK_Cannonlake: 2747 case CK_KNL: 2748 case CK_Athlon64: 2749 case CK_Athlon64SSE3: 2750 case CK_AthlonFX: 2751 case CK_K8: 2752 case CK_K8SSE3: 2753 case CK_Opteron: 2754 case CK_OpteronSSE3: 2755 case CK_AMDFAM10: 2756 case CK_BTVER1: 2757 case CK_BTVER2: 2758 case CK_BDVER1: 2759 case CK_BDVER2: 2760 case CK_BDVER3: 2761 case CK_BDVER4: 2762 case CK_x86_64: 2763 return true; 2764 } 2765 llvm_unreachable("Unhandled CPU kind"); 2766 } 2767 2768 bool setFPMath(StringRef Name) override; 2769 2770 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2771 // Most of the non-ARM calling conventions are i386 conventions. 2772 switch (CC) { 2773 case CC_X86ThisCall: 2774 case CC_X86FastCall: 2775 case CC_X86StdCall: 2776 case CC_X86VectorCall: 2777 case CC_C: 2778 case CC_Swift: 2779 case CC_X86Pascal: 2780 case CC_IntelOclBicc: 2781 return CCCR_OK; 2782 default: 2783 return CCCR_Warning; 2784 } 2785 } 2786 2787 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2788 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2789 } 2790 2791 bool hasSjLjLowering() const override { 2792 return true; 2793 } 2794 2795 void setSupportedOpenCLOpts() override { 2796 getSupportedOpenCLOpts().setAll(); 2797 } 2798 }; 2799 2800 bool X86TargetInfo::setFPMath(StringRef Name) { 2801 if (Name == "387") { 2802 FPMath = FP_387; 2803 return true; 2804 } 2805 if (Name == "sse") { 2806 FPMath = FP_SSE; 2807 return true; 2808 } 2809 return false; 2810 } 2811 2812 bool X86TargetInfo::initFeatureMap( 2813 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2814 const std::vector<std::string> &FeaturesVec) const { 2815 // FIXME: This *really* should not be here. 2816 // X86_64 always has SSE2. 2817 if (getTriple().getArch() == llvm::Triple::x86_64) 2818 setFeatureEnabledImpl(Features, "sse2", true); 2819 2820 const CPUKind Kind = getCPUKind(CPU); 2821 2822 // Enable X87 for all X86 processors but Lakemont. 2823 if (Kind != CK_Lakemont) 2824 setFeatureEnabledImpl(Features, "x87", true); 2825 2826 switch (Kind) { 2827 case CK_Generic: 2828 case CK_i386: 2829 case CK_i486: 2830 case CK_i586: 2831 case CK_Pentium: 2832 case CK_i686: 2833 case CK_PentiumPro: 2834 case CK_Lakemont: 2835 break; 2836 case CK_PentiumMMX: 2837 case CK_Pentium2: 2838 case CK_K6: 2839 case CK_WinChipC6: 2840 setFeatureEnabledImpl(Features, "mmx", true); 2841 break; 2842 case CK_Pentium3: 2843 case CK_Pentium3M: 2844 case CK_C3_2: 2845 setFeatureEnabledImpl(Features, "sse", true); 2846 setFeatureEnabledImpl(Features, "fxsr", true); 2847 break; 2848 case CK_PentiumM: 2849 case CK_Pentium4: 2850 case CK_Pentium4M: 2851 case CK_x86_64: 2852 setFeatureEnabledImpl(Features, "sse2", true); 2853 setFeatureEnabledImpl(Features, "fxsr", true); 2854 break; 2855 case CK_Yonah: 2856 case CK_Prescott: 2857 case CK_Nocona: 2858 setFeatureEnabledImpl(Features, "sse3", true); 2859 setFeatureEnabledImpl(Features, "fxsr", true); 2860 setFeatureEnabledImpl(Features, "cx16", true); 2861 break; 2862 case CK_Core2: 2863 case CK_Bonnell: 2864 setFeatureEnabledImpl(Features, "ssse3", true); 2865 setFeatureEnabledImpl(Features, "fxsr", true); 2866 setFeatureEnabledImpl(Features, "cx16", true); 2867 break; 2868 case CK_Penryn: 2869 setFeatureEnabledImpl(Features, "sse4.1", true); 2870 setFeatureEnabledImpl(Features, "fxsr", true); 2871 setFeatureEnabledImpl(Features, "cx16", true); 2872 break; 2873 case CK_Cannonlake: 2874 setFeatureEnabledImpl(Features, "avx512ifma", true); 2875 setFeatureEnabledImpl(Features, "avx512vbmi", true); 2876 setFeatureEnabledImpl(Features, "sha", true); 2877 setFeatureEnabledImpl(Features, "umip", true); 2878 // FALLTHROUGH 2879 case CK_SkylakeServer: 2880 setFeatureEnabledImpl(Features, "avx512f", true); 2881 setFeatureEnabledImpl(Features, "avx512cd", true); 2882 setFeatureEnabledImpl(Features, "avx512dq", true); 2883 setFeatureEnabledImpl(Features, "avx512bw", true); 2884 setFeatureEnabledImpl(Features, "avx512vl", true); 2885 setFeatureEnabledImpl(Features, "pku", true); 2886 setFeatureEnabledImpl(Features, "pcommit", true); 2887 setFeatureEnabledImpl(Features, "clwb", true); 2888 // FALLTHROUGH 2889 case CK_SkylakeClient: 2890 setFeatureEnabledImpl(Features, "xsavec", true); 2891 setFeatureEnabledImpl(Features, "xsaves", true); 2892 setFeatureEnabledImpl(Features, "mpx", true); 2893 setFeatureEnabledImpl(Features, "sgx", true); 2894 setFeatureEnabledImpl(Features, "clflushopt", true); 2895 // FALLTHROUGH 2896 case CK_Broadwell: 2897 setFeatureEnabledImpl(Features, "rdseed", true); 2898 setFeatureEnabledImpl(Features, "adx", true); 2899 // FALLTHROUGH 2900 case CK_Haswell: 2901 setFeatureEnabledImpl(Features, "avx2", true); 2902 setFeatureEnabledImpl(Features, "lzcnt", true); 2903 setFeatureEnabledImpl(Features, "bmi", true); 2904 setFeatureEnabledImpl(Features, "bmi2", true); 2905 setFeatureEnabledImpl(Features, "rtm", true); 2906 setFeatureEnabledImpl(Features, "fma", true); 2907 setFeatureEnabledImpl(Features, "movbe", true); 2908 // FALLTHROUGH 2909 case CK_IvyBridge: 2910 setFeatureEnabledImpl(Features, "rdrnd", true); 2911 setFeatureEnabledImpl(Features, "f16c", true); 2912 setFeatureEnabledImpl(Features, "fsgsbase", true); 2913 // FALLTHROUGH 2914 case CK_SandyBridge: 2915 setFeatureEnabledImpl(Features, "avx", true); 2916 setFeatureEnabledImpl(Features, "xsave", true); 2917 setFeatureEnabledImpl(Features, "xsaveopt", true); 2918 // FALLTHROUGH 2919 case CK_Westmere: 2920 case CK_Silvermont: 2921 setFeatureEnabledImpl(Features, "aes", true); 2922 setFeatureEnabledImpl(Features, "pclmul", true); 2923 // FALLTHROUGH 2924 case CK_Nehalem: 2925 setFeatureEnabledImpl(Features, "sse4.2", true); 2926 setFeatureEnabledImpl(Features, "fxsr", true); 2927 setFeatureEnabledImpl(Features, "cx16", true); 2928 break; 2929 case CK_KNL: 2930 setFeatureEnabledImpl(Features, "avx512f", true); 2931 setFeatureEnabledImpl(Features, "avx512cd", true); 2932 setFeatureEnabledImpl(Features, "avx512er", true); 2933 setFeatureEnabledImpl(Features, "avx512pf", true); 2934 setFeatureEnabledImpl(Features, "prefetchwt1", true); 2935 setFeatureEnabledImpl(Features, "fxsr", true); 2936 setFeatureEnabledImpl(Features, "rdseed", true); 2937 setFeatureEnabledImpl(Features, "adx", true); 2938 setFeatureEnabledImpl(Features, "lzcnt", true); 2939 setFeatureEnabledImpl(Features, "bmi", true); 2940 setFeatureEnabledImpl(Features, "bmi2", true); 2941 setFeatureEnabledImpl(Features, "rtm", true); 2942 setFeatureEnabledImpl(Features, "fma", true); 2943 setFeatureEnabledImpl(Features, "rdrnd", true); 2944 setFeatureEnabledImpl(Features, "f16c", true); 2945 setFeatureEnabledImpl(Features, "fsgsbase", true); 2946 setFeatureEnabledImpl(Features, "aes", true); 2947 setFeatureEnabledImpl(Features, "pclmul", true); 2948 setFeatureEnabledImpl(Features, "cx16", true); 2949 setFeatureEnabledImpl(Features, "xsaveopt", true); 2950 setFeatureEnabledImpl(Features, "xsave", true); 2951 setFeatureEnabledImpl(Features, "movbe", true); 2952 break; 2953 case CK_K6_2: 2954 case CK_K6_3: 2955 case CK_WinChip2: 2956 case CK_C3: 2957 setFeatureEnabledImpl(Features, "3dnow", true); 2958 break; 2959 case CK_Athlon: 2960 case CK_AthlonThunderbird: 2961 case CK_Geode: 2962 setFeatureEnabledImpl(Features, "3dnowa", true); 2963 break; 2964 case CK_Athlon4: 2965 case CK_AthlonXP: 2966 case CK_AthlonMP: 2967 setFeatureEnabledImpl(Features, "sse", true); 2968 setFeatureEnabledImpl(Features, "3dnowa", true); 2969 setFeatureEnabledImpl(Features, "fxsr", true); 2970 break; 2971 case CK_K8: 2972 case CK_Opteron: 2973 case CK_Athlon64: 2974 case CK_AthlonFX: 2975 setFeatureEnabledImpl(Features, "sse2", true); 2976 setFeatureEnabledImpl(Features, "3dnowa", true); 2977 setFeatureEnabledImpl(Features, "fxsr", true); 2978 break; 2979 case CK_AMDFAM10: 2980 setFeatureEnabledImpl(Features, "sse4a", true); 2981 setFeatureEnabledImpl(Features, "lzcnt", true); 2982 setFeatureEnabledImpl(Features, "popcnt", true); 2983 // FALLTHROUGH 2984 case CK_K8SSE3: 2985 case CK_OpteronSSE3: 2986 case CK_Athlon64SSE3: 2987 setFeatureEnabledImpl(Features, "sse3", true); 2988 setFeatureEnabledImpl(Features, "3dnowa", true); 2989 setFeatureEnabledImpl(Features, "fxsr", true); 2990 break; 2991 case CK_BTVER2: 2992 setFeatureEnabledImpl(Features, "avx", true); 2993 setFeatureEnabledImpl(Features, "aes", true); 2994 setFeatureEnabledImpl(Features, "pclmul", true); 2995 setFeatureEnabledImpl(Features, "bmi", true); 2996 setFeatureEnabledImpl(Features, "f16c", true); 2997 setFeatureEnabledImpl(Features, "xsaveopt", true); 2998 // FALLTHROUGH 2999 case CK_BTVER1: 3000 setFeatureEnabledImpl(Features, "ssse3", true); 3001 setFeatureEnabledImpl(Features, "sse4a", true); 3002 setFeatureEnabledImpl(Features, "lzcnt", true); 3003 setFeatureEnabledImpl(Features, "popcnt", true); 3004 setFeatureEnabledImpl(Features, "prfchw", true); 3005 setFeatureEnabledImpl(Features, "cx16", true); 3006 setFeatureEnabledImpl(Features, "fxsr", true); 3007 break; 3008 case CK_BDVER4: 3009 setFeatureEnabledImpl(Features, "avx2", true); 3010 setFeatureEnabledImpl(Features, "bmi2", true); 3011 setFeatureEnabledImpl(Features, "mwaitx", true); 3012 // FALLTHROUGH 3013 case CK_BDVER3: 3014 setFeatureEnabledImpl(Features, "fsgsbase", true); 3015 setFeatureEnabledImpl(Features, "xsaveopt", true); 3016 // FALLTHROUGH 3017 case CK_BDVER2: 3018 setFeatureEnabledImpl(Features, "bmi", true); 3019 setFeatureEnabledImpl(Features, "fma", true); 3020 setFeatureEnabledImpl(Features, "f16c", true); 3021 setFeatureEnabledImpl(Features, "tbm", true); 3022 // FALLTHROUGH 3023 case CK_BDVER1: 3024 // xop implies avx, sse4a and fma4. 3025 setFeatureEnabledImpl(Features, "xop", true); 3026 setFeatureEnabledImpl(Features, "lzcnt", true); 3027 setFeatureEnabledImpl(Features, "aes", true); 3028 setFeatureEnabledImpl(Features, "pclmul", true); 3029 setFeatureEnabledImpl(Features, "prfchw", true); 3030 setFeatureEnabledImpl(Features, "cx16", true); 3031 setFeatureEnabledImpl(Features, "fxsr", true); 3032 setFeatureEnabledImpl(Features, "xsave", true); 3033 break; 3034 } 3035 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3036 return false; 3037 3038 // Can't do this earlier because we need to be able to explicitly enable 3039 // or disable these features and the things that they depend upon. 3040 3041 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3042 auto I = Features.find("sse4.2"); 3043 if (I != Features.end() && I->getValue() && 3044 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3045 FeaturesVec.end()) 3046 Features["popcnt"] = true; 3047 3048 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3049 I = Features.find("3dnow"); 3050 if (I != Features.end() && I->getValue() && 3051 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3052 FeaturesVec.end()) 3053 Features["prfchw"] = true; 3054 3055 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3056 // then enable MMX. 3057 I = Features.find("sse"); 3058 if (I != Features.end() && I->getValue() && 3059 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3060 FeaturesVec.end()) 3061 Features["mmx"] = true; 3062 3063 return true; 3064 } 3065 3066 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3067 X86SSEEnum Level, bool Enabled) { 3068 if (Enabled) { 3069 switch (Level) { 3070 case AVX512F: 3071 Features["avx512f"] = true; 3072 case AVX2: 3073 Features["avx2"] = true; 3074 case AVX: 3075 Features["avx"] = true; 3076 Features["xsave"] = true; 3077 case SSE42: 3078 Features["sse4.2"] = true; 3079 case SSE41: 3080 Features["sse4.1"] = true; 3081 case SSSE3: 3082 Features["ssse3"] = true; 3083 case SSE3: 3084 Features["sse3"] = true; 3085 case SSE2: 3086 Features["sse2"] = true; 3087 case SSE1: 3088 Features["sse"] = true; 3089 case NoSSE: 3090 break; 3091 } 3092 return; 3093 } 3094 3095 switch (Level) { 3096 case NoSSE: 3097 case SSE1: 3098 Features["sse"] = false; 3099 case SSE2: 3100 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3101 Features["sha"] = false; 3102 case SSE3: 3103 Features["sse3"] = false; 3104 setXOPLevel(Features, NoXOP, false); 3105 case SSSE3: 3106 Features["ssse3"] = false; 3107 case SSE41: 3108 Features["sse4.1"] = false; 3109 case SSE42: 3110 Features["sse4.2"] = false; 3111 case AVX: 3112 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3113 Features["xsaveopt"] = false; 3114 setXOPLevel(Features, FMA4, false); 3115 case AVX2: 3116 Features["avx2"] = false; 3117 case AVX512F: 3118 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3119 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3120 Features["avx512vl"] = Features["avx512vbmi"] = 3121 Features["avx512ifma"] = false; 3122 } 3123 } 3124 3125 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3126 MMX3DNowEnum Level, bool Enabled) { 3127 if (Enabled) { 3128 switch (Level) { 3129 case AMD3DNowAthlon: 3130 Features["3dnowa"] = true; 3131 case AMD3DNow: 3132 Features["3dnow"] = true; 3133 case MMX: 3134 Features["mmx"] = true; 3135 case NoMMX3DNow: 3136 break; 3137 } 3138 return; 3139 } 3140 3141 switch (Level) { 3142 case NoMMX3DNow: 3143 case MMX: 3144 Features["mmx"] = false; 3145 case AMD3DNow: 3146 Features["3dnow"] = false; 3147 case AMD3DNowAthlon: 3148 Features["3dnowa"] = false; 3149 } 3150 } 3151 3152 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3153 bool Enabled) { 3154 if (Enabled) { 3155 switch (Level) { 3156 case XOP: 3157 Features["xop"] = true; 3158 case FMA4: 3159 Features["fma4"] = true; 3160 setSSELevel(Features, AVX, true); 3161 case SSE4A: 3162 Features["sse4a"] = true; 3163 setSSELevel(Features, SSE3, true); 3164 case NoXOP: 3165 break; 3166 } 3167 return; 3168 } 3169 3170 switch (Level) { 3171 case NoXOP: 3172 case SSE4A: 3173 Features["sse4a"] = false; 3174 case FMA4: 3175 Features["fma4"] = false; 3176 case XOP: 3177 Features["xop"] = false; 3178 } 3179 } 3180 3181 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3182 StringRef Name, bool Enabled) { 3183 // This is a bit of a hack to deal with the sse4 target feature when used 3184 // as part of the target attribute. We handle sse4 correctly everywhere 3185 // else. See below for more information on how we handle the sse4 options. 3186 if (Name != "sse4") 3187 Features[Name] = Enabled; 3188 3189 if (Name == "mmx") { 3190 setMMXLevel(Features, MMX, Enabled); 3191 } else if (Name == "sse") { 3192 setSSELevel(Features, SSE1, Enabled); 3193 } else if (Name == "sse2") { 3194 setSSELevel(Features, SSE2, Enabled); 3195 } else if (Name == "sse3") { 3196 setSSELevel(Features, SSE3, Enabled); 3197 } else if (Name == "ssse3") { 3198 setSSELevel(Features, SSSE3, Enabled); 3199 } else if (Name == "sse4.2") { 3200 setSSELevel(Features, SSE42, Enabled); 3201 } else if (Name == "sse4.1") { 3202 setSSELevel(Features, SSE41, Enabled); 3203 } else if (Name == "3dnow") { 3204 setMMXLevel(Features, AMD3DNow, Enabled); 3205 } else if (Name == "3dnowa") { 3206 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3207 } else if (Name == "aes") { 3208 if (Enabled) 3209 setSSELevel(Features, SSE2, Enabled); 3210 } else if (Name == "pclmul") { 3211 if (Enabled) 3212 setSSELevel(Features, SSE2, Enabled); 3213 } else if (Name == "avx") { 3214 setSSELevel(Features, AVX, Enabled); 3215 } else if (Name == "avx2") { 3216 setSSELevel(Features, AVX2, Enabled); 3217 } else if (Name == "avx512f") { 3218 setSSELevel(Features, AVX512F, Enabled); 3219 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3220 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3221 Name == "avx512vbmi" || Name == "avx512ifma") { 3222 if (Enabled) 3223 setSSELevel(Features, AVX512F, Enabled); 3224 } else if (Name == "fma") { 3225 if (Enabled) 3226 setSSELevel(Features, AVX, Enabled); 3227 } else if (Name == "fma4") { 3228 setXOPLevel(Features, FMA4, Enabled); 3229 } else if (Name == "xop") { 3230 setXOPLevel(Features, XOP, Enabled); 3231 } else if (Name == "sse4a") { 3232 setXOPLevel(Features, SSE4A, Enabled); 3233 } else if (Name == "f16c") { 3234 if (Enabled) 3235 setSSELevel(Features, AVX, Enabled); 3236 } else if (Name == "sha") { 3237 if (Enabled) 3238 setSSELevel(Features, SSE2, Enabled); 3239 } else if (Name == "sse4") { 3240 // We can get here via the __target__ attribute since that's not controlled 3241 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3242 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3243 // disabled. 3244 if (Enabled) 3245 setSSELevel(Features, SSE42, Enabled); 3246 else 3247 setSSELevel(Features, SSE41, Enabled); 3248 } else if (Name == "xsave") { 3249 if (!Enabled) 3250 Features["xsaveopt"] = false; 3251 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3252 if (Enabled) 3253 Features["xsave"] = true; 3254 } 3255 } 3256 3257 /// handleTargetFeatures - Perform initialization based on the user 3258 /// configured set of features. 3259 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3260 DiagnosticsEngine &Diags) { 3261 for (const auto &Feature : Features) { 3262 if (Feature[0] != '+') 3263 continue; 3264 3265 if (Feature == "+aes") { 3266 HasAES = true; 3267 } else if (Feature == "+pclmul") { 3268 HasPCLMUL = true; 3269 } else if (Feature == "+lzcnt") { 3270 HasLZCNT = true; 3271 } else if (Feature == "+rdrnd") { 3272 HasRDRND = true; 3273 } else if (Feature == "+fsgsbase") { 3274 HasFSGSBASE = true; 3275 } else if (Feature == "+bmi") { 3276 HasBMI = true; 3277 } else if (Feature == "+bmi2") { 3278 HasBMI2 = true; 3279 } else if (Feature == "+popcnt") { 3280 HasPOPCNT = true; 3281 } else if (Feature == "+rtm") { 3282 HasRTM = true; 3283 } else if (Feature == "+prfchw") { 3284 HasPRFCHW = true; 3285 } else if (Feature == "+rdseed") { 3286 HasRDSEED = true; 3287 } else if (Feature == "+adx") { 3288 HasADX = true; 3289 } else if (Feature == "+tbm") { 3290 HasTBM = true; 3291 } else if (Feature == "+fma") { 3292 HasFMA = true; 3293 } else if (Feature == "+f16c") { 3294 HasF16C = true; 3295 } else if (Feature == "+avx512cd") { 3296 HasAVX512CD = true; 3297 } else if (Feature == "+avx512er") { 3298 HasAVX512ER = true; 3299 } else if (Feature == "+avx512pf") { 3300 HasAVX512PF = true; 3301 } else if (Feature == "+avx512dq") { 3302 HasAVX512DQ = true; 3303 } else if (Feature == "+avx512bw") { 3304 HasAVX512BW = true; 3305 } else if (Feature == "+avx512vl") { 3306 HasAVX512VL = true; 3307 } else if (Feature == "+avx512vbmi") { 3308 HasAVX512VBMI = true; 3309 } else if (Feature == "+avx512ifma") { 3310 HasAVX512IFMA = true; 3311 } else if (Feature == "+sha") { 3312 HasSHA = true; 3313 } else if (Feature == "+mpx") { 3314 HasMPX = true; 3315 } else if (Feature == "+movbe") { 3316 HasMOVBE = true; 3317 } else if (Feature == "+sgx") { 3318 HasSGX = true; 3319 } else if (Feature == "+cx16") { 3320 HasCX16 = true; 3321 } else if (Feature == "+fxsr") { 3322 HasFXSR = true; 3323 } else if (Feature == "+xsave") { 3324 HasXSAVE = true; 3325 } else if (Feature == "+xsaveopt") { 3326 HasXSAVEOPT = true; 3327 } else if (Feature == "+xsavec") { 3328 HasXSAVEC = true; 3329 } else if (Feature == "+xsaves") { 3330 HasXSAVES = true; 3331 } else if (Feature == "+mwaitx") { 3332 HasMWAITX = true; 3333 } else if (Feature == "+pku") { 3334 HasPKU = true; 3335 } else if (Feature == "+clflushopt") { 3336 HasCLFLUSHOPT = true; 3337 } else if (Feature == "+pcommit") { 3338 HasPCOMMIT = true; 3339 } else if (Feature == "+clwb") { 3340 HasCLWB = true; 3341 } else if (Feature == "+umip") { 3342 HasUMIP = true; 3343 } else if (Feature == "+prefetchwt1") { 3344 HasPREFETCHWT1 = true; 3345 } 3346 3347 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3348 .Case("+avx512f", AVX512F) 3349 .Case("+avx2", AVX2) 3350 .Case("+avx", AVX) 3351 .Case("+sse4.2", SSE42) 3352 .Case("+sse4.1", SSE41) 3353 .Case("+ssse3", SSSE3) 3354 .Case("+sse3", SSE3) 3355 .Case("+sse2", SSE2) 3356 .Case("+sse", SSE1) 3357 .Default(NoSSE); 3358 SSELevel = std::max(SSELevel, Level); 3359 3360 MMX3DNowEnum ThreeDNowLevel = 3361 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3362 .Case("+3dnowa", AMD3DNowAthlon) 3363 .Case("+3dnow", AMD3DNow) 3364 .Case("+mmx", MMX) 3365 .Default(NoMMX3DNow); 3366 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3367 3368 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3369 .Case("+xop", XOP) 3370 .Case("+fma4", FMA4) 3371 .Case("+sse4a", SSE4A) 3372 .Default(NoXOP); 3373 XOPLevel = std::max(XOPLevel, XLevel); 3374 } 3375 3376 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3377 // matches the selected sse level. 3378 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3379 (FPMath == FP_387 && SSELevel >= SSE1)) { 3380 Diags.Report(diag::err_target_unsupported_fpmath) << 3381 (FPMath == FP_SSE ? "sse" : "387"); 3382 return false; 3383 } 3384 3385 SimdDefaultAlign = 3386 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3387 return true; 3388 } 3389 3390 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3391 /// definitions for this particular subtarget. 3392 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3393 MacroBuilder &Builder) const { 3394 // Target identification. 3395 if (getTriple().getArch() == llvm::Triple::x86_64) { 3396 Builder.defineMacro("__amd64__"); 3397 Builder.defineMacro("__amd64"); 3398 Builder.defineMacro("__x86_64"); 3399 Builder.defineMacro("__x86_64__"); 3400 if (getTriple().getArchName() == "x86_64h") { 3401 Builder.defineMacro("__x86_64h"); 3402 Builder.defineMacro("__x86_64h__"); 3403 } 3404 } else { 3405 DefineStd(Builder, "i386", Opts); 3406 } 3407 3408 // Subtarget options. 3409 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3410 // truly should be based on -mtune options. 3411 switch (CPU) { 3412 case CK_Generic: 3413 break; 3414 case CK_i386: 3415 // The rest are coming from the i386 define above. 3416 Builder.defineMacro("__tune_i386__"); 3417 break; 3418 case CK_i486: 3419 case CK_WinChipC6: 3420 case CK_WinChip2: 3421 case CK_C3: 3422 defineCPUMacros(Builder, "i486"); 3423 break; 3424 case CK_PentiumMMX: 3425 Builder.defineMacro("__pentium_mmx__"); 3426 Builder.defineMacro("__tune_pentium_mmx__"); 3427 // Fallthrough 3428 case CK_i586: 3429 case CK_Pentium: 3430 defineCPUMacros(Builder, "i586"); 3431 defineCPUMacros(Builder, "pentium"); 3432 break; 3433 case CK_Pentium3: 3434 case CK_Pentium3M: 3435 case CK_PentiumM: 3436 Builder.defineMacro("__tune_pentium3__"); 3437 // Fallthrough 3438 case CK_Pentium2: 3439 case CK_C3_2: 3440 Builder.defineMacro("__tune_pentium2__"); 3441 // Fallthrough 3442 case CK_PentiumPro: 3443 Builder.defineMacro("__tune_i686__"); 3444 Builder.defineMacro("__tune_pentiumpro__"); 3445 // Fallthrough 3446 case CK_i686: 3447 Builder.defineMacro("__i686"); 3448 Builder.defineMacro("__i686__"); 3449 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3450 Builder.defineMacro("__pentiumpro"); 3451 Builder.defineMacro("__pentiumpro__"); 3452 break; 3453 case CK_Pentium4: 3454 case CK_Pentium4M: 3455 defineCPUMacros(Builder, "pentium4"); 3456 break; 3457 case CK_Yonah: 3458 case CK_Prescott: 3459 case CK_Nocona: 3460 defineCPUMacros(Builder, "nocona"); 3461 break; 3462 case CK_Core2: 3463 case CK_Penryn: 3464 defineCPUMacros(Builder, "core2"); 3465 break; 3466 case CK_Bonnell: 3467 defineCPUMacros(Builder, "atom"); 3468 break; 3469 case CK_Silvermont: 3470 defineCPUMacros(Builder, "slm"); 3471 break; 3472 case CK_Nehalem: 3473 case CK_Westmere: 3474 case CK_SandyBridge: 3475 case CK_IvyBridge: 3476 case CK_Haswell: 3477 case CK_Broadwell: 3478 case CK_SkylakeClient: 3479 // FIXME: Historically, we defined this legacy name, it would be nice to 3480 // remove it at some point. We've never exposed fine-grained names for 3481 // recent primary x86 CPUs, and we should keep it that way. 3482 defineCPUMacros(Builder, "corei7"); 3483 break; 3484 case CK_SkylakeServer: 3485 defineCPUMacros(Builder, "skx"); 3486 break; 3487 case CK_Cannonlake: 3488 break; 3489 case CK_KNL: 3490 defineCPUMacros(Builder, "knl"); 3491 break; 3492 case CK_Lakemont: 3493 Builder.defineMacro("__tune_lakemont__"); 3494 break; 3495 case CK_K6_2: 3496 Builder.defineMacro("__k6_2__"); 3497 Builder.defineMacro("__tune_k6_2__"); 3498 // Fallthrough 3499 case CK_K6_3: 3500 if (CPU != CK_K6_2) { // In case of fallthrough 3501 // FIXME: GCC may be enabling these in cases where some other k6 3502 // architecture is specified but -m3dnow is explicitly provided. The 3503 // exact semantics need to be determined and emulated here. 3504 Builder.defineMacro("__k6_3__"); 3505 Builder.defineMacro("__tune_k6_3__"); 3506 } 3507 // Fallthrough 3508 case CK_K6: 3509 defineCPUMacros(Builder, "k6"); 3510 break; 3511 case CK_Athlon: 3512 case CK_AthlonThunderbird: 3513 case CK_Athlon4: 3514 case CK_AthlonXP: 3515 case CK_AthlonMP: 3516 defineCPUMacros(Builder, "athlon"); 3517 if (SSELevel != NoSSE) { 3518 Builder.defineMacro("__athlon_sse__"); 3519 Builder.defineMacro("__tune_athlon_sse__"); 3520 } 3521 break; 3522 case CK_K8: 3523 case CK_K8SSE3: 3524 case CK_x86_64: 3525 case CK_Opteron: 3526 case CK_OpteronSSE3: 3527 case CK_Athlon64: 3528 case CK_Athlon64SSE3: 3529 case CK_AthlonFX: 3530 defineCPUMacros(Builder, "k8"); 3531 break; 3532 case CK_AMDFAM10: 3533 defineCPUMacros(Builder, "amdfam10"); 3534 break; 3535 case CK_BTVER1: 3536 defineCPUMacros(Builder, "btver1"); 3537 break; 3538 case CK_BTVER2: 3539 defineCPUMacros(Builder, "btver2"); 3540 break; 3541 case CK_BDVER1: 3542 defineCPUMacros(Builder, "bdver1"); 3543 break; 3544 case CK_BDVER2: 3545 defineCPUMacros(Builder, "bdver2"); 3546 break; 3547 case CK_BDVER3: 3548 defineCPUMacros(Builder, "bdver3"); 3549 break; 3550 case CK_BDVER4: 3551 defineCPUMacros(Builder, "bdver4"); 3552 break; 3553 case CK_Geode: 3554 defineCPUMacros(Builder, "geode"); 3555 break; 3556 } 3557 3558 // Target properties. 3559 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3560 3561 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3562 // functions in glibc header files that use FP Stack inline asm which the 3563 // backend can't deal with (PR879). 3564 Builder.defineMacro("__NO_MATH_INLINES"); 3565 3566 if (HasAES) 3567 Builder.defineMacro("__AES__"); 3568 3569 if (HasPCLMUL) 3570 Builder.defineMacro("__PCLMUL__"); 3571 3572 if (HasLZCNT) 3573 Builder.defineMacro("__LZCNT__"); 3574 3575 if (HasRDRND) 3576 Builder.defineMacro("__RDRND__"); 3577 3578 if (HasFSGSBASE) 3579 Builder.defineMacro("__FSGSBASE__"); 3580 3581 if (HasBMI) 3582 Builder.defineMacro("__BMI__"); 3583 3584 if (HasBMI2) 3585 Builder.defineMacro("__BMI2__"); 3586 3587 if (HasPOPCNT) 3588 Builder.defineMacro("__POPCNT__"); 3589 3590 if (HasRTM) 3591 Builder.defineMacro("__RTM__"); 3592 3593 if (HasPRFCHW) 3594 Builder.defineMacro("__PRFCHW__"); 3595 3596 if (HasRDSEED) 3597 Builder.defineMacro("__RDSEED__"); 3598 3599 if (HasADX) 3600 Builder.defineMacro("__ADX__"); 3601 3602 if (HasTBM) 3603 Builder.defineMacro("__TBM__"); 3604 3605 if (HasMWAITX) 3606 Builder.defineMacro("__MWAITX__"); 3607 3608 switch (XOPLevel) { 3609 case XOP: 3610 Builder.defineMacro("__XOP__"); 3611 case FMA4: 3612 Builder.defineMacro("__FMA4__"); 3613 case SSE4A: 3614 Builder.defineMacro("__SSE4A__"); 3615 case NoXOP: 3616 break; 3617 } 3618 3619 if (HasFMA) 3620 Builder.defineMacro("__FMA__"); 3621 3622 if (HasF16C) 3623 Builder.defineMacro("__F16C__"); 3624 3625 if (HasAVX512CD) 3626 Builder.defineMacro("__AVX512CD__"); 3627 if (HasAVX512ER) 3628 Builder.defineMacro("__AVX512ER__"); 3629 if (HasAVX512PF) 3630 Builder.defineMacro("__AVX512PF__"); 3631 if (HasAVX512DQ) 3632 Builder.defineMacro("__AVX512DQ__"); 3633 if (HasAVX512BW) 3634 Builder.defineMacro("__AVX512BW__"); 3635 if (HasAVX512VL) 3636 Builder.defineMacro("__AVX512VL__"); 3637 if (HasAVX512VBMI) 3638 Builder.defineMacro("__AVX512VBMI__"); 3639 if (HasAVX512IFMA) 3640 Builder.defineMacro("__AVX512IFMA__"); 3641 3642 if (HasSHA) 3643 Builder.defineMacro("__SHA__"); 3644 3645 if (HasFXSR) 3646 Builder.defineMacro("__FXSR__"); 3647 if (HasXSAVE) 3648 Builder.defineMacro("__XSAVE__"); 3649 if (HasXSAVEOPT) 3650 Builder.defineMacro("__XSAVEOPT__"); 3651 if (HasXSAVEC) 3652 Builder.defineMacro("__XSAVEC__"); 3653 if (HasXSAVES) 3654 Builder.defineMacro("__XSAVES__"); 3655 if (HasPKU) 3656 Builder.defineMacro("__PKU__"); 3657 if (HasCX16) 3658 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3659 3660 // Each case falls through to the previous one here. 3661 switch (SSELevel) { 3662 case AVX512F: 3663 Builder.defineMacro("__AVX512F__"); 3664 case AVX2: 3665 Builder.defineMacro("__AVX2__"); 3666 case AVX: 3667 Builder.defineMacro("__AVX__"); 3668 case SSE42: 3669 Builder.defineMacro("__SSE4_2__"); 3670 case SSE41: 3671 Builder.defineMacro("__SSE4_1__"); 3672 case SSSE3: 3673 Builder.defineMacro("__SSSE3__"); 3674 case SSE3: 3675 Builder.defineMacro("__SSE3__"); 3676 case SSE2: 3677 Builder.defineMacro("__SSE2__"); 3678 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3679 case SSE1: 3680 Builder.defineMacro("__SSE__"); 3681 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3682 case NoSSE: 3683 break; 3684 } 3685 3686 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3687 switch (SSELevel) { 3688 case AVX512F: 3689 case AVX2: 3690 case AVX: 3691 case SSE42: 3692 case SSE41: 3693 case SSSE3: 3694 case SSE3: 3695 case SSE2: 3696 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3697 break; 3698 case SSE1: 3699 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3700 break; 3701 default: 3702 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3703 } 3704 } 3705 3706 // Each case falls through to the previous one here. 3707 switch (MMX3DNowLevel) { 3708 case AMD3DNowAthlon: 3709 Builder.defineMacro("__3dNOW_A__"); 3710 case AMD3DNow: 3711 Builder.defineMacro("__3dNOW__"); 3712 case MMX: 3713 Builder.defineMacro("__MMX__"); 3714 case NoMMX3DNow: 3715 break; 3716 } 3717 3718 if (CPU >= CK_i486) { 3719 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3720 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3721 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3722 } 3723 if (CPU >= CK_i586) 3724 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3725 } 3726 3727 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3728 return llvm::StringSwitch<bool>(Feature) 3729 .Case("aes", HasAES) 3730 .Case("avx", SSELevel >= AVX) 3731 .Case("avx2", SSELevel >= AVX2) 3732 .Case("avx512f", SSELevel >= AVX512F) 3733 .Case("avx512cd", HasAVX512CD) 3734 .Case("avx512er", HasAVX512ER) 3735 .Case("avx512pf", HasAVX512PF) 3736 .Case("avx512dq", HasAVX512DQ) 3737 .Case("avx512bw", HasAVX512BW) 3738 .Case("avx512vl", HasAVX512VL) 3739 .Case("avx512vbmi", HasAVX512VBMI) 3740 .Case("avx512ifma", HasAVX512IFMA) 3741 .Case("bmi", HasBMI) 3742 .Case("bmi2", HasBMI2) 3743 .Case("clflushopt", HasCLFLUSHOPT) 3744 .Case("clwb", HasCLWB) 3745 .Case("cx16", HasCX16) 3746 .Case("f16c", HasF16C) 3747 .Case("fma", HasFMA) 3748 .Case("fma4", XOPLevel >= FMA4) 3749 .Case("fsgsbase", HasFSGSBASE) 3750 .Case("fxsr", HasFXSR) 3751 .Case("lzcnt", HasLZCNT) 3752 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3753 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3754 .Case("mmx", MMX3DNowLevel >= MMX) 3755 .Case("movbe", HasMOVBE) 3756 .Case("mpx", HasMPX) 3757 .Case("pclmul", HasPCLMUL) 3758 .Case("pcommit", HasPCOMMIT) 3759 .Case("pku", HasPKU) 3760 .Case("popcnt", HasPOPCNT) 3761 .Case("prefetchwt1", HasPREFETCHWT1) 3762 .Case("prfchw", HasPRFCHW) 3763 .Case("rdrnd", HasRDRND) 3764 .Case("rdseed", HasRDSEED) 3765 .Case("rtm", HasRTM) 3766 .Case("sgx", HasSGX) 3767 .Case("sha", HasSHA) 3768 .Case("sse", SSELevel >= SSE1) 3769 .Case("sse2", SSELevel >= SSE2) 3770 .Case("sse3", SSELevel >= SSE3) 3771 .Case("ssse3", SSELevel >= SSSE3) 3772 .Case("sse4.1", SSELevel >= SSE41) 3773 .Case("sse4.2", SSELevel >= SSE42) 3774 .Case("sse4a", XOPLevel >= SSE4A) 3775 .Case("tbm", HasTBM) 3776 .Case("umip", HasUMIP) 3777 .Case("x86", true) 3778 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3779 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3780 .Case("xop", XOPLevel >= XOP) 3781 .Case("xsave", HasXSAVE) 3782 .Case("xsavec", HasXSAVEC) 3783 .Case("xsaves", HasXSAVES) 3784 .Case("xsaveopt", HasXSAVEOPT) 3785 .Default(false); 3786 } 3787 3788 // We can't use a generic validation scheme for the features accepted here 3789 // versus subtarget features accepted in the target attribute because the 3790 // bitfield structure that's initialized in the runtime only supports the 3791 // below currently rather than the full range of subtarget features. (See 3792 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3793 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3794 return llvm::StringSwitch<bool>(FeatureStr) 3795 .Case("cmov", true) 3796 .Case("mmx", true) 3797 .Case("popcnt", true) 3798 .Case("sse", true) 3799 .Case("sse2", true) 3800 .Case("sse3", true) 3801 .Case("ssse3", true) 3802 .Case("sse4.1", true) 3803 .Case("sse4.2", true) 3804 .Case("avx", true) 3805 .Case("avx2", true) 3806 .Case("sse4a", true) 3807 .Case("fma4", true) 3808 .Case("xop", true) 3809 .Case("fma", true) 3810 .Case("avx512f", true) 3811 .Case("bmi", true) 3812 .Case("bmi2", true) 3813 .Case("aes", true) 3814 .Case("pclmul", true) 3815 .Case("avx512vl", true) 3816 .Case("avx512bw", true) 3817 .Case("avx512dq", true) 3818 .Case("avx512cd", true) 3819 .Case("avx512er", true) 3820 .Case("avx512pf", true) 3821 .Case("avx512vbmi", true) 3822 .Case("avx512ifma", true) 3823 .Default(false); 3824 } 3825 3826 bool 3827 X86TargetInfo::validateAsmConstraint(const char *&Name, 3828 TargetInfo::ConstraintInfo &Info) const { 3829 switch (*Name) { 3830 default: return false; 3831 // Constant constraints. 3832 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3833 // instructions. 3834 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3835 // x86_64 instructions. 3836 case 's': 3837 Info.setRequiresImmediate(); 3838 return true; 3839 case 'I': 3840 Info.setRequiresImmediate(0, 31); 3841 return true; 3842 case 'J': 3843 Info.setRequiresImmediate(0, 63); 3844 return true; 3845 case 'K': 3846 Info.setRequiresImmediate(-128, 127); 3847 return true; 3848 case 'L': 3849 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3850 return true; 3851 case 'M': 3852 Info.setRequiresImmediate(0, 3); 3853 return true; 3854 case 'N': 3855 Info.setRequiresImmediate(0, 255); 3856 return true; 3857 case 'O': 3858 Info.setRequiresImmediate(0, 127); 3859 return true; 3860 // Register constraints. 3861 case 'Y': // 'Y' is the first character for several 2-character constraints. 3862 // Shift the pointer to the second character of the constraint. 3863 Name++; 3864 switch (*Name) { 3865 default: 3866 return false; 3867 case '0': // First SSE register. 3868 case 't': // Any SSE register, when SSE2 is enabled. 3869 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3870 case 'm': // Any MMX register, when inter-unit moves enabled. 3871 Info.setAllowsRegister(); 3872 return true; 3873 } 3874 case 'f': // Any x87 floating point stack register. 3875 // Constraint 'f' cannot be used for output operands. 3876 if (Info.ConstraintStr[0] == '=') 3877 return false; 3878 Info.setAllowsRegister(); 3879 return true; 3880 case 'a': // eax. 3881 case 'b': // ebx. 3882 case 'c': // ecx. 3883 case 'd': // edx. 3884 case 'S': // esi. 3885 case 'D': // edi. 3886 case 'A': // edx:eax. 3887 case 't': // Top of floating point stack. 3888 case 'u': // Second from top of floating point stack. 3889 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3890 case 'y': // Any MMX register. 3891 case 'x': // Any SSE register. 3892 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3893 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3894 case 'l': // "Index" registers: any general register that can be used as an 3895 // index in a base+index memory access. 3896 Info.setAllowsRegister(); 3897 return true; 3898 // Floating point constant constraints. 3899 case 'C': // SSE floating point constant. 3900 case 'G': // x87 floating point constant. 3901 return true; 3902 } 3903 } 3904 3905 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3906 unsigned Size) const { 3907 // Strip off constraint modifiers. 3908 while (Constraint[0] == '=' || 3909 Constraint[0] == '+' || 3910 Constraint[0] == '&') 3911 Constraint = Constraint.substr(1); 3912 3913 return validateOperandSize(Constraint, Size); 3914 } 3915 3916 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3917 unsigned Size) const { 3918 return validateOperandSize(Constraint, Size); 3919 } 3920 3921 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3922 unsigned Size) const { 3923 switch (Constraint[0]) { 3924 default: break; 3925 case 'y': 3926 return Size <= 64; 3927 case 'f': 3928 case 't': 3929 case 'u': 3930 return Size <= 128; 3931 case 'x': 3932 if (SSELevel >= AVX512F) 3933 // 512-bit zmm registers can be used if target supports AVX512F. 3934 return Size <= 512U; 3935 else if (SSELevel >= AVX) 3936 // 256-bit ymm registers can be used if target supports AVX. 3937 return Size <= 256U; 3938 return Size <= 128U; 3939 case 'Y': 3940 // 'Y' is the first character for several 2-character constraints. 3941 switch (Constraint[1]) { 3942 default: break; 3943 case 'm': 3944 // 'Ym' is synonymous with 'y'. 3945 return Size <= 64; 3946 case 'i': 3947 case 't': 3948 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3949 if (SSELevel >= AVX512F) 3950 return Size <= 512U; 3951 else if (SSELevel >= AVX) 3952 return Size <= 256U; 3953 return SSELevel >= SSE2 && Size <= 128U; 3954 } 3955 3956 } 3957 3958 return true; 3959 } 3960 3961 std::string 3962 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3963 switch (*Constraint) { 3964 case 'a': return std::string("{ax}"); 3965 case 'b': return std::string("{bx}"); 3966 case 'c': return std::string("{cx}"); 3967 case 'd': return std::string("{dx}"); 3968 case 'S': return std::string("{si}"); 3969 case 'D': return std::string("{di}"); 3970 case 'p': // address 3971 return std::string("im"); 3972 case 't': // top of floating point stack. 3973 return std::string("{st}"); 3974 case 'u': // second from top of floating point stack. 3975 return std::string("{st(1)}"); // second from top of floating point stack. 3976 default: 3977 return std::string(1, *Constraint); 3978 } 3979 } 3980 3981 // X86-32 generic target 3982 class X86_32TargetInfo : public X86TargetInfo { 3983 public: 3984 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3985 : X86TargetInfo(Triple, Opts) { 3986 DoubleAlign = LongLongAlign = 32; 3987 LongDoubleWidth = 96; 3988 LongDoubleAlign = 32; 3989 SuitableAlign = 128; 3990 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 3991 SizeType = UnsignedInt; 3992 PtrDiffType = SignedInt; 3993 IntPtrType = SignedInt; 3994 RegParmMax = 3; 3995 3996 // Use fpret for all types. 3997 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3998 (1 << TargetInfo::Double) | 3999 (1 << TargetInfo::LongDouble)); 4000 4001 // x86-32 has atomics up to 8 bytes 4002 // FIXME: Check that we actually have cmpxchg8b before setting 4003 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4004 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4005 } 4006 BuiltinVaListKind getBuiltinVaListKind() const override { 4007 return TargetInfo::CharPtrBuiltinVaList; 4008 } 4009 4010 int getEHDataRegisterNumber(unsigned RegNo) const override { 4011 if (RegNo == 0) return 0; 4012 if (RegNo == 1) return 2; 4013 return -1; 4014 } 4015 bool validateOperandSize(StringRef Constraint, 4016 unsigned Size) const override { 4017 switch (Constraint[0]) { 4018 default: break; 4019 case 'R': 4020 case 'q': 4021 case 'Q': 4022 case 'a': 4023 case 'b': 4024 case 'c': 4025 case 'd': 4026 case 'S': 4027 case 'D': 4028 return Size <= 32; 4029 case 'A': 4030 return Size <= 64; 4031 } 4032 4033 return X86TargetInfo::validateOperandSize(Constraint, Size); 4034 } 4035 }; 4036 4037 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4038 public: 4039 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4040 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4041 4042 unsigned getFloatEvalMethod() const override { 4043 unsigned Major, Minor, Micro; 4044 getTriple().getOSVersion(Major, Minor, Micro); 4045 // New NetBSD uses the default rounding mode. 4046 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4047 return X86_32TargetInfo::getFloatEvalMethod(); 4048 // NetBSD before 6.99.26 defaults to "double" rounding. 4049 return 1; 4050 } 4051 }; 4052 4053 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4054 public: 4055 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4056 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4057 SizeType = UnsignedLong; 4058 IntPtrType = SignedLong; 4059 PtrDiffType = SignedLong; 4060 } 4061 }; 4062 4063 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4064 public: 4065 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4066 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4067 SizeType = UnsignedLong; 4068 IntPtrType = SignedLong; 4069 PtrDiffType = SignedLong; 4070 } 4071 }; 4072 4073 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4074 public: 4075 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4076 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4077 LongDoubleWidth = 128; 4078 LongDoubleAlign = 128; 4079 SuitableAlign = 128; 4080 MaxVectorAlign = 256; 4081 // The watchOS simulator uses the builtin bool type for Objective-C. 4082 llvm::Triple T = llvm::Triple(Triple); 4083 if (T.isWatchOS()) 4084 UseSignedCharForObjCBool = false; 4085 SizeType = UnsignedLong; 4086 IntPtrType = SignedLong; 4087 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4088 HasAlignMac68kSupport = true; 4089 } 4090 4091 bool handleTargetFeatures(std::vector<std::string> &Features, 4092 DiagnosticsEngine &Diags) override { 4093 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4094 Diags)) 4095 return false; 4096 // We now know the features we have: we can decide how to align vectors. 4097 MaxVectorAlign = 4098 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4099 return true; 4100 } 4101 }; 4102 4103 // x86-32 Windows target 4104 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4105 public: 4106 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4107 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4108 WCharType = UnsignedShort; 4109 DoubleAlign = LongLongAlign = 64; 4110 bool IsWinCOFF = 4111 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4112 resetDataLayout(IsWinCOFF 4113 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4114 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4115 } 4116 void getTargetDefines(const LangOptions &Opts, 4117 MacroBuilder &Builder) const override { 4118 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4119 } 4120 }; 4121 4122 // x86-32 Windows Visual Studio target 4123 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4124 public: 4125 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4126 const TargetOptions &Opts) 4127 : WindowsX86_32TargetInfo(Triple, Opts) { 4128 LongDoubleWidth = LongDoubleAlign = 64; 4129 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4130 } 4131 void getTargetDefines(const LangOptions &Opts, 4132 MacroBuilder &Builder) const override { 4133 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4134 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4135 // The value of the following reflects processor type. 4136 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4137 // We lost the original triple, so we use the default. 4138 Builder.defineMacro("_M_IX86", "600"); 4139 } 4140 }; 4141 4142 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4143 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4144 // supports __declspec natively under -fms-extensions, but we define a no-op 4145 // __declspec macro anyway for pre-processor compatibility. 4146 if (Opts.MicrosoftExt) 4147 Builder.defineMacro("__declspec", "__declspec"); 4148 else 4149 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4150 4151 if (!Opts.MicrosoftExt) { 4152 // Provide macros for all the calling convention keywords. Provide both 4153 // single and double underscore prefixed variants. These are available on 4154 // x64 as well as x86, even though they have no effect. 4155 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4156 for (const char *CC : CCs) { 4157 std::string GCCSpelling = "__attribute__((__"; 4158 GCCSpelling += CC; 4159 GCCSpelling += "__))"; 4160 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4161 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4162 } 4163 } 4164 } 4165 4166 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4167 Builder.defineMacro("__MSVCRT__"); 4168 Builder.defineMacro("__MINGW32__"); 4169 addCygMingDefines(Opts, Builder); 4170 } 4171 4172 // x86-32 MinGW target 4173 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4174 public: 4175 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4176 : WindowsX86_32TargetInfo(Triple, Opts) {} 4177 void getTargetDefines(const LangOptions &Opts, 4178 MacroBuilder &Builder) const override { 4179 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4180 DefineStd(Builder, "WIN32", Opts); 4181 DefineStd(Builder, "WINNT", Opts); 4182 Builder.defineMacro("_X86_"); 4183 addMinGWDefines(Opts, Builder); 4184 } 4185 }; 4186 4187 // x86-32 Cygwin target 4188 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4189 public: 4190 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4191 : X86_32TargetInfo(Triple, Opts) { 4192 WCharType = UnsignedShort; 4193 DoubleAlign = LongLongAlign = 64; 4194 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4195 } 4196 void getTargetDefines(const LangOptions &Opts, 4197 MacroBuilder &Builder) const override { 4198 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4199 Builder.defineMacro("_X86_"); 4200 Builder.defineMacro("__CYGWIN__"); 4201 Builder.defineMacro("__CYGWIN32__"); 4202 addCygMingDefines(Opts, Builder); 4203 DefineStd(Builder, "unix", Opts); 4204 if (Opts.CPlusPlus) 4205 Builder.defineMacro("_GNU_SOURCE"); 4206 } 4207 }; 4208 4209 // x86-32 Haiku target 4210 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4211 public: 4212 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4213 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4214 } 4215 void getTargetDefines(const LangOptions &Opts, 4216 MacroBuilder &Builder) const override { 4217 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4218 Builder.defineMacro("__INTEL__"); 4219 } 4220 }; 4221 4222 // X86-32 MCU target 4223 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4224 public: 4225 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4226 : X86_32TargetInfo(Triple, Opts) { 4227 LongDoubleWidth = 64; 4228 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4229 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4230 WIntType = UnsignedInt; 4231 } 4232 4233 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4234 // On MCU we support only C calling convention. 4235 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4236 } 4237 4238 void getTargetDefines(const LangOptions &Opts, 4239 MacroBuilder &Builder) const override { 4240 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4241 Builder.defineMacro("__iamcu"); 4242 Builder.defineMacro("__iamcu__"); 4243 } 4244 4245 bool allowsLargerPreferedTypeAlignment() const override { 4246 return false; 4247 } 4248 }; 4249 4250 // RTEMS Target 4251 template<typename Target> 4252 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4253 protected: 4254 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4255 MacroBuilder &Builder) const override { 4256 // RTEMS defines; list based off of gcc output 4257 4258 Builder.defineMacro("__rtems__"); 4259 Builder.defineMacro("__ELF__"); 4260 } 4261 4262 public: 4263 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4264 : OSTargetInfo<Target>(Triple, Opts) { 4265 switch (Triple.getArch()) { 4266 default: 4267 case llvm::Triple::x86: 4268 // this->MCountName = ".mcount"; 4269 break; 4270 case llvm::Triple::mips: 4271 case llvm::Triple::mipsel: 4272 case llvm::Triple::ppc: 4273 case llvm::Triple::ppc64: 4274 case llvm::Triple::ppc64le: 4275 // this->MCountName = "_mcount"; 4276 break; 4277 case llvm::Triple::arm: 4278 // this->MCountName = "__mcount"; 4279 break; 4280 } 4281 } 4282 }; 4283 4284 // x86-32 RTEMS target 4285 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4286 public: 4287 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4288 : X86_32TargetInfo(Triple, Opts) { 4289 SizeType = UnsignedLong; 4290 IntPtrType = SignedLong; 4291 PtrDiffType = SignedLong; 4292 } 4293 void getTargetDefines(const LangOptions &Opts, 4294 MacroBuilder &Builder) const override { 4295 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4296 Builder.defineMacro("__INTEL__"); 4297 Builder.defineMacro("__rtems__"); 4298 } 4299 }; 4300 4301 // x86-64 generic target 4302 class X86_64TargetInfo : public X86TargetInfo { 4303 public: 4304 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4305 : X86TargetInfo(Triple, Opts) { 4306 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4307 bool IsWinCOFF = 4308 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4309 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4310 LongDoubleWidth = 128; 4311 LongDoubleAlign = 128; 4312 LargeArrayMinWidth = 128; 4313 LargeArrayAlign = 128; 4314 SuitableAlign = 128; 4315 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4316 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4317 IntPtrType = IsX32 ? SignedInt : SignedLong; 4318 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4319 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4320 RegParmMax = 6; 4321 4322 // Pointers are 32-bit in x32. 4323 resetDataLayout(IsX32 4324 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4325 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4326 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4327 4328 // Use fpret only for long double. 4329 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4330 4331 // Use fp2ret for _Complex long double. 4332 ComplexLongDoubleUsesFP2Ret = true; 4333 4334 // Make __builtin_ms_va_list available. 4335 HasBuiltinMSVaList = true; 4336 4337 // x86-64 has atomics up to 16 bytes. 4338 MaxAtomicPromoteWidth = 128; 4339 MaxAtomicInlineWidth = 128; 4340 } 4341 BuiltinVaListKind getBuiltinVaListKind() const override { 4342 return TargetInfo::X86_64ABIBuiltinVaList; 4343 } 4344 4345 int getEHDataRegisterNumber(unsigned RegNo) const override { 4346 if (RegNo == 0) return 0; 4347 if (RegNo == 1) return 1; 4348 return -1; 4349 } 4350 4351 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4352 switch (CC) { 4353 case CC_C: 4354 case CC_Swift: 4355 case CC_X86VectorCall: 4356 case CC_IntelOclBicc: 4357 case CC_X86_64Win64: 4358 case CC_PreserveMost: 4359 case CC_PreserveAll: 4360 return CCCR_OK; 4361 default: 4362 return CCCR_Warning; 4363 } 4364 } 4365 4366 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4367 return CC_C; 4368 } 4369 4370 // for x32 we need it here explicitly 4371 bool hasInt128Type() const override { return true; } 4372 unsigned getUnwindWordWidth() const override { return 64; } 4373 unsigned getRegisterWidth() const override { return 64; } 4374 4375 bool validateGlobalRegisterVariable(StringRef RegName, 4376 unsigned RegSize, 4377 bool &HasSizeMismatch) const override { 4378 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4379 // handle. 4380 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4381 // Check that the register size is 64-bit. 4382 HasSizeMismatch = RegSize != 64; 4383 return true; 4384 } 4385 4386 // Check if the register is a 32-bit register the backend can handle. 4387 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4388 HasSizeMismatch); 4389 } 4390 }; 4391 4392 // x86-64 Windows target 4393 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4394 public: 4395 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4396 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4397 WCharType = UnsignedShort; 4398 LongWidth = LongAlign = 32; 4399 DoubleAlign = LongLongAlign = 64; 4400 IntMaxType = SignedLongLong; 4401 Int64Type = SignedLongLong; 4402 SizeType = UnsignedLongLong; 4403 PtrDiffType = SignedLongLong; 4404 IntPtrType = SignedLongLong; 4405 } 4406 4407 void getTargetDefines(const LangOptions &Opts, 4408 MacroBuilder &Builder) const override { 4409 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4410 Builder.defineMacro("_WIN64"); 4411 } 4412 4413 BuiltinVaListKind getBuiltinVaListKind() const override { 4414 return TargetInfo::CharPtrBuiltinVaList; 4415 } 4416 4417 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4418 switch (CC) { 4419 case CC_X86StdCall: 4420 case CC_X86ThisCall: 4421 case CC_X86FastCall: 4422 return CCCR_Ignore; 4423 case CC_C: 4424 case CC_X86VectorCall: 4425 case CC_IntelOclBicc: 4426 case CC_X86_64SysV: 4427 return CCCR_OK; 4428 default: 4429 return CCCR_Warning; 4430 } 4431 } 4432 }; 4433 4434 // x86-64 Windows Visual Studio target 4435 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4436 public: 4437 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4438 const TargetOptions &Opts) 4439 : WindowsX86_64TargetInfo(Triple, Opts) { 4440 LongDoubleWidth = LongDoubleAlign = 64; 4441 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4442 } 4443 void getTargetDefines(const LangOptions &Opts, 4444 MacroBuilder &Builder) const override { 4445 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4446 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4447 Builder.defineMacro("_M_X64", "100"); 4448 Builder.defineMacro("_M_AMD64", "100"); 4449 } 4450 }; 4451 4452 // x86-64 MinGW target 4453 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4454 public: 4455 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4456 : WindowsX86_64TargetInfo(Triple, Opts) { 4457 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4458 // with x86 FP ops. Weird. 4459 LongDoubleWidth = LongDoubleAlign = 128; 4460 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4461 } 4462 4463 void getTargetDefines(const LangOptions &Opts, 4464 MacroBuilder &Builder) const override { 4465 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4466 DefineStd(Builder, "WIN64", Opts); 4467 Builder.defineMacro("__MINGW64__"); 4468 addMinGWDefines(Opts, Builder); 4469 4470 // GCC defines this macro when it is using __gxx_personality_seh0. 4471 if (!Opts.SjLjExceptions) 4472 Builder.defineMacro("__SEH__"); 4473 } 4474 }; 4475 4476 // x86-64 Cygwin target 4477 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4478 public: 4479 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4480 : X86_64TargetInfo(Triple, Opts) { 4481 TLSSupported = false; 4482 WCharType = UnsignedShort; 4483 } 4484 void getTargetDefines(const LangOptions &Opts, 4485 MacroBuilder &Builder) const override { 4486 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4487 Builder.defineMacro("__x86_64__"); 4488 Builder.defineMacro("__CYGWIN__"); 4489 Builder.defineMacro("__CYGWIN64__"); 4490 addCygMingDefines(Opts, Builder); 4491 DefineStd(Builder, "unix", Opts); 4492 if (Opts.CPlusPlus) 4493 Builder.defineMacro("_GNU_SOURCE"); 4494 4495 // GCC defines this macro when it is using __gxx_personality_seh0. 4496 if (!Opts.SjLjExceptions) 4497 Builder.defineMacro("__SEH__"); 4498 } 4499 }; 4500 4501 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4502 public: 4503 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4504 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4505 Int64Type = SignedLongLong; 4506 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4507 llvm::Triple T = llvm::Triple(Triple); 4508 if (T.isiOS()) 4509 UseSignedCharForObjCBool = false; 4510 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4511 } 4512 4513 bool handleTargetFeatures(std::vector<std::string> &Features, 4514 DiagnosticsEngine &Diags) override { 4515 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4516 Diags)) 4517 return false; 4518 // We now know the features we have: we can decide how to align vectors. 4519 MaxVectorAlign = 4520 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4521 return true; 4522 } 4523 }; 4524 4525 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4526 public: 4527 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4528 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4529 IntMaxType = SignedLongLong; 4530 Int64Type = SignedLongLong; 4531 } 4532 }; 4533 4534 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4535 public: 4536 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4537 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4538 IntMaxType = SignedLongLong; 4539 Int64Type = SignedLongLong; 4540 } 4541 }; 4542 4543 class ARMTargetInfo : public TargetInfo { 4544 // Possible FPU choices. 4545 enum FPUMode { 4546 VFP2FPU = (1 << 0), 4547 VFP3FPU = (1 << 1), 4548 VFP4FPU = (1 << 2), 4549 NeonFPU = (1 << 3), 4550 FPARMV8 = (1 << 4) 4551 }; 4552 4553 // Possible HWDiv features. 4554 enum HWDivMode { 4555 HWDivThumb = (1 << 0), 4556 HWDivARM = (1 << 1) 4557 }; 4558 4559 static bool FPUModeIsVFP(FPUMode Mode) { 4560 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4561 } 4562 4563 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4564 static const char * const GCCRegNames[]; 4565 4566 std::string ABI, CPU; 4567 4568 StringRef CPUProfile; 4569 StringRef CPUAttr; 4570 4571 enum { 4572 FP_Default, 4573 FP_VFP, 4574 FP_Neon 4575 } FPMath; 4576 4577 unsigned ArchISA; 4578 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4579 unsigned ArchProfile; 4580 unsigned ArchVersion; 4581 4582 unsigned FPU : 5; 4583 4584 unsigned IsAAPCS : 1; 4585 unsigned HWDiv : 2; 4586 4587 // Initialized via features. 4588 unsigned SoftFloat : 1; 4589 unsigned SoftFloatABI : 1; 4590 4591 unsigned CRC : 1; 4592 unsigned Crypto : 1; 4593 unsigned DSP : 1; 4594 unsigned Unaligned : 1; 4595 4596 enum { 4597 LDREX_B = (1 << 0), /// byte (8-bit) 4598 LDREX_H = (1 << 1), /// half (16-bit) 4599 LDREX_W = (1 << 2), /// word (32-bit) 4600 LDREX_D = (1 << 3), /// double (64-bit) 4601 }; 4602 4603 uint32_t LDREX; 4604 4605 // ACLE 6.5.1 Hardware floating point 4606 enum { 4607 HW_FP_HP = (1 << 1), /// half (16-bit) 4608 HW_FP_SP = (1 << 2), /// single (32-bit) 4609 HW_FP_DP = (1 << 3), /// double (64-bit) 4610 }; 4611 uint32_t HW_FP; 4612 4613 static const Builtin::Info BuiltinInfo[]; 4614 4615 void setABIAAPCS() { 4616 IsAAPCS = true; 4617 4618 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4619 const llvm::Triple &T = getTriple(); 4620 4621 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4622 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4623 T.getOS() == llvm::Triple::Bitrig) 4624 SizeType = UnsignedLong; 4625 else 4626 SizeType = UnsignedInt; 4627 4628 switch (T.getOS()) { 4629 case llvm::Triple::NetBSD: 4630 WCharType = SignedInt; 4631 break; 4632 case llvm::Triple::Win32: 4633 WCharType = UnsignedShort; 4634 break; 4635 case llvm::Triple::Linux: 4636 default: 4637 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4638 WCharType = UnsignedInt; 4639 break; 4640 } 4641 4642 UseBitFieldTypeAlignment = true; 4643 4644 ZeroLengthBitfieldBoundary = 0; 4645 4646 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4647 // so set preferred for small types to 32. 4648 if (T.isOSBinFormatMachO()) { 4649 resetDataLayout(BigEndian 4650 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4651 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4652 } else if (T.isOSWindows()) { 4653 assert(!BigEndian && "Windows on ARM does not support big endian"); 4654 resetDataLayout("e" 4655 "-m:w" 4656 "-p:32:32" 4657 "-i64:64" 4658 "-v128:64:128" 4659 "-a:0:32" 4660 "-n32" 4661 "-S64"); 4662 } else if (T.isOSNaCl()) { 4663 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4664 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4665 } else { 4666 resetDataLayout(BigEndian 4667 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4668 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4669 } 4670 4671 // FIXME: Enumerated types are variable width in straight AAPCS. 4672 } 4673 4674 void setABIAPCS(bool IsAAPCS16) { 4675 const llvm::Triple &T = getTriple(); 4676 4677 IsAAPCS = false; 4678 4679 if (IsAAPCS16) 4680 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4681 else 4682 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4683 4684 // size_t is unsigned int on FreeBSD. 4685 if (T.getOS() == llvm::Triple::FreeBSD) 4686 SizeType = UnsignedInt; 4687 else 4688 SizeType = UnsignedLong; 4689 4690 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4691 WCharType = SignedInt; 4692 4693 // Do not respect the alignment of bit-field types when laying out 4694 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4695 UseBitFieldTypeAlignment = false; 4696 4697 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4698 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4699 /// gcc. 4700 ZeroLengthBitfieldBoundary = 32; 4701 4702 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4703 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4704 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4705 } else if (T.isOSBinFormatMachO()) 4706 resetDataLayout( 4707 BigEndian 4708 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4709 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4710 else 4711 resetDataLayout( 4712 BigEndian 4713 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4714 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4715 4716 // FIXME: Override "preferred align" for double and long long. 4717 } 4718 4719 void setArchInfo() { 4720 StringRef ArchName = getTriple().getArchName(); 4721 4722 ArchISA = llvm::ARM::parseArchISA(ArchName); 4723 CPU = llvm::ARM::getDefaultCPU(ArchName); 4724 unsigned AK = llvm::ARM::parseArch(ArchName); 4725 if (AK != llvm::ARM::AK_INVALID) 4726 ArchKind = AK; 4727 setArchInfo(ArchKind); 4728 } 4729 4730 void setArchInfo(unsigned Kind) { 4731 StringRef SubArch; 4732 4733 // cache TargetParser info 4734 ArchKind = Kind; 4735 SubArch = llvm::ARM::getSubArch(ArchKind); 4736 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4737 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4738 4739 // cache CPU related strings 4740 CPUAttr = getCPUAttr(); 4741 CPUProfile = getCPUProfile(); 4742 } 4743 4744 void setAtomic() { 4745 // when triple does not specify a sub arch, 4746 // then we are not using inline atomics 4747 bool ShouldUseInlineAtomic = 4748 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4749 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4750 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4751 if (ArchProfile == llvm::ARM::PK_M) { 4752 MaxAtomicPromoteWidth = 32; 4753 if (ShouldUseInlineAtomic) 4754 MaxAtomicInlineWidth = 32; 4755 } 4756 else { 4757 MaxAtomicPromoteWidth = 64; 4758 if (ShouldUseInlineAtomic) 4759 MaxAtomicInlineWidth = 64; 4760 } 4761 } 4762 4763 bool isThumb() const { 4764 return (ArchISA == llvm::ARM::IK_THUMB); 4765 } 4766 4767 bool supportsThumb() const { 4768 return CPUAttr.count('T') || ArchVersion >= 6; 4769 } 4770 4771 bool supportsThumb2() const { 4772 return CPUAttr.equals("6T2") || 4773 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 4774 } 4775 4776 StringRef getCPUAttr() const { 4777 // For most sub-arches, the build attribute CPU name is enough. 4778 // For Cortex variants, it's slightly different. 4779 switch(ArchKind) { 4780 default: 4781 return llvm::ARM::getCPUAttr(ArchKind); 4782 case llvm::ARM::AK_ARMV6M: 4783 return "6M"; 4784 case llvm::ARM::AK_ARMV7S: 4785 return "7S"; 4786 case llvm::ARM::AK_ARMV7A: 4787 return "7A"; 4788 case llvm::ARM::AK_ARMV7R: 4789 return "7R"; 4790 case llvm::ARM::AK_ARMV7M: 4791 return "7M"; 4792 case llvm::ARM::AK_ARMV7EM: 4793 return "7EM"; 4794 case llvm::ARM::AK_ARMV8A: 4795 return "8A"; 4796 case llvm::ARM::AK_ARMV8_1A: 4797 return "8_1A"; 4798 case llvm::ARM::AK_ARMV8_2A: 4799 return "8_2A"; 4800 case llvm::ARM::AK_ARMV8MBaseline: 4801 return "8M_BASE"; 4802 case llvm::ARM::AK_ARMV8MMainline: 4803 return "8M_MAIN"; 4804 } 4805 } 4806 4807 StringRef getCPUProfile() const { 4808 switch(ArchProfile) { 4809 case llvm::ARM::PK_A: 4810 return "A"; 4811 case llvm::ARM::PK_R: 4812 return "R"; 4813 case llvm::ARM::PK_M: 4814 return "M"; 4815 default: 4816 return ""; 4817 } 4818 } 4819 4820 public: 4821 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 4822 bool IsBigEndian) 4823 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 4824 HW_FP(0) { 4825 BigEndian = IsBigEndian; 4826 4827 switch (getTriple().getOS()) { 4828 case llvm::Triple::NetBSD: 4829 PtrDiffType = SignedLong; 4830 break; 4831 default: 4832 PtrDiffType = SignedInt; 4833 break; 4834 } 4835 4836 // Cache arch related info. 4837 setArchInfo(); 4838 4839 // {} in inline assembly are neon specifiers, not assembly variant 4840 // specifiers. 4841 NoAsmVariants = true; 4842 4843 // FIXME: This duplicates code from the driver that sets the -target-abi 4844 // option - this code is used if -target-abi isn't passed and should 4845 // be unified in some way. 4846 if (Triple.isOSBinFormatMachO()) { 4847 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4848 // the frontend matches that. 4849 if (Triple.getEnvironment() == llvm::Triple::EABI || 4850 Triple.getOS() == llvm::Triple::UnknownOS || 4851 StringRef(CPU).startswith("cortex-m")) { 4852 setABI("aapcs"); 4853 } else if (Triple.isWatchABI()) { 4854 setABI("aapcs16"); 4855 } else { 4856 setABI("apcs-gnu"); 4857 } 4858 } else if (Triple.isOSWindows()) { 4859 // FIXME: this is invalid for WindowsCE 4860 setABI("aapcs"); 4861 } else { 4862 // Select the default based on the platform. 4863 switch (Triple.getEnvironment()) { 4864 case llvm::Triple::Android: 4865 case llvm::Triple::GNUEABI: 4866 case llvm::Triple::GNUEABIHF: 4867 setABI("aapcs-linux"); 4868 break; 4869 case llvm::Triple::EABIHF: 4870 case llvm::Triple::EABI: 4871 setABI("aapcs"); 4872 break; 4873 case llvm::Triple::GNU: 4874 setABI("apcs-gnu"); 4875 break; 4876 default: 4877 if (Triple.getOS() == llvm::Triple::NetBSD) 4878 setABI("apcs-gnu"); 4879 else 4880 setABI("aapcs"); 4881 break; 4882 } 4883 } 4884 4885 // ARM targets default to using the ARM C++ ABI. 4886 TheCXXABI.set(TargetCXXABI::GenericARM); 4887 4888 // ARM has atomics up to 8 bytes 4889 setAtomic(); 4890 4891 // Do force alignment of members that follow zero length bitfields. If 4892 // the alignment of the zero-length bitfield is greater than the member 4893 // that follows it, `bar', `bar' will be aligned as the type of the 4894 // zero length bitfield. 4895 UseZeroLengthBitfieldAlignment = true; 4896 4897 if (Triple.getOS() == llvm::Triple::Linux || 4898 Triple.getOS() == llvm::Triple::UnknownOS) 4899 this->MCountName = 4900 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 4901 } 4902 4903 StringRef getABI() const override { return ABI; } 4904 4905 bool setABI(const std::string &Name) override { 4906 ABI = Name; 4907 4908 // The defaults (above) are for AAPCS, check if we need to change them. 4909 // 4910 // FIXME: We need support for -meabi... we could just mangle it into the 4911 // name. 4912 if (Name == "apcs-gnu" || Name == "aapcs16") { 4913 setABIAPCS(Name == "aapcs16"); 4914 return true; 4915 } 4916 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4917 setABIAAPCS(); 4918 return true; 4919 } 4920 return false; 4921 } 4922 4923 // FIXME: This should be based on Arch attributes, not CPU names. 4924 bool 4925 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4926 StringRef CPU, 4927 const std::vector<std::string> &FeaturesVec) const override { 4928 4929 std::vector<const char*> TargetFeatures; 4930 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4931 4932 // get default FPU features 4933 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4934 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4935 4936 // get default Extension features 4937 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 4938 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4939 4940 for (const char *Feature : TargetFeatures) 4941 if (Feature[0] == '+') 4942 Features[Feature+1] = true; 4943 4944 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4945 } 4946 4947 bool handleTargetFeatures(std::vector<std::string> &Features, 4948 DiagnosticsEngine &Diags) override { 4949 FPU = 0; 4950 CRC = 0; 4951 Crypto = 0; 4952 DSP = 0; 4953 Unaligned = 1; 4954 SoftFloat = SoftFloatABI = false; 4955 HWDiv = 0; 4956 4957 // This does not diagnose illegal cases like having both 4958 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4959 uint32_t HW_FP_remove = 0; 4960 for (const auto &Feature : Features) { 4961 if (Feature == "+soft-float") { 4962 SoftFloat = true; 4963 } else if (Feature == "+soft-float-abi") { 4964 SoftFloatABI = true; 4965 } else if (Feature == "+vfp2") { 4966 FPU |= VFP2FPU; 4967 HW_FP |= HW_FP_SP | HW_FP_DP; 4968 } else if (Feature == "+vfp3") { 4969 FPU |= VFP3FPU; 4970 HW_FP |= HW_FP_SP | HW_FP_DP; 4971 } else if (Feature == "+vfp4") { 4972 FPU |= VFP4FPU; 4973 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4974 } else if (Feature == "+fp-armv8") { 4975 FPU |= FPARMV8; 4976 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4977 } else if (Feature == "+neon") { 4978 FPU |= NeonFPU; 4979 HW_FP |= HW_FP_SP | HW_FP_DP; 4980 } else if (Feature == "+hwdiv") { 4981 HWDiv |= HWDivThumb; 4982 } else if (Feature == "+hwdiv-arm") { 4983 HWDiv |= HWDivARM; 4984 } else if (Feature == "+crc") { 4985 CRC = 1; 4986 } else if (Feature == "+crypto") { 4987 Crypto = 1; 4988 } else if (Feature == "+dsp") { 4989 DSP = 1; 4990 } else if (Feature == "+fp-only-sp") { 4991 HW_FP_remove |= HW_FP_DP; 4992 } else if (Feature == "+strict-align") { 4993 Unaligned = 0; 4994 } else if (Feature == "+fp16") { 4995 HW_FP |= HW_FP_HP; 4996 } 4997 } 4998 HW_FP &= ~HW_FP_remove; 4999 5000 switch (ArchVersion) { 5001 case 6: 5002 if (ArchProfile == llvm::ARM::PK_M) 5003 LDREX = 0; 5004 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5005 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5006 else 5007 LDREX = LDREX_W; 5008 break; 5009 case 7: 5010 if (ArchProfile == llvm::ARM::PK_M) 5011 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5012 else 5013 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5014 break; 5015 case 8: 5016 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5017 } 5018 5019 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5020 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5021 return false; 5022 } 5023 5024 if (FPMath == FP_Neon) 5025 Features.push_back("+neonfp"); 5026 else if (FPMath == FP_VFP) 5027 Features.push_back("-neonfp"); 5028 5029 // Remove front-end specific options which the backend handles differently. 5030 auto Feature = 5031 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5032 if (Feature != Features.end()) 5033 Features.erase(Feature); 5034 5035 return true; 5036 } 5037 5038 bool hasFeature(StringRef Feature) const override { 5039 return llvm::StringSwitch<bool>(Feature) 5040 .Case("arm", true) 5041 .Case("aarch32", true) 5042 .Case("softfloat", SoftFloat) 5043 .Case("thumb", isThumb()) 5044 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5045 .Case("hwdiv", HWDiv & HWDivThumb) 5046 .Case("hwdiv-arm", HWDiv & HWDivARM) 5047 .Default(false); 5048 } 5049 5050 bool setCPU(const std::string &Name) override { 5051 if (Name != "generic") 5052 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5053 5054 if (ArchKind == llvm::ARM::AK_INVALID) 5055 return false; 5056 setAtomic(); 5057 CPU = Name; 5058 return true; 5059 } 5060 5061 bool setFPMath(StringRef Name) override; 5062 5063 void getTargetDefines(const LangOptions &Opts, 5064 MacroBuilder &Builder) const override { 5065 // Target identification. 5066 Builder.defineMacro("__arm"); 5067 Builder.defineMacro("__arm__"); 5068 // For bare-metal none-eabi. 5069 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5070 getTriple().getEnvironment() == llvm::Triple::EABI) 5071 Builder.defineMacro("__ELF__"); 5072 5073 // Target properties. 5074 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5075 5076 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5077 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5078 if (getTriple().isWatchABI()) 5079 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5080 5081 if (!CPUAttr.empty()) 5082 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5083 5084 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5085 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5086 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5087 5088 if (ArchVersion >= 8) { 5089 // ACLE 6.5.7 Crypto Extension 5090 if (Crypto) 5091 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5092 // ACLE 6.5.8 CRC32 Extension 5093 if (CRC) 5094 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5095 // ACLE 6.5.10 Numeric Maximum and Minimum 5096 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5097 // ACLE 6.5.9 Directed Rounding 5098 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5099 } 5100 5101 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5102 // is not defined for the M-profile. 5103 // NOTE that the default profile is assumed to be 'A' 5104 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5105 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5106 5107 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5108 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5109 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5110 // v7 and v8 architectures excluding v8-M Baseline. 5111 if (supportsThumb2()) 5112 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5113 else if (supportsThumb()) 5114 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5115 5116 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5117 // instruction set such as ARM or Thumb. 5118 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5119 5120 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5121 5122 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5123 if (!CPUProfile.empty()) 5124 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5125 5126 // ACLE 6.4.3 Unaligned access supported in hardware 5127 if (Unaligned) 5128 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5129 5130 // ACLE 6.4.4 LDREX/STREX 5131 if (LDREX) 5132 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5133 5134 // ACLE 6.4.5 CLZ 5135 if (ArchVersion == 5 || 5136 (ArchVersion == 6 && CPUProfile != "M") || 5137 ArchVersion > 6) 5138 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5139 5140 // ACLE 6.5.1 Hardware Floating Point 5141 if (HW_FP) 5142 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5143 5144 // ACLE predefines. 5145 Builder.defineMacro("__ARM_ACLE", "200"); 5146 5147 // FP16 support (we currently only support IEEE format). 5148 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5149 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5150 5151 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5152 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5153 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5154 5155 // Subtarget options. 5156 5157 // FIXME: It's more complicated than this and we don't really support 5158 // interworking. 5159 // Windows on ARM does not "support" interworking 5160 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5161 Builder.defineMacro("__THUMB_INTERWORK__"); 5162 5163 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5164 // Embedded targets on Darwin follow AAPCS, but not EABI. 5165 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5166 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5167 Builder.defineMacro("__ARM_EABI__"); 5168 Builder.defineMacro("__ARM_PCS", "1"); 5169 } 5170 5171 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5172 ABI == "aapcs16") 5173 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5174 5175 if (SoftFloat) 5176 Builder.defineMacro("__SOFTFP__"); 5177 5178 if (CPU == "xscale") 5179 Builder.defineMacro("__XSCALE__"); 5180 5181 if (isThumb()) { 5182 Builder.defineMacro("__THUMBEL__"); 5183 Builder.defineMacro("__thumb__"); 5184 if (supportsThumb2()) 5185 Builder.defineMacro("__thumb2__"); 5186 } 5187 5188 // ACLE 6.4.9 32-bit SIMD instructions 5189 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5190 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5191 5192 // ACLE 6.4.10 Hardware Integer Divide 5193 if (((HWDiv & HWDivThumb) && isThumb()) || 5194 ((HWDiv & HWDivARM) && !isThumb())) { 5195 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5196 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5197 } 5198 5199 // Note, this is always on in gcc, even though it doesn't make sense. 5200 Builder.defineMacro("__APCS_32__"); 5201 5202 if (FPUModeIsVFP((FPUMode) FPU)) { 5203 Builder.defineMacro("__VFP_FP__"); 5204 if (FPU & VFP2FPU) 5205 Builder.defineMacro("__ARM_VFPV2__"); 5206 if (FPU & VFP3FPU) 5207 Builder.defineMacro("__ARM_VFPV3__"); 5208 if (FPU & VFP4FPU) 5209 Builder.defineMacro("__ARM_VFPV4__"); 5210 } 5211 5212 // This only gets set when Neon instructions are actually available, unlike 5213 // the VFP define, hence the soft float and arch check. This is subtly 5214 // different from gcc, we follow the intent which was that it should be set 5215 // when Neon instructions are actually available. 5216 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5217 Builder.defineMacro("__ARM_NEON", "1"); 5218 Builder.defineMacro("__ARM_NEON__"); 5219 // current AArch32 NEON implementations do not support double-precision 5220 // floating-point even when it is present in VFP. 5221 Builder.defineMacro("__ARM_NEON_FP", 5222 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5223 } 5224 5225 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5226 Opts.ShortWChar ? "2" : "4"); 5227 5228 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5229 Opts.ShortEnums ? "1" : "4"); 5230 5231 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5232 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5233 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5234 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5235 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5236 } 5237 5238 // ACLE 6.4.7 DSP instructions 5239 if (DSP) { 5240 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5241 } 5242 5243 // ACLE 6.4.8 Saturation instructions 5244 bool SAT = false; 5245 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5246 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5247 SAT = true; 5248 } 5249 5250 // ACLE 6.4.6 Q (saturation) flag 5251 if (DSP || SAT) 5252 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5253 5254 if (Opts.UnsafeFPMath) 5255 Builder.defineMacro("__ARM_FP_FAST", "1"); 5256 5257 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5258 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5259 } 5260 5261 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5262 return llvm::makeArrayRef(BuiltinInfo, 5263 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5264 } 5265 bool isCLZForZeroUndef() const override { return false; } 5266 BuiltinVaListKind getBuiltinVaListKind() const override { 5267 return IsAAPCS 5268 ? AAPCSABIBuiltinVaList 5269 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5270 : TargetInfo::VoidPtrBuiltinVaList); 5271 } 5272 ArrayRef<const char *> getGCCRegNames() const override; 5273 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5274 bool validateAsmConstraint(const char *&Name, 5275 TargetInfo::ConstraintInfo &Info) const override { 5276 switch (*Name) { 5277 default: break; 5278 case 'l': // r0-r7 5279 case 'h': // r8-r15 5280 case 't': // VFP Floating point register single precision 5281 case 'w': // VFP Floating point register double precision 5282 Info.setAllowsRegister(); 5283 return true; 5284 case 'I': 5285 case 'J': 5286 case 'K': 5287 case 'L': 5288 case 'M': 5289 // FIXME 5290 return true; 5291 case 'Q': // A memory address that is a single base register. 5292 Info.setAllowsMemory(); 5293 return true; 5294 case 'U': // a memory reference... 5295 switch (Name[1]) { 5296 case 'q': // ...ARMV4 ldrsb 5297 case 'v': // ...VFP load/store (reg+constant offset) 5298 case 'y': // ...iWMMXt load/store 5299 case 't': // address valid for load/store opaque types wider 5300 // than 128-bits 5301 case 'n': // valid address for Neon doubleword vector load/store 5302 case 'm': // valid address for Neon element and structure load/store 5303 case 's': // valid address for non-offset loads/stores of quad-word 5304 // values in four ARM registers 5305 Info.setAllowsMemory(); 5306 Name++; 5307 return true; 5308 } 5309 } 5310 return false; 5311 } 5312 std::string convertConstraint(const char *&Constraint) const override { 5313 std::string R; 5314 switch (*Constraint) { 5315 case 'U': // Two-character constraint; add "^" hint for later parsing. 5316 R = std::string("^") + std::string(Constraint, 2); 5317 Constraint++; 5318 break; 5319 case 'p': // 'p' should be translated to 'r' by default. 5320 R = std::string("r"); 5321 break; 5322 default: 5323 return std::string(1, *Constraint); 5324 } 5325 return R; 5326 } 5327 bool 5328 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5329 std::string &SuggestedModifier) const override { 5330 bool isOutput = (Constraint[0] == '='); 5331 bool isInOut = (Constraint[0] == '+'); 5332 5333 // Strip off constraint modifiers. 5334 while (Constraint[0] == '=' || 5335 Constraint[0] == '+' || 5336 Constraint[0] == '&') 5337 Constraint = Constraint.substr(1); 5338 5339 switch (Constraint[0]) { 5340 default: break; 5341 case 'r': { 5342 switch (Modifier) { 5343 default: 5344 return (isInOut || isOutput || Size <= 64); 5345 case 'q': 5346 // A register of size 32 cannot fit a vector type. 5347 return false; 5348 } 5349 } 5350 } 5351 5352 return true; 5353 } 5354 const char *getClobbers() const override { 5355 // FIXME: Is this really right? 5356 return ""; 5357 } 5358 5359 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5360 switch (CC) { 5361 case CC_AAPCS: 5362 case CC_AAPCS_VFP: 5363 case CC_Swift: 5364 return CCCR_OK; 5365 default: 5366 return CCCR_Warning; 5367 } 5368 } 5369 5370 int getEHDataRegisterNumber(unsigned RegNo) const override { 5371 if (RegNo == 0) return 0; 5372 if (RegNo == 1) return 1; 5373 return -1; 5374 } 5375 5376 bool hasSjLjLowering() const override { 5377 return true; 5378 } 5379 }; 5380 5381 bool ARMTargetInfo::setFPMath(StringRef Name) { 5382 if (Name == "neon") { 5383 FPMath = FP_Neon; 5384 return true; 5385 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5386 Name == "vfp4") { 5387 FPMath = FP_VFP; 5388 return true; 5389 } 5390 return false; 5391 } 5392 5393 const char * const ARMTargetInfo::GCCRegNames[] = { 5394 // Integer registers 5395 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5396 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5397 5398 // Float registers 5399 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5400 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5401 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5402 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5403 5404 // Double registers 5405 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5406 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5407 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5408 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5409 5410 // Quad registers 5411 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5412 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5413 }; 5414 5415 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5416 return llvm::makeArrayRef(GCCRegNames); 5417 } 5418 5419 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5420 { { "a1" }, "r0" }, 5421 { { "a2" }, "r1" }, 5422 { { "a3" }, "r2" }, 5423 { { "a4" }, "r3" }, 5424 { { "v1" }, "r4" }, 5425 { { "v2" }, "r5" }, 5426 { { "v3" }, "r6" }, 5427 { { "v4" }, "r7" }, 5428 { { "v5" }, "r8" }, 5429 { { "v6", "rfp" }, "r9" }, 5430 { { "sl" }, "r10" }, 5431 { { "fp" }, "r11" }, 5432 { { "ip" }, "r12" }, 5433 { { "r13" }, "sp" }, 5434 { { "r14" }, "lr" }, 5435 { { "r15" }, "pc" }, 5436 // The S, D and Q registers overlap, but aren't really aliases; we 5437 // don't want to substitute one of these for a different-sized one. 5438 }; 5439 5440 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5441 return llvm::makeArrayRef(GCCRegAliases); 5442 } 5443 5444 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5445 #define BUILTIN(ID, TYPE, ATTRS) \ 5446 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5447 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5448 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5449 #include "clang/Basic/BuiltinsNEON.def" 5450 5451 #define BUILTIN(ID, TYPE, ATTRS) \ 5452 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5453 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5454 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5455 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5456 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5457 #include "clang/Basic/BuiltinsARM.def" 5458 }; 5459 5460 class ARMleTargetInfo : public ARMTargetInfo { 5461 public: 5462 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5463 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/false) {} 5464 void getTargetDefines(const LangOptions &Opts, 5465 MacroBuilder &Builder) const override { 5466 Builder.defineMacro("__ARMEL__"); 5467 ARMTargetInfo::getTargetDefines(Opts, Builder); 5468 } 5469 }; 5470 5471 class ARMbeTargetInfo : public ARMTargetInfo { 5472 public: 5473 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5474 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/true) {} 5475 void getTargetDefines(const LangOptions &Opts, 5476 MacroBuilder &Builder) const override { 5477 Builder.defineMacro("__ARMEB__"); 5478 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5479 ARMTargetInfo::getTargetDefines(Opts, Builder); 5480 } 5481 }; 5482 5483 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5484 const llvm::Triple Triple; 5485 public: 5486 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5487 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5488 WCharType = UnsignedShort; 5489 SizeType = UnsignedInt; 5490 } 5491 void getVisualStudioDefines(const LangOptions &Opts, 5492 MacroBuilder &Builder) const { 5493 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5494 5495 // FIXME: this is invalid for WindowsCE 5496 Builder.defineMacro("_M_ARM_NT", "1"); 5497 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5498 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5499 5500 assert((Triple.getArch() == llvm::Triple::arm || 5501 Triple.getArch() == llvm::Triple::thumb) && 5502 "invalid architecture for Windows ARM target info"); 5503 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5504 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5505 5506 // TODO map the complete set of values 5507 // 31: VFPv3 40: VFPv4 5508 Builder.defineMacro("_M_ARM_FP", "31"); 5509 } 5510 BuiltinVaListKind getBuiltinVaListKind() const override { 5511 return TargetInfo::CharPtrBuiltinVaList; 5512 } 5513 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5514 switch (CC) { 5515 case CC_X86StdCall: 5516 case CC_X86ThisCall: 5517 case CC_X86FastCall: 5518 case CC_X86VectorCall: 5519 return CCCR_Ignore; 5520 case CC_C: 5521 return CCCR_OK; 5522 default: 5523 return CCCR_Warning; 5524 } 5525 } 5526 }; 5527 5528 // Windows ARM + Itanium C++ ABI Target 5529 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5530 public: 5531 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5532 const TargetOptions &Opts) 5533 : WindowsARMTargetInfo(Triple, Opts) { 5534 TheCXXABI.set(TargetCXXABI::GenericARM); 5535 } 5536 5537 void getTargetDefines(const LangOptions &Opts, 5538 MacroBuilder &Builder) const override { 5539 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5540 5541 if (Opts.MSVCCompat) 5542 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5543 } 5544 }; 5545 5546 // Windows ARM, MS (C++) ABI 5547 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5548 public: 5549 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5550 const TargetOptions &Opts) 5551 : WindowsARMTargetInfo(Triple, Opts) { 5552 TheCXXABI.set(TargetCXXABI::Microsoft); 5553 } 5554 5555 void getTargetDefines(const LangOptions &Opts, 5556 MacroBuilder &Builder) const override { 5557 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5558 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5559 } 5560 }; 5561 5562 // ARM MinGW target 5563 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5564 public: 5565 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5566 : WindowsARMTargetInfo(Triple, Opts) { 5567 TheCXXABI.set(TargetCXXABI::GenericARM); 5568 } 5569 5570 void getTargetDefines(const LangOptions &Opts, 5571 MacroBuilder &Builder) const override { 5572 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5573 DefineStd(Builder, "WIN32", Opts); 5574 DefineStd(Builder, "WINNT", Opts); 5575 Builder.defineMacro("_ARM_"); 5576 addMinGWDefines(Opts, Builder); 5577 } 5578 }; 5579 5580 // ARM Cygwin target 5581 class CygwinARMTargetInfo : public ARMleTargetInfo { 5582 public: 5583 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5584 : ARMleTargetInfo(Triple, Opts) { 5585 TLSSupported = false; 5586 WCharType = UnsignedShort; 5587 DoubleAlign = LongLongAlign = 64; 5588 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5589 } 5590 void getTargetDefines(const LangOptions &Opts, 5591 MacroBuilder &Builder) const override { 5592 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5593 Builder.defineMacro("_ARM_"); 5594 Builder.defineMacro("__CYGWIN__"); 5595 Builder.defineMacro("__CYGWIN32__"); 5596 DefineStd(Builder, "unix", Opts); 5597 if (Opts.CPlusPlus) 5598 Builder.defineMacro("_GNU_SOURCE"); 5599 } 5600 }; 5601 5602 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 5603 protected: 5604 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5605 MacroBuilder &Builder) const override { 5606 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5607 } 5608 5609 public: 5610 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5611 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 5612 HasAlignMac68kSupport = true; 5613 // iOS always has 64-bit atomic instructions. 5614 // FIXME: This should be based off of the target features in 5615 // ARMleTargetInfo. 5616 MaxAtomicInlineWidth = 64; 5617 5618 if (Triple.isWatchABI()) { 5619 // Darwin on iOS uses a variant of the ARM C++ ABI. 5620 TheCXXABI.set(TargetCXXABI::WatchOS); 5621 5622 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5623 // size_t is long, it's a bit weird for it to be int. 5624 PtrDiffType = SignedLong; 5625 5626 // BOOL should be a real boolean on the new ABI 5627 UseSignedCharForObjCBool = false; 5628 } else 5629 TheCXXABI.set(TargetCXXABI::iOS); 5630 } 5631 }; 5632 5633 class AArch64TargetInfo : public TargetInfo { 5634 virtual void setDataLayout() = 0; 5635 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5636 static const char *const GCCRegNames[]; 5637 5638 enum FPUModeEnum { 5639 FPUMode, 5640 NeonMode 5641 }; 5642 5643 unsigned FPU; 5644 unsigned CRC; 5645 unsigned Crypto; 5646 unsigned Unaligned; 5647 unsigned V8_1A; 5648 5649 static const Builtin::Info BuiltinInfo[]; 5650 5651 std::string ABI; 5652 5653 public: 5654 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5655 : TargetInfo(Triple), ABI("aapcs") { 5656 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5657 WCharType = SignedInt; 5658 5659 // NetBSD apparently prefers consistency across ARM targets to consistency 5660 // across 64-bit targets. 5661 Int64Type = SignedLongLong; 5662 IntMaxType = SignedLongLong; 5663 } else { 5664 WCharType = UnsignedInt; 5665 Int64Type = SignedLong; 5666 IntMaxType = SignedLong; 5667 } 5668 5669 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5670 MaxVectorAlign = 128; 5671 MaxAtomicInlineWidth = 128; 5672 MaxAtomicPromoteWidth = 128; 5673 5674 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5675 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5676 5677 // {} in inline assembly are neon specifiers, not assembly variant 5678 // specifiers. 5679 NoAsmVariants = true; 5680 5681 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5682 // contributes to the alignment of the containing aggregate in the same way 5683 // a plain (non bit-field) member of that type would, without exception for 5684 // zero-sized or anonymous bit-fields." 5685 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5686 UseZeroLengthBitfieldAlignment = true; 5687 5688 // AArch64 targets default to using the ARM C++ ABI. 5689 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5690 5691 if (Triple.getOS() == llvm::Triple::Linux || 5692 Triple.getOS() == llvm::Triple::UnknownOS) 5693 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 5694 } 5695 5696 StringRef getABI() const override { return ABI; } 5697 bool setABI(const std::string &Name) override { 5698 if (Name != "aapcs" && Name != "darwinpcs") 5699 return false; 5700 5701 ABI = Name; 5702 return true; 5703 } 5704 5705 bool setCPU(const std::string &Name) override { 5706 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5707 .Case("generic", true) 5708 .Cases("cortex-a53", "cortex-a57", "cortex-a72", 5709 "cortex-a35", "exynos-m1", true) 5710 .Case("cortex-a73", true) 5711 .Case("cyclone", true) 5712 .Case("kryo", true) 5713 .Default(false); 5714 return CPUKnown; 5715 } 5716 5717 void getTargetDefines(const LangOptions &Opts, 5718 MacroBuilder &Builder) const override { 5719 // Target identification. 5720 Builder.defineMacro("__aarch64__"); 5721 5722 // Target properties. 5723 Builder.defineMacro("_LP64"); 5724 Builder.defineMacro("__LP64__"); 5725 5726 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5727 Builder.defineMacro("__ARM_ACLE", "200"); 5728 Builder.defineMacro("__ARM_ARCH", "8"); 5729 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5730 5731 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5732 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5733 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5734 5735 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5736 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5737 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5738 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5739 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5740 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5741 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5742 5743 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5744 5745 // 0xe implies support for half, single and double precision operations. 5746 Builder.defineMacro("__ARM_FP", "0xE"); 5747 5748 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5749 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5750 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5751 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5752 5753 if (Opts.UnsafeFPMath) 5754 Builder.defineMacro("__ARM_FP_FAST", "1"); 5755 5756 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5757 5758 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5759 Opts.ShortEnums ? "1" : "4"); 5760 5761 if (FPU == NeonMode) { 5762 Builder.defineMacro("__ARM_NEON", "1"); 5763 // 64-bit NEON supports half, single and double precision operations. 5764 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5765 } 5766 5767 if (CRC) 5768 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5769 5770 if (Crypto) 5771 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5772 5773 if (Unaligned) 5774 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5775 5776 if (V8_1A) 5777 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5778 5779 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5780 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5781 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5782 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5783 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5784 } 5785 5786 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5787 return llvm::makeArrayRef(BuiltinInfo, 5788 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5789 } 5790 5791 bool hasFeature(StringRef Feature) const override { 5792 return Feature == "aarch64" || 5793 Feature == "arm64" || 5794 Feature == "arm" || 5795 (Feature == "neon" && FPU == NeonMode); 5796 } 5797 5798 bool handleTargetFeatures(std::vector<std::string> &Features, 5799 DiagnosticsEngine &Diags) override { 5800 FPU = FPUMode; 5801 CRC = 0; 5802 Crypto = 0; 5803 Unaligned = 1; 5804 V8_1A = 0; 5805 5806 for (const auto &Feature : Features) { 5807 if (Feature == "+neon") 5808 FPU = NeonMode; 5809 if (Feature == "+crc") 5810 CRC = 1; 5811 if (Feature == "+crypto") 5812 Crypto = 1; 5813 if (Feature == "+strict-align") 5814 Unaligned = 0; 5815 if (Feature == "+v8.1a") 5816 V8_1A = 1; 5817 } 5818 5819 setDataLayout(); 5820 5821 return true; 5822 } 5823 5824 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5825 switch (CC) { 5826 case CC_C: 5827 case CC_Swift: 5828 case CC_PreserveMost: 5829 case CC_PreserveAll: 5830 return CCCR_OK; 5831 default: 5832 return CCCR_Warning; 5833 } 5834 } 5835 5836 bool isCLZForZeroUndef() const override { return false; } 5837 5838 BuiltinVaListKind getBuiltinVaListKind() const override { 5839 return TargetInfo::AArch64ABIBuiltinVaList; 5840 } 5841 5842 ArrayRef<const char *> getGCCRegNames() const override; 5843 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5844 5845 bool validateAsmConstraint(const char *&Name, 5846 TargetInfo::ConstraintInfo &Info) const override { 5847 switch (*Name) { 5848 default: 5849 return false; 5850 case 'w': // Floating point and SIMD registers (V0-V31) 5851 Info.setAllowsRegister(); 5852 return true; 5853 case 'I': // Constant that can be used with an ADD instruction 5854 case 'J': // Constant that can be used with a SUB instruction 5855 case 'K': // Constant that can be used with a 32-bit logical instruction 5856 case 'L': // Constant that can be used with a 64-bit logical instruction 5857 case 'M': // Constant that can be used as a 32-bit MOV immediate 5858 case 'N': // Constant that can be used as a 64-bit MOV immediate 5859 case 'Y': // Floating point constant zero 5860 case 'Z': // Integer constant zero 5861 return true; 5862 case 'Q': // A memory reference with base register and no offset 5863 Info.setAllowsMemory(); 5864 return true; 5865 case 'S': // A symbolic address 5866 Info.setAllowsRegister(); 5867 return true; 5868 case 'U': 5869 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5870 // Utf: A memory address suitable for ldp/stp in TF mode. 5871 // Usa: An absolute symbolic address. 5872 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5873 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5874 case 'z': // Zero register, wzr or xzr 5875 Info.setAllowsRegister(); 5876 return true; 5877 case 'x': // Floating point and SIMD registers (V0-V15) 5878 Info.setAllowsRegister(); 5879 return true; 5880 } 5881 return false; 5882 } 5883 5884 bool 5885 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5886 std::string &SuggestedModifier) const override { 5887 // Strip off constraint modifiers. 5888 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5889 Constraint = Constraint.substr(1); 5890 5891 switch (Constraint[0]) { 5892 default: 5893 return true; 5894 case 'z': 5895 case 'r': { 5896 switch (Modifier) { 5897 case 'x': 5898 case 'w': 5899 // For now assume that the person knows what they're 5900 // doing with the modifier. 5901 return true; 5902 default: 5903 // By default an 'r' constraint will be in the 'x' 5904 // registers. 5905 if (Size == 64) 5906 return true; 5907 5908 SuggestedModifier = "w"; 5909 return false; 5910 } 5911 } 5912 } 5913 } 5914 5915 const char *getClobbers() const override { return ""; } 5916 5917 int getEHDataRegisterNumber(unsigned RegNo) const override { 5918 if (RegNo == 0) 5919 return 0; 5920 if (RegNo == 1) 5921 return 1; 5922 return -1; 5923 } 5924 }; 5925 5926 const char *const AArch64TargetInfo::GCCRegNames[] = { 5927 // 32-bit Integer registers 5928 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5929 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5930 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5931 5932 // 64-bit Integer registers 5933 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5934 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5935 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5936 5937 // 32-bit floating point regsisters 5938 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5939 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5940 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5941 5942 // 64-bit floating point regsisters 5943 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5944 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5945 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5946 5947 // Vector registers 5948 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5949 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5950 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5951 }; 5952 5953 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 5954 return llvm::makeArrayRef(GCCRegNames); 5955 } 5956 5957 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5958 { { "w31" }, "wsp" }, 5959 { { "x29" }, "fp" }, 5960 { { "x30" }, "lr" }, 5961 { { "x31" }, "sp" }, 5962 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5963 // don't want to substitute one of these for a different-sized one. 5964 }; 5965 5966 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 5967 return llvm::makeArrayRef(GCCRegAliases); 5968 } 5969 5970 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5971 #define BUILTIN(ID, TYPE, ATTRS) \ 5972 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5973 #include "clang/Basic/BuiltinsNEON.def" 5974 5975 #define BUILTIN(ID, TYPE, ATTRS) \ 5976 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5977 #include "clang/Basic/BuiltinsAArch64.def" 5978 }; 5979 5980 class AArch64leTargetInfo : public AArch64TargetInfo { 5981 void setDataLayout() override { 5982 if (getTriple().isOSBinFormatMachO()) 5983 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 5984 else 5985 resetDataLayout("e-m:e-i64:64-i128:128-n32:64-S128"); 5986 } 5987 5988 public: 5989 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5990 : AArch64TargetInfo(Triple, Opts) { 5991 BigEndian = false; 5992 } 5993 void getTargetDefines(const LangOptions &Opts, 5994 MacroBuilder &Builder) const override { 5995 Builder.defineMacro("__AARCH64EL__"); 5996 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5997 } 5998 }; 5999 6000 class AArch64beTargetInfo : public AArch64TargetInfo { 6001 void setDataLayout() override { 6002 assert(!getTriple().isOSBinFormatMachO()); 6003 resetDataLayout("E-m:e-i64:64-i128:128-n32:64-S128"); 6004 } 6005 6006 public: 6007 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6008 : AArch64TargetInfo(Triple, Opts) {} 6009 void getTargetDefines(const LangOptions &Opts, 6010 MacroBuilder &Builder) const override { 6011 Builder.defineMacro("__AARCH64EB__"); 6012 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6013 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6014 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6015 } 6016 }; 6017 6018 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6019 protected: 6020 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6021 MacroBuilder &Builder) const override { 6022 Builder.defineMacro("__AARCH64_SIMD__"); 6023 Builder.defineMacro("__ARM64_ARCH_8__"); 6024 Builder.defineMacro("__ARM_NEON__"); 6025 Builder.defineMacro("__LITTLE_ENDIAN__"); 6026 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6027 Builder.defineMacro("__arm64", "1"); 6028 Builder.defineMacro("__arm64__", "1"); 6029 6030 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6031 } 6032 6033 public: 6034 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6035 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6036 Int64Type = SignedLongLong; 6037 WCharType = SignedInt; 6038 UseSignedCharForObjCBool = false; 6039 6040 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6041 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6042 6043 TheCXXABI.set(TargetCXXABI::iOS64); 6044 } 6045 6046 BuiltinVaListKind getBuiltinVaListKind() const override { 6047 return TargetInfo::CharPtrBuiltinVaList; 6048 } 6049 }; 6050 6051 // Hexagon abstract base class 6052 class HexagonTargetInfo : public TargetInfo { 6053 static const Builtin::Info BuiltinInfo[]; 6054 static const char * const GCCRegNames[]; 6055 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6056 std::string CPU; 6057 bool HasHVX, HasHVXDouble; 6058 6059 public: 6060 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6061 : TargetInfo(Triple) { 6062 BigEndian = false; 6063 // Specify the vector alignment explicitly. For v512x1, the calculated 6064 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6065 // the required minimum of 64 bytes. 6066 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6067 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6068 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6069 SizeType = UnsignedInt; 6070 PtrDiffType = SignedInt; 6071 IntPtrType = SignedInt; 6072 6073 // {} in inline assembly are packet specifiers, not assembly variant 6074 // specifiers. 6075 NoAsmVariants = true; 6076 6077 LargeArrayMinWidth = 64; 6078 LargeArrayAlign = 64; 6079 UseBitFieldTypeAlignment = true; 6080 ZeroLengthBitfieldBoundary = 32; 6081 HasHVX = HasHVXDouble = false; 6082 } 6083 6084 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6085 return llvm::makeArrayRef(BuiltinInfo, 6086 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6087 } 6088 6089 bool validateAsmConstraint(const char *&Name, 6090 TargetInfo::ConstraintInfo &Info) const override { 6091 switch (*Name) { 6092 case 'v': 6093 case 'q': 6094 if (HasHVX) { 6095 Info.setAllowsRegister(); 6096 return true; 6097 } 6098 break; 6099 case 's': 6100 // Relocatable constant. 6101 return true; 6102 } 6103 return false; 6104 } 6105 6106 void getTargetDefines(const LangOptions &Opts, 6107 MacroBuilder &Builder) const override; 6108 6109 bool isCLZForZeroUndef() const override { return false; } 6110 6111 bool hasFeature(StringRef Feature) const override { 6112 return llvm::StringSwitch<bool>(Feature) 6113 .Case("hexagon", true) 6114 .Case("hvx", HasHVX) 6115 .Case("hvx-double", HasHVXDouble) 6116 .Default(false); 6117 } 6118 6119 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6120 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6121 const override; 6122 6123 bool handleTargetFeatures(std::vector<std::string> &Features, 6124 DiagnosticsEngine &Diags) override; 6125 6126 BuiltinVaListKind getBuiltinVaListKind() const override { 6127 return TargetInfo::CharPtrBuiltinVaList; 6128 } 6129 ArrayRef<const char *> getGCCRegNames() const override; 6130 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6131 const char *getClobbers() const override { 6132 return ""; 6133 } 6134 6135 static const char *getHexagonCPUSuffix(StringRef Name) { 6136 return llvm::StringSwitch<const char*>(Name) 6137 .Case("hexagonv4", "4") 6138 .Case("hexagonv5", "5") 6139 .Case("hexagonv55", "55") 6140 .Case("hexagonv60", "60") 6141 .Default(nullptr); 6142 } 6143 6144 bool setCPU(const std::string &Name) override { 6145 if (!getHexagonCPUSuffix(Name)) 6146 return false; 6147 CPU = Name; 6148 return true; 6149 } 6150 6151 int getEHDataRegisterNumber(unsigned RegNo) const override { 6152 return RegNo < 2 ? RegNo : -1; 6153 } 6154 }; 6155 6156 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6157 MacroBuilder &Builder) const { 6158 Builder.defineMacro("__qdsp6__", "1"); 6159 Builder.defineMacro("__hexagon__", "1"); 6160 6161 if (CPU == "hexagonv4") { 6162 Builder.defineMacro("__HEXAGON_V4__"); 6163 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6164 if (Opts.HexagonQdsp6Compat) { 6165 Builder.defineMacro("__QDSP6_V4__"); 6166 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6167 } 6168 } else if (CPU == "hexagonv5") { 6169 Builder.defineMacro("__HEXAGON_V5__"); 6170 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6171 if(Opts.HexagonQdsp6Compat) { 6172 Builder.defineMacro("__QDSP6_V5__"); 6173 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6174 } 6175 } else if (CPU == "hexagonv55") { 6176 Builder.defineMacro("__HEXAGON_V55__"); 6177 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6178 Builder.defineMacro("__QDSP6_V55__"); 6179 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6180 } else if (CPU == "hexagonv60") { 6181 Builder.defineMacro("__HEXAGON_V60__"); 6182 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6183 Builder.defineMacro("__QDSP6_V60__"); 6184 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6185 } 6186 6187 if (hasFeature("hvx")) { 6188 Builder.defineMacro("__HVX__"); 6189 if (hasFeature("hvx-double")) 6190 Builder.defineMacro("__HVXDBL__"); 6191 } 6192 } 6193 6194 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6195 DiagnosticsEngine &Diags) { 6196 for (auto &F : Features) { 6197 if (F == "+hvx") 6198 HasHVX = true; 6199 else if (F == "-hvx") 6200 HasHVX = HasHVXDouble = false; 6201 else if (F == "+hvx-double") 6202 HasHVX = HasHVXDouble = true; 6203 else if (F == "-hvx-double") 6204 HasHVXDouble = false; 6205 } 6206 return true; 6207 } 6208 6209 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6210 DiagnosticsEngine &Diags, StringRef CPU, 6211 const std::vector<std::string> &FeaturesVec) const { 6212 // Default for v60: -hvx, -hvx-double. 6213 Features["hvx"] = false; 6214 Features["hvx-double"] = false; 6215 6216 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6217 } 6218 6219 6220 const char *const HexagonTargetInfo::GCCRegNames[] = { 6221 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6222 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6223 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6224 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6225 "p0", "p1", "p2", "p3", 6226 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6227 }; 6228 6229 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6230 return llvm::makeArrayRef(GCCRegNames); 6231 } 6232 6233 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6234 { { "sp" }, "r29" }, 6235 { { "fp" }, "r30" }, 6236 { { "lr" }, "r31" }, 6237 }; 6238 6239 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6240 return llvm::makeArrayRef(GCCRegAliases); 6241 } 6242 6243 6244 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6245 #define BUILTIN(ID, TYPE, ATTRS) \ 6246 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6247 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6248 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6249 #include "clang/Basic/BuiltinsHexagon.def" 6250 }; 6251 6252 class LanaiTargetInfo : public TargetInfo { 6253 // Class for Lanai (32-bit). 6254 // The CPU profiles supported by the Lanai backend 6255 enum CPUKind { 6256 CK_NONE, 6257 CK_V11, 6258 } CPU; 6259 6260 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6261 static const char *const GCCRegNames[]; 6262 6263 public: 6264 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6265 : TargetInfo(Triple) { 6266 // Description string has to be kept in sync with backend. 6267 resetDataLayout("E" // Big endian 6268 "-m:e" // ELF name manging 6269 "-p:32:32" // 32 bit pointers, 32 bit aligned 6270 "-i64:64" // 64 bit integers, 64 bit aligned 6271 "-a:0:32" // 32 bit alignment of objects of aggregate type 6272 "-n32" // 32 bit native integer width 6273 "-S64" // 64 bit natural stack alignment 6274 ); 6275 6276 // Setting RegParmMax equal to what mregparm was set to in the old 6277 // toolchain 6278 RegParmMax = 4; 6279 6280 // Set the default CPU to V11 6281 CPU = CK_V11; 6282 6283 // Temporary approach to make everything at least word-aligned and allow for 6284 // safely casting between pointers with different alignment requirements. 6285 // TODO: Remove this when there are no more cast align warnings on the 6286 // firmware. 6287 MinGlobalAlign = 32; 6288 } 6289 6290 void getTargetDefines(const LangOptions &Opts, 6291 MacroBuilder &Builder) const override { 6292 // Define __lanai__ when building for target lanai. 6293 Builder.defineMacro("__lanai__"); 6294 6295 // Set define for the CPU specified. 6296 switch (CPU) { 6297 case CK_V11: 6298 Builder.defineMacro("__LANAI_V11__"); 6299 break; 6300 case CK_NONE: 6301 llvm_unreachable("Unhandled target CPU"); 6302 } 6303 } 6304 6305 bool setCPU(const std::string &Name) override { 6306 CPU = llvm::StringSwitch<CPUKind>(Name) 6307 .Case("v11", CK_V11) 6308 .Default(CK_NONE); 6309 6310 return CPU != CK_NONE; 6311 } 6312 6313 bool hasFeature(StringRef Feature) const override { 6314 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6315 } 6316 6317 ArrayRef<const char *> getGCCRegNames() const override; 6318 6319 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6320 6321 BuiltinVaListKind getBuiltinVaListKind() const override { 6322 return TargetInfo::VoidPtrBuiltinVaList; 6323 } 6324 6325 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6326 6327 bool validateAsmConstraint(const char *&Name, 6328 TargetInfo::ConstraintInfo &info) const override { 6329 return false; 6330 } 6331 6332 const char *getClobbers() const override { return ""; } 6333 }; 6334 6335 const char *const LanaiTargetInfo::GCCRegNames[] = { 6336 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6337 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6338 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6339 6340 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6341 return llvm::makeArrayRef(GCCRegNames); 6342 } 6343 6344 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6345 {{"pc"}, "r2"}, 6346 {{"sp"}, "r4"}, 6347 {{"fp"}, "r5"}, 6348 {{"rv"}, "r8"}, 6349 {{"rr1"}, "r10"}, 6350 {{"rr2"}, "r11"}, 6351 {{"rca"}, "r15"}, 6352 }; 6353 6354 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6355 return llvm::makeArrayRef(GCCRegAliases); 6356 } 6357 6358 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6359 class SparcTargetInfo : public TargetInfo { 6360 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6361 static const char * const GCCRegNames[]; 6362 bool SoftFloat; 6363 public: 6364 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6365 : TargetInfo(Triple), SoftFloat(false) {} 6366 6367 int getEHDataRegisterNumber(unsigned RegNo) const override { 6368 if (RegNo == 0) return 24; 6369 if (RegNo == 1) return 25; 6370 return -1; 6371 } 6372 6373 bool handleTargetFeatures(std::vector<std::string> &Features, 6374 DiagnosticsEngine &Diags) override { 6375 // Check if software floating point is enabled 6376 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6377 if (Feature != Features.end()) { 6378 SoftFloat = true; 6379 } 6380 return true; 6381 } 6382 void getTargetDefines(const LangOptions &Opts, 6383 MacroBuilder &Builder) const override { 6384 DefineStd(Builder, "sparc", Opts); 6385 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6386 6387 if (SoftFloat) 6388 Builder.defineMacro("SOFT_FLOAT", "1"); 6389 } 6390 6391 bool hasFeature(StringRef Feature) const override { 6392 return llvm::StringSwitch<bool>(Feature) 6393 .Case("softfloat", SoftFloat) 6394 .Case("sparc", true) 6395 .Default(false); 6396 } 6397 6398 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6399 // FIXME: Implement! 6400 return None; 6401 } 6402 BuiltinVaListKind getBuiltinVaListKind() const override { 6403 return TargetInfo::VoidPtrBuiltinVaList; 6404 } 6405 ArrayRef<const char *> getGCCRegNames() const override; 6406 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6407 bool validateAsmConstraint(const char *&Name, 6408 TargetInfo::ConstraintInfo &info) const override { 6409 // FIXME: Implement! 6410 switch (*Name) { 6411 case 'I': // Signed 13-bit constant 6412 case 'J': // Zero 6413 case 'K': // 32-bit constant with the low 12 bits clear 6414 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6415 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6416 case 'N': // Same as 'K' but zext (required for SIMode) 6417 case 'O': // The constant 4096 6418 return true; 6419 } 6420 return false; 6421 } 6422 const char *getClobbers() const override { 6423 // FIXME: Implement! 6424 return ""; 6425 } 6426 6427 // No Sparc V7 for now, the backend doesn't support it anyway. 6428 enum CPUKind { 6429 CK_GENERIC, 6430 CK_V8, 6431 CK_SUPERSPARC, 6432 CK_SPARCLITE, 6433 CK_F934, 6434 CK_HYPERSPARC, 6435 CK_SPARCLITE86X, 6436 CK_SPARCLET, 6437 CK_TSC701, 6438 CK_V9, 6439 CK_ULTRASPARC, 6440 CK_ULTRASPARC3, 6441 CK_NIAGARA, 6442 CK_NIAGARA2, 6443 CK_NIAGARA3, 6444 CK_NIAGARA4, 6445 CK_MYRIAD2_1, 6446 CK_MYRIAD2_2 6447 } CPU = CK_GENERIC; 6448 6449 enum CPUGeneration { 6450 CG_V8, 6451 CG_V9, 6452 }; 6453 6454 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6455 switch (Kind) { 6456 case CK_GENERIC: 6457 case CK_V8: 6458 case CK_SUPERSPARC: 6459 case CK_SPARCLITE: 6460 case CK_F934: 6461 case CK_HYPERSPARC: 6462 case CK_SPARCLITE86X: 6463 case CK_SPARCLET: 6464 case CK_TSC701: 6465 case CK_MYRIAD2_1: 6466 case CK_MYRIAD2_2: 6467 return CG_V8; 6468 case CK_V9: 6469 case CK_ULTRASPARC: 6470 case CK_ULTRASPARC3: 6471 case CK_NIAGARA: 6472 case CK_NIAGARA2: 6473 case CK_NIAGARA3: 6474 case CK_NIAGARA4: 6475 return CG_V9; 6476 } 6477 llvm_unreachable("Unexpected CPU kind"); 6478 } 6479 6480 CPUKind getCPUKind(StringRef Name) const { 6481 return llvm::StringSwitch<CPUKind>(Name) 6482 .Case("v8", CK_V8) 6483 .Case("supersparc", CK_SUPERSPARC) 6484 .Case("sparclite", CK_SPARCLITE) 6485 .Case("f934", CK_F934) 6486 .Case("hypersparc", CK_HYPERSPARC) 6487 .Case("sparclite86x", CK_SPARCLITE86X) 6488 .Case("sparclet", CK_SPARCLET) 6489 .Case("tsc701", CK_TSC701) 6490 .Case("v9", CK_V9) 6491 .Case("ultrasparc", CK_ULTRASPARC) 6492 .Case("ultrasparc3", CK_ULTRASPARC3) 6493 .Case("niagara", CK_NIAGARA) 6494 .Case("niagara2", CK_NIAGARA2) 6495 .Case("niagara3", CK_NIAGARA3) 6496 .Case("niagara4", CK_NIAGARA4) 6497 .Case("myriad2", CK_MYRIAD2_1) 6498 .Case("myriad2.1", CK_MYRIAD2_1) 6499 .Case("myriad2.2", CK_MYRIAD2_2) 6500 .Default(CK_GENERIC); 6501 } 6502 6503 bool setCPU(const std::string &Name) override { 6504 CPU = getCPUKind(Name); 6505 return CPU != CK_GENERIC; 6506 } 6507 }; 6508 6509 const char * const SparcTargetInfo::GCCRegNames[] = { 6510 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6511 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6512 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6513 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6514 }; 6515 6516 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6517 return llvm::makeArrayRef(GCCRegNames); 6518 } 6519 6520 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6521 { { "g0" }, "r0" }, 6522 { { "g1" }, "r1" }, 6523 { { "g2" }, "r2" }, 6524 { { "g3" }, "r3" }, 6525 { { "g4" }, "r4" }, 6526 { { "g5" }, "r5" }, 6527 { { "g6" }, "r6" }, 6528 { { "g7" }, "r7" }, 6529 { { "o0" }, "r8" }, 6530 { { "o1" }, "r9" }, 6531 { { "o2" }, "r10" }, 6532 { { "o3" }, "r11" }, 6533 { { "o4" }, "r12" }, 6534 { { "o5" }, "r13" }, 6535 { { "o6", "sp" }, "r14" }, 6536 { { "o7" }, "r15" }, 6537 { { "l0" }, "r16" }, 6538 { { "l1" }, "r17" }, 6539 { { "l2" }, "r18" }, 6540 { { "l3" }, "r19" }, 6541 { { "l4" }, "r20" }, 6542 { { "l5" }, "r21" }, 6543 { { "l6" }, "r22" }, 6544 { { "l7" }, "r23" }, 6545 { { "i0" }, "r24" }, 6546 { { "i1" }, "r25" }, 6547 { { "i2" }, "r26" }, 6548 { { "i3" }, "r27" }, 6549 { { "i4" }, "r28" }, 6550 { { "i5" }, "r29" }, 6551 { { "i6", "fp" }, "r30" }, 6552 { { "i7" }, "r31" }, 6553 }; 6554 6555 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6556 return llvm::makeArrayRef(GCCRegAliases); 6557 } 6558 6559 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6560 class SparcV8TargetInfo : public SparcTargetInfo { 6561 public: 6562 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6563 : SparcTargetInfo(Triple, Opts) { 6564 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6565 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6566 switch (getTriple().getOS()) { 6567 default: 6568 SizeType = UnsignedInt; 6569 IntPtrType = SignedInt; 6570 PtrDiffType = SignedInt; 6571 break; 6572 case llvm::Triple::NetBSD: 6573 case llvm::Triple::OpenBSD: 6574 SizeType = UnsignedLong; 6575 IntPtrType = SignedLong; 6576 PtrDiffType = SignedLong; 6577 break; 6578 } 6579 } 6580 6581 void getTargetDefines(const LangOptions &Opts, 6582 MacroBuilder &Builder) const override { 6583 SparcTargetInfo::getTargetDefines(Opts, Builder); 6584 switch (getCPUGeneration(CPU)) { 6585 case CG_V8: 6586 Builder.defineMacro("__sparcv8"); 6587 if (getTriple().getOS() != llvm::Triple::Solaris) 6588 Builder.defineMacro("__sparcv8__"); 6589 break; 6590 case CG_V9: 6591 Builder.defineMacro("__sparcv9"); 6592 if (getTriple().getOS() != llvm::Triple::Solaris) { 6593 Builder.defineMacro("__sparcv9__"); 6594 Builder.defineMacro("__sparc_v9__"); 6595 } 6596 break; 6597 } 6598 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6599 switch (CPU) { 6600 case CK_MYRIAD2_1: 6601 Builder.defineMacro("__myriad2", "1"); 6602 Builder.defineMacro("__myriad2__", "1"); 6603 break; 6604 case CK_MYRIAD2_2: 6605 Builder.defineMacro("__myriad2", "2"); 6606 Builder.defineMacro("__myriad2__", "2"); 6607 break; 6608 default: 6609 break; 6610 } 6611 } 6612 } 6613 6614 bool hasSjLjLowering() const override { 6615 return true; 6616 } 6617 }; 6618 6619 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6620 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6621 public: 6622 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6623 : SparcV8TargetInfo(Triple, Opts) { 6624 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6625 BigEndian = false; 6626 } 6627 }; 6628 6629 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6630 class SparcV9TargetInfo : public SparcTargetInfo { 6631 public: 6632 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6633 : SparcTargetInfo(Triple, Opts) { 6634 // FIXME: Support Sparc quad-precision long double? 6635 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6636 // This is an LP64 platform. 6637 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6638 6639 // OpenBSD uses long long for int64_t and intmax_t. 6640 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6641 IntMaxType = SignedLongLong; 6642 else 6643 IntMaxType = SignedLong; 6644 Int64Type = IntMaxType; 6645 6646 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6647 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6648 LongDoubleWidth = 128; 6649 LongDoubleAlign = 128; 6650 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6651 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6652 } 6653 6654 void getTargetDefines(const LangOptions &Opts, 6655 MacroBuilder &Builder) const override { 6656 SparcTargetInfo::getTargetDefines(Opts, Builder); 6657 Builder.defineMacro("__sparcv9"); 6658 Builder.defineMacro("__arch64__"); 6659 // Solaris doesn't need these variants, but the BSDs do. 6660 if (getTriple().getOS() != llvm::Triple::Solaris) { 6661 Builder.defineMacro("__sparc64__"); 6662 Builder.defineMacro("__sparc_v9__"); 6663 Builder.defineMacro("__sparcv9__"); 6664 } 6665 } 6666 6667 bool setCPU(const std::string &Name) override { 6668 if (!SparcTargetInfo::setCPU(Name)) 6669 return false; 6670 return getCPUGeneration(CPU) == CG_V9; 6671 } 6672 }; 6673 6674 class SystemZTargetInfo : public TargetInfo { 6675 static const Builtin::Info BuiltinInfo[]; 6676 static const char *const GCCRegNames[]; 6677 std::string CPU; 6678 bool HasTransactionalExecution; 6679 bool HasVector; 6680 6681 public: 6682 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6683 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6684 HasVector(false) { 6685 IntMaxType = SignedLong; 6686 Int64Type = SignedLong; 6687 TLSSupported = true; 6688 IntWidth = IntAlign = 32; 6689 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6690 PointerWidth = PointerAlign = 64; 6691 LongDoubleWidth = 128; 6692 LongDoubleAlign = 64; 6693 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6694 DefaultAlignForAttributeAligned = 64; 6695 MinGlobalAlign = 16; 6696 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 6697 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6698 } 6699 void getTargetDefines(const LangOptions &Opts, 6700 MacroBuilder &Builder) const override { 6701 Builder.defineMacro("__s390__"); 6702 Builder.defineMacro("__s390x__"); 6703 Builder.defineMacro("__zarch__"); 6704 Builder.defineMacro("__LONG_DOUBLE_128__"); 6705 6706 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6707 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6708 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6709 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6710 6711 if (HasTransactionalExecution) 6712 Builder.defineMacro("__HTM__"); 6713 if (Opts.ZVector) 6714 Builder.defineMacro("__VEC__", "10301"); 6715 } 6716 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6717 return llvm::makeArrayRef(BuiltinInfo, 6718 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6719 } 6720 6721 ArrayRef<const char *> getGCCRegNames() const override; 6722 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6723 // No aliases. 6724 return None; 6725 } 6726 bool validateAsmConstraint(const char *&Name, 6727 TargetInfo::ConstraintInfo &info) const override; 6728 const char *getClobbers() const override { 6729 // FIXME: Is this really right? 6730 return ""; 6731 } 6732 BuiltinVaListKind getBuiltinVaListKind() const override { 6733 return TargetInfo::SystemZBuiltinVaList; 6734 } 6735 bool setCPU(const std::string &Name) override { 6736 CPU = Name; 6737 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6738 .Case("z10", true) 6739 .Case("z196", true) 6740 .Case("zEC12", true) 6741 .Case("z13", true) 6742 .Default(false); 6743 6744 return CPUKnown; 6745 } 6746 bool 6747 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6748 StringRef CPU, 6749 const std::vector<std::string> &FeaturesVec) const override { 6750 if (CPU == "zEC12") 6751 Features["transactional-execution"] = true; 6752 if (CPU == "z13") { 6753 Features["transactional-execution"] = true; 6754 Features["vector"] = true; 6755 } 6756 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6757 } 6758 6759 bool handleTargetFeatures(std::vector<std::string> &Features, 6760 DiagnosticsEngine &Diags) override { 6761 HasTransactionalExecution = false; 6762 for (const auto &Feature : Features) { 6763 if (Feature == "+transactional-execution") 6764 HasTransactionalExecution = true; 6765 else if (Feature == "+vector") 6766 HasVector = true; 6767 } 6768 // If we use the vector ABI, vector types are 64-bit aligned. 6769 if (HasVector) { 6770 MaxVectorAlign = 64; 6771 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6772 "-v128:64-a:8:16-n32:64"); 6773 } 6774 return true; 6775 } 6776 6777 bool hasFeature(StringRef Feature) const override { 6778 return llvm::StringSwitch<bool>(Feature) 6779 .Case("systemz", true) 6780 .Case("htm", HasTransactionalExecution) 6781 .Case("vx", HasVector) 6782 .Default(false); 6783 } 6784 6785 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6786 switch (CC) { 6787 case CC_C: 6788 case CC_Swift: 6789 return CCCR_OK; 6790 default: 6791 return CCCR_Warning; 6792 } 6793 } 6794 6795 StringRef getABI() const override { 6796 if (HasVector) 6797 return "vector"; 6798 return ""; 6799 } 6800 6801 bool useFloat128ManglingForLongDouble() const override { 6802 return true; 6803 } 6804 }; 6805 6806 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6807 #define BUILTIN(ID, TYPE, ATTRS) \ 6808 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6809 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 6810 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 6811 #include "clang/Basic/BuiltinsSystemZ.def" 6812 }; 6813 6814 const char *const SystemZTargetInfo::GCCRegNames[] = { 6815 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6816 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6817 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6818 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6819 }; 6820 6821 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6822 return llvm::makeArrayRef(GCCRegNames); 6823 } 6824 6825 bool SystemZTargetInfo:: 6826 validateAsmConstraint(const char *&Name, 6827 TargetInfo::ConstraintInfo &Info) const { 6828 switch (*Name) { 6829 default: 6830 return false; 6831 6832 case 'a': // Address register 6833 case 'd': // Data register (equivalent to 'r') 6834 case 'f': // Floating-point register 6835 Info.setAllowsRegister(); 6836 return true; 6837 6838 case 'I': // Unsigned 8-bit constant 6839 case 'J': // Unsigned 12-bit constant 6840 case 'K': // Signed 16-bit constant 6841 case 'L': // Signed 20-bit displacement (on all targets we support) 6842 case 'M': // 0x7fffffff 6843 return true; 6844 6845 case 'Q': // Memory with base and unsigned 12-bit displacement 6846 case 'R': // Likewise, plus an index 6847 case 'S': // Memory with base and signed 20-bit displacement 6848 case 'T': // Likewise, plus an index 6849 Info.setAllowsMemory(); 6850 return true; 6851 } 6852 } 6853 6854 class MSP430TargetInfo : public TargetInfo { 6855 static const char *const GCCRegNames[]; 6856 6857 public: 6858 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6859 : TargetInfo(Triple) { 6860 BigEndian = false; 6861 TLSSupported = false; 6862 IntWidth = 16; 6863 IntAlign = 16; 6864 LongWidth = 32; 6865 LongLongWidth = 64; 6866 LongAlign = LongLongAlign = 16; 6867 PointerWidth = 16; 6868 PointerAlign = 16; 6869 SuitableAlign = 16; 6870 SizeType = UnsignedInt; 6871 IntMaxType = SignedLongLong; 6872 IntPtrType = SignedInt; 6873 PtrDiffType = SignedInt; 6874 SigAtomicType = SignedLong; 6875 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 6876 } 6877 void getTargetDefines(const LangOptions &Opts, 6878 MacroBuilder &Builder) const override { 6879 Builder.defineMacro("MSP430"); 6880 Builder.defineMacro("__MSP430__"); 6881 // FIXME: defines for different 'flavours' of MCU 6882 } 6883 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6884 // FIXME: Implement. 6885 return None; 6886 } 6887 bool hasFeature(StringRef Feature) const override { 6888 return Feature == "msp430"; 6889 } 6890 ArrayRef<const char *> getGCCRegNames() const override; 6891 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6892 // No aliases. 6893 return None; 6894 } 6895 bool validateAsmConstraint(const char *&Name, 6896 TargetInfo::ConstraintInfo &info) const override { 6897 // FIXME: implement 6898 switch (*Name) { 6899 case 'K': // the constant 1 6900 case 'L': // constant -1^20 .. 1^19 6901 case 'M': // constant 1-4: 6902 return true; 6903 } 6904 // No target constraints for now. 6905 return false; 6906 } 6907 const char *getClobbers() const override { 6908 // FIXME: Is this really right? 6909 return ""; 6910 } 6911 BuiltinVaListKind getBuiltinVaListKind() const override { 6912 // FIXME: implement 6913 return TargetInfo::CharPtrBuiltinVaList; 6914 } 6915 }; 6916 6917 const char *const MSP430TargetInfo::GCCRegNames[] = { 6918 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6919 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6920 6921 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 6922 return llvm::makeArrayRef(GCCRegNames); 6923 } 6924 6925 // LLVM and Clang cannot be used directly to output native binaries for 6926 // target, but is used to compile C code to llvm bitcode with correct 6927 // type and alignment information. 6928 // 6929 // TCE uses the llvm bitcode as input and uses it for generating customized 6930 // target processor and program binary. TCE co-design environment is 6931 // publicly available in http://tce.cs.tut.fi 6932 6933 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6934 3, // opencl_global 6935 4, // opencl_local 6936 5, // opencl_constant 6937 // FIXME: generic has to be added to the target 6938 0, // opencl_generic 6939 0, // cuda_device 6940 0, // cuda_constant 6941 0 // cuda_shared 6942 }; 6943 6944 class TCETargetInfo : public TargetInfo { 6945 public: 6946 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6947 : TargetInfo(Triple) { 6948 TLSSupported = false; 6949 IntWidth = 32; 6950 LongWidth = LongLongWidth = 32; 6951 PointerWidth = 32; 6952 IntAlign = 32; 6953 LongAlign = LongLongAlign = 32; 6954 PointerAlign = 32; 6955 SuitableAlign = 32; 6956 SizeType = UnsignedInt; 6957 IntMaxType = SignedLong; 6958 IntPtrType = SignedInt; 6959 PtrDiffType = SignedInt; 6960 FloatWidth = 32; 6961 FloatAlign = 32; 6962 DoubleWidth = 32; 6963 DoubleAlign = 32; 6964 LongDoubleWidth = 32; 6965 LongDoubleAlign = 32; 6966 FloatFormat = &llvm::APFloat::IEEEsingle; 6967 DoubleFormat = &llvm::APFloat::IEEEsingle; 6968 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6969 resetDataLayout("E-p:32:32-i8:8:32-i16:16:32-i64:32" 6970 "-f64:32-v64:32-v128:32-a:0:32-n32"); 6971 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6972 UseAddrSpaceMapMangling = true; 6973 } 6974 6975 void getTargetDefines(const LangOptions &Opts, 6976 MacroBuilder &Builder) const override { 6977 DefineStd(Builder, "tce", Opts); 6978 Builder.defineMacro("__TCE__"); 6979 Builder.defineMacro("__TCE_V1__"); 6980 } 6981 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 6982 6983 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6984 const char *getClobbers() const override { return ""; } 6985 BuiltinVaListKind getBuiltinVaListKind() const override { 6986 return TargetInfo::VoidPtrBuiltinVaList; 6987 } 6988 ArrayRef<const char *> getGCCRegNames() const override { return None; } 6989 bool validateAsmConstraint(const char *&Name, 6990 TargetInfo::ConstraintInfo &info) const override { 6991 return true; 6992 } 6993 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6994 return None; 6995 } 6996 }; 6997 6998 class BPFTargetInfo : public TargetInfo { 6999 public: 7000 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7001 : TargetInfo(Triple) { 7002 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7003 SizeType = UnsignedLong; 7004 PtrDiffType = SignedLong; 7005 IntPtrType = SignedLong; 7006 IntMaxType = SignedLong; 7007 Int64Type = SignedLong; 7008 RegParmMax = 5; 7009 if (Triple.getArch() == llvm::Triple::bpfeb) { 7010 BigEndian = true; 7011 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7012 } else { 7013 BigEndian = false; 7014 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7015 } 7016 MaxAtomicPromoteWidth = 64; 7017 MaxAtomicInlineWidth = 64; 7018 TLSSupported = false; 7019 } 7020 void getTargetDefines(const LangOptions &Opts, 7021 MacroBuilder &Builder) const override { 7022 DefineStd(Builder, "bpf", Opts); 7023 Builder.defineMacro("__BPF__"); 7024 } 7025 bool hasFeature(StringRef Feature) const override { 7026 return Feature == "bpf"; 7027 } 7028 7029 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7030 const char *getClobbers() const override { 7031 return ""; 7032 } 7033 BuiltinVaListKind getBuiltinVaListKind() const override { 7034 return TargetInfo::VoidPtrBuiltinVaList; 7035 } 7036 ArrayRef<const char *> getGCCRegNames() const override { 7037 return None; 7038 } 7039 bool validateAsmConstraint(const char *&Name, 7040 TargetInfo::ConstraintInfo &info) const override { 7041 return true; 7042 } 7043 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7044 return None; 7045 } 7046 }; 7047 7048 class MipsTargetInfo : public TargetInfo { 7049 void setDataLayout() { 7050 StringRef Layout; 7051 7052 if (ABI == "o32") 7053 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7054 else if (ABI == "n32") 7055 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7056 else if (ABI == "n64") 7057 Layout = "m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7058 else 7059 llvm_unreachable("Invalid ABI"); 7060 7061 if (BigEndian) 7062 resetDataLayout(("E-" + Layout).str()); 7063 else 7064 resetDataLayout(("e-" + Layout).str()); 7065 } 7066 7067 7068 static const Builtin::Info BuiltinInfo[]; 7069 std::string CPU; 7070 bool IsMips16; 7071 bool IsMicromips; 7072 bool IsNan2008; 7073 bool IsSingleFloat; 7074 enum MipsFloatABI { 7075 HardFloat, SoftFloat 7076 } FloatABI; 7077 enum DspRevEnum { 7078 NoDSP, DSP1, DSP2 7079 } DspRev; 7080 bool HasMSA; 7081 7082 protected: 7083 bool HasFP64; 7084 std::string ABI; 7085 7086 public: 7087 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7088 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7089 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 7090 DspRev(NoDSP), HasMSA(false), HasFP64(false) { 7091 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7092 BigEndian = getTriple().getArch() == llvm::Triple::mips || 7093 getTriple().getArch() == llvm::Triple::mips64; 7094 7095 setABI((getTriple().getArch() == llvm::Triple::mips || 7096 getTriple().getArch() == llvm::Triple::mipsel) 7097 ? "o32" 7098 : "n64"); 7099 7100 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7101 } 7102 7103 bool isNaN2008Default() const { 7104 return CPU == "mips32r6" || CPU == "mips64r6"; 7105 } 7106 7107 bool isFP64Default() const { 7108 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7109 } 7110 7111 bool isNan2008() const override { 7112 return IsNan2008; 7113 } 7114 7115 StringRef getABI() const override { return ABI; } 7116 bool setABI(const std::string &Name) override { 7117 // FIXME: The Arch component on the triple actually has no bearing on 7118 // whether the ABI is valid or not. It's features of the CPU that 7119 // matters and the size of the GPR's in particular. 7120 // However, we can't allow O32 on 64-bit processors just yet because 7121 // the backend still checks the Arch component instead of the ABI in 7122 // a few places. 7123 if (getTriple().getArch() == llvm::Triple::mips || 7124 getTriple().getArch() == llvm::Triple::mipsel) { 7125 if (Name == "o32") { 7126 setO32ABITypes(); 7127 ABI = Name; 7128 return true; 7129 } 7130 } 7131 if (getTriple().getArch() == llvm::Triple::mips64 || 7132 getTriple().getArch() == llvm::Triple::mips64el) { 7133 if (Name == "n32") { 7134 setN32ABITypes(); 7135 ABI = Name; 7136 return true; 7137 } 7138 if (Name == "n64") { 7139 setN64ABITypes(); 7140 ABI = Name; 7141 return true; 7142 } 7143 } 7144 return false; 7145 } 7146 7147 void setO32ABITypes() { 7148 Int64Type = SignedLongLong; 7149 IntMaxType = Int64Type; 7150 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7151 LongDoubleWidth = LongDoubleAlign = 64; 7152 LongWidth = LongAlign = 32; 7153 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7154 PointerWidth = PointerAlign = 32; 7155 PtrDiffType = SignedInt; 7156 SizeType = UnsignedInt; 7157 SuitableAlign = 64; 7158 } 7159 7160 void setN32N64ABITypes() { 7161 LongDoubleWidth = LongDoubleAlign = 128; 7162 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7163 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7164 LongDoubleWidth = LongDoubleAlign = 64; 7165 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7166 } 7167 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7168 SuitableAlign = 128; 7169 } 7170 7171 void setN64ABITypes() { 7172 setN32N64ABITypes(); 7173 Int64Type = SignedLong; 7174 IntMaxType = Int64Type; 7175 LongWidth = LongAlign = 64; 7176 PointerWidth = PointerAlign = 64; 7177 PtrDiffType = SignedLong; 7178 SizeType = UnsignedLong; 7179 } 7180 7181 void setN32ABITypes() { 7182 setN32N64ABITypes(); 7183 Int64Type = SignedLongLong; 7184 IntMaxType = Int64Type; 7185 LongWidth = LongAlign = 32; 7186 PointerWidth = PointerAlign = 32; 7187 PtrDiffType = SignedInt; 7188 SizeType = UnsignedInt; 7189 } 7190 7191 bool setCPU(const std::string &Name) override { 7192 bool GPR64Required = ABI == "n32" || ABI == "n64"; 7193 CPU = Name; 7194 return llvm::StringSwitch<bool>(Name) 7195 .Case("mips1", !GPR64Required) 7196 .Case("mips2", !GPR64Required) 7197 .Case("mips3", true) 7198 .Case("mips4", true) 7199 .Case("mips5", true) 7200 .Case("mips32", !GPR64Required) 7201 .Case("mips32r2", !GPR64Required) 7202 .Case("mips32r3", !GPR64Required) 7203 .Case("mips32r5", !GPR64Required) 7204 .Case("mips32r6", !GPR64Required) 7205 .Case("mips64", true) 7206 .Case("mips64r2", true) 7207 .Case("mips64r3", true) 7208 .Case("mips64r5", true) 7209 .Case("mips64r6", true) 7210 .Case("octeon", true) 7211 .Case("p5600", !GPR64Required) 7212 .Default(false); 7213 } 7214 const std::string& getCPU() const { return CPU; } 7215 bool 7216 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7217 StringRef CPU, 7218 const std::vector<std::string> &FeaturesVec) const override { 7219 if (CPU.empty()) 7220 CPU = getCPU(); 7221 if (CPU == "octeon") 7222 Features["mips64r2"] = Features["cnmips"] = true; 7223 else 7224 Features[CPU] = true; 7225 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7226 } 7227 7228 void getTargetDefines(const LangOptions &Opts, 7229 MacroBuilder &Builder) const override { 7230 if (BigEndian) { 7231 DefineStd(Builder, "MIPSEB", Opts); 7232 Builder.defineMacro("_MIPSEB"); 7233 } else { 7234 DefineStd(Builder, "MIPSEL", Opts); 7235 Builder.defineMacro("_MIPSEL"); 7236 } 7237 7238 Builder.defineMacro("__mips__"); 7239 Builder.defineMacro("_mips"); 7240 if (Opts.GNUMode) 7241 Builder.defineMacro("mips"); 7242 7243 if (ABI == "o32") { 7244 Builder.defineMacro("__mips", "32"); 7245 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7246 } else { 7247 Builder.defineMacro("__mips", "64"); 7248 Builder.defineMacro("__mips64"); 7249 Builder.defineMacro("__mips64__"); 7250 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7251 } 7252 7253 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7254 .Cases("mips32", "mips64", "1") 7255 .Cases("mips32r2", "mips64r2", "2") 7256 .Cases("mips32r3", "mips64r3", "3") 7257 .Cases("mips32r5", "mips64r5", "5") 7258 .Cases("mips32r6", "mips64r6", "6") 7259 .Default(""); 7260 if (!ISARev.empty()) 7261 Builder.defineMacro("__mips_isa_rev", ISARev); 7262 7263 if (ABI == "o32") { 7264 Builder.defineMacro("__mips_o32"); 7265 Builder.defineMacro("_ABIO32", "1"); 7266 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7267 } else if (ABI == "n32") { 7268 Builder.defineMacro("__mips_n32"); 7269 Builder.defineMacro("_ABIN32", "2"); 7270 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7271 } else if (ABI == "n64") { 7272 Builder.defineMacro("__mips_n64"); 7273 Builder.defineMacro("_ABI64", "3"); 7274 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7275 } else 7276 llvm_unreachable("Invalid ABI."); 7277 7278 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7279 7280 switch (FloatABI) { 7281 case HardFloat: 7282 Builder.defineMacro("__mips_hard_float", Twine(1)); 7283 break; 7284 case SoftFloat: 7285 Builder.defineMacro("__mips_soft_float", Twine(1)); 7286 break; 7287 } 7288 7289 if (IsSingleFloat) 7290 Builder.defineMacro("__mips_single_float", Twine(1)); 7291 7292 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7293 Builder.defineMacro("_MIPS_FPSET", 7294 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7295 7296 if (IsMips16) 7297 Builder.defineMacro("__mips16", Twine(1)); 7298 7299 if (IsMicromips) 7300 Builder.defineMacro("__mips_micromips", Twine(1)); 7301 7302 if (IsNan2008) 7303 Builder.defineMacro("__mips_nan2008", Twine(1)); 7304 7305 switch (DspRev) { 7306 default: 7307 break; 7308 case DSP1: 7309 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7310 Builder.defineMacro("__mips_dsp", Twine(1)); 7311 break; 7312 case DSP2: 7313 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7314 Builder.defineMacro("__mips_dspr2", Twine(1)); 7315 Builder.defineMacro("__mips_dsp", Twine(1)); 7316 break; 7317 } 7318 7319 if (HasMSA) 7320 Builder.defineMacro("__mips_msa", Twine(1)); 7321 7322 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7323 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7324 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7325 7326 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7327 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7328 7329 // These shouldn't be defined for MIPS-I but there's no need to check 7330 // for that since MIPS-I isn't supported. 7331 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7332 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7333 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7334 7335 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7336 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7337 // the instructions exist but using them violates the ABI since they 7338 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7339 if (ABI == "n32" || ABI == "n64") 7340 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7341 } 7342 7343 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7344 return llvm::makeArrayRef(BuiltinInfo, 7345 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7346 } 7347 bool hasFeature(StringRef Feature) const override { 7348 return llvm::StringSwitch<bool>(Feature) 7349 .Case("mips", true) 7350 .Case("fp64", HasFP64) 7351 .Default(false); 7352 } 7353 BuiltinVaListKind getBuiltinVaListKind() const override { 7354 return TargetInfo::VoidPtrBuiltinVaList; 7355 } 7356 ArrayRef<const char *> getGCCRegNames() const override { 7357 static const char *const GCCRegNames[] = { 7358 // CPU register names 7359 // Must match second column of GCCRegAliases 7360 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7361 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7362 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7363 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7364 // Floating point register names 7365 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7366 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7367 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7368 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7369 // Hi/lo and condition register names 7370 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7371 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7372 "$ac3hi","$ac3lo", 7373 // MSA register names 7374 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7375 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7376 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7377 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7378 // MSA control register names 7379 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7380 "$msarequest", "$msamap", "$msaunmap" 7381 }; 7382 return llvm::makeArrayRef(GCCRegNames); 7383 } 7384 bool validateAsmConstraint(const char *&Name, 7385 TargetInfo::ConstraintInfo &Info) const override { 7386 switch (*Name) { 7387 default: 7388 return false; 7389 case 'r': // CPU registers. 7390 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7391 case 'y': // Equivalent to "r", backward compatibility only. 7392 case 'f': // floating-point registers. 7393 case 'c': // $25 for indirect jumps 7394 case 'l': // lo register 7395 case 'x': // hilo register pair 7396 Info.setAllowsRegister(); 7397 return true; 7398 case 'I': // Signed 16-bit constant 7399 case 'J': // Integer 0 7400 case 'K': // Unsigned 16-bit constant 7401 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7402 case 'M': // Constants not loadable via lui, addiu, or ori 7403 case 'N': // Constant -1 to -65535 7404 case 'O': // A signed 15-bit constant 7405 case 'P': // A constant between 1 go 65535 7406 return true; 7407 case 'R': // An address that can be used in a non-macro load or store 7408 Info.setAllowsMemory(); 7409 return true; 7410 case 'Z': 7411 if (Name[1] == 'C') { // An address usable by ll, and sc. 7412 Info.setAllowsMemory(); 7413 Name++; // Skip over 'Z'. 7414 return true; 7415 } 7416 return false; 7417 } 7418 } 7419 7420 std::string convertConstraint(const char *&Constraint) const override { 7421 std::string R; 7422 switch (*Constraint) { 7423 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7424 if (Constraint[1] == 'C') { 7425 R = std::string("^") + std::string(Constraint, 2); 7426 Constraint++; 7427 return R; 7428 } 7429 break; 7430 } 7431 return TargetInfo::convertConstraint(Constraint); 7432 } 7433 7434 const char *getClobbers() const override { 7435 // In GCC, $1 is not widely used in generated code (it's used only in a few 7436 // specific situations), so there is no real need for users to add it to 7437 // the clobbers list if they want to use it in their inline assembly code. 7438 // 7439 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7440 // code generation, so using it in inline assembly without adding it to the 7441 // clobbers list can cause conflicts between the inline assembly code and 7442 // the surrounding generated code. 7443 // 7444 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7445 // operands, which will conflict with the ".set at" assembler option (which 7446 // we use only for inline assembly, in order to maintain compatibility with 7447 // GCC) and will also conflict with the user's usage of $1. 7448 // 7449 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7450 // register for generated code is to automatically clobber $1 for all inline 7451 // assembly code. 7452 // 7453 // FIXME: We should automatically clobber $1 only for inline assembly code 7454 // which actually uses it. This would allow LLVM to use $1 for inline 7455 // assembly operands if the user's assembly code doesn't use it. 7456 return "~{$1}"; 7457 } 7458 7459 bool handleTargetFeatures(std::vector<std::string> &Features, 7460 DiagnosticsEngine &Diags) override { 7461 IsMips16 = false; 7462 IsMicromips = false; 7463 IsNan2008 = isNaN2008Default(); 7464 IsSingleFloat = false; 7465 FloatABI = HardFloat; 7466 DspRev = NoDSP; 7467 HasFP64 = isFP64Default(); 7468 7469 for (const auto &Feature : Features) { 7470 if (Feature == "+single-float") 7471 IsSingleFloat = true; 7472 else if (Feature == "+soft-float") 7473 FloatABI = SoftFloat; 7474 else if (Feature == "+mips16") 7475 IsMips16 = true; 7476 else if (Feature == "+micromips") 7477 IsMicromips = true; 7478 else if (Feature == "+dsp") 7479 DspRev = std::max(DspRev, DSP1); 7480 else if (Feature == "+dspr2") 7481 DspRev = std::max(DspRev, DSP2); 7482 else if (Feature == "+msa") 7483 HasMSA = true; 7484 else if (Feature == "+fp64") 7485 HasFP64 = true; 7486 else if (Feature == "-fp64") 7487 HasFP64 = false; 7488 else if (Feature == "+nan2008") 7489 IsNan2008 = true; 7490 else if (Feature == "-nan2008") 7491 IsNan2008 = false; 7492 } 7493 7494 setDataLayout(); 7495 7496 return true; 7497 } 7498 7499 int getEHDataRegisterNumber(unsigned RegNo) const override { 7500 if (RegNo == 0) return 4; 7501 if (RegNo == 1) return 5; 7502 return -1; 7503 } 7504 7505 bool isCLZForZeroUndef() const override { return false; } 7506 7507 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7508 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 7509 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7510 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7511 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 7512 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 7513 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 7514 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7515 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7516 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7517 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7518 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7519 {{"ra"}, "$31"}}; 7520 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 7521 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7522 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7523 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 7524 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 7525 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 7526 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7527 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7528 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7529 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7530 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7531 {{"ra"}, "$31"}}; 7532 if (ABI == "o32") 7533 return llvm::makeArrayRef(O32RegAliases); 7534 return llvm::makeArrayRef(NewABIRegAliases); 7535 } 7536 7537 bool hasInt128Type() const override { 7538 return ABI == "n32" || ABI == "n64"; 7539 } 7540 }; 7541 7542 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 7543 #define BUILTIN(ID, TYPE, ATTRS) \ 7544 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7545 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7546 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7547 #include "clang/Basic/BuiltinsMips.def" 7548 }; 7549 7550 class PNaClTargetInfo : public TargetInfo { 7551 public: 7552 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7553 : TargetInfo(Triple) { 7554 BigEndian = false; 7555 this->LongAlign = 32; 7556 this->LongWidth = 32; 7557 this->PointerAlign = 32; 7558 this->PointerWidth = 32; 7559 this->IntMaxType = TargetInfo::SignedLongLong; 7560 this->Int64Type = TargetInfo::SignedLongLong; 7561 this->DoubleAlign = 64; 7562 this->LongDoubleWidth = 64; 7563 this->LongDoubleAlign = 64; 7564 this->SizeType = TargetInfo::UnsignedInt; 7565 this->PtrDiffType = TargetInfo::SignedInt; 7566 this->IntPtrType = TargetInfo::SignedInt; 7567 this->RegParmMax = 0; // Disallow regparm 7568 } 7569 7570 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7571 Builder.defineMacro("__le32__"); 7572 Builder.defineMacro("__pnacl__"); 7573 } 7574 void getTargetDefines(const LangOptions &Opts, 7575 MacroBuilder &Builder) const override { 7576 getArchDefines(Opts, Builder); 7577 } 7578 bool hasFeature(StringRef Feature) const override { 7579 return Feature == "pnacl"; 7580 } 7581 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7582 BuiltinVaListKind getBuiltinVaListKind() const override { 7583 return TargetInfo::PNaClABIBuiltinVaList; 7584 } 7585 ArrayRef<const char *> getGCCRegNames() const override; 7586 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7587 bool validateAsmConstraint(const char *&Name, 7588 TargetInfo::ConstraintInfo &Info) const override { 7589 return false; 7590 } 7591 7592 const char *getClobbers() const override { 7593 return ""; 7594 } 7595 }; 7596 7597 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7598 return None; 7599 } 7600 7601 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7602 return None; 7603 } 7604 7605 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7606 class NaClMips32TargetInfo : public MipsTargetInfo { 7607 public: 7608 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7609 : MipsTargetInfo(Triple, Opts) {} 7610 7611 BuiltinVaListKind getBuiltinVaListKind() const override { 7612 return TargetInfo::PNaClABIBuiltinVaList; 7613 } 7614 }; 7615 7616 class Le64TargetInfo : public TargetInfo { 7617 static const Builtin::Info BuiltinInfo[]; 7618 7619 public: 7620 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7621 : TargetInfo(Triple) { 7622 BigEndian = false; 7623 NoAsmVariants = true; 7624 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7625 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7626 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 7627 } 7628 7629 void getTargetDefines(const LangOptions &Opts, 7630 MacroBuilder &Builder) const override { 7631 DefineStd(Builder, "unix", Opts); 7632 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7633 Builder.defineMacro("__ELF__"); 7634 } 7635 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7636 return llvm::makeArrayRef(BuiltinInfo, 7637 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7638 } 7639 BuiltinVaListKind getBuiltinVaListKind() const override { 7640 return TargetInfo::PNaClABIBuiltinVaList; 7641 } 7642 const char *getClobbers() const override { return ""; } 7643 ArrayRef<const char *> getGCCRegNames() const override { 7644 return None; 7645 } 7646 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7647 return None; 7648 } 7649 bool validateAsmConstraint(const char *&Name, 7650 TargetInfo::ConstraintInfo &Info) const override { 7651 return false; 7652 } 7653 7654 bool hasProtectedVisibility() const override { return false; } 7655 }; 7656 7657 class WebAssemblyTargetInfo : public TargetInfo { 7658 static const Builtin::Info BuiltinInfo[]; 7659 7660 enum SIMDEnum { 7661 NoSIMD, 7662 SIMD128, 7663 } SIMDLevel; 7664 7665 public: 7666 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 7667 : TargetInfo(T), SIMDLevel(NoSIMD) { 7668 BigEndian = false; 7669 NoAsmVariants = true; 7670 SuitableAlign = 128; 7671 LargeArrayMinWidth = 128; 7672 LargeArrayAlign = 128; 7673 SimdDefaultAlign = 128; 7674 SigAtomicType = SignedLong; 7675 LongDoubleWidth = LongDoubleAlign = 128; 7676 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7677 } 7678 7679 protected: 7680 void getTargetDefines(const LangOptions &Opts, 7681 MacroBuilder &Builder) const override { 7682 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7683 if (SIMDLevel >= SIMD128) 7684 Builder.defineMacro("__wasm_simd128__"); 7685 } 7686 7687 private: 7688 bool 7689 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7690 StringRef CPU, 7691 const std::vector<std::string> &FeaturesVec) const override { 7692 if (CPU == "bleeding-edge") 7693 Features["simd128"] = true; 7694 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7695 } 7696 bool hasFeature(StringRef Feature) const final { 7697 return llvm::StringSwitch<bool>(Feature) 7698 .Case("simd128", SIMDLevel >= SIMD128) 7699 .Default(false); 7700 } 7701 bool handleTargetFeatures(std::vector<std::string> &Features, 7702 DiagnosticsEngine &Diags) final { 7703 for (const auto &Feature : Features) { 7704 if (Feature == "+simd128") { 7705 SIMDLevel = std::max(SIMDLevel, SIMD128); 7706 continue; 7707 } 7708 if (Feature == "-simd128") { 7709 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7710 continue; 7711 } 7712 7713 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7714 << "-target-feature"; 7715 return false; 7716 } 7717 return true; 7718 } 7719 bool setCPU(const std::string &Name) final { 7720 return llvm::StringSwitch<bool>(Name) 7721 .Case("mvp", true) 7722 .Case("bleeding-edge", true) 7723 .Case("generic", true) 7724 .Default(false); 7725 } 7726 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7727 return llvm::makeArrayRef(BuiltinInfo, 7728 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7729 } 7730 BuiltinVaListKind getBuiltinVaListKind() const final { 7731 return VoidPtrBuiltinVaList; 7732 } 7733 ArrayRef<const char *> getGCCRegNames() const final { 7734 return None; 7735 } 7736 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7737 return None; 7738 } 7739 bool 7740 validateAsmConstraint(const char *&Name, 7741 TargetInfo::ConstraintInfo &Info) const final { 7742 return false; 7743 } 7744 const char *getClobbers() const final { return ""; } 7745 bool isCLZForZeroUndef() const final { return false; } 7746 bool hasInt128Type() const final { return true; } 7747 IntType getIntTypeByWidth(unsigned BitWidth, 7748 bool IsSigned) const final { 7749 // WebAssembly prefers long long for explicitly 64-bit integers. 7750 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7751 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7752 } 7753 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7754 bool IsSigned) const final { 7755 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7756 return BitWidth == 64 7757 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7758 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7759 } 7760 }; 7761 7762 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7763 #define BUILTIN(ID, TYPE, ATTRS) \ 7764 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7765 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7766 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7767 #include "clang/Basic/BuiltinsWebAssembly.def" 7768 }; 7769 7770 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7771 public: 7772 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 7773 const TargetOptions &Opts) 7774 : WebAssemblyTargetInfo(T, Opts) { 7775 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7776 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 7777 } 7778 7779 protected: 7780 void getTargetDefines(const LangOptions &Opts, 7781 MacroBuilder &Builder) const override { 7782 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7783 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7784 } 7785 }; 7786 7787 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7788 public: 7789 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 7790 const TargetOptions &Opts) 7791 : WebAssemblyTargetInfo(T, Opts) { 7792 LongAlign = LongWidth = 64; 7793 PointerAlign = PointerWidth = 64; 7794 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7795 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7796 } 7797 7798 protected: 7799 void getTargetDefines(const LangOptions &Opts, 7800 MacroBuilder &Builder) const override { 7801 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7802 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7803 } 7804 }; 7805 7806 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7807 #define BUILTIN(ID, TYPE, ATTRS) \ 7808 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7809 #include "clang/Basic/BuiltinsLe64.def" 7810 }; 7811 7812 static const unsigned SPIRAddrSpaceMap[] = { 7813 1, // opencl_global 7814 3, // opencl_local 7815 2, // opencl_constant 7816 4, // opencl_generic 7817 0, // cuda_device 7818 0, // cuda_constant 7819 0 // cuda_shared 7820 }; 7821 class SPIRTargetInfo : public TargetInfo { 7822 public: 7823 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7824 : TargetInfo(Triple) { 7825 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7826 "SPIR target must use unknown OS"); 7827 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7828 "SPIR target must use unknown environment type"); 7829 BigEndian = false; 7830 TLSSupported = false; 7831 LongWidth = LongAlign = 64; 7832 AddrSpaceMap = &SPIRAddrSpaceMap; 7833 UseAddrSpaceMapMangling = true; 7834 // Define available target features 7835 // These must be defined in sorted order! 7836 NoAsmVariants = true; 7837 } 7838 void getTargetDefines(const LangOptions &Opts, 7839 MacroBuilder &Builder) const override { 7840 DefineStd(Builder, "SPIR", Opts); 7841 } 7842 bool hasFeature(StringRef Feature) const override { 7843 return Feature == "spir"; 7844 } 7845 7846 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7847 const char *getClobbers() const override { return ""; } 7848 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7849 bool validateAsmConstraint(const char *&Name, 7850 TargetInfo::ConstraintInfo &info) const override { 7851 return true; 7852 } 7853 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7854 return None; 7855 } 7856 BuiltinVaListKind getBuiltinVaListKind() const override { 7857 return TargetInfo::VoidPtrBuiltinVaList; 7858 } 7859 7860 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7861 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK 7862 : CCCR_Warning; 7863 } 7864 7865 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7866 return CC_SpirFunction; 7867 } 7868 7869 void setSupportedOpenCLOpts() override { 7870 // Assume all OpenCL extensions and optional core features are supported 7871 // for SPIR since it is a generic target. 7872 getSupportedOpenCLOpts().setAll(); 7873 } 7874 }; 7875 7876 class SPIR32TargetInfo : public SPIRTargetInfo { 7877 public: 7878 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7879 : SPIRTargetInfo(Triple, Opts) { 7880 PointerWidth = PointerAlign = 32; 7881 SizeType = TargetInfo::UnsignedInt; 7882 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7883 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7884 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7885 } 7886 void getTargetDefines(const LangOptions &Opts, 7887 MacroBuilder &Builder) const override { 7888 DefineStd(Builder, "SPIR32", Opts); 7889 } 7890 }; 7891 7892 class SPIR64TargetInfo : public SPIRTargetInfo { 7893 public: 7894 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7895 : SPIRTargetInfo(Triple, Opts) { 7896 PointerWidth = PointerAlign = 64; 7897 SizeType = TargetInfo::UnsignedLong; 7898 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7899 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7900 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7901 } 7902 void getTargetDefines(const LangOptions &Opts, 7903 MacroBuilder &Builder) const override { 7904 DefineStd(Builder, "SPIR64", Opts); 7905 } 7906 }; 7907 7908 class XCoreTargetInfo : public TargetInfo { 7909 static const Builtin::Info BuiltinInfo[]; 7910 public: 7911 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7912 : TargetInfo(Triple) { 7913 BigEndian = false; 7914 NoAsmVariants = true; 7915 LongLongAlign = 32; 7916 SuitableAlign = 32; 7917 DoubleAlign = LongDoubleAlign = 32; 7918 SizeType = UnsignedInt; 7919 PtrDiffType = SignedInt; 7920 IntPtrType = SignedInt; 7921 WCharType = UnsignedChar; 7922 WIntType = UnsignedInt; 7923 UseZeroLengthBitfieldAlignment = true; 7924 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7925 "-f64:32-a:0:32-n32"); 7926 } 7927 void getTargetDefines(const LangOptions &Opts, 7928 MacroBuilder &Builder) const override { 7929 Builder.defineMacro("__XS1B__"); 7930 } 7931 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7932 return llvm::makeArrayRef(BuiltinInfo, 7933 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 7934 } 7935 BuiltinVaListKind getBuiltinVaListKind() const override { 7936 return TargetInfo::VoidPtrBuiltinVaList; 7937 } 7938 const char *getClobbers() const override { 7939 return ""; 7940 } 7941 ArrayRef<const char *> getGCCRegNames() const override { 7942 static const char * const GCCRegNames[] = { 7943 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7944 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 7945 }; 7946 return llvm::makeArrayRef(GCCRegNames); 7947 } 7948 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7949 return None; 7950 } 7951 bool validateAsmConstraint(const char *&Name, 7952 TargetInfo::ConstraintInfo &Info) const override { 7953 return false; 7954 } 7955 int getEHDataRegisterNumber(unsigned RegNo) const override { 7956 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7957 return (RegNo < 2)? RegNo : -1; 7958 } 7959 bool allowsLargerPreferedTypeAlignment() const override { 7960 return false; 7961 } 7962 }; 7963 7964 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7965 #define BUILTIN(ID, TYPE, ATTRS) \ 7966 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7967 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7968 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7969 #include "clang/Basic/BuiltinsXCore.def" 7970 }; 7971 7972 // x86_32 Android target 7973 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7974 public: 7975 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7976 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 7977 SuitableAlign = 32; 7978 LongDoubleWidth = 64; 7979 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7980 } 7981 }; 7982 7983 // x86_64 Android target 7984 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7985 public: 7986 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7987 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 7988 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7989 } 7990 7991 bool useFloat128ManglingForLongDouble() const override { 7992 return true; 7993 } 7994 }; 7995 } // end anonymous namespace 7996 7997 //===----------------------------------------------------------------------===// 7998 // Driver code 7999 //===----------------------------------------------------------------------===// 8000 8001 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 8002 const TargetOptions &Opts) { 8003 llvm::Triple::OSType os = Triple.getOS(); 8004 8005 switch (Triple.getArch()) { 8006 default: 8007 return nullptr; 8008 8009 case llvm::Triple::xcore: 8010 return new XCoreTargetInfo(Triple, Opts); 8011 8012 case llvm::Triple::hexagon: 8013 return new HexagonTargetInfo(Triple, Opts); 8014 8015 case llvm::Triple::lanai: 8016 return new LanaiTargetInfo(Triple, Opts); 8017 8018 case llvm::Triple::aarch64: 8019 if (Triple.isOSDarwin()) 8020 return new DarwinAArch64TargetInfo(Triple, Opts); 8021 8022 switch (os) { 8023 case llvm::Triple::CloudABI: 8024 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 8025 case llvm::Triple::FreeBSD: 8026 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8027 case llvm::Triple::Linux: 8028 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8029 case llvm::Triple::NetBSD: 8030 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8031 default: 8032 return new AArch64leTargetInfo(Triple, Opts); 8033 } 8034 8035 case llvm::Triple::aarch64_be: 8036 switch (os) { 8037 case llvm::Triple::FreeBSD: 8038 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8039 case llvm::Triple::Linux: 8040 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8041 case llvm::Triple::NetBSD: 8042 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8043 default: 8044 return new AArch64beTargetInfo(Triple, Opts); 8045 } 8046 8047 case llvm::Triple::arm: 8048 case llvm::Triple::thumb: 8049 if (Triple.isOSBinFormatMachO()) 8050 return new DarwinARMTargetInfo(Triple, Opts); 8051 8052 switch (os) { 8053 case llvm::Triple::Linux: 8054 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 8055 case llvm::Triple::FreeBSD: 8056 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8057 case llvm::Triple::NetBSD: 8058 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8059 case llvm::Triple::OpenBSD: 8060 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8061 case llvm::Triple::Bitrig: 8062 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 8063 case llvm::Triple::RTEMS: 8064 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 8065 case llvm::Triple::NaCl: 8066 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 8067 case llvm::Triple::Win32: 8068 switch (Triple.getEnvironment()) { 8069 case llvm::Triple::Cygnus: 8070 return new CygwinARMTargetInfo(Triple, Opts); 8071 case llvm::Triple::GNU: 8072 return new MinGWARMTargetInfo(Triple, Opts); 8073 case llvm::Triple::Itanium: 8074 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 8075 case llvm::Triple::MSVC: 8076 default: // Assume MSVC for unknown environments 8077 return new MicrosoftARMleTargetInfo(Triple, Opts); 8078 } 8079 default: 8080 return new ARMleTargetInfo(Triple, Opts); 8081 } 8082 8083 case llvm::Triple::armeb: 8084 case llvm::Triple::thumbeb: 8085 if (Triple.isOSDarwin()) 8086 return new DarwinARMTargetInfo(Triple, Opts); 8087 8088 switch (os) { 8089 case llvm::Triple::Linux: 8090 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8091 case llvm::Triple::FreeBSD: 8092 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8093 case llvm::Triple::NetBSD: 8094 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8095 case llvm::Triple::OpenBSD: 8096 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8097 case llvm::Triple::Bitrig: 8098 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8099 case llvm::Triple::RTEMS: 8100 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8101 case llvm::Triple::NaCl: 8102 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8103 default: 8104 return new ARMbeTargetInfo(Triple, Opts); 8105 } 8106 8107 case llvm::Triple::bpfeb: 8108 case llvm::Triple::bpfel: 8109 return new BPFTargetInfo(Triple, Opts); 8110 8111 case llvm::Triple::msp430: 8112 return new MSP430TargetInfo(Triple, Opts); 8113 8114 case llvm::Triple::mips: 8115 switch (os) { 8116 case llvm::Triple::Linux: 8117 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8118 case llvm::Triple::RTEMS: 8119 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8120 case llvm::Triple::FreeBSD: 8121 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8122 case llvm::Triple::NetBSD: 8123 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8124 default: 8125 return new MipsTargetInfo(Triple, Opts); 8126 } 8127 8128 case llvm::Triple::mipsel: 8129 switch (os) { 8130 case llvm::Triple::Linux: 8131 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8132 case llvm::Triple::RTEMS: 8133 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8134 case llvm::Triple::FreeBSD: 8135 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8136 case llvm::Triple::NetBSD: 8137 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8138 case llvm::Triple::NaCl: 8139 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 8140 default: 8141 return new MipsTargetInfo(Triple, Opts); 8142 } 8143 8144 case llvm::Triple::mips64: 8145 switch (os) { 8146 case llvm::Triple::Linux: 8147 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8148 case llvm::Triple::RTEMS: 8149 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8150 case llvm::Triple::FreeBSD: 8151 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8152 case llvm::Triple::NetBSD: 8153 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8154 case llvm::Triple::OpenBSD: 8155 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8156 default: 8157 return new MipsTargetInfo(Triple, Opts); 8158 } 8159 8160 case llvm::Triple::mips64el: 8161 switch (os) { 8162 case llvm::Triple::Linux: 8163 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8164 case llvm::Triple::RTEMS: 8165 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8166 case llvm::Triple::FreeBSD: 8167 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8168 case llvm::Triple::NetBSD: 8169 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8170 case llvm::Triple::OpenBSD: 8171 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8172 default: 8173 return new MipsTargetInfo(Triple, Opts); 8174 } 8175 8176 case llvm::Triple::le32: 8177 switch (os) { 8178 case llvm::Triple::NaCl: 8179 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 8180 default: 8181 return nullptr; 8182 } 8183 8184 case llvm::Triple::le64: 8185 return new Le64TargetInfo(Triple, Opts); 8186 8187 case llvm::Triple::ppc: 8188 if (Triple.isOSDarwin()) 8189 return new DarwinPPC32TargetInfo(Triple, Opts); 8190 switch (os) { 8191 case llvm::Triple::Linux: 8192 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 8193 case llvm::Triple::FreeBSD: 8194 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8195 case llvm::Triple::NetBSD: 8196 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8197 case llvm::Triple::OpenBSD: 8198 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8199 case llvm::Triple::RTEMS: 8200 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 8201 default: 8202 return new PPC32TargetInfo(Triple, Opts); 8203 } 8204 8205 case llvm::Triple::ppc64: 8206 if (Triple.isOSDarwin()) 8207 return new DarwinPPC64TargetInfo(Triple, Opts); 8208 switch (os) { 8209 case llvm::Triple::Linux: 8210 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8211 case llvm::Triple::Lv2: 8212 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 8213 case llvm::Triple::FreeBSD: 8214 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8215 case llvm::Triple::NetBSD: 8216 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8217 default: 8218 return new PPC64TargetInfo(Triple, Opts); 8219 } 8220 8221 case llvm::Triple::ppc64le: 8222 switch (os) { 8223 case llvm::Triple::Linux: 8224 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8225 case llvm::Triple::NetBSD: 8226 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8227 default: 8228 return new PPC64TargetInfo(Triple, Opts); 8229 } 8230 8231 case llvm::Triple::nvptx: 8232 return new NVPTX32TargetInfo(Triple, Opts); 8233 case llvm::Triple::nvptx64: 8234 return new NVPTX64TargetInfo(Triple, Opts); 8235 8236 case llvm::Triple::amdgcn: 8237 case llvm::Triple::r600: 8238 return new AMDGPUTargetInfo(Triple, Opts); 8239 8240 case llvm::Triple::sparc: 8241 switch (os) { 8242 case llvm::Triple::Linux: 8243 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8244 case llvm::Triple::Solaris: 8245 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8246 case llvm::Triple::NetBSD: 8247 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8248 case llvm::Triple::OpenBSD: 8249 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8250 case llvm::Triple::RTEMS: 8251 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8252 default: 8253 return new SparcV8TargetInfo(Triple, Opts); 8254 } 8255 8256 // The 'sparcel' architecture copies all the above cases except for Solaris. 8257 case llvm::Triple::sparcel: 8258 switch (os) { 8259 case llvm::Triple::Linux: 8260 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8261 case llvm::Triple::NetBSD: 8262 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8263 case llvm::Triple::OpenBSD: 8264 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8265 case llvm::Triple::RTEMS: 8266 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8267 default: 8268 return new SparcV8elTargetInfo(Triple, Opts); 8269 } 8270 8271 case llvm::Triple::sparcv9: 8272 switch (os) { 8273 case llvm::Triple::Linux: 8274 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8275 case llvm::Triple::Solaris: 8276 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8277 case llvm::Triple::NetBSD: 8278 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8279 case llvm::Triple::OpenBSD: 8280 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8281 case llvm::Triple::FreeBSD: 8282 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8283 default: 8284 return new SparcV9TargetInfo(Triple, Opts); 8285 } 8286 8287 case llvm::Triple::systemz: 8288 switch (os) { 8289 case llvm::Triple::Linux: 8290 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 8291 default: 8292 return new SystemZTargetInfo(Triple, Opts); 8293 } 8294 8295 case llvm::Triple::tce: 8296 return new TCETargetInfo(Triple, Opts); 8297 8298 case llvm::Triple::x86: 8299 if (Triple.isOSDarwin()) 8300 return new DarwinI386TargetInfo(Triple, Opts); 8301 8302 switch (os) { 8303 case llvm::Triple::CloudABI: 8304 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 8305 case llvm::Triple::Linux: { 8306 switch (Triple.getEnvironment()) { 8307 default: 8308 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 8309 case llvm::Triple::Android: 8310 return new AndroidX86_32TargetInfo(Triple, Opts); 8311 } 8312 } 8313 case llvm::Triple::DragonFly: 8314 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8315 case llvm::Triple::NetBSD: 8316 return new NetBSDI386TargetInfo(Triple, Opts); 8317 case llvm::Triple::OpenBSD: 8318 return new OpenBSDI386TargetInfo(Triple, Opts); 8319 case llvm::Triple::Bitrig: 8320 return new BitrigI386TargetInfo(Triple, Opts); 8321 case llvm::Triple::FreeBSD: 8322 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8323 case llvm::Triple::KFreeBSD: 8324 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8325 case llvm::Triple::Minix: 8326 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 8327 case llvm::Triple::Solaris: 8328 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 8329 case llvm::Triple::Win32: { 8330 switch (Triple.getEnvironment()) { 8331 case llvm::Triple::Cygnus: 8332 return new CygwinX86_32TargetInfo(Triple, Opts); 8333 case llvm::Triple::GNU: 8334 return new MinGWX86_32TargetInfo(Triple, Opts); 8335 case llvm::Triple::Itanium: 8336 case llvm::Triple::MSVC: 8337 default: // Assume MSVC for unknown environments 8338 return new MicrosoftX86_32TargetInfo(Triple, Opts); 8339 } 8340 } 8341 case llvm::Triple::Haiku: 8342 return new HaikuX86_32TargetInfo(Triple, Opts); 8343 case llvm::Triple::RTEMS: 8344 return new RTEMSX86_32TargetInfo(Triple, Opts); 8345 case llvm::Triple::NaCl: 8346 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 8347 case llvm::Triple::ELFIAMCU: 8348 return new MCUX86_32TargetInfo(Triple, Opts); 8349 default: 8350 return new X86_32TargetInfo(Triple, Opts); 8351 } 8352 8353 case llvm::Triple::x86_64: 8354 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 8355 return new DarwinX86_64TargetInfo(Triple, Opts); 8356 8357 switch (os) { 8358 case llvm::Triple::CloudABI: 8359 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 8360 case llvm::Triple::Linux: { 8361 switch (Triple.getEnvironment()) { 8362 default: 8363 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 8364 case llvm::Triple::Android: 8365 return new AndroidX86_64TargetInfo(Triple, Opts); 8366 } 8367 } 8368 case llvm::Triple::DragonFly: 8369 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8370 case llvm::Triple::NetBSD: 8371 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8372 case llvm::Triple::OpenBSD: 8373 return new OpenBSDX86_64TargetInfo(Triple, Opts); 8374 case llvm::Triple::Bitrig: 8375 return new BitrigX86_64TargetInfo(Triple, Opts); 8376 case llvm::Triple::FreeBSD: 8377 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8378 case llvm::Triple::KFreeBSD: 8379 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8380 case llvm::Triple::Solaris: 8381 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 8382 case llvm::Triple::Win32: { 8383 switch (Triple.getEnvironment()) { 8384 case llvm::Triple::Cygnus: 8385 return new CygwinX86_64TargetInfo(Triple, Opts); 8386 case llvm::Triple::GNU: 8387 return new MinGWX86_64TargetInfo(Triple, Opts); 8388 case llvm::Triple::MSVC: 8389 default: // Assume MSVC for unknown environments 8390 return new MicrosoftX86_64TargetInfo(Triple, Opts); 8391 } 8392 } 8393 case llvm::Triple::Haiku: 8394 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 8395 case llvm::Triple::NaCl: 8396 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 8397 case llvm::Triple::PS4: 8398 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 8399 default: 8400 return new X86_64TargetInfo(Triple, Opts); 8401 } 8402 8403 case llvm::Triple::spir: { 8404 if (Triple.getOS() != llvm::Triple::UnknownOS || 8405 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8406 return nullptr; 8407 return new SPIR32TargetInfo(Triple, Opts); 8408 } 8409 case llvm::Triple::spir64: { 8410 if (Triple.getOS() != llvm::Triple::UnknownOS || 8411 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8412 return nullptr; 8413 return new SPIR64TargetInfo(Triple, Opts); 8414 } 8415 case llvm::Triple::wasm32: 8416 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8417 return nullptr; 8418 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 8419 case llvm::Triple::wasm64: 8420 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8421 return nullptr; 8422 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 8423 } 8424 } 8425 8426 /// CreateTargetInfo - Return the target info object for the specified target 8427 /// options. 8428 TargetInfo * 8429 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8430 const std::shared_ptr<TargetOptions> &Opts) { 8431 llvm::Triple Triple(Opts->Triple); 8432 8433 // Construct the target 8434 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 8435 if (!Target) { 8436 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8437 return nullptr; 8438 } 8439 Target->TargetOpts = Opts; 8440 8441 // Set the target CPU if specified. 8442 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8443 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8444 return nullptr; 8445 } 8446 8447 // Set the target ABI if specified. 8448 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8449 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8450 return nullptr; 8451 } 8452 8453 // Set the fp math unit. 8454 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8455 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8456 return nullptr; 8457 } 8458 8459 // Compute the default target features, we need the target to handle this 8460 // because features may have dependencies on one another. 8461 llvm::StringMap<bool> Features; 8462 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8463 Opts->FeaturesAsWritten)) 8464 return nullptr; 8465 8466 // Add the features to the compile options. 8467 Opts->Features.clear(); 8468 for (const auto &F : Features) 8469 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8470 8471 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8472 return nullptr; 8473 8474 Target->setSupportedOpenCLOpts(); 8475 8476 return Target.release(); 8477 } 8478