1 //===--- Targets.cpp - Implement -arch option and targets -----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements construction of a TargetInfo object from a
11 // target triple.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/MC/MCSectionMachO.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include <algorithm>
31 #include <memory>
32 using namespace clang;
33 
34 //===----------------------------------------------------------------------===//
35 //  Common code shared among targets.
36 //===----------------------------------------------------------------------===//
37 
38 /// DefineStd - Define a macro name and standard variants.  For example if
39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
40 /// when in GNU mode.
41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
42                       const LangOptions &Opts) {
43   assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
44 
45   // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
46   // in the user's namespace.
47   if (Opts.GNUMode)
48     Builder.defineMacro(MacroName);
49 
50   // Define __unix.
51   Builder.defineMacro("__" + MacroName);
52 
53   // Define __unix__.
54   Builder.defineMacro("__" + MacroName + "__");
55 }
56 
57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
58                             bool Tuning = true) {
59   Builder.defineMacro("__" + CPUName);
60   Builder.defineMacro("__" + CPUName + "__");
61   if (Tuning)
62     Builder.defineMacro("__tune_" + CPUName + "__");
63 }
64 
65 //===----------------------------------------------------------------------===//
66 // Defines specific to certain operating systems.
67 //===----------------------------------------------------------------------===//
68 
69 namespace {
70 template<typename TgtInfo>
71 class OSTargetInfo : public TgtInfo {
72 protected:
73   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
74                             MacroBuilder &Builder) const=0;
75 public:
76   OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
77   void getTargetDefines(const LangOptions &Opts,
78                         MacroBuilder &Builder) const override {
79     TgtInfo::getTargetDefines(Opts, Builder);
80     getOSDefines(Opts, TgtInfo::getTriple(), Builder);
81   }
82 
83 };
84 } // end anonymous namespace
85 
86 
87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
88                              const llvm::Triple &Triple,
89                              StringRef &PlatformName,
90                              VersionTuple &PlatformMinVersion) {
91   Builder.defineMacro("__APPLE_CC__", "6000");
92   Builder.defineMacro("__APPLE__");
93   Builder.defineMacro("OBJC_NEW_PROPERTIES");
94   // AddressSanitizer doesn't play well with source fortification, which is on
95   // by default on Darwin.
96   if (Opts.Sanitize.has(SanitizerKind::Address))
97     Builder.defineMacro("_FORTIFY_SOURCE", "0");
98 
99   if (!Opts.ObjCAutoRefCount) {
100     // __weak is always defined, for use in blocks and with objc pointers.
101     Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
102 
103     // Darwin defines __strong even in C mode (just to nothing).
104     if (Opts.getGC() != LangOptions::NonGC)
105       Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
106     else
107       Builder.defineMacro("__strong", "");
108 
109     // __unsafe_unretained is defined to nothing in non-ARC mode. We even
110     // allow this in C, since one might have block pointers in structs that
111     // are used in pure C code and in Objective-C ARC.
112     Builder.defineMacro("__unsafe_unretained", "");
113   }
114 
115   if (Opts.Static)
116     Builder.defineMacro("__STATIC__");
117   else
118     Builder.defineMacro("__DYNAMIC__");
119 
120   if (Opts.POSIXThreads)
121     Builder.defineMacro("_REENTRANT");
122 
123   // Get the platform type and version number from the triple.
124   unsigned Maj, Min, Rev;
125   if (Triple.isMacOSX()) {
126     Triple.getMacOSXVersion(Maj, Min, Rev);
127     PlatformName = "macosx";
128   } else {
129     Triple.getOSVersion(Maj, Min, Rev);
130     PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
131   }
132 
133   // If -target arch-pc-win32-macho option specified, we're
134   // generating code for Win32 ABI. No need to emit
135   // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
136   if (PlatformName == "win32") {
137     PlatformMinVersion = VersionTuple(Maj, Min, Rev);
138     return;
139   }
140 
141   // Set the appropriate OS version define.
142   if (Triple.isiOS()) {
143     assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
144     char Str[6];
145     Str[0] = '0' + Maj;
146     Str[1] = '0' + (Min / 10);
147     Str[2] = '0' + (Min % 10);
148     Str[3] = '0' + (Rev / 10);
149     Str[4] = '0' + (Rev % 10);
150     Str[5] = '\0';
151     Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
152                         Str);
153   } else if (Triple.isMacOSX()) {
154     // Note that the Driver allows versions which aren't representable in the
155     // define (because we only get a single digit for the minor and micro
156     // revision numbers). So, we limit them to the maximum representable
157     // version.
158     assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
159     char Str[7];
160     if (Maj < 10 || (Maj == 10 && Min < 10)) {
161       Str[0] = '0' + (Maj / 10);
162       Str[1] = '0' + (Maj % 10);
163       Str[2] = '0' + std::min(Min, 9U);
164       Str[3] = '0' + std::min(Rev, 9U);
165       Str[4] = '\0';
166     } else {
167       // Handle versions > 10.9.
168       Str[0] = '0' + (Maj / 10);
169       Str[1] = '0' + (Maj % 10);
170       Str[2] = '0' + (Min / 10);
171       Str[3] = '0' + (Min % 10);
172       Str[4] = '0' + (Rev / 10);
173       Str[5] = '0' + (Rev % 10);
174       Str[6] = '\0';
175     }
176     Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
177   }
178 
179   // Tell users about the kernel if there is one.
180   if (Triple.isOSDarwin())
181     Builder.defineMacro("__MACH__");
182 
183   PlatformMinVersion = VersionTuple(Maj, Min, Rev);
184 }
185 
186 // CloudABI Target
187 template <typename Target>
188 class CloudABITargetInfo : public OSTargetInfo<Target> {
189 protected:
190   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
191                     MacroBuilder &Builder) const override {
192     Builder.defineMacro("__CloudABI__");
193     Builder.defineMacro("__ELF__");
194 
195     // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t.
196     Builder.defineMacro("__STDC_ISO_10646__", "201206L");
197     Builder.defineMacro("__STDC_UTF_16__");
198     Builder.defineMacro("__STDC_UTF_32__");
199   }
200 
201 public:
202   CloudABITargetInfo(const llvm::Triple &Triple)
203       : OSTargetInfo<Target>(Triple) {
204     this->UserLabelPrefix = "";
205   }
206 };
207 
208 namespace {
209 template<typename Target>
210 class DarwinTargetInfo : public OSTargetInfo<Target> {
211 protected:
212   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
213                     MacroBuilder &Builder) const override {
214     getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
215                      this->PlatformMinVersion);
216   }
217 
218 public:
219   DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
220     this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
221     this->MCountName = "\01mcount";
222   }
223 
224   std::string isValidSectionSpecifier(StringRef SR) const override {
225     // Let MCSectionMachO validate this.
226     StringRef Segment, Section;
227     unsigned TAA, StubSize;
228     bool HasTAA;
229     return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
230                                                        TAA, HasTAA, StubSize);
231   }
232 
233   const char *getStaticInitSectionSpecifier() const override {
234     // FIXME: We should return 0 when building kexts.
235     return "__TEXT,__StaticInit,regular,pure_instructions";
236   }
237 
238   /// Darwin does not support protected visibility.  Darwin's "default"
239   /// is very similar to ELF's "protected";  Darwin requires a "weak"
240   /// attribute on declarations that can be dynamically replaced.
241   bool hasProtectedVisibility() const override {
242     return false;
243   }
244 };
245 
246 
247 // DragonFlyBSD Target
248 template<typename Target>
249 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
250 protected:
251   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
252                     MacroBuilder &Builder) const override {
253     // DragonFly defines; list based off of gcc output
254     Builder.defineMacro("__DragonFly__");
255     Builder.defineMacro("__DragonFly_cc_version", "100001");
256     Builder.defineMacro("__ELF__");
257     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
258     Builder.defineMacro("__tune_i386__");
259     DefineStd(Builder, "unix", Opts);
260   }
261 public:
262   DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
263       : OSTargetInfo<Target>(Triple) {
264     this->UserLabelPrefix = "";
265 
266     switch (Triple.getArch()) {
267     default:
268     case llvm::Triple::x86:
269     case llvm::Triple::x86_64:
270       this->MCountName = ".mcount";
271       break;
272     }
273   }
274 };
275 
276 // FreeBSD Target
277 template<typename Target>
278 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
279 protected:
280   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
281                     MacroBuilder &Builder) const override {
282     // FreeBSD defines; list based off of gcc output
283 
284     unsigned Release = Triple.getOSMajorVersion();
285     if (Release == 0U)
286       Release = 8;
287 
288     Builder.defineMacro("__FreeBSD__", Twine(Release));
289     Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
290     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
291     DefineStd(Builder, "unix", Opts);
292     Builder.defineMacro("__ELF__");
293 
294     // On FreeBSD, wchar_t contains the number of the code point as
295     // used by the character set of the locale. These character sets are
296     // not necessarily a superset of ASCII.
297     //
298     // FIXME: This is wrong; the macro refers to the numerical values
299     // of wchar_t *literals*, which are not locale-dependent. However,
300     // FreeBSD systems apparently depend on us getting this wrong, and
301     // setting this to 1 is conforming even if all the basic source
302     // character literals have the same encoding as char and wchar_t.
303     Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
304   }
305 public:
306   FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
307     this->UserLabelPrefix = "";
308 
309     switch (Triple.getArch()) {
310     default:
311     case llvm::Triple::x86:
312     case llvm::Triple::x86_64:
313       this->MCountName = ".mcount";
314       break;
315     case llvm::Triple::mips:
316     case llvm::Triple::mipsel:
317     case llvm::Triple::ppc:
318     case llvm::Triple::ppc64:
319     case llvm::Triple::ppc64le:
320       this->MCountName = "_mcount";
321       break;
322     case llvm::Triple::arm:
323       this->MCountName = "__mcount";
324       break;
325     }
326   }
327 };
328 
329 // GNU/kFreeBSD Target
330 template<typename Target>
331 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
332 protected:
333   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
334                     MacroBuilder &Builder) const override {
335     // GNU/kFreeBSD defines; list based off of gcc output
336 
337     DefineStd(Builder, "unix", Opts);
338     Builder.defineMacro("__FreeBSD_kernel__");
339     Builder.defineMacro("__GLIBC__");
340     Builder.defineMacro("__ELF__");
341     if (Opts.POSIXThreads)
342       Builder.defineMacro("_REENTRANT");
343     if (Opts.CPlusPlus)
344       Builder.defineMacro("_GNU_SOURCE");
345   }
346 public:
347   KFreeBSDTargetInfo(const llvm::Triple &Triple)
348       : OSTargetInfo<Target>(Triple) {
349     this->UserLabelPrefix = "";
350   }
351 };
352 
353 // Minix Target
354 template<typename Target>
355 class MinixTargetInfo : public OSTargetInfo<Target> {
356 protected:
357   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
358                     MacroBuilder &Builder) const override {
359     // Minix defines
360 
361     Builder.defineMacro("__minix", "3");
362     Builder.defineMacro("_EM_WSIZE", "4");
363     Builder.defineMacro("_EM_PSIZE", "4");
364     Builder.defineMacro("_EM_SSIZE", "2");
365     Builder.defineMacro("_EM_LSIZE", "4");
366     Builder.defineMacro("_EM_FSIZE", "4");
367     Builder.defineMacro("_EM_DSIZE", "8");
368     Builder.defineMacro("__ELF__");
369     DefineStd(Builder, "unix", Opts);
370   }
371 public:
372   MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
373     this->UserLabelPrefix = "";
374   }
375 };
376 
377 // Linux target
378 template<typename Target>
379 class LinuxTargetInfo : public OSTargetInfo<Target> {
380 protected:
381   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
382                     MacroBuilder &Builder) const override {
383     // Linux defines; list based off of gcc output
384     DefineStd(Builder, "unix", Opts);
385     DefineStd(Builder, "linux", Opts);
386     Builder.defineMacro("__gnu_linux__");
387     Builder.defineMacro("__ELF__");
388     if (Triple.getEnvironment() == llvm::Triple::Android) {
389       Builder.defineMacro("__ANDROID__", "1");
390       unsigned Maj, Min, Rev;
391       Triple.getOSVersion(Maj, Min, Rev);
392       this->PlatformName = "android";
393       this->PlatformMinVersion = VersionTuple(Maj, Min, Rev);
394     }
395     if (Opts.POSIXThreads)
396       Builder.defineMacro("_REENTRANT");
397     if (Opts.CPlusPlus)
398       Builder.defineMacro("_GNU_SOURCE");
399   }
400 public:
401   LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
402     this->UserLabelPrefix = "";
403     this->WIntType = TargetInfo::UnsignedInt;
404 
405     switch (Triple.getArch()) {
406     default:
407       break;
408     case llvm::Triple::ppc:
409     case llvm::Triple::ppc64:
410     case llvm::Triple::ppc64le:
411       this->MCountName = "_mcount";
412       break;
413     }
414   }
415 
416   const char *getStaticInitSectionSpecifier() const override {
417     return ".text.startup";
418   }
419 };
420 
421 // NetBSD Target
422 template<typename Target>
423 class NetBSDTargetInfo : public OSTargetInfo<Target> {
424 protected:
425   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
426                     MacroBuilder &Builder) const override {
427     // NetBSD defines; list based off of gcc output
428     Builder.defineMacro("__NetBSD__");
429     Builder.defineMacro("__unix__");
430     Builder.defineMacro("__ELF__");
431     if (Opts.POSIXThreads)
432       Builder.defineMacro("_POSIX_THREADS");
433 
434     switch (Triple.getArch()) {
435     default:
436       break;
437     case llvm::Triple::arm:
438     case llvm::Triple::armeb:
439     case llvm::Triple::thumb:
440     case llvm::Triple::thumbeb:
441       Builder.defineMacro("__ARM_DWARF_EH__");
442       break;
443     }
444   }
445 public:
446   NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
447     this->UserLabelPrefix = "";
448   }
449 };
450 
451 // OpenBSD Target
452 template<typename Target>
453 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
454 protected:
455   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
456                     MacroBuilder &Builder) const override {
457     // OpenBSD defines; list based off of gcc output
458 
459     Builder.defineMacro("__OpenBSD__");
460     DefineStd(Builder, "unix", Opts);
461     Builder.defineMacro("__ELF__");
462     if (Opts.POSIXThreads)
463       Builder.defineMacro("_REENTRANT");
464   }
465 public:
466   OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
467     this->UserLabelPrefix = "";
468     this->TLSSupported = false;
469 
470       switch (Triple.getArch()) {
471         default:
472         case llvm::Triple::x86:
473         case llvm::Triple::x86_64:
474         case llvm::Triple::arm:
475         case llvm::Triple::sparc:
476           this->MCountName = "__mcount";
477           break;
478         case llvm::Triple::mips64:
479         case llvm::Triple::mips64el:
480         case llvm::Triple::ppc:
481         case llvm::Triple::sparcv9:
482           this->MCountName = "_mcount";
483           break;
484       }
485   }
486 };
487 
488 // Bitrig Target
489 template<typename Target>
490 class BitrigTargetInfo : public OSTargetInfo<Target> {
491 protected:
492   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
493                     MacroBuilder &Builder) const override {
494     // Bitrig defines; list based off of gcc output
495 
496     Builder.defineMacro("__Bitrig__");
497     DefineStd(Builder, "unix", Opts);
498     Builder.defineMacro("__ELF__");
499     if (Opts.POSIXThreads)
500       Builder.defineMacro("_REENTRANT");
501 
502     switch (Triple.getArch()) {
503     default:
504       break;
505     case llvm::Triple::arm:
506     case llvm::Triple::armeb:
507     case llvm::Triple::thumb:
508     case llvm::Triple::thumbeb:
509       Builder.defineMacro("__ARM_DWARF_EH__");
510       break;
511     }
512   }
513 public:
514   BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
515     this->UserLabelPrefix = "";
516     this->MCountName = "__mcount";
517   }
518 };
519 
520 // PSP Target
521 template<typename Target>
522 class PSPTargetInfo : public OSTargetInfo<Target> {
523 protected:
524   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
525                     MacroBuilder &Builder) const override {
526     // PSP defines; list based on the output of the pspdev gcc toolchain.
527     Builder.defineMacro("PSP");
528     Builder.defineMacro("_PSP");
529     Builder.defineMacro("__psp__");
530     Builder.defineMacro("__ELF__");
531   }
532 public:
533   PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
534     this->UserLabelPrefix = "";
535   }
536 };
537 
538 // PS3 PPU Target
539 template<typename Target>
540 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
541 protected:
542   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
543                     MacroBuilder &Builder) const override {
544     // PS3 PPU defines.
545     Builder.defineMacro("__PPC__");
546     Builder.defineMacro("__PPU__");
547     Builder.defineMacro("__CELLOS_LV2__");
548     Builder.defineMacro("__ELF__");
549     Builder.defineMacro("__LP32__");
550     Builder.defineMacro("_ARCH_PPC64");
551     Builder.defineMacro("__powerpc64__");
552   }
553 public:
554   PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
555     this->UserLabelPrefix = "";
556     this->LongWidth = this->LongAlign = 32;
557     this->PointerWidth = this->PointerAlign = 32;
558     this->IntMaxType = TargetInfo::SignedLongLong;
559     this->Int64Type = TargetInfo::SignedLongLong;
560     this->SizeType = TargetInfo::UnsignedInt;
561     this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64";
562   }
563 };
564 
565 template <typename Target>
566 class PS4OSTargetInfo : public OSTargetInfo<Target> {
567 protected:
568   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
569                     MacroBuilder &Builder) const override {
570     Builder.defineMacro("__FreeBSD__", "9");
571     Builder.defineMacro("__FreeBSD_cc_version", "900001");
572     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
573     DefineStd(Builder, "unix", Opts);
574     Builder.defineMacro("__ELF__");
575     Builder.defineMacro("__PS4__");
576   }
577 public:
578   PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
579     this->WCharType = this->UnsignedShort;
580 
581     this->UserLabelPrefix = "";
582 
583     switch (Triple.getArch()) {
584     default:
585     case llvm::Triple::x86_64:
586       this->MCountName = ".mcount";
587       break;
588     }
589   }
590 };
591 
592 // Solaris target
593 template<typename Target>
594 class SolarisTargetInfo : public OSTargetInfo<Target> {
595 protected:
596   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
597                     MacroBuilder &Builder) const override {
598     DefineStd(Builder, "sun", Opts);
599     DefineStd(Builder, "unix", Opts);
600     Builder.defineMacro("__ELF__");
601     Builder.defineMacro("__svr4__");
602     Builder.defineMacro("__SVR4");
603     // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
604     // newer, but to 500 for everything else.  feature_test.h has a check to
605     // ensure that you are not using C99 with an old version of X/Open or C89
606     // with a new version.
607     if (Opts.C99)
608       Builder.defineMacro("_XOPEN_SOURCE", "600");
609     else
610       Builder.defineMacro("_XOPEN_SOURCE", "500");
611     if (Opts.CPlusPlus)
612       Builder.defineMacro("__C99FEATURES__");
613     Builder.defineMacro("_LARGEFILE_SOURCE");
614     Builder.defineMacro("_LARGEFILE64_SOURCE");
615     Builder.defineMacro("__EXTENSIONS__");
616     Builder.defineMacro("_REENTRANT");
617   }
618 public:
619   SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
620     this->UserLabelPrefix = "";
621     this->WCharType = this->SignedInt;
622     // FIXME: WIntType should be SignedLong
623   }
624 };
625 
626 // Windows target
627 template<typename Target>
628 class WindowsTargetInfo : public OSTargetInfo<Target> {
629 protected:
630   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
631                     MacroBuilder &Builder) const override {
632     Builder.defineMacro("_WIN32");
633   }
634   void getVisualStudioDefines(const LangOptions &Opts,
635                               MacroBuilder &Builder) const {
636     if (Opts.CPlusPlus) {
637       if (Opts.RTTIData)
638         Builder.defineMacro("_CPPRTTI");
639 
640       if (Opts.CXXExceptions)
641         Builder.defineMacro("_CPPUNWIND");
642     }
643 
644     if (!Opts.CharIsSigned)
645       Builder.defineMacro("_CHAR_UNSIGNED");
646 
647     // FIXME: POSIXThreads isn't exactly the option this should be defined for,
648     //        but it works for now.
649     if (Opts.POSIXThreads)
650       Builder.defineMacro("_MT");
651 
652     if (Opts.MSCompatibilityVersion) {
653       Builder.defineMacro("_MSC_VER",
654                           Twine(Opts.MSCompatibilityVersion / 100000));
655       Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
656       // FIXME We cannot encode the revision information into 32-bits
657       Builder.defineMacro("_MSC_BUILD", Twine(1));
658 
659       if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(19))
660         Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1));
661     }
662 
663     if (Opts.MicrosoftExt) {
664       Builder.defineMacro("_MSC_EXTENSIONS");
665 
666       if (Opts.CPlusPlus11) {
667         Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
668         Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
669         Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
670       }
671     }
672 
673     Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
674   }
675 
676 public:
677   WindowsTargetInfo(const llvm::Triple &Triple)
678       : OSTargetInfo<Target>(Triple) {}
679 };
680 
681 template <typename Target>
682 class NaClTargetInfo : public OSTargetInfo<Target> {
683 protected:
684   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
685                     MacroBuilder &Builder) const override {
686     if (Opts.POSIXThreads)
687       Builder.defineMacro("_REENTRANT");
688     if (Opts.CPlusPlus)
689       Builder.defineMacro("_GNU_SOURCE");
690 
691     DefineStd(Builder, "unix", Opts);
692     Builder.defineMacro("__ELF__");
693     Builder.defineMacro("__native_client__");
694   }
695 
696 public:
697   NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
698     this->UserLabelPrefix = "";
699     this->LongAlign = 32;
700     this->LongWidth = 32;
701     this->PointerAlign = 32;
702     this->PointerWidth = 32;
703     this->IntMaxType = TargetInfo::SignedLongLong;
704     this->Int64Type = TargetInfo::SignedLongLong;
705     this->DoubleAlign = 64;
706     this->LongDoubleWidth = 64;
707     this->LongDoubleAlign = 64;
708     this->LongLongWidth = 64;
709     this->LongLongAlign = 64;
710     this->SizeType = TargetInfo::UnsignedInt;
711     this->PtrDiffType = TargetInfo::SignedInt;
712     this->IntPtrType = TargetInfo::SignedInt;
713     // RegParmMax is inherited from the underlying architecture
714     this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
715     if (Triple.getArch() == llvm::Triple::arm) {
716       this->DescriptionString =
717           "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128";
718     } else if (Triple.getArch() == llvm::Triple::x86) {
719       this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
720     } else if (Triple.getArch() == llvm::Triple::x86_64) {
721       this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128";
722     } else if (Triple.getArch() == llvm::Triple::mipsel) {
723       // Handled on mips' setDescriptionString.
724     } else {
725       assert(Triple.getArch() == llvm::Triple::le32);
726       this->DescriptionString = "e-p:32:32-i64:64";
727     }
728   }
729 };
730 } // end anonymous namespace.
731 
732 //===----------------------------------------------------------------------===//
733 // Specific target implementations.
734 //===----------------------------------------------------------------------===//
735 
736 namespace {
737 // PPC abstract base class
738 class PPCTargetInfo : public TargetInfo {
739   static const Builtin::Info BuiltinInfo[];
740   static const char * const GCCRegNames[];
741   static const TargetInfo::GCCRegAlias GCCRegAliases[];
742   std::string CPU;
743 
744   // Target cpu features.
745   bool HasVSX;
746   bool HasP8Vector;
747   bool HasP8Crypto;
748   bool HasQPX;
749 
750 protected:
751   std::string ABI;
752 
753 public:
754   PPCTargetInfo(const llvm::Triple &Triple)
755     : TargetInfo(Triple), HasVSX(false), HasP8Vector(false),
756       HasP8Crypto(false), HasQPX(false) {
757     BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
758     LongDoubleWidth = LongDoubleAlign = 128;
759     LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
760   }
761 
762   /// \brief Flags for architecture specific defines.
763   typedef enum {
764     ArchDefineNone  = 0,
765     ArchDefineName  = 1 << 0, // <name> is substituted for arch name.
766     ArchDefinePpcgr = 1 << 1,
767     ArchDefinePpcsq = 1 << 2,
768     ArchDefine440   = 1 << 3,
769     ArchDefine603   = 1 << 4,
770     ArchDefine604   = 1 << 5,
771     ArchDefinePwr4  = 1 << 6,
772     ArchDefinePwr5  = 1 << 7,
773     ArchDefinePwr5x = 1 << 8,
774     ArchDefinePwr6  = 1 << 9,
775     ArchDefinePwr6x = 1 << 10,
776     ArchDefinePwr7  = 1 << 11,
777     ArchDefinePwr8  = 1 << 12,
778     ArchDefineA2    = 1 << 13,
779     ArchDefineA2q   = 1 << 14
780   } ArchDefineTypes;
781 
782   // Note: GCC recognizes the following additional cpus:
783   //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
784   //  821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
785   //  titan, rs64.
786   bool setCPU(const std::string &Name) override {
787     bool CPUKnown = llvm::StringSwitch<bool>(Name)
788       .Case("generic", true)
789       .Case("440", true)
790       .Case("450", true)
791       .Case("601", true)
792       .Case("602", true)
793       .Case("603", true)
794       .Case("603e", true)
795       .Case("603ev", true)
796       .Case("604", true)
797       .Case("604e", true)
798       .Case("620", true)
799       .Case("630", true)
800       .Case("g3", true)
801       .Case("7400", true)
802       .Case("g4", true)
803       .Case("7450", true)
804       .Case("g4+", true)
805       .Case("750", true)
806       .Case("970", true)
807       .Case("g5", true)
808       .Case("a2", true)
809       .Case("a2q", true)
810       .Case("e500mc", true)
811       .Case("e5500", true)
812       .Case("power3", true)
813       .Case("pwr3", true)
814       .Case("power4", true)
815       .Case("pwr4", true)
816       .Case("power5", true)
817       .Case("pwr5", true)
818       .Case("power5x", true)
819       .Case("pwr5x", true)
820       .Case("power6", true)
821       .Case("pwr6", true)
822       .Case("power6x", true)
823       .Case("pwr6x", true)
824       .Case("power7", true)
825       .Case("pwr7", true)
826       .Case("power8", true)
827       .Case("pwr8", true)
828       .Case("powerpc", true)
829       .Case("ppc", true)
830       .Case("powerpc64", true)
831       .Case("ppc64", true)
832       .Case("powerpc64le", true)
833       .Case("ppc64le", true)
834       .Default(false);
835 
836     if (CPUKnown)
837       CPU = Name;
838 
839     return CPUKnown;
840   }
841 
842 
843   StringRef getABI() const override { return ABI; }
844 
845   void getTargetBuiltins(const Builtin::Info *&Records,
846                          unsigned &NumRecords) const override {
847     Records = BuiltinInfo;
848     NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
849   }
850 
851   bool isCLZForZeroUndef() const override { return false; }
852 
853   void getTargetDefines(const LangOptions &Opts,
854                         MacroBuilder &Builder) const override;
855 
856   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
857 
858   bool handleTargetFeatures(std::vector<std::string> &Features,
859                             DiagnosticsEngine &Diags) override;
860   bool hasFeature(StringRef Feature) const override;
861 
862   void getGCCRegNames(const char * const *&Names,
863                       unsigned &NumNames) const override;
864   void getGCCRegAliases(const GCCRegAlias *&Aliases,
865                         unsigned &NumAliases) const override;
866   bool validateAsmConstraint(const char *&Name,
867                              TargetInfo::ConstraintInfo &Info) const override {
868     switch (*Name) {
869     default: return false;
870     case 'O': // Zero
871       break;
872     case 'b': // Base register
873     case 'f': // Floating point register
874       Info.setAllowsRegister();
875       break;
876     // FIXME: The following are added to allow parsing.
877     // I just took a guess at what the actions should be.
878     // Also, is more specific checking needed?  I.e. specific registers?
879     case 'd': // Floating point register (containing 64-bit value)
880     case 'v': // Altivec vector register
881       Info.setAllowsRegister();
882       break;
883     case 'w':
884       switch (Name[1]) {
885         case 'd':// VSX vector register to hold vector double data
886         case 'f':// VSX vector register to hold vector float data
887         case 's':// VSX vector register to hold scalar float data
888         case 'a':// Any VSX register
889         case 'c':// An individual CR bit
890           break;
891         default:
892           return false;
893       }
894       Info.setAllowsRegister();
895       Name++; // Skip over 'w'.
896       break;
897     case 'h': // `MQ', `CTR', or `LINK' register
898     case 'q': // `MQ' register
899     case 'c': // `CTR' register
900     case 'l': // `LINK' register
901     case 'x': // `CR' register (condition register) number 0
902     case 'y': // `CR' register (condition register)
903     case 'z': // `XER[CA]' carry bit (part of the XER register)
904       Info.setAllowsRegister();
905       break;
906     case 'I': // Signed 16-bit constant
907     case 'J': // Unsigned 16-bit constant shifted left 16 bits
908               //  (use `L' instead for SImode constants)
909     case 'K': // Unsigned 16-bit constant
910     case 'L': // Signed 16-bit constant shifted left 16 bits
911     case 'M': // Constant larger than 31
912     case 'N': // Exact power of 2
913     case 'P': // Constant whose negation is a signed 16-bit constant
914     case 'G': // Floating point constant that can be loaded into a
915               // register with one instruction per word
916     case 'H': // Integer/Floating point constant that can be loaded
917               // into a register using three instructions
918       break;
919     case 'm': // Memory operand. Note that on PowerPC targets, m can
920               // include addresses that update the base register. It
921               // is therefore only safe to use `m' in an asm statement
922               // if that asm statement accesses the operand exactly once.
923               // The asm statement must also use `%U<opno>' as a
924               // placeholder for the "update" flag in the corresponding
925               // load or store instruction. For example:
926               // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
927               // is correct but:
928               // asm ("st %1,%0" : "=m" (mem) : "r" (val));
929               // is not. Use es rather than m if you don't want the base
930               // register to be updated.
931     case 'e':
932       if (Name[1] != 's')
933           return false;
934               // es: A "stable" memory operand; that is, one which does not
935               // include any automodification of the base register. Unlike
936               // `m', this constraint can be used in asm statements that
937               // might access the operand several times, or that might not
938               // access it at all.
939       Info.setAllowsMemory();
940       Name++; // Skip over 'e'.
941       break;
942     case 'Q': // Memory operand that is an offset from a register (it is
943               // usually better to use `m' or `es' in asm statements)
944     case 'Z': // Memory operand that is an indexed or indirect from a
945               // register (it is usually better to use `m' or `es' in
946               // asm statements)
947       Info.setAllowsMemory();
948       Info.setAllowsRegister();
949       break;
950     case 'R': // AIX TOC entry
951     case 'a': // Address operand that is an indexed or indirect from a
952               // register (`p' is preferable for asm statements)
953     case 'S': // Constant suitable as a 64-bit mask operand
954     case 'T': // Constant suitable as a 32-bit mask operand
955     case 'U': // System V Release 4 small data area reference
956     case 't': // AND masks that can be performed by two rldic{l, r}
957               // instructions
958     case 'W': // Vector constant that does not require memory
959     case 'j': // Vector constant that is all zeros.
960       break;
961     // End FIXME.
962     }
963     return true;
964   }
965   std::string convertConstraint(const char *&Constraint) const override {
966     std::string R;
967     switch (*Constraint) {
968     case 'e':
969     case 'w':
970       // Two-character constraint; add "^" hint for later parsing.
971       R = std::string("^") + std::string(Constraint, 2);
972       Constraint++;
973       break;
974     default:
975       return TargetInfo::convertConstraint(Constraint);
976     }
977     return R;
978   }
979   const char *getClobbers() const override {
980     return "";
981   }
982   int getEHDataRegisterNumber(unsigned RegNo) const override {
983     if (RegNo == 0) return 3;
984     if (RegNo == 1) return 4;
985     return -1;
986   }
987 
988   bool hasSjLjLowering() const override {
989     return true;
990   }
991 };
992 
993 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
994 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
995 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
996                                               ALL_LANGUAGES },
997 #include "clang/Basic/BuiltinsPPC.def"
998 };
999 
1000 /// handleTargetFeatures - Perform initialization based on the user
1001 /// configured set of features.
1002 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
1003                                          DiagnosticsEngine &Diags) {
1004   for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
1005     // Ignore disabled features.
1006     if (Features[i][0] == '-')
1007       continue;
1008 
1009     StringRef Feature = StringRef(Features[i]).substr(1);
1010 
1011     if (Feature == "vsx") {
1012       HasVSX = true;
1013       continue;
1014     }
1015 
1016     if (Feature == "power8-vector") {
1017       HasP8Vector = true;
1018       continue;
1019     }
1020 
1021     if (Feature == "crypto") {
1022       HasP8Crypto = true;
1023       continue;
1024     }
1025 
1026     if (Feature == "qpx") {
1027       HasQPX = true;
1028       continue;
1029     }
1030 
1031     // TODO: Finish this list and add an assert that we've handled them
1032     // all.
1033   }
1034 
1035   return true;
1036 }
1037 
1038 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
1039 /// #defines that are not tied to a specific subtarget.
1040 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
1041                                      MacroBuilder &Builder) const {
1042   // Target identification.
1043   Builder.defineMacro("__ppc__");
1044   Builder.defineMacro("__PPC__");
1045   Builder.defineMacro("_ARCH_PPC");
1046   Builder.defineMacro("__powerpc__");
1047   Builder.defineMacro("__POWERPC__");
1048   if (PointerWidth == 64) {
1049     Builder.defineMacro("_ARCH_PPC64");
1050     Builder.defineMacro("__powerpc64__");
1051     Builder.defineMacro("__ppc64__");
1052     Builder.defineMacro("__PPC64__");
1053   }
1054 
1055   // Target properties.
1056   if (getTriple().getArch() == llvm::Triple::ppc64le) {
1057     Builder.defineMacro("_LITTLE_ENDIAN");
1058   } else {
1059     if (getTriple().getOS() != llvm::Triple::NetBSD &&
1060         getTriple().getOS() != llvm::Triple::OpenBSD)
1061       Builder.defineMacro("_BIG_ENDIAN");
1062   }
1063 
1064   // ABI options.
1065   if (ABI == "elfv1" || ABI == "elfv1-qpx")
1066     Builder.defineMacro("_CALL_ELF", "1");
1067   if (ABI == "elfv2")
1068     Builder.defineMacro("_CALL_ELF", "2");
1069 
1070   // Subtarget options.
1071   Builder.defineMacro("__NATURAL_ALIGNMENT__");
1072   Builder.defineMacro("__REGISTER_PREFIX__", "");
1073 
1074   // FIXME: Should be controlled by command line option.
1075   if (LongDoubleWidth == 128)
1076     Builder.defineMacro("__LONG_DOUBLE_128__");
1077 
1078   if (Opts.AltiVec) {
1079     Builder.defineMacro("__VEC__", "10206");
1080     Builder.defineMacro("__ALTIVEC__");
1081   }
1082 
1083   // CPU identification.
1084   ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1085     .Case("440",   ArchDefineName)
1086     .Case("450",   ArchDefineName | ArchDefine440)
1087     .Case("601",   ArchDefineName)
1088     .Case("602",   ArchDefineName | ArchDefinePpcgr)
1089     .Case("603",   ArchDefineName | ArchDefinePpcgr)
1090     .Case("603e",  ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1091     .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1092     .Case("604",   ArchDefineName | ArchDefinePpcgr)
1093     .Case("604e",  ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1094     .Case("620",   ArchDefineName | ArchDefinePpcgr)
1095     .Case("630",   ArchDefineName | ArchDefinePpcgr)
1096     .Case("7400",  ArchDefineName | ArchDefinePpcgr)
1097     .Case("7450",  ArchDefineName | ArchDefinePpcgr)
1098     .Case("750",   ArchDefineName | ArchDefinePpcgr)
1099     .Case("970",   ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1100                      | ArchDefinePpcsq)
1101     .Case("a2",    ArchDefineA2)
1102     .Case("a2q",   ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1103     .Case("pwr3",  ArchDefinePpcgr)
1104     .Case("pwr4",  ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1105     .Case("pwr5",  ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1106                      | ArchDefinePpcsq)
1107     .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1108                      | ArchDefinePpcgr | ArchDefinePpcsq)
1109     .Case("pwr6",  ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1110                      | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1111     .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1112                      | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1113                      | ArchDefinePpcsq)
1114     .Case("pwr7",  ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1115                      | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1116                      | ArchDefinePpcgr | ArchDefinePpcsq)
1117     .Case("pwr8",  ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1118                      | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1119                      | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1120     .Case("power3",  ArchDefinePpcgr)
1121     .Case("power4",  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1122     .Case("power5",  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1123                        | ArchDefinePpcsq)
1124     .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1125                        | ArchDefinePpcgr | ArchDefinePpcsq)
1126     .Case("power6",  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1127                        | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1128     .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1129                        | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1130                        | ArchDefinePpcsq)
1131     .Case("power7",  ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1132                        | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1133                        | ArchDefinePpcgr | ArchDefinePpcsq)
1134     .Case("power8",  ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1135                        | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1136                        | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1137     .Default(ArchDefineNone);
1138 
1139   if (defs & ArchDefineName)
1140     Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1141   if (defs & ArchDefinePpcgr)
1142     Builder.defineMacro("_ARCH_PPCGR");
1143   if (defs & ArchDefinePpcsq)
1144     Builder.defineMacro("_ARCH_PPCSQ");
1145   if (defs & ArchDefine440)
1146     Builder.defineMacro("_ARCH_440");
1147   if (defs & ArchDefine603)
1148     Builder.defineMacro("_ARCH_603");
1149   if (defs & ArchDefine604)
1150     Builder.defineMacro("_ARCH_604");
1151   if (defs & ArchDefinePwr4)
1152     Builder.defineMacro("_ARCH_PWR4");
1153   if (defs & ArchDefinePwr5)
1154     Builder.defineMacro("_ARCH_PWR5");
1155   if (defs & ArchDefinePwr5x)
1156     Builder.defineMacro("_ARCH_PWR5X");
1157   if (defs & ArchDefinePwr6)
1158     Builder.defineMacro("_ARCH_PWR6");
1159   if (defs & ArchDefinePwr6x)
1160     Builder.defineMacro("_ARCH_PWR6X");
1161   if (defs & ArchDefinePwr7)
1162     Builder.defineMacro("_ARCH_PWR7");
1163   if (defs & ArchDefinePwr8)
1164     Builder.defineMacro("_ARCH_PWR8");
1165   if (defs & ArchDefineA2)
1166     Builder.defineMacro("_ARCH_A2");
1167   if (defs & ArchDefineA2q) {
1168     Builder.defineMacro("_ARCH_A2Q");
1169     Builder.defineMacro("_ARCH_QP");
1170   }
1171 
1172   if (getTriple().getVendor() == llvm::Triple::BGQ) {
1173     Builder.defineMacro("__bg__");
1174     Builder.defineMacro("__THW_BLUEGENE__");
1175     Builder.defineMacro("__bgq__");
1176     Builder.defineMacro("__TOS_BGQ__");
1177   }
1178 
1179   if (HasVSX)
1180     Builder.defineMacro("__VSX__");
1181   if (HasP8Vector)
1182     Builder.defineMacro("__POWER8_VECTOR__");
1183   if (HasP8Crypto)
1184     Builder.defineMacro("__CRYPTO__");
1185 
1186   // FIXME: The following are not yet generated here by Clang, but are
1187   //        generated by GCC:
1188   //
1189   //   _SOFT_FLOAT_
1190   //   __RECIP_PRECISION__
1191   //   __APPLE_ALTIVEC__
1192   //   __RECIP__
1193   //   __RECIPF__
1194   //   __RSQRTE__
1195   //   __RSQRTEF__
1196   //   _SOFT_DOUBLE_
1197   //   __NO_LWSYNC__
1198   //   __HAVE_BSWAP__
1199   //   __LONGDOUBLE128
1200   //   __CMODEL_MEDIUM__
1201   //   __CMODEL_LARGE__
1202   //   _CALL_SYSV
1203   //   _CALL_DARWIN
1204   //   __NO_FPRS__
1205 }
1206 
1207 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1208   Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1209     .Case("7400", true)
1210     .Case("g4", true)
1211     .Case("7450", true)
1212     .Case("g4+", true)
1213     .Case("970", true)
1214     .Case("g5", true)
1215     .Case("pwr6", true)
1216     .Case("pwr7", true)
1217     .Case("pwr8", true)
1218     .Case("ppc64", true)
1219     .Case("ppc64le", true)
1220     .Default(false);
1221 
1222   Features["qpx"] = (CPU == "a2q");
1223   Features["crypto"] = llvm::StringSwitch<bool>(CPU)
1224     .Case("ppc64le", true)
1225     .Case("pwr8", true)
1226     .Default(false);
1227   Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
1228     .Case("ppc64le", true)
1229     .Case("pwr8", true)
1230     .Default(false);
1231 }
1232 
1233 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1234   return llvm::StringSwitch<bool>(Feature)
1235     .Case("powerpc", true)
1236     .Case("vsx", HasVSX)
1237     .Case("power8-vector", HasP8Vector)
1238     .Case("crypto", HasP8Crypto)
1239     .Case("qpx", HasQPX)
1240     .Default(false);
1241 }
1242 
1243 const char * const PPCTargetInfo::GCCRegNames[] = {
1244   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1245   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1246   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1247   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1248   "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1249   "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1250   "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1251   "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1252   "mq", "lr", "ctr", "ap",
1253   "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1254   "xer",
1255   "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1256   "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1257   "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1258   "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1259   "vrsave", "vscr",
1260   "spe_acc", "spefscr",
1261   "sfp"
1262 };
1263 
1264 void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1265                                    unsigned &NumNames) const {
1266   Names = GCCRegNames;
1267   NumNames = llvm::array_lengthof(GCCRegNames);
1268 }
1269 
1270 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1271   // While some of these aliases do map to different registers
1272   // they still share the same register name.
1273   { { "0" }, "r0" },
1274   { { "1"}, "r1" },
1275   { { "2" }, "r2" },
1276   { { "3" }, "r3" },
1277   { { "4" }, "r4" },
1278   { { "5" }, "r5" },
1279   { { "6" }, "r6" },
1280   { { "7" }, "r7" },
1281   { { "8" }, "r8" },
1282   { { "9" }, "r9" },
1283   { { "10" }, "r10" },
1284   { { "11" }, "r11" },
1285   { { "12" }, "r12" },
1286   { { "13" }, "r13" },
1287   { { "14" }, "r14" },
1288   { { "15" }, "r15" },
1289   { { "16" }, "r16" },
1290   { { "17" }, "r17" },
1291   { { "18" }, "r18" },
1292   { { "19" }, "r19" },
1293   { { "20" }, "r20" },
1294   { { "21" }, "r21" },
1295   { { "22" }, "r22" },
1296   { { "23" }, "r23" },
1297   { { "24" }, "r24" },
1298   { { "25" }, "r25" },
1299   { { "26" }, "r26" },
1300   { { "27" }, "r27" },
1301   { { "28" }, "r28" },
1302   { { "29" }, "r29" },
1303   { { "30" }, "r30" },
1304   { { "31" }, "r31" },
1305   { { "fr0" }, "f0" },
1306   { { "fr1" }, "f1" },
1307   { { "fr2" }, "f2" },
1308   { { "fr3" }, "f3" },
1309   { { "fr4" }, "f4" },
1310   { { "fr5" }, "f5" },
1311   { { "fr6" }, "f6" },
1312   { { "fr7" }, "f7" },
1313   { { "fr8" }, "f8" },
1314   { { "fr9" }, "f9" },
1315   { { "fr10" }, "f10" },
1316   { { "fr11" }, "f11" },
1317   { { "fr12" }, "f12" },
1318   { { "fr13" }, "f13" },
1319   { { "fr14" }, "f14" },
1320   { { "fr15" }, "f15" },
1321   { { "fr16" }, "f16" },
1322   { { "fr17" }, "f17" },
1323   { { "fr18" }, "f18" },
1324   { { "fr19" }, "f19" },
1325   { { "fr20" }, "f20" },
1326   { { "fr21" }, "f21" },
1327   { { "fr22" }, "f22" },
1328   { { "fr23" }, "f23" },
1329   { { "fr24" }, "f24" },
1330   { { "fr25" }, "f25" },
1331   { { "fr26" }, "f26" },
1332   { { "fr27" }, "f27" },
1333   { { "fr28" }, "f28" },
1334   { { "fr29" }, "f29" },
1335   { { "fr30" }, "f30" },
1336   { { "fr31" }, "f31" },
1337   { { "cc" }, "cr0" },
1338 };
1339 
1340 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1341                                      unsigned &NumAliases) const {
1342   Aliases = GCCRegAliases;
1343   NumAliases = llvm::array_lengthof(GCCRegAliases);
1344 }
1345 } // end anonymous namespace.
1346 
1347 namespace {
1348 class PPC32TargetInfo : public PPCTargetInfo {
1349 public:
1350   PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1351     DescriptionString = "E-m:e-p:32:32-i64:64-n32";
1352 
1353     switch (getTriple().getOS()) {
1354     case llvm::Triple::Linux:
1355     case llvm::Triple::FreeBSD:
1356     case llvm::Triple::NetBSD:
1357       SizeType = UnsignedInt;
1358       PtrDiffType = SignedInt;
1359       IntPtrType = SignedInt;
1360       break;
1361     default:
1362       break;
1363     }
1364 
1365     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1366       LongDoubleWidth = LongDoubleAlign = 64;
1367       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1368     }
1369 
1370     // PPC32 supports atomics up to 4 bytes.
1371     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1372   }
1373 
1374   BuiltinVaListKind getBuiltinVaListKind() const override {
1375     // This is the ELF definition, and is overridden by the Darwin sub-target
1376     return TargetInfo::PowerABIBuiltinVaList;
1377   }
1378 };
1379 } // end anonymous namespace.
1380 
1381 // Note: ABI differences may eventually require us to have a separate
1382 // TargetInfo for little endian.
1383 namespace {
1384 class PPC64TargetInfo : public PPCTargetInfo {
1385 public:
1386   PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1387     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1388     IntMaxType = SignedLong;
1389     Int64Type = SignedLong;
1390 
1391     if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1392       DescriptionString = "e-m:e-i64:64-n32:64";
1393       ABI = "elfv2";
1394     } else {
1395       DescriptionString = "E-m:e-i64:64-n32:64";
1396       ABI = "elfv1";
1397     }
1398 
1399     switch (getTriple().getOS()) {
1400     case llvm::Triple::FreeBSD:
1401       LongDoubleWidth = LongDoubleAlign = 64;
1402       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1403       break;
1404     case llvm::Triple::NetBSD:
1405       IntMaxType = SignedLongLong;
1406       Int64Type = SignedLongLong;
1407       break;
1408     default:
1409       break;
1410     }
1411 
1412     // PPC64 supports atomics up to 8 bytes.
1413     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1414   }
1415   BuiltinVaListKind getBuiltinVaListKind() const override {
1416     return TargetInfo::CharPtrBuiltinVaList;
1417   }
1418   // PPC64 Linux-specifc ABI options.
1419   bool setABI(const std::string &Name) override {
1420     if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
1421       ABI = Name;
1422       return true;
1423     }
1424     return false;
1425   }
1426 };
1427 } // end anonymous namespace.
1428 
1429 
1430 namespace {
1431 class DarwinPPC32TargetInfo :
1432   public DarwinTargetInfo<PPC32TargetInfo> {
1433 public:
1434   DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1435       : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1436     HasAlignMac68kSupport = true;
1437     BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1438     PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1439     LongLongAlign = 32;
1440     SuitableAlign = 128;
1441     DescriptionString = "E-m:o-p:32:32-f64:32:64-n32";
1442   }
1443   BuiltinVaListKind getBuiltinVaListKind() const override {
1444     return TargetInfo::CharPtrBuiltinVaList;
1445   }
1446 };
1447 
1448 class DarwinPPC64TargetInfo :
1449   public DarwinTargetInfo<PPC64TargetInfo> {
1450 public:
1451   DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1452       : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1453     HasAlignMac68kSupport = true;
1454     SuitableAlign = 128;
1455     DescriptionString = "E-m:o-i64:64-n32:64";
1456   }
1457 };
1458 } // end anonymous namespace.
1459 
1460 namespace {
1461   static const unsigned NVPTXAddrSpaceMap[] = {
1462     1,    // opencl_global
1463     3,    // opencl_local
1464     4,    // opencl_constant
1465     // FIXME: generic has to be added to the target
1466     0,    // opencl_generic
1467     1,    // cuda_device
1468     4,    // cuda_constant
1469     3,    // cuda_shared
1470   };
1471   class NVPTXTargetInfo : public TargetInfo {
1472     static const char * const GCCRegNames[];
1473     static const Builtin::Info BuiltinInfo[];
1474 
1475   // The GPU profiles supported by the NVPTX backend
1476   enum GPUKind {
1477     GK_NONE,
1478     GK_SM20,
1479     GK_SM21,
1480     GK_SM30,
1481     GK_SM35,
1482   } GPU;
1483 
1484   public:
1485     NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1486       BigEndian = false;
1487       TLSSupported = false;
1488       LongWidth = LongAlign = 64;
1489       AddrSpaceMap = &NVPTXAddrSpaceMap;
1490       UseAddrSpaceMapMangling = true;
1491       // Define available target features
1492       // These must be defined in sorted order!
1493       NoAsmVariants = true;
1494       // Set the default GPU to sm20
1495       GPU = GK_SM20;
1496     }
1497     void getTargetDefines(const LangOptions &Opts,
1498                           MacroBuilder &Builder) const override {
1499       Builder.defineMacro("__PTX__");
1500       Builder.defineMacro("__NVPTX__");
1501       if (Opts.CUDAIsDevice) {
1502         // Set __CUDA_ARCH__ for the GPU specified.
1503         std::string CUDAArchCode;
1504         switch (GPU) {
1505         case GK_SM20:
1506           CUDAArchCode = "200";
1507           break;
1508         case GK_SM21:
1509           CUDAArchCode = "210";
1510           break;
1511         case GK_SM30:
1512           CUDAArchCode = "300";
1513           break;
1514         case GK_SM35:
1515           CUDAArchCode = "350";
1516           break;
1517         default:
1518           llvm_unreachable("Unhandled target CPU");
1519         }
1520         Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1521       }
1522     }
1523     void getTargetBuiltins(const Builtin::Info *&Records,
1524                            unsigned &NumRecords) const override {
1525       Records = BuiltinInfo;
1526       NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1527     }
1528     bool hasFeature(StringRef Feature) const override {
1529       return Feature == "ptx" || Feature == "nvptx";
1530     }
1531 
1532     void getGCCRegNames(const char * const *&Names,
1533                         unsigned &NumNames) const override;
1534     void getGCCRegAliases(const GCCRegAlias *&Aliases,
1535                                   unsigned &NumAliases) const override {
1536       // No aliases.
1537       Aliases = nullptr;
1538       NumAliases = 0;
1539     }
1540     bool
1541     validateAsmConstraint(const char *&Name,
1542                           TargetInfo::ConstraintInfo &Info) const override {
1543       switch (*Name) {
1544       default: return false;
1545       case 'c':
1546       case 'h':
1547       case 'r':
1548       case 'l':
1549       case 'f':
1550       case 'd':
1551         Info.setAllowsRegister();
1552         return true;
1553       }
1554     }
1555     const char *getClobbers() const override {
1556       // FIXME: Is this really right?
1557       return "";
1558     }
1559     BuiltinVaListKind getBuiltinVaListKind() const override {
1560       // FIXME: implement
1561       return TargetInfo::CharPtrBuiltinVaList;
1562     }
1563     bool setCPU(const std::string &Name) override {
1564       GPU = llvm::StringSwitch<GPUKind>(Name)
1565                 .Case("sm_20", GK_SM20)
1566                 .Case("sm_21", GK_SM21)
1567                 .Case("sm_30", GK_SM30)
1568                 .Case("sm_35", GK_SM35)
1569                 .Default(GK_NONE);
1570 
1571       return GPU != GK_NONE;
1572     }
1573   };
1574 
1575   const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1576 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1577 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1578                                               ALL_LANGUAGES },
1579 #include "clang/Basic/BuiltinsNVPTX.def"
1580   };
1581 
1582   const char * const NVPTXTargetInfo::GCCRegNames[] = {
1583     "r0"
1584   };
1585 
1586   void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1587                                      unsigned &NumNames) const {
1588     Names = GCCRegNames;
1589     NumNames = llvm::array_lengthof(GCCRegNames);
1590   }
1591 
1592   class NVPTX32TargetInfo : public NVPTXTargetInfo {
1593   public:
1594     NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1595       PointerWidth = PointerAlign = 32;
1596       SizeType     = PtrDiffType = TargetInfo::UnsignedInt;
1597       IntPtrType = TargetInfo::SignedInt;
1598       DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
1599   }
1600   };
1601 
1602   class NVPTX64TargetInfo : public NVPTXTargetInfo {
1603   public:
1604     NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1605       PointerWidth = PointerAlign = 64;
1606       SizeType     = PtrDiffType = TargetInfo::UnsignedLongLong;
1607       IntPtrType = TargetInfo::SignedLongLong;
1608       DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64";
1609   }
1610   };
1611 }
1612 
1613 namespace {
1614 
1615 static const unsigned R600AddrSpaceMap[] = {
1616   1,    // opencl_global
1617   3,    // opencl_local
1618   2,    // opencl_constant
1619   4,    // opencl_generic
1620   1,    // cuda_device
1621   2,    // cuda_constant
1622   3     // cuda_shared
1623 };
1624 
1625 // If you edit the description strings, make sure you update
1626 // getPointerWidthV().
1627 
1628 static const char *DescriptionStringR600 =
1629   "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1630   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1631 
1632 static const char *DescriptionStringR600DoubleOps =
1633   "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1634   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1635 
1636 static const char *DescriptionStringSI =
1637   "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"
1638   "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1639   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1640 
1641 class R600TargetInfo : public TargetInfo {
1642   static const Builtin::Info BuiltinInfo[];
1643 
1644   /// \brief The GPU profiles supported by the R600 target.
1645   enum GPUKind {
1646     GK_NONE,
1647     GK_R600,
1648     GK_R600_DOUBLE_OPS,
1649     GK_R700,
1650     GK_R700_DOUBLE_OPS,
1651     GK_EVERGREEN,
1652     GK_EVERGREEN_DOUBLE_OPS,
1653     GK_NORTHERN_ISLANDS,
1654     GK_CAYMAN,
1655     GK_SOUTHERN_ISLANDS,
1656     GK_SEA_ISLANDS
1657   } GPU;
1658 
1659 public:
1660   R600TargetInfo(const llvm::Triple &Triple)
1661       : TargetInfo(Triple) {
1662 
1663     if (Triple.getArch() == llvm::Triple::amdgcn) {
1664       DescriptionString = DescriptionStringSI;
1665       GPU = GK_SOUTHERN_ISLANDS;
1666     } else {
1667       DescriptionString = DescriptionStringR600;
1668       GPU = GK_R600;
1669     }
1670     AddrSpaceMap = &R600AddrSpaceMap;
1671     UseAddrSpaceMapMangling = true;
1672   }
1673 
1674   uint64_t getPointerWidthV(unsigned AddrSpace) const override {
1675     if (GPU <= GK_CAYMAN)
1676       return 32;
1677 
1678     switch(AddrSpace) {
1679       default:
1680         return 64;
1681       case 0:
1682       case 3:
1683       case 5:
1684         return 32;
1685     }
1686   }
1687 
1688   const char * getClobbers() const override {
1689     return "";
1690   }
1691 
1692   void getGCCRegNames(const char * const *&Names,
1693                       unsigned &numNames) const override {
1694     Names = nullptr;
1695     numNames = 0;
1696   }
1697 
1698   void getGCCRegAliases(const GCCRegAlias *&Aliases,
1699                         unsigned &NumAliases) const override {
1700     Aliases = nullptr;
1701     NumAliases = 0;
1702   }
1703 
1704   bool validateAsmConstraint(const char *&Name,
1705                              TargetInfo::ConstraintInfo &info) const override {
1706     return true;
1707   }
1708 
1709   void getTargetBuiltins(const Builtin::Info *&Records,
1710                          unsigned &NumRecords) const override {
1711     Records = BuiltinInfo;
1712     NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin;
1713   }
1714 
1715   void getTargetDefines(const LangOptions &Opts,
1716                         MacroBuilder &Builder) const override {
1717     Builder.defineMacro("__R600__");
1718     if (GPU >= GK_SOUTHERN_ISLANDS && Opts.OpenCL)
1719       Builder.defineMacro("cl_khr_fp64");
1720   }
1721 
1722   BuiltinVaListKind getBuiltinVaListKind() const override {
1723     return TargetInfo::CharPtrBuiltinVaList;
1724   }
1725 
1726   bool setCPU(const std::string &Name) override {
1727     GPU = llvm::StringSwitch<GPUKind>(Name)
1728       .Case("r600" ,    GK_R600)
1729       .Case("rv610",    GK_R600)
1730       .Case("rv620",    GK_R600)
1731       .Case("rv630",    GK_R600)
1732       .Case("rv635",    GK_R600)
1733       .Case("rs780",    GK_R600)
1734       .Case("rs880",    GK_R600)
1735       .Case("rv670",    GK_R600_DOUBLE_OPS)
1736       .Case("rv710",    GK_R700)
1737       .Case("rv730",    GK_R700)
1738       .Case("rv740",    GK_R700_DOUBLE_OPS)
1739       .Case("rv770",    GK_R700_DOUBLE_OPS)
1740       .Case("palm",     GK_EVERGREEN)
1741       .Case("cedar",    GK_EVERGREEN)
1742       .Case("sumo",     GK_EVERGREEN)
1743       .Case("sumo2",    GK_EVERGREEN)
1744       .Case("redwood",  GK_EVERGREEN)
1745       .Case("juniper",  GK_EVERGREEN)
1746       .Case("hemlock",  GK_EVERGREEN_DOUBLE_OPS)
1747       .Case("cypress",  GK_EVERGREEN_DOUBLE_OPS)
1748       .Case("barts",    GK_NORTHERN_ISLANDS)
1749       .Case("turks",    GK_NORTHERN_ISLANDS)
1750       .Case("caicos",   GK_NORTHERN_ISLANDS)
1751       .Case("cayman",   GK_CAYMAN)
1752       .Case("aruba",    GK_CAYMAN)
1753       .Case("tahiti",   GK_SOUTHERN_ISLANDS)
1754       .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1755       .Case("verde",    GK_SOUTHERN_ISLANDS)
1756       .Case("oland",    GK_SOUTHERN_ISLANDS)
1757       .Case("hainan",   GK_SOUTHERN_ISLANDS)
1758       .Case("bonaire",  GK_SEA_ISLANDS)
1759       .Case("kabini",   GK_SEA_ISLANDS)
1760       .Case("kaveri",   GK_SEA_ISLANDS)
1761       .Case("hawaii",   GK_SEA_ISLANDS)
1762       .Case("mullins",  GK_SEA_ISLANDS)
1763       .Default(GK_NONE);
1764 
1765     if (GPU == GK_NONE) {
1766       return false;
1767     }
1768 
1769     // Set the correct data layout
1770     switch (GPU) {
1771     case GK_NONE:
1772     case GK_R600:
1773     case GK_R700:
1774     case GK_EVERGREEN:
1775     case GK_NORTHERN_ISLANDS:
1776       DescriptionString = DescriptionStringR600;
1777       break;
1778     case GK_R600_DOUBLE_OPS:
1779     case GK_R700_DOUBLE_OPS:
1780     case GK_EVERGREEN_DOUBLE_OPS:
1781     case GK_CAYMAN:
1782       DescriptionString = DescriptionStringR600DoubleOps;
1783       break;
1784     case GK_SOUTHERN_ISLANDS:
1785     case GK_SEA_ISLANDS:
1786       DescriptionString = DescriptionStringSI;
1787       break;
1788     }
1789 
1790     return true;
1791   }
1792 };
1793 
1794 const Builtin::Info R600TargetInfo::BuiltinInfo[] = {
1795 #define BUILTIN(ID, TYPE, ATTRS)                \
1796   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1797 #include "clang/Basic/BuiltinsR600.def"
1798 };
1799 
1800 } // end anonymous namespace
1801 
1802 namespace {
1803 // Namespace for x86 abstract base class
1804 const Builtin::Info BuiltinInfo[] = {
1805 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1806 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1807                                               ALL_LANGUAGES },
1808 #include "clang/Basic/BuiltinsX86.def"
1809 };
1810 
1811 static const char* const GCCRegNames[] = {
1812   "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1813   "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1814   "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1815   "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1816   "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1817   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1818   "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1819   "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1820   "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1821 };
1822 
1823 const TargetInfo::AddlRegName AddlRegNames[] = {
1824   { { "al", "ah", "eax", "rax" }, 0 },
1825   { { "bl", "bh", "ebx", "rbx" }, 3 },
1826   { { "cl", "ch", "ecx", "rcx" }, 2 },
1827   { { "dl", "dh", "edx", "rdx" }, 1 },
1828   { { "esi", "rsi" }, 4 },
1829   { { "edi", "rdi" }, 5 },
1830   { { "esp", "rsp" }, 7 },
1831   { { "ebp", "rbp" }, 6 },
1832 };
1833 
1834 // X86 target abstract base class; x86-32 and x86-64 are very close, so
1835 // most of the implementation can be shared.
1836 class X86TargetInfo : public TargetInfo {
1837   enum X86SSEEnum {
1838     NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
1839   } SSELevel;
1840   enum MMX3DNowEnum {
1841     NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1842   } MMX3DNowLevel;
1843   enum XOPEnum {
1844     NoXOP,
1845     SSE4A,
1846     FMA4,
1847     XOP
1848   } XOPLevel;
1849 
1850   bool HasAES;
1851   bool HasPCLMUL;
1852   bool HasLZCNT;
1853   bool HasRDRND;
1854   bool HasFSGSBASE;
1855   bool HasBMI;
1856   bool HasBMI2;
1857   bool HasPOPCNT;
1858   bool HasRTM;
1859   bool HasPRFCHW;
1860   bool HasRDSEED;
1861   bool HasADX;
1862   bool HasTBM;
1863   bool HasFMA;
1864   bool HasF16C;
1865   bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW,
1866       HasAVX512VL;
1867   bool HasSHA;
1868   bool HasCX16;
1869 
1870   /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1871   ///
1872   /// Each enumeration represents a particular CPU supported by Clang. These
1873   /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1874   enum CPUKind {
1875     CK_Generic,
1876 
1877     /// \name i386
1878     /// i386-generation processors.
1879     //@{
1880     CK_i386,
1881     //@}
1882 
1883     /// \name i486
1884     /// i486-generation processors.
1885     //@{
1886     CK_i486,
1887     CK_WinChipC6,
1888     CK_WinChip2,
1889     CK_C3,
1890     //@}
1891 
1892     /// \name i586
1893     /// i586-generation processors, P5 microarchitecture based.
1894     //@{
1895     CK_i586,
1896     CK_Pentium,
1897     CK_PentiumMMX,
1898     //@}
1899 
1900     /// \name i686
1901     /// i686-generation processors, P6 / Pentium M microarchitecture based.
1902     //@{
1903     CK_i686,
1904     CK_PentiumPro,
1905     CK_Pentium2,
1906     CK_Pentium3,
1907     CK_Pentium3M,
1908     CK_PentiumM,
1909     CK_C3_2,
1910 
1911     /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1912     /// Clang however has some logic to suport this.
1913     // FIXME: Warn, deprecate, and potentially remove this.
1914     CK_Yonah,
1915     //@}
1916 
1917     /// \name Netburst
1918     /// Netburst microarchitecture based processors.
1919     //@{
1920     CK_Pentium4,
1921     CK_Pentium4M,
1922     CK_Prescott,
1923     CK_Nocona,
1924     //@}
1925 
1926     /// \name Core
1927     /// Core microarchitecture based processors.
1928     //@{
1929     CK_Core2,
1930 
1931     /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1932     /// codename which GCC no longer accepts as an option to -march, but Clang
1933     /// has some logic for recognizing it.
1934     // FIXME: Warn, deprecate, and potentially remove this.
1935     CK_Penryn,
1936     //@}
1937 
1938     /// \name Atom
1939     /// Atom processors
1940     //@{
1941     CK_Bonnell,
1942     CK_Silvermont,
1943     //@}
1944 
1945     /// \name Nehalem
1946     /// Nehalem microarchitecture based processors.
1947     CK_Nehalem,
1948 
1949     /// \name Westmere
1950     /// Westmere microarchitecture based processors.
1951     CK_Westmere,
1952 
1953     /// \name Sandy Bridge
1954     /// Sandy Bridge microarchitecture based processors.
1955     CK_SandyBridge,
1956 
1957     /// \name Ivy Bridge
1958     /// Ivy Bridge microarchitecture based processors.
1959     CK_IvyBridge,
1960 
1961     /// \name Haswell
1962     /// Haswell microarchitecture based processors.
1963     CK_Haswell,
1964 
1965     /// \name Broadwell
1966     /// Broadwell microarchitecture based processors.
1967     CK_Broadwell,
1968 
1969     /// \name Skylake
1970     /// Skylake microarchitecture based processors.
1971     CK_Skylake,
1972 
1973     /// \name Knights Landing
1974     /// Knights Landing processor.
1975     CK_KNL,
1976 
1977     /// \name K6
1978     /// K6 architecture processors.
1979     //@{
1980     CK_K6,
1981     CK_K6_2,
1982     CK_K6_3,
1983     //@}
1984 
1985     /// \name K7
1986     /// K7 architecture processors.
1987     //@{
1988     CK_Athlon,
1989     CK_AthlonThunderbird,
1990     CK_Athlon4,
1991     CK_AthlonXP,
1992     CK_AthlonMP,
1993     //@}
1994 
1995     /// \name K8
1996     /// K8 architecture processors.
1997     //@{
1998     CK_Athlon64,
1999     CK_Athlon64SSE3,
2000     CK_AthlonFX,
2001     CK_K8,
2002     CK_K8SSE3,
2003     CK_Opteron,
2004     CK_OpteronSSE3,
2005     CK_AMDFAM10,
2006     //@}
2007 
2008     /// \name Bobcat
2009     /// Bobcat architecture processors.
2010     //@{
2011     CK_BTVER1,
2012     CK_BTVER2,
2013     //@}
2014 
2015     /// \name Bulldozer
2016     /// Bulldozer architecture processors.
2017     //@{
2018     CK_BDVER1,
2019     CK_BDVER2,
2020     CK_BDVER3,
2021     CK_BDVER4,
2022     //@}
2023 
2024     /// This specification is deprecated and will be removed in the future.
2025     /// Users should prefer \see CK_K8.
2026     // FIXME: Warn on this when the CPU is set to it.
2027     //@{
2028     CK_x86_64,
2029     //@}
2030 
2031     /// \name Geode
2032     /// Geode processors.
2033     //@{
2034     CK_Geode
2035     //@}
2036   } CPU;
2037 
2038   enum FPMathKind {
2039     FP_Default,
2040     FP_SSE,
2041     FP_387
2042   } FPMath;
2043 
2044 public:
2045   X86TargetInfo(const llvm::Triple &Triple)
2046       : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
2047         XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
2048         HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false),
2049         HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false),
2050         HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false),
2051         HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false),
2052         HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false),
2053         HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) {
2054     BigEndian = false;
2055     LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
2056   }
2057   unsigned getFloatEvalMethod() const override {
2058     // X87 evaluates with 80 bits "long double" precision.
2059     return SSELevel == NoSSE ? 2 : 0;
2060   }
2061   void getTargetBuiltins(const Builtin::Info *&Records,
2062                                  unsigned &NumRecords) const override {
2063     Records = BuiltinInfo;
2064     NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
2065   }
2066   void getGCCRegNames(const char * const *&Names,
2067                       unsigned &NumNames) const override {
2068     Names = GCCRegNames;
2069     NumNames = llvm::array_lengthof(GCCRegNames);
2070   }
2071   void getGCCRegAliases(const GCCRegAlias *&Aliases,
2072                         unsigned &NumAliases) const override {
2073     Aliases = nullptr;
2074     NumAliases = 0;
2075   }
2076   void getGCCAddlRegNames(const AddlRegName *&Names,
2077                           unsigned &NumNames) const override {
2078     Names = AddlRegNames;
2079     NumNames = llvm::array_lengthof(AddlRegNames);
2080   }
2081   bool validateAsmConstraint(const char *&Name,
2082                              TargetInfo::ConstraintInfo &info) const override;
2083 
2084   bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
2085 
2086   bool validateInputSize(StringRef Constraint, unsigned Size) const override;
2087 
2088   virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
2089 
2090   std::string convertConstraint(const char *&Constraint) const override;
2091   const char *getClobbers() const override {
2092     return "~{dirflag},~{fpsr},~{flags}";
2093   }
2094   void getTargetDefines(const LangOptions &Opts,
2095                         MacroBuilder &Builder) const override;
2096   static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
2097                           bool Enabled);
2098   static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
2099                           bool Enabled);
2100   static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2101                           bool Enabled);
2102   void setFeatureEnabled(llvm::StringMap<bool> &Features,
2103                          StringRef Name, bool Enabled) const override {
2104     setFeatureEnabledImpl(Features, Name, Enabled);
2105   }
2106   // This exists purely to cut down on the number of virtual calls in
2107   // getDefaultFeatures which calls this repeatedly.
2108   static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2109                                     StringRef Name, bool Enabled);
2110   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
2111   bool hasFeature(StringRef Feature) const override;
2112   bool handleTargetFeatures(std::vector<std::string> &Features,
2113                             DiagnosticsEngine &Diags) override;
2114   StringRef getABI() const override {
2115     if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
2116       return "avx";
2117     else if (getTriple().getArch() == llvm::Triple::x86 &&
2118              MMX3DNowLevel == NoMMX3DNow)
2119       return "no-mmx";
2120     return "";
2121   }
2122   bool setCPU(const std::string &Name) override {
2123     CPU = llvm::StringSwitch<CPUKind>(Name)
2124       .Case("i386", CK_i386)
2125       .Case("i486", CK_i486)
2126       .Case("winchip-c6", CK_WinChipC6)
2127       .Case("winchip2", CK_WinChip2)
2128       .Case("c3", CK_C3)
2129       .Case("i586", CK_i586)
2130       .Case("pentium", CK_Pentium)
2131       .Case("pentium-mmx", CK_PentiumMMX)
2132       .Case("i686", CK_i686)
2133       .Case("pentiumpro", CK_PentiumPro)
2134       .Case("pentium2", CK_Pentium2)
2135       .Case("pentium3", CK_Pentium3)
2136       .Case("pentium3m", CK_Pentium3M)
2137       .Case("pentium-m", CK_PentiumM)
2138       .Case("c3-2", CK_C3_2)
2139       .Case("yonah", CK_Yonah)
2140       .Case("pentium4", CK_Pentium4)
2141       .Case("pentium4m", CK_Pentium4M)
2142       .Case("prescott", CK_Prescott)
2143       .Case("nocona", CK_Nocona)
2144       .Case("core2", CK_Core2)
2145       .Case("penryn", CK_Penryn)
2146       .Case("bonnell", CK_Bonnell)
2147       .Case("atom", CK_Bonnell) // Legacy name.
2148       .Case("silvermont", CK_Silvermont)
2149       .Case("slm", CK_Silvermont) // Legacy name.
2150       .Case("nehalem", CK_Nehalem)
2151       .Case("corei7", CK_Nehalem) // Legacy name.
2152       .Case("westmere", CK_Westmere)
2153       .Case("sandybridge", CK_SandyBridge)
2154       .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2155       .Case("ivybridge", CK_IvyBridge)
2156       .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2157       .Case("haswell", CK_Haswell)
2158       .Case("core-avx2", CK_Haswell) // Legacy name.
2159       .Case("broadwell", CK_Broadwell)
2160       .Case("skylake", CK_Skylake)
2161       .Case("skx", CK_Skylake) // Legacy name.
2162       .Case("knl", CK_KNL)
2163       .Case("k6", CK_K6)
2164       .Case("k6-2", CK_K6_2)
2165       .Case("k6-3", CK_K6_3)
2166       .Case("athlon", CK_Athlon)
2167       .Case("athlon-tbird", CK_AthlonThunderbird)
2168       .Case("athlon-4", CK_Athlon4)
2169       .Case("athlon-xp", CK_AthlonXP)
2170       .Case("athlon-mp", CK_AthlonMP)
2171       .Case("athlon64", CK_Athlon64)
2172       .Case("athlon64-sse3", CK_Athlon64SSE3)
2173       .Case("athlon-fx", CK_AthlonFX)
2174       .Case("k8", CK_K8)
2175       .Case("k8-sse3", CK_K8SSE3)
2176       .Case("opteron", CK_Opteron)
2177       .Case("opteron-sse3", CK_OpteronSSE3)
2178       .Case("barcelona", CK_AMDFAM10)
2179       .Case("amdfam10", CK_AMDFAM10)
2180       .Case("btver1", CK_BTVER1)
2181       .Case("btver2", CK_BTVER2)
2182       .Case("bdver1", CK_BDVER1)
2183       .Case("bdver2", CK_BDVER2)
2184       .Case("bdver3", CK_BDVER3)
2185       .Case("bdver4", CK_BDVER4)
2186       .Case("x86-64", CK_x86_64)
2187       .Case("geode", CK_Geode)
2188       .Default(CK_Generic);
2189 
2190     // Perform any per-CPU checks necessary to determine if this CPU is
2191     // acceptable.
2192     // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2193     // invalid without explaining *why*.
2194     switch (CPU) {
2195     case CK_Generic:
2196       // No processor selected!
2197       return false;
2198 
2199     case CK_i386:
2200     case CK_i486:
2201     case CK_WinChipC6:
2202     case CK_WinChip2:
2203     case CK_C3:
2204     case CK_i586:
2205     case CK_Pentium:
2206     case CK_PentiumMMX:
2207     case CK_i686:
2208     case CK_PentiumPro:
2209     case CK_Pentium2:
2210     case CK_Pentium3:
2211     case CK_Pentium3M:
2212     case CK_PentiumM:
2213     case CK_Yonah:
2214     case CK_C3_2:
2215     case CK_Pentium4:
2216     case CK_Pentium4M:
2217     case CK_Prescott:
2218     case CK_K6:
2219     case CK_K6_2:
2220     case CK_K6_3:
2221     case CK_Athlon:
2222     case CK_AthlonThunderbird:
2223     case CK_Athlon4:
2224     case CK_AthlonXP:
2225     case CK_AthlonMP:
2226     case CK_Geode:
2227       // Only accept certain architectures when compiling in 32-bit mode.
2228       if (getTriple().getArch() != llvm::Triple::x86)
2229         return false;
2230 
2231       // Fallthrough
2232     case CK_Nocona:
2233     case CK_Core2:
2234     case CK_Penryn:
2235     case CK_Bonnell:
2236     case CK_Silvermont:
2237     case CK_Nehalem:
2238     case CK_Westmere:
2239     case CK_SandyBridge:
2240     case CK_IvyBridge:
2241     case CK_Haswell:
2242     case CK_Broadwell:
2243     case CK_Skylake:
2244     case CK_KNL:
2245     case CK_Athlon64:
2246     case CK_Athlon64SSE3:
2247     case CK_AthlonFX:
2248     case CK_K8:
2249     case CK_K8SSE3:
2250     case CK_Opteron:
2251     case CK_OpteronSSE3:
2252     case CK_AMDFAM10:
2253     case CK_BTVER1:
2254     case CK_BTVER2:
2255     case CK_BDVER1:
2256     case CK_BDVER2:
2257     case CK_BDVER3:
2258     case CK_BDVER4:
2259     case CK_x86_64:
2260       return true;
2261     }
2262     llvm_unreachable("Unhandled CPU kind");
2263   }
2264 
2265   bool setFPMath(StringRef Name) override;
2266 
2267   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2268     // We accept all non-ARM calling conventions
2269     return (CC == CC_X86ThisCall ||
2270             CC == CC_X86FastCall ||
2271             CC == CC_X86StdCall ||
2272             CC == CC_X86VectorCall ||
2273             CC == CC_C ||
2274             CC == CC_X86Pascal ||
2275             CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2276   }
2277 
2278   CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2279     return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2280   }
2281 
2282   bool hasSjLjLowering() const override {
2283     return true;
2284   }
2285 };
2286 
2287 bool X86TargetInfo::setFPMath(StringRef Name) {
2288   if (Name == "387") {
2289     FPMath = FP_387;
2290     return true;
2291   }
2292   if (Name == "sse") {
2293     FPMath = FP_SSE;
2294     return true;
2295   }
2296   return false;
2297 }
2298 
2299 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2300   // FIXME: This *really* should not be here.
2301 
2302   // X86_64 always has SSE2.
2303   if (getTriple().getArch() == llvm::Triple::x86_64)
2304     setFeatureEnabledImpl(Features, "sse2", true);
2305 
2306   switch (CPU) {
2307   case CK_Generic:
2308   case CK_i386:
2309   case CK_i486:
2310   case CK_i586:
2311   case CK_Pentium:
2312   case CK_i686:
2313   case CK_PentiumPro:
2314     break;
2315   case CK_PentiumMMX:
2316   case CK_Pentium2:
2317   case CK_K6:
2318   case CK_WinChipC6:
2319     setFeatureEnabledImpl(Features, "mmx", true);
2320     break;
2321   case CK_Pentium3:
2322   case CK_Pentium3M:
2323   case CK_C3_2:
2324     setFeatureEnabledImpl(Features, "sse", true);
2325     break;
2326   case CK_PentiumM:
2327   case CK_Pentium4:
2328   case CK_Pentium4M:
2329   case CK_x86_64:
2330     setFeatureEnabledImpl(Features, "sse2", true);
2331     break;
2332   case CK_Yonah:
2333   case CK_Prescott:
2334   case CK_Nocona:
2335     setFeatureEnabledImpl(Features, "sse3", true);
2336     setFeatureEnabledImpl(Features, "cx16", true);
2337     break;
2338   case CK_Core2:
2339   case CK_Bonnell:
2340     setFeatureEnabledImpl(Features, "ssse3", true);
2341     setFeatureEnabledImpl(Features, "cx16", true);
2342     break;
2343   case CK_Penryn:
2344     setFeatureEnabledImpl(Features, "sse4.1", true);
2345     setFeatureEnabledImpl(Features, "cx16", true);
2346     break;
2347   case CK_Skylake:
2348     setFeatureEnabledImpl(Features, "avx512f", true);
2349     setFeatureEnabledImpl(Features, "avx512cd", true);
2350     setFeatureEnabledImpl(Features, "avx512dq", true);
2351     setFeatureEnabledImpl(Features, "avx512bw", true);
2352     setFeatureEnabledImpl(Features, "avx512vl", true);
2353     // FALLTHROUGH
2354   case CK_Broadwell:
2355     setFeatureEnabledImpl(Features, "rdseed", true);
2356     setFeatureEnabledImpl(Features, "adx", true);
2357     // FALLTHROUGH
2358   case CK_Haswell:
2359     setFeatureEnabledImpl(Features, "avx2", true);
2360     setFeatureEnabledImpl(Features, "lzcnt", true);
2361     setFeatureEnabledImpl(Features, "bmi", true);
2362     setFeatureEnabledImpl(Features, "bmi2", true);
2363     setFeatureEnabledImpl(Features, "rtm", true);
2364     setFeatureEnabledImpl(Features, "fma", true);
2365     // FALLTHROUGH
2366   case CK_IvyBridge:
2367     setFeatureEnabledImpl(Features, "rdrnd", true);
2368     setFeatureEnabledImpl(Features, "f16c", true);
2369     setFeatureEnabledImpl(Features, "fsgsbase", true);
2370     // FALLTHROUGH
2371   case CK_SandyBridge:
2372     setFeatureEnabledImpl(Features, "avx", true);
2373     // FALLTHROUGH
2374   case CK_Westmere:
2375   case CK_Silvermont:
2376     setFeatureEnabledImpl(Features, "aes", true);
2377     setFeatureEnabledImpl(Features, "pclmul", true);
2378     // FALLTHROUGH
2379   case CK_Nehalem:
2380     setFeatureEnabledImpl(Features, "sse4.2", true);
2381     setFeatureEnabledImpl(Features, "cx16", true);
2382     break;
2383   case CK_KNL:
2384     setFeatureEnabledImpl(Features, "avx512f", true);
2385     setFeatureEnabledImpl(Features, "avx512cd", true);
2386     setFeatureEnabledImpl(Features, "avx512er", true);
2387     setFeatureEnabledImpl(Features, "avx512pf", true);
2388     setFeatureEnabledImpl(Features, "rdseed", true);
2389     setFeatureEnabledImpl(Features, "adx", true);
2390     setFeatureEnabledImpl(Features, "lzcnt", true);
2391     setFeatureEnabledImpl(Features, "bmi", true);
2392     setFeatureEnabledImpl(Features, "bmi2", true);
2393     setFeatureEnabledImpl(Features, "rtm", true);
2394     setFeatureEnabledImpl(Features, "fma", true);
2395     setFeatureEnabledImpl(Features, "rdrnd", true);
2396     setFeatureEnabledImpl(Features, "f16c", true);
2397     setFeatureEnabledImpl(Features, "fsgsbase", true);
2398     setFeatureEnabledImpl(Features, "aes", true);
2399     setFeatureEnabledImpl(Features, "pclmul", true);
2400     setFeatureEnabledImpl(Features, "cx16", true);
2401     break;
2402   case CK_K6_2:
2403   case CK_K6_3:
2404   case CK_WinChip2:
2405   case CK_C3:
2406     setFeatureEnabledImpl(Features, "3dnow", true);
2407     break;
2408   case CK_Athlon:
2409   case CK_AthlonThunderbird:
2410   case CK_Geode:
2411     setFeatureEnabledImpl(Features, "3dnowa", true);
2412     break;
2413   case CK_Athlon4:
2414   case CK_AthlonXP:
2415   case CK_AthlonMP:
2416     setFeatureEnabledImpl(Features, "sse", true);
2417     setFeatureEnabledImpl(Features, "3dnowa", true);
2418     break;
2419   case CK_K8:
2420   case CK_Opteron:
2421   case CK_Athlon64:
2422   case CK_AthlonFX:
2423     setFeatureEnabledImpl(Features, "sse2", true);
2424     setFeatureEnabledImpl(Features, "3dnowa", true);
2425     break;
2426   case CK_AMDFAM10:
2427     setFeatureEnabledImpl(Features, "sse4a", true);
2428     setFeatureEnabledImpl(Features, "lzcnt", true);
2429     setFeatureEnabledImpl(Features, "popcnt", true);
2430     // FALLTHROUGH
2431   case CK_K8SSE3:
2432   case CK_OpteronSSE3:
2433   case CK_Athlon64SSE3:
2434     setFeatureEnabledImpl(Features, "sse3", true);
2435     setFeatureEnabledImpl(Features, "3dnowa", true);
2436     break;
2437   case CK_BTVER2:
2438     setFeatureEnabledImpl(Features, "avx", true);
2439     setFeatureEnabledImpl(Features, "aes", true);
2440     setFeatureEnabledImpl(Features, "pclmul", true);
2441     setFeatureEnabledImpl(Features, "bmi", true);
2442     setFeatureEnabledImpl(Features, "f16c", true);
2443     // FALLTHROUGH
2444   case CK_BTVER1:
2445     setFeatureEnabledImpl(Features, "ssse3", true);
2446     setFeatureEnabledImpl(Features, "sse4a", true);
2447     setFeatureEnabledImpl(Features, "lzcnt", true);
2448     setFeatureEnabledImpl(Features, "popcnt", true);
2449     setFeatureEnabledImpl(Features, "prfchw", true);
2450     setFeatureEnabledImpl(Features, "cx16", true);
2451     break;
2452   case CK_BDVER4:
2453     setFeatureEnabledImpl(Features, "avx2", true);
2454     setFeatureEnabledImpl(Features, "bmi2", true);
2455     // FALLTHROUGH
2456   case CK_BDVER3:
2457     setFeatureEnabledImpl(Features, "fsgsbase", true);
2458     // FALLTHROUGH
2459   case CK_BDVER2:
2460     setFeatureEnabledImpl(Features, "bmi", true);
2461     setFeatureEnabledImpl(Features, "fma", true);
2462     setFeatureEnabledImpl(Features, "f16c", true);
2463     setFeatureEnabledImpl(Features, "tbm", true);
2464     // FALLTHROUGH
2465   case CK_BDVER1:
2466     // xop implies avx, sse4a and fma4.
2467     setFeatureEnabledImpl(Features, "xop", true);
2468     setFeatureEnabledImpl(Features, "lzcnt", true);
2469     setFeatureEnabledImpl(Features, "aes", true);
2470     setFeatureEnabledImpl(Features, "pclmul", true);
2471     setFeatureEnabledImpl(Features, "prfchw", true);
2472     setFeatureEnabledImpl(Features, "cx16", true);
2473     break;
2474   }
2475 }
2476 
2477 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2478                                 X86SSEEnum Level, bool Enabled) {
2479   if (Enabled) {
2480     switch (Level) {
2481     case AVX512F:
2482       Features["avx512f"] = true;
2483     case AVX2:
2484       Features["avx2"] = true;
2485     case AVX:
2486       Features["avx"] = true;
2487     case SSE42:
2488       Features["sse4.2"] = true;
2489     case SSE41:
2490       Features["sse4.1"] = true;
2491     case SSSE3:
2492       Features["ssse3"] = true;
2493     case SSE3:
2494       Features["sse3"] = true;
2495     case SSE2:
2496       Features["sse2"] = true;
2497     case SSE1:
2498       Features["sse"] = true;
2499     case NoSSE:
2500       break;
2501     }
2502     return;
2503   }
2504 
2505   switch (Level) {
2506   case NoSSE:
2507   case SSE1:
2508     Features["sse"] = false;
2509   case SSE2:
2510     Features["sse2"] = Features["pclmul"] = Features["aes"] =
2511       Features["sha"] = false;
2512   case SSE3:
2513     Features["sse3"] = false;
2514     setXOPLevel(Features, NoXOP, false);
2515   case SSSE3:
2516     Features["ssse3"] = false;
2517   case SSE41:
2518     Features["sse4.1"] = false;
2519   case SSE42:
2520     Features["sse4.2"] = false;
2521   case AVX:
2522     Features["fma"] = Features["avx"] = Features["f16c"] = false;
2523     setXOPLevel(Features, FMA4, false);
2524   case AVX2:
2525     Features["avx2"] = false;
2526   case AVX512F:
2527     Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
2528       Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
2529       Features["avx512vl"] = false;
2530   }
2531 }
2532 
2533 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2534                                 MMX3DNowEnum Level, bool Enabled) {
2535   if (Enabled) {
2536     switch (Level) {
2537     case AMD3DNowAthlon:
2538       Features["3dnowa"] = true;
2539     case AMD3DNow:
2540       Features["3dnow"] = true;
2541     case MMX:
2542       Features["mmx"] = true;
2543     case NoMMX3DNow:
2544       break;
2545     }
2546     return;
2547   }
2548 
2549   switch (Level) {
2550   case NoMMX3DNow:
2551   case MMX:
2552     Features["mmx"] = false;
2553   case AMD3DNow:
2554     Features["3dnow"] = false;
2555   case AMD3DNowAthlon:
2556     Features["3dnowa"] = false;
2557   }
2558 }
2559 
2560 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2561                                 bool Enabled) {
2562   if (Enabled) {
2563     switch (Level) {
2564     case XOP:
2565       Features["xop"] = true;
2566     case FMA4:
2567       Features["fma4"] = true;
2568       setSSELevel(Features, AVX, true);
2569     case SSE4A:
2570       Features["sse4a"] = true;
2571       setSSELevel(Features, SSE3, true);
2572     case NoXOP:
2573       break;
2574     }
2575     return;
2576   }
2577 
2578   switch (Level) {
2579   case NoXOP:
2580   case SSE4A:
2581     Features["sse4a"] = false;
2582   case FMA4:
2583     Features["fma4"] = false;
2584   case XOP:
2585     Features["xop"] = false;
2586   }
2587 }
2588 
2589 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2590                                           StringRef Name, bool Enabled) {
2591   // FIXME: This *really* should not be here.  We need some way of translating
2592   // options into llvm subtarget features.
2593   if (Name == "sse4")
2594     Name = "sse4.2";
2595 
2596   Features[Name] = Enabled;
2597 
2598   if (Name == "mmx") {
2599     setMMXLevel(Features, MMX, Enabled);
2600   } else if (Name == "sse") {
2601     setSSELevel(Features, SSE1, Enabled);
2602   } else if (Name == "sse2") {
2603     setSSELevel(Features, SSE2, Enabled);
2604   } else if (Name == "sse3") {
2605     setSSELevel(Features, SSE3, Enabled);
2606   } else if (Name == "ssse3") {
2607     setSSELevel(Features, SSSE3, Enabled);
2608   } else if (Name == "sse4.2") {
2609     setSSELevel(Features, SSE42, Enabled);
2610   } else if (Name == "sse4.1") {
2611     setSSELevel(Features, SSE41, Enabled);
2612   } else if (Name == "3dnow") {
2613     setMMXLevel(Features, AMD3DNow, Enabled);
2614   } else if (Name == "3dnowa") {
2615     setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2616   } else if (Name == "aes") {
2617     if (Enabled)
2618       setSSELevel(Features, SSE2, Enabled);
2619   } else if (Name == "pclmul") {
2620     if (Enabled)
2621       setSSELevel(Features, SSE2, Enabled);
2622   } else if (Name == "avx") {
2623     setSSELevel(Features, AVX, Enabled);
2624   } else if (Name == "avx2") {
2625     setSSELevel(Features, AVX2, Enabled);
2626   } else if (Name == "avx512f") {
2627     setSSELevel(Features, AVX512F, Enabled);
2628   } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf"
2629           || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") {
2630     if (Enabled)
2631       setSSELevel(Features, AVX512F, Enabled);
2632   } else if (Name == "fma") {
2633     if (Enabled)
2634       setSSELevel(Features, AVX, Enabled);
2635   } else if (Name == "fma4") {
2636     setXOPLevel(Features, FMA4, Enabled);
2637   } else if (Name == "xop") {
2638     setXOPLevel(Features, XOP, Enabled);
2639   } else if (Name == "sse4a") {
2640     setXOPLevel(Features, SSE4A, Enabled);
2641   } else if (Name == "f16c") {
2642     if (Enabled)
2643       setSSELevel(Features, AVX, Enabled);
2644   } else if (Name == "sha") {
2645     if (Enabled)
2646       setSSELevel(Features, SSE2, Enabled);
2647   }
2648 }
2649 
2650 /// handleTargetFeatures - Perform initialization based on the user
2651 /// configured set of features.
2652 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2653                                          DiagnosticsEngine &Diags) {
2654   // Remember the maximum enabled sselevel.
2655   for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2656     // Ignore disabled features.
2657     if (Features[i][0] == '-')
2658       continue;
2659 
2660     StringRef Feature = StringRef(Features[i]).substr(1);
2661 
2662     if (Feature == "aes") {
2663       HasAES = true;
2664       continue;
2665     }
2666 
2667     if (Feature == "pclmul") {
2668       HasPCLMUL = true;
2669       continue;
2670     }
2671 
2672     if (Feature == "lzcnt") {
2673       HasLZCNT = true;
2674       continue;
2675     }
2676 
2677     if (Feature == "rdrnd") {
2678       HasRDRND = true;
2679       continue;
2680     }
2681 
2682     if (Feature == "fsgsbase") {
2683       HasFSGSBASE = true;
2684       continue;
2685     }
2686 
2687     if (Feature == "bmi") {
2688       HasBMI = true;
2689       continue;
2690     }
2691 
2692     if (Feature == "bmi2") {
2693       HasBMI2 = true;
2694       continue;
2695     }
2696 
2697     if (Feature == "popcnt") {
2698       HasPOPCNT = true;
2699       continue;
2700     }
2701 
2702     if (Feature == "rtm") {
2703       HasRTM = true;
2704       continue;
2705     }
2706 
2707     if (Feature == "prfchw") {
2708       HasPRFCHW = true;
2709       continue;
2710     }
2711 
2712     if (Feature == "rdseed") {
2713       HasRDSEED = true;
2714       continue;
2715     }
2716 
2717     if (Feature == "adx") {
2718       HasADX = true;
2719       continue;
2720     }
2721 
2722     if (Feature == "tbm") {
2723       HasTBM = true;
2724       continue;
2725     }
2726 
2727     if (Feature == "fma") {
2728       HasFMA = true;
2729       continue;
2730     }
2731 
2732     if (Feature == "f16c") {
2733       HasF16C = true;
2734       continue;
2735     }
2736 
2737     if (Feature == "avx512cd") {
2738       HasAVX512CD = true;
2739       continue;
2740     }
2741 
2742     if (Feature == "avx512er") {
2743       HasAVX512ER = true;
2744       continue;
2745     }
2746 
2747     if (Feature == "avx512pf") {
2748       HasAVX512PF = true;
2749       continue;
2750     }
2751 
2752     if (Feature == "avx512dq") {
2753       HasAVX512DQ = true;
2754       continue;
2755     }
2756 
2757     if (Feature == "avx512bw") {
2758       HasAVX512BW = true;
2759       continue;
2760     }
2761 
2762     if (Feature == "avx512vl") {
2763       HasAVX512VL = true;
2764       continue;
2765     }
2766 
2767     if (Feature == "sha") {
2768       HasSHA = true;
2769       continue;
2770     }
2771 
2772     if (Feature == "cx16") {
2773       HasCX16 = true;
2774       continue;
2775     }
2776 
2777     assert(Features[i][0] == '+' && "Invalid target feature!");
2778     X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2779       .Case("avx512f", AVX512F)
2780       .Case("avx2", AVX2)
2781       .Case("avx", AVX)
2782       .Case("sse4.2", SSE42)
2783       .Case("sse4.1", SSE41)
2784       .Case("ssse3", SSSE3)
2785       .Case("sse3", SSE3)
2786       .Case("sse2", SSE2)
2787       .Case("sse", SSE1)
2788       .Default(NoSSE);
2789     SSELevel = std::max(SSELevel, Level);
2790 
2791     MMX3DNowEnum ThreeDNowLevel =
2792       llvm::StringSwitch<MMX3DNowEnum>(Feature)
2793         .Case("3dnowa", AMD3DNowAthlon)
2794         .Case("3dnow", AMD3DNow)
2795         .Case("mmx", MMX)
2796         .Default(NoMMX3DNow);
2797     MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2798 
2799     XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
2800         .Case("xop", XOP)
2801         .Case("fma4", FMA4)
2802         .Case("sse4a", SSE4A)
2803         .Default(NoXOP);
2804     XOPLevel = std::max(XOPLevel, XLevel);
2805   }
2806 
2807   // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2808   // Can't do this earlier because we need to be able to explicitly enable
2809   // popcnt and still disable sse4.2.
2810   if (!HasPOPCNT && SSELevel >= SSE42 &&
2811       std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){
2812     HasPOPCNT = true;
2813     Features.push_back("+popcnt");
2814   }
2815 
2816   // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
2817   if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow &&
2818       std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){
2819     HasPRFCHW = true;
2820     Features.push_back("+prfchw");
2821   }
2822 
2823   // LLVM doesn't have a separate switch for fpmath, so only accept it if it
2824   // matches the selected sse level.
2825   if (FPMath == FP_SSE && SSELevel < SSE1) {
2826     Diags.Report(diag::err_target_unsupported_fpmath) << "sse";
2827     return false;
2828   } else if (FPMath == FP_387 && SSELevel >= SSE1) {
2829     Diags.Report(diag::err_target_unsupported_fpmath) << "387";
2830     return false;
2831   }
2832 
2833   // Don't tell the backend if we're turning off mmx; it will end up disabling
2834   // SSE, which we don't want.
2835   // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2836   // then enable MMX.
2837   std::vector<std::string>::iterator it;
2838   it = std::find(Features.begin(), Features.end(), "-mmx");
2839   if (it != Features.end())
2840     Features.erase(it);
2841   else if (SSELevel > NoSSE)
2842     MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
2843   return true;
2844 }
2845 
2846 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2847 /// definitions for this particular subtarget.
2848 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2849                                      MacroBuilder &Builder) const {
2850   // Target identification.
2851   if (getTriple().getArch() == llvm::Triple::x86_64) {
2852     Builder.defineMacro("__amd64__");
2853     Builder.defineMacro("__amd64");
2854     Builder.defineMacro("__x86_64");
2855     Builder.defineMacro("__x86_64__");
2856     if (getTriple().getArchName() == "x86_64h") {
2857       Builder.defineMacro("__x86_64h");
2858       Builder.defineMacro("__x86_64h__");
2859     }
2860   } else {
2861     DefineStd(Builder, "i386", Opts);
2862   }
2863 
2864   // Subtarget options.
2865   // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2866   // truly should be based on -mtune options.
2867   switch (CPU) {
2868   case CK_Generic:
2869     break;
2870   case CK_i386:
2871     // The rest are coming from the i386 define above.
2872     Builder.defineMacro("__tune_i386__");
2873     break;
2874   case CK_i486:
2875   case CK_WinChipC6:
2876   case CK_WinChip2:
2877   case CK_C3:
2878     defineCPUMacros(Builder, "i486");
2879     break;
2880   case CK_PentiumMMX:
2881     Builder.defineMacro("__pentium_mmx__");
2882     Builder.defineMacro("__tune_pentium_mmx__");
2883     // Fallthrough
2884   case CK_i586:
2885   case CK_Pentium:
2886     defineCPUMacros(Builder, "i586");
2887     defineCPUMacros(Builder, "pentium");
2888     break;
2889   case CK_Pentium3:
2890   case CK_Pentium3M:
2891   case CK_PentiumM:
2892     Builder.defineMacro("__tune_pentium3__");
2893     // Fallthrough
2894   case CK_Pentium2:
2895   case CK_C3_2:
2896     Builder.defineMacro("__tune_pentium2__");
2897     // Fallthrough
2898   case CK_PentiumPro:
2899     Builder.defineMacro("__tune_i686__");
2900     Builder.defineMacro("__tune_pentiumpro__");
2901     // Fallthrough
2902   case CK_i686:
2903     Builder.defineMacro("__i686");
2904     Builder.defineMacro("__i686__");
2905     // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2906     Builder.defineMacro("__pentiumpro");
2907     Builder.defineMacro("__pentiumpro__");
2908     break;
2909   case CK_Pentium4:
2910   case CK_Pentium4M:
2911     defineCPUMacros(Builder, "pentium4");
2912     break;
2913   case CK_Yonah:
2914   case CK_Prescott:
2915   case CK_Nocona:
2916     defineCPUMacros(Builder, "nocona");
2917     break;
2918   case CK_Core2:
2919   case CK_Penryn:
2920     defineCPUMacros(Builder, "core2");
2921     break;
2922   case CK_Bonnell:
2923     defineCPUMacros(Builder, "atom");
2924     break;
2925   case CK_Silvermont:
2926     defineCPUMacros(Builder, "slm");
2927     break;
2928   case CK_Nehalem:
2929   case CK_Westmere:
2930   case CK_SandyBridge:
2931   case CK_IvyBridge:
2932   case CK_Haswell:
2933   case CK_Broadwell:
2934     // FIXME: Historically, we defined this legacy name, it would be nice to
2935     // remove it at some point. We've never exposed fine-grained names for
2936     // recent primary x86 CPUs, and we should keep it that way.
2937     defineCPUMacros(Builder, "corei7");
2938     break;
2939   case CK_Skylake:
2940     // FIXME: Historically, we defined this legacy name, it would be nice to
2941     // remove it at some point. This is the only fine-grained CPU macro in the
2942     // main intel CPU line, and it would be better to not have these and force
2943     // people to use ISA macros.
2944     defineCPUMacros(Builder, "skx");
2945     break;
2946   case CK_KNL:
2947     defineCPUMacros(Builder, "knl");
2948     break;
2949   case CK_K6_2:
2950     Builder.defineMacro("__k6_2__");
2951     Builder.defineMacro("__tune_k6_2__");
2952     // Fallthrough
2953   case CK_K6_3:
2954     if (CPU != CK_K6_2) {  // In case of fallthrough
2955       // FIXME: GCC may be enabling these in cases where some other k6
2956       // architecture is specified but -m3dnow is explicitly provided. The
2957       // exact semantics need to be determined and emulated here.
2958       Builder.defineMacro("__k6_3__");
2959       Builder.defineMacro("__tune_k6_3__");
2960     }
2961     // Fallthrough
2962   case CK_K6:
2963     defineCPUMacros(Builder, "k6");
2964     break;
2965   case CK_Athlon:
2966   case CK_AthlonThunderbird:
2967   case CK_Athlon4:
2968   case CK_AthlonXP:
2969   case CK_AthlonMP:
2970     defineCPUMacros(Builder, "athlon");
2971     if (SSELevel != NoSSE) {
2972       Builder.defineMacro("__athlon_sse__");
2973       Builder.defineMacro("__tune_athlon_sse__");
2974     }
2975     break;
2976   case CK_K8:
2977   case CK_K8SSE3:
2978   case CK_x86_64:
2979   case CK_Opteron:
2980   case CK_OpteronSSE3:
2981   case CK_Athlon64:
2982   case CK_Athlon64SSE3:
2983   case CK_AthlonFX:
2984     defineCPUMacros(Builder, "k8");
2985     break;
2986   case CK_AMDFAM10:
2987     defineCPUMacros(Builder, "amdfam10");
2988     break;
2989   case CK_BTVER1:
2990     defineCPUMacros(Builder, "btver1");
2991     break;
2992   case CK_BTVER2:
2993     defineCPUMacros(Builder, "btver2");
2994     break;
2995   case CK_BDVER1:
2996     defineCPUMacros(Builder, "bdver1");
2997     break;
2998   case CK_BDVER2:
2999     defineCPUMacros(Builder, "bdver2");
3000     break;
3001   case CK_BDVER3:
3002     defineCPUMacros(Builder, "bdver3");
3003     break;
3004   case CK_BDVER4:
3005     defineCPUMacros(Builder, "bdver4");
3006     break;
3007   case CK_Geode:
3008     defineCPUMacros(Builder, "geode");
3009     break;
3010   }
3011 
3012   // Target properties.
3013   Builder.defineMacro("__REGISTER_PREFIX__", "");
3014 
3015   // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
3016   // functions in glibc header files that use FP Stack inline asm which the
3017   // backend can't deal with (PR879).
3018   Builder.defineMacro("__NO_MATH_INLINES");
3019 
3020   if (HasAES)
3021     Builder.defineMacro("__AES__");
3022 
3023   if (HasPCLMUL)
3024     Builder.defineMacro("__PCLMUL__");
3025 
3026   if (HasLZCNT)
3027     Builder.defineMacro("__LZCNT__");
3028 
3029   if (HasRDRND)
3030     Builder.defineMacro("__RDRND__");
3031 
3032   if (HasFSGSBASE)
3033     Builder.defineMacro("__FSGSBASE__");
3034 
3035   if (HasBMI)
3036     Builder.defineMacro("__BMI__");
3037 
3038   if (HasBMI2)
3039     Builder.defineMacro("__BMI2__");
3040 
3041   if (HasPOPCNT)
3042     Builder.defineMacro("__POPCNT__");
3043 
3044   if (HasRTM)
3045     Builder.defineMacro("__RTM__");
3046 
3047   if (HasPRFCHW)
3048     Builder.defineMacro("__PRFCHW__");
3049 
3050   if (HasRDSEED)
3051     Builder.defineMacro("__RDSEED__");
3052 
3053   if (HasADX)
3054     Builder.defineMacro("__ADX__");
3055 
3056   if (HasTBM)
3057     Builder.defineMacro("__TBM__");
3058 
3059   switch (XOPLevel) {
3060   case XOP:
3061     Builder.defineMacro("__XOP__");
3062   case FMA4:
3063     Builder.defineMacro("__FMA4__");
3064   case SSE4A:
3065     Builder.defineMacro("__SSE4A__");
3066   case NoXOP:
3067     break;
3068   }
3069 
3070   if (HasFMA)
3071     Builder.defineMacro("__FMA__");
3072 
3073   if (HasF16C)
3074     Builder.defineMacro("__F16C__");
3075 
3076   if (HasAVX512CD)
3077     Builder.defineMacro("__AVX512CD__");
3078   if (HasAVX512ER)
3079     Builder.defineMacro("__AVX512ER__");
3080   if (HasAVX512PF)
3081     Builder.defineMacro("__AVX512PF__");
3082   if (HasAVX512DQ)
3083     Builder.defineMacro("__AVX512DQ__");
3084   if (HasAVX512BW)
3085     Builder.defineMacro("__AVX512BW__");
3086   if (HasAVX512VL)
3087     Builder.defineMacro("__AVX512VL__");
3088 
3089   if (HasSHA)
3090     Builder.defineMacro("__SHA__");
3091 
3092   if (HasCX16)
3093     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
3094 
3095   // Each case falls through to the previous one here.
3096   switch (SSELevel) {
3097   case AVX512F:
3098     Builder.defineMacro("__AVX512F__");
3099   case AVX2:
3100     Builder.defineMacro("__AVX2__");
3101   case AVX:
3102     Builder.defineMacro("__AVX__");
3103   case SSE42:
3104     Builder.defineMacro("__SSE4_2__");
3105   case SSE41:
3106     Builder.defineMacro("__SSE4_1__");
3107   case SSSE3:
3108     Builder.defineMacro("__SSSE3__");
3109   case SSE3:
3110     Builder.defineMacro("__SSE3__");
3111   case SSE2:
3112     Builder.defineMacro("__SSE2__");
3113     Builder.defineMacro("__SSE2_MATH__");  // -mfp-math=sse always implied.
3114   case SSE1:
3115     Builder.defineMacro("__SSE__");
3116     Builder.defineMacro("__SSE_MATH__");   // -mfp-math=sse always implied.
3117   case NoSSE:
3118     break;
3119   }
3120 
3121   if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
3122     switch (SSELevel) {
3123     case AVX512F:
3124     case AVX2:
3125     case AVX:
3126     case SSE42:
3127     case SSE41:
3128     case SSSE3:
3129     case SSE3:
3130     case SSE2:
3131       Builder.defineMacro("_M_IX86_FP", Twine(2));
3132       break;
3133     case SSE1:
3134       Builder.defineMacro("_M_IX86_FP", Twine(1));
3135       break;
3136     default:
3137       Builder.defineMacro("_M_IX86_FP", Twine(0));
3138     }
3139   }
3140 
3141   // Each case falls through to the previous one here.
3142   switch (MMX3DNowLevel) {
3143   case AMD3DNowAthlon:
3144     Builder.defineMacro("__3dNOW_A__");
3145   case AMD3DNow:
3146     Builder.defineMacro("__3dNOW__");
3147   case MMX:
3148     Builder.defineMacro("__MMX__");
3149   case NoMMX3DNow:
3150     break;
3151   }
3152 
3153   if (CPU >= CK_i486) {
3154     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3155     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3156     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3157   }
3158   if (CPU >= CK_i586)
3159     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3160 }
3161 
3162 bool X86TargetInfo::hasFeature(StringRef Feature) const {
3163   return llvm::StringSwitch<bool>(Feature)
3164       .Case("aes", HasAES)
3165       .Case("avx", SSELevel >= AVX)
3166       .Case("avx2", SSELevel >= AVX2)
3167       .Case("avx512f", SSELevel >= AVX512F)
3168       .Case("avx512cd", HasAVX512CD)
3169       .Case("avx512er", HasAVX512ER)
3170       .Case("avx512pf", HasAVX512PF)
3171       .Case("avx512dq", HasAVX512DQ)
3172       .Case("avx512bw", HasAVX512BW)
3173       .Case("avx512vl", HasAVX512VL)
3174       .Case("bmi", HasBMI)
3175       .Case("bmi2", HasBMI2)
3176       .Case("cx16", HasCX16)
3177       .Case("f16c", HasF16C)
3178       .Case("fma", HasFMA)
3179       .Case("fma4", XOPLevel >= FMA4)
3180       .Case("fsgsbase", HasFSGSBASE)
3181       .Case("lzcnt", HasLZCNT)
3182       .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3183       .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3184       .Case("mmx", MMX3DNowLevel >= MMX)
3185       .Case("pclmul", HasPCLMUL)
3186       .Case("popcnt", HasPOPCNT)
3187       .Case("prfchw", HasPRFCHW)
3188       .Case("rdrnd", HasRDRND)
3189       .Case("rdseed", HasRDSEED)
3190       .Case("rtm", HasRTM)
3191       .Case("sha", HasSHA)
3192       .Case("sse", SSELevel >= SSE1)
3193       .Case("sse2", SSELevel >= SSE2)
3194       .Case("sse3", SSELevel >= SSE3)
3195       .Case("ssse3", SSELevel >= SSSE3)
3196       .Case("sse4.1", SSELevel >= SSE41)
3197       .Case("sse4.2", SSELevel >= SSE42)
3198       .Case("sse4a", XOPLevel >= SSE4A)
3199       .Case("tbm", HasTBM)
3200       .Case("x86", true)
3201       .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
3202       .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
3203       .Case("xop", XOPLevel >= XOP)
3204       .Default(false);
3205 }
3206 
3207 bool
3208 X86TargetInfo::validateAsmConstraint(const char *&Name,
3209                                      TargetInfo::ConstraintInfo &Info) const {
3210   switch (*Name) {
3211   default: return false;
3212   case 'I':
3213     Info.setRequiresImmediate(0, 31);
3214     return true;
3215   case 'J':
3216     Info.setRequiresImmediate(0, 63);
3217     return true;
3218   case 'K':
3219     Info.setRequiresImmediate(-128, 127);
3220     return true;
3221   case 'L':
3222     // FIXME: properly analyze this constraint:
3223     //  must be one of 0xff, 0xffff, or 0xffffffff
3224     return true;
3225   case 'M':
3226     Info.setRequiresImmediate(0, 3);
3227     return true;
3228   case 'N':
3229     Info.setRequiresImmediate(0, 255);
3230     return true;
3231   case 'O':
3232     Info.setRequiresImmediate(0, 127);
3233     return true;
3234   case 'Y': // first letter of a pair:
3235     switch (*(Name+1)) {
3236     default: return false;
3237     case '0':  // First SSE register.
3238     case 't':  // Any SSE register, when SSE2 is enabled.
3239     case 'i':  // Any SSE register, when SSE2 and inter-unit moves enabled.
3240     case 'm':  // any MMX register, when inter-unit moves enabled.
3241       break;   // falls through to setAllowsRegister.
3242   }
3243   case 'f': // any x87 floating point stack register.
3244     // Constraint 'f' cannot be used for output operands.
3245     if (Info.ConstraintStr[0] == '=')
3246       return false;
3247 
3248     Info.setAllowsRegister();
3249     return true;
3250   case 'a': // eax.
3251   case 'b': // ebx.
3252   case 'c': // ecx.
3253   case 'd': // edx.
3254   case 'S': // esi.
3255   case 'D': // edi.
3256   case 'A': // edx:eax.
3257   case 't': // top of floating point stack.
3258   case 'u': // second from top of floating point stack.
3259   case 'q': // Any register accessible as [r]l: a, b, c, and d.
3260   case 'y': // Any MMX register.
3261   case 'x': // Any SSE register.
3262   case 'Q': // Any register accessible as [r]h: a, b, c, and d.
3263   case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
3264   case 'l': // "Index" registers: any general register that can be used as an
3265             // index in a base+index memory access.
3266     Info.setAllowsRegister();
3267     return true;
3268   case 'C': // SSE floating point constant.
3269   case 'G': // x87 floating point constant.
3270   case 'e': // 32-bit signed integer constant for use with zero-extending
3271             // x86_64 instructions.
3272   case 'Z': // 32-bit unsigned integer constant for use with zero-extending
3273             // x86_64 instructions.
3274     return true;
3275   }
3276 }
3277 
3278 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
3279                                        unsigned Size) const {
3280   // Strip off constraint modifiers.
3281   while (Constraint[0] == '=' ||
3282          Constraint[0] == '+' ||
3283          Constraint[0] == '&')
3284     Constraint = Constraint.substr(1);
3285 
3286   return validateOperandSize(Constraint, Size);
3287 }
3288 
3289 bool X86TargetInfo::validateInputSize(StringRef Constraint,
3290                                       unsigned Size) const {
3291   return validateOperandSize(Constraint, Size);
3292 }
3293 
3294 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
3295                                         unsigned Size) const {
3296   switch (Constraint[0]) {
3297   default: break;
3298   case 'y':
3299     return Size <= 64;
3300   case 'f':
3301   case 't':
3302   case 'u':
3303     return Size <= 128;
3304   case 'x':
3305     // 256-bit ymm registers can be used if target supports AVX.
3306     return Size <= (SSELevel >= AVX ? 256U : 128U);
3307   }
3308 
3309   return true;
3310 }
3311 
3312 std::string
3313 X86TargetInfo::convertConstraint(const char *&Constraint) const {
3314   switch (*Constraint) {
3315   case 'a': return std::string("{ax}");
3316   case 'b': return std::string("{bx}");
3317   case 'c': return std::string("{cx}");
3318   case 'd': return std::string("{dx}");
3319   case 'S': return std::string("{si}");
3320   case 'D': return std::string("{di}");
3321   case 'p': // address
3322     return std::string("im");
3323   case 't': // top of floating point stack.
3324     return std::string("{st}");
3325   case 'u': // second from top of floating point stack.
3326     return std::string("{st(1)}"); // second from top of floating point stack.
3327   default:
3328     return std::string(1, *Constraint);
3329   }
3330 }
3331 } // end anonymous namespace
3332 
3333 namespace {
3334 // X86-32 generic target
3335 class X86_32TargetInfo : public X86TargetInfo {
3336 public:
3337   X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3338     DoubleAlign = LongLongAlign = 32;
3339     LongDoubleWidth = 96;
3340     LongDoubleAlign = 32;
3341     SuitableAlign = 128;
3342     DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128";
3343     SizeType = UnsignedInt;
3344     PtrDiffType = SignedInt;
3345     IntPtrType = SignedInt;
3346     RegParmMax = 3;
3347 
3348     // Use fpret for all types.
3349     RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
3350                              (1 << TargetInfo::Double) |
3351                              (1 << TargetInfo::LongDouble));
3352 
3353     // x86-32 has atomics up to 8 bytes
3354     // FIXME: Check that we actually have cmpxchg8b before setting
3355     // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
3356     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3357   }
3358   BuiltinVaListKind getBuiltinVaListKind() const override {
3359     return TargetInfo::CharPtrBuiltinVaList;
3360   }
3361 
3362   int getEHDataRegisterNumber(unsigned RegNo) const override {
3363     if (RegNo == 0) return 0;
3364     if (RegNo == 1) return 2;
3365     return -1;
3366   }
3367   bool validateOperandSize(StringRef Constraint,
3368                            unsigned Size) const override {
3369     switch (Constraint[0]) {
3370     default: break;
3371     case 'R':
3372     case 'q':
3373     case 'Q':
3374     case 'a':
3375     case 'b':
3376     case 'c':
3377     case 'd':
3378     case 'S':
3379     case 'D':
3380       return Size <= 32;
3381     case 'A':
3382       return Size <= 64;
3383     }
3384 
3385     return X86TargetInfo::validateOperandSize(Constraint, Size);
3386   }
3387 };
3388 } // end anonymous namespace
3389 
3390 namespace {
3391 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
3392 public:
3393   NetBSDI386TargetInfo(const llvm::Triple &Triple)
3394       : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
3395 
3396   unsigned getFloatEvalMethod() const override {
3397     unsigned Major, Minor, Micro;
3398     getTriple().getOSVersion(Major, Minor, Micro);
3399     // New NetBSD uses the default rounding mode.
3400     if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3401       return X86_32TargetInfo::getFloatEvalMethod();
3402     // NetBSD before 6.99.26 defaults to "double" rounding.
3403     return 1;
3404   }
3405 };
3406 } // end anonymous namespace
3407 
3408 namespace {
3409 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3410 public:
3411   OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3412       : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3413     SizeType = UnsignedLong;
3414     IntPtrType = SignedLong;
3415     PtrDiffType = SignedLong;
3416   }
3417 };
3418 } // end anonymous namespace
3419 
3420 namespace {
3421 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3422 public:
3423   BitrigI386TargetInfo(const llvm::Triple &Triple)
3424       : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3425     SizeType = UnsignedLong;
3426     IntPtrType = SignedLong;
3427     PtrDiffType = SignedLong;
3428   }
3429 };
3430 } // end anonymous namespace
3431 
3432 namespace {
3433 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3434 public:
3435   DarwinI386TargetInfo(const llvm::Triple &Triple)
3436       : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3437     LongDoubleWidth = 128;
3438     LongDoubleAlign = 128;
3439     SuitableAlign = 128;
3440     MaxVectorAlign = 256;
3441     SizeType = UnsignedLong;
3442     IntPtrType = SignedLong;
3443     DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
3444     HasAlignMac68kSupport = true;
3445   }
3446 
3447 };
3448 } // end anonymous namespace
3449 
3450 namespace {
3451 // x86-32 Windows target
3452 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3453 public:
3454   WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3455       : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3456     WCharType = UnsignedShort;
3457     DoubleAlign = LongLongAlign = 64;
3458     DescriptionString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-S32";
3459   }
3460   void getTargetDefines(const LangOptions &Opts,
3461                         MacroBuilder &Builder) const override {
3462     WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3463   }
3464 };
3465 
3466 // x86-32 Windows Visual Studio target
3467 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
3468 public:
3469   MicrosoftX86_32TargetInfo(const llvm::Triple &Triple)
3470       : WindowsX86_32TargetInfo(Triple) {
3471     LongDoubleWidth = LongDoubleAlign = 64;
3472     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3473   }
3474   void getTargetDefines(const LangOptions &Opts,
3475                         MacroBuilder &Builder) const override {
3476     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3477     WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3478     // The value of the following reflects processor type.
3479     // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3480     // We lost the original triple, so we use the default.
3481     Builder.defineMacro("_M_IX86", "600");
3482   }
3483 };
3484 } // end anonymous namespace
3485 
3486 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3487   Builder.defineMacro("__MSVCRT__");
3488   Builder.defineMacro("__MINGW32__");
3489 
3490   // Mingw defines __declspec(a) to __attribute__((a)).  Clang supports
3491   // __declspec natively under -fms-extensions, but we define a no-op __declspec
3492   // macro anyway for pre-processor compatibility.
3493   if (Opts.MicrosoftExt)
3494     Builder.defineMacro("__declspec", "__declspec");
3495   else
3496     Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3497 
3498   if (!Opts.MicrosoftExt) {
3499     // Provide macros for all the calling convention keywords.  Provide both
3500     // single and double underscore prefixed variants.  These are available on
3501     // x64 as well as x86, even though they have no effect.
3502     const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
3503     for (const char *CC : CCs) {
3504       std::string GCCSpelling = "__attribute__((__";
3505       GCCSpelling += CC;
3506       GCCSpelling += "__))";
3507       Builder.defineMacro(Twine("_") + CC, GCCSpelling);
3508       Builder.defineMacro(Twine("__") + CC, GCCSpelling);
3509     }
3510   }
3511 }
3512 
3513 namespace {
3514 // x86-32 MinGW target
3515 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3516 public:
3517   MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3518       : WindowsX86_32TargetInfo(Triple) {}
3519   void getTargetDefines(const LangOptions &Opts,
3520                         MacroBuilder &Builder) const override {
3521     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3522     DefineStd(Builder, "WIN32", Opts);
3523     DefineStd(Builder, "WINNT", Opts);
3524     Builder.defineMacro("_X86_");
3525     addMinGWDefines(Opts, Builder);
3526   }
3527 };
3528 } // end anonymous namespace
3529 
3530 namespace {
3531 // x86-32 Cygwin target
3532 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3533 public:
3534   CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3535       : X86_32TargetInfo(Triple) {
3536     TLSSupported = false;
3537     WCharType = UnsignedShort;
3538     DoubleAlign = LongLongAlign = 64;
3539     DescriptionString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-S32";
3540   }
3541   void getTargetDefines(const LangOptions &Opts,
3542                         MacroBuilder &Builder) const override {
3543     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3544     Builder.defineMacro("_X86_");
3545     Builder.defineMacro("__CYGWIN__");
3546     Builder.defineMacro("__CYGWIN32__");
3547     DefineStd(Builder, "unix", Opts);
3548     if (Opts.CPlusPlus)
3549       Builder.defineMacro("_GNU_SOURCE");
3550   }
3551 };
3552 } // end anonymous namespace
3553 
3554 namespace {
3555 // x86-32 Haiku target
3556 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3557 public:
3558   HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3559     SizeType = UnsignedLong;
3560     IntPtrType = SignedLong;
3561     PtrDiffType = SignedLong;
3562     ProcessIDType = SignedLong;
3563     this->UserLabelPrefix = "";
3564     this->TLSSupported = false;
3565   }
3566   void getTargetDefines(const LangOptions &Opts,
3567                         MacroBuilder &Builder) const override {
3568     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3569     Builder.defineMacro("__INTEL__");
3570     Builder.defineMacro("__HAIKU__");
3571   }
3572 };
3573 } // end anonymous namespace
3574 
3575 // RTEMS Target
3576 template<typename Target>
3577 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3578 protected:
3579   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3580                     MacroBuilder &Builder) const override {
3581     // RTEMS defines; list based off of gcc output
3582 
3583     Builder.defineMacro("__rtems__");
3584     Builder.defineMacro("__ELF__");
3585   }
3586 
3587 public:
3588   RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3589     this->UserLabelPrefix = "";
3590 
3591     switch (Triple.getArch()) {
3592     default:
3593     case llvm::Triple::x86:
3594       // this->MCountName = ".mcount";
3595       break;
3596     case llvm::Triple::mips:
3597     case llvm::Triple::mipsel:
3598     case llvm::Triple::ppc:
3599     case llvm::Triple::ppc64:
3600     case llvm::Triple::ppc64le:
3601       // this->MCountName = "_mcount";
3602       break;
3603     case llvm::Triple::arm:
3604       // this->MCountName = "__mcount";
3605       break;
3606     }
3607   }
3608 };
3609 
3610 namespace {
3611 // x86-32 RTEMS target
3612 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3613 public:
3614   RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3615     SizeType = UnsignedLong;
3616     IntPtrType = SignedLong;
3617     PtrDiffType = SignedLong;
3618     this->UserLabelPrefix = "";
3619   }
3620   void getTargetDefines(const LangOptions &Opts,
3621                         MacroBuilder &Builder) const override {
3622     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3623     Builder.defineMacro("__INTEL__");
3624     Builder.defineMacro("__rtems__");
3625   }
3626 };
3627 } // end anonymous namespace
3628 
3629 namespace {
3630 // x86-64 generic target
3631 class X86_64TargetInfo : public X86TargetInfo {
3632 public:
3633   X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3634     const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
3635     bool IsWinCOFF =
3636         getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
3637     LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
3638     LongDoubleWidth = 128;
3639     LongDoubleAlign = 128;
3640     LargeArrayMinWidth = 128;
3641     LargeArrayAlign = 128;
3642     SuitableAlign = 128;
3643     SizeType    = IsX32 ? UnsignedInt      : UnsignedLong;
3644     PtrDiffType = IsX32 ? SignedInt        : SignedLong;
3645     IntPtrType  = IsX32 ? SignedInt        : SignedLong;
3646     IntMaxType  = IsX32 ? SignedLongLong   : SignedLong;
3647     Int64Type   = IsX32 ? SignedLongLong   : SignedLong;
3648     RegParmMax = 6;
3649 
3650     // Pointers are 32-bit in x32.
3651     DescriptionString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
3652                               : IsWinCOFF
3653                                     ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
3654                                     : "e-m:e-i64:64-f80:128-n8:16:32:64-S128";
3655 
3656     // Use fpret only for long double.
3657     RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3658 
3659     // Use fp2ret for _Complex long double.
3660     ComplexLongDoubleUsesFP2Ret = true;
3661 
3662     // x86-64 has atomics up to 16 bytes.
3663     MaxAtomicPromoteWidth = 128;
3664     MaxAtomicInlineWidth = 128;
3665   }
3666   BuiltinVaListKind getBuiltinVaListKind() const override {
3667     return TargetInfo::X86_64ABIBuiltinVaList;
3668   }
3669 
3670   int getEHDataRegisterNumber(unsigned RegNo) const override {
3671     if (RegNo == 0) return 0;
3672     if (RegNo == 1) return 1;
3673     return -1;
3674   }
3675 
3676   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3677     return (CC == CC_C ||
3678             CC == CC_X86VectorCall ||
3679             CC == CC_IntelOclBicc ||
3680             CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
3681   }
3682 
3683   CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3684     return CC_C;
3685   }
3686 
3687   // for x32 we need it here explicitly
3688   bool hasInt128Type() const override { return true; }
3689 };
3690 } // end anonymous namespace
3691 
3692 namespace {
3693 // x86-64 Windows target
3694 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3695 public:
3696   WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3697       : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3698     WCharType = UnsignedShort;
3699     LongWidth = LongAlign = 32;
3700     DoubleAlign = LongLongAlign = 64;
3701     IntMaxType = SignedLongLong;
3702     Int64Type = SignedLongLong;
3703     SizeType = UnsignedLongLong;
3704     PtrDiffType = SignedLongLong;
3705     IntPtrType = SignedLongLong;
3706     this->UserLabelPrefix = "";
3707   }
3708 
3709   void getTargetDefines(const LangOptions &Opts,
3710                                 MacroBuilder &Builder) const override {
3711     WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3712     Builder.defineMacro("_WIN64");
3713   }
3714 
3715   BuiltinVaListKind getBuiltinVaListKind() const override {
3716     return TargetInfo::CharPtrBuiltinVaList;
3717   }
3718 
3719   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3720     switch (CC) {
3721     case CC_X86StdCall:
3722     case CC_X86ThisCall:
3723     case CC_X86FastCall:
3724       return CCCR_Ignore;
3725     case CC_C:
3726     case CC_X86VectorCall:
3727     case CC_IntelOclBicc:
3728     case CC_X86_64SysV:
3729       return CCCR_OK;
3730     default:
3731       return CCCR_Warning;
3732     }
3733   }
3734 };
3735 } // end anonymous namespace
3736 
3737 namespace {
3738 // x86-64 Windows Visual Studio target
3739 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
3740 public:
3741   MicrosoftX86_64TargetInfo(const llvm::Triple &Triple)
3742       : WindowsX86_64TargetInfo(Triple) {
3743     LongDoubleWidth = LongDoubleAlign = 64;
3744     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3745   }
3746   void getTargetDefines(const LangOptions &Opts,
3747                         MacroBuilder &Builder) const override {
3748     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3749     WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3750     Builder.defineMacro("_M_X64");
3751     Builder.defineMacro("_M_AMD64");
3752   }
3753 };
3754 } // end anonymous namespace
3755 
3756 namespace {
3757 // x86-64 MinGW target
3758 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3759 public:
3760   MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3761       : WindowsX86_64TargetInfo(Triple) {}
3762   void getTargetDefines(const LangOptions &Opts,
3763                         MacroBuilder &Builder) const override {
3764     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3765     DefineStd(Builder, "WIN64", Opts);
3766     Builder.defineMacro("__MINGW64__");
3767     addMinGWDefines(Opts, Builder);
3768 
3769     // GCC defines this macro when it is using __gxx_personality_seh0.
3770     if (!Opts.SjLjExceptions)
3771       Builder.defineMacro("__SEH__");
3772   }
3773 };
3774 } // end anonymous namespace
3775 
3776 namespace {
3777 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3778 public:
3779   DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3780       : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3781     Int64Type = SignedLongLong;
3782     MaxVectorAlign = 256;
3783     // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
3784     llvm::Triple T = llvm::Triple(Triple);
3785     if (T.isiOS())
3786       UseSignedCharForObjCBool = false;
3787     DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
3788   }
3789 };
3790 } // end anonymous namespace
3791 
3792 namespace {
3793 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3794 public:
3795   OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
3796       : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
3797     IntMaxType = SignedLongLong;
3798     Int64Type = SignedLongLong;
3799   }
3800 };
3801 } // end anonymous namespace
3802 
3803 namespace {
3804 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3805 public:
3806   BitrigX86_64TargetInfo(const llvm::Triple &Triple)
3807       : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
3808     IntMaxType = SignedLongLong;
3809     Int64Type = SignedLongLong;
3810   }
3811 };
3812 }
3813 
3814 
3815 namespace {
3816 class ARMTargetInfo : public TargetInfo {
3817   // Possible FPU choices.
3818   enum FPUMode {
3819     VFP2FPU = (1 << 0),
3820     VFP3FPU = (1 << 1),
3821     VFP4FPU = (1 << 2),
3822     NeonFPU = (1 << 3),
3823     FPARMV8 = (1 << 4)
3824   };
3825 
3826   // Possible HWDiv features.
3827   enum HWDivMode {
3828     HWDivThumb = (1 << 0),
3829     HWDivARM = (1 << 1)
3830   };
3831 
3832   static bool FPUModeIsVFP(FPUMode Mode) {
3833     return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
3834   }
3835 
3836   static const TargetInfo::GCCRegAlias GCCRegAliases[];
3837   static const char * const GCCRegNames[];
3838 
3839   std::string ABI, CPU;
3840 
3841   enum {
3842     FP_Default,
3843     FP_VFP,
3844     FP_Neon
3845   } FPMath;
3846 
3847   unsigned FPU : 5;
3848 
3849   unsigned IsAAPCS : 1;
3850   unsigned IsThumb : 1;
3851   unsigned HWDiv : 2;
3852 
3853   // Initialized via features.
3854   unsigned SoftFloat : 1;
3855   unsigned SoftFloatABI : 1;
3856 
3857   unsigned CRC : 1;
3858   unsigned Crypto : 1;
3859 
3860   // ACLE 6.5.1 Hardware floating point
3861   enum {
3862     HW_FP_HP = (1 << 1), /// half (16-bit)
3863     HW_FP_SP = (1 << 2), /// single (32-bit)
3864     HW_FP_DP = (1 << 3), /// double (64-bit)
3865   };
3866   uint32_t HW_FP;
3867 
3868   static const Builtin::Info BuiltinInfo[];
3869 
3870   static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3871     StringRef ArchName = T.getArchName();
3872     if (T.getArch() == llvm::Triple::arm ||
3873         T.getArch() == llvm::Triple::armeb) {
3874       StringRef VersionStr;
3875       if (ArchName.startswith("armv"))
3876         VersionStr = ArchName.substr(4, 1);
3877       else if (ArchName.startswith("armebv"))
3878         VersionStr = ArchName.substr(6, 1);
3879       else
3880         return false;
3881       unsigned Version;
3882       if (VersionStr.getAsInteger(10, Version))
3883         return false;
3884       return Version >= 6;
3885     }
3886     assert(T.getArch() == llvm::Triple::thumb ||
3887            T.getArch() == llvm::Triple::thumbeb);
3888     StringRef VersionStr;
3889     if (ArchName.startswith("thumbv"))
3890       VersionStr = ArchName.substr(6, 1);
3891     else if (ArchName.startswith("thumbebv"))
3892       VersionStr = ArchName.substr(8, 1);
3893     else
3894       return false;
3895     unsigned Version;
3896     if (VersionStr.getAsInteger(10, Version))
3897       return false;
3898     return Version >= 7;
3899   }
3900 
3901   void setABIAAPCS() {
3902     IsAAPCS = true;
3903 
3904     DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
3905     const llvm::Triple &T = getTriple();
3906 
3907     // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig.
3908     if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD ||
3909         T.getOS() == llvm::Triple::Bitrig)
3910       SizeType = UnsignedLong;
3911     else
3912       SizeType = UnsignedInt;
3913 
3914     switch (T.getOS()) {
3915     case llvm::Triple::NetBSD:
3916       WCharType = SignedInt;
3917       break;
3918     case llvm::Triple::Win32:
3919       WCharType = UnsignedShort;
3920       break;
3921     case llvm::Triple::Linux:
3922     default:
3923       // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3924       WCharType = UnsignedInt;
3925       break;
3926     }
3927 
3928     UseBitFieldTypeAlignment = true;
3929 
3930     ZeroLengthBitfieldBoundary = 0;
3931 
3932     // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3933     // so set preferred for small types to 32.
3934     if (T.isOSBinFormatMachO()) {
3935       DescriptionString =
3936           BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
3937                     : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
3938     } else if (T.isOSWindows()) {
3939       assert(!BigEndian && "Windows on ARM does not support big endian");
3940       DescriptionString = "e"
3941                           "-m:w"
3942                           "-p:32:32"
3943                           "-i64:64"
3944                           "-v128:64:128"
3945                           "-a:0:32"
3946                           "-n32"
3947                           "-S64";
3948     } else {
3949       DescriptionString =
3950           BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
3951                     : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
3952     }
3953 
3954     // FIXME: Enumerated types are variable width in straight AAPCS.
3955   }
3956 
3957   void setABIAPCS() {
3958     const llvm::Triple &T = getTriple();
3959 
3960     IsAAPCS = false;
3961 
3962     DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3963 
3964     // size_t is unsigned int on FreeBSD.
3965     if (T.getOS() == llvm::Triple::FreeBSD)
3966       SizeType = UnsignedInt;
3967     else
3968       SizeType = UnsignedLong;
3969 
3970     // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3971     WCharType = SignedInt;
3972 
3973     // Do not respect the alignment of bit-field types when laying out
3974     // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3975     UseBitFieldTypeAlignment = false;
3976 
3977     /// gcc forces the alignment to 4 bytes, regardless of the type of the
3978     /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
3979     /// gcc.
3980     ZeroLengthBitfieldBoundary = 32;
3981 
3982     if (T.isOSBinFormatMachO())
3983       DescriptionString =
3984           BigEndian
3985               ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
3986               : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3987     else
3988       DescriptionString =
3989           BigEndian
3990               ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
3991               : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3992 
3993     // FIXME: Override "preferred align" for double and long long.
3994   }
3995 
3996 public:
3997   ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
3998       : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default),
3999         IsAAPCS(true), HW_FP(0) {
4000     BigEndian = IsBigEndian;
4001 
4002     switch (getTriple().getOS()) {
4003     case llvm::Triple::NetBSD:
4004       PtrDiffType = SignedLong;
4005       break;
4006     default:
4007       PtrDiffType = SignedInt;
4008       break;
4009     }
4010 
4011     // {} in inline assembly are neon specifiers, not assembly variant
4012     // specifiers.
4013     NoAsmVariants = true;
4014 
4015     // FIXME: Should we just treat this as a feature?
4016     IsThumb = getTriple().getArchName().startswith("thumb");
4017 
4018     // FIXME: This duplicates code from the driver that sets the -target-abi
4019     // option - this code is used if -target-abi isn't passed and should
4020     // be unified in some way.
4021     if (Triple.isOSBinFormatMachO()) {
4022       // The backend is hardwired to assume AAPCS for M-class processors, ensure
4023       // the frontend matches that.
4024       if (Triple.getEnvironment() == llvm::Triple::EABI ||
4025           Triple.getOS() == llvm::Triple::UnknownOS ||
4026           StringRef(CPU).startswith("cortex-m")) {
4027         setABI("aapcs");
4028       } else {
4029         setABI("apcs-gnu");
4030       }
4031     } else if (Triple.isOSWindows()) {
4032       // FIXME: this is invalid for WindowsCE
4033       setABI("aapcs");
4034     } else {
4035       // Select the default based on the platform.
4036       switch (Triple.getEnvironment()) {
4037       case llvm::Triple::Android:
4038       case llvm::Triple::GNUEABI:
4039       case llvm::Triple::GNUEABIHF:
4040         setABI("aapcs-linux");
4041         break;
4042       case llvm::Triple::EABIHF:
4043       case llvm::Triple::EABI:
4044         setABI("aapcs");
4045         break;
4046       case llvm::Triple::GNU:
4047 	setABI("apcs-gnu");
4048 	break;
4049       default:
4050         if (Triple.getOS() == llvm::Triple::NetBSD)
4051           setABI("apcs-gnu");
4052         else
4053           setABI("aapcs");
4054         break;
4055       }
4056     }
4057 
4058     // ARM targets default to using the ARM C++ ABI.
4059     TheCXXABI.set(TargetCXXABI::GenericARM);
4060 
4061     // ARM has atomics up to 8 bytes
4062     MaxAtomicPromoteWidth = 64;
4063     if (shouldUseInlineAtomic(getTriple()))
4064       MaxAtomicInlineWidth = 64;
4065 
4066     // Do force alignment of members that follow zero length bitfields.  If
4067     // the alignment of the zero-length bitfield is greater than the member
4068     // that follows it, `bar', `bar' will be aligned as the  type of the
4069     // zero length bitfield.
4070     UseZeroLengthBitfieldAlignment = true;
4071   }
4072   StringRef getABI() const override { return ABI; }
4073   bool setABI(const std::string &Name) override {
4074     ABI = Name;
4075 
4076     // The defaults (above) are for AAPCS, check if we need to change them.
4077     //
4078     // FIXME: We need support for -meabi... we could just mangle it into the
4079     // name.
4080     if (Name == "apcs-gnu") {
4081       setABIAPCS();
4082       return true;
4083     }
4084     if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
4085       setABIAAPCS();
4086       return true;
4087     }
4088     return false;
4089   }
4090 
4091   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
4092     StringRef ArchName = getTriple().getArchName();
4093     if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
4094       Features["vfp2"] = true;
4095     else if (CPU == "cortex-a8" || CPU == "cortex-a9") {
4096       Features["vfp3"] = true;
4097       Features["neon"] = true;
4098     }
4099     else if (CPU == "cortex-a5") {
4100       Features["vfp4"] = true;
4101       Features["neon"] = true;
4102     } else if (CPU == "swift" || CPU == "cortex-a7" ||
4103                CPU == "cortex-a12" || CPU == "cortex-a15" ||
4104                CPU == "cortex-a17" || CPU == "krait") {
4105       Features["vfp4"] = true;
4106       Features["neon"] = true;
4107       Features["hwdiv"] = true;
4108       Features["hwdiv-arm"] = true;
4109     } else if (CPU == "cyclone") {
4110       Features["v8fp"] = true;
4111       Features["neon"] = true;
4112       Features["hwdiv"] = true;
4113       Features["hwdiv-arm"] = true;
4114     } else if (CPU == "cortex-a53" || CPU == "cortex-a57" || CPU == "cortex-a72") {
4115       Features["fp-armv8"] = true;
4116       Features["neon"] = true;
4117       Features["hwdiv"] = true;
4118       Features["hwdiv-arm"] = true;
4119       Features["crc"] = true;
4120       Features["crypto"] = true;
4121     } else if (CPU == "cortex-r5" || CPU == "cortex-r7" ||
4122                // Enable the hwdiv extension for all v8a AArch32 cores by
4123                // default.
4124                ArchName == "armv8a" || ArchName == "armv8" ||
4125                ArchName == "armebv8a" || ArchName == "armebv8" ||
4126                ArchName == "thumbv8a" || ArchName == "thumbv8" ||
4127                ArchName == "thumbebv8a" || ArchName == "thumbebv8") {
4128       Features["hwdiv"] = true;
4129       Features["hwdiv-arm"] = true;
4130     } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" ||
4131                CPU == "sc300") {
4132       Features["hwdiv"] = true;
4133     }
4134   }
4135 
4136   bool handleTargetFeatures(std::vector<std::string> &Features,
4137                             DiagnosticsEngine &Diags) override {
4138     FPU = 0;
4139     CRC = 0;
4140     Crypto = 0;
4141     SoftFloat = SoftFloatABI = false;
4142     HWDiv = 0;
4143 
4144     for (const auto &Feature : Features) {
4145       if (Feature == "+soft-float") {
4146         SoftFloat = true;
4147       } else if (Feature == "+soft-float-abi") {
4148         SoftFloatABI = true;
4149       } else if (Feature == "+vfp2") {
4150         FPU |= VFP2FPU;
4151         HW_FP = HW_FP_SP | HW_FP_DP;
4152       } else if (Feature == "+vfp3") {
4153         FPU |= VFP3FPU;
4154         HW_FP = HW_FP_SP | HW_FP_DP;
4155       } else if (Feature == "+vfp4") {
4156         FPU |= VFP4FPU;
4157         HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
4158       } else if (Feature == "+fp-armv8") {
4159         FPU |= FPARMV8;
4160         HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
4161       } else if (Feature == "+neon") {
4162         FPU |= NeonFPU;
4163         HW_FP = HW_FP_SP | HW_FP_DP;
4164       } else if (Feature == "+hwdiv") {
4165         HWDiv |= HWDivThumb;
4166       } else if (Feature == "+hwdiv-arm") {
4167         HWDiv |= HWDivARM;
4168       } else if (Feature == "+crc") {
4169         CRC = 1;
4170       } else if (Feature == "+crypto") {
4171         Crypto = 1;
4172       } else if (Feature == "+fp-only-sp") {
4173         HW_FP &= ~HW_FP_DP;
4174       }
4175     }
4176 
4177     if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
4178       Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
4179       return false;
4180     }
4181 
4182     if (FPMath == FP_Neon)
4183       Features.push_back("+neonfp");
4184     else if (FPMath == FP_VFP)
4185       Features.push_back("-neonfp");
4186 
4187     // Remove front-end specific options which the backend handles differently.
4188     const StringRef FrontEndFeatures[] = { "+soft-float", "+soft-float-abi" };
4189     for (const auto &FEFeature : FrontEndFeatures) {
4190       auto Feature = std::find(Features.begin(), Features.end(), FEFeature);
4191       if (Feature != Features.end())
4192         Features.erase(Feature);
4193     }
4194 
4195     return true;
4196   }
4197 
4198   bool hasFeature(StringRef Feature) const override {
4199     return llvm::StringSwitch<bool>(Feature)
4200         .Case("arm", true)
4201         .Case("softfloat", SoftFloat)
4202         .Case("thumb", IsThumb)
4203         .Case("neon", (FPU & NeonFPU) && !SoftFloat)
4204         .Case("hwdiv", HWDiv & HWDivThumb)
4205         .Case("hwdiv-arm", HWDiv & HWDivARM)
4206         .Default(false);
4207   }
4208   // FIXME: Should we actually have some table instead of these switches?
4209   static const char *getCPUDefineSuffix(StringRef Name) {
4210     return llvm::StringSwitch<const char *>(Name)
4211         .Cases("arm8", "arm810", "4")
4212         .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110",
4213                "4")
4214         .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
4215         .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
4216         .Case("ep9312", "4T")
4217         .Cases("arm10tdmi", "arm1020t", "5T")
4218         .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
4219         .Case("arm926ej-s", "5TEJ")
4220         .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
4221         .Cases("xscale", "iwmmxt", "5TE")
4222         .Case("arm1136j-s", "6J")
4223         .Case("arm1136jf-s", "6")
4224         .Cases("mpcorenovfp", "mpcore", "6K")
4225         .Cases("arm1176jz-s", "arm1176jzf-s", "6K")
4226         .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
4227         .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
4228         .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
4229                "7A")
4230         .Cases("cortex-r4", "cortex-r5", "cortex-r7", "7R")
4231         .Case("swift", "7S")
4232         .Case("cyclone", "8A")
4233         .Cases("sc300", "cortex-m3", "7M")
4234         .Cases("cortex-m4", "cortex-m7", "7EM")
4235         .Cases("sc000", "cortex-m0", "cortex-m0plus", "cortex-m1", "6M")
4236         .Cases("cortex-a53", "cortex-a57", "cortex-a72", "8A")
4237         .Default(nullptr);
4238   }
4239   static const char *getCPUProfile(StringRef Name) {
4240     return llvm::StringSwitch<const char *>(Name)
4241         .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A")
4242         .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
4243                "A")
4244         .Cases("cortex-a53", "cortex-a57", "cortex-a72", "A")
4245         .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m0plus", "M")
4246         .Cases("cortex-m1", "cortex-m7", "sc000", "sc300", "M")
4247         .Cases("cortex-r4", "cortex-r5", "cortex-r7", "R")
4248         .Default("");
4249   }
4250   bool setCPU(const std::string &Name) override {
4251     if (!getCPUDefineSuffix(Name))
4252       return false;
4253 
4254     // Cortex M does not support 8 byte atomics, while general Thumb2 does.
4255     StringRef Profile = getCPUProfile(Name);
4256     if (Profile == "M" && MaxAtomicInlineWidth) {
4257       MaxAtomicPromoteWidth = 32;
4258       MaxAtomicInlineWidth = 32;
4259     }
4260 
4261     CPU = Name;
4262     return true;
4263   }
4264   bool setFPMath(StringRef Name) override;
4265   bool supportsThumb(StringRef ArchName, StringRef CPUArch,
4266                      unsigned CPUArchVer) const {
4267     return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) ||
4268            (CPUArch.find('M') != StringRef::npos);
4269   }
4270   bool supportsThumb2(StringRef ArchName, StringRef CPUArch,
4271                       unsigned CPUArchVer) const {
4272     // We check both CPUArchVer and ArchName because when only triple is
4273     // specified, the default CPU is arm1136j-s.
4274     return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
4275            ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
4276   }
4277   void getTargetDefines(const LangOptions &Opts,
4278                         MacroBuilder &Builder) const override {
4279     // Target identification.
4280     Builder.defineMacro("__arm");
4281     Builder.defineMacro("__arm__");
4282 
4283     // Target properties.
4284     Builder.defineMacro("__REGISTER_PREFIX__", "");
4285 
4286     StringRef CPUArch = getCPUDefineSuffix(CPU);
4287     unsigned int CPUArchVer;
4288     if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer))
4289       llvm_unreachable("Invalid char for architecture version number");
4290     Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
4291 
4292     // ACLE 6.4.1 ARM/Thumb instruction set architecture
4293     StringRef CPUProfile = getCPUProfile(CPU);
4294     StringRef ArchName = getTriple().getArchName();
4295 
4296     // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
4297     Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
4298     if (CPUArch[0] >= '8') {
4299       Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4300       Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4301     }
4302 
4303     // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA.  It
4304     // is not defined for the M-profile.
4305     // NOTE that the deffault profile is assumed to be 'A'
4306     if (CPUProfile.empty() || CPUProfile != "M")
4307       Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
4308 
4309     // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
4310     // Thumb ISA (including v6-M).  It is set to 2 if the core supports the
4311     // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
4312     if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4313       Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
4314     else if (supportsThumb(ArchName, CPUArch, CPUArchVer))
4315       Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
4316 
4317     // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
4318     // instruction set such as ARM or Thumb.
4319     Builder.defineMacro("__ARM_32BIT_STATE", "1");
4320 
4321     // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
4322 
4323     // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
4324     if (!CPUProfile.empty())
4325       Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
4326 
4327     // ACLE 6.5.1 Hardware Floating Point
4328     if (HW_FP)
4329       Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
4330 
4331     // ACLE predefines.
4332     Builder.defineMacro("__ARM_ACLE", "200");
4333 
4334     // Subtarget options.
4335 
4336     // FIXME: It's more complicated than this and we don't really support
4337     // interworking.
4338     // Windows on ARM does not "support" interworking
4339     if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows())
4340       Builder.defineMacro("__THUMB_INTERWORK__");
4341 
4342     if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
4343       // Embedded targets on Darwin follow AAPCS, but not EABI.
4344       // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
4345       if (!getTriple().isOSDarwin() && !getTriple().isOSWindows())
4346         Builder.defineMacro("__ARM_EABI__");
4347       Builder.defineMacro("__ARM_PCS", "1");
4348 
4349       if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
4350         Builder.defineMacro("__ARM_PCS_VFP", "1");
4351     }
4352 
4353     if (SoftFloat)
4354       Builder.defineMacro("__SOFTFP__");
4355 
4356     if (CPU == "xscale")
4357       Builder.defineMacro("__XSCALE__");
4358 
4359     if (IsThumb) {
4360       Builder.defineMacro("__THUMBEL__");
4361       Builder.defineMacro("__thumb__");
4362       if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4363         Builder.defineMacro("__thumb2__");
4364     }
4365     if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
4366       Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
4367 
4368     // Note, this is always on in gcc, even though it doesn't make sense.
4369     Builder.defineMacro("__APCS_32__");
4370 
4371     if (FPUModeIsVFP((FPUMode) FPU)) {
4372       Builder.defineMacro("__VFP_FP__");
4373       if (FPU & VFP2FPU)
4374         Builder.defineMacro("__ARM_VFPV2__");
4375       if (FPU & VFP3FPU)
4376         Builder.defineMacro("__ARM_VFPV3__");
4377       if (FPU & VFP4FPU)
4378         Builder.defineMacro("__ARM_VFPV4__");
4379     }
4380 
4381     // This only gets set when Neon instructions are actually available, unlike
4382     // the VFP define, hence the soft float and arch check. This is subtly
4383     // different from gcc, we follow the intent which was that it should be set
4384     // when Neon instructions are actually available.
4385     if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) {
4386       Builder.defineMacro("__ARM_NEON");
4387       Builder.defineMacro("__ARM_NEON__");
4388     }
4389 
4390     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
4391                         Opts.ShortWChar ? "2" : "4");
4392 
4393     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4394                         Opts.ShortEnums ? "1" : "4");
4395 
4396     if (CRC)
4397       Builder.defineMacro("__ARM_FEATURE_CRC32");
4398 
4399     if (Crypto)
4400       Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4401 
4402     if (CPUArchVer >= 6 && CPUArch != "6M") {
4403       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4404       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4405       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4406       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4407     }
4408 
4409     bool is5EOrAbove = (CPUArchVer >= 6 ||
4410                         (CPUArchVer == 5 &&
4411                          CPUArch.find('E') != StringRef::npos));
4412     bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer));
4413     if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch  == "7EM"))
4414       Builder.defineMacro("__ARM_FEATURE_DSP");
4415   }
4416   void getTargetBuiltins(const Builtin::Info *&Records,
4417                          unsigned &NumRecords) const override {
4418     Records = BuiltinInfo;
4419     NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
4420   }
4421   bool isCLZForZeroUndef() const override { return false; }
4422   BuiltinVaListKind getBuiltinVaListKind() const override {
4423     return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
4424   }
4425   void getGCCRegNames(const char * const *&Names,
4426                       unsigned &NumNames) const override;
4427   void getGCCRegAliases(const GCCRegAlias *&Aliases,
4428                         unsigned &NumAliases) const override;
4429   bool validateAsmConstraint(const char *&Name,
4430                              TargetInfo::ConstraintInfo &Info) const override {
4431     switch (*Name) {
4432     default: break;
4433     case 'l': // r0-r7
4434     case 'h': // r8-r15
4435     case 'w': // VFP Floating point register single precision
4436     case 'P': // VFP Floating point register double precision
4437       Info.setAllowsRegister();
4438       return true;
4439     case 'I':
4440     case 'J':
4441     case 'K':
4442     case 'L':
4443     case 'M':
4444       // FIXME
4445       return true;
4446     case 'Q': // A memory address that is a single base register.
4447       Info.setAllowsMemory();
4448       return true;
4449     case 'U': // a memory reference...
4450       switch (Name[1]) {
4451       case 'q': // ...ARMV4 ldrsb
4452       case 'v': // ...VFP load/store (reg+constant offset)
4453       case 'y': // ...iWMMXt load/store
4454       case 't': // address valid for load/store opaque types wider
4455                 // than 128-bits
4456       case 'n': // valid address for Neon doubleword vector load/store
4457       case 'm': // valid address for Neon element and structure load/store
4458       case 's': // valid address for non-offset loads/stores of quad-word
4459                 // values in four ARM registers
4460         Info.setAllowsMemory();
4461         Name++;
4462         return true;
4463       }
4464     }
4465     return false;
4466   }
4467   std::string convertConstraint(const char *&Constraint) const override {
4468     std::string R;
4469     switch (*Constraint) {
4470     case 'U':   // Two-character constraint; add "^" hint for later parsing.
4471       R = std::string("^") + std::string(Constraint, 2);
4472       Constraint++;
4473       break;
4474     case 'p': // 'p' should be translated to 'r' by default.
4475       R = std::string("r");
4476       break;
4477     default:
4478       return std::string(1, *Constraint);
4479     }
4480     return R;
4481   }
4482   bool
4483   validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4484                              std::string &SuggestedModifier) const override {
4485     bool isOutput = (Constraint[0] == '=');
4486     bool isInOut = (Constraint[0] == '+');
4487 
4488     // Strip off constraint modifiers.
4489     while (Constraint[0] == '=' ||
4490            Constraint[0] == '+' ||
4491            Constraint[0] == '&')
4492       Constraint = Constraint.substr(1);
4493 
4494     switch (Constraint[0]) {
4495     default: break;
4496     case 'r': {
4497       switch (Modifier) {
4498       default:
4499         return (isInOut || isOutput || Size <= 64);
4500       case 'q':
4501         // A register of size 32 cannot fit a vector type.
4502         return false;
4503       }
4504     }
4505     }
4506 
4507     return true;
4508   }
4509   const char *getClobbers() const override {
4510     // FIXME: Is this really right?
4511     return "";
4512   }
4513 
4514   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4515     return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
4516   }
4517 
4518   int getEHDataRegisterNumber(unsigned RegNo) const override {
4519     if (RegNo == 0) return 0;
4520     if (RegNo == 1) return 1;
4521     return -1;
4522   }
4523 };
4524 
4525 bool ARMTargetInfo::setFPMath(StringRef Name) {
4526   if (Name == "neon") {
4527     FPMath = FP_Neon;
4528     return true;
4529   } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
4530              Name == "vfp4") {
4531     FPMath = FP_VFP;
4532     return true;
4533   }
4534   return false;
4535 }
4536 
4537 const char * const ARMTargetInfo::GCCRegNames[] = {
4538   // Integer registers
4539   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4540   "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
4541 
4542   // Float registers
4543   "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
4544   "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
4545   "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
4546   "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4547 
4548   // Double registers
4549   "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
4550   "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
4551   "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
4552   "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4553 
4554   // Quad registers
4555   "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
4556   "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
4557 };
4558 
4559 void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
4560                                    unsigned &NumNames) const {
4561   Names = GCCRegNames;
4562   NumNames = llvm::array_lengthof(GCCRegNames);
4563 }
4564 
4565 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
4566   { { "a1" }, "r0" },
4567   { { "a2" }, "r1" },
4568   { { "a3" }, "r2" },
4569   { { "a4" }, "r3" },
4570   { { "v1" }, "r4" },
4571   { { "v2" }, "r5" },
4572   { { "v3" }, "r6" },
4573   { { "v4" }, "r7" },
4574   { { "v5" }, "r8" },
4575   { { "v6", "rfp" }, "r9" },
4576   { { "sl" }, "r10" },
4577   { { "fp" }, "r11" },
4578   { { "ip" }, "r12" },
4579   { { "r13" }, "sp" },
4580   { { "r14" }, "lr" },
4581   { { "r15" }, "pc" },
4582   // The S, D and Q registers overlap, but aren't really aliases; we
4583   // don't want to substitute one of these for a different-sized one.
4584 };
4585 
4586 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4587                                        unsigned &NumAliases) const {
4588   Aliases = GCCRegAliases;
4589   NumAliases = llvm::array_lengthof(GCCRegAliases);
4590 }
4591 
4592 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
4593 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4594 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4595                                               ALL_LANGUAGES },
4596 #include "clang/Basic/BuiltinsNEON.def"
4597 
4598 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4599 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG },
4600 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4601                                               ALL_LANGUAGES },
4602 #include "clang/Basic/BuiltinsARM.def"
4603 };
4604 
4605 class ARMleTargetInfo : public ARMTargetInfo {
4606 public:
4607   ARMleTargetInfo(const llvm::Triple &Triple)
4608     : ARMTargetInfo(Triple, false) { }
4609   virtual void getTargetDefines(const LangOptions &Opts,
4610                                 MacroBuilder &Builder) const {
4611     Builder.defineMacro("__ARMEL__");
4612     ARMTargetInfo::getTargetDefines(Opts, Builder);
4613   }
4614 };
4615 
4616 class ARMbeTargetInfo : public ARMTargetInfo {
4617 public:
4618   ARMbeTargetInfo(const llvm::Triple &Triple)
4619     : ARMTargetInfo(Triple, true) { }
4620   virtual void getTargetDefines(const LangOptions &Opts,
4621                                 MacroBuilder &Builder) const {
4622     Builder.defineMacro("__ARMEB__");
4623     Builder.defineMacro("__ARM_BIG_ENDIAN");
4624     ARMTargetInfo::getTargetDefines(Opts, Builder);
4625   }
4626 };
4627 } // end anonymous namespace.
4628 
4629 namespace {
4630 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
4631   const llvm::Triple Triple;
4632 public:
4633   WindowsARMTargetInfo(const llvm::Triple &Triple)
4634     : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) {
4635     TLSSupported = false;
4636     WCharType = UnsignedShort;
4637     SizeType = UnsignedInt;
4638     UserLabelPrefix = "";
4639   }
4640   void getVisualStudioDefines(const LangOptions &Opts,
4641                               MacroBuilder &Builder) const {
4642     WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
4643 
4644     // FIXME: this is invalid for WindowsCE
4645     Builder.defineMacro("_M_ARM_NT", "1");
4646     Builder.defineMacro("_M_ARMT", "_M_ARM");
4647     Builder.defineMacro("_M_THUMB", "_M_ARM");
4648 
4649     assert((Triple.getArch() == llvm::Triple::arm ||
4650             Triple.getArch() == llvm::Triple::thumb) &&
4651            "invalid architecture for Windows ARM target info");
4652     unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
4653     Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
4654 
4655     // TODO map the complete set of values
4656     // 31: VFPv3 40: VFPv4
4657     Builder.defineMacro("_M_ARM_FP", "31");
4658   }
4659   BuiltinVaListKind getBuiltinVaListKind() const override {
4660     return TargetInfo::CharPtrBuiltinVaList;
4661   }
4662 };
4663 
4664 // Windows ARM + Itanium C++ ABI Target
4665 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
4666 public:
4667   ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple)
4668     : WindowsARMTargetInfo(Triple) {
4669     TheCXXABI.set(TargetCXXABI::GenericARM);
4670   }
4671 
4672   void getTargetDefines(const LangOptions &Opts,
4673                         MacroBuilder &Builder) const override {
4674     WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4675 
4676     if (Opts.MSVCCompat)
4677       WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4678   }
4679 };
4680 
4681 // Windows ARM, MS (C++) ABI
4682 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
4683 public:
4684   MicrosoftARMleTargetInfo(const llvm::Triple &Triple)
4685     : WindowsARMTargetInfo(Triple) {
4686     TheCXXABI.set(TargetCXXABI::Microsoft);
4687   }
4688 
4689   void getTargetDefines(const LangOptions &Opts,
4690                         MacroBuilder &Builder) const override {
4691     WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4692     WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4693   }
4694 };
4695 }
4696 
4697 
4698 namespace {
4699 class DarwinARMTargetInfo :
4700   public DarwinTargetInfo<ARMleTargetInfo> {
4701 protected:
4702   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4703                     MacroBuilder &Builder) const override {
4704     getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4705   }
4706 
4707 public:
4708   DarwinARMTargetInfo(const llvm::Triple &Triple)
4709       : DarwinTargetInfo<ARMleTargetInfo>(Triple) {
4710     HasAlignMac68kSupport = true;
4711     // iOS always has 64-bit atomic instructions.
4712     // FIXME: This should be based off of the target features in
4713     // ARMleTargetInfo.
4714     MaxAtomicInlineWidth = 64;
4715 
4716     // Darwin on iOS uses a variant of the ARM C++ ABI.
4717     TheCXXABI.set(TargetCXXABI::iOS);
4718   }
4719 };
4720 } // end anonymous namespace.
4721 
4722 
4723 namespace {
4724 class AArch64TargetInfo : public TargetInfo {
4725   virtual void setDescriptionString() = 0;
4726   static const TargetInfo::GCCRegAlias GCCRegAliases[];
4727   static const char *const GCCRegNames[];
4728 
4729   enum FPUModeEnum {
4730     FPUMode,
4731     NeonMode
4732   };
4733 
4734   unsigned FPU;
4735   unsigned CRC;
4736   unsigned Crypto;
4737 
4738   static const Builtin::Info BuiltinInfo[];
4739 
4740   std::string ABI;
4741 
4742 public:
4743   AArch64TargetInfo(const llvm::Triple &Triple)
4744       : TargetInfo(Triple), ABI("aapcs") {
4745 
4746     if (getTriple().getOS() == llvm::Triple::NetBSD) {
4747       WCharType = SignedInt;
4748 
4749       // NetBSD apparently prefers consistency across ARM targets to consistency
4750       // across 64-bit targets.
4751       Int64Type = SignedLongLong;
4752       IntMaxType = SignedLongLong;
4753     } else {
4754       WCharType = UnsignedInt;
4755       Int64Type = SignedLong;
4756       IntMaxType = SignedLong;
4757     }
4758 
4759     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4760     MaxVectorAlign = 128;
4761     RegParmMax = 8;
4762     MaxAtomicInlineWidth = 128;
4763     MaxAtomicPromoteWidth = 128;
4764 
4765     LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
4766     LongDoubleFormat = &llvm::APFloat::IEEEquad;
4767 
4768     // {} in inline assembly are neon specifiers, not assembly variant
4769     // specifiers.
4770     NoAsmVariants = true;
4771 
4772     // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
4773     // contributes to the alignment of the containing aggregate in the same way
4774     // a plain (non bit-field) member of that type would, without exception for
4775     // zero-sized or anonymous bit-fields."
4776     UseBitFieldTypeAlignment = true;
4777     UseZeroLengthBitfieldAlignment = true;
4778 
4779     // AArch64 targets default to using the ARM C++ ABI.
4780     TheCXXABI.set(TargetCXXABI::GenericAArch64);
4781   }
4782 
4783   StringRef getABI() const override { return ABI; }
4784   bool setABI(const std::string &Name) override {
4785     if (Name != "aapcs" && Name != "darwinpcs")
4786       return false;
4787 
4788     ABI = Name;
4789     return true;
4790   }
4791 
4792   bool setCPU(const std::string &Name) override {
4793     bool CPUKnown = llvm::StringSwitch<bool>(Name)
4794                         .Case("generic", true)
4795                         .Cases("cortex-a53", "cortex-a57", "cortex-a72", true)
4796                         .Case("cyclone", true)
4797                         .Default(false);
4798     return CPUKnown;
4799   }
4800 
4801   virtual void getTargetDefines(const LangOptions &Opts,
4802                                 MacroBuilder &Builder) const  override {
4803     // Target identification.
4804     Builder.defineMacro("__aarch64__");
4805 
4806     // Target properties.
4807     Builder.defineMacro("_LP64");
4808     Builder.defineMacro("__LP64__");
4809 
4810     // ACLE predefines. Many can only have one possible value on v8 AArch64.
4811     Builder.defineMacro("__ARM_ACLE", "200");
4812     Builder.defineMacro("__ARM_ARCH", "8");
4813     Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
4814 
4815     Builder.defineMacro("__ARM_64BIT_STATE");
4816     Builder.defineMacro("__ARM_PCS_AAPCS64");
4817     Builder.defineMacro("__ARM_ARCH_ISA_A64");
4818 
4819     Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
4820     Builder.defineMacro("__ARM_FEATURE_CLZ");
4821     Builder.defineMacro("__ARM_FEATURE_FMA");
4822     Builder.defineMacro("__ARM_FEATURE_DIV");
4823     Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE
4824     Builder.defineMacro("__ARM_FEATURE_DIV");  // For backwards compatibility
4825     Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4826     Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4827 
4828     Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
4829 
4830     // 0xe implies support for half, single and double precision operations.
4831     Builder.defineMacro("__ARM_FP", "0xe");
4832 
4833     // PCS specifies this for SysV variants, which is all we support. Other ABIs
4834     // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
4835     Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
4836 
4837     if (Opts.FastMath || Opts.FiniteMathOnly)
4838       Builder.defineMacro("__ARM_FP_FAST");
4839 
4840     if (Opts.C99 && !Opts.Freestanding)
4841       Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
4842 
4843     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
4844 
4845     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4846                         Opts.ShortEnums ? "1" : "4");
4847 
4848     if (FPU == NeonMode) {
4849       Builder.defineMacro("__ARM_NEON");
4850       // 64-bit NEON supports half, single and double precision operations.
4851       Builder.defineMacro("__ARM_NEON_FP", "0xe");
4852     }
4853 
4854     if (CRC)
4855       Builder.defineMacro("__ARM_FEATURE_CRC32");
4856 
4857     if (Crypto)
4858       Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4859   }
4860 
4861   virtual void getTargetBuiltins(const Builtin::Info *&Records,
4862                                  unsigned &NumRecords) const override {
4863     Records = BuiltinInfo;
4864     NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin;
4865   }
4866 
4867   bool hasFeature(StringRef Feature) const override {
4868     return Feature == "aarch64" ||
4869       Feature == "arm64" ||
4870       (Feature == "neon" && FPU == NeonMode);
4871   }
4872 
4873   bool handleTargetFeatures(std::vector<std::string> &Features,
4874                             DiagnosticsEngine &Diags) override {
4875     FPU = FPUMode;
4876     CRC = 0;
4877     Crypto = 0;
4878     for (unsigned i = 0, e = Features.size(); i != e; ++i) {
4879       if (Features[i] == "+neon")
4880         FPU = NeonMode;
4881       if (Features[i] == "+crc")
4882         CRC = 1;
4883       if (Features[i] == "+crypto")
4884         Crypto = 1;
4885     }
4886 
4887     setDescriptionString();
4888 
4889     return true;
4890   }
4891 
4892   bool isCLZForZeroUndef() const override { return false; }
4893 
4894   BuiltinVaListKind getBuiltinVaListKind() const override {
4895     return TargetInfo::AArch64ABIBuiltinVaList;
4896   }
4897 
4898   virtual void getGCCRegNames(const char *const *&Names,
4899                               unsigned &NumNames) const override;
4900   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4901                                 unsigned &NumAliases) const override;
4902 
4903   virtual bool
4904   validateAsmConstraint(const char *&Name,
4905                         TargetInfo::ConstraintInfo &Info) const override {
4906     switch (*Name) {
4907     default:
4908       return false;
4909     case 'w': // Floating point and SIMD registers (V0-V31)
4910       Info.setAllowsRegister();
4911       return true;
4912     case 'I': // Constant that can be used with an ADD instruction
4913     case 'J': // Constant that can be used with a SUB instruction
4914     case 'K': // Constant that can be used with a 32-bit logical instruction
4915     case 'L': // Constant that can be used with a 64-bit logical instruction
4916     case 'M': // Constant that can be used as a 32-bit MOV immediate
4917     case 'N': // Constant that can be used as a 64-bit MOV immediate
4918     case 'Y': // Floating point constant zero
4919     case 'Z': // Integer constant zero
4920       return true;
4921     case 'Q': // A memory reference with base register and no offset
4922       Info.setAllowsMemory();
4923       return true;
4924     case 'S': // A symbolic address
4925       Info.setAllowsRegister();
4926       return true;
4927     case 'U':
4928       // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
4929       // Utf: A memory address suitable for ldp/stp in TF mode.
4930       // Usa: An absolute symbolic address.
4931       // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
4932       llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
4933     case 'z': // Zero register, wzr or xzr
4934       Info.setAllowsRegister();
4935       return true;
4936     case 'x': // Floating point and SIMD registers (V0-V15)
4937       Info.setAllowsRegister();
4938       return true;
4939     }
4940     return false;
4941   }
4942 
4943   bool
4944   validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4945                              std::string &SuggestedModifier) const override {
4946     // Strip off constraint modifiers.
4947     while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
4948       Constraint = Constraint.substr(1);
4949 
4950     switch (Constraint[0]) {
4951     default:
4952       return true;
4953     case 'z':
4954     case 'r': {
4955       switch (Modifier) {
4956       case 'x':
4957       case 'w':
4958         // For now assume that the person knows what they're
4959         // doing with the modifier.
4960         return true;
4961       default:
4962         // By default an 'r' constraint will be in the 'x'
4963         // registers.
4964         if (Size == 64)
4965           return true;
4966 
4967         SuggestedModifier = "w";
4968         return false;
4969       }
4970     }
4971     }
4972   }
4973 
4974   const char *getClobbers() const override { return ""; }
4975 
4976   int getEHDataRegisterNumber(unsigned RegNo) const override {
4977     if (RegNo == 0)
4978       return 0;
4979     if (RegNo == 1)
4980       return 1;
4981     return -1;
4982   }
4983 };
4984 
4985 const char *const AArch64TargetInfo::GCCRegNames[] = {
4986   // 32-bit Integer registers
4987   "w0",  "w1",  "w2",  "w3",  "w4",  "w5",  "w6",  "w7",  "w8",  "w9",  "w10",
4988   "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
4989   "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
4990 
4991   // 64-bit Integer registers
4992   "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",  "x8",  "x9",  "x10",
4993   "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
4994   "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp",  "lr",  "sp",
4995 
4996   // 32-bit floating point regsisters
4997   "s0",  "s1",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",  "s8",  "s9",  "s10",
4998   "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
4999   "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5000 
5001   // 64-bit floating point regsisters
5002   "d0",  "d1",  "d2",  "d3",  "d4",  "d5",  "d6",  "d7",  "d8",  "d9",  "d10",
5003   "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
5004   "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
5005 
5006   // Vector registers
5007   "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",  "v8",  "v9",  "v10",
5008   "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
5009   "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
5010 };
5011 
5012 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names,
5013                                      unsigned &NumNames) const {
5014   Names = GCCRegNames;
5015   NumNames = llvm::array_lengthof(GCCRegNames);
5016 }
5017 
5018 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
5019   { { "w31" }, "wsp" },
5020   { { "x29" }, "fp" },
5021   { { "x30" }, "lr" },
5022   { { "x31" }, "sp" },
5023   // The S/D/Q and W/X registers overlap, but aren't really aliases; we
5024   // don't want to substitute one of these for a different-sized one.
5025 };
5026 
5027 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5028                                        unsigned &NumAliases) const {
5029   Aliases = GCCRegAliases;
5030   NumAliases = llvm::array_lengthof(GCCRegAliases);
5031 }
5032 
5033 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
5034 #define BUILTIN(ID, TYPE, ATTRS)                                               \
5035   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5036 #include "clang/Basic/BuiltinsNEON.def"
5037 
5038 #define BUILTIN(ID, TYPE, ATTRS)                                               \
5039   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5040 #include "clang/Basic/BuiltinsAArch64.def"
5041 };
5042 
5043 class AArch64leTargetInfo : public AArch64TargetInfo {
5044   void setDescriptionString() override {
5045     if (getTriple().isOSBinFormatMachO())
5046       DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128";
5047     else
5048       DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128";
5049   }
5050 
5051 public:
5052   AArch64leTargetInfo(const llvm::Triple &Triple)
5053     : AArch64TargetInfo(Triple) {
5054     BigEndian = false;
5055     }
5056   void getTargetDefines(const LangOptions &Opts,
5057                         MacroBuilder &Builder) const override {
5058     Builder.defineMacro("__AARCH64EL__");
5059     AArch64TargetInfo::getTargetDefines(Opts, Builder);
5060   }
5061 };
5062 
5063 class AArch64beTargetInfo : public AArch64TargetInfo {
5064   void setDescriptionString() override {
5065     assert(!getTriple().isOSBinFormatMachO());
5066     DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128";
5067   }
5068 
5069 public:
5070   AArch64beTargetInfo(const llvm::Triple &Triple)
5071     : AArch64TargetInfo(Triple) { }
5072   void getTargetDefines(const LangOptions &Opts,
5073                         MacroBuilder &Builder) const override {
5074     Builder.defineMacro("__AARCH64EB__");
5075     Builder.defineMacro("__AARCH_BIG_ENDIAN");
5076     Builder.defineMacro("__ARM_BIG_ENDIAN");
5077     AArch64TargetInfo::getTargetDefines(Opts, Builder);
5078   }
5079 };
5080 } // end anonymous namespace.
5081 
5082 namespace {
5083 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
5084 protected:
5085   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
5086                     MacroBuilder &Builder) const override {
5087     Builder.defineMacro("__AARCH64_SIMD__");
5088     Builder.defineMacro("__ARM64_ARCH_8__");
5089     Builder.defineMacro("__ARM_NEON__");
5090     Builder.defineMacro("__LITTLE_ENDIAN__");
5091     Builder.defineMacro("__REGISTER_PREFIX__", "");
5092     Builder.defineMacro("__arm64", "1");
5093     Builder.defineMacro("__arm64__", "1");
5094 
5095     getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
5096   }
5097 
5098 public:
5099   DarwinAArch64TargetInfo(const llvm::Triple &Triple)
5100       : DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
5101     Int64Type = SignedLongLong;
5102     WCharType = SignedInt;
5103     UseSignedCharForObjCBool = false;
5104 
5105     LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
5106     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
5107 
5108     TheCXXABI.set(TargetCXXABI::iOS64);
5109   }
5110 
5111   BuiltinVaListKind getBuiltinVaListKind() const override {
5112     return TargetInfo::CharPtrBuiltinVaList;
5113   }
5114 };
5115 } // end anonymous namespace
5116 
5117 namespace {
5118 // Hexagon abstract base class
5119 class HexagonTargetInfo : public TargetInfo {
5120   static const Builtin::Info BuiltinInfo[];
5121   static const char * const GCCRegNames[];
5122   static const TargetInfo::GCCRegAlias GCCRegAliases[];
5123   std::string CPU;
5124 public:
5125   HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5126     BigEndian = false;
5127     DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32";
5128 
5129     // {} in inline assembly are packet specifiers, not assembly variant
5130     // specifiers.
5131     NoAsmVariants = true;
5132   }
5133 
5134   void getTargetBuiltins(const Builtin::Info *&Records,
5135                          unsigned &NumRecords) const override {
5136     Records = BuiltinInfo;
5137     NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
5138   }
5139 
5140   bool validateAsmConstraint(const char *&Name,
5141                              TargetInfo::ConstraintInfo &Info) const override {
5142     return true;
5143   }
5144 
5145   void getTargetDefines(const LangOptions &Opts,
5146                         MacroBuilder &Builder) const override;
5147 
5148   bool hasFeature(StringRef Feature) const override {
5149     return Feature == "hexagon";
5150   }
5151 
5152   BuiltinVaListKind getBuiltinVaListKind() const override {
5153     return TargetInfo::CharPtrBuiltinVaList;
5154   }
5155   void getGCCRegNames(const char * const *&Names,
5156                       unsigned &NumNames) const override;
5157   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5158                         unsigned &NumAliases) const override;
5159   const char *getClobbers() const override {
5160     return "";
5161   }
5162 
5163   static const char *getHexagonCPUSuffix(StringRef Name) {
5164     return llvm::StringSwitch<const char*>(Name)
5165       .Case("hexagonv4", "4")
5166       .Case("hexagonv5", "5")
5167       .Default(nullptr);
5168   }
5169 
5170   bool setCPU(const std::string &Name) override {
5171     if (!getHexagonCPUSuffix(Name))
5172       return false;
5173 
5174     CPU = Name;
5175     return true;
5176   }
5177 };
5178 
5179 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
5180                                 MacroBuilder &Builder) const {
5181   Builder.defineMacro("qdsp6");
5182   Builder.defineMacro("__qdsp6", "1");
5183   Builder.defineMacro("__qdsp6__", "1");
5184 
5185   Builder.defineMacro("hexagon");
5186   Builder.defineMacro("__hexagon", "1");
5187   Builder.defineMacro("__hexagon__", "1");
5188 
5189   if(CPU == "hexagonv1") {
5190     Builder.defineMacro("__HEXAGON_V1__");
5191     Builder.defineMacro("__HEXAGON_ARCH__", "1");
5192     if(Opts.HexagonQdsp6Compat) {
5193       Builder.defineMacro("__QDSP6_V1__");
5194       Builder.defineMacro("__QDSP6_ARCH__", "1");
5195     }
5196   }
5197   else if(CPU == "hexagonv2") {
5198     Builder.defineMacro("__HEXAGON_V2__");
5199     Builder.defineMacro("__HEXAGON_ARCH__", "2");
5200     if(Opts.HexagonQdsp6Compat) {
5201       Builder.defineMacro("__QDSP6_V2__");
5202       Builder.defineMacro("__QDSP6_ARCH__", "2");
5203     }
5204   }
5205   else if(CPU == "hexagonv3") {
5206     Builder.defineMacro("__HEXAGON_V3__");
5207     Builder.defineMacro("__HEXAGON_ARCH__", "3");
5208     if(Opts.HexagonQdsp6Compat) {
5209       Builder.defineMacro("__QDSP6_V3__");
5210       Builder.defineMacro("__QDSP6_ARCH__", "3");
5211     }
5212   }
5213   else if(CPU == "hexagonv4") {
5214     Builder.defineMacro("__HEXAGON_V4__");
5215     Builder.defineMacro("__HEXAGON_ARCH__", "4");
5216     if(Opts.HexagonQdsp6Compat) {
5217       Builder.defineMacro("__QDSP6_V4__");
5218       Builder.defineMacro("__QDSP6_ARCH__", "4");
5219     }
5220   }
5221   else if(CPU == "hexagonv5") {
5222     Builder.defineMacro("__HEXAGON_V5__");
5223     Builder.defineMacro("__HEXAGON_ARCH__", "5");
5224     if(Opts.HexagonQdsp6Compat) {
5225       Builder.defineMacro("__QDSP6_V5__");
5226       Builder.defineMacro("__QDSP6_ARCH__", "5");
5227     }
5228   }
5229 }
5230 
5231 const char * const HexagonTargetInfo::GCCRegNames[] = {
5232   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5233   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5234   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5235   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
5236   "p0", "p1", "p2", "p3",
5237   "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
5238 };
5239 
5240 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
5241                                    unsigned &NumNames) const {
5242   Names = GCCRegNames;
5243   NumNames = llvm::array_lengthof(GCCRegNames);
5244 }
5245 
5246 
5247 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
5248   { { "sp" }, "r29" },
5249   { { "fp" }, "r30" },
5250   { { "lr" }, "r31" },
5251  };
5252 
5253 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5254                                      unsigned &NumAliases) const {
5255   Aliases = GCCRegAliases;
5256   NumAliases = llvm::array_lengthof(GCCRegAliases);
5257 }
5258 
5259 
5260 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
5261 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5262 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5263                                               ALL_LANGUAGES },
5264 #include "clang/Basic/BuiltinsHexagon.def"
5265 };
5266 }
5267 
5268 
5269 namespace {
5270 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
5271 class SparcTargetInfo : public TargetInfo {
5272   static const TargetInfo::GCCRegAlias GCCRegAliases[];
5273   static const char * const GCCRegNames[];
5274   bool SoftFloat;
5275 public:
5276   SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {}
5277 
5278   bool handleTargetFeatures(std::vector<std::string> &Features,
5279                             DiagnosticsEngine &Diags) override {
5280     SoftFloat = false;
5281     for (unsigned i = 0, e = Features.size(); i != e; ++i)
5282       if (Features[i] == "+soft-float")
5283         SoftFloat = true;
5284     return true;
5285   }
5286   void getTargetDefines(const LangOptions &Opts,
5287                         MacroBuilder &Builder) const override {
5288     DefineStd(Builder, "sparc", Opts);
5289     Builder.defineMacro("__REGISTER_PREFIX__", "");
5290 
5291     if (SoftFloat)
5292       Builder.defineMacro("SOFT_FLOAT", "1");
5293   }
5294 
5295   bool hasFeature(StringRef Feature) const override {
5296     return llvm::StringSwitch<bool>(Feature)
5297              .Case("softfloat", SoftFloat)
5298              .Case("sparc", true)
5299              .Default(false);
5300   }
5301 
5302   void getTargetBuiltins(const Builtin::Info *&Records,
5303                          unsigned &NumRecords) const override {
5304     // FIXME: Implement!
5305   }
5306   BuiltinVaListKind getBuiltinVaListKind() const override {
5307     return TargetInfo::VoidPtrBuiltinVaList;
5308   }
5309   void getGCCRegNames(const char * const *&Names,
5310                       unsigned &NumNames) const override;
5311   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5312                         unsigned &NumAliases) const override;
5313   bool validateAsmConstraint(const char *&Name,
5314                              TargetInfo::ConstraintInfo &info) const override {
5315     // FIXME: Implement!
5316     switch (*Name) {
5317     case 'I': // Signed 13-bit constant
5318     case 'J': // Zero
5319     case 'K': // 32-bit constant with the low 12 bits clear
5320     case 'L': // A constant in the range supported by movcc (11-bit signed imm)
5321     case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
5322     case 'N': // Same as 'K' but zext (required for SIMode)
5323     case 'O': // The constant 4096
5324       return true;
5325     }
5326     return false;
5327   }
5328   const char *getClobbers() const override {
5329     // FIXME: Implement!
5330     return "";
5331   }
5332 };
5333 
5334 const char * const SparcTargetInfo::GCCRegNames[] = {
5335   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5336   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5337   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5338   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5339 };
5340 
5341 void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
5342                                      unsigned &NumNames) const {
5343   Names = GCCRegNames;
5344   NumNames = llvm::array_lengthof(GCCRegNames);
5345 }
5346 
5347 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
5348   { { "g0" }, "r0" },
5349   { { "g1" }, "r1" },
5350   { { "g2" }, "r2" },
5351   { { "g3" }, "r3" },
5352   { { "g4" }, "r4" },
5353   { { "g5" }, "r5" },
5354   { { "g6" }, "r6" },
5355   { { "g7" }, "r7" },
5356   { { "o0" }, "r8" },
5357   { { "o1" }, "r9" },
5358   { { "o2" }, "r10" },
5359   { { "o3" }, "r11" },
5360   { { "o4" }, "r12" },
5361   { { "o5" }, "r13" },
5362   { { "o6", "sp" }, "r14" },
5363   { { "o7" }, "r15" },
5364   { { "l0" }, "r16" },
5365   { { "l1" }, "r17" },
5366   { { "l2" }, "r18" },
5367   { { "l3" }, "r19" },
5368   { { "l4" }, "r20" },
5369   { { "l5" }, "r21" },
5370   { { "l6" }, "r22" },
5371   { { "l7" }, "r23" },
5372   { { "i0" }, "r24" },
5373   { { "i1" }, "r25" },
5374   { { "i2" }, "r26" },
5375   { { "i3" }, "r27" },
5376   { { "i4" }, "r28" },
5377   { { "i5" }, "r29" },
5378   { { "i6", "fp" }, "r30" },
5379   { { "i7" }, "r31" },
5380 };
5381 
5382 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5383                                        unsigned &NumAliases) const {
5384   Aliases = GCCRegAliases;
5385   NumAliases = llvm::array_lengthof(GCCRegAliases);
5386 }
5387 
5388 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
5389 class SparcV8TargetInfo : public SparcTargetInfo {
5390 public:
5391   SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5392     DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
5393   }
5394 
5395   void getTargetDefines(const LangOptions &Opts,
5396                         MacroBuilder &Builder) const override {
5397     SparcTargetInfo::getTargetDefines(Opts, Builder);
5398     Builder.defineMacro("__sparcv8");
5399   }
5400 };
5401 
5402 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
5403 class SparcV9TargetInfo : public SparcTargetInfo {
5404 public:
5405   SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5406     // FIXME: Support Sparc quad-precision long double?
5407     DescriptionString = "E-m:e-i64:64-n32:64-S128";
5408     // This is an LP64 platform.
5409     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5410 
5411     // OpenBSD uses long long for int64_t and intmax_t.
5412     if (getTriple().getOS() == llvm::Triple::OpenBSD)
5413       IntMaxType = SignedLongLong;
5414     else
5415       IntMaxType = SignedLong;
5416     Int64Type = IntMaxType;
5417 
5418     // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
5419     // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
5420     LongDoubleWidth = 128;
5421     LongDoubleAlign = 128;
5422     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5423     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5424   }
5425 
5426   void getTargetDefines(const LangOptions &Opts,
5427                         MacroBuilder &Builder) const override {
5428     SparcTargetInfo::getTargetDefines(Opts, Builder);
5429     Builder.defineMacro("__sparcv9");
5430     Builder.defineMacro("__arch64__");
5431     // Solaris doesn't need these variants, but the BSDs do.
5432     if (getTriple().getOS() != llvm::Triple::Solaris) {
5433       Builder.defineMacro("__sparc64__");
5434       Builder.defineMacro("__sparc_v9__");
5435       Builder.defineMacro("__sparcv9__");
5436     }
5437   }
5438 
5439   bool setCPU(const std::string &Name) override {
5440     bool CPUKnown = llvm::StringSwitch<bool>(Name)
5441       .Case("v9", true)
5442       .Case("ultrasparc", true)
5443       .Case("ultrasparc3", true)
5444       .Case("niagara", true)
5445       .Case("niagara2", true)
5446       .Case("niagara3", true)
5447       .Case("niagara4", true)
5448       .Default(false);
5449 
5450     // No need to store the CPU yet.  There aren't any CPU-specific
5451     // macros to define.
5452     return CPUKnown;
5453   }
5454 };
5455 
5456 } // end anonymous namespace.
5457 
5458 namespace {
5459 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
5460 public:
5461   SolarisSparcV8TargetInfo(const llvm::Triple &Triple)
5462       : SolarisTargetInfo<SparcV8TargetInfo>(Triple) {
5463     SizeType = UnsignedInt;
5464     PtrDiffType = SignedInt;
5465   }
5466 };
5467 } // end anonymous namespace.
5468 
5469 namespace {
5470 class SystemZTargetInfo : public TargetInfo {
5471   static const char *const GCCRegNames[];
5472 
5473 public:
5474   SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5475     TLSSupported = true;
5476     IntWidth = IntAlign = 32;
5477     LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
5478     PointerWidth = PointerAlign = 64;
5479     LongDoubleWidth = 128;
5480     LongDoubleAlign = 64;
5481     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5482     MinGlobalAlign = 16;
5483     DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
5484     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5485   }
5486   void getTargetDefines(const LangOptions &Opts,
5487                         MacroBuilder &Builder) const override {
5488     Builder.defineMacro("__s390__");
5489     Builder.defineMacro("__s390x__");
5490     Builder.defineMacro("__zarch__");
5491     Builder.defineMacro("__LONG_DOUBLE_128__");
5492   }
5493   void getTargetBuiltins(const Builtin::Info *&Records,
5494                          unsigned &NumRecords) const override {
5495     // FIXME: Implement.
5496     Records = nullptr;
5497     NumRecords = 0;
5498   }
5499 
5500   void getGCCRegNames(const char *const *&Names,
5501                       unsigned &NumNames) const override;
5502   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5503                         unsigned &NumAliases) const override {
5504     // No aliases.
5505     Aliases = nullptr;
5506     NumAliases = 0;
5507   }
5508   bool validateAsmConstraint(const char *&Name,
5509                              TargetInfo::ConstraintInfo &info) const override;
5510   const char *getClobbers() const override {
5511     // FIXME: Is this really right?
5512     return "";
5513   }
5514   BuiltinVaListKind getBuiltinVaListKind() const override {
5515     return TargetInfo::SystemZBuiltinVaList;
5516   }
5517   bool setCPU(const std::string &Name) override {
5518     bool CPUKnown = llvm::StringSwitch<bool>(Name)
5519       .Case("z10", true)
5520       .Case("z196", true)
5521       .Case("zEC12", true)
5522       .Default(false);
5523 
5524     // No need to store the CPU yet.  There aren't any CPU-specific
5525     // macros to define.
5526     return CPUKnown;
5527   }
5528 };
5529 
5530 const char *const SystemZTargetInfo::GCCRegNames[] = {
5531   "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
5532   "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
5533   "f0",  "f2",  "f4",  "f6",  "f1",  "f3",  "f5",  "f7",
5534   "f8",  "f10", "f12", "f14", "f9",  "f11", "f13", "f15"
5535 };
5536 
5537 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
5538                                        unsigned &NumNames) const {
5539   Names = GCCRegNames;
5540   NumNames = llvm::array_lengthof(GCCRegNames);
5541 }
5542 
5543 bool SystemZTargetInfo::
5544 validateAsmConstraint(const char *&Name,
5545                       TargetInfo::ConstraintInfo &Info) const {
5546   switch (*Name) {
5547   default:
5548     return false;
5549 
5550   case 'a': // Address register
5551   case 'd': // Data register (equivalent to 'r')
5552   case 'f': // Floating-point register
5553     Info.setAllowsRegister();
5554     return true;
5555 
5556   case 'I': // Unsigned 8-bit constant
5557   case 'J': // Unsigned 12-bit constant
5558   case 'K': // Signed 16-bit constant
5559   case 'L': // Signed 20-bit displacement (on all targets we support)
5560   case 'M': // 0x7fffffff
5561     return true;
5562 
5563   case 'Q': // Memory with base and unsigned 12-bit displacement
5564   case 'R': // Likewise, plus an index
5565   case 'S': // Memory with base and signed 20-bit displacement
5566   case 'T': // Likewise, plus an index
5567     Info.setAllowsMemory();
5568     return true;
5569   }
5570 }
5571 }
5572 
5573 namespace {
5574   class MSP430TargetInfo : public TargetInfo {
5575     static const char * const GCCRegNames[];
5576   public:
5577     MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5578       BigEndian = false;
5579       TLSSupported = false;
5580       IntWidth = 16; IntAlign = 16;
5581       LongWidth = 32; LongLongWidth = 64;
5582       LongAlign = LongLongAlign = 16;
5583       PointerWidth = 16; PointerAlign = 16;
5584       SuitableAlign = 16;
5585       SizeType = UnsignedInt;
5586       IntMaxType = SignedLongLong;
5587       IntPtrType = SignedInt;
5588       PtrDiffType = SignedInt;
5589       SigAtomicType = SignedLong;
5590       DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16";
5591     }
5592     void getTargetDefines(const LangOptions &Opts,
5593                           MacroBuilder &Builder) const override {
5594       Builder.defineMacro("MSP430");
5595       Builder.defineMacro("__MSP430__");
5596       // FIXME: defines for different 'flavours' of MCU
5597     }
5598     void getTargetBuiltins(const Builtin::Info *&Records,
5599                            unsigned &NumRecords) const override {
5600       // FIXME: Implement.
5601       Records = nullptr;
5602       NumRecords = 0;
5603     }
5604     bool hasFeature(StringRef Feature) const override {
5605       return Feature == "msp430";
5606     }
5607     void getGCCRegNames(const char * const *&Names,
5608                         unsigned &NumNames) const override;
5609     void getGCCRegAliases(const GCCRegAlias *&Aliases,
5610                           unsigned &NumAliases) const override {
5611       // No aliases.
5612       Aliases = nullptr;
5613       NumAliases = 0;
5614     }
5615     bool
5616     validateAsmConstraint(const char *&Name,
5617                           TargetInfo::ConstraintInfo &info) const override {
5618       // FIXME: implement
5619       switch (*Name) {
5620       case 'K': // the constant 1
5621       case 'L': // constant -1^20 .. 1^19
5622       case 'M': // constant 1-4:
5623         return true;
5624       }
5625       // No target constraints for now.
5626       return false;
5627     }
5628     const char *getClobbers() const override {
5629       // FIXME: Is this really right?
5630       return "";
5631     }
5632     BuiltinVaListKind getBuiltinVaListKind() const override {
5633       // FIXME: implement
5634       return TargetInfo::CharPtrBuiltinVaList;
5635    }
5636   };
5637 
5638   const char * const MSP430TargetInfo::GCCRegNames[] = {
5639     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5640     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5641   };
5642 
5643   void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
5644                                         unsigned &NumNames) const {
5645     Names = GCCRegNames;
5646     NumNames = llvm::array_lengthof(GCCRegNames);
5647   }
5648 }
5649 
5650 namespace {
5651 
5652   // LLVM and Clang cannot be used directly to output native binaries for
5653   // target, but is used to compile C code to llvm bitcode with correct
5654   // type and alignment information.
5655   //
5656   // TCE uses the llvm bitcode as input and uses it for generating customized
5657   // target processor and program binary. TCE co-design environment is
5658   // publicly available in http://tce.cs.tut.fi
5659 
5660   static const unsigned TCEOpenCLAddrSpaceMap[] = {
5661       3, // opencl_global
5662       4, // opencl_local
5663       5, // opencl_constant
5664       // FIXME: generic has to be added to the target
5665       0, // opencl_generic
5666       0, // cuda_device
5667       0, // cuda_constant
5668       0  // cuda_shared
5669   };
5670 
5671   class TCETargetInfo : public TargetInfo{
5672   public:
5673     TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5674       TLSSupported = false;
5675       IntWidth = 32;
5676       LongWidth = LongLongWidth = 32;
5677       PointerWidth = 32;
5678       IntAlign = 32;
5679       LongAlign = LongLongAlign = 32;
5680       PointerAlign = 32;
5681       SuitableAlign = 32;
5682       SizeType = UnsignedInt;
5683       IntMaxType = SignedLong;
5684       IntPtrType = SignedInt;
5685       PtrDiffType = SignedInt;
5686       FloatWidth = 32;
5687       FloatAlign = 32;
5688       DoubleWidth = 32;
5689       DoubleAlign = 32;
5690       LongDoubleWidth = 32;
5691       LongDoubleAlign = 32;
5692       FloatFormat = &llvm::APFloat::IEEEsingle;
5693       DoubleFormat = &llvm::APFloat::IEEEsingle;
5694       LongDoubleFormat = &llvm::APFloat::IEEEsingle;
5695       DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32"
5696                           "-f64:32-v64:32-v128:32-a:0:32-n32";
5697       AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
5698       UseAddrSpaceMapMangling = true;
5699     }
5700 
5701     void getTargetDefines(const LangOptions &Opts,
5702                           MacroBuilder &Builder) const override {
5703       DefineStd(Builder, "tce", Opts);
5704       Builder.defineMacro("__TCE__");
5705       Builder.defineMacro("__TCE_V1__");
5706     }
5707     bool hasFeature(StringRef Feature) const override {
5708       return Feature == "tce";
5709     }
5710 
5711     void getTargetBuiltins(const Builtin::Info *&Records,
5712                            unsigned &NumRecords) const override {}
5713     const char *getClobbers() const override {
5714       return "";
5715     }
5716     BuiltinVaListKind getBuiltinVaListKind() const override {
5717       return TargetInfo::VoidPtrBuiltinVaList;
5718     }
5719     void getGCCRegNames(const char * const *&Names,
5720                         unsigned &NumNames) const override {}
5721     bool validateAsmConstraint(const char *&Name,
5722                                TargetInfo::ConstraintInfo &info) const override{
5723       return true;
5724     }
5725     void getGCCRegAliases(const GCCRegAlias *&Aliases,
5726                           unsigned &NumAliases) const override {}
5727   };
5728 }
5729 
5730 namespace {
5731 class MipsTargetInfoBase : public TargetInfo {
5732   virtual void setDescriptionString() = 0;
5733 
5734   static const Builtin::Info BuiltinInfo[];
5735   std::string CPU;
5736   bool IsMips16;
5737   bool IsMicromips;
5738   bool IsNan2008;
5739   bool IsSingleFloat;
5740   enum MipsFloatABI {
5741     HardFloat, SoftFloat
5742   } FloatABI;
5743   enum DspRevEnum {
5744     NoDSP, DSP1, DSP2
5745   } DspRev;
5746   bool HasMSA;
5747 
5748 protected:
5749   bool HasFP64;
5750   std::string ABI;
5751 
5752 public:
5753   MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
5754                      const std::string &CPUStr)
5755       : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
5756         IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
5757         DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {
5758     TheCXXABI.set(TargetCXXABI::GenericMIPS);
5759   }
5760 
5761   bool isNaN2008Default() const {
5762     return CPU == "mips32r6" || CPU == "mips64r6";
5763   }
5764 
5765   bool isFP64Default() const {
5766     return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
5767   }
5768 
5769   bool isNan2008() const override {
5770     return IsNan2008;
5771   }
5772 
5773   StringRef getABI() const override { return ABI; }
5774   bool setCPU(const std::string &Name) override {
5775     bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
5776                     getTriple().getArch() == llvm::Triple::mipsel;
5777     CPU = Name;
5778     return llvm::StringSwitch<bool>(Name)
5779         .Case("mips1", IsMips32)
5780         .Case("mips2", IsMips32)
5781         .Case("mips3", true)
5782         .Case("mips4", true)
5783         .Case("mips5", true)
5784         .Case("mips32", IsMips32)
5785         .Case("mips32r2", IsMips32)
5786         .Case("mips32r3", IsMips32)
5787         .Case("mips32r5", IsMips32)
5788         .Case("mips32r6", IsMips32)
5789         .Case("mips64", true)
5790         .Case("mips64r2", true)
5791         .Case("mips64r3", true)
5792         .Case("mips64r5", true)
5793         .Case("mips64r6", true)
5794         .Case("octeon", true)
5795         .Default(false);
5796   }
5797   const std::string& getCPU() const { return CPU; }
5798   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
5799     if (CPU == "octeon")
5800       Features["mips64r2"] = Features["cnmips"] = true;
5801     else
5802       Features[CPU] = true;
5803   }
5804 
5805   void getTargetDefines(const LangOptions &Opts,
5806                         MacroBuilder &Builder) const override {
5807     Builder.defineMacro("__mips__");
5808     Builder.defineMacro("_mips");
5809     if (Opts.GNUMode)
5810       Builder.defineMacro("mips");
5811 
5812     Builder.defineMacro("__REGISTER_PREFIX__", "");
5813 
5814     switch (FloatABI) {
5815     case HardFloat:
5816       Builder.defineMacro("__mips_hard_float", Twine(1));
5817       break;
5818     case SoftFloat:
5819       Builder.defineMacro("__mips_soft_float", Twine(1));
5820       break;
5821     }
5822 
5823     if (IsSingleFloat)
5824       Builder.defineMacro("__mips_single_float", Twine(1));
5825 
5826     Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
5827     Builder.defineMacro("_MIPS_FPSET",
5828                         Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
5829 
5830     if (IsMips16)
5831       Builder.defineMacro("__mips16", Twine(1));
5832 
5833     if (IsMicromips)
5834       Builder.defineMacro("__mips_micromips", Twine(1));
5835 
5836     if (IsNan2008)
5837       Builder.defineMacro("__mips_nan2008", Twine(1));
5838 
5839     switch (DspRev) {
5840     default:
5841       break;
5842     case DSP1:
5843       Builder.defineMacro("__mips_dsp_rev", Twine(1));
5844       Builder.defineMacro("__mips_dsp", Twine(1));
5845       break;
5846     case DSP2:
5847       Builder.defineMacro("__mips_dsp_rev", Twine(2));
5848       Builder.defineMacro("__mips_dspr2", Twine(1));
5849       Builder.defineMacro("__mips_dsp", Twine(1));
5850       break;
5851     }
5852 
5853     if (HasMSA)
5854       Builder.defineMacro("__mips_msa", Twine(1));
5855 
5856     Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
5857     Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
5858     Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
5859 
5860     Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
5861     Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
5862   }
5863 
5864   void getTargetBuiltins(const Builtin::Info *&Records,
5865                          unsigned &NumRecords) const override {
5866     Records = BuiltinInfo;
5867     NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
5868   }
5869   bool hasFeature(StringRef Feature) const override {
5870     return llvm::StringSwitch<bool>(Feature)
5871       .Case("mips", true)
5872       .Case("fp64", HasFP64)
5873       .Default(false);
5874   }
5875   BuiltinVaListKind getBuiltinVaListKind() const override {
5876     return TargetInfo::VoidPtrBuiltinVaList;
5877   }
5878   void getGCCRegNames(const char * const *&Names,
5879                       unsigned &NumNames) const override {
5880     static const char *const GCCRegNames[] = {
5881       // CPU register names
5882       // Must match second column of GCCRegAliases
5883       "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
5884       "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
5885       "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
5886       "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
5887       // Floating point register names
5888       "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
5889       "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
5890       "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
5891       "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
5892       // Hi/lo and condition register names
5893       "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
5894       "$fcc5","$fcc6","$fcc7",
5895       // MSA register names
5896       "$w0",  "$w1",  "$w2",  "$w3",  "$w4",  "$w5",  "$w6",  "$w7",
5897       "$w8",  "$w9",  "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
5898       "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
5899       "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
5900       // MSA control register names
5901       "$msair",      "$msacsr", "$msaaccess", "$msasave", "$msamodify",
5902       "$msarequest", "$msamap", "$msaunmap"
5903     };
5904     Names = GCCRegNames;
5905     NumNames = llvm::array_lengthof(GCCRegNames);
5906   }
5907   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5908                         unsigned &NumAliases) const override = 0;
5909   bool validateAsmConstraint(const char *&Name,
5910                              TargetInfo::ConstraintInfo &Info) const override {
5911     switch (*Name) {
5912     default:
5913       return false;
5914     case 'r': // CPU registers.
5915     case 'd': // Equivalent to "r" unless generating MIPS16 code.
5916     case 'y': // Equivalent to "r", backward compatibility only.
5917     case 'f': // floating-point registers.
5918     case 'c': // $25 for indirect jumps
5919     case 'l': // lo register
5920     case 'x': // hilo register pair
5921       Info.setAllowsRegister();
5922       return true;
5923     case 'I': // Signed 16-bit constant
5924     case 'J': // Integer 0
5925     case 'K': // Unsigned 16-bit constant
5926     case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
5927     case 'M': // Constants not loadable via lui, addiu, or ori
5928     case 'N': // Constant -1 to -65535
5929     case 'O': // A signed 15-bit constant
5930     case 'P': // A constant between 1 go 65535
5931       return true;
5932     case 'R': // An address that can be used in a non-macro load or store
5933       Info.setAllowsMemory();
5934       return true;
5935     }
5936   }
5937 
5938   const char *getClobbers() const override {
5939     // In GCC, $1 is not widely used in generated code (it's used only in a few
5940     // specific situations), so there is no real need for users to add it to
5941     // the clobbers list if they want to use it in their inline assembly code.
5942     //
5943     // In LLVM, $1 is treated as a normal GPR and is always allocatable during
5944     // code generation, so using it in inline assembly without adding it to the
5945     // clobbers list can cause conflicts between the inline assembly code and
5946     // the surrounding generated code.
5947     //
5948     // Another problem is that LLVM is allowed to choose $1 for inline assembly
5949     // operands, which will conflict with the ".set at" assembler option (which
5950     // we use only for inline assembly, in order to maintain compatibility with
5951     // GCC) and will also conflict with the user's usage of $1.
5952     //
5953     // The easiest way to avoid these conflicts and keep $1 as an allocatable
5954     // register for generated code is to automatically clobber $1 for all inline
5955     // assembly code.
5956     //
5957     // FIXME: We should automatically clobber $1 only for inline assembly code
5958     // which actually uses it. This would allow LLVM to use $1 for inline
5959     // assembly operands if the user's assembly code doesn't use it.
5960     return "~{$1}";
5961   }
5962 
5963   bool handleTargetFeatures(std::vector<std::string> &Features,
5964                             DiagnosticsEngine &Diags) override {
5965     IsMips16 = false;
5966     IsMicromips = false;
5967     IsNan2008 = isNaN2008Default();
5968     IsSingleFloat = false;
5969     FloatABI = HardFloat;
5970     DspRev = NoDSP;
5971     HasFP64 = isFP64Default();
5972 
5973     for (std::vector<std::string>::iterator it = Features.begin(),
5974          ie = Features.end(); it != ie; ++it) {
5975       if (*it == "+single-float")
5976         IsSingleFloat = true;
5977       else if (*it == "+soft-float")
5978         FloatABI = SoftFloat;
5979       else if (*it == "+mips16")
5980         IsMips16 = true;
5981       else if (*it == "+micromips")
5982         IsMicromips = true;
5983       else if (*it == "+dsp")
5984         DspRev = std::max(DspRev, DSP1);
5985       else if (*it == "+dspr2")
5986         DspRev = std::max(DspRev, DSP2);
5987       else if (*it == "+msa")
5988         HasMSA = true;
5989       else if (*it == "+fp64")
5990         HasFP64 = true;
5991       else if (*it == "-fp64")
5992         HasFP64 = false;
5993       else if (*it == "+nan2008")
5994         IsNan2008 = true;
5995       else if (*it == "-nan2008")
5996         IsNan2008 = false;
5997     }
5998 
5999     // Remove front-end specific options.
6000     std::vector<std::string>::iterator it =
6001       std::find(Features.begin(), Features.end(), "+soft-float");
6002     if (it != Features.end())
6003       Features.erase(it);
6004 
6005     setDescriptionString();
6006 
6007     return true;
6008   }
6009 
6010   int getEHDataRegisterNumber(unsigned RegNo) const override {
6011     if (RegNo == 0) return 4;
6012     if (RegNo == 1) return 5;
6013     return -1;
6014   }
6015 
6016   bool isCLZForZeroUndef() const override { return false; }
6017 };
6018 
6019 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
6020 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6021 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6022                                               ALL_LANGUAGES },
6023 #include "clang/Basic/BuiltinsMips.def"
6024 };
6025 
6026 class Mips32TargetInfoBase : public MipsTargetInfoBase {
6027 public:
6028   Mips32TargetInfoBase(const llvm::Triple &Triple)
6029       : MipsTargetInfoBase(Triple, "o32", "mips32r2") {
6030     SizeType = UnsignedInt;
6031     PtrDiffType = SignedInt;
6032     Int64Type = SignedLongLong;
6033     IntMaxType = Int64Type;
6034     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
6035   }
6036   bool setABI(const std::string &Name) override {
6037     if (Name == "o32" || Name == "eabi") {
6038       ABI = Name;
6039       return true;
6040     }
6041     return false;
6042   }
6043   void getTargetDefines(const LangOptions &Opts,
6044                         MacroBuilder &Builder) const override {
6045     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6046 
6047     Builder.defineMacro("__mips", "32");
6048     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
6049 
6050     const std::string& CPUStr = getCPU();
6051     if (CPUStr == "mips32")
6052       Builder.defineMacro("__mips_isa_rev", "1");
6053     else if (CPUStr == "mips32r2")
6054       Builder.defineMacro("__mips_isa_rev", "2");
6055     else if (CPUStr == "mips32r3")
6056       Builder.defineMacro("__mips_isa_rev", "3");
6057     else if (CPUStr == "mips32r5")
6058       Builder.defineMacro("__mips_isa_rev", "5");
6059     else if (CPUStr == "mips32r6")
6060       Builder.defineMacro("__mips_isa_rev", "6");
6061 
6062     if (ABI == "o32") {
6063       Builder.defineMacro("__mips_o32");
6064       Builder.defineMacro("_ABIO32", "1");
6065       Builder.defineMacro("_MIPS_SIM", "_ABIO32");
6066     }
6067     else if (ABI == "eabi")
6068       Builder.defineMacro("__mips_eabi");
6069     else
6070       llvm_unreachable("Invalid ABI for Mips32.");
6071   }
6072   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6073                         unsigned &NumAliases) const override {
6074     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6075       { { "at" },  "$1" },
6076       { { "v0" },  "$2" },
6077       { { "v1" },  "$3" },
6078       { { "a0" },  "$4" },
6079       { { "a1" },  "$5" },
6080       { { "a2" },  "$6" },
6081       { { "a3" },  "$7" },
6082       { { "t0" },  "$8" },
6083       { { "t1" },  "$9" },
6084       { { "t2" }, "$10" },
6085       { { "t3" }, "$11" },
6086       { { "t4" }, "$12" },
6087       { { "t5" }, "$13" },
6088       { { "t6" }, "$14" },
6089       { { "t7" }, "$15" },
6090       { { "s0" }, "$16" },
6091       { { "s1" }, "$17" },
6092       { { "s2" }, "$18" },
6093       { { "s3" }, "$19" },
6094       { { "s4" }, "$20" },
6095       { { "s5" }, "$21" },
6096       { { "s6" }, "$22" },
6097       { { "s7" }, "$23" },
6098       { { "t8" }, "$24" },
6099       { { "t9" }, "$25" },
6100       { { "k0" }, "$26" },
6101       { { "k1" }, "$27" },
6102       { { "gp" }, "$28" },
6103       { { "sp","$sp" }, "$29" },
6104       { { "fp","$fp" }, "$30" },
6105       { { "ra" }, "$31" }
6106     };
6107     Aliases = GCCRegAliases;
6108     NumAliases = llvm::array_lengthof(GCCRegAliases);
6109   }
6110 };
6111 
6112 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
6113   void setDescriptionString() override {
6114     DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6115   }
6116 
6117 public:
6118   Mips32EBTargetInfo(const llvm::Triple &Triple)
6119       : Mips32TargetInfoBase(Triple) {
6120   }
6121   void getTargetDefines(const LangOptions &Opts,
6122                         MacroBuilder &Builder) const override {
6123     DefineStd(Builder, "MIPSEB", Opts);
6124     Builder.defineMacro("_MIPSEB");
6125     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6126   }
6127 };
6128 
6129 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
6130   void setDescriptionString() override {
6131     DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6132   }
6133 
6134 public:
6135   Mips32ELTargetInfo(const llvm::Triple &Triple)
6136       : Mips32TargetInfoBase(Triple) {
6137     BigEndian = false;
6138   }
6139   void getTargetDefines(const LangOptions &Opts,
6140                         MacroBuilder &Builder) const override {
6141     DefineStd(Builder, "MIPSEL", Opts);
6142     Builder.defineMacro("_MIPSEL");
6143     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6144   }
6145 };
6146 
6147 class Mips64TargetInfoBase : public MipsTargetInfoBase {
6148 public:
6149   Mips64TargetInfoBase(const llvm::Triple &Triple)
6150       : MipsTargetInfoBase(Triple, "n64", "mips64r2") {
6151     LongDoubleWidth = LongDoubleAlign = 128;
6152     LongDoubleFormat = &llvm::APFloat::IEEEquad;
6153     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
6154       LongDoubleWidth = LongDoubleAlign = 64;
6155       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
6156     }
6157     setN64ABITypes();
6158     SuitableAlign = 128;
6159     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6160   }
6161 
6162   void setN64ABITypes() {
6163     LongWidth = LongAlign = 64;
6164     PointerWidth = PointerAlign = 64;
6165     SizeType = UnsignedLong;
6166     PtrDiffType = SignedLong;
6167     Int64Type = SignedLong;
6168     IntMaxType = Int64Type;
6169   }
6170 
6171   void setN32ABITypes() {
6172     LongWidth = LongAlign = 32;
6173     PointerWidth = PointerAlign = 32;
6174     SizeType = UnsignedInt;
6175     PtrDiffType = SignedInt;
6176     Int64Type = SignedLongLong;
6177     IntMaxType = Int64Type;
6178   }
6179 
6180   bool setABI(const std::string &Name) override {
6181     if (Name == "n32") {
6182       setN32ABITypes();
6183       ABI = Name;
6184       return true;
6185     }
6186     if (Name == "n64") {
6187       setN64ABITypes();
6188       ABI = Name;
6189       return true;
6190     }
6191     return false;
6192   }
6193 
6194   void getTargetDefines(const LangOptions &Opts,
6195                         MacroBuilder &Builder) const override {
6196     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6197 
6198     Builder.defineMacro("__mips", "64");
6199     Builder.defineMacro("__mips64");
6200     Builder.defineMacro("__mips64__");
6201     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
6202 
6203     const std::string& CPUStr = getCPU();
6204     if (CPUStr == "mips64")
6205       Builder.defineMacro("__mips_isa_rev", "1");
6206     else if (CPUStr == "mips64r2")
6207       Builder.defineMacro("__mips_isa_rev", "2");
6208     else if (CPUStr == "mips64r3")
6209       Builder.defineMacro("__mips_isa_rev", "3");
6210     else if (CPUStr == "mips64r5")
6211       Builder.defineMacro("__mips_isa_rev", "5");
6212     else if (CPUStr == "mips64r6")
6213       Builder.defineMacro("__mips_isa_rev", "6");
6214 
6215     if (ABI == "n32") {
6216       Builder.defineMacro("__mips_n32");
6217       Builder.defineMacro("_ABIN32", "2");
6218       Builder.defineMacro("_MIPS_SIM", "_ABIN32");
6219     }
6220     else if (ABI == "n64") {
6221       Builder.defineMacro("__mips_n64");
6222       Builder.defineMacro("_ABI64", "3");
6223       Builder.defineMacro("_MIPS_SIM", "_ABI64");
6224     }
6225     else
6226       llvm_unreachable("Invalid ABI for Mips64.");
6227   }
6228   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6229                         unsigned &NumAliases) const override {
6230     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6231       { { "at" },  "$1" },
6232       { { "v0" },  "$2" },
6233       { { "v1" },  "$3" },
6234       { { "a0" },  "$4" },
6235       { { "a1" },  "$5" },
6236       { { "a2" },  "$6" },
6237       { { "a3" },  "$7" },
6238       { { "a4" },  "$8" },
6239       { { "a5" },  "$9" },
6240       { { "a6" }, "$10" },
6241       { { "a7" }, "$11" },
6242       { { "t0" }, "$12" },
6243       { { "t1" }, "$13" },
6244       { { "t2" }, "$14" },
6245       { { "t3" }, "$15" },
6246       { { "s0" }, "$16" },
6247       { { "s1" }, "$17" },
6248       { { "s2" }, "$18" },
6249       { { "s3" }, "$19" },
6250       { { "s4" }, "$20" },
6251       { { "s5" }, "$21" },
6252       { { "s6" }, "$22" },
6253       { { "s7" }, "$23" },
6254       { { "t8" }, "$24" },
6255       { { "t9" }, "$25" },
6256       { { "k0" }, "$26" },
6257       { { "k1" }, "$27" },
6258       { { "gp" }, "$28" },
6259       { { "sp","$sp" }, "$29" },
6260       { { "fp","$fp" }, "$30" },
6261       { { "ra" }, "$31" }
6262     };
6263     Aliases = GCCRegAliases;
6264     NumAliases = llvm::array_lengthof(GCCRegAliases);
6265   }
6266 
6267   bool hasInt128Type() const override { return true; }
6268 };
6269 
6270 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
6271   void setDescriptionString() override {
6272     if (ABI == "n32")
6273       DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6274     else
6275       DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6276 
6277   }
6278 
6279 public:
6280   Mips64EBTargetInfo(const llvm::Triple &Triple)
6281       : Mips64TargetInfoBase(Triple) {}
6282   void getTargetDefines(const LangOptions &Opts,
6283                         MacroBuilder &Builder) const override {
6284     DefineStd(Builder, "MIPSEB", Opts);
6285     Builder.defineMacro("_MIPSEB");
6286     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6287   }
6288 };
6289 
6290 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
6291   void setDescriptionString() override {
6292     if (ABI == "n32")
6293       DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6294     else
6295       DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6296   }
6297 public:
6298   Mips64ELTargetInfo(const llvm::Triple &Triple)
6299       : Mips64TargetInfoBase(Triple) {
6300     // Default ABI is n64.
6301     BigEndian = false;
6302   }
6303   void getTargetDefines(const LangOptions &Opts,
6304                         MacroBuilder &Builder) const override {
6305     DefineStd(Builder, "MIPSEL", Opts);
6306     Builder.defineMacro("_MIPSEL");
6307     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6308   }
6309 };
6310 } // end anonymous namespace.
6311 
6312 namespace {
6313 class PNaClTargetInfo : public TargetInfo {
6314 public:
6315   PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6316     BigEndian = false;
6317     this->UserLabelPrefix = "";
6318     this->LongAlign = 32;
6319     this->LongWidth = 32;
6320     this->PointerAlign = 32;
6321     this->PointerWidth = 32;
6322     this->IntMaxType = TargetInfo::SignedLongLong;
6323     this->Int64Type = TargetInfo::SignedLongLong;
6324     this->DoubleAlign = 64;
6325     this->LongDoubleWidth = 64;
6326     this->LongDoubleAlign = 64;
6327     this->SizeType = TargetInfo::UnsignedInt;
6328     this->PtrDiffType = TargetInfo::SignedInt;
6329     this->IntPtrType = TargetInfo::SignedInt;
6330     this->RegParmMax = 0; // Disallow regparm
6331   }
6332 
6333   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
6334   }
6335   void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
6336     Builder.defineMacro("__le32__");
6337     Builder.defineMacro("__pnacl__");
6338   }
6339   void getTargetDefines(const LangOptions &Opts,
6340                         MacroBuilder &Builder) const override {
6341     getArchDefines(Opts, Builder);
6342   }
6343   bool hasFeature(StringRef Feature) const override {
6344     return Feature == "pnacl";
6345   }
6346   void getTargetBuiltins(const Builtin::Info *&Records,
6347                          unsigned &NumRecords) const override {
6348   }
6349   BuiltinVaListKind getBuiltinVaListKind() const override {
6350     return TargetInfo::PNaClABIBuiltinVaList;
6351   }
6352   void getGCCRegNames(const char * const *&Names,
6353                       unsigned &NumNames) const override;
6354   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6355                         unsigned &NumAliases) const override;
6356   bool validateAsmConstraint(const char *&Name,
6357                              TargetInfo::ConstraintInfo &Info) const override {
6358     return false;
6359   }
6360 
6361   const char *getClobbers() const override {
6362     return "";
6363   }
6364 };
6365 
6366 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
6367                                      unsigned &NumNames) const {
6368   Names = nullptr;
6369   NumNames = 0;
6370 }
6371 
6372 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
6373                                        unsigned &NumAliases) const {
6374   Aliases = nullptr;
6375   NumAliases = 0;
6376 }
6377 } // end anonymous namespace.
6378 
6379 namespace {
6380 class Le64TargetInfo : public TargetInfo {
6381   static const Builtin::Info BuiltinInfo[];
6382 
6383 public:
6384   Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6385     BigEndian = false;
6386     NoAsmVariants = true;
6387     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6388     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6389     DescriptionString =
6390         "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128";
6391   }
6392 
6393   void getTargetDefines(const LangOptions &Opts,
6394                         MacroBuilder &Builder) const override {
6395     DefineStd(Builder, "unix", Opts);
6396     defineCPUMacros(Builder, "le64", /*Tuning=*/false);
6397     Builder.defineMacro("__ELF__");
6398   }
6399   void getTargetBuiltins(const Builtin::Info *&Records,
6400                          unsigned &NumRecords) const override {
6401     Records = BuiltinInfo;
6402     NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin;
6403   }
6404   BuiltinVaListKind getBuiltinVaListKind() const override {
6405     return TargetInfo::PNaClABIBuiltinVaList;
6406   }
6407   const char *getClobbers() const override { return ""; }
6408   void getGCCRegNames(const char *const *&Names,
6409                       unsigned &NumNames) const override {
6410     Names = nullptr;
6411     NumNames = 0;
6412   }
6413   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6414                         unsigned &NumAliases) const override {
6415     Aliases = nullptr;
6416     NumAliases = 0;
6417   }
6418   bool validateAsmConstraint(const char *&Name,
6419                              TargetInfo::ConstraintInfo &Info) const override {
6420     return false;
6421   }
6422 
6423   bool hasProtectedVisibility() const override { return false; }
6424 };
6425 } // end anonymous namespace.
6426 
6427 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
6428 #define BUILTIN(ID, TYPE, ATTRS)                                               \
6429   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6430 #include "clang/Basic/BuiltinsLe64.def"
6431 };
6432 
6433 namespace {
6434   static const unsigned SPIRAddrSpaceMap[] = {
6435     1,    // opencl_global
6436     3,    // opencl_local
6437     2,    // opencl_constant
6438     4,    // opencl_generic
6439     0,    // cuda_device
6440     0,    // cuda_constant
6441     0     // cuda_shared
6442   };
6443   class SPIRTargetInfo : public TargetInfo {
6444   public:
6445     SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6446       assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
6447         "SPIR target must use unknown OS");
6448       assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
6449         "SPIR target must use unknown environment type");
6450       BigEndian = false;
6451       TLSSupported = false;
6452       LongWidth = LongAlign = 64;
6453       AddrSpaceMap = &SPIRAddrSpaceMap;
6454       UseAddrSpaceMapMangling = true;
6455       // Define available target features
6456       // These must be defined in sorted order!
6457       NoAsmVariants = true;
6458     }
6459     void getTargetDefines(const LangOptions &Opts,
6460                           MacroBuilder &Builder) const override {
6461       DefineStd(Builder, "SPIR", Opts);
6462     }
6463     bool hasFeature(StringRef Feature) const override {
6464       return Feature == "spir";
6465     }
6466 
6467     void getTargetBuiltins(const Builtin::Info *&Records,
6468                            unsigned &NumRecords) const override {}
6469     const char *getClobbers() const override {
6470       return "";
6471     }
6472     void getGCCRegNames(const char * const *&Names,
6473                         unsigned &NumNames) const override {}
6474     bool
6475     validateAsmConstraint(const char *&Name,
6476                           TargetInfo::ConstraintInfo &info) const override {
6477       return true;
6478     }
6479     void getGCCRegAliases(const GCCRegAlias *&Aliases,
6480                           unsigned &NumAliases) const override {}
6481     BuiltinVaListKind getBuiltinVaListKind() const override {
6482       return TargetInfo::VoidPtrBuiltinVaList;
6483     }
6484 
6485     CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
6486       return (CC == CC_SpirFunction ||
6487               CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning;
6488     }
6489 
6490     CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
6491       return CC_SpirFunction;
6492     }
6493   };
6494 
6495 
6496   class SPIR32TargetInfo : public SPIRTargetInfo {
6497   public:
6498     SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6499       PointerWidth = PointerAlign = 32;
6500       SizeType     = TargetInfo::UnsignedInt;
6501       PtrDiffType = IntPtrType = TargetInfo::SignedInt;
6502       DescriptionString
6503         = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
6504           "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6505     }
6506     void getTargetDefines(const LangOptions &Opts,
6507                           MacroBuilder &Builder) const override {
6508       DefineStd(Builder, "SPIR32", Opts);
6509     }
6510   };
6511 
6512   class SPIR64TargetInfo : public SPIRTargetInfo {
6513   public:
6514     SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6515       PointerWidth = PointerAlign = 64;
6516       SizeType     = TargetInfo::UnsignedLong;
6517       PtrDiffType = IntPtrType = TargetInfo::SignedLong;
6518       DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
6519                           "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6520     }
6521     void getTargetDefines(const LangOptions &Opts,
6522                           MacroBuilder &Builder) const override {
6523       DefineStd(Builder, "SPIR64", Opts);
6524     }
6525   };
6526 }
6527 
6528 namespace {
6529 class XCoreTargetInfo : public TargetInfo {
6530   static const Builtin::Info BuiltinInfo[];
6531 public:
6532   XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6533     BigEndian = false;
6534     NoAsmVariants = true;
6535     LongLongAlign = 32;
6536     SuitableAlign = 32;
6537     DoubleAlign = LongDoubleAlign = 32;
6538     SizeType = UnsignedInt;
6539     PtrDiffType = SignedInt;
6540     IntPtrType = SignedInt;
6541     WCharType = UnsignedChar;
6542     WIntType = UnsignedInt;
6543     UseZeroLengthBitfieldAlignment = true;
6544     DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
6545                         "-f64:32-a:0:32-n32";
6546   }
6547   void getTargetDefines(const LangOptions &Opts,
6548                         MacroBuilder &Builder) const override {
6549     Builder.defineMacro("__XS1B__");
6550   }
6551   void getTargetBuiltins(const Builtin::Info *&Records,
6552                          unsigned &NumRecords) const override {
6553     Records = BuiltinInfo;
6554     NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin;
6555   }
6556   BuiltinVaListKind getBuiltinVaListKind() const override {
6557     return TargetInfo::VoidPtrBuiltinVaList;
6558   }
6559   const char *getClobbers() const override {
6560     return "";
6561   }
6562   void getGCCRegNames(const char * const *&Names,
6563                       unsigned &NumNames) const override {
6564     static const char * const GCCRegNames[] = {
6565       "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
6566       "r8",   "r9",   "r10",  "r11",  "cp",   "dp",   "sp",   "lr"
6567     };
6568     Names = GCCRegNames;
6569     NumNames = llvm::array_lengthof(GCCRegNames);
6570   }
6571   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6572                         unsigned &NumAliases) const override {
6573     Aliases = nullptr;
6574     NumAliases = 0;
6575   }
6576   bool validateAsmConstraint(const char *&Name,
6577                              TargetInfo::ConstraintInfo &Info) const override {
6578     return false;
6579   }
6580   int getEHDataRegisterNumber(unsigned RegNo) const override {
6581     // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
6582     return (RegNo < 2)? RegNo : -1;
6583   }
6584 };
6585 
6586 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
6587 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6588 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6589                                               ALL_LANGUAGES },
6590 #include "clang/Basic/BuiltinsXCore.def"
6591 };
6592 } // end anonymous namespace.
6593 
6594 
6595 //===----------------------------------------------------------------------===//
6596 // Driver code
6597 //===----------------------------------------------------------------------===//
6598 
6599 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
6600   llvm::Triple::OSType os = Triple.getOS();
6601 
6602   switch (Triple.getArch()) {
6603   default:
6604     return nullptr;
6605 
6606   case llvm::Triple::xcore:
6607     return new XCoreTargetInfo(Triple);
6608 
6609   case llvm::Triple::hexagon:
6610     return new HexagonTargetInfo(Triple);
6611 
6612   case llvm::Triple::aarch64:
6613     if (Triple.isOSDarwin())
6614       return new DarwinAArch64TargetInfo(Triple);
6615 
6616     switch (os) {
6617     case llvm::Triple::FreeBSD:
6618       return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple);
6619     case llvm::Triple::Linux:
6620       return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
6621     case llvm::Triple::NetBSD:
6622       return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
6623     default:
6624       return new AArch64leTargetInfo(Triple);
6625     }
6626 
6627   case llvm::Triple::aarch64_be:
6628     switch (os) {
6629     case llvm::Triple::FreeBSD:
6630       return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple);
6631     case llvm::Triple::Linux:
6632       return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
6633     case llvm::Triple::NetBSD:
6634       return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
6635     default:
6636       return new AArch64beTargetInfo(Triple);
6637     }
6638 
6639   case llvm::Triple::arm:
6640   case llvm::Triple::thumb:
6641     if (Triple.isOSBinFormatMachO())
6642       return new DarwinARMTargetInfo(Triple);
6643 
6644     switch (os) {
6645     case llvm::Triple::Linux:
6646       return new LinuxTargetInfo<ARMleTargetInfo>(Triple);
6647     case llvm::Triple::FreeBSD:
6648       return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple);
6649     case llvm::Triple::NetBSD:
6650       return new NetBSDTargetInfo<ARMleTargetInfo>(Triple);
6651     case llvm::Triple::OpenBSD:
6652       return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple);
6653     case llvm::Triple::Bitrig:
6654       return new BitrigTargetInfo<ARMleTargetInfo>(Triple);
6655     case llvm::Triple::RTEMS:
6656       return new RTEMSTargetInfo<ARMleTargetInfo>(Triple);
6657     case llvm::Triple::NaCl:
6658       return new NaClTargetInfo<ARMleTargetInfo>(Triple);
6659     case llvm::Triple::Win32:
6660       switch (Triple.getEnvironment()) {
6661       default:
6662         return new ARMleTargetInfo(Triple);
6663       case llvm::Triple::Itanium:
6664         return new ItaniumWindowsARMleTargetInfo(Triple);
6665       case llvm::Triple::MSVC:
6666         return new MicrosoftARMleTargetInfo(Triple);
6667       }
6668     default:
6669       return new ARMleTargetInfo(Triple);
6670     }
6671 
6672   case llvm::Triple::armeb:
6673   case llvm::Triple::thumbeb:
6674     if (Triple.isOSDarwin())
6675       return new DarwinARMTargetInfo(Triple);
6676 
6677     switch (os) {
6678     case llvm::Triple::Linux:
6679       return new LinuxTargetInfo<ARMbeTargetInfo>(Triple);
6680     case llvm::Triple::FreeBSD:
6681       return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple);
6682     case llvm::Triple::NetBSD:
6683       return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple);
6684     case llvm::Triple::OpenBSD:
6685       return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple);
6686     case llvm::Triple::Bitrig:
6687       return new BitrigTargetInfo<ARMbeTargetInfo>(Triple);
6688     case llvm::Triple::RTEMS:
6689       return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple);
6690     case llvm::Triple::NaCl:
6691       return new NaClTargetInfo<ARMbeTargetInfo>(Triple);
6692     default:
6693       return new ARMbeTargetInfo(Triple);
6694     }
6695 
6696   case llvm::Triple::msp430:
6697     return new MSP430TargetInfo(Triple);
6698 
6699   case llvm::Triple::mips:
6700     switch (os) {
6701     case llvm::Triple::Linux:
6702       return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
6703     case llvm::Triple::RTEMS:
6704       return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
6705     case llvm::Triple::FreeBSD:
6706       return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6707     case llvm::Triple::NetBSD:
6708       return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6709     default:
6710       return new Mips32EBTargetInfo(Triple);
6711     }
6712 
6713   case llvm::Triple::mipsel:
6714     switch (os) {
6715     case llvm::Triple::Linux:
6716       return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
6717     case llvm::Triple::RTEMS:
6718       return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
6719     case llvm::Triple::FreeBSD:
6720       return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6721     case llvm::Triple::NetBSD:
6722       return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6723     case llvm::Triple::NaCl:
6724       return new NaClTargetInfo<Mips32ELTargetInfo>(Triple);
6725     default:
6726       return new Mips32ELTargetInfo(Triple);
6727     }
6728 
6729   case llvm::Triple::mips64:
6730     switch (os) {
6731     case llvm::Triple::Linux:
6732       return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
6733     case llvm::Triple::RTEMS:
6734       return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
6735     case llvm::Triple::FreeBSD:
6736       return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6737     case llvm::Triple::NetBSD:
6738       return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6739     case llvm::Triple::OpenBSD:
6740       return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6741     default:
6742       return new Mips64EBTargetInfo(Triple);
6743     }
6744 
6745   case llvm::Triple::mips64el:
6746     switch (os) {
6747     case llvm::Triple::Linux:
6748       return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
6749     case llvm::Triple::RTEMS:
6750       return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
6751     case llvm::Triple::FreeBSD:
6752       return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6753     case llvm::Triple::NetBSD:
6754       return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6755     case llvm::Triple::OpenBSD:
6756       return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6757     default:
6758       return new Mips64ELTargetInfo(Triple);
6759     }
6760 
6761   case llvm::Triple::le32:
6762     switch (os) {
6763       case llvm::Triple::NaCl:
6764         return new NaClTargetInfo<PNaClTargetInfo>(Triple);
6765       default:
6766         return nullptr;
6767     }
6768 
6769   case llvm::Triple::le64:
6770     return new Le64TargetInfo(Triple);
6771 
6772   case llvm::Triple::ppc:
6773     if (Triple.isOSDarwin())
6774       return new DarwinPPC32TargetInfo(Triple);
6775     switch (os) {
6776     case llvm::Triple::Linux:
6777       return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
6778     case llvm::Triple::FreeBSD:
6779       return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
6780     case llvm::Triple::NetBSD:
6781       return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
6782     case llvm::Triple::OpenBSD:
6783       return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
6784     case llvm::Triple::RTEMS:
6785       return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
6786     default:
6787       return new PPC32TargetInfo(Triple);
6788     }
6789 
6790   case llvm::Triple::ppc64:
6791     if (Triple.isOSDarwin())
6792       return new DarwinPPC64TargetInfo(Triple);
6793     switch (os) {
6794     case llvm::Triple::Linux:
6795       return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6796     case llvm::Triple::Lv2:
6797       return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
6798     case llvm::Triple::FreeBSD:
6799       return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
6800     case llvm::Triple::NetBSD:
6801       return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
6802     default:
6803       return new PPC64TargetInfo(Triple);
6804     }
6805 
6806   case llvm::Triple::ppc64le:
6807     switch (os) {
6808     case llvm::Triple::Linux:
6809       return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6810     default:
6811       return new PPC64TargetInfo(Triple);
6812     }
6813 
6814   case llvm::Triple::nvptx:
6815     return new NVPTX32TargetInfo(Triple);
6816   case llvm::Triple::nvptx64:
6817     return new NVPTX64TargetInfo(Triple);
6818 
6819   case llvm::Triple::amdgcn:
6820   case llvm::Triple::r600:
6821     return new R600TargetInfo(Triple);
6822 
6823   case llvm::Triple::sparc:
6824     switch (os) {
6825     case llvm::Triple::Linux:
6826       return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
6827     case llvm::Triple::Solaris:
6828       return new SolarisSparcV8TargetInfo(Triple);
6829     case llvm::Triple::NetBSD:
6830       return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
6831     case llvm::Triple::OpenBSD:
6832       return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
6833     case llvm::Triple::RTEMS:
6834       return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
6835     default:
6836       return new SparcV8TargetInfo(Triple);
6837     }
6838 
6839   case llvm::Triple::sparcv9:
6840     switch (os) {
6841     case llvm::Triple::Linux:
6842       return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
6843     case llvm::Triple::Solaris:
6844       return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
6845     case llvm::Triple::NetBSD:
6846       return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
6847     case llvm::Triple::OpenBSD:
6848       return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
6849     case llvm::Triple::FreeBSD:
6850       return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
6851     default:
6852       return new SparcV9TargetInfo(Triple);
6853     }
6854 
6855   case llvm::Triple::systemz:
6856     switch (os) {
6857     case llvm::Triple::Linux:
6858       return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
6859     default:
6860       return new SystemZTargetInfo(Triple);
6861     }
6862 
6863   case llvm::Triple::tce:
6864     return new TCETargetInfo(Triple);
6865 
6866   case llvm::Triple::x86:
6867     if (Triple.isOSDarwin())
6868       return new DarwinI386TargetInfo(Triple);
6869 
6870     switch (os) {
6871     case llvm::Triple::Linux:
6872       return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
6873     case llvm::Triple::DragonFly:
6874       return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
6875     case llvm::Triple::NetBSD:
6876       return new NetBSDI386TargetInfo(Triple);
6877     case llvm::Triple::OpenBSD:
6878       return new OpenBSDI386TargetInfo(Triple);
6879     case llvm::Triple::Bitrig:
6880       return new BitrigI386TargetInfo(Triple);
6881     case llvm::Triple::FreeBSD:
6882       return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6883     case llvm::Triple::KFreeBSD:
6884       return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6885     case llvm::Triple::Minix:
6886       return new MinixTargetInfo<X86_32TargetInfo>(Triple);
6887     case llvm::Triple::Solaris:
6888       return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
6889     case llvm::Triple::Win32: {
6890       switch (Triple.getEnvironment()) {
6891       default:
6892         return new X86_32TargetInfo(Triple);
6893       case llvm::Triple::Cygnus:
6894         return new CygwinX86_32TargetInfo(Triple);
6895       case llvm::Triple::GNU:
6896         return new MinGWX86_32TargetInfo(Triple);
6897       case llvm::Triple::Itanium:
6898       case llvm::Triple::MSVC:
6899         return new MicrosoftX86_32TargetInfo(Triple);
6900       }
6901     }
6902     case llvm::Triple::Haiku:
6903       return new HaikuX86_32TargetInfo(Triple);
6904     case llvm::Triple::RTEMS:
6905       return new RTEMSX86_32TargetInfo(Triple);
6906     case llvm::Triple::NaCl:
6907       return new NaClTargetInfo<X86_32TargetInfo>(Triple);
6908     default:
6909       return new X86_32TargetInfo(Triple);
6910     }
6911 
6912   case llvm::Triple::x86_64:
6913     if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
6914       return new DarwinX86_64TargetInfo(Triple);
6915 
6916     switch (os) {
6917     case llvm::Triple::CloudABI:
6918       return new CloudABITargetInfo<X86_64TargetInfo>(Triple);
6919     case llvm::Triple::Linux:
6920       return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
6921     case llvm::Triple::DragonFly:
6922       return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
6923     case llvm::Triple::NetBSD:
6924       return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
6925     case llvm::Triple::OpenBSD:
6926       return new OpenBSDX86_64TargetInfo(Triple);
6927     case llvm::Triple::Bitrig:
6928       return new BitrigX86_64TargetInfo(Triple);
6929     case llvm::Triple::FreeBSD:
6930       return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6931     case llvm::Triple::KFreeBSD:
6932       return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6933     case llvm::Triple::Solaris:
6934       return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
6935     case llvm::Triple::Win32: {
6936       switch (Triple.getEnvironment()) {
6937       default:
6938         return new X86_64TargetInfo(Triple);
6939       case llvm::Triple::GNU:
6940         return new MinGWX86_64TargetInfo(Triple);
6941       case llvm::Triple::MSVC:
6942         return new MicrosoftX86_64TargetInfo(Triple);
6943       }
6944     }
6945     case llvm::Triple::NaCl:
6946       return new NaClTargetInfo<X86_64TargetInfo>(Triple);
6947     case llvm::Triple::PS4:
6948       return new PS4OSTargetInfo<X86_64TargetInfo>(Triple);
6949     default:
6950       return new X86_64TargetInfo(Triple);
6951     }
6952 
6953     case llvm::Triple::spir: {
6954       if (Triple.getOS() != llvm::Triple::UnknownOS ||
6955           Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6956         return nullptr;
6957       return new SPIR32TargetInfo(Triple);
6958     }
6959     case llvm::Triple::spir64: {
6960       if (Triple.getOS() != llvm::Triple::UnknownOS ||
6961           Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6962         return nullptr;
6963       return new SPIR64TargetInfo(Triple);
6964     }
6965   }
6966 }
6967 
6968 /// CreateTargetInfo - Return the target info object for the specified target
6969 /// triple.
6970 TargetInfo *
6971 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
6972                              const std::shared_ptr<TargetOptions> &Opts) {
6973   llvm::Triple Triple(Opts->Triple);
6974 
6975   // Construct the target
6976   std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple));
6977   if (!Target) {
6978     Diags.Report(diag::err_target_unknown_triple) << Triple.str();
6979     return nullptr;
6980   }
6981   Target->TargetOpts = Opts;
6982 
6983   // Set the target CPU if specified.
6984   if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
6985     Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
6986     return nullptr;
6987   }
6988 
6989   // Set the target ABI if specified.
6990   if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
6991     Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
6992     return nullptr;
6993   }
6994 
6995   // Set the fp math unit.
6996   if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
6997     Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
6998     return nullptr;
6999   }
7000 
7001   // Compute the default target features, we need the target to handle this
7002   // because features may have dependencies on one another.
7003   llvm::StringMap<bool> Features;
7004   Target->getDefaultFeatures(Features);
7005 
7006   // Apply the user specified deltas.
7007   for (unsigned I = 0, N = Opts->FeaturesAsWritten.size();
7008        I < N; ++I) {
7009     const char *Name = Opts->FeaturesAsWritten[I].c_str();
7010     // Apply the feature via the target.
7011     bool Enabled = Name[0] == '+';
7012     Target->setFeatureEnabled(Features, Name + 1, Enabled);
7013   }
7014 
7015   // Add the features to the compile options.
7016   //
7017   // FIXME: If we are completely confident that we have the right set, we only
7018   // need to pass the minuses.
7019   Opts->Features.clear();
7020   for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
7021          ie = Features.end(); it != ie; ++it)
7022     Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
7023   if (!Target->handleTargetFeatures(Opts->Features, Diags))
7024     return nullptr;
7025 
7026   return Target.release();
7027 }
7028