1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/TargetParser.h" 31 #include <algorithm> 32 #include <memory> 33 using namespace clang; 34 35 //===----------------------------------------------------------------------===// 36 // Common code shared among targets. 37 //===----------------------------------------------------------------------===// 38 39 /// DefineStd - Define a macro name and standard variants. For example if 40 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 41 /// when in GNU mode. 42 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 43 const LangOptions &Opts) { 44 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 45 46 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 47 // in the user's namespace. 48 if (Opts.GNUMode) 49 Builder.defineMacro(MacroName); 50 51 // Define __unix. 52 Builder.defineMacro("__" + MacroName); 53 54 // Define __unix__. 55 Builder.defineMacro("__" + MacroName + "__"); 56 } 57 58 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 59 bool Tuning = true) { 60 Builder.defineMacro("__" + CPUName); 61 Builder.defineMacro("__" + CPUName + "__"); 62 if (Tuning) 63 Builder.defineMacro("__tune_" + CPUName + "__"); 64 } 65 66 //===----------------------------------------------------------------------===// 67 // Defines specific to certain operating systems. 68 //===----------------------------------------------------------------------===// 69 70 namespace { 71 template<typename TgtInfo> 72 class OSTargetInfo : public TgtInfo { 73 protected: 74 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 75 MacroBuilder &Builder) const=0; 76 public: 77 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 78 void getTargetDefines(const LangOptions &Opts, 79 MacroBuilder &Builder) const override { 80 TgtInfo::getTargetDefines(Opts, Builder); 81 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 82 } 83 84 }; 85 } // end anonymous namespace 86 87 88 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 89 const llvm::Triple &Triple, 90 StringRef &PlatformName, 91 VersionTuple &PlatformMinVersion) { 92 Builder.defineMacro("__APPLE_CC__", "6000"); 93 Builder.defineMacro("__APPLE__"); 94 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 95 // AddressSanitizer doesn't play well with source fortification, which is on 96 // by default on Darwin. 97 if (Opts.Sanitize.has(SanitizerKind::Address)) 98 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 99 100 if (!Opts.ObjCAutoRefCount) { 101 // __weak is always defined, for use in blocks and with objc pointers. 102 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 103 104 // Darwin defines __strong even in C mode (just to nothing). 105 if (Opts.getGC() != LangOptions::NonGC) 106 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 107 else 108 Builder.defineMacro("__strong", ""); 109 110 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 111 // allow this in C, since one might have block pointers in structs that 112 // are used in pure C code and in Objective-C ARC. 113 Builder.defineMacro("__unsafe_unretained", ""); 114 } 115 116 if (Opts.Static) 117 Builder.defineMacro("__STATIC__"); 118 else 119 Builder.defineMacro("__DYNAMIC__"); 120 121 if (Opts.POSIXThreads) 122 Builder.defineMacro("_REENTRANT"); 123 124 // Get the platform type and version number from the triple. 125 unsigned Maj, Min, Rev; 126 if (Triple.isMacOSX()) { 127 Triple.getMacOSXVersion(Maj, Min, Rev); 128 PlatformName = "macosx"; 129 } else { 130 Triple.getOSVersion(Maj, Min, Rev); 131 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 132 } 133 134 // If -target arch-pc-win32-macho option specified, we're 135 // generating code for Win32 ABI. No need to emit 136 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 137 if (PlatformName == "win32") { 138 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 139 return; 140 } 141 142 // Set the appropriate OS version define. 143 if (Triple.isiOS()) { 144 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 145 char Str[6]; 146 Str[0] = '0' + Maj; 147 Str[1] = '0' + (Min / 10); 148 Str[2] = '0' + (Min % 10); 149 Str[3] = '0' + (Rev / 10); 150 Str[4] = '0' + (Rev % 10); 151 Str[5] = '\0'; 152 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 153 Str); 154 } else if (Triple.isMacOSX()) { 155 // Note that the Driver allows versions which aren't representable in the 156 // define (because we only get a single digit for the minor and micro 157 // revision numbers). So, we limit them to the maximum representable 158 // version. 159 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 160 char Str[7]; 161 if (Maj < 10 || (Maj == 10 && Min < 10)) { 162 Str[0] = '0' + (Maj / 10); 163 Str[1] = '0' + (Maj % 10); 164 Str[2] = '0' + std::min(Min, 9U); 165 Str[3] = '0' + std::min(Rev, 9U); 166 Str[4] = '\0'; 167 } else { 168 // Handle versions > 10.9. 169 Str[0] = '0' + (Maj / 10); 170 Str[1] = '0' + (Maj % 10); 171 Str[2] = '0' + (Min / 10); 172 Str[3] = '0' + (Min % 10); 173 Str[4] = '0' + (Rev / 10); 174 Str[5] = '0' + (Rev % 10); 175 Str[6] = '\0'; 176 } 177 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 178 } 179 180 // Tell users about the kernel if there is one. 181 if (Triple.isOSDarwin()) 182 Builder.defineMacro("__MACH__"); 183 184 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 185 } 186 187 namespace { 188 // CloudABI Target 189 template <typename Target> 190 class CloudABITargetInfo : public OSTargetInfo<Target> { 191 protected: 192 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 193 MacroBuilder &Builder) const override { 194 Builder.defineMacro("__CloudABI__"); 195 Builder.defineMacro("__ELF__"); 196 197 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 198 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 199 Builder.defineMacro("__STDC_UTF_16__"); 200 Builder.defineMacro("__STDC_UTF_32__"); 201 } 202 203 public: 204 CloudABITargetInfo(const llvm::Triple &Triple) 205 : OSTargetInfo<Target>(Triple) { 206 this->UserLabelPrefix = ""; 207 } 208 }; 209 210 template<typename Target> 211 class DarwinTargetInfo : public OSTargetInfo<Target> { 212 protected: 213 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 214 MacroBuilder &Builder) const override { 215 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 216 this->PlatformMinVersion); 217 } 218 219 public: 220 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 221 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 222 this->MCountName = "\01mcount"; 223 } 224 225 std::string isValidSectionSpecifier(StringRef SR) const override { 226 // Let MCSectionMachO validate this. 227 StringRef Segment, Section; 228 unsigned TAA, StubSize; 229 bool HasTAA; 230 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 231 TAA, HasTAA, StubSize); 232 } 233 234 const char *getStaticInitSectionSpecifier() const override { 235 // FIXME: We should return 0 when building kexts. 236 return "__TEXT,__StaticInit,regular,pure_instructions"; 237 } 238 239 /// Darwin does not support protected visibility. Darwin's "default" 240 /// is very similar to ELF's "protected"; Darwin requires a "weak" 241 /// attribute on declarations that can be dynamically replaced. 242 bool hasProtectedVisibility() const override { 243 return false; 244 } 245 }; 246 247 248 // DragonFlyBSD Target 249 template<typename Target> 250 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 251 protected: 252 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 253 MacroBuilder &Builder) const override { 254 // DragonFly defines; list based off of gcc output 255 Builder.defineMacro("__DragonFly__"); 256 Builder.defineMacro("__DragonFly_cc_version", "100001"); 257 Builder.defineMacro("__ELF__"); 258 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 259 Builder.defineMacro("__tune_i386__"); 260 DefineStd(Builder, "unix", Opts); 261 } 262 public: 263 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 264 : OSTargetInfo<Target>(Triple) { 265 this->UserLabelPrefix = ""; 266 267 switch (Triple.getArch()) { 268 default: 269 case llvm::Triple::x86: 270 case llvm::Triple::x86_64: 271 this->MCountName = ".mcount"; 272 break; 273 } 274 } 275 }; 276 277 // FreeBSD Target 278 template<typename Target> 279 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 280 protected: 281 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 282 MacroBuilder &Builder) const override { 283 // FreeBSD defines; list based off of gcc output 284 285 unsigned Release = Triple.getOSMajorVersion(); 286 if (Release == 0U) 287 Release = 8; 288 289 Builder.defineMacro("__FreeBSD__", Twine(Release)); 290 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 291 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 292 DefineStd(Builder, "unix", Opts); 293 Builder.defineMacro("__ELF__"); 294 295 // On FreeBSD, wchar_t contains the number of the code point as 296 // used by the character set of the locale. These character sets are 297 // not necessarily a superset of ASCII. 298 // 299 // FIXME: This is wrong; the macro refers to the numerical values 300 // of wchar_t *literals*, which are not locale-dependent. However, 301 // FreeBSD systems apparently depend on us getting this wrong, and 302 // setting this to 1 is conforming even if all the basic source 303 // character literals have the same encoding as char and wchar_t. 304 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 305 } 306 public: 307 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 308 this->UserLabelPrefix = ""; 309 310 switch (Triple.getArch()) { 311 default: 312 case llvm::Triple::x86: 313 case llvm::Triple::x86_64: 314 this->MCountName = ".mcount"; 315 break; 316 case llvm::Triple::mips: 317 case llvm::Triple::mipsel: 318 case llvm::Triple::ppc: 319 case llvm::Triple::ppc64: 320 case llvm::Triple::ppc64le: 321 this->MCountName = "_mcount"; 322 break; 323 case llvm::Triple::arm: 324 this->MCountName = "__mcount"; 325 break; 326 } 327 } 328 }; 329 330 // GNU/kFreeBSD Target 331 template<typename Target> 332 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 333 protected: 334 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 335 MacroBuilder &Builder) const override { 336 // GNU/kFreeBSD defines; list based off of gcc output 337 338 DefineStd(Builder, "unix", Opts); 339 Builder.defineMacro("__FreeBSD_kernel__"); 340 Builder.defineMacro("__GLIBC__"); 341 Builder.defineMacro("__ELF__"); 342 if (Opts.POSIXThreads) 343 Builder.defineMacro("_REENTRANT"); 344 if (Opts.CPlusPlus) 345 Builder.defineMacro("_GNU_SOURCE"); 346 } 347 public: 348 KFreeBSDTargetInfo(const llvm::Triple &Triple) 349 : OSTargetInfo<Target>(Triple) { 350 this->UserLabelPrefix = ""; 351 } 352 }; 353 354 // Minix Target 355 template<typename Target> 356 class MinixTargetInfo : public OSTargetInfo<Target> { 357 protected: 358 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 359 MacroBuilder &Builder) const override { 360 // Minix defines 361 362 Builder.defineMacro("__minix", "3"); 363 Builder.defineMacro("_EM_WSIZE", "4"); 364 Builder.defineMacro("_EM_PSIZE", "4"); 365 Builder.defineMacro("_EM_SSIZE", "2"); 366 Builder.defineMacro("_EM_LSIZE", "4"); 367 Builder.defineMacro("_EM_FSIZE", "4"); 368 Builder.defineMacro("_EM_DSIZE", "8"); 369 Builder.defineMacro("__ELF__"); 370 DefineStd(Builder, "unix", Opts); 371 } 372 public: 373 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 374 this->UserLabelPrefix = ""; 375 } 376 }; 377 378 // Linux target 379 template<typename Target> 380 class LinuxTargetInfo : public OSTargetInfo<Target> { 381 protected: 382 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 383 MacroBuilder &Builder) const override { 384 // Linux defines; list based off of gcc output 385 DefineStd(Builder, "unix", Opts); 386 DefineStd(Builder, "linux", Opts); 387 Builder.defineMacro("__gnu_linux__"); 388 Builder.defineMacro("__ELF__"); 389 if (Triple.getEnvironment() == llvm::Triple::Android) { 390 Builder.defineMacro("__ANDROID__", "1"); 391 unsigned Maj, Min, Rev; 392 Triple.getEnvironmentVersion(Maj, Min, Rev); 393 this->PlatformName = "android"; 394 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 395 } 396 if (Opts.POSIXThreads) 397 Builder.defineMacro("_REENTRANT"); 398 if (Opts.CPlusPlus) 399 Builder.defineMacro("_GNU_SOURCE"); 400 } 401 public: 402 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 403 this->UserLabelPrefix = ""; 404 this->WIntType = TargetInfo::UnsignedInt; 405 406 switch (Triple.getArch()) { 407 default: 408 break; 409 case llvm::Triple::ppc: 410 case llvm::Triple::ppc64: 411 case llvm::Triple::ppc64le: 412 this->MCountName = "_mcount"; 413 break; 414 } 415 } 416 417 const char *getStaticInitSectionSpecifier() const override { 418 return ".text.startup"; 419 } 420 }; 421 422 // NetBSD Target 423 template<typename Target> 424 class NetBSDTargetInfo : public OSTargetInfo<Target> { 425 protected: 426 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 427 MacroBuilder &Builder) const override { 428 // NetBSD defines; list based off of gcc output 429 Builder.defineMacro("__NetBSD__"); 430 Builder.defineMacro("__unix__"); 431 Builder.defineMacro("__ELF__"); 432 if (Opts.POSIXThreads) 433 Builder.defineMacro("_POSIX_THREADS"); 434 435 switch (Triple.getArch()) { 436 default: 437 break; 438 case llvm::Triple::arm: 439 case llvm::Triple::armeb: 440 case llvm::Triple::thumb: 441 case llvm::Triple::thumbeb: 442 Builder.defineMacro("__ARM_DWARF_EH__"); 443 break; 444 } 445 } 446 public: 447 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 448 this->UserLabelPrefix = ""; 449 this->MCountName = "_mcount"; 450 } 451 }; 452 453 // OpenBSD Target 454 template<typename Target> 455 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 456 protected: 457 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 458 MacroBuilder &Builder) const override { 459 // OpenBSD defines; list based off of gcc output 460 461 Builder.defineMacro("__OpenBSD__"); 462 DefineStd(Builder, "unix", Opts); 463 Builder.defineMacro("__ELF__"); 464 if (Opts.POSIXThreads) 465 Builder.defineMacro("_REENTRANT"); 466 } 467 public: 468 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 469 this->UserLabelPrefix = ""; 470 this->TLSSupported = false; 471 472 switch (Triple.getArch()) { 473 default: 474 case llvm::Triple::x86: 475 case llvm::Triple::x86_64: 476 case llvm::Triple::arm: 477 case llvm::Triple::sparc: 478 this->MCountName = "__mcount"; 479 break; 480 case llvm::Triple::mips64: 481 case llvm::Triple::mips64el: 482 case llvm::Triple::ppc: 483 case llvm::Triple::sparcv9: 484 this->MCountName = "_mcount"; 485 break; 486 } 487 } 488 }; 489 490 // Bitrig Target 491 template<typename Target> 492 class BitrigTargetInfo : public OSTargetInfo<Target> { 493 protected: 494 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 495 MacroBuilder &Builder) const override { 496 // Bitrig defines; list based off of gcc output 497 498 Builder.defineMacro("__Bitrig__"); 499 DefineStd(Builder, "unix", Opts); 500 Builder.defineMacro("__ELF__"); 501 if (Opts.POSIXThreads) 502 Builder.defineMacro("_REENTRANT"); 503 504 switch (Triple.getArch()) { 505 default: 506 break; 507 case llvm::Triple::arm: 508 case llvm::Triple::armeb: 509 case llvm::Triple::thumb: 510 case llvm::Triple::thumbeb: 511 Builder.defineMacro("__ARM_DWARF_EH__"); 512 break; 513 } 514 } 515 public: 516 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 517 this->UserLabelPrefix = ""; 518 this->MCountName = "__mcount"; 519 } 520 }; 521 522 // PSP Target 523 template<typename Target> 524 class PSPTargetInfo : public OSTargetInfo<Target> { 525 protected: 526 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 527 MacroBuilder &Builder) const override { 528 // PSP defines; list based on the output of the pspdev gcc toolchain. 529 Builder.defineMacro("PSP"); 530 Builder.defineMacro("_PSP"); 531 Builder.defineMacro("__psp__"); 532 Builder.defineMacro("__ELF__"); 533 } 534 public: 535 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 536 this->UserLabelPrefix = ""; 537 } 538 }; 539 540 // PS3 PPU Target 541 template<typename Target> 542 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 543 protected: 544 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 545 MacroBuilder &Builder) const override { 546 // PS3 PPU defines. 547 Builder.defineMacro("__PPC__"); 548 Builder.defineMacro("__PPU__"); 549 Builder.defineMacro("__CELLOS_LV2__"); 550 Builder.defineMacro("__ELF__"); 551 Builder.defineMacro("__LP32__"); 552 Builder.defineMacro("_ARCH_PPC64"); 553 Builder.defineMacro("__powerpc64__"); 554 } 555 public: 556 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 557 this->UserLabelPrefix = ""; 558 this->LongWidth = this->LongAlign = 32; 559 this->PointerWidth = this->PointerAlign = 32; 560 this->IntMaxType = TargetInfo::SignedLongLong; 561 this->Int64Type = TargetInfo::SignedLongLong; 562 this->SizeType = TargetInfo::UnsignedInt; 563 this->DataLayoutString = "E-m:e-p:32:32-i64:64-n32:64"; 564 } 565 }; 566 567 template <typename Target> 568 class PS4OSTargetInfo : public OSTargetInfo<Target> { 569 protected: 570 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 571 MacroBuilder &Builder) const override { 572 Builder.defineMacro("__FreeBSD__", "9"); 573 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 574 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 575 DefineStd(Builder, "unix", Opts); 576 Builder.defineMacro("__ELF__"); 577 Builder.defineMacro("__PS4__"); 578 } 579 public: 580 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 581 this->WCharType = this->UnsignedShort; 582 583 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 584 this->MaxTLSAlign = 256; 585 this->UserLabelPrefix = ""; 586 587 switch (Triple.getArch()) { 588 default: 589 case llvm::Triple::x86_64: 590 this->MCountName = ".mcount"; 591 break; 592 } 593 } 594 }; 595 596 // Solaris target 597 template<typename Target> 598 class SolarisTargetInfo : public OSTargetInfo<Target> { 599 protected: 600 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 601 MacroBuilder &Builder) const override { 602 DefineStd(Builder, "sun", Opts); 603 DefineStd(Builder, "unix", Opts); 604 Builder.defineMacro("__ELF__"); 605 Builder.defineMacro("__svr4__"); 606 Builder.defineMacro("__SVR4"); 607 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 608 // newer, but to 500 for everything else. feature_test.h has a check to 609 // ensure that you are not using C99 with an old version of X/Open or C89 610 // with a new version. 611 if (Opts.C99) 612 Builder.defineMacro("_XOPEN_SOURCE", "600"); 613 else 614 Builder.defineMacro("_XOPEN_SOURCE", "500"); 615 if (Opts.CPlusPlus) 616 Builder.defineMacro("__C99FEATURES__"); 617 Builder.defineMacro("_LARGEFILE_SOURCE"); 618 Builder.defineMacro("_LARGEFILE64_SOURCE"); 619 Builder.defineMacro("__EXTENSIONS__"); 620 Builder.defineMacro("_REENTRANT"); 621 } 622 public: 623 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 624 this->UserLabelPrefix = ""; 625 this->WCharType = this->SignedInt; 626 // FIXME: WIntType should be SignedLong 627 } 628 }; 629 630 // Windows target 631 template<typename Target> 632 class WindowsTargetInfo : public OSTargetInfo<Target> { 633 protected: 634 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 635 MacroBuilder &Builder) const override { 636 Builder.defineMacro("_WIN32"); 637 } 638 void getVisualStudioDefines(const LangOptions &Opts, 639 MacroBuilder &Builder) const { 640 if (Opts.CPlusPlus) { 641 if (Opts.RTTIData) 642 Builder.defineMacro("_CPPRTTI"); 643 644 if (Opts.CXXExceptions) 645 Builder.defineMacro("_CPPUNWIND"); 646 } 647 648 if (Opts.Bool) 649 Builder.defineMacro("__BOOL_DEFINED"); 650 651 if (!Opts.CharIsSigned) 652 Builder.defineMacro("_CHAR_UNSIGNED"); 653 654 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 655 // but it works for now. 656 if (Opts.POSIXThreads) 657 Builder.defineMacro("_MT"); 658 659 if (Opts.MSCompatibilityVersion) { 660 Builder.defineMacro("_MSC_VER", 661 Twine(Opts.MSCompatibilityVersion / 100000)); 662 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 663 // FIXME We cannot encode the revision information into 32-bits 664 Builder.defineMacro("_MSC_BUILD", Twine(1)); 665 666 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 667 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 668 } 669 670 if (Opts.MicrosoftExt) { 671 Builder.defineMacro("_MSC_EXTENSIONS"); 672 673 if (Opts.CPlusPlus11) { 674 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 675 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 676 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 677 } 678 } 679 680 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 681 } 682 683 public: 684 WindowsTargetInfo(const llvm::Triple &Triple) 685 : OSTargetInfo<Target>(Triple) {} 686 }; 687 688 template <typename Target> 689 class NaClTargetInfo : public OSTargetInfo<Target> { 690 protected: 691 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 692 MacroBuilder &Builder) const override { 693 if (Opts.POSIXThreads) 694 Builder.defineMacro("_REENTRANT"); 695 if (Opts.CPlusPlus) 696 Builder.defineMacro("_GNU_SOURCE"); 697 698 DefineStd(Builder, "unix", Opts); 699 Builder.defineMacro("__ELF__"); 700 Builder.defineMacro("__native_client__"); 701 } 702 703 public: 704 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 705 this->UserLabelPrefix = ""; 706 this->LongAlign = 32; 707 this->LongWidth = 32; 708 this->PointerAlign = 32; 709 this->PointerWidth = 32; 710 this->IntMaxType = TargetInfo::SignedLongLong; 711 this->Int64Type = TargetInfo::SignedLongLong; 712 this->DoubleAlign = 64; 713 this->LongDoubleWidth = 64; 714 this->LongDoubleAlign = 64; 715 this->LongLongWidth = 64; 716 this->LongLongAlign = 64; 717 this->SizeType = TargetInfo::UnsignedInt; 718 this->PtrDiffType = TargetInfo::SignedInt; 719 this->IntPtrType = TargetInfo::SignedInt; 720 // RegParmMax is inherited from the underlying architecture 721 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 722 if (Triple.getArch() == llvm::Triple::arm) { 723 // Handled in ARM's setABI(). 724 } else if (Triple.getArch() == llvm::Triple::x86) { 725 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 726 } else if (Triple.getArch() == llvm::Triple::x86_64) { 727 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 728 } else if (Triple.getArch() == llvm::Triple::mipsel) { 729 // Handled on mips' setDataLayoutString. 730 } else { 731 assert(Triple.getArch() == llvm::Triple::le32); 732 this->DataLayoutString = "e-p:32:32-i64:64"; 733 } 734 } 735 }; 736 737 //===----------------------------------------------------------------------===// 738 // Specific target implementations. 739 //===----------------------------------------------------------------------===// 740 741 // PPC abstract base class 742 class PPCTargetInfo : public TargetInfo { 743 static const Builtin::Info BuiltinInfo[]; 744 static const char * const GCCRegNames[]; 745 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 746 std::string CPU; 747 748 // Target cpu features. 749 bool HasVSX; 750 bool HasP8Vector; 751 bool HasP8Crypto; 752 bool HasDirectMove; 753 bool HasQPX; 754 bool HasHTM; 755 bool HasBPERMD; 756 bool HasExtDiv; 757 758 protected: 759 std::string ABI; 760 761 public: 762 PPCTargetInfo(const llvm::Triple &Triple) 763 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 764 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 765 HasBPERMD(false), HasExtDiv(false) { 766 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 767 SimdDefaultAlign = 128; 768 LongDoubleWidth = LongDoubleAlign = 128; 769 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 770 } 771 772 /// \brief Flags for architecture specific defines. 773 typedef enum { 774 ArchDefineNone = 0, 775 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 776 ArchDefinePpcgr = 1 << 1, 777 ArchDefinePpcsq = 1 << 2, 778 ArchDefine440 = 1 << 3, 779 ArchDefine603 = 1 << 4, 780 ArchDefine604 = 1 << 5, 781 ArchDefinePwr4 = 1 << 6, 782 ArchDefinePwr5 = 1 << 7, 783 ArchDefinePwr5x = 1 << 8, 784 ArchDefinePwr6 = 1 << 9, 785 ArchDefinePwr6x = 1 << 10, 786 ArchDefinePwr7 = 1 << 11, 787 ArchDefinePwr8 = 1 << 12, 788 ArchDefineA2 = 1 << 13, 789 ArchDefineA2q = 1 << 14 790 } ArchDefineTypes; 791 792 // Note: GCC recognizes the following additional cpus: 793 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 794 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 795 // titan, rs64. 796 bool setCPU(const std::string &Name) override { 797 bool CPUKnown = llvm::StringSwitch<bool>(Name) 798 .Case("generic", true) 799 .Case("440", true) 800 .Case("450", true) 801 .Case("601", true) 802 .Case("602", true) 803 .Case("603", true) 804 .Case("603e", true) 805 .Case("603ev", true) 806 .Case("604", true) 807 .Case("604e", true) 808 .Case("620", true) 809 .Case("630", true) 810 .Case("g3", true) 811 .Case("7400", true) 812 .Case("g4", true) 813 .Case("7450", true) 814 .Case("g4+", true) 815 .Case("750", true) 816 .Case("970", true) 817 .Case("g5", true) 818 .Case("a2", true) 819 .Case("a2q", true) 820 .Case("e500mc", true) 821 .Case("e5500", true) 822 .Case("power3", true) 823 .Case("pwr3", true) 824 .Case("power4", true) 825 .Case("pwr4", true) 826 .Case("power5", true) 827 .Case("pwr5", true) 828 .Case("power5x", true) 829 .Case("pwr5x", true) 830 .Case("power6", true) 831 .Case("pwr6", true) 832 .Case("power6x", true) 833 .Case("pwr6x", true) 834 .Case("power7", true) 835 .Case("pwr7", true) 836 .Case("power8", true) 837 .Case("pwr8", true) 838 .Case("powerpc", true) 839 .Case("ppc", true) 840 .Case("powerpc64", true) 841 .Case("ppc64", true) 842 .Case("powerpc64le", true) 843 .Case("ppc64le", true) 844 .Default(false); 845 846 if (CPUKnown) 847 CPU = Name; 848 849 return CPUKnown; 850 } 851 852 853 StringRef getABI() const override { return ABI; } 854 855 void getTargetBuiltins(const Builtin::Info *&Records, 856 unsigned &NumRecords) const override { 857 Records = BuiltinInfo; 858 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 859 } 860 861 bool isCLZForZeroUndef() const override { return false; } 862 863 void getTargetDefines(const LangOptions &Opts, 864 MacroBuilder &Builder) const override; 865 866 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 867 868 bool handleTargetFeatures(std::vector<std::string> &Features, 869 DiagnosticsEngine &Diags) override; 870 bool hasFeature(StringRef Feature) const override; 871 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 872 bool Enabled) const override; 873 874 void getGCCRegNames(const char * const *&Names, 875 unsigned &NumNames) const override; 876 void getGCCRegAliases(const GCCRegAlias *&Aliases, 877 unsigned &NumAliases) const override; 878 bool validateAsmConstraint(const char *&Name, 879 TargetInfo::ConstraintInfo &Info) const override { 880 switch (*Name) { 881 default: return false; 882 case 'O': // Zero 883 break; 884 case 'b': // Base register 885 case 'f': // Floating point register 886 Info.setAllowsRegister(); 887 break; 888 // FIXME: The following are added to allow parsing. 889 // I just took a guess at what the actions should be. 890 // Also, is more specific checking needed? I.e. specific registers? 891 case 'd': // Floating point register (containing 64-bit value) 892 case 'v': // Altivec vector register 893 Info.setAllowsRegister(); 894 break; 895 case 'w': 896 switch (Name[1]) { 897 case 'd':// VSX vector register to hold vector double data 898 case 'f':// VSX vector register to hold vector float data 899 case 's':// VSX vector register to hold scalar float data 900 case 'a':// Any VSX register 901 case 'c':// An individual CR bit 902 break; 903 default: 904 return false; 905 } 906 Info.setAllowsRegister(); 907 Name++; // Skip over 'w'. 908 break; 909 case 'h': // `MQ', `CTR', or `LINK' register 910 case 'q': // `MQ' register 911 case 'c': // `CTR' register 912 case 'l': // `LINK' register 913 case 'x': // `CR' register (condition register) number 0 914 case 'y': // `CR' register (condition register) 915 case 'z': // `XER[CA]' carry bit (part of the XER register) 916 Info.setAllowsRegister(); 917 break; 918 case 'I': // Signed 16-bit constant 919 case 'J': // Unsigned 16-bit constant shifted left 16 bits 920 // (use `L' instead for SImode constants) 921 case 'K': // Unsigned 16-bit constant 922 case 'L': // Signed 16-bit constant shifted left 16 bits 923 case 'M': // Constant larger than 31 924 case 'N': // Exact power of 2 925 case 'P': // Constant whose negation is a signed 16-bit constant 926 case 'G': // Floating point constant that can be loaded into a 927 // register with one instruction per word 928 case 'H': // Integer/Floating point constant that can be loaded 929 // into a register using three instructions 930 break; 931 case 'm': // Memory operand. Note that on PowerPC targets, m can 932 // include addresses that update the base register. It 933 // is therefore only safe to use `m' in an asm statement 934 // if that asm statement accesses the operand exactly once. 935 // The asm statement must also use `%U<opno>' as a 936 // placeholder for the "update" flag in the corresponding 937 // load or store instruction. For example: 938 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 939 // is correct but: 940 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 941 // is not. Use es rather than m if you don't want the base 942 // register to be updated. 943 case 'e': 944 if (Name[1] != 's') 945 return false; 946 // es: A "stable" memory operand; that is, one which does not 947 // include any automodification of the base register. Unlike 948 // `m', this constraint can be used in asm statements that 949 // might access the operand several times, or that might not 950 // access it at all. 951 Info.setAllowsMemory(); 952 Name++; // Skip over 'e'. 953 break; 954 case 'Q': // Memory operand that is an offset from a register (it is 955 // usually better to use `m' or `es' in asm statements) 956 case 'Z': // Memory operand that is an indexed or indirect from a 957 // register (it is usually better to use `m' or `es' in 958 // asm statements) 959 Info.setAllowsMemory(); 960 Info.setAllowsRegister(); 961 break; 962 case 'R': // AIX TOC entry 963 case 'a': // Address operand that is an indexed or indirect from a 964 // register (`p' is preferable for asm statements) 965 case 'S': // Constant suitable as a 64-bit mask operand 966 case 'T': // Constant suitable as a 32-bit mask operand 967 case 'U': // System V Release 4 small data area reference 968 case 't': // AND masks that can be performed by two rldic{l, r} 969 // instructions 970 case 'W': // Vector constant that does not require memory 971 case 'j': // Vector constant that is all zeros. 972 break; 973 // End FIXME. 974 } 975 return true; 976 } 977 std::string convertConstraint(const char *&Constraint) const override { 978 std::string R; 979 switch (*Constraint) { 980 case 'e': 981 case 'w': 982 // Two-character constraint; add "^" hint for later parsing. 983 R = std::string("^") + std::string(Constraint, 2); 984 Constraint++; 985 break; 986 default: 987 return TargetInfo::convertConstraint(Constraint); 988 } 989 return R; 990 } 991 const char *getClobbers() const override { 992 return ""; 993 } 994 int getEHDataRegisterNumber(unsigned RegNo) const override { 995 if (RegNo == 0) return 3; 996 if (RegNo == 1) return 4; 997 return -1; 998 } 999 1000 bool hasSjLjLowering() const override { 1001 return true; 1002 } 1003 1004 bool useFloat128ManglingForLongDouble() const override { 1005 return LongDoubleWidth == 128 && 1006 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1007 getTriple().isOSBinFormatELF(); 1008 } 1009 }; 1010 1011 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1012 #define BUILTIN(ID, TYPE, ATTRS) \ 1013 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1014 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1015 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1016 #include "clang/Basic/BuiltinsPPC.def" 1017 }; 1018 1019 /// handleTargetFeatures - Perform initialization based on the user 1020 /// configured set of features. 1021 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1022 DiagnosticsEngine &Diags) { 1023 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 1024 // Ignore disabled features. 1025 if (Features[i][0] == '-') 1026 continue; 1027 1028 StringRef Feature = StringRef(Features[i]).substr(1); 1029 1030 if (Feature == "vsx") { 1031 HasVSX = true; 1032 continue; 1033 } 1034 1035 if (Feature == "bpermd") { 1036 HasBPERMD = true; 1037 continue; 1038 } 1039 1040 if (Feature == "extdiv") { 1041 HasExtDiv = true; 1042 continue; 1043 } 1044 1045 if (Feature == "power8-vector") { 1046 HasP8Vector = true; 1047 continue; 1048 } 1049 1050 if (Feature == "crypto") { 1051 HasP8Crypto = true; 1052 continue; 1053 } 1054 1055 if (Feature == "direct-move") { 1056 HasDirectMove = true; 1057 continue; 1058 } 1059 1060 if (Feature == "qpx") { 1061 HasQPX = true; 1062 continue; 1063 } 1064 1065 if (Feature == "htm") { 1066 HasHTM = true; 1067 continue; 1068 } 1069 1070 // TODO: Finish this list and add an assert that we've handled them 1071 // all. 1072 } 1073 if (!HasVSX && (HasP8Vector || HasDirectMove)) { 1074 if (HasP8Vector) 1075 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" << 1076 "-mno-vsx"; 1077 else if (HasDirectMove) 1078 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" << 1079 "-mno-vsx"; 1080 return false; 1081 } 1082 1083 return true; 1084 } 1085 1086 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1087 /// #defines that are not tied to a specific subtarget. 1088 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1089 MacroBuilder &Builder) const { 1090 // Target identification. 1091 Builder.defineMacro("__ppc__"); 1092 Builder.defineMacro("__PPC__"); 1093 Builder.defineMacro("_ARCH_PPC"); 1094 Builder.defineMacro("__powerpc__"); 1095 Builder.defineMacro("__POWERPC__"); 1096 if (PointerWidth == 64) { 1097 Builder.defineMacro("_ARCH_PPC64"); 1098 Builder.defineMacro("__powerpc64__"); 1099 Builder.defineMacro("__ppc64__"); 1100 Builder.defineMacro("__PPC64__"); 1101 } 1102 1103 // Target properties. 1104 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1105 Builder.defineMacro("_LITTLE_ENDIAN"); 1106 } else { 1107 if (getTriple().getOS() != llvm::Triple::NetBSD && 1108 getTriple().getOS() != llvm::Triple::OpenBSD) 1109 Builder.defineMacro("_BIG_ENDIAN"); 1110 } 1111 1112 // ABI options. 1113 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1114 Builder.defineMacro("_CALL_ELF", "1"); 1115 if (ABI == "elfv2") 1116 Builder.defineMacro("_CALL_ELF", "2"); 1117 1118 // Subtarget options. 1119 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1120 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1121 1122 // FIXME: Should be controlled by command line option. 1123 if (LongDoubleWidth == 128) 1124 Builder.defineMacro("__LONG_DOUBLE_128__"); 1125 1126 if (Opts.AltiVec) { 1127 Builder.defineMacro("__VEC__", "10206"); 1128 Builder.defineMacro("__ALTIVEC__"); 1129 } 1130 1131 // CPU identification. 1132 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1133 .Case("440", ArchDefineName) 1134 .Case("450", ArchDefineName | ArchDefine440) 1135 .Case("601", ArchDefineName) 1136 .Case("602", ArchDefineName | ArchDefinePpcgr) 1137 .Case("603", ArchDefineName | ArchDefinePpcgr) 1138 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1139 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1140 .Case("604", ArchDefineName | ArchDefinePpcgr) 1141 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1142 .Case("620", ArchDefineName | ArchDefinePpcgr) 1143 .Case("630", ArchDefineName | ArchDefinePpcgr) 1144 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1145 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1146 .Case("750", ArchDefineName | ArchDefinePpcgr) 1147 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1148 | ArchDefinePpcsq) 1149 .Case("a2", ArchDefineA2) 1150 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1151 .Case("pwr3", ArchDefinePpcgr) 1152 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1153 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1154 | ArchDefinePpcsq) 1155 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1156 | ArchDefinePpcgr | ArchDefinePpcsq) 1157 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1158 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1159 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1160 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1161 | ArchDefinePpcsq) 1162 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1163 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1164 | ArchDefinePpcgr | ArchDefinePpcsq) 1165 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1166 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1167 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1168 .Case("power3", ArchDefinePpcgr) 1169 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1170 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1171 | ArchDefinePpcsq) 1172 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1173 | ArchDefinePpcgr | ArchDefinePpcsq) 1174 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1175 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1176 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1177 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1178 | ArchDefinePpcsq) 1179 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1180 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1181 | ArchDefinePpcgr | ArchDefinePpcsq) 1182 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1183 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1184 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1185 .Default(ArchDefineNone); 1186 1187 if (defs & ArchDefineName) 1188 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1189 if (defs & ArchDefinePpcgr) 1190 Builder.defineMacro("_ARCH_PPCGR"); 1191 if (defs & ArchDefinePpcsq) 1192 Builder.defineMacro("_ARCH_PPCSQ"); 1193 if (defs & ArchDefine440) 1194 Builder.defineMacro("_ARCH_440"); 1195 if (defs & ArchDefine603) 1196 Builder.defineMacro("_ARCH_603"); 1197 if (defs & ArchDefine604) 1198 Builder.defineMacro("_ARCH_604"); 1199 if (defs & ArchDefinePwr4) 1200 Builder.defineMacro("_ARCH_PWR4"); 1201 if (defs & ArchDefinePwr5) 1202 Builder.defineMacro("_ARCH_PWR5"); 1203 if (defs & ArchDefinePwr5x) 1204 Builder.defineMacro("_ARCH_PWR5X"); 1205 if (defs & ArchDefinePwr6) 1206 Builder.defineMacro("_ARCH_PWR6"); 1207 if (defs & ArchDefinePwr6x) 1208 Builder.defineMacro("_ARCH_PWR6X"); 1209 if (defs & ArchDefinePwr7) 1210 Builder.defineMacro("_ARCH_PWR7"); 1211 if (defs & ArchDefinePwr8) 1212 Builder.defineMacro("_ARCH_PWR8"); 1213 if (defs & ArchDefineA2) 1214 Builder.defineMacro("_ARCH_A2"); 1215 if (defs & ArchDefineA2q) { 1216 Builder.defineMacro("_ARCH_A2Q"); 1217 Builder.defineMacro("_ARCH_QP"); 1218 } 1219 1220 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1221 Builder.defineMacro("__bg__"); 1222 Builder.defineMacro("__THW_BLUEGENE__"); 1223 Builder.defineMacro("__bgq__"); 1224 Builder.defineMacro("__TOS_BGQ__"); 1225 } 1226 1227 if (HasVSX) 1228 Builder.defineMacro("__VSX__"); 1229 if (HasP8Vector) 1230 Builder.defineMacro("__POWER8_VECTOR__"); 1231 if (HasP8Crypto) 1232 Builder.defineMacro("__CRYPTO__"); 1233 if (HasHTM) 1234 Builder.defineMacro("__HTM__"); 1235 if (getTriple().getArch() == llvm::Triple::ppc64le || 1236 (defs & ArchDefinePwr8) || (CPU == "pwr8")) { 1237 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1238 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1239 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1240 if (PointerWidth == 64) 1241 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1242 } 1243 1244 // FIXME: The following are not yet generated here by Clang, but are 1245 // generated by GCC: 1246 // 1247 // _SOFT_FLOAT_ 1248 // __RECIP_PRECISION__ 1249 // __APPLE_ALTIVEC__ 1250 // __RECIP__ 1251 // __RECIPF__ 1252 // __RSQRTE__ 1253 // __RSQRTEF__ 1254 // _SOFT_DOUBLE_ 1255 // __NO_LWSYNC__ 1256 // __HAVE_BSWAP__ 1257 // __LONGDOUBLE128 1258 // __CMODEL_MEDIUM__ 1259 // __CMODEL_LARGE__ 1260 // _CALL_SYSV 1261 // _CALL_DARWIN 1262 // __NO_FPRS__ 1263 } 1264 1265 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1266 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1267 .Case("7400", true) 1268 .Case("g4", true) 1269 .Case("7450", true) 1270 .Case("g4+", true) 1271 .Case("970", true) 1272 .Case("g5", true) 1273 .Case("pwr6", true) 1274 .Case("pwr7", true) 1275 .Case("pwr8", true) 1276 .Case("ppc64", true) 1277 .Case("ppc64le", true) 1278 .Default(false); 1279 1280 Features["qpx"] = (CPU == "a2q"); 1281 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1282 .Case("ppc64le", true) 1283 .Case("pwr8", true) 1284 .Default(false); 1285 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1286 .Case("ppc64le", true) 1287 .Case("pwr8", true) 1288 .Default(false); 1289 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1290 .Case("ppc64le", true) 1291 .Case("pwr8", true) 1292 .Case("pwr7", true) 1293 .Default(false); 1294 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1295 .Case("ppc64le", true) 1296 .Case("pwr8", true) 1297 .Case("pwr7", true) 1298 .Default(false); 1299 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1300 .Case("ppc64le", true) 1301 .Case("pwr8", true) 1302 .Default(false); 1303 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1304 .Case("ppc64le", true) 1305 .Case("pwr8", true) 1306 .Case("pwr7", true) 1307 .Default(false); 1308 } 1309 1310 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1311 return llvm::StringSwitch<bool>(Feature) 1312 .Case("powerpc", true) 1313 .Case("vsx", HasVSX) 1314 .Case("power8-vector", HasP8Vector) 1315 .Case("crypto", HasP8Crypto) 1316 .Case("direct-move", HasDirectMove) 1317 .Case("qpx", HasQPX) 1318 .Case("htm", HasHTM) 1319 .Case("bpermd", HasBPERMD) 1320 .Case("extdiv", HasExtDiv) 1321 .Default(false); 1322 } 1323 1324 /* There is no clear way for the target to know which of the features in the 1325 final feature vector came from defaults and which are actually specified by 1326 the user. To that end, we use the fact that this function is not called on 1327 default features - only user specified ones. By the first time this 1328 function is called, the default features are populated. 1329 We then keep track of the features that the user specified so that we 1330 can ensure we do not override a user's request (only defaults). 1331 For example: 1332 -mcpu=pwr8 -mno-vsx (should disable vsx and everything that depends on it) 1333 -mcpu=pwr8 -mdirect-move -mno-vsx (should actually be diagnosed) 1334 1335 NOTE: Do not call this from PPCTargetInfo::getDefaultFeatures 1336 */ 1337 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1338 StringRef Name, bool Enabled) const { 1339 static llvm::StringMap<bool> ExplicitFeatures; 1340 ExplicitFeatures[Name] = Enabled; 1341 1342 // At this point, -mno-vsx turns off the dependent features but we respect 1343 // the user's requests. 1344 if (!Enabled && Name == "vsx") { 1345 Features["direct-move"] = ExplicitFeatures["direct-move"]; 1346 Features["power8-vector"] = ExplicitFeatures["power8-vector"]; 1347 } 1348 if ((Enabled && Name == "power8-vector") || 1349 (Enabled && Name == "direct-move")) { 1350 if (ExplicitFeatures.find("vsx") == ExplicitFeatures.end()) { 1351 Features["vsx"] = true; 1352 } 1353 } 1354 Features[Name] = Enabled; 1355 } 1356 1357 const char * const PPCTargetInfo::GCCRegNames[] = { 1358 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1359 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1360 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1361 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1362 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1363 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1364 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1365 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1366 "mq", "lr", "ctr", "ap", 1367 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1368 "xer", 1369 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1370 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1371 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1372 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1373 "vrsave", "vscr", 1374 "spe_acc", "spefscr", 1375 "sfp" 1376 }; 1377 1378 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1379 unsigned &NumNames) const { 1380 Names = GCCRegNames; 1381 NumNames = llvm::array_lengthof(GCCRegNames); 1382 } 1383 1384 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1385 // While some of these aliases do map to different registers 1386 // they still share the same register name. 1387 { { "0" }, "r0" }, 1388 { { "1"}, "r1" }, 1389 { { "2" }, "r2" }, 1390 { { "3" }, "r3" }, 1391 { { "4" }, "r4" }, 1392 { { "5" }, "r5" }, 1393 { { "6" }, "r6" }, 1394 { { "7" }, "r7" }, 1395 { { "8" }, "r8" }, 1396 { { "9" }, "r9" }, 1397 { { "10" }, "r10" }, 1398 { { "11" }, "r11" }, 1399 { { "12" }, "r12" }, 1400 { { "13" }, "r13" }, 1401 { { "14" }, "r14" }, 1402 { { "15" }, "r15" }, 1403 { { "16" }, "r16" }, 1404 { { "17" }, "r17" }, 1405 { { "18" }, "r18" }, 1406 { { "19" }, "r19" }, 1407 { { "20" }, "r20" }, 1408 { { "21" }, "r21" }, 1409 { { "22" }, "r22" }, 1410 { { "23" }, "r23" }, 1411 { { "24" }, "r24" }, 1412 { { "25" }, "r25" }, 1413 { { "26" }, "r26" }, 1414 { { "27" }, "r27" }, 1415 { { "28" }, "r28" }, 1416 { { "29" }, "r29" }, 1417 { { "30" }, "r30" }, 1418 { { "31" }, "r31" }, 1419 { { "fr0" }, "f0" }, 1420 { { "fr1" }, "f1" }, 1421 { { "fr2" }, "f2" }, 1422 { { "fr3" }, "f3" }, 1423 { { "fr4" }, "f4" }, 1424 { { "fr5" }, "f5" }, 1425 { { "fr6" }, "f6" }, 1426 { { "fr7" }, "f7" }, 1427 { { "fr8" }, "f8" }, 1428 { { "fr9" }, "f9" }, 1429 { { "fr10" }, "f10" }, 1430 { { "fr11" }, "f11" }, 1431 { { "fr12" }, "f12" }, 1432 { { "fr13" }, "f13" }, 1433 { { "fr14" }, "f14" }, 1434 { { "fr15" }, "f15" }, 1435 { { "fr16" }, "f16" }, 1436 { { "fr17" }, "f17" }, 1437 { { "fr18" }, "f18" }, 1438 { { "fr19" }, "f19" }, 1439 { { "fr20" }, "f20" }, 1440 { { "fr21" }, "f21" }, 1441 { { "fr22" }, "f22" }, 1442 { { "fr23" }, "f23" }, 1443 { { "fr24" }, "f24" }, 1444 { { "fr25" }, "f25" }, 1445 { { "fr26" }, "f26" }, 1446 { { "fr27" }, "f27" }, 1447 { { "fr28" }, "f28" }, 1448 { { "fr29" }, "f29" }, 1449 { { "fr30" }, "f30" }, 1450 { { "fr31" }, "f31" }, 1451 { { "cc" }, "cr0" }, 1452 }; 1453 1454 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1455 unsigned &NumAliases) const { 1456 Aliases = GCCRegAliases; 1457 NumAliases = llvm::array_lengthof(GCCRegAliases); 1458 } 1459 1460 class PPC32TargetInfo : public PPCTargetInfo { 1461 public: 1462 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1463 DataLayoutString = "E-m:e-p:32:32-i64:64-n32"; 1464 1465 switch (getTriple().getOS()) { 1466 case llvm::Triple::Linux: 1467 case llvm::Triple::FreeBSD: 1468 case llvm::Triple::NetBSD: 1469 SizeType = UnsignedInt; 1470 PtrDiffType = SignedInt; 1471 IntPtrType = SignedInt; 1472 break; 1473 default: 1474 break; 1475 } 1476 1477 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1478 LongDoubleWidth = LongDoubleAlign = 64; 1479 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1480 } 1481 1482 // PPC32 supports atomics up to 4 bytes. 1483 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1484 } 1485 1486 BuiltinVaListKind getBuiltinVaListKind() const override { 1487 // This is the ELF definition, and is overridden by the Darwin sub-target 1488 return TargetInfo::PowerABIBuiltinVaList; 1489 } 1490 }; 1491 1492 // Note: ABI differences may eventually require us to have a separate 1493 // TargetInfo for little endian. 1494 class PPC64TargetInfo : public PPCTargetInfo { 1495 public: 1496 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1497 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1498 IntMaxType = SignedLong; 1499 Int64Type = SignedLong; 1500 1501 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1502 DataLayoutString = "e-m:e-i64:64-n32:64"; 1503 ABI = "elfv2"; 1504 } else { 1505 DataLayoutString = "E-m:e-i64:64-n32:64"; 1506 ABI = "elfv1"; 1507 } 1508 1509 switch (getTriple().getOS()) { 1510 case llvm::Triple::FreeBSD: 1511 LongDoubleWidth = LongDoubleAlign = 64; 1512 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1513 break; 1514 case llvm::Triple::NetBSD: 1515 IntMaxType = SignedLongLong; 1516 Int64Type = SignedLongLong; 1517 break; 1518 default: 1519 break; 1520 } 1521 1522 // PPC64 supports atomics up to 8 bytes. 1523 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1524 } 1525 BuiltinVaListKind getBuiltinVaListKind() const override { 1526 return TargetInfo::CharPtrBuiltinVaList; 1527 } 1528 // PPC64 Linux-specific ABI options. 1529 bool setABI(const std::string &Name) override { 1530 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1531 ABI = Name; 1532 return true; 1533 } 1534 return false; 1535 } 1536 }; 1537 1538 class DarwinPPC32TargetInfo : 1539 public DarwinTargetInfo<PPC32TargetInfo> { 1540 public: 1541 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1542 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1543 HasAlignMac68kSupport = true; 1544 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1545 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1546 LongLongAlign = 32; 1547 SuitableAlign = 128; 1548 DataLayoutString = "E-m:o-p:32:32-f64:32:64-n32"; 1549 } 1550 BuiltinVaListKind getBuiltinVaListKind() const override { 1551 return TargetInfo::CharPtrBuiltinVaList; 1552 } 1553 }; 1554 1555 class DarwinPPC64TargetInfo : 1556 public DarwinTargetInfo<PPC64TargetInfo> { 1557 public: 1558 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1559 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1560 HasAlignMac68kSupport = true; 1561 SuitableAlign = 128; 1562 DataLayoutString = "E-m:o-i64:64-n32:64"; 1563 } 1564 }; 1565 1566 static const unsigned NVPTXAddrSpaceMap[] = { 1567 1, // opencl_global 1568 3, // opencl_local 1569 4, // opencl_constant 1570 // FIXME: generic has to be added to the target 1571 0, // opencl_generic 1572 1, // cuda_device 1573 4, // cuda_constant 1574 3, // cuda_shared 1575 }; 1576 class NVPTXTargetInfo : public TargetInfo { 1577 static const char * const GCCRegNames[]; 1578 static const Builtin::Info BuiltinInfo[]; 1579 1580 // The GPU profiles supported by the NVPTX backend 1581 enum GPUKind { 1582 GK_NONE, 1583 GK_SM20, 1584 GK_SM21, 1585 GK_SM30, 1586 GK_SM35, 1587 GK_SM37, 1588 } GPU; 1589 1590 public: 1591 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1592 BigEndian = false; 1593 TLSSupported = false; 1594 LongWidth = LongAlign = 64; 1595 AddrSpaceMap = &NVPTXAddrSpaceMap; 1596 UseAddrSpaceMapMangling = true; 1597 // Define available target features 1598 // These must be defined in sorted order! 1599 NoAsmVariants = true; 1600 // Set the default GPU to sm20 1601 GPU = GK_SM20; 1602 } 1603 void getTargetDefines(const LangOptions &Opts, 1604 MacroBuilder &Builder) const override { 1605 Builder.defineMacro("__PTX__"); 1606 Builder.defineMacro("__NVPTX__"); 1607 if (Opts.CUDAIsDevice) { 1608 // Set __CUDA_ARCH__ for the GPU specified. 1609 std::string CUDAArchCode; 1610 switch (GPU) { 1611 case GK_SM20: 1612 CUDAArchCode = "200"; 1613 break; 1614 case GK_SM21: 1615 CUDAArchCode = "210"; 1616 break; 1617 case GK_SM30: 1618 CUDAArchCode = "300"; 1619 break; 1620 case GK_SM35: 1621 CUDAArchCode = "350"; 1622 break; 1623 case GK_SM37: 1624 CUDAArchCode = "370"; 1625 break; 1626 default: 1627 llvm_unreachable("Unhandled target CPU"); 1628 } 1629 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1630 } 1631 } 1632 void getTargetBuiltins(const Builtin::Info *&Records, 1633 unsigned &NumRecords) const override { 1634 Records = BuiltinInfo; 1635 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1636 } 1637 bool hasFeature(StringRef Feature) const override { 1638 return Feature == "ptx" || Feature == "nvptx"; 1639 } 1640 1641 void getGCCRegNames(const char * const *&Names, 1642 unsigned &NumNames) const override; 1643 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1644 unsigned &NumAliases) const override { 1645 // No aliases. 1646 Aliases = nullptr; 1647 NumAliases = 0; 1648 } 1649 bool 1650 validateAsmConstraint(const char *&Name, 1651 TargetInfo::ConstraintInfo &Info) const override { 1652 switch (*Name) { 1653 default: return false; 1654 case 'c': 1655 case 'h': 1656 case 'r': 1657 case 'l': 1658 case 'f': 1659 case 'd': 1660 Info.setAllowsRegister(); 1661 return true; 1662 } 1663 } 1664 const char *getClobbers() const override { 1665 // FIXME: Is this really right? 1666 return ""; 1667 } 1668 BuiltinVaListKind getBuiltinVaListKind() const override { 1669 // FIXME: implement 1670 return TargetInfo::CharPtrBuiltinVaList; 1671 } 1672 bool setCPU(const std::string &Name) override { 1673 GPU = llvm::StringSwitch<GPUKind>(Name) 1674 .Case("sm_20", GK_SM20) 1675 .Case("sm_21", GK_SM21) 1676 .Case("sm_30", GK_SM30) 1677 .Case("sm_35", GK_SM35) 1678 .Case("sm_37", GK_SM37) 1679 .Default(GK_NONE); 1680 1681 return GPU != GK_NONE; 1682 } 1683 }; 1684 1685 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1686 #define BUILTIN(ID, TYPE, ATTRS) \ 1687 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1688 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1689 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1690 #include "clang/Basic/BuiltinsNVPTX.def" 1691 }; 1692 1693 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1694 "r0" 1695 }; 1696 1697 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1698 unsigned &NumNames) const { 1699 Names = GCCRegNames; 1700 NumNames = llvm::array_lengthof(GCCRegNames); 1701 } 1702 1703 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1704 public: 1705 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1706 PointerWidth = PointerAlign = 32; 1707 SizeType = TargetInfo::UnsignedInt; 1708 PtrDiffType = TargetInfo::SignedInt; 1709 IntPtrType = TargetInfo::SignedInt; 1710 DataLayoutString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1711 } 1712 }; 1713 1714 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1715 public: 1716 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1717 PointerWidth = PointerAlign = 64; 1718 SizeType = TargetInfo::UnsignedLong; 1719 PtrDiffType = TargetInfo::SignedLong; 1720 IntPtrType = TargetInfo::SignedLong; 1721 DataLayoutString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1722 } 1723 }; 1724 1725 static const unsigned AMDGPUAddrSpaceMap[] = { 1726 1, // opencl_global 1727 3, // opencl_local 1728 2, // opencl_constant 1729 4, // opencl_generic 1730 1, // cuda_device 1731 2, // cuda_constant 1732 3 // cuda_shared 1733 }; 1734 1735 // If you edit the description strings, make sure you update 1736 // getPointerWidthV(). 1737 1738 static const char *DataLayoutStringR600 = 1739 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1740 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1741 1742 static const char *DataLayoutStringR600DoubleOps = 1743 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1744 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1745 1746 static const char *DataLayoutStringSI = 1747 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1748 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1749 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1750 1751 class AMDGPUTargetInfo : public TargetInfo { 1752 static const Builtin::Info BuiltinInfo[]; 1753 static const char * const GCCRegNames[]; 1754 1755 /// \brief The GPU profiles supported by the AMDGPU target. 1756 enum GPUKind { 1757 GK_NONE, 1758 GK_R600, 1759 GK_R600_DOUBLE_OPS, 1760 GK_R700, 1761 GK_R700_DOUBLE_OPS, 1762 GK_EVERGREEN, 1763 GK_EVERGREEN_DOUBLE_OPS, 1764 GK_NORTHERN_ISLANDS, 1765 GK_CAYMAN, 1766 GK_SOUTHERN_ISLANDS, 1767 GK_SEA_ISLANDS, 1768 GK_VOLCANIC_ISLANDS 1769 } GPU; 1770 1771 bool hasFP64:1; 1772 bool hasFMAF:1; 1773 bool hasLDEXPF:1; 1774 1775 public: 1776 AMDGPUTargetInfo(const llvm::Triple &Triple) 1777 : TargetInfo(Triple) { 1778 1779 if (Triple.getArch() == llvm::Triple::amdgcn) { 1780 DataLayoutString = DataLayoutStringSI; 1781 GPU = GK_SOUTHERN_ISLANDS; 1782 hasFP64 = true; 1783 hasFMAF = true; 1784 hasLDEXPF = true; 1785 } else { 1786 DataLayoutString = DataLayoutStringR600; 1787 GPU = GK_R600; 1788 hasFP64 = false; 1789 hasFMAF = false; 1790 hasLDEXPF = false; 1791 } 1792 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1793 UseAddrSpaceMapMangling = true; 1794 } 1795 1796 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1797 if (GPU <= GK_CAYMAN) 1798 return 32; 1799 1800 switch(AddrSpace) { 1801 default: 1802 return 64; 1803 case 0: 1804 case 3: 1805 case 5: 1806 return 32; 1807 } 1808 } 1809 1810 const char * getClobbers() const override { 1811 return ""; 1812 } 1813 1814 void getGCCRegNames(const char * const *&Names, 1815 unsigned &NumNames) const override; 1816 1817 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1818 unsigned &NumAliases) const override { 1819 Aliases = nullptr; 1820 NumAliases = 0; 1821 } 1822 1823 bool validateAsmConstraint(const char *&Name, 1824 TargetInfo::ConstraintInfo &info) const override { 1825 return true; 1826 } 1827 1828 void getTargetBuiltins(const Builtin::Info *&Records, 1829 unsigned &NumRecords) const override { 1830 Records = BuiltinInfo; 1831 NumRecords = clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin; 1832 } 1833 1834 void getTargetDefines(const LangOptions &Opts, 1835 MacroBuilder &Builder) const override { 1836 Builder.defineMacro("__R600__"); 1837 if (hasFMAF) 1838 Builder.defineMacro("__HAS_FMAF__"); 1839 if (hasLDEXPF) 1840 Builder.defineMacro("__HAS_LDEXPF__"); 1841 if (hasFP64 && Opts.OpenCL) 1842 Builder.defineMacro("cl_khr_fp64"); 1843 if (Opts.OpenCL) { 1844 if (GPU >= GK_NORTHERN_ISLANDS) { 1845 Builder.defineMacro("cl_khr_byte_addressable_store"); 1846 Builder.defineMacro("cl_khr_global_int32_base_atomics"); 1847 Builder.defineMacro("cl_khr_global_int32_extended_atomics"); 1848 Builder.defineMacro("cl_khr_local_int32_base_atomics"); 1849 Builder.defineMacro("cl_khr_local_int32_extended_atomics"); 1850 } 1851 } 1852 } 1853 1854 BuiltinVaListKind getBuiltinVaListKind() const override { 1855 return TargetInfo::CharPtrBuiltinVaList; 1856 } 1857 1858 bool setCPU(const std::string &Name) override { 1859 GPU = llvm::StringSwitch<GPUKind>(Name) 1860 .Case("r600" , GK_R600) 1861 .Case("rv610", GK_R600) 1862 .Case("rv620", GK_R600) 1863 .Case("rv630", GK_R600) 1864 .Case("rv635", GK_R600) 1865 .Case("rs780", GK_R600) 1866 .Case("rs880", GK_R600) 1867 .Case("rv670", GK_R600_DOUBLE_OPS) 1868 .Case("rv710", GK_R700) 1869 .Case("rv730", GK_R700) 1870 .Case("rv740", GK_R700_DOUBLE_OPS) 1871 .Case("rv770", GK_R700_DOUBLE_OPS) 1872 .Case("palm", GK_EVERGREEN) 1873 .Case("cedar", GK_EVERGREEN) 1874 .Case("sumo", GK_EVERGREEN) 1875 .Case("sumo2", GK_EVERGREEN) 1876 .Case("redwood", GK_EVERGREEN) 1877 .Case("juniper", GK_EVERGREEN) 1878 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1879 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1880 .Case("barts", GK_NORTHERN_ISLANDS) 1881 .Case("turks", GK_NORTHERN_ISLANDS) 1882 .Case("caicos", GK_NORTHERN_ISLANDS) 1883 .Case("cayman", GK_CAYMAN) 1884 .Case("aruba", GK_CAYMAN) 1885 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1886 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1887 .Case("verde", GK_SOUTHERN_ISLANDS) 1888 .Case("oland", GK_SOUTHERN_ISLANDS) 1889 .Case("hainan", GK_SOUTHERN_ISLANDS) 1890 .Case("bonaire", GK_SEA_ISLANDS) 1891 .Case("kabini", GK_SEA_ISLANDS) 1892 .Case("kaveri", GK_SEA_ISLANDS) 1893 .Case("hawaii", GK_SEA_ISLANDS) 1894 .Case("mullins", GK_SEA_ISLANDS) 1895 .Case("tonga", GK_VOLCANIC_ISLANDS) 1896 .Case("iceland", GK_VOLCANIC_ISLANDS) 1897 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1898 .Default(GK_NONE); 1899 1900 if (GPU == GK_NONE) { 1901 return false; 1902 } 1903 1904 // Set the correct data layout 1905 switch (GPU) { 1906 case GK_NONE: 1907 case GK_R600: 1908 case GK_R700: 1909 case GK_EVERGREEN: 1910 case GK_NORTHERN_ISLANDS: 1911 DataLayoutString = DataLayoutStringR600; 1912 hasFP64 = false; 1913 hasFMAF = false; 1914 hasLDEXPF = false; 1915 break; 1916 case GK_R600_DOUBLE_OPS: 1917 case GK_R700_DOUBLE_OPS: 1918 case GK_EVERGREEN_DOUBLE_OPS: 1919 case GK_CAYMAN: 1920 DataLayoutString = DataLayoutStringR600DoubleOps; 1921 hasFP64 = true; 1922 hasFMAF = true; 1923 hasLDEXPF = false; 1924 break; 1925 case GK_SOUTHERN_ISLANDS: 1926 case GK_SEA_ISLANDS: 1927 case GK_VOLCANIC_ISLANDS: 1928 DataLayoutString = DataLayoutStringSI; 1929 hasFP64 = true; 1930 hasFMAF = true; 1931 hasLDEXPF = true; 1932 break; 1933 } 1934 1935 return true; 1936 } 1937 }; 1938 1939 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1940 #define BUILTIN(ID, TYPE, ATTRS) \ 1941 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1942 #include "clang/Basic/BuiltinsAMDGPU.def" 1943 }; 1944 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1945 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1946 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1947 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1948 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1949 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1950 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1951 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1952 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1953 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1954 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1955 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1956 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1957 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1958 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1959 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1960 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1961 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1962 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1963 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1964 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 1965 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 1966 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 1967 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 1968 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 1969 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 1970 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 1971 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 1972 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 1973 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 1974 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 1975 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 1976 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 1977 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 1978 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 1979 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 1980 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 1981 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 1982 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 1983 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 1984 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 1985 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 1986 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 1987 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 1988 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 1989 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 1990 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 1991 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 1992 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127" 1993 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi", 1994 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi" 1995 }; 1996 1997 void AMDGPUTargetInfo::getGCCRegNames(const char * const *&Names, 1998 unsigned &NumNames) const { 1999 Names = GCCRegNames; 2000 NumNames = llvm::array_lengthof(GCCRegNames); 2001 } 2002 2003 // Namespace for x86 abstract base class 2004 const Builtin::Info BuiltinInfo[] = { 2005 #define BUILTIN(ID, TYPE, ATTRS) \ 2006 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2007 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2008 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2009 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2010 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2011 #include "clang/Basic/BuiltinsX86.def" 2012 }; 2013 2014 static const char* const GCCRegNames[] = { 2015 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2016 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2017 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2018 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2019 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2020 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2021 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2022 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2023 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2024 }; 2025 2026 const TargetInfo::AddlRegName AddlRegNames[] = { 2027 { { "al", "ah", "eax", "rax" }, 0 }, 2028 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2029 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2030 { { "dl", "dh", "edx", "rdx" }, 1 }, 2031 { { "esi", "rsi" }, 4 }, 2032 { { "edi", "rdi" }, 5 }, 2033 { { "esp", "rsp" }, 7 }, 2034 { { "ebp", "rbp" }, 6 }, 2035 }; 2036 2037 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2038 // most of the implementation can be shared. 2039 class X86TargetInfo : public TargetInfo { 2040 enum X86SSEEnum { 2041 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2042 } SSELevel; 2043 enum MMX3DNowEnum { 2044 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2045 } MMX3DNowLevel; 2046 enum XOPEnum { 2047 NoXOP, 2048 SSE4A, 2049 FMA4, 2050 XOP 2051 } XOPLevel; 2052 2053 bool HasAES; 2054 bool HasPCLMUL; 2055 bool HasLZCNT; 2056 bool HasRDRND; 2057 bool HasFSGSBASE; 2058 bool HasBMI; 2059 bool HasBMI2; 2060 bool HasPOPCNT; 2061 bool HasRTM; 2062 bool HasPRFCHW; 2063 bool HasRDSEED; 2064 bool HasADX; 2065 bool HasTBM; 2066 bool HasFMA; 2067 bool HasF16C; 2068 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW, 2069 HasAVX512VL; 2070 bool HasSHA; 2071 bool HasCX16; 2072 2073 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2074 /// 2075 /// Each enumeration represents a particular CPU supported by Clang. These 2076 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2077 enum CPUKind { 2078 CK_Generic, 2079 2080 /// \name i386 2081 /// i386-generation processors. 2082 //@{ 2083 CK_i386, 2084 //@} 2085 2086 /// \name i486 2087 /// i486-generation processors. 2088 //@{ 2089 CK_i486, 2090 CK_WinChipC6, 2091 CK_WinChip2, 2092 CK_C3, 2093 //@} 2094 2095 /// \name i586 2096 /// i586-generation processors, P5 microarchitecture based. 2097 //@{ 2098 CK_i586, 2099 CK_Pentium, 2100 CK_PentiumMMX, 2101 //@} 2102 2103 /// \name i686 2104 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2105 //@{ 2106 CK_i686, 2107 CK_PentiumPro, 2108 CK_Pentium2, 2109 CK_Pentium3, 2110 CK_Pentium3M, 2111 CK_PentiumM, 2112 CK_C3_2, 2113 2114 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2115 /// Clang however has some logic to suport this. 2116 // FIXME: Warn, deprecate, and potentially remove this. 2117 CK_Yonah, 2118 //@} 2119 2120 /// \name Netburst 2121 /// Netburst microarchitecture based processors. 2122 //@{ 2123 CK_Pentium4, 2124 CK_Pentium4M, 2125 CK_Prescott, 2126 CK_Nocona, 2127 //@} 2128 2129 /// \name Core 2130 /// Core microarchitecture based processors. 2131 //@{ 2132 CK_Core2, 2133 2134 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2135 /// codename which GCC no longer accepts as an option to -march, but Clang 2136 /// has some logic for recognizing it. 2137 // FIXME: Warn, deprecate, and potentially remove this. 2138 CK_Penryn, 2139 //@} 2140 2141 /// \name Atom 2142 /// Atom processors 2143 //@{ 2144 CK_Bonnell, 2145 CK_Silvermont, 2146 //@} 2147 2148 /// \name Nehalem 2149 /// Nehalem microarchitecture based processors. 2150 CK_Nehalem, 2151 2152 /// \name Westmere 2153 /// Westmere microarchitecture based processors. 2154 CK_Westmere, 2155 2156 /// \name Sandy Bridge 2157 /// Sandy Bridge microarchitecture based processors. 2158 CK_SandyBridge, 2159 2160 /// \name Ivy Bridge 2161 /// Ivy Bridge microarchitecture based processors. 2162 CK_IvyBridge, 2163 2164 /// \name Haswell 2165 /// Haswell microarchitecture based processors. 2166 CK_Haswell, 2167 2168 /// \name Broadwell 2169 /// Broadwell microarchitecture based processors. 2170 CK_Broadwell, 2171 2172 /// \name Skylake 2173 /// Skylake microarchitecture based processors. 2174 CK_Skylake, 2175 2176 /// \name Knights Landing 2177 /// Knights Landing processor. 2178 CK_KNL, 2179 2180 /// \name K6 2181 /// K6 architecture processors. 2182 //@{ 2183 CK_K6, 2184 CK_K6_2, 2185 CK_K6_3, 2186 //@} 2187 2188 /// \name K7 2189 /// K7 architecture processors. 2190 //@{ 2191 CK_Athlon, 2192 CK_AthlonThunderbird, 2193 CK_Athlon4, 2194 CK_AthlonXP, 2195 CK_AthlonMP, 2196 //@} 2197 2198 /// \name K8 2199 /// K8 architecture processors. 2200 //@{ 2201 CK_Athlon64, 2202 CK_Athlon64SSE3, 2203 CK_AthlonFX, 2204 CK_K8, 2205 CK_K8SSE3, 2206 CK_Opteron, 2207 CK_OpteronSSE3, 2208 CK_AMDFAM10, 2209 //@} 2210 2211 /// \name Bobcat 2212 /// Bobcat architecture processors. 2213 //@{ 2214 CK_BTVER1, 2215 CK_BTVER2, 2216 //@} 2217 2218 /// \name Bulldozer 2219 /// Bulldozer architecture processors. 2220 //@{ 2221 CK_BDVER1, 2222 CK_BDVER2, 2223 CK_BDVER3, 2224 CK_BDVER4, 2225 //@} 2226 2227 /// This specification is deprecated and will be removed in the future. 2228 /// Users should prefer \see CK_K8. 2229 // FIXME: Warn on this when the CPU is set to it. 2230 //@{ 2231 CK_x86_64, 2232 //@} 2233 2234 /// \name Geode 2235 /// Geode processors. 2236 //@{ 2237 CK_Geode 2238 //@} 2239 } CPU; 2240 2241 enum FPMathKind { 2242 FP_Default, 2243 FP_SSE, 2244 FP_387 2245 } FPMath; 2246 2247 public: 2248 X86TargetInfo(const llvm::Triple &Triple) 2249 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 2250 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 2251 HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false), 2252 HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false), 2253 HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false), 2254 HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false), 2255 HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false), 2256 HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) { 2257 BigEndian = false; 2258 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2259 } 2260 unsigned getFloatEvalMethod() const override { 2261 // X87 evaluates with 80 bits "long double" precision. 2262 return SSELevel == NoSSE ? 2 : 0; 2263 } 2264 void getTargetBuiltins(const Builtin::Info *&Records, 2265 unsigned &NumRecords) const override { 2266 Records = BuiltinInfo; 2267 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 2268 } 2269 void getGCCRegNames(const char * const *&Names, 2270 unsigned &NumNames) const override { 2271 Names = GCCRegNames; 2272 NumNames = llvm::array_lengthof(GCCRegNames); 2273 } 2274 void getGCCRegAliases(const GCCRegAlias *&Aliases, 2275 unsigned &NumAliases) const override { 2276 Aliases = nullptr; 2277 NumAliases = 0; 2278 } 2279 void getGCCAddlRegNames(const AddlRegName *&Names, 2280 unsigned &NumNames) const override { 2281 Names = AddlRegNames; 2282 NumNames = llvm::array_lengthof(AddlRegNames); 2283 } 2284 bool validateCpuSupports(StringRef Name) const override; 2285 bool validateAsmConstraint(const char *&Name, 2286 TargetInfo::ConstraintInfo &info) const override; 2287 2288 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2289 2290 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2291 2292 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2293 2294 std::string convertConstraint(const char *&Constraint) const override; 2295 const char *getClobbers() const override { 2296 return "~{dirflag},~{fpsr},~{flags}"; 2297 } 2298 void getTargetDefines(const LangOptions &Opts, 2299 MacroBuilder &Builder) const override; 2300 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2301 bool Enabled); 2302 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2303 bool Enabled); 2304 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2305 bool Enabled); 2306 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2307 StringRef Name, bool Enabled) const override { 2308 setFeatureEnabledImpl(Features, Name, Enabled); 2309 } 2310 // This exists purely to cut down on the number of virtual calls in 2311 // getDefaultFeatures which calls this repeatedly. 2312 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2313 StringRef Name, bool Enabled); 2314 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 2315 bool hasFeature(StringRef Feature) const override; 2316 bool handleTargetFeatures(std::vector<std::string> &Features, 2317 DiagnosticsEngine &Diags) override; 2318 StringRef getABI() const override { 2319 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2320 return "avx512"; 2321 else if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2322 return "avx"; 2323 else if (getTriple().getArch() == llvm::Triple::x86 && 2324 MMX3DNowLevel == NoMMX3DNow) 2325 return "no-mmx"; 2326 return ""; 2327 } 2328 bool setCPU(const std::string &Name) override { 2329 CPU = llvm::StringSwitch<CPUKind>(Name) 2330 .Case("i386", CK_i386) 2331 .Case("i486", CK_i486) 2332 .Case("winchip-c6", CK_WinChipC6) 2333 .Case("winchip2", CK_WinChip2) 2334 .Case("c3", CK_C3) 2335 .Case("i586", CK_i586) 2336 .Case("pentium", CK_Pentium) 2337 .Case("pentium-mmx", CK_PentiumMMX) 2338 .Case("i686", CK_i686) 2339 .Case("pentiumpro", CK_PentiumPro) 2340 .Case("pentium2", CK_Pentium2) 2341 .Case("pentium3", CK_Pentium3) 2342 .Case("pentium3m", CK_Pentium3M) 2343 .Case("pentium-m", CK_PentiumM) 2344 .Case("c3-2", CK_C3_2) 2345 .Case("yonah", CK_Yonah) 2346 .Case("pentium4", CK_Pentium4) 2347 .Case("pentium4m", CK_Pentium4M) 2348 .Case("prescott", CK_Prescott) 2349 .Case("nocona", CK_Nocona) 2350 .Case("core2", CK_Core2) 2351 .Case("penryn", CK_Penryn) 2352 .Case("bonnell", CK_Bonnell) 2353 .Case("atom", CK_Bonnell) // Legacy name. 2354 .Case("silvermont", CK_Silvermont) 2355 .Case("slm", CK_Silvermont) // Legacy name. 2356 .Case("nehalem", CK_Nehalem) 2357 .Case("corei7", CK_Nehalem) // Legacy name. 2358 .Case("westmere", CK_Westmere) 2359 .Case("sandybridge", CK_SandyBridge) 2360 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2361 .Case("ivybridge", CK_IvyBridge) 2362 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2363 .Case("haswell", CK_Haswell) 2364 .Case("core-avx2", CK_Haswell) // Legacy name. 2365 .Case("broadwell", CK_Broadwell) 2366 .Case("skylake", CK_Skylake) 2367 .Case("skx", CK_Skylake) // Legacy name. 2368 .Case("knl", CK_KNL) 2369 .Case("k6", CK_K6) 2370 .Case("k6-2", CK_K6_2) 2371 .Case("k6-3", CK_K6_3) 2372 .Case("athlon", CK_Athlon) 2373 .Case("athlon-tbird", CK_AthlonThunderbird) 2374 .Case("athlon-4", CK_Athlon4) 2375 .Case("athlon-xp", CK_AthlonXP) 2376 .Case("athlon-mp", CK_AthlonMP) 2377 .Case("athlon64", CK_Athlon64) 2378 .Case("athlon64-sse3", CK_Athlon64SSE3) 2379 .Case("athlon-fx", CK_AthlonFX) 2380 .Case("k8", CK_K8) 2381 .Case("k8-sse3", CK_K8SSE3) 2382 .Case("opteron", CK_Opteron) 2383 .Case("opteron-sse3", CK_OpteronSSE3) 2384 .Case("barcelona", CK_AMDFAM10) 2385 .Case("amdfam10", CK_AMDFAM10) 2386 .Case("btver1", CK_BTVER1) 2387 .Case("btver2", CK_BTVER2) 2388 .Case("bdver1", CK_BDVER1) 2389 .Case("bdver2", CK_BDVER2) 2390 .Case("bdver3", CK_BDVER3) 2391 .Case("bdver4", CK_BDVER4) 2392 .Case("x86-64", CK_x86_64) 2393 .Case("geode", CK_Geode) 2394 .Default(CK_Generic); 2395 2396 // Perform any per-CPU checks necessary to determine if this CPU is 2397 // acceptable. 2398 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2399 // invalid without explaining *why*. 2400 switch (CPU) { 2401 case CK_Generic: 2402 // No processor selected! 2403 return false; 2404 2405 case CK_i386: 2406 case CK_i486: 2407 case CK_WinChipC6: 2408 case CK_WinChip2: 2409 case CK_C3: 2410 case CK_i586: 2411 case CK_Pentium: 2412 case CK_PentiumMMX: 2413 case CK_i686: 2414 case CK_PentiumPro: 2415 case CK_Pentium2: 2416 case CK_Pentium3: 2417 case CK_Pentium3M: 2418 case CK_PentiumM: 2419 case CK_Yonah: 2420 case CK_C3_2: 2421 case CK_Pentium4: 2422 case CK_Pentium4M: 2423 case CK_Prescott: 2424 case CK_K6: 2425 case CK_K6_2: 2426 case CK_K6_3: 2427 case CK_Athlon: 2428 case CK_AthlonThunderbird: 2429 case CK_Athlon4: 2430 case CK_AthlonXP: 2431 case CK_AthlonMP: 2432 case CK_Geode: 2433 // Only accept certain architectures when compiling in 32-bit mode. 2434 if (getTriple().getArch() != llvm::Triple::x86) 2435 return false; 2436 2437 // Fallthrough 2438 case CK_Nocona: 2439 case CK_Core2: 2440 case CK_Penryn: 2441 case CK_Bonnell: 2442 case CK_Silvermont: 2443 case CK_Nehalem: 2444 case CK_Westmere: 2445 case CK_SandyBridge: 2446 case CK_IvyBridge: 2447 case CK_Haswell: 2448 case CK_Broadwell: 2449 case CK_Skylake: 2450 case CK_KNL: 2451 case CK_Athlon64: 2452 case CK_Athlon64SSE3: 2453 case CK_AthlonFX: 2454 case CK_K8: 2455 case CK_K8SSE3: 2456 case CK_Opteron: 2457 case CK_OpteronSSE3: 2458 case CK_AMDFAM10: 2459 case CK_BTVER1: 2460 case CK_BTVER2: 2461 case CK_BDVER1: 2462 case CK_BDVER2: 2463 case CK_BDVER3: 2464 case CK_BDVER4: 2465 case CK_x86_64: 2466 return true; 2467 } 2468 llvm_unreachable("Unhandled CPU kind"); 2469 } 2470 2471 bool setFPMath(StringRef Name) override; 2472 2473 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2474 // We accept all non-ARM calling conventions 2475 return (CC == CC_X86ThisCall || 2476 CC == CC_X86FastCall || 2477 CC == CC_X86StdCall || 2478 CC == CC_X86VectorCall || 2479 CC == CC_C || 2480 CC == CC_X86Pascal || 2481 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2482 } 2483 2484 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2485 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2486 } 2487 2488 bool hasSjLjLowering() const override { 2489 return true; 2490 } 2491 }; 2492 2493 bool X86TargetInfo::setFPMath(StringRef Name) { 2494 if (Name == "387") { 2495 FPMath = FP_387; 2496 return true; 2497 } 2498 if (Name == "sse") { 2499 FPMath = FP_SSE; 2500 return true; 2501 } 2502 return false; 2503 } 2504 2505 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2506 // FIXME: This *really* should not be here. 2507 2508 // X86_64 always has SSE2. 2509 if (getTriple().getArch() == llvm::Triple::x86_64) 2510 setFeatureEnabledImpl(Features, "sse2", true); 2511 2512 switch (CPU) { 2513 case CK_Generic: 2514 case CK_i386: 2515 case CK_i486: 2516 case CK_i586: 2517 case CK_Pentium: 2518 case CK_i686: 2519 case CK_PentiumPro: 2520 break; 2521 case CK_PentiumMMX: 2522 case CK_Pentium2: 2523 case CK_K6: 2524 case CK_WinChipC6: 2525 setFeatureEnabledImpl(Features, "mmx", true); 2526 break; 2527 case CK_Pentium3: 2528 case CK_Pentium3M: 2529 case CK_C3_2: 2530 setFeatureEnabledImpl(Features, "sse", true); 2531 break; 2532 case CK_PentiumM: 2533 case CK_Pentium4: 2534 case CK_Pentium4M: 2535 case CK_x86_64: 2536 setFeatureEnabledImpl(Features, "sse2", true); 2537 break; 2538 case CK_Yonah: 2539 case CK_Prescott: 2540 case CK_Nocona: 2541 setFeatureEnabledImpl(Features, "sse3", true); 2542 setFeatureEnabledImpl(Features, "cx16", true); 2543 break; 2544 case CK_Core2: 2545 case CK_Bonnell: 2546 setFeatureEnabledImpl(Features, "ssse3", true); 2547 setFeatureEnabledImpl(Features, "cx16", true); 2548 break; 2549 case CK_Penryn: 2550 setFeatureEnabledImpl(Features, "sse4.1", true); 2551 setFeatureEnabledImpl(Features, "cx16", true); 2552 break; 2553 case CK_Skylake: 2554 setFeatureEnabledImpl(Features, "avx512f", true); 2555 setFeatureEnabledImpl(Features, "avx512cd", true); 2556 setFeatureEnabledImpl(Features, "avx512dq", true); 2557 setFeatureEnabledImpl(Features, "avx512bw", true); 2558 setFeatureEnabledImpl(Features, "avx512vl", true); 2559 // FALLTHROUGH 2560 case CK_Broadwell: 2561 setFeatureEnabledImpl(Features, "rdseed", true); 2562 setFeatureEnabledImpl(Features, "adx", true); 2563 // FALLTHROUGH 2564 case CK_Haswell: 2565 setFeatureEnabledImpl(Features, "avx2", true); 2566 setFeatureEnabledImpl(Features, "lzcnt", true); 2567 setFeatureEnabledImpl(Features, "bmi", true); 2568 setFeatureEnabledImpl(Features, "bmi2", true); 2569 setFeatureEnabledImpl(Features, "rtm", true); 2570 setFeatureEnabledImpl(Features, "fma", true); 2571 // FALLTHROUGH 2572 case CK_IvyBridge: 2573 setFeatureEnabledImpl(Features, "rdrnd", true); 2574 setFeatureEnabledImpl(Features, "f16c", true); 2575 setFeatureEnabledImpl(Features, "fsgsbase", true); 2576 // FALLTHROUGH 2577 case CK_SandyBridge: 2578 setFeatureEnabledImpl(Features, "avx", true); 2579 // FALLTHROUGH 2580 case CK_Westmere: 2581 case CK_Silvermont: 2582 setFeatureEnabledImpl(Features, "aes", true); 2583 setFeatureEnabledImpl(Features, "pclmul", true); 2584 // FALLTHROUGH 2585 case CK_Nehalem: 2586 setFeatureEnabledImpl(Features, "sse4.2", true); 2587 setFeatureEnabledImpl(Features, "cx16", true); 2588 break; 2589 case CK_KNL: 2590 setFeatureEnabledImpl(Features, "avx512f", true); 2591 setFeatureEnabledImpl(Features, "avx512cd", true); 2592 setFeatureEnabledImpl(Features, "avx512er", true); 2593 setFeatureEnabledImpl(Features, "avx512pf", true); 2594 setFeatureEnabledImpl(Features, "rdseed", true); 2595 setFeatureEnabledImpl(Features, "adx", true); 2596 setFeatureEnabledImpl(Features, "lzcnt", true); 2597 setFeatureEnabledImpl(Features, "bmi", true); 2598 setFeatureEnabledImpl(Features, "bmi2", true); 2599 setFeatureEnabledImpl(Features, "rtm", true); 2600 setFeatureEnabledImpl(Features, "fma", true); 2601 setFeatureEnabledImpl(Features, "rdrnd", true); 2602 setFeatureEnabledImpl(Features, "f16c", true); 2603 setFeatureEnabledImpl(Features, "fsgsbase", true); 2604 setFeatureEnabledImpl(Features, "aes", true); 2605 setFeatureEnabledImpl(Features, "pclmul", true); 2606 setFeatureEnabledImpl(Features, "cx16", true); 2607 break; 2608 case CK_K6_2: 2609 case CK_K6_3: 2610 case CK_WinChip2: 2611 case CK_C3: 2612 setFeatureEnabledImpl(Features, "3dnow", true); 2613 break; 2614 case CK_Athlon: 2615 case CK_AthlonThunderbird: 2616 case CK_Geode: 2617 setFeatureEnabledImpl(Features, "3dnowa", true); 2618 break; 2619 case CK_Athlon4: 2620 case CK_AthlonXP: 2621 case CK_AthlonMP: 2622 setFeatureEnabledImpl(Features, "sse", true); 2623 setFeatureEnabledImpl(Features, "3dnowa", true); 2624 break; 2625 case CK_K8: 2626 case CK_Opteron: 2627 case CK_Athlon64: 2628 case CK_AthlonFX: 2629 setFeatureEnabledImpl(Features, "sse2", true); 2630 setFeatureEnabledImpl(Features, "3dnowa", true); 2631 break; 2632 case CK_AMDFAM10: 2633 setFeatureEnabledImpl(Features, "sse4a", true); 2634 setFeatureEnabledImpl(Features, "lzcnt", true); 2635 setFeatureEnabledImpl(Features, "popcnt", true); 2636 // FALLTHROUGH 2637 case CK_K8SSE3: 2638 case CK_OpteronSSE3: 2639 case CK_Athlon64SSE3: 2640 setFeatureEnabledImpl(Features, "sse3", true); 2641 setFeatureEnabledImpl(Features, "3dnowa", true); 2642 break; 2643 case CK_BTVER2: 2644 setFeatureEnabledImpl(Features, "avx", true); 2645 setFeatureEnabledImpl(Features, "aes", true); 2646 setFeatureEnabledImpl(Features, "pclmul", true); 2647 setFeatureEnabledImpl(Features, "bmi", true); 2648 setFeatureEnabledImpl(Features, "f16c", true); 2649 // FALLTHROUGH 2650 case CK_BTVER1: 2651 setFeatureEnabledImpl(Features, "ssse3", true); 2652 setFeatureEnabledImpl(Features, "sse4a", true); 2653 setFeatureEnabledImpl(Features, "lzcnt", true); 2654 setFeatureEnabledImpl(Features, "popcnt", true); 2655 setFeatureEnabledImpl(Features, "prfchw", true); 2656 setFeatureEnabledImpl(Features, "cx16", true); 2657 break; 2658 case CK_BDVER4: 2659 setFeatureEnabledImpl(Features, "avx2", true); 2660 setFeatureEnabledImpl(Features, "bmi2", true); 2661 // FALLTHROUGH 2662 case CK_BDVER3: 2663 setFeatureEnabledImpl(Features, "fsgsbase", true); 2664 // FALLTHROUGH 2665 case CK_BDVER2: 2666 setFeatureEnabledImpl(Features, "bmi", true); 2667 setFeatureEnabledImpl(Features, "fma", true); 2668 setFeatureEnabledImpl(Features, "f16c", true); 2669 setFeatureEnabledImpl(Features, "tbm", true); 2670 // FALLTHROUGH 2671 case CK_BDVER1: 2672 // xop implies avx, sse4a and fma4. 2673 setFeatureEnabledImpl(Features, "xop", true); 2674 setFeatureEnabledImpl(Features, "lzcnt", true); 2675 setFeatureEnabledImpl(Features, "aes", true); 2676 setFeatureEnabledImpl(Features, "pclmul", true); 2677 setFeatureEnabledImpl(Features, "prfchw", true); 2678 setFeatureEnabledImpl(Features, "cx16", true); 2679 break; 2680 } 2681 } 2682 2683 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2684 X86SSEEnum Level, bool Enabled) { 2685 if (Enabled) { 2686 switch (Level) { 2687 case AVX512F: 2688 Features["avx512f"] = true; 2689 case AVX2: 2690 Features["avx2"] = true; 2691 case AVX: 2692 Features["avx"] = true; 2693 case SSE42: 2694 Features["sse4.2"] = true; 2695 case SSE41: 2696 Features["sse4.1"] = true; 2697 case SSSE3: 2698 Features["ssse3"] = true; 2699 case SSE3: 2700 Features["sse3"] = true; 2701 case SSE2: 2702 Features["sse2"] = true; 2703 case SSE1: 2704 Features["sse"] = true; 2705 case NoSSE: 2706 break; 2707 } 2708 return; 2709 } 2710 2711 switch (Level) { 2712 case NoSSE: 2713 case SSE1: 2714 Features["sse"] = false; 2715 case SSE2: 2716 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2717 Features["sha"] = false; 2718 case SSE3: 2719 Features["sse3"] = false; 2720 setXOPLevel(Features, NoXOP, false); 2721 case SSSE3: 2722 Features["ssse3"] = false; 2723 case SSE41: 2724 Features["sse4.1"] = false; 2725 case SSE42: 2726 Features["sse4.2"] = false; 2727 case AVX: 2728 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2729 setXOPLevel(Features, FMA4, false); 2730 case AVX2: 2731 Features["avx2"] = false; 2732 case AVX512F: 2733 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2734 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2735 Features["avx512vl"] = false; 2736 } 2737 } 2738 2739 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2740 MMX3DNowEnum Level, bool Enabled) { 2741 if (Enabled) { 2742 switch (Level) { 2743 case AMD3DNowAthlon: 2744 Features["3dnowa"] = true; 2745 case AMD3DNow: 2746 Features["3dnow"] = true; 2747 case MMX: 2748 Features["mmx"] = true; 2749 case NoMMX3DNow: 2750 break; 2751 } 2752 return; 2753 } 2754 2755 switch (Level) { 2756 case NoMMX3DNow: 2757 case MMX: 2758 Features["mmx"] = false; 2759 case AMD3DNow: 2760 Features["3dnow"] = false; 2761 case AMD3DNowAthlon: 2762 Features["3dnowa"] = false; 2763 } 2764 } 2765 2766 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2767 bool Enabled) { 2768 if (Enabled) { 2769 switch (Level) { 2770 case XOP: 2771 Features["xop"] = true; 2772 case FMA4: 2773 Features["fma4"] = true; 2774 setSSELevel(Features, AVX, true); 2775 case SSE4A: 2776 Features["sse4a"] = true; 2777 setSSELevel(Features, SSE3, true); 2778 case NoXOP: 2779 break; 2780 } 2781 return; 2782 } 2783 2784 switch (Level) { 2785 case NoXOP: 2786 case SSE4A: 2787 Features["sse4a"] = false; 2788 case FMA4: 2789 Features["fma4"] = false; 2790 case XOP: 2791 Features["xop"] = false; 2792 } 2793 } 2794 2795 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2796 StringRef Name, bool Enabled) { 2797 // This is a bit of a hack to deal with the sse4 target feature when used 2798 // as part of the target attribute. We handle sse4 correctly everywhere 2799 // else. See below for more information on how we handle the sse4 options. 2800 if (Name != "sse4") 2801 Features[Name] = Enabled; 2802 2803 if (Name == "mmx") { 2804 setMMXLevel(Features, MMX, Enabled); 2805 } else if (Name == "sse") { 2806 setSSELevel(Features, SSE1, Enabled); 2807 } else if (Name == "sse2") { 2808 setSSELevel(Features, SSE2, Enabled); 2809 } else if (Name == "sse3") { 2810 setSSELevel(Features, SSE3, Enabled); 2811 } else if (Name == "ssse3") { 2812 setSSELevel(Features, SSSE3, Enabled); 2813 } else if (Name == "sse4.2") { 2814 setSSELevel(Features, SSE42, Enabled); 2815 } else if (Name == "sse4.1") { 2816 setSSELevel(Features, SSE41, Enabled); 2817 } else if (Name == "3dnow") { 2818 setMMXLevel(Features, AMD3DNow, Enabled); 2819 } else if (Name == "3dnowa") { 2820 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2821 } else if (Name == "aes") { 2822 if (Enabled) 2823 setSSELevel(Features, SSE2, Enabled); 2824 } else if (Name == "pclmul") { 2825 if (Enabled) 2826 setSSELevel(Features, SSE2, Enabled); 2827 } else if (Name == "avx") { 2828 setSSELevel(Features, AVX, Enabled); 2829 } else if (Name == "avx2") { 2830 setSSELevel(Features, AVX2, Enabled); 2831 } else if (Name == "avx512f") { 2832 setSSELevel(Features, AVX512F, Enabled); 2833 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2834 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2835 if (Enabled) 2836 setSSELevel(Features, AVX512F, Enabled); 2837 } else if (Name == "fma") { 2838 if (Enabled) 2839 setSSELevel(Features, AVX, Enabled); 2840 } else if (Name == "fma4") { 2841 setXOPLevel(Features, FMA4, Enabled); 2842 } else if (Name == "xop") { 2843 setXOPLevel(Features, XOP, Enabled); 2844 } else if (Name == "sse4a") { 2845 setXOPLevel(Features, SSE4A, Enabled); 2846 } else if (Name == "f16c") { 2847 if (Enabled) 2848 setSSELevel(Features, AVX, Enabled); 2849 } else if (Name == "sha") { 2850 if (Enabled) 2851 setSSELevel(Features, SSE2, Enabled); 2852 } else if (Name == "sse4") { 2853 // We can get here via the __target__ attribute since that's not controlled 2854 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 2855 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 2856 // disabled. 2857 if (Enabled) 2858 setSSELevel(Features, SSE42, Enabled); 2859 else 2860 setSSELevel(Features, SSE41, Enabled); 2861 } 2862 } 2863 2864 /// handleTargetFeatures - Perform initialization based on the user 2865 /// configured set of features. 2866 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2867 DiagnosticsEngine &Diags) { 2868 // Remember the maximum enabled sselevel. 2869 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2870 // Ignore disabled features. 2871 if (Features[i][0] == '-') 2872 continue; 2873 2874 StringRef Feature = StringRef(Features[i]).substr(1); 2875 2876 if (Feature == "aes") { 2877 HasAES = true; 2878 continue; 2879 } 2880 2881 if (Feature == "pclmul") { 2882 HasPCLMUL = true; 2883 continue; 2884 } 2885 2886 if (Feature == "lzcnt") { 2887 HasLZCNT = true; 2888 continue; 2889 } 2890 2891 if (Feature == "rdrnd") { 2892 HasRDRND = true; 2893 continue; 2894 } 2895 2896 if (Feature == "fsgsbase") { 2897 HasFSGSBASE = true; 2898 continue; 2899 } 2900 2901 if (Feature == "bmi") { 2902 HasBMI = true; 2903 continue; 2904 } 2905 2906 if (Feature == "bmi2") { 2907 HasBMI2 = true; 2908 continue; 2909 } 2910 2911 if (Feature == "popcnt") { 2912 HasPOPCNT = true; 2913 continue; 2914 } 2915 2916 if (Feature == "rtm") { 2917 HasRTM = true; 2918 continue; 2919 } 2920 2921 if (Feature == "prfchw") { 2922 HasPRFCHW = true; 2923 continue; 2924 } 2925 2926 if (Feature == "rdseed") { 2927 HasRDSEED = true; 2928 continue; 2929 } 2930 2931 if (Feature == "adx") { 2932 HasADX = true; 2933 continue; 2934 } 2935 2936 if (Feature == "tbm") { 2937 HasTBM = true; 2938 continue; 2939 } 2940 2941 if (Feature == "fma") { 2942 HasFMA = true; 2943 continue; 2944 } 2945 2946 if (Feature == "f16c") { 2947 HasF16C = true; 2948 continue; 2949 } 2950 2951 if (Feature == "avx512cd") { 2952 HasAVX512CD = true; 2953 continue; 2954 } 2955 2956 if (Feature == "avx512er") { 2957 HasAVX512ER = true; 2958 continue; 2959 } 2960 2961 if (Feature == "avx512pf") { 2962 HasAVX512PF = true; 2963 continue; 2964 } 2965 2966 if (Feature == "avx512dq") { 2967 HasAVX512DQ = true; 2968 continue; 2969 } 2970 2971 if (Feature == "avx512bw") { 2972 HasAVX512BW = true; 2973 continue; 2974 } 2975 2976 if (Feature == "avx512vl") { 2977 HasAVX512VL = true; 2978 continue; 2979 } 2980 2981 if (Feature == "sha") { 2982 HasSHA = true; 2983 continue; 2984 } 2985 2986 if (Feature == "cx16") { 2987 HasCX16 = true; 2988 continue; 2989 } 2990 2991 assert(Features[i][0] == '+' && "Invalid target feature!"); 2992 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2993 .Case("avx512f", AVX512F) 2994 .Case("avx2", AVX2) 2995 .Case("avx", AVX) 2996 .Case("sse4.2", SSE42) 2997 .Case("sse4.1", SSE41) 2998 .Case("ssse3", SSSE3) 2999 .Case("sse3", SSE3) 3000 .Case("sse2", SSE2) 3001 .Case("sse", SSE1) 3002 .Default(NoSSE); 3003 SSELevel = std::max(SSELevel, Level); 3004 3005 MMX3DNowEnum ThreeDNowLevel = 3006 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3007 .Case("3dnowa", AMD3DNowAthlon) 3008 .Case("3dnow", AMD3DNow) 3009 .Case("mmx", MMX) 3010 .Default(NoMMX3DNow); 3011 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3012 3013 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3014 .Case("xop", XOP) 3015 .Case("fma4", FMA4) 3016 .Case("sse4a", SSE4A) 3017 .Default(NoXOP); 3018 XOPLevel = std::max(XOPLevel, XLevel); 3019 } 3020 3021 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3022 // Can't do this earlier because we need to be able to explicitly enable 3023 // popcnt and still disable sse4.2. 3024 if (!HasPOPCNT && SSELevel >= SSE42 && 3025 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 3026 HasPOPCNT = true; 3027 Features.push_back("+popcnt"); 3028 } 3029 3030 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3031 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 3032 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 3033 HasPRFCHW = true; 3034 Features.push_back("+prfchw"); 3035 } 3036 3037 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3038 // matches the selected sse level. 3039 if (FPMath == FP_SSE && SSELevel < SSE1) { 3040 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 3041 return false; 3042 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 3043 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 3044 return false; 3045 } 3046 3047 // Don't tell the backend if we're turning off mmx; it will end up disabling 3048 // SSE, which we don't want. 3049 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3050 // then enable MMX. 3051 std::vector<std::string>::iterator it; 3052 it = std::find(Features.begin(), Features.end(), "-mmx"); 3053 if (it != Features.end()) 3054 Features.erase(it); 3055 else if (SSELevel > NoSSE) 3056 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 3057 3058 SimdDefaultAlign = 3059 (getABI() == "avx512") ? 512 : (getABI() == "avx") ? 256 : 128; 3060 return true; 3061 } 3062 3063 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3064 /// definitions for this particular subtarget. 3065 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3066 MacroBuilder &Builder) const { 3067 // Target identification. 3068 if (getTriple().getArch() == llvm::Triple::x86_64) { 3069 Builder.defineMacro("__amd64__"); 3070 Builder.defineMacro("__amd64"); 3071 Builder.defineMacro("__x86_64"); 3072 Builder.defineMacro("__x86_64__"); 3073 if (getTriple().getArchName() == "x86_64h") { 3074 Builder.defineMacro("__x86_64h"); 3075 Builder.defineMacro("__x86_64h__"); 3076 } 3077 } else { 3078 DefineStd(Builder, "i386", Opts); 3079 } 3080 3081 // Subtarget options. 3082 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3083 // truly should be based on -mtune options. 3084 switch (CPU) { 3085 case CK_Generic: 3086 break; 3087 case CK_i386: 3088 // The rest are coming from the i386 define above. 3089 Builder.defineMacro("__tune_i386__"); 3090 break; 3091 case CK_i486: 3092 case CK_WinChipC6: 3093 case CK_WinChip2: 3094 case CK_C3: 3095 defineCPUMacros(Builder, "i486"); 3096 break; 3097 case CK_PentiumMMX: 3098 Builder.defineMacro("__pentium_mmx__"); 3099 Builder.defineMacro("__tune_pentium_mmx__"); 3100 // Fallthrough 3101 case CK_i586: 3102 case CK_Pentium: 3103 defineCPUMacros(Builder, "i586"); 3104 defineCPUMacros(Builder, "pentium"); 3105 break; 3106 case CK_Pentium3: 3107 case CK_Pentium3M: 3108 case CK_PentiumM: 3109 Builder.defineMacro("__tune_pentium3__"); 3110 // Fallthrough 3111 case CK_Pentium2: 3112 case CK_C3_2: 3113 Builder.defineMacro("__tune_pentium2__"); 3114 // Fallthrough 3115 case CK_PentiumPro: 3116 Builder.defineMacro("__tune_i686__"); 3117 Builder.defineMacro("__tune_pentiumpro__"); 3118 // Fallthrough 3119 case CK_i686: 3120 Builder.defineMacro("__i686"); 3121 Builder.defineMacro("__i686__"); 3122 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3123 Builder.defineMacro("__pentiumpro"); 3124 Builder.defineMacro("__pentiumpro__"); 3125 break; 3126 case CK_Pentium4: 3127 case CK_Pentium4M: 3128 defineCPUMacros(Builder, "pentium4"); 3129 break; 3130 case CK_Yonah: 3131 case CK_Prescott: 3132 case CK_Nocona: 3133 defineCPUMacros(Builder, "nocona"); 3134 break; 3135 case CK_Core2: 3136 case CK_Penryn: 3137 defineCPUMacros(Builder, "core2"); 3138 break; 3139 case CK_Bonnell: 3140 defineCPUMacros(Builder, "atom"); 3141 break; 3142 case CK_Silvermont: 3143 defineCPUMacros(Builder, "slm"); 3144 break; 3145 case CK_Nehalem: 3146 case CK_Westmere: 3147 case CK_SandyBridge: 3148 case CK_IvyBridge: 3149 case CK_Haswell: 3150 case CK_Broadwell: 3151 // FIXME: Historically, we defined this legacy name, it would be nice to 3152 // remove it at some point. We've never exposed fine-grained names for 3153 // recent primary x86 CPUs, and we should keep it that way. 3154 defineCPUMacros(Builder, "corei7"); 3155 break; 3156 case CK_Skylake: 3157 // FIXME: Historically, we defined this legacy name, it would be nice to 3158 // remove it at some point. This is the only fine-grained CPU macro in the 3159 // main intel CPU line, and it would be better to not have these and force 3160 // people to use ISA macros. 3161 defineCPUMacros(Builder, "skx"); 3162 break; 3163 case CK_KNL: 3164 defineCPUMacros(Builder, "knl"); 3165 break; 3166 case CK_K6_2: 3167 Builder.defineMacro("__k6_2__"); 3168 Builder.defineMacro("__tune_k6_2__"); 3169 // Fallthrough 3170 case CK_K6_3: 3171 if (CPU != CK_K6_2) { // In case of fallthrough 3172 // FIXME: GCC may be enabling these in cases where some other k6 3173 // architecture is specified but -m3dnow is explicitly provided. The 3174 // exact semantics need to be determined and emulated here. 3175 Builder.defineMacro("__k6_3__"); 3176 Builder.defineMacro("__tune_k6_3__"); 3177 } 3178 // Fallthrough 3179 case CK_K6: 3180 defineCPUMacros(Builder, "k6"); 3181 break; 3182 case CK_Athlon: 3183 case CK_AthlonThunderbird: 3184 case CK_Athlon4: 3185 case CK_AthlonXP: 3186 case CK_AthlonMP: 3187 defineCPUMacros(Builder, "athlon"); 3188 if (SSELevel != NoSSE) { 3189 Builder.defineMacro("__athlon_sse__"); 3190 Builder.defineMacro("__tune_athlon_sse__"); 3191 } 3192 break; 3193 case CK_K8: 3194 case CK_K8SSE3: 3195 case CK_x86_64: 3196 case CK_Opteron: 3197 case CK_OpteronSSE3: 3198 case CK_Athlon64: 3199 case CK_Athlon64SSE3: 3200 case CK_AthlonFX: 3201 defineCPUMacros(Builder, "k8"); 3202 break; 3203 case CK_AMDFAM10: 3204 defineCPUMacros(Builder, "amdfam10"); 3205 break; 3206 case CK_BTVER1: 3207 defineCPUMacros(Builder, "btver1"); 3208 break; 3209 case CK_BTVER2: 3210 defineCPUMacros(Builder, "btver2"); 3211 break; 3212 case CK_BDVER1: 3213 defineCPUMacros(Builder, "bdver1"); 3214 break; 3215 case CK_BDVER2: 3216 defineCPUMacros(Builder, "bdver2"); 3217 break; 3218 case CK_BDVER3: 3219 defineCPUMacros(Builder, "bdver3"); 3220 break; 3221 case CK_BDVER4: 3222 defineCPUMacros(Builder, "bdver4"); 3223 break; 3224 case CK_Geode: 3225 defineCPUMacros(Builder, "geode"); 3226 break; 3227 } 3228 3229 // Target properties. 3230 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3231 3232 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3233 // functions in glibc header files that use FP Stack inline asm which the 3234 // backend can't deal with (PR879). 3235 Builder.defineMacro("__NO_MATH_INLINES"); 3236 3237 if (HasAES) 3238 Builder.defineMacro("__AES__"); 3239 3240 if (HasPCLMUL) 3241 Builder.defineMacro("__PCLMUL__"); 3242 3243 if (HasLZCNT) 3244 Builder.defineMacro("__LZCNT__"); 3245 3246 if (HasRDRND) 3247 Builder.defineMacro("__RDRND__"); 3248 3249 if (HasFSGSBASE) 3250 Builder.defineMacro("__FSGSBASE__"); 3251 3252 if (HasBMI) 3253 Builder.defineMacro("__BMI__"); 3254 3255 if (HasBMI2) 3256 Builder.defineMacro("__BMI2__"); 3257 3258 if (HasPOPCNT) 3259 Builder.defineMacro("__POPCNT__"); 3260 3261 if (HasRTM) 3262 Builder.defineMacro("__RTM__"); 3263 3264 if (HasPRFCHW) 3265 Builder.defineMacro("__PRFCHW__"); 3266 3267 if (HasRDSEED) 3268 Builder.defineMacro("__RDSEED__"); 3269 3270 if (HasADX) 3271 Builder.defineMacro("__ADX__"); 3272 3273 if (HasTBM) 3274 Builder.defineMacro("__TBM__"); 3275 3276 switch (XOPLevel) { 3277 case XOP: 3278 Builder.defineMacro("__XOP__"); 3279 case FMA4: 3280 Builder.defineMacro("__FMA4__"); 3281 case SSE4A: 3282 Builder.defineMacro("__SSE4A__"); 3283 case NoXOP: 3284 break; 3285 } 3286 3287 if (HasFMA) 3288 Builder.defineMacro("__FMA__"); 3289 3290 if (HasF16C) 3291 Builder.defineMacro("__F16C__"); 3292 3293 if (HasAVX512CD) 3294 Builder.defineMacro("__AVX512CD__"); 3295 if (HasAVX512ER) 3296 Builder.defineMacro("__AVX512ER__"); 3297 if (HasAVX512PF) 3298 Builder.defineMacro("__AVX512PF__"); 3299 if (HasAVX512DQ) 3300 Builder.defineMacro("__AVX512DQ__"); 3301 if (HasAVX512BW) 3302 Builder.defineMacro("__AVX512BW__"); 3303 if (HasAVX512VL) 3304 Builder.defineMacro("__AVX512VL__"); 3305 3306 if (HasSHA) 3307 Builder.defineMacro("__SHA__"); 3308 3309 if (HasCX16) 3310 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3311 3312 // Each case falls through to the previous one here. 3313 switch (SSELevel) { 3314 case AVX512F: 3315 Builder.defineMacro("__AVX512F__"); 3316 case AVX2: 3317 Builder.defineMacro("__AVX2__"); 3318 case AVX: 3319 Builder.defineMacro("__AVX__"); 3320 case SSE42: 3321 Builder.defineMacro("__SSE4_2__"); 3322 case SSE41: 3323 Builder.defineMacro("__SSE4_1__"); 3324 case SSSE3: 3325 Builder.defineMacro("__SSSE3__"); 3326 case SSE3: 3327 Builder.defineMacro("__SSE3__"); 3328 case SSE2: 3329 Builder.defineMacro("__SSE2__"); 3330 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3331 case SSE1: 3332 Builder.defineMacro("__SSE__"); 3333 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3334 case NoSSE: 3335 break; 3336 } 3337 3338 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3339 switch (SSELevel) { 3340 case AVX512F: 3341 case AVX2: 3342 case AVX: 3343 case SSE42: 3344 case SSE41: 3345 case SSSE3: 3346 case SSE3: 3347 case SSE2: 3348 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3349 break; 3350 case SSE1: 3351 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3352 break; 3353 default: 3354 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3355 } 3356 } 3357 3358 // Each case falls through to the previous one here. 3359 switch (MMX3DNowLevel) { 3360 case AMD3DNowAthlon: 3361 Builder.defineMacro("__3dNOW_A__"); 3362 case AMD3DNow: 3363 Builder.defineMacro("__3dNOW__"); 3364 case MMX: 3365 Builder.defineMacro("__MMX__"); 3366 case NoMMX3DNow: 3367 break; 3368 } 3369 3370 if (CPU >= CK_i486) { 3371 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3372 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3373 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3374 } 3375 if (CPU >= CK_i586) 3376 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3377 } 3378 3379 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3380 return llvm::StringSwitch<bool>(Feature) 3381 .Case("aes", HasAES) 3382 .Case("avx", SSELevel >= AVX) 3383 .Case("avx2", SSELevel >= AVX2) 3384 .Case("avx512f", SSELevel >= AVX512F) 3385 .Case("avx512cd", HasAVX512CD) 3386 .Case("avx512er", HasAVX512ER) 3387 .Case("avx512pf", HasAVX512PF) 3388 .Case("avx512dq", HasAVX512DQ) 3389 .Case("avx512bw", HasAVX512BW) 3390 .Case("avx512vl", HasAVX512VL) 3391 .Case("bmi", HasBMI) 3392 .Case("bmi2", HasBMI2) 3393 .Case("cx16", HasCX16) 3394 .Case("f16c", HasF16C) 3395 .Case("fma", HasFMA) 3396 .Case("fma4", XOPLevel >= FMA4) 3397 .Case("fsgsbase", HasFSGSBASE) 3398 .Case("lzcnt", HasLZCNT) 3399 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3400 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3401 .Case("mmx", MMX3DNowLevel >= MMX) 3402 .Case("pclmul", HasPCLMUL) 3403 .Case("popcnt", HasPOPCNT) 3404 .Case("prfchw", HasPRFCHW) 3405 .Case("rdrnd", HasRDRND) 3406 .Case("rdseed", HasRDSEED) 3407 .Case("rtm", HasRTM) 3408 .Case("sha", HasSHA) 3409 .Case("sse", SSELevel >= SSE1) 3410 .Case("sse2", SSELevel >= SSE2) 3411 .Case("sse3", SSELevel >= SSE3) 3412 .Case("ssse3", SSELevel >= SSSE3) 3413 .Case("sse4.1", SSELevel >= SSE41) 3414 .Case("sse4.2", SSELevel >= SSE42) 3415 .Case("sse4a", XOPLevel >= SSE4A) 3416 .Case("tbm", HasTBM) 3417 .Case("x86", true) 3418 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3419 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3420 .Case("xop", XOPLevel >= XOP) 3421 .Default(false); 3422 } 3423 3424 // We can't use a generic validation scheme for the features accepted here 3425 // versus subtarget features accepted in the target attribute because the 3426 // bitfield structure that's initialized in the runtime only supports the 3427 // below currently rather than the full range of subtarget features. (See 3428 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3429 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3430 return llvm::StringSwitch<bool>(FeatureStr) 3431 .Case("cmov", true) 3432 .Case("mmx", true) 3433 .Case("popcnt", true) 3434 .Case("sse", true) 3435 .Case("sse2", true) 3436 .Case("sse3", true) 3437 .Case("sse4.1", true) 3438 .Case("sse4.2", true) 3439 .Case("avx", true) 3440 .Case("avx2", true) 3441 .Case("sse4a", true) 3442 .Case("fma4", true) 3443 .Case("xop", true) 3444 .Case("fma", true) 3445 .Case("avx512f", true) 3446 .Case("bmi", true) 3447 .Case("bmi2", true) 3448 .Default(false); 3449 } 3450 3451 bool 3452 X86TargetInfo::validateAsmConstraint(const char *&Name, 3453 TargetInfo::ConstraintInfo &Info) const { 3454 switch (*Name) { 3455 default: return false; 3456 // Constant constraints. 3457 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3458 // instructions. 3459 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3460 // x86_64 instructions. 3461 case 's': 3462 Info.setRequiresImmediate(); 3463 return true; 3464 case 'I': 3465 Info.setRequiresImmediate(0, 31); 3466 return true; 3467 case 'J': 3468 Info.setRequiresImmediate(0, 63); 3469 return true; 3470 case 'K': 3471 Info.setRequiresImmediate(-128, 127); 3472 return true; 3473 case 'L': 3474 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3475 return true; 3476 case 'M': 3477 Info.setRequiresImmediate(0, 3); 3478 return true; 3479 case 'N': 3480 Info.setRequiresImmediate(0, 255); 3481 return true; 3482 case 'O': 3483 Info.setRequiresImmediate(0, 127); 3484 return true; 3485 // Register constraints. 3486 case 'Y': // 'Y' is the first character for several 2-character constraints. 3487 // Shift the pointer to the second character of the constraint. 3488 Name++; 3489 switch (*Name) { 3490 default: 3491 return false; 3492 case '0': // First SSE register. 3493 case 't': // Any SSE register, when SSE2 is enabled. 3494 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3495 case 'm': // Any MMX register, when inter-unit moves enabled. 3496 Info.setAllowsRegister(); 3497 return true; 3498 } 3499 case 'f': // Any x87 floating point stack register. 3500 // Constraint 'f' cannot be used for output operands. 3501 if (Info.ConstraintStr[0] == '=') 3502 return false; 3503 Info.setAllowsRegister(); 3504 return true; 3505 case 'a': // eax. 3506 case 'b': // ebx. 3507 case 'c': // ecx. 3508 case 'd': // edx. 3509 case 'S': // esi. 3510 case 'D': // edi. 3511 case 'A': // edx:eax. 3512 case 't': // Top of floating point stack. 3513 case 'u': // Second from top of floating point stack. 3514 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3515 case 'y': // Any MMX register. 3516 case 'x': // Any SSE register. 3517 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3518 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3519 case 'l': // "Index" registers: any general register that can be used as an 3520 // index in a base+index memory access. 3521 Info.setAllowsRegister(); 3522 return true; 3523 // Floating point constant constraints. 3524 case 'C': // SSE floating point constant. 3525 case 'G': // x87 floating point constant. 3526 return true; 3527 } 3528 } 3529 3530 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3531 unsigned Size) const { 3532 // Strip off constraint modifiers. 3533 while (Constraint[0] == '=' || 3534 Constraint[0] == '+' || 3535 Constraint[0] == '&') 3536 Constraint = Constraint.substr(1); 3537 3538 return validateOperandSize(Constraint, Size); 3539 } 3540 3541 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3542 unsigned Size) const { 3543 return validateOperandSize(Constraint, Size); 3544 } 3545 3546 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3547 unsigned Size) const { 3548 switch (Constraint[0]) { 3549 default: break; 3550 case 'y': 3551 return Size <= 64; 3552 case 'f': 3553 case 't': 3554 case 'u': 3555 return Size <= 128; 3556 case 'x': 3557 if (SSELevel >= AVX512F) 3558 // 512-bit zmm registers can be used if target supports AVX512F. 3559 return Size <= 512U; 3560 else if (SSELevel >= AVX) 3561 // 256-bit ymm registers can be used if target supports AVX. 3562 return Size <= 256U; 3563 return Size <= 128U; 3564 case 'Y': 3565 // 'Y' is the first character for several 2-character constraints. 3566 switch (Constraint[1]) { 3567 default: break; 3568 case 'm': 3569 // 'Ym' is synonymous with 'y'. 3570 return Size <= 64; 3571 case 'i': 3572 case 't': 3573 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3574 if (SSELevel >= AVX512F) 3575 return Size <= 512U; 3576 else if (SSELevel >= AVX) 3577 return Size <= 256U; 3578 return SSELevel >= SSE2 && Size <= 128U; 3579 } 3580 3581 } 3582 3583 return true; 3584 } 3585 3586 std::string 3587 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3588 switch (*Constraint) { 3589 case 'a': return std::string("{ax}"); 3590 case 'b': return std::string("{bx}"); 3591 case 'c': return std::string("{cx}"); 3592 case 'd': return std::string("{dx}"); 3593 case 'S': return std::string("{si}"); 3594 case 'D': return std::string("{di}"); 3595 case 'p': // address 3596 return std::string("im"); 3597 case 't': // top of floating point stack. 3598 return std::string("{st}"); 3599 case 'u': // second from top of floating point stack. 3600 return std::string("{st(1)}"); // second from top of floating point stack. 3601 default: 3602 return std::string(1, *Constraint); 3603 } 3604 } 3605 3606 // X86-32 generic target 3607 class X86_32TargetInfo : public X86TargetInfo { 3608 public: 3609 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3610 DoubleAlign = LongLongAlign = 32; 3611 LongDoubleWidth = 96; 3612 LongDoubleAlign = 32; 3613 SuitableAlign = 128; 3614 DataLayoutString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3615 SizeType = UnsignedInt; 3616 PtrDiffType = SignedInt; 3617 IntPtrType = SignedInt; 3618 RegParmMax = 3; 3619 3620 // Use fpret for all types. 3621 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3622 (1 << TargetInfo::Double) | 3623 (1 << TargetInfo::LongDouble)); 3624 3625 // x86-32 has atomics up to 8 bytes 3626 // FIXME: Check that we actually have cmpxchg8b before setting 3627 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3628 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3629 } 3630 BuiltinVaListKind getBuiltinVaListKind() const override { 3631 return TargetInfo::CharPtrBuiltinVaList; 3632 } 3633 3634 int getEHDataRegisterNumber(unsigned RegNo) const override { 3635 if (RegNo == 0) return 0; 3636 if (RegNo == 1) return 2; 3637 return -1; 3638 } 3639 bool validateOperandSize(StringRef Constraint, 3640 unsigned Size) const override { 3641 switch (Constraint[0]) { 3642 default: break; 3643 case 'R': 3644 case 'q': 3645 case 'Q': 3646 case 'a': 3647 case 'b': 3648 case 'c': 3649 case 'd': 3650 case 'S': 3651 case 'D': 3652 return Size <= 32; 3653 case 'A': 3654 return Size <= 64; 3655 } 3656 3657 return X86TargetInfo::validateOperandSize(Constraint, Size); 3658 } 3659 }; 3660 3661 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3662 public: 3663 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3664 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3665 3666 unsigned getFloatEvalMethod() const override { 3667 unsigned Major, Minor, Micro; 3668 getTriple().getOSVersion(Major, Minor, Micro); 3669 // New NetBSD uses the default rounding mode. 3670 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3671 return X86_32TargetInfo::getFloatEvalMethod(); 3672 // NetBSD before 6.99.26 defaults to "double" rounding. 3673 return 1; 3674 } 3675 }; 3676 3677 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3678 public: 3679 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3680 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3681 SizeType = UnsignedLong; 3682 IntPtrType = SignedLong; 3683 PtrDiffType = SignedLong; 3684 } 3685 }; 3686 3687 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3688 public: 3689 BitrigI386TargetInfo(const llvm::Triple &Triple) 3690 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3691 SizeType = UnsignedLong; 3692 IntPtrType = SignedLong; 3693 PtrDiffType = SignedLong; 3694 } 3695 }; 3696 3697 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3698 public: 3699 DarwinI386TargetInfo(const llvm::Triple &Triple) 3700 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3701 LongDoubleWidth = 128; 3702 LongDoubleAlign = 128; 3703 SuitableAlign = 128; 3704 MaxVectorAlign = 256; 3705 SizeType = UnsignedLong; 3706 IntPtrType = SignedLong; 3707 DataLayoutString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3708 HasAlignMac68kSupport = true; 3709 } 3710 3711 }; 3712 3713 // x86-32 Windows target 3714 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3715 public: 3716 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3717 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3718 WCharType = UnsignedShort; 3719 DoubleAlign = LongLongAlign = 64; 3720 bool IsWinCOFF = 3721 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3722 DataLayoutString = IsWinCOFF 3723 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3724 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3725 } 3726 void getTargetDefines(const LangOptions &Opts, 3727 MacroBuilder &Builder) const override { 3728 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3729 } 3730 }; 3731 3732 // x86-32 Windows Visual Studio target 3733 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3734 public: 3735 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3736 : WindowsX86_32TargetInfo(Triple) { 3737 LongDoubleWidth = LongDoubleAlign = 64; 3738 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3739 } 3740 void getTargetDefines(const LangOptions &Opts, 3741 MacroBuilder &Builder) const override { 3742 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3743 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3744 // The value of the following reflects processor type. 3745 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3746 // We lost the original triple, so we use the default. 3747 Builder.defineMacro("_M_IX86", "600"); 3748 } 3749 }; 3750 } // end anonymous namespace 3751 3752 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3753 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang supports 3754 // __declspec natively under -fms-extensions, but we define a no-op __declspec 3755 // macro anyway for pre-processor compatibility. 3756 if (Opts.MicrosoftExt) 3757 Builder.defineMacro("__declspec", "__declspec"); 3758 else 3759 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3760 3761 if (!Opts.MicrosoftExt) { 3762 // Provide macros for all the calling convention keywords. Provide both 3763 // single and double underscore prefixed variants. These are available on 3764 // x64 as well as x86, even though they have no effect. 3765 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3766 for (const char *CC : CCs) { 3767 std::string GCCSpelling = "__attribute__((__"; 3768 GCCSpelling += CC; 3769 GCCSpelling += "__))"; 3770 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3771 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3772 } 3773 } 3774 } 3775 3776 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3777 Builder.defineMacro("__MSVCRT__"); 3778 Builder.defineMacro("__MINGW32__"); 3779 addCygMingDefines(Opts, Builder); 3780 } 3781 3782 namespace { 3783 // x86-32 MinGW target 3784 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3785 public: 3786 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3787 : WindowsX86_32TargetInfo(Triple) {} 3788 void getTargetDefines(const LangOptions &Opts, 3789 MacroBuilder &Builder) const override { 3790 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3791 DefineStd(Builder, "WIN32", Opts); 3792 DefineStd(Builder, "WINNT", Opts); 3793 Builder.defineMacro("_X86_"); 3794 addMinGWDefines(Opts, Builder); 3795 } 3796 }; 3797 3798 // x86-32 Cygwin target 3799 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3800 public: 3801 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3802 : X86_32TargetInfo(Triple) { 3803 TLSSupported = false; 3804 WCharType = UnsignedShort; 3805 DoubleAlign = LongLongAlign = 64; 3806 DataLayoutString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3807 } 3808 void getTargetDefines(const LangOptions &Opts, 3809 MacroBuilder &Builder) const override { 3810 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3811 Builder.defineMacro("_X86_"); 3812 Builder.defineMacro("__CYGWIN__"); 3813 Builder.defineMacro("__CYGWIN32__"); 3814 addCygMingDefines(Opts, Builder); 3815 DefineStd(Builder, "unix", Opts); 3816 if (Opts.CPlusPlus) 3817 Builder.defineMacro("_GNU_SOURCE"); 3818 } 3819 }; 3820 3821 // x86-32 Haiku target 3822 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3823 public: 3824 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3825 SizeType = UnsignedLong; 3826 IntPtrType = SignedLong; 3827 PtrDiffType = SignedLong; 3828 ProcessIDType = SignedLong; 3829 this->UserLabelPrefix = ""; 3830 this->TLSSupported = false; 3831 } 3832 void getTargetDefines(const LangOptions &Opts, 3833 MacroBuilder &Builder) const override { 3834 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3835 Builder.defineMacro("__INTEL__"); 3836 Builder.defineMacro("__HAIKU__"); 3837 } 3838 }; 3839 3840 // RTEMS Target 3841 template<typename Target> 3842 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3843 protected: 3844 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3845 MacroBuilder &Builder) const override { 3846 // RTEMS defines; list based off of gcc output 3847 3848 Builder.defineMacro("__rtems__"); 3849 Builder.defineMacro("__ELF__"); 3850 } 3851 3852 public: 3853 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3854 this->UserLabelPrefix = ""; 3855 3856 switch (Triple.getArch()) { 3857 default: 3858 case llvm::Triple::x86: 3859 // this->MCountName = ".mcount"; 3860 break; 3861 case llvm::Triple::mips: 3862 case llvm::Triple::mipsel: 3863 case llvm::Triple::ppc: 3864 case llvm::Triple::ppc64: 3865 case llvm::Triple::ppc64le: 3866 // this->MCountName = "_mcount"; 3867 break; 3868 case llvm::Triple::arm: 3869 // this->MCountName = "__mcount"; 3870 break; 3871 } 3872 } 3873 }; 3874 3875 // x86-32 RTEMS target 3876 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3877 public: 3878 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3879 SizeType = UnsignedLong; 3880 IntPtrType = SignedLong; 3881 PtrDiffType = SignedLong; 3882 this->UserLabelPrefix = ""; 3883 } 3884 void getTargetDefines(const LangOptions &Opts, 3885 MacroBuilder &Builder) const override { 3886 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3887 Builder.defineMacro("__INTEL__"); 3888 Builder.defineMacro("__rtems__"); 3889 } 3890 }; 3891 3892 // x86-64 generic target 3893 class X86_64TargetInfo : public X86TargetInfo { 3894 public: 3895 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3896 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3897 bool IsWinCOFF = 3898 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3899 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3900 LongDoubleWidth = 128; 3901 LongDoubleAlign = 128; 3902 LargeArrayMinWidth = 128; 3903 LargeArrayAlign = 128; 3904 SuitableAlign = 128; 3905 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3906 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3907 IntPtrType = IsX32 ? SignedInt : SignedLong; 3908 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3909 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3910 RegParmMax = 6; 3911 3912 // Pointers are 32-bit in x32. 3913 DataLayoutString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3914 : IsWinCOFF 3915 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 3916 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3917 3918 // Use fpret only for long double. 3919 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3920 3921 // Use fp2ret for _Complex long double. 3922 ComplexLongDoubleUsesFP2Ret = true; 3923 3924 // x86-64 has atomics up to 16 bytes. 3925 MaxAtomicPromoteWidth = 128; 3926 MaxAtomicInlineWidth = 128; 3927 } 3928 BuiltinVaListKind getBuiltinVaListKind() const override { 3929 return TargetInfo::X86_64ABIBuiltinVaList; 3930 } 3931 3932 int getEHDataRegisterNumber(unsigned RegNo) const override { 3933 if (RegNo == 0) return 0; 3934 if (RegNo == 1) return 1; 3935 return -1; 3936 } 3937 3938 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3939 return (CC == CC_C || 3940 CC == CC_X86VectorCall || 3941 CC == CC_IntelOclBicc || 3942 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3943 } 3944 3945 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3946 return CC_C; 3947 } 3948 3949 // for x32 we need it here explicitly 3950 bool hasInt128Type() const override { return true; } 3951 }; 3952 3953 // x86-64 Windows target 3954 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3955 public: 3956 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3957 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3958 WCharType = UnsignedShort; 3959 LongWidth = LongAlign = 32; 3960 DoubleAlign = LongLongAlign = 64; 3961 IntMaxType = SignedLongLong; 3962 Int64Type = SignedLongLong; 3963 SizeType = UnsignedLongLong; 3964 PtrDiffType = SignedLongLong; 3965 IntPtrType = SignedLongLong; 3966 this->UserLabelPrefix = ""; 3967 } 3968 3969 void getTargetDefines(const LangOptions &Opts, 3970 MacroBuilder &Builder) const override { 3971 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3972 Builder.defineMacro("_WIN64"); 3973 } 3974 3975 BuiltinVaListKind getBuiltinVaListKind() const override { 3976 return TargetInfo::CharPtrBuiltinVaList; 3977 } 3978 3979 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3980 switch (CC) { 3981 case CC_X86StdCall: 3982 case CC_X86ThisCall: 3983 case CC_X86FastCall: 3984 return CCCR_Ignore; 3985 case CC_C: 3986 case CC_X86VectorCall: 3987 case CC_IntelOclBicc: 3988 case CC_X86_64SysV: 3989 return CCCR_OK; 3990 default: 3991 return CCCR_Warning; 3992 } 3993 } 3994 }; 3995 3996 // x86-64 Windows Visual Studio target 3997 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 3998 public: 3999 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 4000 : WindowsX86_64TargetInfo(Triple) { 4001 LongDoubleWidth = LongDoubleAlign = 64; 4002 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4003 } 4004 void getTargetDefines(const LangOptions &Opts, 4005 MacroBuilder &Builder) const override { 4006 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4007 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4008 Builder.defineMacro("_M_X64", "100"); 4009 Builder.defineMacro("_M_AMD64", "100"); 4010 } 4011 }; 4012 4013 // x86-64 MinGW target 4014 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4015 public: 4016 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 4017 : WindowsX86_64TargetInfo(Triple) {} 4018 void getTargetDefines(const LangOptions &Opts, 4019 MacroBuilder &Builder) const override { 4020 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4021 DefineStd(Builder, "WIN64", Opts); 4022 Builder.defineMacro("__MINGW64__"); 4023 addMinGWDefines(Opts, Builder); 4024 4025 // GCC defines this macro when it is using __gxx_personality_seh0. 4026 if (!Opts.SjLjExceptions) 4027 Builder.defineMacro("__SEH__"); 4028 } 4029 }; 4030 4031 // x86-64 Cygwin target 4032 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4033 public: 4034 CygwinX86_64TargetInfo(const llvm::Triple &Triple) 4035 : X86_64TargetInfo(Triple) { 4036 TLSSupported = false; 4037 WCharType = UnsignedShort; 4038 } 4039 void getTargetDefines(const LangOptions &Opts, 4040 MacroBuilder &Builder) const override { 4041 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4042 Builder.defineMacro("__x86_64__"); 4043 Builder.defineMacro("__CYGWIN__"); 4044 Builder.defineMacro("__CYGWIN64__"); 4045 addCygMingDefines(Opts, Builder); 4046 DefineStd(Builder, "unix", Opts); 4047 if (Opts.CPlusPlus) 4048 Builder.defineMacro("_GNU_SOURCE"); 4049 4050 // GCC defines this macro when it is using __gxx_personality_seh0. 4051 if (!Opts.SjLjExceptions) 4052 Builder.defineMacro("__SEH__"); 4053 } 4054 }; 4055 4056 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4057 public: 4058 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 4059 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 4060 Int64Type = SignedLongLong; 4061 MaxVectorAlign = 256; 4062 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4063 llvm::Triple T = llvm::Triple(Triple); 4064 if (T.isiOS()) 4065 UseSignedCharForObjCBool = false; 4066 DataLayoutString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 4067 } 4068 }; 4069 4070 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4071 public: 4072 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 4073 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 4074 IntMaxType = SignedLongLong; 4075 Int64Type = SignedLongLong; 4076 } 4077 }; 4078 4079 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4080 public: 4081 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 4082 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 4083 IntMaxType = SignedLongLong; 4084 Int64Type = SignedLongLong; 4085 } 4086 }; 4087 4088 class ARMTargetInfo : public TargetInfo { 4089 // Possible FPU choices. 4090 enum FPUMode { 4091 VFP2FPU = (1 << 0), 4092 VFP3FPU = (1 << 1), 4093 VFP4FPU = (1 << 2), 4094 NeonFPU = (1 << 3), 4095 FPARMV8 = (1 << 4) 4096 }; 4097 4098 // Possible HWDiv features. 4099 enum HWDivMode { 4100 HWDivThumb = (1 << 0), 4101 HWDivARM = (1 << 1) 4102 }; 4103 4104 static bool FPUModeIsVFP(FPUMode Mode) { 4105 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4106 } 4107 4108 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4109 static const char * const GCCRegNames[]; 4110 4111 std::string ABI, CPU; 4112 4113 StringRef DefaultCPU; 4114 StringRef CPUProfile; 4115 StringRef CPUAttr; 4116 4117 enum { 4118 FP_Default, 4119 FP_VFP, 4120 FP_Neon 4121 } FPMath; 4122 4123 unsigned ArchISA; 4124 unsigned ArchKind; 4125 unsigned ArchProfile; 4126 unsigned ArchVersion; 4127 4128 unsigned FPU : 5; 4129 4130 unsigned IsAAPCS : 1; 4131 unsigned HWDiv : 2; 4132 4133 // Initialized via features. 4134 unsigned SoftFloat : 1; 4135 unsigned SoftFloatABI : 1; 4136 4137 unsigned CRC : 1; 4138 unsigned Crypto : 1; 4139 4140 // ACLE 6.5.1 Hardware floating point 4141 enum { 4142 HW_FP_HP = (1 << 1), /// half (16-bit) 4143 HW_FP_SP = (1 << 2), /// single (32-bit) 4144 HW_FP_DP = (1 << 3), /// double (64-bit) 4145 }; 4146 uint32_t HW_FP; 4147 4148 static const Builtin::Info BuiltinInfo[]; 4149 4150 void setABIAAPCS() { 4151 IsAAPCS = true; 4152 4153 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4154 const llvm::Triple &T = getTriple(); 4155 4156 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4157 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4158 T.getOS() == llvm::Triple::Bitrig) 4159 SizeType = UnsignedLong; 4160 else 4161 SizeType = UnsignedInt; 4162 4163 switch (T.getOS()) { 4164 case llvm::Triple::NetBSD: 4165 WCharType = SignedInt; 4166 break; 4167 case llvm::Triple::Win32: 4168 WCharType = UnsignedShort; 4169 break; 4170 case llvm::Triple::Linux: 4171 default: 4172 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4173 WCharType = UnsignedInt; 4174 break; 4175 } 4176 4177 UseBitFieldTypeAlignment = true; 4178 4179 ZeroLengthBitfieldBoundary = 0; 4180 4181 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4182 // so set preferred for small types to 32. 4183 if (T.isOSBinFormatMachO()) { 4184 DataLayoutString = 4185 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4186 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4187 } else if (T.isOSWindows()) { 4188 assert(!BigEndian && "Windows on ARM does not support big endian"); 4189 DataLayoutString = "e" 4190 "-m:w" 4191 "-p:32:32" 4192 "-i64:64" 4193 "-v128:64:128" 4194 "-a:0:32" 4195 "-n32" 4196 "-S64"; 4197 } else if (T.isOSNaCl()) { 4198 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4199 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 4200 } else { 4201 DataLayoutString = 4202 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4203 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4204 } 4205 4206 // FIXME: Enumerated types are variable width in straight AAPCS. 4207 } 4208 4209 void setABIAPCS() { 4210 const llvm::Triple &T = getTriple(); 4211 4212 IsAAPCS = false; 4213 4214 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4215 4216 // size_t is unsigned int on FreeBSD. 4217 if (T.getOS() == llvm::Triple::FreeBSD) 4218 SizeType = UnsignedInt; 4219 else 4220 SizeType = UnsignedLong; 4221 4222 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4223 WCharType = SignedInt; 4224 4225 // Do not respect the alignment of bit-field types when laying out 4226 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4227 UseBitFieldTypeAlignment = false; 4228 4229 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4230 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4231 /// gcc. 4232 ZeroLengthBitfieldBoundary = 32; 4233 4234 if (T.isOSBinFormatMachO()) 4235 DataLayoutString = 4236 BigEndian 4237 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4238 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4239 else 4240 DataLayoutString = 4241 BigEndian 4242 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4243 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4244 4245 // FIXME: Override "preferred align" for double and long long. 4246 } 4247 4248 void setArchInfo() { 4249 StringRef ArchName = getTriple().getArchName(); 4250 4251 ArchISA = llvm::ARMTargetParser::parseArchISA(ArchName); 4252 DefaultCPU = getDefaultCPU(ArchName); 4253 4254 // SubArch is specified by the target triple 4255 if (!DefaultCPU.empty()) 4256 setArchInfo(DefaultCPU); 4257 else 4258 // FIXME ArchInfo should be based on ArchName from triple, not on 4259 // a hard-coded CPU name. Doing so currently causes regressions: 4260 // test/Preprocessor/init.c: __ARM_ARCH_6J__ not defined 4261 setArchInfo(CPU); 4262 } 4263 4264 void setArchInfo(StringRef CPU) { 4265 StringRef SubArch; 4266 4267 // cache TargetParser info 4268 ArchKind = llvm::ARMTargetParser::parseCPUArch(CPU); 4269 SubArch = llvm::ARMTargetParser::getSubArch(ArchKind); 4270 ArchProfile = llvm::ARMTargetParser::parseArchProfile(SubArch); 4271 ArchVersion = llvm::ARMTargetParser::parseArchVersion(SubArch); 4272 4273 // cache CPU related strings 4274 CPUAttr = getCPUAttr(); 4275 CPUProfile = getCPUProfile(); 4276 } 4277 4278 void setAtomic() { 4279 // when triple does not specify a sub arch, 4280 // then we are not using inline atomics 4281 bool ShouldUseInlineAtomic = DefaultCPU.empty() ? 4282 false : 4283 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4284 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4285 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4286 if (ArchProfile == llvm::ARM::PK_M) { 4287 MaxAtomicPromoteWidth = 32; 4288 if (ShouldUseInlineAtomic) 4289 MaxAtomicInlineWidth = 32; 4290 } 4291 else { 4292 MaxAtomicPromoteWidth = 64; 4293 if (ShouldUseInlineAtomic) 4294 MaxAtomicInlineWidth = 64; 4295 } 4296 } 4297 4298 bool isThumb() const { 4299 return (ArchISA == llvm::ARM::IK_THUMB); 4300 } 4301 4302 bool supportsThumb() const { 4303 return CPUAttr.count('T') || ArchVersion >= 6; 4304 } 4305 4306 bool supportsThumb2() const { 4307 return CPUAttr.equals("6T2") || ArchVersion >= 7; 4308 } 4309 4310 StringRef getDefaultCPU(StringRef ArchName) const { 4311 const char *DefaultCPU = llvm::ARMTargetParser::getDefaultCPU(ArchName); 4312 return DefaultCPU ? DefaultCPU : ""; 4313 } 4314 4315 StringRef getCPUAttr() const { 4316 const char *CPUAttr; 4317 // For most sub-arches, the build attribute CPU name is enough. 4318 // For Cortex variants, it's slightly different. 4319 switch(ArchKind) { 4320 default: 4321 CPUAttr = llvm::ARMTargetParser::getCPUAttr(ArchKind); 4322 return CPUAttr ? CPUAttr : ""; 4323 case llvm::ARM::AK_ARMV6M: 4324 case llvm::ARM::AK_ARMV6SM: 4325 case llvm::ARM::AK_ARMV6HL: 4326 return "6M"; 4327 case llvm::ARM::AK_ARMV7S: 4328 return "7S"; 4329 case llvm::ARM::AK_ARMV7: 4330 case llvm::ARM::AK_ARMV7A: 4331 case llvm::ARM::AK_ARMV7L: 4332 case llvm::ARM::AK_ARMV7HL: 4333 return "7A"; 4334 case llvm::ARM::AK_ARMV7R: 4335 return "7R"; 4336 case llvm::ARM::AK_ARMV7M: 4337 return "7M"; 4338 case llvm::ARM::AK_ARMV7EM: 4339 return "7EM"; 4340 case llvm::ARM::AK_ARMV8A: 4341 return "8A"; 4342 case llvm::ARM::AK_ARMV8_1A: 4343 return "8_1A"; 4344 } 4345 } 4346 4347 StringRef getCPUProfile() const { 4348 switch(ArchProfile) { 4349 case llvm::ARM::PK_A: 4350 return "A"; 4351 case llvm::ARM::PK_R: 4352 return "R"; 4353 case llvm::ARM::PK_M: 4354 return "M"; 4355 default: 4356 return ""; 4357 } 4358 } 4359 4360 public: 4361 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4362 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 4363 IsAAPCS(true), HW_FP(0) { 4364 BigEndian = IsBigEndian; 4365 4366 switch (getTriple().getOS()) { 4367 case llvm::Triple::NetBSD: 4368 PtrDiffType = SignedLong; 4369 break; 4370 default: 4371 PtrDiffType = SignedInt; 4372 break; 4373 } 4374 4375 // cache arch related info 4376 setArchInfo(); 4377 4378 // {} in inline assembly are neon specifiers, not assembly variant 4379 // specifiers. 4380 NoAsmVariants = true; 4381 4382 // FIXME: This duplicates code from the driver that sets the -target-abi 4383 // option - this code is used if -target-abi isn't passed and should 4384 // be unified in some way. 4385 if (Triple.isOSBinFormatMachO()) { 4386 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4387 // the frontend matches that. 4388 if (Triple.getEnvironment() == llvm::Triple::EABI || 4389 Triple.getOS() == llvm::Triple::UnknownOS || 4390 StringRef(CPU).startswith("cortex-m")) { 4391 setABI("aapcs"); 4392 } else { 4393 setABI("apcs-gnu"); 4394 } 4395 } else if (Triple.isOSWindows()) { 4396 // FIXME: this is invalid for WindowsCE 4397 setABI("aapcs"); 4398 } else { 4399 // Select the default based on the platform. 4400 switch (Triple.getEnvironment()) { 4401 case llvm::Triple::Android: 4402 case llvm::Triple::GNUEABI: 4403 case llvm::Triple::GNUEABIHF: 4404 setABI("aapcs-linux"); 4405 break; 4406 case llvm::Triple::EABIHF: 4407 case llvm::Triple::EABI: 4408 setABI("aapcs"); 4409 break; 4410 case llvm::Triple::GNU: 4411 setABI("apcs-gnu"); 4412 break; 4413 default: 4414 if (Triple.getOS() == llvm::Triple::NetBSD) 4415 setABI("apcs-gnu"); 4416 else 4417 setABI("aapcs"); 4418 break; 4419 } 4420 } 4421 4422 // ARM targets default to using the ARM C++ ABI. 4423 TheCXXABI.set(TargetCXXABI::GenericARM); 4424 4425 // ARM has atomics up to 8 bytes 4426 setAtomic(); 4427 4428 // Do force alignment of members that follow zero length bitfields. If 4429 // the alignment of the zero-length bitfield is greater than the member 4430 // that follows it, `bar', `bar' will be aligned as the type of the 4431 // zero length bitfield. 4432 UseZeroLengthBitfieldAlignment = true; 4433 } 4434 4435 StringRef getABI() const override { return ABI; } 4436 4437 bool setABI(const std::string &Name) override { 4438 ABI = Name; 4439 4440 // The defaults (above) are for AAPCS, check if we need to change them. 4441 // 4442 // FIXME: We need support for -meabi... we could just mangle it into the 4443 // name. 4444 if (Name == "apcs-gnu") { 4445 setABIAPCS(); 4446 return true; 4447 } 4448 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4449 setABIAAPCS(); 4450 return true; 4451 } 4452 return false; 4453 } 4454 4455 // FIXME: This should be based on Arch attributes, not CPU names. 4456 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 4457 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 4458 Features["vfp2"] = true; 4459 else if (CPU == "cortex-a8" || CPU == "cortex-a9") { 4460 Features["vfp3"] = true; 4461 Features["neon"] = true; 4462 } 4463 else if (CPU == "cortex-a5") { 4464 Features["vfp4"] = true; 4465 Features["neon"] = true; 4466 } else if (CPU == "swift" || CPU == "cortex-a7" || 4467 CPU == "cortex-a12" || CPU == "cortex-a15" || 4468 CPU == "cortex-a17" || CPU == "krait") { 4469 Features["vfp4"] = true; 4470 Features["neon"] = true; 4471 Features["hwdiv"] = true; 4472 Features["hwdiv-arm"] = true; 4473 } else if (CPU == "cyclone" || CPU == "cortex-a53" || CPU == "cortex-a57" || 4474 CPU == "cortex-a72") { 4475 Features["fp-armv8"] = true; 4476 Features["neon"] = true; 4477 Features["hwdiv"] = true; 4478 Features["hwdiv-arm"] = true; 4479 Features["crc"] = true; 4480 Features["crypto"] = true; 4481 } else if (CPU == "cortex-r5" || CPU == "cortex-r7" || ArchVersion == 8) { 4482 Features["hwdiv"] = true; 4483 Features["hwdiv-arm"] = true; 4484 } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" || 4485 CPU == "sc300" || CPU == "cortex-r4" || CPU == "cortex-r4f") { 4486 Features["hwdiv"] = true; 4487 } 4488 } 4489 4490 bool handleTargetFeatures(std::vector<std::string> &Features, 4491 DiagnosticsEngine &Diags) override { 4492 FPU = 0; 4493 CRC = 0; 4494 Crypto = 0; 4495 SoftFloat = SoftFloatABI = false; 4496 HWDiv = 0; 4497 4498 // This does not diagnose illegal cases like having both 4499 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4500 uint32_t HW_FP_remove = 0; 4501 for (const auto &Feature : Features) { 4502 if (Feature == "+soft-float") { 4503 SoftFloat = true; 4504 } else if (Feature == "+soft-float-abi") { 4505 SoftFloatABI = true; 4506 } else if (Feature == "+vfp2") { 4507 FPU |= VFP2FPU; 4508 HW_FP |= HW_FP_SP | HW_FP_DP; 4509 } else if (Feature == "+vfp3") { 4510 FPU |= VFP3FPU; 4511 HW_FP |= HW_FP_SP | HW_FP_DP; 4512 } else if (Feature == "+vfp4") { 4513 FPU |= VFP4FPU; 4514 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4515 } else if (Feature == "+fp-armv8") { 4516 FPU |= FPARMV8; 4517 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4518 } else if (Feature == "+neon") { 4519 FPU |= NeonFPU; 4520 HW_FP |= HW_FP_SP | HW_FP_DP; 4521 } else if (Feature == "+hwdiv") { 4522 HWDiv |= HWDivThumb; 4523 } else if (Feature == "+hwdiv-arm") { 4524 HWDiv |= HWDivARM; 4525 } else if (Feature == "+crc") { 4526 CRC = 1; 4527 } else if (Feature == "+crypto") { 4528 Crypto = 1; 4529 } else if (Feature == "+fp-only-sp") { 4530 HW_FP_remove |= HW_FP_DP | HW_FP_HP; 4531 } 4532 } 4533 HW_FP &= ~HW_FP_remove; 4534 4535 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4536 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4537 return false; 4538 } 4539 4540 if (FPMath == FP_Neon) 4541 Features.push_back("+neonfp"); 4542 else if (FPMath == FP_VFP) 4543 Features.push_back("-neonfp"); 4544 4545 // Remove front-end specific options which the backend handles differently. 4546 auto Feature = 4547 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4548 if (Feature != Features.end()) 4549 Features.erase(Feature); 4550 4551 return true; 4552 } 4553 4554 bool hasFeature(StringRef Feature) const override { 4555 return llvm::StringSwitch<bool>(Feature) 4556 .Case("arm", true) 4557 .Case("aarch32", true) 4558 .Case("softfloat", SoftFloat) 4559 .Case("thumb", isThumb()) 4560 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4561 .Case("hwdiv", HWDiv & HWDivThumb) 4562 .Case("hwdiv-arm", HWDiv & HWDivARM) 4563 .Default(false); 4564 } 4565 4566 bool setCPU(const std::string &Name) override { 4567 unsigned ArchKind = llvm::ARMTargetParser::parseCPUArch(Name); 4568 if (ArchKind == llvm::ARM::AK_INVALID) 4569 return false; 4570 setArchInfo(Name); 4571 setAtomic(); 4572 CPU = Name; 4573 return true; 4574 } 4575 4576 bool setFPMath(StringRef Name) override; 4577 4578 void getTargetDefines(const LangOptions &Opts, 4579 MacroBuilder &Builder) const override { 4580 // Target identification. 4581 Builder.defineMacro("__arm"); 4582 Builder.defineMacro("__arm__"); 4583 4584 // Target properties. 4585 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4586 if (!CPUAttr.empty()) 4587 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 4588 4589 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4590 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4591 Builder.defineMacro("__ARM_ARCH", llvm::utostr(ArchVersion)); 4592 if (ArchVersion >= 8) { 4593 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4594 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4595 } 4596 4597 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4598 // is not defined for the M-profile. 4599 // NOTE that the deffault profile is assumed to be 'A' 4600 if (CPUProfile.empty() || CPUProfile != "M") 4601 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4602 4603 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4604 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4605 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4606 if (supportsThumb2()) 4607 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4608 else if (supportsThumb()) 4609 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4610 4611 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4612 // instruction set such as ARM or Thumb. 4613 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4614 4615 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4616 4617 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4618 if (!CPUProfile.empty()) 4619 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4620 4621 // ACLE 6.5.1 Hardware Floating Point 4622 if (HW_FP) 4623 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4624 4625 // ACLE predefines. 4626 Builder.defineMacro("__ARM_ACLE", "200"); 4627 4628 // Subtarget options. 4629 4630 // FIXME: It's more complicated than this and we don't really support 4631 // interworking. 4632 // Windows on ARM does not "support" interworking 4633 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 4634 Builder.defineMacro("__THUMB_INTERWORK__"); 4635 4636 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4637 // Embedded targets on Darwin follow AAPCS, but not EABI. 4638 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4639 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4640 Builder.defineMacro("__ARM_EABI__"); 4641 Builder.defineMacro("__ARM_PCS", "1"); 4642 4643 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4644 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4645 } 4646 4647 if (SoftFloat) 4648 Builder.defineMacro("__SOFTFP__"); 4649 4650 if (CPU == "xscale") 4651 Builder.defineMacro("__XSCALE__"); 4652 4653 if (isThumb()) { 4654 Builder.defineMacro("__THUMBEL__"); 4655 Builder.defineMacro("__thumb__"); 4656 if (supportsThumb2()) 4657 Builder.defineMacro("__thumb2__"); 4658 } 4659 if (((HWDiv & HWDivThumb) && isThumb()) || ((HWDiv & HWDivARM) && !isThumb())) 4660 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4661 4662 // Note, this is always on in gcc, even though it doesn't make sense. 4663 Builder.defineMacro("__APCS_32__"); 4664 4665 if (FPUModeIsVFP((FPUMode) FPU)) { 4666 Builder.defineMacro("__VFP_FP__"); 4667 if (FPU & VFP2FPU) 4668 Builder.defineMacro("__ARM_VFPV2__"); 4669 if (FPU & VFP3FPU) 4670 Builder.defineMacro("__ARM_VFPV3__"); 4671 if (FPU & VFP4FPU) 4672 Builder.defineMacro("__ARM_VFPV4__"); 4673 } 4674 4675 // This only gets set when Neon instructions are actually available, unlike 4676 // the VFP define, hence the soft float and arch check. This is subtly 4677 // different from gcc, we follow the intent which was that it should be set 4678 // when Neon instructions are actually available. 4679 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 4680 Builder.defineMacro("__ARM_NEON"); 4681 Builder.defineMacro("__ARM_NEON__"); 4682 } 4683 4684 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4685 Opts.ShortWChar ? "2" : "4"); 4686 4687 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4688 Opts.ShortEnums ? "1" : "4"); 4689 4690 if (CRC) 4691 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4692 4693 if (Crypto) 4694 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4695 4696 if (ArchVersion >= 6 && CPUAttr != "6M") { 4697 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4698 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4699 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4700 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4701 } 4702 4703 bool is5EOrAbove = (ArchVersion >= 6 || 4704 (ArchVersion == 5 && CPUAttr.count('E'))); 4705 // FIXME: We are not getting all 32-bit ARM architectures 4706 bool is32Bit = (!isThumb() || supportsThumb2()); 4707 if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUAttr == "7EM")) 4708 Builder.defineMacro("__ARM_FEATURE_DSP"); 4709 } 4710 4711 void getTargetBuiltins(const Builtin::Info *&Records, 4712 unsigned &NumRecords) const override { 4713 Records = BuiltinInfo; 4714 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4715 } 4716 bool isCLZForZeroUndef() const override { return false; } 4717 BuiltinVaListKind getBuiltinVaListKind() const override { 4718 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4719 } 4720 void getGCCRegNames(const char * const *&Names, 4721 unsigned &NumNames) const override; 4722 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4723 unsigned &NumAliases) const override; 4724 bool validateAsmConstraint(const char *&Name, 4725 TargetInfo::ConstraintInfo &Info) const override { 4726 switch (*Name) { 4727 default: break; 4728 case 'l': // r0-r7 4729 case 'h': // r8-r15 4730 case 'w': // VFP Floating point register single precision 4731 case 'P': // VFP Floating point register double precision 4732 Info.setAllowsRegister(); 4733 return true; 4734 case 'I': 4735 case 'J': 4736 case 'K': 4737 case 'L': 4738 case 'M': 4739 // FIXME 4740 return true; 4741 case 'Q': // A memory address that is a single base register. 4742 Info.setAllowsMemory(); 4743 return true; 4744 case 'U': // a memory reference... 4745 switch (Name[1]) { 4746 case 'q': // ...ARMV4 ldrsb 4747 case 'v': // ...VFP load/store (reg+constant offset) 4748 case 'y': // ...iWMMXt load/store 4749 case 't': // address valid for load/store opaque types wider 4750 // than 128-bits 4751 case 'n': // valid address for Neon doubleword vector load/store 4752 case 'm': // valid address for Neon element and structure load/store 4753 case 's': // valid address for non-offset loads/stores of quad-word 4754 // values in four ARM registers 4755 Info.setAllowsMemory(); 4756 Name++; 4757 return true; 4758 } 4759 } 4760 return false; 4761 } 4762 std::string convertConstraint(const char *&Constraint) const override { 4763 std::string R; 4764 switch (*Constraint) { 4765 case 'U': // Two-character constraint; add "^" hint for later parsing. 4766 R = std::string("^") + std::string(Constraint, 2); 4767 Constraint++; 4768 break; 4769 case 'p': // 'p' should be translated to 'r' by default. 4770 R = std::string("r"); 4771 break; 4772 default: 4773 return std::string(1, *Constraint); 4774 } 4775 return R; 4776 } 4777 bool 4778 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4779 std::string &SuggestedModifier) const override { 4780 bool isOutput = (Constraint[0] == '='); 4781 bool isInOut = (Constraint[0] == '+'); 4782 4783 // Strip off constraint modifiers. 4784 while (Constraint[0] == '=' || 4785 Constraint[0] == '+' || 4786 Constraint[0] == '&') 4787 Constraint = Constraint.substr(1); 4788 4789 switch (Constraint[0]) { 4790 default: break; 4791 case 'r': { 4792 switch (Modifier) { 4793 default: 4794 return (isInOut || isOutput || Size <= 64); 4795 case 'q': 4796 // A register of size 32 cannot fit a vector type. 4797 return false; 4798 } 4799 } 4800 } 4801 4802 return true; 4803 } 4804 const char *getClobbers() const override { 4805 // FIXME: Is this really right? 4806 return ""; 4807 } 4808 4809 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4810 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4811 } 4812 4813 int getEHDataRegisterNumber(unsigned RegNo) const override { 4814 if (RegNo == 0) return 0; 4815 if (RegNo == 1) return 1; 4816 return -1; 4817 } 4818 4819 bool hasSjLjLowering() const override { 4820 return true; 4821 } 4822 }; 4823 4824 bool ARMTargetInfo::setFPMath(StringRef Name) { 4825 if (Name == "neon") { 4826 FPMath = FP_Neon; 4827 return true; 4828 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4829 Name == "vfp4") { 4830 FPMath = FP_VFP; 4831 return true; 4832 } 4833 return false; 4834 } 4835 4836 const char * const ARMTargetInfo::GCCRegNames[] = { 4837 // Integer registers 4838 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4839 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4840 4841 // Float registers 4842 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4843 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4844 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4845 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4846 4847 // Double registers 4848 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4849 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4850 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4851 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4852 4853 // Quad registers 4854 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4855 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4856 }; 4857 4858 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4859 unsigned &NumNames) const { 4860 Names = GCCRegNames; 4861 NumNames = llvm::array_lengthof(GCCRegNames); 4862 } 4863 4864 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4865 { { "a1" }, "r0" }, 4866 { { "a2" }, "r1" }, 4867 { { "a3" }, "r2" }, 4868 { { "a4" }, "r3" }, 4869 { { "v1" }, "r4" }, 4870 { { "v2" }, "r5" }, 4871 { { "v3" }, "r6" }, 4872 { { "v4" }, "r7" }, 4873 { { "v5" }, "r8" }, 4874 { { "v6", "rfp" }, "r9" }, 4875 { { "sl" }, "r10" }, 4876 { { "fp" }, "r11" }, 4877 { { "ip" }, "r12" }, 4878 { { "r13" }, "sp" }, 4879 { { "r14" }, "lr" }, 4880 { { "r15" }, "pc" }, 4881 // The S, D and Q registers overlap, but aren't really aliases; we 4882 // don't want to substitute one of these for a different-sized one. 4883 }; 4884 4885 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4886 unsigned &NumAliases) const { 4887 Aliases = GCCRegAliases; 4888 NumAliases = llvm::array_lengthof(GCCRegAliases); 4889 } 4890 4891 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4892 #define BUILTIN(ID, TYPE, ATTRS) \ 4893 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 4894 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 4895 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 4896 #include "clang/Basic/BuiltinsNEON.def" 4897 4898 #define BUILTIN(ID, TYPE, ATTRS) \ 4899 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 4900 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 4901 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr}, 4902 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 4903 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 4904 #include "clang/Basic/BuiltinsARM.def" 4905 }; 4906 4907 class ARMleTargetInfo : public ARMTargetInfo { 4908 public: 4909 ARMleTargetInfo(const llvm::Triple &Triple) 4910 : ARMTargetInfo(Triple, false) { } 4911 void getTargetDefines(const LangOptions &Opts, 4912 MacroBuilder &Builder) const override { 4913 Builder.defineMacro("__ARMEL__"); 4914 ARMTargetInfo::getTargetDefines(Opts, Builder); 4915 } 4916 }; 4917 4918 class ARMbeTargetInfo : public ARMTargetInfo { 4919 public: 4920 ARMbeTargetInfo(const llvm::Triple &Triple) 4921 : ARMTargetInfo(Triple, true) { } 4922 void getTargetDefines(const LangOptions &Opts, 4923 MacroBuilder &Builder) const override { 4924 Builder.defineMacro("__ARMEB__"); 4925 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4926 ARMTargetInfo::getTargetDefines(Opts, Builder); 4927 } 4928 }; 4929 4930 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 4931 const llvm::Triple Triple; 4932 public: 4933 WindowsARMTargetInfo(const llvm::Triple &Triple) 4934 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 4935 TLSSupported = false; 4936 WCharType = UnsignedShort; 4937 SizeType = UnsignedInt; 4938 UserLabelPrefix = ""; 4939 } 4940 void getVisualStudioDefines(const LangOptions &Opts, 4941 MacroBuilder &Builder) const { 4942 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 4943 4944 // FIXME: this is invalid for WindowsCE 4945 Builder.defineMacro("_M_ARM_NT", "1"); 4946 Builder.defineMacro("_M_ARMT", "_M_ARM"); 4947 Builder.defineMacro("_M_THUMB", "_M_ARM"); 4948 4949 assert((Triple.getArch() == llvm::Triple::arm || 4950 Triple.getArch() == llvm::Triple::thumb) && 4951 "invalid architecture for Windows ARM target info"); 4952 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 4953 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 4954 4955 // TODO map the complete set of values 4956 // 31: VFPv3 40: VFPv4 4957 Builder.defineMacro("_M_ARM_FP", "31"); 4958 } 4959 BuiltinVaListKind getBuiltinVaListKind() const override { 4960 return TargetInfo::CharPtrBuiltinVaList; 4961 } 4962 }; 4963 4964 // Windows ARM + Itanium C++ ABI Target 4965 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 4966 public: 4967 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 4968 : WindowsARMTargetInfo(Triple) { 4969 TheCXXABI.set(TargetCXXABI::GenericARM); 4970 } 4971 4972 void getTargetDefines(const LangOptions &Opts, 4973 MacroBuilder &Builder) const override { 4974 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4975 4976 if (Opts.MSVCCompat) 4977 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4978 } 4979 }; 4980 4981 // Windows ARM, MS (C++) ABI 4982 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 4983 public: 4984 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 4985 : WindowsARMTargetInfo(Triple) { 4986 TheCXXABI.set(TargetCXXABI::Microsoft); 4987 } 4988 4989 void getTargetDefines(const LangOptions &Opts, 4990 MacroBuilder &Builder) const override { 4991 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4992 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4993 } 4994 }; 4995 4996 // ARM MinGW target 4997 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 4998 public: 4999 MinGWARMTargetInfo(const llvm::Triple &Triple) 5000 : WindowsARMTargetInfo(Triple) { 5001 TheCXXABI.set(TargetCXXABI::GenericARM); 5002 } 5003 5004 void getTargetDefines(const LangOptions &Opts, 5005 MacroBuilder &Builder) const override { 5006 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5007 DefineStd(Builder, "WIN32", Opts); 5008 DefineStd(Builder, "WINNT", Opts); 5009 Builder.defineMacro("_ARM_"); 5010 addMinGWDefines(Opts, Builder); 5011 } 5012 }; 5013 5014 // ARM Cygwin target 5015 class CygwinARMTargetInfo : public ARMleTargetInfo { 5016 public: 5017 CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) { 5018 TLSSupported = false; 5019 WCharType = UnsignedShort; 5020 DoubleAlign = LongLongAlign = 64; 5021 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 5022 } 5023 void getTargetDefines(const LangOptions &Opts, 5024 MacroBuilder &Builder) const override { 5025 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5026 Builder.defineMacro("_ARM_"); 5027 Builder.defineMacro("__CYGWIN__"); 5028 Builder.defineMacro("__CYGWIN32__"); 5029 DefineStd(Builder, "unix", Opts); 5030 if (Opts.CPlusPlus) 5031 Builder.defineMacro("_GNU_SOURCE"); 5032 } 5033 }; 5034 5035 class DarwinARMTargetInfo : 5036 public DarwinTargetInfo<ARMleTargetInfo> { 5037 protected: 5038 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5039 MacroBuilder &Builder) const override { 5040 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5041 } 5042 5043 public: 5044 DarwinARMTargetInfo(const llvm::Triple &Triple) 5045 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 5046 HasAlignMac68kSupport = true; 5047 // iOS always has 64-bit atomic instructions. 5048 // FIXME: This should be based off of the target features in 5049 // ARMleTargetInfo. 5050 MaxAtomicInlineWidth = 64; 5051 5052 // Darwin on iOS uses a variant of the ARM C++ ABI. 5053 TheCXXABI.set(TargetCXXABI::iOS); 5054 } 5055 }; 5056 5057 class AArch64TargetInfo : public TargetInfo { 5058 virtual void setDataLayoutString() = 0; 5059 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5060 static const char *const GCCRegNames[]; 5061 5062 enum FPUModeEnum { 5063 FPUMode, 5064 NeonMode 5065 }; 5066 5067 unsigned FPU; 5068 unsigned CRC; 5069 unsigned Crypto; 5070 5071 static const Builtin::Info BuiltinInfo[]; 5072 5073 std::string ABI; 5074 5075 public: 5076 AArch64TargetInfo(const llvm::Triple &Triple) 5077 : TargetInfo(Triple), ABI("aapcs") { 5078 5079 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5080 WCharType = SignedInt; 5081 5082 // NetBSD apparently prefers consistency across ARM targets to consistency 5083 // across 64-bit targets. 5084 Int64Type = SignedLongLong; 5085 IntMaxType = SignedLongLong; 5086 } else { 5087 WCharType = UnsignedInt; 5088 Int64Type = SignedLong; 5089 IntMaxType = SignedLong; 5090 } 5091 5092 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5093 MaxVectorAlign = 128; 5094 MaxAtomicInlineWidth = 128; 5095 MaxAtomicPromoteWidth = 128; 5096 5097 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5098 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5099 5100 // {} in inline assembly are neon specifiers, not assembly variant 5101 // specifiers. 5102 NoAsmVariants = true; 5103 5104 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5105 // contributes to the alignment of the containing aggregate in the same way 5106 // a plain (non bit-field) member of that type would, without exception for 5107 // zero-sized or anonymous bit-fields." 5108 UseBitFieldTypeAlignment = true; 5109 UseZeroLengthBitfieldAlignment = true; 5110 5111 // AArch64 targets default to using the ARM C++ ABI. 5112 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5113 } 5114 5115 StringRef getABI() const override { return ABI; } 5116 bool setABI(const std::string &Name) override { 5117 if (Name != "aapcs" && Name != "darwinpcs") 5118 return false; 5119 5120 ABI = Name; 5121 return true; 5122 } 5123 5124 bool setCPU(const std::string &Name) override { 5125 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5126 .Case("generic", true) 5127 .Cases("cortex-a53", "cortex-a57", "cortex-a72", true) 5128 .Case("cyclone", true) 5129 .Default(false); 5130 return CPUKnown; 5131 } 5132 5133 void getTargetDefines(const LangOptions &Opts, 5134 MacroBuilder &Builder) const override { 5135 // Target identification. 5136 Builder.defineMacro("__aarch64__"); 5137 5138 // Target properties. 5139 Builder.defineMacro("_LP64"); 5140 Builder.defineMacro("__LP64__"); 5141 5142 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5143 Builder.defineMacro("__ARM_ACLE", "200"); 5144 Builder.defineMacro("__ARM_ARCH", "8"); 5145 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5146 5147 Builder.defineMacro("__ARM_64BIT_STATE"); 5148 Builder.defineMacro("__ARM_PCS_AAPCS64"); 5149 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 5150 5151 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 5152 Builder.defineMacro("__ARM_FEATURE_CLZ"); 5153 Builder.defineMacro("__ARM_FEATURE_FMA"); 5154 Builder.defineMacro("__ARM_FEATURE_DIV"); 5155 Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE 5156 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5157 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 5158 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 5159 5160 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5161 5162 // 0xe implies support for half, single and double precision operations. 5163 Builder.defineMacro("__ARM_FP", "0xe"); 5164 5165 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5166 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5167 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 5168 5169 if (Opts.FastMath || Opts.FiniteMathOnly) 5170 Builder.defineMacro("__ARM_FP_FAST"); 5171 5172 if (Opts.C99 && !Opts.Freestanding) 5173 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 5174 5175 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5176 5177 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5178 Opts.ShortEnums ? "1" : "4"); 5179 5180 if (FPU == NeonMode) { 5181 Builder.defineMacro("__ARM_NEON"); 5182 // 64-bit NEON supports half, single and double precision operations. 5183 Builder.defineMacro("__ARM_NEON_FP", "0xe"); 5184 } 5185 5186 if (CRC) 5187 Builder.defineMacro("__ARM_FEATURE_CRC32"); 5188 5189 if (Crypto) 5190 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 5191 5192 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5193 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5194 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5195 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5196 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5197 } 5198 5199 void getTargetBuiltins(const Builtin::Info *&Records, 5200 unsigned &NumRecords) const override { 5201 Records = BuiltinInfo; 5202 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin; 5203 } 5204 5205 bool hasFeature(StringRef Feature) const override { 5206 return Feature == "aarch64" || 5207 Feature == "arm64" || 5208 Feature == "arm" || 5209 (Feature == "neon" && FPU == NeonMode); 5210 } 5211 5212 bool handleTargetFeatures(std::vector<std::string> &Features, 5213 DiagnosticsEngine &Diags) override { 5214 FPU = FPUMode; 5215 CRC = 0; 5216 Crypto = 0; 5217 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 5218 if (Features[i] == "+neon") 5219 FPU = NeonMode; 5220 if (Features[i] == "+crc") 5221 CRC = 1; 5222 if (Features[i] == "+crypto") 5223 Crypto = 1; 5224 } 5225 5226 setDataLayoutString(); 5227 5228 return true; 5229 } 5230 5231 bool isCLZForZeroUndef() const override { return false; } 5232 5233 BuiltinVaListKind getBuiltinVaListKind() const override { 5234 return TargetInfo::AArch64ABIBuiltinVaList; 5235 } 5236 5237 void getGCCRegNames(const char *const *&Names, 5238 unsigned &NumNames) const override; 5239 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5240 unsigned &NumAliases) const override; 5241 5242 bool validateAsmConstraint(const char *&Name, 5243 TargetInfo::ConstraintInfo &Info) const override { 5244 switch (*Name) { 5245 default: 5246 return false; 5247 case 'w': // Floating point and SIMD registers (V0-V31) 5248 Info.setAllowsRegister(); 5249 return true; 5250 case 'I': // Constant that can be used with an ADD instruction 5251 case 'J': // Constant that can be used with a SUB instruction 5252 case 'K': // Constant that can be used with a 32-bit logical instruction 5253 case 'L': // Constant that can be used with a 64-bit logical instruction 5254 case 'M': // Constant that can be used as a 32-bit MOV immediate 5255 case 'N': // Constant that can be used as a 64-bit MOV immediate 5256 case 'Y': // Floating point constant zero 5257 case 'Z': // Integer constant zero 5258 return true; 5259 case 'Q': // A memory reference with base register and no offset 5260 Info.setAllowsMemory(); 5261 return true; 5262 case 'S': // A symbolic address 5263 Info.setAllowsRegister(); 5264 return true; 5265 case 'U': 5266 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5267 // Utf: A memory address suitable for ldp/stp in TF mode. 5268 // Usa: An absolute symbolic address. 5269 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5270 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5271 case 'z': // Zero register, wzr or xzr 5272 Info.setAllowsRegister(); 5273 return true; 5274 case 'x': // Floating point and SIMD registers (V0-V15) 5275 Info.setAllowsRegister(); 5276 return true; 5277 } 5278 return false; 5279 } 5280 5281 bool 5282 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5283 std::string &SuggestedModifier) const override { 5284 // Strip off constraint modifiers. 5285 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5286 Constraint = Constraint.substr(1); 5287 5288 switch (Constraint[0]) { 5289 default: 5290 return true; 5291 case 'z': 5292 case 'r': { 5293 switch (Modifier) { 5294 case 'x': 5295 case 'w': 5296 // For now assume that the person knows what they're 5297 // doing with the modifier. 5298 return true; 5299 default: 5300 // By default an 'r' constraint will be in the 'x' 5301 // registers. 5302 if (Size == 64) 5303 return true; 5304 5305 SuggestedModifier = "w"; 5306 return false; 5307 } 5308 } 5309 } 5310 } 5311 5312 const char *getClobbers() const override { return ""; } 5313 5314 int getEHDataRegisterNumber(unsigned RegNo) const override { 5315 if (RegNo == 0) 5316 return 0; 5317 if (RegNo == 1) 5318 return 1; 5319 return -1; 5320 } 5321 }; 5322 5323 const char *const AArch64TargetInfo::GCCRegNames[] = { 5324 // 32-bit Integer registers 5325 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5326 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5327 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5328 5329 // 64-bit Integer registers 5330 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5331 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5332 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5333 5334 // 32-bit floating point regsisters 5335 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5336 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5337 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5338 5339 // 64-bit floating point regsisters 5340 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5341 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5342 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5343 5344 // Vector registers 5345 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5346 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5347 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5348 }; 5349 5350 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names, 5351 unsigned &NumNames) const { 5352 Names = GCCRegNames; 5353 NumNames = llvm::array_lengthof(GCCRegNames); 5354 } 5355 5356 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5357 { { "w31" }, "wsp" }, 5358 { { "x29" }, "fp" }, 5359 { { "x30" }, "lr" }, 5360 { { "x31" }, "sp" }, 5361 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5362 // don't want to substitute one of these for a different-sized one. 5363 }; 5364 5365 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5366 unsigned &NumAliases) const { 5367 Aliases = GCCRegAliases; 5368 NumAliases = llvm::array_lengthof(GCCRegAliases); 5369 } 5370 5371 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5372 #define BUILTIN(ID, TYPE, ATTRS) \ 5373 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5374 #include "clang/Basic/BuiltinsNEON.def" 5375 5376 #define BUILTIN(ID, TYPE, ATTRS) \ 5377 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5378 #include "clang/Basic/BuiltinsAArch64.def" 5379 }; 5380 5381 class AArch64leTargetInfo : public AArch64TargetInfo { 5382 void setDataLayoutString() override { 5383 if (getTriple().isOSBinFormatMachO()) 5384 DataLayoutString = "e-m:o-i64:64-i128:128-n32:64-S128"; 5385 else 5386 DataLayoutString = "e-m:e-i64:64-i128:128-n32:64-S128"; 5387 } 5388 5389 public: 5390 AArch64leTargetInfo(const llvm::Triple &Triple) 5391 : AArch64TargetInfo(Triple) { 5392 BigEndian = false; 5393 } 5394 void getTargetDefines(const LangOptions &Opts, 5395 MacroBuilder &Builder) const override { 5396 Builder.defineMacro("__AARCH64EL__"); 5397 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5398 } 5399 }; 5400 5401 class AArch64beTargetInfo : public AArch64TargetInfo { 5402 void setDataLayoutString() override { 5403 assert(!getTriple().isOSBinFormatMachO()); 5404 DataLayoutString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5405 } 5406 5407 public: 5408 AArch64beTargetInfo(const llvm::Triple &Triple) 5409 : AArch64TargetInfo(Triple) { } 5410 void getTargetDefines(const LangOptions &Opts, 5411 MacroBuilder &Builder) const override { 5412 Builder.defineMacro("__AARCH64EB__"); 5413 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5414 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5415 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5416 } 5417 }; 5418 5419 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5420 protected: 5421 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5422 MacroBuilder &Builder) const override { 5423 Builder.defineMacro("__AARCH64_SIMD__"); 5424 Builder.defineMacro("__ARM64_ARCH_8__"); 5425 Builder.defineMacro("__ARM_NEON__"); 5426 Builder.defineMacro("__LITTLE_ENDIAN__"); 5427 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5428 Builder.defineMacro("__arm64", "1"); 5429 Builder.defineMacro("__arm64__", "1"); 5430 5431 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5432 } 5433 5434 public: 5435 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5436 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5437 Int64Type = SignedLongLong; 5438 WCharType = SignedInt; 5439 UseSignedCharForObjCBool = false; 5440 5441 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5442 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5443 5444 TheCXXABI.set(TargetCXXABI::iOS64); 5445 } 5446 5447 BuiltinVaListKind getBuiltinVaListKind() const override { 5448 return TargetInfo::CharPtrBuiltinVaList; 5449 } 5450 }; 5451 5452 // Hexagon abstract base class 5453 class HexagonTargetInfo : public TargetInfo { 5454 static const Builtin::Info BuiltinInfo[]; 5455 static const char * const GCCRegNames[]; 5456 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5457 std::string CPU; 5458 public: 5459 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5460 BigEndian = false; 5461 DataLayoutString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 5462 5463 // {} in inline assembly are packet specifiers, not assembly variant 5464 // specifiers. 5465 NoAsmVariants = true; 5466 } 5467 5468 void getTargetBuiltins(const Builtin::Info *&Records, 5469 unsigned &NumRecords) const override { 5470 Records = BuiltinInfo; 5471 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 5472 } 5473 5474 bool validateAsmConstraint(const char *&Name, 5475 TargetInfo::ConstraintInfo &Info) const override { 5476 return true; 5477 } 5478 5479 void getTargetDefines(const LangOptions &Opts, 5480 MacroBuilder &Builder) const override; 5481 5482 bool hasFeature(StringRef Feature) const override { 5483 return Feature == "hexagon"; 5484 } 5485 5486 BuiltinVaListKind getBuiltinVaListKind() const override { 5487 return TargetInfo::CharPtrBuiltinVaList; 5488 } 5489 void getGCCRegNames(const char * const *&Names, 5490 unsigned &NumNames) const override; 5491 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5492 unsigned &NumAliases) const override; 5493 const char *getClobbers() const override { 5494 return ""; 5495 } 5496 5497 static const char *getHexagonCPUSuffix(StringRef Name) { 5498 return llvm::StringSwitch<const char*>(Name) 5499 .Case("hexagonv4", "4") 5500 .Case("hexagonv5", "5") 5501 .Default(nullptr); 5502 } 5503 5504 bool setCPU(const std::string &Name) override { 5505 if (!getHexagonCPUSuffix(Name)) 5506 return false; 5507 5508 CPU = Name; 5509 return true; 5510 } 5511 }; 5512 5513 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5514 MacroBuilder &Builder) const { 5515 Builder.defineMacro("qdsp6"); 5516 Builder.defineMacro("__qdsp6", "1"); 5517 Builder.defineMacro("__qdsp6__", "1"); 5518 5519 Builder.defineMacro("hexagon"); 5520 Builder.defineMacro("__hexagon", "1"); 5521 Builder.defineMacro("__hexagon__", "1"); 5522 5523 if(CPU == "hexagonv1") { 5524 Builder.defineMacro("__HEXAGON_V1__"); 5525 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 5526 if(Opts.HexagonQdsp6Compat) { 5527 Builder.defineMacro("__QDSP6_V1__"); 5528 Builder.defineMacro("__QDSP6_ARCH__", "1"); 5529 } 5530 } 5531 else if(CPU == "hexagonv2") { 5532 Builder.defineMacro("__HEXAGON_V2__"); 5533 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 5534 if(Opts.HexagonQdsp6Compat) { 5535 Builder.defineMacro("__QDSP6_V2__"); 5536 Builder.defineMacro("__QDSP6_ARCH__", "2"); 5537 } 5538 } 5539 else if(CPU == "hexagonv3") { 5540 Builder.defineMacro("__HEXAGON_V3__"); 5541 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 5542 if(Opts.HexagonQdsp6Compat) { 5543 Builder.defineMacro("__QDSP6_V3__"); 5544 Builder.defineMacro("__QDSP6_ARCH__", "3"); 5545 } 5546 } 5547 else if(CPU == "hexagonv4") { 5548 Builder.defineMacro("__HEXAGON_V4__"); 5549 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5550 if(Opts.HexagonQdsp6Compat) { 5551 Builder.defineMacro("__QDSP6_V4__"); 5552 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5553 } 5554 } 5555 else if(CPU == "hexagonv5") { 5556 Builder.defineMacro("__HEXAGON_V5__"); 5557 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5558 if(Opts.HexagonQdsp6Compat) { 5559 Builder.defineMacro("__QDSP6_V5__"); 5560 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5561 } 5562 } 5563 } 5564 5565 const char * const HexagonTargetInfo::GCCRegNames[] = { 5566 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5567 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5568 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5569 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5570 "p0", "p1", "p2", "p3", 5571 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5572 }; 5573 5574 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 5575 unsigned &NumNames) const { 5576 Names = GCCRegNames; 5577 NumNames = llvm::array_lengthof(GCCRegNames); 5578 } 5579 5580 5581 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5582 { { "sp" }, "r29" }, 5583 { { "fp" }, "r30" }, 5584 { { "lr" }, "r31" }, 5585 }; 5586 5587 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5588 unsigned &NumAliases) const { 5589 Aliases = GCCRegAliases; 5590 NumAliases = llvm::array_lengthof(GCCRegAliases); 5591 } 5592 5593 5594 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5595 #define BUILTIN(ID, TYPE, ATTRS) \ 5596 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5597 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5598 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5599 #include "clang/Basic/BuiltinsHexagon.def" 5600 }; 5601 5602 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5603 class SparcTargetInfo : public TargetInfo { 5604 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5605 static const char * const GCCRegNames[]; 5606 bool SoftFloat; 5607 public: 5608 SparcTargetInfo(const llvm::Triple &Triple) 5609 : TargetInfo(Triple), SoftFloat(false) {} 5610 5611 bool handleTargetFeatures(std::vector<std::string> &Features, 5612 DiagnosticsEngine &Diags) override { 5613 // The backend doesn't actually handle soft float yet, but in case someone 5614 // is using the support for the front end continue to support it. 5615 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 5616 if (Feature != Features.end()) { 5617 SoftFloat = true; 5618 Features.erase(Feature); 5619 } 5620 return true; 5621 } 5622 void getTargetDefines(const LangOptions &Opts, 5623 MacroBuilder &Builder) const override { 5624 DefineStd(Builder, "sparc", Opts); 5625 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5626 5627 if (SoftFloat) 5628 Builder.defineMacro("SOFT_FLOAT", "1"); 5629 } 5630 5631 bool hasFeature(StringRef Feature) const override { 5632 return llvm::StringSwitch<bool>(Feature) 5633 .Case("softfloat", SoftFloat) 5634 .Case("sparc", true) 5635 .Default(false); 5636 } 5637 5638 void getTargetBuiltins(const Builtin::Info *&Records, 5639 unsigned &NumRecords) const override { 5640 // FIXME: Implement! 5641 } 5642 BuiltinVaListKind getBuiltinVaListKind() const override { 5643 return TargetInfo::VoidPtrBuiltinVaList; 5644 } 5645 void getGCCRegNames(const char * const *&Names, 5646 unsigned &NumNames) const override; 5647 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5648 unsigned &NumAliases) const override; 5649 bool validateAsmConstraint(const char *&Name, 5650 TargetInfo::ConstraintInfo &info) const override { 5651 // FIXME: Implement! 5652 switch (*Name) { 5653 case 'I': // Signed 13-bit constant 5654 case 'J': // Zero 5655 case 'K': // 32-bit constant with the low 12 bits clear 5656 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5657 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5658 case 'N': // Same as 'K' but zext (required for SIMode) 5659 case 'O': // The constant 4096 5660 return true; 5661 } 5662 return false; 5663 } 5664 const char *getClobbers() const override { 5665 // FIXME: Implement! 5666 return ""; 5667 } 5668 }; 5669 5670 const char * const SparcTargetInfo::GCCRegNames[] = { 5671 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5672 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5673 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5674 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5675 }; 5676 5677 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 5678 unsigned &NumNames) const { 5679 Names = GCCRegNames; 5680 NumNames = llvm::array_lengthof(GCCRegNames); 5681 } 5682 5683 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5684 { { "g0" }, "r0" }, 5685 { { "g1" }, "r1" }, 5686 { { "g2" }, "r2" }, 5687 { { "g3" }, "r3" }, 5688 { { "g4" }, "r4" }, 5689 { { "g5" }, "r5" }, 5690 { { "g6" }, "r6" }, 5691 { { "g7" }, "r7" }, 5692 { { "o0" }, "r8" }, 5693 { { "o1" }, "r9" }, 5694 { { "o2" }, "r10" }, 5695 { { "o3" }, "r11" }, 5696 { { "o4" }, "r12" }, 5697 { { "o5" }, "r13" }, 5698 { { "o6", "sp" }, "r14" }, 5699 { { "o7" }, "r15" }, 5700 { { "l0" }, "r16" }, 5701 { { "l1" }, "r17" }, 5702 { { "l2" }, "r18" }, 5703 { { "l3" }, "r19" }, 5704 { { "l4" }, "r20" }, 5705 { { "l5" }, "r21" }, 5706 { { "l6" }, "r22" }, 5707 { { "l7" }, "r23" }, 5708 { { "i0" }, "r24" }, 5709 { { "i1" }, "r25" }, 5710 { { "i2" }, "r26" }, 5711 { { "i3" }, "r27" }, 5712 { { "i4" }, "r28" }, 5713 { { "i5" }, "r29" }, 5714 { { "i6", "fp" }, "r30" }, 5715 { { "i7" }, "r31" }, 5716 }; 5717 5718 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5719 unsigned &NumAliases) const { 5720 Aliases = GCCRegAliases; 5721 NumAliases = llvm::array_lengthof(GCCRegAliases); 5722 } 5723 5724 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5725 class SparcV8TargetInfo : public SparcTargetInfo { 5726 public: 5727 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5728 DataLayoutString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5729 // NetBSD uses long (same as llvm default); everyone else uses int. 5730 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5731 SizeType = UnsignedLong; 5732 IntPtrType = SignedLong; 5733 PtrDiffType = SignedLong; 5734 } else { 5735 SizeType = UnsignedInt; 5736 IntPtrType = SignedInt; 5737 PtrDiffType = SignedInt; 5738 } 5739 } 5740 5741 void getTargetDefines(const LangOptions &Opts, 5742 MacroBuilder &Builder) const override { 5743 SparcTargetInfo::getTargetDefines(Opts, Builder); 5744 Builder.defineMacro("__sparcv8"); 5745 } 5746 }; 5747 5748 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 5749 class SparcV8elTargetInfo : public SparcV8TargetInfo { 5750 public: 5751 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 5752 DataLayoutString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5753 BigEndian = false; 5754 } 5755 }; 5756 5757 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 5758 class SparcV9TargetInfo : public SparcTargetInfo { 5759 public: 5760 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5761 // FIXME: Support Sparc quad-precision long double? 5762 DataLayoutString = "E-m:e-i64:64-n32:64-S128"; 5763 // This is an LP64 platform. 5764 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5765 5766 // OpenBSD uses long long for int64_t and intmax_t. 5767 if (getTriple().getOS() == llvm::Triple::OpenBSD) 5768 IntMaxType = SignedLongLong; 5769 else 5770 IntMaxType = SignedLong; 5771 Int64Type = IntMaxType; 5772 5773 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 5774 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 5775 LongDoubleWidth = 128; 5776 LongDoubleAlign = 128; 5777 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5778 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5779 } 5780 5781 void getTargetDefines(const LangOptions &Opts, 5782 MacroBuilder &Builder) const override { 5783 SparcTargetInfo::getTargetDefines(Opts, Builder); 5784 Builder.defineMacro("__sparcv9"); 5785 Builder.defineMacro("__arch64__"); 5786 // Solaris doesn't need these variants, but the BSDs do. 5787 if (getTriple().getOS() != llvm::Triple::Solaris) { 5788 Builder.defineMacro("__sparc64__"); 5789 Builder.defineMacro("__sparc_v9__"); 5790 Builder.defineMacro("__sparcv9__"); 5791 } 5792 } 5793 5794 bool setCPU(const std::string &Name) override { 5795 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5796 .Case("v9", true) 5797 .Case("ultrasparc", true) 5798 .Case("ultrasparc3", true) 5799 .Case("niagara", true) 5800 .Case("niagara2", true) 5801 .Case("niagara3", true) 5802 .Case("niagara4", true) 5803 .Default(false); 5804 5805 // No need to store the CPU yet. There aren't any CPU-specific 5806 // macros to define. 5807 return CPUKnown; 5808 } 5809 }; 5810 5811 class SystemZTargetInfo : public TargetInfo { 5812 static const Builtin::Info BuiltinInfo[]; 5813 static const char *const GCCRegNames[]; 5814 std::string CPU; 5815 bool HasTransactionalExecution; 5816 bool HasVector; 5817 5818 public: 5819 SystemZTargetInfo(const llvm::Triple &Triple) 5820 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), HasVector(false) { 5821 IntMaxType = SignedLong; 5822 Int64Type = SignedLong; 5823 TLSSupported = true; 5824 IntWidth = IntAlign = 32; 5825 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5826 PointerWidth = PointerAlign = 64; 5827 LongDoubleWidth = 128; 5828 LongDoubleAlign = 64; 5829 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5830 DefaultAlignForAttributeAligned = 64; 5831 MinGlobalAlign = 16; 5832 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5833 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5834 } 5835 void getTargetDefines(const LangOptions &Opts, 5836 MacroBuilder &Builder) const override { 5837 Builder.defineMacro("__s390__"); 5838 Builder.defineMacro("__s390x__"); 5839 Builder.defineMacro("__zarch__"); 5840 Builder.defineMacro("__LONG_DOUBLE_128__"); 5841 if (HasTransactionalExecution) 5842 Builder.defineMacro("__HTM__"); 5843 if (Opts.ZVector) 5844 Builder.defineMacro("__VEC__", "10301"); 5845 } 5846 void getTargetBuiltins(const Builtin::Info *&Records, 5847 unsigned &NumRecords) const override { 5848 Records = BuiltinInfo; 5849 NumRecords = clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin; 5850 } 5851 5852 void getGCCRegNames(const char *const *&Names, 5853 unsigned &NumNames) const override; 5854 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5855 unsigned &NumAliases) const override { 5856 // No aliases. 5857 Aliases = nullptr; 5858 NumAliases = 0; 5859 } 5860 bool validateAsmConstraint(const char *&Name, 5861 TargetInfo::ConstraintInfo &info) const override; 5862 const char *getClobbers() const override { 5863 // FIXME: Is this really right? 5864 return ""; 5865 } 5866 BuiltinVaListKind getBuiltinVaListKind() const override { 5867 return TargetInfo::SystemZBuiltinVaList; 5868 } 5869 bool setCPU(const std::string &Name) override { 5870 CPU = Name; 5871 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5872 .Case("z10", true) 5873 .Case("z196", true) 5874 .Case("zEC12", true) 5875 .Case("z13", true) 5876 .Default(false); 5877 5878 return CPUKnown; 5879 } 5880 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5881 if (CPU == "zEC12") 5882 Features["transactional-execution"] = true; 5883 if (CPU == "z13") { 5884 Features["transactional-execution"] = true; 5885 Features["vector"] = true; 5886 } 5887 } 5888 5889 bool handleTargetFeatures(std::vector<std::string> &Features, 5890 DiagnosticsEngine &Diags) override { 5891 HasTransactionalExecution = false; 5892 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 5893 if (Features[i] == "+transactional-execution") 5894 HasTransactionalExecution = true; 5895 if (Features[i] == "+vector") 5896 HasVector = true; 5897 } 5898 // If we use the vector ABI, vector types are 64-bit aligned. 5899 if (HasVector) { 5900 MaxVectorAlign = 64; 5901 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 5902 "-v128:64-a:8:16-n32:64"; 5903 } 5904 return true; 5905 } 5906 5907 bool hasFeature(StringRef Feature) const override { 5908 return llvm::StringSwitch<bool>(Feature) 5909 .Case("systemz", true) 5910 .Case("htm", HasTransactionalExecution) 5911 .Case("vx", HasVector) 5912 .Default(false); 5913 } 5914 5915 StringRef getABI() const override { 5916 if (HasVector) 5917 return "vector"; 5918 return ""; 5919 } 5920 5921 bool useFloat128ManglingForLongDouble() const override { 5922 return true; 5923 } 5924 }; 5925 5926 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 5927 #define BUILTIN(ID, TYPE, ATTRS) \ 5928 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5929 #include "clang/Basic/BuiltinsSystemZ.def" 5930 }; 5931 5932 const char *const SystemZTargetInfo::GCCRegNames[] = { 5933 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5934 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5935 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 5936 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 5937 }; 5938 5939 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 5940 unsigned &NumNames) const { 5941 Names = GCCRegNames; 5942 NumNames = llvm::array_lengthof(GCCRegNames); 5943 } 5944 5945 bool SystemZTargetInfo:: 5946 validateAsmConstraint(const char *&Name, 5947 TargetInfo::ConstraintInfo &Info) const { 5948 switch (*Name) { 5949 default: 5950 return false; 5951 5952 case 'a': // Address register 5953 case 'd': // Data register (equivalent to 'r') 5954 case 'f': // Floating-point register 5955 Info.setAllowsRegister(); 5956 return true; 5957 5958 case 'I': // Unsigned 8-bit constant 5959 case 'J': // Unsigned 12-bit constant 5960 case 'K': // Signed 16-bit constant 5961 case 'L': // Signed 20-bit displacement (on all targets we support) 5962 case 'M': // 0x7fffffff 5963 return true; 5964 5965 case 'Q': // Memory with base and unsigned 12-bit displacement 5966 case 'R': // Likewise, plus an index 5967 case 'S': // Memory with base and signed 20-bit displacement 5968 case 'T': // Likewise, plus an index 5969 Info.setAllowsMemory(); 5970 return true; 5971 } 5972 } 5973 5974 class MSP430TargetInfo : public TargetInfo { 5975 static const char * const GCCRegNames[]; 5976 public: 5977 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5978 BigEndian = false; 5979 TLSSupported = false; 5980 IntWidth = 16; IntAlign = 16; 5981 LongWidth = 32; LongLongWidth = 64; 5982 LongAlign = LongLongAlign = 16; 5983 PointerWidth = 16; PointerAlign = 16; 5984 SuitableAlign = 16; 5985 SizeType = UnsignedInt; 5986 IntMaxType = SignedLongLong; 5987 IntPtrType = SignedInt; 5988 PtrDiffType = SignedInt; 5989 SigAtomicType = SignedLong; 5990 DataLayoutString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 5991 } 5992 void getTargetDefines(const LangOptions &Opts, 5993 MacroBuilder &Builder) const override { 5994 Builder.defineMacro("MSP430"); 5995 Builder.defineMacro("__MSP430__"); 5996 // FIXME: defines for different 'flavours' of MCU 5997 } 5998 void getTargetBuiltins(const Builtin::Info *&Records, 5999 unsigned &NumRecords) const override { 6000 // FIXME: Implement. 6001 Records = nullptr; 6002 NumRecords = 0; 6003 } 6004 bool hasFeature(StringRef Feature) const override { 6005 return Feature == "msp430"; 6006 } 6007 void getGCCRegNames(const char * const *&Names, 6008 unsigned &NumNames) const override; 6009 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6010 unsigned &NumAliases) const override { 6011 // No aliases. 6012 Aliases = nullptr; 6013 NumAliases = 0; 6014 } 6015 bool 6016 validateAsmConstraint(const char *&Name, 6017 TargetInfo::ConstraintInfo &info) const override { 6018 // FIXME: implement 6019 switch (*Name) { 6020 case 'K': // the constant 1 6021 case 'L': // constant -1^20 .. 1^19 6022 case 'M': // constant 1-4: 6023 return true; 6024 } 6025 // No target constraints for now. 6026 return false; 6027 } 6028 const char *getClobbers() const override { 6029 // FIXME: Is this really right? 6030 return ""; 6031 } 6032 BuiltinVaListKind getBuiltinVaListKind() const override { 6033 // FIXME: implement 6034 return TargetInfo::CharPtrBuiltinVaList; 6035 } 6036 }; 6037 6038 const char * const MSP430TargetInfo::GCCRegNames[] = { 6039 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6040 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 6041 }; 6042 6043 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 6044 unsigned &NumNames) const { 6045 Names = GCCRegNames; 6046 NumNames = llvm::array_lengthof(GCCRegNames); 6047 } 6048 6049 // LLVM and Clang cannot be used directly to output native binaries for 6050 // target, but is used to compile C code to llvm bitcode with correct 6051 // type and alignment information. 6052 // 6053 // TCE uses the llvm bitcode as input and uses it for generating customized 6054 // target processor and program binary. TCE co-design environment is 6055 // publicly available in http://tce.cs.tut.fi 6056 6057 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6058 3, // opencl_global 6059 4, // opencl_local 6060 5, // opencl_constant 6061 // FIXME: generic has to be added to the target 6062 0, // opencl_generic 6063 0, // cuda_device 6064 0, // cuda_constant 6065 0 // cuda_shared 6066 }; 6067 6068 class TCETargetInfo : public TargetInfo{ 6069 public: 6070 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6071 TLSSupported = false; 6072 IntWidth = 32; 6073 LongWidth = LongLongWidth = 32; 6074 PointerWidth = 32; 6075 IntAlign = 32; 6076 LongAlign = LongLongAlign = 32; 6077 PointerAlign = 32; 6078 SuitableAlign = 32; 6079 SizeType = UnsignedInt; 6080 IntMaxType = SignedLong; 6081 IntPtrType = SignedInt; 6082 PtrDiffType = SignedInt; 6083 FloatWidth = 32; 6084 FloatAlign = 32; 6085 DoubleWidth = 32; 6086 DoubleAlign = 32; 6087 LongDoubleWidth = 32; 6088 LongDoubleAlign = 32; 6089 FloatFormat = &llvm::APFloat::IEEEsingle; 6090 DoubleFormat = &llvm::APFloat::IEEEsingle; 6091 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6092 DataLayoutString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 6093 "-f64:32-v64:32-v128:32-a:0:32-n32"; 6094 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6095 UseAddrSpaceMapMangling = true; 6096 } 6097 6098 void getTargetDefines(const LangOptions &Opts, 6099 MacroBuilder &Builder) const override { 6100 DefineStd(Builder, "tce", Opts); 6101 Builder.defineMacro("__TCE__"); 6102 Builder.defineMacro("__TCE_V1__"); 6103 } 6104 bool hasFeature(StringRef Feature) const override { 6105 return Feature == "tce"; 6106 } 6107 6108 void getTargetBuiltins(const Builtin::Info *&Records, 6109 unsigned &NumRecords) const override {} 6110 const char *getClobbers() const override { 6111 return ""; 6112 } 6113 BuiltinVaListKind getBuiltinVaListKind() const override { 6114 return TargetInfo::VoidPtrBuiltinVaList; 6115 } 6116 void getGCCRegNames(const char * const *&Names, 6117 unsigned &NumNames) const override {} 6118 bool validateAsmConstraint(const char *&Name, 6119 TargetInfo::ConstraintInfo &info) const override{ 6120 return true; 6121 } 6122 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6123 unsigned &NumAliases) const override {} 6124 }; 6125 6126 class BPFTargetInfo : public TargetInfo { 6127 public: 6128 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6129 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6130 SizeType = UnsignedLong; 6131 PtrDiffType = SignedLong; 6132 IntPtrType = SignedLong; 6133 IntMaxType = SignedLong; 6134 Int64Type = SignedLong; 6135 RegParmMax = 5; 6136 if (Triple.getArch() == llvm::Triple::bpfeb) { 6137 BigEndian = true; 6138 DataLayoutString = "E-m:e-p:64:64-i64:64-n32:64-S128"; 6139 } else { 6140 BigEndian = false; 6141 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 6142 } 6143 MaxAtomicPromoteWidth = 64; 6144 MaxAtomicInlineWidth = 64; 6145 TLSSupported = false; 6146 } 6147 void getTargetDefines(const LangOptions &Opts, 6148 MacroBuilder &Builder) const override { 6149 DefineStd(Builder, "bpf", Opts); 6150 Builder.defineMacro("__BPF__"); 6151 } 6152 bool hasFeature(StringRef Feature) const override { 6153 return Feature == "bpf"; 6154 } 6155 6156 void getTargetBuiltins(const Builtin::Info *&Records, 6157 unsigned &NumRecords) const override {} 6158 const char *getClobbers() const override { 6159 return ""; 6160 } 6161 BuiltinVaListKind getBuiltinVaListKind() const override { 6162 return TargetInfo::VoidPtrBuiltinVaList; 6163 } 6164 void getGCCRegNames(const char * const *&Names, 6165 unsigned &NumNames) const override { 6166 Names = nullptr; 6167 NumNames = 0; 6168 } 6169 bool validateAsmConstraint(const char *&Name, 6170 TargetInfo::ConstraintInfo &info) const override { 6171 return true; 6172 } 6173 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6174 unsigned &NumAliases) const override { 6175 Aliases = nullptr; 6176 NumAliases = 0; 6177 } 6178 }; 6179 6180 class MipsTargetInfoBase : public TargetInfo { 6181 virtual void setDataLayoutString() = 0; 6182 6183 static const Builtin::Info BuiltinInfo[]; 6184 std::string CPU; 6185 bool IsMips16; 6186 bool IsMicromips; 6187 bool IsNan2008; 6188 bool IsSingleFloat; 6189 enum MipsFloatABI { 6190 HardFloat, SoftFloat 6191 } FloatABI; 6192 enum DspRevEnum { 6193 NoDSP, DSP1, DSP2 6194 } DspRev; 6195 bool HasMSA; 6196 6197 protected: 6198 bool HasFP64; 6199 std::string ABI; 6200 6201 public: 6202 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 6203 const std::string &CPUStr) 6204 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6205 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6206 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6207 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6208 } 6209 6210 bool isNaN2008Default() const { 6211 return CPU == "mips32r6" || CPU == "mips64r6"; 6212 } 6213 6214 bool isFP64Default() const { 6215 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6216 } 6217 6218 bool isNan2008() const override { 6219 return IsNan2008; 6220 } 6221 6222 StringRef getABI() const override { return ABI; } 6223 bool setCPU(const std::string &Name) override { 6224 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6225 getTriple().getArch() == llvm::Triple::mipsel; 6226 CPU = Name; 6227 return llvm::StringSwitch<bool>(Name) 6228 .Case("mips1", IsMips32) 6229 .Case("mips2", IsMips32) 6230 .Case("mips3", true) 6231 .Case("mips4", true) 6232 .Case("mips5", true) 6233 .Case("mips32", IsMips32) 6234 .Case("mips32r2", IsMips32) 6235 .Case("mips32r3", IsMips32) 6236 .Case("mips32r5", IsMips32) 6237 .Case("mips32r6", IsMips32) 6238 .Case("mips64", true) 6239 .Case("mips64r2", true) 6240 .Case("mips64r3", true) 6241 .Case("mips64r5", true) 6242 .Case("mips64r6", true) 6243 .Case("octeon", true) 6244 .Default(false); 6245 } 6246 const std::string& getCPU() const { return CPU; } 6247 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 6248 if (CPU == "octeon") 6249 Features["mips64r2"] = Features["cnmips"] = true; 6250 else 6251 Features[CPU] = true; 6252 } 6253 6254 void getTargetDefines(const LangOptions &Opts, 6255 MacroBuilder &Builder) const override { 6256 Builder.defineMacro("__mips__"); 6257 Builder.defineMacro("_mips"); 6258 if (Opts.GNUMode) 6259 Builder.defineMacro("mips"); 6260 6261 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6262 6263 switch (FloatABI) { 6264 case HardFloat: 6265 Builder.defineMacro("__mips_hard_float", Twine(1)); 6266 break; 6267 case SoftFloat: 6268 Builder.defineMacro("__mips_soft_float", Twine(1)); 6269 break; 6270 } 6271 6272 if (IsSingleFloat) 6273 Builder.defineMacro("__mips_single_float", Twine(1)); 6274 6275 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6276 Builder.defineMacro("_MIPS_FPSET", 6277 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6278 6279 if (IsMips16) 6280 Builder.defineMacro("__mips16", Twine(1)); 6281 6282 if (IsMicromips) 6283 Builder.defineMacro("__mips_micromips", Twine(1)); 6284 6285 if (IsNan2008) 6286 Builder.defineMacro("__mips_nan2008", Twine(1)); 6287 6288 switch (DspRev) { 6289 default: 6290 break; 6291 case DSP1: 6292 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6293 Builder.defineMacro("__mips_dsp", Twine(1)); 6294 break; 6295 case DSP2: 6296 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6297 Builder.defineMacro("__mips_dspr2", Twine(1)); 6298 Builder.defineMacro("__mips_dsp", Twine(1)); 6299 break; 6300 } 6301 6302 if (HasMSA) 6303 Builder.defineMacro("__mips_msa", Twine(1)); 6304 6305 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6306 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6307 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6308 6309 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6310 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6311 } 6312 6313 void getTargetBuiltins(const Builtin::Info *&Records, 6314 unsigned &NumRecords) const override { 6315 Records = BuiltinInfo; 6316 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 6317 } 6318 bool hasFeature(StringRef Feature) const override { 6319 return llvm::StringSwitch<bool>(Feature) 6320 .Case("mips", true) 6321 .Case("fp64", HasFP64) 6322 .Default(false); 6323 } 6324 BuiltinVaListKind getBuiltinVaListKind() const override { 6325 return TargetInfo::VoidPtrBuiltinVaList; 6326 } 6327 void getGCCRegNames(const char * const *&Names, 6328 unsigned &NumNames) const override { 6329 static const char *const GCCRegNames[] = { 6330 // CPU register names 6331 // Must match second column of GCCRegAliases 6332 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6333 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6334 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6335 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6336 // Floating point register names 6337 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6338 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6339 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6340 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6341 // Hi/lo and condition register names 6342 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6343 "$fcc5","$fcc6","$fcc7", 6344 // MSA register names 6345 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6346 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6347 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6348 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6349 // MSA control register names 6350 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6351 "$msarequest", "$msamap", "$msaunmap" 6352 }; 6353 Names = GCCRegNames; 6354 NumNames = llvm::array_lengthof(GCCRegNames); 6355 } 6356 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6357 unsigned &NumAliases) const override = 0; 6358 bool validateAsmConstraint(const char *&Name, 6359 TargetInfo::ConstraintInfo &Info) const override { 6360 switch (*Name) { 6361 default: 6362 return false; 6363 case 'r': // CPU registers. 6364 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6365 case 'y': // Equivalent to "r", backward compatibility only. 6366 case 'f': // floating-point registers. 6367 case 'c': // $25 for indirect jumps 6368 case 'l': // lo register 6369 case 'x': // hilo register pair 6370 Info.setAllowsRegister(); 6371 return true; 6372 case 'I': // Signed 16-bit constant 6373 case 'J': // Integer 0 6374 case 'K': // Unsigned 16-bit constant 6375 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6376 case 'M': // Constants not loadable via lui, addiu, or ori 6377 case 'N': // Constant -1 to -65535 6378 case 'O': // A signed 15-bit constant 6379 case 'P': // A constant between 1 go 65535 6380 return true; 6381 case 'R': // An address that can be used in a non-macro load or store 6382 Info.setAllowsMemory(); 6383 return true; 6384 case 'Z': 6385 if (Name[1] == 'C') { // An address usable by ll, and sc. 6386 Info.setAllowsMemory(); 6387 Name++; // Skip over 'Z'. 6388 return true; 6389 } 6390 return false; 6391 } 6392 } 6393 6394 std::string convertConstraint(const char *&Constraint) const override { 6395 std::string R; 6396 switch (*Constraint) { 6397 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6398 if (Constraint[1] == 'C') { 6399 R = std::string("^") + std::string(Constraint, 2); 6400 Constraint++; 6401 return R; 6402 } 6403 break; 6404 } 6405 return TargetInfo::convertConstraint(Constraint); 6406 } 6407 6408 const char *getClobbers() const override { 6409 // In GCC, $1 is not widely used in generated code (it's used only in a few 6410 // specific situations), so there is no real need for users to add it to 6411 // the clobbers list if they want to use it in their inline assembly code. 6412 // 6413 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6414 // code generation, so using it in inline assembly without adding it to the 6415 // clobbers list can cause conflicts between the inline assembly code and 6416 // the surrounding generated code. 6417 // 6418 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6419 // operands, which will conflict with the ".set at" assembler option (which 6420 // we use only for inline assembly, in order to maintain compatibility with 6421 // GCC) and will also conflict with the user's usage of $1. 6422 // 6423 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6424 // register for generated code is to automatically clobber $1 for all inline 6425 // assembly code. 6426 // 6427 // FIXME: We should automatically clobber $1 only for inline assembly code 6428 // which actually uses it. This would allow LLVM to use $1 for inline 6429 // assembly operands if the user's assembly code doesn't use it. 6430 return "~{$1}"; 6431 } 6432 6433 bool handleTargetFeatures(std::vector<std::string> &Features, 6434 DiagnosticsEngine &Diags) override { 6435 IsMips16 = false; 6436 IsMicromips = false; 6437 IsNan2008 = isNaN2008Default(); 6438 IsSingleFloat = false; 6439 FloatABI = HardFloat; 6440 DspRev = NoDSP; 6441 HasFP64 = isFP64Default(); 6442 6443 for (std::vector<std::string>::iterator it = Features.begin(), 6444 ie = Features.end(); it != ie; ++it) { 6445 if (*it == "+single-float") 6446 IsSingleFloat = true; 6447 else if (*it == "+soft-float") 6448 FloatABI = SoftFloat; 6449 else if (*it == "+mips16") 6450 IsMips16 = true; 6451 else if (*it == "+micromips") 6452 IsMicromips = true; 6453 else if (*it == "+dsp") 6454 DspRev = std::max(DspRev, DSP1); 6455 else if (*it == "+dspr2") 6456 DspRev = std::max(DspRev, DSP2); 6457 else if (*it == "+msa") 6458 HasMSA = true; 6459 else if (*it == "+fp64") 6460 HasFP64 = true; 6461 else if (*it == "-fp64") 6462 HasFP64 = false; 6463 else if (*it == "+nan2008") 6464 IsNan2008 = true; 6465 else if (*it == "-nan2008") 6466 IsNan2008 = false; 6467 } 6468 6469 setDataLayoutString(); 6470 6471 return true; 6472 } 6473 6474 int getEHDataRegisterNumber(unsigned RegNo) const override { 6475 if (RegNo == 0) return 4; 6476 if (RegNo == 1) return 5; 6477 return -1; 6478 } 6479 6480 bool isCLZForZeroUndef() const override { return false; } 6481 }; 6482 6483 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 6484 #define BUILTIN(ID, TYPE, ATTRS) \ 6485 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6486 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6487 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6488 #include "clang/Basic/BuiltinsMips.def" 6489 }; 6490 6491 class Mips32TargetInfoBase : public MipsTargetInfoBase { 6492 public: 6493 Mips32TargetInfoBase(const llvm::Triple &Triple) 6494 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 6495 SizeType = UnsignedInt; 6496 PtrDiffType = SignedInt; 6497 Int64Type = SignedLongLong; 6498 IntMaxType = Int64Type; 6499 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 6500 } 6501 bool setABI(const std::string &Name) override { 6502 if (Name == "o32" || Name == "eabi") { 6503 ABI = Name; 6504 return true; 6505 } 6506 return false; 6507 } 6508 void getTargetDefines(const LangOptions &Opts, 6509 MacroBuilder &Builder) const override { 6510 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6511 6512 Builder.defineMacro("__mips", "32"); 6513 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 6514 6515 const std::string& CPUStr = getCPU(); 6516 if (CPUStr == "mips32") 6517 Builder.defineMacro("__mips_isa_rev", "1"); 6518 else if (CPUStr == "mips32r2") 6519 Builder.defineMacro("__mips_isa_rev", "2"); 6520 else if (CPUStr == "mips32r3") 6521 Builder.defineMacro("__mips_isa_rev", "3"); 6522 else if (CPUStr == "mips32r5") 6523 Builder.defineMacro("__mips_isa_rev", "5"); 6524 else if (CPUStr == "mips32r6") 6525 Builder.defineMacro("__mips_isa_rev", "6"); 6526 6527 if (ABI == "o32") { 6528 Builder.defineMacro("__mips_o32"); 6529 Builder.defineMacro("_ABIO32", "1"); 6530 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6531 } 6532 else if (ABI == "eabi") 6533 Builder.defineMacro("__mips_eabi"); 6534 else 6535 llvm_unreachable("Invalid ABI for Mips32."); 6536 } 6537 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6538 unsigned &NumAliases) const override { 6539 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6540 { { "at" }, "$1" }, 6541 { { "v0" }, "$2" }, 6542 { { "v1" }, "$3" }, 6543 { { "a0" }, "$4" }, 6544 { { "a1" }, "$5" }, 6545 { { "a2" }, "$6" }, 6546 { { "a3" }, "$7" }, 6547 { { "t0" }, "$8" }, 6548 { { "t1" }, "$9" }, 6549 { { "t2" }, "$10" }, 6550 { { "t3" }, "$11" }, 6551 { { "t4" }, "$12" }, 6552 { { "t5" }, "$13" }, 6553 { { "t6" }, "$14" }, 6554 { { "t7" }, "$15" }, 6555 { { "s0" }, "$16" }, 6556 { { "s1" }, "$17" }, 6557 { { "s2" }, "$18" }, 6558 { { "s3" }, "$19" }, 6559 { { "s4" }, "$20" }, 6560 { { "s5" }, "$21" }, 6561 { { "s6" }, "$22" }, 6562 { { "s7" }, "$23" }, 6563 { { "t8" }, "$24" }, 6564 { { "t9" }, "$25" }, 6565 { { "k0" }, "$26" }, 6566 { { "k1" }, "$27" }, 6567 { { "gp" }, "$28" }, 6568 { { "sp","$sp" }, "$29" }, 6569 { { "fp","$fp" }, "$30" }, 6570 { { "ra" }, "$31" } 6571 }; 6572 Aliases = GCCRegAliases; 6573 NumAliases = llvm::array_lengthof(GCCRegAliases); 6574 } 6575 }; 6576 6577 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6578 void setDataLayoutString() override { 6579 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6580 } 6581 6582 public: 6583 Mips32EBTargetInfo(const llvm::Triple &Triple) 6584 : Mips32TargetInfoBase(Triple) { 6585 } 6586 void getTargetDefines(const LangOptions &Opts, 6587 MacroBuilder &Builder) const override { 6588 DefineStd(Builder, "MIPSEB", Opts); 6589 Builder.defineMacro("_MIPSEB"); 6590 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6591 } 6592 }; 6593 6594 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6595 void setDataLayoutString() override { 6596 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6597 } 6598 6599 public: 6600 Mips32ELTargetInfo(const llvm::Triple &Triple) 6601 : Mips32TargetInfoBase(Triple) { 6602 BigEndian = false; 6603 } 6604 void getTargetDefines(const LangOptions &Opts, 6605 MacroBuilder &Builder) const override { 6606 DefineStd(Builder, "MIPSEL", Opts); 6607 Builder.defineMacro("_MIPSEL"); 6608 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6609 } 6610 }; 6611 6612 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6613 public: 6614 Mips64TargetInfoBase(const llvm::Triple &Triple) 6615 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6616 LongDoubleWidth = LongDoubleAlign = 128; 6617 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6618 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6619 LongDoubleWidth = LongDoubleAlign = 64; 6620 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6621 } 6622 setN64ABITypes(); 6623 SuitableAlign = 128; 6624 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6625 } 6626 6627 void setN64ABITypes() { 6628 LongWidth = LongAlign = 64; 6629 PointerWidth = PointerAlign = 64; 6630 SizeType = UnsignedLong; 6631 PtrDiffType = SignedLong; 6632 Int64Type = SignedLong; 6633 IntMaxType = Int64Type; 6634 } 6635 6636 void setN32ABITypes() { 6637 LongWidth = LongAlign = 32; 6638 PointerWidth = PointerAlign = 32; 6639 SizeType = UnsignedInt; 6640 PtrDiffType = SignedInt; 6641 Int64Type = SignedLongLong; 6642 IntMaxType = Int64Type; 6643 } 6644 6645 bool setABI(const std::string &Name) override { 6646 if (Name == "n32") { 6647 setN32ABITypes(); 6648 ABI = Name; 6649 return true; 6650 } 6651 if (Name == "n64") { 6652 setN64ABITypes(); 6653 ABI = Name; 6654 return true; 6655 } 6656 return false; 6657 } 6658 6659 void getTargetDefines(const LangOptions &Opts, 6660 MacroBuilder &Builder) const override { 6661 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6662 6663 Builder.defineMacro("__mips", "64"); 6664 Builder.defineMacro("__mips64"); 6665 Builder.defineMacro("__mips64__"); 6666 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 6667 6668 const std::string& CPUStr = getCPU(); 6669 if (CPUStr == "mips64") 6670 Builder.defineMacro("__mips_isa_rev", "1"); 6671 else if (CPUStr == "mips64r2") 6672 Builder.defineMacro("__mips_isa_rev", "2"); 6673 else if (CPUStr == "mips64r3") 6674 Builder.defineMacro("__mips_isa_rev", "3"); 6675 else if (CPUStr == "mips64r5") 6676 Builder.defineMacro("__mips_isa_rev", "5"); 6677 else if (CPUStr == "mips64r6") 6678 Builder.defineMacro("__mips_isa_rev", "6"); 6679 6680 if (ABI == "n32") { 6681 Builder.defineMacro("__mips_n32"); 6682 Builder.defineMacro("_ABIN32", "2"); 6683 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 6684 } 6685 else if (ABI == "n64") { 6686 Builder.defineMacro("__mips_n64"); 6687 Builder.defineMacro("_ABI64", "3"); 6688 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 6689 } 6690 else 6691 llvm_unreachable("Invalid ABI for Mips64."); 6692 } 6693 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6694 unsigned &NumAliases) const override { 6695 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6696 { { "at" }, "$1" }, 6697 { { "v0" }, "$2" }, 6698 { { "v1" }, "$3" }, 6699 { { "a0" }, "$4" }, 6700 { { "a1" }, "$5" }, 6701 { { "a2" }, "$6" }, 6702 { { "a3" }, "$7" }, 6703 { { "a4" }, "$8" }, 6704 { { "a5" }, "$9" }, 6705 { { "a6" }, "$10" }, 6706 { { "a7" }, "$11" }, 6707 { { "t0" }, "$12" }, 6708 { { "t1" }, "$13" }, 6709 { { "t2" }, "$14" }, 6710 { { "t3" }, "$15" }, 6711 { { "s0" }, "$16" }, 6712 { { "s1" }, "$17" }, 6713 { { "s2" }, "$18" }, 6714 { { "s3" }, "$19" }, 6715 { { "s4" }, "$20" }, 6716 { { "s5" }, "$21" }, 6717 { { "s6" }, "$22" }, 6718 { { "s7" }, "$23" }, 6719 { { "t8" }, "$24" }, 6720 { { "t9" }, "$25" }, 6721 { { "k0" }, "$26" }, 6722 { { "k1" }, "$27" }, 6723 { { "gp" }, "$28" }, 6724 { { "sp","$sp" }, "$29" }, 6725 { { "fp","$fp" }, "$30" }, 6726 { { "ra" }, "$31" } 6727 }; 6728 Aliases = GCCRegAliases; 6729 NumAliases = llvm::array_lengthof(GCCRegAliases); 6730 } 6731 6732 bool hasInt128Type() const override { return true; } 6733 }; 6734 6735 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 6736 void setDataLayoutString() override { 6737 if (ABI == "n32") 6738 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6739 else 6740 DataLayoutString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6741 6742 } 6743 6744 public: 6745 Mips64EBTargetInfo(const llvm::Triple &Triple) 6746 : Mips64TargetInfoBase(Triple) {} 6747 void getTargetDefines(const LangOptions &Opts, 6748 MacroBuilder &Builder) const override { 6749 DefineStd(Builder, "MIPSEB", Opts); 6750 Builder.defineMacro("_MIPSEB"); 6751 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6752 } 6753 }; 6754 6755 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 6756 void setDataLayoutString() override { 6757 if (ABI == "n32") 6758 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6759 else 6760 DataLayoutString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6761 } 6762 public: 6763 Mips64ELTargetInfo(const llvm::Triple &Triple) 6764 : Mips64TargetInfoBase(Triple) { 6765 // Default ABI is n64. 6766 BigEndian = false; 6767 } 6768 void getTargetDefines(const LangOptions &Opts, 6769 MacroBuilder &Builder) const override { 6770 DefineStd(Builder, "MIPSEL", Opts); 6771 Builder.defineMacro("_MIPSEL"); 6772 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6773 } 6774 }; 6775 6776 class PNaClTargetInfo : public TargetInfo { 6777 public: 6778 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6779 BigEndian = false; 6780 this->UserLabelPrefix = ""; 6781 this->LongAlign = 32; 6782 this->LongWidth = 32; 6783 this->PointerAlign = 32; 6784 this->PointerWidth = 32; 6785 this->IntMaxType = TargetInfo::SignedLongLong; 6786 this->Int64Type = TargetInfo::SignedLongLong; 6787 this->DoubleAlign = 64; 6788 this->LongDoubleWidth = 64; 6789 this->LongDoubleAlign = 64; 6790 this->SizeType = TargetInfo::UnsignedInt; 6791 this->PtrDiffType = TargetInfo::SignedInt; 6792 this->IntPtrType = TargetInfo::SignedInt; 6793 this->RegParmMax = 0; // Disallow regparm 6794 } 6795 6796 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 6797 } 6798 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 6799 Builder.defineMacro("__le32__"); 6800 Builder.defineMacro("__pnacl__"); 6801 } 6802 void getTargetDefines(const LangOptions &Opts, 6803 MacroBuilder &Builder) const override { 6804 getArchDefines(Opts, Builder); 6805 } 6806 bool hasFeature(StringRef Feature) const override { 6807 return Feature == "pnacl"; 6808 } 6809 void getTargetBuiltins(const Builtin::Info *&Records, 6810 unsigned &NumRecords) const override { 6811 } 6812 BuiltinVaListKind getBuiltinVaListKind() const override { 6813 return TargetInfo::PNaClABIBuiltinVaList; 6814 } 6815 void getGCCRegNames(const char * const *&Names, 6816 unsigned &NumNames) const override; 6817 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6818 unsigned &NumAliases) const override; 6819 bool validateAsmConstraint(const char *&Name, 6820 TargetInfo::ConstraintInfo &Info) const override { 6821 return false; 6822 } 6823 6824 const char *getClobbers() const override { 6825 return ""; 6826 } 6827 }; 6828 6829 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 6830 unsigned &NumNames) const { 6831 Names = nullptr; 6832 NumNames = 0; 6833 } 6834 6835 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 6836 unsigned &NumAliases) const { 6837 Aliases = nullptr; 6838 NumAliases = 0; 6839 } 6840 6841 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 6842 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 6843 public: 6844 NaClMips32ELTargetInfo(const llvm::Triple &Triple) : 6845 Mips32ELTargetInfo(Triple) { 6846 } 6847 6848 BuiltinVaListKind getBuiltinVaListKind() const override { 6849 return TargetInfo::PNaClABIBuiltinVaList; 6850 } 6851 }; 6852 6853 class Le64TargetInfo : public TargetInfo { 6854 static const Builtin::Info BuiltinInfo[]; 6855 6856 public: 6857 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6858 BigEndian = false; 6859 NoAsmVariants = true; 6860 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6861 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6862 DataLayoutString = "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 6863 } 6864 6865 void getTargetDefines(const LangOptions &Opts, 6866 MacroBuilder &Builder) const override { 6867 DefineStd(Builder, "unix", Opts); 6868 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 6869 Builder.defineMacro("__ELF__"); 6870 } 6871 void getTargetBuiltins(const Builtin::Info *&Records, 6872 unsigned &NumRecords) const override { 6873 Records = BuiltinInfo; 6874 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin; 6875 } 6876 BuiltinVaListKind getBuiltinVaListKind() const override { 6877 return TargetInfo::PNaClABIBuiltinVaList; 6878 } 6879 const char *getClobbers() const override { return ""; } 6880 void getGCCRegNames(const char *const *&Names, 6881 unsigned &NumNames) const override { 6882 Names = nullptr; 6883 NumNames = 0; 6884 } 6885 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6886 unsigned &NumAliases) const override { 6887 Aliases = nullptr; 6888 NumAliases = 0; 6889 } 6890 bool validateAsmConstraint(const char *&Name, 6891 TargetInfo::ConstraintInfo &Info) const override { 6892 return false; 6893 } 6894 6895 bool hasProtectedVisibility() const override { return false; } 6896 }; 6897 } // end anonymous namespace. 6898 6899 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 6900 #define BUILTIN(ID, TYPE, ATTRS) \ 6901 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6902 #include "clang/Basic/BuiltinsLe64.def" 6903 }; 6904 6905 namespace { 6906 static const unsigned SPIRAddrSpaceMap[] = { 6907 1, // opencl_global 6908 3, // opencl_local 6909 2, // opencl_constant 6910 4, // opencl_generic 6911 0, // cuda_device 6912 0, // cuda_constant 6913 0 // cuda_shared 6914 }; 6915 class SPIRTargetInfo : public TargetInfo { 6916 public: 6917 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6918 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 6919 "SPIR target must use unknown OS"); 6920 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 6921 "SPIR target must use unknown environment type"); 6922 BigEndian = false; 6923 TLSSupported = false; 6924 LongWidth = LongAlign = 64; 6925 AddrSpaceMap = &SPIRAddrSpaceMap; 6926 UseAddrSpaceMapMangling = true; 6927 // Define available target features 6928 // These must be defined in sorted order! 6929 NoAsmVariants = true; 6930 } 6931 void getTargetDefines(const LangOptions &Opts, 6932 MacroBuilder &Builder) const override { 6933 DefineStd(Builder, "SPIR", Opts); 6934 } 6935 bool hasFeature(StringRef Feature) const override { 6936 return Feature == "spir"; 6937 } 6938 6939 void getTargetBuiltins(const Builtin::Info *&Records, 6940 unsigned &NumRecords) const override {} 6941 const char *getClobbers() const override { 6942 return ""; 6943 } 6944 void getGCCRegNames(const char * const *&Names, 6945 unsigned &NumNames) const override {} 6946 bool 6947 validateAsmConstraint(const char *&Name, 6948 TargetInfo::ConstraintInfo &info) const override { 6949 return true; 6950 } 6951 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6952 unsigned &NumAliases) const override {} 6953 BuiltinVaListKind getBuiltinVaListKind() const override { 6954 return TargetInfo::VoidPtrBuiltinVaList; 6955 } 6956 6957 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6958 return (CC == CC_SpirFunction || 6959 CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning; 6960 } 6961 6962 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 6963 return CC_SpirFunction; 6964 } 6965 }; 6966 6967 6968 class SPIR32TargetInfo : public SPIRTargetInfo { 6969 public: 6970 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6971 PointerWidth = PointerAlign = 32; 6972 SizeType = TargetInfo::UnsignedInt; 6973 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 6974 DataLayoutString = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 6975 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6976 } 6977 void getTargetDefines(const LangOptions &Opts, 6978 MacroBuilder &Builder) const override { 6979 DefineStd(Builder, "SPIR32", Opts); 6980 } 6981 }; 6982 6983 class SPIR64TargetInfo : public SPIRTargetInfo { 6984 public: 6985 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6986 PointerWidth = PointerAlign = 64; 6987 SizeType = TargetInfo::UnsignedLong; 6988 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 6989 DataLayoutString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 6990 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6991 } 6992 void getTargetDefines(const LangOptions &Opts, 6993 MacroBuilder &Builder) const override { 6994 DefineStd(Builder, "SPIR64", Opts); 6995 } 6996 }; 6997 6998 class XCoreTargetInfo : public TargetInfo { 6999 static const Builtin::Info BuiltinInfo[]; 7000 public: 7001 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7002 BigEndian = false; 7003 NoAsmVariants = true; 7004 LongLongAlign = 32; 7005 SuitableAlign = 32; 7006 DoubleAlign = LongDoubleAlign = 32; 7007 SizeType = UnsignedInt; 7008 PtrDiffType = SignedInt; 7009 IntPtrType = SignedInt; 7010 WCharType = UnsignedChar; 7011 WIntType = UnsignedInt; 7012 UseZeroLengthBitfieldAlignment = true; 7013 DataLayoutString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7014 "-f64:32-a:0:32-n32"; 7015 } 7016 void getTargetDefines(const LangOptions &Opts, 7017 MacroBuilder &Builder) const override { 7018 Builder.defineMacro("__XS1B__"); 7019 } 7020 void getTargetBuiltins(const Builtin::Info *&Records, 7021 unsigned &NumRecords) const override { 7022 Records = BuiltinInfo; 7023 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 7024 } 7025 BuiltinVaListKind getBuiltinVaListKind() const override { 7026 return TargetInfo::VoidPtrBuiltinVaList; 7027 } 7028 const char *getClobbers() const override { 7029 return ""; 7030 } 7031 void getGCCRegNames(const char * const *&Names, 7032 unsigned &NumNames) const override { 7033 static const char * const GCCRegNames[] = { 7034 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7035 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 7036 }; 7037 Names = GCCRegNames; 7038 NumNames = llvm::array_lengthof(GCCRegNames); 7039 } 7040 void getGCCRegAliases(const GCCRegAlias *&Aliases, 7041 unsigned &NumAliases) const override { 7042 Aliases = nullptr; 7043 NumAliases = 0; 7044 } 7045 bool validateAsmConstraint(const char *&Name, 7046 TargetInfo::ConstraintInfo &Info) const override { 7047 return false; 7048 } 7049 int getEHDataRegisterNumber(unsigned RegNo) const override { 7050 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7051 return (RegNo < 2)? RegNo : -1; 7052 } 7053 }; 7054 7055 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7056 #define BUILTIN(ID, TYPE, ATTRS) \ 7057 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7058 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7059 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7060 #include "clang/Basic/BuiltinsXCore.def" 7061 }; 7062 } // end anonymous namespace. 7063 7064 namespace { 7065 // x86_32 Android target 7066 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7067 public: 7068 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 7069 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 7070 SuitableAlign = 32; 7071 LongDoubleWidth = 64; 7072 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7073 } 7074 }; 7075 } // end anonymous namespace 7076 7077 namespace { 7078 // x86_64 Android target 7079 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7080 public: 7081 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 7082 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 7083 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7084 } 7085 7086 bool useFloat128ManglingForLongDouble() const override { 7087 return true; 7088 } 7089 }; 7090 } // end anonymous namespace 7091 7092 7093 //===----------------------------------------------------------------------===// 7094 // Driver code 7095 //===----------------------------------------------------------------------===// 7096 7097 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 7098 llvm::Triple::OSType os = Triple.getOS(); 7099 7100 switch (Triple.getArch()) { 7101 default: 7102 return nullptr; 7103 7104 case llvm::Triple::xcore: 7105 return new XCoreTargetInfo(Triple); 7106 7107 case llvm::Triple::hexagon: 7108 return new HexagonTargetInfo(Triple); 7109 7110 case llvm::Triple::aarch64: 7111 if (Triple.isOSDarwin()) 7112 return new DarwinAArch64TargetInfo(Triple); 7113 7114 switch (os) { 7115 case llvm::Triple::FreeBSD: 7116 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 7117 case llvm::Triple::Linux: 7118 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 7119 case llvm::Triple::NetBSD: 7120 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 7121 default: 7122 return new AArch64leTargetInfo(Triple); 7123 } 7124 7125 case llvm::Triple::aarch64_be: 7126 switch (os) { 7127 case llvm::Triple::FreeBSD: 7128 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 7129 case llvm::Triple::Linux: 7130 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 7131 case llvm::Triple::NetBSD: 7132 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 7133 default: 7134 return new AArch64beTargetInfo(Triple); 7135 } 7136 7137 case llvm::Triple::arm: 7138 case llvm::Triple::thumb: 7139 if (Triple.isOSBinFormatMachO()) 7140 return new DarwinARMTargetInfo(Triple); 7141 7142 switch (os) { 7143 case llvm::Triple::Linux: 7144 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 7145 case llvm::Triple::FreeBSD: 7146 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 7147 case llvm::Triple::NetBSD: 7148 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 7149 case llvm::Triple::OpenBSD: 7150 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 7151 case llvm::Triple::Bitrig: 7152 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 7153 case llvm::Triple::RTEMS: 7154 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 7155 case llvm::Triple::NaCl: 7156 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 7157 case llvm::Triple::Win32: 7158 switch (Triple.getEnvironment()) { 7159 case llvm::Triple::Cygnus: 7160 return new CygwinARMTargetInfo(Triple); 7161 case llvm::Triple::GNU: 7162 return new MinGWARMTargetInfo(Triple); 7163 case llvm::Triple::Itanium: 7164 return new ItaniumWindowsARMleTargetInfo(Triple); 7165 case llvm::Triple::MSVC: 7166 default: // Assume MSVC for unknown environments 7167 return new MicrosoftARMleTargetInfo(Triple); 7168 } 7169 default: 7170 return new ARMleTargetInfo(Triple); 7171 } 7172 7173 case llvm::Triple::armeb: 7174 case llvm::Triple::thumbeb: 7175 if (Triple.isOSDarwin()) 7176 return new DarwinARMTargetInfo(Triple); 7177 7178 switch (os) { 7179 case llvm::Triple::Linux: 7180 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 7181 case llvm::Triple::FreeBSD: 7182 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 7183 case llvm::Triple::NetBSD: 7184 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 7185 case llvm::Triple::OpenBSD: 7186 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 7187 case llvm::Triple::Bitrig: 7188 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 7189 case llvm::Triple::RTEMS: 7190 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 7191 case llvm::Triple::NaCl: 7192 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 7193 default: 7194 return new ARMbeTargetInfo(Triple); 7195 } 7196 7197 case llvm::Triple::bpfeb: 7198 case llvm::Triple::bpfel: 7199 return new BPFTargetInfo(Triple); 7200 7201 case llvm::Triple::msp430: 7202 return new MSP430TargetInfo(Triple); 7203 7204 case llvm::Triple::mips: 7205 switch (os) { 7206 case llvm::Triple::Linux: 7207 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 7208 case llvm::Triple::RTEMS: 7209 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 7210 case llvm::Triple::FreeBSD: 7211 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7212 case llvm::Triple::NetBSD: 7213 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7214 default: 7215 return new Mips32EBTargetInfo(Triple); 7216 } 7217 7218 case llvm::Triple::mipsel: 7219 switch (os) { 7220 case llvm::Triple::Linux: 7221 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 7222 case llvm::Triple::RTEMS: 7223 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 7224 case llvm::Triple::FreeBSD: 7225 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7226 case llvm::Triple::NetBSD: 7227 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7228 case llvm::Triple::NaCl: 7229 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple); 7230 default: 7231 return new Mips32ELTargetInfo(Triple); 7232 } 7233 7234 case llvm::Triple::mips64: 7235 switch (os) { 7236 case llvm::Triple::Linux: 7237 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 7238 case llvm::Triple::RTEMS: 7239 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 7240 case llvm::Triple::FreeBSD: 7241 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7242 case llvm::Triple::NetBSD: 7243 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7244 case llvm::Triple::OpenBSD: 7245 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7246 default: 7247 return new Mips64EBTargetInfo(Triple); 7248 } 7249 7250 case llvm::Triple::mips64el: 7251 switch (os) { 7252 case llvm::Triple::Linux: 7253 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 7254 case llvm::Triple::RTEMS: 7255 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 7256 case llvm::Triple::FreeBSD: 7257 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7258 case llvm::Triple::NetBSD: 7259 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7260 case llvm::Triple::OpenBSD: 7261 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7262 default: 7263 return new Mips64ELTargetInfo(Triple); 7264 } 7265 7266 case llvm::Triple::le32: 7267 switch (os) { 7268 case llvm::Triple::NaCl: 7269 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 7270 default: 7271 return nullptr; 7272 } 7273 7274 case llvm::Triple::le64: 7275 return new Le64TargetInfo(Triple); 7276 7277 case llvm::Triple::ppc: 7278 if (Triple.isOSDarwin()) 7279 return new DarwinPPC32TargetInfo(Triple); 7280 switch (os) { 7281 case llvm::Triple::Linux: 7282 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 7283 case llvm::Triple::FreeBSD: 7284 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 7285 case llvm::Triple::NetBSD: 7286 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 7287 case llvm::Triple::OpenBSD: 7288 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 7289 case llvm::Triple::RTEMS: 7290 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 7291 default: 7292 return new PPC32TargetInfo(Triple); 7293 } 7294 7295 case llvm::Triple::ppc64: 7296 if (Triple.isOSDarwin()) 7297 return new DarwinPPC64TargetInfo(Triple); 7298 switch (os) { 7299 case llvm::Triple::Linux: 7300 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7301 case llvm::Triple::Lv2: 7302 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 7303 case llvm::Triple::FreeBSD: 7304 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 7305 case llvm::Triple::NetBSD: 7306 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7307 default: 7308 return new PPC64TargetInfo(Triple); 7309 } 7310 7311 case llvm::Triple::ppc64le: 7312 switch (os) { 7313 case llvm::Triple::Linux: 7314 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7315 case llvm::Triple::NetBSD: 7316 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7317 default: 7318 return new PPC64TargetInfo(Triple); 7319 } 7320 7321 case llvm::Triple::nvptx: 7322 return new NVPTX32TargetInfo(Triple); 7323 case llvm::Triple::nvptx64: 7324 return new NVPTX64TargetInfo(Triple); 7325 7326 case llvm::Triple::amdgcn: 7327 case llvm::Triple::r600: 7328 return new AMDGPUTargetInfo(Triple); 7329 7330 case llvm::Triple::sparc: 7331 switch (os) { 7332 case llvm::Triple::Linux: 7333 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 7334 case llvm::Triple::Solaris: 7335 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple); 7336 case llvm::Triple::NetBSD: 7337 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 7338 case llvm::Triple::OpenBSD: 7339 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 7340 case llvm::Triple::RTEMS: 7341 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 7342 default: 7343 return new SparcV8TargetInfo(Triple); 7344 } 7345 7346 // The 'sparcel' architecture copies all the above cases except for Solaris. 7347 case llvm::Triple::sparcel: 7348 switch (os) { 7349 case llvm::Triple::Linux: 7350 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 7351 case llvm::Triple::NetBSD: 7352 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7353 case llvm::Triple::OpenBSD: 7354 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7355 case llvm::Triple::RTEMS: 7356 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 7357 default: 7358 return new SparcV8elTargetInfo(Triple); 7359 } 7360 7361 case llvm::Triple::sparcv9: 7362 switch (os) { 7363 case llvm::Triple::Linux: 7364 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 7365 case llvm::Triple::Solaris: 7366 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 7367 case llvm::Triple::NetBSD: 7368 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 7369 case llvm::Triple::OpenBSD: 7370 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 7371 case llvm::Triple::FreeBSD: 7372 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 7373 default: 7374 return new SparcV9TargetInfo(Triple); 7375 } 7376 7377 case llvm::Triple::systemz: 7378 switch (os) { 7379 case llvm::Triple::Linux: 7380 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 7381 default: 7382 return new SystemZTargetInfo(Triple); 7383 } 7384 7385 case llvm::Triple::tce: 7386 return new TCETargetInfo(Triple); 7387 7388 case llvm::Triple::x86: 7389 if (Triple.isOSDarwin()) 7390 return new DarwinI386TargetInfo(Triple); 7391 7392 switch (os) { 7393 case llvm::Triple::CloudABI: 7394 return new CloudABITargetInfo<X86_32TargetInfo>(Triple); 7395 case llvm::Triple::Linux: { 7396 switch (Triple.getEnvironment()) { 7397 default: 7398 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 7399 case llvm::Triple::Android: 7400 return new AndroidX86_32TargetInfo(Triple); 7401 } 7402 } 7403 case llvm::Triple::DragonFly: 7404 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 7405 case llvm::Triple::NetBSD: 7406 return new NetBSDI386TargetInfo(Triple); 7407 case llvm::Triple::OpenBSD: 7408 return new OpenBSDI386TargetInfo(Triple); 7409 case llvm::Triple::Bitrig: 7410 return new BitrigI386TargetInfo(Triple); 7411 case llvm::Triple::FreeBSD: 7412 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7413 case llvm::Triple::KFreeBSD: 7414 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7415 case llvm::Triple::Minix: 7416 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 7417 case llvm::Triple::Solaris: 7418 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 7419 case llvm::Triple::Win32: { 7420 switch (Triple.getEnvironment()) { 7421 case llvm::Triple::Cygnus: 7422 return new CygwinX86_32TargetInfo(Triple); 7423 case llvm::Triple::GNU: 7424 return new MinGWX86_32TargetInfo(Triple); 7425 case llvm::Triple::Itanium: 7426 case llvm::Triple::MSVC: 7427 default: // Assume MSVC for unknown environments 7428 return new MicrosoftX86_32TargetInfo(Triple); 7429 } 7430 } 7431 case llvm::Triple::Haiku: 7432 return new HaikuX86_32TargetInfo(Triple); 7433 case llvm::Triple::RTEMS: 7434 return new RTEMSX86_32TargetInfo(Triple); 7435 case llvm::Triple::NaCl: 7436 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 7437 default: 7438 return new X86_32TargetInfo(Triple); 7439 } 7440 7441 case llvm::Triple::x86_64: 7442 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 7443 return new DarwinX86_64TargetInfo(Triple); 7444 7445 switch (os) { 7446 case llvm::Triple::CloudABI: 7447 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 7448 case llvm::Triple::Linux: { 7449 switch (Triple.getEnvironment()) { 7450 default: 7451 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 7452 case llvm::Triple::Android: 7453 return new AndroidX86_64TargetInfo(Triple); 7454 } 7455 } 7456 case llvm::Triple::DragonFly: 7457 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 7458 case llvm::Triple::NetBSD: 7459 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 7460 case llvm::Triple::OpenBSD: 7461 return new OpenBSDX86_64TargetInfo(Triple); 7462 case llvm::Triple::Bitrig: 7463 return new BitrigX86_64TargetInfo(Triple); 7464 case llvm::Triple::FreeBSD: 7465 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7466 case llvm::Triple::KFreeBSD: 7467 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7468 case llvm::Triple::Solaris: 7469 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 7470 case llvm::Triple::Win32: { 7471 switch (Triple.getEnvironment()) { 7472 case llvm::Triple::Cygnus: 7473 return new CygwinX86_64TargetInfo(Triple); 7474 case llvm::Triple::GNU: 7475 return new MinGWX86_64TargetInfo(Triple); 7476 case llvm::Triple::MSVC: 7477 default: // Assume MSVC for unknown environments 7478 return new MicrosoftX86_64TargetInfo(Triple); 7479 } 7480 } 7481 case llvm::Triple::NaCl: 7482 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 7483 case llvm::Triple::PS4: 7484 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 7485 default: 7486 return new X86_64TargetInfo(Triple); 7487 } 7488 7489 case llvm::Triple::spir: { 7490 if (Triple.getOS() != llvm::Triple::UnknownOS || 7491 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7492 return nullptr; 7493 return new SPIR32TargetInfo(Triple); 7494 } 7495 case llvm::Triple::spir64: { 7496 if (Triple.getOS() != llvm::Triple::UnknownOS || 7497 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7498 return nullptr; 7499 return new SPIR64TargetInfo(Triple); 7500 } 7501 } 7502 } 7503 7504 /// CreateTargetInfo - Return the target info object for the specified target 7505 /// options. 7506 TargetInfo * 7507 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 7508 const std::shared_ptr<TargetOptions> &Opts) { 7509 llvm::Triple Triple(Opts->Triple); 7510 7511 // Construct the target 7512 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 7513 if (!Target) { 7514 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 7515 return nullptr; 7516 } 7517 Target->TargetOpts = Opts; 7518 7519 // Set the target CPU if specified. 7520 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 7521 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 7522 return nullptr; 7523 } 7524 7525 // Set the target ABI if specified. 7526 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 7527 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 7528 return nullptr; 7529 } 7530 7531 // Set the fp math unit. 7532 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 7533 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 7534 return nullptr; 7535 } 7536 7537 // Compute the default target features, we need the target to handle this 7538 // because features may have dependencies on one another. 7539 llvm::StringMap<bool> Features; 7540 Target->getDefaultFeatures(Features); 7541 7542 // Apply the user specified deltas. 7543 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 7544 I < N; ++I) { 7545 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 7546 // Apply the feature via the target. 7547 bool Enabled = Name[0] == '+'; 7548 Target->setFeatureEnabled(Features, Name + 1, Enabled); 7549 } 7550 7551 // Add the features to the compile options. 7552 // 7553 // FIXME: If we are completely confident that we have the right set, we only 7554 // need to pass the minuses. 7555 Opts->Features.clear(); 7556 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 7557 ie = Features.end(); it != ie; ++it) 7558 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 7559 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 7560 return nullptr; 7561 7562 return Target.release(); 7563 } 7564