1 //===--- Targets.cpp - Implement -arch option and targets -----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements construction of a TargetInfo object from a
11 // target triple.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/OwningPtr.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/MC/MCSectionMachO.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include <algorithm>
32 using namespace clang;
33 
34 //===----------------------------------------------------------------------===//
35 //  Common code shared among targets.
36 //===----------------------------------------------------------------------===//
37 
38 /// DefineStd - Define a macro name and standard variants.  For example if
39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
40 /// when in GNU mode.
41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
42                       const LangOptions &Opts) {
43   assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
44 
45   // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
46   // in the user's namespace.
47   if (Opts.GNUMode)
48     Builder.defineMacro(MacroName);
49 
50   // Define __unix.
51   Builder.defineMacro("__" + MacroName);
52 
53   // Define __unix__.
54   Builder.defineMacro("__" + MacroName + "__");
55 }
56 
57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
58                             bool Tuning = true) {
59   Builder.defineMacro("__" + CPUName);
60   Builder.defineMacro("__" + CPUName + "__");
61   if (Tuning)
62     Builder.defineMacro("__tune_" + CPUName + "__");
63 }
64 
65 //===----------------------------------------------------------------------===//
66 // Defines specific to certain operating systems.
67 //===----------------------------------------------------------------------===//
68 
69 namespace {
70 template<typename TgtInfo>
71 class OSTargetInfo : public TgtInfo {
72 protected:
73   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
74                             MacroBuilder &Builder) const=0;
75 public:
76   OSTargetInfo(const std::string& triple) : TgtInfo(triple) {}
77   virtual void getTargetDefines(const LangOptions &Opts,
78                                 MacroBuilder &Builder) const {
79     TgtInfo::getTargetDefines(Opts, Builder);
80     getOSDefines(Opts, TgtInfo::getTriple(), Builder);
81   }
82 
83 };
84 } // end anonymous namespace
85 
86 
87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
88                              const llvm::Triple &Triple,
89                              StringRef &PlatformName,
90                              VersionTuple &PlatformMinVersion) {
91   Builder.defineMacro("__APPLE_CC__", "5621");
92   Builder.defineMacro("__APPLE__");
93   Builder.defineMacro("__MACH__");
94   Builder.defineMacro("OBJC_NEW_PROPERTIES");
95   // AddressSanitizer doesn't play well with source fortification, which is on
96   // by default on Darwin.
97   if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0");
98 
99   if (!Opts.ObjCAutoRefCount) {
100     // __weak is always defined, for use in blocks and with objc pointers.
101     Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
102 
103     // Darwin defines __strong even in C mode (just to nothing).
104     if (Opts.getGC() != LangOptions::NonGC)
105       Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
106     else
107       Builder.defineMacro("__strong", "");
108 
109     // __unsafe_unretained is defined to nothing in non-ARC mode. We even
110     // allow this in C, since one might have block pointers in structs that
111     // are used in pure C code and in Objective-C ARC.
112     Builder.defineMacro("__unsafe_unretained", "");
113   }
114 
115   if (Opts.Static)
116     Builder.defineMacro("__STATIC__");
117   else
118     Builder.defineMacro("__DYNAMIC__");
119 
120   if (Opts.POSIXThreads)
121     Builder.defineMacro("_REENTRANT");
122 
123   // Get the platform type and version number from the triple.
124   unsigned Maj, Min, Rev;
125   if (Triple.isMacOSX()) {
126     Triple.getMacOSXVersion(Maj, Min, Rev);
127     PlatformName = "macosx";
128   } else {
129     Triple.getOSVersion(Maj, Min, Rev);
130     PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
131   }
132 
133   // If -target arch-pc-win32-macho option specified, we're
134   // generating code for Win32 ABI. No need to emit
135   // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
136   if (PlatformName == "win32") {
137     PlatformMinVersion = VersionTuple(Maj, Min, Rev);
138     return;
139   }
140 
141   // Set the appropriate OS version define.
142   if (Triple.getOS() == llvm::Triple::IOS) {
143     assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
144     char Str[6];
145     Str[0] = '0' + Maj;
146     Str[1] = '0' + (Min / 10);
147     Str[2] = '0' + (Min % 10);
148     Str[3] = '0' + (Rev / 10);
149     Str[4] = '0' + (Rev % 10);
150     Str[5] = '\0';
151     Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str);
152   } else {
153     // Note that the Driver allows versions which aren't representable in the
154     // define (because we only get a single digit for the minor and micro
155     // revision numbers). So, we limit them to the maximum representable
156     // version.
157     assert(Triple.getEnvironmentName().empty() && "Invalid environment!");
158     assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
159     char Str[5];
160     Str[0] = '0' + (Maj / 10);
161     Str[1] = '0' + (Maj % 10);
162     Str[2] = '0' + std::min(Min, 9U);
163     Str[3] = '0' + std::min(Rev, 9U);
164     Str[4] = '\0';
165     Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
166   }
167 
168   PlatformMinVersion = VersionTuple(Maj, Min, Rev);
169 }
170 
171 namespace {
172 template<typename Target>
173 class DarwinTargetInfo : public OSTargetInfo<Target> {
174 protected:
175   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
176                             MacroBuilder &Builder) const {
177     getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
178                      this->PlatformMinVersion);
179   }
180 
181 public:
182   DarwinTargetInfo(const std::string& triple) :
183     OSTargetInfo<Target>(triple) {
184       llvm::Triple T = llvm::Triple(triple);
185       this->TLSSupported = T.isMacOSX() && !T.isMacOSXVersionLT(10,7);
186       this->MCountName = "\01mcount";
187     }
188 
189   virtual std::string isValidSectionSpecifier(StringRef SR) const {
190     // Let MCSectionMachO validate this.
191     StringRef Segment, Section;
192     unsigned TAA, StubSize;
193     bool HasTAA;
194     return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
195                                                        TAA, HasTAA, StubSize);
196   }
197 
198   virtual const char *getStaticInitSectionSpecifier() const {
199     // FIXME: We should return 0 when building kexts.
200     return "__TEXT,__StaticInit,regular,pure_instructions";
201   }
202 
203   /// Darwin does not support protected visibility.  Darwin's "default"
204   /// is very similar to ELF's "protected";  Darwin requires a "weak"
205   /// attribute on declarations that can be dynamically replaced.
206   virtual bool hasProtectedVisibility() const {
207     return false;
208   }
209 };
210 
211 
212 // DragonFlyBSD Target
213 template<typename Target>
214 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
215 protected:
216   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
217                             MacroBuilder &Builder) const {
218     // DragonFly defines; list based off of gcc output
219     Builder.defineMacro("__DragonFly__");
220     Builder.defineMacro("__DragonFly_cc_version", "100001");
221     Builder.defineMacro("__ELF__");
222     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
223     Builder.defineMacro("__tune_i386__");
224     DefineStd(Builder, "unix", Opts);
225   }
226 public:
227   DragonFlyBSDTargetInfo(const std::string &triple)
228     : OSTargetInfo<Target>(triple) {
229       this->UserLabelPrefix = "";
230 
231       llvm::Triple Triple(triple);
232       switch (Triple.getArch()) {
233         default:
234         case llvm::Triple::x86:
235         case llvm::Triple::x86_64:
236           this->MCountName = ".mcount";
237           break;
238       }
239   }
240 };
241 
242 // FreeBSD Target
243 template<typename Target>
244 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
245 protected:
246   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
247                             MacroBuilder &Builder) const {
248     // FreeBSD defines; list based off of gcc output
249 
250     unsigned Release = Triple.getOSMajorVersion();
251     if (Release == 0U)
252       Release = 8;
253 
254     Builder.defineMacro("__FreeBSD__", Twine(Release));
255     Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
256     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
257     DefineStd(Builder, "unix", Opts);
258     Builder.defineMacro("__ELF__");
259   }
260 public:
261   FreeBSDTargetInfo(const std::string &triple)
262     : OSTargetInfo<Target>(triple) {
263       this->UserLabelPrefix = "";
264 
265       llvm::Triple Triple(triple);
266       switch (Triple.getArch()) {
267         default:
268         case llvm::Triple::x86:
269         case llvm::Triple::x86_64:
270           this->MCountName = ".mcount";
271           break;
272         case llvm::Triple::mips:
273         case llvm::Triple::mipsel:
274         case llvm::Triple::ppc:
275         case llvm::Triple::ppc64:
276           this->MCountName = "_mcount";
277           break;
278         case llvm::Triple::arm:
279           this->MCountName = "__mcount";
280           break;
281       }
282 
283     }
284 };
285 
286 // Minix Target
287 template<typename Target>
288 class MinixTargetInfo : public OSTargetInfo<Target> {
289 protected:
290   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
291                             MacroBuilder &Builder) const {
292     // Minix defines
293 
294     Builder.defineMacro("__minix", "3");
295     Builder.defineMacro("_EM_WSIZE", "4");
296     Builder.defineMacro("_EM_PSIZE", "4");
297     Builder.defineMacro("_EM_SSIZE", "2");
298     Builder.defineMacro("_EM_LSIZE", "4");
299     Builder.defineMacro("_EM_FSIZE", "4");
300     Builder.defineMacro("_EM_DSIZE", "8");
301     Builder.defineMacro("__ELF__");
302     DefineStd(Builder, "unix", Opts);
303   }
304 public:
305   MinixTargetInfo(const std::string &triple)
306     : OSTargetInfo<Target>(triple) {
307       this->UserLabelPrefix = "";
308     }
309 };
310 
311 // Linux target
312 template<typename Target>
313 class LinuxTargetInfo : public OSTargetInfo<Target> {
314 protected:
315   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
316                             MacroBuilder &Builder) const {
317     // Linux defines; list based off of gcc output
318     DefineStd(Builder, "unix", Opts);
319     DefineStd(Builder, "linux", Opts);
320     Builder.defineMacro("__gnu_linux__");
321     Builder.defineMacro("__ELF__");
322     if (Triple.getEnvironment() == llvm::Triple::Android)
323       Builder.defineMacro("__ANDROID__", "1");
324     if (Opts.POSIXThreads)
325       Builder.defineMacro("_REENTRANT");
326     if (Opts.CPlusPlus)
327       Builder.defineMacro("_GNU_SOURCE");
328   }
329 public:
330   LinuxTargetInfo(const std::string& triple)
331     : OSTargetInfo<Target>(triple) {
332     this->UserLabelPrefix = "";
333     this->WIntType = TargetInfo::UnsignedInt;
334   }
335 
336   virtual const char *getStaticInitSectionSpecifier() const {
337     return ".text.startup";
338   }
339 };
340 
341 // NetBSD Target
342 template<typename Target>
343 class NetBSDTargetInfo : public OSTargetInfo<Target> {
344 protected:
345   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
346                             MacroBuilder &Builder) const {
347     // NetBSD defines; list based off of gcc output
348     Builder.defineMacro("__NetBSD__");
349     Builder.defineMacro("__unix__");
350     Builder.defineMacro("__ELF__");
351     if (Opts.POSIXThreads)
352       Builder.defineMacro("_POSIX_THREADS");
353   }
354 public:
355   NetBSDTargetInfo(const std::string &triple)
356     : OSTargetInfo<Target>(triple) {
357       this->UserLabelPrefix = "";
358     }
359 };
360 
361 // OpenBSD Target
362 template<typename Target>
363 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
364 protected:
365   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
366                             MacroBuilder &Builder) const {
367     // OpenBSD defines; list based off of gcc output
368 
369     Builder.defineMacro("__OpenBSD__");
370     DefineStd(Builder, "unix", Opts);
371     Builder.defineMacro("__ELF__");
372     if (Opts.POSIXThreads)
373       Builder.defineMacro("_REENTRANT");
374   }
375 public:
376   OpenBSDTargetInfo(const std::string &triple)
377     : OSTargetInfo<Target>(triple) {
378       this->UserLabelPrefix = "";
379       this->TLSSupported = false;
380 
381       llvm::Triple Triple(triple);
382       switch (Triple.getArch()) {
383         default:
384         case llvm::Triple::x86:
385         case llvm::Triple::x86_64:
386         case llvm::Triple::arm:
387         case llvm::Triple::sparc:
388           this->MCountName = "__mcount";
389           break;
390         case llvm::Triple::mips64:
391         case llvm::Triple::mips64el:
392         case llvm::Triple::ppc:
393         case llvm::Triple::sparcv9:
394           this->MCountName = "_mcount";
395           break;
396       }
397   }
398 };
399 
400 // Bitrig Target
401 template<typename Target>
402 class BitrigTargetInfo : public OSTargetInfo<Target> {
403 protected:
404   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
405                             MacroBuilder &Builder) const {
406     // Bitrig defines; list based off of gcc output
407 
408     Builder.defineMacro("__Bitrig__");
409     DefineStd(Builder, "unix", Opts);
410     Builder.defineMacro("__ELF__");
411     if (Opts.POSIXThreads)
412       Builder.defineMacro("_REENTRANT");
413   }
414 public:
415   BitrigTargetInfo(const std::string &triple)
416     : OSTargetInfo<Target>(triple) {
417       this->UserLabelPrefix = "";
418       this->TLSSupported = false;
419       this->MCountName = "__mcount";
420   }
421 };
422 
423 // PSP Target
424 template<typename Target>
425 class PSPTargetInfo : public OSTargetInfo<Target> {
426 protected:
427   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
428                             MacroBuilder &Builder) const {
429     // PSP defines; list based on the output of the pspdev gcc toolchain.
430     Builder.defineMacro("PSP");
431     Builder.defineMacro("_PSP");
432     Builder.defineMacro("__psp__");
433     Builder.defineMacro("__ELF__");
434   }
435 public:
436   PSPTargetInfo(const std::string& triple)
437     : OSTargetInfo<Target>(triple) {
438     this->UserLabelPrefix = "";
439   }
440 };
441 
442 // PS3 PPU Target
443 template<typename Target>
444 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
445 protected:
446   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
447                             MacroBuilder &Builder) const {
448     // PS3 PPU defines.
449     Builder.defineMacro("__PPC__");
450     Builder.defineMacro("__PPU__");
451     Builder.defineMacro("__CELLOS_LV2__");
452     Builder.defineMacro("__ELF__");
453     Builder.defineMacro("__LP32__");
454     Builder.defineMacro("_ARCH_PPC64");
455     Builder.defineMacro("__powerpc64__");
456   }
457 public:
458   PS3PPUTargetInfo(const std::string& triple)
459     : OSTargetInfo<Target>(triple) {
460     this->UserLabelPrefix = "";
461     this->LongWidth = this->LongAlign = 32;
462     this->PointerWidth = this->PointerAlign = 32;
463     this->IntMaxType = TargetInfo::SignedLongLong;
464     this->UIntMaxType = TargetInfo::UnsignedLongLong;
465     this->Int64Type = TargetInfo::SignedLongLong;
466     this->SizeType = TargetInfo::UnsignedInt;
467     this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
468                               "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
469   }
470 };
471 
472 // FIXME: Need a real SPU target.
473 // PS3 SPU Target
474 template<typename Target>
475 class PS3SPUTargetInfo : public OSTargetInfo<Target> {
476 protected:
477   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
478                             MacroBuilder &Builder) const {
479     // PS3 PPU defines.
480     Builder.defineMacro("__SPU__");
481     Builder.defineMacro("__ELF__");
482   }
483 public:
484   PS3SPUTargetInfo(const std::string& triple)
485     : OSTargetInfo<Target>(triple) {
486     this->UserLabelPrefix = "";
487   }
488 };
489 
490 // AuroraUX target
491 template<typename Target>
492 class AuroraUXTargetInfo : public OSTargetInfo<Target> {
493 protected:
494   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
495                             MacroBuilder &Builder) const {
496     DefineStd(Builder, "sun", Opts);
497     DefineStd(Builder, "unix", Opts);
498     Builder.defineMacro("__ELF__");
499     Builder.defineMacro("__svr4__");
500     Builder.defineMacro("__SVR4");
501   }
502 public:
503   AuroraUXTargetInfo(const std::string& triple)
504     : OSTargetInfo<Target>(triple) {
505     this->UserLabelPrefix = "";
506     this->WCharType = this->SignedLong;
507     // FIXME: WIntType should be SignedLong
508   }
509 };
510 
511 // Solaris target
512 template<typename Target>
513 class SolarisTargetInfo : public OSTargetInfo<Target> {
514 protected:
515   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
516                             MacroBuilder &Builder) const {
517     DefineStd(Builder, "sun", Opts);
518     DefineStd(Builder, "unix", Opts);
519     Builder.defineMacro("__ELF__");
520     Builder.defineMacro("__svr4__");
521     Builder.defineMacro("__SVR4");
522     // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
523     // newer, but to 500 for everything else.  feature_test.h has a check to
524     // ensure that you are not using C99 with an old version of X/Open or C89
525     // with a new version.
526     if (Opts.C99 || Opts.C11)
527       Builder.defineMacro("_XOPEN_SOURCE", "600");
528     else
529       Builder.defineMacro("_XOPEN_SOURCE", "500");
530     if (Opts.CPlusPlus)
531       Builder.defineMacro("__C99FEATURES__");
532     Builder.defineMacro("_LARGEFILE_SOURCE");
533     Builder.defineMacro("_LARGEFILE64_SOURCE");
534     Builder.defineMacro("__EXTENSIONS__");
535     Builder.defineMacro("_REENTRANT");
536   }
537 public:
538   SolarisTargetInfo(const std::string& triple)
539     : OSTargetInfo<Target>(triple) {
540     this->UserLabelPrefix = "";
541     this->WCharType = this->SignedInt;
542     // FIXME: WIntType should be SignedLong
543   }
544 };
545 
546 // Windows target
547 template<typename Target>
548 class WindowsTargetInfo : public OSTargetInfo<Target> {
549 protected:
550   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
551                             MacroBuilder &Builder) const {
552     Builder.defineMacro("_WIN32");
553   }
554   void getVisualStudioDefines(const LangOptions &Opts,
555                               MacroBuilder &Builder) const {
556     if (Opts.CPlusPlus) {
557       if (Opts.RTTI)
558         Builder.defineMacro("_CPPRTTI");
559 
560       if (Opts.Exceptions)
561         Builder.defineMacro("_CPPUNWIND");
562     }
563 
564     if (!Opts.CharIsSigned)
565       Builder.defineMacro("_CHAR_UNSIGNED");
566 
567     // FIXME: POSIXThreads isn't exactly the option this should be defined for,
568     //        but it works for now.
569     if (Opts.POSIXThreads)
570       Builder.defineMacro("_MT");
571 
572     if (Opts.MSCVersion != 0)
573       Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion));
574 
575     if (Opts.MicrosoftExt) {
576       Builder.defineMacro("_MSC_EXTENSIONS");
577 
578       if (Opts.CPlusPlus11) {
579         Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
580         Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
581         Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
582       }
583     }
584 
585     Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
586   }
587 
588 public:
589   WindowsTargetInfo(const std::string &triple)
590     : OSTargetInfo<Target>(triple) {}
591 };
592 
593 template <typename Target>
594 class NaClTargetInfo : public OSTargetInfo<Target> {
595  protected:
596   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
597                             MacroBuilder &Builder) const {
598     if (Opts.POSIXThreads)
599       Builder.defineMacro("_REENTRANT");
600     if (Opts.CPlusPlus)
601       Builder.defineMacro("_GNU_SOURCE");
602 
603     DefineStd(Builder, "unix", Opts);
604     Builder.defineMacro("__ELF__");
605     Builder.defineMacro("__native_client__");
606   }
607  public:
608   NaClTargetInfo(const std::string &triple)
609     : OSTargetInfo<Target>(triple) {
610     this->UserLabelPrefix = "";
611     this->LongAlign = 32;
612     this->LongWidth = 32;
613     this->PointerAlign = 32;
614     this->PointerWidth = 32;
615     this->IntMaxType = TargetInfo::SignedLongLong;
616     this->UIntMaxType = TargetInfo::UnsignedLongLong;
617     this->Int64Type = TargetInfo::SignedLongLong;
618     this->DoubleAlign = 64;
619     this->LongDoubleWidth = 64;
620     this->LongDoubleAlign = 64;
621     this->SizeType = TargetInfo::UnsignedInt;
622     this->PtrDiffType = TargetInfo::SignedInt;
623     this->IntPtrType = TargetInfo::SignedInt;
624     // RegParmMax is inherited from the underlying architecture
625     this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
626     this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
627                               "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
628   }
629   virtual typename Target::CallingConvCheckResult checkCallingConvention(
630       CallingConv CC) const {
631     return CC == CC_PnaclCall ? Target::CCCR_OK :
632         Target::checkCallingConvention(CC);
633   }
634 };
635 } // end anonymous namespace.
636 
637 //===----------------------------------------------------------------------===//
638 // Specific target implementations.
639 //===----------------------------------------------------------------------===//
640 
641 namespace {
642 // PPC abstract base class
643 class PPCTargetInfo : public TargetInfo {
644   static const Builtin::Info BuiltinInfo[];
645   static const char * const GCCRegNames[];
646   static const TargetInfo::GCCRegAlias GCCRegAliases[];
647   std::string CPU;
648 public:
649   PPCTargetInfo(const std::string& triple) : TargetInfo(triple) {
650     LongDoubleWidth = LongDoubleAlign = 128;
651     LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
652   }
653 
654   /// \brief Flags for architecture specific defines.
655   typedef enum {
656     ArchDefineNone  = 0,
657     ArchDefineName  = 1 << 0, // <name> is substituted for arch name.
658     ArchDefinePpcgr = 1 << 1,
659     ArchDefinePpcsq = 1 << 2,
660     ArchDefine440   = 1 << 3,
661     ArchDefine603   = 1 << 4,
662     ArchDefine604   = 1 << 5,
663     ArchDefinePwr4  = 1 << 6,
664     ArchDefinePwr5  = 1 << 7,
665     ArchDefinePwr5x = 1 << 8,
666     ArchDefinePwr6  = 1 << 9,
667     ArchDefinePwr6x = 1 << 10,
668     ArchDefinePwr7  = 1 << 11,
669     ArchDefineA2    = 1 << 12,
670     ArchDefineA2q   = 1 << 13
671   } ArchDefineTypes;
672 
673   // Note: GCC recognizes the following additional cpus:
674   //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
675   //  821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
676   //  titan, rs64.
677   virtual bool setCPU(const std::string &Name) {
678     bool CPUKnown = llvm::StringSwitch<bool>(Name)
679       .Case("generic", true)
680       .Case("440", true)
681       .Case("450", true)
682       .Case("601", true)
683       .Case("602", true)
684       .Case("603", true)
685       .Case("603e", true)
686       .Case("603ev", true)
687       .Case("604", true)
688       .Case("604e", true)
689       .Case("620", true)
690       .Case("630", true)
691       .Case("g3", true)
692       .Case("7400", true)
693       .Case("g4", true)
694       .Case("7450", true)
695       .Case("g4+", true)
696       .Case("750", true)
697       .Case("970", true)
698       .Case("g5", true)
699       .Case("a2", true)
700       .Case("a2q", true)
701       .Case("e500mc", true)
702       .Case("e5500", true)
703       .Case("power3", true)
704       .Case("pwr3", true)
705       .Case("power4", true)
706       .Case("pwr4", true)
707       .Case("power5", true)
708       .Case("pwr5", true)
709       .Case("power5x", true)
710       .Case("pwr5x", true)
711       .Case("power6", true)
712       .Case("pwr6", true)
713       .Case("power6x", true)
714       .Case("pwr6x", true)
715       .Case("power7", true)
716       .Case("pwr7", true)
717       .Case("powerpc", true)
718       .Case("ppc", true)
719       .Case("powerpc64", true)
720       .Case("ppc64", true)
721       .Default(false);
722 
723     if (CPUKnown)
724       CPU = Name;
725 
726     return CPUKnown;
727   }
728 
729   virtual void getTargetBuiltins(const Builtin::Info *&Records,
730                                  unsigned &NumRecords) const {
731     Records = BuiltinInfo;
732     NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
733   }
734 
735   virtual bool isCLZForZeroUndef() const { return false; }
736 
737   virtual void getTargetDefines(const LangOptions &Opts,
738                                 MacroBuilder &Builder) const;
739 
740   virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
741 
742   virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
743                                  StringRef Name,
744                                  bool Enabled) const;
745 
746   virtual bool hasFeature(StringRef Feature) const;
747 
748   virtual void getGCCRegNames(const char * const *&Names,
749                               unsigned &NumNames) const;
750   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
751                                 unsigned &NumAliases) const;
752   virtual bool validateAsmConstraint(const char *&Name,
753                                      TargetInfo::ConstraintInfo &Info) const {
754     switch (*Name) {
755     default: return false;
756     case 'O': // Zero
757       break;
758     case 'b': // Base register
759     case 'f': // Floating point register
760       Info.setAllowsRegister();
761       break;
762     // FIXME: The following are added to allow parsing.
763     // I just took a guess at what the actions should be.
764     // Also, is more specific checking needed?  I.e. specific registers?
765     case 'd': // Floating point register (containing 64-bit value)
766     case 'v': // Altivec vector register
767       Info.setAllowsRegister();
768       break;
769     case 'w':
770       switch (Name[1]) {
771         case 'd':// VSX vector register to hold vector double data
772         case 'f':// VSX vector register to hold vector float data
773         case 's':// VSX vector register to hold scalar float data
774         case 'a':// Any VSX register
775           break;
776         default:
777           return false;
778       }
779       Info.setAllowsRegister();
780       Name++; // Skip over 'w'.
781       break;
782     case 'h': // `MQ', `CTR', or `LINK' register
783     case 'q': // `MQ' register
784     case 'c': // `CTR' register
785     case 'l': // `LINK' register
786     case 'x': // `CR' register (condition register) number 0
787     case 'y': // `CR' register (condition register)
788     case 'z': // `XER[CA]' carry bit (part of the XER register)
789       Info.setAllowsRegister();
790       break;
791     case 'I': // Signed 16-bit constant
792     case 'J': // Unsigned 16-bit constant shifted left 16 bits
793               //  (use `L' instead for SImode constants)
794     case 'K': // Unsigned 16-bit constant
795     case 'L': // Signed 16-bit constant shifted left 16 bits
796     case 'M': // Constant larger than 31
797     case 'N': // Exact power of 2
798     case 'P': // Constant whose negation is a signed 16-bit constant
799     case 'G': // Floating point constant that can be loaded into a
800               // register with one instruction per word
801     case 'H': // Integer/Floating point constant that can be loaded
802               // into a register using three instructions
803       break;
804     case 'm': // Memory operand. Note that on PowerPC targets, m can
805               // include addresses that update the base register. It
806               // is therefore only safe to use `m' in an asm statement
807               // if that asm statement accesses the operand exactly once.
808               // The asm statement must also use `%U<opno>' as a
809               // placeholder for the "update" flag in the corresponding
810               // load or store instruction. For example:
811               // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
812               // is correct but:
813               // asm ("st %1,%0" : "=m" (mem) : "r" (val));
814               // is not. Use es rather than m if you don't want the base
815               // register to be updated.
816     case 'e':
817       if (Name[1] != 's')
818           return false;
819               // es: A "stable" memory operand; that is, one which does not
820               // include any automodification of the base register. Unlike
821               // `m', this constraint can be used in asm statements that
822               // might access the operand several times, or that might not
823               // access it at all.
824       Info.setAllowsMemory();
825       Name++; // Skip over 'e'.
826       break;
827     case 'Q': // Memory operand that is an offset from a register (it is
828               // usually better to use `m' or `es' in asm statements)
829     case 'Z': // Memory operand that is an indexed or indirect from a
830               // register (it is usually better to use `m' or `es' in
831               // asm statements)
832       Info.setAllowsMemory();
833       Info.setAllowsRegister();
834       break;
835     case 'R': // AIX TOC entry
836     case 'a': // Address operand that is an indexed or indirect from a
837               // register (`p' is preferable for asm statements)
838     case 'S': // Constant suitable as a 64-bit mask operand
839     case 'T': // Constant suitable as a 32-bit mask operand
840     case 'U': // System V Release 4 small data area reference
841     case 't': // AND masks that can be performed by two rldic{l, r}
842               // instructions
843     case 'W': // Vector constant that does not require memory
844     case 'j': // Vector constant that is all zeros.
845       break;
846     // End FIXME.
847     }
848     return true;
849   }
850   virtual const char *getClobbers() const {
851     return "";
852   }
853   int getEHDataRegisterNumber(unsigned RegNo) const {
854     if (RegNo == 0) return 3;
855     if (RegNo == 1) return 4;
856     return -1;
857   }
858 };
859 
860 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
861 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
862 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
863                                               ALL_LANGUAGES },
864 #include "clang/Basic/BuiltinsPPC.def"
865 };
866 
867 
868 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
869 /// #defines that are not tied to a specific subtarget.
870 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
871                                      MacroBuilder &Builder) const {
872   // Target identification.
873   Builder.defineMacro("__ppc__");
874   Builder.defineMacro("_ARCH_PPC");
875   Builder.defineMacro("__powerpc__");
876   Builder.defineMacro("__POWERPC__");
877   if (PointerWidth == 64) {
878     Builder.defineMacro("_ARCH_PPC64");
879     Builder.defineMacro("__powerpc64__");
880     Builder.defineMacro("__ppc64__");
881   } else {
882     Builder.defineMacro("__ppc__");
883   }
884 
885   // Target properties.
886   if (getTriple().getOS() != llvm::Triple::NetBSD &&
887       getTriple().getOS() != llvm::Triple::OpenBSD)
888     Builder.defineMacro("_BIG_ENDIAN");
889   Builder.defineMacro("__BIG_ENDIAN__");
890 
891   // Subtarget options.
892   Builder.defineMacro("__NATURAL_ALIGNMENT__");
893   Builder.defineMacro("__REGISTER_PREFIX__", "");
894 
895   // FIXME: Should be controlled by command line option.
896   Builder.defineMacro("__LONG_DOUBLE_128__");
897 
898   if (Opts.AltiVec) {
899     Builder.defineMacro("__VEC__", "10206");
900     Builder.defineMacro("__ALTIVEC__");
901   }
902 
903   // CPU identification.
904   ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
905     .Case("440",   ArchDefineName)
906     .Case("450",   ArchDefineName | ArchDefine440)
907     .Case("601",   ArchDefineName)
908     .Case("602",   ArchDefineName | ArchDefinePpcgr)
909     .Case("603",   ArchDefineName | ArchDefinePpcgr)
910     .Case("603e",  ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
911     .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
912     .Case("604",   ArchDefineName | ArchDefinePpcgr)
913     .Case("604e",  ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
914     .Case("620",   ArchDefineName | ArchDefinePpcgr)
915     .Case("630",   ArchDefineName | ArchDefinePpcgr)
916     .Case("7400",  ArchDefineName | ArchDefinePpcgr)
917     .Case("7450",  ArchDefineName | ArchDefinePpcgr)
918     .Case("750",   ArchDefineName | ArchDefinePpcgr)
919     .Case("970",   ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
920                      | ArchDefinePpcsq)
921     .Case("a2",    ArchDefineA2)
922     .Case("a2q",   ArchDefineName | ArchDefineA2 | ArchDefineA2q)
923     .Case("pwr3",  ArchDefinePpcgr)
924     .Case("pwr4",  ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
925     .Case("pwr5",  ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
926                      | ArchDefinePpcsq)
927     .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
928                      | ArchDefinePpcgr | ArchDefinePpcsq)
929     .Case("pwr6",  ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
930                      | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
931     .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
932                      | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
933                      | ArchDefinePpcsq)
934     .Case("pwr7",  ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
935                      | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
936                      | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
937     .Case("power3",  ArchDefinePpcgr)
938     .Case("power4",  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
939     .Case("power5",  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
940                        | ArchDefinePpcsq)
941     .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
942                        | ArchDefinePpcgr | ArchDefinePpcsq)
943     .Case("power6",  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
944                        | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
945     .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
946                        | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
947                        | ArchDefinePpcsq)
948     .Case("power7",  ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
949                        | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
950                        | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
951     .Default(ArchDefineNone);
952 
953   if (defs & ArchDefineName)
954     Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
955   if (defs & ArchDefinePpcgr)
956     Builder.defineMacro("_ARCH_PPCGR");
957   if (defs & ArchDefinePpcsq)
958     Builder.defineMacro("_ARCH_PPCSQ");
959   if (defs & ArchDefine440)
960     Builder.defineMacro("_ARCH_440");
961   if (defs & ArchDefine603)
962     Builder.defineMacro("_ARCH_603");
963   if (defs & ArchDefine604)
964     Builder.defineMacro("_ARCH_604");
965   if (defs & ArchDefinePwr4)
966     Builder.defineMacro("_ARCH_PWR4");
967   if (defs & ArchDefinePwr5)
968     Builder.defineMacro("_ARCH_PWR5");
969   if (defs & ArchDefinePwr5x)
970     Builder.defineMacro("_ARCH_PWR5X");
971   if (defs & ArchDefinePwr6)
972     Builder.defineMacro("_ARCH_PWR6");
973   if (defs & ArchDefinePwr6x)
974     Builder.defineMacro("_ARCH_PWR6X");
975   if (defs & ArchDefinePwr7)
976     Builder.defineMacro("_ARCH_PWR7");
977   if (defs & ArchDefineA2)
978     Builder.defineMacro("_ARCH_A2");
979   if (defs & ArchDefineA2q) {
980     Builder.defineMacro("_ARCH_A2Q");
981     Builder.defineMacro("_ARCH_QP");
982   }
983 
984   if (getTriple().getVendor() == llvm::Triple::BGQ) {
985     Builder.defineMacro("__bg__");
986     Builder.defineMacro("__THW_BLUEGENE__");
987     Builder.defineMacro("__bgq__");
988     Builder.defineMacro("__TOS_BGQ__");
989   }
990 
991   // FIXME: The following are not yet generated here by Clang, but are
992   //        generated by GCC:
993   //
994   //   _SOFT_FLOAT_
995   //   __RECIP_PRECISION__
996   //   __APPLE_ALTIVEC__
997   //   __VSX__
998   //   __RECIP__
999   //   __RECIPF__
1000   //   __RSQRTE__
1001   //   __RSQRTEF__
1002   //   _SOFT_DOUBLE_
1003   //   __NO_LWSYNC__
1004   //   __HAVE_BSWAP__
1005   //   __LONGDOUBLE128
1006   //   __CMODEL_MEDIUM__
1007   //   __CMODEL_LARGE__
1008   //   _CALL_SYSV
1009   //   _CALL_DARWIN
1010   //   __NO_FPRS__
1011 }
1012 
1013 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1014   Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1015     .Case("7400", true)
1016     .Case("g4", true)
1017     .Case("7450", true)
1018     .Case("g4+", true)
1019     .Case("970", true)
1020     .Case("g5", true)
1021     .Case("pwr6", true)
1022     .Case("pwr7", true)
1023     .Case("ppc64", true)
1024     .Default(false);
1025 
1026   Features["qpx"] = (CPU == "a2q");
1027 }
1028 
1029 bool PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1030                                          StringRef Name,
1031                                          bool Enabled) const {
1032   if (Name == "altivec" || Name == "fprnd" || Name == "mfocrf" ||
1033       Name == "popcntd" || Name == "qpx") {
1034     Features[Name] = Enabled;
1035     return true;
1036   }
1037 
1038   return false;
1039 }
1040 
1041 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1042   return Feature == "powerpc";
1043 }
1044 
1045 
1046 const char * const PPCTargetInfo::GCCRegNames[] = {
1047   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1048   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1049   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1050   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1051   "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1052   "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1053   "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1054   "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1055   "mq", "lr", "ctr", "ap",
1056   "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1057   "xer",
1058   "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1059   "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1060   "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1061   "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1062   "vrsave", "vscr",
1063   "spe_acc", "spefscr",
1064   "sfp"
1065 };
1066 
1067 void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1068                                    unsigned &NumNames) const {
1069   Names = GCCRegNames;
1070   NumNames = llvm::array_lengthof(GCCRegNames);
1071 }
1072 
1073 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1074   // While some of these aliases do map to different registers
1075   // they still share the same register name.
1076   { { "0" }, "r0" },
1077   { { "1"}, "r1" },
1078   { { "2" }, "r2" },
1079   { { "3" }, "r3" },
1080   { { "4" }, "r4" },
1081   { { "5" }, "r5" },
1082   { { "6" }, "r6" },
1083   { { "7" }, "r7" },
1084   { { "8" }, "r8" },
1085   { { "9" }, "r9" },
1086   { { "10" }, "r10" },
1087   { { "11" }, "r11" },
1088   { { "12" }, "r12" },
1089   { { "13" }, "r13" },
1090   { { "14" }, "r14" },
1091   { { "15" }, "r15" },
1092   { { "16" }, "r16" },
1093   { { "17" }, "r17" },
1094   { { "18" }, "r18" },
1095   { { "19" }, "r19" },
1096   { { "20" }, "r20" },
1097   { { "21" }, "r21" },
1098   { { "22" }, "r22" },
1099   { { "23" }, "r23" },
1100   { { "24" }, "r24" },
1101   { { "25" }, "r25" },
1102   { { "26" }, "r26" },
1103   { { "27" }, "r27" },
1104   { { "28" }, "r28" },
1105   { { "29" }, "r29" },
1106   { { "30" }, "r30" },
1107   { { "31" }, "r31" },
1108   { { "fr0" }, "f0" },
1109   { { "fr1" }, "f1" },
1110   { { "fr2" }, "f2" },
1111   { { "fr3" }, "f3" },
1112   { { "fr4" }, "f4" },
1113   { { "fr5" }, "f5" },
1114   { { "fr6" }, "f6" },
1115   { { "fr7" }, "f7" },
1116   { { "fr8" }, "f8" },
1117   { { "fr9" }, "f9" },
1118   { { "fr10" }, "f10" },
1119   { { "fr11" }, "f11" },
1120   { { "fr12" }, "f12" },
1121   { { "fr13" }, "f13" },
1122   { { "fr14" }, "f14" },
1123   { { "fr15" }, "f15" },
1124   { { "fr16" }, "f16" },
1125   { { "fr17" }, "f17" },
1126   { { "fr18" }, "f18" },
1127   { { "fr19" }, "f19" },
1128   { { "fr20" }, "f20" },
1129   { { "fr21" }, "f21" },
1130   { { "fr22" }, "f22" },
1131   { { "fr23" }, "f23" },
1132   { { "fr24" }, "f24" },
1133   { { "fr25" }, "f25" },
1134   { { "fr26" }, "f26" },
1135   { { "fr27" }, "f27" },
1136   { { "fr28" }, "f28" },
1137   { { "fr29" }, "f29" },
1138   { { "fr30" }, "f30" },
1139   { { "fr31" }, "f31" },
1140   { { "cc" }, "cr0" },
1141 };
1142 
1143 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1144                                      unsigned &NumAliases) const {
1145   Aliases = GCCRegAliases;
1146   NumAliases = llvm::array_lengthof(GCCRegAliases);
1147 }
1148 } // end anonymous namespace.
1149 
1150 namespace {
1151 class PPC32TargetInfo : public PPCTargetInfo {
1152 public:
1153   PPC32TargetInfo(const std::string &triple) : PPCTargetInfo(triple) {
1154     DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1155                         "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
1156 
1157     switch (getTriple().getOS()) {
1158     case llvm::Triple::Linux:
1159     case llvm::Triple::FreeBSD:
1160     case llvm::Triple::NetBSD:
1161       SizeType = UnsignedInt;
1162       PtrDiffType = SignedInt;
1163       IntPtrType = SignedInt;
1164       break;
1165     default:
1166       break;
1167     }
1168 
1169     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1170       LongDoubleWidth = LongDoubleAlign = 64;
1171       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1172     }
1173 
1174     // PPC32 supports atomics up to 4 bytes.
1175     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1176   }
1177 
1178   virtual BuiltinVaListKind getBuiltinVaListKind() const {
1179     // This is the ELF definition, and is overridden by the Darwin sub-target
1180     return TargetInfo::PowerABIBuiltinVaList;
1181   }
1182 };
1183 } // end anonymous namespace.
1184 
1185 namespace {
1186 class PPC64TargetInfo : public PPCTargetInfo {
1187 public:
1188   PPC64TargetInfo(const std::string& triple) : PPCTargetInfo(triple) {
1189     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1190     IntMaxType = SignedLong;
1191     UIntMaxType = UnsignedLong;
1192     Int64Type = SignedLong;
1193 
1194     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1195       LongDoubleWidth = LongDoubleAlign = 64;
1196       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1197       DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1198                           "i64:64:64-f32:32:32-f64:64:64-f128:64:64-"
1199                           "v128:128:128-n32:64";
1200     } else
1201       DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1202                           "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
1203                           "v128:128:128-n32:64";
1204 
1205     // PPC64 supports atomics up to 8 bytes.
1206     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1207   }
1208   virtual BuiltinVaListKind getBuiltinVaListKind() const {
1209     return TargetInfo::CharPtrBuiltinVaList;
1210   }
1211 };
1212 } // end anonymous namespace.
1213 
1214 
1215 namespace {
1216 class DarwinPPC32TargetInfo :
1217   public DarwinTargetInfo<PPC32TargetInfo> {
1218 public:
1219   DarwinPPC32TargetInfo(const std::string& triple)
1220     : DarwinTargetInfo<PPC32TargetInfo>(triple) {
1221     HasAlignMac68kSupport = true;
1222     BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1223     PtrDiffType = SignedInt;	// for http://llvm.org/bugs/show_bug.cgi?id=15726
1224     LongLongAlign = 32;
1225     SuitableAlign = 128;
1226     DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1227                         "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32";
1228   }
1229   virtual BuiltinVaListKind getBuiltinVaListKind() const {
1230     return TargetInfo::CharPtrBuiltinVaList;
1231   }
1232 };
1233 
1234 class DarwinPPC64TargetInfo :
1235   public DarwinTargetInfo<PPC64TargetInfo> {
1236 public:
1237   DarwinPPC64TargetInfo(const std::string& triple)
1238     : DarwinTargetInfo<PPC64TargetInfo>(triple) {
1239     HasAlignMac68kSupport = true;
1240     SuitableAlign = 128;
1241     DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1242                         "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64";
1243   }
1244 };
1245 } // end anonymous namespace.
1246 
1247 namespace {
1248   static const unsigned NVPTXAddrSpaceMap[] = {
1249     1,    // opencl_global
1250     3,    // opencl_local
1251     4,    // opencl_constant
1252     1,    // cuda_device
1253     4,    // cuda_constant
1254     3,    // cuda_shared
1255   };
1256   class NVPTXTargetInfo : public TargetInfo {
1257     static const char * const GCCRegNames[];
1258     static const Builtin::Info BuiltinInfo[];
1259     std::vector<StringRef> AvailableFeatures;
1260   public:
1261     NVPTXTargetInfo(const std::string& triple) : TargetInfo(triple) {
1262       BigEndian = false;
1263       TLSSupported = false;
1264       LongWidth = LongAlign = 64;
1265       AddrSpaceMap = &NVPTXAddrSpaceMap;
1266       // Define available target features
1267       // These must be defined in sorted order!
1268       NoAsmVariants = true;
1269     }
1270     virtual void getTargetDefines(const LangOptions &Opts,
1271                                   MacroBuilder &Builder) const {
1272       Builder.defineMacro("__PTX__");
1273       Builder.defineMacro("__NVPTX__");
1274     }
1275     virtual void getTargetBuiltins(const Builtin::Info *&Records,
1276                                    unsigned &NumRecords) const {
1277       Records = BuiltinInfo;
1278       NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1279     }
1280     virtual bool hasFeature(StringRef Feature) const {
1281       return Feature == "ptx" || Feature == "nvptx";
1282     }
1283 
1284     virtual void getGCCRegNames(const char * const *&Names,
1285                                 unsigned &NumNames) const;
1286     virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1287                                   unsigned &NumAliases) const {
1288       // No aliases.
1289       Aliases = 0;
1290       NumAliases = 0;
1291     }
1292     virtual bool validateAsmConstraint(const char *&Name,
1293                                        TargetInfo::ConstraintInfo &info) const {
1294       // FIXME: implement
1295       return true;
1296     }
1297     virtual const char *getClobbers() const {
1298       // FIXME: Is this really right?
1299       return "";
1300     }
1301     virtual BuiltinVaListKind getBuiltinVaListKind() const {
1302       // FIXME: implement
1303       return TargetInfo::CharPtrBuiltinVaList;
1304     }
1305     virtual bool setCPU(const std::string &Name) {
1306       bool Valid = llvm::StringSwitch<bool>(Name)
1307         .Case("sm_20", true)
1308         .Case("sm_21", true)
1309         .Case("sm_30", true)
1310         .Case("sm_35", true)
1311         .Default(false);
1312 
1313       return Valid;
1314     }
1315     virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1316                                    StringRef Name,
1317                                    bool Enabled) const;
1318   };
1319 
1320   const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1321 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1322 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1323                                               ALL_LANGUAGES },
1324 #include "clang/Basic/BuiltinsNVPTX.def"
1325   };
1326 
1327   const char * const NVPTXTargetInfo::GCCRegNames[] = {
1328     "r0"
1329   };
1330 
1331   void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1332                                      unsigned &NumNames) const {
1333     Names = GCCRegNames;
1334     NumNames = llvm::array_lengthof(GCCRegNames);
1335   }
1336 
1337   bool NVPTXTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1338                                           StringRef Name,
1339                                           bool Enabled) const {
1340     if(std::binary_search(AvailableFeatures.begin(), AvailableFeatures.end(),
1341                           Name)) {
1342       Features[Name] = Enabled;
1343       return true;
1344     } else {
1345       return false;
1346     }
1347   }
1348 
1349   class NVPTX32TargetInfo : public NVPTXTargetInfo {
1350   public:
1351     NVPTX32TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) {
1352       PointerWidth = PointerAlign = 32;
1353       SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt;
1354       DescriptionString
1355         = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1356           "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1357           "n16:32:64";
1358   }
1359   };
1360 
1361   class NVPTX64TargetInfo : public NVPTXTargetInfo {
1362   public:
1363     NVPTX64TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) {
1364       PointerWidth = PointerAlign = 64;
1365       SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong;
1366       DescriptionString
1367         = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1368           "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1369           "n16:32:64";
1370   }
1371   };
1372 }
1373 
1374 namespace {
1375 
1376 static const unsigned R600AddrSpaceMap[] = {
1377   1,    // opencl_global
1378   3,    // opencl_local
1379   2,    // opencl_constant
1380   1,    // cuda_device
1381   2,    // cuda_constant
1382   3     // cuda_shared
1383 };
1384 
1385 static const char *DescriptionStringR600 =
1386   "e"
1387   "-p:32:32:32"
1388   "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32"
1389   "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1390   "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1391   "-n32:64";
1392 
1393 static const char *DescriptionStringR600DoubleOps =
1394   "e"
1395   "-p:32:32:32"
1396   "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1397   "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1398   "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1399   "-n32:64";
1400 
1401 static const char *DescriptionStringSI =
1402   "e"
1403   "-p:64:64:64"
1404   "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1405   "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1406   "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1407   "-n32:64";
1408 
1409 class R600TargetInfo : public TargetInfo {
1410   /// \brief The GPU profiles supported by the R600 target.
1411   enum GPUKind {
1412     GK_NONE,
1413     GK_R600,
1414     GK_R600_DOUBLE_OPS,
1415     GK_R700,
1416     GK_R700_DOUBLE_OPS,
1417     GK_EVERGREEN,
1418     GK_EVERGREEN_DOUBLE_OPS,
1419     GK_NORTHERN_ISLANDS,
1420     GK_CAYMAN,
1421     GK_SOUTHERN_ISLANDS
1422   } GPU;
1423 
1424 public:
1425   R600TargetInfo(const std::string& triple)
1426     : TargetInfo(triple),
1427       GPU(GK_R600) {
1428     DescriptionString = DescriptionStringR600;
1429     AddrSpaceMap = &R600AddrSpaceMap;
1430   }
1431 
1432   virtual const char * getClobbers() const {
1433     return "";
1434   }
1435 
1436   virtual void getGCCRegNames(const char * const *&Names,
1437                               unsigned &numNames) const  {
1438     Names = NULL;
1439     numNames = 0;
1440   }
1441 
1442   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1443                                 unsigned &NumAliases) const {
1444     Aliases = NULL;
1445     NumAliases = 0;
1446   }
1447 
1448   virtual bool validateAsmConstraint(const char *&Name,
1449                                      TargetInfo::ConstraintInfo &info) const {
1450     return true;
1451   }
1452 
1453   virtual void getTargetBuiltins(const Builtin::Info *&Records,
1454                                  unsigned &NumRecords) const {
1455     Records = NULL;
1456     NumRecords = 0;
1457   }
1458 
1459 
1460   virtual void getTargetDefines(const LangOptions &Opts,
1461                                 MacroBuilder &Builder) const {
1462     Builder.defineMacro("__R600__");
1463   }
1464 
1465   virtual BuiltinVaListKind getBuiltinVaListKind() const {
1466     return TargetInfo::CharPtrBuiltinVaList;
1467   }
1468 
1469   virtual bool setCPU(const std::string &Name) {
1470     GPU = llvm::StringSwitch<GPUKind>(Name)
1471       .Case("r600" ,    GK_R600)
1472       .Case("rv610",    GK_R600)
1473       .Case("rv620",    GK_R600)
1474       .Case("rv630",    GK_R600)
1475       .Case("rv635",    GK_R600)
1476       .Case("rs780",    GK_R600)
1477       .Case("rs880",    GK_R600)
1478       .Case("rv670",    GK_R600_DOUBLE_OPS)
1479       .Case("rv710",    GK_R700)
1480       .Case("rv730",    GK_R700)
1481       .Case("rv740",    GK_R700_DOUBLE_OPS)
1482       .Case("rv770",    GK_R700_DOUBLE_OPS)
1483       .Case("palm",     GK_EVERGREEN)
1484       .Case("cedar",    GK_EVERGREEN)
1485       .Case("sumo",     GK_EVERGREEN)
1486       .Case("sumo2",    GK_EVERGREEN)
1487       .Case("redwood",  GK_EVERGREEN)
1488       .Case("juniper",  GK_EVERGREEN)
1489       .Case("hemlock",  GK_EVERGREEN_DOUBLE_OPS)
1490       .Case("cypress",  GK_EVERGREEN_DOUBLE_OPS)
1491       .Case("barts",    GK_NORTHERN_ISLANDS)
1492       .Case("turks",    GK_NORTHERN_ISLANDS)
1493       .Case("caicos",   GK_NORTHERN_ISLANDS)
1494       .Case("cayman",   GK_CAYMAN)
1495       .Case("aruba",    GK_CAYMAN)
1496       .Case("tahiti",   GK_SOUTHERN_ISLANDS)
1497       .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1498       .Case("verde",    GK_SOUTHERN_ISLANDS)
1499       .Case("oland",    GK_SOUTHERN_ISLANDS)
1500       .Default(GK_NONE);
1501 
1502     if (GPU == GK_NONE) {
1503       return false;
1504     }
1505 
1506     // Set the correct data layout
1507     switch (GPU) {
1508     case GK_NONE:
1509     case GK_R600:
1510     case GK_R700:
1511     case GK_EVERGREEN:
1512     case GK_NORTHERN_ISLANDS:
1513       DescriptionString = DescriptionStringR600;
1514       break;
1515     case GK_R600_DOUBLE_OPS:
1516     case GK_R700_DOUBLE_OPS:
1517     case GK_EVERGREEN_DOUBLE_OPS:
1518     case GK_CAYMAN:
1519       DescriptionString = DescriptionStringR600DoubleOps;
1520       break;
1521     case GK_SOUTHERN_ISLANDS:
1522       DescriptionString = DescriptionStringSI;
1523       break;
1524     }
1525 
1526     return true;
1527   }
1528 };
1529 
1530 } // end anonymous namespace
1531 
1532 namespace {
1533 // MBlaze abstract base class
1534 class MBlazeTargetInfo : public TargetInfo {
1535   static const char * const GCCRegNames[];
1536   static const TargetInfo::GCCRegAlias GCCRegAliases[];
1537 
1538 public:
1539   MBlazeTargetInfo(const std::string& triple) : TargetInfo(triple) {
1540     DescriptionString = "E-p:32:32:32-i8:8:8-i16:16:16";
1541   }
1542 
1543   virtual void getTargetBuiltins(const Builtin::Info *&Records,
1544                                  unsigned &NumRecords) const {
1545     // FIXME: Implement.
1546     Records = 0;
1547     NumRecords = 0;
1548   }
1549 
1550   virtual void getTargetDefines(const LangOptions &Opts,
1551                                 MacroBuilder &Builder) const;
1552 
1553   virtual bool hasFeature(StringRef Feature) const {
1554     return Feature == "mblaze";
1555   }
1556 
1557   virtual BuiltinVaListKind getBuiltinVaListKind() const {
1558     return TargetInfo::CharPtrBuiltinVaList;
1559   }
1560   virtual const char *getTargetPrefix() const {
1561     return "mblaze";
1562   }
1563   virtual void getGCCRegNames(const char * const *&Names,
1564                               unsigned &NumNames) const;
1565   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1566                                 unsigned &NumAliases) const;
1567   virtual bool validateAsmConstraint(const char *&Name,
1568                                      TargetInfo::ConstraintInfo &Info) const {
1569     switch (*Name) {
1570     default: return false;
1571     case 'O': // Zero
1572       return true;
1573     case 'b': // Base register
1574     case 'f': // Floating point register
1575       Info.setAllowsRegister();
1576       return true;
1577     }
1578   }
1579   virtual const char *getClobbers() const {
1580     return "";
1581   }
1582 };
1583 
1584 /// MBlazeTargetInfo::getTargetDefines - Return a set of the MBlaze-specific
1585 /// #defines that are not tied to a specific subtarget.
1586 void MBlazeTargetInfo::getTargetDefines(const LangOptions &Opts,
1587                                      MacroBuilder &Builder) const {
1588   // Target identification.
1589   Builder.defineMacro("__microblaze__");
1590   Builder.defineMacro("_ARCH_MICROBLAZE");
1591   Builder.defineMacro("__MICROBLAZE__");
1592 
1593   // Target properties.
1594   Builder.defineMacro("_BIG_ENDIAN");
1595   Builder.defineMacro("__BIG_ENDIAN__");
1596 
1597   // Subtarget options.
1598   Builder.defineMacro("__REGISTER_PREFIX__", "");
1599 }
1600 
1601 
1602 const char * const MBlazeTargetInfo::GCCRegNames[] = {
1603   "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
1604   "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
1605   "r16",  "r17",  "r18",  "r19",  "r20",  "r21",  "r22",  "r23",
1606   "r24",  "r25",  "r26",  "r27",  "r28",  "r29",  "r30",  "r31",
1607   "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
1608   "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
1609   "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
1610   "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
1611   "hi",   "lo",   "accum","rmsr", "$fcc1","$fcc2","$fcc3","$fcc4",
1612   "$fcc5","$fcc6","$fcc7","$ap",  "$rap", "$frp"
1613 };
1614 
1615 void MBlazeTargetInfo::getGCCRegNames(const char * const *&Names,
1616                                    unsigned &NumNames) const {
1617   Names = GCCRegNames;
1618   NumNames = llvm::array_lengthof(GCCRegNames);
1619 }
1620 
1621 const TargetInfo::GCCRegAlias MBlazeTargetInfo::GCCRegAliases[] = {
1622   { {"f0"},  "r0" },
1623   { {"f1"},  "r1" },
1624   { {"f2"},  "r2" },
1625   { {"f3"},  "r3" },
1626   { {"f4"},  "r4" },
1627   { {"f5"},  "r5" },
1628   { {"f6"},  "r6" },
1629   { {"f7"},  "r7" },
1630   { {"f8"},  "r8" },
1631   { {"f9"},  "r9" },
1632   { {"f10"}, "r10" },
1633   { {"f11"}, "r11" },
1634   { {"f12"}, "r12" },
1635   { {"f13"}, "r13" },
1636   { {"f14"}, "r14" },
1637   { {"f15"}, "r15" },
1638   { {"f16"}, "r16" },
1639   { {"f17"}, "r17" },
1640   { {"f18"}, "r18" },
1641   { {"f19"}, "r19" },
1642   { {"f20"}, "r20" },
1643   { {"f21"}, "r21" },
1644   { {"f22"}, "r22" },
1645   { {"f23"}, "r23" },
1646   { {"f24"}, "r24" },
1647   { {"f25"}, "r25" },
1648   { {"f26"}, "r26" },
1649   { {"f27"}, "r27" },
1650   { {"f28"}, "r28" },
1651   { {"f29"}, "r29" },
1652   { {"f30"}, "r30" },
1653   { {"f31"}, "r31" },
1654 };
1655 
1656 void MBlazeTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1657                                      unsigned &NumAliases) const {
1658   Aliases = GCCRegAliases;
1659   NumAliases = llvm::array_lengthof(GCCRegAliases);
1660 }
1661 } // end anonymous namespace.
1662 
1663 namespace {
1664 // Namespace for x86 abstract base class
1665 const Builtin::Info BuiltinInfo[] = {
1666 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1667 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1668                                               ALL_LANGUAGES },
1669 #include "clang/Basic/BuiltinsX86.def"
1670 };
1671 
1672 static const char* const GCCRegNames[] = {
1673   "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1674   "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1675   "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1676   "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1677   "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1678   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1679   "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1680   "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1681   "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1682 };
1683 
1684 const TargetInfo::AddlRegName AddlRegNames[] = {
1685   { { "al", "ah", "eax", "rax" }, 0 },
1686   { { "bl", "bh", "ebx", "rbx" }, 3 },
1687   { { "cl", "ch", "ecx", "rcx" }, 2 },
1688   { { "dl", "dh", "edx", "rdx" }, 1 },
1689   { { "esi", "rsi" }, 4 },
1690   { { "edi", "rdi" }, 5 },
1691   { { "esp", "rsp" }, 7 },
1692   { { "ebp", "rbp" }, 6 },
1693 };
1694 
1695 // X86 target abstract base class; x86-32 and x86-64 are very close, so
1696 // most of the implementation can be shared.
1697 class X86TargetInfo : public TargetInfo {
1698   enum X86SSEEnum {
1699     NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2
1700   } SSELevel;
1701   enum MMX3DNowEnum {
1702     NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1703   } MMX3DNowLevel;
1704 
1705   bool HasAES;
1706   bool HasPCLMUL;
1707   bool HasLZCNT;
1708   bool HasRDRND;
1709   bool HasBMI;
1710   bool HasBMI2;
1711   bool HasPOPCNT;
1712   bool HasRTM;
1713   bool HasPRFCHW;
1714   bool HasRDSEED;
1715   bool HasSSE4a;
1716   bool HasFMA4;
1717   bool HasFMA;
1718   bool HasXOP;
1719   bool HasF16C;
1720 
1721   /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1722   ///
1723   /// Each enumeration represents a particular CPU supported by Clang. These
1724   /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1725   enum CPUKind {
1726     CK_Generic,
1727 
1728     /// \name i386
1729     /// i386-generation processors.
1730     //@{
1731     CK_i386,
1732     //@}
1733 
1734     /// \name i486
1735     /// i486-generation processors.
1736     //@{
1737     CK_i486,
1738     CK_WinChipC6,
1739     CK_WinChip2,
1740     CK_C3,
1741     //@}
1742 
1743     /// \name i586
1744     /// i586-generation processors, P5 microarchitecture based.
1745     //@{
1746     CK_i586,
1747     CK_Pentium,
1748     CK_PentiumMMX,
1749     //@}
1750 
1751     /// \name i686
1752     /// i686-generation processors, P6 / Pentium M microarchitecture based.
1753     //@{
1754     CK_i686,
1755     CK_PentiumPro,
1756     CK_Pentium2,
1757     CK_Pentium3,
1758     CK_Pentium3M,
1759     CK_PentiumM,
1760     CK_C3_2,
1761 
1762     /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1763     /// Clang however has some logic to suport this.
1764     // FIXME: Warn, deprecate, and potentially remove this.
1765     CK_Yonah,
1766     //@}
1767 
1768     /// \name Netburst
1769     /// Netburst microarchitecture based processors.
1770     //@{
1771     CK_Pentium4,
1772     CK_Pentium4M,
1773     CK_Prescott,
1774     CK_Nocona,
1775     //@}
1776 
1777     /// \name Core
1778     /// Core microarchitecture based processors.
1779     //@{
1780     CK_Core2,
1781 
1782     /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1783     /// codename which GCC no longer accepts as an option to -march, but Clang
1784     /// has some logic for recognizing it.
1785     // FIXME: Warn, deprecate, and potentially remove this.
1786     CK_Penryn,
1787     //@}
1788 
1789     /// \name Atom
1790     /// Atom processors
1791     //@{
1792     CK_Atom,
1793     //@}
1794 
1795     /// \name Nehalem
1796     /// Nehalem microarchitecture based processors.
1797     //@{
1798     CK_Corei7,
1799     CK_Corei7AVX,
1800     CK_CoreAVXi,
1801     CK_CoreAVX2,
1802     //@}
1803 
1804     /// \name K6
1805     /// K6 architecture processors.
1806     //@{
1807     CK_K6,
1808     CK_K6_2,
1809     CK_K6_3,
1810     //@}
1811 
1812     /// \name K7
1813     /// K7 architecture processors.
1814     //@{
1815     CK_Athlon,
1816     CK_AthlonThunderbird,
1817     CK_Athlon4,
1818     CK_AthlonXP,
1819     CK_AthlonMP,
1820     //@}
1821 
1822     /// \name K8
1823     /// K8 architecture processors.
1824     //@{
1825     CK_Athlon64,
1826     CK_Athlon64SSE3,
1827     CK_AthlonFX,
1828     CK_K8,
1829     CK_K8SSE3,
1830     CK_Opteron,
1831     CK_OpteronSSE3,
1832     CK_AMDFAM10,
1833     //@}
1834 
1835     /// \name Bobcat
1836     /// Bobcat architecture processors.
1837     //@{
1838     CK_BTVER1,
1839     CK_BTVER2,
1840     //@}
1841 
1842     /// \name Bulldozer
1843     /// Bulldozer architecture processors.
1844     //@{
1845     CK_BDVER1,
1846     CK_BDVER2,
1847     //@}
1848 
1849     /// This specification is deprecated and will be removed in the future.
1850     /// Users should prefer \see CK_K8.
1851     // FIXME: Warn on this when the CPU is set to it.
1852     CK_x86_64,
1853     //@}
1854 
1855     /// \name Geode
1856     /// Geode processors.
1857     //@{
1858     CK_Geode
1859     //@}
1860   } CPU;
1861 
1862 public:
1863   X86TargetInfo(const std::string& triple)
1864     : TargetInfo(triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1865       HasAES(false), HasPCLMUL(false), HasLZCNT(false), HasRDRND(false),
1866       HasBMI(false), HasBMI2(false), HasPOPCNT(false), HasRTM(false),
1867       HasPRFCHW(false), HasRDSEED(false), HasSSE4a(false), HasFMA4(false),
1868       HasFMA(false), HasXOP(false), HasF16C(false), CPU(CK_Generic) {
1869     BigEndian = false;
1870     LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1871   }
1872   virtual unsigned getFloatEvalMethod() const {
1873     // X87 evaluates with 80 bits "long double" precision.
1874     return SSELevel == NoSSE ? 2 : 0;
1875   }
1876   virtual void getTargetBuiltins(const Builtin::Info *&Records,
1877                                  unsigned &NumRecords) const {
1878     Records = BuiltinInfo;
1879     NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1880   }
1881   virtual void getGCCRegNames(const char * const *&Names,
1882                               unsigned &NumNames) const {
1883     Names = GCCRegNames;
1884     NumNames = llvm::array_lengthof(GCCRegNames);
1885   }
1886   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1887                                 unsigned &NumAliases) const {
1888     Aliases = 0;
1889     NumAliases = 0;
1890   }
1891   virtual void getGCCAddlRegNames(const AddlRegName *&Names,
1892                                   unsigned &NumNames) const {
1893     Names = AddlRegNames;
1894     NumNames = llvm::array_lengthof(AddlRegNames);
1895   }
1896   virtual bool validateAsmConstraint(const char *&Name,
1897                                      TargetInfo::ConstraintInfo &info) const;
1898   virtual std::string convertConstraint(const char *&Constraint) const;
1899   virtual const char *getClobbers() const {
1900     return "~{dirflag},~{fpsr},~{flags}";
1901   }
1902   virtual void getTargetDefines(const LangOptions &Opts,
1903                                 MacroBuilder &Builder) const;
1904   virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
1905                                  StringRef Name,
1906                                  bool Enabled) const;
1907   virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
1908   virtual bool hasFeature(StringRef Feature) const;
1909   virtual void HandleTargetFeatures(std::vector<std::string> &Features);
1910   virtual const char* getABI() const {
1911     if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
1912       return "avx";
1913     else if (getTriple().getArch() == llvm::Triple::x86 &&
1914              MMX3DNowLevel == NoMMX3DNow)
1915       return "no-mmx";
1916     return "";
1917   }
1918   virtual bool setCPU(const std::string &Name) {
1919     CPU = llvm::StringSwitch<CPUKind>(Name)
1920       .Case("i386", CK_i386)
1921       .Case("i486", CK_i486)
1922       .Case("winchip-c6", CK_WinChipC6)
1923       .Case("winchip2", CK_WinChip2)
1924       .Case("c3", CK_C3)
1925       .Case("i586", CK_i586)
1926       .Case("pentium", CK_Pentium)
1927       .Case("pentium-mmx", CK_PentiumMMX)
1928       .Case("i686", CK_i686)
1929       .Case("pentiumpro", CK_PentiumPro)
1930       .Case("pentium2", CK_Pentium2)
1931       .Case("pentium3", CK_Pentium3)
1932       .Case("pentium3m", CK_Pentium3M)
1933       .Case("pentium-m", CK_PentiumM)
1934       .Case("c3-2", CK_C3_2)
1935       .Case("yonah", CK_Yonah)
1936       .Case("pentium4", CK_Pentium4)
1937       .Case("pentium4m", CK_Pentium4M)
1938       .Case("prescott", CK_Prescott)
1939       .Case("nocona", CK_Nocona)
1940       .Case("core2", CK_Core2)
1941       .Case("penryn", CK_Penryn)
1942       .Case("atom", CK_Atom)
1943       .Case("corei7", CK_Corei7)
1944       .Case("corei7-avx", CK_Corei7AVX)
1945       .Case("core-avx-i", CK_CoreAVXi)
1946       .Case("core-avx2", CK_CoreAVX2)
1947       .Case("k6", CK_K6)
1948       .Case("k6-2", CK_K6_2)
1949       .Case("k6-3", CK_K6_3)
1950       .Case("athlon", CK_Athlon)
1951       .Case("athlon-tbird", CK_AthlonThunderbird)
1952       .Case("athlon-4", CK_Athlon4)
1953       .Case("athlon-xp", CK_AthlonXP)
1954       .Case("athlon-mp", CK_AthlonMP)
1955       .Case("athlon64", CK_Athlon64)
1956       .Case("athlon64-sse3", CK_Athlon64SSE3)
1957       .Case("athlon-fx", CK_AthlonFX)
1958       .Case("k8", CK_K8)
1959       .Case("k8-sse3", CK_K8SSE3)
1960       .Case("opteron", CK_Opteron)
1961       .Case("opteron-sse3", CK_OpteronSSE3)
1962       .Case("amdfam10", CK_AMDFAM10)
1963       .Case("btver1", CK_BTVER1)
1964       .Case("btver2", CK_BTVER2)
1965       .Case("bdver1", CK_BDVER1)
1966       .Case("bdver2", CK_BDVER2)
1967       .Case("x86-64", CK_x86_64)
1968       .Case("geode", CK_Geode)
1969       .Default(CK_Generic);
1970 
1971     // Perform any per-CPU checks necessary to determine if this CPU is
1972     // acceptable.
1973     // FIXME: This results in terrible diagnostics. Clang just says the CPU is
1974     // invalid without explaining *why*.
1975     switch (CPU) {
1976     case CK_Generic:
1977       // No processor selected!
1978       return false;
1979 
1980     case CK_i386:
1981     case CK_i486:
1982     case CK_WinChipC6:
1983     case CK_WinChip2:
1984     case CK_C3:
1985     case CK_i586:
1986     case CK_Pentium:
1987     case CK_PentiumMMX:
1988     case CK_i686:
1989     case CK_PentiumPro:
1990     case CK_Pentium2:
1991     case CK_Pentium3:
1992     case CK_Pentium3M:
1993     case CK_PentiumM:
1994     case CK_Yonah:
1995     case CK_C3_2:
1996     case CK_Pentium4:
1997     case CK_Pentium4M:
1998     case CK_Prescott:
1999     case CK_K6:
2000     case CK_K6_2:
2001     case CK_K6_3:
2002     case CK_Athlon:
2003     case CK_AthlonThunderbird:
2004     case CK_Athlon4:
2005     case CK_AthlonXP:
2006     case CK_AthlonMP:
2007     case CK_Geode:
2008       // Only accept certain architectures when compiling in 32-bit mode.
2009       if (getTriple().getArch() != llvm::Triple::x86)
2010         return false;
2011 
2012       // Fallthrough
2013     case CK_Nocona:
2014     case CK_Core2:
2015     case CK_Penryn:
2016     case CK_Atom:
2017     case CK_Corei7:
2018     case CK_Corei7AVX:
2019     case CK_CoreAVXi:
2020     case CK_CoreAVX2:
2021     case CK_Athlon64:
2022     case CK_Athlon64SSE3:
2023     case CK_AthlonFX:
2024     case CK_K8:
2025     case CK_K8SSE3:
2026     case CK_Opteron:
2027     case CK_OpteronSSE3:
2028     case CK_AMDFAM10:
2029     case CK_BTVER1:
2030     case CK_BTVER2:
2031     case CK_BDVER1:
2032     case CK_BDVER2:
2033     case CK_x86_64:
2034       return true;
2035     }
2036     llvm_unreachable("Unhandled CPU kind");
2037   }
2038 
2039   virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
2040     // We accept all non-ARM calling conventions
2041     return (CC == CC_X86ThisCall ||
2042             CC == CC_X86FastCall ||
2043             CC == CC_X86StdCall ||
2044             CC == CC_C ||
2045             CC == CC_X86Pascal ||
2046             CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2047   }
2048 
2049   virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
2050     return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2051   }
2052 };
2053 
2054 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2055   // FIXME: This should not be here.
2056   Features["3dnow"] = false;
2057   Features["3dnowa"] = false;
2058   Features["mmx"] = false;
2059   Features["sse"] = false;
2060   Features["sse2"] = false;
2061   Features["sse3"] = false;
2062   Features["ssse3"] = false;
2063   Features["sse41"] = false;
2064   Features["sse42"] = false;
2065   Features["sse4a"] = false;
2066   Features["aes"] = false;
2067   Features["pclmul"] = false;
2068   Features["avx"] = false;
2069   Features["avx2"] = false;
2070   Features["lzcnt"] = false;
2071   Features["rdrand"] = false;
2072   Features["bmi"] = false;
2073   Features["bmi2"] = false;
2074   Features["popcnt"] = false;
2075   Features["rtm"] = false;
2076   Features["prfchw"] = false;
2077   Features["rdseed"] = false;
2078   Features["fma4"] = false;
2079   Features["fma"] = false;
2080   Features["xop"] = false;
2081   Features["f16c"] = false;
2082 
2083   // FIXME: This *really* should not be here.
2084 
2085   // X86_64 always has SSE2.
2086   if (getTriple().getArch() == llvm::Triple::x86_64)
2087     setFeatureEnabled(Features, "sse2", true);
2088 
2089   switch (CPU) {
2090   case CK_Generic:
2091   case CK_i386:
2092   case CK_i486:
2093   case CK_i586:
2094   case CK_Pentium:
2095   case CK_i686:
2096   case CK_PentiumPro:
2097     break;
2098   case CK_PentiumMMX:
2099   case CK_Pentium2:
2100     setFeatureEnabled(Features, "mmx", true);
2101     break;
2102   case CK_Pentium3:
2103   case CK_Pentium3M:
2104     setFeatureEnabled(Features, "sse", true);
2105     break;
2106   case CK_PentiumM:
2107   case CK_Pentium4:
2108   case CK_Pentium4M:
2109   case CK_x86_64:
2110     setFeatureEnabled(Features, "sse2", true);
2111     break;
2112   case CK_Yonah:
2113   case CK_Prescott:
2114   case CK_Nocona:
2115     setFeatureEnabled(Features, "sse3", true);
2116     break;
2117   case CK_Core2:
2118     setFeatureEnabled(Features, "ssse3", true);
2119     break;
2120   case CK_Penryn:
2121     setFeatureEnabled(Features, "sse4.1", true);
2122     break;
2123   case CK_Atom:
2124     setFeatureEnabled(Features, "ssse3", true);
2125     break;
2126   case CK_Corei7:
2127     setFeatureEnabled(Features, "sse4", true);
2128     break;
2129   case CK_Corei7AVX:
2130     setFeatureEnabled(Features, "avx", true);
2131     setFeatureEnabled(Features, "aes", true);
2132     setFeatureEnabled(Features, "pclmul", true);
2133     break;
2134   case CK_CoreAVXi:
2135     setFeatureEnabled(Features, "avx", true);
2136     setFeatureEnabled(Features, "aes", true);
2137     setFeatureEnabled(Features, "pclmul", true);
2138     setFeatureEnabled(Features, "rdrnd", true);
2139     setFeatureEnabled(Features, "f16c", true);
2140     break;
2141   case CK_CoreAVX2:
2142     setFeatureEnabled(Features, "avx2", true);
2143     setFeatureEnabled(Features, "aes", true);
2144     setFeatureEnabled(Features, "pclmul", true);
2145     setFeatureEnabled(Features, "lzcnt", true);
2146     setFeatureEnabled(Features, "rdrnd", true);
2147     setFeatureEnabled(Features, "f16c", true);
2148     setFeatureEnabled(Features, "bmi", true);
2149     setFeatureEnabled(Features, "bmi2", true);
2150     setFeatureEnabled(Features, "rtm", true);
2151     setFeatureEnabled(Features, "fma", true);
2152     break;
2153   case CK_K6:
2154   case CK_WinChipC6:
2155     setFeatureEnabled(Features, "mmx", true);
2156     break;
2157   case CK_K6_2:
2158   case CK_K6_3:
2159   case CK_WinChip2:
2160   case CK_C3:
2161     setFeatureEnabled(Features, "3dnow", true);
2162     break;
2163   case CK_Athlon:
2164   case CK_AthlonThunderbird:
2165   case CK_Geode:
2166     setFeatureEnabled(Features, "3dnowa", true);
2167     break;
2168   case CK_Athlon4:
2169   case CK_AthlonXP:
2170   case CK_AthlonMP:
2171     setFeatureEnabled(Features, "sse", true);
2172     setFeatureEnabled(Features, "3dnowa", true);
2173     break;
2174   case CK_K8:
2175   case CK_Opteron:
2176   case CK_Athlon64:
2177   case CK_AthlonFX:
2178     setFeatureEnabled(Features, "sse2", true);
2179     setFeatureEnabled(Features, "3dnowa", true);
2180     break;
2181   case CK_K8SSE3:
2182   case CK_OpteronSSE3:
2183   case CK_Athlon64SSE3:
2184     setFeatureEnabled(Features, "sse3", true);
2185     setFeatureEnabled(Features, "3dnowa", true);
2186     break;
2187   case CK_AMDFAM10:
2188     setFeatureEnabled(Features, "sse3", true);
2189     setFeatureEnabled(Features, "sse4a", true);
2190     setFeatureEnabled(Features, "3dnowa", true);
2191     setFeatureEnabled(Features, "lzcnt", true);
2192     setFeatureEnabled(Features, "popcnt", true);
2193     break;
2194   case CK_BTVER1:
2195     setFeatureEnabled(Features, "ssse3", true);
2196     setFeatureEnabled(Features, "sse4a", true);
2197     setFeatureEnabled(Features, "lzcnt", true);
2198     setFeatureEnabled(Features, "popcnt", true);
2199     break;
2200   case CK_BTVER2:
2201     setFeatureEnabled(Features, "avx", true);
2202     setFeatureEnabled(Features, "sse4a", true);
2203     setFeatureEnabled(Features, "lzcnt", true);
2204     setFeatureEnabled(Features, "aes", true);
2205     setFeatureEnabled(Features, "pclmul", true);
2206     setFeatureEnabled(Features, "bmi", true);
2207     setFeatureEnabled(Features, "f16c", true);
2208     break;
2209   case CK_BDVER1:
2210     setFeatureEnabled(Features, "xop", true);
2211     setFeatureEnabled(Features, "lzcnt", true);
2212     setFeatureEnabled(Features, "aes", true);
2213     setFeatureEnabled(Features, "pclmul", true);
2214     break;
2215   case CK_BDVER2:
2216     setFeatureEnabled(Features, "xop", true);
2217     setFeatureEnabled(Features, "lzcnt", true);
2218     setFeatureEnabled(Features, "aes", true);
2219     setFeatureEnabled(Features, "pclmul", true);
2220     setFeatureEnabled(Features, "bmi", true);
2221     setFeatureEnabled(Features, "fma", true);
2222     setFeatureEnabled(Features, "f16c", true);
2223     break;
2224   case CK_C3_2:
2225     setFeatureEnabled(Features, "sse", true);
2226     break;
2227   }
2228 }
2229 
2230 bool X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
2231                                       StringRef Name,
2232                                       bool Enabled) const {
2233   // FIXME: This *really* should not be here.  We need some way of translating
2234   // options into llvm subtarget features.
2235   if (!Features.count(Name) &&
2236       (Name != "sse4" && Name != "sse4.2" && Name != "sse4.1" &&
2237        Name != "rdrnd"))
2238     return false;
2239 
2240   // FIXME: this should probably use a switch with fall through.
2241 
2242   if (Enabled) {
2243     if (Name == "mmx")
2244       Features["mmx"] = true;
2245     else if (Name == "sse")
2246       Features["mmx"] = Features["sse"] = true;
2247     else if (Name == "sse2")
2248       Features["mmx"] = Features["sse"] = Features["sse2"] = true;
2249     else if (Name == "sse3")
2250       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2251         true;
2252     else if (Name == "ssse3")
2253       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2254         Features["ssse3"] = true;
2255     else if (Name == "sse4" || Name == "sse4.2")
2256       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2257         Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2258         Features["popcnt"] = true;
2259     else if (Name == "sse4.1")
2260       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2261         Features["ssse3"] = Features["sse41"] = true;
2262     else if (Name == "3dnow")
2263       Features["mmx"] = Features["3dnow"] = true;
2264     else if (Name == "3dnowa")
2265       Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = true;
2266     else if (Name == "aes")
2267       Features["sse"] = Features["sse2"] = Features["aes"] = true;
2268     else if (Name == "pclmul")
2269       Features["sse"] = Features["sse2"] = Features["pclmul"] = true;
2270     else if (Name == "avx")
2271       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2272         Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2273         Features["popcnt"] = Features["avx"] = true;
2274     else if (Name == "avx2")
2275       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2276         Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2277         Features["popcnt"] = Features["avx"] = Features["avx2"] = true;
2278     else if (Name == "fma")
2279       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2280         Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2281         Features["popcnt"] = Features["avx"] = Features["fma"] = true;
2282     else if (Name == "fma4")
2283       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2284         Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2285         Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2286         Features["fma4"] = true;
2287     else if (Name == "xop")
2288       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2289         Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2290         Features["popcnt"] = Features["avx"] = Features["sse4a"] =
2291         Features["fma4"] = Features["xop"] = true;
2292     else if (Name == "sse4a")
2293       Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] =
2294         Features["sse4a"] = true;
2295     else if (Name == "lzcnt")
2296       Features["lzcnt"] = true;
2297     else if (Name == "rdrnd")
2298       Features["rdrand"] = true;
2299     else if (Name == "bmi")
2300       Features["bmi"] = true;
2301     else if (Name == "bmi2")
2302       Features["bmi2"] = true;
2303     else if (Name == "popcnt")
2304       Features["popcnt"] = true;
2305     else if (Name == "f16c")
2306       Features["f16c"] = true;
2307     else if (Name == "rtm")
2308       Features["rtm"] = true;
2309     else if (Name == "prfchw")
2310       Features["prfchw"] = true;
2311     else if (Name == "rdseed")
2312       Features["rdseed"] = true;
2313   } else {
2314     if (Name == "mmx")
2315       Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = false;
2316     else if (Name == "sse")
2317       Features["sse"] = Features["sse2"] = Features["sse3"] =
2318         Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2319         Features["sse4a"] = Features["avx"] = Features["avx2"] =
2320         Features["fma"] = Features["fma4"] = Features["aes"] =
2321         Features["pclmul"] = Features["xop"] = false;
2322     else if (Name == "sse2")
2323       Features["sse2"] = Features["sse3"] = Features["ssse3"] =
2324         Features["sse41"] = Features["sse42"] = Features["sse4a"] =
2325         Features["avx"] = Features["avx2"] = Features["fma"] =
2326         Features["fma4"] = Features["aes"] = Features["pclmul"] =
2327         Features["xop"] = false;
2328     else if (Name == "sse3")
2329       Features["sse3"] = Features["ssse3"] = Features["sse41"] =
2330         Features["sse42"] = Features["sse4a"] = Features["avx"] =
2331         Features["avx2"] = Features["fma"] = Features["fma4"] =
2332         Features["xop"] = false;
2333     else if (Name == "ssse3")
2334       Features["ssse3"] = Features["sse41"] = Features["sse42"] =
2335         Features["avx"] = Features["avx2"] = Features["fma"] = false;
2336     else if (Name == "sse4" || Name == "sse4.1")
2337       Features["sse41"] = Features["sse42"] = Features["avx"] =
2338         Features["avx2"] = Features["fma"] = false;
2339     else if (Name == "sse4.2")
2340       Features["sse42"] = Features["avx"] = Features["avx2"] =
2341         Features["fma"] = false;
2342     else if (Name == "3dnow")
2343       Features["3dnow"] = Features["3dnowa"] = false;
2344     else if (Name == "3dnowa")
2345       Features["3dnowa"] = false;
2346     else if (Name == "aes")
2347       Features["aes"] = false;
2348     else if (Name == "pclmul")
2349       Features["pclmul"] = false;
2350     else if (Name == "avx")
2351       Features["avx"] = Features["avx2"] = Features["fma"] =
2352         Features["fma4"] = Features["xop"] = false;
2353     else if (Name == "avx2")
2354       Features["avx2"] = false;
2355     else if (Name == "fma")
2356       Features["fma"] = false;
2357     else if (Name == "sse4a")
2358       Features["sse4a"] = Features["fma4"] = Features["xop"] = false;
2359     else if (Name == "lzcnt")
2360       Features["lzcnt"] = false;
2361     else if (Name == "rdrnd")
2362       Features["rdrand"] = false;
2363     else if (Name == "bmi")
2364       Features["bmi"] = false;
2365     else if (Name == "bmi2")
2366       Features["bmi2"] = false;
2367     else if (Name == "popcnt")
2368       Features["popcnt"] = false;
2369     else if (Name == "fma4")
2370       Features["fma4"] = Features["xop"] = false;
2371     else if (Name == "xop")
2372       Features["xop"] = false;
2373     else if (Name == "f16c")
2374       Features["f16c"] = false;
2375     else if (Name == "rtm")
2376       Features["rtm"] = false;
2377     else if (Name == "prfchw")
2378       Features["prfchw"] = false;
2379     else if (Name == "rdseed")
2380       Features["rdseed"] = false;
2381   }
2382 
2383   return true;
2384 }
2385 
2386 /// HandleTargetOptions - Perform initialization based on the user
2387 /// configured set of features.
2388 void X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features) {
2389   // Remember the maximum enabled sselevel.
2390   for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2391     // Ignore disabled features.
2392     if (Features[i][0] == '-')
2393       continue;
2394 
2395     StringRef Feature = StringRef(Features[i]).substr(1);
2396 
2397     if (Feature == "aes") {
2398       HasAES = true;
2399       continue;
2400     }
2401 
2402     if (Feature == "pclmul") {
2403       HasPCLMUL = true;
2404       continue;
2405     }
2406 
2407     if (Feature == "lzcnt") {
2408       HasLZCNT = true;
2409       continue;
2410     }
2411 
2412     if (Feature == "rdrand") {
2413       HasRDRND = true;
2414       continue;
2415     }
2416 
2417     if (Feature == "bmi") {
2418       HasBMI = true;
2419       continue;
2420     }
2421 
2422     if (Feature == "bmi2") {
2423       HasBMI2 = true;
2424       continue;
2425     }
2426 
2427     if (Feature == "popcnt") {
2428       HasPOPCNT = true;
2429       continue;
2430     }
2431 
2432     if (Feature == "rtm") {
2433       HasRTM = true;
2434       continue;
2435     }
2436 
2437     if (Feature == "prfchw") {
2438       HasPRFCHW = true;
2439       continue;
2440     }
2441 
2442     if (Feature == "rdseed") {
2443       HasRDSEED = true;
2444       continue;
2445     }
2446 
2447     if (Feature == "sse4a") {
2448       HasSSE4a = true;
2449       continue;
2450     }
2451 
2452     if (Feature == "fma4") {
2453       HasFMA4 = true;
2454       continue;
2455     }
2456 
2457     if (Feature == "fma") {
2458       HasFMA = true;
2459       continue;
2460     }
2461 
2462     if (Feature == "xop") {
2463       HasXOP = true;
2464       continue;
2465     }
2466 
2467     if (Feature == "f16c") {
2468       HasF16C = true;
2469       continue;
2470     }
2471 
2472     assert(Features[i][0] == '+' && "Invalid target feature!");
2473     X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2474       .Case("avx2", AVX2)
2475       .Case("avx", AVX)
2476       .Case("sse42", SSE42)
2477       .Case("sse41", SSE41)
2478       .Case("ssse3", SSSE3)
2479       .Case("sse3", SSE3)
2480       .Case("sse2", SSE2)
2481       .Case("sse", SSE1)
2482       .Default(NoSSE);
2483     SSELevel = std::max(SSELevel, Level);
2484 
2485     MMX3DNowEnum ThreeDNowLevel =
2486       llvm::StringSwitch<MMX3DNowEnum>(Feature)
2487         .Case("3dnowa", AMD3DNowAthlon)
2488         .Case("3dnow", AMD3DNow)
2489         .Case("mmx", MMX)
2490         .Default(NoMMX3DNow);
2491 
2492     MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2493   }
2494 
2495   // Don't tell the backend if we're turning off mmx; it will end up disabling
2496   // SSE, which we don't want.
2497   std::vector<std::string>::iterator it;
2498   it = std::find(Features.begin(), Features.end(), "-mmx");
2499   if (it != Features.end())
2500     Features.erase(it);
2501 }
2502 
2503 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2504 /// definitions for this particular subtarget.
2505 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2506                                      MacroBuilder &Builder) const {
2507   // Target identification.
2508   if (getTriple().getArch() == llvm::Triple::x86_64) {
2509     Builder.defineMacro("__amd64__");
2510     Builder.defineMacro("__amd64");
2511     Builder.defineMacro("__x86_64");
2512     Builder.defineMacro("__x86_64__");
2513   } else {
2514     DefineStd(Builder, "i386", Opts);
2515   }
2516 
2517   // Subtarget options.
2518   // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2519   // truly should be based on -mtune options.
2520   switch (CPU) {
2521   case CK_Generic:
2522     break;
2523   case CK_i386:
2524     // The rest are coming from the i386 define above.
2525     Builder.defineMacro("__tune_i386__");
2526     break;
2527   case CK_i486:
2528   case CK_WinChipC6:
2529   case CK_WinChip2:
2530   case CK_C3:
2531     defineCPUMacros(Builder, "i486");
2532     break;
2533   case CK_PentiumMMX:
2534     Builder.defineMacro("__pentium_mmx__");
2535     Builder.defineMacro("__tune_pentium_mmx__");
2536     // Fallthrough
2537   case CK_i586:
2538   case CK_Pentium:
2539     defineCPUMacros(Builder, "i586");
2540     defineCPUMacros(Builder, "pentium");
2541     break;
2542   case CK_Pentium3:
2543   case CK_Pentium3M:
2544   case CK_PentiumM:
2545     Builder.defineMacro("__tune_pentium3__");
2546     // Fallthrough
2547   case CK_Pentium2:
2548   case CK_C3_2:
2549     Builder.defineMacro("__tune_pentium2__");
2550     // Fallthrough
2551   case CK_PentiumPro:
2552     Builder.defineMacro("__tune_i686__");
2553     Builder.defineMacro("__tune_pentiumpro__");
2554     // Fallthrough
2555   case CK_i686:
2556     Builder.defineMacro("__i686");
2557     Builder.defineMacro("__i686__");
2558     // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2559     Builder.defineMacro("__pentiumpro");
2560     Builder.defineMacro("__pentiumpro__");
2561     break;
2562   case CK_Pentium4:
2563   case CK_Pentium4M:
2564     defineCPUMacros(Builder, "pentium4");
2565     break;
2566   case CK_Yonah:
2567   case CK_Prescott:
2568   case CK_Nocona:
2569     defineCPUMacros(Builder, "nocona");
2570     break;
2571   case CK_Core2:
2572   case CK_Penryn:
2573     defineCPUMacros(Builder, "core2");
2574     break;
2575   case CK_Atom:
2576     defineCPUMacros(Builder, "atom");
2577     break;
2578   case CK_Corei7:
2579   case CK_Corei7AVX:
2580   case CK_CoreAVXi:
2581   case CK_CoreAVX2:
2582     defineCPUMacros(Builder, "corei7");
2583     break;
2584   case CK_K6_2:
2585     Builder.defineMacro("__k6_2__");
2586     Builder.defineMacro("__tune_k6_2__");
2587     // Fallthrough
2588   case CK_K6_3:
2589     if (CPU != CK_K6_2) {  // In case of fallthrough
2590       // FIXME: GCC may be enabling these in cases where some other k6
2591       // architecture is specified but -m3dnow is explicitly provided. The
2592       // exact semantics need to be determined and emulated here.
2593       Builder.defineMacro("__k6_3__");
2594       Builder.defineMacro("__tune_k6_3__");
2595     }
2596     // Fallthrough
2597   case CK_K6:
2598     defineCPUMacros(Builder, "k6");
2599     break;
2600   case CK_Athlon:
2601   case CK_AthlonThunderbird:
2602   case CK_Athlon4:
2603   case CK_AthlonXP:
2604   case CK_AthlonMP:
2605     defineCPUMacros(Builder, "athlon");
2606     if (SSELevel != NoSSE) {
2607       Builder.defineMacro("__athlon_sse__");
2608       Builder.defineMacro("__tune_athlon_sse__");
2609     }
2610     break;
2611   case CK_K8:
2612   case CK_K8SSE3:
2613   case CK_x86_64:
2614   case CK_Opteron:
2615   case CK_OpteronSSE3:
2616   case CK_Athlon64:
2617   case CK_Athlon64SSE3:
2618   case CK_AthlonFX:
2619     defineCPUMacros(Builder, "k8");
2620     break;
2621   case CK_AMDFAM10:
2622     defineCPUMacros(Builder, "amdfam10");
2623     break;
2624   case CK_BTVER1:
2625     defineCPUMacros(Builder, "btver1");
2626     break;
2627   case CK_BTVER2:
2628     defineCPUMacros(Builder, "btver2");
2629     break;
2630   case CK_BDVER1:
2631     defineCPUMacros(Builder, "bdver1");
2632     break;
2633   case CK_BDVER2:
2634     defineCPUMacros(Builder, "bdver2");
2635     break;
2636   case CK_Geode:
2637     defineCPUMacros(Builder, "geode");
2638     break;
2639   }
2640 
2641   // Target properties.
2642   Builder.defineMacro("__LITTLE_ENDIAN__");
2643   Builder.defineMacro("__REGISTER_PREFIX__", "");
2644 
2645   // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2646   // functions in glibc header files that use FP Stack inline asm which the
2647   // backend can't deal with (PR879).
2648   Builder.defineMacro("__NO_MATH_INLINES");
2649 
2650   if (HasAES)
2651     Builder.defineMacro("__AES__");
2652 
2653   if (HasPCLMUL)
2654     Builder.defineMacro("__PCLMUL__");
2655 
2656   if (HasLZCNT)
2657     Builder.defineMacro("__LZCNT__");
2658 
2659   if (HasRDRND)
2660     Builder.defineMacro("__RDRND__");
2661 
2662   if (HasBMI)
2663     Builder.defineMacro("__BMI__");
2664 
2665   if (HasBMI2)
2666     Builder.defineMacro("__BMI2__");
2667 
2668   if (HasPOPCNT)
2669     Builder.defineMacro("__POPCNT__");
2670 
2671   if (HasRTM)
2672     Builder.defineMacro("__RTM__");
2673 
2674   if (HasPRFCHW)
2675     Builder.defineMacro("__PRFCHW__");
2676 
2677   if (HasRDSEED)
2678     Builder.defineMacro("__RDSEED__");
2679 
2680   if (HasSSE4a)
2681     Builder.defineMacro("__SSE4A__");
2682 
2683   if (HasFMA4)
2684     Builder.defineMacro("__FMA4__");
2685 
2686   if (HasFMA)
2687     Builder.defineMacro("__FMA__");
2688 
2689   if (HasXOP)
2690     Builder.defineMacro("__XOP__");
2691 
2692   if (HasF16C)
2693     Builder.defineMacro("__F16C__");
2694 
2695   // Each case falls through to the previous one here.
2696   switch (SSELevel) {
2697   case AVX2:
2698     Builder.defineMacro("__AVX2__");
2699   case AVX:
2700     Builder.defineMacro("__AVX__");
2701   case SSE42:
2702     Builder.defineMacro("__SSE4_2__");
2703   case SSE41:
2704     Builder.defineMacro("__SSE4_1__");
2705   case SSSE3:
2706     Builder.defineMacro("__SSSE3__");
2707   case SSE3:
2708     Builder.defineMacro("__SSE3__");
2709   case SSE2:
2710     Builder.defineMacro("__SSE2__");
2711     Builder.defineMacro("__SSE2_MATH__");  // -mfp-math=sse always implied.
2712   case SSE1:
2713     Builder.defineMacro("__SSE__");
2714     Builder.defineMacro("__SSE_MATH__");   // -mfp-math=sse always implied.
2715   case NoSSE:
2716     break;
2717   }
2718 
2719   if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
2720     switch (SSELevel) {
2721     case AVX2:
2722     case AVX:
2723     case SSE42:
2724     case SSE41:
2725     case SSSE3:
2726     case SSE3:
2727     case SSE2:
2728       Builder.defineMacro("_M_IX86_FP", Twine(2));
2729       break;
2730     case SSE1:
2731       Builder.defineMacro("_M_IX86_FP", Twine(1));
2732       break;
2733     default:
2734       Builder.defineMacro("_M_IX86_FP", Twine(0));
2735     }
2736   }
2737 
2738   // Each case falls through to the previous one here.
2739   switch (MMX3DNowLevel) {
2740   case AMD3DNowAthlon:
2741     Builder.defineMacro("__3dNOW_A__");
2742   case AMD3DNow:
2743     Builder.defineMacro("__3dNOW__");
2744   case MMX:
2745     Builder.defineMacro("__MMX__");
2746   case NoMMX3DNow:
2747     break;
2748   }
2749 
2750   if (CPU >= CK_i486) {
2751     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
2752     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
2753     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
2754   }
2755   if (CPU >= CK_i586)
2756     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
2757 }
2758 
2759 bool X86TargetInfo::hasFeature(StringRef Feature) const {
2760   return llvm::StringSwitch<bool>(Feature)
2761       .Case("aes", HasAES)
2762       .Case("avx", SSELevel >= AVX)
2763       .Case("avx2", SSELevel >= AVX2)
2764       .Case("bmi", HasBMI)
2765       .Case("bmi2", HasBMI2)
2766       .Case("fma", HasFMA)
2767       .Case("fma4", HasFMA4)
2768       .Case("lzcnt", HasLZCNT)
2769       .Case("rdrnd", HasRDRND)
2770       .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
2771       .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
2772       .Case("mmx", MMX3DNowLevel >= MMX)
2773       .Case("pclmul", HasPCLMUL)
2774       .Case("popcnt", HasPOPCNT)
2775       .Case("rtm", HasRTM)
2776       .Case("prfchw", HasPRFCHW)
2777       .Case("rdseed", HasRDSEED)
2778       .Case("sse", SSELevel >= SSE1)
2779       .Case("sse2", SSELevel >= SSE2)
2780       .Case("sse3", SSELevel >= SSE3)
2781       .Case("ssse3", SSELevel >= SSSE3)
2782       .Case("sse41", SSELevel >= SSE41)
2783       .Case("sse42", SSELevel >= SSE42)
2784       .Case("sse4a", HasSSE4a)
2785       .Case("x86", true)
2786       .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
2787       .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
2788       .Case("xop", HasXOP)
2789       .Case("f16c", HasF16C)
2790       .Default(false);
2791 }
2792 
2793 bool
2794 X86TargetInfo::validateAsmConstraint(const char *&Name,
2795                                      TargetInfo::ConstraintInfo &Info) const {
2796   switch (*Name) {
2797   default: return false;
2798   case 'Y': // first letter of a pair:
2799     switch (*(Name+1)) {
2800     default: return false;
2801     case '0':  // First SSE register.
2802     case 't':  // Any SSE register, when SSE2 is enabled.
2803     case 'i':  // Any SSE register, when SSE2 and inter-unit moves enabled.
2804     case 'm':  // any MMX register, when inter-unit moves enabled.
2805       break;   // falls through to setAllowsRegister.
2806   }
2807   case 'a': // eax.
2808   case 'b': // ebx.
2809   case 'c': // ecx.
2810   case 'd': // edx.
2811   case 'S': // esi.
2812   case 'D': // edi.
2813   case 'A': // edx:eax.
2814   case 'f': // any x87 floating point stack register.
2815   case 't': // top of floating point stack.
2816   case 'u': // second from top of floating point stack.
2817   case 'q': // Any register accessible as [r]l: a, b, c, and d.
2818   case 'y': // Any MMX register.
2819   case 'x': // Any SSE register.
2820   case 'Q': // Any register accessible as [r]h: a, b, c, and d.
2821   case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
2822   case 'l': // "Index" registers: any general register that can be used as an
2823             // index in a base+index memory access.
2824     Info.setAllowsRegister();
2825     return true;
2826   case 'C': // SSE floating point constant.
2827   case 'G': // x87 floating point constant.
2828   case 'e': // 32-bit signed integer constant for use with zero-extending
2829             // x86_64 instructions.
2830   case 'Z': // 32-bit unsigned integer constant for use with zero-extending
2831             // x86_64 instructions.
2832     return true;
2833   }
2834 }
2835 
2836 
2837 std::string
2838 X86TargetInfo::convertConstraint(const char *&Constraint) const {
2839   switch (*Constraint) {
2840   case 'a': return std::string("{ax}");
2841   case 'b': return std::string("{bx}");
2842   case 'c': return std::string("{cx}");
2843   case 'd': return std::string("{dx}");
2844   case 'S': return std::string("{si}");
2845   case 'D': return std::string("{di}");
2846   case 'p': // address
2847     return std::string("im");
2848   case 't': // top of floating point stack.
2849     return std::string("{st}");
2850   case 'u': // second from top of floating point stack.
2851     return std::string("{st(1)}"); // second from top of floating point stack.
2852   default:
2853     return std::string(1, *Constraint);
2854   }
2855 }
2856 } // end anonymous namespace
2857 
2858 namespace {
2859 // X86-32 generic target
2860 class X86_32TargetInfo : public X86TargetInfo {
2861 public:
2862   X86_32TargetInfo(const std::string& triple) : X86TargetInfo(triple) {
2863     DoubleAlign = LongLongAlign = 32;
2864     LongDoubleWidth = 96;
2865     LongDoubleAlign = 32;
2866     SuitableAlign = 128;
2867     DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2868                         "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2869                         "a0:0:64-f80:32:32-n8:16:32-S128";
2870     SizeType = UnsignedInt;
2871     PtrDiffType = SignedInt;
2872     IntPtrType = SignedInt;
2873     RegParmMax = 3;
2874 
2875     // Use fpret for all types.
2876     RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
2877                              (1 << TargetInfo::Double) |
2878                              (1 << TargetInfo::LongDouble));
2879 
2880     // x86-32 has atomics up to 8 bytes
2881     // FIXME: Check that we actually have cmpxchg8b before setting
2882     // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
2883     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
2884   }
2885   virtual BuiltinVaListKind getBuiltinVaListKind() const {
2886     return TargetInfo::CharPtrBuiltinVaList;
2887   }
2888 
2889   int getEHDataRegisterNumber(unsigned RegNo) const {
2890     if (RegNo == 0) return 0;
2891     if (RegNo == 1) return 2;
2892     return -1;
2893   }
2894   virtual bool validateInputSize(StringRef Constraint,
2895                                  unsigned Size) const {
2896     switch (Constraint[0]) {
2897     default: break;
2898     case 'a':
2899     case 'b':
2900     case 'c':
2901     case 'd':
2902       return Size <= 32;
2903     }
2904 
2905     return true;
2906   }
2907 };
2908 } // end anonymous namespace
2909 
2910 namespace {
2911 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
2912 public:
2913   NetBSDI386TargetInfo(const std::string &triple) :
2914     NetBSDTargetInfo<X86_32TargetInfo>(triple) {
2915   }
2916 
2917   virtual unsigned getFloatEvalMethod() const {
2918     // NetBSD defaults to "double" rounding
2919     return 1;
2920   }
2921 };
2922 } // end anonymous namespace
2923 
2924 namespace {
2925 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
2926 public:
2927   OpenBSDI386TargetInfo(const std::string& triple) :
2928     OpenBSDTargetInfo<X86_32TargetInfo>(triple) {
2929     SizeType = UnsignedLong;
2930     IntPtrType = SignedLong;
2931     PtrDiffType = SignedLong;
2932   }
2933 };
2934 } // end anonymous namespace
2935 
2936 namespace {
2937 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
2938 public:
2939   BitrigI386TargetInfo(const std::string& triple) :
2940     BitrigTargetInfo<X86_32TargetInfo>(triple) {
2941     SizeType = UnsignedLong;
2942     IntPtrType = SignedLong;
2943     PtrDiffType = SignedLong;
2944   }
2945 };
2946 } // end anonymous namespace
2947 
2948 namespace {
2949 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
2950 public:
2951   DarwinI386TargetInfo(const std::string& triple) :
2952     DarwinTargetInfo<X86_32TargetInfo>(triple) {
2953     LongDoubleWidth = 128;
2954     LongDoubleAlign = 128;
2955     SuitableAlign = 128;
2956     MaxVectorAlign = 256;
2957     SizeType = UnsignedLong;
2958     IntPtrType = SignedLong;
2959     DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2960                         "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2961                         "a0:0:64-f80:128:128-n8:16:32-S128";
2962     HasAlignMac68kSupport = true;
2963   }
2964 
2965 };
2966 } // end anonymous namespace
2967 
2968 namespace {
2969 // x86-32 Windows target
2970 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
2971 public:
2972   WindowsX86_32TargetInfo(const std::string& triple)
2973     : WindowsTargetInfo<X86_32TargetInfo>(triple) {
2974     TLSSupported = false;
2975     WCharType = UnsignedShort;
2976     DoubleAlign = LongLongAlign = 64;
2977     DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2978                         "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-"
2979                         "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32";
2980   }
2981   virtual void getTargetDefines(const LangOptions &Opts,
2982                                 MacroBuilder &Builder) const {
2983     WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
2984   }
2985 };
2986 } // end anonymous namespace
2987 
2988 namespace {
2989 
2990 // x86-32 Windows Visual Studio target
2991 class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo {
2992 public:
2993   VisualStudioWindowsX86_32TargetInfo(const std::string& triple)
2994     : WindowsX86_32TargetInfo(triple) {
2995     LongDoubleWidth = LongDoubleAlign = 64;
2996     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
2997   }
2998   virtual void getTargetDefines(const LangOptions &Opts,
2999                                 MacroBuilder &Builder) const {
3000     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3001     WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3002     // The value of the following reflects processor type.
3003     // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3004     // We lost the original triple, so we use the default.
3005     Builder.defineMacro("_M_IX86", "600");
3006   }
3007 };
3008 } // end anonymous namespace
3009 
3010 namespace {
3011 // x86-32 MinGW target
3012 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3013 public:
3014   MinGWX86_32TargetInfo(const std::string& triple)
3015     : WindowsX86_32TargetInfo(triple) {
3016   }
3017   virtual void getTargetDefines(const LangOptions &Opts,
3018                                 MacroBuilder &Builder) const {
3019     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3020     DefineStd(Builder, "WIN32", Opts);
3021     DefineStd(Builder, "WINNT", Opts);
3022     Builder.defineMacro("_X86_");
3023     Builder.defineMacro("__MSVCRT__");
3024     Builder.defineMacro("__MINGW32__");
3025 
3026     // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3027     // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3028     if (Opts.MicrosoftExt)
3029       // Provide "as-is" __declspec.
3030       Builder.defineMacro("__declspec", "__declspec");
3031     else
3032       // Provide alias of __attribute__ like mingw32-gcc.
3033       Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3034   }
3035 };
3036 } // end anonymous namespace
3037 
3038 namespace {
3039 // x86-32 Cygwin target
3040 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3041 public:
3042   CygwinX86_32TargetInfo(const std::string& triple)
3043     : X86_32TargetInfo(triple) {
3044     TLSSupported = false;
3045     WCharType = UnsignedShort;
3046     DoubleAlign = LongLongAlign = 64;
3047     DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3048                         "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3049                         "a0:0:64-f80:32:32-n8:16:32-S32";
3050   }
3051   virtual void getTargetDefines(const LangOptions &Opts,
3052                                 MacroBuilder &Builder) const {
3053     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3054     Builder.defineMacro("_X86_");
3055     Builder.defineMacro("__CYGWIN__");
3056     Builder.defineMacro("__CYGWIN32__");
3057     DefineStd(Builder, "unix", Opts);
3058     if (Opts.CPlusPlus)
3059       Builder.defineMacro("_GNU_SOURCE");
3060   }
3061 };
3062 } // end anonymous namespace
3063 
3064 namespace {
3065 // x86-32 Haiku target
3066 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3067 public:
3068   HaikuX86_32TargetInfo(const std::string& triple)
3069     : X86_32TargetInfo(triple) {
3070     SizeType = UnsignedLong;
3071     IntPtrType = SignedLong;
3072     PtrDiffType = SignedLong;
3073     ProcessIDType = SignedLong;
3074     this->UserLabelPrefix = "";
3075     this->TLSSupported = false;
3076   }
3077   virtual void getTargetDefines(const LangOptions &Opts,
3078                                 MacroBuilder &Builder) const {
3079     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3080     Builder.defineMacro("__INTEL__");
3081     Builder.defineMacro("__HAIKU__");
3082   }
3083 };
3084 } // end anonymous namespace
3085 
3086 // RTEMS Target
3087 template<typename Target>
3088 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3089 protected:
3090   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3091                             MacroBuilder &Builder) const {
3092     // RTEMS defines; list based off of gcc output
3093 
3094     Builder.defineMacro("__rtems__");
3095     Builder.defineMacro("__ELF__");
3096   }
3097 public:
3098   RTEMSTargetInfo(const std::string &triple)
3099     : OSTargetInfo<Target>(triple) {
3100       this->UserLabelPrefix = "";
3101 
3102       llvm::Triple Triple(triple);
3103       switch (Triple.getArch()) {
3104         default:
3105         case llvm::Triple::x86:
3106           // this->MCountName = ".mcount";
3107           break;
3108         case llvm::Triple::mips:
3109         case llvm::Triple::mipsel:
3110         case llvm::Triple::ppc:
3111         case llvm::Triple::ppc64:
3112           // this->MCountName = "_mcount";
3113           break;
3114         case llvm::Triple::arm:
3115           // this->MCountName = "__mcount";
3116           break;
3117       }
3118 
3119     }
3120 };
3121 
3122 namespace {
3123 // x86-32 RTEMS target
3124 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3125 public:
3126   RTEMSX86_32TargetInfo(const std::string& triple)
3127     : X86_32TargetInfo(triple) {
3128     SizeType = UnsignedLong;
3129     IntPtrType = SignedLong;
3130     PtrDiffType = SignedLong;
3131     this->UserLabelPrefix = "";
3132   }
3133   virtual void getTargetDefines(const LangOptions &Opts,
3134                                 MacroBuilder &Builder) const {
3135     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3136     Builder.defineMacro("__INTEL__");
3137     Builder.defineMacro("__rtems__");
3138   }
3139 };
3140 } // end anonymous namespace
3141 
3142 namespace {
3143 // x86-64 generic target
3144 class X86_64TargetInfo : public X86TargetInfo {
3145 public:
3146   X86_64TargetInfo(const std::string &triple) : X86TargetInfo(triple) {
3147     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
3148     LongDoubleWidth = 128;
3149     LongDoubleAlign = 128;
3150     LargeArrayMinWidth = 128;
3151     LargeArrayAlign = 128;
3152     SuitableAlign = 128;
3153     IntMaxType = SignedLong;
3154     UIntMaxType = UnsignedLong;
3155     Int64Type = SignedLong;
3156     RegParmMax = 6;
3157 
3158     DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3159                         "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3160                         "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128";
3161 
3162     // Use fpret only for long double.
3163     RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3164 
3165     // Use fp2ret for _Complex long double.
3166     ComplexLongDoubleUsesFP2Ret = true;
3167 
3168     // x86-64 has atomics up to 16 bytes.
3169     // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128
3170     // on CPUs with cmpxchg16b
3171     MaxAtomicPromoteWidth = 128;
3172     MaxAtomicInlineWidth = 64;
3173   }
3174   virtual BuiltinVaListKind getBuiltinVaListKind() const {
3175     return TargetInfo::X86_64ABIBuiltinVaList;
3176   }
3177 
3178   int getEHDataRegisterNumber(unsigned RegNo) const {
3179     if (RegNo == 0) return 0;
3180     if (RegNo == 1) return 1;
3181     return -1;
3182   }
3183 
3184   virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3185     return (CC == CC_Default ||
3186             CC == CC_C ||
3187             CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
3188   }
3189 
3190   virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
3191     return CC_C;
3192   }
3193 
3194 };
3195 } // end anonymous namespace
3196 
3197 namespace {
3198 // x86-64 Windows target
3199 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3200 public:
3201   WindowsX86_64TargetInfo(const std::string& triple)
3202     : WindowsTargetInfo<X86_64TargetInfo>(triple) {
3203     TLSSupported = false;
3204     WCharType = UnsignedShort;
3205     LongWidth = LongAlign = 32;
3206     DoubleAlign = LongLongAlign = 64;
3207     IntMaxType = SignedLongLong;
3208     UIntMaxType = UnsignedLongLong;
3209     Int64Type = SignedLongLong;
3210     SizeType = UnsignedLongLong;
3211     PtrDiffType = SignedLongLong;
3212     IntPtrType = SignedLongLong;
3213     this->UserLabelPrefix = "";
3214   }
3215   virtual void getTargetDefines(const LangOptions &Opts,
3216                                 MacroBuilder &Builder) const {
3217     WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3218     Builder.defineMacro("_WIN64");
3219   }
3220   virtual BuiltinVaListKind getBuiltinVaListKind() const {
3221     return TargetInfo::CharPtrBuiltinVaList;
3222   }
3223 };
3224 } // end anonymous namespace
3225 
3226 namespace {
3227 // x86-64 Windows Visual Studio target
3228 class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo {
3229 public:
3230   VisualStudioWindowsX86_64TargetInfo(const std::string& triple)
3231     : WindowsX86_64TargetInfo(triple) {
3232     LongDoubleWidth = LongDoubleAlign = 64;
3233     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3234   }
3235   virtual void getTargetDefines(const LangOptions &Opts,
3236                                 MacroBuilder &Builder) const {
3237     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3238     WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3239     Builder.defineMacro("_M_X64");
3240     Builder.defineMacro("_M_AMD64");
3241   }
3242 };
3243 } // end anonymous namespace
3244 
3245 namespace {
3246 // x86-64 MinGW target
3247 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3248 public:
3249   MinGWX86_64TargetInfo(const std::string& triple)
3250     : WindowsX86_64TargetInfo(triple) {
3251   }
3252   virtual void getTargetDefines(const LangOptions &Opts,
3253                                 MacroBuilder &Builder) const {
3254     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3255     DefineStd(Builder, "WIN64", Opts);
3256     Builder.defineMacro("__MSVCRT__");
3257     Builder.defineMacro("__MINGW32__");
3258     Builder.defineMacro("__MINGW64__");
3259 
3260     // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3261     // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3262     if (Opts.MicrosoftExt)
3263       // Provide "as-is" __declspec.
3264       Builder.defineMacro("__declspec", "__declspec");
3265     else
3266       // Provide alias of __attribute__ like mingw32-gcc.
3267       Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3268   }
3269 };
3270 } // end anonymous namespace
3271 
3272 namespace {
3273 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3274 public:
3275   DarwinX86_64TargetInfo(const std::string& triple)
3276       : DarwinTargetInfo<X86_64TargetInfo>(triple) {
3277     Int64Type = SignedLongLong;
3278     MaxVectorAlign = 256;
3279   }
3280 };
3281 } // end anonymous namespace
3282 
3283 namespace {
3284 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3285 public:
3286   OpenBSDX86_64TargetInfo(const std::string& triple)
3287       : OpenBSDTargetInfo<X86_64TargetInfo>(triple) {
3288     IntMaxType = SignedLongLong;
3289     UIntMaxType = UnsignedLongLong;
3290     Int64Type = SignedLongLong;
3291   }
3292 };
3293 } // end anonymous namespace
3294 
3295 namespace {
3296 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3297 public:
3298   BitrigX86_64TargetInfo(const std::string& triple)
3299       : BitrigTargetInfo<X86_64TargetInfo>(triple) {
3300      IntMaxType = SignedLongLong;
3301      UIntMaxType = UnsignedLongLong;
3302      Int64Type = SignedLongLong;
3303   }
3304 };
3305 }
3306 
3307 namespace {
3308 class AArch64TargetInfo : public TargetInfo {
3309   static const char * const GCCRegNames[];
3310   static const TargetInfo::GCCRegAlias GCCRegAliases[];
3311 
3312   static const Builtin::Info BuiltinInfo[];
3313 public:
3314   AArch64TargetInfo(const std::string& triple) : TargetInfo(triple) {
3315     BigEndian = false;
3316     LongWidth = LongAlign = 64;
3317     LongDoubleWidth = LongDoubleAlign = 128;
3318     PointerWidth = PointerAlign = 64;
3319     SuitableAlign = 128;
3320     DescriptionString = "e-p:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3321                         "i64:64:64-i128:128:128-f32:32:32-f64:64:64-"
3322                         "f128:128:128-n32:64-S128";
3323 
3324     WCharType = UnsignedInt;
3325     LongDoubleFormat = &llvm::APFloat::IEEEquad;
3326 
3327     // AArch64 backend supports 64-bit operations at the moment. In principle
3328     // 128-bit is possible if register-pairs are used.
3329     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3330 
3331     TheCXXABI.set(TargetCXXABI::GenericAArch64);
3332   }
3333   virtual void getTargetDefines(const LangOptions &Opts,
3334                                 MacroBuilder &Builder) const {
3335     // GCC defines theses currently
3336     Builder.defineMacro("__aarch64__");
3337     Builder.defineMacro("__AARCH64EL__");
3338 
3339     // ACLE predefines. Many can only have one possible value on v8 AArch64.
3340 
3341     // FIXME: these were written based on an unreleased version of a 32-bit ACLE
3342     // which was intended to be compatible with a 64-bit implementation. They
3343     // will need updating when a real 64-bit ACLE exists. Particularly pressing
3344     // instances are: __ARM_ARCH_ISA_ARM, __ARM_ARCH_ISA_THUMB, __ARM_PCS.
3345     Builder.defineMacro("__ARM_ACLE",         "101");
3346     Builder.defineMacro("__ARM_ARCH",         "8");
3347     Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
3348 
3349     Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
3350     Builder.defineMacro("__ARM_FEATURE_CLZ");
3351     Builder.defineMacro("__ARM_FEATURE_FMA");
3352 
3353     // FIXME: ACLE 1.1 reserves bit 4. Will almost certainly come to mean
3354     // 128-bit LDXP present, at which point this becomes 0x1f.
3355     Builder.defineMacro("__ARM_FEATURE_LDREX", "0xf");
3356 
3357     // 0xe implies support for half, single and double precision operations.
3358     Builder.defineMacro("__ARM_FP", "0xe");
3359 
3360     // PCS specifies this for SysV variants, which is all we support. Other ABIs
3361     // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
3362     Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
3363 
3364     if (Opts.FastMath || Opts.FiniteMathOnly)
3365       Builder.defineMacro("__ARM_FP_FAST");
3366 
3367     if ((Opts.C99 || Opts.C11) && !Opts.Freestanding)
3368       Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
3369 
3370     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
3371                         Opts.ShortWChar ? "2" : "4");
3372 
3373     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
3374                         Opts.ShortEnums ? "1" : "4");
3375 
3376     if (BigEndian)
3377       Builder.defineMacro("__ARM_BIG_ENDIAN");
3378   }
3379   virtual void getTargetBuiltins(const Builtin::Info *&Records,
3380                                  unsigned &NumRecords) const {
3381     Records = BuiltinInfo;
3382     NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin;
3383   }
3384   virtual bool hasFeature(StringRef Feature) const {
3385     return Feature == "aarch64";
3386   }
3387   virtual void getGCCRegNames(const char * const *&Names,
3388                               unsigned &NumNames) const;
3389   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3390                                 unsigned &NumAliases) const;
3391 
3392   virtual bool isCLZForZeroUndef() const { return false; }
3393 
3394   virtual bool validateAsmConstraint(const char *&Name,
3395                                      TargetInfo::ConstraintInfo &Info) const {
3396     switch (*Name) {
3397     default: return false;
3398     case 'w': // An FP/SIMD vector register
3399       Info.setAllowsRegister();
3400       return true;
3401     case 'I': // Constant that can be used with an ADD instruction
3402     case 'J': // Constant that can be used with a SUB instruction
3403     case 'K': // Constant that can be used with a 32-bit logical instruction
3404     case 'L': // Constant that can be used with a 64-bit logical instruction
3405     case 'M': // Constant that can be used as a 32-bit MOV immediate
3406     case 'N': // Constant that can be used as a 64-bit MOV immediate
3407     case 'Y': // Floating point constant zero
3408     case 'Z': // Integer constant zero
3409       return true;
3410     case 'Q': // A memory reference with base register and no offset
3411       Info.setAllowsMemory();
3412       return true;
3413     case 'S': // A symbolic address
3414       Info.setAllowsRegister();
3415       return true;
3416     case 'U':
3417       // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be
3418       // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
3419       // Usa: An absolute symbolic address
3420       // Ush: The high part (bits 32:12) of a pc-relative symbolic address
3421       llvm_unreachable("FIXME: Unimplemented support for bizarre constraints");
3422     }
3423   }
3424 
3425   virtual const char *getClobbers() const {
3426     // There are no AArch64 clobbers shared by all asm statements.
3427     return "";
3428   }
3429 
3430   virtual BuiltinVaListKind getBuiltinVaListKind() const {
3431     return TargetInfo::AArch64ABIBuiltinVaList;
3432   }
3433 };
3434 
3435 const char * const AArch64TargetInfo::GCCRegNames[] = {
3436   "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7",
3437   "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15",
3438   "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23",
3439   "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr",
3440 
3441   "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
3442   "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
3443   "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
3444   "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr",
3445 
3446   "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
3447   "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15",
3448   "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23",
3449   "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31",
3450 
3451   "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7",
3452   "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15",
3453   "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23",
3454   "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31",
3455 
3456   "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3457   "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3458   "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3459   "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3460 
3461   "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3462   "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3463   "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3464   "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3465 
3466   "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3467   "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
3468   "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23",
3469   "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31"
3470 };
3471 
3472 void AArch64TargetInfo::getGCCRegNames(const char * const *&Names,
3473                                        unsigned &NumNames) const {
3474   Names = GCCRegNames;
3475   NumNames = llvm::array_lengthof(GCCRegNames);
3476 }
3477 
3478 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
3479   { { "x16" }, "ip0"},
3480   { { "x17" }, "ip1"},
3481   { { "x29" }, "fp" },
3482   { { "x30" }, "lr" }
3483 };
3484 
3485 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3486                                          unsigned &NumAliases) const {
3487   Aliases = GCCRegAliases;
3488   NumAliases = llvm::array_lengthof(GCCRegAliases);
3489 
3490 }
3491 
3492 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
3493 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3494 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3495                                               ALL_LANGUAGES },
3496 #include "clang/Basic/BuiltinsAArch64.def"
3497 };
3498 
3499 } // end anonymous namespace
3500 
3501 namespace {
3502 class ARMTargetInfo : public TargetInfo {
3503   // Possible FPU choices.
3504   enum FPUMode {
3505     VFP2FPU = (1 << 0),
3506     VFP3FPU = (1 << 1),
3507     VFP4FPU = (1 << 2),
3508     NeonFPU = (1 << 3)
3509   };
3510 
3511   static bool FPUModeIsVFP(FPUMode Mode) {
3512     return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU);
3513   }
3514 
3515   static const TargetInfo::GCCRegAlias GCCRegAliases[];
3516   static const char * const GCCRegNames[];
3517 
3518   std::string ABI, CPU;
3519 
3520   unsigned FPU : 4;
3521 
3522   unsigned IsAAPCS : 1;
3523   unsigned IsThumb : 1;
3524 
3525   // Initialized via features.
3526   unsigned SoftFloat : 1;
3527   unsigned SoftFloatABI : 1;
3528 
3529   static const Builtin::Info BuiltinInfo[];
3530 
3531   static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3532     // On linux, binaries targeting old cpus call functions in libgcc to
3533     // perform atomic operations. The implementation in libgcc then calls into
3534     // the kernel which on armv6 and newer uses ldrex and strex. The net result
3535     // is that if we assume the kernel is at least as recent as the hardware,
3536     // it is safe to use atomic instructions on armv6 and newer.
3537     if (T.getOS() != llvm::Triple::Linux &&
3538         T.getOS() != llvm::Triple::FreeBSD &&
3539         T.getOS() != llvm::Triple::Bitrig)
3540       return false;
3541     StringRef ArchName = T.getArchName();
3542     if (T.getArch() == llvm::Triple::arm) {
3543       if (!ArchName.startswith("armv"))
3544         return false;
3545       StringRef VersionStr = ArchName.substr(4);
3546       unsigned Version;
3547       if (VersionStr.getAsInteger(10, Version))
3548         return false;
3549       return Version >= 6;
3550     }
3551     assert(T.getArch() == llvm::Triple::thumb);
3552     if (!ArchName.startswith("thumbv"))
3553       return false;
3554     StringRef VersionStr = ArchName.substr(6);
3555     unsigned Version;
3556     if (VersionStr.getAsInteger(10, Version))
3557       return false;
3558     return Version >= 7;
3559   }
3560 
3561 public:
3562   ARMTargetInfo(const std::string &TripleStr)
3563     : TargetInfo(TripleStr), ABI("aapcs-linux"), CPU("arm1136j-s"), IsAAPCS(true)
3564   {
3565     BigEndian = false;
3566     SizeType = UnsignedInt;
3567     PtrDiffType = SignedInt;
3568     // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3569     WCharType = UnsignedInt;
3570 
3571     // {} in inline assembly are neon specifiers, not assembly variant
3572     // specifiers.
3573     NoAsmVariants = true;
3574 
3575     // FIXME: Should we just treat this as a feature?
3576     IsThumb = getTriple().getArchName().startswith("thumb");
3577     if (IsThumb) {
3578       // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3579       // so set preferred for small types to 32.
3580       DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3581                            "i64:64:64-f32:32:32-f64:64:64-"
3582                            "v64:64:64-v128:64:128-a0:0:32-n32-S64");
3583     } else {
3584       DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3585                            "i64:64:64-f32:32:32-f64:64:64-"
3586                            "v64:64:64-v128:64:128-a0:0:64-n32-S64");
3587     }
3588 
3589     // ARM targets default to using the ARM C++ ABI.
3590     TheCXXABI.set(TargetCXXABI::GenericARM);
3591 
3592     // ARM has atomics up to 8 bytes
3593     MaxAtomicPromoteWidth = 64;
3594     if (shouldUseInlineAtomic(getTriple()))
3595       MaxAtomicInlineWidth = 64;
3596 
3597     // Do force alignment of members that follow zero length bitfields.  If
3598     // the alignment of the zero-length bitfield is greater than the member
3599     // that follows it, `bar', `bar' will be aligned as the  type of the
3600     // zero length bitfield.
3601     UseZeroLengthBitfieldAlignment = true;
3602   }
3603   virtual const char *getABI() const { return ABI.c_str(); }
3604   virtual bool setABI(const std::string &Name) {
3605     ABI = Name;
3606 
3607     // The defaults (above) are for AAPCS, check if we need to change them.
3608     //
3609     // FIXME: We need support for -meabi... we could just mangle it into the
3610     // name.
3611     if (Name == "apcs-gnu") {
3612       DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3613       // size_t is unsigned int on FreeBSD.
3614       if (getTriple().getOS() != llvm::Triple::FreeBSD)
3615         SizeType = UnsignedLong;
3616 
3617       // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3618       WCharType = SignedInt;
3619 
3620       // Do not respect the alignment of bit-field types when laying out
3621       // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3622       UseBitFieldTypeAlignment = false;
3623 
3624       /// gcc forces the alignment to 4 bytes, regardless of the type of the
3625       /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
3626       /// gcc.
3627       ZeroLengthBitfieldBoundary = 32;
3628 
3629       IsAAPCS = false;
3630 
3631       if (IsThumb) {
3632         // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3633         // so set preferred for small types to 32.
3634         DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3635                              "i64:32:64-f32:32:32-f64:32:64-"
3636                              "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3637       } else {
3638         DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3639                              "i64:32:64-f32:32:32-f64:32:64-"
3640                              "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3641       }
3642 
3643       // FIXME: Override "preferred align" for double and long long.
3644     } else if (Name == "aapcs" || Name == "aapcs-vfp") {
3645       // size_t is unsigned long on Darwin.
3646       if (getTriple().isOSDarwin())
3647         SizeType = UnsignedLong;
3648       IsAAPCS = true;
3649       // FIXME: Enumerated types are variable width in straight AAPCS.
3650     } else if (Name == "aapcs-linux") {
3651       IsAAPCS = true;
3652     } else
3653       return false;
3654 
3655     return true;
3656   }
3657 
3658   void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
3659     if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3660       Features["vfp2"] = true;
3661     else if (CPU == "cortex-a8" || CPU == "cortex-a15" ||
3662              CPU == "cortex-a9" || CPU == "cortex-a9-mp")
3663       Features["neon"] = true;
3664     else if (CPU == "swift" || CPU == "cortex-a7") {
3665       Features["vfp4"] = true;
3666       Features["neon"] = true;
3667     }
3668   }
3669 
3670   virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
3671                                  StringRef Name,
3672                                  bool Enabled) const {
3673     if (Name == "soft-float" || Name == "soft-float-abi" ||
3674         Name == "vfp2" || Name == "vfp3" || Name == "vfp4" || Name == "neon" ||
3675         Name == "d16" || Name == "neonfp") {
3676       Features[Name] = Enabled;
3677     } else
3678       return false;
3679 
3680     return true;
3681   }
3682 
3683   virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
3684     FPU = 0;
3685     SoftFloat = SoftFloatABI = false;
3686     for (unsigned i = 0, e = Features.size(); i != e; ++i) {
3687       if (Features[i] == "+soft-float")
3688         SoftFloat = true;
3689       else if (Features[i] == "+soft-float-abi")
3690         SoftFloatABI = true;
3691       else if (Features[i] == "+vfp2")
3692         FPU |= VFP2FPU;
3693       else if (Features[i] == "+vfp3")
3694         FPU |= VFP3FPU;
3695       else if (Features[i] == "+vfp4")
3696         FPU |= VFP4FPU;
3697       else if (Features[i] == "+neon")
3698         FPU |= NeonFPU;
3699     }
3700 
3701     // Remove front-end specific options which the backend handles differently.
3702     std::vector<std::string>::iterator it;
3703     it = std::find(Features.begin(), Features.end(), "+soft-float");
3704     if (it != Features.end())
3705       Features.erase(it);
3706     it = std::find(Features.begin(), Features.end(), "+soft-float-abi");
3707     if (it != Features.end())
3708       Features.erase(it);
3709   }
3710 
3711   virtual bool hasFeature(StringRef Feature) const {
3712     return llvm::StringSwitch<bool>(Feature)
3713         .Case("arm", true)
3714         .Case("softfloat", SoftFloat)
3715         .Case("thumb", IsThumb)
3716         .Case("neon", FPU == NeonFPU && !SoftFloat &&
3717               StringRef(getCPUDefineSuffix(CPU)).startswith("7"))
3718         .Default(false);
3719   }
3720   // FIXME: Should we actually have some table instead of these switches?
3721   static const char *getCPUDefineSuffix(StringRef Name) {
3722     return llvm::StringSwitch<const char*>(Name)
3723       .Cases("arm8", "arm810", "4")
3724       .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4")
3725       .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
3726       .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
3727       .Case("ep9312", "4T")
3728       .Cases("arm10tdmi", "arm1020t", "5T")
3729       .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
3730       .Case("arm926ej-s", "5TEJ")
3731       .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
3732       .Cases("xscale", "iwmmxt", "5TE")
3733       .Case("arm1136j-s", "6J")
3734       .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
3735       .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
3736       .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
3737       .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
3738       .Cases("cortex-a9", "cortex-a15", "7A")
3739       .Case("cortex-r5", "7R")
3740       .Case("cortex-a9-mp", "7F")
3741       .Case("swift", "7S")
3742       .Cases("cortex-m3", "cortex-m4", "7M")
3743       .Case("cortex-m0", "6M")
3744       .Default(0);
3745   }
3746   static const char *getCPUProfile(StringRef Name) {
3747     return llvm::StringSwitch<const char*>(Name)
3748       .Cases("cortex-a8", "cortex-a9", "A")
3749       .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M")
3750       .Case("cortex-r5", "R")
3751       .Default("");
3752   }
3753   virtual bool setCPU(const std::string &Name) {
3754     if (!getCPUDefineSuffix(Name))
3755       return false;
3756 
3757     CPU = Name;
3758     return true;
3759   }
3760   virtual void getTargetDefines(const LangOptions &Opts,
3761                                 MacroBuilder &Builder) const {
3762     // Target identification.
3763     Builder.defineMacro("__arm");
3764     Builder.defineMacro("__arm__");
3765 
3766     // Target properties.
3767     Builder.defineMacro("__ARMEL__");
3768     Builder.defineMacro("__LITTLE_ENDIAN__");
3769     Builder.defineMacro("__REGISTER_PREFIX__", "");
3770 
3771     StringRef CPUArch = getCPUDefineSuffix(CPU);
3772     Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
3773     Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
3774     StringRef CPUProfile = getCPUProfile(CPU);
3775     if (!CPUProfile.empty())
3776       Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile);
3777 
3778     // Subtarget options.
3779 
3780     // FIXME: It's more complicated than this and we don't really support
3781     // interworking.
3782     if ('5' <= CPUArch[0] && CPUArch[0] <= '7')
3783       Builder.defineMacro("__THUMB_INTERWORK__");
3784 
3785     if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
3786       // M-class CPUs on Darwin follow AAPCS, but not EABI.
3787       if (!(getTriple().isOSDarwin() && CPUProfile == "M"))
3788         Builder.defineMacro("__ARM_EABI__");
3789       Builder.defineMacro("__ARM_PCS", "1");
3790 
3791       if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
3792         Builder.defineMacro("__ARM_PCS_VFP", "1");
3793     }
3794 
3795     if (SoftFloat)
3796       Builder.defineMacro("__SOFTFP__");
3797 
3798     if (CPU == "xscale")
3799       Builder.defineMacro("__XSCALE__");
3800 
3801     bool IsARMv7 = CPUArch.startswith("7");
3802     if (IsThumb) {
3803       Builder.defineMacro("__THUMBEL__");
3804       Builder.defineMacro("__thumb__");
3805       if (CPUArch == "6T2" || IsARMv7)
3806         Builder.defineMacro("__thumb2__");
3807     }
3808 
3809     // Note, this is always on in gcc, even though it doesn't make sense.
3810     Builder.defineMacro("__APCS_32__");
3811 
3812     if (FPUModeIsVFP((FPUMode) FPU)) {
3813       Builder.defineMacro("__VFP_FP__");
3814       if (FPU & VFP2FPU)
3815         Builder.defineMacro("__ARM_VFPV2__");
3816       if (FPU & VFP3FPU)
3817         Builder.defineMacro("__ARM_VFPV3__");
3818       if (FPU & VFP4FPU)
3819         Builder.defineMacro("__ARM_VFPV4__");
3820     }
3821 
3822     // This only gets set when Neon instructions are actually available, unlike
3823     // the VFP define, hence the soft float and arch check. This is subtly
3824     // different from gcc, we follow the intent which was that it should be set
3825     // when Neon instructions are actually available.
3826     if ((FPU & NeonFPU) && !SoftFloat && IsARMv7)
3827       Builder.defineMacro("__ARM_NEON__");
3828   }
3829   virtual void getTargetBuiltins(const Builtin::Info *&Records,
3830                                  unsigned &NumRecords) const {
3831     Records = BuiltinInfo;
3832     NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
3833   }
3834   virtual bool isCLZForZeroUndef() const { return false; }
3835   virtual BuiltinVaListKind getBuiltinVaListKind() const {
3836     return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
3837   }
3838   virtual void getGCCRegNames(const char * const *&Names,
3839                               unsigned &NumNames) const;
3840   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3841                                 unsigned &NumAliases) const;
3842   virtual bool validateAsmConstraint(const char *&Name,
3843                                      TargetInfo::ConstraintInfo &Info) const {
3844     switch (*Name) {
3845     default: break;
3846     case 'l': // r0-r7
3847     case 'h': // r8-r15
3848     case 'w': // VFP Floating point register single precision
3849     case 'P': // VFP Floating point register double precision
3850       Info.setAllowsRegister();
3851       return true;
3852     case 'Q': // A memory address that is a single base register.
3853       Info.setAllowsMemory();
3854       return true;
3855     case 'U': // a memory reference...
3856       switch (Name[1]) {
3857       case 'q': // ...ARMV4 ldrsb
3858       case 'v': // ...VFP load/store (reg+constant offset)
3859       case 'y': // ...iWMMXt load/store
3860       case 't': // address valid for load/store opaque types wider
3861                 // than 128-bits
3862       case 'n': // valid address for Neon doubleword vector load/store
3863       case 'm': // valid address for Neon element and structure load/store
3864       case 's': // valid address for non-offset loads/stores of quad-word
3865                 // values in four ARM registers
3866         Info.setAllowsMemory();
3867         Name++;
3868         return true;
3869       }
3870     }
3871     return false;
3872   }
3873   virtual std::string convertConstraint(const char *&Constraint) const {
3874     std::string R;
3875     switch (*Constraint) {
3876     case 'U':   // Two-character constraint; add "^" hint for later parsing.
3877       R = std::string("^") + std::string(Constraint, 2);
3878       Constraint++;
3879       break;
3880     case 'p': // 'p' should be translated to 'r' by default.
3881       R = std::string("r");
3882       break;
3883     default:
3884       return std::string(1, *Constraint);
3885     }
3886     return R;
3887   }
3888   virtual bool validateConstraintModifier(StringRef Constraint,
3889                                           const char Modifier,
3890                                           unsigned Size) const {
3891     bool isOutput = (Constraint[0] == '=');
3892     bool isInOut = (Constraint[0] == '+');
3893 
3894     // Strip off constraint modifiers.
3895     while (Constraint[0] == '=' ||
3896            Constraint[0] == '+' ||
3897            Constraint[0] == '&')
3898       Constraint = Constraint.substr(1);
3899 
3900     switch (Constraint[0]) {
3901     default: break;
3902     case 'r': {
3903       switch (Modifier) {
3904       default:
3905         return (isInOut || isOutput || Size <= 32);
3906       case 'q':
3907         // A register of size 32 cannot fit a vector type.
3908         return false;
3909       }
3910     }
3911     }
3912 
3913     return true;
3914   }
3915   virtual const char *getClobbers() const {
3916     // FIXME: Is this really right?
3917     return "";
3918   }
3919 
3920   virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3921     return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
3922   }
3923 
3924   virtual int getEHDataRegisterNumber(unsigned RegNo) const {
3925     if (RegNo == 0) return 0;
3926     if (RegNo == 1) return 1;
3927     return -1;
3928   }
3929 };
3930 
3931 const char * const ARMTargetInfo::GCCRegNames[] = {
3932   // Integer registers
3933   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3934   "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
3935 
3936   // Float registers
3937   "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3938   "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3939   "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3940   "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3941 
3942   // Double registers
3943   "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3944   "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3945   "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3946   "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3947 
3948   // Quad registers
3949   "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3950   "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
3951 };
3952 
3953 void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
3954                                    unsigned &NumNames) const {
3955   Names = GCCRegNames;
3956   NumNames = llvm::array_lengthof(GCCRegNames);
3957 }
3958 
3959 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
3960   { { "a1" }, "r0" },
3961   { { "a2" }, "r1" },
3962   { { "a3" }, "r2" },
3963   { { "a4" }, "r3" },
3964   { { "v1" }, "r4" },
3965   { { "v2" }, "r5" },
3966   { { "v3" }, "r6" },
3967   { { "v4" }, "r7" },
3968   { { "v5" }, "r8" },
3969   { { "v6", "rfp" }, "r9" },
3970   { { "sl" }, "r10" },
3971   { { "fp" }, "r11" },
3972   { { "ip" }, "r12" },
3973   { { "r13" }, "sp" },
3974   { { "r14" }, "lr" },
3975   { { "r15" }, "pc" },
3976   // The S, D and Q registers overlap, but aren't really aliases; we
3977   // don't want to substitute one of these for a different-sized one.
3978 };
3979 
3980 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3981                                        unsigned &NumAliases) const {
3982   Aliases = GCCRegAliases;
3983   NumAliases = llvm::array_lengthof(GCCRegAliases);
3984 }
3985 
3986 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
3987 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3988 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3989                                               ALL_LANGUAGES },
3990 #include "clang/Basic/BuiltinsARM.def"
3991 };
3992 } // end anonymous namespace.
3993 
3994 namespace {
3995 class DarwinARMTargetInfo :
3996   public DarwinTargetInfo<ARMTargetInfo> {
3997 protected:
3998   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3999                             MacroBuilder &Builder) const {
4000     getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4001   }
4002 
4003 public:
4004   DarwinARMTargetInfo(const std::string& triple)
4005     : DarwinTargetInfo<ARMTargetInfo>(triple) {
4006     HasAlignMac68kSupport = true;
4007     // iOS always has 64-bit atomic instructions.
4008     // FIXME: This should be based off of the target features in ARMTargetInfo.
4009     MaxAtomicInlineWidth = 64;
4010 
4011     // Darwin on iOS uses a variant of the ARM C++ ABI.
4012     TheCXXABI.set(TargetCXXABI::iOS);
4013   }
4014 };
4015 } // end anonymous namespace.
4016 
4017 
4018 namespace {
4019 // Hexagon abstract base class
4020 class HexagonTargetInfo : public TargetInfo {
4021   static const Builtin::Info BuiltinInfo[];
4022   static const char * const GCCRegNames[];
4023   static const TargetInfo::GCCRegAlias GCCRegAliases[];
4024   std::string CPU;
4025 public:
4026   HexagonTargetInfo(const std::string& triple) : TargetInfo(triple)  {
4027     BigEndian = false;
4028     DescriptionString = ("e-p:32:32:32-"
4029                          "i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
4030                          "f64:64:64-f32:32:32-a0:0-n32");
4031 
4032     // {} in inline assembly are packet specifiers, not assembly variant
4033     // specifiers.
4034     NoAsmVariants = true;
4035   }
4036 
4037   virtual void getTargetBuiltins(const Builtin::Info *&Records,
4038                                  unsigned &NumRecords) const {
4039     Records = BuiltinInfo;
4040     NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
4041   }
4042 
4043   virtual bool validateAsmConstraint(const char *&Name,
4044                                      TargetInfo::ConstraintInfo &Info) const {
4045     return true;
4046   }
4047 
4048   virtual void getTargetDefines(const LangOptions &Opts,
4049                                 MacroBuilder &Builder) const;
4050 
4051   virtual bool hasFeature(StringRef Feature) const {
4052     return Feature == "hexagon";
4053   }
4054 
4055   virtual BuiltinVaListKind getBuiltinVaListKind() const {
4056     return TargetInfo::CharPtrBuiltinVaList;
4057   }
4058   virtual void getGCCRegNames(const char * const *&Names,
4059                               unsigned &NumNames) const;
4060   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4061                                 unsigned &NumAliases) const;
4062   virtual const char *getClobbers() const {
4063     return "";
4064   }
4065 
4066   static const char *getHexagonCPUSuffix(StringRef Name) {
4067     return llvm::StringSwitch<const char*>(Name)
4068       .Case("hexagonv4", "4")
4069       .Case("hexagonv5", "5")
4070       .Default(0);
4071   }
4072 
4073   virtual bool setCPU(const std::string &Name) {
4074     if (!getHexagonCPUSuffix(Name))
4075       return false;
4076 
4077     CPU = Name;
4078     return true;
4079   }
4080 };
4081 
4082 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
4083                                 MacroBuilder &Builder) const {
4084   Builder.defineMacro("qdsp6");
4085   Builder.defineMacro("__qdsp6", "1");
4086   Builder.defineMacro("__qdsp6__", "1");
4087 
4088   Builder.defineMacro("hexagon");
4089   Builder.defineMacro("__hexagon", "1");
4090   Builder.defineMacro("__hexagon__", "1");
4091 
4092   if(CPU == "hexagonv1") {
4093     Builder.defineMacro("__HEXAGON_V1__");
4094     Builder.defineMacro("__HEXAGON_ARCH__", "1");
4095     if(Opts.HexagonQdsp6Compat) {
4096       Builder.defineMacro("__QDSP6_V1__");
4097       Builder.defineMacro("__QDSP6_ARCH__", "1");
4098     }
4099   }
4100   else if(CPU == "hexagonv2") {
4101     Builder.defineMacro("__HEXAGON_V2__");
4102     Builder.defineMacro("__HEXAGON_ARCH__", "2");
4103     if(Opts.HexagonQdsp6Compat) {
4104       Builder.defineMacro("__QDSP6_V2__");
4105       Builder.defineMacro("__QDSP6_ARCH__", "2");
4106     }
4107   }
4108   else if(CPU == "hexagonv3") {
4109     Builder.defineMacro("__HEXAGON_V3__");
4110     Builder.defineMacro("__HEXAGON_ARCH__", "3");
4111     if(Opts.HexagonQdsp6Compat) {
4112       Builder.defineMacro("__QDSP6_V3__");
4113       Builder.defineMacro("__QDSP6_ARCH__", "3");
4114     }
4115   }
4116   else if(CPU == "hexagonv4") {
4117     Builder.defineMacro("__HEXAGON_V4__");
4118     Builder.defineMacro("__HEXAGON_ARCH__", "4");
4119     if(Opts.HexagonQdsp6Compat) {
4120       Builder.defineMacro("__QDSP6_V4__");
4121       Builder.defineMacro("__QDSP6_ARCH__", "4");
4122     }
4123   }
4124   else if(CPU == "hexagonv5") {
4125     Builder.defineMacro("__HEXAGON_V5__");
4126     Builder.defineMacro("__HEXAGON_ARCH__", "5");
4127     if(Opts.HexagonQdsp6Compat) {
4128       Builder.defineMacro("__QDSP6_V5__");
4129       Builder.defineMacro("__QDSP6_ARCH__", "5");
4130     }
4131   }
4132 }
4133 
4134 const char * const HexagonTargetInfo::GCCRegNames[] = {
4135   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4136   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4137   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4138   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
4139   "p0", "p1", "p2", "p3",
4140   "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
4141 };
4142 
4143 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
4144                                    unsigned &NumNames) const {
4145   Names = GCCRegNames;
4146   NumNames = llvm::array_lengthof(GCCRegNames);
4147 }
4148 
4149 
4150 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
4151   { { "sp" }, "r29" },
4152   { { "fp" }, "r30" },
4153   { { "lr" }, "r31" },
4154  };
4155 
4156 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4157                                      unsigned &NumAliases) const {
4158   Aliases = GCCRegAliases;
4159   NumAliases = llvm::array_lengthof(GCCRegAliases);
4160 }
4161 
4162 
4163 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
4164 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4165 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4166                                               ALL_LANGUAGES },
4167 #include "clang/Basic/BuiltinsHexagon.def"
4168 };
4169 }
4170 
4171 
4172 namespace {
4173 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
4174 class SparcTargetInfo : public TargetInfo {
4175   static const TargetInfo::GCCRegAlias GCCRegAliases[];
4176   static const char * const GCCRegNames[];
4177   bool SoftFloat;
4178 public:
4179   SparcTargetInfo(const std::string &triple) : TargetInfo(triple) {}
4180 
4181   virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
4182                                  StringRef Name,
4183                                  bool Enabled) const {
4184     if (Name == "soft-float")
4185       Features[Name] = Enabled;
4186     else
4187       return false;
4188 
4189     return true;
4190   }
4191   virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
4192     SoftFloat = false;
4193     for (unsigned i = 0, e = Features.size(); i != e; ++i)
4194       if (Features[i] == "+soft-float")
4195         SoftFloat = true;
4196   }
4197   virtual void getTargetDefines(const LangOptions &Opts,
4198                                 MacroBuilder &Builder) const {
4199     DefineStd(Builder, "sparc", Opts);
4200     Builder.defineMacro("__REGISTER_PREFIX__", "");
4201 
4202     if (SoftFloat)
4203       Builder.defineMacro("SOFT_FLOAT", "1");
4204   }
4205 
4206   virtual bool hasFeature(StringRef Feature) const {
4207     return llvm::StringSwitch<bool>(Feature)
4208              .Case("softfloat", SoftFloat)
4209              .Case("sparc", true)
4210              .Default(false);
4211   }
4212 
4213   virtual void getTargetBuiltins(const Builtin::Info *&Records,
4214                                  unsigned &NumRecords) const {
4215     // FIXME: Implement!
4216   }
4217   virtual BuiltinVaListKind getBuiltinVaListKind() const {
4218     return TargetInfo::VoidPtrBuiltinVaList;
4219   }
4220   virtual void getGCCRegNames(const char * const *&Names,
4221                               unsigned &NumNames) const;
4222   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4223                                 unsigned &NumAliases) const;
4224   virtual bool validateAsmConstraint(const char *&Name,
4225                                      TargetInfo::ConstraintInfo &info) const {
4226     // FIXME: Implement!
4227     return false;
4228   }
4229   virtual const char *getClobbers() const {
4230     // FIXME: Implement!
4231     return "";
4232   }
4233 };
4234 
4235 const char * const SparcTargetInfo::GCCRegNames[] = {
4236   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4237   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4238   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4239   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
4240 };
4241 
4242 void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
4243                                      unsigned &NumNames) const {
4244   Names = GCCRegNames;
4245   NumNames = llvm::array_lengthof(GCCRegNames);
4246 }
4247 
4248 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
4249   { { "g0" }, "r0" },
4250   { { "g1" }, "r1" },
4251   { { "g2" }, "r2" },
4252   { { "g3" }, "r3" },
4253   { { "g4" }, "r4" },
4254   { { "g5" }, "r5" },
4255   { { "g6" }, "r6" },
4256   { { "g7" }, "r7" },
4257   { { "o0" }, "r8" },
4258   { { "o1" }, "r9" },
4259   { { "o2" }, "r10" },
4260   { { "o3" }, "r11" },
4261   { { "o4" }, "r12" },
4262   { { "o5" }, "r13" },
4263   { { "o6", "sp" }, "r14" },
4264   { { "o7" }, "r15" },
4265   { { "l0" }, "r16" },
4266   { { "l1" }, "r17" },
4267   { { "l2" }, "r18" },
4268   { { "l3" }, "r19" },
4269   { { "l4" }, "r20" },
4270   { { "l5" }, "r21" },
4271   { { "l6" }, "r22" },
4272   { { "l7" }, "r23" },
4273   { { "i0" }, "r24" },
4274   { { "i1" }, "r25" },
4275   { { "i2" }, "r26" },
4276   { { "i3" }, "r27" },
4277   { { "i4" }, "r28" },
4278   { { "i5" }, "r29" },
4279   { { "i6", "fp" }, "r30" },
4280   { { "i7" }, "r31" },
4281 };
4282 
4283 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4284                                        unsigned &NumAliases) const {
4285   Aliases = GCCRegAliases;
4286   NumAliases = llvm::array_lengthof(GCCRegAliases);
4287 }
4288 
4289 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
4290 class SparcV8TargetInfo : public SparcTargetInfo {
4291 public:
4292   SparcV8TargetInfo(const std::string& triple) : SparcTargetInfo(triple) {
4293     // FIXME: Support Sparc quad-precision long double?
4294     DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4295                         "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4296   }
4297 
4298   virtual void getTargetDefines(const LangOptions &Opts,
4299                                 MacroBuilder &Builder) const {
4300     SparcTargetInfo::getTargetDefines(Opts, Builder);
4301     Builder.defineMacro("__sparcv8");
4302   }
4303 };
4304 
4305 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
4306 class SparcV9TargetInfo : public SparcTargetInfo {
4307 public:
4308   SparcV9TargetInfo(const std::string& triple) : SparcTargetInfo(triple) {
4309     // FIXME: Support Sparc quad-precision long double?
4310     DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4311                         "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32:64-S128";
4312     // This is an LP64 platform.
4313     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4314 
4315     // OpenBSD uses long long for int64_t and intmax_t.
4316     if (getTriple().getOS() == llvm::Triple::OpenBSD) {
4317       IntMaxType = SignedLongLong;
4318       UIntMaxType = UnsignedLongLong;
4319     } else {
4320       IntMaxType = SignedLong;
4321       UIntMaxType = UnsignedLong;
4322     }
4323     Int64Type = IntMaxType;
4324   }
4325 
4326   virtual void getTargetDefines(const LangOptions &Opts,
4327                                 MacroBuilder &Builder) const {
4328     SparcTargetInfo::getTargetDefines(Opts, Builder);
4329     Builder.defineMacro("__sparcv9");
4330     Builder.defineMacro("__arch64__");
4331     // Solaris and its derivative AuroraUX don't need these variants, but the
4332     // BSDs do.
4333     if (getTriple().getOS() != llvm::Triple::Solaris &&
4334         getTriple().getOS() != llvm::Triple::AuroraUX) {
4335       Builder.defineMacro("__sparc64__");
4336       Builder.defineMacro("__sparc_v9__");
4337       Builder.defineMacro("__sparcv9__");
4338     }
4339   }
4340 };
4341 
4342 } // end anonymous namespace.
4343 
4344 namespace {
4345 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> {
4346 public:
4347   AuroraUXSparcV8TargetInfo(const std::string& triple) :
4348       AuroraUXTargetInfo<SparcV8TargetInfo>(triple) {
4349     SizeType = UnsignedInt;
4350     PtrDiffType = SignedInt;
4351   }
4352 };
4353 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
4354 public:
4355   SolarisSparcV8TargetInfo(const std::string& triple) :
4356       SolarisTargetInfo<SparcV8TargetInfo>(triple) {
4357     SizeType = UnsignedInt;
4358     PtrDiffType = SignedInt;
4359   }
4360 };
4361 } // end anonymous namespace.
4362 
4363 namespace {
4364   class SystemZTargetInfo : public TargetInfo {
4365     static const char *const GCCRegNames[];
4366 
4367   public:
4368     SystemZTargetInfo(const std::string& triple) : TargetInfo(triple) {
4369       TLSSupported = true;
4370       IntWidth = IntAlign = 32;
4371       LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
4372       PointerWidth = PointerAlign = 64;
4373       LongDoubleWidth = 128;
4374       LongDoubleAlign = 64;
4375       LongDoubleFormat = &llvm::APFloat::IEEEquad;
4376       MinGlobalAlign = 16;
4377       DescriptionString = "E-p:64:64:64-i1:8:16-i8:8:16-i16:16-i32:32-i64:64"
4378        "-f32:32-f64:64-f128:64-a0:8:16-n32:64";
4379       MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4380     }
4381     virtual void getTargetDefines(const LangOptions &Opts,
4382                                   MacroBuilder &Builder) const {
4383       Builder.defineMacro("__s390__");
4384       Builder.defineMacro("__s390x__");
4385       Builder.defineMacro("__zarch__");
4386       Builder.defineMacro("__LONG_DOUBLE_128__");
4387     }
4388     virtual void getTargetBuiltins(const Builtin::Info *&Records,
4389                                    unsigned &NumRecords) const {
4390       // FIXME: Implement.
4391       Records = 0;
4392       NumRecords = 0;
4393     }
4394 
4395     virtual void getGCCRegNames(const char *const *&Names,
4396                                 unsigned &NumNames) const;
4397     virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4398                                   unsigned &NumAliases) const {
4399       // No aliases.
4400       Aliases = 0;
4401       NumAliases = 0;
4402     }
4403     virtual bool validateAsmConstraint(const char *&Name,
4404                                        TargetInfo::ConstraintInfo &info) const;
4405     virtual const char *getClobbers() const {
4406       // FIXME: Is this really right?
4407       return "";
4408     }
4409     virtual BuiltinVaListKind getBuiltinVaListKind() const {
4410       return TargetInfo::SystemZBuiltinVaList;
4411     }
4412   };
4413 
4414   const char *const SystemZTargetInfo::GCCRegNames[] = {
4415     "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
4416     "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
4417     "f0",  "f2",  "f4",  "f6",  "f1",  "f3",  "f5",  "f7",
4418     "f8",  "f10", "f12", "f14", "f9",  "f11", "f13", "f15"
4419   };
4420 
4421   void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
4422                                          unsigned &NumNames) const {
4423     Names = GCCRegNames;
4424     NumNames = llvm::array_lengthof(GCCRegNames);
4425   }
4426 
4427   bool SystemZTargetInfo::
4428   validateAsmConstraint(const char *&Name,
4429                         TargetInfo::ConstraintInfo &Info) const {
4430     switch (*Name) {
4431     default:
4432       return false;
4433 
4434     case 'a': // Address register
4435     case 'd': // Data register (equivalent to 'r')
4436     case 'f': // Floating-point register
4437       Info.setAllowsRegister();
4438       return true;
4439 
4440     case 'I': // Unsigned 8-bit constant
4441     case 'J': // Unsigned 12-bit constant
4442     case 'K': // Signed 16-bit constant
4443     case 'L': // Signed 20-bit displacement (on all targets we support)
4444     case 'M': // 0x7fffffff
4445       return true;
4446 
4447     case 'Q': // Memory with base and unsigned 12-bit displacement
4448     case 'R': // Likewise, plus an index
4449     case 'S': // Memory with base and signed 20-bit displacement
4450     case 'T': // Likewise, plus an index
4451       Info.setAllowsMemory();
4452       return true;
4453     }
4454   }
4455 }
4456 
4457 namespace {
4458   class MSP430TargetInfo : public TargetInfo {
4459     static const char * const GCCRegNames[];
4460   public:
4461     MSP430TargetInfo(const std::string& triple) : TargetInfo(triple) {
4462       BigEndian = false;
4463       TLSSupported = false;
4464       IntWidth = 16; IntAlign = 16;
4465       LongWidth = 32; LongLongWidth = 64;
4466       LongAlign = LongLongAlign = 16;
4467       PointerWidth = 16; PointerAlign = 16;
4468       SuitableAlign = 16;
4469       SizeType = UnsignedInt;
4470       IntMaxType = SignedLong;
4471       UIntMaxType = UnsignedLong;
4472       IntPtrType = SignedShort;
4473       PtrDiffType = SignedInt;
4474       SigAtomicType = SignedLong;
4475       DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16";
4476    }
4477     virtual void getTargetDefines(const LangOptions &Opts,
4478                                   MacroBuilder &Builder) const {
4479       Builder.defineMacro("MSP430");
4480       Builder.defineMacro("__MSP430__");
4481       // FIXME: defines for different 'flavours' of MCU
4482     }
4483     virtual void getTargetBuiltins(const Builtin::Info *&Records,
4484                                    unsigned &NumRecords) const {
4485      // FIXME: Implement.
4486       Records = 0;
4487       NumRecords = 0;
4488     }
4489     virtual bool hasFeature(StringRef Feature) const {
4490       return Feature == "msp430";
4491     }
4492     virtual void getGCCRegNames(const char * const *&Names,
4493                                 unsigned &NumNames) const;
4494     virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4495                                   unsigned &NumAliases) const {
4496       // No aliases.
4497       Aliases = 0;
4498       NumAliases = 0;
4499     }
4500     virtual bool validateAsmConstraint(const char *&Name,
4501                                        TargetInfo::ConstraintInfo &info) const {
4502       // No target constraints for now.
4503       return false;
4504     }
4505     virtual const char *getClobbers() const {
4506       // FIXME: Is this really right?
4507       return "";
4508     }
4509     virtual BuiltinVaListKind getBuiltinVaListKind() const {
4510       // FIXME: implement
4511       return TargetInfo::CharPtrBuiltinVaList;
4512    }
4513   };
4514 
4515   const char * const MSP430TargetInfo::GCCRegNames[] = {
4516     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4517     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4518   };
4519 
4520   void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
4521                                         unsigned &NumNames) const {
4522     Names = GCCRegNames;
4523     NumNames = llvm::array_lengthof(GCCRegNames);
4524   }
4525 }
4526 
4527 namespace {
4528 
4529   // LLVM and Clang cannot be used directly to output native binaries for
4530   // target, but is used to compile C code to llvm bitcode with correct
4531   // type and alignment information.
4532   //
4533   // TCE uses the llvm bitcode as input and uses it for generating customized
4534   // target processor and program binary. TCE co-design environment is
4535   // publicly available in http://tce.cs.tut.fi
4536 
4537   static const unsigned TCEOpenCLAddrSpaceMap[] = {
4538       3, // opencl_global
4539       4, // opencl_local
4540       5, // opencl_constant
4541       0, // cuda_device
4542       0, // cuda_constant
4543       0  // cuda_shared
4544   };
4545 
4546   class TCETargetInfo : public TargetInfo{
4547   public:
4548     TCETargetInfo(const std::string& triple) : TargetInfo(triple) {
4549       TLSSupported = false;
4550       IntWidth = 32;
4551       LongWidth = LongLongWidth = 32;
4552       PointerWidth = 32;
4553       IntAlign = 32;
4554       LongAlign = LongLongAlign = 32;
4555       PointerAlign = 32;
4556       SuitableAlign = 32;
4557       SizeType = UnsignedInt;
4558       IntMaxType = SignedLong;
4559       UIntMaxType = UnsignedLong;
4560       IntPtrType = SignedInt;
4561       PtrDiffType = SignedInt;
4562       FloatWidth = 32;
4563       FloatAlign = 32;
4564       DoubleWidth = 32;
4565       DoubleAlign = 32;
4566       LongDoubleWidth = 32;
4567       LongDoubleAlign = 32;
4568       FloatFormat = &llvm::APFloat::IEEEsingle;
4569       DoubleFormat = &llvm::APFloat::IEEEsingle;
4570       LongDoubleFormat = &llvm::APFloat::IEEEsingle;
4571       DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-"
4572                           "i16:16:32-i32:32:32-i64:32:32-"
4573                           "f32:32:32-f64:32:32-v64:32:32-"
4574                           "v128:32:32-a0:0:32-n32";
4575       AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
4576     }
4577 
4578     virtual void getTargetDefines(const LangOptions &Opts,
4579                                   MacroBuilder &Builder) const {
4580       DefineStd(Builder, "tce", Opts);
4581       Builder.defineMacro("__TCE__");
4582       Builder.defineMacro("__TCE_V1__");
4583     }
4584     virtual bool hasFeature(StringRef Feature) const {
4585       return Feature == "tce";
4586     }
4587 
4588     virtual void getTargetBuiltins(const Builtin::Info *&Records,
4589                                    unsigned &NumRecords) const {}
4590     virtual const char *getClobbers() const {
4591       return "";
4592     }
4593     virtual BuiltinVaListKind getBuiltinVaListKind() const {
4594       return TargetInfo::VoidPtrBuiltinVaList;
4595     }
4596     virtual void getGCCRegNames(const char * const *&Names,
4597                                 unsigned &NumNames) const {}
4598     virtual bool validateAsmConstraint(const char *&Name,
4599                                        TargetInfo::ConstraintInfo &info) const {
4600       return true;
4601     }
4602     virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4603                                   unsigned &NumAliases) const {}
4604   };
4605 }
4606 
4607 namespace {
4608 class MipsTargetInfoBase : public TargetInfo {
4609   static const Builtin::Info BuiltinInfo[];
4610   std::string CPU;
4611   bool IsMips16;
4612   bool IsMicromips;
4613   bool IsSingleFloat;
4614   enum MipsFloatABI {
4615     HardFloat, SoftFloat
4616   } FloatABI;
4617   enum DspRevEnum {
4618     NoDSP, DSP1, DSP2
4619   } DspRev;
4620 
4621 protected:
4622   std::string ABI;
4623 
4624 public:
4625   MipsTargetInfoBase(const std::string& triple,
4626                      const std::string& ABIStr,
4627                      const std::string& CPUStr)
4628     : TargetInfo(triple),
4629       CPU(CPUStr),
4630       IsMips16(false),
4631       IsMicromips(false),
4632       IsSingleFloat(false),
4633       FloatABI(HardFloat),
4634       DspRev(NoDSP),
4635       ABI(ABIStr)
4636   {}
4637 
4638   virtual const char *getABI() const { return ABI.c_str(); }
4639   virtual bool setABI(const std::string &Name) = 0;
4640   virtual bool setCPU(const std::string &Name) {
4641     CPU = Name;
4642     return true;
4643   }
4644   void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
4645     Features[ABI] = true;
4646     Features[CPU] = true;
4647   }
4648 
4649   virtual void getTargetDefines(const LangOptions &Opts,
4650                                 MacroBuilder &Builder) const {
4651     DefineStd(Builder, "mips", Opts);
4652     Builder.defineMacro("_mips");
4653     Builder.defineMacro("__REGISTER_PREFIX__", "");
4654 
4655     switch (FloatABI) {
4656     case HardFloat:
4657       Builder.defineMacro("__mips_hard_float", Twine(1));
4658       break;
4659     case SoftFloat:
4660       Builder.defineMacro("__mips_soft_float", Twine(1));
4661       break;
4662     }
4663 
4664     if (IsSingleFloat)
4665       Builder.defineMacro("__mips_single_float", Twine(1));
4666 
4667     if (IsMips16)
4668       Builder.defineMacro("__mips16", Twine(1));
4669 
4670     if (IsMicromips)
4671       Builder.defineMacro("__mips_micromips", Twine(1));
4672 
4673     switch (DspRev) {
4674     default:
4675       break;
4676     case DSP1:
4677       Builder.defineMacro("__mips_dsp_rev", Twine(1));
4678       Builder.defineMacro("__mips_dsp", Twine(1));
4679       break;
4680     case DSP2:
4681       Builder.defineMacro("__mips_dsp_rev", Twine(2));
4682       Builder.defineMacro("__mips_dspr2", Twine(1));
4683       Builder.defineMacro("__mips_dsp", Twine(1));
4684       break;
4685     }
4686 
4687     Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
4688     Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
4689     Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
4690 
4691     Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
4692     Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
4693   }
4694 
4695   virtual void getTargetBuiltins(const Builtin::Info *&Records,
4696                                  unsigned &NumRecords) const {
4697     Records = BuiltinInfo;
4698     NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
4699   }
4700   virtual bool hasFeature(StringRef Feature) const {
4701     return Feature == "mips";
4702   }
4703   virtual BuiltinVaListKind getBuiltinVaListKind() const {
4704     return TargetInfo::VoidPtrBuiltinVaList;
4705   }
4706   virtual void getGCCRegNames(const char * const *&Names,
4707                               unsigned &NumNames) const {
4708     static const char * const GCCRegNames[] = {
4709       // CPU register names
4710       // Must match second column of GCCRegAliases
4711       "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
4712       "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
4713       "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
4714       "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
4715       // Floating point register names
4716       "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
4717       "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
4718       "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
4719       "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
4720       // Hi/lo and condition register names
4721       "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
4722       "$fcc5","$fcc6","$fcc7"
4723     };
4724     Names = GCCRegNames;
4725     NumNames = llvm::array_lengthof(GCCRegNames);
4726   }
4727   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4728                                 unsigned &NumAliases) const = 0;
4729   virtual bool validateAsmConstraint(const char *&Name,
4730                                      TargetInfo::ConstraintInfo &Info) const {
4731     switch (*Name) {
4732     default:
4733       return false;
4734 
4735     case 'r': // CPU registers.
4736     case 'd': // Equivalent to "r" unless generating MIPS16 code.
4737     case 'y': // Equivalent to "r", backwards compatibility only.
4738     case 'f': // floating-point registers.
4739     case 'c': // $25 for indirect jumps
4740     case 'l': // lo register
4741     case 'x': // hilo register pair
4742       Info.setAllowsRegister();
4743       return true;
4744     case 'R': // An address that can be used in a non-macro load or store
4745       Info.setAllowsMemory();
4746       return true;
4747     }
4748   }
4749 
4750   virtual const char *getClobbers() const {
4751     // FIXME: Implement!
4752     return "";
4753   }
4754 
4755   virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features,
4756                                  StringRef Name,
4757                                  bool Enabled) const {
4758     if (Name == "soft-float" || Name == "single-float" ||
4759         Name == "o32" || Name == "n32" || Name == "n64" || Name == "eabi" ||
4760         Name == "mips32" || Name == "mips32r2" ||
4761         Name == "mips64" || Name == "mips64r2" ||
4762         Name == "mips16" || Name == "micromips" ||
4763         Name == "dsp" || Name == "dspr2") {
4764       Features[Name] = Enabled;
4765       return true;
4766     } else if (Name == "32") {
4767       Features["o32"] = Enabled;
4768       return true;
4769     } else if (Name == "64") {
4770       Features["n64"] = Enabled;
4771       return true;
4772     }
4773     return false;
4774   }
4775 
4776   virtual void HandleTargetFeatures(std::vector<std::string> &Features) {
4777     IsMips16 = false;
4778     IsMicromips = false;
4779     IsSingleFloat = false;
4780     FloatABI = HardFloat;
4781     DspRev = NoDSP;
4782 
4783     for (std::vector<std::string>::iterator it = Features.begin(),
4784          ie = Features.end(); it != ie; ++it) {
4785       if (*it == "+single-float")
4786         IsSingleFloat = true;
4787       else if (*it == "+soft-float")
4788         FloatABI = SoftFloat;
4789       else if (*it == "+mips16")
4790         IsMips16 = true;
4791       else if (*it == "+micromips")
4792         IsMicromips = true;
4793       else if (*it == "+dsp")
4794         DspRev = std::max(DspRev, DSP1);
4795       else if (*it == "+dspr2")
4796         DspRev = std::max(DspRev, DSP2);
4797     }
4798 
4799     // Remove front-end specific option.
4800     std::vector<std::string>::iterator it =
4801       std::find(Features.begin(), Features.end(), "+soft-float");
4802     if (it != Features.end())
4803       Features.erase(it);
4804   }
4805 
4806   virtual int getEHDataRegisterNumber(unsigned RegNo) const {
4807     if (RegNo == 0) return 4;
4808     if (RegNo == 1) return 5;
4809     return -1;
4810   }
4811 };
4812 
4813 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
4814 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4815 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4816                                               ALL_LANGUAGES },
4817 #include "clang/Basic/BuiltinsMips.def"
4818 };
4819 
4820 class Mips32TargetInfoBase : public MipsTargetInfoBase {
4821 public:
4822   Mips32TargetInfoBase(const std::string& triple) :
4823     MipsTargetInfoBase(triple, "o32", "mips32") {
4824     SizeType = UnsignedInt;
4825     PtrDiffType = SignedInt;
4826     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
4827   }
4828   virtual bool setABI(const std::string &Name) {
4829     if ((Name == "o32") || (Name == "eabi")) {
4830       ABI = Name;
4831       return true;
4832     } else if (Name == "32") {
4833       ABI = "o32";
4834       return true;
4835     } else
4836       return false;
4837   }
4838   virtual void getTargetDefines(const LangOptions &Opts,
4839                                 MacroBuilder &Builder) const {
4840     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4841 
4842     if (ABI == "o32") {
4843       Builder.defineMacro("__mips_o32");
4844       Builder.defineMacro("_ABIO32", "1");
4845       Builder.defineMacro("_MIPS_SIM", "_ABIO32");
4846     }
4847     else if (ABI == "eabi")
4848       Builder.defineMacro("__mips_eabi");
4849     else
4850       llvm_unreachable("Invalid ABI for Mips32.");
4851   }
4852   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4853                                 unsigned &NumAliases) const {
4854     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4855       { { "at" },  "$1" },
4856       { { "v0" },  "$2" },
4857       { { "v1" },  "$3" },
4858       { { "a0" },  "$4" },
4859       { { "a1" },  "$5" },
4860       { { "a2" },  "$6" },
4861       { { "a3" },  "$7" },
4862       { { "t0" },  "$8" },
4863       { { "t1" },  "$9" },
4864       { { "t2" }, "$10" },
4865       { { "t3" }, "$11" },
4866       { { "t4" }, "$12" },
4867       { { "t5" }, "$13" },
4868       { { "t6" }, "$14" },
4869       { { "t7" }, "$15" },
4870       { { "s0" }, "$16" },
4871       { { "s1" }, "$17" },
4872       { { "s2" }, "$18" },
4873       { { "s3" }, "$19" },
4874       { { "s4" }, "$20" },
4875       { { "s5" }, "$21" },
4876       { { "s6" }, "$22" },
4877       { { "s7" }, "$23" },
4878       { { "t8" }, "$24" },
4879       { { "t9" }, "$25" },
4880       { { "k0" }, "$26" },
4881       { { "k1" }, "$27" },
4882       { { "gp" }, "$28" },
4883       { { "sp","$sp" }, "$29" },
4884       { { "fp","$fp" }, "$30" },
4885       { { "ra" }, "$31" }
4886     };
4887     Aliases = GCCRegAliases;
4888     NumAliases = llvm::array_lengthof(GCCRegAliases);
4889   }
4890 };
4891 
4892 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
4893 public:
4894   Mips32EBTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) {
4895     DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4896                         "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4897   }
4898   virtual void getTargetDefines(const LangOptions &Opts,
4899                                 MacroBuilder &Builder) const {
4900     DefineStd(Builder, "MIPSEB", Opts);
4901     Builder.defineMacro("_MIPSEB");
4902     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4903   }
4904 };
4905 
4906 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
4907 public:
4908   Mips32ELTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) {
4909     BigEndian = false;
4910     DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
4911                         "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4912   }
4913   virtual void getTargetDefines(const LangOptions &Opts,
4914                                 MacroBuilder &Builder) const {
4915     DefineStd(Builder, "MIPSEL", Opts);
4916     Builder.defineMacro("_MIPSEL");
4917     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
4918   }
4919 };
4920 
4921 class Mips64TargetInfoBase : public MipsTargetInfoBase {
4922   virtual void SetDescriptionString(const std::string &Name) = 0;
4923 public:
4924   Mips64TargetInfoBase(const std::string& triple) :
4925     MipsTargetInfoBase(triple, "n64", "mips64") {
4926     LongWidth = LongAlign = 64;
4927     PointerWidth = PointerAlign = 64;
4928     LongDoubleWidth = LongDoubleAlign = 128;
4929     LongDoubleFormat = &llvm::APFloat::IEEEquad;
4930     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
4931       LongDoubleWidth = LongDoubleAlign = 64;
4932       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4933     }
4934     SuitableAlign = 128;
4935     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4936   }
4937   virtual bool setABI(const std::string &Name) {
4938     SetDescriptionString(Name);
4939     if (Name == "n32") {
4940       LongWidth = LongAlign = 32;
4941       PointerWidth = PointerAlign = 32;
4942       ABI = Name;
4943       return true;
4944     } else if (Name == "n64") {
4945       ABI = Name;
4946       return true;
4947     } else if (Name == "64") {
4948       ABI = "n64";
4949       return true;
4950     } else
4951       return false;
4952   }
4953   virtual void getTargetDefines(const LangOptions &Opts,
4954                                 MacroBuilder &Builder) const {
4955     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
4956 
4957     Builder.defineMacro("__mips64");
4958     Builder.defineMacro("__mips64__");
4959 
4960     if (ABI == "n32") {
4961       Builder.defineMacro("__mips_n32");
4962       Builder.defineMacro("_ABIN32", "2");
4963       Builder.defineMacro("_MIPS_SIM", "_ABIN32");
4964     }
4965     else if (ABI == "n64") {
4966       Builder.defineMacro("__mips_n64");
4967       Builder.defineMacro("_ABI64", "3");
4968       Builder.defineMacro("_MIPS_SIM", "_ABI64");
4969     }
4970     else
4971       llvm_unreachable("Invalid ABI for Mips64.");
4972   }
4973   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4974                                 unsigned &NumAliases) const {
4975     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
4976       { { "at" },  "$1" },
4977       { { "v0" },  "$2" },
4978       { { "v1" },  "$3" },
4979       { { "a0" },  "$4" },
4980       { { "a1" },  "$5" },
4981       { { "a2" },  "$6" },
4982       { { "a3" },  "$7" },
4983       { { "a4" },  "$8" },
4984       { { "a5" },  "$9" },
4985       { { "a6" }, "$10" },
4986       { { "a7" }, "$11" },
4987       { { "t0" }, "$12" },
4988       { { "t1" }, "$13" },
4989       { { "t2" }, "$14" },
4990       { { "t3" }, "$15" },
4991       { { "s0" }, "$16" },
4992       { { "s1" }, "$17" },
4993       { { "s2" }, "$18" },
4994       { { "s3" }, "$19" },
4995       { { "s4" }, "$20" },
4996       { { "s5" }, "$21" },
4997       { { "s6" }, "$22" },
4998       { { "s7" }, "$23" },
4999       { { "t8" }, "$24" },
5000       { { "t9" }, "$25" },
5001       { { "k0" }, "$26" },
5002       { { "k1" }, "$27" },
5003       { { "gp" }, "$28" },
5004       { { "sp","$sp" }, "$29" },
5005       { { "fp","$fp" }, "$30" },
5006       { { "ra" }, "$31" }
5007     };
5008     Aliases = GCCRegAliases;
5009     NumAliases = llvm::array_lengthof(GCCRegAliases);
5010   }
5011 };
5012 
5013 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
5014   virtual void SetDescriptionString(const std::string &Name) {
5015     // Change DescriptionString only if ABI is n32.
5016     if (Name == "n32")
5017       DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5018                           "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5019                           "v64:64:64-n32:64-S128";
5020   }
5021 public:
5022   Mips64EBTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) {
5023     // Default ABI is n64.
5024     DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5025                         "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5026                         "v64:64:64-n32:64-S128";
5027   }
5028   virtual void getTargetDefines(const LangOptions &Opts,
5029                                 MacroBuilder &Builder) const {
5030     DefineStd(Builder, "MIPSEB", Opts);
5031     Builder.defineMacro("_MIPSEB");
5032     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5033   }
5034 };
5035 
5036 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
5037   virtual void SetDescriptionString(const std::string &Name) {
5038     // Change DescriptionString only if ABI is n32.
5039     if (Name == "n32")
5040       DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5041                           "i64:64:64-f32:32:32-f64:64:64-f128:128:128"
5042                           "-v64:64:64-n32:64-S128";
5043   }
5044 public:
5045   Mips64ELTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) {
5046     // Default ABI is n64.
5047     BigEndian = false;
5048     DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5049                         "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5050                         "v64:64:64-n32:64-S128";
5051   }
5052   virtual void getTargetDefines(const LangOptions &Opts,
5053                                 MacroBuilder &Builder) const {
5054     DefineStd(Builder, "MIPSEL", Opts);
5055     Builder.defineMacro("_MIPSEL");
5056     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5057   }
5058 };
5059 } // end anonymous namespace.
5060 
5061 namespace {
5062 class PNaClTargetInfo : public TargetInfo {
5063 public:
5064   PNaClTargetInfo(const std::string& triple) : TargetInfo(triple) {
5065     BigEndian = false;
5066     this->UserLabelPrefix = "";
5067     this->LongAlign = 32;
5068     this->LongWidth = 32;
5069     this->PointerAlign = 32;
5070     this->PointerWidth = 32;
5071     this->IntMaxType = TargetInfo::SignedLongLong;
5072     this->UIntMaxType = TargetInfo::UnsignedLongLong;
5073     this->Int64Type = TargetInfo::SignedLongLong;
5074     this->DoubleAlign = 64;
5075     this->LongDoubleWidth = 64;
5076     this->LongDoubleAlign = 64;
5077     this->SizeType = TargetInfo::UnsignedInt;
5078     this->PtrDiffType = TargetInfo::SignedInt;
5079     this->IntPtrType = TargetInfo::SignedInt;
5080     this->RegParmMax = 0; // Disallow regparm
5081     DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5082                         "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
5083   }
5084 
5085   void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
5086   }
5087   virtual void getArchDefines(const LangOptions &Opts,
5088                               MacroBuilder &Builder) const {
5089     Builder.defineMacro("__le32__");
5090     Builder.defineMacro("__pnacl__");
5091   }
5092   virtual void getTargetDefines(const LangOptions &Opts,
5093                                 MacroBuilder &Builder) const {
5094     Builder.defineMacro("__LITTLE_ENDIAN__");
5095     getArchDefines(Opts, Builder);
5096   }
5097   virtual bool hasFeature(StringRef Feature) const {
5098     return Feature == "pnacl";
5099   }
5100   virtual void getTargetBuiltins(const Builtin::Info *&Records,
5101                                  unsigned &NumRecords) const {
5102   }
5103   virtual BuiltinVaListKind getBuiltinVaListKind() const {
5104     return TargetInfo::PNaClABIBuiltinVaList;
5105   }
5106   virtual void getGCCRegNames(const char * const *&Names,
5107                               unsigned &NumNames) const;
5108   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5109                                 unsigned &NumAliases) const;
5110   virtual bool validateAsmConstraint(const char *&Name,
5111                                      TargetInfo::ConstraintInfo &Info) const {
5112     return false;
5113   }
5114 
5115   virtual const char *getClobbers() const {
5116     return "";
5117   }
5118 };
5119 
5120 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
5121                                      unsigned &NumNames) const {
5122   Names = NULL;
5123   NumNames = 0;
5124 }
5125 
5126 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5127                                        unsigned &NumAliases) const {
5128   Aliases = NULL;
5129   NumAliases = 0;
5130 }
5131 } // end anonymous namespace.
5132 
5133 namespace {
5134   static const unsigned SPIRAddrSpaceMap[] = {
5135     1,    // opencl_global
5136     3,    // opencl_local
5137     2,    // opencl_constant
5138     0,    // cuda_device
5139     0,    // cuda_constant
5140     0     // cuda_shared
5141   };
5142   class SPIRTargetInfo : public TargetInfo {
5143     static const char * const GCCRegNames[];
5144     static const Builtin::Info BuiltinInfo[];
5145     std::vector<StringRef> AvailableFeatures;
5146   public:
5147     SPIRTargetInfo(const std::string& triple) : TargetInfo(triple) {
5148       assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
5149         "SPIR target must use unknown OS");
5150       assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
5151         "SPIR target must use unknown environment type");
5152       BigEndian = false;
5153       TLSSupported = false;
5154       LongWidth = LongAlign = 64;
5155       AddrSpaceMap = &SPIRAddrSpaceMap;
5156       // Define available target features
5157       // These must be defined in sorted order!
5158       NoAsmVariants = true;
5159     }
5160     virtual void getTargetDefines(const LangOptions &Opts,
5161                                   MacroBuilder &Builder) const {
5162       DefineStd(Builder, "SPIR", Opts);
5163     }
5164     virtual bool hasFeature(StringRef Feature) const {
5165       return Feature == "spir";
5166     }
5167 
5168     virtual void getTargetBuiltins(const Builtin::Info *&Records,
5169                                    unsigned &NumRecords) const {}
5170     virtual const char *getClobbers() const {
5171       return "";
5172     }
5173     virtual void getGCCRegNames(const char * const *&Names,
5174                                 unsigned &NumNames) const {}
5175     virtual bool validateAsmConstraint(const char *&Name,
5176                                        TargetInfo::ConstraintInfo &info) const {
5177       return true;
5178     }
5179     virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5180                                   unsigned &NumAliases) const {}
5181     virtual BuiltinVaListKind getBuiltinVaListKind() const {
5182       return TargetInfo::VoidPtrBuiltinVaList;
5183     }
5184   };
5185 
5186 
5187   class SPIR32TargetInfo : public SPIRTargetInfo {
5188   public:
5189     SPIR32TargetInfo(const std::string& triple) : SPIRTargetInfo(triple) {
5190       PointerWidth = PointerAlign = 32;
5191       SizeType     = TargetInfo::UnsignedInt;
5192       PtrDiffType = IntPtrType = TargetInfo::SignedInt;
5193       DescriptionString
5194         = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5195           "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
5196           "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
5197           "v512:512:512-v1024:1024:1024";
5198     }
5199     virtual void getTargetDefines(const LangOptions &Opts,
5200                                   MacroBuilder &Builder) const {
5201       DefineStd(Builder, "SPIR32", Opts);
5202     }
5203   };
5204 
5205   class SPIR64TargetInfo : public SPIRTargetInfo {
5206   public:
5207     SPIR64TargetInfo(const std::string& triple) : SPIRTargetInfo(triple) {
5208       PointerWidth = PointerAlign = 64;
5209       SizeType     = TargetInfo::UnsignedLong;
5210       PtrDiffType = IntPtrType = TargetInfo::SignedLong;
5211       DescriptionString
5212         = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5213           "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
5214           "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
5215           "v512:512:512-v1024:1024:1024";
5216     }
5217     virtual void getTargetDefines(const LangOptions &Opts,
5218                                   MacroBuilder &Builder) const {
5219       DefineStd(Builder, "SPIR64", Opts);
5220     }
5221   };
5222 }
5223 
5224 
5225 //===----------------------------------------------------------------------===//
5226 // Driver code
5227 //===----------------------------------------------------------------------===//
5228 
5229 static TargetInfo *AllocateTarget(const std::string &T) {
5230   llvm::Triple Triple(T);
5231   llvm::Triple::OSType os = Triple.getOS();
5232 
5233   switch (Triple.getArch()) {
5234   default:
5235     return NULL;
5236 
5237   case llvm::Triple::hexagon:
5238     return new HexagonTargetInfo(T);
5239 
5240   case llvm::Triple::aarch64:
5241     switch (os) {
5242     case llvm::Triple::Linux:
5243       return new LinuxTargetInfo<AArch64TargetInfo>(T);
5244     default:
5245       return new AArch64TargetInfo(T);
5246     }
5247 
5248   case llvm::Triple::arm:
5249   case llvm::Triple::thumb:
5250     if (Triple.isOSDarwin())
5251       return new DarwinARMTargetInfo(T);
5252 
5253     switch (os) {
5254     case llvm::Triple::Linux:
5255       return new LinuxTargetInfo<ARMTargetInfo>(T);
5256     case llvm::Triple::FreeBSD:
5257       return new FreeBSDTargetInfo<ARMTargetInfo>(T);
5258     case llvm::Triple::NetBSD:
5259       return new NetBSDTargetInfo<ARMTargetInfo>(T);
5260     case llvm::Triple::OpenBSD:
5261       return new OpenBSDTargetInfo<ARMTargetInfo>(T);
5262     case llvm::Triple::Bitrig:
5263       return new BitrigTargetInfo<ARMTargetInfo>(T);
5264     case llvm::Triple::RTEMS:
5265       return new RTEMSTargetInfo<ARMTargetInfo>(T);
5266     case llvm::Triple::NaCl:
5267       return new NaClTargetInfo<ARMTargetInfo>(T);
5268     default:
5269       return new ARMTargetInfo(T);
5270     }
5271 
5272   case llvm::Triple::msp430:
5273     return new MSP430TargetInfo(T);
5274 
5275   case llvm::Triple::mips:
5276     switch (os) {
5277     case llvm::Triple::Linux:
5278       return new LinuxTargetInfo<Mips32EBTargetInfo>(T);
5279     case llvm::Triple::RTEMS:
5280       return new RTEMSTargetInfo<Mips32EBTargetInfo>(T);
5281     case llvm::Triple::FreeBSD:
5282       return new FreeBSDTargetInfo<Mips32EBTargetInfo>(T);
5283     case llvm::Triple::NetBSD:
5284       return new NetBSDTargetInfo<Mips32EBTargetInfo>(T);
5285     default:
5286       return new Mips32EBTargetInfo(T);
5287     }
5288 
5289   case llvm::Triple::mipsel:
5290     switch (os) {
5291     case llvm::Triple::Linux:
5292       return new LinuxTargetInfo<Mips32ELTargetInfo>(T);
5293     case llvm::Triple::RTEMS:
5294       return new RTEMSTargetInfo<Mips32ELTargetInfo>(T);
5295     case llvm::Triple::FreeBSD:
5296       return new FreeBSDTargetInfo<Mips32ELTargetInfo>(T);
5297     case llvm::Triple::NetBSD:
5298       return new NetBSDTargetInfo<Mips32ELTargetInfo>(T);
5299     default:
5300       return new Mips32ELTargetInfo(T);
5301     }
5302 
5303   case llvm::Triple::mips64:
5304     switch (os) {
5305     case llvm::Triple::Linux:
5306       return new LinuxTargetInfo<Mips64EBTargetInfo>(T);
5307     case llvm::Triple::RTEMS:
5308       return new RTEMSTargetInfo<Mips64EBTargetInfo>(T);
5309     case llvm::Triple::FreeBSD:
5310       return new FreeBSDTargetInfo<Mips64EBTargetInfo>(T);
5311     case llvm::Triple::NetBSD:
5312       return new NetBSDTargetInfo<Mips64EBTargetInfo>(T);
5313     case llvm::Triple::OpenBSD:
5314       return new OpenBSDTargetInfo<Mips64EBTargetInfo>(T);
5315     default:
5316       return new Mips64EBTargetInfo(T);
5317     }
5318 
5319   case llvm::Triple::mips64el:
5320     switch (os) {
5321     case llvm::Triple::Linux:
5322       return new LinuxTargetInfo<Mips64ELTargetInfo>(T);
5323     case llvm::Triple::RTEMS:
5324       return new RTEMSTargetInfo<Mips64ELTargetInfo>(T);
5325     case llvm::Triple::FreeBSD:
5326       return new FreeBSDTargetInfo<Mips64ELTargetInfo>(T);
5327     case llvm::Triple::NetBSD:
5328       return new NetBSDTargetInfo<Mips64ELTargetInfo>(T);
5329     case llvm::Triple::OpenBSD:
5330       return new OpenBSDTargetInfo<Mips64ELTargetInfo>(T);
5331     default:
5332       return new Mips64ELTargetInfo(T);
5333     }
5334 
5335   case llvm::Triple::le32:
5336     switch (os) {
5337       case llvm::Triple::NaCl:
5338         return new NaClTargetInfo<PNaClTargetInfo>(T);
5339       default:
5340         return NULL;
5341     }
5342 
5343   case llvm::Triple::ppc:
5344     if (Triple.isOSDarwin())
5345       return new DarwinPPC32TargetInfo(T);
5346     switch (os) {
5347     case llvm::Triple::Linux:
5348       return new LinuxTargetInfo<PPC32TargetInfo>(T);
5349     case llvm::Triple::FreeBSD:
5350       return new FreeBSDTargetInfo<PPC32TargetInfo>(T);
5351     case llvm::Triple::NetBSD:
5352       return new NetBSDTargetInfo<PPC32TargetInfo>(T);
5353     case llvm::Triple::OpenBSD:
5354       return new OpenBSDTargetInfo<PPC32TargetInfo>(T);
5355     case llvm::Triple::RTEMS:
5356       return new RTEMSTargetInfo<PPC32TargetInfo>(T);
5357     default:
5358       return new PPC32TargetInfo(T);
5359     }
5360 
5361   case llvm::Triple::ppc64:
5362     if (Triple.isOSDarwin())
5363       return new DarwinPPC64TargetInfo(T);
5364     switch (os) {
5365     case llvm::Triple::Linux:
5366       return new LinuxTargetInfo<PPC64TargetInfo>(T);
5367     case llvm::Triple::Lv2:
5368       return new PS3PPUTargetInfo<PPC64TargetInfo>(T);
5369     case llvm::Triple::FreeBSD:
5370       return new FreeBSDTargetInfo<PPC64TargetInfo>(T);
5371     case llvm::Triple::NetBSD:
5372       return new NetBSDTargetInfo<PPC64TargetInfo>(T);
5373     default:
5374       return new PPC64TargetInfo(T);
5375     }
5376 
5377   case llvm::Triple::nvptx:
5378     return new NVPTX32TargetInfo(T);
5379   case llvm::Triple::nvptx64:
5380     return new NVPTX64TargetInfo(T);
5381 
5382   case llvm::Triple::mblaze:
5383     return new MBlazeTargetInfo(T);
5384 
5385   case llvm::Triple::r600:
5386     return new R600TargetInfo(T);
5387 
5388   case llvm::Triple::sparc:
5389     switch (os) {
5390     case llvm::Triple::Linux:
5391       return new LinuxTargetInfo<SparcV8TargetInfo>(T);
5392     case llvm::Triple::AuroraUX:
5393       return new AuroraUXSparcV8TargetInfo(T);
5394     case llvm::Triple::Solaris:
5395       return new SolarisSparcV8TargetInfo(T);
5396     case llvm::Triple::NetBSD:
5397       return new NetBSDTargetInfo<SparcV8TargetInfo>(T);
5398     case llvm::Triple::OpenBSD:
5399       return new OpenBSDTargetInfo<SparcV8TargetInfo>(T);
5400     case llvm::Triple::RTEMS:
5401       return new RTEMSTargetInfo<SparcV8TargetInfo>(T);
5402     default:
5403       return new SparcV8TargetInfo(T);
5404     }
5405 
5406   case llvm::Triple::sparcv9:
5407     switch (os) {
5408     case llvm::Triple::Linux:
5409       return new LinuxTargetInfo<SparcV9TargetInfo>(T);
5410     case llvm::Triple::AuroraUX:
5411       return new AuroraUXTargetInfo<SparcV9TargetInfo>(T);
5412     case llvm::Triple::Solaris:
5413       return new SolarisTargetInfo<SparcV9TargetInfo>(T);
5414     case llvm::Triple::NetBSD:
5415       return new NetBSDTargetInfo<SparcV9TargetInfo>(T);
5416     case llvm::Triple::OpenBSD:
5417       return new OpenBSDTargetInfo<SparcV9TargetInfo>(T);
5418     case llvm::Triple::FreeBSD:
5419       return new FreeBSDTargetInfo<SparcV9TargetInfo>(T);
5420     default:
5421       return new SparcV9TargetInfo(T);
5422     }
5423 
5424   case llvm::Triple::systemz:
5425     switch (os) {
5426     case llvm::Triple::Linux:
5427       return new LinuxTargetInfo<SystemZTargetInfo>(T);
5428     default:
5429       return new SystemZTargetInfo(T);
5430     }
5431 
5432   case llvm::Triple::tce:
5433     return new TCETargetInfo(T);
5434 
5435   case llvm::Triple::x86:
5436     if (Triple.isOSDarwin())
5437       return new DarwinI386TargetInfo(T);
5438 
5439     switch (os) {
5440     case llvm::Triple::AuroraUX:
5441       return new AuroraUXTargetInfo<X86_32TargetInfo>(T);
5442     case llvm::Triple::Linux:
5443       return new LinuxTargetInfo<X86_32TargetInfo>(T);
5444     case llvm::Triple::DragonFly:
5445       return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(T);
5446     case llvm::Triple::NetBSD:
5447       return new NetBSDI386TargetInfo(T);
5448     case llvm::Triple::OpenBSD:
5449       return new OpenBSDI386TargetInfo(T);
5450     case llvm::Triple::Bitrig:
5451       return new BitrigI386TargetInfo(T);
5452     case llvm::Triple::FreeBSD:
5453       return new FreeBSDTargetInfo<X86_32TargetInfo>(T);
5454     case llvm::Triple::Minix:
5455       return new MinixTargetInfo<X86_32TargetInfo>(T);
5456     case llvm::Triple::Solaris:
5457       return new SolarisTargetInfo<X86_32TargetInfo>(T);
5458     case llvm::Triple::Cygwin:
5459       return new CygwinX86_32TargetInfo(T);
5460     case llvm::Triple::MinGW32:
5461       return new MinGWX86_32TargetInfo(T);
5462     case llvm::Triple::Win32:
5463       return new VisualStudioWindowsX86_32TargetInfo(T);
5464     case llvm::Triple::Haiku:
5465       return new HaikuX86_32TargetInfo(T);
5466     case llvm::Triple::RTEMS:
5467       return new RTEMSX86_32TargetInfo(T);
5468     case llvm::Triple::NaCl:
5469       return new NaClTargetInfo<X86_32TargetInfo>(T);
5470     default:
5471       return new X86_32TargetInfo(T);
5472     }
5473 
5474   case llvm::Triple::x86_64:
5475     if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO)
5476       return new DarwinX86_64TargetInfo(T);
5477 
5478     switch (os) {
5479     case llvm::Triple::AuroraUX:
5480       return new AuroraUXTargetInfo<X86_64TargetInfo>(T);
5481     case llvm::Triple::Linux:
5482       return new LinuxTargetInfo<X86_64TargetInfo>(T);
5483     case llvm::Triple::DragonFly:
5484       return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(T);
5485     case llvm::Triple::NetBSD:
5486       return new NetBSDTargetInfo<X86_64TargetInfo>(T);
5487     case llvm::Triple::OpenBSD:
5488       return new OpenBSDX86_64TargetInfo(T);
5489     case llvm::Triple::Bitrig:
5490       return new BitrigX86_64TargetInfo(T);
5491     case llvm::Triple::FreeBSD:
5492       return new FreeBSDTargetInfo<X86_64TargetInfo>(T);
5493     case llvm::Triple::Solaris:
5494       return new SolarisTargetInfo<X86_64TargetInfo>(T);
5495     case llvm::Triple::MinGW32:
5496       return new MinGWX86_64TargetInfo(T);
5497     case llvm::Triple::Win32:   // This is what Triple.h supports now.
5498       return new VisualStudioWindowsX86_64TargetInfo(T);
5499     case llvm::Triple::NaCl:
5500       return new NaClTargetInfo<X86_64TargetInfo>(T);
5501     default:
5502       return new X86_64TargetInfo(T);
5503     }
5504 
5505     case llvm::Triple::spir: {
5506       llvm::Triple Triple(T);
5507       if (Triple.getOS() != llvm::Triple::UnknownOS ||
5508         Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5509         return NULL;
5510       return new SPIR32TargetInfo(T);
5511     }
5512     case llvm::Triple::spir64: {
5513       llvm::Triple Triple(T);
5514       if (Triple.getOS() != llvm::Triple::UnknownOS ||
5515         Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5516         return NULL;
5517       return new SPIR64TargetInfo(T);
5518     }
5519   }
5520 }
5521 
5522 /// CreateTargetInfo - Return the target info object for the specified target
5523 /// triple.
5524 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
5525                                          TargetOptions *Opts) {
5526   llvm::Triple Triple(Opts->Triple);
5527 
5528   // Construct the target
5529   OwningPtr<TargetInfo> Target(AllocateTarget(Triple.str()));
5530   if (!Target) {
5531     Diags.Report(diag::err_target_unknown_triple) << Triple.str();
5532     return 0;
5533   }
5534   Target->setTargetOpts(Opts);
5535 
5536   // Set the target CPU if specified.
5537   if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
5538     Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
5539     return 0;
5540   }
5541 
5542   // Set the target ABI if specified.
5543   if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
5544     Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
5545     return 0;
5546   }
5547 
5548   // Set the target C++ ABI.
5549   if (!Opts->CXXABI.empty() && !Target->setCXXABI(Opts->CXXABI)) {
5550     Diags.Report(diag::err_target_unknown_cxxabi) << Opts->CXXABI;
5551     return 0;
5552   }
5553 
5554   // Compute the default target features, we need the target to handle this
5555   // because features may have dependencies on one another.
5556   llvm::StringMap<bool> Features;
5557   Target->getDefaultFeatures(Features);
5558 
5559   // Apply the user specified deltas.
5560   // First the enables.
5561   for (std::vector<std::string>::const_iterator
5562          it = Opts->FeaturesAsWritten.begin(),
5563          ie = Opts->FeaturesAsWritten.end();
5564        it != ie; ++it) {
5565     const char *Name = it->c_str();
5566 
5567     if (Name[0] != '+')
5568       continue;
5569 
5570     // Apply the feature via the target.
5571     if (!Target->setFeatureEnabled(Features, Name + 1, true)) {
5572       Diags.Report(diag::err_target_invalid_feature) << Name;
5573       return 0;
5574     }
5575   }
5576 
5577   // Then the disables.
5578   for (std::vector<std::string>::const_iterator
5579          it = Opts->FeaturesAsWritten.begin(),
5580          ie = Opts->FeaturesAsWritten.end();
5581        it != ie; ++it) {
5582     const char *Name = it->c_str();
5583 
5584     if (Name[0] == '+')
5585       continue;
5586 
5587     // Apply the feature via the target.
5588     if (Name[0] != '-' ||
5589         !Target->setFeatureEnabled(Features, Name + 1, false)) {
5590       Diags.Report(diag::err_target_invalid_feature) << Name;
5591       return 0;
5592     }
5593   }
5594 
5595   // Add the features to the compile options.
5596   //
5597   // FIXME: If we are completely confident that we have the right set, we only
5598   // need to pass the minuses.
5599   Opts->Features.clear();
5600   for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
5601          ie = Features.end(); it != ie; ++it)
5602     Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
5603   Target->HandleTargetFeatures(Opts->Features);
5604 
5605   return Target.take();
5606 }
5607