1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 115 const llvm::Triple &Triple, 116 StringRef &PlatformName, 117 VersionTuple &PlatformMinVersion) { 118 Builder.defineMacro("__APPLE_CC__", "6000"); 119 Builder.defineMacro("__APPLE__"); 120 Builder.defineMacro("__STDC_NO_THREADS__"); 121 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 122 // AddressSanitizer doesn't play well with source fortification, which is on 123 // by default on Darwin. 124 if (Opts.Sanitize.has(SanitizerKind::Address)) 125 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 126 127 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 128 if (!Opts.ObjC1) { 129 // __weak is always defined, for use in blocks and with objc pointers. 130 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 131 Builder.defineMacro("__strong", ""); 132 Builder.defineMacro("__unsafe_unretained", ""); 133 } 134 135 if (Opts.Static) 136 Builder.defineMacro("__STATIC__"); 137 else 138 Builder.defineMacro("__DYNAMIC__"); 139 140 if (Opts.POSIXThreads) 141 Builder.defineMacro("_REENTRANT"); 142 143 // Get the platform type and version number from the triple. 144 unsigned Maj, Min, Rev; 145 if (Triple.isMacOSX()) { 146 Triple.getMacOSXVersion(Maj, Min, Rev); 147 PlatformName = "macos"; 148 } else { 149 Triple.getOSVersion(Maj, Min, Rev); 150 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 151 } 152 153 // If -target arch-pc-win32-macho option specified, we're 154 // generating code for Win32 ABI. No need to emit 155 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 156 if (PlatformName == "win32") { 157 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 158 return; 159 } 160 161 // Set the appropriate OS version define. 162 if (Triple.isiOS()) { 163 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 164 char Str[7]; 165 if (Maj < 10) { 166 Str[0] = '0' + Maj; 167 Str[1] = '0' + (Min / 10); 168 Str[2] = '0' + (Min % 10); 169 Str[3] = '0' + (Rev / 10); 170 Str[4] = '0' + (Rev % 10); 171 Str[5] = '\0'; 172 } else { 173 // Handle versions >= 10. 174 Str[0] = '0' + (Maj / 10); 175 Str[1] = '0' + (Maj % 10); 176 Str[2] = '0' + (Min / 10); 177 Str[3] = '0' + (Min % 10); 178 Str[4] = '0' + (Rev / 10); 179 Str[5] = '0' + (Rev % 10); 180 Str[6] = '\0'; 181 } 182 if (Triple.isTvOS()) 183 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 184 else 185 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 186 Str); 187 188 } else if (Triple.isWatchOS()) { 189 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 190 char Str[6]; 191 Str[0] = '0' + Maj; 192 Str[1] = '0' + (Min / 10); 193 Str[2] = '0' + (Min % 10); 194 Str[3] = '0' + (Rev / 10); 195 Str[4] = '0' + (Rev % 10); 196 Str[5] = '\0'; 197 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 198 } else if (Triple.isMacOSX()) { 199 // Note that the Driver allows versions which aren't representable in the 200 // define (because we only get a single digit for the minor and micro 201 // revision numbers). So, we limit them to the maximum representable 202 // version. 203 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 204 char Str[7]; 205 if (Maj < 10 || (Maj == 10 && Min < 10)) { 206 Str[0] = '0' + (Maj / 10); 207 Str[1] = '0' + (Maj % 10); 208 Str[2] = '0' + std::min(Min, 9U); 209 Str[3] = '0' + std::min(Rev, 9U); 210 Str[4] = '\0'; 211 } else { 212 // Handle versions > 10.9. 213 Str[0] = '0' + (Maj / 10); 214 Str[1] = '0' + (Maj % 10); 215 Str[2] = '0' + (Min / 10); 216 Str[3] = '0' + (Min % 10); 217 Str[4] = '0' + (Rev / 10); 218 Str[5] = '0' + (Rev % 10); 219 Str[6] = '\0'; 220 } 221 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 222 } 223 224 // Tell users about the kernel if there is one. 225 if (Triple.isOSDarwin()) 226 Builder.defineMacro("__MACH__"); 227 228 // The Watch ABI uses Dwarf EH. 229 if(Triple.isWatchABI()) 230 Builder.defineMacro("__ARM_DWARF_EH__"); 231 232 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 233 } 234 235 template<typename Target> 236 class DarwinTargetInfo : public OSTargetInfo<Target> { 237 protected: 238 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 239 MacroBuilder &Builder) const override { 240 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 241 this->PlatformMinVersion); 242 } 243 244 public: 245 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 246 : OSTargetInfo<Target>(Triple, Opts) { 247 // By default, no TLS, and we whitelist permitted architecture/OS 248 // combinations. 249 this->TLSSupported = false; 250 251 if (Triple.isMacOSX()) 252 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 253 else if (Triple.isiOS()) { 254 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 255 if (Triple.getArch() == llvm::Triple::x86_64 || 256 Triple.getArch() == llvm::Triple::aarch64) 257 this->TLSSupported = !Triple.isOSVersionLT(8); 258 else if (Triple.getArch() == llvm::Triple::x86 || 259 Triple.getArch() == llvm::Triple::arm || 260 Triple.getArch() == llvm::Triple::thumb) 261 this->TLSSupported = !Triple.isOSVersionLT(9); 262 } else if (Triple.isWatchOS()) 263 this->TLSSupported = !Triple.isOSVersionLT(2); 264 265 this->MCountName = "\01mcount"; 266 } 267 268 std::string isValidSectionSpecifier(StringRef SR) const override { 269 // Let MCSectionMachO validate this. 270 StringRef Segment, Section; 271 unsigned TAA, StubSize; 272 bool HasTAA; 273 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 274 TAA, HasTAA, StubSize); 275 } 276 277 const char *getStaticInitSectionSpecifier() const override { 278 // FIXME: We should return 0 when building kexts. 279 return "__TEXT,__StaticInit,regular,pure_instructions"; 280 } 281 282 /// Darwin does not support protected visibility. Darwin's "default" 283 /// is very similar to ELF's "protected"; Darwin requires a "weak" 284 /// attribute on declarations that can be dynamically replaced. 285 bool hasProtectedVisibility() const override { 286 return false; 287 } 288 289 unsigned getExnObjectAlignment() const override { 290 // The alignment of an exception object is 8-bytes for darwin since 291 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 292 // and therefore doesn't guarantee 16-byte alignment. 293 return 64; 294 } 295 }; 296 297 298 // DragonFlyBSD Target 299 template<typename Target> 300 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 301 protected: 302 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 303 MacroBuilder &Builder) const override { 304 // DragonFly defines; list based off of gcc output 305 Builder.defineMacro("__DragonFly__"); 306 Builder.defineMacro("__DragonFly_cc_version", "100001"); 307 Builder.defineMacro("__ELF__"); 308 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 309 Builder.defineMacro("__tune_i386__"); 310 DefineStd(Builder, "unix", Opts); 311 } 312 public: 313 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 314 : OSTargetInfo<Target>(Triple, Opts) { 315 switch (Triple.getArch()) { 316 default: 317 case llvm::Triple::x86: 318 case llvm::Triple::x86_64: 319 this->MCountName = ".mcount"; 320 break; 321 } 322 } 323 }; 324 325 #ifndef FREEBSD_CC_VERSION 326 #define FREEBSD_CC_VERSION 0U 327 #endif 328 329 // FreeBSD Target 330 template<typename Target> 331 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 332 protected: 333 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 334 MacroBuilder &Builder) const override { 335 // FreeBSD defines; list based off of gcc output 336 337 unsigned Release = Triple.getOSMajorVersion(); 338 if (Release == 0U) 339 Release = 8U; 340 unsigned CCVersion = FREEBSD_CC_VERSION; 341 if (CCVersion == 0U) 342 CCVersion = Release * 100000U + 1U; 343 344 Builder.defineMacro("__FreeBSD__", Twine(Release)); 345 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 346 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 347 DefineStd(Builder, "unix", Opts); 348 Builder.defineMacro("__ELF__"); 349 350 // On FreeBSD, wchar_t contains the number of the code point as 351 // used by the character set of the locale. These character sets are 352 // not necessarily a superset of ASCII. 353 // 354 // FIXME: This is wrong; the macro refers to the numerical values 355 // of wchar_t *literals*, which are not locale-dependent. However, 356 // FreeBSD systems apparently depend on us getting this wrong, and 357 // setting this to 1 is conforming even if all the basic source 358 // character literals have the same encoding as char and wchar_t. 359 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 360 } 361 public: 362 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 363 : OSTargetInfo<Target>(Triple, Opts) { 364 switch (Triple.getArch()) { 365 default: 366 case llvm::Triple::x86: 367 case llvm::Triple::x86_64: 368 this->MCountName = ".mcount"; 369 break; 370 case llvm::Triple::mips: 371 case llvm::Triple::mipsel: 372 case llvm::Triple::ppc: 373 case llvm::Triple::ppc64: 374 case llvm::Triple::ppc64le: 375 this->MCountName = "_mcount"; 376 break; 377 case llvm::Triple::arm: 378 this->MCountName = "__mcount"; 379 break; 380 } 381 } 382 }; 383 384 // GNU/kFreeBSD Target 385 template<typename Target> 386 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 387 protected: 388 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 389 MacroBuilder &Builder) const override { 390 // GNU/kFreeBSD defines; list based off of gcc output 391 392 DefineStd(Builder, "unix", Opts); 393 Builder.defineMacro("__FreeBSD_kernel__"); 394 Builder.defineMacro("__GLIBC__"); 395 Builder.defineMacro("__ELF__"); 396 if (Opts.POSIXThreads) 397 Builder.defineMacro("_REENTRANT"); 398 if (Opts.CPlusPlus) 399 Builder.defineMacro("_GNU_SOURCE"); 400 } 401 public: 402 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 403 : OSTargetInfo<Target>(Triple, Opts) {} 404 }; 405 406 // Haiku Target 407 template<typename Target> 408 class HaikuTargetInfo : public OSTargetInfo<Target> { 409 protected: 410 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 411 MacroBuilder &Builder) const override { 412 // Haiku defines; list based off of gcc output 413 Builder.defineMacro("__HAIKU__"); 414 Builder.defineMacro("__ELF__"); 415 DefineStd(Builder, "unix", Opts); 416 } 417 public: 418 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 419 : OSTargetInfo<Target>(Triple, Opts) { 420 this->SizeType = TargetInfo::UnsignedLong; 421 this->IntPtrType = TargetInfo::SignedLong; 422 this->PtrDiffType = TargetInfo::SignedLong; 423 this->ProcessIDType = TargetInfo::SignedLong; 424 this->TLSSupported = false; 425 426 } 427 }; 428 429 // Minix Target 430 template<typename Target> 431 class MinixTargetInfo : public OSTargetInfo<Target> { 432 protected: 433 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 434 MacroBuilder &Builder) const override { 435 // Minix defines 436 437 Builder.defineMacro("__minix", "3"); 438 Builder.defineMacro("_EM_WSIZE", "4"); 439 Builder.defineMacro("_EM_PSIZE", "4"); 440 Builder.defineMacro("_EM_SSIZE", "2"); 441 Builder.defineMacro("_EM_LSIZE", "4"); 442 Builder.defineMacro("_EM_FSIZE", "4"); 443 Builder.defineMacro("_EM_DSIZE", "8"); 444 Builder.defineMacro("__ELF__"); 445 DefineStd(Builder, "unix", Opts); 446 } 447 public: 448 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 449 : OSTargetInfo<Target>(Triple, Opts) {} 450 }; 451 452 // Linux target 453 template<typename Target> 454 class LinuxTargetInfo : public OSTargetInfo<Target> { 455 protected: 456 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 457 MacroBuilder &Builder) const override { 458 // Linux defines; list based off of gcc output 459 DefineStd(Builder, "unix", Opts); 460 DefineStd(Builder, "linux", Opts); 461 Builder.defineMacro("__gnu_linux__"); 462 Builder.defineMacro("__ELF__"); 463 if (Triple.isAndroid()) { 464 Builder.defineMacro("__ANDROID__", "1"); 465 unsigned Maj, Min, Rev; 466 Triple.getEnvironmentVersion(Maj, Min, Rev); 467 this->PlatformName = "android"; 468 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 469 if (Maj) 470 Builder.defineMacro("__ANDROID_API__", Twine(Maj)); 471 } 472 if (Opts.POSIXThreads) 473 Builder.defineMacro("_REENTRANT"); 474 if (Opts.CPlusPlus) 475 Builder.defineMacro("_GNU_SOURCE"); 476 if (this->HasFloat128) 477 Builder.defineMacro("__FLOAT128__"); 478 } 479 public: 480 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 481 : OSTargetInfo<Target>(Triple, Opts) { 482 this->WIntType = TargetInfo::UnsignedInt; 483 484 switch (Triple.getArch()) { 485 default: 486 break; 487 case llvm::Triple::ppc: 488 case llvm::Triple::ppc64: 489 case llvm::Triple::ppc64le: 490 this->MCountName = "_mcount"; 491 break; 492 case llvm::Triple::x86: 493 case llvm::Triple::x86_64: 494 case llvm::Triple::systemz: 495 this->HasFloat128 = true; 496 break; 497 } 498 } 499 500 const char *getStaticInitSectionSpecifier() const override { 501 return ".text.startup"; 502 } 503 }; 504 505 // NetBSD Target 506 template<typename Target> 507 class NetBSDTargetInfo : public OSTargetInfo<Target> { 508 protected: 509 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 510 MacroBuilder &Builder) const override { 511 // NetBSD defines; list based off of gcc output 512 Builder.defineMacro("__NetBSD__"); 513 Builder.defineMacro("__unix__"); 514 Builder.defineMacro("__ELF__"); 515 if (Opts.POSIXThreads) 516 Builder.defineMacro("_REENTRANT"); 517 518 switch (Triple.getArch()) { 519 default: 520 break; 521 case llvm::Triple::arm: 522 case llvm::Triple::armeb: 523 case llvm::Triple::thumb: 524 case llvm::Triple::thumbeb: 525 Builder.defineMacro("__ARM_DWARF_EH__"); 526 break; 527 } 528 } 529 public: 530 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 531 : OSTargetInfo<Target>(Triple, Opts) { 532 this->MCountName = "_mcount"; 533 } 534 }; 535 536 // OpenBSD Target 537 template<typename Target> 538 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 539 protected: 540 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 541 MacroBuilder &Builder) const override { 542 // OpenBSD defines; list based off of gcc output 543 544 Builder.defineMacro("__OpenBSD__"); 545 DefineStd(Builder, "unix", Opts); 546 Builder.defineMacro("__ELF__"); 547 if (Opts.POSIXThreads) 548 Builder.defineMacro("_REENTRANT"); 549 if (this->HasFloat128) 550 Builder.defineMacro("__FLOAT128__"); 551 } 552 public: 553 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 554 : OSTargetInfo<Target>(Triple, Opts) { 555 this->TLSSupported = false; 556 557 switch (Triple.getArch()) { 558 case llvm::Triple::x86: 559 case llvm::Triple::x86_64: 560 this->HasFloat128 = true; 561 // FALLTHROUGH 562 default: 563 this->MCountName = "__mcount"; 564 break; 565 case llvm::Triple::mips64: 566 case llvm::Triple::mips64el: 567 case llvm::Triple::ppc: 568 case llvm::Triple::sparcv9: 569 this->MCountName = "_mcount"; 570 break; 571 } 572 } 573 }; 574 575 // Bitrig Target 576 template<typename Target> 577 class BitrigTargetInfo : public OSTargetInfo<Target> { 578 protected: 579 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 580 MacroBuilder &Builder) const override { 581 // Bitrig defines; list based off of gcc output 582 583 Builder.defineMacro("__Bitrig__"); 584 DefineStd(Builder, "unix", Opts); 585 Builder.defineMacro("__ELF__"); 586 if (Opts.POSIXThreads) 587 Builder.defineMacro("_REENTRANT"); 588 589 switch (Triple.getArch()) { 590 default: 591 break; 592 case llvm::Triple::arm: 593 case llvm::Triple::armeb: 594 case llvm::Triple::thumb: 595 case llvm::Triple::thumbeb: 596 Builder.defineMacro("__ARM_DWARF_EH__"); 597 break; 598 } 599 } 600 public: 601 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 602 : OSTargetInfo<Target>(Triple, Opts) { 603 this->MCountName = "__mcount"; 604 } 605 }; 606 607 // PSP Target 608 template<typename Target> 609 class PSPTargetInfo : public OSTargetInfo<Target> { 610 protected: 611 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 612 MacroBuilder &Builder) const override { 613 // PSP defines; list based on the output of the pspdev gcc toolchain. 614 Builder.defineMacro("PSP"); 615 Builder.defineMacro("_PSP"); 616 Builder.defineMacro("__psp__"); 617 Builder.defineMacro("__ELF__"); 618 } 619 public: 620 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 621 }; 622 623 // PS3 PPU Target 624 template<typename Target> 625 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 626 protected: 627 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 628 MacroBuilder &Builder) const override { 629 // PS3 PPU defines. 630 Builder.defineMacro("__PPC__"); 631 Builder.defineMacro("__PPU__"); 632 Builder.defineMacro("__CELLOS_LV2__"); 633 Builder.defineMacro("__ELF__"); 634 Builder.defineMacro("__LP32__"); 635 Builder.defineMacro("_ARCH_PPC64"); 636 Builder.defineMacro("__powerpc64__"); 637 } 638 public: 639 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 640 : OSTargetInfo<Target>(Triple, Opts) { 641 this->LongWidth = this->LongAlign = 32; 642 this->PointerWidth = this->PointerAlign = 32; 643 this->IntMaxType = TargetInfo::SignedLongLong; 644 this->Int64Type = TargetInfo::SignedLongLong; 645 this->SizeType = TargetInfo::UnsignedInt; 646 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 647 } 648 }; 649 650 template <typename Target> 651 class PS4OSTargetInfo : public OSTargetInfo<Target> { 652 protected: 653 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 654 MacroBuilder &Builder) const override { 655 Builder.defineMacro("__FreeBSD__", "9"); 656 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 657 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 658 DefineStd(Builder, "unix", Opts); 659 Builder.defineMacro("__ELF__"); 660 Builder.defineMacro("__ORBIS__"); 661 } 662 public: 663 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 664 : OSTargetInfo<Target>(Triple, Opts) { 665 this->WCharType = this->UnsignedShort; 666 667 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 668 this->MaxTLSAlign = 256; 669 670 // On PS4, do not honor explicit bit field alignment, 671 // as in "__attribute__((aligned(2))) int b : 1;". 672 this->UseExplicitBitFieldAlignment = false; 673 674 switch (Triple.getArch()) { 675 default: 676 case llvm::Triple::x86_64: 677 this->MCountName = ".mcount"; 678 break; 679 } 680 } 681 }; 682 683 // Solaris target 684 template<typename Target> 685 class SolarisTargetInfo : public OSTargetInfo<Target> { 686 protected: 687 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 688 MacroBuilder &Builder) const override { 689 DefineStd(Builder, "sun", Opts); 690 DefineStd(Builder, "unix", Opts); 691 Builder.defineMacro("__ELF__"); 692 Builder.defineMacro("__svr4__"); 693 Builder.defineMacro("__SVR4"); 694 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 695 // newer, but to 500 for everything else. feature_test.h has a check to 696 // ensure that you are not using C99 with an old version of X/Open or C89 697 // with a new version. 698 if (Opts.C99) 699 Builder.defineMacro("_XOPEN_SOURCE", "600"); 700 else 701 Builder.defineMacro("_XOPEN_SOURCE", "500"); 702 if (Opts.CPlusPlus) 703 Builder.defineMacro("__C99FEATURES__"); 704 Builder.defineMacro("_LARGEFILE_SOURCE"); 705 Builder.defineMacro("_LARGEFILE64_SOURCE"); 706 Builder.defineMacro("__EXTENSIONS__"); 707 Builder.defineMacro("_REENTRANT"); 708 } 709 public: 710 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 711 : OSTargetInfo<Target>(Triple, Opts) { 712 this->WCharType = this->SignedInt; 713 // FIXME: WIntType should be SignedLong 714 } 715 }; 716 717 // Windows target 718 template<typename Target> 719 class WindowsTargetInfo : public OSTargetInfo<Target> { 720 protected: 721 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 722 MacroBuilder &Builder) const override { 723 Builder.defineMacro("_WIN32"); 724 } 725 void getVisualStudioDefines(const LangOptions &Opts, 726 MacroBuilder &Builder) const { 727 if (Opts.CPlusPlus) { 728 if (Opts.RTTIData) 729 Builder.defineMacro("_CPPRTTI"); 730 731 if (Opts.CXXExceptions) 732 Builder.defineMacro("_CPPUNWIND"); 733 } 734 735 if (Opts.Bool) 736 Builder.defineMacro("__BOOL_DEFINED"); 737 738 if (!Opts.CharIsSigned) 739 Builder.defineMacro("_CHAR_UNSIGNED"); 740 741 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 742 // but it works for now. 743 if (Opts.POSIXThreads) 744 Builder.defineMacro("_MT"); 745 746 if (Opts.MSCompatibilityVersion) { 747 Builder.defineMacro("_MSC_VER", 748 Twine(Opts.MSCompatibilityVersion / 100000)); 749 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 750 // FIXME We cannot encode the revision information into 32-bits 751 Builder.defineMacro("_MSC_BUILD", Twine(1)); 752 753 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 754 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 755 756 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 757 if (Opts.CPlusPlus1z) 758 Builder.defineMacro("_MSVC_LANG", "201403L"); 759 else if (Opts.CPlusPlus14) 760 Builder.defineMacro("_MSVC_LANG", "201402L"); 761 } 762 } 763 764 if (Opts.MicrosoftExt) { 765 Builder.defineMacro("_MSC_EXTENSIONS"); 766 767 if (Opts.CPlusPlus11) { 768 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 769 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 770 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 771 } 772 } 773 774 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 775 } 776 777 public: 778 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 779 : OSTargetInfo<Target>(Triple, Opts) {} 780 }; 781 782 template <typename Target> 783 class NaClTargetInfo : public OSTargetInfo<Target> { 784 protected: 785 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 786 MacroBuilder &Builder) const override { 787 if (Opts.POSIXThreads) 788 Builder.defineMacro("_REENTRANT"); 789 if (Opts.CPlusPlus) 790 Builder.defineMacro("_GNU_SOURCE"); 791 792 DefineStd(Builder, "unix", Opts); 793 Builder.defineMacro("__ELF__"); 794 Builder.defineMacro("__native_client__"); 795 } 796 797 public: 798 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 799 : OSTargetInfo<Target>(Triple, Opts) { 800 this->LongAlign = 32; 801 this->LongWidth = 32; 802 this->PointerAlign = 32; 803 this->PointerWidth = 32; 804 this->IntMaxType = TargetInfo::SignedLongLong; 805 this->Int64Type = TargetInfo::SignedLongLong; 806 this->DoubleAlign = 64; 807 this->LongDoubleWidth = 64; 808 this->LongDoubleAlign = 64; 809 this->LongLongWidth = 64; 810 this->LongLongAlign = 64; 811 this->SizeType = TargetInfo::UnsignedInt; 812 this->PtrDiffType = TargetInfo::SignedInt; 813 this->IntPtrType = TargetInfo::SignedInt; 814 // RegParmMax is inherited from the underlying architecture. 815 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 816 if (Triple.getArch() == llvm::Triple::arm) { 817 // Handled in ARM's setABI(). 818 } else if (Triple.getArch() == llvm::Triple::x86) { 819 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 820 } else if (Triple.getArch() == llvm::Triple::x86_64) { 821 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 822 } else if (Triple.getArch() == llvm::Triple::mipsel) { 823 // Handled on mips' setDataLayout. 824 } else { 825 assert(Triple.getArch() == llvm::Triple::le32); 826 this->resetDataLayout("e-p:32:32-i64:64"); 827 } 828 } 829 }; 830 831 // Fuchsia Target 832 template<typename Target> 833 class FuchsiaTargetInfo : public OSTargetInfo<Target> { 834 protected: 835 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 836 MacroBuilder &Builder) const override { 837 Builder.defineMacro("__Fuchsia__"); 838 Builder.defineMacro("__ELF__"); 839 if (Opts.POSIXThreads) 840 Builder.defineMacro("_REENTRANT"); 841 // Required by the libc++ locale support. 842 if (Opts.CPlusPlus) 843 Builder.defineMacro("_GNU_SOURCE"); 844 } 845 public: 846 FuchsiaTargetInfo(const llvm::Triple &Triple, 847 const TargetOptions &Opts) 848 : OSTargetInfo<Target>(Triple, Opts) { 849 this->MCountName = "__mcount"; 850 } 851 }; 852 853 // WebAssembly target 854 template <typename Target> 855 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 856 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 857 MacroBuilder &Builder) const final { 858 // A common platform macro. 859 if (Opts.POSIXThreads) 860 Builder.defineMacro("_REENTRANT"); 861 // Follow g++ convention and predefine _GNU_SOURCE for C++. 862 if (Opts.CPlusPlus) 863 Builder.defineMacro("_GNU_SOURCE"); 864 } 865 866 // As an optimization, group static init code together in a section. 867 const char *getStaticInitSectionSpecifier() const final { 868 return ".text.__startup"; 869 } 870 871 public: 872 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 873 const TargetOptions &Opts) 874 : OSTargetInfo<Target>(Triple, Opts) { 875 this->MCountName = "__mcount"; 876 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 877 } 878 }; 879 880 //===----------------------------------------------------------------------===// 881 // Specific target implementations. 882 //===----------------------------------------------------------------------===// 883 884 // PPC abstract base class 885 class PPCTargetInfo : public TargetInfo { 886 static const Builtin::Info BuiltinInfo[]; 887 static const char * const GCCRegNames[]; 888 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 889 std::string CPU; 890 891 // Target cpu features. 892 bool HasAltivec; 893 bool HasVSX; 894 bool HasP8Vector; 895 bool HasP8Crypto; 896 bool HasDirectMove; 897 bool HasQPX; 898 bool HasHTM; 899 bool HasBPERMD; 900 bool HasExtDiv; 901 bool HasP9Vector; 902 903 protected: 904 std::string ABI; 905 906 public: 907 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 908 : TargetInfo(Triple), HasAltivec(false), HasVSX(false), HasP8Vector(false), 909 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 910 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) { 911 SuitableAlign = 128; 912 SimdDefaultAlign = 128; 913 LongDoubleWidth = LongDoubleAlign = 128; 914 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 915 } 916 917 /// \brief Flags for architecture specific defines. 918 typedef enum { 919 ArchDefineNone = 0, 920 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 921 ArchDefinePpcgr = 1 << 1, 922 ArchDefinePpcsq = 1 << 2, 923 ArchDefine440 = 1 << 3, 924 ArchDefine603 = 1 << 4, 925 ArchDefine604 = 1 << 5, 926 ArchDefinePwr4 = 1 << 6, 927 ArchDefinePwr5 = 1 << 7, 928 ArchDefinePwr5x = 1 << 8, 929 ArchDefinePwr6 = 1 << 9, 930 ArchDefinePwr6x = 1 << 10, 931 ArchDefinePwr7 = 1 << 11, 932 ArchDefinePwr8 = 1 << 12, 933 ArchDefinePwr9 = 1 << 13, 934 ArchDefineA2 = 1 << 14, 935 ArchDefineA2q = 1 << 15 936 } ArchDefineTypes; 937 938 // Set the language option for altivec based on our value. 939 void adjust(LangOptions &Opts) override { 940 if (HasAltivec) 941 Opts.AltiVec = 1; 942 TargetInfo::adjust(Opts); 943 } 944 945 // Note: GCC recognizes the following additional cpus: 946 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 947 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 948 // titan, rs64. 949 bool setCPU(const std::string &Name) override { 950 bool CPUKnown = llvm::StringSwitch<bool>(Name) 951 .Case("generic", true) 952 .Case("440", true) 953 .Case("450", true) 954 .Case("601", true) 955 .Case("602", true) 956 .Case("603", true) 957 .Case("603e", true) 958 .Case("603ev", true) 959 .Case("604", true) 960 .Case("604e", true) 961 .Case("620", true) 962 .Case("630", true) 963 .Case("g3", true) 964 .Case("7400", true) 965 .Case("g4", true) 966 .Case("7450", true) 967 .Case("g4+", true) 968 .Case("750", true) 969 .Case("970", true) 970 .Case("g5", true) 971 .Case("a2", true) 972 .Case("a2q", true) 973 .Case("e500mc", true) 974 .Case("e5500", true) 975 .Case("power3", true) 976 .Case("pwr3", true) 977 .Case("power4", true) 978 .Case("pwr4", true) 979 .Case("power5", true) 980 .Case("pwr5", true) 981 .Case("power5x", true) 982 .Case("pwr5x", true) 983 .Case("power6", true) 984 .Case("pwr6", true) 985 .Case("power6x", true) 986 .Case("pwr6x", true) 987 .Case("power7", true) 988 .Case("pwr7", true) 989 .Case("power8", true) 990 .Case("pwr8", true) 991 .Case("power9", true) 992 .Case("pwr9", true) 993 .Case("powerpc", true) 994 .Case("ppc", true) 995 .Case("powerpc64", true) 996 .Case("ppc64", true) 997 .Case("powerpc64le", true) 998 .Case("ppc64le", true) 999 .Default(false); 1000 1001 if (CPUKnown) 1002 CPU = Name; 1003 1004 return CPUKnown; 1005 } 1006 1007 1008 StringRef getABI() const override { return ABI; } 1009 1010 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1011 return llvm::makeArrayRef(BuiltinInfo, 1012 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 1013 } 1014 1015 bool isCLZForZeroUndef() const override { return false; } 1016 1017 void getTargetDefines(const LangOptions &Opts, 1018 MacroBuilder &Builder) const override; 1019 1020 bool 1021 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1022 StringRef CPU, 1023 const std::vector<std::string> &FeaturesVec) const override; 1024 1025 bool handleTargetFeatures(std::vector<std::string> &Features, 1026 DiagnosticsEngine &Diags) override; 1027 bool hasFeature(StringRef Feature) const override; 1028 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 1029 bool Enabled) const override; 1030 1031 ArrayRef<const char *> getGCCRegNames() const override; 1032 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 1033 bool validateAsmConstraint(const char *&Name, 1034 TargetInfo::ConstraintInfo &Info) const override { 1035 switch (*Name) { 1036 default: return false; 1037 case 'O': // Zero 1038 break; 1039 case 'b': // Base register 1040 case 'f': // Floating point register 1041 Info.setAllowsRegister(); 1042 break; 1043 // FIXME: The following are added to allow parsing. 1044 // I just took a guess at what the actions should be. 1045 // Also, is more specific checking needed? I.e. specific registers? 1046 case 'd': // Floating point register (containing 64-bit value) 1047 case 'v': // Altivec vector register 1048 Info.setAllowsRegister(); 1049 break; 1050 case 'w': 1051 switch (Name[1]) { 1052 case 'd':// VSX vector register to hold vector double data 1053 case 'f':// VSX vector register to hold vector float data 1054 case 's':// VSX vector register to hold scalar float data 1055 case 'a':// Any VSX register 1056 case 'c':// An individual CR bit 1057 break; 1058 default: 1059 return false; 1060 } 1061 Info.setAllowsRegister(); 1062 Name++; // Skip over 'w'. 1063 break; 1064 case 'h': // `MQ', `CTR', or `LINK' register 1065 case 'q': // `MQ' register 1066 case 'c': // `CTR' register 1067 case 'l': // `LINK' register 1068 case 'x': // `CR' register (condition register) number 0 1069 case 'y': // `CR' register (condition register) 1070 case 'z': // `XER[CA]' carry bit (part of the XER register) 1071 Info.setAllowsRegister(); 1072 break; 1073 case 'I': // Signed 16-bit constant 1074 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1075 // (use `L' instead for SImode constants) 1076 case 'K': // Unsigned 16-bit constant 1077 case 'L': // Signed 16-bit constant shifted left 16 bits 1078 case 'M': // Constant larger than 31 1079 case 'N': // Exact power of 2 1080 case 'P': // Constant whose negation is a signed 16-bit constant 1081 case 'G': // Floating point constant that can be loaded into a 1082 // register with one instruction per word 1083 case 'H': // Integer/Floating point constant that can be loaded 1084 // into a register using three instructions 1085 break; 1086 case 'm': // Memory operand. Note that on PowerPC targets, m can 1087 // include addresses that update the base register. It 1088 // is therefore only safe to use `m' in an asm statement 1089 // if that asm statement accesses the operand exactly once. 1090 // The asm statement must also use `%U<opno>' as a 1091 // placeholder for the "update" flag in the corresponding 1092 // load or store instruction. For example: 1093 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1094 // is correct but: 1095 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1096 // is not. Use es rather than m if you don't want the base 1097 // register to be updated. 1098 case 'e': 1099 if (Name[1] != 's') 1100 return false; 1101 // es: A "stable" memory operand; that is, one which does not 1102 // include any automodification of the base register. Unlike 1103 // `m', this constraint can be used in asm statements that 1104 // might access the operand several times, or that might not 1105 // access it at all. 1106 Info.setAllowsMemory(); 1107 Name++; // Skip over 'e'. 1108 break; 1109 case 'Q': // Memory operand that is an offset from a register (it is 1110 // usually better to use `m' or `es' in asm statements) 1111 case 'Z': // Memory operand that is an indexed or indirect from a 1112 // register (it is usually better to use `m' or `es' in 1113 // asm statements) 1114 Info.setAllowsMemory(); 1115 Info.setAllowsRegister(); 1116 break; 1117 case 'R': // AIX TOC entry 1118 case 'a': // Address operand that is an indexed or indirect from a 1119 // register (`p' is preferable for asm statements) 1120 case 'S': // Constant suitable as a 64-bit mask operand 1121 case 'T': // Constant suitable as a 32-bit mask operand 1122 case 'U': // System V Release 4 small data area reference 1123 case 't': // AND masks that can be performed by two rldic{l, r} 1124 // instructions 1125 case 'W': // Vector constant that does not require memory 1126 case 'j': // Vector constant that is all zeros. 1127 break; 1128 // End FIXME. 1129 } 1130 return true; 1131 } 1132 std::string convertConstraint(const char *&Constraint) const override { 1133 std::string R; 1134 switch (*Constraint) { 1135 case 'e': 1136 case 'w': 1137 // Two-character constraint; add "^" hint for later parsing. 1138 R = std::string("^") + std::string(Constraint, 2); 1139 Constraint++; 1140 break; 1141 default: 1142 return TargetInfo::convertConstraint(Constraint); 1143 } 1144 return R; 1145 } 1146 const char *getClobbers() const override { 1147 return ""; 1148 } 1149 int getEHDataRegisterNumber(unsigned RegNo) const override { 1150 if (RegNo == 0) return 3; 1151 if (RegNo == 1) return 4; 1152 return -1; 1153 } 1154 1155 bool hasSjLjLowering() const override { 1156 return true; 1157 } 1158 1159 bool useFloat128ManglingForLongDouble() const override { 1160 return LongDoubleWidth == 128 && 1161 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() && 1162 getTriple().isOSBinFormatELF(); 1163 } 1164 }; 1165 1166 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1167 #define BUILTIN(ID, TYPE, ATTRS) \ 1168 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1169 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1170 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1171 #include "clang/Basic/BuiltinsPPC.def" 1172 }; 1173 1174 /// handleTargetFeatures - Perform initialization based on the user 1175 /// configured set of features. 1176 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1177 DiagnosticsEngine &Diags) { 1178 for (const auto &Feature : Features) { 1179 if (Feature == "+altivec") { 1180 HasAltivec = true; 1181 } else if (Feature == "+vsx") { 1182 HasVSX = true; 1183 } else if (Feature == "+bpermd") { 1184 HasBPERMD = true; 1185 } else if (Feature == "+extdiv") { 1186 HasExtDiv = true; 1187 } else if (Feature == "+power8-vector") { 1188 HasP8Vector = true; 1189 } else if (Feature == "+crypto") { 1190 HasP8Crypto = true; 1191 } else if (Feature == "+direct-move") { 1192 HasDirectMove = true; 1193 } else if (Feature == "+qpx") { 1194 HasQPX = true; 1195 } else if (Feature == "+htm") { 1196 HasHTM = true; 1197 } else if (Feature == "+float128") { 1198 HasFloat128 = true; 1199 } else if (Feature == "+power9-vector") { 1200 HasP9Vector = true; 1201 } 1202 // TODO: Finish this list and add an assert that we've handled them 1203 // all. 1204 } 1205 1206 return true; 1207 } 1208 1209 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1210 /// #defines that are not tied to a specific subtarget. 1211 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1212 MacroBuilder &Builder) const { 1213 // Target identification. 1214 Builder.defineMacro("__ppc__"); 1215 Builder.defineMacro("__PPC__"); 1216 Builder.defineMacro("_ARCH_PPC"); 1217 Builder.defineMacro("__powerpc__"); 1218 Builder.defineMacro("__POWERPC__"); 1219 if (PointerWidth == 64) { 1220 Builder.defineMacro("_ARCH_PPC64"); 1221 Builder.defineMacro("__powerpc64__"); 1222 Builder.defineMacro("__ppc64__"); 1223 Builder.defineMacro("__PPC64__"); 1224 } 1225 1226 // Target properties. 1227 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1228 Builder.defineMacro("_LITTLE_ENDIAN"); 1229 } else { 1230 if (getTriple().getOS() != llvm::Triple::NetBSD && 1231 getTriple().getOS() != llvm::Triple::OpenBSD) 1232 Builder.defineMacro("_BIG_ENDIAN"); 1233 } 1234 1235 // ABI options. 1236 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1237 Builder.defineMacro("_CALL_ELF", "1"); 1238 if (ABI == "elfv2") 1239 Builder.defineMacro("_CALL_ELF", "2"); 1240 1241 // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but 1242 // our suppport post-dates this and it should work on all 64-bit ppc linux 1243 // platforms. It is guaranteed to work on all elfv2 platforms. 1244 if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64) 1245 Builder.defineMacro("_CALL_LINUX", "1"); 1246 1247 // Subtarget options. 1248 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1249 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1250 1251 // FIXME: Should be controlled by command line option. 1252 if (LongDoubleWidth == 128) { 1253 Builder.defineMacro("__LONG_DOUBLE_128__"); 1254 Builder.defineMacro("__LONGDOUBLE128"); 1255 } 1256 1257 // Define this for elfv2 (64-bit only) or 64-bit darwin. 1258 if (ABI == "elfv2" || 1259 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64)) 1260 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16"); 1261 1262 // CPU identification. 1263 ArchDefineTypes defs = 1264 (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1265 .Case("440", ArchDefineName) 1266 .Case("450", ArchDefineName | ArchDefine440) 1267 .Case("601", ArchDefineName) 1268 .Case("602", ArchDefineName | ArchDefinePpcgr) 1269 .Case("603", ArchDefineName | ArchDefinePpcgr) 1270 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1271 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1272 .Case("604", ArchDefineName | ArchDefinePpcgr) 1273 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1274 .Case("620", ArchDefineName | ArchDefinePpcgr) 1275 .Case("630", ArchDefineName | ArchDefinePpcgr) 1276 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1277 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1278 .Case("750", ArchDefineName | ArchDefinePpcgr) 1279 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1280 ArchDefinePpcsq) 1281 .Case("a2", ArchDefineA2) 1282 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1283 .Case("pwr3", ArchDefinePpcgr) 1284 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1285 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1286 ArchDefinePpcsq) 1287 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 | 1288 ArchDefinePpcgr | ArchDefinePpcsq) 1289 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 | 1290 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1291 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x | 1292 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1293 ArchDefinePpcsq) 1294 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 | 1295 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1296 ArchDefinePpcgr | ArchDefinePpcsq) 1297 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x | 1298 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1299 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1300 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 | 1301 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1302 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1303 ArchDefinePpcsq) 1304 .Case("power3", ArchDefinePpcgr) 1305 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1306 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1307 ArchDefinePpcsq) 1308 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1309 ArchDefinePpcgr | ArchDefinePpcsq) 1310 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1311 ArchDefinePwr4 | ArchDefinePpcgr | 1312 ArchDefinePpcsq) 1313 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1314 ArchDefinePwr5 | ArchDefinePwr4 | 1315 ArchDefinePpcgr | ArchDefinePpcsq) 1316 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 | 1317 ArchDefinePwr5x | ArchDefinePwr5 | 1318 ArchDefinePwr4 | ArchDefinePpcgr | 1319 ArchDefinePpcsq) 1320 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1321 ArchDefinePwr6 | ArchDefinePwr5x | 1322 ArchDefinePwr5 | ArchDefinePwr4 | 1323 ArchDefinePpcgr | ArchDefinePpcsq) 1324 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 1325 ArchDefinePwr6x | ArchDefinePwr6 | 1326 ArchDefinePwr5x | ArchDefinePwr5 | 1327 ArchDefinePwr4 | ArchDefinePpcgr | 1328 ArchDefinePpcsq) 1329 // powerpc64le automatically defaults to at least power8. 1330 .Case("ppc64le", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1331 ArchDefinePwr6 | ArchDefinePwr5x | 1332 ArchDefinePwr5 | ArchDefinePwr4 | 1333 ArchDefinePpcgr | ArchDefinePpcsq) 1334 .Default(ArchDefineNone); 1335 1336 if (defs & ArchDefineName) 1337 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1338 if (defs & ArchDefinePpcgr) 1339 Builder.defineMacro("_ARCH_PPCGR"); 1340 if (defs & ArchDefinePpcsq) 1341 Builder.defineMacro("_ARCH_PPCSQ"); 1342 if (defs & ArchDefine440) 1343 Builder.defineMacro("_ARCH_440"); 1344 if (defs & ArchDefine603) 1345 Builder.defineMacro("_ARCH_603"); 1346 if (defs & ArchDefine604) 1347 Builder.defineMacro("_ARCH_604"); 1348 if (defs & ArchDefinePwr4) 1349 Builder.defineMacro("_ARCH_PWR4"); 1350 if (defs & ArchDefinePwr5) 1351 Builder.defineMacro("_ARCH_PWR5"); 1352 if (defs & ArchDefinePwr5x) 1353 Builder.defineMacro("_ARCH_PWR5X"); 1354 if (defs & ArchDefinePwr6) 1355 Builder.defineMacro("_ARCH_PWR6"); 1356 if (defs & ArchDefinePwr6x) 1357 Builder.defineMacro("_ARCH_PWR6X"); 1358 if (defs & ArchDefinePwr7) 1359 Builder.defineMacro("_ARCH_PWR7"); 1360 if (defs & ArchDefinePwr8) 1361 Builder.defineMacro("_ARCH_PWR8"); 1362 if (defs & ArchDefinePwr9) 1363 Builder.defineMacro("_ARCH_PWR9"); 1364 if (defs & ArchDefineA2) 1365 Builder.defineMacro("_ARCH_A2"); 1366 if (defs & ArchDefineA2q) { 1367 Builder.defineMacro("_ARCH_A2Q"); 1368 Builder.defineMacro("_ARCH_QP"); 1369 } 1370 1371 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1372 Builder.defineMacro("__bg__"); 1373 Builder.defineMacro("__THW_BLUEGENE__"); 1374 Builder.defineMacro("__bgq__"); 1375 Builder.defineMacro("__TOS_BGQ__"); 1376 } 1377 1378 if (HasAltivec) { 1379 Builder.defineMacro("__VEC__", "10206"); 1380 Builder.defineMacro("__ALTIVEC__"); 1381 } 1382 if (HasVSX) 1383 Builder.defineMacro("__VSX__"); 1384 if (HasP8Vector) 1385 Builder.defineMacro("__POWER8_VECTOR__"); 1386 if (HasP8Crypto) 1387 Builder.defineMacro("__CRYPTO__"); 1388 if (HasHTM) 1389 Builder.defineMacro("__HTM__"); 1390 if (HasFloat128) 1391 Builder.defineMacro("__FLOAT128__"); 1392 if (HasP9Vector) 1393 Builder.defineMacro("__POWER9_VECTOR__"); 1394 1395 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1396 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1397 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1398 if (PointerWidth == 64) 1399 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1400 1401 // We have support for the bswap intrinsics so we can define this. 1402 Builder.defineMacro("__HAVE_BSWAP__", "1"); 1403 1404 // FIXME: The following are not yet generated here by Clang, but are 1405 // generated by GCC: 1406 // 1407 // _SOFT_FLOAT_ 1408 // __RECIP_PRECISION__ 1409 // __APPLE_ALTIVEC__ 1410 // __RECIP__ 1411 // __RECIPF__ 1412 // __RSQRTE__ 1413 // __RSQRTEF__ 1414 // _SOFT_DOUBLE_ 1415 // __NO_LWSYNC__ 1416 // __CMODEL_MEDIUM__ 1417 // __CMODEL_LARGE__ 1418 // _CALL_SYSV 1419 // _CALL_DARWIN 1420 // __NO_FPRS__ 1421 } 1422 1423 // Handle explicit options being passed to the compiler here: if we've 1424 // explicitly turned off vsx and turned on any of: 1425 // - power8-vector 1426 // - direct-move 1427 // - float128 1428 // - power9-vector 1429 // then go ahead and error since the customer has expressed an incompatible 1430 // set of options. 1431 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1432 const std::vector<std::string> &FeaturesVec) { 1433 1434 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1435 FeaturesVec.end()) { 1436 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1437 FeaturesVec.end()) { 1438 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1439 << "-mno-vsx"; 1440 return false; 1441 } 1442 1443 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1444 FeaturesVec.end()) { 1445 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1446 << "-mno-vsx"; 1447 return false; 1448 } 1449 1450 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1451 FeaturesVec.end()) { 1452 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1453 << "-mno-vsx"; 1454 return false; 1455 } 1456 1457 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") != 1458 FeaturesVec.end()) { 1459 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector" 1460 << "-mno-vsx"; 1461 return false; 1462 } 1463 } 1464 1465 return true; 1466 } 1467 1468 bool PPCTargetInfo::initFeatureMap( 1469 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1470 const std::vector<std::string> &FeaturesVec) const { 1471 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1472 .Case("7400", true) 1473 .Case("g4", true) 1474 .Case("7450", true) 1475 .Case("g4+", true) 1476 .Case("970", true) 1477 .Case("g5", true) 1478 .Case("pwr6", true) 1479 .Case("pwr7", true) 1480 .Case("pwr8", true) 1481 .Case("pwr9", true) 1482 .Case("ppc64", true) 1483 .Case("ppc64le", true) 1484 .Default(false); 1485 1486 Features["qpx"] = (CPU == "a2q"); 1487 Features["power9-vector"] = (CPU == "pwr9"); 1488 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1489 .Case("ppc64le", true) 1490 .Case("pwr9", true) 1491 .Case("pwr8", true) 1492 .Default(false); 1493 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1494 .Case("ppc64le", true) 1495 .Case("pwr9", true) 1496 .Case("pwr8", true) 1497 .Default(false); 1498 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1499 .Case("ppc64le", true) 1500 .Case("pwr9", true) 1501 .Case("pwr8", true) 1502 .Case("pwr7", true) 1503 .Default(false); 1504 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1505 .Case("ppc64le", true) 1506 .Case("pwr9", true) 1507 .Case("pwr8", true) 1508 .Case("pwr7", true) 1509 .Default(false); 1510 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1511 .Case("ppc64le", true) 1512 .Case("pwr9", true) 1513 .Case("pwr8", true) 1514 .Default(false); 1515 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1516 .Case("ppc64le", true) 1517 .Case("pwr9", true) 1518 .Case("pwr8", true) 1519 .Case("pwr7", true) 1520 .Default(false); 1521 Features["htm"] = llvm::StringSwitch<bool>(CPU) 1522 .Case("ppc64le", true) 1523 .Case("pwr9", true) 1524 .Case("pwr8", true) 1525 .Default(false); 1526 1527 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1528 return false; 1529 1530 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1531 } 1532 1533 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1534 return llvm::StringSwitch<bool>(Feature) 1535 .Case("powerpc", true) 1536 .Case("altivec", HasAltivec) 1537 .Case("vsx", HasVSX) 1538 .Case("power8-vector", HasP8Vector) 1539 .Case("crypto", HasP8Crypto) 1540 .Case("direct-move", HasDirectMove) 1541 .Case("qpx", HasQPX) 1542 .Case("htm", HasHTM) 1543 .Case("bpermd", HasBPERMD) 1544 .Case("extdiv", HasExtDiv) 1545 .Case("float128", HasFloat128) 1546 .Case("power9-vector", HasP9Vector) 1547 .Default(false); 1548 } 1549 1550 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1551 StringRef Name, bool Enabled) const { 1552 if (Enabled) { 1553 // If we're enabling any of the vsx based features then enable vsx and 1554 // altivec. We'll diagnose any problems later. 1555 bool FeatureHasVSX = llvm::StringSwitch<bool>(Name) 1556 .Case("vsx", true) 1557 .Case("direct-move", true) 1558 .Case("power8-vector", true) 1559 .Case("power9-vector", true) 1560 .Case("float128", true) 1561 .Default(false); 1562 if (FeatureHasVSX) 1563 Features["vsx"] = Features["altivec"] = true; 1564 if (Name == "power9-vector") 1565 Features["power8-vector"] = true; 1566 Features[Name] = true; 1567 } else { 1568 // If we're disabling altivec or vsx go ahead and disable all of the vsx 1569 // features. 1570 if ((Name == "altivec") || (Name == "vsx")) 1571 Features["vsx"] = Features["direct-move"] = Features["power8-vector"] = 1572 Features["float128"] = Features["power9-vector"] = false; 1573 if (Name == "power8-vector") 1574 Features["power9-vector"] = false; 1575 Features[Name] = false; 1576 } 1577 } 1578 1579 const char * const PPCTargetInfo::GCCRegNames[] = { 1580 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1581 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1582 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1583 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1584 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1585 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1586 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1587 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1588 "mq", "lr", "ctr", "ap", 1589 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1590 "xer", 1591 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1592 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1593 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1594 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1595 "vrsave", "vscr", 1596 "spe_acc", "spefscr", 1597 "sfp" 1598 }; 1599 1600 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1601 return llvm::makeArrayRef(GCCRegNames); 1602 } 1603 1604 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1605 // While some of these aliases do map to different registers 1606 // they still share the same register name. 1607 { { "0" }, "r0" }, 1608 { { "1"}, "r1" }, 1609 { { "2" }, "r2" }, 1610 { { "3" }, "r3" }, 1611 { { "4" }, "r4" }, 1612 { { "5" }, "r5" }, 1613 { { "6" }, "r6" }, 1614 { { "7" }, "r7" }, 1615 { { "8" }, "r8" }, 1616 { { "9" }, "r9" }, 1617 { { "10" }, "r10" }, 1618 { { "11" }, "r11" }, 1619 { { "12" }, "r12" }, 1620 { { "13" }, "r13" }, 1621 { { "14" }, "r14" }, 1622 { { "15" }, "r15" }, 1623 { { "16" }, "r16" }, 1624 { { "17" }, "r17" }, 1625 { { "18" }, "r18" }, 1626 { { "19" }, "r19" }, 1627 { { "20" }, "r20" }, 1628 { { "21" }, "r21" }, 1629 { { "22" }, "r22" }, 1630 { { "23" }, "r23" }, 1631 { { "24" }, "r24" }, 1632 { { "25" }, "r25" }, 1633 { { "26" }, "r26" }, 1634 { { "27" }, "r27" }, 1635 { { "28" }, "r28" }, 1636 { { "29" }, "r29" }, 1637 { { "30" }, "r30" }, 1638 { { "31" }, "r31" }, 1639 { { "fr0" }, "f0" }, 1640 { { "fr1" }, "f1" }, 1641 { { "fr2" }, "f2" }, 1642 { { "fr3" }, "f3" }, 1643 { { "fr4" }, "f4" }, 1644 { { "fr5" }, "f5" }, 1645 { { "fr6" }, "f6" }, 1646 { { "fr7" }, "f7" }, 1647 { { "fr8" }, "f8" }, 1648 { { "fr9" }, "f9" }, 1649 { { "fr10" }, "f10" }, 1650 { { "fr11" }, "f11" }, 1651 { { "fr12" }, "f12" }, 1652 { { "fr13" }, "f13" }, 1653 { { "fr14" }, "f14" }, 1654 { { "fr15" }, "f15" }, 1655 { { "fr16" }, "f16" }, 1656 { { "fr17" }, "f17" }, 1657 { { "fr18" }, "f18" }, 1658 { { "fr19" }, "f19" }, 1659 { { "fr20" }, "f20" }, 1660 { { "fr21" }, "f21" }, 1661 { { "fr22" }, "f22" }, 1662 { { "fr23" }, "f23" }, 1663 { { "fr24" }, "f24" }, 1664 { { "fr25" }, "f25" }, 1665 { { "fr26" }, "f26" }, 1666 { { "fr27" }, "f27" }, 1667 { { "fr28" }, "f28" }, 1668 { { "fr29" }, "f29" }, 1669 { { "fr30" }, "f30" }, 1670 { { "fr31" }, "f31" }, 1671 { { "cc" }, "cr0" }, 1672 }; 1673 1674 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1675 return llvm::makeArrayRef(GCCRegAliases); 1676 } 1677 1678 class PPC32TargetInfo : public PPCTargetInfo { 1679 public: 1680 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1681 : PPCTargetInfo(Triple, Opts) { 1682 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1683 1684 switch (getTriple().getOS()) { 1685 case llvm::Triple::Linux: 1686 case llvm::Triple::FreeBSD: 1687 case llvm::Triple::NetBSD: 1688 SizeType = UnsignedInt; 1689 PtrDiffType = SignedInt; 1690 IntPtrType = SignedInt; 1691 break; 1692 default: 1693 break; 1694 } 1695 1696 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1697 LongDoubleWidth = LongDoubleAlign = 64; 1698 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1699 } 1700 1701 // PPC32 supports atomics up to 4 bytes. 1702 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1703 } 1704 1705 BuiltinVaListKind getBuiltinVaListKind() const override { 1706 // This is the ELF definition, and is overridden by the Darwin sub-target 1707 return TargetInfo::PowerABIBuiltinVaList; 1708 } 1709 }; 1710 1711 // Note: ABI differences may eventually require us to have a separate 1712 // TargetInfo for little endian. 1713 class PPC64TargetInfo : public PPCTargetInfo { 1714 public: 1715 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1716 : PPCTargetInfo(Triple, Opts) { 1717 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1718 IntMaxType = SignedLong; 1719 Int64Type = SignedLong; 1720 1721 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1722 resetDataLayout("e-m:e-i64:64-n32:64"); 1723 ABI = "elfv2"; 1724 } else { 1725 resetDataLayout("E-m:e-i64:64-n32:64"); 1726 ABI = "elfv1"; 1727 } 1728 1729 switch (getTriple().getOS()) { 1730 case llvm::Triple::FreeBSD: 1731 LongDoubleWidth = LongDoubleAlign = 64; 1732 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1733 break; 1734 case llvm::Triple::NetBSD: 1735 IntMaxType = SignedLongLong; 1736 Int64Type = SignedLongLong; 1737 break; 1738 default: 1739 break; 1740 } 1741 1742 // PPC64 supports atomics up to 8 bytes. 1743 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1744 } 1745 BuiltinVaListKind getBuiltinVaListKind() const override { 1746 return TargetInfo::CharPtrBuiltinVaList; 1747 } 1748 // PPC64 Linux-specific ABI options. 1749 bool setABI(const std::string &Name) override { 1750 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1751 ABI = Name; 1752 return true; 1753 } 1754 return false; 1755 } 1756 }; 1757 1758 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1759 public: 1760 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1761 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1762 HasAlignMac68kSupport = true; 1763 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1764 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1765 LongLongAlign = 32; 1766 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1767 } 1768 BuiltinVaListKind getBuiltinVaListKind() const override { 1769 return TargetInfo::CharPtrBuiltinVaList; 1770 } 1771 }; 1772 1773 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1774 public: 1775 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1776 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1777 HasAlignMac68kSupport = true; 1778 resetDataLayout("E-m:o-i64:64-n32:64"); 1779 } 1780 }; 1781 1782 static const unsigned NVPTXAddrSpaceMap[] = { 1783 0, // Default 1784 1, // opencl_global 1785 3, // opencl_local 1786 4, // opencl_constant 1787 // FIXME: generic has to be added to the target 1788 0, // opencl_generic 1789 1, // cuda_device 1790 4, // cuda_constant 1791 3, // cuda_shared 1792 }; 1793 1794 class NVPTXTargetInfo : public TargetInfo { 1795 static const char *const GCCRegNames[]; 1796 static const Builtin::Info BuiltinInfo[]; 1797 CudaArch GPU; 1798 std::unique_ptr<TargetInfo> HostTarget; 1799 1800 public: 1801 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 1802 unsigned TargetPointerWidth) 1803 : TargetInfo(Triple) { 1804 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) && 1805 "NVPTX only supports 32- and 64-bit modes."); 1806 1807 TLSSupported = false; 1808 AddrSpaceMap = &NVPTXAddrSpaceMap; 1809 UseAddrSpaceMapMangling = true; 1810 1811 // Define available target features 1812 // These must be defined in sorted order! 1813 NoAsmVariants = true; 1814 GPU = CudaArch::SM_20; 1815 1816 if (TargetPointerWidth == 32) 1817 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1818 else 1819 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1820 1821 // If possible, get a TargetInfo for our host triple, so we can match its 1822 // types. 1823 llvm::Triple HostTriple(Opts.HostTriple); 1824 if (!HostTriple.isNVPTX()) 1825 HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1826 1827 // If no host target, make some guesses about the data layout and return. 1828 if (!HostTarget) { 1829 LongWidth = LongAlign = TargetPointerWidth; 1830 PointerWidth = PointerAlign = TargetPointerWidth; 1831 switch (TargetPointerWidth) { 1832 case 32: 1833 SizeType = TargetInfo::UnsignedInt; 1834 PtrDiffType = TargetInfo::SignedInt; 1835 IntPtrType = TargetInfo::SignedInt; 1836 break; 1837 case 64: 1838 SizeType = TargetInfo::UnsignedLong; 1839 PtrDiffType = TargetInfo::SignedLong; 1840 IntPtrType = TargetInfo::SignedLong; 1841 break; 1842 default: 1843 llvm_unreachable("TargetPointerWidth must be 32 or 64"); 1844 } 1845 return; 1846 } 1847 1848 // Copy properties from host target. 1849 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1850 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1851 BoolWidth = HostTarget->getBoolWidth(); 1852 BoolAlign = HostTarget->getBoolAlign(); 1853 IntWidth = HostTarget->getIntWidth(); 1854 IntAlign = HostTarget->getIntAlign(); 1855 HalfWidth = HostTarget->getHalfWidth(); 1856 HalfAlign = HostTarget->getHalfAlign(); 1857 FloatWidth = HostTarget->getFloatWidth(); 1858 FloatAlign = HostTarget->getFloatAlign(); 1859 DoubleWidth = HostTarget->getDoubleWidth(); 1860 DoubleAlign = HostTarget->getDoubleAlign(); 1861 LongWidth = HostTarget->getLongWidth(); 1862 LongAlign = HostTarget->getLongAlign(); 1863 LongLongWidth = HostTarget->getLongLongWidth(); 1864 LongLongAlign = HostTarget->getLongLongAlign(); 1865 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1866 NewAlign = HostTarget->getNewAlign(); 1867 DefaultAlignForAttributeAligned = 1868 HostTarget->getDefaultAlignForAttributeAligned(); 1869 SizeType = HostTarget->getSizeType(); 1870 IntMaxType = HostTarget->getIntMaxType(); 1871 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1872 IntPtrType = HostTarget->getIntPtrType(); 1873 WCharType = HostTarget->getWCharType(); 1874 WIntType = HostTarget->getWIntType(); 1875 Char16Type = HostTarget->getChar16Type(); 1876 Char32Type = HostTarget->getChar32Type(); 1877 Int64Type = HostTarget->getInt64Type(); 1878 SigAtomicType = HostTarget->getSigAtomicType(); 1879 ProcessIDType = HostTarget->getProcessIDType(); 1880 1881 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1882 UseZeroLengthBitfieldAlignment = 1883 HostTarget->useZeroLengthBitfieldAlignment(); 1884 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1885 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1886 1887 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and 1888 // we need those macros to be identical on host and device, because (among 1889 // other things) they affect which standard library classes are defined, and 1890 // we need all classes to be defined on both the host and device. 1891 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth(); 1892 1893 // Properties intentionally not copied from host: 1894 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1895 // host/device boundary. 1896 // - SuitableAlign: Not visible across the host/device boundary, and may 1897 // correctly be different on host/device, e.g. if host has wider vector 1898 // types than device. 1899 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1900 // as its double type, but that's not necessarily true on the host. 1901 // TODO: nvcc emits a warning when using long double on device; we should 1902 // do the same. 1903 } 1904 void getTargetDefines(const LangOptions &Opts, 1905 MacroBuilder &Builder) const override { 1906 Builder.defineMacro("__PTX__"); 1907 Builder.defineMacro("__NVPTX__"); 1908 if (Opts.CUDAIsDevice) { 1909 // Set __CUDA_ARCH__ for the GPU specified. 1910 std::string CUDAArchCode = [this] { 1911 switch (GPU) { 1912 case CudaArch::UNKNOWN: 1913 assert(false && "No GPU arch when compiling CUDA device code."); 1914 return ""; 1915 case CudaArch::SM_20: 1916 return "200"; 1917 case CudaArch::SM_21: 1918 return "210"; 1919 case CudaArch::SM_30: 1920 return "300"; 1921 case CudaArch::SM_32: 1922 return "320"; 1923 case CudaArch::SM_35: 1924 return "350"; 1925 case CudaArch::SM_37: 1926 return "370"; 1927 case CudaArch::SM_50: 1928 return "500"; 1929 case CudaArch::SM_52: 1930 return "520"; 1931 case CudaArch::SM_53: 1932 return "530"; 1933 case CudaArch::SM_60: 1934 return "600"; 1935 case CudaArch::SM_61: 1936 return "610"; 1937 case CudaArch::SM_62: 1938 return "620"; 1939 } 1940 llvm_unreachable("unhandled CudaArch"); 1941 }(); 1942 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1943 } 1944 } 1945 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1946 return llvm::makeArrayRef(BuiltinInfo, 1947 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1948 } 1949 bool 1950 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1951 StringRef CPU, 1952 const std::vector<std::string> &FeaturesVec) const override { 1953 Features["satom"] = GPU >= CudaArch::SM_60; 1954 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1955 } 1956 1957 bool hasFeature(StringRef Feature) const override { 1958 return llvm::StringSwitch<bool>(Feature) 1959 .Cases("ptx", "nvptx", true) 1960 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope. 1961 .Default(false); 1962 } 1963 1964 ArrayRef<const char *> getGCCRegNames() const override; 1965 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1966 // No aliases. 1967 return None; 1968 } 1969 bool validateAsmConstraint(const char *&Name, 1970 TargetInfo::ConstraintInfo &Info) const override { 1971 switch (*Name) { 1972 default: 1973 return false; 1974 case 'c': 1975 case 'h': 1976 case 'r': 1977 case 'l': 1978 case 'f': 1979 case 'd': 1980 Info.setAllowsRegister(); 1981 return true; 1982 } 1983 } 1984 const char *getClobbers() const override { 1985 // FIXME: Is this really right? 1986 return ""; 1987 } 1988 BuiltinVaListKind getBuiltinVaListKind() const override { 1989 // FIXME: implement 1990 return TargetInfo::CharPtrBuiltinVaList; 1991 } 1992 bool setCPU(const std::string &Name) override { 1993 GPU = StringToCudaArch(Name); 1994 return GPU != CudaArch::UNKNOWN; 1995 } 1996 void setSupportedOpenCLOpts() override { 1997 auto &Opts = getSupportedOpenCLOpts(); 1998 Opts.support("cl_clang_storage_class_specifiers"); 1999 Opts.support("cl_khr_gl_sharing"); 2000 Opts.support("cl_khr_icd"); 2001 2002 Opts.support("cl_khr_fp64"); 2003 Opts.support("cl_khr_byte_addressable_store"); 2004 Opts.support("cl_khr_global_int32_base_atomics"); 2005 Opts.support("cl_khr_global_int32_extended_atomics"); 2006 Opts.support("cl_khr_local_int32_base_atomics"); 2007 Opts.support("cl_khr_local_int32_extended_atomics"); 2008 } 2009 2010 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2011 // CUDA compilations support all of the host's calling conventions. 2012 // 2013 // TODO: We should warn if you apply a non-default CC to anything other than 2014 // a host function. 2015 if (HostTarget) 2016 return HostTarget->checkCallingConvention(CC); 2017 return CCCR_Warning; 2018 } 2019 }; 2020 2021 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 2022 #define BUILTIN(ID, TYPE, ATTRS) \ 2023 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2024 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2025 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2026 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2027 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2028 #include "clang/Basic/BuiltinsNVPTX.def" 2029 }; 2030 2031 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 2032 2033 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 2034 return llvm::makeArrayRef(GCCRegNames); 2035 } 2036 2037 static const LangAS::Map AMDGPUNonOpenCLPrivateIsZeroMap = { 2038 4, // Default 2039 1, // opencl_global 2040 3, // opencl_local 2041 2, // opencl_constant 2042 4, // opencl_generic 2043 1, // cuda_device 2044 2, // cuda_constant 2045 3 // cuda_shared 2046 }; 2047 static const LangAS::Map AMDGPUNonOpenCLGenericIsZeroMap = { 2048 0, // Default 2049 1, // opencl_global 2050 3, // opencl_local 2051 2, // opencl_constant 2052 0, // opencl_generic 2053 1, // cuda_device 2054 2, // cuda_constant 2055 3 // cuda_shared 2056 }; 2057 static const LangAS::Map AMDGPUOpenCLPrivateIsZeroMap = { 2058 0, // Default 2059 1, // opencl_global 2060 3, // opencl_local 2061 2, // opencl_constant 2062 4, // opencl_generic 2063 1, // cuda_device 2064 2, // cuda_constant 2065 3 // cuda_shared 2066 }; 2067 static const LangAS::Map AMDGPUOpenCLGenericIsZeroMap = { 2068 5, // Default 2069 1, // opencl_global 2070 3, // opencl_local 2071 2, // opencl_constant 2072 0, // opencl_generic 2073 1, // cuda_device 2074 2, // cuda_constant 2075 3 // cuda_shared 2076 }; 2077 2078 // If you edit the description strings, make sure you update 2079 // getPointerWidthV(). 2080 2081 static const char *const DataLayoutStringR600 = 2082 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2083 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2084 2085 static const char *const DataLayoutStringSIPrivateIsZero = 2086 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 2087 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2088 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2089 2090 static const char *const DataLayoutStringSIGenericIsZero = 2091 "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32" 2092 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2093 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"; 2094 2095 class AMDGPUTargetInfo final : public TargetInfo { 2096 static const Builtin::Info BuiltinInfo[]; 2097 static const char * const GCCRegNames[]; 2098 2099 struct AddrSpace { 2100 unsigned Generic, Global, Local, Constant, Private; 2101 AddrSpace(bool IsGenericZero_ = false){ 2102 if (IsGenericZero_) { 2103 Generic = 0; 2104 Global = 1; 2105 Local = 3; 2106 Constant = 2; 2107 Private = 5; 2108 } else { 2109 Generic = 4; 2110 Global = 1; 2111 Local = 3; 2112 Constant = 2; 2113 Private = 0; 2114 } 2115 } 2116 }; 2117 2118 /// \brief The GPU profiles supported by the AMDGPU target. 2119 enum GPUKind { 2120 GK_NONE, 2121 GK_R600, 2122 GK_R600_DOUBLE_OPS, 2123 GK_R700, 2124 GK_R700_DOUBLE_OPS, 2125 GK_EVERGREEN, 2126 GK_EVERGREEN_DOUBLE_OPS, 2127 GK_NORTHERN_ISLANDS, 2128 GK_CAYMAN, 2129 GK_GFX6, 2130 GK_GFX7, 2131 GK_GFX8, 2132 GK_GFX9 2133 } GPU; 2134 2135 bool hasFP64:1; 2136 bool hasFMAF:1; 2137 bool hasLDEXPF:1; 2138 const AddrSpace AS; 2139 2140 static bool hasFullSpeedFMAF32(StringRef GPUName) { 2141 return parseAMDGCNName(GPUName) >= GK_GFX9; 2142 } 2143 2144 static bool isAMDGCN(const llvm::Triple &TT) { 2145 return TT.getArch() == llvm::Triple::amdgcn; 2146 } 2147 2148 static bool isGenericZero(const llvm::Triple &TT) { 2149 return TT.getEnvironmentName() == "amdgiz" || 2150 TT.getEnvironmentName() == "amdgizcl"; 2151 } 2152 public: 2153 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 2154 : TargetInfo(Triple) , 2155 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600), 2156 hasFP64(false), 2157 hasFMAF(false), 2158 hasLDEXPF(false), 2159 AS(isGenericZero(Triple)){ 2160 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2161 hasFP64 = true; 2162 hasFMAF = true; 2163 hasLDEXPF = true; 2164 } 2165 auto IsGenericZero = isGenericZero(Triple); 2166 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 2167 (IsGenericZero ? DataLayoutStringSIGenericIsZero : 2168 DataLayoutStringSIPrivateIsZero) 2169 : DataLayoutStringR600); 2170 assert(DataLayout->getAllocaAddrSpace() == AS.Private); 2171 2172 UseAddrSpaceMapMangling = true; 2173 } 2174 2175 void adjust(LangOptions &Opts) override { 2176 TargetInfo::adjust(Opts); 2177 if (isGenericZero(getTriple())) { 2178 AddrSpaceMap = Opts.OpenCL ? &AMDGPUOpenCLGenericIsZeroMap 2179 : &AMDGPUNonOpenCLGenericIsZeroMap; 2180 } else { 2181 AddrSpaceMap = Opts.OpenCL ? &AMDGPUOpenCLPrivateIsZeroMap 2182 : &AMDGPUNonOpenCLPrivateIsZeroMap; 2183 } 2184 } 2185 2186 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 2187 if (GPU <= GK_CAYMAN) 2188 return 32; 2189 2190 if (AddrSpace == AS.Private || AddrSpace == AS.Local) { 2191 return 32; 2192 } 2193 return 64; 2194 } 2195 2196 uint64_t getMaxPointerWidth() const override { 2197 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2198 } 2199 2200 const char * getClobbers() const override { 2201 return ""; 2202 } 2203 2204 ArrayRef<const char *> getGCCRegNames() const override; 2205 2206 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2207 return None; 2208 } 2209 2210 bool validateAsmConstraint(const char *&Name, 2211 TargetInfo::ConstraintInfo &Info) const override { 2212 switch (*Name) { 2213 default: break; 2214 case 'v': // vgpr 2215 case 's': // sgpr 2216 Info.setAllowsRegister(); 2217 return true; 2218 } 2219 return false; 2220 } 2221 2222 bool initFeatureMap(llvm::StringMap<bool> &Features, 2223 DiagnosticsEngine &Diags, StringRef CPU, 2224 const std::vector<std::string> &FeatureVec) const override; 2225 2226 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2227 TargetOptions &TargetOpts) const override { 2228 bool hasFP32Denormals = false; 2229 bool hasFP64Denormals = false; 2230 for (auto &I : TargetOpts.FeaturesAsWritten) { 2231 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2232 hasFP32Denormals = true; 2233 if (I == "+fp64-fp16-denormals" || I == "-fp64-fp16-denormals") 2234 hasFP64Denormals = true; 2235 } 2236 if (!hasFP32Denormals) 2237 TargetOpts.Features.push_back( 2238 (Twine(hasFullSpeedFMAF32(TargetOpts.CPU) && 2239 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str()); 2240 // Always do not flush fp64 or fp16 denorms. 2241 if (!hasFP64Denormals && hasFP64) 2242 TargetOpts.Features.push_back("+fp64-fp16-denormals"); 2243 } 2244 2245 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2246 return llvm::makeArrayRef(BuiltinInfo, 2247 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2248 } 2249 2250 void getTargetDefines(const LangOptions &Opts, 2251 MacroBuilder &Builder) const override { 2252 if (getTriple().getArch() == llvm::Triple::amdgcn) 2253 Builder.defineMacro("__AMDGCN__"); 2254 else 2255 Builder.defineMacro("__R600__"); 2256 2257 if (hasFMAF) 2258 Builder.defineMacro("__HAS_FMAF__"); 2259 if (hasLDEXPF) 2260 Builder.defineMacro("__HAS_LDEXPF__"); 2261 if (hasFP64) 2262 Builder.defineMacro("__HAS_FP64__"); 2263 } 2264 2265 BuiltinVaListKind getBuiltinVaListKind() const override { 2266 return TargetInfo::CharPtrBuiltinVaList; 2267 } 2268 2269 static GPUKind parseR600Name(StringRef Name) { 2270 return llvm::StringSwitch<GPUKind>(Name) 2271 .Case("r600" , GK_R600) 2272 .Case("rv610", GK_R600) 2273 .Case("rv620", GK_R600) 2274 .Case("rv630", GK_R600) 2275 .Case("rv635", GK_R600) 2276 .Case("rs780", GK_R600) 2277 .Case("rs880", GK_R600) 2278 .Case("rv670", GK_R600_DOUBLE_OPS) 2279 .Case("rv710", GK_R700) 2280 .Case("rv730", GK_R700) 2281 .Case("rv740", GK_R700_DOUBLE_OPS) 2282 .Case("rv770", GK_R700_DOUBLE_OPS) 2283 .Case("palm", GK_EVERGREEN) 2284 .Case("cedar", GK_EVERGREEN) 2285 .Case("sumo", GK_EVERGREEN) 2286 .Case("sumo2", GK_EVERGREEN) 2287 .Case("redwood", GK_EVERGREEN) 2288 .Case("juniper", GK_EVERGREEN) 2289 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2290 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2291 .Case("barts", GK_NORTHERN_ISLANDS) 2292 .Case("turks", GK_NORTHERN_ISLANDS) 2293 .Case("caicos", GK_NORTHERN_ISLANDS) 2294 .Case("cayman", GK_CAYMAN) 2295 .Case("aruba", GK_CAYMAN) 2296 .Default(GK_NONE); 2297 } 2298 2299 static GPUKind parseAMDGCNName(StringRef Name) { 2300 return llvm::StringSwitch<GPUKind>(Name) 2301 .Case("tahiti", GK_GFX6) 2302 .Case("pitcairn", GK_GFX6) 2303 .Case("verde", GK_GFX6) 2304 .Case("oland", GK_GFX6) 2305 .Case("hainan", GK_GFX6) 2306 .Case("bonaire", GK_GFX7) 2307 .Case("kabini", GK_GFX7) 2308 .Case("kaveri", GK_GFX7) 2309 .Case("hawaii", GK_GFX7) 2310 .Case("mullins", GK_GFX7) 2311 .Case("gfx700", GK_GFX7) 2312 .Case("gfx701", GK_GFX7) 2313 .Case("gfx702", GK_GFX7) 2314 .Case("tonga", GK_GFX8) 2315 .Case("iceland", GK_GFX8) 2316 .Case("carrizo", GK_GFX8) 2317 .Case("fiji", GK_GFX8) 2318 .Case("stoney", GK_GFX8) 2319 .Case("polaris10", GK_GFX8) 2320 .Case("polaris11", GK_GFX8) 2321 .Case("gfx800", GK_GFX8) 2322 .Case("gfx801", GK_GFX8) 2323 .Case("gfx802", GK_GFX8) 2324 .Case("gfx803", GK_GFX8) 2325 .Case("gfx804", GK_GFX8) 2326 .Case("gfx810", GK_GFX8) 2327 .Case("gfx900", GK_GFX9) 2328 .Case("gfx901", GK_GFX9) 2329 .Default(GK_NONE); 2330 } 2331 2332 bool setCPU(const std::string &Name) override { 2333 if (getTriple().getArch() == llvm::Triple::amdgcn) 2334 GPU = parseAMDGCNName(Name); 2335 else 2336 GPU = parseR600Name(Name); 2337 2338 return GPU != GK_NONE; 2339 } 2340 2341 void setSupportedOpenCLOpts() override { 2342 auto &Opts = getSupportedOpenCLOpts(); 2343 Opts.support("cl_clang_storage_class_specifiers"); 2344 Opts.support("cl_khr_icd"); 2345 2346 if (hasFP64) 2347 Opts.support("cl_khr_fp64"); 2348 if (GPU >= GK_EVERGREEN) { 2349 Opts.support("cl_khr_byte_addressable_store"); 2350 Opts.support("cl_khr_global_int32_base_atomics"); 2351 Opts.support("cl_khr_global_int32_extended_atomics"); 2352 Opts.support("cl_khr_local_int32_base_atomics"); 2353 Opts.support("cl_khr_local_int32_extended_atomics"); 2354 } 2355 if (GPU >= GK_GFX6) { 2356 Opts.support("cl_khr_fp16"); 2357 Opts.support("cl_khr_int64_base_atomics"); 2358 Opts.support("cl_khr_int64_extended_atomics"); 2359 Opts.support("cl_khr_mipmap_image"); 2360 Opts.support("cl_khr_subgroups"); 2361 Opts.support("cl_khr_3d_image_writes"); 2362 Opts.support("cl_amd_media_ops"); 2363 Opts.support("cl_amd_media_ops2"); 2364 } 2365 } 2366 2367 LangAS::ID getOpenCLImageAddrSpace() const override { 2368 return LangAS::opencl_constant; 2369 } 2370 2371 /// \returns Target specific vtbl ptr address space. 2372 unsigned getVtblPtrAddressSpace() const override { 2373 // \todo: We currently have address spaces defined in AMDGPU Backend. It 2374 // would be nice if we could use it here instead of using bare numbers (same 2375 // applies to getDWARFAddressSpace). 2376 return 2; // constant. 2377 } 2378 2379 /// \returns If a target requires an address within a target specific address 2380 /// space \p AddressSpace to be converted in order to be used, then return the 2381 /// corresponding target specific DWARF address space. 2382 /// 2383 /// \returns Otherwise return None and no conversion will be emitted in the 2384 /// DWARF. 2385 Optional<unsigned> getDWARFAddressSpace( 2386 unsigned AddressSpace) const override { 2387 const unsigned DWARF_Private = 1; 2388 const unsigned DWARF_Local = 2; 2389 if (AddressSpace == AS.Private) { 2390 return DWARF_Private; 2391 } else if (AddressSpace == AS.Local) { 2392 return DWARF_Local; 2393 } else { 2394 return None; 2395 } 2396 } 2397 2398 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2399 switch (CC) { 2400 default: 2401 return CCCR_Warning; 2402 case CC_C: 2403 case CC_OpenCLKernel: 2404 return CCCR_OK; 2405 } 2406 } 2407 2408 // In amdgcn target the null pointer in global, constant, and generic 2409 // address space has value 0 but in private and local address space has 2410 // value ~0. 2411 uint64_t getNullPointerValue(unsigned AS) const override { 2412 return AS == LangAS::opencl_local ? ~0 : 0; 2413 } 2414 }; 2415 2416 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2417 #define BUILTIN(ID, TYPE, ATTRS) \ 2418 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2419 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2420 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2421 #include "clang/Basic/BuiltinsAMDGPU.def" 2422 }; 2423 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2424 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2425 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2426 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2427 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2428 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2429 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2430 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2431 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2432 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2433 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2434 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2435 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2436 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2437 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2438 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2439 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2440 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2441 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2442 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2443 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2444 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2445 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2446 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2447 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2448 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2449 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2450 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2451 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2452 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2453 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2454 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2455 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2456 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2457 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2458 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2459 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2460 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2461 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2462 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2463 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2464 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2465 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2466 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2467 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2468 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2469 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2470 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2471 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2472 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2473 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2474 }; 2475 2476 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2477 return llvm::makeArrayRef(GCCRegNames); 2478 } 2479 2480 bool AMDGPUTargetInfo::initFeatureMap( 2481 llvm::StringMap<bool> &Features, 2482 DiagnosticsEngine &Diags, StringRef CPU, 2483 const std::vector<std::string> &FeatureVec) const { 2484 2485 // XXX - What does the member GPU mean if device name string passed here? 2486 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2487 if (CPU.empty()) 2488 CPU = "tahiti"; 2489 2490 switch (parseAMDGCNName(CPU)) { 2491 case GK_GFX6: 2492 case GK_GFX7: 2493 break; 2494 2495 case GK_GFX9: 2496 Features["gfx9-insts"] = true; 2497 LLVM_FALLTHROUGH; 2498 case GK_GFX8: 2499 Features["s-memrealtime"] = true; 2500 Features["16-bit-insts"] = true; 2501 Features["dpp"] = true; 2502 break; 2503 2504 case GK_NONE: 2505 return false; 2506 default: 2507 llvm_unreachable("unhandled subtarget"); 2508 } 2509 } else { 2510 if (CPU.empty()) 2511 CPU = "r600"; 2512 2513 switch (parseR600Name(CPU)) { 2514 case GK_R600: 2515 case GK_R700: 2516 case GK_EVERGREEN: 2517 case GK_NORTHERN_ISLANDS: 2518 break; 2519 case GK_R600_DOUBLE_OPS: 2520 case GK_R700_DOUBLE_OPS: 2521 case GK_EVERGREEN_DOUBLE_OPS: 2522 case GK_CAYMAN: 2523 Features["fp64"] = true; 2524 break; 2525 case GK_NONE: 2526 return false; 2527 default: 2528 llvm_unreachable("unhandled subtarget"); 2529 } 2530 } 2531 2532 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2533 } 2534 2535 const Builtin::Info BuiltinInfoX86[] = { 2536 #define BUILTIN(ID, TYPE, ATTRS) \ 2537 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2538 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2539 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2540 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2541 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2542 #include "clang/Basic/BuiltinsX86.def" 2543 2544 #define BUILTIN(ID, TYPE, ATTRS) \ 2545 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2546 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2547 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2548 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2549 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2550 #include "clang/Basic/BuiltinsX86_64.def" 2551 }; 2552 2553 2554 static const char* const GCCRegNames[] = { 2555 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2556 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2557 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2558 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2559 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2560 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2561 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2562 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2563 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2564 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2565 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2566 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2567 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2568 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2569 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2570 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2571 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2572 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", 2573 }; 2574 2575 const TargetInfo::AddlRegName AddlRegNames[] = { 2576 { { "al", "ah", "eax", "rax" }, 0 }, 2577 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2578 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2579 { { "dl", "dh", "edx", "rdx" }, 1 }, 2580 { { "esi", "rsi" }, 4 }, 2581 { { "edi", "rdi" }, 5 }, 2582 { { "esp", "rsp" }, 7 }, 2583 { { "ebp", "rbp" }, 6 }, 2584 { { "r8d", "r8w", "r8b" }, 38 }, 2585 { { "r9d", "r9w", "r9b" }, 39 }, 2586 { { "r10d", "r10w", "r10b" }, 40 }, 2587 { { "r11d", "r11w", "r11b" }, 41 }, 2588 { { "r12d", "r12w", "r12b" }, 42 }, 2589 { { "r13d", "r13w", "r13b" }, 43 }, 2590 { { "r14d", "r14w", "r14b" }, 44 }, 2591 { { "r15d", "r15w", "r15b" }, 45 }, 2592 }; 2593 2594 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2595 // most of the implementation can be shared. 2596 class X86TargetInfo : public TargetInfo { 2597 enum X86SSEEnum { 2598 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2599 } SSELevel = NoSSE; 2600 enum MMX3DNowEnum { 2601 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2602 } MMX3DNowLevel = NoMMX3DNow; 2603 enum XOPEnum { 2604 NoXOP, 2605 SSE4A, 2606 FMA4, 2607 XOP 2608 } XOPLevel = NoXOP; 2609 2610 bool HasAES = false; 2611 bool HasPCLMUL = false; 2612 bool HasLZCNT = false; 2613 bool HasRDRND = false; 2614 bool HasFSGSBASE = false; 2615 bool HasBMI = false; 2616 bool HasBMI2 = false; 2617 bool HasPOPCNT = false; 2618 bool HasRTM = false; 2619 bool HasPRFCHW = false; 2620 bool HasRDSEED = false; 2621 bool HasADX = false; 2622 bool HasTBM = false; 2623 bool HasLWP = false; 2624 bool HasFMA = false; 2625 bool HasF16C = false; 2626 bool HasAVX512CD = false; 2627 bool HasAVX512ER = false; 2628 bool HasAVX512PF = false; 2629 bool HasAVX512DQ = false; 2630 bool HasAVX512BW = false; 2631 bool HasAVX512VL = false; 2632 bool HasAVX512VBMI = false; 2633 bool HasAVX512IFMA = false; 2634 bool HasSHA = false; 2635 bool HasMPX = false; 2636 bool HasSGX = false; 2637 bool HasCX16 = false; 2638 bool HasFXSR = false; 2639 bool HasXSAVE = false; 2640 bool HasXSAVEOPT = false; 2641 bool HasXSAVEC = false; 2642 bool HasXSAVES = false; 2643 bool HasMWAITX = false; 2644 bool HasCLZERO = false; 2645 bool HasPKU = false; 2646 bool HasCLFLUSHOPT = false; 2647 bool HasCLWB = false; 2648 bool HasMOVBE = false; 2649 bool HasPREFETCHWT1 = false; 2650 2651 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2652 /// 2653 /// Each enumeration represents a particular CPU supported by Clang. These 2654 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2655 enum CPUKind { 2656 CK_Generic, 2657 2658 /// \name i386 2659 /// i386-generation processors. 2660 //@{ 2661 CK_i386, 2662 //@} 2663 2664 /// \name i486 2665 /// i486-generation processors. 2666 //@{ 2667 CK_i486, 2668 CK_WinChipC6, 2669 CK_WinChip2, 2670 CK_C3, 2671 //@} 2672 2673 /// \name i586 2674 /// i586-generation processors, P5 microarchitecture based. 2675 //@{ 2676 CK_i586, 2677 CK_Pentium, 2678 CK_PentiumMMX, 2679 //@} 2680 2681 /// \name i686 2682 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2683 //@{ 2684 CK_i686, 2685 CK_PentiumPro, 2686 CK_Pentium2, 2687 CK_Pentium3, 2688 CK_Pentium3M, 2689 CK_PentiumM, 2690 CK_C3_2, 2691 2692 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2693 /// Clang however has some logic to suport this. 2694 // FIXME: Warn, deprecate, and potentially remove this. 2695 CK_Yonah, 2696 //@} 2697 2698 /// \name Netburst 2699 /// Netburst microarchitecture based processors. 2700 //@{ 2701 CK_Pentium4, 2702 CK_Pentium4M, 2703 CK_Prescott, 2704 CK_Nocona, 2705 //@} 2706 2707 /// \name Core 2708 /// Core microarchitecture based processors. 2709 //@{ 2710 CK_Core2, 2711 2712 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2713 /// codename which GCC no longer accepts as an option to -march, but Clang 2714 /// has some logic for recognizing it. 2715 // FIXME: Warn, deprecate, and potentially remove this. 2716 CK_Penryn, 2717 //@} 2718 2719 /// \name Atom 2720 /// Atom processors 2721 //@{ 2722 CK_Bonnell, 2723 CK_Silvermont, 2724 //@} 2725 2726 /// \name Nehalem 2727 /// Nehalem microarchitecture based processors. 2728 CK_Nehalem, 2729 2730 /// \name Westmere 2731 /// Westmere microarchitecture based processors. 2732 CK_Westmere, 2733 2734 /// \name Sandy Bridge 2735 /// Sandy Bridge microarchitecture based processors. 2736 CK_SandyBridge, 2737 2738 /// \name Ivy Bridge 2739 /// Ivy Bridge microarchitecture based processors. 2740 CK_IvyBridge, 2741 2742 /// \name Haswell 2743 /// Haswell microarchitecture based processors. 2744 CK_Haswell, 2745 2746 /// \name Broadwell 2747 /// Broadwell microarchitecture based processors. 2748 CK_Broadwell, 2749 2750 /// \name Skylake Client 2751 /// Skylake client microarchitecture based processors. 2752 CK_SkylakeClient, 2753 2754 /// \name Skylake Server 2755 /// Skylake server microarchitecture based processors. 2756 CK_SkylakeServer, 2757 2758 /// \name Cannonlake Client 2759 /// Cannonlake client microarchitecture based processors. 2760 CK_Cannonlake, 2761 2762 /// \name Knights Landing 2763 /// Knights Landing processor. 2764 CK_KNL, 2765 2766 /// \name Lakemont 2767 /// Lakemont microarchitecture based processors. 2768 CK_Lakemont, 2769 2770 /// \name K6 2771 /// K6 architecture processors. 2772 //@{ 2773 CK_K6, 2774 CK_K6_2, 2775 CK_K6_3, 2776 //@} 2777 2778 /// \name K7 2779 /// K7 architecture processors. 2780 //@{ 2781 CK_Athlon, 2782 CK_AthlonThunderbird, 2783 CK_Athlon4, 2784 CK_AthlonXP, 2785 CK_AthlonMP, 2786 //@} 2787 2788 /// \name K8 2789 /// K8 architecture processors. 2790 //@{ 2791 CK_Athlon64, 2792 CK_Athlon64SSE3, 2793 CK_AthlonFX, 2794 CK_K8, 2795 CK_K8SSE3, 2796 CK_Opteron, 2797 CK_OpteronSSE3, 2798 CK_AMDFAM10, 2799 //@} 2800 2801 /// \name Bobcat 2802 /// Bobcat architecture processors. 2803 //@{ 2804 CK_BTVER1, 2805 CK_BTVER2, 2806 //@} 2807 2808 /// \name Bulldozer 2809 /// Bulldozer architecture processors. 2810 //@{ 2811 CK_BDVER1, 2812 CK_BDVER2, 2813 CK_BDVER3, 2814 CK_BDVER4, 2815 //@} 2816 2817 /// \name zen 2818 /// Zen architecture processors. 2819 //@{ 2820 CK_ZNVER1, 2821 //@} 2822 2823 /// This specification is deprecated and will be removed in the future. 2824 /// Users should prefer \see CK_K8. 2825 // FIXME: Warn on this when the CPU is set to it. 2826 //@{ 2827 CK_x86_64, 2828 //@} 2829 2830 /// \name Geode 2831 /// Geode processors. 2832 //@{ 2833 CK_Geode 2834 //@} 2835 } CPU = CK_Generic; 2836 2837 CPUKind getCPUKind(StringRef CPU) const { 2838 return llvm::StringSwitch<CPUKind>(CPU) 2839 .Case("i386", CK_i386) 2840 .Case("i486", CK_i486) 2841 .Case("winchip-c6", CK_WinChipC6) 2842 .Case("winchip2", CK_WinChip2) 2843 .Case("c3", CK_C3) 2844 .Case("i586", CK_i586) 2845 .Case("pentium", CK_Pentium) 2846 .Case("pentium-mmx", CK_PentiumMMX) 2847 .Case("i686", CK_i686) 2848 .Case("pentiumpro", CK_PentiumPro) 2849 .Case("pentium2", CK_Pentium2) 2850 .Case("pentium3", CK_Pentium3) 2851 .Case("pentium3m", CK_Pentium3M) 2852 .Case("pentium-m", CK_PentiumM) 2853 .Case("c3-2", CK_C3_2) 2854 .Case("yonah", CK_Yonah) 2855 .Case("pentium4", CK_Pentium4) 2856 .Case("pentium4m", CK_Pentium4M) 2857 .Case("prescott", CK_Prescott) 2858 .Case("nocona", CK_Nocona) 2859 .Case("core2", CK_Core2) 2860 .Case("penryn", CK_Penryn) 2861 .Case("bonnell", CK_Bonnell) 2862 .Case("atom", CK_Bonnell) // Legacy name. 2863 .Case("silvermont", CK_Silvermont) 2864 .Case("slm", CK_Silvermont) // Legacy name. 2865 .Case("nehalem", CK_Nehalem) 2866 .Case("corei7", CK_Nehalem) // Legacy name. 2867 .Case("westmere", CK_Westmere) 2868 .Case("sandybridge", CK_SandyBridge) 2869 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2870 .Case("ivybridge", CK_IvyBridge) 2871 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2872 .Case("haswell", CK_Haswell) 2873 .Case("core-avx2", CK_Haswell) // Legacy name. 2874 .Case("broadwell", CK_Broadwell) 2875 .Case("skylake", CK_SkylakeClient) 2876 .Case("skylake-avx512", CK_SkylakeServer) 2877 .Case("skx", CK_SkylakeServer) // Legacy name. 2878 .Case("cannonlake", CK_Cannonlake) 2879 .Case("knl", CK_KNL) 2880 .Case("lakemont", CK_Lakemont) 2881 .Case("k6", CK_K6) 2882 .Case("k6-2", CK_K6_2) 2883 .Case("k6-3", CK_K6_3) 2884 .Case("athlon", CK_Athlon) 2885 .Case("athlon-tbird", CK_AthlonThunderbird) 2886 .Case("athlon-4", CK_Athlon4) 2887 .Case("athlon-xp", CK_AthlonXP) 2888 .Case("athlon-mp", CK_AthlonMP) 2889 .Case("athlon64", CK_Athlon64) 2890 .Case("athlon64-sse3", CK_Athlon64SSE3) 2891 .Case("athlon-fx", CK_AthlonFX) 2892 .Case("k8", CK_K8) 2893 .Case("k8-sse3", CK_K8SSE3) 2894 .Case("opteron", CK_Opteron) 2895 .Case("opteron-sse3", CK_OpteronSSE3) 2896 .Case("barcelona", CK_AMDFAM10) 2897 .Case("amdfam10", CK_AMDFAM10) 2898 .Case("btver1", CK_BTVER1) 2899 .Case("btver2", CK_BTVER2) 2900 .Case("bdver1", CK_BDVER1) 2901 .Case("bdver2", CK_BDVER2) 2902 .Case("bdver3", CK_BDVER3) 2903 .Case("bdver4", CK_BDVER4) 2904 .Case("znver1", CK_ZNVER1) 2905 .Case("x86-64", CK_x86_64) 2906 .Case("geode", CK_Geode) 2907 .Default(CK_Generic); 2908 } 2909 2910 enum FPMathKind { 2911 FP_Default, 2912 FP_SSE, 2913 FP_387 2914 } FPMath = FP_Default; 2915 2916 public: 2917 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2918 : TargetInfo(Triple) { 2919 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 2920 } 2921 unsigned getFloatEvalMethod() const override { 2922 // X87 evaluates with 80 bits "long double" precision. 2923 return SSELevel == NoSSE ? 2 : 0; 2924 } 2925 ArrayRef<const char *> getGCCRegNames() const override { 2926 return llvm::makeArrayRef(GCCRegNames); 2927 } 2928 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2929 return None; 2930 } 2931 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2932 return llvm::makeArrayRef(AddlRegNames); 2933 } 2934 bool validateCpuSupports(StringRef Name) const override; 2935 bool validateAsmConstraint(const char *&Name, 2936 TargetInfo::ConstraintInfo &info) const override; 2937 2938 bool validateGlobalRegisterVariable(StringRef RegName, 2939 unsigned RegSize, 2940 bool &HasSizeMismatch) const override { 2941 // esp and ebp are the only 32-bit registers the x86 backend can currently 2942 // handle. 2943 if (RegName.equals("esp") || RegName.equals("ebp")) { 2944 // Check that the register size is 32-bit. 2945 HasSizeMismatch = RegSize != 32; 2946 return true; 2947 } 2948 2949 return false; 2950 } 2951 2952 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2953 2954 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2955 2956 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2957 2958 std::string convertConstraint(const char *&Constraint) const override; 2959 const char *getClobbers() const override { 2960 return "~{dirflag},~{fpsr},~{flags}"; 2961 } 2962 2963 StringRef getConstraintRegister(const StringRef &Constraint, 2964 const StringRef &Expression) const override { 2965 StringRef::iterator I, E; 2966 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) { 2967 if (isalpha(*I)) 2968 break; 2969 } 2970 if (I == E) 2971 return ""; 2972 switch (*I) { 2973 // For the register constraints, return the matching register name 2974 case 'a': 2975 return "ax"; 2976 case 'b': 2977 return "bx"; 2978 case 'c': 2979 return "cx"; 2980 case 'd': 2981 return "dx"; 2982 case 'S': 2983 return "si"; 2984 case 'D': 2985 return "di"; 2986 // In case the constraint is 'r' we need to return Expression 2987 case 'r': 2988 return Expression; 2989 default: 2990 // Default value if there is no constraint for the register 2991 return ""; 2992 } 2993 return ""; 2994 } 2995 2996 void getTargetDefines(const LangOptions &Opts, 2997 MacroBuilder &Builder) const override; 2998 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2999 bool Enabled); 3000 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 3001 bool Enabled); 3002 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3003 bool Enabled); 3004 void setFeatureEnabled(llvm::StringMap<bool> &Features, 3005 StringRef Name, bool Enabled) const override { 3006 setFeatureEnabledImpl(Features, Name, Enabled); 3007 } 3008 // This exists purely to cut down on the number of virtual calls in 3009 // initFeatureMap which calls this repeatedly. 3010 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3011 StringRef Name, bool Enabled); 3012 bool 3013 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 3014 StringRef CPU, 3015 const std::vector<std::string> &FeaturesVec) const override; 3016 bool hasFeature(StringRef Feature) const override; 3017 bool handleTargetFeatures(std::vector<std::string> &Features, 3018 DiagnosticsEngine &Diags) override; 3019 StringRef getABI() const override { 3020 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 3021 return "avx512"; 3022 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 3023 return "avx"; 3024 if (getTriple().getArch() == llvm::Triple::x86 && 3025 MMX3DNowLevel == NoMMX3DNow) 3026 return "no-mmx"; 3027 return ""; 3028 } 3029 bool setCPU(const std::string &Name) override { 3030 CPU = getCPUKind(Name); 3031 3032 // Perform any per-CPU checks necessary to determine if this CPU is 3033 // acceptable. 3034 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 3035 // invalid without explaining *why*. 3036 switch (CPU) { 3037 case CK_Generic: 3038 // No processor selected! 3039 return false; 3040 3041 case CK_i386: 3042 case CK_i486: 3043 case CK_WinChipC6: 3044 case CK_WinChip2: 3045 case CK_C3: 3046 case CK_i586: 3047 case CK_Pentium: 3048 case CK_PentiumMMX: 3049 case CK_i686: 3050 case CK_PentiumPro: 3051 case CK_Pentium2: 3052 case CK_Pentium3: 3053 case CK_Pentium3M: 3054 case CK_PentiumM: 3055 case CK_Yonah: 3056 case CK_C3_2: 3057 case CK_Pentium4: 3058 case CK_Pentium4M: 3059 case CK_Lakemont: 3060 case CK_Prescott: 3061 case CK_K6: 3062 case CK_K6_2: 3063 case CK_K6_3: 3064 case CK_Athlon: 3065 case CK_AthlonThunderbird: 3066 case CK_Athlon4: 3067 case CK_AthlonXP: 3068 case CK_AthlonMP: 3069 case CK_Geode: 3070 // Only accept certain architectures when compiling in 32-bit mode. 3071 if (getTriple().getArch() != llvm::Triple::x86) 3072 return false; 3073 3074 // Fallthrough 3075 case CK_Nocona: 3076 case CK_Core2: 3077 case CK_Penryn: 3078 case CK_Bonnell: 3079 case CK_Silvermont: 3080 case CK_Nehalem: 3081 case CK_Westmere: 3082 case CK_SandyBridge: 3083 case CK_IvyBridge: 3084 case CK_Haswell: 3085 case CK_Broadwell: 3086 case CK_SkylakeClient: 3087 case CK_SkylakeServer: 3088 case CK_Cannonlake: 3089 case CK_KNL: 3090 case CK_Athlon64: 3091 case CK_Athlon64SSE3: 3092 case CK_AthlonFX: 3093 case CK_K8: 3094 case CK_K8SSE3: 3095 case CK_Opteron: 3096 case CK_OpteronSSE3: 3097 case CK_AMDFAM10: 3098 case CK_BTVER1: 3099 case CK_BTVER2: 3100 case CK_BDVER1: 3101 case CK_BDVER2: 3102 case CK_BDVER3: 3103 case CK_BDVER4: 3104 case CK_ZNVER1: 3105 case CK_x86_64: 3106 return true; 3107 } 3108 llvm_unreachable("Unhandled CPU kind"); 3109 } 3110 3111 bool setFPMath(StringRef Name) override; 3112 3113 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3114 // Most of the non-ARM calling conventions are i386 conventions. 3115 switch (CC) { 3116 case CC_X86ThisCall: 3117 case CC_X86FastCall: 3118 case CC_X86StdCall: 3119 case CC_X86VectorCall: 3120 case CC_X86RegCall: 3121 case CC_C: 3122 case CC_Swift: 3123 case CC_X86Pascal: 3124 case CC_IntelOclBicc: 3125 return CCCR_OK; 3126 default: 3127 return CCCR_Warning; 3128 } 3129 } 3130 3131 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3132 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 3133 } 3134 3135 bool hasSjLjLowering() const override { 3136 return true; 3137 } 3138 3139 void setSupportedOpenCLOpts() override { 3140 getSupportedOpenCLOpts().supportAll(); 3141 } 3142 }; 3143 3144 bool X86TargetInfo::setFPMath(StringRef Name) { 3145 if (Name == "387") { 3146 FPMath = FP_387; 3147 return true; 3148 } 3149 if (Name == "sse") { 3150 FPMath = FP_SSE; 3151 return true; 3152 } 3153 return false; 3154 } 3155 3156 bool X86TargetInfo::initFeatureMap( 3157 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 3158 const std::vector<std::string> &FeaturesVec) const { 3159 // FIXME: This *really* should not be here. 3160 // X86_64 always has SSE2. 3161 if (getTriple().getArch() == llvm::Triple::x86_64) 3162 setFeatureEnabledImpl(Features, "sse2", true); 3163 3164 const CPUKind Kind = getCPUKind(CPU); 3165 3166 // Enable X87 for all X86 processors but Lakemont. 3167 if (Kind != CK_Lakemont) 3168 setFeatureEnabledImpl(Features, "x87", true); 3169 3170 switch (Kind) { 3171 case CK_Generic: 3172 case CK_i386: 3173 case CK_i486: 3174 case CK_i586: 3175 case CK_Pentium: 3176 case CK_i686: 3177 case CK_PentiumPro: 3178 case CK_Lakemont: 3179 break; 3180 case CK_PentiumMMX: 3181 case CK_Pentium2: 3182 case CK_K6: 3183 case CK_WinChipC6: 3184 setFeatureEnabledImpl(Features, "mmx", true); 3185 break; 3186 case CK_Pentium3: 3187 case CK_Pentium3M: 3188 case CK_C3_2: 3189 setFeatureEnabledImpl(Features, "sse", true); 3190 setFeatureEnabledImpl(Features, "fxsr", true); 3191 break; 3192 case CK_PentiumM: 3193 case CK_Pentium4: 3194 case CK_Pentium4M: 3195 case CK_x86_64: 3196 setFeatureEnabledImpl(Features, "sse2", true); 3197 setFeatureEnabledImpl(Features, "fxsr", true); 3198 break; 3199 case CK_Yonah: 3200 case CK_Prescott: 3201 case CK_Nocona: 3202 setFeatureEnabledImpl(Features, "sse3", true); 3203 setFeatureEnabledImpl(Features, "fxsr", true); 3204 setFeatureEnabledImpl(Features, "cx16", true); 3205 break; 3206 case CK_Core2: 3207 case CK_Bonnell: 3208 setFeatureEnabledImpl(Features, "ssse3", true); 3209 setFeatureEnabledImpl(Features, "fxsr", true); 3210 setFeatureEnabledImpl(Features, "cx16", true); 3211 break; 3212 case CK_Penryn: 3213 setFeatureEnabledImpl(Features, "sse4.1", true); 3214 setFeatureEnabledImpl(Features, "fxsr", true); 3215 setFeatureEnabledImpl(Features, "cx16", true); 3216 break; 3217 case CK_Cannonlake: 3218 setFeatureEnabledImpl(Features, "avx512ifma", true); 3219 setFeatureEnabledImpl(Features, "avx512vbmi", true); 3220 setFeatureEnabledImpl(Features, "sha", true); 3221 LLVM_FALLTHROUGH; 3222 case CK_SkylakeServer: 3223 setFeatureEnabledImpl(Features, "avx512f", true); 3224 setFeatureEnabledImpl(Features, "avx512cd", true); 3225 setFeatureEnabledImpl(Features, "avx512dq", true); 3226 setFeatureEnabledImpl(Features, "avx512bw", true); 3227 setFeatureEnabledImpl(Features, "avx512vl", true); 3228 setFeatureEnabledImpl(Features, "pku", true); 3229 setFeatureEnabledImpl(Features, "clwb", true); 3230 LLVM_FALLTHROUGH; 3231 case CK_SkylakeClient: 3232 setFeatureEnabledImpl(Features, "xsavec", true); 3233 setFeatureEnabledImpl(Features, "xsaves", true); 3234 setFeatureEnabledImpl(Features, "mpx", true); 3235 setFeatureEnabledImpl(Features, "sgx", true); 3236 setFeatureEnabledImpl(Features, "clflushopt", true); 3237 setFeatureEnabledImpl(Features, "rtm", true); 3238 LLVM_FALLTHROUGH; 3239 case CK_Broadwell: 3240 setFeatureEnabledImpl(Features, "rdseed", true); 3241 setFeatureEnabledImpl(Features, "adx", true); 3242 LLVM_FALLTHROUGH; 3243 case CK_Haswell: 3244 setFeatureEnabledImpl(Features, "avx2", true); 3245 setFeatureEnabledImpl(Features, "lzcnt", true); 3246 setFeatureEnabledImpl(Features, "bmi", true); 3247 setFeatureEnabledImpl(Features, "bmi2", true); 3248 setFeatureEnabledImpl(Features, "fma", true); 3249 setFeatureEnabledImpl(Features, "movbe", true); 3250 LLVM_FALLTHROUGH; 3251 case CK_IvyBridge: 3252 setFeatureEnabledImpl(Features, "rdrnd", true); 3253 setFeatureEnabledImpl(Features, "f16c", true); 3254 setFeatureEnabledImpl(Features, "fsgsbase", true); 3255 LLVM_FALLTHROUGH; 3256 case CK_SandyBridge: 3257 setFeatureEnabledImpl(Features, "avx", true); 3258 setFeatureEnabledImpl(Features, "xsave", true); 3259 setFeatureEnabledImpl(Features, "xsaveopt", true); 3260 LLVM_FALLTHROUGH; 3261 case CK_Westmere: 3262 case CK_Silvermont: 3263 setFeatureEnabledImpl(Features, "aes", true); 3264 setFeatureEnabledImpl(Features, "pclmul", true); 3265 LLVM_FALLTHROUGH; 3266 case CK_Nehalem: 3267 setFeatureEnabledImpl(Features, "sse4.2", true); 3268 setFeatureEnabledImpl(Features, "fxsr", true); 3269 setFeatureEnabledImpl(Features, "cx16", true); 3270 break; 3271 case CK_KNL: 3272 setFeatureEnabledImpl(Features, "avx512f", true); 3273 setFeatureEnabledImpl(Features, "avx512cd", true); 3274 setFeatureEnabledImpl(Features, "avx512er", true); 3275 setFeatureEnabledImpl(Features, "avx512pf", true); 3276 setFeatureEnabledImpl(Features, "prefetchwt1", true); 3277 setFeatureEnabledImpl(Features, "fxsr", true); 3278 setFeatureEnabledImpl(Features, "rdseed", true); 3279 setFeatureEnabledImpl(Features, "adx", true); 3280 setFeatureEnabledImpl(Features, "lzcnt", true); 3281 setFeatureEnabledImpl(Features, "bmi", true); 3282 setFeatureEnabledImpl(Features, "bmi2", true); 3283 setFeatureEnabledImpl(Features, "rtm", true); 3284 setFeatureEnabledImpl(Features, "fma", true); 3285 setFeatureEnabledImpl(Features, "rdrnd", true); 3286 setFeatureEnabledImpl(Features, "f16c", true); 3287 setFeatureEnabledImpl(Features, "fsgsbase", true); 3288 setFeatureEnabledImpl(Features, "aes", true); 3289 setFeatureEnabledImpl(Features, "pclmul", true); 3290 setFeatureEnabledImpl(Features, "cx16", true); 3291 setFeatureEnabledImpl(Features, "xsaveopt", true); 3292 setFeatureEnabledImpl(Features, "xsave", true); 3293 setFeatureEnabledImpl(Features, "movbe", true); 3294 break; 3295 case CK_K6_2: 3296 case CK_K6_3: 3297 case CK_WinChip2: 3298 case CK_C3: 3299 setFeatureEnabledImpl(Features, "3dnow", true); 3300 break; 3301 case CK_Athlon: 3302 case CK_AthlonThunderbird: 3303 case CK_Geode: 3304 setFeatureEnabledImpl(Features, "3dnowa", true); 3305 break; 3306 case CK_Athlon4: 3307 case CK_AthlonXP: 3308 case CK_AthlonMP: 3309 setFeatureEnabledImpl(Features, "sse", true); 3310 setFeatureEnabledImpl(Features, "3dnowa", true); 3311 setFeatureEnabledImpl(Features, "fxsr", true); 3312 break; 3313 case CK_K8: 3314 case CK_Opteron: 3315 case CK_Athlon64: 3316 case CK_AthlonFX: 3317 setFeatureEnabledImpl(Features, "sse2", true); 3318 setFeatureEnabledImpl(Features, "3dnowa", true); 3319 setFeatureEnabledImpl(Features, "fxsr", true); 3320 break; 3321 case CK_AMDFAM10: 3322 setFeatureEnabledImpl(Features, "sse4a", true); 3323 setFeatureEnabledImpl(Features, "lzcnt", true); 3324 setFeatureEnabledImpl(Features, "popcnt", true); 3325 LLVM_FALLTHROUGH; 3326 case CK_K8SSE3: 3327 case CK_OpteronSSE3: 3328 case CK_Athlon64SSE3: 3329 setFeatureEnabledImpl(Features, "sse3", true); 3330 setFeatureEnabledImpl(Features, "3dnowa", true); 3331 setFeatureEnabledImpl(Features, "fxsr", true); 3332 break; 3333 case CK_BTVER2: 3334 setFeatureEnabledImpl(Features, "avx", true); 3335 setFeatureEnabledImpl(Features, "aes", true); 3336 setFeatureEnabledImpl(Features, "pclmul", true); 3337 setFeatureEnabledImpl(Features, "bmi", true); 3338 setFeatureEnabledImpl(Features, "f16c", true); 3339 setFeatureEnabledImpl(Features, "xsaveopt", true); 3340 LLVM_FALLTHROUGH; 3341 case CK_BTVER1: 3342 setFeatureEnabledImpl(Features, "ssse3", true); 3343 setFeatureEnabledImpl(Features, "sse4a", true); 3344 setFeatureEnabledImpl(Features, "lzcnt", true); 3345 setFeatureEnabledImpl(Features, "popcnt", true); 3346 setFeatureEnabledImpl(Features, "prfchw", true); 3347 setFeatureEnabledImpl(Features, "cx16", true); 3348 setFeatureEnabledImpl(Features, "fxsr", true); 3349 break; 3350 case CK_ZNVER1: 3351 setFeatureEnabledImpl(Features, "adx", true); 3352 setFeatureEnabledImpl(Features, "aes", true); 3353 setFeatureEnabledImpl(Features, "avx2", true); 3354 setFeatureEnabledImpl(Features, "bmi", true); 3355 setFeatureEnabledImpl(Features, "bmi2", true); 3356 setFeatureEnabledImpl(Features, "clflushopt", true); 3357 setFeatureEnabledImpl(Features, "clzero", true); 3358 setFeatureEnabledImpl(Features, "cx16", true); 3359 setFeatureEnabledImpl(Features, "f16c", true); 3360 setFeatureEnabledImpl(Features, "fma", true); 3361 setFeatureEnabledImpl(Features, "fsgsbase", true); 3362 setFeatureEnabledImpl(Features, "fxsr", true); 3363 setFeatureEnabledImpl(Features, "lzcnt", true); 3364 setFeatureEnabledImpl(Features, "mwaitx", true); 3365 setFeatureEnabledImpl(Features, "movbe", true); 3366 setFeatureEnabledImpl(Features, "pclmul", true); 3367 setFeatureEnabledImpl(Features, "popcnt", true); 3368 setFeatureEnabledImpl(Features, "prfchw", true); 3369 setFeatureEnabledImpl(Features, "rdrnd", true); 3370 setFeatureEnabledImpl(Features, "rdseed", true); 3371 setFeatureEnabledImpl(Features, "sha", true); 3372 setFeatureEnabledImpl(Features, "sse4a", true); 3373 setFeatureEnabledImpl(Features, "xsave", true); 3374 setFeatureEnabledImpl(Features, "xsavec", true); 3375 setFeatureEnabledImpl(Features, "xsaveopt", true); 3376 setFeatureEnabledImpl(Features, "xsaves", true); 3377 break; 3378 case CK_BDVER4: 3379 setFeatureEnabledImpl(Features, "avx2", true); 3380 setFeatureEnabledImpl(Features, "bmi2", true); 3381 setFeatureEnabledImpl(Features, "mwaitx", true); 3382 LLVM_FALLTHROUGH; 3383 case CK_BDVER3: 3384 setFeatureEnabledImpl(Features, "fsgsbase", true); 3385 setFeatureEnabledImpl(Features, "xsaveopt", true); 3386 LLVM_FALLTHROUGH; 3387 case CK_BDVER2: 3388 setFeatureEnabledImpl(Features, "bmi", true); 3389 setFeatureEnabledImpl(Features, "fma", true); 3390 setFeatureEnabledImpl(Features, "f16c", true); 3391 setFeatureEnabledImpl(Features, "tbm", true); 3392 LLVM_FALLTHROUGH; 3393 case CK_BDVER1: 3394 // xop implies avx, sse4a and fma4. 3395 setFeatureEnabledImpl(Features, "xop", true); 3396 setFeatureEnabledImpl(Features, "lwp", true); 3397 setFeatureEnabledImpl(Features, "lzcnt", true); 3398 setFeatureEnabledImpl(Features, "aes", true); 3399 setFeatureEnabledImpl(Features, "pclmul", true); 3400 setFeatureEnabledImpl(Features, "prfchw", true); 3401 setFeatureEnabledImpl(Features, "cx16", true); 3402 setFeatureEnabledImpl(Features, "fxsr", true); 3403 setFeatureEnabledImpl(Features, "xsave", true); 3404 break; 3405 } 3406 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3407 return false; 3408 3409 // Can't do this earlier because we need to be able to explicitly enable 3410 // or disable these features and the things that they depend upon. 3411 3412 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3413 auto I = Features.find("sse4.2"); 3414 if (I != Features.end() && I->getValue() && 3415 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3416 FeaturesVec.end()) 3417 Features["popcnt"] = true; 3418 3419 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3420 I = Features.find("3dnow"); 3421 if (I != Features.end() && I->getValue() && 3422 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3423 FeaturesVec.end()) 3424 Features["prfchw"] = true; 3425 3426 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3427 // then enable MMX. 3428 I = Features.find("sse"); 3429 if (I != Features.end() && I->getValue() && 3430 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3431 FeaturesVec.end()) 3432 Features["mmx"] = true; 3433 3434 return true; 3435 } 3436 3437 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3438 X86SSEEnum Level, bool Enabled) { 3439 if (Enabled) { 3440 switch (Level) { 3441 case AVX512F: 3442 Features["avx512f"] = true; 3443 LLVM_FALLTHROUGH; 3444 case AVX2: 3445 Features["avx2"] = true; 3446 LLVM_FALLTHROUGH; 3447 case AVX: 3448 Features["avx"] = true; 3449 Features["xsave"] = true; 3450 LLVM_FALLTHROUGH; 3451 case SSE42: 3452 Features["sse4.2"] = true; 3453 LLVM_FALLTHROUGH; 3454 case SSE41: 3455 Features["sse4.1"] = true; 3456 LLVM_FALLTHROUGH; 3457 case SSSE3: 3458 Features["ssse3"] = true; 3459 LLVM_FALLTHROUGH; 3460 case SSE3: 3461 Features["sse3"] = true; 3462 LLVM_FALLTHROUGH; 3463 case SSE2: 3464 Features["sse2"] = true; 3465 LLVM_FALLTHROUGH; 3466 case SSE1: 3467 Features["sse"] = true; 3468 LLVM_FALLTHROUGH; 3469 case NoSSE: 3470 break; 3471 } 3472 return; 3473 } 3474 3475 switch (Level) { 3476 case NoSSE: 3477 case SSE1: 3478 Features["sse"] = false; 3479 LLVM_FALLTHROUGH; 3480 case SSE2: 3481 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3482 Features["sha"] = false; 3483 LLVM_FALLTHROUGH; 3484 case SSE3: 3485 Features["sse3"] = false; 3486 setXOPLevel(Features, NoXOP, false); 3487 LLVM_FALLTHROUGH; 3488 case SSSE3: 3489 Features["ssse3"] = false; 3490 LLVM_FALLTHROUGH; 3491 case SSE41: 3492 Features["sse4.1"] = false; 3493 LLVM_FALLTHROUGH; 3494 case SSE42: 3495 Features["sse4.2"] = false; 3496 LLVM_FALLTHROUGH; 3497 case AVX: 3498 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3499 Features["xsaveopt"] = false; 3500 setXOPLevel(Features, FMA4, false); 3501 LLVM_FALLTHROUGH; 3502 case AVX2: 3503 Features["avx2"] = false; 3504 LLVM_FALLTHROUGH; 3505 case AVX512F: 3506 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3507 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3508 Features["avx512vl"] = Features["avx512vbmi"] = 3509 Features["avx512ifma"] = false; 3510 } 3511 } 3512 3513 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3514 MMX3DNowEnum Level, bool Enabled) { 3515 if (Enabled) { 3516 switch (Level) { 3517 case AMD3DNowAthlon: 3518 Features["3dnowa"] = true; 3519 LLVM_FALLTHROUGH; 3520 case AMD3DNow: 3521 Features["3dnow"] = true; 3522 LLVM_FALLTHROUGH; 3523 case MMX: 3524 Features["mmx"] = true; 3525 LLVM_FALLTHROUGH; 3526 case NoMMX3DNow: 3527 break; 3528 } 3529 return; 3530 } 3531 3532 switch (Level) { 3533 case NoMMX3DNow: 3534 case MMX: 3535 Features["mmx"] = false; 3536 LLVM_FALLTHROUGH; 3537 case AMD3DNow: 3538 Features["3dnow"] = false; 3539 LLVM_FALLTHROUGH; 3540 case AMD3DNowAthlon: 3541 Features["3dnowa"] = false; 3542 } 3543 } 3544 3545 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3546 bool Enabled) { 3547 if (Enabled) { 3548 switch (Level) { 3549 case XOP: 3550 Features["xop"] = true; 3551 LLVM_FALLTHROUGH; 3552 case FMA4: 3553 Features["fma4"] = true; 3554 setSSELevel(Features, AVX, true); 3555 LLVM_FALLTHROUGH; 3556 case SSE4A: 3557 Features["sse4a"] = true; 3558 setSSELevel(Features, SSE3, true); 3559 LLVM_FALLTHROUGH; 3560 case NoXOP: 3561 break; 3562 } 3563 return; 3564 } 3565 3566 switch (Level) { 3567 case NoXOP: 3568 case SSE4A: 3569 Features["sse4a"] = false; 3570 LLVM_FALLTHROUGH; 3571 case FMA4: 3572 Features["fma4"] = false; 3573 LLVM_FALLTHROUGH; 3574 case XOP: 3575 Features["xop"] = false; 3576 } 3577 } 3578 3579 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3580 StringRef Name, bool Enabled) { 3581 // This is a bit of a hack to deal with the sse4 target feature when used 3582 // as part of the target attribute. We handle sse4 correctly everywhere 3583 // else. See below for more information on how we handle the sse4 options. 3584 if (Name != "sse4") 3585 Features[Name] = Enabled; 3586 3587 if (Name == "mmx") { 3588 setMMXLevel(Features, MMX, Enabled); 3589 } else if (Name == "sse") { 3590 setSSELevel(Features, SSE1, Enabled); 3591 } else if (Name == "sse2") { 3592 setSSELevel(Features, SSE2, Enabled); 3593 } else if (Name == "sse3") { 3594 setSSELevel(Features, SSE3, Enabled); 3595 } else if (Name == "ssse3") { 3596 setSSELevel(Features, SSSE3, Enabled); 3597 } else if (Name == "sse4.2") { 3598 setSSELevel(Features, SSE42, Enabled); 3599 } else if (Name == "sse4.1") { 3600 setSSELevel(Features, SSE41, Enabled); 3601 } else if (Name == "3dnow") { 3602 setMMXLevel(Features, AMD3DNow, Enabled); 3603 } else if (Name == "3dnowa") { 3604 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3605 } else if (Name == "aes") { 3606 if (Enabled) 3607 setSSELevel(Features, SSE2, Enabled); 3608 } else if (Name == "pclmul") { 3609 if (Enabled) 3610 setSSELevel(Features, SSE2, Enabled); 3611 } else if (Name == "avx") { 3612 setSSELevel(Features, AVX, Enabled); 3613 } else if (Name == "avx2") { 3614 setSSELevel(Features, AVX2, Enabled); 3615 } else if (Name == "avx512f") { 3616 setSSELevel(Features, AVX512F, Enabled); 3617 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3618 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3619 Name == "avx512vbmi" || Name == "avx512ifma") { 3620 if (Enabled) 3621 setSSELevel(Features, AVX512F, Enabled); 3622 // Enable BWI instruction if VBMI is being enabled. 3623 if (Name == "avx512vbmi" && Enabled) 3624 Features["avx512bw"] = true; 3625 // Also disable VBMI if BWI is being disabled. 3626 if (Name == "avx512bw" && !Enabled) 3627 Features["avx512vbmi"] = false; 3628 } else if (Name == "fma") { 3629 if (Enabled) 3630 setSSELevel(Features, AVX, Enabled); 3631 } else if (Name == "fma4") { 3632 setXOPLevel(Features, FMA4, Enabled); 3633 } else if (Name == "xop") { 3634 setXOPLevel(Features, XOP, Enabled); 3635 } else if (Name == "sse4a") { 3636 setXOPLevel(Features, SSE4A, Enabled); 3637 } else if (Name == "f16c") { 3638 if (Enabled) 3639 setSSELevel(Features, AVX, Enabled); 3640 } else if (Name == "sha") { 3641 if (Enabled) 3642 setSSELevel(Features, SSE2, Enabled); 3643 } else if (Name == "sse4") { 3644 // We can get here via the __target__ attribute since that's not controlled 3645 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3646 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3647 // disabled. 3648 if (Enabled) 3649 setSSELevel(Features, SSE42, Enabled); 3650 else 3651 setSSELevel(Features, SSE41, Enabled); 3652 } else if (Name == "xsave") { 3653 if (!Enabled) 3654 Features["xsaveopt"] = false; 3655 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3656 if (Enabled) 3657 Features["xsave"] = true; 3658 } 3659 } 3660 3661 /// handleTargetFeatures - Perform initialization based on the user 3662 /// configured set of features. 3663 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3664 DiagnosticsEngine &Diags) { 3665 for (const auto &Feature : Features) { 3666 if (Feature[0] != '+') 3667 continue; 3668 3669 if (Feature == "+aes") { 3670 HasAES = true; 3671 } else if (Feature == "+pclmul") { 3672 HasPCLMUL = true; 3673 } else if (Feature == "+lzcnt") { 3674 HasLZCNT = true; 3675 } else if (Feature == "+rdrnd") { 3676 HasRDRND = true; 3677 } else if (Feature == "+fsgsbase") { 3678 HasFSGSBASE = true; 3679 } else if (Feature == "+bmi") { 3680 HasBMI = true; 3681 } else if (Feature == "+bmi2") { 3682 HasBMI2 = true; 3683 } else if (Feature == "+popcnt") { 3684 HasPOPCNT = true; 3685 } else if (Feature == "+rtm") { 3686 HasRTM = true; 3687 } else if (Feature == "+prfchw") { 3688 HasPRFCHW = true; 3689 } else if (Feature == "+rdseed") { 3690 HasRDSEED = true; 3691 } else if (Feature == "+adx") { 3692 HasADX = true; 3693 } else if (Feature == "+tbm") { 3694 HasTBM = true; 3695 } else if (Feature == "+lwp") { 3696 HasLWP = true; 3697 } else if (Feature == "+fma") { 3698 HasFMA = true; 3699 } else if (Feature == "+f16c") { 3700 HasF16C = true; 3701 } else if (Feature == "+avx512cd") { 3702 HasAVX512CD = true; 3703 } else if (Feature == "+avx512er") { 3704 HasAVX512ER = true; 3705 } else if (Feature == "+avx512pf") { 3706 HasAVX512PF = true; 3707 } else if (Feature == "+avx512dq") { 3708 HasAVX512DQ = true; 3709 } else if (Feature == "+avx512bw") { 3710 HasAVX512BW = true; 3711 } else if (Feature == "+avx512vl") { 3712 HasAVX512VL = true; 3713 } else if (Feature == "+avx512vbmi") { 3714 HasAVX512VBMI = true; 3715 } else if (Feature == "+avx512ifma") { 3716 HasAVX512IFMA = true; 3717 } else if (Feature == "+sha") { 3718 HasSHA = true; 3719 } else if (Feature == "+mpx") { 3720 HasMPX = true; 3721 } else if (Feature == "+movbe") { 3722 HasMOVBE = true; 3723 } else if (Feature == "+sgx") { 3724 HasSGX = true; 3725 } else if (Feature == "+cx16") { 3726 HasCX16 = true; 3727 } else if (Feature == "+fxsr") { 3728 HasFXSR = true; 3729 } else if (Feature == "+xsave") { 3730 HasXSAVE = true; 3731 } else if (Feature == "+xsaveopt") { 3732 HasXSAVEOPT = true; 3733 } else if (Feature == "+xsavec") { 3734 HasXSAVEC = true; 3735 } else if (Feature == "+xsaves") { 3736 HasXSAVES = true; 3737 } else if (Feature == "+mwaitx") { 3738 HasMWAITX = true; 3739 } else if (Feature == "+pku") { 3740 HasPKU = true; 3741 } else if (Feature == "+clflushopt") { 3742 HasCLFLUSHOPT = true; 3743 } else if (Feature == "+clwb") { 3744 HasCLWB = true; 3745 } else if (Feature == "+prefetchwt1") { 3746 HasPREFETCHWT1 = true; 3747 } else if (Feature == "+clzero") { 3748 HasCLZERO = true; 3749 } 3750 3751 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3752 .Case("+avx512f", AVX512F) 3753 .Case("+avx2", AVX2) 3754 .Case("+avx", AVX) 3755 .Case("+sse4.2", SSE42) 3756 .Case("+sse4.1", SSE41) 3757 .Case("+ssse3", SSSE3) 3758 .Case("+sse3", SSE3) 3759 .Case("+sse2", SSE2) 3760 .Case("+sse", SSE1) 3761 .Default(NoSSE); 3762 SSELevel = std::max(SSELevel, Level); 3763 3764 MMX3DNowEnum ThreeDNowLevel = 3765 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3766 .Case("+3dnowa", AMD3DNowAthlon) 3767 .Case("+3dnow", AMD3DNow) 3768 .Case("+mmx", MMX) 3769 .Default(NoMMX3DNow); 3770 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3771 3772 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3773 .Case("+xop", XOP) 3774 .Case("+fma4", FMA4) 3775 .Case("+sse4a", SSE4A) 3776 .Default(NoXOP); 3777 XOPLevel = std::max(XOPLevel, XLevel); 3778 } 3779 3780 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3781 // matches the selected sse level. 3782 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3783 (FPMath == FP_387 && SSELevel >= SSE1)) { 3784 Diags.Report(diag::err_target_unsupported_fpmath) << 3785 (FPMath == FP_SSE ? "sse" : "387"); 3786 return false; 3787 } 3788 3789 SimdDefaultAlign = 3790 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3791 return true; 3792 } 3793 3794 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3795 /// definitions for this particular subtarget. 3796 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3797 MacroBuilder &Builder) const { 3798 // Target identification. 3799 if (getTriple().getArch() == llvm::Triple::x86_64) { 3800 Builder.defineMacro("__amd64__"); 3801 Builder.defineMacro("__amd64"); 3802 Builder.defineMacro("__x86_64"); 3803 Builder.defineMacro("__x86_64__"); 3804 if (getTriple().getArchName() == "x86_64h") { 3805 Builder.defineMacro("__x86_64h"); 3806 Builder.defineMacro("__x86_64h__"); 3807 } 3808 } else { 3809 DefineStd(Builder, "i386", Opts); 3810 } 3811 3812 // Subtarget options. 3813 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3814 // truly should be based on -mtune options. 3815 switch (CPU) { 3816 case CK_Generic: 3817 break; 3818 case CK_i386: 3819 // The rest are coming from the i386 define above. 3820 Builder.defineMacro("__tune_i386__"); 3821 break; 3822 case CK_i486: 3823 case CK_WinChipC6: 3824 case CK_WinChip2: 3825 case CK_C3: 3826 defineCPUMacros(Builder, "i486"); 3827 break; 3828 case CK_PentiumMMX: 3829 Builder.defineMacro("__pentium_mmx__"); 3830 Builder.defineMacro("__tune_pentium_mmx__"); 3831 // Fallthrough 3832 case CK_i586: 3833 case CK_Pentium: 3834 defineCPUMacros(Builder, "i586"); 3835 defineCPUMacros(Builder, "pentium"); 3836 break; 3837 case CK_Pentium3: 3838 case CK_Pentium3M: 3839 case CK_PentiumM: 3840 Builder.defineMacro("__tune_pentium3__"); 3841 // Fallthrough 3842 case CK_Pentium2: 3843 case CK_C3_2: 3844 Builder.defineMacro("__tune_pentium2__"); 3845 // Fallthrough 3846 case CK_PentiumPro: 3847 Builder.defineMacro("__tune_i686__"); 3848 Builder.defineMacro("__tune_pentiumpro__"); 3849 // Fallthrough 3850 case CK_i686: 3851 Builder.defineMacro("__i686"); 3852 Builder.defineMacro("__i686__"); 3853 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3854 Builder.defineMacro("__pentiumpro"); 3855 Builder.defineMacro("__pentiumpro__"); 3856 break; 3857 case CK_Pentium4: 3858 case CK_Pentium4M: 3859 defineCPUMacros(Builder, "pentium4"); 3860 break; 3861 case CK_Yonah: 3862 case CK_Prescott: 3863 case CK_Nocona: 3864 defineCPUMacros(Builder, "nocona"); 3865 break; 3866 case CK_Core2: 3867 case CK_Penryn: 3868 defineCPUMacros(Builder, "core2"); 3869 break; 3870 case CK_Bonnell: 3871 defineCPUMacros(Builder, "atom"); 3872 break; 3873 case CK_Silvermont: 3874 defineCPUMacros(Builder, "slm"); 3875 break; 3876 case CK_Nehalem: 3877 case CK_Westmere: 3878 case CK_SandyBridge: 3879 case CK_IvyBridge: 3880 case CK_Haswell: 3881 case CK_Broadwell: 3882 case CK_SkylakeClient: 3883 // FIXME: Historically, we defined this legacy name, it would be nice to 3884 // remove it at some point. We've never exposed fine-grained names for 3885 // recent primary x86 CPUs, and we should keep it that way. 3886 defineCPUMacros(Builder, "corei7"); 3887 break; 3888 case CK_SkylakeServer: 3889 defineCPUMacros(Builder, "skx"); 3890 break; 3891 case CK_Cannonlake: 3892 break; 3893 case CK_KNL: 3894 defineCPUMacros(Builder, "knl"); 3895 break; 3896 case CK_Lakemont: 3897 Builder.defineMacro("__tune_lakemont__"); 3898 break; 3899 case CK_K6_2: 3900 Builder.defineMacro("__k6_2__"); 3901 Builder.defineMacro("__tune_k6_2__"); 3902 // Fallthrough 3903 case CK_K6_3: 3904 if (CPU != CK_K6_2) { // In case of fallthrough 3905 // FIXME: GCC may be enabling these in cases where some other k6 3906 // architecture is specified but -m3dnow is explicitly provided. The 3907 // exact semantics need to be determined and emulated here. 3908 Builder.defineMacro("__k6_3__"); 3909 Builder.defineMacro("__tune_k6_3__"); 3910 } 3911 // Fallthrough 3912 case CK_K6: 3913 defineCPUMacros(Builder, "k6"); 3914 break; 3915 case CK_Athlon: 3916 case CK_AthlonThunderbird: 3917 case CK_Athlon4: 3918 case CK_AthlonXP: 3919 case CK_AthlonMP: 3920 defineCPUMacros(Builder, "athlon"); 3921 if (SSELevel != NoSSE) { 3922 Builder.defineMacro("__athlon_sse__"); 3923 Builder.defineMacro("__tune_athlon_sse__"); 3924 } 3925 break; 3926 case CK_K8: 3927 case CK_K8SSE3: 3928 case CK_x86_64: 3929 case CK_Opteron: 3930 case CK_OpteronSSE3: 3931 case CK_Athlon64: 3932 case CK_Athlon64SSE3: 3933 case CK_AthlonFX: 3934 defineCPUMacros(Builder, "k8"); 3935 break; 3936 case CK_AMDFAM10: 3937 defineCPUMacros(Builder, "amdfam10"); 3938 break; 3939 case CK_BTVER1: 3940 defineCPUMacros(Builder, "btver1"); 3941 break; 3942 case CK_BTVER2: 3943 defineCPUMacros(Builder, "btver2"); 3944 break; 3945 case CK_BDVER1: 3946 defineCPUMacros(Builder, "bdver1"); 3947 break; 3948 case CK_BDVER2: 3949 defineCPUMacros(Builder, "bdver2"); 3950 break; 3951 case CK_BDVER3: 3952 defineCPUMacros(Builder, "bdver3"); 3953 break; 3954 case CK_BDVER4: 3955 defineCPUMacros(Builder, "bdver4"); 3956 break; 3957 case CK_ZNVER1: 3958 defineCPUMacros(Builder, "znver1"); 3959 break; 3960 case CK_Geode: 3961 defineCPUMacros(Builder, "geode"); 3962 break; 3963 } 3964 3965 // Target properties. 3966 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3967 3968 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3969 // functions in glibc header files that use FP Stack inline asm which the 3970 // backend can't deal with (PR879). 3971 Builder.defineMacro("__NO_MATH_INLINES"); 3972 3973 if (HasAES) 3974 Builder.defineMacro("__AES__"); 3975 3976 if (HasPCLMUL) 3977 Builder.defineMacro("__PCLMUL__"); 3978 3979 if (HasLZCNT) 3980 Builder.defineMacro("__LZCNT__"); 3981 3982 if (HasRDRND) 3983 Builder.defineMacro("__RDRND__"); 3984 3985 if (HasFSGSBASE) 3986 Builder.defineMacro("__FSGSBASE__"); 3987 3988 if (HasBMI) 3989 Builder.defineMacro("__BMI__"); 3990 3991 if (HasBMI2) 3992 Builder.defineMacro("__BMI2__"); 3993 3994 if (HasPOPCNT) 3995 Builder.defineMacro("__POPCNT__"); 3996 3997 if (HasRTM) 3998 Builder.defineMacro("__RTM__"); 3999 4000 if (HasPRFCHW) 4001 Builder.defineMacro("__PRFCHW__"); 4002 4003 if (HasRDSEED) 4004 Builder.defineMacro("__RDSEED__"); 4005 4006 if (HasADX) 4007 Builder.defineMacro("__ADX__"); 4008 4009 if (HasTBM) 4010 Builder.defineMacro("__TBM__"); 4011 4012 if (HasLWP) 4013 Builder.defineMacro("__LWP__"); 4014 4015 if (HasMWAITX) 4016 Builder.defineMacro("__MWAITX__"); 4017 4018 switch (XOPLevel) { 4019 case XOP: 4020 Builder.defineMacro("__XOP__"); 4021 LLVM_FALLTHROUGH; 4022 case FMA4: 4023 Builder.defineMacro("__FMA4__"); 4024 LLVM_FALLTHROUGH; 4025 case SSE4A: 4026 Builder.defineMacro("__SSE4A__"); 4027 LLVM_FALLTHROUGH; 4028 case NoXOP: 4029 break; 4030 } 4031 4032 if (HasFMA) 4033 Builder.defineMacro("__FMA__"); 4034 4035 if (HasF16C) 4036 Builder.defineMacro("__F16C__"); 4037 4038 if (HasAVX512CD) 4039 Builder.defineMacro("__AVX512CD__"); 4040 if (HasAVX512ER) 4041 Builder.defineMacro("__AVX512ER__"); 4042 if (HasAVX512PF) 4043 Builder.defineMacro("__AVX512PF__"); 4044 if (HasAVX512DQ) 4045 Builder.defineMacro("__AVX512DQ__"); 4046 if (HasAVX512BW) 4047 Builder.defineMacro("__AVX512BW__"); 4048 if (HasAVX512VL) 4049 Builder.defineMacro("__AVX512VL__"); 4050 if (HasAVX512VBMI) 4051 Builder.defineMacro("__AVX512VBMI__"); 4052 if (HasAVX512IFMA) 4053 Builder.defineMacro("__AVX512IFMA__"); 4054 4055 if (HasSHA) 4056 Builder.defineMacro("__SHA__"); 4057 4058 if (HasFXSR) 4059 Builder.defineMacro("__FXSR__"); 4060 if (HasXSAVE) 4061 Builder.defineMacro("__XSAVE__"); 4062 if (HasXSAVEOPT) 4063 Builder.defineMacro("__XSAVEOPT__"); 4064 if (HasXSAVEC) 4065 Builder.defineMacro("__XSAVEC__"); 4066 if (HasXSAVES) 4067 Builder.defineMacro("__XSAVES__"); 4068 if (HasPKU) 4069 Builder.defineMacro("__PKU__"); 4070 if (HasCX16) 4071 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 4072 if (HasCLFLUSHOPT) 4073 Builder.defineMacro("__CLFLUSHOPT__"); 4074 if (HasCLWB) 4075 Builder.defineMacro("__CLWB__"); 4076 if (HasMPX) 4077 Builder.defineMacro("__MPX__"); 4078 if (HasSGX) 4079 Builder.defineMacro("__SGX__"); 4080 if (HasPREFETCHWT1) 4081 Builder.defineMacro("__PREFETCHWT1__"); 4082 if (HasCLZERO) 4083 Builder.defineMacro("__CLZERO__"); 4084 4085 // Each case falls through to the previous one here. 4086 switch (SSELevel) { 4087 case AVX512F: 4088 Builder.defineMacro("__AVX512F__"); 4089 LLVM_FALLTHROUGH; 4090 case AVX2: 4091 Builder.defineMacro("__AVX2__"); 4092 LLVM_FALLTHROUGH; 4093 case AVX: 4094 Builder.defineMacro("__AVX__"); 4095 LLVM_FALLTHROUGH; 4096 case SSE42: 4097 Builder.defineMacro("__SSE4_2__"); 4098 LLVM_FALLTHROUGH; 4099 case SSE41: 4100 Builder.defineMacro("__SSE4_1__"); 4101 LLVM_FALLTHROUGH; 4102 case SSSE3: 4103 Builder.defineMacro("__SSSE3__"); 4104 LLVM_FALLTHROUGH; 4105 case SSE3: 4106 Builder.defineMacro("__SSE3__"); 4107 LLVM_FALLTHROUGH; 4108 case SSE2: 4109 Builder.defineMacro("__SSE2__"); 4110 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 4111 LLVM_FALLTHROUGH; 4112 case SSE1: 4113 Builder.defineMacro("__SSE__"); 4114 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 4115 LLVM_FALLTHROUGH; 4116 case NoSSE: 4117 break; 4118 } 4119 4120 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 4121 switch (SSELevel) { 4122 case AVX512F: 4123 case AVX2: 4124 case AVX: 4125 case SSE42: 4126 case SSE41: 4127 case SSSE3: 4128 case SSE3: 4129 case SSE2: 4130 Builder.defineMacro("_M_IX86_FP", Twine(2)); 4131 break; 4132 case SSE1: 4133 Builder.defineMacro("_M_IX86_FP", Twine(1)); 4134 break; 4135 default: 4136 Builder.defineMacro("_M_IX86_FP", Twine(0)); 4137 } 4138 } 4139 4140 // Each case falls through to the previous one here. 4141 switch (MMX3DNowLevel) { 4142 case AMD3DNowAthlon: 4143 Builder.defineMacro("__3dNOW_A__"); 4144 LLVM_FALLTHROUGH; 4145 case AMD3DNow: 4146 Builder.defineMacro("__3dNOW__"); 4147 LLVM_FALLTHROUGH; 4148 case MMX: 4149 Builder.defineMacro("__MMX__"); 4150 LLVM_FALLTHROUGH; 4151 case NoMMX3DNow: 4152 break; 4153 } 4154 4155 if (CPU >= CK_i486) { 4156 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4157 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4158 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4159 } 4160 if (CPU >= CK_i586) 4161 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4162 } 4163 4164 bool X86TargetInfo::hasFeature(StringRef Feature) const { 4165 return llvm::StringSwitch<bool>(Feature) 4166 .Case("aes", HasAES) 4167 .Case("avx", SSELevel >= AVX) 4168 .Case("avx2", SSELevel >= AVX2) 4169 .Case("avx512f", SSELevel >= AVX512F) 4170 .Case("avx512cd", HasAVX512CD) 4171 .Case("avx512er", HasAVX512ER) 4172 .Case("avx512pf", HasAVX512PF) 4173 .Case("avx512dq", HasAVX512DQ) 4174 .Case("avx512bw", HasAVX512BW) 4175 .Case("avx512vl", HasAVX512VL) 4176 .Case("avx512vbmi", HasAVX512VBMI) 4177 .Case("avx512ifma", HasAVX512IFMA) 4178 .Case("bmi", HasBMI) 4179 .Case("bmi2", HasBMI2) 4180 .Case("clflushopt", HasCLFLUSHOPT) 4181 .Case("clwb", HasCLWB) 4182 .Case("clzero", HasCLZERO) 4183 .Case("cx16", HasCX16) 4184 .Case("f16c", HasF16C) 4185 .Case("fma", HasFMA) 4186 .Case("fma4", XOPLevel >= FMA4) 4187 .Case("fsgsbase", HasFSGSBASE) 4188 .Case("fxsr", HasFXSR) 4189 .Case("lzcnt", HasLZCNT) 4190 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 4191 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 4192 .Case("mmx", MMX3DNowLevel >= MMX) 4193 .Case("movbe", HasMOVBE) 4194 .Case("mpx", HasMPX) 4195 .Case("pclmul", HasPCLMUL) 4196 .Case("pku", HasPKU) 4197 .Case("popcnt", HasPOPCNT) 4198 .Case("prefetchwt1", HasPREFETCHWT1) 4199 .Case("prfchw", HasPRFCHW) 4200 .Case("rdrnd", HasRDRND) 4201 .Case("rdseed", HasRDSEED) 4202 .Case("rtm", HasRTM) 4203 .Case("sgx", HasSGX) 4204 .Case("sha", HasSHA) 4205 .Case("sse", SSELevel >= SSE1) 4206 .Case("sse2", SSELevel >= SSE2) 4207 .Case("sse3", SSELevel >= SSE3) 4208 .Case("ssse3", SSELevel >= SSSE3) 4209 .Case("sse4.1", SSELevel >= SSE41) 4210 .Case("sse4.2", SSELevel >= SSE42) 4211 .Case("sse4a", XOPLevel >= SSE4A) 4212 .Case("tbm", HasTBM) 4213 .Case("lwp", HasLWP) 4214 .Case("x86", true) 4215 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 4216 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 4217 .Case("xop", XOPLevel >= XOP) 4218 .Case("xsave", HasXSAVE) 4219 .Case("xsavec", HasXSAVEC) 4220 .Case("xsaves", HasXSAVES) 4221 .Case("xsaveopt", HasXSAVEOPT) 4222 .Default(false); 4223 } 4224 4225 // We can't use a generic validation scheme for the features accepted here 4226 // versus subtarget features accepted in the target attribute because the 4227 // bitfield structure that's initialized in the runtime only supports the 4228 // below currently rather than the full range of subtarget features. (See 4229 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 4230 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 4231 return llvm::StringSwitch<bool>(FeatureStr) 4232 .Case("cmov", true) 4233 .Case("mmx", true) 4234 .Case("popcnt", true) 4235 .Case("sse", true) 4236 .Case("sse2", true) 4237 .Case("sse3", true) 4238 .Case("ssse3", true) 4239 .Case("sse4.1", true) 4240 .Case("sse4.2", true) 4241 .Case("avx", true) 4242 .Case("avx2", true) 4243 .Case("sse4a", true) 4244 .Case("fma4", true) 4245 .Case("xop", true) 4246 .Case("fma", true) 4247 .Case("avx512f", true) 4248 .Case("bmi", true) 4249 .Case("bmi2", true) 4250 .Case("aes", true) 4251 .Case("pclmul", true) 4252 .Case("avx512vl", true) 4253 .Case("avx512bw", true) 4254 .Case("avx512dq", true) 4255 .Case("avx512cd", true) 4256 .Case("avx512er", true) 4257 .Case("avx512pf", true) 4258 .Case("avx512vbmi", true) 4259 .Case("avx512ifma", true) 4260 .Default(false); 4261 } 4262 4263 bool 4264 X86TargetInfo::validateAsmConstraint(const char *&Name, 4265 TargetInfo::ConstraintInfo &Info) const { 4266 switch (*Name) { 4267 default: return false; 4268 // Constant constraints. 4269 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 4270 // instructions. 4271 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 4272 // x86_64 instructions. 4273 case 's': 4274 Info.setRequiresImmediate(); 4275 return true; 4276 case 'I': 4277 Info.setRequiresImmediate(0, 31); 4278 return true; 4279 case 'J': 4280 Info.setRequiresImmediate(0, 63); 4281 return true; 4282 case 'K': 4283 Info.setRequiresImmediate(-128, 127); 4284 return true; 4285 case 'L': 4286 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 4287 return true; 4288 case 'M': 4289 Info.setRequiresImmediate(0, 3); 4290 return true; 4291 case 'N': 4292 Info.setRequiresImmediate(0, 255); 4293 return true; 4294 case 'O': 4295 Info.setRequiresImmediate(0, 127); 4296 return true; 4297 // Register constraints. 4298 case 'Y': // 'Y' is the first character for several 2-character constraints. 4299 // Shift the pointer to the second character of the constraint. 4300 Name++; 4301 switch (*Name) { 4302 default: 4303 return false; 4304 case '0': // First SSE register. 4305 case 't': // Any SSE register, when SSE2 is enabled. 4306 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 4307 case 'm': // Any MMX register, when inter-unit moves enabled. 4308 case 'k': // AVX512 arch mask registers: k1-k7. 4309 Info.setAllowsRegister(); 4310 return true; 4311 } 4312 case 'f': // Any x87 floating point stack register. 4313 // Constraint 'f' cannot be used for output operands. 4314 if (Info.ConstraintStr[0] == '=') 4315 return false; 4316 Info.setAllowsRegister(); 4317 return true; 4318 case 'a': // eax. 4319 case 'b': // ebx. 4320 case 'c': // ecx. 4321 case 'd': // edx. 4322 case 'S': // esi. 4323 case 'D': // edi. 4324 case 'A': // edx:eax. 4325 case 't': // Top of floating point stack. 4326 case 'u': // Second from top of floating point stack. 4327 case 'q': // Any register accessible as [r]l: a, b, c, and d. 4328 case 'y': // Any MMX register. 4329 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 4330 case 'x': // Any SSE register. 4331 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 4332 // for intermideate k reg operations). 4333 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 4334 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 4335 case 'l': // "Index" registers: any general register that can be used as an 4336 // index in a base+index memory access. 4337 Info.setAllowsRegister(); 4338 return true; 4339 // Floating point constant constraints. 4340 case 'C': // SSE floating point constant. 4341 case 'G': // x87 floating point constant. 4342 return true; 4343 } 4344 } 4345 4346 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 4347 unsigned Size) const { 4348 // Strip off constraint modifiers. 4349 while (Constraint[0] == '=' || 4350 Constraint[0] == '+' || 4351 Constraint[0] == '&') 4352 Constraint = Constraint.substr(1); 4353 4354 return validateOperandSize(Constraint, Size); 4355 } 4356 4357 bool X86TargetInfo::validateInputSize(StringRef Constraint, 4358 unsigned Size) const { 4359 return validateOperandSize(Constraint, Size); 4360 } 4361 4362 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 4363 unsigned Size) const { 4364 switch (Constraint[0]) { 4365 default: break; 4366 case 'k': 4367 // Registers k0-k7 (AVX512) size limit is 64 bit. 4368 case 'y': 4369 return Size <= 64; 4370 case 'f': 4371 case 't': 4372 case 'u': 4373 return Size <= 128; 4374 case 'v': 4375 case 'x': 4376 if (SSELevel >= AVX512F) 4377 // 512-bit zmm registers can be used if target supports AVX512F. 4378 return Size <= 512U; 4379 else if (SSELevel >= AVX) 4380 // 256-bit ymm registers can be used if target supports AVX. 4381 return Size <= 256U; 4382 return Size <= 128U; 4383 case 'Y': 4384 // 'Y' is the first character for several 2-character constraints. 4385 switch (Constraint[1]) { 4386 default: break; 4387 case 'm': 4388 // 'Ym' is synonymous with 'y'. 4389 case 'k': 4390 return Size <= 64; 4391 case 'i': 4392 case 't': 4393 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4394 if (SSELevel >= AVX512F) 4395 return Size <= 512U; 4396 else if (SSELevel >= AVX) 4397 return Size <= 256U; 4398 return SSELevel >= SSE2 && Size <= 128U; 4399 } 4400 4401 } 4402 4403 return true; 4404 } 4405 4406 std::string 4407 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4408 switch (*Constraint) { 4409 case 'a': return std::string("{ax}"); 4410 case 'b': return std::string("{bx}"); 4411 case 'c': return std::string("{cx}"); 4412 case 'd': return std::string("{dx}"); 4413 case 'S': return std::string("{si}"); 4414 case 'D': return std::string("{di}"); 4415 case 'p': // address 4416 return std::string("im"); 4417 case 't': // top of floating point stack. 4418 return std::string("{st}"); 4419 case 'u': // second from top of floating point stack. 4420 return std::string("{st(1)}"); // second from top of floating point stack. 4421 case 'Y': 4422 switch (Constraint[1]) { 4423 default: 4424 // Break from inner switch and fall through (copy single char), 4425 // continue parsing after copying the current constraint into 4426 // the return string. 4427 break; 4428 case 'k': 4429 // "^" hints llvm that this is a 2 letter constraint. 4430 // "Constraint++" is used to promote the string iterator 4431 // to the next constraint. 4432 return std::string("^") + std::string(Constraint++, 2); 4433 } 4434 LLVM_FALLTHROUGH; 4435 default: 4436 return std::string(1, *Constraint); 4437 } 4438 } 4439 4440 // X86-32 generic target 4441 class X86_32TargetInfo : public X86TargetInfo { 4442 public: 4443 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4444 : X86TargetInfo(Triple, Opts) { 4445 DoubleAlign = LongLongAlign = 32; 4446 LongDoubleWidth = 96; 4447 LongDoubleAlign = 32; 4448 SuitableAlign = 128; 4449 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4450 SizeType = UnsignedInt; 4451 PtrDiffType = SignedInt; 4452 IntPtrType = SignedInt; 4453 RegParmMax = 3; 4454 4455 // Use fpret for all types. 4456 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4457 (1 << TargetInfo::Double) | 4458 (1 << TargetInfo::LongDouble)); 4459 4460 // x86-32 has atomics up to 8 bytes 4461 // FIXME: Check that we actually have cmpxchg8b before setting 4462 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4463 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4464 } 4465 BuiltinVaListKind getBuiltinVaListKind() const override { 4466 return TargetInfo::CharPtrBuiltinVaList; 4467 } 4468 4469 int getEHDataRegisterNumber(unsigned RegNo) const override { 4470 if (RegNo == 0) return 0; 4471 if (RegNo == 1) return 2; 4472 return -1; 4473 } 4474 bool validateOperandSize(StringRef Constraint, 4475 unsigned Size) const override { 4476 switch (Constraint[0]) { 4477 default: break; 4478 case 'R': 4479 case 'q': 4480 case 'Q': 4481 case 'a': 4482 case 'b': 4483 case 'c': 4484 case 'd': 4485 case 'S': 4486 case 'D': 4487 return Size <= 32; 4488 case 'A': 4489 return Size <= 64; 4490 } 4491 4492 return X86TargetInfo::validateOperandSize(Constraint, Size); 4493 } 4494 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4495 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 4496 Builtin::FirstTSBuiltin + 1); 4497 } 4498 }; 4499 4500 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4501 public: 4502 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4503 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4504 4505 unsigned getFloatEvalMethod() const override { 4506 unsigned Major, Minor, Micro; 4507 getTriple().getOSVersion(Major, Minor, Micro); 4508 // New NetBSD uses the default rounding mode. 4509 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4510 return X86_32TargetInfo::getFloatEvalMethod(); 4511 // NetBSD before 6.99.26 defaults to "double" rounding. 4512 return 1; 4513 } 4514 }; 4515 4516 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4517 public: 4518 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4519 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4520 SizeType = UnsignedLong; 4521 IntPtrType = SignedLong; 4522 PtrDiffType = SignedLong; 4523 } 4524 }; 4525 4526 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4527 public: 4528 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4529 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4530 SizeType = UnsignedLong; 4531 IntPtrType = SignedLong; 4532 PtrDiffType = SignedLong; 4533 } 4534 }; 4535 4536 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4537 public: 4538 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4539 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4540 LongDoubleWidth = 128; 4541 LongDoubleAlign = 128; 4542 SuitableAlign = 128; 4543 MaxVectorAlign = 256; 4544 // The watchOS simulator uses the builtin bool type for Objective-C. 4545 llvm::Triple T = llvm::Triple(Triple); 4546 if (T.isWatchOS()) 4547 UseSignedCharForObjCBool = false; 4548 SizeType = UnsignedLong; 4549 IntPtrType = SignedLong; 4550 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4551 HasAlignMac68kSupport = true; 4552 } 4553 4554 bool handleTargetFeatures(std::vector<std::string> &Features, 4555 DiagnosticsEngine &Diags) override { 4556 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4557 Diags)) 4558 return false; 4559 // We now know the features we have: we can decide how to align vectors. 4560 MaxVectorAlign = 4561 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4562 return true; 4563 } 4564 }; 4565 4566 // x86-32 Windows target 4567 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4568 public: 4569 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4570 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4571 WCharType = UnsignedShort; 4572 DoubleAlign = LongLongAlign = 64; 4573 bool IsWinCOFF = 4574 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4575 resetDataLayout(IsWinCOFF 4576 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4577 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4578 } 4579 void getTargetDefines(const LangOptions &Opts, 4580 MacroBuilder &Builder) const override { 4581 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4582 } 4583 }; 4584 4585 // x86-32 Windows Visual Studio target 4586 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4587 public: 4588 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4589 const TargetOptions &Opts) 4590 : WindowsX86_32TargetInfo(Triple, Opts) { 4591 LongDoubleWidth = LongDoubleAlign = 64; 4592 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4593 } 4594 void getTargetDefines(const LangOptions &Opts, 4595 MacroBuilder &Builder) const override { 4596 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4597 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4598 // The value of the following reflects processor type. 4599 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4600 // We lost the original triple, so we use the default. 4601 Builder.defineMacro("_M_IX86", "600"); 4602 } 4603 }; 4604 4605 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4606 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4607 // supports __declspec natively under -fms-extensions, but we define a no-op 4608 // __declspec macro anyway for pre-processor compatibility. 4609 if (Opts.MicrosoftExt) 4610 Builder.defineMacro("__declspec", "__declspec"); 4611 else 4612 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4613 4614 if (!Opts.MicrosoftExt) { 4615 // Provide macros for all the calling convention keywords. Provide both 4616 // single and double underscore prefixed variants. These are available on 4617 // x64 as well as x86, even though they have no effect. 4618 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4619 for (const char *CC : CCs) { 4620 std::string GCCSpelling = "__attribute__((__"; 4621 GCCSpelling += CC; 4622 GCCSpelling += "__))"; 4623 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4624 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4625 } 4626 } 4627 } 4628 4629 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4630 Builder.defineMacro("__MSVCRT__"); 4631 Builder.defineMacro("__MINGW32__"); 4632 addCygMingDefines(Opts, Builder); 4633 } 4634 4635 // x86-32 MinGW target 4636 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4637 public: 4638 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4639 : WindowsX86_32TargetInfo(Triple, Opts) {} 4640 void getTargetDefines(const LangOptions &Opts, 4641 MacroBuilder &Builder) const override { 4642 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4643 DefineStd(Builder, "WIN32", Opts); 4644 DefineStd(Builder, "WINNT", Opts); 4645 Builder.defineMacro("_X86_"); 4646 addMinGWDefines(Opts, Builder); 4647 } 4648 }; 4649 4650 // x86-32 Cygwin target 4651 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4652 public: 4653 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4654 : X86_32TargetInfo(Triple, Opts) { 4655 WCharType = UnsignedShort; 4656 DoubleAlign = LongLongAlign = 64; 4657 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4658 } 4659 void getTargetDefines(const LangOptions &Opts, 4660 MacroBuilder &Builder) const override { 4661 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4662 Builder.defineMacro("_X86_"); 4663 Builder.defineMacro("__CYGWIN__"); 4664 Builder.defineMacro("__CYGWIN32__"); 4665 addCygMingDefines(Opts, Builder); 4666 DefineStd(Builder, "unix", Opts); 4667 if (Opts.CPlusPlus) 4668 Builder.defineMacro("_GNU_SOURCE"); 4669 } 4670 }; 4671 4672 // x86-32 Haiku target 4673 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4674 public: 4675 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4676 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4677 } 4678 void getTargetDefines(const LangOptions &Opts, 4679 MacroBuilder &Builder) const override { 4680 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4681 Builder.defineMacro("__INTEL__"); 4682 } 4683 }; 4684 4685 // X86-32 MCU target 4686 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4687 public: 4688 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4689 : X86_32TargetInfo(Triple, Opts) { 4690 LongDoubleWidth = 64; 4691 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4692 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4693 WIntType = UnsignedInt; 4694 } 4695 4696 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4697 // On MCU we support only C calling convention. 4698 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4699 } 4700 4701 void getTargetDefines(const LangOptions &Opts, 4702 MacroBuilder &Builder) const override { 4703 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4704 Builder.defineMacro("__iamcu"); 4705 Builder.defineMacro("__iamcu__"); 4706 } 4707 4708 bool allowsLargerPreferedTypeAlignment() const override { 4709 return false; 4710 } 4711 }; 4712 4713 // RTEMS Target 4714 template<typename Target> 4715 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4716 protected: 4717 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4718 MacroBuilder &Builder) const override { 4719 // RTEMS defines; list based off of gcc output 4720 4721 Builder.defineMacro("__rtems__"); 4722 Builder.defineMacro("__ELF__"); 4723 } 4724 4725 public: 4726 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4727 : OSTargetInfo<Target>(Triple, Opts) { 4728 switch (Triple.getArch()) { 4729 default: 4730 case llvm::Triple::x86: 4731 // this->MCountName = ".mcount"; 4732 break; 4733 case llvm::Triple::mips: 4734 case llvm::Triple::mipsel: 4735 case llvm::Triple::ppc: 4736 case llvm::Triple::ppc64: 4737 case llvm::Triple::ppc64le: 4738 // this->MCountName = "_mcount"; 4739 break; 4740 case llvm::Triple::arm: 4741 // this->MCountName = "__mcount"; 4742 break; 4743 } 4744 } 4745 }; 4746 4747 // x86-32 RTEMS target 4748 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4749 public: 4750 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4751 : X86_32TargetInfo(Triple, Opts) { 4752 SizeType = UnsignedLong; 4753 IntPtrType = SignedLong; 4754 PtrDiffType = SignedLong; 4755 } 4756 void getTargetDefines(const LangOptions &Opts, 4757 MacroBuilder &Builder) const override { 4758 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4759 Builder.defineMacro("__INTEL__"); 4760 Builder.defineMacro("__rtems__"); 4761 } 4762 }; 4763 4764 // x86-64 generic target 4765 class X86_64TargetInfo : public X86TargetInfo { 4766 public: 4767 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4768 : X86TargetInfo(Triple, Opts) { 4769 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4770 bool IsWinCOFF = 4771 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4772 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4773 LongDoubleWidth = 128; 4774 LongDoubleAlign = 128; 4775 LargeArrayMinWidth = 128; 4776 LargeArrayAlign = 128; 4777 SuitableAlign = 128; 4778 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4779 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4780 IntPtrType = IsX32 ? SignedInt : SignedLong; 4781 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4782 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4783 RegParmMax = 6; 4784 4785 // Pointers are 32-bit in x32. 4786 resetDataLayout(IsX32 4787 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4788 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4789 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4790 4791 // Use fpret only for long double. 4792 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4793 4794 // Use fp2ret for _Complex long double. 4795 ComplexLongDoubleUsesFP2Ret = true; 4796 4797 // Make __builtin_ms_va_list available. 4798 HasBuiltinMSVaList = true; 4799 4800 // x86-64 has atomics up to 16 bytes. 4801 MaxAtomicPromoteWidth = 128; 4802 MaxAtomicInlineWidth = 128; 4803 } 4804 BuiltinVaListKind getBuiltinVaListKind() const override { 4805 return TargetInfo::X86_64ABIBuiltinVaList; 4806 } 4807 4808 int getEHDataRegisterNumber(unsigned RegNo) const override { 4809 if (RegNo == 0) return 0; 4810 if (RegNo == 1) return 1; 4811 return -1; 4812 } 4813 4814 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4815 switch (CC) { 4816 case CC_C: 4817 case CC_Swift: 4818 case CC_X86VectorCall: 4819 case CC_IntelOclBicc: 4820 case CC_X86_64Win64: 4821 case CC_PreserveMost: 4822 case CC_PreserveAll: 4823 case CC_X86RegCall: 4824 return CCCR_OK; 4825 default: 4826 return CCCR_Warning; 4827 } 4828 } 4829 4830 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4831 return CC_C; 4832 } 4833 4834 // for x32 we need it here explicitly 4835 bool hasInt128Type() const override { return true; } 4836 unsigned getUnwindWordWidth() const override { return 64; } 4837 unsigned getRegisterWidth() const override { return 64; } 4838 4839 bool validateGlobalRegisterVariable(StringRef RegName, 4840 unsigned RegSize, 4841 bool &HasSizeMismatch) const override { 4842 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4843 // handle. 4844 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4845 // Check that the register size is 64-bit. 4846 HasSizeMismatch = RegSize != 64; 4847 return true; 4848 } 4849 4850 // Check if the register is a 32-bit register the backend can handle. 4851 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4852 HasSizeMismatch); 4853 } 4854 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4855 return llvm::makeArrayRef(BuiltinInfoX86, 4856 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 4857 } 4858 }; 4859 4860 // x86-64 Windows target 4861 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4862 public: 4863 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4864 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4865 WCharType = UnsignedShort; 4866 LongWidth = LongAlign = 32; 4867 DoubleAlign = LongLongAlign = 64; 4868 IntMaxType = SignedLongLong; 4869 Int64Type = SignedLongLong; 4870 SizeType = UnsignedLongLong; 4871 PtrDiffType = SignedLongLong; 4872 IntPtrType = SignedLongLong; 4873 } 4874 4875 void getTargetDefines(const LangOptions &Opts, 4876 MacroBuilder &Builder) const override { 4877 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4878 Builder.defineMacro("_WIN64"); 4879 } 4880 4881 BuiltinVaListKind getBuiltinVaListKind() const override { 4882 return TargetInfo::CharPtrBuiltinVaList; 4883 } 4884 4885 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4886 switch (CC) { 4887 case CC_X86StdCall: 4888 case CC_X86ThisCall: 4889 case CC_X86FastCall: 4890 return CCCR_Ignore; 4891 case CC_C: 4892 case CC_X86VectorCall: 4893 case CC_IntelOclBicc: 4894 case CC_X86_64SysV: 4895 case CC_Swift: 4896 case CC_X86RegCall: 4897 return CCCR_OK; 4898 default: 4899 return CCCR_Warning; 4900 } 4901 } 4902 }; 4903 4904 // x86-64 Windows Visual Studio target 4905 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4906 public: 4907 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4908 const TargetOptions &Opts) 4909 : WindowsX86_64TargetInfo(Triple, Opts) { 4910 LongDoubleWidth = LongDoubleAlign = 64; 4911 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4912 } 4913 void getTargetDefines(const LangOptions &Opts, 4914 MacroBuilder &Builder) const override { 4915 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4916 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4917 Builder.defineMacro("_M_X64", "100"); 4918 Builder.defineMacro("_M_AMD64", "100"); 4919 } 4920 }; 4921 4922 // x86-64 MinGW target 4923 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4924 public: 4925 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4926 : WindowsX86_64TargetInfo(Triple, Opts) { 4927 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4928 // with x86 FP ops. Weird. 4929 LongDoubleWidth = LongDoubleAlign = 128; 4930 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 4931 } 4932 4933 void getTargetDefines(const LangOptions &Opts, 4934 MacroBuilder &Builder) const override { 4935 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4936 DefineStd(Builder, "WIN64", Opts); 4937 Builder.defineMacro("__MINGW64__"); 4938 addMinGWDefines(Opts, Builder); 4939 4940 // GCC defines this macro when it is using __gxx_personality_seh0. 4941 if (!Opts.SjLjExceptions) 4942 Builder.defineMacro("__SEH__"); 4943 } 4944 }; 4945 4946 // x86-64 Cygwin target 4947 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4948 public: 4949 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4950 : X86_64TargetInfo(Triple, Opts) { 4951 TLSSupported = false; 4952 WCharType = UnsignedShort; 4953 } 4954 void getTargetDefines(const LangOptions &Opts, 4955 MacroBuilder &Builder) const override { 4956 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4957 Builder.defineMacro("__x86_64__"); 4958 Builder.defineMacro("__CYGWIN__"); 4959 Builder.defineMacro("__CYGWIN64__"); 4960 addCygMingDefines(Opts, Builder); 4961 DefineStd(Builder, "unix", Opts); 4962 if (Opts.CPlusPlus) 4963 Builder.defineMacro("_GNU_SOURCE"); 4964 4965 // GCC defines this macro when it is using __gxx_personality_seh0. 4966 if (!Opts.SjLjExceptions) 4967 Builder.defineMacro("__SEH__"); 4968 } 4969 }; 4970 4971 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4972 public: 4973 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4974 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4975 Int64Type = SignedLongLong; 4976 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4977 llvm::Triple T = llvm::Triple(Triple); 4978 if (T.isiOS()) 4979 UseSignedCharForObjCBool = false; 4980 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4981 } 4982 4983 bool handleTargetFeatures(std::vector<std::string> &Features, 4984 DiagnosticsEngine &Diags) override { 4985 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4986 Diags)) 4987 return false; 4988 // We now know the features we have: we can decide how to align vectors. 4989 MaxVectorAlign = 4990 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4991 return true; 4992 } 4993 }; 4994 4995 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4996 public: 4997 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4998 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4999 IntMaxType = SignedLongLong; 5000 Int64Type = SignedLongLong; 5001 } 5002 }; 5003 5004 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 5005 public: 5006 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5007 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5008 IntMaxType = SignedLongLong; 5009 Int64Type = SignedLongLong; 5010 } 5011 }; 5012 5013 class ARMTargetInfo : public TargetInfo { 5014 // Possible FPU choices. 5015 enum FPUMode { 5016 VFP2FPU = (1 << 0), 5017 VFP3FPU = (1 << 1), 5018 VFP4FPU = (1 << 2), 5019 NeonFPU = (1 << 3), 5020 FPARMV8 = (1 << 4) 5021 }; 5022 5023 // Possible HWDiv features. 5024 enum HWDivMode { 5025 HWDivThumb = (1 << 0), 5026 HWDivARM = (1 << 1) 5027 }; 5028 5029 static bool FPUModeIsVFP(FPUMode Mode) { 5030 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 5031 } 5032 5033 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5034 static const char * const GCCRegNames[]; 5035 5036 std::string ABI, CPU; 5037 5038 StringRef CPUProfile; 5039 StringRef CPUAttr; 5040 5041 enum { 5042 FP_Default, 5043 FP_VFP, 5044 FP_Neon 5045 } FPMath; 5046 5047 unsigned ArchISA; 5048 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 5049 unsigned ArchProfile; 5050 unsigned ArchVersion; 5051 5052 unsigned FPU : 5; 5053 5054 unsigned IsAAPCS : 1; 5055 unsigned HWDiv : 2; 5056 5057 // Initialized via features. 5058 unsigned SoftFloat : 1; 5059 unsigned SoftFloatABI : 1; 5060 5061 unsigned CRC : 1; 5062 unsigned Crypto : 1; 5063 unsigned DSP : 1; 5064 unsigned Unaligned : 1; 5065 5066 enum { 5067 LDREX_B = (1 << 0), /// byte (8-bit) 5068 LDREX_H = (1 << 1), /// half (16-bit) 5069 LDREX_W = (1 << 2), /// word (32-bit) 5070 LDREX_D = (1 << 3), /// double (64-bit) 5071 }; 5072 5073 uint32_t LDREX; 5074 5075 // ACLE 6.5.1 Hardware floating point 5076 enum { 5077 HW_FP_HP = (1 << 1), /// half (16-bit) 5078 HW_FP_SP = (1 << 2), /// single (32-bit) 5079 HW_FP_DP = (1 << 3), /// double (64-bit) 5080 }; 5081 uint32_t HW_FP; 5082 5083 static const Builtin::Info BuiltinInfo[]; 5084 5085 void setABIAAPCS() { 5086 IsAAPCS = true; 5087 5088 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5089 const llvm::Triple &T = getTriple(); 5090 5091 // size_t is unsigned long on MachO-derived environments, NetBSD, 5092 // OpenBSD and Bitrig. 5093 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 5094 T.getOS() == llvm::Triple::OpenBSD || 5095 T.getOS() == llvm::Triple::Bitrig) 5096 SizeType = UnsignedLong; 5097 else 5098 SizeType = UnsignedInt; 5099 5100 switch (T.getOS()) { 5101 case llvm::Triple::NetBSD: 5102 case llvm::Triple::OpenBSD: 5103 WCharType = SignedInt; 5104 break; 5105 case llvm::Triple::Win32: 5106 WCharType = UnsignedShort; 5107 break; 5108 case llvm::Triple::Linux: 5109 default: 5110 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 5111 WCharType = UnsignedInt; 5112 break; 5113 } 5114 5115 UseBitFieldTypeAlignment = true; 5116 5117 ZeroLengthBitfieldBoundary = 0; 5118 5119 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 5120 // so set preferred for small types to 32. 5121 if (T.isOSBinFormatMachO()) { 5122 resetDataLayout(BigEndian 5123 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5124 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5125 } else if (T.isOSWindows()) { 5126 assert(!BigEndian && "Windows on ARM does not support big endian"); 5127 resetDataLayout("e" 5128 "-m:w" 5129 "-p:32:32" 5130 "-i64:64" 5131 "-v128:64:128" 5132 "-a:0:32" 5133 "-n32" 5134 "-S64"); 5135 } else if (T.isOSNaCl()) { 5136 assert(!BigEndian && "NaCl on ARM does not support big endian"); 5137 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 5138 } else { 5139 resetDataLayout(BigEndian 5140 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5141 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5142 } 5143 5144 // FIXME: Enumerated types are variable width in straight AAPCS. 5145 } 5146 5147 void setABIAPCS(bool IsAAPCS16) { 5148 const llvm::Triple &T = getTriple(); 5149 5150 IsAAPCS = false; 5151 5152 if (IsAAPCS16) 5153 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5154 else 5155 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 5156 5157 // size_t is unsigned int on FreeBSD. 5158 if (T.getOS() == llvm::Triple::FreeBSD) 5159 SizeType = UnsignedInt; 5160 else 5161 SizeType = UnsignedLong; 5162 5163 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 5164 WCharType = SignedInt; 5165 5166 // Do not respect the alignment of bit-field types when laying out 5167 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 5168 UseBitFieldTypeAlignment = false; 5169 5170 /// gcc forces the alignment to 4 bytes, regardless of the type of the 5171 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 5172 /// gcc. 5173 ZeroLengthBitfieldBoundary = 32; 5174 5175 if (T.isOSBinFormatMachO() && IsAAPCS16) { 5176 assert(!BigEndian && "AAPCS16 does not support big-endian"); 5177 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 5178 } else if (T.isOSBinFormatMachO()) 5179 resetDataLayout( 5180 BigEndian 5181 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5182 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5183 else 5184 resetDataLayout( 5185 BigEndian 5186 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5187 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5188 5189 // FIXME: Override "preferred align" for double and long long. 5190 } 5191 5192 void setArchInfo() { 5193 StringRef ArchName = getTriple().getArchName(); 5194 5195 ArchISA = llvm::ARM::parseArchISA(ArchName); 5196 CPU = llvm::ARM::getDefaultCPU(ArchName); 5197 unsigned AK = llvm::ARM::parseArch(ArchName); 5198 if (AK != llvm::ARM::AK_INVALID) 5199 ArchKind = AK; 5200 setArchInfo(ArchKind); 5201 } 5202 5203 void setArchInfo(unsigned Kind) { 5204 StringRef SubArch; 5205 5206 // cache TargetParser info 5207 ArchKind = Kind; 5208 SubArch = llvm::ARM::getSubArch(ArchKind); 5209 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 5210 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 5211 5212 // cache CPU related strings 5213 CPUAttr = getCPUAttr(); 5214 CPUProfile = getCPUProfile(); 5215 } 5216 5217 void setAtomic() { 5218 // when triple does not specify a sub arch, 5219 // then we are not using inline atomics 5220 bool ShouldUseInlineAtomic = 5221 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 5222 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 5223 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 5224 if (ArchProfile == llvm::ARM::PK_M) { 5225 MaxAtomicPromoteWidth = 32; 5226 if (ShouldUseInlineAtomic) 5227 MaxAtomicInlineWidth = 32; 5228 } 5229 else { 5230 MaxAtomicPromoteWidth = 64; 5231 if (ShouldUseInlineAtomic) 5232 MaxAtomicInlineWidth = 64; 5233 } 5234 } 5235 5236 bool isThumb() const { 5237 return (ArchISA == llvm::ARM::IK_THUMB); 5238 } 5239 5240 bool supportsThumb() const { 5241 return CPUAttr.count('T') || ArchVersion >= 6; 5242 } 5243 5244 bool supportsThumb2() const { 5245 return CPUAttr.equals("6T2") || 5246 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 5247 } 5248 5249 StringRef getCPUAttr() const { 5250 // For most sub-arches, the build attribute CPU name is enough. 5251 // For Cortex variants, it's slightly different. 5252 switch(ArchKind) { 5253 default: 5254 return llvm::ARM::getCPUAttr(ArchKind); 5255 case llvm::ARM::AK_ARMV6M: 5256 return "6M"; 5257 case llvm::ARM::AK_ARMV7S: 5258 return "7S"; 5259 case llvm::ARM::AK_ARMV7A: 5260 return "7A"; 5261 case llvm::ARM::AK_ARMV7R: 5262 return "7R"; 5263 case llvm::ARM::AK_ARMV7M: 5264 return "7M"; 5265 case llvm::ARM::AK_ARMV7EM: 5266 return "7EM"; 5267 case llvm::ARM::AK_ARMV7VE: 5268 return "7VE"; 5269 case llvm::ARM::AK_ARMV8A: 5270 return "8A"; 5271 case llvm::ARM::AK_ARMV8_1A: 5272 return "8_1A"; 5273 case llvm::ARM::AK_ARMV8_2A: 5274 return "8_2A"; 5275 case llvm::ARM::AK_ARMV8MBaseline: 5276 return "8M_BASE"; 5277 case llvm::ARM::AK_ARMV8MMainline: 5278 return "8M_MAIN"; 5279 case llvm::ARM::AK_ARMV8R: 5280 return "8R"; 5281 } 5282 } 5283 5284 StringRef getCPUProfile() const { 5285 switch(ArchProfile) { 5286 case llvm::ARM::PK_A: 5287 return "A"; 5288 case llvm::ARM::PK_R: 5289 return "R"; 5290 case llvm::ARM::PK_M: 5291 return "M"; 5292 default: 5293 return ""; 5294 } 5295 } 5296 5297 public: 5298 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5299 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 5300 HW_FP(0) { 5301 5302 switch (getTriple().getOS()) { 5303 case llvm::Triple::NetBSD: 5304 case llvm::Triple::OpenBSD: 5305 PtrDiffType = SignedLong; 5306 break; 5307 default: 5308 PtrDiffType = SignedInt; 5309 break; 5310 } 5311 5312 // Cache arch related info. 5313 setArchInfo(); 5314 5315 // {} in inline assembly are neon specifiers, not assembly variant 5316 // specifiers. 5317 NoAsmVariants = true; 5318 5319 // FIXME: This duplicates code from the driver that sets the -target-abi 5320 // option - this code is used if -target-abi isn't passed and should 5321 // be unified in some way. 5322 if (Triple.isOSBinFormatMachO()) { 5323 // The backend is hardwired to assume AAPCS for M-class processors, ensure 5324 // the frontend matches that. 5325 if (Triple.getEnvironment() == llvm::Triple::EABI || 5326 Triple.getOS() == llvm::Triple::UnknownOS || 5327 ArchProfile == llvm::ARM::PK_M) { 5328 setABI("aapcs"); 5329 } else if (Triple.isWatchABI()) { 5330 setABI("aapcs16"); 5331 } else { 5332 setABI("apcs-gnu"); 5333 } 5334 } else if (Triple.isOSWindows()) { 5335 // FIXME: this is invalid for WindowsCE 5336 setABI("aapcs"); 5337 } else { 5338 // Select the default based on the platform. 5339 switch (Triple.getEnvironment()) { 5340 case llvm::Triple::Android: 5341 case llvm::Triple::GNUEABI: 5342 case llvm::Triple::GNUEABIHF: 5343 case llvm::Triple::MuslEABI: 5344 case llvm::Triple::MuslEABIHF: 5345 setABI("aapcs-linux"); 5346 break; 5347 case llvm::Triple::EABIHF: 5348 case llvm::Triple::EABI: 5349 setABI("aapcs"); 5350 break; 5351 case llvm::Triple::GNU: 5352 setABI("apcs-gnu"); 5353 break; 5354 default: 5355 if (Triple.getOS() == llvm::Triple::NetBSD) 5356 setABI("apcs-gnu"); 5357 else if (Triple.getOS() == llvm::Triple::OpenBSD) 5358 setABI("aapcs-linux"); 5359 else 5360 setABI("aapcs"); 5361 break; 5362 } 5363 } 5364 5365 // ARM targets default to using the ARM C++ ABI. 5366 TheCXXABI.set(TargetCXXABI::GenericARM); 5367 5368 // ARM has atomics up to 8 bytes 5369 setAtomic(); 5370 5371 // Do force alignment of members that follow zero length bitfields. If 5372 // the alignment of the zero-length bitfield is greater than the member 5373 // that follows it, `bar', `bar' will be aligned as the type of the 5374 // zero length bitfield. 5375 UseZeroLengthBitfieldAlignment = true; 5376 5377 if (Triple.getOS() == llvm::Triple::Linux || 5378 Triple.getOS() == llvm::Triple::UnknownOS) 5379 this->MCountName = 5380 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 5381 } 5382 5383 StringRef getABI() const override { return ABI; } 5384 5385 bool setABI(const std::string &Name) override { 5386 ABI = Name; 5387 5388 // The defaults (above) are for AAPCS, check if we need to change them. 5389 // 5390 // FIXME: We need support for -meabi... we could just mangle it into the 5391 // name. 5392 if (Name == "apcs-gnu" || Name == "aapcs16") { 5393 setABIAPCS(Name == "aapcs16"); 5394 return true; 5395 } 5396 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 5397 setABIAAPCS(); 5398 return true; 5399 } 5400 return false; 5401 } 5402 5403 // FIXME: This should be based on Arch attributes, not CPU names. 5404 bool 5405 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5406 StringRef CPU, 5407 const std::vector<std::string> &FeaturesVec) const override { 5408 5409 std::vector<StringRef> TargetFeatures; 5410 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 5411 5412 // get default FPU features 5413 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 5414 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 5415 5416 // get default Extension features 5417 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 5418 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 5419 5420 for (auto Feature : TargetFeatures) 5421 if (Feature[0] == '+') 5422 Features[Feature.drop_front(1)] = true; 5423 5424 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5425 } 5426 5427 bool handleTargetFeatures(std::vector<std::string> &Features, 5428 DiagnosticsEngine &Diags) override { 5429 FPU = 0; 5430 CRC = 0; 5431 Crypto = 0; 5432 DSP = 0; 5433 Unaligned = 1; 5434 SoftFloat = SoftFloatABI = false; 5435 HWDiv = 0; 5436 5437 // This does not diagnose illegal cases like having both 5438 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5439 uint32_t HW_FP_remove = 0; 5440 for (const auto &Feature : Features) { 5441 if (Feature == "+soft-float") { 5442 SoftFloat = true; 5443 } else if (Feature == "+soft-float-abi") { 5444 SoftFloatABI = true; 5445 } else if (Feature == "+vfp2") { 5446 FPU |= VFP2FPU; 5447 HW_FP |= HW_FP_SP | HW_FP_DP; 5448 } else if (Feature == "+vfp3") { 5449 FPU |= VFP3FPU; 5450 HW_FP |= HW_FP_SP | HW_FP_DP; 5451 } else if (Feature == "+vfp4") { 5452 FPU |= VFP4FPU; 5453 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5454 } else if (Feature == "+fp-armv8") { 5455 FPU |= FPARMV8; 5456 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5457 } else if (Feature == "+neon") { 5458 FPU |= NeonFPU; 5459 HW_FP |= HW_FP_SP | HW_FP_DP; 5460 } else if (Feature == "+hwdiv") { 5461 HWDiv |= HWDivThumb; 5462 } else if (Feature == "+hwdiv-arm") { 5463 HWDiv |= HWDivARM; 5464 } else if (Feature == "+crc") { 5465 CRC = 1; 5466 } else if (Feature == "+crypto") { 5467 Crypto = 1; 5468 } else if (Feature == "+dsp") { 5469 DSP = 1; 5470 } else if (Feature == "+fp-only-sp") { 5471 HW_FP_remove |= HW_FP_DP; 5472 } else if (Feature == "+strict-align") { 5473 Unaligned = 0; 5474 } else if (Feature == "+fp16") { 5475 HW_FP |= HW_FP_HP; 5476 } 5477 } 5478 HW_FP &= ~HW_FP_remove; 5479 5480 switch (ArchVersion) { 5481 case 6: 5482 if (ArchProfile == llvm::ARM::PK_M) 5483 LDREX = 0; 5484 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5485 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5486 else 5487 LDREX = LDREX_W; 5488 break; 5489 case 7: 5490 if (ArchProfile == llvm::ARM::PK_M) 5491 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5492 else 5493 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5494 break; 5495 case 8: 5496 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5497 } 5498 5499 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5500 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5501 return false; 5502 } 5503 5504 if (FPMath == FP_Neon) 5505 Features.push_back("+neonfp"); 5506 else if (FPMath == FP_VFP) 5507 Features.push_back("-neonfp"); 5508 5509 // Remove front-end specific options which the backend handles differently. 5510 auto Feature = 5511 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5512 if (Feature != Features.end()) 5513 Features.erase(Feature); 5514 5515 return true; 5516 } 5517 5518 bool hasFeature(StringRef Feature) const override { 5519 return llvm::StringSwitch<bool>(Feature) 5520 .Case("arm", true) 5521 .Case("aarch32", true) 5522 .Case("softfloat", SoftFloat) 5523 .Case("thumb", isThumb()) 5524 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5525 .Case("vfp", FPU && !SoftFloat) 5526 .Case("hwdiv", HWDiv & HWDivThumb) 5527 .Case("hwdiv-arm", HWDiv & HWDivARM) 5528 .Default(false); 5529 } 5530 5531 bool setCPU(const std::string &Name) override { 5532 if (Name != "generic") 5533 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5534 5535 if (ArchKind == llvm::ARM::AK_INVALID) 5536 return false; 5537 setAtomic(); 5538 CPU = Name; 5539 return true; 5540 } 5541 5542 bool setFPMath(StringRef Name) override; 5543 5544 void getTargetDefines(const LangOptions &Opts, 5545 MacroBuilder &Builder) const override { 5546 // Target identification. 5547 Builder.defineMacro("__arm"); 5548 Builder.defineMacro("__arm__"); 5549 // For bare-metal none-eabi. 5550 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5551 (getTriple().getEnvironment() == llvm::Triple::EABI || 5552 getTriple().getEnvironment() == llvm::Triple::EABIHF)) 5553 Builder.defineMacro("__ELF__"); 5554 5555 5556 // Target properties. 5557 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5558 5559 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5560 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5561 if (getTriple().isWatchABI()) 5562 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5563 5564 if (!CPUAttr.empty()) 5565 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5566 5567 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5568 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5569 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5570 5571 if (ArchVersion >= 8) { 5572 // ACLE 6.5.7 Crypto Extension 5573 if (Crypto) 5574 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5575 // ACLE 6.5.8 CRC32 Extension 5576 if (CRC) 5577 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5578 // ACLE 6.5.10 Numeric Maximum and Minimum 5579 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5580 // ACLE 6.5.9 Directed Rounding 5581 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5582 } 5583 5584 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5585 // is not defined for the M-profile. 5586 // NOTE that the default profile is assumed to be 'A' 5587 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5588 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5589 5590 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5591 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5592 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5593 // v7 and v8 architectures excluding v8-M Baseline. 5594 if (supportsThumb2()) 5595 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5596 else if (supportsThumb()) 5597 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5598 5599 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5600 // instruction set such as ARM or Thumb. 5601 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5602 5603 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5604 5605 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5606 if (!CPUProfile.empty()) 5607 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5608 5609 // ACLE 6.4.3 Unaligned access supported in hardware 5610 if (Unaligned) 5611 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5612 5613 // ACLE 6.4.4 LDREX/STREX 5614 if (LDREX) 5615 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5616 5617 // ACLE 6.4.5 CLZ 5618 if (ArchVersion == 5 || 5619 (ArchVersion == 6 && CPUProfile != "M") || 5620 ArchVersion > 6) 5621 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5622 5623 // ACLE 6.5.1 Hardware Floating Point 5624 if (HW_FP) 5625 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5626 5627 // ACLE predefines. 5628 Builder.defineMacro("__ARM_ACLE", "200"); 5629 5630 // FP16 support (we currently only support IEEE format). 5631 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5632 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5633 5634 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5635 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5636 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5637 5638 // Subtarget options. 5639 5640 // FIXME: It's more complicated than this and we don't really support 5641 // interworking. 5642 // Windows on ARM does not "support" interworking 5643 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5644 Builder.defineMacro("__THUMB_INTERWORK__"); 5645 5646 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5647 // Embedded targets on Darwin follow AAPCS, but not EABI. 5648 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5649 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5650 Builder.defineMacro("__ARM_EABI__"); 5651 Builder.defineMacro("__ARM_PCS", "1"); 5652 } 5653 5654 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5655 ABI == "aapcs16") 5656 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5657 5658 if (SoftFloat) 5659 Builder.defineMacro("__SOFTFP__"); 5660 5661 if (ArchKind == llvm::ARM::AK_XSCALE) 5662 Builder.defineMacro("__XSCALE__"); 5663 5664 if (isThumb()) { 5665 Builder.defineMacro("__THUMBEL__"); 5666 Builder.defineMacro("__thumb__"); 5667 if (supportsThumb2()) 5668 Builder.defineMacro("__thumb2__"); 5669 } 5670 5671 // ACLE 6.4.9 32-bit SIMD instructions 5672 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5673 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5674 5675 // ACLE 6.4.10 Hardware Integer Divide 5676 if (((HWDiv & HWDivThumb) && isThumb()) || 5677 ((HWDiv & HWDivARM) && !isThumb())) { 5678 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5679 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5680 } 5681 5682 // Note, this is always on in gcc, even though it doesn't make sense. 5683 Builder.defineMacro("__APCS_32__"); 5684 5685 if (FPUModeIsVFP((FPUMode) FPU)) { 5686 Builder.defineMacro("__VFP_FP__"); 5687 if (FPU & VFP2FPU) 5688 Builder.defineMacro("__ARM_VFPV2__"); 5689 if (FPU & VFP3FPU) 5690 Builder.defineMacro("__ARM_VFPV3__"); 5691 if (FPU & VFP4FPU) 5692 Builder.defineMacro("__ARM_VFPV4__"); 5693 if (FPU & FPARMV8) 5694 Builder.defineMacro("__ARM_FPV5__"); 5695 } 5696 5697 // This only gets set when Neon instructions are actually available, unlike 5698 // the VFP define, hence the soft float and arch check. This is subtly 5699 // different from gcc, we follow the intent which was that it should be set 5700 // when Neon instructions are actually available. 5701 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5702 Builder.defineMacro("__ARM_NEON", "1"); 5703 Builder.defineMacro("__ARM_NEON__"); 5704 // current AArch32 NEON implementations do not support double-precision 5705 // floating-point even when it is present in VFP. 5706 Builder.defineMacro("__ARM_NEON_FP", 5707 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5708 } 5709 5710 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5711 Opts.ShortWChar ? "2" : "4"); 5712 5713 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5714 Opts.ShortEnums ? "1" : "4"); 5715 5716 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5717 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5718 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5719 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5720 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5721 } 5722 5723 // ACLE 6.4.7 DSP instructions 5724 if (DSP) { 5725 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5726 } 5727 5728 // ACLE 6.4.8 Saturation instructions 5729 bool SAT = false; 5730 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5731 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5732 SAT = true; 5733 } 5734 5735 // ACLE 6.4.6 Q (saturation) flag 5736 if (DSP || SAT) 5737 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5738 5739 if (Opts.UnsafeFPMath) 5740 Builder.defineMacro("__ARM_FP_FAST", "1"); 5741 5742 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5743 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5744 } 5745 5746 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5747 return llvm::makeArrayRef(BuiltinInfo, 5748 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5749 } 5750 bool isCLZForZeroUndef() const override { return false; } 5751 BuiltinVaListKind getBuiltinVaListKind() const override { 5752 return IsAAPCS 5753 ? AAPCSABIBuiltinVaList 5754 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5755 : TargetInfo::VoidPtrBuiltinVaList); 5756 } 5757 ArrayRef<const char *> getGCCRegNames() const override; 5758 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5759 bool validateAsmConstraint(const char *&Name, 5760 TargetInfo::ConstraintInfo &Info) const override { 5761 switch (*Name) { 5762 default: break; 5763 case 'l': // r0-r7 5764 case 'h': // r8-r15 5765 case 't': // VFP Floating point register single precision 5766 case 'w': // VFP Floating point register double precision 5767 Info.setAllowsRegister(); 5768 return true; 5769 case 'I': 5770 case 'J': 5771 case 'K': 5772 case 'L': 5773 case 'M': 5774 // FIXME 5775 return true; 5776 case 'Q': // A memory address that is a single base register. 5777 Info.setAllowsMemory(); 5778 return true; 5779 case 'U': // a memory reference... 5780 switch (Name[1]) { 5781 case 'q': // ...ARMV4 ldrsb 5782 case 'v': // ...VFP load/store (reg+constant offset) 5783 case 'y': // ...iWMMXt load/store 5784 case 't': // address valid for load/store opaque types wider 5785 // than 128-bits 5786 case 'n': // valid address for Neon doubleword vector load/store 5787 case 'm': // valid address for Neon element and structure load/store 5788 case 's': // valid address for non-offset loads/stores of quad-word 5789 // values in four ARM registers 5790 Info.setAllowsMemory(); 5791 Name++; 5792 return true; 5793 } 5794 } 5795 return false; 5796 } 5797 std::string convertConstraint(const char *&Constraint) const override { 5798 std::string R; 5799 switch (*Constraint) { 5800 case 'U': // Two-character constraint; add "^" hint for later parsing. 5801 R = std::string("^") + std::string(Constraint, 2); 5802 Constraint++; 5803 break; 5804 case 'p': // 'p' should be translated to 'r' by default. 5805 R = std::string("r"); 5806 break; 5807 default: 5808 return std::string(1, *Constraint); 5809 } 5810 return R; 5811 } 5812 bool 5813 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5814 std::string &SuggestedModifier) const override { 5815 bool isOutput = (Constraint[0] == '='); 5816 bool isInOut = (Constraint[0] == '+'); 5817 5818 // Strip off constraint modifiers. 5819 while (Constraint[0] == '=' || 5820 Constraint[0] == '+' || 5821 Constraint[0] == '&') 5822 Constraint = Constraint.substr(1); 5823 5824 switch (Constraint[0]) { 5825 default: break; 5826 case 'r': { 5827 switch (Modifier) { 5828 default: 5829 return (isInOut || isOutput || Size <= 64); 5830 case 'q': 5831 // A register of size 32 cannot fit a vector type. 5832 return false; 5833 } 5834 } 5835 } 5836 5837 return true; 5838 } 5839 const char *getClobbers() const override { 5840 // FIXME: Is this really right? 5841 return ""; 5842 } 5843 5844 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5845 switch (CC) { 5846 case CC_AAPCS: 5847 case CC_AAPCS_VFP: 5848 case CC_Swift: 5849 return CCCR_OK; 5850 default: 5851 return CCCR_Warning; 5852 } 5853 } 5854 5855 int getEHDataRegisterNumber(unsigned RegNo) const override { 5856 if (RegNo == 0) return 0; 5857 if (RegNo == 1) return 1; 5858 return -1; 5859 } 5860 5861 bool hasSjLjLowering() const override { 5862 return true; 5863 } 5864 }; 5865 5866 bool ARMTargetInfo::setFPMath(StringRef Name) { 5867 if (Name == "neon") { 5868 FPMath = FP_Neon; 5869 return true; 5870 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5871 Name == "vfp4") { 5872 FPMath = FP_VFP; 5873 return true; 5874 } 5875 return false; 5876 } 5877 5878 const char * const ARMTargetInfo::GCCRegNames[] = { 5879 // Integer registers 5880 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5881 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5882 5883 // Float registers 5884 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5885 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5886 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5887 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5888 5889 // Double registers 5890 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5891 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5892 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5893 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5894 5895 // Quad registers 5896 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5897 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5898 }; 5899 5900 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5901 return llvm::makeArrayRef(GCCRegNames); 5902 } 5903 5904 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5905 { { "a1" }, "r0" }, 5906 { { "a2" }, "r1" }, 5907 { { "a3" }, "r2" }, 5908 { { "a4" }, "r3" }, 5909 { { "v1" }, "r4" }, 5910 { { "v2" }, "r5" }, 5911 { { "v3" }, "r6" }, 5912 { { "v4" }, "r7" }, 5913 { { "v5" }, "r8" }, 5914 { { "v6", "rfp" }, "r9" }, 5915 { { "sl" }, "r10" }, 5916 { { "fp" }, "r11" }, 5917 { { "ip" }, "r12" }, 5918 { { "r13" }, "sp" }, 5919 { { "r14" }, "lr" }, 5920 { { "r15" }, "pc" }, 5921 // The S, D and Q registers overlap, but aren't really aliases; we 5922 // don't want to substitute one of these for a different-sized one. 5923 }; 5924 5925 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5926 return llvm::makeArrayRef(GCCRegAliases); 5927 } 5928 5929 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5930 #define BUILTIN(ID, TYPE, ATTRS) \ 5931 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5932 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5933 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5934 #include "clang/Basic/BuiltinsNEON.def" 5935 5936 #define BUILTIN(ID, TYPE, ATTRS) \ 5937 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5938 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5939 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5940 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5941 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5942 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 5943 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 5944 #include "clang/Basic/BuiltinsARM.def" 5945 }; 5946 5947 class ARMleTargetInfo : public ARMTargetInfo { 5948 public: 5949 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5950 : ARMTargetInfo(Triple, Opts) {} 5951 void getTargetDefines(const LangOptions &Opts, 5952 MacroBuilder &Builder) const override { 5953 Builder.defineMacro("__ARMEL__"); 5954 ARMTargetInfo::getTargetDefines(Opts, Builder); 5955 } 5956 }; 5957 5958 class ARMbeTargetInfo : public ARMTargetInfo { 5959 public: 5960 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5961 : ARMTargetInfo(Triple, Opts) {} 5962 void getTargetDefines(const LangOptions &Opts, 5963 MacroBuilder &Builder) const override { 5964 Builder.defineMacro("__ARMEB__"); 5965 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5966 ARMTargetInfo::getTargetDefines(Opts, Builder); 5967 } 5968 }; 5969 5970 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5971 const llvm::Triple Triple; 5972 public: 5973 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5974 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5975 WCharType = UnsignedShort; 5976 SizeType = UnsignedInt; 5977 } 5978 void getVisualStudioDefines(const LangOptions &Opts, 5979 MacroBuilder &Builder) const { 5980 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5981 5982 // FIXME: this is invalid for WindowsCE 5983 Builder.defineMacro("_M_ARM_NT", "1"); 5984 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5985 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5986 5987 assert((Triple.getArch() == llvm::Triple::arm || 5988 Triple.getArch() == llvm::Triple::thumb) && 5989 "invalid architecture for Windows ARM target info"); 5990 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5991 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5992 5993 // TODO map the complete set of values 5994 // 31: VFPv3 40: VFPv4 5995 Builder.defineMacro("_M_ARM_FP", "31"); 5996 } 5997 BuiltinVaListKind getBuiltinVaListKind() const override { 5998 return TargetInfo::CharPtrBuiltinVaList; 5999 } 6000 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6001 switch (CC) { 6002 case CC_X86StdCall: 6003 case CC_X86ThisCall: 6004 case CC_X86FastCall: 6005 case CC_X86VectorCall: 6006 return CCCR_Ignore; 6007 case CC_C: 6008 return CCCR_OK; 6009 default: 6010 return CCCR_Warning; 6011 } 6012 } 6013 }; 6014 6015 // Windows ARM + Itanium C++ ABI Target 6016 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 6017 public: 6018 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 6019 const TargetOptions &Opts) 6020 : WindowsARMTargetInfo(Triple, Opts) { 6021 TheCXXABI.set(TargetCXXABI::GenericARM); 6022 } 6023 6024 void getTargetDefines(const LangOptions &Opts, 6025 MacroBuilder &Builder) const override { 6026 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6027 6028 if (Opts.MSVCCompat) 6029 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 6030 } 6031 }; 6032 6033 // Windows ARM, MS (C++) ABI 6034 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 6035 public: 6036 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 6037 const TargetOptions &Opts) 6038 : WindowsARMTargetInfo(Triple, Opts) { 6039 TheCXXABI.set(TargetCXXABI::Microsoft); 6040 } 6041 6042 void getTargetDefines(const LangOptions &Opts, 6043 MacroBuilder &Builder) const override { 6044 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6045 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 6046 } 6047 }; 6048 6049 // ARM MinGW target 6050 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 6051 public: 6052 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6053 : WindowsARMTargetInfo(Triple, Opts) { 6054 TheCXXABI.set(TargetCXXABI::GenericARM); 6055 } 6056 6057 void getTargetDefines(const LangOptions &Opts, 6058 MacroBuilder &Builder) const override { 6059 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6060 DefineStd(Builder, "WIN32", Opts); 6061 DefineStd(Builder, "WINNT", Opts); 6062 Builder.defineMacro("_ARM_"); 6063 addMinGWDefines(Opts, Builder); 6064 } 6065 }; 6066 6067 // ARM Cygwin target 6068 class CygwinARMTargetInfo : public ARMleTargetInfo { 6069 public: 6070 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6071 : ARMleTargetInfo(Triple, Opts) { 6072 TLSSupported = false; 6073 WCharType = UnsignedShort; 6074 DoubleAlign = LongLongAlign = 64; 6075 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 6076 } 6077 void getTargetDefines(const LangOptions &Opts, 6078 MacroBuilder &Builder) const override { 6079 ARMleTargetInfo::getTargetDefines(Opts, Builder); 6080 Builder.defineMacro("_ARM_"); 6081 Builder.defineMacro("__CYGWIN__"); 6082 Builder.defineMacro("__CYGWIN32__"); 6083 DefineStd(Builder, "unix", Opts); 6084 if (Opts.CPlusPlus) 6085 Builder.defineMacro("_GNU_SOURCE"); 6086 } 6087 }; 6088 6089 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 6090 protected: 6091 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6092 MacroBuilder &Builder) const override { 6093 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6094 } 6095 6096 public: 6097 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6098 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 6099 HasAlignMac68kSupport = true; 6100 // iOS always has 64-bit atomic instructions. 6101 // FIXME: This should be based off of the target features in 6102 // ARMleTargetInfo. 6103 MaxAtomicInlineWidth = 64; 6104 6105 if (Triple.isWatchABI()) { 6106 // Darwin on iOS uses a variant of the ARM C++ ABI. 6107 TheCXXABI.set(TargetCXXABI::WatchOS); 6108 6109 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 6110 // size_t is long, it's a bit weird for it to be int. 6111 PtrDiffType = SignedLong; 6112 6113 // BOOL should be a real boolean on the new ABI 6114 UseSignedCharForObjCBool = false; 6115 } else 6116 TheCXXABI.set(TargetCXXABI::iOS); 6117 } 6118 }; 6119 6120 class AArch64TargetInfo : public TargetInfo { 6121 virtual void setDataLayout() = 0; 6122 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6123 static const char *const GCCRegNames[]; 6124 6125 enum FPUModeEnum { 6126 FPUMode, 6127 NeonMode 6128 }; 6129 6130 unsigned FPU; 6131 unsigned CRC; 6132 unsigned Crypto; 6133 unsigned Unaligned; 6134 unsigned V8_1A; 6135 6136 static const Builtin::Info BuiltinInfo[]; 6137 6138 std::string ABI; 6139 6140 public: 6141 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6142 : TargetInfo(Triple), ABI("aapcs") { 6143 if (getTriple().getOS() == llvm::Triple::NetBSD || 6144 getTriple().getOS() == llvm::Triple::OpenBSD) { 6145 WCharType = SignedInt; 6146 6147 // NetBSD apparently prefers consistency across ARM targets to consistency 6148 // across 64-bit targets. 6149 Int64Type = SignedLongLong; 6150 IntMaxType = SignedLongLong; 6151 } else { 6152 WCharType = UnsignedInt; 6153 Int64Type = SignedLong; 6154 IntMaxType = SignedLong; 6155 } 6156 6157 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6158 MaxVectorAlign = 128; 6159 MaxAtomicInlineWidth = 128; 6160 MaxAtomicPromoteWidth = 128; 6161 6162 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 6163 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 6164 6165 // {} in inline assembly are neon specifiers, not assembly variant 6166 // specifiers. 6167 NoAsmVariants = true; 6168 6169 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 6170 // contributes to the alignment of the containing aggregate in the same way 6171 // a plain (non bit-field) member of that type would, without exception for 6172 // zero-sized or anonymous bit-fields." 6173 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 6174 UseZeroLengthBitfieldAlignment = true; 6175 6176 // AArch64 targets default to using the ARM C++ ABI. 6177 TheCXXABI.set(TargetCXXABI::GenericAArch64); 6178 6179 if (Triple.getOS() == llvm::Triple::Linux) 6180 this->MCountName = "\01_mcount"; 6181 else if (Triple.getOS() == llvm::Triple::UnknownOS) 6182 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 6183 } 6184 6185 StringRef getABI() const override { return ABI; } 6186 bool setABI(const std::string &Name) override { 6187 if (Name != "aapcs" && Name != "darwinpcs") 6188 return false; 6189 6190 ABI = Name; 6191 return true; 6192 } 6193 6194 bool setCPU(const std::string &Name) override { 6195 return Name == "generic" || 6196 llvm::AArch64::parseCPUArch(Name) != 6197 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 6198 } 6199 6200 void getTargetDefines(const LangOptions &Opts, 6201 MacroBuilder &Builder) const override { 6202 // Target identification. 6203 Builder.defineMacro("__aarch64__"); 6204 // For bare-metal none-eabi. 6205 if (getTriple().getOS() == llvm::Triple::UnknownOS && 6206 (getTriple().getEnvironment() == llvm::Triple::EABI || 6207 getTriple().getEnvironment() == llvm::Triple::EABIHF)) 6208 Builder.defineMacro("__ELF__"); 6209 6210 // Target properties. 6211 Builder.defineMacro("_LP64"); 6212 Builder.defineMacro("__LP64__"); 6213 6214 // ACLE predefines. Many can only have one possible value on v8 AArch64. 6215 Builder.defineMacro("__ARM_ACLE", "200"); 6216 Builder.defineMacro("__ARM_ARCH", "8"); 6217 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 6218 6219 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 6220 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 6221 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 6222 6223 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 6224 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 6225 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 6226 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 6227 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 6228 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 6229 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 6230 6231 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 6232 6233 // 0xe implies support for half, single and double precision operations. 6234 Builder.defineMacro("__ARM_FP", "0xE"); 6235 6236 // PCS specifies this for SysV variants, which is all we support. Other ABIs 6237 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 6238 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 6239 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 6240 6241 if (Opts.UnsafeFPMath) 6242 Builder.defineMacro("__ARM_FP_FAST", "1"); 6243 6244 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 6245 6246 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 6247 Opts.ShortEnums ? "1" : "4"); 6248 6249 if (FPU == NeonMode) { 6250 Builder.defineMacro("__ARM_NEON", "1"); 6251 // 64-bit NEON supports half, single and double precision operations. 6252 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 6253 } 6254 6255 if (CRC) 6256 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 6257 6258 if (Crypto) 6259 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 6260 6261 if (Unaligned) 6262 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 6263 6264 if (V8_1A) 6265 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 6266 6267 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 6268 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6269 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6270 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6271 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6272 } 6273 6274 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6275 return llvm::makeArrayRef(BuiltinInfo, 6276 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 6277 } 6278 6279 bool hasFeature(StringRef Feature) const override { 6280 return Feature == "aarch64" || 6281 Feature == "arm64" || 6282 Feature == "arm" || 6283 (Feature == "neon" && FPU == NeonMode); 6284 } 6285 6286 bool handleTargetFeatures(std::vector<std::string> &Features, 6287 DiagnosticsEngine &Diags) override { 6288 FPU = FPUMode; 6289 CRC = 0; 6290 Crypto = 0; 6291 Unaligned = 1; 6292 V8_1A = 0; 6293 6294 for (const auto &Feature : Features) { 6295 if (Feature == "+neon") 6296 FPU = NeonMode; 6297 if (Feature == "+crc") 6298 CRC = 1; 6299 if (Feature == "+crypto") 6300 Crypto = 1; 6301 if (Feature == "+strict-align") 6302 Unaligned = 0; 6303 if (Feature == "+v8.1a") 6304 V8_1A = 1; 6305 } 6306 6307 setDataLayout(); 6308 6309 return true; 6310 } 6311 6312 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6313 switch (CC) { 6314 case CC_C: 6315 case CC_Swift: 6316 case CC_PreserveMost: 6317 case CC_PreserveAll: 6318 return CCCR_OK; 6319 default: 6320 return CCCR_Warning; 6321 } 6322 } 6323 6324 bool isCLZForZeroUndef() const override { return false; } 6325 6326 BuiltinVaListKind getBuiltinVaListKind() const override { 6327 return TargetInfo::AArch64ABIBuiltinVaList; 6328 } 6329 6330 ArrayRef<const char *> getGCCRegNames() const override; 6331 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6332 6333 bool validateAsmConstraint(const char *&Name, 6334 TargetInfo::ConstraintInfo &Info) const override { 6335 switch (*Name) { 6336 default: 6337 return false; 6338 case 'w': // Floating point and SIMD registers (V0-V31) 6339 Info.setAllowsRegister(); 6340 return true; 6341 case 'I': // Constant that can be used with an ADD instruction 6342 case 'J': // Constant that can be used with a SUB instruction 6343 case 'K': // Constant that can be used with a 32-bit logical instruction 6344 case 'L': // Constant that can be used with a 64-bit logical instruction 6345 case 'M': // Constant that can be used as a 32-bit MOV immediate 6346 case 'N': // Constant that can be used as a 64-bit MOV immediate 6347 case 'Y': // Floating point constant zero 6348 case 'Z': // Integer constant zero 6349 return true; 6350 case 'Q': // A memory reference with base register and no offset 6351 Info.setAllowsMemory(); 6352 return true; 6353 case 'S': // A symbolic address 6354 Info.setAllowsRegister(); 6355 return true; 6356 case 'U': 6357 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 6358 // Utf: A memory address suitable for ldp/stp in TF mode. 6359 // Usa: An absolute symbolic address. 6360 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 6361 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 6362 case 'z': // Zero register, wzr or xzr 6363 Info.setAllowsRegister(); 6364 return true; 6365 case 'x': // Floating point and SIMD registers (V0-V15) 6366 Info.setAllowsRegister(); 6367 return true; 6368 } 6369 return false; 6370 } 6371 6372 bool 6373 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 6374 std::string &SuggestedModifier) const override { 6375 // Strip off constraint modifiers. 6376 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 6377 Constraint = Constraint.substr(1); 6378 6379 switch (Constraint[0]) { 6380 default: 6381 return true; 6382 case 'z': 6383 case 'r': { 6384 switch (Modifier) { 6385 case 'x': 6386 case 'w': 6387 // For now assume that the person knows what they're 6388 // doing with the modifier. 6389 return true; 6390 default: 6391 // By default an 'r' constraint will be in the 'x' 6392 // registers. 6393 if (Size == 64) 6394 return true; 6395 6396 SuggestedModifier = "w"; 6397 return false; 6398 } 6399 } 6400 } 6401 } 6402 6403 const char *getClobbers() const override { return ""; } 6404 6405 int getEHDataRegisterNumber(unsigned RegNo) const override { 6406 if (RegNo == 0) 6407 return 0; 6408 if (RegNo == 1) 6409 return 1; 6410 return -1; 6411 } 6412 }; 6413 6414 const char *const AArch64TargetInfo::GCCRegNames[] = { 6415 // 32-bit Integer registers 6416 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 6417 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 6418 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 6419 6420 // 64-bit Integer registers 6421 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 6422 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 6423 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 6424 6425 // 32-bit floating point regsisters 6426 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 6427 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 6428 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6429 6430 // 64-bit floating point regsisters 6431 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 6432 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 6433 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6434 6435 // Vector registers 6436 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6437 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6438 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6439 }; 6440 6441 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6442 return llvm::makeArrayRef(GCCRegNames); 6443 } 6444 6445 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6446 { { "w31" }, "wsp" }, 6447 { { "x29" }, "fp" }, 6448 { { "x30" }, "lr" }, 6449 { { "x31" }, "sp" }, 6450 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6451 // don't want to substitute one of these for a different-sized one. 6452 }; 6453 6454 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6455 return llvm::makeArrayRef(GCCRegAliases); 6456 } 6457 6458 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6459 #define BUILTIN(ID, TYPE, ATTRS) \ 6460 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6461 #include "clang/Basic/BuiltinsNEON.def" 6462 6463 #define BUILTIN(ID, TYPE, ATTRS) \ 6464 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6465 #include "clang/Basic/BuiltinsAArch64.def" 6466 }; 6467 6468 class AArch64leTargetInfo : public AArch64TargetInfo { 6469 void setDataLayout() override { 6470 if (getTriple().isOSBinFormatMachO()) 6471 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6472 else 6473 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6474 } 6475 6476 public: 6477 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6478 : AArch64TargetInfo(Triple, Opts) { 6479 } 6480 void getTargetDefines(const LangOptions &Opts, 6481 MacroBuilder &Builder) const override { 6482 Builder.defineMacro("__AARCH64EL__"); 6483 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6484 } 6485 }; 6486 6487 class AArch64beTargetInfo : public AArch64TargetInfo { 6488 void setDataLayout() override { 6489 assert(!getTriple().isOSBinFormatMachO()); 6490 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6491 } 6492 6493 public: 6494 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6495 : AArch64TargetInfo(Triple, Opts) {} 6496 void getTargetDefines(const LangOptions &Opts, 6497 MacroBuilder &Builder) const override { 6498 Builder.defineMacro("__AARCH64EB__"); 6499 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6500 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6501 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6502 } 6503 }; 6504 6505 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6506 protected: 6507 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6508 MacroBuilder &Builder) const override { 6509 Builder.defineMacro("__AARCH64_SIMD__"); 6510 Builder.defineMacro("__ARM64_ARCH_8__"); 6511 Builder.defineMacro("__ARM_NEON__"); 6512 Builder.defineMacro("__LITTLE_ENDIAN__"); 6513 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6514 Builder.defineMacro("__arm64", "1"); 6515 Builder.defineMacro("__arm64__", "1"); 6516 6517 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6518 } 6519 6520 public: 6521 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6522 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6523 Int64Type = SignedLongLong; 6524 WCharType = SignedInt; 6525 UseSignedCharForObjCBool = false; 6526 6527 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6528 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 6529 6530 TheCXXABI.set(TargetCXXABI::iOS64); 6531 } 6532 6533 BuiltinVaListKind getBuiltinVaListKind() const override { 6534 return TargetInfo::CharPtrBuiltinVaList; 6535 } 6536 }; 6537 6538 // Hexagon abstract base class 6539 class HexagonTargetInfo : public TargetInfo { 6540 static const Builtin::Info BuiltinInfo[]; 6541 static const char * const GCCRegNames[]; 6542 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6543 std::string CPU; 6544 bool HasHVX, HasHVXDouble; 6545 bool UseLongCalls; 6546 6547 public: 6548 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6549 : TargetInfo(Triple) { 6550 // Specify the vector alignment explicitly. For v512x1, the calculated 6551 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6552 // the required minimum of 64 bytes. 6553 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6554 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6555 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6556 SizeType = UnsignedInt; 6557 PtrDiffType = SignedInt; 6558 IntPtrType = SignedInt; 6559 6560 // {} in inline assembly are packet specifiers, not assembly variant 6561 // specifiers. 6562 NoAsmVariants = true; 6563 6564 LargeArrayMinWidth = 64; 6565 LargeArrayAlign = 64; 6566 UseBitFieldTypeAlignment = true; 6567 ZeroLengthBitfieldBoundary = 32; 6568 HasHVX = HasHVXDouble = false; 6569 UseLongCalls = false; 6570 } 6571 6572 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6573 return llvm::makeArrayRef(BuiltinInfo, 6574 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6575 } 6576 6577 bool validateAsmConstraint(const char *&Name, 6578 TargetInfo::ConstraintInfo &Info) const override { 6579 switch (*Name) { 6580 case 'v': 6581 case 'q': 6582 if (HasHVX) { 6583 Info.setAllowsRegister(); 6584 return true; 6585 } 6586 break; 6587 case 's': 6588 // Relocatable constant. 6589 return true; 6590 } 6591 return false; 6592 } 6593 6594 void getTargetDefines(const LangOptions &Opts, 6595 MacroBuilder &Builder) const override; 6596 6597 bool isCLZForZeroUndef() const override { return false; } 6598 6599 bool hasFeature(StringRef Feature) const override { 6600 return llvm::StringSwitch<bool>(Feature) 6601 .Case("hexagon", true) 6602 .Case("hvx", HasHVX) 6603 .Case("hvx-double", HasHVXDouble) 6604 .Case("long-calls", UseLongCalls) 6605 .Default(false); 6606 } 6607 6608 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6609 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6610 const override; 6611 6612 bool handleTargetFeatures(std::vector<std::string> &Features, 6613 DiagnosticsEngine &Diags) override; 6614 6615 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6616 bool Enabled) const override; 6617 6618 BuiltinVaListKind getBuiltinVaListKind() const override { 6619 return TargetInfo::CharPtrBuiltinVaList; 6620 } 6621 ArrayRef<const char *> getGCCRegNames() const override; 6622 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6623 const char *getClobbers() const override { 6624 return ""; 6625 } 6626 6627 static const char *getHexagonCPUSuffix(StringRef Name) { 6628 return llvm::StringSwitch<const char*>(Name) 6629 .Case("hexagonv4", "4") 6630 .Case("hexagonv5", "5") 6631 .Case("hexagonv55", "55") 6632 .Case("hexagonv60", "60") 6633 .Case("hexagonv62", "62") 6634 .Default(nullptr); 6635 } 6636 6637 bool setCPU(const std::string &Name) override { 6638 if (!getHexagonCPUSuffix(Name)) 6639 return false; 6640 CPU = Name; 6641 return true; 6642 } 6643 6644 int getEHDataRegisterNumber(unsigned RegNo) const override { 6645 return RegNo < 2 ? RegNo : -1; 6646 } 6647 }; 6648 6649 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6650 MacroBuilder &Builder) const { 6651 Builder.defineMacro("__qdsp6__", "1"); 6652 Builder.defineMacro("__hexagon__", "1"); 6653 6654 if (CPU == "hexagonv4") { 6655 Builder.defineMacro("__HEXAGON_V4__"); 6656 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6657 if (Opts.HexagonQdsp6Compat) { 6658 Builder.defineMacro("__QDSP6_V4__"); 6659 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6660 } 6661 } else if (CPU == "hexagonv5") { 6662 Builder.defineMacro("__HEXAGON_V5__"); 6663 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6664 if(Opts.HexagonQdsp6Compat) { 6665 Builder.defineMacro("__QDSP6_V5__"); 6666 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6667 } 6668 } else if (CPU == "hexagonv55") { 6669 Builder.defineMacro("__HEXAGON_V55__"); 6670 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6671 Builder.defineMacro("__QDSP6_V55__"); 6672 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6673 } else if (CPU == "hexagonv60") { 6674 Builder.defineMacro("__HEXAGON_V60__"); 6675 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6676 Builder.defineMacro("__QDSP6_V60__"); 6677 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6678 } else if (CPU == "hexagonv62") { 6679 Builder.defineMacro("__HEXAGON_V62__"); 6680 Builder.defineMacro("__HEXAGON_ARCH__", "62"); 6681 } 6682 6683 if (hasFeature("hvx")) { 6684 Builder.defineMacro("__HVX__"); 6685 if (hasFeature("hvx-double")) 6686 Builder.defineMacro("__HVXDBL__"); 6687 } 6688 } 6689 6690 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6691 DiagnosticsEngine &Diags, StringRef CPU, 6692 const std::vector<std::string> &FeaturesVec) const { 6693 // Default for v60: -hvx, -hvx-double. 6694 Features["hvx"] = false; 6695 Features["hvx-double"] = false; 6696 Features["long-calls"] = false; 6697 6698 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6699 } 6700 6701 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6702 DiagnosticsEngine &Diags) { 6703 for (auto &F : Features) { 6704 if (F == "+hvx") 6705 HasHVX = true; 6706 else if (F == "-hvx") 6707 HasHVX = HasHVXDouble = false; 6708 else if (F == "+hvx-double") 6709 HasHVX = HasHVXDouble = true; 6710 else if (F == "-hvx-double") 6711 HasHVXDouble = false; 6712 6713 if (F == "+long-calls") 6714 UseLongCalls = true; 6715 else if (F == "-long-calls") 6716 UseLongCalls = false; 6717 } 6718 return true; 6719 } 6720 6721 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 6722 StringRef Name, bool Enabled) const { 6723 if (Enabled) { 6724 if (Name == "hvx-double") 6725 Features["hvx"] = true; 6726 } else { 6727 if (Name == "hvx") 6728 Features["hvx-double"] = false; 6729 } 6730 Features[Name] = Enabled; 6731 } 6732 6733 const char *const HexagonTargetInfo::GCCRegNames[] = { 6734 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6735 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6736 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6737 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6738 "p0", "p1", "p2", "p3", 6739 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6740 }; 6741 6742 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6743 return llvm::makeArrayRef(GCCRegNames); 6744 } 6745 6746 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6747 { { "sp" }, "r29" }, 6748 { { "fp" }, "r30" }, 6749 { { "lr" }, "r31" }, 6750 }; 6751 6752 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6753 return llvm::makeArrayRef(GCCRegAliases); 6754 } 6755 6756 6757 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6758 #define BUILTIN(ID, TYPE, ATTRS) \ 6759 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6760 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6761 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6762 #include "clang/Basic/BuiltinsHexagon.def" 6763 }; 6764 6765 class LanaiTargetInfo : public TargetInfo { 6766 // Class for Lanai (32-bit). 6767 // The CPU profiles supported by the Lanai backend 6768 enum CPUKind { 6769 CK_NONE, 6770 CK_V11, 6771 } CPU; 6772 6773 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6774 static const char *const GCCRegNames[]; 6775 6776 public: 6777 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6778 : TargetInfo(Triple) { 6779 // Description string has to be kept in sync with backend. 6780 resetDataLayout("E" // Big endian 6781 "-m:e" // ELF name manging 6782 "-p:32:32" // 32 bit pointers, 32 bit aligned 6783 "-i64:64" // 64 bit integers, 64 bit aligned 6784 "-a:0:32" // 32 bit alignment of objects of aggregate type 6785 "-n32" // 32 bit native integer width 6786 "-S64" // 64 bit natural stack alignment 6787 ); 6788 6789 // Setting RegParmMax equal to what mregparm was set to in the old 6790 // toolchain 6791 RegParmMax = 4; 6792 6793 // Set the default CPU to V11 6794 CPU = CK_V11; 6795 6796 // Temporary approach to make everything at least word-aligned and allow for 6797 // safely casting between pointers with different alignment requirements. 6798 // TODO: Remove this when there are no more cast align warnings on the 6799 // firmware. 6800 MinGlobalAlign = 32; 6801 } 6802 6803 void getTargetDefines(const LangOptions &Opts, 6804 MacroBuilder &Builder) const override { 6805 // Define __lanai__ when building for target lanai. 6806 Builder.defineMacro("__lanai__"); 6807 6808 // Set define for the CPU specified. 6809 switch (CPU) { 6810 case CK_V11: 6811 Builder.defineMacro("__LANAI_V11__"); 6812 break; 6813 case CK_NONE: 6814 llvm_unreachable("Unhandled target CPU"); 6815 } 6816 } 6817 6818 bool setCPU(const std::string &Name) override { 6819 CPU = llvm::StringSwitch<CPUKind>(Name) 6820 .Case("v11", CK_V11) 6821 .Default(CK_NONE); 6822 6823 return CPU != CK_NONE; 6824 } 6825 6826 bool hasFeature(StringRef Feature) const override { 6827 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6828 } 6829 6830 ArrayRef<const char *> getGCCRegNames() const override; 6831 6832 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6833 6834 BuiltinVaListKind getBuiltinVaListKind() const override { 6835 return TargetInfo::VoidPtrBuiltinVaList; 6836 } 6837 6838 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6839 6840 bool validateAsmConstraint(const char *&Name, 6841 TargetInfo::ConstraintInfo &info) const override { 6842 return false; 6843 } 6844 6845 const char *getClobbers() const override { return ""; } 6846 }; 6847 6848 const char *const LanaiTargetInfo::GCCRegNames[] = { 6849 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6850 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6851 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6852 6853 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6854 return llvm::makeArrayRef(GCCRegNames); 6855 } 6856 6857 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6858 {{"pc"}, "r2"}, 6859 {{"sp"}, "r4"}, 6860 {{"fp"}, "r5"}, 6861 {{"rv"}, "r8"}, 6862 {{"rr1"}, "r10"}, 6863 {{"rr2"}, "r11"}, 6864 {{"rca"}, "r15"}, 6865 }; 6866 6867 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6868 return llvm::makeArrayRef(GCCRegAliases); 6869 } 6870 6871 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6872 class SparcTargetInfo : public TargetInfo { 6873 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6874 static const char * const GCCRegNames[]; 6875 bool SoftFloat; 6876 public: 6877 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6878 : TargetInfo(Triple), SoftFloat(false) {} 6879 6880 int getEHDataRegisterNumber(unsigned RegNo) const override { 6881 if (RegNo == 0) return 24; 6882 if (RegNo == 1) return 25; 6883 return -1; 6884 } 6885 6886 bool handleTargetFeatures(std::vector<std::string> &Features, 6887 DiagnosticsEngine &Diags) override { 6888 // Check if software floating point is enabled 6889 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6890 if (Feature != Features.end()) { 6891 SoftFloat = true; 6892 } 6893 return true; 6894 } 6895 void getTargetDefines(const LangOptions &Opts, 6896 MacroBuilder &Builder) const override { 6897 DefineStd(Builder, "sparc", Opts); 6898 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6899 6900 if (SoftFloat) 6901 Builder.defineMacro("SOFT_FLOAT", "1"); 6902 } 6903 6904 bool hasFeature(StringRef Feature) const override { 6905 return llvm::StringSwitch<bool>(Feature) 6906 .Case("softfloat", SoftFloat) 6907 .Case("sparc", true) 6908 .Default(false); 6909 } 6910 6911 bool hasSjLjLowering() const override { 6912 return true; 6913 } 6914 6915 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6916 // FIXME: Implement! 6917 return None; 6918 } 6919 BuiltinVaListKind getBuiltinVaListKind() const override { 6920 return TargetInfo::VoidPtrBuiltinVaList; 6921 } 6922 ArrayRef<const char *> getGCCRegNames() const override; 6923 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6924 bool validateAsmConstraint(const char *&Name, 6925 TargetInfo::ConstraintInfo &info) const override { 6926 // FIXME: Implement! 6927 switch (*Name) { 6928 case 'I': // Signed 13-bit constant 6929 case 'J': // Zero 6930 case 'K': // 32-bit constant with the low 12 bits clear 6931 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6932 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6933 case 'N': // Same as 'K' but zext (required for SIMode) 6934 case 'O': // The constant 4096 6935 return true; 6936 6937 case 'f': 6938 case 'e': 6939 info.setAllowsRegister(); 6940 return true; 6941 } 6942 return false; 6943 } 6944 const char *getClobbers() const override { 6945 // FIXME: Implement! 6946 return ""; 6947 } 6948 6949 // No Sparc V7 for now, the backend doesn't support it anyway. 6950 enum CPUKind { 6951 CK_GENERIC, 6952 CK_V8, 6953 CK_SUPERSPARC, 6954 CK_SPARCLITE, 6955 CK_F934, 6956 CK_HYPERSPARC, 6957 CK_SPARCLITE86X, 6958 CK_SPARCLET, 6959 CK_TSC701, 6960 CK_V9, 6961 CK_ULTRASPARC, 6962 CK_ULTRASPARC3, 6963 CK_NIAGARA, 6964 CK_NIAGARA2, 6965 CK_NIAGARA3, 6966 CK_NIAGARA4, 6967 CK_MYRIAD2100, 6968 CK_MYRIAD2150, 6969 CK_MYRIAD2450, 6970 CK_LEON2, 6971 CK_LEON2_AT697E, 6972 CK_LEON2_AT697F, 6973 CK_LEON3, 6974 CK_LEON3_UT699, 6975 CK_LEON3_GR712RC, 6976 CK_LEON4, 6977 CK_LEON4_GR740 6978 } CPU = CK_GENERIC; 6979 6980 enum CPUGeneration { 6981 CG_V8, 6982 CG_V9, 6983 }; 6984 6985 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6986 switch (Kind) { 6987 case CK_GENERIC: 6988 case CK_V8: 6989 case CK_SUPERSPARC: 6990 case CK_SPARCLITE: 6991 case CK_F934: 6992 case CK_HYPERSPARC: 6993 case CK_SPARCLITE86X: 6994 case CK_SPARCLET: 6995 case CK_TSC701: 6996 case CK_MYRIAD2100: 6997 case CK_MYRIAD2150: 6998 case CK_MYRIAD2450: 6999 case CK_LEON2: 7000 case CK_LEON2_AT697E: 7001 case CK_LEON2_AT697F: 7002 case CK_LEON3: 7003 case CK_LEON3_UT699: 7004 case CK_LEON3_GR712RC: 7005 case CK_LEON4: 7006 case CK_LEON4_GR740: 7007 return CG_V8; 7008 case CK_V9: 7009 case CK_ULTRASPARC: 7010 case CK_ULTRASPARC3: 7011 case CK_NIAGARA: 7012 case CK_NIAGARA2: 7013 case CK_NIAGARA3: 7014 case CK_NIAGARA4: 7015 return CG_V9; 7016 } 7017 llvm_unreachable("Unexpected CPU kind"); 7018 } 7019 7020 CPUKind getCPUKind(StringRef Name) const { 7021 return llvm::StringSwitch<CPUKind>(Name) 7022 .Case("v8", CK_V8) 7023 .Case("supersparc", CK_SUPERSPARC) 7024 .Case("sparclite", CK_SPARCLITE) 7025 .Case("f934", CK_F934) 7026 .Case("hypersparc", CK_HYPERSPARC) 7027 .Case("sparclite86x", CK_SPARCLITE86X) 7028 .Case("sparclet", CK_SPARCLET) 7029 .Case("tsc701", CK_TSC701) 7030 .Case("v9", CK_V9) 7031 .Case("ultrasparc", CK_ULTRASPARC) 7032 .Case("ultrasparc3", CK_ULTRASPARC3) 7033 .Case("niagara", CK_NIAGARA) 7034 .Case("niagara2", CK_NIAGARA2) 7035 .Case("niagara3", CK_NIAGARA3) 7036 .Case("niagara4", CK_NIAGARA4) 7037 .Case("ma2100", CK_MYRIAD2100) 7038 .Case("ma2150", CK_MYRIAD2150) 7039 .Case("ma2450", CK_MYRIAD2450) 7040 // FIXME: the myriad2[.n] spellings are obsolete, 7041 // but a grace period is needed to allow updating dependent builds. 7042 .Case("myriad2", CK_MYRIAD2100) 7043 .Case("myriad2.1", CK_MYRIAD2100) 7044 .Case("myriad2.2", CK_MYRIAD2150) 7045 .Case("leon2", CK_LEON2) 7046 .Case("at697e", CK_LEON2_AT697E) 7047 .Case("at697f", CK_LEON2_AT697F) 7048 .Case("leon3", CK_LEON3) 7049 .Case("ut699", CK_LEON3_UT699) 7050 .Case("gr712rc", CK_LEON3_GR712RC) 7051 .Case("leon4", CK_LEON4) 7052 .Case("gr740", CK_LEON4_GR740) 7053 .Default(CK_GENERIC); 7054 } 7055 7056 bool setCPU(const std::string &Name) override { 7057 CPU = getCPUKind(Name); 7058 return CPU != CK_GENERIC; 7059 } 7060 }; 7061 7062 const char * const SparcTargetInfo::GCCRegNames[] = { 7063 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7064 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7065 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 7066 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 7067 }; 7068 7069 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 7070 return llvm::makeArrayRef(GCCRegNames); 7071 } 7072 7073 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 7074 { { "g0" }, "r0" }, 7075 { { "g1" }, "r1" }, 7076 { { "g2" }, "r2" }, 7077 { { "g3" }, "r3" }, 7078 { { "g4" }, "r4" }, 7079 { { "g5" }, "r5" }, 7080 { { "g6" }, "r6" }, 7081 { { "g7" }, "r7" }, 7082 { { "o0" }, "r8" }, 7083 { { "o1" }, "r9" }, 7084 { { "o2" }, "r10" }, 7085 { { "o3" }, "r11" }, 7086 { { "o4" }, "r12" }, 7087 { { "o5" }, "r13" }, 7088 { { "o6", "sp" }, "r14" }, 7089 { { "o7" }, "r15" }, 7090 { { "l0" }, "r16" }, 7091 { { "l1" }, "r17" }, 7092 { { "l2" }, "r18" }, 7093 { { "l3" }, "r19" }, 7094 { { "l4" }, "r20" }, 7095 { { "l5" }, "r21" }, 7096 { { "l6" }, "r22" }, 7097 { { "l7" }, "r23" }, 7098 { { "i0" }, "r24" }, 7099 { { "i1" }, "r25" }, 7100 { { "i2" }, "r26" }, 7101 { { "i3" }, "r27" }, 7102 { { "i4" }, "r28" }, 7103 { { "i5" }, "r29" }, 7104 { { "i6", "fp" }, "r30" }, 7105 { { "i7" }, "r31" }, 7106 }; 7107 7108 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 7109 return llvm::makeArrayRef(GCCRegAliases); 7110 } 7111 7112 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 7113 class SparcV8TargetInfo : public SparcTargetInfo { 7114 public: 7115 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7116 : SparcTargetInfo(Triple, Opts) { 7117 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7118 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 7119 switch (getTriple().getOS()) { 7120 default: 7121 SizeType = UnsignedInt; 7122 IntPtrType = SignedInt; 7123 PtrDiffType = SignedInt; 7124 break; 7125 case llvm::Triple::NetBSD: 7126 case llvm::Triple::OpenBSD: 7127 SizeType = UnsignedLong; 7128 IntPtrType = SignedLong; 7129 PtrDiffType = SignedLong; 7130 break; 7131 } 7132 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops 7133 // on up to 64 bits. 7134 MaxAtomicPromoteWidth = 64; 7135 MaxAtomicInlineWidth = 32; 7136 } 7137 7138 void getTargetDefines(const LangOptions &Opts, 7139 MacroBuilder &Builder) const override { 7140 SparcTargetInfo::getTargetDefines(Opts, Builder); 7141 switch (getCPUGeneration(CPU)) { 7142 case CG_V8: 7143 Builder.defineMacro("__sparcv8"); 7144 if (getTriple().getOS() != llvm::Triple::Solaris) 7145 Builder.defineMacro("__sparcv8__"); 7146 break; 7147 case CG_V9: 7148 Builder.defineMacro("__sparcv9"); 7149 if (getTriple().getOS() != llvm::Triple::Solaris) { 7150 Builder.defineMacro("__sparcv9__"); 7151 Builder.defineMacro("__sparc_v9__"); 7152 } 7153 break; 7154 } 7155 if (getTriple().getVendor() == llvm::Triple::Myriad) { 7156 std::string MyriadArchValue, Myriad2Value; 7157 Builder.defineMacro("__sparc_v8__"); 7158 Builder.defineMacro("__leon__"); 7159 switch (CPU) { 7160 case CK_MYRIAD2150: 7161 MyriadArchValue = "__ma2150"; 7162 Myriad2Value = "2"; 7163 break; 7164 case CK_MYRIAD2450: 7165 MyriadArchValue = "__ma2450"; 7166 Myriad2Value = "2"; 7167 break; 7168 default: 7169 MyriadArchValue = "__ma2100"; 7170 Myriad2Value = "1"; 7171 break; 7172 } 7173 Builder.defineMacro(MyriadArchValue, "1"); 7174 Builder.defineMacro(MyriadArchValue+"__", "1"); 7175 Builder.defineMacro("__myriad2__", Myriad2Value); 7176 Builder.defineMacro("__myriad2", Myriad2Value); 7177 } 7178 } 7179 7180 bool hasSjLjLowering() const override { 7181 return true; 7182 } 7183 }; 7184 7185 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 7186 class SparcV8elTargetInfo : public SparcV8TargetInfo { 7187 public: 7188 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7189 : SparcV8TargetInfo(Triple, Opts) { 7190 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7191 } 7192 }; 7193 7194 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 7195 class SparcV9TargetInfo : public SparcTargetInfo { 7196 public: 7197 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7198 : SparcTargetInfo(Triple, Opts) { 7199 // FIXME: Support Sparc quad-precision long double? 7200 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 7201 // This is an LP64 platform. 7202 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7203 7204 // OpenBSD uses long long for int64_t and intmax_t. 7205 if (getTriple().getOS() == llvm::Triple::OpenBSD) 7206 IntMaxType = SignedLongLong; 7207 else 7208 IntMaxType = SignedLong; 7209 Int64Type = IntMaxType; 7210 7211 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 7212 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 7213 LongDoubleWidth = 128; 7214 LongDoubleAlign = 128; 7215 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7216 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7217 } 7218 7219 void getTargetDefines(const LangOptions &Opts, 7220 MacroBuilder &Builder) const override { 7221 SparcTargetInfo::getTargetDefines(Opts, Builder); 7222 Builder.defineMacro("__sparcv9"); 7223 Builder.defineMacro("__arch64__"); 7224 // Solaris doesn't need these variants, but the BSDs do. 7225 if (getTriple().getOS() != llvm::Triple::Solaris) { 7226 Builder.defineMacro("__sparc64__"); 7227 Builder.defineMacro("__sparc_v9__"); 7228 Builder.defineMacro("__sparcv9__"); 7229 } 7230 } 7231 7232 bool setCPU(const std::string &Name) override { 7233 if (!SparcTargetInfo::setCPU(Name)) 7234 return false; 7235 return getCPUGeneration(CPU) == CG_V9; 7236 } 7237 }; 7238 7239 class SystemZTargetInfo : public TargetInfo { 7240 static const Builtin::Info BuiltinInfo[]; 7241 static const char *const GCCRegNames[]; 7242 std::string CPU; 7243 bool HasTransactionalExecution; 7244 bool HasVector; 7245 7246 public: 7247 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7248 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 7249 HasVector(false) { 7250 IntMaxType = SignedLong; 7251 Int64Type = SignedLong; 7252 TLSSupported = true; 7253 IntWidth = IntAlign = 32; 7254 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 7255 PointerWidth = PointerAlign = 64; 7256 LongDoubleWidth = 128; 7257 LongDoubleAlign = 64; 7258 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7259 DefaultAlignForAttributeAligned = 64; 7260 MinGlobalAlign = 16; 7261 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 7262 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7263 } 7264 void getTargetDefines(const LangOptions &Opts, 7265 MacroBuilder &Builder) const override { 7266 Builder.defineMacro("__s390__"); 7267 Builder.defineMacro("__s390x__"); 7268 Builder.defineMacro("__zarch__"); 7269 Builder.defineMacro("__LONG_DOUBLE_128__"); 7270 7271 const std::string ISARev = llvm::StringSwitch<std::string>(CPU) 7272 .Cases("arch8", "z10", "8") 7273 .Cases("arch9", "z196", "9") 7274 .Cases("arch10", "zEC12", "10") 7275 .Cases("arch11", "z13", "11") 7276 .Default(""); 7277 if (!ISARev.empty()) 7278 Builder.defineMacro("__ARCH__", ISARev); 7279 7280 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7281 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7282 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7283 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7284 7285 if (HasTransactionalExecution) 7286 Builder.defineMacro("__HTM__"); 7287 if (HasVector) 7288 Builder.defineMacro("__VX__"); 7289 if (Opts.ZVector) 7290 Builder.defineMacro("__VEC__", "10301"); 7291 } 7292 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7293 return llvm::makeArrayRef(BuiltinInfo, 7294 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 7295 } 7296 7297 ArrayRef<const char *> getGCCRegNames() const override; 7298 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7299 // No aliases. 7300 return None; 7301 } 7302 bool validateAsmConstraint(const char *&Name, 7303 TargetInfo::ConstraintInfo &info) const override; 7304 const char *getClobbers() const override { 7305 // FIXME: Is this really right? 7306 return ""; 7307 } 7308 BuiltinVaListKind getBuiltinVaListKind() const override { 7309 return TargetInfo::SystemZBuiltinVaList; 7310 } 7311 bool setCPU(const std::string &Name) override { 7312 CPU = Name; 7313 bool CPUKnown = llvm::StringSwitch<bool>(Name) 7314 .Case("z10", true) 7315 .Case("arch8", true) 7316 .Case("z196", true) 7317 .Case("arch9", true) 7318 .Case("zEC12", true) 7319 .Case("arch10", true) 7320 .Case("z13", true) 7321 .Case("arch11", true) 7322 .Default(false); 7323 7324 return CPUKnown; 7325 } 7326 bool 7327 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7328 StringRef CPU, 7329 const std::vector<std::string> &FeaturesVec) const override { 7330 if (CPU == "zEC12" || CPU == "arch10") 7331 Features["transactional-execution"] = true; 7332 if (CPU == "z13" || CPU == "arch11") { 7333 Features["transactional-execution"] = true; 7334 Features["vector"] = true; 7335 } 7336 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7337 } 7338 7339 bool handleTargetFeatures(std::vector<std::string> &Features, 7340 DiagnosticsEngine &Diags) override { 7341 HasTransactionalExecution = false; 7342 for (const auto &Feature : Features) { 7343 if (Feature == "+transactional-execution") 7344 HasTransactionalExecution = true; 7345 else if (Feature == "+vector") 7346 HasVector = true; 7347 } 7348 // If we use the vector ABI, vector types are 64-bit aligned. 7349 if (HasVector) { 7350 MaxVectorAlign = 64; 7351 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 7352 "-v128:64-a:8:16-n32:64"); 7353 } 7354 return true; 7355 } 7356 7357 bool hasFeature(StringRef Feature) const override { 7358 return llvm::StringSwitch<bool>(Feature) 7359 .Case("systemz", true) 7360 .Case("htm", HasTransactionalExecution) 7361 .Case("vx", HasVector) 7362 .Default(false); 7363 } 7364 7365 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7366 switch (CC) { 7367 case CC_C: 7368 case CC_Swift: 7369 return CCCR_OK; 7370 default: 7371 return CCCR_Warning; 7372 } 7373 } 7374 7375 StringRef getABI() const override { 7376 if (HasVector) 7377 return "vector"; 7378 return ""; 7379 } 7380 7381 bool useFloat128ManglingForLongDouble() const override { 7382 return true; 7383 } 7384 }; 7385 7386 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 7387 #define BUILTIN(ID, TYPE, ATTRS) \ 7388 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7389 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7390 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 7391 #include "clang/Basic/BuiltinsSystemZ.def" 7392 }; 7393 7394 const char *const SystemZTargetInfo::GCCRegNames[] = { 7395 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7396 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7397 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 7398 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 7399 }; 7400 7401 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 7402 return llvm::makeArrayRef(GCCRegNames); 7403 } 7404 7405 bool SystemZTargetInfo:: 7406 validateAsmConstraint(const char *&Name, 7407 TargetInfo::ConstraintInfo &Info) const { 7408 switch (*Name) { 7409 default: 7410 return false; 7411 7412 case 'a': // Address register 7413 case 'd': // Data register (equivalent to 'r') 7414 case 'f': // Floating-point register 7415 Info.setAllowsRegister(); 7416 return true; 7417 7418 case 'I': // Unsigned 8-bit constant 7419 case 'J': // Unsigned 12-bit constant 7420 case 'K': // Signed 16-bit constant 7421 case 'L': // Signed 20-bit displacement (on all targets we support) 7422 case 'M': // 0x7fffffff 7423 return true; 7424 7425 case 'Q': // Memory with base and unsigned 12-bit displacement 7426 case 'R': // Likewise, plus an index 7427 case 'S': // Memory with base and signed 20-bit displacement 7428 case 'T': // Likewise, plus an index 7429 Info.setAllowsMemory(); 7430 return true; 7431 } 7432 } 7433 7434 class MSP430TargetInfo : public TargetInfo { 7435 static const char *const GCCRegNames[]; 7436 7437 public: 7438 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7439 : TargetInfo(Triple) { 7440 TLSSupported = false; 7441 IntWidth = 16; 7442 IntAlign = 16; 7443 LongWidth = 32; 7444 LongLongWidth = 64; 7445 LongAlign = LongLongAlign = 16; 7446 PointerWidth = 16; 7447 PointerAlign = 16; 7448 SuitableAlign = 16; 7449 SizeType = UnsignedInt; 7450 IntMaxType = SignedLongLong; 7451 IntPtrType = SignedInt; 7452 PtrDiffType = SignedInt; 7453 SigAtomicType = SignedLong; 7454 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 7455 } 7456 void getTargetDefines(const LangOptions &Opts, 7457 MacroBuilder &Builder) const override { 7458 Builder.defineMacro("MSP430"); 7459 Builder.defineMacro("__MSP430__"); 7460 // FIXME: defines for different 'flavours' of MCU 7461 } 7462 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7463 // FIXME: Implement. 7464 return None; 7465 } 7466 bool hasFeature(StringRef Feature) const override { 7467 return Feature == "msp430"; 7468 } 7469 ArrayRef<const char *> getGCCRegNames() const override; 7470 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7471 // No aliases. 7472 return None; 7473 } 7474 bool validateAsmConstraint(const char *&Name, 7475 TargetInfo::ConstraintInfo &info) const override { 7476 // FIXME: implement 7477 switch (*Name) { 7478 case 'K': // the constant 1 7479 case 'L': // constant -1^20 .. 1^19 7480 case 'M': // constant 1-4: 7481 return true; 7482 } 7483 // No target constraints for now. 7484 return false; 7485 } 7486 const char *getClobbers() const override { 7487 // FIXME: Is this really right? 7488 return ""; 7489 } 7490 BuiltinVaListKind getBuiltinVaListKind() const override { 7491 // FIXME: implement 7492 return TargetInfo::CharPtrBuiltinVaList; 7493 } 7494 }; 7495 7496 const char *const MSP430TargetInfo::GCCRegNames[] = { 7497 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7498 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7499 7500 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7501 return llvm::makeArrayRef(GCCRegNames); 7502 } 7503 7504 // LLVM and Clang cannot be used directly to output native binaries for 7505 // target, but is used to compile C code to llvm bitcode with correct 7506 // type and alignment information. 7507 // 7508 // TCE uses the llvm bitcode as input and uses it for generating customized 7509 // target processor and program binary. TCE co-design environment is 7510 // publicly available in http://tce.cs.tut.fi 7511 7512 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7513 0, // Default 7514 3, // opencl_global 7515 4, // opencl_local 7516 5, // opencl_constant 7517 // FIXME: generic has to be added to the target 7518 0, // opencl_generic 7519 0, // cuda_device 7520 0, // cuda_constant 7521 0 // cuda_shared 7522 }; 7523 7524 class TCETargetInfo : public TargetInfo { 7525 public: 7526 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7527 : TargetInfo(Triple) { 7528 TLSSupported = false; 7529 IntWidth = 32; 7530 LongWidth = LongLongWidth = 32; 7531 PointerWidth = 32; 7532 IntAlign = 32; 7533 LongAlign = LongLongAlign = 32; 7534 PointerAlign = 32; 7535 SuitableAlign = 32; 7536 SizeType = UnsignedInt; 7537 IntMaxType = SignedLong; 7538 IntPtrType = SignedInt; 7539 PtrDiffType = SignedInt; 7540 FloatWidth = 32; 7541 FloatAlign = 32; 7542 DoubleWidth = 32; 7543 DoubleAlign = 32; 7544 LongDoubleWidth = 32; 7545 LongDoubleAlign = 32; 7546 FloatFormat = &llvm::APFloat::IEEEsingle(); 7547 DoubleFormat = &llvm::APFloat::IEEEsingle(); 7548 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 7549 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-" 7550 "i16:16:32-i32:32:32-i64:32:32-" 7551 "f32:32:32-f64:32:32-v64:32:32-" 7552 "v128:32:32-v256:32:32-v512:32:32-" 7553 "v1024:32:32-a0:0:32-n32"); 7554 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7555 UseAddrSpaceMapMangling = true; 7556 } 7557 7558 void getTargetDefines(const LangOptions &Opts, 7559 MacroBuilder &Builder) const override { 7560 DefineStd(Builder, "tce", Opts); 7561 Builder.defineMacro("__TCE__"); 7562 Builder.defineMacro("__TCE_V1__"); 7563 } 7564 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7565 7566 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7567 const char *getClobbers() const override { return ""; } 7568 BuiltinVaListKind getBuiltinVaListKind() const override { 7569 return TargetInfo::VoidPtrBuiltinVaList; 7570 } 7571 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7572 bool validateAsmConstraint(const char *&Name, 7573 TargetInfo::ConstraintInfo &info) const override { 7574 return true; 7575 } 7576 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7577 return None; 7578 } 7579 }; 7580 7581 class TCELETargetInfo : public TCETargetInfo { 7582 public: 7583 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7584 : TCETargetInfo(Triple, Opts) { 7585 BigEndian = false; 7586 7587 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-" 7588 "i16:16:32-i32:32:32-i64:32:32-" 7589 "f32:32:32-f64:32:32-v64:32:32-" 7590 "v128:32:32-v256:32:32-v512:32:32-" 7591 "v1024:32:32-a0:0:32-n32"); 7592 7593 } 7594 7595 virtual void getTargetDefines(const LangOptions &Opts, 7596 MacroBuilder &Builder) const { 7597 DefineStd(Builder, "tcele", Opts); 7598 Builder.defineMacro("__TCE__"); 7599 Builder.defineMacro("__TCE_V1__"); 7600 Builder.defineMacro("__TCELE__"); 7601 Builder.defineMacro("__TCELE_V1__"); 7602 } 7603 7604 }; 7605 7606 class BPFTargetInfo : public TargetInfo { 7607 public: 7608 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7609 : TargetInfo(Triple) { 7610 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7611 SizeType = UnsignedLong; 7612 PtrDiffType = SignedLong; 7613 IntPtrType = SignedLong; 7614 IntMaxType = SignedLong; 7615 Int64Type = SignedLong; 7616 RegParmMax = 5; 7617 if (Triple.getArch() == llvm::Triple::bpfeb) { 7618 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7619 } else { 7620 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7621 } 7622 MaxAtomicPromoteWidth = 64; 7623 MaxAtomicInlineWidth = 64; 7624 TLSSupported = false; 7625 } 7626 void getTargetDefines(const LangOptions &Opts, 7627 MacroBuilder &Builder) const override { 7628 DefineStd(Builder, "bpf", Opts); 7629 Builder.defineMacro("__BPF__"); 7630 } 7631 bool hasFeature(StringRef Feature) const override { 7632 return Feature == "bpf"; 7633 } 7634 7635 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7636 const char *getClobbers() const override { 7637 return ""; 7638 } 7639 BuiltinVaListKind getBuiltinVaListKind() const override { 7640 return TargetInfo::VoidPtrBuiltinVaList; 7641 } 7642 ArrayRef<const char *> getGCCRegNames() const override { 7643 return None; 7644 } 7645 bool validateAsmConstraint(const char *&Name, 7646 TargetInfo::ConstraintInfo &info) const override { 7647 return true; 7648 } 7649 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7650 return None; 7651 } 7652 }; 7653 7654 class MipsTargetInfo : public TargetInfo { 7655 void setDataLayout() { 7656 StringRef Layout; 7657 7658 if (ABI == "o32") 7659 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7660 else if (ABI == "n32") 7661 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7662 else if (ABI == "n64") 7663 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7664 else 7665 llvm_unreachable("Invalid ABI"); 7666 7667 if (BigEndian) 7668 resetDataLayout(("E-" + Layout).str()); 7669 else 7670 resetDataLayout(("e-" + Layout).str()); 7671 } 7672 7673 7674 static const Builtin::Info BuiltinInfo[]; 7675 std::string CPU; 7676 bool IsMips16; 7677 bool IsMicromips; 7678 bool IsNan2008; 7679 bool IsSingleFloat; 7680 bool IsNoABICalls; 7681 bool CanUseBSDABICalls; 7682 enum MipsFloatABI { 7683 HardFloat, SoftFloat 7684 } FloatABI; 7685 enum DspRevEnum { 7686 NoDSP, DSP1, DSP2 7687 } DspRev; 7688 bool HasMSA; 7689 7690 protected: 7691 bool HasFP64; 7692 std::string ABI; 7693 7694 public: 7695 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7696 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7697 IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false), 7698 CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP), 7699 HasMSA(false), HasFP64(false) { 7700 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7701 7702 setABI((getTriple().getArch() == llvm::Triple::mips || 7703 getTriple().getArch() == llvm::Triple::mipsel) 7704 ? "o32" 7705 : "n64"); 7706 7707 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7708 7709 CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD || 7710 Triple.getOS() == llvm::Triple::OpenBSD; 7711 } 7712 7713 bool isNaN2008Default() const { 7714 return CPU == "mips32r6" || CPU == "mips64r6"; 7715 } 7716 7717 bool isFP64Default() const { 7718 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7719 } 7720 7721 bool isNan2008() const override { 7722 return IsNan2008; 7723 } 7724 7725 bool processorSupportsGPR64() const { 7726 return llvm::StringSwitch<bool>(CPU) 7727 .Case("mips3", true) 7728 .Case("mips4", true) 7729 .Case("mips5", true) 7730 .Case("mips64", true) 7731 .Case("mips64r2", true) 7732 .Case("mips64r3", true) 7733 .Case("mips64r5", true) 7734 .Case("mips64r6", true) 7735 .Case("octeon", true) 7736 .Default(false); 7737 return false; 7738 } 7739 7740 StringRef getABI() const override { return ABI; } 7741 bool setABI(const std::string &Name) override { 7742 if (Name == "o32") { 7743 setO32ABITypes(); 7744 ABI = Name; 7745 return true; 7746 } 7747 7748 if (Name == "n32") { 7749 setN32ABITypes(); 7750 ABI = Name; 7751 return true; 7752 } 7753 if (Name == "n64") { 7754 setN64ABITypes(); 7755 ABI = Name; 7756 return true; 7757 } 7758 return false; 7759 } 7760 7761 void setO32ABITypes() { 7762 Int64Type = SignedLongLong; 7763 IntMaxType = Int64Type; 7764 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7765 LongDoubleWidth = LongDoubleAlign = 64; 7766 LongWidth = LongAlign = 32; 7767 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7768 PointerWidth = PointerAlign = 32; 7769 PtrDiffType = SignedInt; 7770 SizeType = UnsignedInt; 7771 SuitableAlign = 64; 7772 } 7773 7774 void setN32N64ABITypes() { 7775 LongDoubleWidth = LongDoubleAlign = 128; 7776 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7777 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7778 LongDoubleWidth = LongDoubleAlign = 64; 7779 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7780 } 7781 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7782 SuitableAlign = 128; 7783 } 7784 7785 void setN64ABITypes() { 7786 setN32N64ABITypes(); 7787 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 7788 Int64Type = SignedLongLong; 7789 } else { 7790 Int64Type = SignedLong; 7791 } 7792 IntMaxType = Int64Type; 7793 LongWidth = LongAlign = 64; 7794 PointerWidth = PointerAlign = 64; 7795 PtrDiffType = SignedLong; 7796 SizeType = UnsignedLong; 7797 } 7798 7799 void setN32ABITypes() { 7800 setN32N64ABITypes(); 7801 Int64Type = SignedLongLong; 7802 IntMaxType = Int64Type; 7803 LongWidth = LongAlign = 32; 7804 PointerWidth = PointerAlign = 32; 7805 PtrDiffType = SignedInt; 7806 SizeType = UnsignedInt; 7807 } 7808 7809 bool setCPU(const std::string &Name) override { 7810 CPU = Name; 7811 return llvm::StringSwitch<bool>(Name) 7812 .Case("mips1", true) 7813 .Case("mips2", true) 7814 .Case("mips3", true) 7815 .Case("mips4", true) 7816 .Case("mips5", true) 7817 .Case("mips32", true) 7818 .Case("mips32r2", true) 7819 .Case("mips32r3", true) 7820 .Case("mips32r5", true) 7821 .Case("mips32r6", true) 7822 .Case("mips64", true) 7823 .Case("mips64r2", true) 7824 .Case("mips64r3", true) 7825 .Case("mips64r5", true) 7826 .Case("mips64r6", true) 7827 .Case("octeon", true) 7828 .Case("p5600", true) 7829 .Default(false); 7830 } 7831 const std::string& getCPU() const { return CPU; } 7832 bool 7833 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7834 StringRef CPU, 7835 const std::vector<std::string> &FeaturesVec) const override { 7836 if (CPU.empty()) 7837 CPU = getCPU(); 7838 if (CPU == "octeon") 7839 Features["mips64r2"] = Features["cnmips"] = true; 7840 else 7841 Features[CPU] = true; 7842 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7843 } 7844 7845 void getTargetDefines(const LangOptions &Opts, 7846 MacroBuilder &Builder) const override { 7847 if (BigEndian) { 7848 DefineStd(Builder, "MIPSEB", Opts); 7849 Builder.defineMacro("_MIPSEB"); 7850 } else { 7851 DefineStd(Builder, "MIPSEL", Opts); 7852 Builder.defineMacro("_MIPSEL"); 7853 } 7854 7855 Builder.defineMacro("__mips__"); 7856 Builder.defineMacro("_mips"); 7857 if (Opts.GNUMode) 7858 Builder.defineMacro("mips"); 7859 7860 if (ABI == "o32") { 7861 Builder.defineMacro("__mips", "32"); 7862 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7863 } else { 7864 Builder.defineMacro("__mips", "64"); 7865 Builder.defineMacro("__mips64"); 7866 Builder.defineMacro("__mips64__"); 7867 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7868 } 7869 7870 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7871 .Cases("mips32", "mips64", "1") 7872 .Cases("mips32r2", "mips64r2", "2") 7873 .Cases("mips32r3", "mips64r3", "3") 7874 .Cases("mips32r5", "mips64r5", "5") 7875 .Cases("mips32r6", "mips64r6", "6") 7876 .Default(""); 7877 if (!ISARev.empty()) 7878 Builder.defineMacro("__mips_isa_rev", ISARev); 7879 7880 if (ABI == "o32") { 7881 Builder.defineMacro("__mips_o32"); 7882 Builder.defineMacro("_ABIO32", "1"); 7883 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7884 } else if (ABI == "n32") { 7885 Builder.defineMacro("__mips_n32"); 7886 Builder.defineMacro("_ABIN32", "2"); 7887 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7888 } else if (ABI == "n64") { 7889 Builder.defineMacro("__mips_n64"); 7890 Builder.defineMacro("_ABI64", "3"); 7891 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7892 } else 7893 llvm_unreachable("Invalid ABI."); 7894 7895 if (!IsNoABICalls) { 7896 Builder.defineMacro("__mips_abicalls"); 7897 if (CanUseBSDABICalls) 7898 Builder.defineMacro("__ABICALLS__"); 7899 } 7900 7901 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7902 7903 switch (FloatABI) { 7904 case HardFloat: 7905 Builder.defineMacro("__mips_hard_float", Twine(1)); 7906 break; 7907 case SoftFloat: 7908 Builder.defineMacro("__mips_soft_float", Twine(1)); 7909 break; 7910 } 7911 7912 if (IsSingleFloat) 7913 Builder.defineMacro("__mips_single_float", Twine(1)); 7914 7915 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7916 Builder.defineMacro("_MIPS_FPSET", 7917 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7918 7919 if (IsMips16) 7920 Builder.defineMacro("__mips16", Twine(1)); 7921 7922 if (IsMicromips) 7923 Builder.defineMacro("__mips_micromips", Twine(1)); 7924 7925 if (IsNan2008) 7926 Builder.defineMacro("__mips_nan2008", Twine(1)); 7927 7928 switch (DspRev) { 7929 default: 7930 break; 7931 case DSP1: 7932 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7933 Builder.defineMacro("__mips_dsp", Twine(1)); 7934 break; 7935 case DSP2: 7936 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7937 Builder.defineMacro("__mips_dspr2", Twine(1)); 7938 Builder.defineMacro("__mips_dsp", Twine(1)); 7939 break; 7940 } 7941 7942 if (HasMSA) 7943 Builder.defineMacro("__mips_msa", Twine(1)); 7944 7945 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7946 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7947 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7948 7949 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7950 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7951 7952 // These shouldn't be defined for MIPS-I but there's no need to check 7953 // for that since MIPS-I isn't supported. 7954 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7955 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7956 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7957 7958 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7959 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7960 // the instructions exist but using them violates the ABI since they 7961 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7962 if (ABI == "n32" || ABI == "n64") 7963 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7964 } 7965 7966 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7967 return llvm::makeArrayRef(BuiltinInfo, 7968 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7969 } 7970 bool hasFeature(StringRef Feature) const override { 7971 return llvm::StringSwitch<bool>(Feature) 7972 .Case("mips", true) 7973 .Case("fp64", HasFP64) 7974 .Default(false); 7975 } 7976 BuiltinVaListKind getBuiltinVaListKind() const override { 7977 return TargetInfo::VoidPtrBuiltinVaList; 7978 } 7979 ArrayRef<const char *> getGCCRegNames() const override { 7980 static const char *const GCCRegNames[] = { 7981 // CPU register names 7982 // Must match second column of GCCRegAliases 7983 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7984 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7985 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7986 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7987 // Floating point register names 7988 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7989 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7990 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7991 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7992 // Hi/lo and condition register names 7993 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7994 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7995 "$ac3hi","$ac3lo", 7996 // MSA register names 7997 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7998 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7999 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 8000 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 8001 // MSA control register names 8002 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 8003 "$msarequest", "$msamap", "$msaunmap" 8004 }; 8005 return llvm::makeArrayRef(GCCRegNames); 8006 } 8007 bool validateAsmConstraint(const char *&Name, 8008 TargetInfo::ConstraintInfo &Info) const override { 8009 switch (*Name) { 8010 default: 8011 return false; 8012 case 'r': // CPU registers. 8013 case 'd': // Equivalent to "r" unless generating MIPS16 code. 8014 case 'y': // Equivalent to "r", backward compatibility only. 8015 case 'f': // floating-point registers. 8016 case 'c': // $25 for indirect jumps 8017 case 'l': // lo register 8018 case 'x': // hilo register pair 8019 Info.setAllowsRegister(); 8020 return true; 8021 case 'I': // Signed 16-bit constant 8022 case 'J': // Integer 0 8023 case 'K': // Unsigned 16-bit constant 8024 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 8025 case 'M': // Constants not loadable via lui, addiu, or ori 8026 case 'N': // Constant -1 to -65535 8027 case 'O': // A signed 15-bit constant 8028 case 'P': // A constant between 1 go 65535 8029 return true; 8030 case 'R': // An address that can be used in a non-macro load or store 8031 Info.setAllowsMemory(); 8032 return true; 8033 case 'Z': 8034 if (Name[1] == 'C') { // An address usable by ll, and sc. 8035 Info.setAllowsMemory(); 8036 Name++; // Skip over 'Z'. 8037 return true; 8038 } 8039 return false; 8040 } 8041 } 8042 8043 std::string convertConstraint(const char *&Constraint) const override { 8044 std::string R; 8045 switch (*Constraint) { 8046 case 'Z': // Two-character constraint; add "^" hint for later parsing. 8047 if (Constraint[1] == 'C') { 8048 R = std::string("^") + std::string(Constraint, 2); 8049 Constraint++; 8050 return R; 8051 } 8052 break; 8053 } 8054 return TargetInfo::convertConstraint(Constraint); 8055 } 8056 8057 const char *getClobbers() const override { 8058 // In GCC, $1 is not widely used in generated code (it's used only in a few 8059 // specific situations), so there is no real need for users to add it to 8060 // the clobbers list if they want to use it in their inline assembly code. 8061 // 8062 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 8063 // code generation, so using it in inline assembly without adding it to the 8064 // clobbers list can cause conflicts between the inline assembly code and 8065 // the surrounding generated code. 8066 // 8067 // Another problem is that LLVM is allowed to choose $1 for inline assembly 8068 // operands, which will conflict with the ".set at" assembler option (which 8069 // we use only for inline assembly, in order to maintain compatibility with 8070 // GCC) and will also conflict with the user's usage of $1. 8071 // 8072 // The easiest way to avoid these conflicts and keep $1 as an allocatable 8073 // register for generated code is to automatically clobber $1 for all inline 8074 // assembly code. 8075 // 8076 // FIXME: We should automatically clobber $1 only for inline assembly code 8077 // which actually uses it. This would allow LLVM to use $1 for inline 8078 // assembly operands if the user's assembly code doesn't use it. 8079 return "~{$1}"; 8080 } 8081 8082 bool handleTargetFeatures(std::vector<std::string> &Features, 8083 DiagnosticsEngine &Diags) override { 8084 IsMips16 = false; 8085 IsMicromips = false; 8086 IsNan2008 = isNaN2008Default(); 8087 IsSingleFloat = false; 8088 FloatABI = HardFloat; 8089 DspRev = NoDSP; 8090 HasFP64 = isFP64Default(); 8091 8092 for (const auto &Feature : Features) { 8093 if (Feature == "+single-float") 8094 IsSingleFloat = true; 8095 else if (Feature == "+soft-float") 8096 FloatABI = SoftFloat; 8097 else if (Feature == "+mips16") 8098 IsMips16 = true; 8099 else if (Feature == "+micromips") 8100 IsMicromips = true; 8101 else if (Feature == "+dsp") 8102 DspRev = std::max(DspRev, DSP1); 8103 else if (Feature == "+dspr2") 8104 DspRev = std::max(DspRev, DSP2); 8105 else if (Feature == "+msa") 8106 HasMSA = true; 8107 else if (Feature == "+fp64") 8108 HasFP64 = true; 8109 else if (Feature == "-fp64") 8110 HasFP64 = false; 8111 else if (Feature == "+nan2008") 8112 IsNan2008 = true; 8113 else if (Feature == "-nan2008") 8114 IsNan2008 = false; 8115 else if (Feature == "+noabicalls") 8116 IsNoABICalls = true; 8117 } 8118 8119 setDataLayout(); 8120 8121 return true; 8122 } 8123 8124 int getEHDataRegisterNumber(unsigned RegNo) const override { 8125 if (RegNo == 0) return 4; 8126 if (RegNo == 1) return 5; 8127 return -1; 8128 } 8129 8130 bool isCLZForZeroUndef() const override { return false; } 8131 8132 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8133 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 8134 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8135 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8136 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 8137 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 8138 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 8139 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8140 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8141 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8142 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8143 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8144 {{"ra"}, "$31"}}; 8145 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 8146 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8147 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8148 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 8149 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 8150 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 8151 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8152 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8153 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8154 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8155 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8156 {{"ra"}, "$31"}}; 8157 if (ABI == "o32") 8158 return llvm::makeArrayRef(O32RegAliases); 8159 return llvm::makeArrayRef(NewABIRegAliases); 8160 } 8161 8162 bool hasInt128Type() const override { 8163 return ABI == "n32" || ABI == "n64"; 8164 } 8165 8166 bool validateTarget(DiagnosticsEngine &Diags) const override { 8167 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 8168 // this yet. It's better to fail here than on the backend assertion. 8169 if (processorSupportsGPR64() && ABI == "o32") { 8170 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8171 return false; 8172 } 8173 8174 // 64-bit ABI's require 64-bit CPU's. 8175 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 8176 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8177 return false; 8178 } 8179 8180 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 8181 // can't handle this yet. It's better to fail here than on the 8182 // backend assertion. 8183 if ((getTriple().getArch() == llvm::Triple::mips64 || 8184 getTriple().getArch() == llvm::Triple::mips64el) && 8185 ABI == "o32") { 8186 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8187 << ABI << getTriple().str(); 8188 return false; 8189 } 8190 8191 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 8192 // can't handle this yet. It's better to fail here than on the 8193 // backend assertion. 8194 if ((getTriple().getArch() == llvm::Triple::mips || 8195 getTriple().getArch() == llvm::Triple::mipsel) && 8196 (ABI == "n32" || ABI == "n64")) { 8197 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8198 << ABI << getTriple().str(); 8199 return false; 8200 } 8201 8202 return true; 8203 } 8204 }; 8205 8206 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 8207 #define BUILTIN(ID, TYPE, ATTRS) \ 8208 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8209 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8210 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8211 #include "clang/Basic/BuiltinsMips.def" 8212 }; 8213 8214 class PNaClTargetInfo : public TargetInfo { 8215 public: 8216 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8217 : TargetInfo(Triple) { 8218 this->LongAlign = 32; 8219 this->LongWidth = 32; 8220 this->PointerAlign = 32; 8221 this->PointerWidth = 32; 8222 this->IntMaxType = TargetInfo::SignedLongLong; 8223 this->Int64Type = TargetInfo::SignedLongLong; 8224 this->DoubleAlign = 64; 8225 this->LongDoubleWidth = 64; 8226 this->LongDoubleAlign = 64; 8227 this->SizeType = TargetInfo::UnsignedInt; 8228 this->PtrDiffType = TargetInfo::SignedInt; 8229 this->IntPtrType = TargetInfo::SignedInt; 8230 this->RegParmMax = 0; // Disallow regparm 8231 } 8232 8233 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 8234 Builder.defineMacro("__le32__"); 8235 Builder.defineMacro("__pnacl__"); 8236 } 8237 void getTargetDefines(const LangOptions &Opts, 8238 MacroBuilder &Builder) const override { 8239 getArchDefines(Opts, Builder); 8240 } 8241 bool hasFeature(StringRef Feature) const override { 8242 return Feature == "pnacl"; 8243 } 8244 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8245 BuiltinVaListKind getBuiltinVaListKind() const override { 8246 return TargetInfo::PNaClABIBuiltinVaList; 8247 } 8248 ArrayRef<const char *> getGCCRegNames() const override; 8249 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 8250 bool validateAsmConstraint(const char *&Name, 8251 TargetInfo::ConstraintInfo &Info) const override { 8252 return false; 8253 } 8254 8255 const char *getClobbers() const override { 8256 return ""; 8257 } 8258 }; 8259 8260 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 8261 return None; 8262 } 8263 8264 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 8265 return None; 8266 } 8267 8268 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 8269 class NaClMips32TargetInfo : public MipsTargetInfo { 8270 public: 8271 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8272 : MipsTargetInfo(Triple, Opts) {} 8273 8274 BuiltinVaListKind getBuiltinVaListKind() const override { 8275 return TargetInfo::PNaClABIBuiltinVaList; 8276 } 8277 }; 8278 8279 class Le64TargetInfo : public TargetInfo { 8280 static const Builtin::Info BuiltinInfo[]; 8281 8282 public: 8283 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8284 : TargetInfo(Triple) { 8285 NoAsmVariants = true; 8286 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 8287 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8288 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 8289 } 8290 8291 void getTargetDefines(const LangOptions &Opts, 8292 MacroBuilder &Builder) const override { 8293 DefineStd(Builder, "unix", Opts); 8294 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 8295 Builder.defineMacro("__ELF__"); 8296 } 8297 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8298 return llvm::makeArrayRef(BuiltinInfo, 8299 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 8300 } 8301 BuiltinVaListKind getBuiltinVaListKind() const override { 8302 return TargetInfo::PNaClABIBuiltinVaList; 8303 } 8304 const char *getClobbers() const override { return ""; } 8305 ArrayRef<const char *> getGCCRegNames() const override { 8306 return None; 8307 } 8308 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8309 return None; 8310 } 8311 bool validateAsmConstraint(const char *&Name, 8312 TargetInfo::ConstraintInfo &Info) const override { 8313 return false; 8314 } 8315 8316 bool hasProtectedVisibility() const override { return false; } 8317 }; 8318 8319 class WebAssemblyTargetInfo : public TargetInfo { 8320 static const Builtin::Info BuiltinInfo[]; 8321 8322 enum SIMDEnum { 8323 NoSIMD, 8324 SIMD128, 8325 } SIMDLevel; 8326 8327 public: 8328 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 8329 : TargetInfo(T), SIMDLevel(NoSIMD) { 8330 NoAsmVariants = true; 8331 SuitableAlign = 128; 8332 LargeArrayMinWidth = 128; 8333 LargeArrayAlign = 128; 8334 SimdDefaultAlign = 128; 8335 SigAtomicType = SignedLong; 8336 LongDoubleWidth = LongDoubleAlign = 128; 8337 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8338 SizeType = UnsignedInt; 8339 PtrDiffType = SignedInt; 8340 IntPtrType = SignedInt; 8341 } 8342 8343 protected: 8344 void getTargetDefines(const LangOptions &Opts, 8345 MacroBuilder &Builder) const override { 8346 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 8347 if (SIMDLevel >= SIMD128) 8348 Builder.defineMacro("__wasm_simd128__"); 8349 } 8350 8351 private: 8352 bool 8353 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 8354 StringRef CPU, 8355 const std::vector<std::string> &FeaturesVec) const override { 8356 if (CPU == "bleeding-edge") 8357 Features["simd128"] = true; 8358 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 8359 } 8360 bool hasFeature(StringRef Feature) const final { 8361 return llvm::StringSwitch<bool>(Feature) 8362 .Case("simd128", SIMDLevel >= SIMD128) 8363 .Default(false); 8364 } 8365 bool handleTargetFeatures(std::vector<std::string> &Features, 8366 DiagnosticsEngine &Diags) final { 8367 for (const auto &Feature : Features) { 8368 if (Feature == "+simd128") { 8369 SIMDLevel = std::max(SIMDLevel, SIMD128); 8370 continue; 8371 } 8372 if (Feature == "-simd128") { 8373 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 8374 continue; 8375 } 8376 8377 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 8378 << "-target-feature"; 8379 return false; 8380 } 8381 return true; 8382 } 8383 bool setCPU(const std::string &Name) final { 8384 return llvm::StringSwitch<bool>(Name) 8385 .Case("mvp", true) 8386 .Case("bleeding-edge", true) 8387 .Case("generic", true) 8388 .Default(false); 8389 } 8390 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 8391 return llvm::makeArrayRef(BuiltinInfo, 8392 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 8393 } 8394 BuiltinVaListKind getBuiltinVaListKind() const final { 8395 return VoidPtrBuiltinVaList; 8396 } 8397 ArrayRef<const char *> getGCCRegNames() const final { 8398 return None; 8399 } 8400 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 8401 return None; 8402 } 8403 bool 8404 validateAsmConstraint(const char *&Name, 8405 TargetInfo::ConstraintInfo &Info) const final { 8406 return false; 8407 } 8408 const char *getClobbers() const final { return ""; } 8409 bool isCLZForZeroUndef() const final { return false; } 8410 bool hasInt128Type() const final { return true; } 8411 IntType getIntTypeByWidth(unsigned BitWidth, 8412 bool IsSigned) const final { 8413 // WebAssembly prefers long long for explicitly 64-bit integers. 8414 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8415 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8416 } 8417 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8418 bool IsSigned) const final { 8419 // WebAssembly uses long long for int_least64_t and int_fast64_t. 8420 return BitWidth == 64 8421 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8422 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 8423 } 8424 }; 8425 8426 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 8427 #define BUILTIN(ID, TYPE, ATTRS) \ 8428 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8429 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8430 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8431 #include "clang/Basic/BuiltinsWebAssembly.def" 8432 }; 8433 8434 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 8435 public: 8436 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 8437 const TargetOptions &Opts) 8438 : WebAssemblyTargetInfo(T, Opts) { 8439 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 8440 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 8441 } 8442 8443 protected: 8444 void getTargetDefines(const LangOptions &Opts, 8445 MacroBuilder &Builder) const override { 8446 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8447 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 8448 } 8449 }; 8450 8451 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 8452 public: 8453 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 8454 const TargetOptions &Opts) 8455 : WebAssemblyTargetInfo(T, Opts) { 8456 LongAlign = LongWidth = 64; 8457 PointerAlign = PointerWidth = 64; 8458 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8459 SizeType = UnsignedLong; 8460 PtrDiffType = SignedLong; 8461 IntPtrType = SignedLong; 8462 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 8463 } 8464 8465 protected: 8466 void getTargetDefines(const LangOptions &Opts, 8467 MacroBuilder &Builder) const override { 8468 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8469 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 8470 } 8471 }; 8472 8473 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 8474 #define BUILTIN(ID, TYPE, ATTRS) \ 8475 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8476 #include "clang/Basic/BuiltinsLe64.def" 8477 }; 8478 8479 static const unsigned SPIRAddrSpaceMap[] = { 8480 0, // Default 8481 1, // opencl_global 8482 3, // opencl_local 8483 2, // opencl_constant 8484 4, // opencl_generic 8485 0, // cuda_device 8486 0, // cuda_constant 8487 0 // cuda_shared 8488 }; 8489 class SPIRTargetInfo : public TargetInfo { 8490 public: 8491 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8492 : TargetInfo(Triple) { 8493 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 8494 "SPIR target must use unknown OS"); 8495 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 8496 "SPIR target must use unknown environment type"); 8497 TLSSupported = false; 8498 LongWidth = LongAlign = 64; 8499 AddrSpaceMap = &SPIRAddrSpaceMap; 8500 UseAddrSpaceMapMangling = true; 8501 // Define available target features 8502 // These must be defined in sorted order! 8503 NoAsmVariants = true; 8504 } 8505 void getTargetDefines(const LangOptions &Opts, 8506 MacroBuilder &Builder) const override { 8507 DefineStd(Builder, "SPIR", Opts); 8508 } 8509 bool hasFeature(StringRef Feature) const override { 8510 return Feature == "spir"; 8511 } 8512 8513 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8514 const char *getClobbers() const override { return ""; } 8515 ArrayRef<const char *> getGCCRegNames() const override { return None; } 8516 bool validateAsmConstraint(const char *&Name, 8517 TargetInfo::ConstraintInfo &info) const override { 8518 return true; 8519 } 8520 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8521 return None; 8522 } 8523 BuiltinVaListKind getBuiltinVaListKind() const override { 8524 return TargetInfo::VoidPtrBuiltinVaList; 8525 } 8526 8527 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 8528 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 8529 : CCCR_Warning; 8530 } 8531 8532 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8533 return CC_SpirFunction; 8534 } 8535 8536 void setSupportedOpenCLOpts() override { 8537 // Assume all OpenCL extensions and optional core features are supported 8538 // for SPIR since it is a generic target. 8539 getSupportedOpenCLOpts().supportAll(); 8540 } 8541 }; 8542 8543 class SPIR32TargetInfo : public SPIRTargetInfo { 8544 public: 8545 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8546 : SPIRTargetInfo(Triple, Opts) { 8547 PointerWidth = PointerAlign = 32; 8548 SizeType = TargetInfo::UnsignedInt; 8549 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8550 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8551 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8552 } 8553 void getTargetDefines(const LangOptions &Opts, 8554 MacroBuilder &Builder) const override { 8555 DefineStd(Builder, "SPIR32", Opts); 8556 } 8557 }; 8558 8559 class SPIR64TargetInfo : public SPIRTargetInfo { 8560 public: 8561 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8562 : SPIRTargetInfo(Triple, Opts) { 8563 PointerWidth = PointerAlign = 64; 8564 SizeType = TargetInfo::UnsignedLong; 8565 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8566 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8567 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8568 } 8569 void getTargetDefines(const LangOptions &Opts, 8570 MacroBuilder &Builder) const override { 8571 DefineStd(Builder, "SPIR64", Opts); 8572 } 8573 }; 8574 8575 class XCoreTargetInfo : public TargetInfo { 8576 static const Builtin::Info BuiltinInfo[]; 8577 public: 8578 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8579 : TargetInfo(Triple) { 8580 NoAsmVariants = true; 8581 LongLongAlign = 32; 8582 SuitableAlign = 32; 8583 DoubleAlign = LongDoubleAlign = 32; 8584 SizeType = UnsignedInt; 8585 PtrDiffType = SignedInt; 8586 IntPtrType = SignedInt; 8587 WCharType = UnsignedChar; 8588 WIntType = UnsignedInt; 8589 UseZeroLengthBitfieldAlignment = true; 8590 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8591 "-f64:32-a:0:32-n32"); 8592 } 8593 void getTargetDefines(const LangOptions &Opts, 8594 MacroBuilder &Builder) const override { 8595 Builder.defineMacro("__XS1B__"); 8596 } 8597 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8598 return llvm::makeArrayRef(BuiltinInfo, 8599 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8600 } 8601 BuiltinVaListKind getBuiltinVaListKind() const override { 8602 return TargetInfo::VoidPtrBuiltinVaList; 8603 } 8604 const char *getClobbers() const override { 8605 return ""; 8606 } 8607 ArrayRef<const char *> getGCCRegNames() const override { 8608 static const char * const GCCRegNames[] = { 8609 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8610 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8611 }; 8612 return llvm::makeArrayRef(GCCRegNames); 8613 } 8614 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8615 return None; 8616 } 8617 bool validateAsmConstraint(const char *&Name, 8618 TargetInfo::ConstraintInfo &Info) const override { 8619 return false; 8620 } 8621 int getEHDataRegisterNumber(unsigned RegNo) const override { 8622 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8623 return (RegNo < 2)? RegNo : -1; 8624 } 8625 bool allowsLargerPreferedTypeAlignment() const override { 8626 return false; 8627 } 8628 }; 8629 8630 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8631 #define BUILTIN(ID, TYPE, ATTRS) \ 8632 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8633 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8634 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8635 #include "clang/Basic/BuiltinsXCore.def" 8636 }; 8637 8638 // x86_32 Android target 8639 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8640 public: 8641 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8642 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8643 SuitableAlign = 32; 8644 LongDoubleWidth = 64; 8645 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8646 } 8647 }; 8648 8649 // x86_64 Android target 8650 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8651 public: 8652 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8653 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8654 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8655 } 8656 8657 bool useFloat128ManglingForLongDouble() const override { 8658 return true; 8659 } 8660 }; 8661 8662 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8663 class RenderScript32TargetInfo : public ARMleTargetInfo { 8664 public: 8665 RenderScript32TargetInfo(const llvm::Triple &Triple, 8666 const TargetOptions &Opts) 8667 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8668 Triple.getOSName(), 8669 Triple.getEnvironmentName()), 8670 Opts) { 8671 IsRenderScriptTarget = true; 8672 LongWidth = LongAlign = 64; 8673 } 8674 void getTargetDefines(const LangOptions &Opts, 8675 MacroBuilder &Builder) const override { 8676 Builder.defineMacro("__RENDERSCRIPT__"); 8677 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8678 } 8679 }; 8680 8681 // 64-bit RenderScript is aarch64 8682 class RenderScript64TargetInfo : public AArch64leTargetInfo { 8683 public: 8684 RenderScript64TargetInfo(const llvm::Triple &Triple, 8685 const TargetOptions &Opts) 8686 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 8687 Triple.getOSName(), 8688 Triple.getEnvironmentName()), 8689 Opts) { 8690 IsRenderScriptTarget = true; 8691 } 8692 8693 void getTargetDefines(const LangOptions &Opts, 8694 MacroBuilder &Builder) const override { 8695 Builder.defineMacro("__RENDERSCRIPT__"); 8696 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 8697 } 8698 }; 8699 8700 /// Information about a specific microcontroller. 8701 struct MCUInfo { 8702 const char *Name; 8703 const char *DefineName; 8704 }; 8705 8706 // This list should be kept up-to-date with AVRDevices.td in LLVM. 8707 static ArrayRef<MCUInfo> AVRMcus = { 8708 { "at90s1200", "__AVR_AT90S1200__" }, 8709 { "attiny11", "__AVR_ATtiny11__" }, 8710 { "attiny12", "__AVR_ATtiny12__" }, 8711 { "attiny15", "__AVR_ATtiny15__" }, 8712 { "attiny28", "__AVR_ATtiny28__" }, 8713 { "at90s2313", "__AVR_AT90S2313__" }, 8714 { "at90s2323", "__AVR_AT90S2323__" }, 8715 { "at90s2333", "__AVR_AT90S2333__" }, 8716 { "at90s2343", "__AVR_AT90S2343__" }, 8717 { "attiny22", "__AVR_ATtiny22__" }, 8718 { "attiny26", "__AVR_ATtiny26__" }, 8719 { "at86rf401", "__AVR_AT86RF401__" }, 8720 { "at90s4414", "__AVR_AT90S4414__" }, 8721 { "at90s4433", "__AVR_AT90S4433__" }, 8722 { "at90s4434", "__AVR_AT90S4434__" }, 8723 { "at90s8515", "__AVR_AT90S8515__" }, 8724 { "at90c8534", "__AVR_AT90c8534__" }, 8725 { "at90s8535", "__AVR_AT90S8535__" }, 8726 { "ata5272", "__AVR_ATA5272__" }, 8727 { "attiny13", "__AVR_ATtiny13__" }, 8728 { "attiny13a", "__AVR_ATtiny13A__" }, 8729 { "attiny2313", "__AVR_ATtiny2313__" }, 8730 { "attiny2313a", "__AVR_ATtiny2313A__" }, 8731 { "attiny24", "__AVR_ATtiny24__" }, 8732 { "attiny24a", "__AVR_ATtiny24A__" }, 8733 { "attiny4313", "__AVR_ATtiny4313__" }, 8734 { "attiny44", "__AVR_ATtiny44__" }, 8735 { "attiny44a", "__AVR_ATtiny44A__" }, 8736 { "attiny84", "__AVR_ATtiny84__" }, 8737 { "attiny84a", "__AVR_ATtiny84A__" }, 8738 { "attiny25", "__AVR_ATtiny25__" }, 8739 { "attiny45", "__AVR_ATtiny45__" }, 8740 { "attiny85", "__AVR_ATtiny85__" }, 8741 { "attiny261", "__AVR_ATtiny261__" }, 8742 { "attiny261a", "__AVR_ATtiny261A__" }, 8743 { "attiny461", "__AVR_ATtiny461__" }, 8744 { "attiny461a", "__AVR_ATtiny461A__" }, 8745 { "attiny861", "__AVR_ATtiny861__" }, 8746 { "attiny861a", "__AVR_ATtiny861A__" }, 8747 { "attiny87", "__AVR_ATtiny87__" }, 8748 { "attiny43u", "__AVR_ATtiny43U__" }, 8749 { "attiny48", "__AVR_ATtiny48__" }, 8750 { "attiny88", "__AVR_ATtiny88__" }, 8751 { "attiny828", "__AVR_ATtiny828__" }, 8752 { "at43usb355", "__AVR_AT43USB355__" }, 8753 { "at76c711", "__AVR_AT76C711__" }, 8754 { "atmega103", "__AVR_ATmega103__" }, 8755 { "at43usb320", "__AVR_AT43USB320__" }, 8756 { "attiny167", "__AVR_ATtiny167__" }, 8757 { "at90usb82", "__AVR_AT90USB82__" }, 8758 { "at90usb162", "__AVR_AT90USB162__" }, 8759 { "ata5505", "__AVR_ATA5505__" }, 8760 { "atmega8u2", "__AVR_ATmega8U2__" }, 8761 { "atmega16u2", "__AVR_ATmega16U2__" }, 8762 { "atmega32u2", "__AVR_ATmega32U2__" }, 8763 { "attiny1634", "__AVR_ATtiny1634__" }, 8764 { "atmega8", "__AVR_ATmega8__" }, 8765 { "ata6289", "__AVR_ATA6289__" }, 8766 { "atmega8a", "__AVR_ATmega8A__" }, 8767 { "ata6285", "__AVR_ATA6285__" }, 8768 { "ata6286", "__AVR_ATA6286__" }, 8769 { "atmega48", "__AVR_ATmega48__" }, 8770 { "atmega48a", "__AVR_ATmega48A__" }, 8771 { "atmega48pa", "__AVR_ATmega48PA__" }, 8772 { "atmega48p", "__AVR_ATmega48P__" }, 8773 { "atmega88", "__AVR_ATmega88__" }, 8774 { "atmega88a", "__AVR_ATmega88A__" }, 8775 { "atmega88p", "__AVR_ATmega88P__" }, 8776 { "atmega88pa", "__AVR_ATmega88PA__" }, 8777 { "atmega8515", "__AVR_ATmega8515__" }, 8778 { "atmega8535", "__AVR_ATmega8535__" }, 8779 { "atmega8hva", "__AVR_ATmega8HVA__" }, 8780 { "at90pwm1", "__AVR_AT90PWM1__" }, 8781 { "at90pwm2", "__AVR_AT90PWM2__" }, 8782 { "at90pwm2b", "__AVR_AT90PWM2B__" }, 8783 { "at90pwm3", "__AVR_AT90PWM3__" }, 8784 { "at90pwm3b", "__AVR_AT90PWM3B__" }, 8785 { "at90pwm81", "__AVR_AT90PWM81__" }, 8786 { "ata5790", "__AVR_ATA5790__" }, 8787 { "ata5795", "__AVR_ATA5795__" }, 8788 { "atmega16", "__AVR_ATmega16__" }, 8789 { "atmega16a", "__AVR_ATmega16A__" }, 8790 { "atmega161", "__AVR_ATmega161__" }, 8791 { "atmega162", "__AVR_ATmega162__" }, 8792 { "atmega163", "__AVR_ATmega163__" }, 8793 { "atmega164a", "__AVR_ATmega164A__" }, 8794 { "atmega164p", "__AVR_ATmega164P__" }, 8795 { "atmega164pa", "__AVR_ATmega164PA__" }, 8796 { "atmega165", "__AVR_ATmega165__" }, 8797 { "atmega165a", "__AVR_ATmega165A__" }, 8798 { "atmega165p", "__AVR_ATmega165P__" }, 8799 { "atmega165pa", "__AVR_ATmega165PA__" }, 8800 { "atmega168", "__AVR_ATmega168__" }, 8801 { "atmega168a", "__AVR_ATmega168A__" }, 8802 { "atmega168p", "__AVR_ATmega168P__" }, 8803 { "atmega168pa", "__AVR_ATmega168PA__" }, 8804 { "atmega169", "__AVR_ATmega169__" }, 8805 { "atmega169a", "__AVR_ATmega169A__" }, 8806 { "atmega169p", "__AVR_ATmega169P__" }, 8807 { "atmega169pa", "__AVR_ATmega169PA__" }, 8808 { "atmega32", "__AVR_ATmega32__" }, 8809 { "atmega32a", "__AVR_ATmega32A__" }, 8810 { "atmega323", "__AVR_ATmega323__" }, 8811 { "atmega324a", "__AVR_ATmega324A__" }, 8812 { "atmega324p", "__AVR_ATmega324P__" }, 8813 { "atmega324pa", "__AVR_ATmega324PA__" }, 8814 { "atmega325", "__AVR_ATmega325__" }, 8815 { "atmega325a", "__AVR_ATmega325A__" }, 8816 { "atmega325p", "__AVR_ATmega325P__" }, 8817 { "atmega325pa", "__AVR_ATmega325PA__" }, 8818 { "atmega3250", "__AVR_ATmega3250__" }, 8819 { "atmega3250a", "__AVR_ATmega3250A__" }, 8820 { "atmega3250p", "__AVR_ATmega3250P__" }, 8821 { "atmega3250pa", "__AVR_ATmega3250PA__" }, 8822 { "atmega328", "__AVR_ATmega328__" }, 8823 { "atmega328p", "__AVR_ATmega328P__" }, 8824 { "atmega329", "__AVR_ATmega329__" }, 8825 { "atmega329a", "__AVR_ATmega329A__" }, 8826 { "atmega329p", "__AVR_ATmega329P__" }, 8827 { "atmega329pa", "__AVR_ATmega329PA__" }, 8828 { "atmega3290", "__AVR_ATmega3290__" }, 8829 { "atmega3290a", "__AVR_ATmega3290A__" }, 8830 { "atmega3290p", "__AVR_ATmega3290P__" }, 8831 { "atmega3290pa", "__AVR_ATmega3290PA__" }, 8832 { "atmega406", "__AVR_ATmega406__" }, 8833 { "atmega64", "__AVR_ATmega64__" }, 8834 { "atmega64a", "__AVR_ATmega64A__" }, 8835 { "atmega640", "__AVR_ATmega640__" }, 8836 { "atmega644", "__AVR_ATmega644__" }, 8837 { "atmega644a", "__AVR_ATmega644A__" }, 8838 { "atmega644p", "__AVR_ATmega644P__" }, 8839 { "atmega644pa", "__AVR_ATmega644PA__" }, 8840 { "atmega645", "__AVR_ATmega645__" }, 8841 { "atmega645a", "__AVR_ATmega645A__" }, 8842 { "atmega645p", "__AVR_ATmega645P__" }, 8843 { "atmega649", "__AVR_ATmega649__" }, 8844 { "atmega649a", "__AVR_ATmega649A__" }, 8845 { "atmega649p", "__AVR_ATmega649P__" }, 8846 { "atmega6450", "__AVR_ATmega6450__" }, 8847 { "atmega6450a", "__AVR_ATmega6450A__" }, 8848 { "atmega6450p", "__AVR_ATmega6450P__" }, 8849 { "atmega6490", "__AVR_ATmega6490__" }, 8850 { "atmega6490a", "__AVR_ATmega6490A__" }, 8851 { "atmega6490p", "__AVR_ATmega6490P__" }, 8852 { "atmega64rfr2", "__AVR_ATmega64RFR2__" }, 8853 { "atmega644rfr2", "__AVR_ATmega644RFR2__" }, 8854 { "atmega16hva", "__AVR_ATmega16HVA__" }, 8855 { "atmega16hva2", "__AVR_ATmega16HVA2__" }, 8856 { "atmega16hvb", "__AVR_ATmega16HVB__" }, 8857 { "atmega16hvbrevb", "__AVR_ATmega16HVBREVB__" }, 8858 { "atmega32hvb", "__AVR_ATmega32HVB__" }, 8859 { "atmega32hvbrevb", "__AVR_ATmega32HVBREVB__" }, 8860 { "atmega64hve", "__AVR_ATmega64HVE__" }, 8861 { "at90can32", "__AVR_AT90CAN32__" }, 8862 { "at90can64", "__AVR_AT90CAN64__" }, 8863 { "at90pwm161", "__AVR_AT90PWM161__" }, 8864 { "at90pwm216", "__AVR_AT90PWM216__" }, 8865 { "at90pwm316", "__AVR_AT90PWM316__" }, 8866 { "atmega32c1", "__AVR_ATmega32C1__" }, 8867 { "atmega64c1", "__AVR_ATmega64C1__" }, 8868 { "atmega16m1", "__AVR_ATmega16M1__" }, 8869 { "atmega32m1", "__AVR_ATmega32M1__" }, 8870 { "atmega64m1", "__AVR_ATmega64M1__" }, 8871 { "atmega16u4", "__AVR_ATmega16U4__" }, 8872 { "atmega32u4", "__AVR_ATmega32U4__" }, 8873 { "atmega32u6", "__AVR_ATmega32U6__" }, 8874 { "at90usb646", "__AVR_AT90USB646__" }, 8875 { "at90usb647", "__AVR_AT90USB647__" }, 8876 { "at90scr100", "__AVR_AT90SCR100__" }, 8877 { "at94k", "__AVR_AT94K__" }, 8878 { "m3000", "__AVR_AT000__" }, 8879 { "atmega128", "__AVR_ATmega128__" }, 8880 { "atmega128a", "__AVR_ATmega128A__" }, 8881 { "atmega1280", "__AVR_ATmega1280__" }, 8882 { "atmega1281", "__AVR_ATmega1281__" }, 8883 { "atmega1284", "__AVR_ATmega1284__" }, 8884 { "atmega1284p", "__AVR_ATmega1284P__" }, 8885 { "atmega128rfa1", "__AVR_ATmega128RFA1__" }, 8886 { "atmega128rfr2", "__AVR_ATmega128RFR2__" }, 8887 { "atmega1284rfr2", "__AVR_ATmega1284RFR2__" }, 8888 { "at90can128", "__AVR_AT90CAN128__" }, 8889 { "at90usb1286", "__AVR_AT90USB1286__" }, 8890 { "at90usb1287", "__AVR_AT90USB1287__" }, 8891 { "atmega2560", "__AVR_ATmega2560__" }, 8892 { "atmega2561", "__AVR_ATmega2561__" }, 8893 { "atmega256rfr2", "__AVR_ATmega256RFR2__" }, 8894 { "atmega2564rfr2", "__AVR_ATmega2564RFR2__" }, 8895 { "atxmega16a4", "__AVR_ATxmega16A4__" }, 8896 { "atxmega16a4u", "__AVR_ATxmega16a4U__" }, 8897 { "atxmega16c4", "__AVR_ATxmega16C4__" }, 8898 { "atxmega16d4", "__AVR_ATxmega16D4__" }, 8899 { "atxmega32a4", "__AVR_ATxmega32A4__" }, 8900 { "atxmega32a4u", "__AVR_ATxmega32A4U__" }, 8901 { "atxmega32c4", "__AVR_ATxmega32C4__" }, 8902 { "atxmega32d4", "__AVR_ATxmega32D4__" }, 8903 { "atxmega32e5", "__AVR_ATxmega32E5__" }, 8904 { "atxmega16e5", "__AVR_ATxmega16E5__" }, 8905 { "atxmega8e5", "__AVR_ATxmega8E5__" }, 8906 { "atxmega32x1", "__AVR_ATxmega32X1__" }, 8907 { "atxmega64a3", "__AVR_ATxmega64A3__" }, 8908 { "atxmega64a3u", "__AVR_ATxmega64A3U__" }, 8909 { "atxmega64a4u", "__AVR_ATxmega64A4U__" }, 8910 { "atxmega64b1", "__AVR_ATxmega64B1__" }, 8911 { "atxmega64b3", "__AVR_ATxmega64B3__" }, 8912 { "atxmega64c3", "__AVR_ATxmega64C3__" }, 8913 { "atxmega64d3", "__AVR_ATxmega64D3__" }, 8914 { "atxmega64d4", "__AVR_ATxmega64D4__" }, 8915 { "atxmega64a1", "__AVR_ATxmega64A1__" }, 8916 { "atxmega64a1u", "__AVR_ATxmega64A1U__" }, 8917 { "atxmega128a3", "__AVR_ATxmega128A3__" }, 8918 { "atxmega128a3u", "__AVR_ATxmega128A3U__" }, 8919 { "atxmega128b1", "__AVR_ATxmega128B1__" }, 8920 { "atxmega128b3", "__AVR_ATxmega128B3__" }, 8921 { "atxmega128c3", "__AVR_ATxmega128C3__" }, 8922 { "atxmega128d3", "__AVR_ATxmega128D3__" }, 8923 { "atxmega128d4", "__AVR_ATxmega128D4__" }, 8924 { "atxmega192a3", "__AVR_ATxmega192A3__" }, 8925 { "atxmega192a3u", "__AVR_ATxmega192A3U__" }, 8926 { "atxmega192c3", "__AVR_ATxmega192C3__" }, 8927 { "atxmega192d3", "__AVR_ATxmega192D3__" }, 8928 { "atxmega256a3", "__AVR_ATxmega256A3__" }, 8929 { "atxmega256a3u", "__AVR_ATxmega256A3U__" }, 8930 { "atxmega256a3b", "__AVR_ATxmega256A3B__" }, 8931 { "atxmega256a3bu", "__AVR_ATxmega256A3BU__" }, 8932 { "atxmega256c3", "__AVR_ATxmega256C3__" }, 8933 { "atxmega256d3", "__AVR_ATxmega256D3__" }, 8934 { "atxmega384c3", "__AVR_ATxmega384C3__" }, 8935 { "atxmega384d3", "__AVR_ATxmega384D3__" }, 8936 { "atxmega128a1", "__AVR_ATxmega128A1__" }, 8937 { "atxmega128a1u", "__AVR_ATxmega128A1U__" }, 8938 { "atxmega128a4u", "__AVR_ATxmega128a4U__" }, 8939 { "attiny4", "__AVR_ATtiny4__" }, 8940 { "attiny5", "__AVR_ATtiny5__" }, 8941 { "attiny9", "__AVR_ATtiny9__" }, 8942 { "attiny10", "__AVR_ATtiny10__" }, 8943 { "attiny20", "__AVR_ATtiny20__" }, 8944 { "attiny40", "__AVR_ATtiny40__" }, 8945 { "attiny102", "__AVR_ATtiny102__" }, 8946 { "attiny104", "__AVR_ATtiny104__" }, 8947 }; 8948 8949 // AVR Target 8950 class AVRTargetInfo : public TargetInfo { 8951 public: 8952 AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8953 : TargetInfo(Triple) { 8954 TLSSupported = false; 8955 PointerWidth = 16; 8956 PointerAlign = 8; 8957 IntWidth = 16; 8958 IntAlign = 8; 8959 LongWidth = 32; 8960 LongAlign = 8; 8961 LongLongWidth = 64; 8962 LongLongAlign = 8; 8963 SuitableAlign = 8; 8964 DefaultAlignForAttributeAligned = 8; 8965 HalfWidth = 16; 8966 HalfAlign = 8; 8967 FloatWidth = 32; 8968 FloatAlign = 8; 8969 DoubleWidth = 32; 8970 DoubleAlign = 8; 8971 DoubleFormat = &llvm::APFloat::IEEEsingle(); 8972 LongDoubleWidth = 32; 8973 LongDoubleAlign = 8; 8974 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 8975 SizeType = UnsignedInt; 8976 PtrDiffType = SignedInt; 8977 IntPtrType = SignedInt; 8978 Char16Type = UnsignedInt; 8979 WCharType = SignedInt; 8980 WIntType = SignedInt; 8981 Char32Type = UnsignedLong; 8982 SigAtomicType = SignedChar; 8983 resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64" 8984 "-f32:32:32-f64:64:64-n8"); 8985 } 8986 8987 void getTargetDefines(const LangOptions &Opts, 8988 MacroBuilder &Builder) const override { 8989 Builder.defineMacro("AVR"); 8990 Builder.defineMacro("__AVR"); 8991 Builder.defineMacro("__AVR__"); 8992 8993 if (!this->CPU.empty()) { 8994 auto It = std::find_if(AVRMcus.begin(), AVRMcus.end(), 8995 [&](const MCUInfo &Info) { return Info.Name == this->CPU; }); 8996 8997 if (It != AVRMcus.end()) 8998 Builder.defineMacro(It->DefineName); 8999 } 9000 } 9001 9002 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 9003 return None; 9004 } 9005 9006 BuiltinVaListKind getBuiltinVaListKind() const override { 9007 return TargetInfo::VoidPtrBuiltinVaList; 9008 } 9009 9010 const char *getClobbers() const override { 9011 return ""; 9012 } 9013 9014 ArrayRef<const char *> getGCCRegNames() const override { 9015 static const char * const GCCRegNames[] = { 9016 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 9017 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 9018 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 9019 "r24", "r25", "X", "Y", "Z", "SP" 9020 }; 9021 return llvm::makeArrayRef(GCCRegNames); 9022 } 9023 9024 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 9025 return None; 9026 } 9027 9028 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 9029 static const TargetInfo::AddlRegName AddlRegNames[] = { 9030 { { "r26", "r27"}, 26 }, 9031 { { "r28", "r29"}, 27 }, 9032 { { "r30", "r31"}, 28 }, 9033 { { "SPL", "SPH"}, 29 }, 9034 }; 9035 return llvm::makeArrayRef(AddlRegNames); 9036 } 9037 9038 bool validateAsmConstraint(const char *&Name, 9039 TargetInfo::ConstraintInfo &Info) const override { 9040 // There aren't any multi-character AVR specific constraints. 9041 if (StringRef(Name).size() > 1) return false; 9042 9043 switch (*Name) { 9044 default: return false; 9045 case 'a': // Simple upper registers 9046 case 'b': // Base pointer registers pairs 9047 case 'd': // Upper register 9048 case 'l': // Lower registers 9049 case 'e': // Pointer register pairs 9050 case 'q': // Stack pointer register 9051 case 'r': // Any register 9052 case 'w': // Special upper register pairs 9053 case 't': // Temporary register 9054 case 'x': case 'X': // Pointer register pair X 9055 case 'y': case 'Y': // Pointer register pair Y 9056 case 'z': case 'Z': // Pointer register pair Z 9057 Info.setAllowsRegister(); 9058 return true; 9059 case 'I': // 6-bit positive integer constant 9060 Info.setRequiresImmediate(0, 63); 9061 return true; 9062 case 'J': // 6-bit negative integer constant 9063 Info.setRequiresImmediate(-63, 0); 9064 return true; 9065 case 'K': // Integer constant (Range: 2) 9066 Info.setRequiresImmediate(2); 9067 return true; 9068 case 'L': // Integer constant (Range: 0) 9069 Info.setRequiresImmediate(0); 9070 return true; 9071 case 'M': // 8-bit integer constant 9072 Info.setRequiresImmediate(0, 0xff); 9073 return true; 9074 case 'N': // Integer constant (Range: -1) 9075 Info.setRequiresImmediate(-1); 9076 return true; 9077 case 'O': // Integer constant (Range: 8, 16, 24) 9078 Info.setRequiresImmediate({8, 16, 24}); 9079 return true; 9080 case 'P': // Integer constant (Range: 1) 9081 Info.setRequiresImmediate(1); 9082 return true; 9083 case 'R': // Integer constant (Range: -6 to 5) 9084 Info.setRequiresImmediate(-6, 5); 9085 return true; 9086 case 'G': // Floating point constant 9087 case 'Q': // A memory address based on Y or Z pointer with displacement. 9088 return true; 9089 } 9090 9091 return false; 9092 } 9093 9094 IntType getIntTypeByWidth(unsigned BitWidth, 9095 bool IsSigned) const final { 9096 // AVR prefers int for 16-bit integers. 9097 return BitWidth == 16 ? (IsSigned ? SignedInt : UnsignedInt) 9098 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 9099 } 9100 9101 IntType getLeastIntTypeByWidth(unsigned BitWidth, 9102 bool IsSigned) const final { 9103 // AVR uses int for int_least16_t and int_fast16_t. 9104 return BitWidth == 16 9105 ? (IsSigned ? SignedInt : UnsignedInt) 9106 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 9107 } 9108 9109 bool setCPU(const std::string &Name) override { 9110 bool IsFamily = llvm::StringSwitch<bool>(Name) 9111 .Case("avr1", true) 9112 .Case("avr2", true) 9113 .Case("avr25", true) 9114 .Case("avr3", true) 9115 .Case("avr31", true) 9116 .Case("avr35", true) 9117 .Case("avr4", true) 9118 .Case("avr5", true) 9119 .Case("avr51", true) 9120 .Case("avr6", true) 9121 .Case("avrxmega1", true) 9122 .Case("avrxmega2", true) 9123 .Case("avrxmega3", true) 9124 .Case("avrxmega4", true) 9125 .Case("avrxmega5", true) 9126 .Case("avrxmega6", true) 9127 .Case("avrxmega7", true) 9128 .Case("avrtiny", true) 9129 .Default(false); 9130 9131 if (IsFamily) this->CPU = Name; 9132 9133 bool IsMCU = std::find_if(AVRMcus.begin(), AVRMcus.end(), 9134 [&](const MCUInfo &Info) { return Info.Name == Name; }) != AVRMcus.end(); 9135 9136 if (IsMCU) this->CPU = Name; 9137 9138 return IsFamily || IsMCU; 9139 } 9140 9141 protected: 9142 std::string CPU; 9143 }; 9144 9145 } // end anonymous namespace 9146 9147 //===----------------------------------------------------------------------===// 9148 // Driver code 9149 //===----------------------------------------------------------------------===// 9150 9151 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 9152 const TargetOptions &Opts) { 9153 llvm::Triple::OSType os = Triple.getOS(); 9154 9155 switch (Triple.getArch()) { 9156 default: 9157 return nullptr; 9158 9159 case llvm::Triple::xcore: 9160 return new XCoreTargetInfo(Triple, Opts); 9161 9162 case llvm::Triple::hexagon: 9163 return new HexagonTargetInfo(Triple, Opts); 9164 9165 case llvm::Triple::lanai: 9166 return new LanaiTargetInfo(Triple, Opts); 9167 9168 case llvm::Triple::aarch64: 9169 if (Triple.isOSDarwin()) 9170 return new DarwinAArch64TargetInfo(Triple, Opts); 9171 9172 switch (os) { 9173 case llvm::Triple::CloudABI: 9174 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 9175 case llvm::Triple::FreeBSD: 9176 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9177 case llvm::Triple::Fuchsia: 9178 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9179 case llvm::Triple::Linux: 9180 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9181 case llvm::Triple::NetBSD: 9182 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9183 case llvm::Triple::OpenBSD: 9184 return new OpenBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9185 default: 9186 return new AArch64leTargetInfo(Triple, Opts); 9187 } 9188 9189 case llvm::Triple::aarch64_be: 9190 switch (os) { 9191 case llvm::Triple::FreeBSD: 9192 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9193 case llvm::Triple::Fuchsia: 9194 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9195 case llvm::Triple::Linux: 9196 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9197 case llvm::Triple::NetBSD: 9198 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9199 default: 9200 return new AArch64beTargetInfo(Triple, Opts); 9201 } 9202 9203 case llvm::Triple::arm: 9204 case llvm::Triple::thumb: 9205 if (Triple.isOSBinFormatMachO()) 9206 return new DarwinARMTargetInfo(Triple, Opts); 9207 9208 switch (os) { 9209 case llvm::Triple::CloudABI: 9210 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts); 9211 case llvm::Triple::Linux: 9212 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 9213 case llvm::Triple::FreeBSD: 9214 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9215 case llvm::Triple::NetBSD: 9216 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9217 case llvm::Triple::OpenBSD: 9218 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9219 case llvm::Triple::Bitrig: 9220 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 9221 case llvm::Triple::RTEMS: 9222 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 9223 case llvm::Triple::NaCl: 9224 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 9225 case llvm::Triple::Win32: 9226 switch (Triple.getEnvironment()) { 9227 case llvm::Triple::Cygnus: 9228 return new CygwinARMTargetInfo(Triple, Opts); 9229 case llvm::Triple::GNU: 9230 return new MinGWARMTargetInfo(Triple, Opts); 9231 case llvm::Triple::Itanium: 9232 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 9233 case llvm::Triple::MSVC: 9234 default: // Assume MSVC for unknown environments 9235 return new MicrosoftARMleTargetInfo(Triple, Opts); 9236 } 9237 default: 9238 return new ARMleTargetInfo(Triple, Opts); 9239 } 9240 9241 case llvm::Triple::armeb: 9242 case llvm::Triple::thumbeb: 9243 if (Triple.isOSDarwin()) 9244 return new DarwinARMTargetInfo(Triple, Opts); 9245 9246 switch (os) { 9247 case llvm::Triple::Linux: 9248 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9249 case llvm::Triple::FreeBSD: 9250 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9251 case llvm::Triple::NetBSD: 9252 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9253 case llvm::Triple::OpenBSD: 9254 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9255 case llvm::Triple::Bitrig: 9256 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9257 case llvm::Triple::RTEMS: 9258 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9259 case llvm::Triple::NaCl: 9260 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9261 default: 9262 return new ARMbeTargetInfo(Triple, Opts); 9263 } 9264 9265 case llvm::Triple::avr: 9266 return new AVRTargetInfo(Triple, Opts); 9267 case llvm::Triple::bpfeb: 9268 case llvm::Triple::bpfel: 9269 return new BPFTargetInfo(Triple, Opts); 9270 9271 case llvm::Triple::msp430: 9272 return new MSP430TargetInfo(Triple, Opts); 9273 9274 case llvm::Triple::mips: 9275 switch (os) { 9276 case llvm::Triple::Linux: 9277 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9278 case llvm::Triple::RTEMS: 9279 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9280 case llvm::Triple::FreeBSD: 9281 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9282 case llvm::Triple::NetBSD: 9283 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9284 default: 9285 return new MipsTargetInfo(Triple, Opts); 9286 } 9287 9288 case llvm::Triple::mipsel: 9289 switch (os) { 9290 case llvm::Triple::Linux: 9291 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9292 case llvm::Triple::RTEMS: 9293 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9294 case llvm::Triple::FreeBSD: 9295 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9296 case llvm::Triple::NetBSD: 9297 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9298 case llvm::Triple::NaCl: 9299 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 9300 default: 9301 return new MipsTargetInfo(Triple, Opts); 9302 } 9303 9304 case llvm::Triple::mips64: 9305 switch (os) { 9306 case llvm::Triple::Linux: 9307 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9308 case llvm::Triple::RTEMS: 9309 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9310 case llvm::Triple::FreeBSD: 9311 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9312 case llvm::Triple::NetBSD: 9313 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9314 case llvm::Triple::OpenBSD: 9315 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9316 default: 9317 return new MipsTargetInfo(Triple, Opts); 9318 } 9319 9320 case llvm::Triple::mips64el: 9321 switch (os) { 9322 case llvm::Triple::Linux: 9323 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9324 case llvm::Triple::RTEMS: 9325 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9326 case llvm::Triple::FreeBSD: 9327 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9328 case llvm::Triple::NetBSD: 9329 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9330 case llvm::Triple::OpenBSD: 9331 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9332 default: 9333 return new MipsTargetInfo(Triple, Opts); 9334 } 9335 9336 case llvm::Triple::le32: 9337 switch (os) { 9338 case llvm::Triple::NaCl: 9339 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 9340 default: 9341 return nullptr; 9342 } 9343 9344 case llvm::Triple::le64: 9345 return new Le64TargetInfo(Triple, Opts); 9346 9347 case llvm::Triple::ppc: 9348 if (Triple.isOSDarwin()) 9349 return new DarwinPPC32TargetInfo(Triple, Opts); 9350 switch (os) { 9351 case llvm::Triple::Linux: 9352 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 9353 case llvm::Triple::FreeBSD: 9354 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9355 case llvm::Triple::NetBSD: 9356 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9357 case llvm::Triple::OpenBSD: 9358 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9359 case llvm::Triple::RTEMS: 9360 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 9361 default: 9362 return new PPC32TargetInfo(Triple, Opts); 9363 } 9364 9365 case llvm::Triple::ppc64: 9366 if (Triple.isOSDarwin()) 9367 return new DarwinPPC64TargetInfo(Triple, Opts); 9368 switch (os) { 9369 case llvm::Triple::Linux: 9370 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9371 case llvm::Triple::Lv2: 9372 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 9373 case llvm::Triple::FreeBSD: 9374 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9375 case llvm::Triple::NetBSD: 9376 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9377 default: 9378 return new PPC64TargetInfo(Triple, Opts); 9379 } 9380 9381 case llvm::Triple::ppc64le: 9382 switch (os) { 9383 case llvm::Triple::Linux: 9384 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9385 case llvm::Triple::NetBSD: 9386 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9387 default: 9388 return new PPC64TargetInfo(Triple, Opts); 9389 } 9390 9391 case llvm::Triple::nvptx: 9392 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/32); 9393 case llvm::Triple::nvptx64: 9394 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64); 9395 9396 case llvm::Triple::amdgcn: 9397 case llvm::Triple::r600: 9398 return new AMDGPUTargetInfo(Triple, Opts); 9399 9400 case llvm::Triple::sparc: 9401 switch (os) { 9402 case llvm::Triple::Linux: 9403 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9404 case llvm::Triple::Solaris: 9405 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9406 case llvm::Triple::NetBSD: 9407 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9408 case llvm::Triple::OpenBSD: 9409 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9410 case llvm::Triple::RTEMS: 9411 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9412 default: 9413 return new SparcV8TargetInfo(Triple, Opts); 9414 } 9415 9416 // The 'sparcel' architecture copies all the above cases except for Solaris. 9417 case llvm::Triple::sparcel: 9418 switch (os) { 9419 case llvm::Triple::Linux: 9420 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9421 case llvm::Triple::NetBSD: 9422 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9423 case llvm::Triple::OpenBSD: 9424 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9425 case llvm::Triple::RTEMS: 9426 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9427 default: 9428 return new SparcV8elTargetInfo(Triple, Opts); 9429 } 9430 9431 case llvm::Triple::sparcv9: 9432 switch (os) { 9433 case llvm::Triple::Linux: 9434 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9435 case llvm::Triple::Solaris: 9436 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9437 case llvm::Triple::NetBSD: 9438 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9439 case llvm::Triple::OpenBSD: 9440 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9441 case llvm::Triple::FreeBSD: 9442 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9443 default: 9444 return new SparcV9TargetInfo(Triple, Opts); 9445 } 9446 9447 case llvm::Triple::systemz: 9448 switch (os) { 9449 case llvm::Triple::Linux: 9450 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 9451 default: 9452 return new SystemZTargetInfo(Triple, Opts); 9453 } 9454 9455 case llvm::Triple::tce: 9456 return new TCETargetInfo(Triple, Opts); 9457 9458 case llvm::Triple::tcele: 9459 return new TCELETargetInfo(Triple, Opts); 9460 9461 case llvm::Triple::x86: 9462 if (Triple.isOSDarwin()) 9463 return new DarwinI386TargetInfo(Triple, Opts); 9464 9465 switch (os) { 9466 case llvm::Triple::CloudABI: 9467 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 9468 case llvm::Triple::Linux: { 9469 switch (Triple.getEnvironment()) { 9470 default: 9471 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 9472 case llvm::Triple::Android: 9473 return new AndroidX86_32TargetInfo(Triple, Opts); 9474 } 9475 } 9476 case llvm::Triple::DragonFly: 9477 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9478 case llvm::Triple::NetBSD: 9479 return new NetBSDI386TargetInfo(Triple, Opts); 9480 case llvm::Triple::OpenBSD: 9481 return new OpenBSDI386TargetInfo(Triple, Opts); 9482 case llvm::Triple::Bitrig: 9483 return new BitrigI386TargetInfo(Triple, Opts); 9484 case llvm::Triple::FreeBSD: 9485 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9486 case llvm::Triple::KFreeBSD: 9487 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9488 case llvm::Triple::Minix: 9489 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 9490 case llvm::Triple::Solaris: 9491 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 9492 case llvm::Triple::Win32: { 9493 switch (Triple.getEnvironment()) { 9494 case llvm::Triple::Cygnus: 9495 return new CygwinX86_32TargetInfo(Triple, Opts); 9496 case llvm::Triple::GNU: 9497 return new MinGWX86_32TargetInfo(Triple, Opts); 9498 case llvm::Triple::Itanium: 9499 case llvm::Triple::MSVC: 9500 default: // Assume MSVC for unknown environments 9501 return new MicrosoftX86_32TargetInfo(Triple, Opts); 9502 } 9503 } 9504 case llvm::Triple::Haiku: 9505 return new HaikuX86_32TargetInfo(Triple, Opts); 9506 case llvm::Triple::RTEMS: 9507 return new RTEMSX86_32TargetInfo(Triple, Opts); 9508 case llvm::Triple::NaCl: 9509 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 9510 case llvm::Triple::ELFIAMCU: 9511 return new MCUX86_32TargetInfo(Triple, Opts); 9512 default: 9513 return new X86_32TargetInfo(Triple, Opts); 9514 } 9515 9516 case llvm::Triple::x86_64: 9517 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 9518 return new DarwinX86_64TargetInfo(Triple, Opts); 9519 9520 switch (os) { 9521 case llvm::Triple::CloudABI: 9522 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 9523 case llvm::Triple::Linux: { 9524 switch (Triple.getEnvironment()) { 9525 default: 9526 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 9527 case llvm::Triple::Android: 9528 return new AndroidX86_64TargetInfo(Triple, Opts); 9529 } 9530 } 9531 case llvm::Triple::DragonFly: 9532 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9533 case llvm::Triple::NetBSD: 9534 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9535 case llvm::Triple::OpenBSD: 9536 return new OpenBSDX86_64TargetInfo(Triple, Opts); 9537 case llvm::Triple::Bitrig: 9538 return new BitrigX86_64TargetInfo(Triple, Opts); 9539 case llvm::Triple::FreeBSD: 9540 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9541 case llvm::Triple::Fuchsia: 9542 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts); 9543 case llvm::Triple::KFreeBSD: 9544 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9545 case llvm::Triple::Solaris: 9546 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 9547 case llvm::Triple::Win32: { 9548 switch (Triple.getEnvironment()) { 9549 case llvm::Triple::Cygnus: 9550 return new CygwinX86_64TargetInfo(Triple, Opts); 9551 case llvm::Triple::GNU: 9552 return new MinGWX86_64TargetInfo(Triple, Opts); 9553 case llvm::Triple::MSVC: 9554 default: // Assume MSVC for unknown environments 9555 return new MicrosoftX86_64TargetInfo(Triple, Opts); 9556 } 9557 } 9558 case llvm::Triple::Haiku: 9559 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 9560 case llvm::Triple::NaCl: 9561 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 9562 case llvm::Triple::PS4: 9563 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 9564 default: 9565 return new X86_64TargetInfo(Triple, Opts); 9566 } 9567 9568 case llvm::Triple::spir: { 9569 if (Triple.getOS() != llvm::Triple::UnknownOS || 9570 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9571 return nullptr; 9572 return new SPIR32TargetInfo(Triple, Opts); 9573 } 9574 case llvm::Triple::spir64: { 9575 if (Triple.getOS() != llvm::Triple::UnknownOS || 9576 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9577 return nullptr; 9578 return new SPIR64TargetInfo(Triple, Opts); 9579 } 9580 case llvm::Triple::wasm32: 9581 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9582 Triple.getVendor() != llvm::Triple::UnknownVendor || 9583 Triple.getOS() != llvm::Triple::UnknownOS || 9584 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9585 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9586 return nullptr; 9587 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 9588 case llvm::Triple::wasm64: 9589 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9590 Triple.getVendor() != llvm::Triple::UnknownVendor || 9591 Triple.getOS() != llvm::Triple::UnknownOS || 9592 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9593 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9594 return nullptr; 9595 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 9596 9597 case llvm::Triple::renderscript32: 9598 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 9599 case llvm::Triple::renderscript64: 9600 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 9601 } 9602 } 9603 9604 /// CreateTargetInfo - Return the target info object for the specified target 9605 /// options. 9606 TargetInfo * 9607 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 9608 const std::shared_ptr<TargetOptions> &Opts) { 9609 llvm::Triple Triple(Opts->Triple); 9610 9611 // Construct the target 9612 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 9613 if (!Target) { 9614 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 9615 return nullptr; 9616 } 9617 Target->TargetOpts = Opts; 9618 9619 // Set the target CPU if specified. 9620 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 9621 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 9622 return nullptr; 9623 } 9624 9625 // Set the target ABI if specified. 9626 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 9627 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 9628 return nullptr; 9629 } 9630 9631 // Set the fp math unit. 9632 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 9633 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 9634 return nullptr; 9635 } 9636 9637 // Compute the default target features, we need the target to handle this 9638 // because features may have dependencies on one another. 9639 llvm::StringMap<bool> Features; 9640 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 9641 Opts->FeaturesAsWritten)) 9642 return nullptr; 9643 9644 // Add the features to the compile options. 9645 Opts->Features.clear(); 9646 for (const auto &F : Features) 9647 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 9648 9649 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 9650 return nullptr; 9651 9652 Target->setSupportedOpenCLOpts(); 9653 Target->setOpenCLExtensionOpts(); 9654 9655 if (!Target->validateTarget(Diags)) 9656 return nullptr; 9657 9658 return Target.release(); 9659 } 9660