1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "clang/Basic/Version.h" 23 #include "llvm/ADT/APFloat.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringExtras.h" 26 #include "llvm/ADT/StringRef.h" 27 #include "llvm/ADT/StringSwitch.h" 28 #include "llvm/ADT/Triple.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/TargetParser.h" 32 #include <algorithm> 33 #include <memory> 34 35 using namespace clang; 36 37 //===----------------------------------------------------------------------===// 38 // Common code shared among targets. 39 //===----------------------------------------------------------------------===// 40 41 /// DefineStd - Define a macro name and standard variants. For example if 42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 43 /// when in GNU mode. 44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 45 const LangOptions &Opts) { 46 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 47 48 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 49 // in the user's namespace. 50 if (Opts.GNUMode) 51 Builder.defineMacro(MacroName); 52 53 // Define __unix. 54 Builder.defineMacro("__" + MacroName); 55 56 // Define __unix__. 57 Builder.defineMacro("__" + MacroName + "__"); 58 } 59 60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 61 bool Tuning = true) { 62 Builder.defineMacro("__" + CPUName); 63 Builder.defineMacro("__" + CPUName + "__"); 64 if (Tuning) 65 Builder.defineMacro("__tune_" + CPUName + "__"); 66 } 67 68 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 69 const TargetOptions &Opts); 70 71 //===----------------------------------------------------------------------===// 72 // Defines specific to certain operating systems. 73 //===----------------------------------------------------------------------===// 74 75 namespace { 76 template<typename TgtInfo> 77 class OSTargetInfo : public TgtInfo { 78 protected: 79 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 80 MacroBuilder &Builder) const=0; 81 public: 82 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 83 : TgtInfo(Triple, Opts) {} 84 void getTargetDefines(const LangOptions &Opts, 85 MacroBuilder &Builder) const override { 86 TgtInfo::getTargetDefines(Opts, Builder); 87 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 88 } 89 90 }; 91 92 // CloudABI Target 93 template <typename Target> 94 class CloudABITargetInfo : public OSTargetInfo<Target> { 95 protected: 96 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 97 MacroBuilder &Builder) const override { 98 Builder.defineMacro("__CloudABI__"); 99 Builder.defineMacro("__ELF__"); 100 101 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 102 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 103 Builder.defineMacro("__STDC_UTF_16__"); 104 Builder.defineMacro("__STDC_UTF_32__"); 105 } 106 107 public: 108 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 109 : OSTargetInfo<Target>(Triple, Opts) {} 110 }; 111 112 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 113 const llvm::Triple &Triple, 114 StringRef &PlatformName, 115 VersionTuple &PlatformMinVersion) { 116 Builder.defineMacro("__APPLE_CC__", "6000"); 117 Builder.defineMacro("__APPLE__"); 118 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 119 // AddressSanitizer doesn't play well with source fortification, which is on 120 // by default on Darwin. 121 if (Opts.Sanitize.has(SanitizerKind::Address)) 122 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 123 124 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 125 if (!Opts.ObjC1) { 126 // __weak is always defined, for use in blocks and with objc pointers. 127 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 128 Builder.defineMacro("__strong", ""); 129 Builder.defineMacro("__unsafe_unretained", ""); 130 } 131 132 if (Opts.Static) 133 Builder.defineMacro("__STATIC__"); 134 else 135 Builder.defineMacro("__DYNAMIC__"); 136 137 if (Opts.POSIXThreads) 138 Builder.defineMacro("_REENTRANT"); 139 140 // Get the platform type and version number from the triple. 141 unsigned Maj, Min, Rev; 142 if (Triple.isMacOSX()) { 143 Triple.getMacOSXVersion(Maj, Min, Rev); 144 PlatformName = "macosx"; 145 } else { 146 Triple.getOSVersion(Maj, Min, Rev); 147 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 148 } 149 150 // If -target arch-pc-win32-macho option specified, we're 151 // generating code for Win32 ABI. No need to emit 152 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 153 if (PlatformName == "win32") { 154 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 155 return; 156 } 157 158 // Set the appropriate OS version define. 159 if (Triple.isiOS()) { 160 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 161 char Str[6]; 162 Str[0] = '0' + Maj; 163 Str[1] = '0' + (Min / 10); 164 Str[2] = '0' + (Min % 10); 165 Str[3] = '0' + (Rev / 10); 166 Str[4] = '0' + (Rev % 10); 167 Str[5] = '\0'; 168 if (Triple.isTvOS()) 169 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 170 else 171 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 172 Str); 173 174 } else if (Triple.isWatchOS()) { 175 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 176 char Str[6]; 177 Str[0] = '0' + Maj; 178 Str[1] = '0' + (Min / 10); 179 Str[2] = '0' + (Min % 10); 180 Str[3] = '0' + (Rev / 10); 181 Str[4] = '0' + (Rev % 10); 182 Str[5] = '\0'; 183 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 184 } else if (Triple.isMacOSX()) { 185 // Note that the Driver allows versions which aren't representable in the 186 // define (because we only get a single digit for the minor and micro 187 // revision numbers). So, we limit them to the maximum representable 188 // version. 189 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 190 char Str[7]; 191 if (Maj < 10 || (Maj == 10 && Min < 10)) { 192 Str[0] = '0' + (Maj / 10); 193 Str[1] = '0' + (Maj % 10); 194 Str[2] = '0' + std::min(Min, 9U); 195 Str[3] = '0' + std::min(Rev, 9U); 196 Str[4] = '\0'; 197 } else { 198 // Handle versions > 10.9. 199 Str[0] = '0' + (Maj / 10); 200 Str[1] = '0' + (Maj % 10); 201 Str[2] = '0' + (Min / 10); 202 Str[3] = '0' + (Min % 10); 203 Str[4] = '0' + (Rev / 10); 204 Str[5] = '0' + (Rev % 10); 205 Str[6] = '\0'; 206 } 207 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 208 } 209 210 // Tell users about the kernel if there is one. 211 if (Triple.isOSDarwin()) 212 Builder.defineMacro("__MACH__"); 213 214 // The Watch ABI uses Dwarf EH. 215 if(Triple.isWatchABI()) 216 Builder.defineMacro("__ARM_DWARF_EH__"); 217 218 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 219 } 220 221 template<typename Target> 222 class DarwinTargetInfo : public OSTargetInfo<Target> { 223 protected: 224 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 225 MacroBuilder &Builder) const override { 226 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 227 this->PlatformMinVersion); 228 } 229 230 public: 231 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 232 : OSTargetInfo<Target>(Triple, Opts) { 233 // By default, no TLS, and we whitelist permitted architecture/OS 234 // combinations. 235 this->TLSSupported = false; 236 237 if (Triple.isMacOSX()) 238 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 239 else if (Triple.isiOS()) { 240 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 241 if (Triple.getArch() == llvm::Triple::x86_64 || 242 Triple.getArch() == llvm::Triple::aarch64) 243 this->TLSSupported = !Triple.isOSVersionLT(8); 244 else if (Triple.getArch() == llvm::Triple::x86 || 245 Triple.getArch() == llvm::Triple::arm || 246 Triple.getArch() == llvm::Triple::thumb) 247 this->TLSSupported = !Triple.isOSVersionLT(9); 248 } else if (Triple.isWatchOS()) 249 this->TLSSupported = !Triple.isOSVersionLT(2); 250 251 this->MCountName = "\01mcount"; 252 } 253 254 std::string isValidSectionSpecifier(StringRef SR) const override { 255 // Let MCSectionMachO validate this. 256 StringRef Segment, Section; 257 unsigned TAA, StubSize; 258 bool HasTAA; 259 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 260 TAA, HasTAA, StubSize); 261 } 262 263 const char *getStaticInitSectionSpecifier() const override { 264 // FIXME: We should return 0 when building kexts. 265 return "__TEXT,__StaticInit,regular,pure_instructions"; 266 } 267 268 /// Darwin does not support protected visibility. Darwin's "default" 269 /// is very similar to ELF's "protected"; Darwin requires a "weak" 270 /// attribute on declarations that can be dynamically replaced. 271 bool hasProtectedVisibility() const override { 272 return false; 273 } 274 275 unsigned getExnObjectAlignment() const override { 276 // The alignment of an exception object is 8-bytes for darwin since 277 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 278 // and therefore doesn't guarantee 16-byte alignment. 279 return 64; 280 } 281 }; 282 283 284 // DragonFlyBSD Target 285 template<typename Target> 286 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 287 protected: 288 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 289 MacroBuilder &Builder) const override { 290 // DragonFly defines; list based off of gcc output 291 Builder.defineMacro("__DragonFly__"); 292 Builder.defineMacro("__DragonFly_cc_version", "100001"); 293 Builder.defineMacro("__ELF__"); 294 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 295 Builder.defineMacro("__tune_i386__"); 296 DefineStd(Builder, "unix", Opts); 297 } 298 public: 299 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 300 : OSTargetInfo<Target>(Triple, Opts) { 301 switch (Triple.getArch()) { 302 default: 303 case llvm::Triple::x86: 304 case llvm::Triple::x86_64: 305 this->MCountName = ".mcount"; 306 break; 307 } 308 } 309 }; 310 311 // FreeBSD Target 312 template<typename Target> 313 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 314 protected: 315 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 316 MacroBuilder &Builder) const override { 317 // FreeBSD defines; list based off of gcc output 318 319 unsigned Release = Triple.getOSMajorVersion(); 320 if (Release == 0U) 321 Release = 8; 322 323 Builder.defineMacro("__FreeBSD__", Twine(Release)); 324 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 325 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 326 DefineStd(Builder, "unix", Opts); 327 Builder.defineMacro("__ELF__"); 328 329 // On FreeBSD, wchar_t contains the number of the code point as 330 // used by the character set of the locale. These character sets are 331 // not necessarily a superset of ASCII. 332 // 333 // FIXME: This is wrong; the macro refers to the numerical values 334 // of wchar_t *literals*, which are not locale-dependent. However, 335 // FreeBSD systems apparently depend on us getting this wrong, and 336 // setting this to 1 is conforming even if all the basic source 337 // character literals have the same encoding as char and wchar_t. 338 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 339 } 340 public: 341 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 342 : OSTargetInfo<Target>(Triple, Opts) { 343 switch (Triple.getArch()) { 344 default: 345 case llvm::Triple::x86: 346 case llvm::Triple::x86_64: 347 this->MCountName = ".mcount"; 348 break; 349 case llvm::Triple::mips: 350 case llvm::Triple::mipsel: 351 case llvm::Triple::ppc: 352 case llvm::Triple::ppc64: 353 case llvm::Triple::ppc64le: 354 this->MCountName = "_mcount"; 355 break; 356 case llvm::Triple::arm: 357 this->MCountName = "__mcount"; 358 break; 359 } 360 } 361 }; 362 363 // GNU/kFreeBSD Target 364 template<typename Target> 365 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 366 protected: 367 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 368 MacroBuilder &Builder) const override { 369 // GNU/kFreeBSD defines; list based off of gcc output 370 371 DefineStd(Builder, "unix", Opts); 372 Builder.defineMacro("__FreeBSD_kernel__"); 373 Builder.defineMacro("__GLIBC__"); 374 Builder.defineMacro("__ELF__"); 375 if (Opts.POSIXThreads) 376 Builder.defineMacro("_REENTRANT"); 377 if (Opts.CPlusPlus) 378 Builder.defineMacro("_GNU_SOURCE"); 379 } 380 public: 381 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 382 : OSTargetInfo<Target>(Triple, Opts) {} 383 }; 384 385 // Minix Target 386 template<typename Target> 387 class MinixTargetInfo : public OSTargetInfo<Target> { 388 protected: 389 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 390 MacroBuilder &Builder) const override { 391 // Minix defines 392 393 Builder.defineMacro("__minix", "3"); 394 Builder.defineMacro("_EM_WSIZE", "4"); 395 Builder.defineMacro("_EM_PSIZE", "4"); 396 Builder.defineMacro("_EM_SSIZE", "2"); 397 Builder.defineMacro("_EM_LSIZE", "4"); 398 Builder.defineMacro("_EM_FSIZE", "4"); 399 Builder.defineMacro("_EM_DSIZE", "8"); 400 Builder.defineMacro("__ELF__"); 401 DefineStd(Builder, "unix", Opts); 402 } 403 public: 404 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 405 : OSTargetInfo<Target>(Triple, Opts) {} 406 }; 407 408 // Linux target 409 template<typename Target> 410 class LinuxTargetInfo : public OSTargetInfo<Target> { 411 protected: 412 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 413 MacroBuilder &Builder) const override { 414 // Linux defines; list based off of gcc output 415 DefineStd(Builder, "unix", Opts); 416 DefineStd(Builder, "linux", Opts); 417 Builder.defineMacro("__gnu_linux__"); 418 Builder.defineMacro("__ELF__"); 419 if (Triple.isAndroid()) { 420 Builder.defineMacro("__ANDROID__", "1"); 421 unsigned Maj, Min, Rev; 422 Triple.getEnvironmentVersion(Maj, Min, Rev); 423 this->PlatformName = "android"; 424 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 425 } 426 if (Opts.POSIXThreads) 427 Builder.defineMacro("_REENTRANT"); 428 if (Opts.CPlusPlus) 429 Builder.defineMacro("_GNU_SOURCE"); 430 } 431 public: 432 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 433 : OSTargetInfo<Target>(Triple, Opts) { 434 this->WIntType = TargetInfo::UnsignedInt; 435 436 switch (Triple.getArch()) { 437 default: 438 break; 439 case llvm::Triple::ppc: 440 case llvm::Triple::ppc64: 441 case llvm::Triple::ppc64le: 442 this->MCountName = "_mcount"; 443 break; 444 } 445 } 446 447 const char *getStaticInitSectionSpecifier() const override { 448 return ".text.startup"; 449 } 450 }; 451 452 // NetBSD Target 453 template<typename Target> 454 class NetBSDTargetInfo : public OSTargetInfo<Target> { 455 protected: 456 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 457 MacroBuilder &Builder) const override { 458 // NetBSD defines; list based off of gcc output 459 Builder.defineMacro("__NetBSD__"); 460 Builder.defineMacro("__unix__"); 461 Builder.defineMacro("__ELF__"); 462 if (Opts.POSIXThreads) 463 Builder.defineMacro("_POSIX_THREADS"); 464 465 switch (Triple.getArch()) { 466 default: 467 break; 468 case llvm::Triple::arm: 469 case llvm::Triple::armeb: 470 case llvm::Triple::thumb: 471 case llvm::Triple::thumbeb: 472 Builder.defineMacro("__ARM_DWARF_EH__"); 473 break; 474 } 475 } 476 public: 477 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 478 : OSTargetInfo<Target>(Triple, Opts) { 479 this->MCountName = "_mcount"; 480 } 481 }; 482 483 // OpenBSD Target 484 template<typename Target> 485 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 486 protected: 487 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 488 MacroBuilder &Builder) const override { 489 // OpenBSD defines; list based off of gcc output 490 491 Builder.defineMacro("__OpenBSD__"); 492 DefineStd(Builder, "unix", Opts); 493 Builder.defineMacro("__ELF__"); 494 if (Opts.POSIXThreads) 495 Builder.defineMacro("_REENTRANT"); 496 } 497 public: 498 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 499 : OSTargetInfo<Target>(Triple, Opts) { 500 this->TLSSupported = false; 501 502 switch (Triple.getArch()) { 503 default: 504 case llvm::Triple::x86: 505 case llvm::Triple::x86_64: 506 case llvm::Triple::arm: 507 case llvm::Triple::sparc: 508 this->MCountName = "__mcount"; 509 break; 510 case llvm::Triple::mips64: 511 case llvm::Triple::mips64el: 512 case llvm::Triple::ppc: 513 case llvm::Triple::sparcv9: 514 this->MCountName = "_mcount"; 515 break; 516 } 517 } 518 }; 519 520 // Bitrig Target 521 template<typename Target> 522 class BitrigTargetInfo : public OSTargetInfo<Target> { 523 protected: 524 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 525 MacroBuilder &Builder) const override { 526 // Bitrig defines; list based off of gcc output 527 528 Builder.defineMacro("__Bitrig__"); 529 DefineStd(Builder, "unix", Opts); 530 Builder.defineMacro("__ELF__"); 531 if (Opts.POSIXThreads) 532 Builder.defineMacro("_REENTRANT"); 533 534 switch (Triple.getArch()) { 535 default: 536 break; 537 case llvm::Triple::arm: 538 case llvm::Triple::armeb: 539 case llvm::Triple::thumb: 540 case llvm::Triple::thumbeb: 541 Builder.defineMacro("__ARM_DWARF_EH__"); 542 break; 543 } 544 } 545 public: 546 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 547 : OSTargetInfo<Target>(Triple, Opts) { 548 this->MCountName = "__mcount"; 549 } 550 }; 551 552 // PSP Target 553 template<typename Target> 554 class PSPTargetInfo : public OSTargetInfo<Target> { 555 protected: 556 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 557 MacroBuilder &Builder) const override { 558 // PSP defines; list based on the output of the pspdev gcc toolchain. 559 Builder.defineMacro("PSP"); 560 Builder.defineMacro("_PSP"); 561 Builder.defineMacro("__psp__"); 562 Builder.defineMacro("__ELF__"); 563 } 564 public: 565 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 566 }; 567 568 // PS3 PPU Target 569 template<typename Target> 570 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 571 protected: 572 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 573 MacroBuilder &Builder) const override { 574 // PS3 PPU defines. 575 Builder.defineMacro("__PPC__"); 576 Builder.defineMacro("__PPU__"); 577 Builder.defineMacro("__CELLOS_LV2__"); 578 Builder.defineMacro("__ELF__"); 579 Builder.defineMacro("__LP32__"); 580 Builder.defineMacro("_ARCH_PPC64"); 581 Builder.defineMacro("__powerpc64__"); 582 } 583 public: 584 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 585 : OSTargetInfo<Target>(Triple, Opts) { 586 this->LongWidth = this->LongAlign = 32; 587 this->PointerWidth = this->PointerAlign = 32; 588 this->IntMaxType = TargetInfo::SignedLongLong; 589 this->Int64Type = TargetInfo::SignedLongLong; 590 this->SizeType = TargetInfo::UnsignedInt; 591 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 592 } 593 }; 594 595 template <typename Target> 596 class PS4OSTargetInfo : public OSTargetInfo<Target> { 597 protected: 598 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 599 MacroBuilder &Builder) const override { 600 Builder.defineMacro("__FreeBSD__", "9"); 601 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 602 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 603 DefineStd(Builder, "unix", Opts); 604 Builder.defineMacro("__ELF__"); 605 Builder.defineMacro("__PS4__"); 606 } 607 public: 608 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 609 : OSTargetInfo<Target>(Triple, Opts) { 610 this->WCharType = this->UnsignedShort; 611 612 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 613 this->MaxTLSAlign = 256; 614 615 // On PS4, do not honor explicit bit field alignment, 616 // as in "__attribute__((aligned(2))) int b : 1;". 617 this->UseExplicitBitFieldAlignment = false; 618 619 switch (Triple.getArch()) { 620 default: 621 case llvm::Triple::x86_64: 622 this->MCountName = ".mcount"; 623 break; 624 } 625 } 626 }; 627 628 // Solaris target 629 template<typename Target> 630 class SolarisTargetInfo : public OSTargetInfo<Target> { 631 protected: 632 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 633 MacroBuilder &Builder) const override { 634 DefineStd(Builder, "sun", Opts); 635 DefineStd(Builder, "unix", Opts); 636 Builder.defineMacro("__ELF__"); 637 Builder.defineMacro("__svr4__"); 638 Builder.defineMacro("__SVR4"); 639 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 640 // newer, but to 500 for everything else. feature_test.h has a check to 641 // ensure that you are not using C99 with an old version of X/Open or C89 642 // with a new version. 643 if (Opts.C99) 644 Builder.defineMacro("_XOPEN_SOURCE", "600"); 645 else 646 Builder.defineMacro("_XOPEN_SOURCE", "500"); 647 if (Opts.CPlusPlus) 648 Builder.defineMacro("__C99FEATURES__"); 649 Builder.defineMacro("_LARGEFILE_SOURCE"); 650 Builder.defineMacro("_LARGEFILE64_SOURCE"); 651 Builder.defineMacro("__EXTENSIONS__"); 652 Builder.defineMacro("_REENTRANT"); 653 } 654 public: 655 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 656 : OSTargetInfo<Target>(Triple, Opts) { 657 this->WCharType = this->SignedInt; 658 // FIXME: WIntType should be SignedLong 659 } 660 }; 661 662 // Windows target 663 template<typename Target> 664 class WindowsTargetInfo : public OSTargetInfo<Target> { 665 protected: 666 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 667 MacroBuilder &Builder) const override { 668 Builder.defineMacro("_WIN32"); 669 } 670 void getVisualStudioDefines(const LangOptions &Opts, 671 MacroBuilder &Builder) const { 672 if (Opts.CPlusPlus) { 673 if (Opts.RTTIData) 674 Builder.defineMacro("_CPPRTTI"); 675 676 if (Opts.CXXExceptions) 677 Builder.defineMacro("_CPPUNWIND"); 678 } 679 680 if (Opts.Bool) 681 Builder.defineMacro("__BOOL_DEFINED"); 682 683 if (!Opts.CharIsSigned) 684 Builder.defineMacro("_CHAR_UNSIGNED"); 685 686 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 687 // but it works for now. 688 if (Opts.POSIXThreads) 689 Builder.defineMacro("_MT"); 690 691 if (Opts.MSCompatibilityVersion) { 692 Builder.defineMacro("_MSC_VER", 693 Twine(Opts.MSCompatibilityVersion / 100000)); 694 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 695 // FIXME We cannot encode the revision information into 32-bits 696 Builder.defineMacro("_MSC_BUILD", Twine(1)); 697 698 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 699 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 700 } 701 702 if (Opts.MicrosoftExt) { 703 Builder.defineMacro("_MSC_EXTENSIONS"); 704 705 if (Opts.CPlusPlus11) { 706 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 707 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 708 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 709 } 710 } 711 712 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 713 } 714 715 public: 716 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 717 : OSTargetInfo<Target>(Triple, Opts) {} 718 }; 719 720 template <typename Target> 721 class NaClTargetInfo : public OSTargetInfo<Target> { 722 protected: 723 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 724 MacroBuilder &Builder) const override { 725 if (Opts.POSIXThreads) 726 Builder.defineMacro("_REENTRANT"); 727 if (Opts.CPlusPlus) 728 Builder.defineMacro("_GNU_SOURCE"); 729 730 DefineStd(Builder, "unix", Opts); 731 Builder.defineMacro("__ELF__"); 732 Builder.defineMacro("__native_client__"); 733 } 734 735 public: 736 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 737 : OSTargetInfo<Target>(Triple, Opts) { 738 this->LongAlign = 32; 739 this->LongWidth = 32; 740 this->PointerAlign = 32; 741 this->PointerWidth = 32; 742 this->IntMaxType = TargetInfo::SignedLongLong; 743 this->Int64Type = TargetInfo::SignedLongLong; 744 this->DoubleAlign = 64; 745 this->LongDoubleWidth = 64; 746 this->LongDoubleAlign = 64; 747 this->LongLongWidth = 64; 748 this->LongLongAlign = 64; 749 this->SizeType = TargetInfo::UnsignedInt; 750 this->PtrDiffType = TargetInfo::SignedInt; 751 this->IntPtrType = TargetInfo::SignedInt; 752 // RegParmMax is inherited from the underlying architecture 753 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 754 if (Triple.getArch() == llvm::Triple::arm) { 755 // Handled in ARM's setABI(). 756 } else if (Triple.getArch() == llvm::Triple::x86) { 757 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 758 } else if (Triple.getArch() == llvm::Triple::x86_64) { 759 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 760 } else if (Triple.getArch() == llvm::Triple::mipsel) { 761 // Handled on mips' setDataLayout. 762 } else { 763 assert(Triple.getArch() == llvm::Triple::le32); 764 this->resetDataLayout("e-p:32:32-i64:64"); 765 } 766 } 767 }; 768 769 // WebAssembly target 770 template <typename Target> 771 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 772 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 773 MacroBuilder &Builder) const final { 774 // A common platform macro. 775 if (Opts.POSIXThreads) 776 Builder.defineMacro("_REENTRANT"); 777 // Follow g++ convention and predefine _GNU_SOURCE for C++. 778 if (Opts.CPlusPlus) 779 Builder.defineMacro("_GNU_SOURCE"); 780 } 781 782 // As an optimization, group static init code together in a section. 783 const char *getStaticInitSectionSpecifier() const final { 784 return ".text.__startup"; 785 } 786 787 public: 788 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 789 const TargetOptions &Opts) 790 : OSTargetInfo<Target>(Triple, Opts) { 791 this->MCountName = "__mcount"; 792 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 793 } 794 }; 795 796 //===----------------------------------------------------------------------===// 797 // Specific target implementations. 798 //===----------------------------------------------------------------------===// 799 800 // PPC abstract base class 801 class PPCTargetInfo : public TargetInfo { 802 static const Builtin::Info BuiltinInfo[]; 803 static const char * const GCCRegNames[]; 804 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 805 std::string CPU; 806 807 // Target cpu features. 808 bool HasVSX; 809 bool HasP8Vector; 810 bool HasP8Crypto; 811 bool HasDirectMove; 812 bool HasQPX; 813 bool HasHTM; 814 bool HasBPERMD; 815 bool HasExtDiv; 816 817 protected: 818 std::string ABI; 819 820 public: 821 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 822 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 823 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 824 HasBPERMD(false), HasExtDiv(false) { 825 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 826 SimdDefaultAlign = 128; 827 LongDoubleWidth = LongDoubleAlign = 128; 828 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 829 } 830 831 /// \brief Flags for architecture specific defines. 832 typedef enum { 833 ArchDefineNone = 0, 834 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 835 ArchDefinePpcgr = 1 << 1, 836 ArchDefinePpcsq = 1 << 2, 837 ArchDefine440 = 1 << 3, 838 ArchDefine603 = 1 << 4, 839 ArchDefine604 = 1 << 5, 840 ArchDefinePwr4 = 1 << 6, 841 ArchDefinePwr5 = 1 << 7, 842 ArchDefinePwr5x = 1 << 8, 843 ArchDefinePwr6 = 1 << 9, 844 ArchDefinePwr6x = 1 << 10, 845 ArchDefinePwr7 = 1 << 11, 846 ArchDefinePwr8 = 1 << 12, 847 ArchDefineA2 = 1 << 13, 848 ArchDefineA2q = 1 << 14 849 } ArchDefineTypes; 850 851 // Note: GCC recognizes the following additional cpus: 852 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 853 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 854 // titan, rs64. 855 bool setCPU(const std::string &Name) override { 856 bool CPUKnown = llvm::StringSwitch<bool>(Name) 857 .Case("generic", true) 858 .Case("440", true) 859 .Case("450", true) 860 .Case("601", true) 861 .Case("602", true) 862 .Case("603", true) 863 .Case("603e", true) 864 .Case("603ev", true) 865 .Case("604", true) 866 .Case("604e", true) 867 .Case("620", true) 868 .Case("630", true) 869 .Case("g3", true) 870 .Case("7400", true) 871 .Case("g4", true) 872 .Case("7450", true) 873 .Case("g4+", true) 874 .Case("750", true) 875 .Case("970", true) 876 .Case("g5", true) 877 .Case("a2", true) 878 .Case("a2q", true) 879 .Case("e500mc", true) 880 .Case("e5500", true) 881 .Case("power3", true) 882 .Case("pwr3", true) 883 .Case("power4", true) 884 .Case("pwr4", true) 885 .Case("power5", true) 886 .Case("pwr5", true) 887 .Case("power5x", true) 888 .Case("pwr5x", true) 889 .Case("power6", true) 890 .Case("pwr6", true) 891 .Case("power6x", true) 892 .Case("pwr6x", true) 893 .Case("power7", true) 894 .Case("pwr7", true) 895 .Case("power8", true) 896 .Case("pwr8", true) 897 .Case("powerpc", true) 898 .Case("ppc", true) 899 .Case("powerpc64", true) 900 .Case("ppc64", true) 901 .Case("powerpc64le", true) 902 .Case("ppc64le", true) 903 .Default(false); 904 905 if (CPUKnown) 906 CPU = Name; 907 908 return CPUKnown; 909 } 910 911 912 StringRef getABI() const override { return ABI; } 913 914 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 915 return llvm::makeArrayRef(BuiltinInfo, 916 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 917 } 918 919 bool isCLZForZeroUndef() const override { return false; } 920 921 void getTargetDefines(const LangOptions &Opts, 922 MacroBuilder &Builder) const override; 923 924 bool 925 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 926 StringRef CPU, 927 const std::vector<std::string> &FeaturesVec) const override; 928 929 bool handleTargetFeatures(std::vector<std::string> &Features, 930 DiagnosticsEngine &Diags) override; 931 bool hasFeature(StringRef Feature) const override; 932 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 933 bool Enabled) const override; 934 935 ArrayRef<const char *> getGCCRegNames() const override; 936 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 937 bool validateAsmConstraint(const char *&Name, 938 TargetInfo::ConstraintInfo &Info) const override { 939 switch (*Name) { 940 default: return false; 941 case 'O': // Zero 942 break; 943 case 'b': // Base register 944 case 'f': // Floating point register 945 Info.setAllowsRegister(); 946 break; 947 // FIXME: The following are added to allow parsing. 948 // I just took a guess at what the actions should be. 949 // Also, is more specific checking needed? I.e. specific registers? 950 case 'd': // Floating point register (containing 64-bit value) 951 case 'v': // Altivec vector register 952 Info.setAllowsRegister(); 953 break; 954 case 'w': 955 switch (Name[1]) { 956 case 'd':// VSX vector register to hold vector double data 957 case 'f':// VSX vector register to hold vector float data 958 case 's':// VSX vector register to hold scalar float data 959 case 'a':// Any VSX register 960 case 'c':// An individual CR bit 961 break; 962 default: 963 return false; 964 } 965 Info.setAllowsRegister(); 966 Name++; // Skip over 'w'. 967 break; 968 case 'h': // `MQ', `CTR', or `LINK' register 969 case 'q': // `MQ' register 970 case 'c': // `CTR' register 971 case 'l': // `LINK' register 972 case 'x': // `CR' register (condition register) number 0 973 case 'y': // `CR' register (condition register) 974 case 'z': // `XER[CA]' carry bit (part of the XER register) 975 Info.setAllowsRegister(); 976 break; 977 case 'I': // Signed 16-bit constant 978 case 'J': // Unsigned 16-bit constant shifted left 16 bits 979 // (use `L' instead for SImode constants) 980 case 'K': // Unsigned 16-bit constant 981 case 'L': // Signed 16-bit constant shifted left 16 bits 982 case 'M': // Constant larger than 31 983 case 'N': // Exact power of 2 984 case 'P': // Constant whose negation is a signed 16-bit constant 985 case 'G': // Floating point constant that can be loaded into a 986 // register with one instruction per word 987 case 'H': // Integer/Floating point constant that can be loaded 988 // into a register using three instructions 989 break; 990 case 'm': // Memory operand. Note that on PowerPC targets, m can 991 // include addresses that update the base register. It 992 // is therefore only safe to use `m' in an asm statement 993 // if that asm statement accesses the operand exactly once. 994 // The asm statement must also use `%U<opno>' as a 995 // placeholder for the "update" flag in the corresponding 996 // load or store instruction. For example: 997 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 998 // is correct but: 999 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1000 // is not. Use es rather than m if you don't want the base 1001 // register to be updated. 1002 case 'e': 1003 if (Name[1] != 's') 1004 return false; 1005 // es: A "stable" memory operand; that is, one which does not 1006 // include any automodification of the base register. Unlike 1007 // `m', this constraint can be used in asm statements that 1008 // might access the operand several times, or that might not 1009 // access it at all. 1010 Info.setAllowsMemory(); 1011 Name++; // Skip over 'e'. 1012 break; 1013 case 'Q': // Memory operand that is an offset from a register (it is 1014 // usually better to use `m' or `es' in asm statements) 1015 case 'Z': // Memory operand that is an indexed or indirect from a 1016 // register (it is usually better to use `m' or `es' in 1017 // asm statements) 1018 Info.setAllowsMemory(); 1019 Info.setAllowsRegister(); 1020 break; 1021 case 'R': // AIX TOC entry 1022 case 'a': // Address operand that is an indexed or indirect from a 1023 // register (`p' is preferable for asm statements) 1024 case 'S': // Constant suitable as a 64-bit mask operand 1025 case 'T': // Constant suitable as a 32-bit mask operand 1026 case 'U': // System V Release 4 small data area reference 1027 case 't': // AND masks that can be performed by two rldic{l, r} 1028 // instructions 1029 case 'W': // Vector constant that does not require memory 1030 case 'j': // Vector constant that is all zeros. 1031 break; 1032 // End FIXME. 1033 } 1034 return true; 1035 } 1036 std::string convertConstraint(const char *&Constraint) const override { 1037 std::string R; 1038 switch (*Constraint) { 1039 case 'e': 1040 case 'w': 1041 // Two-character constraint; add "^" hint for later parsing. 1042 R = std::string("^") + std::string(Constraint, 2); 1043 Constraint++; 1044 break; 1045 default: 1046 return TargetInfo::convertConstraint(Constraint); 1047 } 1048 return R; 1049 } 1050 const char *getClobbers() const override { 1051 return ""; 1052 } 1053 int getEHDataRegisterNumber(unsigned RegNo) const override { 1054 if (RegNo == 0) return 3; 1055 if (RegNo == 1) return 4; 1056 return -1; 1057 } 1058 1059 bool hasSjLjLowering() const override { 1060 return true; 1061 } 1062 1063 bool useFloat128ManglingForLongDouble() const override { 1064 return LongDoubleWidth == 128 && 1065 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1066 getTriple().isOSBinFormatELF(); 1067 } 1068 }; 1069 1070 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1071 #define BUILTIN(ID, TYPE, ATTRS) \ 1072 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1073 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1074 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1075 #include "clang/Basic/BuiltinsPPC.def" 1076 }; 1077 1078 /// handleTargetFeatures - Perform initialization based on the user 1079 /// configured set of features. 1080 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1081 DiagnosticsEngine &Diags) { 1082 for (const auto &Feature : Features) { 1083 if (Feature == "+vsx") { 1084 HasVSX = true; 1085 } else if (Feature == "+bpermd") { 1086 HasBPERMD = true; 1087 } else if (Feature == "+extdiv") { 1088 HasExtDiv = true; 1089 } else if (Feature == "+power8-vector") { 1090 HasP8Vector = true; 1091 } else if (Feature == "+crypto") { 1092 HasP8Crypto = true; 1093 } else if (Feature == "+direct-move") { 1094 HasDirectMove = true; 1095 } else if (Feature == "+qpx") { 1096 HasQPX = true; 1097 } else if (Feature == "+htm") { 1098 HasHTM = true; 1099 } 1100 // TODO: Finish this list and add an assert that we've handled them 1101 // all. 1102 } 1103 1104 return true; 1105 } 1106 1107 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1108 /// #defines that are not tied to a specific subtarget. 1109 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1110 MacroBuilder &Builder) const { 1111 // Target identification. 1112 Builder.defineMacro("__ppc__"); 1113 Builder.defineMacro("__PPC__"); 1114 Builder.defineMacro("_ARCH_PPC"); 1115 Builder.defineMacro("__powerpc__"); 1116 Builder.defineMacro("__POWERPC__"); 1117 if (PointerWidth == 64) { 1118 Builder.defineMacro("_ARCH_PPC64"); 1119 Builder.defineMacro("__powerpc64__"); 1120 Builder.defineMacro("__ppc64__"); 1121 Builder.defineMacro("__PPC64__"); 1122 } 1123 1124 // Target properties. 1125 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1126 Builder.defineMacro("_LITTLE_ENDIAN"); 1127 } else { 1128 if (getTriple().getOS() != llvm::Triple::NetBSD && 1129 getTriple().getOS() != llvm::Triple::OpenBSD) 1130 Builder.defineMacro("_BIG_ENDIAN"); 1131 } 1132 1133 // ABI options. 1134 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1135 Builder.defineMacro("_CALL_ELF", "1"); 1136 if (ABI == "elfv2") 1137 Builder.defineMacro("_CALL_ELF", "2"); 1138 1139 // Subtarget options. 1140 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1141 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1142 1143 // FIXME: Should be controlled by command line option. 1144 if (LongDoubleWidth == 128) 1145 Builder.defineMacro("__LONG_DOUBLE_128__"); 1146 1147 if (Opts.AltiVec) { 1148 Builder.defineMacro("__VEC__", "10206"); 1149 Builder.defineMacro("__ALTIVEC__"); 1150 } 1151 1152 // CPU identification. 1153 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1154 .Case("440", ArchDefineName) 1155 .Case("450", ArchDefineName | ArchDefine440) 1156 .Case("601", ArchDefineName) 1157 .Case("602", ArchDefineName | ArchDefinePpcgr) 1158 .Case("603", ArchDefineName | ArchDefinePpcgr) 1159 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1160 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1161 .Case("604", ArchDefineName | ArchDefinePpcgr) 1162 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1163 .Case("620", ArchDefineName | ArchDefinePpcgr) 1164 .Case("630", ArchDefineName | ArchDefinePpcgr) 1165 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1166 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1167 .Case("750", ArchDefineName | ArchDefinePpcgr) 1168 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1169 | ArchDefinePpcsq) 1170 .Case("a2", ArchDefineA2) 1171 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1172 .Case("pwr3", ArchDefinePpcgr) 1173 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1174 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1175 | ArchDefinePpcsq) 1176 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1177 | ArchDefinePpcgr | ArchDefinePpcsq) 1178 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1179 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1180 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1181 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1182 | ArchDefinePpcsq) 1183 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1184 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1185 | ArchDefinePpcgr | ArchDefinePpcsq) 1186 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1187 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1188 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1189 .Case("power3", ArchDefinePpcgr) 1190 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1191 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1192 | ArchDefinePpcsq) 1193 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1194 | ArchDefinePpcgr | ArchDefinePpcsq) 1195 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1196 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1197 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1198 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1199 | ArchDefinePpcsq) 1200 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1201 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1202 | ArchDefinePpcgr | ArchDefinePpcsq) 1203 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1204 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1205 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1206 .Default(ArchDefineNone); 1207 1208 if (defs & ArchDefineName) 1209 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1210 if (defs & ArchDefinePpcgr) 1211 Builder.defineMacro("_ARCH_PPCGR"); 1212 if (defs & ArchDefinePpcsq) 1213 Builder.defineMacro("_ARCH_PPCSQ"); 1214 if (defs & ArchDefine440) 1215 Builder.defineMacro("_ARCH_440"); 1216 if (defs & ArchDefine603) 1217 Builder.defineMacro("_ARCH_603"); 1218 if (defs & ArchDefine604) 1219 Builder.defineMacro("_ARCH_604"); 1220 if (defs & ArchDefinePwr4) 1221 Builder.defineMacro("_ARCH_PWR4"); 1222 if (defs & ArchDefinePwr5) 1223 Builder.defineMacro("_ARCH_PWR5"); 1224 if (defs & ArchDefinePwr5x) 1225 Builder.defineMacro("_ARCH_PWR5X"); 1226 if (defs & ArchDefinePwr6) 1227 Builder.defineMacro("_ARCH_PWR6"); 1228 if (defs & ArchDefinePwr6x) 1229 Builder.defineMacro("_ARCH_PWR6X"); 1230 if (defs & ArchDefinePwr7) 1231 Builder.defineMacro("_ARCH_PWR7"); 1232 if (defs & ArchDefinePwr8) 1233 Builder.defineMacro("_ARCH_PWR8"); 1234 if (defs & ArchDefineA2) 1235 Builder.defineMacro("_ARCH_A2"); 1236 if (defs & ArchDefineA2q) { 1237 Builder.defineMacro("_ARCH_A2Q"); 1238 Builder.defineMacro("_ARCH_QP"); 1239 } 1240 1241 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1242 Builder.defineMacro("__bg__"); 1243 Builder.defineMacro("__THW_BLUEGENE__"); 1244 Builder.defineMacro("__bgq__"); 1245 Builder.defineMacro("__TOS_BGQ__"); 1246 } 1247 1248 if (HasVSX) 1249 Builder.defineMacro("__VSX__"); 1250 if (HasP8Vector) 1251 Builder.defineMacro("__POWER8_VECTOR__"); 1252 if (HasP8Crypto) 1253 Builder.defineMacro("__CRYPTO__"); 1254 if (HasHTM) 1255 Builder.defineMacro("__HTM__"); 1256 1257 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1258 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1259 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1260 if (PointerWidth == 64) 1261 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1262 1263 // FIXME: The following are not yet generated here by Clang, but are 1264 // generated by GCC: 1265 // 1266 // _SOFT_FLOAT_ 1267 // __RECIP_PRECISION__ 1268 // __APPLE_ALTIVEC__ 1269 // __RECIP__ 1270 // __RECIPF__ 1271 // __RSQRTE__ 1272 // __RSQRTEF__ 1273 // _SOFT_DOUBLE_ 1274 // __NO_LWSYNC__ 1275 // __HAVE_BSWAP__ 1276 // __LONGDOUBLE128 1277 // __CMODEL_MEDIUM__ 1278 // __CMODEL_LARGE__ 1279 // _CALL_SYSV 1280 // _CALL_DARWIN 1281 // __NO_FPRS__ 1282 } 1283 1284 // Handle explicit options being passed to the compiler here: if we've 1285 // explicitly turned off vsx and turned on power8-vector or direct-move then 1286 // go ahead and error since the customer has expressed a somewhat incompatible 1287 // set of options. 1288 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1289 const std::vector<std::string> &FeaturesVec) { 1290 1291 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1292 FeaturesVec.end()) { 1293 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1294 FeaturesVec.end()) { 1295 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1296 << "-mno-vsx"; 1297 return false; 1298 } 1299 1300 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1301 FeaturesVec.end()) { 1302 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1303 << "-mno-vsx"; 1304 return false; 1305 } 1306 } 1307 1308 return true; 1309 } 1310 1311 bool PPCTargetInfo::initFeatureMap( 1312 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1313 const std::vector<std::string> &FeaturesVec) const { 1314 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1315 .Case("7400", true) 1316 .Case("g4", true) 1317 .Case("7450", true) 1318 .Case("g4+", true) 1319 .Case("970", true) 1320 .Case("g5", true) 1321 .Case("pwr6", true) 1322 .Case("pwr7", true) 1323 .Case("pwr8", true) 1324 .Case("ppc64", true) 1325 .Case("ppc64le", true) 1326 .Default(false); 1327 1328 Features["qpx"] = (CPU == "a2q"); 1329 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1330 .Case("ppc64le", true) 1331 .Case("pwr8", true) 1332 .Default(false); 1333 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1334 .Case("ppc64le", true) 1335 .Case("pwr8", true) 1336 .Default(false); 1337 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1338 .Case("ppc64le", true) 1339 .Case("pwr8", true) 1340 .Case("pwr7", true) 1341 .Default(false); 1342 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1343 .Case("ppc64le", true) 1344 .Case("pwr8", true) 1345 .Case("pwr7", true) 1346 .Default(false); 1347 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1348 .Case("ppc64le", true) 1349 .Case("pwr8", true) 1350 .Default(false); 1351 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1352 .Case("ppc64le", true) 1353 .Case("pwr8", true) 1354 .Case("pwr7", true) 1355 .Default(false); 1356 1357 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1358 return false; 1359 1360 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1361 } 1362 1363 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1364 return llvm::StringSwitch<bool>(Feature) 1365 .Case("powerpc", true) 1366 .Case("vsx", HasVSX) 1367 .Case("power8-vector", HasP8Vector) 1368 .Case("crypto", HasP8Crypto) 1369 .Case("direct-move", HasDirectMove) 1370 .Case("qpx", HasQPX) 1371 .Case("htm", HasHTM) 1372 .Case("bpermd", HasBPERMD) 1373 .Case("extdiv", HasExtDiv) 1374 .Default(false); 1375 } 1376 1377 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1378 StringRef Name, bool Enabled) const { 1379 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1380 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1381 // incompatible options. 1382 if (Enabled) { 1383 if (Name == "vsx") { 1384 Features[Name] = true; 1385 } else if (Name == "direct-move") { 1386 Features[Name] = Features["vsx"] = true; 1387 } else if (Name == "power8-vector") { 1388 Features[Name] = Features["vsx"] = true; 1389 } else { 1390 Features[Name] = true; 1391 } 1392 } else { 1393 if (Name == "vsx") { 1394 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1395 false; 1396 } else { 1397 Features[Name] = false; 1398 } 1399 } 1400 } 1401 1402 const char * const PPCTargetInfo::GCCRegNames[] = { 1403 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1404 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1405 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1406 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1407 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1408 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1409 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1410 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1411 "mq", "lr", "ctr", "ap", 1412 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1413 "xer", 1414 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1415 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1416 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1417 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1418 "vrsave", "vscr", 1419 "spe_acc", "spefscr", 1420 "sfp" 1421 }; 1422 1423 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1424 return llvm::makeArrayRef(GCCRegNames); 1425 } 1426 1427 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1428 // While some of these aliases do map to different registers 1429 // they still share the same register name. 1430 { { "0" }, "r0" }, 1431 { { "1"}, "r1" }, 1432 { { "2" }, "r2" }, 1433 { { "3" }, "r3" }, 1434 { { "4" }, "r4" }, 1435 { { "5" }, "r5" }, 1436 { { "6" }, "r6" }, 1437 { { "7" }, "r7" }, 1438 { { "8" }, "r8" }, 1439 { { "9" }, "r9" }, 1440 { { "10" }, "r10" }, 1441 { { "11" }, "r11" }, 1442 { { "12" }, "r12" }, 1443 { { "13" }, "r13" }, 1444 { { "14" }, "r14" }, 1445 { { "15" }, "r15" }, 1446 { { "16" }, "r16" }, 1447 { { "17" }, "r17" }, 1448 { { "18" }, "r18" }, 1449 { { "19" }, "r19" }, 1450 { { "20" }, "r20" }, 1451 { { "21" }, "r21" }, 1452 { { "22" }, "r22" }, 1453 { { "23" }, "r23" }, 1454 { { "24" }, "r24" }, 1455 { { "25" }, "r25" }, 1456 { { "26" }, "r26" }, 1457 { { "27" }, "r27" }, 1458 { { "28" }, "r28" }, 1459 { { "29" }, "r29" }, 1460 { { "30" }, "r30" }, 1461 { { "31" }, "r31" }, 1462 { { "fr0" }, "f0" }, 1463 { { "fr1" }, "f1" }, 1464 { { "fr2" }, "f2" }, 1465 { { "fr3" }, "f3" }, 1466 { { "fr4" }, "f4" }, 1467 { { "fr5" }, "f5" }, 1468 { { "fr6" }, "f6" }, 1469 { { "fr7" }, "f7" }, 1470 { { "fr8" }, "f8" }, 1471 { { "fr9" }, "f9" }, 1472 { { "fr10" }, "f10" }, 1473 { { "fr11" }, "f11" }, 1474 { { "fr12" }, "f12" }, 1475 { { "fr13" }, "f13" }, 1476 { { "fr14" }, "f14" }, 1477 { { "fr15" }, "f15" }, 1478 { { "fr16" }, "f16" }, 1479 { { "fr17" }, "f17" }, 1480 { { "fr18" }, "f18" }, 1481 { { "fr19" }, "f19" }, 1482 { { "fr20" }, "f20" }, 1483 { { "fr21" }, "f21" }, 1484 { { "fr22" }, "f22" }, 1485 { { "fr23" }, "f23" }, 1486 { { "fr24" }, "f24" }, 1487 { { "fr25" }, "f25" }, 1488 { { "fr26" }, "f26" }, 1489 { { "fr27" }, "f27" }, 1490 { { "fr28" }, "f28" }, 1491 { { "fr29" }, "f29" }, 1492 { { "fr30" }, "f30" }, 1493 { { "fr31" }, "f31" }, 1494 { { "cc" }, "cr0" }, 1495 }; 1496 1497 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1498 return llvm::makeArrayRef(GCCRegAliases); 1499 } 1500 1501 class PPC32TargetInfo : public PPCTargetInfo { 1502 public: 1503 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1504 : PPCTargetInfo(Triple, Opts) { 1505 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1506 1507 switch (getTriple().getOS()) { 1508 case llvm::Triple::Linux: 1509 case llvm::Triple::FreeBSD: 1510 case llvm::Triple::NetBSD: 1511 SizeType = UnsignedInt; 1512 PtrDiffType = SignedInt; 1513 IntPtrType = SignedInt; 1514 break; 1515 default: 1516 break; 1517 } 1518 1519 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1520 LongDoubleWidth = LongDoubleAlign = 64; 1521 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1522 } 1523 1524 // PPC32 supports atomics up to 4 bytes. 1525 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1526 } 1527 1528 BuiltinVaListKind getBuiltinVaListKind() const override { 1529 // This is the ELF definition, and is overridden by the Darwin sub-target 1530 return TargetInfo::PowerABIBuiltinVaList; 1531 } 1532 }; 1533 1534 // Note: ABI differences may eventually require us to have a separate 1535 // TargetInfo for little endian. 1536 class PPC64TargetInfo : public PPCTargetInfo { 1537 public: 1538 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1539 : PPCTargetInfo(Triple, Opts) { 1540 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1541 IntMaxType = SignedLong; 1542 Int64Type = SignedLong; 1543 1544 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1545 resetDataLayout("e-m:e-i64:64-n32:64"); 1546 ABI = "elfv2"; 1547 } else { 1548 resetDataLayout("E-m:e-i64:64-n32:64"); 1549 ABI = "elfv1"; 1550 } 1551 1552 switch (getTriple().getOS()) { 1553 case llvm::Triple::FreeBSD: 1554 LongDoubleWidth = LongDoubleAlign = 64; 1555 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1556 break; 1557 case llvm::Triple::NetBSD: 1558 IntMaxType = SignedLongLong; 1559 Int64Type = SignedLongLong; 1560 break; 1561 default: 1562 break; 1563 } 1564 1565 // PPC64 supports atomics up to 8 bytes. 1566 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1567 } 1568 BuiltinVaListKind getBuiltinVaListKind() const override { 1569 return TargetInfo::CharPtrBuiltinVaList; 1570 } 1571 // PPC64 Linux-specific ABI options. 1572 bool setABI(const std::string &Name) override { 1573 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1574 ABI = Name; 1575 return true; 1576 } 1577 return false; 1578 } 1579 }; 1580 1581 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1582 public: 1583 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1584 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1585 HasAlignMac68kSupport = true; 1586 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1587 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1588 LongLongAlign = 32; 1589 SuitableAlign = 128; 1590 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1591 } 1592 BuiltinVaListKind getBuiltinVaListKind() const override { 1593 return TargetInfo::CharPtrBuiltinVaList; 1594 } 1595 }; 1596 1597 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1598 public: 1599 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1600 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1601 HasAlignMac68kSupport = true; 1602 SuitableAlign = 128; 1603 resetDataLayout("E-m:o-i64:64-n32:64"); 1604 } 1605 }; 1606 1607 static const unsigned NVPTXAddrSpaceMap[] = { 1608 1, // opencl_global 1609 3, // opencl_local 1610 4, // opencl_constant 1611 // FIXME: generic has to be added to the target 1612 0, // opencl_generic 1613 1, // cuda_device 1614 4, // cuda_constant 1615 3, // cuda_shared 1616 }; 1617 1618 class NVPTXTargetInfo : public TargetInfo { 1619 static const char *const GCCRegNames[]; 1620 static const Builtin::Info BuiltinInfo[]; 1621 1622 // The GPU profiles supported by the NVPTX backend 1623 enum GPUKind { 1624 GK_NONE, 1625 GK_SM20, 1626 GK_SM21, 1627 GK_SM30, 1628 GK_SM35, 1629 GK_SM37, 1630 } GPU; 1631 1632 public: 1633 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1634 : TargetInfo(Triple) { 1635 BigEndian = false; 1636 TLSSupported = false; 1637 LongWidth = LongAlign = 64; 1638 AddrSpaceMap = &NVPTXAddrSpaceMap; 1639 UseAddrSpaceMapMangling = true; 1640 // Define available target features 1641 // These must be defined in sorted order! 1642 NoAsmVariants = true; 1643 // Set the default GPU to sm20 1644 GPU = GK_SM20; 1645 1646 // If possible, get a TargetInfo for our host triple, so we can match its 1647 // types. 1648 llvm::Triple HostTriple(Opts.HostTriple); 1649 if (HostTriple.isNVPTX()) 1650 return; 1651 std::unique_ptr<TargetInfo> HostTarget( 1652 AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1653 if (!HostTarget) { 1654 return; 1655 } 1656 1657 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1658 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1659 BoolWidth = HostTarget->getBoolWidth(); 1660 BoolAlign = HostTarget->getBoolAlign(); 1661 IntWidth = HostTarget->getIntWidth(); 1662 IntAlign = HostTarget->getIntAlign(); 1663 HalfWidth = HostTarget->getHalfWidth(); 1664 HalfAlign = HostTarget->getHalfAlign(); 1665 FloatWidth = HostTarget->getFloatWidth(); 1666 FloatAlign = HostTarget->getFloatAlign(); 1667 DoubleWidth = HostTarget->getDoubleWidth(); 1668 DoubleAlign = HostTarget->getDoubleAlign(); 1669 LongWidth = HostTarget->getLongWidth(); 1670 LongAlign = HostTarget->getLongAlign(); 1671 LongLongWidth = HostTarget->getLongLongWidth(); 1672 LongLongAlign = HostTarget->getLongLongAlign(); 1673 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1674 DefaultAlignForAttributeAligned = 1675 HostTarget->getDefaultAlignForAttributeAligned(); 1676 SizeType = HostTarget->getSizeType(); 1677 IntMaxType = HostTarget->getIntMaxType(); 1678 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1679 IntPtrType = HostTarget->getIntPtrType(); 1680 WCharType = HostTarget->getWCharType(); 1681 WIntType = HostTarget->getWIntType(); 1682 Char16Type = HostTarget->getChar16Type(); 1683 Char32Type = HostTarget->getChar32Type(); 1684 Int64Type = HostTarget->getInt64Type(); 1685 SigAtomicType = HostTarget->getSigAtomicType(); 1686 ProcessIDType = HostTarget->getProcessIDType(); 1687 1688 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1689 UseZeroLengthBitfieldAlignment = 1690 HostTarget->useZeroLengthBitfieldAlignment(); 1691 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1692 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1693 1694 // Properties intentionally not copied from host: 1695 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1696 // host/device boundary. 1697 // - SuitableAlign: Not visible across the host/device boundary, and may 1698 // correctly be different on host/device, e.g. if host has wider vector 1699 // types than device. 1700 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1701 // as its double type, but that's not necessarily true on the host. 1702 // TODO: nvcc emits a warning when using long double on device; we should 1703 // do the same. 1704 } 1705 void getTargetDefines(const LangOptions &Opts, 1706 MacroBuilder &Builder) const override { 1707 Builder.defineMacro("__PTX__"); 1708 Builder.defineMacro("__NVPTX__"); 1709 if (Opts.CUDAIsDevice) { 1710 // Set __CUDA_ARCH__ for the GPU specified. 1711 std::string CUDAArchCode; 1712 switch (GPU) { 1713 case GK_SM20: 1714 CUDAArchCode = "200"; 1715 break; 1716 case GK_SM21: 1717 CUDAArchCode = "210"; 1718 break; 1719 case GK_SM30: 1720 CUDAArchCode = "300"; 1721 break; 1722 case GK_SM35: 1723 CUDAArchCode = "350"; 1724 break; 1725 case GK_SM37: 1726 CUDAArchCode = "370"; 1727 break; 1728 default: 1729 llvm_unreachable("Unhandled target CPU"); 1730 } 1731 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1732 } 1733 } 1734 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1735 return llvm::makeArrayRef(BuiltinInfo, 1736 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1737 } 1738 bool hasFeature(StringRef Feature) const override { 1739 return Feature == "ptx" || Feature == "nvptx"; 1740 } 1741 1742 ArrayRef<const char *> getGCCRegNames() const override; 1743 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1744 // No aliases. 1745 return None; 1746 } 1747 bool validateAsmConstraint(const char *&Name, 1748 TargetInfo::ConstraintInfo &Info) const override { 1749 switch (*Name) { 1750 default: 1751 return false; 1752 case 'c': 1753 case 'h': 1754 case 'r': 1755 case 'l': 1756 case 'f': 1757 case 'd': 1758 Info.setAllowsRegister(); 1759 return true; 1760 } 1761 } 1762 const char *getClobbers() const override { 1763 // FIXME: Is this really right? 1764 return ""; 1765 } 1766 BuiltinVaListKind getBuiltinVaListKind() const override { 1767 // FIXME: implement 1768 return TargetInfo::CharPtrBuiltinVaList; 1769 } 1770 bool setCPU(const std::string &Name) override { 1771 GPU = llvm::StringSwitch<GPUKind>(Name) 1772 .Case("sm_20", GK_SM20) 1773 .Case("sm_21", GK_SM21) 1774 .Case("sm_30", GK_SM30) 1775 .Case("sm_35", GK_SM35) 1776 .Case("sm_37", GK_SM37) 1777 .Default(GK_NONE); 1778 1779 return GPU != GK_NONE; 1780 } 1781 }; 1782 1783 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1784 #define BUILTIN(ID, TYPE, ATTRS) \ 1785 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1786 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1787 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1788 #include "clang/Basic/BuiltinsNVPTX.def" 1789 }; 1790 1791 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1792 1793 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1794 return llvm::makeArrayRef(GCCRegNames); 1795 } 1796 1797 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1798 public: 1799 NVPTX32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1800 : NVPTXTargetInfo(Triple, Opts) { 1801 LongWidth = LongAlign = 32; 1802 PointerWidth = PointerAlign = 32; 1803 SizeType = TargetInfo::UnsignedInt; 1804 PtrDiffType = TargetInfo::SignedInt; 1805 IntPtrType = TargetInfo::SignedInt; 1806 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1807 } 1808 }; 1809 1810 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1811 public: 1812 NVPTX64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1813 : NVPTXTargetInfo(Triple, Opts) { 1814 PointerWidth = PointerAlign = 64; 1815 SizeType = TargetInfo::UnsignedLong; 1816 PtrDiffType = TargetInfo::SignedLong; 1817 IntPtrType = TargetInfo::SignedLong; 1818 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1819 } 1820 }; 1821 1822 static const unsigned AMDGPUAddrSpaceMap[] = { 1823 1, // opencl_global 1824 3, // opencl_local 1825 2, // opencl_constant 1826 4, // opencl_generic 1827 1, // cuda_device 1828 2, // cuda_constant 1829 3 // cuda_shared 1830 }; 1831 1832 // If you edit the description strings, make sure you update 1833 // getPointerWidthV(). 1834 1835 static const char *const DataLayoutStringR600 = 1836 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1837 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1838 1839 static const char *const DataLayoutStringSI = 1840 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1841 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1842 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1843 1844 class AMDGPUTargetInfo : public TargetInfo { 1845 static const Builtin::Info BuiltinInfo[]; 1846 static const char * const GCCRegNames[]; 1847 1848 /// \brief The GPU profiles supported by the AMDGPU target. 1849 enum GPUKind { 1850 GK_NONE, 1851 GK_R600, 1852 GK_R600_DOUBLE_OPS, 1853 GK_R700, 1854 GK_R700_DOUBLE_OPS, 1855 GK_EVERGREEN, 1856 GK_EVERGREEN_DOUBLE_OPS, 1857 GK_NORTHERN_ISLANDS, 1858 GK_CAYMAN, 1859 GK_SOUTHERN_ISLANDS, 1860 GK_SEA_ISLANDS, 1861 GK_VOLCANIC_ISLANDS 1862 } GPU; 1863 1864 bool hasFP64:1; 1865 bool hasFMAF:1; 1866 bool hasLDEXPF:1; 1867 1868 public: 1869 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 1870 : TargetInfo(Triple) { 1871 if (Triple.getArch() == llvm::Triple::amdgcn) { 1872 resetDataLayout(DataLayoutStringSI); 1873 GPU = GK_SOUTHERN_ISLANDS; 1874 hasFP64 = true; 1875 hasFMAF = true; 1876 hasLDEXPF = true; 1877 } else { 1878 resetDataLayout(DataLayoutStringR600); 1879 GPU = GK_R600; 1880 hasFP64 = false; 1881 hasFMAF = false; 1882 hasLDEXPF = false; 1883 } 1884 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1885 UseAddrSpaceMapMangling = true; 1886 } 1887 1888 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1889 if (GPU <= GK_CAYMAN) 1890 return 32; 1891 1892 switch(AddrSpace) { 1893 default: 1894 return 64; 1895 case 0: 1896 case 3: 1897 case 5: 1898 return 32; 1899 } 1900 } 1901 1902 const char * getClobbers() const override { 1903 return ""; 1904 } 1905 1906 ArrayRef<const char *> getGCCRegNames() const override; 1907 1908 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1909 return None; 1910 } 1911 1912 bool validateAsmConstraint(const char *&Name, 1913 TargetInfo::ConstraintInfo &Info) const override { 1914 switch (*Name) { 1915 default: break; 1916 case 'v': // vgpr 1917 case 's': // sgpr 1918 Info.setAllowsRegister(); 1919 return true; 1920 } 1921 return false; 1922 } 1923 1924 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1925 return llvm::makeArrayRef(BuiltinInfo, 1926 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 1927 } 1928 1929 void getTargetDefines(const LangOptions &Opts, 1930 MacroBuilder &Builder) const override { 1931 if (getTriple().getArch() == llvm::Triple::amdgcn) 1932 Builder.defineMacro("__AMDGCN__"); 1933 else 1934 Builder.defineMacro("__R600__"); 1935 1936 if (hasFMAF) 1937 Builder.defineMacro("__HAS_FMAF__"); 1938 if (hasLDEXPF) 1939 Builder.defineMacro("__HAS_LDEXPF__"); 1940 if (hasFP64 && Opts.OpenCL) 1941 Builder.defineMacro("cl_khr_fp64"); 1942 if (Opts.OpenCL) { 1943 if (GPU >= GK_NORTHERN_ISLANDS) { 1944 Builder.defineMacro("cl_khr_byte_addressable_store"); 1945 Builder.defineMacro("cl_khr_global_int32_base_atomics"); 1946 Builder.defineMacro("cl_khr_global_int32_extended_atomics"); 1947 Builder.defineMacro("cl_khr_local_int32_base_atomics"); 1948 Builder.defineMacro("cl_khr_local_int32_extended_atomics"); 1949 } 1950 } 1951 } 1952 1953 BuiltinVaListKind getBuiltinVaListKind() const override { 1954 return TargetInfo::CharPtrBuiltinVaList; 1955 } 1956 1957 bool setCPU(const std::string &Name) override { 1958 GPU = llvm::StringSwitch<GPUKind>(Name) 1959 .Case("r600" , GK_R600) 1960 .Case("rv610", GK_R600) 1961 .Case("rv620", GK_R600) 1962 .Case("rv630", GK_R600) 1963 .Case("rv635", GK_R600) 1964 .Case("rs780", GK_R600) 1965 .Case("rs880", GK_R600) 1966 .Case("rv670", GK_R600_DOUBLE_OPS) 1967 .Case("rv710", GK_R700) 1968 .Case("rv730", GK_R700) 1969 .Case("rv740", GK_R700_DOUBLE_OPS) 1970 .Case("rv770", GK_R700_DOUBLE_OPS) 1971 .Case("palm", GK_EVERGREEN) 1972 .Case("cedar", GK_EVERGREEN) 1973 .Case("sumo", GK_EVERGREEN) 1974 .Case("sumo2", GK_EVERGREEN) 1975 .Case("redwood", GK_EVERGREEN) 1976 .Case("juniper", GK_EVERGREEN) 1977 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1978 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1979 .Case("barts", GK_NORTHERN_ISLANDS) 1980 .Case("turks", GK_NORTHERN_ISLANDS) 1981 .Case("caicos", GK_NORTHERN_ISLANDS) 1982 .Case("cayman", GK_CAYMAN) 1983 .Case("aruba", GK_CAYMAN) 1984 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1985 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1986 .Case("verde", GK_SOUTHERN_ISLANDS) 1987 .Case("oland", GK_SOUTHERN_ISLANDS) 1988 .Case("hainan", GK_SOUTHERN_ISLANDS) 1989 .Case("bonaire", GK_SEA_ISLANDS) 1990 .Case("kabini", GK_SEA_ISLANDS) 1991 .Case("kaveri", GK_SEA_ISLANDS) 1992 .Case("hawaii", GK_SEA_ISLANDS) 1993 .Case("mullins", GK_SEA_ISLANDS) 1994 .Case("tonga", GK_VOLCANIC_ISLANDS) 1995 .Case("iceland", GK_VOLCANIC_ISLANDS) 1996 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1997 .Case("fiji", GK_VOLCANIC_ISLANDS) 1998 .Case("stoney", GK_VOLCANIC_ISLANDS) 1999 .Default(GK_NONE); 2000 2001 if (GPU == GK_NONE) { 2002 return false; 2003 } 2004 2005 // Set the correct data layout 2006 switch (GPU) { 2007 case GK_NONE: 2008 case GK_R600: 2009 case GK_R700: 2010 case GK_EVERGREEN: 2011 case GK_NORTHERN_ISLANDS: 2012 resetDataLayout(DataLayoutStringR600); 2013 hasFP64 = false; 2014 hasFMAF = false; 2015 hasLDEXPF = false; 2016 break; 2017 case GK_R600_DOUBLE_OPS: 2018 case GK_R700_DOUBLE_OPS: 2019 case GK_EVERGREEN_DOUBLE_OPS: 2020 case GK_CAYMAN: 2021 resetDataLayout(DataLayoutStringR600); 2022 hasFP64 = true; 2023 hasFMAF = true; 2024 hasLDEXPF = false; 2025 break; 2026 case GK_SOUTHERN_ISLANDS: 2027 case GK_SEA_ISLANDS: 2028 case GK_VOLCANIC_ISLANDS: 2029 resetDataLayout(DataLayoutStringSI); 2030 hasFP64 = true; 2031 hasFMAF = true; 2032 hasLDEXPF = true; 2033 break; 2034 } 2035 2036 return true; 2037 } 2038 }; 2039 2040 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2041 #define BUILTIN(ID, TYPE, ATTRS) \ 2042 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2043 #include "clang/Basic/BuiltinsAMDGPU.def" 2044 }; 2045 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2046 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2047 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2048 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2049 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2050 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2051 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2052 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2053 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2054 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2055 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2056 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2057 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2058 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2059 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2060 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2061 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2062 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2063 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2064 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2065 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2066 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2067 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2068 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2069 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2070 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2071 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2072 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2073 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2074 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2075 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2076 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2077 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2078 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2079 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2080 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2081 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2082 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2083 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2084 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2085 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2086 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2087 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2088 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2089 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2090 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2091 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2092 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2093 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2094 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2095 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2096 }; 2097 2098 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2099 return llvm::makeArrayRef(GCCRegNames); 2100 } 2101 2102 // Namespace for x86 abstract base class 2103 const Builtin::Info BuiltinInfo[] = { 2104 #define BUILTIN(ID, TYPE, ATTRS) \ 2105 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2106 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2107 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2108 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2109 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2110 #include "clang/Basic/BuiltinsX86.def" 2111 }; 2112 2113 static const char* const GCCRegNames[] = { 2114 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2115 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2116 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2117 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2118 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2119 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2120 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2121 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2122 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2123 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2124 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2125 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2126 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2127 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2128 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2129 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2130 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2131 }; 2132 2133 const TargetInfo::AddlRegName AddlRegNames[] = { 2134 { { "al", "ah", "eax", "rax" }, 0 }, 2135 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2136 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2137 { { "dl", "dh", "edx", "rdx" }, 1 }, 2138 { { "esi", "rsi" }, 4 }, 2139 { { "edi", "rdi" }, 5 }, 2140 { { "esp", "rsp" }, 7 }, 2141 { { "ebp", "rbp" }, 6 }, 2142 { { "r8d", "r8w", "r8b" }, 38 }, 2143 { { "r9d", "r9w", "r9b" }, 39 }, 2144 { { "r10d", "r10w", "r10b" }, 40 }, 2145 { { "r11d", "r11w", "r11b" }, 41 }, 2146 { { "r12d", "r12w", "r12b" }, 42 }, 2147 { { "r13d", "r13w", "r13b" }, 43 }, 2148 { { "r14d", "r14w", "r14b" }, 44 }, 2149 { { "r15d", "r15w", "r15b" }, 45 }, 2150 }; 2151 2152 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2153 // most of the implementation can be shared. 2154 class X86TargetInfo : public TargetInfo { 2155 enum X86SSEEnum { 2156 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2157 } SSELevel = NoSSE; 2158 enum MMX3DNowEnum { 2159 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2160 } MMX3DNowLevel = NoMMX3DNow; 2161 enum XOPEnum { 2162 NoXOP, 2163 SSE4A, 2164 FMA4, 2165 XOP 2166 } XOPLevel = NoXOP; 2167 2168 bool HasAES = false; 2169 bool HasPCLMUL = false; 2170 bool HasLZCNT = false; 2171 bool HasRDRND = false; 2172 bool HasFSGSBASE = false; 2173 bool HasBMI = false; 2174 bool HasBMI2 = false; 2175 bool HasPOPCNT = false; 2176 bool HasRTM = false; 2177 bool HasPRFCHW = false; 2178 bool HasRDSEED = false; 2179 bool HasADX = false; 2180 bool HasTBM = false; 2181 bool HasFMA = false; 2182 bool HasF16C = false; 2183 bool HasAVX512CD = false; 2184 bool HasAVX512ER = false; 2185 bool HasAVX512PF = false; 2186 bool HasAVX512DQ = false; 2187 bool HasAVX512BW = false; 2188 bool HasAVX512VL = false; 2189 bool HasAVX512VBMI = false; 2190 bool HasAVX512IFMA = false; 2191 bool HasSHA = false; 2192 bool HasMPX = false; 2193 bool HasSGX = false; 2194 bool HasCX16 = false; 2195 bool HasFXSR = false; 2196 bool HasXSAVE = false; 2197 bool HasXSAVEOPT = false; 2198 bool HasXSAVEC = false; 2199 bool HasXSAVES = false; 2200 bool HasPKU = false; 2201 bool HasCLFLUSHOPT = false; 2202 bool HasPCOMMIT = false; 2203 bool HasCLWB = false; 2204 bool HasUMIP = false; 2205 bool HasMOVBE = false; 2206 bool HasPREFETCHWT1 = false; 2207 2208 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2209 /// 2210 /// Each enumeration represents a particular CPU supported by Clang. These 2211 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2212 enum CPUKind { 2213 CK_Generic, 2214 2215 /// \name i386 2216 /// i386-generation processors. 2217 //@{ 2218 CK_i386, 2219 //@} 2220 2221 /// \name i486 2222 /// i486-generation processors. 2223 //@{ 2224 CK_i486, 2225 CK_WinChipC6, 2226 CK_WinChip2, 2227 CK_C3, 2228 //@} 2229 2230 /// \name i586 2231 /// i586-generation processors, P5 microarchitecture based. 2232 //@{ 2233 CK_i586, 2234 CK_Pentium, 2235 CK_PentiumMMX, 2236 //@} 2237 2238 /// \name i686 2239 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2240 //@{ 2241 CK_i686, 2242 CK_PentiumPro, 2243 CK_Pentium2, 2244 CK_Pentium3, 2245 CK_Pentium3M, 2246 CK_PentiumM, 2247 CK_C3_2, 2248 2249 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2250 /// Clang however has some logic to suport this. 2251 // FIXME: Warn, deprecate, and potentially remove this. 2252 CK_Yonah, 2253 //@} 2254 2255 /// \name Netburst 2256 /// Netburst microarchitecture based processors. 2257 //@{ 2258 CK_Pentium4, 2259 CK_Pentium4M, 2260 CK_Prescott, 2261 CK_Nocona, 2262 //@} 2263 2264 /// \name Core 2265 /// Core microarchitecture based processors. 2266 //@{ 2267 CK_Core2, 2268 2269 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2270 /// codename which GCC no longer accepts as an option to -march, but Clang 2271 /// has some logic for recognizing it. 2272 // FIXME: Warn, deprecate, and potentially remove this. 2273 CK_Penryn, 2274 //@} 2275 2276 /// \name Atom 2277 /// Atom processors 2278 //@{ 2279 CK_Bonnell, 2280 CK_Silvermont, 2281 //@} 2282 2283 /// \name Nehalem 2284 /// Nehalem microarchitecture based processors. 2285 CK_Nehalem, 2286 2287 /// \name Westmere 2288 /// Westmere microarchitecture based processors. 2289 CK_Westmere, 2290 2291 /// \name Sandy Bridge 2292 /// Sandy Bridge microarchitecture based processors. 2293 CK_SandyBridge, 2294 2295 /// \name Ivy Bridge 2296 /// Ivy Bridge microarchitecture based processors. 2297 CK_IvyBridge, 2298 2299 /// \name Haswell 2300 /// Haswell microarchitecture based processors. 2301 CK_Haswell, 2302 2303 /// \name Broadwell 2304 /// Broadwell microarchitecture based processors. 2305 CK_Broadwell, 2306 2307 /// \name Skylake Client 2308 /// Skylake client microarchitecture based processors. 2309 CK_SkylakeClient, 2310 2311 /// \name Skylake Server 2312 /// Skylake server microarchitecture based processors. 2313 CK_SkylakeServer, 2314 2315 /// \name Cannonlake Client 2316 /// Cannonlake client microarchitecture based processors. 2317 CK_Cannonlake, 2318 2319 /// \name Knights Landing 2320 /// Knights Landing processor. 2321 CK_KNL, 2322 2323 /// \name Lakemont 2324 /// Lakemont microarchitecture based processors. 2325 CK_Lakemont, 2326 2327 /// \name K6 2328 /// K6 architecture processors. 2329 //@{ 2330 CK_K6, 2331 CK_K6_2, 2332 CK_K6_3, 2333 //@} 2334 2335 /// \name K7 2336 /// K7 architecture processors. 2337 //@{ 2338 CK_Athlon, 2339 CK_AthlonThunderbird, 2340 CK_Athlon4, 2341 CK_AthlonXP, 2342 CK_AthlonMP, 2343 //@} 2344 2345 /// \name K8 2346 /// K8 architecture processors. 2347 //@{ 2348 CK_Athlon64, 2349 CK_Athlon64SSE3, 2350 CK_AthlonFX, 2351 CK_K8, 2352 CK_K8SSE3, 2353 CK_Opteron, 2354 CK_OpteronSSE3, 2355 CK_AMDFAM10, 2356 //@} 2357 2358 /// \name Bobcat 2359 /// Bobcat architecture processors. 2360 //@{ 2361 CK_BTVER1, 2362 CK_BTVER2, 2363 //@} 2364 2365 /// \name Bulldozer 2366 /// Bulldozer architecture processors. 2367 //@{ 2368 CK_BDVER1, 2369 CK_BDVER2, 2370 CK_BDVER3, 2371 CK_BDVER4, 2372 //@} 2373 2374 /// This specification is deprecated and will be removed in the future. 2375 /// Users should prefer \see CK_K8. 2376 // FIXME: Warn on this when the CPU is set to it. 2377 //@{ 2378 CK_x86_64, 2379 //@} 2380 2381 /// \name Geode 2382 /// Geode processors. 2383 //@{ 2384 CK_Geode 2385 //@} 2386 } CPU = CK_Generic; 2387 2388 CPUKind getCPUKind(StringRef CPU) const { 2389 return llvm::StringSwitch<CPUKind>(CPU) 2390 .Case("i386", CK_i386) 2391 .Case("i486", CK_i486) 2392 .Case("winchip-c6", CK_WinChipC6) 2393 .Case("winchip2", CK_WinChip2) 2394 .Case("c3", CK_C3) 2395 .Case("i586", CK_i586) 2396 .Case("pentium", CK_Pentium) 2397 .Case("pentium-mmx", CK_PentiumMMX) 2398 .Case("i686", CK_i686) 2399 .Case("pentiumpro", CK_PentiumPro) 2400 .Case("pentium2", CK_Pentium2) 2401 .Case("pentium3", CK_Pentium3) 2402 .Case("pentium3m", CK_Pentium3M) 2403 .Case("pentium-m", CK_PentiumM) 2404 .Case("c3-2", CK_C3_2) 2405 .Case("yonah", CK_Yonah) 2406 .Case("pentium4", CK_Pentium4) 2407 .Case("pentium4m", CK_Pentium4M) 2408 .Case("prescott", CK_Prescott) 2409 .Case("nocona", CK_Nocona) 2410 .Case("core2", CK_Core2) 2411 .Case("penryn", CK_Penryn) 2412 .Case("bonnell", CK_Bonnell) 2413 .Case("atom", CK_Bonnell) // Legacy name. 2414 .Case("silvermont", CK_Silvermont) 2415 .Case("slm", CK_Silvermont) // Legacy name. 2416 .Case("nehalem", CK_Nehalem) 2417 .Case("corei7", CK_Nehalem) // Legacy name. 2418 .Case("westmere", CK_Westmere) 2419 .Case("sandybridge", CK_SandyBridge) 2420 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2421 .Case("ivybridge", CK_IvyBridge) 2422 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2423 .Case("haswell", CK_Haswell) 2424 .Case("core-avx2", CK_Haswell) // Legacy name. 2425 .Case("broadwell", CK_Broadwell) 2426 .Case("skylake", CK_SkylakeClient) 2427 .Case("skylake-avx512", CK_SkylakeServer) 2428 .Case("skx", CK_SkylakeServer) // Legacy name. 2429 .Case("cannonlake", CK_Cannonlake) 2430 .Case("knl", CK_KNL) 2431 .Case("lakemont", CK_Lakemont) 2432 .Case("k6", CK_K6) 2433 .Case("k6-2", CK_K6_2) 2434 .Case("k6-3", CK_K6_3) 2435 .Case("athlon", CK_Athlon) 2436 .Case("athlon-tbird", CK_AthlonThunderbird) 2437 .Case("athlon-4", CK_Athlon4) 2438 .Case("athlon-xp", CK_AthlonXP) 2439 .Case("athlon-mp", CK_AthlonMP) 2440 .Case("athlon64", CK_Athlon64) 2441 .Case("athlon64-sse3", CK_Athlon64SSE3) 2442 .Case("athlon-fx", CK_AthlonFX) 2443 .Case("k8", CK_K8) 2444 .Case("k8-sse3", CK_K8SSE3) 2445 .Case("opteron", CK_Opteron) 2446 .Case("opteron-sse3", CK_OpteronSSE3) 2447 .Case("barcelona", CK_AMDFAM10) 2448 .Case("amdfam10", CK_AMDFAM10) 2449 .Case("btver1", CK_BTVER1) 2450 .Case("btver2", CK_BTVER2) 2451 .Case("bdver1", CK_BDVER1) 2452 .Case("bdver2", CK_BDVER2) 2453 .Case("bdver3", CK_BDVER3) 2454 .Case("bdver4", CK_BDVER4) 2455 .Case("x86-64", CK_x86_64) 2456 .Case("geode", CK_Geode) 2457 .Default(CK_Generic); 2458 } 2459 2460 enum FPMathKind { 2461 FP_Default, 2462 FP_SSE, 2463 FP_387 2464 } FPMath = FP_Default; 2465 2466 public: 2467 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2468 : TargetInfo(Triple) { 2469 BigEndian = false; 2470 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2471 } 2472 unsigned getFloatEvalMethod() const override { 2473 // X87 evaluates with 80 bits "long double" precision. 2474 return SSELevel == NoSSE ? 2 : 0; 2475 } 2476 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2477 return llvm::makeArrayRef(BuiltinInfo, 2478 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2479 } 2480 ArrayRef<const char *> getGCCRegNames() const override { 2481 return llvm::makeArrayRef(GCCRegNames); 2482 } 2483 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2484 return None; 2485 } 2486 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2487 return llvm::makeArrayRef(AddlRegNames); 2488 } 2489 bool validateCpuSupports(StringRef Name) const override; 2490 bool validateAsmConstraint(const char *&Name, 2491 TargetInfo::ConstraintInfo &info) const override; 2492 2493 bool validateGlobalRegisterVariable(StringRef RegName, 2494 unsigned RegSize, 2495 bool &HasSizeMismatch) const override { 2496 // esp and ebp are the only 32-bit registers the x86 backend can currently 2497 // handle. 2498 if (RegName.equals("esp") || RegName.equals("ebp")) { 2499 // Check that the register size is 32-bit. 2500 HasSizeMismatch = RegSize != 32; 2501 return true; 2502 } 2503 2504 return false; 2505 } 2506 2507 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2508 2509 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2510 2511 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2512 2513 std::string convertConstraint(const char *&Constraint) const override; 2514 const char *getClobbers() const override { 2515 return "~{dirflag},~{fpsr},~{flags}"; 2516 } 2517 void getTargetDefines(const LangOptions &Opts, 2518 MacroBuilder &Builder) const override; 2519 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2520 bool Enabled); 2521 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2522 bool Enabled); 2523 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2524 bool Enabled); 2525 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2526 StringRef Name, bool Enabled) const override { 2527 setFeatureEnabledImpl(Features, Name, Enabled); 2528 } 2529 // This exists purely to cut down on the number of virtual calls in 2530 // initFeatureMap which calls this repeatedly. 2531 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2532 StringRef Name, bool Enabled); 2533 bool 2534 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2535 StringRef CPU, 2536 const std::vector<std::string> &FeaturesVec) const override; 2537 bool hasFeature(StringRef Feature) const override; 2538 bool handleTargetFeatures(std::vector<std::string> &Features, 2539 DiagnosticsEngine &Diags) override; 2540 StringRef getABI() const override { 2541 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2542 return "avx512"; 2543 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2544 return "avx"; 2545 if (getTriple().getArch() == llvm::Triple::x86 && 2546 MMX3DNowLevel == NoMMX3DNow) 2547 return "no-mmx"; 2548 return ""; 2549 } 2550 bool setCPU(const std::string &Name) override { 2551 CPU = getCPUKind(Name); 2552 2553 // Perform any per-CPU checks necessary to determine if this CPU is 2554 // acceptable. 2555 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2556 // invalid without explaining *why*. 2557 switch (CPU) { 2558 case CK_Generic: 2559 // No processor selected! 2560 return false; 2561 2562 case CK_i386: 2563 case CK_i486: 2564 case CK_WinChipC6: 2565 case CK_WinChip2: 2566 case CK_C3: 2567 case CK_i586: 2568 case CK_Pentium: 2569 case CK_PentiumMMX: 2570 case CK_i686: 2571 case CK_PentiumPro: 2572 case CK_Pentium2: 2573 case CK_Pentium3: 2574 case CK_Pentium3M: 2575 case CK_PentiumM: 2576 case CK_Yonah: 2577 case CK_C3_2: 2578 case CK_Pentium4: 2579 case CK_Pentium4M: 2580 case CK_Lakemont: 2581 case CK_Prescott: 2582 case CK_K6: 2583 case CK_K6_2: 2584 case CK_K6_3: 2585 case CK_Athlon: 2586 case CK_AthlonThunderbird: 2587 case CK_Athlon4: 2588 case CK_AthlonXP: 2589 case CK_AthlonMP: 2590 case CK_Geode: 2591 // Only accept certain architectures when compiling in 32-bit mode. 2592 if (getTriple().getArch() != llvm::Triple::x86) 2593 return false; 2594 2595 // Fallthrough 2596 case CK_Nocona: 2597 case CK_Core2: 2598 case CK_Penryn: 2599 case CK_Bonnell: 2600 case CK_Silvermont: 2601 case CK_Nehalem: 2602 case CK_Westmere: 2603 case CK_SandyBridge: 2604 case CK_IvyBridge: 2605 case CK_Haswell: 2606 case CK_Broadwell: 2607 case CK_SkylakeClient: 2608 case CK_SkylakeServer: 2609 case CK_Cannonlake: 2610 case CK_KNL: 2611 case CK_Athlon64: 2612 case CK_Athlon64SSE3: 2613 case CK_AthlonFX: 2614 case CK_K8: 2615 case CK_K8SSE3: 2616 case CK_Opteron: 2617 case CK_OpteronSSE3: 2618 case CK_AMDFAM10: 2619 case CK_BTVER1: 2620 case CK_BTVER2: 2621 case CK_BDVER1: 2622 case CK_BDVER2: 2623 case CK_BDVER3: 2624 case CK_BDVER4: 2625 case CK_x86_64: 2626 return true; 2627 } 2628 llvm_unreachable("Unhandled CPU kind"); 2629 } 2630 2631 bool setFPMath(StringRef Name) override; 2632 2633 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2634 // Most of the non-ARM calling conventions are i386 conventions. 2635 switch (CC) { 2636 case CC_X86ThisCall: 2637 case CC_X86FastCall: 2638 case CC_X86StdCall: 2639 case CC_X86VectorCall: 2640 case CC_C: 2641 case CC_Swift: 2642 case CC_X86Pascal: 2643 case CC_IntelOclBicc: 2644 return CCCR_OK; 2645 default: 2646 return CCCR_Warning; 2647 } 2648 } 2649 2650 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2651 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2652 } 2653 2654 bool hasSjLjLowering() const override { 2655 return true; 2656 } 2657 }; 2658 2659 bool X86TargetInfo::setFPMath(StringRef Name) { 2660 if (Name == "387") { 2661 FPMath = FP_387; 2662 return true; 2663 } 2664 if (Name == "sse") { 2665 FPMath = FP_SSE; 2666 return true; 2667 } 2668 return false; 2669 } 2670 2671 bool X86TargetInfo::initFeatureMap( 2672 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2673 const std::vector<std::string> &FeaturesVec) const { 2674 // FIXME: This *really* should not be here. 2675 // X86_64 always has SSE2. 2676 if (getTriple().getArch() == llvm::Triple::x86_64) 2677 setFeatureEnabledImpl(Features, "sse2", true); 2678 2679 const CPUKind Kind = getCPUKind(CPU); 2680 2681 // Enable X87 for all X86 processors but Lakemont. 2682 if (Kind != CK_Lakemont) 2683 setFeatureEnabledImpl(Features, "x87", true); 2684 2685 switch (Kind) { 2686 case CK_Generic: 2687 case CK_i386: 2688 case CK_i486: 2689 case CK_i586: 2690 case CK_Pentium: 2691 case CK_i686: 2692 case CK_PentiumPro: 2693 case CK_Lakemont: 2694 break; 2695 case CK_PentiumMMX: 2696 case CK_Pentium2: 2697 case CK_K6: 2698 case CK_WinChipC6: 2699 setFeatureEnabledImpl(Features, "mmx", true); 2700 break; 2701 case CK_Pentium3: 2702 case CK_Pentium3M: 2703 case CK_C3_2: 2704 setFeatureEnabledImpl(Features, "sse", true); 2705 setFeatureEnabledImpl(Features, "fxsr", true); 2706 break; 2707 case CK_PentiumM: 2708 case CK_Pentium4: 2709 case CK_Pentium4M: 2710 case CK_x86_64: 2711 setFeatureEnabledImpl(Features, "sse2", true); 2712 setFeatureEnabledImpl(Features, "fxsr", true); 2713 break; 2714 case CK_Yonah: 2715 case CK_Prescott: 2716 case CK_Nocona: 2717 setFeatureEnabledImpl(Features, "sse3", true); 2718 setFeatureEnabledImpl(Features, "fxsr", true); 2719 setFeatureEnabledImpl(Features, "cx16", true); 2720 break; 2721 case CK_Core2: 2722 case CK_Bonnell: 2723 setFeatureEnabledImpl(Features, "ssse3", true); 2724 setFeatureEnabledImpl(Features, "fxsr", true); 2725 setFeatureEnabledImpl(Features, "cx16", true); 2726 break; 2727 case CK_Penryn: 2728 setFeatureEnabledImpl(Features, "sse4.1", true); 2729 setFeatureEnabledImpl(Features, "fxsr", true); 2730 setFeatureEnabledImpl(Features, "cx16", true); 2731 break; 2732 case CK_Cannonlake: 2733 setFeatureEnabledImpl(Features, "avx512ifma", true); 2734 setFeatureEnabledImpl(Features, "avx512vbmi", true); 2735 setFeatureEnabledImpl(Features, "sha", true); 2736 setFeatureEnabledImpl(Features, "umip", true); 2737 // FALLTHROUGH 2738 case CK_SkylakeServer: 2739 setFeatureEnabledImpl(Features, "avx512f", true); 2740 setFeatureEnabledImpl(Features, "avx512cd", true); 2741 setFeatureEnabledImpl(Features, "avx512dq", true); 2742 setFeatureEnabledImpl(Features, "avx512bw", true); 2743 setFeatureEnabledImpl(Features, "avx512vl", true); 2744 setFeatureEnabledImpl(Features, "pku", true); 2745 setFeatureEnabledImpl(Features, "pcommit", true); 2746 setFeatureEnabledImpl(Features, "clwb", true); 2747 // FALLTHROUGH 2748 case CK_SkylakeClient: 2749 setFeatureEnabledImpl(Features, "xsavec", true); 2750 setFeatureEnabledImpl(Features, "xsaves", true); 2751 setFeatureEnabledImpl(Features, "mpx", true); 2752 setFeatureEnabledImpl(Features, "sgx", true); 2753 setFeatureEnabledImpl(Features, "clflushopt", true); 2754 // FALLTHROUGH 2755 case CK_Broadwell: 2756 setFeatureEnabledImpl(Features, "rdseed", true); 2757 setFeatureEnabledImpl(Features, "adx", true); 2758 // FALLTHROUGH 2759 case CK_Haswell: 2760 setFeatureEnabledImpl(Features, "avx2", true); 2761 setFeatureEnabledImpl(Features, "lzcnt", true); 2762 setFeatureEnabledImpl(Features, "bmi", true); 2763 setFeatureEnabledImpl(Features, "bmi2", true); 2764 setFeatureEnabledImpl(Features, "rtm", true); 2765 setFeatureEnabledImpl(Features, "fma", true); 2766 setFeatureEnabledImpl(Features, "movbe", true); 2767 // FALLTHROUGH 2768 case CK_IvyBridge: 2769 setFeatureEnabledImpl(Features, "rdrnd", true); 2770 setFeatureEnabledImpl(Features, "f16c", true); 2771 setFeatureEnabledImpl(Features, "fsgsbase", true); 2772 // FALLTHROUGH 2773 case CK_SandyBridge: 2774 setFeatureEnabledImpl(Features, "avx", true); 2775 setFeatureEnabledImpl(Features, "xsave", true); 2776 setFeatureEnabledImpl(Features, "xsaveopt", true); 2777 // FALLTHROUGH 2778 case CK_Westmere: 2779 case CK_Silvermont: 2780 setFeatureEnabledImpl(Features, "aes", true); 2781 setFeatureEnabledImpl(Features, "pclmul", true); 2782 // FALLTHROUGH 2783 case CK_Nehalem: 2784 setFeatureEnabledImpl(Features, "sse4.2", true); 2785 setFeatureEnabledImpl(Features, "fxsr", true); 2786 setFeatureEnabledImpl(Features, "cx16", true); 2787 break; 2788 case CK_KNL: 2789 setFeatureEnabledImpl(Features, "avx512f", true); 2790 setFeatureEnabledImpl(Features, "avx512cd", true); 2791 setFeatureEnabledImpl(Features, "avx512er", true); 2792 setFeatureEnabledImpl(Features, "avx512pf", true); 2793 setFeatureEnabledImpl(Features, "prefetchwt1", true); 2794 setFeatureEnabledImpl(Features, "fxsr", true); 2795 setFeatureEnabledImpl(Features, "rdseed", true); 2796 setFeatureEnabledImpl(Features, "adx", true); 2797 setFeatureEnabledImpl(Features, "lzcnt", true); 2798 setFeatureEnabledImpl(Features, "bmi", true); 2799 setFeatureEnabledImpl(Features, "bmi2", true); 2800 setFeatureEnabledImpl(Features, "rtm", true); 2801 setFeatureEnabledImpl(Features, "fma", true); 2802 setFeatureEnabledImpl(Features, "rdrnd", true); 2803 setFeatureEnabledImpl(Features, "f16c", true); 2804 setFeatureEnabledImpl(Features, "fsgsbase", true); 2805 setFeatureEnabledImpl(Features, "aes", true); 2806 setFeatureEnabledImpl(Features, "pclmul", true); 2807 setFeatureEnabledImpl(Features, "cx16", true); 2808 setFeatureEnabledImpl(Features, "xsaveopt", true); 2809 setFeatureEnabledImpl(Features, "xsave", true); 2810 setFeatureEnabledImpl(Features, "movbe", true); 2811 break; 2812 case CK_K6_2: 2813 case CK_K6_3: 2814 case CK_WinChip2: 2815 case CK_C3: 2816 setFeatureEnabledImpl(Features, "3dnow", true); 2817 break; 2818 case CK_Athlon: 2819 case CK_AthlonThunderbird: 2820 case CK_Geode: 2821 setFeatureEnabledImpl(Features, "3dnowa", true); 2822 break; 2823 case CK_Athlon4: 2824 case CK_AthlonXP: 2825 case CK_AthlonMP: 2826 setFeatureEnabledImpl(Features, "sse", true); 2827 setFeatureEnabledImpl(Features, "3dnowa", true); 2828 setFeatureEnabledImpl(Features, "fxsr", true); 2829 break; 2830 case CK_K8: 2831 case CK_Opteron: 2832 case CK_Athlon64: 2833 case CK_AthlonFX: 2834 setFeatureEnabledImpl(Features, "sse2", true); 2835 setFeatureEnabledImpl(Features, "3dnowa", true); 2836 setFeatureEnabledImpl(Features, "fxsr", true); 2837 break; 2838 case CK_AMDFAM10: 2839 setFeatureEnabledImpl(Features, "sse4a", true); 2840 setFeatureEnabledImpl(Features, "lzcnt", true); 2841 setFeatureEnabledImpl(Features, "popcnt", true); 2842 // FALLTHROUGH 2843 case CK_K8SSE3: 2844 case CK_OpteronSSE3: 2845 case CK_Athlon64SSE3: 2846 setFeatureEnabledImpl(Features, "sse3", true); 2847 setFeatureEnabledImpl(Features, "3dnowa", true); 2848 setFeatureEnabledImpl(Features, "fxsr", true); 2849 break; 2850 case CK_BTVER2: 2851 setFeatureEnabledImpl(Features, "avx", true); 2852 setFeatureEnabledImpl(Features, "aes", true); 2853 setFeatureEnabledImpl(Features, "pclmul", true); 2854 setFeatureEnabledImpl(Features, "bmi", true); 2855 setFeatureEnabledImpl(Features, "f16c", true); 2856 setFeatureEnabledImpl(Features, "xsaveopt", true); 2857 // FALLTHROUGH 2858 case CK_BTVER1: 2859 setFeatureEnabledImpl(Features, "ssse3", true); 2860 setFeatureEnabledImpl(Features, "sse4a", true); 2861 setFeatureEnabledImpl(Features, "lzcnt", true); 2862 setFeatureEnabledImpl(Features, "popcnt", true); 2863 setFeatureEnabledImpl(Features, "prfchw", true); 2864 setFeatureEnabledImpl(Features, "cx16", true); 2865 setFeatureEnabledImpl(Features, "fxsr", true); 2866 break; 2867 case CK_BDVER4: 2868 setFeatureEnabledImpl(Features, "avx2", true); 2869 setFeatureEnabledImpl(Features, "bmi2", true); 2870 // FALLTHROUGH 2871 case CK_BDVER3: 2872 setFeatureEnabledImpl(Features, "fsgsbase", true); 2873 setFeatureEnabledImpl(Features, "xsaveopt", true); 2874 // FALLTHROUGH 2875 case CK_BDVER2: 2876 setFeatureEnabledImpl(Features, "bmi", true); 2877 setFeatureEnabledImpl(Features, "fma", true); 2878 setFeatureEnabledImpl(Features, "f16c", true); 2879 setFeatureEnabledImpl(Features, "tbm", true); 2880 // FALLTHROUGH 2881 case CK_BDVER1: 2882 // xop implies avx, sse4a and fma4. 2883 setFeatureEnabledImpl(Features, "xop", true); 2884 setFeatureEnabledImpl(Features, "lzcnt", true); 2885 setFeatureEnabledImpl(Features, "aes", true); 2886 setFeatureEnabledImpl(Features, "pclmul", true); 2887 setFeatureEnabledImpl(Features, "prfchw", true); 2888 setFeatureEnabledImpl(Features, "cx16", true); 2889 setFeatureEnabledImpl(Features, "fxsr", true); 2890 setFeatureEnabledImpl(Features, "xsave", true); 2891 break; 2892 } 2893 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 2894 return false; 2895 2896 // Can't do this earlier because we need to be able to explicitly enable 2897 // or disable these features and the things that they depend upon. 2898 2899 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2900 auto I = Features.find("sse4.2"); 2901 if (I != Features.end() && I->getValue() && 2902 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 2903 FeaturesVec.end()) 2904 Features["popcnt"] = true; 2905 2906 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2907 I = Features.find("3dnow"); 2908 if (I != Features.end() && I->getValue() && 2909 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 2910 FeaturesVec.end()) 2911 Features["prfchw"] = true; 2912 2913 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2914 // then enable MMX. 2915 I = Features.find("sse"); 2916 if (I != Features.end() && I->getValue() && 2917 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 2918 FeaturesVec.end()) 2919 Features["mmx"] = true; 2920 2921 return true; 2922 } 2923 2924 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2925 X86SSEEnum Level, bool Enabled) { 2926 if (Enabled) { 2927 switch (Level) { 2928 case AVX512F: 2929 Features["avx512f"] = true; 2930 case AVX2: 2931 Features["avx2"] = true; 2932 case AVX: 2933 Features["avx"] = true; 2934 Features["xsave"] = true; 2935 case SSE42: 2936 Features["sse4.2"] = true; 2937 case SSE41: 2938 Features["sse4.1"] = true; 2939 case SSSE3: 2940 Features["ssse3"] = true; 2941 case SSE3: 2942 Features["sse3"] = true; 2943 case SSE2: 2944 Features["sse2"] = true; 2945 case SSE1: 2946 Features["sse"] = true; 2947 case NoSSE: 2948 break; 2949 } 2950 return; 2951 } 2952 2953 switch (Level) { 2954 case NoSSE: 2955 case SSE1: 2956 Features["sse"] = false; 2957 case SSE2: 2958 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2959 Features["sha"] = false; 2960 case SSE3: 2961 Features["sse3"] = false; 2962 setXOPLevel(Features, NoXOP, false); 2963 case SSSE3: 2964 Features["ssse3"] = false; 2965 case SSE41: 2966 Features["sse4.1"] = false; 2967 case SSE42: 2968 Features["sse4.2"] = false; 2969 case AVX: 2970 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 2971 Features["xsaveopt"] = false; 2972 setXOPLevel(Features, FMA4, false); 2973 case AVX2: 2974 Features["avx2"] = false; 2975 case AVX512F: 2976 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2977 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2978 Features["avx512vl"] = Features["avx512vbmi"] = 2979 Features["avx512ifma"] = false; 2980 } 2981 } 2982 2983 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2984 MMX3DNowEnum Level, bool Enabled) { 2985 if (Enabled) { 2986 switch (Level) { 2987 case AMD3DNowAthlon: 2988 Features["3dnowa"] = true; 2989 case AMD3DNow: 2990 Features["3dnow"] = true; 2991 case MMX: 2992 Features["mmx"] = true; 2993 case NoMMX3DNow: 2994 break; 2995 } 2996 return; 2997 } 2998 2999 switch (Level) { 3000 case NoMMX3DNow: 3001 case MMX: 3002 Features["mmx"] = false; 3003 case AMD3DNow: 3004 Features["3dnow"] = false; 3005 case AMD3DNowAthlon: 3006 Features["3dnowa"] = false; 3007 } 3008 } 3009 3010 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3011 bool Enabled) { 3012 if (Enabled) { 3013 switch (Level) { 3014 case XOP: 3015 Features["xop"] = true; 3016 case FMA4: 3017 Features["fma4"] = true; 3018 setSSELevel(Features, AVX, true); 3019 case SSE4A: 3020 Features["sse4a"] = true; 3021 setSSELevel(Features, SSE3, true); 3022 case NoXOP: 3023 break; 3024 } 3025 return; 3026 } 3027 3028 switch (Level) { 3029 case NoXOP: 3030 case SSE4A: 3031 Features["sse4a"] = false; 3032 case FMA4: 3033 Features["fma4"] = false; 3034 case XOP: 3035 Features["xop"] = false; 3036 } 3037 } 3038 3039 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3040 StringRef Name, bool Enabled) { 3041 // This is a bit of a hack to deal with the sse4 target feature when used 3042 // as part of the target attribute. We handle sse4 correctly everywhere 3043 // else. See below for more information on how we handle the sse4 options. 3044 if (Name != "sse4") 3045 Features[Name] = Enabled; 3046 3047 if (Name == "mmx") { 3048 setMMXLevel(Features, MMX, Enabled); 3049 } else if (Name == "sse") { 3050 setSSELevel(Features, SSE1, Enabled); 3051 } else if (Name == "sse2") { 3052 setSSELevel(Features, SSE2, Enabled); 3053 } else if (Name == "sse3") { 3054 setSSELevel(Features, SSE3, Enabled); 3055 } else if (Name == "ssse3") { 3056 setSSELevel(Features, SSSE3, Enabled); 3057 } else if (Name == "sse4.2") { 3058 setSSELevel(Features, SSE42, Enabled); 3059 } else if (Name == "sse4.1") { 3060 setSSELevel(Features, SSE41, Enabled); 3061 } else if (Name == "3dnow") { 3062 setMMXLevel(Features, AMD3DNow, Enabled); 3063 } else if (Name == "3dnowa") { 3064 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3065 } else if (Name == "aes") { 3066 if (Enabled) 3067 setSSELevel(Features, SSE2, Enabled); 3068 } else if (Name == "pclmul") { 3069 if (Enabled) 3070 setSSELevel(Features, SSE2, Enabled); 3071 } else if (Name == "avx") { 3072 setSSELevel(Features, AVX, Enabled); 3073 } else if (Name == "avx2") { 3074 setSSELevel(Features, AVX2, Enabled); 3075 } else if (Name == "avx512f") { 3076 setSSELevel(Features, AVX512F, Enabled); 3077 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3078 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3079 Name == "avx512vbmi" || Name == "avx512ifma") { 3080 if (Enabled) 3081 setSSELevel(Features, AVX512F, Enabled); 3082 } else if (Name == "fma") { 3083 if (Enabled) 3084 setSSELevel(Features, AVX, Enabled); 3085 } else if (Name == "fma4") { 3086 setXOPLevel(Features, FMA4, Enabled); 3087 } else if (Name == "xop") { 3088 setXOPLevel(Features, XOP, Enabled); 3089 } else if (Name == "sse4a") { 3090 setXOPLevel(Features, SSE4A, Enabled); 3091 } else if (Name == "f16c") { 3092 if (Enabled) 3093 setSSELevel(Features, AVX, Enabled); 3094 } else if (Name == "sha") { 3095 if (Enabled) 3096 setSSELevel(Features, SSE2, Enabled); 3097 } else if (Name == "sse4") { 3098 // We can get here via the __target__ attribute since that's not controlled 3099 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3100 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3101 // disabled. 3102 if (Enabled) 3103 setSSELevel(Features, SSE42, Enabled); 3104 else 3105 setSSELevel(Features, SSE41, Enabled); 3106 } else if (Name == "xsave") { 3107 if (!Enabled) 3108 Features["xsaveopt"] = false; 3109 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3110 if (Enabled) 3111 Features["xsave"] = true; 3112 } 3113 } 3114 3115 /// handleTargetFeatures - Perform initialization based on the user 3116 /// configured set of features. 3117 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3118 DiagnosticsEngine &Diags) { 3119 for (const auto &Feature : Features) { 3120 if (Feature[0] != '+') 3121 continue; 3122 3123 if (Feature == "+aes") { 3124 HasAES = true; 3125 } else if (Feature == "+pclmul") { 3126 HasPCLMUL = true; 3127 } else if (Feature == "+lzcnt") { 3128 HasLZCNT = true; 3129 } else if (Feature == "+rdrnd") { 3130 HasRDRND = true; 3131 } else if (Feature == "+fsgsbase") { 3132 HasFSGSBASE = true; 3133 } else if (Feature == "+bmi") { 3134 HasBMI = true; 3135 } else if (Feature == "+bmi2") { 3136 HasBMI2 = true; 3137 } else if (Feature == "+popcnt") { 3138 HasPOPCNT = true; 3139 } else if (Feature == "+rtm") { 3140 HasRTM = true; 3141 } else if (Feature == "+prfchw") { 3142 HasPRFCHW = true; 3143 } else if (Feature == "+rdseed") { 3144 HasRDSEED = true; 3145 } else if (Feature == "+adx") { 3146 HasADX = true; 3147 } else if (Feature == "+tbm") { 3148 HasTBM = true; 3149 } else if (Feature == "+fma") { 3150 HasFMA = true; 3151 } else if (Feature == "+f16c") { 3152 HasF16C = true; 3153 } else if (Feature == "+avx512cd") { 3154 HasAVX512CD = true; 3155 } else if (Feature == "+avx512er") { 3156 HasAVX512ER = true; 3157 } else if (Feature == "+avx512pf") { 3158 HasAVX512PF = true; 3159 } else if (Feature == "+avx512dq") { 3160 HasAVX512DQ = true; 3161 } else if (Feature == "+avx512bw") { 3162 HasAVX512BW = true; 3163 } else if (Feature == "+avx512vl") { 3164 HasAVX512VL = true; 3165 } else if (Feature == "+avx512vbmi") { 3166 HasAVX512VBMI = true; 3167 } else if (Feature == "+avx512ifma") { 3168 HasAVX512IFMA = true; 3169 } else if (Feature == "+sha") { 3170 HasSHA = true; 3171 } else if (Feature == "+mpx") { 3172 HasMPX = true; 3173 } else if (Feature == "+movbe") { 3174 HasMOVBE = true; 3175 } else if (Feature == "+sgx") { 3176 HasSGX = true; 3177 } else if (Feature == "+cx16") { 3178 HasCX16 = true; 3179 } else if (Feature == "+fxsr") { 3180 HasFXSR = true; 3181 } else if (Feature == "+xsave") { 3182 HasXSAVE = true; 3183 } else if (Feature == "+xsaveopt") { 3184 HasXSAVEOPT = true; 3185 } else if (Feature == "+xsavec") { 3186 HasXSAVEC = true; 3187 } else if (Feature == "+xsaves") { 3188 HasXSAVES = true; 3189 } else if (Feature == "+pku") { 3190 HasPKU = true; 3191 } else if (Feature == "+clflushopt") { 3192 HasCLFLUSHOPT = true; 3193 } else if (Feature == "+pcommit") { 3194 HasPCOMMIT = true; 3195 } else if (Feature == "+clwb") { 3196 HasCLWB = true; 3197 } else if (Feature == "+umip") { 3198 HasUMIP = true; 3199 } else if (Feature == "+prefetchwt1") { 3200 HasPREFETCHWT1 = true; 3201 } 3202 3203 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3204 .Case("+avx512f", AVX512F) 3205 .Case("+avx2", AVX2) 3206 .Case("+avx", AVX) 3207 .Case("+sse4.2", SSE42) 3208 .Case("+sse4.1", SSE41) 3209 .Case("+ssse3", SSSE3) 3210 .Case("+sse3", SSE3) 3211 .Case("+sse2", SSE2) 3212 .Case("+sse", SSE1) 3213 .Default(NoSSE); 3214 SSELevel = std::max(SSELevel, Level); 3215 3216 MMX3DNowEnum ThreeDNowLevel = 3217 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3218 .Case("+3dnowa", AMD3DNowAthlon) 3219 .Case("+3dnow", AMD3DNow) 3220 .Case("+mmx", MMX) 3221 .Default(NoMMX3DNow); 3222 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3223 3224 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3225 .Case("+xop", XOP) 3226 .Case("+fma4", FMA4) 3227 .Case("+sse4a", SSE4A) 3228 .Default(NoXOP); 3229 XOPLevel = std::max(XOPLevel, XLevel); 3230 } 3231 3232 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3233 // matches the selected sse level. 3234 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3235 (FPMath == FP_387 && SSELevel >= SSE1)) { 3236 Diags.Report(diag::err_target_unsupported_fpmath) << 3237 (FPMath == FP_SSE ? "sse" : "387"); 3238 return false; 3239 } 3240 3241 SimdDefaultAlign = 3242 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3243 return true; 3244 } 3245 3246 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3247 /// definitions for this particular subtarget. 3248 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3249 MacroBuilder &Builder) const { 3250 // Target identification. 3251 if (getTriple().getArch() == llvm::Triple::x86_64) { 3252 Builder.defineMacro("__amd64__"); 3253 Builder.defineMacro("__amd64"); 3254 Builder.defineMacro("__x86_64"); 3255 Builder.defineMacro("__x86_64__"); 3256 if (getTriple().getArchName() == "x86_64h") { 3257 Builder.defineMacro("__x86_64h"); 3258 Builder.defineMacro("__x86_64h__"); 3259 } 3260 } else { 3261 DefineStd(Builder, "i386", Opts); 3262 } 3263 3264 // Subtarget options. 3265 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3266 // truly should be based on -mtune options. 3267 switch (CPU) { 3268 case CK_Generic: 3269 break; 3270 case CK_i386: 3271 // The rest are coming from the i386 define above. 3272 Builder.defineMacro("__tune_i386__"); 3273 break; 3274 case CK_i486: 3275 case CK_WinChipC6: 3276 case CK_WinChip2: 3277 case CK_C3: 3278 defineCPUMacros(Builder, "i486"); 3279 break; 3280 case CK_PentiumMMX: 3281 Builder.defineMacro("__pentium_mmx__"); 3282 Builder.defineMacro("__tune_pentium_mmx__"); 3283 // Fallthrough 3284 case CK_i586: 3285 case CK_Pentium: 3286 defineCPUMacros(Builder, "i586"); 3287 defineCPUMacros(Builder, "pentium"); 3288 break; 3289 case CK_Pentium3: 3290 case CK_Pentium3M: 3291 case CK_PentiumM: 3292 Builder.defineMacro("__tune_pentium3__"); 3293 // Fallthrough 3294 case CK_Pentium2: 3295 case CK_C3_2: 3296 Builder.defineMacro("__tune_pentium2__"); 3297 // Fallthrough 3298 case CK_PentiumPro: 3299 Builder.defineMacro("__tune_i686__"); 3300 Builder.defineMacro("__tune_pentiumpro__"); 3301 // Fallthrough 3302 case CK_i686: 3303 Builder.defineMacro("__i686"); 3304 Builder.defineMacro("__i686__"); 3305 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3306 Builder.defineMacro("__pentiumpro"); 3307 Builder.defineMacro("__pentiumpro__"); 3308 break; 3309 case CK_Pentium4: 3310 case CK_Pentium4M: 3311 defineCPUMacros(Builder, "pentium4"); 3312 break; 3313 case CK_Yonah: 3314 case CK_Prescott: 3315 case CK_Nocona: 3316 defineCPUMacros(Builder, "nocona"); 3317 break; 3318 case CK_Core2: 3319 case CK_Penryn: 3320 defineCPUMacros(Builder, "core2"); 3321 break; 3322 case CK_Bonnell: 3323 defineCPUMacros(Builder, "atom"); 3324 break; 3325 case CK_Silvermont: 3326 defineCPUMacros(Builder, "slm"); 3327 break; 3328 case CK_Nehalem: 3329 case CK_Westmere: 3330 case CK_SandyBridge: 3331 case CK_IvyBridge: 3332 case CK_Haswell: 3333 case CK_Broadwell: 3334 case CK_SkylakeClient: 3335 // FIXME: Historically, we defined this legacy name, it would be nice to 3336 // remove it at some point. We've never exposed fine-grained names for 3337 // recent primary x86 CPUs, and we should keep it that way. 3338 defineCPUMacros(Builder, "corei7"); 3339 break; 3340 case CK_SkylakeServer: 3341 defineCPUMacros(Builder, "skx"); 3342 break; 3343 case CK_Cannonlake: 3344 break; 3345 case CK_KNL: 3346 defineCPUMacros(Builder, "knl"); 3347 break; 3348 case CK_Lakemont: 3349 Builder.defineMacro("__tune_lakemont__"); 3350 break; 3351 case CK_K6_2: 3352 Builder.defineMacro("__k6_2__"); 3353 Builder.defineMacro("__tune_k6_2__"); 3354 // Fallthrough 3355 case CK_K6_3: 3356 if (CPU != CK_K6_2) { // In case of fallthrough 3357 // FIXME: GCC may be enabling these in cases where some other k6 3358 // architecture is specified but -m3dnow is explicitly provided. The 3359 // exact semantics need to be determined and emulated here. 3360 Builder.defineMacro("__k6_3__"); 3361 Builder.defineMacro("__tune_k6_3__"); 3362 } 3363 // Fallthrough 3364 case CK_K6: 3365 defineCPUMacros(Builder, "k6"); 3366 break; 3367 case CK_Athlon: 3368 case CK_AthlonThunderbird: 3369 case CK_Athlon4: 3370 case CK_AthlonXP: 3371 case CK_AthlonMP: 3372 defineCPUMacros(Builder, "athlon"); 3373 if (SSELevel != NoSSE) { 3374 Builder.defineMacro("__athlon_sse__"); 3375 Builder.defineMacro("__tune_athlon_sse__"); 3376 } 3377 break; 3378 case CK_K8: 3379 case CK_K8SSE3: 3380 case CK_x86_64: 3381 case CK_Opteron: 3382 case CK_OpteronSSE3: 3383 case CK_Athlon64: 3384 case CK_Athlon64SSE3: 3385 case CK_AthlonFX: 3386 defineCPUMacros(Builder, "k8"); 3387 break; 3388 case CK_AMDFAM10: 3389 defineCPUMacros(Builder, "amdfam10"); 3390 break; 3391 case CK_BTVER1: 3392 defineCPUMacros(Builder, "btver1"); 3393 break; 3394 case CK_BTVER2: 3395 defineCPUMacros(Builder, "btver2"); 3396 break; 3397 case CK_BDVER1: 3398 defineCPUMacros(Builder, "bdver1"); 3399 break; 3400 case CK_BDVER2: 3401 defineCPUMacros(Builder, "bdver2"); 3402 break; 3403 case CK_BDVER3: 3404 defineCPUMacros(Builder, "bdver3"); 3405 break; 3406 case CK_BDVER4: 3407 defineCPUMacros(Builder, "bdver4"); 3408 break; 3409 case CK_Geode: 3410 defineCPUMacros(Builder, "geode"); 3411 break; 3412 } 3413 3414 // Target properties. 3415 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3416 3417 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3418 // functions in glibc header files that use FP Stack inline asm which the 3419 // backend can't deal with (PR879). 3420 Builder.defineMacro("__NO_MATH_INLINES"); 3421 3422 if (HasAES) 3423 Builder.defineMacro("__AES__"); 3424 3425 if (HasPCLMUL) 3426 Builder.defineMacro("__PCLMUL__"); 3427 3428 if (HasLZCNT) 3429 Builder.defineMacro("__LZCNT__"); 3430 3431 if (HasRDRND) 3432 Builder.defineMacro("__RDRND__"); 3433 3434 if (HasFSGSBASE) 3435 Builder.defineMacro("__FSGSBASE__"); 3436 3437 if (HasBMI) 3438 Builder.defineMacro("__BMI__"); 3439 3440 if (HasBMI2) 3441 Builder.defineMacro("__BMI2__"); 3442 3443 if (HasPOPCNT) 3444 Builder.defineMacro("__POPCNT__"); 3445 3446 if (HasRTM) 3447 Builder.defineMacro("__RTM__"); 3448 3449 if (HasPRFCHW) 3450 Builder.defineMacro("__PRFCHW__"); 3451 3452 if (HasRDSEED) 3453 Builder.defineMacro("__RDSEED__"); 3454 3455 if (HasADX) 3456 Builder.defineMacro("__ADX__"); 3457 3458 if (HasTBM) 3459 Builder.defineMacro("__TBM__"); 3460 3461 switch (XOPLevel) { 3462 case XOP: 3463 Builder.defineMacro("__XOP__"); 3464 case FMA4: 3465 Builder.defineMacro("__FMA4__"); 3466 case SSE4A: 3467 Builder.defineMacro("__SSE4A__"); 3468 case NoXOP: 3469 break; 3470 } 3471 3472 if (HasFMA) 3473 Builder.defineMacro("__FMA__"); 3474 3475 if (HasF16C) 3476 Builder.defineMacro("__F16C__"); 3477 3478 if (HasAVX512CD) 3479 Builder.defineMacro("__AVX512CD__"); 3480 if (HasAVX512ER) 3481 Builder.defineMacro("__AVX512ER__"); 3482 if (HasAVX512PF) 3483 Builder.defineMacro("__AVX512PF__"); 3484 if (HasAVX512DQ) 3485 Builder.defineMacro("__AVX512DQ__"); 3486 if (HasAVX512BW) 3487 Builder.defineMacro("__AVX512BW__"); 3488 if (HasAVX512VL) 3489 Builder.defineMacro("__AVX512VL__"); 3490 if (HasAVX512VBMI) 3491 Builder.defineMacro("__AVX512VBMI__"); 3492 if (HasAVX512IFMA) 3493 Builder.defineMacro("__AVX512IFMA__"); 3494 3495 if (HasSHA) 3496 Builder.defineMacro("__SHA__"); 3497 3498 if (HasFXSR) 3499 Builder.defineMacro("__FXSR__"); 3500 if (HasXSAVE) 3501 Builder.defineMacro("__XSAVE__"); 3502 if (HasXSAVEOPT) 3503 Builder.defineMacro("__XSAVEOPT__"); 3504 if (HasXSAVEC) 3505 Builder.defineMacro("__XSAVEC__"); 3506 if (HasXSAVES) 3507 Builder.defineMacro("__XSAVES__"); 3508 if (HasPKU) 3509 Builder.defineMacro("__PKU__"); 3510 if (HasCX16) 3511 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3512 3513 // Each case falls through to the previous one here. 3514 switch (SSELevel) { 3515 case AVX512F: 3516 Builder.defineMacro("__AVX512F__"); 3517 case AVX2: 3518 Builder.defineMacro("__AVX2__"); 3519 case AVX: 3520 Builder.defineMacro("__AVX__"); 3521 case SSE42: 3522 Builder.defineMacro("__SSE4_2__"); 3523 case SSE41: 3524 Builder.defineMacro("__SSE4_1__"); 3525 case SSSE3: 3526 Builder.defineMacro("__SSSE3__"); 3527 case SSE3: 3528 Builder.defineMacro("__SSE3__"); 3529 case SSE2: 3530 Builder.defineMacro("__SSE2__"); 3531 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3532 case SSE1: 3533 Builder.defineMacro("__SSE__"); 3534 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3535 case NoSSE: 3536 break; 3537 } 3538 3539 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3540 switch (SSELevel) { 3541 case AVX512F: 3542 case AVX2: 3543 case AVX: 3544 case SSE42: 3545 case SSE41: 3546 case SSSE3: 3547 case SSE3: 3548 case SSE2: 3549 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3550 break; 3551 case SSE1: 3552 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3553 break; 3554 default: 3555 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3556 } 3557 } 3558 3559 // Each case falls through to the previous one here. 3560 switch (MMX3DNowLevel) { 3561 case AMD3DNowAthlon: 3562 Builder.defineMacro("__3dNOW_A__"); 3563 case AMD3DNow: 3564 Builder.defineMacro("__3dNOW__"); 3565 case MMX: 3566 Builder.defineMacro("__MMX__"); 3567 case NoMMX3DNow: 3568 break; 3569 } 3570 3571 if (CPU >= CK_i486) { 3572 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3573 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3574 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3575 } 3576 if (CPU >= CK_i586) 3577 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3578 } 3579 3580 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3581 return llvm::StringSwitch<bool>(Feature) 3582 .Case("aes", HasAES) 3583 .Case("avx", SSELevel >= AVX) 3584 .Case("avx2", SSELevel >= AVX2) 3585 .Case("avx512f", SSELevel >= AVX512F) 3586 .Case("avx512cd", HasAVX512CD) 3587 .Case("avx512er", HasAVX512ER) 3588 .Case("avx512pf", HasAVX512PF) 3589 .Case("avx512dq", HasAVX512DQ) 3590 .Case("avx512bw", HasAVX512BW) 3591 .Case("avx512vl", HasAVX512VL) 3592 .Case("avx512vbmi", HasAVX512VBMI) 3593 .Case("avx512ifma", HasAVX512IFMA) 3594 .Case("bmi", HasBMI) 3595 .Case("bmi2", HasBMI2) 3596 .Case("clflushopt", HasCLFLUSHOPT) 3597 .Case("clwb", HasCLWB) 3598 .Case("cx16", HasCX16) 3599 .Case("f16c", HasF16C) 3600 .Case("fma", HasFMA) 3601 .Case("fma4", XOPLevel >= FMA4) 3602 .Case("fsgsbase", HasFSGSBASE) 3603 .Case("fxsr", HasFXSR) 3604 .Case("lzcnt", HasLZCNT) 3605 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3606 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3607 .Case("mmx", MMX3DNowLevel >= MMX) 3608 .Case("movbe", HasMOVBE) 3609 .Case("mpx", HasMPX) 3610 .Case("pclmul", HasPCLMUL) 3611 .Case("pcommit", HasPCOMMIT) 3612 .Case("pku", HasPKU) 3613 .Case("popcnt", HasPOPCNT) 3614 .Case("prefetchwt1", HasPREFETCHWT1) 3615 .Case("prfchw", HasPRFCHW) 3616 .Case("rdrnd", HasRDRND) 3617 .Case("rdseed", HasRDSEED) 3618 .Case("rtm", HasRTM) 3619 .Case("sgx", HasSGX) 3620 .Case("sha", HasSHA) 3621 .Case("sse", SSELevel >= SSE1) 3622 .Case("sse2", SSELevel >= SSE2) 3623 .Case("sse3", SSELevel >= SSE3) 3624 .Case("ssse3", SSELevel >= SSSE3) 3625 .Case("sse4.1", SSELevel >= SSE41) 3626 .Case("sse4.2", SSELevel >= SSE42) 3627 .Case("sse4a", XOPLevel >= SSE4A) 3628 .Case("tbm", HasTBM) 3629 .Case("umip", HasUMIP) 3630 .Case("x86", true) 3631 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3632 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3633 .Case("xop", XOPLevel >= XOP) 3634 .Case("xsave", HasXSAVE) 3635 .Case("xsavec", HasXSAVEC) 3636 .Case("xsaves", HasXSAVES) 3637 .Case("xsaveopt", HasXSAVEOPT) 3638 .Default(false); 3639 } 3640 3641 // We can't use a generic validation scheme for the features accepted here 3642 // versus subtarget features accepted in the target attribute because the 3643 // bitfield structure that's initialized in the runtime only supports the 3644 // below currently rather than the full range of subtarget features. (See 3645 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3646 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3647 return llvm::StringSwitch<bool>(FeatureStr) 3648 .Case("cmov", true) 3649 .Case("mmx", true) 3650 .Case("popcnt", true) 3651 .Case("sse", true) 3652 .Case("sse2", true) 3653 .Case("sse3", true) 3654 .Case("sse4.1", true) 3655 .Case("sse4.2", true) 3656 .Case("avx", true) 3657 .Case("avx2", true) 3658 .Case("sse4a", true) 3659 .Case("fma4", true) 3660 .Case("xop", true) 3661 .Case("fma", true) 3662 .Case("avx512f", true) 3663 .Case("bmi", true) 3664 .Case("bmi2", true) 3665 .Default(false); 3666 } 3667 3668 bool 3669 X86TargetInfo::validateAsmConstraint(const char *&Name, 3670 TargetInfo::ConstraintInfo &Info) const { 3671 switch (*Name) { 3672 default: return false; 3673 // Constant constraints. 3674 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3675 // instructions. 3676 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3677 // x86_64 instructions. 3678 case 's': 3679 Info.setRequiresImmediate(); 3680 return true; 3681 case 'I': 3682 Info.setRequiresImmediate(0, 31); 3683 return true; 3684 case 'J': 3685 Info.setRequiresImmediate(0, 63); 3686 return true; 3687 case 'K': 3688 Info.setRequiresImmediate(-128, 127); 3689 return true; 3690 case 'L': 3691 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3692 return true; 3693 case 'M': 3694 Info.setRequiresImmediate(0, 3); 3695 return true; 3696 case 'N': 3697 Info.setRequiresImmediate(0, 255); 3698 return true; 3699 case 'O': 3700 Info.setRequiresImmediate(0, 127); 3701 return true; 3702 // Register constraints. 3703 case 'Y': // 'Y' is the first character for several 2-character constraints. 3704 // Shift the pointer to the second character of the constraint. 3705 Name++; 3706 switch (*Name) { 3707 default: 3708 return false; 3709 case '0': // First SSE register. 3710 case 't': // Any SSE register, when SSE2 is enabled. 3711 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3712 case 'm': // Any MMX register, when inter-unit moves enabled. 3713 Info.setAllowsRegister(); 3714 return true; 3715 } 3716 case 'f': // Any x87 floating point stack register. 3717 // Constraint 'f' cannot be used for output operands. 3718 if (Info.ConstraintStr[0] == '=') 3719 return false; 3720 Info.setAllowsRegister(); 3721 return true; 3722 case 'a': // eax. 3723 case 'b': // ebx. 3724 case 'c': // ecx. 3725 case 'd': // edx. 3726 case 'S': // esi. 3727 case 'D': // edi. 3728 case 'A': // edx:eax. 3729 case 't': // Top of floating point stack. 3730 case 'u': // Second from top of floating point stack. 3731 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3732 case 'y': // Any MMX register. 3733 case 'x': // Any SSE register. 3734 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3735 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3736 case 'l': // "Index" registers: any general register that can be used as an 3737 // index in a base+index memory access. 3738 Info.setAllowsRegister(); 3739 return true; 3740 // Floating point constant constraints. 3741 case 'C': // SSE floating point constant. 3742 case 'G': // x87 floating point constant. 3743 return true; 3744 } 3745 } 3746 3747 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3748 unsigned Size) const { 3749 // Strip off constraint modifiers. 3750 while (Constraint[0] == '=' || 3751 Constraint[0] == '+' || 3752 Constraint[0] == '&') 3753 Constraint = Constraint.substr(1); 3754 3755 return validateOperandSize(Constraint, Size); 3756 } 3757 3758 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3759 unsigned Size) const { 3760 return validateOperandSize(Constraint, Size); 3761 } 3762 3763 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3764 unsigned Size) const { 3765 switch (Constraint[0]) { 3766 default: break; 3767 case 'y': 3768 return Size <= 64; 3769 case 'f': 3770 case 't': 3771 case 'u': 3772 return Size <= 128; 3773 case 'x': 3774 if (SSELevel >= AVX512F) 3775 // 512-bit zmm registers can be used if target supports AVX512F. 3776 return Size <= 512U; 3777 else if (SSELevel >= AVX) 3778 // 256-bit ymm registers can be used if target supports AVX. 3779 return Size <= 256U; 3780 return Size <= 128U; 3781 case 'Y': 3782 // 'Y' is the first character for several 2-character constraints. 3783 switch (Constraint[1]) { 3784 default: break; 3785 case 'm': 3786 // 'Ym' is synonymous with 'y'. 3787 return Size <= 64; 3788 case 'i': 3789 case 't': 3790 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3791 if (SSELevel >= AVX512F) 3792 return Size <= 512U; 3793 else if (SSELevel >= AVX) 3794 return Size <= 256U; 3795 return SSELevel >= SSE2 && Size <= 128U; 3796 } 3797 3798 } 3799 3800 return true; 3801 } 3802 3803 std::string 3804 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3805 switch (*Constraint) { 3806 case 'a': return std::string("{ax}"); 3807 case 'b': return std::string("{bx}"); 3808 case 'c': return std::string("{cx}"); 3809 case 'd': return std::string("{dx}"); 3810 case 'S': return std::string("{si}"); 3811 case 'D': return std::string("{di}"); 3812 case 'p': // address 3813 return std::string("im"); 3814 case 't': // top of floating point stack. 3815 return std::string("{st}"); 3816 case 'u': // second from top of floating point stack. 3817 return std::string("{st(1)}"); // second from top of floating point stack. 3818 default: 3819 return std::string(1, *Constraint); 3820 } 3821 } 3822 3823 // X86-32 generic target 3824 class X86_32TargetInfo : public X86TargetInfo { 3825 public: 3826 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3827 : X86TargetInfo(Triple, Opts) { 3828 DoubleAlign = LongLongAlign = 32; 3829 LongDoubleWidth = 96; 3830 LongDoubleAlign = 32; 3831 SuitableAlign = 128; 3832 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 3833 SizeType = UnsignedInt; 3834 PtrDiffType = SignedInt; 3835 IntPtrType = SignedInt; 3836 RegParmMax = 3; 3837 3838 // Use fpret for all types. 3839 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3840 (1 << TargetInfo::Double) | 3841 (1 << TargetInfo::LongDouble)); 3842 3843 // x86-32 has atomics up to 8 bytes 3844 // FIXME: Check that we actually have cmpxchg8b before setting 3845 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3846 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3847 } 3848 BuiltinVaListKind getBuiltinVaListKind() const override { 3849 return TargetInfo::CharPtrBuiltinVaList; 3850 } 3851 3852 int getEHDataRegisterNumber(unsigned RegNo) const override { 3853 if (RegNo == 0) return 0; 3854 if (RegNo == 1) return 2; 3855 return -1; 3856 } 3857 bool validateOperandSize(StringRef Constraint, 3858 unsigned Size) const override { 3859 switch (Constraint[0]) { 3860 default: break; 3861 case 'R': 3862 case 'q': 3863 case 'Q': 3864 case 'a': 3865 case 'b': 3866 case 'c': 3867 case 'd': 3868 case 'S': 3869 case 'D': 3870 return Size <= 32; 3871 case 'A': 3872 return Size <= 64; 3873 } 3874 3875 return X86TargetInfo::validateOperandSize(Constraint, Size); 3876 } 3877 }; 3878 3879 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3880 public: 3881 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3882 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 3883 3884 unsigned getFloatEvalMethod() const override { 3885 unsigned Major, Minor, Micro; 3886 getTriple().getOSVersion(Major, Minor, Micro); 3887 // New NetBSD uses the default rounding mode. 3888 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3889 return X86_32TargetInfo::getFloatEvalMethod(); 3890 // NetBSD before 6.99.26 defaults to "double" rounding. 3891 return 1; 3892 } 3893 }; 3894 3895 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3896 public: 3897 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3898 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 3899 SizeType = UnsignedLong; 3900 IntPtrType = SignedLong; 3901 PtrDiffType = SignedLong; 3902 } 3903 }; 3904 3905 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3906 public: 3907 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3908 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 3909 SizeType = UnsignedLong; 3910 IntPtrType = SignedLong; 3911 PtrDiffType = SignedLong; 3912 } 3913 }; 3914 3915 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3916 public: 3917 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3918 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 3919 LongDoubleWidth = 128; 3920 LongDoubleAlign = 128; 3921 SuitableAlign = 128; 3922 MaxVectorAlign = 256; 3923 // The watchOS simulator uses the builtin bool type for Objective-C. 3924 llvm::Triple T = llvm::Triple(Triple); 3925 if (T.isWatchOS()) 3926 UseSignedCharForObjCBool = false; 3927 SizeType = UnsignedLong; 3928 IntPtrType = SignedLong; 3929 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 3930 HasAlignMac68kSupport = true; 3931 } 3932 3933 bool handleTargetFeatures(std::vector<std::string> &Features, 3934 DiagnosticsEngine &Diags) override { 3935 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 3936 Diags)) 3937 return false; 3938 // We now know the features we have: we can decide how to align vectors. 3939 MaxVectorAlign = 3940 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3941 return true; 3942 } 3943 }; 3944 3945 // x86-32 Windows target 3946 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3947 public: 3948 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3949 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 3950 WCharType = UnsignedShort; 3951 DoubleAlign = LongLongAlign = 64; 3952 bool IsWinCOFF = 3953 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3954 resetDataLayout(IsWinCOFF 3955 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3956 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 3957 } 3958 void getTargetDefines(const LangOptions &Opts, 3959 MacroBuilder &Builder) const override { 3960 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3961 } 3962 }; 3963 3964 // x86-32 Windows Visual Studio target 3965 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3966 public: 3967 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 3968 const TargetOptions &Opts) 3969 : WindowsX86_32TargetInfo(Triple, Opts) { 3970 LongDoubleWidth = LongDoubleAlign = 64; 3971 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3972 } 3973 void getTargetDefines(const LangOptions &Opts, 3974 MacroBuilder &Builder) const override { 3975 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3976 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3977 // The value of the following reflects processor type. 3978 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3979 // We lost the original triple, so we use the default. 3980 Builder.defineMacro("_M_IX86", "600"); 3981 } 3982 }; 3983 3984 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3985 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 3986 // supports __declspec natively under -fms-extensions, but we define a no-op 3987 // __declspec macro anyway for pre-processor compatibility. 3988 if (Opts.MicrosoftExt) 3989 Builder.defineMacro("__declspec", "__declspec"); 3990 else 3991 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3992 3993 if (!Opts.MicrosoftExt) { 3994 // Provide macros for all the calling convention keywords. Provide both 3995 // single and double underscore prefixed variants. These are available on 3996 // x64 as well as x86, even though they have no effect. 3997 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3998 for (const char *CC : CCs) { 3999 std::string GCCSpelling = "__attribute__((__"; 4000 GCCSpelling += CC; 4001 GCCSpelling += "__))"; 4002 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4003 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4004 } 4005 } 4006 } 4007 4008 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4009 Builder.defineMacro("__MSVCRT__"); 4010 Builder.defineMacro("__MINGW32__"); 4011 addCygMingDefines(Opts, Builder); 4012 } 4013 4014 // x86-32 MinGW target 4015 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4016 public: 4017 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4018 : WindowsX86_32TargetInfo(Triple, Opts) {} 4019 void getTargetDefines(const LangOptions &Opts, 4020 MacroBuilder &Builder) const override { 4021 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4022 DefineStd(Builder, "WIN32", Opts); 4023 DefineStd(Builder, "WINNT", Opts); 4024 Builder.defineMacro("_X86_"); 4025 addMinGWDefines(Opts, Builder); 4026 } 4027 }; 4028 4029 // x86-32 Cygwin target 4030 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4031 public: 4032 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4033 : X86_32TargetInfo(Triple, Opts) { 4034 WCharType = UnsignedShort; 4035 DoubleAlign = LongLongAlign = 64; 4036 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4037 } 4038 void getTargetDefines(const LangOptions &Opts, 4039 MacroBuilder &Builder) const override { 4040 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4041 Builder.defineMacro("_X86_"); 4042 Builder.defineMacro("__CYGWIN__"); 4043 Builder.defineMacro("__CYGWIN32__"); 4044 addCygMingDefines(Opts, Builder); 4045 DefineStd(Builder, "unix", Opts); 4046 if (Opts.CPlusPlus) 4047 Builder.defineMacro("_GNU_SOURCE"); 4048 } 4049 }; 4050 4051 // x86-32 Haiku target 4052 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 4053 public: 4054 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4055 : X86_32TargetInfo(Triple, Opts) { 4056 SizeType = UnsignedLong; 4057 IntPtrType = SignedLong; 4058 PtrDiffType = SignedLong; 4059 ProcessIDType = SignedLong; 4060 this->TLSSupported = false; 4061 } 4062 void getTargetDefines(const LangOptions &Opts, 4063 MacroBuilder &Builder) const override { 4064 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4065 Builder.defineMacro("__INTEL__"); 4066 Builder.defineMacro("__HAIKU__"); 4067 } 4068 }; 4069 4070 // X86-32 MCU target 4071 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4072 public: 4073 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4074 : X86_32TargetInfo(Triple, Opts) { 4075 LongDoubleWidth = 64; 4076 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4077 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4078 WIntType = UnsignedInt; 4079 } 4080 4081 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4082 // On MCU we support only C calling convention. 4083 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4084 } 4085 4086 void getTargetDefines(const LangOptions &Opts, 4087 MacroBuilder &Builder) const override { 4088 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4089 Builder.defineMacro("__iamcu"); 4090 Builder.defineMacro("__iamcu__"); 4091 } 4092 4093 bool allowsLargerPreferedTypeAlignment() const override { 4094 return false; 4095 } 4096 }; 4097 4098 // RTEMS Target 4099 template<typename Target> 4100 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4101 protected: 4102 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4103 MacroBuilder &Builder) const override { 4104 // RTEMS defines; list based off of gcc output 4105 4106 Builder.defineMacro("__rtems__"); 4107 Builder.defineMacro("__ELF__"); 4108 } 4109 4110 public: 4111 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4112 : OSTargetInfo<Target>(Triple, Opts) { 4113 switch (Triple.getArch()) { 4114 default: 4115 case llvm::Triple::x86: 4116 // this->MCountName = ".mcount"; 4117 break; 4118 case llvm::Triple::mips: 4119 case llvm::Triple::mipsel: 4120 case llvm::Triple::ppc: 4121 case llvm::Triple::ppc64: 4122 case llvm::Triple::ppc64le: 4123 // this->MCountName = "_mcount"; 4124 break; 4125 case llvm::Triple::arm: 4126 // this->MCountName = "__mcount"; 4127 break; 4128 } 4129 } 4130 }; 4131 4132 // x86-32 RTEMS target 4133 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4134 public: 4135 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4136 : X86_32TargetInfo(Triple, Opts) { 4137 SizeType = UnsignedLong; 4138 IntPtrType = SignedLong; 4139 PtrDiffType = SignedLong; 4140 } 4141 void getTargetDefines(const LangOptions &Opts, 4142 MacroBuilder &Builder) const override { 4143 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4144 Builder.defineMacro("__INTEL__"); 4145 Builder.defineMacro("__rtems__"); 4146 } 4147 }; 4148 4149 // x86-64 generic target 4150 class X86_64TargetInfo : public X86TargetInfo { 4151 public: 4152 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4153 : X86TargetInfo(Triple, Opts) { 4154 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4155 bool IsWinCOFF = 4156 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4157 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4158 LongDoubleWidth = 128; 4159 LongDoubleAlign = 128; 4160 LargeArrayMinWidth = 128; 4161 LargeArrayAlign = 128; 4162 SuitableAlign = 128; 4163 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4164 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4165 IntPtrType = IsX32 ? SignedInt : SignedLong; 4166 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4167 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4168 RegParmMax = 6; 4169 4170 // Pointers are 32-bit in x32. 4171 resetDataLayout(IsX32 4172 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4173 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4174 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4175 4176 // Use fpret only for long double. 4177 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4178 4179 // Use fp2ret for _Complex long double. 4180 ComplexLongDoubleUsesFP2Ret = true; 4181 4182 // Make __builtin_ms_va_list available. 4183 HasBuiltinMSVaList = true; 4184 4185 // x86-64 has atomics up to 16 bytes. 4186 MaxAtomicPromoteWidth = 128; 4187 MaxAtomicInlineWidth = 128; 4188 } 4189 BuiltinVaListKind getBuiltinVaListKind() const override { 4190 return TargetInfo::X86_64ABIBuiltinVaList; 4191 } 4192 4193 int getEHDataRegisterNumber(unsigned RegNo) const override { 4194 if (RegNo == 0) return 0; 4195 if (RegNo == 1) return 1; 4196 return -1; 4197 } 4198 4199 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4200 switch (CC) { 4201 case CC_C: 4202 case CC_Swift: 4203 case CC_X86VectorCall: 4204 case CC_IntelOclBicc: 4205 case CC_X86_64Win64: 4206 case CC_PreserveMost: 4207 case CC_PreserveAll: 4208 return CCCR_OK; 4209 default: 4210 return CCCR_Warning; 4211 } 4212 } 4213 4214 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4215 return CC_C; 4216 } 4217 4218 // for x32 we need it here explicitly 4219 bool hasInt128Type() const override { return true; } 4220 unsigned getUnwindWordWidth() const override { return 64; } 4221 unsigned getRegisterWidth() const override { return 64; } 4222 4223 bool validateGlobalRegisterVariable(StringRef RegName, 4224 unsigned RegSize, 4225 bool &HasSizeMismatch) const override { 4226 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4227 // handle. 4228 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4229 // Check that the register size is 64-bit. 4230 HasSizeMismatch = RegSize != 64; 4231 return true; 4232 } 4233 4234 // Check if the register is a 32-bit register the backend can handle. 4235 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4236 HasSizeMismatch); 4237 } 4238 }; 4239 4240 // x86-64 Windows target 4241 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4242 public: 4243 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4244 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4245 WCharType = UnsignedShort; 4246 LongWidth = LongAlign = 32; 4247 DoubleAlign = LongLongAlign = 64; 4248 IntMaxType = SignedLongLong; 4249 Int64Type = SignedLongLong; 4250 SizeType = UnsignedLongLong; 4251 PtrDiffType = SignedLongLong; 4252 IntPtrType = SignedLongLong; 4253 } 4254 4255 void getTargetDefines(const LangOptions &Opts, 4256 MacroBuilder &Builder) const override { 4257 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4258 Builder.defineMacro("_WIN64"); 4259 } 4260 4261 BuiltinVaListKind getBuiltinVaListKind() const override { 4262 return TargetInfo::CharPtrBuiltinVaList; 4263 } 4264 4265 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4266 switch (CC) { 4267 case CC_X86StdCall: 4268 case CC_X86ThisCall: 4269 case CC_X86FastCall: 4270 return CCCR_Ignore; 4271 case CC_C: 4272 case CC_X86VectorCall: 4273 case CC_IntelOclBicc: 4274 case CC_X86_64SysV: 4275 return CCCR_OK; 4276 default: 4277 return CCCR_Warning; 4278 } 4279 } 4280 }; 4281 4282 // x86-64 Windows Visual Studio target 4283 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4284 public: 4285 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4286 const TargetOptions &Opts) 4287 : WindowsX86_64TargetInfo(Triple, Opts) { 4288 LongDoubleWidth = LongDoubleAlign = 64; 4289 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4290 } 4291 void getTargetDefines(const LangOptions &Opts, 4292 MacroBuilder &Builder) const override { 4293 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4294 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4295 Builder.defineMacro("_M_X64", "100"); 4296 Builder.defineMacro("_M_AMD64", "100"); 4297 } 4298 }; 4299 4300 // x86-64 MinGW target 4301 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4302 public: 4303 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4304 : WindowsX86_64TargetInfo(Triple, Opts) { 4305 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4306 // with x86 FP ops. Weird. 4307 LongDoubleWidth = LongDoubleAlign = 128; 4308 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4309 } 4310 4311 void getTargetDefines(const LangOptions &Opts, 4312 MacroBuilder &Builder) const override { 4313 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4314 DefineStd(Builder, "WIN64", Opts); 4315 Builder.defineMacro("__MINGW64__"); 4316 addMinGWDefines(Opts, Builder); 4317 4318 // GCC defines this macro when it is using __gxx_personality_seh0. 4319 if (!Opts.SjLjExceptions) 4320 Builder.defineMacro("__SEH__"); 4321 } 4322 }; 4323 4324 // x86-64 Cygwin target 4325 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4326 public: 4327 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4328 : X86_64TargetInfo(Triple, Opts) { 4329 TLSSupported = false; 4330 WCharType = UnsignedShort; 4331 } 4332 void getTargetDefines(const LangOptions &Opts, 4333 MacroBuilder &Builder) const override { 4334 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4335 Builder.defineMacro("__x86_64__"); 4336 Builder.defineMacro("__CYGWIN__"); 4337 Builder.defineMacro("__CYGWIN64__"); 4338 addCygMingDefines(Opts, Builder); 4339 DefineStd(Builder, "unix", Opts); 4340 if (Opts.CPlusPlus) 4341 Builder.defineMacro("_GNU_SOURCE"); 4342 4343 // GCC defines this macro when it is using __gxx_personality_seh0. 4344 if (!Opts.SjLjExceptions) 4345 Builder.defineMacro("__SEH__"); 4346 } 4347 }; 4348 4349 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4350 public: 4351 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4352 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4353 Int64Type = SignedLongLong; 4354 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4355 llvm::Triple T = llvm::Triple(Triple); 4356 if (T.isiOS()) 4357 UseSignedCharForObjCBool = false; 4358 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4359 } 4360 4361 bool handleTargetFeatures(std::vector<std::string> &Features, 4362 DiagnosticsEngine &Diags) override { 4363 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4364 Diags)) 4365 return false; 4366 // We now know the features we have: we can decide how to align vectors. 4367 MaxVectorAlign = 4368 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4369 return true; 4370 } 4371 }; 4372 4373 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4374 public: 4375 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4376 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4377 IntMaxType = SignedLongLong; 4378 Int64Type = SignedLongLong; 4379 } 4380 }; 4381 4382 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4383 public: 4384 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4385 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4386 IntMaxType = SignedLongLong; 4387 Int64Type = SignedLongLong; 4388 } 4389 }; 4390 4391 class ARMTargetInfo : public TargetInfo { 4392 // Possible FPU choices. 4393 enum FPUMode { 4394 VFP2FPU = (1 << 0), 4395 VFP3FPU = (1 << 1), 4396 VFP4FPU = (1 << 2), 4397 NeonFPU = (1 << 3), 4398 FPARMV8 = (1 << 4) 4399 }; 4400 4401 // Possible HWDiv features. 4402 enum HWDivMode { 4403 HWDivThumb = (1 << 0), 4404 HWDivARM = (1 << 1) 4405 }; 4406 4407 static bool FPUModeIsVFP(FPUMode Mode) { 4408 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4409 } 4410 4411 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4412 static const char * const GCCRegNames[]; 4413 4414 std::string ABI, CPU; 4415 4416 StringRef CPUProfile; 4417 StringRef CPUAttr; 4418 4419 enum { 4420 FP_Default, 4421 FP_VFP, 4422 FP_Neon 4423 } FPMath; 4424 4425 unsigned ArchISA; 4426 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4427 unsigned ArchProfile; 4428 unsigned ArchVersion; 4429 4430 unsigned FPU : 5; 4431 4432 unsigned IsAAPCS : 1; 4433 unsigned HWDiv : 2; 4434 4435 // Initialized via features. 4436 unsigned SoftFloat : 1; 4437 unsigned SoftFloatABI : 1; 4438 4439 unsigned CRC : 1; 4440 unsigned Crypto : 1; 4441 unsigned DSP : 1; 4442 unsigned Unaligned : 1; 4443 4444 enum { 4445 LDREX_B = (1 << 0), /// byte (8-bit) 4446 LDREX_H = (1 << 1), /// half (16-bit) 4447 LDREX_W = (1 << 2), /// word (32-bit) 4448 LDREX_D = (1 << 3), /// double (64-bit) 4449 }; 4450 4451 uint32_t LDREX; 4452 4453 // ACLE 6.5.1 Hardware floating point 4454 enum { 4455 HW_FP_HP = (1 << 1), /// half (16-bit) 4456 HW_FP_SP = (1 << 2), /// single (32-bit) 4457 HW_FP_DP = (1 << 3), /// double (64-bit) 4458 }; 4459 uint32_t HW_FP; 4460 4461 static const Builtin::Info BuiltinInfo[]; 4462 4463 void setABIAAPCS() { 4464 IsAAPCS = true; 4465 4466 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4467 const llvm::Triple &T = getTriple(); 4468 4469 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4470 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4471 T.getOS() == llvm::Triple::Bitrig) 4472 SizeType = UnsignedLong; 4473 else 4474 SizeType = UnsignedInt; 4475 4476 switch (T.getOS()) { 4477 case llvm::Triple::NetBSD: 4478 WCharType = SignedInt; 4479 break; 4480 case llvm::Triple::Win32: 4481 WCharType = UnsignedShort; 4482 break; 4483 case llvm::Triple::Linux: 4484 default: 4485 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4486 WCharType = UnsignedInt; 4487 break; 4488 } 4489 4490 UseBitFieldTypeAlignment = true; 4491 4492 ZeroLengthBitfieldBoundary = 0; 4493 4494 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4495 // so set preferred for small types to 32. 4496 if (T.isOSBinFormatMachO()) { 4497 resetDataLayout(BigEndian 4498 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4499 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4500 } else if (T.isOSWindows()) { 4501 assert(!BigEndian && "Windows on ARM does not support big endian"); 4502 resetDataLayout("e" 4503 "-m:w" 4504 "-p:32:32" 4505 "-i64:64" 4506 "-v128:64:128" 4507 "-a:0:32" 4508 "-n32" 4509 "-S64"); 4510 } else if (T.isOSNaCl()) { 4511 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4512 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4513 } else { 4514 resetDataLayout(BigEndian 4515 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4516 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4517 } 4518 4519 // FIXME: Enumerated types are variable width in straight AAPCS. 4520 } 4521 4522 void setABIAPCS(bool IsAAPCS16) { 4523 const llvm::Triple &T = getTriple(); 4524 4525 IsAAPCS = false; 4526 4527 if (IsAAPCS16) 4528 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4529 else 4530 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4531 4532 // size_t is unsigned int on FreeBSD. 4533 if (T.getOS() == llvm::Triple::FreeBSD) 4534 SizeType = UnsignedInt; 4535 else 4536 SizeType = UnsignedLong; 4537 4538 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4539 WCharType = SignedInt; 4540 4541 // Do not respect the alignment of bit-field types when laying out 4542 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4543 UseBitFieldTypeAlignment = false; 4544 4545 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4546 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4547 /// gcc. 4548 ZeroLengthBitfieldBoundary = 32; 4549 4550 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4551 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4552 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4553 } else if (T.isOSBinFormatMachO()) 4554 resetDataLayout( 4555 BigEndian 4556 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4557 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4558 else 4559 resetDataLayout( 4560 BigEndian 4561 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4562 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4563 4564 // FIXME: Override "preferred align" for double and long long. 4565 } 4566 4567 void setArchInfo() { 4568 StringRef ArchName = getTriple().getArchName(); 4569 4570 ArchISA = llvm::ARM::parseArchISA(ArchName); 4571 CPU = llvm::ARM::getDefaultCPU(ArchName); 4572 unsigned AK = llvm::ARM::parseArch(ArchName); 4573 if (AK != llvm::ARM::AK_INVALID) 4574 ArchKind = AK; 4575 setArchInfo(ArchKind); 4576 } 4577 4578 void setArchInfo(unsigned Kind) { 4579 StringRef SubArch; 4580 4581 // cache TargetParser info 4582 ArchKind = Kind; 4583 SubArch = llvm::ARM::getSubArch(ArchKind); 4584 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4585 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4586 4587 // cache CPU related strings 4588 CPUAttr = getCPUAttr(); 4589 CPUProfile = getCPUProfile(); 4590 } 4591 4592 void setAtomic() { 4593 // when triple does not specify a sub arch, 4594 // then we are not using inline atomics 4595 bool ShouldUseInlineAtomic = 4596 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4597 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4598 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4599 if (ArchProfile == llvm::ARM::PK_M) { 4600 MaxAtomicPromoteWidth = 32; 4601 if (ShouldUseInlineAtomic) 4602 MaxAtomicInlineWidth = 32; 4603 } 4604 else { 4605 MaxAtomicPromoteWidth = 64; 4606 if (ShouldUseInlineAtomic) 4607 MaxAtomicInlineWidth = 64; 4608 } 4609 } 4610 4611 bool isThumb() const { 4612 return (ArchISA == llvm::ARM::IK_THUMB); 4613 } 4614 4615 bool supportsThumb() const { 4616 return CPUAttr.count('T') || ArchVersion >= 6; 4617 } 4618 4619 bool supportsThumb2() const { 4620 return CPUAttr.equals("6T2") || 4621 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 4622 } 4623 4624 StringRef getCPUAttr() const { 4625 // For most sub-arches, the build attribute CPU name is enough. 4626 // For Cortex variants, it's slightly different. 4627 switch(ArchKind) { 4628 default: 4629 return llvm::ARM::getCPUAttr(ArchKind); 4630 case llvm::ARM::AK_ARMV6M: 4631 return "6M"; 4632 case llvm::ARM::AK_ARMV7S: 4633 return "7S"; 4634 case llvm::ARM::AK_ARMV7A: 4635 return "7A"; 4636 case llvm::ARM::AK_ARMV7R: 4637 return "7R"; 4638 case llvm::ARM::AK_ARMV7M: 4639 return "7M"; 4640 case llvm::ARM::AK_ARMV7EM: 4641 return "7EM"; 4642 case llvm::ARM::AK_ARMV8A: 4643 return "8A"; 4644 case llvm::ARM::AK_ARMV8_1A: 4645 return "8_1A"; 4646 case llvm::ARM::AK_ARMV8_2A: 4647 return "8_2A"; 4648 case llvm::ARM::AK_ARMV8MBaseline: 4649 return "8M_BASE"; 4650 case llvm::ARM::AK_ARMV8MMainline: 4651 return "8M_MAIN"; 4652 } 4653 } 4654 4655 StringRef getCPUProfile() const { 4656 switch(ArchProfile) { 4657 case llvm::ARM::PK_A: 4658 return "A"; 4659 case llvm::ARM::PK_R: 4660 return "R"; 4661 case llvm::ARM::PK_M: 4662 return "M"; 4663 default: 4664 return ""; 4665 } 4666 } 4667 4668 public: 4669 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 4670 bool IsBigEndian) 4671 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 4672 HW_FP(0) { 4673 BigEndian = IsBigEndian; 4674 4675 switch (getTriple().getOS()) { 4676 case llvm::Triple::NetBSD: 4677 PtrDiffType = SignedLong; 4678 break; 4679 default: 4680 PtrDiffType = SignedInt; 4681 break; 4682 } 4683 4684 // Cache arch related info. 4685 setArchInfo(); 4686 4687 // {} in inline assembly are neon specifiers, not assembly variant 4688 // specifiers. 4689 NoAsmVariants = true; 4690 4691 // FIXME: This duplicates code from the driver that sets the -target-abi 4692 // option - this code is used if -target-abi isn't passed and should 4693 // be unified in some way. 4694 if (Triple.isOSBinFormatMachO()) { 4695 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4696 // the frontend matches that. 4697 if (Triple.getEnvironment() == llvm::Triple::EABI || 4698 Triple.getOS() == llvm::Triple::UnknownOS || 4699 StringRef(CPU).startswith("cortex-m")) { 4700 setABI("aapcs"); 4701 } else if (Triple.isWatchABI()) { 4702 setABI("aapcs16"); 4703 } else { 4704 setABI("apcs-gnu"); 4705 } 4706 } else if (Triple.isOSWindows()) { 4707 // FIXME: this is invalid for WindowsCE 4708 setABI("aapcs"); 4709 } else { 4710 // Select the default based on the platform. 4711 switch (Triple.getEnvironment()) { 4712 case llvm::Triple::Android: 4713 case llvm::Triple::GNUEABI: 4714 case llvm::Triple::GNUEABIHF: 4715 setABI("aapcs-linux"); 4716 break; 4717 case llvm::Triple::EABIHF: 4718 case llvm::Triple::EABI: 4719 setABI("aapcs"); 4720 break; 4721 case llvm::Triple::GNU: 4722 setABI("apcs-gnu"); 4723 break; 4724 default: 4725 if (Triple.getOS() == llvm::Triple::NetBSD) 4726 setABI("apcs-gnu"); 4727 else 4728 setABI("aapcs"); 4729 break; 4730 } 4731 } 4732 4733 // ARM targets default to using the ARM C++ ABI. 4734 TheCXXABI.set(TargetCXXABI::GenericARM); 4735 4736 // ARM has atomics up to 8 bytes 4737 setAtomic(); 4738 4739 // Do force alignment of members that follow zero length bitfields. If 4740 // the alignment of the zero-length bitfield is greater than the member 4741 // that follows it, `bar', `bar' will be aligned as the type of the 4742 // zero length bitfield. 4743 UseZeroLengthBitfieldAlignment = true; 4744 4745 if (Triple.getOS() == llvm::Triple::Linux || 4746 Triple.getOS() == llvm::Triple::UnknownOS) 4747 this->MCountName = 4748 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 4749 } 4750 4751 StringRef getABI() const override { return ABI; } 4752 4753 bool setABI(const std::string &Name) override { 4754 ABI = Name; 4755 4756 // The defaults (above) are for AAPCS, check if we need to change them. 4757 // 4758 // FIXME: We need support for -meabi... we could just mangle it into the 4759 // name. 4760 if (Name == "apcs-gnu" || Name == "aapcs16") { 4761 setABIAPCS(Name == "aapcs16"); 4762 return true; 4763 } 4764 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4765 setABIAAPCS(); 4766 return true; 4767 } 4768 return false; 4769 } 4770 4771 // FIXME: This should be based on Arch attributes, not CPU names. 4772 bool 4773 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4774 StringRef CPU, 4775 const std::vector<std::string> &FeaturesVec) const override { 4776 4777 std::vector<const char*> TargetFeatures; 4778 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4779 4780 // get default FPU features 4781 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4782 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4783 4784 // get default Extension features 4785 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 4786 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4787 4788 for (const char *Feature : TargetFeatures) 4789 if (Feature[0] == '+') 4790 Features[Feature+1] = true; 4791 4792 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4793 } 4794 4795 bool handleTargetFeatures(std::vector<std::string> &Features, 4796 DiagnosticsEngine &Diags) override { 4797 FPU = 0; 4798 CRC = 0; 4799 Crypto = 0; 4800 DSP = 0; 4801 Unaligned = 1; 4802 SoftFloat = SoftFloatABI = false; 4803 HWDiv = 0; 4804 4805 // This does not diagnose illegal cases like having both 4806 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4807 uint32_t HW_FP_remove = 0; 4808 for (const auto &Feature : Features) { 4809 if (Feature == "+soft-float") { 4810 SoftFloat = true; 4811 } else if (Feature == "+soft-float-abi") { 4812 SoftFloatABI = true; 4813 } else if (Feature == "+vfp2") { 4814 FPU |= VFP2FPU; 4815 HW_FP |= HW_FP_SP | HW_FP_DP; 4816 } else if (Feature == "+vfp3") { 4817 FPU |= VFP3FPU; 4818 HW_FP |= HW_FP_SP | HW_FP_DP; 4819 } else if (Feature == "+vfp4") { 4820 FPU |= VFP4FPU; 4821 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4822 } else if (Feature == "+fp-armv8") { 4823 FPU |= FPARMV8; 4824 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4825 } else if (Feature == "+neon") { 4826 FPU |= NeonFPU; 4827 HW_FP |= HW_FP_SP | HW_FP_DP; 4828 } else if (Feature == "+hwdiv") { 4829 HWDiv |= HWDivThumb; 4830 } else if (Feature == "+hwdiv-arm") { 4831 HWDiv |= HWDivARM; 4832 } else if (Feature == "+crc") { 4833 CRC = 1; 4834 } else if (Feature == "+crypto") { 4835 Crypto = 1; 4836 } else if (Feature == "+dsp") { 4837 DSP = 1; 4838 } else if (Feature == "+fp-only-sp") { 4839 HW_FP_remove |= HW_FP_DP; 4840 } else if (Feature == "+strict-align") { 4841 Unaligned = 0; 4842 } else if (Feature == "+fp16") { 4843 HW_FP |= HW_FP_HP; 4844 } 4845 } 4846 HW_FP &= ~HW_FP_remove; 4847 4848 switch (ArchVersion) { 4849 case 6: 4850 if (ArchProfile == llvm::ARM::PK_M) 4851 LDREX = 0; 4852 else if (ArchKind == llvm::ARM::AK_ARMV6K) 4853 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4854 else 4855 LDREX = LDREX_W; 4856 break; 4857 case 7: 4858 if (ArchProfile == llvm::ARM::PK_M) 4859 LDREX = LDREX_W | LDREX_H | LDREX_B ; 4860 else 4861 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4862 break; 4863 case 8: 4864 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4865 } 4866 4867 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4868 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4869 return false; 4870 } 4871 4872 if (FPMath == FP_Neon) 4873 Features.push_back("+neonfp"); 4874 else if (FPMath == FP_VFP) 4875 Features.push_back("-neonfp"); 4876 4877 // Remove front-end specific options which the backend handles differently. 4878 auto Feature = 4879 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4880 if (Feature != Features.end()) 4881 Features.erase(Feature); 4882 4883 return true; 4884 } 4885 4886 bool hasFeature(StringRef Feature) const override { 4887 return llvm::StringSwitch<bool>(Feature) 4888 .Case("arm", true) 4889 .Case("aarch32", true) 4890 .Case("softfloat", SoftFloat) 4891 .Case("thumb", isThumb()) 4892 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4893 .Case("hwdiv", HWDiv & HWDivThumb) 4894 .Case("hwdiv-arm", HWDiv & HWDivARM) 4895 .Default(false); 4896 } 4897 4898 bool setCPU(const std::string &Name) override { 4899 if (Name != "generic") 4900 setArchInfo(llvm::ARM::parseCPUArch(Name)); 4901 4902 if (ArchKind == llvm::ARM::AK_INVALID) 4903 return false; 4904 setAtomic(); 4905 CPU = Name; 4906 return true; 4907 } 4908 4909 bool setFPMath(StringRef Name) override; 4910 4911 void getTargetDefines(const LangOptions &Opts, 4912 MacroBuilder &Builder) const override { 4913 // Target identification. 4914 Builder.defineMacro("__arm"); 4915 Builder.defineMacro("__arm__"); 4916 // For bare-metal none-eabi. 4917 if (getTriple().getOS() == llvm::Triple::UnknownOS && 4918 getTriple().getEnvironment() == llvm::Triple::EABI) 4919 Builder.defineMacro("__ELF__"); 4920 4921 // Target properties. 4922 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4923 4924 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 4925 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 4926 if (getTriple().isWatchABI()) 4927 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 4928 4929 if (!CPUAttr.empty()) 4930 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 4931 4932 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4933 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4934 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 4935 4936 if (ArchVersion >= 8) { 4937 // ACLE 6.5.7 Crypto Extension 4938 if (Crypto) 4939 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 4940 // ACLE 6.5.8 CRC32 Extension 4941 if (CRC) 4942 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 4943 // ACLE 6.5.10 Numeric Maximum and Minimum 4944 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 4945 // ACLE 6.5.9 Directed Rounding 4946 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 4947 } 4948 4949 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4950 // is not defined for the M-profile. 4951 // NOTE that the default profile is assumed to be 'A' 4952 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 4953 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4954 4955 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 4956 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 4957 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 4958 // v7 and v8 architectures excluding v8-M Baseline. 4959 if (supportsThumb2()) 4960 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4961 else if (supportsThumb()) 4962 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4963 4964 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4965 // instruction set such as ARM or Thumb. 4966 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4967 4968 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4969 4970 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4971 if (!CPUProfile.empty()) 4972 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4973 4974 // ACLE 6.4.3 Unaligned access supported in hardware 4975 if (Unaligned) 4976 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 4977 4978 // ACLE 6.4.4 LDREX/STREX 4979 if (LDREX) 4980 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 4981 4982 // ACLE 6.4.5 CLZ 4983 if (ArchVersion == 5 || 4984 (ArchVersion == 6 && CPUProfile != "M") || 4985 ArchVersion > 6) 4986 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 4987 4988 // ACLE 6.5.1 Hardware Floating Point 4989 if (HW_FP) 4990 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4991 4992 // ACLE predefines. 4993 Builder.defineMacro("__ARM_ACLE", "200"); 4994 4995 // FP16 support (we currently only support IEEE format). 4996 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 4997 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 4998 4999 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5000 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5001 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5002 5003 // Subtarget options. 5004 5005 // FIXME: It's more complicated than this and we don't really support 5006 // interworking. 5007 // Windows on ARM does not "support" interworking 5008 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5009 Builder.defineMacro("__THUMB_INTERWORK__"); 5010 5011 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5012 // Embedded targets on Darwin follow AAPCS, but not EABI. 5013 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5014 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 5015 Builder.defineMacro("__ARM_EABI__"); 5016 Builder.defineMacro("__ARM_PCS", "1"); 5017 } 5018 5019 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5020 ABI == "aapcs16") 5021 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5022 5023 if (SoftFloat) 5024 Builder.defineMacro("__SOFTFP__"); 5025 5026 if (CPU == "xscale") 5027 Builder.defineMacro("__XSCALE__"); 5028 5029 if (isThumb()) { 5030 Builder.defineMacro("__THUMBEL__"); 5031 Builder.defineMacro("__thumb__"); 5032 if (supportsThumb2()) 5033 Builder.defineMacro("__thumb2__"); 5034 } 5035 5036 // ACLE 6.4.9 32-bit SIMD instructions 5037 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5038 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5039 5040 // ACLE 6.4.10 Hardware Integer Divide 5041 if (((HWDiv & HWDivThumb) && isThumb()) || 5042 ((HWDiv & HWDivARM) && !isThumb())) { 5043 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5044 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5045 } 5046 5047 // Note, this is always on in gcc, even though it doesn't make sense. 5048 Builder.defineMacro("__APCS_32__"); 5049 5050 if (FPUModeIsVFP((FPUMode) FPU)) { 5051 Builder.defineMacro("__VFP_FP__"); 5052 if (FPU & VFP2FPU) 5053 Builder.defineMacro("__ARM_VFPV2__"); 5054 if (FPU & VFP3FPU) 5055 Builder.defineMacro("__ARM_VFPV3__"); 5056 if (FPU & VFP4FPU) 5057 Builder.defineMacro("__ARM_VFPV4__"); 5058 } 5059 5060 // This only gets set when Neon instructions are actually available, unlike 5061 // the VFP define, hence the soft float and arch check. This is subtly 5062 // different from gcc, we follow the intent which was that it should be set 5063 // when Neon instructions are actually available. 5064 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5065 Builder.defineMacro("__ARM_NEON", "1"); 5066 Builder.defineMacro("__ARM_NEON__"); 5067 // current AArch32 NEON implementations do not support double-precision 5068 // floating-point even when it is present in VFP. 5069 Builder.defineMacro("__ARM_NEON_FP", 5070 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5071 } 5072 5073 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5074 Opts.ShortWChar ? "2" : "4"); 5075 5076 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5077 Opts.ShortEnums ? "1" : "4"); 5078 5079 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5080 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5081 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5082 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5083 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5084 } 5085 5086 // ACLE 6.4.7 DSP instructions 5087 if (DSP) { 5088 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5089 } 5090 5091 // ACLE 6.4.8 Saturation instructions 5092 bool SAT = false; 5093 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5094 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5095 SAT = true; 5096 } 5097 5098 // ACLE 6.4.6 Q (saturation) flag 5099 if (DSP || SAT) 5100 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5101 5102 if (Opts.UnsafeFPMath) 5103 Builder.defineMacro("__ARM_FP_FAST", "1"); 5104 5105 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5106 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5107 } 5108 5109 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5110 return llvm::makeArrayRef(BuiltinInfo, 5111 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5112 } 5113 bool isCLZForZeroUndef() const override { return false; } 5114 BuiltinVaListKind getBuiltinVaListKind() const override { 5115 return IsAAPCS 5116 ? AAPCSABIBuiltinVaList 5117 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5118 : TargetInfo::VoidPtrBuiltinVaList); 5119 } 5120 ArrayRef<const char *> getGCCRegNames() const override; 5121 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5122 bool validateAsmConstraint(const char *&Name, 5123 TargetInfo::ConstraintInfo &Info) const override { 5124 switch (*Name) { 5125 default: break; 5126 case 'l': // r0-r7 5127 case 'h': // r8-r15 5128 case 't': // VFP Floating point register single precision 5129 case 'w': // VFP Floating point register double precision 5130 Info.setAllowsRegister(); 5131 return true; 5132 case 'I': 5133 case 'J': 5134 case 'K': 5135 case 'L': 5136 case 'M': 5137 // FIXME 5138 return true; 5139 case 'Q': // A memory address that is a single base register. 5140 Info.setAllowsMemory(); 5141 return true; 5142 case 'U': // a memory reference... 5143 switch (Name[1]) { 5144 case 'q': // ...ARMV4 ldrsb 5145 case 'v': // ...VFP load/store (reg+constant offset) 5146 case 'y': // ...iWMMXt load/store 5147 case 't': // address valid for load/store opaque types wider 5148 // than 128-bits 5149 case 'n': // valid address for Neon doubleword vector load/store 5150 case 'm': // valid address for Neon element and structure load/store 5151 case 's': // valid address for non-offset loads/stores of quad-word 5152 // values in four ARM registers 5153 Info.setAllowsMemory(); 5154 Name++; 5155 return true; 5156 } 5157 } 5158 return false; 5159 } 5160 std::string convertConstraint(const char *&Constraint) const override { 5161 std::string R; 5162 switch (*Constraint) { 5163 case 'U': // Two-character constraint; add "^" hint for later parsing. 5164 R = std::string("^") + std::string(Constraint, 2); 5165 Constraint++; 5166 break; 5167 case 'p': // 'p' should be translated to 'r' by default. 5168 R = std::string("r"); 5169 break; 5170 default: 5171 return std::string(1, *Constraint); 5172 } 5173 return R; 5174 } 5175 bool 5176 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5177 std::string &SuggestedModifier) const override { 5178 bool isOutput = (Constraint[0] == '='); 5179 bool isInOut = (Constraint[0] == '+'); 5180 5181 // Strip off constraint modifiers. 5182 while (Constraint[0] == '=' || 5183 Constraint[0] == '+' || 5184 Constraint[0] == '&') 5185 Constraint = Constraint.substr(1); 5186 5187 switch (Constraint[0]) { 5188 default: break; 5189 case 'r': { 5190 switch (Modifier) { 5191 default: 5192 return (isInOut || isOutput || Size <= 64); 5193 case 'q': 5194 // A register of size 32 cannot fit a vector type. 5195 return false; 5196 } 5197 } 5198 } 5199 5200 return true; 5201 } 5202 const char *getClobbers() const override { 5203 // FIXME: Is this really right? 5204 return ""; 5205 } 5206 5207 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5208 switch (CC) { 5209 case CC_AAPCS: 5210 case CC_AAPCS_VFP: 5211 case CC_Swift: 5212 return CCCR_OK; 5213 default: 5214 return CCCR_Warning; 5215 } 5216 } 5217 5218 int getEHDataRegisterNumber(unsigned RegNo) const override { 5219 if (RegNo == 0) return 0; 5220 if (RegNo == 1) return 1; 5221 return -1; 5222 } 5223 5224 bool hasSjLjLowering() const override { 5225 return true; 5226 } 5227 }; 5228 5229 bool ARMTargetInfo::setFPMath(StringRef Name) { 5230 if (Name == "neon") { 5231 FPMath = FP_Neon; 5232 return true; 5233 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5234 Name == "vfp4") { 5235 FPMath = FP_VFP; 5236 return true; 5237 } 5238 return false; 5239 } 5240 5241 const char * const ARMTargetInfo::GCCRegNames[] = { 5242 // Integer registers 5243 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5244 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5245 5246 // Float registers 5247 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5248 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5249 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5250 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5251 5252 // Double registers 5253 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5254 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5255 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5256 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5257 5258 // Quad registers 5259 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5260 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5261 }; 5262 5263 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5264 return llvm::makeArrayRef(GCCRegNames); 5265 } 5266 5267 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5268 { { "a1" }, "r0" }, 5269 { { "a2" }, "r1" }, 5270 { { "a3" }, "r2" }, 5271 { { "a4" }, "r3" }, 5272 { { "v1" }, "r4" }, 5273 { { "v2" }, "r5" }, 5274 { { "v3" }, "r6" }, 5275 { { "v4" }, "r7" }, 5276 { { "v5" }, "r8" }, 5277 { { "v6", "rfp" }, "r9" }, 5278 { { "sl" }, "r10" }, 5279 { { "fp" }, "r11" }, 5280 { { "ip" }, "r12" }, 5281 { { "r13" }, "sp" }, 5282 { { "r14" }, "lr" }, 5283 { { "r15" }, "pc" }, 5284 // The S, D and Q registers overlap, but aren't really aliases; we 5285 // don't want to substitute one of these for a different-sized one. 5286 }; 5287 5288 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5289 return llvm::makeArrayRef(GCCRegAliases); 5290 } 5291 5292 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5293 #define BUILTIN(ID, TYPE, ATTRS) \ 5294 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5295 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5296 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5297 #include "clang/Basic/BuiltinsNEON.def" 5298 5299 #define BUILTIN(ID, TYPE, ATTRS) \ 5300 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5301 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5302 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5303 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5304 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5305 #include "clang/Basic/BuiltinsARM.def" 5306 }; 5307 5308 class ARMleTargetInfo : public ARMTargetInfo { 5309 public: 5310 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5311 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/false) {} 5312 void getTargetDefines(const LangOptions &Opts, 5313 MacroBuilder &Builder) const override { 5314 Builder.defineMacro("__ARMEL__"); 5315 ARMTargetInfo::getTargetDefines(Opts, Builder); 5316 } 5317 }; 5318 5319 class ARMbeTargetInfo : public ARMTargetInfo { 5320 public: 5321 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5322 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/true) {} 5323 void getTargetDefines(const LangOptions &Opts, 5324 MacroBuilder &Builder) const override { 5325 Builder.defineMacro("__ARMEB__"); 5326 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5327 ARMTargetInfo::getTargetDefines(Opts, Builder); 5328 } 5329 }; 5330 5331 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5332 const llvm::Triple Triple; 5333 public: 5334 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5335 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5336 WCharType = UnsignedShort; 5337 SizeType = UnsignedInt; 5338 } 5339 void getVisualStudioDefines(const LangOptions &Opts, 5340 MacroBuilder &Builder) const { 5341 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5342 5343 // FIXME: this is invalid for WindowsCE 5344 Builder.defineMacro("_M_ARM_NT", "1"); 5345 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5346 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5347 5348 assert((Triple.getArch() == llvm::Triple::arm || 5349 Triple.getArch() == llvm::Triple::thumb) && 5350 "invalid architecture for Windows ARM target info"); 5351 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5352 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5353 5354 // TODO map the complete set of values 5355 // 31: VFPv3 40: VFPv4 5356 Builder.defineMacro("_M_ARM_FP", "31"); 5357 } 5358 BuiltinVaListKind getBuiltinVaListKind() const override { 5359 return TargetInfo::CharPtrBuiltinVaList; 5360 } 5361 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5362 switch (CC) { 5363 case CC_X86StdCall: 5364 case CC_X86ThisCall: 5365 case CC_X86FastCall: 5366 case CC_X86VectorCall: 5367 return CCCR_Ignore; 5368 case CC_C: 5369 return CCCR_OK; 5370 default: 5371 return CCCR_Warning; 5372 } 5373 } 5374 }; 5375 5376 // Windows ARM + Itanium C++ ABI Target 5377 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5378 public: 5379 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5380 const TargetOptions &Opts) 5381 : WindowsARMTargetInfo(Triple, Opts) { 5382 TheCXXABI.set(TargetCXXABI::GenericARM); 5383 } 5384 5385 void getTargetDefines(const LangOptions &Opts, 5386 MacroBuilder &Builder) const override { 5387 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5388 5389 if (Opts.MSVCCompat) 5390 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5391 } 5392 }; 5393 5394 // Windows ARM, MS (C++) ABI 5395 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5396 public: 5397 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5398 const TargetOptions &Opts) 5399 : WindowsARMTargetInfo(Triple, Opts) { 5400 TheCXXABI.set(TargetCXXABI::Microsoft); 5401 } 5402 5403 void getTargetDefines(const LangOptions &Opts, 5404 MacroBuilder &Builder) const override { 5405 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5406 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5407 } 5408 }; 5409 5410 // ARM MinGW target 5411 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5412 public: 5413 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5414 : WindowsARMTargetInfo(Triple, Opts) { 5415 TheCXXABI.set(TargetCXXABI::GenericARM); 5416 } 5417 5418 void getTargetDefines(const LangOptions &Opts, 5419 MacroBuilder &Builder) const override { 5420 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5421 DefineStd(Builder, "WIN32", Opts); 5422 DefineStd(Builder, "WINNT", Opts); 5423 Builder.defineMacro("_ARM_"); 5424 addMinGWDefines(Opts, Builder); 5425 } 5426 }; 5427 5428 // ARM Cygwin target 5429 class CygwinARMTargetInfo : public ARMleTargetInfo { 5430 public: 5431 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5432 : ARMleTargetInfo(Triple, Opts) { 5433 TLSSupported = false; 5434 WCharType = UnsignedShort; 5435 DoubleAlign = LongLongAlign = 64; 5436 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5437 } 5438 void getTargetDefines(const LangOptions &Opts, 5439 MacroBuilder &Builder) const override { 5440 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5441 Builder.defineMacro("_ARM_"); 5442 Builder.defineMacro("__CYGWIN__"); 5443 Builder.defineMacro("__CYGWIN32__"); 5444 DefineStd(Builder, "unix", Opts); 5445 if (Opts.CPlusPlus) 5446 Builder.defineMacro("_GNU_SOURCE"); 5447 } 5448 }; 5449 5450 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 5451 protected: 5452 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5453 MacroBuilder &Builder) const override { 5454 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5455 } 5456 5457 public: 5458 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5459 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 5460 HasAlignMac68kSupport = true; 5461 // iOS always has 64-bit atomic instructions. 5462 // FIXME: This should be based off of the target features in 5463 // ARMleTargetInfo. 5464 MaxAtomicInlineWidth = 64; 5465 5466 if (Triple.isWatchABI()) { 5467 // Darwin on iOS uses a variant of the ARM C++ ABI. 5468 TheCXXABI.set(TargetCXXABI::WatchOS); 5469 5470 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5471 // size_t is long, it's a bit weird for it to be int. 5472 PtrDiffType = SignedLong; 5473 5474 // BOOL should be a real boolean on the new ABI 5475 UseSignedCharForObjCBool = false; 5476 } else 5477 TheCXXABI.set(TargetCXXABI::iOS); 5478 } 5479 }; 5480 5481 class AArch64TargetInfo : public TargetInfo { 5482 virtual void setDataLayout() = 0; 5483 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5484 static const char *const GCCRegNames[]; 5485 5486 enum FPUModeEnum { 5487 FPUMode, 5488 NeonMode 5489 }; 5490 5491 unsigned FPU; 5492 unsigned CRC; 5493 unsigned Crypto; 5494 unsigned Unaligned; 5495 unsigned V8_1A; 5496 5497 static const Builtin::Info BuiltinInfo[]; 5498 5499 std::string ABI; 5500 5501 public: 5502 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5503 : TargetInfo(Triple), ABI("aapcs") { 5504 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5505 WCharType = SignedInt; 5506 5507 // NetBSD apparently prefers consistency across ARM targets to consistency 5508 // across 64-bit targets. 5509 Int64Type = SignedLongLong; 5510 IntMaxType = SignedLongLong; 5511 } else { 5512 WCharType = UnsignedInt; 5513 Int64Type = SignedLong; 5514 IntMaxType = SignedLong; 5515 } 5516 5517 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5518 MaxVectorAlign = 128; 5519 MaxAtomicInlineWidth = 128; 5520 MaxAtomicPromoteWidth = 128; 5521 5522 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5523 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5524 5525 // {} in inline assembly are neon specifiers, not assembly variant 5526 // specifiers. 5527 NoAsmVariants = true; 5528 5529 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5530 // contributes to the alignment of the containing aggregate in the same way 5531 // a plain (non bit-field) member of that type would, without exception for 5532 // zero-sized or anonymous bit-fields." 5533 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5534 UseZeroLengthBitfieldAlignment = true; 5535 5536 // AArch64 targets default to using the ARM C++ ABI. 5537 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5538 5539 if (Triple.getOS() == llvm::Triple::Linux || 5540 Triple.getOS() == llvm::Triple::UnknownOS) 5541 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 5542 } 5543 5544 StringRef getABI() const override { return ABI; } 5545 bool setABI(const std::string &Name) override { 5546 if (Name != "aapcs" && Name != "darwinpcs") 5547 return false; 5548 5549 ABI = Name; 5550 return true; 5551 } 5552 5553 bool setCPU(const std::string &Name) override { 5554 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5555 .Case("generic", true) 5556 .Cases("cortex-a53", "cortex-a57", "cortex-a72", 5557 "cortex-a35", "exynos-m1", true) 5558 .Case("cyclone", true) 5559 .Case("kryo", true) 5560 .Default(false); 5561 return CPUKnown; 5562 } 5563 5564 void getTargetDefines(const LangOptions &Opts, 5565 MacroBuilder &Builder) const override { 5566 // Target identification. 5567 Builder.defineMacro("__aarch64__"); 5568 5569 // Target properties. 5570 Builder.defineMacro("_LP64"); 5571 Builder.defineMacro("__LP64__"); 5572 5573 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5574 Builder.defineMacro("__ARM_ACLE", "200"); 5575 Builder.defineMacro("__ARM_ARCH", "8"); 5576 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5577 5578 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5579 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5580 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5581 5582 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5583 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5584 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5585 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5586 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5587 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5588 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5589 5590 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5591 5592 // 0xe implies support for half, single and double precision operations. 5593 Builder.defineMacro("__ARM_FP", "0xE"); 5594 5595 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5596 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5597 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5598 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5599 5600 if (Opts.UnsafeFPMath) 5601 Builder.defineMacro("__ARM_FP_FAST", "1"); 5602 5603 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5604 5605 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5606 Opts.ShortEnums ? "1" : "4"); 5607 5608 if (FPU == NeonMode) { 5609 Builder.defineMacro("__ARM_NEON", "1"); 5610 // 64-bit NEON supports half, single and double precision operations. 5611 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5612 } 5613 5614 if (CRC) 5615 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5616 5617 if (Crypto) 5618 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5619 5620 if (Unaligned) 5621 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5622 5623 if (V8_1A) 5624 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5625 5626 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5627 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5628 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5629 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5630 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5631 } 5632 5633 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5634 return llvm::makeArrayRef(BuiltinInfo, 5635 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5636 } 5637 5638 bool hasFeature(StringRef Feature) const override { 5639 return Feature == "aarch64" || 5640 Feature == "arm64" || 5641 Feature == "arm" || 5642 (Feature == "neon" && FPU == NeonMode); 5643 } 5644 5645 bool handleTargetFeatures(std::vector<std::string> &Features, 5646 DiagnosticsEngine &Diags) override { 5647 FPU = FPUMode; 5648 CRC = 0; 5649 Crypto = 0; 5650 Unaligned = 1; 5651 V8_1A = 0; 5652 5653 for (const auto &Feature : Features) { 5654 if (Feature == "+neon") 5655 FPU = NeonMode; 5656 if (Feature == "+crc") 5657 CRC = 1; 5658 if (Feature == "+crypto") 5659 Crypto = 1; 5660 if (Feature == "+strict-align") 5661 Unaligned = 0; 5662 if (Feature == "+v8.1a") 5663 V8_1A = 1; 5664 } 5665 5666 setDataLayout(); 5667 5668 return true; 5669 } 5670 5671 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5672 switch (CC) { 5673 case CC_C: 5674 case CC_Swift: 5675 case CC_PreserveMost: 5676 case CC_PreserveAll: 5677 return CCCR_OK; 5678 default: 5679 return CCCR_Warning; 5680 } 5681 } 5682 5683 bool isCLZForZeroUndef() const override { return false; } 5684 5685 BuiltinVaListKind getBuiltinVaListKind() const override { 5686 return TargetInfo::AArch64ABIBuiltinVaList; 5687 } 5688 5689 ArrayRef<const char *> getGCCRegNames() const override; 5690 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5691 5692 bool validateAsmConstraint(const char *&Name, 5693 TargetInfo::ConstraintInfo &Info) const override { 5694 switch (*Name) { 5695 default: 5696 return false; 5697 case 'w': // Floating point and SIMD registers (V0-V31) 5698 Info.setAllowsRegister(); 5699 return true; 5700 case 'I': // Constant that can be used with an ADD instruction 5701 case 'J': // Constant that can be used with a SUB instruction 5702 case 'K': // Constant that can be used with a 32-bit logical instruction 5703 case 'L': // Constant that can be used with a 64-bit logical instruction 5704 case 'M': // Constant that can be used as a 32-bit MOV immediate 5705 case 'N': // Constant that can be used as a 64-bit MOV immediate 5706 case 'Y': // Floating point constant zero 5707 case 'Z': // Integer constant zero 5708 return true; 5709 case 'Q': // A memory reference with base register and no offset 5710 Info.setAllowsMemory(); 5711 return true; 5712 case 'S': // A symbolic address 5713 Info.setAllowsRegister(); 5714 return true; 5715 case 'U': 5716 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5717 // Utf: A memory address suitable for ldp/stp in TF mode. 5718 // Usa: An absolute symbolic address. 5719 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5720 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5721 case 'z': // Zero register, wzr or xzr 5722 Info.setAllowsRegister(); 5723 return true; 5724 case 'x': // Floating point and SIMD registers (V0-V15) 5725 Info.setAllowsRegister(); 5726 return true; 5727 } 5728 return false; 5729 } 5730 5731 bool 5732 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5733 std::string &SuggestedModifier) const override { 5734 // Strip off constraint modifiers. 5735 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5736 Constraint = Constraint.substr(1); 5737 5738 switch (Constraint[0]) { 5739 default: 5740 return true; 5741 case 'z': 5742 case 'r': { 5743 switch (Modifier) { 5744 case 'x': 5745 case 'w': 5746 // For now assume that the person knows what they're 5747 // doing with the modifier. 5748 return true; 5749 default: 5750 // By default an 'r' constraint will be in the 'x' 5751 // registers. 5752 if (Size == 64) 5753 return true; 5754 5755 SuggestedModifier = "w"; 5756 return false; 5757 } 5758 } 5759 } 5760 } 5761 5762 const char *getClobbers() const override { return ""; } 5763 5764 int getEHDataRegisterNumber(unsigned RegNo) const override { 5765 if (RegNo == 0) 5766 return 0; 5767 if (RegNo == 1) 5768 return 1; 5769 return -1; 5770 } 5771 }; 5772 5773 const char *const AArch64TargetInfo::GCCRegNames[] = { 5774 // 32-bit Integer registers 5775 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5776 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5777 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5778 5779 // 64-bit Integer registers 5780 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5781 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5782 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5783 5784 // 32-bit floating point regsisters 5785 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5786 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5787 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5788 5789 // 64-bit floating point regsisters 5790 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5791 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5792 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5793 5794 // Vector registers 5795 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5796 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5797 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5798 }; 5799 5800 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 5801 return llvm::makeArrayRef(GCCRegNames); 5802 } 5803 5804 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5805 { { "w31" }, "wsp" }, 5806 { { "x29" }, "fp" }, 5807 { { "x30" }, "lr" }, 5808 { { "x31" }, "sp" }, 5809 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5810 // don't want to substitute one of these for a different-sized one. 5811 }; 5812 5813 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 5814 return llvm::makeArrayRef(GCCRegAliases); 5815 } 5816 5817 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5818 #define BUILTIN(ID, TYPE, ATTRS) \ 5819 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5820 #include "clang/Basic/BuiltinsNEON.def" 5821 5822 #define BUILTIN(ID, TYPE, ATTRS) \ 5823 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5824 #include "clang/Basic/BuiltinsAArch64.def" 5825 }; 5826 5827 class AArch64leTargetInfo : public AArch64TargetInfo { 5828 void setDataLayout() override { 5829 if (getTriple().isOSBinFormatMachO()) 5830 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 5831 else 5832 resetDataLayout("e-m:e-i64:64-i128:128-n32:64-S128"); 5833 } 5834 5835 public: 5836 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5837 : AArch64TargetInfo(Triple, Opts) { 5838 BigEndian = false; 5839 } 5840 void getTargetDefines(const LangOptions &Opts, 5841 MacroBuilder &Builder) const override { 5842 Builder.defineMacro("__AARCH64EL__"); 5843 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5844 } 5845 }; 5846 5847 class AArch64beTargetInfo : public AArch64TargetInfo { 5848 void setDataLayout() override { 5849 assert(!getTriple().isOSBinFormatMachO()); 5850 resetDataLayout("E-m:e-i64:64-i128:128-n32:64-S128"); 5851 } 5852 5853 public: 5854 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5855 : AArch64TargetInfo(Triple, Opts) {} 5856 void getTargetDefines(const LangOptions &Opts, 5857 MacroBuilder &Builder) const override { 5858 Builder.defineMacro("__AARCH64EB__"); 5859 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5860 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5861 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5862 } 5863 }; 5864 5865 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5866 protected: 5867 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5868 MacroBuilder &Builder) const override { 5869 Builder.defineMacro("__AARCH64_SIMD__"); 5870 Builder.defineMacro("__ARM64_ARCH_8__"); 5871 Builder.defineMacro("__ARM_NEON__"); 5872 Builder.defineMacro("__LITTLE_ENDIAN__"); 5873 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5874 Builder.defineMacro("__arm64", "1"); 5875 Builder.defineMacro("__arm64__", "1"); 5876 5877 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5878 } 5879 5880 public: 5881 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5882 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 5883 Int64Type = SignedLongLong; 5884 WCharType = SignedInt; 5885 UseSignedCharForObjCBool = false; 5886 5887 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5888 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5889 5890 TheCXXABI.set(TargetCXXABI::iOS64); 5891 } 5892 5893 BuiltinVaListKind getBuiltinVaListKind() const override { 5894 return TargetInfo::CharPtrBuiltinVaList; 5895 } 5896 }; 5897 5898 // Hexagon abstract base class 5899 class HexagonTargetInfo : public TargetInfo { 5900 static const Builtin::Info BuiltinInfo[]; 5901 static const char * const GCCRegNames[]; 5902 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5903 std::string CPU; 5904 bool HasHVX, HasHVXDouble; 5905 5906 public: 5907 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 5908 : TargetInfo(Triple) { 5909 BigEndian = false; 5910 // Specify the vector alignment explicitly. For v512x1, the calculated 5911 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 5912 // the required minimum of 64 bytes. 5913 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 5914 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 5915 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 5916 SizeType = UnsignedInt; 5917 PtrDiffType = SignedInt; 5918 IntPtrType = SignedInt; 5919 5920 // {} in inline assembly are packet specifiers, not assembly variant 5921 // specifiers. 5922 NoAsmVariants = true; 5923 5924 LargeArrayMinWidth = 64; 5925 LargeArrayAlign = 64; 5926 UseBitFieldTypeAlignment = true; 5927 ZeroLengthBitfieldBoundary = 32; 5928 HasHVX = HasHVXDouble = false; 5929 } 5930 5931 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5932 return llvm::makeArrayRef(BuiltinInfo, 5933 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 5934 } 5935 5936 bool validateAsmConstraint(const char *&Name, 5937 TargetInfo::ConstraintInfo &Info) const override { 5938 return true; 5939 } 5940 5941 void getTargetDefines(const LangOptions &Opts, 5942 MacroBuilder &Builder) const override; 5943 5944 bool isCLZForZeroUndef() const override { return false; } 5945 5946 bool hasFeature(StringRef Feature) const override { 5947 return llvm::StringSwitch<bool>(Feature) 5948 .Case("hexagon", true) 5949 .Case("hvx", HasHVX) 5950 .Case("hvx-double", HasHVXDouble) 5951 .Default(false); 5952 } 5953 5954 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5955 StringRef CPU, const std::vector<std::string> &FeaturesVec) 5956 const override; 5957 5958 bool handleTargetFeatures(std::vector<std::string> &Features, 5959 DiagnosticsEngine &Diags) override; 5960 5961 BuiltinVaListKind getBuiltinVaListKind() const override { 5962 return TargetInfo::CharPtrBuiltinVaList; 5963 } 5964 ArrayRef<const char *> getGCCRegNames() const override; 5965 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5966 const char *getClobbers() const override { 5967 return ""; 5968 } 5969 5970 static const char *getHexagonCPUSuffix(StringRef Name) { 5971 return llvm::StringSwitch<const char*>(Name) 5972 .Case("hexagonv4", "4") 5973 .Case("hexagonv5", "5") 5974 .Case("hexagonv55", "55") 5975 .Case("hexagonv60", "60") 5976 .Default(nullptr); 5977 } 5978 5979 bool setCPU(const std::string &Name) override { 5980 if (!getHexagonCPUSuffix(Name)) 5981 return false; 5982 CPU = Name; 5983 return true; 5984 } 5985 5986 int getEHDataRegisterNumber(unsigned RegNo) const override { 5987 return RegNo < 2 ? RegNo : -1; 5988 } 5989 }; 5990 5991 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5992 MacroBuilder &Builder) const { 5993 Builder.defineMacro("__qdsp6__", "1"); 5994 Builder.defineMacro("__hexagon__", "1"); 5995 5996 if (CPU == "hexagonv4") { 5997 Builder.defineMacro("__HEXAGON_V4__"); 5998 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5999 if (Opts.HexagonQdsp6Compat) { 6000 Builder.defineMacro("__QDSP6_V4__"); 6001 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6002 } 6003 } else if (CPU == "hexagonv5") { 6004 Builder.defineMacro("__HEXAGON_V5__"); 6005 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6006 if(Opts.HexagonQdsp6Compat) { 6007 Builder.defineMacro("__QDSP6_V5__"); 6008 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6009 } 6010 } else if (CPU == "hexagonv55") { 6011 Builder.defineMacro("__HEXAGON_V55__"); 6012 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6013 Builder.defineMacro("__QDSP6_V55__"); 6014 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6015 } else if (CPU == "hexagonv60") { 6016 Builder.defineMacro("__HEXAGON_V60__"); 6017 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6018 Builder.defineMacro("__QDSP6_V60__"); 6019 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6020 } 6021 6022 if (hasFeature("hvx")) { 6023 Builder.defineMacro("__HVX__"); 6024 if (hasFeature("hvx-double")) 6025 Builder.defineMacro("__HVXDBL__"); 6026 } 6027 } 6028 6029 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6030 DiagnosticsEngine &Diags) { 6031 for (auto &F : Features) { 6032 if (F == "+hvx") 6033 HasHVX = true; 6034 else if (F == "-hvx") 6035 HasHVX = HasHVXDouble = false; 6036 else if (F == "+hvx-double") 6037 HasHVX = HasHVXDouble = true; 6038 else if (F == "-hvx-double") 6039 HasHVXDouble = false; 6040 } 6041 return true; 6042 } 6043 6044 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6045 DiagnosticsEngine &Diags, StringRef CPU, 6046 const std::vector<std::string> &FeaturesVec) const { 6047 // Default for v60: -hvx, -hvx-double. 6048 Features["hvx"] = false; 6049 Features["hvx-double"] = false; 6050 6051 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6052 } 6053 6054 6055 const char *const HexagonTargetInfo::GCCRegNames[] = { 6056 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6057 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6058 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6059 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6060 "p0", "p1", "p2", "p3", 6061 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6062 }; 6063 6064 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6065 return llvm::makeArrayRef(GCCRegNames); 6066 } 6067 6068 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6069 { { "sp" }, "r29" }, 6070 { { "fp" }, "r30" }, 6071 { { "lr" }, "r31" }, 6072 }; 6073 6074 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6075 return llvm::makeArrayRef(GCCRegAliases); 6076 } 6077 6078 6079 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6080 #define BUILTIN(ID, TYPE, ATTRS) \ 6081 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6082 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6083 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6084 #include "clang/Basic/BuiltinsHexagon.def" 6085 }; 6086 6087 class LanaiTargetInfo : public TargetInfo { 6088 // Class for Lanai (32-bit). 6089 // The CPU profiles supported by the Lanai backend 6090 enum CPUKind { 6091 CK_NONE, 6092 CK_V11, 6093 } CPU; 6094 6095 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6096 static const char *const GCCRegNames[]; 6097 6098 public: 6099 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6100 : TargetInfo(Triple) { 6101 // Description string has to be kept in sync with backend. 6102 resetDataLayout("E" // Big endian 6103 "-m:e" // ELF name manging 6104 "-p:32:32" // 32 bit pointers, 32 bit aligned 6105 "-i64:64" // 64 bit integers, 64 bit aligned 6106 "-a:0:32" // 32 bit alignment of objects of aggregate type 6107 "-n32" // 32 bit native integer width 6108 "-S64" // 64 bit natural stack alignment 6109 ); 6110 6111 // Setting RegParmMax equal to what mregparm was set to in the old 6112 // toolchain 6113 RegParmMax = 4; 6114 6115 // Set the default CPU to V11 6116 CPU = CK_V11; 6117 6118 // Temporary approach to make everything at least word-aligned and allow for 6119 // safely casting between pointers with different alignment requirements. 6120 // TODO: Remove this when there are no more cast align warnings on the 6121 // firmware. 6122 MinGlobalAlign = 32; 6123 } 6124 6125 void getTargetDefines(const LangOptions &Opts, 6126 MacroBuilder &Builder) const override { 6127 // Define __lanai__ when building for target lanai. 6128 Builder.defineMacro("__lanai__"); 6129 6130 // Set define for the CPU specified. 6131 switch (CPU) { 6132 case CK_V11: 6133 Builder.defineMacro("__LANAI_V11__"); 6134 break; 6135 case CK_NONE: 6136 llvm_unreachable("Unhandled target CPU"); 6137 } 6138 } 6139 6140 bool setCPU(const std::string &Name) override { 6141 CPU = llvm::StringSwitch<CPUKind>(Name) 6142 .Case("v11", CK_V11) 6143 .Default(CK_NONE); 6144 6145 return CPU != CK_NONE; 6146 } 6147 6148 bool hasFeature(StringRef Feature) const override { 6149 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6150 } 6151 6152 ArrayRef<const char *> getGCCRegNames() const override; 6153 6154 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6155 6156 BuiltinVaListKind getBuiltinVaListKind() const override { 6157 return TargetInfo::VoidPtrBuiltinVaList; 6158 } 6159 6160 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6161 6162 bool validateAsmConstraint(const char *&Name, 6163 TargetInfo::ConstraintInfo &info) const override { 6164 return false; 6165 } 6166 6167 const char *getClobbers() const override { return ""; } 6168 }; 6169 6170 const char *const LanaiTargetInfo::GCCRegNames[] = { 6171 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6172 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6173 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6174 6175 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6176 return llvm::makeArrayRef(GCCRegNames); 6177 } 6178 6179 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6180 {{"pc"}, "r2"}, 6181 {{"sp"}, "r4"}, 6182 {{"fp"}, "r5"}, 6183 {{"rv"}, "r8"}, 6184 {{"rr1"}, "r10"}, 6185 {{"rr2"}, "r11"}, 6186 {{"rca"}, "r15"}, 6187 }; 6188 6189 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6190 return llvm::makeArrayRef(GCCRegAliases); 6191 } 6192 6193 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6194 class SparcTargetInfo : public TargetInfo { 6195 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6196 static const char * const GCCRegNames[]; 6197 bool SoftFloat; 6198 public: 6199 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6200 : TargetInfo(Triple), SoftFloat(false) {} 6201 6202 int getEHDataRegisterNumber(unsigned RegNo) const override { 6203 if (RegNo == 0) return 24; 6204 if (RegNo == 1) return 25; 6205 return -1; 6206 } 6207 6208 bool handleTargetFeatures(std::vector<std::string> &Features, 6209 DiagnosticsEngine &Diags) override { 6210 // The backend doesn't actually handle soft float yet, but in case someone 6211 // is using the support for the front end continue to support it. 6212 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6213 if (Feature != Features.end()) { 6214 SoftFloat = true; 6215 Features.erase(Feature); 6216 } 6217 return true; 6218 } 6219 void getTargetDefines(const LangOptions &Opts, 6220 MacroBuilder &Builder) const override { 6221 DefineStd(Builder, "sparc", Opts); 6222 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6223 6224 if (SoftFloat) 6225 Builder.defineMacro("SOFT_FLOAT", "1"); 6226 } 6227 6228 bool hasFeature(StringRef Feature) const override { 6229 return llvm::StringSwitch<bool>(Feature) 6230 .Case("softfloat", SoftFloat) 6231 .Case("sparc", true) 6232 .Default(false); 6233 } 6234 6235 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6236 // FIXME: Implement! 6237 return None; 6238 } 6239 BuiltinVaListKind getBuiltinVaListKind() const override { 6240 return TargetInfo::VoidPtrBuiltinVaList; 6241 } 6242 ArrayRef<const char *> getGCCRegNames() const override; 6243 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6244 bool validateAsmConstraint(const char *&Name, 6245 TargetInfo::ConstraintInfo &info) const override { 6246 // FIXME: Implement! 6247 switch (*Name) { 6248 case 'I': // Signed 13-bit constant 6249 case 'J': // Zero 6250 case 'K': // 32-bit constant with the low 12 bits clear 6251 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6252 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6253 case 'N': // Same as 'K' but zext (required for SIMode) 6254 case 'O': // The constant 4096 6255 return true; 6256 } 6257 return false; 6258 } 6259 const char *getClobbers() const override { 6260 // FIXME: Implement! 6261 return ""; 6262 } 6263 6264 // No Sparc V7 for now, the backend doesn't support it anyway. 6265 enum CPUKind { 6266 CK_GENERIC, 6267 CK_V8, 6268 CK_SUPERSPARC, 6269 CK_SPARCLITE, 6270 CK_F934, 6271 CK_HYPERSPARC, 6272 CK_SPARCLITE86X, 6273 CK_SPARCLET, 6274 CK_TSC701, 6275 CK_V9, 6276 CK_ULTRASPARC, 6277 CK_ULTRASPARC3, 6278 CK_NIAGARA, 6279 CK_NIAGARA2, 6280 CK_NIAGARA3, 6281 CK_NIAGARA4, 6282 CK_MYRIAD2_1, 6283 CK_MYRIAD2_2 6284 } CPU = CK_GENERIC; 6285 6286 enum CPUGeneration { 6287 CG_V8, 6288 CG_V9, 6289 }; 6290 6291 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6292 switch (Kind) { 6293 case CK_GENERIC: 6294 case CK_V8: 6295 case CK_SUPERSPARC: 6296 case CK_SPARCLITE: 6297 case CK_F934: 6298 case CK_HYPERSPARC: 6299 case CK_SPARCLITE86X: 6300 case CK_SPARCLET: 6301 case CK_TSC701: 6302 case CK_MYRIAD2_1: 6303 case CK_MYRIAD2_2: 6304 return CG_V8; 6305 case CK_V9: 6306 case CK_ULTRASPARC: 6307 case CK_ULTRASPARC3: 6308 case CK_NIAGARA: 6309 case CK_NIAGARA2: 6310 case CK_NIAGARA3: 6311 case CK_NIAGARA4: 6312 return CG_V9; 6313 } 6314 llvm_unreachable("Unexpected CPU kind"); 6315 } 6316 6317 CPUKind getCPUKind(StringRef Name) const { 6318 return llvm::StringSwitch<CPUKind>(Name) 6319 .Case("v8", CK_V8) 6320 .Case("supersparc", CK_SUPERSPARC) 6321 .Case("sparclite", CK_SPARCLITE) 6322 .Case("f934", CK_F934) 6323 .Case("hypersparc", CK_HYPERSPARC) 6324 .Case("sparclite86x", CK_SPARCLITE86X) 6325 .Case("sparclet", CK_SPARCLET) 6326 .Case("tsc701", CK_TSC701) 6327 .Case("v9", CK_V9) 6328 .Case("ultrasparc", CK_ULTRASPARC) 6329 .Case("ultrasparc3", CK_ULTRASPARC3) 6330 .Case("niagara", CK_NIAGARA) 6331 .Case("niagara2", CK_NIAGARA2) 6332 .Case("niagara3", CK_NIAGARA3) 6333 .Case("niagara4", CK_NIAGARA4) 6334 .Case("myriad2", CK_MYRIAD2_1) 6335 .Case("myriad2.1", CK_MYRIAD2_1) 6336 .Case("myriad2.2", CK_MYRIAD2_2) 6337 .Default(CK_GENERIC); 6338 } 6339 6340 bool setCPU(const std::string &Name) override { 6341 CPU = getCPUKind(Name); 6342 return CPU != CK_GENERIC; 6343 } 6344 }; 6345 6346 const char * const SparcTargetInfo::GCCRegNames[] = { 6347 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6348 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6349 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6350 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6351 }; 6352 6353 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6354 return llvm::makeArrayRef(GCCRegNames); 6355 } 6356 6357 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6358 { { "g0" }, "r0" }, 6359 { { "g1" }, "r1" }, 6360 { { "g2" }, "r2" }, 6361 { { "g3" }, "r3" }, 6362 { { "g4" }, "r4" }, 6363 { { "g5" }, "r5" }, 6364 { { "g6" }, "r6" }, 6365 { { "g7" }, "r7" }, 6366 { { "o0" }, "r8" }, 6367 { { "o1" }, "r9" }, 6368 { { "o2" }, "r10" }, 6369 { { "o3" }, "r11" }, 6370 { { "o4" }, "r12" }, 6371 { { "o5" }, "r13" }, 6372 { { "o6", "sp" }, "r14" }, 6373 { { "o7" }, "r15" }, 6374 { { "l0" }, "r16" }, 6375 { { "l1" }, "r17" }, 6376 { { "l2" }, "r18" }, 6377 { { "l3" }, "r19" }, 6378 { { "l4" }, "r20" }, 6379 { { "l5" }, "r21" }, 6380 { { "l6" }, "r22" }, 6381 { { "l7" }, "r23" }, 6382 { { "i0" }, "r24" }, 6383 { { "i1" }, "r25" }, 6384 { { "i2" }, "r26" }, 6385 { { "i3" }, "r27" }, 6386 { { "i4" }, "r28" }, 6387 { { "i5" }, "r29" }, 6388 { { "i6", "fp" }, "r30" }, 6389 { { "i7" }, "r31" }, 6390 }; 6391 6392 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6393 return llvm::makeArrayRef(GCCRegAliases); 6394 } 6395 6396 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6397 class SparcV8TargetInfo : public SparcTargetInfo { 6398 public: 6399 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6400 : SparcTargetInfo(Triple, Opts) { 6401 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6402 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6403 switch (getTriple().getOS()) { 6404 default: 6405 SizeType = UnsignedInt; 6406 IntPtrType = SignedInt; 6407 PtrDiffType = SignedInt; 6408 break; 6409 case llvm::Triple::NetBSD: 6410 case llvm::Triple::OpenBSD: 6411 SizeType = UnsignedLong; 6412 IntPtrType = SignedLong; 6413 PtrDiffType = SignedLong; 6414 break; 6415 } 6416 } 6417 6418 void getTargetDefines(const LangOptions &Opts, 6419 MacroBuilder &Builder) const override { 6420 SparcTargetInfo::getTargetDefines(Opts, Builder); 6421 switch (getCPUGeneration(CPU)) { 6422 case CG_V8: 6423 Builder.defineMacro("__sparcv8"); 6424 if (getTriple().getOS() != llvm::Triple::Solaris) 6425 Builder.defineMacro("__sparcv8__"); 6426 break; 6427 case CG_V9: 6428 Builder.defineMacro("__sparcv9"); 6429 if (getTriple().getOS() != llvm::Triple::Solaris) { 6430 Builder.defineMacro("__sparcv9__"); 6431 Builder.defineMacro("__sparc_v9__"); 6432 } 6433 break; 6434 } 6435 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6436 switch (CPU) { 6437 case CK_MYRIAD2_1: 6438 Builder.defineMacro("__myriad2", "1"); 6439 Builder.defineMacro("__myriad2__", "1"); 6440 break; 6441 case CK_MYRIAD2_2: 6442 Builder.defineMacro("__myriad2", "2"); 6443 Builder.defineMacro("__myriad2__", "2"); 6444 break; 6445 default: 6446 break; 6447 } 6448 } 6449 } 6450 }; 6451 6452 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6453 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6454 public: 6455 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6456 : SparcV8TargetInfo(Triple, Opts) { 6457 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6458 BigEndian = false; 6459 } 6460 }; 6461 6462 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6463 class SparcV9TargetInfo : public SparcTargetInfo { 6464 public: 6465 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6466 : SparcTargetInfo(Triple, Opts) { 6467 // FIXME: Support Sparc quad-precision long double? 6468 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6469 // This is an LP64 platform. 6470 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6471 6472 // OpenBSD uses long long for int64_t and intmax_t. 6473 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6474 IntMaxType = SignedLongLong; 6475 else 6476 IntMaxType = SignedLong; 6477 Int64Type = IntMaxType; 6478 6479 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6480 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6481 LongDoubleWidth = 128; 6482 LongDoubleAlign = 128; 6483 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6484 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6485 } 6486 6487 void getTargetDefines(const LangOptions &Opts, 6488 MacroBuilder &Builder) const override { 6489 SparcTargetInfo::getTargetDefines(Opts, Builder); 6490 Builder.defineMacro("__sparcv9"); 6491 Builder.defineMacro("__arch64__"); 6492 // Solaris doesn't need these variants, but the BSDs do. 6493 if (getTriple().getOS() != llvm::Triple::Solaris) { 6494 Builder.defineMacro("__sparc64__"); 6495 Builder.defineMacro("__sparc_v9__"); 6496 Builder.defineMacro("__sparcv9__"); 6497 } 6498 } 6499 6500 bool setCPU(const std::string &Name) override { 6501 if (!SparcTargetInfo::setCPU(Name)) 6502 return false; 6503 return getCPUGeneration(CPU) == CG_V9; 6504 } 6505 }; 6506 6507 class SystemZTargetInfo : public TargetInfo { 6508 static const Builtin::Info BuiltinInfo[]; 6509 static const char *const GCCRegNames[]; 6510 std::string CPU; 6511 bool HasTransactionalExecution; 6512 bool HasVector; 6513 6514 public: 6515 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6516 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6517 HasVector(false) { 6518 IntMaxType = SignedLong; 6519 Int64Type = SignedLong; 6520 TLSSupported = true; 6521 IntWidth = IntAlign = 32; 6522 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6523 PointerWidth = PointerAlign = 64; 6524 LongDoubleWidth = 128; 6525 LongDoubleAlign = 64; 6526 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6527 DefaultAlignForAttributeAligned = 64; 6528 MinGlobalAlign = 16; 6529 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 6530 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6531 } 6532 void getTargetDefines(const LangOptions &Opts, 6533 MacroBuilder &Builder) const override { 6534 Builder.defineMacro("__s390__"); 6535 Builder.defineMacro("__s390x__"); 6536 Builder.defineMacro("__zarch__"); 6537 Builder.defineMacro("__LONG_DOUBLE_128__"); 6538 6539 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6540 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6541 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6542 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6543 6544 if (HasTransactionalExecution) 6545 Builder.defineMacro("__HTM__"); 6546 if (Opts.ZVector) 6547 Builder.defineMacro("__VEC__", "10301"); 6548 } 6549 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6550 return llvm::makeArrayRef(BuiltinInfo, 6551 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6552 } 6553 6554 ArrayRef<const char *> getGCCRegNames() const override; 6555 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6556 // No aliases. 6557 return None; 6558 } 6559 bool validateAsmConstraint(const char *&Name, 6560 TargetInfo::ConstraintInfo &info) const override; 6561 const char *getClobbers() const override { 6562 // FIXME: Is this really right? 6563 return ""; 6564 } 6565 BuiltinVaListKind getBuiltinVaListKind() const override { 6566 return TargetInfo::SystemZBuiltinVaList; 6567 } 6568 bool setCPU(const std::string &Name) override { 6569 CPU = Name; 6570 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6571 .Case("z10", true) 6572 .Case("z196", true) 6573 .Case("zEC12", true) 6574 .Case("z13", true) 6575 .Default(false); 6576 6577 return CPUKnown; 6578 } 6579 bool 6580 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6581 StringRef CPU, 6582 const std::vector<std::string> &FeaturesVec) const override { 6583 if (CPU == "zEC12") 6584 Features["transactional-execution"] = true; 6585 if (CPU == "z13") { 6586 Features["transactional-execution"] = true; 6587 Features["vector"] = true; 6588 } 6589 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6590 } 6591 6592 bool handleTargetFeatures(std::vector<std::string> &Features, 6593 DiagnosticsEngine &Diags) override { 6594 HasTransactionalExecution = false; 6595 for (const auto &Feature : Features) { 6596 if (Feature == "+transactional-execution") 6597 HasTransactionalExecution = true; 6598 else if (Feature == "+vector") 6599 HasVector = true; 6600 } 6601 // If we use the vector ABI, vector types are 64-bit aligned. 6602 if (HasVector) { 6603 MaxVectorAlign = 64; 6604 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6605 "-v128:64-a:8:16-n32:64"); 6606 } 6607 return true; 6608 } 6609 6610 bool hasFeature(StringRef Feature) const override { 6611 return llvm::StringSwitch<bool>(Feature) 6612 .Case("systemz", true) 6613 .Case("htm", HasTransactionalExecution) 6614 .Case("vx", HasVector) 6615 .Default(false); 6616 } 6617 6618 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6619 switch (CC) { 6620 case CC_C: 6621 case CC_Swift: 6622 return CCCR_OK; 6623 default: 6624 return CCCR_Warning; 6625 } 6626 } 6627 6628 StringRef getABI() const override { 6629 if (HasVector) 6630 return "vector"; 6631 return ""; 6632 } 6633 6634 bool useFloat128ManglingForLongDouble() const override { 6635 return true; 6636 } 6637 }; 6638 6639 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6640 #define BUILTIN(ID, TYPE, ATTRS) \ 6641 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6642 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 6643 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 6644 #include "clang/Basic/BuiltinsSystemZ.def" 6645 }; 6646 6647 const char *const SystemZTargetInfo::GCCRegNames[] = { 6648 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6649 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6650 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6651 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6652 }; 6653 6654 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6655 return llvm::makeArrayRef(GCCRegNames); 6656 } 6657 6658 bool SystemZTargetInfo:: 6659 validateAsmConstraint(const char *&Name, 6660 TargetInfo::ConstraintInfo &Info) const { 6661 switch (*Name) { 6662 default: 6663 return false; 6664 6665 case 'a': // Address register 6666 case 'd': // Data register (equivalent to 'r') 6667 case 'f': // Floating-point register 6668 Info.setAllowsRegister(); 6669 return true; 6670 6671 case 'I': // Unsigned 8-bit constant 6672 case 'J': // Unsigned 12-bit constant 6673 case 'K': // Signed 16-bit constant 6674 case 'L': // Signed 20-bit displacement (on all targets we support) 6675 case 'M': // 0x7fffffff 6676 return true; 6677 6678 case 'Q': // Memory with base and unsigned 12-bit displacement 6679 case 'R': // Likewise, plus an index 6680 case 'S': // Memory with base and signed 20-bit displacement 6681 case 'T': // Likewise, plus an index 6682 Info.setAllowsMemory(); 6683 return true; 6684 } 6685 } 6686 6687 class MSP430TargetInfo : public TargetInfo { 6688 static const char *const GCCRegNames[]; 6689 6690 public: 6691 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6692 : TargetInfo(Triple) { 6693 BigEndian = false; 6694 TLSSupported = false; 6695 IntWidth = 16; 6696 IntAlign = 16; 6697 LongWidth = 32; 6698 LongLongWidth = 64; 6699 LongAlign = LongLongAlign = 16; 6700 PointerWidth = 16; 6701 PointerAlign = 16; 6702 SuitableAlign = 16; 6703 SizeType = UnsignedInt; 6704 IntMaxType = SignedLongLong; 6705 IntPtrType = SignedInt; 6706 PtrDiffType = SignedInt; 6707 SigAtomicType = SignedLong; 6708 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 6709 } 6710 void getTargetDefines(const LangOptions &Opts, 6711 MacroBuilder &Builder) const override { 6712 Builder.defineMacro("MSP430"); 6713 Builder.defineMacro("__MSP430__"); 6714 // FIXME: defines for different 'flavours' of MCU 6715 } 6716 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6717 // FIXME: Implement. 6718 return None; 6719 } 6720 bool hasFeature(StringRef Feature) const override { 6721 return Feature == "msp430"; 6722 } 6723 ArrayRef<const char *> getGCCRegNames() const override; 6724 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6725 // No aliases. 6726 return None; 6727 } 6728 bool validateAsmConstraint(const char *&Name, 6729 TargetInfo::ConstraintInfo &info) const override { 6730 // FIXME: implement 6731 switch (*Name) { 6732 case 'K': // the constant 1 6733 case 'L': // constant -1^20 .. 1^19 6734 case 'M': // constant 1-4: 6735 return true; 6736 } 6737 // No target constraints for now. 6738 return false; 6739 } 6740 const char *getClobbers() const override { 6741 // FIXME: Is this really right? 6742 return ""; 6743 } 6744 BuiltinVaListKind getBuiltinVaListKind() const override { 6745 // FIXME: implement 6746 return TargetInfo::CharPtrBuiltinVaList; 6747 } 6748 }; 6749 6750 const char *const MSP430TargetInfo::GCCRegNames[] = { 6751 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6752 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6753 6754 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 6755 return llvm::makeArrayRef(GCCRegNames); 6756 } 6757 6758 // LLVM and Clang cannot be used directly to output native binaries for 6759 // target, but is used to compile C code to llvm bitcode with correct 6760 // type and alignment information. 6761 // 6762 // TCE uses the llvm bitcode as input and uses it for generating customized 6763 // target processor and program binary. TCE co-design environment is 6764 // publicly available in http://tce.cs.tut.fi 6765 6766 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6767 3, // opencl_global 6768 4, // opencl_local 6769 5, // opencl_constant 6770 // FIXME: generic has to be added to the target 6771 0, // opencl_generic 6772 0, // cuda_device 6773 0, // cuda_constant 6774 0 // cuda_shared 6775 }; 6776 6777 class TCETargetInfo : public TargetInfo { 6778 public: 6779 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6780 : TargetInfo(Triple) { 6781 TLSSupported = false; 6782 IntWidth = 32; 6783 LongWidth = LongLongWidth = 32; 6784 PointerWidth = 32; 6785 IntAlign = 32; 6786 LongAlign = LongLongAlign = 32; 6787 PointerAlign = 32; 6788 SuitableAlign = 32; 6789 SizeType = UnsignedInt; 6790 IntMaxType = SignedLong; 6791 IntPtrType = SignedInt; 6792 PtrDiffType = SignedInt; 6793 FloatWidth = 32; 6794 FloatAlign = 32; 6795 DoubleWidth = 32; 6796 DoubleAlign = 32; 6797 LongDoubleWidth = 32; 6798 LongDoubleAlign = 32; 6799 FloatFormat = &llvm::APFloat::IEEEsingle; 6800 DoubleFormat = &llvm::APFloat::IEEEsingle; 6801 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6802 resetDataLayout("E-p:32:32-i8:8:32-i16:16:32-i64:32" 6803 "-f64:32-v64:32-v128:32-a:0:32-n32"); 6804 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6805 UseAddrSpaceMapMangling = true; 6806 } 6807 6808 void getTargetDefines(const LangOptions &Opts, 6809 MacroBuilder &Builder) const override { 6810 DefineStd(Builder, "tce", Opts); 6811 Builder.defineMacro("__TCE__"); 6812 Builder.defineMacro("__TCE_V1__"); 6813 } 6814 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 6815 6816 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6817 const char *getClobbers() const override { return ""; } 6818 BuiltinVaListKind getBuiltinVaListKind() const override { 6819 return TargetInfo::VoidPtrBuiltinVaList; 6820 } 6821 ArrayRef<const char *> getGCCRegNames() const override { return None; } 6822 bool validateAsmConstraint(const char *&Name, 6823 TargetInfo::ConstraintInfo &info) const override { 6824 return true; 6825 } 6826 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6827 return None; 6828 } 6829 }; 6830 6831 class BPFTargetInfo : public TargetInfo { 6832 public: 6833 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6834 : TargetInfo(Triple) { 6835 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6836 SizeType = UnsignedLong; 6837 PtrDiffType = SignedLong; 6838 IntPtrType = SignedLong; 6839 IntMaxType = SignedLong; 6840 Int64Type = SignedLong; 6841 RegParmMax = 5; 6842 if (Triple.getArch() == llvm::Triple::bpfeb) { 6843 BigEndian = true; 6844 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 6845 } else { 6846 BigEndian = false; 6847 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 6848 } 6849 MaxAtomicPromoteWidth = 64; 6850 MaxAtomicInlineWidth = 64; 6851 TLSSupported = false; 6852 } 6853 void getTargetDefines(const LangOptions &Opts, 6854 MacroBuilder &Builder) const override { 6855 DefineStd(Builder, "bpf", Opts); 6856 Builder.defineMacro("__BPF__"); 6857 } 6858 bool hasFeature(StringRef Feature) const override { 6859 return Feature == "bpf"; 6860 } 6861 6862 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6863 const char *getClobbers() const override { 6864 return ""; 6865 } 6866 BuiltinVaListKind getBuiltinVaListKind() const override { 6867 return TargetInfo::VoidPtrBuiltinVaList; 6868 } 6869 ArrayRef<const char *> getGCCRegNames() const override { 6870 return None; 6871 } 6872 bool validateAsmConstraint(const char *&Name, 6873 TargetInfo::ConstraintInfo &info) const override { 6874 return true; 6875 } 6876 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6877 return None; 6878 } 6879 }; 6880 6881 class MipsTargetInfoBase : public TargetInfo { 6882 virtual void setDataLayout() = 0; 6883 6884 static const Builtin::Info BuiltinInfo[]; 6885 std::string CPU; 6886 bool IsMips16; 6887 bool IsMicromips; 6888 bool IsNan2008; 6889 bool IsSingleFloat; 6890 enum MipsFloatABI { 6891 HardFloat, SoftFloat 6892 } FloatABI; 6893 enum DspRevEnum { 6894 NoDSP, DSP1, DSP2 6895 } DspRev; 6896 bool HasMSA; 6897 6898 protected: 6899 bool HasFP64; 6900 std::string ABI; 6901 6902 public: 6903 MipsTargetInfoBase(const llvm::Triple &Triple, const TargetOptions &, 6904 const std::string &ABIStr, const std::string &CPUStr) 6905 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6906 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6907 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6908 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6909 } 6910 6911 bool isNaN2008Default() const { 6912 return CPU == "mips32r6" || CPU == "mips64r6"; 6913 } 6914 6915 bool isFP64Default() const { 6916 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6917 } 6918 6919 bool isNan2008() const override { 6920 return IsNan2008; 6921 } 6922 6923 StringRef getABI() const override { return ABI; } 6924 bool setCPU(const std::string &Name) override { 6925 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6926 getTriple().getArch() == llvm::Triple::mipsel; 6927 CPU = Name; 6928 return llvm::StringSwitch<bool>(Name) 6929 .Case("mips1", IsMips32) 6930 .Case("mips2", IsMips32) 6931 .Case("mips3", true) 6932 .Case("mips4", true) 6933 .Case("mips5", true) 6934 .Case("mips32", IsMips32) 6935 .Case("mips32r2", IsMips32) 6936 .Case("mips32r3", IsMips32) 6937 .Case("mips32r5", IsMips32) 6938 .Case("mips32r6", IsMips32) 6939 .Case("mips64", true) 6940 .Case("mips64r2", true) 6941 .Case("mips64r3", true) 6942 .Case("mips64r5", true) 6943 .Case("mips64r6", true) 6944 .Case("octeon", true) 6945 .Case("p5600", true) 6946 .Default(false); 6947 } 6948 const std::string& getCPU() const { return CPU; } 6949 bool 6950 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6951 StringRef CPU, 6952 const std::vector<std::string> &FeaturesVec) const override { 6953 if (CPU.empty()) 6954 CPU = getCPU(); 6955 if (CPU == "octeon") 6956 Features["mips64r2"] = Features["cnmips"] = true; 6957 else 6958 Features[CPU] = true; 6959 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6960 } 6961 6962 void getTargetDefines(const LangOptions &Opts, 6963 MacroBuilder &Builder) const override { 6964 Builder.defineMacro("__mips__"); 6965 Builder.defineMacro("_mips"); 6966 if (Opts.GNUMode) 6967 Builder.defineMacro("mips"); 6968 6969 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6970 6971 switch (FloatABI) { 6972 case HardFloat: 6973 Builder.defineMacro("__mips_hard_float", Twine(1)); 6974 break; 6975 case SoftFloat: 6976 Builder.defineMacro("__mips_soft_float", Twine(1)); 6977 break; 6978 } 6979 6980 if (IsSingleFloat) 6981 Builder.defineMacro("__mips_single_float", Twine(1)); 6982 6983 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6984 Builder.defineMacro("_MIPS_FPSET", 6985 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6986 6987 if (IsMips16) 6988 Builder.defineMacro("__mips16", Twine(1)); 6989 6990 if (IsMicromips) 6991 Builder.defineMacro("__mips_micromips", Twine(1)); 6992 6993 if (IsNan2008) 6994 Builder.defineMacro("__mips_nan2008", Twine(1)); 6995 6996 switch (DspRev) { 6997 default: 6998 break; 6999 case DSP1: 7000 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7001 Builder.defineMacro("__mips_dsp", Twine(1)); 7002 break; 7003 case DSP2: 7004 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7005 Builder.defineMacro("__mips_dspr2", Twine(1)); 7006 Builder.defineMacro("__mips_dsp", Twine(1)); 7007 break; 7008 } 7009 7010 if (HasMSA) 7011 Builder.defineMacro("__mips_msa", Twine(1)); 7012 7013 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7014 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7015 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7016 7017 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7018 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7019 7020 // These shouldn't be defined for MIPS-I but there's no need to check 7021 // for that since MIPS-I isn't supported. 7022 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7023 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7024 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7025 } 7026 7027 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7028 return llvm::makeArrayRef(BuiltinInfo, 7029 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7030 } 7031 bool hasFeature(StringRef Feature) const override { 7032 return llvm::StringSwitch<bool>(Feature) 7033 .Case("mips", true) 7034 .Case("fp64", HasFP64) 7035 .Default(false); 7036 } 7037 BuiltinVaListKind getBuiltinVaListKind() const override { 7038 return TargetInfo::VoidPtrBuiltinVaList; 7039 } 7040 ArrayRef<const char *> getGCCRegNames() const override { 7041 static const char *const GCCRegNames[] = { 7042 // CPU register names 7043 // Must match second column of GCCRegAliases 7044 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7045 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7046 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7047 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7048 // Floating point register names 7049 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7050 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7051 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7052 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7053 // Hi/lo and condition register names 7054 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7055 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7056 "$ac3hi","$ac3lo", 7057 // MSA register names 7058 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7059 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7060 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7061 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7062 // MSA control register names 7063 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7064 "$msarequest", "$msamap", "$msaunmap" 7065 }; 7066 return llvm::makeArrayRef(GCCRegNames); 7067 } 7068 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override = 0; 7069 bool validateAsmConstraint(const char *&Name, 7070 TargetInfo::ConstraintInfo &Info) const override { 7071 switch (*Name) { 7072 default: 7073 return false; 7074 case 'r': // CPU registers. 7075 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7076 case 'y': // Equivalent to "r", backward compatibility only. 7077 case 'f': // floating-point registers. 7078 case 'c': // $25 for indirect jumps 7079 case 'l': // lo register 7080 case 'x': // hilo register pair 7081 Info.setAllowsRegister(); 7082 return true; 7083 case 'I': // Signed 16-bit constant 7084 case 'J': // Integer 0 7085 case 'K': // Unsigned 16-bit constant 7086 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7087 case 'M': // Constants not loadable via lui, addiu, or ori 7088 case 'N': // Constant -1 to -65535 7089 case 'O': // A signed 15-bit constant 7090 case 'P': // A constant between 1 go 65535 7091 return true; 7092 case 'R': // An address that can be used in a non-macro load or store 7093 Info.setAllowsMemory(); 7094 return true; 7095 case 'Z': 7096 if (Name[1] == 'C') { // An address usable by ll, and sc. 7097 Info.setAllowsMemory(); 7098 Name++; // Skip over 'Z'. 7099 return true; 7100 } 7101 return false; 7102 } 7103 } 7104 7105 std::string convertConstraint(const char *&Constraint) const override { 7106 std::string R; 7107 switch (*Constraint) { 7108 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7109 if (Constraint[1] == 'C') { 7110 R = std::string("^") + std::string(Constraint, 2); 7111 Constraint++; 7112 return R; 7113 } 7114 break; 7115 } 7116 return TargetInfo::convertConstraint(Constraint); 7117 } 7118 7119 const char *getClobbers() const override { 7120 // In GCC, $1 is not widely used in generated code (it's used only in a few 7121 // specific situations), so there is no real need for users to add it to 7122 // the clobbers list if they want to use it in their inline assembly code. 7123 // 7124 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7125 // code generation, so using it in inline assembly without adding it to the 7126 // clobbers list can cause conflicts between the inline assembly code and 7127 // the surrounding generated code. 7128 // 7129 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7130 // operands, which will conflict with the ".set at" assembler option (which 7131 // we use only for inline assembly, in order to maintain compatibility with 7132 // GCC) and will also conflict with the user's usage of $1. 7133 // 7134 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7135 // register for generated code is to automatically clobber $1 for all inline 7136 // assembly code. 7137 // 7138 // FIXME: We should automatically clobber $1 only for inline assembly code 7139 // which actually uses it. This would allow LLVM to use $1 for inline 7140 // assembly operands if the user's assembly code doesn't use it. 7141 return "~{$1}"; 7142 } 7143 7144 bool handleTargetFeatures(std::vector<std::string> &Features, 7145 DiagnosticsEngine &Diags) override { 7146 IsMips16 = false; 7147 IsMicromips = false; 7148 IsNan2008 = isNaN2008Default(); 7149 IsSingleFloat = false; 7150 FloatABI = HardFloat; 7151 DspRev = NoDSP; 7152 HasFP64 = isFP64Default(); 7153 7154 for (const auto &Feature : Features) { 7155 if (Feature == "+single-float") 7156 IsSingleFloat = true; 7157 else if (Feature == "+soft-float") 7158 FloatABI = SoftFloat; 7159 else if (Feature == "+mips16") 7160 IsMips16 = true; 7161 else if (Feature == "+micromips") 7162 IsMicromips = true; 7163 else if (Feature == "+dsp") 7164 DspRev = std::max(DspRev, DSP1); 7165 else if (Feature == "+dspr2") 7166 DspRev = std::max(DspRev, DSP2); 7167 else if (Feature == "+msa") 7168 HasMSA = true; 7169 else if (Feature == "+fp64") 7170 HasFP64 = true; 7171 else if (Feature == "-fp64") 7172 HasFP64 = false; 7173 else if (Feature == "+nan2008") 7174 IsNan2008 = true; 7175 else if (Feature == "-nan2008") 7176 IsNan2008 = false; 7177 } 7178 7179 setDataLayout(); 7180 7181 return true; 7182 } 7183 7184 int getEHDataRegisterNumber(unsigned RegNo) const override { 7185 if (RegNo == 0) return 4; 7186 if (RegNo == 1) return 5; 7187 return -1; 7188 } 7189 7190 bool isCLZForZeroUndef() const override { return false; } 7191 }; 7192 7193 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 7194 #define BUILTIN(ID, TYPE, ATTRS) \ 7195 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7196 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7197 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7198 #include "clang/Basic/BuiltinsMips.def" 7199 }; 7200 7201 class Mips32TargetInfoBase : public MipsTargetInfoBase { 7202 public: 7203 Mips32TargetInfoBase(const llvm::Triple &Triple, const TargetOptions &Opts) 7204 : MipsTargetInfoBase(Triple, Opts, "o32", "mips32r2") { 7205 SizeType = UnsignedInt; 7206 PtrDiffType = SignedInt; 7207 Int64Type = SignedLongLong; 7208 IntMaxType = Int64Type; 7209 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7210 } 7211 bool setABI(const std::string &Name) override { 7212 if (Name == "o32" || Name == "eabi") { 7213 ABI = Name; 7214 return true; 7215 } 7216 return false; 7217 } 7218 void getTargetDefines(const LangOptions &Opts, 7219 MacroBuilder &Builder) const override { 7220 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 7221 7222 Builder.defineMacro("__mips", "32"); 7223 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7224 7225 const std::string& CPUStr = getCPU(); 7226 if (CPUStr == "mips32") 7227 Builder.defineMacro("__mips_isa_rev", "1"); 7228 else if (CPUStr == "mips32r2") 7229 Builder.defineMacro("__mips_isa_rev", "2"); 7230 else if (CPUStr == "mips32r3") 7231 Builder.defineMacro("__mips_isa_rev", "3"); 7232 else if (CPUStr == "mips32r5") 7233 Builder.defineMacro("__mips_isa_rev", "5"); 7234 else if (CPUStr == "mips32r6") 7235 Builder.defineMacro("__mips_isa_rev", "6"); 7236 7237 if (ABI == "o32") { 7238 Builder.defineMacro("__mips_o32"); 7239 Builder.defineMacro("_ABIO32", "1"); 7240 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7241 } 7242 else if (ABI == "eabi") 7243 Builder.defineMacro("__mips_eabi"); 7244 else 7245 llvm_unreachable("Invalid ABI for Mips32."); 7246 } 7247 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7248 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 7249 { { "at" }, "$1" }, 7250 { { "v0" }, "$2" }, 7251 { { "v1" }, "$3" }, 7252 { { "a0" }, "$4" }, 7253 { { "a1" }, "$5" }, 7254 { { "a2" }, "$6" }, 7255 { { "a3" }, "$7" }, 7256 { { "t0" }, "$8" }, 7257 { { "t1" }, "$9" }, 7258 { { "t2" }, "$10" }, 7259 { { "t3" }, "$11" }, 7260 { { "t4" }, "$12" }, 7261 { { "t5" }, "$13" }, 7262 { { "t6" }, "$14" }, 7263 { { "t7" }, "$15" }, 7264 { { "s0" }, "$16" }, 7265 { { "s1" }, "$17" }, 7266 { { "s2" }, "$18" }, 7267 { { "s3" }, "$19" }, 7268 { { "s4" }, "$20" }, 7269 { { "s5" }, "$21" }, 7270 { { "s6" }, "$22" }, 7271 { { "s7" }, "$23" }, 7272 { { "t8" }, "$24" }, 7273 { { "t9" }, "$25" }, 7274 { { "k0" }, "$26" }, 7275 { { "k1" }, "$27" }, 7276 { { "gp" }, "$28" }, 7277 { { "sp","$sp" }, "$29" }, 7278 { { "fp","$fp" }, "$30" }, 7279 { { "ra" }, "$31" } 7280 }; 7281 return llvm::makeArrayRef(GCCRegAliases); 7282 } 7283 }; 7284 7285 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 7286 void setDataLayout() override { 7287 resetDataLayout("E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"); 7288 } 7289 7290 public: 7291 Mips32EBTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7292 : Mips32TargetInfoBase(Triple, Opts) { 7293 } 7294 void getTargetDefines(const LangOptions &Opts, 7295 MacroBuilder &Builder) const override { 7296 DefineStd(Builder, "MIPSEB", Opts); 7297 Builder.defineMacro("_MIPSEB"); 7298 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 7299 } 7300 }; 7301 7302 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 7303 void setDataLayout() override { 7304 resetDataLayout("e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"); 7305 } 7306 7307 public: 7308 Mips32ELTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7309 : Mips32TargetInfoBase(Triple, Opts) { 7310 BigEndian = false; 7311 } 7312 void getTargetDefines(const LangOptions &Opts, 7313 MacroBuilder &Builder) const override { 7314 DefineStd(Builder, "MIPSEL", Opts); 7315 Builder.defineMacro("_MIPSEL"); 7316 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 7317 } 7318 }; 7319 7320 class Mips64TargetInfoBase : public MipsTargetInfoBase { 7321 public: 7322 Mips64TargetInfoBase(const llvm::Triple &Triple, const TargetOptions &Opts) 7323 : MipsTargetInfoBase(Triple, Opts, "n64", "mips64r2") { 7324 LongDoubleWidth = LongDoubleAlign = 128; 7325 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7326 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7327 LongDoubleWidth = LongDoubleAlign = 64; 7328 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7329 } 7330 setN64ABITypes(); 7331 SuitableAlign = 128; 7332 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7333 } 7334 7335 void setN64ABITypes() { 7336 LongWidth = LongAlign = 64; 7337 PointerWidth = PointerAlign = 64; 7338 SizeType = UnsignedLong; 7339 PtrDiffType = SignedLong; 7340 Int64Type = SignedLong; 7341 IntMaxType = Int64Type; 7342 } 7343 7344 void setN32ABITypes() { 7345 LongWidth = LongAlign = 32; 7346 PointerWidth = PointerAlign = 32; 7347 SizeType = UnsignedInt; 7348 PtrDiffType = SignedInt; 7349 Int64Type = SignedLongLong; 7350 IntMaxType = Int64Type; 7351 } 7352 7353 bool setABI(const std::string &Name) override { 7354 if (Name == "n32") { 7355 setN32ABITypes(); 7356 ABI = Name; 7357 return true; 7358 } 7359 if (Name == "n64") { 7360 setN64ABITypes(); 7361 ABI = Name; 7362 return true; 7363 } 7364 return false; 7365 } 7366 7367 void getTargetDefines(const LangOptions &Opts, 7368 MacroBuilder &Builder) const override { 7369 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 7370 7371 Builder.defineMacro("__mips", "64"); 7372 Builder.defineMacro("__mips64"); 7373 Builder.defineMacro("__mips64__"); 7374 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7375 7376 const std::string& CPUStr = getCPU(); 7377 if (CPUStr == "mips64") 7378 Builder.defineMacro("__mips_isa_rev", "1"); 7379 else if (CPUStr == "mips64r2") 7380 Builder.defineMacro("__mips_isa_rev", "2"); 7381 else if (CPUStr == "mips64r3") 7382 Builder.defineMacro("__mips_isa_rev", "3"); 7383 else if (CPUStr == "mips64r5") 7384 Builder.defineMacro("__mips_isa_rev", "5"); 7385 else if (CPUStr == "mips64r6") 7386 Builder.defineMacro("__mips_isa_rev", "6"); 7387 7388 if (ABI == "n32") { 7389 Builder.defineMacro("__mips_n32"); 7390 Builder.defineMacro("_ABIN32", "2"); 7391 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7392 } 7393 else if (ABI == "n64") { 7394 Builder.defineMacro("__mips_n64"); 7395 Builder.defineMacro("_ABI64", "3"); 7396 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7397 } 7398 else 7399 llvm_unreachable("Invalid ABI for Mips64."); 7400 7401 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7402 } 7403 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7404 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 7405 { { "at" }, "$1" }, 7406 { { "v0" }, "$2" }, 7407 { { "v1" }, "$3" }, 7408 { { "a0" }, "$4" }, 7409 { { "a1" }, "$5" }, 7410 { { "a2" }, "$6" }, 7411 { { "a3" }, "$7" }, 7412 { { "a4" }, "$8" }, 7413 { { "a5" }, "$9" }, 7414 { { "a6" }, "$10" }, 7415 { { "a7" }, "$11" }, 7416 { { "t0" }, "$12" }, 7417 { { "t1" }, "$13" }, 7418 { { "t2" }, "$14" }, 7419 { { "t3" }, "$15" }, 7420 { { "s0" }, "$16" }, 7421 { { "s1" }, "$17" }, 7422 { { "s2" }, "$18" }, 7423 { { "s3" }, "$19" }, 7424 { { "s4" }, "$20" }, 7425 { { "s5" }, "$21" }, 7426 { { "s6" }, "$22" }, 7427 { { "s7" }, "$23" }, 7428 { { "t8" }, "$24" }, 7429 { { "t9" }, "$25" }, 7430 { { "k0" }, "$26" }, 7431 { { "k1" }, "$27" }, 7432 { { "gp" }, "$28" }, 7433 { { "sp","$sp" }, "$29" }, 7434 { { "fp","$fp" }, "$30" }, 7435 { { "ra" }, "$31" } 7436 }; 7437 return llvm::makeArrayRef(GCCRegAliases); 7438 } 7439 7440 bool hasInt128Type() const override { return true; } 7441 }; 7442 7443 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 7444 void setDataLayout() override { 7445 if (ABI == "n32") 7446 resetDataLayout("E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7447 else 7448 resetDataLayout("E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7449 } 7450 7451 public: 7452 Mips64EBTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7453 : Mips64TargetInfoBase(Triple, Opts) {} 7454 void getTargetDefines(const LangOptions &Opts, 7455 MacroBuilder &Builder) const override { 7456 DefineStd(Builder, "MIPSEB", Opts); 7457 Builder.defineMacro("_MIPSEB"); 7458 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7459 } 7460 }; 7461 7462 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 7463 void setDataLayout() override { 7464 if (ABI == "n32") 7465 resetDataLayout("e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7466 else 7467 resetDataLayout("e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7468 } 7469 public: 7470 Mips64ELTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7471 : Mips64TargetInfoBase(Triple, Opts) { 7472 // Default ABI is n64. 7473 BigEndian = false; 7474 } 7475 void getTargetDefines(const LangOptions &Opts, 7476 MacroBuilder &Builder) const override { 7477 DefineStd(Builder, "MIPSEL", Opts); 7478 Builder.defineMacro("_MIPSEL"); 7479 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7480 } 7481 }; 7482 7483 class PNaClTargetInfo : public TargetInfo { 7484 public: 7485 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7486 : TargetInfo(Triple) { 7487 BigEndian = false; 7488 this->LongAlign = 32; 7489 this->LongWidth = 32; 7490 this->PointerAlign = 32; 7491 this->PointerWidth = 32; 7492 this->IntMaxType = TargetInfo::SignedLongLong; 7493 this->Int64Type = TargetInfo::SignedLongLong; 7494 this->DoubleAlign = 64; 7495 this->LongDoubleWidth = 64; 7496 this->LongDoubleAlign = 64; 7497 this->SizeType = TargetInfo::UnsignedInt; 7498 this->PtrDiffType = TargetInfo::SignedInt; 7499 this->IntPtrType = TargetInfo::SignedInt; 7500 this->RegParmMax = 0; // Disallow regparm 7501 } 7502 7503 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7504 Builder.defineMacro("__le32__"); 7505 Builder.defineMacro("__pnacl__"); 7506 } 7507 void getTargetDefines(const LangOptions &Opts, 7508 MacroBuilder &Builder) const override { 7509 getArchDefines(Opts, Builder); 7510 } 7511 bool hasFeature(StringRef Feature) const override { 7512 return Feature == "pnacl"; 7513 } 7514 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7515 BuiltinVaListKind getBuiltinVaListKind() const override { 7516 return TargetInfo::PNaClABIBuiltinVaList; 7517 } 7518 ArrayRef<const char *> getGCCRegNames() const override; 7519 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7520 bool validateAsmConstraint(const char *&Name, 7521 TargetInfo::ConstraintInfo &Info) const override { 7522 return false; 7523 } 7524 7525 const char *getClobbers() const override { 7526 return ""; 7527 } 7528 }; 7529 7530 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7531 return None; 7532 } 7533 7534 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7535 return None; 7536 } 7537 7538 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7539 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 7540 public: 7541 NaClMips32ELTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7542 : Mips32ELTargetInfo(Triple, Opts) {} 7543 7544 BuiltinVaListKind getBuiltinVaListKind() const override { 7545 return TargetInfo::PNaClABIBuiltinVaList; 7546 } 7547 }; 7548 7549 class Le64TargetInfo : public TargetInfo { 7550 static const Builtin::Info BuiltinInfo[]; 7551 7552 public: 7553 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7554 : TargetInfo(Triple) { 7555 BigEndian = false; 7556 NoAsmVariants = true; 7557 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7558 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7559 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 7560 } 7561 7562 void getTargetDefines(const LangOptions &Opts, 7563 MacroBuilder &Builder) const override { 7564 DefineStd(Builder, "unix", Opts); 7565 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7566 Builder.defineMacro("__ELF__"); 7567 } 7568 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7569 return llvm::makeArrayRef(BuiltinInfo, 7570 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7571 } 7572 BuiltinVaListKind getBuiltinVaListKind() const override { 7573 return TargetInfo::PNaClABIBuiltinVaList; 7574 } 7575 const char *getClobbers() const override { return ""; } 7576 ArrayRef<const char *> getGCCRegNames() const override { 7577 return None; 7578 } 7579 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7580 return None; 7581 } 7582 bool validateAsmConstraint(const char *&Name, 7583 TargetInfo::ConstraintInfo &Info) const override { 7584 return false; 7585 } 7586 7587 bool hasProtectedVisibility() const override { return false; } 7588 }; 7589 7590 class WebAssemblyTargetInfo : public TargetInfo { 7591 static const Builtin::Info BuiltinInfo[]; 7592 7593 enum SIMDEnum { 7594 NoSIMD, 7595 SIMD128, 7596 } SIMDLevel; 7597 7598 public: 7599 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 7600 : TargetInfo(T), SIMDLevel(NoSIMD) { 7601 BigEndian = false; 7602 NoAsmVariants = true; 7603 SuitableAlign = 128; 7604 LargeArrayMinWidth = 128; 7605 LargeArrayAlign = 128; 7606 SimdDefaultAlign = 128; 7607 SigAtomicType = SignedLong; 7608 LongDoubleWidth = LongDoubleAlign = 128; 7609 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7610 } 7611 7612 protected: 7613 void getTargetDefines(const LangOptions &Opts, 7614 MacroBuilder &Builder) const override { 7615 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7616 if (SIMDLevel >= SIMD128) 7617 Builder.defineMacro("__wasm_simd128__"); 7618 } 7619 7620 private: 7621 bool 7622 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7623 StringRef CPU, 7624 const std::vector<std::string> &FeaturesVec) const override { 7625 if (CPU == "bleeding-edge") 7626 Features["simd128"] = true; 7627 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7628 } 7629 bool hasFeature(StringRef Feature) const final { 7630 return llvm::StringSwitch<bool>(Feature) 7631 .Case("simd128", SIMDLevel >= SIMD128) 7632 .Default(false); 7633 } 7634 bool handleTargetFeatures(std::vector<std::string> &Features, 7635 DiagnosticsEngine &Diags) final { 7636 for (const auto &Feature : Features) { 7637 if (Feature == "+simd128") { 7638 SIMDLevel = std::max(SIMDLevel, SIMD128); 7639 continue; 7640 } 7641 if (Feature == "-simd128") { 7642 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7643 continue; 7644 } 7645 7646 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7647 << "-target-feature"; 7648 return false; 7649 } 7650 return true; 7651 } 7652 bool setCPU(const std::string &Name) final { 7653 return llvm::StringSwitch<bool>(Name) 7654 .Case("mvp", true) 7655 .Case("bleeding-edge", true) 7656 .Case("generic", true) 7657 .Default(false); 7658 } 7659 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7660 return llvm::makeArrayRef(BuiltinInfo, 7661 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7662 } 7663 BuiltinVaListKind getBuiltinVaListKind() const final { 7664 return VoidPtrBuiltinVaList; 7665 } 7666 ArrayRef<const char *> getGCCRegNames() const final { 7667 return None; 7668 } 7669 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7670 return None; 7671 } 7672 bool 7673 validateAsmConstraint(const char *&Name, 7674 TargetInfo::ConstraintInfo &Info) const final { 7675 return false; 7676 } 7677 const char *getClobbers() const final { return ""; } 7678 bool isCLZForZeroUndef() const final { return false; } 7679 bool hasInt128Type() const final { return true; } 7680 IntType getIntTypeByWidth(unsigned BitWidth, 7681 bool IsSigned) const final { 7682 // WebAssembly prefers long long for explicitly 64-bit integers. 7683 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7684 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7685 } 7686 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7687 bool IsSigned) const final { 7688 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7689 return BitWidth == 64 7690 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7691 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7692 } 7693 }; 7694 7695 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7696 #define BUILTIN(ID, TYPE, ATTRS) \ 7697 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7698 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7699 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7700 #include "clang/Basic/BuiltinsWebAssembly.def" 7701 }; 7702 7703 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7704 public: 7705 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 7706 const TargetOptions &Opts) 7707 : WebAssemblyTargetInfo(T, Opts) { 7708 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7709 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 7710 } 7711 7712 protected: 7713 void getTargetDefines(const LangOptions &Opts, 7714 MacroBuilder &Builder) const override { 7715 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7716 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7717 } 7718 }; 7719 7720 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7721 public: 7722 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 7723 const TargetOptions &Opts) 7724 : WebAssemblyTargetInfo(T, Opts) { 7725 LongAlign = LongWidth = 64; 7726 PointerAlign = PointerWidth = 64; 7727 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7728 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7729 } 7730 7731 protected: 7732 void getTargetDefines(const LangOptions &Opts, 7733 MacroBuilder &Builder) const override { 7734 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7735 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7736 } 7737 }; 7738 7739 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7740 #define BUILTIN(ID, TYPE, ATTRS) \ 7741 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7742 #include "clang/Basic/BuiltinsLe64.def" 7743 }; 7744 7745 static const unsigned SPIRAddrSpaceMap[] = { 7746 1, // opencl_global 7747 3, // opencl_local 7748 2, // opencl_constant 7749 4, // opencl_generic 7750 0, // cuda_device 7751 0, // cuda_constant 7752 0 // cuda_shared 7753 }; 7754 class SPIRTargetInfo : public TargetInfo { 7755 public: 7756 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7757 : TargetInfo(Triple) { 7758 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7759 "SPIR target must use unknown OS"); 7760 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7761 "SPIR target must use unknown environment type"); 7762 BigEndian = false; 7763 TLSSupported = false; 7764 LongWidth = LongAlign = 64; 7765 AddrSpaceMap = &SPIRAddrSpaceMap; 7766 UseAddrSpaceMapMangling = true; 7767 // Define available target features 7768 // These must be defined in sorted order! 7769 NoAsmVariants = true; 7770 } 7771 void getTargetDefines(const LangOptions &Opts, 7772 MacroBuilder &Builder) const override { 7773 DefineStd(Builder, "SPIR", Opts); 7774 } 7775 bool hasFeature(StringRef Feature) const override { 7776 return Feature == "spir"; 7777 } 7778 7779 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7780 const char *getClobbers() const override { return ""; } 7781 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7782 bool validateAsmConstraint(const char *&Name, 7783 TargetInfo::ConstraintInfo &info) const override { 7784 return true; 7785 } 7786 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7787 return None; 7788 } 7789 BuiltinVaListKind getBuiltinVaListKind() const override { 7790 return TargetInfo::VoidPtrBuiltinVaList; 7791 } 7792 7793 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7794 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK 7795 : CCCR_Warning; 7796 } 7797 7798 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7799 return CC_SpirFunction; 7800 } 7801 }; 7802 7803 class SPIR32TargetInfo : public SPIRTargetInfo { 7804 public: 7805 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7806 : SPIRTargetInfo(Triple, Opts) { 7807 PointerWidth = PointerAlign = 32; 7808 SizeType = TargetInfo::UnsignedInt; 7809 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7810 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7811 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7812 } 7813 void getTargetDefines(const LangOptions &Opts, 7814 MacroBuilder &Builder) const override { 7815 DefineStd(Builder, "SPIR32", Opts); 7816 } 7817 }; 7818 7819 class SPIR64TargetInfo : public SPIRTargetInfo { 7820 public: 7821 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7822 : SPIRTargetInfo(Triple, Opts) { 7823 PointerWidth = PointerAlign = 64; 7824 SizeType = TargetInfo::UnsignedLong; 7825 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7826 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7827 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7828 } 7829 void getTargetDefines(const LangOptions &Opts, 7830 MacroBuilder &Builder) const override { 7831 DefineStd(Builder, "SPIR64", Opts); 7832 } 7833 }; 7834 7835 class XCoreTargetInfo : public TargetInfo { 7836 static const Builtin::Info BuiltinInfo[]; 7837 public: 7838 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7839 : TargetInfo(Triple) { 7840 BigEndian = false; 7841 NoAsmVariants = true; 7842 LongLongAlign = 32; 7843 SuitableAlign = 32; 7844 DoubleAlign = LongDoubleAlign = 32; 7845 SizeType = UnsignedInt; 7846 PtrDiffType = SignedInt; 7847 IntPtrType = SignedInt; 7848 WCharType = UnsignedChar; 7849 WIntType = UnsignedInt; 7850 UseZeroLengthBitfieldAlignment = true; 7851 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7852 "-f64:32-a:0:32-n32"); 7853 } 7854 void getTargetDefines(const LangOptions &Opts, 7855 MacroBuilder &Builder) const override { 7856 Builder.defineMacro("__XS1B__"); 7857 } 7858 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7859 return llvm::makeArrayRef(BuiltinInfo, 7860 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 7861 } 7862 BuiltinVaListKind getBuiltinVaListKind() const override { 7863 return TargetInfo::VoidPtrBuiltinVaList; 7864 } 7865 const char *getClobbers() const override { 7866 return ""; 7867 } 7868 ArrayRef<const char *> getGCCRegNames() const override { 7869 static const char * const GCCRegNames[] = { 7870 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7871 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 7872 }; 7873 return llvm::makeArrayRef(GCCRegNames); 7874 } 7875 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7876 return None; 7877 } 7878 bool validateAsmConstraint(const char *&Name, 7879 TargetInfo::ConstraintInfo &Info) const override { 7880 return false; 7881 } 7882 int getEHDataRegisterNumber(unsigned RegNo) const override { 7883 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7884 return (RegNo < 2)? RegNo : -1; 7885 } 7886 bool allowsLargerPreferedTypeAlignment() const override { 7887 return false; 7888 } 7889 }; 7890 7891 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7892 #define BUILTIN(ID, TYPE, ATTRS) \ 7893 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7894 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7895 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7896 #include "clang/Basic/BuiltinsXCore.def" 7897 }; 7898 7899 // x86_32 Android target 7900 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7901 public: 7902 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7903 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 7904 SuitableAlign = 32; 7905 LongDoubleWidth = 64; 7906 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7907 } 7908 }; 7909 7910 // x86_64 Android target 7911 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7912 public: 7913 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7914 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 7915 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7916 } 7917 7918 bool useFloat128ManglingForLongDouble() const override { 7919 return true; 7920 } 7921 }; 7922 } // end anonymous namespace 7923 7924 //===----------------------------------------------------------------------===// 7925 // Driver code 7926 //===----------------------------------------------------------------------===// 7927 7928 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 7929 const TargetOptions &Opts) { 7930 llvm::Triple::OSType os = Triple.getOS(); 7931 7932 switch (Triple.getArch()) { 7933 default: 7934 return nullptr; 7935 7936 case llvm::Triple::xcore: 7937 return new XCoreTargetInfo(Triple, Opts); 7938 7939 case llvm::Triple::hexagon: 7940 return new HexagonTargetInfo(Triple, Opts); 7941 7942 case llvm::Triple::lanai: 7943 return new LanaiTargetInfo(Triple, Opts); 7944 7945 case llvm::Triple::aarch64: 7946 if (Triple.isOSDarwin()) 7947 return new DarwinAArch64TargetInfo(Triple, Opts); 7948 7949 switch (os) { 7950 case llvm::Triple::CloudABI: 7951 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 7952 case llvm::Triple::FreeBSD: 7953 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 7954 case llvm::Triple::Linux: 7955 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 7956 case llvm::Triple::NetBSD: 7957 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 7958 default: 7959 return new AArch64leTargetInfo(Triple, Opts); 7960 } 7961 7962 case llvm::Triple::aarch64_be: 7963 switch (os) { 7964 case llvm::Triple::FreeBSD: 7965 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 7966 case llvm::Triple::Linux: 7967 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 7968 case llvm::Triple::NetBSD: 7969 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 7970 default: 7971 return new AArch64beTargetInfo(Triple, Opts); 7972 } 7973 7974 case llvm::Triple::arm: 7975 case llvm::Triple::thumb: 7976 if (Triple.isOSBinFormatMachO()) 7977 return new DarwinARMTargetInfo(Triple, Opts); 7978 7979 switch (os) { 7980 case llvm::Triple::Linux: 7981 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 7982 case llvm::Triple::FreeBSD: 7983 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 7984 case llvm::Triple::NetBSD: 7985 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 7986 case llvm::Triple::OpenBSD: 7987 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 7988 case llvm::Triple::Bitrig: 7989 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 7990 case llvm::Triple::RTEMS: 7991 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 7992 case llvm::Triple::NaCl: 7993 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 7994 case llvm::Triple::Win32: 7995 switch (Triple.getEnvironment()) { 7996 case llvm::Triple::Cygnus: 7997 return new CygwinARMTargetInfo(Triple, Opts); 7998 case llvm::Triple::GNU: 7999 return new MinGWARMTargetInfo(Triple, Opts); 8000 case llvm::Triple::Itanium: 8001 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 8002 case llvm::Triple::MSVC: 8003 default: // Assume MSVC for unknown environments 8004 return new MicrosoftARMleTargetInfo(Triple, Opts); 8005 } 8006 default: 8007 return new ARMleTargetInfo(Triple, Opts); 8008 } 8009 8010 case llvm::Triple::armeb: 8011 case llvm::Triple::thumbeb: 8012 if (Triple.isOSDarwin()) 8013 return new DarwinARMTargetInfo(Triple, Opts); 8014 8015 switch (os) { 8016 case llvm::Triple::Linux: 8017 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8018 case llvm::Triple::FreeBSD: 8019 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8020 case llvm::Triple::NetBSD: 8021 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8022 case llvm::Triple::OpenBSD: 8023 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8024 case llvm::Triple::Bitrig: 8025 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8026 case llvm::Triple::RTEMS: 8027 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8028 case llvm::Triple::NaCl: 8029 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8030 default: 8031 return new ARMbeTargetInfo(Triple, Opts); 8032 } 8033 8034 case llvm::Triple::bpfeb: 8035 case llvm::Triple::bpfel: 8036 return new BPFTargetInfo(Triple, Opts); 8037 8038 case llvm::Triple::msp430: 8039 return new MSP430TargetInfo(Triple, Opts); 8040 8041 case llvm::Triple::mips: 8042 switch (os) { 8043 case llvm::Triple::Linux: 8044 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple, Opts); 8045 case llvm::Triple::RTEMS: 8046 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple, Opts); 8047 case llvm::Triple::FreeBSD: 8048 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple, Opts); 8049 case llvm::Triple::NetBSD: 8050 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple, Opts); 8051 default: 8052 return new Mips32EBTargetInfo(Triple, Opts); 8053 } 8054 8055 case llvm::Triple::mipsel: 8056 switch (os) { 8057 case llvm::Triple::Linux: 8058 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple, Opts); 8059 case llvm::Triple::RTEMS: 8060 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple, Opts); 8061 case llvm::Triple::FreeBSD: 8062 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple, Opts); 8063 case llvm::Triple::NetBSD: 8064 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple, Opts); 8065 case llvm::Triple::NaCl: 8066 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple, Opts); 8067 default: 8068 return new Mips32ELTargetInfo(Triple, Opts); 8069 } 8070 8071 case llvm::Triple::mips64: 8072 switch (os) { 8073 case llvm::Triple::Linux: 8074 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 8075 case llvm::Triple::RTEMS: 8076 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 8077 case llvm::Triple::FreeBSD: 8078 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 8079 case llvm::Triple::NetBSD: 8080 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 8081 case llvm::Triple::OpenBSD: 8082 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 8083 default: 8084 return new Mips64EBTargetInfo(Triple, Opts); 8085 } 8086 8087 case llvm::Triple::mips64el: 8088 switch (os) { 8089 case llvm::Triple::Linux: 8090 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8091 case llvm::Triple::RTEMS: 8092 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8093 case llvm::Triple::FreeBSD: 8094 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8095 case llvm::Triple::NetBSD: 8096 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8097 case llvm::Triple::OpenBSD: 8098 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8099 default: 8100 return new Mips64ELTargetInfo(Triple, Opts); 8101 } 8102 8103 case llvm::Triple::le32: 8104 switch (os) { 8105 case llvm::Triple::NaCl: 8106 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 8107 default: 8108 return nullptr; 8109 } 8110 8111 case llvm::Triple::le64: 8112 return new Le64TargetInfo(Triple, Opts); 8113 8114 case llvm::Triple::ppc: 8115 if (Triple.isOSDarwin()) 8116 return new DarwinPPC32TargetInfo(Triple, Opts); 8117 switch (os) { 8118 case llvm::Triple::Linux: 8119 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 8120 case llvm::Triple::FreeBSD: 8121 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8122 case llvm::Triple::NetBSD: 8123 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8124 case llvm::Triple::OpenBSD: 8125 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8126 case llvm::Triple::RTEMS: 8127 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 8128 default: 8129 return new PPC32TargetInfo(Triple, Opts); 8130 } 8131 8132 case llvm::Triple::ppc64: 8133 if (Triple.isOSDarwin()) 8134 return new DarwinPPC64TargetInfo(Triple, Opts); 8135 switch (os) { 8136 case llvm::Triple::Linux: 8137 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8138 case llvm::Triple::Lv2: 8139 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 8140 case llvm::Triple::FreeBSD: 8141 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8142 case llvm::Triple::NetBSD: 8143 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8144 default: 8145 return new PPC64TargetInfo(Triple, Opts); 8146 } 8147 8148 case llvm::Triple::ppc64le: 8149 switch (os) { 8150 case llvm::Triple::Linux: 8151 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8152 case llvm::Triple::NetBSD: 8153 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8154 default: 8155 return new PPC64TargetInfo(Triple, Opts); 8156 } 8157 8158 case llvm::Triple::nvptx: 8159 return new NVPTX32TargetInfo(Triple, Opts); 8160 case llvm::Triple::nvptx64: 8161 return new NVPTX64TargetInfo(Triple, Opts); 8162 8163 case llvm::Triple::amdgcn: 8164 case llvm::Triple::r600: 8165 return new AMDGPUTargetInfo(Triple, Opts); 8166 8167 case llvm::Triple::sparc: 8168 switch (os) { 8169 case llvm::Triple::Linux: 8170 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8171 case llvm::Triple::Solaris: 8172 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8173 case llvm::Triple::NetBSD: 8174 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8175 case llvm::Triple::OpenBSD: 8176 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8177 case llvm::Triple::RTEMS: 8178 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8179 default: 8180 return new SparcV8TargetInfo(Triple, Opts); 8181 } 8182 8183 // The 'sparcel' architecture copies all the above cases except for Solaris. 8184 case llvm::Triple::sparcel: 8185 switch (os) { 8186 case llvm::Triple::Linux: 8187 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8188 case llvm::Triple::NetBSD: 8189 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8190 case llvm::Triple::OpenBSD: 8191 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8192 case llvm::Triple::RTEMS: 8193 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8194 default: 8195 return new SparcV8elTargetInfo(Triple, Opts); 8196 } 8197 8198 case llvm::Triple::sparcv9: 8199 switch (os) { 8200 case llvm::Triple::Linux: 8201 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8202 case llvm::Triple::Solaris: 8203 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8204 case llvm::Triple::NetBSD: 8205 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8206 case llvm::Triple::OpenBSD: 8207 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8208 case llvm::Triple::FreeBSD: 8209 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8210 default: 8211 return new SparcV9TargetInfo(Triple, Opts); 8212 } 8213 8214 case llvm::Triple::systemz: 8215 switch (os) { 8216 case llvm::Triple::Linux: 8217 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 8218 default: 8219 return new SystemZTargetInfo(Triple, Opts); 8220 } 8221 8222 case llvm::Triple::tce: 8223 return new TCETargetInfo(Triple, Opts); 8224 8225 case llvm::Triple::x86: 8226 if (Triple.isOSDarwin()) 8227 return new DarwinI386TargetInfo(Triple, Opts); 8228 8229 switch (os) { 8230 case llvm::Triple::CloudABI: 8231 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 8232 case llvm::Triple::Linux: { 8233 switch (Triple.getEnvironment()) { 8234 default: 8235 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 8236 case llvm::Triple::Android: 8237 return new AndroidX86_32TargetInfo(Triple, Opts); 8238 } 8239 } 8240 case llvm::Triple::DragonFly: 8241 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8242 case llvm::Triple::NetBSD: 8243 return new NetBSDI386TargetInfo(Triple, Opts); 8244 case llvm::Triple::OpenBSD: 8245 return new OpenBSDI386TargetInfo(Triple, Opts); 8246 case llvm::Triple::Bitrig: 8247 return new BitrigI386TargetInfo(Triple, Opts); 8248 case llvm::Triple::FreeBSD: 8249 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8250 case llvm::Triple::KFreeBSD: 8251 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8252 case llvm::Triple::Minix: 8253 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 8254 case llvm::Triple::Solaris: 8255 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 8256 case llvm::Triple::Win32: { 8257 switch (Triple.getEnvironment()) { 8258 case llvm::Triple::Cygnus: 8259 return new CygwinX86_32TargetInfo(Triple, Opts); 8260 case llvm::Triple::GNU: 8261 return new MinGWX86_32TargetInfo(Triple, Opts); 8262 case llvm::Triple::Itanium: 8263 case llvm::Triple::MSVC: 8264 default: // Assume MSVC for unknown environments 8265 return new MicrosoftX86_32TargetInfo(Triple, Opts); 8266 } 8267 } 8268 case llvm::Triple::Haiku: 8269 return new HaikuX86_32TargetInfo(Triple, Opts); 8270 case llvm::Triple::RTEMS: 8271 return new RTEMSX86_32TargetInfo(Triple, Opts); 8272 case llvm::Triple::NaCl: 8273 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 8274 case llvm::Triple::ELFIAMCU: 8275 return new MCUX86_32TargetInfo(Triple, Opts); 8276 default: 8277 return new X86_32TargetInfo(Triple, Opts); 8278 } 8279 8280 case llvm::Triple::x86_64: 8281 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 8282 return new DarwinX86_64TargetInfo(Triple, Opts); 8283 8284 switch (os) { 8285 case llvm::Triple::CloudABI: 8286 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 8287 case llvm::Triple::Linux: { 8288 switch (Triple.getEnvironment()) { 8289 default: 8290 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 8291 case llvm::Triple::Android: 8292 return new AndroidX86_64TargetInfo(Triple, Opts); 8293 } 8294 } 8295 case llvm::Triple::DragonFly: 8296 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8297 case llvm::Triple::NetBSD: 8298 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8299 case llvm::Triple::OpenBSD: 8300 return new OpenBSDX86_64TargetInfo(Triple, Opts); 8301 case llvm::Triple::Bitrig: 8302 return new BitrigX86_64TargetInfo(Triple, Opts); 8303 case llvm::Triple::FreeBSD: 8304 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8305 case llvm::Triple::KFreeBSD: 8306 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8307 case llvm::Triple::Solaris: 8308 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 8309 case llvm::Triple::Win32: { 8310 switch (Triple.getEnvironment()) { 8311 case llvm::Triple::Cygnus: 8312 return new CygwinX86_64TargetInfo(Triple, Opts); 8313 case llvm::Triple::GNU: 8314 return new MinGWX86_64TargetInfo(Triple, Opts); 8315 case llvm::Triple::MSVC: 8316 default: // Assume MSVC for unknown environments 8317 return new MicrosoftX86_64TargetInfo(Triple, Opts); 8318 } 8319 } 8320 case llvm::Triple::NaCl: 8321 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 8322 case llvm::Triple::PS4: 8323 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 8324 default: 8325 return new X86_64TargetInfo(Triple, Opts); 8326 } 8327 8328 case llvm::Triple::spir: { 8329 if (Triple.getOS() != llvm::Triple::UnknownOS || 8330 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8331 return nullptr; 8332 return new SPIR32TargetInfo(Triple, Opts); 8333 } 8334 case llvm::Triple::spir64: { 8335 if (Triple.getOS() != llvm::Triple::UnknownOS || 8336 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8337 return nullptr; 8338 return new SPIR64TargetInfo(Triple, Opts); 8339 } 8340 case llvm::Triple::wasm32: 8341 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8342 return nullptr; 8343 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 8344 case llvm::Triple::wasm64: 8345 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8346 return nullptr; 8347 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 8348 } 8349 } 8350 8351 /// CreateTargetInfo - Return the target info object for the specified target 8352 /// options. 8353 TargetInfo * 8354 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8355 const std::shared_ptr<TargetOptions> &Opts) { 8356 llvm::Triple Triple(Opts->Triple); 8357 8358 // Construct the target 8359 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 8360 if (!Target) { 8361 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8362 return nullptr; 8363 } 8364 Target->TargetOpts = Opts; 8365 8366 // Set the target CPU if specified. 8367 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8368 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8369 return nullptr; 8370 } 8371 8372 // Set the target ABI if specified. 8373 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8374 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8375 return nullptr; 8376 } 8377 8378 // Set the fp math unit. 8379 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8380 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8381 return nullptr; 8382 } 8383 8384 // Compute the default target features, we need the target to handle this 8385 // because features may have dependencies on one another. 8386 llvm::StringMap<bool> Features; 8387 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8388 Opts->FeaturesAsWritten)) 8389 return nullptr; 8390 8391 // Add the features to the compile options. 8392 Opts->Features.clear(); 8393 for (const auto &F : Features) 8394 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8395 8396 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8397 return nullptr; 8398 8399 return Target.release(); 8400 } 8401