1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "clang/Basic/Version.h" 23 #include "llvm/ADT/APFloat.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringExtras.h" 26 #include "llvm/ADT/StringRef.h" 27 #include "llvm/ADT/StringSwitch.h" 28 #include "llvm/ADT/Triple.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/TargetParser.h" 32 #include <algorithm> 33 #include <memory> 34 35 using namespace clang; 36 37 //===----------------------------------------------------------------------===// 38 // Common code shared among targets. 39 //===----------------------------------------------------------------------===// 40 41 /// DefineStd - Define a macro name and standard variants. For example if 42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 43 /// when in GNU mode. 44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 45 const LangOptions &Opts) { 46 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 47 48 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 49 // in the user's namespace. 50 if (Opts.GNUMode) 51 Builder.defineMacro(MacroName); 52 53 // Define __unix. 54 Builder.defineMacro("__" + MacroName); 55 56 // Define __unix__. 57 Builder.defineMacro("__" + MacroName + "__"); 58 } 59 60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 61 bool Tuning = true) { 62 Builder.defineMacro("__" + CPUName); 63 Builder.defineMacro("__" + CPUName + "__"); 64 if (Tuning) 65 Builder.defineMacro("__tune_" + CPUName + "__"); 66 } 67 68 //===----------------------------------------------------------------------===// 69 // Defines specific to certain operating systems. 70 //===----------------------------------------------------------------------===// 71 72 namespace { 73 template<typename TgtInfo> 74 class OSTargetInfo : public TgtInfo { 75 protected: 76 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 77 MacroBuilder &Builder) const=0; 78 public: 79 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 80 void getTargetDefines(const LangOptions &Opts, 81 MacroBuilder &Builder) const override { 82 TgtInfo::getTargetDefines(Opts, Builder); 83 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 84 } 85 86 }; 87 88 // CloudABI Target 89 template <typename Target> 90 class CloudABITargetInfo : public OSTargetInfo<Target> { 91 protected: 92 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 93 MacroBuilder &Builder) const override { 94 Builder.defineMacro("__CloudABI__"); 95 Builder.defineMacro("__ELF__"); 96 97 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 98 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 99 Builder.defineMacro("__STDC_UTF_16__"); 100 Builder.defineMacro("__STDC_UTF_32__"); 101 } 102 103 public: 104 CloudABITargetInfo(const llvm::Triple &Triple) 105 : OSTargetInfo<Target>(Triple) { 106 this->UserLabelPrefix = ""; 107 } 108 }; 109 110 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 111 const llvm::Triple &Triple, 112 StringRef &PlatformName, 113 VersionTuple &PlatformMinVersion) { 114 Builder.defineMacro("__APPLE_CC__", "6000"); 115 Builder.defineMacro("__APPLE__"); 116 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 117 // AddressSanitizer doesn't play well with source fortification, which is on 118 // by default on Darwin. 119 if (Opts.Sanitize.has(SanitizerKind::Address)) 120 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 121 122 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 123 if (!Opts.ObjC1) { 124 // __weak is always defined, for use in blocks and with objc pointers. 125 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 126 Builder.defineMacro("__strong", ""); 127 Builder.defineMacro("__unsafe_unretained", ""); 128 } 129 130 if (Opts.Static) 131 Builder.defineMacro("__STATIC__"); 132 else 133 Builder.defineMacro("__DYNAMIC__"); 134 135 if (Opts.POSIXThreads) 136 Builder.defineMacro("_REENTRANT"); 137 138 // Get the platform type and version number from the triple. 139 unsigned Maj, Min, Rev; 140 if (Triple.isMacOSX()) { 141 Triple.getMacOSXVersion(Maj, Min, Rev); 142 PlatformName = "macosx"; 143 } else { 144 Triple.getOSVersion(Maj, Min, Rev); 145 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 146 } 147 148 // If -target arch-pc-win32-macho option specified, we're 149 // generating code for Win32 ABI. No need to emit 150 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 151 if (PlatformName == "win32") { 152 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 153 return; 154 } 155 156 // Set the appropriate OS version define. 157 if (Triple.isiOS()) { 158 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 159 char Str[6]; 160 Str[0] = '0' + Maj; 161 Str[1] = '0' + (Min / 10); 162 Str[2] = '0' + (Min % 10); 163 Str[3] = '0' + (Rev / 10); 164 Str[4] = '0' + (Rev % 10); 165 Str[5] = '\0'; 166 if (Triple.isTvOS()) 167 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 168 else 169 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 170 Str); 171 172 } else if (Triple.isWatchOS()) { 173 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 174 char Str[6]; 175 Str[0] = '0' + Maj; 176 Str[1] = '0' + (Min / 10); 177 Str[2] = '0' + (Min % 10); 178 Str[3] = '0' + (Rev / 10); 179 Str[4] = '0' + (Rev % 10); 180 Str[5] = '\0'; 181 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 182 } else if (Triple.isMacOSX()) { 183 // Note that the Driver allows versions which aren't representable in the 184 // define (because we only get a single digit for the minor and micro 185 // revision numbers). So, we limit them to the maximum representable 186 // version. 187 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 188 char Str[7]; 189 if (Maj < 10 || (Maj == 10 && Min < 10)) { 190 Str[0] = '0' + (Maj / 10); 191 Str[1] = '0' + (Maj % 10); 192 Str[2] = '0' + std::min(Min, 9U); 193 Str[3] = '0' + std::min(Rev, 9U); 194 Str[4] = '\0'; 195 } else { 196 // Handle versions > 10.9. 197 Str[0] = '0' + (Maj / 10); 198 Str[1] = '0' + (Maj % 10); 199 Str[2] = '0' + (Min / 10); 200 Str[3] = '0' + (Min % 10); 201 Str[4] = '0' + (Rev / 10); 202 Str[5] = '0' + (Rev % 10); 203 Str[6] = '\0'; 204 } 205 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 206 } 207 208 // Tell users about the kernel if there is one. 209 if (Triple.isOSDarwin()) 210 Builder.defineMacro("__MACH__"); 211 212 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 213 } 214 215 template<typename Target> 216 class DarwinTargetInfo : public OSTargetInfo<Target> { 217 protected: 218 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 219 MacroBuilder &Builder) const override { 220 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 221 this->PlatformMinVersion); 222 } 223 224 public: 225 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 226 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 227 this->MCountName = "\01mcount"; 228 } 229 230 std::string isValidSectionSpecifier(StringRef SR) const override { 231 // Let MCSectionMachO validate this. 232 StringRef Segment, Section; 233 unsigned TAA, StubSize; 234 bool HasTAA; 235 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 236 TAA, HasTAA, StubSize); 237 } 238 239 const char *getStaticInitSectionSpecifier() const override { 240 // FIXME: We should return 0 when building kexts. 241 return "__TEXT,__StaticInit,regular,pure_instructions"; 242 } 243 244 /// Darwin does not support protected visibility. Darwin's "default" 245 /// is very similar to ELF's "protected"; Darwin requires a "weak" 246 /// attribute on declarations that can be dynamically replaced. 247 bool hasProtectedVisibility() const override { 248 return false; 249 } 250 }; 251 252 253 // DragonFlyBSD Target 254 template<typename Target> 255 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 256 protected: 257 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 258 MacroBuilder &Builder) const override { 259 // DragonFly defines; list based off of gcc output 260 Builder.defineMacro("__DragonFly__"); 261 Builder.defineMacro("__DragonFly_cc_version", "100001"); 262 Builder.defineMacro("__ELF__"); 263 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 264 Builder.defineMacro("__tune_i386__"); 265 DefineStd(Builder, "unix", Opts); 266 } 267 public: 268 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 269 : OSTargetInfo<Target>(Triple) { 270 this->UserLabelPrefix = ""; 271 272 switch (Triple.getArch()) { 273 default: 274 case llvm::Triple::x86: 275 case llvm::Triple::x86_64: 276 this->MCountName = ".mcount"; 277 break; 278 } 279 } 280 }; 281 282 // FreeBSD Target 283 template<typename Target> 284 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 285 protected: 286 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 287 MacroBuilder &Builder) const override { 288 // FreeBSD defines; list based off of gcc output 289 290 unsigned Release = Triple.getOSMajorVersion(); 291 if (Release == 0U) 292 Release = 8; 293 294 Builder.defineMacro("__FreeBSD__", Twine(Release)); 295 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 296 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 297 DefineStd(Builder, "unix", Opts); 298 Builder.defineMacro("__ELF__"); 299 300 // On FreeBSD, wchar_t contains the number of the code point as 301 // used by the character set of the locale. These character sets are 302 // not necessarily a superset of ASCII. 303 // 304 // FIXME: This is wrong; the macro refers to the numerical values 305 // of wchar_t *literals*, which are not locale-dependent. However, 306 // FreeBSD systems apparently depend on us getting this wrong, and 307 // setting this to 1 is conforming even if all the basic source 308 // character literals have the same encoding as char and wchar_t. 309 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 310 } 311 public: 312 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 313 this->UserLabelPrefix = ""; 314 315 switch (Triple.getArch()) { 316 default: 317 case llvm::Triple::x86: 318 case llvm::Triple::x86_64: 319 this->MCountName = ".mcount"; 320 break; 321 case llvm::Triple::mips: 322 case llvm::Triple::mipsel: 323 case llvm::Triple::ppc: 324 case llvm::Triple::ppc64: 325 case llvm::Triple::ppc64le: 326 this->MCountName = "_mcount"; 327 break; 328 case llvm::Triple::arm: 329 this->MCountName = "__mcount"; 330 break; 331 } 332 } 333 }; 334 335 // GNU/kFreeBSD Target 336 template<typename Target> 337 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 338 protected: 339 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 340 MacroBuilder &Builder) const override { 341 // GNU/kFreeBSD defines; list based off of gcc output 342 343 DefineStd(Builder, "unix", Opts); 344 Builder.defineMacro("__FreeBSD_kernel__"); 345 Builder.defineMacro("__GLIBC__"); 346 Builder.defineMacro("__ELF__"); 347 if (Opts.POSIXThreads) 348 Builder.defineMacro("_REENTRANT"); 349 if (Opts.CPlusPlus) 350 Builder.defineMacro("_GNU_SOURCE"); 351 } 352 public: 353 KFreeBSDTargetInfo(const llvm::Triple &Triple) 354 : OSTargetInfo<Target>(Triple) { 355 this->UserLabelPrefix = ""; 356 } 357 }; 358 359 // Minix Target 360 template<typename Target> 361 class MinixTargetInfo : public OSTargetInfo<Target> { 362 protected: 363 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 364 MacroBuilder &Builder) const override { 365 // Minix defines 366 367 Builder.defineMacro("__minix", "3"); 368 Builder.defineMacro("_EM_WSIZE", "4"); 369 Builder.defineMacro("_EM_PSIZE", "4"); 370 Builder.defineMacro("_EM_SSIZE", "2"); 371 Builder.defineMacro("_EM_LSIZE", "4"); 372 Builder.defineMacro("_EM_FSIZE", "4"); 373 Builder.defineMacro("_EM_DSIZE", "8"); 374 Builder.defineMacro("__ELF__"); 375 DefineStd(Builder, "unix", Opts); 376 } 377 public: 378 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 379 this->UserLabelPrefix = ""; 380 } 381 }; 382 383 // Linux target 384 template<typename Target> 385 class LinuxTargetInfo : public OSTargetInfo<Target> { 386 protected: 387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 388 MacroBuilder &Builder) const override { 389 // Linux defines; list based off of gcc output 390 DefineStd(Builder, "unix", Opts); 391 DefineStd(Builder, "linux", Opts); 392 Builder.defineMacro("__gnu_linux__"); 393 Builder.defineMacro("__ELF__"); 394 if (Triple.isAndroid()) { 395 Builder.defineMacro("__ANDROID__", "1"); 396 unsigned Maj, Min, Rev; 397 Triple.getEnvironmentVersion(Maj, Min, Rev); 398 this->PlatformName = "android"; 399 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 400 } 401 if (Opts.POSIXThreads) 402 Builder.defineMacro("_REENTRANT"); 403 if (Opts.CPlusPlus) 404 Builder.defineMacro("_GNU_SOURCE"); 405 } 406 public: 407 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 408 this->UserLabelPrefix = ""; 409 this->WIntType = TargetInfo::UnsignedInt; 410 411 switch (Triple.getArch()) { 412 default: 413 break; 414 case llvm::Triple::ppc: 415 case llvm::Triple::ppc64: 416 case llvm::Triple::ppc64le: 417 this->MCountName = "_mcount"; 418 break; 419 } 420 } 421 422 const char *getStaticInitSectionSpecifier() const override { 423 return ".text.startup"; 424 } 425 }; 426 427 // NetBSD Target 428 template<typename Target> 429 class NetBSDTargetInfo : public OSTargetInfo<Target> { 430 protected: 431 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 432 MacroBuilder &Builder) const override { 433 // NetBSD defines; list based off of gcc output 434 Builder.defineMacro("__NetBSD__"); 435 Builder.defineMacro("__unix__"); 436 Builder.defineMacro("__ELF__"); 437 if (Opts.POSIXThreads) 438 Builder.defineMacro("_POSIX_THREADS"); 439 440 switch (Triple.getArch()) { 441 default: 442 break; 443 case llvm::Triple::arm: 444 case llvm::Triple::armeb: 445 case llvm::Triple::thumb: 446 case llvm::Triple::thumbeb: 447 Builder.defineMacro("__ARM_DWARF_EH__"); 448 break; 449 } 450 } 451 public: 452 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 453 this->UserLabelPrefix = ""; 454 this->MCountName = "_mcount"; 455 } 456 }; 457 458 // OpenBSD Target 459 template<typename Target> 460 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 461 protected: 462 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 463 MacroBuilder &Builder) const override { 464 // OpenBSD defines; list based off of gcc output 465 466 Builder.defineMacro("__OpenBSD__"); 467 DefineStd(Builder, "unix", Opts); 468 Builder.defineMacro("__ELF__"); 469 if (Opts.POSIXThreads) 470 Builder.defineMacro("_REENTRANT"); 471 } 472 public: 473 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 474 this->UserLabelPrefix = ""; 475 this->TLSSupported = false; 476 477 switch (Triple.getArch()) { 478 default: 479 case llvm::Triple::x86: 480 case llvm::Triple::x86_64: 481 case llvm::Triple::arm: 482 case llvm::Triple::sparc: 483 this->MCountName = "__mcount"; 484 break; 485 case llvm::Triple::mips64: 486 case llvm::Triple::mips64el: 487 case llvm::Triple::ppc: 488 case llvm::Triple::sparcv9: 489 this->MCountName = "_mcount"; 490 break; 491 } 492 } 493 }; 494 495 // Bitrig Target 496 template<typename Target> 497 class BitrigTargetInfo : public OSTargetInfo<Target> { 498 protected: 499 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 500 MacroBuilder &Builder) const override { 501 // Bitrig defines; list based off of gcc output 502 503 Builder.defineMacro("__Bitrig__"); 504 DefineStd(Builder, "unix", Opts); 505 Builder.defineMacro("__ELF__"); 506 if (Opts.POSIXThreads) 507 Builder.defineMacro("_REENTRANT"); 508 509 switch (Triple.getArch()) { 510 default: 511 break; 512 case llvm::Triple::arm: 513 case llvm::Triple::armeb: 514 case llvm::Triple::thumb: 515 case llvm::Triple::thumbeb: 516 Builder.defineMacro("__ARM_DWARF_EH__"); 517 break; 518 } 519 } 520 public: 521 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 522 this->UserLabelPrefix = ""; 523 this->MCountName = "__mcount"; 524 } 525 }; 526 527 // PSP Target 528 template<typename Target> 529 class PSPTargetInfo : public OSTargetInfo<Target> { 530 protected: 531 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 532 MacroBuilder &Builder) const override { 533 // PSP defines; list based on the output of the pspdev gcc toolchain. 534 Builder.defineMacro("PSP"); 535 Builder.defineMacro("_PSP"); 536 Builder.defineMacro("__psp__"); 537 Builder.defineMacro("__ELF__"); 538 } 539 public: 540 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 541 this->UserLabelPrefix = ""; 542 } 543 }; 544 545 // PS3 PPU Target 546 template<typename Target> 547 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 548 protected: 549 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 550 MacroBuilder &Builder) const override { 551 // PS3 PPU defines. 552 Builder.defineMacro("__PPC__"); 553 Builder.defineMacro("__PPU__"); 554 Builder.defineMacro("__CELLOS_LV2__"); 555 Builder.defineMacro("__ELF__"); 556 Builder.defineMacro("__LP32__"); 557 Builder.defineMacro("_ARCH_PPC64"); 558 Builder.defineMacro("__powerpc64__"); 559 } 560 public: 561 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 562 this->UserLabelPrefix = ""; 563 this->LongWidth = this->LongAlign = 32; 564 this->PointerWidth = this->PointerAlign = 32; 565 this->IntMaxType = TargetInfo::SignedLongLong; 566 this->Int64Type = TargetInfo::SignedLongLong; 567 this->SizeType = TargetInfo::UnsignedInt; 568 this->DataLayoutString = "E-m:e-p:32:32-i64:64-n32:64"; 569 } 570 }; 571 572 template <typename Target> 573 class PS4OSTargetInfo : public OSTargetInfo<Target> { 574 protected: 575 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 576 MacroBuilder &Builder) const override { 577 Builder.defineMacro("__FreeBSD__", "9"); 578 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 579 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 580 DefineStd(Builder, "unix", Opts); 581 Builder.defineMacro("__ELF__"); 582 Builder.defineMacro("__PS4__"); 583 } 584 public: 585 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 586 this->WCharType = this->UnsignedShort; 587 588 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 589 this->MaxTLSAlign = 256; 590 this->UserLabelPrefix = ""; 591 592 switch (Triple.getArch()) { 593 default: 594 case llvm::Triple::x86_64: 595 this->MCountName = ".mcount"; 596 break; 597 } 598 } 599 }; 600 601 // Solaris target 602 template<typename Target> 603 class SolarisTargetInfo : public OSTargetInfo<Target> { 604 protected: 605 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 606 MacroBuilder &Builder) const override { 607 DefineStd(Builder, "sun", Opts); 608 DefineStd(Builder, "unix", Opts); 609 Builder.defineMacro("__ELF__"); 610 Builder.defineMacro("__svr4__"); 611 Builder.defineMacro("__SVR4"); 612 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 613 // newer, but to 500 for everything else. feature_test.h has a check to 614 // ensure that you are not using C99 with an old version of X/Open or C89 615 // with a new version. 616 if (Opts.C99) 617 Builder.defineMacro("_XOPEN_SOURCE", "600"); 618 else 619 Builder.defineMacro("_XOPEN_SOURCE", "500"); 620 if (Opts.CPlusPlus) 621 Builder.defineMacro("__C99FEATURES__"); 622 Builder.defineMacro("_LARGEFILE_SOURCE"); 623 Builder.defineMacro("_LARGEFILE64_SOURCE"); 624 Builder.defineMacro("__EXTENSIONS__"); 625 Builder.defineMacro("_REENTRANT"); 626 } 627 public: 628 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 629 this->UserLabelPrefix = ""; 630 this->WCharType = this->SignedInt; 631 // FIXME: WIntType should be SignedLong 632 } 633 }; 634 635 // Windows target 636 template<typename Target> 637 class WindowsTargetInfo : public OSTargetInfo<Target> { 638 protected: 639 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 640 MacroBuilder &Builder) const override { 641 Builder.defineMacro("_WIN32"); 642 } 643 void getVisualStudioDefines(const LangOptions &Opts, 644 MacroBuilder &Builder) const { 645 if (Opts.CPlusPlus) { 646 if (Opts.RTTIData) 647 Builder.defineMacro("_CPPRTTI"); 648 649 if (Opts.CXXExceptions) 650 Builder.defineMacro("_CPPUNWIND"); 651 } 652 653 if (Opts.Bool) 654 Builder.defineMacro("__BOOL_DEFINED"); 655 656 if (!Opts.CharIsSigned) 657 Builder.defineMacro("_CHAR_UNSIGNED"); 658 659 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 660 // but it works for now. 661 if (Opts.POSIXThreads) 662 Builder.defineMacro("_MT"); 663 664 if (Opts.MSCompatibilityVersion) { 665 Builder.defineMacro("_MSC_VER", 666 Twine(Opts.MSCompatibilityVersion / 100000)); 667 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 668 // FIXME We cannot encode the revision information into 32-bits 669 Builder.defineMacro("_MSC_BUILD", Twine(1)); 670 671 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 672 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 673 } 674 675 if (Opts.MicrosoftExt) { 676 Builder.defineMacro("_MSC_EXTENSIONS"); 677 678 if (Opts.CPlusPlus11) { 679 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 680 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 681 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 682 } 683 } 684 685 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 686 } 687 688 public: 689 WindowsTargetInfo(const llvm::Triple &Triple) 690 : OSTargetInfo<Target>(Triple) {} 691 }; 692 693 template <typename Target> 694 class NaClTargetInfo : public OSTargetInfo<Target> { 695 protected: 696 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 697 MacroBuilder &Builder) const override { 698 if (Opts.POSIXThreads) 699 Builder.defineMacro("_REENTRANT"); 700 if (Opts.CPlusPlus) 701 Builder.defineMacro("_GNU_SOURCE"); 702 703 DefineStd(Builder, "unix", Opts); 704 Builder.defineMacro("__ELF__"); 705 Builder.defineMacro("__native_client__"); 706 } 707 708 public: 709 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 710 this->UserLabelPrefix = ""; 711 this->LongAlign = 32; 712 this->LongWidth = 32; 713 this->PointerAlign = 32; 714 this->PointerWidth = 32; 715 this->IntMaxType = TargetInfo::SignedLongLong; 716 this->Int64Type = TargetInfo::SignedLongLong; 717 this->DoubleAlign = 64; 718 this->LongDoubleWidth = 64; 719 this->LongDoubleAlign = 64; 720 this->LongLongWidth = 64; 721 this->LongLongAlign = 64; 722 this->SizeType = TargetInfo::UnsignedInt; 723 this->PtrDiffType = TargetInfo::SignedInt; 724 this->IntPtrType = TargetInfo::SignedInt; 725 // RegParmMax is inherited from the underlying architecture 726 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 727 if (Triple.getArch() == llvm::Triple::arm) { 728 // Handled in ARM's setABI(). 729 } else if (Triple.getArch() == llvm::Triple::x86) { 730 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 731 } else if (Triple.getArch() == llvm::Triple::x86_64) { 732 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 733 } else if (Triple.getArch() == llvm::Triple::mipsel) { 734 // Handled on mips' setDataLayoutString. 735 } else { 736 assert(Triple.getArch() == llvm::Triple::le32); 737 this->DataLayoutString = "e-p:32:32-i64:64"; 738 } 739 } 740 }; 741 742 // WebAssembly target 743 template <typename Target> 744 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 745 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 746 MacroBuilder &Builder) const final { 747 // A common platform macro. 748 if (Opts.POSIXThreads) 749 Builder.defineMacro("_REENTRANT"); 750 // Follow g++ convention and predefine _GNU_SOURCE for C++. 751 if (Opts.CPlusPlus) 752 Builder.defineMacro("_GNU_SOURCE"); 753 } 754 755 // As an optimization, group static init code together in a section. 756 const char *getStaticInitSectionSpecifier() const final { 757 return ".text.__startup"; 758 } 759 760 public: 761 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple) 762 : OSTargetInfo<Target>(Triple) { 763 this->MCountName = "__mcount"; 764 this->UserLabelPrefix = ""; 765 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 766 } 767 }; 768 769 //===----------------------------------------------------------------------===// 770 // Specific target implementations. 771 //===----------------------------------------------------------------------===// 772 773 // PPC abstract base class 774 class PPCTargetInfo : public TargetInfo { 775 static const Builtin::Info BuiltinInfo[]; 776 static const char * const GCCRegNames[]; 777 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 778 std::string CPU; 779 780 // Target cpu features. 781 bool HasVSX; 782 bool HasP8Vector; 783 bool HasP8Crypto; 784 bool HasDirectMove; 785 bool HasQPX; 786 bool HasHTM; 787 bool HasBPERMD; 788 bool HasExtDiv; 789 790 protected: 791 std::string ABI; 792 793 public: 794 PPCTargetInfo(const llvm::Triple &Triple) 795 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 796 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 797 HasBPERMD(false), HasExtDiv(false) { 798 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 799 SimdDefaultAlign = 128; 800 LongDoubleWidth = LongDoubleAlign = 128; 801 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 802 } 803 804 /// \brief Flags for architecture specific defines. 805 typedef enum { 806 ArchDefineNone = 0, 807 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 808 ArchDefinePpcgr = 1 << 1, 809 ArchDefinePpcsq = 1 << 2, 810 ArchDefine440 = 1 << 3, 811 ArchDefine603 = 1 << 4, 812 ArchDefine604 = 1 << 5, 813 ArchDefinePwr4 = 1 << 6, 814 ArchDefinePwr5 = 1 << 7, 815 ArchDefinePwr5x = 1 << 8, 816 ArchDefinePwr6 = 1 << 9, 817 ArchDefinePwr6x = 1 << 10, 818 ArchDefinePwr7 = 1 << 11, 819 ArchDefinePwr8 = 1 << 12, 820 ArchDefineA2 = 1 << 13, 821 ArchDefineA2q = 1 << 14 822 } ArchDefineTypes; 823 824 // Note: GCC recognizes the following additional cpus: 825 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 826 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 827 // titan, rs64. 828 bool setCPU(const std::string &Name) override { 829 bool CPUKnown = llvm::StringSwitch<bool>(Name) 830 .Case("generic", true) 831 .Case("440", true) 832 .Case("450", true) 833 .Case("601", true) 834 .Case("602", true) 835 .Case("603", true) 836 .Case("603e", true) 837 .Case("603ev", true) 838 .Case("604", true) 839 .Case("604e", true) 840 .Case("620", true) 841 .Case("630", true) 842 .Case("g3", true) 843 .Case("7400", true) 844 .Case("g4", true) 845 .Case("7450", true) 846 .Case("g4+", true) 847 .Case("750", true) 848 .Case("970", true) 849 .Case("g5", true) 850 .Case("a2", true) 851 .Case("a2q", true) 852 .Case("e500mc", true) 853 .Case("e5500", true) 854 .Case("power3", true) 855 .Case("pwr3", true) 856 .Case("power4", true) 857 .Case("pwr4", true) 858 .Case("power5", true) 859 .Case("pwr5", true) 860 .Case("power5x", true) 861 .Case("pwr5x", true) 862 .Case("power6", true) 863 .Case("pwr6", true) 864 .Case("power6x", true) 865 .Case("pwr6x", true) 866 .Case("power7", true) 867 .Case("pwr7", true) 868 .Case("power8", true) 869 .Case("pwr8", true) 870 .Case("powerpc", true) 871 .Case("ppc", true) 872 .Case("powerpc64", true) 873 .Case("ppc64", true) 874 .Case("powerpc64le", true) 875 .Case("ppc64le", true) 876 .Default(false); 877 878 if (CPUKnown) 879 CPU = Name; 880 881 return CPUKnown; 882 } 883 884 885 StringRef getABI() const override { return ABI; } 886 887 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 888 return llvm::makeArrayRef(BuiltinInfo, 889 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 890 } 891 892 bool isCLZForZeroUndef() const override { return false; } 893 894 void getTargetDefines(const LangOptions &Opts, 895 MacroBuilder &Builder) const override; 896 897 bool 898 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 899 StringRef CPU, 900 const std::vector<std::string> &FeaturesVec) const override; 901 902 bool handleTargetFeatures(std::vector<std::string> &Features, 903 DiagnosticsEngine &Diags) override; 904 bool hasFeature(StringRef Feature) const override; 905 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 906 bool Enabled) const override; 907 908 ArrayRef<const char *> getGCCRegNames() const override; 909 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 910 bool validateAsmConstraint(const char *&Name, 911 TargetInfo::ConstraintInfo &Info) const override { 912 switch (*Name) { 913 default: return false; 914 case 'O': // Zero 915 break; 916 case 'b': // Base register 917 case 'f': // Floating point register 918 Info.setAllowsRegister(); 919 break; 920 // FIXME: The following are added to allow parsing. 921 // I just took a guess at what the actions should be. 922 // Also, is more specific checking needed? I.e. specific registers? 923 case 'd': // Floating point register (containing 64-bit value) 924 case 'v': // Altivec vector register 925 Info.setAllowsRegister(); 926 break; 927 case 'w': 928 switch (Name[1]) { 929 case 'd':// VSX vector register to hold vector double data 930 case 'f':// VSX vector register to hold vector float data 931 case 's':// VSX vector register to hold scalar float data 932 case 'a':// Any VSX register 933 case 'c':// An individual CR bit 934 break; 935 default: 936 return false; 937 } 938 Info.setAllowsRegister(); 939 Name++; // Skip over 'w'. 940 break; 941 case 'h': // `MQ', `CTR', or `LINK' register 942 case 'q': // `MQ' register 943 case 'c': // `CTR' register 944 case 'l': // `LINK' register 945 case 'x': // `CR' register (condition register) number 0 946 case 'y': // `CR' register (condition register) 947 case 'z': // `XER[CA]' carry bit (part of the XER register) 948 Info.setAllowsRegister(); 949 break; 950 case 'I': // Signed 16-bit constant 951 case 'J': // Unsigned 16-bit constant shifted left 16 bits 952 // (use `L' instead for SImode constants) 953 case 'K': // Unsigned 16-bit constant 954 case 'L': // Signed 16-bit constant shifted left 16 bits 955 case 'M': // Constant larger than 31 956 case 'N': // Exact power of 2 957 case 'P': // Constant whose negation is a signed 16-bit constant 958 case 'G': // Floating point constant that can be loaded into a 959 // register with one instruction per word 960 case 'H': // Integer/Floating point constant that can be loaded 961 // into a register using three instructions 962 break; 963 case 'm': // Memory operand. Note that on PowerPC targets, m can 964 // include addresses that update the base register. It 965 // is therefore only safe to use `m' in an asm statement 966 // if that asm statement accesses the operand exactly once. 967 // The asm statement must also use `%U<opno>' as a 968 // placeholder for the "update" flag in the corresponding 969 // load or store instruction. For example: 970 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 971 // is correct but: 972 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 973 // is not. Use es rather than m if you don't want the base 974 // register to be updated. 975 case 'e': 976 if (Name[1] != 's') 977 return false; 978 // es: A "stable" memory operand; that is, one which does not 979 // include any automodification of the base register. Unlike 980 // `m', this constraint can be used in asm statements that 981 // might access the operand several times, or that might not 982 // access it at all. 983 Info.setAllowsMemory(); 984 Name++; // Skip over 'e'. 985 break; 986 case 'Q': // Memory operand that is an offset from a register (it is 987 // usually better to use `m' or `es' in asm statements) 988 case 'Z': // Memory operand that is an indexed or indirect from a 989 // register (it is usually better to use `m' or `es' in 990 // asm statements) 991 Info.setAllowsMemory(); 992 Info.setAllowsRegister(); 993 break; 994 case 'R': // AIX TOC entry 995 case 'a': // Address operand that is an indexed or indirect from a 996 // register (`p' is preferable for asm statements) 997 case 'S': // Constant suitable as a 64-bit mask operand 998 case 'T': // Constant suitable as a 32-bit mask operand 999 case 'U': // System V Release 4 small data area reference 1000 case 't': // AND masks that can be performed by two rldic{l, r} 1001 // instructions 1002 case 'W': // Vector constant that does not require memory 1003 case 'j': // Vector constant that is all zeros. 1004 break; 1005 // End FIXME. 1006 } 1007 return true; 1008 } 1009 std::string convertConstraint(const char *&Constraint) const override { 1010 std::string R; 1011 switch (*Constraint) { 1012 case 'e': 1013 case 'w': 1014 // Two-character constraint; add "^" hint for later parsing. 1015 R = std::string("^") + std::string(Constraint, 2); 1016 Constraint++; 1017 break; 1018 default: 1019 return TargetInfo::convertConstraint(Constraint); 1020 } 1021 return R; 1022 } 1023 const char *getClobbers() const override { 1024 return ""; 1025 } 1026 int getEHDataRegisterNumber(unsigned RegNo) const override { 1027 if (RegNo == 0) return 3; 1028 if (RegNo == 1) return 4; 1029 return -1; 1030 } 1031 1032 bool hasSjLjLowering() const override { 1033 return true; 1034 } 1035 1036 bool useFloat128ManglingForLongDouble() const override { 1037 return LongDoubleWidth == 128 && 1038 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1039 getTriple().isOSBinFormatELF(); 1040 } 1041 }; 1042 1043 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1044 #define BUILTIN(ID, TYPE, ATTRS) \ 1045 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1046 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1047 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1048 #include "clang/Basic/BuiltinsPPC.def" 1049 }; 1050 1051 /// handleTargetFeatures - Perform initialization based on the user 1052 /// configured set of features. 1053 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1054 DiagnosticsEngine &Diags) { 1055 for (const auto &Feature : Features) { 1056 if (Feature == "+vsx") { 1057 HasVSX = true; 1058 } else if (Feature == "+bpermd") { 1059 HasBPERMD = true; 1060 } else if (Feature == "+extdiv") { 1061 HasExtDiv = true; 1062 } else if (Feature == "+power8-vector") { 1063 HasP8Vector = true; 1064 } else if (Feature == "+crypto") { 1065 HasP8Crypto = true; 1066 } else if (Feature == "+direct-move") { 1067 HasDirectMove = true; 1068 } else if (Feature == "+qpx") { 1069 HasQPX = true; 1070 } else if (Feature == "+htm") { 1071 HasHTM = true; 1072 } 1073 // TODO: Finish this list and add an assert that we've handled them 1074 // all. 1075 } 1076 1077 return true; 1078 } 1079 1080 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1081 /// #defines that are not tied to a specific subtarget. 1082 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1083 MacroBuilder &Builder) const { 1084 // Target identification. 1085 Builder.defineMacro("__ppc__"); 1086 Builder.defineMacro("__PPC__"); 1087 Builder.defineMacro("_ARCH_PPC"); 1088 Builder.defineMacro("__powerpc__"); 1089 Builder.defineMacro("__POWERPC__"); 1090 if (PointerWidth == 64) { 1091 Builder.defineMacro("_ARCH_PPC64"); 1092 Builder.defineMacro("__powerpc64__"); 1093 Builder.defineMacro("__ppc64__"); 1094 Builder.defineMacro("__PPC64__"); 1095 } 1096 1097 // Target properties. 1098 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1099 Builder.defineMacro("_LITTLE_ENDIAN"); 1100 } else { 1101 if (getTriple().getOS() != llvm::Triple::NetBSD && 1102 getTriple().getOS() != llvm::Triple::OpenBSD) 1103 Builder.defineMacro("_BIG_ENDIAN"); 1104 } 1105 1106 // ABI options. 1107 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1108 Builder.defineMacro("_CALL_ELF", "1"); 1109 if (ABI == "elfv2") 1110 Builder.defineMacro("_CALL_ELF", "2"); 1111 1112 // Subtarget options. 1113 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1114 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1115 1116 // FIXME: Should be controlled by command line option. 1117 if (LongDoubleWidth == 128) 1118 Builder.defineMacro("__LONG_DOUBLE_128__"); 1119 1120 if (Opts.AltiVec) { 1121 Builder.defineMacro("__VEC__", "10206"); 1122 Builder.defineMacro("__ALTIVEC__"); 1123 } 1124 1125 // CPU identification. 1126 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1127 .Case("440", ArchDefineName) 1128 .Case("450", ArchDefineName | ArchDefine440) 1129 .Case("601", ArchDefineName) 1130 .Case("602", ArchDefineName | ArchDefinePpcgr) 1131 .Case("603", ArchDefineName | ArchDefinePpcgr) 1132 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1133 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1134 .Case("604", ArchDefineName | ArchDefinePpcgr) 1135 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1136 .Case("620", ArchDefineName | ArchDefinePpcgr) 1137 .Case("630", ArchDefineName | ArchDefinePpcgr) 1138 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1139 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1140 .Case("750", ArchDefineName | ArchDefinePpcgr) 1141 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1142 | ArchDefinePpcsq) 1143 .Case("a2", ArchDefineA2) 1144 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1145 .Case("pwr3", ArchDefinePpcgr) 1146 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1147 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1148 | ArchDefinePpcsq) 1149 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1150 | ArchDefinePpcgr | ArchDefinePpcsq) 1151 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1152 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1153 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1154 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1155 | ArchDefinePpcsq) 1156 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1157 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1158 | ArchDefinePpcgr | ArchDefinePpcsq) 1159 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1160 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1161 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1162 .Case("power3", ArchDefinePpcgr) 1163 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1164 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1165 | ArchDefinePpcsq) 1166 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1167 | ArchDefinePpcgr | ArchDefinePpcsq) 1168 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1169 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1170 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1171 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1172 | ArchDefinePpcsq) 1173 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1174 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1175 | ArchDefinePpcgr | ArchDefinePpcsq) 1176 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1177 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1178 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1179 .Default(ArchDefineNone); 1180 1181 if (defs & ArchDefineName) 1182 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1183 if (defs & ArchDefinePpcgr) 1184 Builder.defineMacro("_ARCH_PPCGR"); 1185 if (defs & ArchDefinePpcsq) 1186 Builder.defineMacro("_ARCH_PPCSQ"); 1187 if (defs & ArchDefine440) 1188 Builder.defineMacro("_ARCH_440"); 1189 if (defs & ArchDefine603) 1190 Builder.defineMacro("_ARCH_603"); 1191 if (defs & ArchDefine604) 1192 Builder.defineMacro("_ARCH_604"); 1193 if (defs & ArchDefinePwr4) 1194 Builder.defineMacro("_ARCH_PWR4"); 1195 if (defs & ArchDefinePwr5) 1196 Builder.defineMacro("_ARCH_PWR5"); 1197 if (defs & ArchDefinePwr5x) 1198 Builder.defineMacro("_ARCH_PWR5X"); 1199 if (defs & ArchDefinePwr6) 1200 Builder.defineMacro("_ARCH_PWR6"); 1201 if (defs & ArchDefinePwr6x) 1202 Builder.defineMacro("_ARCH_PWR6X"); 1203 if (defs & ArchDefinePwr7) 1204 Builder.defineMacro("_ARCH_PWR7"); 1205 if (defs & ArchDefinePwr8) 1206 Builder.defineMacro("_ARCH_PWR8"); 1207 if (defs & ArchDefineA2) 1208 Builder.defineMacro("_ARCH_A2"); 1209 if (defs & ArchDefineA2q) { 1210 Builder.defineMacro("_ARCH_A2Q"); 1211 Builder.defineMacro("_ARCH_QP"); 1212 } 1213 1214 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1215 Builder.defineMacro("__bg__"); 1216 Builder.defineMacro("__THW_BLUEGENE__"); 1217 Builder.defineMacro("__bgq__"); 1218 Builder.defineMacro("__TOS_BGQ__"); 1219 } 1220 1221 if (HasVSX) 1222 Builder.defineMacro("__VSX__"); 1223 if (HasP8Vector) 1224 Builder.defineMacro("__POWER8_VECTOR__"); 1225 if (HasP8Crypto) 1226 Builder.defineMacro("__CRYPTO__"); 1227 if (HasHTM) 1228 Builder.defineMacro("__HTM__"); 1229 1230 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1231 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1232 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1233 if (PointerWidth == 64) 1234 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1235 1236 // FIXME: The following are not yet generated here by Clang, but are 1237 // generated by GCC: 1238 // 1239 // _SOFT_FLOAT_ 1240 // __RECIP_PRECISION__ 1241 // __APPLE_ALTIVEC__ 1242 // __RECIP__ 1243 // __RECIPF__ 1244 // __RSQRTE__ 1245 // __RSQRTEF__ 1246 // _SOFT_DOUBLE_ 1247 // __NO_LWSYNC__ 1248 // __HAVE_BSWAP__ 1249 // __LONGDOUBLE128 1250 // __CMODEL_MEDIUM__ 1251 // __CMODEL_LARGE__ 1252 // _CALL_SYSV 1253 // _CALL_DARWIN 1254 // __NO_FPRS__ 1255 } 1256 1257 // Handle explicit options being passed to the compiler here: if we've 1258 // explicitly turned off vsx and turned on power8-vector or direct-move then 1259 // go ahead and error since the customer has expressed a somewhat incompatible 1260 // set of options. 1261 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1262 const std::vector<std::string> &FeaturesVec) { 1263 1264 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1265 FeaturesVec.end()) { 1266 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1267 FeaturesVec.end()) { 1268 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1269 << "-mno-vsx"; 1270 return false; 1271 } 1272 1273 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1274 FeaturesVec.end()) { 1275 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1276 << "-mno-vsx"; 1277 return false; 1278 } 1279 } 1280 1281 return true; 1282 } 1283 1284 bool PPCTargetInfo::initFeatureMap( 1285 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1286 const std::vector<std::string> &FeaturesVec) const { 1287 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1288 .Case("7400", true) 1289 .Case("g4", true) 1290 .Case("7450", true) 1291 .Case("g4+", true) 1292 .Case("970", true) 1293 .Case("g5", true) 1294 .Case("pwr6", true) 1295 .Case("pwr7", true) 1296 .Case("pwr8", true) 1297 .Case("ppc64", true) 1298 .Case("ppc64le", true) 1299 .Default(false); 1300 1301 Features["qpx"] = (CPU == "a2q"); 1302 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1303 .Case("ppc64le", true) 1304 .Case("pwr8", true) 1305 .Default(false); 1306 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1307 .Case("ppc64le", true) 1308 .Case("pwr8", true) 1309 .Default(false); 1310 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1311 .Case("ppc64le", true) 1312 .Case("pwr8", true) 1313 .Case("pwr7", true) 1314 .Default(false); 1315 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1316 .Case("ppc64le", true) 1317 .Case("pwr8", true) 1318 .Case("pwr7", true) 1319 .Default(false); 1320 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1321 .Case("ppc64le", true) 1322 .Case("pwr8", true) 1323 .Default(false); 1324 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1325 .Case("ppc64le", true) 1326 .Case("pwr8", true) 1327 .Case("pwr7", true) 1328 .Default(false); 1329 1330 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1331 return false; 1332 1333 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1334 } 1335 1336 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1337 return llvm::StringSwitch<bool>(Feature) 1338 .Case("powerpc", true) 1339 .Case("vsx", HasVSX) 1340 .Case("power8-vector", HasP8Vector) 1341 .Case("crypto", HasP8Crypto) 1342 .Case("direct-move", HasDirectMove) 1343 .Case("qpx", HasQPX) 1344 .Case("htm", HasHTM) 1345 .Case("bpermd", HasBPERMD) 1346 .Case("extdiv", HasExtDiv) 1347 .Default(false); 1348 } 1349 1350 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1351 StringRef Name, bool Enabled) const { 1352 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1353 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1354 // incompatible options. 1355 if (Enabled) { 1356 if (Name == "vsx") { 1357 Features[Name] = true; 1358 } else if (Name == "direct-move") { 1359 Features[Name] = Features["vsx"] = true; 1360 } else if (Name == "power8-vector") { 1361 Features[Name] = Features["vsx"] = true; 1362 } else { 1363 Features[Name] = true; 1364 } 1365 } else { 1366 if (Name == "vsx") { 1367 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1368 false; 1369 } else { 1370 Features[Name] = false; 1371 } 1372 } 1373 } 1374 1375 const char * const PPCTargetInfo::GCCRegNames[] = { 1376 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1377 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1378 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1379 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1380 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1381 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1382 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1383 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1384 "mq", "lr", "ctr", "ap", 1385 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1386 "xer", 1387 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1388 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1389 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1390 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1391 "vrsave", "vscr", 1392 "spe_acc", "spefscr", 1393 "sfp" 1394 }; 1395 1396 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1397 return llvm::makeArrayRef(GCCRegNames); 1398 } 1399 1400 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1401 // While some of these aliases do map to different registers 1402 // they still share the same register name. 1403 { { "0" }, "r0" }, 1404 { { "1"}, "r1" }, 1405 { { "2" }, "r2" }, 1406 { { "3" }, "r3" }, 1407 { { "4" }, "r4" }, 1408 { { "5" }, "r5" }, 1409 { { "6" }, "r6" }, 1410 { { "7" }, "r7" }, 1411 { { "8" }, "r8" }, 1412 { { "9" }, "r9" }, 1413 { { "10" }, "r10" }, 1414 { { "11" }, "r11" }, 1415 { { "12" }, "r12" }, 1416 { { "13" }, "r13" }, 1417 { { "14" }, "r14" }, 1418 { { "15" }, "r15" }, 1419 { { "16" }, "r16" }, 1420 { { "17" }, "r17" }, 1421 { { "18" }, "r18" }, 1422 { { "19" }, "r19" }, 1423 { { "20" }, "r20" }, 1424 { { "21" }, "r21" }, 1425 { { "22" }, "r22" }, 1426 { { "23" }, "r23" }, 1427 { { "24" }, "r24" }, 1428 { { "25" }, "r25" }, 1429 { { "26" }, "r26" }, 1430 { { "27" }, "r27" }, 1431 { { "28" }, "r28" }, 1432 { { "29" }, "r29" }, 1433 { { "30" }, "r30" }, 1434 { { "31" }, "r31" }, 1435 { { "fr0" }, "f0" }, 1436 { { "fr1" }, "f1" }, 1437 { { "fr2" }, "f2" }, 1438 { { "fr3" }, "f3" }, 1439 { { "fr4" }, "f4" }, 1440 { { "fr5" }, "f5" }, 1441 { { "fr6" }, "f6" }, 1442 { { "fr7" }, "f7" }, 1443 { { "fr8" }, "f8" }, 1444 { { "fr9" }, "f9" }, 1445 { { "fr10" }, "f10" }, 1446 { { "fr11" }, "f11" }, 1447 { { "fr12" }, "f12" }, 1448 { { "fr13" }, "f13" }, 1449 { { "fr14" }, "f14" }, 1450 { { "fr15" }, "f15" }, 1451 { { "fr16" }, "f16" }, 1452 { { "fr17" }, "f17" }, 1453 { { "fr18" }, "f18" }, 1454 { { "fr19" }, "f19" }, 1455 { { "fr20" }, "f20" }, 1456 { { "fr21" }, "f21" }, 1457 { { "fr22" }, "f22" }, 1458 { { "fr23" }, "f23" }, 1459 { { "fr24" }, "f24" }, 1460 { { "fr25" }, "f25" }, 1461 { { "fr26" }, "f26" }, 1462 { { "fr27" }, "f27" }, 1463 { { "fr28" }, "f28" }, 1464 { { "fr29" }, "f29" }, 1465 { { "fr30" }, "f30" }, 1466 { { "fr31" }, "f31" }, 1467 { { "cc" }, "cr0" }, 1468 }; 1469 1470 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1471 return llvm::makeArrayRef(GCCRegAliases); 1472 } 1473 1474 class PPC32TargetInfo : public PPCTargetInfo { 1475 public: 1476 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1477 DataLayoutString = "E-m:e-p:32:32-i64:64-n32"; 1478 1479 switch (getTriple().getOS()) { 1480 case llvm::Triple::Linux: 1481 case llvm::Triple::FreeBSD: 1482 case llvm::Triple::NetBSD: 1483 SizeType = UnsignedInt; 1484 PtrDiffType = SignedInt; 1485 IntPtrType = SignedInt; 1486 break; 1487 default: 1488 break; 1489 } 1490 1491 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1492 LongDoubleWidth = LongDoubleAlign = 64; 1493 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1494 } 1495 1496 // PPC32 supports atomics up to 4 bytes. 1497 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1498 } 1499 1500 BuiltinVaListKind getBuiltinVaListKind() const override { 1501 // This is the ELF definition, and is overridden by the Darwin sub-target 1502 return TargetInfo::PowerABIBuiltinVaList; 1503 } 1504 }; 1505 1506 // Note: ABI differences may eventually require us to have a separate 1507 // TargetInfo for little endian. 1508 class PPC64TargetInfo : public PPCTargetInfo { 1509 public: 1510 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1511 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1512 IntMaxType = SignedLong; 1513 Int64Type = SignedLong; 1514 1515 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1516 DataLayoutString = "e-m:e-i64:64-n32:64"; 1517 ABI = "elfv2"; 1518 } else { 1519 DataLayoutString = "E-m:e-i64:64-n32:64"; 1520 ABI = "elfv1"; 1521 } 1522 1523 switch (getTriple().getOS()) { 1524 case llvm::Triple::FreeBSD: 1525 LongDoubleWidth = LongDoubleAlign = 64; 1526 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1527 break; 1528 case llvm::Triple::NetBSD: 1529 IntMaxType = SignedLongLong; 1530 Int64Type = SignedLongLong; 1531 break; 1532 default: 1533 break; 1534 } 1535 1536 // PPC64 supports atomics up to 8 bytes. 1537 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1538 } 1539 BuiltinVaListKind getBuiltinVaListKind() const override { 1540 return TargetInfo::CharPtrBuiltinVaList; 1541 } 1542 // PPC64 Linux-specific ABI options. 1543 bool setABI(const std::string &Name) override { 1544 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1545 ABI = Name; 1546 return true; 1547 } 1548 return false; 1549 } 1550 }; 1551 1552 class DarwinPPC32TargetInfo : 1553 public DarwinTargetInfo<PPC32TargetInfo> { 1554 public: 1555 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1556 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1557 HasAlignMac68kSupport = true; 1558 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1559 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1560 LongLongAlign = 32; 1561 SuitableAlign = 128; 1562 DataLayoutString = "E-m:o-p:32:32-f64:32:64-n32"; 1563 } 1564 BuiltinVaListKind getBuiltinVaListKind() const override { 1565 return TargetInfo::CharPtrBuiltinVaList; 1566 } 1567 }; 1568 1569 class DarwinPPC64TargetInfo : 1570 public DarwinTargetInfo<PPC64TargetInfo> { 1571 public: 1572 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1573 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1574 HasAlignMac68kSupport = true; 1575 SuitableAlign = 128; 1576 DataLayoutString = "E-m:o-i64:64-n32:64"; 1577 } 1578 }; 1579 1580 static const unsigned NVPTXAddrSpaceMap[] = { 1581 1, // opencl_global 1582 3, // opencl_local 1583 4, // opencl_constant 1584 // FIXME: generic has to be added to the target 1585 0, // opencl_generic 1586 1, // cuda_device 1587 4, // cuda_constant 1588 3, // cuda_shared 1589 }; 1590 1591 class NVPTXTargetInfo : public TargetInfo { 1592 static const char *const GCCRegNames[]; 1593 static const Builtin::Info BuiltinInfo[]; 1594 1595 // The GPU profiles supported by the NVPTX backend 1596 enum GPUKind { 1597 GK_NONE, 1598 GK_SM20, 1599 GK_SM21, 1600 GK_SM30, 1601 GK_SM35, 1602 GK_SM37, 1603 } GPU; 1604 1605 public: 1606 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1607 BigEndian = false; 1608 TLSSupported = false; 1609 LongWidth = LongAlign = 64; 1610 AddrSpaceMap = &NVPTXAddrSpaceMap; 1611 UseAddrSpaceMapMangling = true; 1612 // Define available target features 1613 // These must be defined in sorted order! 1614 NoAsmVariants = true; 1615 // Set the default GPU to sm20 1616 GPU = GK_SM20; 1617 } 1618 void getTargetDefines(const LangOptions &Opts, 1619 MacroBuilder &Builder) const override { 1620 Builder.defineMacro("__PTX__"); 1621 Builder.defineMacro("__NVPTX__"); 1622 if (Opts.CUDAIsDevice) { 1623 // Set __CUDA_ARCH__ for the GPU specified. 1624 std::string CUDAArchCode; 1625 switch (GPU) { 1626 case GK_SM20: 1627 CUDAArchCode = "200"; 1628 break; 1629 case GK_SM21: 1630 CUDAArchCode = "210"; 1631 break; 1632 case GK_SM30: 1633 CUDAArchCode = "300"; 1634 break; 1635 case GK_SM35: 1636 CUDAArchCode = "350"; 1637 break; 1638 case GK_SM37: 1639 CUDAArchCode = "370"; 1640 break; 1641 default: 1642 llvm_unreachable("Unhandled target CPU"); 1643 } 1644 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1645 } 1646 } 1647 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1648 return llvm::makeArrayRef(BuiltinInfo, 1649 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1650 } 1651 bool hasFeature(StringRef Feature) const override { 1652 return Feature == "ptx" || Feature == "nvptx"; 1653 } 1654 1655 ArrayRef<const char *> getGCCRegNames() const override; 1656 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1657 // No aliases. 1658 return None; 1659 } 1660 bool validateAsmConstraint(const char *&Name, 1661 TargetInfo::ConstraintInfo &Info) const override { 1662 switch (*Name) { 1663 default: 1664 return false; 1665 case 'c': 1666 case 'h': 1667 case 'r': 1668 case 'l': 1669 case 'f': 1670 case 'd': 1671 Info.setAllowsRegister(); 1672 return true; 1673 } 1674 } 1675 const char *getClobbers() const override { 1676 // FIXME: Is this really right? 1677 return ""; 1678 } 1679 BuiltinVaListKind getBuiltinVaListKind() const override { 1680 // FIXME: implement 1681 return TargetInfo::CharPtrBuiltinVaList; 1682 } 1683 bool setCPU(const std::string &Name) override { 1684 GPU = llvm::StringSwitch<GPUKind>(Name) 1685 .Case("sm_20", GK_SM20) 1686 .Case("sm_21", GK_SM21) 1687 .Case("sm_30", GK_SM30) 1688 .Case("sm_35", GK_SM35) 1689 .Case("sm_37", GK_SM37) 1690 .Default(GK_NONE); 1691 1692 return GPU != GK_NONE; 1693 } 1694 }; 1695 1696 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1697 #define BUILTIN(ID, TYPE, ATTRS) \ 1698 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1699 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1700 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1701 #include "clang/Basic/BuiltinsNVPTX.def" 1702 }; 1703 1704 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1705 1706 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1707 return llvm::makeArrayRef(GCCRegNames); 1708 } 1709 1710 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1711 public: 1712 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1713 LongWidth = LongAlign = 32; 1714 PointerWidth = PointerAlign = 32; 1715 SizeType = TargetInfo::UnsignedInt; 1716 PtrDiffType = TargetInfo::SignedInt; 1717 IntPtrType = TargetInfo::SignedInt; 1718 DataLayoutString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1719 } 1720 }; 1721 1722 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1723 public: 1724 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1725 PointerWidth = PointerAlign = 64; 1726 SizeType = TargetInfo::UnsignedLong; 1727 PtrDiffType = TargetInfo::SignedLong; 1728 IntPtrType = TargetInfo::SignedLong; 1729 DataLayoutString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1730 } 1731 }; 1732 1733 static const unsigned AMDGPUAddrSpaceMap[] = { 1734 1, // opencl_global 1735 3, // opencl_local 1736 2, // opencl_constant 1737 4, // opencl_generic 1738 1, // cuda_device 1739 2, // cuda_constant 1740 3 // cuda_shared 1741 }; 1742 1743 // If you edit the description strings, make sure you update 1744 // getPointerWidthV(). 1745 1746 static const char *const DataLayoutStringR600 = 1747 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1748 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1749 1750 static const char *const DataLayoutStringR600DoubleOps = 1751 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1752 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1753 1754 static const char *const DataLayoutStringSI = 1755 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1756 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1757 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1758 1759 class AMDGPUTargetInfo : public TargetInfo { 1760 static const Builtin::Info BuiltinInfo[]; 1761 static const char * const GCCRegNames[]; 1762 1763 /// \brief The GPU profiles supported by the AMDGPU target. 1764 enum GPUKind { 1765 GK_NONE, 1766 GK_R600, 1767 GK_R600_DOUBLE_OPS, 1768 GK_R700, 1769 GK_R700_DOUBLE_OPS, 1770 GK_EVERGREEN, 1771 GK_EVERGREEN_DOUBLE_OPS, 1772 GK_NORTHERN_ISLANDS, 1773 GK_CAYMAN, 1774 GK_SOUTHERN_ISLANDS, 1775 GK_SEA_ISLANDS, 1776 GK_VOLCANIC_ISLANDS 1777 } GPU; 1778 1779 bool hasFP64:1; 1780 bool hasFMAF:1; 1781 bool hasLDEXPF:1; 1782 1783 public: 1784 AMDGPUTargetInfo(const llvm::Triple &Triple) 1785 : TargetInfo(Triple) { 1786 1787 if (Triple.getArch() == llvm::Triple::amdgcn) { 1788 DataLayoutString = DataLayoutStringSI; 1789 GPU = GK_SOUTHERN_ISLANDS; 1790 hasFP64 = true; 1791 hasFMAF = true; 1792 hasLDEXPF = true; 1793 } else { 1794 DataLayoutString = DataLayoutStringR600; 1795 GPU = GK_R600; 1796 hasFP64 = false; 1797 hasFMAF = false; 1798 hasLDEXPF = false; 1799 } 1800 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1801 UseAddrSpaceMapMangling = true; 1802 } 1803 1804 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1805 if (GPU <= GK_CAYMAN) 1806 return 32; 1807 1808 switch(AddrSpace) { 1809 default: 1810 return 64; 1811 case 0: 1812 case 3: 1813 case 5: 1814 return 32; 1815 } 1816 } 1817 1818 const char * getClobbers() const override { 1819 return ""; 1820 } 1821 1822 ArrayRef<const char *> getGCCRegNames() const override; 1823 1824 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1825 return None; 1826 } 1827 1828 bool validateAsmConstraint(const char *&Name, 1829 TargetInfo::ConstraintInfo &Info) const override { 1830 switch (*Name) { 1831 default: break; 1832 case 'v': // vgpr 1833 case 's': // sgpr 1834 Info.setAllowsRegister(); 1835 return true; 1836 } 1837 return false; 1838 } 1839 1840 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1841 return llvm::makeArrayRef(BuiltinInfo, 1842 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 1843 } 1844 1845 void getTargetDefines(const LangOptions &Opts, 1846 MacroBuilder &Builder) const override { 1847 Builder.defineMacro("__R600__"); 1848 if (hasFMAF) 1849 Builder.defineMacro("__HAS_FMAF__"); 1850 if (hasLDEXPF) 1851 Builder.defineMacro("__HAS_LDEXPF__"); 1852 if (hasFP64 && Opts.OpenCL) 1853 Builder.defineMacro("cl_khr_fp64"); 1854 if (Opts.OpenCL) { 1855 if (GPU >= GK_NORTHERN_ISLANDS) { 1856 Builder.defineMacro("cl_khr_byte_addressable_store"); 1857 Builder.defineMacro("cl_khr_global_int32_base_atomics"); 1858 Builder.defineMacro("cl_khr_global_int32_extended_atomics"); 1859 Builder.defineMacro("cl_khr_local_int32_base_atomics"); 1860 Builder.defineMacro("cl_khr_local_int32_extended_atomics"); 1861 } 1862 } 1863 } 1864 1865 BuiltinVaListKind getBuiltinVaListKind() const override { 1866 return TargetInfo::CharPtrBuiltinVaList; 1867 } 1868 1869 bool setCPU(const std::string &Name) override { 1870 GPU = llvm::StringSwitch<GPUKind>(Name) 1871 .Case("r600" , GK_R600) 1872 .Case("rv610", GK_R600) 1873 .Case("rv620", GK_R600) 1874 .Case("rv630", GK_R600) 1875 .Case("rv635", GK_R600) 1876 .Case("rs780", GK_R600) 1877 .Case("rs880", GK_R600) 1878 .Case("rv670", GK_R600_DOUBLE_OPS) 1879 .Case("rv710", GK_R700) 1880 .Case("rv730", GK_R700) 1881 .Case("rv740", GK_R700_DOUBLE_OPS) 1882 .Case("rv770", GK_R700_DOUBLE_OPS) 1883 .Case("palm", GK_EVERGREEN) 1884 .Case("cedar", GK_EVERGREEN) 1885 .Case("sumo", GK_EVERGREEN) 1886 .Case("sumo2", GK_EVERGREEN) 1887 .Case("redwood", GK_EVERGREEN) 1888 .Case("juniper", GK_EVERGREEN) 1889 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1890 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1891 .Case("barts", GK_NORTHERN_ISLANDS) 1892 .Case("turks", GK_NORTHERN_ISLANDS) 1893 .Case("caicos", GK_NORTHERN_ISLANDS) 1894 .Case("cayman", GK_CAYMAN) 1895 .Case("aruba", GK_CAYMAN) 1896 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1897 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1898 .Case("verde", GK_SOUTHERN_ISLANDS) 1899 .Case("oland", GK_SOUTHERN_ISLANDS) 1900 .Case("hainan", GK_SOUTHERN_ISLANDS) 1901 .Case("bonaire", GK_SEA_ISLANDS) 1902 .Case("kabini", GK_SEA_ISLANDS) 1903 .Case("kaveri", GK_SEA_ISLANDS) 1904 .Case("hawaii", GK_SEA_ISLANDS) 1905 .Case("mullins", GK_SEA_ISLANDS) 1906 .Case("tonga", GK_VOLCANIC_ISLANDS) 1907 .Case("iceland", GK_VOLCANIC_ISLANDS) 1908 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1909 .Default(GK_NONE); 1910 1911 if (GPU == GK_NONE) { 1912 return false; 1913 } 1914 1915 // Set the correct data layout 1916 switch (GPU) { 1917 case GK_NONE: 1918 case GK_R600: 1919 case GK_R700: 1920 case GK_EVERGREEN: 1921 case GK_NORTHERN_ISLANDS: 1922 DataLayoutString = DataLayoutStringR600; 1923 hasFP64 = false; 1924 hasFMAF = false; 1925 hasLDEXPF = false; 1926 break; 1927 case GK_R600_DOUBLE_OPS: 1928 case GK_R700_DOUBLE_OPS: 1929 case GK_EVERGREEN_DOUBLE_OPS: 1930 case GK_CAYMAN: 1931 DataLayoutString = DataLayoutStringR600DoubleOps; 1932 hasFP64 = true; 1933 hasFMAF = true; 1934 hasLDEXPF = false; 1935 break; 1936 case GK_SOUTHERN_ISLANDS: 1937 case GK_SEA_ISLANDS: 1938 case GK_VOLCANIC_ISLANDS: 1939 DataLayoutString = DataLayoutStringSI; 1940 hasFP64 = true; 1941 hasFMAF = true; 1942 hasLDEXPF = true; 1943 break; 1944 } 1945 1946 return true; 1947 } 1948 }; 1949 1950 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1951 #define BUILTIN(ID, TYPE, ATTRS) \ 1952 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1953 #include "clang/Basic/BuiltinsAMDGPU.def" 1954 }; 1955 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1956 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1957 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1958 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1959 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1960 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1961 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1962 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1963 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1964 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1965 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1966 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1967 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1968 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1969 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1970 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1971 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1972 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1973 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1974 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1975 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 1976 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 1977 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 1978 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 1979 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 1980 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 1981 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 1982 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 1983 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 1984 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 1985 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 1986 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 1987 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 1988 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 1989 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 1990 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 1991 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 1992 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 1993 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 1994 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 1995 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 1996 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 1997 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 1998 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 1999 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2000 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2001 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2002 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2003 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127" 2004 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi", 2005 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi" 2006 }; 2007 2008 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2009 return llvm::makeArrayRef(GCCRegNames); 2010 } 2011 2012 // Namespace for x86 abstract base class 2013 const Builtin::Info BuiltinInfo[] = { 2014 #define BUILTIN(ID, TYPE, ATTRS) \ 2015 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2016 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2017 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2018 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2019 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2020 #include "clang/Basic/BuiltinsX86.def" 2021 }; 2022 2023 static const char* const GCCRegNames[] = { 2024 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2025 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2026 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2027 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2028 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2029 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2030 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2031 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2032 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2033 }; 2034 2035 const TargetInfo::AddlRegName AddlRegNames[] = { 2036 { { "al", "ah", "eax", "rax" }, 0 }, 2037 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2038 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2039 { { "dl", "dh", "edx", "rdx" }, 1 }, 2040 { { "esi", "rsi" }, 4 }, 2041 { { "edi", "rdi" }, 5 }, 2042 { { "esp", "rsp" }, 7 }, 2043 { { "ebp", "rbp" }, 6 }, 2044 { { "r8d", "r8w", "r8b" }, 38 }, 2045 { { "r9d", "r9w", "r9b" }, 39 }, 2046 { { "r10d", "r10w", "r10b" }, 40 }, 2047 { { "r11d", "r11w", "r11b" }, 41 }, 2048 { { "r12d", "r12w", "r12b" }, 42 }, 2049 { { "r13d", "r13w", "r13b" }, 43 }, 2050 { { "r14d", "r14w", "r14b" }, 44 }, 2051 { { "r15d", "r15w", "r15b" }, 45 }, 2052 }; 2053 2054 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2055 // most of the implementation can be shared. 2056 class X86TargetInfo : public TargetInfo { 2057 enum X86SSEEnum { 2058 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2059 } SSELevel = NoSSE; 2060 enum MMX3DNowEnum { 2061 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2062 } MMX3DNowLevel = NoMMX3DNow; 2063 enum XOPEnum { 2064 NoXOP, 2065 SSE4A, 2066 FMA4, 2067 XOP 2068 } XOPLevel = NoXOP; 2069 2070 bool HasAES = false; 2071 bool HasPCLMUL = false; 2072 bool HasLZCNT = false; 2073 bool HasRDRND = false; 2074 bool HasFSGSBASE = false; 2075 bool HasBMI = false; 2076 bool HasBMI2 = false; 2077 bool HasPOPCNT = false; 2078 bool HasRTM = false; 2079 bool HasPRFCHW = false; 2080 bool HasRDSEED = false; 2081 bool HasADX = false; 2082 bool HasTBM = false; 2083 bool HasFMA = false; 2084 bool HasF16C = false; 2085 bool HasAVX512CD = false; 2086 bool HasAVX512ER = false; 2087 bool HasAVX512PF = false; 2088 bool HasAVX512DQ = false; 2089 bool HasAVX512BW = false; 2090 bool HasAVX512VL = false; 2091 bool HasSHA = false; 2092 bool HasCX16 = false; 2093 bool HasFXSR = false; 2094 bool HasXSAVE = false; 2095 bool HasXSAVEOPT = false; 2096 bool HasXSAVEC = false; 2097 bool HasXSAVES = false; 2098 2099 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2100 /// 2101 /// Each enumeration represents a particular CPU supported by Clang. These 2102 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2103 enum CPUKind { 2104 CK_Generic, 2105 2106 /// \name i386 2107 /// i386-generation processors. 2108 //@{ 2109 CK_i386, 2110 //@} 2111 2112 /// \name i486 2113 /// i486-generation processors. 2114 //@{ 2115 CK_i486, 2116 CK_WinChipC6, 2117 CK_WinChip2, 2118 CK_C3, 2119 //@} 2120 2121 /// \name i586 2122 /// i586-generation processors, P5 microarchitecture based. 2123 //@{ 2124 CK_i586, 2125 CK_Pentium, 2126 CK_PentiumMMX, 2127 //@} 2128 2129 /// \name i686 2130 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2131 //@{ 2132 CK_i686, 2133 CK_PentiumPro, 2134 CK_Pentium2, 2135 CK_Pentium3, 2136 CK_Pentium3M, 2137 CK_PentiumM, 2138 CK_C3_2, 2139 2140 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2141 /// Clang however has some logic to suport this. 2142 // FIXME: Warn, deprecate, and potentially remove this. 2143 CK_Yonah, 2144 //@} 2145 2146 /// \name Netburst 2147 /// Netburst microarchitecture based processors. 2148 //@{ 2149 CK_Pentium4, 2150 CK_Pentium4M, 2151 CK_Prescott, 2152 CK_Nocona, 2153 //@} 2154 2155 /// \name Core 2156 /// Core microarchitecture based processors. 2157 //@{ 2158 CK_Core2, 2159 2160 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2161 /// codename which GCC no longer accepts as an option to -march, but Clang 2162 /// has some logic for recognizing it. 2163 // FIXME: Warn, deprecate, and potentially remove this. 2164 CK_Penryn, 2165 //@} 2166 2167 /// \name Atom 2168 /// Atom processors 2169 //@{ 2170 CK_Bonnell, 2171 CK_Silvermont, 2172 //@} 2173 2174 /// \name Nehalem 2175 /// Nehalem microarchitecture based processors. 2176 CK_Nehalem, 2177 2178 /// \name Westmere 2179 /// Westmere microarchitecture based processors. 2180 CK_Westmere, 2181 2182 /// \name Sandy Bridge 2183 /// Sandy Bridge microarchitecture based processors. 2184 CK_SandyBridge, 2185 2186 /// \name Ivy Bridge 2187 /// Ivy Bridge microarchitecture based processors. 2188 CK_IvyBridge, 2189 2190 /// \name Haswell 2191 /// Haswell microarchitecture based processors. 2192 CK_Haswell, 2193 2194 /// \name Broadwell 2195 /// Broadwell microarchitecture based processors. 2196 CK_Broadwell, 2197 2198 /// \name Skylake 2199 /// Skylake microarchitecture based processors. 2200 CK_Skylake, 2201 2202 /// \name Knights Landing 2203 /// Knights Landing processor. 2204 CK_KNL, 2205 2206 /// \name K6 2207 /// K6 architecture processors. 2208 //@{ 2209 CK_K6, 2210 CK_K6_2, 2211 CK_K6_3, 2212 //@} 2213 2214 /// \name K7 2215 /// K7 architecture processors. 2216 //@{ 2217 CK_Athlon, 2218 CK_AthlonThunderbird, 2219 CK_Athlon4, 2220 CK_AthlonXP, 2221 CK_AthlonMP, 2222 //@} 2223 2224 /// \name K8 2225 /// K8 architecture processors. 2226 //@{ 2227 CK_Athlon64, 2228 CK_Athlon64SSE3, 2229 CK_AthlonFX, 2230 CK_K8, 2231 CK_K8SSE3, 2232 CK_Opteron, 2233 CK_OpteronSSE3, 2234 CK_AMDFAM10, 2235 //@} 2236 2237 /// \name Bobcat 2238 /// Bobcat architecture processors. 2239 //@{ 2240 CK_BTVER1, 2241 CK_BTVER2, 2242 //@} 2243 2244 /// \name Bulldozer 2245 /// Bulldozer architecture processors. 2246 //@{ 2247 CK_BDVER1, 2248 CK_BDVER2, 2249 CK_BDVER3, 2250 CK_BDVER4, 2251 //@} 2252 2253 /// This specification is deprecated and will be removed in the future. 2254 /// Users should prefer \see CK_K8. 2255 // FIXME: Warn on this when the CPU is set to it. 2256 //@{ 2257 CK_x86_64, 2258 //@} 2259 2260 /// \name Geode 2261 /// Geode processors. 2262 //@{ 2263 CK_Geode 2264 //@} 2265 } CPU = CK_Generic; 2266 2267 CPUKind getCPUKind(StringRef CPU) const { 2268 return llvm::StringSwitch<CPUKind>(CPU) 2269 .Case("i386", CK_i386) 2270 .Case("i486", CK_i486) 2271 .Case("winchip-c6", CK_WinChipC6) 2272 .Case("winchip2", CK_WinChip2) 2273 .Case("c3", CK_C3) 2274 .Case("i586", CK_i586) 2275 .Case("pentium", CK_Pentium) 2276 .Case("pentium-mmx", CK_PentiumMMX) 2277 .Case("i686", CK_i686) 2278 .Case("pentiumpro", CK_PentiumPro) 2279 .Case("pentium2", CK_Pentium2) 2280 .Case("pentium3", CK_Pentium3) 2281 .Case("pentium3m", CK_Pentium3M) 2282 .Case("pentium-m", CK_PentiumM) 2283 .Case("c3-2", CK_C3_2) 2284 .Case("yonah", CK_Yonah) 2285 .Case("pentium4", CK_Pentium4) 2286 .Case("pentium4m", CK_Pentium4M) 2287 .Case("prescott", CK_Prescott) 2288 .Case("nocona", CK_Nocona) 2289 .Case("core2", CK_Core2) 2290 .Case("penryn", CK_Penryn) 2291 .Case("bonnell", CK_Bonnell) 2292 .Case("atom", CK_Bonnell) // Legacy name. 2293 .Case("silvermont", CK_Silvermont) 2294 .Case("slm", CK_Silvermont) // Legacy name. 2295 .Case("nehalem", CK_Nehalem) 2296 .Case("corei7", CK_Nehalem) // Legacy name. 2297 .Case("westmere", CK_Westmere) 2298 .Case("sandybridge", CK_SandyBridge) 2299 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2300 .Case("ivybridge", CK_IvyBridge) 2301 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2302 .Case("haswell", CK_Haswell) 2303 .Case("core-avx2", CK_Haswell) // Legacy name. 2304 .Case("broadwell", CK_Broadwell) 2305 .Case("skylake", CK_Skylake) 2306 .Case("skx", CK_Skylake) // Legacy name. 2307 .Case("knl", CK_KNL) 2308 .Case("k6", CK_K6) 2309 .Case("k6-2", CK_K6_2) 2310 .Case("k6-3", CK_K6_3) 2311 .Case("athlon", CK_Athlon) 2312 .Case("athlon-tbird", CK_AthlonThunderbird) 2313 .Case("athlon-4", CK_Athlon4) 2314 .Case("athlon-xp", CK_AthlonXP) 2315 .Case("athlon-mp", CK_AthlonMP) 2316 .Case("athlon64", CK_Athlon64) 2317 .Case("athlon64-sse3", CK_Athlon64SSE3) 2318 .Case("athlon-fx", CK_AthlonFX) 2319 .Case("k8", CK_K8) 2320 .Case("k8-sse3", CK_K8SSE3) 2321 .Case("opteron", CK_Opteron) 2322 .Case("opteron-sse3", CK_OpteronSSE3) 2323 .Case("barcelona", CK_AMDFAM10) 2324 .Case("amdfam10", CK_AMDFAM10) 2325 .Case("btver1", CK_BTVER1) 2326 .Case("btver2", CK_BTVER2) 2327 .Case("bdver1", CK_BDVER1) 2328 .Case("bdver2", CK_BDVER2) 2329 .Case("bdver3", CK_BDVER3) 2330 .Case("bdver4", CK_BDVER4) 2331 .Case("x86-64", CK_x86_64) 2332 .Case("geode", CK_Geode) 2333 .Default(CK_Generic); 2334 } 2335 2336 enum FPMathKind { 2337 FP_Default, 2338 FP_SSE, 2339 FP_387 2340 } FPMath = FP_Default; 2341 2342 public: 2343 X86TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 2344 BigEndian = false; 2345 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2346 } 2347 unsigned getFloatEvalMethod() const override { 2348 // X87 evaluates with 80 bits "long double" precision. 2349 return SSELevel == NoSSE ? 2 : 0; 2350 } 2351 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2352 return llvm::makeArrayRef(BuiltinInfo, 2353 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2354 } 2355 ArrayRef<const char *> getGCCRegNames() const override { 2356 return llvm::makeArrayRef(GCCRegNames); 2357 } 2358 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2359 return None; 2360 } 2361 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2362 return llvm::makeArrayRef(AddlRegNames); 2363 } 2364 bool validateCpuSupports(StringRef Name) const override; 2365 bool validateAsmConstraint(const char *&Name, 2366 TargetInfo::ConstraintInfo &info) const override; 2367 2368 bool validateGlobalRegisterVariable(StringRef RegName, 2369 unsigned RegSize, 2370 bool &HasSizeMismatch) const override { 2371 // esp and ebp are the only 32-bit registers the x86 backend can currently 2372 // handle. 2373 if (RegName.equals("esp") || RegName.equals("ebp")) { 2374 // Check that the register size is 32-bit. 2375 HasSizeMismatch = RegSize != 32; 2376 return true; 2377 } 2378 2379 return false; 2380 } 2381 2382 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2383 2384 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2385 2386 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2387 2388 std::string convertConstraint(const char *&Constraint) const override; 2389 const char *getClobbers() const override { 2390 return "~{dirflag},~{fpsr},~{flags}"; 2391 } 2392 void getTargetDefines(const LangOptions &Opts, 2393 MacroBuilder &Builder) const override; 2394 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2395 bool Enabled); 2396 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2397 bool Enabled); 2398 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2399 bool Enabled); 2400 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2401 StringRef Name, bool Enabled) const override { 2402 setFeatureEnabledImpl(Features, Name, Enabled); 2403 } 2404 // This exists purely to cut down on the number of virtual calls in 2405 // initFeatureMap which calls this repeatedly. 2406 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2407 StringRef Name, bool Enabled); 2408 bool 2409 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2410 StringRef CPU, 2411 const std::vector<std::string> &FeaturesVec) const override; 2412 bool hasFeature(StringRef Feature) const override; 2413 bool handleTargetFeatures(std::vector<std::string> &Features, 2414 DiagnosticsEngine &Diags) override; 2415 StringRef getABI() const override { 2416 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2417 return "avx512"; 2418 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2419 return "avx"; 2420 if (getTriple().getArch() == llvm::Triple::x86 && 2421 MMX3DNowLevel == NoMMX3DNow) 2422 return "no-mmx"; 2423 return ""; 2424 } 2425 bool setCPU(const std::string &Name) override { 2426 CPU = getCPUKind(Name); 2427 2428 // Perform any per-CPU checks necessary to determine if this CPU is 2429 // acceptable. 2430 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2431 // invalid without explaining *why*. 2432 switch (CPU) { 2433 case CK_Generic: 2434 // No processor selected! 2435 return false; 2436 2437 case CK_i386: 2438 case CK_i486: 2439 case CK_WinChipC6: 2440 case CK_WinChip2: 2441 case CK_C3: 2442 case CK_i586: 2443 case CK_Pentium: 2444 case CK_PentiumMMX: 2445 case CK_i686: 2446 case CK_PentiumPro: 2447 case CK_Pentium2: 2448 case CK_Pentium3: 2449 case CK_Pentium3M: 2450 case CK_PentiumM: 2451 case CK_Yonah: 2452 case CK_C3_2: 2453 case CK_Pentium4: 2454 case CK_Pentium4M: 2455 case CK_Prescott: 2456 case CK_K6: 2457 case CK_K6_2: 2458 case CK_K6_3: 2459 case CK_Athlon: 2460 case CK_AthlonThunderbird: 2461 case CK_Athlon4: 2462 case CK_AthlonXP: 2463 case CK_AthlonMP: 2464 case CK_Geode: 2465 // Only accept certain architectures when compiling in 32-bit mode. 2466 if (getTriple().getArch() != llvm::Triple::x86) 2467 return false; 2468 2469 // Fallthrough 2470 case CK_Nocona: 2471 case CK_Core2: 2472 case CK_Penryn: 2473 case CK_Bonnell: 2474 case CK_Silvermont: 2475 case CK_Nehalem: 2476 case CK_Westmere: 2477 case CK_SandyBridge: 2478 case CK_IvyBridge: 2479 case CK_Haswell: 2480 case CK_Broadwell: 2481 case CK_Skylake: 2482 case CK_KNL: 2483 case CK_Athlon64: 2484 case CK_Athlon64SSE3: 2485 case CK_AthlonFX: 2486 case CK_K8: 2487 case CK_K8SSE3: 2488 case CK_Opteron: 2489 case CK_OpteronSSE3: 2490 case CK_AMDFAM10: 2491 case CK_BTVER1: 2492 case CK_BTVER2: 2493 case CK_BDVER1: 2494 case CK_BDVER2: 2495 case CK_BDVER3: 2496 case CK_BDVER4: 2497 case CK_x86_64: 2498 return true; 2499 } 2500 llvm_unreachable("Unhandled CPU kind"); 2501 } 2502 2503 bool setFPMath(StringRef Name) override; 2504 2505 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2506 // We accept all non-ARM calling conventions 2507 return (CC == CC_X86ThisCall || 2508 CC == CC_X86FastCall || 2509 CC == CC_X86StdCall || 2510 CC == CC_X86VectorCall || 2511 CC == CC_C || 2512 CC == CC_X86Pascal || 2513 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2514 } 2515 2516 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2517 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2518 } 2519 2520 bool hasSjLjLowering() const override { 2521 return true; 2522 } 2523 }; 2524 2525 bool X86TargetInfo::setFPMath(StringRef Name) { 2526 if (Name == "387") { 2527 FPMath = FP_387; 2528 return true; 2529 } 2530 if (Name == "sse") { 2531 FPMath = FP_SSE; 2532 return true; 2533 } 2534 return false; 2535 } 2536 2537 bool X86TargetInfo::initFeatureMap( 2538 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2539 const std::vector<std::string> &FeaturesVec) const { 2540 // FIXME: This *really* should not be here. 2541 // X86_64 always has SSE2. 2542 if (getTriple().getArch() == llvm::Triple::x86_64) 2543 setFeatureEnabledImpl(Features, "sse2", true); 2544 2545 switch (getCPUKind(CPU)) { 2546 case CK_Generic: 2547 case CK_i386: 2548 case CK_i486: 2549 case CK_i586: 2550 case CK_Pentium: 2551 case CK_i686: 2552 case CK_PentiumPro: 2553 break; 2554 case CK_PentiumMMX: 2555 case CK_Pentium2: 2556 case CK_K6: 2557 case CK_WinChipC6: 2558 setFeatureEnabledImpl(Features, "mmx", true); 2559 break; 2560 case CK_Pentium3: 2561 case CK_Pentium3M: 2562 case CK_C3_2: 2563 setFeatureEnabledImpl(Features, "sse", true); 2564 setFeatureEnabledImpl(Features, "fxsr", true); 2565 break; 2566 case CK_PentiumM: 2567 case CK_Pentium4: 2568 case CK_Pentium4M: 2569 case CK_x86_64: 2570 setFeatureEnabledImpl(Features, "sse2", true); 2571 setFeatureEnabledImpl(Features, "fxsr", true); 2572 break; 2573 case CK_Yonah: 2574 case CK_Prescott: 2575 case CK_Nocona: 2576 setFeatureEnabledImpl(Features, "sse3", true); 2577 setFeatureEnabledImpl(Features, "fxsr", true); 2578 setFeatureEnabledImpl(Features, "cx16", true); 2579 break; 2580 case CK_Core2: 2581 case CK_Bonnell: 2582 setFeatureEnabledImpl(Features, "ssse3", true); 2583 setFeatureEnabledImpl(Features, "fxsr", true); 2584 setFeatureEnabledImpl(Features, "cx16", true); 2585 break; 2586 case CK_Penryn: 2587 setFeatureEnabledImpl(Features, "sse4.1", true); 2588 setFeatureEnabledImpl(Features, "fxsr", true); 2589 setFeatureEnabledImpl(Features, "cx16", true); 2590 break; 2591 case CK_Skylake: 2592 setFeatureEnabledImpl(Features, "avx512f", true); 2593 setFeatureEnabledImpl(Features, "avx512cd", true); 2594 setFeatureEnabledImpl(Features, "avx512dq", true); 2595 setFeatureEnabledImpl(Features, "avx512bw", true); 2596 setFeatureEnabledImpl(Features, "avx512vl", true); 2597 setFeatureEnabledImpl(Features, "xsavec", true); 2598 setFeatureEnabledImpl(Features, "xsaves", true); 2599 // FALLTHROUGH 2600 case CK_Broadwell: 2601 setFeatureEnabledImpl(Features, "rdseed", true); 2602 setFeatureEnabledImpl(Features, "adx", true); 2603 // FALLTHROUGH 2604 case CK_Haswell: 2605 setFeatureEnabledImpl(Features, "avx2", true); 2606 setFeatureEnabledImpl(Features, "lzcnt", true); 2607 setFeatureEnabledImpl(Features, "bmi", true); 2608 setFeatureEnabledImpl(Features, "bmi2", true); 2609 setFeatureEnabledImpl(Features, "rtm", true); 2610 setFeatureEnabledImpl(Features, "fma", true); 2611 // FALLTHROUGH 2612 case CK_IvyBridge: 2613 setFeatureEnabledImpl(Features, "rdrnd", true); 2614 setFeatureEnabledImpl(Features, "f16c", true); 2615 setFeatureEnabledImpl(Features, "fsgsbase", true); 2616 // FALLTHROUGH 2617 case CK_SandyBridge: 2618 setFeatureEnabledImpl(Features, "avx", true); 2619 setFeatureEnabledImpl(Features, "xsave", true); 2620 setFeatureEnabledImpl(Features, "xsaveopt", true); 2621 // FALLTHROUGH 2622 case CK_Westmere: 2623 case CK_Silvermont: 2624 setFeatureEnabledImpl(Features, "aes", true); 2625 setFeatureEnabledImpl(Features, "pclmul", true); 2626 // FALLTHROUGH 2627 case CK_Nehalem: 2628 setFeatureEnabledImpl(Features, "sse4.2", true); 2629 setFeatureEnabledImpl(Features, "fxsr", true); 2630 setFeatureEnabledImpl(Features, "cx16", true); 2631 break; 2632 case CK_KNL: 2633 setFeatureEnabledImpl(Features, "avx512f", true); 2634 setFeatureEnabledImpl(Features, "avx512cd", true); 2635 setFeatureEnabledImpl(Features, "avx512er", true); 2636 setFeatureEnabledImpl(Features, "avx512pf", true); 2637 setFeatureEnabledImpl(Features, "fxsr", true); 2638 setFeatureEnabledImpl(Features, "rdseed", true); 2639 setFeatureEnabledImpl(Features, "adx", true); 2640 setFeatureEnabledImpl(Features, "lzcnt", true); 2641 setFeatureEnabledImpl(Features, "bmi", true); 2642 setFeatureEnabledImpl(Features, "bmi2", true); 2643 setFeatureEnabledImpl(Features, "rtm", true); 2644 setFeatureEnabledImpl(Features, "fma", true); 2645 setFeatureEnabledImpl(Features, "rdrnd", true); 2646 setFeatureEnabledImpl(Features, "f16c", true); 2647 setFeatureEnabledImpl(Features, "fsgsbase", true); 2648 setFeatureEnabledImpl(Features, "aes", true); 2649 setFeatureEnabledImpl(Features, "pclmul", true); 2650 setFeatureEnabledImpl(Features, "cx16", true); 2651 setFeatureEnabledImpl(Features, "xsaveopt", true); 2652 setFeatureEnabledImpl(Features, "xsave", true); 2653 break; 2654 case CK_K6_2: 2655 case CK_K6_3: 2656 case CK_WinChip2: 2657 case CK_C3: 2658 setFeatureEnabledImpl(Features, "3dnow", true); 2659 break; 2660 case CK_Athlon: 2661 case CK_AthlonThunderbird: 2662 case CK_Geode: 2663 setFeatureEnabledImpl(Features, "3dnowa", true); 2664 break; 2665 case CK_Athlon4: 2666 case CK_AthlonXP: 2667 case CK_AthlonMP: 2668 setFeatureEnabledImpl(Features, "sse", true); 2669 setFeatureEnabledImpl(Features, "3dnowa", true); 2670 setFeatureEnabledImpl(Features, "fxsr", true); 2671 break; 2672 case CK_K8: 2673 case CK_Opteron: 2674 case CK_Athlon64: 2675 case CK_AthlonFX: 2676 setFeatureEnabledImpl(Features, "sse2", true); 2677 setFeatureEnabledImpl(Features, "3dnowa", true); 2678 setFeatureEnabledImpl(Features, "fxsr", true); 2679 break; 2680 case CK_AMDFAM10: 2681 setFeatureEnabledImpl(Features, "sse4a", true); 2682 setFeatureEnabledImpl(Features, "lzcnt", true); 2683 setFeatureEnabledImpl(Features, "popcnt", true); 2684 // FALLTHROUGH 2685 case CK_K8SSE3: 2686 case CK_OpteronSSE3: 2687 case CK_Athlon64SSE3: 2688 setFeatureEnabledImpl(Features, "sse3", true); 2689 setFeatureEnabledImpl(Features, "3dnowa", true); 2690 setFeatureEnabledImpl(Features, "fxsr", true); 2691 break; 2692 case CK_BTVER2: 2693 setFeatureEnabledImpl(Features, "avx", true); 2694 setFeatureEnabledImpl(Features, "aes", true); 2695 setFeatureEnabledImpl(Features, "pclmul", true); 2696 setFeatureEnabledImpl(Features, "bmi", true); 2697 setFeatureEnabledImpl(Features, "f16c", true); 2698 setFeatureEnabledImpl(Features, "xsaveopt", true); 2699 // FALLTHROUGH 2700 case CK_BTVER1: 2701 setFeatureEnabledImpl(Features, "ssse3", true); 2702 setFeatureEnabledImpl(Features, "sse4a", true); 2703 setFeatureEnabledImpl(Features, "lzcnt", true); 2704 setFeatureEnabledImpl(Features, "popcnt", true); 2705 setFeatureEnabledImpl(Features, "prfchw", true); 2706 setFeatureEnabledImpl(Features, "cx16", true); 2707 setFeatureEnabledImpl(Features, "fxsr", true); 2708 setFeatureEnabledImpl(Features, "xsave", true); 2709 break; 2710 case CK_BDVER4: 2711 setFeatureEnabledImpl(Features, "avx2", true); 2712 setFeatureEnabledImpl(Features, "bmi2", true); 2713 // FALLTHROUGH 2714 case CK_BDVER3: 2715 setFeatureEnabledImpl(Features, "fsgsbase", true); 2716 setFeatureEnabledImpl(Features, "xsaveopt", true); 2717 // FALLTHROUGH 2718 case CK_BDVER2: 2719 setFeatureEnabledImpl(Features, "bmi", true); 2720 setFeatureEnabledImpl(Features, "fma", true); 2721 setFeatureEnabledImpl(Features, "f16c", true); 2722 setFeatureEnabledImpl(Features, "tbm", true); 2723 // FALLTHROUGH 2724 case CK_BDVER1: 2725 // xop implies avx, sse4a and fma4. 2726 setFeatureEnabledImpl(Features, "xop", true); 2727 setFeatureEnabledImpl(Features, "lzcnt", true); 2728 setFeatureEnabledImpl(Features, "aes", true); 2729 setFeatureEnabledImpl(Features, "pclmul", true); 2730 setFeatureEnabledImpl(Features, "prfchw", true); 2731 setFeatureEnabledImpl(Features, "cx16", true); 2732 setFeatureEnabledImpl(Features, "fxsr", true); 2733 setFeatureEnabledImpl(Features, "xsave", true); 2734 break; 2735 } 2736 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 2737 return false; 2738 2739 // Can't do this earlier because we need to be able to explicitly enable 2740 // or disable these features and the things that they depend upon. 2741 2742 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2743 auto I = Features.find("sse4.2"); 2744 if (I != Features.end() && I->getValue() && 2745 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 2746 FeaturesVec.end()) 2747 Features["popcnt"] = true; 2748 2749 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2750 I = Features.find("3dnow"); 2751 if (I != Features.end() && I->getValue() && 2752 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 2753 FeaturesVec.end()) 2754 Features["prfchw"] = true; 2755 2756 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2757 // then enable MMX. 2758 I = Features.find("sse"); 2759 if (I != Features.end() && I->getValue() && 2760 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 2761 FeaturesVec.end()) 2762 Features["mmx"] = true; 2763 2764 return true; 2765 } 2766 2767 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2768 X86SSEEnum Level, bool Enabled) { 2769 if (Enabled) { 2770 switch (Level) { 2771 case AVX512F: 2772 Features["avx512f"] = true; 2773 case AVX2: 2774 Features["avx2"] = true; 2775 case AVX: 2776 Features["avx"] = true; 2777 Features["xsave"] = true; 2778 case SSE42: 2779 Features["sse4.2"] = true; 2780 case SSE41: 2781 Features["sse4.1"] = true; 2782 case SSSE3: 2783 Features["ssse3"] = true; 2784 case SSE3: 2785 Features["sse3"] = true; 2786 case SSE2: 2787 Features["sse2"] = true; 2788 case SSE1: 2789 Features["sse"] = true; 2790 case NoSSE: 2791 break; 2792 } 2793 return; 2794 } 2795 2796 switch (Level) { 2797 case NoSSE: 2798 case SSE1: 2799 Features["sse"] = false; 2800 case SSE2: 2801 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2802 Features["sha"] = false; 2803 case SSE3: 2804 Features["sse3"] = false; 2805 setXOPLevel(Features, NoXOP, false); 2806 case SSSE3: 2807 Features["ssse3"] = false; 2808 case SSE41: 2809 Features["sse4.1"] = false; 2810 case SSE42: 2811 Features["sse4.2"] = false; 2812 case AVX: 2813 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 2814 Features["xsaveopt"] = false; 2815 setXOPLevel(Features, FMA4, false); 2816 case AVX2: 2817 Features["avx2"] = false; 2818 case AVX512F: 2819 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2820 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2821 Features["avx512vl"] = false; 2822 } 2823 } 2824 2825 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2826 MMX3DNowEnum Level, bool Enabled) { 2827 if (Enabled) { 2828 switch (Level) { 2829 case AMD3DNowAthlon: 2830 Features["3dnowa"] = true; 2831 case AMD3DNow: 2832 Features["3dnow"] = true; 2833 case MMX: 2834 Features["mmx"] = true; 2835 case NoMMX3DNow: 2836 break; 2837 } 2838 return; 2839 } 2840 2841 switch (Level) { 2842 case NoMMX3DNow: 2843 case MMX: 2844 Features["mmx"] = false; 2845 case AMD3DNow: 2846 Features["3dnow"] = false; 2847 case AMD3DNowAthlon: 2848 Features["3dnowa"] = false; 2849 } 2850 } 2851 2852 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2853 bool Enabled) { 2854 if (Enabled) { 2855 switch (Level) { 2856 case XOP: 2857 Features["xop"] = true; 2858 case FMA4: 2859 Features["fma4"] = true; 2860 setSSELevel(Features, AVX, true); 2861 case SSE4A: 2862 Features["sse4a"] = true; 2863 setSSELevel(Features, SSE3, true); 2864 case NoXOP: 2865 break; 2866 } 2867 return; 2868 } 2869 2870 switch (Level) { 2871 case NoXOP: 2872 case SSE4A: 2873 Features["sse4a"] = false; 2874 case FMA4: 2875 Features["fma4"] = false; 2876 case XOP: 2877 Features["xop"] = false; 2878 } 2879 } 2880 2881 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2882 StringRef Name, bool Enabled) { 2883 // This is a bit of a hack to deal with the sse4 target feature when used 2884 // as part of the target attribute. We handle sse4 correctly everywhere 2885 // else. See below for more information on how we handle the sse4 options. 2886 if (Name != "sse4") 2887 Features[Name] = Enabled; 2888 2889 if (Name == "mmx") { 2890 setMMXLevel(Features, MMX, Enabled); 2891 } else if (Name == "sse") { 2892 setSSELevel(Features, SSE1, Enabled); 2893 } else if (Name == "sse2") { 2894 setSSELevel(Features, SSE2, Enabled); 2895 } else if (Name == "sse3") { 2896 setSSELevel(Features, SSE3, Enabled); 2897 } else if (Name == "ssse3") { 2898 setSSELevel(Features, SSSE3, Enabled); 2899 } else if (Name == "sse4.2") { 2900 setSSELevel(Features, SSE42, Enabled); 2901 } else if (Name == "sse4.1") { 2902 setSSELevel(Features, SSE41, Enabled); 2903 } else if (Name == "3dnow") { 2904 setMMXLevel(Features, AMD3DNow, Enabled); 2905 } else if (Name == "3dnowa") { 2906 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2907 } else if (Name == "aes") { 2908 if (Enabled) 2909 setSSELevel(Features, SSE2, Enabled); 2910 } else if (Name == "pclmul") { 2911 if (Enabled) 2912 setSSELevel(Features, SSE2, Enabled); 2913 } else if (Name == "avx") { 2914 setSSELevel(Features, AVX, Enabled); 2915 } else if (Name == "avx2") { 2916 setSSELevel(Features, AVX2, Enabled); 2917 } else if (Name == "avx512f") { 2918 setSSELevel(Features, AVX512F, Enabled); 2919 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2920 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2921 if (Enabled) 2922 setSSELevel(Features, AVX512F, Enabled); 2923 } else if (Name == "fma") { 2924 if (Enabled) 2925 setSSELevel(Features, AVX, Enabled); 2926 } else if (Name == "fma4") { 2927 setXOPLevel(Features, FMA4, Enabled); 2928 } else if (Name == "xop") { 2929 setXOPLevel(Features, XOP, Enabled); 2930 } else if (Name == "sse4a") { 2931 setXOPLevel(Features, SSE4A, Enabled); 2932 } else if (Name == "f16c") { 2933 if (Enabled) 2934 setSSELevel(Features, AVX, Enabled); 2935 } else if (Name == "sha") { 2936 if (Enabled) 2937 setSSELevel(Features, SSE2, Enabled); 2938 } else if (Name == "sse4") { 2939 // We can get here via the __target__ attribute since that's not controlled 2940 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 2941 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 2942 // disabled. 2943 if (Enabled) 2944 setSSELevel(Features, SSE42, Enabled); 2945 else 2946 setSSELevel(Features, SSE41, Enabled); 2947 } else if (Name == "xsave") { 2948 if (Enabled) 2949 setSSELevel(Features, AVX, Enabled); 2950 else 2951 Features["xsaveopt"] = false; 2952 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 2953 if (Enabled) { 2954 Features["xsave"] = true; 2955 setSSELevel(Features, AVX, Enabled); 2956 } 2957 } 2958 } 2959 2960 /// handleTargetFeatures - Perform initialization based on the user 2961 /// configured set of features. 2962 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2963 DiagnosticsEngine &Diags) { 2964 for (const auto &Feature : Features) { 2965 if (Feature[0] != '+') 2966 continue; 2967 2968 if (Feature == "+aes") { 2969 HasAES = true; 2970 } else if (Feature == "+pclmul") { 2971 HasPCLMUL = true; 2972 } else if (Feature == "+lzcnt") { 2973 HasLZCNT = true; 2974 } else if (Feature == "+rdrnd") { 2975 HasRDRND = true; 2976 } else if (Feature == "+fsgsbase") { 2977 HasFSGSBASE = true; 2978 } else if (Feature == "+bmi") { 2979 HasBMI = true; 2980 } else if (Feature == "+bmi2") { 2981 HasBMI2 = true; 2982 } else if (Feature == "+popcnt") { 2983 HasPOPCNT = true; 2984 } else if (Feature == "+rtm") { 2985 HasRTM = true; 2986 } else if (Feature == "+prfchw") { 2987 HasPRFCHW = true; 2988 } else if (Feature == "+rdseed") { 2989 HasRDSEED = true; 2990 } else if (Feature == "+adx") { 2991 HasADX = true; 2992 } else if (Feature == "+tbm") { 2993 HasTBM = true; 2994 } else if (Feature == "+fma") { 2995 HasFMA = true; 2996 } else if (Feature == "+f16c") { 2997 HasF16C = true; 2998 } else if (Feature == "+avx512cd") { 2999 HasAVX512CD = true; 3000 } else if (Feature == "+avx512er") { 3001 HasAVX512ER = true; 3002 } else if (Feature == "+avx512pf") { 3003 HasAVX512PF = true; 3004 } else if (Feature == "+avx512dq") { 3005 HasAVX512DQ = true; 3006 } else if (Feature == "+avx512bw") { 3007 HasAVX512BW = true; 3008 } else if (Feature == "+avx512vl") { 3009 HasAVX512VL = true; 3010 } else if (Feature == "+sha") { 3011 HasSHA = true; 3012 } else if (Feature == "+cx16") { 3013 HasCX16 = true; 3014 } else if (Feature == "+fxsr") { 3015 HasFXSR = true; 3016 } else if (Feature == "+xsave") { 3017 HasXSAVE = true; 3018 } else if (Feature == "+xsaveopt") { 3019 HasXSAVEOPT = true; 3020 } else if (Feature == "+xsavec") { 3021 HasXSAVEC = true; 3022 } else if (Feature == "+xsaves") { 3023 HasXSAVES = true; 3024 } 3025 3026 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3027 .Case("+avx512f", AVX512F) 3028 .Case("+avx2", AVX2) 3029 .Case("+avx", AVX) 3030 .Case("+sse4.2", SSE42) 3031 .Case("+sse4.1", SSE41) 3032 .Case("+ssse3", SSSE3) 3033 .Case("+sse3", SSE3) 3034 .Case("+sse2", SSE2) 3035 .Case("+sse", SSE1) 3036 .Default(NoSSE); 3037 SSELevel = std::max(SSELevel, Level); 3038 3039 MMX3DNowEnum ThreeDNowLevel = 3040 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3041 .Case("+3dnowa", AMD3DNowAthlon) 3042 .Case("+3dnow", AMD3DNow) 3043 .Case("+mmx", MMX) 3044 .Default(NoMMX3DNow); 3045 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3046 3047 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3048 .Case("+xop", XOP) 3049 .Case("+fma4", FMA4) 3050 .Case("+sse4a", SSE4A) 3051 .Default(NoXOP); 3052 XOPLevel = std::max(XOPLevel, XLevel); 3053 } 3054 3055 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3056 // matches the selected sse level. 3057 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3058 (FPMath == FP_387 && SSELevel >= SSE1)) { 3059 Diags.Report(diag::err_target_unsupported_fpmath) << 3060 (FPMath == FP_SSE ? "sse" : "387"); 3061 return false; 3062 } 3063 3064 SimdDefaultAlign = 3065 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3066 return true; 3067 } 3068 3069 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3070 /// definitions for this particular subtarget. 3071 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3072 MacroBuilder &Builder) const { 3073 // Target identification. 3074 if (getTriple().getArch() == llvm::Triple::x86_64) { 3075 Builder.defineMacro("__amd64__"); 3076 Builder.defineMacro("__amd64"); 3077 Builder.defineMacro("__x86_64"); 3078 Builder.defineMacro("__x86_64__"); 3079 if (getTriple().getArchName() == "x86_64h") { 3080 Builder.defineMacro("__x86_64h"); 3081 Builder.defineMacro("__x86_64h__"); 3082 } 3083 } else { 3084 DefineStd(Builder, "i386", Opts); 3085 } 3086 3087 // Subtarget options. 3088 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3089 // truly should be based on -mtune options. 3090 switch (CPU) { 3091 case CK_Generic: 3092 break; 3093 case CK_i386: 3094 // The rest are coming from the i386 define above. 3095 Builder.defineMacro("__tune_i386__"); 3096 break; 3097 case CK_i486: 3098 case CK_WinChipC6: 3099 case CK_WinChip2: 3100 case CK_C3: 3101 defineCPUMacros(Builder, "i486"); 3102 break; 3103 case CK_PentiumMMX: 3104 Builder.defineMacro("__pentium_mmx__"); 3105 Builder.defineMacro("__tune_pentium_mmx__"); 3106 // Fallthrough 3107 case CK_i586: 3108 case CK_Pentium: 3109 defineCPUMacros(Builder, "i586"); 3110 defineCPUMacros(Builder, "pentium"); 3111 break; 3112 case CK_Pentium3: 3113 case CK_Pentium3M: 3114 case CK_PentiumM: 3115 Builder.defineMacro("__tune_pentium3__"); 3116 // Fallthrough 3117 case CK_Pentium2: 3118 case CK_C3_2: 3119 Builder.defineMacro("__tune_pentium2__"); 3120 // Fallthrough 3121 case CK_PentiumPro: 3122 Builder.defineMacro("__tune_i686__"); 3123 Builder.defineMacro("__tune_pentiumpro__"); 3124 // Fallthrough 3125 case CK_i686: 3126 Builder.defineMacro("__i686"); 3127 Builder.defineMacro("__i686__"); 3128 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3129 Builder.defineMacro("__pentiumpro"); 3130 Builder.defineMacro("__pentiumpro__"); 3131 break; 3132 case CK_Pentium4: 3133 case CK_Pentium4M: 3134 defineCPUMacros(Builder, "pentium4"); 3135 break; 3136 case CK_Yonah: 3137 case CK_Prescott: 3138 case CK_Nocona: 3139 defineCPUMacros(Builder, "nocona"); 3140 break; 3141 case CK_Core2: 3142 case CK_Penryn: 3143 defineCPUMacros(Builder, "core2"); 3144 break; 3145 case CK_Bonnell: 3146 defineCPUMacros(Builder, "atom"); 3147 break; 3148 case CK_Silvermont: 3149 defineCPUMacros(Builder, "slm"); 3150 break; 3151 case CK_Nehalem: 3152 case CK_Westmere: 3153 case CK_SandyBridge: 3154 case CK_IvyBridge: 3155 case CK_Haswell: 3156 case CK_Broadwell: 3157 // FIXME: Historically, we defined this legacy name, it would be nice to 3158 // remove it at some point. We've never exposed fine-grained names for 3159 // recent primary x86 CPUs, and we should keep it that way. 3160 defineCPUMacros(Builder, "corei7"); 3161 break; 3162 case CK_Skylake: 3163 // FIXME: Historically, we defined this legacy name, it would be nice to 3164 // remove it at some point. This is the only fine-grained CPU macro in the 3165 // main intel CPU line, and it would be better to not have these and force 3166 // people to use ISA macros. 3167 defineCPUMacros(Builder, "skx"); 3168 break; 3169 case CK_KNL: 3170 defineCPUMacros(Builder, "knl"); 3171 break; 3172 case CK_K6_2: 3173 Builder.defineMacro("__k6_2__"); 3174 Builder.defineMacro("__tune_k6_2__"); 3175 // Fallthrough 3176 case CK_K6_3: 3177 if (CPU != CK_K6_2) { // In case of fallthrough 3178 // FIXME: GCC may be enabling these in cases where some other k6 3179 // architecture is specified but -m3dnow is explicitly provided. The 3180 // exact semantics need to be determined and emulated here. 3181 Builder.defineMacro("__k6_3__"); 3182 Builder.defineMacro("__tune_k6_3__"); 3183 } 3184 // Fallthrough 3185 case CK_K6: 3186 defineCPUMacros(Builder, "k6"); 3187 break; 3188 case CK_Athlon: 3189 case CK_AthlonThunderbird: 3190 case CK_Athlon4: 3191 case CK_AthlonXP: 3192 case CK_AthlonMP: 3193 defineCPUMacros(Builder, "athlon"); 3194 if (SSELevel != NoSSE) { 3195 Builder.defineMacro("__athlon_sse__"); 3196 Builder.defineMacro("__tune_athlon_sse__"); 3197 } 3198 break; 3199 case CK_K8: 3200 case CK_K8SSE3: 3201 case CK_x86_64: 3202 case CK_Opteron: 3203 case CK_OpteronSSE3: 3204 case CK_Athlon64: 3205 case CK_Athlon64SSE3: 3206 case CK_AthlonFX: 3207 defineCPUMacros(Builder, "k8"); 3208 break; 3209 case CK_AMDFAM10: 3210 defineCPUMacros(Builder, "amdfam10"); 3211 break; 3212 case CK_BTVER1: 3213 defineCPUMacros(Builder, "btver1"); 3214 break; 3215 case CK_BTVER2: 3216 defineCPUMacros(Builder, "btver2"); 3217 break; 3218 case CK_BDVER1: 3219 defineCPUMacros(Builder, "bdver1"); 3220 break; 3221 case CK_BDVER2: 3222 defineCPUMacros(Builder, "bdver2"); 3223 break; 3224 case CK_BDVER3: 3225 defineCPUMacros(Builder, "bdver3"); 3226 break; 3227 case CK_BDVER4: 3228 defineCPUMacros(Builder, "bdver4"); 3229 break; 3230 case CK_Geode: 3231 defineCPUMacros(Builder, "geode"); 3232 break; 3233 } 3234 3235 // Target properties. 3236 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3237 3238 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3239 // functions in glibc header files that use FP Stack inline asm which the 3240 // backend can't deal with (PR879). 3241 Builder.defineMacro("__NO_MATH_INLINES"); 3242 3243 if (HasAES) 3244 Builder.defineMacro("__AES__"); 3245 3246 if (HasPCLMUL) 3247 Builder.defineMacro("__PCLMUL__"); 3248 3249 if (HasLZCNT) 3250 Builder.defineMacro("__LZCNT__"); 3251 3252 if (HasRDRND) 3253 Builder.defineMacro("__RDRND__"); 3254 3255 if (HasFSGSBASE) 3256 Builder.defineMacro("__FSGSBASE__"); 3257 3258 if (HasBMI) 3259 Builder.defineMacro("__BMI__"); 3260 3261 if (HasBMI2) 3262 Builder.defineMacro("__BMI2__"); 3263 3264 if (HasPOPCNT) 3265 Builder.defineMacro("__POPCNT__"); 3266 3267 if (HasRTM) 3268 Builder.defineMacro("__RTM__"); 3269 3270 if (HasPRFCHW) 3271 Builder.defineMacro("__PRFCHW__"); 3272 3273 if (HasRDSEED) 3274 Builder.defineMacro("__RDSEED__"); 3275 3276 if (HasADX) 3277 Builder.defineMacro("__ADX__"); 3278 3279 if (HasTBM) 3280 Builder.defineMacro("__TBM__"); 3281 3282 switch (XOPLevel) { 3283 case XOP: 3284 Builder.defineMacro("__XOP__"); 3285 case FMA4: 3286 Builder.defineMacro("__FMA4__"); 3287 case SSE4A: 3288 Builder.defineMacro("__SSE4A__"); 3289 case NoXOP: 3290 break; 3291 } 3292 3293 if (HasFMA) 3294 Builder.defineMacro("__FMA__"); 3295 3296 if (HasF16C) 3297 Builder.defineMacro("__F16C__"); 3298 3299 if (HasAVX512CD) 3300 Builder.defineMacro("__AVX512CD__"); 3301 if (HasAVX512ER) 3302 Builder.defineMacro("__AVX512ER__"); 3303 if (HasAVX512PF) 3304 Builder.defineMacro("__AVX512PF__"); 3305 if (HasAVX512DQ) 3306 Builder.defineMacro("__AVX512DQ__"); 3307 if (HasAVX512BW) 3308 Builder.defineMacro("__AVX512BW__"); 3309 if (HasAVX512VL) 3310 Builder.defineMacro("__AVX512VL__"); 3311 3312 if (HasSHA) 3313 Builder.defineMacro("__SHA__"); 3314 3315 if (HasFXSR) 3316 Builder.defineMacro("__FXSR__"); 3317 if (HasXSAVE) 3318 Builder.defineMacro("__XSAVE__"); 3319 if (HasXSAVEOPT) 3320 Builder.defineMacro("__XSAVEOPT__"); 3321 if (HasXSAVEC) 3322 Builder.defineMacro("__XSAVEC__"); 3323 if (HasXSAVES) 3324 Builder.defineMacro("__XSAVES__"); 3325 3326 if (HasCX16) 3327 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3328 3329 // Each case falls through to the previous one here. 3330 switch (SSELevel) { 3331 case AVX512F: 3332 Builder.defineMacro("__AVX512F__"); 3333 case AVX2: 3334 Builder.defineMacro("__AVX2__"); 3335 case AVX: 3336 Builder.defineMacro("__AVX__"); 3337 case SSE42: 3338 Builder.defineMacro("__SSE4_2__"); 3339 case SSE41: 3340 Builder.defineMacro("__SSE4_1__"); 3341 case SSSE3: 3342 Builder.defineMacro("__SSSE3__"); 3343 case SSE3: 3344 Builder.defineMacro("__SSE3__"); 3345 case SSE2: 3346 Builder.defineMacro("__SSE2__"); 3347 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3348 case SSE1: 3349 Builder.defineMacro("__SSE__"); 3350 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3351 case NoSSE: 3352 break; 3353 } 3354 3355 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3356 switch (SSELevel) { 3357 case AVX512F: 3358 case AVX2: 3359 case AVX: 3360 case SSE42: 3361 case SSE41: 3362 case SSSE3: 3363 case SSE3: 3364 case SSE2: 3365 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3366 break; 3367 case SSE1: 3368 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3369 break; 3370 default: 3371 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3372 } 3373 } 3374 3375 // Each case falls through to the previous one here. 3376 switch (MMX3DNowLevel) { 3377 case AMD3DNowAthlon: 3378 Builder.defineMacro("__3dNOW_A__"); 3379 case AMD3DNow: 3380 Builder.defineMacro("__3dNOW__"); 3381 case MMX: 3382 Builder.defineMacro("__MMX__"); 3383 case NoMMX3DNow: 3384 break; 3385 } 3386 3387 if (CPU >= CK_i486) { 3388 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3389 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3390 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3391 } 3392 if (CPU >= CK_i586) 3393 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3394 3395 if (getTriple().isOSIAMCU()) { 3396 Builder.defineMacro("__iamcu"); 3397 Builder.defineMacro("__iamcu__"); 3398 } 3399 } 3400 3401 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3402 return llvm::StringSwitch<bool>(Feature) 3403 .Case("aes", HasAES) 3404 .Case("avx", SSELevel >= AVX) 3405 .Case("avx2", SSELevel >= AVX2) 3406 .Case("avx512f", SSELevel >= AVX512F) 3407 .Case("avx512cd", HasAVX512CD) 3408 .Case("avx512er", HasAVX512ER) 3409 .Case("avx512pf", HasAVX512PF) 3410 .Case("avx512dq", HasAVX512DQ) 3411 .Case("avx512bw", HasAVX512BW) 3412 .Case("avx512vl", HasAVX512VL) 3413 .Case("bmi", HasBMI) 3414 .Case("bmi2", HasBMI2) 3415 .Case("cx16", HasCX16) 3416 .Case("f16c", HasF16C) 3417 .Case("fma", HasFMA) 3418 .Case("fma4", XOPLevel >= FMA4) 3419 .Case("fsgsbase", HasFSGSBASE) 3420 .Case("fxsr", HasFXSR) 3421 .Case("lzcnt", HasLZCNT) 3422 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3423 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3424 .Case("mmx", MMX3DNowLevel >= MMX) 3425 .Case("pclmul", HasPCLMUL) 3426 .Case("popcnt", HasPOPCNT) 3427 .Case("prfchw", HasPRFCHW) 3428 .Case("rdrnd", HasRDRND) 3429 .Case("rdseed", HasRDSEED) 3430 .Case("rtm", HasRTM) 3431 .Case("sha", HasSHA) 3432 .Case("sse", SSELevel >= SSE1) 3433 .Case("sse2", SSELevel >= SSE2) 3434 .Case("sse3", SSELevel >= SSE3) 3435 .Case("ssse3", SSELevel >= SSSE3) 3436 .Case("sse4.1", SSELevel >= SSE41) 3437 .Case("sse4.2", SSELevel >= SSE42) 3438 .Case("sse4a", XOPLevel >= SSE4A) 3439 .Case("tbm", HasTBM) 3440 .Case("x86", true) 3441 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3442 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3443 .Case("xop", XOPLevel >= XOP) 3444 .Case("xsave", HasXSAVE) 3445 .Case("xsavec", HasXSAVEC) 3446 .Case("xsaves", HasXSAVES) 3447 .Case("xsaveopt", HasXSAVEOPT) 3448 .Default(false); 3449 } 3450 3451 // We can't use a generic validation scheme for the features accepted here 3452 // versus subtarget features accepted in the target attribute because the 3453 // bitfield structure that's initialized in the runtime only supports the 3454 // below currently rather than the full range of subtarget features. (See 3455 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3456 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3457 return llvm::StringSwitch<bool>(FeatureStr) 3458 .Case("cmov", true) 3459 .Case("mmx", true) 3460 .Case("popcnt", true) 3461 .Case("sse", true) 3462 .Case("sse2", true) 3463 .Case("sse3", true) 3464 .Case("sse4.1", true) 3465 .Case("sse4.2", true) 3466 .Case("avx", true) 3467 .Case("avx2", true) 3468 .Case("sse4a", true) 3469 .Case("fma4", true) 3470 .Case("xop", true) 3471 .Case("fma", true) 3472 .Case("avx512f", true) 3473 .Case("bmi", true) 3474 .Case("bmi2", true) 3475 .Default(false); 3476 } 3477 3478 bool 3479 X86TargetInfo::validateAsmConstraint(const char *&Name, 3480 TargetInfo::ConstraintInfo &Info) const { 3481 switch (*Name) { 3482 default: return false; 3483 // Constant constraints. 3484 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3485 // instructions. 3486 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3487 // x86_64 instructions. 3488 case 's': 3489 Info.setRequiresImmediate(); 3490 return true; 3491 case 'I': 3492 Info.setRequiresImmediate(0, 31); 3493 return true; 3494 case 'J': 3495 Info.setRequiresImmediate(0, 63); 3496 return true; 3497 case 'K': 3498 Info.setRequiresImmediate(-128, 127); 3499 return true; 3500 case 'L': 3501 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3502 return true; 3503 case 'M': 3504 Info.setRequiresImmediate(0, 3); 3505 return true; 3506 case 'N': 3507 Info.setRequiresImmediate(0, 255); 3508 return true; 3509 case 'O': 3510 Info.setRequiresImmediate(0, 127); 3511 return true; 3512 // Register constraints. 3513 case 'Y': // 'Y' is the first character for several 2-character constraints. 3514 // Shift the pointer to the second character of the constraint. 3515 Name++; 3516 switch (*Name) { 3517 default: 3518 return false; 3519 case '0': // First SSE register. 3520 case 't': // Any SSE register, when SSE2 is enabled. 3521 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3522 case 'm': // Any MMX register, when inter-unit moves enabled. 3523 Info.setAllowsRegister(); 3524 return true; 3525 } 3526 case 'f': // Any x87 floating point stack register. 3527 // Constraint 'f' cannot be used for output operands. 3528 if (Info.ConstraintStr[0] == '=') 3529 return false; 3530 Info.setAllowsRegister(); 3531 return true; 3532 case 'a': // eax. 3533 case 'b': // ebx. 3534 case 'c': // ecx. 3535 case 'd': // edx. 3536 case 'S': // esi. 3537 case 'D': // edi. 3538 case 'A': // edx:eax. 3539 case 't': // Top of floating point stack. 3540 case 'u': // Second from top of floating point stack. 3541 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3542 case 'y': // Any MMX register. 3543 case 'x': // Any SSE register. 3544 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3545 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3546 case 'l': // "Index" registers: any general register that can be used as an 3547 // index in a base+index memory access. 3548 Info.setAllowsRegister(); 3549 return true; 3550 // Floating point constant constraints. 3551 case 'C': // SSE floating point constant. 3552 case 'G': // x87 floating point constant. 3553 return true; 3554 } 3555 } 3556 3557 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3558 unsigned Size) const { 3559 // Strip off constraint modifiers. 3560 while (Constraint[0] == '=' || 3561 Constraint[0] == '+' || 3562 Constraint[0] == '&') 3563 Constraint = Constraint.substr(1); 3564 3565 return validateOperandSize(Constraint, Size); 3566 } 3567 3568 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3569 unsigned Size) const { 3570 return validateOperandSize(Constraint, Size); 3571 } 3572 3573 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3574 unsigned Size) const { 3575 switch (Constraint[0]) { 3576 default: break; 3577 case 'y': 3578 return Size <= 64; 3579 case 'f': 3580 case 't': 3581 case 'u': 3582 return Size <= 128; 3583 case 'x': 3584 if (SSELevel >= AVX512F) 3585 // 512-bit zmm registers can be used if target supports AVX512F. 3586 return Size <= 512U; 3587 else if (SSELevel >= AVX) 3588 // 256-bit ymm registers can be used if target supports AVX. 3589 return Size <= 256U; 3590 return Size <= 128U; 3591 case 'Y': 3592 // 'Y' is the first character for several 2-character constraints. 3593 switch (Constraint[1]) { 3594 default: break; 3595 case 'm': 3596 // 'Ym' is synonymous with 'y'. 3597 return Size <= 64; 3598 case 'i': 3599 case 't': 3600 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3601 if (SSELevel >= AVX512F) 3602 return Size <= 512U; 3603 else if (SSELevel >= AVX) 3604 return Size <= 256U; 3605 return SSELevel >= SSE2 && Size <= 128U; 3606 } 3607 3608 } 3609 3610 return true; 3611 } 3612 3613 std::string 3614 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3615 switch (*Constraint) { 3616 case 'a': return std::string("{ax}"); 3617 case 'b': return std::string("{bx}"); 3618 case 'c': return std::string("{cx}"); 3619 case 'd': return std::string("{dx}"); 3620 case 'S': return std::string("{si}"); 3621 case 'D': return std::string("{di}"); 3622 case 'p': // address 3623 return std::string("im"); 3624 case 't': // top of floating point stack. 3625 return std::string("{st}"); 3626 case 'u': // second from top of floating point stack. 3627 return std::string("{st(1)}"); // second from top of floating point stack. 3628 default: 3629 return std::string(1, *Constraint); 3630 } 3631 } 3632 3633 // X86-32 generic target 3634 class X86_32TargetInfo : public X86TargetInfo { 3635 public: 3636 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3637 DoubleAlign = LongLongAlign = 32; 3638 LongDoubleWidth = 96; 3639 LongDoubleAlign = 32; 3640 SuitableAlign = 128; 3641 DataLayoutString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3642 SizeType = UnsignedInt; 3643 PtrDiffType = SignedInt; 3644 IntPtrType = SignedInt; 3645 RegParmMax = 3; 3646 3647 if (getTriple().isOSIAMCU()) { 3648 LongDoubleWidth = 64; 3649 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3650 } 3651 3652 // Use fpret for all types. 3653 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3654 (1 << TargetInfo::Double) | 3655 (1 << TargetInfo::LongDouble)); 3656 3657 // x86-32 has atomics up to 8 bytes 3658 // FIXME: Check that we actually have cmpxchg8b before setting 3659 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3660 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3661 } 3662 BuiltinVaListKind getBuiltinVaListKind() const override { 3663 return TargetInfo::CharPtrBuiltinVaList; 3664 } 3665 3666 int getEHDataRegisterNumber(unsigned RegNo) const override { 3667 if (RegNo == 0) return 0; 3668 if (RegNo == 1) return 2; 3669 return -1; 3670 } 3671 bool validateOperandSize(StringRef Constraint, 3672 unsigned Size) const override { 3673 switch (Constraint[0]) { 3674 default: break; 3675 case 'R': 3676 case 'q': 3677 case 'Q': 3678 case 'a': 3679 case 'b': 3680 case 'c': 3681 case 'd': 3682 case 'S': 3683 case 'D': 3684 return Size <= 32; 3685 case 'A': 3686 return Size <= 64; 3687 } 3688 3689 return X86TargetInfo::validateOperandSize(Constraint, Size); 3690 } 3691 }; 3692 3693 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3694 public: 3695 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3696 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3697 3698 unsigned getFloatEvalMethod() const override { 3699 unsigned Major, Minor, Micro; 3700 getTriple().getOSVersion(Major, Minor, Micro); 3701 // New NetBSD uses the default rounding mode. 3702 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3703 return X86_32TargetInfo::getFloatEvalMethod(); 3704 // NetBSD before 6.99.26 defaults to "double" rounding. 3705 return 1; 3706 } 3707 }; 3708 3709 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3710 public: 3711 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3712 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3713 SizeType = UnsignedLong; 3714 IntPtrType = SignedLong; 3715 PtrDiffType = SignedLong; 3716 } 3717 }; 3718 3719 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3720 public: 3721 BitrigI386TargetInfo(const llvm::Triple &Triple) 3722 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3723 SizeType = UnsignedLong; 3724 IntPtrType = SignedLong; 3725 PtrDiffType = SignedLong; 3726 } 3727 }; 3728 3729 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3730 public: 3731 DarwinI386TargetInfo(const llvm::Triple &Triple) 3732 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3733 LongDoubleWidth = 128; 3734 LongDoubleAlign = 128; 3735 SuitableAlign = 128; 3736 MaxVectorAlign = 256; 3737 // The watchOS simulator uses the builtin bool type for Objective-C. 3738 llvm::Triple T = llvm::Triple(Triple); 3739 if (T.isWatchOS()) 3740 UseSignedCharForObjCBool = false; 3741 SizeType = UnsignedLong; 3742 IntPtrType = SignedLong; 3743 DataLayoutString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3744 HasAlignMac68kSupport = true; 3745 } 3746 3747 bool handleTargetFeatures(std::vector<std::string> &Features, 3748 DiagnosticsEngine &Diags) override { 3749 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 3750 Diags)) 3751 return false; 3752 // We now know the features we have: we can decide how to align vectors. 3753 MaxVectorAlign = 3754 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3755 return true; 3756 } 3757 }; 3758 3759 // x86-32 Windows target 3760 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3761 public: 3762 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3763 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3764 WCharType = UnsignedShort; 3765 DoubleAlign = LongLongAlign = 64; 3766 bool IsWinCOFF = 3767 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3768 DataLayoutString = IsWinCOFF 3769 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3770 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3771 } 3772 void getTargetDefines(const LangOptions &Opts, 3773 MacroBuilder &Builder) const override { 3774 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3775 } 3776 }; 3777 3778 // x86-32 Windows Visual Studio target 3779 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3780 public: 3781 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3782 : WindowsX86_32TargetInfo(Triple) { 3783 LongDoubleWidth = LongDoubleAlign = 64; 3784 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3785 } 3786 void getTargetDefines(const LangOptions &Opts, 3787 MacroBuilder &Builder) const override { 3788 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3789 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3790 // The value of the following reflects processor type. 3791 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3792 // We lost the original triple, so we use the default. 3793 Builder.defineMacro("_M_IX86", "600"); 3794 } 3795 }; 3796 3797 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3798 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 3799 // supports __declspec natively under -fms-extensions, but we define a no-op 3800 // __declspec macro anyway for pre-processor compatibility. 3801 if (Opts.MicrosoftExt) 3802 Builder.defineMacro("__declspec", "__declspec"); 3803 else 3804 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3805 3806 if (!Opts.MicrosoftExt) { 3807 // Provide macros for all the calling convention keywords. Provide both 3808 // single and double underscore prefixed variants. These are available on 3809 // x64 as well as x86, even though they have no effect. 3810 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3811 for (const char *CC : CCs) { 3812 std::string GCCSpelling = "__attribute__((__"; 3813 GCCSpelling += CC; 3814 GCCSpelling += "__))"; 3815 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3816 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3817 } 3818 } 3819 } 3820 3821 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3822 Builder.defineMacro("__MSVCRT__"); 3823 Builder.defineMacro("__MINGW32__"); 3824 addCygMingDefines(Opts, Builder); 3825 } 3826 3827 // x86-32 MinGW target 3828 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3829 public: 3830 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3831 : WindowsX86_32TargetInfo(Triple) {} 3832 void getTargetDefines(const LangOptions &Opts, 3833 MacroBuilder &Builder) const override { 3834 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3835 DefineStd(Builder, "WIN32", Opts); 3836 DefineStd(Builder, "WINNT", Opts); 3837 Builder.defineMacro("_X86_"); 3838 addMinGWDefines(Opts, Builder); 3839 } 3840 }; 3841 3842 // x86-32 Cygwin target 3843 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3844 public: 3845 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3846 : X86_32TargetInfo(Triple) { 3847 TLSSupported = false; 3848 WCharType = UnsignedShort; 3849 DoubleAlign = LongLongAlign = 64; 3850 DataLayoutString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3851 } 3852 void getTargetDefines(const LangOptions &Opts, 3853 MacroBuilder &Builder) const override { 3854 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3855 Builder.defineMacro("_X86_"); 3856 Builder.defineMacro("__CYGWIN__"); 3857 Builder.defineMacro("__CYGWIN32__"); 3858 addCygMingDefines(Opts, Builder); 3859 DefineStd(Builder, "unix", Opts); 3860 if (Opts.CPlusPlus) 3861 Builder.defineMacro("_GNU_SOURCE"); 3862 } 3863 }; 3864 3865 // x86-32 Haiku target 3866 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3867 public: 3868 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3869 SizeType = UnsignedLong; 3870 IntPtrType = SignedLong; 3871 PtrDiffType = SignedLong; 3872 ProcessIDType = SignedLong; 3873 this->UserLabelPrefix = ""; 3874 this->TLSSupported = false; 3875 } 3876 void getTargetDefines(const LangOptions &Opts, 3877 MacroBuilder &Builder) const override { 3878 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3879 Builder.defineMacro("__INTEL__"); 3880 Builder.defineMacro("__HAIKU__"); 3881 } 3882 }; 3883 3884 // RTEMS Target 3885 template<typename Target> 3886 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3887 protected: 3888 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3889 MacroBuilder &Builder) const override { 3890 // RTEMS defines; list based off of gcc output 3891 3892 Builder.defineMacro("__rtems__"); 3893 Builder.defineMacro("__ELF__"); 3894 } 3895 3896 public: 3897 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3898 this->UserLabelPrefix = ""; 3899 3900 switch (Triple.getArch()) { 3901 default: 3902 case llvm::Triple::x86: 3903 // this->MCountName = ".mcount"; 3904 break; 3905 case llvm::Triple::mips: 3906 case llvm::Triple::mipsel: 3907 case llvm::Triple::ppc: 3908 case llvm::Triple::ppc64: 3909 case llvm::Triple::ppc64le: 3910 // this->MCountName = "_mcount"; 3911 break; 3912 case llvm::Triple::arm: 3913 // this->MCountName = "__mcount"; 3914 break; 3915 } 3916 } 3917 }; 3918 3919 // x86-32 RTEMS target 3920 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3921 public: 3922 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3923 SizeType = UnsignedLong; 3924 IntPtrType = SignedLong; 3925 PtrDiffType = SignedLong; 3926 this->UserLabelPrefix = ""; 3927 } 3928 void getTargetDefines(const LangOptions &Opts, 3929 MacroBuilder &Builder) const override { 3930 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3931 Builder.defineMacro("__INTEL__"); 3932 Builder.defineMacro("__rtems__"); 3933 } 3934 }; 3935 3936 // x86-64 generic target 3937 class X86_64TargetInfo : public X86TargetInfo { 3938 public: 3939 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3940 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3941 bool IsWinCOFF = 3942 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3943 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3944 LongDoubleWidth = 128; 3945 LongDoubleAlign = 128; 3946 LargeArrayMinWidth = 128; 3947 LargeArrayAlign = 128; 3948 SuitableAlign = 128; 3949 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3950 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3951 IntPtrType = IsX32 ? SignedInt : SignedLong; 3952 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3953 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3954 RegParmMax = 6; 3955 3956 // Pointers are 32-bit in x32. 3957 DataLayoutString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3958 : IsWinCOFF 3959 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 3960 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3961 3962 // Use fpret only for long double. 3963 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3964 3965 // Use fp2ret for _Complex long double. 3966 ComplexLongDoubleUsesFP2Ret = true; 3967 3968 // Make __builtin_ms_va_list available. 3969 HasBuiltinMSVaList = true; 3970 3971 // x86-64 has atomics up to 16 bytes. 3972 MaxAtomicPromoteWidth = 128; 3973 MaxAtomicInlineWidth = 128; 3974 } 3975 BuiltinVaListKind getBuiltinVaListKind() const override { 3976 return TargetInfo::X86_64ABIBuiltinVaList; 3977 } 3978 3979 int getEHDataRegisterNumber(unsigned RegNo) const override { 3980 if (RegNo == 0) return 0; 3981 if (RegNo == 1) return 1; 3982 return -1; 3983 } 3984 3985 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3986 return (CC == CC_C || 3987 CC == CC_X86VectorCall || 3988 CC == CC_IntelOclBicc || 3989 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3990 } 3991 3992 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3993 return CC_C; 3994 } 3995 3996 // for x32 we need it here explicitly 3997 bool hasInt128Type() const override { return true; } 3998 3999 bool validateGlobalRegisterVariable(StringRef RegName, 4000 unsigned RegSize, 4001 bool &HasSizeMismatch) const override { 4002 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4003 // handle. 4004 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4005 // Check that the register size is 64-bit. 4006 HasSizeMismatch = RegSize != 64; 4007 return true; 4008 } 4009 4010 // Check if the register is a 32-bit register the backend can handle. 4011 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4012 HasSizeMismatch); 4013 } 4014 }; 4015 4016 // x86-64 Windows target 4017 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4018 public: 4019 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 4020 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 4021 WCharType = UnsignedShort; 4022 LongWidth = LongAlign = 32; 4023 DoubleAlign = LongLongAlign = 64; 4024 IntMaxType = SignedLongLong; 4025 Int64Type = SignedLongLong; 4026 SizeType = UnsignedLongLong; 4027 PtrDiffType = SignedLongLong; 4028 IntPtrType = SignedLongLong; 4029 this->UserLabelPrefix = ""; 4030 } 4031 4032 void getTargetDefines(const LangOptions &Opts, 4033 MacroBuilder &Builder) const override { 4034 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4035 Builder.defineMacro("_WIN64"); 4036 } 4037 4038 BuiltinVaListKind getBuiltinVaListKind() const override { 4039 return TargetInfo::CharPtrBuiltinVaList; 4040 } 4041 4042 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4043 switch (CC) { 4044 case CC_X86StdCall: 4045 case CC_X86ThisCall: 4046 case CC_X86FastCall: 4047 return CCCR_Ignore; 4048 case CC_C: 4049 case CC_X86VectorCall: 4050 case CC_IntelOclBicc: 4051 case CC_X86_64SysV: 4052 return CCCR_OK; 4053 default: 4054 return CCCR_Warning; 4055 } 4056 } 4057 }; 4058 4059 // x86-64 Windows Visual Studio target 4060 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4061 public: 4062 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 4063 : WindowsX86_64TargetInfo(Triple) { 4064 LongDoubleWidth = LongDoubleAlign = 64; 4065 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4066 } 4067 void getTargetDefines(const LangOptions &Opts, 4068 MacroBuilder &Builder) const override { 4069 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4070 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4071 Builder.defineMacro("_M_X64", "100"); 4072 Builder.defineMacro("_M_AMD64", "100"); 4073 } 4074 }; 4075 4076 // x86-64 MinGW target 4077 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4078 public: 4079 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 4080 : WindowsX86_64TargetInfo(Triple) { 4081 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4082 // with x86 FP ops. Weird. 4083 LongDoubleWidth = LongDoubleAlign = 128; 4084 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4085 } 4086 4087 void getTargetDefines(const LangOptions &Opts, 4088 MacroBuilder &Builder) const override { 4089 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4090 DefineStd(Builder, "WIN64", Opts); 4091 Builder.defineMacro("__MINGW64__"); 4092 addMinGWDefines(Opts, Builder); 4093 4094 // GCC defines this macro when it is using __gxx_personality_seh0. 4095 if (!Opts.SjLjExceptions) 4096 Builder.defineMacro("__SEH__"); 4097 } 4098 }; 4099 4100 // x86-64 Cygwin target 4101 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4102 public: 4103 CygwinX86_64TargetInfo(const llvm::Triple &Triple) 4104 : X86_64TargetInfo(Triple) { 4105 TLSSupported = false; 4106 WCharType = UnsignedShort; 4107 } 4108 void getTargetDefines(const LangOptions &Opts, 4109 MacroBuilder &Builder) const override { 4110 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4111 Builder.defineMacro("__x86_64__"); 4112 Builder.defineMacro("__CYGWIN__"); 4113 Builder.defineMacro("__CYGWIN64__"); 4114 addCygMingDefines(Opts, Builder); 4115 DefineStd(Builder, "unix", Opts); 4116 if (Opts.CPlusPlus) 4117 Builder.defineMacro("_GNU_SOURCE"); 4118 4119 // GCC defines this macro when it is using __gxx_personality_seh0. 4120 if (!Opts.SjLjExceptions) 4121 Builder.defineMacro("__SEH__"); 4122 } 4123 }; 4124 4125 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4126 public: 4127 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 4128 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 4129 Int64Type = SignedLongLong; 4130 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4131 llvm::Triple T = llvm::Triple(Triple); 4132 if (T.isiOS()) 4133 UseSignedCharForObjCBool = false; 4134 DataLayoutString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 4135 } 4136 4137 bool handleTargetFeatures(std::vector<std::string> &Features, 4138 DiagnosticsEngine &Diags) override { 4139 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4140 Diags)) 4141 return false; 4142 // We now know the features we have: we can decide how to align vectors. 4143 MaxVectorAlign = 4144 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4145 return true; 4146 } 4147 }; 4148 4149 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4150 public: 4151 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 4152 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 4153 IntMaxType = SignedLongLong; 4154 Int64Type = SignedLongLong; 4155 } 4156 }; 4157 4158 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4159 public: 4160 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 4161 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 4162 IntMaxType = SignedLongLong; 4163 Int64Type = SignedLongLong; 4164 } 4165 }; 4166 4167 class ARMTargetInfo : public TargetInfo { 4168 // Possible FPU choices. 4169 enum FPUMode { 4170 VFP2FPU = (1 << 0), 4171 VFP3FPU = (1 << 1), 4172 VFP4FPU = (1 << 2), 4173 NeonFPU = (1 << 3), 4174 FPARMV8 = (1 << 4) 4175 }; 4176 4177 // Possible HWDiv features. 4178 enum HWDivMode { 4179 HWDivThumb = (1 << 0), 4180 HWDivARM = (1 << 1) 4181 }; 4182 4183 static bool FPUModeIsVFP(FPUMode Mode) { 4184 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4185 } 4186 4187 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4188 static const char * const GCCRegNames[]; 4189 4190 std::string ABI, CPU; 4191 4192 StringRef CPUProfile; 4193 StringRef CPUAttr; 4194 4195 enum { 4196 FP_Default, 4197 FP_VFP, 4198 FP_Neon 4199 } FPMath; 4200 4201 unsigned ArchISA; 4202 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4203 unsigned ArchProfile; 4204 unsigned ArchVersion; 4205 4206 unsigned FPU : 5; 4207 4208 unsigned IsAAPCS : 1; 4209 unsigned HWDiv : 2; 4210 4211 // Initialized via features. 4212 unsigned SoftFloat : 1; 4213 unsigned SoftFloatABI : 1; 4214 4215 unsigned CRC : 1; 4216 unsigned Crypto : 1; 4217 unsigned DSP : 1; 4218 unsigned Unaligned : 1; 4219 4220 enum { 4221 LDREX_B = (1 << 0), /// byte (8-bit) 4222 LDREX_H = (1 << 1), /// half (16-bit) 4223 LDREX_W = (1 << 2), /// word (32-bit) 4224 LDREX_D = (1 << 3), /// double (64-bit) 4225 }; 4226 4227 uint32_t LDREX; 4228 4229 // ACLE 6.5.1 Hardware floating point 4230 enum { 4231 HW_FP_HP = (1 << 1), /// half (16-bit) 4232 HW_FP_SP = (1 << 2), /// single (32-bit) 4233 HW_FP_DP = (1 << 3), /// double (64-bit) 4234 }; 4235 uint32_t HW_FP; 4236 4237 static const Builtin::Info BuiltinInfo[]; 4238 4239 void setABIAAPCS() { 4240 IsAAPCS = true; 4241 4242 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4243 const llvm::Triple &T = getTriple(); 4244 4245 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4246 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4247 T.getOS() == llvm::Triple::Bitrig) 4248 SizeType = UnsignedLong; 4249 else 4250 SizeType = UnsignedInt; 4251 4252 switch (T.getOS()) { 4253 case llvm::Triple::NetBSD: 4254 WCharType = SignedInt; 4255 break; 4256 case llvm::Triple::Win32: 4257 WCharType = UnsignedShort; 4258 break; 4259 case llvm::Triple::Linux: 4260 default: 4261 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4262 WCharType = UnsignedInt; 4263 break; 4264 } 4265 4266 UseBitFieldTypeAlignment = true; 4267 4268 ZeroLengthBitfieldBoundary = 0; 4269 4270 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4271 // so set preferred for small types to 32. 4272 if (T.isOSBinFormatMachO()) { 4273 DataLayoutString = 4274 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4275 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4276 } else if (T.isOSWindows()) { 4277 assert(!BigEndian && "Windows on ARM does not support big endian"); 4278 DataLayoutString = "e" 4279 "-m:w" 4280 "-p:32:32" 4281 "-i64:64" 4282 "-v128:64:128" 4283 "-a:0:32" 4284 "-n32" 4285 "-S64"; 4286 } else if (T.isOSNaCl()) { 4287 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4288 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 4289 } else { 4290 DataLayoutString = 4291 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4292 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4293 } 4294 4295 // FIXME: Enumerated types are variable width in straight AAPCS. 4296 } 4297 4298 void setABIAPCS(bool IsAAPCS16) { 4299 const llvm::Triple &T = getTriple(); 4300 4301 IsAAPCS = false; 4302 4303 if (IsAAPCS16) 4304 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4305 else 4306 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4307 4308 // size_t is unsigned int on FreeBSD. 4309 if (T.getOS() == llvm::Triple::FreeBSD) 4310 SizeType = UnsignedInt; 4311 else 4312 SizeType = UnsignedLong; 4313 4314 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4315 WCharType = SignedInt; 4316 4317 // Do not respect the alignment of bit-field types when laying out 4318 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4319 UseBitFieldTypeAlignment = false; 4320 4321 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4322 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4323 /// gcc. 4324 ZeroLengthBitfieldBoundary = 32; 4325 4326 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4327 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4328 DataLayoutString = "e-m:o-p:32:32-i64:64-a:0:32-n32-S128"; 4329 } else if (T.isOSBinFormatMachO()) 4330 DataLayoutString = 4331 BigEndian 4332 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4333 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4334 else 4335 DataLayoutString = 4336 BigEndian 4337 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4338 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4339 4340 // FIXME: Override "preferred align" for double and long long. 4341 } 4342 4343 void setArchInfo() { 4344 StringRef ArchName = getTriple().getArchName(); 4345 4346 ArchISA = llvm::ARM::parseArchISA(ArchName); 4347 CPU = llvm::ARM::getDefaultCPU(ArchName); 4348 unsigned AK = llvm::ARM::parseArch(ArchName); 4349 if (AK != llvm::ARM::AK_INVALID) 4350 ArchKind = AK; 4351 setArchInfo(ArchKind); 4352 } 4353 4354 void setArchInfo(unsigned Kind) { 4355 StringRef SubArch; 4356 4357 // cache TargetParser info 4358 ArchKind = Kind; 4359 SubArch = llvm::ARM::getSubArch(ArchKind); 4360 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4361 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4362 4363 // cache CPU related strings 4364 CPUAttr = getCPUAttr(); 4365 CPUProfile = getCPUProfile(); 4366 } 4367 4368 void setAtomic() { 4369 // when triple does not specify a sub arch, 4370 // then we are not using inline atomics 4371 bool ShouldUseInlineAtomic = 4372 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4373 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4374 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4375 if (ArchProfile == llvm::ARM::PK_M) { 4376 MaxAtomicPromoteWidth = 32; 4377 if (ShouldUseInlineAtomic) 4378 MaxAtomicInlineWidth = 32; 4379 } 4380 else { 4381 MaxAtomicPromoteWidth = 64; 4382 if (ShouldUseInlineAtomic) 4383 MaxAtomicInlineWidth = 64; 4384 } 4385 } 4386 4387 bool isThumb() const { 4388 return (ArchISA == llvm::ARM::IK_THUMB); 4389 } 4390 4391 bool supportsThumb() const { 4392 return CPUAttr.count('T') || ArchVersion >= 6; 4393 } 4394 4395 bool supportsThumb2() const { 4396 return CPUAttr.equals("6T2") || ArchVersion >= 7; 4397 } 4398 4399 StringRef getCPUAttr() const { 4400 // For most sub-arches, the build attribute CPU name is enough. 4401 // For Cortex variants, it's slightly different. 4402 switch(ArchKind) { 4403 default: 4404 return llvm::ARM::getCPUAttr(ArchKind); 4405 case llvm::ARM::AK_ARMV6M: 4406 return "6M"; 4407 case llvm::ARM::AK_ARMV7S: 4408 return "7S"; 4409 case llvm::ARM::AK_ARMV7A: 4410 return "7A"; 4411 case llvm::ARM::AK_ARMV7R: 4412 return "7R"; 4413 case llvm::ARM::AK_ARMV7M: 4414 return "7M"; 4415 case llvm::ARM::AK_ARMV7EM: 4416 return "7EM"; 4417 case llvm::ARM::AK_ARMV8A: 4418 return "8A"; 4419 case llvm::ARM::AK_ARMV8_1A: 4420 return "8_1A"; 4421 } 4422 } 4423 4424 StringRef getCPUProfile() const { 4425 switch(ArchProfile) { 4426 case llvm::ARM::PK_A: 4427 return "A"; 4428 case llvm::ARM::PK_R: 4429 return "R"; 4430 case llvm::ARM::PK_M: 4431 return "M"; 4432 default: 4433 return ""; 4434 } 4435 } 4436 4437 public: 4438 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4439 : TargetInfo(Triple), FPMath(FP_Default), 4440 IsAAPCS(true), LDREX(0), HW_FP(0) { 4441 BigEndian = IsBigEndian; 4442 4443 switch (getTriple().getOS()) { 4444 case llvm::Triple::NetBSD: 4445 PtrDiffType = SignedLong; 4446 break; 4447 default: 4448 PtrDiffType = SignedInt; 4449 break; 4450 } 4451 4452 // Cache arch related info. 4453 setArchInfo(); 4454 4455 // {} in inline assembly are neon specifiers, not assembly variant 4456 // specifiers. 4457 NoAsmVariants = true; 4458 4459 // FIXME: This duplicates code from the driver that sets the -target-abi 4460 // option - this code is used if -target-abi isn't passed and should 4461 // be unified in some way. 4462 if (Triple.isOSBinFormatMachO()) { 4463 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4464 // the frontend matches that. 4465 if (Triple.getEnvironment() == llvm::Triple::EABI || 4466 Triple.getOS() == llvm::Triple::UnknownOS || 4467 StringRef(CPU).startswith("cortex-m")) { 4468 setABI("aapcs"); 4469 } else if (Triple.isWatchOS()) { 4470 setABI("aapcs16"); 4471 } else { 4472 setABI("apcs-gnu"); 4473 } 4474 } else if (Triple.isOSWindows()) { 4475 // FIXME: this is invalid for WindowsCE 4476 setABI("aapcs"); 4477 } else { 4478 // Select the default based on the platform. 4479 switch (Triple.getEnvironment()) { 4480 case llvm::Triple::Android: 4481 case llvm::Triple::GNUEABI: 4482 case llvm::Triple::GNUEABIHF: 4483 setABI("aapcs-linux"); 4484 break; 4485 case llvm::Triple::EABIHF: 4486 case llvm::Triple::EABI: 4487 setABI("aapcs"); 4488 break; 4489 case llvm::Triple::GNU: 4490 setABI("apcs-gnu"); 4491 break; 4492 default: 4493 if (Triple.getOS() == llvm::Triple::NetBSD) 4494 setABI("apcs-gnu"); 4495 else 4496 setABI("aapcs"); 4497 break; 4498 } 4499 } 4500 4501 // ARM targets default to using the ARM C++ ABI. 4502 TheCXXABI.set(TargetCXXABI::GenericARM); 4503 4504 // ARM has atomics up to 8 bytes 4505 setAtomic(); 4506 4507 // Do force alignment of members that follow zero length bitfields. If 4508 // the alignment of the zero-length bitfield is greater than the member 4509 // that follows it, `bar', `bar' will be aligned as the type of the 4510 // zero length bitfield. 4511 UseZeroLengthBitfieldAlignment = true; 4512 } 4513 4514 StringRef getABI() const override { return ABI; } 4515 4516 bool setABI(const std::string &Name) override { 4517 ABI = Name; 4518 4519 // The defaults (above) are for AAPCS, check if we need to change them. 4520 // 4521 // FIXME: We need support for -meabi... we could just mangle it into the 4522 // name. 4523 if (Name == "apcs-gnu" || Name == "aapcs16") { 4524 setABIAPCS(Name == "aapcs16"); 4525 return true; 4526 } 4527 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4528 setABIAAPCS(); 4529 return true; 4530 } 4531 return false; 4532 } 4533 4534 // FIXME: This should be based on Arch attributes, not CPU names. 4535 bool 4536 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4537 StringRef CPU, 4538 const std::vector<std::string> &FeaturesVec) const override { 4539 4540 std::vector<const char*> TargetFeatures; 4541 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4542 4543 // get default FPU features 4544 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4545 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4546 4547 // get default Extension features 4548 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 4549 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4550 4551 for (const char *Feature : TargetFeatures) 4552 if (Feature[0] == '+') 4553 Features[Feature+1] = true; 4554 4555 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4556 } 4557 4558 bool handleTargetFeatures(std::vector<std::string> &Features, 4559 DiagnosticsEngine &Diags) override { 4560 FPU = 0; 4561 CRC = 0; 4562 Crypto = 0; 4563 DSP = 0; 4564 Unaligned = 1; 4565 SoftFloat = SoftFloatABI = false; 4566 HWDiv = 0; 4567 4568 // This does not diagnose illegal cases like having both 4569 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4570 uint32_t HW_FP_remove = 0; 4571 for (const auto &Feature : Features) { 4572 if (Feature == "+soft-float") { 4573 SoftFloat = true; 4574 } else if (Feature == "+soft-float-abi") { 4575 SoftFloatABI = true; 4576 } else if (Feature == "+vfp2") { 4577 FPU |= VFP2FPU; 4578 HW_FP |= HW_FP_SP | HW_FP_DP; 4579 } else if (Feature == "+vfp3") { 4580 FPU |= VFP3FPU; 4581 HW_FP |= HW_FP_SP | HW_FP_DP; 4582 } else if (Feature == "+vfp4") { 4583 FPU |= VFP4FPU; 4584 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4585 } else if (Feature == "+fp-armv8") { 4586 FPU |= FPARMV8; 4587 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4588 } else if (Feature == "+neon") { 4589 FPU |= NeonFPU; 4590 HW_FP |= HW_FP_SP | HW_FP_DP; 4591 } else if (Feature == "+hwdiv") { 4592 HWDiv |= HWDivThumb; 4593 } else if (Feature == "+hwdiv-arm") { 4594 HWDiv |= HWDivARM; 4595 } else if (Feature == "+crc") { 4596 CRC = 1; 4597 } else if (Feature == "+crypto") { 4598 Crypto = 1; 4599 } else if (Feature == "+dsp") { 4600 DSP = 1; 4601 } else if (Feature == "+fp-only-sp") { 4602 HW_FP_remove |= HW_FP_DP; 4603 } else if (Feature == "+strict-align") { 4604 Unaligned = 0; 4605 } else if (Feature == "+fp16") { 4606 HW_FP |= HW_FP_HP; 4607 } 4608 } 4609 HW_FP &= ~HW_FP_remove; 4610 4611 switch (ArchVersion) { 4612 case 6: 4613 if (ArchProfile == llvm::ARM::PK_M) 4614 LDREX = 0; 4615 else if (ArchKind == llvm::ARM::AK_ARMV6K) 4616 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4617 else 4618 LDREX = LDREX_W; 4619 break; 4620 case 7: 4621 if (ArchProfile == llvm::ARM::PK_M) 4622 LDREX = LDREX_W | LDREX_H | LDREX_B ; 4623 else 4624 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4625 break; 4626 case 8: 4627 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4628 } 4629 4630 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4631 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4632 return false; 4633 } 4634 4635 if (FPMath == FP_Neon) 4636 Features.push_back("+neonfp"); 4637 else if (FPMath == FP_VFP) 4638 Features.push_back("-neonfp"); 4639 4640 // Remove front-end specific options which the backend handles differently. 4641 auto Feature = 4642 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4643 if (Feature != Features.end()) 4644 Features.erase(Feature); 4645 4646 return true; 4647 } 4648 4649 bool hasFeature(StringRef Feature) const override { 4650 return llvm::StringSwitch<bool>(Feature) 4651 .Case("arm", true) 4652 .Case("aarch32", true) 4653 .Case("softfloat", SoftFloat) 4654 .Case("thumb", isThumb()) 4655 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4656 .Case("hwdiv", HWDiv & HWDivThumb) 4657 .Case("hwdiv-arm", HWDiv & HWDivARM) 4658 .Default(false); 4659 } 4660 4661 bool setCPU(const std::string &Name) override { 4662 if (Name != "generic") 4663 setArchInfo(llvm::ARM::parseCPUArch(Name)); 4664 4665 if (ArchKind == llvm::ARM::AK_INVALID) 4666 return false; 4667 setAtomic(); 4668 CPU = Name; 4669 return true; 4670 } 4671 4672 bool setFPMath(StringRef Name) override; 4673 4674 void getTargetDefines(const LangOptions &Opts, 4675 MacroBuilder &Builder) const override { 4676 // Target identification. 4677 Builder.defineMacro("__arm"); 4678 Builder.defineMacro("__arm__"); 4679 4680 // Target properties. 4681 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4682 4683 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 4684 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 4685 if (getTriple().isWatchOS()) 4686 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 4687 4688 if (!CPUAttr.empty()) 4689 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 4690 4691 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4692 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4693 Builder.defineMacro("__ARM_ARCH", llvm::utostr(ArchVersion)); 4694 4695 if (ArchVersion >= 8) { 4696 // ACLE 6.5.7 Crypto Extension 4697 if (Crypto) 4698 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 4699 // ACLE 6.5.8 CRC32 Extension 4700 if (CRC) 4701 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 4702 // ACLE 6.5.10 Numeric Maximum and Minimum 4703 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 4704 // ACLE 6.5.9 Directed Rounding 4705 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 4706 } 4707 4708 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4709 // is not defined for the M-profile. 4710 // NOTE that the deffault profile is assumed to be 'A' 4711 if (CPUProfile.empty() || CPUProfile != "M") 4712 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4713 4714 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4715 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4716 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4717 if (supportsThumb2()) 4718 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4719 else if (supportsThumb()) 4720 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4721 4722 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4723 // instruction set such as ARM or Thumb. 4724 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4725 4726 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4727 4728 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4729 if (!CPUProfile.empty()) 4730 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4731 4732 // ACLE 6.4.3 Unaligned access supported in hardware 4733 if (Unaligned) 4734 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 4735 4736 // ACLE 6.4.4 LDREX/STREX 4737 if (LDREX) 4738 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 4739 4740 // ACLE 6.4.5 CLZ 4741 if (ArchVersion == 5 || 4742 (ArchVersion == 6 && CPUProfile != "M") || 4743 ArchVersion > 6) 4744 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 4745 4746 // ACLE 6.5.1 Hardware Floating Point 4747 if (HW_FP) 4748 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4749 4750 // ACLE predefines. 4751 Builder.defineMacro("__ARM_ACLE", "200"); 4752 4753 // FP16 support (we currently only support IEEE format). 4754 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 4755 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 4756 4757 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 4758 if (ArchVersion >= 7 && (CPUProfile != "M" || CPUAttr == "7EM")) 4759 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 4760 4761 // Subtarget options. 4762 4763 // FIXME: It's more complicated than this and we don't really support 4764 // interworking. 4765 // Windows on ARM does not "support" interworking 4766 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 4767 Builder.defineMacro("__THUMB_INTERWORK__"); 4768 4769 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4770 // Embedded targets on Darwin follow AAPCS, but not EABI. 4771 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4772 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4773 Builder.defineMacro("__ARM_EABI__"); 4774 Builder.defineMacro("__ARM_PCS", "1"); 4775 4776 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4777 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4778 } 4779 4780 if (SoftFloat) 4781 Builder.defineMacro("__SOFTFP__"); 4782 4783 if (CPU == "xscale") 4784 Builder.defineMacro("__XSCALE__"); 4785 4786 if (isThumb()) { 4787 Builder.defineMacro("__THUMBEL__"); 4788 Builder.defineMacro("__thumb__"); 4789 if (supportsThumb2()) 4790 Builder.defineMacro("__thumb2__"); 4791 } 4792 4793 // ACLE 6.4.9 32-bit SIMD instructions 4794 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 4795 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 4796 4797 // ACLE 6.4.10 Hardware Integer Divide 4798 if (((HWDiv & HWDivThumb) && isThumb()) || 4799 ((HWDiv & HWDivARM) && !isThumb())) { 4800 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 4801 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4802 } 4803 4804 // Note, this is always on in gcc, even though it doesn't make sense. 4805 Builder.defineMacro("__APCS_32__"); 4806 4807 if (FPUModeIsVFP((FPUMode) FPU)) { 4808 Builder.defineMacro("__VFP_FP__"); 4809 if (FPU & VFP2FPU) 4810 Builder.defineMacro("__ARM_VFPV2__"); 4811 if (FPU & VFP3FPU) 4812 Builder.defineMacro("__ARM_VFPV3__"); 4813 if (FPU & VFP4FPU) 4814 Builder.defineMacro("__ARM_VFPV4__"); 4815 } 4816 4817 // This only gets set when Neon instructions are actually available, unlike 4818 // the VFP define, hence the soft float and arch check. This is subtly 4819 // different from gcc, we follow the intent which was that it should be set 4820 // when Neon instructions are actually available. 4821 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 4822 Builder.defineMacro("__ARM_NEON", "1"); 4823 Builder.defineMacro("__ARM_NEON__"); 4824 // current AArch32 NEON implementations do not support double-precision 4825 // floating-point even when it is present in VFP. 4826 Builder.defineMacro("__ARM_NEON_FP", 4827 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 4828 } 4829 4830 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4831 Opts.ShortWChar ? "2" : "4"); 4832 4833 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4834 Opts.ShortEnums ? "1" : "4"); 4835 4836 if (ArchVersion >= 6 && CPUAttr != "6M") { 4837 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4838 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4839 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4840 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4841 } 4842 4843 // ACLE 6.4.7 DSP instructions 4844 if (DSP) { 4845 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 4846 } 4847 4848 // ACLE 6.4.8 Saturation instructions 4849 bool SAT = false; 4850 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 4851 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 4852 SAT = true; 4853 } 4854 4855 // ACLE 6.4.6 Q (saturation) flag 4856 if (DSP || SAT) 4857 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 4858 4859 if (Opts.UnsafeFPMath) 4860 Builder.defineMacro("__ARM_FP_FAST", "1"); 4861 } 4862 4863 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4864 return llvm::makeArrayRef(BuiltinInfo, 4865 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 4866 } 4867 bool isCLZForZeroUndef() const override { return false; } 4868 BuiltinVaListKind getBuiltinVaListKind() const override { 4869 return IsAAPCS 4870 ? AAPCSABIBuiltinVaList 4871 : (getTriple().isWatchOS() ? TargetInfo::CharPtrBuiltinVaList 4872 : TargetInfo::VoidPtrBuiltinVaList); 4873 } 4874 ArrayRef<const char *> getGCCRegNames() const override; 4875 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 4876 bool validateAsmConstraint(const char *&Name, 4877 TargetInfo::ConstraintInfo &Info) const override { 4878 switch (*Name) { 4879 default: break; 4880 case 'l': // r0-r7 4881 case 'h': // r8-r15 4882 case 'w': // VFP Floating point register single precision 4883 case 'P': // VFP Floating point register double precision 4884 Info.setAllowsRegister(); 4885 return true; 4886 case 'I': 4887 case 'J': 4888 case 'K': 4889 case 'L': 4890 case 'M': 4891 // FIXME 4892 return true; 4893 case 'Q': // A memory address that is a single base register. 4894 Info.setAllowsMemory(); 4895 return true; 4896 case 'U': // a memory reference... 4897 switch (Name[1]) { 4898 case 'q': // ...ARMV4 ldrsb 4899 case 'v': // ...VFP load/store (reg+constant offset) 4900 case 'y': // ...iWMMXt load/store 4901 case 't': // address valid for load/store opaque types wider 4902 // than 128-bits 4903 case 'n': // valid address for Neon doubleword vector load/store 4904 case 'm': // valid address for Neon element and structure load/store 4905 case 's': // valid address for non-offset loads/stores of quad-word 4906 // values in four ARM registers 4907 Info.setAllowsMemory(); 4908 Name++; 4909 return true; 4910 } 4911 } 4912 return false; 4913 } 4914 std::string convertConstraint(const char *&Constraint) const override { 4915 std::string R; 4916 switch (*Constraint) { 4917 case 'U': // Two-character constraint; add "^" hint for later parsing. 4918 R = std::string("^") + std::string(Constraint, 2); 4919 Constraint++; 4920 break; 4921 case 'p': // 'p' should be translated to 'r' by default. 4922 R = std::string("r"); 4923 break; 4924 default: 4925 return std::string(1, *Constraint); 4926 } 4927 return R; 4928 } 4929 bool 4930 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4931 std::string &SuggestedModifier) const override { 4932 bool isOutput = (Constraint[0] == '='); 4933 bool isInOut = (Constraint[0] == '+'); 4934 4935 // Strip off constraint modifiers. 4936 while (Constraint[0] == '=' || 4937 Constraint[0] == '+' || 4938 Constraint[0] == '&') 4939 Constraint = Constraint.substr(1); 4940 4941 switch (Constraint[0]) { 4942 default: break; 4943 case 'r': { 4944 switch (Modifier) { 4945 default: 4946 return (isInOut || isOutput || Size <= 64); 4947 case 'q': 4948 // A register of size 32 cannot fit a vector type. 4949 return false; 4950 } 4951 } 4952 } 4953 4954 return true; 4955 } 4956 const char *getClobbers() const override { 4957 // FIXME: Is this really right? 4958 return ""; 4959 } 4960 4961 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4962 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4963 } 4964 4965 int getEHDataRegisterNumber(unsigned RegNo) const override { 4966 if (RegNo == 0) return 0; 4967 if (RegNo == 1) return 1; 4968 return -1; 4969 } 4970 4971 bool hasSjLjLowering() const override { 4972 return true; 4973 } 4974 }; 4975 4976 bool ARMTargetInfo::setFPMath(StringRef Name) { 4977 if (Name == "neon") { 4978 FPMath = FP_Neon; 4979 return true; 4980 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4981 Name == "vfp4") { 4982 FPMath = FP_VFP; 4983 return true; 4984 } 4985 return false; 4986 } 4987 4988 const char * const ARMTargetInfo::GCCRegNames[] = { 4989 // Integer registers 4990 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4991 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4992 4993 // Float registers 4994 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4995 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4996 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4997 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4998 4999 // Double registers 5000 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5001 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5002 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5003 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5004 5005 // Quad registers 5006 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5007 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5008 }; 5009 5010 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5011 return llvm::makeArrayRef(GCCRegNames); 5012 } 5013 5014 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5015 { { "a1" }, "r0" }, 5016 { { "a2" }, "r1" }, 5017 { { "a3" }, "r2" }, 5018 { { "a4" }, "r3" }, 5019 { { "v1" }, "r4" }, 5020 { { "v2" }, "r5" }, 5021 { { "v3" }, "r6" }, 5022 { { "v4" }, "r7" }, 5023 { { "v5" }, "r8" }, 5024 { { "v6", "rfp" }, "r9" }, 5025 { { "sl" }, "r10" }, 5026 { { "fp" }, "r11" }, 5027 { { "ip" }, "r12" }, 5028 { { "r13" }, "sp" }, 5029 { { "r14" }, "lr" }, 5030 { { "r15" }, "pc" }, 5031 // The S, D and Q registers overlap, but aren't really aliases; we 5032 // don't want to substitute one of these for a different-sized one. 5033 }; 5034 5035 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5036 return llvm::makeArrayRef(GCCRegAliases); 5037 } 5038 5039 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5040 #define BUILTIN(ID, TYPE, ATTRS) \ 5041 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5042 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5043 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5044 #include "clang/Basic/BuiltinsNEON.def" 5045 5046 #define BUILTIN(ID, TYPE, ATTRS) \ 5047 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5048 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5049 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5050 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5051 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5052 #include "clang/Basic/BuiltinsARM.def" 5053 }; 5054 5055 class ARMleTargetInfo : public ARMTargetInfo { 5056 public: 5057 ARMleTargetInfo(const llvm::Triple &Triple) 5058 : ARMTargetInfo(Triple, false) { } 5059 void getTargetDefines(const LangOptions &Opts, 5060 MacroBuilder &Builder) const override { 5061 Builder.defineMacro("__ARMEL__"); 5062 ARMTargetInfo::getTargetDefines(Opts, Builder); 5063 } 5064 }; 5065 5066 class ARMbeTargetInfo : public ARMTargetInfo { 5067 public: 5068 ARMbeTargetInfo(const llvm::Triple &Triple) 5069 : ARMTargetInfo(Triple, true) { } 5070 void getTargetDefines(const LangOptions &Opts, 5071 MacroBuilder &Builder) const override { 5072 Builder.defineMacro("__ARMEB__"); 5073 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5074 ARMTargetInfo::getTargetDefines(Opts, Builder); 5075 } 5076 }; 5077 5078 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5079 const llvm::Triple Triple; 5080 public: 5081 WindowsARMTargetInfo(const llvm::Triple &Triple) 5082 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 5083 TLSSupported = false; 5084 WCharType = UnsignedShort; 5085 SizeType = UnsignedInt; 5086 UserLabelPrefix = ""; 5087 } 5088 void getVisualStudioDefines(const LangOptions &Opts, 5089 MacroBuilder &Builder) const { 5090 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5091 5092 // FIXME: this is invalid for WindowsCE 5093 Builder.defineMacro("_M_ARM_NT", "1"); 5094 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5095 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5096 5097 assert((Triple.getArch() == llvm::Triple::arm || 5098 Triple.getArch() == llvm::Triple::thumb) && 5099 "invalid architecture for Windows ARM target info"); 5100 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5101 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5102 5103 // TODO map the complete set of values 5104 // 31: VFPv3 40: VFPv4 5105 Builder.defineMacro("_M_ARM_FP", "31"); 5106 } 5107 BuiltinVaListKind getBuiltinVaListKind() const override { 5108 return TargetInfo::CharPtrBuiltinVaList; 5109 } 5110 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5111 switch (CC) { 5112 case CC_X86StdCall: 5113 case CC_X86ThisCall: 5114 case CC_X86FastCall: 5115 case CC_X86VectorCall: 5116 return CCCR_Ignore; 5117 case CC_C: 5118 return CCCR_OK; 5119 default: 5120 return CCCR_Warning; 5121 } 5122 } 5123 }; 5124 5125 // Windows ARM + Itanium C++ ABI Target 5126 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5127 public: 5128 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 5129 : WindowsARMTargetInfo(Triple) { 5130 TheCXXABI.set(TargetCXXABI::GenericARM); 5131 } 5132 5133 void getTargetDefines(const LangOptions &Opts, 5134 MacroBuilder &Builder) const override { 5135 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5136 5137 if (Opts.MSVCCompat) 5138 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5139 } 5140 }; 5141 5142 // Windows ARM, MS (C++) ABI 5143 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5144 public: 5145 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 5146 : WindowsARMTargetInfo(Triple) { 5147 TheCXXABI.set(TargetCXXABI::Microsoft); 5148 } 5149 5150 void getTargetDefines(const LangOptions &Opts, 5151 MacroBuilder &Builder) const override { 5152 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5153 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5154 } 5155 }; 5156 5157 // ARM MinGW target 5158 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5159 public: 5160 MinGWARMTargetInfo(const llvm::Triple &Triple) 5161 : WindowsARMTargetInfo(Triple) { 5162 TheCXXABI.set(TargetCXXABI::GenericARM); 5163 } 5164 5165 void getTargetDefines(const LangOptions &Opts, 5166 MacroBuilder &Builder) const override { 5167 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5168 DefineStd(Builder, "WIN32", Opts); 5169 DefineStd(Builder, "WINNT", Opts); 5170 Builder.defineMacro("_ARM_"); 5171 addMinGWDefines(Opts, Builder); 5172 } 5173 }; 5174 5175 // ARM Cygwin target 5176 class CygwinARMTargetInfo : public ARMleTargetInfo { 5177 public: 5178 CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) { 5179 TLSSupported = false; 5180 WCharType = UnsignedShort; 5181 DoubleAlign = LongLongAlign = 64; 5182 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 5183 } 5184 void getTargetDefines(const LangOptions &Opts, 5185 MacroBuilder &Builder) const override { 5186 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5187 Builder.defineMacro("_ARM_"); 5188 Builder.defineMacro("__CYGWIN__"); 5189 Builder.defineMacro("__CYGWIN32__"); 5190 DefineStd(Builder, "unix", Opts); 5191 if (Opts.CPlusPlus) 5192 Builder.defineMacro("_GNU_SOURCE"); 5193 } 5194 }; 5195 5196 class DarwinARMTargetInfo : 5197 public DarwinTargetInfo<ARMleTargetInfo> { 5198 protected: 5199 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5200 MacroBuilder &Builder) const override { 5201 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5202 } 5203 5204 public: 5205 DarwinARMTargetInfo(const llvm::Triple &Triple) 5206 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 5207 HasAlignMac68kSupport = true; 5208 // iOS always has 64-bit atomic instructions. 5209 // FIXME: This should be based off of the target features in 5210 // ARMleTargetInfo. 5211 MaxAtomicInlineWidth = 64; 5212 5213 if (Triple.isWatchOS()) { 5214 // Darwin on iOS uses a variant of the ARM C++ ABI. 5215 TheCXXABI.set(TargetCXXABI::WatchOS); 5216 5217 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5218 // size_t is long, it's a bit weird for it to be int. 5219 PtrDiffType = SignedLong; 5220 5221 // BOOL should be a real boolean on the new ABI 5222 UseSignedCharForObjCBool = false; 5223 } else 5224 TheCXXABI.set(TargetCXXABI::iOS); 5225 } 5226 }; 5227 5228 class AArch64TargetInfo : public TargetInfo { 5229 virtual void setDataLayoutString() = 0; 5230 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5231 static const char *const GCCRegNames[]; 5232 5233 enum FPUModeEnum { 5234 FPUMode, 5235 NeonMode 5236 }; 5237 5238 unsigned FPU; 5239 unsigned CRC; 5240 unsigned Crypto; 5241 unsigned Unaligned; 5242 5243 static const Builtin::Info BuiltinInfo[]; 5244 5245 std::string ABI; 5246 5247 public: 5248 AArch64TargetInfo(const llvm::Triple &Triple) 5249 : TargetInfo(Triple), ABI("aapcs") { 5250 5251 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5252 WCharType = SignedInt; 5253 5254 // NetBSD apparently prefers consistency across ARM targets to consistency 5255 // across 64-bit targets. 5256 Int64Type = SignedLongLong; 5257 IntMaxType = SignedLongLong; 5258 } else { 5259 WCharType = UnsignedInt; 5260 Int64Type = SignedLong; 5261 IntMaxType = SignedLong; 5262 } 5263 5264 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5265 MaxVectorAlign = 128; 5266 MaxAtomicInlineWidth = 128; 5267 MaxAtomicPromoteWidth = 128; 5268 5269 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5270 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5271 5272 // {} in inline assembly are neon specifiers, not assembly variant 5273 // specifiers. 5274 NoAsmVariants = true; 5275 5276 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5277 // contributes to the alignment of the containing aggregate in the same way 5278 // a plain (non bit-field) member of that type would, without exception for 5279 // zero-sized or anonymous bit-fields." 5280 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5281 UseZeroLengthBitfieldAlignment = true; 5282 5283 // AArch64 targets default to using the ARM C++ ABI. 5284 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5285 } 5286 5287 StringRef getABI() const override { return ABI; } 5288 bool setABI(const std::string &Name) override { 5289 if (Name != "aapcs" && Name != "darwinpcs") 5290 return false; 5291 5292 ABI = Name; 5293 return true; 5294 } 5295 5296 bool setCPU(const std::string &Name) override { 5297 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5298 .Case("generic", true) 5299 .Cases("cortex-a53", "cortex-a57", "cortex-a72", true) 5300 .Case("cyclone", true) 5301 .Default(false); 5302 return CPUKnown; 5303 } 5304 5305 void getTargetDefines(const LangOptions &Opts, 5306 MacroBuilder &Builder) const override { 5307 // Target identification. 5308 Builder.defineMacro("__aarch64__"); 5309 5310 // Target properties. 5311 Builder.defineMacro("_LP64"); 5312 Builder.defineMacro("__LP64__"); 5313 5314 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5315 Builder.defineMacro("__ARM_ACLE", "200"); 5316 Builder.defineMacro("__ARM_ARCH", "8"); 5317 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5318 5319 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5320 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5321 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5322 5323 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5324 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5325 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5326 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5327 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5328 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5329 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5330 5331 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5332 5333 // 0xe implies support for half, single and double precision operations. 5334 Builder.defineMacro("__ARM_FP", "0xE"); 5335 5336 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5337 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5338 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5339 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5340 5341 if (Opts.UnsafeFPMath) 5342 Builder.defineMacro("__ARM_FP_FAST", "1"); 5343 5344 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5345 5346 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5347 Opts.ShortEnums ? "1" : "4"); 5348 5349 if (FPU == NeonMode) { 5350 Builder.defineMacro("__ARM_NEON", "1"); 5351 // 64-bit NEON supports half, single and double precision operations. 5352 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5353 } 5354 5355 if (CRC) 5356 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5357 5358 if (Crypto) 5359 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5360 5361 if (Unaligned) 5362 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5363 5364 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5365 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5366 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5367 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5368 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5369 } 5370 5371 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5372 return llvm::makeArrayRef(BuiltinInfo, 5373 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5374 } 5375 5376 bool hasFeature(StringRef Feature) const override { 5377 return Feature == "aarch64" || 5378 Feature == "arm64" || 5379 Feature == "arm" || 5380 (Feature == "neon" && FPU == NeonMode); 5381 } 5382 5383 bool handleTargetFeatures(std::vector<std::string> &Features, 5384 DiagnosticsEngine &Diags) override { 5385 FPU = FPUMode; 5386 CRC = 0; 5387 Crypto = 0; 5388 Unaligned = 1; 5389 5390 for (const auto &Feature : Features) { 5391 if (Feature == "+neon") 5392 FPU = NeonMode; 5393 if (Feature == "+crc") 5394 CRC = 1; 5395 if (Feature == "+crypto") 5396 Crypto = 1; 5397 if (Feature == "+strict-align") 5398 Unaligned = 0; 5399 } 5400 5401 setDataLayoutString(); 5402 5403 return true; 5404 } 5405 5406 bool isCLZForZeroUndef() const override { return false; } 5407 5408 BuiltinVaListKind getBuiltinVaListKind() const override { 5409 return TargetInfo::AArch64ABIBuiltinVaList; 5410 } 5411 5412 ArrayRef<const char *> getGCCRegNames() const override; 5413 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5414 5415 bool validateAsmConstraint(const char *&Name, 5416 TargetInfo::ConstraintInfo &Info) const override { 5417 switch (*Name) { 5418 default: 5419 return false; 5420 case 'w': // Floating point and SIMD registers (V0-V31) 5421 Info.setAllowsRegister(); 5422 return true; 5423 case 'I': // Constant that can be used with an ADD instruction 5424 case 'J': // Constant that can be used with a SUB instruction 5425 case 'K': // Constant that can be used with a 32-bit logical instruction 5426 case 'L': // Constant that can be used with a 64-bit logical instruction 5427 case 'M': // Constant that can be used as a 32-bit MOV immediate 5428 case 'N': // Constant that can be used as a 64-bit MOV immediate 5429 case 'Y': // Floating point constant zero 5430 case 'Z': // Integer constant zero 5431 return true; 5432 case 'Q': // A memory reference with base register and no offset 5433 Info.setAllowsMemory(); 5434 return true; 5435 case 'S': // A symbolic address 5436 Info.setAllowsRegister(); 5437 return true; 5438 case 'U': 5439 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5440 // Utf: A memory address suitable for ldp/stp in TF mode. 5441 // Usa: An absolute symbolic address. 5442 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5443 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5444 case 'z': // Zero register, wzr or xzr 5445 Info.setAllowsRegister(); 5446 return true; 5447 case 'x': // Floating point and SIMD registers (V0-V15) 5448 Info.setAllowsRegister(); 5449 return true; 5450 } 5451 return false; 5452 } 5453 5454 bool 5455 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5456 std::string &SuggestedModifier) const override { 5457 // Strip off constraint modifiers. 5458 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5459 Constraint = Constraint.substr(1); 5460 5461 switch (Constraint[0]) { 5462 default: 5463 return true; 5464 case 'z': 5465 case 'r': { 5466 switch (Modifier) { 5467 case 'x': 5468 case 'w': 5469 // For now assume that the person knows what they're 5470 // doing with the modifier. 5471 return true; 5472 default: 5473 // By default an 'r' constraint will be in the 'x' 5474 // registers. 5475 if (Size == 64) 5476 return true; 5477 5478 SuggestedModifier = "w"; 5479 return false; 5480 } 5481 } 5482 } 5483 } 5484 5485 const char *getClobbers() const override { return ""; } 5486 5487 int getEHDataRegisterNumber(unsigned RegNo) const override { 5488 if (RegNo == 0) 5489 return 0; 5490 if (RegNo == 1) 5491 return 1; 5492 return -1; 5493 } 5494 }; 5495 5496 const char *const AArch64TargetInfo::GCCRegNames[] = { 5497 // 32-bit Integer registers 5498 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5499 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5500 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5501 5502 // 64-bit Integer registers 5503 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5504 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5505 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5506 5507 // 32-bit floating point regsisters 5508 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5509 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5510 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5511 5512 // 64-bit floating point regsisters 5513 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5514 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5515 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5516 5517 // Vector registers 5518 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5519 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5520 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5521 }; 5522 5523 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 5524 return llvm::makeArrayRef(GCCRegNames); 5525 } 5526 5527 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5528 { { "w31" }, "wsp" }, 5529 { { "x29" }, "fp" }, 5530 { { "x30" }, "lr" }, 5531 { { "x31" }, "sp" }, 5532 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5533 // don't want to substitute one of these for a different-sized one. 5534 }; 5535 5536 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 5537 return llvm::makeArrayRef(GCCRegAliases); 5538 } 5539 5540 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5541 #define BUILTIN(ID, TYPE, ATTRS) \ 5542 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5543 #include "clang/Basic/BuiltinsNEON.def" 5544 5545 #define BUILTIN(ID, TYPE, ATTRS) \ 5546 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5547 #include "clang/Basic/BuiltinsAArch64.def" 5548 }; 5549 5550 class AArch64leTargetInfo : public AArch64TargetInfo { 5551 void setDataLayoutString() override { 5552 if (getTriple().isOSBinFormatMachO()) 5553 DataLayoutString = "e-m:o-i64:64-i128:128-n32:64-S128"; 5554 else 5555 DataLayoutString = "e-m:e-i64:64-i128:128-n32:64-S128"; 5556 } 5557 5558 public: 5559 AArch64leTargetInfo(const llvm::Triple &Triple) 5560 : AArch64TargetInfo(Triple) { 5561 BigEndian = false; 5562 } 5563 void getTargetDefines(const LangOptions &Opts, 5564 MacroBuilder &Builder) const override { 5565 Builder.defineMacro("__AARCH64EL__"); 5566 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5567 } 5568 }; 5569 5570 class AArch64beTargetInfo : public AArch64TargetInfo { 5571 void setDataLayoutString() override { 5572 assert(!getTriple().isOSBinFormatMachO()); 5573 DataLayoutString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5574 } 5575 5576 public: 5577 AArch64beTargetInfo(const llvm::Triple &Triple) 5578 : AArch64TargetInfo(Triple) { } 5579 void getTargetDefines(const LangOptions &Opts, 5580 MacroBuilder &Builder) const override { 5581 Builder.defineMacro("__AARCH64EB__"); 5582 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5583 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5584 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5585 } 5586 }; 5587 5588 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5589 protected: 5590 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5591 MacroBuilder &Builder) const override { 5592 Builder.defineMacro("__AARCH64_SIMD__"); 5593 Builder.defineMacro("__ARM64_ARCH_8__"); 5594 Builder.defineMacro("__ARM_NEON__"); 5595 Builder.defineMacro("__LITTLE_ENDIAN__"); 5596 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5597 Builder.defineMacro("__arm64", "1"); 5598 Builder.defineMacro("__arm64__", "1"); 5599 5600 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5601 } 5602 5603 public: 5604 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5605 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5606 Int64Type = SignedLongLong; 5607 WCharType = SignedInt; 5608 UseSignedCharForObjCBool = false; 5609 5610 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5611 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5612 5613 TheCXXABI.set(TargetCXXABI::iOS64); 5614 } 5615 5616 BuiltinVaListKind getBuiltinVaListKind() const override { 5617 return TargetInfo::CharPtrBuiltinVaList; 5618 } 5619 }; 5620 5621 // Hexagon abstract base class 5622 class HexagonTargetInfo : public TargetInfo { 5623 static const Builtin::Info BuiltinInfo[]; 5624 static const char * const GCCRegNames[]; 5625 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5626 std::string CPU; 5627 public: 5628 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5629 BigEndian = false; 5630 DataLayoutString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 5631 5632 // {} in inline assembly are packet specifiers, not assembly variant 5633 // specifiers. 5634 NoAsmVariants = true; 5635 } 5636 5637 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5638 return llvm::makeArrayRef(BuiltinInfo, 5639 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 5640 } 5641 5642 bool validateAsmConstraint(const char *&Name, 5643 TargetInfo::ConstraintInfo &Info) const override { 5644 return true; 5645 } 5646 5647 void getTargetDefines(const LangOptions &Opts, 5648 MacroBuilder &Builder) const override; 5649 5650 bool hasFeature(StringRef Feature) const override { 5651 return Feature == "hexagon"; 5652 } 5653 5654 BuiltinVaListKind getBuiltinVaListKind() const override { 5655 return TargetInfo::CharPtrBuiltinVaList; 5656 } 5657 ArrayRef<const char *> getGCCRegNames() const override; 5658 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5659 const char *getClobbers() const override { 5660 return ""; 5661 } 5662 5663 static const char *getHexagonCPUSuffix(StringRef Name) { 5664 return llvm::StringSwitch<const char*>(Name) 5665 .Case("hexagonv4", "4") 5666 .Case("hexagonv5", "5") 5667 .Default(nullptr); 5668 } 5669 5670 bool setCPU(const std::string &Name) override { 5671 if (!getHexagonCPUSuffix(Name)) 5672 return false; 5673 5674 CPU = Name; 5675 return true; 5676 } 5677 }; 5678 5679 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5680 MacroBuilder &Builder) const { 5681 Builder.defineMacro("qdsp6"); 5682 Builder.defineMacro("__qdsp6", "1"); 5683 Builder.defineMacro("__qdsp6__", "1"); 5684 5685 Builder.defineMacro("hexagon"); 5686 Builder.defineMacro("__hexagon", "1"); 5687 Builder.defineMacro("__hexagon__", "1"); 5688 5689 if(CPU == "hexagonv1") { 5690 Builder.defineMacro("__HEXAGON_V1__"); 5691 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 5692 if(Opts.HexagonQdsp6Compat) { 5693 Builder.defineMacro("__QDSP6_V1__"); 5694 Builder.defineMacro("__QDSP6_ARCH__", "1"); 5695 } 5696 } 5697 else if(CPU == "hexagonv2") { 5698 Builder.defineMacro("__HEXAGON_V2__"); 5699 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 5700 if(Opts.HexagonQdsp6Compat) { 5701 Builder.defineMacro("__QDSP6_V2__"); 5702 Builder.defineMacro("__QDSP6_ARCH__", "2"); 5703 } 5704 } 5705 else if(CPU == "hexagonv3") { 5706 Builder.defineMacro("__HEXAGON_V3__"); 5707 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 5708 if(Opts.HexagonQdsp6Compat) { 5709 Builder.defineMacro("__QDSP6_V3__"); 5710 Builder.defineMacro("__QDSP6_ARCH__", "3"); 5711 } 5712 } 5713 else if(CPU == "hexagonv4") { 5714 Builder.defineMacro("__HEXAGON_V4__"); 5715 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5716 if(Opts.HexagonQdsp6Compat) { 5717 Builder.defineMacro("__QDSP6_V4__"); 5718 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5719 } 5720 } 5721 else if(CPU == "hexagonv5") { 5722 Builder.defineMacro("__HEXAGON_V5__"); 5723 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5724 if(Opts.HexagonQdsp6Compat) { 5725 Builder.defineMacro("__QDSP6_V5__"); 5726 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5727 } 5728 } 5729 } 5730 5731 const char * const HexagonTargetInfo::GCCRegNames[] = { 5732 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5733 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5734 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5735 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5736 "p0", "p1", "p2", "p3", 5737 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5738 }; 5739 5740 ArrayRef<const char *> HexagonTargetInfo::getGCCRegNames() const { 5741 return llvm::makeArrayRef(GCCRegNames); 5742 } 5743 5744 5745 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5746 { { "sp" }, "r29" }, 5747 { { "fp" }, "r30" }, 5748 { { "lr" }, "r31" }, 5749 }; 5750 5751 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 5752 return llvm::makeArrayRef(GCCRegAliases); 5753 } 5754 5755 5756 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5757 #define BUILTIN(ID, TYPE, ATTRS) \ 5758 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5759 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5760 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5761 #include "clang/Basic/BuiltinsHexagon.def" 5762 }; 5763 5764 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5765 class SparcTargetInfo : public TargetInfo { 5766 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5767 static const char * const GCCRegNames[]; 5768 bool SoftFloat; 5769 public: 5770 SparcTargetInfo(const llvm::Triple &Triple) 5771 : TargetInfo(Triple), SoftFloat(false) {} 5772 5773 bool handleTargetFeatures(std::vector<std::string> &Features, 5774 DiagnosticsEngine &Diags) override { 5775 // The backend doesn't actually handle soft float yet, but in case someone 5776 // is using the support for the front end continue to support it. 5777 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 5778 if (Feature != Features.end()) { 5779 SoftFloat = true; 5780 Features.erase(Feature); 5781 } 5782 return true; 5783 } 5784 void getTargetDefines(const LangOptions &Opts, 5785 MacroBuilder &Builder) const override { 5786 DefineStd(Builder, "sparc", Opts); 5787 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5788 5789 if (SoftFloat) 5790 Builder.defineMacro("SOFT_FLOAT", "1"); 5791 } 5792 5793 bool hasFeature(StringRef Feature) const override { 5794 return llvm::StringSwitch<bool>(Feature) 5795 .Case("softfloat", SoftFloat) 5796 .Case("sparc", true) 5797 .Default(false); 5798 } 5799 5800 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5801 // FIXME: Implement! 5802 return None; 5803 } 5804 BuiltinVaListKind getBuiltinVaListKind() const override { 5805 return TargetInfo::VoidPtrBuiltinVaList; 5806 } 5807 ArrayRef<const char *> getGCCRegNames() const override; 5808 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5809 bool validateAsmConstraint(const char *&Name, 5810 TargetInfo::ConstraintInfo &info) const override { 5811 // FIXME: Implement! 5812 switch (*Name) { 5813 case 'I': // Signed 13-bit constant 5814 case 'J': // Zero 5815 case 'K': // 32-bit constant with the low 12 bits clear 5816 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5817 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5818 case 'N': // Same as 'K' but zext (required for SIMode) 5819 case 'O': // The constant 4096 5820 return true; 5821 } 5822 return false; 5823 } 5824 const char *getClobbers() const override { 5825 // FIXME: Implement! 5826 return ""; 5827 } 5828 5829 // No Sparc V7 for now, the backend doesn't support it anyway. 5830 enum CPUKind { 5831 CK_GENERIC, 5832 CK_V8, 5833 CK_SUPERSPARC, 5834 CK_SPARCLITE, 5835 CK_F934, 5836 CK_HYPERSPARC, 5837 CK_SPARCLITE86X, 5838 CK_SPARCLET, 5839 CK_TSC701, 5840 CK_V9, 5841 CK_ULTRASPARC, 5842 CK_ULTRASPARC3, 5843 CK_NIAGARA, 5844 CK_NIAGARA2, 5845 CK_NIAGARA3, 5846 CK_NIAGARA4 5847 } CPU = CK_GENERIC; 5848 5849 enum CPUGeneration { 5850 CG_V8, 5851 CG_V9, 5852 }; 5853 5854 CPUGeneration getCPUGeneration(CPUKind Kind) const { 5855 switch (Kind) { 5856 case CK_GENERIC: 5857 case CK_V8: 5858 case CK_SUPERSPARC: 5859 case CK_SPARCLITE: 5860 case CK_F934: 5861 case CK_HYPERSPARC: 5862 case CK_SPARCLITE86X: 5863 case CK_SPARCLET: 5864 case CK_TSC701: 5865 return CG_V8; 5866 case CK_V9: 5867 case CK_ULTRASPARC: 5868 case CK_ULTRASPARC3: 5869 case CK_NIAGARA: 5870 case CK_NIAGARA2: 5871 case CK_NIAGARA3: 5872 case CK_NIAGARA4: 5873 return CG_V9; 5874 } 5875 llvm_unreachable("Unexpected CPU kind"); 5876 } 5877 5878 CPUKind getCPUKind(StringRef Name) const { 5879 return llvm::StringSwitch<CPUKind>(Name) 5880 .Case("v8", CK_V8) 5881 .Case("supersparc", CK_SUPERSPARC) 5882 .Case("sparclite", CK_SPARCLITE) 5883 .Case("f934", CK_F934) 5884 .Case("hypersparc", CK_HYPERSPARC) 5885 .Case("sparclite86x", CK_SPARCLITE86X) 5886 .Case("sparclet", CK_SPARCLET) 5887 .Case("tsc701", CK_TSC701) 5888 .Case("v9", CK_V9) 5889 .Case("ultrasparc", CK_ULTRASPARC) 5890 .Case("ultrasparc3", CK_ULTRASPARC3) 5891 .Case("niagara", CK_NIAGARA) 5892 .Case("niagara2", CK_NIAGARA2) 5893 .Case("niagara3", CK_NIAGARA3) 5894 .Case("niagara4", CK_NIAGARA4) 5895 .Default(CK_GENERIC); 5896 } 5897 5898 bool setCPU(const std::string &Name) override { 5899 CPU = getCPUKind(Name); 5900 return CPU != CK_GENERIC; 5901 } 5902 }; 5903 5904 const char * const SparcTargetInfo::GCCRegNames[] = { 5905 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5906 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5907 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5908 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5909 }; 5910 5911 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 5912 return llvm::makeArrayRef(GCCRegNames); 5913 } 5914 5915 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5916 { { "g0" }, "r0" }, 5917 { { "g1" }, "r1" }, 5918 { { "g2" }, "r2" }, 5919 { { "g3" }, "r3" }, 5920 { { "g4" }, "r4" }, 5921 { { "g5" }, "r5" }, 5922 { { "g6" }, "r6" }, 5923 { { "g7" }, "r7" }, 5924 { { "o0" }, "r8" }, 5925 { { "o1" }, "r9" }, 5926 { { "o2" }, "r10" }, 5927 { { "o3" }, "r11" }, 5928 { { "o4" }, "r12" }, 5929 { { "o5" }, "r13" }, 5930 { { "o6", "sp" }, "r14" }, 5931 { { "o7" }, "r15" }, 5932 { { "l0" }, "r16" }, 5933 { { "l1" }, "r17" }, 5934 { { "l2" }, "r18" }, 5935 { { "l3" }, "r19" }, 5936 { { "l4" }, "r20" }, 5937 { { "l5" }, "r21" }, 5938 { { "l6" }, "r22" }, 5939 { { "l7" }, "r23" }, 5940 { { "i0" }, "r24" }, 5941 { { "i1" }, "r25" }, 5942 { { "i2" }, "r26" }, 5943 { { "i3" }, "r27" }, 5944 { { "i4" }, "r28" }, 5945 { { "i5" }, "r29" }, 5946 { { "i6", "fp" }, "r30" }, 5947 { { "i7" }, "r31" }, 5948 }; 5949 5950 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 5951 return llvm::makeArrayRef(GCCRegAliases); 5952 } 5953 5954 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5955 class SparcV8TargetInfo : public SparcTargetInfo { 5956 public: 5957 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5958 DataLayoutString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5959 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 5960 switch (getTriple().getOS()) { 5961 default: 5962 SizeType = UnsignedInt; 5963 IntPtrType = SignedInt; 5964 PtrDiffType = SignedInt; 5965 break; 5966 case llvm::Triple::NetBSD: 5967 case llvm::Triple::OpenBSD: 5968 SizeType = UnsignedLong; 5969 IntPtrType = SignedLong; 5970 PtrDiffType = SignedLong; 5971 break; 5972 } 5973 } 5974 5975 void getTargetDefines(const LangOptions &Opts, 5976 MacroBuilder &Builder) const override { 5977 SparcTargetInfo::getTargetDefines(Opts, Builder); 5978 switch (getCPUGeneration(CPU)) { 5979 case CG_V8: 5980 Builder.defineMacro("__sparcv8"); 5981 if (getTriple().getOS() != llvm::Triple::Solaris) 5982 Builder.defineMacro("__sparcv8__"); 5983 break; 5984 case CG_V9: 5985 Builder.defineMacro("__sparcv9"); 5986 if (getTriple().getOS() != llvm::Triple::Solaris) { 5987 Builder.defineMacro("__sparcv9__"); 5988 Builder.defineMacro("__sparc_v9__"); 5989 } 5990 break; 5991 } 5992 } 5993 }; 5994 5995 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 5996 class SparcV8elTargetInfo : public SparcV8TargetInfo { 5997 public: 5998 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 5999 DataLayoutString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64"; 6000 BigEndian = false; 6001 } 6002 }; 6003 6004 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6005 class SparcV9TargetInfo : public SparcTargetInfo { 6006 public: 6007 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 6008 // FIXME: Support Sparc quad-precision long double? 6009 DataLayoutString = "E-m:e-i64:64-n32:64-S128"; 6010 // This is an LP64 platform. 6011 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6012 6013 // OpenBSD uses long long for int64_t and intmax_t. 6014 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6015 IntMaxType = SignedLongLong; 6016 else 6017 IntMaxType = SignedLong; 6018 Int64Type = IntMaxType; 6019 6020 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6021 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6022 LongDoubleWidth = 128; 6023 LongDoubleAlign = 128; 6024 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6025 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6026 } 6027 6028 void getTargetDefines(const LangOptions &Opts, 6029 MacroBuilder &Builder) const override { 6030 SparcTargetInfo::getTargetDefines(Opts, Builder); 6031 Builder.defineMacro("__sparcv9"); 6032 Builder.defineMacro("__arch64__"); 6033 // Solaris doesn't need these variants, but the BSDs do. 6034 if (getTriple().getOS() != llvm::Triple::Solaris) { 6035 Builder.defineMacro("__sparc64__"); 6036 Builder.defineMacro("__sparc_v9__"); 6037 Builder.defineMacro("__sparcv9__"); 6038 } 6039 } 6040 6041 bool setCPU(const std::string &Name) override { 6042 if (!SparcTargetInfo::setCPU(Name)) 6043 return false; 6044 return getCPUGeneration(CPU) == CG_V9; 6045 } 6046 }; 6047 6048 class SystemZTargetInfo : public TargetInfo { 6049 static const Builtin::Info BuiltinInfo[]; 6050 static const char *const GCCRegNames[]; 6051 std::string CPU; 6052 bool HasTransactionalExecution; 6053 bool HasVector; 6054 6055 public: 6056 SystemZTargetInfo(const llvm::Triple &Triple) 6057 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6058 HasVector(false) { 6059 IntMaxType = SignedLong; 6060 Int64Type = SignedLong; 6061 TLSSupported = true; 6062 IntWidth = IntAlign = 32; 6063 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6064 PointerWidth = PointerAlign = 64; 6065 LongDoubleWidth = 128; 6066 LongDoubleAlign = 64; 6067 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6068 DefaultAlignForAttributeAligned = 64; 6069 MinGlobalAlign = 16; 6070 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 6071 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6072 } 6073 void getTargetDefines(const LangOptions &Opts, 6074 MacroBuilder &Builder) const override { 6075 Builder.defineMacro("__s390__"); 6076 Builder.defineMacro("__s390x__"); 6077 Builder.defineMacro("__zarch__"); 6078 Builder.defineMacro("__LONG_DOUBLE_128__"); 6079 if (HasTransactionalExecution) 6080 Builder.defineMacro("__HTM__"); 6081 if (Opts.ZVector) 6082 Builder.defineMacro("__VEC__", "10301"); 6083 } 6084 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6085 return llvm::makeArrayRef(BuiltinInfo, 6086 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6087 } 6088 6089 ArrayRef<const char *> getGCCRegNames() const override; 6090 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6091 // No aliases. 6092 return None; 6093 } 6094 bool validateAsmConstraint(const char *&Name, 6095 TargetInfo::ConstraintInfo &info) const override; 6096 const char *getClobbers() const override { 6097 // FIXME: Is this really right? 6098 return ""; 6099 } 6100 BuiltinVaListKind getBuiltinVaListKind() const override { 6101 return TargetInfo::SystemZBuiltinVaList; 6102 } 6103 bool setCPU(const std::string &Name) override { 6104 CPU = Name; 6105 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6106 .Case("z10", true) 6107 .Case("z196", true) 6108 .Case("zEC12", true) 6109 .Case("z13", true) 6110 .Default(false); 6111 6112 return CPUKnown; 6113 } 6114 bool 6115 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6116 StringRef CPU, 6117 const std::vector<std::string> &FeaturesVec) const override { 6118 if (CPU == "zEC12") 6119 Features["transactional-execution"] = true; 6120 if (CPU == "z13") { 6121 Features["transactional-execution"] = true; 6122 Features["vector"] = true; 6123 } 6124 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6125 } 6126 6127 bool handleTargetFeatures(std::vector<std::string> &Features, 6128 DiagnosticsEngine &Diags) override { 6129 HasTransactionalExecution = false; 6130 for (const auto &Feature : Features) { 6131 if (Feature == "+transactional-execution") 6132 HasTransactionalExecution = true; 6133 else if (Feature == "+vector") 6134 HasVector = true; 6135 } 6136 // If we use the vector ABI, vector types are 64-bit aligned. 6137 if (HasVector) { 6138 MaxVectorAlign = 64; 6139 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6140 "-v128:64-a:8:16-n32:64"; 6141 } 6142 return true; 6143 } 6144 6145 bool hasFeature(StringRef Feature) const override { 6146 return llvm::StringSwitch<bool>(Feature) 6147 .Case("systemz", true) 6148 .Case("htm", HasTransactionalExecution) 6149 .Case("vx", HasVector) 6150 .Default(false); 6151 } 6152 6153 StringRef getABI() const override { 6154 if (HasVector) 6155 return "vector"; 6156 return ""; 6157 } 6158 6159 bool useFloat128ManglingForLongDouble() const override { 6160 return true; 6161 } 6162 }; 6163 6164 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6165 #define BUILTIN(ID, TYPE, ATTRS) \ 6166 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6167 #include "clang/Basic/BuiltinsSystemZ.def" 6168 }; 6169 6170 const char *const SystemZTargetInfo::GCCRegNames[] = { 6171 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6172 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6173 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6174 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6175 }; 6176 6177 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6178 return llvm::makeArrayRef(GCCRegNames); 6179 } 6180 6181 bool SystemZTargetInfo:: 6182 validateAsmConstraint(const char *&Name, 6183 TargetInfo::ConstraintInfo &Info) const { 6184 switch (*Name) { 6185 default: 6186 return false; 6187 6188 case 'a': // Address register 6189 case 'd': // Data register (equivalent to 'r') 6190 case 'f': // Floating-point register 6191 Info.setAllowsRegister(); 6192 return true; 6193 6194 case 'I': // Unsigned 8-bit constant 6195 case 'J': // Unsigned 12-bit constant 6196 case 'K': // Signed 16-bit constant 6197 case 'L': // Signed 20-bit displacement (on all targets we support) 6198 case 'M': // 0x7fffffff 6199 return true; 6200 6201 case 'Q': // Memory with base and unsigned 12-bit displacement 6202 case 'R': // Likewise, plus an index 6203 case 'S': // Memory with base and signed 20-bit displacement 6204 case 'T': // Likewise, plus an index 6205 Info.setAllowsMemory(); 6206 return true; 6207 } 6208 } 6209 6210 class MSP430TargetInfo : public TargetInfo { 6211 static const char *const GCCRegNames[]; 6212 6213 public: 6214 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6215 BigEndian = false; 6216 TLSSupported = false; 6217 IntWidth = 16; 6218 IntAlign = 16; 6219 LongWidth = 32; 6220 LongLongWidth = 64; 6221 LongAlign = LongLongAlign = 16; 6222 PointerWidth = 16; 6223 PointerAlign = 16; 6224 SuitableAlign = 16; 6225 SizeType = UnsignedInt; 6226 IntMaxType = SignedLongLong; 6227 IntPtrType = SignedInt; 6228 PtrDiffType = SignedInt; 6229 SigAtomicType = SignedLong; 6230 DataLayoutString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 6231 } 6232 void getTargetDefines(const LangOptions &Opts, 6233 MacroBuilder &Builder) const override { 6234 Builder.defineMacro("MSP430"); 6235 Builder.defineMacro("__MSP430__"); 6236 // FIXME: defines for different 'flavours' of MCU 6237 } 6238 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6239 // FIXME: Implement. 6240 return None; 6241 } 6242 bool hasFeature(StringRef Feature) const override { 6243 return Feature == "msp430"; 6244 } 6245 ArrayRef<const char *> getGCCRegNames() const override; 6246 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6247 // No aliases. 6248 return None; 6249 } 6250 bool validateAsmConstraint(const char *&Name, 6251 TargetInfo::ConstraintInfo &info) const override { 6252 // FIXME: implement 6253 switch (*Name) { 6254 case 'K': // the constant 1 6255 case 'L': // constant -1^20 .. 1^19 6256 case 'M': // constant 1-4: 6257 return true; 6258 } 6259 // No target constraints for now. 6260 return false; 6261 } 6262 const char *getClobbers() const override { 6263 // FIXME: Is this really right? 6264 return ""; 6265 } 6266 BuiltinVaListKind getBuiltinVaListKind() const override { 6267 // FIXME: implement 6268 return TargetInfo::CharPtrBuiltinVaList; 6269 } 6270 }; 6271 6272 const char *const MSP430TargetInfo::GCCRegNames[] = { 6273 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6274 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6275 6276 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 6277 return llvm::makeArrayRef(GCCRegNames); 6278 } 6279 6280 // LLVM and Clang cannot be used directly to output native binaries for 6281 // target, but is used to compile C code to llvm bitcode with correct 6282 // type and alignment information. 6283 // 6284 // TCE uses the llvm bitcode as input and uses it for generating customized 6285 // target processor and program binary. TCE co-design environment is 6286 // publicly available in http://tce.cs.tut.fi 6287 6288 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6289 3, // opencl_global 6290 4, // opencl_local 6291 5, // opencl_constant 6292 // FIXME: generic has to be added to the target 6293 0, // opencl_generic 6294 0, // cuda_device 6295 0, // cuda_constant 6296 0 // cuda_shared 6297 }; 6298 6299 class TCETargetInfo : public TargetInfo { 6300 public: 6301 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6302 TLSSupported = false; 6303 IntWidth = 32; 6304 LongWidth = LongLongWidth = 32; 6305 PointerWidth = 32; 6306 IntAlign = 32; 6307 LongAlign = LongLongAlign = 32; 6308 PointerAlign = 32; 6309 SuitableAlign = 32; 6310 SizeType = UnsignedInt; 6311 IntMaxType = SignedLong; 6312 IntPtrType = SignedInt; 6313 PtrDiffType = SignedInt; 6314 FloatWidth = 32; 6315 FloatAlign = 32; 6316 DoubleWidth = 32; 6317 DoubleAlign = 32; 6318 LongDoubleWidth = 32; 6319 LongDoubleAlign = 32; 6320 FloatFormat = &llvm::APFloat::IEEEsingle; 6321 DoubleFormat = &llvm::APFloat::IEEEsingle; 6322 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6323 DataLayoutString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 6324 "-f64:32-v64:32-v128:32-a:0:32-n32"; 6325 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6326 UseAddrSpaceMapMangling = true; 6327 } 6328 6329 void getTargetDefines(const LangOptions &Opts, 6330 MacroBuilder &Builder) const override { 6331 DefineStd(Builder, "tce", Opts); 6332 Builder.defineMacro("__TCE__"); 6333 Builder.defineMacro("__TCE_V1__"); 6334 } 6335 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 6336 6337 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6338 const char *getClobbers() const override { return ""; } 6339 BuiltinVaListKind getBuiltinVaListKind() const override { 6340 return TargetInfo::VoidPtrBuiltinVaList; 6341 } 6342 ArrayRef<const char *> getGCCRegNames() const override { return None; } 6343 bool validateAsmConstraint(const char *&Name, 6344 TargetInfo::ConstraintInfo &info) const override { 6345 return true; 6346 } 6347 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6348 return None; 6349 } 6350 }; 6351 6352 class BPFTargetInfo : public TargetInfo { 6353 public: 6354 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6355 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6356 SizeType = UnsignedLong; 6357 PtrDiffType = SignedLong; 6358 IntPtrType = SignedLong; 6359 IntMaxType = SignedLong; 6360 Int64Type = SignedLong; 6361 RegParmMax = 5; 6362 if (Triple.getArch() == llvm::Triple::bpfeb) { 6363 BigEndian = true; 6364 DataLayoutString = "E-m:e-p:64:64-i64:64-n32:64-S128"; 6365 } else { 6366 BigEndian = false; 6367 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 6368 } 6369 MaxAtomicPromoteWidth = 64; 6370 MaxAtomicInlineWidth = 64; 6371 TLSSupported = false; 6372 } 6373 void getTargetDefines(const LangOptions &Opts, 6374 MacroBuilder &Builder) const override { 6375 DefineStd(Builder, "bpf", Opts); 6376 Builder.defineMacro("__BPF__"); 6377 } 6378 bool hasFeature(StringRef Feature) const override { 6379 return Feature == "bpf"; 6380 } 6381 6382 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6383 const char *getClobbers() const override { 6384 return ""; 6385 } 6386 BuiltinVaListKind getBuiltinVaListKind() const override { 6387 return TargetInfo::VoidPtrBuiltinVaList; 6388 } 6389 ArrayRef<const char *> getGCCRegNames() const override { 6390 return None; 6391 } 6392 bool validateAsmConstraint(const char *&Name, 6393 TargetInfo::ConstraintInfo &info) const override { 6394 return true; 6395 } 6396 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6397 return None; 6398 } 6399 }; 6400 6401 class MipsTargetInfoBase : public TargetInfo { 6402 virtual void setDataLayoutString() = 0; 6403 6404 static const Builtin::Info BuiltinInfo[]; 6405 std::string CPU; 6406 bool IsMips16; 6407 bool IsMicromips; 6408 bool IsNan2008; 6409 bool IsSingleFloat; 6410 enum MipsFloatABI { 6411 HardFloat, SoftFloat 6412 } FloatABI; 6413 enum DspRevEnum { 6414 NoDSP, DSP1, DSP2 6415 } DspRev; 6416 bool HasMSA; 6417 6418 protected: 6419 bool HasFP64; 6420 std::string ABI; 6421 6422 public: 6423 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 6424 const std::string &CPUStr) 6425 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6426 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6427 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6428 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6429 } 6430 6431 bool isNaN2008Default() const { 6432 return CPU == "mips32r6" || CPU == "mips64r6"; 6433 } 6434 6435 bool isFP64Default() const { 6436 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6437 } 6438 6439 bool isNan2008() const override { 6440 return IsNan2008; 6441 } 6442 6443 StringRef getABI() const override { return ABI; } 6444 bool setCPU(const std::string &Name) override { 6445 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6446 getTriple().getArch() == llvm::Triple::mipsel; 6447 CPU = Name; 6448 return llvm::StringSwitch<bool>(Name) 6449 .Case("mips1", IsMips32) 6450 .Case("mips2", IsMips32) 6451 .Case("mips3", true) 6452 .Case("mips4", true) 6453 .Case("mips5", true) 6454 .Case("mips32", IsMips32) 6455 .Case("mips32r2", IsMips32) 6456 .Case("mips32r3", IsMips32) 6457 .Case("mips32r5", IsMips32) 6458 .Case("mips32r6", IsMips32) 6459 .Case("mips64", true) 6460 .Case("mips64r2", true) 6461 .Case("mips64r3", true) 6462 .Case("mips64r5", true) 6463 .Case("mips64r6", true) 6464 .Case("octeon", true) 6465 .Case("p5600", true) 6466 .Default(false); 6467 } 6468 const std::string& getCPU() const { return CPU; } 6469 bool 6470 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6471 StringRef CPU, 6472 const std::vector<std::string> &FeaturesVec) const override { 6473 if (CPU == "octeon") 6474 Features["mips64r2"] = Features["cnmips"] = true; 6475 else 6476 Features[CPU] = true; 6477 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6478 } 6479 6480 void getTargetDefines(const LangOptions &Opts, 6481 MacroBuilder &Builder) const override { 6482 Builder.defineMacro("__mips__"); 6483 Builder.defineMacro("_mips"); 6484 if (Opts.GNUMode) 6485 Builder.defineMacro("mips"); 6486 6487 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6488 6489 switch (FloatABI) { 6490 case HardFloat: 6491 Builder.defineMacro("__mips_hard_float", Twine(1)); 6492 break; 6493 case SoftFloat: 6494 Builder.defineMacro("__mips_soft_float", Twine(1)); 6495 break; 6496 } 6497 6498 if (IsSingleFloat) 6499 Builder.defineMacro("__mips_single_float", Twine(1)); 6500 6501 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6502 Builder.defineMacro("_MIPS_FPSET", 6503 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6504 6505 if (IsMips16) 6506 Builder.defineMacro("__mips16", Twine(1)); 6507 6508 if (IsMicromips) 6509 Builder.defineMacro("__mips_micromips", Twine(1)); 6510 6511 if (IsNan2008) 6512 Builder.defineMacro("__mips_nan2008", Twine(1)); 6513 6514 switch (DspRev) { 6515 default: 6516 break; 6517 case DSP1: 6518 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6519 Builder.defineMacro("__mips_dsp", Twine(1)); 6520 break; 6521 case DSP2: 6522 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6523 Builder.defineMacro("__mips_dspr2", Twine(1)); 6524 Builder.defineMacro("__mips_dsp", Twine(1)); 6525 break; 6526 } 6527 6528 if (HasMSA) 6529 Builder.defineMacro("__mips_msa", Twine(1)); 6530 6531 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6532 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6533 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6534 6535 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6536 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6537 } 6538 6539 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6540 return llvm::makeArrayRef(BuiltinInfo, 6541 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 6542 } 6543 bool hasFeature(StringRef Feature) const override { 6544 return llvm::StringSwitch<bool>(Feature) 6545 .Case("mips", true) 6546 .Case("fp64", HasFP64) 6547 .Default(false); 6548 } 6549 BuiltinVaListKind getBuiltinVaListKind() const override { 6550 return TargetInfo::VoidPtrBuiltinVaList; 6551 } 6552 ArrayRef<const char *> getGCCRegNames() const override { 6553 static const char *const GCCRegNames[] = { 6554 // CPU register names 6555 // Must match second column of GCCRegAliases 6556 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6557 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6558 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6559 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6560 // Floating point register names 6561 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6562 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6563 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6564 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6565 // Hi/lo and condition register names 6566 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6567 "$fcc5","$fcc6","$fcc7", 6568 // MSA register names 6569 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6570 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6571 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6572 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6573 // MSA control register names 6574 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6575 "$msarequest", "$msamap", "$msaunmap" 6576 }; 6577 return llvm::makeArrayRef(GCCRegNames); 6578 } 6579 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override = 0; 6580 bool validateAsmConstraint(const char *&Name, 6581 TargetInfo::ConstraintInfo &Info) const override { 6582 switch (*Name) { 6583 default: 6584 return false; 6585 case 'r': // CPU registers. 6586 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6587 case 'y': // Equivalent to "r", backward compatibility only. 6588 case 'f': // floating-point registers. 6589 case 'c': // $25 for indirect jumps 6590 case 'l': // lo register 6591 case 'x': // hilo register pair 6592 Info.setAllowsRegister(); 6593 return true; 6594 case 'I': // Signed 16-bit constant 6595 case 'J': // Integer 0 6596 case 'K': // Unsigned 16-bit constant 6597 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6598 case 'M': // Constants not loadable via lui, addiu, or ori 6599 case 'N': // Constant -1 to -65535 6600 case 'O': // A signed 15-bit constant 6601 case 'P': // A constant between 1 go 65535 6602 return true; 6603 case 'R': // An address that can be used in a non-macro load or store 6604 Info.setAllowsMemory(); 6605 return true; 6606 case 'Z': 6607 if (Name[1] == 'C') { // An address usable by ll, and sc. 6608 Info.setAllowsMemory(); 6609 Name++; // Skip over 'Z'. 6610 return true; 6611 } 6612 return false; 6613 } 6614 } 6615 6616 std::string convertConstraint(const char *&Constraint) const override { 6617 std::string R; 6618 switch (*Constraint) { 6619 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6620 if (Constraint[1] == 'C') { 6621 R = std::string("^") + std::string(Constraint, 2); 6622 Constraint++; 6623 return R; 6624 } 6625 break; 6626 } 6627 return TargetInfo::convertConstraint(Constraint); 6628 } 6629 6630 const char *getClobbers() const override { 6631 // In GCC, $1 is not widely used in generated code (it's used only in a few 6632 // specific situations), so there is no real need for users to add it to 6633 // the clobbers list if they want to use it in their inline assembly code. 6634 // 6635 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6636 // code generation, so using it in inline assembly without adding it to the 6637 // clobbers list can cause conflicts between the inline assembly code and 6638 // the surrounding generated code. 6639 // 6640 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6641 // operands, which will conflict with the ".set at" assembler option (which 6642 // we use only for inline assembly, in order to maintain compatibility with 6643 // GCC) and will also conflict with the user's usage of $1. 6644 // 6645 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6646 // register for generated code is to automatically clobber $1 for all inline 6647 // assembly code. 6648 // 6649 // FIXME: We should automatically clobber $1 only for inline assembly code 6650 // which actually uses it. This would allow LLVM to use $1 for inline 6651 // assembly operands if the user's assembly code doesn't use it. 6652 return "~{$1}"; 6653 } 6654 6655 bool handleTargetFeatures(std::vector<std::string> &Features, 6656 DiagnosticsEngine &Diags) override { 6657 IsMips16 = false; 6658 IsMicromips = false; 6659 IsNan2008 = isNaN2008Default(); 6660 IsSingleFloat = false; 6661 FloatABI = HardFloat; 6662 DspRev = NoDSP; 6663 HasFP64 = isFP64Default(); 6664 6665 for (const auto &Feature : Features) { 6666 if (Feature == "+single-float") 6667 IsSingleFloat = true; 6668 else if (Feature == "+soft-float") 6669 FloatABI = SoftFloat; 6670 else if (Feature == "+mips16") 6671 IsMips16 = true; 6672 else if (Feature == "+micromips") 6673 IsMicromips = true; 6674 else if (Feature == "+dsp") 6675 DspRev = std::max(DspRev, DSP1); 6676 else if (Feature == "+dspr2") 6677 DspRev = std::max(DspRev, DSP2); 6678 else if (Feature == "+msa") 6679 HasMSA = true; 6680 else if (Feature == "+fp64") 6681 HasFP64 = true; 6682 else if (Feature == "-fp64") 6683 HasFP64 = false; 6684 else if (Feature == "+nan2008") 6685 IsNan2008 = true; 6686 else if (Feature == "-nan2008") 6687 IsNan2008 = false; 6688 } 6689 6690 setDataLayoutString(); 6691 6692 return true; 6693 } 6694 6695 int getEHDataRegisterNumber(unsigned RegNo) const override { 6696 if (RegNo == 0) return 4; 6697 if (RegNo == 1) return 5; 6698 return -1; 6699 } 6700 6701 bool isCLZForZeroUndef() const override { return false; } 6702 }; 6703 6704 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 6705 #define BUILTIN(ID, TYPE, ATTRS) \ 6706 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6707 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6708 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6709 #include "clang/Basic/BuiltinsMips.def" 6710 }; 6711 6712 class Mips32TargetInfoBase : public MipsTargetInfoBase { 6713 public: 6714 Mips32TargetInfoBase(const llvm::Triple &Triple) 6715 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 6716 SizeType = UnsignedInt; 6717 PtrDiffType = SignedInt; 6718 Int64Type = SignedLongLong; 6719 IntMaxType = Int64Type; 6720 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 6721 } 6722 bool setABI(const std::string &Name) override { 6723 if (Name == "o32" || Name == "eabi") { 6724 ABI = Name; 6725 return true; 6726 } 6727 return false; 6728 } 6729 void getTargetDefines(const LangOptions &Opts, 6730 MacroBuilder &Builder) const override { 6731 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6732 6733 Builder.defineMacro("__mips", "32"); 6734 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 6735 6736 const std::string& CPUStr = getCPU(); 6737 if (CPUStr == "mips32") 6738 Builder.defineMacro("__mips_isa_rev", "1"); 6739 else if (CPUStr == "mips32r2") 6740 Builder.defineMacro("__mips_isa_rev", "2"); 6741 else if (CPUStr == "mips32r3") 6742 Builder.defineMacro("__mips_isa_rev", "3"); 6743 else if (CPUStr == "mips32r5") 6744 Builder.defineMacro("__mips_isa_rev", "5"); 6745 else if (CPUStr == "mips32r6") 6746 Builder.defineMacro("__mips_isa_rev", "6"); 6747 6748 if (ABI == "o32") { 6749 Builder.defineMacro("__mips_o32"); 6750 Builder.defineMacro("_ABIO32", "1"); 6751 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6752 } 6753 else if (ABI == "eabi") 6754 Builder.defineMacro("__mips_eabi"); 6755 else 6756 llvm_unreachable("Invalid ABI for Mips32."); 6757 } 6758 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6759 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6760 { { "at" }, "$1" }, 6761 { { "v0" }, "$2" }, 6762 { { "v1" }, "$3" }, 6763 { { "a0" }, "$4" }, 6764 { { "a1" }, "$5" }, 6765 { { "a2" }, "$6" }, 6766 { { "a3" }, "$7" }, 6767 { { "t0" }, "$8" }, 6768 { { "t1" }, "$9" }, 6769 { { "t2" }, "$10" }, 6770 { { "t3" }, "$11" }, 6771 { { "t4" }, "$12" }, 6772 { { "t5" }, "$13" }, 6773 { { "t6" }, "$14" }, 6774 { { "t7" }, "$15" }, 6775 { { "s0" }, "$16" }, 6776 { { "s1" }, "$17" }, 6777 { { "s2" }, "$18" }, 6778 { { "s3" }, "$19" }, 6779 { { "s4" }, "$20" }, 6780 { { "s5" }, "$21" }, 6781 { { "s6" }, "$22" }, 6782 { { "s7" }, "$23" }, 6783 { { "t8" }, "$24" }, 6784 { { "t9" }, "$25" }, 6785 { { "k0" }, "$26" }, 6786 { { "k1" }, "$27" }, 6787 { { "gp" }, "$28" }, 6788 { { "sp","$sp" }, "$29" }, 6789 { { "fp","$fp" }, "$30" }, 6790 { { "ra" }, "$31" } 6791 }; 6792 return llvm::makeArrayRef(GCCRegAliases); 6793 } 6794 }; 6795 6796 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6797 void setDataLayoutString() override { 6798 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6799 } 6800 6801 public: 6802 Mips32EBTargetInfo(const llvm::Triple &Triple) 6803 : Mips32TargetInfoBase(Triple) { 6804 } 6805 void getTargetDefines(const LangOptions &Opts, 6806 MacroBuilder &Builder) const override { 6807 DefineStd(Builder, "MIPSEB", Opts); 6808 Builder.defineMacro("_MIPSEB"); 6809 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6810 } 6811 }; 6812 6813 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6814 void setDataLayoutString() override { 6815 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6816 } 6817 6818 public: 6819 Mips32ELTargetInfo(const llvm::Triple &Triple) 6820 : Mips32TargetInfoBase(Triple) { 6821 BigEndian = false; 6822 } 6823 void getTargetDefines(const LangOptions &Opts, 6824 MacroBuilder &Builder) const override { 6825 DefineStd(Builder, "MIPSEL", Opts); 6826 Builder.defineMacro("_MIPSEL"); 6827 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6828 } 6829 }; 6830 6831 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6832 public: 6833 Mips64TargetInfoBase(const llvm::Triple &Triple) 6834 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6835 LongDoubleWidth = LongDoubleAlign = 128; 6836 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6837 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6838 LongDoubleWidth = LongDoubleAlign = 64; 6839 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6840 } 6841 setN64ABITypes(); 6842 SuitableAlign = 128; 6843 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6844 } 6845 6846 void setN64ABITypes() { 6847 LongWidth = LongAlign = 64; 6848 PointerWidth = PointerAlign = 64; 6849 SizeType = UnsignedLong; 6850 PtrDiffType = SignedLong; 6851 Int64Type = SignedLong; 6852 IntMaxType = Int64Type; 6853 } 6854 6855 void setN32ABITypes() { 6856 LongWidth = LongAlign = 32; 6857 PointerWidth = PointerAlign = 32; 6858 SizeType = UnsignedInt; 6859 PtrDiffType = SignedInt; 6860 Int64Type = SignedLongLong; 6861 IntMaxType = Int64Type; 6862 } 6863 6864 bool setABI(const std::string &Name) override { 6865 if (Name == "n32") { 6866 setN32ABITypes(); 6867 ABI = Name; 6868 return true; 6869 } 6870 if (Name == "n64") { 6871 setN64ABITypes(); 6872 ABI = Name; 6873 return true; 6874 } 6875 return false; 6876 } 6877 6878 void getTargetDefines(const LangOptions &Opts, 6879 MacroBuilder &Builder) const override { 6880 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6881 6882 Builder.defineMacro("__mips", "64"); 6883 Builder.defineMacro("__mips64"); 6884 Builder.defineMacro("__mips64__"); 6885 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 6886 6887 const std::string& CPUStr = getCPU(); 6888 if (CPUStr == "mips64") 6889 Builder.defineMacro("__mips_isa_rev", "1"); 6890 else if (CPUStr == "mips64r2") 6891 Builder.defineMacro("__mips_isa_rev", "2"); 6892 else if (CPUStr == "mips64r3") 6893 Builder.defineMacro("__mips_isa_rev", "3"); 6894 else if (CPUStr == "mips64r5") 6895 Builder.defineMacro("__mips_isa_rev", "5"); 6896 else if (CPUStr == "mips64r6") 6897 Builder.defineMacro("__mips_isa_rev", "6"); 6898 6899 if (ABI == "n32") { 6900 Builder.defineMacro("__mips_n32"); 6901 Builder.defineMacro("_ABIN32", "2"); 6902 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 6903 } 6904 else if (ABI == "n64") { 6905 Builder.defineMacro("__mips_n64"); 6906 Builder.defineMacro("_ABI64", "3"); 6907 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 6908 } 6909 else 6910 llvm_unreachable("Invalid ABI for Mips64."); 6911 } 6912 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6913 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6914 { { "at" }, "$1" }, 6915 { { "v0" }, "$2" }, 6916 { { "v1" }, "$3" }, 6917 { { "a0" }, "$4" }, 6918 { { "a1" }, "$5" }, 6919 { { "a2" }, "$6" }, 6920 { { "a3" }, "$7" }, 6921 { { "a4" }, "$8" }, 6922 { { "a5" }, "$9" }, 6923 { { "a6" }, "$10" }, 6924 { { "a7" }, "$11" }, 6925 { { "t0" }, "$12" }, 6926 { { "t1" }, "$13" }, 6927 { { "t2" }, "$14" }, 6928 { { "t3" }, "$15" }, 6929 { { "s0" }, "$16" }, 6930 { { "s1" }, "$17" }, 6931 { { "s2" }, "$18" }, 6932 { { "s3" }, "$19" }, 6933 { { "s4" }, "$20" }, 6934 { { "s5" }, "$21" }, 6935 { { "s6" }, "$22" }, 6936 { { "s7" }, "$23" }, 6937 { { "t8" }, "$24" }, 6938 { { "t9" }, "$25" }, 6939 { { "k0" }, "$26" }, 6940 { { "k1" }, "$27" }, 6941 { { "gp" }, "$28" }, 6942 { { "sp","$sp" }, "$29" }, 6943 { { "fp","$fp" }, "$30" }, 6944 { { "ra" }, "$31" } 6945 }; 6946 return llvm::makeArrayRef(GCCRegAliases); 6947 } 6948 6949 bool hasInt128Type() const override { return true; } 6950 }; 6951 6952 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 6953 void setDataLayoutString() override { 6954 if (ABI == "n32") 6955 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6956 else 6957 DataLayoutString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6958 6959 } 6960 6961 public: 6962 Mips64EBTargetInfo(const llvm::Triple &Triple) 6963 : Mips64TargetInfoBase(Triple) {} 6964 void getTargetDefines(const LangOptions &Opts, 6965 MacroBuilder &Builder) const override { 6966 DefineStd(Builder, "MIPSEB", Opts); 6967 Builder.defineMacro("_MIPSEB"); 6968 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6969 } 6970 }; 6971 6972 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 6973 void setDataLayoutString() override { 6974 if (ABI == "n32") 6975 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6976 else 6977 DataLayoutString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6978 } 6979 public: 6980 Mips64ELTargetInfo(const llvm::Triple &Triple) 6981 : Mips64TargetInfoBase(Triple) { 6982 // Default ABI is n64. 6983 BigEndian = false; 6984 } 6985 void getTargetDefines(const LangOptions &Opts, 6986 MacroBuilder &Builder) const override { 6987 DefineStd(Builder, "MIPSEL", Opts); 6988 Builder.defineMacro("_MIPSEL"); 6989 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6990 } 6991 }; 6992 6993 class PNaClTargetInfo : public TargetInfo { 6994 public: 6995 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6996 BigEndian = false; 6997 this->UserLabelPrefix = ""; 6998 this->LongAlign = 32; 6999 this->LongWidth = 32; 7000 this->PointerAlign = 32; 7001 this->PointerWidth = 32; 7002 this->IntMaxType = TargetInfo::SignedLongLong; 7003 this->Int64Type = TargetInfo::SignedLongLong; 7004 this->DoubleAlign = 64; 7005 this->LongDoubleWidth = 64; 7006 this->LongDoubleAlign = 64; 7007 this->SizeType = TargetInfo::UnsignedInt; 7008 this->PtrDiffType = TargetInfo::SignedInt; 7009 this->IntPtrType = TargetInfo::SignedInt; 7010 this->RegParmMax = 0; // Disallow regparm 7011 } 7012 7013 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7014 Builder.defineMacro("__le32__"); 7015 Builder.defineMacro("__pnacl__"); 7016 } 7017 void getTargetDefines(const LangOptions &Opts, 7018 MacroBuilder &Builder) const override { 7019 getArchDefines(Opts, Builder); 7020 } 7021 bool hasFeature(StringRef Feature) const override { 7022 return Feature == "pnacl"; 7023 } 7024 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7025 BuiltinVaListKind getBuiltinVaListKind() const override { 7026 return TargetInfo::PNaClABIBuiltinVaList; 7027 } 7028 ArrayRef<const char *> getGCCRegNames() const override; 7029 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7030 bool validateAsmConstraint(const char *&Name, 7031 TargetInfo::ConstraintInfo &Info) const override { 7032 return false; 7033 } 7034 7035 const char *getClobbers() const override { 7036 return ""; 7037 } 7038 }; 7039 7040 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7041 return None; 7042 } 7043 7044 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7045 return None; 7046 } 7047 7048 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7049 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 7050 public: 7051 NaClMips32ELTargetInfo(const llvm::Triple &Triple) : 7052 Mips32ELTargetInfo(Triple) { 7053 } 7054 7055 BuiltinVaListKind getBuiltinVaListKind() const override { 7056 return TargetInfo::PNaClABIBuiltinVaList; 7057 } 7058 }; 7059 7060 class Le64TargetInfo : public TargetInfo { 7061 static const Builtin::Info BuiltinInfo[]; 7062 7063 public: 7064 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7065 BigEndian = false; 7066 NoAsmVariants = true; 7067 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7068 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7069 DataLayoutString = "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 7070 } 7071 7072 void getTargetDefines(const LangOptions &Opts, 7073 MacroBuilder &Builder) const override { 7074 DefineStd(Builder, "unix", Opts); 7075 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7076 Builder.defineMacro("__ELF__"); 7077 } 7078 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7079 return llvm::makeArrayRef(BuiltinInfo, 7080 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7081 } 7082 BuiltinVaListKind getBuiltinVaListKind() const override { 7083 return TargetInfo::PNaClABIBuiltinVaList; 7084 } 7085 const char *getClobbers() const override { return ""; } 7086 ArrayRef<const char *> getGCCRegNames() const override { 7087 return None; 7088 } 7089 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7090 return None; 7091 } 7092 bool validateAsmConstraint(const char *&Name, 7093 TargetInfo::ConstraintInfo &Info) const override { 7094 return false; 7095 } 7096 7097 bool hasProtectedVisibility() const override { return false; } 7098 }; 7099 7100 class WebAssemblyTargetInfo : public TargetInfo { 7101 static const Builtin::Info BuiltinInfo[]; 7102 7103 enum SIMDEnum { 7104 NoSIMD, 7105 SIMD128, 7106 } SIMDLevel; 7107 7108 public: 7109 explicit WebAssemblyTargetInfo(const llvm::Triple &T) 7110 : TargetInfo(T), SIMDLevel(NoSIMD) { 7111 BigEndian = false; 7112 NoAsmVariants = true; 7113 SuitableAlign = 128; 7114 LargeArrayMinWidth = 128; 7115 LargeArrayAlign = 128; 7116 SimdDefaultAlign = 128; 7117 SigAtomicType = SignedLong; 7118 LongDoubleWidth = LongDoubleAlign = 128; 7119 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7120 } 7121 7122 protected: 7123 void getTargetDefines(const LangOptions &Opts, 7124 MacroBuilder &Builder) const override { 7125 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7126 if (SIMDLevel >= SIMD128) 7127 Builder.defineMacro("__wasm_simd128__"); 7128 } 7129 7130 private: 7131 bool 7132 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7133 StringRef CPU, 7134 const std::vector<std::string> &FeaturesVec) const override { 7135 if (CPU == "bleeding-edge") 7136 Features["simd128"] = true; 7137 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7138 } 7139 bool hasFeature(StringRef Feature) const final { 7140 return llvm::StringSwitch<bool>(Feature) 7141 .Case("simd128", SIMDLevel >= SIMD128) 7142 .Default(false); 7143 } 7144 bool handleTargetFeatures(std::vector<std::string> &Features, 7145 DiagnosticsEngine &Diags) final { 7146 for (const auto &Feature : Features) { 7147 if (Feature == "+simd128") { 7148 SIMDLevel = std::max(SIMDLevel, SIMD128); 7149 continue; 7150 } 7151 if (Feature == "-simd128") { 7152 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7153 continue; 7154 } 7155 7156 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7157 << "-target-feature"; 7158 return false; 7159 } 7160 return true; 7161 } 7162 bool setCPU(const std::string &Name) final { 7163 return llvm::StringSwitch<bool>(Name) 7164 .Case("mvp", true) 7165 .Case("bleeding-edge", true) 7166 .Case("generic", true) 7167 .Default(false); 7168 } 7169 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7170 return llvm::makeArrayRef(BuiltinInfo, 7171 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7172 } 7173 BuiltinVaListKind getBuiltinVaListKind() const final { 7174 // TODO: Implement va_list properly. 7175 return VoidPtrBuiltinVaList; 7176 } 7177 ArrayRef<const char *> getGCCRegNames() const final { 7178 return None; 7179 } 7180 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7181 return None; 7182 } 7183 bool 7184 validateAsmConstraint(const char *&Name, 7185 TargetInfo::ConstraintInfo &Info) const final { 7186 return false; 7187 } 7188 const char *getClobbers() const final { return ""; } 7189 bool isCLZForZeroUndef() const final { return false; } 7190 bool hasInt128Type() const final { return true; } 7191 IntType getIntTypeByWidth(unsigned BitWidth, 7192 bool IsSigned) const final { 7193 // WebAssembly prefers long long for explicitly 64-bit integers. 7194 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7195 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7196 } 7197 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7198 bool IsSigned) const final { 7199 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7200 return BitWidth == 64 7201 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7202 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7203 } 7204 }; 7205 7206 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7207 #define BUILTIN(ID, TYPE, ATTRS) \ 7208 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7209 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7210 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7211 #include "clang/Basic/BuiltinsWebAssembly.def" 7212 }; 7213 7214 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7215 public: 7216 explicit WebAssembly32TargetInfo(const llvm::Triple &T) 7217 : WebAssemblyTargetInfo(T) { 7218 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7219 DataLayoutString = "e-p:32:32-i64:64-n32:64-S128"; 7220 } 7221 7222 protected: 7223 void getTargetDefines(const LangOptions &Opts, 7224 MacroBuilder &Builder) const override { 7225 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7226 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7227 } 7228 }; 7229 7230 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7231 public: 7232 explicit WebAssembly64TargetInfo(const llvm::Triple &T) 7233 : WebAssemblyTargetInfo(T) { 7234 LongAlign = LongWidth = 64; 7235 PointerAlign = PointerWidth = 64; 7236 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7237 DataLayoutString = "e-p:64:64-i64:64-n32:64-S128"; 7238 } 7239 7240 protected: 7241 void getTargetDefines(const LangOptions &Opts, 7242 MacroBuilder &Builder) const override { 7243 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7244 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7245 } 7246 }; 7247 7248 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7249 #define BUILTIN(ID, TYPE, ATTRS) \ 7250 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7251 #include "clang/Basic/BuiltinsLe64.def" 7252 }; 7253 7254 static const unsigned SPIRAddrSpaceMap[] = { 7255 1, // opencl_global 7256 3, // opencl_local 7257 2, // opencl_constant 7258 4, // opencl_generic 7259 0, // cuda_device 7260 0, // cuda_constant 7261 0 // cuda_shared 7262 }; 7263 class SPIRTargetInfo : public TargetInfo { 7264 public: 7265 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7266 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7267 "SPIR target must use unknown OS"); 7268 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7269 "SPIR target must use unknown environment type"); 7270 BigEndian = false; 7271 TLSSupported = false; 7272 LongWidth = LongAlign = 64; 7273 AddrSpaceMap = &SPIRAddrSpaceMap; 7274 UseAddrSpaceMapMangling = true; 7275 // Define available target features 7276 // These must be defined in sorted order! 7277 NoAsmVariants = true; 7278 } 7279 void getTargetDefines(const LangOptions &Opts, 7280 MacroBuilder &Builder) const override { 7281 DefineStd(Builder, "SPIR", Opts); 7282 } 7283 bool hasFeature(StringRef Feature) const override { 7284 return Feature == "spir"; 7285 } 7286 7287 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7288 const char *getClobbers() const override { return ""; } 7289 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7290 bool validateAsmConstraint(const char *&Name, 7291 TargetInfo::ConstraintInfo &info) const override { 7292 return true; 7293 } 7294 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7295 return None; 7296 } 7297 BuiltinVaListKind getBuiltinVaListKind() const override { 7298 return TargetInfo::VoidPtrBuiltinVaList; 7299 } 7300 7301 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7302 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK 7303 : CCCR_Warning; 7304 } 7305 7306 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7307 return CC_SpirFunction; 7308 } 7309 }; 7310 7311 class SPIR32TargetInfo : public SPIRTargetInfo { 7312 public: 7313 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7314 PointerWidth = PointerAlign = 32; 7315 SizeType = TargetInfo::UnsignedInt; 7316 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7317 DataLayoutString = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7318 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7319 } 7320 void getTargetDefines(const LangOptions &Opts, 7321 MacroBuilder &Builder) const override { 7322 DefineStd(Builder, "SPIR32", Opts); 7323 } 7324 }; 7325 7326 class SPIR64TargetInfo : public SPIRTargetInfo { 7327 public: 7328 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7329 PointerWidth = PointerAlign = 64; 7330 SizeType = TargetInfo::UnsignedLong; 7331 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7332 DataLayoutString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7333 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7334 } 7335 void getTargetDefines(const LangOptions &Opts, 7336 MacroBuilder &Builder) const override { 7337 DefineStd(Builder, "SPIR64", Opts); 7338 } 7339 }; 7340 7341 class XCoreTargetInfo : public TargetInfo { 7342 static const Builtin::Info BuiltinInfo[]; 7343 public: 7344 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7345 BigEndian = false; 7346 NoAsmVariants = true; 7347 LongLongAlign = 32; 7348 SuitableAlign = 32; 7349 DoubleAlign = LongDoubleAlign = 32; 7350 SizeType = UnsignedInt; 7351 PtrDiffType = SignedInt; 7352 IntPtrType = SignedInt; 7353 WCharType = UnsignedChar; 7354 WIntType = UnsignedInt; 7355 UseZeroLengthBitfieldAlignment = true; 7356 DataLayoutString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7357 "-f64:32-a:0:32-n32"; 7358 } 7359 void getTargetDefines(const LangOptions &Opts, 7360 MacroBuilder &Builder) const override { 7361 Builder.defineMacro("__XS1B__"); 7362 } 7363 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7364 return llvm::makeArrayRef(BuiltinInfo, 7365 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 7366 } 7367 BuiltinVaListKind getBuiltinVaListKind() const override { 7368 return TargetInfo::VoidPtrBuiltinVaList; 7369 } 7370 const char *getClobbers() const override { 7371 return ""; 7372 } 7373 ArrayRef<const char *> getGCCRegNames() const override { 7374 static const char * const GCCRegNames[] = { 7375 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7376 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 7377 }; 7378 return llvm::makeArrayRef(GCCRegNames); 7379 } 7380 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7381 return None; 7382 } 7383 bool validateAsmConstraint(const char *&Name, 7384 TargetInfo::ConstraintInfo &Info) const override { 7385 return false; 7386 } 7387 int getEHDataRegisterNumber(unsigned RegNo) const override { 7388 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7389 return (RegNo < 2)? RegNo : -1; 7390 } 7391 }; 7392 7393 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7394 #define BUILTIN(ID, TYPE, ATTRS) \ 7395 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7396 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7397 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7398 #include "clang/Basic/BuiltinsXCore.def" 7399 }; 7400 7401 // x86_32 Android target 7402 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7403 public: 7404 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 7405 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 7406 SuitableAlign = 32; 7407 LongDoubleWidth = 64; 7408 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7409 } 7410 }; 7411 7412 // x86_64 Android target 7413 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7414 public: 7415 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 7416 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 7417 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7418 } 7419 7420 bool useFloat128ManglingForLongDouble() const override { 7421 return true; 7422 } 7423 }; 7424 } // end anonymous namespace 7425 7426 //===----------------------------------------------------------------------===// 7427 // Driver code 7428 //===----------------------------------------------------------------------===// 7429 7430 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 7431 llvm::Triple::OSType os = Triple.getOS(); 7432 7433 switch (Triple.getArch()) { 7434 default: 7435 return nullptr; 7436 7437 case llvm::Triple::xcore: 7438 return new XCoreTargetInfo(Triple); 7439 7440 case llvm::Triple::hexagon: 7441 return new HexagonTargetInfo(Triple); 7442 7443 case llvm::Triple::aarch64: 7444 if (Triple.isOSDarwin()) 7445 return new DarwinAArch64TargetInfo(Triple); 7446 7447 switch (os) { 7448 case llvm::Triple::CloudABI: 7449 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple); 7450 case llvm::Triple::FreeBSD: 7451 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 7452 case llvm::Triple::Linux: 7453 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 7454 case llvm::Triple::NetBSD: 7455 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 7456 default: 7457 return new AArch64leTargetInfo(Triple); 7458 } 7459 7460 case llvm::Triple::aarch64_be: 7461 switch (os) { 7462 case llvm::Triple::FreeBSD: 7463 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 7464 case llvm::Triple::Linux: 7465 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 7466 case llvm::Triple::NetBSD: 7467 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 7468 default: 7469 return new AArch64beTargetInfo(Triple); 7470 } 7471 7472 case llvm::Triple::arm: 7473 case llvm::Triple::thumb: 7474 if (Triple.isOSBinFormatMachO()) 7475 return new DarwinARMTargetInfo(Triple); 7476 7477 switch (os) { 7478 case llvm::Triple::Linux: 7479 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 7480 case llvm::Triple::FreeBSD: 7481 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 7482 case llvm::Triple::NetBSD: 7483 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 7484 case llvm::Triple::OpenBSD: 7485 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 7486 case llvm::Triple::Bitrig: 7487 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 7488 case llvm::Triple::RTEMS: 7489 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 7490 case llvm::Triple::NaCl: 7491 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 7492 case llvm::Triple::Win32: 7493 switch (Triple.getEnvironment()) { 7494 case llvm::Triple::Cygnus: 7495 return new CygwinARMTargetInfo(Triple); 7496 case llvm::Triple::GNU: 7497 return new MinGWARMTargetInfo(Triple); 7498 case llvm::Triple::Itanium: 7499 return new ItaniumWindowsARMleTargetInfo(Triple); 7500 case llvm::Triple::MSVC: 7501 default: // Assume MSVC for unknown environments 7502 return new MicrosoftARMleTargetInfo(Triple); 7503 } 7504 default: 7505 return new ARMleTargetInfo(Triple); 7506 } 7507 7508 case llvm::Triple::armeb: 7509 case llvm::Triple::thumbeb: 7510 if (Triple.isOSDarwin()) 7511 return new DarwinARMTargetInfo(Triple); 7512 7513 switch (os) { 7514 case llvm::Triple::Linux: 7515 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 7516 case llvm::Triple::FreeBSD: 7517 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 7518 case llvm::Triple::NetBSD: 7519 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 7520 case llvm::Triple::OpenBSD: 7521 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 7522 case llvm::Triple::Bitrig: 7523 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 7524 case llvm::Triple::RTEMS: 7525 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 7526 case llvm::Triple::NaCl: 7527 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 7528 default: 7529 return new ARMbeTargetInfo(Triple); 7530 } 7531 7532 case llvm::Triple::bpfeb: 7533 case llvm::Triple::bpfel: 7534 return new BPFTargetInfo(Triple); 7535 7536 case llvm::Triple::msp430: 7537 return new MSP430TargetInfo(Triple); 7538 7539 case llvm::Triple::mips: 7540 switch (os) { 7541 case llvm::Triple::Linux: 7542 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 7543 case llvm::Triple::RTEMS: 7544 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 7545 case llvm::Triple::FreeBSD: 7546 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7547 case llvm::Triple::NetBSD: 7548 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7549 default: 7550 return new Mips32EBTargetInfo(Triple); 7551 } 7552 7553 case llvm::Triple::mipsel: 7554 switch (os) { 7555 case llvm::Triple::Linux: 7556 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 7557 case llvm::Triple::RTEMS: 7558 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 7559 case llvm::Triple::FreeBSD: 7560 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7561 case llvm::Triple::NetBSD: 7562 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7563 case llvm::Triple::NaCl: 7564 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple); 7565 default: 7566 return new Mips32ELTargetInfo(Triple); 7567 } 7568 7569 case llvm::Triple::mips64: 7570 switch (os) { 7571 case llvm::Triple::Linux: 7572 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 7573 case llvm::Triple::RTEMS: 7574 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 7575 case llvm::Triple::FreeBSD: 7576 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7577 case llvm::Triple::NetBSD: 7578 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7579 case llvm::Triple::OpenBSD: 7580 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7581 default: 7582 return new Mips64EBTargetInfo(Triple); 7583 } 7584 7585 case llvm::Triple::mips64el: 7586 switch (os) { 7587 case llvm::Triple::Linux: 7588 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 7589 case llvm::Triple::RTEMS: 7590 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 7591 case llvm::Triple::FreeBSD: 7592 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7593 case llvm::Triple::NetBSD: 7594 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7595 case llvm::Triple::OpenBSD: 7596 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7597 default: 7598 return new Mips64ELTargetInfo(Triple); 7599 } 7600 7601 case llvm::Triple::le32: 7602 switch (os) { 7603 case llvm::Triple::NaCl: 7604 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 7605 default: 7606 return nullptr; 7607 } 7608 7609 case llvm::Triple::le64: 7610 return new Le64TargetInfo(Triple); 7611 7612 case llvm::Triple::ppc: 7613 if (Triple.isOSDarwin()) 7614 return new DarwinPPC32TargetInfo(Triple); 7615 switch (os) { 7616 case llvm::Triple::Linux: 7617 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 7618 case llvm::Triple::FreeBSD: 7619 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 7620 case llvm::Triple::NetBSD: 7621 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 7622 case llvm::Triple::OpenBSD: 7623 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 7624 case llvm::Triple::RTEMS: 7625 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 7626 default: 7627 return new PPC32TargetInfo(Triple); 7628 } 7629 7630 case llvm::Triple::ppc64: 7631 if (Triple.isOSDarwin()) 7632 return new DarwinPPC64TargetInfo(Triple); 7633 switch (os) { 7634 case llvm::Triple::Linux: 7635 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7636 case llvm::Triple::Lv2: 7637 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 7638 case llvm::Triple::FreeBSD: 7639 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 7640 case llvm::Triple::NetBSD: 7641 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7642 default: 7643 return new PPC64TargetInfo(Triple); 7644 } 7645 7646 case llvm::Triple::ppc64le: 7647 switch (os) { 7648 case llvm::Triple::Linux: 7649 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7650 case llvm::Triple::NetBSD: 7651 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7652 default: 7653 return new PPC64TargetInfo(Triple); 7654 } 7655 7656 case llvm::Triple::nvptx: 7657 return new NVPTX32TargetInfo(Triple); 7658 case llvm::Triple::nvptx64: 7659 return new NVPTX64TargetInfo(Triple); 7660 7661 case llvm::Triple::amdgcn: 7662 case llvm::Triple::r600: 7663 return new AMDGPUTargetInfo(Triple); 7664 7665 case llvm::Triple::sparc: 7666 switch (os) { 7667 case llvm::Triple::Linux: 7668 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 7669 case llvm::Triple::Solaris: 7670 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple); 7671 case llvm::Triple::NetBSD: 7672 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 7673 case llvm::Triple::OpenBSD: 7674 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 7675 case llvm::Triple::RTEMS: 7676 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 7677 default: 7678 return new SparcV8TargetInfo(Triple); 7679 } 7680 7681 // The 'sparcel' architecture copies all the above cases except for Solaris. 7682 case llvm::Triple::sparcel: 7683 switch (os) { 7684 case llvm::Triple::Linux: 7685 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 7686 case llvm::Triple::NetBSD: 7687 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7688 case llvm::Triple::OpenBSD: 7689 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7690 case llvm::Triple::RTEMS: 7691 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 7692 default: 7693 return new SparcV8elTargetInfo(Triple); 7694 } 7695 7696 case llvm::Triple::sparcv9: 7697 switch (os) { 7698 case llvm::Triple::Linux: 7699 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 7700 case llvm::Triple::Solaris: 7701 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 7702 case llvm::Triple::NetBSD: 7703 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 7704 case llvm::Triple::OpenBSD: 7705 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 7706 case llvm::Triple::FreeBSD: 7707 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 7708 default: 7709 return new SparcV9TargetInfo(Triple); 7710 } 7711 7712 case llvm::Triple::systemz: 7713 switch (os) { 7714 case llvm::Triple::Linux: 7715 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 7716 default: 7717 return new SystemZTargetInfo(Triple); 7718 } 7719 7720 case llvm::Triple::tce: 7721 return new TCETargetInfo(Triple); 7722 7723 case llvm::Triple::x86: 7724 if (Triple.isOSDarwin()) 7725 return new DarwinI386TargetInfo(Triple); 7726 7727 switch (os) { 7728 case llvm::Triple::CloudABI: 7729 return new CloudABITargetInfo<X86_32TargetInfo>(Triple); 7730 case llvm::Triple::Linux: { 7731 switch (Triple.getEnvironment()) { 7732 default: 7733 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 7734 case llvm::Triple::Android: 7735 return new AndroidX86_32TargetInfo(Triple); 7736 } 7737 } 7738 case llvm::Triple::DragonFly: 7739 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 7740 case llvm::Triple::NetBSD: 7741 return new NetBSDI386TargetInfo(Triple); 7742 case llvm::Triple::OpenBSD: 7743 return new OpenBSDI386TargetInfo(Triple); 7744 case llvm::Triple::Bitrig: 7745 return new BitrigI386TargetInfo(Triple); 7746 case llvm::Triple::FreeBSD: 7747 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7748 case llvm::Triple::KFreeBSD: 7749 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7750 case llvm::Triple::Minix: 7751 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 7752 case llvm::Triple::Solaris: 7753 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 7754 case llvm::Triple::Win32: { 7755 switch (Triple.getEnvironment()) { 7756 case llvm::Triple::Cygnus: 7757 return new CygwinX86_32TargetInfo(Triple); 7758 case llvm::Triple::GNU: 7759 return new MinGWX86_32TargetInfo(Triple); 7760 case llvm::Triple::Itanium: 7761 case llvm::Triple::MSVC: 7762 default: // Assume MSVC for unknown environments 7763 return new MicrosoftX86_32TargetInfo(Triple); 7764 } 7765 } 7766 case llvm::Triple::Haiku: 7767 return new HaikuX86_32TargetInfo(Triple); 7768 case llvm::Triple::RTEMS: 7769 return new RTEMSX86_32TargetInfo(Triple); 7770 case llvm::Triple::NaCl: 7771 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 7772 default: 7773 return new X86_32TargetInfo(Triple); 7774 } 7775 7776 case llvm::Triple::x86_64: 7777 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 7778 return new DarwinX86_64TargetInfo(Triple); 7779 7780 switch (os) { 7781 case llvm::Triple::CloudABI: 7782 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 7783 case llvm::Triple::Linux: { 7784 switch (Triple.getEnvironment()) { 7785 default: 7786 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 7787 case llvm::Triple::Android: 7788 return new AndroidX86_64TargetInfo(Triple); 7789 } 7790 } 7791 case llvm::Triple::DragonFly: 7792 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 7793 case llvm::Triple::NetBSD: 7794 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 7795 case llvm::Triple::OpenBSD: 7796 return new OpenBSDX86_64TargetInfo(Triple); 7797 case llvm::Triple::Bitrig: 7798 return new BitrigX86_64TargetInfo(Triple); 7799 case llvm::Triple::FreeBSD: 7800 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7801 case llvm::Triple::KFreeBSD: 7802 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7803 case llvm::Triple::Solaris: 7804 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 7805 case llvm::Triple::Win32: { 7806 switch (Triple.getEnvironment()) { 7807 case llvm::Triple::Cygnus: 7808 return new CygwinX86_64TargetInfo(Triple); 7809 case llvm::Triple::GNU: 7810 return new MinGWX86_64TargetInfo(Triple); 7811 case llvm::Triple::MSVC: 7812 default: // Assume MSVC for unknown environments 7813 return new MicrosoftX86_64TargetInfo(Triple); 7814 } 7815 } 7816 case llvm::Triple::NaCl: 7817 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 7818 case llvm::Triple::PS4: 7819 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 7820 default: 7821 return new X86_64TargetInfo(Triple); 7822 } 7823 7824 case llvm::Triple::spir: { 7825 if (Triple.getOS() != llvm::Triple::UnknownOS || 7826 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7827 return nullptr; 7828 return new SPIR32TargetInfo(Triple); 7829 } 7830 case llvm::Triple::spir64: { 7831 if (Triple.getOS() != llvm::Triple::UnknownOS || 7832 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7833 return nullptr; 7834 return new SPIR64TargetInfo(Triple); 7835 } 7836 case llvm::Triple::wasm32: 7837 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 7838 return nullptr; 7839 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple); 7840 case llvm::Triple::wasm64: 7841 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 7842 return nullptr; 7843 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple); 7844 } 7845 } 7846 7847 /// CreateTargetInfo - Return the target info object for the specified target 7848 /// options. 7849 TargetInfo * 7850 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 7851 const std::shared_ptr<TargetOptions> &Opts) { 7852 llvm::Triple Triple(Opts->Triple); 7853 7854 // Construct the target 7855 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 7856 if (!Target) { 7857 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 7858 return nullptr; 7859 } 7860 Target->TargetOpts = Opts; 7861 7862 // Set the target CPU if specified. 7863 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 7864 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 7865 return nullptr; 7866 } 7867 7868 // Set the target ABI if specified. 7869 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 7870 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 7871 return nullptr; 7872 } 7873 7874 // Set the fp math unit. 7875 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 7876 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 7877 return nullptr; 7878 } 7879 7880 // Compute the default target features, we need the target to handle this 7881 // because features may have dependencies on one another. 7882 llvm::StringMap<bool> Features; 7883 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 7884 Opts->FeaturesAsWritten)) 7885 return nullptr; 7886 7887 // Add the features to the compile options. 7888 Opts->Features.clear(); 7889 for (const auto &F : Features) 7890 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 7891 7892 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 7893 return nullptr; 7894 7895 return Target.release(); 7896 } 7897