1 //===--- Targets.cpp - Implement -arch option and targets -----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements construction of a TargetInfo object from a
11 // target triple.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/MC/MCSectionMachO.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include <algorithm>
31 #include <memory>
32 using namespace clang;
33 
34 //===----------------------------------------------------------------------===//
35 //  Common code shared among targets.
36 //===----------------------------------------------------------------------===//
37 
38 /// DefineStd - Define a macro name and standard variants.  For example if
39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
40 /// when in GNU mode.
41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
42                       const LangOptions &Opts) {
43   assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
44 
45   // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
46   // in the user's namespace.
47   if (Opts.GNUMode)
48     Builder.defineMacro(MacroName);
49 
50   // Define __unix.
51   Builder.defineMacro("__" + MacroName);
52 
53   // Define __unix__.
54   Builder.defineMacro("__" + MacroName + "__");
55 }
56 
57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
58                             bool Tuning = true) {
59   Builder.defineMacro("__" + CPUName);
60   Builder.defineMacro("__" + CPUName + "__");
61   if (Tuning)
62     Builder.defineMacro("__tune_" + CPUName + "__");
63 }
64 
65 //===----------------------------------------------------------------------===//
66 // Defines specific to certain operating systems.
67 //===----------------------------------------------------------------------===//
68 
69 namespace {
70 template<typename TgtInfo>
71 class OSTargetInfo : public TgtInfo {
72 protected:
73   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
74                             MacroBuilder &Builder) const=0;
75 public:
76   OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
77   void getTargetDefines(const LangOptions &Opts,
78                         MacroBuilder &Builder) const override {
79     TgtInfo::getTargetDefines(Opts, Builder);
80     getOSDefines(Opts, TgtInfo::getTriple(), Builder);
81   }
82 
83 };
84 } // end anonymous namespace
85 
86 
87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
88                              const llvm::Triple &Triple,
89                              StringRef &PlatformName,
90                              VersionTuple &PlatformMinVersion) {
91   Builder.defineMacro("__APPLE_CC__", "6000");
92   Builder.defineMacro("__APPLE__");
93   Builder.defineMacro("OBJC_NEW_PROPERTIES");
94   // AddressSanitizer doesn't play well with source fortification, which is on
95   // by default on Darwin.
96   if (Opts.Sanitize.has(SanitizerKind::Address))
97     Builder.defineMacro("_FORTIFY_SOURCE", "0");
98 
99   if (!Opts.ObjCAutoRefCount) {
100     // __weak is always defined, for use in blocks and with objc pointers.
101     Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
102 
103     // Darwin defines __strong even in C mode (just to nothing).
104     if (Opts.getGC() != LangOptions::NonGC)
105       Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
106     else
107       Builder.defineMacro("__strong", "");
108 
109     // __unsafe_unretained is defined to nothing in non-ARC mode. We even
110     // allow this in C, since one might have block pointers in structs that
111     // are used in pure C code and in Objective-C ARC.
112     Builder.defineMacro("__unsafe_unretained", "");
113   }
114 
115   if (Opts.Static)
116     Builder.defineMacro("__STATIC__");
117   else
118     Builder.defineMacro("__DYNAMIC__");
119 
120   if (Opts.POSIXThreads)
121     Builder.defineMacro("_REENTRANT");
122 
123   // Get the platform type and version number from the triple.
124   unsigned Maj, Min, Rev;
125   if (Triple.isMacOSX()) {
126     Triple.getMacOSXVersion(Maj, Min, Rev);
127     PlatformName = "macosx";
128   } else {
129     Triple.getOSVersion(Maj, Min, Rev);
130     PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
131   }
132 
133   // If -target arch-pc-win32-macho option specified, we're
134   // generating code for Win32 ABI. No need to emit
135   // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
136   if (PlatformName == "win32") {
137     PlatformMinVersion = VersionTuple(Maj, Min, Rev);
138     return;
139   }
140 
141   // Set the appropriate OS version define.
142   if (Triple.isiOS()) {
143     assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
144     char Str[6];
145     Str[0] = '0' + Maj;
146     Str[1] = '0' + (Min / 10);
147     Str[2] = '0' + (Min % 10);
148     Str[3] = '0' + (Rev / 10);
149     Str[4] = '0' + (Rev % 10);
150     Str[5] = '\0';
151     Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
152                         Str);
153   } else if (Triple.isMacOSX()) {
154     // Note that the Driver allows versions which aren't representable in the
155     // define (because we only get a single digit for the minor and micro
156     // revision numbers). So, we limit them to the maximum representable
157     // version.
158     assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
159     char Str[7];
160     if (Maj < 10 || (Maj == 10 && Min < 10)) {
161       Str[0] = '0' + (Maj / 10);
162       Str[1] = '0' + (Maj % 10);
163       Str[2] = '0' + std::min(Min, 9U);
164       Str[3] = '0' + std::min(Rev, 9U);
165       Str[4] = '\0';
166     } else {
167       // Handle versions > 10.9.
168       Str[0] = '0' + (Maj / 10);
169       Str[1] = '0' + (Maj % 10);
170       Str[2] = '0' + (Min / 10);
171       Str[3] = '0' + (Min % 10);
172       Str[4] = '0' + (Rev / 10);
173       Str[5] = '0' + (Rev % 10);
174       Str[6] = '\0';
175     }
176     Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
177   }
178 
179   // Tell users about the kernel if there is one.
180   if (Triple.isOSDarwin())
181     Builder.defineMacro("__MACH__");
182 
183   PlatformMinVersion = VersionTuple(Maj, Min, Rev);
184 }
185 
186 namespace {
187 template<typename Target>
188 class DarwinTargetInfo : public OSTargetInfo<Target> {
189 protected:
190   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
191                     MacroBuilder &Builder) const override {
192     getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
193                      this->PlatformMinVersion);
194   }
195 
196 public:
197   DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
198     this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
199     this->MCountName = "\01mcount";
200   }
201 
202   std::string isValidSectionSpecifier(StringRef SR) const override {
203     // Let MCSectionMachO validate this.
204     StringRef Segment, Section;
205     unsigned TAA, StubSize;
206     bool HasTAA;
207     return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
208                                                        TAA, HasTAA, StubSize);
209   }
210 
211   const char *getStaticInitSectionSpecifier() const override {
212     // FIXME: We should return 0 when building kexts.
213     return "__TEXT,__StaticInit,regular,pure_instructions";
214   }
215 
216   /// Darwin does not support protected visibility.  Darwin's "default"
217   /// is very similar to ELF's "protected";  Darwin requires a "weak"
218   /// attribute on declarations that can be dynamically replaced.
219   bool hasProtectedVisibility() const override {
220     return false;
221   }
222 };
223 
224 
225 // DragonFlyBSD Target
226 template<typename Target>
227 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
228 protected:
229   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
230                     MacroBuilder &Builder) const override {
231     // DragonFly defines; list based off of gcc output
232     Builder.defineMacro("__DragonFly__");
233     Builder.defineMacro("__DragonFly_cc_version", "100001");
234     Builder.defineMacro("__ELF__");
235     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
236     Builder.defineMacro("__tune_i386__");
237     DefineStd(Builder, "unix", Opts);
238   }
239 public:
240   DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
241       : OSTargetInfo<Target>(Triple) {
242     this->UserLabelPrefix = "";
243 
244     switch (Triple.getArch()) {
245     default:
246     case llvm::Triple::x86:
247     case llvm::Triple::x86_64:
248       this->MCountName = ".mcount";
249       break;
250     }
251   }
252 };
253 
254 // FreeBSD Target
255 template<typename Target>
256 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
257 protected:
258   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
259                     MacroBuilder &Builder) const override {
260     // FreeBSD defines; list based off of gcc output
261 
262     unsigned Release = Triple.getOSMajorVersion();
263     if (Release == 0U)
264       Release = 8;
265 
266     Builder.defineMacro("__FreeBSD__", Twine(Release));
267     Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
268     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
269     DefineStd(Builder, "unix", Opts);
270     Builder.defineMacro("__ELF__");
271 
272     // On FreeBSD, wchar_t contains the number of the code point as
273     // used by the character set of the locale. These character sets are
274     // not necessarily a superset of ASCII.
275     //
276     // FIXME: This is wrong; the macro refers to the numerical values
277     // of wchar_t *literals*, which are not locale-dependent. However,
278     // FreeBSD systems apparently depend on us getting this wrong, and
279     // setting this to 1 is conforming even if all the basic source
280     // character literals have the same encoding as char and wchar_t.
281     Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
282   }
283 public:
284   FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
285     this->UserLabelPrefix = "";
286 
287     switch (Triple.getArch()) {
288     default:
289     case llvm::Triple::x86:
290     case llvm::Triple::x86_64:
291       this->MCountName = ".mcount";
292       break;
293     case llvm::Triple::mips:
294     case llvm::Triple::mipsel:
295     case llvm::Triple::ppc:
296     case llvm::Triple::ppc64:
297     case llvm::Triple::ppc64le:
298       this->MCountName = "_mcount";
299       break;
300     case llvm::Triple::arm:
301       this->MCountName = "__mcount";
302       break;
303     }
304   }
305 };
306 
307 // GNU/kFreeBSD Target
308 template<typename Target>
309 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
310 protected:
311   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
312                     MacroBuilder &Builder) const override {
313     // GNU/kFreeBSD defines; list based off of gcc output
314 
315     DefineStd(Builder, "unix", Opts);
316     Builder.defineMacro("__FreeBSD_kernel__");
317     Builder.defineMacro("__GLIBC__");
318     Builder.defineMacro("__ELF__");
319     if (Opts.POSIXThreads)
320       Builder.defineMacro("_REENTRANT");
321     if (Opts.CPlusPlus)
322       Builder.defineMacro("_GNU_SOURCE");
323   }
324 public:
325   KFreeBSDTargetInfo(const llvm::Triple &Triple)
326       : OSTargetInfo<Target>(Triple) {
327     this->UserLabelPrefix = "";
328   }
329 };
330 
331 // Minix Target
332 template<typename Target>
333 class MinixTargetInfo : public OSTargetInfo<Target> {
334 protected:
335   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
336                     MacroBuilder &Builder) const override {
337     // Minix defines
338 
339     Builder.defineMacro("__minix", "3");
340     Builder.defineMacro("_EM_WSIZE", "4");
341     Builder.defineMacro("_EM_PSIZE", "4");
342     Builder.defineMacro("_EM_SSIZE", "2");
343     Builder.defineMacro("_EM_LSIZE", "4");
344     Builder.defineMacro("_EM_FSIZE", "4");
345     Builder.defineMacro("_EM_DSIZE", "8");
346     Builder.defineMacro("__ELF__");
347     DefineStd(Builder, "unix", Opts);
348   }
349 public:
350   MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
351     this->UserLabelPrefix = "";
352   }
353 };
354 
355 // Linux target
356 template<typename Target>
357 class LinuxTargetInfo : public OSTargetInfo<Target> {
358 protected:
359   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
360                     MacroBuilder &Builder) const override {
361     // Linux defines; list based off of gcc output
362     DefineStd(Builder, "unix", Opts);
363     DefineStd(Builder, "linux", Opts);
364     Builder.defineMacro("__gnu_linux__");
365     Builder.defineMacro("__ELF__");
366     if (Triple.getEnvironment() == llvm::Triple::Android) {
367       Builder.defineMacro("__ANDROID__", "1");
368       unsigned Maj, Min, Rev;
369       Triple.getOSVersion(Maj, Min, Rev);
370       this->PlatformName = "android";
371       this->PlatformMinVersion = VersionTuple(Maj, Min, Rev);
372     }
373     if (Opts.POSIXThreads)
374       Builder.defineMacro("_REENTRANT");
375     if (Opts.CPlusPlus)
376       Builder.defineMacro("_GNU_SOURCE");
377   }
378 public:
379   LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
380     this->UserLabelPrefix = "";
381     this->WIntType = TargetInfo::UnsignedInt;
382 
383     switch (Triple.getArch()) {
384     default:
385       break;
386     case llvm::Triple::ppc:
387     case llvm::Triple::ppc64:
388     case llvm::Triple::ppc64le:
389       this->MCountName = "_mcount";
390       break;
391     }
392   }
393 
394   const char *getStaticInitSectionSpecifier() const override {
395     return ".text.startup";
396   }
397 };
398 
399 // NetBSD Target
400 template<typename Target>
401 class NetBSDTargetInfo : public OSTargetInfo<Target> {
402 protected:
403   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
404                     MacroBuilder &Builder) const override {
405     // NetBSD defines; list based off of gcc output
406     Builder.defineMacro("__NetBSD__");
407     Builder.defineMacro("__unix__");
408     Builder.defineMacro("__ELF__");
409     if (Opts.POSIXThreads)
410       Builder.defineMacro("_POSIX_THREADS");
411 
412     switch (Triple.getArch()) {
413     default:
414       break;
415     case llvm::Triple::arm:
416     case llvm::Triple::armeb:
417     case llvm::Triple::thumb:
418     case llvm::Triple::thumbeb:
419       Builder.defineMacro("__ARM_DWARF_EH__");
420       break;
421     }
422   }
423 public:
424   NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
425     this->UserLabelPrefix = "";
426   }
427 };
428 
429 // OpenBSD Target
430 template<typename Target>
431 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
432 protected:
433   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
434                     MacroBuilder &Builder) const override {
435     // OpenBSD defines; list based off of gcc output
436 
437     Builder.defineMacro("__OpenBSD__");
438     DefineStd(Builder, "unix", Opts);
439     Builder.defineMacro("__ELF__");
440     if (Opts.POSIXThreads)
441       Builder.defineMacro("_REENTRANT");
442   }
443 public:
444   OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
445     this->UserLabelPrefix = "";
446     this->TLSSupported = false;
447 
448       switch (Triple.getArch()) {
449         default:
450         case llvm::Triple::x86:
451         case llvm::Triple::x86_64:
452         case llvm::Triple::arm:
453         case llvm::Triple::sparc:
454           this->MCountName = "__mcount";
455           break;
456         case llvm::Triple::mips64:
457         case llvm::Triple::mips64el:
458         case llvm::Triple::ppc:
459         case llvm::Triple::sparcv9:
460           this->MCountName = "_mcount";
461           break;
462       }
463   }
464 };
465 
466 // Bitrig Target
467 template<typename Target>
468 class BitrigTargetInfo : public OSTargetInfo<Target> {
469 protected:
470   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
471                     MacroBuilder &Builder) const override {
472     // Bitrig defines; list based off of gcc output
473 
474     Builder.defineMacro("__Bitrig__");
475     DefineStd(Builder, "unix", Opts);
476     Builder.defineMacro("__ELF__");
477     if (Opts.POSIXThreads)
478       Builder.defineMacro("_REENTRANT");
479 
480     switch (Triple.getArch()) {
481     default:
482       break;
483     case llvm::Triple::arm:
484     case llvm::Triple::armeb:
485     case llvm::Triple::thumb:
486     case llvm::Triple::thumbeb:
487       Builder.defineMacro("__ARM_DWARF_EH__");
488       break;
489     }
490   }
491 public:
492   BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
493     this->UserLabelPrefix = "";
494     this->MCountName = "__mcount";
495   }
496 };
497 
498 // PSP Target
499 template<typename Target>
500 class PSPTargetInfo : public OSTargetInfo<Target> {
501 protected:
502   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
503                     MacroBuilder &Builder) const override {
504     // PSP defines; list based on the output of the pspdev gcc toolchain.
505     Builder.defineMacro("PSP");
506     Builder.defineMacro("_PSP");
507     Builder.defineMacro("__psp__");
508     Builder.defineMacro("__ELF__");
509   }
510 public:
511   PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
512     this->UserLabelPrefix = "";
513   }
514 };
515 
516 // PS3 PPU Target
517 template<typename Target>
518 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
519 protected:
520   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
521                     MacroBuilder &Builder) const override {
522     // PS3 PPU defines.
523     Builder.defineMacro("__PPC__");
524     Builder.defineMacro("__PPU__");
525     Builder.defineMacro("__CELLOS_LV2__");
526     Builder.defineMacro("__ELF__");
527     Builder.defineMacro("__LP32__");
528     Builder.defineMacro("_ARCH_PPC64");
529     Builder.defineMacro("__powerpc64__");
530   }
531 public:
532   PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
533     this->UserLabelPrefix = "";
534     this->LongWidth = this->LongAlign = 32;
535     this->PointerWidth = this->PointerAlign = 32;
536     this->IntMaxType = TargetInfo::SignedLongLong;
537     this->Int64Type = TargetInfo::SignedLongLong;
538     this->SizeType = TargetInfo::UnsignedInt;
539     this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64";
540   }
541 };
542 
543 template <typename Target>
544 class PS4OSTargetInfo : public OSTargetInfo<Target> {
545 protected:
546   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
547                     MacroBuilder &Builder) const override {
548     Builder.defineMacro("__FreeBSD__", "9");
549     Builder.defineMacro("__FreeBSD_cc_version", "900001");
550     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
551     DefineStd(Builder, "unix", Opts);
552     Builder.defineMacro("__ELF__");
553     Builder.defineMacro("__PS4__");
554   }
555 public:
556   PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
557     this->WCharType = this->UnsignedShort;
558 
559     this->UserLabelPrefix = "";
560 
561     switch (Triple.getArch()) {
562     default:
563     case llvm::Triple::x86_64:
564       this->MCountName = ".mcount";
565       break;
566     }
567   }
568 };
569 
570 // Solaris target
571 template<typename Target>
572 class SolarisTargetInfo : public OSTargetInfo<Target> {
573 protected:
574   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
575                     MacroBuilder &Builder) const override {
576     DefineStd(Builder, "sun", Opts);
577     DefineStd(Builder, "unix", Opts);
578     Builder.defineMacro("__ELF__");
579     Builder.defineMacro("__svr4__");
580     Builder.defineMacro("__SVR4");
581     // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
582     // newer, but to 500 for everything else.  feature_test.h has a check to
583     // ensure that you are not using C99 with an old version of X/Open or C89
584     // with a new version.
585     if (Opts.C99)
586       Builder.defineMacro("_XOPEN_SOURCE", "600");
587     else
588       Builder.defineMacro("_XOPEN_SOURCE", "500");
589     if (Opts.CPlusPlus)
590       Builder.defineMacro("__C99FEATURES__");
591     Builder.defineMacro("_LARGEFILE_SOURCE");
592     Builder.defineMacro("_LARGEFILE64_SOURCE");
593     Builder.defineMacro("__EXTENSIONS__");
594     Builder.defineMacro("_REENTRANT");
595   }
596 public:
597   SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
598     this->UserLabelPrefix = "";
599     this->WCharType = this->SignedInt;
600     // FIXME: WIntType should be SignedLong
601   }
602 };
603 
604 // Windows target
605 template<typename Target>
606 class WindowsTargetInfo : public OSTargetInfo<Target> {
607 protected:
608   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
609                     MacroBuilder &Builder) const override {
610     Builder.defineMacro("_WIN32");
611   }
612   void getVisualStudioDefines(const LangOptions &Opts,
613                               MacroBuilder &Builder) const {
614     if (Opts.CPlusPlus) {
615       if (Opts.RTTIData)
616         Builder.defineMacro("_CPPRTTI");
617 
618       if (Opts.CXXExceptions)
619         Builder.defineMacro("_CPPUNWIND");
620     }
621 
622     if (!Opts.CharIsSigned)
623       Builder.defineMacro("_CHAR_UNSIGNED");
624 
625     // FIXME: POSIXThreads isn't exactly the option this should be defined for,
626     //        but it works for now.
627     if (Opts.POSIXThreads)
628       Builder.defineMacro("_MT");
629 
630     if (Opts.MSCompatibilityVersion) {
631       Builder.defineMacro("_MSC_VER",
632                           Twine(Opts.MSCompatibilityVersion / 100000));
633       Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
634       // FIXME We cannot encode the revision information into 32-bits
635       Builder.defineMacro("_MSC_BUILD", Twine(1));
636     }
637 
638     if (Opts.MicrosoftExt) {
639       Builder.defineMacro("_MSC_EXTENSIONS");
640 
641       if (Opts.CPlusPlus11) {
642         Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
643         Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
644         Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
645       }
646     }
647 
648     Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
649   }
650 
651 public:
652   WindowsTargetInfo(const llvm::Triple &Triple)
653       : OSTargetInfo<Target>(Triple) {}
654 };
655 
656 template <typename Target>
657 class NaClTargetInfo : public OSTargetInfo<Target> {
658 protected:
659   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
660                     MacroBuilder &Builder) const override {
661     if (Opts.POSIXThreads)
662       Builder.defineMacro("_REENTRANT");
663     if (Opts.CPlusPlus)
664       Builder.defineMacro("_GNU_SOURCE");
665 
666     DefineStd(Builder, "unix", Opts);
667     Builder.defineMacro("__ELF__");
668     Builder.defineMacro("__native_client__");
669   }
670 
671 public:
672   NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
673     this->UserLabelPrefix = "";
674     this->LongAlign = 32;
675     this->LongWidth = 32;
676     this->PointerAlign = 32;
677     this->PointerWidth = 32;
678     this->IntMaxType = TargetInfo::SignedLongLong;
679     this->Int64Type = TargetInfo::SignedLongLong;
680     this->DoubleAlign = 64;
681     this->LongDoubleWidth = 64;
682     this->LongDoubleAlign = 64;
683     this->LongLongWidth = 64;
684     this->LongLongAlign = 64;
685     this->SizeType = TargetInfo::UnsignedInt;
686     this->PtrDiffType = TargetInfo::SignedInt;
687     this->IntPtrType = TargetInfo::SignedInt;
688     // RegParmMax is inherited from the underlying architecture
689     this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
690     if (Triple.getArch() == llvm::Triple::arm) {
691       this->DescriptionString =
692           "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128";
693     } else if (Triple.getArch() == llvm::Triple::x86) {
694       this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
695     } else if (Triple.getArch() == llvm::Triple::x86_64) {
696       this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128";
697     } else if (Triple.getArch() == llvm::Triple::mipsel) {
698       // Handled on mips' setDescriptionString.
699     } else {
700       assert(Triple.getArch() == llvm::Triple::le32);
701       this->DescriptionString = "e-p:32:32-i64:64";
702     }
703   }
704 };
705 } // end anonymous namespace.
706 
707 //===----------------------------------------------------------------------===//
708 // Specific target implementations.
709 //===----------------------------------------------------------------------===//
710 
711 namespace {
712 // PPC abstract base class
713 class PPCTargetInfo : public TargetInfo {
714   static const Builtin::Info BuiltinInfo[];
715   static const char * const GCCRegNames[];
716   static const TargetInfo::GCCRegAlias GCCRegAliases[];
717   std::string CPU;
718 
719   // Target cpu features.
720   bool HasVSX;
721   bool HasP8Vector;
722   bool HasP8Crypto;
723 
724 protected:
725   std::string ABI;
726 
727 public:
728   PPCTargetInfo(const llvm::Triple &Triple)
729     : TargetInfo(Triple), HasVSX(false), HasP8Vector(false),
730       HasP8Crypto(false) {
731     BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
732     LongDoubleWidth = LongDoubleAlign = 128;
733     LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
734   }
735 
736   /// \brief Flags for architecture specific defines.
737   typedef enum {
738     ArchDefineNone  = 0,
739     ArchDefineName  = 1 << 0, // <name> is substituted for arch name.
740     ArchDefinePpcgr = 1 << 1,
741     ArchDefinePpcsq = 1 << 2,
742     ArchDefine440   = 1 << 3,
743     ArchDefine603   = 1 << 4,
744     ArchDefine604   = 1 << 5,
745     ArchDefinePwr4  = 1 << 6,
746     ArchDefinePwr5  = 1 << 7,
747     ArchDefinePwr5x = 1 << 8,
748     ArchDefinePwr6  = 1 << 9,
749     ArchDefinePwr6x = 1 << 10,
750     ArchDefinePwr7  = 1 << 11,
751     ArchDefinePwr8  = 1 << 12,
752     ArchDefineA2    = 1 << 13,
753     ArchDefineA2q   = 1 << 14
754   } ArchDefineTypes;
755 
756   // Note: GCC recognizes the following additional cpus:
757   //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
758   //  821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
759   //  titan, rs64.
760   bool setCPU(const std::string &Name) override {
761     bool CPUKnown = llvm::StringSwitch<bool>(Name)
762       .Case("generic", true)
763       .Case("440", true)
764       .Case("450", true)
765       .Case("601", true)
766       .Case("602", true)
767       .Case("603", true)
768       .Case("603e", true)
769       .Case("603ev", true)
770       .Case("604", true)
771       .Case("604e", true)
772       .Case("620", true)
773       .Case("630", true)
774       .Case("g3", true)
775       .Case("7400", true)
776       .Case("g4", true)
777       .Case("7450", true)
778       .Case("g4+", true)
779       .Case("750", true)
780       .Case("970", true)
781       .Case("g5", true)
782       .Case("a2", true)
783       .Case("a2q", true)
784       .Case("e500mc", true)
785       .Case("e5500", true)
786       .Case("power3", true)
787       .Case("pwr3", true)
788       .Case("power4", true)
789       .Case("pwr4", true)
790       .Case("power5", true)
791       .Case("pwr5", true)
792       .Case("power5x", true)
793       .Case("pwr5x", true)
794       .Case("power6", true)
795       .Case("pwr6", true)
796       .Case("power6x", true)
797       .Case("pwr6x", true)
798       .Case("power7", true)
799       .Case("pwr7", true)
800       .Case("power8", true)
801       .Case("pwr8", true)
802       .Case("powerpc", true)
803       .Case("ppc", true)
804       .Case("powerpc64", true)
805       .Case("ppc64", true)
806       .Case("powerpc64le", true)
807       .Case("ppc64le", true)
808       .Default(false);
809 
810     if (CPUKnown)
811       CPU = Name;
812 
813     return CPUKnown;
814   }
815 
816 
817   StringRef getABI() const override { return ABI; }
818 
819   void getTargetBuiltins(const Builtin::Info *&Records,
820                          unsigned &NumRecords) const override {
821     Records = BuiltinInfo;
822     NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
823   }
824 
825   bool isCLZForZeroUndef() const override { return false; }
826 
827   void getTargetDefines(const LangOptions &Opts,
828                         MacroBuilder &Builder) const override;
829 
830   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
831 
832   bool handleTargetFeatures(std::vector<std::string> &Features,
833                             DiagnosticsEngine &Diags) override;
834   bool hasFeature(StringRef Feature) const override;
835 
836   void getGCCRegNames(const char * const *&Names,
837                       unsigned &NumNames) const override;
838   void getGCCRegAliases(const GCCRegAlias *&Aliases,
839                         unsigned &NumAliases) const override;
840   bool validateAsmConstraint(const char *&Name,
841                              TargetInfo::ConstraintInfo &Info) const override {
842     switch (*Name) {
843     default: return false;
844     case 'O': // Zero
845       break;
846     case 'b': // Base register
847     case 'f': // Floating point register
848       Info.setAllowsRegister();
849       break;
850     // FIXME: The following are added to allow parsing.
851     // I just took a guess at what the actions should be.
852     // Also, is more specific checking needed?  I.e. specific registers?
853     case 'd': // Floating point register (containing 64-bit value)
854     case 'v': // Altivec vector register
855       Info.setAllowsRegister();
856       break;
857     case 'w':
858       switch (Name[1]) {
859         case 'd':// VSX vector register to hold vector double data
860         case 'f':// VSX vector register to hold vector float data
861         case 's':// VSX vector register to hold scalar float data
862         case 'a':// Any VSX register
863         case 'c':// An individual CR bit
864           break;
865         default:
866           return false;
867       }
868       Info.setAllowsRegister();
869       Name++; // Skip over 'w'.
870       break;
871     case 'h': // `MQ', `CTR', or `LINK' register
872     case 'q': // `MQ' register
873     case 'c': // `CTR' register
874     case 'l': // `LINK' register
875     case 'x': // `CR' register (condition register) number 0
876     case 'y': // `CR' register (condition register)
877     case 'z': // `XER[CA]' carry bit (part of the XER register)
878       Info.setAllowsRegister();
879       break;
880     case 'I': // Signed 16-bit constant
881     case 'J': // Unsigned 16-bit constant shifted left 16 bits
882               //  (use `L' instead for SImode constants)
883     case 'K': // Unsigned 16-bit constant
884     case 'L': // Signed 16-bit constant shifted left 16 bits
885     case 'M': // Constant larger than 31
886     case 'N': // Exact power of 2
887     case 'P': // Constant whose negation is a signed 16-bit constant
888     case 'G': // Floating point constant that can be loaded into a
889               // register with one instruction per word
890     case 'H': // Integer/Floating point constant that can be loaded
891               // into a register using three instructions
892       break;
893     case 'm': // Memory operand. Note that on PowerPC targets, m can
894               // include addresses that update the base register. It
895               // is therefore only safe to use `m' in an asm statement
896               // if that asm statement accesses the operand exactly once.
897               // The asm statement must also use `%U<opno>' as a
898               // placeholder for the "update" flag in the corresponding
899               // load or store instruction. For example:
900               // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
901               // is correct but:
902               // asm ("st %1,%0" : "=m" (mem) : "r" (val));
903               // is not. Use es rather than m if you don't want the base
904               // register to be updated.
905     case 'e':
906       if (Name[1] != 's')
907           return false;
908               // es: A "stable" memory operand; that is, one which does not
909               // include any automodification of the base register. Unlike
910               // `m', this constraint can be used in asm statements that
911               // might access the operand several times, or that might not
912               // access it at all.
913       Info.setAllowsMemory();
914       Name++; // Skip over 'e'.
915       break;
916     case 'Q': // Memory operand that is an offset from a register (it is
917               // usually better to use `m' or `es' in asm statements)
918     case 'Z': // Memory operand that is an indexed or indirect from a
919               // register (it is usually better to use `m' or `es' in
920               // asm statements)
921       Info.setAllowsMemory();
922       Info.setAllowsRegister();
923       break;
924     case 'R': // AIX TOC entry
925     case 'a': // Address operand that is an indexed or indirect from a
926               // register (`p' is preferable for asm statements)
927     case 'S': // Constant suitable as a 64-bit mask operand
928     case 'T': // Constant suitable as a 32-bit mask operand
929     case 'U': // System V Release 4 small data area reference
930     case 't': // AND masks that can be performed by two rldic{l, r}
931               // instructions
932     case 'W': // Vector constant that does not require memory
933     case 'j': // Vector constant that is all zeros.
934       break;
935     // End FIXME.
936     }
937     return true;
938   }
939   std::string convertConstraint(const char *&Constraint) const override {
940     std::string R;
941     switch (*Constraint) {
942     case 'e':
943     case 'w':
944       // Two-character constraint; add "^" hint for later parsing.
945       R = std::string("^") + std::string(Constraint, 2);
946       Constraint++;
947       break;
948     default:
949       return TargetInfo::convertConstraint(Constraint);
950     }
951     return R;
952   }
953   const char *getClobbers() const override {
954     return "";
955   }
956   int getEHDataRegisterNumber(unsigned RegNo) const override {
957     if (RegNo == 0) return 3;
958     if (RegNo == 1) return 4;
959     return -1;
960   }
961 };
962 
963 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
964 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
965 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
966                                               ALL_LANGUAGES },
967 #include "clang/Basic/BuiltinsPPC.def"
968 };
969 
970 /// handleTargetFeatures - Perform initialization based on the user
971 /// configured set of features.
972 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
973                                          DiagnosticsEngine &Diags) {
974   for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
975     // Ignore disabled features.
976     if (Features[i][0] == '-')
977       continue;
978 
979     StringRef Feature = StringRef(Features[i]).substr(1);
980 
981     if (Feature == "vsx") {
982       HasVSX = true;
983       continue;
984     }
985 
986     if (Feature == "power8-vector") {
987       HasP8Vector = true;
988       continue;
989     }
990 
991     if (Feature == "crypto") {
992       HasP8Crypto = true;
993       continue;
994     }
995 
996     // TODO: Finish this list and add an assert that we've handled them
997     // all.
998   }
999 
1000   return true;
1001 }
1002 
1003 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
1004 /// #defines that are not tied to a specific subtarget.
1005 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
1006                                      MacroBuilder &Builder) const {
1007   // Target identification.
1008   Builder.defineMacro("__ppc__");
1009   Builder.defineMacro("__PPC__");
1010   Builder.defineMacro("_ARCH_PPC");
1011   Builder.defineMacro("__powerpc__");
1012   Builder.defineMacro("__POWERPC__");
1013   if (PointerWidth == 64) {
1014     Builder.defineMacro("_ARCH_PPC64");
1015     Builder.defineMacro("__powerpc64__");
1016     Builder.defineMacro("__ppc64__");
1017     Builder.defineMacro("__PPC64__");
1018   }
1019 
1020   // Target properties.
1021   if (getTriple().getArch() == llvm::Triple::ppc64le) {
1022     Builder.defineMacro("_LITTLE_ENDIAN");
1023   } else {
1024     if (getTriple().getOS() != llvm::Triple::NetBSD &&
1025         getTriple().getOS() != llvm::Triple::OpenBSD)
1026       Builder.defineMacro("_BIG_ENDIAN");
1027   }
1028 
1029   // ABI options.
1030   if (ABI == "elfv1")
1031     Builder.defineMacro("_CALL_ELF", "1");
1032   if (ABI == "elfv2")
1033     Builder.defineMacro("_CALL_ELF", "2");
1034 
1035   // Subtarget options.
1036   Builder.defineMacro("__NATURAL_ALIGNMENT__");
1037   Builder.defineMacro("__REGISTER_PREFIX__", "");
1038 
1039   // FIXME: Should be controlled by command line option.
1040   if (LongDoubleWidth == 128)
1041     Builder.defineMacro("__LONG_DOUBLE_128__");
1042 
1043   if (Opts.AltiVec) {
1044     Builder.defineMacro("__VEC__", "10206");
1045     Builder.defineMacro("__ALTIVEC__");
1046   }
1047 
1048   // CPU identification.
1049   ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1050     .Case("440",   ArchDefineName)
1051     .Case("450",   ArchDefineName | ArchDefine440)
1052     .Case("601",   ArchDefineName)
1053     .Case("602",   ArchDefineName | ArchDefinePpcgr)
1054     .Case("603",   ArchDefineName | ArchDefinePpcgr)
1055     .Case("603e",  ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1056     .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1057     .Case("604",   ArchDefineName | ArchDefinePpcgr)
1058     .Case("604e",  ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1059     .Case("620",   ArchDefineName | ArchDefinePpcgr)
1060     .Case("630",   ArchDefineName | ArchDefinePpcgr)
1061     .Case("7400",  ArchDefineName | ArchDefinePpcgr)
1062     .Case("7450",  ArchDefineName | ArchDefinePpcgr)
1063     .Case("750",   ArchDefineName | ArchDefinePpcgr)
1064     .Case("970",   ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1065                      | ArchDefinePpcsq)
1066     .Case("a2",    ArchDefineA2)
1067     .Case("a2q",   ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1068     .Case("pwr3",  ArchDefinePpcgr)
1069     .Case("pwr4",  ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1070     .Case("pwr5",  ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1071                      | ArchDefinePpcsq)
1072     .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1073                      | ArchDefinePpcgr | ArchDefinePpcsq)
1074     .Case("pwr6",  ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1075                      | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1076     .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1077                      | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1078                      | ArchDefinePpcsq)
1079     .Case("pwr7",  ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1080                      | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1081                      | ArchDefinePpcgr | ArchDefinePpcsq)
1082     .Case("pwr8",  ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1083                      | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1084                      | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1085     .Case("power3",  ArchDefinePpcgr)
1086     .Case("power4",  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1087     .Case("power5",  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1088                        | ArchDefinePpcsq)
1089     .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1090                        | ArchDefinePpcgr | ArchDefinePpcsq)
1091     .Case("power6",  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1092                        | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1093     .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1094                        | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1095                        | ArchDefinePpcsq)
1096     .Case("power7",  ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1097                        | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1098                        | ArchDefinePpcgr | ArchDefinePpcsq)
1099     .Case("power8",  ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1100                        | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1101                        | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1102     .Default(ArchDefineNone);
1103 
1104   if (defs & ArchDefineName)
1105     Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1106   if (defs & ArchDefinePpcgr)
1107     Builder.defineMacro("_ARCH_PPCGR");
1108   if (defs & ArchDefinePpcsq)
1109     Builder.defineMacro("_ARCH_PPCSQ");
1110   if (defs & ArchDefine440)
1111     Builder.defineMacro("_ARCH_440");
1112   if (defs & ArchDefine603)
1113     Builder.defineMacro("_ARCH_603");
1114   if (defs & ArchDefine604)
1115     Builder.defineMacro("_ARCH_604");
1116   if (defs & ArchDefinePwr4)
1117     Builder.defineMacro("_ARCH_PWR4");
1118   if (defs & ArchDefinePwr5)
1119     Builder.defineMacro("_ARCH_PWR5");
1120   if (defs & ArchDefinePwr5x)
1121     Builder.defineMacro("_ARCH_PWR5X");
1122   if (defs & ArchDefinePwr6)
1123     Builder.defineMacro("_ARCH_PWR6");
1124   if (defs & ArchDefinePwr6x)
1125     Builder.defineMacro("_ARCH_PWR6X");
1126   if (defs & ArchDefinePwr7)
1127     Builder.defineMacro("_ARCH_PWR7");
1128   if (defs & ArchDefinePwr8)
1129     Builder.defineMacro("_ARCH_PWR8");
1130   if (defs & ArchDefineA2)
1131     Builder.defineMacro("_ARCH_A2");
1132   if (defs & ArchDefineA2q) {
1133     Builder.defineMacro("_ARCH_A2Q");
1134     Builder.defineMacro("_ARCH_QP");
1135   }
1136 
1137   if (getTriple().getVendor() == llvm::Triple::BGQ) {
1138     Builder.defineMacro("__bg__");
1139     Builder.defineMacro("__THW_BLUEGENE__");
1140     Builder.defineMacro("__bgq__");
1141     Builder.defineMacro("__TOS_BGQ__");
1142   }
1143 
1144   if (HasVSX)
1145     Builder.defineMacro("__VSX__");
1146   if (HasP8Vector)
1147     Builder.defineMacro("__POWER8_VECTOR__");
1148   if (HasP8Crypto)
1149     Builder.defineMacro("__CRYPTO__");
1150 
1151   // FIXME: The following are not yet generated here by Clang, but are
1152   //        generated by GCC:
1153   //
1154   //   _SOFT_FLOAT_
1155   //   __RECIP_PRECISION__
1156   //   __APPLE_ALTIVEC__
1157   //   __RECIP__
1158   //   __RECIPF__
1159   //   __RSQRTE__
1160   //   __RSQRTEF__
1161   //   _SOFT_DOUBLE_
1162   //   __NO_LWSYNC__
1163   //   __HAVE_BSWAP__
1164   //   __LONGDOUBLE128
1165   //   __CMODEL_MEDIUM__
1166   //   __CMODEL_LARGE__
1167   //   _CALL_SYSV
1168   //   _CALL_DARWIN
1169   //   __NO_FPRS__
1170 }
1171 
1172 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1173   Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1174     .Case("7400", true)
1175     .Case("g4", true)
1176     .Case("7450", true)
1177     .Case("g4+", true)
1178     .Case("970", true)
1179     .Case("g5", true)
1180     .Case("pwr6", true)
1181     .Case("pwr7", true)
1182     .Case("pwr8", true)
1183     .Case("ppc64", true)
1184     .Case("ppc64le", true)
1185     .Default(false);
1186 
1187   Features["qpx"] = (CPU == "a2q");
1188   Features["crypto"] = llvm::StringSwitch<bool>(CPU)
1189     .Case("ppc64le", true)
1190     .Case("pwr8", true)
1191     .Default(false);
1192   Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
1193     .Case("ppc64le", true)
1194     .Case("pwr8", true)
1195     .Default(false);
1196 }
1197 
1198 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1199   return llvm::StringSwitch<bool>(Feature)
1200     .Case("powerpc", true)
1201     .Case("vsx", HasVSX)
1202     .Case("power8-vector", HasP8Vector)
1203     .Case("crypto", HasP8Crypto)
1204     .Default(false);
1205 }
1206 
1207 const char * const PPCTargetInfo::GCCRegNames[] = {
1208   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1209   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1210   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1211   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1212   "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1213   "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1214   "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1215   "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1216   "mq", "lr", "ctr", "ap",
1217   "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1218   "xer",
1219   "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1220   "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1221   "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1222   "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1223   "vrsave", "vscr",
1224   "spe_acc", "spefscr",
1225   "sfp"
1226 };
1227 
1228 void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1229                                    unsigned &NumNames) const {
1230   Names = GCCRegNames;
1231   NumNames = llvm::array_lengthof(GCCRegNames);
1232 }
1233 
1234 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1235   // While some of these aliases do map to different registers
1236   // they still share the same register name.
1237   { { "0" }, "r0" },
1238   { { "1"}, "r1" },
1239   { { "2" }, "r2" },
1240   { { "3" }, "r3" },
1241   { { "4" }, "r4" },
1242   { { "5" }, "r5" },
1243   { { "6" }, "r6" },
1244   { { "7" }, "r7" },
1245   { { "8" }, "r8" },
1246   { { "9" }, "r9" },
1247   { { "10" }, "r10" },
1248   { { "11" }, "r11" },
1249   { { "12" }, "r12" },
1250   { { "13" }, "r13" },
1251   { { "14" }, "r14" },
1252   { { "15" }, "r15" },
1253   { { "16" }, "r16" },
1254   { { "17" }, "r17" },
1255   { { "18" }, "r18" },
1256   { { "19" }, "r19" },
1257   { { "20" }, "r20" },
1258   { { "21" }, "r21" },
1259   { { "22" }, "r22" },
1260   { { "23" }, "r23" },
1261   { { "24" }, "r24" },
1262   { { "25" }, "r25" },
1263   { { "26" }, "r26" },
1264   { { "27" }, "r27" },
1265   { { "28" }, "r28" },
1266   { { "29" }, "r29" },
1267   { { "30" }, "r30" },
1268   { { "31" }, "r31" },
1269   { { "fr0" }, "f0" },
1270   { { "fr1" }, "f1" },
1271   { { "fr2" }, "f2" },
1272   { { "fr3" }, "f3" },
1273   { { "fr4" }, "f4" },
1274   { { "fr5" }, "f5" },
1275   { { "fr6" }, "f6" },
1276   { { "fr7" }, "f7" },
1277   { { "fr8" }, "f8" },
1278   { { "fr9" }, "f9" },
1279   { { "fr10" }, "f10" },
1280   { { "fr11" }, "f11" },
1281   { { "fr12" }, "f12" },
1282   { { "fr13" }, "f13" },
1283   { { "fr14" }, "f14" },
1284   { { "fr15" }, "f15" },
1285   { { "fr16" }, "f16" },
1286   { { "fr17" }, "f17" },
1287   { { "fr18" }, "f18" },
1288   { { "fr19" }, "f19" },
1289   { { "fr20" }, "f20" },
1290   { { "fr21" }, "f21" },
1291   { { "fr22" }, "f22" },
1292   { { "fr23" }, "f23" },
1293   { { "fr24" }, "f24" },
1294   { { "fr25" }, "f25" },
1295   { { "fr26" }, "f26" },
1296   { { "fr27" }, "f27" },
1297   { { "fr28" }, "f28" },
1298   { { "fr29" }, "f29" },
1299   { { "fr30" }, "f30" },
1300   { { "fr31" }, "f31" },
1301   { { "cc" }, "cr0" },
1302 };
1303 
1304 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1305                                      unsigned &NumAliases) const {
1306   Aliases = GCCRegAliases;
1307   NumAliases = llvm::array_lengthof(GCCRegAliases);
1308 }
1309 } // end anonymous namespace.
1310 
1311 namespace {
1312 class PPC32TargetInfo : public PPCTargetInfo {
1313 public:
1314   PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1315     DescriptionString = "E-m:e-p:32:32-i64:64-n32";
1316 
1317     switch (getTriple().getOS()) {
1318     case llvm::Triple::Linux:
1319     case llvm::Triple::FreeBSD:
1320     case llvm::Triple::NetBSD:
1321       SizeType = UnsignedInt;
1322       PtrDiffType = SignedInt;
1323       IntPtrType = SignedInt;
1324       break;
1325     default:
1326       break;
1327     }
1328 
1329     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1330       LongDoubleWidth = LongDoubleAlign = 64;
1331       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1332     }
1333 
1334     // PPC32 supports atomics up to 4 bytes.
1335     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1336   }
1337 
1338   BuiltinVaListKind getBuiltinVaListKind() const override {
1339     // This is the ELF definition, and is overridden by the Darwin sub-target
1340     return TargetInfo::PowerABIBuiltinVaList;
1341   }
1342 };
1343 } // end anonymous namespace.
1344 
1345 // Note: ABI differences may eventually require us to have a separate
1346 // TargetInfo for little endian.
1347 namespace {
1348 class PPC64TargetInfo : public PPCTargetInfo {
1349 public:
1350   PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1351     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1352     IntMaxType = SignedLong;
1353     Int64Type = SignedLong;
1354 
1355     if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1356       DescriptionString = "e-m:e-i64:64-n32:64";
1357       ABI = "elfv2";
1358     } else {
1359       DescriptionString = "E-m:e-i64:64-n32:64";
1360       ABI = "elfv1";
1361     }
1362 
1363     switch (getTriple().getOS()) {
1364     case llvm::Triple::FreeBSD:
1365       LongDoubleWidth = LongDoubleAlign = 64;
1366       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1367       break;
1368     case llvm::Triple::NetBSD:
1369       IntMaxType = SignedLongLong;
1370       Int64Type = SignedLongLong;
1371       break;
1372     default:
1373       break;
1374     }
1375 
1376     // PPC64 supports atomics up to 8 bytes.
1377     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1378   }
1379   BuiltinVaListKind getBuiltinVaListKind() const override {
1380     return TargetInfo::CharPtrBuiltinVaList;
1381   }
1382   // PPC64 Linux-specifc ABI options.
1383   bool setABI(const std::string &Name) override {
1384     if (Name == "elfv1" || Name == "elfv2") {
1385       ABI = Name;
1386       return true;
1387     }
1388     return false;
1389   }
1390 };
1391 } // end anonymous namespace.
1392 
1393 
1394 namespace {
1395 class DarwinPPC32TargetInfo :
1396   public DarwinTargetInfo<PPC32TargetInfo> {
1397 public:
1398   DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1399       : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1400     HasAlignMac68kSupport = true;
1401     BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1402     PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1403     LongLongAlign = 32;
1404     SuitableAlign = 128;
1405     DescriptionString = "E-m:o-p:32:32-f64:32:64-n32";
1406   }
1407   BuiltinVaListKind getBuiltinVaListKind() const override {
1408     return TargetInfo::CharPtrBuiltinVaList;
1409   }
1410 };
1411 
1412 class DarwinPPC64TargetInfo :
1413   public DarwinTargetInfo<PPC64TargetInfo> {
1414 public:
1415   DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1416       : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1417     HasAlignMac68kSupport = true;
1418     SuitableAlign = 128;
1419     DescriptionString = "E-m:o-i64:64-n32:64";
1420   }
1421 };
1422 } // end anonymous namespace.
1423 
1424 namespace {
1425   static const unsigned NVPTXAddrSpaceMap[] = {
1426     1,    // opencl_global
1427     3,    // opencl_local
1428     4,    // opencl_constant
1429     // FIXME: generic has to be added to the target
1430     0,    // opencl_generic
1431     1,    // cuda_device
1432     4,    // cuda_constant
1433     3,    // cuda_shared
1434   };
1435   class NVPTXTargetInfo : public TargetInfo {
1436     static const char * const GCCRegNames[];
1437     static const Builtin::Info BuiltinInfo[];
1438 
1439   // The GPU profiles supported by the NVPTX backend
1440   enum GPUKind {
1441     GK_NONE,
1442     GK_SM20,
1443     GK_SM21,
1444     GK_SM30,
1445     GK_SM35,
1446   } GPU;
1447 
1448   public:
1449     NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1450       BigEndian = false;
1451       TLSSupported = false;
1452       LongWidth = LongAlign = 64;
1453       AddrSpaceMap = &NVPTXAddrSpaceMap;
1454       UseAddrSpaceMapMangling = true;
1455       // Define available target features
1456       // These must be defined in sorted order!
1457       NoAsmVariants = true;
1458       // Set the default GPU to sm20
1459       GPU = GK_SM20;
1460     }
1461     void getTargetDefines(const LangOptions &Opts,
1462                           MacroBuilder &Builder) const override {
1463       Builder.defineMacro("__PTX__");
1464       Builder.defineMacro("__NVPTX__");
1465       if (Opts.CUDAIsDevice) {
1466         // Set __CUDA_ARCH__ for the GPU specified.
1467         std::string CUDAArchCode;
1468         switch (GPU) {
1469         case GK_SM20:
1470           CUDAArchCode = "200";
1471           break;
1472         case GK_SM21:
1473           CUDAArchCode = "210";
1474           break;
1475         case GK_SM30:
1476           CUDAArchCode = "300";
1477           break;
1478         case GK_SM35:
1479           CUDAArchCode = "350";
1480           break;
1481         default:
1482           llvm_unreachable("Unhandled target CPU");
1483         }
1484         Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1485       }
1486     }
1487     void getTargetBuiltins(const Builtin::Info *&Records,
1488                            unsigned &NumRecords) const override {
1489       Records = BuiltinInfo;
1490       NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1491     }
1492     bool hasFeature(StringRef Feature) const override {
1493       return Feature == "ptx" || Feature == "nvptx";
1494     }
1495 
1496     void getGCCRegNames(const char * const *&Names,
1497                         unsigned &NumNames) const override;
1498     void getGCCRegAliases(const GCCRegAlias *&Aliases,
1499                                   unsigned &NumAliases) const override {
1500       // No aliases.
1501       Aliases = nullptr;
1502       NumAliases = 0;
1503     }
1504     bool
1505     validateAsmConstraint(const char *&Name,
1506                           TargetInfo::ConstraintInfo &Info) const override {
1507       switch (*Name) {
1508       default: return false;
1509       case 'c':
1510       case 'h':
1511       case 'r':
1512       case 'l':
1513       case 'f':
1514       case 'd':
1515         Info.setAllowsRegister();
1516         return true;
1517       }
1518     }
1519     const char *getClobbers() const override {
1520       // FIXME: Is this really right?
1521       return "";
1522     }
1523     BuiltinVaListKind getBuiltinVaListKind() const override {
1524       // FIXME: implement
1525       return TargetInfo::CharPtrBuiltinVaList;
1526     }
1527     bool setCPU(const std::string &Name) override {
1528       GPU = llvm::StringSwitch<GPUKind>(Name)
1529                 .Case("sm_20", GK_SM20)
1530                 .Case("sm_21", GK_SM21)
1531                 .Case("sm_30", GK_SM30)
1532                 .Case("sm_35", GK_SM35)
1533                 .Default(GK_NONE);
1534 
1535       return GPU != GK_NONE;
1536     }
1537   };
1538 
1539   const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1540 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1541 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1542                                               ALL_LANGUAGES },
1543 #include "clang/Basic/BuiltinsNVPTX.def"
1544   };
1545 
1546   const char * const NVPTXTargetInfo::GCCRegNames[] = {
1547     "r0"
1548   };
1549 
1550   void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1551                                      unsigned &NumNames) const {
1552     Names = GCCRegNames;
1553     NumNames = llvm::array_lengthof(GCCRegNames);
1554   }
1555 
1556   class NVPTX32TargetInfo : public NVPTXTargetInfo {
1557   public:
1558     NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1559       PointerWidth = PointerAlign = 32;
1560       SizeType     = PtrDiffType = TargetInfo::UnsignedInt;
1561       IntPtrType = TargetInfo::SignedInt;
1562       DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
1563   }
1564   };
1565 
1566   class NVPTX64TargetInfo : public NVPTXTargetInfo {
1567   public:
1568     NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1569       PointerWidth = PointerAlign = 64;
1570       SizeType     = PtrDiffType = TargetInfo::UnsignedLongLong;
1571       IntPtrType = TargetInfo::SignedLongLong;
1572       DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64";
1573   }
1574   };
1575 }
1576 
1577 namespace {
1578 
1579 static const unsigned R600AddrSpaceMap[] = {
1580   1,    // opencl_global
1581   3,    // opencl_local
1582   2,    // opencl_constant
1583   4,    // opencl_generic
1584   1,    // cuda_device
1585   2,    // cuda_constant
1586   3     // cuda_shared
1587 };
1588 
1589 // If you edit the description strings, make sure you update
1590 // getPointerWidthV().
1591 
1592 static const char *DescriptionStringR600 =
1593   "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1594   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1595 
1596 static const char *DescriptionStringR600DoubleOps =
1597   "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1598   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1599 
1600 static const char *DescriptionStringSI =
1601   "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"
1602   "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1603   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1604 
1605 class R600TargetInfo : public TargetInfo {
1606   static const Builtin::Info BuiltinInfo[];
1607 
1608   /// \brief The GPU profiles supported by the R600 target.
1609   enum GPUKind {
1610     GK_NONE,
1611     GK_R600,
1612     GK_R600_DOUBLE_OPS,
1613     GK_R700,
1614     GK_R700_DOUBLE_OPS,
1615     GK_EVERGREEN,
1616     GK_EVERGREEN_DOUBLE_OPS,
1617     GK_NORTHERN_ISLANDS,
1618     GK_CAYMAN,
1619     GK_SOUTHERN_ISLANDS,
1620     GK_SEA_ISLANDS
1621   } GPU;
1622 
1623 public:
1624   R600TargetInfo(const llvm::Triple &Triple)
1625       : TargetInfo(Triple) {
1626 
1627     if (Triple.getArch() == llvm::Triple::amdgcn) {
1628       DescriptionString = DescriptionStringSI;
1629       GPU = GK_SOUTHERN_ISLANDS;
1630     } else {
1631       DescriptionString = DescriptionStringR600;
1632       GPU = GK_R600;
1633     }
1634     AddrSpaceMap = &R600AddrSpaceMap;
1635     UseAddrSpaceMapMangling = true;
1636   }
1637 
1638   uint64_t getPointerWidthV(unsigned AddrSpace) const override {
1639     if (GPU <= GK_CAYMAN)
1640       return 32;
1641 
1642     switch(AddrSpace) {
1643       default:
1644         return 64;
1645       case 0:
1646       case 3:
1647       case 5:
1648         return 32;
1649     }
1650   }
1651 
1652   const char * getClobbers() const override {
1653     return "";
1654   }
1655 
1656   void getGCCRegNames(const char * const *&Names,
1657                       unsigned &numNames) const override {
1658     Names = nullptr;
1659     numNames = 0;
1660   }
1661 
1662   void getGCCRegAliases(const GCCRegAlias *&Aliases,
1663                         unsigned &NumAliases) const override {
1664     Aliases = nullptr;
1665     NumAliases = 0;
1666   }
1667 
1668   bool validateAsmConstraint(const char *&Name,
1669                              TargetInfo::ConstraintInfo &info) const override {
1670     return true;
1671   }
1672 
1673   void getTargetBuiltins(const Builtin::Info *&Records,
1674                          unsigned &NumRecords) const override {
1675     Records = BuiltinInfo;
1676     NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin;
1677   }
1678 
1679   void getTargetDefines(const LangOptions &Opts,
1680                         MacroBuilder &Builder) const override {
1681     Builder.defineMacro("__R600__");
1682     if (GPU >= GK_SOUTHERN_ISLANDS && Opts.OpenCL)
1683       Builder.defineMacro("cl_khr_fp64");
1684   }
1685 
1686   BuiltinVaListKind getBuiltinVaListKind() const override {
1687     return TargetInfo::CharPtrBuiltinVaList;
1688   }
1689 
1690   bool setCPU(const std::string &Name) override {
1691     GPU = llvm::StringSwitch<GPUKind>(Name)
1692       .Case("r600" ,    GK_R600)
1693       .Case("rv610",    GK_R600)
1694       .Case("rv620",    GK_R600)
1695       .Case("rv630",    GK_R600)
1696       .Case("rv635",    GK_R600)
1697       .Case("rs780",    GK_R600)
1698       .Case("rs880",    GK_R600)
1699       .Case("rv670",    GK_R600_DOUBLE_OPS)
1700       .Case("rv710",    GK_R700)
1701       .Case("rv730",    GK_R700)
1702       .Case("rv740",    GK_R700_DOUBLE_OPS)
1703       .Case("rv770",    GK_R700_DOUBLE_OPS)
1704       .Case("palm",     GK_EVERGREEN)
1705       .Case("cedar",    GK_EVERGREEN)
1706       .Case("sumo",     GK_EVERGREEN)
1707       .Case("sumo2",    GK_EVERGREEN)
1708       .Case("redwood",  GK_EVERGREEN)
1709       .Case("juniper",  GK_EVERGREEN)
1710       .Case("hemlock",  GK_EVERGREEN_DOUBLE_OPS)
1711       .Case("cypress",  GK_EVERGREEN_DOUBLE_OPS)
1712       .Case("barts",    GK_NORTHERN_ISLANDS)
1713       .Case("turks",    GK_NORTHERN_ISLANDS)
1714       .Case("caicos",   GK_NORTHERN_ISLANDS)
1715       .Case("cayman",   GK_CAYMAN)
1716       .Case("aruba",    GK_CAYMAN)
1717       .Case("tahiti",   GK_SOUTHERN_ISLANDS)
1718       .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1719       .Case("verde",    GK_SOUTHERN_ISLANDS)
1720       .Case("oland",    GK_SOUTHERN_ISLANDS)
1721       .Case("hainan",   GK_SOUTHERN_ISLANDS)
1722       .Case("bonaire",  GK_SEA_ISLANDS)
1723       .Case("kabini",   GK_SEA_ISLANDS)
1724       .Case("kaveri",   GK_SEA_ISLANDS)
1725       .Case("hawaii",   GK_SEA_ISLANDS)
1726       .Case("mullins",  GK_SEA_ISLANDS)
1727       .Default(GK_NONE);
1728 
1729     if (GPU == GK_NONE) {
1730       return false;
1731     }
1732 
1733     // Set the correct data layout
1734     switch (GPU) {
1735     case GK_NONE:
1736     case GK_R600:
1737     case GK_R700:
1738     case GK_EVERGREEN:
1739     case GK_NORTHERN_ISLANDS:
1740       DescriptionString = DescriptionStringR600;
1741       break;
1742     case GK_R600_DOUBLE_OPS:
1743     case GK_R700_DOUBLE_OPS:
1744     case GK_EVERGREEN_DOUBLE_OPS:
1745     case GK_CAYMAN:
1746       DescriptionString = DescriptionStringR600DoubleOps;
1747       break;
1748     case GK_SOUTHERN_ISLANDS:
1749     case GK_SEA_ISLANDS:
1750       DescriptionString = DescriptionStringSI;
1751       break;
1752     }
1753 
1754     return true;
1755   }
1756 };
1757 
1758 const Builtin::Info R600TargetInfo::BuiltinInfo[] = {
1759 #define BUILTIN(ID, TYPE, ATTRS)                \
1760   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1761 #include "clang/Basic/BuiltinsR600.def"
1762 };
1763 
1764 } // end anonymous namespace
1765 
1766 namespace {
1767 // Namespace for x86 abstract base class
1768 const Builtin::Info BuiltinInfo[] = {
1769 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1770 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1771                                               ALL_LANGUAGES },
1772 #include "clang/Basic/BuiltinsX86.def"
1773 };
1774 
1775 static const char* const GCCRegNames[] = {
1776   "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1777   "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1778   "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1779   "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1780   "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1781   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1782   "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1783   "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1784   "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1785 };
1786 
1787 const TargetInfo::AddlRegName AddlRegNames[] = {
1788   { { "al", "ah", "eax", "rax" }, 0 },
1789   { { "bl", "bh", "ebx", "rbx" }, 3 },
1790   { { "cl", "ch", "ecx", "rcx" }, 2 },
1791   { { "dl", "dh", "edx", "rdx" }, 1 },
1792   { { "esi", "rsi" }, 4 },
1793   { { "edi", "rdi" }, 5 },
1794   { { "esp", "rsp" }, 7 },
1795   { { "ebp", "rbp" }, 6 },
1796 };
1797 
1798 // X86 target abstract base class; x86-32 and x86-64 are very close, so
1799 // most of the implementation can be shared.
1800 class X86TargetInfo : public TargetInfo {
1801   enum X86SSEEnum {
1802     NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
1803   } SSELevel;
1804   enum MMX3DNowEnum {
1805     NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1806   } MMX3DNowLevel;
1807   enum XOPEnum {
1808     NoXOP,
1809     SSE4A,
1810     FMA4,
1811     XOP
1812   } XOPLevel;
1813 
1814   bool HasAES;
1815   bool HasPCLMUL;
1816   bool HasLZCNT;
1817   bool HasRDRND;
1818   bool HasFSGSBASE;
1819   bool HasBMI;
1820   bool HasBMI2;
1821   bool HasPOPCNT;
1822   bool HasRTM;
1823   bool HasPRFCHW;
1824   bool HasRDSEED;
1825   bool HasADX;
1826   bool HasTBM;
1827   bool HasFMA;
1828   bool HasF16C;
1829   bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW,
1830       HasAVX512VL;
1831   bool HasSHA;
1832   bool HasCX16;
1833 
1834   /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1835   ///
1836   /// Each enumeration represents a particular CPU supported by Clang. These
1837   /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1838   enum CPUKind {
1839     CK_Generic,
1840 
1841     /// \name i386
1842     /// i386-generation processors.
1843     //@{
1844     CK_i386,
1845     //@}
1846 
1847     /// \name i486
1848     /// i486-generation processors.
1849     //@{
1850     CK_i486,
1851     CK_WinChipC6,
1852     CK_WinChip2,
1853     CK_C3,
1854     //@}
1855 
1856     /// \name i586
1857     /// i586-generation processors, P5 microarchitecture based.
1858     //@{
1859     CK_i586,
1860     CK_Pentium,
1861     CK_PentiumMMX,
1862     //@}
1863 
1864     /// \name i686
1865     /// i686-generation processors, P6 / Pentium M microarchitecture based.
1866     //@{
1867     CK_i686,
1868     CK_PentiumPro,
1869     CK_Pentium2,
1870     CK_Pentium3,
1871     CK_Pentium3M,
1872     CK_PentiumM,
1873     CK_C3_2,
1874 
1875     /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1876     /// Clang however has some logic to suport this.
1877     // FIXME: Warn, deprecate, and potentially remove this.
1878     CK_Yonah,
1879     //@}
1880 
1881     /// \name Netburst
1882     /// Netburst microarchitecture based processors.
1883     //@{
1884     CK_Pentium4,
1885     CK_Pentium4M,
1886     CK_Prescott,
1887     CK_Nocona,
1888     //@}
1889 
1890     /// \name Core
1891     /// Core microarchitecture based processors.
1892     //@{
1893     CK_Core2,
1894 
1895     /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1896     /// codename which GCC no longer accepts as an option to -march, but Clang
1897     /// has some logic for recognizing it.
1898     // FIXME: Warn, deprecate, and potentially remove this.
1899     CK_Penryn,
1900     //@}
1901 
1902     /// \name Atom
1903     /// Atom processors
1904     //@{
1905     CK_Bonnell,
1906     CK_Silvermont,
1907     //@}
1908 
1909     /// \name Nehalem
1910     /// Nehalem microarchitecture based processors.
1911     CK_Nehalem,
1912 
1913     /// \name Westmere
1914     /// Westmere microarchitecture based processors.
1915     CK_Westmere,
1916 
1917     /// \name Sandy Bridge
1918     /// Sandy Bridge microarchitecture based processors.
1919     CK_SandyBridge,
1920 
1921     /// \name Ivy Bridge
1922     /// Ivy Bridge microarchitecture based processors.
1923     CK_IvyBridge,
1924 
1925     /// \name Haswell
1926     /// Haswell microarchitecture based processors.
1927     CK_Haswell,
1928 
1929     /// \name Broadwell
1930     /// Broadwell microarchitecture based processors.
1931     CK_Broadwell,
1932 
1933     /// \name Skylake
1934     /// Skylake microarchitecture based processors.
1935     CK_Skylake,
1936 
1937     /// \name Knights Landing
1938     /// Knights Landing processor.
1939     CK_KNL,
1940 
1941     /// \name K6
1942     /// K6 architecture processors.
1943     //@{
1944     CK_K6,
1945     CK_K6_2,
1946     CK_K6_3,
1947     //@}
1948 
1949     /// \name K7
1950     /// K7 architecture processors.
1951     //@{
1952     CK_Athlon,
1953     CK_AthlonThunderbird,
1954     CK_Athlon4,
1955     CK_AthlonXP,
1956     CK_AthlonMP,
1957     //@}
1958 
1959     /// \name K8
1960     /// K8 architecture processors.
1961     //@{
1962     CK_Athlon64,
1963     CK_Athlon64SSE3,
1964     CK_AthlonFX,
1965     CK_K8,
1966     CK_K8SSE3,
1967     CK_Opteron,
1968     CK_OpteronSSE3,
1969     CK_AMDFAM10,
1970     //@}
1971 
1972     /// \name Bobcat
1973     /// Bobcat architecture processors.
1974     //@{
1975     CK_BTVER1,
1976     CK_BTVER2,
1977     //@}
1978 
1979     /// \name Bulldozer
1980     /// Bulldozer architecture processors.
1981     //@{
1982     CK_BDVER1,
1983     CK_BDVER2,
1984     CK_BDVER3,
1985     CK_BDVER4,
1986     //@}
1987 
1988     /// This specification is deprecated and will be removed in the future.
1989     /// Users should prefer \see CK_K8.
1990     // FIXME: Warn on this when the CPU is set to it.
1991     //@{
1992     CK_x86_64,
1993     //@}
1994 
1995     /// \name Geode
1996     /// Geode processors.
1997     //@{
1998     CK_Geode
1999     //@}
2000   } CPU;
2001 
2002   enum FPMathKind {
2003     FP_Default,
2004     FP_SSE,
2005     FP_387
2006   } FPMath;
2007 
2008 public:
2009   X86TargetInfo(const llvm::Triple &Triple)
2010       : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
2011         XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
2012         HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false),
2013         HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false),
2014         HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false),
2015         HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false),
2016         HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false),
2017         HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) {
2018     BigEndian = false;
2019     LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
2020   }
2021   unsigned getFloatEvalMethod() const override {
2022     // X87 evaluates with 80 bits "long double" precision.
2023     return SSELevel == NoSSE ? 2 : 0;
2024   }
2025   void getTargetBuiltins(const Builtin::Info *&Records,
2026                                  unsigned &NumRecords) const override {
2027     Records = BuiltinInfo;
2028     NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
2029   }
2030   void getGCCRegNames(const char * const *&Names,
2031                       unsigned &NumNames) const override {
2032     Names = GCCRegNames;
2033     NumNames = llvm::array_lengthof(GCCRegNames);
2034   }
2035   void getGCCRegAliases(const GCCRegAlias *&Aliases,
2036                         unsigned &NumAliases) const override {
2037     Aliases = nullptr;
2038     NumAliases = 0;
2039   }
2040   void getGCCAddlRegNames(const AddlRegName *&Names,
2041                           unsigned &NumNames) const override {
2042     Names = AddlRegNames;
2043     NumNames = llvm::array_lengthof(AddlRegNames);
2044   }
2045   bool validateAsmConstraint(const char *&Name,
2046                              TargetInfo::ConstraintInfo &info) const override;
2047 
2048   bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
2049 
2050   bool validateInputSize(StringRef Constraint, unsigned Size) const override;
2051 
2052   virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
2053 
2054   std::string convertConstraint(const char *&Constraint) const override;
2055   const char *getClobbers() const override {
2056     return "~{dirflag},~{fpsr},~{flags}";
2057   }
2058   void getTargetDefines(const LangOptions &Opts,
2059                         MacroBuilder &Builder) const override;
2060   static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
2061                           bool Enabled);
2062   static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
2063                           bool Enabled);
2064   static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2065                           bool Enabled);
2066   void setFeatureEnabled(llvm::StringMap<bool> &Features,
2067                          StringRef Name, bool Enabled) const override {
2068     setFeatureEnabledImpl(Features, Name, Enabled);
2069   }
2070   // This exists purely to cut down on the number of virtual calls in
2071   // getDefaultFeatures which calls this repeatedly.
2072   static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2073                                     StringRef Name, bool Enabled);
2074   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
2075   bool hasFeature(StringRef Feature) const override;
2076   bool handleTargetFeatures(std::vector<std::string> &Features,
2077                             DiagnosticsEngine &Diags) override;
2078   StringRef getABI() const override {
2079     if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
2080       return "avx";
2081     else if (getTriple().getArch() == llvm::Triple::x86 &&
2082              MMX3DNowLevel == NoMMX3DNow)
2083       return "no-mmx";
2084     return "";
2085   }
2086   bool setCPU(const std::string &Name) override {
2087     CPU = llvm::StringSwitch<CPUKind>(Name)
2088       .Case("i386", CK_i386)
2089       .Case("i486", CK_i486)
2090       .Case("winchip-c6", CK_WinChipC6)
2091       .Case("winchip2", CK_WinChip2)
2092       .Case("c3", CK_C3)
2093       .Case("i586", CK_i586)
2094       .Case("pentium", CK_Pentium)
2095       .Case("pentium-mmx", CK_PentiumMMX)
2096       .Case("i686", CK_i686)
2097       .Case("pentiumpro", CK_PentiumPro)
2098       .Case("pentium2", CK_Pentium2)
2099       .Case("pentium3", CK_Pentium3)
2100       .Case("pentium3m", CK_Pentium3M)
2101       .Case("pentium-m", CK_PentiumM)
2102       .Case("c3-2", CK_C3_2)
2103       .Case("yonah", CK_Yonah)
2104       .Case("pentium4", CK_Pentium4)
2105       .Case("pentium4m", CK_Pentium4M)
2106       .Case("prescott", CK_Prescott)
2107       .Case("nocona", CK_Nocona)
2108       .Case("core2", CK_Core2)
2109       .Case("penryn", CK_Penryn)
2110       .Case("bonnell", CK_Bonnell)
2111       .Case("atom", CK_Bonnell) // Legacy name.
2112       .Case("silvermont", CK_Silvermont)
2113       .Case("slm", CK_Silvermont) // Legacy name.
2114       .Case("nehalem", CK_Nehalem)
2115       .Case("corei7", CK_Nehalem) // Legacy name.
2116       .Case("westmere", CK_Westmere)
2117       .Case("sandybridge", CK_SandyBridge)
2118       .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2119       .Case("ivybridge", CK_IvyBridge)
2120       .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2121       .Case("haswell", CK_Haswell)
2122       .Case("core-avx2", CK_Haswell) // Legacy name.
2123       .Case("broadwell", CK_Broadwell)
2124       .Case("skylake", CK_Skylake)
2125       .Case("skx", CK_Skylake) // Legacy name.
2126       .Case("knl", CK_KNL)
2127       .Case("k6", CK_K6)
2128       .Case("k6-2", CK_K6_2)
2129       .Case("k6-3", CK_K6_3)
2130       .Case("athlon", CK_Athlon)
2131       .Case("athlon-tbird", CK_AthlonThunderbird)
2132       .Case("athlon-4", CK_Athlon4)
2133       .Case("athlon-xp", CK_AthlonXP)
2134       .Case("athlon-mp", CK_AthlonMP)
2135       .Case("athlon64", CK_Athlon64)
2136       .Case("athlon64-sse3", CK_Athlon64SSE3)
2137       .Case("athlon-fx", CK_AthlonFX)
2138       .Case("k8", CK_K8)
2139       .Case("k8-sse3", CK_K8SSE3)
2140       .Case("opteron", CK_Opteron)
2141       .Case("opteron-sse3", CK_OpteronSSE3)
2142       .Case("barcelona", CK_AMDFAM10)
2143       .Case("amdfam10", CK_AMDFAM10)
2144       .Case("btver1", CK_BTVER1)
2145       .Case("btver2", CK_BTVER2)
2146       .Case("bdver1", CK_BDVER1)
2147       .Case("bdver2", CK_BDVER2)
2148       .Case("bdver3", CK_BDVER3)
2149       .Case("bdver4", CK_BDVER4)
2150       .Case("x86-64", CK_x86_64)
2151       .Case("geode", CK_Geode)
2152       .Default(CK_Generic);
2153 
2154     // Perform any per-CPU checks necessary to determine if this CPU is
2155     // acceptable.
2156     // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2157     // invalid without explaining *why*.
2158     switch (CPU) {
2159     case CK_Generic:
2160       // No processor selected!
2161       return false;
2162 
2163     case CK_i386:
2164     case CK_i486:
2165     case CK_WinChipC6:
2166     case CK_WinChip2:
2167     case CK_C3:
2168     case CK_i586:
2169     case CK_Pentium:
2170     case CK_PentiumMMX:
2171     case CK_i686:
2172     case CK_PentiumPro:
2173     case CK_Pentium2:
2174     case CK_Pentium3:
2175     case CK_Pentium3M:
2176     case CK_PentiumM:
2177     case CK_Yonah:
2178     case CK_C3_2:
2179     case CK_Pentium4:
2180     case CK_Pentium4M:
2181     case CK_Prescott:
2182     case CK_K6:
2183     case CK_K6_2:
2184     case CK_K6_3:
2185     case CK_Athlon:
2186     case CK_AthlonThunderbird:
2187     case CK_Athlon4:
2188     case CK_AthlonXP:
2189     case CK_AthlonMP:
2190     case CK_Geode:
2191       // Only accept certain architectures when compiling in 32-bit mode.
2192       if (getTriple().getArch() != llvm::Triple::x86)
2193         return false;
2194 
2195       // Fallthrough
2196     case CK_Nocona:
2197     case CK_Core2:
2198     case CK_Penryn:
2199     case CK_Bonnell:
2200     case CK_Silvermont:
2201     case CK_Nehalem:
2202     case CK_Westmere:
2203     case CK_SandyBridge:
2204     case CK_IvyBridge:
2205     case CK_Haswell:
2206     case CK_Broadwell:
2207     case CK_Skylake:
2208     case CK_KNL:
2209     case CK_Athlon64:
2210     case CK_Athlon64SSE3:
2211     case CK_AthlonFX:
2212     case CK_K8:
2213     case CK_K8SSE3:
2214     case CK_Opteron:
2215     case CK_OpteronSSE3:
2216     case CK_AMDFAM10:
2217     case CK_BTVER1:
2218     case CK_BTVER2:
2219     case CK_BDVER1:
2220     case CK_BDVER2:
2221     case CK_BDVER3:
2222     case CK_BDVER4:
2223     case CK_x86_64:
2224       return true;
2225     }
2226     llvm_unreachable("Unhandled CPU kind");
2227   }
2228 
2229   bool setFPMath(StringRef Name) override;
2230 
2231   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2232     // We accept all non-ARM calling conventions
2233     return (CC == CC_X86ThisCall ||
2234             CC == CC_X86FastCall ||
2235             CC == CC_X86StdCall ||
2236             CC == CC_X86VectorCall ||
2237             CC == CC_C ||
2238             CC == CC_X86Pascal ||
2239             CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2240   }
2241 
2242   CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2243     return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2244   }
2245 };
2246 
2247 bool X86TargetInfo::setFPMath(StringRef Name) {
2248   if (Name == "387") {
2249     FPMath = FP_387;
2250     return true;
2251   }
2252   if (Name == "sse") {
2253     FPMath = FP_SSE;
2254     return true;
2255   }
2256   return false;
2257 }
2258 
2259 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2260   // FIXME: This *really* should not be here.
2261 
2262   // X86_64 always has SSE2.
2263   if (getTriple().getArch() == llvm::Triple::x86_64)
2264     setFeatureEnabledImpl(Features, "sse2", true);
2265 
2266   switch (CPU) {
2267   case CK_Generic:
2268   case CK_i386:
2269   case CK_i486:
2270   case CK_i586:
2271   case CK_Pentium:
2272   case CK_i686:
2273   case CK_PentiumPro:
2274     break;
2275   case CK_PentiumMMX:
2276   case CK_Pentium2:
2277   case CK_K6:
2278   case CK_WinChipC6:
2279     setFeatureEnabledImpl(Features, "mmx", true);
2280     break;
2281   case CK_Pentium3:
2282   case CK_Pentium3M:
2283   case CK_C3_2:
2284     setFeatureEnabledImpl(Features, "sse", true);
2285     break;
2286   case CK_PentiumM:
2287   case CK_Pentium4:
2288   case CK_Pentium4M:
2289   case CK_x86_64:
2290     setFeatureEnabledImpl(Features, "sse2", true);
2291     break;
2292   case CK_Yonah:
2293   case CK_Prescott:
2294   case CK_Nocona:
2295     setFeatureEnabledImpl(Features, "sse3", true);
2296     setFeatureEnabledImpl(Features, "cx16", true);
2297     break;
2298   case CK_Core2:
2299   case CK_Bonnell:
2300     setFeatureEnabledImpl(Features, "ssse3", true);
2301     setFeatureEnabledImpl(Features, "cx16", true);
2302     break;
2303   case CK_Penryn:
2304     setFeatureEnabledImpl(Features, "sse4.1", true);
2305     setFeatureEnabledImpl(Features, "cx16", true);
2306     break;
2307   case CK_Skylake:
2308     setFeatureEnabledImpl(Features, "avx512f", true);
2309     setFeatureEnabledImpl(Features, "avx512cd", true);
2310     setFeatureEnabledImpl(Features, "avx512dq", true);
2311     setFeatureEnabledImpl(Features, "avx512bw", true);
2312     setFeatureEnabledImpl(Features, "avx512vl", true);
2313     // FALLTHROUGH
2314   case CK_Broadwell:
2315     setFeatureEnabledImpl(Features, "rdseed", true);
2316     setFeatureEnabledImpl(Features, "adx", true);
2317     // FALLTHROUGH
2318   case CK_Haswell:
2319     setFeatureEnabledImpl(Features, "avx2", true);
2320     setFeatureEnabledImpl(Features, "lzcnt", true);
2321     setFeatureEnabledImpl(Features, "bmi", true);
2322     setFeatureEnabledImpl(Features, "bmi2", true);
2323     setFeatureEnabledImpl(Features, "rtm", true);
2324     setFeatureEnabledImpl(Features, "fma", true);
2325     // FALLTHROUGH
2326   case CK_IvyBridge:
2327     setFeatureEnabledImpl(Features, "rdrnd", true);
2328     setFeatureEnabledImpl(Features, "f16c", true);
2329     setFeatureEnabledImpl(Features, "fsgsbase", true);
2330     // FALLTHROUGH
2331   case CK_SandyBridge:
2332     setFeatureEnabledImpl(Features, "avx", true);
2333     // FALLTHROUGH
2334   case CK_Westmere:
2335   case CK_Silvermont:
2336     setFeatureEnabledImpl(Features, "aes", true);
2337     setFeatureEnabledImpl(Features, "pclmul", true);
2338     // FALLTHROUGH
2339   case CK_Nehalem:
2340     setFeatureEnabledImpl(Features, "sse4.2", true);
2341     setFeatureEnabledImpl(Features, "cx16", true);
2342     break;
2343   case CK_KNL:
2344     setFeatureEnabledImpl(Features, "avx512f", true);
2345     setFeatureEnabledImpl(Features, "avx512cd", true);
2346     setFeatureEnabledImpl(Features, "avx512er", true);
2347     setFeatureEnabledImpl(Features, "avx512pf", true);
2348     setFeatureEnabledImpl(Features, "rdseed", true);
2349     setFeatureEnabledImpl(Features, "adx", true);
2350     setFeatureEnabledImpl(Features, "lzcnt", true);
2351     setFeatureEnabledImpl(Features, "bmi", true);
2352     setFeatureEnabledImpl(Features, "bmi2", true);
2353     setFeatureEnabledImpl(Features, "rtm", true);
2354     setFeatureEnabledImpl(Features, "fma", true);
2355     setFeatureEnabledImpl(Features, "rdrnd", true);
2356     setFeatureEnabledImpl(Features, "f16c", true);
2357     setFeatureEnabledImpl(Features, "fsgsbase", true);
2358     setFeatureEnabledImpl(Features, "aes", true);
2359     setFeatureEnabledImpl(Features, "pclmul", true);
2360     setFeatureEnabledImpl(Features, "cx16", true);
2361     break;
2362   case CK_K6_2:
2363   case CK_K6_3:
2364   case CK_WinChip2:
2365   case CK_C3:
2366     setFeatureEnabledImpl(Features, "3dnow", true);
2367     break;
2368   case CK_Athlon:
2369   case CK_AthlonThunderbird:
2370   case CK_Geode:
2371     setFeatureEnabledImpl(Features, "3dnowa", true);
2372     break;
2373   case CK_Athlon4:
2374   case CK_AthlonXP:
2375   case CK_AthlonMP:
2376     setFeatureEnabledImpl(Features, "sse", true);
2377     setFeatureEnabledImpl(Features, "3dnowa", true);
2378     break;
2379   case CK_K8:
2380   case CK_Opteron:
2381   case CK_Athlon64:
2382   case CK_AthlonFX:
2383     setFeatureEnabledImpl(Features, "sse2", true);
2384     setFeatureEnabledImpl(Features, "3dnowa", true);
2385     break;
2386   case CK_AMDFAM10:
2387     setFeatureEnabledImpl(Features, "sse4a", true);
2388     setFeatureEnabledImpl(Features, "lzcnt", true);
2389     setFeatureEnabledImpl(Features, "popcnt", true);
2390     // FALLTHROUGH
2391   case CK_K8SSE3:
2392   case CK_OpteronSSE3:
2393   case CK_Athlon64SSE3:
2394     setFeatureEnabledImpl(Features, "sse3", true);
2395     setFeatureEnabledImpl(Features, "3dnowa", true);
2396     break;
2397   case CK_BTVER2:
2398     setFeatureEnabledImpl(Features, "avx", true);
2399     setFeatureEnabledImpl(Features, "aes", true);
2400     setFeatureEnabledImpl(Features, "pclmul", true);
2401     setFeatureEnabledImpl(Features, "bmi", true);
2402     setFeatureEnabledImpl(Features, "f16c", true);
2403     // FALLTHROUGH
2404   case CK_BTVER1:
2405     setFeatureEnabledImpl(Features, "ssse3", true);
2406     setFeatureEnabledImpl(Features, "sse4a", true);
2407     setFeatureEnabledImpl(Features, "lzcnt", true);
2408     setFeatureEnabledImpl(Features, "popcnt", true);
2409     setFeatureEnabledImpl(Features, "prfchw", true);
2410     setFeatureEnabledImpl(Features, "cx16", true);
2411     break;
2412   case CK_BDVER4:
2413     setFeatureEnabledImpl(Features, "avx2", true);
2414     setFeatureEnabledImpl(Features, "bmi2", true);
2415     // FALLTHROUGH
2416   case CK_BDVER3:
2417     setFeatureEnabledImpl(Features, "fsgsbase", true);
2418     // FALLTHROUGH
2419   case CK_BDVER2:
2420     setFeatureEnabledImpl(Features, "bmi", true);
2421     setFeatureEnabledImpl(Features, "fma", true);
2422     setFeatureEnabledImpl(Features, "f16c", true);
2423     setFeatureEnabledImpl(Features, "tbm", true);
2424     // FALLTHROUGH
2425   case CK_BDVER1:
2426     // xop implies avx, sse4a and fma4.
2427     setFeatureEnabledImpl(Features, "xop", true);
2428     setFeatureEnabledImpl(Features, "lzcnt", true);
2429     setFeatureEnabledImpl(Features, "aes", true);
2430     setFeatureEnabledImpl(Features, "pclmul", true);
2431     setFeatureEnabledImpl(Features, "prfchw", true);
2432     setFeatureEnabledImpl(Features, "cx16", true);
2433     break;
2434   }
2435 }
2436 
2437 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2438                                 X86SSEEnum Level, bool Enabled) {
2439   if (Enabled) {
2440     switch (Level) {
2441     case AVX512F:
2442       Features["avx512f"] = true;
2443     case AVX2:
2444       Features["avx2"] = true;
2445     case AVX:
2446       Features["avx"] = true;
2447     case SSE42:
2448       Features["sse4.2"] = true;
2449     case SSE41:
2450       Features["sse4.1"] = true;
2451     case SSSE3:
2452       Features["ssse3"] = true;
2453     case SSE3:
2454       Features["sse3"] = true;
2455     case SSE2:
2456       Features["sse2"] = true;
2457     case SSE1:
2458       Features["sse"] = true;
2459     case NoSSE:
2460       break;
2461     }
2462     return;
2463   }
2464 
2465   switch (Level) {
2466   case NoSSE:
2467   case SSE1:
2468     Features["sse"] = false;
2469   case SSE2:
2470     Features["sse2"] = Features["pclmul"] = Features["aes"] =
2471       Features["sha"] = false;
2472   case SSE3:
2473     Features["sse3"] = false;
2474     setXOPLevel(Features, NoXOP, false);
2475   case SSSE3:
2476     Features["ssse3"] = false;
2477   case SSE41:
2478     Features["sse4.1"] = false;
2479   case SSE42:
2480     Features["sse4.2"] = false;
2481   case AVX:
2482     Features["fma"] = Features["avx"] = Features["f16c"] = false;
2483     setXOPLevel(Features, FMA4, false);
2484   case AVX2:
2485     Features["avx2"] = false;
2486   case AVX512F:
2487     Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
2488       Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
2489       Features["avx512vl"] = false;
2490   }
2491 }
2492 
2493 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2494                                 MMX3DNowEnum Level, bool Enabled) {
2495   if (Enabled) {
2496     switch (Level) {
2497     case AMD3DNowAthlon:
2498       Features["3dnowa"] = true;
2499     case AMD3DNow:
2500       Features["3dnow"] = true;
2501     case MMX:
2502       Features["mmx"] = true;
2503     case NoMMX3DNow:
2504       break;
2505     }
2506     return;
2507   }
2508 
2509   switch (Level) {
2510   case NoMMX3DNow:
2511   case MMX:
2512     Features["mmx"] = false;
2513   case AMD3DNow:
2514     Features["3dnow"] = false;
2515   case AMD3DNowAthlon:
2516     Features["3dnowa"] = false;
2517   }
2518 }
2519 
2520 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2521                                 bool Enabled) {
2522   if (Enabled) {
2523     switch (Level) {
2524     case XOP:
2525       Features["xop"] = true;
2526     case FMA4:
2527       Features["fma4"] = true;
2528       setSSELevel(Features, AVX, true);
2529     case SSE4A:
2530       Features["sse4a"] = true;
2531       setSSELevel(Features, SSE3, true);
2532     case NoXOP:
2533       break;
2534     }
2535     return;
2536   }
2537 
2538   switch (Level) {
2539   case NoXOP:
2540   case SSE4A:
2541     Features["sse4a"] = false;
2542   case FMA4:
2543     Features["fma4"] = false;
2544   case XOP:
2545     Features["xop"] = false;
2546   }
2547 }
2548 
2549 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2550                                           StringRef Name, bool Enabled) {
2551   // FIXME: This *really* should not be here.  We need some way of translating
2552   // options into llvm subtarget features.
2553   if (Name == "sse4")
2554     Name = "sse4.2";
2555 
2556   Features[Name] = Enabled;
2557 
2558   if (Name == "mmx") {
2559     setMMXLevel(Features, MMX, Enabled);
2560   } else if (Name == "sse") {
2561     setSSELevel(Features, SSE1, Enabled);
2562   } else if (Name == "sse2") {
2563     setSSELevel(Features, SSE2, Enabled);
2564   } else if (Name == "sse3") {
2565     setSSELevel(Features, SSE3, Enabled);
2566   } else if (Name == "ssse3") {
2567     setSSELevel(Features, SSSE3, Enabled);
2568   } else if (Name == "sse4.2") {
2569     setSSELevel(Features, SSE42, Enabled);
2570   } else if (Name == "sse4.1") {
2571     setSSELevel(Features, SSE41, Enabled);
2572   } else if (Name == "3dnow") {
2573     setMMXLevel(Features, AMD3DNow, Enabled);
2574   } else if (Name == "3dnowa") {
2575     setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2576   } else if (Name == "aes") {
2577     if (Enabled)
2578       setSSELevel(Features, SSE2, Enabled);
2579   } else if (Name == "pclmul") {
2580     if (Enabled)
2581       setSSELevel(Features, SSE2, Enabled);
2582   } else if (Name == "avx") {
2583     setSSELevel(Features, AVX, Enabled);
2584   } else if (Name == "avx2") {
2585     setSSELevel(Features, AVX2, Enabled);
2586   } else if (Name == "avx512f") {
2587     setSSELevel(Features, AVX512F, Enabled);
2588   } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf"
2589           || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") {
2590     if (Enabled)
2591       setSSELevel(Features, AVX512F, Enabled);
2592   } else if (Name == "fma") {
2593     if (Enabled)
2594       setSSELevel(Features, AVX, Enabled);
2595   } else if (Name == "fma4") {
2596     setXOPLevel(Features, FMA4, Enabled);
2597   } else if (Name == "xop") {
2598     setXOPLevel(Features, XOP, Enabled);
2599   } else if (Name == "sse4a") {
2600     setXOPLevel(Features, SSE4A, Enabled);
2601   } else if (Name == "f16c") {
2602     if (Enabled)
2603       setSSELevel(Features, AVX, Enabled);
2604   } else if (Name == "sha") {
2605     if (Enabled)
2606       setSSELevel(Features, SSE2, Enabled);
2607   }
2608 }
2609 
2610 /// handleTargetFeatures - Perform initialization based on the user
2611 /// configured set of features.
2612 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2613                                          DiagnosticsEngine &Diags) {
2614   // Remember the maximum enabled sselevel.
2615   for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2616     // Ignore disabled features.
2617     if (Features[i][0] == '-')
2618       continue;
2619 
2620     StringRef Feature = StringRef(Features[i]).substr(1);
2621 
2622     if (Feature == "aes") {
2623       HasAES = true;
2624       continue;
2625     }
2626 
2627     if (Feature == "pclmul") {
2628       HasPCLMUL = true;
2629       continue;
2630     }
2631 
2632     if (Feature == "lzcnt") {
2633       HasLZCNT = true;
2634       continue;
2635     }
2636 
2637     if (Feature == "rdrnd") {
2638       HasRDRND = true;
2639       continue;
2640     }
2641 
2642     if (Feature == "fsgsbase") {
2643       HasFSGSBASE = true;
2644       continue;
2645     }
2646 
2647     if (Feature == "bmi") {
2648       HasBMI = true;
2649       continue;
2650     }
2651 
2652     if (Feature == "bmi2") {
2653       HasBMI2 = true;
2654       continue;
2655     }
2656 
2657     if (Feature == "popcnt") {
2658       HasPOPCNT = true;
2659       continue;
2660     }
2661 
2662     if (Feature == "rtm") {
2663       HasRTM = true;
2664       continue;
2665     }
2666 
2667     if (Feature == "prfchw") {
2668       HasPRFCHW = true;
2669       continue;
2670     }
2671 
2672     if (Feature == "rdseed") {
2673       HasRDSEED = true;
2674       continue;
2675     }
2676 
2677     if (Feature == "adx") {
2678       HasADX = true;
2679       continue;
2680     }
2681 
2682     if (Feature == "tbm") {
2683       HasTBM = true;
2684       continue;
2685     }
2686 
2687     if (Feature == "fma") {
2688       HasFMA = true;
2689       continue;
2690     }
2691 
2692     if (Feature == "f16c") {
2693       HasF16C = true;
2694       continue;
2695     }
2696 
2697     if (Feature == "avx512cd") {
2698       HasAVX512CD = true;
2699       continue;
2700     }
2701 
2702     if (Feature == "avx512er") {
2703       HasAVX512ER = true;
2704       continue;
2705     }
2706 
2707     if (Feature == "avx512pf") {
2708       HasAVX512PF = true;
2709       continue;
2710     }
2711 
2712     if (Feature == "avx512dq") {
2713       HasAVX512DQ = true;
2714       continue;
2715     }
2716 
2717     if (Feature == "avx512bw") {
2718       HasAVX512BW = true;
2719       continue;
2720     }
2721 
2722     if (Feature == "avx512vl") {
2723       HasAVX512VL = true;
2724       continue;
2725     }
2726 
2727     if (Feature == "sha") {
2728       HasSHA = true;
2729       continue;
2730     }
2731 
2732     if (Feature == "cx16") {
2733       HasCX16 = true;
2734       continue;
2735     }
2736 
2737     assert(Features[i][0] == '+' && "Invalid target feature!");
2738     X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2739       .Case("avx512f", AVX512F)
2740       .Case("avx2", AVX2)
2741       .Case("avx", AVX)
2742       .Case("sse4.2", SSE42)
2743       .Case("sse4.1", SSE41)
2744       .Case("ssse3", SSSE3)
2745       .Case("sse3", SSE3)
2746       .Case("sse2", SSE2)
2747       .Case("sse", SSE1)
2748       .Default(NoSSE);
2749     SSELevel = std::max(SSELevel, Level);
2750 
2751     MMX3DNowEnum ThreeDNowLevel =
2752       llvm::StringSwitch<MMX3DNowEnum>(Feature)
2753         .Case("3dnowa", AMD3DNowAthlon)
2754         .Case("3dnow", AMD3DNow)
2755         .Case("mmx", MMX)
2756         .Default(NoMMX3DNow);
2757     MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2758 
2759     XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
2760         .Case("xop", XOP)
2761         .Case("fma4", FMA4)
2762         .Case("sse4a", SSE4A)
2763         .Default(NoXOP);
2764     XOPLevel = std::max(XOPLevel, XLevel);
2765   }
2766 
2767   // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2768   // Can't do this earlier because we need to be able to explicitly enable
2769   // popcnt and still disable sse4.2.
2770   if (!HasPOPCNT && SSELevel >= SSE42 &&
2771       std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){
2772     HasPOPCNT = true;
2773     Features.push_back("+popcnt");
2774   }
2775 
2776   // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
2777   if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow &&
2778       std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){
2779     HasPRFCHW = true;
2780     Features.push_back("+prfchw");
2781   }
2782 
2783   // LLVM doesn't have a separate switch for fpmath, so only accept it if it
2784   // matches the selected sse level.
2785   if (FPMath == FP_SSE && SSELevel < SSE1) {
2786     Diags.Report(diag::err_target_unsupported_fpmath) << "sse";
2787     return false;
2788   } else if (FPMath == FP_387 && SSELevel >= SSE1) {
2789     Diags.Report(diag::err_target_unsupported_fpmath) << "387";
2790     return false;
2791   }
2792 
2793   // Don't tell the backend if we're turning off mmx; it will end up disabling
2794   // SSE, which we don't want.
2795   // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2796   // then enable MMX.
2797   std::vector<std::string>::iterator it;
2798   it = std::find(Features.begin(), Features.end(), "-mmx");
2799   if (it != Features.end())
2800     Features.erase(it);
2801   else if (SSELevel > NoSSE)
2802     MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
2803   return true;
2804 }
2805 
2806 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2807 /// definitions for this particular subtarget.
2808 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2809                                      MacroBuilder &Builder) const {
2810   // Target identification.
2811   if (getTriple().getArch() == llvm::Triple::x86_64) {
2812     Builder.defineMacro("__amd64__");
2813     Builder.defineMacro("__amd64");
2814     Builder.defineMacro("__x86_64");
2815     Builder.defineMacro("__x86_64__");
2816     if (getTriple().getArchName() == "x86_64h") {
2817       Builder.defineMacro("__x86_64h");
2818       Builder.defineMacro("__x86_64h__");
2819     }
2820   } else {
2821     DefineStd(Builder, "i386", Opts);
2822   }
2823 
2824   // Subtarget options.
2825   // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2826   // truly should be based on -mtune options.
2827   switch (CPU) {
2828   case CK_Generic:
2829     break;
2830   case CK_i386:
2831     // The rest are coming from the i386 define above.
2832     Builder.defineMacro("__tune_i386__");
2833     break;
2834   case CK_i486:
2835   case CK_WinChipC6:
2836   case CK_WinChip2:
2837   case CK_C3:
2838     defineCPUMacros(Builder, "i486");
2839     break;
2840   case CK_PentiumMMX:
2841     Builder.defineMacro("__pentium_mmx__");
2842     Builder.defineMacro("__tune_pentium_mmx__");
2843     // Fallthrough
2844   case CK_i586:
2845   case CK_Pentium:
2846     defineCPUMacros(Builder, "i586");
2847     defineCPUMacros(Builder, "pentium");
2848     break;
2849   case CK_Pentium3:
2850   case CK_Pentium3M:
2851   case CK_PentiumM:
2852     Builder.defineMacro("__tune_pentium3__");
2853     // Fallthrough
2854   case CK_Pentium2:
2855   case CK_C3_2:
2856     Builder.defineMacro("__tune_pentium2__");
2857     // Fallthrough
2858   case CK_PentiumPro:
2859     Builder.defineMacro("__tune_i686__");
2860     Builder.defineMacro("__tune_pentiumpro__");
2861     // Fallthrough
2862   case CK_i686:
2863     Builder.defineMacro("__i686");
2864     Builder.defineMacro("__i686__");
2865     // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2866     Builder.defineMacro("__pentiumpro");
2867     Builder.defineMacro("__pentiumpro__");
2868     break;
2869   case CK_Pentium4:
2870   case CK_Pentium4M:
2871     defineCPUMacros(Builder, "pentium4");
2872     break;
2873   case CK_Yonah:
2874   case CK_Prescott:
2875   case CK_Nocona:
2876     defineCPUMacros(Builder, "nocona");
2877     break;
2878   case CK_Core2:
2879   case CK_Penryn:
2880     defineCPUMacros(Builder, "core2");
2881     break;
2882   case CK_Bonnell:
2883     defineCPUMacros(Builder, "atom");
2884     break;
2885   case CK_Silvermont:
2886     defineCPUMacros(Builder, "slm");
2887     break;
2888   case CK_Nehalem:
2889   case CK_Westmere:
2890   case CK_SandyBridge:
2891   case CK_IvyBridge:
2892   case CK_Haswell:
2893   case CK_Broadwell:
2894     // FIXME: Historically, we defined this legacy name, it would be nice to
2895     // remove it at some point. We've never exposed fine-grained names for
2896     // recent primary x86 CPUs, and we should keep it that way.
2897     defineCPUMacros(Builder, "corei7");
2898     break;
2899   case CK_Skylake:
2900     // FIXME: Historically, we defined this legacy name, it would be nice to
2901     // remove it at some point. This is the only fine-grained CPU macro in the
2902     // main intel CPU line, and it would be better to not have these and force
2903     // people to use ISA macros.
2904     defineCPUMacros(Builder, "skx");
2905     break;
2906   case CK_KNL:
2907     defineCPUMacros(Builder, "knl");
2908     break;
2909   case CK_K6_2:
2910     Builder.defineMacro("__k6_2__");
2911     Builder.defineMacro("__tune_k6_2__");
2912     // Fallthrough
2913   case CK_K6_3:
2914     if (CPU != CK_K6_2) {  // In case of fallthrough
2915       // FIXME: GCC may be enabling these in cases where some other k6
2916       // architecture is specified but -m3dnow is explicitly provided. The
2917       // exact semantics need to be determined and emulated here.
2918       Builder.defineMacro("__k6_3__");
2919       Builder.defineMacro("__tune_k6_3__");
2920     }
2921     // Fallthrough
2922   case CK_K6:
2923     defineCPUMacros(Builder, "k6");
2924     break;
2925   case CK_Athlon:
2926   case CK_AthlonThunderbird:
2927   case CK_Athlon4:
2928   case CK_AthlonXP:
2929   case CK_AthlonMP:
2930     defineCPUMacros(Builder, "athlon");
2931     if (SSELevel != NoSSE) {
2932       Builder.defineMacro("__athlon_sse__");
2933       Builder.defineMacro("__tune_athlon_sse__");
2934     }
2935     break;
2936   case CK_K8:
2937   case CK_K8SSE3:
2938   case CK_x86_64:
2939   case CK_Opteron:
2940   case CK_OpteronSSE3:
2941   case CK_Athlon64:
2942   case CK_Athlon64SSE3:
2943   case CK_AthlonFX:
2944     defineCPUMacros(Builder, "k8");
2945     break;
2946   case CK_AMDFAM10:
2947     defineCPUMacros(Builder, "amdfam10");
2948     break;
2949   case CK_BTVER1:
2950     defineCPUMacros(Builder, "btver1");
2951     break;
2952   case CK_BTVER2:
2953     defineCPUMacros(Builder, "btver2");
2954     break;
2955   case CK_BDVER1:
2956     defineCPUMacros(Builder, "bdver1");
2957     break;
2958   case CK_BDVER2:
2959     defineCPUMacros(Builder, "bdver2");
2960     break;
2961   case CK_BDVER3:
2962     defineCPUMacros(Builder, "bdver3");
2963     break;
2964   case CK_BDVER4:
2965     defineCPUMacros(Builder, "bdver4");
2966     break;
2967   case CK_Geode:
2968     defineCPUMacros(Builder, "geode");
2969     break;
2970   }
2971 
2972   // Target properties.
2973   Builder.defineMacro("__REGISTER_PREFIX__", "");
2974 
2975   // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2976   // functions in glibc header files that use FP Stack inline asm which the
2977   // backend can't deal with (PR879).
2978   Builder.defineMacro("__NO_MATH_INLINES");
2979 
2980   if (HasAES)
2981     Builder.defineMacro("__AES__");
2982 
2983   if (HasPCLMUL)
2984     Builder.defineMacro("__PCLMUL__");
2985 
2986   if (HasLZCNT)
2987     Builder.defineMacro("__LZCNT__");
2988 
2989   if (HasRDRND)
2990     Builder.defineMacro("__RDRND__");
2991 
2992   if (HasFSGSBASE)
2993     Builder.defineMacro("__FSGSBASE__");
2994 
2995   if (HasBMI)
2996     Builder.defineMacro("__BMI__");
2997 
2998   if (HasBMI2)
2999     Builder.defineMacro("__BMI2__");
3000 
3001   if (HasPOPCNT)
3002     Builder.defineMacro("__POPCNT__");
3003 
3004   if (HasRTM)
3005     Builder.defineMacro("__RTM__");
3006 
3007   if (HasPRFCHW)
3008     Builder.defineMacro("__PRFCHW__");
3009 
3010   if (HasRDSEED)
3011     Builder.defineMacro("__RDSEED__");
3012 
3013   if (HasADX)
3014     Builder.defineMacro("__ADX__");
3015 
3016   if (HasTBM)
3017     Builder.defineMacro("__TBM__");
3018 
3019   switch (XOPLevel) {
3020   case XOP:
3021     Builder.defineMacro("__XOP__");
3022   case FMA4:
3023     Builder.defineMacro("__FMA4__");
3024   case SSE4A:
3025     Builder.defineMacro("__SSE4A__");
3026   case NoXOP:
3027     break;
3028   }
3029 
3030   if (HasFMA)
3031     Builder.defineMacro("__FMA__");
3032 
3033   if (HasF16C)
3034     Builder.defineMacro("__F16C__");
3035 
3036   if (HasAVX512CD)
3037     Builder.defineMacro("__AVX512CD__");
3038   if (HasAVX512ER)
3039     Builder.defineMacro("__AVX512ER__");
3040   if (HasAVX512PF)
3041     Builder.defineMacro("__AVX512PF__");
3042   if (HasAVX512DQ)
3043     Builder.defineMacro("__AVX512DQ__");
3044   if (HasAVX512BW)
3045     Builder.defineMacro("__AVX512BW__");
3046   if (HasAVX512VL)
3047     Builder.defineMacro("__AVX512VL__");
3048 
3049   if (HasSHA)
3050     Builder.defineMacro("__SHA__");
3051 
3052   if (HasCX16)
3053     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
3054 
3055   // Each case falls through to the previous one here.
3056   switch (SSELevel) {
3057   case AVX512F:
3058     Builder.defineMacro("__AVX512F__");
3059   case AVX2:
3060     Builder.defineMacro("__AVX2__");
3061   case AVX:
3062     Builder.defineMacro("__AVX__");
3063   case SSE42:
3064     Builder.defineMacro("__SSE4_2__");
3065   case SSE41:
3066     Builder.defineMacro("__SSE4_1__");
3067   case SSSE3:
3068     Builder.defineMacro("__SSSE3__");
3069   case SSE3:
3070     Builder.defineMacro("__SSE3__");
3071   case SSE2:
3072     Builder.defineMacro("__SSE2__");
3073     Builder.defineMacro("__SSE2_MATH__");  // -mfp-math=sse always implied.
3074   case SSE1:
3075     Builder.defineMacro("__SSE__");
3076     Builder.defineMacro("__SSE_MATH__");   // -mfp-math=sse always implied.
3077   case NoSSE:
3078     break;
3079   }
3080 
3081   if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
3082     switch (SSELevel) {
3083     case AVX512F:
3084     case AVX2:
3085     case AVX:
3086     case SSE42:
3087     case SSE41:
3088     case SSSE3:
3089     case SSE3:
3090     case SSE2:
3091       Builder.defineMacro("_M_IX86_FP", Twine(2));
3092       break;
3093     case SSE1:
3094       Builder.defineMacro("_M_IX86_FP", Twine(1));
3095       break;
3096     default:
3097       Builder.defineMacro("_M_IX86_FP", Twine(0));
3098     }
3099   }
3100 
3101   // Each case falls through to the previous one here.
3102   switch (MMX3DNowLevel) {
3103   case AMD3DNowAthlon:
3104     Builder.defineMacro("__3dNOW_A__");
3105   case AMD3DNow:
3106     Builder.defineMacro("__3dNOW__");
3107   case MMX:
3108     Builder.defineMacro("__MMX__");
3109   case NoMMX3DNow:
3110     break;
3111   }
3112 
3113   if (CPU >= CK_i486) {
3114     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3115     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3116     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3117   }
3118   if (CPU >= CK_i586)
3119     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3120 }
3121 
3122 bool X86TargetInfo::hasFeature(StringRef Feature) const {
3123   return llvm::StringSwitch<bool>(Feature)
3124       .Case("aes", HasAES)
3125       .Case("avx", SSELevel >= AVX)
3126       .Case("avx2", SSELevel >= AVX2)
3127       .Case("avx512f", SSELevel >= AVX512F)
3128       .Case("avx512cd", HasAVX512CD)
3129       .Case("avx512er", HasAVX512ER)
3130       .Case("avx512pf", HasAVX512PF)
3131       .Case("avx512dq", HasAVX512DQ)
3132       .Case("avx512bw", HasAVX512BW)
3133       .Case("avx512vl", HasAVX512VL)
3134       .Case("bmi", HasBMI)
3135       .Case("bmi2", HasBMI2)
3136       .Case("cx16", HasCX16)
3137       .Case("f16c", HasF16C)
3138       .Case("fma", HasFMA)
3139       .Case("fma4", XOPLevel >= FMA4)
3140       .Case("fsgsbase", HasFSGSBASE)
3141       .Case("lzcnt", HasLZCNT)
3142       .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3143       .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3144       .Case("mmx", MMX3DNowLevel >= MMX)
3145       .Case("pclmul", HasPCLMUL)
3146       .Case("popcnt", HasPOPCNT)
3147       .Case("prfchw", HasPRFCHW)
3148       .Case("rdrnd", HasRDRND)
3149       .Case("rdseed", HasRDSEED)
3150       .Case("rtm", HasRTM)
3151       .Case("sha", HasSHA)
3152       .Case("sse", SSELevel >= SSE1)
3153       .Case("sse2", SSELevel >= SSE2)
3154       .Case("sse3", SSELevel >= SSE3)
3155       .Case("ssse3", SSELevel >= SSSE3)
3156       .Case("sse4.1", SSELevel >= SSE41)
3157       .Case("sse4.2", SSELevel >= SSE42)
3158       .Case("sse4a", XOPLevel >= SSE4A)
3159       .Case("tbm", HasTBM)
3160       .Case("x86", true)
3161       .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
3162       .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
3163       .Case("xop", XOPLevel >= XOP)
3164       .Default(false);
3165 }
3166 
3167 bool
3168 X86TargetInfo::validateAsmConstraint(const char *&Name,
3169                                      TargetInfo::ConstraintInfo &Info) const {
3170   switch (*Name) {
3171   default: return false;
3172   case 'I':
3173     Info.setRequiresImmediate(0, 31);
3174     return true;
3175   case 'J':
3176     Info.setRequiresImmediate(0, 63);
3177     return true;
3178   case 'K':
3179     Info.setRequiresImmediate(-128, 127);
3180     return true;
3181   case 'L':
3182     // FIXME: properly analyze this constraint:
3183     //  must be one of 0xff, 0xffff, or 0xffffffff
3184     return true;
3185   case 'M':
3186     Info.setRequiresImmediate(0, 3);
3187     return true;
3188   case 'N':
3189     Info.setRequiresImmediate(0, 255);
3190     return true;
3191   case 'O':
3192     Info.setRequiresImmediate(0, 127);
3193     return true;
3194   case 'Y': // first letter of a pair:
3195     switch (*(Name+1)) {
3196     default: return false;
3197     case '0':  // First SSE register.
3198     case 't':  // Any SSE register, when SSE2 is enabled.
3199     case 'i':  // Any SSE register, when SSE2 and inter-unit moves enabled.
3200     case 'm':  // any MMX register, when inter-unit moves enabled.
3201       break;   // falls through to setAllowsRegister.
3202   }
3203   case 'f': // any x87 floating point stack register.
3204     // Constraint 'f' cannot be used for output operands.
3205     if (Info.ConstraintStr[0] == '=')
3206       return false;
3207 
3208     Info.setAllowsRegister();
3209     return true;
3210   case 'a': // eax.
3211   case 'b': // ebx.
3212   case 'c': // ecx.
3213   case 'd': // edx.
3214   case 'S': // esi.
3215   case 'D': // edi.
3216   case 'A': // edx:eax.
3217   case 't': // top of floating point stack.
3218   case 'u': // second from top of floating point stack.
3219   case 'q': // Any register accessible as [r]l: a, b, c, and d.
3220   case 'y': // Any MMX register.
3221   case 'x': // Any SSE register.
3222   case 'Q': // Any register accessible as [r]h: a, b, c, and d.
3223   case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
3224   case 'l': // "Index" registers: any general register that can be used as an
3225             // index in a base+index memory access.
3226     Info.setAllowsRegister();
3227     return true;
3228   case 'C': // SSE floating point constant.
3229   case 'G': // x87 floating point constant.
3230   case 'e': // 32-bit signed integer constant for use with zero-extending
3231             // x86_64 instructions.
3232   case 'Z': // 32-bit unsigned integer constant for use with zero-extending
3233             // x86_64 instructions.
3234     return true;
3235   }
3236 }
3237 
3238 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
3239                                        unsigned Size) const {
3240   // Strip off constraint modifiers.
3241   while (Constraint[0] == '=' ||
3242          Constraint[0] == '+' ||
3243          Constraint[0] == '&')
3244     Constraint = Constraint.substr(1);
3245 
3246   return validateOperandSize(Constraint, Size);
3247 }
3248 
3249 bool X86TargetInfo::validateInputSize(StringRef Constraint,
3250                                       unsigned Size) const {
3251   return validateOperandSize(Constraint, Size);
3252 }
3253 
3254 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
3255                                         unsigned Size) const {
3256   switch (Constraint[0]) {
3257   default: break;
3258   case 'y':
3259     return Size <= 64;
3260   case 'f':
3261   case 't':
3262   case 'u':
3263     return Size <= 128;
3264   case 'x':
3265     // 256-bit ymm registers can be used if target supports AVX.
3266     return Size <= (SSELevel >= AVX ? 256U : 128U);
3267   }
3268 
3269   return true;
3270 }
3271 
3272 std::string
3273 X86TargetInfo::convertConstraint(const char *&Constraint) const {
3274   switch (*Constraint) {
3275   case 'a': return std::string("{ax}");
3276   case 'b': return std::string("{bx}");
3277   case 'c': return std::string("{cx}");
3278   case 'd': return std::string("{dx}");
3279   case 'S': return std::string("{si}");
3280   case 'D': return std::string("{di}");
3281   case 'p': // address
3282     return std::string("im");
3283   case 't': // top of floating point stack.
3284     return std::string("{st}");
3285   case 'u': // second from top of floating point stack.
3286     return std::string("{st(1)}"); // second from top of floating point stack.
3287   default:
3288     return std::string(1, *Constraint);
3289   }
3290 }
3291 } // end anonymous namespace
3292 
3293 namespace {
3294 // X86-32 generic target
3295 class X86_32TargetInfo : public X86TargetInfo {
3296 public:
3297   X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3298     DoubleAlign = LongLongAlign = 32;
3299     LongDoubleWidth = 96;
3300     LongDoubleAlign = 32;
3301     SuitableAlign = 128;
3302     DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128";
3303     SizeType = UnsignedInt;
3304     PtrDiffType = SignedInt;
3305     IntPtrType = SignedInt;
3306     RegParmMax = 3;
3307 
3308     // Use fpret for all types.
3309     RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
3310                              (1 << TargetInfo::Double) |
3311                              (1 << TargetInfo::LongDouble));
3312 
3313     // x86-32 has atomics up to 8 bytes
3314     // FIXME: Check that we actually have cmpxchg8b before setting
3315     // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
3316     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3317   }
3318   BuiltinVaListKind getBuiltinVaListKind() const override {
3319     return TargetInfo::CharPtrBuiltinVaList;
3320   }
3321 
3322   int getEHDataRegisterNumber(unsigned RegNo) const override {
3323     if (RegNo == 0) return 0;
3324     if (RegNo == 1) return 2;
3325     return -1;
3326   }
3327   bool validateOperandSize(StringRef Constraint,
3328                            unsigned Size) const override {
3329     switch (Constraint[0]) {
3330     default: break;
3331     case 'R':
3332     case 'q':
3333     case 'Q':
3334     case 'a':
3335     case 'b':
3336     case 'c':
3337     case 'd':
3338     case 'S':
3339     case 'D':
3340       return Size <= 32;
3341     case 'A':
3342       return Size <= 64;
3343     }
3344 
3345     return X86TargetInfo::validateOperandSize(Constraint, Size);
3346   }
3347 };
3348 } // end anonymous namespace
3349 
3350 namespace {
3351 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
3352 public:
3353   NetBSDI386TargetInfo(const llvm::Triple &Triple)
3354       : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
3355 
3356   unsigned getFloatEvalMethod() const override {
3357     unsigned Major, Minor, Micro;
3358     getTriple().getOSVersion(Major, Minor, Micro);
3359     // New NetBSD uses the default rounding mode.
3360     if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3361       return X86_32TargetInfo::getFloatEvalMethod();
3362     // NetBSD before 6.99.26 defaults to "double" rounding.
3363     return 1;
3364   }
3365 };
3366 } // end anonymous namespace
3367 
3368 namespace {
3369 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3370 public:
3371   OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3372       : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3373     SizeType = UnsignedLong;
3374     IntPtrType = SignedLong;
3375     PtrDiffType = SignedLong;
3376   }
3377 };
3378 } // end anonymous namespace
3379 
3380 namespace {
3381 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3382 public:
3383   BitrigI386TargetInfo(const llvm::Triple &Triple)
3384       : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3385     SizeType = UnsignedLong;
3386     IntPtrType = SignedLong;
3387     PtrDiffType = SignedLong;
3388   }
3389 };
3390 } // end anonymous namespace
3391 
3392 namespace {
3393 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3394 public:
3395   DarwinI386TargetInfo(const llvm::Triple &Triple)
3396       : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3397     LongDoubleWidth = 128;
3398     LongDoubleAlign = 128;
3399     SuitableAlign = 128;
3400     MaxVectorAlign = 256;
3401     SizeType = UnsignedLong;
3402     IntPtrType = SignedLong;
3403     DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
3404     HasAlignMac68kSupport = true;
3405   }
3406 
3407 };
3408 } // end anonymous namespace
3409 
3410 namespace {
3411 // x86-32 Windows target
3412 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3413 public:
3414   WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3415       : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3416     WCharType = UnsignedShort;
3417     DoubleAlign = LongLongAlign = 64;
3418     DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32";
3419   }
3420   void getTargetDefines(const LangOptions &Opts,
3421                         MacroBuilder &Builder) const override {
3422     WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3423   }
3424 };
3425 
3426 // x86-32 Windows Visual Studio target
3427 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
3428 public:
3429   MicrosoftX86_32TargetInfo(const llvm::Triple &Triple)
3430       : WindowsX86_32TargetInfo(Triple) {
3431     LongDoubleWidth = LongDoubleAlign = 64;
3432     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3433   }
3434   void getTargetDefines(const LangOptions &Opts,
3435                         MacroBuilder &Builder) const override {
3436     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3437     WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3438     // The value of the following reflects processor type.
3439     // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3440     // We lost the original triple, so we use the default.
3441     Builder.defineMacro("_M_IX86", "600");
3442   }
3443 };
3444 } // end anonymous namespace
3445 
3446 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3447   Builder.defineMacro("__MSVCRT__");
3448   Builder.defineMacro("__MINGW32__");
3449 
3450   // Mingw defines __declspec(a) to __attribute__((a)).  Clang supports
3451   // __declspec natively under -fms-extensions, but we define a no-op __declspec
3452   // macro anyway for pre-processor compatibility.
3453   if (Opts.MicrosoftExt)
3454     Builder.defineMacro("__declspec", "__declspec");
3455   else
3456     Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3457 
3458   if (!Opts.MicrosoftExt) {
3459     // Provide macros for all the calling convention keywords.  Provide both
3460     // single and double underscore prefixed variants.  These are available on
3461     // x64 as well as x86, even though they have no effect.
3462     const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
3463     for (const char *CC : CCs) {
3464       std::string GCCSpelling = "__attribute__((__";
3465       GCCSpelling += CC;
3466       GCCSpelling += "__))";
3467       Builder.defineMacro(Twine("_") + CC, GCCSpelling);
3468       Builder.defineMacro(Twine("__") + CC, GCCSpelling);
3469     }
3470   }
3471 }
3472 
3473 namespace {
3474 // x86-32 MinGW target
3475 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3476 public:
3477   MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3478       : WindowsX86_32TargetInfo(Triple) {}
3479   void getTargetDefines(const LangOptions &Opts,
3480                         MacroBuilder &Builder) const override {
3481     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3482     DefineStd(Builder, "WIN32", Opts);
3483     DefineStd(Builder, "WINNT", Opts);
3484     Builder.defineMacro("_X86_");
3485     addMinGWDefines(Opts, Builder);
3486   }
3487 };
3488 } // end anonymous namespace
3489 
3490 namespace {
3491 // x86-32 Cygwin target
3492 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3493 public:
3494   CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3495       : X86_32TargetInfo(Triple) {
3496     TLSSupported = false;
3497     WCharType = UnsignedShort;
3498     DoubleAlign = LongLongAlign = 64;
3499     DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32";
3500   }
3501   void getTargetDefines(const LangOptions &Opts,
3502                         MacroBuilder &Builder) const override {
3503     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3504     Builder.defineMacro("_X86_");
3505     Builder.defineMacro("__CYGWIN__");
3506     Builder.defineMacro("__CYGWIN32__");
3507     DefineStd(Builder, "unix", Opts);
3508     if (Opts.CPlusPlus)
3509       Builder.defineMacro("_GNU_SOURCE");
3510   }
3511 };
3512 } // end anonymous namespace
3513 
3514 namespace {
3515 // x86-32 Haiku target
3516 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3517 public:
3518   HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3519     SizeType = UnsignedLong;
3520     IntPtrType = SignedLong;
3521     PtrDiffType = SignedLong;
3522     ProcessIDType = SignedLong;
3523     this->UserLabelPrefix = "";
3524     this->TLSSupported = false;
3525   }
3526   void getTargetDefines(const LangOptions &Opts,
3527                         MacroBuilder &Builder) const override {
3528     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3529     Builder.defineMacro("__INTEL__");
3530     Builder.defineMacro("__HAIKU__");
3531   }
3532 };
3533 } // end anonymous namespace
3534 
3535 // RTEMS Target
3536 template<typename Target>
3537 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3538 protected:
3539   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3540                     MacroBuilder &Builder) const override {
3541     // RTEMS defines; list based off of gcc output
3542 
3543     Builder.defineMacro("__rtems__");
3544     Builder.defineMacro("__ELF__");
3545   }
3546 
3547 public:
3548   RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3549     this->UserLabelPrefix = "";
3550 
3551     switch (Triple.getArch()) {
3552     default:
3553     case llvm::Triple::x86:
3554       // this->MCountName = ".mcount";
3555       break;
3556     case llvm::Triple::mips:
3557     case llvm::Triple::mipsel:
3558     case llvm::Triple::ppc:
3559     case llvm::Triple::ppc64:
3560     case llvm::Triple::ppc64le:
3561       // this->MCountName = "_mcount";
3562       break;
3563     case llvm::Triple::arm:
3564       // this->MCountName = "__mcount";
3565       break;
3566     }
3567   }
3568 };
3569 
3570 namespace {
3571 // x86-32 RTEMS target
3572 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3573 public:
3574   RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3575     SizeType = UnsignedLong;
3576     IntPtrType = SignedLong;
3577     PtrDiffType = SignedLong;
3578     this->UserLabelPrefix = "";
3579   }
3580   void getTargetDefines(const LangOptions &Opts,
3581                         MacroBuilder &Builder) const override {
3582     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3583     Builder.defineMacro("__INTEL__");
3584     Builder.defineMacro("__rtems__");
3585   }
3586 };
3587 } // end anonymous namespace
3588 
3589 namespace {
3590 // x86-64 generic target
3591 class X86_64TargetInfo : public X86TargetInfo {
3592 public:
3593   X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3594     const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
3595     LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
3596     LongDoubleWidth = 128;
3597     LongDoubleAlign = 128;
3598     LargeArrayMinWidth = 128;
3599     LargeArrayAlign = 128;
3600     SuitableAlign = 128;
3601     SizeType    = IsX32 ? UnsignedInt      : UnsignedLong;
3602     PtrDiffType = IsX32 ? SignedInt        : SignedLong;
3603     IntPtrType  = IsX32 ? SignedInt        : SignedLong;
3604     IntMaxType  = IsX32 ? SignedLongLong   : SignedLong;
3605     Int64Type   = IsX32 ? SignedLongLong   : SignedLong;
3606     RegParmMax = 6;
3607 
3608     // Pointers are 32-bit in x32.
3609     DescriptionString = (IsX32)
3610                             ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
3611                             : "e-m:e-i64:64-f80:128-n8:16:32:64-S128";
3612 
3613     // Use fpret only for long double.
3614     RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3615 
3616     // Use fp2ret for _Complex long double.
3617     ComplexLongDoubleUsesFP2Ret = true;
3618 
3619     // x86-64 has atomics up to 16 bytes.
3620     MaxAtomicPromoteWidth = 128;
3621     MaxAtomicInlineWidth = 128;
3622   }
3623   BuiltinVaListKind getBuiltinVaListKind() const override {
3624     return TargetInfo::X86_64ABIBuiltinVaList;
3625   }
3626 
3627   int getEHDataRegisterNumber(unsigned RegNo) const override {
3628     if (RegNo == 0) return 0;
3629     if (RegNo == 1) return 1;
3630     return -1;
3631   }
3632 
3633   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3634     return (CC == CC_C ||
3635             CC == CC_X86VectorCall ||
3636             CC == CC_IntelOclBicc ||
3637             CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
3638   }
3639 
3640   CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3641     return CC_C;
3642   }
3643 
3644   // for x32 we need it here explicitly
3645   bool hasInt128Type() const override { return true; }
3646 };
3647 } // end anonymous namespace
3648 
3649 namespace {
3650 // x86-64 Windows target
3651 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3652 public:
3653   WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3654       : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3655     WCharType = UnsignedShort;
3656     LongWidth = LongAlign = 32;
3657     DoubleAlign = LongLongAlign = 64;
3658     IntMaxType = SignedLongLong;
3659     Int64Type = SignedLongLong;
3660     SizeType = UnsignedLongLong;
3661     PtrDiffType = SignedLongLong;
3662     IntPtrType = SignedLongLong;
3663     this->UserLabelPrefix = "";
3664   }
3665 
3666   void getTargetDefines(const LangOptions &Opts,
3667                                 MacroBuilder &Builder) const override {
3668     WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3669     Builder.defineMacro("_WIN64");
3670   }
3671 
3672   BuiltinVaListKind getBuiltinVaListKind() const override {
3673     return TargetInfo::CharPtrBuiltinVaList;
3674   }
3675 
3676   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3677     switch (CC) {
3678     case CC_X86StdCall:
3679     case CC_X86ThisCall:
3680     case CC_X86FastCall:
3681       return CCCR_Ignore;
3682     case CC_C:
3683     case CC_X86VectorCall:
3684     case CC_IntelOclBicc:
3685     case CC_X86_64SysV:
3686       return CCCR_OK;
3687     default:
3688       return CCCR_Warning;
3689     }
3690   }
3691 };
3692 } // end anonymous namespace
3693 
3694 namespace {
3695 // x86-64 Windows Visual Studio target
3696 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
3697 public:
3698   MicrosoftX86_64TargetInfo(const llvm::Triple &Triple)
3699       : WindowsX86_64TargetInfo(Triple) {
3700     LongDoubleWidth = LongDoubleAlign = 64;
3701     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3702   }
3703   void getTargetDefines(const LangOptions &Opts,
3704                         MacroBuilder &Builder) const override {
3705     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3706     WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3707     Builder.defineMacro("_M_X64");
3708     Builder.defineMacro("_M_AMD64");
3709   }
3710 };
3711 } // end anonymous namespace
3712 
3713 namespace {
3714 // x86-64 MinGW target
3715 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3716 public:
3717   MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3718       : WindowsX86_64TargetInfo(Triple) {}
3719   void getTargetDefines(const LangOptions &Opts,
3720                         MacroBuilder &Builder) const override {
3721     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3722     DefineStd(Builder, "WIN64", Opts);
3723     Builder.defineMacro("__MINGW64__");
3724     addMinGWDefines(Opts, Builder);
3725 
3726     // GCC defines this macro when it is using __gxx_personality_seh0.
3727     if (!Opts.SjLjExceptions)
3728       Builder.defineMacro("__SEH__");
3729   }
3730 };
3731 } // end anonymous namespace
3732 
3733 namespace {
3734 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3735 public:
3736   DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3737       : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3738     Int64Type = SignedLongLong;
3739     MaxVectorAlign = 256;
3740     // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
3741     llvm::Triple T = llvm::Triple(Triple);
3742     if (T.isiOS())
3743       UseSignedCharForObjCBool = false;
3744     DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
3745   }
3746 };
3747 } // end anonymous namespace
3748 
3749 namespace {
3750 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3751 public:
3752   OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
3753       : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
3754     IntMaxType = SignedLongLong;
3755     Int64Type = SignedLongLong;
3756   }
3757 };
3758 } // end anonymous namespace
3759 
3760 namespace {
3761 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3762 public:
3763   BitrigX86_64TargetInfo(const llvm::Triple &Triple)
3764       : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
3765     IntMaxType = SignedLongLong;
3766     Int64Type = SignedLongLong;
3767   }
3768 };
3769 }
3770 
3771 
3772 namespace {
3773 class ARMTargetInfo : public TargetInfo {
3774   // Possible FPU choices.
3775   enum FPUMode {
3776     VFP2FPU = (1 << 0),
3777     VFP3FPU = (1 << 1),
3778     VFP4FPU = (1 << 2),
3779     NeonFPU = (1 << 3),
3780     FPARMV8 = (1 << 4)
3781   };
3782 
3783   // Possible HWDiv features.
3784   enum HWDivMode {
3785     HWDivThumb = (1 << 0),
3786     HWDivARM = (1 << 1)
3787   };
3788 
3789   static bool FPUModeIsVFP(FPUMode Mode) {
3790     return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
3791   }
3792 
3793   static const TargetInfo::GCCRegAlias GCCRegAliases[];
3794   static const char * const GCCRegNames[];
3795 
3796   std::string ABI, CPU;
3797 
3798   enum {
3799     FP_Default,
3800     FP_VFP,
3801     FP_Neon
3802   } FPMath;
3803 
3804   unsigned FPU : 5;
3805 
3806   unsigned IsAAPCS : 1;
3807   unsigned IsThumb : 1;
3808   unsigned HWDiv : 2;
3809 
3810   // Initialized via features.
3811   unsigned SoftFloat : 1;
3812   unsigned SoftFloatABI : 1;
3813 
3814   unsigned CRC : 1;
3815   unsigned Crypto : 1;
3816 
3817   // ACLE 6.5.1 Hardware floating point
3818   enum {
3819     HW_FP_HP = (1 << 1), /// half (16-bit)
3820     HW_FP_SP = (1 << 2), /// single (32-bit)
3821     HW_FP_DP = (1 << 3), /// double (64-bit)
3822   };
3823   uint32_t HW_FP;
3824 
3825   static const Builtin::Info BuiltinInfo[];
3826 
3827   static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3828     StringRef ArchName = T.getArchName();
3829     if (T.getArch() == llvm::Triple::arm ||
3830         T.getArch() == llvm::Triple::armeb) {
3831       StringRef VersionStr;
3832       if (ArchName.startswith("armv"))
3833         VersionStr = ArchName.substr(4, 1);
3834       else if (ArchName.startswith("armebv"))
3835         VersionStr = ArchName.substr(6, 1);
3836       else
3837         return false;
3838       unsigned Version;
3839       if (VersionStr.getAsInteger(10, Version))
3840         return false;
3841       return Version >= 6;
3842     }
3843     assert(T.getArch() == llvm::Triple::thumb ||
3844            T.getArch() == llvm::Triple::thumbeb);
3845     StringRef VersionStr;
3846     if (ArchName.startswith("thumbv"))
3847       VersionStr = ArchName.substr(6, 1);
3848     else if (ArchName.startswith("thumbebv"))
3849       VersionStr = ArchName.substr(8, 1);
3850     else
3851       return false;
3852     unsigned Version;
3853     if (VersionStr.getAsInteger(10, Version))
3854       return false;
3855     return Version >= 7;
3856   }
3857 
3858   void setABIAAPCS() {
3859     IsAAPCS = true;
3860 
3861     DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
3862     const llvm::Triple &T = getTriple();
3863 
3864     // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig.
3865     if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD ||
3866         T.getOS() == llvm::Triple::Bitrig)
3867       SizeType = UnsignedLong;
3868     else
3869       SizeType = UnsignedInt;
3870 
3871     switch (T.getOS()) {
3872     case llvm::Triple::NetBSD:
3873       WCharType = SignedInt;
3874       break;
3875     case llvm::Triple::Win32:
3876       WCharType = UnsignedShort;
3877       break;
3878     case llvm::Triple::Linux:
3879     default:
3880       // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3881       WCharType = UnsignedInt;
3882       break;
3883     }
3884 
3885     UseBitFieldTypeAlignment = true;
3886 
3887     ZeroLengthBitfieldBoundary = 0;
3888 
3889     // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3890     // so set preferred for small types to 32.
3891     if (T.isOSBinFormatMachO()) {
3892       DescriptionString =
3893           BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
3894                     : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
3895     } else if (T.isOSWindows()) {
3896       // FIXME: this is invalid for WindowsCE
3897       assert(!BigEndian && "Windows on ARM does not support big endian");
3898       DescriptionString = "e"
3899                           "-m:e"
3900                           "-p:32:32"
3901                           "-i64:64"
3902                           "-v128:64:128"
3903                           "-a:0:32"
3904                           "-n32"
3905                           "-S64";
3906     } else {
3907       DescriptionString =
3908           BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
3909                     : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
3910     }
3911 
3912     // FIXME: Enumerated types are variable width in straight AAPCS.
3913   }
3914 
3915   void setABIAPCS() {
3916     const llvm::Triple &T = getTriple();
3917 
3918     IsAAPCS = false;
3919 
3920     DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3921 
3922     // size_t is unsigned int on FreeBSD.
3923     if (T.getOS() == llvm::Triple::FreeBSD)
3924       SizeType = UnsignedInt;
3925     else
3926       SizeType = UnsignedLong;
3927 
3928     // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3929     WCharType = SignedInt;
3930 
3931     // Do not respect the alignment of bit-field types when laying out
3932     // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3933     UseBitFieldTypeAlignment = false;
3934 
3935     /// gcc forces the alignment to 4 bytes, regardless of the type of the
3936     /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
3937     /// gcc.
3938     ZeroLengthBitfieldBoundary = 32;
3939 
3940     if (T.isOSBinFormatMachO())
3941       DescriptionString =
3942           BigEndian
3943               ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
3944               : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3945     else
3946       DescriptionString =
3947           BigEndian
3948               ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
3949               : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3950 
3951     // FIXME: Override "preferred align" for double and long long.
3952   }
3953 
3954 public:
3955   ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
3956       : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default),
3957         IsAAPCS(true), HW_FP(0) {
3958     BigEndian = IsBigEndian;
3959 
3960     switch (getTriple().getOS()) {
3961     case llvm::Triple::NetBSD:
3962       PtrDiffType = SignedLong;
3963       break;
3964     default:
3965       PtrDiffType = SignedInt;
3966       break;
3967     }
3968 
3969     // {} in inline assembly are neon specifiers, not assembly variant
3970     // specifiers.
3971     NoAsmVariants = true;
3972 
3973     // FIXME: Should we just treat this as a feature?
3974     IsThumb = getTriple().getArchName().startswith("thumb");
3975 
3976     // FIXME: This duplicates code from the driver that sets the -target-abi
3977     // option - this code is used if -target-abi isn't passed and should
3978     // be unified in some way.
3979     if (Triple.isOSBinFormatMachO()) {
3980       // The backend is hardwired to assume AAPCS for M-class processors, ensure
3981       // the frontend matches that.
3982       if (Triple.getEnvironment() == llvm::Triple::EABI ||
3983           Triple.getOS() == llvm::Triple::UnknownOS ||
3984           StringRef(CPU).startswith("cortex-m")) {
3985         setABI("aapcs");
3986       } else {
3987         setABI("apcs-gnu");
3988       }
3989     } else if (Triple.isOSWindows()) {
3990       // FIXME: this is invalid for WindowsCE
3991       setABI("aapcs");
3992     } else {
3993       // Select the default based on the platform.
3994       switch (Triple.getEnvironment()) {
3995       case llvm::Triple::Android:
3996       case llvm::Triple::GNUEABI:
3997       case llvm::Triple::GNUEABIHF:
3998         setABI("aapcs-linux");
3999         break;
4000       case llvm::Triple::EABIHF:
4001       case llvm::Triple::EABI:
4002         setABI("aapcs");
4003         break;
4004       case llvm::Triple::GNU:
4005 	setABI("apcs-gnu");
4006 	break;
4007       default:
4008         if (Triple.getOS() == llvm::Triple::NetBSD)
4009           setABI("apcs-gnu");
4010         else
4011           setABI("aapcs");
4012         break;
4013       }
4014     }
4015 
4016     // ARM targets default to using the ARM C++ ABI.
4017     TheCXXABI.set(TargetCXXABI::GenericARM);
4018 
4019     // ARM has atomics up to 8 bytes
4020     MaxAtomicPromoteWidth = 64;
4021     if (shouldUseInlineAtomic(getTriple()))
4022       MaxAtomicInlineWidth = 64;
4023 
4024     // Do force alignment of members that follow zero length bitfields.  If
4025     // the alignment of the zero-length bitfield is greater than the member
4026     // that follows it, `bar', `bar' will be aligned as the  type of the
4027     // zero length bitfield.
4028     UseZeroLengthBitfieldAlignment = true;
4029   }
4030   StringRef getABI() const override { return ABI; }
4031   bool setABI(const std::string &Name) override {
4032     ABI = Name;
4033 
4034     // The defaults (above) are for AAPCS, check if we need to change them.
4035     //
4036     // FIXME: We need support for -meabi... we could just mangle it into the
4037     // name.
4038     if (Name == "apcs-gnu") {
4039       setABIAPCS();
4040       return true;
4041     }
4042     if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
4043       setABIAAPCS();
4044       return true;
4045     }
4046     return false;
4047   }
4048 
4049   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
4050     StringRef ArchName = getTriple().getArchName();
4051     if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
4052       Features["vfp2"] = true;
4053     else if (CPU == "cortex-a8" || CPU == "cortex-a9") {
4054       Features["vfp3"] = true;
4055       Features["neon"] = true;
4056     }
4057     else if (CPU == "cortex-a5") {
4058       Features["vfp4"] = true;
4059       Features["neon"] = true;
4060     } else if (CPU == "swift" || CPU == "cortex-a7" ||
4061                CPU == "cortex-a12" || CPU == "cortex-a15" ||
4062                CPU == "cortex-a17" || CPU == "krait") {
4063       Features["vfp4"] = true;
4064       Features["neon"] = true;
4065       Features["hwdiv"] = true;
4066       Features["hwdiv-arm"] = true;
4067     } else if (CPU == "cyclone") {
4068       Features["v8fp"] = true;
4069       Features["neon"] = true;
4070       Features["hwdiv"] = true;
4071       Features["hwdiv-arm"] = true;
4072     } else if (CPU == "cortex-a53" || CPU == "cortex-a57" || CPU == "cortex-a72") {
4073       Features["fp-armv8"] = true;
4074       Features["neon"] = true;
4075       Features["hwdiv"] = true;
4076       Features["hwdiv-arm"] = true;
4077       Features["crc"] = true;
4078       Features["crypto"] = true;
4079     } else if (CPU == "cortex-r5" || CPU == "cortex-r7" ||
4080                // Enable the hwdiv extension for all v8a AArch32 cores by
4081                // default.
4082                ArchName == "armv8a" || ArchName == "armv8" ||
4083                ArchName == "armebv8a" || ArchName == "armebv8" ||
4084                ArchName == "thumbv8a" || ArchName == "thumbv8" ||
4085                ArchName == "thumbebv8a" || ArchName == "thumbebv8") {
4086       Features["hwdiv"] = true;
4087       Features["hwdiv-arm"] = true;
4088     } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" ||
4089                CPU == "sc300") {
4090       Features["hwdiv"] = true;
4091     }
4092   }
4093 
4094   bool handleTargetFeatures(std::vector<std::string> &Features,
4095                             DiagnosticsEngine &Diags) override {
4096     FPU = 0;
4097     CRC = 0;
4098     Crypto = 0;
4099     SoftFloat = SoftFloatABI = false;
4100     HWDiv = 0;
4101 
4102     for (const auto &Feature : Features) {
4103       if (Feature == "+soft-float") {
4104         SoftFloat = true;
4105       } else if (Feature == "+soft-float-abi") {
4106         SoftFloatABI = true;
4107       } else if (Feature == "+vfp2") {
4108         FPU |= VFP2FPU;
4109         HW_FP = HW_FP_SP | HW_FP_DP;
4110       } else if (Feature == "+vfp3") {
4111         FPU |= VFP3FPU;
4112         HW_FP = HW_FP_SP | HW_FP_DP;
4113       } else if (Feature == "+vfp4") {
4114         FPU |= VFP4FPU;
4115         HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
4116       } else if (Feature == "+fp-armv8") {
4117         FPU |= FPARMV8;
4118         HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
4119       } else if (Feature == "+neon") {
4120         FPU |= NeonFPU;
4121         HW_FP = HW_FP_SP | HW_FP_DP;
4122       } else if (Feature == "+hwdiv") {
4123         HWDiv |= HWDivThumb;
4124       } else if (Feature == "+hwdiv-arm") {
4125         HWDiv |= HWDivARM;
4126       } else if (Feature == "+crc") {
4127         CRC = 1;
4128       } else if (Feature == "+crypto") {
4129         Crypto = 1;
4130       } else if (Feature == "+fp-only-sp") {
4131         HW_FP &= ~HW_FP_DP;
4132       }
4133     }
4134 
4135     if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
4136       Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
4137       return false;
4138     }
4139 
4140     if (FPMath == FP_Neon)
4141       Features.push_back("+neonfp");
4142     else if (FPMath == FP_VFP)
4143       Features.push_back("-neonfp");
4144 
4145     // Remove front-end specific options which the backend handles differently.
4146     const StringRef FrontEndFeatures[] = { "+soft-float", "+soft-float-abi" };
4147     for (const auto &FEFeature : FrontEndFeatures) {
4148       auto Feature = std::find(Features.begin(), Features.end(), FEFeature);
4149       if (Feature != Features.end())
4150         Features.erase(Feature);
4151     }
4152 
4153     return true;
4154   }
4155 
4156   bool hasFeature(StringRef Feature) const override {
4157     return llvm::StringSwitch<bool>(Feature)
4158         .Case("arm", true)
4159         .Case("softfloat", SoftFloat)
4160         .Case("thumb", IsThumb)
4161         .Case("neon", (FPU & NeonFPU) && !SoftFloat)
4162         .Case("hwdiv", HWDiv & HWDivThumb)
4163         .Case("hwdiv-arm", HWDiv & HWDivARM)
4164         .Default(false);
4165   }
4166   // FIXME: Should we actually have some table instead of these switches?
4167   static const char *getCPUDefineSuffix(StringRef Name) {
4168     return llvm::StringSwitch<const char *>(Name)
4169         .Cases("arm8", "arm810", "4")
4170         .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110",
4171                "4")
4172         .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
4173         .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
4174         .Case("ep9312", "4T")
4175         .Cases("arm10tdmi", "arm1020t", "5T")
4176         .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
4177         .Case("arm926ej-s", "5TEJ")
4178         .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
4179         .Cases("xscale", "iwmmxt", "5TE")
4180         .Case("arm1136j-s", "6J")
4181         .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
4182         .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
4183         .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
4184         .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
4185         .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
4186                "7A")
4187         .Cases("cortex-r4", "cortex-r5", "cortex-r7", "7R")
4188         .Case("swift", "7S")
4189         .Case("cyclone", "8A")
4190         .Cases("sc300", "cortex-m3", "7M")
4191         .Cases("cortex-m4", "cortex-m7", "7EM")
4192         .Cases("sc000", "cortex-m0", "cortex-m0plus", "cortex-m1", "6M")
4193         .Cases("cortex-a53", "cortex-a57", "cortex-a72", "8A")
4194         .Default(nullptr);
4195   }
4196   static const char *getCPUProfile(StringRef Name) {
4197     return llvm::StringSwitch<const char *>(Name)
4198         .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A")
4199         .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
4200                "A")
4201         .Cases("cortex-a53", "cortex-a57", "cortex-a72", "A")
4202         .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m0plus", "M")
4203         .Cases("cortex-m1", "cortex-m7", "sc000", "sc300", "M")
4204         .Cases("cortex-r4", "cortex-r5", "cortex-r7", "R")
4205         .Default("");
4206   }
4207   bool setCPU(const std::string &Name) override {
4208     if (!getCPUDefineSuffix(Name))
4209       return false;
4210 
4211     // Cortex M does not support 8 byte atomics, while general Thumb2 does.
4212     StringRef Profile = getCPUProfile(Name);
4213     if (Profile == "M" && MaxAtomicInlineWidth) {
4214       MaxAtomicPromoteWidth = 32;
4215       MaxAtomicInlineWidth = 32;
4216     }
4217 
4218     CPU = Name;
4219     return true;
4220   }
4221   bool setFPMath(StringRef Name) override;
4222   bool supportsThumb(StringRef ArchName, StringRef CPUArch,
4223                      unsigned CPUArchVer) const {
4224     return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) ||
4225            (CPUArch.find('M') != StringRef::npos);
4226   }
4227   bool supportsThumb2(StringRef ArchName, StringRef CPUArch,
4228                       unsigned CPUArchVer) const {
4229     // We check both CPUArchVer and ArchName because when only triple is
4230     // specified, the default CPU is arm1136j-s.
4231     return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
4232            ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
4233   }
4234   void getTargetDefines(const LangOptions &Opts,
4235                         MacroBuilder &Builder) const override {
4236     // Target identification.
4237     Builder.defineMacro("__arm");
4238     Builder.defineMacro("__arm__");
4239 
4240     // Target properties.
4241     Builder.defineMacro("__REGISTER_PREFIX__", "");
4242 
4243     StringRef CPUArch = getCPUDefineSuffix(CPU);
4244     unsigned int CPUArchVer;
4245     if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer))
4246       llvm_unreachable("Invalid char for architecture version number");
4247     Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
4248 
4249     // ACLE 6.4.1 ARM/Thumb instruction set architecture
4250     StringRef CPUProfile = getCPUProfile(CPU);
4251     StringRef ArchName = getTriple().getArchName();
4252 
4253     // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
4254     Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
4255     if (CPUArch[0] >= '8') {
4256       Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4257       Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4258     }
4259 
4260     // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA.  It
4261     // is not defined for the M-profile.
4262     // NOTE that the deffault profile is assumed to be 'A'
4263     if (CPUProfile.empty() || CPUProfile != "M")
4264       Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
4265 
4266     // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
4267     // Thumb ISA (including v6-M).  It is set to 2 if the core supports the
4268     // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
4269     if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4270       Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
4271     else if (supportsThumb(ArchName, CPUArch, CPUArchVer))
4272       Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
4273 
4274     // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
4275     // instruction set such as ARM or Thumb.
4276     Builder.defineMacro("__ARM_32BIT_STATE", "1");
4277 
4278     // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
4279 
4280     // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
4281     if (!CPUProfile.empty())
4282       Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
4283 
4284     // ACLE 6.5.1 Hardware Floating Point
4285     if (HW_FP)
4286       Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
4287 
4288     // ACLE predefines.
4289     Builder.defineMacro("__ARM_ACLE", "200");
4290 
4291     // Subtarget options.
4292 
4293     // FIXME: It's more complicated than this and we don't really support
4294     // interworking.
4295     // Windows on ARM does not "support" interworking
4296     if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows())
4297       Builder.defineMacro("__THUMB_INTERWORK__");
4298 
4299     if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
4300       // Embedded targets on Darwin follow AAPCS, but not EABI.
4301       // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
4302       if (!getTriple().isOSDarwin() && !getTriple().isOSWindows())
4303         Builder.defineMacro("__ARM_EABI__");
4304       Builder.defineMacro("__ARM_PCS", "1");
4305 
4306       if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
4307         Builder.defineMacro("__ARM_PCS_VFP", "1");
4308     }
4309 
4310     if (SoftFloat)
4311       Builder.defineMacro("__SOFTFP__");
4312 
4313     if (CPU == "xscale")
4314       Builder.defineMacro("__XSCALE__");
4315 
4316     if (IsThumb) {
4317       Builder.defineMacro("__THUMBEL__");
4318       Builder.defineMacro("__thumb__");
4319       if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4320         Builder.defineMacro("__thumb2__");
4321     }
4322     if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
4323       Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
4324 
4325     // Note, this is always on in gcc, even though it doesn't make sense.
4326     Builder.defineMacro("__APCS_32__");
4327 
4328     if (FPUModeIsVFP((FPUMode) FPU)) {
4329       Builder.defineMacro("__VFP_FP__");
4330       if (FPU & VFP2FPU)
4331         Builder.defineMacro("__ARM_VFPV2__");
4332       if (FPU & VFP3FPU)
4333         Builder.defineMacro("__ARM_VFPV3__");
4334       if (FPU & VFP4FPU)
4335         Builder.defineMacro("__ARM_VFPV4__");
4336     }
4337 
4338     // This only gets set when Neon instructions are actually available, unlike
4339     // the VFP define, hence the soft float and arch check. This is subtly
4340     // different from gcc, we follow the intent which was that it should be set
4341     // when Neon instructions are actually available.
4342     if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) {
4343       Builder.defineMacro("__ARM_NEON");
4344       Builder.defineMacro("__ARM_NEON__");
4345     }
4346 
4347     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
4348                         Opts.ShortWChar ? "2" : "4");
4349 
4350     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4351                         Opts.ShortEnums ? "1" : "4");
4352 
4353     if (CRC)
4354       Builder.defineMacro("__ARM_FEATURE_CRC32");
4355 
4356     if (Crypto)
4357       Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4358 
4359     if (CPUArchVer >= 6 && CPUArch != "6M") {
4360       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4361       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4362       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4363       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4364     }
4365 
4366     bool is5EOrAbove = (CPUArchVer >= 6 ||
4367                         (CPUArchVer == 5 &&
4368                          CPUArch.find('E') != StringRef::npos));
4369     bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer));
4370     if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch  == "7EM"))
4371       Builder.defineMacro("__ARM_FEATURE_DSP");
4372   }
4373   void getTargetBuiltins(const Builtin::Info *&Records,
4374                          unsigned &NumRecords) const override {
4375     Records = BuiltinInfo;
4376     NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
4377   }
4378   bool isCLZForZeroUndef() const override { return false; }
4379   BuiltinVaListKind getBuiltinVaListKind() const override {
4380     return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
4381   }
4382   void getGCCRegNames(const char * const *&Names,
4383                       unsigned &NumNames) const override;
4384   void getGCCRegAliases(const GCCRegAlias *&Aliases,
4385                         unsigned &NumAliases) const override;
4386   bool validateAsmConstraint(const char *&Name,
4387                              TargetInfo::ConstraintInfo &Info) const override {
4388     switch (*Name) {
4389     default: break;
4390     case 'l': // r0-r7
4391     case 'h': // r8-r15
4392     case 'w': // VFP Floating point register single precision
4393     case 'P': // VFP Floating point register double precision
4394       Info.setAllowsRegister();
4395       return true;
4396     case 'I':
4397     case 'J':
4398     case 'K':
4399     case 'L':
4400     case 'M':
4401       // FIXME
4402       return true;
4403     case 'Q': // A memory address that is a single base register.
4404       Info.setAllowsMemory();
4405       return true;
4406     case 'U': // a memory reference...
4407       switch (Name[1]) {
4408       case 'q': // ...ARMV4 ldrsb
4409       case 'v': // ...VFP load/store (reg+constant offset)
4410       case 'y': // ...iWMMXt load/store
4411       case 't': // address valid for load/store opaque types wider
4412                 // than 128-bits
4413       case 'n': // valid address for Neon doubleword vector load/store
4414       case 'm': // valid address for Neon element and structure load/store
4415       case 's': // valid address for non-offset loads/stores of quad-word
4416                 // values in four ARM registers
4417         Info.setAllowsMemory();
4418         Name++;
4419         return true;
4420       }
4421     }
4422     return false;
4423   }
4424   std::string convertConstraint(const char *&Constraint) const override {
4425     std::string R;
4426     switch (*Constraint) {
4427     case 'U':   // Two-character constraint; add "^" hint for later parsing.
4428       R = std::string("^") + std::string(Constraint, 2);
4429       Constraint++;
4430       break;
4431     case 'p': // 'p' should be translated to 'r' by default.
4432       R = std::string("r");
4433       break;
4434     default:
4435       return std::string(1, *Constraint);
4436     }
4437     return R;
4438   }
4439   bool
4440   validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4441                              std::string &SuggestedModifier) const override {
4442     bool isOutput = (Constraint[0] == '=');
4443     bool isInOut = (Constraint[0] == '+');
4444 
4445     // Strip off constraint modifiers.
4446     while (Constraint[0] == '=' ||
4447            Constraint[0] == '+' ||
4448            Constraint[0] == '&')
4449       Constraint = Constraint.substr(1);
4450 
4451     switch (Constraint[0]) {
4452     default: break;
4453     case 'r': {
4454       switch (Modifier) {
4455       default:
4456         return (isInOut || isOutput || Size <= 64);
4457       case 'q':
4458         // A register of size 32 cannot fit a vector type.
4459         return false;
4460       }
4461     }
4462     }
4463 
4464     return true;
4465   }
4466   const char *getClobbers() const override {
4467     // FIXME: Is this really right?
4468     return "";
4469   }
4470 
4471   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4472     return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
4473   }
4474 
4475   int getEHDataRegisterNumber(unsigned RegNo) const override {
4476     if (RegNo == 0) return 0;
4477     if (RegNo == 1) return 1;
4478     return -1;
4479   }
4480 };
4481 
4482 bool ARMTargetInfo::setFPMath(StringRef Name) {
4483   if (Name == "neon") {
4484     FPMath = FP_Neon;
4485     return true;
4486   } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
4487              Name == "vfp4") {
4488     FPMath = FP_VFP;
4489     return true;
4490   }
4491   return false;
4492 }
4493 
4494 const char * const ARMTargetInfo::GCCRegNames[] = {
4495   // Integer registers
4496   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4497   "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
4498 
4499   // Float registers
4500   "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
4501   "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
4502   "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
4503   "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4504 
4505   // Double registers
4506   "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
4507   "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
4508   "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
4509   "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4510 
4511   // Quad registers
4512   "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
4513   "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
4514 };
4515 
4516 void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
4517                                    unsigned &NumNames) const {
4518   Names = GCCRegNames;
4519   NumNames = llvm::array_lengthof(GCCRegNames);
4520 }
4521 
4522 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
4523   { { "a1" }, "r0" },
4524   { { "a2" }, "r1" },
4525   { { "a3" }, "r2" },
4526   { { "a4" }, "r3" },
4527   { { "v1" }, "r4" },
4528   { { "v2" }, "r5" },
4529   { { "v3" }, "r6" },
4530   { { "v4" }, "r7" },
4531   { { "v5" }, "r8" },
4532   { { "v6", "rfp" }, "r9" },
4533   { { "sl" }, "r10" },
4534   { { "fp" }, "r11" },
4535   { { "ip" }, "r12" },
4536   { { "r13" }, "sp" },
4537   { { "r14" }, "lr" },
4538   { { "r15" }, "pc" },
4539   // The S, D and Q registers overlap, but aren't really aliases; we
4540   // don't want to substitute one of these for a different-sized one.
4541 };
4542 
4543 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4544                                        unsigned &NumAliases) const {
4545   Aliases = GCCRegAliases;
4546   NumAliases = llvm::array_lengthof(GCCRegAliases);
4547 }
4548 
4549 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
4550 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4551 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4552                                               ALL_LANGUAGES },
4553 #include "clang/Basic/BuiltinsNEON.def"
4554 
4555 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4556 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG },
4557 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4558                                               ALL_LANGUAGES },
4559 #include "clang/Basic/BuiltinsARM.def"
4560 };
4561 
4562 class ARMleTargetInfo : public ARMTargetInfo {
4563 public:
4564   ARMleTargetInfo(const llvm::Triple &Triple)
4565     : ARMTargetInfo(Triple, false) { }
4566   virtual void getTargetDefines(const LangOptions &Opts,
4567                                 MacroBuilder &Builder) const {
4568     Builder.defineMacro("__ARMEL__");
4569     ARMTargetInfo::getTargetDefines(Opts, Builder);
4570   }
4571 };
4572 
4573 class ARMbeTargetInfo : public ARMTargetInfo {
4574 public:
4575   ARMbeTargetInfo(const llvm::Triple &Triple)
4576     : ARMTargetInfo(Triple, true) { }
4577   virtual void getTargetDefines(const LangOptions &Opts,
4578                                 MacroBuilder &Builder) const {
4579     Builder.defineMacro("__ARMEB__");
4580     Builder.defineMacro("__ARM_BIG_ENDIAN");
4581     ARMTargetInfo::getTargetDefines(Opts, Builder);
4582   }
4583 };
4584 } // end anonymous namespace.
4585 
4586 namespace {
4587 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
4588   const llvm::Triple Triple;
4589 public:
4590   WindowsARMTargetInfo(const llvm::Triple &Triple)
4591     : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) {
4592     TLSSupported = false;
4593     WCharType = UnsignedShort;
4594     SizeType = UnsignedInt;
4595     UserLabelPrefix = "";
4596   }
4597   void getVisualStudioDefines(const LangOptions &Opts,
4598                               MacroBuilder &Builder) const {
4599     WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
4600 
4601     // FIXME: this is invalid for WindowsCE
4602     Builder.defineMacro("_M_ARM_NT", "1");
4603     Builder.defineMacro("_M_ARMT", "_M_ARM");
4604     Builder.defineMacro("_M_THUMB", "_M_ARM");
4605 
4606     assert((Triple.getArch() == llvm::Triple::arm ||
4607             Triple.getArch() == llvm::Triple::thumb) &&
4608            "invalid architecture for Windows ARM target info");
4609     unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
4610     Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
4611 
4612     // TODO map the complete set of values
4613     // 31: VFPv3 40: VFPv4
4614     Builder.defineMacro("_M_ARM_FP", "31");
4615   }
4616   BuiltinVaListKind getBuiltinVaListKind() const override {
4617     return TargetInfo::CharPtrBuiltinVaList;
4618   }
4619 };
4620 
4621 // Windows ARM + Itanium C++ ABI Target
4622 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
4623 public:
4624   ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple)
4625     : WindowsARMTargetInfo(Triple) {
4626     TheCXXABI.set(TargetCXXABI::GenericARM);
4627   }
4628 
4629   void getTargetDefines(const LangOptions &Opts,
4630                         MacroBuilder &Builder) const override {
4631     WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4632 
4633     if (Opts.MSVCCompat)
4634       WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4635   }
4636 };
4637 
4638 // Windows ARM, MS (C++) ABI
4639 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
4640 public:
4641   MicrosoftARMleTargetInfo(const llvm::Triple &Triple)
4642     : WindowsARMTargetInfo(Triple) {
4643     TheCXXABI.set(TargetCXXABI::Microsoft);
4644   }
4645 
4646   void getTargetDefines(const LangOptions &Opts,
4647                         MacroBuilder &Builder) const override {
4648     WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4649     WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4650   }
4651 };
4652 }
4653 
4654 
4655 namespace {
4656 class DarwinARMTargetInfo :
4657   public DarwinTargetInfo<ARMleTargetInfo> {
4658 protected:
4659   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4660                     MacroBuilder &Builder) const override {
4661     getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4662   }
4663 
4664 public:
4665   DarwinARMTargetInfo(const llvm::Triple &Triple)
4666       : DarwinTargetInfo<ARMleTargetInfo>(Triple) {
4667     HasAlignMac68kSupport = true;
4668     // iOS always has 64-bit atomic instructions.
4669     // FIXME: This should be based off of the target features in
4670     // ARMleTargetInfo.
4671     MaxAtomicInlineWidth = 64;
4672 
4673     // Darwin on iOS uses a variant of the ARM C++ ABI.
4674     TheCXXABI.set(TargetCXXABI::iOS);
4675   }
4676 };
4677 } // end anonymous namespace.
4678 
4679 
4680 namespace {
4681 class AArch64TargetInfo : public TargetInfo {
4682   virtual void setDescriptionString() = 0;
4683   static const TargetInfo::GCCRegAlias GCCRegAliases[];
4684   static const char *const GCCRegNames[];
4685 
4686   enum FPUModeEnum {
4687     FPUMode,
4688     NeonMode
4689   };
4690 
4691   unsigned FPU;
4692   unsigned CRC;
4693   unsigned Crypto;
4694 
4695   static const Builtin::Info BuiltinInfo[];
4696 
4697   std::string ABI;
4698 
4699 public:
4700   AArch64TargetInfo(const llvm::Triple &Triple)
4701       : TargetInfo(Triple), ABI("aapcs") {
4702 
4703     if (getTriple().getOS() == llvm::Triple::NetBSD) {
4704       WCharType = SignedInt;
4705 
4706       // NetBSD apparently prefers consistency across ARM targets to consistency
4707       // across 64-bit targets.
4708       Int64Type = SignedLongLong;
4709       IntMaxType = SignedLongLong;
4710     } else {
4711       WCharType = UnsignedInt;
4712       Int64Type = SignedLong;
4713       IntMaxType = SignedLong;
4714     }
4715 
4716     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4717     MaxVectorAlign = 128;
4718     RegParmMax = 8;
4719     MaxAtomicInlineWidth = 128;
4720     MaxAtomicPromoteWidth = 128;
4721 
4722     LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
4723     LongDoubleFormat = &llvm::APFloat::IEEEquad;
4724 
4725     // {} in inline assembly are neon specifiers, not assembly variant
4726     // specifiers.
4727     NoAsmVariants = true;
4728 
4729     // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
4730     // contributes to the alignment of the containing aggregate in the same way
4731     // a plain (non bit-field) member of that type would, without exception for
4732     // zero-sized or anonymous bit-fields."
4733     UseBitFieldTypeAlignment = true;
4734     UseZeroLengthBitfieldAlignment = true;
4735 
4736     // AArch64 targets default to using the ARM C++ ABI.
4737     TheCXXABI.set(TargetCXXABI::GenericAArch64);
4738   }
4739 
4740   StringRef getABI() const override { return ABI; }
4741   bool setABI(const std::string &Name) override {
4742     if (Name != "aapcs" && Name != "darwinpcs")
4743       return false;
4744 
4745     ABI = Name;
4746     return true;
4747   }
4748 
4749   bool setCPU(const std::string &Name) override {
4750     bool CPUKnown = llvm::StringSwitch<bool>(Name)
4751                         .Case("generic", true)
4752                         .Cases("cortex-a53", "cortex-a57", "cortex-a72", true)
4753                         .Case("cyclone", true)
4754                         .Default(false);
4755     return CPUKnown;
4756   }
4757 
4758   virtual void getTargetDefines(const LangOptions &Opts,
4759                                 MacroBuilder &Builder) const  override {
4760     // Target identification.
4761     Builder.defineMacro("__aarch64__");
4762 
4763     // Target properties.
4764     Builder.defineMacro("_LP64");
4765     Builder.defineMacro("__LP64__");
4766 
4767     // ACLE predefines. Many can only have one possible value on v8 AArch64.
4768     Builder.defineMacro("__ARM_ACLE", "200");
4769     Builder.defineMacro("__ARM_ARCH", "8");
4770     Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
4771 
4772     Builder.defineMacro("__ARM_64BIT_STATE");
4773     Builder.defineMacro("__ARM_PCS_AAPCS64");
4774     Builder.defineMacro("__ARM_ARCH_ISA_A64");
4775 
4776     Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
4777     Builder.defineMacro("__ARM_FEATURE_CLZ");
4778     Builder.defineMacro("__ARM_FEATURE_FMA");
4779     Builder.defineMacro("__ARM_FEATURE_DIV");
4780     Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE
4781     Builder.defineMacro("__ARM_FEATURE_DIV");  // For backwards compatibility
4782     Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4783     Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4784 
4785     Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
4786 
4787     // 0xe implies support for half, single and double precision operations.
4788     Builder.defineMacro("__ARM_FP", "0xe");
4789 
4790     // PCS specifies this for SysV variants, which is all we support. Other ABIs
4791     // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
4792     Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
4793 
4794     if (Opts.FastMath || Opts.FiniteMathOnly)
4795       Builder.defineMacro("__ARM_FP_FAST");
4796 
4797     if (Opts.C99 && !Opts.Freestanding)
4798       Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
4799 
4800     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
4801 
4802     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4803                         Opts.ShortEnums ? "1" : "4");
4804 
4805     if (FPU == NeonMode) {
4806       Builder.defineMacro("__ARM_NEON");
4807       // 64-bit NEON supports half, single and double precision operations.
4808       Builder.defineMacro("__ARM_NEON_FP", "0xe");
4809     }
4810 
4811     if (CRC)
4812       Builder.defineMacro("__ARM_FEATURE_CRC32");
4813 
4814     if (Crypto)
4815       Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4816   }
4817 
4818   virtual void getTargetBuiltins(const Builtin::Info *&Records,
4819                                  unsigned &NumRecords) const override {
4820     Records = BuiltinInfo;
4821     NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin;
4822   }
4823 
4824   bool hasFeature(StringRef Feature) const override {
4825     return Feature == "aarch64" ||
4826       Feature == "arm64" ||
4827       (Feature == "neon" && FPU == NeonMode);
4828   }
4829 
4830   bool handleTargetFeatures(std::vector<std::string> &Features,
4831                             DiagnosticsEngine &Diags) override {
4832     FPU = FPUMode;
4833     CRC = 0;
4834     Crypto = 0;
4835     for (unsigned i = 0, e = Features.size(); i != e; ++i) {
4836       if (Features[i] == "+neon")
4837         FPU = NeonMode;
4838       if (Features[i] == "+crc")
4839         CRC = 1;
4840       if (Features[i] == "+crypto")
4841         Crypto = 1;
4842     }
4843 
4844     setDescriptionString();
4845 
4846     return true;
4847   }
4848 
4849   bool isCLZForZeroUndef() const override { return false; }
4850 
4851   BuiltinVaListKind getBuiltinVaListKind() const override {
4852     return TargetInfo::AArch64ABIBuiltinVaList;
4853   }
4854 
4855   virtual void getGCCRegNames(const char *const *&Names,
4856                               unsigned &NumNames) const override;
4857   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4858                                 unsigned &NumAliases) const override;
4859 
4860   virtual bool
4861   validateAsmConstraint(const char *&Name,
4862                         TargetInfo::ConstraintInfo &Info) const override {
4863     switch (*Name) {
4864     default:
4865       return false;
4866     case 'w': // Floating point and SIMD registers (V0-V31)
4867       Info.setAllowsRegister();
4868       return true;
4869     case 'I': // Constant that can be used with an ADD instruction
4870     case 'J': // Constant that can be used with a SUB instruction
4871     case 'K': // Constant that can be used with a 32-bit logical instruction
4872     case 'L': // Constant that can be used with a 64-bit logical instruction
4873     case 'M': // Constant that can be used as a 32-bit MOV immediate
4874     case 'N': // Constant that can be used as a 64-bit MOV immediate
4875     case 'Y': // Floating point constant zero
4876     case 'Z': // Integer constant zero
4877       return true;
4878     case 'Q': // A memory reference with base register and no offset
4879       Info.setAllowsMemory();
4880       return true;
4881     case 'S': // A symbolic address
4882       Info.setAllowsRegister();
4883       return true;
4884     case 'U':
4885       // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
4886       // Utf: A memory address suitable for ldp/stp in TF mode.
4887       // Usa: An absolute symbolic address.
4888       // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
4889       llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
4890     case 'z': // Zero register, wzr or xzr
4891       Info.setAllowsRegister();
4892       return true;
4893     case 'x': // Floating point and SIMD registers (V0-V15)
4894       Info.setAllowsRegister();
4895       return true;
4896     }
4897     return false;
4898   }
4899 
4900   bool
4901   validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4902                              std::string &SuggestedModifier) const override {
4903     // Strip off constraint modifiers.
4904     while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
4905       Constraint = Constraint.substr(1);
4906 
4907     switch (Constraint[0]) {
4908     default:
4909       return true;
4910     case 'z':
4911     case 'r': {
4912       switch (Modifier) {
4913       case 'x':
4914       case 'w':
4915         // For now assume that the person knows what they're
4916         // doing with the modifier.
4917         return true;
4918       default:
4919         // By default an 'r' constraint will be in the 'x'
4920         // registers.
4921         if (Size == 64)
4922           return true;
4923 
4924         SuggestedModifier = "w";
4925         return false;
4926       }
4927     }
4928     }
4929   }
4930 
4931   const char *getClobbers() const override { return ""; }
4932 
4933   int getEHDataRegisterNumber(unsigned RegNo) const override {
4934     if (RegNo == 0)
4935       return 0;
4936     if (RegNo == 1)
4937       return 1;
4938     return -1;
4939   }
4940 };
4941 
4942 const char *const AArch64TargetInfo::GCCRegNames[] = {
4943   // 32-bit Integer registers
4944   "w0",  "w1",  "w2",  "w3",  "w4",  "w5",  "w6",  "w7",  "w8",  "w9",  "w10",
4945   "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
4946   "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
4947 
4948   // 64-bit Integer registers
4949   "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",  "x8",  "x9",  "x10",
4950   "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
4951   "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp",  "lr",  "sp",
4952 
4953   // 32-bit floating point regsisters
4954   "s0",  "s1",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",  "s8",  "s9",  "s10",
4955   "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
4956   "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4957 
4958   // 64-bit floating point regsisters
4959   "d0",  "d1",  "d2",  "d3",  "d4",  "d5",  "d6",  "d7",  "d8",  "d9",  "d10",
4960   "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
4961   "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4962 
4963   // Vector registers
4964   "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",  "v8",  "v9",  "v10",
4965   "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
4966   "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
4967 };
4968 
4969 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names,
4970                                      unsigned &NumNames) const {
4971   Names = GCCRegNames;
4972   NumNames = llvm::array_lengthof(GCCRegNames);
4973 }
4974 
4975 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
4976   { { "w31" }, "wsp" },
4977   { { "x29" }, "fp" },
4978   { { "x30" }, "lr" },
4979   { { "x31" }, "sp" },
4980   // The S/D/Q and W/X registers overlap, but aren't really aliases; we
4981   // don't want to substitute one of these for a different-sized one.
4982 };
4983 
4984 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4985                                        unsigned &NumAliases) const {
4986   Aliases = GCCRegAliases;
4987   NumAliases = llvm::array_lengthof(GCCRegAliases);
4988 }
4989 
4990 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
4991 #define BUILTIN(ID, TYPE, ATTRS)                                               \
4992   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4993 #include "clang/Basic/BuiltinsNEON.def"
4994 
4995 #define BUILTIN(ID, TYPE, ATTRS)                                               \
4996   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4997 #include "clang/Basic/BuiltinsAArch64.def"
4998 };
4999 
5000 class AArch64leTargetInfo : public AArch64TargetInfo {
5001   void setDescriptionString() override {
5002     if (getTriple().isOSBinFormatMachO())
5003       DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128";
5004     else
5005       DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128";
5006   }
5007 
5008 public:
5009   AArch64leTargetInfo(const llvm::Triple &Triple)
5010     : AArch64TargetInfo(Triple) {
5011     BigEndian = false;
5012     }
5013   void getTargetDefines(const LangOptions &Opts,
5014                         MacroBuilder &Builder) const override {
5015     Builder.defineMacro("__AARCH64EL__");
5016     AArch64TargetInfo::getTargetDefines(Opts, Builder);
5017   }
5018 };
5019 
5020 class AArch64beTargetInfo : public AArch64TargetInfo {
5021   void setDescriptionString() override {
5022     assert(!getTriple().isOSBinFormatMachO());
5023     DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128";
5024   }
5025 
5026 public:
5027   AArch64beTargetInfo(const llvm::Triple &Triple)
5028     : AArch64TargetInfo(Triple) { }
5029   void getTargetDefines(const LangOptions &Opts,
5030                         MacroBuilder &Builder) const override {
5031     Builder.defineMacro("__AARCH64EB__");
5032     Builder.defineMacro("__AARCH_BIG_ENDIAN");
5033     Builder.defineMacro("__ARM_BIG_ENDIAN");
5034     AArch64TargetInfo::getTargetDefines(Opts, Builder);
5035   }
5036 };
5037 } // end anonymous namespace.
5038 
5039 namespace {
5040 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
5041 protected:
5042   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
5043                     MacroBuilder &Builder) const override {
5044     Builder.defineMacro("__AARCH64_SIMD__");
5045     Builder.defineMacro("__ARM64_ARCH_8__");
5046     Builder.defineMacro("__ARM_NEON__");
5047     Builder.defineMacro("__LITTLE_ENDIAN__");
5048     Builder.defineMacro("__REGISTER_PREFIX__", "");
5049     Builder.defineMacro("__arm64", "1");
5050     Builder.defineMacro("__arm64__", "1");
5051 
5052     getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
5053   }
5054 
5055 public:
5056   DarwinAArch64TargetInfo(const llvm::Triple &Triple)
5057       : DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
5058     Int64Type = SignedLongLong;
5059     WCharType = SignedInt;
5060     UseSignedCharForObjCBool = false;
5061 
5062     LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
5063     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
5064 
5065     TheCXXABI.set(TargetCXXABI::iOS64);
5066   }
5067 
5068   BuiltinVaListKind getBuiltinVaListKind() const override {
5069     return TargetInfo::CharPtrBuiltinVaList;
5070   }
5071 };
5072 } // end anonymous namespace
5073 
5074 namespace {
5075 // Hexagon abstract base class
5076 class HexagonTargetInfo : public TargetInfo {
5077   static const Builtin::Info BuiltinInfo[];
5078   static const char * const GCCRegNames[];
5079   static const TargetInfo::GCCRegAlias GCCRegAliases[];
5080   std::string CPU;
5081 public:
5082   HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5083     BigEndian = false;
5084     DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32";
5085 
5086     // {} in inline assembly are packet specifiers, not assembly variant
5087     // specifiers.
5088     NoAsmVariants = true;
5089   }
5090 
5091   void getTargetBuiltins(const Builtin::Info *&Records,
5092                          unsigned &NumRecords) const override {
5093     Records = BuiltinInfo;
5094     NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
5095   }
5096 
5097   bool validateAsmConstraint(const char *&Name,
5098                              TargetInfo::ConstraintInfo &Info) const override {
5099     return true;
5100   }
5101 
5102   void getTargetDefines(const LangOptions &Opts,
5103                         MacroBuilder &Builder) const override;
5104 
5105   bool hasFeature(StringRef Feature) const override {
5106     return Feature == "hexagon";
5107   }
5108 
5109   BuiltinVaListKind getBuiltinVaListKind() const override {
5110     return TargetInfo::CharPtrBuiltinVaList;
5111   }
5112   void getGCCRegNames(const char * const *&Names,
5113                       unsigned &NumNames) const override;
5114   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5115                         unsigned &NumAliases) const override;
5116   const char *getClobbers() const override {
5117     return "";
5118   }
5119 
5120   static const char *getHexagonCPUSuffix(StringRef Name) {
5121     return llvm::StringSwitch<const char*>(Name)
5122       .Case("hexagonv4", "4")
5123       .Case("hexagonv5", "5")
5124       .Default(nullptr);
5125   }
5126 
5127   bool setCPU(const std::string &Name) override {
5128     if (!getHexagonCPUSuffix(Name))
5129       return false;
5130 
5131     CPU = Name;
5132     return true;
5133   }
5134 };
5135 
5136 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
5137                                 MacroBuilder &Builder) const {
5138   Builder.defineMacro("qdsp6");
5139   Builder.defineMacro("__qdsp6", "1");
5140   Builder.defineMacro("__qdsp6__", "1");
5141 
5142   Builder.defineMacro("hexagon");
5143   Builder.defineMacro("__hexagon", "1");
5144   Builder.defineMacro("__hexagon__", "1");
5145 
5146   if(CPU == "hexagonv1") {
5147     Builder.defineMacro("__HEXAGON_V1__");
5148     Builder.defineMacro("__HEXAGON_ARCH__", "1");
5149     if(Opts.HexagonQdsp6Compat) {
5150       Builder.defineMacro("__QDSP6_V1__");
5151       Builder.defineMacro("__QDSP6_ARCH__", "1");
5152     }
5153   }
5154   else if(CPU == "hexagonv2") {
5155     Builder.defineMacro("__HEXAGON_V2__");
5156     Builder.defineMacro("__HEXAGON_ARCH__", "2");
5157     if(Opts.HexagonQdsp6Compat) {
5158       Builder.defineMacro("__QDSP6_V2__");
5159       Builder.defineMacro("__QDSP6_ARCH__", "2");
5160     }
5161   }
5162   else if(CPU == "hexagonv3") {
5163     Builder.defineMacro("__HEXAGON_V3__");
5164     Builder.defineMacro("__HEXAGON_ARCH__", "3");
5165     if(Opts.HexagonQdsp6Compat) {
5166       Builder.defineMacro("__QDSP6_V3__");
5167       Builder.defineMacro("__QDSP6_ARCH__", "3");
5168     }
5169   }
5170   else if(CPU == "hexagonv4") {
5171     Builder.defineMacro("__HEXAGON_V4__");
5172     Builder.defineMacro("__HEXAGON_ARCH__", "4");
5173     if(Opts.HexagonQdsp6Compat) {
5174       Builder.defineMacro("__QDSP6_V4__");
5175       Builder.defineMacro("__QDSP6_ARCH__", "4");
5176     }
5177   }
5178   else if(CPU == "hexagonv5") {
5179     Builder.defineMacro("__HEXAGON_V5__");
5180     Builder.defineMacro("__HEXAGON_ARCH__", "5");
5181     if(Opts.HexagonQdsp6Compat) {
5182       Builder.defineMacro("__QDSP6_V5__");
5183       Builder.defineMacro("__QDSP6_ARCH__", "5");
5184     }
5185   }
5186 }
5187 
5188 const char * const HexagonTargetInfo::GCCRegNames[] = {
5189   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5190   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5191   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5192   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
5193   "p0", "p1", "p2", "p3",
5194   "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
5195 };
5196 
5197 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
5198                                    unsigned &NumNames) const {
5199   Names = GCCRegNames;
5200   NumNames = llvm::array_lengthof(GCCRegNames);
5201 }
5202 
5203 
5204 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
5205   { { "sp" }, "r29" },
5206   { { "fp" }, "r30" },
5207   { { "lr" }, "r31" },
5208  };
5209 
5210 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5211                                      unsigned &NumAliases) const {
5212   Aliases = GCCRegAliases;
5213   NumAliases = llvm::array_lengthof(GCCRegAliases);
5214 }
5215 
5216 
5217 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
5218 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5219 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5220                                               ALL_LANGUAGES },
5221 #include "clang/Basic/BuiltinsHexagon.def"
5222 };
5223 }
5224 
5225 
5226 namespace {
5227 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
5228 class SparcTargetInfo : public TargetInfo {
5229   static const TargetInfo::GCCRegAlias GCCRegAliases[];
5230   static const char * const GCCRegNames[];
5231   bool SoftFloat;
5232 public:
5233   SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {}
5234 
5235   bool handleTargetFeatures(std::vector<std::string> &Features,
5236                             DiagnosticsEngine &Diags) override {
5237     SoftFloat = false;
5238     for (unsigned i = 0, e = Features.size(); i != e; ++i)
5239       if (Features[i] == "+soft-float")
5240         SoftFloat = true;
5241     return true;
5242   }
5243   void getTargetDefines(const LangOptions &Opts,
5244                         MacroBuilder &Builder) const override {
5245     DefineStd(Builder, "sparc", Opts);
5246     Builder.defineMacro("__REGISTER_PREFIX__", "");
5247 
5248     if (SoftFloat)
5249       Builder.defineMacro("SOFT_FLOAT", "1");
5250   }
5251 
5252   bool hasFeature(StringRef Feature) const override {
5253     return llvm::StringSwitch<bool>(Feature)
5254              .Case("softfloat", SoftFloat)
5255              .Case("sparc", true)
5256              .Default(false);
5257   }
5258 
5259   void getTargetBuiltins(const Builtin::Info *&Records,
5260                          unsigned &NumRecords) const override {
5261     // FIXME: Implement!
5262   }
5263   BuiltinVaListKind getBuiltinVaListKind() const override {
5264     return TargetInfo::VoidPtrBuiltinVaList;
5265   }
5266   void getGCCRegNames(const char * const *&Names,
5267                       unsigned &NumNames) const override;
5268   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5269                         unsigned &NumAliases) const override;
5270   bool validateAsmConstraint(const char *&Name,
5271                              TargetInfo::ConstraintInfo &info) const override {
5272     // FIXME: Implement!
5273     switch (*Name) {
5274     case 'I': // Signed 13-bit constant
5275     case 'J': // Zero
5276     case 'K': // 32-bit constant with the low 12 bits clear
5277     case 'L': // A constant in the range supported by movcc (11-bit signed imm)
5278     case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
5279     case 'N': // Same as 'K' but zext (required for SIMode)
5280     case 'O': // The constant 4096
5281       return true;
5282     }
5283     return false;
5284   }
5285   const char *getClobbers() const override {
5286     // FIXME: Implement!
5287     return "";
5288   }
5289 };
5290 
5291 const char * const SparcTargetInfo::GCCRegNames[] = {
5292   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5293   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5294   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5295   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5296 };
5297 
5298 void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
5299                                      unsigned &NumNames) const {
5300   Names = GCCRegNames;
5301   NumNames = llvm::array_lengthof(GCCRegNames);
5302 }
5303 
5304 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
5305   { { "g0" }, "r0" },
5306   { { "g1" }, "r1" },
5307   { { "g2" }, "r2" },
5308   { { "g3" }, "r3" },
5309   { { "g4" }, "r4" },
5310   { { "g5" }, "r5" },
5311   { { "g6" }, "r6" },
5312   { { "g7" }, "r7" },
5313   { { "o0" }, "r8" },
5314   { { "o1" }, "r9" },
5315   { { "o2" }, "r10" },
5316   { { "o3" }, "r11" },
5317   { { "o4" }, "r12" },
5318   { { "o5" }, "r13" },
5319   { { "o6", "sp" }, "r14" },
5320   { { "o7" }, "r15" },
5321   { { "l0" }, "r16" },
5322   { { "l1" }, "r17" },
5323   { { "l2" }, "r18" },
5324   { { "l3" }, "r19" },
5325   { { "l4" }, "r20" },
5326   { { "l5" }, "r21" },
5327   { { "l6" }, "r22" },
5328   { { "l7" }, "r23" },
5329   { { "i0" }, "r24" },
5330   { { "i1" }, "r25" },
5331   { { "i2" }, "r26" },
5332   { { "i3" }, "r27" },
5333   { { "i4" }, "r28" },
5334   { { "i5" }, "r29" },
5335   { { "i6", "fp" }, "r30" },
5336   { { "i7" }, "r31" },
5337 };
5338 
5339 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5340                                        unsigned &NumAliases) const {
5341   Aliases = GCCRegAliases;
5342   NumAliases = llvm::array_lengthof(GCCRegAliases);
5343 }
5344 
5345 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
5346 class SparcV8TargetInfo : public SparcTargetInfo {
5347 public:
5348   SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5349     DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
5350   }
5351 
5352   void getTargetDefines(const LangOptions &Opts,
5353                         MacroBuilder &Builder) const override {
5354     SparcTargetInfo::getTargetDefines(Opts, Builder);
5355     Builder.defineMacro("__sparcv8");
5356   }
5357 };
5358 
5359 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
5360 class SparcV9TargetInfo : public SparcTargetInfo {
5361 public:
5362   SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5363     // FIXME: Support Sparc quad-precision long double?
5364     DescriptionString = "E-m:e-i64:64-n32:64-S128";
5365     // This is an LP64 platform.
5366     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5367 
5368     // OpenBSD uses long long for int64_t and intmax_t.
5369     if (getTriple().getOS() == llvm::Triple::OpenBSD)
5370       IntMaxType = SignedLongLong;
5371     else
5372       IntMaxType = SignedLong;
5373     Int64Type = IntMaxType;
5374 
5375     // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
5376     // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
5377     LongDoubleWidth = 128;
5378     LongDoubleAlign = 128;
5379     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5380     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5381   }
5382 
5383   void getTargetDefines(const LangOptions &Opts,
5384                         MacroBuilder &Builder) const override {
5385     SparcTargetInfo::getTargetDefines(Opts, Builder);
5386     Builder.defineMacro("__sparcv9");
5387     Builder.defineMacro("__arch64__");
5388     // Solaris doesn't need these variants, but the BSDs do.
5389     if (getTriple().getOS() != llvm::Triple::Solaris) {
5390       Builder.defineMacro("__sparc64__");
5391       Builder.defineMacro("__sparc_v9__");
5392       Builder.defineMacro("__sparcv9__");
5393     }
5394   }
5395 
5396   bool setCPU(const std::string &Name) override {
5397     bool CPUKnown = llvm::StringSwitch<bool>(Name)
5398       .Case("v9", true)
5399       .Case("ultrasparc", true)
5400       .Case("ultrasparc3", true)
5401       .Case("niagara", true)
5402       .Case("niagara2", true)
5403       .Case("niagara3", true)
5404       .Case("niagara4", true)
5405       .Default(false);
5406 
5407     // No need to store the CPU yet.  There aren't any CPU-specific
5408     // macros to define.
5409     return CPUKnown;
5410   }
5411 };
5412 
5413 } // end anonymous namespace.
5414 
5415 namespace {
5416 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
5417 public:
5418   SolarisSparcV8TargetInfo(const llvm::Triple &Triple)
5419       : SolarisTargetInfo<SparcV8TargetInfo>(Triple) {
5420     SizeType = UnsignedInt;
5421     PtrDiffType = SignedInt;
5422   }
5423 };
5424 } // end anonymous namespace.
5425 
5426 namespace {
5427 class SystemZTargetInfo : public TargetInfo {
5428   static const char *const GCCRegNames[];
5429 
5430 public:
5431   SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5432     TLSSupported = true;
5433     IntWidth = IntAlign = 32;
5434     LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
5435     PointerWidth = PointerAlign = 64;
5436     LongDoubleWidth = 128;
5437     LongDoubleAlign = 64;
5438     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5439     MinGlobalAlign = 16;
5440     DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
5441     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5442   }
5443   void getTargetDefines(const LangOptions &Opts,
5444                         MacroBuilder &Builder) const override {
5445     Builder.defineMacro("__s390__");
5446     Builder.defineMacro("__s390x__");
5447     Builder.defineMacro("__zarch__");
5448     Builder.defineMacro("__LONG_DOUBLE_128__");
5449   }
5450   void getTargetBuiltins(const Builtin::Info *&Records,
5451                          unsigned &NumRecords) const override {
5452     // FIXME: Implement.
5453     Records = nullptr;
5454     NumRecords = 0;
5455   }
5456 
5457   void getGCCRegNames(const char *const *&Names,
5458                       unsigned &NumNames) const override;
5459   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5460                         unsigned &NumAliases) const override {
5461     // No aliases.
5462     Aliases = nullptr;
5463     NumAliases = 0;
5464   }
5465   bool validateAsmConstraint(const char *&Name,
5466                              TargetInfo::ConstraintInfo &info) const override;
5467   const char *getClobbers() const override {
5468     // FIXME: Is this really right?
5469     return "";
5470   }
5471   BuiltinVaListKind getBuiltinVaListKind() const override {
5472     return TargetInfo::SystemZBuiltinVaList;
5473   }
5474   bool setCPU(const std::string &Name) override {
5475     bool CPUKnown = llvm::StringSwitch<bool>(Name)
5476       .Case("z10", true)
5477       .Case("z196", true)
5478       .Case("zEC12", true)
5479       .Default(false);
5480 
5481     // No need to store the CPU yet.  There aren't any CPU-specific
5482     // macros to define.
5483     return CPUKnown;
5484   }
5485 };
5486 
5487 const char *const SystemZTargetInfo::GCCRegNames[] = {
5488   "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
5489   "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
5490   "f0",  "f2",  "f4",  "f6",  "f1",  "f3",  "f5",  "f7",
5491   "f8",  "f10", "f12", "f14", "f9",  "f11", "f13", "f15"
5492 };
5493 
5494 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
5495                                        unsigned &NumNames) const {
5496   Names = GCCRegNames;
5497   NumNames = llvm::array_lengthof(GCCRegNames);
5498 }
5499 
5500 bool SystemZTargetInfo::
5501 validateAsmConstraint(const char *&Name,
5502                       TargetInfo::ConstraintInfo &Info) const {
5503   switch (*Name) {
5504   default:
5505     return false;
5506 
5507   case 'a': // Address register
5508   case 'd': // Data register (equivalent to 'r')
5509   case 'f': // Floating-point register
5510     Info.setAllowsRegister();
5511     return true;
5512 
5513   case 'I': // Unsigned 8-bit constant
5514   case 'J': // Unsigned 12-bit constant
5515   case 'K': // Signed 16-bit constant
5516   case 'L': // Signed 20-bit displacement (on all targets we support)
5517   case 'M': // 0x7fffffff
5518     return true;
5519 
5520   case 'Q': // Memory with base and unsigned 12-bit displacement
5521   case 'R': // Likewise, plus an index
5522   case 'S': // Memory with base and signed 20-bit displacement
5523   case 'T': // Likewise, plus an index
5524     Info.setAllowsMemory();
5525     return true;
5526   }
5527 }
5528 }
5529 
5530 namespace {
5531   class MSP430TargetInfo : public TargetInfo {
5532     static const char * const GCCRegNames[];
5533   public:
5534     MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5535       BigEndian = false;
5536       TLSSupported = false;
5537       IntWidth = 16; IntAlign = 16;
5538       LongWidth = 32; LongLongWidth = 64;
5539       LongAlign = LongLongAlign = 16;
5540       PointerWidth = 16; PointerAlign = 16;
5541       SuitableAlign = 16;
5542       SizeType = UnsignedInt;
5543       IntMaxType = SignedLongLong;
5544       IntPtrType = SignedInt;
5545       PtrDiffType = SignedInt;
5546       SigAtomicType = SignedLong;
5547       DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16";
5548     }
5549     void getTargetDefines(const LangOptions &Opts,
5550                           MacroBuilder &Builder) const override {
5551       Builder.defineMacro("MSP430");
5552       Builder.defineMacro("__MSP430__");
5553       // FIXME: defines for different 'flavours' of MCU
5554     }
5555     void getTargetBuiltins(const Builtin::Info *&Records,
5556                            unsigned &NumRecords) const override {
5557       // FIXME: Implement.
5558       Records = nullptr;
5559       NumRecords = 0;
5560     }
5561     bool hasFeature(StringRef Feature) const override {
5562       return Feature == "msp430";
5563     }
5564     void getGCCRegNames(const char * const *&Names,
5565                         unsigned &NumNames) const override;
5566     void getGCCRegAliases(const GCCRegAlias *&Aliases,
5567                           unsigned &NumAliases) const override {
5568       // No aliases.
5569       Aliases = nullptr;
5570       NumAliases = 0;
5571     }
5572     bool
5573     validateAsmConstraint(const char *&Name,
5574                           TargetInfo::ConstraintInfo &info) const override {
5575       // FIXME: implement
5576       switch (*Name) {
5577       case 'K': // the constant 1
5578       case 'L': // constant -1^20 .. 1^19
5579       case 'M': // constant 1-4:
5580         return true;
5581       }
5582       // No target constraints for now.
5583       return false;
5584     }
5585     const char *getClobbers() const override {
5586       // FIXME: Is this really right?
5587       return "";
5588     }
5589     BuiltinVaListKind getBuiltinVaListKind() const override {
5590       // FIXME: implement
5591       return TargetInfo::CharPtrBuiltinVaList;
5592    }
5593   };
5594 
5595   const char * const MSP430TargetInfo::GCCRegNames[] = {
5596     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5597     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5598   };
5599 
5600   void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
5601                                         unsigned &NumNames) const {
5602     Names = GCCRegNames;
5603     NumNames = llvm::array_lengthof(GCCRegNames);
5604   }
5605 }
5606 
5607 namespace {
5608 
5609   // LLVM and Clang cannot be used directly to output native binaries for
5610   // target, but is used to compile C code to llvm bitcode with correct
5611   // type and alignment information.
5612   //
5613   // TCE uses the llvm bitcode as input and uses it for generating customized
5614   // target processor and program binary. TCE co-design environment is
5615   // publicly available in http://tce.cs.tut.fi
5616 
5617   static const unsigned TCEOpenCLAddrSpaceMap[] = {
5618       3, // opencl_global
5619       4, // opencl_local
5620       5, // opencl_constant
5621       // FIXME: generic has to be added to the target
5622       0, // opencl_generic
5623       0, // cuda_device
5624       0, // cuda_constant
5625       0  // cuda_shared
5626   };
5627 
5628   class TCETargetInfo : public TargetInfo{
5629   public:
5630     TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5631       TLSSupported = false;
5632       IntWidth = 32;
5633       LongWidth = LongLongWidth = 32;
5634       PointerWidth = 32;
5635       IntAlign = 32;
5636       LongAlign = LongLongAlign = 32;
5637       PointerAlign = 32;
5638       SuitableAlign = 32;
5639       SizeType = UnsignedInt;
5640       IntMaxType = SignedLong;
5641       IntPtrType = SignedInt;
5642       PtrDiffType = SignedInt;
5643       FloatWidth = 32;
5644       FloatAlign = 32;
5645       DoubleWidth = 32;
5646       DoubleAlign = 32;
5647       LongDoubleWidth = 32;
5648       LongDoubleAlign = 32;
5649       FloatFormat = &llvm::APFloat::IEEEsingle;
5650       DoubleFormat = &llvm::APFloat::IEEEsingle;
5651       LongDoubleFormat = &llvm::APFloat::IEEEsingle;
5652       DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32"
5653                           "-f64:32-v64:32-v128:32-a:0:32-n32";
5654       AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
5655       UseAddrSpaceMapMangling = true;
5656     }
5657 
5658     void getTargetDefines(const LangOptions &Opts,
5659                           MacroBuilder &Builder) const override {
5660       DefineStd(Builder, "tce", Opts);
5661       Builder.defineMacro("__TCE__");
5662       Builder.defineMacro("__TCE_V1__");
5663     }
5664     bool hasFeature(StringRef Feature) const override {
5665       return Feature == "tce";
5666     }
5667 
5668     void getTargetBuiltins(const Builtin::Info *&Records,
5669                            unsigned &NumRecords) const override {}
5670     const char *getClobbers() const override {
5671       return "";
5672     }
5673     BuiltinVaListKind getBuiltinVaListKind() const override {
5674       return TargetInfo::VoidPtrBuiltinVaList;
5675     }
5676     void getGCCRegNames(const char * const *&Names,
5677                         unsigned &NumNames) const override {}
5678     bool validateAsmConstraint(const char *&Name,
5679                                TargetInfo::ConstraintInfo &info) const override{
5680       return true;
5681     }
5682     void getGCCRegAliases(const GCCRegAlias *&Aliases,
5683                           unsigned &NumAliases) const override {}
5684   };
5685 }
5686 
5687 namespace {
5688 class MipsTargetInfoBase : public TargetInfo {
5689   virtual void setDescriptionString() = 0;
5690 
5691   static const Builtin::Info BuiltinInfo[];
5692   std::string CPU;
5693   bool IsMips16;
5694   bool IsMicromips;
5695   bool IsNan2008;
5696   bool IsSingleFloat;
5697   enum MipsFloatABI {
5698     HardFloat, SoftFloat
5699   } FloatABI;
5700   enum DspRevEnum {
5701     NoDSP, DSP1, DSP2
5702   } DspRev;
5703   bool HasMSA;
5704 
5705 protected:
5706   bool HasFP64;
5707   std::string ABI;
5708 
5709 public:
5710   MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
5711                      const std::string &CPUStr)
5712       : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
5713         IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
5714         DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {
5715     TheCXXABI.set(TargetCXXABI::GenericMIPS);
5716   }
5717 
5718   bool isNaN2008Default() const {
5719     return CPU == "mips32r6" || CPU == "mips64r6";
5720   }
5721 
5722   bool isFP64Default() const {
5723     return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
5724   }
5725 
5726   bool isNan2008() const override {
5727     return IsNan2008;
5728   }
5729 
5730   StringRef getABI() const override { return ABI; }
5731   bool setCPU(const std::string &Name) override {
5732     bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
5733                     getTriple().getArch() == llvm::Triple::mipsel;
5734     CPU = Name;
5735     return llvm::StringSwitch<bool>(Name)
5736         .Case("mips1", IsMips32)
5737         .Case("mips2", IsMips32)
5738         .Case("mips3", true)
5739         .Case("mips4", true)
5740         .Case("mips5", true)
5741         .Case("mips32", IsMips32)
5742         .Case("mips32r2", IsMips32)
5743         .Case("mips32r3", IsMips32)
5744         .Case("mips32r5", IsMips32)
5745         .Case("mips32r6", IsMips32)
5746         .Case("mips64", true)
5747         .Case("mips64r2", true)
5748         .Case("mips64r3", true)
5749         .Case("mips64r5", true)
5750         .Case("mips64r6", true)
5751         .Case("octeon", true)
5752         .Default(false);
5753   }
5754   const std::string& getCPU() const { return CPU; }
5755   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
5756     if (CPU == "octeon")
5757       Features["mips64r2"] = Features["cnmips"] = true;
5758     else
5759       Features[CPU] = true;
5760   }
5761 
5762   void getTargetDefines(const LangOptions &Opts,
5763                         MacroBuilder &Builder) const override {
5764     Builder.defineMacro("__mips__");
5765     Builder.defineMacro("_mips");
5766     if (Opts.GNUMode)
5767       Builder.defineMacro("mips");
5768 
5769     Builder.defineMacro("__REGISTER_PREFIX__", "");
5770 
5771     switch (FloatABI) {
5772     case HardFloat:
5773       Builder.defineMacro("__mips_hard_float", Twine(1));
5774       break;
5775     case SoftFloat:
5776       Builder.defineMacro("__mips_soft_float", Twine(1));
5777       break;
5778     }
5779 
5780     if (IsSingleFloat)
5781       Builder.defineMacro("__mips_single_float", Twine(1));
5782 
5783     Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
5784     Builder.defineMacro("_MIPS_FPSET",
5785                         Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
5786 
5787     if (IsMips16)
5788       Builder.defineMacro("__mips16", Twine(1));
5789 
5790     if (IsMicromips)
5791       Builder.defineMacro("__mips_micromips", Twine(1));
5792 
5793     if (IsNan2008)
5794       Builder.defineMacro("__mips_nan2008", Twine(1));
5795 
5796     switch (DspRev) {
5797     default:
5798       break;
5799     case DSP1:
5800       Builder.defineMacro("__mips_dsp_rev", Twine(1));
5801       Builder.defineMacro("__mips_dsp", Twine(1));
5802       break;
5803     case DSP2:
5804       Builder.defineMacro("__mips_dsp_rev", Twine(2));
5805       Builder.defineMacro("__mips_dspr2", Twine(1));
5806       Builder.defineMacro("__mips_dsp", Twine(1));
5807       break;
5808     }
5809 
5810     if (HasMSA)
5811       Builder.defineMacro("__mips_msa", Twine(1));
5812 
5813     Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
5814     Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
5815     Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
5816 
5817     Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
5818     Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
5819   }
5820 
5821   void getTargetBuiltins(const Builtin::Info *&Records,
5822                          unsigned &NumRecords) const override {
5823     Records = BuiltinInfo;
5824     NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
5825   }
5826   bool hasFeature(StringRef Feature) const override {
5827     return llvm::StringSwitch<bool>(Feature)
5828       .Case("mips", true)
5829       .Case("fp64", HasFP64)
5830       .Default(false);
5831   }
5832   BuiltinVaListKind getBuiltinVaListKind() const override {
5833     return TargetInfo::VoidPtrBuiltinVaList;
5834   }
5835   void getGCCRegNames(const char * const *&Names,
5836                       unsigned &NumNames) const override {
5837     static const char *const GCCRegNames[] = {
5838       // CPU register names
5839       // Must match second column of GCCRegAliases
5840       "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
5841       "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
5842       "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
5843       "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
5844       // Floating point register names
5845       "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
5846       "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
5847       "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
5848       "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
5849       // Hi/lo and condition register names
5850       "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
5851       "$fcc5","$fcc6","$fcc7",
5852       // MSA register names
5853       "$w0",  "$w1",  "$w2",  "$w3",  "$w4",  "$w5",  "$w6",  "$w7",
5854       "$w8",  "$w9",  "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
5855       "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
5856       "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
5857       // MSA control register names
5858       "$msair",      "$msacsr", "$msaaccess", "$msasave", "$msamodify",
5859       "$msarequest", "$msamap", "$msaunmap"
5860     };
5861     Names = GCCRegNames;
5862     NumNames = llvm::array_lengthof(GCCRegNames);
5863   }
5864   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5865                         unsigned &NumAliases) const override = 0;
5866   bool validateAsmConstraint(const char *&Name,
5867                              TargetInfo::ConstraintInfo &Info) const override {
5868     switch (*Name) {
5869     default:
5870       return false;
5871     case 'r': // CPU registers.
5872     case 'd': // Equivalent to "r" unless generating MIPS16 code.
5873     case 'y': // Equivalent to "r", backward compatibility only.
5874     case 'f': // floating-point registers.
5875     case 'c': // $25 for indirect jumps
5876     case 'l': // lo register
5877     case 'x': // hilo register pair
5878       Info.setAllowsRegister();
5879       return true;
5880     case 'I': // Signed 16-bit constant
5881     case 'J': // Integer 0
5882     case 'K': // Unsigned 16-bit constant
5883     case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
5884     case 'M': // Constants not loadable via lui, addiu, or ori
5885     case 'N': // Constant -1 to -65535
5886     case 'O': // A signed 15-bit constant
5887     case 'P': // A constant between 1 go 65535
5888       return true;
5889     case 'R': // An address that can be used in a non-macro load or store
5890       Info.setAllowsMemory();
5891       return true;
5892     }
5893   }
5894 
5895   const char *getClobbers() const override {
5896     // In GCC, $1 is not widely used in generated code (it's used only in a few
5897     // specific situations), so there is no real need for users to add it to
5898     // the clobbers list if they want to use it in their inline assembly code.
5899     //
5900     // In LLVM, $1 is treated as a normal GPR and is always allocatable during
5901     // code generation, so using it in inline assembly without adding it to the
5902     // clobbers list can cause conflicts between the inline assembly code and
5903     // the surrounding generated code.
5904     //
5905     // Another problem is that LLVM is allowed to choose $1 for inline assembly
5906     // operands, which will conflict with the ".set at" assembler option (which
5907     // we use only for inline assembly, in order to maintain compatibility with
5908     // GCC) and will also conflict with the user's usage of $1.
5909     //
5910     // The easiest way to avoid these conflicts and keep $1 as an allocatable
5911     // register for generated code is to automatically clobber $1 for all inline
5912     // assembly code.
5913     //
5914     // FIXME: We should automatically clobber $1 only for inline assembly code
5915     // which actually uses it. This would allow LLVM to use $1 for inline
5916     // assembly operands if the user's assembly code doesn't use it.
5917     return "~{$1}";
5918   }
5919 
5920   bool handleTargetFeatures(std::vector<std::string> &Features,
5921                             DiagnosticsEngine &Diags) override {
5922     IsMips16 = false;
5923     IsMicromips = false;
5924     IsNan2008 = isNaN2008Default();
5925     IsSingleFloat = false;
5926     FloatABI = HardFloat;
5927     DspRev = NoDSP;
5928     HasFP64 = isFP64Default();
5929 
5930     for (std::vector<std::string>::iterator it = Features.begin(),
5931          ie = Features.end(); it != ie; ++it) {
5932       if (*it == "+single-float")
5933         IsSingleFloat = true;
5934       else if (*it == "+soft-float")
5935         FloatABI = SoftFloat;
5936       else if (*it == "+mips16")
5937         IsMips16 = true;
5938       else if (*it == "+micromips")
5939         IsMicromips = true;
5940       else if (*it == "+dsp")
5941         DspRev = std::max(DspRev, DSP1);
5942       else if (*it == "+dspr2")
5943         DspRev = std::max(DspRev, DSP2);
5944       else if (*it == "+msa")
5945         HasMSA = true;
5946       else if (*it == "+fp64")
5947         HasFP64 = true;
5948       else if (*it == "-fp64")
5949         HasFP64 = false;
5950       else if (*it == "+nan2008")
5951         IsNan2008 = true;
5952       else if (*it == "-nan2008")
5953         IsNan2008 = false;
5954     }
5955 
5956     // Remove front-end specific options.
5957     std::vector<std::string>::iterator it =
5958       std::find(Features.begin(), Features.end(), "+soft-float");
5959     if (it != Features.end())
5960       Features.erase(it);
5961 
5962     setDescriptionString();
5963 
5964     return true;
5965   }
5966 
5967   int getEHDataRegisterNumber(unsigned RegNo) const override {
5968     if (RegNo == 0) return 4;
5969     if (RegNo == 1) return 5;
5970     return -1;
5971   }
5972 
5973   bool isCLZForZeroUndef() const override { return false; }
5974 };
5975 
5976 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
5977 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5978 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5979                                               ALL_LANGUAGES },
5980 #include "clang/Basic/BuiltinsMips.def"
5981 };
5982 
5983 class Mips32TargetInfoBase : public MipsTargetInfoBase {
5984 public:
5985   Mips32TargetInfoBase(const llvm::Triple &Triple)
5986       : MipsTargetInfoBase(Triple, "o32", "mips32r2") {
5987     SizeType = UnsignedInt;
5988     PtrDiffType = SignedInt;
5989     Int64Type = SignedLongLong;
5990     IntMaxType = Int64Type;
5991     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
5992   }
5993   bool setABI(const std::string &Name) override {
5994     if (Name == "o32" || Name == "eabi") {
5995       ABI = Name;
5996       return true;
5997     }
5998     return false;
5999   }
6000   void getTargetDefines(const LangOptions &Opts,
6001                         MacroBuilder &Builder) const override {
6002     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6003 
6004     Builder.defineMacro("__mips", "32");
6005     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
6006 
6007     const std::string& CPUStr = getCPU();
6008     if (CPUStr == "mips32")
6009       Builder.defineMacro("__mips_isa_rev", "1");
6010     else if (CPUStr == "mips32r2")
6011       Builder.defineMacro("__mips_isa_rev", "2");
6012     else if (CPUStr == "mips32r3")
6013       Builder.defineMacro("__mips_isa_rev", "3");
6014     else if (CPUStr == "mips32r5")
6015       Builder.defineMacro("__mips_isa_rev", "5");
6016     else if (CPUStr == "mips32r6")
6017       Builder.defineMacro("__mips_isa_rev", "6");
6018 
6019     if (ABI == "o32") {
6020       Builder.defineMacro("__mips_o32");
6021       Builder.defineMacro("_ABIO32", "1");
6022       Builder.defineMacro("_MIPS_SIM", "_ABIO32");
6023     }
6024     else if (ABI == "eabi")
6025       Builder.defineMacro("__mips_eabi");
6026     else
6027       llvm_unreachable("Invalid ABI for Mips32.");
6028   }
6029   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6030                         unsigned &NumAliases) const override {
6031     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6032       { { "at" },  "$1" },
6033       { { "v0" },  "$2" },
6034       { { "v1" },  "$3" },
6035       { { "a0" },  "$4" },
6036       { { "a1" },  "$5" },
6037       { { "a2" },  "$6" },
6038       { { "a3" },  "$7" },
6039       { { "t0" },  "$8" },
6040       { { "t1" },  "$9" },
6041       { { "t2" }, "$10" },
6042       { { "t3" }, "$11" },
6043       { { "t4" }, "$12" },
6044       { { "t5" }, "$13" },
6045       { { "t6" }, "$14" },
6046       { { "t7" }, "$15" },
6047       { { "s0" }, "$16" },
6048       { { "s1" }, "$17" },
6049       { { "s2" }, "$18" },
6050       { { "s3" }, "$19" },
6051       { { "s4" }, "$20" },
6052       { { "s5" }, "$21" },
6053       { { "s6" }, "$22" },
6054       { { "s7" }, "$23" },
6055       { { "t8" }, "$24" },
6056       { { "t9" }, "$25" },
6057       { { "k0" }, "$26" },
6058       { { "k1" }, "$27" },
6059       { { "gp" }, "$28" },
6060       { { "sp","$sp" }, "$29" },
6061       { { "fp","$fp" }, "$30" },
6062       { { "ra" }, "$31" }
6063     };
6064     Aliases = GCCRegAliases;
6065     NumAliases = llvm::array_lengthof(GCCRegAliases);
6066   }
6067 };
6068 
6069 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
6070   void setDescriptionString() override {
6071     DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6072   }
6073 
6074 public:
6075   Mips32EBTargetInfo(const llvm::Triple &Triple)
6076       : Mips32TargetInfoBase(Triple) {
6077   }
6078   void getTargetDefines(const LangOptions &Opts,
6079                         MacroBuilder &Builder) const override {
6080     DefineStd(Builder, "MIPSEB", Opts);
6081     Builder.defineMacro("_MIPSEB");
6082     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6083   }
6084 };
6085 
6086 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
6087   void setDescriptionString() override {
6088     DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6089   }
6090 
6091 public:
6092   Mips32ELTargetInfo(const llvm::Triple &Triple)
6093       : Mips32TargetInfoBase(Triple) {
6094     BigEndian = false;
6095   }
6096   void getTargetDefines(const LangOptions &Opts,
6097                         MacroBuilder &Builder) const override {
6098     DefineStd(Builder, "MIPSEL", Opts);
6099     Builder.defineMacro("_MIPSEL");
6100     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6101   }
6102 };
6103 
6104 class Mips64TargetInfoBase : public MipsTargetInfoBase {
6105 public:
6106   Mips64TargetInfoBase(const llvm::Triple &Triple)
6107       : MipsTargetInfoBase(Triple, "n64", "mips64r2") {
6108     LongDoubleWidth = LongDoubleAlign = 128;
6109     LongDoubleFormat = &llvm::APFloat::IEEEquad;
6110     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
6111       LongDoubleWidth = LongDoubleAlign = 64;
6112       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
6113     }
6114     setN64ABITypes();
6115     SuitableAlign = 128;
6116     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6117   }
6118 
6119   void setN64ABITypes() {
6120     LongWidth = LongAlign = 64;
6121     PointerWidth = PointerAlign = 64;
6122     SizeType = UnsignedLong;
6123     PtrDiffType = SignedLong;
6124     Int64Type = SignedLong;
6125     IntMaxType = Int64Type;
6126   }
6127 
6128   void setN32ABITypes() {
6129     LongWidth = LongAlign = 32;
6130     PointerWidth = PointerAlign = 32;
6131     SizeType = UnsignedInt;
6132     PtrDiffType = SignedInt;
6133     Int64Type = SignedLongLong;
6134     IntMaxType = Int64Type;
6135   }
6136 
6137   bool setABI(const std::string &Name) override {
6138     if (Name == "n32") {
6139       setN32ABITypes();
6140       ABI = Name;
6141       return true;
6142     }
6143     if (Name == "n64") {
6144       setN64ABITypes();
6145       ABI = Name;
6146       return true;
6147     }
6148     return false;
6149   }
6150 
6151   void getTargetDefines(const LangOptions &Opts,
6152                         MacroBuilder &Builder) const override {
6153     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6154 
6155     Builder.defineMacro("__mips", "64");
6156     Builder.defineMacro("__mips64");
6157     Builder.defineMacro("__mips64__");
6158     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
6159 
6160     const std::string& CPUStr = getCPU();
6161     if (CPUStr == "mips64")
6162       Builder.defineMacro("__mips_isa_rev", "1");
6163     else if (CPUStr == "mips64r2")
6164       Builder.defineMacro("__mips_isa_rev", "2");
6165     else if (CPUStr == "mips64r3")
6166       Builder.defineMacro("__mips_isa_rev", "3");
6167     else if (CPUStr == "mips64r5")
6168       Builder.defineMacro("__mips_isa_rev", "5");
6169     else if (CPUStr == "mips64r6")
6170       Builder.defineMacro("__mips_isa_rev", "6");
6171 
6172     if (ABI == "n32") {
6173       Builder.defineMacro("__mips_n32");
6174       Builder.defineMacro("_ABIN32", "2");
6175       Builder.defineMacro("_MIPS_SIM", "_ABIN32");
6176     }
6177     else if (ABI == "n64") {
6178       Builder.defineMacro("__mips_n64");
6179       Builder.defineMacro("_ABI64", "3");
6180       Builder.defineMacro("_MIPS_SIM", "_ABI64");
6181     }
6182     else
6183       llvm_unreachable("Invalid ABI for Mips64.");
6184   }
6185   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6186                         unsigned &NumAliases) const override {
6187     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6188       { { "at" },  "$1" },
6189       { { "v0" },  "$2" },
6190       { { "v1" },  "$3" },
6191       { { "a0" },  "$4" },
6192       { { "a1" },  "$5" },
6193       { { "a2" },  "$6" },
6194       { { "a3" },  "$7" },
6195       { { "a4" },  "$8" },
6196       { { "a5" },  "$9" },
6197       { { "a6" }, "$10" },
6198       { { "a7" }, "$11" },
6199       { { "t0" }, "$12" },
6200       { { "t1" }, "$13" },
6201       { { "t2" }, "$14" },
6202       { { "t3" }, "$15" },
6203       { { "s0" }, "$16" },
6204       { { "s1" }, "$17" },
6205       { { "s2" }, "$18" },
6206       { { "s3" }, "$19" },
6207       { { "s4" }, "$20" },
6208       { { "s5" }, "$21" },
6209       { { "s6" }, "$22" },
6210       { { "s7" }, "$23" },
6211       { { "t8" }, "$24" },
6212       { { "t9" }, "$25" },
6213       { { "k0" }, "$26" },
6214       { { "k1" }, "$27" },
6215       { { "gp" }, "$28" },
6216       { { "sp","$sp" }, "$29" },
6217       { { "fp","$fp" }, "$30" },
6218       { { "ra" }, "$31" }
6219     };
6220     Aliases = GCCRegAliases;
6221     NumAliases = llvm::array_lengthof(GCCRegAliases);
6222   }
6223 
6224   bool hasInt128Type() const override { return true; }
6225 };
6226 
6227 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
6228   void setDescriptionString() override {
6229     if (ABI == "n32")
6230       DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6231     else
6232       DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6233 
6234   }
6235 
6236 public:
6237   Mips64EBTargetInfo(const llvm::Triple &Triple)
6238       : Mips64TargetInfoBase(Triple) {}
6239   void getTargetDefines(const LangOptions &Opts,
6240                         MacroBuilder &Builder) const override {
6241     DefineStd(Builder, "MIPSEB", Opts);
6242     Builder.defineMacro("_MIPSEB");
6243     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6244   }
6245 };
6246 
6247 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
6248   void setDescriptionString() override {
6249     if (ABI == "n32")
6250       DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6251     else
6252       DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6253   }
6254 public:
6255   Mips64ELTargetInfo(const llvm::Triple &Triple)
6256       : Mips64TargetInfoBase(Triple) {
6257     // Default ABI is n64.
6258     BigEndian = false;
6259   }
6260   void getTargetDefines(const LangOptions &Opts,
6261                         MacroBuilder &Builder) const override {
6262     DefineStd(Builder, "MIPSEL", Opts);
6263     Builder.defineMacro("_MIPSEL");
6264     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6265   }
6266 };
6267 } // end anonymous namespace.
6268 
6269 namespace {
6270 class PNaClTargetInfo : public TargetInfo {
6271 public:
6272   PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6273     BigEndian = false;
6274     this->UserLabelPrefix = "";
6275     this->LongAlign = 32;
6276     this->LongWidth = 32;
6277     this->PointerAlign = 32;
6278     this->PointerWidth = 32;
6279     this->IntMaxType = TargetInfo::SignedLongLong;
6280     this->Int64Type = TargetInfo::SignedLongLong;
6281     this->DoubleAlign = 64;
6282     this->LongDoubleWidth = 64;
6283     this->LongDoubleAlign = 64;
6284     this->SizeType = TargetInfo::UnsignedInt;
6285     this->PtrDiffType = TargetInfo::SignedInt;
6286     this->IntPtrType = TargetInfo::SignedInt;
6287     this->RegParmMax = 0; // Disallow regparm
6288   }
6289 
6290   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
6291   }
6292   void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
6293     Builder.defineMacro("__le32__");
6294     Builder.defineMacro("__pnacl__");
6295   }
6296   void getTargetDefines(const LangOptions &Opts,
6297                         MacroBuilder &Builder) const override {
6298     getArchDefines(Opts, Builder);
6299   }
6300   bool hasFeature(StringRef Feature) const override {
6301     return Feature == "pnacl";
6302   }
6303   void getTargetBuiltins(const Builtin::Info *&Records,
6304                          unsigned &NumRecords) const override {
6305   }
6306   BuiltinVaListKind getBuiltinVaListKind() const override {
6307     return TargetInfo::PNaClABIBuiltinVaList;
6308   }
6309   void getGCCRegNames(const char * const *&Names,
6310                       unsigned &NumNames) const override;
6311   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6312                         unsigned &NumAliases) const override;
6313   bool validateAsmConstraint(const char *&Name,
6314                              TargetInfo::ConstraintInfo &Info) const override {
6315     return false;
6316   }
6317 
6318   const char *getClobbers() const override {
6319     return "";
6320   }
6321 };
6322 
6323 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
6324                                      unsigned &NumNames) const {
6325   Names = nullptr;
6326   NumNames = 0;
6327 }
6328 
6329 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
6330                                        unsigned &NumAliases) const {
6331   Aliases = nullptr;
6332   NumAliases = 0;
6333 }
6334 } // end anonymous namespace.
6335 
6336 namespace {
6337 class Le64TargetInfo : public TargetInfo {
6338   static const Builtin::Info BuiltinInfo[];
6339 
6340 public:
6341   Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6342     BigEndian = false;
6343     NoAsmVariants = true;
6344     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6345     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6346     DescriptionString =
6347         "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128";
6348   }
6349 
6350   void getTargetDefines(const LangOptions &Opts,
6351                         MacroBuilder &Builder) const override {
6352     DefineStd(Builder, "unix", Opts);
6353     defineCPUMacros(Builder, "le64", /*Tuning=*/false);
6354     Builder.defineMacro("__ELF__");
6355   }
6356   void getTargetBuiltins(const Builtin::Info *&Records,
6357                          unsigned &NumRecords) const override {
6358     Records = BuiltinInfo;
6359     NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin;
6360   }
6361   BuiltinVaListKind getBuiltinVaListKind() const override {
6362     return TargetInfo::PNaClABIBuiltinVaList;
6363   }
6364   const char *getClobbers() const override { return ""; }
6365   void getGCCRegNames(const char *const *&Names,
6366                       unsigned &NumNames) const override {
6367     Names = nullptr;
6368     NumNames = 0;
6369   }
6370   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6371                         unsigned &NumAliases) const override {
6372     Aliases = nullptr;
6373     NumAliases = 0;
6374   }
6375   bool validateAsmConstraint(const char *&Name,
6376                              TargetInfo::ConstraintInfo &Info) const override {
6377     return false;
6378   }
6379 
6380   bool hasProtectedVisibility() const override { return false; }
6381 };
6382 } // end anonymous namespace.
6383 
6384 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
6385 #define BUILTIN(ID, TYPE, ATTRS)                                               \
6386   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6387 #include "clang/Basic/BuiltinsLe64.def"
6388 };
6389 
6390 namespace {
6391   static const unsigned SPIRAddrSpaceMap[] = {
6392     1,    // opencl_global
6393     3,    // opencl_local
6394     2,    // opencl_constant
6395     4,    // opencl_generic
6396     0,    // cuda_device
6397     0,    // cuda_constant
6398     0     // cuda_shared
6399   };
6400   class SPIRTargetInfo : public TargetInfo {
6401   public:
6402     SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6403       assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
6404         "SPIR target must use unknown OS");
6405       assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
6406         "SPIR target must use unknown environment type");
6407       BigEndian = false;
6408       TLSSupported = false;
6409       LongWidth = LongAlign = 64;
6410       AddrSpaceMap = &SPIRAddrSpaceMap;
6411       UseAddrSpaceMapMangling = true;
6412       // Define available target features
6413       // These must be defined in sorted order!
6414       NoAsmVariants = true;
6415     }
6416     void getTargetDefines(const LangOptions &Opts,
6417                           MacroBuilder &Builder) const override {
6418       DefineStd(Builder, "SPIR", Opts);
6419     }
6420     bool hasFeature(StringRef Feature) const override {
6421       return Feature == "spir";
6422     }
6423 
6424     void getTargetBuiltins(const Builtin::Info *&Records,
6425                            unsigned &NumRecords) const override {}
6426     const char *getClobbers() const override {
6427       return "";
6428     }
6429     void getGCCRegNames(const char * const *&Names,
6430                         unsigned &NumNames) const override {}
6431     bool
6432     validateAsmConstraint(const char *&Name,
6433                           TargetInfo::ConstraintInfo &info) const override {
6434       return true;
6435     }
6436     void getGCCRegAliases(const GCCRegAlias *&Aliases,
6437                           unsigned &NumAliases) const override {}
6438     BuiltinVaListKind getBuiltinVaListKind() const override {
6439       return TargetInfo::VoidPtrBuiltinVaList;
6440     }
6441 
6442     CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
6443       return (CC == CC_SpirFunction ||
6444               CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning;
6445     }
6446 
6447     CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
6448       return CC_SpirFunction;
6449     }
6450   };
6451 
6452 
6453   class SPIR32TargetInfo : public SPIRTargetInfo {
6454   public:
6455     SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6456       PointerWidth = PointerAlign = 32;
6457       SizeType     = TargetInfo::UnsignedInt;
6458       PtrDiffType = IntPtrType = TargetInfo::SignedInt;
6459       DescriptionString
6460         = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
6461           "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6462     }
6463     void getTargetDefines(const LangOptions &Opts,
6464                           MacroBuilder &Builder) const override {
6465       DefineStd(Builder, "SPIR32", Opts);
6466     }
6467   };
6468 
6469   class SPIR64TargetInfo : public SPIRTargetInfo {
6470   public:
6471     SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6472       PointerWidth = PointerAlign = 64;
6473       SizeType     = TargetInfo::UnsignedLong;
6474       PtrDiffType = IntPtrType = TargetInfo::SignedLong;
6475       DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
6476                           "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6477     }
6478     void getTargetDefines(const LangOptions &Opts,
6479                           MacroBuilder &Builder) const override {
6480       DefineStd(Builder, "SPIR64", Opts);
6481     }
6482   };
6483 }
6484 
6485 namespace {
6486 class XCoreTargetInfo : public TargetInfo {
6487   static const Builtin::Info BuiltinInfo[];
6488 public:
6489   XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6490     BigEndian = false;
6491     NoAsmVariants = true;
6492     LongLongAlign = 32;
6493     SuitableAlign = 32;
6494     DoubleAlign = LongDoubleAlign = 32;
6495     SizeType = UnsignedInt;
6496     PtrDiffType = SignedInt;
6497     IntPtrType = SignedInt;
6498     WCharType = UnsignedChar;
6499     WIntType = UnsignedInt;
6500     UseZeroLengthBitfieldAlignment = true;
6501     DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
6502                         "-f64:32-a:0:32-n32";
6503   }
6504   void getTargetDefines(const LangOptions &Opts,
6505                         MacroBuilder &Builder) const override {
6506     Builder.defineMacro("__XS1B__");
6507   }
6508   void getTargetBuiltins(const Builtin::Info *&Records,
6509                          unsigned &NumRecords) const override {
6510     Records = BuiltinInfo;
6511     NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin;
6512   }
6513   BuiltinVaListKind getBuiltinVaListKind() const override {
6514     return TargetInfo::VoidPtrBuiltinVaList;
6515   }
6516   const char *getClobbers() const override {
6517     return "";
6518   }
6519   void getGCCRegNames(const char * const *&Names,
6520                       unsigned &NumNames) const override {
6521     static const char * const GCCRegNames[] = {
6522       "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
6523       "r8",   "r9",   "r10",  "r11",  "cp",   "dp",   "sp",   "lr"
6524     };
6525     Names = GCCRegNames;
6526     NumNames = llvm::array_lengthof(GCCRegNames);
6527   }
6528   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6529                         unsigned &NumAliases) const override {
6530     Aliases = nullptr;
6531     NumAliases = 0;
6532   }
6533   bool validateAsmConstraint(const char *&Name,
6534                              TargetInfo::ConstraintInfo &Info) const override {
6535     return false;
6536   }
6537   int getEHDataRegisterNumber(unsigned RegNo) const override {
6538     // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
6539     return (RegNo < 2)? RegNo : -1;
6540   }
6541 };
6542 
6543 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
6544 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6545 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6546                                               ALL_LANGUAGES },
6547 #include "clang/Basic/BuiltinsXCore.def"
6548 };
6549 } // end anonymous namespace.
6550 
6551 
6552 //===----------------------------------------------------------------------===//
6553 // Driver code
6554 //===----------------------------------------------------------------------===//
6555 
6556 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
6557   llvm::Triple::OSType os = Triple.getOS();
6558 
6559   switch (Triple.getArch()) {
6560   default:
6561     return nullptr;
6562 
6563   case llvm::Triple::xcore:
6564     return new XCoreTargetInfo(Triple);
6565 
6566   case llvm::Triple::hexagon:
6567     return new HexagonTargetInfo(Triple);
6568 
6569   case llvm::Triple::aarch64:
6570     if (Triple.isOSDarwin())
6571       return new DarwinAArch64TargetInfo(Triple);
6572 
6573     switch (os) {
6574     case llvm::Triple::FreeBSD:
6575       return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple);
6576     case llvm::Triple::Linux:
6577       return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
6578     case llvm::Triple::NetBSD:
6579       return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
6580     default:
6581       return new AArch64leTargetInfo(Triple);
6582     }
6583 
6584   case llvm::Triple::aarch64_be:
6585     switch (os) {
6586     case llvm::Triple::FreeBSD:
6587       return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple);
6588     case llvm::Triple::Linux:
6589       return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
6590     case llvm::Triple::NetBSD:
6591       return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
6592     default:
6593       return new AArch64beTargetInfo(Triple);
6594     }
6595 
6596   case llvm::Triple::arm:
6597   case llvm::Triple::thumb:
6598     if (Triple.isOSBinFormatMachO())
6599       return new DarwinARMTargetInfo(Triple);
6600 
6601     switch (os) {
6602     case llvm::Triple::Linux:
6603       return new LinuxTargetInfo<ARMleTargetInfo>(Triple);
6604     case llvm::Triple::FreeBSD:
6605       return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple);
6606     case llvm::Triple::NetBSD:
6607       return new NetBSDTargetInfo<ARMleTargetInfo>(Triple);
6608     case llvm::Triple::OpenBSD:
6609       return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple);
6610     case llvm::Triple::Bitrig:
6611       return new BitrigTargetInfo<ARMleTargetInfo>(Triple);
6612     case llvm::Triple::RTEMS:
6613       return new RTEMSTargetInfo<ARMleTargetInfo>(Triple);
6614     case llvm::Triple::NaCl:
6615       return new NaClTargetInfo<ARMleTargetInfo>(Triple);
6616     case llvm::Triple::Win32:
6617       switch (Triple.getEnvironment()) {
6618       default:
6619         return new ARMleTargetInfo(Triple);
6620       case llvm::Triple::Itanium:
6621         return new ItaniumWindowsARMleTargetInfo(Triple);
6622       case llvm::Triple::MSVC:
6623         return new MicrosoftARMleTargetInfo(Triple);
6624       }
6625     default:
6626       return new ARMleTargetInfo(Triple);
6627     }
6628 
6629   case llvm::Triple::armeb:
6630   case llvm::Triple::thumbeb:
6631     if (Triple.isOSDarwin())
6632       return new DarwinARMTargetInfo(Triple);
6633 
6634     switch (os) {
6635     case llvm::Triple::Linux:
6636       return new LinuxTargetInfo<ARMbeTargetInfo>(Triple);
6637     case llvm::Triple::FreeBSD:
6638       return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple);
6639     case llvm::Triple::NetBSD:
6640       return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple);
6641     case llvm::Triple::OpenBSD:
6642       return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple);
6643     case llvm::Triple::Bitrig:
6644       return new BitrigTargetInfo<ARMbeTargetInfo>(Triple);
6645     case llvm::Triple::RTEMS:
6646       return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple);
6647     case llvm::Triple::NaCl:
6648       return new NaClTargetInfo<ARMbeTargetInfo>(Triple);
6649     default:
6650       return new ARMbeTargetInfo(Triple);
6651     }
6652 
6653   case llvm::Triple::msp430:
6654     return new MSP430TargetInfo(Triple);
6655 
6656   case llvm::Triple::mips:
6657     switch (os) {
6658     case llvm::Triple::Linux:
6659       return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
6660     case llvm::Triple::RTEMS:
6661       return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
6662     case llvm::Triple::FreeBSD:
6663       return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6664     case llvm::Triple::NetBSD:
6665       return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6666     default:
6667       return new Mips32EBTargetInfo(Triple);
6668     }
6669 
6670   case llvm::Triple::mipsel:
6671     switch (os) {
6672     case llvm::Triple::Linux:
6673       return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
6674     case llvm::Triple::RTEMS:
6675       return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
6676     case llvm::Triple::FreeBSD:
6677       return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6678     case llvm::Triple::NetBSD:
6679       return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6680     case llvm::Triple::NaCl:
6681       return new NaClTargetInfo<Mips32ELTargetInfo>(Triple);
6682     default:
6683       return new Mips32ELTargetInfo(Triple);
6684     }
6685 
6686   case llvm::Triple::mips64:
6687     switch (os) {
6688     case llvm::Triple::Linux:
6689       return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
6690     case llvm::Triple::RTEMS:
6691       return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
6692     case llvm::Triple::FreeBSD:
6693       return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6694     case llvm::Triple::NetBSD:
6695       return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6696     case llvm::Triple::OpenBSD:
6697       return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6698     default:
6699       return new Mips64EBTargetInfo(Triple);
6700     }
6701 
6702   case llvm::Triple::mips64el:
6703     switch (os) {
6704     case llvm::Triple::Linux:
6705       return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
6706     case llvm::Triple::RTEMS:
6707       return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
6708     case llvm::Triple::FreeBSD:
6709       return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6710     case llvm::Triple::NetBSD:
6711       return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6712     case llvm::Triple::OpenBSD:
6713       return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6714     default:
6715       return new Mips64ELTargetInfo(Triple);
6716     }
6717 
6718   case llvm::Triple::le32:
6719     switch (os) {
6720       case llvm::Triple::NaCl:
6721         return new NaClTargetInfo<PNaClTargetInfo>(Triple);
6722       default:
6723         return nullptr;
6724     }
6725 
6726   case llvm::Triple::le64:
6727     return new Le64TargetInfo(Triple);
6728 
6729   case llvm::Triple::ppc:
6730     if (Triple.isOSDarwin())
6731       return new DarwinPPC32TargetInfo(Triple);
6732     switch (os) {
6733     case llvm::Triple::Linux:
6734       return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
6735     case llvm::Triple::FreeBSD:
6736       return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
6737     case llvm::Triple::NetBSD:
6738       return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
6739     case llvm::Triple::OpenBSD:
6740       return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
6741     case llvm::Triple::RTEMS:
6742       return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
6743     default:
6744       return new PPC32TargetInfo(Triple);
6745     }
6746 
6747   case llvm::Triple::ppc64:
6748     if (Triple.isOSDarwin())
6749       return new DarwinPPC64TargetInfo(Triple);
6750     switch (os) {
6751     case llvm::Triple::Linux:
6752       return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6753     case llvm::Triple::Lv2:
6754       return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
6755     case llvm::Triple::FreeBSD:
6756       return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
6757     case llvm::Triple::NetBSD:
6758       return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
6759     default:
6760       return new PPC64TargetInfo(Triple);
6761     }
6762 
6763   case llvm::Triple::ppc64le:
6764     switch (os) {
6765     case llvm::Triple::Linux:
6766       return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6767     default:
6768       return new PPC64TargetInfo(Triple);
6769     }
6770 
6771   case llvm::Triple::nvptx:
6772     return new NVPTX32TargetInfo(Triple);
6773   case llvm::Triple::nvptx64:
6774     return new NVPTX64TargetInfo(Triple);
6775 
6776   case llvm::Triple::amdgcn:
6777   case llvm::Triple::r600:
6778     return new R600TargetInfo(Triple);
6779 
6780   case llvm::Triple::sparc:
6781     switch (os) {
6782     case llvm::Triple::Linux:
6783       return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
6784     case llvm::Triple::Solaris:
6785       return new SolarisSparcV8TargetInfo(Triple);
6786     case llvm::Triple::NetBSD:
6787       return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
6788     case llvm::Triple::OpenBSD:
6789       return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
6790     case llvm::Triple::RTEMS:
6791       return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
6792     default:
6793       return new SparcV8TargetInfo(Triple);
6794     }
6795 
6796   case llvm::Triple::sparcv9:
6797     switch (os) {
6798     case llvm::Triple::Linux:
6799       return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
6800     case llvm::Triple::Solaris:
6801       return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
6802     case llvm::Triple::NetBSD:
6803       return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
6804     case llvm::Triple::OpenBSD:
6805       return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
6806     case llvm::Triple::FreeBSD:
6807       return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
6808     default:
6809       return new SparcV9TargetInfo(Triple);
6810     }
6811 
6812   case llvm::Triple::systemz:
6813     switch (os) {
6814     case llvm::Triple::Linux:
6815       return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
6816     default:
6817       return new SystemZTargetInfo(Triple);
6818     }
6819 
6820   case llvm::Triple::tce:
6821     return new TCETargetInfo(Triple);
6822 
6823   case llvm::Triple::x86:
6824     if (Triple.isOSDarwin())
6825       return new DarwinI386TargetInfo(Triple);
6826 
6827     switch (os) {
6828     case llvm::Triple::Linux:
6829       return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
6830     case llvm::Triple::DragonFly:
6831       return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
6832     case llvm::Triple::NetBSD:
6833       return new NetBSDI386TargetInfo(Triple);
6834     case llvm::Triple::OpenBSD:
6835       return new OpenBSDI386TargetInfo(Triple);
6836     case llvm::Triple::Bitrig:
6837       return new BitrigI386TargetInfo(Triple);
6838     case llvm::Triple::FreeBSD:
6839       return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6840     case llvm::Triple::KFreeBSD:
6841       return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6842     case llvm::Triple::Minix:
6843       return new MinixTargetInfo<X86_32TargetInfo>(Triple);
6844     case llvm::Triple::Solaris:
6845       return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
6846     case llvm::Triple::Win32: {
6847       switch (Triple.getEnvironment()) {
6848       default:
6849         return new X86_32TargetInfo(Triple);
6850       case llvm::Triple::Cygnus:
6851         return new CygwinX86_32TargetInfo(Triple);
6852       case llvm::Triple::GNU:
6853         return new MinGWX86_32TargetInfo(Triple);
6854       case llvm::Triple::Itanium:
6855       case llvm::Triple::MSVC:
6856         return new MicrosoftX86_32TargetInfo(Triple);
6857       }
6858     }
6859     case llvm::Triple::Haiku:
6860       return new HaikuX86_32TargetInfo(Triple);
6861     case llvm::Triple::RTEMS:
6862       return new RTEMSX86_32TargetInfo(Triple);
6863     case llvm::Triple::NaCl:
6864       return new NaClTargetInfo<X86_32TargetInfo>(Triple);
6865     default:
6866       return new X86_32TargetInfo(Triple);
6867     }
6868 
6869   case llvm::Triple::x86_64:
6870     if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
6871       return new DarwinX86_64TargetInfo(Triple);
6872 
6873     switch (os) {
6874     case llvm::Triple::Linux:
6875       return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
6876     case llvm::Triple::DragonFly:
6877       return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
6878     case llvm::Triple::NetBSD:
6879       return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
6880     case llvm::Triple::OpenBSD:
6881       return new OpenBSDX86_64TargetInfo(Triple);
6882     case llvm::Triple::Bitrig:
6883       return new BitrigX86_64TargetInfo(Triple);
6884     case llvm::Triple::FreeBSD:
6885       return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6886     case llvm::Triple::KFreeBSD:
6887       return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6888     case llvm::Triple::Solaris:
6889       return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
6890     case llvm::Triple::Win32: {
6891       switch (Triple.getEnvironment()) {
6892       default:
6893         return new X86_64TargetInfo(Triple);
6894       case llvm::Triple::GNU:
6895         return new MinGWX86_64TargetInfo(Triple);
6896       case llvm::Triple::MSVC:
6897         return new MicrosoftX86_64TargetInfo(Triple);
6898       }
6899     }
6900     case llvm::Triple::NaCl:
6901       return new NaClTargetInfo<X86_64TargetInfo>(Triple);
6902     case llvm::Triple::PS4:
6903       return new PS4OSTargetInfo<X86_64TargetInfo>(Triple);
6904     default:
6905       return new X86_64TargetInfo(Triple);
6906     }
6907 
6908     case llvm::Triple::spir: {
6909       if (Triple.getOS() != llvm::Triple::UnknownOS ||
6910           Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6911         return nullptr;
6912       return new SPIR32TargetInfo(Triple);
6913     }
6914     case llvm::Triple::spir64: {
6915       if (Triple.getOS() != llvm::Triple::UnknownOS ||
6916           Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6917         return nullptr;
6918       return new SPIR64TargetInfo(Triple);
6919     }
6920   }
6921 }
6922 
6923 /// CreateTargetInfo - Return the target info object for the specified target
6924 /// triple.
6925 TargetInfo *
6926 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
6927                              const std::shared_ptr<TargetOptions> &Opts) {
6928   llvm::Triple Triple(Opts->Triple);
6929 
6930   // Construct the target
6931   std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple));
6932   if (!Target) {
6933     Diags.Report(diag::err_target_unknown_triple) << Triple.str();
6934     return nullptr;
6935   }
6936   Target->TargetOpts = Opts;
6937 
6938   // Set the target CPU if specified.
6939   if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
6940     Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
6941     return nullptr;
6942   }
6943 
6944   // Set the target ABI if specified.
6945   if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
6946     Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
6947     return nullptr;
6948   }
6949 
6950   // Set the fp math unit.
6951   if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
6952     Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
6953     return nullptr;
6954   }
6955 
6956   // Compute the default target features, we need the target to handle this
6957   // because features may have dependencies on one another.
6958   llvm::StringMap<bool> Features;
6959   Target->getDefaultFeatures(Features);
6960 
6961   // Apply the user specified deltas.
6962   for (unsigned I = 0, N = Opts->FeaturesAsWritten.size();
6963        I < N; ++I) {
6964     const char *Name = Opts->FeaturesAsWritten[I].c_str();
6965     // Apply the feature via the target.
6966     bool Enabled = Name[0] == '+';
6967     Target->setFeatureEnabled(Features, Name + 1, Enabled);
6968   }
6969 
6970   // Add the features to the compile options.
6971   //
6972   // FIXME: If we are completely confident that we have the right set, we only
6973   // need to pass the minuses.
6974   Opts->Features.clear();
6975   for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
6976          ie = Features.end(); it != ie; ++it)
6977     Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
6978   if (!Target->handleTargetFeatures(Opts->Features, Diags))
6979     return nullptr;
6980 
6981   return Target.release();
6982 }
6983