1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "clang/Basic/Version.h" 23 #include "llvm/ADT/APFloat.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringExtras.h" 26 #include "llvm/ADT/StringRef.h" 27 #include "llvm/ADT/StringSwitch.h" 28 #include "llvm/ADT/Triple.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/TargetParser.h" 32 #include <algorithm> 33 #include <memory> 34 35 using namespace clang; 36 37 //===----------------------------------------------------------------------===// 38 // Common code shared among targets. 39 //===----------------------------------------------------------------------===// 40 41 /// DefineStd - Define a macro name and standard variants. For example if 42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 43 /// when in GNU mode. 44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 45 const LangOptions &Opts) { 46 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 47 48 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 49 // in the user's namespace. 50 if (Opts.GNUMode) 51 Builder.defineMacro(MacroName); 52 53 // Define __unix. 54 Builder.defineMacro("__" + MacroName); 55 56 // Define __unix__. 57 Builder.defineMacro("__" + MacroName + "__"); 58 } 59 60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 61 bool Tuning = true) { 62 Builder.defineMacro("__" + CPUName); 63 Builder.defineMacro("__" + CPUName + "__"); 64 if (Tuning) 65 Builder.defineMacro("__tune_" + CPUName + "__"); 66 } 67 68 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 69 const TargetOptions &Opts); 70 71 //===----------------------------------------------------------------------===// 72 // Defines specific to certain operating systems. 73 //===----------------------------------------------------------------------===// 74 75 namespace { 76 template<typename TgtInfo> 77 class OSTargetInfo : public TgtInfo { 78 protected: 79 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 80 MacroBuilder &Builder) const=0; 81 public: 82 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 83 : TgtInfo(Triple, Opts) {} 84 void getTargetDefines(const LangOptions &Opts, 85 MacroBuilder &Builder) const override { 86 TgtInfo::getTargetDefines(Opts, Builder); 87 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 88 } 89 90 }; 91 92 // CloudABI Target 93 template <typename Target> 94 class CloudABITargetInfo : public OSTargetInfo<Target> { 95 protected: 96 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 97 MacroBuilder &Builder) const override { 98 Builder.defineMacro("__CloudABI__"); 99 Builder.defineMacro("__ELF__"); 100 101 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 102 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 103 Builder.defineMacro("__STDC_UTF_16__"); 104 Builder.defineMacro("__STDC_UTF_32__"); 105 } 106 107 public: 108 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 109 : OSTargetInfo<Target>(Triple, Opts) {} 110 }; 111 112 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 113 const llvm::Triple &Triple, 114 StringRef &PlatformName, 115 VersionTuple &PlatformMinVersion) { 116 Builder.defineMacro("__APPLE_CC__", "6000"); 117 Builder.defineMacro("__APPLE__"); 118 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 119 // AddressSanitizer doesn't play well with source fortification, which is on 120 // by default on Darwin. 121 if (Opts.Sanitize.has(SanitizerKind::Address)) 122 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 123 124 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 125 if (!Opts.ObjC1) { 126 // __weak is always defined, for use in blocks and with objc pointers. 127 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 128 Builder.defineMacro("__strong", ""); 129 Builder.defineMacro("__unsafe_unretained", ""); 130 } 131 132 if (Opts.Static) 133 Builder.defineMacro("__STATIC__"); 134 else 135 Builder.defineMacro("__DYNAMIC__"); 136 137 if (Opts.POSIXThreads) 138 Builder.defineMacro("_REENTRANT"); 139 140 // Get the platform type and version number from the triple. 141 unsigned Maj, Min, Rev; 142 if (Triple.isMacOSX()) { 143 Triple.getMacOSXVersion(Maj, Min, Rev); 144 PlatformName = "macosx"; 145 } else { 146 Triple.getOSVersion(Maj, Min, Rev); 147 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 148 } 149 150 // If -target arch-pc-win32-macho option specified, we're 151 // generating code for Win32 ABI. No need to emit 152 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 153 if (PlatformName == "win32") { 154 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 155 return; 156 } 157 158 // Set the appropriate OS version define. 159 if (Triple.isiOS()) { 160 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 161 char Str[6]; 162 Str[0] = '0' + Maj; 163 Str[1] = '0' + (Min / 10); 164 Str[2] = '0' + (Min % 10); 165 Str[3] = '0' + (Rev / 10); 166 Str[4] = '0' + (Rev % 10); 167 Str[5] = '\0'; 168 if (Triple.isTvOS()) 169 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 170 else 171 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 172 Str); 173 174 } else if (Triple.isWatchOS()) { 175 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 176 char Str[6]; 177 Str[0] = '0' + Maj; 178 Str[1] = '0' + (Min / 10); 179 Str[2] = '0' + (Min % 10); 180 Str[3] = '0' + (Rev / 10); 181 Str[4] = '0' + (Rev % 10); 182 Str[5] = '\0'; 183 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 184 } else if (Triple.isMacOSX()) { 185 // Note that the Driver allows versions which aren't representable in the 186 // define (because we only get a single digit for the minor and micro 187 // revision numbers). So, we limit them to the maximum representable 188 // version. 189 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 190 char Str[7]; 191 if (Maj < 10 || (Maj == 10 && Min < 10)) { 192 Str[0] = '0' + (Maj / 10); 193 Str[1] = '0' + (Maj % 10); 194 Str[2] = '0' + std::min(Min, 9U); 195 Str[3] = '0' + std::min(Rev, 9U); 196 Str[4] = '\0'; 197 } else { 198 // Handle versions > 10.9. 199 Str[0] = '0' + (Maj / 10); 200 Str[1] = '0' + (Maj % 10); 201 Str[2] = '0' + (Min / 10); 202 Str[3] = '0' + (Min % 10); 203 Str[4] = '0' + (Rev / 10); 204 Str[5] = '0' + (Rev % 10); 205 Str[6] = '\0'; 206 } 207 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 208 } 209 210 // Tell users about the kernel if there is one. 211 if (Triple.isOSDarwin()) 212 Builder.defineMacro("__MACH__"); 213 214 // The Watch ABI uses Dwarf EH. 215 if(Triple.isWatchABI()) 216 Builder.defineMacro("__ARM_DWARF_EH__"); 217 218 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 219 } 220 221 template<typename Target> 222 class DarwinTargetInfo : public OSTargetInfo<Target> { 223 protected: 224 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 225 MacroBuilder &Builder) const override { 226 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 227 this->PlatformMinVersion); 228 } 229 230 public: 231 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 232 : OSTargetInfo<Target>(Triple, Opts) { 233 // By default, no TLS, and we whitelist permitted architecture/OS 234 // combinations. 235 this->TLSSupported = false; 236 237 if (Triple.isMacOSX()) 238 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 239 else if (Triple.isiOS()) { 240 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 241 if (Triple.getArch() == llvm::Triple::x86_64 || 242 Triple.getArch() == llvm::Triple::aarch64) 243 this->TLSSupported = !Triple.isOSVersionLT(8); 244 else if (Triple.getArch() == llvm::Triple::x86 || 245 Triple.getArch() == llvm::Triple::arm || 246 Triple.getArch() == llvm::Triple::thumb) 247 this->TLSSupported = !Triple.isOSVersionLT(9); 248 } else if (Triple.isWatchOS()) 249 this->TLSSupported = !Triple.isOSVersionLT(2); 250 251 this->MCountName = "\01mcount"; 252 } 253 254 std::string isValidSectionSpecifier(StringRef SR) const override { 255 // Let MCSectionMachO validate this. 256 StringRef Segment, Section; 257 unsigned TAA, StubSize; 258 bool HasTAA; 259 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 260 TAA, HasTAA, StubSize); 261 } 262 263 const char *getStaticInitSectionSpecifier() const override { 264 // FIXME: We should return 0 when building kexts. 265 return "__TEXT,__StaticInit,regular,pure_instructions"; 266 } 267 268 /// Darwin does not support protected visibility. Darwin's "default" 269 /// is very similar to ELF's "protected"; Darwin requires a "weak" 270 /// attribute on declarations that can be dynamically replaced. 271 bool hasProtectedVisibility() const override { 272 return false; 273 } 274 275 unsigned getExnObjectAlignment() const override { 276 // The alignment of an exception object is 8-bytes for darwin since 277 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 278 // and therefore doesn't guarantee 16-byte alignment. 279 return 64; 280 } 281 }; 282 283 284 // DragonFlyBSD Target 285 template<typename Target> 286 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 287 protected: 288 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 289 MacroBuilder &Builder) const override { 290 // DragonFly defines; list based off of gcc output 291 Builder.defineMacro("__DragonFly__"); 292 Builder.defineMacro("__DragonFly_cc_version", "100001"); 293 Builder.defineMacro("__ELF__"); 294 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 295 Builder.defineMacro("__tune_i386__"); 296 DefineStd(Builder, "unix", Opts); 297 } 298 public: 299 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 300 : OSTargetInfo<Target>(Triple, Opts) { 301 switch (Triple.getArch()) { 302 default: 303 case llvm::Triple::x86: 304 case llvm::Triple::x86_64: 305 this->MCountName = ".mcount"; 306 break; 307 } 308 } 309 }; 310 311 // FreeBSD Target 312 template<typename Target> 313 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 314 protected: 315 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 316 MacroBuilder &Builder) const override { 317 // FreeBSD defines; list based off of gcc output 318 319 unsigned Release = Triple.getOSMajorVersion(); 320 if (Release == 0U) 321 Release = 8; 322 323 Builder.defineMacro("__FreeBSD__", Twine(Release)); 324 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 325 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 326 DefineStd(Builder, "unix", Opts); 327 Builder.defineMacro("__ELF__"); 328 329 // On FreeBSD, wchar_t contains the number of the code point as 330 // used by the character set of the locale. These character sets are 331 // not necessarily a superset of ASCII. 332 // 333 // FIXME: This is wrong; the macro refers to the numerical values 334 // of wchar_t *literals*, which are not locale-dependent. However, 335 // FreeBSD systems apparently depend on us getting this wrong, and 336 // setting this to 1 is conforming even if all the basic source 337 // character literals have the same encoding as char and wchar_t. 338 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 339 } 340 public: 341 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 342 : OSTargetInfo<Target>(Triple, Opts) { 343 switch (Triple.getArch()) { 344 default: 345 case llvm::Triple::x86: 346 case llvm::Triple::x86_64: 347 this->MCountName = ".mcount"; 348 break; 349 case llvm::Triple::mips: 350 case llvm::Triple::mipsel: 351 case llvm::Triple::ppc: 352 case llvm::Triple::ppc64: 353 case llvm::Triple::ppc64le: 354 this->MCountName = "_mcount"; 355 break; 356 case llvm::Triple::arm: 357 this->MCountName = "__mcount"; 358 break; 359 } 360 } 361 }; 362 363 // GNU/kFreeBSD Target 364 template<typename Target> 365 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 366 protected: 367 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 368 MacroBuilder &Builder) const override { 369 // GNU/kFreeBSD defines; list based off of gcc output 370 371 DefineStd(Builder, "unix", Opts); 372 Builder.defineMacro("__FreeBSD_kernel__"); 373 Builder.defineMacro("__GLIBC__"); 374 Builder.defineMacro("__ELF__"); 375 if (Opts.POSIXThreads) 376 Builder.defineMacro("_REENTRANT"); 377 if (Opts.CPlusPlus) 378 Builder.defineMacro("_GNU_SOURCE"); 379 } 380 public: 381 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 382 : OSTargetInfo<Target>(Triple, Opts) {} 383 }; 384 385 // Haiku Target 386 template<typename Target> 387 class HaikuTargetInfo : public OSTargetInfo<Target> { 388 protected: 389 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 390 MacroBuilder &Builder) const override { 391 // Haiku defines; list based off of gcc output 392 Builder.defineMacro("__HAIKU__"); 393 Builder.defineMacro("__ELF__"); 394 DefineStd(Builder, "unix", Opts); 395 } 396 public: 397 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 398 : OSTargetInfo<Target>(Triple, Opts) { 399 this->SizeType = TargetInfo::UnsignedLong; 400 this->IntPtrType = TargetInfo::SignedLong; 401 this->PtrDiffType = TargetInfo::SignedLong; 402 this->ProcessIDType = TargetInfo::SignedLong; 403 this->TLSSupported = false; 404 405 } 406 }; 407 408 // Minix Target 409 template<typename Target> 410 class MinixTargetInfo : public OSTargetInfo<Target> { 411 protected: 412 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 413 MacroBuilder &Builder) const override { 414 // Minix defines 415 416 Builder.defineMacro("__minix", "3"); 417 Builder.defineMacro("_EM_WSIZE", "4"); 418 Builder.defineMacro("_EM_PSIZE", "4"); 419 Builder.defineMacro("_EM_SSIZE", "2"); 420 Builder.defineMacro("_EM_LSIZE", "4"); 421 Builder.defineMacro("_EM_FSIZE", "4"); 422 Builder.defineMacro("_EM_DSIZE", "8"); 423 Builder.defineMacro("__ELF__"); 424 DefineStd(Builder, "unix", Opts); 425 } 426 public: 427 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 428 : OSTargetInfo<Target>(Triple, Opts) {} 429 }; 430 431 // Linux target 432 template<typename Target> 433 class LinuxTargetInfo : public OSTargetInfo<Target> { 434 protected: 435 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 436 MacroBuilder &Builder) const override { 437 // Linux defines; list based off of gcc output 438 DefineStd(Builder, "unix", Opts); 439 DefineStd(Builder, "linux", Opts); 440 Builder.defineMacro("__gnu_linux__"); 441 Builder.defineMacro("__ELF__"); 442 if (Triple.isAndroid()) { 443 Builder.defineMacro("__ANDROID__", "1"); 444 unsigned Maj, Min, Rev; 445 Triple.getEnvironmentVersion(Maj, Min, Rev); 446 this->PlatformName = "android"; 447 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 448 } 449 if (Opts.POSIXThreads) 450 Builder.defineMacro("_REENTRANT"); 451 if (Opts.CPlusPlus) 452 Builder.defineMacro("_GNU_SOURCE"); 453 if (this->HasFloat128) 454 Builder.defineMacro("__FLOAT128__"); 455 } 456 public: 457 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 458 : OSTargetInfo<Target>(Triple, Opts) { 459 this->WIntType = TargetInfo::UnsignedInt; 460 461 switch (Triple.getArch()) { 462 default: 463 break; 464 case llvm::Triple::ppc: 465 case llvm::Triple::ppc64: 466 case llvm::Triple::ppc64le: 467 this->MCountName = "_mcount"; 468 break; 469 case llvm::Triple::x86: 470 case llvm::Triple::x86_64: 471 case llvm::Triple::systemz: 472 this->HasFloat128 = true; 473 break; 474 } 475 } 476 477 const char *getStaticInitSectionSpecifier() const override { 478 return ".text.startup"; 479 } 480 }; 481 482 // NetBSD Target 483 template<typename Target> 484 class NetBSDTargetInfo : public OSTargetInfo<Target> { 485 protected: 486 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 487 MacroBuilder &Builder) const override { 488 // NetBSD defines; list based off of gcc output 489 Builder.defineMacro("__NetBSD__"); 490 Builder.defineMacro("__unix__"); 491 Builder.defineMacro("__ELF__"); 492 if (Opts.POSIXThreads) 493 Builder.defineMacro("_POSIX_THREADS"); 494 495 switch (Triple.getArch()) { 496 default: 497 break; 498 case llvm::Triple::arm: 499 case llvm::Triple::armeb: 500 case llvm::Triple::thumb: 501 case llvm::Triple::thumbeb: 502 Builder.defineMacro("__ARM_DWARF_EH__"); 503 break; 504 } 505 } 506 public: 507 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 508 : OSTargetInfo<Target>(Triple, Opts) { 509 this->MCountName = "_mcount"; 510 } 511 }; 512 513 // OpenBSD Target 514 template<typename Target> 515 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 516 protected: 517 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 518 MacroBuilder &Builder) const override { 519 // OpenBSD defines; list based off of gcc output 520 521 Builder.defineMacro("__OpenBSD__"); 522 DefineStd(Builder, "unix", Opts); 523 Builder.defineMacro("__ELF__"); 524 if (Opts.POSIXThreads) 525 Builder.defineMacro("_REENTRANT"); 526 } 527 public: 528 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 529 : OSTargetInfo<Target>(Triple, Opts) { 530 this->TLSSupported = false; 531 532 switch (Triple.getArch()) { 533 default: 534 case llvm::Triple::x86: 535 case llvm::Triple::x86_64: 536 case llvm::Triple::arm: 537 case llvm::Triple::sparc: 538 this->MCountName = "__mcount"; 539 break; 540 case llvm::Triple::mips64: 541 case llvm::Triple::mips64el: 542 case llvm::Triple::ppc: 543 case llvm::Triple::sparcv9: 544 this->MCountName = "_mcount"; 545 break; 546 } 547 } 548 }; 549 550 // Bitrig Target 551 template<typename Target> 552 class BitrigTargetInfo : public OSTargetInfo<Target> { 553 protected: 554 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 555 MacroBuilder &Builder) const override { 556 // Bitrig defines; list based off of gcc output 557 558 Builder.defineMacro("__Bitrig__"); 559 DefineStd(Builder, "unix", Opts); 560 Builder.defineMacro("__ELF__"); 561 if (Opts.POSIXThreads) 562 Builder.defineMacro("_REENTRANT"); 563 564 switch (Triple.getArch()) { 565 default: 566 break; 567 case llvm::Triple::arm: 568 case llvm::Triple::armeb: 569 case llvm::Triple::thumb: 570 case llvm::Triple::thumbeb: 571 Builder.defineMacro("__ARM_DWARF_EH__"); 572 break; 573 } 574 } 575 public: 576 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 577 : OSTargetInfo<Target>(Triple, Opts) { 578 this->MCountName = "__mcount"; 579 } 580 }; 581 582 // PSP Target 583 template<typename Target> 584 class PSPTargetInfo : public OSTargetInfo<Target> { 585 protected: 586 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 587 MacroBuilder &Builder) const override { 588 // PSP defines; list based on the output of the pspdev gcc toolchain. 589 Builder.defineMacro("PSP"); 590 Builder.defineMacro("_PSP"); 591 Builder.defineMacro("__psp__"); 592 Builder.defineMacro("__ELF__"); 593 } 594 public: 595 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 596 }; 597 598 // PS3 PPU Target 599 template<typename Target> 600 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 601 protected: 602 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 603 MacroBuilder &Builder) const override { 604 // PS3 PPU defines. 605 Builder.defineMacro("__PPC__"); 606 Builder.defineMacro("__PPU__"); 607 Builder.defineMacro("__CELLOS_LV2__"); 608 Builder.defineMacro("__ELF__"); 609 Builder.defineMacro("__LP32__"); 610 Builder.defineMacro("_ARCH_PPC64"); 611 Builder.defineMacro("__powerpc64__"); 612 } 613 public: 614 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 615 : OSTargetInfo<Target>(Triple, Opts) { 616 this->LongWidth = this->LongAlign = 32; 617 this->PointerWidth = this->PointerAlign = 32; 618 this->IntMaxType = TargetInfo::SignedLongLong; 619 this->Int64Type = TargetInfo::SignedLongLong; 620 this->SizeType = TargetInfo::UnsignedInt; 621 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 622 } 623 }; 624 625 template <typename Target> 626 class PS4OSTargetInfo : public OSTargetInfo<Target> { 627 protected: 628 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 629 MacroBuilder &Builder) const override { 630 Builder.defineMacro("__FreeBSD__", "9"); 631 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 632 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 633 DefineStd(Builder, "unix", Opts); 634 Builder.defineMacro("__ELF__"); 635 Builder.defineMacro("__PS4__"); 636 } 637 public: 638 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 639 : OSTargetInfo<Target>(Triple, Opts) { 640 this->WCharType = this->UnsignedShort; 641 642 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 643 this->MaxTLSAlign = 256; 644 645 // On PS4, do not honor explicit bit field alignment, 646 // as in "__attribute__((aligned(2))) int b : 1;". 647 this->UseExplicitBitFieldAlignment = false; 648 649 switch (Triple.getArch()) { 650 default: 651 case llvm::Triple::x86_64: 652 this->MCountName = ".mcount"; 653 break; 654 } 655 } 656 }; 657 658 // Solaris target 659 template<typename Target> 660 class SolarisTargetInfo : public OSTargetInfo<Target> { 661 protected: 662 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 663 MacroBuilder &Builder) const override { 664 DefineStd(Builder, "sun", Opts); 665 DefineStd(Builder, "unix", Opts); 666 Builder.defineMacro("__ELF__"); 667 Builder.defineMacro("__svr4__"); 668 Builder.defineMacro("__SVR4"); 669 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 670 // newer, but to 500 for everything else. feature_test.h has a check to 671 // ensure that you are not using C99 with an old version of X/Open or C89 672 // with a new version. 673 if (Opts.C99) 674 Builder.defineMacro("_XOPEN_SOURCE", "600"); 675 else 676 Builder.defineMacro("_XOPEN_SOURCE", "500"); 677 if (Opts.CPlusPlus) 678 Builder.defineMacro("__C99FEATURES__"); 679 Builder.defineMacro("_LARGEFILE_SOURCE"); 680 Builder.defineMacro("_LARGEFILE64_SOURCE"); 681 Builder.defineMacro("__EXTENSIONS__"); 682 Builder.defineMacro("_REENTRANT"); 683 } 684 public: 685 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 686 : OSTargetInfo<Target>(Triple, Opts) { 687 this->WCharType = this->SignedInt; 688 // FIXME: WIntType should be SignedLong 689 } 690 }; 691 692 // Windows target 693 template<typename Target> 694 class WindowsTargetInfo : public OSTargetInfo<Target> { 695 protected: 696 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 697 MacroBuilder &Builder) const override { 698 Builder.defineMacro("_WIN32"); 699 } 700 void getVisualStudioDefines(const LangOptions &Opts, 701 MacroBuilder &Builder) const { 702 if (Opts.CPlusPlus) { 703 if (Opts.RTTIData) 704 Builder.defineMacro("_CPPRTTI"); 705 706 if (Opts.CXXExceptions) 707 Builder.defineMacro("_CPPUNWIND"); 708 } 709 710 if (Opts.Bool) 711 Builder.defineMacro("__BOOL_DEFINED"); 712 713 if (!Opts.CharIsSigned) 714 Builder.defineMacro("_CHAR_UNSIGNED"); 715 716 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 717 // but it works for now. 718 if (Opts.POSIXThreads) 719 Builder.defineMacro("_MT"); 720 721 if (Opts.MSCompatibilityVersion) { 722 Builder.defineMacro("_MSC_VER", 723 Twine(Opts.MSCompatibilityVersion / 100000)); 724 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 725 // FIXME We cannot encode the revision information into 32-bits 726 Builder.defineMacro("_MSC_BUILD", Twine(1)); 727 728 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 729 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 730 } 731 732 if (Opts.MicrosoftExt) { 733 Builder.defineMacro("_MSC_EXTENSIONS"); 734 735 if (Opts.CPlusPlus11) { 736 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 737 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 738 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 739 } 740 } 741 742 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 743 } 744 745 public: 746 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 747 : OSTargetInfo<Target>(Triple, Opts) {} 748 }; 749 750 template <typename Target> 751 class NaClTargetInfo : public OSTargetInfo<Target> { 752 protected: 753 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 754 MacroBuilder &Builder) const override { 755 if (Opts.POSIXThreads) 756 Builder.defineMacro("_REENTRANT"); 757 if (Opts.CPlusPlus) 758 Builder.defineMacro("_GNU_SOURCE"); 759 760 DefineStd(Builder, "unix", Opts); 761 Builder.defineMacro("__ELF__"); 762 Builder.defineMacro("__native_client__"); 763 } 764 765 public: 766 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 767 : OSTargetInfo<Target>(Triple, Opts) { 768 this->LongAlign = 32; 769 this->LongWidth = 32; 770 this->PointerAlign = 32; 771 this->PointerWidth = 32; 772 this->IntMaxType = TargetInfo::SignedLongLong; 773 this->Int64Type = TargetInfo::SignedLongLong; 774 this->DoubleAlign = 64; 775 this->LongDoubleWidth = 64; 776 this->LongDoubleAlign = 64; 777 this->LongLongWidth = 64; 778 this->LongLongAlign = 64; 779 this->SizeType = TargetInfo::UnsignedInt; 780 this->PtrDiffType = TargetInfo::SignedInt; 781 this->IntPtrType = TargetInfo::SignedInt; 782 // RegParmMax is inherited from the underlying architecture 783 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 784 if (Triple.getArch() == llvm::Triple::arm) { 785 // Handled in ARM's setABI(). 786 } else if (Triple.getArch() == llvm::Triple::x86) { 787 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 788 } else if (Triple.getArch() == llvm::Triple::x86_64) { 789 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 790 } else if (Triple.getArch() == llvm::Triple::mipsel) { 791 // Handled on mips' setDataLayout. 792 } else { 793 assert(Triple.getArch() == llvm::Triple::le32); 794 this->resetDataLayout("e-p:32:32-i64:64"); 795 } 796 } 797 }; 798 799 // WebAssembly target 800 template <typename Target> 801 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 802 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 803 MacroBuilder &Builder) const final { 804 // A common platform macro. 805 if (Opts.POSIXThreads) 806 Builder.defineMacro("_REENTRANT"); 807 // Follow g++ convention and predefine _GNU_SOURCE for C++. 808 if (Opts.CPlusPlus) 809 Builder.defineMacro("_GNU_SOURCE"); 810 } 811 812 // As an optimization, group static init code together in a section. 813 const char *getStaticInitSectionSpecifier() const final { 814 return ".text.__startup"; 815 } 816 817 public: 818 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 819 const TargetOptions &Opts) 820 : OSTargetInfo<Target>(Triple, Opts) { 821 this->MCountName = "__mcount"; 822 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 823 } 824 }; 825 826 //===----------------------------------------------------------------------===// 827 // Specific target implementations. 828 //===----------------------------------------------------------------------===// 829 830 // PPC abstract base class 831 class PPCTargetInfo : public TargetInfo { 832 static const Builtin::Info BuiltinInfo[]; 833 static const char * const GCCRegNames[]; 834 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 835 std::string CPU; 836 837 // Target cpu features. 838 bool HasVSX; 839 bool HasP8Vector; 840 bool HasP8Crypto; 841 bool HasDirectMove; 842 bool HasQPX; 843 bool HasHTM; 844 bool HasBPERMD; 845 bool HasExtDiv; 846 847 protected: 848 std::string ABI; 849 850 public: 851 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 852 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 853 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 854 HasBPERMD(false), HasExtDiv(false) { 855 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 856 SimdDefaultAlign = 128; 857 LongDoubleWidth = LongDoubleAlign = 128; 858 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 859 } 860 861 /// \brief Flags for architecture specific defines. 862 typedef enum { 863 ArchDefineNone = 0, 864 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 865 ArchDefinePpcgr = 1 << 1, 866 ArchDefinePpcsq = 1 << 2, 867 ArchDefine440 = 1 << 3, 868 ArchDefine603 = 1 << 4, 869 ArchDefine604 = 1 << 5, 870 ArchDefinePwr4 = 1 << 6, 871 ArchDefinePwr5 = 1 << 7, 872 ArchDefinePwr5x = 1 << 8, 873 ArchDefinePwr6 = 1 << 9, 874 ArchDefinePwr6x = 1 << 10, 875 ArchDefinePwr7 = 1 << 11, 876 ArchDefinePwr8 = 1 << 12, 877 ArchDefinePwr9 = 1 << 13, 878 ArchDefineA2 = 1 << 14, 879 ArchDefineA2q = 1 << 15 880 } ArchDefineTypes; 881 882 // Note: GCC recognizes the following additional cpus: 883 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 884 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 885 // titan, rs64. 886 bool setCPU(const std::string &Name) override { 887 bool CPUKnown = llvm::StringSwitch<bool>(Name) 888 .Case("generic", true) 889 .Case("440", true) 890 .Case("450", true) 891 .Case("601", true) 892 .Case("602", true) 893 .Case("603", true) 894 .Case("603e", true) 895 .Case("603ev", true) 896 .Case("604", true) 897 .Case("604e", true) 898 .Case("620", true) 899 .Case("630", true) 900 .Case("g3", true) 901 .Case("7400", true) 902 .Case("g4", true) 903 .Case("7450", true) 904 .Case("g4+", true) 905 .Case("750", true) 906 .Case("970", true) 907 .Case("g5", true) 908 .Case("a2", true) 909 .Case("a2q", true) 910 .Case("e500mc", true) 911 .Case("e5500", true) 912 .Case("power3", true) 913 .Case("pwr3", true) 914 .Case("power4", true) 915 .Case("pwr4", true) 916 .Case("power5", true) 917 .Case("pwr5", true) 918 .Case("power5x", true) 919 .Case("pwr5x", true) 920 .Case("power6", true) 921 .Case("pwr6", true) 922 .Case("power6x", true) 923 .Case("pwr6x", true) 924 .Case("power7", true) 925 .Case("pwr7", true) 926 .Case("power8", true) 927 .Case("pwr8", true) 928 .Case("power9", true) 929 .Case("pwr9", true) 930 .Case("powerpc", true) 931 .Case("ppc", true) 932 .Case("powerpc64", true) 933 .Case("ppc64", true) 934 .Case("powerpc64le", true) 935 .Case("ppc64le", true) 936 .Default(false); 937 938 if (CPUKnown) 939 CPU = Name; 940 941 return CPUKnown; 942 } 943 944 945 StringRef getABI() const override { return ABI; } 946 947 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 948 return llvm::makeArrayRef(BuiltinInfo, 949 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 950 } 951 952 bool isCLZForZeroUndef() const override { return false; } 953 954 void getTargetDefines(const LangOptions &Opts, 955 MacroBuilder &Builder) const override; 956 957 bool 958 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 959 StringRef CPU, 960 const std::vector<std::string> &FeaturesVec) const override; 961 962 bool handleTargetFeatures(std::vector<std::string> &Features, 963 DiagnosticsEngine &Diags) override; 964 bool hasFeature(StringRef Feature) const override; 965 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 966 bool Enabled) const override; 967 968 ArrayRef<const char *> getGCCRegNames() const override; 969 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 970 bool validateAsmConstraint(const char *&Name, 971 TargetInfo::ConstraintInfo &Info) const override { 972 switch (*Name) { 973 default: return false; 974 case 'O': // Zero 975 break; 976 case 'b': // Base register 977 case 'f': // Floating point register 978 Info.setAllowsRegister(); 979 break; 980 // FIXME: The following are added to allow parsing. 981 // I just took a guess at what the actions should be. 982 // Also, is more specific checking needed? I.e. specific registers? 983 case 'd': // Floating point register (containing 64-bit value) 984 case 'v': // Altivec vector register 985 Info.setAllowsRegister(); 986 break; 987 case 'w': 988 switch (Name[1]) { 989 case 'd':// VSX vector register to hold vector double data 990 case 'f':// VSX vector register to hold vector float data 991 case 's':// VSX vector register to hold scalar float data 992 case 'a':// Any VSX register 993 case 'c':// An individual CR bit 994 break; 995 default: 996 return false; 997 } 998 Info.setAllowsRegister(); 999 Name++; // Skip over 'w'. 1000 break; 1001 case 'h': // `MQ', `CTR', or `LINK' register 1002 case 'q': // `MQ' register 1003 case 'c': // `CTR' register 1004 case 'l': // `LINK' register 1005 case 'x': // `CR' register (condition register) number 0 1006 case 'y': // `CR' register (condition register) 1007 case 'z': // `XER[CA]' carry bit (part of the XER register) 1008 Info.setAllowsRegister(); 1009 break; 1010 case 'I': // Signed 16-bit constant 1011 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1012 // (use `L' instead for SImode constants) 1013 case 'K': // Unsigned 16-bit constant 1014 case 'L': // Signed 16-bit constant shifted left 16 bits 1015 case 'M': // Constant larger than 31 1016 case 'N': // Exact power of 2 1017 case 'P': // Constant whose negation is a signed 16-bit constant 1018 case 'G': // Floating point constant that can be loaded into a 1019 // register with one instruction per word 1020 case 'H': // Integer/Floating point constant that can be loaded 1021 // into a register using three instructions 1022 break; 1023 case 'm': // Memory operand. Note that on PowerPC targets, m can 1024 // include addresses that update the base register. It 1025 // is therefore only safe to use `m' in an asm statement 1026 // if that asm statement accesses the operand exactly once. 1027 // The asm statement must also use `%U<opno>' as a 1028 // placeholder for the "update" flag in the corresponding 1029 // load or store instruction. For example: 1030 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1031 // is correct but: 1032 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1033 // is not. Use es rather than m if you don't want the base 1034 // register to be updated. 1035 case 'e': 1036 if (Name[1] != 's') 1037 return false; 1038 // es: A "stable" memory operand; that is, one which does not 1039 // include any automodification of the base register. Unlike 1040 // `m', this constraint can be used in asm statements that 1041 // might access the operand several times, or that might not 1042 // access it at all. 1043 Info.setAllowsMemory(); 1044 Name++; // Skip over 'e'. 1045 break; 1046 case 'Q': // Memory operand that is an offset from a register (it is 1047 // usually better to use `m' or `es' in asm statements) 1048 case 'Z': // Memory operand that is an indexed or indirect from a 1049 // register (it is usually better to use `m' or `es' in 1050 // asm statements) 1051 Info.setAllowsMemory(); 1052 Info.setAllowsRegister(); 1053 break; 1054 case 'R': // AIX TOC entry 1055 case 'a': // Address operand that is an indexed or indirect from a 1056 // register (`p' is preferable for asm statements) 1057 case 'S': // Constant suitable as a 64-bit mask operand 1058 case 'T': // Constant suitable as a 32-bit mask operand 1059 case 'U': // System V Release 4 small data area reference 1060 case 't': // AND masks that can be performed by two rldic{l, r} 1061 // instructions 1062 case 'W': // Vector constant that does not require memory 1063 case 'j': // Vector constant that is all zeros. 1064 break; 1065 // End FIXME. 1066 } 1067 return true; 1068 } 1069 std::string convertConstraint(const char *&Constraint) const override { 1070 std::string R; 1071 switch (*Constraint) { 1072 case 'e': 1073 case 'w': 1074 // Two-character constraint; add "^" hint for later parsing. 1075 R = std::string("^") + std::string(Constraint, 2); 1076 Constraint++; 1077 break; 1078 default: 1079 return TargetInfo::convertConstraint(Constraint); 1080 } 1081 return R; 1082 } 1083 const char *getClobbers() const override { 1084 return ""; 1085 } 1086 int getEHDataRegisterNumber(unsigned RegNo) const override { 1087 if (RegNo == 0) return 3; 1088 if (RegNo == 1) return 4; 1089 return -1; 1090 } 1091 1092 bool hasSjLjLowering() const override { 1093 return true; 1094 } 1095 1096 bool useFloat128ManglingForLongDouble() const override { 1097 return LongDoubleWidth == 128 && 1098 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1099 getTriple().isOSBinFormatELF(); 1100 } 1101 }; 1102 1103 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1104 #define BUILTIN(ID, TYPE, ATTRS) \ 1105 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1106 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1107 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1108 #include "clang/Basic/BuiltinsPPC.def" 1109 }; 1110 1111 /// handleTargetFeatures - Perform initialization based on the user 1112 /// configured set of features. 1113 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1114 DiagnosticsEngine &Diags) { 1115 for (const auto &Feature : Features) { 1116 if (Feature == "+vsx") { 1117 HasVSX = true; 1118 } else if (Feature == "+bpermd") { 1119 HasBPERMD = true; 1120 } else if (Feature == "+extdiv") { 1121 HasExtDiv = true; 1122 } else if (Feature == "+power8-vector") { 1123 HasP8Vector = true; 1124 } else if (Feature == "+crypto") { 1125 HasP8Crypto = true; 1126 } else if (Feature == "+direct-move") { 1127 HasDirectMove = true; 1128 } else if (Feature == "+qpx") { 1129 HasQPX = true; 1130 } else if (Feature == "+htm") { 1131 HasHTM = true; 1132 } else if (Feature == "+float128") { 1133 HasFloat128 = true; 1134 } 1135 // TODO: Finish this list and add an assert that we've handled them 1136 // all. 1137 } 1138 1139 return true; 1140 } 1141 1142 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1143 /// #defines that are not tied to a specific subtarget. 1144 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1145 MacroBuilder &Builder) const { 1146 // Target identification. 1147 Builder.defineMacro("__ppc__"); 1148 Builder.defineMacro("__PPC__"); 1149 Builder.defineMacro("_ARCH_PPC"); 1150 Builder.defineMacro("__powerpc__"); 1151 Builder.defineMacro("__POWERPC__"); 1152 if (PointerWidth == 64) { 1153 Builder.defineMacro("_ARCH_PPC64"); 1154 Builder.defineMacro("__powerpc64__"); 1155 Builder.defineMacro("__ppc64__"); 1156 Builder.defineMacro("__PPC64__"); 1157 } 1158 1159 // Target properties. 1160 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1161 Builder.defineMacro("_LITTLE_ENDIAN"); 1162 } else { 1163 if (getTriple().getOS() != llvm::Triple::NetBSD && 1164 getTriple().getOS() != llvm::Triple::OpenBSD) 1165 Builder.defineMacro("_BIG_ENDIAN"); 1166 } 1167 1168 // ABI options. 1169 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1170 Builder.defineMacro("_CALL_ELF", "1"); 1171 if (ABI == "elfv2") 1172 Builder.defineMacro("_CALL_ELF", "2"); 1173 1174 // Subtarget options. 1175 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1176 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1177 1178 // FIXME: Should be controlled by command line option. 1179 if (LongDoubleWidth == 128) 1180 Builder.defineMacro("__LONG_DOUBLE_128__"); 1181 1182 if (Opts.AltiVec) { 1183 Builder.defineMacro("__VEC__", "10206"); 1184 Builder.defineMacro("__ALTIVEC__"); 1185 } 1186 1187 // CPU identification. 1188 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1189 .Case("440", ArchDefineName) 1190 .Case("450", ArchDefineName | ArchDefine440) 1191 .Case("601", ArchDefineName) 1192 .Case("602", ArchDefineName | ArchDefinePpcgr) 1193 .Case("603", ArchDefineName | ArchDefinePpcgr) 1194 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1195 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1196 .Case("604", ArchDefineName | ArchDefinePpcgr) 1197 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1198 .Case("620", ArchDefineName | ArchDefinePpcgr) 1199 .Case("630", ArchDefineName | ArchDefinePpcgr) 1200 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1201 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1202 .Case("750", ArchDefineName | ArchDefinePpcgr) 1203 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1204 | ArchDefinePpcsq) 1205 .Case("a2", ArchDefineA2) 1206 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1207 .Case("pwr3", ArchDefinePpcgr) 1208 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1209 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1210 | ArchDefinePpcsq) 1211 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1212 | ArchDefinePpcgr | ArchDefinePpcsq) 1213 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1214 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1215 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1216 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1217 | ArchDefinePpcsq) 1218 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1219 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1220 | ArchDefinePpcgr | ArchDefinePpcsq) 1221 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1222 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1223 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1224 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 1225 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1226 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1227 | ArchDefinePpcsq) 1228 .Case("power3", ArchDefinePpcgr) 1229 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1230 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1231 | ArchDefinePpcsq) 1232 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1233 | ArchDefinePpcgr | ArchDefinePpcsq) 1234 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1235 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1236 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1237 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1238 | ArchDefinePpcsq) 1239 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1240 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1241 | ArchDefinePpcgr | ArchDefinePpcsq) 1242 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1243 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1244 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1245 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 1246 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1247 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1248 | ArchDefinePpcsq) 1249 .Default(ArchDefineNone); 1250 1251 if (defs & ArchDefineName) 1252 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1253 if (defs & ArchDefinePpcgr) 1254 Builder.defineMacro("_ARCH_PPCGR"); 1255 if (defs & ArchDefinePpcsq) 1256 Builder.defineMacro("_ARCH_PPCSQ"); 1257 if (defs & ArchDefine440) 1258 Builder.defineMacro("_ARCH_440"); 1259 if (defs & ArchDefine603) 1260 Builder.defineMacro("_ARCH_603"); 1261 if (defs & ArchDefine604) 1262 Builder.defineMacro("_ARCH_604"); 1263 if (defs & ArchDefinePwr4) 1264 Builder.defineMacro("_ARCH_PWR4"); 1265 if (defs & ArchDefinePwr5) 1266 Builder.defineMacro("_ARCH_PWR5"); 1267 if (defs & ArchDefinePwr5x) 1268 Builder.defineMacro("_ARCH_PWR5X"); 1269 if (defs & ArchDefinePwr6) 1270 Builder.defineMacro("_ARCH_PWR6"); 1271 if (defs & ArchDefinePwr6x) 1272 Builder.defineMacro("_ARCH_PWR6X"); 1273 if (defs & ArchDefinePwr7) 1274 Builder.defineMacro("_ARCH_PWR7"); 1275 if (defs & ArchDefinePwr8) 1276 Builder.defineMacro("_ARCH_PWR8"); 1277 if (defs & ArchDefinePwr9) 1278 Builder.defineMacro("_ARCH_PWR9"); 1279 if (defs & ArchDefineA2) 1280 Builder.defineMacro("_ARCH_A2"); 1281 if (defs & ArchDefineA2q) { 1282 Builder.defineMacro("_ARCH_A2Q"); 1283 Builder.defineMacro("_ARCH_QP"); 1284 } 1285 1286 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1287 Builder.defineMacro("__bg__"); 1288 Builder.defineMacro("__THW_BLUEGENE__"); 1289 Builder.defineMacro("__bgq__"); 1290 Builder.defineMacro("__TOS_BGQ__"); 1291 } 1292 1293 if (HasVSX) 1294 Builder.defineMacro("__VSX__"); 1295 if (HasP8Vector) 1296 Builder.defineMacro("__POWER8_VECTOR__"); 1297 if (HasP8Crypto) 1298 Builder.defineMacro("__CRYPTO__"); 1299 if (HasHTM) 1300 Builder.defineMacro("__HTM__"); 1301 if (HasFloat128) 1302 Builder.defineMacro("__FLOAT128__"); 1303 1304 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1305 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1306 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1307 if (PointerWidth == 64) 1308 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1309 1310 // FIXME: The following are not yet generated here by Clang, but are 1311 // generated by GCC: 1312 // 1313 // _SOFT_FLOAT_ 1314 // __RECIP_PRECISION__ 1315 // __APPLE_ALTIVEC__ 1316 // __RECIP__ 1317 // __RECIPF__ 1318 // __RSQRTE__ 1319 // __RSQRTEF__ 1320 // _SOFT_DOUBLE_ 1321 // __NO_LWSYNC__ 1322 // __HAVE_BSWAP__ 1323 // __LONGDOUBLE128 1324 // __CMODEL_MEDIUM__ 1325 // __CMODEL_LARGE__ 1326 // _CALL_SYSV 1327 // _CALL_DARWIN 1328 // __NO_FPRS__ 1329 } 1330 1331 // Handle explicit options being passed to the compiler here: if we've 1332 // explicitly turned off vsx and turned on power8-vector or direct-move then 1333 // go ahead and error since the customer has expressed a somewhat incompatible 1334 // set of options. 1335 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1336 const std::vector<std::string> &FeaturesVec) { 1337 1338 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1339 FeaturesVec.end()) { 1340 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1341 FeaturesVec.end()) { 1342 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1343 << "-mno-vsx"; 1344 return false; 1345 } 1346 1347 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1348 FeaturesVec.end()) { 1349 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1350 << "-mno-vsx"; 1351 return false; 1352 } 1353 1354 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1355 FeaturesVec.end()) { 1356 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1357 << "-mno-vsx"; 1358 return false; 1359 } 1360 } 1361 1362 return true; 1363 } 1364 1365 bool PPCTargetInfo::initFeatureMap( 1366 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1367 const std::vector<std::string> &FeaturesVec) const { 1368 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1369 .Case("7400", true) 1370 .Case("g4", true) 1371 .Case("7450", true) 1372 .Case("g4+", true) 1373 .Case("970", true) 1374 .Case("g5", true) 1375 .Case("pwr6", true) 1376 .Case("pwr7", true) 1377 .Case("pwr8", true) 1378 .Case("pwr9", true) 1379 .Case("ppc64", true) 1380 .Case("ppc64le", true) 1381 .Default(false); 1382 1383 Features["qpx"] = (CPU == "a2q"); 1384 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1385 .Case("ppc64le", true) 1386 .Case("pwr9", true) 1387 .Case("pwr8", true) 1388 .Default(false); 1389 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1390 .Case("ppc64le", true) 1391 .Case("pwr9", true) 1392 .Case("pwr8", true) 1393 .Default(false); 1394 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1395 .Case("ppc64le", true) 1396 .Case("pwr9", true) 1397 .Case("pwr8", true) 1398 .Case("pwr7", true) 1399 .Default(false); 1400 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1401 .Case("ppc64le", true) 1402 .Case("pwr9", true) 1403 .Case("pwr8", true) 1404 .Case("pwr7", true) 1405 .Default(false); 1406 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1407 .Case("ppc64le", true) 1408 .Case("pwr9", true) 1409 .Case("pwr8", true) 1410 .Default(false); 1411 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1412 .Case("ppc64le", true) 1413 .Case("pwr9", true) 1414 .Case("pwr8", true) 1415 .Case("pwr7", true) 1416 .Default(false); 1417 1418 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1419 return false; 1420 1421 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1422 } 1423 1424 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1425 return llvm::StringSwitch<bool>(Feature) 1426 .Case("powerpc", true) 1427 .Case("vsx", HasVSX) 1428 .Case("power8-vector", HasP8Vector) 1429 .Case("crypto", HasP8Crypto) 1430 .Case("direct-move", HasDirectMove) 1431 .Case("qpx", HasQPX) 1432 .Case("htm", HasHTM) 1433 .Case("bpermd", HasBPERMD) 1434 .Case("extdiv", HasExtDiv) 1435 .Case("float128", HasFloat128) 1436 .Default(false); 1437 } 1438 1439 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1440 StringRef Name, bool Enabled) const { 1441 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1442 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1443 // incompatible options. 1444 if (Enabled) { 1445 if (Name == "direct-move") { 1446 Features[Name] = Features["vsx"] = true; 1447 } else if (Name == "power8-vector") { 1448 Features[Name] = Features["vsx"] = true; 1449 } else if (Name == "float128") { 1450 Features[Name] = Features["vsx"] = true; 1451 } else { 1452 Features[Name] = true; 1453 } 1454 } else { 1455 if (Name == "vsx") { 1456 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1457 Features["float128"] = false; 1458 } else { 1459 Features[Name] = false; 1460 } 1461 } 1462 } 1463 1464 const char * const PPCTargetInfo::GCCRegNames[] = { 1465 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1466 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1467 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1468 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1469 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1470 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1471 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1472 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1473 "mq", "lr", "ctr", "ap", 1474 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1475 "xer", 1476 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1477 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1478 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1479 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1480 "vrsave", "vscr", 1481 "spe_acc", "spefscr", 1482 "sfp" 1483 }; 1484 1485 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1486 return llvm::makeArrayRef(GCCRegNames); 1487 } 1488 1489 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1490 // While some of these aliases do map to different registers 1491 // they still share the same register name. 1492 { { "0" }, "r0" }, 1493 { { "1"}, "r1" }, 1494 { { "2" }, "r2" }, 1495 { { "3" }, "r3" }, 1496 { { "4" }, "r4" }, 1497 { { "5" }, "r5" }, 1498 { { "6" }, "r6" }, 1499 { { "7" }, "r7" }, 1500 { { "8" }, "r8" }, 1501 { { "9" }, "r9" }, 1502 { { "10" }, "r10" }, 1503 { { "11" }, "r11" }, 1504 { { "12" }, "r12" }, 1505 { { "13" }, "r13" }, 1506 { { "14" }, "r14" }, 1507 { { "15" }, "r15" }, 1508 { { "16" }, "r16" }, 1509 { { "17" }, "r17" }, 1510 { { "18" }, "r18" }, 1511 { { "19" }, "r19" }, 1512 { { "20" }, "r20" }, 1513 { { "21" }, "r21" }, 1514 { { "22" }, "r22" }, 1515 { { "23" }, "r23" }, 1516 { { "24" }, "r24" }, 1517 { { "25" }, "r25" }, 1518 { { "26" }, "r26" }, 1519 { { "27" }, "r27" }, 1520 { { "28" }, "r28" }, 1521 { { "29" }, "r29" }, 1522 { { "30" }, "r30" }, 1523 { { "31" }, "r31" }, 1524 { { "fr0" }, "f0" }, 1525 { { "fr1" }, "f1" }, 1526 { { "fr2" }, "f2" }, 1527 { { "fr3" }, "f3" }, 1528 { { "fr4" }, "f4" }, 1529 { { "fr5" }, "f5" }, 1530 { { "fr6" }, "f6" }, 1531 { { "fr7" }, "f7" }, 1532 { { "fr8" }, "f8" }, 1533 { { "fr9" }, "f9" }, 1534 { { "fr10" }, "f10" }, 1535 { { "fr11" }, "f11" }, 1536 { { "fr12" }, "f12" }, 1537 { { "fr13" }, "f13" }, 1538 { { "fr14" }, "f14" }, 1539 { { "fr15" }, "f15" }, 1540 { { "fr16" }, "f16" }, 1541 { { "fr17" }, "f17" }, 1542 { { "fr18" }, "f18" }, 1543 { { "fr19" }, "f19" }, 1544 { { "fr20" }, "f20" }, 1545 { { "fr21" }, "f21" }, 1546 { { "fr22" }, "f22" }, 1547 { { "fr23" }, "f23" }, 1548 { { "fr24" }, "f24" }, 1549 { { "fr25" }, "f25" }, 1550 { { "fr26" }, "f26" }, 1551 { { "fr27" }, "f27" }, 1552 { { "fr28" }, "f28" }, 1553 { { "fr29" }, "f29" }, 1554 { { "fr30" }, "f30" }, 1555 { { "fr31" }, "f31" }, 1556 { { "cc" }, "cr0" }, 1557 }; 1558 1559 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1560 return llvm::makeArrayRef(GCCRegAliases); 1561 } 1562 1563 class PPC32TargetInfo : public PPCTargetInfo { 1564 public: 1565 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1566 : PPCTargetInfo(Triple, Opts) { 1567 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1568 1569 switch (getTriple().getOS()) { 1570 case llvm::Triple::Linux: 1571 case llvm::Triple::FreeBSD: 1572 case llvm::Triple::NetBSD: 1573 SizeType = UnsignedInt; 1574 PtrDiffType = SignedInt; 1575 IntPtrType = SignedInt; 1576 break; 1577 default: 1578 break; 1579 } 1580 1581 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1582 LongDoubleWidth = LongDoubleAlign = 64; 1583 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1584 } 1585 1586 // PPC32 supports atomics up to 4 bytes. 1587 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1588 } 1589 1590 BuiltinVaListKind getBuiltinVaListKind() const override { 1591 // This is the ELF definition, and is overridden by the Darwin sub-target 1592 return TargetInfo::PowerABIBuiltinVaList; 1593 } 1594 }; 1595 1596 // Note: ABI differences may eventually require us to have a separate 1597 // TargetInfo for little endian. 1598 class PPC64TargetInfo : public PPCTargetInfo { 1599 public: 1600 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1601 : PPCTargetInfo(Triple, Opts) { 1602 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1603 IntMaxType = SignedLong; 1604 Int64Type = SignedLong; 1605 1606 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1607 resetDataLayout("e-m:e-i64:64-n32:64"); 1608 ABI = "elfv2"; 1609 } else { 1610 resetDataLayout("E-m:e-i64:64-n32:64"); 1611 ABI = "elfv1"; 1612 } 1613 1614 switch (getTriple().getOS()) { 1615 case llvm::Triple::FreeBSD: 1616 LongDoubleWidth = LongDoubleAlign = 64; 1617 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1618 break; 1619 case llvm::Triple::NetBSD: 1620 IntMaxType = SignedLongLong; 1621 Int64Type = SignedLongLong; 1622 break; 1623 default: 1624 break; 1625 } 1626 1627 // PPC64 supports atomics up to 8 bytes. 1628 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1629 } 1630 BuiltinVaListKind getBuiltinVaListKind() const override { 1631 return TargetInfo::CharPtrBuiltinVaList; 1632 } 1633 // PPC64 Linux-specific ABI options. 1634 bool setABI(const std::string &Name) override { 1635 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1636 ABI = Name; 1637 return true; 1638 } 1639 return false; 1640 } 1641 }; 1642 1643 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1644 public: 1645 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1646 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1647 HasAlignMac68kSupport = true; 1648 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1649 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1650 LongLongAlign = 32; 1651 SuitableAlign = 128; 1652 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1653 } 1654 BuiltinVaListKind getBuiltinVaListKind() const override { 1655 return TargetInfo::CharPtrBuiltinVaList; 1656 } 1657 }; 1658 1659 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1660 public: 1661 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1662 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1663 HasAlignMac68kSupport = true; 1664 SuitableAlign = 128; 1665 resetDataLayout("E-m:o-i64:64-n32:64"); 1666 } 1667 }; 1668 1669 static const unsigned NVPTXAddrSpaceMap[] = { 1670 1, // opencl_global 1671 3, // opencl_local 1672 4, // opencl_constant 1673 // FIXME: generic has to be added to the target 1674 0, // opencl_generic 1675 1, // cuda_device 1676 4, // cuda_constant 1677 3, // cuda_shared 1678 }; 1679 1680 class NVPTXTargetInfo : public TargetInfo { 1681 static const char *const GCCRegNames[]; 1682 static const Builtin::Info BuiltinInfo[]; 1683 1684 // The GPU profiles supported by the NVPTX backend 1685 enum GPUKind { 1686 GK_NONE, 1687 GK_SM20, 1688 GK_SM21, 1689 GK_SM30, 1690 GK_SM35, 1691 GK_SM37, 1692 } GPU; 1693 1694 public: 1695 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1696 : TargetInfo(Triple) { 1697 BigEndian = false; 1698 TLSSupported = false; 1699 LongWidth = LongAlign = 64; 1700 AddrSpaceMap = &NVPTXAddrSpaceMap; 1701 UseAddrSpaceMapMangling = true; 1702 // Define available target features 1703 // These must be defined in sorted order! 1704 NoAsmVariants = true; 1705 // Set the default GPU to sm20 1706 GPU = GK_SM20; 1707 1708 // If possible, get a TargetInfo for our host triple, so we can match its 1709 // types. 1710 llvm::Triple HostTriple(Opts.HostTriple); 1711 if (HostTriple.isNVPTX()) 1712 return; 1713 std::unique_ptr<TargetInfo> HostTarget( 1714 AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1715 if (!HostTarget) { 1716 return; 1717 } 1718 1719 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1720 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1721 BoolWidth = HostTarget->getBoolWidth(); 1722 BoolAlign = HostTarget->getBoolAlign(); 1723 IntWidth = HostTarget->getIntWidth(); 1724 IntAlign = HostTarget->getIntAlign(); 1725 HalfWidth = HostTarget->getHalfWidth(); 1726 HalfAlign = HostTarget->getHalfAlign(); 1727 FloatWidth = HostTarget->getFloatWidth(); 1728 FloatAlign = HostTarget->getFloatAlign(); 1729 DoubleWidth = HostTarget->getDoubleWidth(); 1730 DoubleAlign = HostTarget->getDoubleAlign(); 1731 LongWidth = HostTarget->getLongWidth(); 1732 LongAlign = HostTarget->getLongAlign(); 1733 LongLongWidth = HostTarget->getLongLongWidth(); 1734 LongLongAlign = HostTarget->getLongLongAlign(); 1735 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1736 DefaultAlignForAttributeAligned = 1737 HostTarget->getDefaultAlignForAttributeAligned(); 1738 SizeType = HostTarget->getSizeType(); 1739 IntMaxType = HostTarget->getIntMaxType(); 1740 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1741 IntPtrType = HostTarget->getIntPtrType(); 1742 WCharType = HostTarget->getWCharType(); 1743 WIntType = HostTarget->getWIntType(); 1744 Char16Type = HostTarget->getChar16Type(); 1745 Char32Type = HostTarget->getChar32Type(); 1746 Int64Type = HostTarget->getInt64Type(); 1747 SigAtomicType = HostTarget->getSigAtomicType(); 1748 ProcessIDType = HostTarget->getProcessIDType(); 1749 1750 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1751 UseZeroLengthBitfieldAlignment = 1752 HostTarget->useZeroLengthBitfieldAlignment(); 1753 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1754 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1755 1756 // Properties intentionally not copied from host: 1757 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1758 // host/device boundary. 1759 // - SuitableAlign: Not visible across the host/device boundary, and may 1760 // correctly be different on host/device, e.g. if host has wider vector 1761 // types than device. 1762 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1763 // as its double type, but that's not necessarily true on the host. 1764 // TODO: nvcc emits a warning when using long double on device; we should 1765 // do the same. 1766 } 1767 void getTargetDefines(const LangOptions &Opts, 1768 MacroBuilder &Builder) const override { 1769 Builder.defineMacro("__PTX__"); 1770 Builder.defineMacro("__NVPTX__"); 1771 if (Opts.CUDAIsDevice) { 1772 // Set __CUDA_ARCH__ for the GPU specified. 1773 std::string CUDAArchCode; 1774 switch (GPU) { 1775 case GK_SM20: 1776 CUDAArchCode = "200"; 1777 break; 1778 case GK_SM21: 1779 CUDAArchCode = "210"; 1780 break; 1781 case GK_SM30: 1782 CUDAArchCode = "300"; 1783 break; 1784 case GK_SM35: 1785 CUDAArchCode = "350"; 1786 break; 1787 case GK_SM37: 1788 CUDAArchCode = "370"; 1789 break; 1790 default: 1791 llvm_unreachable("Unhandled target CPU"); 1792 } 1793 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1794 } 1795 } 1796 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1797 return llvm::makeArrayRef(BuiltinInfo, 1798 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1799 } 1800 bool hasFeature(StringRef Feature) const override { 1801 return Feature == "ptx" || Feature == "nvptx"; 1802 } 1803 1804 ArrayRef<const char *> getGCCRegNames() const override; 1805 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1806 // No aliases. 1807 return None; 1808 } 1809 bool validateAsmConstraint(const char *&Name, 1810 TargetInfo::ConstraintInfo &Info) const override { 1811 switch (*Name) { 1812 default: 1813 return false; 1814 case 'c': 1815 case 'h': 1816 case 'r': 1817 case 'l': 1818 case 'f': 1819 case 'd': 1820 Info.setAllowsRegister(); 1821 return true; 1822 } 1823 } 1824 const char *getClobbers() const override { 1825 // FIXME: Is this really right? 1826 return ""; 1827 } 1828 BuiltinVaListKind getBuiltinVaListKind() const override { 1829 // FIXME: implement 1830 return TargetInfo::CharPtrBuiltinVaList; 1831 } 1832 bool setCPU(const std::string &Name) override { 1833 GPU = llvm::StringSwitch<GPUKind>(Name) 1834 .Case("sm_20", GK_SM20) 1835 .Case("sm_21", GK_SM21) 1836 .Case("sm_30", GK_SM30) 1837 .Case("sm_35", GK_SM35) 1838 .Case("sm_37", GK_SM37) 1839 .Default(GK_NONE); 1840 1841 return GPU != GK_NONE; 1842 } 1843 }; 1844 1845 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1846 #define BUILTIN(ID, TYPE, ATTRS) \ 1847 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1848 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1849 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1850 #include "clang/Basic/BuiltinsNVPTX.def" 1851 }; 1852 1853 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1854 1855 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1856 return llvm::makeArrayRef(GCCRegNames); 1857 } 1858 1859 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1860 public: 1861 NVPTX32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1862 : NVPTXTargetInfo(Triple, Opts) { 1863 LongWidth = LongAlign = 32; 1864 PointerWidth = PointerAlign = 32; 1865 SizeType = TargetInfo::UnsignedInt; 1866 PtrDiffType = TargetInfo::SignedInt; 1867 IntPtrType = TargetInfo::SignedInt; 1868 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1869 } 1870 }; 1871 1872 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1873 public: 1874 NVPTX64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1875 : NVPTXTargetInfo(Triple, Opts) { 1876 PointerWidth = PointerAlign = 64; 1877 SizeType = TargetInfo::UnsignedLong; 1878 PtrDiffType = TargetInfo::SignedLong; 1879 IntPtrType = TargetInfo::SignedLong; 1880 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1881 } 1882 }; 1883 1884 static const unsigned AMDGPUAddrSpaceMap[] = { 1885 1, // opencl_global 1886 3, // opencl_local 1887 2, // opencl_constant 1888 4, // opencl_generic 1889 1, // cuda_device 1890 2, // cuda_constant 1891 3 // cuda_shared 1892 }; 1893 1894 // If you edit the description strings, make sure you update 1895 // getPointerWidthV(). 1896 1897 static const char *const DataLayoutStringR600 = 1898 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1899 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1900 1901 static const char *const DataLayoutStringSI = 1902 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1903 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1904 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1905 1906 class AMDGPUTargetInfo : public TargetInfo { 1907 static const Builtin::Info BuiltinInfo[]; 1908 static const char * const GCCRegNames[]; 1909 1910 /// \brief The GPU profiles supported by the AMDGPU target. 1911 enum GPUKind { 1912 GK_NONE, 1913 GK_R600, 1914 GK_R600_DOUBLE_OPS, 1915 GK_R700, 1916 GK_R700_DOUBLE_OPS, 1917 GK_EVERGREEN, 1918 GK_EVERGREEN_DOUBLE_OPS, 1919 GK_NORTHERN_ISLANDS, 1920 GK_CAYMAN, 1921 GK_SOUTHERN_ISLANDS, 1922 GK_SEA_ISLANDS, 1923 GK_VOLCANIC_ISLANDS 1924 } GPU; 1925 1926 bool hasFP64:1; 1927 bool hasFMAF:1; 1928 bool hasLDEXPF:1; 1929 1930 public: 1931 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 1932 : TargetInfo(Triple) { 1933 if (Triple.getArch() == llvm::Triple::amdgcn) { 1934 resetDataLayout(DataLayoutStringSI); 1935 GPU = GK_SOUTHERN_ISLANDS; 1936 hasFP64 = true; 1937 hasFMAF = true; 1938 hasLDEXPF = true; 1939 } else { 1940 resetDataLayout(DataLayoutStringR600); 1941 GPU = GK_R600; 1942 hasFP64 = false; 1943 hasFMAF = false; 1944 hasLDEXPF = false; 1945 } 1946 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1947 UseAddrSpaceMapMangling = true; 1948 } 1949 1950 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1951 if (GPU <= GK_CAYMAN) 1952 return 32; 1953 1954 switch(AddrSpace) { 1955 default: 1956 return 64; 1957 case 0: 1958 case 3: 1959 case 5: 1960 return 32; 1961 } 1962 } 1963 1964 const char * getClobbers() const override { 1965 return ""; 1966 } 1967 1968 ArrayRef<const char *> getGCCRegNames() const override; 1969 1970 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1971 return None; 1972 } 1973 1974 bool validateAsmConstraint(const char *&Name, 1975 TargetInfo::ConstraintInfo &Info) const override { 1976 switch (*Name) { 1977 default: break; 1978 case 'v': // vgpr 1979 case 's': // sgpr 1980 Info.setAllowsRegister(); 1981 return true; 1982 } 1983 return false; 1984 } 1985 1986 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1987 return llvm::makeArrayRef(BuiltinInfo, 1988 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 1989 } 1990 1991 void getTargetDefines(const LangOptions &Opts, 1992 MacroBuilder &Builder) const override { 1993 if (getTriple().getArch() == llvm::Triple::amdgcn) 1994 Builder.defineMacro("__AMDGCN__"); 1995 else 1996 Builder.defineMacro("__R600__"); 1997 1998 if (hasFMAF) 1999 Builder.defineMacro("__HAS_FMAF__"); 2000 if (hasLDEXPF) 2001 Builder.defineMacro("__HAS_LDEXPF__"); 2002 if (hasFP64 && Opts.OpenCL) 2003 Builder.defineMacro("cl_khr_fp64"); 2004 if (Opts.OpenCL) { 2005 if (GPU >= GK_NORTHERN_ISLANDS) { 2006 Builder.defineMacro("cl_khr_byte_addressable_store"); 2007 Builder.defineMacro("cl_khr_global_int32_base_atomics"); 2008 Builder.defineMacro("cl_khr_global_int32_extended_atomics"); 2009 Builder.defineMacro("cl_khr_local_int32_base_atomics"); 2010 Builder.defineMacro("cl_khr_local_int32_extended_atomics"); 2011 } 2012 } 2013 } 2014 2015 BuiltinVaListKind getBuiltinVaListKind() const override { 2016 return TargetInfo::CharPtrBuiltinVaList; 2017 } 2018 2019 bool setCPU(const std::string &Name) override { 2020 GPU = llvm::StringSwitch<GPUKind>(Name) 2021 .Case("r600" , GK_R600) 2022 .Case("rv610", GK_R600) 2023 .Case("rv620", GK_R600) 2024 .Case("rv630", GK_R600) 2025 .Case("rv635", GK_R600) 2026 .Case("rs780", GK_R600) 2027 .Case("rs880", GK_R600) 2028 .Case("rv670", GK_R600_DOUBLE_OPS) 2029 .Case("rv710", GK_R700) 2030 .Case("rv730", GK_R700) 2031 .Case("rv740", GK_R700_DOUBLE_OPS) 2032 .Case("rv770", GK_R700_DOUBLE_OPS) 2033 .Case("palm", GK_EVERGREEN) 2034 .Case("cedar", GK_EVERGREEN) 2035 .Case("sumo", GK_EVERGREEN) 2036 .Case("sumo2", GK_EVERGREEN) 2037 .Case("redwood", GK_EVERGREEN) 2038 .Case("juniper", GK_EVERGREEN) 2039 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2040 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2041 .Case("barts", GK_NORTHERN_ISLANDS) 2042 .Case("turks", GK_NORTHERN_ISLANDS) 2043 .Case("caicos", GK_NORTHERN_ISLANDS) 2044 .Case("cayman", GK_CAYMAN) 2045 .Case("aruba", GK_CAYMAN) 2046 .Case("tahiti", GK_SOUTHERN_ISLANDS) 2047 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 2048 .Case("verde", GK_SOUTHERN_ISLANDS) 2049 .Case("oland", GK_SOUTHERN_ISLANDS) 2050 .Case("hainan", GK_SOUTHERN_ISLANDS) 2051 .Case("bonaire", GK_SEA_ISLANDS) 2052 .Case("kabini", GK_SEA_ISLANDS) 2053 .Case("kaveri", GK_SEA_ISLANDS) 2054 .Case("hawaii", GK_SEA_ISLANDS) 2055 .Case("mullins", GK_SEA_ISLANDS) 2056 .Case("tonga", GK_VOLCANIC_ISLANDS) 2057 .Case("iceland", GK_VOLCANIC_ISLANDS) 2058 .Case("carrizo", GK_VOLCANIC_ISLANDS) 2059 .Case("fiji", GK_VOLCANIC_ISLANDS) 2060 .Case("stoney", GK_VOLCANIC_ISLANDS) 2061 .Default(GK_NONE); 2062 2063 if (GPU == GK_NONE) { 2064 return false; 2065 } 2066 2067 // Set the correct data layout 2068 switch (GPU) { 2069 case GK_NONE: 2070 case GK_R600: 2071 case GK_R700: 2072 case GK_EVERGREEN: 2073 case GK_NORTHERN_ISLANDS: 2074 resetDataLayout(DataLayoutStringR600); 2075 hasFP64 = false; 2076 hasFMAF = false; 2077 hasLDEXPF = false; 2078 break; 2079 case GK_R600_DOUBLE_OPS: 2080 case GK_R700_DOUBLE_OPS: 2081 case GK_EVERGREEN_DOUBLE_OPS: 2082 case GK_CAYMAN: 2083 resetDataLayout(DataLayoutStringR600); 2084 hasFP64 = true; 2085 hasFMAF = true; 2086 hasLDEXPF = false; 2087 break; 2088 case GK_SOUTHERN_ISLANDS: 2089 case GK_SEA_ISLANDS: 2090 case GK_VOLCANIC_ISLANDS: 2091 resetDataLayout(DataLayoutStringSI); 2092 hasFP64 = true; 2093 hasFMAF = true; 2094 hasLDEXPF = true; 2095 break; 2096 } 2097 2098 return true; 2099 } 2100 }; 2101 2102 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2103 #define BUILTIN(ID, TYPE, ATTRS) \ 2104 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2105 #include "clang/Basic/BuiltinsAMDGPU.def" 2106 }; 2107 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2108 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2109 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2110 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2111 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2112 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2113 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2114 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2115 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2116 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2117 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2118 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2119 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2120 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2121 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2122 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2123 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2124 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2125 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2126 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2127 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2128 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2129 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2130 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2131 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2132 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2133 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2134 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2135 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2136 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2137 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2138 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2139 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2140 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2141 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2142 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2143 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2144 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2145 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2146 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2147 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2148 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2149 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2150 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2151 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2152 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2153 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2154 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2155 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2156 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2157 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2158 }; 2159 2160 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2161 return llvm::makeArrayRef(GCCRegNames); 2162 } 2163 2164 // Namespace for x86 abstract base class 2165 const Builtin::Info BuiltinInfo[] = { 2166 #define BUILTIN(ID, TYPE, ATTRS) \ 2167 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2168 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2169 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2170 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2171 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2172 #include "clang/Basic/BuiltinsX86.def" 2173 }; 2174 2175 static const char* const GCCRegNames[] = { 2176 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2177 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2178 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2179 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2180 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2181 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2182 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2183 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2184 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2185 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2186 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2187 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2188 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2189 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2190 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2191 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2192 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2193 }; 2194 2195 const TargetInfo::AddlRegName AddlRegNames[] = { 2196 { { "al", "ah", "eax", "rax" }, 0 }, 2197 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2198 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2199 { { "dl", "dh", "edx", "rdx" }, 1 }, 2200 { { "esi", "rsi" }, 4 }, 2201 { { "edi", "rdi" }, 5 }, 2202 { { "esp", "rsp" }, 7 }, 2203 { { "ebp", "rbp" }, 6 }, 2204 { { "r8d", "r8w", "r8b" }, 38 }, 2205 { { "r9d", "r9w", "r9b" }, 39 }, 2206 { { "r10d", "r10w", "r10b" }, 40 }, 2207 { { "r11d", "r11w", "r11b" }, 41 }, 2208 { { "r12d", "r12w", "r12b" }, 42 }, 2209 { { "r13d", "r13w", "r13b" }, 43 }, 2210 { { "r14d", "r14w", "r14b" }, 44 }, 2211 { { "r15d", "r15w", "r15b" }, 45 }, 2212 }; 2213 2214 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2215 // most of the implementation can be shared. 2216 class X86TargetInfo : public TargetInfo { 2217 enum X86SSEEnum { 2218 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2219 } SSELevel = NoSSE; 2220 enum MMX3DNowEnum { 2221 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2222 } MMX3DNowLevel = NoMMX3DNow; 2223 enum XOPEnum { 2224 NoXOP, 2225 SSE4A, 2226 FMA4, 2227 XOP 2228 } XOPLevel = NoXOP; 2229 2230 bool HasAES = false; 2231 bool HasPCLMUL = false; 2232 bool HasLZCNT = false; 2233 bool HasRDRND = false; 2234 bool HasFSGSBASE = false; 2235 bool HasBMI = false; 2236 bool HasBMI2 = false; 2237 bool HasPOPCNT = false; 2238 bool HasRTM = false; 2239 bool HasPRFCHW = false; 2240 bool HasRDSEED = false; 2241 bool HasADX = false; 2242 bool HasTBM = false; 2243 bool HasFMA = false; 2244 bool HasF16C = false; 2245 bool HasAVX512CD = false; 2246 bool HasAVX512ER = false; 2247 bool HasAVX512PF = false; 2248 bool HasAVX512DQ = false; 2249 bool HasAVX512BW = false; 2250 bool HasAVX512VL = false; 2251 bool HasAVX512VBMI = false; 2252 bool HasAVX512IFMA = false; 2253 bool HasSHA = false; 2254 bool HasMPX = false; 2255 bool HasSGX = false; 2256 bool HasCX16 = false; 2257 bool HasFXSR = false; 2258 bool HasXSAVE = false; 2259 bool HasXSAVEOPT = false; 2260 bool HasXSAVEC = false; 2261 bool HasXSAVES = false; 2262 bool HasPKU = false; 2263 bool HasCLFLUSHOPT = false; 2264 bool HasPCOMMIT = false; 2265 bool HasCLWB = false; 2266 bool HasUMIP = false; 2267 bool HasMOVBE = false; 2268 bool HasPREFETCHWT1 = false; 2269 2270 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2271 /// 2272 /// Each enumeration represents a particular CPU supported by Clang. These 2273 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2274 enum CPUKind { 2275 CK_Generic, 2276 2277 /// \name i386 2278 /// i386-generation processors. 2279 //@{ 2280 CK_i386, 2281 //@} 2282 2283 /// \name i486 2284 /// i486-generation processors. 2285 //@{ 2286 CK_i486, 2287 CK_WinChipC6, 2288 CK_WinChip2, 2289 CK_C3, 2290 //@} 2291 2292 /// \name i586 2293 /// i586-generation processors, P5 microarchitecture based. 2294 //@{ 2295 CK_i586, 2296 CK_Pentium, 2297 CK_PentiumMMX, 2298 //@} 2299 2300 /// \name i686 2301 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2302 //@{ 2303 CK_i686, 2304 CK_PentiumPro, 2305 CK_Pentium2, 2306 CK_Pentium3, 2307 CK_Pentium3M, 2308 CK_PentiumM, 2309 CK_C3_2, 2310 2311 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2312 /// Clang however has some logic to suport this. 2313 // FIXME: Warn, deprecate, and potentially remove this. 2314 CK_Yonah, 2315 //@} 2316 2317 /// \name Netburst 2318 /// Netburst microarchitecture based processors. 2319 //@{ 2320 CK_Pentium4, 2321 CK_Pentium4M, 2322 CK_Prescott, 2323 CK_Nocona, 2324 //@} 2325 2326 /// \name Core 2327 /// Core microarchitecture based processors. 2328 //@{ 2329 CK_Core2, 2330 2331 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2332 /// codename which GCC no longer accepts as an option to -march, but Clang 2333 /// has some logic for recognizing it. 2334 // FIXME: Warn, deprecate, and potentially remove this. 2335 CK_Penryn, 2336 //@} 2337 2338 /// \name Atom 2339 /// Atom processors 2340 //@{ 2341 CK_Bonnell, 2342 CK_Silvermont, 2343 //@} 2344 2345 /// \name Nehalem 2346 /// Nehalem microarchitecture based processors. 2347 CK_Nehalem, 2348 2349 /// \name Westmere 2350 /// Westmere microarchitecture based processors. 2351 CK_Westmere, 2352 2353 /// \name Sandy Bridge 2354 /// Sandy Bridge microarchitecture based processors. 2355 CK_SandyBridge, 2356 2357 /// \name Ivy Bridge 2358 /// Ivy Bridge microarchitecture based processors. 2359 CK_IvyBridge, 2360 2361 /// \name Haswell 2362 /// Haswell microarchitecture based processors. 2363 CK_Haswell, 2364 2365 /// \name Broadwell 2366 /// Broadwell microarchitecture based processors. 2367 CK_Broadwell, 2368 2369 /// \name Skylake Client 2370 /// Skylake client microarchitecture based processors. 2371 CK_SkylakeClient, 2372 2373 /// \name Skylake Server 2374 /// Skylake server microarchitecture based processors. 2375 CK_SkylakeServer, 2376 2377 /// \name Cannonlake Client 2378 /// Cannonlake client microarchitecture based processors. 2379 CK_Cannonlake, 2380 2381 /// \name Knights Landing 2382 /// Knights Landing processor. 2383 CK_KNL, 2384 2385 /// \name Lakemont 2386 /// Lakemont microarchitecture based processors. 2387 CK_Lakemont, 2388 2389 /// \name K6 2390 /// K6 architecture processors. 2391 //@{ 2392 CK_K6, 2393 CK_K6_2, 2394 CK_K6_3, 2395 //@} 2396 2397 /// \name K7 2398 /// K7 architecture processors. 2399 //@{ 2400 CK_Athlon, 2401 CK_AthlonThunderbird, 2402 CK_Athlon4, 2403 CK_AthlonXP, 2404 CK_AthlonMP, 2405 //@} 2406 2407 /// \name K8 2408 /// K8 architecture processors. 2409 //@{ 2410 CK_Athlon64, 2411 CK_Athlon64SSE3, 2412 CK_AthlonFX, 2413 CK_K8, 2414 CK_K8SSE3, 2415 CK_Opteron, 2416 CK_OpteronSSE3, 2417 CK_AMDFAM10, 2418 //@} 2419 2420 /// \name Bobcat 2421 /// Bobcat architecture processors. 2422 //@{ 2423 CK_BTVER1, 2424 CK_BTVER2, 2425 //@} 2426 2427 /// \name Bulldozer 2428 /// Bulldozer architecture processors. 2429 //@{ 2430 CK_BDVER1, 2431 CK_BDVER2, 2432 CK_BDVER3, 2433 CK_BDVER4, 2434 //@} 2435 2436 /// This specification is deprecated and will be removed in the future. 2437 /// Users should prefer \see CK_K8. 2438 // FIXME: Warn on this when the CPU is set to it. 2439 //@{ 2440 CK_x86_64, 2441 //@} 2442 2443 /// \name Geode 2444 /// Geode processors. 2445 //@{ 2446 CK_Geode 2447 //@} 2448 } CPU = CK_Generic; 2449 2450 CPUKind getCPUKind(StringRef CPU) const { 2451 return llvm::StringSwitch<CPUKind>(CPU) 2452 .Case("i386", CK_i386) 2453 .Case("i486", CK_i486) 2454 .Case("winchip-c6", CK_WinChipC6) 2455 .Case("winchip2", CK_WinChip2) 2456 .Case("c3", CK_C3) 2457 .Case("i586", CK_i586) 2458 .Case("pentium", CK_Pentium) 2459 .Case("pentium-mmx", CK_PentiumMMX) 2460 .Case("i686", CK_i686) 2461 .Case("pentiumpro", CK_PentiumPro) 2462 .Case("pentium2", CK_Pentium2) 2463 .Case("pentium3", CK_Pentium3) 2464 .Case("pentium3m", CK_Pentium3M) 2465 .Case("pentium-m", CK_PentiumM) 2466 .Case("c3-2", CK_C3_2) 2467 .Case("yonah", CK_Yonah) 2468 .Case("pentium4", CK_Pentium4) 2469 .Case("pentium4m", CK_Pentium4M) 2470 .Case("prescott", CK_Prescott) 2471 .Case("nocona", CK_Nocona) 2472 .Case("core2", CK_Core2) 2473 .Case("penryn", CK_Penryn) 2474 .Case("bonnell", CK_Bonnell) 2475 .Case("atom", CK_Bonnell) // Legacy name. 2476 .Case("silvermont", CK_Silvermont) 2477 .Case("slm", CK_Silvermont) // Legacy name. 2478 .Case("nehalem", CK_Nehalem) 2479 .Case("corei7", CK_Nehalem) // Legacy name. 2480 .Case("westmere", CK_Westmere) 2481 .Case("sandybridge", CK_SandyBridge) 2482 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2483 .Case("ivybridge", CK_IvyBridge) 2484 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2485 .Case("haswell", CK_Haswell) 2486 .Case("core-avx2", CK_Haswell) // Legacy name. 2487 .Case("broadwell", CK_Broadwell) 2488 .Case("skylake", CK_SkylakeClient) 2489 .Case("skylake-avx512", CK_SkylakeServer) 2490 .Case("skx", CK_SkylakeServer) // Legacy name. 2491 .Case("cannonlake", CK_Cannonlake) 2492 .Case("knl", CK_KNL) 2493 .Case("lakemont", CK_Lakemont) 2494 .Case("k6", CK_K6) 2495 .Case("k6-2", CK_K6_2) 2496 .Case("k6-3", CK_K6_3) 2497 .Case("athlon", CK_Athlon) 2498 .Case("athlon-tbird", CK_AthlonThunderbird) 2499 .Case("athlon-4", CK_Athlon4) 2500 .Case("athlon-xp", CK_AthlonXP) 2501 .Case("athlon-mp", CK_AthlonMP) 2502 .Case("athlon64", CK_Athlon64) 2503 .Case("athlon64-sse3", CK_Athlon64SSE3) 2504 .Case("athlon-fx", CK_AthlonFX) 2505 .Case("k8", CK_K8) 2506 .Case("k8-sse3", CK_K8SSE3) 2507 .Case("opteron", CK_Opteron) 2508 .Case("opteron-sse3", CK_OpteronSSE3) 2509 .Case("barcelona", CK_AMDFAM10) 2510 .Case("amdfam10", CK_AMDFAM10) 2511 .Case("btver1", CK_BTVER1) 2512 .Case("btver2", CK_BTVER2) 2513 .Case("bdver1", CK_BDVER1) 2514 .Case("bdver2", CK_BDVER2) 2515 .Case("bdver3", CK_BDVER3) 2516 .Case("bdver4", CK_BDVER4) 2517 .Case("x86-64", CK_x86_64) 2518 .Case("geode", CK_Geode) 2519 .Default(CK_Generic); 2520 } 2521 2522 enum FPMathKind { 2523 FP_Default, 2524 FP_SSE, 2525 FP_387 2526 } FPMath = FP_Default; 2527 2528 public: 2529 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2530 : TargetInfo(Triple) { 2531 BigEndian = false; 2532 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2533 } 2534 unsigned getFloatEvalMethod() const override { 2535 // X87 evaluates with 80 bits "long double" precision. 2536 return SSELevel == NoSSE ? 2 : 0; 2537 } 2538 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2539 return llvm::makeArrayRef(BuiltinInfo, 2540 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2541 } 2542 ArrayRef<const char *> getGCCRegNames() const override { 2543 return llvm::makeArrayRef(GCCRegNames); 2544 } 2545 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2546 return None; 2547 } 2548 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2549 return llvm::makeArrayRef(AddlRegNames); 2550 } 2551 bool validateCpuSupports(StringRef Name) const override; 2552 bool validateAsmConstraint(const char *&Name, 2553 TargetInfo::ConstraintInfo &info) const override; 2554 2555 bool validateGlobalRegisterVariable(StringRef RegName, 2556 unsigned RegSize, 2557 bool &HasSizeMismatch) const override { 2558 // esp and ebp are the only 32-bit registers the x86 backend can currently 2559 // handle. 2560 if (RegName.equals("esp") || RegName.equals("ebp")) { 2561 // Check that the register size is 32-bit. 2562 HasSizeMismatch = RegSize != 32; 2563 return true; 2564 } 2565 2566 return false; 2567 } 2568 2569 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2570 2571 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2572 2573 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2574 2575 std::string convertConstraint(const char *&Constraint) const override; 2576 const char *getClobbers() const override { 2577 return "~{dirflag},~{fpsr},~{flags}"; 2578 } 2579 void getTargetDefines(const LangOptions &Opts, 2580 MacroBuilder &Builder) const override; 2581 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2582 bool Enabled); 2583 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2584 bool Enabled); 2585 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2586 bool Enabled); 2587 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2588 StringRef Name, bool Enabled) const override { 2589 setFeatureEnabledImpl(Features, Name, Enabled); 2590 } 2591 // This exists purely to cut down on the number of virtual calls in 2592 // initFeatureMap which calls this repeatedly. 2593 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2594 StringRef Name, bool Enabled); 2595 bool 2596 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2597 StringRef CPU, 2598 const std::vector<std::string> &FeaturesVec) const override; 2599 bool hasFeature(StringRef Feature) const override; 2600 bool handleTargetFeatures(std::vector<std::string> &Features, 2601 DiagnosticsEngine &Diags) override; 2602 StringRef getABI() const override { 2603 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2604 return "avx512"; 2605 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2606 return "avx"; 2607 if (getTriple().getArch() == llvm::Triple::x86 && 2608 MMX3DNowLevel == NoMMX3DNow) 2609 return "no-mmx"; 2610 return ""; 2611 } 2612 bool setCPU(const std::string &Name) override { 2613 CPU = getCPUKind(Name); 2614 2615 // Perform any per-CPU checks necessary to determine if this CPU is 2616 // acceptable. 2617 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2618 // invalid without explaining *why*. 2619 switch (CPU) { 2620 case CK_Generic: 2621 // No processor selected! 2622 return false; 2623 2624 case CK_i386: 2625 case CK_i486: 2626 case CK_WinChipC6: 2627 case CK_WinChip2: 2628 case CK_C3: 2629 case CK_i586: 2630 case CK_Pentium: 2631 case CK_PentiumMMX: 2632 case CK_i686: 2633 case CK_PentiumPro: 2634 case CK_Pentium2: 2635 case CK_Pentium3: 2636 case CK_Pentium3M: 2637 case CK_PentiumM: 2638 case CK_Yonah: 2639 case CK_C3_2: 2640 case CK_Pentium4: 2641 case CK_Pentium4M: 2642 case CK_Lakemont: 2643 case CK_Prescott: 2644 case CK_K6: 2645 case CK_K6_2: 2646 case CK_K6_3: 2647 case CK_Athlon: 2648 case CK_AthlonThunderbird: 2649 case CK_Athlon4: 2650 case CK_AthlonXP: 2651 case CK_AthlonMP: 2652 case CK_Geode: 2653 // Only accept certain architectures when compiling in 32-bit mode. 2654 if (getTriple().getArch() != llvm::Triple::x86) 2655 return false; 2656 2657 // Fallthrough 2658 case CK_Nocona: 2659 case CK_Core2: 2660 case CK_Penryn: 2661 case CK_Bonnell: 2662 case CK_Silvermont: 2663 case CK_Nehalem: 2664 case CK_Westmere: 2665 case CK_SandyBridge: 2666 case CK_IvyBridge: 2667 case CK_Haswell: 2668 case CK_Broadwell: 2669 case CK_SkylakeClient: 2670 case CK_SkylakeServer: 2671 case CK_Cannonlake: 2672 case CK_KNL: 2673 case CK_Athlon64: 2674 case CK_Athlon64SSE3: 2675 case CK_AthlonFX: 2676 case CK_K8: 2677 case CK_K8SSE3: 2678 case CK_Opteron: 2679 case CK_OpteronSSE3: 2680 case CK_AMDFAM10: 2681 case CK_BTVER1: 2682 case CK_BTVER2: 2683 case CK_BDVER1: 2684 case CK_BDVER2: 2685 case CK_BDVER3: 2686 case CK_BDVER4: 2687 case CK_x86_64: 2688 return true; 2689 } 2690 llvm_unreachable("Unhandled CPU kind"); 2691 } 2692 2693 bool setFPMath(StringRef Name) override; 2694 2695 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2696 // Most of the non-ARM calling conventions are i386 conventions. 2697 switch (CC) { 2698 case CC_X86ThisCall: 2699 case CC_X86FastCall: 2700 case CC_X86StdCall: 2701 case CC_X86VectorCall: 2702 case CC_C: 2703 case CC_Swift: 2704 case CC_X86Pascal: 2705 case CC_IntelOclBicc: 2706 return CCCR_OK; 2707 default: 2708 return CCCR_Warning; 2709 } 2710 } 2711 2712 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2713 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2714 } 2715 2716 bool hasSjLjLowering() const override { 2717 return true; 2718 } 2719 }; 2720 2721 bool X86TargetInfo::setFPMath(StringRef Name) { 2722 if (Name == "387") { 2723 FPMath = FP_387; 2724 return true; 2725 } 2726 if (Name == "sse") { 2727 FPMath = FP_SSE; 2728 return true; 2729 } 2730 return false; 2731 } 2732 2733 bool X86TargetInfo::initFeatureMap( 2734 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2735 const std::vector<std::string> &FeaturesVec) const { 2736 // FIXME: This *really* should not be here. 2737 // X86_64 always has SSE2. 2738 if (getTriple().getArch() == llvm::Triple::x86_64) 2739 setFeatureEnabledImpl(Features, "sse2", true); 2740 2741 const CPUKind Kind = getCPUKind(CPU); 2742 2743 // Enable X87 for all X86 processors but Lakemont. 2744 if (Kind != CK_Lakemont) 2745 setFeatureEnabledImpl(Features, "x87", true); 2746 2747 switch (Kind) { 2748 case CK_Generic: 2749 case CK_i386: 2750 case CK_i486: 2751 case CK_i586: 2752 case CK_Pentium: 2753 case CK_i686: 2754 case CK_PentiumPro: 2755 case CK_Lakemont: 2756 break; 2757 case CK_PentiumMMX: 2758 case CK_Pentium2: 2759 case CK_K6: 2760 case CK_WinChipC6: 2761 setFeatureEnabledImpl(Features, "mmx", true); 2762 break; 2763 case CK_Pentium3: 2764 case CK_Pentium3M: 2765 case CK_C3_2: 2766 setFeatureEnabledImpl(Features, "sse", true); 2767 setFeatureEnabledImpl(Features, "fxsr", true); 2768 break; 2769 case CK_PentiumM: 2770 case CK_Pentium4: 2771 case CK_Pentium4M: 2772 case CK_x86_64: 2773 setFeatureEnabledImpl(Features, "sse2", true); 2774 setFeatureEnabledImpl(Features, "fxsr", true); 2775 break; 2776 case CK_Yonah: 2777 case CK_Prescott: 2778 case CK_Nocona: 2779 setFeatureEnabledImpl(Features, "sse3", true); 2780 setFeatureEnabledImpl(Features, "fxsr", true); 2781 setFeatureEnabledImpl(Features, "cx16", true); 2782 break; 2783 case CK_Core2: 2784 case CK_Bonnell: 2785 setFeatureEnabledImpl(Features, "ssse3", true); 2786 setFeatureEnabledImpl(Features, "fxsr", true); 2787 setFeatureEnabledImpl(Features, "cx16", true); 2788 break; 2789 case CK_Penryn: 2790 setFeatureEnabledImpl(Features, "sse4.1", true); 2791 setFeatureEnabledImpl(Features, "fxsr", true); 2792 setFeatureEnabledImpl(Features, "cx16", true); 2793 break; 2794 case CK_Cannonlake: 2795 setFeatureEnabledImpl(Features, "avx512ifma", true); 2796 setFeatureEnabledImpl(Features, "avx512vbmi", true); 2797 setFeatureEnabledImpl(Features, "sha", true); 2798 setFeatureEnabledImpl(Features, "umip", true); 2799 // FALLTHROUGH 2800 case CK_SkylakeServer: 2801 setFeatureEnabledImpl(Features, "avx512f", true); 2802 setFeatureEnabledImpl(Features, "avx512cd", true); 2803 setFeatureEnabledImpl(Features, "avx512dq", true); 2804 setFeatureEnabledImpl(Features, "avx512bw", true); 2805 setFeatureEnabledImpl(Features, "avx512vl", true); 2806 setFeatureEnabledImpl(Features, "pku", true); 2807 setFeatureEnabledImpl(Features, "pcommit", true); 2808 setFeatureEnabledImpl(Features, "clwb", true); 2809 // FALLTHROUGH 2810 case CK_SkylakeClient: 2811 setFeatureEnabledImpl(Features, "xsavec", true); 2812 setFeatureEnabledImpl(Features, "xsaves", true); 2813 setFeatureEnabledImpl(Features, "mpx", true); 2814 setFeatureEnabledImpl(Features, "sgx", true); 2815 setFeatureEnabledImpl(Features, "clflushopt", true); 2816 // FALLTHROUGH 2817 case CK_Broadwell: 2818 setFeatureEnabledImpl(Features, "rdseed", true); 2819 setFeatureEnabledImpl(Features, "adx", true); 2820 // FALLTHROUGH 2821 case CK_Haswell: 2822 setFeatureEnabledImpl(Features, "avx2", true); 2823 setFeatureEnabledImpl(Features, "lzcnt", true); 2824 setFeatureEnabledImpl(Features, "bmi", true); 2825 setFeatureEnabledImpl(Features, "bmi2", true); 2826 setFeatureEnabledImpl(Features, "rtm", true); 2827 setFeatureEnabledImpl(Features, "fma", true); 2828 setFeatureEnabledImpl(Features, "movbe", true); 2829 // FALLTHROUGH 2830 case CK_IvyBridge: 2831 setFeatureEnabledImpl(Features, "rdrnd", true); 2832 setFeatureEnabledImpl(Features, "f16c", true); 2833 setFeatureEnabledImpl(Features, "fsgsbase", true); 2834 // FALLTHROUGH 2835 case CK_SandyBridge: 2836 setFeatureEnabledImpl(Features, "avx", true); 2837 setFeatureEnabledImpl(Features, "xsave", true); 2838 setFeatureEnabledImpl(Features, "xsaveopt", true); 2839 // FALLTHROUGH 2840 case CK_Westmere: 2841 case CK_Silvermont: 2842 setFeatureEnabledImpl(Features, "aes", true); 2843 setFeatureEnabledImpl(Features, "pclmul", true); 2844 // FALLTHROUGH 2845 case CK_Nehalem: 2846 setFeatureEnabledImpl(Features, "sse4.2", true); 2847 setFeatureEnabledImpl(Features, "fxsr", true); 2848 setFeatureEnabledImpl(Features, "cx16", true); 2849 break; 2850 case CK_KNL: 2851 setFeatureEnabledImpl(Features, "avx512f", true); 2852 setFeatureEnabledImpl(Features, "avx512cd", true); 2853 setFeatureEnabledImpl(Features, "avx512er", true); 2854 setFeatureEnabledImpl(Features, "avx512pf", true); 2855 setFeatureEnabledImpl(Features, "prefetchwt1", true); 2856 setFeatureEnabledImpl(Features, "fxsr", true); 2857 setFeatureEnabledImpl(Features, "rdseed", true); 2858 setFeatureEnabledImpl(Features, "adx", true); 2859 setFeatureEnabledImpl(Features, "lzcnt", true); 2860 setFeatureEnabledImpl(Features, "bmi", true); 2861 setFeatureEnabledImpl(Features, "bmi2", true); 2862 setFeatureEnabledImpl(Features, "rtm", true); 2863 setFeatureEnabledImpl(Features, "fma", true); 2864 setFeatureEnabledImpl(Features, "rdrnd", true); 2865 setFeatureEnabledImpl(Features, "f16c", true); 2866 setFeatureEnabledImpl(Features, "fsgsbase", true); 2867 setFeatureEnabledImpl(Features, "aes", true); 2868 setFeatureEnabledImpl(Features, "pclmul", true); 2869 setFeatureEnabledImpl(Features, "cx16", true); 2870 setFeatureEnabledImpl(Features, "xsaveopt", true); 2871 setFeatureEnabledImpl(Features, "xsave", true); 2872 setFeatureEnabledImpl(Features, "movbe", true); 2873 break; 2874 case CK_K6_2: 2875 case CK_K6_3: 2876 case CK_WinChip2: 2877 case CK_C3: 2878 setFeatureEnabledImpl(Features, "3dnow", true); 2879 break; 2880 case CK_Athlon: 2881 case CK_AthlonThunderbird: 2882 case CK_Geode: 2883 setFeatureEnabledImpl(Features, "3dnowa", true); 2884 break; 2885 case CK_Athlon4: 2886 case CK_AthlonXP: 2887 case CK_AthlonMP: 2888 setFeatureEnabledImpl(Features, "sse", true); 2889 setFeatureEnabledImpl(Features, "3dnowa", true); 2890 setFeatureEnabledImpl(Features, "fxsr", true); 2891 break; 2892 case CK_K8: 2893 case CK_Opteron: 2894 case CK_Athlon64: 2895 case CK_AthlonFX: 2896 setFeatureEnabledImpl(Features, "sse2", true); 2897 setFeatureEnabledImpl(Features, "3dnowa", true); 2898 setFeatureEnabledImpl(Features, "fxsr", true); 2899 break; 2900 case CK_AMDFAM10: 2901 setFeatureEnabledImpl(Features, "sse4a", true); 2902 setFeatureEnabledImpl(Features, "lzcnt", true); 2903 setFeatureEnabledImpl(Features, "popcnt", true); 2904 // FALLTHROUGH 2905 case CK_K8SSE3: 2906 case CK_OpteronSSE3: 2907 case CK_Athlon64SSE3: 2908 setFeatureEnabledImpl(Features, "sse3", true); 2909 setFeatureEnabledImpl(Features, "3dnowa", true); 2910 setFeatureEnabledImpl(Features, "fxsr", true); 2911 break; 2912 case CK_BTVER2: 2913 setFeatureEnabledImpl(Features, "avx", true); 2914 setFeatureEnabledImpl(Features, "aes", true); 2915 setFeatureEnabledImpl(Features, "pclmul", true); 2916 setFeatureEnabledImpl(Features, "bmi", true); 2917 setFeatureEnabledImpl(Features, "f16c", true); 2918 setFeatureEnabledImpl(Features, "xsaveopt", true); 2919 // FALLTHROUGH 2920 case CK_BTVER1: 2921 setFeatureEnabledImpl(Features, "ssse3", true); 2922 setFeatureEnabledImpl(Features, "sse4a", true); 2923 setFeatureEnabledImpl(Features, "lzcnt", true); 2924 setFeatureEnabledImpl(Features, "popcnt", true); 2925 setFeatureEnabledImpl(Features, "prfchw", true); 2926 setFeatureEnabledImpl(Features, "cx16", true); 2927 setFeatureEnabledImpl(Features, "fxsr", true); 2928 break; 2929 case CK_BDVER4: 2930 setFeatureEnabledImpl(Features, "avx2", true); 2931 setFeatureEnabledImpl(Features, "bmi2", true); 2932 // FALLTHROUGH 2933 case CK_BDVER3: 2934 setFeatureEnabledImpl(Features, "fsgsbase", true); 2935 setFeatureEnabledImpl(Features, "xsaveopt", true); 2936 // FALLTHROUGH 2937 case CK_BDVER2: 2938 setFeatureEnabledImpl(Features, "bmi", true); 2939 setFeatureEnabledImpl(Features, "fma", true); 2940 setFeatureEnabledImpl(Features, "f16c", true); 2941 setFeatureEnabledImpl(Features, "tbm", true); 2942 // FALLTHROUGH 2943 case CK_BDVER1: 2944 // xop implies avx, sse4a and fma4. 2945 setFeatureEnabledImpl(Features, "xop", true); 2946 setFeatureEnabledImpl(Features, "lzcnt", true); 2947 setFeatureEnabledImpl(Features, "aes", true); 2948 setFeatureEnabledImpl(Features, "pclmul", true); 2949 setFeatureEnabledImpl(Features, "prfchw", true); 2950 setFeatureEnabledImpl(Features, "cx16", true); 2951 setFeatureEnabledImpl(Features, "fxsr", true); 2952 setFeatureEnabledImpl(Features, "xsave", true); 2953 break; 2954 } 2955 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 2956 return false; 2957 2958 // Can't do this earlier because we need to be able to explicitly enable 2959 // or disable these features and the things that they depend upon. 2960 2961 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2962 auto I = Features.find("sse4.2"); 2963 if (I != Features.end() && I->getValue() && 2964 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 2965 FeaturesVec.end()) 2966 Features["popcnt"] = true; 2967 2968 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2969 I = Features.find("3dnow"); 2970 if (I != Features.end() && I->getValue() && 2971 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 2972 FeaturesVec.end()) 2973 Features["prfchw"] = true; 2974 2975 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2976 // then enable MMX. 2977 I = Features.find("sse"); 2978 if (I != Features.end() && I->getValue() && 2979 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 2980 FeaturesVec.end()) 2981 Features["mmx"] = true; 2982 2983 return true; 2984 } 2985 2986 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2987 X86SSEEnum Level, bool Enabled) { 2988 if (Enabled) { 2989 switch (Level) { 2990 case AVX512F: 2991 Features["avx512f"] = true; 2992 case AVX2: 2993 Features["avx2"] = true; 2994 case AVX: 2995 Features["avx"] = true; 2996 Features["xsave"] = true; 2997 case SSE42: 2998 Features["sse4.2"] = true; 2999 case SSE41: 3000 Features["sse4.1"] = true; 3001 case SSSE3: 3002 Features["ssse3"] = true; 3003 case SSE3: 3004 Features["sse3"] = true; 3005 case SSE2: 3006 Features["sse2"] = true; 3007 case SSE1: 3008 Features["sse"] = true; 3009 case NoSSE: 3010 break; 3011 } 3012 return; 3013 } 3014 3015 switch (Level) { 3016 case NoSSE: 3017 case SSE1: 3018 Features["sse"] = false; 3019 case SSE2: 3020 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3021 Features["sha"] = false; 3022 case SSE3: 3023 Features["sse3"] = false; 3024 setXOPLevel(Features, NoXOP, false); 3025 case SSSE3: 3026 Features["ssse3"] = false; 3027 case SSE41: 3028 Features["sse4.1"] = false; 3029 case SSE42: 3030 Features["sse4.2"] = false; 3031 case AVX: 3032 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3033 Features["xsaveopt"] = false; 3034 setXOPLevel(Features, FMA4, false); 3035 case AVX2: 3036 Features["avx2"] = false; 3037 case AVX512F: 3038 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3039 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3040 Features["avx512vl"] = Features["avx512vbmi"] = 3041 Features["avx512ifma"] = false; 3042 } 3043 } 3044 3045 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3046 MMX3DNowEnum Level, bool Enabled) { 3047 if (Enabled) { 3048 switch (Level) { 3049 case AMD3DNowAthlon: 3050 Features["3dnowa"] = true; 3051 case AMD3DNow: 3052 Features["3dnow"] = true; 3053 case MMX: 3054 Features["mmx"] = true; 3055 case NoMMX3DNow: 3056 break; 3057 } 3058 return; 3059 } 3060 3061 switch (Level) { 3062 case NoMMX3DNow: 3063 case MMX: 3064 Features["mmx"] = false; 3065 case AMD3DNow: 3066 Features["3dnow"] = false; 3067 case AMD3DNowAthlon: 3068 Features["3dnowa"] = false; 3069 } 3070 } 3071 3072 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3073 bool Enabled) { 3074 if (Enabled) { 3075 switch (Level) { 3076 case XOP: 3077 Features["xop"] = true; 3078 case FMA4: 3079 Features["fma4"] = true; 3080 setSSELevel(Features, AVX, true); 3081 case SSE4A: 3082 Features["sse4a"] = true; 3083 setSSELevel(Features, SSE3, true); 3084 case NoXOP: 3085 break; 3086 } 3087 return; 3088 } 3089 3090 switch (Level) { 3091 case NoXOP: 3092 case SSE4A: 3093 Features["sse4a"] = false; 3094 case FMA4: 3095 Features["fma4"] = false; 3096 case XOP: 3097 Features["xop"] = false; 3098 } 3099 } 3100 3101 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3102 StringRef Name, bool Enabled) { 3103 // This is a bit of a hack to deal with the sse4 target feature when used 3104 // as part of the target attribute. We handle sse4 correctly everywhere 3105 // else. See below for more information on how we handle the sse4 options. 3106 if (Name != "sse4") 3107 Features[Name] = Enabled; 3108 3109 if (Name == "mmx") { 3110 setMMXLevel(Features, MMX, Enabled); 3111 } else if (Name == "sse") { 3112 setSSELevel(Features, SSE1, Enabled); 3113 } else if (Name == "sse2") { 3114 setSSELevel(Features, SSE2, Enabled); 3115 } else if (Name == "sse3") { 3116 setSSELevel(Features, SSE3, Enabled); 3117 } else if (Name == "ssse3") { 3118 setSSELevel(Features, SSSE3, Enabled); 3119 } else if (Name == "sse4.2") { 3120 setSSELevel(Features, SSE42, Enabled); 3121 } else if (Name == "sse4.1") { 3122 setSSELevel(Features, SSE41, Enabled); 3123 } else if (Name == "3dnow") { 3124 setMMXLevel(Features, AMD3DNow, Enabled); 3125 } else if (Name == "3dnowa") { 3126 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3127 } else if (Name == "aes") { 3128 if (Enabled) 3129 setSSELevel(Features, SSE2, Enabled); 3130 } else if (Name == "pclmul") { 3131 if (Enabled) 3132 setSSELevel(Features, SSE2, Enabled); 3133 } else if (Name == "avx") { 3134 setSSELevel(Features, AVX, Enabled); 3135 } else if (Name == "avx2") { 3136 setSSELevel(Features, AVX2, Enabled); 3137 } else if (Name == "avx512f") { 3138 setSSELevel(Features, AVX512F, Enabled); 3139 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3140 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3141 Name == "avx512vbmi" || Name == "avx512ifma") { 3142 if (Enabled) 3143 setSSELevel(Features, AVX512F, Enabled); 3144 } else if (Name == "fma") { 3145 if (Enabled) 3146 setSSELevel(Features, AVX, Enabled); 3147 } else if (Name == "fma4") { 3148 setXOPLevel(Features, FMA4, Enabled); 3149 } else if (Name == "xop") { 3150 setXOPLevel(Features, XOP, Enabled); 3151 } else if (Name == "sse4a") { 3152 setXOPLevel(Features, SSE4A, Enabled); 3153 } else if (Name == "f16c") { 3154 if (Enabled) 3155 setSSELevel(Features, AVX, Enabled); 3156 } else if (Name == "sha") { 3157 if (Enabled) 3158 setSSELevel(Features, SSE2, Enabled); 3159 } else if (Name == "sse4") { 3160 // We can get here via the __target__ attribute since that's not controlled 3161 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3162 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3163 // disabled. 3164 if (Enabled) 3165 setSSELevel(Features, SSE42, Enabled); 3166 else 3167 setSSELevel(Features, SSE41, Enabled); 3168 } else if (Name == "xsave") { 3169 if (!Enabled) 3170 Features["xsaveopt"] = false; 3171 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3172 if (Enabled) 3173 Features["xsave"] = true; 3174 } 3175 } 3176 3177 /// handleTargetFeatures - Perform initialization based on the user 3178 /// configured set of features. 3179 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3180 DiagnosticsEngine &Diags) { 3181 for (const auto &Feature : Features) { 3182 if (Feature[0] != '+') 3183 continue; 3184 3185 if (Feature == "+aes") { 3186 HasAES = true; 3187 } else if (Feature == "+pclmul") { 3188 HasPCLMUL = true; 3189 } else if (Feature == "+lzcnt") { 3190 HasLZCNT = true; 3191 } else if (Feature == "+rdrnd") { 3192 HasRDRND = true; 3193 } else if (Feature == "+fsgsbase") { 3194 HasFSGSBASE = true; 3195 } else if (Feature == "+bmi") { 3196 HasBMI = true; 3197 } else if (Feature == "+bmi2") { 3198 HasBMI2 = true; 3199 } else if (Feature == "+popcnt") { 3200 HasPOPCNT = true; 3201 } else if (Feature == "+rtm") { 3202 HasRTM = true; 3203 } else if (Feature == "+prfchw") { 3204 HasPRFCHW = true; 3205 } else if (Feature == "+rdseed") { 3206 HasRDSEED = true; 3207 } else if (Feature == "+adx") { 3208 HasADX = true; 3209 } else if (Feature == "+tbm") { 3210 HasTBM = true; 3211 } else if (Feature == "+fma") { 3212 HasFMA = true; 3213 } else if (Feature == "+f16c") { 3214 HasF16C = true; 3215 } else if (Feature == "+avx512cd") { 3216 HasAVX512CD = true; 3217 } else if (Feature == "+avx512er") { 3218 HasAVX512ER = true; 3219 } else if (Feature == "+avx512pf") { 3220 HasAVX512PF = true; 3221 } else if (Feature == "+avx512dq") { 3222 HasAVX512DQ = true; 3223 } else if (Feature == "+avx512bw") { 3224 HasAVX512BW = true; 3225 } else if (Feature == "+avx512vl") { 3226 HasAVX512VL = true; 3227 } else if (Feature == "+avx512vbmi") { 3228 HasAVX512VBMI = true; 3229 } else if (Feature == "+avx512ifma") { 3230 HasAVX512IFMA = true; 3231 } else if (Feature == "+sha") { 3232 HasSHA = true; 3233 } else if (Feature == "+mpx") { 3234 HasMPX = true; 3235 } else if (Feature == "+movbe") { 3236 HasMOVBE = true; 3237 } else if (Feature == "+sgx") { 3238 HasSGX = true; 3239 } else if (Feature == "+cx16") { 3240 HasCX16 = true; 3241 } else if (Feature == "+fxsr") { 3242 HasFXSR = true; 3243 } else if (Feature == "+xsave") { 3244 HasXSAVE = true; 3245 } else if (Feature == "+xsaveopt") { 3246 HasXSAVEOPT = true; 3247 } else if (Feature == "+xsavec") { 3248 HasXSAVEC = true; 3249 } else if (Feature == "+xsaves") { 3250 HasXSAVES = true; 3251 } else if (Feature == "+pku") { 3252 HasPKU = true; 3253 } else if (Feature == "+clflushopt") { 3254 HasCLFLUSHOPT = true; 3255 } else if (Feature == "+pcommit") { 3256 HasPCOMMIT = true; 3257 } else if (Feature == "+clwb") { 3258 HasCLWB = true; 3259 } else if (Feature == "+umip") { 3260 HasUMIP = true; 3261 } else if (Feature == "+prefetchwt1") { 3262 HasPREFETCHWT1 = true; 3263 } 3264 3265 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3266 .Case("+avx512f", AVX512F) 3267 .Case("+avx2", AVX2) 3268 .Case("+avx", AVX) 3269 .Case("+sse4.2", SSE42) 3270 .Case("+sse4.1", SSE41) 3271 .Case("+ssse3", SSSE3) 3272 .Case("+sse3", SSE3) 3273 .Case("+sse2", SSE2) 3274 .Case("+sse", SSE1) 3275 .Default(NoSSE); 3276 SSELevel = std::max(SSELevel, Level); 3277 3278 MMX3DNowEnum ThreeDNowLevel = 3279 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3280 .Case("+3dnowa", AMD3DNowAthlon) 3281 .Case("+3dnow", AMD3DNow) 3282 .Case("+mmx", MMX) 3283 .Default(NoMMX3DNow); 3284 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3285 3286 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3287 .Case("+xop", XOP) 3288 .Case("+fma4", FMA4) 3289 .Case("+sse4a", SSE4A) 3290 .Default(NoXOP); 3291 XOPLevel = std::max(XOPLevel, XLevel); 3292 } 3293 3294 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3295 // matches the selected sse level. 3296 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3297 (FPMath == FP_387 && SSELevel >= SSE1)) { 3298 Diags.Report(diag::err_target_unsupported_fpmath) << 3299 (FPMath == FP_SSE ? "sse" : "387"); 3300 return false; 3301 } 3302 3303 SimdDefaultAlign = 3304 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3305 return true; 3306 } 3307 3308 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3309 /// definitions for this particular subtarget. 3310 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3311 MacroBuilder &Builder) const { 3312 // Target identification. 3313 if (getTriple().getArch() == llvm::Triple::x86_64) { 3314 Builder.defineMacro("__amd64__"); 3315 Builder.defineMacro("__amd64"); 3316 Builder.defineMacro("__x86_64"); 3317 Builder.defineMacro("__x86_64__"); 3318 if (getTriple().getArchName() == "x86_64h") { 3319 Builder.defineMacro("__x86_64h"); 3320 Builder.defineMacro("__x86_64h__"); 3321 } 3322 } else { 3323 DefineStd(Builder, "i386", Opts); 3324 } 3325 3326 // Subtarget options. 3327 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3328 // truly should be based on -mtune options. 3329 switch (CPU) { 3330 case CK_Generic: 3331 break; 3332 case CK_i386: 3333 // The rest are coming from the i386 define above. 3334 Builder.defineMacro("__tune_i386__"); 3335 break; 3336 case CK_i486: 3337 case CK_WinChipC6: 3338 case CK_WinChip2: 3339 case CK_C3: 3340 defineCPUMacros(Builder, "i486"); 3341 break; 3342 case CK_PentiumMMX: 3343 Builder.defineMacro("__pentium_mmx__"); 3344 Builder.defineMacro("__tune_pentium_mmx__"); 3345 // Fallthrough 3346 case CK_i586: 3347 case CK_Pentium: 3348 defineCPUMacros(Builder, "i586"); 3349 defineCPUMacros(Builder, "pentium"); 3350 break; 3351 case CK_Pentium3: 3352 case CK_Pentium3M: 3353 case CK_PentiumM: 3354 Builder.defineMacro("__tune_pentium3__"); 3355 // Fallthrough 3356 case CK_Pentium2: 3357 case CK_C3_2: 3358 Builder.defineMacro("__tune_pentium2__"); 3359 // Fallthrough 3360 case CK_PentiumPro: 3361 Builder.defineMacro("__tune_i686__"); 3362 Builder.defineMacro("__tune_pentiumpro__"); 3363 // Fallthrough 3364 case CK_i686: 3365 Builder.defineMacro("__i686"); 3366 Builder.defineMacro("__i686__"); 3367 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3368 Builder.defineMacro("__pentiumpro"); 3369 Builder.defineMacro("__pentiumpro__"); 3370 break; 3371 case CK_Pentium4: 3372 case CK_Pentium4M: 3373 defineCPUMacros(Builder, "pentium4"); 3374 break; 3375 case CK_Yonah: 3376 case CK_Prescott: 3377 case CK_Nocona: 3378 defineCPUMacros(Builder, "nocona"); 3379 break; 3380 case CK_Core2: 3381 case CK_Penryn: 3382 defineCPUMacros(Builder, "core2"); 3383 break; 3384 case CK_Bonnell: 3385 defineCPUMacros(Builder, "atom"); 3386 break; 3387 case CK_Silvermont: 3388 defineCPUMacros(Builder, "slm"); 3389 break; 3390 case CK_Nehalem: 3391 case CK_Westmere: 3392 case CK_SandyBridge: 3393 case CK_IvyBridge: 3394 case CK_Haswell: 3395 case CK_Broadwell: 3396 case CK_SkylakeClient: 3397 // FIXME: Historically, we defined this legacy name, it would be nice to 3398 // remove it at some point. We've never exposed fine-grained names for 3399 // recent primary x86 CPUs, and we should keep it that way. 3400 defineCPUMacros(Builder, "corei7"); 3401 break; 3402 case CK_SkylakeServer: 3403 defineCPUMacros(Builder, "skx"); 3404 break; 3405 case CK_Cannonlake: 3406 break; 3407 case CK_KNL: 3408 defineCPUMacros(Builder, "knl"); 3409 break; 3410 case CK_Lakemont: 3411 Builder.defineMacro("__tune_lakemont__"); 3412 break; 3413 case CK_K6_2: 3414 Builder.defineMacro("__k6_2__"); 3415 Builder.defineMacro("__tune_k6_2__"); 3416 // Fallthrough 3417 case CK_K6_3: 3418 if (CPU != CK_K6_2) { // In case of fallthrough 3419 // FIXME: GCC may be enabling these in cases where some other k6 3420 // architecture is specified but -m3dnow is explicitly provided. The 3421 // exact semantics need to be determined and emulated here. 3422 Builder.defineMacro("__k6_3__"); 3423 Builder.defineMacro("__tune_k6_3__"); 3424 } 3425 // Fallthrough 3426 case CK_K6: 3427 defineCPUMacros(Builder, "k6"); 3428 break; 3429 case CK_Athlon: 3430 case CK_AthlonThunderbird: 3431 case CK_Athlon4: 3432 case CK_AthlonXP: 3433 case CK_AthlonMP: 3434 defineCPUMacros(Builder, "athlon"); 3435 if (SSELevel != NoSSE) { 3436 Builder.defineMacro("__athlon_sse__"); 3437 Builder.defineMacro("__tune_athlon_sse__"); 3438 } 3439 break; 3440 case CK_K8: 3441 case CK_K8SSE3: 3442 case CK_x86_64: 3443 case CK_Opteron: 3444 case CK_OpteronSSE3: 3445 case CK_Athlon64: 3446 case CK_Athlon64SSE3: 3447 case CK_AthlonFX: 3448 defineCPUMacros(Builder, "k8"); 3449 break; 3450 case CK_AMDFAM10: 3451 defineCPUMacros(Builder, "amdfam10"); 3452 break; 3453 case CK_BTVER1: 3454 defineCPUMacros(Builder, "btver1"); 3455 break; 3456 case CK_BTVER2: 3457 defineCPUMacros(Builder, "btver2"); 3458 break; 3459 case CK_BDVER1: 3460 defineCPUMacros(Builder, "bdver1"); 3461 break; 3462 case CK_BDVER2: 3463 defineCPUMacros(Builder, "bdver2"); 3464 break; 3465 case CK_BDVER3: 3466 defineCPUMacros(Builder, "bdver3"); 3467 break; 3468 case CK_BDVER4: 3469 defineCPUMacros(Builder, "bdver4"); 3470 break; 3471 case CK_Geode: 3472 defineCPUMacros(Builder, "geode"); 3473 break; 3474 } 3475 3476 // Target properties. 3477 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3478 3479 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3480 // functions in glibc header files that use FP Stack inline asm which the 3481 // backend can't deal with (PR879). 3482 Builder.defineMacro("__NO_MATH_INLINES"); 3483 3484 if (HasAES) 3485 Builder.defineMacro("__AES__"); 3486 3487 if (HasPCLMUL) 3488 Builder.defineMacro("__PCLMUL__"); 3489 3490 if (HasLZCNT) 3491 Builder.defineMacro("__LZCNT__"); 3492 3493 if (HasRDRND) 3494 Builder.defineMacro("__RDRND__"); 3495 3496 if (HasFSGSBASE) 3497 Builder.defineMacro("__FSGSBASE__"); 3498 3499 if (HasBMI) 3500 Builder.defineMacro("__BMI__"); 3501 3502 if (HasBMI2) 3503 Builder.defineMacro("__BMI2__"); 3504 3505 if (HasPOPCNT) 3506 Builder.defineMacro("__POPCNT__"); 3507 3508 if (HasRTM) 3509 Builder.defineMacro("__RTM__"); 3510 3511 if (HasPRFCHW) 3512 Builder.defineMacro("__PRFCHW__"); 3513 3514 if (HasRDSEED) 3515 Builder.defineMacro("__RDSEED__"); 3516 3517 if (HasADX) 3518 Builder.defineMacro("__ADX__"); 3519 3520 if (HasTBM) 3521 Builder.defineMacro("__TBM__"); 3522 3523 switch (XOPLevel) { 3524 case XOP: 3525 Builder.defineMacro("__XOP__"); 3526 case FMA4: 3527 Builder.defineMacro("__FMA4__"); 3528 case SSE4A: 3529 Builder.defineMacro("__SSE4A__"); 3530 case NoXOP: 3531 break; 3532 } 3533 3534 if (HasFMA) 3535 Builder.defineMacro("__FMA__"); 3536 3537 if (HasF16C) 3538 Builder.defineMacro("__F16C__"); 3539 3540 if (HasAVX512CD) 3541 Builder.defineMacro("__AVX512CD__"); 3542 if (HasAVX512ER) 3543 Builder.defineMacro("__AVX512ER__"); 3544 if (HasAVX512PF) 3545 Builder.defineMacro("__AVX512PF__"); 3546 if (HasAVX512DQ) 3547 Builder.defineMacro("__AVX512DQ__"); 3548 if (HasAVX512BW) 3549 Builder.defineMacro("__AVX512BW__"); 3550 if (HasAVX512VL) 3551 Builder.defineMacro("__AVX512VL__"); 3552 if (HasAVX512VBMI) 3553 Builder.defineMacro("__AVX512VBMI__"); 3554 if (HasAVX512IFMA) 3555 Builder.defineMacro("__AVX512IFMA__"); 3556 3557 if (HasSHA) 3558 Builder.defineMacro("__SHA__"); 3559 3560 if (HasFXSR) 3561 Builder.defineMacro("__FXSR__"); 3562 if (HasXSAVE) 3563 Builder.defineMacro("__XSAVE__"); 3564 if (HasXSAVEOPT) 3565 Builder.defineMacro("__XSAVEOPT__"); 3566 if (HasXSAVEC) 3567 Builder.defineMacro("__XSAVEC__"); 3568 if (HasXSAVES) 3569 Builder.defineMacro("__XSAVES__"); 3570 if (HasPKU) 3571 Builder.defineMacro("__PKU__"); 3572 if (HasCX16) 3573 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3574 3575 // Each case falls through to the previous one here. 3576 switch (SSELevel) { 3577 case AVX512F: 3578 Builder.defineMacro("__AVX512F__"); 3579 case AVX2: 3580 Builder.defineMacro("__AVX2__"); 3581 case AVX: 3582 Builder.defineMacro("__AVX__"); 3583 case SSE42: 3584 Builder.defineMacro("__SSE4_2__"); 3585 case SSE41: 3586 Builder.defineMacro("__SSE4_1__"); 3587 case SSSE3: 3588 Builder.defineMacro("__SSSE3__"); 3589 case SSE3: 3590 Builder.defineMacro("__SSE3__"); 3591 case SSE2: 3592 Builder.defineMacro("__SSE2__"); 3593 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3594 case SSE1: 3595 Builder.defineMacro("__SSE__"); 3596 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3597 case NoSSE: 3598 break; 3599 } 3600 3601 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3602 switch (SSELevel) { 3603 case AVX512F: 3604 case AVX2: 3605 case AVX: 3606 case SSE42: 3607 case SSE41: 3608 case SSSE3: 3609 case SSE3: 3610 case SSE2: 3611 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3612 break; 3613 case SSE1: 3614 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3615 break; 3616 default: 3617 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3618 } 3619 } 3620 3621 // Each case falls through to the previous one here. 3622 switch (MMX3DNowLevel) { 3623 case AMD3DNowAthlon: 3624 Builder.defineMacro("__3dNOW_A__"); 3625 case AMD3DNow: 3626 Builder.defineMacro("__3dNOW__"); 3627 case MMX: 3628 Builder.defineMacro("__MMX__"); 3629 case NoMMX3DNow: 3630 break; 3631 } 3632 3633 if (CPU >= CK_i486) { 3634 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3635 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3636 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3637 } 3638 if (CPU >= CK_i586) 3639 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3640 } 3641 3642 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3643 return llvm::StringSwitch<bool>(Feature) 3644 .Case("aes", HasAES) 3645 .Case("avx", SSELevel >= AVX) 3646 .Case("avx2", SSELevel >= AVX2) 3647 .Case("avx512f", SSELevel >= AVX512F) 3648 .Case("avx512cd", HasAVX512CD) 3649 .Case("avx512er", HasAVX512ER) 3650 .Case("avx512pf", HasAVX512PF) 3651 .Case("avx512dq", HasAVX512DQ) 3652 .Case("avx512bw", HasAVX512BW) 3653 .Case("avx512vl", HasAVX512VL) 3654 .Case("avx512vbmi", HasAVX512VBMI) 3655 .Case("avx512ifma", HasAVX512IFMA) 3656 .Case("bmi", HasBMI) 3657 .Case("bmi2", HasBMI2) 3658 .Case("clflushopt", HasCLFLUSHOPT) 3659 .Case("clwb", HasCLWB) 3660 .Case("cx16", HasCX16) 3661 .Case("f16c", HasF16C) 3662 .Case("fma", HasFMA) 3663 .Case("fma4", XOPLevel >= FMA4) 3664 .Case("fsgsbase", HasFSGSBASE) 3665 .Case("fxsr", HasFXSR) 3666 .Case("lzcnt", HasLZCNT) 3667 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3668 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3669 .Case("mmx", MMX3DNowLevel >= MMX) 3670 .Case("movbe", HasMOVBE) 3671 .Case("mpx", HasMPX) 3672 .Case("pclmul", HasPCLMUL) 3673 .Case("pcommit", HasPCOMMIT) 3674 .Case("pku", HasPKU) 3675 .Case("popcnt", HasPOPCNT) 3676 .Case("prefetchwt1", HasPREFETCHWT1) 3677 .Case("prfchw", HasPRFCHW) 3678 .Case("rdrnd", HasRDRND) 3679 .Case("rdseed", HasRDSEED) 3680 .Case("rtm", HasRTM) 3681 .Case("sgx", HasSGX) 3682 .Case("sha", HasSHA) 3683 .Case("sse", SSELevel >= SSE1) 3684 .Case("sse2", SSELevel >= SSE2) 3685 .Case("sse3", SSELevel >= SSE3) 3686 .Case("ssse3", SSELevel >= SSSE3) 3687 .Case("sse4.1", SSELevel >= SSE41) 3688 .Case("sse4.2", SSELevel >= SSE42) 3689 .Case("sse4a", XOPLevel >= SSE4A) 3690 .Case("tbm", HasTBM) 3691 .Case("umip", HasUMIP) 3692 .Case("x86", true) 3693 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3694 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3695 .Case("xop", XOPLevel >= XOP) 3696 .Case("xsave", HasXSAVE) 3697 .Case("xsavec", HasXSAVEC) 3698 .Case("xsaves", HasXSAVES) 3699 .Case("xsaveopt", HasXSAVEOPT) 3700 .Default(false); 3701 } 3702 3703 // We can't use a generic validation scheme for the features accepted here 3704 // versus subtarget features accepted in the target attribute because the 3705 // bitfield structure that's initialized in the runtime only supports the 3706 // below currently rather than the full range of subtarget features. (See 3707 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3708 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3709 return llvm::StringSwitch<bool>(FeatureStr) 3710 .Case("cmov", true) 3711 .Case("mmx", true) 3712 .Case("popcnt", true) 3713 .Case("sse", true) 3714 .Case("sse2", true) 3715 .Case("sse3", true) 3716 .Case("sse4.1", true) 3717 .Case("sse4.2", true) 3718 .Case("avx", true) 3719 .Case("avx2", true) 3720 .Case("sse4a", true) 3721 .Case("fma4", true) 3722 .Case("xop", true) 3723 .Case("fma", true) 3724 .Case("avx512f", true) 3725 .Case("bmi", true) 3726 .Case("bmi2", true) 3727 .Default(false); 3728 } 3729 3730 bool 3731 X86TargetInfo::validateAsmConstraint(const char *&Name, 3732 TargetInfo::ConstraintInfo &Info) const { 3733 switch (*Name) { 3734 default: return false; 3735 // Constant constraints. 3736 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3737 // instructions. 3738 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3739 // x86_64 instructions. 3740 case 's': 3741 Info.setRequiresImmediate(); 3742 return true; 3743 case 'I': 3744 Info.setRequiresImmediate(0, 31); 3745 return true; 3746 case 'J': 3747 Info.setRequiresImmediate(0, 63); 3748 return true; 3749 case 'K': 3750 Info.setRequiresImmediate(-128, 127); 3751 return true; 3752 case 'L': 3753 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3754 return true; 3755 case 'M': 3756 Info.setRequiresImmediate(0, 3); 3757 return true; 3758 case 'N': 3759 Info.setRequiresImmediate(0, 255); 3760 return true; 3761 case 'O': 3762 Info.setRequiresImmediate(0, 127); 3763 return true; 3764 // Register constraints. 3765 case 'Y': // 'Y' is the first character for several 2-character constraints. 3766 // Shift the pointer to the second character of the constraint. 3767 Name++; 3768 switch (*Name) { 3769 default: 3770 return false; 3771 case '0': // First SSE register. 3772 case 't': // Any SSE register, when SSE2 is enabled. 3773 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3774 case 'm': // Any MMX register, when inter-unit moves enabled. 3775 Info.setAllowsRegister(); 3776 return true; 3777 } 3778 case 'f': // Any x87 floating point stack register. 3779 // Constraint 'f' cannot be used for output operands. 3780 if (Info.ConstraintStr[0] == '=') 3781 return false; 3782 Info.setAllowsRegister(); 3783 return true; 3784 case 'a': // eax. 3785 case 'b': // ebx. 3786 case 'c': // ecx. 3787 case 'd': // edx. 3788 case 'S': // esi. 3789 case 'D': // edi. 3790 case 'A': // edx:eax. 3791 case 't': // Top of floating point stack. 3792 case 'u': // Second from top of floating point stack. 3793 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3794 case 'y': // Any MMX register. 3795 case 'x': // Any SSE register. 3796 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3797 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3798 case 'l': // "Index" registers: any general register that can be used as an 3799 // index in a base+index memory access. 3800 Info.setAllowsRegister(); 3801 return true; 3802 // Floating point constant constraints. 3803 case 'C': // SSE floating point constant. 3804 case 'G': // x87 floating point constant. 3805 return true; 3806 } 3807 } 3808 3809 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3810 unsigned Size) const { 3811 // Strip off constraint modifiers. 3812 while (Constraint[0] == '=' || 3813 Constraint[0] == '+' || 3814 Constraint[0] == '&') 3815 Constraint = Constraint.substr(1); 3816 3817 return validateOperandSize(Constraint, Size); 3818 } 3819 3820 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3821 unsigned Size) const { 3822 return validateOperandSize(Constraint, Size); 3823 } 3824 3825 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3826 unsigned Size) const { 3827 switch (Constraint[0]) { 3828 default: break; 3829 case 'y': 3830 return Size <= 64; 3831 case 'f': 3832 case 't': 3833 case 'u': 3834 return Size <= 128; 3835 case 'x': 3836 if (SSELevel >= AVX512F) 3837 // 512-bit zmm registers can be used if target supports AVX512F. 3838 return Size <= 512U; 3839 else if (SSELevel >= AVX) 3840 // 256-bit ymm registers can be used if target supports AVX. 3841 return Size <= 256U; 3842 return Size <= 128U; 3843 case 'Y': 3844 // 'Y' is the first character for several 2-character constraints. 3845 switch (Constraint[1]) { 3846 default: break; 3847 case 'm': 3848 // 'Ym' is synonymous with 'y'. 3849 return Size <= 64; 3850 case 'i': 3851 case 't': 3852 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3853 if (SSELevel >= AVX512F) 3854 return Size <= 512U; 3855 else if (SSELevel >= AVX) 3856 return Size <= 256U; 3857 return SSELevel >= SSE2 && Size <= 128U; 3858 } 3859 3860 } 3861 3862 return true; 3863 } 3864 3865 std::string 3866 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3867 switch (*Constraint) { 3868 case 'a': return std::string("{ax}"); 3869 case 'b': return std::string("{bx}"); 3870 case 'c': return std::string("{cx}"); 3871 case 'd': return std::string("{dx}"); 3872 case 'S': return std::string("{si}"); 3873 case 'D': return std::string("{di}"); 3874 case 'p': // address 3875 return std::string("im"); 3876 case 't': // top of floating point stack. 3877 return std::string("{st}"); 3878 case 'u': // second from top of floating point stack. 3879 return std::string("{st(1)}"); // second from top of floating point stack. 3880 default: 3881 return std::string(1, *Constraint); 3882 } 3883 } 3884 3885 // X86-32 generic target 3886 class X86_32TargetInfo : public X86TargetInfo { 3887 public: 3888 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3889 : X86TargetInfo(Triple, Opts) { 3890 DoubleAlign = LongLongAlign = 32; 3891 LongDoubleWidth = 96; 3892 LongDoubleAlign = 32; 3893 SuitableAlign = 128; 3894 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 3895 SizeType = UnsignedInt; 3896 PtrDiffType = SignedInt; 3897 IntPtrType = SignedInt; 3898 RegParmMax = 3; 3899 3900 // Use fpret for all types. 3901 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3902 (1 << TargetInfo::Double) | 3903 (1 << TargetInfo::LongDouble)); 3904 3905 // x86-32 has atomics up to 8 bytes 3906 // FIXME: Check that we actually have cmpxchg8b before setting 3907 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3908 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3909 } 3910 BuiltinVaListKind getBuiltinVaListKind() const override { 3911 return TargetInfo::CharPtrBuiltinVaList; 3912 } 3913 3914 int getEHDataRegisterNumber(unsigned RegNo) const override { 3915 if (RegNo == 0) return 0; 3916 if (RegNo == 1) return 2; 3917 return -1; 3918 } 3919 bool validateOperandSize(StringRef Constraint, 3920 unsigned Size) const override { 3921 switch (Constraint[0]) { 3922 default: break; 3923 case 'R': 3924 case 'q': 3925 case 'Q': 3926 case 'a': 3927 case 'b': 3928 case 'c': 3929 case 'd': 3930 case 'S': 3931 case 'D': 3932 return Size <= 32; 3933 case 'A': 3934 return Size <= 64; 3935 } 3936 3937 return X86TargetInfo::validateOperandSize(Constraint, Size); 3938 } 3939 }; 3940 3941 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3942 public: 3943 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3944 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 3945 3946 unsigned getFloatEvalMethod() const override { 3947 unsigned Major, Minor, Micro; 3948 getTriple().getOSVersion(Major, Minor, Micro); 3949 // New NetBSD uses the default rounding mode. 3950 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3951 return X86_32TargetInfo::getFloatEvalMethod(); 3952 // NetBSD before 6.99.26 defaults to "double" rounding. 3953 return 1; 3954 } 3955 }; 3956 3957 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3958 public: 3959 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3960 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 3961 SizeType = UnsignedLong; 3962 IntPtrType = SignedLong; 3963 PtrDiffType = SignedLong; 3964 } 3965 }; 3966 3967 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3968 public: 3969 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3970 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 3971 SizeType = UnsignedLong; 3972 IntPtrType = SignedLong; 3973 PtrDiffType = SignedLong; 3974 } 3975 }; 3976 3977 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3978 public: 3979 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3980 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 3981 LongDoubleWidth = 128; 3982 LongDoubleAlign = 128; 3983 SuitableAlign = 128; 3984 MaxVectorAlign = 256; 3985 // The watchOS simulator uses the builtin bool type for Objective-C. 3986 llvm::Triple T = llvm::Triple(Triple); 3987 if (T.isWatchOS()) 3988 UseSignedCharForObjCBool = false; 3989 SizeType = UnsignedLong; 3990 IntPtrType = SignedLong; 3991 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 3992 HasAlignMac68kSupport = true; 3993 } 3994 3995 bool handleTargetFeatures(std::vector<std::string> &Features, 3996 DiagnosticsEngine &Diags) override { 3997 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 3998 Diags)) 3999 return false; 4000 // We now know the features we have: we can decide how to align vectors. 4001 MaxVectorAlign = 4002 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4003 return true; 4004 } 4005 }; 4006 4007 // x86-32 Windows target 4008 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4009 public: 4010 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4011 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4012 WCharType = UnsignedShort; 4013 DoubleAlign = LongLongAlign = 64; 4014 bool IsWinCOFF = 4015 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4016 resetDataLayout(IsWinCOFF 4017 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4018 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4019 } 4020 void getTargetDefines(const LangOptions &Opts, 4021 MacroBuilder &Builder) const override { 4022 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4023 } 4024 }; 4025 4026 // x86-32 Windows Visual Studio target 4027 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4028 public: 4029 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4030 const TargetOptions &Opts) 4031 : WindowsX86_32TargetInfo(Triple, Opts) { 4032 LongDoubleWidth = LongDoubleAlign = 64; 4033 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4034 } 4035 void getTargetDefines(const LangOptions &Opts, 4036 MacroBuilder &Builder) const override { 4037 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4038 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4039 // The value of the following reflects processor type. 4040 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4041 // We lost the original triple, so we use the default. 4042 Builder.defineMacro("_M_IX86", "600"); 4043 } 4044 }; 4045 4046 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4047 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4048 // supports __declspec natively under -fms-extensions, but we define a no-op 4049 // __declspec macro anyway for pre-processor compatibility. 4050 if (Opts.MicrosoftExt) 4051 Builder.defineMacro("__declspec", "__declspec"); 4052 else 4053 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4054 4055 if (!Opts.MicrosoftExt) { 4056 // Provide macros for all the calling convention keywords. Provide both 4057 // single and double underscore prefixed variants. These are available on 4058 // x64 as well as x86, even though they have no effect. 4059 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4060 for (const char *CC : CCs) { 4061 std::string GCCSpelling = "__attribute__((__"; 4062 GCCSpelling += CC; 4063 GCCSpelling += "__))"; 4064 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4065 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4066 } 4067 } 4068 } 4069 4070 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4071 Builder.defineMacro("__MSVCRT__"); 4072 Builder.defineMacro("__MINGW32__"); 4073 addCygMingDefines(Opts, Builder); 4074 } 4075 4076 // x86-32 MinGW target 4077 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4078 public: 4079 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4080 : WindowsX86_32TargetInfo(Triple, Opts) {} 4081 void getTargetDefines(const LangOptions &Opts, 4082 MacroBuilder &Builder) const override { 4083 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4084 DefineStd(Builder, "WIN32", Opts); 4085 DefineStd(Builder, "WINNT", Opts); 4086 Builder.defineMacro("_X86_"); 4087 addMinGWDefines(Opts, Builder); 4088 } 4089 }; 4090 4091 // x86-32 Cygwin target 4092 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4093 public: 4094 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4095 : X86_32TargetInfo(Triple, Opts) { 4096 WCharType = UnsignedShort; 4097 DoubleAlign = LongLongAlign = 64; 4098 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4099 } 4100 void getTargetDefines(const LangOptions &Opts, 4101 MacroBuilder &Builder) const override { 4102 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4103 Builder.defineMacro("_X86_"); 4104 Builder.defineMacro("__CYGWIN__"); 4105 Builder.defineMacro("__CYGWIN32__"); 4106 addCygMingDefines(Opts, Builder); 4107 DefineStd(Builder, "unix", Opts); 4108 if (Opts.CPlusPlus) 4109 Builder.defineMacro("_GNU_SOURCE"); 4110 } 4111 }; 4112 4113 // x86-32 Haiku target 4114 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4115 public: 4116 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4117 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4118 } 4119 void getTargetDefines(const LangOptions &Opts, 4120 MacroBuilder &Builder) const override { 4121 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4122 Builder.defineMacro("__INTEL__"); 4123 } 4124 }; 4125 4126 // X86-32 MCU target 4127 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4128 public: 4129 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4130 : X86_32TargetInfo(Triple, Opts) { 4131 LongDoubleWidth = 64; 4132 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4133 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4134 WIntType = UnsignedInt; 4135 } 4136 4137 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4138 // On MCU we support only C calling convention. 4139 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4140 } 4141 4142 void getTargetDefines(const LangOptions &Opts, 4143 MacroBuilder &Builder) const override { 4144 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4145 Builder.defineMacro("__iamcu"); 4146 Builder.defineMacro("__iamcu__"); 4147 } 4148 4149 bool allowsLargerPreferedTypeAlignment() const override { 4150 return false; 4151 } 4152 }; 4153 4154 // RTEMS Target 4155 template<typename Target> 4156 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4157 protected: 4158 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4159 MacroBuilder &Builder) const override { 4160 // RTEMS defines; list based off of gcc output 4161 4162 Builder.defineMacro("__rtems__"); 4163 Builder.defineMacro("__ELF__"); 4164 } 4165 4166 public: 4167 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4168 : OSTargetInfo<Target>(Triple, Opts) { 4169 switch (Triple.getArch()) { 4170 default: 4171 case llvm::Triple::x86: 4172 // this->MCountName = ".mcount"; 4173 break; 4174 case llvm::Triple::mips: 4175 case llvm::Triple::mipsel: 4176 case llvm::Triple::ppc: 4177 case llvm::Triple::ppc64: 4178 case llvm::Triple::ppc64le: 4179 // this->MCountName = "_mcount"; 4180 break; 4181 case llvm::Triple::arm: 4182 // this->MCountName = "__mcount"; 4183 break; 4184 } 4185 } 4186 }; 4187 4188 // x86-32 RTEMS target 4189 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4190 public: 4191 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4192 : X86_32TargetInfo(Triple, Opts) { 4193 SizeType = UnsignedLong; 4194 IntPtrType = SignedLong; 4195 PtrDiffType = SignedLong; 4196 } 4197 void getTargetDefines(const LangOptions &Opts, 4198 MacroBuilder &Builder) const override { 4199 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4200 Builder.defineMacro("__INTEL__"); 4201 Builder.defineMacro("__rtems__"); 4202 } 4203 }; 4204 4205 // x86-64 generic target 4206 class X86_64TargetInfo : public X86TargetInfo { 4207 public: 4208 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4209 : X86TargetInfo(Triple, Opts) { 4210 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4211 bool IsWinCOFF = 4212 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4213 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4214 LongDoubleWidth = 128; 4215 LongDoubleAlign = 128; 4216 LargeArrayMinWidth = 128; 4217 LargeArrayAlign = 128; 4218 SuitableAlign = 128; 4219 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4220 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4221 IntPtrType = IsX32 ? SignedInt : SignedLong; 4222 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4223 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4224 RegParmMax = 6; 4225 4226 // Pointers are 32-bit in x32. 4227 resetDataLayout(IsX32 4228 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4229 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4230 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4231 4232 // Use fpret only for long double. 4233 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4234 4235 // Use fp2ret for _Complex long double. 4236 ComplexLongDoubleUsesFP2Ret = true; 4237 4238 // Make __builtin_ms_va_list available. 4239 HasBuiltinMSVaList = true; 4240 4241 // x86-64 has atomics up to 16 bytes. 4242 MaxAtomicPromoteWidth = 128; 4243 MaxAtomicInlineWidth = 128; 4244 } 4245 BuiltinVaListKind getBuiltinVaListKind() const override { 4246 return TargetInfo::X86_64ABIBuiltinVaList; 4247 } 4248 4249 int getEHDataRegisterNumber(unsigned RegNo) const override { 4250 if (RegNo == 0) return 0; 4251 if (RegNo == 1) return 1; 4252 return -1; 4253 } 4254 4255 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4256 switch (CC) { 4257 case CC_C: 4258 case CC_Swift: 4259 case CC_X86VectorCall: 4260 case CC_IntelOclBicc: 4261 case CC_X86_64Win64: 4262 case CC_PreserveMost: 4263 case CC_PreserveAll: 4264 return CCCR_OK; 4265 default: 4266 return CCCR_Warning; 4267 } 4268 } 4269 4270 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4271 return CC_C; 4272 } 4273 4274 // for x32 we need it here explicitly 4275 bool hasInt128Type() const override { return true; } 4276 unsigned getUnwindWordWidth() const override { return 64; } 4277 unsigned getRegisterWidth() const override { return 64; } 4278 4279 bool validateGlobalRegisterVariable(StringRef RegName, 4280 unsigned RegSize, 4281 bool &HasSizeMismatch) const override { 4282 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4283 // handle. 4284 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4285 // Check that the register size is 64-bit. 4286 HasSizeMismatch = RegSize != 64; 4287 return true; 4288 } 4289 4290 // Check if the register is a 32-bit register the backend can handle. 4291 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4292 HasSizeMismatch); 4293 } 4294 }; 4295 4296 // x86-64 Windows target 4297 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4298 public: 4299 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4300 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4301 WCharType = UnsignedShort; 4302 LongWidth = LongAlign = 32; 4303 DoubleAlign = LongLongAlign = 64; 4304 IntMaxType = SignedLongLong; 4305 Int64Type = SignedLongLong; 4306 SizeType = UnsignedLongLong; 4307 PtrDiffType = SignedLongLong; 4308 IntPtrType = SignedLongLong; 4309 } 4310 4311 void getTargetDefines(const LangOptions &Opts, 4312 MacroBuilder &Builder) const override { 4313 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4314 Builder.defineMacro("_WIN64"); 4315 } 4316 4317 BuiltinVaListKind getBuiltinVaListKind() const override { 4318 return TargetInfo::CharPtrBuiltinVaList; 4319 } 4320 4321 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4322 switch (CC) { 4323 case CC_X86StdCall: 4324 case CC_X86ThisCall: 4325 case CC_X86FastCall: 4326 return CCCR_Ignore; 4327 case CC_C: 4328 case CC_X86VectorCall: 4329 case CC_IntelOclBicc: 4330 case CC_X86_64SysV: 4331 return CCCR_OK; 4332 default: 4333 return CCCR_Warning; 4334 } 4335 } 4336 }; 4337 4338 // x86-64 Windows Visual Studio target 4339 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4340 public: 4341 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4342 const TargetOptions &Opts) 4343 : WindowsX86_64TargetInfo(Triple, Opts) { 4344 LongDoubleWidth = LongDoubleAlign = 64; 4345 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4346 } 4347 void getTargetDefines(const LangOptions &Opts, 4348 MacroBuilder &Builder) const override { 4349 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4350 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4351 Builder.defineMacro("_M_X64", "100"); 4352 Builder.defineMacro("_M_AMD64", "100"); 4353 } 4354 }; 4355 4356 // x86-64 MinGW target 4357 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4358 public: 4359 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4360 : WindowsX86_64TargetInfo(Triple, Opts) { 4361 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4362 // with x86 FP ops. Weird. 4363 LongDoubleWidth = LongDoubleAlign = 128; 4364 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4365 } 4366 4367 void getTargetDefines(const LangOptions &Opts, 4368 MacroBuilder &Builder) const override { 4369 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4370 DefineStd(Builder, "WIN64", Opts); 4371 Builder.defineMacro("__MINGW64__"); 4372 addMinGWDefines(Opts, Builder); 4373 4374 // GCC defines this macro when it is using __gxx_personality_seh0. 4375 if (!Opts.SjLjExceptions) 4376 Builder.defineMacro("__SEH__"); 4377 } 4378 }; 4379 4380 // x86-64 Cygwin target 4381 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4382 public: 4383 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4384 : X86_64TargetInfo(Triple, Opts) { 4385 TLSSupported = false; 4386 WCharType = UnsignedShort; 4387 } 4388 void getTargetDefines(const LangOptions &Opts, 4389 MacroBuilder &Builder) const override { 4390 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4391 Builder.defineMacro("__x86_64__"); 4392 Builder.defineMacro("__CYGWIN__"); 4393 Builder.defineMacro("__CYGWIN64__"); 4394 addCygMingDefines(Opts, Builder); 4395 DefineStd(Builder, "unix", Opts); 4396 if (Opts.CPlusPlus) 4397 Builder.defineMacro("_GNU_SOURCE"); 4398 4399 // GCC defines this macro when it is using __gxx_personality_seh0. 4400 if (!Opts.SjLjExceptions) 4401 Builder.defineMacro("__SEH__"); 4402 } 4403 }; 4404 4405 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4406 public: 4407 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4408 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4409 Int64Type = SignedLongLong; 4410 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4411 llvm::Triple T = llvm::Triple(Triple); 4412 if (T.isiOS()) 4413 UseSignedCharForObjCBool = false; 4414 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4415 } 4416 4417 bool handleTargetFeatures(std::vector<std::string> &Features, 4418 DiagnosticsEngine &Diags) override { 4419 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4420 Diags)) 4421 return false; 4422 // We now know the features we have: we can decide how to align vectors. 4423 MaxVectorAlign = 4424 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4425 return true; 4426 } 4427 }; 4428 4429 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4430 public: 4431 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4432 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4433 IntMaxType = SignedLongLong; 4434 Int64Type = SignedLongLong; 4435 } 4436 }; 4437 4438 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4439 public: 4440 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4441 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4442 IntMaxType = SignedLongLong; 4443 Int64Type = SignedLongLong; 4444 } 4445 }; 4446 4447 class ARMTargetInfo : public TargetInfo { 4448 // Possible FPU choices. 4449 enum FPUMode { 4450 VFP2FPU = (1 << 0), 4451 VFP3FPU = (1 << 1), 4452 VFP4FPU = (1 << 2), 4453 NeonFPU = (1 << 3), 4454 FPARMV8 = (1 << 4) 4455 }; 4456 4457 // Possible HWDiv features. 4458 enum HWDivMode { 4459 HWDivThumb = (1 << 0), 4460 HWDivARM = (1 << 1) 4461 }; 4462 4463 static bool FPUModeIsVFP(FPUMode Mode) { 4464 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4465 } 4466 4467 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4468 static const char * const GCCRegNames[]; 4469 4470 std::string ABI, CPU; 4471 4472 StringRef CPUProfile; 4473 StringRef CPUAttr; 4474 4475 enum { 4476 FP_Default, 4477 FP_VFP, 4478 FP_Neon 4479 } FPMath; 4480 4481 unsigned ArchISA; 4482 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4483 unsigned ArchProfile; 4484 unsigned ArchVersion; 4485 4486 unsigned FPU : 5; 4487 4488 unsigned IsAAPCS : 1; 4489 unsigned HWDiv : 2; 4490 4491 // Initialized via features. 4492 unsigned SoftFloat : 1; 4493 unsigned SoftFloatABI : 1; 4494 4495 unsigned CRC : 1; 4496 unsigned Crypto : 1; 4497 unsigned DSP : 1; 4498 unsigned Unaligned : 1; 4499 4500 enum { 4501 LDREX_B = (1 << 0), /// byte (8-bit) 4502 LDREX_H = (1 << 1), /// half (16-bit) 4503 LDREX_W = (1 << 2), /// word (32-bit) 4504 LDREX_D = (1 << 3), /// double (64-bit) 4505 }; 4506 4507 uint32_t LDREX; 4508 4509 // ACLE 6.5.1 Hardware floating point 4510 enum { 4511 HW_FP_HP = (1 << 1), /// half (16-bit) 4512 HW_FP_SP = (1 << 2), /// single (32-bit) 4513 HW_FP_DP = (1 << 3), /// double (64-bit) 4514 }; 4515 uint32_t HW_FP; 4516 4517 static const Builtin::Info BuiltinInfo[]; 4518 4519 void setABIAAPCS() { 4520 IsAAPCS = true; 4521 4522 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4523 const llvm::Triple &T = getTriple(); 4524 4525 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4526 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4527 T.getOS() == llvm::Triple::Bitrig) 4528 SizeType = UnsignedLong; 4529 else 4530 SizeType = UnsignedInt; 4531 4532 switch (T.getOS()) { 4533 case llvm::Triple::NetBSD: 4534 WCharType = SignedInt; 4535 break; 4536 case llvm::Triple::Win32: 4537 WCharType = UnsignedShort; 4538 break; 4539 case llvm::Triple::Linux: 4540 default: 4541 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4542 WCharType = UnsignedInt; 4543 break; 4544 } 4545 4546 UseBitFieldTypeAlignment = true; 4547 4548 ZeroLengthBitfieldBoundary = 0; 4549 4550 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4551 // so set preferred for small types to 32. 4552 if (T.isOSBinFormatMachO()) { 4553 resetDataLayout(BigEndian 4554 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4555 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4556 } else if (T.isOSWindows()) { 4557 assert(!BigEndian && "Windows on ARM does not support big endian"); 4558 resetDataLayout("e" 4559 "-m:w" 4560 "-p:32:32" 4561 "-i64:64" 4562 "-v128:64:128" 4563 "-a:0:32" 4564 "-n32" 4565 "-S64"); 4566 } else if (T.isOSNaCl()) { 4567 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4568 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4569 } else { 4570 resetDataLayout(BigEndian 4571 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4572 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4573 } 4574 4575 // FIXME: Enumerated types are variable width in straight AAPCS. 4576 } 4577 4578 void setABIAPCS(bool IsAAPCS16) { 4579 const llvm::Triple &T = getTriple(); 4580 4581 IsAAPCS = false; 4582 4583 if (IsAAPCS16) 4584 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4585 else 4586 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4587 4588 // size_t is unsigned int on FreeBSD. 4589 if (T.getOS() == llvm::Triple::FreeBSD) 4590 SizeType = UnsignedInt; 4591 else 4592 SizeType = UnsignedLong; 4593 4594 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4595 WCharType = SignedInt; 4596 4597 // Do not respect the alignment of bit-field types when laying out 4598 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4599 UseBitFieldTypeAlignment = false; 4600 4601 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4602 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4603 /// gcc. 4604 ZeroLengthBitfieldBoundary = 32; 4605 4606 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4607 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4608 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4609 } else if (T.isOSBinFormatMachO()) 4610 resetDataLayout( 4611 BigEndian 4612 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4613 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4614 else 4615 resetDataLayout( 4616 BigEndian 4617 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4618 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4619 4620 // FIXME: Override "preferred align" for double and long long. 4621 } 4622 4623 void setArchInfo() { 4624 StringRef ArchName = getTriple().getArchName(); 4625 4626 ArchISA = llvm::ARM::parseArchISA(ArchName); 4627 CPU = llvm::ARM::getDefaultCPU(ArchName); 4628 unsigned AK = llvm::ARM::parseArch(ArchName); 4629 if (AK != llvm::ARM::AK_INVALID) 4630 ArchKind = AK; 4631 setArchInfo(ArchKind); 4632 } 4633 4634 void setArchInfo(unsigned Kind) { 4635 StringRef SubArch; 4636 4637 // cache TargetParser info 4638 ArchKind = Kind; 4639 SubArch = llvm::ARM::getSubArch(ArchKind); 4640 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4641 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4642 4643 // cache CPU related strings 4644 CPUAttr = getCPUAttr(); 4645 CPUProfile = getCPUProfile(); 4646 } 4647 4648 void setAtomic() { 4649 // when triple does not specify a sub arch, 4650 // then we are not using inline atomics 4651 bool ShouldUseInlineAtomic = 4652 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4653 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4654 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4655 if (ArchProfile == llvm::ARM::PK_M) { 4656 MaxAtomicPromoteWidth = 32; 4657 if (ShouldUseInlineAtomic) 4658 MaxAtomicInlineWidth = 32; 4659 } 4660 else { 4661 MaxAtomicPromoteWidth = 64; 4662 if (ShouldUseInlineAtomic) 4663 MaxAtomicInlineWidth = 64; 4664 } 4665 } 4666 4667 bool isThumb() const { 4668 return (ArchISA == llvm::ARM::IK_THUMB); 4669 } 4670 4671 bool supportsThumb() const { 4672 return CPUAttr.count('T') || ArchVersion >= 6; 4673 } 4674 4675 bool supportsThumb2() const { 4676 return CPUAttr.equals("6T2") || 4677 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 4678 } 4679 4680 StringRef getCPUAttr() const { 4681 // For most sub-arches, the build attribute CPU name is enough. 4682 // For Cortex variants, it's slightly different. 4683 switch(ArchKind) { 4684 default: 4685 return llvm::ARM::getCPUAttr(ArchKind); 4686 case llvm::ARM::AK_ARMV6M: 4687 return "6M"; 4688 case llvm::ARM::AK_ARMV7S: 4689 return "7S"; 4690 case llvm::ARM::AK_ARMV7A: 4691 return "7A"; 4692 case llvm::ARM::AK_ARMV7R: 4693 return "7R"; 4694 case llvm::ARM::AK_ARMV7M: 4695 return "7M"; 4696 case llvm::ARM::AK_ARMV7EM: 4697 return "7EM"; 4698 case llvm::ARM::AK_ARMV8A: 4699 return "8A"; 4700 case llvm::ARM::AK_ARMV8_1A: 4701 return "8_1A"; 4702 case llvm::ARM::AK_ARMV8_2A: 4703 return "8_2A"; 4704 case llvm::ARM::AK_ARMV8MBaseline: 4705 return "8M_BASE"; 4706 case llvm::ARM::AK_ARMV8MMainline: 4707 return "8M_MAIN"; 4708 } 4709 } 4710 4711 StringRef getCPUProfile() const { 4712 switch(ArchProfile) { 4713 case llvm::ARM::PK_A: 4714 return "A"; 4715 case llvm::ARM::PK_R: 4716 return "R"; 4717 case llvm::ARM::PK_M: 4718 return "M"; 4719 default: 4720 return ""; 4721 } 4722 } 4723 4724 public: 4725 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 4726 bool IsBigEndian) 4727 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 4728 HW_FP(0) { 4729 BigEndian = IsBigEndian; 4730 4731 switch (getTriple().getOS()) { 4732 case llvm::Triple::NetBSD: 4733 PtrDiffType = SignedLong; 4734 break; 4735 default: 4736 PtrDiffType = SignedInt; 4737 break; 4738 } 4739 4740 // Cache arch related info. 4741 setArchInfo(); 4742 4743 // {} in inline assembly are neon specifiers, not assembly variant 4744 // specifiers. 4745 NoAsmVariants = true; 4746 4747 // FIXME: This duplicates code from the driver that sets the -target-abi 4748 // option - this code is used if -target-abi isn't passed and should 4749 // be unified in some way. 4750 if (Triple.isOSBinFormatMachO()) { 4751 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4752 // the frontend matches that. 4753 if (Triple.getEnvironment() == llvm::Triple::EABI || 4754 Triple.getOS() == llvm::Triple::UnknownOS || 4755 StringRef(CPU).startswith("cortex-m")) { 4756 setABI("aapcs"); 4757 } else if (Triple.isWatchABI()) { 4758 setABI("aapcs16"); 4759 } else { 4760 setABI("apcs-gnu"); 4761 } 4762 } else if (Triple.isOSWindows()) { 4763 // FIXME: this is invalid for WindowsCE 4764 setABI("aapcs"); 4765 } else { 4766 // Select the default based on the platform. 4767 switch (Triple.getEnvironment()) { 4768 case llvm::Triple::Android: 4769 case llvm::Triple::GNUEABI: 4770 case llvm::Triple::GNUEABIHF: 4771 setABI("aapcs-linux"); 4772 break; 4773 case llvm::Triple::EABIHF: 4774 case llvm::Triple::EABI: 4775 setABI("aapcs"); 4776 break; 4777 case llvm::Triple::GNU: 4778 setABI("apcs-gnu"); 4779 break; 4780 default: 4781 if (Triple.getOS() == llvm::Triple::NetBSD) 4782 setABI("apcs-gnu"); 4783 else 4784 setABI("aapcs"); 4785 break; 4786 } 4787 } 4788 4789 // ARM targets default to using the ARM C++ ABI. 4790 TheCXXABI.set(TargetCXXABI::GenericARM); 4791 4792 // ARM has atomics up to 8 bytes 4793 setAtomic(); 4794 4795 // Do force alignment of members that follow zero length bitfields. If 4796 // the alignment of the zero-length bitfield is greater than the member 4797 // that follows it, `bar', `bar' will be aligned as the type of the 4798 // zero length bitfield. 4799 UseZeroLengthBitfieldAlignment = true; 4800 4801 if (Triple.getOS() == llvm::Triple::Linux || 4802 Triple.getOS() == llvm::Triple::UnknownOS) 4803 this->MCountName = 4804 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 4805 } 4806 4807 StringRef getABI() const override { return ABI; } 4808 4809 bool setABI(const std::string &Name) override { 4810 ABI = Name; 4811 4812 // The defaults (above) are for AAPCS, check if we need to change them. 4813 // 4814 // FIXME: We need support for -meabi... we could just mangle it into the 4815 // name. 4816 if (Name == "apcs-gnu" || Name == "aapcs16") { 4817 setABIAPCS(Name == "aapcs16"); 4818 return true; 4819 } 4820 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4821 setABIAAPCS(); 4822 return true; 4823 } 4824 return false; 4825 } 4826 4827 // FIXME: This should be based on Arch attributes, not CPU names. 4828 bool 4829 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4830 StringRef CPU, 4831 const std::vector<std::string> &FeaturesVec) const override { 4832 4833 std::vector<const char*> TargetFeatures; 4834 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4835 4836 // get default FPU features 4837 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4838 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4839 4840 // get default Extension features 4841 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 4842 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4843 4844 for (const char *Feature : TargetFeatures) 4845 if (Feature[0] == '+') 4846 Features[Feature+1] = true; 4847 4848 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4849 } 4850 4851 bool handleTargetFeatures(std::vector<std::string> &Features, 4852 DiagnosticsEngine &Diags) override { 4853 FPU = 0; 4854 CRC = 0; 4855 Crypto = 0; 4856 DSP = 0; 4857 Unaligned = 1; 4858 SoftFloat = SoftFloatABI = false; 4859 HWDiv = 0; 4860 4861 // This does not diagnose illegal cases like having both 4862 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4863 uint32_t HW_FP_remove = 0; 4864 for (const auto &Feature : Features) { 4865 if (Feature == "+soft-float") { 4866 SoftFloat = true; 4867 } else if (Feature == "+soft-float-abi") { 4868 SoftFloatABI = true; 4869 } else if (Feature == "+vfp2") { 4870 FPU |= VFP2FPU; 4871 HW_FP |= HW_FP_SP | HW_FP_DP; 4872 } else if (Feature == "+vfp3") { 4873 FPU |= VFP3FPU; 4874 HW_FP |= HW_FP_SP | HW_FP_DP; 4875 } else if (Feature == "+vfp4") { 4876 FPU |= VFP4FPU; 4877 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4878 } else if (Feature == "+fp-armv8") { 4879 FPU |= FPARMV8; 4880 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4881 } else if (Feature == "+neon") { 4882 FPU |= NeonFPU; 4883 HW_FP |= HW_FP_SP | HW_FP_DP; 4884 } else if (Feature == "+hwdiv") { 4885 HWDiv |= HWDivThumb; 4886 } else if (Feature == "+hwdiv-arm") { 4887 HWDiv |= HWDivARM; 4888 } else if (Feature == "+crc") { 4889 CRC = 1; 4890 } else if (Feature == "+crypto") { 4891 Crypto = 1; 4892 } else if (Feature == "+dsp") { 4893 DSP = 1; 4894 } else if (Feature == "+fp-only-sp") { 4895 HW_FP_remove |= HW_FP_DP; 4896 } else if (Feature == "+strict-align") { 4897 Unaligned = 0; 4898 } else if (Feature == "+fp16") { 4899 HW_FP |= HW_FP_HP; 4900 } 4901 } 4902 HW_FP &= ~HW_FP_remove; 4903 4904 switch (ArchVersion) { 4905 case 6: 4906 if (ArchProfile == llvm::ARM::PK_M) 4907 LDREX = 0; 4908 else if (ArchKind == llvm::ARM::AK_ARMV6K) 4909 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4910 else 4911 LDREX = LDREX_W; 4912 break; 4913 case 7: 4914 if (ArchProfile == llvm::ARM::PK_M) 4915 LDREX = LDREX_W | LDREX_H | LDREX_B ; 4916 else 4917 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4918 break; 4919 case 8: 4920 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4921 } 4922 4923 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4924 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4925 return false; 4926 } 4927 4928 if (FPMath == FP_Neon) 4929 Features.push_back("+neonfp"); 4930 else if (FPMath == FP_VFP) 4931 Features.push_back("-neonfp"); 4932 4933 // Remove front-end specific options which the backend handles differently. 4934 auto Feature = 4935 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4936 if (Feature != Features.end()) 4937 Features.erase(Feature); 4938 4939 return true; 4940 } 4941 4942 bool hasFeature(StringRef Feature) const override { 4943 return llvm::StringSwitch<bool>(Feature) 4944 .Case("arm", true) 4945 .Case("aarch32", true) 4946 .Case("softfloat", SoftFloat) 4947 .Case("thumb", isThumb()) 4948 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4949 .Case("hwdiv", HWDiv & HWDivThumb) 4950 .Case("hwdiv-arm", HWDiv & HWDivARM) 4951 .Default(false); 4952 } 4953 4954 bool setCPU(const std::string &Name) override { 4955 if (Name != "generic") 4956 setArchInfo(llvm::ARM::parseCPUArch(Name)); 4957 4958 if (ArchKind == llvm::ARM::AK_INVALID) 4959 return false; 4960 setAtomic(); 4961 CPU = Name; 4962 return true; 4963 } 4964 4965 bool setFPMath(StringRef Name) override; 4966 4967 void getTargetDefines(const LangOptions &Opts, 4968 MacroBuilder &Builder) const override { 4969 // Target identification. 4970 Builder.defineMacro("__arm"); 4971 Builder.defineMacro("__arm__"); 4972 // For bare-metal none-eabi. 4973 if (getTriple().getOS() == llvm::Triple::UnknownOS && 4974 getTriple().getEnvironment() == llvm::Triple::EABI) 4975 Builder.defineMacro("__ELF__"); 4976 4977 // Target properties. 4978 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4979 4980 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 4981 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 4982 if (getTriple().isWatchABI()) 4983 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 4984 4985 if (!CPUAttr.empty()) 4986 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 4987 4988 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4989 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4990 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 4991 4992 if (ArchVersion >= 8) { 4993 // ACLE 6.5.7 Crypto Extension 4994 if (Crypto) 4995 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 4996 // ACLE 6.5.8 CRC32 Extension 4997 if (CRC) 4998 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 4999 // ACLE 6.5.10 Numeric Maximum and Minimum 5000 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5001 // ACLE 6.5.9 Directed Rounding 5002 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5003 } 5004 5005 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5006 // is not defined for the M-profile. 5007 // NOTE that the default profile is assumed to be 'A' 5008 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5009 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5010 5011 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5012 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5013 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5014 // v7 and v8 architectures excluding v8-M Baseline. 5015 if (supportsThumb2()) 5016 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5017 else if (supportsThumb()) 5018 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5019 5020 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5021 // instruction set such as ARM or Thumb. 5022 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5023 5024 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5025 5026 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5027 if (!CPUProfile.empty()) 5028 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5029 5030 // ACLE 6.4.3 Unaligned access supported in hardware 5031 if (Unaligned) 5032 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5033 5034 // ACLE 6.4.4 LDREX/STREX 5035 if (LDREX) 5036 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5037 5038 // ACLE 6.4.5 CLZ 5039 if (ArchVersion == 5 || 5040 (ArchVersion == 6 && CPUProfile != "M") || 5041 ArchVersion > 6) 5042 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5043 5044 // ACLE 6.5.1 Hardware Floating Point 5045 if (HW_FP) 5046 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5047 5048 // ACLE predefines. 5049 Builder.defineMacro("__ARM_ACLE", "200"); 5050 5051 // FP16 support (we currently only support IEEE format). 5052 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5053 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5054 5055 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5056 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5057 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5058 5059 // Subtarget options. 5060 5061 // FIXME: It's more complicated than this and we don't really support 5062 // interworking. 5063 // Windows on ARM does not "support" interworking 5064 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5065 Builder.defineMacro("__THUMB_INTERWORK__"); 5066 5067 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5068 // Embedded targets on Darwin follow AAPCS, but not EABI. 5069 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5070 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 5071 Builder.defineMacro("__ARM_EABI__"); 5072 Builder.defineMacro("__ARM_PCS", "1"); 5073 } 5074 5075 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5076 ABI == "aapcs16") 5077 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5078 5079 if (SoftFloat) 5080 Builder.defineMacro("__SOFTFP__"); 5081 5082 if (CPU == "xscale") 5083 Builder.defineMacro("__XSCALE__"); 5084 5085 if (isThumb()) { 5086 Builder.defineMacro("__THUMBEL__"); 5087 Builder.defineMacro("__thumb__"); 5088 if (supportsThumb2()) 5089 Builder.defineMacro("__thumb2__"); 5090 } 5091 5092 // ACLE 6.4.9 32-bit SIMD instructions 5093 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5094 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5095 5096 // ACLE 6.4.10 Hardware Integer Divide 5097 if (((HWDiv & HWDivThumb) && isThumb()) || 5098 ((HWDiv & HWDivARM) && !isThumb())) { 5099 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5100 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5101 } 5102 5103 // Note, this is always on in gcc, even though it doesn't make sense. 5104 Builder.defineMacro("__APCS_32__"); 5105 5106 if (FPUModeIsVFP((FPUMode) FPU)) { 5107 Builder.defineMacro("__VFP_FP__"); 5108 if (FPU & VFP2FPU) 5109 Builder.defineMacro("__ARM_VFPV2__"); 5110 if (FPU & VFP3FPU) 5111 Builder.defineMacro("__ARM_VFPV3__"); 5112 if (FPU & VFP4FPU) 5113 Builder.defineMacro("__ARM_VFPV4__"); 5114 } 5115 5116 // This only gets set when Neon instructions are actually available, unlike 5117 // the VFP define, hence the soft float and arch check. This is subtly 5118 // different from gcc, we follow the intent which was that it should be set 5119 // when Neon instructions are actually available. 5120 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5121 Builder.defineMacro("__ARM_NEON", "1"); 5122 Builder.defineMacro("__ARM_NEON__"); 5123 // current AArch32 NEON implementations do not support double-precision 5124 // floating-point even when it is present in VFP. 5125 Builder.defineMacro("__ARM_NEON_FP", 5126 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5127 } 5128 5129 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5130 Opts.ShortWChar ? "2" : "4"); 5131 5132 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5133 Opts.ShortEnums ? "1" : "4"); 5134 5135 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5136 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5137 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5138 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5139 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5140 } 5141 5142 // ACLE 6.4.7 DSP instructions 5143 if (DSP) { 5144 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5145 } 5146 5147 // ACLE 6.4.8 Saturation instructions 5148 bool SAT = false; 5149 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5150 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5151 SAT = true; 5152 } 5153 5154 // ACLE 6.4.6 Q (saturation) flag 5155 if (DSP || SAT) 5156 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5157 5158 if (Opts.UnsafeFPMath) 5159 Builder.defineMacro("__ARM_FP_FAST", "1"); 5160 5161 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5162 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5163 } 5164 5165 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5166 return llvm::makeArrayRef(BuiltinInfo, 5167 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5168 } 5169 bool isCLZForZeroUndef() const override { return false; } 5170 BuiltinVaListKind getBuiltinVaListKind() const override { 5171 return IsAAPCS 5172 ? AAPCSABIBuiltinVaList 5173 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5174 : TargetInfo::VoidPtrBuiltinVaList); 5175 } 5176 ArrayRef<const char *> getGCCRegNames() const override; 5177 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5178 bool validateAsmConstraint(const char *&Name, 5179 TargetInfo::ConstraintInfo &Info) const override { 5180 switch (*Name) { 5181 default: break; 5182 case 'l': // r0-r7 5183 case 'h': // r8-r15 5184 case 't': // VFP Floating point register single precision 5185 case 'w': // VFP Floating point register double precision 5186 Info.setAllowsRegister(); 5187 return true; 5188 case 'I': 5189 case 'J': 5190 case 'K': 5191 case 'L': 5192 case 'M': 5193 // FIXME 5194 return true; 5195 case 'Q': // A memory address that is a single base register. 5196 Info.setAllowsMemory(); 5197 return true; 5198 case 'U': // a memory reference... 5199 switch (Name[1]) { 5200 case 'q': // ...ARMV4 ldrsb 5201 case 'v': // ...VFP load/store (reg+constant offset) 5202 case 'y': // ...iWMMXt load/store 5203 case 't': // address valid for load/store opaque types wider 5204 // than 128-bits 5205 case 'n': // valid address for Neon doubleword vector load/store 5206 case 'm': // valid address for Neon element and structure load/store 5207 case 's': // valid address for non-offset loads/stores of quad-word 5208 // values in four ARM registers 5209 Info.setAllowsMemory(); 5210 Name++; 5211 return true; 5212 } 5213 } 5214 return false; 5215 } 5216 std::string convertConstraint(const char *&Constraint) const override { 5217 std::string R; 5218 switch (*Constraint) { 5219 case 'U': // Two-character constraint; add "^" hint for later parsing. 5220 R = std::string("^") + std::string(Constraint, 2); 5221 Constraint++; 5222 break; 5223 case 'p': // 'p' should be translated to 'r' by default. 5224 R = std::string("r"); 5225 break; 5226 default: 5227 return std::string(1, *Constraint); 5228 } 5229 return R; 5230 } 5231 bool 5232 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5233 std::string &SuggestedModifier) const override { 5234 bool isOutput = (Constraint[0] == '='); 5235 bool isInOut = (Constraint[0] == '+'); 5236 5237 // Strip off constraint modifiers. 5238 while (Constraint[0] == '=' || 5239 Constraint[0] == '+' || 5240 Constraint[0] == '&') 5241 Constraint = Constraint.substr(1); 5242 5243 switch (Constraint[0]) { 5244 default: break; 5245 case 'r': { 5246 switch (Modifier) { 5247 default: 5248 return (isInOut || isOutput || Size <= 64); 5249 case 'q': 5250 // A register of size 32 cannot fit a vector type. 5251 return false; 5252 } 5253 } 5254 } 5255 5256 return true; 5257 } 5258 const char *getClobbers() const override { 5259 // FIXME: Is this really right? 5260 return ""; 5261 } 5262 5263 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5264 switch (CC) { 5265 case CC_AAPCS: 5266 case CC_AAPCS_VFP: 5267 case CC_Swift: 5268 return CCCR_OK; 5269 default: 5270 return CCCR_Warning; 5271 } 5272 } 5273 5274 int getEHDataRegisterNumber(unsigned RegNo) const override { 5275 if (RegNo == 0) return 0; 5276 if (RegNo == 1) return 1; 5277 return -1; 5278 } 5279 5280 bool hasSjLjLowering() const override { 5281 return true; 5282 } 5283 }; 5284 5285 bool ARMTargetInfo::setFPMath(StringRef Name) { 5286 if (Name == "neon") { 5287 FPMath = FP_Neon; 5288 return true; 5289 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5290 Name == "vfp4") { 5291 FPMath = FP_VFP; 5292 return true; 5293 } 5294 return false; 5295 } 5296 5297 const char * const ARMTargetInfo::GCCRegNames[] = { 5298 // Integer registers 5299 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5300 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5301 5302 // Float registers 5303 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5304 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5305 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5306 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5307 5308 // Double registers 5309 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5310 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5311 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5312 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5313 5314 // Quad registers 5315 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5316 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5317 }; 5318 5319 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5320 return llvm::makeArrayRef(GCCRegNames); 5321 } 5322 5323 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5324 { { "a1" }, "r0" }, 5325 { { "a2" }, "r1" }, 5326 { { "a3" }, "r2" }, 5327 { { "a4" }, "r3" }, 5328 { { "v1" }, "r4" }, 5329 { { "v2" }, "r5" }, 5330 { { "v3" }, "r6" }, 5331 { { "v4" }, "r7" }, 5332 { { "v5" }, "r8" }, 5333 { { "v6", "rfp" }, "r9" }, 5334 { { "sl" }, "r10" }, 5335 { { "fp" }, "r11" }, 5336 { { "ip" }, "r12" }, 5337 { { "r13" }, "sp" }, 5338 { { "r14" }, "lr" }, 5339 { { "r15" }, "pc" }, 5340 // The S, D and Q registers overlap, but aren't really aliases; we 5341 // don't want to substitute one of these for a different-sized one. 5342 }; 5343 5344 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5345 return llvm::makeArrayRef(GCCRegAliases); 5346 } 5347 5348 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5349 #define BUILTIN(ID, TYPE, ATTRS) \ 5350 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5351 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5352 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5353 #include "clang/Basic/BuiltinsNEON.def" 5354 5355 #define BUILTIN(ID, TYPE, ATTRS) \ 5356 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5357 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5358 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5359 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5360 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5361 #include "clang/Basic/BuiltinsARM.def" 5362 }; 5363 5364 class ARMleTargetInfo : public ARMTargetInfo { 5365 public: 5366 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5367 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/false) {} 5368 void getTargetDefines(const LangOptions &Opts, 5369 MacroBuilder &Builder) const override { 5370 Builder.defineMacro("__ARMEL__"); 5371 ARMTargetInfo::getTargetDefines(Opts, Builder); 5372 } 5373 }; 5374 5375 class ARMbeTargetInfo : public ARMTargetInfo { 5376 public: 5377 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5378 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/true) {} 5379 void getTargetDefines(const LangOptions &Opts, 5380 MacroBuilder &Builder) const override { 5381 Builder.defineMacro("__ARMEB__"); 5382 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5383 ARMTargetInfo::getTargetDefines(Opts, Builder); 5384 } 5385 }; 5386 5387 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5388 const llvm::Triple Triple; 5389 public: 5390 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5391 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5392 WCharType = UnsignedShort; 5393 SizeType = UnsignedInt; 5394 } 5395 void getVisualStudioDefines(const LangOptions &Opts, 5396 MacroBuilder &Builder) const { 5397 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5398 5399 // FIXME: this is invalid for WindowsCE 5400 Builder.defineMacro("_M_ARM_NT", "1"); 5401 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5402 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5403 5404 assert((Triple.getArch() == llvm::Triple::arm || 5405 Triple.getArch() == llvm::Triple::thumb) && 5406 "invalid architecture for Windows ARM target info"); 5407 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5408 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5409 5410 // TODO map the complete set of values 5411 // 31: VFPv3 40: VFPv4 5412 Builder.defineMacro("_M_ARM_FP", "31"); 5413 } 5414 BuiltinVaListKind getBuiltinVaListKind() const override { 5415 return TargetInfo::CharPtrBuiltinVaList; 5416 } 5417 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5418 switch (CC) { 5419 case CC_X86StdCall: 5420 case CC_X86ThisCall: 5421 case CC_X86FastCall: 5422 case CC_X86VectorCall: 5423 return CCCR_Ignore; 5424 case CC_C: 5425 return CCCR_OK; 5426 default: 5427 return CCCR_Warning; 5428 } 5429 } 5430 }; 5431 5432 // Windows ARM + Itanium C++ ABI Target 5433 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5434 public: 5435 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5436 const TargetOptions &Opts) 5437 : WindowsARMTargetInfo(Triple, Opts) { 5438 TheCXXABI.set(TargetCXXABI::GenericARM); 5439 } 5440 5441 void getTargetDefines(const LangOptions &Opts, 5442 MacroBuilder &Builder) const override { 5443 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5444 5445 if (Opts.MSVCCompat) 5446 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5447 } 5448 }; 5449 5450 // Windows ARM, MS (C++) ABI 5451 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5452 public: 5453 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5454 const TargetOptions &Opts) 5455 : WindowsARMTargetInfo(Triple, Opts) { 5456 TheCXXABI.set(TargetCXXABI::Microsoft); 5457 } 5458 5459 void getTargetDefines(const LangOptions &Opts, 5460 MacroBuilder &Builder) const override { 5461 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5462 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5463 } 5464 }; 5465 5466 // ARM MinGW target 5467 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5468 public: 5469 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5470 : WindowsARMTargetInfo(Triple, Opts) { 5471 TheCXXABI.set(TargetCXXABI::GenericARM); 5472 } 5473 5474 void getTargetDefines(const LangOptions &Opts, 5475 MacroBuilder &Builder) const override { 5476 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5477 DefineStd(Builder, "WIN32", Opts); 5478 DefineStd(Builder, "WINNT", Opts); 5479 Builder.defineMacro("_ARM_"); 5480 addMinGWDefines(Opts, Builder); 5481 } 5482 }; 5483 5484 // ARM Cygwin target 5485 class CygwinARMTargetInfo : public ARMleTargetInfo { 5486 public: 5487 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5488 : ARMleTargetInfo(Triple, Opts) { 5489 TLSSupported = false; 5490 WCharType = UnsignedShort; 5491 DoubleAlign = LongLongAlign = 64; 5492 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5493 } 5494 void getTargetDefines(const LangOptions &Opts, 5495 MacroBuilder &Builder) const override { 5496 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5497 Builder.defineMacro("_ARM_"); 5498 Builder.defineMacro("__CYGWIN__"); 5499 Builder.defineMacro("__CYGWIN32__"); 5500 DefineStd(Builder, "unix", Opts); 5501 if (Opts.CPlusPlus) 5502 Builder.defineMacro("_GNU_SOURCE"); 5503 } 5504 }; 5505 5506 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 5507 protected: 5508 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5509 MacroBuilder &Builder) const override { 5510 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5511 } 5512 5513 public: 5514 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5515 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 5516 HasAlignMac68kSupport = true; 5517 // iOS always has 64-bit atomic instructions. 5518 // FIXME: This should be based off of the target features in 5519 // ARMleTargetInfo. 5520 MaxAtomicInlineWidth = 64; 5521 5522 if (Triple.isWatchABI()) { 5523 // Darwin on iOS uses a variant of the ARM C++ ABI. 5524 TheCXXABI.set(TargetCXXABI::WatchOS); 5525 5526 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5527 // size_t is long, it's a bit weird for it to be int. 5528 PtrDiffType = SignedLong; 5529 5530 // BOOL should be a real boolean on the new ABI 5531 UseSignedCharForObjCBool = false; 5532 } else 5533 TheCXXABI.set(TargetCXXABI::iOS); 5534 } 5535 }; 5536 5537 class AArch64TargetInfo : public TargetInfo { 5538 virtual void setDataLayout() = 0; 5539 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5540 static const char *const GCCRegNames[]; 5541 5542 enum FPUModeEnum { 5543 FPUMode, 5544 NeonMode 5545 }; 5546 5547 unsigned FPU; 5548 unsigned CRC; 5549 unsigned Crypto; 5550 unsigned Unaligned; 5551 unsigned V8_1A; 5552 5553 static const Builtin::Info BuiltinInfo[]; 5554 5555 std::string ABI; 5556 5557 public: 5558 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5559 : TargetInfo(Triple), ABI("aapcs") { 5560 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5561 WCharType = SignedInt; 5562 5563 // NetBSD apparently prefers consistency across ARM targets to consistency 5564 // across 64-bit targets. 5565 Int64Type = SignedLongLong; 5566 IntMaxType = SignedLongLong; 5567 } else { 5568 WCharType = UnsignedInt; 5569 Int64Type = SignedLong; 5570 IntMaxType = SignedLong; 5571 } 5572 5573 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5574 MaxVectorAlign = 128; 5575 MaxAtomicInlineWidth = 128; 5576 MaxAtomicPromoteWidth = 128; 5577 5578 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5579 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5580 5581 // {} in inline assembly are neon specifiers, not assembly variant 5582 // specifiers. 5583 NoAsmVariants = true; 5584 5585 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5586 // contributes to the alignment of the containing aggregate in the same way 5587 // a plain (non bit-field) member of that type would, without exception for 5588 // zero-sized or anonymous bit-fields." 5589 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5590 UseZeroLengthBitfieldAlignment = true; 5591 5592 // AArch64 targets default to using the ARM C++ ABI. 5593 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5594 5595 if (Triple.getOS() == llvm::Triple::Linux || 5596 Triple.getOS() == llvm::Triple::UnknownOS) 5597 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 5598 } 5599 5600 StringRef getABI() const override { return ABI; } 5601 bool setABI(const std::string &Name) override { 5602 if (Name != "aapcs" && Name != "darwinpcs") 5603 return false; 5604 5605 ABI = Name; 5606 return true; 5607 } 5608 5609 bool setCPU(const std::string &Name) override { 5610 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5611 .Case("generic", true) 5612 .Cases("cortex-a53", "cortex-a57", "cortex-a72", 5613 "cortex-a35", "exynos-m1", true) 5614 .Case("cyclone", true) 5615 .Case("kryo", true) 5616 .Default(false); 5617 return CPUKnown; 5618 } 5619 5620 void getTargetDefines(const LangOptions &Opts, 5621 MacroBuilder &Builder) const override { 5622 // Target identification. 5623 Builder.defineMacro("__aarch64__"); 5624 5625 // Target properties. 5626 Builder.defineMacro("_LP64"); 5627 Builder.defineMacro("__LP64__"); 5628 5629 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5630 Builder.defineMacro("__ARM_ACLE", "200"); 5631 Builder.defineMacro("__ARM_ARCH", "8"); 5632 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5633 5634 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5635 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5636 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5637 5638 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5639 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5640 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5641 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5642 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5643 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5644 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5645 5646 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5647 5648 // 0xe implies support for half, single and double precision operations. 5649 Builder.defineMacro("__ARM_FP", "0xE"); 5650 5651 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5652 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5653 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5654 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5655 5656 if (Opts.UnsafeFPMath) 5657 Builder.defineMacro("__ARM_FP_FAST", "1"); 5658 5659 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5660 5661 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5662 Opts.ShortEnums ? "1" : "4"); 5663 5664 if (FPU == NeonMode) { 5665 Builder.defineMacro("__ARM_NEON", "1"); 5666 // 64-bit NEON supports half, single and double precision operations. 5667 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5668 } 5669 5670 if (CRC) 5671 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5672 5673 if (Crypto) 5674 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5675 5676 if (Unaligned) 5677 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5678 5679 if (V8_1A) 5680 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5681 5682 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5683 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5684 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5685 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5686 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5687 } 5688 5689 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5690 return llvm::makeArrayRef(BuiltinInfo, 5691 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5692 } 5693 5694 bool hasFeature(StringRef Feature) const override { 5695 return Feature == "aarch64" || 5696 Feature == "arm64" || 5697 Feature == "arm" || 5698 (Feature == "neon" && FPU == NeonMode); 5699 } 5700 5701 bool handleTargetFeatures(std::vector<std::string> &Features, 5702 DiagnosticsEngine &Diags) override { 5703 FPU = FPUMode; 5704 CRC = 0; 5705 Crypto = 0; 5706 Unaligned = 1; 5707 V8_1A = 0; 5708 5709 for (const auto &Feature : Features) { 5710 if (Feature == "+neon") 5711 FPU = NeonMode; 5712 if (Feature == "+crc") 5713 CRC = 1; 5714 if (Feature == "+crypto") 5715 Crypto = 1; 5716 if (Feature == "+strict-align") 5717 Unaligned = 0; 5718 if (Feature == "+v8.1a") 5719 V8_1A = 1; 5720 } 5721 5722 setDataLayout(); 5723 5724 return true; 5725 } 5726 5727 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5728 switch (CC) { 5729 case CC_C: 5730 case CC_Swift: 5731 case CC_PreserveMost: 5732 case CC_PreserveAll: 5733 return CCCR_OK; 5734 default: 5735 return CCCR_Warning; 5736 } 5737 } 5738 5739 bool isCLZForZeroUndef() const override { return false; } 5740 5741 BuiltinVaListKind getBuiltinVaListKind() const override { 5742 return TargetInfo::AArch64ABIBuiltinVaList; 5743 } 5744 5745 ArrayRef<const char *> getGCCRegNames() const override; 5746 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5747 5748 bool validateAsmConstraint(const char *&Name, 5749 TargetInfo::ConstraintInfo &Info) const override { 5750 switch (*Name) { 5751 default: 5752 return false; 5753 case 'w': // Floating point and SIMD registers (V0-V31) 5754 Info.setAllowsRegister(); 5755 return true; 5756 case 'I': // Constant that can be used with an ADD instruction 5757 case 'J': // Constant that can be used with a SUB instruction 5758 case 'K': // Constant that can be used with a 32-bit logical instruction 5759 case 'L': // Constant that can be used with a 64-bit logical instruction 5760 case 'M': // Constant that can be used as a 32-bit MOV immediate 5761 case 'N': // Constant that can be used as a 64-bit MOV immediate 5762 case 'Y': // Floating point constant zero 5763 case 'Z': // Integer constant zero 5764 return true; 5765 case 'Q': // A memory reference with base register and no offset 5766 Info.setAllowsMemory(); 5767 return true; 5768 case 'S': // A symbolic address 5769 Info.setAllowsRegister(); 5770 return true; 5771 case 'U': 5772 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5773 // Utf: A memory address suitable for ldp/stp in TF mode. 5774 // Usa: An absolute symbolic address. 5775 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5776 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5777 case 'z': // Zero register, wzr or xzr 5778 Info.setAllowsRegister(); 5779 return true; 5780 case 'x': // Floating point and SIMD registers (V0-V15) 5781 Info.setAllowsRegister(); 5782 return true; 5783 } 5784 return false; 5785 } 5786 5787 bool 5788 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5789 std::string &SuggestedModifier) const override { 5790 // Strip off constraint modifiers. 5791 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5792 Constraint = Constraint.substr(1); 5793 5794 switch (Constraint[0]) { 5795 default: 5796 return true; 5797 case 'z': 5798 case 'r': { 5799 switch (Modifier) { 5800 case 'x': 5801 case 'w': 5802 // For now assume that the person knows what they're 5803 // doing with the modifier. 5804 return true; 5805 default: 5806 // By default an 'r' constraint will be in the 'x' 5807 // registers. 5808 if (Size == 64) 5809 return true; 5810 5811 SuggestedModifier = "w"; 5812 return false; 5813 } 5814 } 5815 } 5816 } 5817 5818 const char *getClobbers() const override { return ""; } 5819 5820 int getEHDataRegisterNumber(unsigned RegNo) const override { 5821 if (RegNo == 0) 5822 return 0; 5823 if (RegNo == 1) 5824 return 1; 5825 return -1; 5826 } 5827 }; 5828 5829 const char *const AArch64TargetInfo::GCCRegNames[] = { 5830 // 32-bit Integer registers 5831 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5832 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5833 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5834 5835 // 64-bit Integer registers 5836 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5837 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5838 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5839 5840 // 32-bit floating point regsisters 5841 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5842 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5843 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5844 5845 // 64-bit floating point regsisters 5846 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5847 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5848 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5849 5850 // Vector registers 5851 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5852 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5853 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5854 }; 5855 5856 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 5857 return llvm::makeArrayRef(GCCRegNames); 5858 } 5859 5860 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5861 { { "w31" }, "wsp" }, 5862 { { "x29" }, "fp" }, 5863 { { "x30" }, "lr" }, 5864 { { "x31" }, "sp" }, 5865 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5866 // don't want to substitute one of these for a different-sized one. 5867 }; 5868 5869 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 5870 return llvm::makeArrayRef(GCCRegAliases); 5871 } 5872 5873 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5874 #define BUILTIN(ID, TYPE, ATTRS) \ 5875 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5876 #include "clang/Basic/BuiltinsNEON.def" 5877 5878 #define BUILTIN(ID, TYPE, ATTRS) \ 5879 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5880 #include "clang/Basic/BuiltinsAArch64.def" 5881 }; 5882 5883 class AArch64leTargetInfo : public AArch64TargetInfo { 5884 void setDataLayout() override { 5885 if (getTriple().isOSBinFormatMachO()) 5886 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 5887 else 5888 resetDataLayout("e-m:e-i64:64-i128:128-n32:64-S128"); 5889 } 5890 5891 public: 5892 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5893 : AArch64TargetInfo(Triple, Opts) { 5894 BigEndian = false; 5895 } 5896 void getTargetDefines(const LangOptions &Opts, 5897 MacroBuilder &Builder) const override { 5898 Builder.defineMacro("__AARCH64EL__"); 5899 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5900 } 5901 }; 5902 5903 class AArch64beTargetInfo : public AArch64TargetInfo { 5904 void setDataLayout() override { 5905 assert(!getTriple().isOSBinFormatMachO()); 5906 resetDataLayout("E-m:e-i64:64-i128:128-n32:64-S128"); 5907 } 5908 5909 public: 5910 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5911 : AArch64TargetInfo(Triple, Opts) {} 5912 void getTargetDefines(const LangOptions &Opts, 5913 MacroBuilder &Builder) const override { 5914 Builder.defineMacro("__AARCH64EB__"); 5915 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5916 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5917 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5918 } 5919 }; 5920 5921 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5922 protected: 5923 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5924 MacroBuilder &Builder) const override { 5925 Builder.defineMacro("__AARCH64_SIMD__"); 5926 Builder.defineMacro("__ARM64_ARCH_8__"); 5927 Builder.defineMacro("__ARM_NEON__"); 5928 Builder.defineMacro("__LITTLE_ENDIAN__"); 5929 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5930 Builder.defineMacro("__arm64", "1"); 5931 Builder.defineMacro("__arm64__", "1"); 5932 5933 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5934 } 5935 5936 public: 5937 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5938 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 5939 Int64Type = SignedLongLong; 5940 WCharType = SignedInt; 5941 UseSignedCharForObjCBool = false; 5942 5943 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5944 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5945 5946 TheCXXABI.set(TargetCXXABI::iOS64); 5947 } 5948 5949 BuiltinVaListKind getBuiltinVaListKind() const override { 5950 return TargetInfo::CharPtrBuiltinVaList; 5951 } 5952 }; 5953 5954 // Hexagon abstract base class 5955 class HexagonTargetInfo : public TargetInfo { 5956 static const Builtin::Info BuiltinInfo[]; 5957 static const char * const GCCRegNames[]; 5958 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5959 std::string CPU; 5960 bool HasHVX, HasHVXDouble; 5961 5962 public: 5963 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 5964 : TargetInfo(Triple) { 5965 BigEndian = false; 5966 // Specify the vector alignment explicitly. For v512x1, the calculated 5967 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 5968 // the required minimum of 64 bytes. 5969 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 5970 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 5971 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 5972 SizeType = UnsignedInt; 5973 PtrDiffType = SignedInt; 5974 IntPtrType = SignedInt; 5975 5976 // {} in inline assembly are packet specifiers, not assembly variant 5977 // specifiers. 5978 NoAsmVariants = true; 5979 5980 LargeArrayMinWidth = 64; 5981 LargeArrayAlign = 64; 5982 UseBitFieldTypeAlignment = true; 5983 ZeroLengthBitfieldBoundary = 32; 5984 HasHVX = HasHVXDouble = false; 5985 } 5986 5987 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5988 return llvm::makeArrayRef(BuiltinInfo, 5989 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 5990 } 5991 5992 bool validateAsmConstraint(const char *&Name, 5993 TargetInfo::ConstraintInfo &Info) const override { 5994 return true; 5995 } 5996 5997 void getTargetDefines(const LangOptions &Opts, 5998 MacroBuilder &Builder) const override; 5999 6000 bool isCLZForZeroUndef() const override { return false; } 6001 6002 bool hasFeature(StringRef Feature) const override { 6003 return llvm::StringSwitch<bool>(Feature) 6004 .Case("hexagon", true) 6005 .Case("hvx", HasHVX) 6006 .Case("hvx-double", HasHVXDouble) 6007 .Default(false); 6008 } 6009 6010 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6011 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6012 const override; 6013 6014 bool handleTargetFeatures(std::vector<std::string> &Features, 6015 DiagnosticsEngine &Diags) override; 6016 6017 BuiltinVaListKind getBuiltinVaListKind() const override { 6018 return TargetInfo::CharPtrBuiltinVaList; 6019 } 6020 ArrayRef<const char *> getGCCRegNames() const override; 6021 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6022 const char *getClobbers() const override { 6023 return ""; 6024 } 6025 6026 static const char *getHexagonCPUSuffix(StringRef Name) { 6027 return llvm::StringSwitch<const char*>(Name) 6028 .Case("hexagonv4", "4") 6029 .Case("hexagonv5", "5") 6030 .Case("hexagonv55", "55") 6031 .Case("hexagonv60", "60") 6032 .Default(nullptr); 6033 } 6034 6035 bool setCPU(const std::string &Name) override { 6036 if (!getHexagonCPUSuffix(Name)) 6037 return false; 6038 CPU = Name; 6039 return true; 6040 } 6041 6042 int getEHDataRegisterNumber(unsigned RegNo) const override { 6043 return RegNo < 2 ? RegNo : -1; 6044 } 6045 }; 6046 6047 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6048 MacroBuilder &Builder) const { 6049 Builder.defineMacro("__qdsp6__", "1"); 6050 Builder.defineMacro("__hexagon__", "1"); 6051 6052 if (CPU == "hexagonv4") { 6053 Builder.defineMacro("__HEXAGON_V4__"); 6054 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6055 if (Opts.HexagonQdsp6Compat) { 6056 Builder.defineMacro("__QDSP6_V4__"); 6057 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6058 } 6059 } else if (CPU == "hexagonv5") { 6060 Builder.defineMacro("__HEXAGON_V5__"); 6061 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6062 if(Opts.HexagonQdsp6Compat) { 6063 Builder.defineMacro("__QDSP6_V5__"); 6064 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6065 } 6066 } else if (CPU == "hexagonv55") { 6067 Builder.defineMacro("__HEXAGON_V55__"); 6068 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6069 Builder.defineMacro("__QDSP6_V55__"); 6070 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6071 } else if (CPU == "hexagonv60") { 6072 Builder.defineMacro("__HEXAGON_V60__"); 6073 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6074 Builder.defineMacro("__QDSP6_V60__"); 6075 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6076 } 6077 6078 if (hasFeature("hvx")) { 6079 Builder.defineMacro("__HVX__"); 6080 if (hasFeature("hvx-double")) 6081 Builder.defineMacro("__HVXDBL__"); 6082 } 6083 } 6084 6085 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6086 DiagnosticsEngine &Diags) { 6087 for (auto &F : Features) { 6088 if (F == "+hvx") 6089 HasHVX = true; 6090 else if (F == "-hvx") 6091 HasHVX = HasHVXDouble = false; 6092 else if (F == "+hvx-double") 6093 HasHVX = HasHVXDouble = true; 6094 else if (F == "-hvx-double") 6095 HasHVXDouble = false; 6096 } 6097 return true; 6098 } 6099 6100 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6101 DiagnosticsEngine &Diags, StringRef CPU, 6102 const std::vector<std::string> &FeaturesVec) const { 6103 // Default for v60: -hvx, -hvx-double. 6104 Features["hvx"] = false; 6105 Features["hvx-double"] = false; 6106 6107 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6108 } 6109 6110 6111 const char *const HexagonTargetInfo::GCCRegNames[] = { 6112 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6113 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6114 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6115 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6116 "p0", "p1", "p2", "p3", 6117 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6118 }; 6119 6120 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6121 return llvm::makeArrayRef(GCCRegNames); 6122 } 6123 6124 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6125 { { "sp" }, "r29" }, 6126 { { "fp" }, "r30" }, 6127 { { "lr" }, "r31" }, 6128 }; 6129 6130 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6131 return llvm::makeArrayRef(GCCRegAliases); 6132 } 6133 6134 6135 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6136 #define BUILTIN(ID, TYPE, ATTRS) \ 6137 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6138 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6139 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6140 #include "clang/Basic/BuiltinsHexagon.def" 6141 }; 6142 6143 class LanaiTargetInfo : public TargetInfo { 6144 // Class for Lanai (32-bit). 6145 // The CPU profiles supported by the Lanai backend 6146 enum CPUKind { 6147 CK_NONE, 6148 CK_V11, 6149 } CPU; 6150 6151 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6152 static const char *const GCCRegNames[]; 6153 6154 public: 6155 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6156 : TargetInfo(Triple) { 6157 // Description string has to be kept in sync with backend. 6158 resetDataLayout("E" // Big endian 6159 "-m:e" // ELF name manging 6160 "-p:32:32" // 32 bit pointers, 32 bit aligned 6161 "-i64:64" // 64 bit integers, 64 bit aligned 6162 "-a:0:32" // 32 bit alignment of objects of aggregate type 6163 "-n32" // 32 bit native integer width 6164 "-S64" // 64 bit natural stack alignment 6165 ); 6166 6167 // Setting RegParmMax equal to what mregparm was set to in the old 6168 // toolchain 6169 RegParmMax = 4; 6170 6171 // Set the default CPU to V11 6172 CPU = CK_V11; 6173 6174 // Temporary approach to make everything at least word-aligned and allow for 6175 // safely casting between pointers with different alignment requirements. 6176 // TODO: Remove this when there are no more cast align warnings on the 6177 // firmware. 6178 MinGlobalAlign = 32; 6179 } 6180 6181 void getTargetDefines(const LangOptions &Opts, 6182 MacroBuilder &Builder) const override { 6183 // Define __lanai__ when building for target lanai. 6184 Builder.defineMacro("__lanai__"); 6185 6186 // Set define for the CPU specified. 6187 switch (CPU) { 6188 case CK_V11: 6189 Builder.defineMacro("__LANAI_V11__"); 6190 break; 6191 case CK_NONE: 6192 llvm_unreachable("Unhandled target CPU"); 6193 } 6194 } 6195 6196 bool setCPU(const std::string &Name) override { 6197 CPU = llvm::StringSwitch<CPUKind>(Name) 6198 .Case("v11", CK_V11) 6199 .Default(CK_NONE); 6200 6201 return CPU != CK_NONE; 6202 } 6203 6204 bool hasFeature(StringRef Feature) const override { 6205 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6206 } 6207 6208 ArrayRef<const char *> getGCCRegNames() const override; 6209 6210 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6211 6212 BuiltinVaListKind getBuiltinVaListKind() const override { 6213 return TargetInfo::VoidPtrBuiltinVaList; 6214 } 6215 6216 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6217 6218 bool validateAsmConstraint(const char *&Name, 6219 TargetInfo::ConstraintInfo &info) const override { 6220 return false; 6221 } 6222 6223 const char *getClobbers() const override { return ""; } 6224 }; 6225 6226 const char *const LanaiTargetInfo::GCCRegNames[] = { 6227 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6228 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6229 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6230 6231 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6232 return llvm::makeArrayRef(GCCRegNames); 6233 } 6234 6235 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6236 {{"pc"}, "r2"}, 6237 {{"sp"}, "r4"}, 6238 {{"fp"}, "r5"}, 6239 {{"rv"}, "r8"}, 6240 {{"rr1"}, "r10"}, 6241 {{"rr2"}, "r11"}, 6242 {{"rca"}, "r15"}, 6243 }; 6244 6245 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6246 return llvm::makeArrayRef(GCCRegAliases); 6247 } 6248 6249 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6250 class SparcTargetInfo : public TargetInfo { 6251 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6252 static const char * const GCCRegNames[]; 6253 bool SoftFloat; 6254 public: 6255 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6256 : TargetInfo(Triple), SoftFloat(false) {} 6257 6258 int getEHDataRegisterNumber(unsigned RegNo) const override { 6259 if (RegNo == 0) return 24; 6260 if (RegNo == 1) return 25; 6261 return -1; 6262 } 6263 6264 bool handleTargetFeatures(std::vector<std::string> &Features, 6265 DiagnosticsEngine &Diags) override { 6266 // The backend doesn't actually handle soft float yet, but in case someone 6267 // is using the support for the front end continue to support it. 6268 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6269 if (Feature != Features.end()) { 6270 SoftFloat = true; 6271 Features.erase(Feature); 6272 } 6273 return true; 6274 } 6275 void getTargetDefines(const LangOptions &Opts, 6276 MacroBuilder &Builder) const override { 6277 DefineStd(Builder, "sparc", Opts); 6278 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6279 6280 if (SoftFloat) 6281 Builder.defineMacro("SOFT_FLOAT", "1"); 6282 } 6283 6284 bool hasFeature(StringRef Feature) const override { 6285 return llvm::StringSwitch<bool>(Feature) 6286 .Case("softfloat", SoftFloat) 6287 .Case("sparc", true) 6288 .Default(false); 6289 } 6290 6291 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6292 // FIXME: Implement! 6293 return None; 6294 } 6295 BuiltinVaListKind getBuiltinVaListKind() const override { 6296 return TargetInfo::VoidPtrBuiltinVaList; 6297 } 6298 ArrayRef<const char *> getGCCRegNames() const override; 6299 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6300 bool validateAsmConstraint(const char *&Name, 6301 TargetInfo::ConstraintInfo &info) const override { 6302 // FIXME: Implement! 6303 switch (*Name) { 6304 case 'I': // Signed 13-bit constant 6305 case 'J': // Zero 6306 case 'K': // 32-bit constant with the low 12 bits clear 6307 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6308 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6309 case 'N': // Same as 'K' but zext (required for SIMode) 6310 case 'O': // The constant 4096 6311 return true; 6312 } 6313 return false; 6314 } 6315 const char *getClobbers() const override { 6316 // FIXME: Implement! 6317 return ""; 6318 } 6319 6320 // No Sparc V7 for now, the backend doesn't support it anyway. 6321 enum CPUKind { 6322 CK_GENERIC, 6323 CK_V8, 6324 CK_SUPERSPARC, 6325 CK_SPARCLITE, 6326 CK_F934, 6327 CK_HYPERSPARC, 6328 CK_SPARCLITE86X, 6329 CK_SPARCLET, 6330 CK_TSC701, 6331 CK_V9, 6332 CK_ULTRASPARC, 6333 CK_ULTRASPARC3, 6334 CK_NIAGARA, 6335 CK_NIAGARA2, 6336 CK_NIAGARA3, 6337 CK_NIAGARA4, 6338 CK_MYRIAD2_1, 6339 CK_MYRIAD2_2 6340 } CPU = CK_GENERIC; 6341 6342 enum CPUGeneration { 6343 CG_V8, 6344 CG_V9, 6345 }; 6346 6347 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6348 switch (Kind) { 6349 case CK_GENERIC: 6350 case CK_V8: 6351 case CK_SUPERSPARC: 6352 case CK_SPARCLITE: 6353 case CK_F934: 6354 case CK_HYPERSPARC: 6355 case CK_SPARCLITE86X: 6356 case CK_SPARCLET: 6357 case CK_TSC701: 6358 case CK_MYRIAD2_1: 6359 case CK_MYRIAD2_2: 6360 return CG_V8; 6361 case CK_V9: 6362 case CK_ULTRASPARC: 6363 case CK_ULTRASPARC3: 6364 case CK_NIAGARA: 6365 case CK_NIAGARA2: 6366 case CK_NIAGARA3: 6367 case CK_NIAGARA4: 6368 return CG_V9; 6369 } 6370 llvm_unreachable("Unexpected CPU kind"); 6371 } 6372 6373 CPUKind getCPUKind(StringRef Name) const { 6374 return llvm::StringSwitch<CPUKind>(Name) 6375 .Case("v8", CK_V8) 6376 .Case("supersparc", CK_SUPERSPARC) 6377 .Case("sparclite", CK_SPARCLITE) 6378 .Case("f934", CK_F934) 6379 .Case("hypersparc", CK_HYPERSPARC) 6380 .Case("sparclite86x", CK_SPARCLITE86X) 6381 .Case("sparclet", CK_SPARCLET) 6382 .Case("tsc701", CK_TSC701) 6383 .Case("v9", CK_V9) 6384 .Case("ultrasparc", CK_ULTRASPARC) 6385 .Case("ultrasparc3", CK_ULTRASPARC3) 6386 .Case("niagara", CK_NIAGARA) 6387 .Case("niagara2", CK_NIAGARA2) 6388 .Case("niagara3", CK_NIAGARA3) 6389 .Case("niagara4", CK_NIAGARA4) 6390 .Case("myriad2", CK_MYRIAD2_1) 6391 .Case("myriad2.1", CK_MYRIAD2_1) 6392 .Case("myriad2.2", CK_MYRIAD2_2) 6393 .Default(CK_GENERIC); 6394 } 6395 6396 bool setCPU(const std::string &Name) override { 6397 CPU = getCPUKind(Name); 6398 return CPU != CK_GENERIC; 6399 } 6400 }; 6401 6402 const char * const SparcTargetInfo::GCCRegNames[] = { 6403 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6404 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6405 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6406 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6407 }; 6408 6409 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6410 return llvm::makeArrayRef(GCCRegNames); 6411 } 6412 6413 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6414 { { "g0" }, "r0" }, 6415 { { "g1" }, "r1" }, 6416 { { "g2" }, "r2" }, 6417 { { "g3" }, "r3" }, 6418 { { "g4" }, "r4" }, 6419 { { "g5" }, "r5" }, 6420 { { "g6" }, "r6" }, 6421 { { "g7" }, "r7" }, 6422 { { "o0" }, "r8" }, 6423 { { "o1" }, "r9" }, 6424 { { "o2" }, "r10" }, 6425 { { "o3" }, "r11" }, 6426 { { "o4" }, "r12" }, 6427 { { "o5" }, "r13" }, 6428 { { "o6", "sp" }, "r14" }, 6429 { { "o7" }, "r15" }, 6430 { { "l0" }, "r16" }, 6431 { { "l1" }, "r17" }, 6432 { { "l2" }, "r18" }, 6433 { { "l3" }, "r19" }, 6434 { { "l4" }, "r20" }, 6435 { { "l5" }, "r21" }, 6436 { { "l6" }, "r22" }, 6437 { { "l7" }, "r23" }, 6438 { { "i0" }, "r24" }, 6439 { { "i1" }, "r25" }, 6440 { { "i2" }, "r26" }, 6441 { { "i3" }, "r27" }, 6442 { { "i4" }, "r28" }, 6443 { { "i5" }, "r29" }, 6444 { { "i6", "fp" }, "r30" }, 6445 { { "i7" }, "r31" }, 6446 }; 6447 6448 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6449 return llvm::makeArrayRef(GCCRegAliases); 6450 } 6451 6452 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6453 class SparcV8TargetInfo : public SparcTargetInfo { 6454 public: 6455 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6456 : SparcTargetInfo(Triple, Opts) { 6457 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6458 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6459 switch (getTriple().getOS()) { 6460 default: 6461 SizeType = UnsignedInt; 6462 IntPtrType = SignedInt; 6463 PtrDiffType = SignedInt; 6464 break; 6465 case llvm::Triple::NetBSD: 6466 case llvm::Triple::OpenBSD: 6467 SizeType = UnsignedLong; 6468 IntPtrType = SignedLong; 6469 PtrDiffType = SignedLong; 6470 break; 6471 } 6472 } 6473 6474 void getTargetDefines(const LangOptions &Opts, 6475 MacroBuilder &Builder) const override { 6476 SparcTargetInfo::getTargetDefines(Opts, Builder); 6477 switch (getCPUGeneration(CPU)) { 6478 case CG_V8: 6479 Builder.defineMacro("__sparcv8"); 6480 if (getTriple().getOS() != llvm::Triple::Solaris) 6481 Builder.defineMacro("__sparcv8__"); 6482 break; 6483 case CG_V9: 6484 Builder.defineMacro("__sparcv9"); 6485 if (getTriple().getOS() != llvm::Triple::Solaris) { 6486 Builder.defineMacro("__sparcv9__"); 6487 Builder.defineMacro("__sparc_v9__"); 6488 } 6489 break; 6490 } 6491 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6492 switch (CPU) { 6493 case CK_MYRIAD2_1: 6494 Builder.defineMacro("__myriad2", "1"); 6495 Builder.defineMacro("__myriad2__", "1"); 6496 break; 6497 case CK_MYRIAD2_2: 6498 Builder.defineMacro("__myriad2", "2"); 6499 Builder.defineMacro("__myriad2__", "2"); 6500 break; 6501 default: 6502 break; 6503 } 6504 } 6505 } 6506 6507 bool hasSjLjLowering() const override { 6508 return true; 6509 } 6510 }; 6511 6512 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6513 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6514 public: 6515 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6516 : SparcV8TargetInfo(Triple, Opts) { 6517 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6518 BigEndian = false; 6519 } 6520 }; 6521 6522 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6523 class SparcV9TargetInfo : public SparcTargetInfo { 6524 public: 6525 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6526 : SparcTargetInfo(Triple, Opts) { 6527 // FIXME: Support Sparc quad-precision long double? 6528 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6529 // This is an LP64 platform. 6530 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6531 6532 // OpenBSD uses long long for int64_t and intmax_t. 6533 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6534 IntMaxType = SignedLongLong; 6535 else 6536 IntMaxType = SignedLong; 6537 Int64Type = IntMaxType; 6538 6539 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6540 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6541 LongDoubleWidth = 128; 6542 LongDoubleAlign = 128; 6543 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6544 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6545 } 6546 6547 void getTargetDefines(const LangOptions &Opts, 6548 MacroBuilder &Builder) const override { 6549 SparcTargetInfo::getTargetDefines(Opts, Builder); 6550 Builder.defineMacro("__sparcv9"); 6551 Builder.defineMacro("__arch64__"); 6552 // Solaris doesn't need these variants, but the BSDs do. 6553 if (getTriple().getOS() != llvm::Triple::Solaris) { 6554 Builder.defineMacro("__sparc64__"); 6555 Builder.defineMacro("__sparc_v9__"); 6556 Builder.defineMacro("__sparcv9__"); 6557 } 6558 } 6559 6560 bool setCPU(const std::string &Name) override { 6561 if (!SparcTargetInfo::setCPU(Name)) 6562 return false; 6563 return getCPUGeneration(CPU) == CG_V9; 6564 } 6565 }; 6566 6567 class SystemZTargetInfo : public TargetInfo { 6568 static const Builtin::Info BuiltinInfo[]; 6569 static const char *const GCCRegNames[]; 6570 std::string CPU; 6571 bool HasTransactionalExecution; 6572 bool HasVector; 6573 6574 public: 6575 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6576 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6577 HasVector(false) { 6578 IntMaxType = SignedLong; 6579 Int64Type = SignedLong; 6580 TLSSupported = true; 6581 IntWidth = IntAlign = 32; 6582 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6583 PointerWidth = PointerAlign = 64; 6584 LongDoubleWidth = 128; 6585 LongDoubleAlign = 64; 6586 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6587 DefaultAlignForAttributeAligned = 64; 6588 MinGlobalAlign = 16; 6589 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 6590 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6591 } 6592 void getTargetDefines(const LangOptions &Opts, 6593 MacroBuilder &Builder) const override { 6594 Builder.defineMacro("__s390__"); 6595 Builder.defineMacro("__s390x__"); 6596 Builder.defineMacro("__zarch__"); 6597 Builder.defineMacro("__LONG_DOUBLE_128__"); 6598 6599 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6600 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6601 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6602 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6603 6604 if (HasTransactionalExecution) 6605 Builder.defineMacro("__HTM__"); 6606 if (Opts.ZVector) 6607 Builder.defineMacro("__VEC__", "10301"); 6608 } 6609 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6610 return llvm::makeArrayRef(BuiltinInfo, 6611 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6612 } 6613 6614 ArrayRef<const char *> getGCCRegNames() const override; 6615 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6616 // No aliases. 6617 return None; 6618 } 6619 bool validateAsmConstraint(const char *&Name, 6620 TargetInfo::ConstraintInfo &info) const override; 6621 const char *getClobbers() const override { 6622 // FIXME: Is this really right? 6623 return ""; 6624 } 6625 BuiltinVaListKind getBuiltinVaListKind() const override { 6626 return TargetInfo::SystemZBuiltinVaList; 6627 } 6628 bool setCPU(const std::string &Name) override { 6629 CPU = Name; 6630 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6631 .Case("z10", true) 6632 .Case("z196", true) 6633 .Case("zEC12", true) 6634 .Case("z13", true) 6635 .Default(false); 6636 6637 return CPUKnown; 6638 } 6639 bool 6640 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6641 StringRef CPU, 6642 const std::vector<std::string> &FeaturesVec) const override { 6643 if (CPU == "zEC12") 6644 Features["transactional-execution"] = true; 6645 if (CPU == "z13") { 6646 Features["transactional-execution"] = true; 6647 Features["vector"] = true; 6648 } 6649 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6650 } 6651 6652 bool handleTargetFeatures(std::vector<std::string> &Features, 6653 DiagnosticsEngine &Diags) override { 6654 HasTransactionalExecution = false; 6655 for (const auto &Feature : Features) { 6656 if (Feature == "+transactional-execution") 6657 HasTransactionalExecution = true; 6658 else if (Feature == "+vector") 6659 HasVector = true; 6660 } 6661 // If we use the vector ABI, vector types are 64-bit aligned. 6662 if (HasVector) { 6663 MaxVectorAlign = 64; 6664 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6665 "-v128:64-a:8:16-n32:64"); 6666 } 6667 return true; 6668 } 6669 6670 bool hasFeature(StringRef Feature) const override { 6671 return llvm::StringSwitch<bool>(Feature) 6672 .Case("systemz", true) 6673 .Case("htm", HasTransactionalExecution) 6674 .Case("vx", HasVector) 6675 .Default(false); 6676 } 6677 6678 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6679 switch (CC) { 6680 case CC_C: 6681 case CC_Swift: 6682 return CCCR_OK; 6683 default: 6684 return CCCR_Warning; 6685 } 6686 } 6687 6688 StringRef getABI() const override { 6689 if (HasVector) 6690 return "vector"; 6691 return ""; 6692 } 6693 6694 bool useFloat128ManglingForLongDouble() const override { 6695 return true; 6696 } 6697 }; 6698 6699 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6700 #define BUILTIN(ID, TYPE, ATTRS) \ 6701 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6702 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 6703 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 6704 #include "clang/Basic/BuiltinsSystemZ.def" 6705 }; 6706 6707 const char *const SystemZTargetInfo::GCCRegNames[] = { 6708 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6709 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6710 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6711 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6712 }; 6713 6714 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6715 return llvm::makeArrayRef(GCCRegNames); 6716 } 6717 6718 bool SystemZTargetInfo:: 6719 validateAsmConstraint(const char *&Name, 6720 TargetInfo::ConstraintInfo &Info) const { 6721 switch (*Name) { 6722 default: 6723 return false; 6724 6725 case 'a': // Address register 6726 case 'd': // Data register (equivalent to 'r') 6727 case 'f': // Floating-point register 6728 Info.setAllowsRegister(); 6729 return true; 6730 6731 case 'I': // Unsigned 8-bit constant 6732 case 'J': // Unsigned 12-bit constant 6733 case 'K': // Signed 16-bit constant 6734 case 'L': // Signed 20-bit displacement (on all targets we support) 6735 case 'M': // 0x7fffffff 6736 return true; 6737 6738 case 'Q': // Memory with base and unsigned 12-bit displacement 6739 case 'R': // Likewise, plus an index 6740 case 'S': // Memory with base and signed 20-bit displacement 6741 case 'T': // Likewise, plus an index 6742 Info.setAllowsMemory(); 6743 return true; 6744 } 6745 } 6746 6747 class MSP430TargetInfo : public TargetInfo { 6748 static const char *const GCCRegNames[]; 6749 6750 public: 6751 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6752 : TargetInfo(Triple) { 6753 BigEndian = false; 6754 TLSSupported = false; 6755 IntWidth = 16; 6756 IntAlign = 16; 6757 LongWidth = 32; 6758 LongLongWidth = 64; 6759 LongAlign = LongLongAlign = 16; 6760 PointerWidth = 16; 6761 PointerAlign = 16; 6762 SuitableAlign = 16; 6763 SizeType = UnsignedInt; 6764 IntMaxType = SignedLongLong; 6765 IntPtrType = SignedInt; 6766 PtrDiffType = SignedInt; 6767 SigAtomicType = SignedLong; 6768 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 6769 } 6770 void getTargetDefines(const LangOptions &Opts, 6771 MacroBuilder &Builder) const override { 6772 Builder.defineMacro("MSP430"); 6773 Builder.defineMacro("__MSP430__"); 6774 // FIXME: defines for different 'flavours' of MCU 6775 } 6776 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6777 // FIXME: Implement. 6778 return None; 6779 } 6780 bool hasFeature(StringRef Feature) const override { 6781 return Feature == "msp430"; 6782 } 6783 ArrayRef<const char *> getGCCRegNames() const override; 6784 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6785 // No aliases. 6786 return None; 6787 } 6788 bool validateAsmConstraint(const char *&Name, 6789 TargetInfo::ConstraintInfo &info) const override { 6790 // FIXME: implement 6791 switch (*Name) { 6792 case 'K': // the constant 1 6793 case 'L': // constant -1^20 .. 1^19 6794 case 'M': // constant 1-4: 6795 return true; 6796 } 6797 // No target constraints for now. 6798 return false; 6799 } 6800 const char *getClobbers() const override { 6801 // FIXME: Is this really right? 6802 return ""; 6803 } 6804 BuiltinVaListKind getBuiltinVaListKind() const override { 6805 // FIXME: implement 6806 return TargetInfo::CharPtrBuiltinVaList; 6807 } 6808 }; 6809 6810 const char *const MSP430TargetInfo::GCCRegNames[] = { 6811 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6812 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6813 6814 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 6815 return llvm::makeArrayRef(GCCRegNames); 6816 } 6817 6818 // LLVM and Clang cannot be used directly to output native binaries for 6819 // target, but is used to compile C code to llvm bitcode with correct 6820 // type and alignment information. 6821 // 6822 // TCE uses the llvm bitcode as input and uses it for generating customized 6823 // target processor and program binary. TCE co-design environment is 6824 // publicly available in http://tce.cs.tut.fi 6825 6826 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6827 3, // opencl_global 6828 4, // opencl_local 6829 5, // opencl_constant 6830 // FIXME: generic has to be added to the target 6831 0, // opencl_generic 6832 0, // cuda_device 6833 0, // cuda_constant 6834 0 // cuda_shared 6835 }; 6836 6837 class TCETargetInfo : public TargetInfo { 6838 public: 6839 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6840 : TargetInfo(Triple) { 6841 TLSSupported = false; 6842 IntWidth = 32; 6843 LongWidth = LongLongWidth = 32; 6844 PointerWidth = 32; 6845 IntAlign = 32; 6846 LongAlign = LongLongAlign = 32; 6847 PointerAlign = 32; 6848 SuitableAlign = 32; 6849 SizeType = UnsignedInt; 6850 IntMaxType = SignedLong; 6851 IntPtrType = SignedInt; 6852 PtrDiffType = SignedInt; 6853 FloatWidth = 32; 6854 FloatAlign = 32; 6855 DoubleWidth = 32; 6856 DoubleAlign = 32; 6857 LongDoubleWidth = 32; 6858 LongDoubleAlign = 32; 6859 FloatFormat = &llvm::APFloat::IEEEsingle; 6860 DoubleFormat = &llvm::APFloat::IEEEsingle; 6861 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6862 resetDataLayout("E-p:32:32-i8:8:32-i16:16:32-i64:32" 6863 "-f64:32-v64:32-v128:32-a:0:32-n32"); 6864 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6865 UseAddrSpaceMapMangling = true; 6866 } 6867 6868 void getTargetDefines(const LangOptions &Opts, 6869 MacroBuilder &Builder) const override { 6870 DefineStd(Builder, "tce", Opts); 6871 Builder.defineMacro("__TCE__"); 6872 Builder.defineMacro("__TCE_V1__"); 6873 } 6874 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 6875 6876 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6877 const char *getClobbers() const override { return ""; } 6878 BuiltinVaListKind getBuiltinVaListKind() const override { 6879 return TargetInfo::VoidPtrBuiltinVaList; 6880 } 6881 ArrayRef<const char *> getGCCRegNames() const override { return None; } 6882 bool validateAsmConstraint(const char *&Name, 6883 TargetInfo::ConstraintInfo &info) const override { 6884 return true; 6885 } 6886 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6887 return None; 6888 } 6889 }; 6890 6891 class BPFTargetInfo : public TargetInfo { 6892 public: 6893 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6894 : TargetInfo(Triple) { 6895 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6896 SizeType = UnsignedLong; 6897 PtrDiffType = SignedLong; 6898 IntPtrType = SignedLong; 6899 IntMaxType = SignedLong; 6900 Int64Type = SignedLong; 6901 RegParmMax = 5; 6902 if (Triple.getArch() == llvm::Triple::bpfeb) { 6903 BigEndian = true; 6904 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 6905 } else { 6906 BigEndian = false; 6907 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 6908 } 6909 MaxAtomicPromoteWidth = 64; 6910 MaxAtomicInlineWidth = 64; 6911 TLSSupported = false; 6912 } 6913 void getTargetDefines(const LangOptions &Opts, 6914 MacroBuilder &Builder) const override { 6915 DefineStd(Builder, "bpf", Opts); 6916 Builder.defineMacro("__BPF__"); 6917 } 6918 bool hasFeature(StringRef Feature) const override { 6919 return Feature == "bpf"; 6920 } 6921 6922 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6923 const char *getClobbers() const override { 6924 return ""; 6925 } 6926 BuiltinVaListKind getBuiltinVaListKind() const override { 6927 return TargetInfo::VoidPtrBuiltinVaList; 6928 } 6929 ArrayRef<const char *> getGCCRegNames() const override { 6930 return None; 6931 } 6932 bool validateAsmConstraint(const char *&Name, 6933 TargetInfo::ConstraintInfo &info) const override { 6934 return true; 6935 } 6936 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6937 return None; 6938 } 6939 }; 6940 6941 class MipsTargetInfoBase : public TargetInfo { 6942 virtual void setDataLayout() = 0; 6943 6944 static const Builtin::Info BuiltinInfo[]; 6945 std::string CPU; 6946 bool IsMips16; 6947 bool IsMicromips; 6948 bool IsNan2008; 6949 bool IsSingleFloat; 6950 enum MipsFloatABI { 6951 HardFloat, SoftFloat 6952 } FloatABI; 6953 enum DspRevEnum { 6954 NoDSP, DSP1, DSP2 6955 } DspRev; 6956 bool HasMSA; 6957 6958 protected: 6959 bool HasFP64; 6960 std::string ABI; 6961 6962 public: 6963 MipsTargetInfoBase(const llvm::Triple &Triple, const TargetOptions &, 6964 const std::string &ABIStr, const std::string &CPUStr) 6965 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6966 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6967 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6968 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6969 } 6970 6971 bool isNaN2008Default() const { 6972 return CPU == "mips32r6" || CPU == "mips64r6"; 6973 } 6974 6975 bool isFP64Default() const { 6976 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6977 } 6978 6979 bool isNan2008() const override { 6980 return IsNan2008; 6981 } 6982 6983 StringRef getABI() const override { return ABI; } 6984 bool setCPU(const std::string &Name) override { 6985 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6986 getTriple().getArch() == llvm::Triple::mipsel; 6987 CPU = Name; 6988 return llvm::StringSwitch<bool>(Name) 6989 .Case("mips1", IsMips32) 6990 .Case("mips2", IsMips32) 6991 .Case("mips3", true) 6992 .Case("mips4", true) 6993 .Case("mips5", true) 6994 .Case("mips32", IsMips32) 6995 .Case("mips32r2", IsMips32) 6996 .Case("mips32r3", IsMips32) 6997 .Case("mips32r5", IsMips32) 6998 .Case("mips32r6", IsMips32) 6999 .Case("mips64", true) 7000 .Case("mips64r2", true) 7001 .Case("mips64r3", true) 7002 .Case("mips64r5", true) 7003 .Case("mips64r6", true) 7004 .Case("octeon", true) 7005 .Case("p5600", true) 7006 .Default(false); 7007 } 7008 const std::string& getCPU() const { return CPU; } 7009 bool 7010 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7011 StringRef CPU, 7012 const std::vector<std::string> &FeaturesVec) const override { 7013 if (CPU.empty()) 7014 CPU = getCPU(); 7015 if (CPU == "octeon") 7016 Features["mips64r2"] = Features["cnmips"] = true; 7017 else 7018 Features[CPU] = true; 7019 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7020 } 7021 7022 void getTargetDefines(const LangOptions &Opts, 7023 MacroBuilder &Builder) const override { 7024 Builder.defineMacro("__mips__"); 7025 Builder.defineMacro("_mips"); 7026 if (Opts.GNUMode) 7027 Builder.defineMacro("mips"); 7028 7029 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7030 7031 switch (FloatABI) { 7032 case HardFloat: 7033 Builder.defineMacro("__mips_hard_float", Twine(1)); 7034 break; 7035 case SoftFloat: 7036 Builder.defineMacro("__mips_soft_float", Twine(1)); 7037 break; 7038 } 7039 7040 if (IsSingleFloat) 7041 Builder.defineMacro("__mips_single_float", Twine(1)); 7042 7043 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7044 Builder.defineMacro("_MIPS_FPSET", 7045 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7046 7047 if (IsMips16) 7048 Builder.defineMacro("__mips16", Twine(1)); 7049 7050 if (IsMicromips) 7051 Builder.defineMacro("__mips_micromips", Twine(1)); 7052 7053 if (IsNan2008) 7054 Builder.defineMacro("__mips_nan2008", Twine(1)); 7055 7056 switch (DspRev) { 7057 default: 7058 break; 7059 case DSP1: 7060 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7061 Builder.defineMacro("__mips_dsp", Twine(1)); 7062 break; 7063 case DSP2: 7064 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7065 Builder.defineMacro("__mips_dspr2", Twine(1)); 7066 Builder.defineMacro("__mips_dsp", Twine(1)); 7067 break; 7068 } 7069 7070 if (HasMSA) 7071 Builder.defineMacro("__mips_msa", Twine(1)); 7072 7073 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7074 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7075 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7076 7077 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7078 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7079 7080 // These shouldn't be defined for MIPS-I but there's no need to check 7081 // for that since MIPS-I isn't supported. 7082 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7083 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7084 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7085 } 7086 7087 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7088 return llvm::makeArrayRef(BuiltinInfo, 7089 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7090 } 7091 bool hasFeature(StringRef Feature) const override { 7092 return llvm::StringSwitch<bool>(Feature) 7093 .Case("mips", true) 7094 .Case("fp64", HasFP64) 7095 .Default(false); 7096 } 7097 BuiltinVaListKind getBuiltinVaListKind() const override { 7098 return TargetInfo::VoidPtrBuiltinVaList; 7099 } 7100 ArrayRef<const char *> getGCCRegNames() const override { 7101 static const char *const GCCRegNames[] = { 7102 // CPU register names 7103 // Must match second column of GCCRegAliases 7104 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7105 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7106 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7107 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7108 // Floating point register names 7109 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7110 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7111 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7112 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7113 // Hi/lo and condition register names 7114 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7115 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7116 "$ac3hi","$ac3lo", 7117 // MSA register names 7118 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7119 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7120 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7121 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7122 // MSA control register names 7123 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7124 "$msarequest", "$msamap", "$msaunmap" 7125 }; 7126 return llvm::makeArrayRef(GCCRegNames); 7127 } 7128 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override = 0; 7129 bool validateAsmConstraint(const char *&Name, 7130 TargetInfo::ConstraintInfo &Info) const override { 7131 switch (*Name) { 7132 default: 7133 return false; 7134 case 'r': // CPU registers. 7135 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7136 case 'y': // Equivalent to "r", backward compatibility only. 7137 case 'f': // floating-point registers. 7138 case 'c': // $25 for indirect jumps 7139 case 'l': // lo register 7140 case 'x': // hilo register pair 7141 Info.setAllowsRegister(); 7142 return true; 7143 case 'I': // Signed 16-bit constant 7144 case 'J': // Integer 0 7145 case 'K': // Unsigned 16-bit constant 7146 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7147 case 'M': // Constants not loadable via lui, addiu, or ori 7148 case 'N': // Constant -1 to -65535 7149 case 'O': // A signed 15-bit constant 7150 case 'P': // A constant between 1 go 65535 7151 return true; 7152 case 'R': // An address that can be used in a non-macro load or store 7153 Info.setAllowsMemory(); 7154 return true; 7155 case 'Z': 7156 if (Name[1] == 'C') { // An address usable by ll, and sc. 7157 Info.setAllowsMemory(); 7158 Name++; // Skip over 'Z'. 7159 return true; 7160 } 7161 return false; 7162 } 7163 } 7164 7165 std::string convertConstraint(const char *&Constraint) const override { 7166 std::string R; 7167 switch (*Constraint) { 7168 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7169 if (Constraint[1] == 'C') { 7170 R = std::string("^") + std::string(Constraint, 2); 7171 Constraint++; 7172 return R; 7173 } 7174 break; 7175 } 7176 return TargetInfo::convertConstraint(Constraint); 7177 } 7178 7179 const char *getClobbers() const override { 7180 // In GCC, $1 is not widely used in generated code (it's used only in a few 7181 // specific situations), so there is no real need for users to add it to 7182 // the clobbers list if they want to use it in their inline assembly code. 7183 // 7184 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7185 // code generation, so using it in inline assembly without adding it to the 7186 // clobbers list can cause conflicts between the inline assembly code and 7187 // the surrounding generated code. 7188 // 7189 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7190 // operands, which will conflict with the ".set at" assembler option (which 7191 // we use only for inline assembly, in order to maintain compatibility with 7192 // GCC) and will also conflict with the user's usage of $1. 7193 // 7194 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7195 // register for generated code is to automatically clobber $1 for all inline 7196 // assembly code. 7197 // 7198 // FIXME: We should automatically clobber $1 only for inline assembly code 7199 // which actually uses it. This would allow LLVM to use $1 for inline 7200 // assembly operands if the user's assembly code doesn't use it. 7201 return "~{$1}"; 7202 } 7203 7204 bool handleTargetFeatures(std::vector<std::string> &Features, 7205 DiagnosticsEngine &Diags) override { 7206 IsMips16 = false; 7207 IsMicromips = false; 7208 IsNan2008 = isNaN2008Default(); 7209 IsSingleFloat = false; 7210 FloatABI = HardFloat; 7211 DspRev = NoDSP; 7212 HasFP64 = isFP64Default(); 7213 7214 for (const auto &Feature : Features) { 7215 if (Feature == "+single-float") 7216 IsSingleFloat = true; 7217 else if (Feature == "+soft-float") 7218 FloatABI = SoftFloat; 7219 else if (Feature == "+mips16") 7220 IsMips16 = true; 7221 else if (Feature == "+micromips") 7222 IsMicromips = true; 7223 else if (Feature == "+dsp") 7224 DspRev = std::max(DspRev, DSP1); 7225 else if (Feature == "+dspr2") 7226 DspRev = std::max(DspRev, DSP2); 7227 else if (Feature == "+msa") 7228 HasMSA = true; 7229 else if (Feature == "+fp64") 7230 HasFP64 = true; 7231 else if (Feature == "-fp64") 7232 HasFP64 = false; 7233 else if (Feature == "+nan2008") 7234 IsNan2008 = true; 7235 else if (Feature == "-nan2008") 7236 IsNan2008 = false; 7237 } 7238 7239 setDataLayout(); 7240 7241 return true; 7242 } 7243 7244 int getEHDataRegisterNumber(unsigned RegNo) const override { 7245 if (RegNo == 0) return 4; 7246 if (RegNo == 1) return 5; 7247 return -1; 7248 } 7249 7250 bool isCLZForZeroUndef() const override { return false; } 7251 }; 7252 7253 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 7254 #define BUILTIN(ID, TYPE, ATTRS) \ 7255 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7256 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7257 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7258 #include "clang/Basic/BuiltinsMips.def" 7259 }; 7260 7261 class Mips32TargetInfoBase : public MipsTargetInfoBase { 7262 public: 7263 Mips32TargetInfoBase(const llvm::Triple &Triple, const TargetOptions &Opts) 7264 : MipsTargetInfoBase(Triple, Opts, "o32", "mips32r2") { 7265 SizeType = UnsignedInt; 7266 PtrDiffType = SignedInt; 7267 Int64Type = SignedLongLong; 7268 IntMaxType = Int64Type; 7269 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7270 } 7271 bool setABI(const std::string &Name) override { 7272 if (Name == "o32" || Name == "eabi") { 7273 ABI = Name; 7274 return true; 7275 } 7276 return false; 7277 } 7278 void getTargetDefines(const LangOptions &Opts, 7279 MacroBuilder &Builder) const override { 7280 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 7281 7282 Builder.defineMacro("__mips", "32"); 7283 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7284 7285 const std::string& CPUStr = getCPU(); 7286 if (CPUStr == "mips32") 7287 Builder.defineMacro("__mips_isa_rev", "1"); 7288 else if (CPUStr == "mips32r2") 7289 Builder.defineMacro("__mips_isa_rev", "2"); 7290 else if (CPUStr == "mips32r3") 7291 Builder.defineMacro("__mips_isa_rev", "3"); 7292 else if (CPUStr == "mips32r5") 7293 Builder.defineMacro("__mips_isa_rev", "5"); 7294 else if (CPUStr == "mips32r6") 7295 Builder.defineMacro("__mips_isa_rev", "6"); 7296 7297 if (ABI == "o32") { 7298 Builder.defineMacro("__mips_o32"); 7299 Builder.defineMacro("_ABIO32", "1"); 7300 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7301 } 7302 else if (ABI == "eabi") 7303 Builder.defineMacro("__mips_eabi"); 7304 else 7305 llvm_unreachable("Invalid ABI for Mips32."); 7306 } 7307 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7308 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 7309 { { "at" }, "$1" }, 7310 { { "v0" }, "$2" }, 7311 { { "v1" }, "$3" }, 7312 { { "a0" }, "$4" }, 7313 { { "a1" }, "$5" }, 7314 { { "a2" }, "$6" }, 7315 { { "a3" }, "$7" }, 7316 { { "t0" }, "$8" }, 7317 { { "t1" }, "$9" }, 7318 { { "t2" }, "$10" }, 7319 { { "t3" }, "$11" }, 7320 { { "t4" }, "$12" }, 7321 { { "t5" }, "$13" }, 7322 { { "t6" }, "$14" }, 7323 { { "t7" }, "$15" }, 7324 { { "s0" }, "$16" }, 7325 { { "s1" }, "$17" }, 7326 { { "s2" }, "$18" }, 7327 { { "s3" }, "$19" }, 7328 { { "s4" }, "$20" }, 7329 { { "s5" }, "$21" }, 7330 { { "s6" }, "$22" }, 7331 { { "s7" }, "$23" }, 7332 { { "t8" }, "$24" }, 7333 { { "t9" }, "$25" }, 7334 { { "k0" }, "$26" }, 7335 { { "k1" }, "$27" }, 7336 { { "gp" }, "$28" }, 7337 { { "sp","$sp" }, "$29" }, 7338 { { "fp","$fp" }, "$30" }, 7339 { { "ra" }, "$31" } 7340 }; 7341 return llvm::makeArrayRef(GCCRegAliases); 7342 } 7343 }; 7344 7345 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 7346 void setDataLayout() override { 7347 resetDataLayout("E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"); 7348 } 7349 7350 public: 7351 Mips32EBTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7352 : Mips32TargetInfoBase(Triple, Opts) { 7353 } 7354 void getTargetDefines(const LangOptions &Opts, 7355 MacroBuilder &Builder) const override { 7356 DefineStd(Builder, "MIPSEB", Opts); 7357 Builder.defineMacro("_MIPSEB"); 7358 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 7359 } 7360 }; 7361 7362 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 7363 void setDataLayout() override { 7364 resetDataLayout("e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"); 7365 } 7366 7367 public: 7368 Mips32ELTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7369 : Mips32TargetInfoBase(Triple, Opts) { 7370 BigEndian = false; 7371 } 7372 void getTargetDefines(const LangOptions &Opts, 7373 MacroBuilder &Builder) const override { 7374 DefineStd(Builder, "MIPSEL", Opts); 7375 Builder.defineMacro("_MIPSEL"); 7376 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 7377 } 7378 }; 7379 7380 class Mips64TargetInfoBase : public MipsTargetInfoBase { 7381 public: 7382 Mips64TargetInfoBase(const llvm::Triple &Triple, const TargetOptions &Opts) 7383 : MipsTargetInfoBase(Triple, Opts, "n64", "mips64r2") { 7384 LongDoubleWidth = LongDoubleAlign = 128; 7385 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7386 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7387 LongDoubleWidth = LongDoubleAlign = 64; 7388 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7389 } 7390 setN64ABITypes(); 7391 SuitableAlign = 128; 7392 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7393 } 7394 7395 void setN64ABITypes() { 7396 LongWidth = LongAlign = 64; 7397 PointerWidth = PointerAlign = 64; 7398 SizeType = UnsignedLong; 7399 PtrDiffType = SignedLong; 7400 Int64Type = SignedLong; 7401 IntMaxType = Int64Type; 7402 } 7403 7404 void setN32ABITypes() { 7405 LongWidth = LongAlign = 32; 7406 PointerWidth = PointerAlign = 32; 7407 SizeType = UnsignedInt; 7408 PtrDiffType = SignedInt; 7409 Int64Type = SignedLongLong; 7410 IntMaxType = Int64Type; 7411 } 7412 7413 bool setABI(const std::string &Name) override { 7414 if (Name == "n32") { 7415 setN32ABITypes(); 7416 ABI = Name; 7417 return true; 7418 } 7419 if (Name == "n64") { 7420 setN64ABITypes(); 7421 ABI = Name; 7422 return true; 7423 } 7424 return false; 7425 } 7426 7427 void getTargetDefines(const LangOptions &Opts, 7428 MacroBuilder &Builder) const override { 7429 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 7430 7431 Builder.defineMacro("__mips", "64"); 7432 Builder.defineMacro("__mips64"); 7433 Builder.defineMacro("__mips64__"); 7434 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7435 7436 const std::string& CPUStr = getCPU(); 7437 if (CPUStr == "mips64") 7438 Builder.defineMacro("__mips_isa_rev", "1"); 7439 else if (CPUStr == "mips64r2") 7440 Builder.defineMacro("__mips_isa_rev", "2"); 7441 else if (CPUStr == "mips64r3") 7442 Builder.defineMacro("__mips_isa_rev", "3"); 7443 else if (CPUStr == "mips64r5") 7444 Builder.defineMacro("__mips_isa_rev", "5"); 7445 else if (CPUStr == "mips64r6") 7446 Builder.defineMacro("__mips_isa_rev", "6"); 7447 7448 if (ABI == "n32") { 7449 Builder.defineMacro("__mips_n32"); 7450 Builder.defineMacro("_ABIN32", "2"); 7451 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7452 } 7453 else if (ABI == "n64") { 7454 Builder.defineMacro("__mips_n64"); 7455 Builder.defineMacro("_ABI64", "3"); 7456 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7457 } 7458 else 7459 llvm_unreachable("Invalid ABI for Mips64."); 7460 7461 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7462 } 7463 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7464 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 7465 { { "at" }, "$1" }, 7466 { { "v0" }, "$2" }, 7467 { { "v1" }, "$3" }, 7468 { { "a0" }, "$4" }, 7469 { { "a1" }, "$5" }, 7470 { { "a2" }, "$6" }, 7471 { { "a3" }, "$7" }, 7472 { { "a4" }, "$8" }, 7473 { { "a5" }, "$9" }, 7474 { { "a6" }, "$10" }, 7475 { { "a7" }, "$11" }, 7476 { { "t0" }, "$12" }, 7477 { { "t1" }, "$13" }, 7478 { { "t2" }, "$14" }, 7479 { { "t3" }, "$15" }, 7480 { { "s0" }, "$16" }, 7481 { { "s1" }, "$17" }, 7482 { { "s2" }, "$18" }, 7483 { { "s3" }, "$19" }, 7484 { { "s4" }, "$20" }, 7485 { { "s5" }, "$21" }, 7486 { { "s6" }, "$22" }, 7487 { { "s7" }, "$23" }, 7488 { { "t8" }, "$24" }, 7489 { { "t9" }, "$25" }, 7490 { { "k0" }, "$26" }, 7491 { { "k1" }, "$27" }, 7492 { { "gp" }, "$28" }, 7493 { { "sp","$sp" }, "$29" }, 7494 { { "fp","$fp" }, "$30" }, 7495 { { "ra" }, "$31" } 7496 }; 7497 return llvm::makeArrayRef(GCCRegAliases); 7498 } 7499 7500 bool hasInt128Type() const override { return true; } 7501 }; 7502 7503 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 7504 void setDataLayout() override { 7505 if (ABI == "n32") 7506 resetDataLayout("E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7507 else 7508 resetDataLayout("E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7509 } 7510 7511 public: 7512 Mips64EBTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7513 : Mips64TargetInfoBase(Triple, Opts) {} 7514 void getTargetDefines(const LangOptions &Opts, 7515 MacroBuilder &Builder) const override { 7516 DefineStd(Builder, "MIPSEB", Opts); 7517 Builder.defineMacro("_MIPSEB"); 7518 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7519 } 7520 }; 7521 7522 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 7523 void setDataLayout() override { 7524 if (ABI == "n32") 7525 resetDataLayout("e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7526 else 7527 resetDataLayout("e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7528 } 7529 public: 7530 Mips64ELTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7531 : Mips64TargetInfoBase(Triple, Opts) { 7532 // Default ABI is n64. 7533 BigEndian = false; 7534 } 7535 void getTargetDefines(const LangOptions &Opts, 7536 MacroBuilder &Builder) const override { 7537 DefineStd(Builder, "MIPSEL", Opts); 7538 Builder.defineMacro("_MIPSEL"); 7539 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7540 } 7541 }; 7542 7543 class PNaClTargetInfo : public TargetInfo { 7544 public: 7545 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7546 : TargetInfo(Triple) { 7547 BigEndian = false; 7548 this->LongAlign = 32; 7549 this->LongWidth = 32; 7550 this->PointerAlign = 32; 7551 this->PointerWidth = 32; 7552 this->IntMaxType = TargetInfo::SignedLongLong; 7553 this->Int64Type = TargetInfo::SignedLongLong; 7554 this->DoubleAlign = 64; 7555 this->LongDoubleWidth = 64; 7556 this->LongDoubleAlign = 64; 7557 this->SizeType = TargetInfo::UnsignedInt; 7558 this->PtrDiffType = TargetInfo::SignedInt; 7559 this->IntPtrType = TargetInfo::SignedInt; 7560 this->RegParmMax = 0; // Disallow regparm 7561 } 7562 7563 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7564 Builder.defineMacro("__le32__"); 7565 Builder.defineMacro("__pnacl__"); 7566 } 7567 void getTargetDefines(const LangOptions &Opts, 7568 MacroBuilder &Builder) const override { 7569 getArchDefines(Opts, Builder); 7570 } 7571 bool hasFeature(StringRef Feature) const override { 7572 return Feature == "pnacl"; 7573 } 7574 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7575 BuiltinVaListKind getBuiltinVaListKind() const override { 7576 return TargetInfo::PNaClABIBuiltinVaList; 7577 } 7578 ArrayRef<const char *> getGCCRegNames() const override; 7579 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7580 bool validateAsmConstraint(const char *&Name, 7581 TargetInfo::ConstraintInfo &Info) const override { 7582 return false; 7583 } 7584 7585 const char *getClobbers() const override { 7586 return ""; 7587 } 7588 }; 7589 7590 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7591 return None; 7592 } 7593 7594 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7595 return None; 7596 } 7597 7598 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7599 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 7600 public: 7601 NaClMips32ELTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7602 : Mips32ELTargetInfo(Triple, Opts) {} 7603 7604 BuiltinVaListKind getBuiltinVaListKind() const override { 7605 return TargetInfo::PNaClABIBuiltinVaList; 7606 } 7607 }; 7608 7609 class Le64TargetInfo : public TargetInfo { 7610 static const Builtin::Info BuiltinInfo[]; 7611 7612 public: 7613 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7614 : TargetInfo(Triple) { 7615 BigEndian = false; 7616 NoAsmVariants = true; 7617 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7618 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7619 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 7620 } 7621 7622 void getTargetDefines(const LangOptions &Opts, 7623 MacroBuilder &Builder) const override { 7624 DefineStd(Builder, "unix", Opts); 7625 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7626 Builder.defineMacro("__ELF__"); 7627 } 7628 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7629 return llvm::makeArrayRef(BuiltinInfo, 7630 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7631 } 7632 BuiltinVaListKind getBuiltinVaListKind() const override { 7633 return TargetInfo::PNaClABIBuiltinVaList; 7634 } 7635 const char *getClobbers() const override { return ""; } 7636 ArrayRef<const char *> getGCCRegNames() const override { 7637 return None; 7638 } 7639 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7640 return None; 7641 } 7642 bool validateAsmConstraint(const char *&Name, 7643 TargetInfo::ConstraintInfo &Info) const override { 7644 return false; 7645 } 7646 7647 bool hasProtectedVisibility() const override { return false; } 7648 }; 7649 7650 class WebAssemblyTargetInfo : public TargetInfo { 7651 static const Builtin::Info BuiltinInfo[]; 7652 7653 enum SIMDEnum { 7654 NoSIMD, 7655 SIMD128, 7656 } SIMDLevel; 7657 7658 public: 7659 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 7660 : TargetInfo(T), SIMDLevel(NoSIMD) { 7661 BigEndian = false; 7662 NoAsmVariants = true; 7663 SuitableAlign = 128; 7664 LargeArrayMinWidth = 128; 7665 LargeArrayAlign = 128; 7666 SimdDefaultAlign = 128; 7667 SigAtomicType = SignedLong; 7668 LongDoubleWidth = LongDoubleAlign = 128; 7669 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7670 } 7671 7672 protected: 7673 void getTargetDefines(const LangOptions &Opts, 7674 MacroBuilder &Builder) const override { 7675 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7676 if (SIMDLevel >= SIMD128) 7677 Builder.defineMacro("__wasm_simd128__"); 7678 } 7679 7680 private: 7681 bool 7682 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7683 StringRef CPU, 7684 const std::vector<std::string> &FeaturesVec) const override { 7685 if (CPU == "bleeding-edge") 7686 Features["simd128"] = true; 7687 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7688 } 7689 bool hasFeature(StringRef Feature) const final { 7690 return llvm::StringSwitch<bool>(Feature) 7691 .Case("simd128", SIMDLevel >= SIMD128) 7692 .Default(false); 7693 } 7694 bool handleTargetFeatures(std::vector<std::string> &Features, 7695 DiagnosticsEngine &Diags) final { 7696 for (const auto &Feature : Features) { 7697 if (Feature == "+simd128") { 7698 SIMDLevel = std::max(SIMDLevel, SIMD128); 7699 continue; 7700 } 7701 if (Feature == "-simd128") { 7702 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7703 continue; 7704 } 7705 7706 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7707 << "-target-feature"; 7708 return false; 7709 } 7710 return true; 7711 } 7712 bool setCPU(const std::string &Name) final { 7713 return llvm::StringSwitch<bool>(Name) 7714 .Case("mvp", true) 7715 .Case("bleeding-edge", true) 7716 .Case("generic", true) 7717 .Default(false); 7718 } 7719 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7720 return llvm::makeArrayRef(BuiltinInfo, 7721 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7722 } 7723 BuiltinVaListKind getBuiltinVaListKind() const final { 7724 return VoidPtrBuiltinVaList; 7725 } 7726 ArrayRef<const char *> getGCCRegNames() const final { 7727 return None; 7728 } 7729 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7730 return None; 7731 } 7732 bool 7733 validateAsmConstraint(const char *&Name, 7734 TargetInfo::ConstraintInfo &Info) const final { 7735 return false; 7736 } 7737 const char *getClobbers() const final { return ""; } 7738 bool isCLZForZeroUndef() const final { return false; } 7739 bool hasInt128Type() const final { return true; } 7740 IntType getIntTypeByWidth(unsigned BitWidth, 7741 bool IsSigned) const final { 7742 // WebAssembly prefers long long for explicitly 64-bit integers. 7743 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7744 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7745 } 7746 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7747 bool IsSigned) const final { 7748 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7749 return BitWidth == 64 7750 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7751 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7752 } 7753 }; 7754 7755 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7756 #define BUILTIN(ID, TYPE, ATTRS) \ 7757 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7758 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7759 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7760 #include "clang/Basic/BuiltinsWebAssembly.def" 7761 }; 7762 7763 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7764 public: 7765 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 7766 const TargetOptions &Opts) 7767 : WebAssemblyTargetInfo(T, Opts) { 7768 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7769 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 7770 } 7771 7772 protected: 7773 void getTargetDefines(const LangOptions &Opts, 7774 MacroBuilder &Builder) const override { 7775 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7776 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7777 } 7778 }; 7779 7780 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7781 public: 7782 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 7783 const TargetOptions &Opts) 7784 : WebAssemblyTargetInfo(T, Opts) { 7785 LongAlign = LongWidth = 64; 7786 PointerAlign = PointerWidth = 64; 7787 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7788 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7789 } 7790 7791 protected: 7792 void getTargetDefines(const LangOptions &Opts, 7793 MacroBuilder &Builder) const override { 7794 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7795 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7796 } 7797 }; 7798 7799 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7800 #define BUILTIN(ID, TYPE, ATTRS) \ 7801 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7802 #include "clang/Basic/BuiltinsLe64.def" 7803 }; 7804 7805 static const unsigned SPIRAddrSpaceMap[] = { 7806 1, // opencl_global 7807 3, // opencl_local 7808 2, // opencl_constant 7809 4, // opencl_generic 7810 0, // cuda_device 7811 0, // cuda_constant 7812 0 // cuda_shared 7813 }; 7814 class SPIRTargetInfo : public TargetInfo { 7815 public: 7816 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7817 : TargetInfo(Triple) { 7818 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7819 "SPIR target must use unknown OS"); 7820 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7821 "SPIR target must use unknown environment type"); 7822 BigEndian = false; 7823 TLSSupported = false; 7824 LongWidth = LongAlign = 64; 7825 AddrSpaceMap = &SPIRAddrSpaceMap; 7826 UseAddrSpaceMapMangling = true; 7827 // Define available target features 7828 // These must be defined in sorted order! 7829 NoAsmVariants = true; 7830 } 7831 void getTargetDefines(const LangOptions &Opts, 7832 MacroBuilder &Builder) const override { 7833 DefineStd(Builder, "SPIR", Opts); 7834 } 7835 bool hasFeature(StringRef Feature) const override { 7836 return Feature == "spir"; 7837 } 7838 7839 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7840 const char *getClobbers() const override { return ""; } 7841 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7842 bool validateAsmConstraint(const char *&Name, 7843 TargetInfo::ConstraintInfo &info) const override { 7844 return true; 7845 } 7846 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7847 return None; 7848 } 7849 BuiltinVaListKind getBuiltinVaListKind() const override { 7850 return TargetInfo::VoidPtrBuiltinVaList; 7851 } 7852 7853 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7854 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK 7855 : CCCR_Warning; 7856 } 7857 7858 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7859 return CC_SpirFunction; 7860 } 7861 }; 7862 7863 class SPIR32TargetInfo : public SPIRTargetInfo { 7864 public: 7865 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7866 : SPIRTargetInfo(Triple, Opts) { 7867 PointerWidth = PointerAlign = 32; 7868 SizeType = TargetInfo::UnsignedInt; 7869 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7870 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7871 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7872 } 7873 void getTargetDefines(const LangOptions &Opts, 7874 MacroBuilder &Builder) const override { 7875 DefineStd(Builder, "SPIR32", Opts); 7876 } 7877 }; 7878 7879 class SPIR64TargetInfo : public SPIRTargetInfo { 7880 public: 7881 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7882 : SPIRTargetInfo(Triple, Opts) { 7883 PointerWidth = PointerAlign = 64; 7884 SizeType = TargetInfo::UnsignedLong; 7885 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7886 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7887 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7888 } 7889 void getTargetDefines(const LangOptions &Opts, 7890 MacroBuilder &Builder) const override { 7891 DefineStd(Builder, "SPIR64", Opts); 7892 } 7893 }; 7894 7895 class XCoreTargetInfo : public TargetInfo { 7896 static const Builtin::Info BuiltinInfo[]; 7897 public: 7898 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7899 : TargetInfo(Triple) { 7900 BigEndian = false; 7901 NoAsmVariants = true; 7902 LongLongAlign = 32; 7903 SuitableAlign = 32; 7904 DoubleAlign = LongDoubleAlign = 32; 7905 SizeType = UnsignedInt; 7906 PtrDiffType = SignedInt; 7907 IntPtrType = SignedInt; 7908 WCharType = UnsignedChar; 7909 WIntType = UnsignedInt; 7910 UseZeroLengthBitfieldAlignment = true; 7911 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7912 "-f64:32-a:0:32-n32"); 7913 } 7914 void getTargetDefines(const LangOptions &Opts, 7915 MacroBuilder &Builder) const override { 7916 Builder.defineMacro("__XS1B__"); 7917 } 7918 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7919 return llvm::makeArrayRef(BuiltinInfo, 7920 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 7921 } 7922 BuiltinVaListKind getBuiltinVaListKind() const override { 7923 return TargetInfo::VoidPtrBuiltinVaList; 7924 } 7925 const char *getClobbers() const override { 7926 return ""; 7927 } 7928 ArrayRef<const char *> getGCCRegNames() const override { 7929 static const char * const GCCRegNames[] = { 7930 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7931 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 7932 }; 7933 return llvm::makeArrayRef(GCCRegNames); 7934 } 7935 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7936 return None; 7937 } 7938 bool validateAsmConstraint(const char *&Name, 7939 TargetInfo::ConstraintInfo &Info) const override { 7940 return false; 7941 } 7942 int getEHDataRegisterNumber(unsigned RegNo) const override { 7943 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7944 return (RegNo < 2)? RegNo : -1; 7945 } 7946 bool allowsLargerPreferedTypeAlignment() const override { 7947 return false; 7948 } 7949 }; 7950 7951 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7952 #define BUILTIN(ID, TYPE, ATTRS) \ 7953 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7954 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7955 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7956 #include "clang/Basic/BuiltinsXCore.def" 7957 }; 7958 7959 // x86_32 Android target 7960 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7961 public: 7962 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7963 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 7964 SuitableAlign = 32; 7965 LongDoubleWidth = 64; 7966 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7967 } 7968 }; 7969 7970 // x86_64 Android target 7971 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7972 public: 7973 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7974 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 7975 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7976 } 7977 7978 bool useFloat128ManglingForLongDouble() const override { 7979 return true; 7980 } 7981 }; 7982 } // end anonymous namespace 7983 7984 //===----------------------------------------------------------------------===// 7985 // Driver code 7986 //===----------------------------------------------------------------------===// 7987 7988 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 7989 const TargetOptions &Opts) { 7990 llvm::Triple::OSType os = Triple.getOS(); 7991 7992 switch (Triple.getArch()) { 7993 default: 7994 return nullptr; 7995 7996 case llvm::Triple::xcore: 7997 return new XCoreTargetInfo(Triple, Opts); 7998 7999 case llvm::Triple::hexagon: 8000 return new HexagonTargetInfo(Triple, Opts); 8001 8002 case llvm::Triple::lanai: 8003 return new LanaiTargetInfo(Triple, Opts); 8004 8005 case llvm::Triple::aarch64: 8006 if (Triple.isOSDarwin()) 8007 return new DarwinAArch64TargetInfo(Triple, Opts); 8008 8009 switch (os) { 8010 case llvm::Triple::CloudABI: 8011 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 8012 case llvm::Triple::FreeBSD: 8013 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8014 case llvm::Triple::Linux: 8015 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8016 case llvm::Triple::NetBSD: 8017 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8018 default: 8019 return new AArch64leTargetInfo(Triple, Opts); 8020 } 8021 8022 case llvm::Triple::aarch64_be: 8023 switch (os) { 8024 case llvm::Triple::FreeBSD: 8025 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8026 case llvm::Triple::Linux: 8027 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8028 case llvm::Triple::NetBSD: 8029 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8030 default: 8031 return new AArch64beTargetInfo(Triple, Opts); 8032 } 8033 8034 case llvm::Triple::arm: 8035 case llvm::Triple::thumb: 8036 if (Triple.isOSBinFormatMachO()) 8037 return new DarwinARMTargetInfo(Triple, Opts); 8038 8039 switch (os) { 8040 case llvm::Triple::Linux: 8041 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 8042 case llvm::Triple::FreeBSD: 8043 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8044 case llvm::Triple::NetBSD: 8045 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8046 case llvm::Triple::OpenBSD: 8047 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8048 case llvm::Triple::Bitrig: 8049 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 8050 case llvm::Triple::RTEMS: 8051 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 8052 case llvm::Triple::NaCl: 8053 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 8054 case llvm::Triple::Win32: 8055 switch (Triple.getEnvironment()) { 8056 case llvm::Triple::Cygnus: 8057 return new CygwinARMTargetInfo(Triple, Opts); 8058 case llvm::Triple::GNU: 8059 return new MinGWARMTargetInfo(Triple, Opts); 8060 case llvm::Triple::Itanium: 8061 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 8062 case llvm::Triple::MSVC: 8063 default: // Assume MSVC for unknown environments 8064 return new MicrosoftARMleTargetInfo(Triple, Opts); 8065 } 8066 default: 8067 return new ARMleTargetInfo(Triple, Opts); 8068 } 8069 8070 case llvm::Triple::armeb: 8071 case llvm::Triple::thumbeb: 8072 if (Triple.isOSDarwin()) 8073 return new DarwinARMTargetInfo(Triple, Opts); 8074 8075 switch (os) { 8076 case llvm::Triple::Linux: 8077 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8078 case llvm::Triple::FreeBSD: 8079 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8080 case llvm::Triple::NetBSD: 8081 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8082 case llvm::Triple::OpenBSD: 8083 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8084 case llvm::Triple::Bitrig: 8085 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8086 case llvm::Triple::RTEMS: 8087 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8088 case llvm::Triple::NaCl: 8089 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8090 default: 8091 return new ARMbeTargetInfo(Triple, Opts); 8092 } 8093 8094 case llvm::Triple::bpfeb: 8095 case llvm::Triple::bpfel: 8096 return new BPFTargetInfo(Triple, Opts); 8097 8098 case llvm::Triple::msp430: 8099 return new MSP430TargetInfo(Triple, Opts); 8100 8101 case llvm::Triple::mips: 8102 switch (os) { 8103 case llvm::Triple::Linux: 8104 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple, Opts); 8105 case llvm::Triple::RTEMS: 8106 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple, Opts); 8107 case llvm::Triple::FreeBSD: 8108 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple, Opts); 8109 case llvm::Triple::NetBSD: 8110 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple, Opts); 8111 default: 8112 return new Mips32EBTargetInfo(Triple, Opts); 8113 } 8114 8115 case llvm::Triple::mipsel: 8116 switch (os) { 8117 case llvm::Triple::Linux: 8118 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple, Opts); 8119 case llvm::Triple::RTEMS: 8120 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple, Opts); 8121 case llvm::Triple::FreeBSD: 8122 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple, Opts); 8123 case llvm::Triple::NetBSD: 8124 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple, Opts); 8125 case llvm::Triple::NaCl: 8126 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple, Opts); 8127 default: 8128 return new Mips32ELTargetInfo(Triple, Opts); 8129 } 8130 8131 case llvm::Triple::mips64: 8132 switch (os) { 8133 case llvm::Triple::Linux: 8134 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 8135 case llvm::Triple::RTEMS: 8136 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 8137 case llvm::Triple::FreeBSD: 8138 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 8139 case llvm::Triple::NetBSD: 8140 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 8141 case llvm::Triple::OpenBSD: 8142 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 8143 default: 8144 return new Mips64EBTargetInfo(Triple, Opts); 8145 } 8146 8147 case llvm::Triple::mips64el: 8148 switch (os) { 8149 case llvm::Triple::Linux: 8150 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8151 case llvm::Triple::RTEMS: 8152 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8153 case llvm::Triple::FreeBSD: 8154 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8155 case llvm::Triple::NetBSD: 8156 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8157 case llvm::Triple::OpenBSD: 8158 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8159 default: 8160 return new Mips64ELTargetInfo(Triple, Opts); 8161 } 8162 8163 case llvm::Triple::le32: 8164 switch (os) { 8165 case llvm::Triple::NaCl: 8166 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 8167 default: 8168 return nullptr; 8169 } 8170 8171 case llvm::Triple::le64: 8172 return new Le64TargetInfo(Triple, Opts); 8173 8174 case llvm::Triple::ppc: 8175 if (Triple.isOSDarwin()) 8176 return new DarwinPPC32TargetInfo(Triple, Opts); 8177 switch (os) { 8178 case llvm::Triple::Linux: 8179 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 8180 case llvm::Triple::FreeBSD: 8181 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8182 case llvm::Triple::NetBSD: 8183 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8184 case llvm::Triple::OpenBSD: 8185 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8186 case llvm::Triple::RTEMS: 8187 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 8188 default: 8189 return new PPC32TargetInfo(Triple, Opts); 8190 } 8191 8192 case llvm::Triple::ppc64: 8193 if (Triple.isOSDarwin()) 8194 return new DarwinPPC64TargetInfo(Triple, Opts); 8195 switch (os) { 8196 case llvm::Triple::Linux: 8197 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8198 case llvm::Triple::Lv2: 8199 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 8200 case llvm::Triple::FreeBSD: 8201 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8202 case llvm::Triple::NetBSD: 8203 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8204 default: 8205 return new PPC64TargetInfo(Triple, Opts); 8206 } 8207 8208 case llvm::Triple::ppc64le: 8209 switch (os) { 8210 case llvm::Triple::Linux: 8211 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8212 case llvm::Triple::NetBSD: 8213 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8214 default: 8215 return new PPC64TargetInfo(Triple, Opts); 8216 } 8217 8218 case llvm::Triple::nvptx: 8219 return new NVPTX32TargetInfo(Triple, Opts); 8220 case llvm::Triple::nvptx64: 8221 return new NVPTX64TargetInfo(Triple, Opts); 8222 8223 case llvm::Triple::amdgcn: 8224 case llvm::Triple::r600: 8225 return new AMDGPUTargetInfo(Triple, Opts); 8226 8227 case llvm::Triple::sparc: 8228 switch (os) { 8229 case llvm::Triple::Linux: 8230 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8231 case llvm::Triple::Solaris: 8232 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8233 case llvm::Triple::NetBSD: 8234 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8235 case llvm::Triple::OpenBSD: 8236 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8237 case llvm::Triple::RTEMS: 8238 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8239 default: 8240 return new SparcV8TargetInfo(Triple, Opts); 8241 } 8242 8243 // The 'sparcel' architecture copies all the above cases except for Solaris. 8244 case llvm::Triple::sparcel: 8245 switch (os) { 8246 case llvm::Triple::Linux: 8247 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8248 case llvm::Triple::NetBSD: 8249 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8250 case llvm::Triple::OpenBSD: 8251 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8252 case llvm::Triple::RTEMS: 8253 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8254 default: 8255 return new SparcV8elTargetInfo(Triple, Opts); 8256 } 8257 8258 case llvm::Triple::sparcv9: 8259 switch (os) { 8260 case llvm::Triple::Linux: 8261 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8262 case llvm::Triple::Solaris: 8263 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8264 case llvm::Triple::NetBSD: 8265 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8266 case llvm::Triple::OpenBSD: 8267 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8268 case llvm::Triple::FreeBSD: 8269 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8270 default: 8271 return new SparcV9TargetInfo(Triple, Opts); 8272 } 8273 8274 case llvm::Triple::systemz: 8275 switch (os) { 8276 case llvm::Triple::Linux: 8277 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 8278 default: 8279 return new SystemZTargetInfo(Triple, Opts); 8280 } 8281 8282 case llvm::Triple::tce: 8283 return new TCETargetInfo(Triple, Opts); 8284 8285 case llvm::Triple::x86: 8286 if (Triple.isOSDarwin()) 8287 return new DarwinI386TargetInfo(Triple, Opts); 8288 8289 switch (os) { 8290 case llvm::Triple::CloudABI: 8291 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 8292 case llvm::Triple::Linux: { 8293 switch (Triple.getEnvironment()) { 8294 default: 8295 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 8296 case llvm::Triple::Android: 8297 return new AndroidX86_32TargetInfo(Triple, Opts); 8298 } 8299 } 8300 case llvm::Triple::DragonFly: 8301 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8302 case llvm::Triple::NetBSD: 8303 return new NetBSDI386TargetInfo(Triple, Opts); 8304 case llvm::Triple::OpenBSD: 8305 return new OpenBSDI386TargetInfo(Triple, Opts); 8306 case llvm::Triple::Bitrig: 8307 return new BitrigI386TargetInfo(Triple, Opts); 8308 case llvm::Triple::FreeBSD: 8309 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8310 case llvm::Triple::KFreeBSD: 8311 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8312 case llvm::Triple::Minix: 8313 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 8314 case llvm::Triple::Solaris: 8315 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 8316 case llvm::Triple::Win32: { 8317 switch (Triple.getEnvironment()) { 8318 case llvm::Triple::Cygnus: 8319 return new CygwinX86_32TargetInfo(Triple, Opts); 8320 case llvm::Triple::GNU: 8321 return new MinGWX86_32TargetInfo(Triple, Opts); 8322 case llvm::Triple::Itanium: 8323 case llvm::Triple::MSVC: 8324 default: // Assume MSVC for unknown environments 8325 return new MicrosoftX86_32TargetInfo(Triple, Opts); 8326 } 8327 } 8328 case llvm::Triple::Haiku: 8329 return new HaikuX86_32TargetInfo(Triple, Opts); 8330 case llvm::Triple::RTEMS: 8331 return new RTEMSX86_32TargetInfo(Triple, Opts); 8332 case llvm::Triple::NaCl: 8333 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 8334 case llvm::Triple::ELFIAMCU: 8335 return new MCUX86_32TargetInfo(Triple, Opts); 8336 default: 8337 return new X86_32TargetInfo(Triple, Opts); 8338 } 8339 8340 case llvm::Triple::x86_64: 8341 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 8342 return new DarwinX86_64TargetInfo(Triple, Opts); 8343 8344 switch (os) { 8345 case llvm::Triple::CloudABI: 8346 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 8347 case llvm::Triple::Linux: { 8348 switch (Triple.getEnvironment()) { 8349 default: 8350 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 8351 case llvm::Triple::Android: 8352 return new AndroidX86_64TargetInfo(Triple, Opts); 8353 } 8354 } 8355 case llvm::Triple::DragonFly: 8356 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8357 case llvm::Triple::NetBSD: 8358 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8359 case llvm::Triple::OpenBSD: 8360 return new OpenBSDX86_64TargetInfo(Triple, Opts); 8361 case llvm::Triple::Bitrig: 8362 return new BitrigX86_64TargetInfo(Triple, Opts); 8363 case llvm::Triple::FreeBSD: 8364 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8365 case llvm::Triple::KFreeBSD: 8366 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8367 case llvm::Triple::Solaris: 8368 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 8369 case llvm::Triple::Win32: { 8370 switch (Triple.getEnvironment()) { 8371 case llvm::Triple::Cygnus: 8372 return new CygwinX86_64TargetInfo(Triple, Opts); 8373 case llvm::Triple::GNU: 8374 return new MinGWX86_64TargetInfo(Triple, Opts); 8375 case llvm::Triple::MSVC: 8376 default: // Assume MSVC for unknown environments 8377 return new MicrosoftX86_64TargetInfo(Triple, Opts); 8378 } 8379 } 8380 case llvm::Triple::Haiku: 8381 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 8382 case llvm::Triple::NaCl: 8383 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 8384 case llvm::Triple::PS4: 8385 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 8386 default: 8387 return new X86_64TargetInfo(Triple, Opts); 8388 } 8389 8390 case llvm::Triple::spir: { 8391 if (Triple.getOS() != llvm::Triple::UnknownOS || 8392 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8393 return nullptr; 8394 return new SPIR32TargetInfo(Triple, Opts); 8395 } 8396 case llvm::Triple::spir64: { 8397 if (Triple.getOS() != llvm::Triple::UnknownOS || 8398 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8399 return nullptr; 8400 return new SPIR64TargetInfo(Triple, Opts); 8401 } 8402 case llvm::Triple::wasm32: 8403 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8404 return nullptr; 8405 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 8406 case llvm::Triple::wasm64: 8407 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8408 return nullptr; 8409 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 8410 } 8411 } 8412 8413 /// CreateTargetInfo - Return the target info object for the specified target 8414 /// options. 8415 TargetInfo * 8416 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8417 const std::shared_ptr<TargetOptions> &Opts) { 8418 llvm::Triple Triple(Opts->Triple); 8419 8420 // Construct the target 8421 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 8422 if (!Target) { 8423 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8424 return nullptr; 8425 } 8426 Target->TargetOpts = Opts; 8427 8428 // Set the target CPU if specified. 8429 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8430 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8431 return nullptr; 8432 } 8433 8434 // Set the target ABI if specified. 8435 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8436 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8437 return nullptr; 8438 } 8439 8440 // Set the fp math unit. 8441 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8442 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8443 return nullptr; 8444 } 8445 8446 // Compute the default target features, we need the target to handle this 8447 // because features may have dependencies on one another. 8448 llvm::StringMap<bool> Features; 8449 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8450 Opts->FeaturesAsWritten)) 8451 return nullptr; 8452 8453 // Add the features to the compile options. 8454 Opts->Features.clear(); 8455 for (const auto &F : Features) 8456 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8457 8458 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8459 return nullptr; 8460 8461 return Target.release(); 8462 } 8463