1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "clang/Basic/Version.h" 23 #include "llvm/ADT/APFloat.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringExtras.h" 26 #include "llvm/ADT/StringRef.h" 27 #include "llvm/ADT/StringSwitch.h" 28 #include "llvm/ADT/Triple.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/TargetParser.h" 32 #include <algorithm> 33 #include <memory> 34 35 using namespace clang; 36 37 //===----------------------------------------------------------------------===// 38 // Common code shared among targets. 39 //===----------------------------------------------------------------------===// 40 41 /// DefineStd - Define a macro name and standard variants. For example if 42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 43 /// when in GNU mode. 44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 45 const LangOptions &Opts) { 46 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 47 48 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 49 // in the user's namespace. 50 if (Opts.GNUMode) 51 Builder.defineMacro(MacroName); 52 53 // Define __unix. 54 Builder.defineMacro("__" + MacroName); 55 56 // Define __unix__. 57 Builder.defineMacro("__" + MacroName + "__"); 58 } 59 60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 61 bool Tuning = true) { 62 Builder.defineMacro("__" + CPUName); 63 Builder.defineMacro("__" + CPUName + "__"); 64 if (Tuning) 65 Builder.defineMacro("__tune_" + CPUName + "__"); 66 } 67 68 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 69 const TargetOptions &Opts); 70 71 //===----------------------------------------------------------------------===// 72 // Defines specific to certain operating systems. 73 //===----------------------------------------------------------------------===// 74 75 namespace { 76 template<typename TgtInfo> 77 class OSTargetInfo : public TgtInfo { 78 protected: 79 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 80 MacroBuilder &Builder) const=0; 81 public: 82 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 83 : TgtInfo(Triple, Opts) {} 84 void getTargetDefines(const LangOptions &Opts, 85 MacroBuilder &Builder) const override { 86 TgtInfo::getTargetDefines(Opts, Builder); 87 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 88 } 89 90 }; 91 92 // CloudABI Target 93 template <typename Target> 94 class CloudABITargetInfo : public OSTargetInfo<Target> { 95 protected: 96 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 97 MacroBuilder &Builder) const override { 98 Builder.defineMacro("__CloudABI__"); 99 Builder.defineMacro("__ELF__"); 100 101 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 102 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 103 Builder.defineMacro("__STDC_UTF_16__"); 104 Builder.defineMacro("__STDC_UTF_32__"); 105 } 106 107 public: 108 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 109 : OSTargetInfo<Target>(Triple, Opts) {} 110 }; 111 112 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 113 const llvm::Triple &Triple, 114 StringRef &PlatformName, 115 VersionTuple &PlatformMinVersion) { 116 Builder.defineMacro("__APPLE_CC__", "6000"); 117 Builder.defineMacro("__APPLE__"); 118 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 119 // AddressSanitizer doesn't play well with source fortification, which is on 120 // by default on Darwin. 121 if (Opts.Sanitize.has(SanitizerKind::Address)) 122 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 123 124 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 125 if (!Opts.ObjC1) { 126 // __weak is always defined, for use in blocks and with objc pointers. 127 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 128 Builder.defineMacro("__strong", ""); 129 Builder.defineMacro("__unsafe_unretained", ""); 130 } 131 132 if (Opts.Static) 133 Builder.defineMacro("__STATIC__"); 134 else 135 Builder.defineMacro("__DYNAMIC__"); 136 137 if (Opts.POSIXThreads) 138 Builder.defineMacro("_REENTRANT"); 139 140 // Get the platform type and version number from the triple. 141 unsigned Maj, Min, Rev; 142 if (Triple.isMacOSX()) { 143 Triple.getMacOSXVersion(Maj, Min, Rev); 144 PlatformName = "macosx"; 145 } else { 146 Triple.getOSVersion(Maj, Min, Rev); 147 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 148 } 149 150 // If -target arch-pc-win32-macho option specified, we're 151 // generating code for Win32 ABI. No need to emit 152 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 153 if (PlatformName == "win32") { 154 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 155 return; 156 } 157 158 // Set the appropriate OS version define. 159 if (Triple.isiOS()) { 160 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 161 char Str[6]; 162 Str[0] = '0' + Maj; 163 Str[1] = '0' + (Min / 10); 164 Str[2] = '0' + (Min % 10); 165 Str[3] = '0' + (Rev / 10); 166 Str[4] = '0' + (Rev % 10); 167 Str[5] = '\0'; 168 if (Triple.isTvOS()) 169 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 170 else 171 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 172 Str); 173 174 } else if (Triple.isWatchOS()) { 175 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 176 char Str[6]; 177 Str[0] = '0' + Maj; 178 Str[1] = '0' + (Min / 10); 179 Str[2] = '0' + (Min % 10); 180 Str[3] = '0' + (Rev / 10); 181 Str[4] = '0' + (Rev % 10); 182 Str[5] = '\0'; 183 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 184 } else if (Triple.isMacOSX()) { 185 // Note that the Driver allows versions which aren't representable in the 186 // define (because we only get a single digit for the minor and micro 187 // revision numbers). So, we limit them to the maximum representable 188 // version. 189 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 190 char Str[7]; 191 if (Maj < 10 || (Maj == 10 && Min < 10)) { 192 Str[0] = '0' + (Maj / 10); 193 Str[1] = '0' + (Maj % 10); 194 Str[2] = '0' + std::min(Min, 9U); 195 Str[3] = '0' + std::min(Rev, 9U); 196 Str[4] = '\0'; 197 } else { 198 // Handle versions > 10.9. 199 Str[0] = '0' + (Maj / 10); 200 Str[1] = '0' + (Maj % 10); 201 Str[2] = '0' + (Min / 10); 202 Str[3] = '0' + (Min % 10); 203 Str[4] = '0' + (Rev / 10); 204 Str[5] = '0' + (Rev % 10); 205 Str[6] = '\0'; 206 } 207 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 208 } 209 210 // Tell users about the kernel if there is one. 211 if (Triple.isOSDarwin()) 212 Builder.defineMacro("__MACH__"); 213 214 // The Watch ABI uses Dwarf EH. 215 if(Triple.isWatchABI()) 216 Builder.defineMacro("__ARM_DWARF_EH__"); 217 218 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 219 } 220 221 template<typename Target> 222 class DarwinTargetInfo : public OSTargetInfo<Target> { 223 protected: 224 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 225 MacroBuilder &Builder) const override { 226 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 227 this->PlatformMinVersion); 228 } 229 230 public: 231 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 232 : OSTargetInfo<Target>(Triple, Opts) { 233 // By default, no TLS, and we whitelist permitted architecture/OS 234 // combinations. 235 this->TLSSupported = false; 236 237 if (Triple.isMacOSX()) 238 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 239 else if (Triple.isiOS()) { 240 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 241 if (Triple.getArch() == llvm::Triple::x86_64 || 242 Triple.getArch() == llvm::Triple::aarch64) 243 this->TLSSupported = !Triple.isOSVersionLT(8); 244 else if (Triple.getArch() == llvm::Triple::x86 || 245 Triple.getArch() == llvm::Triple::arm || 246 Triple.getArch() == llvm::Triple::thumb) 247 this->TLSSupported = !Triple.isOSVersionLT(9); 248 } else if (Triple.isWatchOS()) 249 this->TLSSupported = !Triple.isOSVersionLT(2); 250 251 this->MCountName = "\01mcount"; 252 } 253 254 std::string isValidSectionSpecifier(StringRef SR) const override { 255 // Let MCSectionMachO validate this. 256 StringRef Segment, Section; 257 unsigned TAA, StubSize; 258 bool HasTAA; 259 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 260 TAA, HasTAA, StubSize); 261 } 262 263 const char *getStaticInitSectionSpecifier() const override { 264 // FIXME: We should return 0 when building kexts. 265 return "__TEXT,__StaticInit,regular,pure_instructions"; 266 } 267 268 /// Darwin does not support protected visibility. Darwin's "default" 269 /// is very similar to ELF's "protected"; Darwin requires a "weak" 270 /// attribute on declarations that can be dynamically replaced. 271 bool hasProtectedVisibility() const override { 272 return false; 273 } 274 275 unsigned getExnObjectAlignment() const override { 276 // The alignment of an exception object is 8-bytes for darwin since 277 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 278 // and therefore doesn't guarantee 16-byte alignment. 279 return 64; 280 } 281 }; 282 283 284 // DragonFlyBSD Target 285 template<typename Target> 286 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 287 protected: 288 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 289 MacroBuilder &Builder) const override { 290 // DragonFly defines; list based off of gcc output 291 Builder.defineMacro("__DragonFly__"); 292 Builder.defineMacro("__DragonFly_cc_version", "100001"); 293 Builder.defineMacro("__ELF__"); 294 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 295 Builder.defineMacro("__tune_i386__"); 296 DefineStd(Builder, "unix", Opts); 297 } 298 public: 299 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 300 : OSTargetInfo<Target>(Triple, Opts) { 301 switch (Triple.getArch()) { 302 default: 303 case llvm::Triple::x86: 304 case llvm::Triple::x86_64: 305 this->MCountName = ".mcount"; 306 break; 307 } 308 } 309 }; 310 311 #ifndef FREEBSD_CC_VERSION 312 #define FREEBSD_CC_VERSION 0U 313 #endif 314 315 // FreeBSD Target 316 template<typename Target> 317 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 318 protected: 319 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 320 MacroBuilder &Builder) const override { 321 // FreeBSD defines; list based off of gcc output 322 323 unsigned Release = Triple.getOSMajorVersion(); 324 if (Release == 0U) 325 Release = 8U; 326 unsigned CCVersion = FREEBSD_CC_VERSION; 327 if (CCVersion == 0U) 328 CCVersion = Release * 100000U + 1U; 329 330 Builder.defineMacro("__FreeBSD__", Twine(Release)); 331 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 332 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 333 DefineStd(Builder, "unix", Opts); 334 Builder.defineMacro("__ELF__"); 335 336 // On FreeBSD, wchar_t contains the number of the code point as 337 // used by the character set of the locale. These character sets are 338 // not necessarily a superset of ASCII. 339 // 340 // FIXME: This is wrong; the macro refers to the numerical values 341 // of wchar_t *literals*, which are not locale-dependent. However, 342 // FreeBSD systems apparently depend on us getting this wrong, and 343 // setting this to 1 is conforming even if all the basic source 344 // character literals have the same encoding as char and wchar_t. 345 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 346 } 347 public: 348 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 349 : OSTargetInfo<Target>(Triple, Opts) { 350 switch (Triple.getArch()) { 351 default: 352 case llvm::Triple::x86: 353 case llvm::Triple::x86_64: 354 this->MCountName = ".mcount"; 355 break; 356 case llvm::Triple::mips: 357 case llvm::Triple::mipsel: 358 case llvm::Triple::ppc: 359 case llvm::Triple::ppc64: 360 case llvm::Triple::ppc64le: 361 this->MCountName = "_mcount"; 362 break; 363 case llvm::Triple::arm: 364 this->MCountName = "__mcount"; 365 break; 366 } 367 } 368 }; 369 370 // GNU/kFreeBSD Target 371 template<typename Target> 372 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 373 protected: 374 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 375 MacroBuilder &Builder) const override { 376 // GNU/kFreeBSD defines; list based off of gcc output 377 378 DefineStd(Builder, "unix", Opts); 379 Builder.defineMacro("__FreeBSD_kernel__"); 380 Builder.defineMacro("__GLIBC__"); 381 Builder.defineMacro("__ELF__"); 382 if (Opts.POSIXThreads) 383 Builder.defineMacro("_REENTRANT"); 384 if (Opts.CPlusPlus) 385 Builder.defineMacro("_GNU_SOURCE"); 386 } 387 public: 388 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 389 : OSTargetInfo<Target>(Triple, Opts) {} 390 }; 391 392 // Haiku Target 393 template<typename Target> 394 class HaikuTargetInfo : public OSTargetInfo<Target> { 395 protected: 396 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 397 MacroBuilder &Builder) const override { 398 // Haiku defines; list based off of gcc output 399 Builder.defineMacro("__HAIKU__"); 400 Builder.defineMacro("__ELF__"); 401 DefineStd(Builder, "unix", Opts); 402 } 403 public: 404 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 405 : OSTargetInfo<Target>(Triple, Opts) { 406 this->SizeType = TargetInfo::UnsignedLong; 407 this->IntPtrType = TargetInfo::SignedLong; 408 this->PtrDiffType = TargetInfo::SignedLong; 409 this->ProcessIDType = TargetInfo::SignedLong; 410 this->TLSSupported = false; 411 412 } 413 }; 414 415 // Minix Target 416 template<typename Target> 417 class MinixTargetInfo : public OSTargetInfo<Target> { 418 protected: 419 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 420 MacroBuilder &Builder) const override { 421 // Minix defines 422 423 Builder.defineMacro("__minix", "3"); 424 Builder.defineMacro("_EM_WSIZE", "4"); 425 Builder.defineMacro("_EM_PSIZE", "4"); 426 Builder.defineMacro("_EM_SSIZE", "2"); 427 Builder.defineMacro("_EM_LSIZE", "4"); 428 Builder.defineMacro("_EM_FSIZE", "4"); 429 Builder.defineMacro("_EM_DSIZE", "8"); 430 Builder.defineMacro("__ELF__"); 431 DefineStd(Builder, "unix", Opts); 432 } 433 public: 434 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 435 : OSTargetInfo<Target>(Triple, Opts) {} 436 }; 437 438 // Linux target 439 template<typename Target> 440 class LinuxTargetInfo : public OSTargetInfo<Target> { 441 protected: 442 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 443 MacroBuilder &Builder) const override { 444 // Linux defines; list based off of gcc output 445 DefineStd(Builder, "unix", Opts); 446 DefineStd(Builder, "linux", Opts); 447 Builder.defineMacro("__gnu_linux__"); 448 Builder.defineMacro("__ELF__"); 449 if (Triple.isAndroid()) { 450 Builder.defineMacro("__ANDROID__", "1"); 451 unsigned Maj, Min, Rev; 452 Triple.getEnvironmentVersion(Maj, Min, Rev); 453 this->PlatformName = "android"; 454 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 455 } 456 if (Opts.POSIXThreads) 457 Builder.defineMacro("_REENTRANT"); 458 if (Opts.CPlusPlus) 459 Builder.defineMacro("_GNU_SOURCE"); 460 if (this->HasFloat128) 461 Builder.defineMacro("__FLOAT128__"); 462 } 463 public: 464 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 465 : OSTargetInfo<Target>(Triple, Opts) { 466 this->WIntType = TargetInfo::UnsignedInt; 467 468 switch (Triple.getArch()) { 469 default: 470 break; 471 case llvm::Triple::ppc: 472 case llvm::Triple::ppc64: 473 case llvm::Triple::ppc64le: 474 this->MCountName = "_mcount"; 475 break; 476 case llvm::Triple::x86: 477 case llvm::Triple::x86_64: 478 case llvm::Triple::systemz: 479 this->HasFloat128 = true; 480 break; 481 } 482 } 483 484 const char *getStaticInitSectionSpecifier() const override { 485 return ".text.startup"; 486 } 487 }; 488 489 // NetBSD Target 490 template<typename Target> 491 class NetBSDTargetInfo : public OSTargetInfo<Target> { 492 protected: 493 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 494 MacroBuilder &Builder) const override { 495 // NetBSD defines; list based off of gcc output 496 Builder.defineMacro("__NetBSD__"); 497 Builder.defineMacro("__unix__"); 498 Builder.defineMacro("__ELF__"); 499 if (Opts.POSIXThreads) 500 Builder.defineMacro("_POSIX_THREADS"); 501 502 switch (Triple.getArch()) { 503 default: 504 break; 505 case llvm::Triple::arm: 506 case llvm::Triple::armeb: 507 case llvm::Triple::thumb: 508 case llvm::Triple::thumbeb: 509 Builder.defineMacro("__ARM_DWARF_EH__"); 510 break; 511 } 512 } 513 public: 514 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 515 : OSTargetInfo<Target>(Triple, Opts) { 516 this->MCountName = "_mcount"; 517 } 518 }; 519 520 // OpenBSD Target 521 template<typename Target> 522 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 523 protected: 524 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 525 MacroBuilder &Builder) const override { 526 // OpenBSD defines; list based off of gcc output 527 528 Builder.defineMacro("__OpenBSD__"); 529 DefineStd(Builder, "unix", Opts); 530 Builder.defineMacro("__ELF__"); 531 if (Opts.POSIXThreads) 532 Builder.defineMacro("_REENTRANT"); 533 } 534 public: 535 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 536 : OSTargetInfo<Target>(Triple, Opts) { 537 this->TLSSupported = false; 538 539 switch (Triple.getArch()) { 540 default: 541 case llvm::Triple::x86: 542 case llvm::Triple::x86_64: 543 case llvm::Triple::arm: 544 case llvm::Triple::sparc: 545 this->MCountName = "__mcount"; 546 break; 547 case llvm::Triple::mips64: 548 case llvm::Triple::mips64el: 549 case llvm::Triple::ppc: 550 case llvm::Triple::sparcv9: 551 this->MCountName = "_mcount"; 552 break; 553 } 554 } 555 }; 556 557 // Bitrig Target 558 template<typename Target> 559 class BitrigTargetInfo : public OSTargetInfo<Target> { 560 protected: 561 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 562 MacroBuilder &Builder) const override { 563 // Bitrig defines; list based off of gcc output 564 565 Builder.defineMacro("__Bitrig__"); 566 DefineStd(Builder, "unix", Opts); 567 Builder.defineMacro("__ELF__"); 568 if (Opts.POSIXThreads) 569 Builder.defineMacro("_REENTRANT"); 570 571 switch (Triple.getArch()) { 572 default: 573 break; 574 case llvm::Triple::arm: 575 case llvm::Triple::armeb: 576 case llvm::Triple::thumb: 577 case llvm::Triple::thumbeb: 578 Builder.defineMacro("__ARM_DWARF_EH__"); 579 break; 580 } 581 } 582 public: 583 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 584 : OSTargetInfo<Target>(Triple, Opts) { 585 this->MCountName = "__mcount"; 586 } 587 }; 588 589 // PSP Target 590 template<typename Target> 591 class PSPTargetInfo : public OSTargetInfo<Target> { 592 protected: 593 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 594 MacroBuilder &Builder) const override { 595 // PSP defines; list based on the output of the pspdev gcc toolchain. 596 Builder.defineMacro("PSP"); 597 Builder.defineMacro("_PSP"); 598 Builder.defineMacro("__psp__"); 599 Builder.defineMacro("__ELF__"); 600 } 601 public: 602 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 603 }; 604 605 // PS3 PPU Target 606 template<typename Target> 607 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 608 protected: 609 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 610 MacroBuilder &Builder) const override { 611 // PS3 PPU defines. 612 Builder.defineMacro("__PPC__"); 613 Builder.defineMacro("__PPU__"); 614 Builder.defineMacro("__CELLOS_LV2__"); 615 Builder.defineMacro("__ELF__"); 616 Builder.defineMacro("__LP32__"); 617 Builder.defineMacro("_ARCH_PPC64"); 618 Builder.defineMacro("__powerpc64__"); 619 } 620 public: 621 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 622 : OSTargetInfo<Target>(Triple, Opts) { 623 this->LongWidth = this->LongAlign = 32; 624 this->PointerWidth = this->PointerAlign = 32; 625 this->IntMaxType = TargetInfo::SignedLongLong; 626 this->Int64Type = TargetInfo::SignedLongLong; 627 this->SizeType = TargetInfo::UnsignedInt; 628 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 629 } 630 }; 631 632 template <typename Target> 633 class PS4OSTargetInfo : public OSTargetInfo<Target> { 634 protected: 635 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 636 MacroBuilder &Builder) const override { 637 Builder.defineMacro("__FreeBSD__", "9"); 638 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 639 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 640 DefineStd(Builder, "unix", Opts); 641 Builder.defineMacro("__ELF__"); 642 Builder.defineMacro("__ORBIS__"); 643 } 644 public: 645 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 646 : OSTargetInfo<Target>(Triple, Opts) { 647 this->WCharType = this->UnsignedShort; 648 649 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 650 this->MaxTLSAlign = 256; 651 652 // On PS4, do not honor explicit bit field alignment, 653 // as in "__attribute__((aligned(2))) int b : 1;". 654 this->UseExplicitBitFieldAlignment = false; 655 656 switch (Triple.getArch()) { 657 default: 658 case llvm::Triple::x86_64: 659 this->MCountName = ".mcount"; 660 break; 661 } 662 } 663 }; 664 665 // Solaris target 666 template<typename Target> 667 class SolarisTargetInfo : public OSTargetInfo<Target> { 668 protected: 669 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 670 MacroBuilder &Builder) const override { 671 DefineStd(Builder, "sun", Opts); 672 DefineStd(Builder, "unix", Opts); 673 Builder.defineMacro("__ELF__"); 674 Builder.defineMacro("__svr4__"); 675 Builder.defineMacro("__SVR4"); 676 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 677 // newer, but to 500 for everything else. feature_test.h has a check to 678 // ensure that you are not using C99 with an old version of X/Open or C89 679 // with a new version. 680 if (Opts.C99) 681 Builder.defineMacro("_XOPEN_SOURCE", "600"); 682 else 683 Builder.defineMacro("_XOPEN_SOURCE", "500"); 684 if (Opts.CPlusPlus) 685 Builder.defineMacro("__C99FEATURES__"); 686 Builder.defineMacro("_LARGEFILE_SOURCE"); 687 Builder.defineMacro("_LARGEFILE64_SOURCE"); 688 Builder.defineMacro("__EXTENSIONS__"); 689 Builder.defineMacro("_REENTRANT"); 690 } 691 public: 692 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 693 : OSTargetInfo<Target>(Triple, Opts) { 694 this->WCharType = this->SignedInt; 695 // FIXME: WIntType should be SignedLong 696 } 697 }; 698 699 // Windows target 700 template<typename Target> 701 class WindowsTargetInfo : public OSTargetInfo<Target> { 702 protected: 703 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 704 MacroBuilder &Builder) const override { 705 Builder.defineMacro("_WIN32"); 706 } 707 void getVisualStudioDefines(const LangOptions &Opts, 708 MacroBuilder &Builder) const { 709 if (Opts.CPlusPlus) { 710 if (Opts.RTTIData) 711 Builder.defineMacro("_CPPRTTI"); 712 713 if (Opts.CXXExceptions) 714 Builder.defineMacro("_CPPUNWIND"); 715 } 716 717 if (Opts.Bool) 718 Builder.defineMacro("__BOOL_DEFINED"); 719 720 if (!Opts.CharIsSigned) 721 Builder.defineMacro("_CHAR_UNSIGNED"); 722 723 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 724 // but it works for now. 725 if (Opts.POSIXThreads) 726 Builder.defineMacro("_MT"); 727 728 if (Opts.MSCompatibilityVersion) { 729 Builder.defineMacro("_MSC_VER", 730 Twine(Opts.MSCompatibilityVersion / 100000)); 731 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 732 // FIXME We cannot encode the revision information into 32-bits 733 Builder.defineMacro("_MSC_BUILD", Twine(1)); 734 735 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 736 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 737 } 738 739 if (Opts.MicrosoftExt) { 740 Builder.defineMacro("_MSC_EXTENSIONS"); 741 742 if (Opts.CPlusPlus11) { 743 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 744 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 745 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 746 } 747 } 748 749 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 750 } 751 752 public: 753 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 754 : OSTargetInfo<Target>(Triple, Opts) {} 755 }; 756 757 template <typename Target> 758 class NaClTargetInfo : public OSTargetInfo<Target> { 759 protected: 760 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 761 MacroBuilder &Builder) const override { 762 if (Opts.POSIXThreads) 763 Builder.defineMacro("_REENTRANT"); 764 if (Opts.CPlusPlus) 765 Builder.defineMacro("_GNU_SOURCE"); 766 767 DefineStd(Builder, "unix", Opts); 768 Builder.defineMacro("__ELF__"); 769 Builder.defineMacro("__native_client__"); 770 } 771 772 public: 773 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 774 : OSTargetInfo<Target>(Triple, Opts) { 775 this->LongAlign = 32; 776 this->LongWidth = 32; 777 this->PointerAlign = 32; 778 this->PointerWidth = 32; 779 this->IntMaxType = TargetInfo::SignedLongLong; 780 this->Int64Type = TargetInfo::SignedLongLong; 781 this->DoubleAlign = 64; 782 this->LongDoubleWidth = 64; 783 this->LongDoubleAlign = 64; 784 this->LongLongWidth = 64; 785 this->LongLongAlign = 64; 786 this->SizeType = TargetInfo::UnsignedInt; 787 this->PtrDiffType = TargetInfo::SignedInt; 788 this->IntPtrType = TargetInfo::SignedInt; 789 // RegParmMax is inherited from the underlying architecture 790 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 791 if (Triple.getArch() == llvm::Triple::arm) { 792 // Handled in ARM's setABI(). 793 } else if (Triple.getArch() == llvm::Triple::x86) { 794 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 795 } else if (Triple.getArch() == llvm::Triple::x86_64) { 796 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 797 } else if (Triple.getArch() == llvm::Triple::mipsel) { 798 // Handled on mips' setDataLayout. 799 } else { 800 assert(Triple.getArch() == llvm::Triple::le32); 801 this->resetDataLayout("e-p:32:32-i64:64"); 802 } 803 } 804 }; 805 806 // WebAssembly target 807 template <typename Target> 808 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 809 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 810 MacroBuilder &Builder) const final { 811 // A common platform macro. 812 if (Opts.POSIXThreads) 813 Builder.defineMacro("_REENTRANT"); 814 // Follow g++ convention and predefine _GNU_SOURCE for C++. 815 if (Opts.CPlusPlus) 816 Builder.defineMacro("_GNU_SOURCE"); 817 } 818 819 // As an optimization, group static init code together in a section. 820 const char *getStaticInitSectionSpecifier() const final { 821 return ".text.__startup"; 822 } 823 824 public: 825 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 826 const TargetOptions &Opts) 827 : OSTargetInfo<Target>(Triple, Opts) { 828 this->MCountName = "__mcount"; 829 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 830 } 831 }; 832 833 //===----------------------------------------------------------------------===// 834 // Specific target implementations. 835 //===----------------------------------------------------------------------===// 836 837 // PPC abstract base class 838 class PPCTargetInfo : public TargetInfo { 839 static const Builtin::Info BuiltinInfo[]; 840 static const char * const GCCRegNames[]; 841 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 842 std::string CPU; 843 844 // Target cpu features. 845 bool HasVSX; 846 bool HasP8Vector; 847 bool HasP8Crypto; 848 bool HasDirectMove; 849 bool HasQPX; 850 bool HasHTM; 851 bool HasBPERMD; 852 bool HasExtDiv; 853 854 protected: 855 std::string ABI; 856 857 public: 858 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 859 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 860 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 861 HasBPERMD(false), HasExtDiv(false) { 862 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 863 SimdDefaultAlign = 128; 864 LongDoubleWidth = LongDoubleAlign = 128; 865 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 866 } 867 868 /// \brief Flags for architecture specific defines. 869 typedef enum { 870 ArchDefineNone = 0, 871 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 872 ArchDefinePpcgr = 1 << 1, 873 ArchDefinePpcsq = 1 << 2, 874 ArchDefine440 = 1 << 3, 875 ArchDefine603 = 1 << 4, 876 ArchDefine604 = 1 << 5, 877 ArchDefinePwr4 = 1 << 6, 878 ArchDefinePwr5 = 1 << 7, 879 ArchDefinePwr5x = 1 << 8, 880 ArchDefinePwr6 = 1 << 9, 881 ArchDefinePwr6x = 1 << 10, 882 ArchDefinePwr7 = 1 << 11, 883 ArchDefinePwr8 = 1 << 12, 884 ArchDefinePwr9 = 1 << 13, 885 ArchDefineA2 = 1 << 14, 886 ArchDefineA2q = 1 << 15 887 } ArchDefineTypes; 888 889 // Note: GCC recognizes the following additional cpus: 890 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 891 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 892 // titan, rs64. 893 bool setCPU(const std::string &Name) override { 894 bool CPUKnown = llvm::StringSwitch<bool>(Name) 895 .Case("generic", true) 896 .Case("440", true) 897 .Case("450", true) 898 .Case("601", true) 899 .Case("602", true) 900 .Case("603", true) 901 .Case("603e", true) 902 .Case("603ev", true) 903 .Case("604", true) 904 .Case("604e", true) 905 .Case("620", true) 906 .Case("630", true) 907 .Case("g3", true) 908 .Case("7400", true) 909 .Case("g4", true) 910 .Case("7450", true) 911 .Case("g4+", true) 912 .Case("750", true) 913 .Case("970", true) 914 .Case("g5", true) 915 .Case("a2", true) 916 .Case("a2q", true) 917 .Case("e500mc", true) 918 .Case("e5500", true) 919 .Case("power3", true) 920 .Case("pwr3", true) 921 .Case("power4", true) 922 .Case("pwr4", true) 923 .Case("power5", true) 924 .Case("pwr5", true) 925 .Case("power5x", true) 926 .Case("pwr5x", true) 927 .Case("power6", true) 928 .Case("pwr6", true) 929 .Case("power6x", true) 930 .Case("pwr6x", true) 931 .Case("power7", true) 932 .Case("pwr7", true) 933 .Case("power8", true) 934 .Case("pwr8", true) 935 .Case("power9", true) 936 .Case("pwr9", true) 937 .Case("powerpc", true) 938 .Case("ppc", true) 939 .Case("powerpc64", true) 940 .Case("ppc64", true) 941 .Case("powerpc64le", true) 942 .Case("ppc64le", true) 943 .Default(false); 944 945 if (CPUKnown) 946 CPU = Name; 947 948 return CPUKnown; 949 } 950 951 952 StringRef getABI() const override { return ABI; } 953 954 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 955 return llvm::makeArrayRef(BuiltinInfo, 956 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 957 } 958 959 bool isCLZForZeroUndef() const override { return false; } 960 961 void getTargetDefines(const LangOptions &Opts, 962 MacroBuilder &Builder) const override; 963 964 bool 965 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 966 StringRef CPU, 967 const std::vector<std::string> &FeaturesVec) const override; 968 969 bool handleTargetFeatures(std::vector<std::string> &Features, 970 DiagnosticsEngine &Diags) override; 971 bool hasFeature(StringRef Feature) const override; 972 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 973 bool Enabled) const override; 974 975 ArrayRef<const char *> getGCCRegNames() const override; 976 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 977 bool validateAsmConstraint(const char *&Name, 978 TargetInfo::ConstraintInfo &Info) const override { 979 switch (*Name) { 980 default: return false; 981 case 'O': // Zero 982 break; 983 case 'b': // Base register 984 case 'f': // Floating point register 985 Info.setAllowsRegister(); 986 break; 987 // FIXME: The following are added to allow parsing. 988 // I just took a guess at what the actions should be. 989 // Also, is more specific checking needed? I.e. specific registers? 990 case 'd': // Floating point register (containing 64-bit value) 991 case 'v': // Altivec vector register 992 Info.setAllowsRegister(); 993 break; 994 case 'w': 995 switch (Name[1]) { 996 case 'd':// VSX vector register to hold vector double data 997 case 'f':// VSX vector register to hold vector float data 998 case 's':// VSX vector register to hold scalar float data 999 case 'a':// Any VSX register 1000 case 'c':// An individual CR bit 1001 break; 1002 default: 1003 return false; 1004 } 1005 Info.setAllowsRegister(); 1006 Name++; // Skip over 'w'. 1007 break; 1008 case 'h': // `MQ', `CTR', or `LINK' register 1009 case 'q': // `MQ' register 1010 case 'c': // `CTR' register 1011 case 'l': // `LINK' register 1012 case 'x': // `CR' register (condition register) number 0 1013 case 'y': // `CR' register (condition register) 1014 case 'z': // `XER[CA]' carry bit (part of the XER register) 1015 Info.setAllowsRegister(); 1016 break; 1017 case 'I': // Signed 16-bit constant 1018 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1019 // (use `L' instead for SImode constants) 1020 case 'K': // Unsigned 16-bit constant 1021 case 'L': // Signed 16-bit constant shifted left 16 bits 1022 case 'M': // Constant larger than 31 1023 case 'N': // Exact power of 2 1024 case 'P': // Constant whose negation is a signed 16-bit constant 1025 case 'G': // Floating point constant that can be loaded into a 1026 // register with one instruction per word 1027 case 'H': // Integer/Floating point constant that can be loaded 1028 // into a register using three instructions 1029 break; 1030 case 'm': // Memory operand. Note that on PowerPC targets, m can 1031 // include addresses that update the base register. It 1032 // is therefore only safe to use `m' in an asm statement 1033 // if that asm statement accesses the operand exactly once. 1034 // The asm statement must also use `%U<opno>' as a 1035 // placeholder for the "update" flag in the corresponding 1036 // load or store instruction. For example: 1037 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1038 // is correct but: 1039 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1040 // is not. Use es rather than m if you don't want the base 1041 // register to be updated. 1042 case 'e': 1043 if (Name[1] != 's') 1044 return false; 1045 // es: A "stable" memory operand; that is, one which does not 1046 // include any automodification of the base register. Unlike 1047 // `m', this constraint can be used in asm statements that 1048 // might access the operand several times, or that might not 1049 // access it at all. 1050 Info.setAllowsMemory(); 1051 Name++; // Skip over 'e'. 1052 break; 1053 case 'Q': // Memory operand that is an offset from a register (it is 1054 // usually better to use `m' or `es' in asm statements) 1055 case 'Z': // Memory operand that is an indexed or indirect from a 1056 // register (it is usually better to use `m' or `es' in 1057 // asm statements) 1058 Info.setAllowsMemory(); 1059 Info.setAllowsRegister(); 1060 break; 1061 case 'R': // AIX TOC entry 1062 case 'a': // Address operand that is an indexed or indirect from a 1063 // register (`p' is preferable for asm statements) 1064 case 'S': // Constant suitable as a 64-bit mask operand 1065 case 'T': // Constant suitable as a 32-bit mask operand 1066 case 'U': // System V Release 4 small data area reference 1067 case 't': // AND masks that can be performed by two rldic{l, r} 1068 // instructions 1069 case 'W': // Vector constant that does not require memory 1070 case 'j': // Vector constant that is all zeros. 1071 break; 1072 // End FIXME. 1073 } 1074 return true; 1075 } 1076 std::string convertConstraint(const char *&Constraint) const override { 1077 std::string R; 1078 switch (*Constraint) { 1079 case 'e': 1080 case 'w': 1081 // Two-character constraint; add "^" hint for later parsing. 1082 R = std::string("^") + std::string(Constraint, 2); 1083 Constraint++; 1084 break; 1085 default: 1086 return TargetInfo::convertConstraint(Constraint); 1087 } 1088 return R; 1089 } 1090 const char *getClobbers() const override { 1091 return ""; 1092 } 1093 int getEHDataRegisterNumber(unsigned RegNo) const override { 1094 if (RegNo == 0) return 3; 1095 if (RegNo == 1) return 4; 1096 return -1; 1097 } 1098 1099 bool hasSjLjLowering() const override { 1100 return true; 1101 } 1102 1103 bool useFloat128ManglingForLongDouble() const override { 1104 return LongDoubleWidth == 128 && 1105 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1106 getTriple().isOSBinFormatELF(); 1107 } 1108 }; 1109 1110 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1111 #define BUILTIN(ID, TYPE, ATTRS) \ 1112 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1113 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1114 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1115 #include "clang/Basic/BuiltinsPPC.def" 1116 }; 1117 1118 /// handleTargetFeatures - Perform initialization based on the user 1119 /// configured set of features. 1120 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1121 DiagnosticsEngine &Diags) { 1122 for (const auto &Feature : Features) { 1123 if (Feature == "+vsx") { 1124 HasVSX = true; 1125 } else if (Feature == "+bpermd") { 1126 HasBPERMD = true; 1127 } else if (Feature == "+extdiv") { 1128 HasExtDiv = true; 1129 } else if (Feature == "+power8-vector") { 1130 HasP8Vector = true; 1131 } else if (Feature == "+crypto") { 1132 HasP8Crypto = true; 1133 } else if (Feature == "+direct-move") { 1134 HasDirectMove = true; 1135 } else if (Feature == "+qpx") { 1136 HasQPX = true; 1137 } else if (Feature == "+htm") { 1138 HasHTM = true; 1139 } else if (Feature == "+float128") { 1140 HasFloat128 = true; 1141 } 1142 // TODO: Finish this list and add an assert that we've handled them 1143 // all. 1144 } 1145 1146 return true; 1147 } 1148 1149 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1150 /// #defines that are not tied to a specific subtarget. 1151 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1152 MacroBuilder &Builder) const { 1153 // Target identification. 1154 Builder.defineMacro("__ppc__"); 1155 Builder.defineMacro("__PPC__"); 1156 Builder.defineMacro("_ARCH_PPC"); 1157 Builder.defineMacro("__powerpc__"); 1158 Builder.defineMacro("__POWERPC__"); 1159 if (PointerWidth == 64) { 1160 Builder.defineMacro("_ARCH_PPC64"); 1161 Builder.defineMacro("__powerpc64__"); 1162 Builder.defineMacro("__ppc64__"); 1163 Builder.defineMacro("__PPC64__"); 1164 } 1165 1166 // Target properties. 1167 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1168 Builder.defineMacro("_LITTLE_ENDIAN"); 1169 } else { 1170 if (getTriple().getOS() != llvm::Triple::NetBSD && 1171 getTriple().getOS() != llvm::Triple::OpenBSD) 1172 Builder.defineMacro("_BIG_ENDIAN"); 1173 } 1174 1175 // ABI options. 1176 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1177 Builder.defineMacro("_CALL_ELF", "1"); 1178 if (ABI == "elfv2") 1179 Builder.defineMacro("_CALL_ELF", "2"); 1180 1181 // Subtarget options. 1182 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1183 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1184 1185 // FIXME: Should be controlled by command line option. 1186 if (LongDoubleWidth == 128) 1187 Builder.defineMacro("__LONG_DOUBLE_128__"); 1188 1189 if (Opts.AltiVec) { 1190 Builder.defineMacro("__VEC__", "10206"); 1191 Builder.defineMacro("__ALTIVEC__"); 1192 } 1193 1194 // CPU identification. 1195 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1196 .Case("440", ArchDefineName) 1197 .Case("450", ArchDefineName | ArchDefine440) 1198 .Case("601", ArchDefineName) 1199 .Case("602", ArchDefineName | ArchDefinePpcgr) 1200 .Case("603", ArchDefineName | ArchDefinePpcgr) 1201 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1202 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1203 .Case("604", ArchDefineName | ArchDefinePpcgr) 1204 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1205 .Case("620", ArchDefineName | ArchDefinePpcgr) 1206 .Case("630", ArchDefineName | ArchDefinePpcgr) 1207 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1208 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1209 .Case("750", ArchDefineName | ArchDefinePpcgr) 1210 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1211 | ArchDefinePpcsq) 1212 .Case("a2", ArchDefineA2) 1213 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1214 .Case("pwr3", ArchDefinePpcgr) 1215 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1216 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1217 | ArchDefinePpcsq) 1218 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1219 | ArchDefinePpcgr | ArchDefinePpcsq) 1220 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1221 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1222 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1223 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1224 | ArchDefinePpcsq) 1225 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1226 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1227 | ArchDefinePpcgr | ArchDefinePpcsq) 1228 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1229 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1230 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1231 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 1232 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1233 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1234 | ArchDefinePpcsq) 1235 .Case("power3", ArchDefinePpcgr) 1236 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1237 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1238 | ArchDefinePpcsq) 1239 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1240 | ArchDefinePpcgr | ArchDefinePpcsq) 1241 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1242 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1243 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1244 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1245 | ArchDefinePpcsq) 1246 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1247 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1248 | ArchDefinePpcgr | ArchDefinePpcsq) 1249 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1250 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1251 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1252 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 1253 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1254 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1255 | ArchDefinePpcsq) 1256 .Default(ArchDefineNone); 1257 1258 if (defs & ArchDefineName) 1259 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1260 if (defs & ArchDefinePpcgr) 1261 Builder.defineMacro("_ARCH_PPCGR"); 1262 if (defs & ArchDefinePpcsq) 1263 Builder.defineMacro("_ARCH_PPCSQ"); 1264 if (defs & ArchDefine440) 1265 Builder.defineMacro("_ARCH_440"); 1266 if (defs & ArchDefine603) 1267 Builder.defineMacro("_ARCH_603"); 1268 if (defs & ArchDefine604) 1269 Builder.defineMacro("_ARCH_604"); 1270 if (defs & ArchDefinePwr4) 1271 Builder.defineMacro("_ARCH_PWR4"); 1272 if (defs & ArchDefinePwr5) 1273 Builder.defineMacro("_ARCH_PWR5"); 1274 if (defs & ArchDefinePwr5x) 1275 Builder.defineMacro("_ARCH_PWR5X"); 1276 if (defs & ArchDefinePwr6) 1277 Builder.defineMacro("_ARCH_PWR6"); 1278 if (defs & ArchDefinePwr6x) 1279 Builder.defineMacro("_ARCH_PWR6X"); 1280 if (defs & ArchDefinePwr7) 1281 Builder.defineMacro("_ARCH_PWR7"); 1282 if (defs & ArchDefinePwr8) 1283 Builder.defineMacro("_ARCH_PWR8"); 1284 if (defs & ArchDefinePwr9) 1285 Builder.defineMacro("_ARCH_PWR9"); 1286 if (defs & ArchDefineA2) 1287 Builder.defineMacro("_ARCH_A2"); 1288 if (defs & ArchDefineA2q) { 1289 Builder.defineMacro("_ARCH_A2Q"); 1290 Builder.defineMacro("_ARCH_QP"); 1291 } 1292 1293 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1294 Builder.defineMacro("__bg__"); 1295 Builder.defineMacro("__THW_BLUEGENE__"); 1296 Builder.defineMacro("__bgq__"); 1297 Builder.defineMacro("__TOS_BGQ__"); 1298 } 1299 1300 if (HasVSX) 1301 Builder.defineMacro("__VSX__"); 1302 if (HasP8Vector) 1303 Builder.defineMacro("__POWER8_VECTOR__"); 1304 if (HasP8Crypto) 1305 Builder.defineMacro("__CRYPTO__"); 1306 if (HasHTM) 1307 Builder.defineMacro("__HTM__"); 1308 if (HasFloat128) 1309 Builder.defineMacro("__FLOAT128__"); 1310 1311 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1312 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1313 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1314 if (PointerWidth == 64) 1315 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1316 1317 // FIXME: The following are not yet generated here by Clang, but are 1318 // generated by GCC: 1319 // 1320 // _SOFT_FLOAT_ 1321 // __RECIP_PRECISION__ 1322 // __APPLE_ALTIVEC__ 1323 // __RECIP__ 1324 // __RECIPF__ 1325 // __RSQRTE__ 1326 // __RSQRTEF__ 1327 // _SOFT_DOUBLE_ 1328 // __NO_LWSYNC__ 1329 // __HAVE_BSWAP__ 1330 // __LONGDOUBLE128 1331 // __CMODEL_MEDIUM__ 1332 // __CMODEL_LARGE__ 1333 // _CALL_SYSV 1334 // _CALL_DARWIN 1335 // __NO_FPRS__ 1336 } 1337 1338 // Handle explicit options being passed to the compiler here: if we've 1339 // explicitly turned off vsx and turned on power8-vector or direct-move then 1340 // go ahead and error since the customer has expressed a somewhat incompatible 1341 // set of options. 1342 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1343 const std::vector<std::string> &FeaturesVec) { 1344 1345 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1346 FeaturesVec.end()) { 1347 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1348 FeaturesVec.end()) { 1349 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1350 << "-mno-vsx"; 1351 return false; 1352 } 1353 1354 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1355 FeaturesVec.end()) { 1356 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1357 << "-mno-vsx"; 1358 return false; 1359 } 1360 1361 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1362 FeaturesVec.end()) { 1363 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1364 << "-mno-vsx"; 1365 return false; 1366 } 1367 } 1368 1369 return true; 1370 } 1371 1372 bool PPCTargetInfo::initFeatureMap( 1373 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1374 const std::vector<std::string> &FeaturesVec) const { 1375 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1376 .Case("7400", true) 1377 .Case("g4", true) 1378 .Case("7450", true) 1379 .Case("g4+", true) 1380 .Case("970", true) 1381 .Case("g5", true) 1382 .Case("pwr6", true) 1383 .Case("pwr7", true) 1384 .Case("pwr8", true) 1385 .Case("pwr9", true) 1386 .Case("ppc64", true) 1387 .Case("ppc64le", true) 1388 .Default(false); 1389 1390 Features["qpx"] = (CPU == "a2q"); 1391 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1392 .Case("ppc64le", true) 1393 .Case("pwr9", true) 1394 .Case("pwr8", true) 1395 .Default(false); 1396 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1397 .Case("ppc64le", true) 1398 .Case("pwr9", true) 1399 .Case("pwr8", true) 1400 .Default(false); 1401 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1402 .Case("ppc64le", true) 1403 .Case("pwr9", true) 1404 .Case("pwr8", true) 1405 .Case("pwr7", true) 1406 .Default(false); 1407 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1408 .Case("ppc64le", true) 1409 .Case("pwr9", true) 1410 .Case("pwr8", true) 1411 .Case("pwr7", true) 1412 .Default(false); 1413 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1414 .Case("ppc64le", true) 1415 .Case("pwr9", true) 1416 .Case("pwr8", true) 1417 .Default(false); 1418 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1419 .Case("ppc64le", true) 1420 .Case("pwr9", true) 1421 .Case("pwr8", true) 1422 .Case("pwr7", true) 1423 .Default(false); 1424 1425 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1426 return false; 1427 1428 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1429 } 1430 1431 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1432 return llvm::StringSwitch<bool>(Feature) 1433 .Case("powerpc", true) 1434 .Case("vsx", HasVSX) 1435 .Case("power8-vector", HasP8Vector) 1436 .Case("crypto", HasP8Crypto) 1437 .Case("direct-move", HasDirectMove) 1438 .Case("qpx", HasQPX) 1439 .Case("htm", HasHTM) 1440 .Case("bpermd", HasBPERMD) 1441 .Case("extdiv", HasExtDiv) 1442 .Case("float128", HasFloat128) 1443 .Default(false); 1444 } 1445 1446 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1447 StringRef Name, bool Enabled) const { 1448 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1449 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1450 // incompatible options. 1451 if (Enabled) { 1452 if (Name == "direct-move") { 1453 Features[Name] = Features["vsx"] = true; 1454 } else if (Name == "power8-vector") { 1455 Features[Name] = Features["vsx"] = true; 1456 } else if (Name == "float128") { 1457 Features[Name] = Features["vsx"] = true; 1458 } else { 1459 Features[Name] = true; 1460 } 1461 } else { 1462 if (Name == "vsx") { 1463 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1464 Features["float128"] = false; 1465 } else { 1466 Features[Name] = false; 1467 } 1468 } 1469 } 1470 1471 const char * const PPCTargetInfo::GCCRegNames[] = { 1472 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1473 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1474 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1475 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1476 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1477 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1478 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1479 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1480 "mq", "lr", "ctr", "ap", 1481 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1482 "xer", 1483 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1484 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1485 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1486 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1487 "vrsave", "vscr", 1488 "spe_acc", "spefscr", 1489 "sfp" 1490 }; 1491 1492 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1493 return llvm::makeArrayRef(GCCRegNames); 1494 } 1495 1496 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1497 // While some of these aliases do map to different registers 1498 // they still share the same register name. 1499 { { "0" }, "r0" }, 1500 { { "1"}, "r1" }, 1501 { { "2" }, "r2" }, 1502 { { "3" }, "r3" }, 1503 { { "4" }, "r4" }, 1504 { { "5" }, "r5" }, 1505 { { "6" }, "r6" }, 1506 { { "7" }, "r7" }, 1507 { { "8" }, "r8" }, 1508 { { "9" }, "r9" }, 1509 { { "10" }, "r10" }, 1510 { { "11" }, "r11" }, 1511 { { "12" }, "r12" }, 1512 { { "13" }, "r13" }, 1513 { { "14" }, "r14" }, 1514 { { "15" }, "r15" }, 1515 { { "16" }, "r16" }, 1516 { { "17" }, "r17" }, 1517 { { "18" }, "r18" }, 1518 { { "19" }, "r19" }, 1519 { { "20" }, "r20" }, 1520 { { "21" }, "r21" }, 1521 { { "22" }, "r22" }, 1522 { { "23" }, "r23" }, 1523 { { "24" }, "r24" }, 1524 { { "25" }, "r25" }, 1525 { { "26" }, "r26" }, 1526 { { "27" }, "r27" }, 1527 { { "28" }, "r28" }, 1528 { { "29" }, "r29" }, 1529 { { "30" }, "r30" }, 1530 { { "31" }, "r31" }, 1531 { { "fr0" }, "f0" }, 1532 { { "fr1" }, "f1" }, 1533 { { "fr2" }, "f2" }, 1534 { { "fr3" }, "f3" }, 1535 { { "fr4" }, "f4" }, 1536 { { "fr5" }, "f5" }, 1537 { { "fr6" }, "f6" }, 1538 { { "fr7" }, "f7" }, 1539 { { "fr8" }, "f8" }, 1540 { { "fr9" }, "f9" }, 1541 { { "fr10" }, "f10" }, 1542 { { "fr11" }, "f11" }, 1543 { { "fr12" }, "f12" }, 1544 { { "fr13" }, "f13" }, 1545 { { "fr14" }, "f14" }, 1546 { { "fr15" }, "f15" }, 1547 { { "fr16" }, "f16" }, 1548 { { "fr17" }, "f17" }, 1549 { { "fr18" }, "f18" }, 1550 { { "fr19" }, "f19" }, 1551 { { "fr20" }, "f20" }, 1552 { { "fr21" }, "f21" }, 1553 { { "fr22" }, "f22" }, 1554 { { "fr23" }, "f23" }, 1555 { { "fr24" }, "f24" }, 1556 { { "fr25" }, "f25" }, 1557 { { "fr26" }, "f26" }, 1558 { { "fr27" }, "f27" }, 1559 { { "fr28" }, "f28" }, 1560 { { "fr29" }, "f29" }, 1561 { { "fr30" }, "f30" }, 1562 { { "fr31" }, "f31" }, 1563 { { "cc" }, "cr0" }, 1564 }; 1565 1566 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1567 return llvm::makeArrayRef(GCCRegAliases); 1568 } 1569 1570 class PPC32TargetInfo : public PPCTargetInfo { 1571 public: 1572 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1573 : PPCTargetInfo(Triple, Opts) { 1574 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1575 1576 switch (getTriple().getOS()) { 1577 case llvm::Triple::Linux: 1578 case llvm::Triple::FreeBSD: 1579 case llvm::Triple::NetBSD: 1580 SizeType = UnsignedInt; 1581 PtrDiffType = SignedInt; 1582 IntPtrType = SignedInt; 1583 break; 1584 default: 1585 break; 1586 } 1587 1588 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1589 LongDoubleWidth = LongDoubleAlign = 64; 1590 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1591 } 1592 1593 // PPC32 supports atomics up to 4 bytes. 1594 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1595 } 1596 1597 BuiltinVaListKind getBuiltinVaListKind() const override { 1598 // This is the ELF definition, and is overridden by the Darwin sub-target 1599 return TargetInfo::PowerABIBuiltinVaList; 1600 } 1601 }; 1602 1603 // Note: ABI differences may eventually require us to have a separate 1604 // TargetInfo for little endian. 1605 class PPC64TargetInfo : public PPCTargetInfo { 1606 public: 1607 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1608 : PPCTargetInfo(Triple, Opts) { 1609 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1610 IntMaxType = SignedLong; 1611 Int64Type = SignedLong; 1612 1613 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1614 resetDataLayout("e-m:e-i64:64-n32:64"); 1615 ABI = "elfv2"; 1616 } else { 1617 resetDataLayout("E-m:e-i64:64-n32:64"); 1618 ABI = "elfv1"; 1619 } 1620 1621 switch (getTriple().getOS()) { 1622 case llvm::Triple::FreeBSD: 1623 LongDoubleWidth = LongDoubleAlign = 64; 1624 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1625 break; 1626 case llvm::Triple::NetBSD: 1627 IntMaxType = SignedLongLong; 1628 Int64Type = SignedLongLong; 1629 break; 1630 default: 1631 break; 1632 } 1633 1634 // PPC64 supports atomics up to 8 bytes. 1635 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1636 } 1637 BuiltinVaListKind getBuiltinVaListKind() const override { 1638 return TargetInfo::CharPtrBuiltinVaList; 1639 } 1640 // PPC64 Linux-specific ABI options. 1641 bool setABI(const std::string &Name) override { 1642 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1643 ABI = Name; 1644 return true; 1645 } 1646 return false; 1647 } 1648 }; 1649 1650 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1651 public: 1652 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1653 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1654 HasAlignMac68kSupport = true; 1655 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1656 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1657 LongLongAlign = 32; 1658 SuitableAlign = 128; 1659 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1660 } 1661 BuiltinVaListKind getBuiltinVaListKind() const override { 1662 return TargetInfo::CharPtrBuiltinVaList; 1663 } 1664 }; 1665 1666 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1667 public: 1668 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1669 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1670 HasAlignMac68kSupport = true; 1671 SuitableAlign = 128; 1672 resetDataLayout("E-m:o-i64:64-n32:64"); 1673 } 1674 }; 1675 1676 static const unsigned NVPTXAddrSpaceMap[] = { 1677 1, // opencl_global 1678 3, // opencl_local 1679 4, // opencl_constant 1680 // FIXME: generic has to be added to the target 1681 0, // opencl_generic 1682 1, // cuda_device 1683 4, // cuda_constant 1684 3, // cuda_shared 1685 }; 1686 1687 class NVPTXTargetInfo : public TargetInfo { 1688 static const char *const GCCRegNames[]; 1689 static const Builtin::Info BuiltinInfo[]; 1690 1691 // The GPU profiles supported by the NVPTX backend 1692 enum GPUKind { 1693 GK_NONE, 1694 GK_SM20, 1695 GK_SM21, 1696 GK_SM30, 1697 GK_SM35, 1698 GK_SM37, 1699 GK_SM50, 1700 GK_SM52, 1701 GK_SM53, 1702 } GPU; 1703 1704 public: 1705 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1706 : TargetInfo(Triple) { 1707 BigEndian = false; 1708 TLSSupported = false; 1709 LongWidth = LongAlign = 64; 1710 AddrSpaceMap = &NVPTXAddrSpaceMap; 1711 UseAddrSpaceMapMangling = true; 1712 // Define available target features 1713 // These must be defined in sorted order! 1714 NoAsmVariants = true; 1715 // Set the default GPU to sm20 1716 GPU = GK_SM20; 1717 1718 // If possible, get a TargetInfo for our host triple, so we can match its 1719 // types. 1720 llvm::Triple HostTriple(Opts.HostTriple); 1721 if (HostTriple.isNVPTX()) 1722 return; 1723 std::unique_ptr<TargetInfo> HostTarget( 1724 AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1725 if (!HostTarget) { 1726 return; 1727 } 1728 1729 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1730 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1731 BoolWidth = HostTarget->getBoolWidth(); 1732 BoolAlign = HostTarget->getBoolAlign(); 1733 IntWidth = HostTarget->getIntWidth(); 1734 IntAlign = HostTarget->getIntAlign(); 1735 HalfWidth = HostTarget->getHalfWidth(); 1736 HalfAlign = HostTarget->getHalfAlign(); 1737 FloatWidth = HostTarget->getFloatWidth(); 1738 FloatAlign = HostTarget->getFloatAlign(); 1739 DoubleWidth = HostTarget->getDoubleWidth(); 1740 DoubleAlign = HostTarget->getDoubleAlign(); 1741 LongWidth = HostTarget->getLongWidth(); 1742 LongAlign = HostTarget->getLongAlign(); 1743 LongLongWidth = HostTarget->getLongLongWidth(); 1744 LongLongAlign = HostTarget->getLongLongAlign(); 1745 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1746 DefaultAlignForAttributeAligned = 1747 HostTarget->getDefaultAlignForAttributeAligned(); 1748 SizeType = HostTarget->getSizeType(); 1749 IntMaxType = HostTarget->getIntMaxType(); 1750 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1751 IntPtrType = HostTarget->getIntPtrType(); 1752 WCharType = HostTarget->getWCharType(); 1753 WIntType = HostTarget->getWIntType(); 1754 Char16Type = HostTarget->getChar16Type(); 1755 Char32Type = HostTarget->getChar32Type(); 1756 Int64Type = HostTarget->getInt64Type(); 1757 SigAtomicType = HostTarget->getSigAtomicType(); 1758 ProcessIDType = HostTarget->getProcessIDType(); 1759 1760 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1761 UseZeroLengthBitfieldAlignment = 1762 HostTarget->useZeroLengthBitfieldAlignment(); 1763 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1764 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1765 1766 // Properties intentionally not copied from host: 1767 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1768 // host/device boundary. 1769 // - SuitableAlign: Not visible across the host/device boundary, and may 1770 // correctly be different on host/device, e.g. if host has wider vector 1771 // types than device. 1772 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1773 // as its double type, but that's not necessarily true on the host. 1774 // TODO: nvcc emits a warning when using long double on device; we should 1775 // do the same. 1776 } 1777 void getTargetDefines(const LangOptions &Opts, 1778 MacroBuilder &Builder) const override { 1779 Builder.defineMacro("__PTX__"); 1780 Builder.defineMacro("__NVPTX__"); 1781 if (Opts.CUDAIsDevice) { 1782 // Set __CUDA_ARCH__ for the GPU specified. 1783 std::string CUDAArchCode; 1784 switch (GPU) { 1785 case GK_SM20: 1786 CUDAArchCode = "200"; 1787 break; 1788 case GK_SM21: 1789 CUDAArchCode = "210"; 1790 break; 1791 case GK_SM30: 1792 CUDAArchCode = "300"; 1793 break; 1794 case GK_SM35: 1795 CUDAArchCode = "350"; 1796 break; 1797 case GK_SM37: 1798 CUDAArchCode = "370"; 1799 break; 1800 case GK_SM50: 1801 CUDAArchCode = "500"; 1802 break; 1803 case GK_SM52: 1804 CUDAArchCode = "520"; 1805 break; 1806 case GK_SM53: 1807 CUDAArchCode = "530"; 1808 break; 1809 default: 1810 llvm_unreachable("Unhandled target CPU"); 1811 } 1812 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1813 } 1814 } 1815 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1816 return llvm::makeArrayRef(BuiltinInfo, 1817 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1818 } 1819 bool hasFeature(StringRef Feature) const override { 1820 return Feature == "ptx" || Feature == "nvptx"; 1821 } 1822 1823 ArrayRef<const char *> getGCCRegNames() const override; 1824 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1825 // No aliases. 1826 return None; 1827 } 1828 bool validateAsmConstraint(const char *&Name, 1829 TargetInfo::ConstraintInfo &Info) const override { 1830 switch (*Name) { 1831 default: 1832 return false; 1833 case 'c': 1834 case 'h': 1835 case 'r': 1836 case 'l': 1837 case 'f': 1838 case 'd': 1839 Info.setAllowsRegister(); 1840 return true; 1841 } 1842 } 1843 const char *getClobbers() const override { 1844 // FIXME: Is this really right? 1845 return ""; 1846 } 1847 BuiltinVaListKind getBuiltinVaListKind() const override { 1848 // FIXME: implement 1849 return TargetInfo::CharPtrBuiltinVaList; 1850 } 1851 bool setCPU(const std::string &Name) override { 1852 GPU = llvm::StringSwitch<GPUKind>(Name) 1853 .Case("sm_20", GK_SM20) 1854 .Case("sm_21", GK_SM21) 1855 .Case("sm_30", GK_SM30) 1856 .Case("sm_35", GK_SM35) 1857 .Case("sm_37", GK_SM37) 1858 .Case("sm_50", GK_SM50) 1859 .Case("sm_52", GK_SM52) 1860 .Case("sm_53", GK_SM53) 1861 .Default(GK_NONE); 1862 1863 return GPU != GK_NONE; 1864 } 1865 void setSupportedOpenCLOpts() override { 1866 auto &Opts = getSupportedOpenCLOpts(); 1867 Opts.cl_clang_storage_class_specifiers = 1; 1868 Opts.cl_khr_gl_sharing = 1; 1869 Opts.cl_khr_icd = 1; 1870 1871 Opts.cl_khr_fp64 = 1; 1872 Opts.cl_khr_byte_addressable_store = 1; 1873 Opts.cl_khr_global_int32_base_atomics = 1; 1874 Opts.cl_khr_global_int32_extended_atomics = 1; 1875 Opts.cl_khr_local_int32_base_atomics = 1; 1876 Opts.cl_khr_local_int32_extended_atomics = 1; 1877 } 1878 }; 1879 1880 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1881 #define BUILTIN(ID, TYPE, ATTRS) \ 1882 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1883 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1884 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1885 #include "clang/Basic/BuiltinsNVPTX.def" 1886 }; 1887 1888 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1889 1890 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1891 return llvm::makeArrayRef(GCCRegNames); 1892 } 1893 1894 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1895 public: 1896 NVPTX32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1897 : NVPTXTargetInfo(Triple, Opts) { 1898 LongWidth = LongAlign = 32; 1899 PointerWidth = PointerAlign = 32; 1900 SizeType = TargetInfo::UnsignedInt; 1901 PtrDiffType = TargetInfo::SignedInt; 1902 IntPtrType = TargetInfo::SignedInt; 1903 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1904 } 1905 }; 1906 1907 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1908 public: 1909 NVPTX64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1910 : NVPTXTargetInfo(Triple, Opts) { 1911 PointerWidth = PointerAlign = 64; 1912 SizeType = TargetInfo::UnsignedLong; 1913 PtrDiffType = TargetInfo::SignedLong; 1914 IntPtrType = TargetInfo::SignedLong; 1915 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1916 } 1917 }; 1918 1919 static const unsigned AMDGPUAddrSpaceMap[] = { 1920 1, // opencl_global 1921 3, // opencl_local 1922 2, // opencl_constant 1923 4, // opencl_generic 1924 1, // cuda_device 1925 2, // cuda_constant 1926 3 // cuda_shared 1927 }; 1928 1929 // If you edit the description strings, make sure you update 1930 // getPointerWidthV(). 1931 1932 static const char *const DataLayoutStringR600 = 1933 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1934 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1935 1936 static const char *const DataLayoutStringSI = 1937 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 1938 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1939 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1940 1941 class AMDGPUTargetInfo final : public TargetInfo { 1942 static const Builtin::Info BuiltinInfo[]; 1943 static const char * const GCCRegNames[]; 1944 1945 /// \brief The GPU profiles supported by the AMDGPU target. 1946 enum GPUKind { 1947 GK_NONE, 1948 GK_R600, 1949 GK_R600_DOUBLE_OPS, 1950 GK_R700, 1951 GK_R700_DOUBLE_OPS, 1952 GK_EVERGREEN, 1953 GK_EVERGREEN_DOUBLE_OPS, 1954 GK_NORTHERN_ISLANDS, 1955 GK_CAYMAN, 1956 GK_SOUTHERN_ISLANDS, 1957 GK_SEA_ISLANDS, 1958 GK_VOLCANIC_ISLANDS 1959 } GPU; 1960 1961 bool hasFP64:1; 1962 bool hasFMAF:1; 1963 bool hasLDEXPF:1; 1964 1965 static bool isAMDGCN(const llvm::Triple &TT) { 1966 return TT.getArch() == llvm::Triple::amdgcn; 1967 } 1968 1969 public: 1970 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 1971 : TargetInfo(Triple) , 1972 GPU(isAMDGCN(Triple) ? GK_SOUTHERN_ISLANDS : GK_R600), 1973 hasFP64(false), 1974 hasFMAF(false), 1975 hasLDEXPF(false) { 1976 if (getTriple().getArch() == llvm::Triple::amdgcn) { 1977 hasFP64 = true; 1978 hasFMAF = true; 1979 hasLDEXPF = true; 1980 } 1981 1982 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 1983 DataLayoutStringSI : DataLayoutStringR600); 1984 1985 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1986 UseAddrSpaceMapMangling = true; 1987 } 1988 1989 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1990 if (GPU <= GK_CAYMAN) 1991 return 32; 1992 1993 switch(AddrSpace) { 1994 default: 1995 return 64; 1996 case 0: 1997 case 3: 1998 case 5: 1999 return 32; 2000 } 2001 } 2002 2003 const char * getClobbers() const override { 2004 return ""; 2005 } 2006 2007 ArrayRef<const char *> getGCCRegNames() const override; 2008 2009 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2010 return None; 2011 } 2012 2013 bool validateAsmConstraint(const char *&Name, 2014 TargetInfo::ConstraintInfo &Info) const override { 2015 switch (*Name) { 2016 default: break; 2017 case 'v': // vgpr 2018 case 's': // sgpr 2019 Info.setAllowsRegister(); 2020 return true; 2021 } 2022 return false; 2023 } 2024 2025 bool initFeatureMap(llvm::StringMap<bool> &Features, 2026 DiagnosticsEngine &Diags, StringRef CPU, 2027 const std::vector<std::string> &FeatureVec) const override; 2028 2029 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2030 return llvm::makeArrayRef(BuiltinInfo, 2031 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2032 } 2033 2034 void getTargetDefines(const LangOptions &Opts, 2035 MacroBuilder &Builder) const override { 2036 if (getTriple().getArch() == llvm::Triple::amdgcn) 2037 Builder.defineMacro("__AMDGCN__"); 2038 else 2039 Builder.defineMacro("__R600__"); 2040 2041 if (hasFMAF) 2042 Builder.defineMacro("__HAS_FMAF__"); 2043 if (hasLDEXPF) 2044 Builder.defineMacro("__HAS_LDEXPF__"); 2045 if (hasFP64) 2046 Builder.defineMacro("__HAS_FP64__"); 2047 } 2048 2049 BuiltinVaListKind getBuiltinVaListKind() const override { 2050 return TargetInfo::CharPtrBuiltinVaList; 2051 } 2052 2053 static GPUKind parseR600Name(StringRef Name) { 2054 return llvm::StringSwitch<GPUKind>(Name) 2055 .Case("r600" , GK_R600) 2056 .Case("rv610", GK_R600) 2057 .Case("rv620", GK_R600) 2058 .Case("rv630", GK_R600) 2059 .Case("rv635", GK_R600) 2060 .Case("rs780", GK_R600) 2061 .Case("rs880", GK_R600) 2062 .Case("rv670", GK_R600_DOUBLE_OPS) 2063 .Case("rv710", GK_R700) 2064 .Case("rv730", GK_R700) 2065 .Case("rv740", GK_R700_DOUBLE_OPS) 2066 .Case("rv770", GK_R700_DOUBLE_OPS) 2067 .Case("palm", GK_EVERGREEN) 2068 .Case("cedar", GK_EVERGREEN) 2069 .Case("sumo", GK_EVERGREEN) 2070 .Case("sumo2", GK_EVERGREEN) 2071 .Case("redwood", GK_EVERGREEN) 2072 .Case("juniper", GK_EVERGREEN) 2073 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2074 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2075 .Case("barts", GK_NORTHERN_ISLANDS) 2076 .Case("turks", GK_NORTHERN_ISLANDS) 2077 .Case("caicos", GK_NORTHERN_ISLANDS) 2078 .Case("cayman", GK_CAYMAN) 2079 .Case("aruba", GK_CAYMAN) 2080 .Default(GK_NONE); 2081 } 2082 2083 static GPUKind parseAMDGCNName(StringRef Name) { 2084 return llvm::StringSwitch<GPUKind>(Name) 2085 .Case("tahiti", GK_SOUTHERN_ISLANDS) 2086 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 2087 .Case("verde", GK_SOUTHERN_ISLANDS) 2088 .Case("oland", GK_SOUTHERN_ISLANDS) 2089 .Case("hainan", GK_SOUTHERN_ISLANDS) 2090 .Case("bonaire", GK_SEA_ISLANDS) 2091 .Case("kabini", GK_SEA_ISLANDS) 2092 .Case("kaveri", GK_SEA_ISLANDS) 2093 .Case("hawaii", GK_SEA_ISLANDS) 2094 .Case("mullins", GK_SEA_ISLANDS) 2095 .Case("tonga", GK_VOLCANIC_ISLANDS) 2096 .Case("iceland", GK_VOLCANIC_ISLANDS) 2097 .Case("carrizo", GK_VOLCANIC_ISLANDS) 2098 .Case("fiji", GK_VOLCANIC_ISLANDS) 2099 .Case("stoney", GK_VOLCANIC_ISLANDS) 2100 .Default(GK_NONE); 2101 } 2102 2103 bool setCPU(const std::string &Name) override { 2104 if (getTriple().getArch() == llvm::Triple::amdgcn) 2105 GPU = parseAMDGCNName(Name); 2106 else 2107 GPU = parseR600Name(Name); 2108 2109 return GPU != GK_NONE; 2110 } 2111 2112 void setSupportedOpenCLOpts() override { 2113 auto &Opts = getSupportedOpenCLOpts(); 2114 Opts.cl_clang_storage_class_specifiers = 1; 2115 Opts.cl_khr_icd = 1; 2116 2117 if (hasFP64) 2118 Opts.cl_khr_fp64 = 1; 2119 if (GPU >= GK_EVERGREEN) { 2120 Opts.cl_khr_byte_addressable_store = 1; 2121 Opts.cl_khr_global_int32_base_atomics = 1; 2122 Opts.cl_khr_global_int32_extended_atomics = 1; 2123 Opts.cl_khr_local_int32_base_atomics = 1; 2124 Opts.cl_khr_local_int32_extended_atomics = 1; 2125 } 2126 if (GPU >= GK_SOUTHERN_ISLANDS) { 2127 Opts.cl_khr_fp16 = 1; 2128 Opts.cl_khr_int64_base_atomics = 1; 2129 Opts.cl_khr_int64_extended_atomics = 1; 2130 Opts.cl_khr_3d_image_writes = 1; 2131 } 2132 } 2133 }; 2134 2135 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2136 #define BUILTIN(ID, TYPE, ATTRS) \ 2137 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2138 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2139 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2140 #include "clang/Basic/BuiltinsAMDGPU.def" 2141 }; 2142 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2143 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2144 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2145 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2146 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2147 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2148 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2149 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2150 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2151 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2152 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2153 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2154 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2155 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2156 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2157 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2158 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2159 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2160 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2161 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2162 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2163 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2164 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2165 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2166 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2167 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2168 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2169 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2170 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2171 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2172 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2173 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2174 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2175 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2176 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2177 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2178 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2179 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2180 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2181 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2182 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2183 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2184 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2185 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2186 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2187 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2188 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2189 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2190 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2191 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2192 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2193 }; 2194 2195 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2196 return llvm::makeArrayRef(GCCRegNames); 2197 } 2198 2199 bool AMDGPUTargetInfo::initFeatureMap( 2200 llvm::StringMap<bool> &Features, 2201 DiagnosticsEngine &Diags, StringRef CPU, 2202 const std::vector<std::string> &FeatureVec) const { 2203 2204 // XXX - What does the member GPU mean if device name string passed here? 2205 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2206 if (CPU.empty()) 2207 CPU = "tahiti"; 2208 2209 switch (parseAMDGCNName(CPU)) { 2210 case GK_SOUTHERN_ISLANDS: 2211 case GK_SEA_ISLANDS: 2212 break; 2213 2214 case GK_VOLCANIC_ISLANDS: 2215 Features["s-memrealtime"] = true; 2216 Features["16-bit-insts"] = true; 2217 break; 2218 2219 case GK_NONE: 2220 return false; 2221 default: 2222 llvm_unreachable("unhandled subtarget"); 2223 } 2224 } else { 2225 if (CPU.empty()) 2226 CPU = "r600"; 2227 2228 switch (parseR600Name(CPU)) { 2229 case GK_R600: 2230 case GK_R700: 2231 case GK_EVERGREEN: 2232 case GK_NORTHERN_ISLANDS: 2233 break; 2234 case GK_R600_DOUBLE_OPS: 2235 case GK_R700_DOUBLE_OPS: 2236 case GK_EVERGREEN_DOUBLE_OPS: 2237 case GK_CAYMAN: 2238 Features["fp64"] = true; 2239 break; 2240 case GK_NONE: 2241 return false; 2242 default: 2243 llvm_unreachable("unhandled subtarget"); 2244 } 2245 } 2246 2247 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2248 } 2249 2250 // Namespace for x86 abstract base class 2251 const Builtin::Info BuiltinInfo[] = { 2252 #define BUILTIN(ID, TYPE, ATTRS) \ 2253 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2254 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2255 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2256 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2257 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2258 #include "clang/Basic/BuiltinsX86.def" 2259 }; 2260 2261 static const char* const GCCRegNames[] = { 2262 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2263 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2264 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2265 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2266 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2267 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2268 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2269 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2270 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2271 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2272 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2273 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2274 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2275 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2276 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2277 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2278 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2279 }; 2280 2281 const TargetInfo::AddlRegName AddlRegNames[] = { 2282 { { "al", "ah", "eax", "rax" }, 0 }, 2283 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2284 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2285 { { "dl", "dh", "edx", "rdx" }, 1 }, 2286 { { "esi", "rsi" }, 4 }, 2287 { { "edi", "rdi" }, 5 }, 2288 { { "esp", "rsp" }, 7 }, 2289 { { "ebp", "rbp" }, 6 }, 2290 { { "r8d", "r8w", "r8b" }, 38 }, 2291 { { "r9d", "r9w", "r9b" }, 39 }, 2292 { { "r10d", "r10w", "r10b" }, 40 }, 2293 { { "r11d", "r11w", "r11b" }, 41 }, 2294 { { "r12d", "r12w", "r12b" }, 42 }, 2295 { { "r13d", "r13w", "r13b" }, 43 }, 2296 { { "r14d", "r14w", "r14b" }, 44 }, 2297 { { "r15d", "r15w", "r15b" }, 45 }, 2298 }; 2299 2300 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2301 // most of the implementation can be shared. 2302 class X86TargetInfo : public TargetInfo { 2303 enum X86SSEEnum { 2304 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2305 } SSELevel = NoSSE; 2306 enum MMX3DNowEnum { 2307 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2308 } MMX3DNowLevel = NoMMX3DNow; 2309 enum XOPEnum { 2310 NoXOP, 2311 SSE4A, 2312 FMA4, 2313 XOP 2314 } XOPLevel = NoXOP; 2315 2316 bool HasAES = false; 2317 bool HasPCLMUL = false; 2318 bool HasLZCNT = false; 2319 bool HasRDRND = false; 2320 bool HasFSGSBASE = false; 2321 bool HasBMI = false; 2322 bool HasBMI2 = false; 2323 bool HasPOPCNT = false; 2324 bool HasRTM = false; 2325 bool HasPRFCHW = false; 2326 bool HasRDSEED = false; 2327 bool HasADX = false; 2328 bool HasTBM = false; 2329 bool HasFMA = false; 2330 bool HasF16C = false; 2331 bool HasAVX512CD = false; 2332 bool HasAVX512ER = false; 2333 bool HasAVX512PF = false; 2334 bool HasAVX512DQ = false; 2335 bool HasAVX512BW = false; 2336 bool HasAVX512VL = false; 2337 bool HasAVX512VBMI = false; 2338 bool HasAVX512IFMA = false; 2339 bool HasSHA = false; 2340 bool HasMPX = false; 2341 bool HasSGX = false; 2342 bool HasCX16 = false; 2343 bool HasFXSR = false; 2344 bool HasXSAVE = false; 2345 bool HasXSAVEOPT = false; 2346 bool HasXSAVEC = false; 2347 bool HasXSAVES = false; 2348 bool HasMWAITX = false; 2349 bool HasPKU = false; 2350 bool HasCLFLUSHOPT = false; 2351 bool HasPCOMMIT = false; 2352 bool HasCLWB = false; 2353 bool HasUMIP = false; 2354 bool HasMOVBE = false; 2355 bool HasPREFETCHWT1 = false; 2356 2357 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2358 /// 2359 /// Each enumeration represents a particular CPU supported by Clang. These 2360 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2361 enum CPUKind { 2362 CK_Generic, 2363 2364 /// \name i386 2365 /// i386-generation processors. 2366 //@{ 2367 CK_i386, 2368 //@} 2369 2370 /// \name i486 2371 /// i486-generation processors. 2372 //@{ 2373 CK_i486, 2374 CK_WinChipC6, 2375 CK_WinChip2, 2376 CK_C3, 2377 //@} 2378 2379 /// \name i586 2380 /// i586-generation processors, P5 microarchitecture based. 2381 //@{ 2382 CK_i586, 2383 CK_Pentium, 2384 CK_PentiumMMX, 2385 //@} 2386 2387 /// \name i686 2388 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2389 //@{ 2390 CK_i686, 2391 CK_PentiumPro, 2392 CK_Pentium2, 2393 CK_Pentium3, 2394 CK_Pentium3M, 2395 CK_PentiumM, 2396 CK_C3_2, 2397 2398 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2399 /// Clang however has some logic to suport this. 2400 // FIXME: Warn, deprecate, and potentially remove this. 2401 CK_Yonah, 2402 //@} 2403 2404 /// \name Netburst 2405 /// Netburst microarchitecture based processors. 2406 //@{ 2407 CK_Pentium4, 2408 CK_Pentium4M, 2409 CK_Prescott, 2410 CK_Nocona, 2411 //@} 2412 2413 /// \name Core 2414 /// Core microarchitecture based processors. 2415 //@{ 2416 CK_Core2, 2417 2418 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2419 /// codename which GCC no longer accepts as an option to -march, but Clang 2420 /// has some logic for recognizing it. 2421 // FIXME: Warn, deprecate, and potentially remove this. 2422 CK_Penryn, 2423 //@} 2424 2425 /// \name Atom 2426 /// Atom processors 2427 //@{ 2428 CK_Bonnell, 2429 CK_Silvermont, 2430 //@} 2431 2432 /// \name Nehalem 2433 /// Nehalem microarchitecture based processors. 2434 CK_Nehalem, 2435 2436 /// \name Westmere 2437 /// Westmere microarchitecture based processors. 2438 CK_Westmere, 2439 2440 /// \name Sandy Bridge 2441 /// Sandy Bridge microarchitecture based processors. 2442 CK_SandyBridge, 2443 2444 /// \name Ivy Bridge 2445 /// Ivy Bridge microarchitecture based processors. 2446 CK_IvyBridge, 2447 2448 /// \name Haswell 2449 /// Haswell microarchitecture based processors. 2450 CK_Haswell, 2451 2452 /// \name Broadwell 2453 /// Broadwell microarchitecture based processors. 2454 CK_Broadwell, 2455 2456 /// \name Skylake Client 2457 /// Skylake client microarchitecture based processors. 2458 CK_SkylakeClient, 2459 2460 /// \name Skylake Server 2461 /// Skylake server microarchitecture based processors. 2462 CK_SkylakeServer, 2463 2464 /// \name Cannonlake Client 2465 /// Cannonlake client microarchitecture based processors. 2466 CK_Cannonlake, 2467 2468 /// \name Knights Landing 2469 /// Knights Landing processor. 2470 CK_KNL, 2471 2472 /// \name Lakemont 2473 /// Lakemont microarchitecture based processors. 2474 CK_Lakemont, 2475 2476 /// \name K6 2477 /// K6 architecture processors. 2478 //@{ 2479 CK_K6, 2480 CK_K6_2, 2481 CK_K6_3, 2482 //@} 2483 2484 /// \name K7 2485 /// K7 architecture processors. 2486 //@{ 2487 CK_Athlon, 2488 CK_AthlonThunderbird, 2489 CK_Athlon4, 2490 CK_AthlonXP, 2491 CK_AthlonMP, 2492 //@} 2493 2494 /// \name K8 2495 /// K8 architecture processors. 2496 //@{ 2497 CK_Athlon64, 2498 CK_Athlon64SSE3, 2499 CK_AthlonFX, 2500 CK_K8, 2501 CK_K8SSE3, 2502 CK_Opteron, 2503 CK_OpteronSSE3, 2504 CK_AMDFAM10, 2505 //@} 2506 2507 /// \name Bobcat 2508 /// Bobcat architecture processors. 2509 //@{ 2510 CK_BTVER1, 2511 CK_BTVER2, 2512 //@} 2513 2514 /// \name Bulldozer 2515 /// Bulldozer architecture processors. 2516 //@{ 2517 CK_BDVER1, 2518 CK_BDVER2, 2519 CK_BDVER3, 2520 CK_BDVER4, 2521 //@} 2522 2523 /// This specification is deprecated and will be removed in the future. 2524 /// Users should prefer \see CK_K8. 2525 // FIXME: Warn on this when the CPU is set to it. 2526 //@{ 2527 CK_x86_64, 2528 //@} 2529 2530 /// \name Geode 2531 /// Geode processors. 2532 //@{ 2533 CK_Geode 2534 //@} 2535 } CPU = CK_Generic; 2536 2537 CPUKind getCPUKind(StringRef CPU) const { 2538 return llvm::StringSwitch<CPUKind>(CPU) 2539 .Case("i386", CK_i386) 2540 .Case("i486", CK_i486) 2541 .Case("winchip-c6", CK_WinChipC6) 2542 .Case("winchip2", CK_WinChip2) 2543 .Case("c3", CK_C3) 2544 .Case("i586", CK_i586) 2545 .Case("pentium", CK_Pentium) 2546 .Case("pentium-mmx", CK_PentiumMMX) 2547 .Case("i686", CK_i686) 2548 .Case("pentiumpro", CK_PentiumPro) 2549 .Case("pentium2", CK_Pentium2) 2550 .Case("pentium3", CK_Pentium3) 2551 .Case("pentium3m", CK_Pentium3M) 2552 .Case("pentium-m", CK_PentiumM) 2553 .Case("c3-2", CK_C3_2) 2554 .Case("yonah", CK_Yonah) 2555 .Case("pentium4", CK_Pentium4) 2556 .Case("pentium4m", CK_Pentium4M) 2557 .Case("prescott", CK_Prescott) 2558 .Case("nocona", CK_Nocona) 2559 .Case("core2", CK_Core2) 2560 .Case("penryn", CK_Penryn) 2561 .Case("bonnell", CK_Bonnell) 2562 .Case("atom", CK_Bonnell) // Legacy name. 2563 .Case("silvermont", CK_Silvermont) 2564 .Case("slm", CK_Silvermont) // Legacy name. 2565 .Case("nehalem", CK_Nehalem) 2566 .Case("corei7", CK_Nehalem) // Legacy name. 2567 .Case("westmere", CK_Westmere) 2568 .Case("sandybridge", CK_SandyBridge) 2569 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2570 .Case("ivybridge", CK_IvyBridge) 2571 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2572 .Case("haswell", CK_Haswell) 2573 .Case("core-avx2", CK_Haswell) // Legacy name. 2574 .Case("broadwell", CK_Broadwell) 2575 .Case("skylake", CK_SkylakeClient) 2576 .Case("skylake-avx512", CK_SkylakeServer) 2577 .Case("skx", CK_SkylakeServer) // Legacy name. 2578 .Case("cannonlake", CK_Cannonlake) 2579 .Case("knl", CK_KNL) 2580 .Case("lakemont", CK_Lakemont) 2581 .Case("k6", CK_K6) 2582 .Case("k6-2", CK_K6_2) 2583 .Case("k6-3", CK_K6_3) 2584 .Case("athlon", CK_Athlon) 2585 .Case("athlon-tbird", CK_AthlonThunderbird) 2586 .Case("athlon-4", CK_Athlon4) 2587 .Case("athlon-xp", CK_AthlonXP) 2588 .Case("athlon-mp", CK_AthlonMP) 2589 .Case("athlon64", CK_Athlon64) 2590 .Case("athlon64-sse3", CK_Athlon64SSE3) 2591 .Case("athlon-fx", CK_AthlonFX) 2592 .Case("k8", CK_K8) 2593 .Case("k8-sse3", CK_K8SSE3) 2594 .Case("opteron", CK_Opteron) 2595 .Case("opteron-sse3", CK_OpteronSSE3) 2596 .Case("barcelona", CK_AMDFAM10) 2597 .Case("amdfam10", CK_AMDFAM10) 2598 .Case("btver1", CK_BTVER1) 2599 .Case("btver2", CK_BTVER2) 2600 .Case("bdver1", CK_BDVER1) 2601 .Case("bdver2", CK_BDVER2) 2602 .Case("bdver3", CK_BDVER3) 2603 .Case("bdver4", CK_BDVER4) 2604 .Case("x86-64", CK_x86_64) 2605 .Case("geode", CK_Geode) 2606 .Default(CK_Generic); 2607 } 2608 2609 enum FPMathKind { 2610 FP_Default, 2611 FP_SSE, 2612 FP_387 2613 } FPMath = FP_Default; 2614 2615 public: 2616 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2617 : TargetInfo(Triple) { 2618 BigEndian = false; 2619 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2620 } 2621 unsigned getFloatEvalMethod() const override { 2622 // X87 evaluates with 80 bits "long double" precision. 2623 return SSELevel == NoSSE ? 2 : 0; 2624 } 2625 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2626 return llvm::makeArrayRef(BuiltinInfo, 2627 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2628 } 2629 ArrayRef<const char *> getGCCRegNames() const override { 2630 return llvm::makeArrayRef(GCCRegNames); 2631 } 2632 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2633 return None; 2634 } 2635 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2636 return llvm::makeArrayRef(AddlRegNames); 2637 } 2638 bool validateCpuSupports(StringRef Name) const override; 2639 bool validateAsmConstraint(const char *&Name, 2640 TargetInfo::ConstraintInfo &info) const override; 2641 2642 bool validateGlobalRegisterVariable(StringRef RegName, 2643 unsigned RegSize, 2644 bool &HasSizeMismatch) const override { 2645 // esp and ebp are the only 32-bit registers the x86 backend can currently 2646 // handle. 2647 if (RegName.equals("esp") || RegName.equals("ebp")) { 2648 // Check that the register size is 32-bit. 2649 HasSizeMismatch = RegSize != 32; 2650 return true; 2651 } 2652 2653 return false; 2654 } 2655 2656 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2657 2658 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2659 2660 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2661 2662 std::string convertConstraint(const char *&Constraint) const override; 2663 const char *getClobbers() const override { 2664 return "~{dirflag},~{fpsr},~{flags}"; 2665 } 2666 void getTargetDefines(const LangOptions &Opts, 2667 MacroBuilder &Builder) const override; 2668 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2669 bool Enabled); 2670 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2671 bool Enabled); 2672 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2673 bool Enabled); 2674 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2675 StringRef Name, bool Enabled) const override { 2676 setFeatureEnabledImpl(Features, Name, Enabled); 2677 } 2678 // This exists purely to cut down on the number of virtual calls in 2679 // initFeatureMap which calls this repeatedly. 2680 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2681 StringRef Name, bool Enabled); 2682 bool 2683 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2684 StringRef CPU, 2685 const std::vector<std::string> &FeaturesVec) const override; 2686 bool hasFeature(StringRef Feature) const override; 2687 bool handleTargetFeatures(std::vector<std::string> &Features, 2688 DiagnosticsEngine &Diags) override; 2689 StringRef getABI() const override { 2690 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2691 return "avx512"; 2692 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2693 return "avx"; 2694 if (getTriple().getArch() == llvm::Triple::x86 && 2695 MMX3DNowLevel == NoMMX3DNow) 2696 return "no-mmx"; 2697 return ""; 2698 } 2699 bool setCPU(const std::string &Name) override { 2700 CPU = getCPUKind(Name); 2701 2702 // Perform any per-CPU checks necessary to determine if this CPU is 2703 // acceptable. 2704 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2705 // invalid without explaining *why*. 2706 switch (CPU) { 2707 case CK_Generic: 2708 // No processor selected! 2709 return false; 2710 2711 case CK_i386: 2712 case CK_i486: 2713 case CK_WinChipC6: 2714 case CK_WinChip2: 2715 case CK_C3: 2716 case CK_i586: 2717 case CK_Pentium: 2718 case CK_PentiumMMX: 2719 case CK_i686: 2720 case CK_PentiumPro: 2721 case CK_Pentium2: 2722 case CK_Pentium3: 2723 case CK_Pentium3M: 2724 case CK_PentiumM: 2725 case CK_Yonah: 2726 case CK_C3_2: 2727 case CK_Pentium4: 2728 case CK_Pentium4M: 2729 case CK_Lakemont: 2730 case CK_Prescott: 2731 case CK_K6: 2732 case CK_K6_2: 2733 case CK_K6_3: 2734 case CK_Athlon: 2735 case CK_AthlonThunderbird: 2736 case CK_Athlon4: 2737 case CK_AthlonXP: 2738 case CK_AthlonMP: 2739 case CK_Geode: 2740 // Only accept certain architectures when compiling in 32-bit mode. 2741 if (getTriple().getArch() != llvm::Triple::x86) 2742 return false; 2743 2744 // Fallthrough 2745 case CK_Nocona: 2746 case CK_Core2: 2747 case CK_Penryn: 2748 case CK_Bonnell: 2749 case CK_Silvermont: 2750 case CK_Nehalem: 2751 case CK_Westmere: 2752 case CK_SandyBridge: 2753 case CK_IvyBridge: 2754 case CK_Haswell: 2755 case CK_Broadwell: 2756 case CK_SkylakeClient: 2757 case CK_SkylakeServer: 2758 case CK_Cannonlake: 2759 case CK_KNL: 2760 case CK_Athlon64: 2761 case CK_Athlon64SSE3: 2762 case CK_AthlonFX: 2763 case CK_K8: 2764 case CK_K8SSE3: 2765 case CK_Opteron: 2766 case CK_OpteronSSE3: 2767 case CK_AMDFAM10: 2768 case CK_BTVER1: 2769 case CK_BTVER2: 2770 case CK_BDVER1: 2771 case CK_BDVER2: 2772 case CK_BDVER3: 2773 case CK_BDVER4: 2774 case CK_x86_64: 2775 return true; 2776 } 2777 llvm_unreachable("Unhandled CPU kind"); 2778 } 2779 2780 bool setFPMath(StringRef Name) override; 2781 2782 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2783 // Most of the non-ARM calling conventions are i386 conventions. 2784 switch (CC) { 2785 case CC_X86ThisCall: 2786 case CC_X86FastCall: 2787 case CC_X86StdCall: 2788 case CC_X86VectorCall: 2789 case CC_C: 2790 case CC_Swift: 2791 case CC_X86Pascal: 2792 case CC_IntelOclBicc: 2793 return CCCR_OK; 2794 default: 2795 return CCCR_Warning; 2796 } 2797 } 2798 2799 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2800 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2801 } 2802 2803 bool hasSjLjLowering() const override { 2804 return true; 2805 } 2806 2807 void setSupportedOpenCLOpts() override { 2808 getSupportedOpenCLOpts().setAll(); 2809 } 2810 }; 2811 2812 bool X86TargetInfo::setFPMath(StringRef Name) { 2813 if (Name == "387") { 2814 FPMath = FP_387; 2815 return true; 2816 } 2817 if (Name == "sse") { 2818 FPMath = FP_SSE; 2819 return true; 2820 } 2821 return false; 2822 } 2823 2824 bool X86TargetInfo::initFeatureMap( 2825 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2826 const std::vector<std::string> &FeaturesVec) const { 2827 // FIXME: This *really* should not be here. 2828 // X86_64 always has SSE2. 2829 if (getTriple().getArch() == llvm::Triple::x86_64) 2830 setFeatureEnabledImpl(Features, "sse2", true); 2831 2832 const CPUKind Kind = getCPUKind(CPU); 2833 2834 // Enable X87 for all X86 processors but Lakemont. 2835 if (Kind != CK_Lakemont) 2836 setFeatureEnabledImpl(Features, "x87", true); 2837 2838 switch (Kind) { 2839 case CK_Generic: 2840 case CK_i386: 2841 case CK_i486: 2842 case CK_i586: 2843 case CK_Pentium: 2844 case CK_i686: 2845 case CK_PentiumPro: 2846 case CK_Lakemont: 2847 break; 2848 case CK_PentiumMMX: 2849 case CK_Pentium2: 2850 case CK_K6: 2851 case CK_WinChipC6: 2852 setFeatureEnabledImpl(Features, "mmx", true); 2853 break; 2854 case CK_Pentium3: 2855 case CK_Pentium3M: 2856 case CK_C3_2: 2857 setFeatureEnabledImpl(Features, "sse", true); 2858 setFeatureEnabledImpl(Features, "fxsr", true); 2859 break; 2860 case CK_PentiumM: 2861 case CK_Pentium4: 2862 case CK_Pentium4M: 2863 case CK_x86_64: 2864 setFeatureEnabledImpl(Features, "sse2", true); 2865 setFeatureEnabledImpl(Features, "fxsr", true); 2866 break; 2867 case CK_Yonah: 2868 case CK_Prescott: 2869 case CK_Nocona: 2870 setFeatureEnabledImpl(Features, "sse3", true); 2871 setFeatureEnabledImpl(Features, "fxsr", true); 2872 setFeatureEnabledImpl(Features, "cx16", true); 2873 break; 2874 case CK_Core2: 2875 case CK_Bonnell: 2876 setFeatureEnabledImpl(Features, "ssse3", true); 2877 setFeatureEnabledImpl(Features, "fxsr", true); 2878 setFeatureEnabledImpl(Features, "cx16", true); 2879 break; 2880 case CK_Penryn: 2881 setFeatureEnabledImpl(Features, "sse4.1", true); 2882 setFeatureEnabledImpl(Features, "fxsr", true); 2883 setFeatureEnabledImpl(Features, "cx16", true); 2884 break; 2885 case CK_Cannonlake: 2886 setFeatureEnabledImpl(Features, "avx512ifma", true); 2887 setFeatureEnabledImpl(Features, "avx512vbmi", true); 2888 setFeatureEnabledImpl(Features, "sha", true); 2889 setFeatureEnabledImpl(Features, "umip", true); 2890 // FALLTHROUGH 2891 case CK_SkylakeServer: 2892 setFeatureEnabledImpl(Features, "avx512f", true); 2893 setFeatureEnabledImpl(Features, "avx512cd", true); 2894 setFeatureEnabledImpl(Features, "avx512dq", true); 2895 setFeatureEnabledImpl(Features, "avx512bw", true); 2896 setFeatureEnabledImpl(Features, "avx512vl", true); 2897 setFeatureEnabledImpl(Features, "pku", true); 2898 setFeatureEnabledImpl(Features, "pcommit", true); 2899 setFeatureEnabledImpl(Features, "clwb", true); 2900 // FALLTHROUGH 2901 case CK_SkylakeClient: 2902 setFeatureEnabledImpl(Features, "xsavec", true); 2903 setFeatureEnabledImpl(Features, "xsaves", true); 2904 setFeatureEnabledImpl(Features, "mpx", true); 2905 setFeatureEnabledImpl(Features, "sgx", true); 2906 setFeatureEnabledImpl(Features, "clflushopt", true); 2907 // FALLTHROUGH 2908 case CK_Broadwell: 2909 setFeatureEnabledImpl(Features, "rdseed", true); 2910 setFeatureEnabledImpl(Features, "adx", true); 2911 // FALLTHROUGH 2912 case CK_Haswell: 2913 setFeatureEnabledImpl(Features, "avx2", true); 2914 setFeatureEnabledImpl(Features, "lzcnt", true); 2915 setFeatureEnabledImpl(Features, "bmi", true); 2916 setFeatureEnabledImpl(Features, "bmi2", true); 2917 setFeatureEnabledImpl(Features, "rtm", true); 2918 setFeatureEnabledImpl(Features, "fma", true); 2919 setFeatureEnabledImpl(Features, "movbe", true); 2920 // FALLTHROUGH 2921 case CK_IvyBridge: 2922 setFeatureEnabledImpl(Features, "rdrnd", true); 2923 setFeatureEnabledImpl(Features, "f16c", true); 2924 setFeatureEnabledImpl(Features, "fsgsbase", true); 2925 // FALLTHROUGH 2926 case CK_SandyBridge: 2927 setFeatureEnabledImpl(Features, "avx", true); 2928 setFeatureEnabledImpl(Features, "xsave", true); 2929 setFeatureEnabledImpl(Features, "xsaveopt", true); 2930 // FALLTHROUGH 2931 case CK_Westmere: 2932 case CK_Silvermont: 2933 setFeatureEnabledImpl(Features, "aes", true); 2934 setFeatureEnabledImpl(Features, "pclmul", true); 2935 // FALLTHROUGH 2936 case CK_Nehalem: 2937 setFeatureEnabledImpl(Features, "sse4.2", true); 2938 setFeatureEnabledImpl(Features, "fxsr", true); 2939 setFeatureEnabledImpl(Features, "cx16", true); 2940 break; 2941 case CK_KNL: 2942 setFeatureEnabledImpl(Features, "avx512f", true); 2943 setFeatureEnabledImpl(Features, "avx512cd", true); 2944 setFeatureEnabledImpl(Features, "avx512er", true); 2945 setFeatureEnabledImpl(Features, "avx512pf", true); 2946 setFeatureEnabledImpl(Features, "prefetchwt1", true); 2947 setFeatureEnabledImpl(Features, "fxsr", true); 2948 setFeatureEnabledImpl(Features, "rdseed", true); 2949 setFeatureEnabledImpl(Features, "adx", true); 2950 setFeatureEnabledImpl(Features, "lzcnt", true); 2951 setFeatureEnabledImpl(Features, "bmi", true); 2952 setFeatureEnabledImpl(Features, "bmi2", true); 2953 setFeatureEnabledImpl(Features, "rtm", true); 2954 setFeatureEnabledImpl(Features, "fma", true); 2955 setFeatureEnabledImpl(Features, "rdrnd", true); 2956 setFeatureEnabledImpl(Features, "f16c", true); 2957 setFeatureEnabledImpl(Features, "fsgsbase", true); 2958 setFeatureEnabledImpl(Features, "aes", true); 2959 setFeatureEnabledImpl(Features, "pclmul", true); 2960 setFeatureEnabledImpl(Features, "cx16", true); 2961 setFeatureEnabledImpl(Features, "xsaveopt", true); 2962 setFeatureEnabledImpl(Features, "xsave", true); 2963 setFeatureEnabledImpl(Features, "movbe", true); 2964 break; 2965 case CK_K6_2: 2966 case CK_K6_3: 2967 case CK_WinChip2: 2968 case CK_C3: 2969 setFeatureEnabledImpl(Features, "3dnow", true); 2970 break; 2971 case CK_Athlon: 2972 case CK_AthlonThunderbird: 2973 case CK_Geode: 2974 setFeatureEnabledImpl(Features, "3dnowa", true); 2975 break; 2976 case CK_Athlon4: 2977 case CK_AthlonXP: 2978 case CK_AthlonMP: 2979 setFeatureEnabledImpl(Features, "sse", true); 2980 setFeatureEnabledImpl(Features, "3dnowa", true); 2981 setFeatureEnabledImpl(Features, "fxsr", true); 2982 break; 2983 case CK_K8: 2984 case CK_Opteron: 2985 case CK_Athlon64: 2986 case CK_AthlonFX: 2987 setFeatureEnabledImpl(Features, "sse2", true); 2988 setFeatureEnabledImpl(Features, "3dnowa", true); 2989 setFeatureEnabledImpl(Features, "fxsr", true); 2990 break; 2991 case CK_AMDFAM10: 2992 setFeatureEnabledImpl(Features, "sse4a", true); 2993 setFeatureEnabledImpl(Features, "lzcnt", true); 2994 setFeatureEnabledImpl(Features, "popcnt", true); 2995 // FALLTHROUGH 2996 case CK_K8SSE3: 2997 case CK_OpteronSSE3: 2998 case CK_Athlon64SSE3: 2999 setFeatureEnabledImpl(Features, "sse3", true); 3000 setFeatureEnabledImpl(Features, "3dnowa", true); 3001 setFeatureEnabledImpl(Features, "fxsr", true); 3002 break; 3003 case CK_BTVER2: 3004 setFeatureEnabledImpl(Features, "avx", true); 3005 setFeatureEnabledImpl(Features, "aes", true); 3006 setFeatureEnabledImpl(Features, "pclmul", true); 3007 setFeatureEnabledImpl(Features, "bmi", true); 3008 setFeatureEnabledImpl(Features, "f16c", true); 3009 setFeatureEnabledImpl(Features, "xsaveopt", true); 3010 // FALLTHROUGH 3011 case CK_BTVER1: 3012 setFeatureEnabledImpl(Features, "ssse3", true); 3013 setFeatureEnabledImpl(Features, "sse4a", true); 3014 setFeatureEnabledImpl(Features, "lzcnt", true); 3015 setFeatureEnabledImpl(Features, "popcnt", true); 3016 setFeatureEnabledImpl(Features, "prfchw", true); 3017 setFeatureEnabledImpl(Features, "cx16", true); 3018 setFeatureEnabledImpl(Features, "fxsr", true); 3019 break; 3020 case CK_BDVER4: 3021 setFeatureEnabledImpl(Features, "avx2", true); 3022 setFeatureEnabledImpl(Features, "bmi2", true); 3023 setFeatureEnabledImpl(Features, "mwaitx", true); 3024 // FALLTHROUGH 3025 case CK_BDVER3: 3026 setFeatureEnabledImpl(Features, "fsgsbase", true); 3027 setFeatureEnabledImpl(Features, "xsaveopt", true); 3028 // FALLTHROUGH 3029 case CK_BDVER2: 3030 setFeatureEnabledImpl(Features, "bmi", true); 3031 setFeatureEnabledImpl(Features, "fma", true); 3032 setFeatureEnabledImpl(Features, "f16c", true); 3033 setFeatureEnabledImpl(Features, "tbm", true); 3034 // FALLTHROUGH 3035 case CK_BDVER1: 3036 // xop implies avx, sse4a and fma4. 3037 setFeatureEnabledImpl(Features, "xop", true); 3038 setFeatureEnabledImpl(Features, "lzcnt", true); 3039 setFeatureEnabledImpl(Features, "aes", true); 3040 setFeatureEnabledImpl(Features, "pclmul", true); 3041 setFeatureEnabledImpl(Features, "prfchw", true); 3042 setFeatureEnabledImpl(Features, "cx16", true); 3043 setFeatureEnabledImpl(Features, "fxsr", true); 3044 setFeatureEnabledImpl(Features, "xsave", true); 3045 break; 3046 } 3047 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3048 return false; 3049 3050 // Can't do this earlier because we need to be able to explicitly enable 3051 // or disable these features and the things that they depend upon. 3052 3053 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3054 auto I = Features.find("sse4.2"); 3055 if (I != Features.end() && I->getValue() && 3056 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3057 FeaturesVec.end()) 3058 Features["popcnt"] = true; 3059 3060 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3061 I = Features.find("3dnow"); 3062 if (I != Features.end() && I->getValue() && 3063 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3064 FeaturesVec.end()) 3065 Features["prfchw"] = true; 3066 3067 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3068 // then enable MMX. 3069 I = Features.find("sse"); 3070 if (I != Features.end() && I->getValue() && 3071 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3072 FeaturesVec.end()) 3073 Features["mmx"] = true; 3074 3075 return true; 3076 } 3077 3078 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3079 X86SSEEnum Level, bool Enabled) { 3080 if (Enabled) { 3081 switch (Level) { 3082 case AVX512F: 3083 Features["avx512f"] = true; 3084 case AVX2: 3085 Features["avx2"] = true; 3086 case AVX: 3087 Features["avx"] = true; 3088 Features["xsave"] = true; 3089 case SSE42: 3090 Features["sse4.2"] = true; 3091 case SSE41: 3092 Features["sse4.1"] = true; 3093 case SSSE3: 3094 Features["ssse3"] = true; 3095 case SSE3: 3096 Features["sse3"] = true; 3097 case SSE2: 3098 Features["sse2"] = true; 3099 case SSE1: 3100 Features["sse"] = true; 3101 case NoSSE: 3102 break; 3103 } 3104 return; 3105 } 3106 3107 switch (Level) { 3108 case NoSSE: 3109 case SSE1: 3110 Features["sse"] = false; 3111 case SSE2: 3112 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3113 Features["sha"] = false; 3114 case SSE3: 3115 Features["sse3"] = false; 3116 setXOPLevel(Features, NoXOP, false); 3117 case SSSE3: 3118 Features["ssse3"] = false; 3119 case SSE41: 3120 Features["sse4.1"] = false; 3121 case SSE42: 3122 Features["sse4.2"] = false; 3123 case AVX: 3124 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3125 Features["xsaveopt"] = false; 3126 setXOPLevel(Features, FMA4, false); 3127 case AVX2: 3128 Features["avx2"] = false; 3129 case AVX512F: 3130 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3131 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3132 Features["avx512vl"] = Features["avx512vbmi"] = 3133 Features["avx512ifma"] = false; 3134 } 3135 } 3136 3137 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3138 MMX3DNowEnum Level, bool Enabled) { 3139 if (Enabled) { 3140 switch (Level) { 3141 case AMD3DNowAthlon: 3142 Features["3dnowa"] = true; 3143 case AMD3DNow: 3144 Features["3dnow"] = true; 3145 case MMX: 3146 Features["mmx"] = true; 3147 case NoMMX3DNow: 3148 break; 3149 } 3150 return; 3151 } 3152 3153 switch (Level) { 3154 case NoMMX3DNow: 3155 case MMX: 3156 Features["mmx"] = false; 3157 case AMD3DNow: 3158 Features["3dnow"] = false; 3159 case AMD3DNowAthlon: 3160 Features["3dnowa"] = false; 3161 } 3162 } 3163 3164 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3165 bool Enabled) { 3166 if (Enabled) { 3167 switch (Level) { 3168 case XOP: 3169 Features["xop"] = true; 3170 case FMA4: 3171 Features["fma4"] = true; 3172 setSSELevel(Features, AVX, true); 3173 case SSE4A: 3174 Features["sse4a"] = true; 3175 setSSELevel(Features, SSE3, true); 3176 case NoXOP: 3177 break; 3178 } 3179 return; 3180 } 3181 3182 switch (Level) { 3183 case NoXOP: 3184 case SSE4A: 3185 Features["sse4a"] = false; 3186 case FMA4: 3187 Features["fma4"] = false; 3188 case XOP: 3189 Features["xop"] = false; 3190 } 3191 } 3192 3193 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3194 StringRef Name, bool Enabled) { 3195 // This is a bit of a hack to deal with the sse4 target feature when used 3196 // as part of the target attribute. We handle sse4 correctly everywhere 3197 // else. See below for more information on how we handle the sse4 options. 3198 if (Name != "sse4") 3199 Features[Name] = Enabled; 3200 3201 if (Name == "mmx") { 3202 setMMXLevel(Features, MMX, Enabled); 3203 } else if (Name == "sse") { 3204 setSSELevel(Features, SSE1, Enabled); 3205 } else if (Name == "sse2") { 3206 setSSELevel(Features, SSE2, Enabled); 3207 } else if (Name == "sse3") { 3208 setSSELevel(Features, SSE3, Enabled); 3209 } else if (Name == "ssse3") { 3210 setSSELevel(Features, SSSE3, Enabled); 3211 } else if (Name == "sse4.2") { 3212 setSSELevel(Features, SSE42, Enabled); 3213 } else if (Name == "sse4.1") { 3214 setSSELevel(Features, SSE41, Enabled); 3215 } else if (Name == "3dnow") { 3216 setMMXLevel(Features, AMD3DNow, Enabled); 3217 } else if (Name == "3dnowa") { 3218 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3219 } else if (Name == "aes") { 3220 if (Enabled) 3221 setSSELevel(Features, SSE2, Enabled); 3222 } else if (Name == "pclmul") { 3223 if (Enabled) 3224 setSSELevel(Features, SSE2, Enabled); 3225 } else if (Name == "avx") { 3226 setSSELevel(Features, AVX, Enabled); 3227 } else if (Name == "avx2") { 3228 setSSELevel(Features, AVX2, Enabled); 3229 } else if (Name == "avx512f") { 3230 setSSELevel(Features, AVX512F, Enabled); 3231 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3232 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3233 Name == "avx512vbmi" || Name == "avx512ifma") { 3234 if (Enabled) 3235 setSSELevel(Features, AVX512F, Enabled); 3236 } else if (Name == "fma") { 3237 if (Enabled) 3238 setSSELevel(Features, AVX, Enabled); 3239 } else if (Name == "fma4") { 3240 setXOPLevel(Features, FMA4, Enabled); 3241 } else if (Name == "xop") { 3242 setXOPLevel(Features, XOP, Enabled); 3243 } else if (Name == "sse4a") { 3244 setXOPLevel(Features, SSE4A, Enabled); 3245 } else if (Name == "f16c") { 3246 if (Enabled) 3247 setSSELevel(Features, AVX, Enabled); 3248 } else if (Name == "sha") { 3249 if (Enabled) 3250 setSSELevel(Features, SSE2, Enabled); 3251 } else if (Name == "sse4") { 3252 // We can get here via the __target__ attribute since that's not controlled 3253 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3254 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3255 // disabled. 3256 if (Enabled) 3257 setSSELevel(Features, SSE42, Enabled); 3258 else 3259 setSSELevel(Features, SSE41, Enabled); 3260 } else if (Name == "xsave") { 3261 if (!Enabled) 3262 Features["xsaveopt"] = false; 3263 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3264 if (Enabled) 3265 Features["xsave"] = true; 3266 } 3267 } 3268 3269 /// handleTargetFeatures - Perform initialization based on the user 3270 /// configured set of features. 3271 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3272 DiagnosticsEngine &Diags) { 3273 for (const auto &Feature : Features) { 3274 if (Feature[0] != '+') 3275 continue; 3276 3277 if (Feature == "+aes") { 3278 HasAES = true; 3279 } else if (Feature == "+pclmul") { 3280 HasPCLMUL = true; 3281 } else if (Feature == "+lzcnt") { 3282 HasLZCNT = true; 3283 } else if (Feature == "+rdrnd") { 3284 HasRDRND = true; 3285 } else if (Feature == "+fsgsbase") { 3286 HasFSGSBASE = true; 3287 } else if (Feature == "+bmi") { 3288 HasBMI = true; 3289 } else if (Feature == "+bmi2") { 3290 HasBMI2 = true; 3291 } else if (Feature == "+popcnt") { 3292 HasPOPCNT = true; 3293 } else if (Feature == "+rtm") { 3294 HasRTM = true; 3295 } else if (Feature == "+prfchw") { 3296 HasPRFCHW = true; 3297 } else if (Feature == "+rdseed") { 3298 HasRDSEED = true; 3299 } else if (Feature == "+adx") { 3300 HasADX = true; 3301 } else if (Feature == "+tbm") { 3302 HasTBM = true; 3303 } else if (Feature == "+fma") { 3304 HasFMA = true; 3305 } else if (Feature == "+f16c") { 3306 HasF16C = true; 3307 } else if (Feature == "+avx512cd") { 3308 HasAVX512CD = true; 3309 } else if (Feature == "+avx512er") { 3310 HasAVX512ER = true; 3311 } else if (Feature == "+avx512pf") { 3312 HasAVX512PF = true; 3313 } else if (Feature == "+avx512dq") { 3314 HasAVX512DQ = true; 3315 } else if (Feature == "+avx512bw") { 3316 HasAVX512BW = true; 3317 } else if (Feature == "+avx512vl") { 3318 HasAVX512VL = true; 3319 } else if (Feature == "+avx512vbmi") { 3320 HasAVX512VBMI = true; 3321 } else if (Feature == "+avx512ifma") { 3322 HasAVX512IFMA = true; 3323 } else if (Feature == "+sha") { 3324 HasSHA = true; 3325 } else if (Feature == "+mpx") { 3326 HasMPX = true; 3327 } else if (Feature == "+movbe") { 3328 HasMOVBE = true; 3329 } else if (Feature == "+sgx") { 3330 HasSGX = true; 3331 } else if (Feature == "+cx16") { 3332 HasCX16 = true; 3333 } else if (Feature == "+fxsr") { 3334 HasFXSR = true; 3335 } else if (Feature == "+xsave") { 3336 HasXSAVE = true; 3337 } else if (Feature == "+xsaveopt") { 3338 HasXSAVEOPT = true; 3339 } else if (Feature == "+xsavec") { 3340 HasXSAVEC = true; 3341 } else if (Feature == "+xsaves") { 3342 HasXSAVES = true; 3343 } else if (Feature == "+mwaitx") { 3344 HasMWAITX = true; 3345 } else if (Feature == "+pku") { 3346 HasPKU = true; 3347 } else if (Feature == "+clflushopt") { 3348 HasCLFLUSHOPT = true; 3349 } else if (Feature == "+pcommit") { 3350 HasPCOMMIT = true; 3351 } else if (Feature == "+clwb") { 3352 HasCLWB = true; 3353 } else if (Feature == "+umip") { 3354 HasUMIP = true; 3355 } else if (Feature == "+prefetchwt1") { 3356 HasPREFETCHWT1 = true; 3357 } 3358 3359 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3360 .Case("+avx512f", AVX512F) 3361 .Case("+avx2", AVX2) 3362 .Case("+avx", AVX) 3363 .Case("+sse4.2", SSE42) 3364 .Case("+sse4.1", SSE41) 3365 .Case("+ssse3", SSSE3) 3366 .Case("+sse3", SSE3) 3367 .Case("+sse2", SSE2) 3368 .Case("+sse", SSE1) 3369 .Default(NoSSE); 3370 SSELevel = std::max(SSELevel, Level); 3371 3372 MMX3DNowEnum ThreeDNowLevel = 3373 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3374 .Case("+3dnowa", AMD3DNowAthlon) 3375 .Case("+3dnow", AMD3DNow) 3376 .Case("+mmx", MMX) 3377 .Default(NoMMX3DNow); 3378 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3379 3380 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3381 .Case("+xop", XOP) 3382 .Case("+fma4", FMA4) 3383 .Case("+sse4a", SSE4A) 3384 .Default(NoXOP); 3385 XOPLevel = std::max(XOPLevel, XLevel); 3386 } 3387 3388 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3389 // matches the selected sse level. 3390 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3391 (FPMath == FP_387 && SSELevel >= SSE1)) { 3392 Diags.Report(diag::err_target_unsupported_fpmath) << 3393 (FPMath == FP_SSE ? "sse" : "387"); 3394 return false; 3395 } 3396 3397 SimdDefaultAlign = 3398 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3399 return true; 3400 } 3401 3402 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3403 /// definitions for this particular subtarget. 3404 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3405 MacroBuilder &Builder) const { 3406 // Target identification. 3407 if (getTriple().getArch() == llvm::Triple::x86_64) { 3408 Builder.defineMacro("__amd64__"); 3409 Builder.defineMacro("__amd64"); 3410 Builder.defineMacro("__x86_64"); 3411 Builder.defineMacro("__x86_64__"); 3412 if (getTriple().getArchName() == "x86_64h") { 3413 Builder.defineMacro("__x86_64h"); 3414 Builder.defineMacro("__x86_64h__"); 3415 } 3416 } else { 3417 DefineStd(Builder, "i386", Opts); 3418 } 3419 3420 // Subtarget options. 3421 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3422 // truly should be based on -mtune options. 3423 switch (CPU) { 3424 case CK_Generic: 3425 break; 3426 case CK_i386: 3427 // The rest are coming from the i386 define above. 3428 Builder.defineMacro("__tune_i386__"); 3429 break; 3430 case CK_i486: 3431 case CK_WinChipC6: 3432 case CK_WinChip2: 3433 case CK_C3: 3434 defineCPUMacros(Builder, "i486"); 3435 break; 3436 case CK_PentiumMMX: 3437 Builder.defineMacro("__pentium_mmx__"); 3438 Builder.defineMacro("__tune_pentium_mmx__"); 3439 // Fallthrough 3440 case CK_i586: 3441 case CK_Pentium: 3442 defineCPUMacros(Builder, "i586"); 3443 defineCPUMacros(Builder, "pentium"); 3444 break; 3445 case CK_Pentium3: 3446 case CK_Pentium3M: 3447 case CK_PentiumM: 3448 Builder.defineMacro("__tune_pentium3__"); 3449 // Fallthrough 3450 case CK_Pentium2: 3451 case CK_C3_2: 3452 Builder.defineMacro("__tune_pentium2__"); 3453 // Fallthrough 3454 case CK_PentiumPro: 3455 Builder.defineMacro("__tune_i686__"); 3456 Builder.defineMacro("__tune_pentiumpro__"); 3457 // Fallthrough 3458 case CK_i686: 3459 Builder.defineMacro("__i686"); 3460 Builder.defineMacro("__i686__"); 3461 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3462 Builder.defineMacro("__pentiumpro"); 3463 Builder.defineMacro("__pentiumpro__"); 3464 break; 3465 case CK_Pentium4: 3466 case CK_Pentium4M: 3467 defineCPUMacros(Builder, "pentium4"); 3468 break; 3469 case CK_Yonah: 3470 case CK_Prescott: 3471 case CK_Nocona: 3472 defineCPUMacros(Builder, "nocona"); 3473 break; 3474 case CK_Core2: 3475 case CK_Penryn: 3476 defineCPUMacros(Builder, "core2"); 3477 break; 3478 case CK_Bonnell: 3479 defineCPUMacros(Builder, "atom"); 3480 break; 3481 case CK_Silvermont: 3482 defineCPUMacros(Builder, "slm"); 3483 break; 3484 case CK_Nehalem: 3485 case CK_Westmere: 3486 case CK_SandyBridge: 3487 case CK_IvyBridge: 3488 case CK_Haswell: 3489 case CK_Broadwell: 3490 case CK_SkylakeClient: 3491 // FIXME: Historically, we defined this legacy name, it would be nice to 3492 // remove it at some point. We've never exposed fine-grained names for 3493 // recent primary x86 CPUs, and we should keep it that way. 3494 defineCPUMacros(Builder, "corei7"); 3495 break; 3496 case CK_SkylakeServer: 3497 defineCPUMacros(Builder, "skx"); 3498 break; 3499 case CK_Cannonlake: 3500 break; 3501 case CK_KNL: 3502 defineCPUMacros(Builder, "knl"); 3503 break; 3504 case CK_Lakemont: 3505 Builder.defineMacro("__tune_lakemont__"); 3506 break; 3507 case CK_K6_2: 3508 Builder.defineMacro("__k6_2__"); 3509 Builder.defineMacro("__tune_k6_2__"); 3510 // Fallthrough 3511 case CK_K6_3: 3512 if (CPU != CK_K6_2) { // In case of fallthrough 3513 // FIXME: GCC may be enabling these in cases where some other k6 3514 // architecture is specified but -m3dnow is explicitly provided. The 3515 // exact semantics need to be determined and emulated here. 3516 Builder.defineMacro("__k6_3__"); 3517 Builder.defineMacro("__tune_k6_3__"); 3518 } 3519 // Fallthrough 3520 case CK_K6: 3521 defineCPUMacros(Builder, "k6"); 3522 break; 3523 case CK_Athlon: 3524 case CK_AthlonThunderbird: 3525 case CK_Athlon4: 3526 case CK_AthlonXP: 3527 case CK_AthlonMP: 3528 defineCPUMacros(Builder, "athlon"); 3529 if (SSELevel != NoSSE) { 3530 Builder.defineMacro("__athlon_sse__"); 3531 Builder.defineMacro("__tune_athlon_sse__"); 3532 } 3533 break; 3534 case CK_K8: 3535 case CK_K8SSE3: 3536 case CK_x86_64: 3537 case CK_Opteron: 3538 case CK_OpteronSSE3: 3539 case CK_Athlon64: 3540 case CK_Athlon64SSE3: 3541 case CK_AthlonFX: 3542 defineCPUMacros(Builder, "k8"); 3543 break; 3544 case CK_AMDFAM10: 3545 defineCPUMacros(Builder, "amdfam10"); 3546 break; 3547 case CK_BTVER1: 3548 defineCPUMacros(Builder, "btver1"); 3549 break; 3550 case CK_BTVER2: 3551 defineCPUMacros(Builder, "btver2"); 3552 break; 3553 case CK_BDVER1: 3554 defineCPUMacros(Builder, "bdver1"); 3555 break; 3556 case CK_BDVER2: 3557 defineCPUMacros(Builder, "bdver2"); 3558 break; 3559 case CK_BDVER3: 3560 defineCPUMacros(Builder, "bdver3"); 3561 break; 3562 case CK_BDVER4: 3563 defineCPUMacros(Builder, "bdver4"); 3564 break; 3565 case CK_Geode: 3566 defineCPUMacros(Builder, "geode"); 3567 break; 3568 } 3569 3570 // Target properties. 3571 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3572 3573 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3574 // functions in glibc header files that use FP Stack inline asm which the 3575 // backend can't deal with (PR879). 3576 Builder.defineMacro("__NO_MATH_INLINES"); 3577 3578 if (HasAES) 3579 Builder.defineMacro("__AES__"); 3580 3581 if (HasPCLMUL) 3582 Builder.defineMacro("__PCLMUL__"); 3583 3584 if (HasLZCNT) 3585 Builder.defineMacro("__LZCNT__"); 3586 3587 if (HasRDRND) 3588 Builder.defineMacro("__RDRND__"); 3589 3590 if (HasFSGSBASE) 3591 Builder.defineMacro("__FSGSBASE__"); 3592 3593 if (HasBMI) 3594 Builder.defineMacro("__BMI__"); 3595 3596 if (HasBMI2) 3597 Builder.defineMacro("__BMI2__"); 3598 3599 if (HasPOPCNT) 3600 Builder.defineMacro("__POPCNT__"); 3601 3602 if (HasRTM) 3603 Builder.defineMacro("__RTM__"); 3604 3605 if (HasPRFCHW) 3606 Builder.defineMacro("__PRFCHW__"); 3607 3608 if (HasRDSEED) 3609 Builder.defineMacro("__RDSEED__"); 3610 3611 if (HasADX) 3612 Builder.defineMacro("__ADX__"); 3613 3614 if (HasTBM) 3615 Builder.defineMacro("__TBM__"); 3616 3617 if (HasMWAITX) 3618 Builder.defineMacro("__MWAITX__"); 3619 3620 switch (XOPLevel) { 3621 case XOP: 3622 Builder.defineMacro("__XOP__"); 3623 case FMA4: 3624 Builder.defineMacro("__FMA4__"); 3625 case SSE4A: 3626 Builder.defineMacro("__SSE4A__"); 3627 case NoXOP: 3628 break; 3629 } 3630 3631 if (HasFMA) 3632 Builder.defineMacro("__FMA__"); 3633 3634 if (HasF16C) 3635 Builder.defineMacro("__F16C__"); 3636 3637 if (HasAVX512CD) 3638 Builder.defineMacro("__AVX512CD__"); 3639 if (HasAVX512ER) 3640 Builder.defineMacro("__AVX512ER__"); 3641 if (HasAVX512PF) 3642 Builder.defineMacro("__AVX512PF__"); 3643 if (HasAVX512DQ) 3644 Builder.defineMacro("__AVX512DQ__"); 3645 if (HasAVX512BW) 3646 Builder.defineMacro("__AVX512BW__"); 3647 if (HasAVX512VL) 3648 Builder.defineMacro("__AVX512VL__"); 3649 if (HasAVX512VBMI) 3650 Builder.defineMacro("__AVX512VBMI__"); 3651 if (HasAVX512IFMA) 3652 Builder.defineMacro("__AVX512IFMA__"); 3653 3654 if (HasSHA) 3655 Builder.defineMacro("__SHA__"); 3656 3657 if (HasFXSR) 3658 Builder.defineMacro("__FXSR__"); 3659 if (HasXSAVE) 3660 Builder.defineMacro("__XSAVE__"); 3661 if (HasXSAVEOPT) 3662 Builder.defineMacro("__XSAVEOPT__"); 3663 if (HasXSAVEC) 3664 Builder.defineMacro("__XSAVEC__"); 3665 if (HasXSAVES) 3666 Builder.defineMacro("__XSAVES__"); 3667 if (HasPKU) 3668 Builder.defineMacro("__PKU__"); 3669 if (HasCX16) 3670 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3671 3672 // Each case falls through to the previous one here. 3673 switch (SSELevel) { 3674 case AVX512F: 3675 Builder.defineMacro("__AVX512F__"); 3676 case AVX2: 3677 Builder.defineMacro("__AVX2__"); 3678 case AVX: 3679 Builder.defineMacro("__AVX__"); 3680 case SSE42: 3681 Builder.defineMacro("__SSE4_2__"); 3682 case SSE41: 3683 Builder.defineMacro("__SSE4_1__"); 3684 case SSSE3: 3685 Builder.defineMacro("__SSSE3__"); 3686 case SSE3: 3687 Builder.defineMacro("__SSE3__"); 3688 case SSE2: 3689 Builder.defineMacro("__SSE2__"); 3690 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3691 case SSE1: 3692 Builder.defineMacro("__SSE__"); 3693 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3694 case NoSSE: 3695 break; 3696 } 3697 3698 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3699 switch (SSELevel) { 3700 case AVX512F: 3701 case AVX2: 3702 case AVX: 3703 case SSE42: 3704 case SSE41: 3705 case SSSE3: 3706 case SSE3: 3707 case SSE2: 3708 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3709 break; 3710 case SSE1: 3711 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3712 break; 3713 default: 3714 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3715 } 3716 } 3717 3718 // Each case falls through to the previous one here. 3719 switch (MMX3DNowLevel) { 3720 case AMD3DNowAthlon: 3721 Builder.defineMacro("__3dNOW_A__"); 3722 case AMD3DNow: 3723 Builder.defineMacro("__3dNOW__"); 3724 case MMX: 3725 Builder.defineMacro("__MMX__"); 3726 case NoMMX3DNow: 3727 break; 3728 } 3729 3730 if (CPU >= CK_i486) { 3731 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3732 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3733 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3734 } 3735 if (CPU >= CK_i586) 3736 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3737 } 3738 3739 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3740 return llvm::StringSwitch<bool>(Feature) 3741 .Case("aes", HasAES) 3742 .Case("avx", SSELevel >= AVX) 3743 .Case("avx2", SSELevel >= AVX2) 3744 .Case("avx512f", SSELevel >= AVX512F) 3745 .Case("avx512cd", HasAVX512CD) 3746 .Case("avx512er", HasAVX512ER) 3747 .Case("avx512pf", HasAVX512PF) 3748 .Case("avx512dq", HasAVX512DQ) 3749 .Case("avx512bw", HasAVX512BW) 3750 .Case("avx512vl", HasAVX512VL) 3751 .Case("avx512vbmi", HasAVX512VBMI) 3752 .Case("avx512ifma", HasAVX512IFMA) 3753 .Case("bmi", HasBMI) 3754 .Case("bmi2", HasBMI2) 3755 .Case("clflushopt", HasCLFLUSHOPT) 3756 .Case("clwb", HasCLWB) 3757 .Case("cx16", HasCX16) 3758 .Case("f16c", HasF16C) 3759 .Case("fma", HasFMA) 3760 .Case("fma4", XOPLevel >= FMA4) 3761 .Case("fsgsbase", HasFSGSBASE) 3762 .Case("fxsr", HasFXSR) 3763 .Case("lzcnt", HasLZCNT) 3764 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3765 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3766 .Case("mmx", MMX3DNowLevel >= MMX) 3767 .Case("movbe", HasMOVBE) 3768 .Case("mpx", HasMPX) 3769 .Case("pclmul", HasPCLMUL) 3770 .Case("pcommit", HasPCOMMIT) 3771 .Case("pku", HasPKU) 3772 .Case("popcnt", HasPOPCNT) 3773 .Case("prefetchwt1", HasPREFETCHWT1) 3774 .Case("prfchw", HasPRFCHW) 3775 .Case("rdrnd", HasRDRND) 3776 .Case("rdseed", HasRDSEED) 3777 .Case("rtm", HasRTM) 3778 .Case("sgx", HasSGX) 3779 .Case("sha", HasSHA) 3780 .Case("sse", SSELevel >= SSE1) 3781 .Case("sse2", SSELevel >= SSE2) 3782 .Case("sse3", SSELevel >= SSE3) 3783 .Case("ssse3", SSELevel >= SSSE3) 3784 .Case("sse4.1", SSELevel >= SSE41) 3785 .Case("sse4.2", SSELevel >= SSE42) 3786 .Case("sse4a", XOPLevel >= SSE4A) 3787 .Case("tbm", HasTBM) 3788 .Case("umip", HasUMIP) 3789 .Case("x86", true) 3790 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3791 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3792 .Case("xop", XOPLevel >= XOP) 3793 .Case("xsave", HasXSAVE) 3794 .Case("xsavec", HasXSAVEC) 3795 .Case("xsaves", HasXSAVES) 3796 .Case("xsaveopt", HasXSAVEOPT) 3797 .Default(false); 3798 } 3799 3800 // We can't use a generic validation scheme for the features accepted here 3801 // versus subtarget features accepted in the target attribute because the 3802 // bitfield structure that's initialized in the runtime only supports the 3803 // below currently rather than the full range of subtarget features. (See 3804 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3805 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3806 return llvm::StringSwitch<bool>(FeatureStr) 3807 .Case("cmov", true) 3808 .Case("mmx", true) 3809 .Case("popcnt", true) 3810 .Case("sse", true) 3811 .Case("sse2", true) 3812 .Case("sse3", true) 3813 .Case("ssse3", true) 3814 .Case("sse4.1", true) 3815 .Case("sse4.2", true) 3816 .Case("avx", true) 3817 .Case("avx2", true) 3818 .Case("sse4a", true) 3819 .Case("fma4", true) 3820 .Case("xop", true) 3821 .Case("fma", true) 3822 .Case("avx512f", true) 3823 .Case("bmi", true) 3824 .Case("bmi2", true) 3825 .Case("aes", true) 3826 .Case("pclmul", true) 3827 .Case("avx512vl", true) 3828 .Case("avx512bw", true) 3829 .Case("avx512dq", true) 3830 .Case("avx512cd", true) 3831 .Case("avx512er", true) 3832 .Case("avx512pf", true) 3833 .Case("avx512vbmi", true) 3834 .Case("avx512ifma", true) 3835 .Default(false); 3836 } 3837 3838 bool 3839 X86TargetInfo::validateAsmConstraint(const char *&Name, 3840 TargetInfo::ConstraintInfo &Info) const { 3841 switch (*Name) { 3842 default: return false; 3843 // Constant constraints. 3844 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3845 // instructions. 3846 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3847 // x86_64 instructions. 3848 case 's': 3849 Info.setRequiresImmediate(); 3850 return true; 3851 case 'I': 3852 Info.setRequiresImmediate(0, 31); 3853 return true; 3854 case 'J': 3855 Info.setRequiresImmediate(0, 63); 3856 return true; 3857 case 'K': 3858 Info.setRequiresImmediate(-128, 127); 3859 return true; 3860 case 'L': 3861 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3862 return true; 3863 case 'M': 3864 Info.setRequiresImmediate(0, 3); 3865 return true; 3866 case 'N': 3867 Info.setRequiresImmediate(0, 255); 3868 return true; 3869 case 'O': 3870 Info.setRequiresImmediate(0, 127); 3871 return true; 3872 // Register constraints. 3873 case 'Y': // 'Y' is the first character for several 2-character constraints. 3874 // Shift the pointer to the second character of the constraint. 3875 Name++; 3876 switch (*Name) { 3877 default: 3878 return false; 3879 case '0': // First SSE register. 3880 case 't': // Any SSE register, when SSE2 is enabled. 3881 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3882 case 'm': // Any MMX register, when inter-unit moves enabled. 3883 Info.setAllowsRegister(); 3884 return true; 3885 } 3886 case 'f': // Any x87 floating point stack register. 3887 // Constraint 'f' cannot be used for output operands. 3888 if (Info.ConstraintStr[0] == '=') 3889 return false; 3890 Info.setAllowsRegister(); 3891 return true; 3892 case 'a': // eax. 3893 case 'b': // ebx. 3894 case 'c': // ecx. 3895 case 'd': // edx. 3896 case 'S': // esi. 3897 case 'D': // edi. 3898 case 'A': // edx:eax. 3899 case 't': // Top of floating point stack. 3900 case 'u': // Second from top of floating point stack. 3901 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3902 case 'y': // Any MMX register. 3903 case 'x': // Any SSE register. 3904 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3905 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3906 case 'l': // "Index" registers: any general register that can be used as an 3907 // index in a base+index memory access. 3908 Info.setAllowsRegister(); 3909 return true; 3910 // Floating point constant constraints. 3911 case 'C': // SSE floating point constant. 3912 case 'G': // x87 floating point constant. 3913 return true; 3914 } 3915 } 3916 3917 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3918 unsigned Size) const { 3919 // Strip off constraint modifiers. 3920 while (Constraint[0] == '=' || 3921 Constraint[0] == '+' || 3922 Constraint[0] == '&') 3923 Constraint = Constraint.substr(1); 3924 3925 return validateOperandSize(Constraint, Size); 3926 } 3927 3928 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3929 unsigned Size) const { 3930 return validateOperandSize(Constraint, Size); 3931 } 3932 3933 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3934 unsigned Size) const { 3935 switch (Constraint[0]) { 3936 default: break; 3937 case 'y': 3938 return Size <= 64; 3939 case 'f': 3940 case 't': 3941 case 'u': 3942 return Size <= 128; 3943 case 'x': 3944 if (SSELevel >= AVX512F) 3945 // 512-bit zmm registers can be used if target supports AVX512F. 3946 return Size <= 512U; 3947 else if (SSELevel >= AVX) 3948 // 256-bit ymm registers can be used if target supports AVX. 3949 return Size <= 256U; 3950 return Size <= 128U; 3951 case 'Y': 3952 // 'Y' is the first character for several 2-character constraints. 3953 switch (Constraint[1]) { 3954 default: break; 3955 case 'm': 3956 // 'Ym' is synonymous with 'y'. 3957 return Size <= 64; 3958 case 'i': 3959 case 't': 3960 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3961 if (SSELevel >= AVX512F) 3962 return Size <= 512U; 3963 else if (SSELevel >= AVX) 3964 return Size <= 256U; 3965 return SSELevel >= SSE2 && Size <= 128U; 3966 } 3967 3968 } 3969 3970 return true; 3971 } 3972 3973 std::string 3974 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3975 switch (*Constraint) { 3976 case 'a': return std::string("{ax}"); 3977 case 'b': return std::string("{bx}"); 3978 case 'c': return std::string("{cx}"); 3979 case 'd': return std::string("{dx}"); 3980 case 'S': return std::string("{si}"); 3981 case 'D': return std::string("{di}"); 3982 case 'p': // address 3983 return std::string("im"); 3984 case 't': // top of floating point stack. 3985 return std::string("{st}"); 3986 case 'u': // second from top of floating point stack. 3987 return std::string("{st(1)}"); // second from top of floating point stack. 3988 default: 3989 return std::string(1, *Constraint); 3990 } 3991 } 3992 3993 // X86-32 generic target 3994 class X86_32TargetInfo : public X86TargetInfo { 3995 public: 3996 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3997 : X86TargetInfo(Triple, Opts) { 3998 DoubleAlign = LongLongAlign = 32; 3999 LongDoubleWidth = 96; 4000 LongDoubleAlign = 32; 4001 SuitableAlign = 128; 4002 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4003 SizeType = UnsignedInt; 4004 PtrDiffType = SignedInt; 4005 IntPtrType = SignedInt; 4006 RegParmMax = 3; 4007 4008 // Use fpret for all types. 4009 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4010 (1 << TargetInfo::Double) | 4011 (1 << TargetInfo::LongDouble)); 4012 4013 // x86-32 has atomics up to 8 bytes 4014 // FIXME: Check that we actually have cmpxchg8b before setting 4015 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4016 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4017 } 4018 BuiltinVaListKind getBuiltinVaListKind() const override { 4019 return TargetInfo::CharPtrBuiltinVaList; 4020 } 4021 4022 int getEHDataRegisterNumber(unsigned RegNo) const override { 4023 if (RegNo == 0) return 0; 4024 if (RegNo == 1) return 2; 4025 return -1; 4026 } 4027 bool validateOperandSize(StringRef Constraint, 4028 unsigned Size) const override { 4029 switch (Constraint[0]) { 4030 default: break; 4031 case 'R': 4032 case 'q': 4033 case 'Q': 4034 case 'a': 4035 case 'b': 4036 case 'c': 4037 case 'd': 4038 case 'S': 4039 case 'D': 4040 return Size <= 32; 4041 case 'A': 4042 return Size <= 64; 4043 } 4044 4045 return X86TargetInfo::validateOperandSize(Constraint, Size); 4046 } 4047 }; 4048 4049 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4050 public: 4051 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4052 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4053 4054 unsigned getFloatEvalMethod() const override { 4055 unsigned Major, Minor, Micro; 4056 getTriple().getOSVersion(Major, Minor, Micro); 4057 // New NetBSD uses the default rounding mode. 4058 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4059 return X86_32TargetInfo::getFloatEvalMethod(); 4060 // NetBSD before 6.99.26 defaults to "double" rounding. 4061 return 1; 4062 } 4063 }; 4064 4065 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4066 public: 4067 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4068 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4069 SizeType = UnsignedLong; 4070 IntPtrType = SignedLong; 4071 PtrDiffType = SignedLong; 4072 } 4073 }; 4074 4075 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4076 public: 4077 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4078 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4079 SizeType = UnsignedLong; 4080 IntPtrType = SignedLong; 4081 PtrDiffType = SignedLong; 4082 } 4083 }; 4084 4085 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4086 public: 4087 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4088 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4089 LongDoubleWidth = 128; 4090 LongDoubleAlign = 128; 4091 SuitableAlign = 128; 4092 MaxVectorAlign = 256; 4093 // The watchOS simulator uses the builtin bool type for Objective-C. 4094 llvm::Triple T = llvm::Triple(Triple); 4095 if (T.isWatchOS()) 4096 UseSignedCharForObjCBool = false; 4097 SizeType = UnsignedLong; 4098 IntPtrType = SignedLong; 4099 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4100 HasAlignMac68kSupport = true; 4101 } 4102 4103 bool handleTargetFeatures(std::vector<std::string> &Features, 4104 DiagnosticsEngine &Diags) override { 4105 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4106 Diags)) 4107 return false; 4108 // We now know the features we have: we can decide how to align vectors. 4109 MaxVectorAlign = 4110 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4111 return true; 4112 } 4113 }; 4114 4115 // x86-32 Windows target 4116 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4117 public: 4118 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4119 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4120 WCharType = UnsignedShort; 4121 DoubleAlign = LongLongAlign = 64; 4122 bool IsWinCOFF = 4123 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4124 resetDataLayout(IsWinCOFF 4125 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4126 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4127 } 4128 void getTargetDefines(const LangOptions &Opts, 4129 MacroBuilder &Builder) const override { 4130 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4131 } 4132 }; 4133 4134 // x86-32 Windows Visual Studio target 4135 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4136 public: 4137 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4138 const TargetOptions &Opts) 4139 : WindowsX86_32TargetInfo(Triple, Opts) { 4140 LongDoubleWidth = LongDoubleAlign = 64; 4141 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4142 } 4143 void getTargetDefines(const LangOptions &Opts, 4144 MacroBuilder &Builder) const override { 4145 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4146 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4147 // The value of the following reflects processor type. 4148 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4149 // We lost the original triple, so we use the default. 4150 Builder.defineMacro("_M_IX86", "600"); 4151 } 4152 }; 4153 4154 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4155 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4156 // supports __declspec natively under -fms-extensions, but we define a no-op 4157 // __declspec macro anyway for pre-processor compatibility. 4158 if (Opts.MicrosoftExt) 4159 Builder.defineMacro("__declspec", "__declspec"); 4160 else 4161 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4162 4163 if (!Opts.MicrosoftExt) { 4164 // Provide macros for all the calling convention keywords. Provide both 4165 // single and double underscore prefixed variants. These are available on 4166 // x64 as well as x86, even though they have no effect. 4167 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4168 for (const char *CC : CCs) { 4169 std::string GCCSpelling = "__attribute__((__"; 4170 GCCSpelling += CC; 4171 GCCSpelling += "__))"; 4172 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4173 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4174 } 4175 } 4176 } 4177 4178 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4179 Builder.defineMacro("__MSVCRT__"); 4180 Builder.defineMacro("__MINGW32__"); 4181 addCygMingDefines(Opts, Builder); 4182 } 4183 4184 // x86-32 MinGW target 4185 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4186 public: 4187 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4188 : WindowsX86_32TargetInfo(Triple, Opts) {} 4189 void getTargetDefines(const LangOptions &Opts, 4190 MacroBuilder &Builder) const override { 4191 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4192 DefineStd(Builder, "WIN32", Opts); 4193 DefineStd(Builder, "WINNT", Opts); 4194 Builder.defineMacro("_X86_"); 4195 addMinGWDefines(Opts, Builder); 4196 } 4197 }; 4198 4199 // x86-32 Cygwin target 4200 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4201 public: 4202 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4203 : X86_32TargetInfo(Triple, Opts) { 4204 WCharType = UnsignedShort; 4205 DoubleAlign = LongLongAlign = 64; 4206 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4207 } 4208 void getTargetDefines(const LangOptions &Opts, 4209 MacroBuilder &Builder) const override { 4210 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4211 Builder.defineMacro("_X86_"); 4212 Builder.defineMacro("__CYGWIN__"); 4213 Builder.defineMacro("__CYGWIN32__"); 4214 addCygMingDefines(Opts, Builder); 4215 DefineStd(Builder, "unix", Opts); 4216 if (Opts.CPlusPlus) 4217 Builder.defineMacro("_GNU_SOURCE"); 4218 } 4219 }; 4220 4221 // x86-32 Haiku target 4222 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4223 public: 4224 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4225 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4226 } 4227 void getTargetDefines(const LangOptions &Opts, 4228 MacroBuilder &Builder) const override { 4229 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4230 Builder.defineMacro("__INTEL__"); 4231 } 4232 }; 4233 4234 // X86-32 MCU target 4235 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4236 public: 4237 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4238 : X86_32TargetInfo(Triple, Opts) { 4239 LongDoubleWidth = 64; 4240 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4241 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4242 WIntType = UnsignedInt; 4243 } 4244 4245 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4246 // On MCU we support only C calling convention. 4247 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4248 } 4249 4250 void getTargetDefines(const LangOptions &Opts, 4251 MacroBuilder &Builder) const override { 4252 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4253 Builder.defineMacro("__iamcu"); 4254 Builder.defineMacro("__iamcu__"); 4255 } 4256 4257 bool allowsLargerPreferedTypeAlignment() const override { 4258 return false; 4259 } 4260 }; 4261 4262 // RTEMS Target 4263 template<typename Target> 4264 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4265 protected: 4266 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4267 MacroBuilder &Builder) const override { 4268 // RTEMS defines; list based off of gcc output 4269 4270 Builder.defineMacro("__rtems__"); 4271 Builder.defineMacro("__ELF__"); 4272 } 4273 4274 public: 4275 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4276 : OSTargetInfo<Target>(Triple, Opts) { 4277 switch (Triple.getArch()) { 4278 default: 4279 case llvm::Triple::x86: 4280 // this->MCountName = ".mcount"; 4281 break; 4282 case llvm::Triple::mips: 4283 case llvm::Triple::mipsel: 4284 case llvm::Triple::ppc: 4285 case llvm::Triple::ppc64: 4286 case llvm::Triple::ppc64le: 4287 // this->MCountName = "_mcount"; 4288 break; 4289 case llvm::Triple::arm: 4290 // this->MCountName = "__mcount"; 4291 break; 4292 } 4293 } 4294 }; 4295 4296 // x86-32 RTEMS target 4297 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4298 public: 4299 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4300 : X86_32TargetInfo(Triple, Opts) { 4301 SizeType = UnsignedLong; 4302 IntPtrType = SignedLong; 4303 PtrDiffType = SignedLong; 4304 } 4305 void getTargetDefines(const LangOptions &Opts, 4306 MacroBuilder &Builder) const override { 4307 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4308 Builder.defineMacro("__INTEL__"); 4309 Builder.defineMacro("__rtems__"); 4310 } 4311 }; 4312 4313 // x86-64 generic target 4314 class X86_64TargetInfo : public X86TargetInfo { 4315 public: 4316 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4317 : X86TargetInfo(Triple, Opts) { 4318 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4319 bool IsWinCOFF = 4320 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4321 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4322 LongDoubleWidth = 128; 4323 LongDoubleAlign = 128; 4324 LargeArrayMinWidth = 128; 4325 LargeArrayAlign = 128; 4326 SuitableAlign = 128; 4327 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4328 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4329 IntPtrType = IsX32 ? SignedInt : SignedLong; 4330 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4331 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4332 RegParmMax = 6; 4333 4334 // Pointers are 32-bit in x32. 4335 resetDataLayout(IsX32 4336 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4337 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4338 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4339 4340 // Use fpret only for long double. 4341 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4342 4343 // Use fp2ret for _Complex long double. 4344 ComplexLongDoubleUsesFP2Ret = true; 4345 4346 // Make __builtin_ms_va_list available. 4347 HasBuiltinMSVaList = true; 4348 4349 // x86-64 has atomics up to 16 bytes. 4350 MaxAtomicPromoteWidth = 128; 4351 MaxAtomicInlineWidth = 128; 4352 } 4353 BuiltinVaListKind getBuiltinVaListKind() const override { 4354 return TargetInfo::X86_64ABIBuiltinVaList; 4355 } 4356 4357 int getEHDataRegisterNumber(unsigned RegNo) const override { 4358 if (RegNo == 0) return 0; 4359 if (RegNo == 1) return 1; 4360 return -1; 4361 } 4362 4363 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4364 switch (CC) { 4365 case CC_C: 4366 case CC_Swift: 4367 case CC_X86VectorCall: 4368 case CC_IntelOclBicc: 4369 case CC_X86_64Win64: 4370 case CC_PreserveMost: 4371 case CC_PreserveAll: 4372 return CCCR_OK; 4373 default: 4374 return CCCR_Warning; 4375 } 4376 } 4377 4378 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4379 return CC_C; 4380 } 4381 4382 // for x32 we need it here explicitly 4383 bool hasInt128Type() const override { return true; } 4384 unsigned getUnwindWordWidth() const override { return 64; } 4385 unsigned getRegisterWidth() const override { return 64; } 4386 4387 bool validateGlobalRegisterVariable(StringRef RegName, 4388 unsigned RegSize, 4389 bool &HasSizeMismatch) const override { 4390 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4391 // handle. 4392 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4393 // Check that the register size is 64-bit. 4394 HasSizeMismatch = RegSize != 64; 4395 return true; 4396 } 4397 4398 // Check if the register is a 32-bit register the backend can handle. 4399 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4400 HasSizeMismatch); 4401 } 4402 }; 4403 4404 // x86-64 Windows target 4405 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4406 public: 4407 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4408 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4409 WCharType = UnsignedShort; 4410 LongWidth = LongAlign = 32; 4411 DoubleAlign = LongLongAlign = 64; 4412 IntMaxType = SignedLongLong; 4413 Int64Type = SignedLongLong; 4414 SizeType = UnsignedLongLong; 4415 PtrDiffType = SignedLongLong; 4416 IntPtrType = SignedLongLong; 4417 } 4418 4419 void getTargetDefines(const LangOptions &Opts, 4420 MacroBuilder &Builder) const override { 4421 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4422 Builder.defineMacro("_WIN64"); 4423 } 4424 4425 BuiltinVaListKind getBuiltinVaListKind() const override { 4426 return TargetInfo::CharPtrBuiltinVaList; 4427 } 4428 4429 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4430 switch (CC) { 4431 case CC_X86StdCall: 4432 case CC_X86ThisCall: 4433 case CC_X86FastCall: 4434 return CCCR_Ignore; 4435 case CC_C: 4436 case CC_X86VectorCall: 4437 case CC_IntelOclBicc: 4438 case CC_X86_64SysV: 4439 return CCCR_OK; 4440 default: 4441 return CCCR_Warning; 4442 } 4443 } 4444 }; 4445 4446 // x86-64 Windows Visual Studio target 4447 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4448 public: 4449 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4450 const TargetOptions &Opts) 4451 : WindowsX86_64TargetInfo(Triple, Opts) { 4452 LongDoubleWidth = LongDoubleAlign = 64; 4453 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4454 } 4455 void getTargetDefines(const LangOptions &Opts, 4456 MacroBuilder &Builder) const override { 4457 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4458 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4459 Builder.defineMacro("_M_X64", "100"); 4460 Builder.defineMacro("_M_AMD64", "100"); 4461 } 4462 }; 4463 4464 // x86-64 MinGW target 4465 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4466 public: 4467 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4468 : WindowsX86_64TargetInfo(Triple, Opts) { 4469 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4470 // with x86 FP ops. Weird. 4471 LongDoubleWidth = LongDoubleAlign = 128; 4472 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4473 } 4474 4475 void getTargetDefines(const LangOptions &Opts, 4476 MacroBuilder &Builder) const override { 4477 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4478 DefineStd(Builder, "WIN64", Opts); 4479 Builder.defineMacro("__MINGW64__"); 4480 addMinGWDefines(Opts, Builder); 4481 4482 // GCC defines this macro when it is using __gxx_personality_seh0. 4483 if (!Opts.SjLjExceptions) 4484 Builder.defineMacro("__SEH__"); 4485 } 4486 }; 4487 4488 // x86-64 Cygwin target 4489 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4490 public: 4491 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4492 : X86_64TargetInfo(Triple, Opts) { 4493 TLSSupported = false; 4494 WCharType = UnsignedShort; 4495 } 4496 void getTargetDefines(const LangOptions &Opts, 4497 MacroBuilder &Builder) const override { 4498 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4499 Builder.defineMacro("__x86_64__"); 4500 Builder.defineMacro("__CYGWIN__"); 4501 Builder.defineMacro("__CYGWIN64__"); 4502 addCygMingDefines(Opts, Builder); 4503 DefineStd(Builder, "unix", Opts); 4504 if (Opts.CPlusPlus) 4505 Builder.defineMacro("_GNU_SOURCE"); 4506 4507 // GCC defines this macro when it is using __gxx_personality_seh0. 4508 if (!Opts.SjLjExceptions) 4509 Builder.defineMacro("__SEH__"); 4510 } 4511 }; 4512 4513 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4514 public: 4515 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4516 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4517 Int64Type = SignedLongLong; 4518 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4519 llvm::Triple T = llvm::Triple(Triple); 4520 if (T.isiOS()) 4521 UseSignedCharForObjCBool = false; 4522 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4523 } 4524 4525 bool handleTargetFeatures(std::vector<std::string> &Features, 4526 DiagnosticsEngine &Diags) override { 4527 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4528 Diags)) 4529 return false; 4530 // We now know the features we have: we can decide how to align vectors. 4531 MaxVectorAlign = 4532 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4533 return true; 4534 } 4535 }; 4536 4537 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4538 public: 4539 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4540 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4541 IntMaxType = SignedLongLong; 4542 Int64Type = SignedLongLong; 4543 } 4544 }; 4545 4546 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4547 public: 4548 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4549 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4550 IntMaxType = SignedLongLong; 4551 Int64Type = SignedLongLong; 4552 } 4553 }; 4554 4555 class ARMTargetInfo : public TargetInfo { 4556 // Possible FPU choices. 4557 enum FPUMode { 4558 VFP2FPU = (1 << 0), 4559 VFP3FPU = (1 << 1), 4560 VFP4FPU = (1 << 2), 4561 NeonFPU = (1 << 3), 4562 FPARMV8 = (1 << 4) 4563 }; 4564 4565 // Possible HWDiv features. 4566 enum HWDivMode { 4567 HWDivThumb = (1 << 0), 4568 HWDivARM = (1 << 1) 4569 }; 4570 4571 static bool FPUModeIsVFP(FPUMode Mode) { 4572 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4573 } 4574 4575 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4576 static const char * const GCCRegNames[]; 4577 4578 std::string ABI, CPU; 4579 4580 StringRef CPUProfile; 4581 StringRef CPUAttr; 4582 4583 enum { 4584 FP_Default, 4585 FP_VFP, 4586 FP_Neon 4587 } FPMath; 4588 4589 unsigned ArchISA; 4590 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4591 unsigned ArchProfile; 4592 unsigned ArchVersion; 4593 4594 unsigned FPU : 5; 4595 4596 unsigned IsAAPCS : 1; 4597 unsigned HWDiv : 2; 4598 4599 // Initialized via features. 4600 unsigned SoftFloat : 1; 4601 unsigned SoftFloatABI : 1; 4602 4603 unsigned CRC : 1; 4604 unsigned Crypto : 1; 4605 unsigned DSP : 1; 4606 unsigned Unaligned : 1; 4607 4608 enum { 4609 LDREX_B = (1 << 0), /// byte (8-bit) 4610 LDREX_H = (1 << 1), /// half (16-bit) 4611 LDREX_W = (1 << 2), /// word (32-bit) 4612 LDREX_D = (1 << 3), /// double (64-bit) 4613 }; 4614 4615 uint32_t LDREX; 4616 4617 // ACLE 6.5.1 Hardware floating point 4618 enum { 4619 HW_FP_HP = (1 << 1), /// half (16-bit) 4620 HW_FP_SP = (1 << 2), /// single (32-bit) 4621 HW_FP_DP = (1 << 3), /// double (64-bit) 4622 }; 4623 uint32_t HW_FP; 4624 4625 static const Builtin::Info BuiltinInfo[]; 4626 4627 void setABIAAPCS() { 4628 IsAAPCS = true; 4629 4630 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4631 const llvm::Triple &T = getTriple(); 4632 4633 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4634 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4635 T.getOS() == llvm::Triple::Bitrig) 4636 SizeType = UnsignedLong; 4637 else 4638 SizeType = UnsignedInt; 4639 4640 switch (T.getOS()) { 4641 case llvm::Triple::NetBSD: 4642 WCharType = SignedInt; 4643 break; 4644 case llvm::Triple::Win32: 4645 WCharType = UnsignedShort; 4646 break; 4647 case llvm::Triple::Linux: 4648 default: 4649 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4650 WCharType = UnsignedInt; 4651 break; 4652 } 4653 4654 UseBitFieldTypeAlignment = true; 4655 4656 ZeroLengthBitfieldBoundary = 0; 4657 4658 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4659 // so set preferred for small types to 32. 4660 if (T.isOSBinFormatMachO()) { 4661 resetDataLayout(BigEndian 4662 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4663 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4664 } else if (T.isOSWindows()) { 4665 assert(!BigEndian && "Windows on ARM does not support big endian"); 4666 resetDataLayout("e" 4667 "-m:w" 4668 "-p:32:32" 4669 "-i64:64" 4670 "-v128:64:128" 4671 "-a:0:32" 4672 "-n32" 4673 "-S64"); 4674 } else if (T.isOSNaCl()) { 4675 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4676 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4677 } else { 4678 resetDataLayout(BigEndian 4679 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4680 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4681 } 4682 4683 // FIXME: Enumerated types are variable width in straight AAPCS. 4684 } 4685 4686 void setABIAPCS(bool IsAAPCS16) { 4687 const llvm::Triple &T = getTriple(); 4688 4689 IsAAPCS = false; 4690 4691 if (IsAAPCS16) 4692 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4693 else 4694 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4695 4696 // size_t is unsigned int on FreeBSD. 4697 if (T.getOS() == llvm::Triple::FreeBSD) 4698 SizeType = UnsignedInt; 4699 else 4700 SizeType = UnsignedLong; 4701 4702 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4703 WCharType = SignedInt; 4704 4705 // Do not respect the alignment of bit-field types when laying out 4706 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4707 UseBitFieldTypeAlignment = false; 4708 4709 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4710 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4711 /// gcc. 4712 ZeroLengthBitfieldBoundary = 32; 4713 4714 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4715 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4716 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4717 } else if (T.isOSBinFormatMachO()) 4718 resetDataLayout( 4719 BigEndian 4720 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4721 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4722 else 4723 resetDataLayout( 4724 BigEndian 4725 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4726 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4727 4728 // FIXME: Override "preferred align" for double and long long. 4729 } 4730 4731 void setArchInfo() { 4732 StringRef ArchName = getTriple().getArchName(); 4733 4734 ArchISA = llvm::ARM::parseArchISA(ArchName); 4735 CPU = llvm::ARM::getDefaultCPU(ArchName); 4736 unsigned AK = llvm::ARM::parseArch(ArchName); 4737 if (AK != llvm::ARM::AK_INVALID) 4738 ArchKind = AK; 4739 setArchInfo(ArchKind); 4740 } 4741 4742 void setArchInfo(unsigned Kind) { 4743 StringRef SubArch; 4744 4745 // cache TargetParser info 4746 ArchKind = Kind; 4747 SubArch = llvm::ARM::getSubArch(ArchKind); 4748 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4749 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4750 4751 // cache CPU related strings 4752 CPUAttr = getCPUAttr(); 4753 CPUProfile = getCPUProfile(); 4754 } 4755 4756 void setAtomic() { 4757 // when triple does not specify a sub arch, 4758 // then we are not using inline atomics 4759 bool ShouldUseInlineAtomic = 4760 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4761 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4762 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4763 if (ArchProfile == llvm::ARM::PK_M) { 4764 MaxAtomicPromoteWidth = 32; 4765 if (ShouldUseInlineAtomic) 4766 MaxAtomicInlineWidth = 32; 4767 } 4768 else { 4769 MaxAtomicPromoteWidth = 64; 4770 if (ShouldUseInlineAtomic) 4771 MaxAtomicInlineWidth = 64; 4772 } 4773 } 4774 4775 bool isThumb() const { 4776 return (ArchISA == llvm::ARM::IK_THUMB); 4777 } 4778 4779 bool supportsThumb() const { 4780 return CPUAttr.count('T') || ArchVersion >= 6; 4781 } 4782 4783 bool supportsThumb2() const { 4784 return CPUAttr.equals("6T2") || 4785 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 4786 } 4787 4788 StringRef getCPUAttr() const { 4789 // For most sub-arches, the build attribute CPU name is enough. 4790 // For Cortex variants, it's slightly different. 4791 switch(ArchKind) { 4792 default: 4793 return llvm::ARM::getCPUAttr(ArchKind); 4794 case llvm::ARM::AK_ARMV6M: 4795 return "6M"; 4796 case llvm::ARM::AK_ARMV7S: 4797 return "7S"; 4798 case llvm::ARM::AK_ARMV7A: 4799 return "7A"; 4800 case llvm::ARM::AK_ARMV7R: 4801 return "7R"; 4802 case llvm::ARM::AK_ARMV7M: 4803 return "7M"; 4804 case llvm::ARM::AK_ARMV7EM: 4805 return "7EM"; 4806 case llvm::ARM::AK_ARMV8A: 4807 return "8A"; 4808 case llvm::ARM::AK_ARMV8_1A: 4809 return "8_1A"; 4810 case llvm::ARM::AK_ARMV8_2A: 4811 return "8_2A"; 4812 case llvm::ARM::AK_ARMV8MBaseline: 4813 return "8M_BASE"; 4814 case llvm::ARM::AK_ARMV8MMainline: 4815 return "8M_MAIN"; 4816 } 4817 } 4818 4819 StringRef getCPUProfile() const { 4820 switch(ArchProfile) { 4821 case llvm::ARM::PK_A: 4822 return "A"; 4823 case llvm::ARM::PK_R: 4824 return "R"; 4825 case llvm::ARM::PK_M: 4826 return "M"; 4827 default: 4828 return ""; 4829 } 4830 } 4831 4832 public: 4833 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 4834 bool IsBigEndian) 4835 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 4836 HW_FP(0) { 4837 BigEndian = IsBigEndian; 4838 4839 switch (getTriple().getOS()) { 4840 case llvm::Triple::NetBSD: 4841 PtrDiffType = SignedLong; 4842 break; 4843 default: 4844 PtrDiffType = SignedInt; 4845 break; 4846 } 4847 4848 // Cache arch related info. 4849 setArchInfo(); 4850 4851 // {} in inline assembly are neon specifiers, not assembly variant 4852 // specifiers. 4853 NoAsmVariants = true; 4854 4855 // FIXME: This duplicates code from the driver that sets the -target-abi 4856 // option - this code is used if -target-abi isn't passed and should 4857 // be unified in some way. 4858 if (Triple.isOSBinFormatMachO()) { 4859 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4860 // the frontend matches that. 4861 if (Triple.getEnvironment() == llvm::Triple::EABI || 4862 Triple.getOS() == llvm::Triple::UnknownOS || 4863 StringRef(CPU).startswith("cortex-m")) { 4864 setABI("aapcs"); 4865 } else if (Triple.isWatchABI()) { 4866 setABI("aapcs16"); 4867 } else { 4868 setABI("apcs-gnu"); 4869 } 4870 } else if (Triple.isOSWindows()) { 4871 // FIXME: this is invalid for WindowsCE 4872 setABI("aapcs"); 4873 } else { 4874 // Select the default based on the platform. 4875 switch (Triple.getEnvironment()) { 4876 case llvm::Triple::Android: 4877 case llvm::Triple::GNUEABI: 4878 case llvm::Triple::GNUEABIHF: 4879 setABI("aapcs-linux"); 4880 break; 4881 case llvm::Triple::EABIHF: 4882 case llvm::Triple::EABI: 4883 setABI("aapcs"); 4884 break; 4885 case llvm::Triple::GNU: 4886 setABI("apcs-gnu"); 4887 break; 4888 default: 4889 if (Triple.getOS() == llvm::Triple::NetBSD) 4890 setABI("apcs-gnu"); 4891 else 4892 setABI("aapcs"); 4893 break; 4894 } 4895 } 4896 4897 // ARM targets default to using the ARM C++ ABI. 4898 TheCXXABI.set(TargetCXXABI::GenericARM); 4899 4900 // ARM has atomics up to 8 bytes 4901 setAtomic(); 4902 4903 // Do force alignment of members that follow zero length bitfields. If 4904 // the alignment of the zero-length bitfield is greater than the member 4905 // that follows it, `bar', `bar' will be aligned as the type of the 4906 // zero length bitfield. 4907 UseZeroLengthBitfieldAlignment = true; 4908 4909 if (Triple.getOS() == llvm::Triple::Linux || 4910 Triple.getOS() == llvm::Triple::UnknownOS) 4911 this->MCountName = 4912 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 4913 } 4914 4915 StringRef getABI() const override { return ABI; } 4916 4917 bool setABI(const std::string &Name) override { 4918 ABI = Name; 4919 4920 // The defaults (above) are for AAPCS, check if we need to change them. 4921 // 4922 // FIXME: We need support for -meabi... we could just mangle it into the 4923 // name. 4924 if (Name == "apcs-gnu" || Name == "aapcs16") { 4925 setABIAPCS(Name == "aapcs16"); 4926 return true; 4927 } 4928 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4929 setABIAAPCS(); 4930 return true; 4931 } 4932 return false; 4933 } 4934 4935 // FIXME: This should be based on Arch attributes, not CPU names. 4936 bool 4937 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4938 StringRef CPU, 4939 const std::vector<std::string> &FeaturesVec) const override { 4940 4941 std::vector<const char*> TargetFeatures; 4942 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4943 4944 // get default FPU features 4945 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4946 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4947 4948 // get default Extension features 4949 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 4950 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4951 4952 for (const char *Feature : TargetFeatures) 4953 if (Feature[0] == '+') 4954 Features[Feature+1] = true; 4955 4956 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4957 } 4958 4959 bool handleTargetFeatures(std::vector<std::string> &Features, 4960 DiagnosticsEngine &Diags) override { 4961 FPU = 0; 4962 CRC = 0; 4963 Crypto = 0; 4964 DSP = 0; 4965 Unaligned = 1; 4966 SoftFloat = SoftFloatABI = false; 4967 HWDiv = 0; 4968 4969 // This does not diagnose illegal cases like having both 4970 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4971 uint32_t HW_FP_remove = 0; 4972 for (const auto &Feature : Features) { 4973 if (Feature == "+soft-float") { 4974 SoftFloat = true; 4975 } else if (Feature == "+soft-float-abi") { 4976 SoftFloatABI = true; 4977 } else if (Feature == "+vfp2") { 4978 FPU |= VFP2FPU; 4979 HW_FP |= HW_FP_SP | HW_FP_DP; 4980 } else if (Feature == "+vfp3") { 4981 FPU |= VFP3FPU; 4982 HW_FP |= HW_FP_SP | HW_FP_DP; 4983 } else if (Feature == "+vfp4") { 4984 FPU |= VFP4FPU; 4985 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4986 } else if (Feature == "+fp-armv8") { 4987 FPU |= FPARMV8; 4988 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4989 } else if (Feature == "+neon") { 4990 FPU |= NeonFPU; 4991 HW_FP |= HW_FP_SP | HW_FP_DP; 4992 } else if (Feature == "+hwdiv") { 4993 HWDiv |= HWDivThumb; 4994 } else if (Feature == "+hwdiv-arm") { 4995 HWDiv |= HWDivARM; 4996 } else if (Feature == "+crc") { 4997 CRC = 1; 4998 } else if (Feature == "+crypto") { 4999 Crypto = 1; 5000 } else if (Feature == "+dsp") { 5001 DSP = 1; 5002 } else if (Feature == "+fp-only-sp") { 5003 HW_FP_remove |= HW_FP_DP; 5004 } else if (Feature == "+strict-align") { 5005 Unaligned = 0; 5006 } else if (Feature == "+fp16") { 5007 HW_FP |= HW_FP_HP; 5008 } 5009 } 5010 HW_FP &= ~HW_FP_remove; 5011 5012 switch (ArchVersion) { 5013 case 6: 5014 if (ArchProfile == llvm::ARM::PK_M) 5015 LDREX = 0; 5016 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5017 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5018 else 5019 LDREX = LDREX_W; 5020 break; 5021 case 7: 5022 if (ArchProfile == llvm::ARM::PK_M) 5023 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5024 else 5025 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5026 break; 5027 case 8: 5028 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5029 } 5030 5031 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5032 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5033 return false; 5034 } 5035 5036 if (FPMath == FP_Neon) 5037 Features.push_back("+neonfp"); 5038 else if (FPMath == FP_VFP) 5039 Features.push_back("-neonfp"); 5040 5041 // Remove front-end specific options which the backend handles differently. 5042 auto Feature = 5043 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5044 if (Feature != Features.end()) 5045 Features.erase(Feature); 5046 5047 return true; 5048 } 5049 5050 bool hasFeature(StringRef Feature) const override { 5051 return llvm::StringSwitch<bool>(Feature) 5052 .Case("arm", true) 5053 .Case("aarch32", true) 5054 .Case("softfloat", SoftFloat) 5055 .Case("thumb", isThumb()) 5056 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5057 .Case("hwdiv", HWDiv & HWDivThumb) 5058 .Case("hwdiv-arm", HWDiv & HWDivARM) 5059 .Default(false); 5060 } 5061 5062 bool setCPU(const std::string &Name) override { 5063 if (Name != "generic") 5064 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5065 5066 if (ArchKind == llvm::ARM::AK_INVALID) 5067 return false; 5068 setAtomic(); 5069 CPU = Name; 5070 return true; 5071 } 5072 5073 bool setFPMath(StringRef Name) override; 5074 5075 void getTargetDefines(const LangOptions &Opts, 5076 MacroBuilder &Builder) const override { 5077 // Target identification. 5078 Builder.defineMacro("__arm"); 5079 Builder.defineMacro("__arm__"); 5080 // For bare-metal none-eabi. 5081 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5082 getTriple().getEnvironment() == llvm::Triple::EABI) 5083 Builder.defineMacro("__ELF__"); 5084 5085 // Target properties. 5086 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5087 5088 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5089 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5090 if (getTriple().isWatchABI()) 5091 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5092 5093 if (!CPUAttr.empty()) 5094 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5095 5096 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5097 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5098 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5099 5100 if (ArchVersion >= 8) { 5101 // ACLE 6.5.7 Crypto Extension 5102 if (Crypto) 5103 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5104 // ACLE 6.5.8 CRC32 Extension 5105 if (CRC) 5106 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5107 // ACLE 6.5.10 Numeric Maximum and Minimum 5108 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5109 // ACLE 6.5.9 Directed Rounding 5110 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5111 } 5112 5113 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5114 // is not defined for the M-profile. 5115 // NOTE that the default profile is assumed to be 'A' 5116 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5117 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5118 5119 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5120 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5121 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5122 // v7 and v8 architectures excluding v8-M Baseline. 5123 if (supportsThumb2()) 5124 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5125 else if (supportsThumb()) 5126 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5127 5128 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5129 // instruction set such as ARM or Thumb. 5130 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5131 5132 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5133 5134 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5135 if (!CPUProfile.empty()) 5136 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5137 5138 // ACLE 6.4.3 Unaligned access supported in hardware 5139 if (Unaligned) 5140 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5141 5142 // ACLE 6.4.4 LDREX/STREX 5143 if (LDREX) 5144 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5145 5146 // ACLE 6.4.5 CLZ 5147 if (ArchVersion == 5 || 5148 (ArchVersion == 6 && CPUProfile != "M") || 5149 ArchVersion > 6) 5150 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5151 5152 // ACLE 6.5.1 Hardware Floating Point 5153 if (HW_FP) 5154 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5155 5156 // ACLE predefines. 5157 Builder.defineMacro("__ARM_ACLE", "200"); 5158 5159 // FP16 support (we currently only support IEEE format). 5160 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5161 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5162 5163 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5164 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5165 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5166 5167 // Subtarget options. 5168 5169 // FIXME: It's more complicated than this and we don't really support 5170 // interworking. 5171 // Windows on ARM does not "support" interworking 5172 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5173 Builder.defineMacro("__THUMB_INTERWORK__"); 5174 5175 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5176 // Embedded targets on Darwin follow AAPCS, but not EABI. 5177 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5178 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5179 Builder.defineMacro("__ARM_EABI__"); 5180 Builder.defineMacro("__ARM_PCS", "1"); 5181 } 5182 5183 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5184 ABI == "aapcs16") 5185 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5186 5187 if (SoftFloat) 5188 Builder.defineMacro("__SOFTFP__"); 5189 5190 if (CPU == "xscale") 5191 Builder.defineMacro("__XSCALE__"); 5192 5193 if (isThumb()) { 5194 Builder.defineMacro("__THUMBEL__"); 5195 Builder.defineMacro("__thumb__"); 5196 if (supportsThumb2()) 5197 Builder.defineMacro("__thumb2__"); 5198 } 5199 5200 // ACLE 6.4.9 32-bit SIMD instructions 5201 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5202 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5203 5204 // ACLE 6.4.10 Hardware Integer Divide 5205 if (((HWDiv & HWDivThumb) && isThumb()) || 5206 ((HWDiv & HWDivARM) && !isThumb())) { 5207 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5208 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5209 } 5210 5211 // Note, this is always on in gcc, even though it doesn't make sense. 5212 Builder.defineMacro("__APCS_32__"); 5213 5214 if (FPUModeIsVFP((FPUMode) FPU)) { 5215 Builder.defineMacro("__VFP_FP__"); 5216 if (FPU & VFP2FPU) 5217 Builder.defineMacro("__ARM_VFPV2__"); 5218 if (FPU & VFP3FPU) 5219 Builder.defineMacro("__ARM_VFPV3__"); 5220 if (FPU & VFP4FPU) 5221 Builder.defineMacro("__ARM_VFPV4__"); 5222 } 5223 5224 // This only gets set when Neon instructions are actually available, unlike 5225 // the VFP define, hence the soft float and arch check. This is subtly 5226 // different from gcc, we follow the intent which was that it should be set 5227 // when Neon instructions are actually available. 5228 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5229 Builder.defineMacro("__ARM_NEON", "1"); 5230 Builder.defineMacro("__ARM_NEON__"); 5231 // current AArch32 NEON implementations do not support double-precision 5232 // floating-point even when it is present in VFP. 5233 Builder.defineMacro("__ARM_NEON_FP", 5234 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5235 } 5236 5237 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5238 Opts.ShortWChar ? "2" : "4"); 5239 5240 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5241 Opts.ShortEnums ? "1" : "4"); 5242 5243 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5244 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5245 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5246 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5247 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5248 } 5249 5250 // ACLE 6.4.7 DSP instructions 5251 if (DSP) { 5252 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5253 } 5254 5255 // ACLE 6.4.8 Saturation instructions 5256 bool SAT = false; 5257 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5258 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5259 SAT = true; 5260 } 5261 5262 // ACLE 6.4.6 Q (saturation) flag 5263 if (DSP || SAT) 5264 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5265 5266 if (Opts.UnsafeFPMath) 5267 Builder.defineMacro("__ARM_FP_FAST", "1"); 5268 5269 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5270 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5271 } 5272 5273 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5274 return llvm::makeArrayRef(BuiltinInfo, 5275 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5276 } 5277 bool isCLZForZeroUndef() const override { return false; } 5278 BuiltinVaListKind getBuiltinVaListKind() const override { 5279 return IsAAPCS 5280 ? AAPCSABIBuiltinVaList 5281 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5282 : TargetInfo::VoidPtrBuiltinVaList); 5283 } 5284 ArrayRef<const char *> getGCCRegNames() const override; 5285 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5286 bool validateAsmConstraint(const char *&Name, 5287 TargetInfo::ConstraintInfo &Info) const override { 5288 switch (*Name) { 5289 default: break; 5290 case 'l': // r0-r7 5291 case 'h': // r8-r15 5292 case 't': // VFP Floating point register single precision 5293 case 'w': // VFP Floating point register double precision 5294 Info.setAllowsRegister(); 5295 return true; 5296 case 'I': 5297 case 'J': 5298 case 'K': 5299 case 'L': 5300 case 'M': 5301 // FIXME 5302 return true; 5303 case 'Q': // A memory address that is a single base register. 5304 Info.setAllowsMemory(); 5305 return true; 5306 case 'U': // a memory reference... 5307 switch (Name[1]) { 5308 case 'q': // ...ARMV4 ldrsb 5309 case 'v': // ...VFP load/store (reg+constant offset) 5310 case 'y': // ...iWMMXt load/store 5311 case 't': // address valid for load/store opaque types wider 5312 // than 128-bits 5313 case 'n': // valid address for Neon doubleword vector load/store 5314 case 'm': // valid address for Neon element and structure load/store 5315 case 's': // valid address for non-offset loads/stores of quad-word 5316 // values in four ARM registers 5317 Info.setAllowsMemory(); 5318 Name++; 5319 return true; 5320 } 5321 } 5322 return false; 5323 } 5324 std::string convertConstraint(const char *&Constraint) const override { 5325 std::string R; 5326 switch (*Constraint) { 5327 case 'U': // Two-character constraint; add "^" hint for later parsing. 5328 R = std::string("^") + std::string(Constraint, 2); 5329 Constraint++; 5330 break; 5331 case 'p': // 'p' should be translated to 'r' by default. 5332 R = std::string("r"); 5333 break; 5334 default: 5335 return std::string(1, *Constraint); 5336 } 5337 return R; 5338 } 5339 bool 5340 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5341 std::string &SuggestedModifier) const override { 5342 bool isOutput = (Constraint[0] == '='); 5343 bool isInOut = (Constraint[0] == '+'); 5344 5345 // Strip off constraint modifiers. 5346 while (Constraint[0] == '=' || 5347 Constraint[0] == '+' || 5348 Constraint[0] == '&') 5349 Constraint = Constraint.substr(1); 5350 5351 switch (Constraint[0]) { 5352 default: break; 5353 case 'r': { 5354 switch (Modifier) { 5355 default: 5356 return (isInOut || isOutput || Size <= 64); 5357 case 'q': 5358 // A register of size 32 cannot fit a vector type. 5359 return false; 5360 } 5361 } 5362 } 5363 5364 return true; 5365 } 5366 const char *getClobbers() const override { 5367 // FIXME: Is this really right? 5368 return ""; 5369 } 5370 5371 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5372 switch (CC) { 5373 case CC_AAPCS: 5374 case CC_AAPCS_VFP: 5375 case CC_Swift: 5376 return CCCR_OK; 5377 default: 5378 return CCCR_Warning; 5379 } 5380 } 5381 5382 int getEHDataRegisterNumber(unsigned RegNo) const override { 5383 if (RegNo == 0) return 0; 5384 if (RegNo == 1) return 1; 5385 return -1; 5386 } 5387 5388 bool hasSjLjLowering() const override { 5389 return true; 5390 } 5391 }; 5392 5393 bool ARMTargetInfo::setFPMath(StringRef Name) { 5394 if (Name == "neon") { 5395 FPMath = FP_Neon; 5396 return true; 5397 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5398 Name == "vfp4") { 5399 FPMath = FP_VFP; 5400 return true; 5401 } 5402 return false; 5403 } 5404 5405 const char * const ARMTargetInfo::GCCRegNames[] = { 5406 // Integer registers 5407 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5408 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5409 5410 // Float registers 5411 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5412 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5413 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5414 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5415 5416 // Double registers 5417 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5418 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5419 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5420 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5421 5422 // Quad registers 5423 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5424 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5425 }; 5426 5427 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5428 return llvm::makeArrayRef(GCCRegNames); 5429 } 5430 5431 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5432 { { "a1" }, "r0" }, 5433 { { "a2" }, "r1" }, 5434 { { "a3" }, "r2" }, 5435 { { "a4" }, "r3" }, 5436 { { "v1" }, "r4" }, 5437 { { "v2" }, "r5" }, 5438 { { "v3" }, "r6" }, 5439 { { "v4" }, "r7" }, 5440 { { "v5" }, "r8" }, 5441 { { "v6", "rfp" }, "r9" }, 5442 { { "sl" }, "r10" }, 5443 { { "fp" }, "r11" }, 5444 { { "ip" }, "r12" }, 5445 { { "r13" }, "sp" }, 5446 { { "r14" }, "lr" }, 5447 { { "r15" }, "pc" }, 5448 // The S, D and Q registers overlap, but aren't really aliases; we 5449 // don't want to substitute one of these for a different-sized one. 5450 }; 5451 5452 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5453 return llvm::makeArrayRef(GCCRegAliases); 5454 } 5455 5456 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5457 #define BUILTIN(ID, TYPE, ATTRS) \ 5458 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5459 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5460 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5461 #include "clang/Basic/BuiltinsNEON.def" 5462 5463 #define BUILTIN(ID, TYPE, ATTRS) \ 5464 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5465 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5466 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5467 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5468 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5469 #include "clang/Basic/BuiltinsARM.def" 5470 }; 5471 5472 class ARMleTargetInfo : public ARMTargetInfo { 5473 public: 5474 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5475 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/false) {} 5476 void getTargetDefines(const LangOptions &Opts, 5477 MacroBuilder &Builder) const override { 5478 Builder.defineMacro("__ARMEL__"); 5479 ARMTargetInfo::getTargetDefines(Opts, Builder); 5480 } 5481 }; 5482 5483 class ARMbeTargetInfo : public ARMTargetInfo { 5484 public: 5485 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5486 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/true) {} 5487 void getTargetDefines(const LangOptions &Opts, 5488 MacroBuilder &Builder) const override { 5489 Builder.defineMacro("__ARMEB__"); 5490 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5491 ARMTargetInfo::getTargetDefines(Opts, Builder); 5492 } 5493 }; 5494 5495 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5496 const llvm::Triple Triple; 5497 public: 5498 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5499 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5500 WCharType = UnsignedShort; 5501 SizeType = UnsignedInt; 5502 } 5503 void getVisualStudioDefines(const LangOptions &Opts, 5504 MacroBuilder &Builder) const { 5505 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5506 5507 // FIXME: this is invalid for WindowsCE 5508 Builder.defineMacro("_M_ARM_NT", "1"); 5509 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5510 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5511 5512 assert((Triple.getArch() == llvm::Triple::arm || 5513 Triple.getArch() == llvm::Triple::thumb) && 5514 "invalid architecture for Windows ARM target info"); 5515 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5516 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5517 5518 // TODO map the complete set of values 5519 // 31: VFPv3 40: VFPv4 5520 Builder.defineMacro("_M_ARM_FP", "31"); 5521 } 5522 BuiltinVaListKind getBuiltinVaListKind() const override { 5523 return TargetInfo::CharPtrBuiltinVaList; 5524 } 5525 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5526 switch (CC) { 5527 case CC_X86StdCall: 5528 case CC_X86ThisCall: 5529 case CC_X86FastCall: 5530 case CC_X86VectorCall: 5531 return CCCR_Ignore; 5532 case CC_C: 5533 return CCCR_OK; 5534 default: 5535 return CCCR_Warning; 5536 } 5537 } 5538 }; 5539 5540 // Windows ARM + Itanium C++ ABI Target 5541 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5542 public: 5543 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5544 const TargetOptions &Opts) 5545 : WindowsARMTargetInfo(Triple, Opts) { 5546 TheCXXABI.set(TargetCXXABI::GenericARM); 5547 } 5548 5549 void getTargetDefines(const LangOptions &Opts, 5550 MacroBuilder &Builder) const override { 5551 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5552 5553 if (Opts.MSVCCompat) 5554 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5555 } 5556 }; 5557 5558 // Windows ARM, MS (C++) ABI 5559 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5560 public: 5561 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5562 const TargetOptions &Opts) 5563 : WindowsARMTargetInfo(Triple, Opts) { 5564 TheCXXABI.set(TargetCXXABI::Microsoft); 5565 } 5566 5567 void getTargetDefines(const LangOptions &Opts, 5568 MacroBuilder &Builder) const override { 5569 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5570 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5571 } 5572 }; 5573 5574 // ARM MinGW target 5575 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5576 public: 5577 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5578 : WindowsARMTargetInfo(Triple, Opts) { 5579 TheCXXABI.set(TargetCXXABI::GenericARM); 5580 } 5581 5582 void getTargetDefines(const LangOptions &Opts, 5583 MacroBuilder &Builder) const override { 5584 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5585 DefineStd(Builder, "WIN32", Opts); 5586 DefineStd(Builder, "WINNT", Opts); 5587 Builder.defineMacro("_ARM_"); 5588 addMinGWDefines(Opts, Builder); 5589 } 5590 }; 5591 5592 // ARM Cygwin target 5593 class CygwinARMTargetInfo : public ARMleTargetInfo { 5594 public: 5595 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5596 : ARMleTargetInfo(Triple, Opts) { 5597 TLSSupported = false; 5598 WCharType = UnsignedShort; 5599 DoubleAlign = LongLongAlign = 64; 5600 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5601 } 5602 void getTargetDefines(const LangOptions &Opts, 5603 MacroBuilder &Builder) const override { 5604 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5605 Builder.defineMacro("_ARM_"); 5606 Builder.defineMacro("__CYGWIN__"); 5607 Builder.defineMacro("__CYGWIN32__"); 5608 DefineStd(Builder, "unix", Opts); 5609 if (Opts.CPlusPlus) 5610 Builder.defineMacro("_GNU_SOURCE"); 5611 } 5612 }; 5613 5614 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 5615 protected: 5616 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5617 MacroBuilder &Builder) const override { 5618 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5619 } 5620 5621 public: 5622 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5623 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 5624 HasAlignMac68kSupport = true; 5625 // iOS always has 64-bit atomic instructions. 5626 // FIXME: This should be based off of the target features in 5627 // ARMleTargetInfo. 5628 MaxAtomicInlineWidth = 64; 5629 5630 if (Triple.isWatchABI()) { 5631 // Darwin on iOS uses a variant of the ARM C++ ABI. 5632 TheCXXABI.set(TargetCXXABI::WatchOS); 5633 5634 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5635 // size_t is long, it's a bit weird for it to be int. 5636 PtrDiffType = SignedLong; 5637 5638 // BOOL should be a real boolean on the new ABI 5639 UseSignedCharForObjCBool = false; 5640 } else 5641 TheCXXABI.set(TargetCXXABI::iOS); 5642 } 5643 }; 5644 5645 class AArch64TargetInfo : public TargetInfo { 5646 virtual void setDataLayout() = 0; 5647 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5648 static const char *const GCCRegNames[]; 5649 5650 enum FPUModeEnum { 5651 FPUMode, 5652 NeonMode 5653 }; 5654 5655 unsigned FPU; 5656 unsigned CRC; 5657 unsigned Crypto; 5658 unsigned Unaligned; 5659 unsigned V8_1A; 5660 5661 static const Builtin::Info BuiltinInfo[]; 5662 5663 std::string ABI; 5664 5665 public: 5666 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5667 : TargetInfo(Triple), ABI("aapcs") { 5668 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5669 WCharType = SignedInt; 5670 5671 // NetBSD apparently prefers consistency across ARM targets to consistency 5672 // across 64-bit targets. 5673 Int64Type = SignedLongLong; 5674 IntMaxType = SignedLongLong; 5675 } else { 5676 WCharType = UnsignedInt; 5677 Int64Type = SignedLong; 5678 IntMaxType = SignedLong; 5679 } 5680 5681 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5682 MaxVectorAlign = 128; 5683 MaxAtomicInlineWidth = 128; 5684 MaxAtomicPromoteWidth = 128; 5685 5686 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5687 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5688 5689 // {} in inline assembly are neon specifiers, not assembly variant 5690 // specifiers. 5691 NoAsmVariants = true; 5692 5693 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5694 // contributes to the alignment of the containing aggregate in the same way 5695 // a plain (non bit-field) member of that type would, without exception for 5696 // zero-sized or anonymous bit-fields." 5697 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5698 UseZeroLengthBitfieldAlignment = true; 5699 5700 // AArch64 targets default to using the ARM C++ ABI. 5701 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5702 5703 if (Triple.getOS() == llvm::Triple::Linux || 5704 Triple.getOS() == llvm::Triple::UnknownOS) 5705 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 5706 } 5707 5708 StringRef getABI() const override { return ABI; } 5709 bool setABI(const std::string &Name) override { 5710 if (Name != "aapcs" && Name != "darwinpcs") 5711 return false; 5712 5713 ABI = Name; 5714 return true; 5715 } 5716 5717 bool setCPU(const std::string &Name) override { 5718 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5719 .Case("generic", true) 5720 .Cases("cortex-a53", "cortex-a57", "cortex-a72", 5721 "cortex-a35", "exynos-m1", true) 5722 .Case("cortex-a73", true) 5723 .Case("cyclone", true) 5724 .Case("kryo", true) 5725 .Default(false); 5726 return CPUKnown; 5727 } 5728 5729 void getTargetDefines(const LangOptions &Opts, 5730 MacroBuilder &Builder) const override { 5731 // Target identification. 5732 Builder.defineMacro("__aarch64__"); 5733 5734 // Target properties. 5735 Builder.defineMacro("_LP64"); 5736 Builder.defineMacro("__LP64__"); 5737 5738 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5739 Builder.defineMacro("__ARM_ACLE", "200"); 5740 Builder.defineMacro("__ARM_ARCH", "8"); 5741 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5742 5743 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5744 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5745 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5746 5747 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5748 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5749 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5750 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5751 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5752 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5753 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5754 5755 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5756 5757 // 0xe implies support for half, single and double precision operations. 5758 Builder.defineMacro("__ARM_FP", "0xE"); 5759 5760 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5761 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5762 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5763 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5764 5765 if (Opts.UnsafeFPMath) 5766 Builder.defineMacro("__ARM_FP_FAST", "1"); 5767 5768 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5769 5770 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5771 Opts.ShortEnums ? "1" : "4"); 5772 5773 if (FPU == NeonMode) { 5774 Builder.defineMacro("__ARM_NEON", "1"); 5775 // 64-bit NEON supports half, single and double precision operations. 5776 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5777 } 5778 5779 if (CRC) 5780 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5781 5782 if (Crypto) 5783 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5784 5785 if (Unaligned) 5786 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5787 5788 if (V8_1A) 5789 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5790 5791 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5792 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5793 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5794 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5795 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5796 } 5797 5798 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5799 return llvm::makeArrayRef(BuiltinInfo, 5800 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5801 } 5802 5803 bool hasFeature(StringRef Feature) const override { 5804 return Feature == "aarch64" || 5805 Feature == "arm64" || 5806 Feature == "arm" || 5807 (Feature == "neon" && FPU == NeonMode); 5808 } 5809 5810 bool handleTargetFeatures(std::vector<std::string> &Features, 5811 DiagnosticsEngine &Diags) override { 5812 FPU = FPUMode; 5813 CRC = 0; 5814 Crypto = 0; 5815 Unaligned = 1; 5816 V8_1A = 0; 5817 5818 for (const auto &Feature : Features) { 5819 if (Feature == "+neon") 5820 FPU = NeonMode; 5821 if (Feature == "+crc") 5822 CRC = 1; 5823 if (Feature == "+crypto") 5824 Crypto = 1; 5825 if (Feature == "+strict-align") 5826 Unaligned = 0; 5827 if (Feature == "+v8.1a") 5828 V8_1A = 1; 5829 } 5830 5831 setDataLayout(); 5832 5833 return true; 5834 } 5835 5836 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5837 switch (CC) { 5838 case CC_C: 5839 case CC_Swift: 5840 case CC_PreserveMost: 5841 case CC_PreserveAll: 5842 return CCCR_OK; 5843 default: 5844 return CCCR_Warning; 5845 } 5846 } 5847 5848 bool isCLZForZeroUndef() const override { return false; } 5849 5850 BuiltinVaListKind getBuiltinVaListKind() const override { 5851 return TargetInfo::AArch64ABIBuiltinVaList; 5852 } 5853 5854 ArrayRef<const char *> getGCCRegNames() const override; 5855 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5856 5857 bool validateAsmConstraint(const char *&Name, 5858 TargetInfo::ConstraintInfo &Info) const override { 5859 switch (*Name) { 5860 default: 5861 return false; 5862 case 'w': // Floating point and SIMD registers (V0-V31) 5863 Info.setAllowsRegister(); 5864 return true; 5865 case 'I': // Constant that can be used with an ADD instruction 5866 case 'J': // Constant that can be used with a SUB instruction 5867 case 'K': // Constant that can be used with a 32-bit logical instruction 5868 case 'L': // Constant that can be used with a 64-bit logical instruction 5869 case 'M': // Constant that can be used as a 32-bit MOV immediate 5870 case 'N': // Constant that can be used as a 64-bit MOV immediate 5871 case 'Y': // Floating point constant zero 5872 case 'Z': // Integer constant zero 5873 return true; 5874 case 'Q': // A memory reference with base register and no offset 5875 Info.setAllowsMemory(); 5876 return true; 5877 case 'S': // A symbolic address 5878 Info.setAllowsRegister(); 5879 return true; 5880 case 'U': 5881 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5882 // Utf: A memory address suitable for ldp/stp in TF mode. 5883 // Usa: An absolute symbolic address. 5884 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5885 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5886 case 'z': // Zero register, wzr or xzr 5887 Info.setAllowsRegister(); 5888 return true; 5889 case 'x': // Floating point and SIMD registers (V0-V15) 5890 Info.setAllowsRegister(); 5891 return true; 5892 } 5893 return false; 5894 } 5895 5896 bool 5897 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5898 std::string &SuggestedModifier) const override { 5899 // Strip off constraint modifiers. 5900 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5901 Constraint = Constraint.substr(1); 5902 5903 switch (Constraint[0]) { 5904 default: 5905 return true; 5906 case 'z': 5907 case 'r': { 5908 switch (Modifier) { 5909 case 'x': 5910 case 'w': 5911 // For now assume that the person knows what they're 5912 // doing with the modifier. 5913 return true; 5914 default: 5915 // By default an 'r' constraint will be in the 'x' 5916 // registers. 5917 if (Size == 64) 5918 return true; 5919 5920 SuggestedModifier = "w"; 5921 return false; 5922 } 5923 } 5924 } 5925 } 5926 5927 const char *getClobbers() const override { return ""; } 5928 5929 int getEHDataRegisterNumber(unsigned RegNo) const override { 5930 if (RegNo == 0) 5931 return 0; 5932 if (RegNo == 1) 5933 return 1; 5934 return -1; 5935 } 5936 }; 5937 5938 const char *const AArch64TargetInfo::GCCRegNames[] = { 5939 // 32-bit Integer registers 5940 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5941 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5942 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5943 5944 // 64-bit Integer registers 5945 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5946 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5947 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5948 5949 // 32-bit floating point regsisters 5950 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5951 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5952 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5953 5954 // 64-bit floating point regsisters 5955 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5956 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5957 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5958 5959 // Vector registers 5960 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5961 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5962 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5963 }; 5964 5965 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 5966 return llvm::makeArrayRef(GCCRegNames); 5967 } 5968 5969 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5970 { { "w31" }, "wsp" }, 5971 { { "x29" }, "fp" }, 5972 { { "x30" }, "lr" }, 5973 { { "x31" }, "sp" }, 5974 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5975 // don't want to substitute one of these for a different-sized one. 5976 }; 5977 5978 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 5979 return llvm::makeArrayRef(GCCRegAliases); 5980 } 5981 5982 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5983 #define BUILTIN(ID, TYPE, ATTRS) \ 5984 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5985 #include "clang/Basic/BuiltinsNEON.def" 5986 5987 #define BUILTIN(ID, TYPE, ATTRS) \ 5988 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5989 #include "clang/Basic/BuiltinsAArch64.def" 5990 }; 5991 5992 class AArch64leTargetInfo : public AArch64TargetInfo { 5993 void setDataLayout() override { 5994 if (getTriple().isOSBinFormatMachO()) 5995 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 5996 else 5997 resetDataLayout("e-m:e-i64:64-i128:128-n32:64-S128"); 5998 } 5999 6000 public: 6001 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6002 : AArch64TargetInfo(Triple, Opts) { 6003 BigEndian = false; 6004 } 6005 void getTargetDefines(const LangOptions &Opts, 6006 MacroBuilder &Builder) const override { 6007 Builder.defineMacro("__AARCH64EL__"); 6008 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6009 } 6010 }; 6011 6012 class AArch64beTargetInfo : public AArch64TargetInfo { 6013 void setDataLayout() override { 6014 assert(!getTriple().isOSBinFormatMachO()); 6015 resetDataLayout("E-m:e-i64:64-i128:128-n32:64-S128"); 6016 } 6017 6018 public: 6019 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6020 : AArch64TargetInfo(Triple, Opts) {} 6021 void getTargetDefines(const LangOptions &Opts, 6022 MacroBuilder &Builder) const override { 6023 Builder.defineMacro("__AARCH64EB__"); 6024 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6025 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6026 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6027 } 6028 }; 6029 6030 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6031 protected: 6032 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6033 MacroBuilder &Builder) const override { 6034 Builder.defineMacro("__AARCH64_SIMD__"); 6035 Builder.defineMacro("__ARM64_ARCH_8__"); 6036 Builder.defineMacro("__ARM_NEON__"); 6037 Builder.defineMacro("__LITTLE_ENDIAN__"); 6038 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6039 Builder.defineMacro("__arm64", "1"); 6040 Builder.defineMacro("__arm64__", "1"); 6041 6042 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6043 } 6044 6045 public: 6046 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6047 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6048 Int64Type = SignedLongLong; 6049 WCharType = SignedInt; 6050 UseSignedCharForObjCBool = false; 6051 6052 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6053 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6054 6055 TheCXXABI.set(TargetCXXABI::iOS64); 6056 } 6057 6058 BuiltinVaListKind getBuiltinVaListKind() const override { 6059 return TargetInfo::CharPtrBuiltinVaList; 6060 } 6061 }; 6062 6063 // Hexagon abstract base class 6064 class HexagonTargetInfo : public TargetInfo { 6065 static const Builtin::Info BuiltinInfo[]; 6066 static const char * const GCCRegNames[]; 6067 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6068 std::string CPU; 6069 bool HasHVX, HasHVXDouble; 6070 6071 public: 6072 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6073 : TargetInfo(Triple) { 6074 BigEndian = false; 6075 // Specify the vector alignment explicitly. For v512x1, the calculated 6076 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6077 // the required minimum of 64 bytes. 6078 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6079 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6080 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6081 SizeType = UnsignedInt; 6082 PtrDiffType = SignedInt; 6083 IntPtrType = SignedInt; 6084 6085 // {} in inline assembly are packet specifiers, not assembly variant 6086 // specifiers. 6087 NoAsmVariants = true; 6088 6089 LargeArrayMinWidth = 64; 6090 LargeArrayAlign = 64; 6091 UseBitFieldTypeAlignment = true; 6092 ZeroLengthBitfieldBoundary = 32; 6093 HasHVX = HasHVXDouble = false; 6094 } 6095 6096 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6097 return llvm::makeArrayRef(BuiltinInfo, 6098 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6099 } 6100 6101 bool validateAsmConstraint(const char *&Name, 6102 TargetInfo::ConstraintInfo &Info) const override { 6103 switch (*Name) { 6104 case 'v': 6105 case 'q': 6106 if (HasHVX) { 6107 Info.setAllowsRegister(); 6108 return true; 6109 } 6110 break; 6111 case 's': 6112 // Relocatable constant. 6113 return true; 6114 } 6115 return false; 6116 } 6117 6118 void getTargetDefines(const LangOptions &Opts, 6119 MacroBuilder &Builder) const override; 6120 6121 bool isCLZForZeroUndef() const override { return false; } 6122 6123 bool hasFeature(StringRef Feature) const override { 6124 return llvm::StringSwitch<bool>(Feature) 6125 .Case("hexagon", true) 6126 .Case("hvx", HasHVX) 6127 .Case("hvx-double", HasHVXDouble) 6128 .Default(false); 6129 } 6130 6131 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6132 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6133 const override; 6134 6135 bool handleTargetFeatures(std::vector<std::string> &Features, 6136 DiagnosticsEngine &Diags) override; 6137 6138 BuiltinVaListKind getBuiltinVaListKind() const override { 6139 return TargetInfo::CharPtrBuiltinVaList; 6140 } 6141 ArrayRef<const char *> getGCCRegNames() const override; 6142 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6143 const char *getClobbers() const override { 6144 return ""; 6145 } 6146 6147 static const char *getHexagonCPUSuffix(StringRef Name) { 6148 return llvm::StringSwitch<const char*>(Name) 6149 .Case("hexagonv4", "4") 6150 .Case("hexagonv5", "5") 6151 .Case("hexagonv55", "55") 6152 .Case("hexagonv60", "60") 6153 .Default(nullptr); 6154 } 6155 6156 bool setCPU(const std::string &Name) override { 6157 if (!getHexagonCPUSuffix(Name)) 6158 return false; 6159 CPU = Name; 6160 return true; 6161 } 6162 6163 int getEHDataRegisterNumber(unsigned RegNo) const override { 6164 return RegNo < 2 ? RegNo : -1; 6165 } 6166 }; 6167 6168 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6169 MacroBuilder &Builder) const { 6170 Builder.defineMacro("__qdsp6__", "1"); 6171 Builder.defineMacro("__hexagon__", "1"); 6172 6173 if (CPU == "hexagonv4") { 6174 Builder.defineMacro("__HEXAGON_V4__"); 6175 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6176 if (Opts.HexagonQdsp6Compat) { 6177 Builder.defineMacro("__QDSP6_V4__"); 6178 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6179 } 6180 } else if (CPU == "hexagonv5") { 6181 Builder.defineMacro("__HEXAGON_V5__"); 6182 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6183 if(Opts.HexagonQdsp6Compat) { 6184 Builder.defineMacro("__QDSP6_V5__"); 6185 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6186 } 6187 } else if (CPU == "hexagonv55") { 6188 Builder.defineMacro("__HEXAGON_V55__"); 6189 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6190 Builder.defineMacro("__QDSP6_V55__"); 6191 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6192 } else if (CPU == "hexagonv60") { 6193 Builder.defineMacro("__HEXAGON_V60__"); 6194 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6195 Builder.defineMacro("__QDSP6_V60__"); 6196 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6197 } 6198 6199 if (hasFeature("hvx")) { 6200 Builder.defineMacro("__HVX__"); 6201 if (hasFeature("hvx-double")) 6202 Builder.defineMacro("__HVXDBL__"); 6203 } 6204 } 6205 6206 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6207 DiagnosticsEngine &Diags) { 6208 for (auto &F : Features) { 6209 if (F == "+hvx") 6210 HasHVX = true; 6211 else if (F == "-hvx") 6212 HasHVX = HasHVXDouble = false; 6213 else if (F == "+hvx-double") 6214 HasHVX = HasHVXDouble = true; 6215 else if (F == "-hvx-double") 6216 HasHVXDouble = false; 6217 } 6218 return true; 6219 } 6220 6221 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6222 DiagnosticsEngine &Diags, StringRef CPU, 6223 const std::vector<std::string> &FeaturesVec) const { 6224 // Default for v60: -hvx, -hvx-double. 6225 Features["hvx"] = false; 6226 Features["hvx-double"] = false; 6227 6228 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6229 } 6230 6231 6232 const char *const HexagonTargetInfo::GCCRegNames[] = { 6233 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6234 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6235 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6236 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6237 "p0", "p1", "p2", "p3", 6238 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6239 }; 6240 6241 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6242 return llvm::makeArrayRef(GCCRegNames); 6243 } 6244 6245 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6246 { { "sp" }, "r29" }, 6247 { { "fp" }, "r30" }, 6248 { { "lr" }, "r31" }, 6249 }; 6250 6251 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6252 return llvm::makeArrayRef(GCCRegAliases); 6253 } 6254 6255 6256 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6257 #define BUILTIN(ID, TYPE, ATTRS) \ 6258 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6259 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6260 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6261 #include "clang/Basic/BuiltinsHexagon.def" 6262 }; 6263 6264 class LanaiTargetInfo : public TargetInfo { 6265 // Class for Lanai (32-bit). 6266 // The CPU profiles supported by the Lanai backend 6267 enum CPUKind { 6268 CK_NONE, 6269 CK_V11, 6270 } CPU; 6271 6272 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6273 static const char *const GCCRegNames[]; 6274 6275 public: 6276 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6277 : TargetInfo(Triple) { 6278 // Description string has to be kept in sync with backend. 6279 resetDataLayout("E" // Big endian 6280 "-m:e" // ELF name manging 6281 "-p:32:32" // 32 bit pointers, 32 bit aligned 6282 "-i64:64" // 64 bit integers, 64 bit aligned 6283 "-a:0:32" // 32 bit alignment of objects of aggregate type 6284 "-n32" // 32 bit native integer width 6285 "-S64" // 64 bit natural stack alignment 6286 ); 6287 6288 // Setting RegParmMax equal to what mregparm was set to in the old 6289 // toolchain 6290 RegParmMax = 4; 6291 6292 // Set the default CPU to V11 6293 CPU = CK_V11; 6294 6295 // Temporary approach to make everything at least word-aligned and allow for 6296 // safely casting between pointers with different alignment requirements. 6297 // TODO: Remove this when there are no more cast align warnings on the 6298 // firmware. 6299 MinGlobalAlign = 32; 6300 } 6301 6302 void getTargetDefines(const LangOptions &Opts, 6303 MacroBuilder &Builder) const override { 6304 // Define __lanai__ when building for target lanai. 6305 Builder.defineMacro("__lanai__"); 6306 6307 // Set define for the CPU specified. 6308 switch (CPU) { 6309 case CK_V11: 6310 Builder.defineMacro("__LANAI_V11__"); 6311 break; 6312 case CK_NONE: 6313 llvm_unreachable("Unhandled target CPU"); 6314 } 6315 } 6316 6317 bool setCPU(const std::string &Name) override { 6318 CPU = llvm::StringSwitch<CPUKind>(Name) 6319 .Case("v11", CK_V11) 6320 .Default(CK_NONE); 6321 6322 return CPU != CK_NONE; 6323 } 6324 6325 bool hasFeature(StringRef Feature) const override { 6326 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6327 } 6328 6329 ArrayRef<const char *> getGCCRegNames() const override; 6330 6331 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6332 6333 BuiltinVaListKind getBuiltinVaListKind() const override { 6334 return TargetInfo::VoidPtrBuiltinVaList; 6335 } 6336 6337 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6338 6339 bool validateAsmConstraint(const char *&Name, 6340 TargetInfo::ConstraintInfo &info) const override { 6341 return false; 6342 } 6343 6344 const char *getClobbers() const override { return ""; } 6345 }; 6346 6347 const char *const LanaiTargetInfo::GCCRegNames[] = { 6348 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6349 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6350 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6351 6352 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6353 return llvm::makeArrayRef(GCCRegNames); 6354 } 6355 6356 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6357 {{"pc"}, "r2"}, 6358 {{"sp"}, "r4"}, 6359 {{"fp"}, "r5"}, 6360 {{"rv"}, "r8"}, 6361 {{"rr1"}, "r10"}, 6362 {{"rr2"}, "r11"}, 6363 {{"rca"}, "r15"}, 6364 }; 6365 6366 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6367 return llvm::makeArrayRef(GCCRegAliases); 6368 } 6369 6370 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6371 class SparcTargetInfo : public TargetInfo { 6372 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6373 static const char * const GCCRegNames[]; 6374 bool SoftFloat; 6375 public: 6376 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6377 : TargetInfo(Triple), SoftFloat(false) {} 6378 6379 int getEHDataRegisterNumber(unsigned RegNo) const override { 6380 if (RegNo == 0) return 24; 6381 if (RegNo == 1) return 25; 6382 return -1; 6383 } 6384 6385 bool handleTargetFeatures(std::vector<std::string> &Features, 6386 DiagnosticsEngine &Diags) override { 6387 // Check if software floating point is enabled 6388 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6389 if (Feature != Features.end()) { 6390 SoftFloat = true; 6391 } 6392 return true; 6393 } 6394 void getTargetDefines(const LangOptions &Opts, 6395 MacroBuilder &Builder) const override { 6396 DefineStd(Builder, "sparc", Opts); 6397 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6398 6399 if (SoftFloat) 6400 Builder.defineMacro("SOFT_FLOAT", "1"); 6401 } 6402 6403 bool hasFeature(StringRef Feature) const override { 6404 return llvm::StringSwitch<bool>(Feature) 6405 .Case("softfloat", SoftFloat) 6406 .Case("sparc", true) 6407 .Default(false); 6408 } 6409 6410 bool hasSjLjLowering() const override { 6411 return true; 6412 } 6413 6414 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6415 // FIXME: Implement! 6416 return None; 6417 } 6418 BuiltinVaListKind getBuiltinVaListKind() const override { 6419 return TargetInfo::VoidPtrBuiltinVaList; 6420 } 6421 ArrayRef<const char *> getGCCRegNames() const override; 6422 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6423 bool validateAsmConstraint(const char *&Name, 6424 TargetInfo::ConstraintInfo &info) const override { 6425 // FIXME: Implement! 6426 switch (*Name) { 6427 case 'I': // Signed 13-bit constant 6428 case 'J': // Zero 6429 case 'K': // 32-bit constant with the low 12 bits clear 6430 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6431 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6432 case 'N': // Same as 'K' but zext (required for SIMode) 6433 case 'O': // The constant 4096 6434 return true; 6435 } 6436 return false; 6437 } 6438 const char *getClobbers() const override { 6439 // FIXME: Implement! 6440 return ""; 6441 } 6442 6443 // No Sparc V7 for now, the backend doesn't support it anyway. 6444 enum CPUKind { 6445 CK_GENERIC, 6446 CK_V8, 6447 CK_SUPERSPARC, 6448 CK_SPARCLITE, 6449 CK_F934, 6450 CK_HYPERSPARC, 6451 CK_SPARCLITE86X, 6452 CK_SPARCLET, 6453 CK_TSC701, 6454 CK_V9, 6455 CK_ULTRASPARC, 6456 CK_ULTRASPARC3, 6457 CK_NIAGARA, 6458 CK_NIAGARA2, 6459 CK_NIAGARA3, 6460 CK_NIAGARA4, 6461 CK_MYRIAD2_1, 6462 CK_MYRIAD2_2 6463 } CPU = CK_GENERIC; 6464 6465 enum CPUGeneration { 6466 CG_V8, 6467 CG_V9, 6468 }; 6469 6470 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6471 switch (Kind) { 6472 case CK_GENERIC: 6473 case CK_V8: 6474 case CK_SUPERSPARC: 6475 case CK_SPARCLITE: 6476 case CK_F934: 6477 case CK_HYPERSPARC: 6478 case CK_SPARCLITE86X: 6479 case CK_SPARCLET: 6480 case CK_TSC701: 6481 case CK_MYRIAD2_1: 6482 case CK_MYRIAD2_2: 6483 return CG_V8; 6484 case CK_V9: 6485 case CK_ULTRASPARC: 6486 case CK_ULTRASPARC3: 6487 case CK_NIAGARA: 6488 case CK_NIAGARA2: 6489 case CK_NIAGARA3: 6490 case CK_NIAGARA4: 6491 return CG_V9; 6492 } 6493 llvm_unreachable("Unexpected CPU kind"); 6494 } 6495 6496 CPUKind getCPUKind(StringRef Name) const { 6497 return llvm::StringSwitch<CPUKind>(Name) 6498 .Case("v8", CK_V8) 6499 .Case("supersparc", CK_SUPERSPARC) 6500 .Case("sparclite", CK_SPARCLITE) 6501 .Case("f934", CK_F934) 6502 .Case("hypersparc", CK_HYPERSPARC) 6503 .Case("sparclite86x", CK_SPARCLITE86X) 6504 .Case("sparclet", CK_SPARCLET) 6505 .Case("tsc701", CK_TSC701) 6506 .Case("v9", CK_V9) 6507 .Case("ultrasparc", CK_ULTRASPARC) 6508 .Case("ultrasparc3", CK_ULTRASPARC3) 6509 .Case("niagara", CK_NIAGARA) 6510 .Case("niagara2", CK_NIAGARA2) 6511 .Case("niagara3", CK_NIAGARA3) 6512 .Case("niagara4", CK_NIAGARA4) 6513 .Case("myriad2", CK_MYRIAD2_1) 6514 .Case("myriad2.1", CK_MYRIAD2_1) 6515 .Case("myriad2.2", CK_MYRIAD2_2) 6516 .Default(CK_GENERIC); 6517 } 6518 6519 bool setCPU(const std::string &Name) override { 6520 CPU = getCPUKind(Name); 6521 return CPU != CK_GENERIC; 6522 } 6523 }; 6524 6525 const char * const SparcTargetInfo::GCCRegNames[] = { 6526 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6527 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6528 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6529 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6530 }; 6531 6532 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6533 return llvm::makeArrayRef(GCCRegNames); 6534 } 6535 6536 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6537 { { "g0" }, "r0" }, 6538 { { "g1" }, "r1" }, 6539 { { "g2" }, "r2" }, 6540 { { "g3" }, "r3" }, 6541 { { "g4" }, "r4" }, 6542 { { "g5" }, "r5" }, 6543 { { "g6" }, "r6" }, 6544 { { "g7" }, "r7" }, 6545 { { "o0" }, "r8" }, 6546 { { "o1" }, "r9" }, 6547 { { "o2" }, "r10" }, 6548 { { "o3" }, "r11" }, 6549 { { "o4" }, "r12" }, 6550 { { "o5" }, "r13" }, 6551 { { "o6", "sp" }, "r14" }, 6552 { { "o7" }, "r15" }, 6553 { { "l0" }, "r16" }, 6554 { { "l1" }, "r17" }, 6555 { { "l2" }, "r18" }, 6556 { { "l3" }, "r19" }, 6557 { { "l4" }, "r20" }, 6558 { { "l5" }, "r21" }, 6559 { { "l6" }, "r22" }, 6560 { { "l7" }, "r23" }, 6561 { { "i0" }, "r24" }, 6562 { { "i1" }, "r25" }, 6563 { { "i2" }, "r26" }, 6564 { { "i3" }, "r27" }, 6565 { { "i4" }, "r28" }, 6566 { { "i5" }, "r29" }, 6567 { { "i6", "fp" }, "r30" }, 6568 { { "i7" }, "r31" }, 6569 }; 6570 6571 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6572 return llvm::makeArrayRef(GCCRegAliases); 6573 } 6574 6575 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6576 class SparcV8TargetInfo : public SparcTargetInfo { 6577 public: 6578 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6579 : SparcTargetInfo(Triple, Opts) { 6580 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6581 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6582 switch (getTriple().getOS()) { 6583 default: 6584 SizeType = UnsignedInt; 6585 IntPtrType = SignedInt; 6586 PtrDiffType = SignedInt; 6587 break; 6588 case llvm::Triple::NetBSD: 6589 case llvm::Triple::OpenBSD: 6590 SizeType = UnsignedLong; 6591 IntPtrType = SignedLong; 6592 PtrDiffType = SignedLong; 6593 break; 6594 } 6595 } 6596 6597 void getTargetDefines(const LangOptions &Opts, 6598 MacroBuilder &Builder) const override { 6599 SparcTargetInfo::getTargetDefines(Opts, Builder); 6600 switch (getCPUGeneration(CPU)) { 6601 case CG_V8: 6602 Builder.defineMacro("__sparcv8"); 6603 if (getTriple().getOS() != llvm::Triple::Solaris) 6604 Builder.defineMacro("__sparcv8__"); 6605 break; 6606 case CG_V9: 6607 Builder.defineMacro("__sparcv9"); 6608 if (getTriple().getOS() != llvm::Triple::Solaris) { 6609 Builder.defineMacro("__sparcv9__"); 6610 Builder.defineMacro("__sparc_v9__"); 6611 } 6612 break; 6613 } 6614 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6615 switch (CPU) { 6616 case CK_MYRIAD2_1: 6617 Builder.defineMacro("__myriad2", "1"); 6618 Builder.defineMacro("__myriad2__", "1"); 6619 break; 6620 case CK_MYRIAD2_2: 6621 Builder.defineMacro("__myriad2", "2"); 6622 Builder.defineMacro("__myriad2__", "2"); 6623 break; 6624 default: 6625 break; 6626 } 6627 } 6628 } 6629 6630 bool hasSjLjLowering() const override { 6631 return true; 6632 } 6633 }; 6634 6635 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6636 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6637 public: 6638 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6639 : SparcV8TargetInfo(Triple, Opts) { 6640 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6641 BigEndian = false; 6642 } 6643 }; 6644 6645 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6646 class SparcV9TargetInfo : public SparcTargetInfo { 6647 public: 6648 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6649 : SparcTargetInfo(Triple, Opts) { 6650 // FIXME: Support Sparc quad-precision long double? 6651 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6652 // This is an LP64 platform. 6653 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6654 6655 // OpenBSD uses long long for int64_t and intmax_t. 6656 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6657 IntMaxType = SignedLongLong; 6658 else 6659 IntMaxType = SignedLong; 6660 Int64Type = IntMaxType; 6661 6662 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6663 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6664 LongDoubleWidth = 128; 6665 LongDoubleAlign = 128; 6666 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6667 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6668 } 6669 6670 void getTargetDefines(const LangOptions &Opts, 6671 MacroBuilder &Builder) const override { 6672 SparcTargetInfo::getTargetDefines(Opts, Builder); 6673 Builder.defineMacro("__sparcv9"); 6674 Builder.defineMacro("__arch64__"); 6675 // Solaris doesn't need these variants, but the BSDs do. 6676 if (getTriple().getOS() != llvm::Triple::Solaris) { 6677 Builder.defineMacro("__sparc64__"); 6678 Builder.defineMacro("__sparc_v9__"); 6679 Builder.defineMacro("__sparcv9__"); 6680 } 6681 } 6682 6683 bool setCPU(const std::string &Name) override { 6684 if (!SparcTargetInfo::setCPU(Name)) 6685 return false; 6686 return getCPUGeneration(CPU) == CG_V9; 6687 } 6688 }; 6689 6690 class SystemZTargetInfo : public TargetInfo { 6691 static const Builtin::Info BuiltinInfo[]; 6692 static const char *const GCCRegNames[]; 6693 std::string CPU; 6694 bool HasTransactionalExecution; 6695 bool HasVector; 6696 6697 public: 6698 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6699 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6700 HasVector(false) { 6701 IntMaxType = SignedLong; 6702 Int64Type = SignedLong; 6703 TLSSupported = true; 6704 IntWidth = IntAlign = 32; 6705 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6706 PointerWidth = PointerAlign = 64; 6707 LongDoubleWidth = 128; 6708 LongDoubleAlign = 64; 6709 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6710 DefaultAlignForAttributeAligned = 64; 6711 MinGlobalAlign = 16; 6712 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 6713 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6714 } 6715 void getTargetDefines(const LangOptions &Opts, 6716 MacroBuilder &Builder) const override { 6717 Builder.defineMacro("__s390__"); 6718 Builder.defineMacro("__s390x__"); 6719 Builder.defineMacro("__zarch__"); 6720 Builder.defineMacro("__LONG_DOUBLE_128__"); 6721 6722 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6723 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6724 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6725 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6726 6727 if (HasTransactionalExecution) 6728 Builder.defineMacro("__HTM__"); 6729 if (Opts.ZVector) 6730 Builder.defineMacro("__VEC__", "10301"); 6731 } 6732 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6733 return llvm::makeArrayRef(BuiltinInfo, 6734 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6735 } 6736 6737 ArrayRef<const char *> getGCCRegNames() const override; 6738 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6739 // No aliases. 6740 return None; 6741 } 6742 bool validateAsmConstraint(const char *&Name, 6743 TargetInfo::ConstraintInfo &info) const override; 6744 const char *getClobbers() const override { 6745 // FIXME: Is this really right? 6746 return ""; 6747 } 6748 BuiltinVaListKind getBuiltinVaListKind() const override { 6749 return TargetInfo::SystemZBuiltinVaList; 6750 } 6751 bool setCPU(const std::string &Name) override { 6752 CPU = Name; 6753 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6754 .Case("z10", true) 6755 .Case("z196", true) 6756 .Case("zEC12", true) 6757 .Case("z13", true) 6758 .Default(false); 6759 6760 return CPUKnown; 6761 } 6762 bool 6763 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6764 StringRef CPU, 6765 const std::vector<std::string> &FeaturesVec) const override { 6766 if (CPU == "zEC12") 6767 Features["transactional-execution"] = true; 6768 if (CPU == "z13") { 6769 Features["transactional-execution"] = true; 6770 Features["vector"] = true; 6771 } 6772 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6773 } 6774 6775 bool handleTargetFeatures(std::vector<std::string> &Features, 6776 DiagnosticsEngine &Diags) override { 6777 HasTransactionalExecution = false; 6778 for (const auto &Feature : Features) { 6779 if (Feature == "+transactional-execution") 6780 HasTransactionalExecution = true; 6781 else if (Feature == "+vector") 6782 HasVector = true; 6783 } 6784 // If we use the vector ABI, vector types are 64-bit aligned. 6785 if (HasVector) { 6786 MaxVectorAlign = 64; 6787 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6788 "-v128:64-a:8:16-n32:64"); 6789 } 6790 return true; 6791 } 6792 6793 bool hasFeature(StringRef Feature) const override { 6794 return llvm::StringSwitch<bool>(Feature) 6795 .Case("systemz", true) 6796 .Case("htm", HasTransactionalExecution) 6797 .Case("vx", HasVector) 6798 .Default(false); 6799 } 6800 6801 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6802 switch (CC) { 6803 case CC_C: 6804 case CC_Swift: 6805 return CCCR_OK; 6806 default: 6807 return CCCR_Warning; 6808 } 6809 } 6810 6811 StringRef getABI() const override { 6812 if (HasVector) 6813 return "vector"; 6814 return ""; 6815 } 6816 6817 bool useFloat128ManglingForLongDouble() const override { 6818 return true; 6819 } 6820 }; 6821 6822 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6823 #define BUILTIN(ID, TYPE, ATTRS) \ 6824 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6825 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 6826 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 6827 #include "clang/Basic/BuiltinsSystemZ.def" 6828 }; 6829 6830 const char *const SystemZTargetInfo::GCCRegNames[] = { 6831 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6832 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6833 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6834 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6835 }; 6836 6837 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6838 return llvm::makeArrayRef(GCCRegNames); 6839 } 6840 6841 bool SystemZTargetInfo:: 6842 validateAsmConstraint(const char *&Name, 6843 TargetInfo::ConstraintInfo &Info) const { 6844 switch (*Name) { 6845 default: 6846 return false; 6847 6848 case 'a': // Address register 6849 case 'd': // Data register (equivalent to 'r') 6850 case 'f': // Floating-point register 6851 Info.setAllowsRegister(); 6852 return true; 6853 6854 case 'I': // Unsigned 8-bit constant 6855 case 'J': // Unsigned 12-bit constant 6856 case 'K': // Signed 16-bit constant 6857 case 'L': // Signed 20-bit displacement (on all targets we support) 6858 case 'M': // 0x7fffffff 6859 return true; 6860 6861 case 'Q': // Memory with base and unsigned 12-bit displacement 6862 case 'R': // Likewise, plus an index 6863 case 'S': // Memory with base and signed 20-bit displacement 6864 case 'T': // Likewise, plus an index 6865 Info.setAllowsMemory(); 6866 return true; 6867 } 6868 } 6869 6870 class MSP430TargetInfo : public TargetInfo { 6871 static const char *const GCCRegNames[]; 6872 6873 public: 6874 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6875 : TargetInfo(Triple) { 6876 BigEndian = false; 6877 TLSSupported = false; 6878 IntWidth = 16; 6879 IntAlign = 16; 6880 LongWidth = 32; 6881 LongLongWidth = 64; 6882 LongAlign = LongLongAlign = 16; 6883 PointerWidth = 16; 6884 PointerAlign = 16; 6885 SuitableAlign = 16; 6886 SizeType = UnsignedInt; 6887 IntMaxType = SignedLongLong; 6888 IntPtrType = SignedInt; 6889 PtrDiffType = SignedInt; 6890 SigAtomicType = SignedLong; 6891 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 6892 } 6893 void getTargetDefines(const LangOptions &Opts, 6894 MacroBuilder &Builder) const override { 6895 Builder.defineMacro("MSP430"); 6896 Builder.defineMacro("__MSP430__"); 6897 // FIXME: defines for different 'flavours' of MCU 6898 } 6899 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6900 // FIXME: Implement. 6901 return None; 6902 } 6903 bool hasFeature(StringRef Feature) const override { 6904 return Feature == "msp430"; 6905 } 6906 ArrayRef<const char *> getGCCRegNames() const override; 6907 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6908 // No aliases. 6909 return None; 6910 } 6911 bool validateAsmConstraint(const char *&Name, 6912 TargetInfo::ConstraintInfo &info) const override { 6913 // FIXME: implement 6914 switch (*Name) { 6915 case 'K': // the constant 1 6916 case 'L': // constant -1^20 .. 1^19 6917 case 'M': // constant 1-4: 6918 return true; 6919 } 6920 // No target constraints for now. 6921 return false; 6922 } 6923 const char *getClobbers() const override { 6924 // FIXME: Is this really right? 6925 return ""; 6926 } 6927 BuiltinVaListKind getBuiltinVaListKind() const override { 6928 // FIXME: implement 6929 return TargetInfo::CharPtrBuiltinVaList; 6930 } 6931 }; 6932 6933 const char *const MSP430TargetInfo::GCCRegNames[] = { 6934 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6935 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6936 6937 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 6938 return llvm::makeArrayRef(GCCRegNames); 6939 } 6940 6941 // LLVM and Clang cannot be used directly to output native binaries for 6942 // target, but is used to compile C code to llvm bitcode with correct 6943 // type and alignment information. 6944 // 6945 // TCE uses the llvm bitcode as input and uses it for generating customized 6946 // target processor and program binary. TCE co-design environment is 6947 // publicly available in http://tce.cs.tut.fi 6948 6949 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6950 3, // opencl_global 6951 4, // opencl_local 6952 5, // opencl_constant 6953 // FIXME: generic has to be added to the target 6954 0, // opencl_generic 6955 0, // cuda_device 6956 0, // cuda_constant 6957 0 // cuda_shared 6958 }; 6959 6960 class TCETargetInfo : public TargetInfo { 6961 public: 6962 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6963 : TargetInfo(Triple) { 6964 TLSSupported = false; 6965 IntWidth = 32; 6966 LongWidth = LongLongWidth = 32; 6967 PointerWidth = 32; 6968 IntAlign = 32; 6969 LongAlign = LongLongAlign = 32; 6970 PointerAlign = 32; 6971 SuitableAlign = 32; 6972 SizeType = UnsignedInt; 6973 IntMaxType = SignedLong; 6974 IntPtrType = SignedInt; 6975 PtrDiffType = SignedInt; 6976 FloatWidth = 32; 6977 FloatAlign = 32; 6978 DoubleWidth = 32; 6979 DoubleAlign = 32; 6980 LongDoubleWidth = 32; 6981 LongDoubleAlign = 32; 6982 FloatFormat = &llvm::APFloat::IEEEsingle; 6983 DoubleFormat = &llvm::APFloat::IEEEsingle; 6984 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6985 resetDataLayout("E-p:32:32-i8:8:32-i16:16:32-i64:32" 6986 "-f64:32-v64:32-v128:32-a:0:32-n32"); 6987 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6988 UseAddrSpaceMapMangling = true; 6989 } 6990 6991 void getTargetDefines(const LangOptions &Opts, 6992 MacroBuilder &Builder) const override { 6993 DefineStd(Builder, "tce", Opts); 6994 Builder.defineMacro("__TCE__"); 6995 Builder.defineMacro("__TCE_V1__"); 6996 } 6997 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 6998 6999 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7000 const char *getClobbers() const override { return ""; } 7001 BuiltinVaListKind getBuiltinVaListKind() const override { 7002 return TargetInfo::VoidPtrBuiltinVaList; 7003 } 7004 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7005 bool validateAsmConstraint(const char *&Name, 7006 TargetInfo::ConstraintInfo &info) const override { 7007 return true; 7008 } 7009 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7010 return None; 7011 } 7012 }; 7013 7014 class BPFTargetInfo : public TargetInfo { 7015 public: 7016 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7017 : TargetInfo(Triple) { 7018 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7019 SizeType = UnsignedLong; 7020 PtrDiffType = SignedLong; 7021 IntPtrType = SignedLong; 7022 IntMaxType = SignedLong; 7023 Int64Type = SignedLong; 7024 RegParmMax = 5; 7025 if (Triple.getArch() == llvm::Triple::bpfeb) { 7026 BigEndian = true; 7027 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7028 } else { 7029 BigEndian = false; 7030 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7031 } 7032 MaxAtomicPromoteWidth = 64; 7033 MaxAtomicInlineWidth = 64; 7034 TLSSupported = false; 7035 } 7036 void getTargetDefines(const LangOptions &Opts, 7037 MacroBuilder &Builder) const override { 7038 DefineStd(Builder, "bpf", Opts); 7039 Builder.defineMacro("__BPF__"); 7040 } 7041 bool hasFeature(StringRef Feature) const override { 7042 return Feature == "bpf"; 7043 } 7044 7045 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7046 const char *getClobbers() const override { 7047 return ""; 7048 } 7049 BuiltinVaListKind getBuiltinVaListKind() const override { 7050 return TargetInfo::VoidPtrBuiltinVaList; 7051 } 7052 ArrayRef<const char *> getGCCRegNames() const override { 7053 return None; 7054 } 7055 bool validateAsmConstraint(const char *&Name, 7056 TargetInfo::ConstraintInfo &info) const override { 7057 return true; 7058 } 7059 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7060 return None; 7061 } 7062 }; 7063 7064 class MipsTargetInfo : public TargetInfo { 7065 void setDataLayout() { 7066 StringRef Layout; 7067 7068 if (ABI == "o32") 7069 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7070 else if (ABI == "n32") 7071 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7072 else if (ABI == "n64") 7073 Layout = "m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7074 else 7075 llvm_unreachable("Invalid ABI"); 7076 7077 if (BigEndian) 7078 resetDataLayout(("E-" + Layout).str()); 7079 else 7080 resetDataLayout(("e-" + Layout).str()); 7081 } 7082 7083 7084 static const Builtin::Info BuiltinInfo[]; 7085 std::string CPU; 7086 bool IsMips16; 7087 bool IsMicromips; 7088 bool IsNan2008; 7089 bool IsSingleFloat; 7090 enum MipsFloatABI { 7091 HardFloat, SoftFloat 7092 } FloatABI; 7093 enum DspRevEnum { 7094 NoDSP, DSP1, DSP2 7095 } DspRev; 7096 bool HasMSA; 7097 7098 protected: 7099 bool HasFP64; 7100 std::string ABI; 7101 7102 public: 7103 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7104 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7105 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 7106 DspRev(NoDSP), HasMSA(false), HasFP64(false) { 7107 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7108 BigEndian = getTriple().getArch() == llvm::Triple::mips || 7109 getTriple().getArch() == llvm::Triple::mips64; 7110 7111 setABI((getTriple().getArch() == llvm::Triple::mips || 7112 getTriple().getArch() == llvm::Triple::mipsel) 7113 ? "o32" 7114 : "n64"); 7115 7116 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7117 } 7118 7119 bool isNaN2008Default() const { 7120 return CPU == "mips32r6" || CPU == "mips64r6"; 7121 } 7122 7123 bool isFP64Default() const { 7124 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7125 } 7126 7127 bool isNan2008() const override { 7128 return IsNan2008; 7129 } 7130 7131 bool processorSupportsGPR64() const { 7132 return llvm::StringSwitch<bool>(CPU) 7133 .Case("mips3", true) 7134 .Case("mips4", true) 7135 .Case("mips5", true) 7136 .Case("mips64", true) 7137 .Case("mips64r2", true) 7138 .Case("mips64r3", true) 7139 .Case("mips64r5", true) 7140 .Case("mips64r6", true) 7141 .Case("octeon", true) 7142 .Default(false); 7143 return false; 7144 } 7145 7146 StringRef getABI() const override { return ABI; } 7147 bool setABI(const std::string &Name) override { 7148 if (Name == "o32") { 7149 setO32ABITypes(); 7150 ABI = Name; 7151 return true; 7152 } 7153 7154 if (Name == "n32") { 7155 setN32ABITypes(); 7156 ABI = Name; 7157 return true; 7158 } 7159 if (Name == "n64") { 7160 setN64ABITypes(); 7161 ABI = Name; 7162 return true; 7163 } 7164 return false; 7165 } 7166 7167 void setO32ABITypes() { 7168 Int64Type = SignedLongLong; 7169 IntMaxType = Int64Type; 7170 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7171 LongDoubleWidth = LongDoubleAlign = 64; 7172 LongWidth = LongAlign = 32; 7173 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7174 PointerWidth = PointerAlign = 32; 7175 PtrDiffType = SignedInt; 7176 SizeType = UnsignedInt; 7177 SuitableAlign = 64; 7178 } 7179 7180 void setN32N64ABITypes() { 7181 LongDoubleWidth = LongDoubleAlign = 128; 7182 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7183 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7184 LongDoubleWidth = LongDoubleAlign = 64; 7185 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7186 } 7187 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7188 SuitableAlign = 128; 7189 } 7190 7191 void setN64ABITypes() { 7192 setN32N64ABITypes(); 7193 Int64Type = SignedLong; 7194 IntMaxType = Int64Type; 7195 LongWidth = LongAlign = 64; 7196 PointerWidth = PointerAlign = 64; 7197 PtrDiffType = SignedLong; 7198 SizeType = UnsignedLong; 7199 } 7200 7201 void setN32ABITypes() { 7202 setN32N64ABITypes(); 7203 Int64Type = SignedLongLong; 7204 IntMaxType = Int64Type; 7205 LongWidth = LongAlign = 32; 7206 PointerWidth = PointerAlign = 32; 7207 PtrDiffType = SignedInt; 7208 SizeType = UnsignedInt; 7209 } 7210 7211 bool setCPU(const std::string &Name) override { 7212 CPU = Name; 7213 return llvm::StringSwitch<bool>(Name) 7214 .Case("mips1", true) 7215 .Case("mips2", true) 7216 .Case("mips3", true) 7217 .Case("mips4", true) 7218 .Case("mips5", true) 7219 .Case("mips32", true) 7220 .Case("mips32r2", true) 7221 .Case("mips32r3", true) 7222 .Case("mips32r5", true) 7223 .Case("mips32r6", true) 7224 .Case("mips64", true) 7225 .Case("mips64r2", true) 7226 .Case("mips64r3", true) 7227 .Case("mips64r5", true) 7228 .Case("mips64r6", true) 7229 .Case("octeon", true) 7230 .Case("p5600", true) 7231 .Default(false); 7232 } 7233 const std::string& getCPU() const { return CPU; } 7234 bool 7235 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7236 StringRef CPU, 7237 const std::vector<std::string> &FeaturesVec) const override { 7238 if (CPU.empty()) 7239 CPU = getCPU(); 7240 if (CPU == "octeon") 7241 Features["mips64r2"] = Features["cnmips"] = true; 7242 else 7243 Features[CPU] = true; 7244 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7245 } 7246 7247 void getTargetDefines(const LangOptions &Opts, 7248 MacroBuilder &Builder) const override { 7249 if (BigEndian) { 7250 DefineStd(Builder, "MIPSEB", Opts); 7251 Builder.defineMacro("_MIPSEB"); 7252 } else { 7253 DefineStd(Builder, "MIPSEL", Opts); 7254 Builder.defineMacro("_MIPSEL"); 7255 } 7256 7257 Builder.defineMacro("__mips__"); 7258 Builder.defineMacro("_mips"); 7259 if (Opts.GNUMode) 7260 Builder.defineMacro("mips"); 7261 7262 if (ABI == "o32") { 7263 Builder.defineMacro("__mips", "32"); 7264 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7265 } else { 7266 Builder.defineMacro("__mips", "64"); 7267 Builder.defineMacro("__mips64"); 7268 Builder.defineMacro("__mips64__"); 7269 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7270 } 7271 7272 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7273 .Cases("mips32", "mips64", "1") 7274 .Cases("mips32r2", "mips64r2", "2") 7275 .Cases("mips32r3", "mips64r3", "3") 7276 .Cases("mips32r5", "mips64r5", "5") 7277 .Cases("mips32r6", "mips64r6", "6") 7278 .Default(""); 7279 if (!ISARev.empty()) 7280 Builder.defineMacro("__mips_isa_rev", ISARev); 7281 7282 if (ABI == "o32") { 7283 Builder.defineMacro("__mips_o32"); 7284 Builder.defineMacro("_ABIO32", "1"); 7285 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7286 } else if (ABI == "n32") { 7287 Builder.defineMacro("__mips_n32"); 7288 Builder.defineMacro("_ABIN32", "2"); 7289 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7290 } else if (ABI == "n64") { 7291 Builder.defineMacro("__mips_n64"); 7292 Builder.defineMacro("_ABI64", "3"); 7293 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7294 } else 7295 llvm_unreachable("Invalid ABI."); 7296 7297 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7298 7299 switch (FloatABI) { 7300 case HardFloat: 7301 Builder.defineMacro("__mips_hard_float", Twine(1)); 7302 break; 7303 case SoftFloat: 7304 Builder.defineMacro("__mips_soft_float", Twine(1)); 7305 break; 7306 } 7307 7308 if (IsSingleFloat) 7309 Builder.defineMacro("__mips_single_float", Twine(1)); 7310 7311 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7312 Builder.defineMacro("_MIPS_FPSET", 7313 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7314 7315 if (IsMips16) 7316 Builder.defineMacro("__mips16", Twine(1)); 7317 7318 if (IsMicromips) 7319 Builder.defineMacro("__mips_micromips", Twine(1)); 7320 7321 if (IsNan2008) 7322 Builder.defineMacro("__mips_nan2008", Twine(1)); 7323 7324 switch (DspRev) { 7325 default: 7326 break; 7327 case DSP1: 7328 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7329 Builder.defineMacro("__mips_dsp", Twine(1)); 7330 break; 7331 case DSP2: 7332 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7333 Builder.defineMacro("__mips_dspr2", Twine(1)); 7334 Builder.defineMacro("__mips_dsp", Twine(1)); 7335 break; 7336 } 7337 7338 if (HasMSA) 7339 Builder.defineMacro("__mips_msa", Twine(1)); 7340 7341 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7342 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7343 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7344 7345 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7346 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7347 7348 // These shouldn't be defined for MIPS-I but there's no need to check 7349 // for that since MIPS-I isn't supported. 7350 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7351 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7352 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7353 7354 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7355 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7356 // the instructions exist but using them violates the ABI since they 7357 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7358 if (ABI == "n32" || ABI == "n64") 7359 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7360 } 7361 7362 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7363 return llvm::makeArrayRef(BuiltinInfo, 7364 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7365 } 7366 bool hasFeature(StringRef Feature) const override { 7367 return llvm::StringSwitch<bool>(Feature) 7368 .Case("mips", true) 7369 .Case("fp64", HasFP64) 7370 .Default(false); 7371 } 7372 BuiltinVaListKind getBuiltinVaListKind() const override { 7373 return TargetInfo::VoidPtrBuiltinVaList; 7374 } 7375 ArrayRef<const char *> getGCCRegNames() const override { 7376 static const char *const GCCRegNames[] = { 7377 // CPU register names 7378 // Must match second column of GCCRegAliases 7379 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7380 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7381 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7382 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7383 // Floating point register names 7384 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7385 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7386 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7387 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7388 // Hi/lo and condition register names 7389 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7390 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7391 "$ac3hi","$ac3lo", 7392 // MSA register names 7393 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7394 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7395 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7396 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7397 // MSA control register names 7398 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7399 "$msarequest", "$msamap", "$msaunmap" 7400 }; 7401 return llvm::makeArrayRef(GCCRegNames); 7402 } 7403 bool validateAsmConstraint(const char *&Name, 7404 TargetInfo::ConstraintInfo &Info) const override { 7405 switch (*Name) { 7406 default: 7407 return false; 7408 case 'r': // CPU registers. 7409 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7410 case 'y': // Equivalent to "r", backward compatibility only. 7411 case 'f': // floating-point registers. 7412 case 'c': // $25 for indirect jumps 7413 case 'l': // lo register 7414 case 'x': // hilo register pair 7415 Info.setAllowsRegister(); 7416 return true; 7417 case 'I': // Signed 16-bit constant 7418 case 'J': // Integer 0 7419 case 'K': // Unsigned 16-bit constant 7420 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7421 case 'M': // Constants not loadable via lui, addiu, or ori 7422 case 'N': // Constant -1 to -65535 7423 case 'O': // A signed 15-bit constant 7424 case 'P': // A constant between 1 go 65535 7425 return true; 7426 case 'R': // An address that can be used in a non-macro load or store 7427 Info.setAllowsMemory(); 7428 return true; 7429 case 'Z': 7430 if (Name[1] == 'C') { // An address usable by ll, and sc. 7431 Info.setAllowsMemory(); 7432 Name++; // Skip over 'Z'. 7433 return true; 7434 } 7435 return false; 7436 } 7437 } 7438 7439 std::string convertConstraint(const char *&Constraint) const override { 7440 std::string R; 7441 switch (*Constraint) { 7442 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7443 if (Constraint[1] == 'C') { 7444 R = std::string("^") + std::string(Constraint, 2); 7445 Constraint++; 7446 return R; 7447 } 7448 break; 7449 } 7450 return TargetInfo::convertConstraint(Constraint); 7451 } 7452 7453 const char *getClobbers() const override { 7454 // In GCC, $1 is not widely used in generated code (it's used only in a few 7455 // specific situations), so there is no real need for users to add it to 7456 // the clobbers list if they want to use it in their inline assembly code. 7457 // 7458 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7459 // code generation, so using it in inline assembly without adding it to the 7460 // clobbers list can cause conflicts between the inline assembly code and 7461 // the surrounding generated code. 7462 // 7463 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7464 // operands, which will conflict with the ".set at" assembler option (which 7465 // we use only for inline assembly, in order to maintain compatibility with 7466 // GCC) and will also conflict with the user's usage of $1. 7467 // 7468 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7469 // register for generated code is to automatically clobber $1 for all inline 7470 // assembly code. 7471 // 7472 // FIXME: We should automatically clobber $1 only for inline assembly code 7473 // which actually uses it. This would allow LLVM to use $1 for inline 7474 // assembly operands if the user's assembly code doesn't use it. 7475 return "~{$1}"; 7476 } 7477 7478 bool handleTargetFeatures(std::vector<std::string> &Features, 7479 DiagnosticsEngine &Diags) override { 7480 IsMips16 = false; 7481 IsMicromips = false; 7482 IsNan2008 = isNaN2008Default(); 7483 IsSingleFloat = false; 7484 FloatABI = HardFloat; 7485 DspRev = NoDSP; 7486 HasFP64 = isFP64Default(); 7487 7488 for (const auto &Feature : Features) { 7489 if (Feature == "+single-float") 7490 IsSingleFloat = true; 7491 else if (Feature == "+soft-float") 7492 FloatABI = SoftFloat; 7493 else if (Feature == "+mips16") 7494 IsMips16 = true; 7495 else if (Feature == "+micromips") 7496 IsMicromips = true; 7497 else if (Feature == "+dsp") 7498 DspRev = std::max(DspRev, DSP1); 7499 else if (Feature == "+dspr2") 7500 DspRev = std::max(DspRev, DSP2); 7501 else if (Feature == "+msa") 7502 HasMSA = true; 7503 else if (Feature == "+fp64") 7504 HasFP64 = true; 7505 else if (Feature == "-fp64") 7506 HasFP64 = false; 7507 else if (Feature == "+nan2008") 7508 IsNan2008 = true; 7509 else if (Feature == "-nan2008") 7510 IsNan2008 = false; 7511 } 7512 7513 setDataLayout(); 7514 7515 return true; 7516 } 7517 7518 int getEHDataRegisterNumber(unsigned RegNo) const override { 7519 if (RegNo == 0) return 4; 7520 if (RegNo == 1) return 5; 7521 return -1; 7522 } 7523 7524 bool isCLZForZeroUndef() const override { return false; } 7525 7526 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7527 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 7528 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7529 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7530 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 7531 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 7532 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 7533 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7534 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7535 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7536 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7537 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7538 {{"ra"}, "$31"}}; 7539 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 7540 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7541 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7542 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 7543 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 7544 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 7545 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7546 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7547 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7548 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7549 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7550 {{"ra"}, "$31"}}; 7551 if (ABI == "o32") 7552 return llvm::makeArrayRef(O32RegAliases); 7553 return llvm::makeArrayRef(NewABIRegAliases); 7554 } 7555 7556 bool hasInt128Type() const override { 7557 return ABI == "n32" || ABI == "n64"; 7558 } 7559 7560 bool validateTarget(DiagnosticsEngine &Diags) const override { 7561 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 7562 // this yet. It's better to fail here than on the backend assertion. 7563 if (processorSupportsGPR64() && ABI == "o32") { 7564 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7565 return false; 7566 } 7567 7568 // 64-bit ABI's require 64-bit CPU's. 7569 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 7570 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7571 return false; 7572 } 7573 7574 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 7575 // can't handle this yet. It's better to fail here than on the 7576 // backend assertion. 7577 if ((getTriple().getArch() == llvm::Triple::mips64 || 7578 getTriple().getArch() == llvm::Triple::mips64el) && 7579 ABI == "o32") { 7580 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7581 << ABI << getTriple().str(); 7582 return false; 7583 } 7584 7585 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 7586 // can't handle this yet. It's better to fail here than on the 7587 // backend assertion. 7588 if ((getTriple().getArch() == llvm::Triple::mips || 7589 getTriple().getArch() == llvm::Triple::mipsel) && 7590 (ABI == "n32" || ABI == "n64")) { 7591 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7592 << ABI << getTriple().str(); 7593 return false; 7594 } 7595 7596 return true; 7597 } 7598 }; 7599 7600 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 7601 #define BUILTIN(ID, TYPE, ATTRS) \ 7602 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7603 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7604 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7605 #include "clang/Basic/BuiltinsMips.def" 7606 }; 7607 7608 class PNaClTargetInfo : public TargetInfo { 7609 public: 7610 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7611 : TargetInfo(Triple) { 7612 BigEndian = false; 7613 this->LongAlign = 32; 7614 this->LongWidth = 32; 7615 this->PointerAlign = 32; 7616 this->PointerWidth = 32; 7617 this->IntMaxType = TargetInfo::SignedLongLong; 7618 this->Int64Type = TargetInfo::SignedLongLong; 7619 this->DoubleAlign = 64; 7620 this->LongDoubleWidth = 64; 7621 this->LongDoubleAlign = 64; 7622 this->SizeType = TargetInfo::UnsignedInt; 7623 this->PtrDiffType = TargetInfo::SignedInt; 7624 this->IntPtrType = TargetInfo::SignedInt; 7625 this->RegParmMax = 0; // Disallow regparm 7626 } 7627 7628 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7629 Builder.defineMacro("__le32__"); 7630 Builder.defineMacro("__pnacl__"); 7631 } 7632 void getTargetDefines(const LangOptions &Opts, 7633 MacroBuilder &Builder) const override { 7634 getArchDefines(Opts, Builder); 7635 } 7636 bool hasFeature(StringRef Feature) const override { 7637 return Feature == "pnacl"; 7638 } 7639 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7640 BuiltinVaListKind getBuiltinVaListKind() const override { 7641 return TargetInfo::PNaClABIBuiltinVaList; 7642 } 7643 ArrayRef<const char *> getGCCRegNames() const override; 7644 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7645 bool validateAsmConstraint(const char *&Name, 7646 TargetInfo::ConstraintInfo &Info) const override { 7647 return false; 7648 } 7649 7650 const char *getClobbers() const override { 7651 return ""; 7652 } 7653 }; 7654 7655 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7656 return None; 7657 } 7658 7659 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7660 return None; 7661 } 7662 7663 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7664 class NaClMips32TargetInfo : public MipsTargetInfo { 7665 public: 7666 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7667 : MipsTargetInfo(Triple, Opts) {} 7668 7669 BuiltinVaListKind getBuiltinVaListKind() const override { 7670 return TargetInfo::PNaClABIBuiltinVaList; 7671 } 7672 }; 7673 7674 class Le64TargetInfo : public TargetInfo { 7675 static const Builtin::Info BuiltinInfo[]; 7676 7677 public: 7678 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7679 : TargetInfo(Triple) { 7680 BigEndian = false; 7681 NoAsmVariants = true; 7682 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7683 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7684 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 7685 } 7686 7687 void getTargetDefines(const LangOptions &Opts, 7688 MacroBuilder &Builder) const override { 7689 DefineStd(Builder, "unix", Opts); 7690 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7691 Builder.defineMacro("__ELF__"); 7692 } 7693 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7694 return llvm::makeArrayRef(BuiltinInfo, 7695 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7696 } 7697 BuiltinVaListKind getBuiltinVaListKind() const override { 7698 return TargetInfo::PNaClABIBuiltinVaList; 7699 } 7700 const char *getClobbers() const override { return ""; } 7701 ArrayRef<const char *> getGCCRegNames() const override { 7702 return None; 7703 } 7704 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7705 return None; 7706 } 7707 bool validateAsmConstraint(const char *&Name, 7708 TargetInfo::ConstraintInfo &Info) const override { 7709 return false; 7710 } 7711 7712 bool hasProtectedVisibility() const override { return false; } 7713 }; 7714 7715 class WebAssemblyTargetInfo : public TargetInfo { 7716 static const Builtin::Info BuiltinInfo[]; 7717 7718 enum SIMDEnum { 7719 NoSIMD, 7720 SIMD128, 7721 } SIMDLevel; 7722 7723 public: 7724 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 7725 : TargetInfo(T), SIMDLevel(NoSIMD) { 7726 BigEndian = false; 7727 NoAsmVariants = true; 7728 SuitableAlign = 128; 7729 LargeArrayMinWidth = 128; 7730 LargeArrayAlign = 128; 7731 SimdDefaultAlign = 128; 7732 SigAtomicType = SignedLong; 7733 LongDoubleWidth = LongDoubleAlign = 128; 7734 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7735 } 7736 7737 protected: 7738 void getTargetDefines(const LangOptions &Opts, 7739 MacroBuilder &Builder) const override { 7740 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7741 if (SIMDLevel >= SIMD128) 7742 Builder.defineMacro("__wasm_simd128__"); 7743 } 7744 7745 private: 7746 bool 7747 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7748 StringRef CPU, 7749 const std::vector<std::string> &FeaturesVec) const override { 7750 if (CPU == "bleeding-edge") 7751 Features["simd128"] = true; 7752 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7753 } 7754 bool hasFeature(StringRef Feature) const final { 7755 return llvm::StringSwitch<bool>(Feature) 7756 .Case("simd128", SIMDLevel >= SIMD128) 7757 .Default(false); 7758 } 7759 bool handleTargetFeatures(std::vector<std::string> &Features, 7760 DiagnosticsEngine &Diags) final { 7761 for (const auto &Feature : Features) { 7762 if (Feature == "+simd128") { 7763 SIMDLevel = std::max(SIMDLevel, SIMD128); 7764 continue; 7765 } 7766 if (Feature == "-simd128") { 7767 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7768 continue; 7769 } 7770 7771 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7772 << "-target-feature"; 7773 return false; 7774 } 7775 return true; 7776 } 7777 bool setCPU(const std::string &Name) final { 7778 return llvm::StringSwitch<bool>(Name) 7779 .Case("mvp", true) 7780 .Case("bleeding-edge", true) 7781 .Case("generic", true) 7782 .Default(false); 7783 } 7784 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7785 return llvm::makeArrayRef(BuiltinInfo, 7786 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7787 } 7788 BuiltinVaListKind getBuiltinVaListKind() const final { 7789 return VoidPtrBuiltinVaList; 7790 } 7791 ArrayRef<const char *> getGCCRegNames() const final { 7792 return None; 7793 } 7794 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7795 return None; 7796 } 7797 bool 7798 validateAsmConstraint(const char *&Name, 7799 TargetInfo::ConstraintInfo &Info) const final { 7800 return false; 7801 } 7802 const char *getClobbers() const final { return ""; } 7803 bool isCLZForZeroUndef() const final { return false; } 7804 bool hasInt128Type() const final { return true; } 7805 IntType getIntTypeByWidth(unsigned BitWidth, 7806 bool IsSigned) const final { 7807 // WebAssembly prefers long long for explicitly 64-bit integers. 7808 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7809 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7810 } 7811 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7812 bool IsSigned) const final { 7813 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7814 return BitWidth == 64 7815 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7816 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7817 } 7818 }; 7819 7820 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7821 #define BUILTIN(ID, TYPE, ATTRS) \ 7822 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7823 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7824 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7825 #include "clang/Basic/BuiltinsWebAssembly.def" 7826 }; 7827 7828 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7829 public: 7830 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 7831 const TargetOptions &Opts) 7832 : WebAssemblyTargetInfo(T, Opts) { 7833 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7834 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 7835 } 7836 7837 protected: 7838 void getTargetDefines(const LangOptions &Opts, 7839 MacroBuilder &Builder) const override { 7840 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7841 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7842 } 7843 }; 7844 7845 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7846 public: 7847 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 7848 const TargetOptions &Opts) 7849 : WebAssemblyTargetInfo(T, Opts) { 7850 LongAlign = LongWidth = 64; 7851 PointerAlign = PointerWidth = 64; 7852 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7853 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7854 } 7855 7856 protected: 7857 void getTargetDefines(const LangOptions &Opts, 7858 MacroBuilder &Builder) const override { 7859 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7860 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7861 } 7862 }; 7863 7864 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7865 #define BUILTIN(ID, TYPE, ATTRS) \ 7866 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7867 #include "clang/Basic/BuiltinsLe64.def" 7868 }; 7869 7870 static const unsigned SPIRAddrSpaceMap[] = { 7871 1, // opencl_global 7872 3, // opencl_local 7873 2, // opencl_constant 7874 4, // opencl_generic 7875 0, // cuda_device 7876 0, // cuda_constant 7877 0 // cuda_shared 7878 }; 7879 class SPIRTargetInfo : public TargetInfo { 7880 public: 7881 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7882 : TargetInfo(Triple) { 7883 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7884 "SPIR target must use unknown OS"); 7885 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7886 "SPIR target must use unknown environment type"); 7887 BigEndian = false; 7888 TLSSupported = false; 7889 LongWidth = LongAlign = 64; 7890 AddrSpaceMap = &SPIRAddrSpaceMap; 7891 UseAddrSpaceMapMangling = true; 7892 // Define available target features 7893 // These must be defined in sorted order! 7894 NoAsmVariants = true; 7895 } 7896 void getTargetDefines(const LangOptions &Opts, 7897 MacroBuilder &Builder) const override { 7898 DefineStd(Builder, "SPIR", Opts); 7899 } 7900 bool hasFeature(StringRef Feature) const override { 7901 return Feature == "spir"; 7902 } 7903 7904 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7905 const char *getClobbers() const override { return ""; } 7906 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7907 bool validateAsmConstraint(const char *&Name, 7908 TargetInfo::ConstraintInfo &info) const override { 7909 return true; 7910 } 7911 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7912 return None; 7913 } 7914 BuiltinVaListKind getBuiltinVaListKind() const override { 7915 return TargetInfo::VoidPtrBuiltinVaList; 7916 } 7917 7918 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7919 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK 7920 : CCCR_Warning; 7921 } 7922 7923 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7924 return CC_SpirFunction; 7925 } 7926 7927 void setSupportedOpenCLOpts() override { 7928 // Assume all OpenCL extensions and optional core features are supported 7929 // for SPIR since it is a generic target. 7930 getSupportedOpenCLOpts().setAll(); 7931 } 7932 }; 7933 7934 class SPIR32TargetInfo : public SPIRTargetInfo { 7935 public: 7936 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7937 : SPIRTargetInfo(Triple, Opts) { 7938 PointerWidth = PointerAlign = 32; 7939 SizeType = TargetInfo::UnsignedInt; 7940 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7941 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7942 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7943 } 7944 void getTargetDefines(const LangOptions &Opts, 7945 MacroBuilder &Builder) const override { 7946 DefineStd(Builder, "SPIR32", Opts); 7947 } 7948 }; 7949 7950 class SPIR64TargetInfo : public SPIRTargetInfo { 7951 public: 7952 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7953 : SPIRTargetInfo(Triple, Opts) { 7954 PointerWidth = PointerAlign = 64; 7955 SizeType = TargetInfo::UnsignedLong; 7956 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7957 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7958 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7959 } 7960 void getTargetDefines(const LangOptions &Opts, 7961 MacroBuilder &Builder) const override { 7962 DefineStd(Builder, "SPIR64", Opts); 7963 } 7964 }; 7965 7966 class XCoreTargetInfo : public TargetInfo { 7967 static const Builtin::Info BuiltinInfo[]; 7968 public: 7969 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7970 : TargetInfo(Triple) { 7971 BigEndian = false; 7972 NoAsmVariants = true; 7973 LongLongAlign = 32; 7974 SuitableAlign = 32; 7975 DoubleAlign = LongDoubleAlign = 32; 7976 SizeType = UnsignedInt; 7977 PtrDiffType = SignedInt; 7978 IntPtrType = SignedInt; 7979 WCharType = UnsignedChar; 7980 WIntType = UnsignedInt; 7981 UseZeroLengthBitfieldAlignment = true; 7982 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7983 "-f64:32-a:0:32-n32"); 7984 } 7985 void getTargetDefines(const LangOptions &Opts, 7986 MacroBuilder &Builder) const override { 7987 Builder.defineMacro("__XS1B__"); 7988 } 7989 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7990 return llvm::makeArrayRef(BuiltinInfo, 7991 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 7992 } 7993 BuiltinVaListKind getBuiltinVaListKind() const override { 7994 return TargetInfo::VoidPtrBuiltinVaList; 7995 } 7996 const char *getClobbers() const override { 7997 return ""; 7998 } 7999 ArrayRef<const char *> getGCCRegNames() const override { 8000 static const char * const GCCRegNames[] = { 8001 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8002 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8003 }; 8004 return llvm::makeArrayRef(GCCRegNames); 8005 } 8006 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8007 return None; 8008 } 8009 bool validateAsmConstraint(const char *&Name, 8010 TargetInfo::ConstraintInfo &Info) const override { 8011 return false; 8012 } 8013 int getEHDataRegisterNumber(unsigned RegNo) const override { 8014 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8015 return (RegNo < 2)? RegNo : -1; 8016 } 8017 bool allowsLargerPreferedTypeAlignment() const override { 8018 return false; 8019 } 8020 }; 8021 8022 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8023 #define BUILTIN(ID, TYPE, ATTRS) \ 8024 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8025 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8026 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8027 #include "clang/Basic/BuiltinsXCore.def" 8028 }; 8029 8030 // x86_32 Android target 8031 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8032 public: 8033 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8034 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8035 SuitableAlign = 32; 8036 LongDoubleWidth = 64; 8037 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 8038 } 8039 }; 8040 8041 // x86_64 Android target 8042 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8043 public: 8044 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8045 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8046 LongDoubleFormat = &llvm::APFloat::IEEEquad; 8047 } 8048 8049 bool useFloat128ManglingForLongDouble() const override { 8050 return true; 8051 } 8052 }; 8053 } // end anonymous namespace 8054 8055 //===----------------------------------------------------------------------===// 8056 // Driver code 8057 //===----------------------------------------------------------------------===// 8058 8059 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 8060 const TargetOptions &Opts) { 8061 llvm::Triple::OSType os = Triple.getOS(); 8062 8063 switch (Triple.getArch()) { 8064 default: 8065 return nullptr; 8066 8067 case llvm::Triple::xcore: 8068 return new XCoreTargetInfo(Triple, Opts); 8069 8070 case llvm::Triple::hexagon: 8071 return new HexagonTargetInfo(Triple, Opts); 8072 8073 case llvm::Triple::lanai: 8074 return new LanaiTargetInfo(Triple, Opts); 8075 8076 case llvm::Triple::aarch64: 8077 if (Triple.isOSDarwin()) 8078 return new DarwinAArch64TargetInfo(Triple, Opts); 8079 8080 switch (os) { 8081 case llvm::Triple::CloudABI: 8082 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 8083 case llvm::Triple::FreeBSD: 8084 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8085 case llvm::Triple::Linux: 8086 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8087 case llvm::Triple::NetBSD: 8088 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8089 default: 8090 return new AArch64leTargetInfo(Triple, Opts); 8091 } 8092 8093 case llvm::Triple::aarch64_be: 8094 switch (os) { 8095 case llvm::Triple::FreeBSD: 8096 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8097 case llvm::Triple::Linux: 8098 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8099 case llvm::Triple::NetBSD: 8100 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8101 default: 8102 return new AArch64beTargetInfo(Triple, Opts); 8103 } 8104 8105 case llvm::Triple::arm: 8106 case llvm::Triple::thumb: 8107 if (Triple.isOSBinFormatMachO()) 8108 return new DarwinARMTargetInfo(Triple, Opts); 8109 8110 switch (os) { 8111 case llvm::Triple::Linux: 8112 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 8113 case llvm::Triple::FreeBSD: 8114 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8115 case llvm::Triple::NetBSD: 8116 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8117 case llvm::Triple::OpenBSD: 8118 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8119 case llvm::Triple::Bitrig: 8120 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 8121 case llvm::Triple::RTEMS: 8122 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 8123 case llvm::Triple::NaCl: 8124 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 8125 case llvm::Triple::Win32: 8126 switch (Triple.getEnvironment()) { 8127 case llvm::Triple::Cygnus: 8128 return new CygwinARMTargetInfo(Triple, Opts); 8129 case llvm::Triple::GNU: 8130 return new MinGWARMTargetInfo(Triple, Opts); 8131 case llvm::Triple::Itanium: 8132 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 8133 case llvm::Triple::MSVC: 8134 default: // Assume MSVC for unknown environments 8135 return new MicrosoftARMleTargetInfo(Triple, Opts); 8136 } 8137 default: 8138 return new ARMleTargetInfo(Triple, Opts); 8139 } 8140 8141 case llvm::Triple::armeb: 8142 case llvm::Triple::thumbeb: 8143 if (Triple.isOSDarwin()) 8144 return new DarwinARMTargetInfo(Triple, Opts); 8145 8146 switch (os) { 8147 case llvm::Triple::Linux: 8148 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8149 case llvm::Triple::FreeBSD: 8150 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8151 case llvm::Triple::NetBSD: 8152 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8153 case llvm::Triple::OpenBSD: 8154 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8155 case llvm::Triple::Bitrig: 8156 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8157 case llvm::Triple::RTEMS: 8158 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8159 case llvm::Triple::NaCl: 8160 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8161 default: 8162 return new ARMbeTargetInfo(Triple, Opts); 8163 } 8164 8165 case llvm::Triple::bpfeb: 8166 case llvm::Triple::bpfel: 8167 return new BPFTargetInfo(Triple, Opts); 8168 8169 case llvm::Triple::msp430: 8170 return new MSP430TargetInfo(Triple, Opts); 8171 8172 case llvm::Triple::mips: 8173 switch (os) { 8174 case llvm::Triple::Linux: 8175 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8176 case llvm::Triple::RTEMS: 8177 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8178 case llvm::Triple::FreeBSD: 8179 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8180 case llvm::Triple::NetBSD: 8181 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8182 default: 8183 return new MipsTargetInfo(Triple, Opts); 8184 } 8185 8186 case llvm::Triple::mipsel: 8187 switch (os) { 8188 case llvm::Triple::Linux: 8189 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8190 case llvm::Triple::RTEMS: 8191 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8192 case llvm::Triple::FreeBSD: 8193 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8194 case llvm::Triple::NetBSD: 8195 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8196 case llvm::Triple::NaCl: 8197 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 8198 default: 8199 return new MipsTargetInfo(Triple, Opts); 8200 } 8201 8202 case llvm::Triple::mips64: 8203 switch (os) { 8204 case llvm::Triple::Linux: 8205 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8206 case llvm::Triple::RTEMS: 8207 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8208 case llvm::Triple::FreeBSD: 8209 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8210 case llvm::Triple::NetBSD: 8211 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8212 case llvm::Triple::OpenBSD: 8213 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8214 default: 8215 return new MipsTargetInfo(Triple, Opts); 8216 } 8217 8218 case llvm::Triple::mips64el: 8219 switch (os) { 8220 case llvm::Triple::Linux: 8221 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8222 case llvm::Triple::RTEMS: 8223 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8224 case llvm::Triple::FreeBSD: 8225 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8226 case llvm::Triple::NetBSD: 8227 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8228 case llvm::Triple::OpenBSD: 8229 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8230 default: 8231 return new MipsTargetInfo(Triple, Opts); 8232 } 8233 8234 case llvm::Triple::le32: 8235 switch (os) { 8236 case llvm::Triple::NaCl: 8237 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 8238 default: 8239 return nullptr; 8240 } 8241 8242 case llvm::Triple::le64: 8243 return new Le64TargetInfo(Triple, Opts); 8244 8245 case llvm::Triple::ppc: 8246 if (Triple.isOSDarwin()) 8247 return new DarwinPPC32TargetInfo(Triple, Opts); 8248 switch (os) { 8249 case llvm::Triple::Linux: 8250 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 8251 case llvm::Triple::FreeBSD: 8252 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8253 case llvm::Triple::NetBSD: 8254 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8255 case llvm::Triple::OpenBSD: 8256 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8257 case llvm::Triple::RTEMS: 8258 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 8259 default: 8260 return new PPC32TargetInfo(Triple, Opts); 8261 } 8262 8263 case llvm::Triple::ppc64: 8264 if (Triple.isOSDarwin()) 8265 return new DarwinPPC64TargetInfo(Triple, Opts); 8266 switch (os) { 8267 case llvm::Triple::Linux: 8268 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8269 case llvm::Triple::Lv2: 8270 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 8271 case llvm::Triple::FreeBSD: 8272 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8273 case llvm::Triple::NetBSD: 8274 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8275 default: 8276 return new PPC64TargetInfo(Triple, Opts); 8277 } 8278 8279 case llvm::Triple::ppc64le: 8280 switch (os) { 8281 case llvm::Triple::Linux: 8282 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8283 case llvm::Triple::NetBSD: 8284 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8285 default: 8286 return new PPC64TargetInfo(Triple, Opts); 8287 } 8288 8289 case llvm::Triple::nvptx: 8290 return new NVPTX32TargetInfo(Triple, Opts); 8291 case llvm::Triple::nvptx64: 8292 return new NVPTX64TargetInfo(Triple, Opts); 8293 8294 case llvm::Triple::amdgcn: 8295 case llvm::Triple::r600: 8296 return new AMDGPUTargetInfo(Triple, Opts); 8297 8298 case llvm::Triple::sparc: 8299 switch (os) { 8300 case llvm::Triple::Linux: 8301 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8302 case llvm::Triple::Solaris: 8303 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8304 case llvm::Triple::NetBSD: 8305 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8306 case llvm::Triple::OpenBSD: 8307 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8308 case llvm::Triple::RTEMS: 8309 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8310 default: 8311 return new SparcV8TargetInfo(Triple, Opts); 8312 } 8313 8314 // The 'sparcel' architecture copies all the above cases except for Solaris. 8315 case llvm::Triple::sparcel: 8316 switch (os) { 8317 case llvm::Triple::Linux: 8318 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8319 case llvm::Triple::NetBSD: 8320 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8321 case llvm::Triple::OpenBSD: 8322 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8323 case llvm::Triple::RTEMS: 8324 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8325 default: 8326 return new SparcV8elTargetInfo(Triple, Opts); 8327 } 8328 8329 case llvm::Triple::sparcv9: 8330 switch (os) { 8331 case llvm::Triple::Linux: 8332 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8333 case llvm::Triple::Solaris: 8334 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8335 case llvm::Triple::NetBSD: 8336 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8337 case llvm::Triple::OpenBSD: 8338 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8339 case llvm::Triple::FreeBSD: 8340 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8341 default: 8342 return new SparcV9TargetInfo(Triple, Opts); 8343 } 8344 8345 case llvm::Triple::systemz: 8346 switch (os) { 8347 case llvm::Triple::Linux: 8348 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 8349 default: 8350 return new SystemZTargetInfo(Triple, Opts); 8351 } 8352 8353 case llvm::Triple::tce: 8354 return new TCETargetInfo(Triple, Opts); 8355 8356 case llvm::Triple::x86: 8357 if (Triple.isOSDarwin()) 8358 return new DarwinI386TargetInfo(Triple, Opts); 8359 8360 switch (os) { 8361 case llvm::Triple::CloudABI: 8362 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 8363 case llvm::Triple::Linux: { 8364 switch (Triple.getEnvironment()) { 8365 default: 8366 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 8367 case llvm::Triple::Android: 8368 return new AndroidX86_32TargetInfo(Triple, Opts); 8369 } 8370 } 8371 case llvm::Triple::DragonFly: 8372 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8373 case llvm::Triple::NetBSD: 8374 return new NetBSDI386TargetInfo(Triple, Opts); 8375 case llvm::Triple::OpenBSD: 8376 return new OpenBSDI386TargetInfo(Triple, Opts); 8377 case llvm::Triple::Bitrig: 8378 return new BitrigI386TargetInfo(Triple, Opts); 8379 case llvm::Triple::FreeBSD: 8380 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8381 case llvm::Triple::KFreeBSD: 8382 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8383 case llvm::Triple::Minix: 8384 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 8385 case llvm::Triple::Solaris: 8386 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 8387 case llvm::Triple::Win32: { 8388 switch (Triple.getEnvironment()) { 8389 case llvm::Triple::Cygnus: 8390 return new CygwinX86_32TargetInfo(Triple, Opts); 8391 case llvm::Triple::GNU: 8392 return new MinGWX86_32TargetInfo(Triple, Opts); 8393 case llvm::Triple::Itanium: 8394 case llvm::Triple::MSVC: 8395 default: // Assume MSVC for unknown environments 8396 return new MicrosoftX86_32TargetInfo(Triple, Opts); 8397 } 8398 } 8399 case llvm::Triple::Haiku: 8400 return new HaikuX86_32TargetInfo(Triple, Opts); 8401 case llvm::Triple::RTEMS: 8402 return new RTEMSX86_32TargetInfo(Triple, Opts); 8403 case llvm::Triple::NaCl: 8404 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 8405 case llvm::Triple::ELFIAMCU: 8406 return new MCUX86_32TargetInfo(Triple, Opts); 8407 default: 8408 return new X86_32TargetInfo(Triple, Opts); 8409 } 8410 8411 case llvm::Triple::x86_64: 8412 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 8413 return new DarwinX86_64TargetInfo(Triple, Opts); 8414 8415 switch (os) { 8416 case llvm::Triple::CloudABI: 8417 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 8418 case llvm::Triple::Linux: { 8419 switch (Triple.getEnvironment()) { 8420 default: 8421 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 8422 case llvm::Triple::Android: 8423 return new AndroidX86_64TargetInfo(Triple, Opts); 8424 } 8425 } 8426 case llvm::Triple::DragonFly: 8427 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8428 case llvm::Triple::NetBSD: 8429 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8430 case llvm::Triple::OpenBSD: 8431 return new OpenBSDX86_64TargetInfo(Triple, Opts); 8432 case llvm::Triple::Bitrig: 8433 return new BitrigX86_64TargetInfo(Triple, Opts); 8434 case llvm::Triple::FreeBSD: 8435 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8436 case llvm::Triple::KFreeBSD: 8437 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8438 case llvm::Triple::Solaris: 8439 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 8440 case llvm::Triple::Win32: { 8441 switch (Triple.getEnvironment()) { 8442 case llvm::Triple::Cygnus: 8443 return new CygwinX86_64TargetInfo(Triple, Opts); 8444 case llvm::Triple::GNU: 8445 return new MinGWX86_64TargetInfo(Triple, Opts); 8446 case llvm::Triple::MSVC: 8447 default: // Assume MSVC for unknown environments 8448 return new MicrosoftX86_64TargetInfo(Triple, Opts); 8449 } 8450 } 8451 case llvm::Triple::Haiku: 8452 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 8453 case llvm::Triple::NaCl: 8454 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 8455 case llvm::Triple::PS4: 8456 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 8457 default: 8458 return new X86_64TargetInfo(Triple, Opts); 8459 } 8460 8461 case llvm::Triple::spir: { 8462 if (Triple.getOS() != llvm::Triple::UnknownOS || 8463 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8464 return nullptr; 8465 return new SPIR32TargetInfo(Triple, Opts); 8466 } 8467 case llvm::Triple::spir64: { 8468 if (Triple.getOS() != llvm::Triple::UnknownOS || 8469 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8470 return nullptr; 8471 return new SPIR64TargetInfo(Triple, Opts); 8472 } 8473 case llvm::Triple::wasm32: 8474 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8475 return nullptr; 8476 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 8477 case llvm::Triple::wasm64: 8478 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8479 return nullptr; 8480 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 8481 } 8482 } 8483 8484 /// CreateTargetInfo - Return the target info object for the specified target 8485 /// options. 8486 TargetInfo * 8487 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8488 const std::shared_ptr<TargetOptions> &Opts) { 8489 llvm::Triple Triple(Opts->Triple); 8490 8491 // Construct the target 8492 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 8493 if (!Target) { 8494 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8495 return nullptr; 8496 } 8497 Target->TargetOpts = Opts; 8498 8499 // Set the target CPU if specified. 8500 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8501 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8502 return nullptr; 8503 } 8504 8505 // Set the target ABI if specified. 8506 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8507 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8508 return nullptr; 8509 } 8510 8511 // Set the fp math unit. 8512 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8513 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8514 return nullptr; 8515 } 8516 8517 // Compute the default target features, we need the target to handle this 8518 // because features may have dependencies on one another. 8519 llvm::StringMap<bool> Features; 8520 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8521 Opts->FeaturesAsWritten)) 8522 return nullptr; 8523 8524 // Add the features to the compile options. 8525 Opts->Features.clear(); 8526 for (const auto &F : Features) 8527 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8528 8529 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8530 return nullptr; 8531 8532 Target->setSupportedOpenCLOpts(); 8533 8534 if (!Target->validateTarget(Diags)) 8535 return nullptr; 8536 8537 return Target.release(); 8538 } 8539