1 //===--- Targets.cpp - Implement target feature support -------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements construction of a TargetInfo object from a
11 // target triple.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "clang/Basic/Version.h"
23 #include "llvm/ADT/APFloat.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/ADT/Triple.h"
29 #include "llvm/MC/MCSectionMachO.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/TargetParser.h"
32 #include <algorithm>
33 #include <memory>
34 
35 using namespace clang;
36 
37 //===----------------------------------------------------------------------===//
38 //  Common code shared among targets.
39 //===----------------------------------------------------------------------===//
40 
41 /// DefineStd - Define a macro name and standard variants.  For example if
42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
43 /// when in GNU mode.
44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
45                       const LangOptions &Opts) {
46   assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
47 
48   // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
49   // in the user's namespace.
50   if (Opts.GNUMode)
51     Builder.defineMacro(MacroName);
52 
53   // Define __unix.
54   Builder.defineMacro("__" + MacroName);
55 
56   // Define __unix__.
57   Builder.defineMacro("__" + MacroName + "__");
58 }
59 
60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
61                             bool Tuning = true) {
62   Builder.defineMacro("__" + CPUName);
63   Builder.defineMacro("__" + CPUName + "__");
64   if (Tuning)
65     Builder.defineMacro("__tune_" + CPUName + "__");
66 }
67 
68 //===----------------------------------------------------------------------===//
69 // Defines specific to certain operating systems.
70 //===----------------------------------------------------------------------===//
71 
72 namespace {
73 template<typename TgtInfo>
74 class OSTargetInfo : public TgtInfo {
75 protected:
76   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
77                             MacroBuilder &Builder) const=0;
78 public:
79   OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
80   void getTargetDefines(const LangOptions &Opts,
81                         MacroBuilder &Builder) const override {
82     TgtInfo::getTargetDefines(Opts, Builder);
83     getOSDefines(Opts, TgtInfo::getTriple(), Builder);
84   }
85 
86 };
87 
88 // CloudABI Target
89 template <typename Target>
90 class CloudABITargetInfo : public OSTargetInfo<Target> {
91 protected:
92   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
93                     MacroBuilder &Builder) const override {
94     Builder.defineMacro("__CloudABI__");
95     Builder.defineMacro("__ELF__");
96 
97     // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t.
98     Builder.defineMacro("__STDC_ISO_10646__", "201206L");
99     Builder.defineMacro("__STDC_UTF_16__");
100     Builder.defineMacro("__STDC_UTF_32__");
101   }
102 
103 public:
104   CloudABITargetInfo(const llvm::Triple &Triple)
105       : OSTargetInfo<Target>(Triple) {
106     this->UserLabelPrefix = "";
107   }
108 };
109 
110 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
111                              const llvm::Triple &Triple,
112                              StringRef &PlatformName,
113                              VersionTuple &PlatformMinVersion) {
114   Builder.defineMacro("__APPLE_CC__", "6000");
115   Builder.defineMacro("__APPLE__");
116   Builder.defineMacro("OBJC_NEW_PROPERTIES");
117   // AddressSanitizer doesn't play well with source fortification, which is on
118   // by default on Darwin.
119   if (Opts.Sanitize.has(SanitizerKind::Address))
120     Builder.defineMacro("_FORTIFY_SOURCE", "0");
121 
122   // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode.
123   if (!Opts.ObjC1) {
124     // __weak is always defined, for use in blocks and with objc pointers.
125     Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
126     Builder.defineMacro("__strong", "");
127     Builder.defineMacro("__unsafe_unretained", "");
128   }
129 
130   if (Opts.Static)
131     Builder.defineMacro("__STATIC__");
132   else
133     Builder.defineMacro("__DYNAMIC__");
134 
135   if (Opts.POSIXThreads)
136     Builder.defineMacro("_REENTRANT");
137 
138   // Get the platform type and version number from the triple.
139   unsigned Maj, Min, Rev;
140   if (Triple.isMacOSX()) {
141     Triple.getMacOSXVersion(Maj, Min, Rev);
142     PlatformName = "macosx";
143   } else {
144     Triple.getOSVersion(Maj, Min, Rev);
145     PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
146   }
147 
148   // If -target arch-pc-win32-macho option specified, we're
149   // generating code for Win32 ABI. No need to emit
150   // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
151   if (PlatformName == "win32") {
152     PlatformMinVersion = VersionTuple(Maj, Min, Rev);
153     return;
154   }
155 
156   // Set the appropriate OS version define.
157   if (Triple.isiOS()) {
158     assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
159     char Str[6];
160     Str[0] = '0' + Maj;
161     Str[1] = '0' + (Min / 10);
162     Str[2] = '0' + (Min % 10);
163     Str[3] = '0' + (Rev / 10);
164     Str[4] = '0' + (Rev % 10);
165     Str[5] = '\0';
166     if (Triple.isTvOS())
167       Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str);
168     else
169       Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
170                           Str);
171 
172   } else if (Triple.isWatchOS()) {
173     assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
174     char Str[6];
175     Str[0] = '0' + Maj;
176     Str[1] = '0' + (Min / 10);
177     Str[2] = '0' + (Min % 10);
178     Str[3] = '0' + (Rev / 10);
179     Str[4] = '0' + (Rev % 10);
180     Str[5] = '\0';
181     Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str);
182   } else if (Triple.isMacOSX()) {
183     // Note that the Driver allows versions which aren't representable in the
184     // define (because we only get a single digit for the minor and micro
185     // revision numbers). So, we limit them to the maximum representable
186     // version.
187     assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
188     char Str[7];
189     if (Maj < 10 || (Maj == 10 && Min < 10)) {
190       Str[0] = '0' + (Maj / 10);
191       Str[1] = '0' + (Maj % 10);
192       Str[2] = '0' + std::min(Min, 9U);
193       Str[3] = '0' + std::min(Rev, 9U);
194       Str[4] = '\0';
195     } else {
196       // Handle versions > 10.9.
197       Str[0] = '0' + (Maj / 10);
198       Str[1] = '0' + (Maj % 10);
199       Str[2] = '0' + (Min / 10);
200       Str[3] = '0' + (Min % 10);
201       Str[4] = '0' + (Rev / 10);
202       Str[5] = '0' + (Rev % 10);
203       Str[6] = '\0';
204     }
205     Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
206   }
207 
208   // Tell users about the kernel if there is one.
209   if (Triple.isOSDarwin())
210     Builder.defineMacro("__MACH__");
211 
212   PlatformMinVersion = VersionTuple(Maj, Min, Rev);
213 }
214 
215 template<typename Target>
216 class DarwinTargetInfo : public OSTargetInfo<Target> {
217 protected:
218   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
219                     MacroBuilder &Builder) const override {
220     getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
221                      this->PlatformMinVersion);
222   }
223 
224 public:
225   DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
226     this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
227     this->MCountName = "\01mcount";
228   }
229 
230   std::string isValidSectionSpecifier(StringRef SR) const override {
231     // Let MCSectionMachO validate this.
232     StringRef Segment, Section;
233     unsigned TAA, StubSize;
234     bool HasTAA;
235     return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
236                                                        TAA, HasTAA, StubSize);
237   }
238 
239   const char *getStaticInitSectionSpecifier() const override {
240     // FIXME: We should return 0 when building kexts.
241     return "__TEXT,__StaticInit,regular,pure_instructions";
242   }
243 
244   /// Darwin does not support protected visibility.  Darwin's "default"
245   /// is very similar to ELF's "protected";  Darwin requires a "weak"
246   /// attribute on declarations that can be dynamically replaced.
247   bool hasProtectedVisibility() const override {
248     return false;
249   }
250 };
251 
252 
253 // DragonFlyBSD Target
254 template<typename Target>
255 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
256 protected:
257   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
258                     MacroBuilder &Builder) const override {
259     // DragonFly defines; list based off of gcc output
260     Builder.defineMacro("__DragonFly__");
261     Builder.defineMacro("__DragonFly_cc_version", "100001");
262     Builder.defineMacro("__ELF__");
263     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
264     Builder.defineMacro("__tune_i386__");
265     DefineStd(Builder, "unix", Opts);
266   }
267 public:
268   DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
269       : OSTargetInfo<Target>(Triple) {
270     this->UserLabelPrefix = "";
271 
272     switch (Triple.getArch()) {
273     default:
274     case llvm::Triple::x86:
275     case llvm::Triple::x86_64:
276       this->MCountName = ".mcount";
277       break;
278     }
279   }
280 };
281 
282 // FreeBSD Target
283 template<typename Target>
284 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
285 protected:
286   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
287                     MacroBuilder &Builder) const override {
288     // FreeBSD defines; list based off of gcc output
289 
290     unsigned Release = Triple.getOSMajorVersion();
291     if (Release == 0U)
292       Release = 8;
293 
294     Builder.defineMacro("__FreeBSD__", Twine(Release));
295     Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
296     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
297     DefineStd(Builder, "unix", Opts);
298     Builder.defineMacro("__ELF__");
299 
300     // On FreeBSD, wchar_t contains the number of the code point as
301     // used by the character set of the locale. These character sets are
302     // not necessarily a superset of ASCII.
303     //
304     // FIXME: This is wrong; the macro refers to the numerical values
305     // of wchar_t *literals*, which are not locale-dependent. However,
306     // FreeBSD systems apparently depend on us getting this wrong, and
307     // setting this to 1 is conforming even if all the basic source
308     // character literals have the same encoding as char and wchar_t.
309     Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
310   }
311 public:
312   FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
313     this->UserLabelPrefix = "";
314 
315     switch (Triple.getArch()) {
316     default:
317     case llvm::Triple::x86:
318     case llvm::Triple::x86_64:
319       this->MCountName = ".mcount";
320       break;
321     case llvm::Triple::mips:
322     case llvm::Triple::mipsel:
323     case llvm::Triple::ppc:
324     case llvm::Triple::ppc64:
325     case llvm::Triple::ppc64le:
326       this->MCountName = "_mcount";
327       break;
328     case llvm::Triple::arm:
329       this->MCountName = "__mcount";
330       break;
331     }
332   }
333 };
334 
335 // GNU/kFreeBSD Target
336 template<typename Target>
337 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
338 protected:
339   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
340                     MacroBuilder &Builder) const override {
341     // GNU/kFreeBSD defines; list based off of gcc output
342 
343     DefineStd(Builder, "unix", Opts);
344     Builder.defineMacro("__FreeBSD_kernel__");
345     Builder.defineMacro("__GLIBC__");
346     Builder.defineMacro("__ELF__");
347     if (Opts.POSIXThreads)
348       Builder.defineMacro("_REENTRANT");
349     if (Opts.CPlusPlus)
350       Builder.defineMacro("_GNU_SOURCE");
351   }
352 public:
353   KFreeBSDTargetInfo(const llvm::Triple &Triple)
354       : OSTargetInfo<Target>(Triple) {
355     this->UserLabelPrefix = "";
356   }
357 };
358 
359 // Minix Target
360 template<typename Target>
361 class MinixTargetInfo : public OSTargetInfo<Target> {
362 protected:
363   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
364                     MacroBuilder &Builder) const override {
365     // Minix defines
366 
367     Builder.defineMacro("__minix", "3");
368     Builder.defineMacro("_EM_WSIZE", "4");
369     Builder.defineMacro("_EM_PSIZE", "4");
370     Builder.defineMacro("_EM_SSIZE", "2");
371     Builder.defineMacro("_EM_LSIZE", "4");
372     Builder.defineMacro("_EM_FSIZE", "4");
373     Builder.defineMacro("_EM_DSIZE", "8");
374     Builder.defineMacro("__ELF__");
375     DefineStd(Builder, "unix", Opts);
376   }
377 public:
378   MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
379     this->UserLabelPrefix = "";
380   }
381 };
382 
383 // Linux target
384 template<typename Target>
385 class LinuxTargetInfo : public OSTargetInfo<Target> {
386 protected:
387   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
388                     MacroBuilder &Builder) const override {
389     // Linux defines; list based off of gcc output
390     DefineStd(Builder, "unix", Opts);
391     DefineStd(Builder, "linux", Opts);
392     Builder.defineMacro("__gnu_linux__");
393     Builder.defineMacro("__ELF__");
394     if (Triple.isAndroid()) {
395       Builder.defineMacro("__ANDROID__", "1");
396       unsigned Maj, Min, Rev;
397       Triple.getEnvironmentVersion(Maj, Min, Rev);
398       this->PlatformName = "android";
399       this->PlatformMinVersion = VersionTuple(Maj, Min, Rev);
400     }
401     if (Opts.POSIXThreads)
402       Builder.defineMacro("_REENTRANT");
403     if (Opts.CPlusPlus)
404       Builder.defineMacro("_GNU_SOURCE");
405   }
406 public:
407   LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
408     this->UserLabelPrefix = "";
409     this->WIntType = TargetInfo::UnsignedInt;
410 
411     switch (Triple.getArch()) {
412     default:
413       break;
414     case llvm::Triple::ppc:
415     case llvm::Triple::ppc64:
416     case llvm::Triple::ppc64le:
417       this->MCountName = "_mcount";
418       break;
419     }
420   }
421 
422   const char *getStaticInitSectionSpecifier() const override {
423     return ".text.startup";
424   }
425 };
426 
427 // NetBSD Target
428 template<typename Target>
429 class NetBSDTargetInfo : public OSTargetInfo<Target> {
430 protected:
431   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
432                     MacroBuilder &Builder) const override {
433     // NetBSD defines; list based off of gcc output
434     Builder.defineMacro("__NetBSD__");
435     Builder.defineMacro("__unix__");
436     Builder.defineMacro("__ELF__");
437     if (Opts.POSIXThreads)
438       Builder.defineMacro("_POSIX_THREADS");
439 
440     switch (Triple.getArch()) {
441     default:
442       break;
443     case llvm::Triple::arm:
444     case llvm::Triple::armeb:
445     case llvm::Triple::thumb:
446     case llvm::Triple::thumbeb:
447       Builder.defineMacro("__ARM_DWARF_EH__");
448       break;
449     }
450   }
451 public:
452   NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
453     this->UserLabelPrefix = "";
454     this->MCountName = "_mcount";
455   }
456 };
457 
458 // OpenBSD Target
459 template<typename Target>
460 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
461 protected:
462   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
463                     MacroBuilder &Builder) const override {
464     // OpenBSD defines; list based off of gcc output
465 
466     Builder.defineMacro("__OpenBSD__");
467     DefineStd(Builder, "unix", Opts);
468     Builder.defineMacro("__ELF__");
469     if (Opts.POSIXThreads)
470       Builder.defineMacro("_REENTRANT");
471   }
472 public:
473   OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
474     this->UserLabelPrefix = "";
475     this->TLSSupported = false;
476 
477       switch (Triple.getArch()) {
478         default:
479         case llvm::Triple::x86:
480         case llvm::Triple::x86_64:
481         case llvm::Triple::arm:
482         case llvm::Triple::sparc:
483           this->MCountName = "__mcount";
484           break;
485         case llvm::Triple::mips64:
486         case llvm::Triple::mips64el:
487         case llvm::Triple::ppc:
488         case llvm::Triple::sparcv9:
489           this->MCountName = "_mcount";
490           break;
491       }
492   }
493 };
494 
495 // Bitrig Target
496 template<typename Target>
497 class BitrigTargetInfo : public OSTargetInfo<Target> {
498 protected:
499   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
500                     MacroBuilder &Builder) const override {
501     // Bitrig defines; list based off of gcc output
502 
503     Builder.defineMacro("__Bitrig__");
504     DefineStd(Builder, "unix", Opts);
505     Builder.defineMacro("__ELF__");
506     if (Opts.POSIXThreads)
507       Builder.defineMacro("_REENTRANT");
508 
509     switch (Triple.getArch()) {
510     default:
511       break;
512     case llvm::Triple::arm:
513     case llvm::Triple::armeb:
514     case llvm::Triple::thumb:
515     case llvm::Triple::thumbeb:
516       Builder.defineMacro("__ARM_DWARF_EH__");
517       break;
518     }
519   }
520 public:
521   BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
522     this->UserLabelPrefix = "";
523     this->MCountName = "__mcount";
524   }
525 };
526 
527 // PSP Target
528 template<typename Target>
529 class PSPTargetInfo : public OSTargetInfo<Target> {
530 protected:
531   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
532                     MacroBuilder &Builder) const override {
533     // PSP defines; list based on the output of the pspdev gcc toolchain.
534     Builder.defineMacro("PSP");
535     Builder.defineMacro("_PSP");
536     Builder.defineMacro("__psp__");
537     Builder.defineMacro("__ELF__");
538   }
539 public:
540   PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
541     this->UserLabelPrefix = "";
542   }
543 };
544 
545 // PS3 PPU Target
546 template<typename Target>
547 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
548 protected:
549   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
550                     MacroBuilder &Builder) const override {
551     // PS3 PPU defines.
552     Builder.defineMacro("__PPC__");
553     Builder.defineMacro("__PPU__");
554     Builder.defineMacro("__CELLOS_LV2__");
555     Builder.defineMacro("__ELF__");
556     Builder.defineMacro("__LP32__");
557     Builder.defineMacro("_ARCH_PPC64");
558     Builder.defineMacro("__powerpc64__");
559   }
560 public:
561   PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
562     this->UserLabelPrefix = "";
563     this->LongWidth = this->LongAlign = 32;
564     this->PointerWidth = this->PointerAlign = 32;
565     this->IntMaxType = TargetInfo::SignedLongLong;
566     this->Int64Type = TargetInfo::SignedLongLong;
567     this->SizeType = TargetInfo::UnsignedInt;
568     this->DataLayoutString = "E-m:e-p:32:32-i64:64-n32:64";
569   }
570 };
571 
572 template <typename Target>
573 class PS4OSTargetInfo : public OSTargetInfo<Target> {
574 protected:
575   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
576                     MacroBuilder &Builder) const override {
577     Builder.defineMacro("__FreeBSD__", "9");
578     Builder.defineMacro("__FreeBSD_cc_version", "900001");
579     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
580     DefineStd(Builder, "unix", Opts);
581     Builder.defineMacro("__ELF__");
582     Builder.defineMacro("__PS4__");
583   }
584 public:
585   PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
586     this->WCharType = this->UnsignedShort;
587 
588     // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits).
589     this->MaxTLSAlign = 256;
590     this->UserLabelPrefix = "";
591 
592     switch (Triple.getArch()) {
593     default:
594     case llvm::Triple::x86_64:
595       this->MCountName = ".mcount";
596       break;
597     }
598   }
599 };
600 
601 // Solaris target
602 template<typename Target>
603 class SolarisTargetInfo : public OSTargetInfo<Target> {
604 protected:
605   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
606                     MacroBuilder &Builder) const override {
607     DefineStd(Builder, "sun", Opts);
608     DefineStd(Builder, "unix", Opts);
609     Builder.defineMacro("__ELF__");
610     Builder.defineMacro("__svr4__");
611     Builder.defineMacro("__SVR4");
612     // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
613     // newer, but to 500 for everything else.  feature_test.h has a check to
614     // ensure that you are not using C99 with an old version of X/Open or C89
615     // with a new version.
616     if (Opts.C99)
617       Builder.defineMacro("_XOPEN_SOURCE", "600");
618     else
619       Builder.defineMacro("_XOPEN_SOURCE", "500");
620     if (Opts.CPlusPlus)
621       Builder.defineMacro("__C99FEATURES__");
622     Builder.defineMacro("_LARGEFILE_SOURCE");
623     Builder.defineMacro("_LARGEFILE64_SOURCE");
624     Builder.defineMacro("__EXTENSIONS__");
625     Builder.defineMacro("_REENTRANT");
626   }
627 public:
628   SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
629     this->UserLabelPrefix = "";
630     this->WCharType = this->SignedInt;
631     // FIXME: WIntType should be SignedLong
632   }
633 };
634 
635 // Windows target
636 template<typename Target>
637 class WindowsTargetInfo : public OSTargetInfo<Target> {
638 protected:
639   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
640                     MacroBuilder &Builder) const override {
641     Builder.defineMacro("_WIN32");
642   }
643   void getVisualStudioDefines(const LangOptions &Opts,
644                               MacroBuilder &Builder) const {
645     if (Opts.CPlusPlus) {
646       if (Opts.RTTIData)
647         Builder.defineMacro("_CPPRTTI");
648 
649       if (Opts.CXXExceptions)
650         Builder.defineMacro("_CPPUNWIND");
651     }
652 
653     if (Opts.Bool)
654       Builder.defineMacro("__BOOL_DEFINED");
655 
656     if (!Opts.CharIsSigned)
657       Builder.defineMacro("_CHAR_UNSIGNED");
658 
659     // FIXME: POSIXThreads isn't exactly the option this should be defined for,
660     //        but it works for now.
661     if (Opts.POSIXThreads)
662       Builder.defineMacro("_MT");
663 
664     if (Opts.MSCompatibilityVersion) {
665       Builder.defineMacro("_MSC_VER",
666                           Twine(Opts.MSCompatibilityVersion / 100000));
667       Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
668       // FIXME We cannot encode the revision information into 32-bits
669       Builder.defineMacro("_MSC_BUILD", Twine(1));
670 
671       if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015))
672         Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1));
673     }
674 
675     if (Opts.MicrosoftExt) {
676       Builder.defineMacro("_MSC_EXTENSIONS");
677 
678       if (Opts.CPlusPlus11) {
679         Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
680         Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
681         Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
682       }
683     }
684 
685     Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
686   }
687 
688 public:
689   WindowsTargetInfo(const llvm::Triple &Triple)
690       : OSTargetInfo<Target>(Triple) {}
691 };
692 
693 template <typename Target>
694 class NaClTargetInfo : public OSTargetInfo<Target> {
695 protected:
696   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
697                     MacroBuilder &Builder) const override {
698     if (Opts.POSIXThreads)
699       Builder.defineMacro("_REENTRANT");
700     if (Opts.CPlusPlus)
701       Builder.defineMacro("_GNU_SOURCE");
702 
703     DefineStd(Builder, "unix", Opts);
704     Builder.defineMacro("__ELF__");
705     Builder.defineMacro("__native_client__");
706   }
707 
708 public:
709   NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
710     this->UserLabelPrefix = "";
711     this->LongAlign = 32;
712     this->LongWidth = 32;
713     this->PointerAlign = 32;
714     this->PointerWidth = 32;
715     this->IntMaxType = TargetInfo::SignedLongLong;
716     this->Int64Type = TargetInfo::SignedLongLong;
717     this->DoubleAlign = 64;
718     this->LongDoubleWidth = 64;
719     this->LongDoubleAlign = 64;
720     this->LongLongWidth = 64;
721     this->LongLongAlign = 64;
722     this->SizeType = TargetInfo::UnsignedInt;
723     this->PtrDiffType = TargetInfo::SignedInt;
724     this->IntPtrType = TargetInfo::SignedInt;
725     // RegParmMax is inherited from the underlying architecture
726     this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
727     if (Triple.getArch() == llvm::Triple::arm) {
728       // Handled in ARM's setABI().
729     } else if (Triple.getArch() == llvm::Triple::x86) {
730       this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
731     } else if (Triple.getArch() == llvm::Triple::x86_64) {
732       this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128";
733     } else if (Triple.getArch() == llvm::Triple::mipsel) {
734       // Handled on mips' setDataLayoutString.
735     } else {
736       assert(Triple.getArch() == llvm::Triple::le32);
737       this->DataLayoutString = "e-p:32:32-i64:64";
738     }
739   }
740 };
741 
742 // WebAssembly target
743 template <typename Target>
744 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> {
745   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
746                     MacroBuilder &Builder) const final {
747     // A common platform macro.
748     if (Opts.POSIXThreads)
749       Builder.defineMacro("_REENTRANT");
750     // Follow g++ convention and predefine _GNU_SOURCE for C++.
751     if (Opts.CPlusPlus)
752       Builder.defineMacro("_GNU_SOURCE");
753   }
754 
755   // As an optimization, group static init code together in a section.
756   const char *getStaticInitSectionSpecifier() const final {
757     return ".text.__startup";
758   }
759 
760 public:
761   explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple)
762       : OSTargetInfo<Target>(Triple) {
763     this->MCountName = "__mcount";
764     this->UserLabelPrefix = "";
765     this->TheCXXABI.set(TargetCXXABI::WebAssembly);
766   }
767 };
768 
769 //===----------------------------------------------------------------------===//
770 // Specific target implementations.
771 //===----------------------------------------------------------------------===//
772 
773 // PPC abstract base class
774 class PPCTargetInfo : public TargetInfo {
775   static const Builtin::Info BuiltinInfo[];
776   static const char * const GCCRegNames[];
777   static const TargetInfo::GCCRegAlias GCCRegAliases[];
778   std::string CPU;
779 
780   // Target cpu features.
781   bool HasVSX;
782   bool HasP8Vector;
783   bool HasP8Crypto;
784   bool HasDirectMove;
785   bool HasQPX;
786   bool HasHTM;
787   bool HasBPERMD;
788   bool HasExtDiv;
789 
790 protected:
791   std::string ABI;
792 
793 public:
794   PPCTargetInfo(const llvm::Triple &Triple)
795     : TargetInfo(Triple), HasVSX(false), HasP8Vector(false),
796       HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false),
797       HasBPERMD(false), HasExtDiv(false) {
798     BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
799     SimdDefaultAlign = 128;
800     LongDoubleWidth = LongDoubleAlign = 128;
801     LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
802   }
803 
804   /// \brief Flags for architecture specific defines.
805   typedef enum {
806     ArchDefineNone  = 0,
807     ArchDefineName  = 1 << 0, // <name> is substituted for arch name.
808     ArchDefinePpcgr = 1 << 1,
809     ArchDefinePpcsq = 1 << 2,
810     ArchDefine440   = 1 << 3,
811     ArchDefine603   = 1 << 4,
812     ArchDefine604   = 1 << 5,
813     ArchDefinePwr4  = 1 << 6,
814     ArchDefinePwr5  = 1 << 7,
815     ArchDefinePwr5x = 1 << 8,
816     ArchDefinePwr6  = 1 << 9,
817     ArchDefinePwr6x = 1 << 10,
818     ArchDefinePwr7  = 1 << 11,
819     ArchDefinePwr8  = 1 << 12,
820     ArchDefineA2    = 1 << 13,
821     ArchDefineA2q   = 1 << 14
822   } ArchDefineTypes;
823 
824   // Note: GCC recognizes the following additional cpus:
825   //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
826   //  821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
827   //  titan, rs64.
828   bool setCPU(const std::string &Name) override {
829     bool CPUKnown = llvm::StringSwitch<bool>(Name)
830       .Case("generic", true)
831       .Case("440", true)
832       .Case("450", true)
833       .Case("601", true)
834       .Case("602", true)
835       .Case("603", true)
836       .Case("603e", true)
837       .Case("603ev", true)
838       .Case("604", true)
839       .Case("604e", true)
840       .Case("620", true)
841       .Case("630", true)
842       .Case("g3", true)
843       .Case("7400", true)
844       .Case("g4", true)
845       .Case("7450", true)
846       .Case("g4+", true)
847       .Case("750", true)
848       .Case("970", true)
849       .Case("g5", true)
850       .Case("a2", true)
851       .Case("a2q", true)
852       .Case("e500mc", true)
853       .Case("e5500", true)
854       .Case("power3", true)
855       .Case("pwr3", true)
856       .Case("power4", true)
857       .Case("pwr4", true)
858       .Case("power5", true)
859       .Case("pwr5", true)
860       .Case("power5x", true)
861       .Case("pwr5x", true)
862       .Case("power6", true)
863       .Case("pwr6", true)
864       .Case("power6x", true)
865       .Case("pwr6x", true)
866       .Case("power7", true)
867       .Case("pwr7", true)
868       .Case("power8", true)
869       .Case("pwr8", true)
870       .Case("powerpc", true)
871       .Case("ppc", true)
872       .Case("powerpc64", true)
873       .Case("ppc64", true)
874       .Case("powerpc64le", true)
875       .Case("ppc64le", true)
876       .Default(false);
877 
878     if (CPUKnown)
879       CPU = Name;
880 
881     return CPUKnown;
882   }
883 
884 
885   StringRef getABI() const override { return ABI; }
886 
887   ArrayRef<Builtin::Info> getTargetBuiltins() const override {
888     return llvm::makeArrayRef(BuiltinInfo,
889                              clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin);
890   }
891 
892   bool isCLZForZeroUndef() const override { return false; }
893 
894   void getTargetDefines(const LangOptions &Opts,
895                         MacroBuilder &Builder) const override;
896 
897   bool
898   initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
899                  StringRef CPU,
900                  const std::vector<std::string> &FeaturesVec) const override;
901 
902   bool handleTargetFeatures(std::vector<std::string> &Features,
903                             DiagnosticsEngine &Diags) override;
904   bool hasFeature(StringRef Feature) const override;
905   void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
906                          bool Enabled) const override;
907 
908   ArrayRef<const char *> getGCCRegNames() const override;
909   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
910   bool validateAsmConstraint(const char *&Name,
911                              TargetInfo::ConstraintInfo &Info) const override {
912     switch (*Name) {
913     default: return false;
914     case 'O': // Zero
915       break;
916     case 'b': // Base register
917     case 'f': // Floating point register
918       Info.setAllowsRegister();
919       break;
920     // FIXME: The following are added to allow parsing.
921     // I just took a guess at what the actions should be.
922     // Also, is more specific checking needed?  I.e. specific registers?
923     case 'd': // Floating point register (containing 64-bit value)
924     case 'v': // Altivec vector register
925       Info.setAllowsRegister();
926       break;
927     case 'w':
928       switch (Name[1]) {
929         case 'd':// VSX vector register to hold vector double data
930         case 'f':// VSX vector register to hold vector float data
931         case 's':// VSX vector register to hold scalar float data
932         case 'a':// Any VSX register
933         case 'c':// An individual CR bit
934           break;
935         default:
936           return false;
937       }
938       Info.setAllowsRegister();
939       Name++; // Skip over 'w'.
940       break;
941     case 'h': // `MQ', `CTR', or `LINK' register
942     case 'q': // `MQ' register
943     case 'c': // `CTR' register
944     case 'l': // `LINK' register
945     case 'x': // `CR' register (condition register) number 0
946     case 'y': // `CR' register (condition register)
947     case 'z': // `XER[CA]' carry bit (part of the XER register)
948       Info.setAllowsRegister();
949       break;
950     case 'I': // Signed 16-bit constant
951     case 'J': // Unsigned 16-bit constant shifted left 16 bits
952               //  (use `L' instead for SImode constants)
953     case 'K': // Unsigned 16-bit constant
954     case 'L': // Signed 16-bit constant shifted left 16 bits
955     case 'M': // Constant larger than 31
956     case 'N': // Exact power of 2
957     case 'P': // Constant whose negation is a signed 16-bit constant
958     case 'G': // Floating point constant that can be loaded into a
959               // register with one instruction per word
960     case 'H': // Integer/Floating point constant that can be loaded
961               // into a register using three instructions
962       break;
963     case 'm': // Memory operand. Note that on PowerPC targets, m can
964               // include addresses that update the base register. It
965               // is therefore only safe to use `m' in an asm statement
966               // if that asm statement accesses the operand exactly once.
967               // The asm statement must also use `%U<opno>' as a
968               // placeholder for the "update" flag in the corresponding
969               // load or store instruction. For example:
970               // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
971               // is correct but:
972               // asm ("st %1,%0" : "=m" (mem) : "r" (val));
973               // is not. Use es rather than m if you don't want the base
974               // register to be updated.
975     case 'e':
976       if (Name[1] != 's')
977           return false;
978               // es: A "stable" memory operand; that is, one which does not
979               // include any automodification of the base register. Unlike
980               // `m', this constraint can be used in asm statements that
981               // might access the operand several times, or that might not
982               // access it at all.
983       Info.setAllowsMemory();
984       Name++; // Skip over 'e'.
985       break;
986     case 'Q': // Memory operand that is an offset from a register (it is
987               // usually better to use `m' or `es' in asm statements)
988     case 'Z': // Memory operand that is an indexed or indirect from a
989               // register (it is usually better to use `m' or `es' in
990               // asm statements)
991       Info.setAllowsMemory();
992       Info.setAllowsRegister();
993       break;
994     case 'R': // AIX TOC entry
995     case 'a': // Address operand that is an indexed or indirect from a
996               // register (`p' is preferable for asm statements)
997     case 'S': // Constant suitable as a 64-bit mask operand
998     case 'T': // Constant suitable as a 32-bit mask operand
999     case 'U': // System V Release 4 small data area reference
1000     case 't': // AND masks that can be performed by two rldic{l, r}
1001               // instructions
1002     case 'W': // Vector constant that does not require memory
1003     case 'j': // Vector constant that is all zeros.
1004       break;
1005     // End FIXME.
1006     }
1007     return true;
1008   }
1009   std::string convertConstraint(const char *&Constraint) const override {
1010     std::string R;
1011     switch (*Constraint) {
1012     case 'e':
1013     case 'w':
1014       // Two-character constraint; add "^" hint for later parsing.
1015       R = std::string("^") + std::string(Constraint, 2);
1016       Constraint++;
1017       break;
1018     default:
1019       return TargetInfo::convertConstraint(Constraint);
1020     }
1021     return R;
1022   }
1023   const char *getClobbers() const override {
1024     return "";
1025   }
1026   int getEHDataRegisterNumber(unsigned RegNo) const override {
1027     if (RegNo == 0) return 3;
1028     if (RegNo == 1) return 4;
1029     return -1;
1030   }
1031 
1032   bool hasSjLjLowering() const override {
1033     return true;
1034   }
1035 
1036   bool useFloat128ManglingForLongDouble() const override {
1037     return LongDoubleWidth == 128 &&
1038            LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble &&
1039            getTriple().isOSBinFormatELF();
1040   }
1041 };
1042 
1043 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
1044 #define BUILTIN(ID, TYPE, ATTRS) \
1045   { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1046 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
1047   { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
1048 #include "clang/Basic/BuiltinsPPC.def"
1049 };
1050 
1051 /// handleTargetFeatures - Perform initialization based on the user
1052 /// configured set of features.
1053 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
1054                                          DiagnosticsEngine &Diags) {
1055   for (const auto &Feature : Features) {
1056     if (Feature == "+vsx") {
1057       HasVSX = true;
1058     } else if (Feature == "+bpermd") {
1059       HasBPERMD = true;
1060     } else if (Feature == "+extdiv") {
1061       HasExtDiv = true;
1062     } else if (Feature == "+power8-vector") {
1063       HasP8Vector = true;
1064     } else if (Feature == "+crypto") {
1065       HasP8Crypto = true;
1066     } else if (Feature == "+direct-move") {
1067       HasDirectMove = true;
1068     } else if (Feature == "+qpx") {
1069       HasQPX = true;
1070     } else if (Feature == "+htm") {
1071       HasHTM = true;
1072     }
1073     // TODO: Finish this list and add an assert that we've handled them
1074     // all.
1075   }
1076 
1077   return true;
1078 }
1079 
1080 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
1081 /// #defines that are not tied to a specific subtarget.
1082 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
1083                                      MacroBuilder &Builder) const {
1084   // Target identification.
1085   Builder.defineMacro("__ppc__");
1086   Builder.defineMacro("__PPC__");
1087   Builder.defineMacro("_ARCH_PPC");
1088   Builder.defineMacro("__powerpc__");
1089   Builder.defineMacro("__POWERPC__");
1090   if (PointerWidth == 64) {
1091     Builder.defineMacro("_ARCH_PPC64");
1092     Builder.defineMacro("__powerpc64__");
1093     Builder.defineMacro("__ppc64__");
1094     Builder.defineMacro("__PPC64__");
1095   }
1096 
1097   // Target properties.
1098   if (getTriple().getArch() == llvm::Triple::ppc64le) {
1099     Builder.defineMacro("_LITTLE_ENDIAN");
1100   } else {
1101     if (getTriple().getOS() != llvm::Triple::NetBSD &&
1102         getTriple().getOS() != llvm::Triple::OpenBSD)
1103       Builder.defineMacro("_BIG_ENDIAN");
1104   }
1105 
1106   // ABI options.
1107   if (ABI == "elfv1" || ABI == "elfv1-qpx")
1108     Builder.defineMacro("_CALL_ELF", "1");
1109   if (ABI == "elfv2")
1110     Builder.defineMacro("_CALL_ELF", "2");
1111 
1112   // Subtarget options.
1113   Builder.defineMacro("__NATURAL_ALIGNMENT__");
1114   Builder.defineMacro("__REGISTER_PREFIX__", "");
1115 
1116   // FIXME: Should be controlled by command line option.
1117   if (LongDoubleWidth == 128)
1118     Builder.defineMacro("__LONG_DOUBLE_128__");
1119 
1120   if (Opts.AltiVec) {
1121     Builder.defineMacro("__VEC__", "10206");
1122     Builder.defineMacro("__ALTIVEC__");
1123   }
1124 
1125   // CPU identification.
1126   ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1127     .Case("440",   ArchDefineName)
1128     .Case("450",   ArchDefineName | ArchDefine440)
1129     .Case("601",   ArchDefineName)
1130     .Case("602",   ArchDefineName | ArchDefinePpcgr)
1131     .Case("603",   ArchDefineName | ArchDefinePpcgr)
1132     .Case("603e",  ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1133     .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1134     .Case("604",   ArchDefineName | ArchDefinePpcgr)
1135     .Case("604e",  ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1136     .Case("620",   ArchDefineName | ArchDefinePpcgr)
1137     .Case("630",   ArchDefineName | ArchDefinePpcgr)
1138     .Case("7400",  ArchDefineName | ArchDefinePpcgr)
1139     .Case("7450",  ArchDefineName | ArchDefinePpcgr)
1140     .Case("750",   ArchDefineName | ArchDefinePpcgr)
1141     .Case("970",   ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1142                      | ArchDefinePpcsq)
1143     .Case("a2",    ArchDefineA2)
1144     .Case("a2q",   ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1145     .Case("pwr3",  ArchDefinePpcgr)
1146     .Case("pwr4",  ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1147     .Case("pwr5",  ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1148                      | ArchDefinePpcsq)
1149     .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1150                      | ArchDefinePpcgr | ArchDefinePpcsq)
1151     .Case("pwr6",  ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1152                      | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1153     .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1154                      | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1155                      | ArchDefinePpcsq)
1156     .Case("pwr7",  ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1157                      | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1158                      | ArchDefinePpcgr | ArchDefinePpcsq)
1159     .Case("pwr8",  ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1160                      | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1161                      | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1162     .Case("power3",  ArchDefinePpcgr)
1163     .Case("power4",  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1164     .Case("power5",  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1165                        | ArchDefinePpcsq)
1166     .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1167                        | ArchDefinePpcgr | ArchDefinePpcsq)
1168     .Case("power6",  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1169                        | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1170     .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1171                        | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1172                        | ArchDefinePpcsq)
1173     .Case("power7",  ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1174                        | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1175                        | ArchDefinePpcgr | ArchDefinePpcsq)
1176     .Case("power8",  ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1177                        | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1178                        | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1179     .Default(ArchDefineNone);
1180 
1181   if (defs & ArchDefineName)
1182     Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1183   if (defs & ArchDefinePpcgr)
1184     Builder.defineMacro("_ARCH_PPCGR");
1185   if (defs & ArchDefinePpcsq)
1186     Builder.defineMacro("_ARCH_PPCSQ");
1187   if (defs & ArchDefine440)
1188     Builder.defineMacro("_ARCH_440");
1189   if (defs & ArchDefine603)
1190     Builder.defineMacro("_ARCH_603");
1191   if (defs & ArchDefine604)
1192     Builder.defineMacro("_ARCH_604");
1193   if (defs & ArchDefinePwr4)
1194     Builder.defineMacro("_ARCH_PWR4");
1195   if (defs & ArchDefinePwr5)
1196     Builder.defineMacro("_ARCH_PWR5");
1197   if (defs & ArchDefinePwr5x)
1198     Builder.defineMacro("_ARCH_PWR5X");
1199   if (defs & ArchDefinePwr6)
1200     Builder.defineMacro("_ARCH_PWR6");
1201   if (defs & ArchDefinePwr6x)
1202     Builder.defineMacro("_ARCH_PWR6X");
1203   if (defs & ArchDefinePwr7)
1204     Builder.defineMacro("_ARCH_PWR7");
1205   if (defs & ArchDefinePwr8)
1206     Builder.defineMacro("_ARCH_PWR8");
1207   if (defs & ArchDefineA2)
1208     Builder.defineMacro("_ARCH_A2");
1209   if (defs & ArchDefineA2q) {
1210     Builder.defineMacro("_ARCH_A2Q");
1211     Builder.defineMacro("_ARCH_QP");
1212   }
1213 
1214   if (getTriple().getVendor() == llvm::Triple::BGQ) {
1215     Builder.defineMacro("__bg__");
1216     Builder.defineMacro("__THW_BLUEGENE__");
1217     Builder.defineMacro("__bgq__");
1218     Builder.defineMacro("__TOS_BGQ__");
1219   }
1220 
1221   if (HasVSX)
1222     Builder.defineMacro("__VSX__");
1223   if (HasP8Vector)
1224     Builder.defineMacro("__POWER8_VECTOR__");
1225   if (HasP8Crypto)
1226     Builder.defineMacro("__CRYPTO__");
1227   if (HasHTM)
1228     Builder.defineMacro("__HTM__");
1229 
1230   Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1231   Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1232   Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1233   if (PointerWidth == 64)
1234     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1235 
1236   // FIXME: The following are not yet generated here by Clang, but are
1237   //        generated by GCC:
1238   //
1239   //   _SOFT_FLOAT_
1240   //   __RECIP_PRECISION__
1241   //   __APPLE_ALTIVEC__
1242   //   __RECIP__
1243   //   __RECIPF__
1244   //   __RSQRTE__
1245   //   __RSQRTEF__
1246   //   _SOFT_DOUBLE_
1247   //   __NO_LWSYNC__
1248   //   __HAVE_BSWAP__
1249   //   __LONGDOUBLE128
1250   //   __CMODEL_MEDIUM__
1251   //   __CMODEL_LARGE__
1252   //   _CALL_SYSV
1253   //   _CALL_DARWIN
1254   //   __NO_FPRS__
1255 }
1256 
1257 // Handle explicit options being passed to the compiler here: if we've
1258 // explicitly turned off vsx and turned on power8-vector or direct-move then
1259 // go ahead and error since the customer has expressed a somewhat incompatible
1260 // set of options.
1261 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
1262                                  const std::vector<std::string> &FeaturesVec) {
1263 
1264   if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") !=
1265       FeaturesVec.end()) {
1266     if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") !=
1267         FeaturesVec.end()) {
1268       Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector"
1269                                                      << "-mno-vsx";
1270       return false;
1271     }
1272 
1273     if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") !=
1274         FeaturesVec.end()) {
1275       Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move"
1276                                                      << "-mno-vsx";
1277       return false;
1278     }
1279   }
1280 
1281   return true;
1282 }
1283 
1284 bool PPCTargetInfo::initFeatureMap(
1285     llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
1286     const std::vector<std::string> &FeaturesVec) const {
1287   Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1288     .Case("7400", true)
1289     .Case("g4", true)
1290     .Case("7450", true)
1291     .Case("g4+", true)
1292     .Case("970", true)
1293     .Case("g5", true)
1294     .Case("pwr6", true)
1295     .Case("pwr7", true)
1296     .Case("pwr8", true)
1297     .Case("ppc64", true)
1298     .Case("ppc64le", true)
1299     .Default(false);
1300 
1301   Features["qpx"] = (CPU == "a2q");
1302   Features["crypto"] = llvm::StringSwitch<bool>(CPU)
1303     .Case("ppc64le", true)
1304     .Case("pwr8", true)
1305     .Default(false);
1306   Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
1307     .Case("ppc64le", true)
1308     .Case("pwr8", true)
1309     .Default(false);
1310   Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
1311     .Case("ppc64le", true)
1312     .Case("pwr8", true)
1313     .Case("pwr7", true)
1314     .Default(false);
1315   Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
1316     .Case("ppc64le", true)
1317     .Case("pwr8", true)
1318     .Case("pwr7", true)
1319     .Default(false);
1320   Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
1321     .Case("ppc64le", true)
1322     .Case("pwr8", true)
1323     .Default(false);
1324   Features["vsx"] = llvm::StringSwitch<bool>(CPU)
1325     .Case("ppc64le", true)
1326     .Case("pwr8", true)
1327     .Case("pwr7", true)
1328     .Default(false);
1329 
1330   if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
1331     return false;
1332 
1333   return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
1334 }
1335 
1336 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1337   return llvm::StringSwitch<bool>(Feature)
1338     .Case("powerpc", true)
1339     .Case("vsx", HasVSX)
1340     .Case("power8-vector", HasP8Vector)
1341     .Case("crypto", HasP8Crypto)
1342     .Case("direct-move", HasDirectMove)
1343     .Case("qpx", HasQPX)
1344     .Case("htm", HasHTM)
1345     .Case("bpermd", HasBPERMD)
1346     .Case("extdiv", HasExtDiv)
1347     .Default(false);
1348 }
1349 
1350 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
1351                                       StringRef Name, bool Enabled) const {
1352   // If we're enabling direct-move or power8-vector go ahead and enable vsx
1353   // as well. Do the inverse if we're disabling vsx. We'll diagnose any user
1354   // incompatible options.
1355   if (Enabled) {
1356     if (Name == "vsx") {
1357      Features[Name] = true;
1358     } else if (Name == "direct-move") {
1359       Features[Name] = Features["vsx"] = true;
1360     } else if (Name == "power8-vector") {
1361       Features[Name] = Features["vsx"] = true;
1362     } else {
1363       Features[Name] = true;
1364     }
1365   } else {
1366     if (Name == "vsx") {
1367       Features[Name] = Features["direct-move"] = Features["power8-vector"] =
1368           false;
1369     } else {
1370       Features[Name] = false;
1371     }
1372   }
1373 }
1374 
1375 const char * const PPCTargetInfo::GCCRegNames[] = {
1376   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1377   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1378   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1379   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1380   "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1381   "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1382   "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1383   "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1384   "mq", "lr", "ctr", "ap",
1385   "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1386   "xer",
1387   "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1388   "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1389   "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1390   "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1391   "vrsave", "vscr",
1392   "spe_acc", "spefscr",
1393   "sfp"
1394 };
1395 
1396 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const {
1397   return llvm::makeArrayRef(GCCRegNames);
1398 }
1399 
1400 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1401   // While some of these aliases do map to different registers
1402   // they still share the same register name.
1403   { { "0" }, "r0" },
1404   { { "1"}, "r1" },
1405   { { "2" }, "r2" },
1406   { { "3" }, "r3" },
1407   { { "4" }, "r4" },
1408   { { "5" }, "r5" },
1409   { { "6" }, "r6" },
1410   { { "7" }, "r7" },
1411   { { "8" }, "r8" },
1412   { { "9" }, "r9" },
1413   { { "10" }, "r10" },
1414   { { "11" }, "r11" },
1415   { { "12" }, "r12" },
1416   { { "13" }, "r13" },
1417   { { "14" }, "r14" },
1418   { { "15" }, "r15" },
1419   { { "16" }, "r16" },
1420   { { "17" }, "r17" },
1421   { { "18" }, "r18" },
1422   { { "19" }, "r19" },
1423   { { "20" }, "r20" },
1424   { { "21" }, "r21" },
1425   { { "22" }, "r22" },
1426   { { "23" }, "r23" },
1427   { { "24" }, "r24" },
1428   { { "25" }, "r25" },
1429   { { "26" }, "r26" },
1430   { { "27" }, "r27" },
1431   { { "28" }, "r28" },
1432   { { "29" }, "r29" },
1433   { { "30" }, "r30" },
1434   { { "31" }, "r31" },
1435   { { "fr0" }, "f0" },
1436   { { "fr1" }, "f1" },
1437   { { "fr2" }, "f2" },
1438   { { "fr3" }, "f3" },
1439   { { "fr4" }, "f4" },
1440   { { "fr5" }, "f5" },
1441   { { "fr6" }, "f6" },
1442   { { "fr7" }, "f7" },
1443   { { "fr8" }, "f8" },
1444   { { "fr9" }, "f9" },
1445   { { "fr10" }, "f10" },
1446   { { "fr11" }, "f11" },
1447   { { "fr12" }, "f12" },
1448   { { "fr13" }, "f13" },
1449   { { "fr14" }, "f14" },
1450   { { "fr15" }, "f15" },
1451   { { "fr16" }, "f16" },
1452   { { "fr17" }, "f17" },
1453   { { "fr18" }, "f18" },
1454   { { "fr19" }, "f19" },
1455   { { "fr20" }, "f20" },
1456   { { "fr21" }, "f21" },
1457   { { "fr22" }, "f22" },
1458   { { "fr23" }, "f23" },
1459   { { "fr24" }, "f24" },
1460   { { "fr25" }, "f25" },
1461   { { "fr26" }, "f26" },
1462   { { "fr27" }, "f27" },
1463   { { "fr28" }, "f28" },
1464   { { "fr29" }, "f29" },
1465   { { "fr30" }, "f30" },
1466   { { "fr31" }, "f31" },
1467   { { "cc" }, "cr0" },
1468 };
1469 
1470 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const {
1471   return llvm::makeArrayRef(GCCRegAliases);
1472 }
1473 
1474 class PPC32TargetInfo : public PPCTargetInfo {
1475 public:
1476   PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1477     DataLayoutString = "E-m:e-p:32:32-i64:64-n32";
1478 
1479     switch (getTriple().getOS()) {
1480     case llvm::Triple::Linux:
1481     case llvm::Triple::FreeBSD:
1482     case llvm::Triple::NetBSD:
1483       SizeType = UnsignedInt;
1484       PtrDiffType = SignedInt;
1485       IntPtrType = SignedInt;
1486       break;
1487     default:
1488       break;
1489     }
1490 
1491     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1492       LongDoubleWidth = LongDoubleAlign = 64;
1493       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1494     }
1495 
1496     // PPC32 supports atomics up to 4 bytes.
1497     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1498   }
1499 
1500   BuiltinVaListKind getBuiltinVaListKind() const override {
1501     // This is the ELF definition, and is overridden by the Darwin sub-target
1502     return TargetInfo::PowerABIBuiltinVaList;
1503   }
1504 };
1505 
1506 // Note: ABI differences may eventually require us to have a separate
1507 // TargetInfo for little endian.
1508 class PPC64TargetInfo : public PPCTargetInfo {
1509 public:
1510   PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1511     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1512     IntMaxType = SignedLong;
1513     Int64Type = SignedLong;
1514 
1515     if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1516       DataLayoutString = "e-m:e-i64:64-n32:64";
1517       ABI = "elfv2";
1518     } else {
1519       DataLayoutString = "E-m:e-i64:64-n32:64";
1520       ABI = "elfv1";
1521     }
1522 
1523     switch (getTriple().getOS()) {
1524     case llvm::Triple::FreeBSD:
1525       LongDoubleWidth = LongDoubleAlign = 64;
1526       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1527       break;
1528     case llvm::Triple::NetBSD:
1529       IntMaxType = SignedLongLong;
1530       Int64Type = SignedLongLong;
1531       break;
1532     default:
1533       break;
1534     }
1535 
1536     // PPC64 supports atomics up to 8 bytes.
1537     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1538   }
1539   BuiltinVaListKind getBuiltinVaListKind() const override {
1540     return TargetInfo::CharPtrBuiltinVaList;
1541   }
1542   // PPC64 Linux-specific ABI options.
1543   bool setABI(const std::string &Name) override {
1544     if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
1545       ABI = Name;
1546       return true;
1547     }
1548     return false;
1549   }
1550 };
1551 
1552 class DarwinPPC32TargetInfo :
1553   public DarwinTargetInfo<PPC32TargetInfo> {
1554 public:
1555   DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1556       : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1557     HasAlignMac68kSupport = true;
1558     BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1559     PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1560     LongLongAlign = 32;
1561     SuitableAlign = 128;
1562     DataLayoutString = "E-m:o-p:32:32-f64:32:64-n32";
1563   }
1564   BuiltinVaListKind getBuiltinVaListKind() const override {
1565     return TargetInfo::CharPtrBuiltinVaList;
1566   }
1567 };
1568 
1569 class DarwinPPC64TargetInfo :
1570   public DarwinTargetInfo<PPC64TargetInfo> {
1571 public:
1572   DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1573       : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1574     HasAlignMac68kSupport = true;
1575     SuitableAlign = 128;
1576     DataLayoutString = "E-m:o-i64:64-n32:64";
1577   }
1578 };
1579 
1580 static const unsigned NVPTXAddrSpaceMap[] = {
1581     1, // opencl_global
1582     3, // opencl_local
1583     4, // opencl_constant
1584     // FIXME: generic has to be added to the target
1585     0, // opencl_generic
1586     1, // cuda_device
1587     4, // cuda_constant
1588     3, // cuda_shared
1589 };
1590 
1591 class NVPTXTargetInfo : public TargetInfo {
1592   static const char *const GCCRegNames[];
1593   static const Builtin::Info BuiltinInfo[];
1594 
1595   // The GPU profiles supported by the NVPTX backend
1596   enum GPUKind {
1597     GK_NONE,
1598     GK_SM20,
1599     GK_SM21,
1600     GK_SM30,
1601     GK_SM35,
1602     GK_SM37,
1603   } GPU;
1604 
1605 public:
1606   NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1607     BigEndian = false;
1608     TLSSupported = false;
1609     LongWidth = LongAlign = 64;
1610     AddrSpaceMap = &NVPTXAddrSpaceMap;
1611     UseAddrSpaceMapMangling = true;
1612     // Define available target features
1613     // These must be defined in sorted order!
1614     NoAsmVariants = true;
1615     // Set the default GPU to sm20
1616     GPU = GK_SM20;
1617   }
1618   void getTargetDefines(const LangOptions &Opts,
1619                         MacroBuilder &Builder) const override {
1620     Builder.defineMacro("__PTX__");
1621     Builder.defineMacro("__NVPTX__");
1622     if (Opts.CUDAIsDevice) {
1623       // Set __CUDA_ARCH__ for the GPU specified.
1624       std::string CUDAArchCode;
1625       switch (GPU) {
1626       case GK_SM20:
1627         CUDAArchCode = "200";
1628         break;
1629       case GK_SM21:
1630         CUDAArchCode = "210";
1631         break;
1632       case GK_SM30:
1633         CUDAArchCode = "300";
1634         break;
1635       case GK_SM35:
1636         CUDAArchCode = "350";
1637         break;
1638       case GK_SM37:
1639         CUDAArchCode = "370";
1640         break;
1641       default:
1642         llvm_unreachable("Unhandled target CPU");
1643       }
1644       Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1645     }
1646   }
1647   ArrayRef<Builtin::Info> getTargetBuiltins() const override {
1648     return llvm::makeArrayRef(BuiltinInfo,
1649                          clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin);
1650   }
1651   bool hasFeature(StringRef Feature) const override {
1652     return Feature == "ptx" || Feature == "nvptx";
1653   }
1654 
1655   ArrayRef<const char *> getGCCRegNames() const override;
1656   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
1657     // No aliases.
1658     return None;
1659   }
1660   bool validateAsmConstraint(const char *&Name,
1661                              TargetInfo::ConstraintInfo &Info) const override {
1662     switch (*Name) {
1663     default:
1664       return false;
1665     case 'c':
1666     case 'h':
1667     case 'r':
1668     case 'l':
1669     case 'f':
1670     case 'd':
1671       Info.setAllowsRegister();
1672       return true;
1673     }
1674   }
1675   const char *getClobbers() const override {
1676     // FIXME: Is this really right?
1677     return "";
1678   }
1679   BuiltinVaListKind getBuiltinVaListKind() const override {
1680     // FIXME: implement
1681     return TargetInfo::CharPtrBuiltinVaList;
1682   }
1683   bool setCPU(const std::string &Name) override {
1684     GPU = llvm::StringSwitch<GPUKind>(Name)
1685               .Case("sm_20", GK_SM20)
1686               .Case("sm_21", GK_SM21)
1687               .Case("sm_30", GK_SM30)
1688               .Case("sm_35", GK_SM35)
1689               .Case("sm_37", GK_SM37)
1690               .Default(GK_NONE);
1691 
1692     return GPU != GK_NONE;
1693   }
1694 };
1695 
1696 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1697 #define BUILTIN(ID, TYPE, ATTRS)                                               \
1698   { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1699 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER)                                    \
1700   { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
1701 #include "clang/Basic/BuiltinsNVPTX.def"
1702 };
1703 
1704 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"};
1705 
1706 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const {
1707   return llvm::makeArrayRef(GCCRegNames);
1708 }
1709 
1710 class NVPTX32TargetInfo : public NVPTXTargetInfo {
1711 public:
1712   NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1713     LongWidth = LongAlign = 32;
1714     PointerWidth = PointerAlign = 32;
1715     SizeType = TargetInfo::UnsignedInt;
1716     PtrDiffType = TargetInfo::SignedInt;
1717     IntPtrType = TargetInfo::SignedInt;
1718     DataLayoutString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
1719   }
1720 };
1721 
1722 class NVPTX64TargetInfo : public NVPTXTargetInfo {
1723 public:
1724   NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1725     PointerWidth = PointerAlign = 64;
1726     SizeType = TargetInfo::UnsignedLong;
1727     PtrDiffType = TargetInfo::SignedLong;
1728     IntPtrType = TargetInfo::SignedLong;
1729     DataLayoutString = "e-i64:64-v16:16-v32:32-n16:32:64";
1730   }
1731 };
1732 
1733 static const unsigned AMDGPUAddrSpaceMap[] = {
1734   1,    // opencl_global
1735   3,    // opencl_local
1736   2,    // opencl_constant
1737   4,    // opencl_generic
1738   1,    // cuda_device
1739   2,    // cuda_constant
1740   3     // cuda_shared
1741 };
1742 
1743 // If you edit the description strings, make sure you update
1744 // getPointerWidthV().
1745 
1746 static const char *const DataLayoutStringR600 =
1747   "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1748   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1749 
1750 static const char *const DataLayoutStringR600DoubleOps =
1751   "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1752   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1753 
1754 static const char *const DataLayoutStringSI =
1755   "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"
1756   "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1757   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1758 
1759 class AMDGPUTargetInfo : public TargetInfo {
1760   static const Builtin::Info BuiltinInfo[];
1761   static const char * const GCCRegNames[];
1762 
1763   /// \brief The GPU profiles supported by the AMDGPU target.
1764   enum GPUKind {
1765     GK_NONE,
1766     GK_R600,
1767     GK_R600_DOUBLE_OPS,
1768     GK_R700,
1769     GK_R700_DOUBLE_OPS,
1770     GK_EVERGREEN,
1771     GK_EVERGREEN_DOUBLE_OPS,
1772     GK_NORTHERN_ISLANDS,
1773     GK_CAYMAN,
1774     GK_SOUTHERN_ISLANDS,
1775     GK_SEA_ISLANDS,
1776     GK_VOLCANIC_ISLANDS
1777   } GPU;
1778 
1779   bool hasFP64:1;
1780   bool hasFMAF:1;
1781   bool hasLDEXPF:1;
1782 
1783 public:
1784   AMDGPUTargetInfo(const llvm::Triple &Triple)
1785     : TargetInfo(Triple) {
1786 
1787     if (Triple.getArch() == llvm::Triple::amdgcn) {
1788       DataLayoutString = DataLayoutStringSI;
1789       GPU = GK_SOUTHERN_ISLANDS;
1790       hasFP64 = true;
1791       hasFMAF = true;
1792       hasLDEXPF = true;
1793     } else {
1794       DataLayoutString = DataLayoutStringR600;
1795       GPU = GK_R600;
1796       hasFP64 = false;
1797       hasFMAF = false;
1798       hasLDEXPF = false;
1799     }
1800     AddrSpaceMap = &AMDGPUAddrSpaceMap;
1801     UseAddrSpaceMapMangling = true;
1802   }
1803 
1804   uint64_t getPointerWidthV(unsigned AddrSpace) const override {
1805     if (GPU <= GK_CAYMAN)
1806       return 32;
1807 
1808     switch(AddrSpace) {
1809       default:
1810         return 64;
1811       case 0:
1812       case 3:
1813       case 5:
1814         return 32;
1815     }
1816   }
1817 
1818   const char * getClobbers() const override {
1819     return "";
1820   }
1821 
1822   ArrayRef<const char *> getGCCRegNames() const override;
1823 
1824   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
1825     return None;
1826   }
1827 
1828   bool validateAsmConstraint(const char *&Name,
1829                              TargetInfo::ConstraintInfo &info) const override {
1830     return true;
1831   }
1832 
1833   ArrayRef<Builtin::Info> getTargetBuiltins() const override {
1834     return llvm::makeArrayRef(BuiltinInfo,
1835                         clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin);
1836   }
1837 
1838   void getTargetDefines(const LangOptions &Opts,
1839                         MacroBuilder &Builder) const override {
1840     Builder.defineMacro("__R600__");
1841     if (hasFMAF)
1842       Builder.defineMacro("__HAS_FMAF__");
1843     if (hasLDEXPF)
1844       Builder.defineMacro("__HAS_LDEXPF__");
1845     if (hasFP64 && Opts.OpenCL)
1846       Builder.defineMacro("cl_khr_fp64");
1847     if (Opts.OpenCL) {
1848       if (GPU >= GK_NORTHERN_ISLANDS) {
1849         Builder.defineMacro("cl_khr_byte_addressable_store");
1850         Builder.defineMacro("cl_khr_global_int32_base_atomics");
1851         Builder.defineMacro("cl_khr_global_int32_extended_atomics");
1852         Builder.defineMacro("cl_khr_local_int32_base_atomics");
1853         Builder.defineMacro("cl_khr_local_int32_extended_atomics");
1854       }
1855     }
1856   }
1857 
1858   BuiltinVaListKind getBuiltinVaListKind() const override {
1859     return TargetInfo::CharPtrBuiltinVaList;
1860   }
1861 
1862   bool setCPU(const std::string &Name) override {
1863     GPU = llvm::StringSwitch<GPUKind>(Name)
1864       .Case("r600" ,    GK_R600)
1865       .Case("rv610",    GK_R600)
1866       .Case("rv620",    GK_R600)
1867       .Case("rv630",    GK_R600)
1868       .Case("rv635",    GK_R600)
1869       .Case("rs780",    GK_R600)
1870       .Case("rs880",    GK_R600)
1871       .Case("rv670",    GK_R600_DOUBLE_OPS)
1872       .Case("rv710",    GK_R700)
1873       .Case("rv730",    GK_R700)
1874       .Case("rv740",    GK_R700_DOUBLE_OPS)
1875       .Case("rv770",    GK_R700_DOUBLE_OPS)
1876       .Case("palm",     GK_EVERGREEN)
1877       .Case("cedar",    GK_EVERGREEN)
1878       .Case("sumo",     GK_EVERGREEN)
1879       .Case("sumo2",    GK_EVERGREEN)
1880       .Case("redwood",  GK_EVERGREEN)
1881       .Case("juniper",  GK_EVERGREEN)
1882       .Case("hemlock",  GK_EVERGREEN_DOUBLE_OPS)
1883       .Case("cypress",  GK_EVERGREEN_DOUBLE_OPS)
1884       .Case("barts",    GK_NORTHERN_ISLANDS)
1885       .Case("turks",    GK_NORTHERN_ISLANDS)
1886       .Case("caicos",   GK_NORTHERN_ISLANDS)
1887       .Case("cayman",   GK_CAYMAN)
1888       .Case("aruba",    GK_CAYMAN)
1889       .Case("tahiti",   GK_SOUTHERN_ISLANDS)
1890       .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1891       .Case("verde",    GK_SOUTHERN_ISLANDS)
1892       .Case("oland",    GK_SOUTHERN_ISLANDS)
1893       .Case("hainan",   GK_SOUTHERN_ISLANDS)
1894       .Case("bonaire",  GK_SEA_ISLANDS)
1895       .Case("kabini",   GK_SEA_ISLANDS)
1896       .Case("kaveri",   GK_SEA_ISLANDS)
1897       .Case("hawaii",   GK_SEA_ISLANDS)
1898       .Case("mullins",  GK_SEA_ISLANDS)
1899       .Case("tonga",    GK_VOLCANIC_ISLANDS)
1900       .Case("iceland",  GK_VOLCANIC_ISLANDS)
1901       .Case("carrizo",  GK_VOLCANIC_ISLANDS)
1902       .Default(GK_NONE);
1903 
1904     if (GPU == GK_NONE) {
1905       return false;
1906     }
1907 
1908     // Set the correct data layout
1909     switch (GPU) {
1910     case GK_NONE:
1911     case GK_R600:
1912     case GK_R700:
1913     case GK_EVERGREEN:
1914     case GK_NORTHERN_ISLANDS:
1915       DataLayoutString = DataLayoutStringR600;
1916       hasFP64 = false;
1917       hasFMAF = false;
1918       hasLDEXPF = false;
1919       break;
1920     case GK_R600_DOUBLE_OPS:
1921     case GK_R700_DOUBLE_OPS:
1922     case GK_EVERGREEN_DOUBLE_OPS:
1923     case GK_CAYMAN:
1924       DataLayoutString = DataLayoutStringR600DoubleOps;
1925       hasFP64 = true;
1926       hasFMAF = true;
1927       hasLDEXPF = false;
1928       break;
1929     case GK_SOUTHERN_ISLANDS:
1930     case GK_SEA_ISLANDS:
1931     case GK_VOLCANIC_ISLANDS:
1932       DataLayoutString = DataLayoutStringSI;
1933       hasFP64 = true;
1934       hasFMAF = true;
1935       hasLDEXPF = true;
1936       break;
1937     }
1938 
1939     return true;
1940   }
1941 };
1942 
1943 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = {
1944 #define BUILTIN(ID, TYPE, ATTRS)                \
1945   { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
1946 #include "clang/Basic/BuiltinsAMDGPU.def"
1947 };
1948 const char * const AMDGPUTargetInfo::GCCRegNames[] = {
1949   "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1950   "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1951   "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1952   "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1953   "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39",
1954   "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47",
1955   "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55",
1956   "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63",
1957   "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
1958   "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79",
1959   "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87",
1960   "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95",
1961   "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103",
1962   "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111",
1963   "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119",
1964   "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127",
1965   "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135",
1966   "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143",
1967   "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151",
1968   "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159",
1969   "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167",
1970   "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175",
1971   "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183",
1972   "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191",
1973   "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199",
1974   "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207",
1975   "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215",
1976   "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223",
1977   "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231",
1978   "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239",
1979   "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247",
1980   "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255",
1981   "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
1982   "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
1983   "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
1984   "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
1985   "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
1986   "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47",
1987   "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55",
1988   "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63",
1989   "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71",
1990   "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
1991   "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87",
1992   "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95",
1993   "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
1994   "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111",
1995   "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119",
1996   "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127"
1997   "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi",
1998   "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi"
1999 };
2000 
2001 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const {
2002   return llvm::makeArrayRef(GCCRegNames);
2003 }
2004 
2005 // Namespace for x86 abstract base class
2006 const Builtin::Info BuiltinInfo[] = {
2007 #define BUILTIN(ID, TYPE, ATTRS)                                               \
2008   { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
2009 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER)                                    \
2010   { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
2011 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
2012   { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE },
2013 #include "clang/Basic/BuiltinsX86.def"
2014 };
2015 
2016 static const char* const GCCRegNames[] = {
2017   "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
2018   "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
2019   "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
2020   "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
2021   "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
2022   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
2023   "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
2024   "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
2025   "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
2026 };
2027 
2028 const TargetInfo::AddlRegName AddlRegNames[] = {
2029   { { "al", "ah", "eax", "rax" }, 0 },
2030   { { "bl", "bh", "ebx", "rbx" }, 3 },
2031   { { "cl", "ch", "ecx", "rcx" }, 2 },
2032   { { "dl", "dh", "edx", "rdx" }, 1 },
2033   { { "esi", "rsi" }, 4 },
2034   { { "edi", "rdi" }, 5 },
2035   { { "esp", "rsp" }, 7 },
2036   { { "ebp", "rbp" }, 6 },
2037   { { "r8d", "r8w", "r8b" }, 38 },
2038   { { "r9d", "r9w", "r9b" }, 39 },
2039   { { "r10d", "r10w", "r10b" }, 40 },
2040   { { "r11d", "r11w", "r11b" }, 41 },
2041   { { "r12d", "r12w", "r12b" }, 42 },
2042   { { "r13d", "r13w", "r13b" }, 43 },
2043   { { "r14d", "r14w", "r14b" }, 44 },
2044   { { "r15d", "r15w", "r15b" }, 45 },
2045 };
2046 
2047 // X86 target abstract base class; x86-32 and x86-64 are very close, so
2048 // most of the implementation can be shared.
2049 class X86TargetInfo : public TargetInfo {
2050   enum X86SSEEnum {
2051     NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
2052   } SSELevel = NoSSE;
2053   enum MMX3DNowEnum {
2054     NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
2055   } MMX3DNowLevel = NoMMX3DNow;
2056   enum XOPEnum {
2057     NoXOP,
2058     SSE4A,
2059     FMA4,
2060     XOP
2061   } XOPLevel = NoXOP;
2062 
2063   bool HasAES = false;
2064   bool HasPCLMUL = false;
2065   bool HasLZCNT = false;
2066   bool HasRDRND = false;
2067   bool HasFSGSBASE = false;
2068   bool HasBMI = false;
2069   bool HasBMI2 = false;
2070   bool HasPOPCNT = false;
2071   bool HasRTM = false;
2072   bool HasPRFCHW = false;
2073   bool HasRDSEED = false;
2074   bool HasADX = false;
2075   bool HasTBM = false;
2076   bool HasFMA = false;
2077   bool HasF16C = false;
2078   bool HasAVX512CD = false;
2079   bool HasAVX512ER = false;
2080   bool HasAVX512PF = false;
2081   bool HasAVX512DQ = false;
2082   bool HasAVX512BW = false;
2083   bool HasAVX512VL = false;
2084   bool HasSHA = false;
2085   bool HasCX16 = false;
2086   bool HasFXSR = false;
2087   bool HasXSAVE = false;
2088   bool HasXSAVEOPT = false;
2089   bool HasXSAVEC = false;
2090   bool HasXSAVES = false;
2091 
2092   /// \brief Enumeration of all of the X86 CPUs supported by Clang.
2093   ///
2094   /// Each enumeration represents a particular CPU supported by Clang. These
2095   /// loosely correspond to the options passed to '-march' or '-mtune' flags.
2096   enum CPUKind {
2097     CK_Generic,
2098 
2099     /// \name i386
2100     /// i386-generation processors.
2101     //@{
2102     CK_i386,
2103     //@}
2104 
2105     /// \name i486
2106     /// i486-generation processors.
2107     //@{
2108     CK_i486,
2109     CK_WinChipC6,
2110     CK_WinChip2,
2111     CK_C3,
2112     //@}
2113 
2114     /// \name i586
2115     /// i586-generation processors, P5 microarchitecture based.
2116     //@{
2117     CK_i586,
2118     CK_Pentium,
2119     CK_PentiumMMX,
2120     //@}
2121 
2122     /// \name i686
2123     /// i686-generation processors, P6 / Pentium M microarchitecture based.
2124     //@{
2125     CK_i686,
2126     CK_PentiumPro,
2127     CK_Pentium2,
2128     CK_Pentium3,
2129     CK_Pentium3M,
2130     CK_PentiumM,
2131     CK_C3_2,
2132 
2133     /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
2134     /// Clang however has some logic to suport this.
2135     // FIXME: Warn, deprecate, and potentially remove this.
2136     CK_Yonah,
2137     //@}
2138 
2139     /// \name Netburst
2140     /// Netburst microarchitecture based processors.
2141     //@{
2142     CK_Pentium4,
2143     CK_Pentium4M,
2144     CK_Prescott,
2145     CK_Nocona,
2146     //@}
2147 
2148     /// \name Core
2149     /// Core microarchitecture based processors.
2150     //@{
2151     CK_Core2,
2152 
2153     /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
2154     /// codename which GCC no longer accepts as an option to -march, but Clang
2155     /// has some logic for recognizing it.
2156     // FIXME: Warn, deprecate, and potentially remove this.
2157     CK_Penryn,
2158     //@}
2159 
2160     /// \name Atom
2161     /// Atom processors
2162     //@{
2163     CK_Bonnell,
2164     CK_Silvermont,
2165     //@}
2166 
2167     /// \name Nehalem
2168     /// Nehalem microarchitecture based processors.
2169     CK_Nehalem,
2170 
2171     /// \name Westmere
2172     /// Westmere microarchitecture based processors.
2173     CK_Westmere,
2174 
2175     /// \name Sandy Bridge
2176     /// Sandy Bridge microarchitecture based processors.
2177     CK_SandyBridge,
2178 
2179     /// \name Ivy Bridge
2180     /// Ivy Bridge microarchitecture based processors.
2181     CK_IvyBridge,
2182 
2183     /// \name Haswell
2184     /// Haswell microarchitecture based processors.
2185     CK_Haswell,
2186 
2187     /// \name Broadwell
2188     /// Broadwell microarchitecture based processors.
2189     CK_Broadwell,
2190 
2191     /// \name Skylake
2192     /// Skylake microarchitecture based processors.
2193     CK_Skylake,
2194 
2195     /// \name Knights Landing
2196     /// Knights Landing processor.
2197     CK_KNL,
2198 
2199     /// \name K6
2200     /// K6 architecture processors.
2201     //@{
2202     CK_K6,
2203     CK_K6_2,
2204     CK_K6_3,
2205     //@}
2206 
2207     /// \name K7
2208     /// K7 architecture processors.
2209     //@{
2210     CK_Athlon,
2211     CK_AthlonThunderbird,
2212     CK_Athlon4,
2213     CK_AthlonXP,
2214     CK_AthlonMP,
2215     //@}
2216 
2217     /// \name K8
2218     /// K8 architecture processors.
2219     //@{
2220     CK_Athlon64,
2221     CK_Athlon64SSE3,
2222     CK_AthlonFX,
2223     CK_K8,
2224     CK_K8SSE3,
2225     CK_Opteron,
2226     CK_OpteronSSE3,
2227     CK_AMDFAM10,
2228     //@}
2229 
2230     /// \name Bobcat
2231     /// Bobcat architecture processors.
2232     //@{
2233     CK_BTVER1,
2234     CK_BTVER2,
2235     //@}
2236 
2237     /// \name Bulldozer
2238     /// Bulldozer architecture processors.
2239     //@{
2240     CK_BDVER1,
2241     CK_BDVER2,
2242     CK_BDVER3,
2243     CK_BDVER4,
2244     //@}
2245 
2246     /// This specification is deprecated and will be removed in the future.
2247     /// Users should prefer \see CK_K8.
2248     // FIXME: Warn on this when the CPU is set to it.
2249     //@{
2250     CK_x86_64,
2251     //@}
2252 
2253     /// \name Geode
2254     /// Geode processors.
2255     //@{
2256     CK_Geode
2257     //@}
2258   } CPU = CK_Generic;
2259 
2260   CPUKind getCPUKind(StringRef CPU) const {
2261     return llvm::StringSwitch<CPUKind>(CPU)
2262         .Case("i386", CK_i386)
2263         .Case("i486", CK_i486)
2264         .Case("winchip-c6", CK_WinChipC6)
2265         .Case("winchip2", CK_WinChip2)
2266         .Case("c3", CK_C3)
2267         .Case("i586", CK_i586)
2268         .Case("pentium", CK_Pentium)
2269         .Case("pentium-mmx", CK_PentiumMMX)
2270         .Case("i686", CK_i686)
2271         .Case("pentiumpro", CK_PentiumPro)
2272         .Case("pentium2", CK_Pentium2)
2273         .Case("pentium3", CK_Pentium3)
2274         .Case("pentium3m", CK_Pentium3M)
2275         .Case("pentium-m", CK_PentiumM)
2276         .Case("c3-2", CK_C3_2)
2277         .Case("yonah", CK_Yonah)
2278         .Case("pentium4", CK_Pentium4)
2279         .Case("pentium4m", CK_Pentium4M)
2280         .Case("prescott", CK_Prescott)
2281         .Case("nocona", CK_Nocona)
2282         .Case("core2", CK_Core2)
2283         .Case("penryn", CK_Penryn)
2284         .Case("bonnell", CK_Bonnell)
2285         .Case("atom", CK_Bonnell) // Legacy name.
2286         .Case("silvermont", CK_Silvermont)
2287         .Case("slm", CK_Silvermont) // Legacy name.
2288         .Case("nehalem", CK_Nehalem)
2289         .Case("corei7", CK_Nehalem) // Legacy name.
2290         .Case("westmere", CK_Westmere)
2291         .Case("sandybridge", CK_SandyBridge)
2292         .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2293         .Case("ivybridge", CK_IvyBridge)
2294         .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2295         .Case("haswell", CK_Haswell)
2296         .Case("core-avx2", CK_Haswell) // Legacy name.
2297         .Case("broadwell", CK_Broadwell)
2298         .Case("skylake", CK_Skylake)
2299         .Case("skx", CK_Skylake) // Legacy name.
2300         .Case("knl", CK_KNL)
2301         .Case("k6", CK_K6)
2302         .Case("k6-2", CK_K6_2)
2303         .Case("k6-3", CK_K6_3)
2304         .Case("athlon", CK_Athlon)
2305         .Case("athlon-tbird", CK_AthlonThunderbird)
2306         .Case("athlon-4", CK_Athlon4)
2307         .Case("athlon-xp", CK_AthlonXP)
2308         .Case("athlon-mp", CK_AthlonMP)
2309         .Case("athlon64", CK_Athlon64)
2310         .Case("athlon64-sse3", CK_Athlon64SSE3)
2311         .Case("athlon-fx", CK_AthlonFX)
2312         .Case("k8", CK_K8)
2313         .Case("k8-sse3", CK_K8SSE3)
2314         .Case("opteron", CK_Opteron)
2315         .Case("opteron-sse3", CK_OpteronSSE3)
2316         .Case("barcelona", CK_AMDFAM10)
2317         .Case("amdfam10", CK_AMDFAM10)
2318         .Case("btver1", CK_BTVER1)
2319         .Case("btver2", CK_BTVER2)
2320         .Case("bdver1", CK_BDVER1)
2321         .Case("bdver2", CK_BDVER2)
2322         .Case("bdver3", CK_BDVER3)
2323         .Case("bdver4", CK_BDVER4)
2324         .Case("x86-64", CK_x86_64)
2325         .Case("geode", CK_Geode)
2326         .Default(CK_Generic);
2327   }
2328 
2329   enum FPMathKind {
2330     FP_Default,
2331     FP_SSE,
2332     FP_387
2333   } FPMath = FP_Default;
2334 
2335 public:
2336   X86TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
2337     BigEndian = false;
2338     LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
2339   }
2340   unsigned getFloatEvalMethod() const override {
2341     // X87 evaluates with 80 bits "long double" precision.
2342     return SSELevel == NoSSE ? 2 : 0;
2343   }
2344   ArrayRef<Builtin::Info> getTargetBuiltins() const override {
2345     return llvm::makeArrayRef(BuiltinInfo,
2346                              clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin);
2347   }
2348   ArrayRef<const char *> getGCCRegNames() const override {
2349     return llvm::makeArrayRef(GCCRegNames);
2350   }
2351   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
2352     return None;
2353   }
2354   ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override {
2355     return llvm::makeArrayRef(AddlRegNames);
2356   }
2357   bool validateCpuSupports(StringRef Name) const override;
2358   bool validateAsmConstraint(const char *&Name,
2359                              TargetInfo::ConstraintInfo &info) const override;
2360 
2361   bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
2362 
2363   bool validateInputSize(StringRef Constraint, unsigned Size) const override;
2364 
2365   virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
2366 
2367   std::string convertConstraint(const char *&Constraint) const override;
2368   const char *getClobbers() const override {
2369     return "~{dirflag},~{fpsr},~{flags}";
2370   }
2371   void getTargetDefines(const LangOptions &Opts,
2372                         MacroBuilder &Builder) const override;
2373   static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
2374                           bool Enabled);
2375   static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
2376                           bool Enabled);
2377   static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2378                           bool Enabled);
2379   void setFeatureEnabled(llvm::StringMap<bool> &Features,
2380                          StringRef Name, bool Enabled) const override {
2381     setFeatureEnabledImpl(Features, Name, Enabled);
2382   }
2383   // This exists purely to cut down on the number of virtual calls in
2384   // initFeatureMap which calls this repeatedly.
2385   static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2386                                     StringRef Name, bool Enabled);
2387   bool
2388   initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
2389                  StringRef CPU,
2390                  const std::vector<std::string> &FeaturesVec) const override;
2391   bool hasFeature(StringRef Feature) const override;
2392   bool handleTargetFeatures(std::vector<std::string> &Features,
2393                             DiagnosticsEngine &Diags) override;
2394   StringRef getABI() const override {
2395     if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F)
2396       return "avx512";
2397     if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
2398       return "avx";
2399     if (getTriple().getArch() == llvm::Triple::x86 &&
2400              MMX3DNowLevel == NoMMX3DNow)
2401       return "no-mmx";
2402     return "";
2403   }
2404   bool setCPU(const std::string &Name) override {
2405     CPU = getCPUKind(Name);
2406 
2407     // Perform any per-CPU checks necessary to determine if this CPU is
2408     // acceptable.
2409     // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2410     // invalid without explaining *why*.
2411     switch (CPU) {
2412     case CK_Generic:
2413       // No processor selected!
2414       return false;
2415 
2416     case CK_i386:
2417     case CK_i486:
2418     case CK_WinChipC6:
2419     case CK_WinChip2:
2420     case CK_C3:
2421     case CK_i586:
2422     case CK_Pentium:
2423     case CK_PentiumMMX:
2424     case CK_i686:
2425     case CK_PentiumPro:
2426     case CK_Pentium2:
2427     case CK_Pentium3:
2428     case CK_Pentium3M:
2429     case CK_PentiumM:
2430     case CK_Yonah:
2431     case CK_C3_2:
2432     case CK_Pentium4:
2433     case CK_Pentium4M:
2434     case CK_Prescott:
2435     case CK_K6:
2436     case CK_K6_2:
2437     case CK_K6_3:
2438     case CK_Athlon:
2439     case CK_AthlonThunderbird:
2440     case CK_Athlon4:
2441     case CK_AthlonXP:
2442     case CK_AthlonMP:
2443     case CK_Geode:
2444       // Only accept certain architectures when compiling in 32-bit mode.
2445       if (getTriple().getArch() != llvm::Triple::x86)
2446         return false;
2447 
2448       // Fallthrough
2449     case CK_Nocona:
2450     case CK_Core2:
2451     case CK_Penryn:
2452     case CK_Bonnell:
2453     case CK_Silvermont:
2454     case CK_Nehalem:
2455     case CK_Westmere:
2456     case CK_SandyBridge:
2457     case CK_IvyBridge:
2458     case CK_Haswell:
2459     case CK_Broadwell:
2460     case CK_Skylake:
2461     case CK_KNL:
2462     case CK_Athlon64:
2463     case CK_Athlon64SSE3:
2464     case CK_AthlonFX:
2465     case CK_K8:
2466     case CK_K8SSE3:
2467     case CK_Opteron:
2468     case CK_OpteronSSE3:
2469     case CK_AMDFAM10:
2470     case CK_BTVER1:
2471     case CK_BTVER2:
2472     case CK_BDVER1:
2473     case CK_BDVER2:
2474     case CK_BDVER3:
2475     case CK_BDVER4:
2476     case CK_x86_64:
2477       return true;
2478     }
2479     llvm_unreachable("Unhandled CPU kind");
2480   }
2481 
2482   bool setFPMath(StringRef Name) override;
2483 
2484   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2485     // We accept all non-ARM calling conventions
2486     return (CC == CC_X86ThisCall ||
2487             CC == CC_X86FastCall ||
2488             CC == CC_X86StdCall ||
2489             CC == CC_X86VectorCall ||
2490             CC == CC_C ||
2491             CC == CC_X86Pascal ||
2492             CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2493   }
2494 
2495   CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2496     return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2497   }
2498 
2499   bool hasSjLjLowering() const override {
2500     return true;
2501   }
2502 };
2503 
2504 bool X86TargetInfo::setFPMath(StringRef Name) {
2505   if (Name == "387") {
2506     FPMath = FP_387;
2507     return true;
2508   }
2509   if (Name == "sse") {
2510     FPMath = FP_SSE;
2511     return true;
2512   }
2513   return false;
2514 }
2515 
2516 bool X86TargetInfo::initFeatureMap(
2517     llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
2518     const std::vector<std::string> &FeaturesVec) const {
2519   // FIXME: This *really* should not be here.
2520   // X86_64 always has SSE2.
2521   if (getTriple().getArch() == llvm::Triple::x86_64)
2522     setFeatureEnabledImpl(Features, "sse2", true);
2523 
2524   switch (getCPUKind(CPU)) {
2525   case CK_Generic:
2526   case CK_i386:
2527   case CK_i486:
2528   case CK_i586:
2529   case CK_Pentium:
2530   case CK_i686:
2531   case CK_PentiumPro:
2532     break;
2533   case CK_PentiumMMX:
2534   case CK_Pentium2:
2535   case CK_K6:
2536   case CK_WinChipC6:
2537     setFeatureEnabledImpl(Features, "mmx", true);
2538     break;
2539   case CK_Pentium3:
2540   case CK_Pentium3M:
2541   case CK_C3_2:
2542     setFeatureEnabledImpl(Features, "sse", true);
2543     setFeatureEnabledImpl(Features, "fxsr", true);
2544     break;
2545   case CK_PentiumM:
2546   case CK_Pentium4:
2547   case CK_Pentium4M:
2548   case CK_x86_64:
2549     setFeatureEnabledImpl(Features, "sse2", true);
2550     setFeatureEnabledImpl(Features, "fxsr", true);
2551     break;
2552   case CK_Yonah:
2553   case CK_Prescott:
2554   case CK_Nocona:
2555     setFeatureEnabledImpl(Features, "sse3", true);
2556     setFeatureEnabledImpl(Features, "fxsr", true);
2557     setFeatureEnabledImpl(Features, "cx16", true);
2558     break;
2559   case CK_Core2:
2560   case CK_Bonnell:
2561     setFeatureEnabledImpl(Features, "ssse3", true);
2562     setFeatureEnabledImpl(Features, "fxsr", true);
2563     setFeatureEnabledImpl(Features, "cx16", true);
2564     break;
2565   case CK_Penryn:
2566     setFeatureEnabledImpl(Features, "sse4.1", true);
2567     setFeatureEnabledImpl(Features, "fxsr", true);
2568     setFeatureEnabledImpl(Features, "cx16", true);
2569     break;
2570   case CK_Skylake:
2571     setFeatureEnabledImpl(Features, "avx512f", true);
2572     setFeatureEnabledImpl(Features, "avx512cd", true);
2573     setFeatureEnabledImpl(Features, "avx512dq", true);
2574     setFeatureEnabledImpl(Features, "avx512bw", true);
2575     setFeatureEnabledImpl(Features, "avx512vl", true);
2576     setFeatureEnabledImpl(Features, "xsavec", true);
2577     setFeatureEnabledImpl(Features, "xsaves", true);
2578     // FALLTHROUGH
2579   case CK_Broadwell:
2580     setFeatureEnabledImpl(Features, "rdseed", true);
2581     setFeatureEnabledImpl(Features, "adx", true);
2582     // FALLTHROUGH
2583   case CK_Haswell:
2584     setFeatureEnabledImpl(Features, "avx2", true);
2585     setFeatureEnabledImpl(Features, "lzcnt", true);
2586     setFeatureEnabledImpl(Features, "bmi", true);
2587     setFeatureEnabledImpl(Features, "bmi2", true);
2588     setFeatureEnabledImpl(Features, "rtm", true);
2589     setFeatureEnabledImpl(Features, "fma", true);
2590     // FALLTHROUGH
2591   case CK_IvyBridge:
2592     setFeatureEnabledImpl(Features, "rdrnd", true);
2593     setFeatureEnabledImpl(Features, "f16c", true);
2594     setFeatureEnabledImpl(Features, "fsgsbase", true);
2595     // FALLTHROUGH
2596   case CK_SandyBridge:
2597     setFeatureEnabledImpl(Features, "avx", true);
2598     setFeatureEnabledImpl(Features, "xsave", true);
2599     setFeatureEnabledImpl(Features, "xsaveopt", true);
2600     // FALLTHROUGH
2601   case CK_Westmere:
2602   case CK_Silvermont:
2603     setFeatureEnabledImpl(Features, "aes", true);
2604     setFeatureEnabledImpl(Features, "pclmul", true);
2605     // FALLTHROUGH
2606   case CK_Nehalem:
2607     setFeatureEnabledImpl(Features, "sse4.2", true);
2608     setFeatureEnabledImpl(Features, "fxsr", true);
2609     setFeatureEnabledImpl(Features, "cx16", true);
2610     break;
2611   case CK_KNL:
2612     setFeatureEnabledImpl(Features, "avx512f", true);
2613     setFeatureEnabledImpl(Features, "avx512cd", true);
2614     setFeatureEnabledImpl(Features, "avx512er", true);
2615     setFeatureEnabledImpl(Features, "avx512pf", true);
2616     setFeatureEnabledImpl(Features, "fxsr", true);
2617     setFeatureEnabledImpl(Features, "rdseed", true);
2618     setFeatureEnabledImpl(Features, "adx", true);
2619     setFeatureEnabledImpl(Features, "lzcnt", true);
2620     setFeatureEnabledImpl(Features, "bmi", true);
2621     setFeatureEnabledImpl(Features, "bmi2", true);
2622     setFeatureEnabledImpl(Features, "rtm", true);
2623     setFeatureEnabledImpl(Features, "fma", true);
2624     setFeatureEnabledImpl(Features, "rdrnd", true);
2625     setFeatureEnabledImpl(Features, "f16c", true);
2626     setFeatureEnabledImpl(Features, "fsgsbase", true);
2627     setFeatureEnabledImpl(Features, "aes", true);
2628     setFeatureEnabledImpl(Features, "pclmul", true);
2629     setFeatureEnabledImpl(Features, "cx16", true);
2630     setFeatureEnabledImpl(Features, "xsaveopt", true);
2631     setFeatureEnabledImpl(Features, "xsave", true);
2632     break;
2633   case CK_K6_2:
2634   case CK_K6_3:
2635   case CK_WinChip2:
2636   case CK_C3:
2637     setFeatureEnabledImpl(Features, "3dnow", true);
2638     break;
2639   case CK_Athlon:
2640   case CK_AthlonThunderbird:
2641   case CK_Geode:
2642     setFeatureEnabledImpl(Features, "3dnowa", true);
2643     break;
2644   case CK_Athlon4:
2645   case CK_AthlonXP:
2646   case CK_AthlonMP:
2647     setFeatureEnabledImpl(Features, "sse", true);
2648     setFeatureEnabledImpl(Features, "3dnowa", true);
2649     setFeatureEnabledImpl(Features, "fxsr", true);
2650     break;
2651   case CK_K8:
2652   case CK_Opteron:
2653   case CK_Athlon64:
2654   case CK_AthlonFX:
2655     setFeatureEnabledImpl(Features, "sse2", true);
2656     setFeatureEnabledImpl(Features, "3dnowa", true);
2657     setFeatureEnabledImpl(Features, "fxsr", true);
2658     break;
2659   case CK_AMDFAM10:
2660     setFeatureEnabledImpl(Features, "sse4a", true);
2661     setFeatureEnabledImpl(Features, "lzcnt", true);
2662     setFeatureEnabledImpl(Features, "popcnt", true);
2663     // FALLTHROUGH
2664   case CK_K8SSE3:
2665   case CK_OpteronSSE3:
2666   case CK_Athlon64SSE3:
2667     setFeatureEnabledImpl(Features, "sse3", true);
2668     setFeatureEnabledImpl(Features, "3dnowa", true);
2669     setFeatureEnabledImpl(Features, "fxsr", true);
2670     break;
2671   case CK_BTVER2:
2672     setFeatureEnabledImpl(Features, "avx", true);
2673     setFeatureEnabledImpl(Features, "aes", true);
2674     setFeatureEnabledImpl(Features, "pclmul", true);
2675     setFeatureEnabledImpl(Features, "bmi", true);
2676     setFeatureEnabledImpl(Features, "f16c", true);
2677     setFeatureEnabledImpl(Features, "xsaveopt", true);
2678     // FALLTHROUGH
2679   case CK_BTVER1:
2680     setFeatureEnabledImpl(Features, "ssse3", true);
2681     setFeatureEnabledImpl(Features, "sse4a", true);
2682     setFeatureEnabledImpl(Features, "lzcnt", true);
2683     setFeatureEnabledImpl(Features, "popcnt", true);
2684     setFeatureEnabledImpl(Features, "prfchw", true);
2685     setFeatureEnabledImpl(Features, "cx16", true);
2686     setFeatureEnabledImpl(Features, "fxsr", true);
2687     setFeatureEnabledImpl(Features, "xsave", true);
2688     break;
2689   case CK_BDVER4:
2690     setFeatureEnabledImpl(Features, "avx2", true);
2691     setFeatureEnabledImpl(Features, "bmi2", true);
2692     // FALLTHROUGH
2693   case CK_BDVER3:
2694     setFeatureEnabledImpl(Features, "fsgsbase", true);
2695     setFeatureEnabledImpl(Features, "xsaveopt", true);
2696     // FALLTHROUGH
2697   case CK_BDVER2:
2698     setFeatureEnabledImpl(Features, "bmi", true);
2699     setFeatureEnabledImpl(Features, "fma", true);
2700     setFeatureEnabledImpl(Features, "f16c", true);
2701     setFeatureEnabledImpl(Features, "tbm", true);
2702     // FALLTHROUGH
2703   case CK_BDVER1:
2704     // xop implies avx, sse4a and fma4.
2705     setFeatureEnabledImpl(Features, "xop", true);
2706     setFeatureEnabledImpl(Features, "lzcnt", true);
2707     setFeatureEnabledImpl(Features, "aes", true);
2708     setFeatureEnabledImpl(Features, "pclmul", true);
2709     setFeatureEnabledImpl(Features, "prfchw", true);
2710     setFeatureEnabledImpl(Features, "cx16", true);
2711     setFeatureEnabledImpl(Features, "fxsr", true);
2712     setFeatureEnabledImpl(Features, "xsave", true);
2713     break;
2714   }
2715   if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec))
2716     return false;
2717 
2718   // Can't do this earlier because we need to be able to explicitly enable
2719   // or disable these features and the things that they depend upon.
2720 
2721   // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2722   auto I = Features.find("sse4.2");
2723   if (I != Features.end() && I->getValue() &&
2724       std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") ==
2725           FeaturesVec.end())
2726     Features["popcnt"] = true;
2727 
2728   // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
2729   I = Features.find("3dnow");
2730   if (I != Features.end() && I->getValue() &&
2731       std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") ==
2732           FeaturesVec.end())
2733     Features["prfchw"] = true;
2734 
2735   // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2736   // then enable MMX.
2737   I = Features.find("sse");
2738   if (I != Features.end() && I->getValue() &&
2739       std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") ==
2740           FeaturesVec.end())
2741     Features["mmx"] = true;
2742 
2743   return true;
2744 }
2745 
2746 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2747                                 X86SSEEnum Level, bool Enabled) {
2748   if (Enabled) {
2749     switch (Level) {
2750     case AVX512F:
2751       Features["avx512f"] = true;
2752     case AVX2:
2753       Features["avx2"] = true;
2754     case AVX:
2755       Features["avx"] = true;
2756       Features["xsave"] = true;
2757     case SSE42:
2758       Features["sse4.2"] = true;
2759     case SSE41:
2760       Features["sse4.1"] = true;
2761     case SSSE3:
2762       Features["ssse3"] = true;
2763     case SSE3:
2764       Features["sse3"] = true;
2765     case SSE2:
2766       Features["sse2"] = true;
2767     case SSE1:
2768       Features["sse"] = true;
2769     case NoSSE:
2770       break;
2771     }
2772     return;
2773   }
2774 
2775   switch (Level) {
2776   case NoSSE:
2777   case SSE1:
2778     Features["sse"] = false;
2779   case SSE2:
2780     Features["sse2"] = Features["pclmul"] = Features["aes"] =
2781       Features["sha"] = false;
2782   case SSE3:
2783     Features["sse3"] = false;
2784     setXOPLevel(Features, NoXOP, false);
2785   case SSSE3:
2786     Features["ssse3"] = false;
2787   case SSE41:
2788     Features["sse4.1"] = false;
2789   case SSE42:
2790     Features["sse4.2"] = false;
2791   case AVX:
2792     Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] =
2793       Features["xsaveopt"] = false;
2794     setXOPLevel(Features, FMA4, false);
2795   case AVX2:
2796     Features["avx2"] = false;
2797   case AVX512F:
2798     Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
2799       Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
2800       Features["avx512vl"] = false;
2801   }
2802 }
2803 
2804 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2805                                 MMX3DNowEnum Level, bool Enabled) {
2806   if (Enabled) {
2807     switch (Level) {
2808     case AMD3DNowAthlon:
2809       Features["3dnowa"] = true;
2810     case AMD3DNow:
2811       Features["3dnow"] = true;
2812     case MMX:
2813       Features["mmx"] = true;
2814     case NoMMX3DNow:
2815       break;
2816     }
2817     return;
2818   }
2819 
2820   switch (Level) {
2821   case NoMMX3DNow:
2822   case MMX:
2823     Features["mmx"] = false;
2824   case AMD3DNow:
2825     Features["3dnow"] = false;
2826   case AMD3DNowAthlon:
2827     Features["3dnowa"] = false;
2828   }
2829 }
2830 
2831 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2832                                 bool Enabled) {
2833   if (Enabled) {
2834     switch (Level) {
2835     case XOP:
2836       Features["xop"] = true;
2837     case FMA4:
2838       Features["fma4"] = true;
2839       setSSELevel(Features, AVX, true);
2840     case SSE4A:
2841       Features["sse4a"] = true;
2842       setSSELevel(Features, SSE3, true);
2843     case NoXOP:
2844       break;
2845     }
2846     return;
2847   }
2848 
2849   switch (Level) {
2850   case NoXOP:
2851   case SSE4A:
2852     Features["sse4a"] = false;
2853   case FMA4:
2854     Features["fma4"] = false;
2855   case XOP:
2856     Features["xop"] = false;
2857   }
2858 }
2859 
2860 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2861                                           StringRef Name, bool Enabled) {
2862   // This is a bit of a hack to deal with the sse4 target feature when used
2863   // as part of the target attribute. We handle sse4 correctly everywhere
2864   // else. See below for more information on how we handle the sse4 options.
2865   if (Name != "sse4")
2866     Features[Name] = Enabled;
2867 
2868   if (Name == "mmx") {
2869     setMMXLevel(Features, MMX, Enabled);
2870   } else if (Name == "sse") {
2871     setSSELevel(Features, SSE1, Enabled);
2872   } else if (Name == "sse2") {
2873     setSSELevel(Features, SSE2, Enabled);
2874   } else if (Name == "sse3") {
2875     setSSELevel(Features, SSE3, Enabled);
2876   } else if (Name == "ssse3") {
2877     setSSELevel(Features, SSSE3, Enabled);
2878   } else if (Name == "sse4.2") {
2879     setSSELevel(Features, SSE42, Enabled);
2880   } else if (Name == "sse4.1") {
2881     setSSELevel(Features, SSE41, Enabled);
2882   } else if (Name == "3dnow") {
2883     setMMXLevel(Features, AMD3DNow, Enabled);
2884   } else if (Name == "3dnowa") {
2885     setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2886   } else if (Name == "aes") {
2887     if (Enabled)
2888       setSSELevel(Features, SSE2, Enabled);
2889   } else if (Name == "pclmul") {
2890     if (Enabled)
2891       setSSELevel(Features, SSE2, Enabled);
2892   } else if (Name == "avx") {
2893     setSSELevel(Features, AVX, Enabled);
2894   } else if (Name == "avx2") {
2895     setSSELevel(Features, AVX2, Enabled);
2896   } else if (Name == "avx512f") {
2897     setSSELevel(Features, AVX512F, Enabled);
2898   } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf"
2899           || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") {
2900     if (Enabled)
2901       setSSELevel(Features, AVX512F, Enabled);
2902   } else if (Name == "fma") {
2903     if (Enabled)
2904       setSSELevel(Features, AVX, Enabled);
2905   } else if (Name == "fma4") {
2906     setXOPLevel(Features, FMA4, Enabled);
2907   } else if (Name == "xop") {
2908     setXOPLevel(Features, XOP, Enabled);
2909   } else if (Name == "sse4a") {
2910     setXOPLevel(Features, SSE4A, Enabled);
2911   } else if (Name == "f16c") {
2912     if (Enabled)
2913       setSSELevel(Features, AVX, Enabled);
2914   } else if (Name == "sha") {
2915     if (Enabled)
2916       setSSELevel(Features, SSE2, Enabled);
2917   } else if (Name == "sse4") {
2918     // We can get here via the __target__ attribute since that's not controlled
2919     // via the -msse4/-mno-sse4 command line alias. Handle this the same way
2920     // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
2921     // disabled.
2922     if (Enabled)
2923       setSSELevel(Features, SSE42, Enabled);
2924     else
2925       setSSELevel(Features, SSE41, Enabled);
2926   } else if (Name == "xsave") {
2927     if (Enabled)
2928       setSSELevel(Features, AVX, Enabled);
2929     else
2930       Features["xsaveopt"] = false;
2931   } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") {
2932     if (Enabled) {
2933       Features["xsave"] = true;
2934       setSSELevel(Features, AVX, Enabled);
2935     }
2936   }
2937 }
2938 
2939 /// handleTargetFeatures - Perform initialization based on the user
2940 /// configured set of features.
2941 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2942                                          DiagnosticsEngine &Diags) {
2943   for (const auto &Feature : Features) {
2944     if (Feature[0] != '+')
2945       continue;
2946 
2947     if (Feature == "+aes") {
2948       HasAES = true;
2949     } else if (Feature == "+pclmul") {
2950       HasPCLMUL = true;
2951     } else if (Feature == "+lzcnt") {
2952       HasLZCNT = true;
2953     } else if (Feature == "+rdrnd") {
2954       HasRDRND = true;
2955     } else if (Feature == "+fsgsbase") {
2956       HasFSGSBASE = true;
2957     } else if (Feature == "+bmi") {
2958       HasBMI = true;
2959     } else if (Feature == "+bmi2") {
2960       HasBMI2 = true;
2961     } else if (Feature == "+popcnt") {
2962       HasPOPCNT = true;
2963     } else if (Feature == "+rtm") {
2964       HasRTM = true;
2965     } else if (Feature == "+prfchw") {
2966       HasPRFCHW = true;
2967     } else if (Feature == "+rdseed") {
2968       HasRDSEED = true;
2969     } else if (Feature == "+adx") {
2970       HasADX = true;
2971     } else if (Feature == "+tbm") {
2972       HasTBM = true;
2973     } else if (Feature == "+fma") {
2974       HasFMA = true;
2975     } else if (Feature == "+f16c") {
2976       HasF16C = true;
2977     } else if (Feature == "+avx512cd") {
2978       HasAVX512CD = true;
2979     } else if (Feature == "+avx512er") {
2980       HasAVX512ER = true;
2981     } else if (Feature == "+avx512pf") {
2982       HasAVX512PF = true;
2983     } else if (Feature == "+avx512dq") {
2984       HasAVX512DQ = true;
2985     } else if (Feature == "+avx512bw") {
2986       HasAVX512BW = true;
2987     } else if (Feature == "+avx512vl") {
2988       HasAVX512VL = true;
2989     } else if (Feature == "+sha") {
2990       HasSHA = true;
2991     } else if (Feature == "+cx16") {
2992       HasCX16 = true;
2993     } else if (Feature == "+fxsr") {
2994       HasFXSR = true;
2995     } else if (Feature == "+xsave") {
2996       HasXSAVE = true;
2997     } else if (Feature == "+xsaveopt") {
2998       HasXSAVEOPT = true;
2999     } else if (Feature == "+xsavec") {
3000       HasXSAVEC = true;
3001     } else if (Feature == "+xsaves") {
3002       HasXSAVES = true;
3003     }
3004 
3005     X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
3006       .Case("+avx512f", AVX512F)
3007       .Case("+avx2", AVX2)
3008       .Case("+avx", AVX)
3009       .Case("+sse4.2", SSE42)
3010       .Case("+sse4.1", SSE41)
3011       .Case("+ssse3", SSSE3)
3012       .Case("+sse3", SSE3)
3013       .Case("+sse2", SSE2)
3014       .Case("+sse", SSE1)
3015       .Default(NoSSE);
3016     SSELevel = std::max(SSELevel, Level);
3017 
3018     MMX3DNowEnum ThreeDNowLevel =
3019       llvm::StringSwitch<MMX3DNowEnum>(Feature)
3020         .Case("+3dnowa", AMD3DNowAthlon)
3021         .Case("+3dnow", AMD3DNow)
3022         .Case("+mmx", MMX)
3023         .Default(NoMMX3DNow);
3024     MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
3025 
3026     XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
3027         .Case("+xop", XOP)
3028         .Case("+fma4", FMA4)
3029         .Case("+sse4a", SSE4A)
3030         .Default(NoXOP);
3031     XOPLevel = std::max(XOPLevel, XLevel);
3032   }
3033 
3034   // LLVM doesn't have a separate switch for fpmath, so only accept it if it
3035   // matches the selected sse level.
3036   if ((FPMath == FP_SSE && SSELevel < SSE1) ||
3037       (FPMath == FP_387 && SSELevel >= SSE1)) {
3038     Diags.Report(diag::err_target_unsupported_fpmath) <<
3039       (FPMath == FP_SSE ? "sse" : "387");
3040     return false;
3041   }
3042 
3043   SimdDefaultAlign =
3044       hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
3045   return true;
3046 }
3047 
3048 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
3049 /// definitions for this particular subtarget.
3050 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
3051                                      MacroBuilder &Builder) const {
3052   // Target identification.
3053   if (getTriple().getArch() == llvm::Triple::x86_64) {
3054     Builder.defineMacro("__amd64__");
3055     Builder.defineMacro("__amd64");
3056     Builder.defineMacro("__x86_64");
3057     Builder.defineMacro("__x86_64__");
3058     if (getTriple().getArchName() == "x86_64h") {
3059       Builder.defineMacro("__x86_64h");
3060       Builder.defineMacro("__x86_64h__");
3061     }
3062   } else {
3063     DefineStd(Builder, "i386", Opts);
3064   }
3065 
3066   // Subtarget options.
3067   // FIXME: We are hard-coding the tune parameters based on the CPU, but they
3068   // truly should be based on -mtune options.
3069   switch (CPU) {
3070   case CK_Generic:
3071     break;
3072   case CK_i386:
3073     // The rest are coming from the i386 define above.
3074     Builder.defineMacro("__tune_i386__");
3075     break;
3076   case CK_i486:
3077   case CK_WinChipC6:
3078   case CK_WinChip2:
3079   case CK_C3:
3080     defineCPUMacros(Builder, "i486");
3081     break;
3082   case CK_PentiumMMX:
3083     Builder.defineMacro("__pentium_mmx__");
3084     Builder.defineMacro("__tune_pentium_mmx__");
3085     // Fallthrough
3086   case CK_i586:
3087   case CK_Pentium:
3088     defineCPUMacros(Builder, "i586");
3089     defineCPUMacros(Builder, "pentium");
3090     break;
3091   case CK_Pentium3:
3092   case CK_Pentium3M:
3093   case CK_PentiumM:
3094     Builder.defineMacro("__tune_pentium3__");
3095     // Fallthrough
3096   case CK_Pentium2:
3097   case CK_C3_2:
3098     Builder.defineMacro("__tune_pentium2__");
3099     // Fallthrough
3100   case CK_PentiumPro:
3101     Builder.defineMacro("__tune_i686__");
3102     Builder.defineMacro("__tune_pentiumpro__");
3103     // Fallthrough
3104   case CK_i686:
3105     Builder.defineMacro("__i686");
3106     Builder.defineMacro("__i686__");
3107     // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
3108     Builder.defineMacro("__pentiumpro");
3109     Builder.defineMacro("__pentiumpro__");
3110     break;
3111   case CK_Pentium4:
3112   case CK_Pentium4M:
3113     defineCPUMacros(Builder, "pentium4");
3114     break;
3115   case CK_Yonah:
3116   case CK_Prescott:
3117   case CK_Nocona:
3118     defineCPUMacros(Builder, "nocona");
3119     break;
3120   case CK_Core2:
3121   case CK_Penryn:
3122     defineCPUMacros(Builder, "core2");
3123     break;
3124   case CK_Bonnell:
3125     defineCPUMacros(Builder, "atom");
3126     break;
3127   case CK_Silvermont:
3128     defineCPUMacros(Builder, "slm");
3129     break;
3130   case CK_Nehalem:
3131   case CK_Westmere:
3132   case CK_SandyBridge:
3133   case CK_IvyBridge:
3134   case CK_Haswell:
3135   case CK_Broadwell:
3136     // FIXME: Historically, we defined this legacy name, it would be nice to
3137     // remove it at some point. We've never exposed fine-grained names for
3138     // recent primary x86 CPUs, and we should keep it that way.
3139     defineCPUMacros(Builder, "corei7");
3140     break;
3141   case CK_Skylake:
3142     // FIXME: Historically, we defined this legacy name, it would be nice to
3143     // remove it at some point. This is the only fine-grained CPU macro in the
3144     // main intel CPU line, and it would be better to not have these and force
3145     // people to use ISA macros.
3146     defineCPUMacros(Builder, "skx");
3147     break;
3148   case CK_KNL:
3149     defineCPUMacros(Builder, "knl");
3150     break;
3151   case CK_K6_2:
3152     Builder.defineMacro("__k6_2__");
3153     Builder.defineMacro("__tune_k6_2__");
3154     // Fallthrough
3155   case CK_K6_3:
3156     if (CPU != CK_K6_2) {  // In case of fallthrough
3157       // FIXME: GCC may be enabling these in cases where some other k6
3158       // architecture is specified but -m3dnow is explicitly provided. The
3159       // exact semantics need to be determined and emulated here.
3160       Builder.defineMacro("__k6_3__");
3161       Builder.defineMacro("__tune_k6_3__");
3162     }
3163     // Fallthrough
3164   case CK_K6:
3165     defineCPUMacros(Builder, "k6");
3166     break;
3167   case CK_Athlon:
3168   case CK_AthlonThunderbird:
3169   case CK_Athlon4:
3170   case CK_AthlonXP:
3171   case CK_AthlonMP:
3172     defineCPUMacros(Builder, "athlon");
3173     if (SSELevel != NoSSE) {
3174       Builder.defineMacro("__athlon_sse__");
3175       Builder.defineMacro("__tune_athlon_sse__");
3176     }
3177     break;
3178   case CK_K8:
3179   case CK_K8SSE3:
3180   case CK_x86_64:
3181   case CK_Opteron:
3182   case CK_OpteronSSE3:
3183   case CK_Athlon64:
3184   case CK_Athlon64SSE3:
3185   case CK_AthlonFX:
3186     defineCPUMacros(Builder, "k8");
3187     break;
3188   case CK_AMDFAM10:
3189     defineCPUMacros(Builder, "amdfam10");
3190     break;
3191   case CK_BTVER1:
3192     defineCPUMacros(Builder, "btver1");
3193     break;
3194   case CK_BTVER2:
3195     defineCPUMacros(Builder, "btver2");
3196     break;
3197   case CK_BDVER1:
3198     defineCPUMacros(Builder, "bdver1");
3199     break;
3200   case CK_BDVER2:
3201     defineCPUMacros(Builder, "bdver2");
3202     break;
3203   case CK_BDVER3:
3204     defineCPUMacros(Builder, "bdver3");
3205     break;
3206   case CK_BDVER4:
3207     defineCPUMacros(Builder, "bdver4");
3208     break;
3209   case CK_Geode:
3210     defineCPUMacros(Builder, "geode");
3211     break;
3212   }
3213 
3214   // Target properties.
3215   Builder.defineMacro("__REGISTER_PREFIX__", "");
3216 
3217   // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
3218   // functions in glibc header files that use FP Stack inline asm which the
3219   // backend can't deal with (PR879).
3220   Builder.defineMacro("__NO_MATH_INLINES");
3221 
3222   if (HasAES)
3223     Builder.defineMacro("__AES__");
3224 
3225   if (HasPCLMUL)
3226     Builder.defineMacro("__PCLMUL__");
3227 
3228   if (HasLZCNT)
3229     Builder.defineMacro("__LZCNT__");
3230 
3231   if (HasRDRND)
3232     Builder.defineMacro("__RDRND__");
3233 
3234   if (HasFSGSBASE)
3235     Builder.defineMacro("__FSGSBASE__");
3236 
3237   if (HasBMI)
3238     Builder.defineMacro("__BMI__");
3239 
3240   if (HasBMI2)
3241     Builder.defineMacro("__BMI2__");
3242 
3243   if (HasPOPCNT)
3244     Builder.defineMacro("__POPCNT__");
3245 
3246   if (HasRTM)
3247     Builder.defineMacro("__RTM__");
3248 
3249   if (HasPRFCHW)
3250     Builder.defineMacro("__PRFCHW__");
3251 
3252   if (HasRDSEED)
3253     Builder.defineMacro("__RDSEED__");
3254 
3255   if (HasADX)
3256     Builder.defineMacro("__ADX__");
3257 
3258   if (HasTBM)
3259     Builder.defineMacro("__TBM__");
3260 
3261   switch (XOPLevel) {
3262   case XOP:
3263     Builder.defineMacro("__XOP__");
3264   case FMA4:
3265     Builder.defineMacro("__FMA4__");
3266   case SSE4A:
3267     Builder.defineMacro("__SSE4A__");
3268   case NoXOP:
3269     break;
3270   }
3271 
3272   if (HasFMA)
3273     Builder.defineMacro("__FMA__");
3274 
3275   if (HasF16C)
3276     Builder.defineMacro("__F16C__");
3277 
3278   if (HasAVX512CD)
3279     Builder.defineMacro("__AVX512CD__");
3280   if (HasAVX512ER)
3281     Builder.defineMacro("__AVX512ER__");
3282   if (HasAVX512PF)
3283     Builder.defineMacro("__AVX512PF__");
3284   if (HasAVX512DQ)
3285     Builder.defineMacro("__AVX512DQ__");
3286   if (HasAVX512BW)
3287     Builder.defineMacro("__AVX512BW__");
3288   if (HasAVX512VL)
3289     Builder.defineMacro("__AVX512VL__");
3290 
3291   if (HasSHA)
3292     Builder.defineMacro("__SHA__");
3293 
3294   if (HasFXSR)
3295     Builder.defineMacro("__FXSR__");
3296   if (HasXSAVE)
3297     Builder.defineMacro("__XSAVE__");
3298   if (HasXSAVEOPT)
3299     Builder.defineMacro("__XSAVEOPT__");
3300   if (HasXSAVEC)
3301     Builder.defineMacro("__XSAVEC__");
3302   if (HasXSAVES)
3303     Builder.defineMacro("__XSAVES__");
3304 
3305   if (HasCX16)
3306     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
3307 
3308   // Each case falls through to the previous one here.
3309   switch (SSELevel) {
3310   case AVX512F:
3311     Builder.defineMacro("__AVX512F__");
3312   case AVX2:
3313     Builder.defineMacro("__AVX2__");
3314   case AVX:
3315     Builder.defineMacro("__AVX__");
3316   case SSE42:
3317     Builder.defineMacro("__SSE4_2__");
3318   case SSE41:
3319     Builder.defineMacro("__SSE4_1__");
3320   case SSSE3:
3321     Builder.defineMacro("__SSSE3__");
3322   case SSE3:
3323     Builder.defineMacro("__SSE3__");
3324   case SSE2:
3325     Builder.defineMacro("__SSE2__");
3326     Builder.defineMacro("__SSE2_MATH__");  // -mfp-math=sse always implied.
3327   case SSE1:
3328     Builder.defineMacro("__SSE__");
3329     Builder.defineMacro("__SSE_MATH__");   // -mfp-math=sse always implied.
3330   case NoSSE:
3331     break;
3332   }
3333 
3334   if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
3335     switch (SSELevel) {
3336     case AVX512F:
3337     case AVX2:
3338     case AVX:
3339     case SSE42:
3340     case SSE41:
3341     case SSSE3:
3342     case SSE3:
3343     case SSE2:
3344       Builder.defineMacro("_M_IX86_FP", Twine(2));
3345       break;
3346     case SSE1:
3347       Builder.defineMacro("_M_IX86_FP", Twine(1));
3348       break;
3349     default:
3350       Builder.defineMacro("_M_IX86_FP", Twine(0));
3351     }
3352   }
3353 
3354   // Each case falls through to the previous one here.
3355   switch (MMX3DNowLevel) {
3356   case AMD3DNowAthlon:
3357     Builder.defineMacro("__3dNOW_A__");
3358   case AMD3DNow:
3359     Builder.defineMacro("__3dNOW__");
3360   case MMX:
3361     Builder.defineMacro("__MMX__");
3362   case NoMMX3DNow:
3363     break;
3364   }
3365 
3366   if (CPU >= CK_i486) {
3367     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3368     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3369     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3370   }
3371   if (CPU >= CK_i586)
3372     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3373 
3374   if (getTriple().isOSIAMCU()) {
3375     Builder.defineMacro("__iamcu");
3376     Builder.defineMacro("__iamcu__");
3377   }
3378 }
3379 
3380 bool X86TargetInfo::hasFeature(StringRef Feature) const {
3381   return llvm::StringSwitch<bool>(Feature)
3382       .Case("aes", HasAES)
3383       .Case("avx", SSELevel >= AVX)
3384       .Case("avx2", SSELevel >= AVX2)
3385       .Case("avx512f", SSELevel >= AVX512F)
3386       .Case("avx512cd", HasAVX512CD)
3387       .Case("avx512er", HasAVX512ER)
3388       .Case("avx512pf", HasAVX512PF)
3389       .Case("avx512dq", HasAVX512DQ)
3390       .Case("avx512bw", HasAVX512BW)
3391       .Case("avx512vl", HasAVX512VL)
3392       .Case("bmi", HasBMI)
3393       .Case("bmi2", HasBMI2)
3394       .Case("cx16", HasCX16)
3395       .Case("f16c", HasF16C)
3396       .Case("fma", HasFMA)
3397       .Case("fma4", XOPLevel >= FMA4)
3398       .Case("fsgsbase", HasFSGSBASE)
3399       .Case("fxsr", HasFXSR)
3400       .Case("lzcnt", HasLZCNT)
3401       .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3402       .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3403       .Case("mmx", MMX3DNowLevel >= MMX)
3404       .Case("pclmul", HasPCLMUL)
3405       .Case("popcnt", HasPOPCNT)
3406       .Case("prfchw", HasPRFCHW)
3407       .Case("rdrnd", HasRDRND)
3408       .Case("rdseed", HasRDSEED)
3409       .Case("rtm", HasRTM)
3410       .Case("sha", HasSHA)
3411       .Case("sse", SSELevel >= SSE1)
3412       .Case("sse2", SSELevel >= SSE2)
3413       .Case("sse3", SSELevel >= SSE3)
3414       .Case("ssse3", SSELevel >= SSSE3)
3415       .Case("sse4.1", SSELevel >= SSE41)
3416       .Case("sse4.2", SSELevel >= SSE42)
3417       .Case("sse4a", XOPLevel >= SSE4A)
3418       .Case("tbm", HasTBM)
3419       .Case("x86", true)
3420       .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
3421       .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
3422       .Case("xop", XOPLevel >= XOP)
3423       .Case("xsave", HasXSAVE)
3424       .Case("xsavec", HasXSAVEC)
3425       .Case("xsaves", HasXSAVES)
3426       .Case("xsaveopt", HasXSAVEOPT)
3427       .Default(false);
3428 }
3429 
3430 // We can't use a generic validation scheme for the features accepted here
3431 // versus subtarget features accepted in the target attribute because the
3432 // bitfield structure that's initialized in the runtime only supports the
3433 // below currently rather than the full range of subtarget features. (See
3434 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
3435 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
3436   return llvm::StringSwitch<bool>(FeatureStr)
3437       .Case("cmov", true)
3438       .Case("mmx", true)
3439       .Case("popcnt", true)
3440       .Case("sse", true)
3441       .Case("sse2", true)
3442       .Case("sse3", true)
3443       .Case("sse4.1", true)
3444       .Case("sse4.2", true)
3445       .Case("avx", true)
3446       .Case("avx2", true)
3447       .Case("sse4a", true)
3448       .Case("fma4", true)
3449       .Case("xop", true)
3450       .Case("fma", true)
3451       .Case("avx512f", true)
3452       .Case("bmi", true)
3453       .Case("bmi2", true)
3454       .Default(false);
3455 }
3456 
3457 bool
3458 X86TargetInfo::validateAsmConstraint(const char *&Name,
3459                                      TargetInfo::ConstraintInfo &Info) const {
3460   switch (*Name) {
3461   default: return false;
3462   // Constant constraints.
3463   case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
3464             // instructions.
3465   case 'Z': // 32-bit unsigned integer constant for use with zero-extending
3466             // x86_64 instructions.
3467   case 's':
3468     Info.setRequiresImmediate();
3469     return true;
3470   case 'I':
3471     Info.setRequiresImmediate(0, 31);
3472     return true;
3473   case 'J':
3474     Info.setRequiresImmediate(0, 63);
3475     return true;
3476   case 'K':
3477     Info.setRequiresImmediate(-128, 127);
3478     return true;
3479   case 'L':
3480     Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) });
3481     return true;
3482   case 'M':
3483     Info.setRequiresImmediate(0, 3);
3484     return true;
3485   case 'N':
3486     Info.setRequiresImmediate(0, 255);
3487     return true;
3488   case 'O':
3489     Info.setRequiresImmediate(0, 127);
3490     return true;
3491   // Register constraints.
3492   case 'Y': // 'Y' is the first character for several 2-character constraints.
3493     // Shift the pointer to the second character of the constraint.
3494     Name++;
3495     switch (*Name) {
3496     default:
3497       return false;
3498     case '0': // First SSE register.
3499     case 't': // Any SSE register, when SSE2 is enabled.
3500     case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
3501     case 'm': // Any MMX register, when inter-unit moves enabled.
3502       Info.setAllowsRegister();
3503       return true;
3504     }
3505   case 'f': // Any x87 floating point stack register.
3506     // Constraint 'f' cannot be used for output operands.
3507     if (Info.ConstraintStr[0] == '=')
3508       return false;
3509     Info.setAllowsRegister();
3510     return true;
3511   case 'a': // eax.
3512   case 'b': // ebx.
3513   case 'c': // ecx.
3514   case 'd': // edx.
3515   case 'S': // esi.
3516   case 'D': // edi.
3517   case 'A': // edx:eax.
3518   case 't': // Top of floating point stack.
3519   case 'u': // Second from top of floating point stack.
3520   case 'q': // Any register accessible as [r]l: a, b, c, and d.
3521   case 'y': // Any MMX register.
3522   case 'x': // Any SSE register.
3523   case 'Q': // Any register accessible as [r]h: a, b, c, and d.
3524   case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
3525   case 'l': // "Index" registers: any general register that can be used as an
3526             // index in a base+index memory access.
3527     Info.setAllowsRegister();
3528     return true;
3529   // Floating point constant constraints.
3530   case 'C': // SSE floating point constant.
3531   case 'G': // x87 floating point constant.
3532     return true;
3533   }
3534 }
3535 
3536 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
3537                                        unsigned Size) const {
3538   // Strip off constraint modifiers.
3539   while (Constraint[0] == '=' ||
3540          Constraint[0] == '+' ||
3541          Constraint[0] == '&')
3542     Constraint = Constraint.substr(1);
3543 
3544   return validateOperandSize(Constraint, Size);
3545 }
3546 
3547 bool X86TargetInfo::validateInputSize(StringRef Constraint,
3548                                       unsigned Size) const {
3549   return validateOperandSize(Constraint, Size);
3550 }
3551 
3552 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
3553                                         unsigned Size) const {
3554   switch (Constraint[0]) {
3555   default: break;
3556   case 'y':
3557     return Size <= 64;
3558   case 'f':
3559   case 't':
3560   case 'u':
3561     return Size <= 128;
3562   case 'x':
3563     if (SSELevel >= AVX512F)
3564       // 512-bit zmm registers can be used if target supports AVX512F.
3565       return Size <= 512U;
3566     else if (SSELevel >= AVX)
3567       // 256-bit ymm registers can be used if target supports AVX.
3568       return Size <= 256U;
3569     return Size <= 128U;
3570   case 'Y':
3571     // 'Y' is the first character for several 2-character constraints.
3572     switch (Constraint[1]) {
3573     default: break;
3574     case 'm':
3575       // 'Ym' is synonymous with 'y'.
3576       return Size <= 64;
3577     case 'i':
3578     case 't':
3579       // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled.
3580       if (SSELevel >= AVX512F)
3581         return Size <= 512U;
3582       else if (SSELevel >= AVX)
3583         return Size <= 256U;
3584       return SSELevel >= SSE2 && Size <= 128U;
3585     }
3586 
3587   }
3588 
3589   return true;
3590 }
3591 
3592 std::string
3593 X86TargetInfo::convertConstraint(const char *&Constraint) const {
3594   switch (*Constraint) {
3595   case 'a': return std::string("{ax}");
3596   case 'b': return std::string("{bx}");
3597   case 'c': return std::string("{cx}");
3598   case 'd': return std::string("{dx}");
3599   case 'S': return std::string("{si}");
3600   case 'D': return std::string("{di}");
3601   case 'p': // address
3602     return std::string("im");
3603   case 't': // top of floating point stack.
3604     return std::string("{st}");
3605   case 'u': // second from top of floating point stack.
3606     return std::string("{st(1)}"); // second from top of floating point stack.
3607   default:
3608     return std::string(1, *Constraint);
3609   }
3610 }
3611 
3612 // X86-32 generic target
3613 class X86_32TargetInfo : public X86TargetInfo {
3614 public:
3615   X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3616     DoubleAlign = LongLongAlign = 32;
3617     LongDoubleWidth = 96;
3618     LongDoubleAlign = 32;
3619     SuitableAlign = 128;
3620     DataLayoutString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128";
3621     SizeType = UnsignedInt;
3622     PtrDiffType = SignedInt;
3623     IntPtrType = SignedInt;
3624     RegParmMax = 3;
3625 
3626     if (getTriple().isOSIAMCU()) {
3627       LongDoubleWidth = 64;
3628       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3629     }
3630 
3631     // Use fpret for all types.
3632     RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
3633                              (1 << TargetInfo::Double) |
3634                              (1 << TargetInfo::LongDouble));
3635 
3636     // x86-32 has atomics up to 8 bytes
3637     // FIXME: Check that we actually have cmpxchg8b before setting
3638     // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
3639     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3640   }
3641   BuiltinVaListKind getBuiltinVaListKind() const override {
3642     return TargetInfo::CharPtrBuiltinVaList;
3643   }
3644 
3645   int getEHDataRegisterNumber(unsigned RegNo) const override {
3646     if (RegNo == 0) return 0;
3647     if (RegNo == 1) return 2;
3648     return -1;
3649   }
3650   bool validateOperandSize(StringRef Constraint,
3651                            unsigned Size) const override {
3652     switch (Constraint[0]) {
3653     default: break;
3654     case 'R':
3655     case 'q':
3656     case 'Q':
3657     case 'a':
3658     case 'b':
3659     case 'c':
3660     case 'd':
3661     case 'S':
3662     case 'D':
3663       return Size <= 32;
3664     case 'A':
3665       return Size <= 64;
3666     }
3667 
3668     return X86TargetInfo::validateOperandSize(Constraint, Size);
3669   }
3670 };
3671 
3672 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
3673 public:
3674   NetBSDI386TargetInfo(const llvm::Triple &Triple)
3675       : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
3676 
3677   unsigned getFloatEvalMethod() const override {
3678     unsigned Major, Minor, Micro;
3679     getTriple().getOSVersion(Major, Minor, Micro);
3680     // New NetBSD uses the default rounding mode.
3681     if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3682       return X86_32TargetInfo::getFloatEvalMethod();
3683     // NetBSD before 6.99.26 defaults to "double" rounding.
3684     return 1;
3685   }
3686 };
3687 
3688 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3689 public:
3690   OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3691       : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3692     SizeType = UnsignedLong;
3693     IntPtrType = SignedLong;
3694     PtrDiffType = SignedLong;
3695   }
3696 };
3697 
3698 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3699 public:
3700   BitrigI386TargetInfo(const llvm::Triple &Triple)
3701       : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3702     SizeType = UnsignedLong;
3703     IntPtrType = SignedLong;
3704     PtrDiffType = SignedLong;
3705   }
3706 };
3707 
3708 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3709 public:
3710   DarwinI386TargetInfo(const llvm::Triple &Triple)
3711       : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3712     LongDoubleWidth = 128;
3713     LongDoubleAlign = 128;
3714     SuitableAlign = 128;
3715     MaxVectorAlign = 256;
3716     // The watchOS simulator uses the builtin bool type for Objective-C.
3717     llvm::Triple T = llvm::Triple(Triple);
3718     if (T.isWatchOS())
3719       UseSignedCharForObjCBool = false;
3720     SizeType = UnsignedLong;
3721     IntPtrType = SignedLong;
3722     DataLayoutString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
3723     HasAlignMac68kSupport = true;
3724   }
3725 
3726   bool handleTargetFeatures(std::vector<std::string> &Features,
3727                             DiagnosticsEngine &Diags) override {
3728     if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features,
3729                                                                   Diags))
3730       return false;
3731     // We now know the features we have: we can decide how to align vectors.
3732     MaxVectorAlign =
3733         hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
3734     return true;
3735   }
3736 };
3737 
3738 // x86-32 Windows target
3739 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3740 public:
3741   WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3742       : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3743     WCharType = UnsignedShort;
3744     DoubleAlign = LongLongAlign = 64;
3745     bool IsWinCOFF =
3746         getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
3747     DataLayoutString = IsWinCOFF
3748                            ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
3749                            : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32";
3750   }
3751   void getTargetDefines(const LangOptions &Opts,
3752                         MacroBuilder &Builder) const override {
3753     WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3754   }
3755 };
3756 
3757 // x86-32 Windows Visual Studio target
3758 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
3759 public:
3760   MicrosoftX86_32TargetInfo(const llvm::Triple &Triple)
3761       : WindowsX86_32TargetInfo(Triple) {
3762     LongDoubleWidth = LongDoubleAlign = 64;
3763     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3764   }
3765   void getTargetDefines(const LangOptions &Opts,
3766                         MacroBuilder &Builder) const override {
3767     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3768     WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3769     // The value of the following reflects processor type.
3770     // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3771     // We lost the original triple, so we use the default.
3772     Builder.defineMacro("_M_IX86", "600");
3773   }
3774 };
3775 
3776 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3777   // Mingw and cygwin define __declspec(a) to __attribute__((a)).  Clang
3778   // supports __declspec natively under -fms-extensions, but we define a no-op
3779   // __declspec macro anyway for pre-processor compatibility.
3780   if (Opts.MicrosoftExt)
3781     Builder.defineMacro("__declspec", "__declspec");
3782   else
3783     Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3784 
3785   if (!Opts.MicrosoftExt) {
3786     // Provide macros for all the calling convention keywords.  Provide both
3787     // single and double underscore prefixed variants.  These are available on
3788     // x64 as well as x86, even though they have no effect.
3789     const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
3790     for (const char *CC : CCs) {
3791       std::string GCCSpelling = "__attribute__((__";
3792       GCCSpelling += CC;
3793       GCCSpelling += "__))";
3794       Builder.defineMacro(Twine("_") + CC, GCCSpelling);
3795       Builder.defineMacro(Twine("__") + CC, GCCSpelling);
3796     }
3797   }
3798 }
3799 
3800 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3801   Builder.defineMacro("__MSVCRT__");
3802   Builder.defineMacro("__MINGW32__");
3803   addCygMingDefines(Opts, Builder);
3804 }
3805 
3806 // x86-32 MinGW target
3807 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3808 public:
3809   MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3810       : WindowsX86_32TargetInfo(Triple) {}
3811   void getTargetDefines(const LangOptions &Opts,
3812                         MacroBuilder &Builder) const override {
3813     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3814     DefineStd(Builder, "WIN32", Opts);
3815     DefineStd(Builder, "WINNT", Opts);
3816     Builder.defineMacro("_X86_");
3817     addMinGWDefines(Opts, Builder);
3818   }
3819 };
3820 
3821 // x86-32 Cygwin target
3822 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3823 public:
3824   CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3825       : X86_32TargetInfo(Triple) {
3826     TLSSupported = false;
3827     WCharType = UnsignedShort;
3828     DoubleAlign = LongLongAlign = 64;
3829     DataLayoutString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32";
3830   }
3831   void getTargetDefines(const LangOptions &Opts,
3832                         MacroBuilder &Builder) const override {
3833     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3834     Builder.defineMacro("_X86_");
3835     Builder.defineMacro("__CYGWIN__");
3836     Builder.defineMacro("__CYGWIN32__");
3837     addCygMingDefines(Opts, Builder);
3838     DefineStd(Builder, "unix", Opts);
3839     if (Opts.CPlusPlus)
3840       Builder.defineMacro("_GNU_SOURCE");
3841   }
3842 };
3843 
3844 // x86-32 Haiku target
3845 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3846 public:
3847   HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3848     SizeType = UnsignedLong;
3849     IntPtrType = SignedLong;
3850     PtrDiffType = SignedLong;
3851     ProcessIDType = SignedLong;
3852     this->UserLabelPrefix = "";
3853     this->TLSSupported = false;
3854   }
3855   void getTargetDefines(const LangOptions &Opts,
3856                         MacroBuilder &Builder) const override {
3857     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3858     Builder.defineMacro("__INTEL__");
3859     Builder.defineMacro("__HAIKU__");
3860   }
3861 };
3862 
3863 // RTEMS Target
3864 template<typename Target>
3865 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3866 protected:
3867   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3868                     MacroBuilder &Builder) const override {
3869     // RTEMS defines; list based off of gcc output
3870 
3871     Builder.defineMacro("__rtems__");
3872     Builder.defineMacro("__ELF__");
3873   }
3874 
3875 public:
3876   RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3877     this->UserLabelPrefix = "";
3878 
3879     switch (Triple.getArch()) {
3880     default:
3881     case llvm::Triple::x86:
3882       // this->MCountName = ".mcount";
3883       break;
3884     case llvm::Triple::mips:
3885     case llvm::Triple::mipsel:
3886     case llvm::Triple::ppc:
3887     case llvm::Triple::ppc64:
3888     case llvm::Triple::ppc64le:
3889       // this->MCountName = "_mcount";
3890       break;
3891     case llvm::Triple::arm:
3892       // this->MCountName = "__mcount";
3893       break;
3894     }
3895   }
3896 };
3897 
3898 // x86-32 RTEMS target
3899 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3900 public:
3901   RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3902     SizeType = UnsignedLong;
3903     IntPtrType = SignedLong;
3904     PtrDiffType = SignedLong;
3905     this->UserLabelPrefix = "";
3906   }
3907   void getTargetDefines(const LangOptions &Opts,
3908                         MacroBuilder &Builder) const override {
3909     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3910     Builder.defineMacro("__INTEL__");
3911     Builder.defineMacro("__rtems__");
3912   }
3913 };
3914 
3915 // x86-64 generic target
3916 class X86_64TargetInfo : public X86TargetInfo {
3917 public:
3918   X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3919     const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
3920     bool IsWinCOFF =
3921         getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
3922     LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
3923     LongDoubleWidth = 128;
3924     LongDoubleAlign = 128;
3925     LargeArrayMinWidth = 128;
3926     LargeArrayAlign = 128;
3927     SuitableAlign = 128;
3928     SizeType    = IsX32 ? UnsignedInt      : UnsignedLong;
3929     PtrDiffType = IsX32 ? SignedInt        : SignedLong;
3930     IntPtrType  = IsX32 ? SignedInt        : SignedLong;
3931     IntMaxType  = IsX32 ? SignedLongLong   : SignedLong;
3932     Int64Type   = IsX32 ? SignedLongLong   : SignedLong;
3933     RegParmMax = 6;
3934 
3935     // Pointers are 32-bit in x32.
3936     DataLayoutString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
3937                              : IsWinCOFF
3938                                    ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
3939                                    : "e-m:e-i64:64-f80:128-n8:16:32:64-S128";
3940 
3941     // Use fpret only for long double.
3942     RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3943 
3944     // Use fp2ret for _Complex long double.
3945     ComplexLongDoubleUsesFP2Ret = true;
3946 
3947     // Make __builtin_ms_va_list available.
3948     HasBuiltinMSVaList = true;
3949 
3950     // x86-64 has atomics up to 16 bytes.
3951     MaxAtomicPromoteWidth = 128;
3952     MaxAtomicInlineWidth = 128;
3953   }
3954   BuiltinVaListKind getBuiltinVaListKind() const override {
3955     return TargetInfo::X86_64ABIBuiltinVaList;
3956   }
3957 
3958   int getEHDataRegisterNumber(unsigned RegNo) const override {
3959     if (RegNo == 0) return 0;
3960     if (RegNo == 1) return 1;
3961     return -1;
3962   }
3963 
3964   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3965     return (CC == CC_C ||
3966             CC == CC_X86VectorCall ||
3967             CC == CC_IntelOclBicc ||
3968             CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
3969   }
3970 
3971   CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3972     return CC_C;
3973   }
3974 
3975   // for x32 we need it here explicitly
3976   bool hasInt128Type() const override { return true; }
3977 };
3978 
3979 // x86-64 Windows target
3980 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3981 public:
3982   WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3983       : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3984     WCharType = UnsignedShort;
3985     LongWidth = LongAlign = 32;
3986     DoubleAlign = LongLongAlign = 64;
3987     IntMaxType = SignedLongLong;
3988     Int64Type = SignedLongLong;
3989     SizeType = UnsignedLongLong;
3990     PtrDiffType = SignedLongLong;
3991     IntPtrType = SignedLongLong;
3992     this->UserLabelPrefix = "";
3993   }
3994 
3995   void getTargetDefines(const LangOptions &Opts,
3996                                 MacroBuilder &Builder) const override {
3997     WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3998     Builder.defineMacro("_WIN64");
3999   }
4000 
4001   BuiltinVaListKind getBuiltinVaListKind() const override {
4002     return TargetInfo::CharPtrBuiltinVaList;
4003   }
4004 
4005   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4006     switch (CC) {
4007     case CC_X86StdCall:
4008     case CC_X86ThisCall:
4009     case CC_X86FastCall:
4010       return CCCR_Ignore;
4011     case CC_C:
4012     case CC_X86VectorCall:
4013     case CC_IntelOclBicc:
4014     case CC_X86_64SysV:
4015       return CCCR_OK;
4016     default:
4017       return CCCR_Warning;
4018     }
4019   }
4020 };
4021 
4022 // x86-64 Windows Visual Studio target
4023 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
4024 public:
4025   MicrosoftX86_64TargetInfo(const llvm::Triple &Triple)
4026       : WindowsX86_64TargetInfo(Triple) {
4027     LongDoubleWidth = LongDoubleAlign = 64;
4028     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4029   }
4030   void getTargetDefines(const LangOptions &Opts,
4031                         MacroBuilder &Builder) const override {
4032     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
4033     WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
4034     Builder.defineMacro("_M_X64", "100");
4035     Builder.defineMacro("_M_AMD64", "100");
4036   }
4037 };
4038 
4039 // x86-64 MinGW target
4040 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
4041 public:
4042   MinGWX86_64TargetInfo(const llvm::Triple &Triple)
4043       : WindowsX86_64TargetInfo(Triple) {
4044     // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks
4045     // with x86 FP ops. Weird.
4046     LongDoubleWidth = LongDoubleAlign = 128;
4047     LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
4048   }
4049 
4050   void getTargetDefines(const LangOptions &Opts,
4051                         MacroBuilder &Builder) const override {
4052     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
4053     DefineStd(Builder, "WIN64", Opts);
4054     Builder.defineMacro("__MINGW64__");
4055     addMinGWDefines(Opts, Builder);
4056 
4057     // GCC defines this macro when it is using __gxx_personality_seh0.
4058     if (!Opts.SjLjExceptions)
4059       Builder.defineMacro("__SEH__");
4060   }
4061 };
4062 
4063 // x86-64 Cygwin target
4064 class CygwinX86_64TargetInfo : public X86_64TargetInfo {
4065 public:
4066   CygwinX86_64TargetInfo(const llvm::Triple &Triple)
4067       : X86_64TargetInfo(Triple) {
4068     TLSSupported = false;
4069     WCharType = UnsignedShort;
4070   }
4071   void getTargetDefines(const LangOptions &Opts,
4072                         MacroBuilder &Builder) const override {
4073     X86_64TargetInfo::getTargetDefines(Opts, Builder);
4074     Builder.defineMacro("__x86_64__");
4075     Builder.defineMacro("__CYGWIN__");
4076     Builder.defineMacro("__CYGWIN64__");
4077     addCygMingDefines(Opts, Builder);
4078     DefineStd(Builder, "unix", Opts);
4079     if (Opts.CPlusPlus)
4080       Builder.defineMacro("_GNU_SOURCE");
4081 
4082     // GCC defines this macro when it is using __gxx_personality_seh0.
4083     if (!Opts.SjLjExceptions)
4084       Builder.defineMacro("__SEH__");
4085   }
4086 };
4087 
4088 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
4089 public:
4090   DarwinX86_64TargetInfo(const llvm::Triple &Triple)
4091       : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
4092     Int64Type = SignedLongLong;
4093     // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
4094     llvm::Triple T = llvm::Triple(Triple);
4095     if (T.isiOS())
4096       UseSignedCharForObjCBool = false;
4097     DataLayoutString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
4098   }
4099 
4100   bool handleTargetFeatures(std::vector<std::string> &Features,
4101                             DiagnosticsEngine &Diags) override {
4102     if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features,
4103                                                                   Diags))
4104       return false;
4105     // We now know the features we have: we can decide how to align vectors.
4106     MaxVectorAlign =
4107         hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
4108     return true;
4109   }
4110 };
4111 
4112 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
4113 public:
4114   OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
4115       : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
4116     IntMaxType = SignedLongLong;
4117     Int64Type = SignedLongLong;
4118   }
4119 };
4120 
4121 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
4122 public:
4123   BitrigX86_64TargetInfo(const llvm::Triple &Triple)
4124       : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
4125     IntMaxType = SignedLongLong;
4126     Int64Type = SignedLongLong;
4127   }
4128 };
4129 
4130 class ARMTargetInfo : public TargetInfo {
4131   // Possible FPU choices.
4132   enum FPUMode {
4133     VFP2FPU = (1 << 0),
4134     VFP3FPU = (1 << 1),
4135     VFP4FPU = (1 << 2),
4136     NeonFPU = (1 << 3),
4137     FPARMV8 = (1 << 4)
4138   };
4139 
4140   // Possible HWDiv features.
4141   enum HWDivMode {
4142     HWDivThumb = (1 << 0),
4143     HWDivARM = (1 << 1)
4144   };
4145 
4146   static bool FPUModeIsVFP(FPUMode Mode) {
4147     return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
4148   }
4149 
4150   static const TargetInfo::GCCRegAlias GCCRegAliases[];
4151   static const char * const GCCRegNames[];
4152 
4153   std::string ABI, CPU;
4154 
4155   StringRef CPUProfile;
4156   StringRef CPUAttr;
4157 
4158   enum {
4159     FP_Default,
4160     FP_VFP,
4161     FP_Neon
4162   } FPMath;
4163 
4164   unsigned ArchISA;
4165   unsigned ArchKind = llvm::ARM::AK_ARMV4T;
4166   unsigned ArchProfile;
4167   unsigned ArchVersion;
4168 
4169   unsigned FPU : 5;
4170 
4171   unsigned IsAAPCS : 1;
4172   unsigned HWDiv : 2;
4173 
4174   // Initialized via features.
4175   unsigned SoftFloat : 1;
4176   unsigned SoftFloatABI : 1;
4177 
4178   unsigned CRC : 1;
4179   unsigned Crypto : 1;
4180   unsigned DSP : 1;
4181   unsigned Unaligned : 1;
4182 
4183   enum {
4184     LDREX_B = (1 << 0), /// byte (8-bit)
4185     LDREX_H = (1 << 1), /// half (16-bit)
4186     LDREX_W = (1 << 2), /// word (32-bit)
4187     LDREX_D = (1 << 3), /// double (64-bit)
4188   };
4189 
4190   uint32_t LDREX;
4191 
4192   // ACLE 6.5.1 Hardware floating point
4193   enum {
4194     HW_FP_HP = (1 << 1), /// half (16-bit)
4195     HW_FP_SP = (1 << 2), /// single (32-bit)
4196     HW_FP_DP = (1 << 3), /// double (64-bit)
4197   };
4198   uint32_t HW_FP;
4199 
4200   static const Builtin::Info BuiltinInfo[];
4201 
4202   void setABIAAPCS() {
4203     IsAAPCS = true;
4204 
4205     DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
4206     const llvm::Triple &T = getTriple();
4207 
4208     // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig.
4209     if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD ||
4210         T.getOS() == llvm::Triple::Bitrig)
4211       SizeType = UnsignedLong;
4212     else
4213       SizeType = UnsignedInt;
4214 
4215     switch (T.getOS()) {
4216     case llvm::Triple::NetBSD:
4217       WCharType = SignedInt;
4218       break;
4219     case llvm::Triple::Win32:
4220       WCharType = UnsignedShort;
4221       break;
4222     case llvm::Triple::Linux:
4223     default:
4224       // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
4225       WCharType = UnsignedInt;
4226       break;
4227     }
4228 
4229     UseBitFieldTypeAlignment = true;
4230 
4231     ZeroLengthBitfieldBoundary = 0;
4232 
4233     // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
4234     // so set preferred for small types to 32.
4235     if (T.isOSBinFormatMachO()) {
4236       DataLayoutString =
4237           BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4238                     : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
4239     } else if (T.isOSWindows()) {
4240       assert(!BigEndian && "Windows on ARM does not support big endian");
4241       DataLayoutString = "e"
4242                          "-m:w"
4243                          "-p:32:32"
4244                          "-i64:64"
4245                          "-v128:64:128"
4246                          "-a:0:32"
4247                          "-n32"
4248                          "-S64";
4249     } else if (T.isOSNaCl()) {
4250       assert(!BigEndian && "NaCl on ARM does not support big endian");
4251       DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128";
4252     } else {
4253       DataLayoutString =
4254           BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4255                     : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
4256     }
4257 
4258     // FIXME: Enumerated types are variable width in straight AAPCS.
4259   }
4260 
4261   void setABIAPCS(bool IsAAPCS16) {
4262     const llvm::Triple &T = getTriple();
4263 
4264     IsAAPCS = false;
4265 
4266     if (IsAAPCS16)
4267       DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
4268     else
4269       DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
4270 
4271     // size_t is unsigned int on FreeBSD.
4272     if (T.getOS() == llvm::Triple::FreeBSD)
4273       SizeType = UnsignedInt;
4274     else
4275       SizeType = UnsignedLong;
4276 
4277     // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
4278     WCharType = SignedInt;
4279 
4280     // Do not respect the alignment of bit-field types when laying out
4281     // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
4282     UseBitFieldTypeAlignment = false;
4283 
4284     /// gcc forces the alignment to 4 bytes, regardless of the type of the
4285     /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
4286     /// gcc.
4287     ZeroLengthBitfieldBoundary = 32;
4288 
4289     if (T.isOSBinFormatMachO() && IsAAPCS16) {
4290       assert(!BigEndian && "AAPCS16 does not support big-endian");
4291       DataLayoutString = "e-m:o-p:32:32-i64:64-a:0:32-n32-S128";
4292     } else if (T.isOSBinFormatMachO())
4293       DataLayoutString =
4294           BigEndian
4295               ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4296               : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
4297     else
4298       DataLayoutString =
4299           BigEndian
4300               ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4301               : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
4302 
4303     // FIXME: Override "preferred align" for double and long long.
4304   }
4305 
4306   void setArchInfo() {
4307     StringRef ArchName = getTriple().getArchName();
4308 
4309     ArchISA     = llvm::ARM::parseArchISA(ArchName);
4310     CPU         = llvm::ARM::getDefaultCPU(ArchName);
4311     unsigned AK = llvm::ARM::parseArch(ArchName);
4312     if (AK != llvm::ARM::AK_INVALID)
4313       ArchKind = AK;
4314     setArchInfo(ArchKind);
4315   }
4316 
4317   void setArchInfo(unsigned Kind) {
4318     StringRef SubArch;
4319 
4320     // cache TargetParser info
4321     ArchKind    = Kind;
4322     SubArch     = llvm::ARM::getSubArch(ArchKind);
4323     ArchProfile = llvm::ARM::parseArchProfile(SubArch);
4324     ArchVersion = llvm::ARM::parseArchVersion(SubArch);
4325 
4326     // cache CPU related strings
4327     CPUAttr    = getCPUAttr();
4328     CPUProfile = getCPUProfile();
4329   }
4330 
4331   void setAtomic() {
4332     // when triple does not specify a sub arch,
4333     // then we are not using inline atomics
4334     bool ShouldUseInlineAtomic =
4335                    (ArchISA == llvm::ARM::IK_ARM   && ArchVersion >= 6) ||
4336                    (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7);
4337     // Cortex M does not support 8 byte atomics, while general Thumb2 does.
4338     if (ArchProfile == llvm::ARM::PK_M) {
4339       MaxAtomicPromoteWidth = 32;
4340       if (ShouldUseInlineAtomic)
4341         MaxAtomicInlineWidth = 32;
4342     }
4343     else {
4344       MaxAtomicPromoteWidth = 64;
4345       if (ShouldUseInlineAtomic)
4346         MaxAtomicInlineWidth = 64;
4347     }
4348   }
4349 
4350   bool isThumb() const {
4351     return (ArchISA == llvm::ARM::IK_THUMB);
4352   }
4353 
4354   bool supportsThumb() const {
4355     return CPUAttr.count('T') || ArchVersion >= 6;
4356   }
4357 
4358   bool supportsThumb2() const {
4359     return CPUAttr.equals("6T2") || ArchVersion >= 7;
4360   }
4361 
4362   StringRef getCPUAttr() const {
4363     // For most sub-arches, the build attribute CPU name is enough.
4364     // For Cortex variants, it's slightly different.
4365     switch(ArchKind) {
4366     default:
4367       return llvm::ARM::getCPUAttr(ArchKind);
4368     case llvm::ARM::AK_ARMV6M:
4369     case llvm::ARM::AK_ARMV6SM:
4370     case llvm::ARM::AK_ARMV6HL:
4371       return "6M";
4372     case llvm::ARM::AK_ARMV7S:
4373       return "7S";
4374     case llvm::ARM::AK_ARMV7:
4375     case llvm::ARM::AK_ARMV7A:
4376     case llvm::ARM::AK_ARMV7L:
4377     case llvm::ARM::AK_ARMV7HL:
4378       return "7A";
4379     case llvm::ARM::AK_ARMV7R:
4380       return "7R";
4381     case llvm::ARM::AK_ARMV7M:
4382       return "7M";
4383     case llvm::ARM::AK_ARMV7EM:
4384       return "7EM";
4385     case llvm::ARM::AK_ARMV8A:
4386       return "8A";
4387     case llvm::ARM::AK_ARMV8_1A:
4388       return "8_1A";
4389     }
4390   }
4391 
4392   StringRef getCPUProfile() const {
4393     switch(ArchProfile) {
4394     case llvm::ARM::PK_A:
4395       return "A";
4396     case llvm::ARM::PK_R:
4397       return "R";
4398     case llvm::ARM::PK_M:
4399       return "M";
4400     default:
4401       return "";
4402     }
4403   }
4404 
4405 public:
4406   ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
4407       : TargetInfo(Triple), FPMath(FP_Default),
4408         IsAAPCS(true), LDREX(0), HW_FP(0) {
4409     BigEndian = IsBigEndian;
4410 
4411     switch (getTriple().getOS()) {
4412     case llvm::Triple::NetBSD:
4413       PtrDiffType = SignedLong;
4414       break;
4415     default:
4416       PtrDiffType = SignedInt;
4417       break;
4418     }
4419 
4420     // Cache arch related info.
4421     setArchInfo();
4422 
4423     // {} in inline assembly are neon specifiers, not assembly variant
4424     // specifiers.
4425     NoAsmVariants = true;
4426 
4427     // FIXME: This duplicates code from the driver that sets the -target-abi
4428     // option - this code is used if -target-abi isn't passed and should
4429     // be unified in some way.
4430     if (Triple.isOSBinFormatMachO()) {
4431       // The backend is hardwired to assume AAPCS for M-class processors, ensure
4432       // the frontend matches that.
4433       if (Triple.getEnvironment() == llvm::Triple::EABI ||
4434           Triple.getOS() == llvm::Triple::UnknownOS ||
4435           StringRef(CPU).startswith("cortex-m")) {
4436         setABI("aapcs");
4437       } else if (Triple.isWatchOS()) {
4438         setABI("aapcs16");
4439       } else {
4440         setABI("apcs-gnu");
4441       }
4442     } else if (Triple.isOSWindows()) {
4443       // FIXME: this is invalid for WindowsCE
4444       setABI("aapcs");
4445     } else {
4446       // Select the default based on the platform.
4447       switch (Triple.getEnvironment()) {
4448       case llvm::Triple::Android:
4449       case llvm::Triple::GNUEABI:
4450       case llvm::Triple::GNUEABIHF:
4451         setABI("aapcs-linux");
4452         break;
4453       case llvm::Triple::EABIHF:
4454       case llvm::Triple::EABI:
4455         setABI("aapcs");
4456         break;
4457       case llvm::Triple::GNU:
4458         setABI("apcs-gnu");
4459       break;
4460       default:
4461         if (Triple.getOS() == llvm::Triple::NetBSD)
4462           setABI("apcs-gnu");
4463         else
4464           setABI("aapcs");
4465         break;
4466       }
4467     }
4468 
4469     // ARM targets default to using the ARM C++ ABI.
4470     TheCXXABI.set(TargetCXXABI::GenericARM);
4471 
4472     // ARM has atomics up to 8 bytes
4473     setAtomic();
4474 
4475     // Do force alignment of members that follow zero length bitfields.  If
4476     // the alignment of the zero-length bitfield is greater than the member
4477     // that follows it, `bar', `bar' will be aligned as the  type of the
4478     // zero length bitfield.
4479     UseZeroLengthBitfieldAlignment = true;
4480   }
4481 
4482   StringRef getABI() const override { return ABI; }
4483 
4484   bool setABI(const std::string &Name) override {
4485     ABI = Name;
4486 
4487     // The defaults (above) are for AAPCS, check if we need to change them.
4488     //
4489     // FIXME: We need support for -meabi... we could just mangle it into the
4490     // name.
4491     if (Name == "apcs-gnu" || Name == "aapcs16") {
4492       setABIAPCS(Name == "aapcs16");
4493       return true;
4494     }
4495     if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
4496       setABIAAPCS();
4497       return true;
4498     }
4499     return false;
4500   }
4501 
4502   // FIXME: This should be based on Arch attributes, not CPU names.
4503   bool
4504   initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
4505                  StringRef CPU,
4506                  const std::vector<std::string> &FeaturesVec) const override {
4507 
4508     std::vector<const char*> TargetFeatures;
4509 
4510     // get default FPU features
4511     unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU);
4512     llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures);
4513 
4514     // get default Extension features
4515     unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU);
4516     llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures);
4517 
4518     for (const char *Feature : TargetFeatures)
4519       if (Feature[0] == '+')
4520         Features[Feature+1] = true;
4521 
4522     return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
4523   }
4524 
4525   bool handleTargetFeatures(std::vector<std::string> &Features,
4526                             DiagnosticsEngine &Diags) override {
4527     FPU = 0;
4528     CRC = 0;
4529     Crypto = 0;
4530     DSP = 0;
4531     Unaligned = 1;
4532     SoftFloat = SoftFloatABI = false;
4533     HWDiv = 0;
4534 
4535     // This does not diagnose illegal cases like having both
4536     // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp".
4537     uint32_t HW_FP_remove = 0;
4538     for (const auto &Feature : Features) {
4539       if (Feature == "+soft-float") {
4540         SoftFloat = true;
4541       } else if (Feature == "+soft-float-abi") {
4542         SoftFloatABI = true;
4543       } else if (Feature == "+vfp2") {
4544         FPU |= VFP2FPU;
4545         HW_FP |= HW_FP_SP | HW_FP_DP;
4546       } else if (Feature == "+vfp3") {
4547         FPU |= VFP3FPU;
4548         HW_FP |= HW_FP_SP | HW_FP_DP;
4549       } else if (Feature == "+vfp4") {
4550         FPU |= VFP4FPU;
4551         HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
4552       } else if (Feature == "+fp-armv8") {
4553         FPU |= FPARMV8;
4554         HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP;
4555       } else if (Feature == "+neon") {
4556         FPU |= NeonFPU;
4557         HW_FP |= HW_FP_SP | HW_FP_DP;
4558       } else if (Feature == "+hwdiv") {
4559         HWDiv |= HWDivThumb;
4560       } else if (Feature == "+hwdiv-arm") {
4561         HWDiv |= HWDivARM;
4562       } else if (Feature == "+crc") {
4563         CRC = 1;
4564       } else if (Feature == "+crypto") {
4565         Crypto = 1;
4566       } else if (Feature == "+dsp") {
4567         DSP = 1;
4568       } else if (Feature == "+fp-only-sp") {
4569         HW_FP_remove |= HW_FP_DP;
4570       } else if (Feature == "+strict-align") {
4571         Unaligned = 0;
4572       } else if (Feature == "+fp16") {
4573         HW_FP |= HW_FP_HP;
4574       }
4575     }
4576     HW_FP &= ~HW_FP_remove;
4577 
4578     switch (ArchVersion) {
4579     case 6:
4580       if (ArchProfile == llvm::ARM::PK_M)
4581         LDREX = 0;
4582       else if (ArchKind == llvm::ARM::AK_ARMV6K)
4583         LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
4584       else
4585         LDREX = LDREX_W;
4586       break;
4587     case 7:
4588       if (ArchProfile == llvm::ARM::PK_M)
4589         LDREX = LDREX_W | LDREX_H | LDREX_B ;
4590       else
4591         LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
4592       break;
4593     case 8:
4594       LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ;
4595     }
4596 
4597     if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
4598       Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
4599       return false;
4600     }
4601 
4602     if (FPMath == FP_Neon)
4603       Features.push_back("+neonfp");
4604     else if (FPMath == FP_VFP)
4605       Features.push_back("-neonfp");
4606 
4607     // Remove front-end specific options which the backend handles differently.
4608     auto Feature =
4609         std::find(Features.begin(), Features.end(), "+soft-float-abi");
4610     if (Feature != Features.end())
4611       Features.erase(Feature);
4612 
4613     return true;
4614   }
4615 
4616   bool hasFeature(StringRef Feature) const override {
4617     return llvm::StringSwitch<bool>(Feature)
4618         .Case("arm", true)
4619         .Case("aarch32", true)
4620         .Case("softfloat", SoftFloat)
4621         .Case("thumb", isThumb())
4622         .Case("neon", (FPU & NeonFPU) && !SoftFloat)
4623         .Case("hwdiv", HWDiv & HWDivThumb)
4624         .Case("hwdiv-arm", HWDiv & HWDivARM)
4625         .Default(false);
4626   }
4627 
4628   bool setCPU(const std::string &Name) override {
4629     if (Name != "generic")
4630       setArchInfo(llvm::ARM::parseCPUArch(Name));
4631 
4632     if (ArchKind == llvm::ARM::AK_INVALID)
4633       return false;
4634     setAtomic();
4635     CPU = Name;
4636     return true;
4637   }
4638 
4639   bool setFPMath(StringRef Name) override;
4640 
4641   void getTargetDefines(const LangOptions &Opts,
4642                         MacroBuilder &Builder) const override {
4643     // Target identification.
4644     Builder.defineMacro("__arm");
4645     Builder.defineMacro("__arm__");
4646 
4647     // Target properties.
4648     Builder.defineMacro("__REGISTER_PREFIX__", "");
4649 
4650     // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU
4651     // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__.
4652     if (getTriple().isWatchOS())
4653       Builder.defineMacro("__ARM_ARCH_7K__", "2");
4654 
4655     if (!CPUAttr.empty())
4656       Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__");
4657 
4658     // ACLE 6.4.1 ARM/Thumb instruction set architecture
4659     // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
4660     Builder.defineMacro("__ARM_ARCH", llvm::utostr(ArchVersion));
4661 
4662     if (ArchVersion >= 8) {
4663       // ACLE 6.5.7 Crypto Extension
4664       if (Crypto)
4665         Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
4666       // ACLE 6.5.8 CRC32 Extension
4667       if (CRC)
4668         Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
4669       // ACLE 6.5.10 Numeric Maximum and Minimum
4670       Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
4671       // ACLE 6.5.9 Directed Rounding
4672       Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
4673     }
4674 
4675     // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA.  It
4676     // is not defined for the M-profile.
4677     // NOTE that the deffault profile is assumed to be 'A'
4678     if (CPUProfile.empty() || CPUProfile != "M")
4679       Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
4680 
4681     // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
4682     // Thumb ISA (including v6-M).  It is set to 2 if the core supports the
4683     // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
4684     if (supportsThumb2())
4685       Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
4686     else if (supportsThumb())
4687       Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
4688 
4689     // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
4690     // instruction set such as ARM or Thumb.
4691     Builder.defineMacro("__ARM_32BIT_STATE", "1");
4692 
4693     // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
4694 
4695     // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
4696     if (!CPUProfile.empty())
4697       Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
4698 
4699     // ACLE 6.4.3 Unaligned access supported in hardware
4700     if (Unaligned)
4701       Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
4702 
4703     // ACLE 6.4.4 LDREX/STREX
4704     if (LDREX)
4705       Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX));
4706 
4707     // ACLE 6.4.5 CLZ
4708     if (ArchVersion == 5 ||
4709        (ArchVersion == 6 && CPUProfile != "M") ||
4710         ArchVersion >  6)
4711       Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
4712 
4713     // ACLE 6.5.1 Hardware Floating Point
4714     if (HW_FP)
4715       Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
4716 
4717     // ACLE predefines.
4718     Builder.defineMacro("__ARM_ACLE", "200");
4719 
4720     // FP16 support (we currently only support IEEE format).
4721     Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
4722     Builder.defineMacro("__ARM_FP16_ARGS", "1");
4723 
4724     // ACLE 6.5.3 Fused multiply-accumulate (FMA)
4725     if (ArchVersion >= 7 && (CPUProfile != "M" || CPUAttr == "7EM"))
4726       Builder.defineMacro("__ARM_FEATURE_FMA", "1");
4727 
4728     // Subtarget options.
4729 
4730     // FIXME: It's more complicated than this and we don't really support
4731     // interworking.
4732     // Windows on ARM does not "support" interworking
4733     if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows())
4734       Builder.defineMacro("__THUMB_INTERWORK__");
4735 
4736     if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
4737       // Embedded targets on Darwin follow AAPCS, but not EABI.
4738       // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
4739       if (!getTriple().isOSDarwin() && !getTriple().isOSWindows())
4740         Builder.defineMacro("__ARM_EABI__");
4741       Builder.defineMacro("__ARM_PCS", "1");
4742 
4743       if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
4744         Builder.defineMacro("__ARM_PCS_VFP", "1");
4745     }
4746 
4747     if (SoftFloat)
4748       Builder.defineMacro("__SOFTFP__");
4749 
4750     if (CPU == "xscale")
4751       Builder.defineMacro("__XSCALE__");
4752 
4753     if (isThumb()) {
4754       Builder.defineMacro("__THUMBEL__");
4755       Builder.defineMacro("__thumb__");
4756       if (supportsThumb2())
4757         Builder.defineMacro("__thumb2__");
4758     }
4759 
4760     // ACLE 6.4.9 32-bit SIMD instructions
4761     if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM"))
4762       Builder.defineMacro("__ARM_FEATURE_SIMD32", "1");
4763 
4764     // ACLE 6.4.10 Hardware Integer Divide
4765     if (((HWDiv & HWDivThumb) && isThumb()) ||
4766         ((HWDiv & HWDivARM) && !isThumb())) {
4767       Builder.defineMacro("__ARM_FEATURE_IDIV", "1");
4768       Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
4769     }
4770 
4771     // Note, this is always on in gcc, even though it doesn't make sense.
4772     Builder.defineMacro("__APCS_32__");
4773 
4774     if (FPUModeIsVFP((FPUMode) FPU)) {
4775       Builder.defineMacro("__VFP_FP__");
4776       if (FPU & VFP2FPU)
4777         Builder.defineMacro("__ARM_VFPV2__");
4778       if (FPU & VFP3FPU)
4779         Builder.defineMacro("__ARM_VFPV3__");
4780       if (FPU & VFP4FPU)
4781         Builder.defineMacro("__ARM_VFPV4__");
4782     }
4783 
4784     // This only gets set when Neon instructions are actually available, unlike
4785     // the VFP define, hence the soft float and arch check. This is subtly
4786     // different from gcc, we follow the intent which was that it should be set
4787     // when Neon instructions are actually available.
4788     if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) {
4789       Builder.defineMacro("__ARM_NEON", "1");
4790       Builder.defineMacro("__ARM_NEON__");
4791       // current AArch32 NEON implementations do not support double-precision
4792       // floating-point even when it is present in VFP.
4793       Builder.defineMacro("__ARM_NEON_FP",
4794                           "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP));
4795     }
4796 
4797     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
4798                         Opts.ShortWChar ? "2" : "4");
4799 
4800     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4801                         Opts.ShortEnums ? "1" : "4");
4802 
4803     if (ArchVersion >= 6 && CPUAttr != "6M") {
4804       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4805       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4806       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4807       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4808     }
4809 
4810     // ACLE 6.4.7 DSP instructions
4811     if (DSP) {
4812       Builder.defineMacro("__ARM_FEATURE_DSP", "1");
4813     }
4814 
4815     // ACLE 6.4.8 Saturation instructions
4816     bool SAT = false;
4817     if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) {
4818       Builder.defineMacro("__ARM_FEATURE_SAT", "1");
4819       SAT = true;
4820     }
4821 
4822     // ACLE 6.4.6 Q (saturation) flag
4823     if (DSP || SAT)
4824       Builder.defineMacro("__ARM_FEATURE_QBIT", "1");
4825 
4826     if (Opts.UnsafeFPMath)
4827       Builder.defineMacro("__ARM_FP_FAST", "1");
4828   }
4829 
4830   ArrayRef<Builtin::Info> getTargetBuiltins() const override {
4831     return llvm::makeArrayRef(BuiltinInfo,
4832                              clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin);
4833   }
4834   bool isCLZForZeroUndef() const override { return false; }
4835   BuiltinVaListKind getBuiltinVaListKind() const override {
4836     return IsAAPCS
4837                ? AAPCSABIBuiltinVaList
4838                : (getTriple().isWatchOS() ? TargetInfo::CharPtrBuiltinVaList
4839                                           : TargetInfo::VoidPtrBuiltinVaList);
4840   }
4841   ArrayRef<const char *> getGCCRegNames() const override;
4842   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
4843   bool validateAsmConstraint(const char *&Name,
4844                              TargetInfo::ConstraintInfo &Info) const override {
4845     switch (*Name) {
4846     default: break;
4847     case 'l': // r0-r7
4848     case 'h': // r8-r15
4849     case 'w': // VFP Floating point register single precision
4850     case 'P': // VFP Floating point register double precision
4851       Info.setAllowsRegister();
4852       return true;
4853     case 'I':
4854     case 'J':
4855     case 'K':
4856     case 'L':
4857     case 'M':
4858       // FIXME
4859       return true;
4860     case 'Q': // A memory address that is a single base register.
4861       Info.setAllowsMemory();
4862       return true;
4863     case 'U': // a memory reference...
4864       switch (Name[1]) {
4865       case 'q': // ...ARMV4 ldrsb
4866       case 'v': // ...VFP load/store (reg+constant offset)
4867       case 'y': // ...iWMMXt load/store
4868       case 't': // address valid for load/store opaque types wider
4869                 // than 128-bits
4870       case 'n': // valid address for Neon doubleword vector load/store
4871       case 'm': // valid address for Neon element and structure load/store
4872       case 's': // valid address for non-offset loads/stores of quad-word
4873                 // values in four ARM registers
4874         Info.setAllowsMemory();
4875         Name++;
4876         return true;
4877       }
4878     }
4879     return false;
4880   }
4881   std::string convertConstraint(const char *&Constraint) const override {
4882     std::string R;
4883     switch (*Constraint) {
4884     case 'U':   // Two-character constraint; add "^" hint for later parsing.
4885       R = std::string("^") + std::string(Constraint, 2);
4886       Constraint++;
4887       break;
4888     case 'p': // 'p' should be translated to 'r' by default.
4889       R = std::string("r");
4890       break;
4891     default:
4892       return std::string(1, *Constraint);
4893     }
4894     return R;
4895   }
4896   bool
4897   validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4898                              std::string &SuggestedModifier) const override {
4899     bool isOutput = (Constraint[0] == '=');
4900     bool isInOut = (Constraint[0] == '+');
4901 
4902     // Strip off constraint modifiers.
4903     while (Constraint[0] == '=' ||
4904            Constraint[0] == '+' ||
4905            Constraint[0] == '&')
4906       Constraint = Constraint.substr(1);
4907 
4908     switch (Constraint[0]) {
4909     default: break;
4910     case 'r': {
4911       switch (Modifier) {
4912       default:
4913         return (isInOut || isOutput || Size <= 64);
4914       case 'q':
4915         // A register of size 32 cannot fit a vector type.
4916         return false;
4917       }
4918     }
4919     }
4920 
4921     return true;
4922   }
4923   const char *getClobbers() const override {
4924     // FIXME: Is this really right?
4925     return "";
4926   }
4927 
4928   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4929     return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
4930   }
4931 
4932   int getEHDataRegisterNumber(unsigned RegNo) const override {
4933     if (RegNo == 0) return 0;
4934     if (RegNo == 1) return 1;
4935     return -1;
4936   }
4937 
4938   bool hasSjLjLowering() const override {
4939     return true;
4940   }
4941 };
4942 
4943 bool ARMTargetInfo::setFPMath(StringRef Name) {
4944   if (Name == "neon") {
4945     FPMath = FP_Neon;
4946     return true;
4947   } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
4948              Name == "vfp4") {
4949     FPMath = FP_VFP;
4950     return true;
4951   }
4952   return false;
4953 }
4954 
4955 const char * const ARMTargetInfo::GCCRegNames[] = {
4956   // Integer registers
4957   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4958   "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
4959 
4960   // Float registers
4961   "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
4962   "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
4963   "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
4964   "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4965 
4966   // Double registers
4967   "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
4968   "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
4969   "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
4970   "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4971 
4972   // Quad registers
4973   "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
4974   "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
4975 };
4976 
4977 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const {
4978   return llvm::makeArrayRef(GCCRegNames);
4979 }
4980 
4981 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
4982   { { "a1" }, "r0" },
4983   { { "a2" }, "r1" },
4984   { { "a3" }, "r2" },
4985   { { "a4" }, "r3" },
4986   { { "v1" }, "r4" },
4987   { { "v2" }, "r5" },
4988   { { "v3" }, "r6" },
4989   { { "v4" }, "r7" },
4990   { { "v5" }, "r8" },
4991   { { "v6", "rfp" }, "r9" },
4992   { { "sl" }, "r10" },
4993   { { "fp" }, "r11" },
4994   { { "ip" }, "r12" },
4995   { { "r13" }, "sp" },
4996   { { "r14" }, "lr" },
4997   { { "r15" }, "pc" },
4998   // The S, D and Q registers overlap, but aren't really aliases; we
4999   // don't want to substitute one of these for a different-sized one.
5000 };
5001 
5002 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const {
5003   return llvm::makeArrayRef(GCCRegAliases);
5004 }
5005 
5006 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
5007 #define BUILTIN(ID, TYPE, ATTRS) \
5008   { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5009 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5010   { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5011 #include "clang/Basic/BuiltinsNEON.def"
5012 
5013 #define BUILTIN(ID, TYPE, ATTRS) \
5014   { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5015 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \
5016   { #ID, TYPE, ATTRS, nullptr, LANG, nullptr },
5017 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5018   { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5019 #include "clang/Basic/BuiltinsARM.def"
5020 };
5021 
5022 class ARMleTargetInfo : public ARMTargetInfo {
5023 public:
5024   ARMleTargetInfo(const llvm::Triple &Triple)
5025     : ARMTargetInfo(Triple, false) { }
5026   void getTargetDefines(const LangOptions &Opts,
5027                         MacroBuilder &Builder) const override {
5028     Builder.defineMacro("__ARMEL__");
5029     ARMTargetInfo::getTargetDefines(Opts, Builder);
5030   }
5031 };
5032 
5033 class ARMbeTargetInfo : public ARMTargetInfo {
5034 public:
5035   ARMbeTargetInfo(const llvm::Triple &Triple)
5036     : ARMTargetInfo(Triple, true) { }
5037   void getTargetDefines(const LangOptions &Opts,
5038                         MacroBuilder &Builder) const override {
5039     Builder.defineMacro("__ARMEB__");
5040     Builder.defineMacro("__ARM_BIG_ENDIAN");
5041     ARMTargetInfo::getTargetDefines(Opts, Builder);
5042   }
5043 };
5044 
5045 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
5046   const llvm::Triple Triple;
5047 public:
5048   WindowsARMTargetInfo(const llvm::Triple &Triple)
5049     : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) {
5050     TLSSupported = false;
5051     WCharType = UnsignedShort;
5052     SizeType = UnsignedInt;
5053     UserLabelPrefix = "";
5054   }
5055   void getVisualStudioDefines(const LangOptions &Opts,
5056                               MacroBuilder &Builder) const {
5057     WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
5058 
5059     // FIXME: this is invalid for WindowsCE
5060     Builder.defineMacro("_M_ARM_NT", "1");
5061     Builder.defineMacro("_M_ARMT", "_M_ARM");
5062     Builder.defineMacro("_M_THUMB", "_M_ARM");
5063 
5064     assert((Triple.getArch() == llvm::Triple::arm ||
5065             Triple.getArch() == llvm::Triple::thumb) &&
5066            "invalid architecture for Windows ARM target info");
5067     unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
5068     Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
5069 
5070     // TODO map the complete set of values
5071     // 31: VFPv3 40: VFPv4
5072     Builder.defineMacro("_M_ARM_FP", "31");
5073   }
5074   BuiltinVaListKind getBuiltinVaListKind() const override {
5075     return TargetInfo::CharPtrBuiltinVaList;
5076   }
5077   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
5078     switch (CC) {
5079     case CC_X86StdCall:
5080     case CC_X86ThisCall:
5081     case CC_X86FastCall:
5082     case CC_X86VectorCall:
5083       return CCCR_Ignore;
5084     case CC_C:
5085       return CCCR_OK;
5086     default:
5087       return CCCR_Warning;
5088     }
5089   }
5090 };
5091 
5092 // Windows ARM + Itanium C++ ABI Target
5093 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
5094 public:
5095   ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple)
5096     : WindowsARMTargetInfo(Triple) {
5097     TheCXXABI.set(TargetCXXABI::GenericARM);
5098   }
5099 
5100   void getTargetDefines(const LangOptions &Opts,
5101                         MacroBuilder &Builder) const override {
5102     WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5103 
5104     if (Opts.MSVCCompat)
5105       WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
5106   }
5107 };
5108 
5109 // Windows ARM, MS (C++) ABI
5110 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
5111 public:
5112   MicrosoftARMleTargetInfo(const llvm::Triple &Triple)
5113     : WindowsARMTargetInfo(Triple) {
5114     TheCXXABI.set(TargetCXXABI::Microsoft);
5115   }
5116 
5117   void getTargetDefines(const LangOptions &Opts,
5118                         MacroBuilder &Builder) const override {
5119     WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5120     WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
5121   }
5122 };
5123 
5124 // ARM MinGW target
5125 class MinGWARMTargetInfo : public WindowsARMTargetInfo {
5126 public:
5127   MinGWARMTargetInfo(const llvm::Triple &Triple)
5128       : WindowsARMTargetInfo(Triple) {
5129     TheCXXABI.set(TargetCXXABI::GenericARM);
5130   }
5131 
5132   void getTargetDefines(const LangOptions &Opts,
5133                         MacroBuilder &Builder) const override {
5134     WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
5135     DefineStd(Builder, "WIN32", Opts);
5136     DefineStd(Builder, "WINNT", Opts);
5137     Builder.defineMacro("_ARM_");
5138     addMinGWDefines(Opts, Builder);
5139   }
5140 };
5141 
5142 // ARM Cygwin target
5143 class CygwinARMTargetInfo : public ARMleTargetInfo {
5144 public:
5145   CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) {
5146     TLSSupported = false;
5147     WCharType = UnsignedShort;
5148     DoubleAlign = LongLongAlign = 64;
5149     DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
5150   }
5151   void getTargetDefines(const LangOptions &Opts,
5152                         MacroBuilder &Builder) const override {
5153     ARMleTargetInfo::getTargetDefines(Opts, Builder);
5154     Builder.defineMacro("_ARM_");
5155     Builder.defineMacro("__CYGWIN__");
5156     Builder.defineMacro("__CYGWIN32__");
5157     DefineStd(Builder, "unix", Opts);
5158     if (Opts.CPlusPlus)
5159       Builder.defineMacro("_GNU_SOURCE");
5160   }
5161 };
5162 
5163 class DarwinARMTargetInfo :
5164   public DarwinTargetInfo<ARMleTargetInfo> {
5165 protected:
5166   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
5167                     MacroBuilder &Builder) const override {
5168     getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
5169   }
5170 
5171 public:
5172   DarwinARMTargetInfo(const llvm::Triple &Triple)
5173       : DarwinTargetInfo<ARMleTargetInfo>(Triple) {
5174     HasAlignMac68kSupport = true;
5175     // iOS always has 64-bit atomic instructions.
5176     // FIXME: This should be based off of the target features in
5177     // ARMleTargetInfo.
5178     MaxAtomicInlineWidth = 64;
5179 
5180     if (Triple.isWatchOS()) {
5181       // Darwin on iOS uses a variant of the ARM C++ ABI.
5182       TheCXXABI.set(TargetCXXABI::WatchOS);
5183 
5184       // The 32-bit ABI is silent on what ptrdiff_t should be, but given that
5185       // size_t is long, it's a bit weird for it to be int.
5186       PtrDiffType = SignedLong;
5187 
5188       // BOOL should be a real boolean on the new ABI
5189       UseSignedCharForObjCBool = false;
5190     } else
5191       TheCXXABI.set(TargetCXXABI::iOS);
5192   }
5193 };
5194 
5195 class AArch64TargetInfo : public TargetInfo {
5196   virtual void setDataLayoutString() = 0;
5197   static const TargetInfo::GCCRegAlias GCCRegAliases[];
5198   static const char *const GCCRegNames[];
5199 
5200   enum FPUModeEnum {
5201     FPUMode,
5202     NeonMode
5203   };
5204 
5205   unsigned FPU;
5206   unsigned CRC;
5207   unsigned Crypto;
5208   unsigned Unaligned;
5209 
5210   static const Builtin::Info BuiltinInfo[];
5211 
5212   std::string ABI;
5213 
5214 public:
5215   AArch64TargetInfo(const llvm::Triple &Triple)
5216       : TargetInfo(Triple), ABI("aapcs") {
5217 
5218     if (getTriple().getOS() == llvm::Triple::NetBSD) {
5219       WCharType = SignedInt;
5220 
5221       // NetBSD apparently prefers consistency across ARM targets to consistency
5222       // across 64-bit targets.
5223       Int64Type = SignedLongLong;
5224       IntMaxType = SignedLongLong;
5225     } else {
5226       WCharType = UnsignedInt;
5227       Int64Type = SignedLong;
5228       IntMaxType = SignedLong;
5229     }
5230 
5231     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5232     MaxVectorAlign = 128;
5233     MaxAtomicInlineWidth = 128;
5234     MaxAtomicPromoteWidth = 128;
5235 
5236     LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
5237     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5238 
5239     // {} in inline assembly are neon specifiers, not assembly variant
5240     // specifiers.
5241     NoAsmVariants = true;
5242 
5243     // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
5244     // contributes to the alignment of the containing aggregate in the same way
5245     // a plain (non bit-field) member of that type would, without exception for
5246     // zero-sized or anonymous bit-fields."
5247     assert(UseBitFieldTypeAlignment && "bitfields affect type alignment");
5248     UseZeroLengthBitfieldAlignment = true;
5249 
5250     // AArch64 targets default to using the ARM C++ ABI.
5251     TheCXXABI.set(TargetCXXABI::GenericAArch64);
5252   }
5253 
5254   StringRef getABI() const override { return ABI; }
5255   bool setABI(const std::string &Name) override {
5256     if (Name != "aapcs" && Name != "darwinpcs")
5257       return false;
5258 
5259     ABI = Name;
5260     return true;
5261   }
5262 
5263   bool setCPU(const std::string &Name) override {
5264     bool CPUKnown = llvm::StringSwitch<bool>(Name)
5265                         .Case("generic", true)
5266                         .Cases("cortex-a53", "cortex-a57", "cortex-a72", true)
5267                         .Case("cyclone", true)
5268                         .Default(false);
5269     return CPUKnown;
5270   }
5271 
5272   void getTargetDefines(const LangOptions &Opts,
5273                         MacroBuilder &Builder) const override {
5274     // Target identification.
5275     Builder.defineMacro("__aarch64__");
5276 
5277     // Target properties.
5278     Builder.defineMacro("_LP64");
5279     Builder.defineMacro("__LP64__");
5280 
5281     // ACLE predefines. Many can only have one possible value on v8 AArch64.
5282     Builder.defineMacro("__ARM_ACLE", "200");
5283     Builder.defineMacro("__ARM_ARCH", "8");
5284     Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
5285 
5286     Builder.defineMacro("__ARM_64BIT_STATE", "1");
5287     Builder.defineMacro("__ARM_PCS_AAPCS64", "1");
5288     Builder.defineMacro("__ARM_ARCH_ISA_A64", "1");
5289 
5290     Builder.defineMacro("__ARM_FEATURE_CLZ", "1");
5291     Builder.defineMacro("__ARM_FEATURE_FMA", "1");
5292     Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF");
5293     Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE
5294     Builder.defineMacro("__ARM_FEATURE_DIV");  // For backwards compatibility
5295     Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1");
5296     Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1");
5297 
5298     Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
5299 
5300     // 0xe implies support for half, single and double precision operations.
5301     Builder.defineMacro("__ARM_FP", "0xE");
5302 
5303     // PCS specifies this for SysV variants, which is all we support. Other ABIs
5304     // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
5305     Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1");
5306     Builder.defineMacro("__ARM_FP16_ARGS", "1");
5307 
5308     if (Opts.UnsafeFPMath)
5309       Builder.defineMacro("__ARM_FP_FAST", "1");
5310 
5311     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
5312 
5313     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
5314                         Opts.ShortEnums ? "1" : "4");
5315 
5316     if (FPU == NeonMode) {
5317       Builder.defineMacro("__ARM_NEON", "1");
5318       // 64-bit NEON supports half, single and double precision operations.
5319       Builder.defineMacro("__ARM_NEON_FP", "0xE");
5320     }
5321 
5322     if (CRC)
5323       Builder.defineMacro("__ARM_FEATURE_CRC32", "1");
5324 
5325     if (Crypto)
5326       Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
5327 
5328     if (Unaligned)
5329       Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
5330 
5331     // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
5332     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
5333     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
5334     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
5335     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
5336   }
5337 
5338   ArrayRef<Builtin::Info> getTargetBuiltins() const override {
5339     return llvm::makeArrayRef(BuiltinInfo,
5340                        clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin);
5341   }
5342 
5343   bool hasFeature(StringRef Feature) const override {
5344     return Feature == "aarch64" ||
5345       Feature == "arm64" ||
5346       Feature == "arm" ||
5347       (Feature == "neon" && FPU == NeonMode);
5348   }
5349 
5350   bool handleTargetFeatures(std::vector<std::string> &Features,
5351                             DiagnosticsEngine &Diags) override {
5352     FPU = FPUMode;
5353     CRC = 0;
5354     Crypto = 0;
5355     Unaligned = 1;
5356 
5357     for (const auto &Feature : Features) {
5358       if (Feature == "+neon")
5359         FPU = NeonMode;
5360       if (Feature == "+crc")
5361         CRC = 1;
5362       if (Feature == "+crypto")
5363         Crypto = 1;
5364       if (Feature == "+strict-align")
5365         Unaligned = 0;
5366     }
5367 
5368     setDataLayoutString();
5369 
5370     return true;
5371   }
5372 
5373   bool isCLZForZeroUndef() const override { return false; }
5374 
5375   BuiltinVaListKind getBuiltinVaListKind() const override {
5376     return TargetInfo::AArch64ABIBuiltinVaList;
5377   }
5378 
5379   ArrayRef<const char *> getGCCRegNames() const override;
5380   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
5381 
5382   bool validateAsmConstraint(const char *&Name,
5383                              TargetInfo::ConstraintInfo &Info) const override {
5384     switch (*Name) {
5385     default:
5386       return false;
5387     case 'w': // Floating point and SIMD registers (V0-V31)
5388       Info.setAllowsRegister();
5389       return true;
5390     case 'I': // Constant that can be used with an ADD instruction
5391     case 'J': // Constant that can be used with a SUB instruction
5392     case 'K': // Constant that can be used with a 32-bit logical instruction
5393     case 'L': // Constant that can be used with a 64-bit logical instruction
5394     case 'M': // Constant that can be used as a 32-bit MOV immediate
5395     case 'N': // Constant that can be used as a 64-bit MOV immediate
5396     case 'Y': // Floating point constant zero
5397     case 'Z': // Integer constant zero
5398       return true;
5399     case 'Q': // A memory reference with base register and no offset
5400       Info.setAllowsMemory();
5401       return true;
5402     case 'S': // A symbolic address
5403       Info.setAllowsRegister();
5404       return true;
5405     case 'U':
5406       // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
5407       // Utf: A memory address suitable for ldp/stp in TF mode.
5408       // Usa: An absolute symbolic address.
5409       // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
5410       llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
5411     case 'z': // Zero register, wzr or xzr
5412       Info.setAllowsRegister();
5413       return true;
5414     case 'x': // Floating point and SIMD registers (V0-V15)
5415       Info.setAllowsRegister();
5416       return true;
5417     }
5418     return false;
5419   }
5420 
5421   bool
5422   validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
5423                              std::string &SuggestedModifier) const override {
5424     // Strip off constraint modifiers.
5425     while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
5426       Constraint = Constraint.substr(1);
5427 
5428     switch (Constraint[0]) {
5429     default:
5430       return true;
5431     case 'z':
5432     case 'r': {
5433       switch (Modifier) {
5434       case 'x':
5435       case 'w':
5436         // For now assume that the person knows what they're
5437         // doing with the modifier.
5438         return true;
5439       default:
5440         // By default an 'r' constraint will be in the 'x'
5441         // registers.
5442         if (Size == 64)
5443           return true;
5444 
5445         SuggestedModifier = "w";
5446         return false;
5447       }
5448     }
5449     }
5450   }
5451 
5452   const char *getClobbers() const override { return ""; }
5453 
5454   int getEHDataRegisterNumber(unsigned RegNo) const override {
5455     if (RegNo == 0)
5456       return 0;
5457     if (RegNo == 1)
5458       return 1;
5459     return -1;
5460   }
5461 };
5462 
5463 const char *const AArch64TargetInfo::GCCRegNames[] = {
5464   // 32-bit Integer registers
5465   "w0",  "w1",  "w2",  "w3",  "w4",  "w5",  "w6",  "w7",  "w8",  "w9",  "w10",
5466   "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
5467   "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
5468 
5469   // 64-bit Integer registers
5470   "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",  "x8",  "x9",  "x10",
5471   "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
5472   "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp",  "lr",  "sp",
5473 
5474   // 32-bit floating point regsisters
5475   "s0",  "s1",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",  "s8",  "s9",  "s10",
5476   "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
5477   "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5478 
5479   // 64-bit floating point regsisters
5480   "d0",  "d1",  "d2",  "d3",  "d4",  "d5",  "d6",  "d7",  "d8",  "d9",  "d10",
5481   "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
5482   "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
5483 
5484   // Vector registers
5485   "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",  "v8",  "v9",  "v10",
5486   "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
5487   "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
5488 };
5489 
5490 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const {
5491   return llvm::makeArrayRef(GCCRegNames);
5492 }
5493 
5494 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
5495   { { "w31" }, "wsp" },
5496   { { "x29" }, "fp" },
5497   { { "x30" }, "lr" },
5498   { { "x31" }, "sp" },
5499   // The S/D/Q and W/X registers overlap, but aren't really aliases; we
5500   // don't want to substitute one of these for a different-sized one.
5501 };
5502 
5503 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const {
5504   return llvm::makeArrayRef(GCCRegAliases);
5505 }
5506 
5507 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
5508 #define BUILTIN(ID, TYPE, ATTRS)                                               \
5509   { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5510 #include "clang/Basic/BuiltinsNEON.def"
5511 
5512 #define BUILTIN(ID, TYPE, ATTRS)                                               \
5513   { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5514 #include "clang/Basic/BuiltinsAArch64.def"
5515 };
5516 
5517 class AArch64leTargetInfo : public AArch64TargetInfo {
5518   void setDataLayoutString() override {
5519     if (getTriple().isOSBinFormatMachO())
5520       DataLayoutString = "e-m:o-i64:64-i128:128-n32:64-S128";
5521     else
5522       DataLayoutString = "e-m:e-i64:64-i128:128-n32:64-S128";
5523   }
5524 
5525 public:
5526   AArch64leTargetInfo(const llvm::Triple &Triple)
5527     : AArch64TargetInfo(Triple) {
5528     BigEndian = false;
5529     }
5530   void getTargetDefines(const LangOptions &Opts,
5531                         MacroBuilder &Builder) const override {
5532     Builder.defineMacro("__AARCH64EL__");
5533     AArch64TargetInfo::getTargetDefines(Opts, Builder);
5534   }
5535 };
5536 
5537 class AArch64beTargetInfo : public AArch64TargetInfo {
5538   void setDataLayoutString() override {
5539     assert(!getTriple().isOSBinFormatMachO());
5540     DataLayoutString = "E-m:e-i64:64-i128:128-n32:64-S128";
5541   }
5542 
5543 public:
5544   AArch64beTargetInfo(const llvm::Triple &Triple)
5545     : AArch64TargetInfo(Triple) { }
5546   void getTargetDefines(const LangOptions &Opts,
5547                         MacroBuilder &Builder) const override {
5548     Builder.defineMacro("__AARCH64EB__");
5549     Builder.defineMacro("__AARCH_BIG_ENDIAN");
5550     Builder.defineMacro("__ARM_BIG_ENDIAN");
5551     AArch64TargetInfo::getTargetDefines(Opts, Builder);
5552   }
5553 };
5554 
5555 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
5556 protected:
5557   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
5558                     MacroBuilder &Builder) const override {
5559     Builder.defineMacro("__AARCH64_SIMD__");
5560     Builder.defineMacro("__ARM64_ARCH_8__");
5561     Builder.defineMacro("__ARM_NEON__");
5562     Builder.defineMacro("__LITTLE_ENDIAN__");
5563     Builder.defineMacro("__REGISTER_PREFIX__", "");
5564     Builder.defineMacro("__arm64", "1");
5565     Builder.defineMacro("__arm64__", "1");
5566 
5567     getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
5568   }
5569 
5570 public:
5571   DarwinAArch64TargetInfo(const llvm::Triple &Triple)
5572       : DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
5573     Int64Type = SignedLongLong;
5574     WCharType = SignedInt;
5575     UseSignedCharForObjCBool = false;
5576 
5577     LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
5578     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
5579 
5580     TheCXXABI.set(TargetCXXABI::iOS64);
5581   }
5582 
5583   BuiltinVaListKind getBuiltinVaListKind() const override {
5584     return TargetInfo::CharPtrBuiltinVaList;
5585   }
5586 };
5587 
5588 // Hexagon abstract base class
5589 class HexagonTargetInfo : public TargetInfo {
5590   static const Builtin::Info BuiltinInfo[];
5591   static const char * const GCCRegNames[];
5592   static const TargetInfo::GCCRegAlias GCCRegAliases[];
5593   std::string CPU;
5594 public:
5595   HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5596     BigEndian = false;
5597     DataLayoutString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32";
5598 
5599     // {} in inline assembly are packet specifiers, not assembly variant
5600     // specifiers.
5601     NoAsmVariants = true;
5602   }
5603 
5604   ArrayRef<Builtin::Info> getTargetBuiltins() const override {
5605     return llvm::makeArrayRef(BuiltinInfo,
5606                          clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin);
5607   }
5608 
5609   bool validateAsmConstraint(const char *&Name,
5610                              TargetInfo::ConstraintInfo &Info) const override {
5611     return true;
5612   }
5613 
5614   void getTargetDefines(const LangOptions &Opts,
5615                         MacroBuilder &Builder) const override;
5616 
5617   bool hasFeature(StringRef Feature) const override {
5618     return Feature == "hexagon";
5619   }
5620 
5621   BuiltinVaListKind getBuiltinVaListKind() const override {
5622     return TargetInfo::CharPtrBuiltinVaList;
5623   }
5624   ArrayRef<const char *> getGCCRegNames() const override;
5625   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
5626   const char *getClobbers() const override {
5627     return "";
5628   }
5629 
5630   static const char *getHexagonCPUSuffix(StringRef Name) {
5631     return llvm::StringSwitch<const char*>(Name)
5632       .Case("hexagonv4", "4")
5633       .Case("hexagonv5", "5")
5634       .Default(nullptr);
5635   }
5636 
5637   bool setCPU(const std::string &Name) override {
5638     if (!getHexagonCPUSuffix(Name))
5639       return false;
5640 
5641     CPU = Name;
5642     return true;
5643   }
5644 };
5645 
5646 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
5647                                 MacroBuilder &Builder) const {
5648   Builder.defineMacro("qdsp6");
5649   Builder.defineMacro("__qdsp6", "1");
5650   Builder.defineMacro("__qdsp6__", "1");
5651 
5652   Builder.defineMacro("hexagon");
5653   Builder.defineMacro("__hexagon", "1");
5654   Builder.defineMacro("__hexagon__", "1");
5655 
5656   if(CPU == "hexagonv1") {
5657     Builder.defineMacro("__HEXAGON_V1__");
5658     Builder.defineMacro("__HEXAGON_ARCH__", "1");
5659     if(Opts.HexagonQdsp6Compat) {
5660       Builder.defineMacro("__QDSP6_V1__");
5661       Builder.defineMacro("__QDSP6_ARCH__", "1");
5662     }
5663   }
5664   else if(CPU == "hexagonv2") {
5665     Builder.defineMacro("__HEXAGON_V2__");
5666     Builder.defineMacro("__HEXAGON_ARCH__", "2");
5667     if(Opts.HexagonQdsp6Compat) {
5668       Builder.defineMacro("__QDSP6_V2__");
5669       Builder.defineMacro("__QDSP6_ARCH__", "2");
5670     }
5671   }
5672   else if(CPU == "hexagonv3") {
5673     Builder.defineMacro("__HEXAGON_V3__");
5674     Builder.defineMacro("__HEXAGON_ARCH__", "3");
5675     if(Opts.HexagonQdsp6Compat) {
5676       Builder.defineMacro("__QDSP6_V3__");
5677       Builder.defineMacro("__QDSP6_ARCH__", "3");
5678     }
5679   }
5680   else if(CPU == "hexagonv4") {
5681     Builder.defineMacro("__HEXAGON_V4__");
5682     Builder.defineMacro("__HEXAGON_ARCH__", "4");
5683     if(Opts.HexagonQdsp6Compat) {
5684       Builder.defineMacro("__QDSP6_V4__");
5685       Builder.defineMacro("__QDSP6_ARCH__", "4");
5686     }
5687   }
5688   else if(CPU == "hexagonv5") {
5689     Builder.defineMacro("__HEXAGON_V5__");
5690     Builder.defineMacro("__HEXAGON_ARCH__", "5");
5691     if(Opts.HexagonQdsp6Compat) {
5692       Builder.defineMacro("__QDSP6_V5__");
5693       Builder.defineMacro("__QDSP6_ARCH__", "5");
5694     }
5695   }
5696 }
5697 
5698 const char * const HexagonTargetInfo::GCCRegNames[] = {
5699   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5700   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5701   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5702   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
5703   "p0", "p1", "p2", "p3",
5704   "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
5705 };
5706 
5707 ArrayRef<const char *> HexagonTargetInfo::getGCCRegNames() const {
5708   return llvm::makeArrayRef(GCCRegNames);
5709 }
5710 
5711 
5712 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
5713   { { "sp" }, "r29" },
5714   { { "fp" }, "r30" },
5715   { { "lr" }, "r31" },
5716  };
5717 
5718 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const {
5719   return llvm::makeArrayRef(GCCRegAliases);
5720 }
5721 
5722 
5723 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
5724 #define BUILTIN(ID, TYPE, ATTRS) \
5725   { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
5726 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
5727   { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
5728 #include "clang/Basic/BuiltinsHexagon.def"
5729 };
5730 
5731 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
5732 class SparcTargetInfo : public TargetInfo {
5733   static const TargetInfo::GCCRegAlias GCCRegAliases[];
5734   static const char * const GCCRegNames[];
5735   bool SoftFloat;
5736 public:
5737   SparcTargetInfo(const llvm::Triple &Triple)
5738       : TargetInfo(Triple), SoftFloat(false) {}
5739 
5740   bool handleTargetFeatures(std::vector<std::string> &Features,
5741                             DiagnosticsEngine &Diags) override {
5742     // The backend doesn't actually handle soft float yet, but in case someone
5743     // is using the support for the front end continue to support it.
5744     auto Feature = std::find(Features.begin(), Features.end(), "+soft-float");
5745     if (Feature != Features.end()) {
5746       SoftFloat = true;
5747       Features.erase(Feature);
5748     }
5749     return true;
5750   }
5751   void getTargetDefines(const LangOptions &Opts,
5752                         MacroBuilder &Builder) const override {
5753     DefineStd(Builder, "sparc", Opts);
5754     Builder.defineMacro("__REGISTER_PREFIX__", "");
5755 
5756     if (SoftFloat)
5757       Builder.defineMacro("SOFT_FLOAT", "1");
5758   }
5759 
5760   bool hasFeature(StringRef Feature) const override {
5761     return llvm::StringSwitch<bool>(Feature)
5762              .Case("softfloat", SoftFloat)
5763              .Case("sparc", true)
5764              .Default(false);
5765   }
5766 
5767   ArrayRef<Builtin::Info> getTargetBuiltins() const override {
5768     // FIXME: Implement!
5769     return None;
5770   }
5771   BuiltinVaListKind getBuiltinVaListKind() const override {
5772     return TargetInfo::VoidPtrBuiltinVaList;
5773   }
5774   ArrayRef<const char *> getGCCRegNames() const override;
5775   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
5776   bool validateAsmConstraint(const char *&Name,
5777                              TargetInfo::ConstraintInfo &info) const override {
5778     // FIXME: Implement!
5779     switch (*Name) {
5780     case 'I': // Signed 13-bit constant
5781     case 'J': // Zero
5782     case 'K': // 32-bit constant with the low 12 bits clear
5783     case 'L': // A constant in the range supported by movcc (11-bit signed imm)
5784     case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
5785     case 'N': // Same as 'K' but zext (required for SIMode)
5786     case 'O': // The constant 4096
5787       return true;
5788     }
5789     return false;
5790   }
5791   const char *getClobbers() const override {
5792     // FIXME: Implement!
5793     return "";
5794   }
5795 
5796   // No Sparc V7 for now, the backend doesn't support it anyway.
5797   enum CPUKind {
5798     CK_GENERIC,
5799     CK_V8,
5800     CK_SUPERSPARC,
5801     CK_SPARCLITE,
5802     CK_F934,
5803     CK_HYPERSPARC,
5804     CK_SPARCLITE86X,
5805     CK_SPARCLET,
5806     CK_TSC701,
5807     CK_V9,
5808     CK_ULTRASPARC,
5809     CK_ULTRASPARC3,
5810     CK_NIAGARA,
5811     CK_NIAGARA2,
5812     CK_NIAGARA3,
5813     CK_NIAGARA4
5814   } CPU = CK_GENERIC;
5815 
5816   enum CPUGeneration {
5817     CG_V8,
5818     CG_V9,
5819   };
5820 
5821   CPUGeneration getCPUGeneration(CPUKind Kind) const {
5822     switch (Kind) {
5823     case CK_GENERIC:
5824     case CK_V8:
5825     case CK_SUPERSPARC:
5826     case CK_SPARCLITE:
5827     case CK_F934:
5828     case CK_HYPERSPARC:
5829     case CK_SPARCLITE86X:
5830     case CK_SPARCLET:
5831     case CK_TSC701:
5832       return CG_V8;
5833     case CK_V9:
5834     case CK_ULTRASPARC:
5835     case CK_ULTRASPARC3:
5836     case CK_NIAGARA:
5837     case CK_NIAGARA2:
5838     case CK_NIAGARA3:
5839     case CK_NIAGARA4:
5840       return CG_V9;
5841     }
5842     llvm_unreachable("Unexpected CPU kind");
5843   }
5844 
5845   CPUKind getCPUKind(StringRef Name) const {
5846     return llvm::StringSwitch<CPUKind>(Name)
5847         .Case("v8", CK_V8)
5848         .Case("supersparc", CK_SUPERSPARC)
5849         .Case("sparclite", CK_SPARCLITE)
5850         .Case("f934", CK_F934)
5851         .Case("hypersparc", CK_HYPERSPARC)
5852         .Case("sparclite86x", CK_SPARCLITE86X)
5853         .Case("sparclet", CK_SPARCLET)
5854         .Case("tsc701", CK_TSC701)
5855         .Case("v9", CK_V9)
5856         .Case("ultrasparc", CK_ULTRASPARC)
5857         .Case("ultrasparc3", CK_ULTRASPARC3)
5858         .Case("niagara", CK_NIAGARA)
5859         .Case("niagara2", CK_NIAGARA2)
5860         .Case("niagara3", CK_NIAGARA3)
5861         .Case("niagara4", CK_NIAGARA4)
5862         .Default(CK_GENERIC);
5863   }
5864 
5865   bool setCPU(const std::string &Name) override {
5866     CPU = getCPUKind(Name);
5867     return CPU != CK_GENERIC;
5868   }
5869 };
5870 
5871 const char * const SparcTargetInfo::GCCRegNames[] = {
5872   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5873   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5874   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5875   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5876 };
5877 
5878 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const {
5879   return llvm::makeArrayRef(GCCRegNames);
5880 }
5881 
5882 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
5883   { { "g0" }, "r0" },
5884   { { "g1" }, "r1" },
5885   { { "g2" }, "r2" },
5886   { { "g3" }, "r3" },
5887   { { "g4" }, "r4" },
5888   { { "g5" }, "r5" },
5889   { { "g6" }, "r6" },
5890   { { "g7" }, "r7" },
5891   { { "o0" }, "r8" },
5892   { { "o1" }, "r9" },
5893   { { "o2" }, "r10" },
5894   { { "o3" }, "r11" },
5895   { { "o4" }, "r12" },
5896   { { "o5" }, "r13" },
5897   { { "o6", "sp" }, "r14" },
5898   { { "o7" }, "r15" },
5899   { { "l0" }, "r16" },
5900   { { "l1" }, "r17" },
5901   { { "l2" }, "r18" },
5902   { { "l3" }, "r19" },
5903   { { "l4" }, "r20" },
5904   { { "l5" }, "r21" },
5905   { { "l6" }, "r22" },
5906   { { "l7" }, "r23" },
5907   { { "i0" }, "r24" },
5908   { { "i1" }, "r25" },
5909   { { "i2" }, "r26" },
5910   { { "i3" }, "r27" },
5911   { { "i4" }, "r28" },
5912   { { "i5" }, "r29" },
5913   { { "i6", "fp" }, "r30" },
5914   { { "i7" }, "r31" },
5915 };
5916 
5917 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const {
5918   return llvm::makeArrayRef(GCCRegAliases);
5919 }
5920 
5921 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
5922 class SparcV8TargetInfo : public SparcTargetInfo {
5923 public:
5924   SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5925     DataLayoutString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
5926     // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int.
5927     switch (getTriple().getOS()) {
5928     default:
5929       SizeType = UnsignedInt;
5930       IntPtrType = SignedInt;
5931       PtrDiffType = SignedInt;
5932       break;
5933     case llvm::Triple::NetBSD:
5934     case llvm::Triple::OpenBSD:
5935       SizeType = UnsignedLong;
5936       IntPtrType = SignedLong;
5937       PtrDiffType = SignedLong;
5938       break;
5939     }
5940   }
5941 
5942   void getTargetDefines(const LangOptions &Opts,
5943                         MacroBuilder &Builder) const override {
5944     SparcTargetInfo::getTargetDefines(Opts, Builder);
5945     switch (getCPUGeneration(CPU)) {
5946     case CG_V8:
5947       Builder.defineMacro("__sparcv8");
5948       if (getTriple().getOS() != llvm::Triple::Solaris)
5949         Builder.defineMacro("__sparcv8__");
5950       break;
5951     case CG_V9:
5952       Builder.defineMacro("__sparcv9");
5953       if (getTriple().getOS() != llvm::Triple::Solaris) {
5954         Builder.defineMacro("__sparcv9__");
5955         Builder.defineMacro("__sparc_v9__");
5956       }
5957       break;
5958     }
5959   }
5960 };
5961 
5962 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel.
5963 class SparcV8elTargetInfo : public SparcV8TargetInfo {
5964  public:
5965   SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) {
5966     DataLayoutString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64";
5967     BigEndian = false;
5968   }
5969 };
5970 
5971 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
5972 class SparcV9TargetInfo : public SparcTargetInfo {
5973 public:
5974   SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5975     // FIXME: Support Sparc quad-precision long double?
5976     DataLayoutString = "E-m:e-i64:64-n32:64-S128";
5977     // This is an LP64 platform.
5978     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5979 
5980     // OpenBSD uses long long for int64_t and intmax_t.
5981     if (getTriple().getOS() == llvm::Triple::OpenBSD)
5982       IntMaxType = SignedLongLong;
5983     else
5984       IntMaxType = SignedLong;
5985     Int64Type = IntMaxType;
5986 
5987     // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
5988     // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
5989     LongDoubleWidth = 128;
5990     LongDoubleAlign = 128;
5991     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5992     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5993   }
5994 
5995   void getTargetDefines(const LangOptions &Opts,
5996                         MacroBuilder &Builder) const override {
5997     SparcTargetInfo::getTargetDefines(Opts, Builder);
5998     Builder.defineMacro("__sparcv9");
5999     Builder.defineMacro("__arch64__");
6000     // Solaris doesn't need these variants, but the BSDs do.
6001     if (getTriple().getOS() != llvm::Triple::Solaris) {
6002       Builder.defineMacro("__sparc64__");
6003       Builder.defineMacro("__sparc_v9__");
6004       Builder.defineMacro("__sparcv9__");
6005     }
6006   }
6007 
6008   bool setCPU(const std::string &Name) override {
6009     if (!SparcTargetInfo::setCPU(Name))
6010       return false;
6011     return getCPUGeneration(CPU) == CG_V9;
6012   }
6013 };
6014 
6015 class SystemZTargetInfo : public TargetInfo {
6016   static const Builtin::Info BuiltinInfo[];
6017   static const char *const GCCRegNames[];
6018   std::string CPU;
6019   bool HasTransactionalExecution;
6020   bool HasVector;
6021 
6022 public:
6023   SystemZTargetInfo(const llvm::Triple &Triple)
6024       : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false),
6025         HasVector(false) {
6026     IntMaxType = SignedLong;
6027     Int64Type = SignedLong;
6028     TLSSupported = true;
6029     IntWidth = IntAlign = 32;
6030     LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
6031     PointerWidth = PointerAlign = 64;
6032     LongDoubleWidth = 128;
6033     LongDoubleAlign = 64;
6034     LongDoubleFormat = &llvm::APFloat::IEEEquad;
6035     DefaultAlignForAttributeAligned = 64;
6036     MinGlobalAlign = 16;
6037     DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
6038     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6039   }
6040   void getTargetDefines(const LangOptions &Opts,
6041                         MacroBuilder &Builder) const override {
6042     Builder.defineMacro("__s390__");
6043     Builder.defineMacro("__s390x__");
6044     Builder.defineMacro("__zarch__");
6045     Builder.defineMacro("__LONG_DOUBLE_128__");
6046     if (HasTransactionalExecution)
6047       Builder.defineMacro("__HTM__");
6048     if (Opts.ZVector)
6049       Builder.defineMacro("__VEC__", "10301");
6050   }
6051   ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6052     return llvm::makeArrayRef(BuiltinInfo,
6053                          clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin);
6054   }
6055 
6056   ArrayRef<const char *> getGCCRegNames() const override;
6057   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6058     // No aliases.
6059     return None;
6060   }
6061   bool validateAsmConstraint(const char *&Name,
6062                              TargetInfo::ConstraintInfo &info) const override;
6063   const char *getClobbers() const override {
6064     // FIXME: Is this really right?
6065     return "";
6066   }
6067   BuiltinVaListKind getBuiltinVaListKind() const override {
6068     return TargetInfo::SystemZBuiltinVaList;
6069   }
6070   bool setCPU(const std::string &Name) override {
6071     CPU = Name;
6072     bool CPUKnown = llvm::StringSwitch<bool>(Name)
6073       .Case("z10", true)
6074       .Case("z196", true)
6075       .Case("zEC12", true)
6076       .Case("z13", true)
6077       .Default(false);
6078 
6079     return CPUKnown;
6080   }
6081   bool
6082   initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
6083                  StringRef CPU,
6084                  const std::vector<std::string> &FeaturesVec) const override {
6085     if (CPU == "zEC12")
6086       Features["transactional-execution"] = true;
6087     if (CPU == "z13") {
6088       Features["transactional-execution"] = true;
6089       Features["vector"] = true;
6090     }
6091     return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
6092   }
6093 
6094   bool handleTargetFeatures(std::vector<std::string> &Features,
6095                             DiagnosticsEngine &Diags) override {
6096     HasTransactionalExecution = false;
6097     for (const auto &Feature : Features) {
6098       if (Feature == "+transactional-execution")
6099         HasTransactionalExecution = true;
6100       else if (Feature == "+vector")
6101         HasVector = true;
6102     }
6103     // If we use the vector ABI, vector types are 64-bit aligned.
6104     if (HasVector) {
6105       MaxVectorAlign = 64;
6106       DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64"
6107                          "-v128:64-a:8:16-n32:64";
6108     }
6109     return true;
6110   }
6111 
6112   bool hasFeature(StringRef Feature) const override {
6113     return llvm::StringSwitch<bool>(Feature)
6114         .Case("systemz", true)
6115         .Case("htm", HasTransactionalExecution)
6116         .Case("vx", HasVector)
6117         .Default(false);
6118   }
6119 
6120   StringRef getABI() const override {
6121     if (HasVector)
6122       return "vector";
6123     return "";
6124   }
6125 
6126   bool useFloat128ManglingForLongDouble() const override {
6127     return true;
6128   }
6129 };
6130 
6131 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = {
6132 #define BUILTIN(ID, TYPE, ATTRS)                                               \
6133   { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6134 #include "clang/Basic/BuiltinsSystemZ.def"
6135 };
6136 
6137 const char *const SystemZTargetInfo::GCCRegNames[] = {
6138   "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
6139   "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
6140   "f0",  "f2",  "f4",  "f6",  "f1",  "f3",  "f5",  "f7",
6141   "f8",  "f10", "f12", "f14", "f9",  "f11", "f13", "f15"
6142 };
6143 
6144 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const {
6145   return llvm::makeArrayRef(GCCRegNames);
6146 }
6147 
6148 bool SystemZTargetInfo::
6149 validateAsmConstraint(const char *&Name,
6150                       TargetInfo::ConstraintInfo &Info) const {
6151   switch (*Name) {
6152   default:
6153     return false;
6154 
6155   case 'a': // Address register
6156   case 'd': // Data register (equivalent to 'r')
6157   case 'f': // Floating-point register
6158     Info.setAllowsRegister();
6159     return true;
6160 
6161   case 'I': // Unsigned 8-bit constant
6162   case 'J': // Unsigned 12-bit constant
6163   case 'K': // Signed 16-bit constant
6164   case 'L': // Signed 20-bit displacement (on all targets we support)
6165   case 'M': // 0x7fffffff
6166     return true;
6167 
6168   case 'Q': // Memory with base and unsigned 12-bit displacement
6169   case 'R': // Likewise, plus an index
6170   case 'S': // Memory with base and signed 20-bit displacement
6171   case 'T': // Likewise, plus an index
6172     Info.setAllowsMemory();
6173     return true;
6174   }
6175 }
6176 
6177 class MSP430TargetInfo : public TargetInfo {
6178   static const char *const GCCRegNames[];
6179 
6180 public:
6181   MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6182     BigEndian = false;
6183     TLSSupported = false;
6184     IntWidth = 16;
6185     IntAlign = 16;
6186     LongWidth = 32;
6187     LongLongWidth = 64;
6188     LongAlign = LongLongAlign = 16;
6189     PointerWidth = 16;
6190     PointerAlign = 16;
6191     SuitableAlign = 16;
6192     SizeType = UnsignedInt;
6193     IntMaxType = SignedLongLong;
6194     IntPtrType = SignedInt;
6195     PtrDiffType = SignedInt;
6196     SigAtomicType = SignedLong;
6197     DataLayoutString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16";
6198   }
6199   void getTargetDefines(const LangOptions &Opts,
6200                         MacroBuilder &Builder) const override {
6201     Builder.defineMacro("MSP430");
6202     Builder.defineMacro("__MSP430__");
6203     // FIXME: defines for different 'flavours' of MCU
6204   }
6205   ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6206     // FIXME: Implement.
6207     return None;
6208   }
6209   bool hasFeature(StringRef Feature) const override {
6210     return Feature == "msp430";
6211   }
6212   ArrayRef<const char *> getGCCRegNames() const override;
6213   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6214     // No aliases.
6215     return None;
6216   }
6217   bool validateAsmConstraint(const char *&Name,
6218                              TargetInfo::ConstraintInfo &info) const override {
6219     // FIXME: implement
6220     switch (*Name) {
6221     case 'K': // the constant 1
6222     case 'L': // constant -1^20 .. 1^19
6223     case 'M': // constant 1-4:
6224       return true;
6225     }
6226     // No target constraints for now.
6227     return false;
6228   }
6229   const char *getClobbers() const override {
6230     // FIXME: Is this really right?
6231     return "";
6232   }
6233   BuiltinVaListKind getBuiltinVaListKind() const override {
6234     // FIXME: implement
6235     return TargetInfo::CharPtrBuiltinVaList;
6236   }
6237 };
6238 
6239 const char *const MSP430TargetInfo::GCCRegNames[] = {
6240     "r0", "r1", "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
6241     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"};
6242 
6243 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const {
6244   return llvm::makeArrayRef(GCCRegNames);
6245 }
6246 
6247 // LLVM and Clang cannot be used directly to output native binaries for
6248 // target, but is used to compile C code to llvm bitcode with correct
6249 // type and alignment information.
6250 //
6251 // TCE uses the llvm bitcode as input and uses it for generating customized
6252 // target processor and program binary. TCE co-design environment is
6253 // publicly available in http://tce.cs.tut.fi
6254 
6255 static const unsigned TCEOpenCLAddrSpaceMap[] = {
6256     3, // opencl_global
6257     4, // opencl_local
6258     5, // opencl_constant
6259     // FIXME: generic has to be added to the target
6260     0, // opencl_generic
6261     0, // cuda_device
6262     0, // cuda_constant
6263     0  // cuda_shared
6264 };
6265 
6266 class TCETargetInfo : public TargetInfo {
6267 public:
6268   TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6269     TLSSupported = false;
6270     IntWidth = 32;
6271     LongWidth = LongLongWidth = 32;
6272     PointerWidth = 32;
6273     IntAlign = 32;
6274     LongAlign = LongLongAlign = 32;
6275     PointerAlign = 32;
6276     SuitableAlign = 32;
6277     SizeType = UnsignedInt;
6278     IntMaxType = SignedLong;
6279     IntPtrType = SignedInt;
6280     PtrDiffType = SignedInt;
6281     FloatWidth = 32;
6282     FloatAlign = 32;
6283     DoubleWidth = 32;
6284     DoubleAlign = 32;
6285     LongDoubleWidth = 32;
6286     LongDoubleAlign = 32;
6287     FloatFormat = &llvm::APFloat::IEEEsingle;
6288     DoubleFormat = &llvm::APFloat::IEEEsingle;
6289     LongDoubleFormat = &llvm::APFloat::IEEEsingle;
6290     DataLayoutString = "E-p:32:32-i8:8:32-i16:16:32-i64:32"
6291                        "-f64:32-v64:32-v128:32-a:0:32-n32";
6292     AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
6293     UseAddrSpaceMapMangling = true;
6294   }
6295 
6296   void getTargetDefines(const LangOptions &Opts,
6297                         MacroBuilder &Builder) const override {
6298     DefineStd(Builder, "tce", Opts);
6299     Builder.defineMacro("__TCE__");
6300     Builder.defineMacro("__TCE_V1__");
6301   }
6302   bool hasFeature(StringRef Feature) const override { return Feature == "tce"; }
6303 
6304   ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
6305   const char *getClobbers() const override { return ""; }
6306   BuiltinVaListKind getBuiltinVaListKind() const override {
6307     return TargetInfo::VoidPtrBuiltinVaList;
6308   }
6309   ArrayRef<const char *> getGCCRegNames() const override { return None; }
6310   bool validateAsmConstraint(const char *&Name,
6311                              TargetInfo::ConstraintInfo &info) const override {
6312     return true;
6313   }
6314   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6315     return None;
6316   }
6317 };
6318 
6319 class BPFTargetInfo : public TargetInfo {
6320 public:
6321   BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6322     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6323     SizeType    = UnsignedLong;
6324     PtrDiffType = SignedLong;
6325     IntPtrType  = SignedLong;
6326     IntMaxType  = SignedLong;
6327     Int64Type   = SignedLong;
6328     RegParmMax = 5;
6329     if (Triple.getArch() == llvm::Triple::bpfeb) {
6330       BigEndian = true;
6331       DataLayoutString = "E-m:e-p:64:64-i64:64-n32:64-S128";
6332     } else {
6333       BigEndian = false;
6334       DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128";
6335     }
6336     MaxAtomicPromoteWidth = 64;
6337     MaxAtomicInlineWidth = 64;
6338     TLSSupported = false;
6339   }
6340   void getTargetDefines(const LangOptions &Opts,
6341                         MacroBuilder &Builder) const override {
6342     DefineStd(Builder, "bpf", Opts);
6343     Builder.defineMacro("__BPF__");
6344   }
6345   bool hasFeature(StringRef Feature) const override {
6346     return Feature == "bpf";
6347   }
6348 
6349   ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
6350   const char *getClobbers() const override {
6351     return "";
6352   }
6353   BuiltinVaListKind getBuiltinVaListKind() const override {
6354     return TargetInfo::VoidPtrBuiltinVaList;
6355   }
6356   ArrayRef<const char *> getGCCRegNames() const override {
6357     return None;
6358   }
6359   bool validateAsmConstraint(const char *&Name,
6360                              TargetInfo::ConstraintInfo &info) const override {
6361     return true;
6362   }
6363   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6364     return None;
6365   }
6366 };
6367 
6368 class MipsTargetInfoBase : public TargetInfo {
6369   virtual void setDataLayoutString() = 0;
6370 
6371   static const Builtin::Info BuiltinInfo[];
6372   std::string CPU;
6373   bool IsMips16;
6374   bool IsMicromips;
6375   bool IsNan2008;
6376   bool IsSingleFloat;
6377   enum MipsFloatABI {
6378     HardFloat, SoftFloat
6379   } FloatABI;
6380   enum DspRevEnum {
6381     NoDSP, DSP1, DSP2
6382   } DspRev;
6383   bool HasMSA;
6384 
6385 protected:
6386   bool HasFP64;
6387   std::string ABI;
6388 
6389 public:
6390   MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
6391                      const std::string &CPUStr)
6392       : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
6393         IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
6394         DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {
6395     TheCXXABI.set(TargetCXXABI::GenericMIPS);
6396   }
6397 
6398   bool isNaN2008Default() const {
6399     return CPU == "mips32r6" || CPU == "mips64r6";
6400   }
6401 
6402   bool isFP64Default() const {
6403     return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
6404   }
6405 
6406   bool isNan2008() const override {
6407     return IsNan2008;
6408   }
6409 
6410   StringRef getABI() const override { return ABI; }
6411   bool setCPU(const std::string &Name) override {
6412     bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
6413                     getTriple().getArch() == llvm::Triple::mipsel;
6414     CPU = Name;
6415     return llvm::StringSwitch<bool>(Name)
6416         .Case("mips1", IsMips32)
6417         .Case("mips2", IsMips32)
6418         .Case("mips3", true)
6419         .Case("mips4", true)
6420         .Case("mips5", true)
6421         .Case("mips32", IsMips32)
6422         .Case("mips32r2", IsMips32)
6423         .Case("mips32r3", IsMips32)
6424         .Case("mips32r5", IsMips32)
6425         .Case("mips32r6", IsMips32)
6426         .Case("mips64", true)
6427         .Case("mips64r2", true)
6428         .Case("mips64r3", true)
6429         .Case("mips64r5", true)
6430         .Case("mips64r6", true)
6431         .Case("octeon", true)
6432         .Case("p5600", true)
6433         .Default(false);
6434   }
6435   const std::string& getCPU() const { return CPU; }
6436   bool
6437   initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
6438                  StringRef CPU,
6439                  const std::vector<std::string> &FeaturesVec) const override {
6440     if (CPU == "octeon")
6441       Features["mips64r2"] = Features["cnmips"] = true;
6442     else
6443       Features[CPU] = true;
6444     return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
6445   }
6446 
6447   void getTargetDefines(const LangOptions &Opts,
6448                         MacroBuilder &Builder) const override {
6449     Builder.defineMacro("__mips__");
6450     Builder.defineMacro("_mips");
6451     if (Opts.GNUMode)
6452       Builder.defineMacro("mips");
6453 
6454     Builder.defineMacro("__REGISTER_PREFIX__", "");
6455 
6456     switch (FloatABI) {
6457     case HardFloat:
6458       Builder.defineMacro("__mips_hard_float", Twine(1));
6459       break;
6460     case SoftFloat:
6461       Builder.defineMacro("__mips_soft_float", Twine(1));
6462       break;
6463     }
6464 
6465     if (IsSingleFloat)
6466       Builder.defineMacro("__mips_single_float", Twine(1));
6467 
6468     Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
6469     Builder.defineMacro("_MIPS_FPSET",
6470                         Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
6471 
6472     if (IsMips16)
6473       Builder.defineMacro("__mips16", Twine(1));
6474 
6475     if (IsMicromips)
6476       Builder.defineMacro("__mips_micromips", Twine(1));
6477 
6478     if (IsNan2008)
6479       Builder.defineMacro("__mips_nan2008", Twine(1));
6480 
6481     switch (DspRev) {
6482     default:
6483       break;
6484     case DSP1:
6485       Builder.defineMacro("__mips_dsp_rev", Twine(1));
6486       Builder.defineMacro("__mips_dsp", Twine(1));
6487       break;
6488     case DSP2:
6489       Builder.defineMacro("__mips_dsp_rev", Twine(2));
6490       Builder.defineMacro("__mips_dspr2", Twine(1));
6491       Builder.defineMacro("__mips_dsp", Twine(1));
6492       break;
6493     }
6494 
6495     if (HasMSA)
6496       Builder.defineMacro("__mips_msa", Twine(1));
6497 
6498     Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
6499     Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
6500     Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
6501 
6502     Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
6503     Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
6504   }
6505 
6506   ArrayRef<Builtin::Info> getTargetBuiltins() const override {
6507     return llvm::makeArrayRef(BuiltinInfo,
6508                           clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin);
6509   }
6510   bool hasFeature(StringRef Feature) const override {
6511     return llvm::StringSwitch<bool>(Feature)
6512       .Case("mips", true)
6513       .Case("fp64", HasFP64)
6514       .Default(false);
6515   }
6516   BuiltinVaListKind getBuiltinVaListKind() const override {
6517     return TargetInfo::VoidPtrBuiltinVaList;
6518   }
6519   ArrayRef<const char *> getGCCRegNames() const override {
6520     static const char *const GCCRegNames[] = {
6521       // CPU register names
6522       // Must match second column of GCCRegAliases
6523       "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
6524       "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
6525       "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
6526       "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
6527       // Floating point register names
6528       "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
6529       "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
6530       "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
6531       "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
6532       // Hi/lo and condition register names
6533       "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
6534       "$fcc5","$fcc6","$fcc7",
6535       // MSA register names
6536       "$w0",  "$w1",  "$w2",  "$w3",  "$w4",  "$w5",  "$w6",  "$w7",
6537       "$w8",  "$w9",  "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
6538       "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
6539       "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
6540       // MSA control register names
6541       "$msair",      "$msacsr", "$msaaccess", "$msasave", "$msamodify",
6542       "$msarequest", "$msamap", "$msaunmap"
6543     };
6544     return llvm::makeArrayRef(GCCRegNames);
6545   }
6546   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override = 0;
6547   bool validateAsmConstraint(const char *&Name,
6548                              TargetInfo::ConstraintInfo &Info) const override {
6549     switch (*Name) {
6550     default:
6551       return false;
6552     case 'r': // CPU registers.
6553     case 'd': // Equivalent to "r" unless generating MIPS16 code.
6554     case 'y': // Equivalent to "r", backward compatibility only.
6555     case 'f': // floating-point registers.
6556     case 'c': // $25 for indirect jumps
6557     case 'l': // lo register
6558     case 'x': // hilo register pair
6559       Info.setAllowsRegister();
6560       return true;
6561     case 'I': // Signed 16-bit constant
6562     case 'J': // Integer 0
6563     case 'K': // Unsigned 16-bit constant
6564     case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
6565     case 'M': // Constants not loadable via lui, addiu, or ori
6566     case 'N': // Constant -1 to -65535
6567     case 'O': // A signed 15-bit constant
6568     case 'P': // A constant between 1 go 65535
6569       return true;
6570     case 'R': // An address that can be used in a non-macro load or store
6571       Info.setAllowsMemory();
6572       return true;
6573     case 'Z':
6574       if (Name[1] == 'C') { // An address usable by ll, and sc.
6575         Info.setAllowsMemory();
6576         Name++; // Skip over 'Z'.
6577         return true;
6578       }
6579       return false;
6580     }
6581   }
6582 
6583   std::string convertConstraint(const char *&Constraint) const override {
6584     std::string R;
6585     switch (*Constraint) {
6586     case 'Z': // Two-character constraint; add "^" hint for later parsing.
6587       if (Constraint[1] == 'C') {
6588         R = std::string("^") + std::string(Constraint, 2);
6589         Constraint++;
6590         return R;
6591       }
6592       break;
6593     }
6594     return TargetInfo::convertConstraint(Constraint);
6595   }
6596 
6597   const char *getClobbers() const override {
6598     // In GCC, $1 is not widely used in generated code (it's used only in a few
6599     // specific situations), so there is no real need for users to add it to
6600     // the clobbers list if they want to use it in their inline assembly code.
6601     //
6602     // In LLVM, $1 is treated as a normal GPR and is always allocatable during
6603     // code generation, so using it in inline assembly without adding it to the
6604     // clobbers list can cause conflicts between the inline assembly code and
6605     // the surrounding generated code.
6606     //
6607     // Another problem is that LLVM is allowed to choose $1 for inline assembly
6608     // operands, which will conflict with the ".set at" assembler option (which
6609     // we use only for inline assembly, in order to maintain compatibility with
6610     // GCC) and will also conflict with the user's usage of $1.
6611     //
6612     // The easiest way to avoid these conflicts and keep $1 as an allocatable
6613     // register for generated code is to automatically clobber $1 for all inline
6614     // assembly code.
6615     //
6616     // FIXME: We should automatically clobber $1 only for inline assembly code
6617     // which actually uses it. This would allow LLVM to use $1 for inline
6618     // assembly operands if the user's assembly code doesn't use it.
6619     return "~{$1}";
6620   }
6621 
6622   bool handleTargetFeatures(std::vector<std::string> &Features,
6623                             DiagnosticsEngine &Diags) override {
6624     IsMips16 = false;
6625     IsMicromips = false;
6626     IsNan2008 = isNaN2008Default();
6627     IsSingleFloat = false;
6628     FloatABI = HardFloat;
6629     DspRev = NoDSP;
6630     HasFP64 = isFP64Default();
6631 
6632     for (const auto &Feature : Features) {
6633       if (Feature == "+single-float")
6634         IsSingleFloat = true;
6635       else if (Feature == "+soft-float")
6636         FloatABI = SoftFloat;
6637       else if (Feature == "+mips16")
6638         IsMips16 = true;
6639       else if (Feature == "+micromips")
6640         IsMicromips = true;
6641       else if (Feature == "+dsp")
6642         DspRev = std::max(DspRev, DSP1);
6643       else if (Feature == "+dspr2")
6644         DspRev = std::max(DspRev, DSP2);
6645       else if (Feature == "+msa")
6646         HasMSA = true;
6647       else if (Feature == "+fp64")
6648         HasFP64 = true;
6649       else if (Feature == "-fp64")
6650         HasFP64 = false;
6651       else if (Feature == "+nan2008")
6652         IsNan2008 = true;
6653       else if (Feature == "-nan2008")
6654         IsNan2008 = false;
6655     }
6656 
6657     setDataLayoutString();
6658 
6659     return true;
6660   }
6661 
6662   int getEHDataRegisterNumber(unsigned RegNo) const override {
6663     if (RegNo == 0) return 4;
6664     if (RegNo == 1) return 5;
6665     return -1;
6666   }
6667 
6668   bool isCLZForZeroUndef() const override { return false; }
6669 };
6670 
6671 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
6672 #define BUILTIN(ID, TYPE, ATTRS) \
6673   { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
6674 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
6675   { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
6676 #include "clang/Basic/BuiltinsMips.def"
6677 };
6678 
6679 class Mips32TargetInfoBase : public MipsTargetInfoBase {
6680 public:
6681   Mips32TargetInfoBase(const llvm::Triple &Triple)
6682       : MipsTargetInfoBase(Triple, "o32", "mips32r2") {
6683     SizeType = UnsignedInt;
6684     PtrDiffType = SignedInt;
6685     Int64Type = SignedLongLong;
6686     IntMaxType = Int64Type;
6687     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
6688   }
6689   bool setABI(const std::string &Name) override {
6690     if (Name == "o32" || Name == "eabi") {
6691       ABI = Name;
6692       return true;
6693     }
6694     return false;
6695   }
6696   void getTargetDefines(const LangOptions &Opts,
6697                         MacroBuilder &Builder) const override {
6698     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6699 
6700     Builder.defineMacro("__mips", "32");
6701     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
6702 
6703     const std::string& CPUStr = getCPU();
6704     if (CPUStr == "mips32")
6705       Builder.defineMacro("__mips_isa_rev", "1");
6706     else if (CPUStr == "mips32r2")
6707       Builder.defineMacro("__mips_isa_rev", "2");
6708     else if (CPUStr == "mips32r3")
6709       Builder.defineMacro("__mips_isa_rev", "3");
6710     else if (CPUStr == "mips32r5")
6711       Builder.defineMacro("__mips_isa_rev", "5");
6712     else if (CPUStr == "mips32r6")
6713       Builder.defineMacro("__mips_isa_rev", "6");
6714 
6715     if (ABI == "o32") {
6716       Builder.defineMacro("__mips_o32");
6717       Builder.defineMacro("_ABIO32", "1");
6718       Builder.defineMacro("_MIPS_SIM", "_ABIO32");
6719     }
6720     else if (ABI == "eabi")
6721       Builder.defineMacro("__mips_eabi");
6722     else
6723       llvm_unreachable("Invalid ABI for Mips32.");
6724   }
6725   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6726     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6727       { { "at" },  "$1" },
6728       { { "v0" },  "$2" },
6729       { { "v1" },  "$3" },
6730       { { "a0" },  "$4" },
6731       { { "a1" },  "$5" },
6732       { { "a2" },  "$6" },
6733       { { "a3" },  "$7" },
6734       { { "t0" },  "$8" },
6735       { { "t1" },  "$9" },
6736       { { "t2" }, "$10" },
6737       { { "t3" }, "$11" },
6738       { { "t4" }, "$12" },
6739       { { "t5" }, "$13" },
6740       { { "t6" }, "$14" },
6741       { { "t7" }, "$15" },
6742       { { "s0" }, "$16" },
6743       { { "s1" }, "$17" },
6744       { { "s2" }, "$18" },
6745       { { "s3" }, "$19" },
6746       { { "s4" }, "$20" },
6747       { { "s5" }, "$21" },
6748       { { "s6" }, "$22" },
6749       { { "s7" }, "$23" },
6750       { { "t8" }, "$24" },
6751       { { "t9" }, "$25" },
6752       { { "k0" }, "$26" },
6753       { { "k1" }, "$27" },
6754       { { "gp" }, "$28" },
6755       { { "sp","$sp" }, "$29" },
6756       { { "fp","$fp" }, "$30" },
6757       { { "ra" }, "$31" }
6758     };
6759     return llvm::makeArrayRef(GCCRegAliases);
6760   }
6761 };
6762 
6763 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
6764   void setDataLayoutString() override {
6765     DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6766   }
6767 
6768 public:
6769   Mips32EBTargetInfo(const llvm::Triple &Triple)
6770       : Mips32TargetInfoBase(Triple) {
6771   }
6772   void getTargetDefines(const LangOptions &Opts,
6773                         MacroBuilder &Builder) const override {
6774     DefineStd(Builder, "MIPSEB", Opts);
6775     Builder.defineMacro("_MIPSEB");
6776     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6777   }
6778 };
6779 
6780 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
6781   void setDataLayoutString() override {
6782     DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6783   }
6784 
6785 public:
6786   Mips32ELTargetInfo(const llvm::Triple &Triple)
6787       : Mips32TargetInfoBase(Triple) {
6788     BigEndian = false;
6789   }
6790   void getTargetDefines(const LangOptions &Opts,
6791                         MacroBuilder &Builder) const override {
6792     DefineStd(Builder, "MIPSEL", Opts);
6793     Builder.defineMacro("_MIPSEL");
6794     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6795   }
6796 };
6797 
6798 class Mips64TargetInfoBase : public MipsTargetInfoBase {
6799 public:
6800   Mips64TargetInfoBase(const llvm::Triple &Triple)
6801       : MipsTargetInfoBase(Triple, "n64", "mips64r2") {
6802     LongDoubleWidth = LongDoubleAlign = 128;
6803     LongDoubleFormat = &llvm::APFloat::IEEEquad;
6804     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
6805       LongDoubleWidth = LongDoubleAlign = 64;
6806       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
6807     }
6808     setN64ABITypes();
6809     SuitableAlign = 128;
6810     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6811   }
6812 
6813   void setN64ABITypes() {
6814     LongWidth = LongAlign = 64;
6815     PointerWidth = PointerAlign = 64;
6816     SizeType = UnsignedLong;
6817     PtrDiffType = SignedLong;
6818     Int64Type = SignedLong;
6819     IntMaxType = Int64Type;
6820   }
6821 
6822   void setN32ABITypes() {
6823     LongWidth = LongAlign = 32;
6824     PointerWidth = PointerAlign = 32;
6825     SizeType = UnsignedInt;
6826     PtrDiffType = SignedInt;
6827     Int64Type = SignedLongLong;
6828     IntMaxType = Int64Type;
6829   }
6830 
6831   bool setABI(const std::string &Name) override {
6832     if (Name == "n32") {
6833       setN32ABITypes();
6834       ABI = Name;
6835       return true;
6836     }
6837     if (Name == "n64") {
6838       setN64ABITypes();
6839       ABI = Name;
6840       return true;
6841     }
6842     return false;
6843   }
6844 
6845   void getTargetDefines(const LangOptions &Opts,
6846                         MacroBuilder &Builder) const override {
6847     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6848 
6849     Builder.defineMacro("__mips", "64");
6850     Builder.defineMacro("__mips64");
6851     Builder.defineMacro("__mips64__");
6852     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
6853 
6854     const std::string& CPUStr = getCPU();
6855     if (CPUStr == "mips64")
6856       Builder.defineMacro("__mips_isa_rev", "1");
6857     else if (CPUStr == "mips64r2")
6858       Builder.defineMacro("__mips_isa_rev", "2");
6859     else if (CPUStr == "mips64r3")
6860       Builder.defineMacro("__mips_isa_rev", "3");
6861     else if (CPUStr == "mips64r5")
6862       Builder.defineMacro("__mips_isa_rev", "5");
6863     else if (CPUStr == "mips64r6")
6864       Builder.defineMacro("__mips_isa_rev", "6");
6865 
6866     if (ABI == "n32") {
6867       Builder.defineMacro("__mips_n32");
6868       Builder.defineMacro("_ABIN32", "2");
6869       Builder.defineMacro("_MIPS_SIM", "_ABIN32");
6870     }
6871     else if (ABI == "n64") {
6872       Builder.defineMacro("__mips_n64");
6873       Builder.defineMacro("_ABI64", "3");
6874       Builder.defineMacro("_MIPS_SIM", "_ABI64");
6875     }
6876     else
6877       llvm_unreachable("Invalid ABI for Mips64.");
6878   }
6879   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
6880     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6881       { { "at" },  "$1" },
6882       { { "v0" },  "$2" },
6883       { { "v1" },  "$3" },
6884       { { "a0" },  "$4" },
6885       { { "a1" },  "$5" },
6886       { { "a2" },  "$6" },
6887       { { "a3" },  "$7" },
6888       { { "a4" },  "$8" },
6889       { { "a5" },  "$9" },
6890       { { "a6" }, "$10" },
6891       { { "a7" }, "$11" },
6892       { { "t0" }, "$12" },
6893       { { "t1" }, "$13" },
6894       { { "t2" }, "$14" },
6895       { { "t3" }, "$15" },
6896       { { "s0" }, "$16" },
6897       { { "s1" }, "$17" },
6898       { { "s2" }, "$18" },
6899       { { "s3" }, "$19" },
6900       { { "s4" }, "$20" },
6901       { { "s5" }, "$21" },
6902       { { "s6" }, "$22" },
6903       { { "s7" }, "$23" },
6904       { { "t8" }, "$24" },
6905       { { "t9" }, "$25" },
6906       { { "k0" }, "$26" },
6907       { { "k1" }, "$27" },
6908       { { "gp" }, "$28" },
6909       { { "sp","$sp" }, "$29" },
6910       { { "fp","$fp" }, "$30" },
6911       { { "ra" }, "$31" }
6912     };
6913     return llvm::makeArrayRef(GCCRegAliases);
6914   }
6915 
6916   bool hasInt128Type() const override { return true; }
6917 };
6918 
6919 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
6920   void setDataLayoutString() override {
6921     if (ABI == "n32")
6922       DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6923     else
6924       DataLayoutString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6925 
6926   }
6927 
6928 public:
6929   Mips64EBTargetInfo(const llvm::Triple &Triple)
6930       : Mips64TargetInfoBase(Triple) {}
6931   void getTargetDefines(const LangOptions &Opts,
6932                         MacroBuilder &Builder) const override {
6933     DefineStd(Builder, "MIPSEB", Opts);
6934     Builder.defineMacro("_MIPSEB");
6935     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6936   }
6937 };
6938 
6939 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
6940   void setDataLayoutString() override {
6941     if (ABI == "n32")
6942       DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6943     else
6944       DataLayoutString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6945   }
6946 public:
6947   Mips64ELTargetInfo(const llvm::Triple &Triple)
6948       : Mips64TargetInfoBase(Triple) {
6949     // Default ABI is n64.
6950     BigEndian = false;
6951   }
6952   void getTargetDefines(const LangOptions &Opts,
6953                         MacroBuilder &Builder) const override {
6954     DefineStd(Builder, "MIPSEL", Opts);
6955     Builder.defineMacro("_MIPSEL");
6956     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6957   }
6958 };
6959 
6960 class PNaClTargetInfo : public TargetInfo {
6961 public:
6962   PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6963     BigEndian = false;
6964     this->UserLabelPrefix = "";
6965     this->LongAlign = 32;
6966     this->LongWidth = 32;
6967     this->PointerAlign = 32;
6968     this->PointerWidth = 32;
6969     this->IntMaxType = TargetInfo::SignedLongLong;
6970     this->Int64Type = TargetInfo::SignedLongLong;
6971     this->DoubleAlign = 64;
6972     this->LongDoubleWidth = 64;
6973     this->LongDoubleAlign = 64;
6974     this->SizeType = TargetInfo::UnsignedInt;
6975     this->PtrDiffType = TargetInfo::SignedInt;
6976     this->IntPtrType = TargetInfo::SignedInt;
6977     this->RegParmMax = 0; // Disallow regparm
6978   }
6979 
6980   void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
6981     Builder.defineMacro("__le32__");
6982     Builder.defineMacro("__pnacl__");
6983   }
6984   void getTargetDefines(const LangOptions &Opts,
6985                         MacroBuilder &Builder) const override {
6986     getArchDefines(Opts, Builder);
6987   }
6988   bool hasFeature(StringRef Feature) const override {
6989     return Feature == "pnacl";
6990   }
6991   ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
6992   BuiltinVaListKind getBuiltinVaListKind() const override {
6993     return TargetInfo::PNaClABIBuiltinVaList;
6994   }
6995   ArrayRef<const char *> getGCCRegNames() const override;
6996   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
6997   bool validateAsmConstraint(const char *&Name,
6998                              TargetInfo::ConstraintInfo &Info) const override {
6999     return false;
7000   }
7001 
7002   const char *getClobbers() const override {
7003     return "";
7004   }
7005 };
7006 
7007 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const {
7008   return None;
7009 }
7010 
7011 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const {
7012   return None;
7013 }
7014 
7015 // We attempt to use PNaCl (le32) frontend and Mips32EL backend.
7016 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo {
7017 public:
7018   NaClMips32ELTargetInfo(const llvm::Triple &Triple) :
7019     Mips32ELTargetInfo(Triple) {
7020   }
7021 
7022   BuiltinVaListKind getBuiltinVaListKind() const override {
7023     return TargetInfo::PNaClABIBuiltinVaList;
7024   }
7025 };
7026 
7027 class Le64TargetInfo : public TargetInfo {
7028   static const Builtin::Info BuiltinInfo[];
7029 
7030 public:
7031   Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
7032     BigEndian = false;
7033     NoAsmVariants = true;
7034     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
7035     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7036     DataLayoutString = "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128";
7037   }
7038 
7039   void getTargetDefines(const LangOptions &Opts,
7040                         MacroBuilder &Builder) const override {
7041     DefineStd(Builder, "unix", Opts);
7042     defineCPUMacros(Builder, "le64", /*Tuning=*/false);
7043     Builder.defineMacro("__ELF__");
7044   }
7045   ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7046     return llvm::makeArrayRef(BuiltinInfo,
7047                           clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin);
7048   }
7049   BuiltinVaListKind getBuiltinVaListKind() const override {
7050     return TargetInfo::PNaClABIBuiltinVaList;
7051   }
7052   const char *getClobbers() const override { return ""; }
7053   ArrayRef<const char *> getGCCRegNames() const override {
7054     return None;
7055   }
7056   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7057     return None;
7058   }
7059   bool validateAsmConstraint(const char *&Name,
7060                              TargetInfo::ConstraintInfo &Info) const override {
7061     return false;
7062   }
7063 
7064   bool hasProtectedVisibility() const override { return false; }
7065 };
7066 
7067 class WebAssemblyTargetInfo : public TargetInfo {
7068   static const Builtin::Info BuiltinInfo[];
7069 
7070   enum SIMDEnum {
7071     NoSIMD,
7072     SIMD128,
7073   } SIMDLevel;
7074 
7075 public:
7076   explicit WebAssemblyTargetInfo(const llvm::Triple &T)
7077       : TargetInfo(T), SIMDLevel(NoSIMD) {
7078     BigEndian = false;
7079     NoAsmVariants = true;
7080     SuitableAlign = 128;
7081     LargeArrayMinWidth = 128;
7082     LargeArrayAlign = 128;
7083     SimdDefaultAlign = 128;
7084     SigAtomicType = SignedLong;
7085     LongDoubleWidth = LongDoubleAlign = 128;
7086     LongDoubleFormat = &llvm::APFloat::IEEEquad;
7087   }
7088 
7089 protected:
7090   void getTargetDefines(const LangOptions &Opts,
7091                         MacroBuilder &Builder) const override {
7092     defineCPUMacros(Builder, "wasm", /*Tuning=*/false);
7093     if (SIMDLevel >= SIMD128)
7094       Builder.defineMacro("__wasm_simd128__");
7095   }
7096 
7097 private:
7098   bool
7099   initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
7100                  StringRef CPU,
7101                  const std::vector<std::string> &FeaturesVec) const override {
7102     if (CPU == "bleeding-edge")
7103       Features["simd128"] = true;
7104     return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
7105   }
7106   bool hasFeature(StringRef Feature) const final {
7107     return llvm::StringSwitch<bool>(Feature)
7108         .Case("simd128", SIMDLevel >= SIMD128)
7109         .Default(false);
7110   }
7111   bool handleTargetFeatures(std::vector<std::string> &Features,
7112                             DiagnosticsEngine &Diags) final {
7113     for (const auto &Feature : Features) {
7114       if (Feature == "+simd128") {
7115         SIMDLevel = std::max(SIMDLevel, SIMD128);
7116         continue;
7117       }
7118       if (Feature == "-simd128") {
7119         SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1));
7120         continue;
7121       }
7122 
7123       Diags.Report(diag::err_opt_not_valid_with_opt) << Feature
7124                                                      << "-target-feature";
7125       return false;
7126     }
7127     return true;
7128   }
7129   bool setCPU(const std::string &Name) final {
7130     return llvm::StringSwitch<bool>(Name)
7131               .Case("mvp",           true)
7132               .Case("bleeding-edge", true)
7133               .Case("generic",       true)
7134               .Default(false);
7135   }
7136   ArrayRef<Builtin::Info> getTargetBuiltins() const final {
7137     return llvm::makeArrayRef(BuiltinInfo,
7138                    clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin);
7139   }
7140   BuiltinVaListKind getBuiltinVaListKind() const final {
7141     // TODO: Implement va_list properly.
7142     return VoidPtrBuiltinVaList;
7143   }
7144   ArrayRef<const char *> getGCCRegNames() const final {
7145     return None;
7146   }
7147   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final {
7148     return None;
7149   }
7150   bool
7151   validateAsmConstraint(const char *&Name,
7152                         TargetInfo::ConstraintInfo &Info) const final {
7153     return false;
7154   }
7155   const char *getClobbers() const final { return ""; }
7156   bool isCLZForZeroUndef() const final { return false; }
7157   bool hasInt128Type() const final { return true; }
7158   IntType getIntTypeByWidth(unsigned BitWidth,
7159                             bool IsSigned) const final {
7160     // WebAssembly prefers long long for explicitly 64-bit integers.
7161     return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong)
7162                           : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned);
7163   }
7164   IntType getLeastIntTypeByWidth(unsigned BitWidth,
7165                                  bool IsSigned) const final {
7166     // WebAssembly uses long long for int_least64_t and int_fast64_t.
7167     return BitWidth == 64
7168                ? (IsSigned ? SignedLongLong : UnsignedLongLong)
7169                : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned);
7170   }
7171 };
7172 
7173 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = {
7174 #define BUILTIN(ID, TYPE, ATTRS) \
7175   { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7176 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
7177   { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
7178 #include "clang/Basic/BuiltinsWebAssembly.def"
7179 };
7180 
7181 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo {
7182 public:
7183   explicit WebAssembly32TargetInfo(const llvm::Triple &T)
7184       : WebAssemblyTargetInfo(T) {
7185     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
7186     DataLayoutString = "e-p:32:32-i64:64-n32:64-S128";
7187   }
7188 
7189 protected:
7190   void getTargetDefines(const LangOptions &Opts,
7191                         MacroBuilder &Builder) const override {
7192     WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
7193     defineCPUMacros(Builder, "wasm32", /*Tuning=*/false);
7194   }
7195 };
7196 
7197 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo {
7198 public:
7199   explicit WebAssembly64TargetInfo(const llvm::Triple &T)
7200       : WebAssemblyTargetInfo(T) {
7201     LongAlign = LongWidth = 64;
7202     PointerAlign = PointerWidth = 64;
7203     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
7204     DataLayoutString = "e-p:64:64-i64:64-n32:64-S128";
7205   }
7206 
7207 protected:
7208   void getTargetDefines(const LangOptions &Opts,
7209                         MacroBuilder &Builder) const override {
7210     WebAssemblyTargetInfo::getTargetDefines(Opts, Builder);
7211     defineCPUMacros(Builder, "wasm64", /*Tuning=*/false);
7212   }
7213 };
7214 
7215 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
7216 #define BUILTIN(ID, TYPE, ATTRS)                                               \
7217   { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7218 #include "clang/Basic/BuiltinsLe64.def"
7219 };
7220 
7221 static const unsigned SPIRAddrSpaceMap[] = {
7222     1, // opencl_global
7223     3, // opencl_local
7224     2, // opencl_constant
7225     4, // opencl_generic
7226     0, // cuda_device
7227     0, // cuda_constant
7228     0  // cuda_shared
7229 };
7230 class SPIRTargetInfo : public TargetInfo {
7231 public:
7232   SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
7233     assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
7234            "SPIR target must use unknown OS");
7235     assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
7236            "SPIR target must use unknown environment type");
7237     BigEndian = false;
7238     TLSSupported = false;
7239     LongWidth = LongAlign = 64;
7240     AddrSpaceMap = &SPIRAddrSpaceMap;
7241     UseAddrSpaceMapMangling = true;
7242     // Define available target features
7243     // These must be defined in sorted order!
7244     NoAsmVariants = true;
7245   }
7246   void getTargetDefines(const LangOptions &Opts,
7247                         MacroBuilder &Builder) const override {
7248     DefineStd(Builder, "SPIR", Opts);
7249   }
7250   bool hasFeature(StringRef Feature) const override {
7251     return Feature == "spir";
7252   }
7253 
7254   ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; }
7255   const char *getClobbers() const override { return ""; }
7256   ArrayRef<const char *> getGCCRegNames() const override { return None; }
7257   bool validateAsmConstraint(const char *&Name,
7258                              TargetInfo::ConstraintInfo &info) const override {
7259     return true;
7260   }
7261   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7262     return None;
7263   }
7264   BuiltinVaListKind getBuiltinVaListKind() const override {
7265     return TargetInfo::VoidPtrBuiltinVaList;
7266   }
7267 
7268   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
7269     return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK
7270                                                           : CCCR_Warning;
7271   }
7272 
7273   CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
7274     return CC_SpirFunction;
7275   }
7276 };
7277 
7278 class SPIR32TargetInfo : public SPIRTargetInfo {
7279 public:
7280   SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
7281     PointerWidth = PointerAlign = 32;
7282     SizeType = TargetInfo::UnsignedInt;
7283     PtrDiffType = IntPtrType = TargetInfo::SignedInt;
7284     DataLayoutString = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
7285                        "v96:128-v192:256-v256:256-v512:512-v1024:1024";
7286   }
7287   void getTargetDefines(const LangOptions &Opts,
7288                         MacroBuilder &Builder) const override {
7289     DefineStd(Builder, "SPIR32", Opts);
7290   }
7291 };
7292 
7293 class SPIR64TargetInfo : public SPIRTargetInfo {
7294 public:
7295   SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
7296     PointerWidth = PointerAlign = 64;
7297     SizeType = TargetInfo::UnsignedLong;
7298     PtrDiffType = IntPtrType = TargetInfo::SignedLong;
7299     DataLayoutString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
7300                        "v96:128-v192:256-v256:256-v512:512-v1024:1024";
7301   }
7302   void getTargetDefines(const LangOptions &Opts,
7303                         MacroBuilder &Builder) const override {
7304     DefineStd(Builder, "SPIR64", Opts);
7305   }
7306 };
7307 
7308 class XCoreTargetInfo : public TargetInfo {
7309   static const Builtin::Info BuiltinInfo[];
7310 public:
7311   XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
7312     BigEndian = false;
7313     NoAsmVariants = true;
7314     LongLongAlign = 32;
7315     SuitableAlign = 32;
7316     DoubleAlign = LongDoubleAlign = 32;
7317     SizeType = UnsignedInt;
7318     PtrDiffType = SignedInt;
7319     IntPtrType = SignedInt;
7320     WCharType = UnsignedChar;
7321     WIntType = UnsignedInt;
7322     UseZeroLengthBitfieldAlignment = true;
7323     DataLayoutString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
7324                        "-f64:32-a:0:32-n32";
7325   }
7326   void getTargetDefines(const LangOptions &Opts,
7327                         MacroBuilder &Builder) const override {
7328     Builder.defineMacro("__XS1B__");
7329   }
7330   ArrayRef<Builtin::Info> getTargetBuiltins() const override {
7331     return llvm::makeArrayRef(BuiltinInfo,
7332                            clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin);
7333   }
7334   BuiltinVaListKind getBuiltinVaListKind() const override {
7335     return TargetInfo::VoidPtrBuiltinVaList;
7336   }
7337   const char *getClobbers() const override {
7338     return "";
7339   }
7340   ArrayRef<const char *> getGCCRegNames() const override {
7341     static const char * const GCCRegNames[] = {
7342       "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
7343       "r8",   "r9",   "r10",  "r11",  "cp",   "dp",   "sp",   "lr"
7344     };
7345     return llvm::makeArrayRef(GCCRegNames);
7346   }
7347   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
7348     return None;
7349   }
7350   bool validateAsmConstraint(const char *&Name,
7351                              TargetInfo::ConstraintInfo &Info) const override {
7352     return false;
7353   }
7354   int getEHDataRegisterNumber(unsigned RegNo) const override {
7355     // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
7356     return (RegNo < 2)? RegNo : -1;
7357   }
7358 };
7359 
7360 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
7361 #define BUILTIN(ID, TYPE, ATTRS) \
7362   { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr },
7363 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \
7364   { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr },
7365 #include "clang/Basic/BuiltinsXCore.def"
7366 };
7367 
7368 // x86_32 Android target
7369 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> {
7370 public:
7371   AndroidX86_32TargetInfo(const llvm::Triple &Triple)
7372       : LinuxTargetInfo<X86_32TargetInfo>(Triple) {
7373     SuitableAlign = 32;
7374     LongDoubleWidth = 64;
7375     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
7376   }
7377 };
7378 
7379 // x86_64 Android target
7380 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> {
7381 public:
7382   AndroidX86_64TargetInfo(const llvm::Triple &Triple)
7383       : LinuxTargetInfo<X86_64TargetInfo>(Triple) {
7384     LongDoubleFormat = &llvm::APFloat::IEEEquad;
7385   }
7386 
7387   bool useFloat128ManglingForLongDouble() const override {
7388     return true;
7389   }
7390 };
7391 } // end anonymous namespace
7392 
7393 //===----------------------------------------------------------------------===//
7394 // Driver code
7395 //===----------------------------------------------------------------------===//
7396 
7397 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
7398   llvm::Triple::OSType os = Triple.getOS();
7399 
7400   switch (Triple.getArch()) {
7401   default:
7402     return nullptr;
7403 
7404   case llvm::Triple::xcore:
7405     return new XCoreTargetInfo(Triple);
7406 
7407   case llvm::Triple::hexagon:
7408     return new HexagonTargetInfo(Triple);
7409 
7410   case llvm::Triple::aarch64:
7411     if (Triple.isOSDarwin())
7412       return new DarwinAArch64TargetInfo(Triple);
7413 
7414     switch (os) {
7415     case llvm::Triple::CloudABI:
7416       return new CloudABITargetInfo<AArch64leTargetInfo>(Triple);
7417     case llvm::Triple::FreeBSD:
7418       return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple);
7419     case llvm::Triple::Linux:
7420       return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
7421     case llvm::Triple::NetBSD:
7422       return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
7423     default:
7424       return new AArch64leTargetInfo(Triple);
7425     }
7426 
7427   case llvm::Triple::aarch64_be:
7428     switch (os) {
7429     case llvm::Triple::FreeBSD:
7430       return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple);
7431     case llvm::Triple::Linux:
7432       return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
7433     case llvm::Triple::NetBSD:
7434       return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
7435     default:
7436       return new AArch64beTargetInfo(Triple);
7437     }
7438 
7439   case llvm::Triple::arm:
7440   case llvm::Triple::thumb:
7441     if (Triple.isOSBinFormatMachO())
7442       return new DarwinARMTargetInfo(Triple);
7443 
7444     switch (os) {
7445     case llvm::Triple::Linux:
7446       return new LinuxTargetInfo<ARMleTargetInfo>(Triple);
7447     case llvm::Triple::FreeBSD:
7448       return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple);
7449     case llvm::Triple::NetBSD:
7450       return new NetBSDTargetInfo<ARMleTargetInfo>(Triple);
7451     case llvm::Triple::OpenBSD:
7452       return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple);
7453     case llvm::Triple::Bitrig:
7454       return new BitrigTargetInfo<ARMleTargetInfo>(Triple);
7455     case llvm::Triple::RTEMS:
7456       return new RTEMSTargetInfo<ARMleTargetInfo>(Triple);
7457     case llvm::Triple::NaCl:
7458       return new NaClTargetInfo<ARMleTargetInfo>(Triple);
7459     case llvm::Triple::Win32:
7460       switch (Triple.getEnvironment()) {
7461       case llvm::Triple::Cygnus:
7462         return new CygwinARMTargetInfo(Triple);
7463       case llvm::Triple::GNU:
7464         return new MinGWARMTargetInfo(Triple);
7465       case llvm::Triple::Itanium:
7466         return new ItaniumWindowsARMleTargetInfo(Triple);
7467       case llvm::Triple::MSVC:
7468       default: // Assume MSVC for unknown environments
7469         return new MicrosoftARMleTargetInfo(Triple);
7470       }
7471     default:
7472       return new ARMleTargetInfo(Triple);
7473     }
7474 
7475   case llvm::Triple::armeb:
7476   case llvm::Triple::thumbeb:
7477     if (Triple.isOSDarwin())
7478       return new DarwinARMTargetInfo(Triple);
7479 
7480     switch (os) {
7481     case llvm::Triple::Linux:
7482       return new LinuxTargetInfo<ARMbeTargetInfo>(Triple);
7483     case llvm::Triple::FreeBSD:
7484       return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple);
7485     case llvm::Triple::NetBSD:
7486       return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple);
7487     case llvm::Triple::OpenBSD:
7488       return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple);
7489     case llvm::Triple::Bitrig:
7490       return new BitrigTargetInfo<ARMbeTargetInfo>(Triple);
7491     case llvm::Triple::RTEMS:
7492       return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple);
7493     case llvm::Triple::NaCl:
7494       return new NaClTargetInfo<ARMbeTargetInfo>(Triple);
7495     default:
7496       return new ARMbeTargetInfo(Triple);
7497     }
7498 
7499   case llvm::Triple::bpfeb:
7500   case llvm::Triple::bpfel:
7501     return new BPFTargetInfo(Triple);
7502 
7503   case llvm::Triple::msp430:
7504     return new MSP430TargetInfo(Triple);
7505 
7506   case llvm::Triple::mips:
7507     switch (os) {
7508     case llvm::Triple::Linux:
7509       return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
7510     case llvm::Triple::RTEMS:
7511       return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
7512     case llvm::Triple::FreeBSD:
7513       return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
7514     case llvm::Triple::NetBSD:
7515       return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
7516     default:
7517       return new Mips32EBTargetInfo(Triple);
7518     }
7519 
7520   case llvm::Triple::mipsel:
7521     switch (os) {
7522     case llvm::Triple::Linux:
7523       return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
7524     case llvm::Triple::RTEMS:
7525       return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
7526     case llvm::Triple::FreeBSD:
7527       return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
7528     case llvm::Triple::NetBSD:
7529       return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
7530     case llvm::Triple::NaCl:
7531       return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple);
7532     default:
7533       return new Mips32ELTargetInfo(Triple);
7534     }
7535 
7536   case llvm::Triple::mips64:
7537     switch (os) {
7538     case llvm::Triple::Linux:
7539       return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
7540     case llvm::Triple::RTEMS:
7541       return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
7542     case llvm::Triple::FreeBSD:
7543       return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
7544     case llvm::Triple::NetBSD:
7545       return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
7546     case llvm::Triple::OpenBSD:
7547       return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
7548     default:
7549       return new Mips64EBTargetInfo(Triple);
7550     }
7551 
7552   case llvm::Triple::mips64el:
7553     switch (os) {
7554     case llvm::Triple::Linux:
7555       return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
7556     case llvm::Triple::RTEMS:
7557       return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
7558     case llvm::Triple::FreeBSD:
7559       return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7560     case llvm::Triple::NetBSD:
7561       return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7562     case llvm::Triple::OpenBSD:
7563       return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7564     default:
7565       return new Mips64ELTargetInfo(Triple);
7566     }
7567 
7568   case llvm::Triple::le32:
7569     switch (os) {
7570     case llvm::Triple::NaCl:
7571       return new NaClTargetInfo<PNaClTargetInfo>(Triple);
7572     default:
7573       return nullptr;
7574     }
7575 
7576   case llvm::Triple::le64:
7577     return new Le64TargetInfo(Triple);
7578 
7579   case llvm::Triple::ppc:
7580     if (Triple.isOSDarwin())
7581       return new DarwinPPC32TargetInfo(Triple);
7582     switch (os) {
7583     case llvm::Triple::Linux:
7584       return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
7585     case llvm::Triple::FreeBSD:
7586       return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
7587     case llvm::Triple::NetBSD:
7588       return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
7589     case llvm::Triple::OpenBSD:
7590       return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
7591     case llvm::Triple::RTEMS:
7592       return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
7593     default:
7594       return new PPC32TargetInfo(Triple);
7595     }
7596 
7597   case llvm::Triple::ppc64:
7598     if (Triple.isOSDarwin())
7599       return new DarwinPPC64TargetInfo(Triple);
7600     switch (os) {
7601     case llvm::Triple::Linux:
7602       return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
7603     case llvm::Triple::Lv2:
7604       return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
7605     case llvm::Triple::FreeBSD:
7606       return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
7607     case llvm::Triple::NetBSD:
7608       return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
7609     default:
7610       return new PPC64TargetInfo(Triple);
7611     }
7612 
7613   case llvm::Triple::ppc64le:
7614     switch (os) {
7615     case llvm::Triple::Linux:
7616       return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
7617     case llvm::Triple::NetBSD:
7618       return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
7619     default:
7620       return new PPC64TargetInfo(Triple);
7621     }
7622 
7623   case llvm::Triple::nvptx:
7624     return new NVPTX32TargetInfo(Triple);
7625   case llvm::Triple::nvptx64:
7626     return new NVPTX64TargetInfo(Triple);
7627 
7628   case llvm::Triple::amdgcn:
7629   case llvm::Triple::r600:
7630     return new AMDGPUTargetInfo(Triple);
7631 
7632   case llvm::Triple::sparc:
7633     switch (os) {
7634     case llvm::Triple::Linux:
7635       return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
7636     case llvm::Triple::Solaris:
7637       return new SolarisTargetInfo<SparcV8TargetInfo>(Triple);
7638     case llvm::Triple::NetBSD:
7639       return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
7640     case llvm::Triple::OpenBSD:
7641       return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
7642     case llvm::Triple::RTEMS:
7643       return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
7644     default:
7645       return new SparcV8TargetInfo(Triple);
7646     }
7647 
7648   // The 'sparcel' architecture copies all the above cases except for Solaris.
7649   case llvm::Triple::sparcel:
7650     switch (os) {
7651     case llvm::Triple::Linux:
7652       return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple);
7653     case llvm::Triple::NetBSD:
7654       return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple);
7655     case llvm::Triple::OpenBSD:
7656       return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple);
7657     case llvm::Triple::RTEMS:
7658       return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple);
7659     default:
7660       return new SparcV8elTargetInfo(Triple);
7661     }
7662 
7663   case llvm::Triple::sparcv9:
7664     switch (os) {
7665     case llvm::Triple::Linux:
7666       return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
7667     case llvm::Triple::Solaris:
7668       return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
7669     case llvm::Triple::NetBSD:
7670       return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
7671     case llvm::Triple::OpenBSD:
7672       return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
7673     case llvm::Triple::FreeBSD:
7674       return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
7675     default:
7676       return new SparcV9TargetInfo(Triple);
7677     }
7678 
7679   case llvm::Triple::systemz:
7680     switch (os) {
7681     case llvm::Triple::Linux:
7682       return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
7683     default:
7684       return new SystemZTargetInfo(Triple);
7685     }
7686 
7687   case llvm::Triple::tce:
7688     return new TCETargetInfo(Triple);
7689 
7690   case llvm::Triple::x86:
7691     if (Triple.isOSDarwin())
7692       return new DarwinI386TargetInfo(Triple);
7693 
7694     switch (os) {
7695     case llvm::Triple::CloudABI:
7696       return new CloudABITargetInfo<X86_32TargetInfo>(Triple);
7697     case llvm::Triple::Linux: {
7698       switch (Triple.getEnvironment()) {
7699       default:
7700         return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
7701       case llvm::Triple::Android:
7702         return new AndroidX86_32TargetInfo(Triple);
7703       }
7704     }
7705     case llvm::Triple::DragonFly:
7706       return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
7707     case llvm::Triple::NetBSD:
7708       return new NetBSDI386TargetInfo(Triple);
7709     case llvm::Triple::OpenBSD:
7710       return new OpenBSDI386TargetInfo(Triple);
7711     case llvm::Triple::Bitrig:
7712       return new BitrigI386TargetInfo(Triple);
7713     case llvm::Triple::FreeBSD:
7714       return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
7715     case llvm::Triple::KFreeBSD:
7716       return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
7717     case llvm::Triple::Minix:
7718       return new MinixTargetInfo<X86_32TargetInfo>(Triple);
7719     case llvm::Triple::Solaris:
7720       return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
7721     case llvm::Triple::Win32: {
7722       switch (Triple.getEnvironment()) {
7723       case llvm::Triple::Cygnus:
7724         return new CygwinX86_32TargetInfo(Triple);
7725       case llvm::Triple::GNU:
7726         return new MinGWX86_32TargetInfo(Triple);
7727       case llvm::Triple::Itanium:
7728       case llvm::Triple::MSVC:
7729       default: // Assume MSVC for unknown environments
7730         return new MicrosoftX86_32TargetInfo(Triple);
7731       }
7732     }
7733     case llvm::Triple::Haiku:
7734       return new HaikuX86_32TargetInfo(Triple);
7735     case llvm::Triple::RTEMS:
7736       return new RTEMSX86_32TargetInfo(Triple);
7737     case llvm::Triple::NaCl:
7738       return new NaClTargetInfo<X86_32TargetInfo>(Triple);
7739     default:
7740       return new X86_32TargetInfo(Triple);
7741     }
7742 
7743   case llvm::Triple::x86_64:
7744     if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
7745       return new DarwinX86_64TargetInfo(Triple);
7746 
7747     switch (os) {
7748     case llvm::Triple::CloudABI:
7749       return new CloudABITargetInfo<X86_64TargetInfo>(Triple);
7750     case llvm::Triple::Linux: {
7751       switch (Triple.getEnvironment()) {
7752       default:
7753         return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
7754       case llvm::Triple::Android:
7755         return new AndroidX86_64TargetInfo(Triple);
7756       }
7757     }
7758     case llvm::Triple::DragonFly:
7759       return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
7760     case llvm::Triple::NetBSD:
7761       return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
7762     case llvm::Triple::OpenBSD:
7763       return new OpenBSDX86_64TargetInfo(Triple);
7764     case llvm::Triple::Bitrig:
7765       return new BitrigX86_64TargetInfo(Triple);
7766     case llvm::Triple::FreeBSD:
7767       return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
7768     case llvm::Triple::KFreeBSD:
7769       return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
7770     case llvm::Triple::Solaris:
7771       return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
7772     case llvm::Triple::Win32: {
7773       switch (Triple.getEnvironment()) {
7774       case llvm::Triple::Cygnus:
7775         return new CygwinX86_64TargetInfo(Triple);
7776       case llvm::Triple::GNU:
7777         return new MinGWX86_64TargetInfo(Triple);
7778       case llvm::Triple::MSVC:
7779       default: // Assume MSVC for unknown environments
7780         return new MicrosoftX86_64TargetInfo(Triple);
7781       }
7782     }
7783     case llvm::Triple::NaCl:
7784       return new NaClTargetInfo<X86_64TargetInfo>(Triple);
7785     case llvm::Triple::PS4:
7786       return new PS4OSTargetInfo<X86_64TargetInfo>(Triple);
7787     default:
7788       return new X86_64TargetInfo(Triple);
7789     }
7790 
7791   case llvm::Triple::spir: {
7792     if (Triple.getOS() != llvm::Triple::UnknownOS ||
7793         Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
7794       return nullptr;
7795     return new SPIR32TargetInfo(Triple);
7796   }
7797   case llvm::Triple::spir64: {
7798     if (Triple.getOS() != llvm::Triple::UnknownOS ||
7799         Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
7800       return nullptr;
7801     return new SPIR64TargetInfo(Triple);
7802   }
7803   case llvm::Triple::wasm32:
7804     if (!(Triple == llvm::Triple("wasm32-unknown-unknown")))
7805       return nullptr;
7806     return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple);
7807   case llvm::Triple::wasm64:
7808     if (!(Triple == llvm::Triple("wasm64-unknown-unknown")))
7809       return nullptr;
7810     return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple);
7811   }
7812 }
7813 
7814 /// CreateTargetInfo - Return the target info object for the specified target
7815 /// options.
7816 TargetInfo *
7817 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
7818                              const std::shared_ptr<TargetOptions> &Opts) {
7819   llvm::Triple Triple(Opts->Triple);
7820 
7821   // Construct the target
7822   std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple));
7823   if (!Target) {
7824     Diags.Report(diag::err_target_unknown_triple) << Triple.str();
7825     return nullptr;
7826   }
7827   Target->TargetOpts = Opts;
7828 
7829   // Set the target CPU if specified.
7830   if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
7831     Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
7832     return nullptr;
7833   }
7834 
7835   // Set the target ABI if specified.
7836   if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
7837     Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
7838     return nullptr;
7839   }
7840 
7841   // Set the fp math unit.
7842   if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
7843     Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
7844     return nullptr;
7845   }
7846 
7847   // Compute the default target features, we need the target to handle this
7848   // because features may have dependencies on one another.
7849   llvm::StringMap<bool> Features;
7850   if (!Target->initFeatureMap(Features, Diags, Opts->CPU,
7851                               Opts->FeaturesAsWritten))
7852       return nullptr;
7853 
7854   // Add the features to the compile options.
7855   Opts->Features.clear();
7856   for (const auto &F : Features)
7857     Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str());
7858 
7859   if (!Target->handleTargetFeatures(Opts->Features, Diags))
7860     return nullptr;
7861 
7862   return Target.release();
7863 }
7864