1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 115 const llvm::Triple &Triple, 116 StringRef &PlatformName, 117 VersionTuple &PlatformMinVersion) { 118 Builder.defineMacro("__APPLE_CC__", "6000"); 119 Builder.defineMacro("__APPLE__"); 120 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 121 // AddressSanitizer doesn't play well with source fortification, which is on 122 // by default on Darwin. 123 if (Opts.Sanitize.has(SanitizerKind::Address)) 124 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 125 126 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 127 if (!Opts.ObjC1) { 128 // __weak is always defined, for use in blocks and with objc pointers. 129 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 130 Builder.defineMacro("__strong", ""); 131 Builder.defineMacro("__unsafe_unretained", ""); 132 } 133 134 if (Opts.Static) 135 Builder.defineMacro("__STATIC__"); 136 else 137 Builder.defineMacro("__DYNAMIC__"); 138 139 if (Opts.POSIXThreads) 140 Builder.defineMacro("_REENTRANT"); 141 142 // Get the platform type and version number from the triple. 143 unsigned Maj, Min, Rev; 144 if (Triple.isMacOSX()) { 145 Triple.getMacOSXVersion(Maj, Min, Rev); 146 PlatformName = "macos"; 147 } else { 148 Triple.getOSVersion(Maj, Min, Rev); 149 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 150 } 151 152 // If -target arch-pc-win32-macho option specified, we're 153 // generating code for Win32 ABI. No need to emit 154 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 155 if (PlatformName == "win32") { 156 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 157 return; 158 } 159 160 // Set the appropriate OS version define. 161 if (Triple.isiOS()) { 162 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 163 char Str[7]; 164 if (Maj < 10) { 165 Str[0] = '0' + Maj; 166 Str[1] = '0' + (Min / 10); 167 Str[2] = '0' + (Min % 10); 168 Str[3] = '0' + (Rev / 10); 169 Str[4] = '0' + (Rev % 10); 170 Str[5] = '\0'; 171 } else { 172 // Handle versions >= 10. 173 Str[0] = '0' + (Maj / 10); 174 Str[1] = '0' + (Maj % 10); 175 Str[2] = '0' + (Min / 10); 176 Str[3] = '0' + (Min % 10); 177 Str[4] = '0' + (Rev / 10); 178 Str[5] = '0' + (Rev % 10); 179 Str[6] = '\0'; 180 } 181 if (Triple.isTvOS()) 182 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 183 else 184 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 185 Str); 186 187 } else if (Triple.isWatchOS()) { 188 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 189 char Str[6]; 190 Str[0] = '0' + Maj; 191 Str[1] = '0' + (Min / 10); 192 Str[2] = '0' + (Min % 10); 193 Str[3] = '0' + (Rev / 10); 194 Str[4] = '0' + (Rev % 10); 195 Str[5] = '\0'; 196 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 197 } else if (Triple.isMacOSX()) { 198 // Note that the Driver allows versions which aren't representable in the 199 // define (because we only get a single digit for the minor and micro 200 // revision numbers). So, we limit them to the maximum representable 201 // version. 202 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 203 char Str[7]; 204 if (Maj < 10 || (Maj == 10 && Min < 10)) { 205 Str[0] = '0' + (Maj / 10); 206 Str[1] = '0' + (Maj % 10); 207 Str[2] = '0' + std::min(Min, 9U); 208 Str[3] = '0' + std::min(Rev, 9U); 209 Str[4] = '\0'; 210 } else { 211 // Handle versions > 10.9. 212 Str[0] = '0' + (Maj / 10); 213 Str[1] = '0' + (Maj % 10); 214 Str[2] = '0' + (Min / 10); 215 Str[3] = '0' + (Min % 10); 216 Str[4] = '0' + (Rev / 10); 217 Str[5] = '0' + (Rev % 10); 218 Str[6] = '\0'; 219 } 220 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 221 } 222 223 // Tell users about the kernel if there is one. 224 if (Triple.isOSDarwin()) 225 Builder.defineMacro("__MACH__"); 226 227 // The Watch ABI uses Dwarf EH. 228 if(Triple.isWatchABI()) 229 Builder.defineMacro("__ARM_DWARF_EH__"); 230 231 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 232 } 233 234 template<typename Target> 235 class DarwinTargetInfo : public OSTargetInfo<Target> { 236 protected: 237 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 238 MacroBuilder &Builder) const override { 239 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 240 this->PlatformMinVersion); 241 } 242 243 public: 244 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 245 : OSTargetInfo<Target>(Triple, Opts) { 246 // By default, no TLS, and we whitelist permitted architecture/OS 247 // combinations. 248 this->TLSSupported = false; 249 250 if (Triple.isMacOSX()) 251 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 252 else if (Triple.isiOS()) { 253 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 254 if (Triple.getArch() == llvm::Triple::x86_64 || 255 Triple.getArch() == llvm::Triple::aarch64) 256 this->TLSSupported = !Triple.isOSVersionLT(8); 257 else if (Triple.getArch() == llvm::Triple::x86 || 258 Triple.getArch() == llvm::Triple::arm || 259 Triple.getArch() == llvm::Triple::thumb) 260 this->TLSSupported = !Triple.isOSVersionLT(9); 261 } else if (Triple.isWatchOS()) 262 this->TLSSupported = !Triple.isOSVersionLT(2); 263 264 this->MCountName = "\01mcount"; 265 } 266 267 std::string isValidSectionSpecifier(StringRef SR) const override { 268 // Let MCSectionMachO validate this. 269 StringRef Segment, Section; 270 unsigned TAA, StubSize; 271 bool HasTAA; 272 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 273 TAA, HasTAA, StubSize); 274 } 275 276 const char *getStaticInitSectionSpecifier() const override { 277 // FIXME: We should return 0 when building kexts. 278 return "__TEXT,__StaticInit,regular,pure_instructions"; 279 } 280 281 /// Darwin does not support protected visibility. Darwin's "default" 282 /// is very similar to ELF's "protected"; Darwin requires a "weak" 283 /// attribute on declarations that can be dynamically replaced. 284 bool hasProtectedVisibility() const override { 285 return false; 286 } 287 288 unsigned getExnObjectAlignment() const override { 289 // The alignment of an exception object is 8-bytes for darwin since 290 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 291 // and therefore doesn't guarantee 16-byte alignment. 292 return 64; 293 } 294 }; 295 296 297 // DragonFlyBSD Target 298 template<typename Target> 299 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 300 protected: 301 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 302 MacroBuilder &Builder) const override { 303 // DragonFly defines; list based off of gcc output 304 Builder.defineMacro("__DragonFly__"); 305 Builder.defineMacro("__DragonFly_cc_version", "100001"); 306 Builder.defineMacro("__ELF__"); 307 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 308 Builder.defineMacro("__tune_i386__"); 309 DefineStd(Builder, "unix", Opts); 310 } 311 public: 312 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 313 : OSTargetInfo<Target>(Triple, Opts) { 314 switch (Triple.getArch()) { 315 default: 316 case llvm::Triple::x86: 317 case llvm::Triple::x86_64: 318 this->MCountName = ".mcount"; 319 break; 320 } 321 } 322 }; 323 324 #ifndef FREEBSD_CC_VERSION 325 #define FREEBSD_CC_VERSION 0U 326 #endif 327 328 // FreeBSD Target 329 template<typename Target> 330 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 331 protected: 332 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 333 MacroBuilder &Builder) const override { 334 // FreeBSD defines; list based off of gcc output 335 336 unsigned Release = Triple.getOSMajorVersion(); 337 if (Release == 0U) 338 Release = 8U; 339 unsigned CCVersion = FREEBSD_CC_VERSION; 340 if (CCVersion == 0U) 341 CCVersion = Release * 100000U + 1U; 342 343 Builder.defineMacro("__FreeBSD__", Twine(Release)); 344 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 345 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 346 DefineStd(Builder, "unix", Opts); 347 Builder.defineMacro("__ELF__"); 348 349 // On FreeBSD, wchar_t contains the number of the code point as 350 // used by the character set of the locale. These character sets are 351 // not necessarily a superset of ASCII. 352 // 353 // FIXME: This is wrong; the macro refers to the numerical values 354 // of wchar_t *literals*, which are not locale-dependent. However, 355 // FreeBSD systems apparently depend on us getting this wrong, and 356 // setting this to 1 is conforming even if all the basic source 357 // character literals have the same encoding as char and wchar_t. 358 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 359 } 360 public: 361 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 362 : OSTargetInfo<Target>(Triple, Opts) { 363 switch (Triple.getArch()) { 364 default: 365 case llvm::Triple::x86: 366 case llvm::Triple::x86_64: 367 this->MCountName = ".mcount"; 368 break; 369 case llvm::Triple::mips: 370 case llvm::Triple::mipsel: 371 case llvm::Triple::ppc: 372 case llvm::Triple::ppc64: 373 case llvm::Triple::ppc64le: 374 this->MCountName = "_mcount"; 375 break; 376 case llvm::Triple::arm: 377 this->MCountName = "__mcount"; 378 break; 379 } 380 } 381 }; 382 383 // GNU/kFreeBSD Target 384 template<typename Target> 385 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 386 protected: 387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 388 MacroBuilder &Builder) const override { 389 // GNU/kFreeBSD defines; list based off of gcc output 390 391 DefineStd(Builder, "unix", Opts); 392 Builder.defineMacro("__FreeBSD_kernel__"); 393 Builder.defineMacro("__GLIBC__"); 394 Builder.defineMacro("__ELF__"); 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 if (Opts.CPlusPlus) 398 Builder.defineMacro("_GNU_SOURCE"); 399 } 400 public: 401 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 402 : OSTargetInfo<Target>(Triple, Opts) {} 403 }; 404 405 // Haiku Target 406 template<typename Target> 407 class HaikuTargetInfo : public OSTargetInfo<Target> { 408 protected: 409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 410 MacroBuilder &Builder) const override { 411 // Haiku defines; list based off of gcc output 412 Builder.defineMacro("__HAIKU__"); 413 Builder.defineMacro("__ELF__"); 414 DefineStd(Builder, "unix", Opts); 415 } 416 public: 417 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 418 : OSTargetInfo<Target>(Triple, Opts) { 419 this->SizeType = TargetInfo::UnsignedLong; 420 this->IntPtrType = TargetInfo::SignedLong; 421 this->PtrDiffType = TargetInfo::SignedLong; 422 this->ProcessIDType = TargetInfo::SignedLong; 423 this->TLSSupported = false; 424 425 } 426 }; 427 428 // Minix Target 429 template<typename Target> 430 class MinixTargetInfo : public OSTargetInfo<Target> { 431 protected: 432 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 433 MacroBuilder &Builder) const override { 434 // Minix defines 435 436 Builder.defineMacro("__minix", "3"); 437 Builder.defineMacro("_EM_WSIZE", "4"); 438 Builder.defineMacro("_EM_PSIZE", "4"); 439 Builder.defineMacro("_EM_SSIZE", "2"); 440 Builder.defineMacro("_EM_LSIZE", "4"); 441 Builder.defineMacro("_EM_FSIZE", "4"); 442 Builder.defineMacro("_EM_DSIZE", "8"); 443 Builder.defineMacro("__ELF__"); 444 DefineStd(Builder, "unix", Opts); 445 } 446 public: 447 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 448 : OSTargetInfo<Target>(Triple, Opts) {} 449 }; 450 451 // Linux target 452 template<typename Target> 453 class LinuxTargetInfo : public OSTargetInfo<Target> { 454 protected: 455 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 456 MacroBuilder &Builder) const override { 457 // Linux defines; list based off of gcc output 458 DefineStd(Builder, "unix", Opts); 459 DefineStd(Builder, "linux", Opts); 460 Builder.defineMacro("__gnu_linux__"); 461 Builder.defineMacro("__ELF__"); 462 if (Triple.isAndroid()) { 463 Builder.defineMacro("__ANDROID__", "1"); 464 unsigned Maj, Min, Rev; 465 Triple.getEnvironmentVersion(Maj, Min, Rev); 466 this->PlatformName = "android"; 467 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 468 if (Maj) 469 Builder.defineMacro("__ANDROID_API__", Twine(Maj)); 470 } 471 if (Opts.POSIXThreads) 472 Builder.defineMacro("_REENTRANT"); 473 if (Opts.CPlusPlus) 474 Builder.defineMacro("_GNU_SOURCE"); 475 if (this->HasFloat128) 476 Builder.defineMacro("__FLOAT128__"); 477 } 478 public: 479 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 480 : OSTargetInfo<Target>(Triple, Opts) { 481 this->WIntType = TargetInfo::UnsignedInt; 482 483 switch (Triple.getArch()) { 484 default: 485 break; 486 case llvm::Triple::ppc: 487 case llvm::Triple::ppc64: 488 case llvm::Triple::ppc64le: 489 this->MCountName = "_mcount"; 490 break; 491 case llvm::Triple::x86: 492 case llvm::Triple::x86_64: 493 case llvm::Triple::systemz: 494 this->HasFloat128 = true; 495 break; 496 } 497 } 498 499 const char *getStaticInitSectionSpecifier() const override { 500 return ".text.startup"; 501 } 502 }; 503 504 // NetBSD Target 505 template<typename Target> 506 class NetBSDTargetInfo : public OSTargetInfo<Target> { 507 protected: 508 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 509 MacroBuilder &Builder) const override { 510 // NetBSD defines; list based off of gcc output 511 Builder.defineMacro("__NetBSD__"); 512 Builder.defineMacro("__unix__"); 513 Builder.defineMacro("__ELF__"); 514 if (Opts.POSIXThreads) 515 Builder.defineMacro("_POSIX_THREADS"); 516 517 switch (Triple.getArch()) { 518 default: 519 break; 520 case llvm::Triple::arm: 521 case llvm::Triple::armeb: 522 case llvm::Triple::thumb: 523 case llvm::Triple::thumbeb: 524 Builder.defineMacro("__ARM_DWARF_EH__"); 525 break; 526 } 527 } 528 public: 529 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 530 : OSTargetInfo<Target>(Triple, Opts) { 531 this->MCountName = "_mcount"; 532 } 533 }; 534 535 // OpenBSD Target 536 template<typename Target> 537 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 538 protected: 539 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 540 MacroBuilder &Builder) const override { 541 // OpenBSD defines; list based off of gcc output 542 543 Builder.defineMacro("__OpenBSD__"); 544 DefineStd(Builder, "unix", Opts); 545 Builder.defineMacro("__ELF__"); 546 if (Opts.POSIXThreads) 547 Builder.defineMacro("_REENTRANT"); 548 } 549 public: 550 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 551 : OSTargetInfo<Target>(Triple, Opts) { 552 this->TLSSupported = false; 553 554 switch (Triple.getArch()) { 555 default: 556 case llvm::Triple::x86: 557 case llvm::Triple::x86_64: 558 case llvm::Triple::arm: 559 case llvm::Triple::sparc: 560 this->MCountName = "__mcount"; 561 break; 562 case llvm::Triple::mips64: 563 case llvm::Triple::mips64el: 564 case llvm::Triple::ppc: 565 case llvm::Triple::sparcv9: 566 this->MCountName = "_mcount"; 567 break; 568 } 569 } 570 }; 571 572 // Bitrig Target 573 template<typename Target> 574 class BitrigTargetInfo : public OSTargetInfo<Target> { 575 protected: 576 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 577 MacroBuilder &Builder) const override { 578 // Bitrig defines; list based off of gcc output 579 580 Builder.defineMacro("__Bitrig__"); 581 DefineStd(Builder, "unix", Opts); 582 Builder.defineMacro("__ELF__"); 583 if (Opts.POSIXThreads) 584 Builder.defineMacro("_REENTRANT"); 585 586 switch (Triple.getArch()) { 587 default: 588 break; 589 case llvm::Triple::arm: 590 case llvm::Triple::armeb: 591 case llvm::Triple::thumb: 592 case llvm::Triple::thumbeb: 593 Builder.defineMacro("__ARM_DWARF_EH__"); 594 break; 595 } 596 } 597 public: 598 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 599 : OSTargetInfo<Target>(Triple, Opts) { 600 this->MCountName = "__mcount"; 601 } 602 }; 603 604 // PSP Target 605 template<typename Target> 606 class PSPTargetInfo : public OSTargetInfo<Target> { 607 protected: 608 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 609 MacroBuilder &Builder) const override { 610 // PSP defines; list based on the output of the pspdev gcc toolchain. 611 Builder.defineMacro("PSP"); 612 Builder.defineMacro("_PSP"); 613 Builder.defineMacro("__psp__"); 614 Builder.defineMacro("__ELF__"); 615 } 616 public: 617 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 618 }; 619 620 // PS3 PPU Target 621 template<typename Target> 622 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 623 protected: 624 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 625 MacroBuilder &Builder) const override { 626 // PS3 PPU defines. 627 Builder.defineMacro("__PPC__"); 628 Builder.defineMacro("__PPU__"); 629 Builder.defineMacro("__CELLOS_LV2__"); 630 Builder.defineMacro("__ELF__"); 631 Builder.defineMacro("__LP32__"); 632 Builder.defineMacro("_ARCH_PPC64"); 633 Builder.defineMacro("__powerpc64__"); 634 } 635 public: 636 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 637 : OSTargetInfo<Target>(Triple, Opts) { 638 this->LongWidth = this->LongAlign = 32; 639 this->PointerWidth = this->PointerAlign = 32; 640 this->IntMaxType = TargetInfo::SignedLongLong; 641 this->Int64Type = TargetInfo::SignedLongLong; 642 this->SizeType = TargetInfo::UnsignedInt; 643 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 644 } 645 }; 646 647 template <typename Target> 648 class PS4OSTargetInfo : public OSTargetInfo<Target> { 649 protected: 650 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 651 MacroBuilder &Builder) const override { 652 Builder.defineMacro("__FreeBSD__", "9"); 653 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 654 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 655 DefineStd(Builder, "unix", Opts); 656 Builder.defineMacro("__ELF__"); 657 Builder.defineMacro("__ORBIS__"); 658 } 659 public: 660 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 661 : OSTargetInfo<Target>(Triple, Opts) { 662 this->WCharType = this->UnsignedShort; 663 664 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 665 this->MaxTLSAlign = 256; 666 667 // On PS4, do not honor explicit bit field alignment, 668 // as in "__attribute__((aligned(2))) int b : 1;". 669 this->UseExplicitBitFieldAlignment = false; 670 671 switch (Triple.getArch()) { 672 default: 673 case llvm::Triple::x86_64: 674 this->MCountName = ".mcount"; 675 break; 676 } 677 } 678 }; 679 680 // Solaris target 681 template<typename Target> 682 class SolarisTargetInfo : public OSTargetInfo<Target> { 683 protected: 684 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 685 MacroBuilder &Builder) const override { 686 DefineStd(Builder, "sun", Opts); 687 DefineStd(Builder, "unix", Opts); 688 Builder.defineMacro("__ELF__"); 689 Builder.defineMacro("__svr4__"); 690 Builder.defineMacro("__SVR4"); 691 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 692 // newer, but to 500 for everything else. feature_test.h has a check to 693 // ensure that you are not using C99 with an old version of X/Open or C89 694 // with a new version. 695 if (Opts.C99) 696 Builder.defineMacro("_XOPEN_SOURCE", "600"); 697 else 698 Builder.defineMacro("_XOPEN_SOURCE", "500"); 699 if (Opts.CPlusPlus) 700 Builder.defineMacro("__C99FEATURES__"); 701 Builder.defineMacro("_LARGEFILE_SOURCE"); 702 Builder.defineMacro("_LARGEFILE64_SOURCE"); 703 Builder.defineMacro("__EXTENSIONS__"); 704 Builder.defineMacro("_REENTRANT"); 705 } 706 public: 707 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 708 : OSTargetInfo<Target>(Triple, Opts) { 709 this->WCharType = this->SignedInt; 710 // FIXME: WIntType should be SignedLong 711 } 712 }; 713 714 // Windows target 715 template<typename Target> 716 class WindowsTargetInfo : public OSTargetInfo<Target> { 717 protected: 718 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 719 MacroBuilder &Builder) const override { 720 Builder.defineMacro("_WIN32"); 721 } 722 void getVisualStudioDefines(const LangOptions &Opts, 723 MacroBuilder &Builder) const { 724 if (Opts.CPlusPlus) { 725 if (Opts.RTTIData) 726 Builder.defineMacro("_CPPRTTI"); 727 728 if (Opts.CXXExceptions) 729 Builder.defineMacro("_CPPUNWIND"); 730 } 731 732 if (Opts.Bool) 733 Builder.defineMacro("__BOOL_DEFINED"); 734 735 if (!Opts.CharIsSigned) 736 Builder.defineMacro("_CHAR_UNSIGNED"); 737 738 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 739 // but it works for now. 740 if (Opts.POSIXThreads) 741 Builder.defineMacro("_MT"); 742 743 if (Opts.MSCompatibilityVersion) { 744 Builder.defineMacro("_MSC_VER", 745 Twine(Opts.MSCompatibilityVersion / 100000)); 746 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 747 // FIXME We cannot encode the revision information into 32-bits 748 Builder.defineMacro("_MSC_BUILD", Twine(1)); 749 750 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 751 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 752 753 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 754 if (Opts.CPlusPlus1z) 755 Builder.defineMacro("_MSVC_LANG", "201403L"); 756 else if (Opts.CPlusPlus14) 757 Builder.defineMacro("_MSVC_LANG", "201402L"); 758 } 759 } 760 761 if (Opts.MicrosoftExt) { 762 Builder.defineMacro("_MSC_EXTENSIONS"); 763 764 if (Opts.CPlusPlus11) { 765 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 766 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 767 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 768 } 769 } 770 771 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 772 } 773 774 public: 775 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 776 : OSTargetInfo<Target>(Triple, Opts) {} 777 }; 778 779 template <typename Target> 780 class NaClTargetInfo : public OSTargetInfo<Target> { 781 protected: 782 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 783 MacroBuilder &Builder) const override { 784 if (Opts.POSIXThreads) 785 Builder.defineMacro("_REENTRANT"); 786 if (Opts.CPlusPlus) 787 Builder.defineMacro("_GNU_SOURCE"); 788 789 DefineStd(Builder, "unix", Opts); 790 Builder.defineMacro("__ELF__"); 791 Builder.defineMacro("__native_client__"); 792 } 793 794 public: 795 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 796 : OSTargetInfo<Target>(Triple, Opts) { 797 this->LongAlign = 32; 798 this->LongWidth = 32; 799 this->PointerAlign = 32; 800 this->PointerWidth = 32; 801 this->IntMaxType = TargetInfo::SignedLongLong; 802 this->Int64Type = TargetInfo::SignedLongLong; 803 this->DoubleAlign = 64; 804 this->LongDoubleWidth = 64; 805 this->LongDoubleAlign = 64; 806 this->LongLongWidth = 64; 807 this->LongLongAlign = 64; 808 this->SizeType = TargetInfo::UnsignedInt; 809 this->PtrDiffType = TargetInfo::SignedInt; 810 this->IntPtrType = TargetInfo::SignedInt; 811 // RegParmMax is inherited from the underlying architecture. 812 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 813 if (Triple.getArch() == llvm::Triple::arm) { 814 // Handled in ARM's setABI(). 815 } else if (Triple.getArch() == llvm::Triple::x86) { 816 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 817 } else if (Triple.getArch() == llvm::Triple::x86_64) { 818 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 819 } else if (Triple.getArch() == llvm::Triple::mipsel) { 820 // Handled on mips' setDataLayout. 821 } else { 822 assert(Triple.getArch() == llvm::Triple::le32); 823 this->resetDataLayout("e-p:32:32-i64:64"); 824 } 825 } 826 }; 827 828 // Fuchsia Target 829 template<typename Target> 830 class FuchsiaTargetInfo : public OSTargetInfo<Target> { 831 protected: 832 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 833 MacroBuilder &Builder) const override { 834 Builder.defineMacro("__Fuchsia__"); 835 Builder.defineMacro("__ELF__"); 836 if (Opts.POSIXThreads) 837 Builder.defineMacro("_REENTRANT"); 838 // Required by the libc++ locale support. 839 if (Opts.CPlusPlus) 840 Builder.defineMacro("_GNU_SOURCE"); 841 } 842 public: 843 FuchsiaTargetInfo(const llvm::Triple &Triple, 844 const TargetOptions &Opts) 845 : OSTargetInfo<Target>(Triple, Opts) { 846 this->MCountName = "__mcount"; 847 } 848 }; 849 850 // WebAssembly target 851 template <typename Target> 852 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 853 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 854 MacroBuilder &Builder) const final { 855 // A common platform macro. 856 if (Opts.POSIXThreads) 857 Builder.defineMacro("_REENTRANT"); 858 // Follow g++ convention and predefine _GNU_SOURCE for C++. 859 if (Opts.CPlusPlus) 860 Builder.defineMacro("_GNU_SOURCE"); 861 } 862 863 // As an optimization, group static init code together in a section. 864 const char *getStaticInitSectionSpecifier() const final { 865 return ".text.__startup"; 866 } 867 868 public: 869 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 870 const TargetOptions &Opts) 871 : OSTargetInfo<Target>(Triple, Opts) { 872 this->MCountName = "__mcount"; 873 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 874 } 875 }; 876 877 //===----------------------------------------------------------------------===// 878 // Specific target implementations. 879 //===----------------------------------------------------------------------===// 880 881 // PPC abstract base class 882 class PPCTargetInfo : public TargetInfo { 883 static const Builtin::Info BuiltinInfo[]; 884 static const char * const GCCRegNames[]; 885 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 886 std::string CPU; 887 888 // Target cpu features. 889 bool HasVSX; 890 bool HasP8Vector; 891 bool HasP8Crypto; 892 bool HasDirectMove; 893 bool HasQPX; 894 bool HasHTM; 895 bool HasBPERMD; 896 bool HasExtDiv; 897 bool HasP9Vector; 898 899 protected: 900 std::string ABI; 901 902 public: 903 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 904 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 905 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 906 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) { 907 SimdDefaultAlign = 128; 908 LongDoubleWidth = LongDoubleAlign = 128; 909 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 910 } 911 912 /// \brief Flags for architecture specific defines. 913 typedef enum { 914 ArchDefineNone = 0, 915 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 916 ArchDefinePpcgr = 1 << 1, 917 ArchDefinePpcsq = 1 << 2, 918 ArchDefine440 = 1 << 3, 919 ArchDefine603 = 1 << 4, 920 ArchDefine604 = 1 << 5, 921 ArchDefinePwr4 = 1 << 6, 922 ArchDefinePwr5 = 1 << 7, 923 ArchDefinePwr5x = 1 << 8, 924 ArchDefinePwr6 = 1 << 9, 925 ArchDefinePwr6x = 1 << 10, 926 ArchDefinePwr7 = 1 << 11, 927 ArchDefinePwr8 = 1 << 12, 928 ArchDefinePwr9 = 1 << 13, 929 ArchDefineA2 = 1 << 14, 930 ArchDefineA2q = 1 << 15 931 } ArchDefineTypes; 932 933 // Note: GCC recognizes the following additional cpus: 934 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 935 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 936 // titan, rs64. 937 bool setCPU(const std::string &Name) override { 938 bool CPUKnown = llvm::StringSwitch<bool>(Name) 939 .Case("generic", true) 940 .Case("440", true) 941 .Case("450", true) 942 .Case("601", true) 943 .Case("602", true) 944 .Case("603", true) 945 .Case("603e", true) 946 .Case("603ev", true) 947 .Case("604", true) 948 .Case("604e", true) 949 .Case("620", true) 950 .Case("630", true) 951 .Case("g3", true) 952 .Case("7400", true) 953 .Case("g4", true) 954 .Case("7450", true) 955 .Case("g4+", true) 956 .Case("750", true) 957 .Case("970", true) 958 .Case("g5", true) 959 .Case("a2", true) 960 .Case("a2q", true) 961 .Case("e500mc", true) 962 .Case("e5500", true) 963 .Case("power3", true) 964 .Case("pwr3", true) 965 .Case("power4", true) 966 .Case("pwr4", true) 967 .Case("power5", true) 968 .Case("pwr5", true) 969 .Case("power5x", true) 970 .Case("pwr5x", true) 971 .Case("power6", true) 972 .Case("pwr6", true) 973 .Case("power6x", true) 974 .Case("pwr6x", true) 975 .Case("power7", true) 976 .Case("pwr7", true) 977 .Case("power8", true) 978 .Case("pwr8", true) 979 .Case("power9", true) 980 .Case("pwr9", true) 981 .Case("powerpc", true) 982 .Case("ppc", true) 983 .Case("powerpc64", true) 984 .Case("ppc64", true) 985 .Case("powerpc64le", true) 986 .Case("ppc64le", true) 987 .Default(false); 988 989 if (CPUKnown) 990 CPU = Name; 991 992 return CPUKnown; 993 } 994 995 996 StringRef getABI() const override { return ABI; } 997 998 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 999 return llvm::makeArrayRef(BuiltinInfo, 1000 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 1001 } 1002 1003 bool isCLZForZeroUndef() const override { return false; } 1004 1005 void getTargetDefines(const LangOptions &Opts, 1006 MacroBuilder &Builder) const override; 1007 1008 bool 1009 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1010 StringRef CPU, 1011 const std::vector<std::string> &FeaturesVec) const override; 1012 1013 bool handleTargetFeatures(std::vector<std::string> &Features, 1014 DiagnosticsEngine &Diags) override; 1015 bool hasFeature(StringRef Feature) const override; 1016 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 1017 bool Enabled) const override; 1018 1019 ArrayRef<const char *> getGCCRegNames() const override; 1020 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 1021 bool validateAsmConstraint(const char *&Name, 1022 TargetInfo::ConstraintInfo &Info) const override { 1023 switch (*Name) { 1024 default: return false; 1025 case 'O': // Zero 1026 break; 1027 case 'b': // Base register 1028 case 'f': // Floating point register 1029 Info.setAllowsRegister(); 1030 break; 1031 // FIXME: The following are added to allow parsing. 1032 // I just took a guess at what the actions should be. 1033 // Also, is more specific checking needed? I.e. specific registers? 1034 case 'd': // Floating point register (containing 64-bit value) 1035 case 'v': // Altivec vector register 1036 Info.setAllowsRegister(); 1037 break; 1038 case 'w': 1039 switch (Name[1]) { 1040 case 'd':// VSX vector register to hold vector double data 1041 case 'f':// VSX vector register to hold vector float data 1042 case 's':// VSX vector register to hold scalar float data 1043 case 'a':// Any VSX register 1044 case 'c':// An individual CR bit 1045 break; 1046 default: 1047 return false; 1048 } 1049 Info.setAllowsRegister(); 1050 Name++; // Skip over 'w'. 1051 break; 1052 case 'h': // `MQ', `CTR', or `LINK' register 1053 case 'q': // `MQ' register 1054 case 'c': // `CTR' register 1055 case 'l': // `LINK' register 1056 case 'x': // `CR' register (condition register) number 0 1057 case 'y': // `CR' register (condition register) 1058 case 'z': // `XER[CA]' carry bit (part of the XER register) 1059 Info.setAllowsRegister(); 1060 break; 1061 case 'I': // Signed 16-bit constant 1062 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1063 // (use `L' instead for SImode constants) 1064 case 'K': // Unsigned 16-bit constant 1065 case 'L': // Signed 16-bit constant shifted left 16 bits 1066 case 'M': // Constant larger than 31 1067 case 'N': // Exact power of 2 1068 case 'P': // Constant whose negation is a signed 16-bit constant 1069 case 'G': // Floating point constant that can be loaded into a 1070 // register with one instruction per word 1071 case 'H': // Integer/Floating point constant that can be loaded 1072 // into a register using three instructions 1073 break; 1074 case 'm': // Memory operand. Note that on PowerPC targets, m can 1075 // include addresses that update the base register. It 1076 // is therefore only safe to use `m' in an asm statement 1077 // if that asm statement accesses the operand exactly once. 1078 // The asm statement must also use `%U<opno>' as a 1079 // placeholder for the "update" flag in the corresponding 1080 // load or store instruction. For example: 1081 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1082 // is correct but: 1083 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1084 // is not. Use es rather than m if you don't want the base 1085 // register to be updated. 1086 case 'e': 1087 if (Name[1] != 's') 1088 return false; 1089 // es: A "stable" memory operand; that is, one which does not 1090 // include any automodification of the base register. Unlike 1091 // `m', this constraint can be used in asm statements that 1092 // might access the operand several times, or that might not 1093 // access it at all. 1094 Info.setAllowsMemory(); 1095 Name++; // Skip over 'e'. 1096 break; 1097 case 'Q': // Memory operand that is an offset from a register (it is 1098 // usually better to use `m' or `es' in asm statements) 1099 case 'Z': // Memory operand that is an indexed or indirect from a 1100 // register (it is usually better to use `m' or `es' in 1101 // asm statements) 1102 Info.setAllowsMemory(); 1103 Info.setAllowsRegister(); 1104 break; 1105 case 'R': // AIX TOC entry 1106 case 'a': // Address operand that is an indexed or indirect from a 1107 // register (`p' is preferable for asm statements) 1108 case 'S': // Constant suitable as a 64-bit mask operand 1109 case 'T': // Constant suitable as a 32-bit mask operand 1110 case 'U': // System V Release 4 small data area reference 1111 case 't': // AND masks that can be performed by two rldic{l, r} 1112 // instructions 1113 case 'W': // Vector constant that does not require memory 1114 case 'j': // Vector constant that is all zeros. 1115 break; 1116 // End FIXME. 1117 } 1118 return true; 1119 } 1120 std::string convertConstraint(const char *&Constraint) const override { 1121 std::string R; 1122 switch (*Constraint) { 1123 case 'e': 1124 case 'w': 1125 // Two-character constraint; add "^" hint for later parsing. 1126 R = std::string("^") + std::string(Constraint, 2); 1127 Constraint++; 1128 break; 1129 default: 1130 return TargetInfo::convertConstraint(Constraint); 1131 } 1132 return R; 1133 } 1134 const char *getClobbers() const override { 1135 return ""; 1136 } 1137 int getEHDataRegisterNumber(unsigned RegNo) const override { 1138 if (RegNo == 0) return 3; 1139 if (RegNo == 1) return 4; 1140 return -1; 1141 } 1142 1143 bool hasSjLjLowering() const override { 1144 return true; 1145 } 1146 1147 bool useFloat128ManglingForLongDouble() const override { 1148 return LongDoubleWidth == 128 && 1149 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1150 getTriple().isOSBinFormatELF(); 1151 } 1152 }; 1153 1154 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1155 #define BUILTIN(ID, TYPE, ATTRS) \ 1156 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1157 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1158 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1159 #include "clang/Basic/BuiltinsPPC.def" 1160 }; 1161 1162 /// handleTargetFeatures - Perform initialization based on the user 1163 /// configured set of features. 1164 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1165 DiagnosticsEngine &Diags) { 1166 for (const auto &Feature : Features) { 1167 if (Feature == "+vsx") { 1168 HasVSX = true; 1169 } else if (Feature == "+bpermd") { 1170 HasBPERMD = true; 1171 } else if (Feature == "+extdiv") { 1172 HasExtDiv = true; 1173 } else if (Feature == "+power8-vector") { 1174 HasP8Vector = true; 1175 } else if (Feature == "+crypto") { 1176 HasP8Crypto = true; 1177 } else if (Feature == "+direct-move") { 1178 HasDirectMove = true; 1179 } else if (Feature == "+qpx") { 1180 HasQPX = true; 1181 } else if (Feature == "+htm") { 1182 HasHTM = true; 1183 } else if (Feature == "+float128") { 1184 HasFloat128 = true; 1185 } else if (Feature == "+power9-vector") { 1186 HasP9Vector = true; 1187 } 1188 // TODO: Finish this list and add an assert that we've handled them 1189 // all. 1190 } 1191 1192 return true; 1193 } 1194 1195 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1196 /// #defines that are not tied to a specific subtarget. 1197 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1198 MacroBuilder &Builder) const { 1199 // Target identification. 1200 Builder.defineMacro("__ppc__"); 1201 Builder.defineMacro("__PPC__"); 1202 Builder.defineMacro("_ARCH_PPC"); 1203 Builder.defineMacro("__powerpc__"); 1204 Builder.defineMacro("__POWERPC__"); 1205 if (PointerWidth == 64) { 1206 Builder.defineMacro("_ARCH_PPC64"); 1207 Builder.defineMacro("__powerpc64__"); 1208 Builder.defineMacro("__ppc64__"); 1209 Builder.defineMacro("__PPC64__"); 1210 } 1211 1212 // Target properties. 1213 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1214 Builder.defineMacro("_LITTLE_ENDIAN"); 1215 } else { 1216 if (getTriple().getOS() != llvm::Triple::NetBSD && 1217 getTriple().getOS() != llvm::Triple::OpenBSD) 1218 Builder.defineMacro("_BIG_ENDIAN"); 1219 } 1220 1221 // ABI options. 1222 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1223 Builder.defineMacro("_CALL_ELF", "1"); 1224 if (ABI == "elfv2") 1225 Builder.defineMacro("_CALL_ELF", "2"); 1226 1227 // Subtarget options. 1228 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1229 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1230 1231 // FIXME: Should be controlled by command line option. 1232 if (LongDoubleWidth == 128) 1233 Builder.defineMacro("__LONG_DOUBLE_128__"); 1234 1235 if (Opts.AltiVec) { 1236 Builder.defineMacro("__VEC__", "10206"); 1237 Builder.defineMacro("__ALTIVEC__"); 1238 } 1239 1240 // CPU identification. 1241 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1242 .Case("440", ArchDefineName) 1243 .Case("450", ArchDefineName | ArchDefine440) 1244 .Case("601", ArchDefineName) 1245 .Case("602", ArchDefineName | ArchDefinePpcgr) 1246 .Case("603", ArchDefineName | ArchDefinePpcgr) 1247 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1248 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1249 .Case("604", ArchDefineName | ArchDefinePpcgr) 1250 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1251 .Case("620", ArchDefineName | ArchDefinePpcgr) 1252 .Case("630", ArchDefineName | ArchDefinePpcgr) 1253 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1254 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1255 .Case("750", ArchDefineName | ArchDefinePpcgr) 1256 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1257 | ArchDefinePpcsq) 1258 .Case("a2", ArchDefineA2) 1259 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1260 .Case("pwr3", ArchDefinePpcgr) 1261 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1262 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1263 | ArchDefinePpcsq) 1264 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1265 | ArchDefinePpcgr | ArchDefinePpcsq) 1266 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1267 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1268 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1269 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1270 | ArchDefinePpcsq) 1271 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1272 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1273 | ArchDefinePpcgr | ArchDefinePpcsq) 1274 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1275 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1276 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1277 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 1278 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1279 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1280 | ArchDefinePpcsq) 1281 .Case("power3", ArchDefinePpcgr) 1282 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1283 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1284 | ArchDefinePpcsq) 1285 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1286 | ArchDefinePpcgr | ArchDefinePpcsq) 1287 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1288 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1289 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1290 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1291 | ArchDefinePpcsq) 1292 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1293 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1294 | ArchDefinePpcgr | ArchDefinePpcsq) 1295 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1296 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1297 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1298 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 1299 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1300 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1301 | ArchDefinePpcsq) 1302 .Default(ArchDefineNone); 1303 1304 if (defs & ArchDefineName) 1305 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1306 if (defs & ArchDefinePpcgr) 1307 Builder.defineMacro("_ARCH_PPCGR"); 1308 if (defs & ArchDefinePpcsq) 1309 Builder.defineMacro("_ARCH_PPCSQ"); 1310 if (defs & ArchDefine440) 1311 Builder.defineMacro("_ARCH_440"); 1312 if (defs & ArchDefine603) 1313 Builder.defineMacro("_ARCH_603"); 1314 if (defs & ArchDefine604) 1315 Builder.defineMacro("_ARCH_604"); 1316 if (defs & ArchDefinePwr4) 1317 Builder.defineMacro("_ARCH_PWR4"); 1318 if (defs & ArchDefinePwr5) 1319 Builder.defineMacro("_ARCH_PWR5"); 1320 if (defs & ArchDefinePwr5x) 1321 Builder.defineMacro("_ARCH_PWR5X"); 1322 if (defs & ArchDefinePwr6) 1323 Builder.defineMacro("_ARCH_PWR6"); 1324 if (defs & ArchDefinePwr6x) 1325 Builder.defineMacro("_ARCH_PWR6X"); 1326 if (defs & ArchDefinePwr7) 1327 Builder.defineMacro("_ARCH_PWR7"); 1328 if (defs & ArchDefinePwr8) 1329 Builder.defineMacro("_ARCH_PWR8"); 1330 if (defs & ArchDefinePwr9) 1331 Builder.defineMacro("_ARCH_PWR9"); 1332 if (defs & ArchDefineA2) 1333 Builder.defineMacro("_ARCH_A2"); 1334 if (defs & ArchDefineA2q) { 1335 Builder.defineMacro("_ARCH_A2Q"); 1336 Builder.defineMacro("_ARCH_QP"); 1337 } 1338 1339 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1340 Builder.defineMacro("__bg__"); 1341 Builder.defineMacro("__THW_BLUEGENE__"); 1342 Builder.defineMacro("__bgq__"); 1343 Builder.defineMacro("__TOS_BGQ__"); 1344 } 1345 1346 if (HasVSX) 1347 Builder.defineMacro("__VSX__"); 1348 if (HasP8Vector) 1349 Builder.defineMacro("__POWER8_VECTOR__"); 1350 if (HasP8Crypto) 1351 Builder.defineMacro("__CRYPTO__"); 1352 if (HasHTM) 1353 Builder.defineMacro("__HTM__"); 1354 if (HasFloat128) 1355 Builder.defineMacro("__FLOAT128__"); 1356 if (HasP9Vector) 1357 Builder.defineMacro("__POWER9_VECTOR__"); 1358 1359 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1360 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1361 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1362 if (PointerWidth == 64) 1363 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1364 1365 // FIXME: The following are not yet generated here by Clang, but are 1366 // generated by GCC: 1367 // 1368 // _SOFT_FLOAT_ 1369 // __RECIP_PRECISION__ 1370 // __APPLE_ALTIVEC__ 1371 // __RECIP__ 1372 // __RECIPF__ 1373 // __RSQRTE__ 1374 // __RSQRTEF__ 1375 // _SOFT_DOUBLE_ 1376 // __NO_LWSYNC__ 1377 // __HAVE_BSWAP__ 1378 // __LONGDOUBLE128 1379 // __CMODEL_MEDIUM__ 1380 // __CMODEL_LARGE__ 1381 // _CALL_SYSV 1382 // _CALL_DARWIN 1383 // __NO_FPRS__ 1384 } 1385 1386 // Handle explicit options being passed to the compiler here: if we've 1387 // explicitly turned off vsx and turned on any of: 1388 // - power8-vector 1389 // - direct-move 1390 // - float128 1391 // - power9-vector 1392 // then go ahead and error since the customer has expressed an incompatible 1393 // set of options. 1394 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1395 const std::vector<std::string> &FeaturesVec) { 1396 1397 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1398 FeaturesVec.end()) { 1399 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1400 FeaturesVec.end()) { 1401 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1402 << "-mno-vsx"; 1403 return false; 1404 } 1405 1406 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1407 FeaturesVec.end()) { 1408 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1409 << "-mno-vsx"; 1410 return false; 1411 } 1412 1413 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1414 FeaturesVec.end()) { 1415 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1416 << "-mno-vsx"; 1417 return false; 1418 } 1419 1420 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") != 1421 FeaturesVec.end()) { 1422 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector" 1423 << "-mno-vsx"; 1424 return false; 1425 } 1426 } 1427 1428 return true; 1429 } 1430 1431 bool PPCTargetInfo::initFeatureMap( 1432 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1433 const std::vector<std::string> &FeaturesVec) const { 1434 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1435 .Case("7400", true) 1436 .Case("g4", true) 1437 .Case("7450", true) 1438 .Case("g4+", true) 1439 .Case("970", true) 1440 .Case("g5", true) 1441 .Case("pwr6", true) 1442 .Case("pwr7", true) 1443 .Case("pwr8", true) 1444 .Case("pwr9", true) 1445 .Case("ppc64", true) 1446 .Case("ppc64le", true) 1447 .Default(false); 1448 1449 Features["qpx"] = (CPU == "a2q"); 1450 Features["power9-vector"] = (CPU == "pwr9"); 1451 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1452 .Case("ppc64le", true) 1453 .Case("pwr9", true) 1454 .Case("pwr8", true) 1455 .Default(false); 1456 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1457 .Case("ppc64le", true) 1458 .Case("pwr9", true) 1459 .Case("pwr8", true) 1460 .Default(false); 1461 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1462 .Case("ppc64le", true) 1463 .Case("pwr9", true) 1464 .Case("pwr8", true) 1465 .Case("pwr7", true) 1466 .Default(false); 1467 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1468 .Case("ppc64le", true) 1469 .Case("pwr9", true) 1470 .Case("pwr8", true) 1471 .Case("pwr7", true) 1472 .Default(false); 1473 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1474 .Case("ppc64le", true) 1475 .Case("pwr9", true) 1476 .Case("pwr8", true) 1477 .Default(false); 1478 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1479 .Case("ppc64le", true) 1480 .Case("pwr9", true) 1481 .Case("pwr8", true) 1482 .Case("pwr7", true) 1483 .Default(false); 1484 1485 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1486 return false; 1487 1488 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1489 } 1490 1491 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1492 return llvm::StringSwitch<bool>(Feature) 1493 .Case("powerpc", true) 1494 .Case("vsx", HasVSX) 1495 .Case("power8-vector", HasP8Vector) 1496 .Case("crypto", HasP8Crypto) 1497 .Case("direct-move", HasDirectMove) 1498 .Case("qpx", HasQPX) 1499 .Case("htm", HasHTM) 1500 .Case("bpermd", HasBPERMD) 1501 .Case("extdiv", HasExtDiv) 1502 .Case("float128", HasFloat128) 1503 .Case("power9-vector", HasP9Vector) 1504 .Default(false); 1505 } 1506 1507 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1508 StringRef Name, bool Enabled) const { 1509 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1510 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1511 // incompatible options. 1512 if (Enabled) { 1513 if (Name == "direct-move" || 1514 Name == "power8-vector" || 1515 Name == "float128" || 1516 Name == "power9-vector") { 1517 // power9-vector is really a superset of power8-vector so encode that. 1518 Features[Name] = Features["vsx"] = true; 1519 if (Name == "power9-vector") 1520 Features["power8-vector"] = true; 1521 } else { 1522 Features[Name] = true; 1523 } 1524 } else { 1525 if (Name == "vsx") { 1526 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1527 Features["float128"] = Features["power9-vector"] = false; 1528 } else { 1529 Features[Name] = false; 1530 } 1531 } 1532 } 1533 1534 const char * const PPCTargetInfo::GCCRegNames[] = { 1535 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1536 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1537 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1538 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1539 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1540 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1541 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1542 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1543 "mq", "lr", "ctr", "ap", 1544 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1545 "xer", 1546 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1547 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1548 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1549 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1550 "vrsave", "vscr", 1551 "spe_acc", "spefscr", 1552 "sfp" 1553 }; 1554 1555 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1556 return llvm::makeArrayRef(GCCRegNames); 1557 } 1558 1559 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1560 // While some of these aliases do map to different registers 1561 // they still share the same register name. 1562 { { "0" }, "r0" }, 1563 { { "1"}, "r1" }, 1564 { { "2" }, "r2" }, 1565 { { "3" }, "r3" }, 1566 { { "4" }, "r4" }, 1567 { { "5" }, "r5" }, 1568 { { "6" }, "r6" }, 1569 { { "7" }, "r7" }, 1570 { { "8" }, "r8" }, 1571 { { "9" }, "r9" }, 1572 { { "10" }, "r10" }, 1573 { { "11" }, "r11" }, 1574 { { "12" }, "r12" }, 1575 { { "13" }, "r13" }, 1576 { { "14" }, "r14" }, 1577 { { "15" }, "r15" }, 1578 { { "16" }, "r16" }, 1579 { { "17" }, "r17" }, 1580 { { "18" }, "r18" }, 1581 { { "19" }, "r19" }, 1582 { { "20" }, "r20" }, 1583 { { "21" }, "r21" }, 1584 { { "22" }, "r22" }, 1585 { { "23" }, "r23" }, 1586 { { "24" }, "r24" }, 1587 { { "25" }, "r25" }, 1588 { { "26" }, "r26" }, 1589 { { "27" }, "r27" }, 1590 { { "28" }, "r28" }, 1591 { { "29" }, "r29" }, 1592 { { "30" }, "r30" }, 1593 { { "31" }, "r31" }, 1594 { { "fr0" }, "f0" }, 1595 { { "fr1" }, "f1" }, 1596 { { "fr2" }, "f2" }, 1597 { { "fr3" }, "f3" }, 1598 { { "fr4" }, "f4" }, 1599 { { "fr5" }, "f5" }, 1600 { { "fr6" }, "f6" }, 1601 { { "fr7" }, "f7" }, 1602 { { "fr8" }, "f8" }, 1603 { { "fr9" }, "f9" }, 1604 { { "fr10" }, "f10" }, 1605 { { "fr11" }, "f11" }, 1606 { { "fr12" }, "f12" }, 1607 { { "fr13" }, "f13" }, 1608 { { "fr14" }, "f14" }, 1609 { { "fr15" }, "f15" }, 1610 { { "fr16" }, "f16" }, 1611 { { "fr17" }, "f17" }, 1612 { { "fr18" }, "f18" }, 1613 { { "fr19" }, "f19" }, 1614 { { "fr20" }, "f20" }, 1615 { { "fr21" }, "f21" }, 1616 { { "fr22" }, "f22" }, 1617 { { "fr23" }, "f23" }, 1618 { { "fr24" }, "f24" }, 1619 { { "fr25" }, "f25" }, 1620 { { "fr26" }, "f26" }, 1621 { { "fr27" }, "f27" }, 1622 { { "fr28" }, "f28" }, 1623 { { "fr29" }, "f29" }, 1624 { { "fr30" }, "f30" }, 1625 { { "fr31" }, "f31" }, 1626 { { "cc" }, "cr0" }, 1627 }; 1628 1629 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1630 return llvm::makeArrayRef(GCCRegAliases); 1631 } 1632 1633 class PPC32TargetInfo : public PPCTargetInfo { 1634 public: 1635 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1636 : PPCTargetInfo(Triple, Opts) { 1637 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1638 1639 switch (getTriple().getOS()) { 1640 case llvm::Triple::Linux: 1641 case llvm::Triple::FreeBSD: 1642 case llvm::Triple::NetBSD: 1643 SizeType = UnsignedInt; 1644 PtrDiffType = SignedInt; 1645 IntPtrType = SignedInt; 1646 break; 1647 default: 1648 break; 1649 } 1650 1651 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1652 LongDoubleWidth = LongDoubleAlign = 64; 1653 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1654 } 1655 1656 // PPC32 supports atomics up to 4 bytes. 1657 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1658 } 1659 1660 BuiltinVaListKind getBuiltinVaListKind() const override { 1661 // This is the ELF definition, and is overridden by the Darwin sub-target 1662 return TargetInfo::PowerABIBuiltinVaList; 1663 } 1664 }; 1665 1666 // Note: ABI differences may eventually require us to have a separate 1667 // TargetInfo for little endian. 1668 class PPC64TargetInfo : public PPCTargetInfo { 1669 public: 1670 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1671 : PPCTargetInfo(Triple, Opts) { 1672 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1673 IntMaxType = SignedLong; 1674 Int64Type = SignedLong; 1675 1676 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1677 resetDataLayout("e-m:e-i64:64-n32:64"); 1678 ABI = "elfv2"; 1679 } else { 1680 resetDataLayout("E-m:e-i64:64-n32:64"); 1681 ABI = "elfv1"; 1682 } 1683 1684 switch (getTriple().getOS()) { 1685 case llvm::Triple::FreeBSD: 1686 LongDoubleWidth = LongDoubleAlign = 64; 1687 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1688 break; 1689 case llvm::Triple::NetBSD: 1690 IntMaxType = SignedLongLong; 1691 Int64Type = SignedLongLong; 1692 break; 1693 default: 1694 break; 1695 } 1696 1697 // PPC64 supports atomics up to 8 bytes. 1698 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1699 } 1700 BuiltinVaListKind getBuiltinVaListKind() const override { 1701 return TargetInfo::CharPtrBuiltinVaList; 1702 } 1703 // PPC64 Linux-specific ABI options. 1704 bool setABI(const std::string &Name) override { 1705 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1706 ABI = Name; 1707 return true; 1708 } 1709 return false; 1710 } 1711 }; 1712 1713 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1714 public: 1715 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1716 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1717 HasAlignMac68kSupport = true; 1718 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1719 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1720 LongLongAlign = 32; 1721 SuitableAlign = 128; 1722 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1723 } 1724 BuiltinVaListKind getBuiltinVaListKind() const override { 1725 return TargetInfo::CharPtrBuiltinVaList; 1726 } 1727 }; 1728 1729 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1730 public: 1731 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1732 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1733 HasAlignMac68kSupport = true; 1734 SuitableAlign = 128; 1735 resetDataLayout("E-m:o-i64:64-n32:64"); 1736 } 1737 }; 1738 1739 static const unsigned NVPTXAddrSpaceMap[] = { 1740 1, // opencl_global 1741 3, // opencl_local 1742 4, // opencl_constant 1743 // FIXME: generic has to be added to the target 1744 0, // opencl_generic 1745 1, // cuda_device 1746 4, // cuda_constant 1747 3, // cuda_shared 1748 }; 1749 1750 class NVPTXTargetInfo : public TargetInfo { 1751 static const char *const GCCRegNames[]; 1752 static const Builtin::Info BuiltinInfo[]; 1753 CudaArch GPU; 1754 1755 public: 1756 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1757 : TargetInfo(Triple) { 1758 TLSSupported = false; 1759 LongWidth = LongAlign = 64; 1760 AddrSpaceMap = &NVPTXAddrSpaceMap; 1761 UseAddrSpaceMapMangling = true; 1762 // Define available target features 1763 // These must be defined in sorted order! 1764 NoAsmVariants = true; 1765 GPU = CudaArch::SM_20; 1766 1767 // If possible, get a TargetInfo for our host triple, so we can match its 1768 // types. 1769 llvm::Triple HostTriple(Opts.HostTriple); 1770 if (HostTriple.isNVPTX()) 1771 return; 1772 std::unique_ptr<TargetInfo> HostTarget( 1773 AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1774 if (!HostTarget) { 1775 return; 1776 } 1777 1778 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1779 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1780 BoolWidth = HostTarget->getBoolWidth(); 1781 BoolAlign = HostTarget->getBoolAlign(); 1782 IntWidth = HostTarget->getIntWidth(); 1783 IntAlign = HostTarget->getIntAlign(); 1784 HalfWidth = HostTarget->getHalfWidth(); 1785 HalfAlign = HostTarget->getHalfAlign(); 1786 FloatWidth = HostTarget->getFloatWidth(); 1787 FloatAlign = HostTarget->getFloatAlign(); 1788 DoubleWidth = HostTarget->getDoubleWidth(); 1789 DoubleAlign = HostTarget->getDoubleAlign(); 1790 LongWidth = HostTarget->getLongWidth(); 1791 LongAlign = HostTarget->getLongAlign(); 1792 LongLongWidth = HostTarget->getLongLongWidth(); 1793 LongLongAlign = HostTarget->getLongLongAlign(); 1794 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1795 NewAlign = HostTarget->getNewAlign(); 1796 DefaultAlignForAttributeAligned = 1797 HostTarget->getDefaultAlignForAttributeAligned(); 1798 SizeType = HostTarget->getSizeType(); 1799 IntMaxType = HostTarget->getIntMaxType(); 1800 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1801 IntPtrType = HostTarget->getIntPtrType(); 1802 WCharType = HostTarget->getWCharType(); 1803 WIntType = HostTarget->getWIntType(); 1804 Char16Type = HostTarget->getChar16Type(); 1805 Char32Type = HostTarget->getChar32Type(); 1806 Int64Type = HostTarget->getInt64Type(); 1807 SigAtomicType = HostTarget->getSigAtomicType(); 1808 ProcessIDType = HostTarget->getProcessIDType(); 1809 1810 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1811 UseZeroLengthBitfieldAlignment = 1812 HostTarget->useZeroLengthBitfieldAlignment(); 1813 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1814 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1815 1816 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and 1817 // we need those macros to be identical on host and device, because (among 1818 // other things) they affect which standard library classes are defined, and 1819 // we need all classes to be defined on both the host and device. 1820 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth(); 1821 1822 // Properties intentionally not copied from host: 1823 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1824 // host/device boundary. 1825 // - SuitableAlign: Not visible across the host/device boundary, and may 1826 // correctly be different on host/device, e.g. if host has wider vector 1827 // types than device. 1828 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1829 // as its double type, but that's not necessarily true on the host. 1830 // TODO: nvcc emits a warning when using long double on device; we should 1831 // do the same. 1832 } 1833 void getTargetDefines(const LangOptions &Opts, 1834 MacroBuilder &Builder) const override { 1835 Builder.defineMacro("__PTX__"); 1836 Builder.defineMacro("__NVPTX__"); 1837 if (Opts.CUDAIsDevice) { 1838 // Set __CUDA_ARCH__ for the GPU specified. 1839 std::string CUDAArchCode = [this] { 1840 switch (GPU) { 1841 case CudaArch::UNKNOWN: 1842 assert(false && "No GPU arch when compiling CUDA device code."); 1843 return ""; 1844 case CudaArch::SM_20: 1845 return "200"; 1846 case CudaArch::SM_21: 1847 return "210"; 1848 case CudaArch::SM_30: 1849 return "300"; 1850 case CudaArch::SM_32: 1851 return "320"; 1852 case CudaArch::SM_35: 1853 return "350"; 1854 case CudaArch::SM_37: 1855 return "370"; 1856 case CudaArch::SM_50: 1857 return "500"; 1858 case CudaArch::SM_52: 1859 return "520"; 1860 case CudaArch::SM_53: 1861 return "530"; 1862 case CudaArch::SM_60: 1863 return "600"; 1864 case CudaArch::SM_61: 1865 return "610"; 1866 case CudaArch::SM_62: 1867 return "620"; 1868 } 1869 llvm_unreachable("unhandled CudaArch"); 1870 }(); 1871 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1872 } 1873 } 1874 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1875 return llvm::makeArrayRef(BuiltinInfo, 1876 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1877 } 1878 bool 1879 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1880 StringRef CPU, 1881 const std::vector<std::string> &FeaturesVec) const override { 1882 Features["satom"] = GPU >= CudaArch::SM_60; 1883 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1884 } 1885 1886 bool hasFeature(StringRef Feature) const override { 1887 return llvm::StringSwitch<bool>(Feature) 1888 .Cases("ptx", "nvptx", true) 1889 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope. 1890 .Default(false); 1891 } 1892 1893 ArrayRef<const char *> getGCCRegNames() const override; 1894 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1895 // No aliases. 1896 return None; 1897 } 1898 bool validateAsmConstraint(const char *&Name, 1899 TargetInfo::ConstraintInfo &Info) const override { 1900 switch (*Name) { 1901 default: 1902 return false; 1903 case 'c': 1904 case 'h': 1905 case 'r': 1906 case 'l': 1907 case 'f': 1908 case 'd': 1909 Info.setAllowsRegister(); 1910 return true; 1911 } 1912 } 1913 const char *getClobbers() const override { 1914 // FIXME: Is this really right? 1915 return ""; 1916 } 1917 BuiltinVaListKind getBuiltinVaListKind() const override { 1918 // FIXME: implement 1919 return TargetInfo::CharPtrBuiltinVaList; 1920 } 1921 bool setCPU(const std::string &Name) override { 1922 GPU = StringToCudaArch(Name); 1923 return GPU != CudaArch::UNKNOWN; 1924 } 1925 void setSupportedOpenCLOpts() override { 1926 auto &Opts = getSupportedOpenCLOpts(); 1927 Opts.cl_clang_storage_class_specifiers = 1; 1928 Opts.cl_khr_gl_sharing = 1; 1929 Opts.cl_khr_icd = 1; 1930 1931 Opts.cl_khr_fp64 = 1; 1932 Opts.cl_khr_byte_addressable_store = 1; 1933 Opts.cl_khr_global_int32_base_atomics = 1; 1934 Opts.cl_khr_global_int32_extended_atomics = 1; 1935 Opts.cl_khr_local_int32_base_atomics = 1; 1936 Opts.cl_khr_local_int32_extended_atomics = 1; 1937 } 1938 }; 1939 1940 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1941 #define BUILTIN(ID, TYPE, ATTRS) \ 1942 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1943 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1944 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1945 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 1946 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 1947 #include "clang/Basic/BuiltinsNVPTX.def" 1948 }; 1949 1950 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1951 1952 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1953 return llvm::makeArrayRef(GCCRegNames); 1954 } 1955 1956 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1957 public: 1958 NVPTX32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1959 : NVPTXTargetInfo(Triple, Opts) { 1960 LongWidth = LongAlign = 32; 1961 PointerWidth = PointerAlign = 32; 1962 SizeType = TargetInfo::UnsignedInt; 1963 PtrDiffType = TargetInfo::SignedInt; 1964 IntPtrType = TargetInfo::SignedInt; 1965 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1966 } 1967 }; 1968 1969 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1970 public: 1971 NVPTX64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1972 : NVPTXTargetInfo(Triple, Opts) { 1973 PointerWidth = PointerAlign = 64; 1974 SizeType = TargetInfo::UnsignedLong; 1975 PtrDiffType = TargetInfo::SignedLong; 1976 IntPtrType = TargetInfo::SignedLong; 1977 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1978 } 1979 }; 1980 1981 static const unsigned AMDGPUAddrSpaceMap[] = { 1982 1, // opencl_global 1983 3, // opencl_local 1984 2, // opencl_constant 1985 4, // opencl_generic 1986 1, // cuda_device 1987 2, // cuda_constant 1988 3 // cuda_shared 1989 }; 1990 1991 // If you edit the description strings, make sure you update 1992 // getPointerWidthV(). 1993 1994 static const char *const DataLayoutStringR600 = 1995 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1996 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1997 1998 static const char *const DataLayoutStringSI = 1999 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 2000 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2001 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2002 2003 class AMDGPUTargetInfo final : public TargetInfo { 2004 static const Builtin::Info BuiltinInfo[]; 2005 static const char * const GCCRegNames[]; 2006 2007 /// \brief The GPU profiles supported by the AMDGPU target. 2008 enum GPUKind { 2009 GK_NONE, 2010 GK_R600, 2011 GK_R600_DOUBLE_OPS, 2012 GK_R700, 2013 GK_R700_DOUBLE_OPS, 2014 GK_EVERGREEN, 2015 GK_EVERGREEN_DOUBLE_OPS, 2016 GK_NORTHERN_ISLANDS, 2017 GK_CAYMAN, 2018 GK_GFX6, 2019 GK_GFX7, 2020 GK_GFX8 2021 } GPU; 2022 2023 bool hasFP64:1; 2024 bool hasFMAF:1; 2025 bool hasLDEXPF:1; 2026 bool hasFullSpeedFP32Denorms:1; 2027 2028 static bool isAMDGCN(const llvm::Triple &TT) { 2029 return TT.getArch() == llvm::Triple::amdgcn; 2030 } 2031 2032 public: 2033 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 2034 : TargetInfo(Triple) , 2035 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600), 2036 hasFP64(false), 2037 hasFMAF(false), 2038 hasLDEXPF(false), 2039 hasFullSpeedFP32Denorms(false){ 2040 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2041 hasFP64 = true; 2042 hasFMAF = true; 2043 hasLDEXPF = true; 2044 } 2045 2046 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 2047 DataLayoutStringSI : DataLayoutStringR600); 2048 2049 AddrSpaceMap = &AMDGPUAddrSpaceMap; 2050 UseAddrSpaceMapMangling = true; 2051 } 2052 2053 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 2054 if (GPU <= GK_CAYMAN) 2055 return 32; 2056 2057 switch(AddrSpace) { 2058 default: 2059 return 64; 2060 case 0: 2061 case 3: 2062 case 5: 2063 return 32; 2064 } 2065 } 2066 2067 uint64_t getMaxPointerWidth() const override { 2068 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2069 } 2070 2071 const char * getClobbers() const override { 2072 return ""; 2073 } 2074 2075 ArrayRef<const char *> getGCCRegNames() const override; 2076 2077 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2078 return None; 2079 } 2080 2081 bool validateAsmConstraint(const char *&Name, 2082 TargetInfo::ConstraintInfo &Info) const override { 2083 switch (*Name) { 2084 default: break; 2085 case 'v': // vgpr 2086 case 's': // sgpr 2087 Info.setAllowsRegister(); 2088 return true; 2089 } 2090 return false; 2091 } 2092 2093 bool initFeatureMap(llvm::StringMap<bool> &Features, 2094 DiagnosticsEngine &Diags, StringRef CPU, 2095 const std::vector<std::string> &FeatureVec) const override; 2096 2097 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2098 TargetOptions &TargetOpts) const override { 2099 bool hasFP32Denormals = false; 2100 bool hasFP64Denormals = false; 2101 for (auto &I : TargetOpts.FeaturesAsWritten) { 2102 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2103 hasFP32Denormals = true; 2104 if (I == "+fp64-denormals" || I == "-fp64-denormals") 2105 hasFP64Denormals = true; 2106 } 2107 if (!hasFP32Denormals) 2108 TargetOpts.Features.push_back((Twine(hasFullSpeedFP32Denorms && 2109 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str()); 2110 // Always do not flush fp64 denorms. 2111 if (!hasFP64Denormals && hasFP64) 2112 TargetOpts.Features.push_back("+fp64-denormals"); 2113 } 2114 2115 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2116 return llvm::makeArrayRef(BuiltinInfo, 2117 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2118 } 2119 2120 void getTargetDefines(const LangOptions &Opts, 2121 MacroBuilder &Builder) const override { 2122 if (getTriple().getArch() == llvm::Triple::amdgcn) 2123 Builder.defineMacro("__AMDGCN__"); 2124 else 2125 Builder.defineMacro("__R600__"); 2126 2127 if (hasFMAF) 2128 Builder.defineMacro("__HAS_FMAF__"); 2129 if (hasLDEXPF) 2130 Builder.defineMacro("__HAS_LDEXPF__"); 2131 if (hasFP64) 2132 Builder.defineMacro("__HAS_FP64__"); 2133 } 2134 2135 BuiltinVaListKind getBuiltinVaListKind() const override { 2136 return TargetInfo::CharPtrBuiltinVaList; 2137 } 2138 2139 static GPUKind parseR600Name(StringRef Name) { 2140 return llvm::StringSwitch<GPUKind>(Name) 2141 .Case("r600" , GK_R600) 2142 .Case("rv610", GK_R600) 2143 .Case("rv620", GK_R600) 2144 .Case("rv630", GK_R600) 2145 .Case("rv635", GK_R600) 2146 .Case("rs780", GK_R600) 2147 .Case("rs880", GK_R600) 2148 .Case("rv670", GK_R600_DOUBLE_OPS) 2149 .Case("rv710", GK_R700) 2150 .Case("rv730", GK_R700) 2151 .Case("rv740", GK_R700_DOUBLE_OPS) 2152 .Case("rv770", GK_R700_DOUBLE_OPS) 2153 .Case("palm", GK_EVERGREEN) 2154 .Case("cedar", GK_EVERGREEN) 2155 .Case("sumo", GK_EVERGREEN) 2156 .Case("sumo2", GK_EVERGREEN) 2157 .Case("redwood", GK_EVERGREEN) 2158 .Case("juniper", GK_EVERGREEN) 2159 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2160 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2161 .Case("barts", GK_NORTHERN_ISLANDS) 2162 .Case("turks", GK_NORTHERN_ISLANDS) 2163 .Case("caicos", GK_NORTHERN_ISLANDS) 2164 .Case("cayman", GK_CAYMAN) 2165 .Case("aruba", GK_CAYMAN) 2166 .Default(GK_NONE); 2167 } 2168 2169 static GPUKind parseAMDGCNName(StringRef Name) { 2170 return llvm::StringSwitch<GPUKind>(Name) 2171 .Case("tahiti", GK_GFX6) 2172 .Case("pitcairn", GK_GFX6) 2173 .Case("verde", GK_GFX6) 2174 .Case("oland", GK_GFX6) 2175 .Case("hainan", GK_GFX6) 2176 .Case("bonaire", GK_GFX7) 2177 .Case("kabini", GK_GFX7) 2178 .Case("kaveri", GK_GFX7) 2179 .Case("hawaii", GK_GFX7) 2180 .Case("mullins", GK_GFX7) 2181 .Case("gfx700", GK_GFX7) 2182 .Case("gfx701", GK_GFX7) 2183 .Case("gfx702", GK_GFX7) 2184 .Case("tonga", GK_GFX8) 2185 .Case("iceland", GK_GFX8) 2186 .Case("carrizo", GK_GFX8) 2187 .Case("fiji", GK_GFX8) 2188 .Case("stoney", GK_GFX8) 2189 .Case("polaris10", GK_GFX8) 2190 .Case("polaris11", GK_GFX8) 2191 .Case("gfx800", GK_GFX8) 2192 .Case("gfx801", GK_GFX8) 2193 .Case("gfx802", GK_GFX8) 2194 .Case("gfx803", GK_GFX8) 2195 .Case("gfx804", GK_GFX8) 2196 .Case("gfx810", GK_GFX8) 2197 .Default(GK_NONE); 2198 } 2199 2200 bool setCPU(const std::string &Name) override { 2201 if (getTriple().getArch() == llvm::Triple::amdgcn) 2202 GPU = parseAMDGCNName(Name); 2203 else 2204 GPU = parseR600Name(Name); 2205 2206 return GPU != GK_NONE; 2207 } 2208 2209 void setSupportedOpenCLOpts() override { 2210 auto &Opts = getSupportedOpenCLOpts(); 2211 Opts.cl_clang_storage_class_specifiers = 1; 2212 Opts.cl_khr_icd = 1; 2213 2214 if (hasFP64) 2215 Opts.cl_khr_fp64 = 1; 2216 if (GPU >= GK_EVERGREEN) { 2217 Opts.cl_khr_byte_addressable_store = 1; 2218 Opts.cl_khr_global_int32_base_atomics = 1; 2219 Opts.cl_khr_global_int32_extended_atomics = 1; 2220 Opts.cl_khr_local_int32_base_atomics = 1; 2221 Opts.cl_khr_local_int32_extended_atomics = 1; 2222 } 2223 if (GPU >= GK_GFX6) { 2224 Opts.cl_khr_fp16 = 1; 2225 Opts.cl_khr_int64_base_atomics = 1; 2226 Opts.cl_khr_int64_extended_atomics = 1; 2227 Opts.cl_khr_mipmap_image = 1; 2228 Opts.cl_khr_subgroups = 1; 2229 Opts.cl_khr_3d_image_writes = 1; 2230 Opts.cl_amd_media_ops = 1; 2231 Opts.cl_amd_media_ops2 = 1; 2232 } 2233 } 2234 2235 LangAS::ID getOpenCLImageAddrSpace() const override { 2236 return LangAS::opencl_constant; 2237 } 2238 2239 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2240 switch (CC) { 2241 default: 2242 return CCCR_Warning; 2243 case CC_C: 2244 case CC_OpenCLKernel: 2245 return CCCR_OK; 2246 } 2247 } 2248 }; 2249 2250 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2251 #define BUILTIN(ID, TYPE, ATTRS) \ 2252 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2253 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2254 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2255 #include "clang/Basic/BuiltinsAMDGPU.def" 2256 }; 2257 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2258 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2259 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2260 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2261 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2262 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2263 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2264 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2265 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2266 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2267 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2268 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2269 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2270 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2271 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2272 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2273 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2274 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2275 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2276 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2277 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2278 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2279 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2280 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2281 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2282 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2283 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2284 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2285 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2286 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2287 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2288 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2289 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2290 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2291 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2292 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2293 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2294 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2295 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2296 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2297 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2298 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2299 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2300 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2301 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2302 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2303 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2304 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2305 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2306 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2307 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2308 }; 2309 2310 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2311 return llvm::makeArrayRef(GCCRegNames); 2312 } 2313 2314 bool AMDGPUTargetInfo::initFeatureMap( 2315 llvm::StringMap<bool> &Features, 2316 DiagnosticsEngine &Diags, StringRef CPU, 2317 const std::vector<std::string> &FeatureVec) const { 2318 2319 // XXX - What does the member GPU mean if device name string passed here? 2320 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2321 if (CPU.empty()) 2322 CPU = "tahiti"; 2323 2324 switch (parseAMDGCNName(CPU)) { 2325 case GK_GFX6: 2326 case GK_GFX7: 2327 break; 2328 2329 case GK_GFX8: 2330 Features["s-memrealtime"] = true; 2331 Features["16-bit-insts"] = true; 2332 break; 2333 2334 case GK_NONE: 2335 return false; 2336 default: 2337 llvm_unreachable("unhandled subtarget"); 2338 } 2339 } else { 2340 if (CPU.empty()) 2341 CPU = "r600"; 2342 2343 switch (parseR600Name(CPU)) { 2344 case GK_R600: 2345 case GK_R700: 2346 case GK_EVERGREEN: 2347 case GK_NORTHERN_ISLANDS: 2348 break; 2349 case GK_R600_DOUBLE_OPS: 2350 case GK_R700_DOUBLE_OPS: 2351 case GK_EVERGREEN_DOUBLE_OPS: 2352 case GK_CAYMAN: 2353 Features["fp64"] = true; 2354 break; 2355 case GK_NONE: 2356 return false; 2357 default: 2358 llvm_unreachable("unhandled subtarget"); 2359 } 2360 } 2361 2362 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2363 } 2364 2365 const Builtin::Info BuiltinInfoX86[] = { 2366 #define BUILTIN(ID, TYPE, ATTRS) \ 2367 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2368 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2369 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2370 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2371 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2372 #include "clang/Basic/BuiltinsX86.def" 2373 2374 #define BUILTIN(ID, TYPE, ATTRS) \ 2375 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2376 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2377 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2378 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2379 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2380 #include "clang/Basic/BuiltinsX86_64.def" 2381 }; 2382 2383 2384 static const char* const GCCRegNames[] = { 2385 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2386 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2387 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2388 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2389 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2390 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2391 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2392 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2393 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2394 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2395 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2396 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2397 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2398 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2399 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2400 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2401 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2402 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", 2403 }; 2404 2405 const TargetInfo::AddlRegName AddlRegNames[] = { 2406 { { "al", "ah", "eax", "rax" }, 0 }, 2407 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2408 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2409 { { "dl", "dh", "edx", "rdx" }, 1 }, 2410 { { "esi", "rsi" }, 4 }, 2411 { { "edi", "rdi" }, 5 }, 2412 { { "esp", "rsp" }, 7 }, 2413 { { "ebp", "rbp" }, 6 }, 2414 { { "r8d", "r8w", "r8b" }, 38 }, 2415 { { "r9d", "r9w", "r9b" }, 39 }, 2416 { { "r10d", "r10w", "r10b" }, 40 }, 2417 { { "r11d", "r11w", "r11b" }, 41 }, 2418 { { "r12d", "r12w", "r12b" }, 42 }, 2419 { { "r13d", "r13w", "r13b" }, 43 }, 2420 { { "r14d", "r14w", "r14b" }, 44 }, 2421 { { "r15d", "r15w", "r15b" }, 45 }, 2422 }; 2423 2424 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2425 // most of the implementation can be shared. 2426 class X86TargetInfo : public TargetInfo { 2427 enum X86SSEEnum { 2428 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2429 } SSELevel = NoSSE; 2430 enum MMX3DNowEnum { 2431 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2432 } MMX3DNowLevel = NoMMX3DNow; 2433 enum XOPEnum { 2434 NoXOP, 2435 SSE4A, 2436 FMA4, 2437 XOP 2438 } XOPLevel = NoXOP; 2439 2440 bool HasAES = false; 2441 bool HasPCLMUL = false; 2442 bool HasLZCNT = false; 2443 bool HasRDRND = false; 2444 bool HasFSGSBASE = false; 2445 bool HasBMI = false; 2446 bool HasBMI2 = false; 2447 bool HasPOPCNT = false; 2448 bool HasRTM = false; 2449 bool HasPRFCHW = false; 2450 bool HasRDSEED = false; 2451 bool HasADX = false; 2452 bool HasTBM = false; 2453 bool HasFMA = false; 2454 bool HasF16C = false; 2455 bool HasAVX512CD = false; 2456 bool HasAVX512ER = false; 2457 bool HasAVX512PF = false; 2458 bool HasAVX512DQ = false; 2459 bool HasAVX512BW = false; 2460 bool HasAVX512VL = false; 2461 bool HasAVX512VBMI = false; 2462 bool HasAVX512IFMA = false; 2463 bool HasSHA = false; 2464 bool HasMPX = false; 2465 bool HasSGX = false; 2466 bool HasCX16 = false; 2467 bool HasFXSR = false; 2468 bool HasXSAVE = false; 2469 bool HasXSAVEOPT = false; 2470 bool HasXSAVEC = false; 2471 bool HasXSAVES = false; 2472 bool HasMWAITX = false; 2473 bool HasPKU = false; 2474 bool HasCLFLUSHOPT = false; 2475 bool HasPCOMMIT = false; 2476 bool HasCLWB = false; 2477 bool HasUMIP = false; 2478 bool HasMOVBE = false; 2479 bool HasPREFETCHWT1 = false; 2480 2481 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2482 /// 2483 /// Each enumeration represents a particular CPU supported by Clang. These 2484 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2485 enum CPUKind { 2486 CK_Generic, 2487 2488 /// \name i386 2489 /// i386-generation processors. 2490 //@{ 2491 CK_i386, 2492 //@} 2493 2494 /// \name i486 2495 /// i486-generation processors. 2496 //@{ 2497 CK_i486, 2498 CK_WinChipC6, 2499 CK_WinChip2, 2500 CK_C3, 2501 //@} 2502 2503 /// \name i586 2504 /// i586-generation processors, P5 microarchitecture based. 2505 //@{ 2506 CK_i586, 2507 CK_Pentium, 2508 CK_PentiumMMX, 2509 //@} 2510 2511 /// \name i686 2512 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2513 //@{ 2514 CK_i686, 2515 CK_PentiumPro, 2516 CK_Pentium2, 2517 CK_Pentium3, 2518 CK_Pentium3M, 2519 CK_PentiumM, 2520 CK_C3_2, 2521 2522 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2523 /// Clang however has some logic to suport this. 2524 // FIXME: Warn, deprecate, and potentially remove this. 2525 CK_Yonah, 2526 //@} 2527 2528 /// \name Netburst 2529 /// Netburst microarchitecture based processors. 2530 //@{ 2531 CK_Pentium4, 2532 CK_Pentium4M, 2533 CK_Prescott, 2534 CK_Nocona, 2535 //@} 2536 2537 /// \name Core 2538 /// Core microarchitecture based processors. 2539 //@{ 2540 CK_Core2, 2541 2542 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2543 /// codename which GCC no longer accepts as an option to -march, but Clang 2544 /// has some logic for recognizing it. 2545 // FIXME: Warn, deprecate, and potentially remove this. 2546 CK_Penryn, 2547 //@} 2548 2549 /// \name Atom 2550 /// Atom processors 2551 //@{ 2552 CK_Bonnell, 2553 CK_Silvermont, 2554 //@} 2555 2556 /// \name Nehalem 2557 /// Nehalem microarchitecture based processors. 2558 CK_Nehalem, 2559 2560 /// \name Westmere 2561 /// Westmere microarchitecture based processors. 2562 CK_Westmere, 2563 2564 /// \name Sandy Bridge 2565 /// Sandy Bridge microarchitecture based processors. 2566 CK_SandyBridge, 2567 2568 /// \name Ivy Bridge 2569 /// Ivy Bridge microarchitecture based processors. 2570 CK_IvyBridge, 2571 2572 /// \name Haswell 2573 /// Haswell microarchitecture based processors. 2574 CK_Haswell, 2575 2576 /// \name Broadwell 2577 /// Broadwell microarchitecture based processors. 2578 CK_Broadwell, 2579 2580 /// \name Skylake Client 2581 /// Skylake client microarchitecture based processors. 2582 CK_SkylakeClient, 2583 2584 /// \name Skylake Server 2585 /// Skylake server microarchitecture based processors. 2586 CK_SkylakeServer, 2587 2588 /// \name Cannonlake Client 2589 /// Cannonlake client microarchitecture based processors. 2590 CK_Cannonlake, 2591 2592 /// \name Knights Landing 2593 /// Knights Landing processor. 2594 CK_KNL, 2595 2596 /// \name Lakemont 2597 /// Lakemont microarchitecture based processors. 2598 CK_Lakemont, 2599 2600 /// \name K6 2601 /// K6 architecture processors. 2602 //@{ 2603 CK_K6, 2604 CK_K6_2, 2605 CK_K6_3, 2606 //@} 2607 2608 /// \name K7 2609 /// K7 architecture processors. 2610 //@{ 2611 CK_Athlon, 2612 CK_AthlonThunderbird, 2613 CK_Athlon4, 2614 CK_AthlonXP, 2615 CK_AthlonMP, 2616 //@} 2617 2618 /// \name K8 2619 /// K8 architecture processors. 2620 //@{ 2621 CK_Athlon64, 2622 CK_Athlon64SSE3, 2623 CK_AthlonFX, 2624 CK_K8, 2625 CK_K8SSE3, 2626 CK_Opteron, 2627 CK_OpteronSSE3, 2628 CK_AMDFAM10, 2629 //@} 2630 2631 /// \name Bobcat 2632 /// Bobcat architecture processors. 2633 //@{ 2634 CK_BTVER1, 2635 CK_BTVER2, 2636 //@} 2637 2638 /// \name Bulldozer 2639 /// Bulldozer architecture processors. 2640 //@{ 2641 CK_BDVER1, 2642 CK_BDVER2, 2643 CK_BDVER3, 2644 CK_BDVER4, 2645 //@} 2646 2647 /// This specification is deprecated and will be removed in the future. 2648 /// Users should prefer \see CK_K8. 2649 // FIXME: Warn on this when the CPU is set to it. 2650 //@{ 2651 CK_x86_64, 2652 //@} 2653 2654 /// \name Geode 2655 /// Geode processors. 2656 //@{ 2657 CK_Geode 2658 //@} 2659 } CPU = CK_Generic; 2660 2661 CPUKind getCPUKind(StringRef CPU) const { 2662 return llvm::StringSwitch<CPUKind>(CPU) 2663 .Case("i386", CK_i386) 2664 .Case("i486", CK_i486) 2665 .Case("winchip-c6", CK_WinChipC6) 2666 .Case("winchip2", CK_WinChip2) 2667 .Case("c3", CK_C3) 2668 .Case("i586", CK_i586) 2669 .Case("pentium", CK_Pentium) 2670 .Case("pentium-mmx", CK_PentiumMMX) 2671 .Case("i686", CK_i686) 2672 .Case("pentiumpro", CK_PentiumPro) 2673 .Case("pentium2", CK_Pentium2) 2674 .Case("pentium3", CK_Pentium3) 2675 .Case("pentium3m", CK_Pentium3M) 2676 .Case("pentium-m", CK_PentiumM) 2677 .Case("c3-2", CK_C3_2) 2678 .Case("yonah", CK_Yonah) 2679 .Case("pentium4", CK_Pentium4) 2680 .Case("pentium4m", CK_Pentium4M) 2681 .Case("prescott", CK_Prescott) 2682 .Case("nocona", CK_Nocona) 2683 .Case("core2", CK_Core2) 2684 .Case("penryn", CK_Penryn) 2685 .Case("bonnell", CK_Bonnell) 2686 .Case("atom", CK_Bonnell) // Legacy name. 2687 .Case("silvermont", CK_Silvermont) 2688 .Case("slm", CK_Silvermont) // Legacy name. 2689 .Case("nehalem", CK_Nehalem) 2690 .Case("corei7", CK_Nehalem) // Legacy name. 2691 .Case("westmere", CK_Westmere) 2692 .Case("sandybridge", CK_SandyBridge) 2693 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2694 .Case("ivybridge", CK_IvyBridge) 2695 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2696 .Case("haswell", CK_Haswell) 2697 .Case("core-avx2", CK_Haswell) // Legacy name. 2698 .Case("broadwell", CK_Broadwell) 2699 .Case("skylake", CK_SkylakeClient) 2700 .Case("skylake-avx512", CK_SkylakeServer) 2701 .Case("skx", CK_SkylakeServer) // Legacy name. 2702 .Case("cannonlake", CK_Cannonlake) 2703 .Case("knl", CK_KNL) 2704 .Case("lakemont", CK_Lakemont) 2705 .Case("k6", CK_K6) 2706 .Case("k6-2", CK_K6_2) 2707 .Case("k6-3", CK_K6_3) 2708 .Case("athlon", CK_Athlon) 2709 .Case("athlon-tbird", CK_AthlonThunderbird) 2710 .Case("athlon-4", CK_Athlon4) 2711 .Case("athlon-xp", CK_AthlonXP) 2712 .Case("athlon-mp", CK_AthlonMP) 2713 .Case("athlon64", CK_Athlon64) 2714 .Case("athlon64-sse3", CK_Athlon64SSE3) 2715 .Case("athlon-fx", CK_AthlonFX) 2716 .Case("k8", CK_K8) 2717 .Case("k8-sse3", CK_K8SSE3) 2718 .Case("opteron", CK_Opteron) 2719 .Case("opteron-sse3", CK_OpteronSSE3) 2720 .Case("barcelona", CK_AMDFAM10) 2721 .Case("amdfam10", CK_AMDFAM10) 2722 .Case("btver1", CK_BTVER1) 2723 .Case("btver2", CK_BTVER2) 2724 .Case("bdver1", CK_BDVER1) 2725 .Case("bdver2", CK_BDVER2) 2726 .Case("bdver3", CK_BDVER3) 2727 .Case("bdver4", CK_BDVER4) 2728 .Case("x86-64", CK_x86_64) 2729 .Case("geode", CK_Geode) 2730 .Default(CK_Generic); 2731 } 2732 2733 enum FPMathKind { 2734 FP_Default, 2735 FP_SSE, 2736 FP_387 2737 } FPMath = FP_Default; 2738 2739 public: 2740 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2741 : TargetInfo(Triple) { 2742 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2743 } 2744 unsigned getFloatEvalMethod() const override { 2745 // X87 evaluates with 80 bits "long double" precision. 2746 return SSELevel == NoSSE ? 2 : 0; 2747 } 2748 ArrayRef<const char *> getGCCRegNames() const override { 2749 return llvm::makeArrayRef(GCCRegNames); 2750 } 2751 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2752 return None; 2753 } 2754 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2755 return llvm::makeArrayRef(AddlRegNames); 2756 } 2757 bool validateCpuSupports(StringRef Name) const override; 2758 bool validateAsmConstraint(const char *&Name, 2759 TargetInfo::ConstraintInfo &info) const override; 2760 2761 bool validateGlobalRegisterVariable(StringRef RegName, 2762 unsigned RegSize, 2763 bool &HasSizeMismatch) const override { 2764 // esp and ebp are the only 32-bit registers the x86 backend can currently 2765 // handle. 2766 if (RegName.equals("esp") || RegName.equals("ebp")) { 2767 // Check that the register size is 32-bit. 2768 HasSizeMismatch = RegSize != 32; 2769 return true; 2770 } 2771 2772 return false; 2773 } 2774 2775 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2776 2777 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2778 2779 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2780 2781 std::string convertConstraint(const char *&Constraint) const override; 2782 const char *getClobbers() const override { 2783 return "~{dirflag},~{fpsr},~{flags}"; 2784 } 2785 void getTargetDefines(const LangOptions &Opts, 2786 MacroBuilder &Builder) const override; 2787 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2788 bool Enabled); 2789 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2790 bool Enabled); 2791 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2792 bool Enabled); 2793 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2794 StringRef Name, bool Enabled) const override { 2795 setFeatureEnabledImpl(Features, Name, Enabled); 2796 } 2797 // This exists purely to cut down on the number of virtual calls in 2798 // initFeatureMap which calls this repeatedly. 2799 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2800 StringRef Name, bool Enabled); 2801 bool 2802 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2803 StringRef CPU, 2804 const std::vector<std::string> &FeaturesVec) const override; 2805 bool hasFeature(StringRef Feature) const override; 2806 bool handleTargetFeatures(std::vector<std::string> &Features, 2807 DiagnosticsEngine &Diags) override; 2808 StringRef getABI() const override { 2809 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2810 return "avx512"; 2811 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2812 return "avx"; 2813 if (getTriple().getArch() == llvm::Triple::x86 && 2814 MMX3DNowLevel == NoMMX3DNow) 2815 return "no-mmx"; 2816 return ""; 2817 } 2818 bool setCPU(const std::string &Name) override { 2819 CPU = getCPUKind(Name); 2820 2821 // Perform any per-CPU checks necessary to determine if this CPU is 2822 // acceptable. 2823 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2824 // invalid without explaining *why*. 2825 switch (CPU) { 2826 case CK_Generic: 2827 // No processor selected! 2828 return false; 2829 2830 case CK_i386: 2831 case CK_i486: 2832 case CK_WinChipC6: 2833 case CK_WinChip2: 2834 case CK_C3: 2835 case CK_i586: 2836 case CK_Pentium: 2837 case CK_PentiumMMX: 2838 case CK_i686: 2839 case CK_PentiumPro: 2840 case CK_Pentium2: 2841 case CK_Pentium3: 2842 case CK_Pentium3M: 2843 case CK_PentiumM: 2844 case CK_Yonah: 2845 case CK_C3_2: 2846 case CK_Pentium4: 2847 case CK_Pentium4M: 2848 case CK_Lakemont: 2849 case CK_Prescott: 2850 case CK_K6: 2851 case CK_K6_2: 2852 case CK_K6_3: 2853 case CK_Athlon: 2854 case CK_AthlonThunderbird: 2855 case CK_Athlon4: 2856 case CK_AthlonXP: 2857 case CK_AthlonMP: 2858 case CK_Geode: 2859 // Only accept certain architectures when compiling in 32-bit mode. 2860 if (getTriple().getArch() != llvm::Triple::x86) 2861 return false; 2862 2863 // Fallthrough 2864 case CK_Nocona: 2865 case CK_Core2: 2866 case CK_Penryn: 2867 case CK_Bonnell: 2868 case CK_Silvermont: 2869 case CK_Nehalem: 2870 case CK_Westmere: 2871 case CK_SandyBridge: 2872 case CK_IvyBridge: 2873 case CK_Haswell: 2874 case CK_Broadwell: 2875 case CK_SkylakeClient: 2876 case CK_SkylakeServer: 2877 case CK_Cannonlake: 2878 case CK_KNL: 2879 case CK_Athlon64: 2880 case CK_Athlon64SSE3: 2881 case CK_AthlonFX: 2882 case CK_K8: 2883 case CK_K8SSE3: 2884 case CK_Opteron: 2885 case CK_OpteronSSE3: 2886 case CK_AMDFAM10: 2887 case CK_BTVER1: 2888 case CK_BTVER2: 2889 case CK_BDVER1: 2890 case CK_BDVER2: 2891 case CK_BDVER3: 2892 case CK_BDVER4: 2893 case CK_x86_64: 2894 return true; 2895 } 2896 llvm_unreachable("Unhandled CPU kind"); 2897 } 2898 2899 bool setFPMath(StringRef Name) override; 2900 2901 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2902 // Most of the non-ARM calling conventions are i386 conventions. 2903 switch (CC) { 2904 case CC_X86ThisCall: 2905 case CC_X86FastCall: 2906 case CC_X86StdCall: 2907 case CC_X86VectorCall: 2908 case CC_X86RegCall: 2909 case CC_C: 2910 case CC_Swift: 2911 case CC_X86Pascal: 2912 case CC_IntelOclBicc: 2913 return CCCR_OK; 2914 default: 2915 return CCCR_Warning; 2916 } 2917 } 2918 2919 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2920 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2921 } 2922 2923 bool hasSjLjLowering() const override { 2924 return true; 2925 } 2926 2927 void setSupportedOpenCLOpts() override { 2928 getSupportedOpenCLOpts().setAll(); 2929 } 2930 }; 2931 2932 bool X86TargetInfo::setFPMath(StringRef Name) { 2933 if (Name == "387") { 2934 FPMath = FP_387; 2935 return true; 2936 } 2937 if (Name == "sse") { 2938 FPMath = FP_SSE; 2939 return true; 2940 } 2941 return false; 2942 } 2943 2944 bool X86TargetInfo::initFeatureMap( 2945 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2946 const std::vector<std::string> &FeaturesVec) const { 2947 // FIXME: This *really* should not be here. 2948 // X86_64 always has SSE2. 2949 if (getTriple().getArch() == llvm::Triple::x86_64) 2950 setFeatureEnabledImpl(Features, "sse2", true); 2951 2952 const CPUKind Kind = getCPUKind(CPU); 2953 2954 // Enable X87 for all X86 processors but Lakemont. 2955 if (Kind != CK_Lakemont) 2956 setFeatureEnabledImpl(Features, "x87", true); 2957 2958 switch (Kind) { 2959 case CK_Generic: 2960 case CK_i386: 2961 case CK_i486: 2962 case CK_i586: 2963 case CK_Pentium: 2964 case CK_i686: 2965 case CK_PentiumPro: 2966 case CK_Lakemont: 2967 break; 2968 case CK_PentiumMMX: 2969 case CK_Pentium2: 2970 case CK_K6: 2971 case CK_WinChipC6: 2972 setFeatureEnabledImpl(Features, "mmx", true); 2973 break; 2974 case CK_Pentium3: 2975 case CK_Pentium3M: 2976 case CK_C3_2: 2977 setFeatureEnabledImpl(Features, "sse", true); 2978 setFeatureEnabledImpl(Features, "fxsr", true); 2979 break; 2980 case CK_PentiumM: 2981 case CK_Pentium4: 2982 case CK_Pentium4M: 2983 case CK_x86_64: 2984 setFeatureEnabledImpl(Features, "sse2", true); 2985 setFeatureEnabledImpl(Features, "fxsr", true); 2986 break; 2987 case CK_Yonah: 2988 case CK_Prescott: 2989 case CK_Nocona: 2990 setFeatureEnabledImpl(Features, "sse3", true); 2991 setFeatureEnabledImpl(Features, "fxsr", true); 2992 setFeatureEnabledImpl(Features, "cx16", true); 2993 break; 2994 case CK_Core2: 2995 case CK_Bonnell: 2996 setFeatureEnabledImpl(Features, "ssse3", true); 2997 setFeatureEnabledImpl(Features, "fxsr", true); 2998 setFeatureEnabledImpl(Features, "cx16", true); 2999 break; 3000 case CK_Penryn: 3001 setFeatureEnabledImpl(Features, "sse4.1", true); 3002 setFeatureEnabledImpl(Features, "fxsr", true); 3003 setFeatureEnabledImpl(Features, "cx16", true); 3004 break; 3005 case CK_Cannonlake: 3006 setFeatureEnabledImpl(Features, "avx512ifma", true); 3007 setFeatureEnabledImpl(Features, "avx512vbmi", true); 3008 setFeatureEnabledImpl(Features, "sha", true); 3009 setFeatureEnabledImpl(Features, "umip", true); 3010 // FALLTHROUGH 3011 case CK_SkylakeServer: 3012 setFeatureEnabledImpl(Features, "avx512f", true); 3013 setFeatureEnabledImpl(Features, "avx512cd", true); 3014 setFeatureEnabledImpl(Features, "avx512dq", true); 3015 setFeatureEnabledImpl(Features, "avx512bw", true); 3016 setFeatureEnabledImpl(Features, "avx512vl", true); 3017 setFeatureEnabledImpl(Features, "pku", true); 3018 setFeatureEnabledImpl(Features, "pcommit", true); 3019 setFeatureEnabledImpl(Features, "clwb", true); 3020 // FALLTHROUGH 3021 case CK_SkylakeClient: 3022 setFeatureEnabledImpl(Features, "xsavec", true); 3023 setFeatureEnabledImpl(Features, "xsaves", true); 3024 setFeatureEnabledImpl(Features, "mpx", true); 3025 setFeatureEnabledImpl(Features, "sgx", true); 3026 setFeatureEnabledImpl(Features, "clflushopt", true); 3027 // FALLTHROUGH 3028 case CK_Broadwell: 3029 setFeatureEnabledImpl(Features, "rdseed", true); 3030 setFeatureEnabledImpl(Features, "adx", true); 3031 // FALLTHROUGH 3032 case CK_Haswell: 3033 setFeatureEnabledImpl(Features, "avx2", true); 3034 setFeatureEnabledImpl(Features, "lzcnt", true); 3035 setFeatureEnabledImpl(Features, "bmi", true); 3036 setFeatureEnabledImpl(Features, "bmi2", true); 3037 setFeatureEnabledImpl(Features, "rtm", true); 3038 setFeatureEnabledImpl(Features, "fma", true); 3039 setFeatureEnabledImpl(Features, "movbe", true); 3040 // FALLTHROUGH 3041 case CK_IvyBridge: 3042 setFeatureEnabledImpl(Features, "rdrnd", true); 3043 setFeatureEnabledImpl(Features, "f16c", true); 3044 setFeatureEnabledImpl(Features, "fsgsbase", true); 3045 // FALLTHROUGH 3046 case CK_SandyBridge: 3047 setFeatureEnabledImpl(Features, "avx", true); 3048 setFeatureEnabledImpl(Features, "xsave", true); 3049 setFeatureEnabledImpl(Features, "xsaveopt", true); 3050 // FALLTHROUGH 3051 case CK_Westmere: 3052 case CK_Silvermont: 3053 setFeatureEnabledImpl(Features, "aes", true); 3054 setFeatureEnabledImpl(Features, "pclmul", true); 3055 // FALLTHROUGH 3056 case CK_Nehalem: 3057 setFeatureEnabledImpl(Features, "sse4.2", true); 3058 setFeatureEnabledImpl(Features, "fxsr", true); 3059 setFeatureEnabledImpl(Features, "cx16", true); 3060 break; 3061 case CK_KNL: 3062 setFeatureEnabledImpl(Features, "avx512f", true); 3063 setFeatureEnabledImpl(Features, "avx512cd", true); 3064 setFeatureEnabledImpl(Features, "avx512er", true); 3065 setFeatureEnabledImpl(Features, "avx512pf", true); 3066 setFeatureEnabledImpl(Features, "prefetchwt1", true); 3067 setFeatureEnabledImpl(Features, "fxsr", true); 3068 setFeatureEnabledImpl(Features, "rdseed", true); 3069 setFeatureEnabledImpl(Features, "adx", true); 3070 setFeatureEnabledImpl(Features, "lzcnt", true); 3071 setFeatureEnabledImpl(Features, "bmi", true); 3072 setFeatureEnabledImpl(Features, "bmi2", true); 3073 setFeatureEnabledImpl(Features, "rtm", true); 3074 setFeatureEnabledImpl(Features, "fma", true); 3075 setFeatureEnabledImpl(Features, "rdrnd", true); 3076 setFeatureEnabledImpl(Features, "f16c", true); 3077 setFeatureEnabledImpl(Features, "fsgsbase", true); 3078 setFeatureEnabledImpl(Features, "aes", true); 3079 setFeatureEnabledImpl(Features, "pclmul", true); 3080 setFeatureEnabledImpl(Features, "cx16", true); 3081 setFeatureEnabledImpl(Features, "xsaveopt", true); 3082 setFeatureEnabledImpl(Features, "xsave", true); 3083 setFeatureEnabledImpl(Features, "movbe", true); 3084 break; 3085 case CK_K6_2: 3086 case CK_K6_3: 3087 case CK_WinChip2: 3088 case CK_C3: 3089 setFeatureEnabledImpl(Features, "3dnow", true); 3090 break; 3091 case CK_Athlon: 3092 case CK_AthlonThunderbird: 3093 case CK_Geode: 3094 setFeatureEnabledImpl(Features, "3dnowa", true); 3095 break; 3096 case CK_Athlon4: 3097 case CK_AthlonXP: 3098 case CK_AthlonMP: 3099 setFeatureEnabledImpl(Features, "sse", true); 3100 setFeatureEnabledImpl(Features, "3dnowa", true); 3101 setFeatureEnabledImpl(Features, "fxsr", true); 3102 break; 3103 case CK_K8: 3104 case CK_Opteron: 3105 case CK_Athlon64: 3106 case CK_AthlonFX: 3107 setFeatureEnabledImpl(Features, "sse2", true); 3108 setFeatureEnabledImpl(Features, "3dnowa", true); 3109 setFeatureEnabledImpl(Features, "fxsr", true); 3110 break; 3111 case CK_AMDFAM10: 3112 setFeatureEnabledImpl(Features, "sse4a", true); 3113 setFeatureEnabledImpl(Features, "lzcnt", true); 3114 setFeatureEnabledImpl(Features, "popcnt", true); 3115 // FALLTHROUGH 3116 case CK_K8SSE3: 3117 case CK_OpteronSSE3: 3118 case CK_Athlon64SSE3: 3119 setFeatureEnabledImpl(Features, "sse3", true); 3120 setFeatureEnabledImpl(Features, "3dnowa", true); 3121 setFeatureEnabledImpl(Features, "fxsr", true); 3122 break; 3123 case CK_BTVER2: 3124 setFeatureEnabledImpl(Features, "avx", true); 3125 setFeatureEnabledImpl(Features, "aes", true); 3126 setFeatureEnabledImpl(Features, "pclmul", true); 3127 setFeatureEnabledImpl(Features, "bmi", true); 3128 setFeatureEnabledImpl(Features, "f16c", true); 3129 setFeatureEnabledImpl(Features, "xsaveopt", true); 3130 // FALLTHROUGH 3131 case CK_BTVER1: 3132 setFeatureEnabledImpl(Features, "ssse3", true); 3133 setFeatureEnabledImpl(Features, "sse4a", true); 3134 setFeatureEnabledImpl(Features, "lzcnt", true); 3135 setFeatureEnabledImpl(Features, "popcnt", true); 3136 setFeatureEnabledImpl(Features, "prfchw", true); 3137 setFeatureEnabledImpl(Features, "cx16", true); 3138 setFeatureEnabledImpl(Features, "fxsr", true); 3139 break; 3140 case CK_BDVER4: 3141 setFeatureEnabledImpl(Features, "avx2", true); 3142 setFeatureEnabledImpl(Features, "bmi2", true); 3143 setFeatureEnabledImpl(Features, "mwaitx", true); 3144 // FALLTHROUGH 3145 case CK_BDVER3: 3146 setFeatureEnabledImpl(Features, "fsgsbase", true); 3147 setFeatureEnabledImpl(Features, "xsaveopt", true); 3148 // FALLTHROUGH 3149 case CK_BDVER2: 3150 setFeatureEnabledImpl(Features, "bmi", true); 3151 setFeatureEnabledImpl(Features, "fma", true); 3152 setFeatureEnabledImpl(Features, "f16c", true); 3153 setFeatureEnabledImpl(Features, "tbm", true); 3154 // FALLTHROUGH 3155 case CK_BDVER1: 3156 // xop implies avx, sse4a and fma4. 3157 setFeatureEnabledImpl(Features, "xop", true); 3158 setFeatureEnabledImpl(Features, "lzcnt", true); 3159 setFeatureEnabledImpl(Features, "aes", true); 3160 setFeatureEnabledImpl(Features, "pclmul", true); 3161 setFeatureEnabledImpl(Features, "prfchw", true); 3162 setFeatureEnabledImpl(Features, "cx16", true); 3163 setFeatureEnabledImpl(Features, "fxsr", true); 3164 setFeatureEnabledImpl(Features, "xsave", true); 3165 break; 3166 } 3167 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3168 return false; 3169 3170 // Can't do this earlier because we need to be able to explicitly enable 3171 // or disable these features and the things that they depend upon. 3172 3173 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3174 auto I = Features.find("sse4.2"); 3175 if (I != Features.end() && I->getValue() && 3176 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3177 FeaturesVec.end()) 3178 Features["popcnt"] = true; 3179 3180 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3181 I = Features.find("3dnow"); 3182 if (I != Features.end() && I->getValue() && 3183 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3184 FeaturesVec.end()) 3185 Features["prfchw"] = true; 3186 3187 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3188 // then enable MMX. 3189 I = Features.find("sse"); 3190 if (I != Features.end() && I->getValue() && 3191 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3192 FeaturesVec.end()) 3193 Features["mmx"] = true; 3194 3195 return true; 3196 } 3197 3198 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3199 X86SSEEnum Level, bool Enabled) { 3200 if (Enabled) { 3201 switch (Level) { 3202 case AVX512F: 3203 Features["avx512f"] = true; 3204 case AVX2: 3205 Features["avx2"] = true; 3206 case AVX: 3207 Features["avx"] = true; 3208 Features["xsave"] = true; 3209 case SSE42: 3210 Features["sse4.2"] = true; 3211 case SSE41: 3212 Features["sse4.1"] = true; 3213 case SSSE3: 3214 Features["ssse3"] = true; 3215 case SSE3: 3216 Features["sse3"] = true; 3217 case SSE2: 3218 Features["sse2"] = true; 3219 case SSE1: 3220 Features["sse"] = true; 3221 case NoSSE: 3222 break; 3223 } 3224 return; 3225 } 3226 3227 switch (Level) { 3228 case NoSSE: 3229 case SSE1: 3230 Features["sse"] = false; 3231 case SSE2: 3232 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3233 Features["sha"] = false; 3234 case SSE3: 3235 Features["sse3"] = false; 3236 setXOPLevel(Features, NoXOP, false); 3237 case SSSE3: 3238 Features["ssse3"] = false; 3239 case SSE41: 3240 Features["sse4.1"] = false; 3241 case SSE42: 3242 Features["sse4.2"] = false; 3243 case AVX: 3244 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3245 Features["xsaveopt"] = false; 3246 setXOPLevel(Features, FMA4, false); 3247 case AVX2: 3248 Features["avx2"] = false; 3249 case AVX512F: 3250 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3251 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3252 Features["avx512vl"] = Features["avx512vbmi"] = 3253 Features["avx512ifma"] = false; 3254 } 3255 } 3256 3257 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3258 MMX3DNowEnum Level, bool Enabled) { 3259 if (Enabled) { 3260 switch (Level) { 3261 case AMD3DNowAthlon: 3262 Features["3dnowa"] = true; 3263 case AMD3DNow: 3264 Features["3dnow"] = true; 3265 case MMX: 3266 Features["mmx"] = true; 3267 case NoMMX3DNow: 3268 break; 3269 } 3270 return; 3271 } 3272 3273 switch (Level) { 3274 case NoMMX3DNow: 3275 case MMX: 3276 Features["mmx"] = false; 3277 case AMD3DNow: 3278 Features["3dnow"] = false; 3279 case AMD3DNowAthlon: 3280 Features["3dnowa"] = false; 3281 } 3282 } 3283 3284 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3285 bool Enabled) { 3286 if (Enabled) { 3287 switch (Level) { 3288 case XOP: 3289 Features["xop"] = true; 3290 case FMA4: 3291 Features["fma4"] = true; 3292 setSSELevel(Features, AVX, true); 3293 case SSE4A: 3294 Features["sse4a"] = true; 3295 setSSELevel(Features, SSE3, true); 3296 case NoXOP: 3297 break; 3298 } 3299 return; 3300 } 3301 3302 switch (Level) { 3303 case NoXOP: 3304 case SSE4A: 3305 Features["sse4a"] = false; 3306 case FMA4: 3307 Features["fma4"] = false; 3308 case XOP: 3309 Features["xop"] = false; 3310 } 3311 } 3312 3313 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3314 StringRef Name, bool Enabled) { 3315 // This is a bit of a hack to deal with the sse4 target feature when used 3316 // as part of the target attribute. We handle sse4 correctly everywhere 3317 // else. See below for more information on how we handle the sse4 options. 3318 if (Name != "sse4") 3319 Features[Name] = Enabled; 3320 3321 if (Name == "mmx") { 3322 setMMXLevel(Features, MMX, Enabled); 3323 } else if (Name == "sse") { 3324 setSSELevel(Features, SSE1, Enabled); 3325 } else if (Name == "sse2") { 3326 setSSELevel(Features, SSE2, Enabled); 3327 } else if (Name == "sse3") { 3328 setSSELevel(Features, SSE3, Enabled); 3329 } else if (Name == "ssse3") { 3330 setSSELevel(Features, SSSE3, Enabled); 3331 } else if (Name == "sse4.2") { 3332 setSSELevel(Features, SSE42, Enabled); 3333 } else if (Name == "sse4.1") { 3334 setSSELevel(Features, SSE41, Enabled); 3335 } else if (Name == "3dnow") { 3336 setMMXLevel(Features, AMD3DNow, Enabled); 3337 } else if (Name == "3dnowa") { 3338 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3339 } else if (Name == "aes") { 3340 if (Enabled) 3341 setSSELevel(Features, SSE2, Enabled); 3342 } else if (Name == "pclmul") { 3343 if (Enabled) 3344 setSSELevel(Features, SSE2, Enabled); 3345 } else if (Name == "avx") { 3346 setSSELevel(Features, AVX, Enabled); 3347 } else if (Name == "avx2") { 3348 setSSELevel(Features, AVX2, Enabled); 3349 } else if (Name == "avx512f") { 3350 setSSELevel(Features, AVX512F, Enabled); 3351 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3352 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3353 Name == "avx512vbmi" || Name == "avx512ifma") { 3354 if (Enabled) 3355 setSSELevel(Features, AVX512F, Enabled); 3356 // Enable BWI instruction if VBMI is being enabled. 3357 if (Name == "avx512vbmi" && Enabled) 3358 Features["avx512bw"] = true; 3359 // Also disable VBMI if BWI is being disabled. 3360 if (Name == "avx512bw" && !Enabled) 3361 Features["avx512vbmi"] = false; 3362 } else if (Name == "fma") { 3363 if (Enabled) 3364 setSSELevel(Features, AVX, Enabled); 3365 } else if (Name == "fma4") { 3366 setXOPLevel(Features, FMA4, Enabled); 3367 } else if (Name == "xop") { 3368 setXOPLevel(Features, XOP, Enabled); 3369 } else if (Name == "sse4a") { 3370 setXOPLevel(Features, SSE4A, Enabled); 3371 } else if (Name == "f16c") { 3372 if (Enabled) 3373 setSSELevel(Features, AVX, Enabled); 3374 } else if (Name == "sha") { 3375 if (Enabled) 3376 setSSELevel(Features, SSE2, Enabled); 3377 } else if (Name == "sse4") { 3378 // We can get here via the __target__ attribute since that's not controlled 3379 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3380 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3381 // disabled. 3382 if (Enabled) 3383 setSSELevel(Features, SSE42, Enabled); 3384 else 3385 setSSELevel(Features, SSE41, Enabled); 3386 } else if (Name == "xsave") { 3387 if (!Enabled) 3388 Features["xsaveopt"] = false; 3389 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3390 if (Enabled) 3391 Features["xsave"] = true; 3392 } 3393 } 3394 3395 /// handleTargetFeatures - Perform initialization based on the user 3396 /// configured set of features. 3397 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3398 DiagnosticsEngine &Diags) { 3399 for (const auto &Feature : Features) { 3400 if (Feature[0] != '+') 3401 continue; 3402 3403 if (Feature == "+aes") { 3404 HasAES = true; 3405 } else if (Feature == "+pclmul") { 3406 HasPCLMUL = true; 3407 } else if (Feature == "+lzcnt") { 3408 HasLZCNT = true; 3409 } else if (Feature == "+rdrnd") { 3410 HasRDRND = true; 3411 } else if (Feature == "+fsgsbase") { 3412 HasFSGSBASE = true; 3413 } else if (Feature == "+bmi") { 3414 HasBMI = true; 3415 } else if (Feature == "+bmi2") { 3416 HasBMI2 = true; 3417 } else if (Feature == "+popcnt") { 3418 HasPOPCNT = true; 3419 } else if (Feature == "+rtm") { 3420 HasRTM = true; 3421 } else if (Feature == "+prfchw") { 3422 HasPRFCHW = true; 3423 } else if (Feature == "+rdseed") { 3424 HasRDSEED = true; 3425 } else if (Feature == "+adx") { 3426 HasADX = true; 3427 } else if (Feature == "+tbm") { 3428 HasTBM = true; 3429 } else if (Feature == "+fma") { 3430 HasFMA = true; 3431 } else if (Feature == "+f16c") { 3432 HasF16C = true; 3433 } else if (Feature == "+avx512cd") { 3434 HasAVX512CD = true; 3435 } else if (Feature == "+avx512er") { 3436 HasAVX512ER = true; 3437 } else if (Feature == "+avx512pf") { 3438 HasAVX512PF = true; 3439 } else if (Feature == "+avx512dq") { 3440 HasAVX512DQ = true; 3441 } else if (Feature == "+avx512bw") { 3442 HasAVX512BW = true; 3443 } else if (Feature == "+avx512vl") { 3444 HasAVX512VL = true; 3445 } else if (Feature == "+avx512vbmi") { 3446 HasAVX512VBMI = true; 3447 } else if (Feature == "+avx512ifma") { 3448 HasAVX512IFMA = true; 3449 } else if (Feature == "+sha") { 3450 HasSHA = true; 3451 } else if (Feature == "+mpx") { 3452 HasMPX = true; 3453 } else if (Feature == "+movbe") { 3454 HasMOVBE = true; 3455 } else if (Feature == "+sgx") { 3456 HasSGX = true; 3457 } else if (Feature == "+cx16") { 3458 HasCX16 = true; 3459 } else if (Feature == "+fxsr") { 3460 HasFXSR = true; 3461 } else if (Feature == "+xsave") { 3462 HasXSAVE = true; 3463 } else if (Feature == "+xsaveopt") { 3464 HasXSAVEOPT = true; 3465 } else if (Feature == "+xsavec") { 3466 HasXSAVEC = true; 3467 } else if (Feature == "+xsaves") { 3468 HasXSAVES = true; 3469 } else if (Feature == "+mwaitx") { 3470 HasMWAITX = true; 3471 } else if (Feature == "+pku") { 3472 HasPKU = true; 3473 } else if (Feature == "+clflushopt") { 3474 HasCLFLUSHOPT = true; 3475 } else if (Feature == "+pcommit") { 3476 HasPCOMMIT = true; 3477 } else if (Feature == "+clwb") { 3478 HasCLWB = true; 3479 } else if (Feature == "+umip") { 3480 HasUMIP = true; 3481 } else if (Feature == "+prefetchwt1") { 3482 HasPREFETCHWT1 = true; 3483 } 3484 3485 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3486 .Case("+avx512f", AVX512F) 3487 .Case("+avx2", AVX2) 3488 .Case("+avx", AVX) 3489 .Case("+sse4.2", SSE42) 3490 .Case("+sse4.1", SSE41) 3491 .Case("+ssse3", SSSE3) 3492 .Case("+sse3", SSE3) 3493 .Case("+sse2", SSE2) 3494 .Case("+sse", SSE1) 3495 .Default(NoSSE); 3496 SSELevel = std::max(SSELevel, Level); 3497 3498 MMX3DNowEnum ThreeDNowLevel = 3499 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3500 .Case("+3dnowa", AMD3DNowAthlon) 3501 .Case("+3dnow", AMD3DNow) 3502 .Case("+mmx", MMX) 3503 .Default(NoMMX3DNow); 3504 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3505 3506 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3507 .Case("+xop", XOP) 3508 .Case("+fma4", FMA4) 3509 .Case("+sse4a", SSE4A) 3510 .Default(NoXOP); 3511 XOPLevel = std::max(XOPLevel, XLevel); 3512 } 3513 3514 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3515 // matches the selected sse level. 3516 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3517 (FPMath == FP_387 && SSELevel >= SSE1)) { 3518 Diags.Report(diag::err_target_unsupported_fpmath) << 3519 (FPMath == FP_SSE ? "sse" : "387"); 3520 return false; 3521 } 3522 3523 SimdDefaultAlign = 3524 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3525 return true; 3526 } 3527 3528 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3529 /// definitions for this particular subtarget. 3530 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3531 MacroBuilder &Builder) const { 3532 // Target identification. 3533 if (getTriple().getArch() == llvm::Triple::x86_64) { 3534 Builder.defineMacro("__amd64__"); 3535 Builder.defineMacro("__amd64"); 3536 Builder.defineMacro("__x86_64"); 3537 Builder.defineMacro("__x86_64__"); 3538 if (getTriple().getArchName() == "x86_64h") { 3539 Builder.defineMacro("__x86_64h"); 3540 Builder.defineMacro("__x86_64h__"); 3541 } 3542 } else { 3543 DefineStd(Builder, "i386", Opts); 3544 } 3545 3546 // Subtarget options. 3547 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3548 // truly should be based on -mtune options. 3549 switch (CPU) { 3550 case CK_Generic: 3551 break; 3552 case CK_i386: 3553 // The rest are coming from the i386 define above. 3554 Builder.defineMacro("__tune_i386__"); 3555 break; 3556 case CK_i486: 3557 case CK_WinChipC6: 3558 case CK_WinChip2: 3559 case CK_C3: 3560 defineCPUMacros(Builder, "i486"); 3561 break; 3562 case CK_PentiumMMX: 3563 Builder.defineMacro("__pentium_mmx__"); 3564 Builder.defineMacro("__tune_pentium_mmx__"); 3565 // Fallthrough 3566 case CK_i586: 3567 case CK_Pentium: 3568 defineCPUMacros(Builder, "i586"); 3569 defineCPUMacros(Builder, "pentium"); 3570 break; 3571 case CK_Pentium3: 3572 case CK_Pentium3M: 3573 case CK_PentiumM: 3574 Builder.defineMacro("__tune_pentium3__"); 3575 // Fallthrough 3576 case CK_Pentium2: 3577 case CK_C3_2: 3578 Builder.defineMacro("__tune_pentium2__"); 3579 // Fallthrough 3580 case CK_PentiumPro: 3581 Builder.defineMacro("__tune_i686__"); 3582 Builder.defineMacro("__tune_pentiumpro__"); 3583 // Fallthrough 3584 case CK_i686: 3585 Builder.defineMacro("__i686"); 3586 Builder.defineMacro("__i686__"); 3587 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3588 Builder.defineMacro("__pentiumpro"); 3589 Builder.defineMacro("__pentiumpro__"); 3590 break; 3591 case CK_Pentium4: 3592 case CK_Pentium4M: 3593 defineCPUMacros(Builder, "pentium4"); 3594 break; 3595 case CK_Yonah: 3596 case CK_Prescott: 3597 case CK_Nocona: 3598 defineCPUMacros(Builder, "nocona"); 3599 break; 3600 case CK_Core2: 3601 case CK_Penryn: 3602 defineCPUMacros(Builder, "core2"); 3603 break; 3604 case CK_Bonnell: 3605 defineCPUMacros(Builder, "atom"); 3606 break; 3607 case CK_Silvermont: 3608 defineCPUMacros(Builder, "slm"); 3609 break; 3610 case CK_Nehalem: 3611 case CK_Westmere: 3612 case CK_SandyBridge: 3613 case CK_IvyBridge: 3614 case CK_Haswell: 3615 case CK_Broadwell: 3616 case CK_SkylakeClient: 3617 // FIXME: Historically, we defined this legacy name, it would be nice to 3618 // remove it at some point. We've never exposed fine-grained names for 3619 // recent primary x86 CPUs, and we should keep it that way. 3620 defineCPUMacros(Builder, "corei7"); 3621 break; 3622 case CK_SkylakeServer: 3623 defineCPUMacros(Builder, "skx"); 3624 break; 3625 case CK_Cannonlake: 3626 break; 3627 case CK_KNL: 3628 defineCPUMacros(Builder, "knl"); 3629 break; 3630 case CK_Lakemont: 3631 Builder.defineMacro("__tune_lakemont__"); 3632 break; 3633 case CK_K6_2: 3634 Builder.defineMacro("__k6_2__"); 3635 Builder.defineMacro("__tune_k6_2__"); 3636 // Fallthrough 3637 case CK_K6_3: 3638 if (CPU != CK_K6_2) { // In case of fallthrough 3639 // FIXME: GCC may be enabling these in cases where some other k6 3640 // architecture is specified but -m3dnow is explicitly provided. The 3641 // exact semantics need to be determined and emulated here. 3642 Builder.defineMacro("__k6_3__"); 3643 Builder.defineMacro("__tune_k6_3__"); 3644 } 3645 // Fallthrough 3646 case CK_K6: 3647 defineCPUMacros(Builder, "k6"); 3648 break; 3649 case CK_Athlon: 3650 case CK_AthlonThunderbird: 3651 case CK_Athlon4: 3652 case CK_AthlonXP: 3653 case CK_AthlonMP: 3654 defineCPUMacros(Builder, "athlon"); 3655 if (SSELevel != NoSSE) { 3656 Builder.defineMacro("__athlon_sse__"); 3657 Builder.defineMacro("__tune_athlon_sse__"); 3658 } 3659 break; 3660 case CK_K8: 3661 case CK_K8SSE3: 3662 case CK_x86_64: 3663 case CK_Opteron: 3664 case CK_OpteronSSE3: 3665 case CK_Athlon64: 3666 case CK_Athlon64SSE3: 3667 case CK_AthlonFX: 3668 defineCPUMacros(Builder, "k8"); 3669 break; 3670 case CK_AMDFAM10: 3671 defineCPUMacros(Builder, "amdfam10"); 3672 break; 3673 case CK_BTVER1: 3674 defineCPUMacros(Builder, "btver1"); 3675 break; 3676 case CK_BTVER2: 3677 defineCPUMacros(Builder, "btver2"); 3678 break; 3679 case CK_BDVER1: 3680 defineCPUMacros(Builder, "bdver1"); 3681 break; 3682 case CK_BDVER2: 3683 defineCPUMacros(Builder, "bdver2"); 3684 break; 3685 case CK_BDVER3: 3686 defineCPUMacros(Builder, "bdver3"); 3687 break; 3688 case CK_BDVER4: 3689 defineCPUMacros(Builder, "bdver4"); 3690 break; 3691 case CK_Geode: 3692 defineCPUMacros(Builder, "geode"); 3693 break; 3694 } 3695 3696 // Target properties. 3697 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3698 3699 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3700 // functions in glibc header files that use FP Stack inline asm which the 3701 // backend can't deal with (PR879). 3702 Builder.defineMacro("__NO_MATH_INLINES"); 3703 3704 if (HasAES) 3705 Builder.defineMacro("__AES__"); 3706 3707 if (HasPCLMUL) 3708 Builder.defineMacro("__PCLMUL__"); 3709 3710 if (HasLZCNT) 3711 Builder.defineMacro("__LZCNT__"); 3712 3713 if (HasRDRND) 3714 Builder.defineMacro("__RDRND__"); 3715 3716 if (HasFSGSBASE) 3717 Builder.defineMacro("__FSGSBASE__"); 3718 3719 if (HasBMI) 3720 Builder.defineMacro("__BMI__"); 3721 3722 if (HasBMI2) 3723 Builder.defineMacro("__BMI2__"); 3724 3725 if (HasPOPCNT) 3726 Builder.defineMacro("__POPCNT__"); 3727 3728 if (HasRTM) 3729 Builder.defineMacro("__RTM__"); 3730 3731 if (HasPRFCHW) 3732 Builder.defineMacro("__PRFCHW__"); 3733 3734 if (HasRDSEED) 3735 Builder.defineMacro("__RDSEED__"); 3736 3737 if (HasADX) 3738 Builder.defineMacro("__ADX__"); 3739 3740 if (HasTBM) 3741 Builder.defineMacro("__TBM__"); 3742 3743 if (HasMWAITX) 3744 Builder.defineMacro("__MWAITX__"); 3745 3746 switch (XOPLevel) { 3747 case XOP: 3748 Builder.defineMacro("__XOP__"); 3749 case FMA4: 3750 Builder.defineMacro("__FMA4__"); 3751 case SSE4A: 3752 Builder.defineMacro("__SSE4A__"); 3753 case NoXOP: 3754 break; 3755 } 3756 3757 if (HasFMA) 3758 Builder.defineMacro("__FMA__"); 3759 3760 if (HasF16C) 3761 Builder.defineMacro("__F16C__"); 3762 3763 if (HasAVX512CD) 3764 Builder.defineMacro("__AVX512CD__"); 3765 if (HasAVX512ER) 3766 Builder.defineMacro("__AVX512ER__"); 3767 if (HasAVX512PF) 3768 Builder.defineMacro("__AVX512PF__"); 3769 if (HasAVX512DQ) 3770 Builder.defineMacro("__AVX512DQ__"); 3771 if (HasAVX512BW) 3772 Builder.defineMacro("__AVX512BW__"); 3773 if (HasAVX512VL) 3774 Builder.defineMacro("__AVX512VL__"); 3775 if (HasAVX512VBMI) 3776 Builder.defineMacro("__AVX512VBMI__"); 3777 if (HasAVX512IFMA) 3778 Builder.defineMacro("__AVX512IFMA__"); 3779 3780 if (HasSHA) 3781 Builder.defineMacro("__SHA__"); 3782 3783 if (HasFXSR) 3784 Builder.defineMacro("__FXSR__"); 3785 if (HasXSAVE) 3786 Builder.defineMacro("__XSAVE__"); 3787 if (HasXSAVEOPT) 3788 Builder.defineMacro("__XSAVEOPT__"); 3789 if (HasXSAVEC) 3790 Builder.defineMacro("__XSAVEC__"); 3791 if (HasXSAVES) 3792 Builder.defineMacro("__XSAVES__"); 3793 if (HasPKU) 3794 Builder.defineMacro("__PKU__"); 3795 if (HasCX16) 3796 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3797 3798 // Each case falls through to the previous one here. 3799 switch (SSELevel) { 3800 case AVX512F: 3801 Builder.defineMacro("__AVX512F__"); 3802 case AVX2: 3803 Builder.defineMacro("__AVX2__"); 3804 case AVX: 3805 Builder.defineMacro("__AVX__"); 3806 case SSE42: 3807 Builder.defineMacro("__SSE4_2__"); 3808 case SSE41: 3809 Builder.defineMacro("__SSE4_1__"); 3810 case SSSE3: 3811 Builder.defineMacro("__SSSE3__"); 3812 case SSE3: 3813 Builder.defineMacro("__SSE3__"); 3814 case SSE2: 3815 Builder.defineMacro("__SSE2__"); 3816 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3817 case SSE1: 3818 Builder.defineMacro("__SSE__"); 3819 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3820 case NoSSE: 3821 break; 3822 } 3823 3824 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3825 switch (SSELevel) { 3826 case AVX512F: 3827 case AVX2: 3828 case AVX: 3829 case SSE42: 3830 case SSE41: 3831 case SSSE3: 3832 case SSE3: 3833 case SSE2: 3834 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3835 break; 3836 case SSE1: 3837 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3838 break; 3839 default: 3840 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3841 } 3842 } 3843 3844 // Each case falls through to the previous one here. 3845 switch (MMX3DNowLevel) { 3846 case AMD3DNowAthlon: 3847 Builder.defineMacro("__3dNOW_A__"); 3848 case AMD3DNow: 3849 Builder.defineMacro("__3dNOW__"); 3850 case MMX: 3851 Builder.defineMacro("__MMX__"); 3852 case NoMMX3DNow: 3853 break; 3854 } 3855 3856 if (CPU >= CK_i486) { 3857 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3858 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3859 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3860 } 3861 if (CPU >= CK_i586) 3862 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3863 } 3864 3865 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3866 return llvm::StringSwitch<bool>(Feature) 3867 .Case("aes", HasAES) 3868 .Case("avx", SSELevel >= AVX) 3869 .Case("avx2", SSELevel >= AVX2) 3870 .Case("avx512f", SSELevel >= AVX512F) 3871 .Case("avx512cd", HasAVX512CD) 3872 .Case("avx512er", HasAVX512ER) 3873 .Case("avx512pf", HasAVX512PF) 3874 .Case("avx512dq", HasAVX512DQ) 3875 .Case("avx512bw", HasAVX512BW) 3876 .Case("avx512vl", HasAVX512VL) 3877 .Case("avx512vbmi", HasAVX512VBMI) 3878 .Case("avx512ifma", HasAVX512IFMA) 3879 .Case("bmi", HasBMI) 3880 .Case("bmi2", HasBMI2) 3881 .Case("clflushopt", HasCLFLUSHOPT) 3882 .Case("clwb", HasCLWB) 3883 .Case("cx16", HasCX16) 3884 .Case("f16c", HasF16C) 3885 .Case("fma", HasFMA) 3886 .Case("fma4", XOPLevel >= FMA4) 3887 .Case("fsgsbase", HasFSGSBASE) 3888 .Case("fxsr", HasFXSR) 3889 .Case("lzcnt", HasLZCNT) 3890 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3891 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3892 .Case("mmx", MMX3DNowLevel >= MMX) 3893 .Case("movbe", HasMOVBE) 3894 .Case("mpx", HasMPX) 3895 .Case("pclmul", HasPCLMUL) 3896 .Case("pcommit", HasPCOMMIT) 3897 .Case("pku", HasPKU) 3898 .Case("popcnt", HasPOPCNT) 3899 .Case("prefetchwt1", HasPREFETCHWT1) 3900 .Case("prfchw", HasPRFCHW) 3901 .Case("rdrnd", HasRDRND) 3902 .Case("rdseed", HasRDSEED) 3903 .Case("rtm", HasRTM) 3904 .Case("sgx", HasSGX) 3905 .Case("sha", HasSHA) 3906 .Case("sse", SSELevel >= SSE1) 3907 .Case("sse2", SSELevel >= SSE2) 3908 .Case("sse3", SSELevel >= SSE3) 3909 .Case("ssse3", SSELevel >= SSSE3) 3910 .Case("sse4.1", SSELevel >= SSE41) 3911 .Case("sse4.2", SSELevel >= SSE42) 3912 .Case("sse4a", XOPLevel >= SSE4A) 3913 .Case("tbm", HasTBM) 3914 .Case("umip", HasUMIP) 3915 .Case("x86", true) 3916 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3917 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3918 .Case("xop", XOPLevel >= XOP) 3919 .Case("xsave", HasXSAVE) 3920 .Case("xsavec", HasXSAVEC) 3921 .Case("xsaves", HasXSAVES) 3922 .Case("xsaveopt", HasXSAVEOPT) 3923 .Default(false); 3924 } 3925 3926 // We can't use a generic validation scheme for the features accepted here 3927 // versus subtarget features accepted in the target attribute because the 3928 // bitfield structure that's initialized in the runtime only supports the 3929 // below currently rather than the full range of subtarget features. (See 3930 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3931 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3932 return llvm::StringSwitch<bool>(FeatureStr) 3933 .Case("cmov", true) 3934 .Case("mmx", true) 3935 .Case("popcnt", true) 3936 .Case("sse", true) 3937 .Case("sse2", true) 3938 .Case("sse3", true) 3939 .Case("ssse3", true) 3940 .Case("sse4.1", true) 3941 .Case("sse4.2", true) 3942 .Case("avx", true) 3943 .Case("avx2", true) 3944 .Case("sse4a", true) 3945 .Case("fma4", true) 3946 .Case("xop", true) 3947 .Case("fma", true) 3948 .Case("avx512f", true) 3949 .Case("bmi", true) 3950 .Case("bmi2", true) 3951 .Case("aes", true) 3952 .Case("pclmul", true) 3953 .Case("avx512vl", true) 3954 .Case("avx512bw", true) 3955 .Case("avx512dq", true) 3956 .Case("avx512cd", true) 3957 .Case("avx512er", true) 3958 .Case("avx512pf", true) 3959 .Case("avx512vbmi", true) 3960 .Case("avx512ifma", true) 3961 .Default(false); 3962 } 3963 3964 bool 3965 X86TargetInfo::validateAsmConstraint(const char *&Name, 3966 TargetInfo::ConstraintInfo &Info) const { 3967 switch (*Name) { 3968 default: return false; 3969 // Constant constraints. 3970 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3971 // instructions. 3972 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3973 // x86_64 instructions. 3974 case 's': 3975 Info.setRequiresImmediate(); 3976 return true; 3977 case 'I': 3978 Info.setRequiresImmediate(0, 31); 3979 return true; 3980 case 'J': 3981 Info.setRequiresImmediate(0, 63); 3982 return true; 3983 case 'K': 3984 Info.setRequiresImmediate(-128, 127); 3985 return true; 3986 case 'L': 3987 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3988 return true; 3989 case 'M': 3990 Info.setRequiresImmediate(0, 3); 3991 return true; 3992 case 'N': 3993 Info.setRequiresImmediate(0, 255); 3994 return true; 3995 case 'O': 3996 Info.setRequiresImmediate(0, 127); 3997 return true; 3998 // Register constraints. 3999 case 'Y': // 'Y' is the first character for several 2-character constraints. 4000 // Shift the pointer to the second character of the constraint. 4001 Name++; 4002 switch (*Name) { 4003 default: 4004 return false; 4005 case '0': // First SSE register. 4006 case 't': // Any SSE register, when SSE2 is enabled. 4007 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 4008 case 'm': // Any MMX register, when inter-unit moves enabled. 4009 case 'k': // AVX512 arch mask registers: k1-k7. 4010 Info.setAllowsRegister(); 4011 return true; 4012 } 4013 case 'f': // Any x87 floating point stack register. 4014 // Constraint 'f' cannot be used for output operands. 4015 if (Info.ConstraintStr[0] == '=') 4016 return false; 4017 Info.setAllowsRegister(); 4018 return true; 4019 case 'a': // eax. 4020 case 'b': // ebx. 4021 case 'c': // ecx. 4022 case 'd': // edx. 4023 case 'S': // esi. 4024 case 'D': // edi. 4025 case 'A': // edx:eax. 4026 case 't': // Top of floating point stack. 4027 case 'u': // Second from top of floating point stack. 4028 case 'q': // Any register accessible as [r]l: a, b, c, and d. 4029 case 'y': // Any MMX register. 4030 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 4031 case 'x': // Any SSE register. 4032 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 4033 // for intermideate k reg operations). 4034 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 4035 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 4036 case 'l': // "Index" registers: any general register that can be used as an 4037 // index in a base+index memory access. 4038 Info.setAllowsRegister(); 4039 return true; 4040 // Floating point constant constraints. 4041 case 'C': // SSE floating point constant. 4042 case 'G': // x87 floating point constant. 4043 return true; 4044 } 4045 } 4046 4047 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 4048 unsigned Size) const { 4049 // Strip off constraint modifiers. 4050 while (Constraint[0] == '=' || 4051 Constraint[0] == '+' || 4052 Constraint[0] == '&') 4053 Constraint = Constraint.substr(1); 4054 4055 return validateOperandSize(Constraint, Size); 4056 } 4057 4058 bool X86TargetInfo::validateInputSize(StringRef Constraint, 4059 unsigned Size) const { 4060 return validateOperandSize(Constraint, Size); 4061 } 4062 4063 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 4064 unsigned Size) const { 4065 switch (Constraint[0]) { 4066 default: break; 4067 case 'k': 4068 // Registers k0-k7 (AVX512) size limit is 64 bit. 4069 case 'y': 4070 return Size <= 64; 4071 case 'f': 4072 case 't': 4073 case 'u': 4074 return Size <= 128; 4075 case 'v': 4076 case 'x': 4077 if (SSELevel >= AVX512F) 4078 // 512-bit zmm registers can be used if target supports AVX512F. 4079 return Size <= 512U; 4080 else if (SSELevel >= AVX) 4081 // 256-bit ymm registers can be used if target supports AVX. 4082 return Size <= 256U; 4083 return Size <= 128U; 4084 case 'Y': 4085 // 'Y' is the first character for several 2-character constraints. 4086 switch (Constraint[1]) { 4087 default: break; 4088 case 'm': 4089 // 'Ym' is synonymous with 'y'. 4090 case 'k': 4091 return Size <= 64; 4092 case 'i': 4093 case 't': 4094 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4095 if (SSELevel >= AVX512F) 4096 return Size <= 512U; 4097 else if (SSELevel >= AVX) 4098 return Size <= 256U; 4099 return SSELevel >= SSE2 && Size <= 128U; 4100 } 4101 4102 } 4103 4104 return true; 4105 } 4106 4107 std::string 4108 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4109 switch (*Constraint) { 4110 case 'a': return std::string("{ax}"); 4111 case 'b': return std::string("{bx}"); 4112 case 'c': return std::string("{cx}"); 4113 case 'd': return std::string("{dx}"); 4114 case 'S': return std::string("{si}"); 4115 case 'D': return std::string("{di}"); 4116 case 'p': // address 4117 return std::string("im"); 4118 case 't': // top of floating point stack. 4119 return std::string("{st}"); 4120 case 'u': // second from top of floating point stack. 4121 return std::string("{st(1)}"); // second from top of floating point stack. 4122 case 'Y': 4123 switch (Constraint[1]) { 4124 default: 4125 // Break from inner switch and fall through (copy single char), 4126 // continue parsing after copying the current constraint into 4127 // the return string. 4128 break; 4129 case 'k': 4130 // "^" hints llvm that this is a 2 letter constraint. 4131 // "Constraint++" is used to promote the string iterator 4132 // to the next constraint. 4133 return std::string("^") + std::string(Constraint++, 2); 4134 } 4135 LLVM_FALLTHROUGH; 4136 default: 4137 return std::string(1, *Constraint); 4138 } 4139 } 4140 4141 // X86-32 generic target 4142 class X86_32TargetInfo : public X86TargetInfo { 4143 public: 4144 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4145 : X86TargetInfo(Triple, Opts) { 4146 DoubleAlign = LongLongAlign = 32; 4147 LongDoubleWidth = 96; 4148 LongDoubleAlign = 32; 4149 SuitableAlign = 128; 4150 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4151 SizeType = UnsignedInt; 4152 PtrDiffType = SignedInt; 4153 IntPtrType = SignedInt; 4154 RegParmMax = 3; 4155 4156 // Use fpret for all types. 4157 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4158 (1 << TargetInfo::Double) | 4159 (1 << TargetInfo::LongDouble)); 4160 4161 // x86-32 has atomics up to 8 bytes 4162 // FIXME: Check that we actually have cmpxchg8b before setting 4163 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4164 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4165 } 4166 BuiltinVaListKind getBuiltinVaListKind() const override { 4167 return TargetInfo::CharPtrBuiltinVaList; 4168 } 4169 4170 int getEHDataRegisterNumber(unsigned RegNo) const override { 4171 if (RegNo == 0) return 0; 4172 if (RegNo == 1) return 2; 4173 return -1; 4174 } 4175 bool validateOperandSize(StringRef Constraint, 4176 unsigned Size) const override { 4177 switch (Constraint[0]) { 4178 default: break; 4179 case 'R': 4180 case 'q': 4181 case 'Q': 4182 case 'a': 4183 case 'b': 4184 case 'c': 4185 case 'd': 4186 case 'S': 4187 case 'D': 4188 return Size <= 32; 4189 case 'A': 4190 return Size <= 64; 4191 } 4192 4193 return X86TargetInfo::validateOperandSize(Constraint, Size); 4194 } 4195 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4196 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 4197 Builtin::FirstTSBuiltin + 1); 4198 } 4199 }; 4200 4201 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4202 public: 4203 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4204 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4205 4206 unsigned getFloatEvalMethod() const override { 4207 unsigned Major, Minor, Micro; 4208 getTriple().getOSVersion(Major, Minor, Micro); 4209 // New NetBSD uses the default rounding mode. 4210 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4211 return X86_32TargetInfo::getFloatEvalMethod(); 4212 // NetBSD before 6.99.26 defaults to "double" rounding. 4213 return 1; 4214 } 4215 }; 4216 4217 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4218 public: 4219 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4220 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4221 SizeType = UnsignedLong; 4222 IntPtrType = SignedLong; 4223 PtrDiffType = SignedLong; 4224 } 4225 }; 4226 4227 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4228 public: 4229 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4230 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4231 SizeType = UnsignedLong; 4232 IntPtrType = SignedLong; 4233 PtrDiffType = SignedLong; 4234 } 4235 }; 4236 4237 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4238 public: 4239 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4240 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4241 LongDoubleWidth = 128; 4242 LongDoubleAlign = 128; 4243 SuitableAlign = 128; 4244 MaxVectorAlign = 256; 4245 // The watchOS simulator uses the builtin bool type for Objective-C. 4246 llvm::Triple T = llvm::Triple(Triple); 4247 if (T.isWatchOS()) 4248 UseSignedCharForObjCBool = false; 4249 SizeType = UnsignedLong; 4250 IntPtrType = SignedLong; 4251 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4252 HasAlignMac68kSupport = true; 4253 } 4254 4255 bool handleTargetFeatures(std::vector<std::string> &Features, 4256 DiagnosticsEngine &Diags) override { 4257 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4258 Diags)) 4259 return false; 4260 // We now know the features we have: we can decide how to align vectors. 4261 MaxVectorAlign = 4262 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4263 return true; 4264 } 4265 }; 4266 4267 // x86-32 Windows target 4268 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4269 public: 4270 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4271 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4272 WCharType = UnsignedShort; 4273 DoubleAlign = LongLongAlign = 64; 4274 bool IsWinCOFF = 4275 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4276 resetDataLayout(IsWinCOFF 4277 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4278 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4279 } 4280 void getTargetDefines(const LangOptions &Opts, 4281 MacroBuilder &Builder) const override { 4282 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4283 } 4284 }; 4285 4286 // x86-32 Windows Visual Studio target 4287 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4288 public: 4289 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4290 const TargetOptions &Opts) 4291 : WindowsX86_32TargetInfo(Triple, Opts) { 4292 LongDoubleWidth = LongDoubleAlign = 64; 4293 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4294 } 4295 void getTargetDefines(const LangOptions &Opts, 4296 MacroBuilder &Builder) const override { 4297 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4298 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4299 // The value of the following reflects processor type. 4300 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4301 // We lost the original triple, so we use the default. 4302 Builder.defineMacro("_M_IX86", "600"); 4303 } 4304 }; 4305 4306 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4307 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4308 // supports __declspec natively under -fms-extensions, but we define a no-op 4309 // __declspec macro anyway for pre-processor compatibility. 4310 if (Opts.MicrosoftExt) 4311 Builder.defineMacro("__declspec", "__declspec"); 4312 else 4313 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4314 4315 if (!Opts.MicrosoftExt) { 4316 // Provide macros for all the calling convention keywords. Provide both 4317 // single and double underscore prefixed variants. These are available on 4318 // x64 as well as x86, even though they have no effect. 4319 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4320 for (const char *CC : CCs) { 4321 std::string GCCSpelling = "__attribute__((__"; 4322 GCCSpelling += CC; 4323 GCCSpelling += "__))"; 4324 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4325 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4326 } 4327 } 4328 } 4329 4330 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4331 Builder.defineMacro("__MSVCRT__"); 4332 Builder.defineMacro("__MINGW32__"); 4333 addCygMingDefines(Opts, Builder); 4334 } 4335 4336 // x86-32 MinGW target 4337 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4338 public: 4339 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4340 : WindowsX86_32TargetInfo(Triple, Opts) {} 4341 void getTargetDefines(const LangOptions &Opts, 4342 MacroBuilder &Builder) const override { 4343 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4344 DefineStd(Builder, "WIN32", Opts); 4345 DefineStd(Builder, "WINNT", Opts); 4346 Builder.defineMacro("_X86_"); 4347 addMinGWDefines(Opts, Builder); 4348 } 4349 }; 4350 4351 // x86-32 Cygwin target 4352 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4353 public: 4354 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4355 : X86_32TargetInfo(Triple, Opts) { 4356 WCharType = UnsignedShort; 4357 DoubleAlign = LongLongAlign = 64; 4358 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4359 } 4360 void getTargetDefines(const LangOptions &Opts, 4361 MacroBuilder &Builder) const override { 4362 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4363 Builder.defineMacro("_X86_"); 4364 Builder.defineMacro("__CYGWIN__"); 4365 Builder.defineMacro("__CYGWIN32__"); 4366 addCygMingDefines(Opts, Builder); 4367 DefineStd(Builder, "unix", Opts); 4368 if (Opts.CPlusPlus) 4369 Builder.defineMacro("_GNU_SOURCE"); 4370 } 4371 }; 4372 4373 // x86-32 Haiku target 4374 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4375 public: 4376 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4377 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4378 } 4379 void getTargetDefines(const LangOptions &Opts, 4380 MacroBuilder &Builder) const override { 4381 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4382 Builder.defineMacro("__INTEL__"); 4383 } 4384 }; 4385 4386 // X86-32 MCU target 4387 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4388 public: 4389 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4390 : X86_32TargetInfo(Triple, Opts) { 4391 LongDoubleWidth = 64; 4392 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4393 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4394 WIntType = UnsignedInt; 4395 } 4396 4397 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4398 // On MCU we support only C calling convention. 4399 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4400 } 4401 4402 void getTargetDefines(const LangOptions &Opts, 4403 MacroBuilder &Builder) const override { 4404 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4405 Builder.defineMacro("__iamcu"); 4406 Builder.defineMacro("__iamcu__"); 4407 } 4408 4409 bool allowsLargerPreferedTypeAlignment() const override { 4410 return false; 4411 } 4412 }; 4413 4414 // RTEMS Target 4415 template<typename Target> 4416 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4417 protected: 4418 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4419 MacroBuilder &Builder) const override { 4420 // RTEMS defines; list based off of gcc output 4421 4422 Builder.defineMacro("__rtems__"); 4423 Builder.defineMacro("__ELF__"); 4424 } 4425 4426 public: 4427 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4428 : OSTargetInfo<Target>(Triple, Opts) { 4429 switch (Triple.getArch()) { 4430 default: 4431 case llvm::Triple::x86: 4432 // this->MCountName = ".mcount"; 4433 break; 4434 case llvm::Triple::mips: 4435 case llvm::Triple::mipsel: 4436 case llvm::Triple::ppc: 4437 case llvm::Triple::ppc64: 4438 case llvm::Triple::ppc64le: 4439 // this->MCountName = "_mcount"; 4440 break; 4441 case llvm::Triple::arm: 4442 // this->MCountName = "__mcount"; 4443 break; 4444 } 4445 } 4446 }; 4447 4448 // x86-32 RTEMS target 4449 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4450 public: 4451 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4452 : X86_32TargetInfo(Triple, Opts) { 4453 SizeType = UnsignedLong; 4454 IntPtrType = SignedLong; 4455 PtrDiffType = SignedLong; 4456 } 4457 void getTargetDefines(const LangOptions &Opts, 4458 MacroBuilder &Builder) const override { 4459 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4460 Builder.defineMacro("__INTEL__"); 4461 Builder.defineMacro("__rtems__"); 4462 } 4463 }; 4464 4465 // x86-64 generic target 4466 class X86_64TargetInfo : public X86TargetInfo { 4467 public: 4468 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4469 : X86TargetInfo(Triple, Opts) { 4470 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4471 bool IsWinCOFF = 4472 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4473 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4474 LongDoubleWidth = 128; 4475 LongDoubleAlign = 128; 4476 LargeArrayMinWidth = 128; 4477 LargeArrayAlign = 128; 4478 SuitableAlign = 128; 4479 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4480 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4481 IntPtrType = IsX32 ? SignedInt : SignedLong; 4482 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4483 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4484 RegParmMax = 6; 4485 4486 // Pointers are 32-bit in x32. 4487 resetDataLayout(IsX32 4488 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4489 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4490 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4491 4492 // Use fpret only for long double. 4493 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4494 4495 // Use fp2ret for _Complex long double. 4496 ComplexLongDoubleUsesFP2Ret = true; 4497 4498 // Make __builtin_ms_va_list available. 4499 HasBuiltinMSVaList = true; 4500 4501 // x86-64 has atomics up to 16 bytes. 4502 MaxAtomicPromoteWidth = 128; 4503 MaxAtomicInlineWidth = 128; 4504 } 4505 BuiltinVaListKind getBuiltinVaListKind() const override { 4506 return TargetInfo::X86_64ABIBuiltinVaList; 4507 } 4508 4509 int getEHDataRegisterNumber(unsigned RegNo) const override { 4510 if (RegNo == 0) return 0; 4511 if (RegNo == 1) return 1; 4512 return -1; 4513 } 4514 4515 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4516 switch (CC) { 4517 case CC_C: 4518 case CC_Swift: 4519 case CC_X86VectorCall: 4520 case CC_IntelOclBicc: 4521 case CC_X86_64Win64: 4522 case CC_PreserveMost: 4523 case CC_PreserveAll: 4524 case CC_X86RegCall: 4525 return CCCR_OK; 4526 default: 4527 return CCCR_Warning; 4528 } 4529 } 4530 4531 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4532 return CC_C; 4533 } 4534 4535 // for x32 we need it here explicitly 4536 bool hasInt128Type() const override { return true; } 4537 unsigned getUnwindWordWidth() const override { return 64; } 4538 unsigned getRegisterWidth() const override { return 64; } 4539 4540 bool validateGlobalRegisterVariable(StringRef RegName, 4541 unsigned RegSize, 4542 bool &HasSizeMismatch) const override { 4543 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4544 // handle. 4545 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4546 // Check that the register size is 64-bit. 4547 HasSizeMismatch = RegSize != 64; 4548 return true; 4549 } 4550 4551 // Check if the register is a 32-bit register the backend can handle. 4552 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4553 HasSizeMismatch); 4554 } 4555 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4556 return llvm::makeArrayRef(BuiltinInfoX86, 4557 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 4558 } 4559 }; 4560 4561 // x86-64 Windows target 4562 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4563 public: 4564 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4565 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4566 WCharType = UnsignedShort; 4567 LongWidth = LongAlign = 32; 4568 DoubleAlign = LongLongAlign = 64; 4569 IntMaxType = SignedLongLong; 4570 Int64Type = SignedLongLong; 4571 SizeType = UnsignedLongLong; 4572 PtrDiffType = SignedLongLong; 4573 IntPtrType = SignedLongLong; 4574 } 4575 4576 void getTargetDefines(const LangOptions &Opts, 4577 MacroBuilder &Builder) const override { 4578 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4579 Builder.defineMacro("_WIN64"); 4580 } 4581 4582 BuiltinVaListKind getBuiltinVaListKind() const override { 4583 return TargetInfo::CharPtrBuiltinVaList; 4584 } 4585 4586 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4587 switch (CC) { 4588 case CC_X86StdCall: 4589 case CC_X86ThisCall: 4590 case CC_X86FastCall: 4591 return CCCR_Ignore; 4592 case CC_C: 4593 case CC_X86VectorCall: 4594 case CC_IntelOclBicc: 4595 case CC_X86_64SysV: 4596 case CC_Swift: 4597 case CC_X86RegCall: 4598 return CCCR_OK; 4599 default: 4600 return CCCR_Warning; 4601 } 4602 } 4603 }; 4604 4605 // x86-64 Windows Visual Studio target 4606 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4607 public: 4608 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4609 const TargetOptions &Opts) 4610 : WindowsX86_64TargetInfo(Triple, Opts) { 4611 LongDoubleWidth = LongDoubleAlign = 64; 4612 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4613 } 4614 void getTargetDefines(const LangOptions &Opts, 4615 MacroBuilder &Builder) const override { 4616 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4617 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4618 Builder.defineMacro("_M_X64", "100"); 4619 Builder.defineMacro("_M_AMD64", "100"); 4620 } 4621 }; 4622 4623 // x86-64 MinGW target 4624 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4625 public: 4626 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4627 : WindowsX86_64TargetInfo(Triple, Opts) { 4628 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4629 // with x86 FP ops. Weird. 4630 LongDoubleWidth = LongDoubleAlign = 128; 4631 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4632 } 4633 4634 void getTargetDefines(const LangOptions &Opts, 4635 MacroBuilder &Builder) const override { 4636 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4637 DefineStd(Builder, "WIN64", Opts); 4638 Builder.defineMacro("__MINGW64__"); 4639 addMinGWDefines(Opts, Builder); 4640 4641 // GCC defines this macro when it is using __gxx_personality_seh0. 4642 if (!Opts.SjLjExceptions) 4643 Builder.defineMacro("__SEH__"); 4644 } 4645 }; 4646 4647 // x86-64 Cygwin target 4648 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4649 public: 4650 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4651 : X86_64TargetInfo(Triple, Opts) { 4652 TLSSupported = false; 4653 WCharType = UnsignedShort; 4654 } 4655 void getTargetDefines(const LangOptions &Opts, 4656 MacroBuilder &Builder) const override { 4657 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4658 Builder.defineMacro("__x86_64__"); 4659 Builder.defineMacro("__CYGWIN__"); 4660 Builder.defineMacro("__CYGWIN64__"); 4661 addCygMingDefines(Opts, Builder); 4662 DefineStd(Builder, "unix", Opts); 4663 if (Opts.CPlusPlus) 4664 Builder.defineMacro("_GNU_SOURCE"); 4665 4666 // GCC defines this macro when it is using __gxx_personality_seh0. 4667 if (!Opts.SjLjExceptions) 4668 Builder.defineMacro("__SEH__"); 4669 } 4670 }; 4671 4672 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4673 public: 4674 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4675 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4676 Int64Type = SignedLongLong; 4677 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4678 llvm::Triple T = llvm::Triple(Triple); 4679 if (T.isiOS()) 4680 UseSignedCharForObjCBool = false; 4681 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4682 } 4683 4684 bool handleTargetFeatures(std::vector<std::string> &Features, 4685 DiagnosticsEngine &Diags) override { 4686 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4687 Diags)) 4688 return false; 4689 // We now know the features we have: we can decide how to align vectors. 4690 MaxVectorAlign = 4691 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4692 return true; 4693 } 4694 }; 4695 4696 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4697 public: 4698 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4699 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4700 IntMaxType = SignedLongLong; 4701 Int64Type = SignedLongLong; 4702 } 4703 }; 4704 4705 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4706 public: 4707 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4708 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4709 IntMaxType = SignedLongLong; 4710 Int64Type = SignedLongLong; 4711 } 4712 }; 4713 4714 class ARMTargetInfo : public TargetInfo { 4715 // Possible FPU choices. 4716 enum FPUMode { 4717 VFP2FPU = (1 << 0), 4718 VFP3FPU = (1 << 1), 4719 VFP4FPU = (1 << 2), 4720 NeonFPU = (1 << 3), 4721 FPARMV8 = (1 << 4) 4722 }; 4723 4724 // Possible HWDiv features. 4725 enum HWDivMode { 4726 HWDivThumb = (1 << 0), 4727 HWDivARM = (1 << 1) 4728 }; 4729 4730 static bool FPUModeIsVFP(FPUMode Mode) { 4731 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4732 } 4733 4734 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4735 static const char * const GCCRegNames[]; 4736 4737 std::string ABI, CPU; 4738 4739 StringRef CPUProfile; 4740 StringRef CPUAttr; 4741 4742 enum { 4743 FP_Default, 4744 FP_VFP, 4745 FP_Neon 4746 } FPMath; 4747 4748 unsigned ArchISA; 4749 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4750 unsigned ArchProfile; 4751 unsigned ArchVersion; 4752 4753 unsigned FPU : 5; 4754 4755 unsigned IsAAPCS : 1; 4756 unsigned HWDiv : 2; 4757 4758 // Initialized via features. 4759 unsigned SoftFloat : 1; 4760 unsigned SoftFloatABI : 1; 4761 4762 unsigned CRC : 1; 4763 unsigned Crypto : 1; 4764 unsigned DSP : 1; 4765 unsigned Unaligned : 1; 4766 4767 enum { 4768 LDREX_B = (1 << 0), /// byte (8-bit) 4769 LDREX_H = (1 << 1), /// half (16-bit) 4770 LDREX_W = (1 << 2), /// word (32-bit) 4771 LDREX_D = (1 << 3), /// double (64-bit) 4772 }; 4773 4774 uint32_t LDREX; 4775 4776 // ACLE 6.5.1 Hardware floating point 4777 enum { 4778 HW_FP_HP = (1 << 1), /// half (16-bit) 4779 HW_FP_SP = (1 << 2), /// single (32-bit) 4780 HW_FP_DP = (1 << 3), /// double (64-bit) 4781 }; 4782 uint32_t HW_FP; 4783 4784 static const Builtin::Info BuiltinInfo[]; 4785 4786 void setABIAAPCS() { 4787 IsAAPCS = true; 4788 4789 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4790 const llvm::Triple &T = getTriple(); 4791 4792 // size_t is unsigned long on MachO-derived environments, NetBSD, 4793 // OpenBSD and Bitrig. 4794 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4795 T.getOS() == llvm::Triple::OpenBSD || 4796 T.getOS() == llvm::Triple::Bitrig) 4797 SizeType = UnsignedLong; 4798 else 4799 SizeType = UnsignedInt; 4800 4801 switch (T.getOS()) { 4802 case llvm::Triple::NetBSD: 4803 case llvm::Triple::OpenBSD: 4804 WCharType = SignedInt; 4805 break; 4806 case llvm::Triple::Win32: 4807 WCharType = UnsignedShort; 4808 break; 4809 case llvm::Triple::Linux: 4810 default: 4811 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4812 WCharType = UnsignedInt; 4813 break; 4814 } 4815 4816 UseBitFieldTypeAlignment = true; 4817 4818 ZeroLengthBitfieldBoundary = 0; 4819 4820 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4821 // so set preferred for small types to 32. 4822 if (T.isOSBinFormatMachO()) { 4823 resetDataLayout(BigEndian 4824 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4825 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4826 } else if (T.isOSWindows()) { 4827 assert(!BigEndian && "Windows on ARM does not support big endian"); 4828 resetDataLayout("e" 4829 "-m:w" 4830 "-p:32:32" 4831 "-i64:64" 4832 "-v128:64:128" 4833 "-a:0:32" 4834 "-n32" 4835 "-S64"); 4836 } else if (T.isOSNaCl()) { 4837 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4838 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4839 } else { 4840 resetDataLayout(BigEndian 4841 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4842 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4843 } 4844 4845 // FIXME: Enumerated types are variable width in straight AAPCS. 4846 } 4847 4848 void setABIAPCS(bool IsAAPCS16) { 4849 const llvm::Triple &T = getTriple(); 4850 4851 IsAAPCS = false; 4852 4853 if (IsAAPCS16) 4854 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4855 else 4856 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4857 4858 // size_t is unsigned int on FreeBSD. 4859 if (T.getOS() == llvm::Triple::FreeBSD) 4860 SizeType = UnsignedInt; 4861 else 4862 SizeType = UnsignedLong; 4863 4864 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4865 WCharType = SignedInt; 4866 4867 // Do not respect the alignment of bit-field types when laying out 4868 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4869 UseBitFieldTypeAlignment = false; 4870 4871 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4872 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4873 /// gcc. 4874 ZeroLengthBitfieldBoundary = 32; 4875 4876 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4877 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4878 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4879 } else if (T.isOSBinFormatMachO()) 4880 resetDataLayout( 4881 BigEndian 4882 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4883 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4884 else 4885 resetDataLayout( 4886 BigEndian 4887 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4888 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4889 4890 // FIXME: Override "preferred align" for double and long long. 4891 } 4892 4893 void setArchInfo() { 4894 StringRef ArchName = getTriple().getArchName(); 4895 4896 ArchISA = llvm::ARM::parseArchISA(ArchName); 4897 CPU = llvm::ARM::getDefaultCPU(ArchName); 4898 unsigned AK = llvm::ARM::parseArch(ArchName); 4899 if (AK != llvm::ARM::AK_INVALID) 4900 ArchKind = AK; 4901 setArchInfo(ArchKind); 4902 } 4903 4904 void setArchInfo(unsigned Kind) { 4905 StringRef SubArch; 4906 4907 // cache TargetParser info 4908 ArchKind = Kind; 4909 SubArch = llvm::ARM::getSubArch(ArchKind); 4910 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4911 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4912 4913 // cache CPU related strings 4914 CPUAttr = getCPUAttr(); 4915 CPUProfile = getCPUProfile(); 4916 } 4917 4918 void setAtomic() { 4919 // when triple does not specify a sub arch, 4920 // then we are not using inline atomics 4921 bool ShouldUseInlineAtomic = 4922 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4923 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4924 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4925 if (ArchProfile == llvm::ARM::PK_M) { 4926 MaxAtomicPromoteWidth = 32; 4927 if (ShouldUseInlineAtomic) 4928 MaxAtomicInlineWidth = 32; 4929 } 4930 else { 4931 MaxAtomicPromoteWidth = 64; 4932 if (ShouldUseInlineAtomic) 4933 MaxAtomicInlineWidth = 64; 4934 } 4935 } 4936 4937 bool isThumb() const { 4938 return (ArchISA == llvm::ARM::IK_THUMB); 4939 } 4940 4941 bool supportsThumb() const { 4942 return CPUAttr.count('T') || ArchVersion >= 6; 4943 } 4944 4945 bool supportsThumb2() const { 4946 return CPUAttr.equals("6T2") || 4947 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 4948 } 4949 4950 StringRef getCPUAttr() const { 4951 // For most sub-arches, the build attribute CPU name is enough. 4952 // For Cortex variants, it's slightly different. 4953 switch(ArchKind) { 4954 default: 4955 return llvm::ARM::getCPUAttr(ArchKind); 4956 case llvm::ARM::AK_ARMV6M: 4957 return "6M"; 4958 case llvm::ARM::AK_ARMV7S: 4959 return "7S"; 4960 case llvm::ARM::AK_ARMV7A: 4961 return "7A"; 4962 case llvm::ARM::AK_ARMV7R: 4963 return "7R"; 4964 case llvm::ARM::AK_ARMV7M: 4965 return "7M"; 4966 case llvm::ARM::AK_ARMV7EM: 4967 return "7EM"; 4968 case llvm::ARM::AK_ARMV8A: 4969 return "8A"; 4970 case llvm::ARM::AK_ARMV8_1A: 4971 return "8_1A"; 4972 case llvm::ARM::AK_ARMV8_2A: 4973 return "8_2A"; 4974 case llvm::ARM::AK_ARMV8MBaseline: 4975 return "8M_BASE"; 4976 case llvm::ARM::AK_ARMV8MMainline: 4977 return "8M_MAIN"; 4978 case llvm::ARM::AK_ARMV8R: 4979 return "8R"; 4980 } 4981 } 4982 4983 StringRef getCPUProfile() const { 4984 switch(ArchProfile) { 4985 case llvm::ARM::PK_A: 4986 return "A"; 4987 case llvm::ARM::PK_R: 4988 return "R"; 4989 case llvm::ARM::PK_M: 4990 return "M"; 4991 default: 4992 return ""; 4993 } 4994 } 4995 4996 public: 4997 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4998 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 4999 HW_FP(0) { 5000 5001 switch (getTriple().getOS()) { 5002 case llvm::Triple::NetBSD: 5003 case llvm::Triple::OpenBSD: 5004 PtrDiffType = SignedLong; 5005 break; 5006 default: 5007 PtrDiffType = SignedInt; 5008 break; 5009 } 5010 5011 // Cache arch related info. 5012 setArchInfo(); 5013 5014 // {} in inline assembly are neon specifiers, not assembly variant 5015 // specifiers. 5016 NoAsmVariants = true; 5017 5018 // FIXME: This duplicates code from the driver that sets the -target-abi 5019 // option - this code is used if -target-abi isn't passed and should 5020 // be unified in some way. 5021 if (Triple.isOSBinFormatMachO()) { 5022 // The backend is hardwired to assume AAPCS for M-class processors, ensure 5023 // the frontend matches that. 5024 if (Triple.getEnvironment() == llvm::Triple::EABI || 5025 Triple.getOS() == llvm::Triple::UnknownOS || 5026 ArchProfile == llvm::ARM::PK_M) { 5027 setABI("aapcs"); 5028 } else if (Triple.isWatchABI()) { 5029 setABI("aapcs16"); 5030 } else { 5031 setABI("apcs-gnu"); 5032 } 5033 } else if (Triple.isOSWindows()) { 5034 // FIXME: this is invalid for WindowsCE 5035 setABI("aapcs"); 5036 } else { 5037 // Select the default based on the platform. 5038 switch (Triple.getEnvironment()) { 5039 case llvm::Triple::Android: 5040 case llvm::Triple::GNUEABI: 5041 case llvm::Triple::GNUEABIHF: 5042 case llvm::Triple::MuslEABI: 5043 case llvm::Triple::MuslEABIHF: 5044 setABI("aapcs-linux"); 5045 break; 5046 case llvm::Triple::EABIHF: 5047 case llvm::Triple::EABI: 5048 setABI("aapcs"); 5049 break; 5050 case llvm::Triple::GNU: 5051 setABI("apcs-gnu"); 5052 break; 5053 default: 5054 if (Triple.getOS() == llvm::Triple::NetBSD) 5055 setABI("apcs-gnu"); 5056 else 5057 setABI("aapcs"); 5058 break; 5059 } 5060 } 5061 5062 // ARM targets default to using the ARM C++ ABI. 5063 TheCXXABI.set(TargetCXXABI::GenericARM); 5064 5065 // ARM has atomics up to 8 bytes 5066 setAtomic(); 5067 5068 // Do force alignment of members that follow zero length bitfields. If 5069 // the alignment of the zero-length bitfield is greater than the member 5070 // that follows it, `bar', `bar' will be aligned as the type of the 5071 // zero length bitfield. 5072 UseZeroLengthBitfieldAlignment = true; 5073 5074 if (Triple.getOS() == llvm::Triple::Linux || 5075 Triple.getOS() == llvm::Triple::UnknownOS) 5076 this->MCountName = 5077 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 5078 } 5079 5080 StringRef getABI() const override { return ABI; } 5081 5082 bool setABI(const std::string &Name) override { 5083 ABI = Name; 5084 5085 // The defaults (above) are for AAPCS, check if we need to change them. 5086 // 5087 // FIXME: We need support for -meabi... we could just mangle it into the 5088 // name. 5089 if (Name == "apcs-gnu" || Name == "aapcs16") { 5090 setABIAPCS(Name == "aapcs16"); 5091 return true; 5092 } 5093 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 5094 setABIAAPCS(); 5095 return true; 5096 } 5097 return false; 5098 } 5099 5100 // FIXME: This should be based on Arch attributes, not CPU names. 5101 bool 5102 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5103 StringRef CPU, 5104 const std::vector<std::string> &FeaturesVec) const override { 5105 5106 std::vector<StringRef> TargetFeatures; 5107 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 5108 5109 // get default FPU features 5110 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 5111 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 5112 5113 // get default Extension features 5114 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 5115 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 5116 5117 for (auto Feature : TargetFeatures) 5118 if (Feature[0] == '+') 5119 Features[Feature.drop_front(1)] = true; 5120 5121 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5122 } 5123 5124 bool handleTargetFeatures(std::vector<std::string> &Features, 5125 DiagnosticsEngine &Diags) override { 5126 FPU = 0; 5127 CRC = 0; 5128 Crypto = 0; 5129 DSP = 0; 5130 Unaligned = 1; 5131 SoftFloat = SoftFloatABI = false; 5132 HWDiv = 0; 5133 5134 // This does not diagnose illegal cases like having both 5135 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5136 uint32_t HW_FP_remove = 0; 5137 for (const auto &Feature : Features) { 5138 if (Feature == "+soft-float") { 5139 SoftFloat = true; 5140 } else if (Feature == "+soft-float-abi") { 5141 SoftFloatABI = true; 5142 } else if (Feature == "+vfp2") { 5143 FPU |= VFP2FPU; 5144 HW_FP |= HW_FP_SP | HW_FP_DP; 5145 } else if (Feature == "+vfp3") { 5146 FPU |= VFP3FPU; 5147 HW_FP |= HW_FP_SP | HW_FP_DP; 5148 } else if (Feature == "+vfp4") { 5149 FPU |= VFP4FPU; 5150 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5151 } else if (Feature == "+fp-armv8") { 5152 FPU |= FPARMV8; 5153 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5154 } else if (Feature == "+neon") { 5155 FPU |= NeonFPU; 5156 HW_FP |= HW_FP_SP | HW_FP_DP; 5157 } else if (Feature == "+hwdiv") { 5158 HWDiv |= HWDivThumb; 5159 } else if (Feature == "+hwdiv-arm") { 5160 HWDiv |= HWDivARM; 5161 } else if (Feature == "+crc") { 5162 CRC = 1; 5163 } else if (Feature == "+crypto") { 5164 Crypto = 1; 5165 } else if (Feature == "+dsp") { 5166 DSP = 1; 5167 } else if (Feature == "+fp-only-sp") { 5168 HW_FP_remove |= HW_FP_DP; 5169 } else if (Feature == "+strict-align") { 5170 Unaligned = 0; 5171 } else if (Feature == "+fp16") { 5172 HW_FP |= HW_FP_HP; 5173 } 5174 } 5175 HW_FP &= ~HW_FP_remove; 5176 5177 switch (ArchVersion) { 5178 case 6: 5179 if (ArchProfile == llvm::ARM::PK_M) 5180 LDREX = 0; 5181 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5182 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5183 else 5184 LDREX = LDREX_W; 5185 break; 5186 case 7: 5187 if (ArchProfile == llvm::ARM::PK_M) 5188 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5189 else 5190 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5191 break; 5192 case 8: 5193 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5194 } 5195 5196 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5197 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5198 return false; 5199 } 5200 5201 if (FPMath == FP_Neon) 5202 Features.push_back("+neonfp"); 5203 else if (FPMath == FP_VFP) 5204 Features.push_back("-neonfp"); 5205 5206 // Remove front-end specific options which the backend handles differently. 5207 auto Feature = 5208 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5209 if (Feature != Features.end()) 5210 Features.erase(Feature); 5211 5212 return true; 5213 } 5214 5215 bool hasFeature(StringRef Feature) const override { 5216 return llvm::StringSwitch<bool>(Feature) 5217 .Case("arm", true) 5218 .Case("aarch32", true) 5219 .Case("softfloat", SoftFloat) 5220 .Case("thumb", isThumb()) 5221 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5222 .Case("hwdiv", HWDiv & HWDivThumb) 5223 .Case("hwdiv-arm", HWDiv & HWDivARM) 5224 .Default(false); 5225 } 5226 5227 bool setCPU(const std::string &Name) override { 5228 if (Name != "generic") 5229 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5230 5231 if (ArchKind == llvm::ARM::AK_INVALID) 5232 return false; 5233 setAtomic(); 5234 CPU = Name; 5235 return true; 5236 } 5237 5238 bool setFPMath(StringRef Name) override; 5239 5240 void getTargetDefines(const LangOptions &Opts, 5241 MacroBuilder &Builder) const override { 5242 // Target identification. 5243 Builder.defineMacro("__arm"); 5244 Builder.defineMacro("__arm__"); 5245 // For bare-metal none-eabi. 5246 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5247 getTriple().getEnvironment() == llvm::Triple::EABI) 5248 Builder.defineMacro("__ELF__"); 5249 5250 // Target properties. 5251 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5252 5253 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5254 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5255 if (getTriple().isWatchABI()) 5256 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5257 5258 if (!CPUAttr.empty()) 5259 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5260 5261 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5262 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5263 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5264 5265 if (ArchVersion >= 8) { 5266 // ACLE 6.5.7 Crypto Extension 5267 if (Crypto) 5268 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5269 // ACLE 6.5.8 CRC32 Extension 5270 if (CRC) 5271 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5272 // ACLE 6.5.10 Numeric Maximum and Minimum 5273 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5274 // ACLE 6.5.9 Directed Rounding 5275 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5276 } 5277 5278 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5279 // is not defined for the M-profile. 5280 // NOTE that the default profile is assumed to be 'A' 5281 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5282 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5283 5284 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5285 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5286 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5287 // v7 and v8 architectures excluding v8-M Baseline. 5288 if (supportsThumb2()) 5289 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5290 else if (supportsThumb()) 5291 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5292 5293 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5294 // instruction set such as ARM or Thumb. 5295 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5296 5297 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5298 5299 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5300 if (!CPUProfile.empty()) 5301 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5302 5303 // ACLE 6.4.3 Unaligned access supported in hardware 5304 if (Unaligned) 5305 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5306 5307 // ACLE 6.4.4 LDREX/STREX 5308 if (LDREX) 5309 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5310 5311 // ACLE 6.4.5 CLZ 5312 if (ArchVersion == 5 || 5313 (ArchVersion == 6 && CPUProfile != "M") || 5314 ArchVersion > 6) 5315 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5316 5317 // ACLE 6.5.1 Hardware Floating Point 5318 if (HW_FP) 5319 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5320 5321 // ACLE predefines. 5322 Builder.defineMacro("__ARM_ACLE", "200"); 5323 5324 // FP16 support (we currently only support IEEE format). 5325 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5326 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5327 5328 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5329 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5330 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5331 5332 // Subtarget options. 5333 5334 // FIXME: It's more complicated than this and we don't really support 5335 // interworking. 5336 // Windows on ARM does not "support" interworking 5337 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5338 Builder.defineMacro("__THUMB_INTERWORK__"); 5339 5340 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5341 // Embedded targets on Darwin follow AAPCS, but not EABI. 5342 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5343 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5344 Builder.defineMacro("__ARM_EABI__"); 5345 Builder.defineMacro("__ARM_PCS", "1"); 5346 } 5347 5348 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5349 ABI == "aapcs16") 5350 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5351 5352 if (SoftFloat) 5353 Builder.defineMacro("__SOFTFP__"); 5354 5355 if (ArchKind == llvm::ARM::AK_XSCALE) 5356 Builder.defineMacro("__XSCALE__"); 5357 5358 if (isThumb()) { 5359 Builder.defineMacro("__THUMBEL__"); 5360 Builder.defineMacro("__thumb__"); 5361 if (supportsThumb2()) 5362 Builder.defineMacro("__thumb2__"); 5363 } 5364 5365 // ACLE 6.4.9 32-bit SIMD instructions 5366 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5367 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5368 5369 // ACLE 6.4.10 Hardware Integer Divide 5370 if (((HWDiv & HWDivThumb) && isThumb()) || 5371 ((HWDiv & HWDivARM) && !isThumb())) { 5372 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5373 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5374 } 5375 5376 // Note, this is always on in gcc, even though it doesn't make sense. 5377 Builder.defineMacro("__APCS_32__"); 5378 5379 if (FPUModeIsVFP((FPUMode) FPU)) { 5380 Builder.defineMacro("__VFP_FP__"); 5381 if (FPU & VFP2FPU) 5382 Builder.defineMacro("__ARM_VFPV2__"); 5383 if (FPU & VFP3FPU) 5384 Builder.defineMacro("__ARM_VFPV3__"); 5385 if (FPU & VFP4FPU) 5386 Builder.defineMacro("__ARM_VFPV4__"); 5387 } 5388 5389 // This only gets set when Neon instructions are actually available, unlike 5390 // the VFP define, hence the soft float and arch check. This is subtly 5391 // different from gcc, we follow the intent which was that it should be set 5392 // when Neon instructions are actually available. 5393 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5394 Builder.defineMacro("__ARM_NEON", "1"); 5395 Builder.defineMacro("__ARM_NEON__"); 5396 // current AArch32 NEON implementations do not support double-precision 5397 // floating-point even when it is present in VFP. 5398 Builder.defineMacro("__ARM_NEON_FP", 5399 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5400 } 5401 5402 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5403 Opts.ShortWChar ? "2" : "4"); 5404 5405 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5406 Opts.ShortEnums ? "1" : "4"); 5407 5408 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5409 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5410 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5411 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5412 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5413 } 5414 5415 // ACLE 6.4.7 DSP instructions 5416 if (DSP) { 5417 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5418 } 5419 5420 // ACLE 6.4.8 Saturation instructions 5421 bool SAT = false; 5422 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5423 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5424 SAT = true; 5425 } 5426 5427 // ACLE 6.4.6 Q (saturation) flag 5428 if (DSP || SAT) 5429 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5430 5431 if (Opts.UnsafeFPMath) 5432 Builder.defineMacro("__ARM_FP_FAST", "1"); 5433 5434 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5435 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5436 } 5437 5438 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5439 return llvm::makeArrayRef(BuiltinInfo, 5440 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5441 } 5442 bool isCLZForZeroUndef() const override { return false; } 5443 BuiltinVaListKind getBuiltinVaListKind() const override { 5444 return IsAAPCS 5445 ? AAPCSABIBuiltinVaList 5446 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5447 : TargetInfo::VoidPtrBuiltinVaList); 5448 } 5449 ArrayRef<const char *> getGCCRegNames() const override; 5450 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5451 bool validateAsmConstraint(const char *&Name, 5452 TargetInfo::ConstraintInfo &Info) const override { 5453 switch (*Name) { 5454 default: break; 5455 case 'l': // r0-r7 5456 case 'h': // r8-r15 5457 case 't': // VFP Floating point register single precision 5458 case 'w': // VFP Floating point register double precision 5459 Info.setAllowsRegister(); 5460 return true; 5461 case 'I': 5462 case 'J': 5463 case 'K': 5464 case 'L': 5465 case 'M': 5466 // FIXME 5467 return true; 5468 case 'Q': // A memory address that is a single base register. 5469 Info.setAllowsMemory(); 5470 return true; 5471 case 'U': // a memory reference... 5472 switch (Name[1]) { 5473 case 'q': // ...ARMV4 ldrsb 5474 case 'v': // ...VFP load/store (reg+constant offset) 5475 case 'y': // ...iWMMXt load/store 5476 case 't': // address valid for load/store opaque types wider 5477 // than 128-bits 5478 case 'n': // valid address for Neon doubleword vector load/store 5479 case 'm': // valid address for Neon element and structure load/store 5480 case 's': // valid address for non-offset loads/stores of quad-word 5481 // values in four ARM registers 5482 Info.setAllowsMemory(); 5483 Name++; 5484 return true; 5485 } 5486 } 5487 return false; 5488 } 5489 std::string convertConstraint(const char *&Constraint) const override { 5490 std::string R; 5491 switch (*Constraint) { 5492 case 'U': // Two-character constraint; add "^" hint for later parsing. 5493 R = std::string("^") + std::string(Constraint, 2); 5494 Constraint++; 5495 break; 5496 case 'p': // 'p' should be translated to 'r' by default. 5497 R = std::string("r"); 5498 break; 5499 default: 5500 return std::string(1, *Constraint); 5501 } 5502 return R; 5503 } 5504 bool 5505 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5506 std::string &SuggestedModifier) const override { 5507 bool isOutput = (Constraint[0] == '='); 5508 bool isInOut = (Constraint[0] == '+'); 5509 5510 // Strip off constraint modifiers. 5511 while (Constraint[0] == '=' || 5512 Constraint[0] == '+' || 5513 Constraint[0] == '&') 5514 Constraint = Constraint.substr(1); 5515 5516 switch (Constraint[0]) { 5517 default: break; 5518 case 'r': { 5519 switch (Modifier) { 5520 default: 5521 return (isInOut || isOutput || Size <= 64); 5522 case 'q': 5523 // A register of size 32 cannot fit a vector type. 5524 return false; 5525 } 5526 } 5527 } 5528 5529 return true; 5530 } 5531 const char *getClobbers() const override { 5532 // FIXME: Is this really right? 5533 return ""; 5534 } 5535 5536 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5537 switch (CC) { 5538 case CC_AAPCS: 5539 case CC_AAPCS_VFP: 5540 case CC_Swift: 5541 return CCCR_OK; 5542 default: 5543 return CCCR_Warning; 5544 } 5545 } 5546 5547 int getEHDataRegisterNumber(unsigned RegNo) const override { 5548 if (RegNo == 0) return 0; 5549 if (RegNo == 1) return 1; 5550 return -1; 5551 } 5552 5553 bool hasSjLjLowering() const override { 5554 return true; 5555 } 5556 }; 5557 5558 bool ARMTargetInfo::setFPMath(StringRef Name) { 5559 if (Name == "neon") { 5560 FPMath = FP_Neon; 5561 return true; 5562 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5563 Name == "vfp4") { 5564 FPMath = FP_VFP; 5565 return true; 5566 } 5567 return false; 5568 } 5569 5570 const char * const ARMTargetInfo::GCCRegNames[] = { 5571 // Integer registers 5572 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5573 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5574 5575 // Float registers 5576 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5577 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5578 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5579 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5580 5581 // Double registers 5582 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5583 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5584 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5585 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5586 5587 // Quad registers 5588 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5589 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5590 }; 5591 5592 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5593 return llvm::makeArrayRef(GCCRegNames); 5594 } 5595 5596 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5597 { { "a1" }, "r0" }, 5598 { { "a2" }, "r1" }, 5599 { { "a3" }, "r2" }, 5600 { { "a4" }, "r3" }, 5601 { { "v1" }, "r4" }, 5602 { { "v2" }, "r5" }, 5603 { { "v3" }, "r6" }, 5604 { { "v4" }, "r7" }, 5605 { { "v5" }, "r8" }, 5606 { { "v6", "rfp" }, "r9" }, 5607 { { "sl" }, "r10" }, 5608 { { "fp" }, "r11" }, 5609 { { "ip" }, "r12" }, 5610 { { "r13" }, "sp" }, 5611 { { "r14" }, "lr" }, 5612 { { "r15" }, "pc" }, 5613 // The S, D and Q registers overlap, but aren't really aliases; we 5614 // don't want to substitute one of these for a different-sized one. 5615 }; 5616 5617 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5618 return llvm::makeArrayRef(GCCRegAliases); 5619 } 5620 5621 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5622 #define BUILTIN(ID, TYPE, ATTRS) \ 5623 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5624 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5625 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5626 #include "clang/Basic/BuiltinsNEON.def" 5627 5628 #define BUILTIN(ID, TYPE, ATTRS) \ 5629 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5630 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5631 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5632 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5633 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5634 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 5635 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 5636 #include "clang/Basic/BuiltinsARM.def" 5637 }; 5638 5639 class ARMleTargetInfo : public ARMTargetInfo { 5640 public: 5641 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5642 : ARMTargetInfo(Triple, Opts) {} 5643 void getTargetDefines(const LangOptions &Opts, 5644 MacroBuilder &Builder) const override { 5645 Builder.defineMacro("__ARMEL__"); 5646 ARMTargetInfo::getTargetDefines(Opts, Builder); 5647 } 5648 }; 5649 5650 class ARMbeTargetInfo : public ARMTargetInfo { 5651 public: 5652 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5653 : ARMTargetInfo(Triple, Opts) {} 5654 void getTargetDefines(const LangOptions &Opts, 5655 MacroBuilder &Builder) const override { 5656 Builder.defineMacro("__ARMEB__"); 5657 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5658 ARMTargetInfo::getTargetDefines(Opts, Builder); 5659 } 5660 }; 5661 5662 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5663 const llvm::Triple Triple; 5664 public: 5665 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5666 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5667 WCharType = UnsignedShort; 5668 SizeType = UnsignedInt; 5669 } 5670 void getVisualStudioDefines(const LangOptions &Opts, 5671 MacroBuilder &Builder) const { 5672 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5673 5674 // FIXME: this is invalid for WindowsCE 5675 Builder.defineMacro("_M_ARM_NT", "1"); 5676 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5677 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5678 5679 assert((Triple.getArch() == llvm::Triple::arm || 5680 Triple.getArch() == llvm::Triple::thumb) && 5681 "invalid architecture for Windows ARM target info"); 5682 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5683 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5684 5685 // TODO map the complete set of values 5686 // 31: VFPv3 40: VFPv4 5687 Builder.defineMacro("_M_ARM_FP", "31"); 5688 } 5689 BuiltinVaListKind getBuiltinVaListKind() const override { 5690 return TargetInfo::CharPtrBuiltinVaList; 5691 } 5692 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5693 switch (CC) { 5694 case CC_X86StdCall: 5695 case CC_X86ThisCall: 5696 case CC_X86FastCall: 5697 case CC_X86VectorCall: 5698 return CCCR_Ignore; 5699 case CC_C: 5700 return CCCR_OK; 5701 default: 5702 return CCCR_Warning; 5703 } 5704 } 5705 }; 5706 5707 // Windows ARM + Itanium C++ ABI Target 5708 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5709 public: 5710 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5711 const TargetOptions &Opts) 5712 : WindowsARMTargetInfo(Triple, Opts) { 5713 TheCXXABI.set(TargetCXXABI::GenericARM); 5714 } 5715 5716 void getTargetDefines(const LangOptions &Opts, 5717 MacroBuilder &Builder) const override { 5718 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5719 5720 if (Opts.MSVCCompat) 5721 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5722 } 5723 }; 5724 5725 // Windows ARM, MS (C++) ABI 5726 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5727 public: 5728 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5729 const TargetOptions &Opts) 5730 : WindowsARMTargetInfo(Triple, Opts) { 5731 TheCXXABI.set(TargetCXXABI::Microsoft); 5732 } 5733 5734 void getTargetDefines(const LangOptions &Opts, 5735 MacroBuilder &Builder) const override { 5736 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5737 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5738 } 5739 }; 5740 5741 // ARM MinGW target 5742 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5743 public: 5744 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5745 : WindowsARMTargetInfo(Triple, Opts) { 5746 TheCXXABI.set(TargetCXXABI::GenericARM); 5747 } 5748 5749 void getTargetDefines(const LangOptions &Opts, 5750 MacroBuilder &Builder) const override { 5751 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5752 DefineStd(Builder, "WIN32", Opts); 5753 DefineStd(Builder, "WINNT", Opts); 5754 Builder.defineMacro("_ARM_"); 5755 addMinGWDefines(Opts, Builder); 5756 } 5757 }; 5758 5759 // ARM Cygwin target 5760 class CygwinARMTargetInfo : public ARMleTargetInfo { 5761 public: 5762 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5763 : ARMleTargetInfo(Triple, Opts) { 5764 TLSSupported = false; 5765 WCharType = UnsignedShort; 5766 DoubleAlign = LongLongAlign = 64; 5767 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5768 } 5769 void getTargetDefines(const LangOptions &Opts, 5770 MacroBuilder &Builder) const override { 5771 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5772 Builder.defineMacro("_ARM_"); 5773 Builder.defineMacro("__CYGWIN__"); 5774 Builder.defineMacro("__CYGWIN32__"); 5775 DefineStd(Builder, "unix", Opts); 5776 if (Opts.CPlusPlus) 5777 Builder.defineMacro("_GNU_SOURCE"); 5778 } 5779 }; 5780 5781 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 5782 protected: 5783 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5784 MacroBuilder &Builder) const override { 5785 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5786 } 5787 5788 public: 5789 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5790 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 5791 HasAlignMac68kSupport = true; 5792 // iOS always has 64-bit atomic instructions. 5793 // FIXME: This should be based off of the target features in 5794 // ARMleTargetInfo. 5795 MaxAtomicInlineWidth = 64; 5796 5797 if (Triple.isWatchABI()) { 5798 // Darwin on iOS uses a variant of the ARM C++ ABI. 5799 TheCXXABI.set(TargetCXXABI::WatchOS); 5800 5801 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5802 // size_t is long, it's a bit weird for it to be int. 5803 PtrDiffType = SignedLong; 5804 5805 // BOOL should be a real boolean on the new ABI 5806 UseSignedCharForObjCBool = false; 5807 } else 5808 TheCXXABI.set(TargetCXXABI::iOS); 5809 } 5810 }; 5811 5812 class AArch64TargetInfo : public TargetInfo { 5813 virtual void setDataLayout() = 0; 5814 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5815 static const char *const GCCRegNames[]; 5816 5817 enum FPUModeEnum { 5818 FPUMode, 5819 NeonMode 5820 }; 5821 5822 unsigned FPU; 5823 unsigned CRC; 5824 unsigned Crypto; 5825 unsigned Unaligned; 5826 unsigned V8_1A; 5827 5828 static const Builtin::Info BuiltinInfo[]; 5829 5830 std::string ABI; 5831 5832 public: 5833 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5834 : TargetInfo(Triple), ABI("aapcs") { 5835 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5836 WCharType = SignedInt; 5837 5838 // NetBSD apparently prefers consistency across ARM targets to consistency 5839 // across 64-bit targets. 5840 Int64Type = SignedLongLong; 5841 IntMaxType = SignedLongLong; 5842 } else { 5843 WCharType = UnsignedInt; 5844 Int64Type = SignedLong; 5845 IntMaxType = SignedLong; 5846 } 5847 5848 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5849 MaxVectorAlign = 128; 5850 MaxAtomicInlineWidth = 128; 5851 MaxAtomicPromoteWidth = 128; 5852 5853 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5854 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5855 5856 // {} in inline assembly are neon specifiers, not assembly variant 5857 // specifiers. 5858 NoAsmVariants = true; 5859 5860 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5861 // contributes to the alignment of the containing aggregate in the same way 5862 // a plain (non bit-field) member of that type would, without exception for 5863 // zero-sized or anonymous bit-fields." 5864 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5865 UseZeroLengthBitfieldAlignment = true; 5866 5867 // AArch64 targets default to using the ARM C++ ABI. 5868 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5869 5870 if (Triple.getOS() == llvm::Triple::Linux || 5871 Triple.getOS() == llvm::Triple::UnknownOS) 5872 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 5873 } 5874 5875 StringRef getABI() const override { return ABI; } 5876 bool setABI(const std::string &Name) override { 5877 if (Name != "aapcs" && Name != "darwinpcs") 5878 return false; 5879 5880 ABI = Name; 5881 return true; 5882 } 5883 5884 bool setCPU(const std::string &Name) override { 5885 return Name == "generic" || 5886 llvm::AArch64::parseCPUArch(Name) != 5887 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 5888 } 5889 5890 void getTargetDefines(const LangOptions &Opts, 5891 MacroBuilder &Builder) const override { 5892 // Target identification. 5893 Builder.defineMacro("__aarch64__"); 5894 5895 // Target properties. 5896 Builder.defineMacro("_LP64"); 5897 Builder.defineMacro("__LP64__"); 5898 5899 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5900 Builder.defineMacro("__ARM_ACLE", "200"); 5901 Builder.defineMacro("__ARM_ARCH", "8"); 5902 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5903 5904 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5905 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5906 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5907 5908 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5909 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5910 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5911 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5912 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5913 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5914 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5915 5916 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5917 5918 // 0xe implies support for half, single and double precision operations. 5919 Builder.defineMacro("__ARM_FP", "0xE"); 5920 5921 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5922 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5923 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5924 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5925 5926 if (Opts.UnsafeFPMath) 5927 Builder.defineMacro("__ARM_FP_FAST", "1"); 5928 5929 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5930 5931 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5932 Opts.ShortEnums ? "1" : "4"); 5933 5934 if (FPU == NeonMode) { 5935 Builder.defineMacro("__ARM_NEON", "1"); 5936 // 64-bit NEON supports half, single and double precision operations. 5937 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5938 } 5939 5940 if (CRC) 5941 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5942 5943 if (Crypto) 5944 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5945 5946 if (Unaligned) 5947 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5948 5949 if (V8_1A) 5950 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5951 5952 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5953 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5954 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5955 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5956 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5957 } 5958 5959 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5960 return llvm::makeArrayRef(BuiltinInfo, 5961 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5962 } 5963 5964 bool hasFeature(StringRef Feature) const override { 5965 return Feature == "aarch64" || 5966 Feature == "arm64" || 5967 Feature == "arm" || 5968 (Feature == "neon" && FPU == NeonMode); 5969 } 5970 5971 bool handleTargetFeatures(std::vector<std::string> &Features, 5972 DiagnosticsEngine &Diags) override { 5973 FPU = FPUMode; 5974 CRC = 0; 5975 Crypto = 0; 5976 Unaligned = 1; 5977 V8_1A = 0; 5978 5979 for (const auto &Feature : Features) { 5980 if (Feature == "+neon") 5981 FPU = NeonMode; 5982 if (Feature == "+crc") 5983 CRC = 1; 5984 if (Feature == "+crypto") 5985 Crypto = 1; 5986 if (Feature == "+strict-align") 5987 Unaligned = 0; 5988 if (Feature == "+v8.1a") 5989 V8_1A = 1; 5990 } 5991 5992 setDataLayout(); 5993 5994 return true; 5995 } 5996 5997 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5998 switch (CC) { 5999 case CC_C: 6000 case CC_Swift: 6001 case CC_PreserveMost: 6002 case CC_PreserveAll: 6003 return CCCR_OK; 6004 default: 6005 return CCCR_Warning; 6006 } 6007 } 6008 6009 bool isCLZForZeroUndef() const override { return false; } 6010 6011 BuiltinVaListKind getBuiltinVaListKind() const override { 6012 return TargetInfo::AArch64ABIBuiltinVaList; 6013 } 6014 6015 ArrayRef<const char *> getGCCRegNames() const override; 6016 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6017 6018 bool validateAsmConstraint(const char *&Name, 6019 TargetInfo::ConstraintInfo &Info) const override { 6020 switch (*Name) { 6021 default: 6022 return false; 6023 case 'w': // Floating point and SIMD registers (V0-V31) 6024 Info.setAllowsRegister(); 6025 return true; 6026 case 'I': // Constant that can be used with an ADD instruction 6027 case 'J': // Constant that can be used with a SUB instruction 6028 case 'K': // Constant that can be used with a 32-bit logical instruction 6029 case 'L': // Constant that can be used with a 64-bit logical instruction 6030 case 'M': // Constant that can be used as a 32-bit MOV immediate 6031 case 'N': // Constant that can be used as a 64-bit MOV immediate 6032 case 'Y': // Floating point constant zero 6033 case 'Z': // Integer constant zero 6034 return true; 6035 case 'Q': // A memory reference with base register and no offset 6036 Info.setAllowsMemory(); 6037 return true; 6038 case 'S': // A symbolic address 6039 Info.setAllowsRegister(); 6040 return true; 6041 case 'U': 6042 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 6043 // Utf: A memory address suitable for ldp/stp in TF mode. 6044 // Usa: An absolute symbolic address. 6045 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 6046 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 6047 case 'z': // Zero register, wzr or xzr 6048 Info.setAllowsRegister(); 6049 return true; 6050 case 'x': // Floating point and SIMD registers (V0-V15) 6051 Info.setAllowsRegister(); 6052 return true; 6053 } 6054 return false; 6055 } 6056 6057 bool 6058 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 6059 std::string &SuggestedModifier) const override { 6060 // Strip off constraint modifiers. 6061 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 6062 Constraint = Constraint.substr(1); 6063 6064 switch (Constraint[0]) { 6065 default: 6066 return true; 6067 case 'z': 6068 case 'r': { 6069 switch (Modifier) { 6070 case 'x': 6071 case 'w': 6072 // For now assume that the person knows what they're 6073 // doing with the modifier. 6074 return true; 6075 default: 6076 // By default an 'r' constraint will be in the 'x' 6077 // registers. 6078 if (Size == 64) 6079 return true; 6080 6081 SuggestedModifier = "w"; 6082 return false; 6083 } 6084 } 6085 } 6086 } 6087 6088 const char *getClobbers() const override { return ""; } 6089 6090 int getEHDataRegisterNumber(unsigned RegNo) const override { 6091 if (RegNo == 0) 6092 return 0; 6093 if (RegNo == 1) 6094 return 1; 6095 return -1; 6096 } 6097 }; 6098 6099 const char *const AArch64TargetInfo::GCCRegNames[] = { 6100 // 32-bit Integer registers 6101 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 6102 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 6103 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 6104 6105 // 64-bit Integer registers 6106 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 6107 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 6108 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 6109 6110 // 32-bit floating point regsisters 6111 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 6112 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 6113 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6114 6115 // 64-bit floating point regsisters 6116 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 6117 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 6118 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6119 6120 // Vector registers 6121 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6122 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6123 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6124 }; 6125 6126 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6127 return llvm::makeArrayRef(GCCRegNames); 6128 } 6129 6130 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6131 { { "w31" }, "wsp" }, 6132 { { "x29" }, "fp" }, 6133 { { "x30" }, "lr" }, 6134 { { "x31" }, "sp" }, 6135 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6136 // don't want to substitute one of these for a different-sized one. 6137 }; 6138 6139 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6140 return llvm::makeArrayRef(GCCRegAliases); 6141 } 6142 6143 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6144 #define BUILTIN(ID, TYPE, ATTRS) \ 6145 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6146 #include "clang/Basic/BuiltinsNEON.def" 6147 6148 #define BUILTIN(ID, TYPE, ATTRS) \ 6149 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6150 #include "clang/Basic/BuiltinsAArch64.def" 6151 }; 6152 6153 class AArch64leTargetInfo : public AArch64TargetInfo { 6154 void setDataLayout() override { 6155 if (getTriple().isOSBinFormatMachO()) 6156 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6157 else 6158 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6159 } 6160 6161 public: 6162 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6163 : AArch64TargetInfo(Triple, Opts) { 6164 } 6165 void getTargetDefines(const LangOptions &Opts, 6166 MacroBuilder &Builder) const override { 6167 Builder.defineMacro("__AARCH64EL__"); 6168 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6169 } 6170 }; 6171 6172 class AArch64beTargetInfo : public AArch64TargetInfo { 6173 void setDataLayout() override { 6174 assert(!getTriple().isOSBinFormatMachO()); 6175 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6176 } 6177 6178 public: 6179 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6180 : AArch64TargetInfo(Triple, Opts) {} 6181 void getTargetDefines(const LangOptions &Opts, 6182 MacroBuilder &Builder) const override { 6183 Builder.defineMacro("__AARCH64EB__"); 6184 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6185 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6186 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6187 } 6188 }; 6189 6190 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6191 protected: 6192 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6193 MacroBuilder &Builder) const override { 6194 Builder.defineMacro("__AARCH64_SIMD__"); 6195 Builder.defineMacro("__ARM64_ARCH_8__"); 6196 Builder.defineMacro("__ARM_NEON__"); 6197 Builder.defineMacro("__LITTLE_ENDIAN__"); 6198 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6199 Builder.defineMacro("__arm64", "1"); 6200 Builder.defineMacro("__arm64__", "1"); 6201 6202 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6203 } 6204 6205 public: 6206 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6207 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6208 Int64Type = SignedLongLong; 6209 WCharType = SignedInt; 6210 UseSignedCharForObjCBool = false; 6211 6212 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6213 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6214 6215 TheCXXABI.set(TargetCXXABI::iOS64); 6216 } 6217 6218 BuiltinVaListKind getBuiltinVaListKind() const override { 6219 return TargetInfo::CharPtrBuiltinVaList; 6220 } 6221 }; 6222 6223 // Hexagon abstract base class 6224 class HexagonTargetInfo : public TargetInfo { 6225 static const Builtin::Info BuiltinInfo[]; 6226 static const char * const GCCRegNames[]; 6227 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6228 std::string CPU; 6229 bool HasHVX, HasHVXDouble; 6230 bool UseLongCalls; 6231 6232 public: 6233 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6234 : TargetInfo(Triple) { 6235 // Specify the vector alignment explicitly. For v512x1, the calculated 6236 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6237 // the required minimum of 64 bytes. 6238 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6239 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6240 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6241 SizeType = UnsignedInt; 6242 PtrDiffType = SignedInt; 6243 IntPtrType = SignedInt; 6244 6245 // {} in inline assembly are packet specifiers, not assembly variant 6246 // specifiers. 6247 NoAsmVariants = true; 6248 6249 LargeArrayMinWidth = 64; 6250 LargeArrayAlign = 64; 6251 UseBitFieldTypeAlignment = true; 6252 ZeroLengthBitfieldBoundary = 32; 6253 HasHVX = HasHVXDouble = false; 6254 UseLongCalls = false; 6255 } 6256 6257 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6258 return llvm::makeArrayRef(BuiltinInfo, 6259 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6260 } 6261 6262 bool validateAsmConstraint(const char *&Name, 6263 TargetInfo::ConstraintInfo &Info) const override { 6264 switch (*Name) { 6265 case 'v': 6266 case 'q': 6267 if (HasHVX) { 6268 Info.setAllowsRegister(); 6269 return true; 6270 } 6271 break; 6272 case 's': 6273 // Relocatable constant. 6274 return true; 6275 } 6276 return false; 6277 } 6278 6279 void getTargetDefines(const LangOptions &Opts, 6280 MacroBuilder &Builder) const override; 6281 6282 bool isCLZForZeroUndef() const override { return false; } 6283 6284 bool hasFeature(StringRef Feature) const override { 6285 return llvm::StringSwitch<bool>(Feature) 6286 .Case("hexagon", true) 6287 .Case("hvx", HasHVX) 6288 .Case("hvx-double", HasHVXDouble) 6289 .Case("long-calls", UseLongCalls) 6290 .Default(false); 6291 } 6292 6293 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6294 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6295 const override; 6296 6297 bool handleTargetFeatures(std::vector<std::string> &Features, 6298 DiagnosticsEngine &Diags) override; 6299 6300 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6301 bool Enabled) const override; 6302 6303 BuiltinVaListKind getBuiltinVaListKind() const override { 6304 return TargetInfo::CharPtrBuiltinVaList; 6305 } 6306 ArrayRef<const char *> getGCCRegNames() const override; 6307 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6308 const char *getClobbers() const override { 6309 return ""; 6310 } 6311 6312 static const char *getHexagonCPUSuffix(StringRef Name) { 6313 return llvm::StringSwitch<const char*>(Name) 6314 .Case("hexagonv4", "4") 6315 .Case("hexagonv5", "5") 6316 .Case("hexagonv55", "55") 6317 .Case("hexagonv60", "60") 6318 .Default(nullptr); 6319 } 6320 6321 bool setCPU(const std::string &Name) override { 6322 if (!getHexagonCPUSuffix(Name)) 6323 return false; 6324 CPU = Name; 6325 return true; 6326 } 6327 6328 int getEHDataRegisterNumber(unsigned RegNo) const override { 6329 return RegNo < 2 ? RegNo : -1; 6330 } 6331 }; 6332 6333 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6334 MacroBuilder &Builder) const { 6335 Builder.defineMacro("__qdsp6__", "1"); 6336 Builder.defineMacro("__hexagon__", "1"); 6337 6338 if (CPU == "hexagonv4") { 6339 Builder.defineMacro("__HEXAGON_V4__"); 6340 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6341 if (Opts.HexagonQdsp6Compat) { 6342 Builder.defineMacro("__QDSP6_V4__"); 6343 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6344 } 6345 } else if (CPU == "hexagonv5") { 6346 Builder.defineMacro("__HEXAGON_V5__"); 6347 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6348 if(Opts.HexagonQdsp6Compat) { 6349 Builder.defineMacro("__QDSP6_V5__"); 6350 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6351 } 6352 } else if (CPU == "hexagonv55") { 6353 Builder.defineMacro("__HEXAGON_V55__"); 6354 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6355 Builder.defineMacro("__QDSP6_V55__"); 6356 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6357 } else if (CPU == "hexagonv60") { 6358 Builder.defineMacro("__HEXAGON_V60__"); 6359 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6360 Builder.defineMacro("__QDSP6_V60__"); 6361 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6362 } 6363 6364 if (hasFeature("hvx")) { 6365 Builder.defineMacro("__HVX__"); 6366 if (hasFeature("hvx-double")) 6367 Builder.defineMacro("__HVXDBL__"); 6368 } 6369 } 6370 6371 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6372 DiagnosticsEngine &Diags, StringRef CPU, 6373 const std::vector<std::string> &FeaturesVec) const { 6374 // Default for v60: -hvx, -hvx-double. 6375 Features["hvx"] = false; 6376 Features["hvx-double"] = false; 6377 Features["long-calls"] = false; 6378 6379 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6380 } 6381 6382 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6383 DiagnosticsEngine &Diags) { 6384 for (auto &F : Features) { 6385 if (F == "+hvx") 6386 HasHVX = true; 6387 else if (F == "-hvx") 6388 HasHVX = HasHVXDouble = false; 6389 else if (F == "+hvx-double") 6390 HasHVX = HasHVXDouble = true; 6391 else if (F == "-hvx-double") 6392 HasHVXDouble = false; 6393 6394 if (F == "+long-calls") 6395 UseLongCalls = true; 6396 else if (F == "-long-calls") 6397 UseLongCalls = false; 6398 } 6399 return true; 6400 } 6401 6402 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 6403 StringRef Name, bool Enabled) const { 6404 if (Enabled) { 6405 if (Name == "hvx-double") 6406 Features["hvx"] = true; 6407 } else { 6408 if (Name == "hvx") 6409 Features["hvx-double"] = false; 6410 } 6411 Features[Name] = Enabled; 6412 } 6413 6414 const char *const HexagonTargetInfo::GCCRegNames[] = { 6415 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6416 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6417 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6418 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6419 "p0", "p1", "p2", "p3", 6420 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6421 }; 6422 6423 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6424 return llvm::makeArrayRef(GCCRegNames); 6425 } 6426 6427 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6428 { { "sp" }, "r29" }, 6429 { { "fp" }, "r30" }, 6430 { { "lr" }, "r31" }, 6431 }; 6432 6433 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6434 return llvm::makeArrayRef(GCCRegAliases); 6435 } 6436 6437 6438 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6439 #define BUILTIN(ID, TYPE, ATTRS) \ 6440 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6441 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6442 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6443 #include "clang/Basic/BuiltinsHexagon.def" 6444 }; 6445 6446 class LanaiTargetInfo : public TargetInfo { 6447 // Class for Lanai (32-bit). 6448 // The CPU profiles supported by the Lanai backend 6449 enum CPUKind { 6450 CK_NONE, 6451 CK_V11, 6452 } CPU; 6453 6454 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6455 static const char *const GCCRegNames[]; 6456 6457 public: 6458 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6459 : TargetInfo(Triple) { 6460 // Description string has to be kept in sync with backend. 6461 resetDataLayout("E" // Big endian 6462 "-m:e" // ELF name manging 6463 "-p:32:32" // 32 bit pointers, 32 bit aligned 6464 "-i64:64" // 64 bit integers, 64 bit aligned 6465 "-a:0:32" // 32 bit alignment of objects of aggregate type 6466 "-n32" // 32 bit native integer width 6467 "-S64" // 64 bit natural stack alignment 6468 ); 6469 6470 // Setting RegParmMax equal to what mregparm was set to in the old 6471 // toolchain 6472 RegParmMax = 4; 6473 6474 // Set the default CPU to V11 6475 CPU = CK_V11; 6476 6477 // Temporary approach to make everything at least word-aligned and allow for 6478 // safely casting between pointers with different alignment requirements. 6479 // TODO: Remove this when there are no more cast align warnings on the 6480 // firmware. 6481 MinGlobalAlign = 32; 6482 } 6483 6484 void getTargetDefines(const LangOptions &Opts, 6485 MacroBuilder &Builder) const override { 6486 // Define __lanai__ when building for target lanai. 6487 Builder.defineMacro("__lanai__"); 6488 6489 // Set define for the CPU specified. 6490 switch (CPU) { 6491 case CK_V11: 6492 Builder.defineMacro("__LANAI_V11__"); 6493 break; 6494 case CK_NONE: 6495 llvm_unreachable("Unhandled target CPU"); 6496 } 6497 } 6498 6499 bool setCPU(const std::string &Name) override { 6500 CPU = llvm::StringSwitch<CPUKind>(Name) 6501 .Case("v11", CK_V11) 6502 .Default(CK_NONE); 6503 6504 return CPU != CK_NONE; 6505 } 6506 6507 bool hasFeature(StringRef Feature) const override { 6508 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6509 } 6510 6511 ArrayRef<const char *> getGCCRegNames() const override; 6512 6513 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6514 6515 BuiltinVaListKind getBuiltinVaListKind() const override { 6516 return TargetInfo::VoidPtrBuiltinVaList; 6517 } 6518 6519 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6520 6521 bool validateAsmConstraint(const char *&Name, 6522 TargetInfo::ConstraintInfo &info) const override { 6523 return false; 6524 } 6525 6526 const char *getClobbers() const override { return ""; } 6527 }; 6528 6529 const char *const LanaiTargetInfo::GCCRegNames[] = { 6530 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6531 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6532 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6533 6534 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6535 return llvm::makeArrayRef(GCCRegNames); 6536 } 6537 6538 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6539 {{"pc"}, "r2"}, 6540 {{"sp"}, "r4"}, 6541 {{"fp"}, "r5"}, 6542 {{"rv"}, "r8"}, 6543 {{"rr1"}, "r10"}, 6544 {{"rr2"}, "r11"}, 6545 {{"rca"}, "r15"}, 6546 }; 6547 6548 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6549 return llvm::makeArrayRef(GCCRegAliases); 6550 } 6551 6552 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6553 class SparcTargetInfo : public TargetInfo { 6554 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6555 static const char * const GCCRegNames[]; 6556 bool SoftFloat; 6557 public: 6558 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6559 : TargetInfo(Triple), SoftFloat(false) {} 6560 6561 int getEHDataRegisterNumber(unsigned RegNo) const override { 6562 if (RegNo == 0) return 24; 6563 if (RegNo == 1) return 25; 6564 return -1; 6565 } 6566 6567 bool handleTargetFeatures(std::vector<std::string> &Features, 6568 DiagnosticsEngine &Diags) override { 6569 // Check if software floating point is enabled 6570 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6571 if (Feature != Features.end()) { 6572 SoftFloat = true; 6573 } 6574 return true; 6575 } 6576 void getTargetDefines(const LangOptions &Opts, 6577 MacroBuilder &Builder) const override { 6578 DefineStd(Builder, "sparc", Opts); 6579 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6580 6581 if (SoftFloat) 6582 Builder.defineMacro("SOFT_FLOAT", "1"); 6583 } 6584 6585 bool hasFeature(StringRef Feature) const override { 6586 return llvm::StringSwitch<bool>(Feature) 6587 .Case("softfloat", SoftFloat) 6588 .Case("sparc", true) 6589 .Default(false); 6590 } 6591 6592 bool hasSjLjLowering() const override { 6593 return true; 6594 } 6595 6596 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6597 // FIXME: Implement! 6598 return None; 6599 } 6600 BuiltinVaListKind getBuiltinVaListKind() const override { 6601 return TargetInfo::VoidPtrBuiltinVaList; 6602 } 6603 ArrayRef<const char *> getGCCRegNames() const override; 6604 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6605 bool validateAsmConstraint(const char *&Name, 6606 TargetInfo::ConstraintInfo &info) const override { 6607 // FIXME: Implement! 6608 switch (*Name) { 6609 case 'I': // Signed 13-bit constant 6610 case 'J': // Zero 6611 case 'K': // 32-bit constant with the low 12 bits clear 6612 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6613 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6614 case 'N': // Same as 'K' but zext (required for SIMode) 6615 case 'O': // The constant 4096 6616 return true; 6617 } 6618 return false; 6619 } 6620 const char *getClobbers() const override { 6621 // FIXME: Implement! 6622 return ""; 6623 } 6624 6625 // No Sparc V7 for now, the backend doesn't support it anyway. 6626 enum CPUKind { 6627 CK_GENERIC, 6628 CK_V8, 6629 CK_SUPERSPARC, 6630 CK_SPARCLITE, 6631 CK_F934, 6632 CK_HYPERSPARC, 6633 CK_SPARCLITE86X, 6634 CK_SPARCLET, 6635 CK_TSC701, 6636 CK_V9, 6637 CK_ULTRASPARC, 6638 CK_ULTRASPARC3, 6639 CK_NIAGARA, 6640 CK_NIAGARA2, 6641 CK_NIAGARA3, 6642 CK_NIAGARA4, 6643 CK_MYRIAD2100, 6644 CK_MYRIAD2150, 6645 CK_MYRIAD2450, 6646 CK_LEON2, 6647 CK_LEON2_AT697E, 6648 CK_LEON2_AT697F, 6649 CK_LEON3, 6650 CK_LEON3_UT699, 6651 CK_LEON3_GR712RC, 6652 CK_LEON4, 6653 CK_LEON4_GR740 6654 } CPU = CK_GENERIC; 6655 6656 enum CPUGeneration { 6657 CG_V8, 6658 CG_V9, 6659 }; 6660 6661 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6662 switch (Kind) { 6663 case CK_GENERIC: 6664 case CK_V8: 6665 case CK_SUPERSPARC: 6666 case CK_SPARCLITE: 6667 case CK_F934: 6668 case CK_HYPERSPARC: 6669 case CK_SPARCLITE86X: 6670 case CK_SPARCLET: 6671 case CK_TSC701: 6672 case CK_MYRIAD2100: 6673 case CK_MYRIAD2150: 6674 case CK_MYRIAD2450: 6675 case CK_LEON2: 6676 case CK_LEON2_AT697E: 6677 case CK_LEON2_AT697F: 6678 case CK_LEON3: 6679 case CK_LEON3_UT699: 6680 case CK_LEON3_GR712RC: 6681 case CK_LEON4: 6682 case CK_LEON4_GR740: 6683 return CG_V8; 6684 case CK_V9: 6685 case CK_ULTRASPARC: 6686 case CK_ULTRASPARC3: 6687 case CK_NIAGARA: 6688 case CK_NIAGARA2: 6689 case CK_NIAGARA3: 6690 case CK_NIAGARA4: 6691 return CG_V9; 6692 } 6693 llvm_unreachable("Unexpected CPU kind"); 6694 } 6695 6696 CPUKind getCPUKind(StringRef Name) const { 6697 return llvm::StringSwitch<CPUKind>(Name) 6698 .Case("v8", CK_V8) 6699 .Case("supersparc", CK_SUPERSPARC) 6700 .Case("sparclite", CK_SPARCLITE) 6701 .Case("f934", CK_F934) 6702 .Case("hypersparc", CK_HYPERSPARC) 6703 .Case("sparclite86x", CK_SPARCLITE86X) 6704 .Case("sparclet", CK_SPARCLET) 6705 .Case("tsc701", CK_TSC701) 6706 .Case("v9", CK_V9) 6707 .Case("ultrasparc", CK_ULTRASPARC) 6708 .Case("ultrasparc3", CK_ULTRASPARC3) 6709 .Case("niagara", CK_NIAGARA) 6710 .Case("niagara2", CK_NIAGARA2) 6711 .Case("niagara3", CK_NIAGARA3) 6712 .Case("niagara4", CK_NIAGARA4) 6713 .Case("ma2100", CK_MYRIAD2100) 6714 .Case("ma2150", CK_MYRIAD2150) 6715 .Case("ma2450", CK_MYRIAD2450) 6716 // FIXME: the myriad2[.n] spellings are obsolete, 6717 // but a grace period is needed to allow updating dependent builds. 6718 .Case("myriad2", CK_MYRIAD2100) 6719 .Case("myriad2.1", CK_MYRIAD2100) 6720 .Case("myriad2.2", CK_MYRIAD2150) 6721 .Case("leon2", CK_LEON2) 6722 .Case("at697e", CK_LEON2_AT697E) 6723 .Case("at697f", CK_LEON2_AT697F) 6724 .Case("leon3", CK_LEON3) 6725 .Case("ut699", CK_LEON3_UT699) 6726 .Case("gr712rc", CK_LEON3_GR712RC) 6727 .Case("leon4", CK_LEON4) 6728 .Case("gr740", CK_LEON4_GR740) 6729 .Default(CK_GENERIC); 6730 } 6731 6732 bool setCPU(const std::string &Name) override { 6733 CPU = getCPUKind(Name); 6734 return CPU != CK_GENERIC; 6735 } 6736 }; 6737 6738 const char * const SparcTargetInfo::GCCRegNames[] = { 6739 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6740 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6741 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6742 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6743 }; 6744 6745 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6746 return llvm::makeArrayRef(GCCRegNames); 6747 } 6748 6749 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6750 { { "g0" }, "r0" }, 6751 { { "g1" }, "r1" }, 6752 { { "g2" }, "r2" }, 6753 { { "g3" }, "r3" }, 6754 { { "g4" }, "r4" }, 6755 { { "g5" }, "r5" }, 6756 { { "g6" }, "r6" }, 6757 { { "g7" }, "r7" }, 6758 { { "o0" }, "r8" }, 6759 { { "o1" }, "r9" }, 6760 { { "o2" }, "r10" }, 6761 { { "o3" }, "r11" }, 6762 { { "o4" }, "r12" }, 6763 { { "o5" }, "r13" }, 6764 { { "o6", "sp" }, "r14" }, 6765 { { "o7" }, "r15" }, 6766 { { "l0" }, "r16" }, 6767 { { "l1" }, "r17" }, 6768 { { "l2" }, "r18" }, 6769 { { "l3" }, "r19" }, 6770 { { "l4" }, "r20" }, 6771 { { "l5" }, "r21" }, 6772 { { "l6" }, "r22" }, 6773 { { "l7" }, "r23" }, 6774 { { "i0" }, "r24" }, 6775 { { "i1" }, "r25" }, 6776 { { "i2" }, "r26" }, 6777 { { "i3" }, "r27" }, 6778 { { "i4" }, "r28" }, 6779 { { "i5" }, "r29" }, 6780 { { "i6", "fp" }, "r30" }, 6781 { { "i7" }, "r31" }, 6782 }; 6783 6784 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6785 return llvm::makeArrayRef(GCCRegAliases); 6786 } 6787 6788 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6789 class SparcV8TargetInfo : public SparcTargetInfo { 6790 public: 6791 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6792 : SparcTargetInfo(Triple, Opts) { 6793 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6794 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6795 switch (getTriple().getOS()) { 6796 default: 6797 SizeType = UnsignedInt; 6798 IntPtrType = SignedInt; 6799 PtrDiffType = SignedInt; 6800 break; 6801 case llvm::Triple::NetBSD: 6802 case llvm::Triple::OpenBSD: 6803 SizeType = UnsignedLong; 6804 IntPtrType = SignedLong; 6805 PtrDiffType = SignedLong; 6806 break; 6807 } 6808 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops 6809 // on up to 64 bits. 6810 MaxAtomicPromoteWidth = 64; 6811 MaxAtomicInlineWidth = 32; 6812 } 6813 6814 void getTargetDefines(const LangOptions &Opts, 6815 MacroBuilder &Builder) const override { 6816 SparcTargetInfo::getTargetDefines(Opts, Builder); 6817 switch (getCPUGeneration(CPU)) { 6818 case CG_V8: 6819 Builder.defineMacro("__sparcv8"); 6820 if (getTriple().getOS() != llvm::Triple::Solaris) 6821 Builder.defineMacro("__sparcv8__"); 6822 break; 6823 case CG_V9: 6824 Builder.defineMacro("__sparcv9"); 6825 if (getTriple().getOS() != llvm::Triple::Solaris) { 6826 Builder.defineMacro("__sparcv9__"); 6827 Builder.defineMacro("__sparc_v9__"); 6828 } 6829 break; 6830 } 6831 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6832 std::string MyriadArchValue, Myriad2Value; 6833 Builder.defineMacro("__sparc_v8__"); 6834 Builder.defineMacro("__leon__"); 6835 switch (CPU) { 6836 case CK_MYRIAD2150: 6837 MyriadArchValue = "__ma2150"; 6838 Myriad2Value = "2"; 6839 break; 6840 case CK_MYRIAD2450: 6841 MyriadArchValue = "__ma2450"; 6842 Myriad2Value = "2"; 6843 break; 6844 default: 6845 MyriadArchValue = "__ma2100"; 6846 Myriad2Value = "1"; 6847 break; 6848 } 6849 Builder.defineMacro(MyriadArchValue, "1"); 6850 Builder.defineMacro(MyriadArchValue+"__", "1"); 6851 Builder.defineMacro("__myriad2__", Myriad2Value); 6852 Builder.defineMacro("__myriad2", Myriad2Value); 6853 } 6854 } 6855 6856 bool hasSjLjLowering() const override { 6857 return true; 6858 } 6859 }; 6860 6861 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6862 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6863 public: 6864 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6865 : SparcV8TargetInfo(Triple, Opts) { 6866 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6867 } 6868 }; 6869 6870 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6871 class SparcV9TargetInfo : public SparcTargetInfo { 6872 public: 6873 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6874 : SparcTargetInfo(Triple, Opts) { 6875 // FIXME: Support Sparc quad-precision long double? 6876 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6877 // This is an LP64 platform. 6878 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6879 6880 // OpenBSD uses long long for int64_t and intmax_t. 6881 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6882 IntMaxType = SignedLongLong; 6883 else 6884 IntMaxType = SignedLong; 6885 Int64Type = IntMaxType; 6886 6887 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6888 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6889 LongDoubleWidth = 128; 6890 LongDoubleAlign = 128; 6891 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6892 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6893 } 6894 6895 void getTargetDefines(const LangOptions &Opts, 6896 MacroBuilder &Builder) const override { 6897 SparcTargetInfo::getTargetDefines(Opts, Builder); 6898 Builder.defineMacro("__sparcv9"); 6899 Builder.defineMacro("__arch64__"); 6900 // Solaris doesn't need these variants, but the BSDs do. 6901 if (getTriple().getOS() != llvm::Triple::Solaris) { 6902 Builder.defineMacro("__sparc64__"); 6903 Builder.defineMacro("__sparc_v9__"); 6904 Builder.defineMacro("__sparcv9__"); 6905 } 6906 } 6907 6908 bool setCPU(const std::string &Name) override { 6909 if (!SparcTargetInfo::setCPU(Name)) 6910 return false; 6911 return getCPUGeneration(CPU) == CG_V9; 6912 } 6913 }; 6914 6915 class SystemZTargetInfo : public TargetInfo { 6916 static const Builtin::Info BuiltinInfo[]; 6917 static const char *const GCCRegNames[]; 6918 std::string CPU; 6919 bool HasTransactionalExecution; 6920 bool HasVector; 6921 6922 public: 6923 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6924 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6925 HasVector(false) { 6926 IntMaxType = SignedLong; 6927 Int64Type = SignedLong; 6928 TLSSupported = true; 6929 IntWidth = IntAlign = 32; 6930 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6931 PointerWidth = PointerAlign = 64; 6932 LongDoubleWidth = 128; 6933 LongDoubleAlign = 64; 6934 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6935 DefaultAlignForAttributeAligned = 64; 6936 MinGlobalAlign = 16; 6937 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 6938 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6939 } 6940 void getTargetDefines(const LangOptions &Opts, 6941 MacroBuilder &Builder) const override { 6942 Builder.defineMacro("__s390__"); 6943 Builder.defineMacro("__s390x__"); 6944 Builder.defineMacro("__zarch__"); 6945 Builder.defineMacro("__LONG_DOUBLE_128__"); 6946 6947 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6948 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6949 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6950 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6951 6952 if (HasTransactionalExecution) 6953 Builder.defineMacro("__HTM__"); 6954 if (Opts.ZVector) 6955 Builder.defineMacro("__VEC__", "10301"); 6956 } 6957 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6958 return llvm::makeArrayRef(BuiltinInfo, 6959 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6960 } 6961 6962 ArrayRef<const char *> getGCCRegNames() const override; 6963 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6964 // No aliases. 6965 return None; 6966 } 6967 bool validateAsmConstraint(const char *&Name, 6968 TargetInfo::ConstraintInfo &info) const override; 6969 const char *getClobbers() const override { 6970 // FIXME: Is this really right? 6971 return ""; 6972 } 6973 BuiltinVaListKind getBuiltinVaListKind() const override { 6974 return TargetInfo::SystemZBuiltinVaList; 6975 } 6976 bool setCPU(const std::string &Name) override { 6977 CPU = Name; 6978 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6979 .Case("z10", true) 6980 .Case("arch8", true) 6981 .Case("z196", true) 6982 .Case("arch9", true) 6983 .Case("zEC12", true) 6984 .Case("arch10", true) 6985 .Case("z13", true) 6986 .Case("arch11", true) 6987 .Default(false); 6988 6989 return CPUKnown; 6990 } 6991 bool 6992 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6993 StringRef CPU, 6994 const std::vector<std::string> &FeaturesVec) const override { 6995 if (CPU == "zEC12" || CPU == "arch10") 6996 Features["transactional-execution"] = true; 6997 if (CPU == "z13" || CPU == "arch11") { 6998 Features["transactional-execution"] = true; 6999 Features["vector"] = true; 7000 } 7001 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7002 } 7003 7004 bool handleTargetFeatures(std::vector<std::string> &Features, 7005 DiagnosticsEngine &Diags) override { 7006 HasTransactionalExecution = false; 7007 for (const auto &Feature : Features) { 7008 if (Feature == "+transactional-execution") 7009 HasTransactionalExecution = true; 7010 else if (Feature == "+vector") 7011 HasVector = true; 7012 } 7013 // If we use the vector ABI, vector types are 64-bit aligned. 7014 if (HasVector) { 7015 MaxVectorAlign = 64; 7016 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 7017 "-v128:64-a:8:16-n32:64"); 7018 } 7019 return true; 7020 } 7021 7022 bool hasFeature(StringRef Feature) const override { 7023 return llvm::StringSwitch<bool>(Feature) 7024 .Case("systemz", true) 7025 .Case("htm", HasTransactionalExecution) 7026 .Case("vx", HasVector) 7027 .Default(false); 7028 } 7029 7030 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7031 switch (CC) { 7032 case CC_C: 7033 case CC_Swift: 7034 return CCCR_OK; 7035 default: 7036 return CCCR_Warning; 7037 } 7038 } 7039 7040 StringRef getABI() const override { 7041 if (HasVector) 7042 return "vector"; 7043 return ""; 7044 } 7045 7046 bool useFloat128ManglingForLongDouble() const override { 7047 return true; 7048 } 7049 }; 7050 7051 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 7052 #define BUILTIN(ID, TYPE, ATTRS) \ 7053 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7054 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7055 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 7056 #include "clang/Basic/BuiltinsSystemZ.def" 7057 }; 7058 7059 const char *const SystemZTargetInfo::GCCRegNames[] = { 7060 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7061 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7062 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 7063 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 7064 }; 7065 7066 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 7067 return llvm::makeArrayRef(GCCRegNames); 7068 } 7069 7070 bool SystemZTargetInfo:: 7071 validateAsmConstraint(const char *&Name, 7072 TargetInfo::ConstraintInfo &Info) const { 7073 switch (*Name) { 7074 default: 7075 return false; 7076 7077 case 'a': // Address register 7078 case 'd': // Data register (equivalent to 'r') 7079 case 'f': // Floating-point register 7080 Info.setAllowsRegister(); 7081 return true; 7082 7083 case 'I': // Unsigned 8-bit constant 7084 case 'J': // Unsigned 12-bit constant 7085 case 'K': // Signed 16-bit constant 7086 case 'L': // Signed 20-bit displacement (on all targets we support) 7087 case 'M': // 0x7fffffff 7088 return true; 7089 7090 case 'Q': // Memory with base and unsigned 12-bit displacement 7091 case 'R': // Likewise, plus an index 7092 case 'S': // Memory with base and signed 20-bit displacement 7093 case 'T': // Likewise, plus an index 7094 Info.setAllowsMemory(); 7095 return true; 7096 } 7097 } 7098 7099 class MSP430TargetInfo : public TargetInfo { 7100 static const char *const GCCRegNames[]; 7101 7102 public: 7103 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7104 : TargetInfo(Triple) { 7105 TLSSupported = false; 7106 IntWidth = 16; 7107 IntAlign = 16; 7108 LongWidth = 32; 7109 LongLongWidth = 64; 7110 LongAlign = LongLongAlign = 16; 7111 PointerWidth = 16; 7112 PointerAlign = 16; 7113 SuitableAlign = 16; 7114 SizeType = UnsignedInt; 7115 IntMaxType = SignedLongLong; 7116 IntPtrType = SignedInt; 7117 PtrDiffType = SignedInt; 7118 SigAtomicType = SignedLong; 7119 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 7120 } 7121 void getTargetDefines(const LangOptions &Opts, 7122 MacroBuilder &Builder) const override { 7123 Builder.defineMacro("MSP430"); 7124 Builder.defineMacro("__MSP430__"); 7125 // FIXME: defines for different 'flavours' of MCU 7126 } 7127 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7128 // FIXME: Implement. 7129 return None; 7130 } 7131 bool hasFeature(StringRef Feature) const override { 7132 return Feature == "msp430"; 7133 } 7134 ArrayRef<const char *> getGCCRegNames() const override; 7135 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7136 // No aliases. 7137 return None; 7138 } 7139 bool validateAsmConstraint(const char *&Name, 7140 TargetInfo::ConstraintInfo &info) const override { 7141 // FIXME: implement 7142 switch (*Name) { 7143 case 'K': // the constant 1 7144 case 'L': // constant -1^20 .. 1^19 7145 case 'M': // constant 1-4: 7146 return true; 7147 } 7148 // No target constraints for now. 7149 return false; 7150 } 7151 const char *getClobbers() const override { 7152 // FIXME: Is this really right? 7153 return ""; 7154 } 7155 BuiltinVaListKind getBuiltinVaListKind() const override { 7156 // FIXME: implement 7157 return TargetInfo::CharPtrBuiltinVaList; 7158 } 7159 }; 7160 7161 const char *const MSP430TargetInfo::GCCRegNames[] = { 7162 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7163 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7164 7165 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7166 return llvm::makeArrayRef(GCCRegNames); 7167 } 7168 7169 // LLVM and Clang cannot be used directly to output native binaries for 7170 // target, but is used to compile C code to llvm bitcode with correct 7171 // type and alignment information. 7172 // 7173 // TCE uses the llvm bitcode as input and uses it for generating customized 7174 // target processor and program binary. TCE co-design environment is 7175 // publicly available in http://tce.cs.tut.fi 7176 7177 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7178 3, // opencl_global 7179 4, // opencl_local 7180 5, // opencl_constant 7181 // FIXME: generic has to be added to the target 7182 0, // opencl_generic 7183 0, // cuda_device 7184 0, // cuda_constant 7185 0 // cuda_shared 7186 }; 7187 7188 class TCETargetInfo : public TargetInfo { 7189 public: 7190 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7191 : TargetInfo(Triple) { 7192 TLSSupported = false; 7193 IntWidth = 32; 7194 LongWidth = LongLongWidth = 32; 7195 PointerWidth = 32; 7196 IntAlign = 32; 7197 LongAlign = LongLongAlign = 32; 7198 PointerAlign = 32; 7199 SuitableAlign = 32; 7200 SizeType = UnsignedInt; 7201 IntMaxType = SignedLong; 7202 IntPtrType = SignedInt; 7203 PtrDiffType = SignedInt; 7204 FloatWidth = 32; 7205 FloatAlign = 32; 7206 DoubleWidth = 32; 7207 DoubleAlign = 32; 7208 LongDoubleWidth = 32; 7209 LongDoubleAlign = 32; 7210 FloatFormat = &llvm::APFloat::IEEEsingle; 7211 DoubleFormat = &llvm::APFloat::IEEEsingle; 7212 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 7213 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-" 7214 "i16:16:32-i32:32:32-i64:32:32-" 7215 "f32:32:32-f64:32:32-v64:32:32-" 7216 "v128:32:32-v256:32:32-v512:32:32-" 7217 "v1024:32:32-a0:0:32-n32"); 7218 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7219 UseAddrSpaceMapMangling = true; 7220 } 7221 7222 void getTargetDefines(const LangOptions &Opts, 7223 MacroBuilder &Builder) const override { 7224 DefineStd(Builder, "tce", Opts); 7225 Builder.defineMacro("__TCE__"); 7226 Builder.defineMacro("__TCE_V1__"); 7227 } 7228 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7229 7230 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7231 const char *getClobbers() const override { return ""; } 7232 BuiltinVaListKind getBuiltinVaListKind() const override { 7233 return TargetInfo::VoidPtrBuiltinVaList; 7234 } 7235 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7236 bool validateAsmConstraint(const char *&Name, 7237 TargetInfo::ConstraintInfo &info) const override { 7238 return true; 7239 } 7240 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7241 return None; 7242 } 7243 }; 7244 7245 class TCELETargetInfo : public TCETargetInfo { 7246 public: 7247 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7248 : TCETargetInfo(Triple, Opts) { 7249 BigEndian = false; 7250 7251 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-" 7252 "i16:16:32-i32:32:32-i64:32:32-" 7253 "f32:32:32-f64:32:32-v64:32:32-" 7254 "v128:32:32-v256:32:32-v512:32:32-" 7255 "v1024:32:32-a0:0:32-n32"); 7256 7257 } 7258 7259 virtual void getTargetDefines(const LangOptions &Opts, 7260 MacroBuilder &Builder) const { 7261 DefineStd(Builder, "tcele", Opts); 7262 Builder.defineMacro("__TCE__"); 7263 Builder.defineMacro("__TCE_V1__"); 7264 Builder.defineMacro("__TCELE__"); 7265 Builder.defineMacro("__TCELE_V1__"); 7266 } 7267 7268 }; 7269 7270 class BPFTargetInfo : public TargetInfo { 7271 public: 7272 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7273 : TargetInfo(Triple) { 7274 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7275 SizeType = UnsignedLong; 7276 PtrDiffType = SignedLong; 7277 IntPtrType = SignedLong; 7278 IntMaxType = SignedLong; 7279 Int64Type = SignedLong; 7280 RegParmMax = 5; 7281 if (Triple.getArch() == llvm::Triple::bpfeb) { 7282 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7283 } else { 7284 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7285 } 7286 MaxAtomicPromoteWidth = 64; 7287 MaxAtomicInlineWidth = 64; 7288 TLSSupported = false; 7289 } 7290 void getTargetDefines(const LangOptions &Opts, 7291 MacroBuilder &Builder) const override { 7292 DefineStd(Builder, "bpf", Opts); 7293 Builder.defineMacro("__BPF__"); 7294 } 7295 bool hasFeature(StringRef Feature) const override { 7296 return Feature == "bpf"; 7297 } 7298 7299 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7300 const char *getClobbers() const override { 7301 return ""; 7302 } 7303 BuiltinVaListKind getBuiltinVaListKind() const override { 7304 return TargetInfo::VoidPtrBuiltinVaList; 7305 } 7306 ArrayRef<const char *> getGCCRegNames() const override { 7307 return None; 7308 } 7309 bool validateAsmConstraint(const char *&Name, 7310 TargetInfo::ConstraintInfo &info) const override { 7311 return true; 7312 } 7313 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7314 return None; 7315 } 7316 }; 7317 7318 class MipsTargetInfo : public TargetInfo { 7319 void setDataLayout() { 7320 StringRef Layout; 7321 7322 if (ABI == "o32") 7323 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7324 else if (ABI == "n32") 7325 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7326 else if (ABI == "n64") 7327 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7328 else 7329 llvm_unreachable("Invalid ABI"); 7330 7331 if (BigEndian) 7332 resetDataLayout(("E-" + Layout).str()); 7333 else 7334 resetDataLayout(("e-" + Layout).str()); 7335 } 7336 7337 7338 static const Builtin::Info BuiltinInfo[]; 7339 std::string CPU; 7340 bool IsMips16; 7341 bool IsMicromips; 7342 bool IsNan2008; 7343 bool IsSingleFloat; 7344 enum MipsFloatABI { 7345 HardFloat, SoftFloat 7346 } FloatABI; 7347 enum DspRevEnum { 7348 NoDSP, DSP1, DSP2 7349 } DspRev; 7350 bool HasMSA; 7351 7352 protected: 7353 bool HasFP64; 7354 std::string ABI; 7355 7356 public: 7357 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7358 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7359 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 7360 DspRev(NoDSP), HasMSA(false), HasFP64(false) { 7361 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7362 7363 setABI((getTriple().getArch() == llvm::Triple::mips || 7364 getTriple().getArch() == llvm::Triple::mipsel) 7365 ? "o32" 7366 : "n64"); 7367 7368 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7369 } 7370 7371 bool isNaN2008Default() const { 7372 return CPU == "mips32r6" || CPU == "mips64r6"; 7373 } 7374 7375 bool isFP64Default() const { 7376 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7377 } 7378 7379 bool isNan2008() const override { 7380 return IsNan2008; 7381 } 7382 7383 bool processorSupportsGPR64() const { 7384 return llvm::StringSwitch<bool>(CPU) 7385 .Case("mips3", true) 7386 .Case("mips4", true) 7387 .Case("mips5", true) 7388 .Case("mips64", true) 7389 .Case("mips64r2", true) 7390 .Case("mips64r3", true) 7391 .Case("mips64r5", true) 7392 .Case("mips64r6", true) 7393 .Case("octeon", true) 7394 .Default(false); 7395 return false; 7396 } 7397 7398 StringRef getABI() const override { return ABI; } 7399 bool setABI(const std::string &Name) override { 7400 if (Name == "o32") { 7401 setO32ABITypes(); 7402 ABI = Name; 7403 return true; 7404 } 7405 7406 if (Name == "n32") { 7407 setN32ABITypes(); 7408 ABI = Name; 7409 return true; 7410 } 7411 if (Name == "n64") { 7412 setN64ABITypes(); 7413 ABI = Name; 7414 return true; 7415 } 7416 return false; 7417 } 7418 7419 void setO32ABITypes() { 7420 Int64Type = SignedLongLong; 7421 IntMaxType = Int64Type; 7422 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7423 LongDoubleWidth = LongDoubleAlign = 64; 7424 LongWidth = LongAlign = 32; 7425 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7426 PointerWidth = PointerAlign = 32; 7427 PtrDiffType = SignedInt; 7428 SizeType = UnsignedInt; 7429 SuitableAlign = 64; 7430 } 7431 7432 void setN32N64ABITypes() { 7433 LongDoubleWidth = LongDoubleAlign = 128; 7434 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7435 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7436 LongDoubleWidth = LongDoubleAlign = 64; 7437 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7438 } 7439 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7440 SuitableAlign = 128; 7441 } 7442 7443 void setN64ABITypes() { 7444 setN32N64ABITypes(); 7445 Int64Type = SignedLong; 7446 IntMaxType = Int64Type; 7447 LongWidth = LongAlign = 64; 7448 PointerWidth = PointerAlign = 64; 7449 PtrDiffType = SignedLong; 7450 SizeType = UnsignedLong; 7451 } 7452 7453 void setN32ABITypes() { 7454 setN32N64ABITypes(); 7455 Int64Type = SignedLongLong; 7456 IntMaxType = Int64Type; 7457 LongWidth = LongAlign = 32; 7458 PointerWidth = PointerAlign = 32; 7459 PtrDiffType = SignedInt; 7460 SizeType = UnsignedInt; 7461 } 7462 7463 bool setCPU(const std::string &Name) override { 7464 CPU = Name; 7465 return llvm::StringSwitch<bool>(Name) 7466 .Case("mips1", true) 7467 .Case("mips2", true) 7468 .Case("mips3", true) 7469 .Case("mips4", true) 7470 .Case("mips5", true) 7471 .Case("mips32", true) 7472 .Case("mips32r2", true) 7473 .Case("mips32r3", true) 7474 .Case("mips32r5", true) 7475 .Case("mips32r6", true) 7476 .Case("mips64", true) 7477 .Case("mips64r2", true) 7478 .Case("mips64r3", true) 7479 .Case("mips64r5", true) 7480 .Case("mips64r6", true) 7481 .Case("octeon", true) 7482 .Case("p5600", true) 7483 .Default(false); 7484 } 7485 const std::string& getCPU() const { return CPU; } 7486 bool 7487 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7488 StringRef CPU, 7489 const std::vector<std::string> &FeaturesVec) const override { 7490 if (CPU.empty()) 7491 CPU = getCPU(); 7492 if (CPU == "octeon") 7493 Features["mips64r2"] = Features["cnmips"] = true; 7494 else 7495 Features[CPU] = true; 7496 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7497 } 7498 7499 void getTargetDefines(const LangOptions &Opts, 7500 MacroBuilder &Builder) const override { 7501 if (BigEndian) { 7502 DefineStd(Builder, "MIPSEB", Opts); 7503 Builder.defineMacro("_MIPSEB"); 7504 } else { 7505 DefineStd(Builder, "MIPSEL", Opts); 7506 Builder.defineMacro("_MIPSEL"); 7507 } 7508 7509 Builder.defineMacro("__mips__"); 7510 Builder.defineMacro("_mips"); 7511 if (Opts.GNUMode) 7512 Builder.defineMacro("mips"); 7513 7514 if (ABI == "o32") { 7515 Builder.defineMacro("__mips", "32"); 7516 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7517 } else { 7518 Builder.defineMacro("__mips", "64"); 7519 Builder.defineMacro("__mips64"); 7520 Builder.defineMacro("__mips64__"); 7521 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7522 } 7523 7524 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7525 .Cases("mips32", "mips64", "1") 7526 .Cases("mips32r2", "mips64r2", "2") 7527 .Cases("mips32r3", "mips64r3", "3") 7528 .Cases("mips32r5", "mips64r5", "5") 7529 .Cases("mips32r6", "mips64r6", "6") 7530 .Default(""); 7531 if (!ISARev.empty()) 7532 Builder.defineMacro("__mips_isa_rev", ISARev); 7533 7534 if (ABI == "o32") { 7535 Builder.defineMacro("__mips_o32"); 7536 Builder.defineMacro("_ABIO32", "1"); 7537 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7538 } else if (ABI == "n32") { 7539 Builder.defineMacro("__mips_n32"); 7540 Builder.defineMacro("_ABIN32", "2"); 7541 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7542 } else if (ABI == "n64") { 7543 Builder.defineMacro("__mips_n64"); 7544 Builder.defineMacro("_ABI64", "3"); 7545 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7546 } else 7547 llvm_unreachable("Invalid ABI."); 7548 7549 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7550 7551 switch (FloatABI) { 7552 case HardFloat: 7553 Builder.defineMacro("__mips_hard_float", Twine(1)); 7554 break; 7555 case SoftFloat: 7556 Builder.defineMacro("__mips_soft_float", Twine(1)); 7557 break; 7558 } 7559 7560 if (IsSingleFloat) 7561 Builder.defineMacro("__mips_single_float", Twine(1)); 7562 7563 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7564 Builder.defineMacro("_MIPS_FPSET", 7565 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7566 7567 if (IsMips16) 7568 Builder.defineMacro("__mips16", Twine(1)); 7569 7570 if (IsMicromips) 7571 Builder.defineMacro("__mips_micromips", Twine(1)); 7572 7573 if (IsNan2008) 7574 Builder.defineMacro("__mips_nan2008", Twine(1)); 7575 7576 switch (DspRev) { 7577 default: 7578 break; 7579 case DSP1: 7580 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7581 Builder.defineMacro("__mips_dsp", Twine(1)); 7582 break; 7583 case DSP2: 7584 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7585 Builder.defineMacro("__mips_dspr2", Twine(1)); 7586 Builder.defineMacro("__mips_dsp", Twine(1)); 7587 break; 7588 } 7589 7590 if (HasMSA) 7591 Builder.defineMacro("__mips_msa", Twine(1)); 7592 7593 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7594 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7595 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7596 7597 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7598 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7599 7600 // These shouldn't be defined for MIPS-I but there's no need to check 7601 // for that since MIPS-I isn't supported. 7602 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7603 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7604 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7605 7606 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7607 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7608 // the instructions exist but using them violates the ABI since they 7609 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7610 if (ABI == "n32" || ABI == "n64") 7611 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7612 } 7613 7614 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7615 return llvm::makeArrayRef(BuiltinInfo, 7616 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7617 } 7618 bool hasFeature(StringRef Feature) const override { 7619 return llvm::StringSwitch<bool>(Feature) 7620 .Case("mips", true) 7621 .Case("fp64", HasFP64) 7622 .Default(false); 7623 } 7624 BuiltinVaListKind getBuiltinVaListKind() const override { 7625 return TargetInfo::VoidPtrBuiltinVaList; 7626 } 7627 ArrayRef<const char *> getGCCRegNames() const override { 7628 static const char *const GCCRegNames[] = { 7629 // CPU register names 7630 // Must match second column of GCCRegAliases 7631 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7632 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7633 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7634 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7635 // Floating point register names 7636 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7637 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7638 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7639 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7640 // Hi/lo and condition register names 7641 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7642 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7643 "$ac3hi","$ac3lo", 7644 // MSA register names 7645 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7646 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7647 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7648 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7649 // MSA control register names 7650 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7651 "$msarequest", "$msamap", "$msaunmap" 7652 }; 7653 return llvm::makeArrayRef(GCCRegNames); 7654 } 7655 bool validateAsmConstraint(const char *&Name, 7656 TargetInfo::ConstraintInfo &Info) const override { 7657 switch (*Name) { 7658 default: 7659 return false; 7660 case 'r': // CPU registers. 7661 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7662 case 'y': // Equivalent to "r", backward compatibility only. 7663 case 'f': // floating-point registers. 7664 case 'c': // $25 for indirect jumps 7665 case 'l': // lo register 7666 case 'x': // hilo register pair 7667 Info.setAllowsRegister(); 7668 return true; 7669 case 'I': // Signed 16-bit constant 7670 case 'J': // Integer 0 7671 case 'K': // Unsigned 16-bit constant 7672 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7673 case 'M': // Constants not loadable via lui, addiu, or ori 7674 case 'N': // Constant -1 to -65535 7675 case 'O': // A signed 15-bit constant 7676 case 'P': // A constant between 1 go 65535 7677 return true; 7678 case 'R': // An address that can be used in a non-macro load or store 7679 Info.setAllowsMemory(); 7680 return true; 7681 case 'Z': 7682 if (Name[1] == 'C') { // An address usable by ll, and sc. 7683 Info.setAllowsMemory(); 7684 Name++; // Skip over 'Z'. 7685 return true; 7686 } 7687 return false; 7688 } 7689 } 7690 7691 std::string convertConstraint(const char *&Constraint) const override { 7692 std::string R; 7693 switch (*Constraint) { 7694 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7695 if (Constraint[1] == 'C') { 7696 R = std::string("^") + std::string(Constraint, 2); 7697 Constraint++; 7698 return R; 7699 } 7700 break; 7701 } 7702 return TargetInfo::convertConstraint(Constraint); 7703 } 7704 7705 const char *getClobbers() const override { 7706 // In GCC, $1 is not widely used in generated code (it's used only in a few 7707 // specific situations), so there is no real need for users to add it to 7708 // the clobbers list if they want to use it in their inline assembly code. 7709 // 7710 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7711 // code generation, so using it in inline assembly without adding it to the 7712 // clobbers list can cause conflicts between the inline assembly code and 7713 // the surrounding generated code. 7714 // 7715 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7716 // operands, which will conflict with the ".set at" assembler option (which 7717 // we use only for inline assembly, in order to maintain compatibility with 7718 // GCC) and will also conflict with the user's usage of $1. 7719 // 7720 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7721 // register for generated code is to automatically clobber $1 for all inline 7722 // assembly code. 7723 // 7724 // FIXME: We should automatically clobber $1 only for inline assembly code 7725 // which actually uses it. This would allow LLVM to use $1 for inline 7726 // assembly operands if the user's assembly code doesn't use it. 7727 return "~{$1}"; 7728 } 7729 7730 bool handleTargetFeatures(std::vector<std::string> &Features, 7731 DiagnosticsEngine &Diags) override { 7732 IsMips16 = false; 7733 IsMicromips = false; 7734 IsNan2008 = isNaN2008Default(); 7735 IsSingleFloat = false; 7736 FloatABI = HardFloat; 7737 DspRev = NoDSP; 7738 HasFP64 = isFP64Default(); 7739 7740 for (const auto &Feature : Features) { 7741 if (Feature == "+single-float") 7742 IsSingleFloat = true; 7743 else if (Feature == "+soft-float") 7744 FloatABI = SoftFloat; 7745 else if (Feature == "+mips16") 7746 IsMips16 = true; 7747 else if (Feature == "+micromips") 7748 IsMicromips = true; 7749 else if (Feature == "+dsp") 7750 DspRev = std::max(DspRev, DSP1); 7751 else if (Feature == "+dspr2") 7752 DspRev = std::max(DspRev, DSP2); 7753 else if (Feature == "+msa") 7754 HasMSA = true; 7755 else if (Feature == "+fp64") 7756 HasFP64 = true; 7757 else if (Feature == "-fp64") 7758 HasFP64 = false; 7759 else if (Feature == "+nan2008") 7760 IsNan2008 = true; 7761 else if (Feature == "-nan2008") 7762 IsNan2008 = false; 7763 } 7764 7765 setDataLayout(); 7766 7767 return true; 7768 } 7769 7770 int getEHDataRegisterNumber(unsigned RegNo) const override { 7771 if (RegNo == 0) return 4; 7772 if (RegNo == 1) return 5; 7773 return -1; 7774 } 7775 7776 bool isCLZForZeroUndef() const override { return false; } 7777 7778 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7779 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 7780 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7781 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7782 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 7783 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 7784 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 7785 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7786 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7787 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7788 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7789 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7790 {{"ra"}, "$31"}}; 7791 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 7792 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7793 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7794 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 7795 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 7796 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 7797 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7798 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7799 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7800 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7801 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7802 {{"ra"}, "$31"}}; 7803 if (ABI == "o32") 7804 return llvm::makeArrayRef(O32RegAliases); 7805 return llvm::makeArrayRef(NewABIRegAliases); 7806 } 7807 7808 bool hasInt128Type() const override { 7809 return ABI == "n32" || ABI == "n64"; 7810 } 7811 7812 bool validateTarget(DiagnosticsEngine &Diags) const override { 7813 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 7814 // this yet. It's better to fail here than on the backend assertion. 7815 if (processorSupportsGPR64() && ABI == "o32") { 7816 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7817 return false; 7818 } 7819 7820 // 64-bit ABI's require 64-bit CPU's. 7821 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 7822 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7823 return false; 7824 } 7825 7826 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 7827 // can't handle this yet. It's better to fail here than on the 7828 // backend assertion. 7829 if ((getTriple().getArch() == llvm::Triple::mips64 || 7830 getTriple().getArch() == llvm::Triple::mips64el) && 7831 ABI == "o32") { 7832 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7833 << ABI << getTriple().str(); 7834 return false; 7835 } 7836 7837 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 7838 // can't handle this yet. It's better to fail here than on the 7839 // backend assertion. 7840 if ((getTriple().getArch() == llvm::Triple::mips || 7841 getTriple().getArch() == llvm::Triple::mipsel) && 7842 (ABI == "n32" || ABI == "n64")) { 7843 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7844 << ABI << getTriple().str(); 7845 return false; 7846 } 7847 7848 return true; 7849 } 7850 }; 7851 7852 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 7853 #define BUILTIN(ID, TYPE, ATTRS) \ 7854 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7855 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7856 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7857 #include "clang/Basic/BuiltinsMips.def" 7858 }; 7859 7860 class PNaClTargetInfo : public TargetInfo { 7861 public: 7862 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7863 : TargetInfo(Triple) { 7864 this->LongAlign = 32; 7865 this->LongWidth = 32; 7866 this->PointerAlign = 32; 7867 this->PointerWidth = 32; 7868 this->IntMaxType = TargetInfo::SignedLongLong; 7869 this->Int64Type = TargetInfo::SignedLongLong; 7870 this->DoubleAlign = 64; 7871 this->LongDoubleWidth = 64; 7872 this->LongDoubleAlign = 64; 7873 this->SizeType = TargetInfo::UnsignedInt; 7874 this->PtrDiffType = TargetInfo::SignedInt; 7875 this->IntPtrType = TargetInfo::SignedInt; 7876 this->RegParmMax = 0; // Disallow regparm 7877 } 7878 7879 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7880 Builder.defineMacro("__le32__"); 7881 Builder.defineMacro("__pnacl__"); 7882 } 7883 void getTargetDefines(const LangOptions &Opts, 7884 MacroBuilder &Builder) const override { 7885 getArchDefines(Opts, Builder); 7886 } 7887 bool hasFeature(StringRef Feature) const override { 7888 return Feature == "pnacl"; 7889 } 7890 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7891 BuiltinVaListKind getBuiltinVaListKind() const override { 7892 return TargetInfo::PNaClABIBuiltinVaList; 7893 } 7894 ArrayRef<const char *> getGCCRegNames() const override; 7895 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7896 bool validateAsmConstraint(const char *&Name, 7897 TargetInfo::ConstraintInfo &Info) const override { 7898 return false; 7899 } 7900 7901 const char *getClobbers() const override { 7902 return ""; 7903 } 7904 }; 7905 7906 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7907 return None; 7908 } 7909 7910 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7911 return None; 7912 } 7913 7914 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7915 class NaClMips32TargetInfo : public MipsTargetInfo { 7916 public: 7917 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7918 : MipsTargetInfo(Triple, Opts) {} 7919 7920 BuiltinVaListKind getBuiltinVaListKind() const override { 7921 return TargetInfo::PNaClABIBuiltinVaList; 7922 } 7923 }; 7924 7925 class Le64TargetInfo : public TargetInfo { 7926 static const Builtin::Info BuiltinInfo[]; 7927 7928 public: 7929 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7930 : TargetInfo(Triple) { 7931 NoAsmVariants = true; 7932 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7933 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7934 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 7935 } 7936 7937 void getTargetDefines(const LangOptions &Opts, 7938 MacroBuilder &Builder) const override { 7939 DefineStd(Builder, "unix", Opts); 7940 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7941 Builder.defineMacro("__ELF__"); 7942 } 7943 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7944 return llvm::makeArrayRef(BuiltinInfo, 7945 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7946 } 7947 BuiltinVaListKind getBuiltinVaListKind() const override { 7948 return TargetInfo::PNaClABIBuiltinVaList; 7949 } 7950 const char *getClobbers() const override { return ""; } 7951 ArrayRef<const char *> getGCCRegNames() const override { 7952 return None; 7953 } 7954 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7955 return None; 7956 } 7957 bool validateAsmConstraint(const char *&Name, 7958 TargetInfo::ConstraintInfo &Info) const override { 7959 return false; 7960 } 7961 7962 bool hasProtectedVisibility() const override { return false; } 7963 }; 7964 7965 class WebAssemblyTargetInfo : public TargetInfo { 7966 static const Builtin::Info BuiltinInfo[]; 7967 7968 enum SIMDEnum { 7969 NoSIMD, 7970 SIMD128, 7971 } SIMDLevel; 7972 7973 public: 7974 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 7975 : TargetInfo(T), SIMDLevel(NoSIMD) { 7976 NoAsmVariants = true; 7977 SuitableAlign = 128; 7978 LargeArrayMinWidth = 128; 7979 LargeArrayAlign = 128; 7980 SimdDefaultAlign = 128; 7981 SigAtomicType = SignedLong; 7982 LongDoubleWidth = LongDoubleAlign = 128; 7983 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7984 SizeType = UnsignedInt; 7985 PtrDiffType = SignedInt; 7986 IntPtrType = SignedInt; 7987 } 7988 7989 protected: 7990 void getTargetDefines(const LangOptions &Opts, 7991 MacroBuilder &Builder) const override { 7992 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7993 if (SIMDLevel >= SIMD128) 7994 Builder.defineMacro("__wasm_simd128__"); 7995 } 7996 7997 private: 7998 bool 7999 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 8000 StringRef CPU, 8001 const std::vector<std::string> &FeaturesVec) const override { 8002 if (CPU == "bleeding-edge") 8003 Features["simd128"] = true; 8004 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 8005 } 8006 bool hasFeature(StringRef Feature) const final { 8007 return llvm::StringSwitch<bool>(Feature) 8008 .Case("simd128", SIMDLevel >= SIMD128) 8009 .Default(false); 8010 } 8011 bool handleTargetFeatures(std::vector<std::string> &Features, 8012 DiagnosticsEngine &Diags) final { 8013 for (const auto &Feature : Features) { 8014 if (Feature == "+simd128") { 8015 SIMDLevel = std::max(SIMDLevel, SIMD128); 8016 continue; 8017 } 8018 if (Feature == "-simd128") { 8019 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 8020 continue; 8021 } 8022 8023 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 8024 << "-target-feature"; 8025 return false; 8026 } 8027 return true; 8028 } 8029 bool setCPU(const std::string &Name) final { 8030 return llvm::StringSwitch<bool>(Name) 8031 .Case("mvp", true) 8032 .Case("bleeding-edge", true) 8033 .Case("generic", true) 8034 .Default(false); 8035 } 8036 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 8037 return llvm::makeArrayRef(BuiltinInfo, 8038 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 8039 } 8040 BuiltinVaListKind getBuiltinVaListKind() const final { 8041 return VoidPtrBuiltinVaList; 8042 } 8043 ArrayRef<const char *> getGCCRegNames() const final { 8044 return None; 8045 } 8046 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 8047 return None; 8048 } 8049 bool 8050 validateAsmConstraint(const char *&Name, 8051 TargetInfo::ConstraintInfo &Info) const final { 8052 return false; 8053 } 8054 const char *getClobbers() const final { return ""; } 8055 bool isCLZForZeroUndef() const final { return false; } 8056 bool hasInt128Type() const final { return true; } 8057 IntType getIntTypeByWidth(unsigned BitWidth, 8058 bool IsSigned) const final { 8059 // WebAssembly prefers long long for explicitly 64-bit integers. 8060 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8061 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8062 } 8063 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8064 bool IsSigned) const final { 8065 // WebAssembly uses long long for int_least64_t and int_fast64_t. 8066 return BitWidth == 64 8067 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8068 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 8069 } 8070 }; 8071 8072 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 8073 #define BUILTIN(ID, TYPE, ATTRS) \ 8074 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8075 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8076 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8077 #include "clang/Basic/BuiltinsWebAssembly.def" 8078 }; 8079 8080 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 8081 public: 8082 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 8083 const TargetOptions &Opts) 8084 : WebAssemblyTargetInfo(T, Opts) { 8085 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 8086 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 8087 } 8088 8089 protected: 8090 void getTargetDefines(const LangOptions &Opts, 8091 MacroBuilder &Builder) const override { 8092 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8093 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 8094 } 8095 }; 8096 8097 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 8098 public: 8099 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 8100 const TargetOptions &Opts) 8101 : WebAssemblyTargetInfo(T, Opts) { 8102 LongAlign = LongWidth = 64; 8103 PointerAlign = PointerWidth = 64; 8104 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8105 SizeType = UnsignedLong; 8106 PtrDiffType = SignedLong; 8107 IntPtrType = SignedLong; 8108 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 8109 } 8110 8111 protected: 8112 void getTargetDefines(const LangOptions &Opts, 8113 MacroBuilder &Builder) const override { 8114 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8115 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 8116 } 8117 }; 8118 8119 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 8120 #define BUILTIN(ID, TYPE, ATTRS) \ 8121 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8122 #include "clang/Basic/BuiltinsLe64.def" 8123 }; 8124 8125 static const unsigned SPIRAddrSpaceMap[] = { 8126 1, // opencl_global 8127 3, // opencl_local 8128 2, // opencl_constant 8129 4, // opencl_generic 8130 0, // cuda_device 8131 0, // cuda_constant 8132 0 // cuda_shared 8133 }; 8134 class SPIRTargetInfo : public TargetInfo { 8135 public: 8136 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8137 : TargetInfo(Triple) { 8138 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 8139 "SPIR target must use unknown OS"); 8140 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 8141 "SPIR target must use unknown environment type"); 8142 TLSSupported = false; 8143 LongWidth = LongAlign = 64; 8144 AddrSpaceMap = &SPIRAddrSpaceMap; 8145 UseAddrSpaceMapMangling = true; 8146 // Define available target features 8147 // These must be defined in sorted order! 8148 NoAsmVariants = true; 8149 } 8150 void getTargetDefines(const LangOptions &Opts, 8151 MacroBuilder &Builder) const override { 8152 DefineStd(Builder, "SPIR", Opts); 8153 } 8154 bool hasFeature(StringRef Feature) const override { 8155 return Feature == "spir"; 8156 } 8157 8158 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8159 const char *getClobbers() const override { return ""; } 8160 ArrayRef<const char *> getGCCRegNames() const override { return None; } 8161 bool validateAsmConstraint(const char *&Name, 8162 TargetInfo::ConstraintInfo &info) const override { 8163 return true; 8164 } 8165 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8166 return None; 8167 } 8168 BuiltinVaListKind getBuiltinVaListKind() const override { 8169 return TargetInfo::VoidPtrBuiltinVaList; 8170 } 8171 8172 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 8173 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 8174 : CCCR_Warning; 8175 } 8176 8177 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8178 return CC_SpirFunction; 8179 } 8180 8181 void setSupportedOpenCLOpts() override { 8182 // Assume all OpenCL extensions and optional core features are supported 8183 // for SPIR since it is a generic target. 8184 getSupportedOpenCLOpts().setAll(); 8185 } 8186 }; 8187 8188 class SPIR32TargetInfo : public SPIRTargetInfo { 8189 public: 8190 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8191 : SPIRTargetInfo(Triple, Opts) { 8192 PointerWidth = PointerAlign = 32; 8193 SizeType = TargetInfo::UnsignedInt; 8194 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8195 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8196 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8197 } 8198 void getTargetDefines(const LangOptions &Opts, 8199 MacroBuilder &Builder) const override { 8200 DefineStd(Builder, "SPIR32", Opts); 8201 } 8202 }; 8203 8204 class SPIR64TargetInfo : public SPIRTargetInfo { 8205 public: 8206 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8207 : SPIRTargetInfo(Triple, Opts) { 8208 PointerWidth = PointerAlign = 64; 8209 SizeType = TargetInfo::UnsignedLong; 8210 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8211 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8212 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8213 } 8214 void getTargetDefines(const LangOptions &Opts, 8215 MacroBuilder &Builder) const override { 8216 DefineStd(Builder, "SPIR64", Opts); 8217 } 8218 }; 8219 8220 class XCoreTargetInfo : public TargetInfo { 8221 static const Builtin::Info BuiltinInfo[]; 8222 public: 8223 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8224 : TargetInfo(Triple) { 8225 NoAsmVariants = true; 8226 LongLongAlign = 32; 8227 SuitableAlign = 32; 8228 DoubleAlign = LongDoubleAlign = 32; 8229 SizeType = UnsignedInt; 8230 PtrDiffType = SignedInt; 8231 IntPtrType = SignedInt; 8232 WCharType = UnsignedChar; 8233 WIntType = UnsignedInt; 8234 UseZeroLengthBitfieldAlignment = true; 8235 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8236 "-f64:32-a:0:32-n32"); 8237 } 8238 void getTargetDefines(const LangOptions &Opts, 8239 MacroBuilder &Builder) const override { 8240 Builder.defineMacro("__XS1B__"); 8241 } 8242 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8243 return llvm::makeArrayRef(BuiltinInfo, 8244 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8245 } 8246 BuiltinVaListKind getBuiltinVaListKind() const override { 8247 return TargetInfo::VoidPtrBuiltinVaList; 8248 } 8249 const char *getClobbers() const override { 8250 return ""; 8251 } 8252 ArrayRef<const char *> getGCCRegNames() const override { 8253 static const char * const GCCRegNames[] = { 8254 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8255 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8256 }; 8257 return llvm::makeArrayRef(GCCRegNames); 8258 } 8259 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8260 return None; 8261 } 8262 bool validateAsmConstraint(const char *&Name, 8263 TargetInfo::ConstraintInfo &Info) const override { 8264 return false; 8265 } 8266 int getEHDataRegisterNumber(unsigned RegNo) const override { 8267 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8268 return (RegNo < 2)? RegNo : -1; 8269 } 8270 bool allowsLargerPreferedTypeAlignment() const override { 8271 return false; 8272 } 8273 }; 8274 8275 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8276 #define BUILTIN(ID, TYPE, ATTRS) \ 8277 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8278 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8279 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8280 #include "clang/Basic/BuiltinsXCore.def" 8281 }; 8282 8283 // x86_32 Android target 8284 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8285 public: 8286 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8287 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8288 SuitableAlign = 32; 8289 LongDoubleWidth = 64; 8290 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 8291 } 8292 }; 8293 8294 // x86_64 Android target 8295 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8296 public: 8297 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8298 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8299 LongDoubleFormat = &llvm::APFloat::IEEEquad; 8300 } 8301 8302 bool useFloat128ManglingForLongDouble() const override { 8303 return true; 8304 } 8305 }; 8306 8307 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8308 class RenderScript32TargetInfo : public ARMleTargetInfo { 8309 public: 8310 RenderScript32TargetInfo(const llvm::Triple &Triple, 8311 const TargetOptions &Opts) 8312 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8313 Triple.getOSName(), 8314 Triple.getEnvironmentName()), 8315 Opts) { 8316 IsRenderScriptTarget = true; 8317 LongWidth = LongAlign = 64; 8318 } 8319 void getTargetDefines(const LangOptions &Opts, 8320 MacroBuilder &Builder) const override { 8321 Builder.defineMacro("__RENDERSCRIPT__"); 8322 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8323 } 8324 }; 8325 8326 // 64-bit RenderScript is aarch64 8327 class RenderScript64TargetInfo : public AArch64leTargetInfo { 8328 public: 8329 RenderScript64TargetInfo(const llvm::Triple &Triple, 8330 const TargetOptions &Opts) 8331 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 8332 Triple.getOSName(), 8333 Triple.getEnvironmentName()), 8334 Opts) { 8335 IsRenderScriptTarget = true; 8336 } 8337 8338 void getTargetDefines(const LangOptions &Opts, 8339 MacroBuilder &Builder) const override { 8340 Builder.defineMacro("__RENDERSCRIPT__"); 8341 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 8342 } 8343 }; 8344 8345 } // end anonymous namespace 8346 8347 //===----------------------------------------------------------------------===// 8348 // Driver code 8349 //===----------------------------------------------------------------------===// 8350 8351 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 8352 const TargetOptions &Opts) { 8353 llvm::Triple::OSType os = Triple.getOS(); 8354 8355 switch (Triple.getArch()) { 8356 default: 8357 return nullptr; 8358 8359 case llvm::Triple::xcore: 8360 return new XCoreTargetInfo(Triple, Opts); 8361 8362 case llvm::Triple::hexagon: 8363 return new HexagonTargetInfo(Triple, Opts); 8364 8365 case llvm::Triple::lanai: 8366 return new LanaiTargetInfo(Triple, Opts); 8367 8368 case llvm::Triple::aarch64: 8369 if (Triple.isOSDarwin()) 8370 return new DarwinAArch64TargetInfo(Triple, Opts); 8371 8372 switch (os) { 8373 case llvm::Triple::CloudABI: 8374 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 8375 case llvm::Triple::FreeBSD: 8376 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8377 case llvm::Triple::Fuchsia: 8378 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8379 case llvm::Triple::Linux: 8380 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8381 case llvm::Triple::NetBSD: 8382 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8383 default: 8384 return new AArch64leTargetInfo(Triple, Opts); 8385 } 8386 8387 case llvm::Triple::aarch64_be: 8388 switch (os) { 8389 case llvm::Triple::FreeBSD: 8390 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8391 case llvm::Triple::Fuchsia: 8392 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8393 case llvm::Triple::Linux: 8394 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8395 case llvm::Triple::NetBSD: 8396 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8397 default: 8398 return new AArch64beTargetInfo(Triple, Opts); 8399 } 8400 8401 case llvm::Triple::arm: 8402 case llvm::Triple::thumb: 8403 if (Triple.isOSBinFormatMachO()) 8404 return new DarwinARMTargetInfo(Triple, Opts); 8405 8406 switch (os) { 8407 case llvm::Triple::CloudABI: 8408 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts); 8409 case llvm::Triple::Linux: 8410 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 8411 case llvm::Triple::FreeBSD: 8412 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8413 case llvm::Triple::Fuchsia: 8414 return new FuchsiaTargetInfo<ARMleTargetInfo>(Triple, Opts); 8415 case llvm::Triple::NetBSD: 8416 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8417 case llvm::Triple::OpenBSD: 8418 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8419 case llvm::Triple::Bitrig: 8420 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 8421 case llvm::Triple::RTEMS: 8422 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 8423 case llvm::Triple::NaCl: 8424 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 8425 case llvm::Triple::Win32: 8426 switch (Triple.getEnvironment()) { 8427 case llvm::Triple::Cygnus: 8428 return new CygwinARMTargetInfo(Triple, Opts); 8429 case llvm::Triple::GNU: 8430 return new MinGWARMTargetInfo(Triple, Opts); 8431 case llvm::Triple::Itanium: 8432 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 8433 case llvm::Triple::MSVC: 8434 default: // Assume MSVC for unknown environments 8435 return new MicrosoftARMleTargetInfo(Triple, Opts); 8436 } 8437 default: 8438 return new ARMleTargetInfo(Triple, Opts); 8439 } 8440 8441 case llvm::Triple::armeb: 8442 case llvm::Triple::thumbeb: 8443 if (Triple.isOSDarwin()) 8444 return new DarwinARMTargetInfo(Triple, Opts); 8445 8446 switch (os) { 8447 case llvm::Triple::Linux: 8448 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8449 case llvm::Triple::FreeBSD: 8450 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8451 case llvm::Triple::Fuchsia: 8452 return new FuchsiaTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8453 case llvm::Triple::NetBSD: 8454 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8455 case llvm::Triple::OpenBSD: 8456 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8457 case llvm::Triple::Bitrig: 8458 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8459 case llvm::Triple::RTEMS: 8460 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8461 case llvm::Triple::NaCl: 8462 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8463 default: 8464 return new ARMbeTargetInfo(Triple, Opts); 8465 } 8466 8467 case llvm::Triple::bpfeb: 8468 case llvm::Triple::bpfel: 8469 return new BPFTargetInfo(Triple, Opts); 8470 8471 case llvm::Triple::msp430: 8472 return new MSP430TargetInfo(Triple, Opts); 8473 8474 case llvm::Triple::mips: 8475 switch (os) { 8476 case llvm::Triple::Linux: 8477 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8478 case llvm::Triple::RTEMS: 8479 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8480 case llvm::Triple::FreeBSD: 8481 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8482 case llvm::Triple::NetBSD: 8483 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8484 default: 8485 return new MipsTargetInfo(Triple, Opts); 8486 } 8487 8488 case llvm::Triple::mipsel: 8489 switch (os) { 8490 case llvm::Triple::Linux: 8491 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8492 case llvm::Triple::RTEMS: 8493 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8494 case llvm::Triple::FreeBSD: 8495 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8496 case llvm::Triple::NetBSD: 8497 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8498 case llvm::Triple::NaCl: 8499 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 8500 default: 8501 return new MipsTargetInfo(Triple, Opts); 8502 } 8503 8504 case llvm::Triple::mips64: 8505 switch (os) { 8506 case llvm::Triple::Linux: 8507 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8508 case llvm::Triple::RTEMS: 8509 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8510 case llvm::Triple::FreeBSD: 8511 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8512 case llvm::Triple::NetBSD: 8513 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8514 case llvm::Triple::OpenBSD: 8515 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8516 default: 8517 return new MipsTargetInfo(Triple, Opts); 8518 } 8519 8520 case llvm::Triple::mips64el: 8521 switch (os) { 8522 case llvm::Triple::Linux: 8523 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8524 case llvm::Triple::RTEMS: 8525 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8526 case llvm::Triple::FreeBSD: 8527 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8528 case llvm::Triple::NetBSD: 8529 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8530 case llvm::Triple::OpenBSD: 8531 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8532 default: 8533 return new MipsTargetInfo(Triple, Opts); 8534 } 8535 8536 case llvm::Triple::le32: 8537 switch (os) { 8538 case llvm::Triple::NaCl: 8539 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 8540 default: 8541 return nullptr; 8542 } 8543 8544 case llvm::Triple::le64: 8545 return new Le64TargetInfo(Triple, Opts); 8546 8547 case llvm::Triple::ppc: 8548 if (Triple.isOSDarwin()) 8549 return new DarwinPPC32TargetInfo(Triple, Opts); 8550 switch (os) { 8551 case llvm::Triple::Linux: 8552 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 8553 case llvm::Triple::FreeBSD: 8554 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8555 case llvm::Triple::NetBSD: 8556 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8557 case llvm::Triple::OpenBSD: 8558 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8559 case llvm::Triple::RTEMS: 8560 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 8561 default: 8562 return new PPC32TargetInfo(Triple, Opts); 8563 } 8564 8565 case llvm::Triple::ppc64: 8566 if (Triple.isOSDarwin()) 8567 return new DarwinPPC64TargetInfo(Triple, Opts); 8568 switch (os) { 8569 case llvm::Triple::Linux: 8570 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8571 case llvm::Triple::Lv2: 8572 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 8573 case llvm::Triple::FreeBSD: 8574 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8575 case llvm::Triple::NetBSD: 8576 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8577 default: 8578 return new PPC64TargetInfo(Triple, Opts); 8579 } 8580 8581 case llvm::Triple::ppc64le: 8582 switch (os) { 8583 case llvm::Triple::Linux: 8584 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8585 case llvm::Triple::NetBSD: 8586 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8587 default: 8588 return new PPC64TargetInfo(Triple, Opts); 8589 } 8590 8591 case llvm::Triple::nvptx: 8592 return new NVPTX32TargetInfo(Triple, Opts); 8593 case llvm::Triple::nvptx64: 8594 return new NVPTX64TargetInfo(Triple, Opts); 8595 8596 case llvm::Triple::amdgcn: 8597 case llvm::Triple::r600: 8598 return new AMDGPUTargetInfo(Triple, Opts); 8599 8600 case llvm::Triple::sparc: 8601 switch (os) { 8602 case llvm::Triple::Linux: 8603 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8604 case llvm::Triple::Solaris: 8605 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8606 case llvm::Triple::NetBSD: 8607 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8608 case llvm::Triple::OpenBSD: 8609 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8610 case llvm::Triple::RTEMS: 8611 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8612 default: 8613 return new SparcV8TargetInfo(Triple, Opts); 8614 } 8615 8616 // The 'sparcel' architecture copies all the above cases except for Solaris. 8617 case llvm::Triple::sparcel: 8618 switch (os) { 8619 case llvm::Triple::Linux: 8620 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8621 case llvm::Triple::NetBSD: 8622 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8623 case llvm::Triple::OpenBSD: 8624 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8625 case llvm::Triple::RTEMS: 8626 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8627 default: 8628 return new SparcV8elTargetInfo(Triple, Opts); 8629 } 8630 8631 case llvm::Triple::sparcv9: 8632 switch (os) { 8633 case llvm::Triple::Linux: 8634 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8635 case llvm::Triple::Solaris: 8636 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8637 case llvm::Triple::NetBSD: 8638 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8639 case llvm::Triple::OpenBSD: 8640 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8641 case llvm::Triple::FreeBSD: 8642 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8643 default: 8644 return new SparcV9TargetInfo(Triple, Opts); 8645 } 8646 8647 case llvm::Triple::systemz: 8648 switch (os) { 8649 case llvm::Triple::Linux: 8650 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 8651 default: 8652 return new SystemZTargetInfo(Triple, Opts); 8653 } 8654 8655 case llvm::Triple::tce: 8656 return new TCETargetInfo(Triple, Opts); 8657 8658 case llvm::Triple::tcele: 8659 return new TCELETargetInfo(Triple, Opts); 8660 8661 case llvm::Triple::x86: 8662 if (Triple.isOSDarwin()) 8663 return new DarwinI386TargetInfo(Triple, Opts); 8664 8665 switch (os) { 8666 case llvm::Triple::CloudABI: 8667 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 8668 case llvm::Triple::Linux: { 8669 switch (Triple.getEnvironment()) { 8670 default: 8671 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 8672 case llvm::Triple::Android: 8673 return new AndroidX86_32TargetInfo(Triple, Opts); 8674 } 8675 } 8676 case llvm::Triple::DragonFly: 8677 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8678 case llvm::Triple::NetBSD: 8679 return new NetBSDI386TargetInfo(Triple, Opts); 8680 case llvm::Triple::OpenBSD: 8681 return new OpenBSDI386TargetInfo(Triple, Opts); 8682 case llvm::Triple::Bitrig: 8683 return new BitrigI386TargetInfo(Triple, Opts); 8684 case llvm::Triple::FreeBSD: 8685 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8686 case llvm::Triple::Fuchsia: 8687 return new FuchsiaTargetInfo<X86_32TargetInfo>(Triple, Opts); 8688 case llvm::Triple::KFreeBSD: 8689 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8690 case llvm::Triple::Minix: 8691 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 8692 case llvm::Triple::Solaris: 8693 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 8694 case llvm::Triple::Win32: { 8695 switch (Triple.getEnvironment()) { 8696 case llvm::Triple::Cygnus: 8697 return new CygwinX86_32TargetInfo(Triple, Opts); 8698 case llvm::Triple::GNU: 8699 return new MinGWX86_32TargetInfo(Triple, Opts); 8700 case llvm::Triple::Itanium: 8701 case llvm::Triple::MSVC: 8702 default: // Assume MSVC for unknown environments 8703 return new MicrosoftX86_32TargetInfo(Triple, Opts); 8704 } 8705 } 8706 case llvm::Triple::Haiku: 8707 return new HaikuX86_32TargetInfo(Triple, Opts); 8708 case llvm::Triple::RTEMS: 8709 return new RTEMSX86_32TargetInfo(Triple, Opts); 8710 case llvm::Triple::NaCl: 8711 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 8712 case llvm::Triple::ELFIAMCU: 8713 return new MCUX86_32TargetInfo(Triple, Opts); 8714 default: 8715 return new X86_32TargetInfo(Triple, Opts); 8716 } 8717 8718 case llvm::Triple::x86_64: 8719 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 8720 return new DarwinX86_64TargetInfo(Triple, Opts); 8721 8722 switch (os) { 8723 case llvm::Triple::CloudABI: 8724 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 8725 case llvm::Triple::Linux: { 8726 switch (Triple.getEnvironment()) { 8727 default: 8728 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 8729 case llvm::Triple::Android: 8730 return new AndroidX86_64TargetInfo(Triple, Opts); 8731 } 8732 } 8733 case llvm::Triple::DragonFly: 8734 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8735 case llvm::Triple::NetBSD: 8736 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8737 case llvm::Triple::OpenBSD: 8738 return new OpenBSDX86_64TargetInfo(Triple, Opts); 8739 case llvm::Triple::Bitrig: 8740 return new BitrigX86_64TargetInfo(Triple, Opts); 8741 case llvm::Triple::FreeBSD: 8742 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8743 case llvm::Triple::Fuchsia: 8744 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts); 8745 case llvm::Triple::KFreeBSD: 8746 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8747 case llvm::Triple::Solaris: 8748 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 8749 case llvm::Triple::Win32: { 8750 switch (Triple.getEnvironment()) { 8751 case llvm::Triple::Cygnus: 8752 return new CygwinX86_64TargetInfo(Triple, Opts); 8753 case llvm::Triple::GNU: 8754 return new MinGWX86_64TargetInfo(Triple, Opts); 8755 case llvm::Triple::MSVC: 8756 default: // Assume MSVC for unknown environments 8757 return new MicrosoftX86_64TargetInfo(Triple, Opts); 8758 } 8759 } 8760 case llvm::Triple::Haiku: 8761 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 8762 case llvm::Triple::NaCl: 8763 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 8764 case llvm::Triple::PS4: 8765 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 8766 default: 8767 return new X86_64TargetInfo(Triple, Opts); 8768 } 8769 8770 case llvm::Triple::spir: { 8771 if (Triple.getOS() != llvm::Triple::UnknownOS || 8772 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8773 return nullptr; 8774 return new SPIR32TargetInfo(Triple, Opts); 8775 } 8776 case llvm::Triple::spir64: { 8777 if (Triple.getOS() != llvm::Triple::UnknownOS || 8778 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8779 return nullptr; 8780 return new SPIR64TargetInfo(Triple, Opts); 8781 } 8782 case llvm::Triple::wasm32: 8783 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8784 return nullptr; 8785 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 8786 case llvm::Triple::wasm64: 8787 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8788 return nullptr; 8789 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 8790 8791 case llvm::Triple::renderscript32: 8792 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 8793 case llvm::Triple::renderscript64: 8794 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 8795 } 8796 } 8797 8798 /// CreateTargetInfo - Return the target info object for the specified target 8799 /// options. 8800 TargetInfo * 8801 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8802 const std::shared_ptr<TargetOptions> &Opts) { 8803 llvm::Triple Triple(Opts->Triple); 8804 8805 // Construct the target 8806 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 8807 if (!Target) { 8808 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8809 return nullptr; 8810 } 8811 Target->TargetOpts = Opts; 8812 8813 // Set the target CPU if specified. 8814 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8815 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8816 return nullptr; 8817 } 8818 8819 // Set the target ABI if specified. 8820 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8821 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8822 return nullptr; 8823 } 8824 8825 // Set the fp math unit. 8826 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8827 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8828 return nullptr; 8829 } 8830 8831 // Compute the default target features, we need the target to handle this 8832 // because features may have dependencies on one another. 8833 llvm::StringMap<bool> Features; 8834 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8835 Opts->FeaturesAsWritten)) 8836 return nullptr; 8837 8838 // Add the features to the compile options. 8839 Opts->Features.clear(); 8840 for (const auto &F : Features) 8841 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8842 8843 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8844 return nullptr; 8845 8846 Target->setSupportedOpenCLOpts(); 8847 Target->setOpenCLExtensionOpts(); 8848 8849 if (!Target->validateTarget(Diags)) 8850 return nullptr; 8851 8852 return Target.release(); 8853 } 8854