1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "clang/Basic/Version.h" 23 #include "llvm/ADT/APFloat.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringExtras.h" 26 #include "llvm/ADT/StringRef.h" 27 #include "llvm/ADT/StringSwitch.h" 28 #include "llvm/ADT/Triple.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/TargetParser.h" 32 #include <algorithm> 33 #include <memory> 34 35 using namespace clang; 36 37 //===----------------------------------------------------------------------===// 38 // Common code shared among targets. 39 //===----------------------------------------------------------------------===// 40 41 /// DefineStd - Define a macro name and standard variants. For example if 42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 43 /// when in GNU mode. 44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 45 const LangOptions &Opts) { 46 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 47 48 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 49 // in the user's namespace. 50 if (Opts.GNUMode) 51 Builder.defineMacro(MacroName); 52 53 // Define __unix. 54 Builder.defineMacro("__" + MacroName); 55 56 // Define __unix__. 57 Builder.defineMacro("__" + MacroName + "__"); 58 } 59 60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 61 bool Tuning = true) { 62 Builder.defineMacro("__" + CPUName); 63 Builder.defineMacro("__" + CPUName + "__"); 64 if (Tuning) 65 Builder.defineMacro("__tune_" + CPUName + "__"); 66 } 67 68 //===----------------------------------------------------------------------===// 69 // Defines specific to certain operating systems. 70 //===----------------------------------------------------------------------===// 71 72 namespace { 73 template<typename TgtInfo> 74 class OSTargetInfo : public TgtInfo { 75 protected: 76 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 77 MacroBuilder &Builder) const=0; 78 public: 79 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 80 void getTargetDefines(const LangOptions &Opts, 81 MacroBuilder &Builder) const override { 82 TgtInfo::getTargetDefines(Opts, Builder); 83 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 84 } 85 86 }; 87 88 // CloudABI Target 89 template <typename Target> 90 class CloudABITargetInfo : public OSTargetInfo<Target> { 91 protected: 92 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 93 MacroBuilder &Builder) const override { 94 Builder.defineMacro("__CloudABI__"); 95 Builder.defineMacro("__ELF__"); 96 97 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 98 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 99 Builder.defineMacro("__STDC_UTF_16__"); 100 Builder.defineMacro("__STDC_UTF_32__"); 101 } 102 103 public: 104 CloudABITargetInfo(const llvm::Triple &Triple) 105 : OSTargetInfo<Target>(Triple) {} 106 }; 107 108 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 109 const llvm::Triple &Triple, 110 StringRef &PlatformName, 111 VersionTuple &PlatformMinVersion) { 112 Builder.defineMacro("__APPLE_CC__", "6000"); 113 Builder.defineMacro("__APPLE__"); 114 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 115 // AddressSanitizer doesn't play well with source fortification, which is on 116 // by default on Darwin. 117 if (Opts.Sanitize.has(SanitizerKind::Address)) 118 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 119 120 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 121 if (!Opts.ObjC1) { 122 // __weak is always defined, for use in blocks and with objc pointers. 123 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 124 Builder.defineMacro("__strong", ""); 125 Builder.defineMacro("__unsafe_unretained", ""); 126 } 127 128 if (Opts.Static) 129 Builder.defineMacro("__STATIC__"); 130 else 131 Builder.defineMacro("__DYNAMIC__"); 132 133 if (Opts.POSIXThreads) 134 Builder.defineMacro("_REENTRANT"); 135 136 // Get the platform type and version number from the triple. 137 unsigned Maj, Min, Rev; 138 if (Triple.isMacOSX()) { 139 Triple.getMacOSXVersion(Maj, Min, Rev); 140 PlatformName = "macosx"; 141 } else { 142 Triple.getOSVersion(Maj, Min, Rev); 143 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 144 } 145 146 // If -target arch-pc-win32-macho option specified, we're 147 // generating code for Win32 ABI. No need to emit 148 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 149 if (PlatformName == "win32") { 150 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 151 return; 152 } 153 154 // Set the appropriate OS version define. 155 if (Triple.isiOS()) { 156 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 157 char Str[6]; 158 Str[0] = '0' + Maj; 159 Str[1] = '0' + (Min / 10); 160 Str[2] = '0' + (Min % 10); 161 Str[3] = '0' + (Rev / 10); 162 Str[4] = '0' + (Rev % 10); 163 Str[5] = '\0'; 164 if (Triple.isTvOS()) 165 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 166 else 167 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 168 Str); 169 170 } else if (Triple.isWatchOS()) { 171 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 172 char Str[6]; 173 Str[0] = '0' + Maj; 174 Str[1] = '0' + (Min / 10); 175 Str[2] = '0' + (Min % 10); 176 Str[3] = '0' + (Rev / 10); 177 Str[4] = '0' + (Rev % 10); 178 Str[5] = '\0'; 179 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 180 } else if (Triple.isMacOSX()) { 181 // Note that the Driver allows versions which aren't representable in the 182 // define (because we only get a single digit for the minor and micro 183 // revision numbers). So, we limit them to the maximum representable 184 // version. 185 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 186 char Str[7]; 187 if (Maj < 10 || (Maj == 10 && Min < 10)) { 188 Str[0] = '0' + (Maj / 10); 189 Str[1] = '0' + (Maj % 10); 190 Str[2] = '0' + std::min(Min, 9U); 191 Str[3] = '0' + std::min(Rev, 9U); 192 Str[4] = '\0'; 193 } else { 194 // Handle versions > 10.9. 195 Str[0] = '0' + (Maj / 10); 196 Str[1] = '0' + (Maj % 10); 197 Str[2] = '0' + (Min / 10); 198 Str[3] = '0' + (Min % 10); 199 Str[4] = '0' + (Rev / 10); 200 Str[5] = '0' + (Rev % 10); 201 Str[6] = '\0'; 202 } 203 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 204 } 205 206 // Tell users about the kernel if there is one. 207 if (Triple.isOSDarwin()) 208 Builder.defineMacro("__MACH__"); 209 210 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 211 } 212 213 template<typename Target> 214 class DarwinTargetInfo : public OSTargetInfo<Target> { 215 protected: 216 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 217 MacroBuilder &Builder) const override { 218 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 219 this->PlatformMinVersion); 220 } 221 222 public: 223 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 224 // By default, no TLS, and we whitelist permitted architecture/OS 225 // combinations. 226 this->TLSSupported = false; 227 228 if (Triple.isMacOSX()) 229 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 230 else if (Triple.isiOS()) { 231 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 232 if (Triple.getArch() == llvm::Triple::x86_64 || 233 Triple.getArch() == llvm::Triple::aarch64) 234 this->TLSSupported = !Triple.isOSVersionLT(8); 235 else if (Triple.getArch() == llvm::Triple::x86 || 236 Triple.getArch() == llvm::Triple::arm || 237 Triple.getArch() == llvm::Triple::thumb) 238 this->TLSSupported = !Triple.isOSVersionLT(9); 239 } else if (Triple.isWatchOS()) 240 this->TLSSupported = !Triple.isOSVersionLT(2); 241 242 this->MCountName = "\01mcount"; 243 } 244 245 std::string isValidSectionSpecifier(StringRef SR) const override { 246 // Let MCSectionMachO validate this. 247 StringRef Segment, Section; 248 unsigned TAA, StubSize; 249 bool HasTAA; 250 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 251 TAA, HasTAA, StubSize); 252 } 253 254 const char *getStaticInitSectionSpecifier() const override { 255 // FIXME: We should return 0 when building kexts. 256 return "__TEXT,__StaticInit,regular,pure_instructions"; 257 } 258 259 /// Darwin does not support protected visibility. Darwin's "default" 260 /// is very similar to ELF's "protected"; Darwin requires a "weak" 261 /// attribute on declarations that can be dynamically replaced. 262 bool hasProtectedVisibility() const override { 263 return false; 264 } 265 }; 266 267 268 // DragonFlyBSD Target 269 template<typename Target> 270 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 271 protected: 272 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 273 MacroBuilder &Builder) const override { 274 // DragonFly defines; list based off of gcc output 275 Builder.defineMacro("__DragonFly__"); 276 Builder.defineMacro("__DragonFly_cc_version", "100001"); 277 Builder.defineMacro("__ELF__"); 278 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 279 Builder.defineMacro("__tune_i386__"); 280 DefineStd(Builder, "unix", Opts); 281 } 282 public: 283 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 284 : OSTargetInfo<Target>(Triple) { 285 switch (Triple.getArch()) { 286 default: 287 case llvm::Triple::x86: 288 case llvm::Triple::x86_64: 289 this->MCountName = ".mcount"; 290 break; 291 } 292 } 293 }; 294 295 // FreeBSD Target 296 template<typename Target> 297 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 298 protected: 299 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 300 MacroBuilder &Builder) const override { 301 // FreeBSD defines; list based off of gcc output 302 303 unsigned Release = Triple.getOSMajorVersion(); 304 if (Release == 0U) 305 Release = 8; 306 307 Builder.defineMacro("__FreeBSD__", Twine(Release)); 308 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 309 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 310 DefineStd(Builder, "unix", Opts); 311 Builder.defineMacro("__ELF__"); 312 313 // On FreeBSD, wchar_t contains the number of the code point as 314 // used by the character set of the locale. These character sets are 315 // not necessarily a superset of ASCII. 316 // 317 // FIXME: This is wrong; the macro refers to the numerical values 318 // of wchar_t *literals*, which are not locale-dependent. However, 319 // FreeBSD systems apparently depend on us getting this wrong, and 320 // setting this to 1 is conforming even if all the basic source 321 // character literals have the same encoding as char and wchar_t. 322 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 323 } 324 public: 325 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 326 switch (Triple.getArch()) { 327 default: 328 case llvm::Triple::x86: 329 case llvm::Triple::x86_64: 330 this->MCountName = ".mcount"; 331 break; 332 case llvm::Triple::mips: 333 case llvm::Triple::mipsel: 334 case llvm::Triple::ppc: 335 case llvm::Triple::ppc64: 336 case llvm::Triple::ppc64le: 337 this->MCountName = "_mcount"; 338 break; 339 case llvm::Triple::arm: 340 this->MCountName = "__mcount"; 341 break; 342 } 343 } 344 }; 345 346 // GNU/kFreeBSD Target 347 template<typename Target> 348 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 349 protected: 350 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 351 MacroBuilder &Builder) const override { 352 // GNU/kFreeBSD defines; list based off of gcc output 353 354 DefineStd(Builder, "unix", Opts); 355 Builder.defineMacro("__FreeBSD_kernel__"); 356 Builder.defineMacro("__GLIBC__"); 357 Builder.defineMacro("__ELF__"); 358 if (Opts.POSIXThreads) 359 Builder.defineMacro("_REENTRANT"); 360 if (Opts.CPlusPlus) 361 Builder.defineMacro("_GNU_SOURCE"); 362 } 363 public: 364 KFreeBSDTargetInfo(const llvm::Triple &Triple) 365 : OSTargetInfo<Target>(Triple) {} 366 }; 367 368 // Minix Target 369 template<typename Target> 370 class MinixTargetInfo : public OSTargetInfo<Target> { 371 protected: 372 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 373 MacroBuilder &Builder) const override { 374 // Minix defines 375 376 Builder.defineMacro("__minix", "3"); 377 Builder.defineMacro("_EM_WSIZE", "4"); 378 Builder.defineMacro("_EM_PSIZE", "4"); 379 Builder.defineMacro("_EM_SSIZE", "2"); 380 Builder.defineMacro("_EM_LSIZE", "4"); 381 Builder.defineMacro("_EM_FSIZE", "4"); 382 Builder.defineMacro("_EM_DSIZE", "8"); 383 Builder.defineMacro("__ELF__"); 384 DefineStd(Builder, "unix", Opts); 385 } 386 public: 387 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 388 }; 389 390 // Linux target 391 template<typename Target> 392 class LinuxTargetInfo : public OSTargetInfo<Target> { 393 protected: 394 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 395 MacroBuilder &Builder) const override { 396 // Linux defines; list based off of gcc output 397 DefineStd(Builder, "unix", Opts); 398 DefineStd(Builder, "linux", Opts); 399 Builder.defineMacro("__gnu_linux__"); 400 Builder.defineMacro("__ELF__"); 401 if (Triple.isAndroid()) { 402 Builder.defineMacro("__ANDROID__", "1"); 403 unsigned Maj, Min, Rev; 404 Triple.getEnvironmentVersion(Maj, Min, Rev); 405 this->PlatformName = "android"; 406 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 407 } 408 if (Opts.POSIXThreads) 409 Builder.defineMacro("_REENTRANT"); 410 if (Opts.CPlusPlus) 411 Builder.defineMacro("_GNU_SOURCE"); 412 } 413 public: 414 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 415 this->WIntType = TargetInfo::UnsignedInt; 416 417 switch (Triple.getArch()) { 418 default: 419 break; 420 case llvm::Triple::ppc: 421 case llvm::Triple::ppc64: 422 case llvm::Triple::ppc64le: 423 this->MCountName = "_mcount"; 424 break; 425 } 426 } 427 428 const char *getStaticInitSectionSpecifier() const override { 429 return ".text.startup"; 430 } 431 }; 432 433 // NetBSD Target 434 template<typename Target> 435 class NetBSDTargetInfo : public OSTargetInfo<Target> { 436 protected: 437 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 438 MacroBuilder &Builder) const override { 439 // NetBSD defines; list based off of gcc output 440 Builder.defineMacro("__NetBSD__"); 441 Builder.defineMacro("__unix__"); 442 Builder.defineMacro("__ELF__"); 443 if (Opts.POSIXThreads) 444 Builder.defineMacro("_POSIX_THREADS"); 445 446 switch (Triple.getArch()) { 447 default: 448 break; 449 case llvm::Triple::arm: 450 case llvm::Triple::armeb: 451 case llvm::Triple::thumb: 452 case llvm::Triple::thumbeb: 453 Builder.defineMacro("__ARM_DWARF_EH__"); 454 break; 455 } 456 } 457 public: 458 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 459 this->MCountName = "_mcount"; 460 } 461 }; 462 463 // OpenBSD Target 464 template<typename Target> 465 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 466 protected: 467 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 468 MacroBuilder &Builder) const override { 469 // OpenBSD defines; list based off of gcc output 470 471 Builder.defineMacro("__OpenBSD__"); 472 DefineStd(Builder, "unix", Opts); 473 Builder.defineMacro("__ELF__"); 474 if (Opts.POSIXThreads) 475 Builder.defineMacro("_REENTRANT"); 476 } 477 public: 478 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 479 this->TLSSupported = false; 480 481 switch (Triple.getArch()) { 482 default: 483 case llvm::Triple::x86: 484 case llvm::Triple::x86_64: 485 case llvm::Triple::arm: 486 case llvm::Triple::sparc: 487 this->MCountName = "__mcount"; 488 break; 489 case llvm::Triple::mips64: 490 case llvm::Triple::mips64el: 491 case llvm::Triple::ppc: 492 case llvm::Triple::sparcv9: 493 this->MCountName = "_mcount"; 494 break; 495 } 496 } 497 }; 498 499 // Bitrig Target 500 template<typename Target> 501 class BitrigTargetInfo : public OSTargetInfo<Target> { 502 protected: 503 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 504 MacroBuilder &Builder) const override { 505 // Bitrig defines; list based off of gcc output 506 507 Builder.defineMacro("__Bitrig__"); 508 DefineStd(Builder, "unix", Opts); 509 Builder.defineMacro("__ELF__"); 510 if (Opts.POSIXThreads) 511 Builder.defineMacro("_REENTRANT"); 512 513 switch (Triple.getArch()) { 514 default: 515 break; 516 case llvm::Triple::arm: 517 case llvm::Triple::armeb: 518 case llvm::Triple::thumb: 519 case llvm::Triple::thumbeb: 520 Builder.defineMacro("__ARM_DWARF_EH__"); 521 break; 522 } 523 } 524 public: 525 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 526 this->MCountName = "__mcount"; 527 } 528 }; 529 530 // PSP Target 531 template<typename Target> 532 class PSPTargetInfo : public OSTargetInfo<Target> { 533 protected: 534 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 535 MacroBuilder &Builder) const override { 536 // PSP defines; list based on the output of the pspdev gcc toolchain. 537 Builder.defineMacro("PSP"); 538 Builder.defineMacro("_PSP"); 539 Builder.defineMacro("__psp__"); 540 Builder.defineMacro("__ELF__"); 541 } 542 public: 543 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 544 }; 545 546 // PS3 PPU Target 547 template<typename Target> 548 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 549 protected: 550 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 551 MacroBuilder &Builder) const override { 552 // PS3 PPU defines. 553 Builder.defineMacro("__PPC__"); 554 Builder.defineMacro("__PPU__"); 555 Builder.defineMacro("__CELLOS_LV2__"); 556 Builder.defineMacro("__ELF__"); 557 Builder.defineMacro("__LP32__"); 558 Builder.defineMacro("_ARCH_PPC64"); 559 Builder.defineMacro("__powerpc64__"); 560 } 561 public: 562 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 563 this->LongWidth = this->LongAlign = 32; 564 this->PointerWidth = this->PointerAlign = 32; 565 this->IntMaxType = TargetInfo::SignedLongLong; 566 this->Int64Type = TargetInfo::SignedLongLong; 567 this->SizeType = TargetInfo::UnsignedInt; 568 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 569 } 570 }; 571 572 template <typename Target> 573 class PS4OSTargetInfo : public OSTargetInfo<Target> { 574 protected: 575 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 576 MacroBuilder &Builder) const override { 577 Builder.defineMacro("__FreeBSD__", "9"); 578 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 579 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 580 DefineStd(Builder, "unix", Opts); 581 Builder.defineMacro("__ELF__"); 582 Builder.defineMacro("__PS4__"); 583 } 584 public: 585 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 586 this->WCharType = this->UnsignedShort; 587 588 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 589 this->MaxTLSAlign = 256; 590 591 // On PS4, do not honor explicit bit field alignment, 592 // as in "__attribute__((aligned(2))) int b : 1;". 593 this->UseExplicitBitFieldAlignment = false; 594 595 switch (Triple.getArch()) { 596 default: 597 case llvm::Triple::x86_64: 598 this->MCountName = ".mcount"; 599 break; 600 } 601 } 602 }; 603 604 // Solaris target 605 template<typename Target> 606 class SolarisTargetInfo : public OSTargetInfo<Target> { 607 protected: 608 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 609 MacroBuilder &Builder) const override { 610 DefineStd(Builder, "sun", Opts); 611 DefineStd(Builder, "unix", Opts); 612 Builder.defineMacro("__ELF__"); 613 Builder.defineMacro("__svr4__"); 614 Builder.defineMacro("__SVR4"); 615 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 616 // newer, but to 500 for everything else. feature_test.h has a check to 617 // ensure that you are not using C99 with an old version of X/Open or C89 618 // with a new version. 619 if (Opts.C99) 620 Builder.defineMacro("_XOPEN_SOURCE", "600"); 621 else 622 Builder.defineMacro("_XOPEN_SOURCE", "500"); 623 if (Opts.CPlusPlus) 624 Builder.defineMacro("__C99FEATURES__"); 625 Builder.defineMacro("_LARGEFILE_SOURCE"); 626 Builder.defineMacro("_LARGEFILE64_SOURCE"); 627 Builder.defineMacro("__EXTENSIONS__"); 628 Builder.defineMacro("_REENTRANT"); 629 } 630 public: 631 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 632 this->WCharType = this->SignedInt; 633 // FIXME: WIntType should be SignedLong 634 } 635 }; 636 637 // Windows target 638 template<typename Target> 639 class WindowsTargetInfo : public OSTargetInfo<Target> { 640 protected: 641 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 642 MacroBuilder &Builder) const override { 643 Builder.defineMacro("_WIN32"); 644 } 645 void getVisualStudioDefines(const LangOptions &Opts, 646 MacroBuilder &Builder) const { 647 if (Opts.CPlusPlus) { 648 if (Opts.RTTIData) 649 Builder.defineMacro("_CPPRTTI"); 650 651 if (Opts.CXXExceptions) 652 Builder.defineMacro("_CPPUNWIND"); 653 } 654 655 if (Opts.Bool) 656 Builder.defineMacro("__BOOL_DEFINED"); 657 658 if (!Opts.CharIsSigned) 659 Builder.defineMacro("_CHAR_UNSIGNED"); 660 661 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 662 // but it works for now. 663 if (Opts.POSIXThreads) 664 Builder.defineMacro("_MT"); 665 666 if (Opts.MSCompatibilityVersion) { 667 Builder.defineMacro("_MSC_VER", 668 Twine(Opts.MSCompatibilityVersion / 100000)); 669 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 670 // FIXME We cannot encode the revision information into 32-bits 671 Builder.defineMacro("_MSC_BUILD", Twine(1)); 672 673 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 674 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 675 } 676 677 if (Opts.MicrosoftExt) { 678 Builder.defineMacro("_MSC_EXTENSIONS"); 679 680 if (Opts.CPlusPlus11) { 681 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 682 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 683 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 684 } 685 } 686 687 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 688 } 689 690 public: 691 WindowsTargetInfo(const llvm::Triple &Triple) 692 : OSTargetInfo<Target>(Triple) {} 693 }; 694 695 template <typename Target> 696 class NaClTargetInfo : public OSTargetInfo<Target> { 697 protected: 698 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 699 MacroBuilder &Builder) const override { 700 if (Opts.POSIXThreads) 701 Builder.defineMacro("_REENTRANT"); 702 if (Opts.CPlusPlus) 703 Builder.defineMacro("_GNU_SOURCE"); 704 705 DefineStd(Builder, "unix", Opts); 706 Builder.defineMacro("__ELF__"); 707 Builder.defineMacro("__native_client__"); 708 } 709 710 public: 711 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 712 this->LongAlign = 32; 713 this->LongWidth = 32; 714 this->PointerAlign = 32; 715 this->PointerWidth = 32; 716 this->IntMaxType = TargetInfo::SignedLongLong; 717 this->Int64Type = TargetInfo::SignedLongLong; 718 this->DoubleAlign = 64; 719 this->LongDoubleWidth = 64; 720 this->LongDoubleAlign = 64; 721 this->LongLongWidth = 64; 722 this->LongLongAlign = 64; 723 this->SizeType = TargetInfo::UnsignedInt; 724 this->PtrDiffType = TargetInfo::SignedInt; 725 this->IntPtrType = TargetInfo::SignedInt; 726 // RegParmMax is inherited from the underlying architecture 727 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 728 if (Triple.getArch() == llvm::Triple::arm) { 729 // Handled in ARM's setABI(). 730 } else if (Triple.getArch() == llvm::Triple::x86) { 731 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 732 } else if (Triple.getArch() == llvm::Triple::x86_64) { 733 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 734 } else if (Triple.getArch() == llvm::Triple::mipsel) { 735 // Handled on mips' setDataLayout. 736 } else { 737 assert(Triple.getArch() == llvm::Triple::le32); 738 this->resetDataLayout("e-p:32:32-i64:64"); 739 } 740 } 741 }; 742 743 // WebAssembly target 744 template <typename Target> 745 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 746 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 747 MacroBuilder &Builder) const final { 748 // A common platform macro. 749 if (Opts.POSIXThreads) 750 Builder.defineMacro("_REENTRANT"); 751 // Follow g++ convention and predefine _GNU_SOURCE for C++. 752 if (Opts.CPlusPlus) 753 Builder.defineMacro("_GNU_SOURCE"); 754 } 755 756 // As an optimization, group static init code together in a section. 757 const char *getStaticInitSectionSpecifier() const final { 758 return ".text.__startup"; 759 } 760 761 public: 762 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple) 763 : OSTargetInfo<Target>(Triple) { 764 this->MCountName = "__mcount"; 765 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 766 } 767 }; 768 769 //===----------------------------------------------------------------------===// 770 // Specific target implementations. 771 //===----------------------------------------------------------------------===// 772 773 // PPC abstract base class 774 class PPCTargetInfo : public TargetInfo { 775 static const Builtin::Info BuiltinInfo[]; 776 static const char * const GCCRegNames[]; 777 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 778 std::string CPU; 779 780 // Target cpu features. 781 bool HasVSX; 782 bool HasP8Vector; 783 bool HasP8Crypto; 784 bool HasDirectMove; 785 bool HasQPX; 786 bool HasHTM; 787 bool HasBPERMD; 788 bool HasExtDiv; 789 790 protected: 791 std::string ABI; 792 793 public: 794 PPCTargetInfo(const llvm::Triple &Triple) 795 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 796 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 797 HasBPERMD(false), HasExtDiv(false) { 798 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 799 SimdDefaultAlign = 128; 800 LongDoubleWidth = LongDoubleAlign = 128; 801 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 802 } 803 804 /// \brief Flags for architecture specific defines. 805 typedef enum { 806 ArchDefineNone = 0, 807 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 808 ArchDefinePpcgr = 1 << 1, 809 ArchDefinePpcsq = 1 << 2, 810 ArchDefine440 = 1 << 3, 811 ArchDefine603 = 1 << 4, 812 ArchDefine604 = 1 << 5, 813 ArchDefinePwr4 = 1 << 6, 814 ArchDefinePwr5 = 1 << 7, 815 ArchDefinePwr5x = 1 << 8, 816 ArchDefinePwr6 = 1 << 9, 817 ArchDefinePwr6x = 1 << 10, 818 ArchDefinePwr7 = 1 << 11, 819 ArchDefinePwr8 = 1 << 12, 820 ArchDefineA2 = 1 << 13, 821 ArchDefineA2q = 1 << 14 822 } ArchDefineTypes; 823 824 // Note: GCC recognizes the following additional cpus: 825 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 826 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 827 // titan, rs64. 828 bool setCPU(const std::string &Name) override { 829 bool CPUKnown = llvm::StringSwitch<bool>(Name) 830 .Case("generic", true) 831 .Case("440", true) 832 .Case("450", true) 833 .Case("601", true) 834 .Case("602", true) 835 .Case("603", true) 836 .Case("603e", true) 837 .Case("603ev", true) 838 .Case("604", true) 839 .Case("604e", true) 840 .Case("620", true) 841 .Case("630", true) 842 .Case("g3", true) 843 .Case("7400", true) 844 .Case("g4", true) 845 .Case("7450", true) 846 .Case("g4+", true) 847 .Case("750", true) 848 .Case("970", true) 849 .Case("g5", true) 850 .Case("a2", true) 851 .Case("a2q", true) 852 .Case("e500mc", true) 853 .Case("e5500", true) 854 .Case("power3", true) 855 .Case("pwr3", true) 856 .Case("power4", true) 857 .Case("pwr4", true) 858 .Case("power5", true) 859 .Case("pwr5", true) 860 .Case("power5x", true) 861 .Case("pwr5x", true) 862 .Case("power6", true) 863 .Case("pwr6", true) 864 .Case("power6x", true) 865 .Case("pwr6x", true) 866 .Case("power7", true) 867 .Case("pwr7", true) 868 .Case("power8", true) 869 .Case("pwr8", true) 870 .Case("powerpc", true) 871 .Case("ppc", true) 872 .Case("powerpc64", true) 873 .Case("ppc64", true) 874 .Case("powerpc64le", true) 875 .Case("ppc64le", true) 876 .Default(false); 877 878 if (CPUKnown) 879 CPU = Name; 880 881 return CPUKnown; 882 } 883 884 885 StringRef getABI() const override { return ABI; } 886 887 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 888 return llvm::makeArrayRef(BuiltinInfo, 889 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 890 } 891 892 bool isCLZForZeroUndef() const override { return false; } 893 894 void getTargetDefines(const LangOptions &Opts, 895 MacroBuilder &Builder) const override; 896 897 bool 898 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 899 StringRef CPU, 900 const std::vector<std::string> &FeaturesVec) const override; 901 902 bool handleTargetFeatures(std::vector<std::string> &Features, 903 DiagnosticsEngine &Diags) override; 904 bool hasFeature(StringRef Feature) const override; 905 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 906 bool Enabled) const override; 907 908 ArrayRef<const char *> getGCCRegNames() const override; 909 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 910 bool validateAsmConstraint(const char *&Name, 911 TargetInfo::ConstraintInfo &Info) const override { 912 switch (*Name) { 913 default: return false; 914 case 'O': // Zero 915 break; 916 case 'b': // Base register 917 case 'f': // Floating point register 918 Info.setAllowsRegister(); 919 break; 920 // FIXME: The following are added to allow parsing. 921 // I just took a guess at what the actions should be. 922 // Also, is more specific checking needed? I.e. specific registers? 923 case 'd': // Floating point register (containing 64-bit value) 924 case 'v': // Altivec vector register 925 Info.setAllowsRegister(); 926 break; 927 case 'w': 928 switch (Name[1]) { 929 case 'd':// VSX vector register to hold vector double data 930 case 'f':// VSX vector register to hold vector float data 931 case 's':// VSX vector register to hold scalar float data 932 case 'a':// Any VSX register 933 case 'c':// An individual CR bit 934 break; 935 default: 936 return false; 937 } 938 Info.setAllowsRegister(); 939 Name++; // Skip over 'w'. 940 break; 941 case 'h': // `MQ', `CTR', or `LINK' register 942 case 'q': // `MQ' register 943 case 'c': // `CTR' register 944 case 'l': // `LINK' register 945 case 'x': // `CR' register (condition register) number 0 946 case 'y': // `CR' register (condition register) 947 case 'z': // `XER[CA]' carry bit (part of the XER register) 948 Info.setAllowsRegister(); 949 break; 950 case 'I': // Signed 16-bit constant 951 case 'J': // Unsigned 16-bit constant shifted left 16 bits 952 // (use `L' instead for SImode constants) 953 case 'K': // Unsigned 16-bit constant 954 case 'L': // Signed 16-bit constant shifted left 16 bits 955 case 'M': // Constant larger than 31 956 case 'N': // Exact power of 2 957 case 'P': // Constant whose negation is a signed 16-bit constant 958 case 'G': // Floating point constant that can be loaded into a 959 // register with one instruction per word 960 case 'H': // Integer/Floating point constant that can be loaded 961 // into a register using three instructions 962 break; 963 case 'm': // Memory operand. Note that on PowerPC targets, m can 964 // include addresses that update the base register. It 965 // is therefore only safe to use `m' in an asm statement 966 // if that asm statement accesses the operand exactly once. 967 // The asm statement must also use `%U<opno>' as a 968 // placeholder for the "update" flag in the corresponding 969 // load or store instruction. For example: 970 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 971 // is correct but: 972 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 973 // is not. Use es rather than m if you don't want the base 974 // register to be updated. 975 case 'e': 976 if (Name[1] != 's') 977 return false; 978 // es: A "stable" memory operand; that is, one which does not 979 // include any automodification of the base register. Unlike 980 // `m', this constraint can be used in asm statements that 981 // might access the operand several times, or that might not 982 // access it at all. 983 Info.setAllowsMemory(); 984 Name++; // Skip over 'e'. 985 break; 986 case 'Q': // Memory operand that is an offset from a register (it is 987 // usually better to use `m' or `es' in asm statements) 988 case 'Z': // Memory operand that is an indexed or indirect from a 989 // register (it is usually better to use `m' or `es' in 990 // asm statements) 991 Info.setAllowsMemory(); 992 Info.setAllowsRegister(); 993 break; 994 case 'R': // AIX TOC entry 995 case 'a': // Address operand that is an indexed or indirect from a 996 // register (`p' is preferable for asm statements) 997 case 'S': // Constant suitable as a 64-bit mask operand 998 case 'T': // Constant suitable as a 32-bit mask operand 999 case 'U': // System V Release 4 small data area reference 1000 case 't': // AND masks that can be performed by two rldic{l, r} 1001 // instructions 1002 case 'W': // Vector constant that does not require memory 1003 case 'j': // Vector constant that is all zeros. 1004 break; 1005 // End FIXME. 1006 } 1007 return true; 1008 } 1009 std::string convertConstraint(const char *&Constraint) const override { 1010 std::string R; 1011 switch (*Constraint) { 1012 case 'e': 1013 case 'w': 1014 // Two-character constraint; add "^" hint for later parsing. 1015 R = std::string("^") + std::string(Constraint, 2); 1016 Constraint++; 1017 break; 1018 default: 1019 return TargetInfo::convertConstraint(Constraint); 1020 } 1021 return R; 1022 } 1023 const char *getClobbers() const override { 1024 return ""; 1025 } 1026 int getEHDataRegisterNumber(unsigned RegNo) const override { 1027 if (RegNo == 0) return 3; 1028 if (RegNo == 1) return 4; 1029 return -1; 1030 } 1031 1032 bool hasSjLjLowering() const override { 1033 return true; 1034 } 1035 1036 bool useFloat128ManglingForLongDouble() const override { 1037 return LongDoubleWidth == 128 && 1038 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1039 getTriple().isOSBinFormatELF(); 1040 } 1041 }; 1042 1043 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1044 #define BUILTIN(ID, TYPE, ATTRS) \ 1045 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1046 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1047 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1048 #include "clang/Basic/BuiltinsPPC.def" 1049 }; 1050 1051 /// handleTargetFeatures - Perform initialization based on the user 1052 /// configured set of features. 1053 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1054 DiagnosticsEngine &Diags) { 1055 for (const auto &Feature : Features) { 1056 if (Feature == "+vsx") { 1057 HasVSX = true; 1058 } else if (Feature == "+bpermd") { 1059 HasBPERMD = true; 1060 } else if (Feature == "+extdiv") { 1061 HasExtDiv = true; 1062 } else if (Feature == "+power8-vector") { 1063 HasP8Vector = true; 1064 } else if (Feature == "+crypto") { 1065 HasP8Crypto = true; 1066 } else if (Feature == "+direct-move") { 1067 HasDirectMove = true; 1068 } else if (Feature == "+qpx") { 1069 HasQPX = true; 1070 } else if (Feature == "+htm") { 1071 HasHTM = true; 1072 } 1073 // TODO: Finish this list and add an assert that we've handled them 1074 // all. 1075 } 1076 1077 return true; 1078 } 1079 1080 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1081 /// #defines that are not tied to a specific subtarget. 1082 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1083 MacroBuilder &Builder) const { 1084 // Target identification. 1085 Builder.defineMacro("__ppc__"); 1086 Builder.defineMacro("__PPC__"); 1087 Builder.defineMacro("_ARCH_PPC"); 1088 Builder.defineMacro("__powerpc__"); 1089 Builder.defineMacro("__POWERPC__"); 1090 if (PointerWidth == 64) { 1091 Builder.defineMacro("_ARCH_PPC64"); 1092 Builder.defineMacro("__powerpc64__"); 1093 Builder.defineMacro("__ppc64__"); 1094 Builder.defineMacro("__PPC64__"); 1095 } 1096 1097 // Target properties. 1098 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1099 Builder.defineMacro("_LITTLE_ENDIAN"); 1100 } else { 1101 if (getTriple().getOS() != llvm::Triple::NetBSD && 1102 getTriple().getOS() != llvm::Triple::OpenBSD) 1103 Builder.defineMacro("_BIG_ENDIAN"); 1104 } 1105 1106 // ABI options. 1107 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1108 Builder.defineMacro("_CALL_ELF", "1"); 1109 if (ABI == "elfv2") 1110 Builder.defineMacro("_CALL_ELF", "2"); 1111 1112 // Subtarget options. 1113 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1114 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1115 1116 // FIXME: Should be controlled by command line option. 1117 if (LongDoubleWidth == 128) 1118 Builder.defineMacro("__LONG_DOUBLE_128__"); 1119 1120 if (Opts.AltiVec) { 1121 Builder.defineMacro("__VEC__", "10206"); 1122 Builder.defineMacro("__ALTIVEC__"); 1123 } 1124 1125 // CPU identification. 1126 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1127 .Case("440", ArchDefineName) 1128 .Case("450", ArchDefineName | ArchDefine440) 1129 .Case("601", ArchDefineName) 1130 .Case("602", ArchDefineName | ArchDefinePpcgr) 1131 .Case("603", ArchDefineName | ArchDefinePpcgr) 1132 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1133 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1134 .Case("604", ArchDefineName | ArchDefinePpcgr) 1135 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1136 .Case("620", ArchDefineName | ArchDefinePpcgr) 1137 .Case("630", ArchDefineName | ArchDefinePpcgr) 1138 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1139 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1140 .Case("750", ArchDefineName | ArchDefinePpcgr) 1141 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1142 | ArchDefinePpcsq) 1143 .Case("a2", ArchDefineA2) 1144 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1145 .Case("pwr3", ArchDefinePpcgr) 1146 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1147 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1148 | ArchDefinePpcsq) 1149 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1150 | ArchDefinePpcgr | ArchDefinePpcsq) 1151 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1152 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1153 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1154 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1155 | ArchDefinePpcsq) 1156 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1157 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1158 | ArchDefinePpcgr | ArchDefinePpcsq) 1159 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1160 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1161 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1162 .Case("power3", ArchDefinePpcgr) 1163 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1164 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1165 | ArchDefinePpcsq) 1166 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1167 | ArchDefinePpcgr | ArchDefinePpcsq) 1168 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1169 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1170 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1171 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1172 | ArchDefinePpcsq) 1173 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1174 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1175 | ArchDefinePpcgr | ArchDefinePpcsq) 1176 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1177 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1178 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1179 .Default(ArchDefineNone); 1180 1181 if (defs & ArchDefineName) 1182 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1183 if (defs & ArchDefinePpcgr) 1184 Builder.defineMacro("_ARCH_PPCGR"); 1185 if (defs & ArchDefinePpcsq) 1186 Builder.defineMacro("_ARCH_PPCSQ"); 1187 if (defs & ArchDefine440) 1188 Builder.defineMacro("_ARCH_440"); 1189 if (defs & ArchDefine603) 1190 Builder.defineMacro("_ARCH_603"); 1191 if (defs & ArchDefine604) 1192 Builder.defineMacro("_ARCH_604"); 1193 if (defs & ArchDefinePwr4) 1194 Builder.defineMacro("_ARCH_PWR4"); 1195 if (defs & ArchDefinePwr5) 1196 Builder.defineMacro("_ARCH_PWR5"); 1197 if (defs & ArchDefinePwr5x) 1198 Builder.defineMacro("_ARCH_PWR5X"); 1199 if (defs & ArchDefinePwr6) 1200 Builder.defineMacro("_ARCH_PWR6"); 1201 if (defs & ArchDefinePwr6x) 1202 Builder.defineMacro("_ARCH_PWR6X"); 1203 if (defs & ArchDefinePwr7) 1204 Builder.defineMacro("_ARCH_PWR7"); 1205 if (defs & ArchDefinePwr8) 1206 Builder.defineMacro("_ARCH_PWR8"); 1207 if (defs & ArchDefineA2) 1208 Builder.defineMacro("_ARCH_A2"); 1209 if (defs & ArchDefineA2q) { 1210 Builder.defineMacro("_ARCH_A2Q"); 1211 Builder.defineMacro("_ARCH_QP"); 1212 } 1213 1214 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1215 Builder.defineMacro("__bg__"); 1216 Builder.defineMacro("__THW_BLUEGENE__"); 1217 Builder.defineMacro("__bgq__"); 1218 Builder.defineMacro("__TOS_BGQ__"); 1219 } 1220 1221 if (HasVSX) 1222 Builder.defineMacro("__VSX__"); 1223 if (HasP8Vector) 1224 Builder.defineMacro("__POWER8_VECTOR__"); 1225 if (HasP8Crypto) 1226 Builder.defineMacro("__CRYPTO__"); 1227 if (HasHTM) 1228 Builder.defineMacro("__HTM__"); 1229 1230 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1231 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1232 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1233 if (PointerWidth == 64) 1234 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1235 1236 // FIXME: The following are not yet generated here by Clang, but are 1237 // generated by GCC: 1238 // 1239 // _SOFT_FLOAT_ 1240 // __RECIP_PRECISION__ 1241 // __APPLE_ALTIVEC__ 1242 // __RECIP__ 1243 // __RECIPF__ 1244 // __RSQRTE__ 1245 // __RSQRTEF__ 1246 // _SOFT_DOUBLE_ 1247 // __NO_LWSYNC__ 1248 // __HAVE_BSWAP__ 1249 // __LONGDOUBLE128 1250 // __CMODEL_MEDIUM__ 1251 // __CMODEL_LARGE__ 1252 // _CALL_SYSV 1253 // _CALL_DARWIN 1254 // __NO_FPRS__ 1255 } 1256 1257 // Handle explicit options being passed to the compiler here: if we've 1258 // explicitly turned off vsx and turned on power8-vector or direct-move then 1259 // go ahead and error since the customer has expressed a somewhat incompatible 1260 // set of options. 1261 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1262 const std::vector<std::string> &FeaturesVec) { 1263 1264 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1265 FeaturesVec.end()) { 1266 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1267 FeaturesVec.end()) { 1268 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1269 << "-mno-vsx"; 1270 return false; 1271 } 1272 1273 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1274 FeaturesVec.end()) { 1275 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1276 << "-mno-vsx"; 1277 return false; 1278 } 1279 } 1280 1281 return true; 1282 } 1283 1284 bool PPCTargetInfo::initFeatureMap( 1285 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1286 const std::vector<std::string> &FeaturesVec) const { 1287 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1288 .Case("7400", true) 1289 .Case("g4", true) 1290 .Case("7450", true) 1291 .Case("g4+", true) 1292 .Case("970", true) 1293 .Case("g5", true) 1294 .Case("pwr6", true) 1295 .Case("pwr7", true) 1296 .Case("pwr8", true) 1297 .Case("ppc64", true) 1298 .Case("ppc64le", true) 1299 .Default(false); 1300 1301 Features["qpx"] = (CPU == "a2q"); 1302 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1303 .Case("ppc64le", true) 1304 .Case("pwr8", true) 1305 .Default(false); 1306 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1307 .Case("ppc64le", true) 1308 .Case("pwr8", true) 1309 .Default(false); 1310 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1311 .Case("ppc64le", true) 1312 .Case("pwr8", true) 1313 .Case("pwr7", true) 1314 .Default(false); 1315 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1316 .Case("ppc64le", true) 1317 .Case("pwr8", true) 1318 .Case("pwr7", true) 1319 .Default(false); 1320 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1321 .Case("ppc64le", true) 1322 .Case("pwr8", true) 1323 .Default(false); 1324 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1325 .Case("ppc64le", true) 1326 .Case("pwr8", true) 1327 .Case("pwr7", true) 1328 .Default(false); 1329 1330 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1331 return false; 1332 1333 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1334 } 1335 1336 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1337 return llvm::StringSwitch<bool>(Feature) 1338 .Case("powerpc", true) 1339 .Case("vsx", HasVSX) 1340 .Case("power8-vector", HasP8Vector) 1341 .Case("crypto", HasP8Crypto) 1342 .Case("direct-move", HasDirectMove) 1343 .Case("qpx", HasQPX) 1344 .Case("htm", HasHTM) 1345 .Case("bpermd", HasBPERMD) 1346 .Case("extdiv", HasExtDiv) 1347 .Default(false); 1348 } 1349 1350 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1351 StringRef Name, bool Enabled) const { 1352 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1353 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1354 // incompatible options. 1355 if (Enabled) { 1356 if (Name == "vsx") { 1357 Features[Name] = true; 1358 } else if (Name == "direct-move") { 1359 Features[Name] = Features["vsx"] = true; 1360 } else if (Name == "power8-vector") { 1361 Features[Name] = Features["vsx"] = true; 1362 } else { 1363 Features[Name] = true; 1364 } 1365 } else { 1366 if (Name == "vsx") { 1367 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1368 false; 1369 } else { 1370 Features[Name] = false; 1371 } 1372 } 1373 } 1374 1375 const char * const PPCTargetInfo::GCCRegNames[] = { 1376 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1377 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1378 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1379 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1380 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1381 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1382 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1383 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1384 "mq", "lr", "ctr", "ap", 1385 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1386 "xer", 1387 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1388 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1389 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1390 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1391 "vrsave", "vscr", 1392 "spe_acc", "spefscr", 1393 "sfp" 1394 }; 1395 1396 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1397 return llvm::makeArrayRef(GCCRegNames); 1398 } 1399 1400 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1401 // While some of these aliases do map to different registers 1402 // they still share the same register name. 1403 { { "0" }, "r0" }, 1404 { { "1"}, "r1" }, 1405 { { "2" }, "r2" }, 1406 { { "3" }, "r3" }, 1407 { { "4" }, "r4" }, 1408 { { "5" }, "r5" }, 1409 { { "6" }, "r6" }, 1410 { { "7" }, "r7" }, 1411 { { "8" }, "r8" }, 1412 { { "9" }, "r9" }, 1413 { { "10" }, "r10" }, 1414 { { "11" }, "r11" }, 1415 { { "12" }, "r12" }, 1416 { { "13" }, "r13" }, 1417 { { "14" }, "r14" }, 1418 { { "15" }, "r15" }, 1419 { { "16" }, "r16" }, 1420 { { "17" }, "r17" }, 1421 { { "18" }, "r18" }, 1422 { { "19" }, "r19" }, 1423 { { "20" }, "r20" }, 1424 { { "21" }, "r21" }, 1425 { { "22" }, "r22" }, 1426 { { "23" }, "r23" }, 1427 { { "24" }, "r24" }, 1428 { { "25" }, "r25" }, 1429 { { "26" }, "r26" }, 1430 { { "27" }, "r27" }, 1431 { { "28" }, "r28" }, 1432 { { "29" }, "r29" }, 1433 { { "30" }, "r30" }, 1434 { { "31" }, "r31" }, 1435 { { "fr0" }, "f0" }, 1436 { { "fr1" }, "f1" }, 1437 { { "fr2" }, "f2" }, 1438 { { "fr3" }, "f3" }, 1439 { { "fr4" }, "f4" }, 1440 { { "fr5" }, "f5" }, 1441 { { "fr6" }, "f6" }, 1442 { { "fr7" }, "f7" }, 1443 { { "fr8" }, "f8" }, 1444 { { "fr9" }, "f9" }, 1445 { { "fr10" }, "f10" }, 1446 { { "fr11" }, "f11" }, 1447 { { "fr12" }, "f12" }, 1448 { { "fr13" }, "f13" }, 1449 { { "fr14" }, "f14" }, 1450 { { "fr15" }, "f15" }, 1451 { { "fr16" }, "f16" }, 1452 { { "fr17" }, "f17" }, 1453 { { "fr18" }, "f18" }, 1454 { { "fr19" }, "f19" }, 1455 { { "fr20" }, "f20" }, 1456 { { "fr21" }, "f21" }, 1457 { { "fr22" }, "f22" }, 1458 { { "fr23" }, "f23" }, 1459 { { "fr24" }, "f24" }, 1460 { { "fr25" }, "f25" }, 1461 { { "fr26" }, "f26" }, 1462 { { "fr27" }, "f27" }, 1463 { { "fr28" }, "f28" }, 1464 { { "fr29" }, "f29" }, 1465 { { "fr30" }, "f30" }, 1466 { { "fr31" }, "f31" }, 1467 { { "cc" }, "cr0" }, 1468 }; 1469 1470 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1471 return llvm::makeArrayRef(GCCRegAliases); 1472 } 1473 1474 class PPC32TargetInfo : public PPCTargetInfo { 1475 public: 1476 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1477 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1478 1479 switch (getTriple().getOS()) { 1480 case llvm::Triple::Linux: 1481 case llvm::Triple::FreeBSD: 1482 case llvm::Triple::NetBSD: 1483 SizeType = UnsignedInt; 1484 PtrDiffType = SignedInt; 1485 IntPtrType = SignedInt; 1486 break; 1487 default: 1488 break; 1489 } 1490 1491 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1492 LongDoubleWidth = LongDoubleAlign = 64; 1493 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1494 } 1495 1496 // PPC32 supports atomics up to 4 bytes. 1497 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1498 } 1499 1500 BuiltinVaListKind getBuiltinVaListKind() const override { 1501 // This is the ELF definition, and is overridden by the Darwin sub-target 1502 return TargetInfo::PowerABIBuiltinVaList; 1503 } 1504 }; 1505 1506 // Note: ABI differences may eventually require us to have a separate 1507 // TargetInfo for little endian. 1508 class PPC64TargetInfo : public PPCTargetInfo { 1509 public: 1510 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1511 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1512 IntMaxType = SignedLong; 1513 Int64Type = SignedLong; 1514 1515 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1516 resetDataLayout("e-m:e-i64:64-n32:64"); 1517 ABI = "elfv2"; 1518 } else { 1519 resetDataLayout("E-m:e-i64:64-n32:64"); 1520 ABI = "elfv1"; 1521 } 1522 1523 switch (getTriple().getOS()) { 1524 case llvm::Triple::FreeBSD: 1525 LongDoubleWidth = LongDoubleAlign = 64; 1526 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1527 break; 1528 case llvm::Triple::NetBSD: 1529 IntMaxType = SignedLongLong; 1530 Int64Type = SignedLongLong; 1531 break; 1532 default: 1533 break; 1534 } 1535 1536 // PPC64 supports atomics up to 8 bytes. 1537 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1538 } 1539 BuiltinVaListKind getBuiltinVaListKind() const override { 1540 return TargetInfo::CharPtrBuiltinVaList; 1541 } 1542 // PPC64 Linux-specific ABI options. 1543 bool setABI(const std::string &Name) override { 1544 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1545 ABI = Name; 1546 return true; 1547 } 1548 return false; 1549 } 1550 }; 1551 1552 class DarwinPPC32TargetInfo : 1553 public DarwinTargetInfo<PPC32TargetInfo> { 1554 public: 1555 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1556 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1557 HasAlignMac68kSupport = true; 1558 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1559 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1560 LongLongAlign = 32; 1561 SuitableAlign = 128; 1562 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1563 } 1564 BuiltinVaListKind getBuiltinVaListKind() const override { 1565 return TargetInfo::CharPtrBuiltinVaList; 1566 } 1567 }; 1568 1569 class DarwinPPC64TargetInfo : 1570 public DarwinTargetInfo<PPC64TargetInfo> { 1571 public: 1572 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1573 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1574 HasAlignMac68kSupport = true; 1575 SuitableAlign = 128; 1576 resetDataLayout("E-m:o-i64:64-n32:64"); 1577 } 1578 }; 1579 1580 static const unsigned NVPTXAddrSpaceMap[] = { 1581 1, // opencl_global 1582 3, // opencl_local 1583 4, // opencl_constant 1584 // FIXME: generic has to be added to the target 1585 0, // opencl_generic 1586 1, // cuda_device 1587 4, // cuda_constant 1588 3, // cuda_shared 1589 }; 1590 1591 class NVPTXTargetInfo : public TargetInfo { 1592 static const char *const GCCRegNames[]; 1593 static const Builtin::Info BuiltinInfo[]; 1594 1595 // The GPU profiles supported by the NVPTX backend 1596 enum GPUKind { 1597 GK_NONE, 1598 GK_SM20, 1599 GK_SM21, 1600 GK_SM30, 1601 GK_SM35, 1602 GK_SM37, 1603 } GPU; 1604 1605 public: 1606 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1607 BigEndian = false; 1608 TLSSupported = false; 1609 LongWidth = LongAlign = 64; 1610 AddrSpaceMap = &NVPTXAddrSpaceMap; 1611 UseAddrSpaceMapMangling = true; 1612 // Define available target features 1613 // These must be defined in sorted order! 1614 NoAsmVariants = true; 1615 // Set the default GPU to sm20 1616 GPU = GK_SM20; 1617 } 1618 void getTargetDefines(const LangOptions &Opts, 1619 MacroBuilder &Builder) const override { 1620 Builder.defineMacro("__PTX__"); 1621 Builder.defineMacro("__NVPTX__"); 1622 if (Opts.CUDAIsDevice) { 1623 // Set __CUDA_ARCH__ for the GPU specified. 1624 std::string CUDAArchCode; 1625 switch (GPU) { 1626 case GK_SM20: 1627 CUDAArchCode = "200"; 1628 break; 1629 case GK_SM21: 1630 CUDAArchCode = "210"; 1631 break; 1632 case GK_SM30: 1633 CUDAArchCode = "300"; 1634 break; 1635 case GK_SM35: 1636 CUDAArchCode = "350"; 1637 break; 1638 case GK_SM37: 1639 CUDAArchCode = "370"; 1640 break; 1641 default: 1642 llvm_unreachable("Unhandled target CPU"); 1643 } 1644 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1645 } 1646 } 1647 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1648 return llvm::makeArrayRef(BuiltinInfo, 1649 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1650 } 1651 bool hasFeature(StringRef Feature) const override { 1652 return Feature == "ptx" || Feature == "nvptx"; 1653 } 1654 1655 ArrayRef<const char *> getGCCRegNames() const override; 1656 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1657 // No aliases. 1658 return None; 1659 } 1660 bool validateAsmConstraint(const char *&Name, 1661 TargetInfo::ConstraintInfo &Info) const override { 1662 switch (*Name) { 1663 default: 1664 return false; 1665 case 'c': 1666 case 'h': 1667 case 'r': 1668 case 'l': 1669 case 'f': 1670 case 'd': 1671 Info.setAllowsRegister(); 1672 return true; 1673 } 1674 } 1675 const char *getClobbers() const override { 1676 // FIXME: Is this really right? 1677 return ""; 1678 } 1679 BuiltinVaListKind getBuiltinVaListKind() const override { 1680 // FIXME: implement 1681 return TargetInfo::CharPtrBuiltinVaList; 1682 } 1683 bool setCPU(const std::string &Name) override { 1684 GPU = llvm::StringSwitch<GPUKind>(Name) 1685 .Case("sm_20", GK_SM20) 1686 .Case("sm_21", GK_SM21) 1687 .Case("sm_30", GK_SM30) 1688 .Case("sm_35", GK_SM35) 1689 .Case("sm_37", GK_SM37) 1690 .Default(GK_NONE); 1691 1692 return GPU != GK_NONE; 1693 } 1694 }; 1695 1696 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1697 #define BUILTIN(ID, TYPE, ATTRS) \ 1698 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1699 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1700 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1701 #include "clang/Basic/BuiltinsNVPTX.def" 1702 }; 1703 1704 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1705 1706 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1707 return llvm::makeArrayRef(GCCRegNames); 1708 } 1709 1710 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1711 public: 1712 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1713 LongWidth = LongAlign = 32; 1714 PointerWidth = PointerAlign = 32; 1715 SizeType = TargetInfo::UnsignedInt; 1716 PtrDiffType = TargetInfo::SignedInt; 1717 IntPtrType = TargetInfo::SignedInt; 1718 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1719 } 1720 }; 1721 1722 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1723 public: 1724 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1725 PointerWidth = PointerAlign = 64; 1726 SizeType = TargetInfo::UnsignedLong; 1727 PtrDiffType = TargetInfo::SignedLong; 1728 IntPtrType = TargetInfo::SignedLong; 1729 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1730 } 1731 }; 1732 1733 static const unsigned AMDGPUAddrSpaceMap[] = { 1734 1, // opencl_global 1735 3, // opencl_local 1736 2, // opencl_constant 1737 4, // opencl_generic 1738 1, // cuda_device 1739 2, // cuda_constant 1740 3 // cuda_shared 1741 }; 1742 1743 // If you edit the description strings, make sure you update 1744 // getPointerWidthV(). 1745 1746 static const char *const DataLayoutStringR600 = 1747 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1748 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1749 1750 static const char *const DataLayoutStringR600DoubleOps = 1751 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1752 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1753 1754 static const char *const DataLayoutStringSI = 1755 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1756 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1757 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1758 1759 class AMDGPUTargetInfo : public TargetInfo { 1760 static const Builtin::Info BuiltinInfo[]; 1761 static const char * const GCCRegNames[]; 1762 1763 /// \brief The GPU profiles supported by the AMDGPU target. 1764 enum GPUKind { 1765 GK_NONE, 1766 GK_R600, 1767 GK_R600_DOUBLE_OPS, 1768 GK_R700, 1769 GK_R700_DOUBLE_OPS, 1770 GK_EVERGREEN, 1771 GK_EVERGREEN_DOUBLE_OPS, 1772 GK_NORTHERN_ISLANDS, 1773 GK_CAYMAN, 1774 GK_SOUTHERN_ISLANDS, 1775 GK_SEA_ISLANDS, 1776 GK_VOLCANIC_ISLANDS 1777 } GPU; 1778 1779 bool hasFP64:1; 1780 bool hasFMAF:1; 1781 bool hasLDEXPF:1; 1782 1783 public: 1784 AMDGPUTargetInfo(const llvm::Triple &Triple) 1785 : TargetInfo(Triple) { 1786 1787 if (Triple.getArch() == llvm::Triple::amdgcn) { 1788 resetDataLayout(DataLayoutStringSI); 1789 GPU = GK_SOUTHERN_ISLANDS; 1790 hasFP64 = true; 1791 hasFMAF = true; 1792 hasLDEXPF = true; 1793 } else { 1794 resetDataLayout(DataLayoutStringR600); 1795 GPU = GK_R600; 1796 hasFP64 = false; 1797 hasFMAF = false; 1798 hasLDEXPF = false; 1799 } 1800 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1801 UseAddrSpaceMapMangling = true; 1802 } 1803 1804 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1805 if (GPU <= GK_CAYMAN) 1806 return 32; 1807 1808 switch(AddrSpace) { 1809 default: 1810 return 64; 1811 case 0: 1812 case 3: 1813 case 5: 1814 return 32; 1815 } 1816 } 1817 1818 const char * getClobbers() const override { 1819 return ""; 1820 } 1821 1822 ArrayRef<const char *> getGCCRegNames() const override; 1823 1824 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1825 return None; 1826 } 1827 1828 bool validateAsmConstraint(const char *&Name, 1829 TargetInfo::ConstraintInfo &Info) const override { 1830 switch (*Name) { 1831 default: break; 1832 case 'v': // vgpr 1833 case 's': // sgpr 1834 Info.setAllowsRegister(); 1835 return true; 1836 } 1837 return false; 1838 } 1839 1840 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1841 return llvm::makeArrayRef(BuiltinInfo, 1842 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 1843 } 1844 1845 void getTargetDefines(const LangOptions &Opts, 1846 MacroBuilder &Builder) const override { 1847 if (getTriple().getArch() == llvm::Triple::amdgcn) 1848 Builder.defineMacro("__AMDGCN__"); 1849 else 1850 Builder.defineMacro("__R600__"); 1851 1852 if (hasFMAF) 1853 Builder.defineMacro("__HAS_FMAF__"); 1854 if (hasLDEXPF) 1855 Builder.defineMacro("__HAS_LDEXPF__"); 1856 if (hasFP64 && Opts.OpenCL) 1857 Builder.defineMacro("cl_khr_fp64"); 1858 if (Opts.OpenCL) { 1859 if (GPU >= GK_NORTHERN_ISLANDS) { 1860 Builder.defineMacro("cl_khr_byte_addressable_store"); 1861 Builder.defineMacro("cl_khr_global_int32_base_atomics"); 1862 Builder.defineMacro("cl_khr_global_int32_extended_atomics"); 1863 Builder.defineMacro("cl_khr_local_int32_base_atomics"); 1864 Builder.defineMacro("cl_khr_local_int32_extended_atomics"); 1865 } 1866 } 1867 } 1868 1869 BuiltinVaListKind getBuiltinVaListKind() const override { 1870 return TargetInfo::CharPtrBuiltinVaList; 1871 } 1872 1873 bool setCPU(const std::string &Name) override { 1874 GPU = llvm::StringSwitch<GPUKind>(Name) 1875 .Case("r600" , GK_R600) 1876 .Case("rv610", GK_R600) 1877 .Case("rv620", GK_R600) 1878 .Case("rv630", GK_R600) 1879 .Case("rv635", GK_R600) 1880 .Case("rs780", GK_R600) 1881 .Case("rs880", GK_R600) 1882 .Case("rv670", GK_R600_DOUBLE_OPS) 1883 .Case("rv710", GK_R700) 1884 .Case("rv730", GK_R700) 1885 .Case("rv740", GK_R700_DOUBLE_OPS) 1886 .Case("rv770", GK_R700_DOUBLE_OPS) 1887 .Case("palm", GK_EVERGREEN) 1888 .Case("cedar", GK_EVERGREEN) 1889 .Case("sumo", GK_EVERGREEN) 1890 .Case("sumo2", GK_EVERGREEN) 1891 .Case("redwood", GK_EVERGREEN) 1892 .Case("juniper", GK_EVERGREEN) 1893 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1894 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1895 .Case("barts", GK_NORTHERN_ISLANDS) 1896 .Case("turks", GK_NORTHERN_ISLANDS) 1897 .Case("caicos", GK_NORTHERN_ISLANDS) 1898 .Case("cayman", GK_CAYMAN) 1899 .Case("aruba", GK_CAYMAN) 1900 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1901 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1902 .Case("verde", GK_SOUTHERN_ISLANDS) 1903 .Case("oland", GK_SOUTHERN_ISLANDS) 1904 .Case("hainan", GK_SOUTHERN_ISLANDS) 1905 .Case("bonaire", GK_SEA_ISLANDS) 1906 .Case("kabini", GK_SEA_ISLANDS) 1907 .Case("kaveri", GK_SEA_ISLANDS) 1908 .Case("hawaii", GK_SEA_ISLANDS) 1909 .Case("mullins", GK_SEA_ISLANDS) 1910 .Case("tonga", GK_VOLCANIC_ISLANDS) 1911 .Case("iceland", GK_VOLCANIC_ISLANDS) 1912 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1913 .Case("fiji", GK_VOLCANIC_ISLANDS) 1914 .Case("stoney", GK_VOLCANIC_ISLANDS) 1915 .Default(GK_NONE); 1916 1917 if (GPU == GK_NONE) { 1918 return false; 1919 } 1920 1921 // Set the correct data layout 1922 switch (GPU) { 1923 case GK_NONE: 1924 case GK_R600: 1925 case GK_R700: 1926 case GK_EVERGREEN: 1927 case GK_NORTHERN_ISLANDS: 1928 resetDataLayout(DataLayoutStringR600); 1929 hasFP64 = false; 1930 hasFMAF = false; 1931 hasLDEXPF = false; 1932 break; 1933 case GK_R600_DOUBLE_OPS: 1934 case GK_R700_DOUBLE_OPS: 1935 case GK_EVERGREEN_DOUBLE_OPS: 1936 case GK_CAYMAN: 1937 resetDataLayout(DataLayoutStringR600DoubleOps); 1938 hasFP64 = true; 1939 hasFMAF = true; 1940 hasLDEXPF = false; 1941 break; 1942 case GK_SOUTHERN_ISLANDS: 1943 case GK_SEA_ISLANDS: 1944 case GK_VOLCANIC_ISLANDS: 1945 resetDataLayout(DataLayoutStringSI); 1946 hasFP64 = true; 1947 hasFMAF = true; 1948 hasLDEXPF = true; 1949 break; 1950 } 1951 1952 return true; 1953 } 1954 }; 1955 1956 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1957 #define BUILTIN(ID, TYPE, ATTRS) \ 1958 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1959 #include "clang/Basic/BuiltinsAMDGPU.def" 1960 }; 1961 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1962 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1963 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1964 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1965 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1966 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1967 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1968 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1969 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1970 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1971 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1972 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1973 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1974 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1975 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1976 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1977 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1978 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1979 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1980 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1981 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 1982 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 1983 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 1984 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 1985 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 1986 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 1987 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 1988 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 1989 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 1990 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 1991 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 1992 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 1993 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 1994 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 1995 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 1996 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 1997 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 1998 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 1999 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2000 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2001 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2002 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2003 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2004 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2005 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2006 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2007 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2008 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2009 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127" 2010 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2011 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2012 }; 2013 2014 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2015 return llvm::makeArrayRef(GCCRegNames); 2016 } 2017 2018 // Namespace for x86 abstract base class 2019 const Builtin::Info BuiltinInfo[] = { 2020 #define BUILTIN(ID, TYPE, ATTRS) \ 2021 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2022 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2023 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2024 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2025 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2026 #include "clang/Basic/BuiltinsX86.def" 2027 }; 2028 2029 static const char* const GCCRegNames[] = { 2030 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2031 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2032 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2033 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2034 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2035 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2036 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2037 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2038 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2039 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2040 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2041 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2042 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2043 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2044 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2045 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2046 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2047 }; 2048 2049 const TargetInfo::AddlRegName AddlRegNames[] = { 2050 { { "al", "ah", "eax", "rax" }, 0 }, 2051 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2052 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2053 { { "dl", "dh", "edx", "rdx" }, 1 }, 2054 { { "esi", "rsi" }, 4 }, 2055 { { "edi", "rdi" }, 5 }, 2056 { { "esp", "rsp" }, 7 }, 2057 { { "ebp", "rbp" }, 6 }, 2058 { { "r8d", "r8w", "r8b" }, 38 }, 2059 { { "r9d", "r9w", "r9b" }, 39 }, 2060 { { "r10d", "r10w", "r10b" }, 40 }, 2061 { { "r11d", "r11w", "r11b" }, 41 }, 2062 { { "r12d", "r12w", "r12b" }, 42 }, 2063 { { "r13d", "r13w", "r13b" }, 43 }, 2064 { { "r14d", "r14w", "r14b" }, 44 }, 2065 { { "r15d", "r15w", "r15b" }, 45 }, 2066 }; 2067 2068 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2069 // most of the implementation can be shared. 2070 class X86TargetInfo : public TargetInfo { 2071 enum X86SSEEnum { 2072 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2073 } SSELevel = NoSSE; 2074 enum MMX3DNowEnum { 2075 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2076 } MMX3DNowLevel = NoMMX3DNow; 2077 enum XOPEnum { 2078 NoXOP, 2079 SSE4A, 2080 FMA4, 2081 XOP 2082 } XOPLevel = NoXOP; 2083 2084 bool HasAES = false; 2085 bool HasPCLMUL = false; 2086 bool HasLZCNT = false; 2087 bool HasRDRND = false; 2088 bool HasFSGSBASE = false; 2089 bool HasBMI = false; 2090 bool HasBMI2 = false; 2091 bool HasPOPCNT = false; 2092 bool HasRTM = false; 2093 bool HasPRFCHW = false; 2094 bool HasRDSEED = false; 2095 bool HasADX = false; 2096 bool HasTBM = false; 2097 bool HasFMA = false; 2098 bool HasF16C = false; 2099 bool HasAVX512CD = false; 2100 bool HasAVX512ER = false; 2101 bool HasAVX512PF = false; 2102 bool HasAVX512DQ = false; 2103 bool HasAVX512BW = false; 2104 bool HasAVX512VL = false; 2105 bool HasAVX512VBMI = false; 2106 bool HasAVX512IFMA = false; 2107 bool HasSHA = false; 2108 bool HasMPX = false; 2109 bool HasSGX = false; 2110 bool HasCX16 = false; 2111 bool HasFXSR = false; 2112 bool HasXSAVE = false; 2113 bool HasXSAVEOPT = false; 2114 bool HasXSAVEC = false; 2115 bool HasXSAVES = false; 2116 bool HasPKU = false; 2117 bool HasCLFLUSHOPT = false; 2118 bool HasPCOMMIT = false; 2119 bool HasCLWB = false; 2120 bool HasUMIP = false; 2121 bool HasMOVBE = false; 2122 bool HasPREFETCHWT1 = false; 2123 2124 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2125 /// 2126 /// Each enumeration represents a particular CPU supported by Clang. These 2127 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2128 enum CPUKind { 2129 CK_Generic, 2130 2131 /// \name i386 2132 /// i386-generation processors. 2133 //@{ 2134 CK_i386, 2135 //@} 2136 2137 /// \name i486 2138 /// i486-generation processors. 2139 //@{ 2140 CK_i486, 2141 CK_WinChipC6, 2142 CK_WinChip2, 2143 CK_C3, 2144 //@} 2145 2146 /// \name i586 2147 /// i586-generation processors, P5 microarchitecture based. 2148 //@{ 2149 CK_i586, 2150 CK_Pentium, 2151 CK_PentiumMMX, 2152 //@} 2153 2154 /// \name i686 2155 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2156 //@{ 2157 CK_i686, 2158 CK_PentiumPro, 2159 CK_Pentium2, 2160 CK_Pentium3, 2161 CK_Pentium3M, 2162 CK_PentiumM, 2163 CK_C3_2, 2164 2165 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2166 /// Clang however has some logic to suport this. 2167 // FIXME: Warn, deprecate, and potentially remove this. 2168 CK_Yonah, 2169 //@} 2170 2171 /// \name Netburst 2172 /// Netburst microarchitecture based processors. 2173 //@{ 2174 CK_Pentium4, 2175 CK_Pentium4M, 2176 CK_Prescott, 2177 CK_Nocona, 2178 //@} 2179 2180 /// \name Core 2181 /// Core microarchitecture based processors. 2182 //@{ 2183 CK_Core2, 2184 2185 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2186 /// codename which GCC no longer accepts as an option to -march, but Clang 2187 /// has some logic for recognizing it. 2188 // FIXME: Warn, deprecate, and potentially remove this. 2189 CK_Penryn, 2190 //@} 2191 2192 /// \name Atom 2193 /// Atom processors 2194 //@{ 2195 CK_Bonnell, 2196 CK_Silvermont, 2197 //@} 2198 2199 /// \name Nehalem 2200 /// Nehalem microarchitecture based processors. 2201 CK_Nehalem, 2202 2203 /// \name Westmere 2204 /// Westmere microarchitecture based processors. 2205 CK_Westmere, 2206 2207 /// \name Sandy Bridge 2208 /// Sandy Bridge microarchitecture based processors. 2209 CK_SandyBridge, 2210 2211 /// \name Ivy Bridge 2212 /// Ivy Bridge microarchitecture based processors. 2213 CK_IvyBridge, 2214 2215 /// \name Haswell 2216 /// Haswell microarchitecture based processors. 2217 CK_Haswell, 2218 2219 /// \name Broadwell 2220 /// Broadwell microarchitecture based processors. 2221 CK_Broadwell, 2222 2223 /// \name Skylake Client 2224 /// Skylake client microarchitecture based processors. 2225 CK_SkylakeClient, 2226 2227 /// \name Skylake Server 2228 /// Skylake server microarchitecture based processors. 2229 CK_SkylakeServer, 2230 2231 /// \name Cannonlake Client 2232 /// Cannonlake client microarchitecture based processors. 2233 CK_Cannonlake, 2234 2235 /// \name Knights Landing 2236 /// Knights Landing processor. 2237 CK_KNL, 2238 2239 /// \name K6 2240 /// K6 architecture processors. 2241 //@{ 2242 CK_K6, 2243 CK_K6_2, 2244 CK_K6_3, 2245 //@} 2246 2247 /// \name K7 2248 /// K7 architecture processors. 2249 //@{ 2250 CK_Athlon, 2251 CK_AthlonThunderbird, 2252 CK_Athlon4, 2253 CK_AthlonXP, 2254 CK_AthlonMP, 2255 //@} 2256 2257 /// \name K8 2258 /// K8 architecture processors. 2259 //@{ 2260 CK_Athlon64, 2261 CK_Athlon64SSE3, 2262 CK_AthlonFX, 2263 CK_K8, 2264 CK_K8SSE3, 2265 CK_Opteron, 2266 CK_OpteronSSE3, 2267 CK_AMDFAM10, 2268 //@} 2269 2270 /// \name Bobcat 2271 /// Bobcat architecture processors. 2272 //@{ 2273 CK_BTVER1, 2274 CK_BTVER2, 2275 //@} 2276 2277 /// \name Bulldozer 2278 /// Bulldozer architecture processors. 2279 //@{ 2280 CK_BDVER1, 2281 CK_BDVER2, 2282 CK_BDVER3, 2283 CK_BDVER4, 2284 //@} 2285 2286 /// This specification is deprecated and will be removed in the future. 2287 /// Users should prefer \see CK_K8. 2288 // FIXME: Warn on this when the CPU is set to it. 2289 //@{ 2290 CK_x86_64, 2291 //@} 2292 2293 /// \name Geode 2294 /// Geode processors. 2295 //@{ 2296 CK_Geode 2297 //@} 2298 } CPU = CK_Generic; 2299 2300 CPUKind getCPUKind(StringRef CPU) const { 2301 return llvm::StringSwitch<CPUKind>(CPU) 2302 .Case("i386", CK_i386) 2303 .Case("i486", CK_i486) 2304 .Case("winchip-c6", CK_WinChipC6) 2305 .Case("winchip2", CK_WinChip2) 2306 .Case("c3", CK_C3) 2307 .Case("i586", CK_i586) 2308 .Case("pentium", CK_Pentium) 2309 .Case("pentium-mmx", CK_PentiumMMX) 2310 .Case("i686", CK_i686) 2311 .Case("pentiumpro", CK_PentiumPro) 2312 .Case("pentium2", CK_Pentium2) 2313 .Case("pentium3", CK_Pentium3) 2314 .Case("pentium3m", CK_Pentium3M) 2315 .Case("pentium-m", CK_PentiumM) 2316 .Case("c3-2", CK_C3_2) 2317 .Case("yonah", CK_Yonah) 2318 .Case("pentium4", CK_Pentium4) 2319 .Case("pentium4m", CK_Pentium4M) 2320 .Case("prescott", CK_Prescott) 2321 .Case("nocona", CK_Nocona) 2322 .Case("core2", CK_Core2) 2323 .Case("penryn", CK_Penryn) 2324 .Case("bonnell", CK_Bonnell) 2325 .Case("atom", CK_Bonnell) // Legacy name. 2326 .Case("silvermont", CK_Silvermont) 2327 .Case("slm", CK_Silvermont) // Legacy name. 2328 .Case("nehalem", CK_Nehalem) 2329 .Case("corei7", CK_Nehalem) // Legacy name. 2330 .Case("westmere", CK_Westmere) 2331 .Case("sandybridge", CK_SandyBridge) 2332 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2333 .Case("ivybridge", CK_IvyBridge) 2334 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2335 .Case("haswell", CK_Haswell) 2336 .Case("core-avx2", CK_Haswell) // Legacy name. 2337 .Case("broadwell", CK_Broadwell) 2338 .Case("skylake", CK_SkylakeClient) 2339 .Case("skylake-avx512", CK_SkylakeServer) 2340 .Case("skx", CK_SkylakeServer) // Legacy name. 2341 .Case("cannonlake", CK_Cannonlake) 2342 .Case("knl", CK_KNL) 2343 .Case("k6", CK_K6) 2344 .Case("k6-2", CK_K6_2) 2345 .Case("k6-3", CK_K6_3) 2346 .Case("athlon", CK_Athlon) 2347 .Case("athlon-tbird", CK_AthlonThunderbird) 2348 .Case("athlon-4", CK_Athlon4) 2349 .Case("athlon-xp", CK_AthlonXP) 2350 .Case("athlon-mp", CK_AthlonMP) 2351 .Case("athlon64", CK_Athlon64) 2352 .Case("athlon64-sse3", CK_Athlon64SSE3) 2353 .Case("athlon-fx", CK_AthlonFX) 2354 .Case("k8", CK_K8) 2355 .Case("k8-sse3", CK_K8SSE3) 2356 .Case("opteron", CK_Opteron) 2357 .Case("opteron-sse3", CK_OpteronSSE3) 2358 .Case("barcelona", CK_AMDFAM10) 2359 .Case("amdfam10", CK_AMDFAM10) 2360 .Case("btver1", CK_BTVER1) 2361 .Case("btver2", CK_BTVER2) 2362 .Case("bdver1", CK_BDVER1) 2363 .Case("bdver2", CK_BDVER2) 2364 .Case("bdver3", CK_BDVER3) 2365 .Case("bdver4", CK_BDVER4) 2366 .Case("x86-64", CK_x86_64) 2367 .Case("geode", CK_Geode) 2368 .Default(CK_Generic); 2369 } 2370 2371 enum FPMathKind { 2372 FP_Default, 2373 FP_SSE, 2374 FP_387 2375 } FPMath = FP_Default; 2376 2377 public: 2378 X86TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 2379 BigEndian = false; 2380 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2381 } 2382 unsigned getFloatEvalMethod() const override { 2383 // X87 evaluates with 80 bits "long double" precision. 2384 return SSELevel == NoSSE ? 2 : 0; 2385 } 2386 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2387 return llvm::makeArrayRef(BuiltinInfo, 2388 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2389 } 2390 ArrayRef<const char *> getGCCRegNames() const override { 2391 return llvm::makeArrayRef(GCCRegNames); 2392 } 2393 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2394 return None; 2395 } 2396 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2397 return llvm::makeArrayRef(AddlRegNames); 2398 } 2399 bool validateCpuSupports(StringRef Name) const override; 2400 bool validateAsmConstraint(const char *&Name, 2401 TargetInfo::ConstraintInfo &info) const override; 2402 2403 bool validateGlobalRegisterVariable(StringRef RegName, 2404 unsigned RegSize, 2405 bool &HasSizeMismatch) const override { 2406 // esp and ebp are the only 32-bit registers the x86 backend can currently 2407 // handle. 2408 if (RegName.equals("esp") || RegName.equals("ebp")) { 2409 // Check that the register size is 32-bit. 2410 HasSizeMismatch = RegSize != 32; 2411 return true; 2412 } 2413 2414 return false; 2415 } 2416 2417 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2418 2419 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2420 2421 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2422 2423 std::string convertConstraint(const char *&Constraint) const override; 2424 const char *getClobbers() const override { 2425 return "~{dirflag},~{fpsr},~{flags}"; 2426 } 2427 void getTargetDefines(const LangOptions &Opts, 2428 MacroBuilder &Builder) const override; 2429 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2430 bool Enabled); 2431 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2432 bool Enabled); 2433 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2434 bool Enabled); 2435 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2436 StringRef Name, bool Enabled) const override { 2437 setFeatureEnabledImpl(Features, Name, Enabled); 2438 } 2439 // This exists purely to cut down on the number of virtual calls in 2440 // initFeatureMap which calls this repeatedly. 2441 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2442 StringRef Name, bool Enabled); 2443 bool 2444 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2445 StringRef CPU, 2446 const std::vector<std::string> &FeaturesVec) const override; 2447 bool hasFeature(StringRef Feature) const override; 2448 bool handleTargetFeatures(std::vector<std::string> &Features, 2449 DiagnosticsEngine &Diags) override; 2450 StringRef getABI() const override { 2451 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2452 return "avx512"; 2453 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2454 return "avx"; 2455 if (getTriple().getArch() == llvm::Triple::x86 && 2456 MMX3DNowLevel == NoMMX3DNow) 2457 return "no-mmx"; 2458 return ""; 2459 } 2460 bool setCPU(const std::string &Name) override { 2461 CPU = getCPUKind(Name); 2462 2463 // Perform any per-CPU checks necessary to determine if this CPU is 2464 // acceptable. 2465 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2466 // invalid without explaining *why*. 2467 switch (CPU) { 2468 case CK_Generic: 2469 // No processor selected! 2470 return false; 2471 2472 case CK_i386: 2473 case CK_i486: 2474 case CK_WinChipC6: 2475 case CK_WinChip2: 2476 case CK_C3: 2477 case CK_i586: 2478 case CK_Pentium: 2479 case CK_PentiumMMX: 2480 case CK_i686: 2481 case CK_PentiumPro: 2482 case CK_Pentium2: 2483 case CK_Pentium3: 2484 case CK_Pentium3M: 2485 case CK_PentiumM: 2486 case CK_Yonah: 2487 case CK_C3_2: 2488 case CK_Pentium4: 2489 case CK_Pentium4M: 2490 case CK_Prescott: 2491 case CK_K6: 2492 case CK_K6_2: 2493 case CK_K6_3: 2494 case CK_Athlon: 2495 case CK_AthlonThunderbird: 2496 case CK_Athlon4: 2497 case CK_AthlonXP: 2498 case CK_AthlonMP: 2499 case CK_Geode: 2500 // Only accept certain architectures when compiling in 32-bit mode. 2501 if (getTriple().getArch() != llvm::Triple::x86) 2502 return false; 2503 2504 // Fallthrough 2505 case CK_Nocona: 2506 case CK_Core2: 2507 case CK_Penryn: 2508 case CK_Bonnell: 2509 case CK_Silvermont: 2510 case CK_Nehalem: 2511 case CK_Westmere: 2512 case CK_SandyBridge: 2513 case CK_IvyBridge: 2514 case CK_Haswell: 2515 case CK_Broadwell: 2516 case CK_SkylakeClient: 2517 case CK_SkylakeServer: 2518 case CK_Cannonlake: 2519 case CK_KNL: 2520 case CK_Athlon64: 2521 case CK_Athlon64SSE3: 2522 case CK_AthlonFX: 2523 case CK_K8: 2524 case CK_K8SSE3: 2525 case CK_Opteron: 2526 case CK_OpteronSSE3: 2527 case CK_AMDFAM10: 2528 case CK_BTVER1: 2529 case CK_BTVER2: 2530 case CK_BDVER1: 2531 case CK_BDVER2: 2532 case CK_BDVER3: 2533 case CK_BDVER4: 2534 case CK_x86_64: 2535 return true; 2536 } 2537 llvm_unreachable("Unhandled CPU kind"); 2538 } 2539 2540 bool setFPMath(StringRef Name) override; 2541 2542 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2543 // Most of the non-ARM calling conventions are i386 conventions. 2544 switch (CC) { 2545 case CC_X86ThisCall: 2546 case CC_X86FastCall: 2547 case CC_X86StdCall: 2548 case CC_X86VectorCall: 2549 case CC_C: 2550 case CC_Swift: 2551 case CC_X86Pascal: 2552 case CC_IntelOclBicc: 2553 return CCCR_OK; 2554 default: 2555 return CCCR_Warning; 2556 } 2557 } 2558 2559 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2560 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2561 } 2562 2563 bool hasSjLjLowering() const override { 2564 return true; 2565 } 2566 }; 2567 2568 bool X86TargetInfo::setFPMath(StringRef Name) { 2569 if (Name == "387") { 2570 FPMath = FP_387; 2571 return true; 2572 } 2573 if (Name == "sse") { 2574 FPMath = FP_SSE; 2575 return true; 2576 } 2577 return false; 2578 } 2579 2580 bool X86TargetInfo::initFeatureMap( 2581 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2582 const std::vector<std::string> &FeaturesVec) const { 2583 // FIXME: This *really* should not be here. 2584 // X86_64 always has SSE2. 2585 if (getTriple().getArch() == llvm::Triple::x86_64) 2586 setFeatureEnabledImpl(Features, "sse2", true); 2587 2588 switch (getCPUKind(CPU)) { 2589 case CK_Generic: 2590 case CK_i386: 2591 case CK_i486: 2592 case CK_i586: 2593 case CK_Pentium: 2594 case CK_i686: 2595 case CK_PentiumPro: 2596 break; 2597 case CK_PentiumMMX: 2598 case CK_Pentium2: 2599 case CK_K6: 2600 case CK_WinChipC6: 2601 setFeatureEnabledImpl(Features, "mmx", true); 2602 break; 2603 case CK_Pentium3: 2604 case CK_Pentium3M: 2605 case CK_C3_2: 2606 setFeatureEnabledImpl(Features, "sse", true); 2607 setFeatureEnabledImpl(Features, "fxsr", true); 2608 break; 2609 case CK_PentiumM: 2610 case CK_Pentium4: 2611 case CK_Pentium4M: 2612 case CK_x86_64: 2613 setFeatureEnabledImpl(Features, "sse2", true); 2614 setFeatureEnabledImpl(Features, "fxsr", true); 2615 break; 2616 case CK_Yonah: 2617 case CK_Prescott: 2618 case CK_Nocona: 2619 setFeatureEnabledImpl(Features, "sse3", true); 2620 setFeatureEnabledImpl(Features, "fxsr", true); 2621 setFeatureEnabledImpl(Features, "cx16", true); 2622 break; 2623 case CK_Core2: 2624 case CK_Bonnell: 2625 setFeatureEnabledImpl(Features, "ssse3", true); 2626 setFeatureEnabledImpl(Features, "fxsr", true); 2627 setFeatureEnabledImpl(Features, "cx16", true); 2628 break; 2629 case CK_Penryn: 2630 setFeatureEnabledImpl(Features, "sse4.1", true); 2631 setFeatureEnabledImpl(Features, "fxsr", true); 2632 setFeatureEnabledImpl(Features, "cx16", true); 2633 break; 2634 case CK_Cannonlake: 2635 setFeatureEnabledImpl(Features, "avx512ifma", true); 2636 setFeatureEnabledImpl(Features, "avx512vbmi", true); 2637 setFeatureEnabledImpl(Features, "sha", true); 2638 setFeatureEnabledImpl(Features, "umip", true); 2639 // FALLTHROUGH 2640 case CK_SkylakeServer: 2641 setFeatureEnabledImpl(Features, "avx512f", true); 2642 setFeatureEnabledImpl(Features, "avx512cd", true); 2643 setFeatureEnabledImpl(Features, "avx512dq", true); 2644 setFeatureEnabledImpl(Features, "avx512bw", true); 2645 setFeatureEnabledImpl(Features, "avx512vl", true); 2646 setFeatureEnabledImpl(Features, "pku", true); 2647 setFeatureEnabledImpl(Features, "pcommit", true); 2648 setFeatureEnabledImpl(Features, "clwb", true); 2649 // FALLTHROUGH 2650 case CK_SkylakeClient: 2651 setFeatureEnabledImpl(Features, "xsavec", true); 2652 setFeatureEnabledImpl(Features, "xsaves", true); 2653 setFeatureEnabledImpl(Features, "mpx", true); 2654 setFeatureEnabledImpl(Features, "sgx", true); 2655 setFeatureEnabledImpl(Features, "clflushopt", true); 2656 // FALLTHROUGH 2657 case CK_Broadwell: 2658 setFeatureEnabledImpl(Features, "rdseed", true); 2659 setFeatureEnabledImpl(Features, "adx", true); 2660 // FALLTHROUGH 2661 case CK_Haswell: 2662 setFeatureEnabledImpl(Features, "avx2", true); 2663 setFeatureEnabledImpl(Features, "lzcnt", true); 2664 setFeatureEnabledImpl(Features, "bmi", true); 2665 setFeatureEnabledImpl(Features, "bmi2", true); 2666 setFeatureEnabledImpl(Features, "rtm", true); 2667 setFeatureEnabledImpl(Features, "fma", true); 2668 setFeatureEnabledImpl(Features, "movbe", true); 2669 // FALLTHROUGH 2670 case CK_IvyBridge: 2671 setFeatureEnabledImpl(Features, "rdrnd", true); 2672 setFeatureEnabledImpl(Features, "f16c", true); 2673 setFeatureEnabledImpl(Features, "fsgsbase", true); 2674 // FALLTHROUGH 2675 case CK_SandyBridge: 2676 setFeatureEnabledImpl(Features, "avx", true); 2677 setFeatureEnabledImpl(Features, "xsave", true); 2678 setFeatureEnabledImpl(Features, "xsaveopt", true); 2679 // FALLTHROUGH 2680 case CK_Westmere: 2681 case CK_Silvermont: 2682 setFeatureEnabledImpl(Features, "aes", true); 2683 setFeatureEnabledImpl(Features, "pclmul", true); 2684 // FALLTHROUGH 2685 case CK_Nehalem: 2686 setFeatureEnabledImpl(Features, "sse4.2", true); 2687 setFeatureEnabledImpl(Features, "fxsr", true); 2688 setFeatureEnabledImpl(Features, "cx16", true); 2689 break; 2690 case CK_KNL: 2691 setFeatureEnabledImpl(Features, "avx512f", true); 2692 setFeatureEnabledImpl(Features, "avx512cd", true); 2693 setFeatureEnabledImpl(Features, "avx512er", true); 2694 setFeatureEnabledImpl(Features, "avx512pf", true); 2695 setFeatureEnabledImpl(Features, "prefetchwt1", true); 2696 setFeatureEnabledImpl(Features, "fxsr", true); 2697 setFeatureEnabledImpl(Features, "rdseed", true); 2698 setFeatureEnabledImpl(Features, "adx", true); 2699 setFeatureEnabledImpl(Features, "lzcnt", true); 2700 setFeatureEnabledImpl(Features, "bmi", true); 2701 setFeatureEnabledImpl(Features, "bmi2", true); 2702 setFeatureEnabledImpl(Features, "rtm", true); 2703 setFeatureEnabledImpl(Features, "fma", true); 2704 setFeatureEnabledImpl(Features, "rdrnd", true); 2705 setFeatureEnabledImpl(Features, "f16c", true); 2706 setFeatureEnabledImpl(Features, "fsgsbase", true); 2707 setFeatureEnabledImpl(Features, "aes", true); 2708 setFeatureEnabledImpl(Features, "pclmul", true); 2709 setFeatureEnabledImpl(Features, "cx16", true); 2710 setFeatureEnabledImpl(Features, "xsaveopt", true); 2711 setFeatureEnabledImpl(Features, "xsave", true); 2712 setFeatureEnabledImpl(Features, "movbe", true); 2713 break; 2714 case CK_K6_2: 2715 case CK_K6_3: 2716 case CK_WinChip2: 2717 case CK_C3: 2718 setFeatureEnabledImpl(Features, "3dnow", true); 2719 break; 2720 case CK_Athlon: 2721 case CK_AthlonThunderbird: 2722 case CK_Geode: 2723 setFeatureEnabledImpl(Features, "3dnowa", true); 2724 break; 2725 case CK_Athlon4: 2726 case CK_AthlonXP: 2727 case CK_AthlonMP: 2728 setFeatureEnabledImpl(Features, "sse", true); 2729 setFeatureEnabledImpl(Features, "3dnowa", true); 2730 setFeatureEnabledImpl(Features, "fxsr", true); 2731 break; 2732 case CK_K8: 2733 case CK_Opteron: 2734 case CK_Athlon64: 2735 case CK_AthlonFX: 2736 setFeatureEnabledImpl(Features, "sse2", true); 2737 setFeatureEnabledImpl(Features, "3dnowa", true); 2738 setFeatureEnabledImpl(Features, "fxsr", true); 2739 break; 2740 case CK_AMDFAM10: 2741 setFeatureEnabledImpl(Features, "sse4a", true); 2742 setFeatureEnabledImpl(Features, "lzcnt", true); 2743 setFeatureEnabledImpl(Features, "popcnt", true); 2744 // FALLTHROUGH 2745 case CK_K8SSE3: 2746 case CK_OpteronSSE3: 2747 case CK_Athlon64SSE3: 2748 setFeatureEnabledImpl(Features, "sse3", true); 2749 setFeatureEnabledImpl(Features, "3dnowa", true); 2750 setFeatureEnabledImpl(Features, "fxsr", true); 2751 break; 2752 case CK_BTVER2: 2753 setFeatureEnabledImpl(Features, "avx", true); 2754 setFeatureEnabledImpl(Features, "aes", true); 2755 setFeatureEnabledImpl(Features, "pclmul", true); 2756 setFeatureEnabledImpl(Features, "bmi", true); 2757 setFeatureEnabledImpl(Features, "f16c", true); 2758 setFeatureEnabledImpl(Features, "xsaveopt", true); 2759 // FALLTHROUGH 2760 case CK_BTVER1: 2761 setFeatureEnabledImpl(Features, "ssse3", true); 2762 setFeatureEnabledImpl(Features, "sse4a", true); 2763 setFeatureEnabledImpl(Features, "lzcnt", true); 2764 setFeatureEnabledImpl(Features, "popcnt", true); 2765 setFeatureEnabledImpl(Features, "prfchw", true); 2766 setFeatureEnabledImpl(Features, "cx16", true); 2767 setFeatureEnabledImpl(Features, "fxsr", true); 2768 break; 2769 case CK_BDVER4: 2770 setFeatureEnabledImpl(Features, "avx2", true); 2771 setFeatureEnabledImpl(Features, "bmi2", true); 2772 // FALLTHROUGH 2773 case CK_BDVER3: 2774 setFeatureEnabledImpl(Features, "fsgsbase", true); 2775 setFeatureEnabledImpl(Features, "xsaveopt", true); 2776 // FALLTHROUGH 2777 case CK_BDVER2: 2778 setFeatureEnabledImpl(Features, "bmi", true); 2779 setFeatureEnabledImpl(Features, "fma", true); 2780 setFeatureEnabledImpl(Features, "f16c", true); 2781 setFeatureEnabledImpl(Features, "tbm", true); 2782 // FALLTHROUGH 2783 case CK_BDVER1: 2784 // xop implies avx, sse4a and fma4. 2785 setFeatureEnabledImpl(Features, "xop", true); 2786 setFeatureEnabledImpl(Features, "lzcnt", true); 2787 setFeatureEnabledImpl(Features, "aes", true); 2788 setFeatureEnabledImpl(Features, "pclmul", true); 2789 setFeatureEnabledImpl(Features, "prfchw", true); 2790 setFeatureEnabledImpl(Features, "cx16", true); 2791 setFeatureEnabledImpl(Features, "fxsr", true); 2792 setFeatureEnabledImpl(Features, "xsave", true); 2793 break; 2794 } 2795 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 2796 return false; 2797 2798 // Can't do this earlier because we need to be able to explicitly enable 2799 // or disable these features and the things that they depend upon. 2800 2801 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2802 auto I = Features.find("sse4.2"); 2803 if (I != Features.end() && I->getValue() && 2804 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 2805 FeaturesVec.end()) 2806 Features["popcnt"] = true; 2807 2808 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2809 I = Features.find("3dnow"); 2810 if (I != Features.end() && I->getValue() && 2811 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 2812 FeaturesVec.end()) 2813 Features["prfchw"] = true; 2814 2815 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2816 // then enable MMX. 2817 I = Features.find("sse"); 2818 if (I != Features.end() && I->getValue() && 2819 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 2820 FeaturesVec.end()) 2821 Features["mmx"] = true; 2822 2823 return true; 2824 } 2825 2826 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2827 X86SSEEnum Level, bool Enabled) { 2828 if (Enabled) { 2829 switch (Level) { 2830 case AVX512F: 2831 Features["avx512f"] = true; 2832 case AVX2: 2833 Features["avx2"] = true; 2834 case AVX: 2835 Features["avx"] = true; 2836 Features["xsave"] = true; 2837 case SSE42: 2838 Features["sse4.2"] = true; 2839 case SSE41: 2840 Features["sse4.1"] = true; 2841 case SSSE3: 2842 Features["ssse3"] = true; 2843 case SSE3: 2844 Features["sse3"] = true; 2845 case SSE2: 2846 Features["sse2"] = true; 2847 case SSE1: 2848 Features["sse"] = true; 2849 case NoSSE: 2850 break; 2851 } 2852 return; 2853 } 2854 2855 switch (Level) { 2856 case NoSSE: 2857 case SSE1: 2858 Features["sse"] = false; 2859 case SSE2: 2860 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2861 Features["sha"] = false; 2862 case SSE3: 2863 Features["sse3"] = false; 2864 setXOPLevel(Features, NoXOP, false); 2865 case SSSE3: 2866 Features["ssse3"] = false; 2867 case SSE41: 2868 Features["sse4.1"] = false; 2869 case SSE42: 2870 Features["sse4.2"] = false; 2871 case AVX: 2872 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 2873 Features["xsaveopt"] = false; 2874 setXOPLevel(Features, FMA4, false); 2875 case AVX2: 2876 Features["avx2"] = false; 2877 case AVX512F: 2878 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2879 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2880 Features["avx512vl"] = Features["avx512vbmi"] = 2881 Features["avx512ifma"] = false; 2882 } 2883 } 2884 2885 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2886 MMX3DNowEnum Level, bool Enabled) { 2887 if (Enabled) { 2888 switch (Level) { 2889 case AMD3DNowAthlon: 2890 Features["3dnowa"] = true; 2891 case AMD3DNow: 2892 Features["3dnow"] = true; 2893 case MMX: 2894 Features["mmx"] = true; 2895 case NoMMX3DNow: 2896 break; 2897 } 2898 return; 2899 } 2900 2901 switch (Level) { 2902 case NoMMX3DNow: 2903 case MMX: 2904 Features["mmx"] = false; 2905 case AMD3DNow: 2906 Features["3dnow"] = false; 2907 case AMD3DNowAthlon: 2908 Features["3dnowa"] = false; 2909 } 2910 } 2911 2912 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2913 bool Enabled) { 2914 if (Enabled) { 2915 switch (Level) { 2916 case XOP: 2917 Features["xop"] = true; 2918 case FMA4: 2919 Features["fma4"] = true; 2920 setSSELevel(Features, AVX, true); 2921 case SSE4A: 2922 Features["sse4a"] = true; 2923 setSSELevel(Features, SSE3, true); 2924 case NoXOP: 2925 break; 2926 } 2927 return; 2928 } 2929 2930 switch (Level) { 2931 case NoXOP: 2932 case SSE4A: 2933 Features["sse4a"] = false; 2934 case FMA4: 2935 Features["fma4"] = false; 2936 case XOP: 2937 Features["xop"] = false; 2938 } 2939 } 2940 2941 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2942 StringRef Name, bool Enabled) { 2943 // This is a bit of a hack to deal with the sse4 target feature when used 2944 // as part of the target attribute. We handle sse4 correctly everywhere 2945 // else. See below for more information on how we handle the sse4 options. 2946 if (Name != "sse4") 2947 Features[Name] = Enabled; 2948 2949 if (Name == "mmx") { 2950 setMMXLevel(Features, MMX, Enabled); 2951 } else if (Name == "sse") { 2952 setSSELevel(Features, SSE1, Enabled); 2953 } else if (Name == "sse2") { 2954 setSSELevel(Features, SSE2, Enabled); 2955 } else if (Name == "sse3") { 2956 setSSELevel(Features, SSE3, Enabled); 2957 } else if (Name == "ssse3") { 2958 setSSELevel(Features, SSSE3, Enabled); 2959 } else if (Name == "sse4.2") { 2960 setSSELevel(Features, SSE42, Enabled); 2961 } else if (Name == "sse4.1") { 2962 setSSELevel(Features, SSE41, Enabled); 2963 } else if (Name == "3dnow") { 2964 setMMXLevel(Features, AMD3DNow, Enabled); 2965 } else if (Name == "3dnowa") { 2966 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2967 } else if (Name == "aes") { 2968 if (Enabled) 2969 setSSELevel(Features, SSE2, Enabled); 2970 } else if (Name == "pclmul") { 2971 if (Enabled) 2972 setSSELevel(Features, SSE2, Enabled); 2973 } else if (Name == "avx") { 2974 setSSELevel(Features, AVX, Enabled); 2975 } else if (Name == "avx2") { 2976 setSSELevel(Features, AVX2, Enabled); 2977 } else if (Name == "avx512f") { 2978 setSSELevel(Features, AVX512F, Enabled); 2979 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 2980 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 2981 Name == "avx512vbmi" || Name == "avx512ifma") { 2982 if (Enabled) 2983 setSSELevel(Features, AVX512F, Enabled); 2984 } else if (Name == "fma") { 2985 if (Enabled) 2986 setSSELevel(Features, AVX, Enabled); 2987 } else if (Name == "fma4") { 2988 setXOPLevel(Features, FMA4, Enabled); 2989 } else if (Name == "xop") { 2990 setXOPLevel(Features, XOP, Enabled); 2991 } else if (Name == "sse4a") { 2992 setXOPLevel(Features, SSE4A, Enabled); 2993 } else if (Name == "f16c") { 2994 if (Enabled) 2995 setSSELevel(Features, AVX, Enabled); 2996 } else if (Name == "sha") { 2997 if (Enabled) 2998 setSSELevel(Features, SSE2, Enabled); 2999 } else if (Name == "sse4") { 3000 // We can get here via the __target__ attribute since that's not controlled 3001 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3002 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3003 // disabled. 3004 if (Enabled) 3005 setSSELevel(Features, SSE42, Enabled); 3006 else 3007 setSSELevel(Features, SSE41, Enabled); 3008 } else if (Name == "xsave") { 3009 if (!Enabled) 3010 Features["xsaveopt"] = false; 3011 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3012 if (Enabled) 3013 Features["xsave"] = true; 3014 } 3015 } 3016 3017 /// handleTargetFeatures - Perform initialization based on the user 3018 /// configured set of features. 3019 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3020 DiagnosticsEngine &Diags) { 3021 for (const auto &Feature : Features) { 3022 if (Feature[0] != '+') 3023 continue; 3024 3025 if (Feature == "+aes") { 3026 HasAES = true; 3027 } else if (Feature == "+pclmul") { 3028 HasPCLMUL = true; 3029 } else if (Feature == "+lzcnt") { 3030 HasLZCNT = true; 3031 } else if (Feature == "+rdrnd") { 3032 HasRDRND = true; 3033 } else if (Feature == "+fsgsbase") { 3034 HasFSGSBASE = true; 3035 } else if (Feature == "+bmi") { 3036 HasBMI = true; 3037 } else if (Feature == "+bmi2") { 3038 HasBMI2 = true; 3039 } else if (Feature == "+popcnt") { 3040 HasPOPCNT = true; 3041 } else if (Feature == "+rtm") { 3042 HasRTM = true; 3043 } else if (Feature == "+prfchw") { 3044 HasPRFCHW = true; 3045 } else if (Feature == "+rdseed") { 3046 HasRDSEED = true; 3047 } else if (Feature == "+adx") { 3048 HasADX = true; 3049 } else if (Feature == "+tbm") { 3050 HasTBM = true; 3051 } else if (Feature == "+fma") { 3052 HasFMA = true; 3053 } else if (Feature == "+f16c") { 3054 HasF16C = true; 3055 } else if (Feature == "+avx512cd") { 3056 HasAVX512CD = true; 3057 } else if (Feature == "+avx512er") { 3058 HasAVX512ER = true; 3059 } else if (Feature == "+avx512pf") { 3060 HasAVX512PF = true; 3061 } else if (Feature == "+avx512dq") { 3062 HasAVX512DQ = true; 3063 } else if (Feature == "+avx512bw") { 3064 HasAVX512BW = true; 3065 } else if (Feature == "+avx512vl") { 3066 HasAVX512VL = true; 3067 } else if (Feature == "+avx512vbmi") { 3068 HasAVX512VBMI = true; 3069 } else if (Feature == "+avx512ifma") { 3070 HasAVX512IFMA = true; 3071 } else if (Feature == "+sha") { 3072 HasSHA = true; 3073 } else if (Feature == "+mpx") { 3074 HasMPX = true; 3075 } else if (Feature == "+movbe") { 3076 HasMOVBE = true; 3077 } else if (Feature == "+sgx") { 3078 HasSGX = true; 3079 } else if (Feature == "+cx16") { 3080 HasCX16 = true; 3081 } else if (Feature == "+fxsr") { 3082 HasFXSR = true; 3083 } else if (Feature == "+xsave") { 3084 HasXSAVE = true; 3085 } else if (Feature == "+xsaveopt") { 3086 HasXSAVEOPT = true; 3087 } else if (Feature == "+xsavec") { 3088 HasXSAVEC = true; 3089 } else if (Feature == "+xsaves") { 3090 HasXSAVES = true; 3091 } else if (Feature == "+pku") { 3092 HasPKU = true; 3093 } else if (Feature == "+clflushopt") { 3094 HasCLFLUSHOPT = true; 3095 } else if (Feature == "+pcommit") { 3096 HasPCOMMIT = true; 3097 } else if (Feature == "+clwb") { 3098 HasCLWB = true; 3099 } else if (Feature == "+umip") { 3100 HasUMIP = true; 3101 } else if (Feature == "+prefetchwt1") { 3102 HasPREFETCHWT1 = true; 3103 } 3104 3105 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3106 .Case("+avx512f", AVX512F) 3107 .Case("+avx2", AVX2) 3108 .Case("+avx", AVX) 3109 .Case("+sse4.2", SSE42) 3110 .Case("+sse4.1", SSE41) 3111 .Case("+ssse3", SSSE3) 3112 .Case("+sse3", SSE3) 3113 .Case("+sse2", SSE2) 3114 .Case("+sse", SSE1) 3115 .Default(NoSSE); 3116 SSELevel = std::max(SSELevel, Level); 3117 3118 MMX3DNowEnum ThreeDNowLevel = 3119 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3120 .Case("+3dnowa", AMD3DNowAthlon) 3121 .Case("+3dnow", AMD3DNow) 3122 .Case("+mmx", MMX) 3123 .Default(NoMMX3DNow); 3124 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3125 3126 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3127 .Case("+xop", XOP) 3128 .Case("+fma4", FMA4) 3129 .Case("+sse4a", SSE4A) 3130 .Default(NoXOP); 3131 XOPLevel = std::max(XOPLevel, XLevel); 3132 } 3133 3134 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3135 // matches the selected sse level. 3136 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3137 (FPMath == FP_387 && SSELevel >= SSE1)) { 3138 Diags.Report(diag::err_target_unsupported_fpmath) << 3139 (FPMath == FP_SSE ? "sse" : "387"); 3140 return false; 3141 } 3142 3143 SimdDefaultAlign = 3144 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3145 return true; 3146 } 3147 3148 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3149 /// definitions for this particular subtarget. 3150 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3151 MacroBuilder &Builder) const { 3152 // Target identification. 3153 if (getTriple().getArch() == llvm::Triple::x86_64) { 3154 Builder.defineMacro("__amd64__"); 3155 Builder.defineMacro("__amd64"); 3156 Builder.defineMacro("__x86_64"); 3157 Builder.defineMacro("__x86_64__"); 3158 if (getTriple().getArchName() == "x86_64h") { 3159 Builder.defineMacro("__x86_64h"); 3160 Builder.defineMacro("__x86_64h__"); 3161 } 3162 } else { 3163 DefineStd(Builder, "i386", Opts); 3164 } 3165 3166 // Subtarget options. 3167 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3168 // truly should be based on -mtune options. 3169 switch (CPU) { 3170 case CK_Generic: 3171 break; 3172 case CK_i386: 3173 // The rest are coming from the i386 define above. 3174 Builder.defineMacro("__tune_i386__"); 3175 break; 3176 case CK_i486: 3177 case CK_WinChipC6: 3178 case CK_WinChip2: 3179 case CK_C3: 3180 defineCPUMacros(Builder, "i486"); 3181 break; 3182 case CK_PentiumMMX: 3183 Builder.defineMacro("__pentium_mmx__"); 3184 Builder.defineMacro("__tune_pentium_mmx__"); 3185 // Fallthrough 3186 case CK_i586: 3187 case CK_Pentium: 3188 defineCPUMacros(Builder, "i586"); 3189 defineCPUMacros(Builder, "pentium"); 3190 break; 3191 case CK_Pentium3: 3192 case CK_Pentium3M: 3193 case CK_PentiumM: 3194 Builder.defineMacro("__tune_pentium3__"); 3195 // Fallthrough 3196 case CK_Pentium2: 3197 case CK_C3_2: 3198 Builder.defineMacro("__tune_pentium2__"); 3199 // Fallthrough 3200 case CK_PentiumPro: 3201 Builder.defineMacro("__tune_i686__"); 3202 Builder.defineMacro("__tune_pentiumpro__"); 3203 // Fallthrough 3204 case CK_i686: 3205 Builder.defineMacro("__i686"); 3206 Builder.defineMacro("__i686__"); 3207 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3208 Builder.defineMacro("__pentiumpro"); 3209 Builder.defineMacro("__pentiumpro__"); 3210 break; 3211 case CK_Pentium4: 3212 case CK_Pentium4M: 3213 defineCPUMacros(Builder, "pentium4"); 3214 break; 3215 case CK_Yonah: 3216 case CK_Prescott: 3217 case CK_Nocona: 3218 defineCPUMacros(Builder, "nocona"); 3219 break; 3220 case CK_Core2: 3221 case CK_Penryn: 3222 defineCPUMacros(Builder, "core2"); 3223 break; 3224 case CK_Bonnell: 3225 defineCPUMacros(Builder, "atom"); 3226 break; 3227 case CK_Silvermont: 3228 defineCPUMacros(Builder, "slm"); 3229 break; 3230 case CK_Nehalem: 3231 case CK_Westmere: 3232 case CK_SandyBridge: 3233 case CK_IvyBridge: 3234 case CK_Haswell: 3235 case CK_Broadwell: 3236 case CK_SkylakeClient: 3237 // FIXME: Historically, we defined this legacy name, it would be nice to 3238 // remove it at some point. We've never exposed fine-grained names for 3239 // recent primary x86 CPUs, and we should keep it that way. 3240 defineCPUMacros(Builder, "corei7"); 3241 break; 3242 case CK_SkylakeServer: 3243 defineCPUMacros(Builder, "skx"); 3244 break; 3245 case CK_Cannonlake: 3246 break; 3247 case CK_KNL: 3248 defineCPUMacros(Builder, "knl"); 3249 break; 3250 case CK_K6_2: 3251 Builder.defineMacro("__k6_2__"); 3252 Builder.defineMacro("__tune_k6_2__"); 3253 // Fallthrough 3254 case CK_K6_3: 3255 if (CPU != CK_K6_2) { // In case of fallthrough 3256 // FIXME: GCC may be enabling these in cases where some other k6 3257 // architecture is specified but -m3dnow is explicitly provided. The 3258 // exact semantics need to be determined and emulated here. 3259 Builder.defineMacro("__k6_3__"); 3260 Builder.defineMacro("__tune_k6_3__"); 3261 } 3262 // Fallthrough 3263 case CK_K6: 3264 defineCPUMacros(Builder, "k6"); 3265 break; 3266 case CK_Athlon: 3267 case CK_AthlonThunderbird: 3268 case CK_Athlon4: 3269 case CK_AthlonXP: 3270 case CK_AthlonMP: 3271 defineCPUMacros(Builder, "athlon"); 3272 if (SSELevel != NoSSE) { 3273 Builder.defineMacro("__athlon_sse__"); 3274 Builder.defineMacro("__tune_athlon_sse__"); 3275 } 3276 break; 3277 case CK_K8: 3278 case CK_K8SSE3: 3279 case CK_x86_64: 3280 case CK_Opteron: 3281 case CK_OpteronSSE3: 3282 case CK_Athlon64: 3283 case CK_Athlon64SSE3: 3284 case CK_AthlonFX: 3285 defineCPUMacros(Builder, "k8"); 3286 break; 3287 case CK_AMDFAM10: 3288 defineCPUMacros(Builder, "amdfam10"); 3289 break; 3290 case CK_BTVER1: 3291 defineCPUMacros(Builder, "btver1"); 3292 break; 3293 case CK_BTVER2: 3294 defineCPUMacros(Builder, "btver2"); 3295 break; 3296 case CK_BDVER1: 3297 defineCPUMacros(Builder, "bdver1"); 3298 break; 3299 case CK_BDVER2: 3300 defineCPUMacros(Builder, "bdver2"); 3301 break; 3302 case CK_BDVER3: 3303 defineCPUMacros(Builder, "bdver3"); 3304 break; 3305 case CK_BDVER4: 3306 defineCPUMacros(Builder, "bdver4"); 3307 break; 3308 case CK_Geode: 3309 defineCPUMacros(Builder, "geode"); 3310 break; 3311 } 3312 3313 // Target properties. 3314 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3315 3316 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3317 // functions in glibc header files that use FP Stack inline asm which the 3318 // backend can't deal with (PR879). 3319 Builder.defineMacro("__NO_MATH_INLINES"); 3320 3321 if (HasAES) 3322 Builder.defineMacro("__AES__"); 3323 3324 if (HasPCLMUL) 3325 Builder.defineMacro("__PCLMUL__"); 3326 3327 if (HasLZCNT) 3328 Builder.defineMacro("__LZCNT__"); 3329 3330 if (HasRDRND) 3331 Builder.defineMacro("__RDRND__"); 3332 3333 if (HasFSGSBASE) 3334 Builder.defineMacro("__FSGSBASE__"); 3335 3336 if (HasBMI) 3337 Builder.defineMacro("__BMI__"); 3338 3339 if (HasBMI2) 3340 Builder.defineMacro("__BMI2__"); 3341 3342 if (HasPOPCNT) 3343 Builder.defineMacro("__POPCNT__"); 3344 3345 if (HasRTM) 3346 Builder.defineMacro("__RTM__"); 3347 3348 if (HasPRFCHW) 3349 Builder.defineMacro("__PRFCHW__"); 3350 3351 if (HasRDSEED) 3352 Builder.defineMacro("__RDSEED__"); 3353 3354 if (HasADX) 3355 Builder.defineMacro("__ADX__"); 3356 3357 if (HasTBM) 3358 Builder.defineMacro("__TBM__"); 3359 3360 switch (XOPLevel) { 3361 case XOP: 3362 Builder.defineMacro("__XOP__"); 3363 case FMA4: 3364 Builder.defineMacro("__FMA4__"); 3365 case SSE4A: 3366 Builder.defineMacro("__SSE4A__"); 3367 case NoXOP: 3368 break; 3369 } 3370 3371 if (HasFMA) 3372 Builder.defineMacro("__FMA__"); 3373 3374 if (HasF16C) 3375 Builder.defineMacro("__F16C__"); 3376 3377 if (HasAVX512CD) 3378 Builder.defineMacro("__AVX512CD__"); 3379 if (HasAVX512ER) 3380 Builder.defineMacro("__AVX512ER__"); 3381 if (HasAVX512PF) 3382 Builder.defineMacro("__AVX512PF__"); 3383 if (HasAVX512DQ) 3384 Builder.defineMacro("__AVX512DQ__"); 3385 if (HasAVX512BW) 3386 Builder.defineMacro("__AVX512BW__"); 3387 if (HasAVX512VL) 3388 Builder.defineMacro("__AVX512VL__"); 3389 if (HasAVX512VBMI) 3390 Builder.defineMacro("__AVX512VBMI__"); 3391 if (HasAVX512IFMA) 3392 Builder.defineMacro("__AVX512IFMA__"); 3393 3394 if (HasSHA) 3395 Builder.defineMacro("__SHA__"); 3396 3397 if (HasFXSR) 3398 Builder.defineMacro("__FXSR__"); 3399 if (HasXSAVE) 3400 Builder.defineMacro("__XSAVE__"); 3401 if (HasXSAVEOPT) 3402 Builder.defineMacro("__XSAVEOPT__"); 3403 if (HasXSAVEC) 3404 Builder.defineMacro("__XSAVEC__"); 3405 if (HasXSAVES) 3406 Builder.defineMacro("__XSAVES__"); 3407 if (HasPKU) 3408 Builder.defineMacro("__PKU__"); 3409 if (HasCX16) 3410 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3411 3412 // Each case falls through to the previous one here. 3413 switch (SSELevel) { 3414 case AVX512F: 3415 Builder.defineMacro("__AVX512F__"); 3416 case AVX2: 3417 Builder.defineMacro("__AVX2__"); 3418 case AVX: 3419 Builder.defineMacro("__AVX__"); 3420 case SSE42: 3421 Builder.defineMacro("__SSE4_2__"); 3422 case SSE41: 3423 Builder.defineMacro("__SSE4_1__"); 3424 case SSSE3: 3425 Builder.defineMacro("__SSSE3__"); 3426 case SSE3: 3427 Builder.defineMacro("__SSE3__"); 3428 case SSE2: 3429 Builder.defineMacro("__SSE2__"); 3430 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3431 case SSE1: 3432 Builder.defineMacro("__SSE__"); 3433 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3434 case NoSSE: 3435 break; 3436 } 3437 3438 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3439 switch (SSELevel) { 3440 case AVX512F: 3441 case AVX2: 3442 case AVX: 3443 case SSE42: 3444 case SSE41: 3445 case SSSE3: 3446 case SSE3: 3447 case SSE2: 3448 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3449 break; 3450 case SSE1: 3451 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3452 break; 3453 default: 3454 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3455 } 3456 } 3457 3458 // Each case falls through to the previous one here. 3459 switch (MMX3DNowLevel) { 3460 case AMD3DNowAthlon: 3461 Builder.defineMacro("__3dNOW_A__"); 3462 case AMD3DNow: 3463 Builder.defineMacro("__3dNOW__"); 3464 case MMX: 3465 Builder.defineMacro("__MMX__"); 3466 case NoMMX3DNow: 3467 break; 3468 } 3469 3470 if (CPU >= CK_i486) { 3471 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3472 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3473 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3474 } 3475 if (CPU >= CK_i586) 3476 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3477 } 3478 3479 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3480 return llvm::StringSwitch<bool>(Feature) 3481 .Case("aes", HasAES) 3482 .Case("avx", SSELevel >= AVX) 3483 .Case("avx2", SSELevel >= AVX2) 3484 .Case("avx512f", SSELevel >= AVX512F) 3485 .Case("avx512cd", HasAVX512CD) 3486 .Case("avx512er", HasAVX512ER) 3487 .Case("avx512pf", HasAVX512PF) 3488 .Case("avx512dq", HasAVX512DQ) 3489 .Case("avx512bw", HasAVX512BW) 3490 .Case("avx512vl", HasAVX512VL) 3491 .Case("avx512vbmi", HasAVX512VBMI) 3492 .Case("avx512ifma", HasAVX512IFMA) 3493 .Case("bmi", HasBMI) 3494 .Case("bmi2", HasBMI2) 3495 .Case("clflushopt", HasCLFLUSHOPT) 3496 .Case("clwb", HasCLWB) 3497 .Case("cx16", HasCX16) 3498 .Case("f16c", HasF16C) 3499 .Case("fma", HasFMA) 3500 .Case("fma4", XOPLevel >= FMA4) 3501 .Case("fsgsbase", HasFSGSBASE) 3502 .Case("fxsr", HasFXSR) 3503 .Case("lzcnt", HasLZCNT) 3504 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3505 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3506 .Case("mmx", MMX3DNowLevel >= MMX) 3507 .Case("movbe", HasMOVBE) 3508 .Case("mpx", HasMPX) 3509 .Case("pclmul", HasPCLMUL) 3510 .Case("pcommit", HasPCOMMIT) 3511 .Case("pku", HasPKU) 3512 .Case("popcnt", HasPOPCNT) 3513 .Case("prefetchwt1", HasPREFETCHWT1) 3514 .Case("prfchw", HasPRFCHW) 3515 .Case("rdrnd", HasRDRND) 3516 .Case("rdseed", HasRDSEED) 3517 .Case("rtm", HasRTM) 3518 .Case("sgx", HasSGX) 3519 .Case("sha", HasSHA) 3520 .Case("sse", SSELevel >= SSE1) 3521 .Case("sse2", SSELevel >= SSE2) 3522 .Case("sse3", SSELevel >= SSE3) 3523 .Case("ssse3", SSELevel >= SSSE3) 3524 .Case("sse4.1", SSELevel >= SSE41) 3525 .Case("sse4.2", SSELevel >= SSE42) 3526 .Case("sse4a", XOPLevel >= SSE4A) 3527 .Case("tbm", HasTBM) 3528 .Case("umip", HasUMIP) 3529 .Case("x86", true) 3530 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3531 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3532 .Case("xop", XOPLevel >= XOP) 3533 .Case("xsave", HasXSAVE) 3534 .Case("xsavec", HasXSAVEC) 3535 .Case("xsaves", HasXSAVES) 3536 .Case("xsaveopt", HasXSAVEOPT) 3537 .Default(false); 3538 } 3539 3540 // We can't use a generic validation scheme for the features accepted here 3541 // versus subtarget features accepted in the target attribute because the 3542 // bitfield structure that's initialized in the runtime only supports the 3543 // below currently rather than the full range of subtarget features. (See 3544 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3545 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3546 return llvm::StringSwitch<bool>(FeatureStr) 3547 .Case("cmov", true) 3548 .Case("mmx", true) 3549 .Case("popcnt", true) 3550 .Case("sse", true) 3551 .Case("sse2", true) 3552 .Case("sse3", true) 3553 .Case("sse4.1", true) 3554 .Case("sse4.2", true) 3555 .Case("avx", true) 3556 .Case("avx2", true) 3557 .Case("sse4a", true) 3558 .Case("fma4", true) 3559 .Case("xop", true) 3560 .Case("fma", true) 3561 .Case("avx512f", true) 3562 .Case("bmi", true) 3563 .Case("bmi2", true) 3564 .Default(false); 3565 } 3566 3567 bool 3568 X86TargetInfo::validateAsmConstraint(const char *&Name, 3569 TargetInfo::ConstraintInfo &Info) const { 3570 switch (*Name) { 3571 default: return false; 3572 // Constant constraints. 3573 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3574 // instructions. 3575 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3576 // x86_64 instructions. 3577 case 's': 3578 Info.setRequiresImmediate(); 3579 return true; 3580 case 'I': 3581 Info.setRequiresImmediate(0, 31); 3582 return true; 3583 case 'J': 3584 Info.setRequiresImmediate(0, 63); 3585 return true; 3586 case 'K': 3587 Info.setRequiresImmediate(-128, 127); 3588 return true; 3589 case 'L': 3590 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3591 return true; 3592 case 'M': 3593 Info.setRequiresImmediate(0, 3); 3594 return true; 3595 case 'N': 3596 Info.setRequiresImmediate(0, 255); 3597 return true; 3598 case 'O': 3599 Info.setRequiresImmediate(0, 127); 3600 return true; 3601 // Register constraints. 3602 case 'Y': // 'Y' is the first character for several 2-character constraints. 3603 // Shift the pointer to the second character of the constraint. 3604 Name++; 3605 switch (*Name) { 3606 default: 3607 return false; 3608 case '0': // First SSE register. 3609 case 't': // Any SSE register, when SSE2 is enabled. 3610 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3611 case 'm': // Any MMX register, when inter-unit moves enabled. 3612 Info.setAllowsRegister(); 3613 return true; 3614 } 3615 case 'f': // Any x87 floating point stack register. 3616 // Constraint 'f' cannot be used for output operands. 3617 if (Info.ConstraintStr[0] == '=') 3618 return false; 3619 Info.setAllowsRegister(); 3620 return true; 3621 case 'a': // eax. 3622 case 'b': // ebx. 3623 case 'c': // ecx. 3624 case 'd': // edx. 3625 case 'S': // esi. 3626 case 'D': // edi. 3627 case 'A': // edx:eax. 3628 case 't': // Top of floating point stack. 3629 case 'u': // Second from top of floating point stack. 3630 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3631 case 'y': // Any MMX register. 3632 case 'x': // Any SSE register. 3633 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3634 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3635 case 'l': // "Index" registers: any general register that can be used as an 3636 // index in a base+index memory access. 3637 Info.setAllowsRegister(); 3638 return true; 3639 // Floating point constant constraints. 3640 case 'C': // SSE floating point constant. 3641 case 'G': // x87 floating point constant. 3642 return true; 3643 } 3644 } 3645 3646 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3647 unsigned Size) const { 3648 // Strip off constraint modifiers. 3649 while (Constraint[0] == '=' || 3650 Constraint[0] == '+' || 3651 Constraint[0] == '&') 3652 Constraint = Constraint.substr(1); 3653 3654 return validateOperandSize(Constraint, Size); 3655 } 3656 3657 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3658 unsigned Size) const { 3659 return validateOperandSize(Constraint, Size); 3660 } 3661 3662 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3663 unsigned Size) const { 3664 switch (Constraint[0]) { 3665 default: break; 3666 case 'y': 3667 return Size <= 64; 3668 case 'f': 3669 case 't': 3670 case 'u': 3671 return Size <= 128; 3672 case 'x': 3673 if (SSELevel >= AVX512F) 3674 // 512-bit zmm registers can be used if target supports AVX512F. 3675 return Size <= 512U; 3676 else if (SSELevel >= AVX) 3677 // 256-bit ymm registers can be used if target supports AVX. 3678 return Size <= 256U; 3679 return Size <= 128U; 3680 case 'Y': 3681 // 'Y' is the first character for several 2-character constraints. 3682 switch (Constraint[1]) { 3683 default: break; 3684 case 'm': 3685 // 'Ym' is synonymous with 'y'. 3686 return Size <= 64; 3687 case 'i': 3688 case 't': 3689 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3690 if (SSELevel >= AVX512F) 3691 return Size <= 512U; 3692 else if (SSELevel >= AVX) 3693 return Size <= 256U; 3694 return SSELevel >= SSE2 && Size <= 128U; 3695 } 3696 3697 } 3698 3699 return true; 3700 } 3701 3702 std::string 3703 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3704 switch (*Constraint) { 3705 case 'a': return std::string("{ax}"); 3706 case 'b': return std::string("{bx}"); 3707 case 'c': return std::string("{cx}"); 3708 case 'd': return std::string("{dx}"); 3709 case 'S': return std::string("{si}"); 3710 case 'D': return std::string("{di}"); 3711 case 'p': // address 3712 return std::string("im"); 3713 case 't': // top of floating point stack. 3714 return std::string("{st}"); 3715 case 'u': // second from top of floating point stack. 3716 return std::string("{st(1)}"); // second from top of floating point stack. 3717 default: 3718 return std::string(1, *Constraint); 3719 } 3720 } 3721 3722 // X86-32 generic target 3723 class X86_32TargetInfo : public X86TargetInfo { 3724 public: 3725 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3726 DoubleAlign = LongLongAlign = 32; 3727 LongDoubleWidth = 96; 3728 LongDoubleAlign = 32; 3729 SuitableAlign = 128; 3730 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 3731 SizeType = UnsignedInt; 3732 PtrDiffType = SignedInt; 3733 IntPtrType = SignedInt; 3734 RegParmMax = 3; 3735 3736 // Use fpret for all types. 3737 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3738 (1 << TargetInfo::Double) | 3739 (1 << TargetInfo::LongDouble)); 3740 3741 // x86-32 has atomics up to 8 bytes 3742 // FIXME: Check that we actually have cmpxchg8b before setting 3743 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3744 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3745 } 3746 BuiltinVaListKind getBuiltinVaListKind() const override { 3747 return TargetInfo::CharPtrBuiltinVaList; 3748 } 3749 3750 int getEHDataRegisterNumber(unsigned RegNo) const override { 3751 if (RegNo == 0) return 0; 3752 if (RegNo == 1) return 2; 3753 return -1; 3754 } 3755 bool validateOperandSize(StringRef Constraint, 3756 unsigned Size) const override { 3757 switch (Constraint[0]) { 3758 default: break; 3759 case 'R': 3760 case 'q': 3761 case 'Q': 3762 case 'a': 3763 case 'b': 3764 case 'c': 3765 case 'd': 3766 case 'S': 3767 case 'D': 3768 return Size <= 32; 3769 case 'A': 3770 return Size <= 64; 3771 } 3772 3773 return X86TargetInfo::validateOperandSize(Constraint, Size); 3774 } 3775 }; 3776 3777 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3778 public: 3779 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3780 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3781 3782 unsigned getFloatEvalMethod() const override { 3783 unsigned Major, Minor, Micro; 3784 getTriple().getOSVersion(Major, Minor, Micro); 3785 // New NetBSD uses the default rounding mode. 3786 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3787 return X86_32TargetInfo::getFloatEvalMethod(); 3788 // NetBSD before 6.99.26 defaults to "double" rounding. 3789 return 1; 3790 } 3791 }; 3792 3793 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3794 public: 3795 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3796 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3797 SizeType = UnsignedLong; 3798 IntPtrType = SignedLong; 3799 PtrDiffType = SignedLong; 3800 } 3801 }; 3802 3803 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3804 public: 3805 BitrigI386TargetInfo(const llvm::Triple &Triple) 3806 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3807 SizeType = UnsignedLong; 3808 IntPtrType = SignedLong; 3809 PtrDiffType = SignedLong; 3810 } 3811 }; 3812 3813 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3814 public: 3815 DarwinI386TargetInfo(const llvm::Triple &Triple) 3816 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3817 LongDoubleWidth = 128; 3818 LongDoubleAlign = 128; 3819 SuitableAlign = 128; 3820 MaxVectorAlign = 256; 3821 // The watchOS simulator uses the builtin bool type for Objective-C. 3822 llvm::Triple T = llvm::Triple(Triple); 3823 if (T.isWatchOS()) 3824 UseSignedCharForObjCBool = false; 3825 SizeType = UnsignedLong; 3826 IntPtrType = SignedLong; 3827 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 3828 HasAlignMac68kSupport = true; 3829 } 3830 3831 bool handleTargetFeatures(std::vector<std::string> &Features, 3832 DiagnosticsEngine &Diags) override { 3833 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 3834 Diags)) 3835 return false; 3836 // We now know the features we have: we can decide how to align vectors. 3837 MaxVectorAlign = 3838 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3839 return true; 3840 } 3841 }; 3842 3843 // x86-32 Windows target 3844 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3845 public: 3846 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3847 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3848 WCharType = UnsignedShort; 3849 DoubleAlign = LongLongAlign = 64; 3850 bool IsWinCOFF = 3851 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3852 resetDataLayout(IsWinCOFF 3853 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3854 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 3855 } 3856 void getTargetDefines(const LangOptions &Opts, 3857 MacroBuilder &Builder) const override { 3858 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3859 } 3860 }; 3861 3862 // x86-32 Windows Visual Studio target 3863 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3864 public: 3865 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3866 : WindowsX86_32TargetInfo(Triple) { 3867 LongDoubleWidth = LongDoubleAlign = 64; 3868 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3869 } 3870 void getTargetDefines(const LangOptions &Opts, 3871 MacroBuilder &Builder) const override { 3872 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3873 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3874 // The value of the following reflects processor type. 3875 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3876 // We lost the original triple, so we use the default. 3877 Builder.defineMacro("_M_IX86", "600"); 3878 } 3879 }; 3880 3881 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3882 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 3883 // supports __declspec natively under -fms-extensions, but we define a no-op 3884 // __declspec macro anyway for pre-processor compatibility. 3885 if (Opts.MicrosoftExt) 3886 Builder.defineMacro("__declspec", "__declspec"); 3887 else 3888 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3889 3890 if (!Opts.MicrosoftExt) { 3891 // Provide macros for all the calling convention keywords. Provide both 3892 // single and double underscore prefixed variants. These are available on 3893 // x64 as well as x86, even though they have no effect. 3894 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3895 for (const char *CC : CCs) { 3896 std::string GCCSpelling = "__attribute__((__"; 3897 GCCSpelling += CC; 3898 GCCSpelling += "__))"; 3899 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3900 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3901 } 3902 } 3903 } 3904 3905 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3906 Builder.defineMacro("__MSVCRT__"); 3907 Builder.defineMacro("__MINGW32__"); 3908 addCygMingDefines(Opts, Builder); 3909 } 3910 3911 // x86-32 MinGW target 3912 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3913 public: 3914 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3915 : WindowsX86_32TargetInfo(Triple) {} 3916 void getTargetDefines(const LangOptions &Opts, 3917 MacroBuilder &Builder) const override { 3918 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3919 DefineStd(Builder, "WIN32", Opts); 3920 DefineStd(Builder, "WINNT", Opts); 3921 Builder.defineMacro("_X86_"); 3922 addMinGWDefines(Opts, Builder); 3923 } 3924 }; 3925 3926 // x86-32 Cygwin target 3927 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3928 public: 3929 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3930 : X86_32TargetInfo(Triple) { 3931 WCharType = UnsignedShort; 3932 DoubleAlign = LongLongAlign = 64; 3933 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 3934 } 3935 void getTargetDefines(const LangOptions &Opts, 3936 MacroBuilder &Builder) const override { 3937 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3938 Builder.defineMacro("_X86_"); 3939 Builder.defineMacro("__CYGWIN__"); 3940 Builder.defineMacro("__CYGWIN32__"); 3941 addCygMingDefines(Opts, Builder); 3942 DefineStd(Builder, "unix", Opts); 3943 if (Opts.CPlusPlus) 3944 Builder.defineMacro("_GNU_SOURCE"); 3945 } 3946 }; 3947 3948 // x86-32 Haiku target 3949 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3950 public: 3951 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3952 SizeType = UnsignedLong; 3953 IntPtrType = SignedLong; 3954 PtrDiffType = SignedLong; 3955 ProcessIDType = SignedLong; 3956 this->TLSSupported = false; 3957 } 3958 void getTargetDefines(const LangOptions &Opts, 3959 MacroBuilder &Builder) const override { 3960 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3961 Builder.defineMacro("__INTEL__"); 3962 Builder.defineMacro("__HAIKU__"); 3963 } 3964 }; 3965 3966 // X86-32 MCU target 3967 class MCUX86_32TargetInfo : public X86_32TargetInfo { 3968 public: 3969 MCUX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3970 LongDoubleWidth = 64; 3971 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3972 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 3973 WIntType = UnsignedInt; 3974 } 3975 3976 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3977 // On MCU we support only C calling convention. 3978 return CC == CC_C ? CCCR_OK : CCCR_Warning; 3979 } 3980 3981 void getTargetDefines(const LangOptions &Opts, 3982 MacroBuilder &Builder) const override { 3983 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3984 Builder.defineMacro("__iamcu"); 3985 Builder.defineMacro("__iamcu__"); 3986 } 3987 3988 bool allowsLargerPreferedTypeAlignment() const override { 3989 return false; 3990 } 3991 }; 3992 3993 // RTEMS Target 3994 template<typename Target> 3995 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3996 protected: 3997 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3998 MacroBuilder &Builder) const override { 3999 // RTEMS defines; list based off of gcc output 4000 4001 Builder.defineMacro("__rtems__"); 4002 Builder.defineMacro("__ELF__"); 4003 } 4004 4005 public: 4006 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 4007 switch (Triple.getArch()) { 4008 default: 4009 case llvm::Triple::x86: 4010 // this->MCountName = ".mcount"; 4011 break; 4012 case llvm::Triple::mips: 4013 case llvm::Triple::mipsel: 4014 case llvm::Triple::ppc: 4015 case llvm::Triple::ppc64: 4016 case llvm::Triple::ppc64le: 4017 // this->MCountName = "_mcount"; 4018 break; 4019 case llvm::Triple::arm: 4020 // this->MCountName = "__mcount"; 4021 break; 4022 } 4023 } 4024 }; 4025 4026 // x86-32 RTEMS target 4027 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4028 public: 4029 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 4030 SizeType = UnsignedLong; 4031 IntPtrType = SignedLong; 4032 PtrDiffType = SignedLong; 4033 } 4034 void getTargetDefines(const LangOptions &Opts, 4035 MacroBuilder &Builder) const override { 4036 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4037 Builder.defineMacro("__INTEL__"); 4038 Builder.defineMacro("__rtems__"); 4039 } 4040 }; 4041 4042 // x86-64 generic target 4043 class X86_64TargetInfo : public X86TargetInfo { 4044 public: 4045 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 4046 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4047 bool IsWinCOFF = 4048 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4049 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4050 LongDoubleWidth = 128; 4051 LongDoubleAlign = 128; 4052 LargeArrayMinWidth = 128; 4053 LargeArrayAlign = 128; 4054 SuitableAlign = 128; 4055 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4056 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4057 IntPtrType = IsX32 ? SignedInt : SignedLong; 4058 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4059 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4060 RegParmMax = 6; 4061 4062 // Pointers are 32-bit in x32. 4063 resetDataLayout(IsX32 4064 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4065 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4066 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4067 4068 // Use fpret only for long double. 4069 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4070 4071 // Use fp2ret for _Complex long double. 4072 ComplexLongDoubleUsesFP2Ret = true; 4073 4074 // Make __builtin_ms_va_list available. 4075 HasBuiltinMSVaList = true; 4076 4077 // x86-64 has atomics up to 16 bytes. 4078 MaxAtomicPromoteWidth = 128; 4079 MaxAtomicInlineWidth = 128; 4080 } 4081 BuiltinVaListKind getBuiltinVaListKind() const override { 4082 return TargetInfo::X86_64ABIBuiltinVaList; 4083 } 4084 4085 int getEHDataRegisterNumber(unsigned RegNo) const override { 4086 if (RegNo == 0) return 0; 4087 if (RegNo == 1) return 1; 4088 return -1; 4089 } 4090 4091 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4092 switch (CC) { 4093 case CC_C: 4094 case CC_Swift: 4095 case CC_X86VectorCall: 4096 case CC_IntelOclBicc: 4097 case CC_X86_64Win64: 4098 return CCCR_OK; 4099 default: 4100 return CCCR_Warning; 4101 } 4102 } 4103 4104 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4105 return CC_C; 4106 } 4107 4108 // for x32 we need it here explicitly 4109 bool hasInt128Type() const override { return true; } 4110 unsigned getUnwindWordWidth() const override { return 64; } 4111 unsigned getRegisterWidth() const override { return 64; } 4112 4113 bool validateGlobalRegisterVariable(StringRef RegName, 4114 unsigned RegSize, 4115 bool &HasSizeMismatch) const override { 4116 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4117 // handle. 4118 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4119 // Check that the register size is 64-bit. 4120 HasSizeMismatch = RegSize != 64; 4121 return true; 4122 } 4123 4124 // Check if the register is a 32-bit register the backend can handle. 4125 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4126 HasSizeMismatch); 4127 } 4128 }; 4129 4130 // x86-64 Windows target 4131 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4132 public: 4133 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 4134 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 4135 WCharType = UnsignedShort; 4136 LongWidth = LongAlign = 32; 4137 DoubleAlign = LongLongAlign = 64; 4138 IntMaxType = SignedLongLong; 4139 Int64Type = SignedLongLong; 4140 SizeType = UnsignedLongLong; 4141 PtrDiffType = SignedLongLong; 4142 IntPtrType = SignedLongLong; 4143 } 4144 4145 void getTargetDefines(const LangOptions &Opts, 4146 MacroBuilder &Builder) const override { 4147 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4148 Builder.defineMacro("_WIN64"); 4149 } 4150 4151 BuiltinVaListKind getBuiltinVaListKind() const override { 4152 return TargetInfo::CharPtrBuiltinVaList; 4153 } 4154 4155 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4156 switch (CC) { 4157 case CC_X86StdCall: 4158 case CC_X86ThisCall: 4159 case CC_X86FastCall: 4160 return CCCR_Ignore; 4161 case CC_C: 4162 case CC_X86VectorCall: 4163 case CC_IntelOclBicc: 4164 case CC_X86_64SysV: 4165 return CCCR_OK; 4166 default: 4167 return CCCR_Warning; 4168 } 4169 } 4170 }; 4171 4172 // x86-64 Windows Visual Studio target 4173 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4174 public: 4175 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 4176 : WindowsX86_64TargetInfo(Triple) { 4177 LongDoubleWidth = LongDoubleAlign = 64; 4178 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4179 } 4180 void getTargetDefines(const LangOptions &Opts, 4181 MacroBuilder &Builder) const override { 4182 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4183 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4184 Builder.defineMacro("_M_X64", "100"); 4185 Builder.defineMacro("_M_AMD64", "100"); 4186 } 4187 }; 4188 4189 // x86-64 MinGW target 4190 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4191 public: 4192 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 4193 : WindowsX86_64TargetInfo(Triple) { 4194 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4195 // with x86 FP ops. Weird. 4196 LongDoubleWidth = LongDoubleAlign = 128; 4197 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4198 } 4199 4200 void getTargetDefines(const LangOptions &Opts, 4201 MacroBuilder &Builder) const override { 4202 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4203 DefineStd(Builder, "WIN64", Opts); 4204 Builder.defineMacro("__MINGW64__"); 4205 addMinGWDefines(Opts, Builder); 4206 4207 // GCC defines this macro when it is using __gxx_personality_seh0. 4208 if (!Opts.SjLjExceptions) 4209 Builder.defineMacro("__SEH__"); 4210 } 4211 }; 4212 4213 // x86-64 Cygwin target 4214 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4215 public: 4216 CygwinX86_64TargetInfo(const llvm::Triple &Triple) 4217 : X86_64TargetInfo(Triple) { 4218 TLSSupported = false; 4219 WCharType = UnsignedShort; 4220 } 4221 void getTargetDefines(const LangOptions &Opts, 4222 MacroBuilder &Builder) const override { 4223 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4224 Builder.defineMacro("__x86_64__"); 4225 Builder.defineMacro("__CYGWIN__"); 4226 Builder.defineMacro("__CYGWIN64__"); 4227 addCygMingDefines(Opts, Builder); 4228 DefineStd(Builder, "unix", Opts); 4229 if (Opts.CPlusPlus) 4230 Builder.defineMacro("_GNU_SOURCE"); 4231 4232 // GCC defines this macro when it is using __gxx_personality_seh0. 4233 if (!Opts.SjLjExceptions) 4234 Builder.defineMacro("__SEH__"); 4235 } 4236 }; 4237 4238 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4239 public: 4240 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 4241 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 4242 Int64Type = SignedLongLong; 4243 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4244 llvm::Triple T = llvm::Triple(Triple); 4245 if (T.isiOS()) 4246 UseSignedCharForObjCBool = false; 4247 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4248 } 4249 4250 bool handleTargetFeatures(std::vector<std::string> &Features, 4251 DiagnosticsEngine &Diags) override { 4252 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4253 Diags)) 4254 return false; 4255 // We now know the features we have: we can decide how to align vectors. 4256 MaxVectorAlign = 4257 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4258 return true; 4259 } 4260 }; 4261 4262 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4263 public: 4264 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 4265 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 4266 IntMaxType = SignedLongLong; 4267 Int64Type = SignedLongLong; 4268 } 4269 }; 4270 4271 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4272 public: 4273 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 4274 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 4275 IntMaxType = SignedLongLong; 4276 Int64Type = SignedLongLong; 4277 } 4278 }; 4279 4280 class ARMTargetInfo : public TargetInfo { 4281 // Possible FPU choices. 4282 enum FPUMode { 4283 VFP2FPU = (1 << 0), 4284 VFP3FPU = (1 << 1), 4285 VFP4FPU = (1 << 2), 4286 NeonFPU = (1 << 3), 4287 FPARMV8 = (1 << 4) 4288 }; 4289 4290 // Possible HWDiv features. 4291 enum HWDivMode { 4292 HWDivThumb = (1 << 0), 4293 HWDivARM = (1 << 1) 4294 }; 4295 4296 static bool FPUModeIsVFP(FPUMode Mode) { 4297 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4298 } 4299 4300 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4301 static const char * const GCCRegNames[]; 4302 4303 std::string ABI, CPU; 4304 4305 StringRef CPUProfile; 4306 StringRef CPUAttr; 4307 4308 enum { 4309 FP_Default, 4310 FP_VFP, 4311 FP_Neon 4312 } FPMath; 4313 4314 unsigned ArchISA; 4315 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4316 unsigned ArchProfile; 4317 unsigned ArchVersion; 4318 4319 unsigned FPU : 5; 4320 4321 unsigned IsAAPCS : 1; 4322 unsigned HWDiv : 2; 4323 4324 // Initialized via features. 4325 unsigned SoftFloat : 1; 4326 unsigned SoftFloatABI : 1; 4327 4328 unsigned CRC : 1; 4329 unsigned Crypto : 1; 4330 unsigned DSP : 1; 4331 unsigned Unaligned : 1; 4332 4333 enum { 4334 LDREX_B = (1 << 0), /// byte (8-bit) 4335 LDREX_H = (1 << 1), /// half (16-bit) 4336 LDREX_W = (1 << 2), /// word (32-bit) 4337 LDREX_D = (1 << 3), /// double (64-bit) 4338 }; 4339 4340 uint32_t LDREX; 4341 4342 // ACLE 6.5.1 Hardware floating point 4343 enum { 4344 HW_FP_HP = (1 << 1), /// half (16-bit) 4345 HW_FP_SP = (1 << 2), /// single (32-bit) 4346 HW_FP_DP = (1 << 3), /// double (64-bit) 4347 }; 4348 uint32_t HW_FP; 4349 4350 static const Builtin::Info BuiltinInfo[]; 4351 4352 void setABIAAPCS() { 4353 IsAAPCS = true; 4354 4355 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4356 const llvm::Triple &T = getTriple(); 4357 4358 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4359 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4360 T.getOS() == llvm::Triple::Bitrig) 4361 SizeType = UnsignedLong; 4362 else 4363 SizeType = UnsignedInt; 4364 4365 switch (T.getOS()) { 4366 case llvm::Triple::NetBSD: 4367 WCharType = SignedInt; 4368 break; 4369 case llvm::Triple::Win32: 4370 WCharType = UnsignedShort; 4371 break; 4372 case llvm::Triple::Linux: 4373 default: 4374 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4375 WCharType = UnsignedInt; 4376 break; 4377 } 4378 4379 UseBitFieldTypeAlignment = true; 4380 4381 ZeroLengthBitfieldBoundary = 0; 4382 4383 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4384 // so set preferred for small types to 32. 4385 if (T.isOSBinFormatMachO()) { 4386 resetDataLayout(BigEndian 4387 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4388 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4389 } else if (T.isOSWindows()) { 4390 assert(!BigEndian && "Windows on ARM does not support big endian"); 4391 resetDataLayout("e" 4392 "-m:w" 4393 "-p:32:32" 4394 "-i64:64" 4395 "-v128:64:128" 4396 "-a:0:32" 4397 "-n32" 4398 "-S64"); 4399 } else if (T.isOSNaCl()) { 4400 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4401 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4402 } else { 4403 resetDataLayout(BigEndian 4404 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4405 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4406 } 4407 4408 // FIXME: Enumerated types are variable width in straight AAPCS. 4409 } 4410 4411 void setABIAPCS(bool IsAAPCS16) { 4412 const llvm::Triple &T = getTriple(); 4413 4414 IsAAPCS = false; 4415 4416 if (IsAAPCS16) 4417 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4418 else 4419 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4420 4421 // size_t is unsigned int on FreeBSD. 4422 if (T.getOS() == llvm::Triple::FreeBSD) 4423 SizeType = UnsignedInt; 4424 else 4425 SizeType = UnsignedLong; 4426 4427 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4428 WCharType = SignedInt; 4429 4430 // Do not respect the alignment of bit-field types when laying out 4431 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4432 UseBitFieldTypeAlignment = false; 4433 4434 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4435 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4436 /// gcc. 4437 ZeroLengthBitfieldBoundary = 32; 4438 4439 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4440 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4441 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4442 } else if (T.isOSBinFormatMachO()) 4443 resetDataLayout( 4444 BigEndian 4445 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4446 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4447 else 4448 resetDataLayout( 4449 BigEndian 4450 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4451 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4452 4453 // FIXME: Override "preferred align" for double and long long. 4454 } 4455 4456 void setArchInfo() { 4457 StringRef ArchName = getTriple().getArchName(); 4458 4459 ArchISA = llvm::ARM::parseArchISA(ArchName); 4460 CPU = llvm::ARM::getDefaultCPU(ArchName); 4461 unsigned AK = llvm::ARM::parseArch(ArchName); 4462 if (AK != llvm::ARM::AK_INVALID) 4463 ArchKind = AK; 4464 setArchInfo(ArchKind); 4465 } 4466 4467 void setArchInfo(unsigned Kind) { 4468 StringRef SubArch; 4469 4470 // cache TargetParser info 4471 ArchKind = Kind; 4472 SubArch = llvm::ARM::getSubArch(ArchKind); 4473 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4474 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4475 4476 // cache CPU related strings 4477 CPUAttr = getCPUAttr(); 4478 CPUProfile = getCPUProfile(); 4479 } 4480 4481 void setAtomic() { 4482 // when triple does not specify a sub arch, 4483 // then we are not using inline atomics 4484 bool ShouldUseInlineAtomic = 4485 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4486 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4487 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4488 if (ArchProfile == llvm::ARM::PK_M) { 4489 MaxAtomicPromoteWidth = 32; 4490 if (ShouldUseInlineAtomic) 4491 MaxAtomicInlineWidth = 32; 4492 } 4493 else { 4494 MaxAtomicPromoteWidth = 64; 4495 if (ShouldUseInlineAtomic) 4496 MaxAtomicInlineWidth = 64; 4497 } 4498 } 4499 4500 bool isThumb() const { 4501 return (ArchISA == llvm::ARM::IK_THUMB); 4502 } 4503 4504 bool supportsThumb() const { 4505 return CPUAttr.count('T') || ArchVersion >= 6; 4506 } 4507 4508 bool supportsThumb2() const { 4509 return CPUAttr.equals("6T2") || 4510 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 4511 } 4512 4513 StringRef getCPUAttr() const { 4514 // For most sub-arches, the build attribute CPU name is enough. 4515 // For Cortex variants, it's slightly different. 4516 switch(ArchKind) { 4517 default: 4518 return llvm::ARM::getCPUAttr(ArchKind); 4519 case llvm::ARM::AK_ARMV6M: 4520 return "6M"; 4521 case llvm::ARM::AK_ARMV7S: 4522 return "7S"; 4523 case llvm::ARM::AK_ARMV7A: 4524 return "7A"; 4525 case llvm::ARM::AK_ARMV7R: 4526 return "7R"; 4527 case llvm::ARM::AK_ARMV7M: 4528 return "7M"; 4529 case llvm::ARM::AK_ARMV7EM: 4530 return "7EM"; 4531 case llvm::ARM::AK_ARMV8A: 4532 return "8A"; 4533 case llvm::ARM::AK_ARMV8_1A: 4534 return "8_1A"; 4535 case llvm::ARM::AK_ARMV8_2A: 4536 return "8_2A"; 4537 case llvm::ARM::AK_ARMV8MBaseline: 4538 return "8M_BASE"; 4539 case llvm::ARM::AK_ARMV8MMainline: 4540 return "8M_MAIN"; 4541 } 4542 } 4543 4544 StringRef getCPUProfile() const { 4545 switch(ArchProfile) { 4546 case llvm::ARM::PK_A: 4547 return "A"; 4548 case llvm::ARM::PK_R: 4549 return "R"; 4550 case llvm::ARM::PK_M: 4551 return "M"; 4552 default: 4553 return ""; 4554 } 4555 } 4556 4557 public: 4558 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4559 : TargetInfo(Triple), FPMath(FP_Default), 4560 IsAAPCS(true), LDREX(0), HW_FP(0) { 4561 BigEndian = IsBigEndian; 4562 4563 switch (getTriple().getOS()) { 4564 case llvm::Triple::NetBSD: 4565 PtrDiffType = SignedLong; 4566 break; 4567 default: 4568 PtrDiffType = SignedInt; 4569 break; 4570 } 4571 4572 // Cache arch related info. 4573 setArchInfo(); 4574 4575 // {} in inline assembly are neon specifiers, not assembly variant 4576 // specifiers. 4577 NoAsmVariants = true; 4578 4579 // FIXME: This duplicates code from the driver that sets the -target-abi 4580 // option - this code is used if -target-abi isn't passed and should 4581 // be unified in some way. 4582 if (Triple.isOSBinFormatMachO()) { 4583 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4584 // the frontend matches that. 4585 if (Triple.getEnvironment() == llvm::Triple::EABI || 4586 Triple.getOS() == llvm::Triple::UnknownOS || 4587 StringRef(CPU).startswith("cortex-m")) { 4588 setABI("aapcs"); 4589 } else if (Triple.isWatchABI()) { 4590 setABI("aapcs16"); 4591 } else { 4592 setABI("apcs-gnu"); 4593 } 4594 } else if (Triple.isOSWindows()) { 4595 // FIXME: this is invalid for WindowsCE 4596 setABI("aapcs"); 4597 } else { 4598 // Select the default based on the platform. 4599 switch (Triple.getEnvironment()) { 4600 case llvm::Triple::Android: 4601 case llvm::Triple::GNUEABI: 4602 case llvm::Triple::GNUEABIHF: 4603 setABI("aapcs-linux"); 4604 break; 4605 case llvm::Triple::EABIHF: 4606 case llvm::Triple::EABI: 4607 setABI("aapcs"); 4608 break; 4609 case llvm::Triple::GNU: 4610 setABI("apcs-gnu"); 4611 break; 4612 default: 4613 if (Triple.getOS() == llvm::Triple::NetBSD) 4614 setABI("apcs-gnu"); 4615 else 4616 setABI("aapcs"); 4617 break; 4618 } 4619 } 4620 4621 // ARM targets default to using the ARM C++ ABI. 4622 TheCXXABI.set(TargetCXXABI::GenericARM); 4623 4624 // ARM has atomics up to 8 bytes 4625 setAtomic(); 4626 4627 // Do force alignment of members that follow zero length bitfields. If 4628 // the alignment of the zero-length bitfield is greater than the member 4629 // that follows it, `bar', `bar' will be aligned as the type of the 4630 // zero length bitfield. 4631 UseZeroLengthBitfieldAlignment = true; 4632 } 4633 4634 StringRef getABI() const override { return ABI; } 4635 4636 bool setABI(const std::string &Name) override { 4637 ABI = Name; 4638 4639 // The defaults (above) are for AAPCS, check if we need to change them. 4640 // 4641 // FIXME: We need support for -meabi... we could just mangle it into the 4642 // name. 4643 if (Name == "apcs-gnu" || Name == "aapcs16") { 4644 setABIAPCS(Name == "aapcs16"); 4645 return true; 4646 } 4647 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4648 setABIAAPCS(); 4649 return true; 4650 } 4651 return false; 4652 } 4653 4654 // FIXME: This should be based on Arch attributes, not CPU names. 4655 bool 4656 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4657 StringRef CPU, 4658 const std::vector<std::string> &FeaturesVec) const override { 4659 4660 std::vector<const char*> TargetFeatures; 4661 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4662 4663 // get default FPU features 4664 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4665 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4666 4667 // get default Extension features 4668 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 4669 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4670 4671 for (const char *Feature : TargetFeatures) 4672 if (Feature[0] == '+') 4673 Features[Feature+1] = true; 4674 4675 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4676 } 4677 4678 bool handleTargetFeatures(std::vector<std::string> &Features, 4679 DiagnosticsEngine &Diags) override { 4680 FPU = 0; 4681 CRC = 0; 4682 Crypto = 0; 4683 DSP = 0; 4684 Unaligned = 1; 4685 SoftFloat = SoftFloatABI = false; 4686 HWDiv = 0; 4687 4688 // This does not diagnose illegal cases like having both 4689 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4690 uint32_t HW_FP_remove = 0; 4691 for (const auto &Feature : Features) { 4692 if (Feature == "+soft-float") { 4693 SoftFloat = true; 4694 } else if (Feature == "+soft-float-abi") { 4695 SoftFloatABI = true; 4696 } else if (Feature == "+vfp2") { 4697 FPU |= VFP2FPU; 4698 HW_FP |= HW_FP_SP | HW_FP_DP; 4699 } else if (Feature == "+vfp3") { 4700 FPU |= VFP3FPU; 4701 HW_FP |= HW_FP_SP | HW_FP_DP; 4702 } else if (Feature == "+vfp4") { 4703 FPU |= VFP4FPU; 4704 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4705 } else if (Feature == "+fp-armv8") { 4706 FPU |= FPARMV8; 4707 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4708 } else if (Feature == "+neon") { 4709 FPU |= NeonFPU; 4710 HW_FP |= HW_FP_SP | HW_FP_DP; 4711 } else if (Feature == "+hwdiv") { 4712 HWDiv |= HWDivThumb; 4713 } else if (Feature == "+hwdiv-arm") { 4714 HWDiv |= HWDivARM; 4715 } else if (Feature == "+crc") { 4716 CRC = 1; 4717 } else if (Feature == "+crypto") { 4718 Crypto = 1; 4719 } else if (Feature == "+dsp") { 4720 DSP = 1; 4721 } else if (Feature == "+fp-only-sp") { 4722 HW_FP_remove |= HW_FP_DP; 4723 } else if (Feature == "+strict-align") { 4724 Unaligned = 0; 4725 } else if (Feature == "+fp16") { 4726 HW_FP |= HW_FP_HP; 4727 } 4728 } 4729 HW_FP &= ~HW_FP_remove; 4730 4731 switch (ArchVersion) { 4732 case 6: 4733 if (ArchProfile == llvm::ARM::PK_M) 4734 LDREX = 0; 4735 else if (ArchKind == llvm::ARM::AK_ARMV6K) 4736 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4737 else 4738 LDREX = LDREX_W; 4739 break; 4740 case 7: 4741 if (ArchProfile == llvm::ARM::PK_M) 4742 LDREX = LDREX_W | LDREX_H | LDREX_B ; 4743 else 4744 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4745 break; 4746 case 8: 4747 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4748 } 4749 4750 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4751 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4752 return false; 4753 } 4754 4755 if (FPMath == FP_Neon) 4756 Features.push_back("+neonfp"); 4757 else if (FPMath == FP_VFP) 4758 Features.push_back("-neonfp"); 4759 4760 // Remove front-end specific options which the backend handles differently. 4761 auto Feature = 4762 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4763 if (Feature != Features.end()) 4764 Features.erase(Feature); 4765 4766 return true; 4767 } 4768 4769 bool hasFeature(StringRef Feature) const override { 4770 return llvm::StringSwitch<bool>(Feature) 4771 .Case("arm", true) 4772 .Case("aarch32", true) 4773 .Case("softfloat", SoftFloat) 4774 .Case("thumb", isThumb()) 4775 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4776 .Case("hwdiv", HWDiv & HWDivThumb) 4777 .Case("hwdiv-arm", HWDiv & HWDivARM) 4778 .Default(false); 4779 } 4780 4781 bool setCPU(const std::string &Name) override { 4782 if (Name != "generic") 4783 setArchInfo(llvm::ARM::parseCPUArch(Name)); 4784 4785 if (ArchKind == llvm::ARM::AK_INVALID) 4786 return false; 4787 setAtomic(); 4788 CPU = Name; 4789 return true; 4790 } 4791 4792 bool setFPMath(StringRef Name) override; 4793 4794 void getTargetDefines(const LangOptions &Opts, 4795 MacroBuilder &Builder) const override { 4796 // Target identification. 4797 Builder.defineMacro("__arm"); 4798 Builder.defineMacro("__arm__"); 4799 4800 // Target properties. 4801 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4802 4803 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 4804 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 4805 if (getTriple().isWatchABI()) 4806 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 4807 4808 if (!CPUAttr.empty()) 4809 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 4810 4811 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4812 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4813 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 4814 4815 if (ArchVersion >= 8) { 4816 // ACLE 6.5.7 Crypto Extension 4817 if (Crypto) 4818 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 4819 // ACLE 6.5.8 CRC32 Extension 4820 if (CRC) 4821 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 4822 // ACLE 6.5.10 Numeric Maximum and Minimum 4823 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 4824 // ACLE 6.5.9 Directed Rounding 4825 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 4826 } 4827 4828 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4829 // is not defined for the M-profile. 4830 // NOTE that the default profile is assumed to be 'A' 4831 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 4832 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4833 4834 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 4835 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 4836 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 4837 // v7 and v8 architectures excluding v8-M Baseline. 4838 if (supportsThumb2()) 4839 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4840 else if (supportsThumb()) 4841 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4842 4843 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4844 // instruction set such as ARM or Thumb. 4845 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4846 4847 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4848 4849 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4850 if (!CPUProfile.empty()) 4851 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4852 4853 // ACLE 6.4.3 Unaligned access supported in hardware 4854 if (Unaligned) 4855 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 4856 4857 // ACLE 6.4.4 LDREX/STREX 4858 if (LDREX) 4859 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 4860 4861 // ACLE 6.4.5 CLZ 4862 if (ArchVersion == 5 || 4863 (ArchVersion == 6 && CPUProfile != "M") || 4864 ArchVersion > 6) 4865 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 4866 4867 // ACLE 6.5.1 Hardware Floating Point 4868 if (HW_FP) 4869 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4870 4871 // ACLE predefines. 4872 Builder.defineMacro("__ARM_ACLE", "200"); 4873 4874 // FP16 support (we currently only support IEEE format). 4875 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 4876 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 4877 4878 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 4879 if (ArchVersion >= 7 && (CPUProfile != "M" || CPUAttr == "7EM")) 4880 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 4881 4882 // Subtarget options. 4883 4884 // FIXME: It's more complicated than this and we don't really support 4885 // interworking. 4886 // Windows on ARM does not "support" interworking 4887 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 4888 Builder.defineMacro("__THUMB_INTERWORK__"); 4889 4890 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4891 // Embedded targets on Darwin follow AAPCS, but not EABI. 4892 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4893 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4894 Builder.defineMacro("__ARM_EABI__"); 4895 Builder.defineMacro("__ARM_PCS", "1"); 4896 4897 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4898 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4899 } 4900 4901 if (SoftFloat) 4902 Builder.defineMacro("__SOFTFP__"); 4903 4904 if (CPU == "xscale") 4905 Builder.defineMacro("__XSCALE__"); 4906 4907 if (isThumb()) { 4908 Builder.defineMacro("__THUMBEL__"); 4909 Builder.defineMacro("__thumb__"); 4910 if (supportsThumb2()) 4911 Builder.defineMacro("__thumb2__"); 4912 } 4913 4914 // ACLE 6.4.9 32-bit SIMD instructions 4915 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 4916 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 4917 4918 // ACLE 6.4.10 Hardware Integer Divide 4919 if (((HWDiv & HWDivThumb) && isThumb()) || 4920 ((HWDiv & HWDivARM) && !isThumb())) { 4921 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 4922 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4923 } 4924 4925 // Note, this is always on in gcc, even though it doesn't make sense. 4926 Builder.defineMacro("__APCS_32__"); 4927 4928 if (FPUModeIsVFP((FPUMode) FPU)) { 4929 Builder.defineMacro("__VFP_FP__"); 4930 if (FPU & VFP2FPU) 4931 Builder.defineMacro("__ARM_VFPV2__"); 4932 if (FPU & VFP3FPU) 4933 Builder.defineMacro("__ARM_VFPV3__"); 4934 if (FPU & VFP4FPU) 4935 Builder.defineMacro("__ARM_VFPV4__"); 4936 } 4937 4938 // This only gets set when Neon instructions are actually available, unlike 4939 // the VFP define, hence the soft float and arch check. This is subtly 4940 // different from gcc, we follow the intent which was that it should be set 4941 // when Neon instructions are actually available. 4942 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 4943 Builder.defineMacro("__ARM_NEON", "1"); 4944 Builder.defineMacro("__ARM_NEON__"); 4945 // current AArch32 NEON implementations do not support double-precision 4946 // floating-point even when it is present in VFP. 4947 Builder.defineMacro("__ARM_NEON_FP", 4948 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 4949 } 4950 4951 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4952 Opts.ShortWChar ? "2" : "4"); 4953 4954 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4955 Opts.ShortEnums ? "1" : "4"); 4956 4957 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 4958 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4959 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4960 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4961 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4962 } 4963 4964 // ACLE 6.4.7 DSP instructions 4965 if (DSP) { 4966 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 4967 } 4968 4969 // ACLE 6.4.8 Saturation instructions 4970 bool SAT = false; 4971 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 4972 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 4973 SAT = true; 4974 } 4975 4976 // ACLE 6.4.6 Q (saturation) flag 4977 if (DSP || SAT) 4978 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 4979 4980 if (Opts.UnsafeFPMath) 4981 Builder.defineMacro("__ARM_FP_FAST", "1"); 4982 4983 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 4984 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 4985 } 4986 4987 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4988 return llvm::makeArrayRef(BuiltinInfo, 4989 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 4990 } 4991 bool isCLZForZeroUndef() const override { return false; } 4992 BuiltinVaListKind getBuiltinVaListKind() const override { 4993 return IsAAPCS 4994 ? AAPCSABIBuiltinVaList 4995 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 4996 : TargetInfo::VoidPtrBuiltinVaList); 4997 } 4998 ArrayRef<const char *> getGCCRegNames() const override; 4999 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5000 bool validateAsmConstraint(const char *&Name, 5001 TargetInfo::ConstraintInfo &Info) const override { 5002 switch (*Name) { 5003 default: break; 5004 case 'l': // r0-r7 5005 case 'h': // r8-r15 5006 case 't': // VFP Floating point register single precision 5007 case 'w': // VFP Floating point register double precision 5008 Info.setAllowsRegister(); 5009 return true; 5010 case 'I': 5011 case 'J': 5012 case 'K': 5013 case 'L': 5014 case 'M': 5015 // FIXME 5016 return true; 5017 case 'Q': // A memory address that is a single base register. 5018 Info.setAllowsMemory(); 5019 return true; 5020 case 'U': // a memory reference... 5021 switch (Name[1]) { 5022 case 'q': // ...ARMV4 ldrsb 5023 case 'v': // ...VFP load/store (reg+constant offset) 5024 case 'y': // ...iWMMXt load/store 5025 case 't': // address valid for load/store opaque types wider 5026 // than 128-bits 5027 case 'n': // valid address for Neon doubleword vector load/store 5028 case 'm': // valid address for Neon element and structure load/store 5029 case 's': // valid address for non-offset loads/stores of quad-word 5030 // values in four ARM registers 5031 Info.setAllowsMemory(); 5032 Name++; 5033 return true; 5034 } 5035 } 5036 return false; 5037 } 5038 std::string convertConstraint(const char *&Constraint) const override { 5039 std::string R; 5040 switch (*Constraint) { 5041 case 'U': // Two-character constraint; add "^" hint for later parsing. 5042 R = std::string("^") + std::string(Constraint, 2); 5043 Constraint++; 5044 break; 5045 case 'p': // 'p' should be translated to 'r' by default. 5046 R = std::string("r"); 5047 break; 5048 default: 5049 return std::string(1, *Constraint); 5050 } 5051 return R; 5052 } 5053 bool 5054 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5055 std::string &SuggestedModifier) const override { 5056 bool isOutput = (Constraint[0] == '='); 5057 bool isInOut = (Constraint[0] == '+'); 5058 5059 // Strip off constraint modifiers. 5060 while (Constraint[0] == '=' || 5061 Constraint[0] == '+' || 5062 Constraint[0] == '&') 5063 Constraint = Constraint.substr(1); 5064 5065 switch (Constraint[0]) { 5066 default: break; 5067 case 'r': { 5068 switch (Modifier) { 5069 default: 5070 return (isInOut || isOutput || Size <= 64); 5071 case 'q': 5072 // A register of size 32 cannot fit a vector type. 5073 return false; 5074 } 5075 } 5076 } 5077 5078 return true; 5079 } 5080 const char *getClobbers() const override { 5081 // FIXME: Is this really right? 5082 return ""; 5083 } 5084 5085 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5086 switch (CC) { 5087 case CC_AAPCS: 5088 case CC_AAPCS_VFP: 5089 case CC_Swift: 5090 return CCCR_OK; 5091 default: 5092 return CCCR_Warning; 5093 } 5094 } 5095 5096 int getEHDataRegisterNumber(unsigned RegNo) const override { 5097 if (RegNo == 0) return 0; 5098 if (RegNo == 1) return 1; 5099 return -1; 5100 } 5101 5102 bool hasSjLjLowering() const override { 5103 return true; 5104 } 5105 }; 5106 5107 bool ARMTargetInfo::setFPMath(StringRef Name) { 5108 if (Name == "neon") { 5109 FPMath = FP_Neon; 5110 return true; 5111 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5112 Name == "vfp4") { 5113 FPMath = FP_VFP; 5114 return true; 5115 } 5116 return false; 5117 } 5118 5119 const char * const ARMTargetInfo::GCCRegNames[] = { 5120 // Integer registers 5121 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5122 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5123 5124 // Float registers 5125 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5126 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5127 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5128 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5129 5130 // Double registers 5131 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5132 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5133 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5134 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5135 5136 // Quad registers 5137 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5138 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5139 }; 5140 5141 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5142 return llvm::makeArrayRef(GCCRegNames); 5143 } 5144 5145 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5146 { { "a1" }, "r0" }, 5147 { { "a2" }, "r1" }, 5148 { { "a3" }, "r2" }, 5149 { { "a4" }, "r3" }, 5150 { { "v1" }, "r4" }, 5151 { { "v2" }, "r5" }, 5152 { { "v3" }, "r6" }, 5153 { { "v4" }, "r7" }, 5154 { { "v5" }, "r8" }, 5155 { { "v6", "rfp" }, "r9" }, 5156 { { "sl" }, "r10" }, 5157 { { "fp" }, "r11" }, 5158 { { "ip" }, "r12" }, 5159 { { "r13" }, "sp" }, 5160 { { "r14" }, "lr" }, 5161 { { "r15" }, "pc" }, 5162 // The S, D and Q registers overlap, but aren't really aliases; we 5163 // don't want to substitute one of these for a different-sized one. 5164 }; 5165 5166 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5167 return llvm::makeArrayRef(GCCRegAliases); 5168 } 5169 5170 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5171 #define BUILTIN(ID, TYPE, ATTRS) \ 5172 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5173 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5174 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5175 #include "clang/Basic/BuiltinsNEON.def" 5176 5177 #define BUILTIN(ID, TYPE, ATTRS) \ 5178 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5179 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5180 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5181 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5182 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5183 #include "clang/Basic/BuiltinsARM.def" 5184 }; 5185 5186 class ARMleTargetInfo : public ARMTargetInfo { 5187 public: 5188 ARMleTargetInfo(const llvm::Triple &Triple) 5189 : ARMTargetInfo(Triple, false) { } 5190 void getTargetDefines(const LangOptions &Opts, 5191 MacroBuilder &Builder) const override { 5192 Builder.defineMacro("__ARMEL__"); 5193 ARMTargetInfo::getTargetDefines(Opts, Builder); 5194 } 5195 }; 5196 5197 class ARMbeTargetInfo : public ARMTargetInfo { 5198 public: 5199 ARMbeTargetInfo(const llvm::Triple &Triple) 5200 : ARMTargetInfo(Triple, true) { } 5201 void getTargetDefines(const LangOptions &Opts, 5202 MacroBuilder &Builder) const override { 5203 Builder.defineMacro("__ARMEB__"); 5204 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5205 ARMTargetInfo::getTargetDefines(Opts, Builder); 5206 } 5207 }; 5208 5209 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5210 const llvm::Triple Triple; 5211 public: 5212 WindowsARMTargetInfo(const llvm::Triple &Triple) 5213 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 5214 WCharType = UnsignedShort; 5215 SizeType = UnsignedInt; 5216 } 5217 void getVisualStudioDefines(const LangOptions &Opts, 5218 MacroBuilder &Builder) const { 5219 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5220 5221 // FIXME: this is invalid for WindowsCE 5222 Builder.defineMacro("_M_ARM_NT", "1"); 5223 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5224 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5225 5226 assert((Triple.getArch() == llvm::Triple::arm || 5227 Triple.getArch() == llvm::Triple::thumb) && 5228 "invalid architecture for Windows ARM target info"); 5229 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5230 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5231 5232 // TODO map the complete set of values 5233 // 31: VFPv3 40: VFPv4 5234 Builder.defineMacro("_M_ARM_FP", "31"); 5235 } 5236 BuiltinVaListKind getBuiltinVaListKind() const override { 5237 return TargetInfo::CharPtrBuiltinVaList; 5238 } 5239 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5240 switch (CC) { 5241 case CC_X86StdCall: 5242 case CC_X86ThisCall: 5243 case CC_X86FastCall: 5244 case CC_X86VectorCall: 5245 return CCCR_Ignore; 5246 case CC_C: 5247 return CCCR_OK; 5248 default: 5249 return CCCR_Warning; 5250 } 5251 } 5252 }; 5253 5254 // Windows ARM + Itanium C++ ABI Target 5255 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5256 public: 5257 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 5258 : WindowsARMTargetInfo(Triple) { 5259 TheCXXABI.set(TargetCXXABI::GenericARM); 5260 } 5261 5262 void getTargetDefines(const LangOptions &Opts, 5263 MacroBuilder &Builder) const override { 5264 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5265 5266 if (Opts.MSVCCompat) 5267 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5268 } 5269 }; 5270 5271 // Windows ARM, MS (C++) ABI 5272 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5273 public: 5274 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 5275 : WindowsARMTargetInfo(Triple) { 5276 TheCXXABI.set(TargetCXXABI::Microsoft); 5277 } 5278 5279 void getTargetDefines(const LangOptions &Opts, 5280 MacroBuilder &Builder) const override { 5281 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5282 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5283 } 5284 }; 5285 5286 // ARM MinGW target 5287 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5288 public: 5289 MinGWARMTargetInfo(const llvm::Triple &Triple) 5290 : WindowsARMTargetInfo(Triple) { 5291 TheCXXABI.set(TargetCXXABI::GenericARM); 5292 } 5293 5294 void getTargetDefines(const LangOptions &Opts, 5295 MacroBuilder &Builder) const override { 5296 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5297 DefineStd(Builder, "WIN32", Opts); 5298 DefineStd(Builder, "WINNT", Opts); 5299 Builder.defineMacro("_ARM_"); 5300 addMinGWDefines(Opts, Builder); 5301 } 5302 }; 5303 5304 // ARM Cygwin target 5305 class CygwinARMTargetInfo : public ARMleTargetInfo { 5306 public: 5307 CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) { 5308 TLSSupported = false; 5309 WCharType = UnsignedShort; 5310 DoubleAlign = LongLongAlign = 64; 5311 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5312 } 5313 void getTargetDefines(const LangOptions &Opts, 5314 MacroBuilder &Builder) const override { 5315 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5316 Builder.defineMacro("_ARM_"); 5317 Builder.defineMacro("__CYGWIN__"); 5318 Builder.defineMacro("__CYGWIN32__"); 5319 DefineStd(Builder, "unix", Opts); 5320 if (Opts.CPlusPlus) 5321 Builder.defineMacro("_GNU_SOURCE"); 5322 } 5323 }; 5324 5325 class DarwinARMTargetInfo : 5326 public DarwinTargetInfo<ARMleTargetInfo> { 5327 protected: 5328 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5329 MacroBuilder &Builder) const override { 5330 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5331 } 5332 5333 public: 5334 DarwinARMTargetInfo(const llvm::Triple &Triple) 5335 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 5336 HasAlignMac68kSupport = true; 5337 // iOS always has 64-bit atomic instructions. 5338 // FIXME: This should be based off of the target features in 5339 // ARMleTargetInfo. 5340 MaxAtomicInlineWidth = 64; 5341 5342 if (Triple.isWatchABI()) { 5343 // Darwin on iOS uses a variant of the ARM C++ ABI. 5344 TheCXXABI.set(TargetCXXABI::WatchOS); 5345 5346 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5347 // size_t is long, it's a bit weird for it to be int. 5348 PtrDiffType = SignedLong; 5349 5350 // BOOL should be a real boolean on the new ABI 5351 UseSignedCharForObjCBool = false; 5352 } else 5353 TheCXXABI.set(TargetCXXABI::iOS); 5354 } 5355 }; 5356 5357 class AArch64TargetInfo : public TargetInfo { 5358 virtual void setDataLayout() = 0; 5359 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5360 static const char *const GCCRegNames[]; 5361 5362 enum FPUModeEnum { 5363 FPUMode, 5364 NeonMode 5365 }; 5366 5367 unsigned FPU; 5368 unsigned CRC; 5369 unsigned Crypto; 5370 unsigned Unaligned; 5371 unsigned V8_1A; 5372 5373 static const Builtin::Info BuiltinInfo[]; 5374 5375 std::string ABI; 5376 5377 public: 5378 AArch64TargetInfo(const llvm::Triple &Triple) 5379 : TargetInfo(Triple), ABI("aapcs") { 5380 5381 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5382 WCharType = SignedInt; 5383 5384 // NetBSD apparently prefers consistency across ARM targets to consistency 5385 // across 64-bit targets. 5386 Int64Type = SignedLongLong; 5387 IntMaxType = SignedLongLong; 5388 } else { 5389 WCharType = UnsignedInt; 5390 Int64Type = SignedLong; 5391 IntMaxType = SignedLong; 5392 } 5393 5394 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5395 MaxVectorAlign = 128; 5396 MaxAtomicInlineWidth = 128; 5397 MaxAtomicPromoteWidth = 128; 5398 5399 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5400 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5401 5402 // {} in inline assembly are neon specifiers, not assembly variant 5403 // specifiers. 5404 NoAsmVariants = true; 5405 5406 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5407 // contributes to the alignment of the containing aggregate in the same way 5408 // a plain (non bit-field) member of that type would, without exception for 5409 // zero-sized or anonymous bit-fields." 5410 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5411 UseZeroLengthBitfieldAlignment = true; 5412 5413 // AArch64 targets default to using the ARM C++ ABI. 5414 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5415 } 5416 5417 StringRef getABI() const override { return ABI; } 5418 bool setABI(const std::string &Name) override { 5419 if (Name != "aapcs" && Name != "darwinpcs") 5420 return false; 5421 5422 ABI = Name; 5423 return true; 5424 } 5425 5426 bool setCPU(const std::string &Name) override { 5427 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5428 .Case("generic", true) 5429 .Cases("cortex-a53", "cortex-a57", "cortex-a72", 5430 "cortex-a35", "exynos-m1", true) 5431 .Case("cyclone", true) 5432 .Case("kryo", true) 5433 .Default(false); 5434 return CPUKnown; 5435 } 5436 5437 void getTargetDefines(const LangOptions &Opts, 5438 MacroBuilder &Builder) const override { 5439 // Target identification. 5440 Builder.defineMacro("__aarch64__"); 5441 5442 // Target properties. 5443 Builder.defineMacro("_LP64"); 5444 Builder.defineMacro("__LP64__"); 5445 5446 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5447 Builder.defineMacro("__ARM_ACLE", "200"); 5448 Builder.defineMacro("__ARM_ARCH", "8"); 5449 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5450 5451 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5452 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5453 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5454 5455 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5456 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5457 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5458 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5459 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5460 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5461 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5462 5463 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5464 5465 // 0xe implies support for half, single and double precision operations. 5466 Builder.defineMacro("__ARM_FP", "0xE"); 5467 5468 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5469 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5470 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5471 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5472 5473 if (Opts.UnsafeFPMath) 5474 Builder.defineMacro("__ARM_FP_FAST", "1"); 5475 5476 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5477 5478 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5479 Opts.ShortEnums ? "1" : "4"); 5480 5481 if (FPU == NeonMode) { 5482 Builder.defineMacro("__ARM_NEON", "1"); 5483 // 64-bit NEON supports half, single and double precision operations. 5484 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5485 } 5486 5487 if (CRC) 5488 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5489 5490 if (Crypto) 5491 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5492 5493 if (Unaligned) 5494 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5495 5496 if (V8_1A) 5497 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5498 5499 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5500 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5501 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5502 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5503 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5504 } 5505 5506 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5507 return llvm::makeArrayRef(BuiltinInfo, 5508 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5509 } 5510 5511 bool hasFeature(StringRef Feature) const override { 5512 return Feature == "aarch64" || 5513 Feature == "arm64" || 5514 Feature == "arm" || 5515 (Feature == "neon" && FPU == NeonMode); 5516 } 5517 5518 bool handleTargetFeatures(std::vector<std::string> &Features, 5519 DiagnosticsEngine &Diags) override { 5520 FPU = FPUMode; 5521 CRC = 0; 5522 Crypto = 0; 5523 Unaligned = 1; 5524 V8_1A = 0; 5525 5526 for (const auto &Feature : Features) { 5527 if (Feature == "+neon") 5528 FPU = NeonMode; 5529 if (Feature == "+crc") 5530 CRC = 1; 5531 if (Feature == "+crypto") 5532 Crypto = 1; 5533 if (Feature == "+strict-align") 5534 Unaligned = 0; 5535 if (Feature == "+v8.1a") 5536 V8_1A = 1; 5537 } 5538 5539 setDataLayout(); 5540 5541 return true; 5542 } 5543 5544 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5545 switch (CC) { 5546 case CC_C: 5547 case CC_Swift: 5548 return CCCR_OK; 5549 default: 5550 return CCCR_Warning; 5551 } 5552 } 5553 5554 bool isCLZForZeroUndef() const override { return false; } 5555 5556 BuiltinVaListKind getBuiltinVaListKind() const override { 5557 return TargetInfo::AArch64ABIBuiltinVaList; 5558 } 5559 5560 ArrayRef<const char *> getGCCRegNames() const override; 5561 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5562 5563 bool validateAsmConstraint(const char *&Name, 5564 TargetInfo::ConstraintInfo &Info) const override { 5565 switch (*Name) { 5566 default: 5567 return false; 5568 case 'w': // Floating point and SIMD registers (V0-V31) 5569 Info.setAllowsRegister(); 5570 return true; 5571 case 'I': // Constant that can be used with an ADD instruction 5572 case 'J': // Constant that can be used with a SUB instruction 5573 case 'K': // Constant that can be used with a 32-bit logical instruction 5574 case 'L': // Constant that can be used with a 64-bit logical instruction 5575 case 'M': // Constant that can be used as a 32-bit MOV immediate 5576 case 'N': // Constant that can be used as a 64-bit MOV immediate 5577 case 'Y': // Floating point constant zero 5578 case 'Z': // Integer constant zero 5579 return true; 5580 case 'Q': // A memory reference with base register and no offset 5581 Info.setAllowsMemory(); 5582 return true; 5583 case 'S': // A symbolic address 5584 Info.setAllowsRegister(); 5585 return true; 5586 case 'U': 5587 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5588 // Utf: A memory address suitable for ldp/stp in TF mode. 5589 // Usa: An absolute symbolic address. 5590 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5591 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5592 case 'z': // Zero register, wzr or xzr 5593 Info.setAllowsRegister(); 5594 return true; 5595 case 'x': // Floating point and SIMD registers (V0-V15) 5596 Info.setAllowsRegister(); 5597 return true; 5598 } 5599 return false; 5600 } 5601 5602 bool 5603 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5604 std::string &SuggestedModifier) const override { 5605 // Strip off constraint modifiers. 5606 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5607 Constraint = Constraint.substr(1); 5608 5609 switch (Constraint[0]) { 5610 default: 5611 return true; 5612 case 'z': 5613 case 'r': { 5614 switch (Modifier) { 5615 case 'x': 5616 case 'w': 5617 // For now assume that the person knows what they're 5618 // doing with the modifier. 5619 return true; 5620 default: 5621 // By default an 'r' constraint will be in the 'x' 5622 // registers. 5623 if (Size == 64) 5624 return true; 5625 5626 SuggestedModifier = "w"; 5627 return false; 5628 } 5629 } 5630 } 5631 } 5632 5633 const char *getClobbers() const override { return ""; } 5634 5635 int getEHDataRegisterNumber(unsigned RegNo) const override { 5636 if (RegNo == 0) 5637 return 0; 5638 if (RegNo == 1) 5639 return 1; 5640 return -1; 5641 } 5642 }; 5643 5644 const char *const AArch64TargetInfo::GCCRegNames[] = { 5645 // 32-bit Integer registers 5646 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5647 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5648 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5649 5650 // 64-bit Integer registers 5651 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5652 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5653 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5654 5655 // 32-bit floating point regsisters 5656 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5657 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5658 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5659 5660 // 64-bit floating point regsisters 5661 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5662 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5663 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5664 5665 // Vector registers 5666 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5667 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5668 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5669 }; 5670 5671 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 5672 return llvm::makeArrayRef(GCCRegNames); 5673 } 5674 5675 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5676 { { "w31" }, "wsp" }, 5677 { { "x29" }, "fp" }, 5678 { { "x30" }, "lr" }, 5679 { { "x31" }, "sp" }, 5680 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5681 // don't want to substitute one of these for a different-sized one. 5682 }; 5683 5684 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 5685 return llvm::makeArrayRef(GCCRegAliases); 5686 } 5687 5688 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5689 #define BUILTIN(ID, TYPE, ATTRS) \ 5690 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5691 #include "clang/Basic/BuiltinsNEON.def" 5692 5693 #define BUILTIN(ID, TYPE, ATTRS) \ 5694 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5695 #include "clang/Basic/BuiltinsAArch64.def" 5696 }; 5697 5698 class AArch64leTargetInfo : public AArch64TargetInfo { 5699 void setDataLayout() override { 5700 if (getTriple().isOSBinFormatMachO()) 5701 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 5702 else 5703 resetDataLayout("e-m:e-i64:64-i128:128-n32:64-S128"); 5704 } 5705 5706 public: 5707 AArch64leTargetInfo(const llvm::Triple &Triple) 5708 : AArch64TargetInfo(Triple) { 5709 BigEndian = false; 5710 } 5711 void getTargetDefines(const LangOptions &Opts, 5712 MacroBuilder &Builder) const override { 5713 Builder.defineMacro("__AARCH64EL__"); 5714 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5715 } 5716 }; 5717 5718 class AArch64beTargetInfo : public AArch64TargetInfo { 5719 void setDataLayout() override { 5720 assert(!getTriple().isOSBinFormatMachO()); 5721 resetDataLayout("E-m:e-i64:64-i128:128-n32:64-S128"); 5722 } 5723 5724 public: 5725 AArch64beTargetInfo(const llvm::Triple &Triple) 5726 : AArch64TargetInfo(Triple) { } 5727 void getTargetDefines(const LangOptions &Opts, 5728 MacroBuilder &Builder) const override { 5729 Builder.defineMacro("__AARCH64EB__"); 5730 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5731 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5732 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5733 } 5734 }; 5735 5736 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5737 protected: 5738 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5739 MacroBuilder &Builder) const override { 5740 Builder.defineMacro("__AARCH64_SIMD__"); 5741 Builder.defineMacro("__ARM64_ARCH_8__"); 5742 Builder.defineMacro("__ARM_NEON__"); 5743 Builder.defineMacro("__LITTLE_ENDIAN__"); 5744 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5745 Builder.defineMacro("__arm64", "1"); 5746 Builder.defineMacro("__arm64__", "1"); 5747 5748 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5749 } 5750 5751 public: 5752 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5753 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5754 Int64Type = SignedLongLong; 5755 WCharType = SignedInt; 5756 UseSignedCharForObjCBool = false; 5757 5758 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5759 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5760 5761 TheCXXABI.set(TargetCXXABI::iOS64); 5762 } 5763 5764 BuiltinVaListKind getBuiltinVaListKind() const override { 5765 return TargetInfo::CharPtrBuiltinVaList; 5766 } 5767 }; 5768 5769 // Hexagon abstract base class 5770 class HexagonTargetInfo : public TargetInfo { 5771 static const Builtin::Info BuiltinInfo[]; 5772 static const char * const GCCRegNames[]; 5773 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5774 std::string CPU; 5775 bool HasHVX, HasHVXDouble; 5776 5777 public: 5778 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5779 BigEndian = false; 5780 // Specify the vector alignment explicitly. For v512x1, the calculated 5781 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 5782 // the required minimum of 64 bytes. 5783 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 5784 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 5785 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 5786 SizeType = UnsignedInt; 5787 PtrDiffType = SignedInt; 5788 IntPtrType = SignedInt; 5789 5790 // {} in inline assembly are packet specifiers, not assembly variant 5791 // specifiers. 5792 NoAsmVariants = true; 5793 5794 LargeArrayMinWidth = 64; 5795 LargeArrayAlign = 64; 5796 UseBitFieldTypeAlignment = true; 5797 ZeroLengthBitfieldBoundary = 32; 5798 HasHVX = HasHVXDouble = false; 5799 } 5800 5801 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5802 return llvm::makeArrayRef(BuiltinInfo, 5803 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 5804 } 5805 5806 bool validateAsmConstraint(const char *&Name, 5807 TargetInfo::ConstraintInfo &Info) const override { 5808 return true; 5809 } 5810 5811 void getTargetDefines(const LangOptions &Opts, 5812 MacroBuilder &Builder) const override; 5813 5814 bool isCLZForZeroUndef() const override { return false; } 5815 5816 bool hasFeature(StringRef Feature) const override { 5817 return llvm::StringSwitch<bool>(Feature) 5818 .Case("hexagon", true) 5819 .Case("hvx", HasHVX) 5820 .Case("hvx-double", HasHVXDouble) 5821 .Default(false); 5822 } 5823 5824 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5825 StringRef CPU, const std::vector<std::string> &FeaturesVec) 5826 const override; 5827 5828 bool handleTargetFeatures(std::vector<std::string> &Features, 5829 DiagnosticsEngine &Diags) override; 5830 5831 BuiltinVaListKind getBuiltinVaListKind() const override { 5832 return TargetInfo::CharPtrBuiltinVaList; 5833 } 5834 ArrayRef<const char *> getGCCRegNames() const override; 5835 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5836 const char *getClobbers() const override { 5837 return ""; 5838 } 5839 5840 static const char *getHexagonCPUSuffix(StringRef Name) { 5841 return llvm::StringSwitch<const char*>(Name) 5842 .Case("hexagonv4", "4") 5843 .Case("hexagonv5", "5") 5844 .Case("hexagonv55", "55") 5845 .Case("hexagonv60", "60") 5846 .Default(nullptr); 5847 } 5848 5849 bool setCPU(const std::string &Name) override { 5850 if (!getHexagonCPUSuffix(Name)) 5851 return false; 5852 CPU = Name; 5853 return true; 5854 } 5855 5856 int getEHDataRegisterNumber(unsigned RegNo) const override { 5857 return RegNo < 2 ? RegNo : -1; 5858 } 5859 }; 5860 5861 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5862 MacroBuilder &Builder) const { 5863 Builder.defineMacro("__qdsp6__", "1"); 5864 Builder.defineMacro("__hexagon__", "1"); 5865 5866 if (CPU == "hexagonv4") { 5867 Builder.defineMacro("__HEXAGON_V4__"); 5868 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5869 if (Opts.HexagonQdsp6Compat) { 5870 Builder.defineMacro("__QDSP6_V4__"); 5871 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5872 } 5873 } else if (CPU == "hexagonv5") { 5874 Builder.defineMacro("__HEXAGON_V5__"); 5875 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5876 if(Opts.HexagonQdsp6Compat) { 5877 Builder.defineMacro("__QDSP6_V5__"); 5878 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5879 } 5880 } else if (CPU == "hexagonv60") { 5881 Builder.defineMacro("__HEXAGON_V60__"); 5882 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 5883 Builder.defineMacro("__QDSP6_V60__"); 5884 Builder.defineMacro("__QDSP6_ARCH__", "60"); 5885 } 5886 } 5887 5888 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 5889 DiagnosticsEngine &Diags) { 5890 for (auto &F : Features) { 5891 if (F == "+hvx") 5892 HasHVX = true; 5893 else if (F == "-hvx") 5894 HasHVX = HasHVXDouble = false; 5895 else if (F == "+hvx-double") 5896 HasHVX = HasHVXDouble = true; 5897 else if (F == "-hvx-double") 5898 HasHVXDouble = false; 5899 } 5900 return true; 5901 } 5902 5903 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 5904 DiagnosticsEngine &Diags, StringRef CPU, 5905 const std::vector<std::string> &FeaturesVec) const { 5906 // Default for v60: -hvx, -hvx-double. 5907 Features["hvx"] = false; 5908 Features["hvx-double"] = false; 5909 5910 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5911 } 5912 5913 5914 const char *const HexagonTargetInfo::GCCRegNames[] = { 5915 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5916 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5917 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5918 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5919 "p0", "p1", "p2", "p3", 5920 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5921 }; 5922 5923 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 5924 return llvm::makeArrayRef(GCCRegNames); 5925 } 5926 5927 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5928 { { "sp" }, "r29" }, 5929 { { "fp" }, "r30" }, 5930 { { "lr" }, "r31" }, 5931 }; 5932 5933 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 5934 return llvm::makeArrayRef(GCCRegAliases); 5935 } 5936 5937 5938 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5939 #define BUILTIN(ID, TYPE, ATTRS) \ 5940 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5941 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5942 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5943 #include "clang/Basic/BuiltinsHexagon.def" 5944 }; 5945 5946 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5947 class SparcTargetInfo : public TargetInfo { 5948 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5949 static const char * const GCCRegNames[]; 5950 bool SoftFloat; 5951 public: 5952 SparcTargetInfo(const llvm::Triple &Triple) 5953 : TargetInfo(Triple), SoftFloat(false) {} 5954 5955 int getEHDataRegisterNumber(unsigned RegNo) const override { 5956 if (RegNo == 0) return 24; 5957 if (RegNo == 1) return 25; 5958 return -1; 5959 } 5960 5961 bool handleTargetFeatures(std::vector<std::string> &Features, 5962 DiagnosticsEngine &Diags) override { 5963 // The backend doesn't actually handle soft float yet, but in case someone 5964 // is using the support for the front end continue to support it. 5965 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 5966 if (Feature != Features.end()) { 5967 SoftFloat = true; 5968 Features.erase(Feature); 5969 } 5970 return true; 5971 } 5972 void getTargetDefines(const LangOptions &Opts, 5973 MacroBuilder &Builder) const override { 5974 DefineStd(Builder, "sparc", Opts); 5975 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5976 5977 if (SoftFloat) 5978 Builder.defineMacro("SOFT_FLOAT", "1"); 5979 } 5980 5981 bool hasFeature(StringRef Feature) const override { 5982 return llvm::StringSwitch<bool>(Feature) 5983 .Case("softfloat", SoftFloat) 5984 .Case("sparc", true) 5985 .Default(false); 5986 } 5987 5988 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5989 // FIXME: Implement! 5990 return None; 5991 } 5992 BuiltinVaListKind getBuiltinVaListKind() const override { 5993 return TargetInfo::VoidPtrBuiltinVaList; 5994 } 5995 ArrayRef<const char *> getGCCRegNames() const override; 5996 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5997 bool validateAsmConstraint(const char *&Name, 5998 TargetInfo::ConstraintInfo &info) const override { 5999 // FIXME: Implement! 6000 switch (*Name) { 6001 case 'I': // Signed 13-bit constant 6002 case 'J': // Zero 6003 case 'K': // 32-bit constant with the low 12 bits clear 6004 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6005 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6006 case 'N': // Same as 'K' but zext (required for SIMode) 6007 case 'O': // The constant 4096 6008 return true; 6009 } 6010 return false; 6011 } 6012 const char *getClobbers() const override { 6013 // FIXME: Implement! 6014 return ""; 6015 } 6016 6017 // No Sparc V7 for now, the backend doesn't support it anyway. 6018 enum CPUKind { 6019 CK_GENERIC, 6020 CK_V8, 6021 CK_SUPERSPARC, 6022 CK_SPARCLITE, 6023 CK_F934, 6024 CK_HYPERSPARC, 6025 CK_SPARCLITE86X, 6026 CK_SPARCLET, 6027 CK_TSC701, 6028 CK_V9, 6029 CK_ULTRASPARC, 6030 CK_ULTRASPARC3, 6031 CK_NIAGARA, 6032 CK_NIAGARA2, 6033 CK_NIAGARA3, 6034 CK_NIAGARA4 6035 } CPU = CK_GENERIC; 6036 6037 enum CPUGeneration { 6038 CG_V8, 6039 CG_V9, 6040 }; 6041 6042 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6043 switch (Kind) { 6044 case CK_GENERIC: 6045 case CK_V8: 6046 case CK_SUPERSPARC: 6047 case CK_SPARCLITE: 6048 case CK_F934: 6049 case CK_HYPERSPARC: 6050 case CK_SPARCLITE86X: 6051 case CK_SPARCLET: 6052 case CK_TSC701: 6053 return CG_V8; 6054 case CK_V9: 6055 case CK_ULTRASPARC: 6056 case CK_ULTRASPARC3: 6057 case CK_NIAGARA: 6058 case CK_NIAGARA2: 6059 case CK_NIAGARA3: 6060 case CK_NIAGARA4: 6061 return CG_V9; 6062 } 6063 llvm_unreachable("Unexpected CPU kind"); 6064 } 6065 6066 CPUKind getCPUKind(StringRef Name) const { 6067 return llvm::StringSwitch<CPUKind>(Name) 6068 .Case("v8", CK_V8) 6069 .Case("supersparc", CK_SUPERSPARC) 6070 .Case("sparclite", CK_SPARCLITE) 6071 .Case("f934", CK_F934) 6072 .Case("hypersparc", CK_HYPERSPARC) 6073 .Case("sparclite86x", CK_SPARCLITE86X) 6074 .Case("sparclet", CK_SPARCLET) 6075 .Case("tsc701", CK_TSC701) 6076 .Case("v9", CK_V9) 6077 .Case("ultrasparc", CK_ULTRASPARC) 6078 .Case("ultrasparc3", CK_ULTRASPARC3) 6079 .Case("niagara", CK_NIAGARA) 6080 .Case("niagara2", CK_NIAGARA2) 6081 .Case("niagara3", CK_NIAGARA3) 6082 .Case("niagara4", CK_NIAGARA4) 6083 .Default(CK_GENERIC); 6084 } 6085 6086 bool setCPU(const std::string &Name) override { 6087 CPU = getCPUKind(Name); 6088 return CPU != CK_GENERIC; 6089 } 6090 }; 6091 6092 const char * const SparcTargetInfo::GCCRegNames[] = { 6093 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6094 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6095 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6096 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6097 }; 6098 6099 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6100 return llvm::makeArrayRef(GCCRegNames); 6101 } 6102 6103 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6104 { { "g0" }, "r0" }, 6105 { { "g1" }, "r1" }, 6106 { { "g2" }, "r2" }, 6107 { { "g3" }, "r3" }, 6108 { { "g4" }, "r4" }, 6109 { { "g5" }, "r5" }, 6110 { { "g6" }, "r6" }, 6111 { { "g7" }, "r7" }, 6112 { { "o0" }, "r8" }, 6113 { { "o1" }, "r9" }, 6114 { { "o2" }, "r10" }, 6115 { { "o3" }, "r11" }, 6116 { { "o4" }, "r12" }, 6117 { { "o5" }, "r13" }, 6118 { { "o6", "sp" }, "r14" }, 6119 { { "o7" }, "r15" }, 6120 { { "l0" }, "r16" }, 6121 { { "l1" }, "r17" }, 6122 { { "l2" }, "r18" }, 6123 { { "l3" }, "r19" }, 6124 { { "l4" }, "r20" }, 6125 { { "l5" }, "r21" }, 6126 { { "l6" }, "r22" }, 6127 { { "l7" }, "r23" }, 6128 { { "i0" }, "r24" }, 6129 { { "i1" }, "r25" }, 6130 { { "i2" }, "r26" }, 6131 { { "i3" }, "r27" }, 6132 { { "i4" }, "r28" }, 6133 { { "i5" }, "r29" }, 6134 { { "i6", "fp" }, "r30" }, 6135 { { "i7" }, "r31" }, 6136 }; 6137 6138 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6139 return llvm::makeArrayRef(GCCRegAliases); 6140 } 6141 6142 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6143 class SparcV8TargetInfo : public SparcTargetInfo { 6144 public: 6145 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 6146 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6147 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6148 switch (getTriple().getOS()) { 6149 default: 6150 SizeType = UnsignedInt; 6151 IntPtrType = SignedInt; 6152 PtrDiffType = SignedInt; 6153 break; 6154 case llvm::Triple::NetBSD: 6155 case llvm::Triple::OpenBSD: 6156 SizeType = UnsignedLong; 6157 IntPtrType = SignedLong; 6158 PtrDiffType = SignedLong; 6159 break; 6160 } 6161 } 6162 6163 void getTargetDefines(const LangOptions &Opts, 6164 MacroBuilder &Builder) const override { 6165 SparcTargetInfo::getTargetDefines(Opts, Builder); 6166 switch (getCPUGeneration(CPU)) { 6167 case CG_V8: 6168 Builder.defineMacro("__sparcv8"); 6169 if (getTriple().getOS() != llvm::Triple::Solaris) 6170 Builder.defineMacro("__sparcv8__"); 6171 break; 6172 case CG_V9: 6173 Builder.defineMacro("__sparcv9"); 6174 if (getTriple().getOS() != llvm::Triple::Solaris) { 6175 Builder.defineMacro("__sparcv9__"); 6176 Builder.defineMacro("__sparc_v9__"); 6177 } 6178 break; 6179 } 6180 } 6181 }; 6182 6183 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6184 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6185 public: 6186 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 6187 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6188 BigEndian = false; 6189 } 6190 }; 6191 6192 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6193 class SparcV9TargetInfo : public SparcTargetInfo { 6194 public: 6195 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 6196 // FIXME: Support Sparc quad-precision long double? 6197 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6198 // This is an LP64 platform. 6199 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6200 6201 // OpenBSD uses long long for int64_t and intmax_t. 6202 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6203 IntMaxType = SignedLongLong; 6204 else 6205 IntMaxType = SignedLong; 6206 Int64Type = IntMaxType; 6207 6208 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6209 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6210 LongDoubleWidth = 128; 6211 LongDoubleAlign = 128; 6212 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6213 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6214 } 6215 6216 void getTargetDefines(const LangOptions &Opts, 6217 MacroBuilder &Builder) const override { 6218 SparcTargetInfo::getTargetDefines(Opts, Builder); 6219 Builder.defineMacro("__sparcv9"); 6220 Builder.defineMacro("__arch64__"); 6221 // Solaris doesn't need these variants, but the BSDs do. 6222 if (getTriple().getOS() != llvm::Triple::Solaris) { 6223 Builder.defineMacro("__sparc64__"); 6224 Builder.defineMacro("__sparc_v9__"); 6225 Builder.defineMacro("__sparcv9__"); 6226 } 6227 } 6228 6229 bool setCPU(const std::string &Name) override { 6230 if (!SparcTargetInfo::setCPU(Name)) 6231 return false; 6232 return getCPUGeneration(CPU) == CG_V9; 6233 } 6234 }; 6235 6236 class SystemZTargetInfo : public TargetInfo { 6237 static const Builtin::Info BuiltinInfo[]; 6238 static const char *const GCCRegNames[]; 6239 std::string CPU; 6240 bool HasTransactionalExecution; 6241 bool HasVector; 6242 6243 public: 6244 SystemZTargetInfo(const llvm::Triple &Triple) 6245 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6246 HasVector(false) { 6247 IntMaxType = SignedLong; 6248 Int64Type = SignedLong; 6249 TLSSupported = true; 6250 IntWidth = IntAlign = 32; 6251 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6252 PointerWidth = PointerAlign = 64; 6253 LongDoubleWidth = 128; 6254 LongDoubleAlign = 64; 6255 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6256 DefaultAlignForAttributeAligned = 64; 6257 MinGlobalAlign = 16; 6258 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 6259 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6260 } 6261 void getTargetDefines(const LangOptions &Opts, 6262 MacroBuilder &Builder) const override { 6263 Builder.defineMacro("__s390__"); 6264 Builder.defineMacro("__s390x__"); 6265 Builder.defineMacro("__zarch__"); 6266 Builder.defineMacro("__LONG_DOUBLE_128__"); 6267 6268 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6269 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6270 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6271 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6272 6273 if (HasTransactionalExecution) 6274 Builder.defineMacro("__HTM__"); 6275 if (Opts.ZVector) 6276 Builder.defineMacro("__VEC__", "10301"); 6277 } 6278 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6279 return llvm::makeArrayRef(BuiltinInfo, 6280 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6281 } 6282 6283 ArrayRef<const char *> getGCCRegNames() const override; 6284 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6285 // No aliases. 6286 return None; 6287 } 6288 bool validateAsmConstraint(const char *&Name, 6289 TargetInfo::ConstraintInfo &info) const override; 6290 const char *getClobbers() const override { 6291 // FIXME: Is this really right? 6292 return ""; 6293 } 6294 BuiltinVaListKind getBuiltinVaListKind() const override { 6295 return TargetInfo::SystemZBuiltinVaList; 6296 } 6297 bool setCPU(const std::string &Name) override { 6298 CPU = Name; 6299 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6300 .Case("z10", true) 6301 .Case("z196", true) 6302 .Case("zEC12", true) 6303 .Case("z13", true) 6304 .Default(false); 6305 6306 return CPUKnown; 6307 } 6308 bool 6309 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6310 StringRef CPU, 6311 const std::vector<std::string> &FeaturesVec) const override { 6312 if (CPU == "zEC12") 6313 Features["transactional-execution"] = true; 6314 if (CPU == "z13") { 6315 Features["transactional-execution"] = true; 6316 Features["vector"] = true; 6317 } 6318 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6319 } 6320 6321 bool handleTargetFeatures(std::vector<std::string> &Features, 6322 DiagnosticsEngine &Diags) override { 6323 HasTransactionalExecution = false; 6324 for (const auto &Feature : Features) { 6325 if (Feature == "+transactional-execution") 6326 HasTransactionalExecution = true; 6327 else if (Feature == "+vector") 6328 HasVector = true; 6329 } 6330 // If we use the vector ABI, vector types are 64-bit aligned. 6331 if (HasVector) { 6332 MaxVectorAlign = 64; 6333 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6334 "-v128:64-a:8:16-n32:64"); 6335 } 6336 return true; 6337 } 6338 6339 bool hasFeature(StringRef Feature) const override { 6340 return llvm::StringSwitch<bool>(Feature) 6341 .Case("systemz", true) 6342 .Case("htm", HasTransactionalExecution) 6343 .Case("vx", HasVector) 6344 .Default(false); 6345 } 6346 6347 StringRef getABI() const override { 6348 if (HasVector) 6349 return "vector"; 6350 return ""; 6351 } 6352 6353 bool useFloat128ManglingForLongDouble() const override { 6354 return true; 6355 } 6356 }; 6357 6358 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6359 #define BUILTIN(ID, TYPE, ATTRS) \ 6360 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6361 #include "clang/Basic/BuiltinsSystemZ.def" 6362 }; 6363 6364 const char *const SystemZTargetInfo::GCCRegNames[] = { 6365 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6366 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6367 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6368 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6369 }; 6370 6371 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6372 return llvm::makeArrayRef(GCCRegNames); 6373 } 6374 6375 bool SystemZTargetInfo:: 6376 validateAsmConstraint(const char *&Name, 6377 TargetInfo::ConstraintInfo &Info) const { 6378 switch (*Name) { 6379 default: 6380 return false; 6381 6382 case 'a': // Address register 6383 case 'd': // Data register (equivalent to 'r') 6384 case 'f': // Floating-point register 6385 Info.setAllowsRegister(); 6386 return true; 6387 6388 case 'I': // Unsigned 8-bit constant 6389 case 'J': // Unsigned 12-bit constant 6390 case 'K': // Signed 16-bit constant 6391 case 'L': // Signed 20-bit displacement (on all targets we support) 6392 case 'M': // 0x7fffffff 6393 return true; 6394 6395 case 'Q': // Memory with base and unsigned 12-bit displacement 6396 case 'R': // Likewise, plus an index 6397 case 'S': // Memory with base and signed 20-bit displacement 6398 case 'T': // Likewise, plus an index 6399 Info.setAllowsMemory(); 6400 return true; 6401 } 6402 } 6403 6404 class MSP430TargetInfo : public TargetInfo { 6405 static const char *const GCCRegNames[]; 6406 6407 public: 6408 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6409 BigEndian = false; 6410 TLSSupported = false; 6411 IntWidth = 16; 6412 IntAlign = 16; 6413 LongWidth = 32; 6414 LongLongWidth = 64; 6415 LongAlign = LongLongAlign = 16; 6416 PointerWidth = 16; 6417 PointerAlign = 16; 6418 SuitableAlign = 16; 6419 SizeType = UnsignedInt; 6420 IntMaxType = SignedLongLong; 6421 IntPtrType = SignedInt; 6422 PtrDiffType = SignedInt; 6423 SigAtomicType = SignedLong; 6424 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 6425 } 6426 void getTargetDefines(const LangOptions &Opts, 6427 MacroBuilder &Builder) const override { 6428 Builder.defineMacro("MSP430"); 6429 Builder.defineMacro("__MSP430__"); 6430 // FIXME: defines for different 'flavours' of MCU 6431 } 6432 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6433 // FIXME: Implement. 6434 return None; 6435 } 6436 bool hasFeature(StringRef Feature) const override { 6437 return Feature == "msp430"; 6438 } 6439 ArrayRef<const char *> getGCCRegNames() const override; 6440 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6441 // No aliases. 6442 return None; 6443 } 6444 bool validateAsmConstraint(const char *&Name, 6445 TargetInfo::ConstraintInfo &info) const override { 6446 // FIXME: implement 6447 switch (*Name) { 6448 case 'K': // the constant 1 6449 case 'L': // constant -1^20 .. 1^19 6450 case 'M': // constant 1-4: 6451 return true; 6452 } 6453 // No target constraints for now. 6454 return false; 6455 } 6456 const char *getClobbers() const override { 6457 // FIXME: Is this really right? 6458 return ""; 6459 } 6460 BuiltinVaListKind getBuiltinVaListKind() const override { 6461 // FIXME: implement 6462 return TargetInfo::CharPtrBuiltinVaList; 6463 } 6464 }; 6465 6466 const char *const MSP430TargetInfo::GCCRegNames[] = { 6467 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6468 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6469 6470 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 6471 return llvm::makeArrayRef(GCCRegNames); 6472 } 6473 6474 // LLVM and Clang cannot be used directly to output native binaries for 6475 // target, but is used to compile C code to llvm bitcode with correct 6476 // type and alignment information. 6477 // 6478 // TCE uses the llvm bitcode as input and uses it for generating customized 6479 // target processor and program binary. TCE co-design environment is 6480 // publicly available in http://tce.cs.tut.fi 6481 6482 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6483 3, // opencl_global 6484 4, // opencl_local 6485 5, // opencl_constant 6486 // FIXME: generic has to be added to the target 6487 0, // opencl_generic 6488 0, // cuda_device 6489 0, // cuda_constant 6490 0 // cuda_shared 6491 }; 6492 6493 class TCETargetInfo : public TargetInfo { 6494 public: 6495 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6496 TLSSupported = false; 6497 IntWidth = 32; 6498 LongWidth = LongLongWidth = 32; 6499 PointerWidth = 32; 6500 IntAlign = 32; 6501 LongAlign = LongLongAlign = 32; 6502 PointerAlign = 32; 6503 SuitableAlign = 32; 6504 SizeType = UnsignedInt; 6505 IntMaxType = SignedLong; 6506 IntPtrType = SignedInt; 6507 PtrDiffType = SignedInt; 6508 FloatWidth = 32; 6509 FloatAlign = 32; 6510 DoubleWidth = 32; 6511 DoubleAlign = 32; 6512 LongDoubleWidth = 32; 6513 LongDoubleAlign = 32; 6514 FloatFormat = &llvm::APFloat::IEEEsingle; 6515 DoubleFormat = &llvm::APFloat::IEEEsingle; 6516 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6517 resetDataLayout("E-p:32:32-i8:8:32-i16:16:32-i64:32" 6518 "-f64:32-v64:32-v128:32-a:0:32-n32"); 6519 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6520 UseAddrSpaceMapMangling = true; 6521 } 6522 6523 void getTargetDefines(const LangOptions &Opts, 6524 MacroBuilder &Builder) const override { 6525 DefineStd(Builder, "tce", Opts); 6526 Builder.defineMacro("__TCE__"); 6527 Builder.defineMacro("__TCE_V1__"); 6528 } 6529 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 6530 6531 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6532 const char *getClobbers() const override { return ""; } 6533 BuiltinVaListKind getBuiltinVaListKind() const override { 6534 return TargetInfo::VoidPtrBuiltinVaList; 6535 } 6536 ArrayRef<const char *> getGCCRegNames() const override { return None; } 6537 bool validateAsmConstraint(const char *&Name, 6538 TargetInfo::ConstraintInfo &info) const override { 6539 return true; 6540 } 6541 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6542 return None; 6543 } 6544 }; 6545 6546 class BPFTargetInfo : public TargetInfo { 6547 public: 6548 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6549 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6550 SizeType = UnsignedLong; 6551 PtrDiffType = SignedLong; 6552 IntPtrType = SignedLong; 6553 IntMaxType = SignedLong; 6554 Int64Type = SignedLong; 6555 RegParmMax = 5; 6556 if (Triple.getArch() == llvm::Triple::bpfeb) { 6557 BigEndian = true; 6558 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 6559 } else { 6560 BigEndian = false; 6561 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 6562 } 6563 MaxAtomicPromoteWidth = 64; 6564 MaxAtomicInlineWidth = 64; 6565 TLSSupported = false; 6566 } 6567 void getTargetDefines(const LangOptions &Opts, 6568 MacroBuilder &Builder) const override { 6569 DefineStd(Builder, "bpf", Opts); 6570 Builder.defineMacro("__BPF__"); 6571 } 6572 bool hasFeature(StringRef Feature) const override { 6573 return Feature == "bpf"; 6574 } 6575 6576 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6577 const char *getClobbers() const override { 6578 return ""; 6579 } 6580 BuiltinVaListKind getBuiltinVaListKind() const override { 6581 return TargetInfo::VoidPtrBuiltinVaList; 6582 } 6583 ArrayRef<const char *> getGCCRegNames() const override { 6584 return None; 6585 } 6586 bool validateAsmConstraint(const char *&Name, 6587 TargetInfo::ConstraintInfo &info) const override { 6588 return true; 6589 } 6590 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6591 return None; 6592 } 6593 }; 6594 6595 class MipsTargetInfoBase : public TargetInfo { 6596 virtual void setDataLayout() = 0; 6597 6598 static const Builtin::Info BuiltinInfo[]; 6599 std::string CPU; 6600 bool IsMips16; 6601 bool IsMicromips; 6602 bool IsNan2008; 6603 bool IsSingleFloat; 6604 enum MipsFloatABI { 6605 HardFloat, SoftFloat 6606 } FloatABI; 6607 enum DspRevEnum { 6608 NoDSP, DSP1, DSP2 6609 } DspRev; 6610 bool HasMSA; 6611 6612 protected: 6613 bool HasFP64; 6614 std::string ABI; 6615 6616 public: 6617 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 6618 const std::string &CPUStr) 6619 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6620 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6621 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6622 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6623 } 6624 6625 bool isNaN2008Default() const { 6626 return CPU == "mips32r6" || CPU == "mips64r6"; 6627 } 6628 6629 bool isFP64Default() const { 6630 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6631 } 6632 6633 bool isNan2008() const override { 6634 return IsNan2008; 6635 } 6636 6637 StringRef getABI() const override { return ABI; } 6638 bool setCPU(const std::string &Name) override { 6639 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6640 getTriple().getArch() == llvm::Triple::mipsel; 6641 CPU = Name; 6642 return llvm::StringSwitch<bool>(Name) 6643 .Case("mips1", IsMips32) 6644 .Case("mips2", IsMips32) 6645 .Case("mips3", true) 6646 .Case("mips4", true) 6647 .Case("mips5", true) 6648 .Case("mips32", IsMips32) 6649 .Case("mips32r2", IsMips32) 6650 .Case("mips32r3", IsMips32) 6651 .Case("mips32r5", IsMips32) 6652 .Case("mips32r6", IsMips32) 6653 .Case("mips64", true) 6654 .Case("mips64r2", true) 6655 .Case("mips64r3", true) 6656 .Case("mips64r5", true) 6657 .Case("mips64r6", true) 6658 .Case("octeon", true) 6659 .Case("p5600", true) 6660 .Default(false); 6661 } 6662 const std::string& getCPU() const { return CPU; } 6663 bool 6664 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6665 StringRef CPU, 6666 const std::vector<std::string> &FeaturesVec) const override { 6667 if (CPU.empty()) 6668 CPU = getCPU(); 6669 if (CPU == "octeon") 6670 Features["mips64r2"] = Features["cnmips"] = true; 6671 else 6672 Features[CPU] = true; 6673 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6674 } 6675 6676 void getTargetDefines(const LangOptions &Opts, 6677 MacroBuilder &Builder) const override { 6678 Builder.defineMacro("__mips__"); 6679 Builder.defineMacro("_mips"); 6680 if (Opts.GNUMode) 6681 Builder.defineMacro("mips"); 6682 6683 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6684 6685 switch (FloatABI) { 6686 case HardFloat: 6687 Builder.defineMacro("__mips_hard_float", Twine(1)); 6688 break; 6689 case SoftFloat: 6690 Builder.defineMacro("__mips_soft_float", Twine(1)); 6691 break; 6692 } 6693 6694 if (IsSingleFloat) 6695 Builder.defineMacro("__mips_single_float", Twine(1)); 6696 6697 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6698 Builder.defineMacro("_MIPS_FPSET", 6699 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6700 6701 if (IsMips16) 6702 Builder.defineMacro("__mips16", Twine(1)); 6703 6704 if (IsMicromips) 6705 Builder.defineMacro("__mips_micromips", Twine(1)); 6706 6707 if (IsNan2008) 6708 Builder.defineMacro("__mips_nan2008", Twine(1)); 6709 6710 switch (DspRev) { 6711 default: 6712 break; 6713 case DSP1: 6714 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6715 Builder.defineMacro("__mips_dsp", Twine(1)); 6716 break; 6717 case DSP2: 6718 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6719 Builder.defineMacro("__mips_dspr2", Twine(1)); 6720 Builder.defineMacro("__mips_dsp", Twine(1)); 6721 break; 6722 } 6723 6724 if (HasMSA) 6725 Builder.defineMacro("__mips_msa", Twine(1)); 6726 6727 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6728 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6729 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6730 6731 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6732 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6733 6734 // These shouldn't be defined for MIPS-I but there's no need to check 6735 // for that since MIPS-I isn't supported. 6736 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6737 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6738 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6739 } 6740 6741 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6742 return llvm::makeArrayRef(BuiltinInfo, 6743 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 6744 } 6745 bool hasFeature(StringRef Feature) const override { 6746 return llvm::StringSwitch<bool>(Feature) 6747 .Case("mips", true) 6748 .Case("fp64", HasFP64) 6749 .Default(false); 6750 } 6751 BuiltinVaListKind getBuiltinVaListKind() const override { 6752 return TargetInfo::VoidPtrBuiltinVaList; 6753 } 6754 ArrayRef<const char *> getGCCRegNames() const override { 6755 static const char *const GCCRegNames[] = { 6756 // CPU register names 6757 // Must match second column of GCCRegAliases 6758 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6759 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6760 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6761 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6762 // Floating point register names 6763 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6764 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6765 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6766 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6767 // Hi/lo and condition register names 6768 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6769 "$fcc5","$fcc6","$fcc7", 6770 // MSA register names 6771 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6772 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6773 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6774 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6775 // MSA control register names 6776 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6777 "$msarequest", "$msamap", "$msaunmap" 6778 }; 6779 return llvm::makeArrayRef(GCCRegNames); 6780 } 6781 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override = 0; 6782 bool validateAsmConstraint(const char *&Name, 6783 TargetInfo::ConstraintInfo &Info) const override { 6784 switch (*Name) { 6785 default: 6786 return false; 6787 case 'r': // CPU registers. 6788 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6789 case 'y': // Equivalent to "r", backward compatibility only. 6790 case 'f': // floating-point registers. 6791 case 'c': // $25 for indirect jumps 6792 case 'l': // lo register 6793 case 'x': // hilo register pair 6794 Info.setAllowsRegister(); 6795 return true; 6796 case 'I': // Signed 16-bit constant 6797 case 'J': // Integer 0 6798 case 'K': // Unsigned 16-bit constant 6799 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6800 case 'M': // Constants not loadable via lui, addiu, or ori 6801 case 'N': // Constant -1 to -65535 6802 case 'O': // A signed 15-bit constant 6803 case 'P': // A constant between 1 go 65535 6804 return true; 6805 case 'R': // An address that can be used in a non-macro load or store 6806 Info.setAllowsMemory(); 6807 return true; 6808 case 'Z': 6809 if (Name[1] == 'C') { // An address usable by ll, and sc. 6810 Info.setAllowsMemory(); 6811 Name++; // Skip over 'Z'. 6812 return true; 6813 } 6814 return false; 6815 } 6816 } 6817 6818 std::string convertConstraint(const char *&Constraint) const override { 6819 std::string R; 6820 switch (*Constraint) { 6821 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6822 if (Constraint[1] == 'C') { 6823 R = std::string("^") + std::string(Constraint, 2); 6824 Constraint++; 6825 return R; 6826 } 6827 break; 6828 } 6829 return TargetInfo::convertConstraint(Constraint); 6830 } 6831 6832 const char *getClobbers() const override { 6833 // In GCC, $1 is not widely used in generated code (it's used only in a few 6834 // specific situations), so there is no real need for users to add it to 6835 // the clobbers list if they want to use it in their inline assembly code. 6836 // 6837 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6838 // code generation, so using it in inline assembly without adding it to the 6839 // clobbers list can cause conflicts between the inline assembly code and 6840 // the surrounding generated code. 6841 // 6842 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6843 // operands, which will conflict with the ".set at" assembler option (which 6844 // we use only for inline assembly, in order to maintain compatibility with 6845 // GCC) and will also conflict with the user's usage of $1. 6846 // 6847 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6848 // register for generated code is to automatically clobber $1 for all inline 6849 // assembly code. 6850 // 6851 // FIXME: We should automatically clobber $1 only for inline assembly code 6852 // which actually uses it. This would allow LLVM to use $1 for inline 6853 // assembly operands if the user's assembly code doesn't use it. 6854 return "~{$1}"; 6855 } 6856 6857 bool handleTargetFeatures(std::vector<std::string> &Features, 6858 DiagnosticsEngine &Diags) override { 6859 IsMips16 = false; 6860 IsMicromips = false; 6861 IsNan2008 = isNaN2008Default(); 6862 IsSingleFloat = false; 6863 FloatABI = HardFloat; 6864 DspRev = NoDSP; 6865 HasFP64 = isFP64Default(); 6866 6867 for (const auto &Feature : Features) { 6868 if (Feature == "+single-float") 6869 IsSingleFloat = true; 6870 else if (Feature == "+soft-float") 6871 FloatABI = SoftFloat; 6872 else if (Feature == "+mips16") 6873 IsMips16 = true; 6874 else if (Feature == "+micromips") 6875 IsMicromips = true; 6876 else if (Feature == "+dsp") 6877 DspRev = std::max(DspRev, DSP1); 6878 else if (Feature == "+dspr2") 6879 DspRev = std::max(DspRev, DSP2); 6880 else if (Feature == "+msa") 6881 HasMSA = true; 6882 else if (Feature == "+fp64") 6883 HasFP64 = true; 6884 else if (Feature == "-fp64") 6885 HasFP64 = false; 6886 else if (Feature == "+nan2008") 6887 IsNan2008 = true; 6888 else if (Feature == "-nan2008") 6889 IsNan2008 = false; 6890 } 6891 6892 setDataLayout(); 6893 6894 return true; 6895 } 6896 6897 int getEHDataRegisterNumber(unsigned RegNo) const override { 6898 if (RegNo == 0) return 4; 6899 if (RegNo == 1) return 5; 6900 return -1; 6901 } 6902 6903 bool isCLZForZeroUndef() const override { return false; } 6904 }; 6905 6906 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 6907 #define BUILTIN(ID, TYPE, ATTRS) \ 6908 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6909 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6910 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6911 #include "clang/Basic/BuiltinsMips.def" 6912 }; 6913 6914 class Mips32TargetInfoBase : public MipsTargetInfoBase { 6915 public: 6916 Mips32TargetInfoBase(const llvm::Triple &Triple) 6917 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 6918 SizeType = UnsignedInt; 6919 PtrDiffType = SignedInt; 6920 Int64Type = SignedLongLong; 6921 IntMaxType = Int64Type; 6922 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 6923 } 6924 bool setABI(const std::string &Name) override { 6925 if (Name == "o32" || Name == "eabi") { 6926 ABI = Name; 6927 return true; 6928 } 6929 return false; 6930 } 6931 void getTargetDefines(const LangOptions &Opts, 6932 MacroBuilder &Builder) const override { 6933 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6934 6935 Builder.defineMacro("__mips", "32"); 6936 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 6937 6938 const std::string& CPUStr = getCPU(); 6939 if (CPUStr == "mips32") 6940 Builder.defineMacro("__mips_isa_rev", "1"); 6941 else if (CPUStr == "mips32r2") 6942 Builder.defineMacro("__mips_isa_rev", "2"); 6943 else if (CPUStr == "mips32r3") 6944 Builder.defineMacro("__mips_isa_rev", "3"); 6945 else if (CPUStr == "mips32r5") 6946 Builder.defineMacro("__mips_isa_rev", "5"); 6947 else if (CPUStr == "mips32r6") 6948 Builder.defineMacro("__mips_isa_rev", "6"); 6949 6950 if (ABI == "o32") { 6951 Builder.defineMacro("__mips_o32"); 6952 Builder.defineMacro("_ABIO32", "1"); 6953 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6954 } 6955 else if (ABI == "eabi") 6956 Builder.defineMacro("__mips_eabi"); 6957 else 6958 llvm_unreachable("Invalid ABI for Mips32."); 6959 } 6960 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6961 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6962 { { "at" }, "$1" }, 6963 { { "v0" }, "$2" }, 6964 { { "v1" }, "$3" }, 6965 { { "a0" }, "$4" }, 6966 { { "a1" }, "$5" }, 6967 { { "a2" }, "$6" }, 6968 { { "a3" }, "$7" }, 6969 { { "t0" }, "$8" }, 6970 { { "t1" }, "$9" }, 6971 { { "t2" }, "$10" }, 6972 { { "t3" }, "$11" }, 6973 { { "t4" }, "$12" }, 6974 { { "t5" }, "$13" }, 6975 { { "t6" }, "$14" }, 6976 { { "t7" }, "$15" }, 6977 { { "s0" }, "$16" }, 6978 { { "s1" }, "$17" }, 6979 { { "s2" }, "$18" }, 6980 { { "s3" }, "$19" }, 6981 { { "s4" }, "$20" }, 6982 { { "s5" }, "$21" }, 6983 { { "s6" }, "$22" }, 6984 { { "s7" }, "$23" }, 6985 { { "t8" }, "$24" }, 6986 { { "t9" }, "$25" }, 6987 { { "k0" }, "$26" }, 6988 { { "k1" }, "$27" }, 6989 { { "gp" }, "$28" }, 6990 { { "sp","$sp" }, "$29" }, 6991 { { "fp","$fp" }, "$30" }, 6992 { { "ra" }, "$31" } 6993 }; 6994 return llvm::makeArrayRef(GCCRegAliases); 6995 } 6996 }; 6997 6998 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6999 void setDataLayout() override { 7000 resetDataLayout("E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"); 7001 } 7002 7003 public: 7004 Mips32EBTargetInfo(const llvm::Triple &Triple) 7005 : Mips32TargetInfoBase(Triple) { 7006 } 7007 void getTargetDefines(const LangOptions &Opts, 7008 MacroBuilder &Builder) const override { 7009 DefineStd(Builder, "MIPSEB", Opts); 7010 Builder.defineMacro("_MIPSEB"); 7011 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 7012 } 7013 }; 7014 7015 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 7016 void setDataLayout() override { 7017 resetDataLayout("e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"); 7018 } 7019 7020 public: 7021 Mips32ELTargetInfo(const llvm::Triple &Triple) 7022 : Mips32TargetInfoBase(Triple) { 7023 BigEndian = false; 7024 } 7025 void getTargetDefines(const LangOptions &Opts, 7026 MacroBuilder &Builder) const override { 7027 DefineStd(Builder, "MIPSEL", Opts); 7028 Builder.defineMacro("_MIPSEL"); 7029 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 7030 } 7031 }; 7032 7033 class Mips64TargetInfoBase : public MipsTargetInfoBase { 7034 public: 7035 Mips64TargetInfoBase(const llvm::Triple &Triple) 7036 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 7037 LongDoubleWidth = LongDoubleAlign = 128; 7038 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7039 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7040 LongDoubleWidth = LongDoubleAlign = 64; 7041 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7042 } 7043 setN64ABITypes(); 7044 SuitableAlign = 128; 7045 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7046 } 7047 7048 void setN64ABITypes() { 7049 LongWidth = LongAlign = 64; 7050 PointerWidth = PointerAlign = 64; 7051 SizeType = UnsignedLong; 7052 PtrDiffType = SignedLong; 7053 Int64Type = SignedLong; 7054 IntMaxType = Int64Type; 7055 } 7056 7057 void setN32ABITypes() { 7058 LongWidth = LongAlign = 32; 7059 PointerWidth = PointerAlign = 32; 7060 SizeType = UnsignedInt; 7061 PtrDiffType = SignedInt; 7062 Int64Type = SignedLongLong; 7063 IntMaxType = Int64Type; 7064 } 7065 7066 bool setABI(const std::string &Name) override { 7067 if (Name == "n32") { 7068 setN32ABITypes(); 7069 ABI = Name; 7070 return true; 7071 } 7072 if (Name == "n64") { 7073 setN64ABITypes(); 7074 ABI = Name; 7075 return true; 7076 } 7077 return false; 7078 } 7079 7080 void getTargetDefines(const LangOptions &Opts, 7081 MacroBuilder &Builder) const override { 7082 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 7083 7084 Builder.defineMacro("__mips", "64"); 7085 Builder.defineMacro("__mips64"); 7086 Builder.defineMacro("__mips64__"); 7087 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7088 7089 const std::string& CPUStr = getCPU(); 7090 if (CPUStr == "mips64") 7091 Builder.defineMacro("__mips_isa_rev", "1"); 7092 else if (CPUStr == "mips64r2") 7093 Builder.defineMacro("__mips_isa_rev", "2"); 7094 else if (CPUStr == "mips64r3") 7095 Builder.defineMacro("__mips_isa_rev", "3"); 7096 else if (CPUStr == "mips64r5") 7097 Builder.defineMacro("__mips_isa_rev", "5"); 7098 else if (CPUStr == "mips64r6") 7099 Builder.defineMacro("__mips_isa_rev", "6"); 7100 7101 if (ABI == "n32") { 7102 Builder.defineMacro("__mips_n32"); 7103 Builder.defineMacro("_ABIN32", "2"); 7104 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7105 } 7106 else if (ABI == "n64") { 7107 Builder.defineMacro("__mips_n64"); 7108 Builder.defineMacro("_ABI64", "3"); 7109 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7110 } 7111 else 7112 llvm_unreachable("Invalid ABI for Mips64."); 7113 7114 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7115 } 7116 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7117 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 7118 { { "at" }, "$1" }, 7119 { { "v0" }, "$2" }, 7120 { { "v1" }, "$3" }, 7121 { { "a0" }, "$4" }, 7122 { { "a1" }, "$5" }, 7123 { { "a2" }, "$6" }, 7124 { { "a3" }, "$7" }, 7125 { { "a4" }, "$8" }, 7126 { { "a5" }, "$9" }, 7127 { { "a6" }, "$10" }, 7128 { { "a7" }, "$11" }, 7129 { { "t0" }, "$12" }, 7130 { { "t1" }, "$13" }, 7131 { { "t2" }, "$14" }, 7132 { { "t3" }, "$15" }, 7133 { { "s0" }, "$16" }, 7134 { { "s1" }, "$17" }, 7135 { { "s2" }, "$18" }, 7136 { { "s3" }, "$19" }, 7137 { { "s4" }, "$20" }, 7138 { { "s5" }, "$21" }, 7139 { { "s6" }, "$22" }, 7140 { { "s7" }, "$23" }, 7141 { { "t8" }, "$24" }, 7142 { { "t9" }, "$25" }, 7143 { { "k0" }, "$26" }, 7144 { { "k1" }, "$27" }, 7145 { { "gp" }, "$28" }, 7146 { { "sp","$sp" }, "$29" }, 7147 { { "fp","$fp" }, "$30" }, 7148 { { "ra" }, "$31" } 7149 }; 7150 return llvm::makeArrayRef(GCCRegAliases); 7151 } 7152 7153 bool hasInt128Type() const override { return true; } 7154 }; 7155 7156 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 7157 void setDataLayout() override { 7158 if (ABI == "n32") 7159 resetDataLayout("E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7160 else 7161 resetDataLayout("E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7162 } 7163 7164 public: 7165 Mips64EBTargetInfo(const llvm::Triple &Triple) 7166 : Mips64TargetInfoBase(Triple) {} 7167 void getTargetDefines(const LangOptions &Opts, 7168 MacroBuilder &Builder) const override { 7169 DefineStd(Builder, "MIPSEB", Opts); 7170 Builder.defineMacro("_MIPSEB"); 7171 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7172 } 7173 }; 7174 7175 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 7176 void setDataLayout() override { 7177 if (ABI == "n32") 7178 resetDataLayout("e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7179 else 7180 resetDataLayout("e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7181 } 7182 public: 7183 Mips64ELTargetInfo(const llvm::Triple &Triple) 7184 : Mips64TargetInfoBase(Triple) { 7185 // Default ABI is n64. 7186 BigEndian = false; 7187 } 7188 void getTargetDefines(const LangOptions &Opts, 7189 MacroBuilder &Builder) const override { 7190 DefineStd(Builder, "MIPSEL", Opts); 7191 Builder.defineMacro("_MIPSEL"); 7192 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7193 } 7194 }; 7195 7196 class PNaClTargetInfo : public TargetInfo { 7197 public: 7198 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7199 BigEndian = false; 7200 this->LongAlign = 32; 7201 this->LongWidth = 32; 7202 this->PointerAlign = 32; 7203 this->PointerWidth = 32; 7204 this->IntMaxType = TargetInfo::SignedLongLong; 7205 this->Int64Type = TargetInfo::SignedLongLong; 7206 this->DoubleAlign = 64; 7207 this->LongDoubleWidth = 64; 7208 this->LongDoubleAlign = 64; 7209 this->SizeType = TargetInfo::UnsignedInt; 7210 this->PtrDiffType = TargetInfo::SignedInt; 7211 this->IntPtrType = TargetInfo::SignedInt; 7212 this->RegParmMax = 0; // Disallow regparm 7213 } 7214 7215 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7216 Builder.defineMacro("__le32__"); 7217 Builder.defineMacro("__pnacl__"); 7218 } 7219 void getTargetDefines(const LangOptions &Opts, 7220 MacroBuilder &Builder) const override { 7221 getArchDefines(Opts, Builder); 7222 } 7223 bool hasFeature(StringRef Feature) const override { 7224 return Feature == "pnacl"; 7225 } 7226 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7227 BuiltinVaListKind getBuiltinVaListKind() const override { 7228 return TargetInfo::PNaClABIBuiltinVaList; 7229 } 7230 ArrayRef<const char *> getGCCRegNames() const override; 7231 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7232 bool validateAsmConstraint(const char *&Name, 7233 TargetInfo::ConstraintInfo &Info) const override { 7234 return false; 7235 } 7236 7237 const char *getClobbers() const override { 7238 return ""; 7239 } 7240 }; 7241 7242 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7243 return None; 7244 } 7245 7246 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7247 return None; 7248 } 7249 7250 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7251 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 7252 public: 7253 NaClMips32ELTargetInfo(const llvm::Triple &Triple) : 7254 Mips32ELTargetInfo(Triple) { 7255 } 7256 7257 BuiltinVaListKind getBuiltinVaListKind() const override { 7258 return TargetInfo::PNaClABIBuiltinVaList; 7259 } 7260 }; 7261 7262 class Le64TargetInfo : public TargetInfo { 7263 static const Builtin::Info BuiltinInfo[]; 7264 7265 public: 7266 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7267 BigEndian = false; 7268 NoAsmVariants = true; 7269 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7270 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7271 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 7272 } 7273 7274 void getTargetDefines(const LangOptions &Opts, 7275 MacroBuilder &Builder) const override { 7276 DefineStd(Builder, "unix", Opts); 7277 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7278 Builder.defineMacro("__ELF__"); 7279 } 7280 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7281 return llvm::makeArrayRef(BuiltinInfo, 7282 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7283 } 7284 BuiltinVaListKind getBuiltinVaListKind() const override { 7285 return TargetInfo::PNaClABIBuiltinVaList; 7286 } 7287 const char *getClobbers() const override { return ""; } 7288 ArrayRef<const char *> getGCCRegNames() const override { 7289 return None; 7290 } 7291 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7292 return None; 7293 } 7294 bool validateAsmConstraint(const char *&Name, 7295 TargetInfo::ConstraintInfo &Info) const override { 7296 return false; 7297 } 7298 7299 bool hasProtectedVisibility() const override { return false; } 7300 }; 7301 7302 class WebAssemblyTargetInfo : public TargetInfo { 7303 static const Builtin::Info BuiltinInfo[]; 7304 7305 enum SIMDEnum { 7306 NoSIMD, 7307 SIMD128, 7308 } SIMDLevel; 7309 7310 public: 7311 explicit WebAssemblyTargetInfo(const llvm::Triple &T) 7312 : TargetInfo(T), SIMDLevel(NoSIMD) { 7313 BigEndian = false; 7314 NoAsmVariants = true; 7315 SuitableAlign = 128; 7316 LargeArrayMinWidth = 128; 7317 LargeArrayAlign = 128; 7318 SimdDefaultAlign = 128; 7319 SigAtomicType = SignedLong; 7320 LongDoubleWidth = LongDoubleAlign = 128; 7321 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7322 } 7323 7324 protected: 7325 void getTargetDefines(const LangOptions &Opts, 7326 MacroBuilder &Builder) const override { 7327 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7328 if (SIMDLevel >= SIMD128) 7329 Builder.defineMacro("__wasm_simd128__"); 7330 } 7331 7332 private: 7333 bool 7334 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7335 StringRef CPU, 7336 const std::vector<std::string> &FeaturesVec) const override { 7337 if (CPU == "bleeding-edge") 7338 Features["simd128"] = true; 7339 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7340 } 7341 bool hasFeature(StringRef Feature) const final { 7342 return llvm::StringSwitch<bool>(Feature) 7343 .Case("simd128", SIMDLevel >= SIMD128) 7344 .Default(false); 7345 } 7346 bool handleTargetFeatures(std::vector<std::string> &Features, 7347 DiagnosticsEngine &Diags) final { 7348 for (const auto &Feature : Features) { 7349 if (Feature == "+simd128") { 7350 SIMDLevel = std::max(SIMDLevel, SIMD128); 7351 continue; 7352 } 7353 if (Feature == "-simd128") { 7354 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7355 continue; 7356 } 7357 7358 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7359 << "-target-feature"; 7360 return false; 7361 } 7362 return true; 7363 } 7364 bool setCPU(const std::string &Name) final { 7365 return llvm::StringSwitch<bool>(Name) 7366 .Case("mvp", true) 7367 .Case("bleeding-edge", true) 7368 .Case("generic", true) 7369 .Default(false); 7370 } 7371 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7372 return llvm::makeArrayRef(BuiltinInfo, 7373 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7374 } 7375 BuiltinVaListKind getBuiltinVaListKind() const final { 7376 return VoidPtrBuiltinVaList; 7377 } 7378 ArrayRef<const char *> getGCCRegNames() const final { 7379 return None; 7380 } 7381 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7382 return None; 7383 } 7384 bool 7385 validateAsmConstraint(const char *&Name, 7386 TargetInfo::ConstraintInfo &Info) const final { 7387 return false; 7388 } 7389 const char *getClobbers() const final { return ""; } 7390 bool isCLZForZeroUndef() const final { return false; } 7391 bool hasInt128Type() const final { return true; } 7392 IntType getIntTypeByWidth(unsigned BitWidth, 7393 bool IsSigned) const final { 7394 // WebAssembly prefers long long for explicitly 64-bit integers. 7395 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7396 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7397 } 7398 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7399 bool IsSigned) const final { 7400 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7401 return BitWidth == 64 7402 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7403 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7404 } 7405 }; 7406 7407 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7408 #define BUILTIN(ID, TYPE, ATTRS) \ 7409 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7410 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7411 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7412 #include "clang/Basic/BuiltinsWebAssembly.def" 7413 }; 7414 7415 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7416 public: 7417 explicit WebAssembly32TargetInfo(const llvm::Triple &T) 7418 : WebAssemblyTargetInfo(T) { 7419 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7420 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 7421 } 7422 7423 protected: 7424 void getTargetDefines(const LangOptions &Opts, 7425 MacroBuilder &Builder) const override { 7426 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7427 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7428 } 7429 }; 7430 7431 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7432 public: 7433 explicit WebAssembly64TargetInfo(const llvm::Triple &T) 7434 : WebAssemblyTargetInfo(T) { 7435 LongAlign = LongWidth = 64; 7436 PointerAlign = PointerWidth = 64; 7437 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7438 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7439 } 7440 7441 protected: 7442 void getTargetDefines(const LangOptions &Opts, 7443 MacroBuilder &Builder) const override { 7444 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7445 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7446 } 7447 }; 7448 7449 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7450 #define BUILTIN(ID, TYPE, ATTRS) \ 7451 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7452 #include "clang/Basic/BuiltinsLe64.def" 7453 }; 7454 7455 static const unsigned SPIRAddrSpaceMap[] = { 7456 1, // opencl_global 7457 3, // opencl_local 7458 2, // opencl_constant 7459 4, // opencl_generic 7460 0, // cuda_device 7461 0, // cuda_constant 7462 0 // cuda_shared 7463 }; 7464 class SPIRTargetInfo : public TargetInfo { 7465 public: 7466 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7467 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7468 "SPIR target must use unknown OS"); 7469 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7470 "SPIR target must use unknown environment type"); 7471 BigEndian = false; 7472 TLSSupported = false; 7473 LongWidth = LongAlign = 64; 7474 AddrSpaceMap = &SPIRAddrSpaceMap; 7475 UseAddrSpaceMapMangling = true; 7476 // Define available target features 7477 // These must be defined in sorted order! 7478 NoAsmVariants = true; 7479 } 7480 void getTargetDefines(const LangOptions &Opts, 7481 MacroBuilder &Builder) const override { 7482 DefineStd(Builder, "SPIR", Opts); 7483 } 7484 bool hasFeature(StringRef Feature) const override { 7485 return Feature == "spir"; 7486 } 7487 7488 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7489 const char *getClobbers() const override { return ""; } 7490 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7491 bool validateAsmConstraint(const char *&Name, 7492 TargetInfo::ConstraintInfo &info) const override { 7493 return true; 7494 } 7495 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7496 return None; 7497 } 7498 BuiltinVaListKind getBuiltinVaListKind() const override { 7499 return TargetInfo::VoidPtrBuiltinVaList; 7500 } 7501 7502 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7503 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK 7504 : CCCR_Warning; 7505 } 7506 7507 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7508 return CC_SpirFunction; 7509 } 7510 }; 7511 7512 class SPIR32TargetInfo : public SPIRTargetInfo { 7513 public: 7514 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7515 PointerWidth = PointerAlign = 32; 7516 SizeType = TargetInfo::UnsignedInt; 7517 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7518 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7519 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7520 } 7521 void getTargetDefines(const LangOptions &Opts, 7522 MacroBuilder &Builder) const override { 7523 DefineStd(Builder, "SPIR32", Opts); 7524 } 7525 }; 7526 7527 class SPIR64TargetInfo : public SPIRTargetInfo { 7528 public: 7529 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7530 PointerWidth = PointerAlign = 64; 7531 SizeType = TargetInfo::UnsignedLong; 7532 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7533 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7534 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7535 } 7536 void getTargetDefines(const LangOptions &Opts, 7537 MacroBuilder &Builder) const override { 7538 DefineStd(Builder, "SPIR64", Opts); 7539 } 7540 }; 7541 7542 class XCoreTargetInfo : public TargetInfo { 7543 static const Builtin::Info BuiltinInfo[]; 7544 public: 7545 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7546 BigEndian = false; 7547 NoAsmVariants = true; 7548 LongLongAlign = 32; 7549 SuitableAlign = 32; 7550 DoubleAlign = LongDoubleAlign = 32; 7551 SizeType = UnsignedInt; 7552 PtrDiffType = SignedInt; 7553 IntPtrType = SignedInt; 7554 WCharType = UnsignedChar; 7555 WIntType = UnsignedInt; 7556 UseZeroLengthBitfieldAlignment = true; 7557 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7558 "-f64:32-a:0:32-n32"); 7559 } 7560 void getTargetDefines(const LangOptions &Opts, 7561 MacroBuilder &Builder) const override { 7562 Builder.defineMacro("__XS1B__"); 7563 } 7564 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7565 return llvm::makeArrayRef(BuiltinInfo, 7566 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 7567 } 7568 BuiltinVaListKind getBuiltinVaListKind() const override { 7569 return TargetInfo::VoidPtrBuiltinVaList; 7570 } 7571 const char *getClobbers() const override { 7572 return ""; 7573 } 7574 ArrayRef<const char *> getGCCRegNames() const override { 7575 static const char * const GCCRegNames[] = { 7576 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7577 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 7578 }; 7579 return llvm::makeArrayRef(GCCRegNames); 7580 } 7581 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7582 return None; 7583 } 7584 bool validateAsmConstraint(const char *&Name, 7585 TargetInfo::ConstraintInfo &Info) const override { 7586 return false; 7587 } 7588 int getEHDataRegisterNumber(unsigned RegNo) const override { 7589 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7590 return (RegNo < 2)? RegNo : -1; 7591 } 7592 bool allowsLargerPreferedTypeAlignment() const override { 7593 return false; 7594 } 7595 }; 7596 7597 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7598 #define BUILTIN(ID, TYPE, ATTRS) \ 7599 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7600 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7601 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7602 #include "clang/Basic/BuiltinsXCore.def" 7603 }; 7604 7605 // x86_32 Android target 7606 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7607 public: 7608 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 7609 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 7610 SuitableAlign = 32; 7611 LongDoubleWidth = 64; 7612 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7613 } 7614 }; 7615 7616 // x86_64 Android target 7617 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7618 public: 7619 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 7620 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 7621 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7622 } 7623 7624 bool useFloat128ManglingForLongDouble() const override { 7625 return true; 7626 } 7627 }; 7628 } // end anonymous namespace 7629 7630 //===----------------------------------------------------------------------===// 7631 // Driver code 7632 //===----------------------------------------------------------------------===// 7633 7634 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 7635 llvm::Triple::OSType os = Triple.getOS(); 7636 7637 switch (Triple.getArch()) { 7638 default: 7639 return nullptr; 7640 7641 case llvm::Triple::xcore: 7642 return new XCoreTargetInfo(Triple); 7643 7644 case llvm::Triple::hexagon: 7645 return new HexagonTargetInfo(Triple); 7646 7647 case llvm::Triple::aarch64: 7648 if (Triple.isOSDarwin()) 7649 return new DarwinAArch64TargetInfo(Triple); 7650 7651 switch (os) { 7652 case llvm::Triple::CloudABI: 7653 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple); 7654 case llvm::Triple::FreeBSD: 7655 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 7656 case llvm::Triple::Linux: 7657 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 7658 case llvm::Triple::NetBSD: 7659 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 7660 default: 7661 return new AArch64leTargetInfo(Triple); 7662 } 7663 7664 case llvm::Triple::aarch64_be: 7665 switch (os) { 7666 case llvm::Triple::FreeBSD: 7667 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 7668 case llvm::Triple::Linux: 7669 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 7670 case llvm::Triple::NetBSD: 7671 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 7672 default: 7673 return new AArch64beTargetInfo(Triple); 7674 } 7675 7676 case llvm::Triple::arm: 7677 case llvm::Triple::thumb: 7678 if (Triple.isOSBinFormatMachO()) 7679 return new DarwinARMTargetInfo(Triple); 7680 7681 switch (os) { 7682 case llvm::Triple::Linux: 7683 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 7684 case llvm::Triple::FreeBSD: 7685 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 7686 case llvm::Triple::NetBSD: 7687 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 7688 case llvm::Triple::OpenBSD: 7689 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 7690 case llvm::Triple::Bitrig: 7691 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 7692 case llvm::Triple::RTEMS: 7693 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 7694 case llvm::Triple::NaCl: 7695 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 7696 case llvm::Triple::Win32: 7697 switch (Triple.getEnvironment()) { 7698 case llvm::Triple::Cygnus: 7699 return new CygwinARMTargetInfo(Triple); 7700 case llvm::Triple::GNU: 7701 return new MinGWARMTargetInfo(Triple); 7702 case llvm::Triple::Itanium: 7703 return new ItaniumWindowsARMleTargetInfo(Triple); 7704 case llvm::Triple::MSVC: 7705 default: // Assume MSVC for unknown environments 7706 return new MicrosoftARMleTargetInfo(Triple); 7707 } 7708 default: 7709 return new ARMleTargetInfo(Triple); 7710 } 7711 7712 case llvm::Triple::armeb: 7713 case llvm::Triple::thumbeb: 7714 if (Triple.isOSDarwin()) 7715 return new DarwinARMTargetInfo(Triple); 7716 7717 switch (os) { 7718 case llvm::Triple::Linux: 7719 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 7720 case llvm::Triple::FreeBSD: 7721 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 7722 case llvm::Triple::NetBSD: 7723 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 7724 case llvm::Triple::OpenBSD: 7725 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 7726 case llvm::Triple::Bitrig: 7727 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 7728 case llvm::Triple::RTEMS: 7729 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 7730 case llvm::Triple::NaCl: 7731 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 7732 default: 7733 return new ARMbeTargetInfo(Triple); 7734 } 7735 7736 case llvm::Triple::bpfeb: 7737 case llvm::Triple::bpfel: 7738 return new BPFTargetInfo(Triple); 7739 7740 case llvm::Triple::msp430: 7741 return new MSP430TargetInfo(Triple); 7742 7743 case llvm::Triple::mips: 7744 switch (os) { 7745 case llvm::Triple::Linux: 7746 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 7747 case llvm::Triple::RTEMS: 7748 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 7749 case llvm::Triple::FreeBSD: 7750 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7751 case llvm::Triple::NetBSD: 7752 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7753 default: 7754 return new Mips32EBTargetInfo(Triple); 7755 } 7756 7757 case llvm::Triple::mipsel: 7758 switch (os) { 7759 case llvm::Triple::Linux: 7760 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 7761 case llvm::Triple::RTEMS: 7762 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 7763 case llvm::Triple::FreeBSD: 7764 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7765 case llvm::Triple::NetBSD: 7766 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7767 case llvm::Triple::NaCl: 7768 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple); 7769 default: 7770 return new Mips32ELTargetInfo(Triple); 7771 } 7772 7773 case llvm::Triple::mips64: 7774 switch (os) { 7775 case llvm::Triple::Linux: 7776 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 7777 case llvm::Triple::RTEMS: 7778 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 7779 case llvm::Triple::FreeBSD: 7780 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7781 case llvm::Triple::NetBSD: 7782 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7783 case llvm::Triple::OpenBSD: 7784 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7785 default: 7786 return new Mips64EBTargetInfo(Triple); 7787 } 7788 7789 case llvm::Triple::mips64el: 7790 switch (os) { 7791 case llvm::Triple::Linux: 7792 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 7793 case llvm::Triple::RTEMS: 7794 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 7795 case llvm::Triple::FreeBSD: 7796 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7797 case llvm::Triple::NetBSD: 7798 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7799 case llvm::Triple::OpenBSD: 7800 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7801 default: 7802 return new Mips64ELTargetInfo(Triple); 7803 } 7804 7805 case llvm::Triple::le32: 7806 switch (os) { 7807 case llvm::Triple::NaCl: 7808 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 7809 default: 7810 return nullptr; 7811 } 7812 7813 case llvm::Triple::le64: 7814 return new Le64TargetInfo(Triple); 7815 7816 case llvm::Triple::ppc: 7817 if (Triple.isOSDarwin()) 7818 return new DarwinPPC32TargetInfo(Triple); 7819 switch (os) { 7820 case llvm::Triple::Linux: 7821 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 7822 case llvm::Triple::FreeBSD: 7823 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 7824 case llvm::Triple::NetBSD: 7825 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 7826 case llvm::Triple::OpenBSD: 7827 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 7828 case llvm::Triple::RTEMS: 7829 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 7830 default: 7831 return new PPC32TargetInfo(Triple); 7832 } 7833 7834 case llvm::Triple::ppc64: 7835 if (Triple.isOSDarwin()) 7836 return new DarwinPPC64TargetInfo(Triple); 7837 switch (os) { 7838 case llvm::Triple::Linux: 7839 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7840 case llvm::Triple::Lv2: 7841 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 7842 case llvm::Triple::FreeBSD: 7843 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 7844 case llvm::Triple::NetBSD: 7845 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7846 default: 7847 return new PPC64TargetInfo(Triple); 7848 } 7849 7850 case llvm::Triple::ppc64le: 7851 switch (os) { 7852 case llvm::Triple::Linux: 7853 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7854 case llvm::Triple::NetBSD: 7855 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7856 default: 7857 return new PPC64TargetInfo(Triple); 7858 } 7859 7860 case llvm::Triple::nvptx: 7861 return new NVPTX32TargetInfo(Triple); 7862 case llvm::Triple::nvptx64: 7863 return new NVPTX64TargetInfo(Triple); 7864 7865 case llvm::Triple::amdgcn: 7866 case llvm::Triple::r600: 7867 return new AMDGPUTargetInfo(Triple); 7868 7869 case llvm::Triple::sparc: 7870 switch (os) { 7871 case llvm::Triple::Linux: 7872 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 7873 case llvm::Triple::Solaris: 7874 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple); 7875 case llvm::Triple::NetBSD: 7876 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 7877 case llvm::Triple::OpenBSD: 7878 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 7879 case llvm::Triple::RTEMS: 7880 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 7881 default: 7882 return new SparcV8TargetInfo(Triple); 7883 } 7884 7885 // The 'sparcel' architecture copies all the above cases except for Solaris. 7886 case llvm::Triple::sparcel: 7887 switch (os) { 7888 case llvm::Triple::Linux: 7889 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 7890 case llvm::Triple::NetBSD: 7891 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7892 case llvm::Triple::OpenBSD: 7893 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7894 case llvm::Triple::RTEMS: 7895 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 7896 default: 7897 return new SparcV8elTargetInfo(Triple); 7898 } 7899 7900 case llvm::Triple::sparcv9: 7901 switch (os) { 7902 case llvm::Triple::Linux: 7903 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 7904 case llvm::Triple::Solaris: 7905 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 7906 case llvm::Triple::NetBSD: 7907 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 7908 case llvm::Triple::OpenBSD: 7909 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 7910 case llvm::Triple::FreeBSD: 7911 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 7912 default: 7913 return new SparcV9TargetInfo(Triple); 7914 } 7915 7916 case llvm::Triple::systemz: 7917 switch (os) { 7918 case llvm::Triple::Linux: 7919 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 7920 default: 7921 return new SystemZTargetInfo(Triple); 7922 } 7923 7924 case llvm::Triple::tce: 7925 return new TCETargetInfo(Triple); 7926 7927 case llvm::Triple::x86: 7928 if (Triple.isOSDarwin()) 7929 return new DarwinI386TargetInfo(Triple); 7930 7931 switch (os) { 7932 case llvm::Triple::CloudABI: 7933 return new CloudABITargetInfo<X86_32TargetInfo>(Triple); 7934 case llvm::Triple::Linux: { 7935 switch (Triple.getEnvironment()) { 7936 default: 7937 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 7938 case llvm::Triple::Android: 7939 return new AndroidX86_32TargetInfo(Triple); 7940 } 7941 } 7942 case llvm::Triple::DragonFly: 7943 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 7944 case llvm::Triple::NetBSD: 7945 return new NetBSDI386TargetInfo(Triple); 7946 case llvm::Triple::OpenBSD: 7947 return new OpenBSDI386TargetInfo(Triple); 7948 case llvm::Triple::Bitrig: 7949 return new BitrigI386TargetInfo(Triple); 7950 case llvm::Triple::FreeBSD: 7951 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7952 case llvm::Triple::KFreeBSD: 7953 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7954 case llvm::Triple::Minix: 7955 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 7956 case llvm::Triple::Solaris: 7957 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 7958 case llvm::Triple::Win32: { 7959 switch (Triple.getEnvironment()) { 7960 case llvm::Triple::Cygnus: 7961 return new CygwinX86_32TargetInfo(Triple); 7962 case llvm::Triple::GNU: 7963 return new MinGWX86_32TargetInfo(Triple); 7964 case llvm::Triple::Itanium: 7965 case llvm::Triple::MSVC: 7966 default: // Assume MSVC for unknown environments 7967 return new MicrosoftX86_32TargetInfo(Triple); 7968 } 7969 } 7970 case llvm::Triple::Haiku: 7971 return new HaikuX86_32TargetInfo(Triple); 7972 case llvm::Triple::RTEMS: 7973 return new RTEMSX86_32TargetInfo(Triple); 7974 case llvm::Triple::NaCl: 7975 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 7976 case llvm::Triple::ELFIAMCU: 7977 return new MCUX86_32TargetInfo(Triple); 7978 default: 7979 return new X86_32TargetInfo(Triple); 7980 } 7981 7982 case llvm::Triple::x86_64: 7983 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 7984 return new DarwinX86_64TargetInfo(Triple); 7985 7986 switch (os) { 7987 case llvm::Triple::CloudABI: 7988 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 7989 case llvm::Triple::Linux: { 7990 switch (Triple.getEnvironment()) { 7991 default: 7992 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 7993 case llvm::Triple::Android: 7994 return new AndroidX86_64TargetInfo(Triple); 7995 } 7996 } 7997 case llvm::Triple::DragonFly: 7998 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 7999 case llvm::Triple::NetBSD: 8000 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 8001 case llvm::Triple::OpenBSD: 8002 return new OpenBSDX86_64TargetInfo(Triple); 8003 case llvm::Triple::Bitrig: 8004 return new BitrigX86_64TargetInfo(Triple); 8005 case llvm::Triple::FreeBSD: 8006 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 8007 case llvm::Triple::KFreeBSD: 8008 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 8009 case llvm::Triple::Solaris: 8010 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 8011 case llvm::Triple::Win32: { 8012 switch (Triple.getEnvironment()) { 8013 case llvm::Triple::Cygnus: 8014 return new CygwinX86_64TargetInfo(Triple); 8015 case llvm::Triple::GNU: 8016 return new MinGWX86_64TargetInfo(Triple); 8017 case llvm::Triple::MSVC: 8018 default: // Assume MSVC for unknown environments 8019 return new MicrosoftX86_64TargetInfo(Triple); 8020 } 8021 } 8022 case llvm::Triple::NaCl: 8023 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 8024 case llvm::Triple::PS4: 8025 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 8026 default: 8027 return new X86_64TargetInfo(Triple); 8028 } 8029 8030 case llvm::Triple::spir: { 8031 if (Triple.getOS() != llvm::Triple::UnknownOS || 8032 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8033 return nullptr; 8034 return new SPIR32TargetInfo(Triple); 8035 } 8036 case llvm::Triple::spir64: { 8037 if (Triple.getOS() != llvm::Triple::UnknownOS || 8038 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8039 return nullptr; 8040 return new SPIR64TargetInfo(Triple); 8041 } 8042 case llvm::Triple::wasm32: 8043 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8044 return nullptr; 8045 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple); 8046 case llvm::Triple::wasm64: 8047 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8048 return nullptr; 8049 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple); 8050 } 8051 } 8052 8053 /// CreateTargetInfo - Return the target info object for the specified target 8054 /// options. 8055 TargetInfo * 8056 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8057 const std::shared_ptr<TargetOptions> &Opts) { 8058 llvm::Triple Triple(Opts->Triple); 8059 8060 // Construct the target 8061 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 8062 if (!Target) { 8063 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8064 return nullptr; 8065 } 8066 Target->TargetOpts = Opts; 8067 8068 // Set the target CPU if specified. 8069 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8070 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8071 return nullptr; 8072 } 8073 8074 // Set the target ABI if specified. 8075 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8076 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8077 return nullptr; 8078 } 8079 8080 // Set the fp math unit. 8081 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8082 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8083 return nullptr; 8084 } 8085 8086 // Compute the default target features, we need the target to handle this 8087 // because features may have dependencies on one another. 8088 llvm::StringMap<bool> Features; 8089 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8090 Opts->FeaturesAsWritten)) 8091 return nullptr; 8092 8093 // Add the features to the compile options. 8094 Opts->Features.clear(); 8095 for (const auto &F : Features) 8096 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8097 8098 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8099 return nullptr; 8100 8101 return Target.release(); 8102 } 8103