1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "clang/Basic/Version.h" 23 #include "llvm/ADT/APFloat.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringExtras.h" 26 #include "llvm/ADT/StringRef.h" 27 #include "llvm/ADT/StringSwitch.h" 28 #include "llvm/ADT/Triple.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/TargetParser.h" 32 #include <algorithm> 33 #include <memory> 34 35 using namespace clang; 36 37 //===----------------------------------------------------------------------===// 38 // Common code shared among targets. 39 //===----------------------------------------------------------------------===// 40 41 /// DefineStd - Define a macro name and standard variants. For example if 42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 43 /// when in GNU mode. 44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 45 const LangOptions &Opts) { 46 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 47 48 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 49 // in the user's namespace. 50 if (Opts.GNUMode) 51 Builder.defineMacro(MacroName); 52 53 // Define __unix. 54 Builder.defineMacro("__" + MacroName); 55 56 // Define __unix__. 57 Builder.defineMacro("__" + MacroName + "__"); 58 } 59 60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 61 bool Tuning = true) { 62 Builder.defineMacro("__" + CPUName); 63 Builder.defineMacro("__" + CPUName + "__"); 64 if (Tuning) 65 Builder.defineMacro("__tune_" + CPUName + "__"); 66 } 67 68 //===----------------------------------------------------------------------===// 69 // Defines specific to certain operating systems. 70 //===----------------------------------------------------------------------===// 71 72 namespace { 73 template<typename TgtInfo> 74 class OSTargetInfo : public TgtInfo { 75 protected: 76 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 77 MacroBuilder &Builder) const=0; 78 public: 79 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 80 void getTargetDefines(const LangOptions &Opts, 81 MacroBuilder &Builder) const override { 82 TgtInfo::getTargetDefines(Opts, Builder); 83 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 84 } 85 86 }; 87 88 // CloudABI Target 89 template <typename Target> 90 class CloudABITargetInfo : public OSTargetInfo<Target> { 91 protected: 92 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 93 MacroBuilder &Builder) const override { 94 Builder.defineMacro("__CloudABI__"); 95 Builder.defineMacro("__ELF__"); 96 97 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 98 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 99 Builder.defineMacro("__STDC_UTF_16__"); 100 Builder.defineMacro("__STDC_UTF_32__"); 101 } 102 103 public: 104 CloudABITargetInfo(const llvm::Triple &Triple) 105 : OSTargetInfo<Target>(Triple) {} 106 }; 107 108 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 109 const llvm::Triple &Triple, 110 StringRef &PlatformName, 111 VersionTuple &PlatformMinVersion) { 112 Builder.defineMacro("__APPLE_CC__", "6000"); 113 Builder.defineMacro("__APPLE__"); 114 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 115 // AddressSanitizer doesn't play well with source fortification, which is on 116 // by default on Darwin. 117 if (Opts.Sanitize.has(SanitizerKind::Address)) 118 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 119 120 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 121 if (!Opts.ObjC1) { 122 // __weak is always defined, for use in blocks and with objc pointers. 123 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 124 Builder.defineMacro("__strong", ""); 125 Builder.defineMacro("__unsafe_unretained", ""); 126 } 127 128 if (Opts.Static) 129 Builder.defineMacro("__STATIC__"); 130 else 131 Builder.defineMacro("__DYNAMIC__"); 132 133 if (Opts.POSIXThreads) 134 Builder.defineMacro("_REENTRANT"); 135 136 // Get the platform type and version number from the triple. 137 unsigned Maj, Min, Rev; 138 if (Triple.isMacOSX()) { 139 Triple.getMacOSXVersion(Maj, Min, Rev); 140 PlatformName = "macosx"; 141 } else { 142 Triple.getOSVersion(Maj, Min, Rev); 143 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 144 } 145 146 // If -target arch-pc-win32-macho option specified, we're 147 // generating code for Win32 ABI. No need to emit 148 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 149 if (PlatformName == "win32") { 150 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 151 return; 152 } 153 154 // Set the appropriate OS version define. 155 if (Triple.isiOS()) { 156 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 157 char Str[6]; 158 Str[0] = '0' + Maj; 159 Str[1] = '0' + (Min / 10); 160 Str[2] = '0' + (Min % 10); 161 Str[3] = '0' + (Rev / 10); 162 Str[4] = '0' + (Rev % 10); 163 Str[5] = '\0'; 164 if (Triple.isTvOS()) 165 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 166 else 167 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 168 Str); 169 170 } else if (Triple.isWatchOS()) { 171 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 172 char Str[6]; 173 Str[0] = '0' + Maj; 174 Str[1] = '0' + (Min / 10); 175 Str[2] = '0' + (Min % 10); 176 Str[3] = '0' + (Rev / 10); 177 Str[4] = '0' + (Rev % 10); 178 Str[5] = '\0'; 179 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 180 } else if (Triple.isMacOSX()) { 181 // Note that the Driver allows versions which aren't representable in the 182 // define (because we only get a single digit for the minor and micro 183 // revision numbers). So, we limit them to the maximum representable 184 // version. 185 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 186 char Str[7]; 187 if (Maj < 10 || (Maj == 10 && Min < 10)) { 188 Str[0] = '0' + (Maj / 10); 189 Str[1] = '0' + (Maj % 10); 190 Str[2] = '0' + std::min(Min, 9U); 191 Str[3] = '0' + std::min(Rev, 9U); 192 Str[4] = '\0'; 193 } else { 194 // Handle versions > 10.9. 195 Str[0] = '0' + (Maj / 10); 196 Str[1] = '0' + (Maj % 10); 197 Str[2] = '0' + (Min / 10); 198 Str[3] = '0' + (Min % 10); 199 Str[4] = '0' + (Rev / 10); 200 Str[5] = '0' + (Rev % 10); 201 Str[6] = '\0'; 202 } 203 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 204 } 205 206 // Tell users about the kernel if there is one. 207 if (Triple.isOSDarwin()) 208 Builder.defineMacro("__MACH__"); 209 210 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 211 } 212 213 template<typename Target> 214 class DarwinTargetInfo : public OSTargetInfo<Target> { 215 protected: 216 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 217 MacroBuilder &Builder) const override { 218 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 219 this->PlatformMinVersion); 220 } 221 222 public: 223 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 224 // By default, no TLS, and we whitelist permitted architecture/OS 225 // combinations. 226 this->TLSSupported = false; 227 228 if (Triple.isMacOSX()) 229 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 230 else if (Triple.isiOS()) { 231 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 232 if (Triple.getArch() == llvm::Triple::x86_64 || 233 Triple.getArch() == llvm::Triple::aarch64) 234 this->TLSSupported = !Triple.isOSVersionLT(8); 235 else if (Triple.getArch() == llvm::Triple::x86 || 236 Triple.getArch() == llvm::Triple::arm || 237 Triple.getArch() == llvm::Triple::thumb) 238 this->TLSSupported = !Triple.isOSVersionLT(9); 239 } else if (Triple.isWatchOS()) 240 this->TLSSupported = !Triple.isOSVersionLT(2); 241 242 this->MCountName = "\01mcount"; 243 } 244 245 std::string isValidSectionSpecifier(StringRef SR) const override { 246 // Let MCSectionMachO validate this. 247 StringRef Segment, Section; 248 unsigned TAA, StubSize; 249 bool HasTAA; 250 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 251 TAA, HasTAA, StubSize); 252 } 253 254 const char *getStaticInitSectionSpecifier() const override { 255 // FIXME: We should return 0 when building kexts. 256 return "__TEXT,__StaticInit,regular,pure_instructions"; 257 } 258 259 /// Darwin does not support protected visibility. Darwin's "default" 260 /// is very similar to ELF's "protected"; Darwin requires a "weak" 261 /// attribute on declarations that can be dynamically replaced. 262 bool hasProtectedVisibility() const override { 263 return false; 264 } 265 }; 266 267 268 // DragonFlyBSD Target 269 template<typename Target> 270 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 271 protected: 272 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 273 MacroBuilder &Builder) const override { 274 // DragonFly defines; list based off of gcc output 275 Builder.defineMacro("__DragonFly__"); 276 Builder.defineMacro("__DragonFly_cc_version", "100001"); 277 Builder.defineMacro("__ELF__"); 278 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 279 Builder.defineMacro("__tune_i386__"); 280 DefineStd(Builder, "unix", Opts); 281 } 282 public: 283 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 284 : OSTargetInfo<Target>(Triple) { 285 switch (Triple.getArch()) { 286 default: 287 case llvm::Triple::x86: 288 case llvm::Triple::x86_64: 289 this->MCountName = ".mcount"; 290 break; 291 } 292 } 293 }; 294 295 // FreeBSD Target 296 template<typename Target> 297 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 298 protected: 299 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 300 MacroBuilder &Builder) const override { 301 // FreeBSD defines; list based off of gcc output 302 303 unsigned Release = Triple.getOSMajorVersion(); 304 if (Release == 0U) 305 Release = 8; 306 307 Builder.defineMacro("__FreeBSD__", Twine(Release)); 308 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 309 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 310 DefineStd(Builder, "unix", Opts); 311 Builder.defineMacro("__ELF__"); 312 313 // On FreeBSD, wchar_t contains the number of the code point as 314 // used by the character set of the locale. These character sets are 315 // not necessarily a superset of ASCII. 316 // 317 // FIXME: This is wrong; the macro refers to the numerical values 318 // of wchar_t *literals*, which are not locale-dependent. However, 319 // FreeBSD systems apparently depend on us getting this wrong, and 320 // setting this to 1 is conforming even if all the basic source 321 // character literals have the same encoding as char and wchar_t. 322 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 323 } 324 public: 325 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 326 switch (Triple.getArch()) { 327 default: 328 case llvm::Triple::x86: 329 case llvm::Triple::x86_64: 330 this->MCountName = ".mcount"; 331 break; 332 case llvm::Triple::mips: 333 case llvm::Triple::mipsel: 334 case llvm::Triple::ppc: 335 case llvm::Triple::ppc64: 336 case llvm::Triple::ppc64le: 337 this->MCountName = "_mcount"; 338 break; 339 case llvm::Triple::arm: 340 this->MCountName = "__mcount"; 341 break; 342 } 343 } 344 }; 345 346 // GNU/kFreeBSD Target 347 template<typename Target> 348 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 349 protected: 350 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 351 MacroBuilder &Builder) const override { 352 // GNU/kFreeBSD defines; list based off of gcc output 353 354 DefineStd(Builder, "unix", Opts); 355 Builder.defineMacro("__FreeBSD_kernel__"); 356 Builder.defineMacro("__GLIBC__"); 357 Builder.defineMacro("__ELF__"); 358 if (Opts.POSIXThreads) 359 Builder.defineMacro("_REENTRANT"); 360 if (Opts.CPlusPlus) 361 Builder.defineMacro("_GNU_SOURCE"); 362 } 363 public: 364 KFreeBSDTargetInfo(const llvm::Triple &Triple) 365 : OSTargetInfo<Target>(Triple) {} 366 }; 367 368 // Minix Target 369 template<typename Target> 370 class MinixTargetInfo : public OSTargetInfo<Target> { 371 protected: 372 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 373 MacroBuilder &Builder) const override { 374 // Minix defines 375 376 Builder.defineMacro("__minix", "3"); 377 Builder.defineMacro("_EM_WSIZE", "4"); 378 Builder.defineMacro("_EM_PSIZE", "4"); 379 Builder.defineMacro("_EM_SSIZE", "2"); 380 Builder.defineMacro("_EM_LSIZE", "4"); 381 Builder.defineMacro("_EM_FSIZE", "4"); 382 Builder.defineMacro("_EM_DSIZE", "8"); 383 Builder.defineMacro("__ELF__"); 384 DefineStd(Builder, "unix", Opts); 385 } 386 public: 387 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 388 }; 389 390 // Linux target 391 template<typename Target> 392 class LinuxTargetInfo : public OSTargetInfo<Target> { 393 protected: 394 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 395 MacroBuilder &Builder) const override { 396 // Linux defines; list based off of gcc output 397 DefineStd(Builder, "unix", Opts); 398 DefineStd(Builder, "linux", Opts); 399 Builder.defineMacro("__gnu_linux__"); 400 Builder.defineMacro("__ELF__"); 401 if (Triple.isAndroid()) { 402 Builder.defineMacro("__ANDROID__", "1"); 403 unsigned Maj, Min, Rev; 404 Triple.getEnvironmentVersion(Maj, Min, Rev); 405 this->PlatformName = "android"; 406 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 407 } 408 if (Opts.POSIXThreads) 409 Builder.defineMacro("_REENTRANT"); 410 if (Opts.CPlusPlus) 411 Builder.defineMacro("_GNU_SOURCE"); 412 } 413 public: 414 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 415 this->WIntType = TargetInfo::UnsignedInt; 416 417 switch (Triple.getArch()) { 418 default: 419 break; 420 case llvm::Triple::ppc: 421 case llvm::Triple::ppc64: 422 case llvm::Triple::ppc64le: 423 this->MCountName = "_mcount"; 424 break; 425 } 426 } 427 428 const char *getStaticInitSectionSpecifier() const override { 429 return ".text.startup"; 430 } 431 }; 432 433 // NetBSD Target 434 template<typename Target> 435 class NetBSDTargetInfo : public OSTargetInfo<Target> { 436 protected: 437 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 438 MacroBuilder &Builder) const override { 439 // NetBSD defines; list based off of gcc output 440 Builder.defineMacro("__NetBSD__"); 441 Builder.defineMacro("__unix__"); 442 Builder.defineMacro("__ELF__"); 443 if (Opts.POSIXThreads) 444 Builder.defineMacro("_POSIX_THREADS"); 445 446 switch (Triple.getArch()) { 447 default: 448 break; 449 case llvm::Triple::arm: 450 case llvm::Triple::armeb: 451 case llvm::Triple::thumb: 452 case llvm::Triple::thumbeb: 453 Builder.defineMacro("__ARM_DWARF_EH__"); 454 break; 455 } 456 } 457 public: 458 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 459 this->MCountName = "_mcount"; 460 } 461 }; 462 463 // OpenBSD Target 464 template<typename Target> 465 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 466 protected: 467 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 468 MacroBuilder &Builder) const override { 469 // OpenBSD defines; list based off of gcc output 470 471 Builder.defineMacro("__OpenBSD__"); 472 DefineStd(Builder, "unix", Opts); 473 Builder.defineMacro("__ELF__"); 474 if (Opts.POSIXThreads) 475 Builder.defineMacro("_REENTRANT"); 476 } 477 public: 478 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 479 this->TLSSupported = false; 480 481 switch (Triple.getArch()) { 482 default: 483 case llvm::Triple::x86: 484 case llvm::Triple::x86_64: 485 case llvm::Triple::arm: 486 case llvm::Triple::sparc: 487 this->MCountName = "__mcount"; 488 break; 489 case llvm::Triple::mips64: 490 case llvm::Triple::mips64el: 491 case llvm::Triple::ppc: 492 case llvm::Triple::sparcv9: 493 this->MCountName = "_mcount"; 494 break; 495 } 496 } 497 }; 498 499 // Bitrig Target 500 template<typename Target> 501 class BitrigTargetInfo : public OSTargetInfo<Target> { 502 protected: 503 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 504 MacroBuilder &Builder) const override { 505 // Bitrig defines; list based off of gcc output 506 507 Builder.defineMacro("__Bitrig__"); 508 DefineStd(Builder, "unix", Opts); 509 Builder.defineMacro("__ELF__"); 510 if (Opts.POSIXThreads) 511 Builder.defineMacro("_REENTRANT"); 512 513 switch (Triple.getArch()) { 514 default: 515 break; 516 case llvm::Triple::arm: 517 case llvm::Triple::armeb: 518 case llvm::Triple::thumb: 519 case llvm::Triple::thumbeb: 520 Builder.defineMacro("__ARM_DWARF_EH__"); 521 break; 522 } 523 } 524 public: 525 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 526 this->MCountName = "__mcount"; 527 } 528 }; 529 530 // PSP Target 531 template<typename Target> 532 class PSPTargetInfo : public OSTargetInfo<Target> { 533 protected: 534 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 535 MacroBuilder &Builder) const override { 536 // PSP defines; list based on the output of the pspdev gcc toolchain. 537 Builder.defineMacro("PSP"); 538 Builder.defineMacro("_PSP"); 539 Builder.defineMacro("__psp__"); 540 Builder.defineMacro("__ELF__"); 541 } 542 public: 543 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 544 }; 545 546 // PS3 PPU Target 547 template<typename Target> 548 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 549 protected: 550 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 551 MacroBuilder &Builder) const override { 552 // PS3 PPU defines. 553 Builder.defineMacro("__PPC__"); 554 Builder.defineMacro("__PPU__"); 555 Builder.defineMacro("__CELLOS_LV2__"); 556 Builder.defineMacro("__ELF__"); 557 Builder.defineMacro("__LP32__"); 558 Builder.defineMacro("_ARCH_PPC64"); 559 Builder.defineMacro("__powerpc64__"); 560 } 561 public: 562 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 563 this->LongWidth = this->LongAlign = 32; 564 this->PointerWidth = this->PointerAlign = 32; 565 this->IntMaxType = TargetInfo::SignedLongLong; 566 this->Int64Type = TargetInfo::SignedLongLong; 567 this->SizeType = TargetInfo::UnsignedInt; 568 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 569 } 570 }; 571 572 template <typename Target> 573 class PS4OSTargetInfo : public OSTargetInfo<Target> { 574 protected: 575 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 576 MacroBuilder &Builder) const override { 577 Builder.defineMacro("__FreeBSD__", "9"); 578 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 579 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 580 DefineStd(Builder, "unix", Opts); 581 Builder.defineMacro("__ELF__"); 582 Builder.defineMacro("__PS4__"); 583 } 584 public: 585 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 586 this->WCharType = this->UnsignedShort; 587 588 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 589 this->MaxTLSAlign = 256; 590 591 // On PS4, do not honor explicit bit field alignment, 592 // as in "__attribute__((aligned(2))) int b : 1;". 593 this->UseExplicitBitFieldAlignment = false; 594 595 switch (Triple.getArch()) { 596 default: 597 case llvm::Triple::x86_64: 598 this->MCountName = ".mcount"; 599 break; 600 } 601 } 602 }; 603 604 // Solaris target 605 template<typename Target> 606 class SolarisTargetInfo : public OSTargetInfo<Target> { 607 protected: 608 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 609 MacroBuilder &Builder) const override { 610 DefineStd(Builder, "sun", Opts); 611 DefineStd(Builder, "unix", Opts); 612 Builder.defineMacro("__ELF__"); 613 Builder.defineMacro("__svr4__"); 614 Builder.defineMacro("__SVR4"); 615 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 616 // newer, but to 500 for everything else. feature_test.h has a check to 617 // ensure that you are not using C99 with an old version of X/Open or C89 618 // with a new version. 619 if (Opts.C99) 620 Builder.defineMacro("_XOPEN_SOURCE", "600"); 621 else 622 Builder.defineMacro("_XOPEN_SOURCE", "500"); 623 if (Opts.CPlusPlus) 624 Builder.defineMacro("__C99FEATURES__"); 625 Builder.defineMacro("_LARGEFILE_SOURCE"); 626 Builder.defineMacro("_LARGEFILE64_SOURCE"); 627 Builder.defineMacro("__EXTENSIONS__"); 628 Builder.defineMacro("_REENTRANT"); 629 } 630 public: 631 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 632 this->WCharType = this->SignedInt; 633 // FIXME: WIntType should be SignedLong 634 } 635 }; 636 637 // Windows target 638 template<typename Target> 639 class WindowsTargetInfo : public OSTargetInfo<Target> { 640 protected: 641 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 642 MacroBuilder &Builder) const override { 643 Builder.defineMacro("_WIN32"); 644 } 645 void getVisualStudioDefines(const LangOptions &Opts, 646 MacroBuilder &Builder) const { 647 if (Opts.CPlusPlus) { 648 if (Opts.RTTIData) 649 Builder.defineMacro("_CPPRTTI"); 650 651 if (Opts.CXXExceptions) 652 Builder.defineMacro("_CPPUNWIND"); 653 } 654 655 if (Opts.Bool) 656 Builder.defineMacro("__BOOL_DEFINED"); 657 658 if (!Opts.CharIsSigned) 659 Builder.defineMacro("_CHAR_UNSIGNED"); 660 661 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 662 // but it works for now. 663 if (Opts.POSIXThreads) 664 Builder.defineMacro("_MT"); 665 666 if (Opts.MSCompatibilityVersion) { 667 Builder.defineMacro("_MSC_VER", 668 Twine(Opts.MSCompatibilityVersion / 100000)); 669 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 670 // FIXME We cannot encode the revision information into 32-bits 671 Builder.defineMacro("_MSC_BUILD", Twine(1)); 672 673 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 674 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 675 } 676 677 if (Opts.MicrosoftExt) { 678 Builder.defineMacro("_MSC_EXTENSIONS"); 679 680 if (Opts.CPlusPlus11) { 681 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 682 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 683 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 684 } 685 } 686 687 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 688 } 689 690 public: 691 WindowsTargetInfo(const llvm::Triple &Triple) 692 : OSTargetInfo<Target>(Triple) {} 693 }; 694 695 template <typename Target> 696 class NaClTargetInfo : public OSTargetInfo<Target> { 697 protected: 698 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 699 MacroBuilder &Builder) const override { 700 if (Opts.POSIXThreads) 701 Builder.defineMacro("_REENTRANT"); 702 if (Opts.CPlusPlus) 703 Builder.defineMacro("_GNU_SOURCE"); 704 705 DefineStd(Builder, "unix", Opts); 706 Builder.defineMacro("__ELF__"); 707 Builder.defineMacro("__native_client__"); 708 } 709 710 public: 711 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 712 this->LongAlign = 32; 713 this->LongWidth = 32; 714 this->PointerAlign = 32; 715 this->PointerWidth = 32; 716 this->IntMaxType = TargetInfo::SignedLongLong; 717 this->Int64Type = TargetInfo::SignedLongLong; 718 this->DoubleAlign = 64; 719 this->LongDoubleWidth = 64; 720 this->LongDoubleAlign = 64; 721 this->LongLongWidth = 64; 722 this->LongLongAlign = 64; 723 this->SizeType = TargetInfo::UnsignedInt; 724 this->PtrDiffType = TargetInfo::SignedInt; 725 this->IntPtrType = TargetInfo::SignedInt; 726 // RegParmMax is inherited from the underlying architecture 727 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 728 if (Triple.getArch() == llvm::Triple::arm) { 729 // Handled in ARM's setABI(). 730 } else if (Triple.getArch() == llvm::Triple::x86) { 731 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 732 } else if (Triple.getArch() == llvm::Triple::x86_64) { 733 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 734 } else if (Triple.getArch() == llvm::Triple::mipsel) { 735 // Handled on mips' setDataLayout. 736 } else { 737 assert(Triple.getArch() == llvm::Triple::le32); 738 this->resetDataLayout("e-p:32:32-i64:64"); 739 } 740 } 741 }; 742 743 // WebAssembly target 744 template <typename Target> 745 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 746 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 747 MacroBuilder &Builder) const final { 748 // A common platform macro. 749 if (Opts.POSIXThreads) 750 Builder.defineMacro("_REENTRANT"); 751 // Follow g++ convention and predefine _GNU_SOURCE for C++. 752 if (Opts.CPlusPlus) 753 Builder.defineMacro("_GNU_SOURCE"); 754 } 755 756 // As an optimization, group static init code together in a section. 757 const char *getStaticInitSectionSpecifier() const final { 758 return ".text.__startup"; 759 } 760 761 public: 762 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple) 763 : OSTargetInfo<Target>(Triple) { 764 this->MCountName = "__mcount"; 765 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 766 } 767 }; 768 769 //===----------------------------------------------------------------------===// 770 // Specific target implementations. 771 //===----------------------------------------------------------------------===// 772 773 // PPC abstract base class 774 class PPCTargetInfo : public TargetInfo { 775 static const Builtin::Info BuiltinInfo[]; 776 static const char * const GCCRegNames[]; 777 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 778 std::string CPU; 779 780 // Target cpu features. 781 bool HasVSX; 782 bool HasP8Vector; 783 bool HasP8Crypto; 784 bool HasDirectMove; 785 bool HasQPX; 786 bool HasHTM; 787 bool HasBPERMD; 788 bool HasExtDiv; 789 790 protected: 791 std::string ABI; 792 793 public: 794 PPCTargetInfo(const llvm::Triple &Triple) 795 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 796 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 797 HasBPERMD(false), HasExtDiv(false) { 798 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 799 SimdDefaultAlign = 128; 800 LongDoubleWidth = LongDoubleAlign = 128; 801 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 802 } 803 804 /// \brief Flags for architecture specific defines. 805 typedef enum { 806 ArchDefineNone = 0, 807 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 808 ArchDefinePpcgr = 1 << 1, 809 ArchDefinePpcsq = 1 << 2, 810 ArchDefine440 = 1 << 3, 811 ArchDefine603 = 1 << 4, 812 ArchDefine604 = 1 << 5, 813 ArchDefinePwr4 = 1 << 6, 814 ArchDefinePwr5 = 1 << 7, 815 ArchDefinePwr5x = 1 << 8, 816 ArchDefinePwr6 = 1 << 9, 817 ArchDefinePwr6x = 1 << 10, 818 ArchDefinePwr7 = 1 << 11, 819 ArchDefinePwr8 = 1 << 12, 820 ArchDefineA2 = 1 << 13, 821 ArchDefineA2q = 1 << 14 822 } ArchDefineTypes; 823 824 // Note: GCC recognizes the following additional cpus: 825 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 826 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 827 // titan, rs64. 828 bool setCPU(const std::string &Name) override { 829 bool CPUKnown = llvm::StringSwitch<bool>(Name) 830 .Case("generic", true) 831 .Case("440", true) 832 .Case("450", true) 833 .Case("601", true) 834 .Case("602", true) 835 .Case("603", true) 836 .Case("603e", true) 837 .Case("603ev", true) 838 .Case("604", true) 839 .Case("604e", true) 840 .Case("620", true) 841 .Case("630", true) 842 .Case("g3", true) 843 .Case("7400", true) 844 .Case("g4", true) 845 .Case("7450", true) 846 .Case("g4+", true) 847 .Case("750", true) 848 .Case("970", true) 849 .Case("g5", true) 850 .Case("a2", true) 851 .Case("a2q", true) 852 .Case("e500mc", true) 853 .Case("e5500", true) 854 .Case("power3", true) 855 .Case("pwr3", true) 856 .Case("power4", true) 857 .Case("pwr4", true) 858 .Case("power5", true) 859 .Case("pwr5", true) 860 .Case("power5x", true) 861 .Case("pwr5x", true) 862 .Case("power6", true) 863 .Case("pwr6", true) 864 .Case("power6x", true) 865 .Case("pwr6x", true) 866 .Case("power7", true) 867 .Case("pwr7", true) 868 .Case("power8", true) 869 .Case("pwr8", true) 870 .Case("powerpc", true) 871 .Case("ppc", true) 872 .Case("powerpc64", true) 873 .Case("ppc64", true) 874 .Case("powerpc64le", true) 875 .Case("ppc64le", true) 876 .Default(false); 877 878 if (CPUKnown) 879 CPU = Name; 880 881 return CPUKnown; 882 } 883 884 885 StringRef getABI() const override { return ABI; } 886 887 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 888 return llvm::makeArrayRef(BuiltinInfo, 889 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 890 } 891 892 bool isCLZForZeroUndef() const override { return false; } 893 894 void getTargetDefines(const LangOptions &Opts, 895 MacroBuilder &Builder) const override; 896 897 bool 898 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 899 StringRef CPU, 900 const std::vector<std::string> &FeaturesVec) const override; 901 902 bool handleTargetFeatures(std::vector<std::string> &Features, 903 DiagnosticsEngine &Diags) override; 904 bool hasFeature(StringRef Feature) const override; 905 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 906 bool Enabled) const override; 907 908 ArrayRef<const char *> getGCCRegNames() const override; 909 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 910 bool validateAsmConstraint(const char *&Name, 911 TargetInfo::ConstraintInfo &Info) const override { 912 switch (*Name) { 913 default: return false; 914 case 'O': // Zero 915 break; 916 case 'b': // Base register 917 case 'f': // Floating point register 918 Info.setAllowsRegister(); 919 break; 920 // FIXME: The following are added to allow parsing. 921 // I just took a guess at what the actions should be. 922 // Also, is more specific checking needed? I.e. specific registers? 923 case 'd': // Floating point register (containing 64-bit value) 924 case 'v': // Altivec vector register 925 Info.setAllowsRegister(); 926 break; 927 case 'w': 928 switch (Name[1]) { 929 case 'd':// VSX vector register to hold vector double data 930 case 'f':// VSX vector register to hold vector float data 931 case 's':// VSX vector register to hold scalar float data 932 case 'a':// Any VSX register 933 case 'c':// An individual CR bit 934 break; 935 default: 936 return false; 937 } 938 Info.setAllowsRegister(); 939 Name++; // Skip over 'w'. 940 break; 941 case 'h': // `MQ', `CTR', or `LINK' register 942 case 'q': // `MQ' register 943 case 'c': // `CTR' register 944 case 'l': // `LINK' register 945 case 'x': // `CR' register (condition register) number 0 946 case 'y': // `CR' register (condition register) 947 case 'z': // `XER[CA]' carry bit (part of the XER register) 948 Info.setAllowsRegister(); 949 break; 950 case 'I': // Signed 16-bit constant 951 case 'J': // Unsigned 16-bit constant shifted left 16 bits 952 // (use `L' instead for SImode constants) 953 case 'K': // Unsigned 16-bit constant 954 case 'L': // Signed 16-bit constant shifted left 16 bits 955 case 'M': // Constant larger than 31 956 case 'N': // Exact power of 2 957 case 'P': // Constant whose negation is a signed 16-bit constant 958 case 'G': // Floating point constant that can be loaded into a 959 // register with one instruction per word 960 case 'H': // Integer/Floating point constant that can be loaded 961 // into a register using three instructions 962 break; 963 case 'm': // Memory operand. Note that on PowerPC targets, m can 964 // include addresses that update the base register. It 965 // is therefore only safe to use `m' in an asm statement 966 // if that asm statement accesses the operand exactly once. 967 // The asm statement must also use `%U<opno>' as a 968 // placeholder for the "update" flag in the corresponding 969 // load or store instruction. For example: 970 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 971 // is correct but: 972 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 973 // is not. Use es rather than m if you don't want the base 974 // register to be updated. 975 case 'e': 976 if (Name[1] != 's') 977 return false; 978 // es: A "stable" memory operand; that is, one which does not 979 // include any automodification of the base register. Unlike 980 // `m', this constraint can be used in asm statements that 981 // might access the operand several times, or that might not 982 // access it at all. 983 Info.setAllowsMemory(); 984 Name++; // Skip over 'e'. 985 break; 986 case 'Q': // Memory operand that is an offset from a register (it is 987 // usually better to use `m' or `es' in asm statements) 988 case 'Z': // Memory operand that is an indexed or indirect from a 989 // register (it is usually better to use `m' or `es' in 990 // asm statements) 991 Info.setAllowsMemory(); 992 Info.setAllowsRegister(); 993 break; 994 case 'R': // AIX TOC entry 995 case 'a': // Address operand that is an indexed or indirect from a 996 // register (`p' is preferable for asm statements) 997 case 'S': // Constant suitable as a 64-bit mask operand 998 case 'T': // Constant suitable as a 32-bit mask operand 999 case 'U': // System V Release 4 small data area reference 1000 case 't': // AND masks that can be performed by two rldic{l, r} 1001 // instructions 1002 case 'W': // Vector constant that does not require memory 1003 case 'j': // Vector constant that is all zeros. 1004 break; 1005 // End FIXME. 1006 } 1007 return true; 1008 } 1009 std::string convertConstraint(const char *&Constraint) const override { 1010 std::string R; 1011 switch (*Constraint) { 1012 case 'e': 1013 case 'w': 1014 // Two-character constraint; add "^" hint for later parsing. 1015 R = std::string("^") + std::string(Constraint, 2); 1016 Constraint++; 1017 break; 1018 default: 1019 return TargetInfo::convertConstraint(Constraint); 1020 } 1021 return R; 1022 } 1023 const char *getClobbers() const override { 1024 return ""; 1025 } 1026 int getEHDataRegisterNumber(unsigned RegNo) const override { 1027 if (RegNo == 0) return 3; 1028 if (RegNo == 1) return 4; 1029 return -1; 1030 } 1031 1032 bool hasSjLjLowering() const override { 1033 return true; 1034 } 1035 1036 bool useFloat128ManglingForLongDouble() const override { 1037 return LongDoubleWidth == 128 && 1038 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1039 getTriple().isOSBinFormatELF(); 1040 } 1041 }; 1042 1043 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1044 #define BUILTIN(ID, TYPE, ATTRS) \ 1045 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1046 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1047 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1048 #include "clang/Basic/BuiltinsPPC.def" 1049 }; 1050 1051 /// handleTargetFeatures - Perform initialization based on the user 1052 /// configured set of features. 1053 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1054 DiagnosticsEngine &Diags) { 1055 for (const auto &Feature : Features) { 1056 if (Feature == "+vsx") { 1057 HasVSX = true; 1058 } else if (Feature == "+bpermd") { 1059 HasBPERMD = true; 1060 } else if (Feature == "+extdiv") { 1061 HasExtDiv = true; 1062 } else if (Feature == "+power8-vector") { 1063 HasP8Vector = true; 1064 } else if (Feature == "+crypto") { 1065 HasP8Crypto = true; 1066 } else if (Feature == "+direct-move") { 1067 HasDirectMove = true; 1068 } else if (Feature == "+qpx") { 1069 HasQPX = true; 1070 } else if (Feature == "+htm") { 1071 HasHTM = true; 1072 } 1073 // TODO: Finish this list and add an assert that we've handled them 1074 // all. 1075 } 1076 1077 return true; 1078 } 1079 1080 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1081 /// #defines that are not tied to a specific subtarget. 1082 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1083 MacroBuilder &Builder) const { 1084 // Target identification. 1085 Builder.defineMacro("__ppc__"); 1086 Builder.defineMacro("__PPC__"); 1087 Builder.defineMacro("_ARCH_PPC"); 1088 Builder.defineMacro("__powerpc__"); 1089 Builder.defineMacro("__POWERPC__"); 1090 if (PointerWidth == 64) { 1091 Builder.defineMacro("_ARCH_PPC64"); 1092 Builder.defineMacro("__powerpc64__"); 1093 Builder.defineMacro("__ppc64__"); 1094 Builder.defineMacro("__PPC64__"); 1095 } 1096 1097 // Target properties. 1098 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1099 Builder.defineMacro("_LITTLE_ENDIAN"); 1100 } else { 1101 if (getTriple().getOS() != llvm::Triple::NetBSD && 1102 getTriple().getOS() != llvm::Triple::OpenBSD) 1103 Builder.defineMacro("_BIG_ENDIAN"); 1104 } 1105 1106 // ABI options. 1107 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1108 Builder.defineMacro("_CALL_ELF", "1"); 1109 if (ABI == "elfv2") 1110 Builder.defineMacro("_CALL_ELF", "2"); 1111 1112 // Subtarget options. 1113 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1114 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1115 1116 // FIXME: Should be controlled by command line option. 1117 if (LongDoubleWidth == 128) 1118 Builder.defineMacro("__LONG_DOUBLE_128__"); 1119 1120 if (Opts.AltiVec) { 1121 Builder.defineMacro("__VEC__", "10206"); 1122 Builder.defineMacro("__ALTIVEC__"); 1123 } 1124 1125 // CPU identification. 1126 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1127 .Case("440", ArchDefineName) 1128 .Case("450", ArchDefineName | ArchDefine440) 1129 .Case("601", ArchDefineName) 1130 .Case("602", ArchDefineName | ArchDefinePpcgr) 1131 .Case("603", ArchDefineName | ArchDefinePpcgr) 1132 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1133 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1134 .Case("604", ArchDefineName | ArchDefinePpcgr) 1135 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1136 .Case("620", ArchDefineName | ArchDefinePpcgr) 1137 .Case("630", ArchDefineName | ArchDefinePpcgr) 1138 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1139 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1140 .Case("750", ArchDefineName | ArchDefinePpcgr) 1141 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1142 | ArchDefinePpcsq) 1143 .Case("a2", ArchDefineA2) 1144 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1145 .Case("pwr3", ArchDefinePpcgr) 1146 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1147 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1148 | ArchDefinePpcsq) 1149 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1150 | ArchDefinePpcgr | ArchDefinePpcsq) 1151 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1152 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1153 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1154 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1155 | ArchDefinePpcsq) 1156 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1157 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1158 | ArchDefinePpcgr | ArchDefinePpcsq) 1159 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1160 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1161 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1162 .Case("power3", ArchDefinePpcgr) 1163 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1164 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1165 | ArchDefinePpcsq) 1166 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1167 | ArchDefinePpcgr | ArchDefinePpcsq) 1168 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1169 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1170 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1171 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1172 | ArchDefinePpcsq) 1173 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1174 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1175 | ArchDefinePpcgr | ArchDefinePpcsq) 1176 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1177 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1178 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1179 .Default(ArchDefineNone); 1180 1181 if (defs & ArchDefineName) 1182 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1183 if (defs & ArchDefinePpcgr) 1184 Builder.defineMacro("_ARCH_PPCGR"); 1185 if (defs & ArchDefinePpcsq) 1186 Builder.defineMacro("_ARCH_PPCSQ"); 1187 if (defs & ArchDefine440) 1188 Builder.defineMacro("_ARCH_440"); 1189 if (defs & ArchDefine603) 1190 Builder.defineMacro("_ARCH_603"); 1191 if (defs & ArchDefine604) 1192 Builder.defineMacro("_ARCH_604"); 1193 if (defs & ArchDefinePwr4) 1194 Builder.defineMacro("_ARCH_PWR4"); 1195 if (defs & ArchDefinePwr5) 1196 Builder.defineMacro("_ARCH_PWR5"); 1197 if (defs & ArchDefinePwr5x) 1198 Builder.defineMacro("_ARCH_PWR5X"); 1199 if (defs & ArchDefinePwr6) 1200 Builder.defineMacro("_ARCH_PWR6"); 1201 if (defs & ArchDefinePwr6x) 1202 Builder.defineMacro("_ARCH_PWR6X"); 1203 if (defs & ArchDefinePwr7) 1204 Builder.defineMacro("_ARCH_PWR7"); 1205 if (defs & ArchDefinePwr8) 1206 Builder.defineMacro("_ARCH_PWR8"); 1207 if (defs & ArchDefineA2) 1208 Builder.defineMacro("_ARCH_A2"); 1209 if (defs & ArchDefineA2q) { 1210 Builder.defineMacro("_ARCH_A2Q"); 1211 Builder.defineMacro("_ARCH_QP"); 1212 } 1213 1214 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1215 Builder.defineMacro("__bg__"); 1216 Builder.defineMacro("__THW_BLUEGENE__"); 1217 Builder.defineMacro("__bgq__"); 1218 Builder.defineMacro("__TOS_BGQ__"); 1219 } 1220 1221 if (HasVSX) 1222 Builder.defineMacro("__VSX__"); 1223 if (HasP8Vector) 1224 Builder.defineMacro("__POWER8_VECTOR__"); 1225 if (HasP8Crypto) 1226 Builder.defineMacro("__CRYPTO__"); 1227 if (HasHTM) 1228 Builder.defineMacro("__HTM__"); 1229 1230 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1231 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1232 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1233 if (PointerWidth == 64) 1234 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1235 1236 // FIXME: The following are not yet generated here by Clang, but are 1237 // generated by GCC: 1238 // 1239 // _SOFT_FLOAT_ 1240 // __RECIP_PRECISION__ 1241 // __APPLE_ALTIVEC__ 1242 // __RECIP__ 1243 // __RECIPF__ 1244 // __RSQRTE__ 1245 // __RSQRTEF__ 1246 // _SOFT_DOUBLE_ 1247 // __NO_LWSYNC__ 1248 // __HAVE_BSWAP__ 1249 // __LONGDOUBLE128 1250 // __CMODEL_MEDIUM__ 1251 // __CMODEL_LARGE__ 1252 // _CALL_SYSV 1253 // _CALL_DARWIN 1254 // __NO_FPRS__ 1255 } 1256 1257 // Handle explicit options being passed to the compiler here: if we've 1258 // explicitly turned off vsx and turned on power8-vector or direct-move then 1259 // go ahead and error since the customer has expressed a somewhat incompatible 1260 // set of options. 1261 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1262 const std::vector<std::string> &FeaturesVec) { 1263 1264 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1265 FeaturesVec.end()) { 1266 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1267 FeaturesVec.end()) { 1268 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1269 << "-mno-vsx"; 1270 return false; 1271 } 1272 1273 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1274 FeaturesVec.end()) { 1275 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1276 << "-mno-vsx"; 1277 return false; 1278 } 1279 } 1280 1281 return true; 1282 } 1283 1284 bool PPCTargetInfo::initFeatureMap( 1285 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1286 const std::vector<std::string> &FeaturesVec) const { 1287 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1288 .Case("7400", true) 1289 .Case("g4", true) 1290 .Case("7450", true) 1291 .Case("g4+", true) 1292 .Case("970", true) 1293 .Case("g5", true) 1294 .Case("pwr6", true) 1295 .Case("pwr7", true) 1296 .Case("pwr8", true) 1297 .Case("ppc64", true) 1298 .Case("ppc64le", true) 1299 .Default(false); 1300 1301 Features["qpx"] = (CPU == "a2q"); 1302 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1303 .Case("ppc64le", true) 1304 .Case("pwr8", true) 1305 .Default(false); 1306 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1307 .Case("ppc64le", true) 1308 .Case("pwr8", true) 1309 .Default(false); 1310 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1311 .Case("ppc64le", true) 1312 .Case("pwr8", true) 1313 .Case("pwr7", true) 1314 .Default(false); 1315 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1316 .Case("ppc64le", true) 1317 .Case("pwr8", true) 1318 .Case("pwr7", true) 1319 .Default(false); 1320 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1321 .Case("ppc64le", true) 1322 .Case("pwr8", true) 1323 .Default(false); 1324 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1325 .Case("ppc64le", true) 1326 .Case("pwr8", true) 1327 .Case("pwr7", true) 1328 .Default(false); 1329 1330 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1331 return false; 1332 1333 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1334 } 1335 1336 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1337 return llvm::StringSwitch<bool>(Feature) 1338 .Case("powerpc", true) 1339 .Case("vsx", HasVSX) 1340 .Case("power8-vector", HasP8Vector) 1341 .Case("crypto", HasP8Crypto) 1342 .Case("direct-move", HasDirectMove) 1343 .Case("qpx", HasQPX) 1344 .Case("htm", HasHTM) 1345 .Case("bpermd", HasBPERMD) 1346 .Case("extdiv", HasExtDiv) 1347 .Default(false); 1348 } 1349 1350 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1351 StringRef Name, bool Enabled) const { 1352 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1353 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1354 // incompatible options. 1355 if (Enabled) { 1356 if (Name == "vsx") { 1357 Features[Name] = true; 1358 } else if (Name == "direct-move") { 1359 Features[Name] = Features["vsx"] = true; 1360 } else if (Name == "power8-vector") { 1361 Features[Name] = Features["vsx"] = true; 1362 } else { 1363 Features[Name] = true; 1364 } 1365 } else { 1366 if (Name == "vsx") { 1367 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1368 false; 1369 } else { 1370 Features[Name] = false; 1371 } 1372 } 1373 } 1374 1375 const char * const PPCTargetInfo::GCCRegNames[] = { 1376 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1377 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1378 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1379 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1380 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1381 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1382 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1383 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1384 "mq", "lr", "ctr", "ap", 1385 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1386 "xer", 1387 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1388 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1389 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1390 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1391 "vrsave", "vscr", 1392 "spe_acc", "spefscr", 1393 "sfp" 1394 }; 1395 1396 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1397 return llvm::makeArrayRef(GCCRegNames); 1398 } 1399 1400 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1401 // While some of these aliases do map to different registers 1402 // they still share the same register name. 1403 { { "0" }, "r0" }, 1404 { { "1"}, "r1" }, 1405 { { "2" }, "r2" }, 1406 { { "3" }, "r3" }, 1407 { { "4" }, "r4" }, 1408 { { "5" }, "r5" }, 1409 { { "6" }, "r6" }, 1410 { { "7" }, "r7" }, 1411 { { "8" }, "r8" }, 1412 { { "9" }, "r9" }, 1413 { { "10" }, "r10" }, 1414 { { "11" }, "r11" }, 1415 { { "12" }, "r12" }, 1416 { { "13" }, "r13" }, 1417 { { "14" }, "r14" }, 1418 { { "15" }, "r15" }, 1419 { { "16" }, "r16" }, 1420 { { "17" }, "r17" }, 1421 { { "18" }, "r18" }, 1422 { { "19" }, "r19" }, 1423 { { "20" }, "r20" }, 1424 { { "21" }, "r21" }, 1425 { { "22" }, "r22" }, 1426 { { "23" }, "r23" }, 1427 { { "24" }, "r24" }, 1428 { { "25" }, "r25" }, 1429 { { "26" }, "r26" }, 1430 { { "27" }, "r27" }, 1431 { { "28" }, "r28" }, 1432 { { "29" }, "r29" }, 1433 { { "30" }, "r30" }, 1434 { { "31" }, "r31" }, 1435 { { "fr0" }, "f0" }, 1436 { { "fr1" }, "f1" }, 1437 { { "fr2" }, "f2" }, 1438 { { "fr3" }, "f3" }, 1439 { { "fr4" }, "f4" }, 1440 { { "fr5" }, "f5" }, 1441 { { "fr6" }, "f6" }, 1442 { { "fr7" }, "f7" }, 1443 { { "fr8" }, "f8" }, 1444 { { "fr9" }, "f9" }, 1445 { { "fr10" }, "f10" }, 1446 { { "fr11" }, "f11" }, 1447 { { "fr12" }, "f12" }, 1448 { { "fr13" }, "f13" }, 1449 { { "fr14" }, "f14" }, 1450 { { "fr15" }, "f15" }, 1451 { { "fr16" }, "f16" }, 1452 { { "fr17" }, "f17" }, 1453 { { "fr18" }, "f18" }, 1454 { { "fr19" }, "f19" }, 1455 { { "fr20" }, "f20" }, 1456 { { "fr21" }, "f21" }, 1457 { { "fr22" }, "f22" }, 1458 { { "fr23" }, "f23" }, 1459 { { "fr24" }, "f24" }, 1460 { { "fr25" }, "f25" }, 1461 { { "fr26" }, "f26" }, 1462 { { "fr27" }, "f27" }, 1463 { { "fr28" }, "f28" }, 1464 { { "fr29" }, "f29" }, 1465 { { "fr30" }, "f30" }, 1466 { { "fr31" }, "f31" }, 1467 { { "cc" }, "cr0" }, 1468 }; 1469 1470 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1471 return llvm::makeArrayRef(GCCRegAliases); 1472 } 1473 1474 class PPC32TargetInfo : public PPCTargetInfo { 1475 public: 1476 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1477 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1478 1479 switch (getTriple().getOS()) { 1480 case llvm::Triple::Linux: 1481 case llvm::Triple::FreeBSD: 1482 case llvm::Triple::NetBSD: 1483 SizeType = UnsignedInt; 1484 PtrDiffType = SignedInt; 1485 IntPtrType = SignedInt; 1486 break; 1487 default: 1488 break; 1489 } 1490 1491 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1492 LongDoubleWidth = LongDoubleAlign = 64; 1493 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1494 } 1495 1496 // PPC32 supports atomics up to 4 bytes. 1497 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1498 } 1499 1500 BuiltinVaListKind getBuiltinVaListKind() const override { 1501 // This is the ELF definition, and is overridden by the Darwin sub-target 1502 return TargetInfo::PowerABIBuiltinVaList; 1503 } 1504 }; 1505 1506 // Note: ABI differences may eventually require us to have a separate 1507 // TargetInfo for little endian. 1508 class PPC64TargetInfo : public PPCTargetInfo { 1509 public: 1510 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1511 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1512 IntMaxType = SignedLong; 1513 Int64Type = SignedLong; 1514 1515 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1516 resetDataLayout("e-m:e-i64:64-n32:64"); 1517 ABI = "elfv2"; 1518 } else { 1519 resetDataLayout("E-m:e-i64:64-n32:64"); 1520 ABI = "elfv1"; 1521 } 1522 1523 switch (getTriple().getOS()) { 1524 case llvm::Triple::FreeBSD: 1525 LongDoubleWidth = LongDoubleAlign = 64; 1526 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1527 break; 1528 case llvm::Triple::NetBSD: 1529 IntMaxType = SignedLongLong; 1530 Int64Type = SignedLongLong; 1531 break; 1532 default: 1533 break; 1534 } 1535 1536 // PPC64 supports atomics up to 8 bytes. 1537 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1538 } 1539 BuiltinVaListKind getBuiltinVaListKind() const override { 1540 return TargetInfo::CharPtrBuiltinVaList; 1541 } 1542 // PPC64 Linux-specific ABI options. 1543 bool setABI(const std::string &Name) override { 1544 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1545 ABI = Name; 1546 return true; 1547 } 1548 return false; 1549 } 1550 }; 1551 1552 class DarwinPPC32TargetInfo : 1553 public DarwinTargetInfo<PPC32TargetInfo> { 1554 public: 1555 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1556 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1557 HasAlignMac68kSupport = true; 1558 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1559 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1560 LongLongAlign = 32; 1561 SuitableAlign = 128; 1562 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1563 } 1564 BuiltinVaListKind getBuiltinVaListKind() const override { 1565 return TargetInfo::CharPtrBuiltinVaList; 1566 } 1567 }; 1568 1569 class DarwinPPC64TargetInfo : 1570 public DarwinTargetInfo<PPC64TargetInfo> { 1571 public: 1572 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1573 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1574 HasAlignMac68kSupport = true; 1575 SuitableAlign = 128; 1576 resetDataLayout("E-m:o-i64:64-n32:64"); 1577 } 1578 }; 1579 1580 static const unsigned NVPTXAddrSpaceMap[] = { 1581 1, // opencl_global 1582 3, // opencl_local 1583 4, // opencl_constant 1584 // FIXME: generic has to be added to the target 1585 0, // opencl_generic 1586 1, // cuda_device 1587 4, // cuda_constant 1588 3, // cuda_shared 1589 }; 1590 1591 class NVPTXTargetInfo : public TargetInfo { 1592 static const char *const GCCRegNames[]; 1593 static const Builtin::Info BuiltinInfo[]; 1594 1595 // The GPU profiles supported by the NVPTX backend 1596 enum GPUKind { 1597 GK_NONE, 1598 GK_SM20, 1599 GK_SM21, 1600 GK_SM30, 1601 GK_SM35, 1602 GK_SM37, 1603 } GPU; 1604 1605 public: 1606 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1607 BigEndian = false; 1608 TLSSupported = false; 1609 LongWidth = LongAlign = 64; 1610 AddrSpaceMap = &NVPTXAddrSpaceMap; 1611 UseAddrSpaceMapMangling = true; 1612 // Define available target features 1613 // These must be defined in sorted order! 1614 NoAsmVariants = true; 1615 // Set the default GPU to sm20 1616 GPU = GK_SM20; 1617 } 1618 void getTargetDefines(const LangOptions &Opts, 1619 MacroBuilder &Builder) const override { 1620 Builder.defineMacro("__PTX__"); 1621 Builder.defineMacro("__NVPTX__"); 1622 if (Opts.CUDAIsDevice) { 1623 // Set __CUDA_ARCH__ for the GPU specified. 1624 std::string CUDAArchCode; 1625 switch (GPU) { 1626 case GK_SM20: 1627 CUDAArchCode = "200"; 1628 break; 1629 case GK_SM21: 1630 CUDAArchCode = "210"; 1631 break; 1632 case GK_SM30: 1633 CUDAArchCode = "300"; 1634 break; 1635 case GK_SM35: 1636 CUDAArchCode = "350"; 1637 break; 1638 case GK_SM37: 1639 CUDAArchCode = "370"; 1640 break; 1641 default: 1642 llvm_unreachable("Unhandled target CPU"); 1643 } 1644 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1645 } 1646 } 1647 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1648 return llvm::makeArrayRef(BuiltinInfo, 1649 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1650 } 1651 bool hasFeature(StringRef Feature) const override { 1652 return Feature == "ptx" || Feature == "nvptx"; 1653 } 1654 1655 ArrayRef<const char *> getGCCRegNames() const override; 1656 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1657 // No aliases. 1658 return None; 1659 } 1660 bool validateAsmConstraint(const char *&Name, 1661 TargetInfo::ConstraintInfo &Info) const override { 1662 switch (*Name) { 1663 default: 1664 return false; 1665 case 'c': 1666 case 'h': 1667 case 'r': 1668 case 'l': 1669 case 'f': 1670 case 'd': 1671 Info.setAllowsRegister(); 1672 return true; 1673 } 1674 } 1675 const char *getClobbers() const override { 1676 // FIXME: Is this really right? 1677 return ""; 1678 } 1679 BuiltinVaListKind getBuiltinVaListKind() const override { 1680 // FIXME: implement 1681 return TargetInfo::CharPtrBuiltinVaList; 1682 } 1683 bool setCPU(const std::string &Name) override { 1684 GPU = llvm::StringSwitch<GPUKind>(Name) 1685 .Case("sm_20", GK_SM20) 1686 .Case("sm_21", GK_SM21) 1687 .Case("sm_30", GK_SM30) 1688 .Case("sm_35", GK_SM35) 1689 .Case("sm_37", GK_SM37) 1690 .Default(GK_NONE); 1691 1692 return GPU != GK_NONE; 1693 } 1694 }; 1695 1696 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1697 #define BUILTIN(ID, TYPE, ATTRS) \ 1698 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1699 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1700 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1701 #include "clang/Basic/BuiltinsNVPTX.def" 1702 }; 1703 1704 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1705 1706 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1707 return llvm::makeArrayRef(GCCRegNames); 1708 } 1709 1710 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1711 public: 1712 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1713 LongWidth = LongAlign = 32; 1714 PointerWidth = PointerAlign = 32; 1715 SizeType = TargetInfo::UnsignedInt; 1716 PtrDiffType = TargetInfo::SignedInt; 1717 IntPtrType = TargetInfo::SignedInt; 1718 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1719 } 1720 }; 1721 1722 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1723 public: 1724 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1725 PointerWidth = PointerAlign = 64; 1726 SizeType = TargetInfo::UnsignedLong; 1727 PtrDiffType = TargetInfo::SignedLong; 1728 IntPtrType = TargetInfo::SignedLong; 1729 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1730 } 1731 }; 1732 1733 static const unsigned AMDGPUAddrSpaceMap[] = { 1734 1, // opencl_global 1735 3, // opencl_local 1736 2, // opencl_constant 1737 4, // opencl_generic 1738 1, // cuda_device 1739 2, // cuda_constant 1740 3 // cuda_shared 1741 }; 1742 1743 // If you edit the description strings, make sure you update 1744 // getPointerWidthV(). 1745 1746 static const char *const DataLayoutStringR600 = 1747 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1748 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1749 1750 static const char *const DataLayoutStringSI = 1751 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1752 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1753 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1754 1755 class AMDGPUTargetInfo : public TargetInfo { 1756 static const Builtin::Info BuiltinInfo[]; 1757 static const char * const GCCRegNames[]; 1758 1759 /// \brief The GPU profiles supported by the AMDGPU target. 1760 enum GPUKind { 1761 GK_NONE, 1762 GK_R600, 1763 GK_R600_DOUBLE_OPS, 1764 GK_R700, 1765 GK_R700_DOUBLE_OPS, 1766 GK_EVERGREEN, 1767 GK_EVERGREEN_DOUBLE_OPS, 1768 GK_NORTHERN_ISLANDS, 1769 GK_CAYMAN, 1770 GK_SOUTHERN_ISLANDS, 1771 GK_SEA_ISLANDS, 1772 GK_VOLCANIC_ISLANDS 1773 } GPU; 1774 1775 bool hasFP64:1; 1776 bool hasFMAF:1; 1777 bool hasLDEXPF:1; 1778 1779 public: 1780 AMDGPUTargetInfo(const llvm::Triple &Triple) 1781 : TargetInfo(Triple) { 1782 1783 if (Triple.getArch() == llvm::Triple::amdgcn) { 1784 resetDataLayout(DataLayoutStringSI); 1785 GPU = GK_SOUTHERN_ISLANDS; 1786 hasFP64 = true; 1787 hasFMAF = true; 1788 hasLDEXPF = true; 1789 } else { 1790 resetDataLayout(DataLayoutStringR600); 1791 GPU = GK_R600; 1792 hasFP64 = false; 1793 hasFMAF = false; 1794 hasLDEXPF = false; 1795 } 1796 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1797 UseAddrSpaceMapMangling = true; 1798 } 1799 1800 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1801 if (GPU <= GK_CAYMAN) 1802 return 32; 1803 1804 switch(AddrSpace) { 1805 default: 1806 return 64; 1807 case 0: 1808 case 3: 1809 case 5: 1810 return 32; 1811 } 1812 } 1813 1814 const char * getClobbers() const override { 1815 return ""; 1816 } 1817 1818 ArrayRef<const char *> getGCCRegNames() const override; 1819 1820 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1821 return None; 1822 } 1823 1824 bool validateAsmConstraint(const char *&Name, 1825 TargetInfo::ConstraintInfo &Info) const override { 1826 switch (*Name) { 1827 default: break; 1828 case 'v': // vgpr 1829 case 's': // sgpr 1830 Info.setAllowsRegister(); 1831 return true; 1832 } 1833 return false; 1834 } 1835 1836 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1837 return llvm::makeArrayRef(BuiltinInfo, 1838 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 1839 } 1840 1841 void getTargetDefines(const LangOptions &Opts, 1842 MacroBuilder &Builder) const override { 1843 if (getTriple().getArch() == llvm::Triple::amdgcn) 1844 Builder.defineMacro("__AMDGCN__"); 1845 else 1846 Builder.defineMacro("__R600__"); 1847 1848 if (hasFMAF) 1849 Builder.defineMacro("__HAS_FMAF__"); 1850 if (hasLDEXPF) 1851 Builder.defineMacro("__HAS_LDEXPF__"); 1852 if (hasFP64 && Opts.OpenCL) 1853 Builder.defineMacro("cl_khr_fp64"); 1854 if (Opts.OpenCL) { 1855 if (GPU >= GK_NORTHERN_ISLANDS) { 1856 Builder.defineMacro("cl_khr_byte_addressable_store"); 1857 Builder.defineMacro("cl_khr_global_int32_base_atomics"); 1858 Builder.defineMacro("cl_khr_global_int32_extended_atomics"); 1859 Builder.defineMacro("cl_khr_local_int32_base_atomics"); 1860 Builder.defineMacro("cl_khr_local_int32_extended_atomics"); 1861 } 1862 } 1863 } 1864 1865 BuiltinVaListKind getBuiltinVaListKind() const override { 1866 return TargetInfo::CharPtrBuiltinVaList; 1867 } 1868 1869 bool setCPU(const std::string &Name) override { 1870 GPU = llvm::StringSwitch<GPUKind>(Name) 1871 .Case("r600" , GK_R600) 1872 .Case("rv610", GK_R600) 1873 .Case("rv620", GK_R600) 1874 .Case("rv630", GK_R600) 1875 .Case("rv635", GK_R600) 1876 .Case("rs780", GK_R600) 1877 .Case("rs880", GK_R600) 1878 .Case("rv670", GK_R600_DOUBLE_OPS) 1879 .Case("rv710", GK_R700) 1880 .Case("rv730", GK_R700) 1881 .Case("rv740", GK_R700_DOUBLE_OPS) 1882 .Case("rv770", GK_R700_DOUBLE_OPS) 1883 .Case("palm", GK_EVERGREEN) 1884 .Case("cedar", GK_EVERGREEN) 1885 .Case("sumo", GK_EVERGREEN) 1886 .Case("sumo2", GK_EVERGREEN) 1887 .Case("redwood", GK_EVERGREEN) 1888 .Case("juniper", GK_EVERGREEN) 1889 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1890 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1891 .Case("barts", GK_NORTHERN_ISLANDS) 1892 .Case("turks", GK_NORTHERN_ISLANDS) 1893 .Case("caicos", GK_NORTHERN_ISLANDS) 1894 .Case("cayman", GK_CAYMAN) 1895 .Case("aruba", GK_CAYMAN) 1896 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1897 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1898 .Case("verde", GK_SOUTHERN_ISLANDS) 1899 .Case("oland", GK_SOUTHERN_ISLANDS) 1900 .Case("hainan", GK_SOUTHERN_ISLANDS) 1901 .Case("bonaire", GK_SEA_ISLANDS) 1902 .Case("kabini", GK_SEA_ISLANDS) 1903 .Case("kaveri", GK_SEA_ISLANDS) 1904 .Case("hawaii", GK_SEA_ISLANDS) 1905 .Case("mullins", GK_SEA_ISLANDS) 1906 .Case("tonga", GK_VOLCANIC_ISLANDS) 1907 .Case("iceland", GK_VOLCANIC_ISLANDS) 1908 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1909 .Case("fiji", GK_VOLCANIC_ISLANDS) 1910 .Case("stoney", GK_VOLCANIC_ISLANDS) 1911 .Default(GK_NONE); 1912 1913 if (GPU == GK_NONE) { 1914 return false; 1915 } 1916 1917 // Set the correct data layout 1918 switch (GPU) { 1919 case GK_NONE: 1920 case GK_R600: 1921 case GK_R700: 1922 case GK_EVERGREEN: 1923 case GK_NORTHERN_ISLANDS: 1924 resetDataLayout(DataLayoutStringR600); 1925 hasFP64 = false; 1926 hasFMAF = false; 1927 hasLDEXPF = false; 1928 break; 1929 case GK_R600_DOUBLE_OPS: 1930 case GK_R700_DOUBLE_OPS: 1931 case GK_EVERGREEN_DOUBLE_OPS: 1932 case GK_CAYMAN: 1933 resetDataLayout(DataLayoutStringR600); 1934 hasFP64 = true; 1935 hasFMAF = true; 1936 hasLDEXPF = false; 1937 break; 1938 case GK_SOUTHERN_ISLANDS: 1939 case GK_SEA_ISLANDS: 1940 case GK_VOLCANIC_ISLANDS: 1941 resetDataLayout(DataLayoutStringSI); 1942 hasFP64 = true; 1943 hasFMAF = true; 1944 hasLDEXPF = true; 1945 break; 1946 } 1947 1948 return true; 1949 } 1950 }; 1951 1952 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1953 #define BUILTIN(ID, TYPE, ATTRS) \ 1954 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1955 #include "clang/Basic/BuiltinsAMDGPU.def" 1956 }; 1957 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1958 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1959 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1960 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1961 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1962 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1963 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1964 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1965 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1966 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1967 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1968 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1969 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1970 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1971 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1972 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1973 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1974 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1975 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1976 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1977 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 1978 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 1979 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 1980 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 1981 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 1982 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 1983 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 1984 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 1985 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 1986 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 1987 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 1988 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 1989 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 1990 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 1991 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 1992 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 1993 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 1994 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 1995 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 1996 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 1997 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 1998 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 1999 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2000 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2001 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2002 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2003 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2004 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2005 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2006 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2007 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2008 }; 2009 2010 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2011 return llvm::makeArrayRef(GCCRegNames); 2012 } 2013 2014 // Namespace for x86 abstract base class 2015 const Builtin::Info BuiltinInfo[] = { 2016 #define BUILTIN(ID, TYPE, ATTRS) \ 2017 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2018 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2019 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2020 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2021 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2022 #include "clang/Basic/BuiltinsX86.def" 2023 }; 2024 2025 static const char* const GCCRegNames[] = { 2026 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2027 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2028 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2029 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2030 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2031 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2032 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2033 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2034 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2035 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2036 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2037 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2038 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2039 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2040 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2041 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2042 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2043 }; 2044 2045 const TargetInfo::AddlRegName AddlRegNames[] = { 2046 { { "al", "ah", "eax", "rax" }, 0 }, 2047 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2048 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2049 { { "dl", "dh", "edx", "rdx" }, 1 }, 2050 { { "esi", "rsi" }, 4 }, 2051 { { "edi", "rdi" }, 5 }, 2052 { { "esp", "rsp" }, 7 }, 2053 { { "ebp", "rbp" }, 6 }, 2054 { { "r8d", "r8w", "r8b" }, 38 }, 2055 { { "r9d", "r9w", "r9b" }, 39 }, 2056 { { "r10d", "r10w", "r10b" }, 40 }, 2057 { { "r11d", "r11w", "r11b" }, 41 }, 2058 { { "r12d", "r12w", "r12b" }, 42 }, 2059 { { "r13d", "r13w", "r13b" }, 43 }, 2060 { { "r14d", "r14w", "r14b" }, 44 }, 2061 { { "r15d", "r15w", "r15b" }, 45 }, 2062 }; 2063 2064 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2065 // most of the implementation can be shared. 2066 class X86TargetInfo : public TargetInfo { 2067 enum X86SSEEnum { 2068 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2069 } SSELevel = NoSSE; 2070 enum MMX3DNowEnum { 2071 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2072 } MMX3DNowLevel = NoMMX3DNow; 2073 enum XOPEnum { 2074 NoXOP, 2075 SSE4A, 2076 FMA4, 2077 XOP 2078 } XOPLevel = NoXOP; 2079 2080 bool HasAES = false; 2081 bool HasPCLMUL = false; 2082 bool HasLZCNT = false; 2083 bool HasRDRND = false; 2084 bool HasFSGSBASE = false; 2085 bool HasBMI = false; 2086 bool HasBMI2 = false; 2087 bool HasPOPCNT = false; 2088 bool HasRTM = false; 2089 bool HasPRFCHW = false; 2090 bool HasRDSEED = false; 2091 bool HasADX = false; 2092 bool HasTBM = false; 2093 bool HasFMA = false; 2094 bool HasF16C = false; 2095 bool HasAVX512CD = false; 2096 bool HasAVX512ER = false; 2097 bool HasAVX512PF = false; 2098 bool HasAVX512DQ = false; 2099 bool HasAVX512BW = false; 2100 bool HasAVX512VL = false; 2101 bool HasAVX512VBMI = false; 2102 bool HasAVX512IFMA = false; 2103 bool HasSHA = false; 2104 bool HasMPX = false; 2105 bool HasSGX = false; 2106 bool HasCX16 = false; 2107 bool HasFXSR = false; 2108 bool HasXSAVE = false; 2109 bool HasXSAVEOPT = false; 2110 bool HasXSAVEC = false; 2111 bool HasXSAVES = false; 2112 bool HasPKU = false; 2113 bool HasCLFLUSHOPT = false; 2114 bool HasPCOMMIT = false; 2115 bool HasCLWB = false; 2116 bool HasUMIP = false; 2117 bool HasMOVBE = false; 2118 bool HasPREFETCHWT1 = false; 2119 2120 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2121 /// 2122 /// Each enumeration represents a particular CPU supported by Clang. These 2123 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2124 enum CPUKind { 2125 CK_Generic, 2126 2127 /// \name i386 2128 /// i386-generation processors. 2129 //@{ 2130 CK_i386, 2131 //@} 2132 2133 /// \name i486 2134 /// i486-generation processors. 2135 //@{ 2136 CK_i486, 2137 CK_WinChipC6, 2138 CK_WinChip2, 2139 CK_C3, 2140 //@} 2141 2142 /// \name i586 2143 /// i586-generation processors, P5 microarchitecture based. 2144 //@{ 2145 CK_i586, 2146 CK_Pentium, 2147 CK_PentiumMMX, 2148 //@} 2149 2150 /// \name i686 2151 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2152 //@{ 2153 CK_i686, 2154 CK_PentiumPro, 2155 CK_Pentium2, 2156 CK_Pentium3, 2157 CK_Pentium3M, 2158 CK_PentiumM, 2159 CK_C3_2, 2160 2161 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2162 /// Clang however has some logic to suport this. 2163 // FIXME: Warn, deprecate, and potentially remove this. 2164 CK_Yonah, 2165 //@} 2166 2167 /// \name Netburst 2168 /// Netburst microarchitecture based processors. 2169 //@{ 2170 CK_Pentium4, 2171 CK_Pentium4M, 2172 CK_Prescott, 2173 CK_Nocona, 2174 //@} 2175 2176 /// \name Core 2177 /// Core microarchitecture based processors. 2178 //@{ 2179 CK_Core2, 2180 2181 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2182 /// codename which GCC no longer accepts as an option to -march, but Clang 2183 /// has some logic for recognizing it. 2184 // FIXME: Warn, deprecate, and potentially remove this. 2185 CK_Penryn, 2186 //@} 2187 2188 /// \name Atom 2189 /// Atom processors 2190 //@{ 2191 CK_Bonnell, 2192 CK_Silvermont, 2193 //@} 2194 2195 /// \name Nehalem 2196 /// Nehalem microarchitecture based processors. 2197 CK_Nehalem, 2198 2199 /// \name Westmere 2200 /// Westmere microarchitecture based processors. 2201 CK_Westmere, 2202 2203 /// \name Sandy Bridge 2204 /// Sandy Bridge microarchitecture based processors. 2205 CK_SandyBridge, 2206 2207 /// \name Ivy Bridge 2208 /// Ivy Bridge microarchitecture based processors. 2209 CK_IvyBridge, 2210 2211 /// \name Haswell 2212 /// Haswell microarchitecture based processors. 2213 CK_Haswell, 2214 2215 /// \name Broadwell 2216 /// Broadwell microarchitecture based processors. 2217 CK_Broadwell, 2218 2219 /// \name Skylake Client 2220 /// Skylake client microarchitecture based processors. 2221 CK_SkylakeClient, 2222 2223 /// \name Skylake Server 2224 /// Skylake server microarchitecture based processors. 2225 CK_SkylakeServer, 2226 2227 /// \name Cannonlake Client 2228 /// Cannonlake client microarchitecture based processors. 2229 CK_Cannonlake, 2230 2231 /// \name Knights Landing 2232 /// Knights Landing processor. 2233 CK_KNL, 2234 2235 /// \name K6 2236 /// K6 architecture processors. 2237 //@{ 2238 CK_K6, 2239 CK_K6_2, 2240 CK_K6_3, 2241 //@} 2242 2243 /// \name K7 2244 /// K7 architecture processors. 2245 //@{ 2246 CK_Athlon, 2247 CK_AthlonThunderbird, 2248 CK_Athlon4, 2249 CK_AthlonXP, 2250 CK_AthlonMP, 2251 //@} 2252 2253 /// \name K8 2254 /// K8 architecture processors. 2255 //@{ 2256 CK_Athlon64, 2257 CK_Athlon64SSE3, 2258 CK_AthlonFX, 2259 CK_K8, 2260 CK_K8SSE3, 2261 CK_Opteron, 2262 CK_OpteronSSE3, 2263 CK_AMDFAM10, 2264 //@} 2265 2266 /// \name Bobcat 2267 /// Bobcat architecture processors. 2268 //@{ 2269 CK_BTVER1, 2270 CK_BTVER2, 2271 //@} 2272 2273 /// \name Bulldozer 2274 /// Bulldozer architecture processors. 2275 //@{ 2276 CK_BDVER1, 2277 CK_BDVER2, 2278 CK_BDVER3, 2279 CK_BDVER4, 2280 //@} 2281 2282 /// This specification is deprecated and will be removed in the future. 2283 /// Users should prefer \see CK_K8. 2284 // FIXME: Warn on this when the CPU is set to it. 2285 //@{ 2286 CK_x86_64, 2287 //@} 2288 2289 /// \name Geode 2290 /// Geode processors. 2291 //@{ 2292 CK_Geode 2293 //@} 2294 } CPU = CK_Generic; 2295 2296 CPUKind getCPUKind(StringRef CPU) const { 2297 return llvm::StringSwitch<CPUKind>(CPU) 2298 .Case("i386", CK_i386) 2299 .Case("i486", CK_i486) 2300 .Case("winchip-c6", CK_WinChipC6) 2301 .Case("winchip2", CK_WinChip2) 2302 .Case("c3", CK_C3) 2303 .Case("i586", CK_i586) 2304 .Case("pentium", CK_Pentium) 2305 .Case("pentium-mmx", CK_PentiumMMX) 2306 .Case("i686", CK_i686) 2307 .Case("pentiumpro", CK_PentiumPro) 2308 .Case("pentium2", CK_Pentium2) 2309 .Case("pentium3", CK_Pentium3) 2310 .Case("pentium3m", CK_Pentium3M) 2311 .Case("pentium-m", CK_PentiumM) 2312 .Case("c3-2", CK_C3_2) 2313 .Case("yonah", CK_Yonah) 2314 .Case("pentium4", CK_Pentium4) 2315 .Case("pentium4m", CK_Pentium4M) 2316 .Case("prescott", CK_Prescott) 2317 .Case("nocona", CK_Nocona) 2318 .Case("core2", CK_Core2) 2319 .Case("penryn", CK_Penryn) 2320 .Case("bonnell", CK_Bonnell) 2321 .Case("atom", CK_Bonnell) // Legacy name. 2322 .Case("silvermont", CK_Silvermont) 2323 .Case("slm", CK_Silvermont) // Legacy name. 2324 .Case("nehalem", CK_Nehalem) 2325 .Case("corei7", CK_Nehalem) // Legacy name. 2326 .Case("westmere", CK_Westmere) 2327 .Case("sandybridge", CK_SandyBridge) 2328 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2329 .Case("ivybridge", CK_IvyBridge) 2330 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2331 .Case("haswell", CK_Haswell) 2332 .Case("core-avx2", CK_Haswell) // Legacy name. 2333 .Case("broadwell", CK_Broadwell) 2334 .Case("skylake", CK_SkylakeClient) 2335 .Case("skylake-avx512", CK_SkylakeServer) 2336 .Case("skx", CK_SkylakeServer) // Legacy name. 2337 .Case("cannonlake", CK_Cannonlake) 2338 .Case("knl", CK_KNL) 2339 .Case("k6", CK_K6) 2340 .Case("k6-2", CK_K6_2) 2341 .Case("k6-3", CK_K6_3) 2342 .Case("athlon", CK_Athlon) 2343 .Case("athlon-tbird", CK_AthlonThunderbird) 2344 .Case("athlon-4", CK_Athlon4) 2345 .Case("athlon-xp", CK_AthlonXP) 2346 .Case("athlon-mp", CK_AthlonMP) 2347 .Case("athlon64", CK_Athlon64) 2348 .Case("athlon64-sse3", CK_Athlon64SSE3) 2349 .Case("athlon-fx", CK_AthlonFX) 2350 .Case("k8", CK_K8) 2351 .Case("k8-sse3", CK_K8SSE3) 2352 .Case("opteron", CK_Opteron) 2353 .Case("opteron-sse3", CK_OpteronSSE3) 2354 .Case("barcelona", CK_AMDFAM10) 2355 .Case("amdfam10", CK_AMDFAM10) 2356 .Case("btver1", CK_BTVER1) 2357 .Case("btver2", CK_BTVER2) 2358 .Case("bdver1", CK_BDVER1) 2359 .Case("bdver2", CK_BDVER2) 2360 .Case("bdver3", CK_BDVER3) 2361 .Case("bdver4", CK_BDVER4) 2362 .Case("x86-64", CK_x86_64) 2363 .Case("geode", CK_Geode) 2364 .Default(CK_Generic); 2365 } 2366 2367 enum FPMathKind { 2368 FP_Default, 2369 FP_SSE, 2370 FP_387 2371 } FPMath = FP_Default; 2372 2373 public: 2374 X86TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 2375 BigEndian = false; 2376 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2377 } 2378 unsigned getFloatEvalMethod() const override { 2379 // X87 evaluates with 80 bits "long double" precision. 2380 return SSELevel == NoSSE ? 2 : 0; 2381 } 2382 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2383 return llvm::makeArrayRef(BuiltinInfo, 2384 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2385 } 2386 ArrayRef<const char *> getGCCRegNames() const override { 2387 return llvm::makeArrayRef(GCCRegNames); 2388 } 2389 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2390 return None; 2391 } 2392 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2393 return llvm::makeArrayRef(AddlRegNames); 2394 } 2395 bool validateCpuSupports(StringRef Name) const override; 2396 bool validateAsmConstraint(const char *&Name, 2397 TargetInfo::ConstraintInfo &info) const override; 2398 2399 bool validateGlobalRegisterVariable(StringRef RegName, 2400 unsigned RegSize, 2401 bool &HasSizeMismatch) const override { 2402 // esp and ebp are the only 32-bit registers the x86 backend can currently 2403 // handle. 2404 if (RegName.equals("esp") || RegName.equals("ebp")) { 2405 // Check that the register size is 32-bit. 2406 HasSizeMismatch = RegSize != 32; 2407 return true; 2408 } 2409 2410 return false; 2411 } 2412 2413 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2414 2415 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2416 2417 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2418 2419 std::string convertConstraint(const char *&Constraint) const override; 2420 const char *getClobbers() const override { 2421 return "~{dirflag},~{fpsr},~{flags}"; 2422 } 2423 void getTargetDefines(const LangOptions &Opts, 2424 MacroBuilder &Builder) const override; 2425 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2426 bool Enabled); 2427 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2428 bool Enabled); 2429 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2430 bool Enabled); 2431 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2432 StringRef Name, bool Enabled) const override { 2433 setFeatureEnabledImpl(Features, Name, Enabled); 2434 } 2435 // This exists purely to cut down on the number of virtual calls in 2436 // initFeatureMap which calls this repeatedly. 2437 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2438 StringRef Name, bool Enabled); 2439 bool 2440 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2441 StringRef CPU, 2442 const std::vector<std::string> &FeaturesVec) const override; 2443 bool hasFeature(StringRef Feature) const override; 2444 bool handleTargetFeatures(std::vector<std::string> &Features, 2445 DiagnosticsEngine &Diags) override; 2446 StringRef getABI() const override { 2447 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2448 return "avx512"; 2449 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2450 return "avx"; 2451 if (getTriple().getArch() == llvm::Triple::x86 && 2452 MMX3DNowLevel == NoMMX3DNow) 2453 return "no-mmx"; 2454 return ""; 2455 } 2456 bool setCPU(const std::string &Name) override { 2457 CPU = getCPUKind(Name); 2458 2459 // Perform any per-CPU checks necessary to determine if this CPU is 2460 // acceptable. 2461 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2462 // invalid without explaining *why*. 2463 switch (CPU) { 2464 case CK_Generic: 2465 // No processor selected! 2466 return false; 2467 2468 case CK_i386: 2469 case CK_i486: 2470 case CK_WinChipC6: 2471 case CK_WinChip2: 2472 case CK_C3: 2473 case CK_i586: 2474 case CK_Pentium: 2475 case CK_PentiumMMX: 2476 case CK_i686: 2477 case CK_PentiumPro: 2478 case CK_Pentium2: 2479 case CK_Pentium3: 2480 case CK_Pentium3M: 2481 case CK_PentiumM: 2482 case CK_Yonah: 2483 case CK_C3_2: 2484 case CK_Pentium4: 2485 case CK_Pentium4M: 2486 case CK_Prescott: 2487 case CK_K6: 2488 case CK_K6_2: 2489 case CK_K6_3: 2490 case CK_Athlon: 2491 case CK_AthlonThunderbird: 2492 case CK_Athlon4: 2493 case CK_AthlonXP: 2494 case CK_AthlonMP: 2495 case CK_Geode: 2496 // Only accept certain architectures when compiling in 32-bit mode. 2497 if (getTriple().getArch() != llvm::Triple::x86) 2498 return false; 2499 2500 // Fallthrough 2501 case CK_Nocona: 2502 case CK_Core2: 2503 case CK_Penryn: 2504 case CK_Bonnell: 2505 case CK_Silvermont: 2506 case CK_Nehalem: 2507 case CK_Westmere: 2508 case CK_SandyBridge: 2509 case CK_IvyBridge: 2510 case CK_Haswell: 2511 case CK_Broadwell: 2512 case CK_SkylakeClient: 2513 case CK_SkylakeServer: 2514 case CK_Cannonlake: 2515 case CK_KNL: 2516 case CK_Athlon64: 2517 case CK_Athlon64SSE3: 2518 case CK_AthlonFX: 2519 case CK_K8: 2520 case CK_K8SSE3: 2521 case CK_Opteron: 2522 case CK_OpteronSSE3: 2523 case CK_AMDFAM10: 2524 case CK_BTVER1: 2525 case CK_BTVER2: 2526 case CK_BDVER1: 2527 case CK_BDVER2: 2528 case CK_BDVER3: 2529 case CK_BDVER4: 2530 case CK_x86_64: 2531 return true; 2532 } 2533 llvm_unreachable("Unhandled CPU kind"); 2534 } 2535 2536 bool setFPMath(StringRef Name) override; 2537 2538 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2539 // Most of the non-ARM calling conventions are i386 conventions. 2540 switch (CC) { 2541 case CC_X86ThisCall: 2542 case CC_X86FastCall: 2543 case CC_X86StdCall: 2544 case CC_X86VectorCall: 2545 case CC_C: 2546 case CC_Swift: 2547 case CC_X86Pascal: 2548 case CC_IntelOclBicc: 2549 return CCCR_OK; 2550 default: 2551 return CCCR_Warning; 2552 } 2553 } 2554 2555 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2556 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2557 } 2558 2559 bool hasSjLjLowering() const override { 2560 return true; 2561 } 2562 }; 2563 2564 bool X86TargetInfo::setFPMath(StringRef Name) { 2565 if (Name == "387") { 2566 FPMath = FP_387; 2567 return true; 2568 } 2569 if (Name == "sse") { 2570 FPMath = FP_SSE; 2571 return true; 2572 } 2573 return false; 2574 } 2575 2576 bool X86TargetInfo::initFeatureMap( 2577 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2578 const std::vector<std::string> &FeaturesVec) const { 2579 // FIXME: This *really* should not be here. 2580 // X86_64 always has SSE2. 2581 if (getTriple().getArch() == llvm::Triple::x86_64) 2582 setFeatureEnabledImpl(Features, "sse2", true); 2583 2584 // Enable X87 for all X86 processors. 2585 setFeatureEnabledImpl(Features, "x87", true); 2586 2587 switch (getCPUKind(CPU)) { 2588 case CK_Generic: 2589 case CK_i386: 2590 case CK_i486: 2591 case CK_i586: 2592 case CK_Pentium: 2593 case CK_i686: 2594 case CK_PentiumPro: 2595 break; 2596 case CK_PentiumMMX: 2597 case CK_Pentium2: 2598 case CK_K6: 2599 case CK_WinChipC6: 2600 setFeatureEnabledImpl(Features, "mmx", true); 2601 break; 2602 case CK_Pentium3: 2603 case CK_Pentium3M: 2604 case CK_C3_2: 2605 setFeatureEnabledImpl(Features, "sse", true); 2606 setFeatureEnabledImpl(Features, "fxsr", true); 2607 break; 2608 case CK_PentiumM: 2609 case CK_Pentium4: 2610 case CK_Pentium4M: 2611 case CK_x86_64: 2612 setFeatureEnabledImpl(Features, "sse2", true); 2613 setFeatureEnabledImpl(Features, "fxsr", true); 2614 break; 2615 case CK_Yonah: 2616 case CK_Prescott: 2617 case CK_Nocona: 2618 setFeatureEnabledImpl(Features, "sse3", true); 2619 setFeatureEnabledImpl(Features, "fxsr", true); 2620 setFeatureEnabledImpl(Features, "cx16", true); 2621 break; 2622 case CK_Core2: 2623 case CK_Bonnell: 2624 setFeatureEnabledImpl(Features, "ssse3", true); 2625 setFeatureEnabledImpl(Features, "fxsr", true); 2626 setFeatureEnabledImpl(Features, "cx16", true); 2627 break; 2628 case CK_Penryn: 2629 setFeatureEnabledImpl(Features, "sse4.1", true); 2630 setFeatureEnabledImpl(Features, "fxsr", true); 2631 setFeatureEnabledImpl(Features, "cx16", true); 2632 break; 2633 case CK_Cannonlake: 2634 setFeatureEnabledImpl(Features, "avx512ifma", true); 2635 setFeatureEnabledImpl(Features, "avx512vbmi", true); 2636 setFeatureEnabledImpl(Features, "sha", true); 2637 setFeatureEnabledImpl(Features, "umip", true); 2638 // FALLTHROUGH 2639 case CK_SkylakeServer: 2640 setFeatureEnabledImpl(Features, "avx512f", true); 2641 setFeatureEnabledImpl(Features, "avx512cd", true); 2642 setFeatureEnabledImpl(Features, "avx512dq", true); 2643 setFeatureEnabledImpl(Features, "avx512bw", true); 2644 setFeatureEnabledImpl(Features, "avx512vl", true); 2645 setFeatureEnabledImpl(Features, "pku", true); 2646 setFeatureEnabledImpl(Features, "pcommit", true); 2647 setFeatureEnabledImpl(Features, "clwb", true); 2648 // FALLTHROUGH 2649 case CK_SkylakeClient: 2650 setFeatureEnabledImpl(Features, "xsavec", true); 2651 setFeatureEnabledImpl(Features, "xsaves", true); 2652 setFeatureEnabledImpl(Features, "mpx", true); 2653 setFeatureEnabledImpl(Features, "sgx", true); 2654 setFeatureEnabledImpl(Features, "clflushopt", true); 2655 // FALLTHROUGH 2656 case CK_Broadwell: 2657 setFeatureEnabledImpl(Features, "rdseed", true); 2658 setFeatureEnabledImpl(Features, "adx", true); 2659 // FALLTHROUGH 2660 case CK_Haswell: 2661 setFeatureEnabledImpl(Features, "avx2", true); 2662 setFeatureEnabledImpl(Features, "lzcnt", true); 2663 setFeatureEnabledImpl(Features, "bmi", true); 2664 setFeatureEnabledImpl(Features, "bmi2", true); 2665 setFeatureEnabledImpl(Features, "rtm", true); 2666 setFeatureEnabledImpl(Features, "fma", true); 2667 setFeatureEnabledImpl(Features, "movbe", true); 2668 // FALLTHROUGH 2669 case CK_IvyBridge: 2670 setFeatureEnabledImpl(Features, "rdrnd", true); 2671 setFeatureEnabledImpl(Features, "f16c", true); 2672 setFeatureEnabledImpl(Features, "fsgsbase", true); 2673 // FALLTHROUGH 2674 case CK_SandyBridge: 2675 setFeatureEnabledImpl(Features, "avx", true); 2676 setFeatureEnabledImpl(Features, "xsave", true); 2677 setFeatureEnabledImpl(Features, "xsaveopt", true); 2678 // FALLTHROUGH 2679 case CK_Westmere: 2680 case CK_Silvermont: 2681 setFeatureEnabledImpl(Features, "aes", true); 2682 setFeatureEnabledImpl(Features, "pclmul", true); 2683 // FALLTHROUGH 2684 case CK_Nehalem: 2685 setFeatureEnabledImpl(Features, "sse4.2", true); 2686 setFeatureEnabledImpl(Features, "fxsr", true); 2687 setFeatureEnabledImpl(Features, "cx16", true); 2688 break; 2689 case CK_KNL: 2690 setFeatureEnabledImpl(Features, "avx512f", true); 2691 setFeatureEnabledImpl(Features, "avx512cd", true); 2692 setFeatureEnabledImpl(Features, "avx512er", true); 2693 setFeatureEnabledImpl(Features, "avx512pf", true); 2694 setFeatureEnabledImpl(Features, "prefetchwt1", true); 2695 setFeatureEnabledImpl(Features, "fxsr", true); 2696 setFeatureEnabledImpl(Features, "rdseed", true); 2697 setFeatureEnabledImpl(Features, "adx", true); 2698 setFeatureEnabledImpl(Features, "lzcnt", true); 2699 setFeatureEnabledImpl(Features, "bmi", true); 2700 setFeatureEnabledImpl(Features, "bmi2", true); 2701 setFeatureEnabledImpl(Features, "rtm", true); 2702 setFeatureEnabledImpl(Features, "fma", true); 2703 setFeatureEnabledImpl(Features, "rdrnd", true); 2704 setFeatureEnabledImpl(Features, "f16c", true); 2705 setFeatureEnabledImpl(Features, "fsgsbase", true); 2706 setFeatureEnabledImpl(Features, "aes", true); 2707 setFeatureEnabledImpl(Features, "pclmul", true); 2708 setFeatureEnabledImpl(Features, "cx16", true); 2709 setFeatureEnabledImpl(Features, "xsaveopt", true); 2710 setFeatureEnabledImpl(Features, "xsave", true); 2711 setFeatureEnabledImpl(Features, "movbe", true); 2712 break; 2713 case CK_K6_2: 2714 case CK_K6_3: 2715 case CK_WinChip2: 2716 case CK_C3: 2717 setFeatureEnabledImpl(Features, "3dnow", true); 2718 break; 2719 case CK_Athlon: 2720 case CK_AthlonThunderbird: 2721 case CK_Geode: 2722 setFeatureEnabledImpl(Features, "3dnowa", true); 2723 break; 2724 case CK_Athlon4: 2725 case CK_AthlonXP: 2726 case CK_AthlonMP: 2727 setFeatureEnabledImpl(Features, "sse", true); 2728 setFeatureEnabledImpl(Features, "3dnowa", true); 2729 setFeatureEnabledImpl(Features, "fxsr", true); 2730 break; 2731 case CK_K8: 2732 case CK_Opteron: 2733 case CK_Athlon64: 2734 case CK_AthlonFX: 2735 setFeatureEnabledImpl(Features, "sse2", true); 2736 setFeatureEnabledImpl(Features, "3dnowa", true); 2737 setFeatureEnabledImpl(Features, "fxsr", true); 2738 break; 2739 case CK_AMDFAM10: 2740 setFeatureEnabledImpl(Features, "sse4a", true); 2741 setFeatureEnabledImpl(Features, "lzcnt", true); 2742 setFeatureEnabledImpl(Features, "popcnt", true); 2743 // FALLTHROUGH 2744 case CK_K8SSE3: 2745 case CK_OpteronSSE3: 2746 case CK_Athlon64SSE3: 2747 setFeatureEnabledImpl(Features, "sse3", true); 2748 setFeatureEnabledImpl(Features, "3dnowa", true); 2749 setFeatureEnabledImpl(Features, "fxsr", true); 2750 break; 2751 case CK_BTVER2: 2752 setFeatureEnabledImpl(Features, "avx", true); 2753 setFeatureEnabledImpl(Features, "aes", true); 2754 setFeatureEnabledImpl(Features, "pclmul", true); 2755 setFeatureEnabledImpl(Features, "bmi", true); 2756 setFeatureEnabledImpl(Features, "f16c", true); 2757 setFeatureEnabledImpl(Features, "xsaveopt", true); 2758 // FALLTHROUGH 2759 case CK_BTVER1: 2760 setFeatureEnabledImpl(Features, "ssse3", true); 2761 setFeatureEnabledImpl(Features, "sse4a", true); 2762 setFeatureEnabledImpl(Features, "lzcnt", true); 2763 setFeatureEnabledImpl(Features, "popcnt", true); 2764 setFeatureEnabledImpl(Features, "prfchw", true); 2765 setFeatureEnabledImpl(Features, "cx16", true); 2766 setFeatureEnabledImpl(Features, "fxsr", true); 2767 break; 2768 case CK_BDVER4: 2769 setFeatureEnabledImpl(Features, "avx2", true); 2770 setFeatureEnabledImpl(Features, "bmi2", true); 2771 // FALLTHROUGH 2772 case CK_BDVER3: 2773 setFeatureEnabledImpl(Features, "fsgsbase", true); 2774 setFeatureEnabledImpl(Features, "xsaveopt", true); 2775 // FALLTHROUGH 2776 case CK_BDVER2: 2777 setFeatureEnabledImpl(Features, "bmi", true); 2778 setFeatureEnabledImpl(Features, "fma", true); 2779 setFeatureEnabledImpl(Features, "f16c", true); 2780 setFeatureEnabledImpl(Features, "tbm", true); 2781 // FALLTHROUGH 2782 case CK_BDVER1: 2783 // xop implies avx, sse4a and fma4. 2784 setFeatureEnabledImpl(Features, "xop", true); 2785 setFeatureEnabledImpl(Features, "lzcnt", true); 2786 setFeatureEnabledImpl(Features, "aes", true); 2787 setFeatureEnabledImpl(Features, "pclmul", true); 2788 setFeatureEnabledImpl(Features, "prfchw", true); 2789 setFeatureEnabledImpl(Features, "cx16", true); 2790 setFeatureEnabledImpl(Features, "fxsr", true); 2791 setFeatureEnabledImpl(Features, "xsave", true); 2792 break; 2793 } 2794 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 2795 return false; 2796 2797 // Can't do this earlier because we need to be able to explicitly enable 2798 // or disable these features and the things that they depend upon. 2799 2800 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2801 auto I = Features.find("sse4.2"); 2802 if (I != Features.end() && I->getValue() && 2803 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 2804 FeaturesVec.end()) 2805 Features["popcnt"] = true; 2806 2807 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2808 I = Features.find("3dnow"); 2809 if (I != Features.end() && I->getValue() && 2810 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 2811 FeaturesVec.end()) 2812 Features["prfchw"] = true; 2813 2814 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2815 // then enable MMX. 2816 I = Features.find("sse"); 2817 if (I != Features.end() && I->getValue() && 2818 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 2819 FeaturesVec.end()) 2820 Features["mmx"] = true; 2821 2822 return true; 2823 } 2824 2825 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2826 X86SSEEnum Level, bool Enabled) { 2827 if (Enabled) { 2828 switch (Level) { 2829 case AVX512F: 2830 Features["avx512f"] = true; 2831 case AVX2: 2832 Features["avx2"] = true; 2833 case AVX: 2834 Features["avx"] = true; 2835 Features["xsave"] = true; 2836 case SSE42: 2837 Features["sse4.2"] = true; 2838 case SSE41: 2839 Features["sse4.1"] = true; 2840 case SSSE3: 2841 Features["ssse3"] = true; 2842 case SSE3: 2843 Features["sse3"] = true; 2844 case SSE2: 2845 Features["sse2"] = true; 2846 case SSE1: 2847 Features["sse"] = true; 2848 case NoSSE: 2849 break; 2850 } 2851 return; 2852 } 2853 2854 switch (Level) { 2855 case NoSSE: 2856 case SSE1: 2857 Features["sse"] = false; 2858 case SSE2: 2859 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2860 Features["sha"] = false; 2861 case SSE3: 2862 Features["sse3"] = false; 2863 setXOPLevel(Features, NoXOP, false); 2864 case SSSE3: 2865 Features["ssse3"] = false; 2866 case SSE41: 2867 Features["sse4.1"] = false; 2868 case SSE42: 2869 Features["sse4.2"] = false; 2870 case AVX: 2871 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 2872 Features["xsaveopt"] = false; 2873 setXOPLevel(Features, FMA4, false); 2874 case AVX2: 2875 Features["avx2"] = false; 2876 case AVX512F: 2877 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2878 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2879 Features["avx512vl"] = Features["avx512vbmi"] = 2880 Features["avx512ifma"] = false; 2881 } 2882 } 2883 2884 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2885 MMX3DNowEnum Level, bool Enabled) { 2886 if (Enabled) { 2887 switch (Level) { 2888 case AMD3DNowAthlon: 2889 Features["3dnowa"] = true; 2890 case AMD3DNow: 2891 Features["3dnow"] = true; 2892 case MMX: 2893 Features["mmx"] = true; 2894 case NoMMX3DNow: 2895 break; 2896 } 2897 return; 2898 } 2899 2900 switch (Level) { 2901 case NoMMX3DNow: 2902 case MMX: 2903 Features["mmx"] = false; 2904 case AMD3DNow: 2905 Features["3dnow"] = false; 2906 case AMD3DNowAthlon: 2907 Features["3dnowa"] = false; 2908 } 2909 } 2910 2911 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2912 bool Enabled) { 2913 if (Enabled) { 2914 switch (Level) { 2915 case XOP: 2916 Features["xop"] = true; 2917 case FMA4: 2918 Features["fma4"] = true; 2919 setSSELevel(Features, AVX, true); 2920 case SSE4A: 2921 Features["sse4a"] = true; 2922 setSSELevel(Features, SSE3, true); 2923 case NoXOP: 2924 break; 2925 } 2926 return; 2927 } 2928 2929 switch (Level) { 2930 case NoXOP: 2931 case SSE4A: 2932 Features["sse4a"] = false; 2933 case FMA4: 2934 Features["fma4"] = false; 2935 case XOP: 2936 Features["xop"] = false; 2937 } 2938 } 2939 2940 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2941 StringRef Name, bool Enabled) { 2942 // This is a bit of a hack to deal with the sse4 target feature when used 2943 // as part of the target attribute. We handle sse4 correctly everywhere 2944 // else. See below for more information on how we handle the sse4 options. 2945 if (Name != "sse4") 2946 Features[Name] = Enabled; 2947 2948 if (Name == "mmx") { 2949 setMMXLevel(Features, MMX, Enabled); 2950 } else if (Name == "sse") { 2951 setSSELevel(Features, SSE1, Enabled); 2952 } else if (Name == "sse2") { 2953 setSSELevel(Features, SSE2, Enabled); 2954 } else if (Name == "sse3") { 2955 setSSELevel(Features, SSE3, Enabled); 2956 } else if (Name == "ssse3") { 2957 setSSELevel(Features, SSSE3, Enabled); 2958 } else if (Name == "sse4.2") { 2959 setSSELevel(Features, SSE42, Enabled); 2960 } else if (Name == "sse4.1") { 2961 setSSELevel(Features, SSE41, Enabled); 2962 } else if (Name == "3dnow") { 2963 setMMXLevel(Features, AMD3DNow, Enabled); 2964 } else if (Name == "3dnowa") { 2965 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2966 } else if (Name == "aes") { 2967 if (Enabled) 2968 setSSELevel(Features, SSE2, Enabled); 2969 } else if (Name == "pclmul") { 2970 if (Enabled) 2971 setSSELevel(Features, SSE2, Enabled); 2972 } else if (Name == "avx") { 2973 setSSELevel(Features, AVX, Enabled); 2974 } else if (Name == "avx2") { 2975 setSSELevel(Features, AVX2, Enabled); 2976 } else if (Name == "avx512f") { 2977 setSSELevel(Features, AVX512F, Enabled); 2978 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 2979 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 2980 Name == "avx512vbmi" || Name == "avx512ifma") { 2981 if (Enabled) 2982 setSSELevel(Features, AVX512F, Enabled); 2983 } else if (Name == "fma") { 2984 if (Enabled) 2985 setSSELevel(Features, AVX, Enabled); 2986 } else if (Name == "fma4") { 2987 setXOPLevel(Features, FMA4, Enabled); 2988 } else if (Name == "xop") { 2989 setXOPLevel(Features, XOP, Enabled); 2990 } else if (Name == "sse4a") { 2991 setXOPLevel(Features, SSE4A, Enabled); 2992 } else if (Name == "f16c") { 2993 if (Enabled) 2994 setSSELevel(Features, AVX, Enabled); 2995 } else if (Name == "sha") { 2996 if (Enabled) 2997 setSSELevel(Features, SSE2, Enabled); 2998 } else if (Name == "sse4") { 2999 // We can get here via the __target__ attribute since that's not controlled 3000 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3001 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3002 // disabled. 3003 if (Enabled) 3004 setSSELevel(Features, SSE42, Enabled); 3005 else 3006 setSSELevel(Features, SSE41, Enabled); 3007 } else if (Name == "xsave") { 3008 if (!Enabled) 3009 Features["xsaveopt"] = false; 3010 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3011 if (Enabled) 3012 Features["xsave"] = true; 3013 } 3014 } 3015 3016 /// handleTargetFeatures - Perform initialization based on the user 3017 /// configured set of features. 3018 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3019 DiagnosticsEngine &Diags) { 3020 for (const auto &Feature : Features) { 3021 if (Feature[0] != '+') 3022 continue; 3023 3024 if (Feature == "+aes") { 3025 HasAES = true; 3026 } else if (Feature == "+pclmul") { 3027 HasPCLMUL = true; 3028 } else if (Feature == "+lzcnt") { 3029 HasLZCNT = true; 3030 } else if (Feature == "+rdrnd") { 3031 HasRDRND = true; 3032 } else if (Feature == "+fsgsbase") { 3033 HasFSGSBASE = true; 3034 } else if (Feature == "+bmi") { 3035 HasBMI = true; 3036 } else if (Feature == "+bmi2") { 3037 HasBMI2 = true; 3038 } else if (Feature == "+popcnt") { 3039 HasPOPCNT = true; 3040 } else if (Feature == "+rtm") { 3041 HasRTM = true; 3042 } else if (Feature == "+prfchw") { 3043 HasPRFCHW = true; 3044 } else if (Feature == "+rdseed") { 3045 HasRDSEED = true; 3046 } else if (Feature == "+adx") { 3047 HasADX = true; 3048 } else if (Feature == "+tbm") { 3049 HasTBM = true; 3050 } else if (Feature == "+fma") { 3051 HasFMA = true; 3052 } else if (Feature == "+f16c") { 3053 HasF16C = true; 3054 } else if (Feature == "+avx512cd") { 3055 HasAVX512CD = true; 3056 } else if (Feature == "+avx512er") { 3057 HasAVX512ER = true; 3058 } else if (Feature == "+avx512pf") { 3059 HasAVX512PF = true; 3060 } else if (Feature == "+avx512dq") { 3061 HasAVX512DQ = true; 3062 } else if (Feature == "+avx512bw") { 3063 HasAVX512BW = true; 3064 } else if (Feature == "+avx512vl") { 3065 HasAVX512VL = true; 3066 } else if (Feature == "+avx512vbmi") { 3067 HasAVX512VBMI = true; 3068 } else if (Feature == "+avx512ifma") { 3069 HasAVX512IFMA = true; 3070 } else if (Feature == "+sha") { 3071 HasSHA = true; 3072 } else if (Feature == "+mpx") { 3073 HasMPX = true; 3074 } else if (Feature == "+movbe") { 3075 HasMOVBE = true; 3076 } else if (Feature == "+sgx") { 3077 HasSGX = true; 3078 } else if (Feature == "+cx16") { 3079 HasCX16 = true; 3080 } else if (Feature == "+fxsr") { 3081 HasFXSR = true; 3082 } else if (Feature == "+xsave") { 3083 HasXSAVE = true; 3084 } else if (Feature == "+xsaveopt") { 3085 HasXSAVEOPT = true; 3086 } else if (Feature == "+xsavec") { 3087 HasXSAVEC = true; 3088 } else if (Feature == "+xsaves") { 3089 HasXSAVES = true; 3090 } else if (Feature == "+pku") { 3091 HasPKU = true; 3092 } else if (Feature == "+clflushopt") { 3093 HasCLFLUSHOPT = true; 3094 } else if (Feature == "+pcommit") { 3095 HasPCOMMIT = true; 3096 } else if (Feature == "+clwb") { 3097 HasCLWB = true; 3098 } else if (Feature == "+umip") { 3099 HasUMIP = true; 3100 } else if (Feature == "+prefetchwt1") { 3101 HasPREFETCHWT1 = true; 3102 } 3103 3104 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3105 .Case("+avx512f", AVX512F) 3106 .Case("+avx2", AVX2) 3107 .Case("+avx", AVX) 3108 .Case("+sse4.2", SSE42) 3109 .Case("+sse4.1", SSE41) 3110 .Case("+ssse3", SSSE3) 3111 .Case("+sse3", SSE3) 3112 .Case("+sse2", SSE2) 3113 .Case("+sse", SSE1) 3114 .Default(NoSSE); 3115 SSELevel = std::max(SSELevel, Level); 3116 3117 MMX3DNowEnum ThreeDNowLevel = 3118 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3119 .Case("+3dnowa", AMD3DNowAthlon) 3120 .Case("+3dnow", AMD3DNow) 3121 .Case("+mmx", MMX) 3122 .Default(NoMMX3DNow); 3123 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3124 3125 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3126 .Case("+xop", XOP) 3127 .Case("+fma4", FMA4) 3128 .Case("+sse4a", SSE4A) 3129 .Default(NoXOP); 3130 XOPLevel = std::max(XOPLevel, XLevel); 3131 } 3132 3133 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3134 // matches the selected sse level. 3135 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3136 (FPMath == FP_387 && SSELevel >= SSE1)) { 3137 Diags.Report(diag::err_target_unsupported_fpmath) << 3138 (FPMath == FP_SSE ? "sse" : "387"); 3139 return false; 3140 } 3141 3142 SimdDefaultAlign = 3143 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3144 return true; 3145 } 3146 3147 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3148 /// definitions for this particular subtarget. 3149 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3150 MacroBuilder &Builder) const { 3151 // Target identification. 3152 if (getTriple().getArch() == llvm::Triple::x86_64) { 3153 Builder.defineMacro("__amd64__"); 3154 Builder.defineMacro("__amd64"); 3155 Builder.defineMacro("__x86_64"); 3156 Builder.defineMacro("__x86_64__"); 3157 if (getTriple().getArchName() == "x86_64h") { 3158 Builder.defineMacro("__x86_64h"); 3159 Builder.defineMacro("__x86_64h__"); 3160 } 3161 } else { 3162 DefineStd(Builder, "i386", Opts); 3163 } 3164 3165 // Subtarget options. 3166 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3167 // truly should be based on -mtune options. 3168 switch (CPU) { 3169 case CK_Generic: 3170 break; 3171 case CK_i386: 3172 // The rest are coming from the i386 define above. 3173 Builder.defineMacro("__tune_i386__"); 3174 break; 3175 case CK_i486: 3176 case CK_WinChipC6: 3177 case CK_WinChip2: 3178 case CK_C3: 3179 defineCPUMacros(Builder, "i486"); 3180 break; 3181 case CK_PentiumMMX: 3182 Builder.defineMacro("__pentium_mmx__"); 3183 Builder.defineMacro("__tune_pentium_mmx__"); 3184 // Fallthrough 3185 case CK_i586: 3186 case CK_Pentium: 3187 defineCPUMacros(Builder, "i586"); 3188 defineCPUMacros(Builder, "pentium"); 3189 break; 3190 case CK_Pentium3: 3191 case CK_Pentium3M: 3192 case CK_PentiumM: 3193 Builder.defineMacro("__tune_pentium3__"); 3194 // Fallthrough 3195 case CK_Pentium2: 3196 case CK_C3_2: 3197 Builder.defineMacro("__tune_pentium2__"); 3198 // Fallthrough 3199 case CK_PentiumPro: 3200 Builder.defineMacro("__tune_i686__"); 3201 Builder.defineMacro("__tune_pentiumpro__"); 3202 // Fallthrough 3203 case CK_i686: 3204 Builder.defineMacro("__i686"); 3205 Builder.defineMacro("__i686__"); 3206 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3207 Builder.defineMacro("__pentiumpro"); 3208 Builder.defineMacro("__pentiumpro__"); 3209 break; 3210 case CK_Pentium4: 3211 case CK_Pentium4M: 3212 defineCPUMacros(Builder, "pentium4"); 3213 break; 3214 case CK_Yonah: 3215 case CK_Prescott: 3216 case CK_Nocona: 3217 defineCPUMacros(Builder, "nocona"); 3218 break; 3219 case CK_Core2: 3220 case CK_Penryn: 3221 defineCPUMacros(Builder, "core2"); 3222 break; 3223 case CK_Bonnell: 3224 defineCPUMacros(Builder, "atom"); 3225 break; 3226 case CK_Silvermont: 3227 defineCPUMacros(Builder, "slm"); 3228 break; 3229 case CK_Nehalem: 3230 case CK_Westmere: 3231 case CK_SandyBridge: 3232 case CK_IvyBridge: 3233 case CK_Haswell: 3234 case CK_Broadwell: 3235 case CK_SkylakeClient: 3236 // FIXME: Historically, we defined this legacy name, it would be nice to 3237 // remove it at some point. We've never exposed fine-grained names for 3238 // recent primary x86 CPUs, and we should keep it that way. 3239 defineCPUMacros(Builder, "corei7"); 3240 break; 3241 case CK_SkylakeServer: 3242 defineCPUMacros(Builder, "skx"); 3243 break; 3244 case CK_Cannonlake: 3245 break; 3246 case CK_KNL: 3247 defineCPUMacros(Builder, "knl"); 3248 break; 3249 case CK_K6_2: 3250 Builder.defineMacro("__k6_2__"); 3251 Builder.defineMacro("__tune_k6_2__"); 3252 // Fallthrough 3253 case CK_K6_3: 3254 if (CPU != CK_K6_2) { // In case of fallthrough 3255 // FIXME: GCC may be enabling these in cases where some other k6 3256 // architecture is specified but -m3dnow is explicitly provided. The 3257 // exact semantics need to be determined and emulated here. 3258 Builder.defineMacro("__k6_3__"); 3259 Builder.defineMacro("__tune_k6_3__"); 3260 } 3261 // Fallthrough 3262 case CK_K6: 3263 defineCPUMacros(Builder, "k6"); 3264 break; 3265 case CK_Athlon: 3266 case CK_AthlonThunderbird: 3267 case CK_Athlon4: 3268 case CK_AthlonXP: 3269 case CK_AthlonMP: 3270 defineCPUMacros(Builder, "athlon"); 3271 if (SSELevel != NoSSE) { 3272 Builder.defineMacro("__athlon_sse__"); 3273 Builder.defineMacro("__tune_athlon_sse__"); 3274 } 3275 break; 3276 case CK_K8: 3277 case CK_K8SSE3: 3278 case CK_x86_64: 3279 case CK_Opteron: 3280 case CK_OpteronSSE3: 3281 case CK_Athlon64: 3282 case CK_Athlon64SSE3: 3283 case CK_AthlonFX: 3284 defineCPUMacros(Builder, "k8"); 3285 break; 3286 case CK_AMDFAM10: 3287 defineCPUMacros(Builder, "amdfam10"); 3288 break; 3289 case CK_BTVER1: 3290 defineCPUMacros(Builder, "btver1"); 3291 break; 3292 case CK_BTVER2: 3293 defineCPUMacros(Builder, "btver2"); 3294 break; 3295 case CK_BDVER1: 3296 defineCPUMacros(Builder, "bdver1"); 3297 break; 3298 case CK_BDVER2: 3299 defineCPUMacros(Builder, "bdver2"); 3300 break; 3301 case CK_BDVER3: 3302 defineCPUMacros(Builder, "bdver3"); 3303 break; 3304 case CK_BDVER4: 3305 defineCPUMacros(Builder, "bdver4"); 3306 break; 3307 case CK_Geode: 3308 defineCPUMacros(Builder, "geode"); 3309 break; 3310 } 3311 3312 // Target properties. 3313 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3314 3315 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3316 // functions in glibc header files that use FP Stack inline asm which the 3317 // backend can't deal with (PR879). 3318 Builder.defineMacro("__NO_MATH_INLINES"); 3319 3320 if (HasAES) 3321 Builder.defineMacro("__AES__"); 3322 3323 if (HasPCLMUL) 3324 Builder.defineMacro("__PCLMUL__"); 3325 3326 if (HasLZCNT) 3327 Builder.defineMacro("__LZCNT__"); 3328 3329 if (HasRDRND) 3330 Builder.defineMacro("__RDRND__"); 3331 3332 if (HasFSGSBASE) 3333 Builder.defineMacro("__FSGSBASE__"); 3334 3335 if (HasBMI) 3336 Builder.defineMacro("__BMI__"); 3337 3338 if (HasBMI2) 3339 Builder.defineMacro("__BMI2__"); 3340 3341 if (HasPOPCNT) 3342 Builder.defineMacro("__POPCNT__"); 3343 3344 if (HasRTM) 3345 Builder.defineMacro("__RTM__"); 3346 3347 if (HasPRFCHW) 3348 Builder.defineMacro("__PRFCHW__"); 3349 3350 if (HasRDSEED) 3351 Builder.defineMacro("__RDSEED__"); 3352 3353 if (HasADX) 3354 Builder.defineMacro("__ADX__"); 3355 3356 if (HasTBM) 3357 Builder.defineMacro("__TBM__"); 3358 3359 switch (XOPLevel) { 3360 case XOP: 3361 Builder.defineMacro("__XOP__"); 3362 case FMA4: 3363 Builder.defineMacro("__FMA4__"); 3364 case SSE4A: 3365 Builder.defineMacro("__SSE4A__"); 3366 case NoXOP: 3367 break; 3368 } 3369 3370 if (HasFMA) 3371 Builder.defineMacro("__FMA__"); 3372 3373 if (HasF16C) 3374 Builder.defineMacro("__F16C__"); 3375 3376 if (HasAVX512CD) 3377 Builder.defineMacro("__AVX512CD__"); 3378 if (HasAVX512ER) 3379 Builder.defineMacro("__AVX512ER__"); 3380 if (HasAVX512PF) 3381 Builder.defineMacro("__AVX512PF__"); 3382 if (HasAVX512DQ) 3383 Builder.defineMacro("__AVX512DQ__"); 3384 if (HasAVX512BW) 3385 Builder.defineMacro("__AVX512BW__"); 3386 if (HasAVX512VL) 3387 Builder.defineMacro("__AVX512VL__"); 3388 if (HasAVX512VBMI) 3389 Builder.defineMacro("__AVX512VBMI__"); 3390 if (HasAVX512IFMA) 3391 Builder.defineMacro("__AVX512IFMA__"); 3392 3393 if (HasSHA) 3394 Builder.defineMacro("__SHA__"); 3395 3396 if (HasFXSR) 3397 Builder.defineMacro("__FXSR__"); 3398 if (HasXSAVE) 3399 Builder.defineMacro("__XSAVE__"); 3400 if (HasXSAVEOPT) 3401 Builder.defineMacro("__XSAVEOPT__"); 3402 if (HasXSAVEC) 3403 Builder.defineMacro("__XSAVEC__"); 3404 if (HasXSAVES) 3405 Builder.defineMacro("__XSAVES__"); 3406 if (HasPKU) 3407 Builder.defineMacro("__PKU__"); 3408 if (HasCX16) 3409 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3410 3411 // Each case falls through to the previous one here. 3412 switch (SSELevel) { 3413 case AVX512F: 3414 Builder.defineMacro("__AVX512F__"); 3415 case AVX2: 3416 Builder.defineMacro("__AVX2__"); 3417 case AVX: 3418 Builder.defineMacro("__AVX__"); 3419 case SSE42: 3420 Builder.defineMacro("__SSE4_2__"); 3421 case SSE41: 3422 Builder.defineMacro("__SSE4_1__"); 3423 case SSSE3: 3424 Builder.defineMacro("__SSSE3__"); 3425 case SSE3: 3426 Builder.defineMacro("__SSE3__"); 3427 case SSE2: 3428 Builder.defineMacro("__SSE2__"); 3429 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3430 case SSE1: 3431 Builder.defineMacro("__SSE__"); 3432 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3433 case NoSSE: 3434 break; 3435 } 3436 3437 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3438 switch (SSELevel) { 3439 case AVX512F: 3440 case AVX2: 3441 case AVX: 3442 case SSE42: 3443 case SSE41: 3444 case SSSE3: 3445 case SSE3: 3446 case SSE2: 3447 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3448 break; 3449 case SSE1: 3450 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3451 break; 3452 default: 3453 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3454 } 3455 } 3456 3457 // Each case falls through to the previous one here. 3458 switch (MMX3DNowLevel) { 3459 case AMD3DNowAthlon: 3460 Builder.defineMacro("__3dNOW_A__"); 3461 case AMD3DNow: 3462 Builder.defineMacro("__3dNOW__"); 3463 case MMX: 3464 Builder.defineMacro("__MMX__"); 3465 case NoMMX3DNow: 3466 break; 3467 } 3468 3469 if (CPU >= CK_i486) { 3470 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3471 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3472 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3473 } 3474 if (CPU >= CK_i586) 3475 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3476 } 3477 3478 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3479 return llvm::StringSwitch<bool>(Feature) 3480 .Case("aes", HasAES) 3481 .Case("avx", SSELevel >= AVX) 3482 .Case("avx2", SSELevel >= AVX2) 3483 .Case("avx512f", SSELevel >= AVX512F) 3484 .Case("avx512cd", HasAVX512CD) 3485 .Case("avx512er", HasAVX512ER) 3486 .Case("avx512pf", HasAVX512PF) 3487 .Case("avx512dq", HasAVX512DQ) 3488 .Case("avx512bw", HasAVX512BW) 3489 .Case("avx512vl", HasAVX512VL) 3490 .Case("avx512vbmi", HasAVX512VBMI) 3491 .Case("avx512ifma", HasAVX512IFMA) 3492 .Case("bmi", HasBMI) 3493 .Case("bmi2", HasBMI2) 3494 .Case("clflushopt", HasCLFLUSHOPT) 3495 .Case("clwb", HasCLWB) 3496 .Case("cx16", HasCX16) 3497 .Case("f16c", HasF16C) 3498 .Case("fma", HasFMA) 3499 .Case("fma4", XOPLevel >= FMA4) 3500 .Case("fsgsbase", HasFSGSBASE) 3501 .Case("fxsr", HasFXSR) 3502 .Case("lzcnt", HasLZCNT) 3503 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3504 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3505 .Case("mmx", MMX3DNowLevel >= MMX) 3506 .Case("movbe", HasMOVBE) 3507 .Case("mpx", HasMPX) 3508 .Case("pclmul", HasPCLMUL) 3509 .Case("pcommit", HasPCOMMIT) 3510 .Case("pku", HasPKU) 3511 .Case("popcnt", HasPOPCNT) 3512 .Case("prefetchwt1", HasPREFETCHWT1) 3513 .Case("prfchw", HasPRFCHW) 3514 .Case("rdrnd", HasRDRND) 3515 .Case("rdseed", HasRDSEED) 3516 .Case("rtm", HasRTM) 3517 .Case("sgx", HasSGX) 3518 .Case("sha", HasSHA) 3519 .Case("sse", SSELevel >= SSE1) 3520 .Case("sse2", SSELevel >= SSE2) 3521 .Case("sse3", SSELevel >= SSE3) 3522 .Case("ssse3", SSELevel >= SSSE3) 3523 .Case("sse4.1", SSELevel >= SSE41) 3524 .Case("sse4.2", SSELevel >= SSE42) 3525 .Case("sse4a", XOPLevel >= SSE4A) 3526 .Case("tbm", HasTBM) 3527 .Case("umip", HasUMIP) 3528 .Case("x86", true) 3529 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3530 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3531 .Case("xop", XOPLevel >= XOP) 3532 .Case("xsave", HasXSAVE) 3533 .Case("xsavec", HasXSAVEC) 3534 .Case("xsaves", HasXSAVES) 3535 .Case("xsaveopt", HasXSAVEOPT) 3536 .Default(false); 3537 } 3538 3539 // We can't use a generic validation scheme for the features accepted here 3540 // versus subtarget features accepted in the target attribute because the 3541 // bitfield structure that's initialized in the runtime only supports the 3542 // below currently rather than the full range of subtarget features. (See 3543 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3544 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3545 return llvm::StringSwitch<bool>(FeatureStr) 3546 .Case("cmov", true) 3547 .Case("mmx", true) 3548 .Case("popcnt", true) 3549 .Case("sse", true) 3550 .Case("sse2", true) 3551 .Case("sse3", true) 3552 .Case("sse4.1", true) 3553 .Case("sse4.2", true) 3554 .Case("avx", true) 3555 .Case("avx2", true) 3556 .Case("sse4a", true) 3557 .Case("fma4", true) 3558 .Case("xop", true) 3559 .Case("fma", true) 3560 .Case("avx512f", true) 3561 .Case("bmi", true) 3562 .Case("bmi2", true) 3563 .Default(false); 3564 } 3565 3566 bool 3567 X86TargetInfo::validateAsmConstraint(const char *&Name, 3568 TargetInfo::ConstraintInfo &Info) const { 3569 switch (*Name) { 3570 default: return false; 3571 // Constant constraints. 3572 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3573 // instructions. 3574 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3575 // x86_64 instructions. 3576 case 's': 3577 Info.setRequiresImmediate(); 3578 return true; 3579 case 'I': 3580 Info.setRequiresImmediate(0, 31); 3581 return true; 3582 case 'J': 3583 Info.setRequiresImmediate(0, 63); 3584 return true; 3585 case 'K': 3586 Info.setRequiresImmediate(-128, 127); 3587 return true; 3588 case 'L': 3589 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3590 return true; 3591 case 'M': 3592 Info.setRequiresImmediate(0, 3); 3593 return true; 3594 case 'N': 3595 Info.setRequiresImmediate(0, 255); 3596 return true; 3597 case 'O': 3598 Info.setRequiresImmediate(0, 127); 3599 return true; 3600 // Register constraints. 3601 case 'Y': // 'Y' is the first character for several 2-character constraints. 3602 // Shift the pointer to the second character of the constraint. 3603 Name++; 3604 switch (*Name) { 3605 default: 3606 return false; 3607 case '0': // First SSE register. 3608 case 't': // Any SSE register, when SSE2 is enabled. 3609 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3610 case 'm': // Any MMX register, when inter-unit moves enabled. 3611 Info.setAllowsRegister(); 3612 return true; 3613 } 3614 case 'f': // Any x87 floating point stack register. 3615 // Constraint 'f' cannot be used for output operands. 3616 if (Info.ConstraintStr[0] == '=') 3617 return false; 3618 Info.setAllowsRegister(); 3619 return true; 3620 case 'a': // eax. 3621 case 'b': // ebx. 3622 case 'c': // ecx. 3623 case 'd': // edx. 3624 case 'S': // esi. 3625 case 'D': // edi. 3626 case 'A': // edx:eax. 3627 case 't': // Top of floating point stack. 3628 case 'u': // Second from top of floating point stack. 3629 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3630 case 'y': // Any MMX register. 3631 case 'x': // Any SSE register. 3632 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3633 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3634 case 'l': // "Index" registers: any general register that can be used as an 3635 // index in a base+index memory access. 3636 Info.setAllowsRegister(); 3637 return true; 3638 // Floating point constant constraints. 3639 case 'C': // SSE floating point constant. 3640 case 'G': // x87 floating point constant. 3641 return true; 3642 } 3643 } 3644 3645 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3646 unsigned Size) const { 3647 // Strip off constraint modifiers. 3648 while (Constraint[0] == '=' || 3649 Constraint[0] == '+' || 3650 Constraint[0] == '&') 3651 Constraint = Constraint.substr(1); 3652 3653 return validateOperandSize(Constraint, Size); 3654 } 3655 3656 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3657 unsigned Size) const { 3658 return validateOperandSize(Constraint, Size); 3659 } 3660 3661 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3662 unsigned Size) const { 3663 switch (Constraint[0]) { 3664 default: break; 3665 case 'y': 3666 return Size <= 64; 3667 case 'f': 3668 case 't': 3669 case 'u': 3670 return Size <= 128; 3671 case 'x': 3672 if (SSELevel >= AVX512F) 3673 // 512-bit zmm registers can be used if target supports AVX512F. 3674 return Size <= 512U; 3675 else if (SSELevel >= AVX) 3676 // 256-bit ymm registers can be used if target supports AVX. 3677 return Size <= 256U; 3678 return Size <= 128U; 3679 case 'Y': 3680 // 'Y' is the first character for several 2-character constraints. 3681 switch (Constraint[1]) { 3682 default: break; 3683 case 'm': 3684 // 'Ym' is synonymous with 'y'. 3685 return Size <= 64; 3686 case 'i': 3687 case 't': 3688 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3689 if (SSELevel >= AVX512F) 3690 return Size <= 512U; 3691 else if (SSELevel >= AVX) 3692 return Size <= 256U; 3693 return SSELevel >= SSE2 && Size <= 128U; 3694 } 3695 3696 } 3697 3698 return true; 3699 } 3700 3701 std::string 3702 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3703 switch (*Constraint) { 3704 case 'a': return std::string("{ax}"); 3705 case 'b': return std::string("{bx}"); 3706 case 'c': return std::string("{cx}"); 3707 case 'd': return std::string("{dx}"); 3708 case 'S': return std::string("{si}"); 3709 case 'D': return std::string("{di}"); 3710 case 'p': // address 3711 return std::string("im"); 3712 case 't': // top of floating point stack. 3713 return std::string("{st}"); 3714 case 'u': // second from top of floating point stack. 3715 return std::string("{st(1)}"); // second from top of floating point stack. 3716 default: 3717 return std::string(1, *Constraint); 3718 } 3719 } 3720 3721 // X86-32 generic target 3722 class X86_32TargetInfo : public X86TargetInfo { 3723 public: 3724 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3725 DoubleAlign = LongLongAlign = 32; 3726 LongDoubleWidth = 96; 3727 LongDoubleAlign = 32; 3728 SuitableAlign = 128; 3729 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 3730 SizeType = UnsignedInt; 3731 PtrDiffType = SignedInt; 3732 IntPtrType = SignedInt; 3733 RegParmMax = 3; 3734 3735 // Use fpret for all types. 3736 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3737 (1 << TargetInfo::Double) | 3738 (1 << TargetInfo::LongDouble)); 3739 3740 // x86-32 has atomics up to 8 bytes 3741 // FIXME: Check that we actually have cmpxchg8b before setting 3742 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3743 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3744 } 3745 BuiltinVaListKind getBuiltinVaListKind() const override { 3746 return TargetInfo::CharPtrBuiltinVaList; 3747 } 3748 3749 int getEHDataRegisterNumber(unsigned RegNo) const override { 3750 if (RegNo == 0) return 0; 3751 if (RegNo == 1) return 2; 3752 return -1; 3753 } 3754 bool validateOperandSize(StringRef Constraint, 3755 unsigned Size) const override { 3756 switch (Constraint[0]) { 3757 default: break; 3758 case 'R': 3759 case 'q': 3760 case 'Q': 3761 case 'a': 3762 case 'b': 3763 case 'c': 3764 case 'd': 3765 case 'S': 3766 case 'D': 3767 return Size <= 32; 3768 case 'A': 3769 return Size <= 64; 3770 } 3771 3772 return X86TargetInfo::validateOperandSize(Constraint, Size); 3773 } 3774 }; 3775 3776 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3777 public: 3778 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3779 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3780 3781 unsigned getFloatEvalMethod() const override { 3782 unsigned Major, Minor, Micro; 3783 getTriple().getOSVersion(Major, Minor, Micro); 3784 // New NetBSD uses the default rounding mode. 3785 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3786 return X86_32TargetInfo::getFloatEvalMethod(); 3787 // NetBSD before 6.99.26 defaults to "double" rounding. 3788 return 1; 3789 } 3790 }; 3791 3792 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3793 public: 3794 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3795 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3796 SizeType = UnsignedLong; 3797 IntPtrType = SignedLong; 3798 PtrDiffType = SignedLong; 3799 } 3800 }; 3801 3802 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3803 public: 3804 BitrigI386TargetInfo(const llvm::Triple &Triple) 3805 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3806 SizeType = UnsignedLong; 3807 IntPtrType = SignedLong; 3808 PtrDiffType = SignedLong; 3809 } 3810 }; 3811 3812 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3813 public: 3814 DarwinI386TargetInfo(const llvm::Triple &Triple) 3815 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3816 LongDoubleWidth = 128; 3817 LongDoubleAlign = 128; 3818 SuitableAlign = 128; 3819 MaxVectorAlign = 256; 3820 // The watchOS simulator uses the builtin bool type for Objective-C. 3821 llvm::Triple T = llvm::Triple(Triple); 3822 if (T.isWatchOS()) 3823 UseSignedCharForObjCBool = false; 3824 SizeType = UnsignedLong; 3825 IntPtrType = SignedLong; 3826 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 3827 HasAlignMac68kSupport = true; 3828 } 3829 3830 bool handleTargetFeatures(std::vector<std::string> &Features, 3831 DiagnosticsEngine &Diags) override { 3832 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 3833 Diags)) 3834 return false; 3835 // We now know the features we have: we can decide how to align vectors. 3836 MaxVectorAlign = 3837 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3838 return true; 3839 } 3840 }; 3841 3842 // x86-32 Windows target 3843 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3844 public: 3845 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3846 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3847 WCharType = UnsignedShort; 3848 DoubleAlign = LongLongAlign = 64; 3849 bool IsWinCOFF = 3850 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3851 resetDataLayout(IsWinCOFF 3852 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3853 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 3854 } 3855 void getTargetDefines(const LangOptions &Opts, 3856 MacroBuilder &Builder) const override { 3857 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3858 } 3859 }; 3860 3861 // x86-32 Windows Visual Studio target 3862 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3863 public: 3864 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3865 : WindowsX86_32TargetInfo(Triple) { 3866 LongDoubleWidth = LongDoubleAlign = 64; 3867 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3868 } 3869 void getTargetDefines(const LangOptions &Opts, 3870 MacroBuilder &Builder) const override { 3871 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3872 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3873 // The value of the following reflects processor type. 3874 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3875 // We lost the original triple, so we use the default. 3876 Builder.defineMacro("_M_IX86", "600"); 3877 } 3878 }; 3879 3880 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3881 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 3882 // supports __declspec natively under -fms-extensions, but we define a no-op 3883 // __declspec macro anyway for pre-processor compatibility. 3884 if (Opts.MicrosoftExt) 3885 Builder.defineMacro("__declspec", "__declspec"); 3886 else 3887 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3888 3889 if (!Opts.MicrosoftExt) { 3890 // Provide macros for all the calling convention keywords. Provide both 3891 // single and double underscore prefixed variants. These are available on 3892 // x64 as well as x86, even though they have no effect. 3893 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3894 for (const char *CC : CCs) { 3895 std::string GCCSpelling = "__attribute__((__"; 3896 GCCSpelling += CC; 3897 GCCSpelling += "__))"; 3898 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3899 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3900 } 3901 } 3902 } 3903 3904 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3905 Builder.defineMacro("__MSVCRT__"); 3906 Builder.defineMacro("__MINGW32__"); 3907 addCygMingDefines(Opts, Builder); 3908 } 3909 3910 // x86-32 MinGW target 3911 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3912 public: 3913 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3914 : WindowsX86_32TargetInfo(Triple) {} 3915 void getTargetDefines(const LangOptions &Opts, 3916 MacroBuilder &Builder) const override { 3917 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3918 DefineStd(Builder, "WIN32", Opts); 3919 DefineStd(Builder, "WINNT", Opts); 3920 Builder.defineMacro("_X86_"); 3921 addMinGWDefines(Opts, Builder); 3922 } 3923 }; 3924 3925 // x86-32 Cygwin target 3926 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3927 public: 3928 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3929 : X86_32TargetInfo(Triple) { 3930 WCharType = UnsignedShort; 3931 DoubleAlign = LongLongAlign = 64; 3932 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 3933 } 3934 void getTargetDefines(const LangOptions &Opts, 3935 MacroBuilder &Builder) const override { 3936 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3937 Builder.defineMacro("_X86_"); 3938 Builder.defineMacro("__CYGWIN__"); 3939 Builder.defineMacro("__CYGWIN32__"); 3940 addCygMingDefines(Opts, Builder); 3941 DefineStd(Builder, "unix", Opts); 3942 if (Opts.CPlusPlus) 3943 Builder.defineMacro("_GNU_SOURCE"); 3944 } 3945 }; 3946 3947 // x86-32 Haiku target 3948 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3949 public: 3950 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3951 SizeType = UnsignedLong; 3952 IntPtrType = SignedLong; 3953 PtrDiffType = SignedLong; 3954 ProcessIDType = SignedLong; 3955 this->TLSSupported = false; 3956 } 3957 void getTargetDefines(const LangOptions &Opts, 3958 MacroBuilder &Builder) const override { 3959 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3960 Builder.defineMacro("__INTEL__"); 3961 Builder.defineMacro("__HAIKU__"); 3962 } 3963 }; 3964 3965 // X86-32 MCU target 3966 class MCUX86_32TargetInfo : public X86_32TargetInfo { 3967 public: 3968 MCUX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3969 LongDoubleWidth = 64; 3970 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3971 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 3972 WIntType = UnsignedInt; 3973 } 3974 3975 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3976 // On MCU we support only C calling convention. 3977 return CC == CC_C ? CCCR_OK : CCCR_Warning; 3978 } 3979 3980 void getTargetDefines(const LangOptions &Opts, 3981 MacroBuilder &Builder) const override { 3982 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3983 Builder.defineMacro("__iamcu"); 3984 Builder.defineMacro("__iamcu__"); 3985 } 3986 3987 bool allowsLargerPreferedTypeAlignment() const override { 3988 return false; 3989 } 3990 }; 3991 3992 // RTEMS Target 3993 template<typename Target> 3994 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3995 protected: 3996 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3997 MacroBuilder &Builder) const override { 3998 // RTEMS defines; list based off of gcc output 3999 4000 Builder.defineMacro("__rtems__"); 4001 Builder.defineMacro("__ELF__"); 4002 } 4003 4004 public: 4005 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 4006 switch (Triple.getArch()) { 4007 default: 4008 case llvm::Triple::x86: 4009 // this->MCountName = ".mcount"; 4010 break; 4011 case llvm::Triple::mips: 4012 case llvm::Triple::mipsel: 4013 case llvm::Triple::ppc: 4014 case llvm::Triple::ppc64: 4015 case llvm::Triple::ppc64le: 4016 // this->MCountName = "_mcount"; 4017 break; 4018 case llvm::Triple::arm: 4019 // this->MCountName = "__mcount"; 4020 break; 4021 } 4022 } 4023 }; 4024 4025 // x86-32 RTEMS target 4026 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4027 public: 4028 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 4029 SizeType = UnsignedLong; 4030 IntPtrType = SignedLong; 4031 PtrDiffType = SignedLong; 4032 } 4033 void getTargetDefines(const LangOptions &Opts, 4034 MacroBuilder &Builder) const override { 4035 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4036 Builder.defineMacro("__INTEL__"); 4037 Builder.defineMacro("__rtems__"); 4038 } 4039 }; 4040 4041 // x86-64 generic target 4042 class X86_64TargetInfo : public X86TargetInfo { 4043 public: 4044 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 4045 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4046 bool IsWinCOFF = 4047 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4048 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4049 LongDoubleWidth = 128; 4050 LongDoubleAlign = 128; 4051 LargeArrayMinWidth = 128; 4052 LargeArrayAlign = 128; 4053 SuitableAlign = 128; 4054 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4055 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4056 IntPtrType = IsX32 ? SignedInt : SignedLong; 4057 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4058 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4059 RegParmMax = 6; 4060 4061 // Pointers are 32-bit in x32. 4062 resetDataLayout(IsX32 4063 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4064 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4065 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4066 4067 // Use fpret only for long double. 4068 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4069 4070 // Use fp2ret for _Complex long double. 4071 ComplexLongDoubleUsesFP2Ret = true; 4072 4073 // Make __builtin_ms_va_list available. 4074 HasBuiltinMSVaList = true; 4075 4076 // x86-64 has atomics up to 16 bytes. 4077 MaxAtomicPromoteWidth = 128; 4078 MaxAtomicInlineWidth = 128; 4079 } 4080 BuiltinVaListKind getBuiltinVaListKind() const override { 4081 return TargetInfo::X86_64ABIBuiltinVaList; 4082 } 4083 4084 int getEHDataRegisterNumber(unsigned RegNo) const override { 4085 if (RegNo == 0) return 0; 4086 if (RegNo == 1) return 1; 4087 return -1; 4088 } 4089 4090 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4091 switch (CC) { 4092 case CC_C: 4093 case CC_Swift: 4094 case CC_X86VectorCall: 4095 case CC_IntelOclBicc: 4096 case CC_X86_64Win64: 4097 case CC_PreserveMost: 4098 case CC_PreserveAll: 4099 return CCCR_OK; 4100 default: 4101 return CCCR_Warning; 4102 } 4103 } 4104 4105 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4106 return CC_C; 4107 } 4108 4109 // for x32 we need it here explicitly 4110 bool hasInt128Type() const override { return true; } 4111 unsigned getUnwindWordWidth() const override { return 64; } 4112 unsigned getRegisterWidth() const override { return 64; } 4113 4114 bool validateGlobalRegisterVariable(StringRef RegName, 4115 unsigned RegSize, 4116 bool &HasSizeMismatch) const override { 4117 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4118 // handle. 4119 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4120 // Check that the register size is 64-bit. 4121 HasSizeMismatch = RegSize != 64; 4122 return true; 4123 } 4124 4125 // Check if the register is a 32-bit register the backend can handle. 4126 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4127 HasSizeMismatch); 4128 } 4129 }; 4130 4131 // x86-64 Windows target 4132 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4133 public: 4134 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 4135 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 4136 WCharType = UnsignedShort; 4137 LongWidth = LongAlign = 32; 4138 DoubleAlign = LongLongAlign = 64; 4139 IntMaxType = SignedLongLong; 4140 Int64Type = SignedLongLong; 4141 SizeType = UnsignedLongLong; 4142 PtrDiffType = SignedLongLong; 4143 IntPtrType = SignedLongLong; 4144 } 4145 4146 void getTargetDefines(const LangOptions &Opts, 4147 MacroBuilder &Builder) const override { 4148 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4149 Builder.defineMacro("_WIN64"); 4150 } 4151 4152 BuiltinVaListKind getBuiltinVaListKind() const override { 4153 return TargetInfo::CharPtrBuiltinVaList; 4154 } 4155 4156 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4157 switch (CC) { 4158 case CC_X86StdCall: 4159 case CC_X86ThisCall: 4160 case CC_X86FastCall: 4161 return CCCR_Ignore; 4162 case CC_C: 4163 case CC_X86VectorCall: 4164 case CC_IntelOclBicc: 4165 case CC_X86_64SysV: 4166 return CCCR_OK; 4167 default: 4168 return CCCR_Warning; 4169 } 4170 } 4171 }; 4172 4173 // x86-64 Windows Visual Studio target 4174 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4175 public: 4176 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 4177 : WindowsX86_64TargetInfo(Triple) { 4178 LongDoubleWidth = LongDoubleAlign = 64; 4179 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4180 } 4181 void getTargetDefines(const LangOptions &Opts, 4182 MacroBuilder &Builder) const override { 4183 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4184 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4185 Builder.defineMacro("_M_X64", "100"); 4186 Builder.defineMacro("_M_AMD64", "100"); 4187 } 4188 }; 4189 4190 // x86-64 MinGW target 4191 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4192 public: 4193 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 4194 : WindowsX86_64TargetInfo(Triple) { 4195 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4196 // with x86 FP ops. Weird. 4197 LongDoubleWidth = LongDoubleAlign = 128; 4198 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4199 } 4200 4201 void getTargetDefines(const LangOptions &Opts, 4202 MacroBuilder &Builder) const override { 4203 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4204 DefineStd(Builder, "WIN64", Opts); 4205 Builder.defineMacro("__MINGW64__"); 4206 addMinGWDefines(Opts, Builder); 4207 4208 // GCC defines this macro when it is using __gxx_personality_seh0. 4209 if (!Opts.SjLjExceptions) 4210 Builder.defineMacro("__SEH__"); 4211 } 4212 }; 4213 4214 // x86-64 Cygwin target 4215 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4216 public: 4217 CygwinX86_64TargetInfo(const llvm::Triple &Triple) 4218 : X86_64TargetInfo(Triple) { 4219 TLSSupported = false; 4220 WCharType = UnsignedShort; 4221 } 4222 void getTargetDefines(const LangOptions &Opts, 4223 MacroBuilder &Builder) const override { 4224 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4225 Builder.defineMacro("__x86_64__"); 4226 Builder.defineMacro("__CYGWIN__"); 4227 Builder.defineMacro("__CYGWIN64__"); 4228 addCygMingDefines(Opts, Builder); 4229 DefineStd(Builder, "unix", Opts); 4230 if (Opts.CPlusPlus) 4231 Builder.defineMacro("_GNU_SOURCE"); 4232 4233 // GCC defines this macro when it is using __gxx_personality_seh0. 4234 if (!Opts.SjLjExceptions) 4235 Builder.defineMacro("__SEH__"); 4236 } 4237 }; 4238 4239 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4240 public: 4241 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 4242 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 4243 Int64Type = SignedLongLong; 4244 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4245 llvm::Triple T = llvm::Triple(Triple); 4246 if (T.isiOS()) 4247 UseSignedCharForObjCBool = false; 4248 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4249 } 4250 4251 bool handleTargetFeatures(std::vector<std::string> &Features, 4252 DiagnosticsEngine &Diags) override { 4253 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4254 Diags)) 4255 return false; 4256 // We now know the features we have: we can decide how to align vectors. 4257 MaxVectorAlign = 4258 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4259 return true; 4260 } 4261 }; 4262 4263 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4264 public: 4265 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 4266 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 4267 IntMaxType = SignedLongLong; 4268 Int64Type = SignedLongLong; 4269 } 4270 }; 4271 4272 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4273 public: 4274 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 4275 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 4276 IntMaxType = SignedLongLong; 4277 Int64Type = SignedLongLong; 4278 } 4279 }; 4280 4281 class ARMTargetInfo : public TargetInfo { 4282 // Possible FPU choices. 4283 enum FPUMode { 4284 VFP2FPU = (1 << 0), 4285 VFP3FPU = (1 << 1), 4286 VFP4FPU = (1 << 2), 4287 NeonFPU = (1 << 3), 4288 FPARMV8 = (1 << 4) 4289 }; 4290 4291 // Possible HWDiv features. 4292 enum HWDivMode { 4293 HWDivThumb = (1 << 0), 4294 HWDivARM = (1 << 1) 4295 }; 4296 4297 static bool FPUModeIsVFP(FPUMode Mode) { 4298 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4299 } 4300 4301 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4302 static const char * const GCCRegNames[]; 4303 4304 std::string ABI, CPU; 4305 4306 StringRef CPUProfile; 4307 StringRef CPUAttr; 4308 4309 enum { 4310 FP_Default, 4311 FP_VFP, 4312 FP_Neon 4313 } FPMath; 4314 4315 unsigned ArchISA; 4316 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4317 unsigned ArchProfile; 4318 unsigned ArchVersion; 4319 4320 unsigned FPU : 5; 4321 4322 unsigned IsAAPCS : 1; 4323 unsigned HWDiv : 2; 4324 4325 // Initialized via features. 4326 unsigned SoftFloat : 1; 4327 unsigned SoftFloatABI : 1; 4328 4329 unsigned CRC : 1; 4330 unsigned Crypto : 1; 4331 unsigned DSP : 1; 4332 unsigned Unaligned : 1; 4333 4334 enum { 4335 LDREX_B = (1 << 0), /// byte (8-bit) 4336 LDREX_H = (1 << 1), /// half (16-bit) 4337 LDREX_W = (1 << 2), /// word (32-bit) 4338 LDREX_D = (1 << 3), /// double (64-bit) 4339 }; 4340 4341 uint32_t LDREX; 4342 4343 // ACLE 6.5.1 Hardware floating point 4344 enum { 4345 HW_FP_HP = (1 << 1), /// half (16-bit) 4346 HW_FP_SP = (1 << 2), /// single (32-bit) 4347 HW_FP_DP = (1 << 3), /// double (64-bit) 4348 }; 4349 uint32_t HW_FP; 4350 4351 static const Builtin::Info BuiltinInfo[]; 4352 4353 void setABIAAPCS() { 4354 IsAAPCS = true; 4355 4356 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4357 const llvm::Triple &T = getTriple(); 4358 4359 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4360 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4361 T.getOS() == llvm::Triple::Bitrig) 4362 SizeType = UnsignedLong; 4363 else 4364 SizeType = UnsignedInt; 4365 4366 switch (T.getOS()) { 4367 case llvm::Triple::NetBSD: 4368 WCharType = SignedInt; 4369 break; 4370 case llvm::Triple::Win32: 4371 WCharType = UnsignedShort; 4372 break; 4373 case llvm::Triple::Linux: 4374 default: 4375 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4376 WCharType = UnsignedInt; 4377 break; 4378 } 4379 4380 UseBitFieldTypeAlignment = true; 4381 4382 ZeroLengthBitfieldBoundary = 0; 4383 4384 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4385 // so set preferred for small types to 32. 4386 if (T.isOSBinFormatMachO()) { 4387 resetDataLayout(BigEndian 4388 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4389 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4390 } else if (T.isOSWindows()) { 4391 assert(!BigEndian && "Windows on ARM does not support big endian"); 4392 resetDataLayout("e" 4393 "-m:w" 4394 "-p:32:32" 4395 "-i64:64" 4396 "-v128:64:128" 4397 "-a:0:32" 4398 "-n32" 4399 "-S64"); 4400 } else if (T.isOSNaCl()) { 4401 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4402 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4403 } else { 4404 resetDataLayout(BigEndian 4405 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4406 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4407 } 4408 4409 // FIXME: Enumerated types are variable width in straight AAPCS. 4410 } 4411 4412 void setABIAPCS(bool IsAAPCS16) { 4413 const llvm::Triple &T = getTriple(); 4414 4415 IsAAPCS = false; 4416 4417 if (IsAAPCS16) 4418 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4419 else 4420 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4421 4422 // size_t is unsigned int on FreeBSD. 4423 if (T.getOS() == llvm::Triple::FreeBSD) 4424 SizeType = UnsignedInt; 4425 else 4426 SizeType = UnsignedLong; 4427 4428 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4429 WCharType = SignedInt; 4430 4431 // Do not respect the alignment of bit-field types when laying out 4432 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4433 UseBitFieldTypeAlignment = false; 4434 4435 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4436 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4437 /// gcc. 4438 ZeroLengthBitfieldBoundary = 32; 4439 4440 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4441 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4442 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4443 } else if (T.isOSBinFormatMachO()) 4444 resetDataLayout( 4445 BigEndian 4446 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4447 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4448 else 4449 resetDataLayout( 4450 BigEndian 4451 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4452 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4453 4454 // FIXME: Override "preferred align" for double and long long. 4455 } 4456 4457 void setArchInfo() { 4458 StringRef ArchName = getTriple().getArchName(); 4459 4460 ArchISA = llvm::ARM::parseArchISA(ArchName); 4461 CPU = llvm::ARM::getDefaultCPU(ArchName); 4462 unsigned AK = llvm::ARM::parseArch(ArchName); 4463 if (AK != llvm::ARM::AK_INVALID) 4464 ArchKind = AK; 4465 setArchInfo(ArchKind); 4466 } 4467 4468 void setArchInfo(unsigned Kind) { 4469 StringRef SubArch; 4470 4471 // cache TargetParser info 4472 ArchKind = Kind; 4473 SubArch = llvm::ARM::getSubArch(ArchKind); 4474 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4475 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4476 4477 // cache CPU related strings 4478 CPUAttr = getCPUAttr(); 4479 CPUProfile = getCPUProfile(); 4480 } 4481 4482 void setAtomic() { 4483 // when triple does not specify a sub arch, 4484 // then we are not using inline atomics 4485 bool ShouldUseInlineAtomic = 4486 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4487 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4488 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4489 if (ArchProfile == llvm::ARM::PK_M) { 4490 MaxAtomicPromoteWidth = 32; 4491 if (ShouldUseInlineAtomic) 4492 MaxAtomicInlineWidth = 32; 4493 } 4494 else { 4495 MaxAtomicPromoteWidth = 64; 4496 if (ShouldUseInlineAtomic) 4497 MaxAtomicInlineWidth = 64; 4498 } 4499 } 4500 4501 bool isThumb() const { 4502 return (ArchISA == llvm::ARM::IK_THUMB); 4503 } 4504 4505 bool supportsThumb() const { 4506 return CPUAttr.count('T') || ArchVersion >= 6; 4507 } 4508 4509 bool supportsThumb2() const { 4510 return CPUAttr.equals("6T2") || 4511 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 4512 } 4513 4514 StringRef getCPUAttr() const { 4515 // For most sub-arches, the build attribute CPU name is enough. 4516 // For Cortex variants, it's slightly different. 4517 switch(ArchKind) { 4518 default: 4519 return llvm::ARM::getCPUAttr(ArchKind); 4520 case llvm::ARM::AK_ARMV6M: 4521 return "6M"; 4522 case llvm::ARM::AK_ARMV7S: 4523 return "7S"; 4524 case llvm::ARM::AK_ARMV7A: 4525 return "7A"; 4526 case llvm::ARM::AK_ARMV7R: 4527 return "7R"; 4528 case llvm::ARM::AK_ARMV7M: 4529 return "7M"; 4530 case llvm::ARM::AK_ARMV7EM: 4531 return "7EM"; 4532 case llvm::ARM::AK_ARMV8A: 4533 return "8A"; 4534 case llvm::ARM::AK_ARMV8_1A: 4535 return "8_1A"; 4536 case llvm::ARM::AK_ARMV8_2A: 4537 return "8_2A"; 4538 case llvm::ARM::AK_ARMV8MBaseline: 4539 return "8M_BASE"; 4540 case llvm::ARM::AK_ARMV8MMainline: 4541 return "8M_MAIN"; 4542 } 4543 } 4544 4545 StringRef getCPUProfile() const { 4546 switch(ArchProfile) { 4547 case llvm::ARM::PK_A: 4548 return "A"; 4549 case llvm::ARM::PK_R: 4550 return "R"; 4551 case llvm::ARM::PK_M: 4552 return "M"; 4553 default: 4554 return ""; 4555 } 4556 } 4557 4558 public: 4559 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4560 : TargetInfo(Triple), FPMath(FP_Default), 4561 IsAAPCS(true), LDREX(0), HW_FP(0) { 4562 BigEndian = IsBigEndian; 4563 4564 switch (getTriple().getOS()) { 4565 case llvm::Triple::NetBSD: 4566 PtrDiffType = SignedLong; 4567 break; 4568 default: 4569 PtrDiffType = SignedInt; 4570 break; 4571 } 4572 4573 // Cache arch related info. 4574 setArchInfo(); 4575 4576 // {} in inline assembly are neon specifiers, not assembly variant 4577 // specifiers. 4578 NoAsmVariants = true; 4579 4580 // FIXME: This duplicates code from the driver that sets the -target-abi 4581 // option - this code is used if -target-abi isn't passed and should 4582 // be unified in some way. 4583 if (Triple.isOSBinFormatMachO()) { 4584 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4585 // the frontend matches that. 4586 if (Triple.getEnvironment() == llvm::Triple::EABI || 4587 Triple.getOS() == llvm::Triple::UnknownOS || 4588 StringRef(CPU).startswith("cortex-m")) { 4589 setABI("aapcs"); 4590 } else if (Triple.isWatchABI()) { 4591 setABI("aapcs16"); 4592 } else { 4593 setABI("apcs-gnu"); 4594 } 4595 } else if (Triple.isOSWindows()) { 4596 // FIXME: this is invalid for WindowsCE 4597 setABI("aapcs"); 4598 } else { 4599 // Select the default based on the platform. 4600 switch (Triple.getEnvironment()) { 4601 case llvm::Triple::Android: 4602 case llvm::Triple::GNUEABI: 4603 case llvm::Triple::GNUEABIHF: 4604 setABI("aapcs-linux"); 4605 break; 4606 case llvm::Triple::EABIHF: 4607 case llvm::Triple::EABI: 4608 setABI("aapcs"); 4609 break; 4610 case llvm::Triple::GNU: 4611 setABI("apcs-gnu"); 4612 break; 4613 default: 4614 if (Triple.getOS() == llvm::Triple::NetBSD) 4615 setABI("apcs-gnu"); 4616 else 4617 setABI("aapcs"); 4618 break; 4619 } 4620 } 4621 4622 // ARM targets default to using the ARM C++ ABI. 4623 TheCXXABI.set(TargetCXXABI::GenericARM); 4624 4625 // ARM has atomics up to 8 bytes 4626 setAtomic(); 4627 4628 // Do force alignment of members that follow zero length bitfields. If 4629 // the alignment of the zero-length bitfield is greater than the member 4630 // that follows it, `bar', `bar' will be aligned as the type of the 4631 // zero length bitfield. 4632 UseZeroLengthBitfieldAlignment = true; 4633 } 4634 4635 StringRef getABI() const override { return ABI; } 4636 4637 bool setABI(const std::string &Name) override { 4638 ABI = Name; 4639 4640 // The defaults (above) are for AAPCS, check if we need to change them. 4641 // 4642 // FIXME: We need support for -meabi... we could just mangle it into the 4643 // name. 4644 if (Name == "apcs-gnu" || Name == "aapcs16") { 4645 setABIAPCS(Name == "aapcs16"); 4646 return true; 4647 } 4648 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4649 setABIAAPCS(); 4650 return true; 4651 } 4652 return false; 4653 } 4654 4655 // FIXME: This should be based on Arch attributes, not CPU names. 4656 bool 4657 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4658 StringRef CPU, 4659 const std::vector<std::string> &FeaturesVec) const override { 4660 4661 std::vector<const char*> TargetFeatures; 4662 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4663 4664 // get default FPU features 4665 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4666 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4667 4668 // get default Extension features 4669 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 4670 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4671 4672 for (const char *Feature : TargetFeatures) 4673 if (Feature[0] == '+') 4674 Features[Feature+1] = true; 4675 4676 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4677 } 4678 4679 bool handleTargetFeatures(std::vector<std::string> &Features, 4680 DiagnosticsEngine &Diags) override { 4681 FPU = 0; 4682 CRC = 0; 4683 Crypto = 0; 4684 DSP = 0; 4685 Unaligned = 1; 4686 SoftFloat = SoftFloatABI = false; 4687 HWDiv = 0; 4688 4689 // This does not diagnose illegal cases like having both 4690 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4691 uint32_t HW_FP_remove = 0; 4692 for (const auto &Feature : Features) { 4693 if (Feature == "+soft-float") { 4694 SoftFloat = true; 4695 } else if (Feature == "+soft-float-abi") { 4696 SoftFloatABI = true; 4697 } else if (Feature == "+vfp2") { 4698 FPU |= VFP2FPU; 4699 HW_FP |= HW_FP_SP | HW_FP_DP; 4700 } else if (Feature == "+vfp3") { 4701 FPU |= VFP3FPU; 4702 HW_FP |= HW_FP_SP | HW_FP_DP; 4703 } else if (Feature == "+vfp4") { 4704 FPU |= VFP4FPU; 4705 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4706 } else if (Feature == "+fp-armv8") { 4707 FPU |= FPARMV8; 4708 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4709 } else if (Feature == "+neon") { 4710 FPU |= NeonFPU; 4711 HW_FP |= HW_FP_SP | HW_FP_DP; 4712 } else if (Feature == "+hwdiv") { 4713 HWDiv |= HWDivThumb; 4714 } else if (Feature == "+hwdiv-arm") { 4715 HWDiv |= HWDivARM; 4716 } else if (Feature == "+crc") { 4717 CRC = 1; 4718 } else if (Feature == "+crypto") { 4719 Crypto = 1; 4720 } else if (Feature == "+dsp") { 4721 DSP = 1; 4722 } else if (Feature == "+fp-only-sp") { 4723 HW_FP_remove |= HW_FP_DP; 4724 } else if (Feature == "+strict-align") { 4725 Unaligned = 0; 4726 } else if (Feature == "+fp16") { 4727 HW_FP |= HW_FP_HP; 4728 } 4729 } 4730 HW_FP &= ~HW_FP_remove; 4731 4732 switch (ArchVersion) { 4733 case 6: 4734 if (ArchProfile == llvm::ARM::PK_M) 4735 LDREX = 0; 4736 else if (ArchKind == llvm::ARM::AK_ARMV6K) 4737 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4738 else 4739 LDREX = LDREX_W; 4740 break; 4741 case 7: 4742 if (ArchProfile == llvm::ARM::PK_M) 4743 LDREX = LDREX_W | LDREX_H | LDREX_B ; 4744 else 4745 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4746 break; 4747 case 8: 4748 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4749 } 4750 4751 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4752 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4753 return false; 4754 } 4755 4756 if (FPMath == FP_Neon) 4757 Features.push_back("+neonfp"); 4758 else if (FPMath == FP_VFP) 4759 Features.push_back("-neonfp"); 4760 4761 // Remove front-end specific options which the backend handles differently. 4762 auto Feature = 4763 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4764 if (Feature != Features.end()) 4765 Features.erase(Feature); 4766 4767 return true; 4768 } 4769 4770 bool hasFeature(StringRef Feature) const override { 4771 return llvm::StringSwitch<bool>(Feature) 4772 .Case("arm", true) 4773 .Case("aarch32", true) 4774 .Case("softfloat", SoftFloat) 4775 .Case("thumb", isThumb()) 4776 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4777 .Case("hwdiv", HWDiv & HWDivThumb) 4778 .Case("hwdiv-arm", HWDiv & HWDivARM) 4779 .Default(false); 4780 } 4781 4782 bool setCPU(const std::string &Name) override { 4783 if (Name != "generic") 4784 setArchInfo(llvm::ARM::parseCPUArch(Name)); 4785 4786 if (ArchKind == llvm::ARM::AK_INVALID) 4787 return false; 4788 setAtomic(); 4789 CPU = Name; 4790 return true; 4791 } 4792 4793 bool setFPMath(StringRef Name) override; 4794 4795 void getTargetDefines(const LangOptions &Opts, 4796 MacroBuilder &Builder) const override { 4797 // Target identification. 4798 Builder.defineMacro("__arm"); 4799 Builder.defineMacro("__arm__"); 4800 4801 // Target properties. 4802 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4803 4804 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 4805 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 4806 if (getTriple().isWatchABI()) 4807 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 4808 4809 if (!CPUAttr.empty()) 4810 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 4811 4812 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4813 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4814 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 4815 4816 if (ArchVersion >= 8) { 4817 // ACLE 6.5.7 Crypto Extension 4818 if (Crypto) 4819 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 4820 // ACLE 6.5.8 CRC32 Extension 4821 if (CRC) 4822 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 4823 // ACLE 6.5.10 Numeric Maximum and Minimum 4824 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 4825 // ACLE 6.5.9 Directed Rounding 4826 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 4827 } 4828 4829 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4830 // is not defined for the M-profile. 4831 // NOTE that the default profile is assumed to be 'A' 4832 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 4833 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4834 4835 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 4836 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 4837 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 4838 // v7 and v8 architectures excluding v8-M Baseline. 4839 if (supportsThumb2()) 4840 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4841 else if (supportsThumb()) 4842 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4843 4844 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4845 // instruction set such as ARM or Thumb. 4846 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4847 4848 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4849 4850 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4851 if (!CPUProfile.empty()) 4852 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4853 4854 // ACLE 6.4.3 Unaligned access supported in hardware 4855 if (Unaligned) 4856 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 4857 4858 // ACLE 6.4.4 LDREX/STREX 4859 if (LDREX) 4860 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 4861 4862 // ACLE 6.4.5 CLZ 4863 if (ArchVersion == 5 || 4864 (ArchVersion == 6 && CPUProfile != "M") || 4865 ArchVersion > 6) 4866 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 4867 4868 // ACLE 6.5.1 Hardware Floating Point 4869 if (HW_FP) 4870 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4871 4872 // ACLE predefines. 4873 Builder.defineMacro("__ARM_ACLE", "200"); 4874 4875 // FP16 support (we currently only support IEEE format). 4876 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 4877 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 4878 4879 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 4880 if (ArchVersion >= 7 && (CPUProfile != "M" || CPUAttr == "7EM")) 4881 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 4882 4883 // Subtarget options. 4884 4885 // FIXME: It's more complicated than this and we don't really support 4886 // interworking. 4887 // Windows on ARM does not "support" interworking 4888 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 4889 Builder.defineMacro("__THUMB_INTERWORK__"); 4890 4891 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4892 // Embedded targets on Darwin follow AAPCS, but not EABI. 4893 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4894 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4895 Builder.defineMacro("__ARM_EABI__"); 4896 Builder.defineMacro("__ARM_PCS", "1"); 4897 4898 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4899 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4900 } 4901 4902 if (SoftFloat) 4903 Builder.defineMacro("__SOFTFP__"); 4904 4905 if (CPU == "xscale") 4906 Builder.defineMacro("__XSCALE__"); 4907 4908 if (isThumb()) { 4909 Builder.defineMacro("__THUMBEL__"); 4910 Builder.defineMacro("__thumb__"); 4911 if (supportsThumb2()) 4912 Builder.defineMacro("__thumb2__"); 4913 } 4914 4915 // ACLE 6.4.9 32-bit SIMD instructions 4916 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 4917 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 4918 4919 // ACLE 6.4.10 Hardware Integer Divide 4920 if (((HWDiv & HWDivThumb) && isThumb()) || 4921 ((HWDiv & HWDivARM) && !isThumb())) { 4922 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 4923 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4924 } 4925 4926 // Note, this is always on in gcc, even though it doesn't make sense. 4927 Builder.defineMacro("__APCS_32__"); 4928 4929 if (FPUModeIsVFP((FPUMode) FPU)) { 4930 Builder.defineMacro("__VFP_FP__"); 4931 if (FPU & VFP2FPU) 4932 Builder.defineMacro("__ARM_VFPV2__"); 4933 if (FPU & VFP3FPU) 4934 Builder.defineMacro("__ARM_VFPV3__"); 4935 if (FPU & VFP4FPU) 4936 Builder.defineMacro("__ARM_VFPV4__"); 4937 } 4938 4939 // This only gets set when Neon instructions are actually available, unlike 4940 // the VFP define, hence the soft float and arch check. This is subtly 4941 // different from gcc, we follow the intent which was that it should be set 4942 // when Neon instructions are actually available. 4943 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 4944 Builder.defineMacro("__ARM_NEON", "1"); 4945 Builder.defineMacro("__ARM_NEON__"); 4946 // current AArch32 NEON implementations do not support double-precision 4947 // floating-point even when it is present in VFP. 4948 Builder.defineMacro("__ARM_NEON_FP", 4949 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 4950 } 4951 4952 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4953 Opts.ShortWChar ? "2" : "4"); 4954 4955 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4956 Opts.ShortEnums ? "1" : "4"); 4957 4958 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 4959 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4960 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4961 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4962 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4963 } 4964 4965 // ACLE 6.4.7 DSP instructions 4966 if (DSP) { 4967 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 4968 } 4969 4970 // ACLE 6.4.8 Saturation instructions 4971 bool SAT = false; 4972 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 4973 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 4974 SAT = true; 4975 } 4976 4977 // ACLE 6.4.6 Q (saturation) flag 4978 if (DSP || SAT) 4979 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 4980 4981 if (Opts.UnsafeFPMath) 4982 Builder.defineMacro("__ARM_FP_FAST", "1"); 4983 4984 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 4985 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 4986 } 4987 4988 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4989 return llvm::makeArrayRef(BuiltinInfo, 4990 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 4991 } 4992 bool isCLZForZeroUndef() const override { return false; } 4993 BuiltinVaListKind getBuiltinVaListKind() const override { 4994 return IsAAPCS 4995 ? AAPCSABIBuiltinVaList 4996 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 4997 : TargetInfo::VoidPtrBuiltinVaList); 4998 } 4999 ArrayRef<const char *> getGCCRegNames() const override; 5000 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5001 bool validateAsmConstraint(const char *&Name, 5002 TargetInfo::ConstraintInfo &Info) const override { 5003 switch (*Name) { 5004 default: break; 5005 case 'l': // r0-r7 5006 case 'h': // r8-r15 5007 case 't': // VFP Floating point register single precision 5008 case 'w': // VFP Floating point register double precision 5009 Info.setAllowsRegister(); 5010 return true; 5011 case 'I': 5012 case 'J': 5013 case 'K': 5014 case 'L': 5015 case 'M': 5016 // FIXME 5017 return true; 5018 case 'Q': // A memory address that is a single base register. 5019 Info.setAllowsMemory(); 5020 return true; 5021 case 'U': // a memory reference... 5022 switch (Name[1]) { 5023 case 'q': // ...ARMV4 ldrsb 5024 case 'v': // ...VFP load/store (reg+constant offset) 5025 case 'y': // ...iWMMXt load/store 5026 case 't': // address valid for load/store opaque types wider 5027 // than 128-bits 5028 case 'n': // valid address for Neon doubleword vector load/store 5029 case 'm': // valid address for Neon element and structure load/store 5030 case 's': // valid address for non-offset loads/stores of quad-word 5031 // values in four ARM registers 5032 Info.setAllowsMemory(); 5033 Name++; 5034 return true; 5035 } 5036 } 5037 return false; 5038 } 5039 std::string convertConstraint(const char *&Constraint) const override { 5040 std::string R; 5041 switch (*Constraint) { 5042 case 'U': // Two-character constraint; add "^" hint for later parsing. 5043 R = std::string("^") + std::string(Constraint, 2); 5044 Constraint++; 5045 break; 5046 case 'p': // 'p' should be translated to 'r' by default. 5047 R = std::string("r"); 5048 break; 5049 default: 5050 return std::string(1, *Constraint); 5051 } 5052 return R; 5053 } 5054 bool 5055 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5056 std::string &SuggestedModifier) const override { 5057 bool isOutput = (Constraint[0] == '='); 5058 bool isInOut = (Constraint[0] == '+'); 5059 5060 // Strip off constraint modifiers. 5061 while (Constraint[0] == '=' || 5062 Constraint[0] == '+' || 5063 Constraint[0] == '&') 5064 Constraint = Constraint.substr(1); 5065 5066 switch (Constraint[0]) { 5067 default: break; 5068 case 'r': { 5069 switch (Modifier) { 5070 default: 5071 return (isInOut || isOutput || Size <= 64); 5072 case 'q': 5073 // A register of size 32 cannot fit a vector type. 5074 return false; 5075 } 5076 } 5077 } 5078 5079 return true; 5080 } 5081 const char *getClobbers() const override { 5082 // FIXME: Is this really right? 5083 return ""; 5084 } 5085 5086 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5087 switch (CC) { 5088 case CC_AAPCS: 5089 case CC_AAPCS_VFP: 5090 case CC_Swift: 5091 return CCCR_OK; 5092 default: 5093 return CCCR_Warning; 5094 } 5095 } 5096 5097 int getEHDataRegisterNumber(unsigned RegNo) const override { 5098 if (RegNo == 0) return 0; 5099 if (RegNo == 1) return 1; 5100 return -1; 5101 } 5102 5103 bool hasSjLjLowering() const override { 5104 return true; 5105 } 5106 }; 5107 5108 bool ARMTargetInfo::setFPMath(StringRef Name) { 5109 if (Name == "neon") { 5110 FPMath = FP_Neon; 5111 return true; 5112 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5113 Name == "vfp4") { 5114 FPMath = FP_VFP; 5115 return true; 5116 } 5117 return false; 5118 } 5119 5120 const char * const ARMTargetInfo::GCCRegNames[] = { 5121 // Integer registers 5122 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5123 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5124 5125 // Float registers 5126 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5127 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5128 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5129 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5130 5131 // Double registers 5132 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5133 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5134 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5135 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5136 5137 // Quad registers 5138 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5139 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5140 }; 5141 5142 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5143 return llvm::makeArrayRef(GCCRegNames); 5144 } 5145 5146 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5147 { { "a1" }, "r0" }, 5148 { { "a2" }, "r1" }, 5149 { { "a3" }, "r2" }, 5150 { { "a4" }, "r3" }, 5151 { { "v1" }, "r4" }, 5152 { { "v2" }, "r5" }, 5153 { { "v3" }, "r6" }, 5154 { { "v4" }, "r7" }, 5155 { { "v5" }, "r8" }, 5156 { { "v6", "rfp" }, "r9" }, 5157 { { "sl" }, "r10" }, 5158 { { "fp" }, "r11" }, 5159 { { "ip" }, "r12" }, 5160 { { "r13" }, "sp" }, 5161 { { "r14" }, "lr" }, 5162 { { "r15" }, "pc" }, 5163 // The S, D and Q registers overlap, but aren't really aliases; we 5164 // don't want to substitute one of these for a different-sized one. 5165 }; 5166 5167 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5168 return llvm::makeArrayRef(GCCRegAliases); 5169 } 5170 5171 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5172 #define BUILTIN(ID, TYPE, ATTRS) \ 5173 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5174 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5175 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5176 #include "clang/Basic/BuiltinsNEON.def" 5177 5178 #define BUILTIN(ID, TYPE, ATTRS) \ 5179 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5180 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5181 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5182 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5183 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5184 #include "clang/Basic/BuiltinsARM.def" 5185 }; 5186 5187 class ARMleTargetInfo : public ARMTargetInfo { 5188 public: 5189 ARMleTargetInfo(const llvm::Triple &Triple) 5190 : ARMTargetInfo(Triple, false) { } 5191 void getTargetDefines(const LangOptions &Opts, 5192 MacroBuilder &Builder) const override { 5193 Builder.defineMacro("__ARMEL__"); 5194 ARMTargetInfo::getTargetDefines(Opts, Builder); 5195 } 5196 }; 5197 5198 class ARMbeTargetInfo : public ARMTargetInfo { 5199 public: 5200 ARMbeTargetInfo(const llvm::Triple &Triple) 5201 : ARMTargetInfo(Triple, true) { } 5202 void getTargetDefines(const LangOptions &Opts, 5203 MacroBuilder &Builder) const override { 5204 Builder.defineMacro("__ARMEB__"); 5205 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5206 ARMTargetInfo::getTargetDefines(Opts, Builder); 5207 } 5208 }; 5209 5210 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5211 const llvm::Triple Triple; 5212 public: 5213 WindowsARMTargetInfo(const llvm::Triple &Triple) 5214 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 5215 WCharType = UnsignedShort; 5216 SizeType = UnsignedInt; 5217 } 5218 void getVisualStudioDefines(const LangOptions &Opts, 5219 MacroBuilder &Builder) const { 5220 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5221 5222 // FIXME: this is invalid for WindowsCE 5223 Builder.defineMacro("_M_ARM_NT", "1"); 5224 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5225 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5226 5227 assert((Triple.getArch() == llvm::Triple::arm || 5228 Triple.getArch() == llvm::Triple::thumb) && 5229 "invalid architecture for Windows ARM target info"); 5230 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5231 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5232 5233 // TODO map the complete set of values 5234 // 31: VFPv3 40: VFPv4 5235 Builder.defineMacro("_M_ARM_FP", "31"); 5236 } 5237 BuiltinVaListKind getBuiltinVaListKind() const override { 5238 return TargetInfo::CharPtrBuiltinVaList; 5239 } 5240 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5241 switch (CC) { 5242 case CC_X86StdCall: 5243 case CC_X86ThisCall: 5244 case CC_X86FastCall: 5245 case CC_X86VectorCall: 5246 return CCCR_Ignore; 5247 case CC_C: 5248 return CCCR_OK; 5249 default: 5250 return CCCR_Warning; 5251 } 5252 } 5253 }; 5254 5255 // Windows ARM + Itanium C++ ABI Target 5256 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5257 public: 5258 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 5259 : WindowsARMTargetInfo(Triple) { 5260 TheCXXABI.set(TargetCXXABI::GenericARM); 5261 } 5262 5263 void getTargetDefines(const LangOptions &Opts, 5264 MacroBuilder &Builder) const override { 5265 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5266 5267 if (Opts.MSVCCompat) 5268 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5269 } 5270 }; 5271 5272 // Windows ARM, MS (C++) ABI 5273 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5274 public: 5275 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 5276 : WindowsARMTargetInfo(Triple) { 5277 TheCXXABI.set(TargetCXXABI::Microsoft); 5278 } 5279 5280 void getTargetDefines(const LangOptions &Opts, 5281 MacroBuilder &Builder) const override { 5282 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5283 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5284 } 5285 }; 5286 5287 // ARM MinGW target 5288 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5289 public: 5290 MinGWARMTargetInfo(const llvm::Triple &Triple) 5291 : WindowsARMTargetInfo(Triple) { 5292 TheCXXABI.set(TargetCXXABI::GenericARM); 5293 } 5294 5295 void getTargetDefines(const LangOptions &Opts, 5296 MacroBuilder &Builder) const override { 5297 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5298 DefineStd(Builder, "WIN32", Opts); 5299 DefineStd(Builder, "WINNT", Opts); 5300 Builder.defineMacro("_ARM_"); 5301 addMinGWDefines(Opts, Builder); 5302 } 5303 }; 5304 5305 // ARM Cygwin target 5306 class CygwinARMTargetInfo : public ARMleTargetInfo { 5307 public: 5308 CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) { 5309 TLSSupported = false; 5310 WCharType = UnsignedShort; 5311 DoubleAlign = LongLongAlign = 64; 5312 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5313 } 5314 void getTargetDefines(const LangOptions &Opts, 5315 MacroBuilder &Builder) const override { 5316 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5317 Builder.defineMacro("_ARM_"); 5318 Builder.defineMacro("__CYGWIN__"); 5319 Builder.defineMacro("__CYGWIN32__"); 5320 DefineStd(Builder, "unix", Opts); 5321 if (Opts.CPlusPlus) 5322 Builder.defineMacro("_GNU_SOURCE"); 5323 } 5324 }; 5325 5326 class DarwinARMTargetInfo : 5327 public DarwinTargetInfo<ARMleTargetInfo> { 5328 protected: 5329 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5330 MacroBuilder &Builder) const override { 5331 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5332 } 5333 5334 public: 5335 DarwinARMTargetInfo(const llvm::Triple &Triple) 5336 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 5337 HasAlignMac68kSupport = true; 5338 // iOS always has 64-bit atomic instructions. 5339 // FIXME: This should be based off of the target features in 5340 // ARMleTargetInfo. 5341 MaxAtomicInlineWidth = 64; 5342 5343 if (Triple.isWatchABI()) { 5344 // Darwin on iOS uses a variant of the ARM C++ ABI. 5345 TheCXXABI.set(TargetCXXABI::WatchOS); 5346 5347 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5348 // size_t is long, it's a bit weird for it to be int. 5349 PtrDiffType = SignedLong; 5350 5351 // BOOL should be a real boolean on the new ABI 5352 UseSignedCharForObjCBool = false; 5353 } else 5354 TheCXXABI.set(TargetCXXABI::iOS); 5355 } 5356 }; 5357 5358 class AArch64TargetInfo : public TargetInfo { 5359 virtual void setDataLayout() = 0; 5360 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5361 static const char *const GCCRegNames[]; 5362 5363 enum FPUModeEnum { 5364 FPUMode, 5365 NeonMode 5366 }; 5367 5368 unsigned FPU; 5369 unsigned CRC; 5370 unsigned Crypto; 5371 unsigned Unaligned; 5372 unsigned V8_1A; 5373 5374 static const Builtin::Info BuiltinInfo[]; 5375 5376 std::string ABI; 5377 5378 public: 5379 AArch64TargetInfo(const llvm::Triple &Triple) 5380 : TargetInfo(Triple), ABI("aapcs") { 5381 5382 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5383 WCharType = SignedInt; 5384 5385 // NetBSD apparently prefers consistency across ARM targets to consistency 5386 // across 64-bit targets. 5387 Int64Type = SignedLongLong; 5388 IntMaxType = SignedLongLong; 5389 } else { 5390 WCharType = UnsignedInt; 5391 Int64Type = SignedLong; 5392 IntMaxType = SignedLong; 5393 } 5394 5395 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5396 MaxVectorAlign = 128; 5397 MaxAtomicInlineWidth = 128; 5398 MaxAtomicPromoteWidth = 128; 5399 5400 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5401 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5402 5403 // {} in inline assembly are neon specifiers, not assembly variant 5404 // specifiers. 5405 NoAsmVariants = true; 5406 5407 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5408 // contributes to the alignment of the containing aggregate in the same way 5409 // a plain (non bit-field) member of that type would, without exception for 5410 // zero-sized or anonymous bit-fields." 5411 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5412 UseZeroLengthBitfieldAlignment = true; 5413 5414 // AArch64 targets default to using the ARM C++ ABI. 5415 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5416 } 5417 5418 StringRef getABI() const override { return ABI; } 5419 bool setABI(const std::string &Name) override { 5420 if (Name != "aapcs" && Name != "darwinpcs") 5421 return false; 5422 5423 ABI = Name; 5424 return true; 5425 } 5426 5427 bool setCPU(const std::string &Name) override { 5428 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5429 .Case("generic", true) 5430 .Cases("cortex-a53", "cortex-a57", "cortex-a72", 5431 "cortex-a35", "exynos-m1", true) 5432 .Case("cyclone", true) 5433 .Case("kryo", true) 5434 .Default(false); 5435 return CPUKnown; 5436 } 5437 5438 void getTargetDefines(const LangOptions &Opts, 5439 MacroBuilder &Builder) const override { 5440 // Target identification. 5441 Builder.defineMacro("__aarch64__"); 5442 5443 // Target properties. 5444 Builder.defineMacro("_LP64"); 5445 Builder.defineMacro("__LP64__"); 5446 5447 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5448 Builder.defineMacro("__ARM_ACLE", "200"); 5449 Builder.defineMacro("__ARM_ARCH", "8"); 5450 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5451 5452 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5453 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5454 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5455 5456 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5457 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5458 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5459 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5460 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5461 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5462 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5463 5464 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5465 5466 // 0xe implies support for half, single and double precision operations. 5467 Builder.defineMacro("__ARM_FP", "0xE"); 5468 5469 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5470 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5471 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5472 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5473 5474 if (Opts.UnsafeFPMath) 5475 Builder.defineMacro("__ARM_FP_FAST", "1"); 5476 5477 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5478 5479 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5480 Opts.ShortEnums ? "1" : "4"); 5481 5482 if (FPU == NeonMode) { 5483 Builder.defineMacro("__ARM_NEON", "1"); 5484 // 64-bit NEON supports half, single and double precision operations. 5485 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5486 } 5487 5488 if (CRC) 5489 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5490 5491 if (Crypto) 5492 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5493 5494 if (Unaligned) 5495 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5496 5497 if (V8_1A) 5498 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5499 5500 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5501 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5502 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5503 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5504 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5505 } 5506 5507 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5508 return llvm::makeArrayRef(BuiltinInfo, 5509 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5510 } 5511 5512 bool hasFeature(StringRef Feature) const override { 5513 return Feature == "aarch64" || 5514 Feature == "arm64" || 5515 Feature == "arm" || 5516 (Feature == "neon" && FPU == NeonMode); 5517 } 5518 5519 bool handleTargetFeatures(std::vector<std::string> &Features, 5520 DiagnosticsEngine &Diags) override { 5521 FPU = FPUMode; 5522 CRC = 0; 5523 Crypto = 0; 5524 Unaligned = 1; 5525 V8_1A = 0; 5526 5527 for (const auto &Feature : Features) { 5528 if (Feature == "+neon") 5529 FPU = NeonMode; 5530 if (Feature == "+crc") 5531 CRC = 1; 5532 if (Feature == "+crypto") 5533 Crypto = 1; 5534 if (Feature == "+strict-align") 5535 Unaligned = 0; 5536 if (Feature == "+v8.1a") 5537 V8_1A = 1; 5538 } 5539 5540 setDataLayout(); 5541 5542 return true; 5543 } 5544 5545 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5546 switch (CC) { 5547 case CC_C: 5548 case CC_Swift: 5549 case CC_PreserveMost: 5550 case CC_PreserveAll: 5551 return CCCR_OK; 5552 default: 5553 return CCCR_Warning; 5554 } 5555 } 5556 5557 bool isCLZForZeroUndef() const override { return false; } 5558 5559 BuiltinVaListKind getBuiltinVaListKind() const override { 5560 return TargetInfo::AArch64ABIBuiltinVaList; 5561 } 5562 5563 ArrayRef<const char *> getGCCRegNames() const override; 5564 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5565 5566 bool validateAsmConstraint(const char *&Name, 5567 TargetInfo::ConstraintInfo &Info) const override { 5568 switch (*Name) { 5569 default: 5570 return false; 5571 case 'w': // Floating point and SIMD registers (V0-V31) 5572 Info.setAllowsRegister(); 5573 return true; 5574 case 'I': // Constant that can be used with an ADD instruction 5575 case 'J': // Constant that can be used with a SUB instruction 5576 case 'K': // Constant that can be used with a 32-bit logical instruction 5577 case 'L': // Constant that can be used with a 64-bit logical instruction 5578 case 'M': // Constant that can be used as a 32-bit MOV immediate 5579 case 'N': // Constant that can be used as a 64-bit MOV immediate 5580 case 'Y': // Floating point constant zero 5581 case 'Z': // Integer constant zero 5582 return true; 5583 case 'Q': // A memory reference with base register and no offset 5584 Info.setAllowsMemory(); 5585 return true; 5586 case 'S': // A symbolic address 5587 Info.setAllowsRegister(); 5588 return true; 5589 case 'U': 5590 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5591 // Utf: A memory address suitable for ldp/stp in TF mode. 5592 // Usa: An absolute symbolic address. 5593 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5594 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5595 case 'z': // Zero register, wzr or xzr 5596 Info.setAllowsRegister(); 5597 return true; 5598 case 'x': // Floating point and SIMD registers (V0-V15) 5599 Info.setAllowsRegister(); 5600 return true; 5601 } 5602 return false; 5603 } 5604 5605 bool 5606 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5607 std::string &SuggestedModifier) const override { 5608 // Strip off constraint modifiers. 5609 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5610 Constraint = Constraint.substr(1); 5611 5612 switch (Constraint[0]) { 5613 default: 5614 return true; 5615 case 'z': 5616 case 'r': { 5617 switch (Modifier) { 5618 case 'x': 5619 case 'w': 5620 // For now assume that the person knows what they're 5621 // doing with the modifier. 5622 return true; 5623 default: 5624 // By default an 'r' constraint will be in the 'x' 5625 // registers. 5626 if (Size == 64) 5627 return true; 5628 5629 SuggestedModifier = "w"; 5630 return false; 5631 } 5632 } 5633 } 5634 } 5635 5636 const char *getClobbers() const override { return ""; } 5637 5638 int getEHDataRegisterNumber(unsigned RegNo) const override { 5639 if (RegNo == 0) 5640 return 0; 5641 if (RegNo == 1) 5642 return 1; 5643 return -1; 5644 } 5645 }; 5646 5647 const char *const AArch64TargetInfo::GCCRegNames[] = { 5648 // 32-bit Integer registers 5649 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5650 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5651 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5652 5653 // 64-bit Integer registers 5654 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5655 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5656 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5657 5658 // 32-bit floating point regsisters 5659 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5660 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5661 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5662 5663 // 64-bit floating point regsisters 5664 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5665 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5666 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5667 5668 // Vector registers 5669 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5670 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5671 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5672 }; 5673 5674 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 5675 return llvm::makeArrayRef(GCCRegNames); 5676 } 5677 5678 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5679 { { "w31" }, "wsp" }, 5680 { { "x29" }, "fp" }, 5681 { { "x30" }, "lr" }, 5682 { { "x31" }, "sp" }, 5683 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5684 // don't want to substitute one of these for a different-sized one. 5685 }; 5686 5687 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 5688 return llvm::makeArrayRef(GCCRegAliases); 5689 } 5690 5691 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5692 #define BUILTIN(ID, TYPE, ATTRS) \ 5693 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5694 #include "clang/Basic/BuiltinsNEON.def" 5695 5696 #define BUILTIN(ID, TYPE, ATTRS) \ 5697 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5698 #include "clang/Basic/BuiltinsAArch64.def" 5699 }; 5700 5701 class AArch64leTargetInfo : public AArch64TargetInfo { 5702 void setDataLayout() override { 5703 if (getTriple().isOSBinFormatMachO()) 5704 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 5705 else 5706 resetDataLayout("e-m:e-i64:64-i128:128-n32:64-S128"); 5707 } 5708 5709 public: 5710 AArch64leTargetInfo(const llvm::Triple &Triple) 5711 : AArch64TargetInfo(Triple) { 5712 BigEndian = false; 5713 } 5714 void getTargetDefines(const LangOptions &Opts, 5715 MacroBuilder &Builder) const override { 5716 Builder.defineMacro("__AARCH64EL__"); 5717 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5718 } 5719 }; 5720 5721 class AArch64beTargetInfo : public AArch64TargetInfo { 5722 void setDataLayout() override { 5723 assert(!getTriple().isOSBinFormatMachO()); 5724 resetDataLayout("E-m:e-i64:64-i128:128-n32:64-S128"); 5725 } 5726 5727 public: 5728 AArch64beTargetInfo(const llvm::Triple &Triple) 5729 : AArch64TargetInfo(Triple) { } 5730 void getTargetDefines(const LangOptions &Opts, 5731 MacroBuilder &Builder) const override { 5732 Builder.defineMacro("__AARCH64EB__"); 5733 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5734 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5735 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5736 } 5737 }; 5738 5739 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5740 protected: 5741 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5742 MacroBuilder &Builder) const override { 5743 Builder.defineMacro("__AARCH64_SIMD__"); 5744 Builder.defineMacro("__ARM64_ARCH_8__"); 5745 Builder.defineMacro("__ARM_NEON__"); 5746 Builder.defineMacro("__LITTLE_ENDIAN__"); 5747 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5748 Builder.defineMacro("__arm64", "1"); 5749 Builder.defineMacro("__arm64__", "1"); 5750 5751 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5752 } 5753 5754 public: 5755 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5756 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5757 Int64Type = SignedLongLong; 5758 WCharType = SignedInt; 5759 UseSignedCharForObjCBool = false; 5760 5761 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5762 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5763 5764 TheCXXABI.set(TargetCXXABI::iOS64); 5765 } 5766 5767 BuiltinVaListKind getBuiltinVaListKind() const override { 5768 return TargetInfo::CharPtrBuiltinVaList; 5769 } 5770 }; 5771 5772 // Hexagon abstract base class 5773 class HexagonTargetInfo : public TargetInfo { 5774 static const Builtin::Info BuiltinInfo[]; 5775 static const char * const GCCRegNames[]; 5776 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5777 std::string CPU; 5778 bool HasHVX, HasHVXDouble; 5779 5780 public: 5781 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5782 BigEndian = false; 5783 // Specify the vector alignment explicitly. For v512x1, the calculated 5784 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 5785 // the required minimum of 64 bytes. 5786 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 5787 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 5788 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 5789 SizeType = UnsignedInt; 5790 PtrDiffType = SignedInt; 5791 IntPtrType = SignedInt; 5792 5793 // {} in inline assembly are packet specifiers, not assembly variant 5794 // specifiers. 5795 NoAsmVariants = true; 5796 5797 LargeArrayMinWidth = 64; 5798 LargeArrayAlign = 64; 5799 UseBitFieldTypeAlignment = true; 5800 ZeroLengthBitfieldBoundary = 32; 5801 HasHVX = HasHVXDouble = false; 5802 } 5803 5804 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5805 return llvm::makeArrayRef(BuiltinInfo, 5806 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 5807 } 5808 5809 bool validateAsmConstraint(const char *&Name, 5810 TargetInfo::ConstraintInfo &Info) const override { 5811 return true; 5812 } 5813 5814 void getTargetDefines(const LangOptions &Opts, 5815 MacroBuilder &Builder) const override; 5816 5817 bool isCLZForZeroUndef() const override { return false; } 5818 5819 bool hasFeature(StringRef Feature) const override { 5820 return llvm::StringSwitch<bool>(Feature) 5821 .Case("hexagon", true) 5822 .Case("hvx", HasHVX) 5823 .Case("hvx-double", HasHVXDouble) 5824 .Default(false); 5825 } 5826 5827 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5828 StringRef CPU, const std::vector<std::string> &FeaturesVec) 5829 const override; 5830 5831 bool handleTargetFeatures(std::vector<std::string> &Features, 5832 DiagnosticsEngine &Diags) override; 5833 5834 BuiltinVaListKind getBuiltinVaListKind() const override { 5835 return TargetInfo::CharPtrBuiltinVaList; 5836 } 5837 ArrayRef<const char *> getGCCRegNames() const override; 5838 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5839 const char *getClobbers() const override { 5840 return ""; 5841 } 5842 5843 static const char *getHexagonCPUSuffix(StringRef Name) { 5844 return llvm::StringSwitch<const char*>(Name) 5845 .Case("hexagonv4", "4") 5846 .Case("hexagonv5", "5") 5847 .Case("hexagonv55", "55") 5848 .Case("hexagonv60", "60") 5849 .Default(nullptr); 5850 } 5851 5852 bool setCPU(const std::string &Name) override { 5853 if (!getHexagonCPUSuffix(Name)) 5854 return false; 5855 CPU = Name; 5856 return true; 5857 } 5858 5859 int getEHDataRegisterNumber(unsigned RegNo) const override { 5860 return RegNo < 2 ? RegNo : -1; 5861 } 5862 }; 5863 5864 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5865 MacroBuilder &Builder) const { 5866 Builder.defineMacro("__qdsp6__", "1"); 5867 Builder.defineMacro("__hexagon__", "1"); 5868 5869 if (CPU == "hexagonv4") { 5870 Builder.defineMacro("__HEXAGON_V4__"); 5871 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5872 if (Opts.HexagonQdsp6Compat) { 5873 Builder.defineMacro("__QDSP6_V4__"); 5874 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5875 } 5876 } else if (CPU == "hexagonv5") { 5877 Builder.defineMacro("__HEXAGON_V5__"); 5878 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5879 if(Opts.HexagonQdsp6Compat) { 5880 Builder.defineMacro("__QDSP6_V5__"); 5881 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5882 } 5883 } else if (CPU == "hexagonv60") { 5884 Builder.defineMacro("__HEXAGON_V60__"); 5885 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 5886 Builder.defineMacro("__QDSP6_V60__"); 5887 Builder.defineMacro("__QDSP6_ARCH__", "60"); 5888 } 5889 } 5890 5891 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 5892 DiagnosticsEngine &Diags) { 5893 for (auto &F : Features) { 5894 if (F == "+hvx") 5895 HasHVX = true; 5896 else if (F == "-hvx") 5897 HasHVX = HasHVXDouble = false; 5898 else if (F == "+hvx-double") 5899 HasHVX = HasHVXDouble = true; 5900 else if (F == "-hvx-double") 5901 HasHVXDouble = false; 5902 } 5903 return true; 5904 } 5905 5906 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 5907 DiagnosticsEngine &Diags, StringRef CPU, 5908 const std::vector<std::string> &FeaturesVec) const { 5909 // Default for v60: -hvx, -hvx-double. 5910 Features["hvx"] = false; 5911 Features["hvx-double"] = false; 5912 5913 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5914 } 5915 5916 5917 const char *const HexagonTargetInfo::GCCRegNames[] = { 5918 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5919 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5920 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5921 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5922 "p0", "p1", "p2", "p3", 5923 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5924 }; 5925 5926 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 5927 return llvm::makeArrayRef(GCCRegNames); 5928 } 5929 5930 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5931 { { "sp" }, "r29" }, 5932 { { "fp" }, "r30" }, 5933 { { "lr" }, "r31" }, 5934 }; 5935 5936 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 5937 return llvm::makeArrayRef(GCCRegAliases); 5938 } 5939 5940 5941 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5942 #define BUILTIN(ID, TYPE, ATTRS) \ 5943 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5944 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5945 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5946 #include "clang/Basic/BuiltinsHexagon.def" 5947 }; 5948 5949 class LanaiTargetInfo : public TargetInfo { 5950 // Class for Lanai (32-bit). 5951 // The CPU profiles supported by the Lanai backend 5952 enum CPUKind { 5953 CK_NONE, 5954 CK_V11, 5955 } CPU; 5956 5957 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5958 static const char *const GCCRegNames[]; 5959 5960 public: 5961 LanaiTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5962 // Description string has to be kept in sync with backend. 5963 resetDataLayout("E" // Big endian 5964 "-m:e" // ELF name manging 5965 "-p:32:32" // 32 bit pointers, 32 bit aligned 5966 "-i64:64" // 64 bit integers, 64 bit aligned 5967 "-a:0:32" // 32 bit alignment of objects of aggregate type 5968 "-n32" // 32 bit native integer width 5969 "-S64" // 64 bit natural stack alignment 5970 ); 5971 5972 // Setting RegParmMax equal to what mregparm was set to in the old 5973 // toolchain 5974 RegParmMax = 4; 5975 5976 // Set the default CPU to V11 5977 CPU = CK_V11; 5978 5979 // Temporary approach to make everything at least word-aligned and allow for 5980 // safely casting between pointers with different alignment requirements. 5981 // TODO: Remove this when there are no more cast align warnings on the 5982 // firmware. 5983 MinGlobalAlign = 32; 5984 } 5985 5986 void getTargetDefines(const LangOptions &Opts, 5987 MacroBuilder &Builder) const override { 5988 // Define __lanai__ when building for target lanai. 5989 Builder.defineMacro("__lanai__"); 5990 5991 // Set define for the CPU specified. 5992 switch (CPU) { 5993 case CK_V11: 5994 Builder.defineMacro("__LANAI_V11__"); 5995 break; 5996 case CK_NONE: 5997 llvm_unreachable("Unhandled target CPU"); 5998 } 5999 } 6000 6001 bool setCPU(const std::string &Name) override { 6002 CPU = llvm::StringSwitch<CPUKind>(Name) 6003 .Case("v11", CK_V11) 6004 .Default(CK_NONE); 6005 6006 return CPU != CK_NONE; 6007 } 6008 6009 bool hasFeature(StringRef Feature) const override { 6010 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6011 } 6012 6013 ArrayRef<const char *> getGCCRegNames() const override; 6014 6015 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6016 6017 BuiltinVaListKind getBuiltinVaListKind() const override { 6018 return TargetInfo::VoidPtrBuiltinVaList; 6019 } 6020 6021 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6022 6023 bool validateAsmConstraint(const char *&Name, 6024 TargetInfo::ConstraintInfo &info) const override { 6025 return false; 6026 } 6027 6028 const char *getClobbers() const override { return ""; } 6029 }; 6030 6031 const char *const LanaiTargetInfo::GCCRegNames[] = { 6032 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6033 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6034 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6035 6036 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6037 return llvm::makeArrayRef(GCCRegNames); 6038 } 6039 6040 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6041 {{"pc"}, "r2"}, 6042 {{"sp"}, "r4"}, 6043 {{"fp"}, "r5"}, 6044 {{"rv"}, "r8"}, 6045 {{"rr1"}, "r10"}, 6046 {{"rr2"}, "r11"}, 6047 {{"rca"}, "r15"}, 6048 }; 6049 6050 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6051 return llvm::makeArrayRef(GCCRegAliases); 6052 } 6053 6054 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6055 class SparcTargetInfo : public TargetInfo { 6056 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6057 static const char * const GCCRegNames[]; 6058 bool SoftFloat; 6059 public: 6060 SparcTargetInfo(const llvm::Triple &Triple) 6061 : TargetInfo(Triple), SoftFloat(false) {} 6062 6063 int getEHDataRegisterNumber(unsigned RegNo) const override { 6064 if (RegNo == 0) return 24; 6065 if (RegNo == 1) return 25; 6066 return -1; 6067 } 6068 6069 bool handleTargetFeatures(std::vector<std::string> &Features, 6070 DiagnosticsEngine &Diags) override { 6071 // The backend doesn't actually handle soft float yet, but in case someone 6072 // is using the support for the front end continue to support it. 6073 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6074 if (Feature != Features.end()) { 6075 SoftFloat = true; 6076 Features.erase(Feature); 6077 } 6078 return true; 6079 } 6080 void getTargetDefines(const LangOptions &Opts, 6081 MacroBuilder &Builder) const override { 6082 DefineStd(Builder, "sparc", Opts); 6083 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6084 6085 if (SoftFloat) 6086 Builder.defineMacro("SOFT_FLOAT", "1"); 6087 } 6088 6089 bool hasFeature(StringRef Feature) const override { 6090 return llvm::StringSwitch<bool>(Feature) 6091 .Case("softfloat", SoftFloat) 6092 .Case("sparc", true) 6093 .Default(false); 6094 } 6095 6096 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6097 // FIXME: Implement! 6098 return None; 6099 } 6100 BuiltinVaListKind getBuiltinVaListKind() const override { 6101 return TargetInfo::VoidPtrBuiltinVaList; 6102 } 6103 ArrayRef<const char *> getGCCRegNames() const override; 6104 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6105 bool validateAsmConstraint(const char *&Name, 6106 TargetInfo::ConstraintInfo &info) const override { 6107 // FIXME: Implement! 6108 switch (*Name) { 6109 case 'I': // Signed 13-bit constant 6110 case 'J': // Zero 6111 case 'K': // 32-bit constant with the low 12 bits clear 6112 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6113 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6114 case 'N': // Same as 'K' but zext (required for SIMode) 6115 case 'O': // The constant 4096 6116 return true; 6117 } 6118 return false; 6119 } 6120 const char *getClobbers() const override { 6121 // FIXME: Implement! 6122 return ""; 6123 } 6124 6125 // No Sparc V7 for now, the backend doesn't support it anyway. 6126 enum CPUKind { 6127 CK_GENERIC, 6128 CK_V8, 6129 CK_SUPERSPARC, 6130 CK_SPARCLITE, 6131 CK_F934, 6132 CK_HYPERSPARC, 6133 CK_SPARCLITE86X, 6134 CK_SPARCLET, 6135 CK_TSC701, 6136 CK_V9, 6137 CK_ULTRASPARC, 6138 CK_ULTRASPARC3, 6139 CK_NIAGARA, 6140 CK_NIAGARA2, 6141 CK_NIAGARA3, 6142 CK_NIAGARA4, 6143 CK_MYRIAD2_1, 6144 CK_MYRIAD2_2 6145 } CPU = CK_GENERIC; 6146 6147 enum CPUGeneration { 6148 CG_V8, 6149 CG_V9, 6150 }; 6151 6152 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6153 switch (Kind) { 6154 case CK_GENERIC: 6155 case CK_V8: 6156 case CK_SUPERSPARC: 6157 case CK_SPARCLITE: 6158 case CK_F934: 6159 case CK_HYPERSPARC: 6160 case CK_SPARCLITE86X: 6161 case CK_SPARCLET: 6162 case CK_TSC701: 6163 case CK_MYRIAD2_1: 6164 case CK_MYRIAD2_2: 6165 return CG_V8; 6166 case CK_V9: 6167 case CK_ULTRASPARC: 6168 case CK_ULTRASPARC3: 6169 case CK_NIAGARA: 6170 case CK_NIAGARA2: 6171 case CK_NIAGARA3: 6172 case CK_NIAGARA4: 6173 return CG_V9; 6174 } 6175 llvm_unreachable("Unexpected CPU kind"); 6176 } 6177 6178 CPUKind getCPUKind(StringRef Name) const { 6179 return llvm::StringSwitch<CPUKind>(Name) 6180 .Case("v8", CK_V8) 6181 .Case("supersparc", CK_SUPERSPARC) 6182 .Case("sparclite", CK_SPARCLITE) 6183 .Case("f934", CK_F934) 6184 .Case("hypersparc", CK_HYPERSPARC) 6185 .Case("sparclite86x", CK_SPARCLITE86X) 6186 .Case("sparclet", CK_SPARCLET) 6187 .Case("tsc701", CK_TSC701) 6188 .Case("v9", CK_V9) 6189 .Case("ultrasparc", CK_ULTRASPARC) 6190 .Case("ultrasparc3", CK_ULTRASPARC3) 6191 .Case("niagara", CK_NIAGARA) 6192 .Case("niagara2", CK_NIAGARA2) 6193 .Case("niagara3", CK_NIAGARA3) 6194 .Case("niagara4", CK_NIAGARA4) 6195 .Case("myriad2", CK_MYRIAD2_1) 6196 .Case("myriad2.1", CK_MYRIAD2_1) 6197 .Case("myriad2.2", CK_MYRIAD2_2) 6198 .Default(CK_GENERIC); 6199 } 6200 6201 bool setCPU(const std::string &Name) override { 6202 CPU = getCPUKind(Name); 6203 return CPU != CK_GENERIC; 6204 } 6205 }; 6206 6207 const char * const SparcTargetInfo::GCCRegNames[] = { 6208 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6209 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6210 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6211 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6212 }; 6213 6214 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6215 return llvm::makeArrayRef(GCCRegNames); 6216 } 6217 6218 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6219 { { "g0" }, "r0" }, 6220 { { "g1" }, "r1" }, 6221 { { "g2" }, "r2" }, 6222 { { "g3" }, "r3" }, 6223 { { "g4" }, "r4" }, 6224 { { "g5" }, "r5" }, 6225 { { "g6" }, "r6" }, 6226 { { "g7" }, "r7" }, 6227 { { "o0" }, "r8" }, 6228 { { "o1" }, "r9" }, 6229 { { "o2" }, "r10" }, 6230 { { "o3" }, "r11" }, 6231 { { "o4" }, "r12" }, 6232 { { "o5" }, "r13" }, 6233 { { "o6", "sp" }, "r14" }, 6234 { { "o7" }, "r15" }, 6235 { { "l0" }, "r16" }, 6236 { { "l1" }, "r17" }, 6237 { { "l2" }, "r18" }, 6238 { { "l3" }, "r19" }, 6239 { { "l4" }, "r20" }, 6240 { { "l5" }, "r21" }, 6241 { { "l6" }, "r22" }, 6242 { { "l7" }, "r23" }, 6243 { { "i0" }, "r24" }, 6244 { { "i1" }, "r25" }, 6245 { { "i2" }, "r26" }, 6246 { { "i3" }, "r27" }, 6247 { { "i4" }, "r28" }, 6248 { { "i5" }, "r29" }, 6249 { { "i6", "fp" }, "r30" }, 6250 { { "i7" }, "r31" }, 6251 }; 6252 6253 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6254 return llvm::makeArrayRef(GCCRegAliases); 6255 } 6256 6257 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6258 class SparcV8TargetInfo : public SparcTargetInfo { 6259 public: 6260 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 6261 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6262 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6263 switch (getTriple().getOS()) { 6264 default: 6265 SizeType = UnsignedInt; 6266 IntPtrType = SignedInt; 6267 PtrDiffType = SignedInt; 6268 break; 6269 case llvm::Triple::NetBSD: 6270 case llvm::Triple::OpenBSD: 6271 SizeType = UnsignedLong; 6272 IntPtrType = SignedLong; 6273 PtrDiffType = SignedLong; 6274 break; 6275 } 6276 } 6277 6278 void getTargetDefines(const LangOptions &Opts, 6279 MacroBuilder &Builder) const override { 6280 SparcTargetInfo::getTargetDefines(Opts, Builder); 6281 switch (getCPUGeneration(CPU)) { 6282 case CG_V8: 6283 Builder.defineMacro("__sparcv8"); 6284 if (getTriple().getOS() != llvm::Triple::Solaris) 6285 Builder.defineMacro("__sparcv8__"); 6286 break; 6287 case CG_V9: 6288 Builder.defineMacro("__sparcv9"); 6289 if (getTriple().getOS() != llvm::Triple::Solaris) { 6290 Builder.defineMacro("__sparcv9__"); 6291 Builder.defineMacro("__sparc_v9__"); 6292 } 6293 break; 6294 } 6295 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6296 switch (CPU) { 6297 case CK_MYRIAD2_1: 6298 Builder.defineMacro("__myriad2", "1"); 6299 Builder.defineMacro("__myriad2__", "1"); 6300 break; 6301 case CK_MYRIAD2_2: 6302 Builder.defineMacro("__myriad2", "2"); 6303 Builder.defineMacro("__myriad2__", "2"); 6304 break; 6305 default: 6306 break; 6307 } 6308 } 6309 } 6310 }; 6311 6312 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6313 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6314 public: 6315 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 6316 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6317 BigEndian = false; 6318 } 6319 }; 6320 6321 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6322 class SparcV9TargetInfo : public SparcTargetInfo { 6323 public: 6324 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 6325 // FIXME: Support Sparc quad-precision long double? 6326 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6327 // This is an LP64 platform. 6328 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6329 6330 // OpenBSD uses long long for int64_t and intmax_t. 6331 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6332 IntMaxType = SignedLongLong; 6333 else 6334 IntMaxType = SignedLong; 6335 Int64Type = IntMaxType; 6336 6337 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6338 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6339 LongDoubleWidth = 128; 6340 LongDoubleAlign = 128; 6341 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6342 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6343 } 6344 6345 void getTargetDefines(const LangOptions &Opts, 6346 MacroBuilder &Builder) const override { 6347 SparcTargetInfo::getTargetDefines(Opts, Builder); 6348 Builder.defineMacro("__sparcv9"); 6349 Builder.defineMacro("__arch64__"); 6350 // Solaris doesn't need these variants, but the BSDs do. 6351 if (getTriple().getOS() != llvm::Triple::Solaris) { 6352 Builder.defineMacro("__sparc64__"); 6353 Builder.defineMacro("__sparc_v9__"); 6354 Builder.defineMacro("__sparcv9__"); 6355 } 6356 } 6357 6358 bool setCPU(const std::string &Name) override { 6359 if (!SparcTargetInfo::setCPU(Name)) 6360 return false; 6361 return getCPUGeneration(CPU) == CG_V9; 6362 } 6363 }; 6364 6365 class SystemZTargetInfo : public TargetInfo { 6366 static const Builtin::Info BuiltinInfo[]; 6367 static const char *const GCCRegNames[]; 6368 std::string CPU; 6369 bool HasTransactionalExecution; 6370 bool HasVector; 6371 6372 public: 6373 SystemZTargetInfo(const llvm::Triple &Triple) 6374 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6375 HasVector(false) { 6376 IntMaxType = SignedLong; 6377 Int64Type = SignedLong; 6378 TLSSupported = true; 6379 IntWidth = IntAlign = 32; 6380 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6381 PointerWidth = PointerAlign = 64; 6382 LongDoubleWidth = 128; 6383 LongDoubleAlign = 64; 6384 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6385 DefaultAlignForAttributeAligned = 64; 6386 MinGlobalAlign = 16; 6387 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 6388 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6389 } 6390 void getTargetDefines(const LangOptions &Opts, 6391 MacroBuilder &Builder) const override { 6392 Builder.defineMacro("__s390__"); 6393 Builder.defineMacro("__s390x__"); 6394 Builder.defineMacro("__zarch__"); 6395 Builder.defineMacro("__LONG_DOUBLE_128__"); 6396 6397 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6398 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6399 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6400 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6401 6402 if (HasTransactionalExecution) 6403 Builder.defineMacro("__HTM__"); 6404 if (Opts.ZVector) 6405 Builder.defineMacro("__VEC__", "10301"); 6406 } 6407 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6408 return llvm::makeArrayRef(BuiltinInfo, 6409 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6410 } 6411 6412 ArrayRef<const char *> getGCCRegNames() const override; 6413 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6414 // No aliases. 6415 return None; 6416 } 6417 bool validateAsmConstraint(const char *&Name, 6418 TargetInfo::ConstraintInfo &info) const override; 6419 const char *getClobbers() const override { 6420 // FIXME: Is this really right? 6421 return ""; 6422 } 6423 BuiltinVaListKind getBuiltinVaListKind() const override { 6424 return TargetInfo::SystemZBuiltinVaList; 6425 } 6426 bool setCPU(const std::string &Name) override { 6427 CPU = Name; 6428 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6429 .Case("z10", true) 6430 .Case("z196", true) 6431 .Case("zEC12", true) 6432 .Case("z13", true) 6433 .Default(false); 6434 6435 return CPUKnown; 6436 } 6437 bool 6438 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6439 StringRef CPU, 6440 const std::vector<std::string> &FeaturesVec) const override { 6441 if (CPU == "zEC12") 6442 Features["transactional-execution"] = true; 6443 if (CPU == "z13") { 6444 Features["transactional-execution"] = true; 6445 Features["vector"] = true; 6446 } 6447 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6448 } 6449 6450 bool handleTargetFeatures(std::vector<std::string> &Features, 6451 DiagnosticsEngine &Diags) override { 6452 HasTransactionalExecution = false; 6453 for (const auto &Feature : Features) { 6454 if (Feature == "+transactional-execution") 6455 HasTransactionalExecution = true; 6456 else if (Feature == "+vector") 6457 HasVector = true; 6458 } 6459 // If we use the vector ABI, vector types are 64-bit aligned. 6460 if (HasVector) { 6461 MaxVectorAlign = 64; 6462 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6463 "-v128:64-a:8:16-n32:64"); 6464 } 6465 return true; 6466 } 6467 6468 bool hasFeature(StringRef Feature) const override { 6469 return llvm::StringSwitch<bool>(Feature) 6470 .Case("systemz", true) 6471 .Case("htm", HasTransactionalExecution) 6472 .Case("vx", HasVector) 6473 .Default(false); 6474 } 6475 6476 StringRef getABI() const override { 6477 if (HasVector) 6478 return "vector"; 6479 return ""; 6480 } 6481 6482 bool useFloat128ManglingForLongDouble() const override { 6483 return true; 6484 } 6485 }; 6486 6487 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6488 #define BUILTIN(ID, TYPE, ATTRS) \ 6489 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6490 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 6491 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 6492 #include "clang/Basic/BuiltinsSystemZ.def" 6493 }; 6494 6495 const char *const SystemZTargetInfo::GCCRegNames[] = { 6496 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6497 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6498 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6499 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6500 }; 6501 6502 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6503 return llvm::makeArrayRef(GCCRegNames); 6504 } 6505 6506 bool SystemZTargetInfo:: 6507 validateAsmConstraint(const char *&Name, 6508 TargetInfo::ConstraintInfo &Info) const { 6509 switch (*Name) { 6510 default: 6511 return false; 6512 6513 case 'a': // Address register 6514 case 'd': // Data register (equivalent to 'r') 6515 case 'f': // Floating-point register 6516 Info.setAllowsRegister(); 6517 return true; 6518 6519 case 'I': // Unsigned 8-bit constant 6520 case 'J': // Unsigned 12-bit constant 6521 case 'K': // Signed 16-bit constant 6522 case 'L': // Signed 20-bit displacement (on all targets we support) 6523 case 'M': // 0x7fffffff 6524 return true; 6525 6526 case 'Q': // Memory with base and unsigned 12-bit displacement 6527 case 'R': // Likewise, plus an index 6528 case 'S': // Memory with base and signed 20-bit displacement 6529 case 'T': // Likewise, plus an index 6530 Info.setAllowsMemory(); 6531 return true; 6532 } 6533 } 6534 6535 class MSP430TargetInfo : public TargetInfo { 6536 static const char *const GCCRegNames[]; 6537 6538 public: 6539 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6540 BigEndian = false; 6541 TLSSupported = false; 6542 IntWidth = 16; 6543 IntAlign = 16; 6544 LongWidth = 32; 6545 LongLongWidth = 64; 6546 LongAlign = LongLongAlign = 16; 6547 PointerWidth = 16; 6548 PointerAlign = 16; 6549 SuitableAlign = 16; 6550 SizeType = UnsignedInt; 6551 IntMaxType = SignedLongLong; 6552 IntPtrType = SignedInt; 6553 PtrDiffType = SignedInt; 6554 SigAtomicType = SignedLong; 6555 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 6556 } 6557 void getTargetDefines(const LangOptions &Opts, 6558 MacroBuilder &Builder) const override { 6559 Builder.defineMacro("MSP430"); 6560 Builder.defineMacro("__MSP430__"); 6561 // FIXME: defines for different 'flavours' of MCU 6562 } 6563 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6564 // FIXME: Implement. 6565 return None; 6566 } 6567 bool hasFeature(StringRef Feature) const override { 6568 return Feature == "msp430"; 6569 } 6570 ArrayRef<const char *> getGCCRegNames() const override; 6571 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6572 // No aliases. 6573 return None; 6574 } 6575 bool validateAsmConstraint(const char *&Name, 6576 TargetInfo::ConstraintInfo &info) const override { 6577 // FIXME: implement 6578 switch (*Name) { 6579 case 'K': // the constant 1 6580 case 'L': // constant -1^20 .. 1^19 6581 case 'M': // constant 1-4: 6582 return true; 6583 } 6584 // No target constraints for now. 6585 return false; 6586 } 6587 const char *getClobbers() const override { 6588 // FIXME: Is this really right? 6589 return ""; 6590 } 6591 BuiltinVaListKind getBuiltinVaListKind() const override { 6592 // FIXME: implement 6593 return TargetInfo::CharPtrBuiltinVaList; 6594 } 6595 }; 6596 6597 const char *const MSP430TargetInfo::GCCRegNames[] = { 6598 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6599 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6600 6601 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 6602 return llvm::makeArrayRef(GCCRegNames); 6603 } 6604 6605 // LLVM and Clang cannot be used directly to output native binaries for 6606 // target, but is used to compile C code to llvm bitcode with correct 6607 // type and alignment information. 6608 // 6609 // TCE uses the llvm bitcode as input and uses it for generating customized 6610 // target processor and program binary. TCE co-design environment is 6611 // publicly available in http://tce.cs.tut.fi 6612 6613 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6614 3, // opencl_global 6615 4, // opencl_local 6616 5, // opencl_constant 6617 // FIXME: generic has to be added to the target 6618 0, // opencl_generic 6619 0, // cuda_device 6620 0, // cuda_constant 6621 0 // cuda_shared 6622 }; 6623 6624 class TCETargetInfo : public TargetInfo { 6625 public: 6626 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6627 TLSSupported = false; 6628 IntWidth = 32; 6629 LongWidth = LongLongWidth = 32; 6630 PointerWidth = 32; 6631 IntAlign = 32; 6632 LongAlign = LongLongAlign = 32; 6633 PointerAlign = 32; 6634 SuitableAlign = 32; 6635 SizeType = UnsignedInt; 6636 IntMaxType = SignedLong; 6637 IntPtrType = SignedInt; 6638 PtrDiffType = SignedInt; 6639 FloatWidth = 32; 6640 FloatAlign = 32; 6641 DoubleWidth = 32; 6642 DoubleAlign = 32; 6643 LongDoubleWidth = 32; 6644 LongDoubleAlign = 32; 6645 FloatFormat = &llvm::APFloat::IEEEsingle; 6646 DoubleFormat = &llvm::APFloat::IEEEsingle; 6647 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6648 resetDataLayout("E-p:32:32-i8:8:32-i16:16:32-i64:32" 6649 "-f64:32-v64:32-v128:32-a:0:32-n32"); 6650 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6651 UseAddrSpaceMapMangling = true; 6652 } 6653 6654 void getTargetDefines(const LangOptions &Opts, 6655 MacroBuilder &Builder) const override { 6656 DefineStd(Builder, "tce", Opts); 6657 Builder.defineMacro("__TCE__"); 6658 Builder.defineMacro("__TCE_V1__"); 6659 } 6660 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 6661 6662 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6663 const char *getClobbers() const override { return ""; } 6664 BuiltinVaListKind getBuiltinVaListKind() const override { 6665 return TargetInfo::VoidPtrBuiltinVaList; 6666 } 6667 ArrayRef<const char *> getGCCRegNames() const override { return None; } 6668 bool validateAsmConstraint(const char *&Name, 6669 TargetInfo::ConstraintInfo &info) const override { 6670 return true; 6671 } 6672 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6673 return None; 6674 } 6675 }; 6676 6677 class BPFTargetInfo : public TargetInfo { 6678 public: 6679 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6680 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6681 SizeType = UnsignedLong; 6682 PtrDiffType = SignedLong; 6683 IntPtrType = SignedLong; 6684 IntMaxType = SignedLong; 6685 Int64Type = SignedLong; 6686 RegParmMax = 5; 6687 if (Triple.getArch() == llvm::Triple::bpfeb) { 6688 BigEndian = true; 6689 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 6690 } else { 6691 BigEndian = false; 6692 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 6693 } 6694 MaxAtomicPromoteWidth = 64; 6695 MaxAtomicInlineWidth = 64; 6696 TLSSupported = false; 6697 } 6698 void getTargetDefines(const LangOptions &Opts, 6699 MacroBuilder &Builder) const override { 6700 DefineStd(Builder, "bpf", Opts); 6701 Builder.defineMacro("__BPF__"); 6702 } 6703 bool hasFeature(StringRef Feature) const override { 6704 return Feature == "bpf"; 6705 } 6706 6707 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6708 const char *getClobbers() const override { 6709 return ""; 6710 } 6711 BuiltinVaListKind getBuiltinVaListKind() const override { 6712 return TargetInfo::VoidPtrBuiltinVaList; 6713 } 6714 ArrayRef<const char *> getGCCRegNames() const override { 6715 return None; 6716 } 6717 bool validateAsmConstraint(const char *&Name, 6718 TargetInfo::ConstraintInfo &info) const override { 6719 return true; 6720 } 6721 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6722 return None; 6723 } 6724 }; 6725 6726 class MipsTargetInfoBase : public TargetInfo { 6727 virtual void setDataLayout() = 0; 6728 6729 static const Builtin::Info BuiltinInfo[]; 6730 std::string CPU; 6731 bool IsMips16; 6732 bool IsMicromips; 6733 bool IsNan2008; 6734 bool IsSingleFloat; 6735 enum MipsFloatABI { 6736 HardFloat, SoftFloat 6737 } FloatABI; 6738 enum DspRevEnum { 6739 NoDSP, DSP1, DSP2 6740 } DspRev; 6741 bool HasMSA; 6742 6743 protected: 6744 bool HasFP64; 6745 std::string ABI; 6746 6747 public: 6748 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 6749 const std::string &CPUStr) 6750 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6751 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6752 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6753 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6754 } 6755 6756 bool isNaN2008Default() const { 6757 return CPU == "mips32r6" || CPU == "mips64r6"; 6758 } 6759 6760 bool isFP64Default() const { 6761 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6762 } 6763 6764 bool isNan2008() const override { 6765 return IsNan2008; 6766 } 6767 6768 StringRef getABI() const override { return ABI; } 6769 bool setCPU(const std::string &Name) override { 6770 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6771 getTriple().getArch() == llvm::Triple::mipsel; 6772 CPU = Name; 6773 return llvm::StringSwitch<bool>(Name) 6774 .Case("mips1", IsMips32) 6775 .Case("mips2", IsMips32) 6776 .Case("mips3", true) 6777 .Case("mips4", true) 6778 .Case("mips5", true) 6779 .Case("mips32", IsMips32) 6780 .Case("mips32r2", IsMips32) 6781 .Case("mips32r3", IsMips32) 6782 .Case("mips32r5", IsMips32) 6783 .Case("mips32r6", IsMips32) 6784 .Case("mips64", true) 6785 .Case("mips64r2", true) 6786 .Case("mips64r3", true) 6787 .Case("mips64r5", true) 6788 .Case("mips64r6", true) 6789 .Case("octeon", true) 6790 .Case("p5600", true) 6791 .Default(false); 6792 } 6793 const std::string& getCPU() const { return CPU; } 6794 bool 6795 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6796 StringRef CPU, 6797 const std::vector<std::string> &FeaturesVec) const override { 6798 if (CPU.empty()) 6799 CPU = getCPU(); 6800 if (CPU == "octeon") 6801 Features["mips64r2"] = Features["cnmips"] = true; 6802 else 6803 Features[CPU] = true; 6804 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6805 } 6806 6807 void getTargetDefines(const LangOptions &Opts, 6808 MacroBuilder &Builder) const override { 6809 Builder.defineMacro("__mips__"); 6810 Builder.defineMacro("_mips"); 6811 if (Opts.GNUMode) 6812 Builder.defineMacro("mips"); 6813 6814 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6815 6816 switch (FloatABI) { 6817 case HardFloat: 6818 Builder.defineMacro("__mips_hard_float", Twine(1)); 6819 break; 6820 case SoftFloat: 6821 Builder.defineMacro("__mips_soft_float", Twine(1)); 6822 break; 6823 } 6824 6825 if (IsSingleFloat) 6826 Builder.defineMacro("__mips_single_float", Twine(1)); 6827 6828 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6829 Builder.defineMacro("_MIPS_FPSET", 6830 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6831 6832 if (IsMips16) 6833 Builder.defineMacro("__mips16", Twine(1)); 6834 6835 if (IsMicromips) 6836 Builder.defineMacro("__mips_micromips", Twine(1)); 6837 6838 if (IsNan2008) 6839 Builder.defineMacro("__mips_nan2008", Twine(1)); 6840 6841 switch (DspRev) { 6842 default: 6843 break; 6844 case DSP1: 6845 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6846 Builder.defineMacro("__mips_dsp", Twine(1)); 6847 break; 6848 case DSP2: 6849 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6850 Builder.defineMacro("__mips_dspr2", Twine(1)); 6851 Builder.defineMacro("__mips_dsp", Twine(1)); 6852 break; 6853 } 6854 6855 if (HasMSA) 6856 Builder.defineMacro("__mips_msa", Twine(1)); 6857 6858 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6859 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6860 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6861 6862 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6863 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6864 6865 // These shouldn't be defined for MIPS-I but there's no need to check 6866 // for that since MIPS-I isn't supported. 6867 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6868 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6869 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6870 } 6871 6872 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6873 return llvm::makeArrayRef(BuiltinInfo, 6874 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 6875 } 6876 bool hasFeature(StringRef Feature) const override { 6877 return llvm::StringSwitch<bool>(Feature) 6878 .Case("mips", true) 6879 .Case("fp64", HasFP64) 6880 .Default(false); 6881 } 6882 BuiltinVaListKind getBuiltinVaListKind() const override { 6883 return TargetInfo::VoidPtrBuiltinVaList; 6884 } 6885 ArrayRef<const char *> getGCCRegNames() const override { 6886 static const char *const GCCRegNames[] = { 6887 // CPU register names 6888 // Must match second column of GCCRegAliases 6889 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6890 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6891 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6892 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6893 // Floating point register names 6894 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6895 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6896 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6897 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6898 // Hi/lo and condition register names 6899 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6900 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 6901 "$ac3hi","$ac3lo", 6902 // MSA register names 6903 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6904 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6905 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6906 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6907 // MSA control register names 6908 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6909 "$msarequest", "$msamap", "$msaunmap" 6910 }; 6911 return llvm::makeArrayRef(GCCRegNames); 6912 } 6913 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override = 0; 6914 bool validateAsmConstraint(const char *&Name, 6915 TargetInfo::ConstraintInfo &Info) const override { 6916 switch (*Name) { 6917 default: 6918 return false; 6919 case 'r': // CPU registers. 6920 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6921 case 'y': // Equivalent to "r", backward compatibility only. 6922 case 'f': // floating-point registers. 6923 case 'c': // $25 for indirect jumps 6924 case 'l': // lo register 6925 case 'x': // hilo register pair 6926 Info.setAllowsRegister(); 6927 return true; 6928 case 'I': // Signed 16-bit constant 6929 case 'J': // Integer 0 6930 case 'K': // Unsigned 16-bit constant 6931 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6932 case 'M': // Constants not loadable via lui, addiu, or ori 6933 case 'N': // Constant -1 to -65535 6934 case 'O': // A signed 15-bit constant 6935 case 'P': // A constant between 1 go 65535 6936 return true; 6937 case 'R': // An address that can be used in a non-macro load or store 6938 Info.setAllowsMemory(); 6939 return true; 6940 case 'Z': 6941 if (Name[1] == 'C') { // An address usable by ll, and sc. 6942 Info.setAllowsMemory(); 6943 Name++; // Skip over 'Z'. 6944 return true; 6945 } 6946 return false; 6947 } 6948 } 6949 6950 std::string convertConstraint(const char *&Constraint) const override { 6951 std::string R; 6952 switch (*Constraint) { 6953 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6954 if (Constraint[1] == 'C') { 6955 R = std::string("^") + std::string(Constraint, 2); 6956 Constraint++; 6957 return R; 6958 } 6959 break; 6960 } 6961 return TargetInfo::convertConstraint(Constraint); 6962 } 6963 6964 const char *getClobbers() const override { 6965 // In GCC, $1 is not widely used in generated code (it's used only in a few 6966 // specific situations), so there is no real need for users to add it to 6967 // the clobbers list if they want to use it in their inline assembly code. 6968 // 6969 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6970 // code generation, so using it in inline assembly without adding it to the 6971 // clobbers list can cause conflicts between the inline assembly code and 6972 // the surrounding generated code. 6973 // 6974 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6975 // operands, which will conflict with the ".set at" assembler option (which 6976 // we use only for inline assembly, in order to maintain compatibility with 6977 // GCC) and will also conflict with the user's usage of $1. 6978 // 6979 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6980 // register for generated code is to automatically clobber $1 for all inline 6981 // assembly code. 6982 // 6983 // FIXME: We should automatically clobber $1 only for inline assembly code 6984 // which actually uses it. This would allow LLVM to use $1 for inline 6985 // assembly operands if the user's assembly code doesn't use it. 6986 return "~{$1}"; 6987 } 6988 6989 bool handleTargetFeatures(std::vector<std::string> &Features, 6990 DiagnosticsEngine &Diags) override { 6991 IsMips16 = false; 6992 IsMicromips = false; 6993 IsNan2008 = isNaN2008Default(); 6994 IsSingleFloat = false; 6995 FloatABI = HardFloat; 6996 DspRev = NoDSP; 6997 HasFP64 = isFP64Default(); 6998 6999 for (const auto &Feature : Features) { 7000 if (Feature == "+single-float") 7001 IsSingleFloat = true; 7002 else if (Feature == "+soft-float") 7003 FloatABI = SoftFloat; 7004 else if (Feature == "+mips16") 7005 IsMips16 = true; 7006 else if (Feature == "+micromips") 7007 IsMicromips = true; 7008 else if (Feature == "+dsp") 7009 DspRev = std::max(DspRev, DSP1); 7010 else if (Feature == "+dspr2") 7011 DspRev = std::max(DspRev, DSP2); 7012 else if (Feature == "+msa") 7013 HasMSA = true; 7014 else if (Feature == "+fp64") 7015 HasFP64 = true; 7016 else if (Feature == "-fp64") 7017 HasFP64 = false; 7018 else if (Feature == "+nan2008") 7019 IsNan2008 = true; 7020 else if (Feature == "-nan2008") 7021 IsNan2008 = false; 7022 } 7023 7024 setDataLayout(); 7025 7026 return true; 7027 } 7028 7029 int getEHDataRegisterNumber(unsigned RegNo) const override { 7030 if (RegNo == 0) return 4; 7031 if (RegNo == 1) return 5; 7032 return -1; 7033 } 7034 7035 bool isCLZForZeroUndef() const override { return false; } 7036 }; 7037 7038 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 7039 #define BUILTIN(ID, TYPE, ATTRS) \ 7040 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7041 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7042 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7043 #include "clang/Basic/BuiltinsMips.def" 7044 }; 7045 7046 class Mips32TargetInfoBase : public MipsTargetInfoBase { 7047 public: 7048 Mips32TargetInfoBase(const llvm::Triple &Triple) 7049 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 7050 SizeType = UnsignedInt; 7051 PtrDiffType = SignedInt; 7052 Int64Type = SignedLongLong; 7053 IntMaxType = Int64Type; 7054 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7055 } 7056 bool setABI(const std::string &Name) override { 7057 if (Name == "o32" || Name == "eabi") { 7058 ABI = Name; 7059 return true; 7060 } 7061 return false; 7062 } 7063 void getTargetDefines(const LangOptions &Opts, 7064 MacroBuilder &Builder) const override { 7065 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 7066 7067 Builder.defineMacro("__mips", "32"); 7068 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7069 7070 const std::string& CPUStr = getCPU(); 7071 if (CPUStr == "mips32") 7072 Builder.defineMacro("__mips_isa_rev", "1"); 7073 else if (CPUStr == "mips32r2") 7074 Builder.defineMacro("__mips_isa_rev", "2"); 7075 else if (CPUStr == "mips32r3") 7076 Builder.defineMacro("__mips_isa_rev", "3"); 7077 else if (CPUStr == "mips32r5") 7078 Builder.defineMacro("__mips_isa_rev", "5"); 7079 else if (CPUStr == "mips32r6") 7080 Builder.defineMacro("__mips_isa_rev", "6"); 7081 7082 if (ABI == "o32") { 7083 Builder.defineMacro("__mips_o32"); 7084 Builder.defineMacro("_ABIO32", "1"); 7085 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7086 } 7087 else if (ABI == "eabi") 7088 Builder.defineMacro("__mips_eabi"); 7089 else 7090 llvm_unreachable("Invalid ABI for Mips32."); 7091 } 7092 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7093 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 7094 { { "at" }, "$1" }, 7095 { { "v0" }, "$2" }, 7096 { { "v1" }, "$3" }, 7097 { { "a0" }, "$4" }, 7098 { { "a1" }, "$5" }, 7099 { { "a2" }, "$6" }, 7100 { { "a3" }, "$7" }, 7101 { { "t0" }, "$8" }, 7102 { { "t1" }, "$9" }, 7103 { { "t2" }, "$10" }, 7104 { { "t3" }, "$11" }, 7105 { { "t4" }, "$12" }, 7106 { { "t5" }, "$13" }, 7107 { { "t6" }, "$14" }, 7108 { { "t7" }, "$15" }, 7109 { { "s0" }, "$16" }, 7110 { { "s1" }, "$17" }, 7111 { { "s2" }, "$18" }, 7112 { { "s3" }, "$19" }, 7113 { { "s4" }, "$20" }, 7114 { { "s5" }, "$21" }, 7115 { { "s6" }, "$22" }, 7116 { { "s7" }, "$23" }, 7117 { { "t8" }, "$24" }, 7118 { { "t9" }, "$25" }, 7119 { { "k0" }, "$26" }, 7120 { { "k1" }, "$27" }, 7121 { { "gp" }, "$28" }, 7122 { { "sp","$sp" }, "$29" }, 7123 { { "fp","$fp" }, "$30" }, 7124 { { "ra" }, "$31" } 7125 }; 7126 return llvm::makeArrayRef(GCCRegAliases); 7127 } 7128 }; 7129 7130 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 7131 void setDataLayout() override { 7132 resetDataLayout("E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"); 7133 } 7134 7135 public: 7136 Mips32EBTargetInfo(const llvm::Triple &Triple) 7137 : Mips32TargetInfoBase(Triple) { 7138 } 7139 void getTargetDefines(const LangOptions &Opts, 7140 MacroBuilder &Builder) const override { 7141 DefineStd(Builder, "MIPSEB", Opts); 7142 Builder.defineMacro("_MIPSEB"); 7143 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 7144 } 7145 }; 7146 7147 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 7148 void setDataLayout() override { 7149 resetDataLayout("e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"); 7150 } 7151 7152 public: 7153 Mips32ELTargetInfo(const llvm::Triple &Triple) 7154 : Mips32TargetInfoBase(Triple) { 7155 BigEndian = false; 7156 } 7157 void getTargetDefines(const LangOptions &Opts, 7158 MacroBuilder &Builder) const override { 7159 DefineStd(Builder, "MIPSEL", Opts); 7160 Builder.defineMacro("_MIPSEL"); 7161 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 7162 } 7163 }; 7164 7165 class Mips64TargetInfoBase : public MipsTargetInfoBase { 7166 public: 7167 Mips64TargetInfoBase(const llvm::Triple &Triple) 7168 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 7169 LongDoubleWidth = LongDoubleAlign = 128; 7170 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7171 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7172 LongDoubleWidth = LongDoubleAlign = 64; 7173 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7174 } 7175 setN64ABITypes(); 7176 SuitableAlign = 128; 7177 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7178 } 7179 7180 void setN64ABITypes() { 7181 LongWidth = LongAlign = 64; 7182 PointerWidth = PointerAlign = 64; 7183 SizeType = UnsignedLong; 7184 PtrDiffType = SignedLong; 7185 Int64Type = SignedLong; 7186 IntMaxType = Int64Type; 7187 } 7188 7189 void setN32ABITypes() { 7190 LongWidth = LongAlign = 32; 7191 PointerWidth = PointerAlign = 32; 7192 SizeType = UnsignedInt; 7193 PtrDiffType = SignedInt; 7194 Int64Type = SignedLongLong; 7195 IntMaxType = Int64Type; 7196 } 7197 7198 bool setABI(const std::string &Name) override { 7199 if (Name == "n32") { 7200 setN32ABITypes(); 7201 ABI = Name; 7202 return true; 7203 } 7204 if (Name == "n64") { 7205 setN64ABITypes(); 7206 ABI = Name; 7207 return true; 7208 } 7209 return false; 7210 } 7211 7212 void getTargetDefines(const LangOptions &Opts, 7213 MacroBuilder &Builder) const override { 7214 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 7215 7216 Builder.defineMacro("__mips", "64"); 7217 Builder.defineMacro("__mips64"); 7218 Builder.defineMacro("__mips64__"); 7219 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7220 7221 const std::string& CPUStr = getCPU(); 7222 if (CPUStr == "mips64") 7223 Builder.defineMacro("__mips_isa_rev", "1"); 7224 else if (CPUStr == "mips64r2") 7225 Builder.defineMacro("__mips_isa_rev", "2"); 7226 else if (CPUStr == "mips64r3") 7227 Builder.defineMacro("__mips_isa_rev", "3"); 7228 else if (CPUStr == "mips64r5") 7229 Builder.defineMacro("__mips_isa_rev", "5"); 7230 else if (CPUStr == "mips64r6") 7231 Builder.defineMacro("__mips_isa_rev", "6"); 7232 7233 if (ABI == "n32") { 7234 Builder.defineMacro("__mips_n32"); 7235 Builder.defineMacro("_ABIN32", "2"); 7236 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7237 } 7238 else if (ABI == "n64") { 7239 Builder.defineMacro("__mips_n64"); 7240 Builder.defineMacro("_ABI64", "3"); 7241 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7242 } 7243 else 7244 llvm_unreachable("Invalid ABI for Mips64."); 7245 7246 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7247 } 7248 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7249 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 7250 { { "at" }, "$1" }, 7251 { { "v0" }, "$2" }, 7252 { { "v1" }, "$3" }, 7253 { { "a0" }, "$4" }, 7254 { { "a1" }, "$5" }, 7255 { { "a2" }, "$6" }, 7256 { { "a3" }, "$7" }, 7257 { { "a4" }, "$8" }, 7258 { { "a5" }, "$9" }, 7259 { { "a6" }, "$10" }, 7260 { { "a7" }, "$11" }, 7261 { { "t0" }, "$12" }, 7262 { { "t1" }, "$13" }, 7263 { { "t2" }, "$14" }, 7264 { { "t3" }, "$15" }, 7265 { { "s0" }, "$16" }, 7266 { { "s1" }, "$17" }, 7267 { { "s2" }, "$18" }, 7268 { { "s3" }, "$19" }, 7269 { { "s4" }, "$20" }, 7270 { { "s5" }, "$21" }, 7271 { { "s6" }, "$22" }, 7272 { { "s7" }, "$23" }, 7273 { { "t8" }, "$24" }, 7274 { { "t9" }, "$25" }, 7275 { { "k0" }, "$26" }, 7276 { { "k1" }, "$27" }, 7277 { { "gp" }, "$28" }, 7278 { { "sp","$sp" }, "$29" }, 7279 { { "fp","$fp" }, "$30" }, 7280 { { "ra" }, "$31" } 7281 }; 7282 return llvm::makeArrayRef(GCCRegAliases); 7283 } 7284 7285 bool hasInt128Type() const override { return true; } 7286 }; 7287 7288 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 7289 void setDataLayout() override { 7290 if (ABI == "n32") 7291 resetDataLayout("E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7292 else 7293 resetDataLayout("E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7294 } 7295 7296 public: 7297 Mips64EBTargetInfo(const llvm::Triple &Triple) 7298 : Mips64TargetInfoBase(Triple) {} 7299 void getTargetDefines(const LangOptions &Opts, 7300 MacroBuilder &Builder) const override { 7301 DefineStd(Builder, "MIPSEB", Opts); 7302 Builder.defineMacro("_MIPSEB"); 7303 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7304 } 7305 }; 7306 7307 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 7308 void setDataLayout() override { 7309 if (ABI == "n32") 7310 resetDataLayout("e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7311 else 7312 resetDataLayout("e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7313 } 7314 public: 7315 Mips64ELTargetInfo(const llvm::Triple &Triple) 7316 : Mips64TargetInfoBase(Triple) { 7317 // Default ABI is n64. 7318 BigEndian = false; 7319 } 7320 void getTargetDefines(const LangOptions &Opts, 7321 MacroBuilder &Builder) const override { 7322 DefineStd(Builder, "MIPSEL", Opts); 7323 Builder.defineMacro("_MIPSEL"); 7324 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7325 } 7326 }; 7327 7328 class PNaClTargetInfo : public TargetInfo { 7329 public: 7330 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7331 BigEndian = false; 7332 this->LongAlign = 32; 7333 this->LongWidth = 32; 7334 this->PointerAlign = 32; 7335 this->PointerWidth = 32; 7336 this->IntMaxType = TargetInfo::SignedLongLong; 7337 this->Int64Type = TargetInfo::SignedLongLong; 7338 this->DoubleAlign = 64; 7339 this->LongDoubleWidth = 64; 7340 this->LongDoubleAlign = 64; 7341 this->SizeType = TargetInfo::UnsignedInt; 7342 this->PtrDiffType = TargetInfo::SignedInt; 7343 this->IntPtrType = TargetInfo::SignedInt; 7344 this->RegParmMax = 0; // Disallow regparm 7345 } 7346 7347 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7348 Builder.defineMacro("__le32__"); 7349 Builder.defineMacro("__pnacl__"); 7350 } 7351 void getTargetDefines(const LangOptions &Opts, 7352 MacroBuilder &Builder) const override { 7353 getArchDefines(Opts, Builder); 7354 } 7355 bool hasFeature(StringRef Feature) const override { 7356 return Feature == "pnacl"; 7357 } 7358 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7359 BuiltinVaListKind getBuiltinVaListKind() const override { 7360 return TargetInfo::PNaClABIBuiltinVaList; 7361 } 7362 ArrayRef<const char *> getGCCRegNames() const override; 7363 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7364 bool validateAsmConstraint(const char *&Name, 7365 TargetInfo::ConstraintInfo &Info) const override { 7366 return false; 7367 } 7368 7369 const char *getClobbers() const override { 7370 return ""; 7371 } 7372 }; 7373 7374 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7375 return None; 7376 } 7377 7378 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7379 return None; 7380 } 7381 7382 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7383 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 7384 public: 7385 NaClMips32ELTargetInfo(const llvm::Triple &Triple) : 7386 Mips32ELTargetInfo(Triple) { 7387 } 7388 7389 BuiltinVaListKind getBuiltinVaListKind() const override { 7390 return TargetInfo::PNaClABIBuiltinVaList; 7391 } 7392 }; 7393 7394 class Le64TargetInfo : public TargetInfo { 7395 static const Builtin::Info BuiltinInfo[]; 7396 7397 public: 7398 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7399 BigEndian = false; 7400 NoAsmVariants = true; 7401 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7402 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7403 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 7404 } 7405 7406 void getTargetDefines(const LangOptions &Opts, 7407 MacroBuilder &Builder) const override { 7408 DefineStd(Builder, "unix", Opts); 7409 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7410 Builder.defineMacro("__ELF__"); 7411 } 7412 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7413 return llvm::makeArrayRef(BuiltinInfo, 7414 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7415 } 7416 BuiltinVaListKind getBuiltinVaListKind() const override { 7417 return TargetInfo::PNaClABIBuiltinVaList; 7418 } 7419 const char *getClobbers() const override { return ""; } 7420 ArrayRef<const char *> getGCCRegNames() const override { 7421 return None; 7422 } 7423 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7424 return None; 7425 } 7426 bool validateAsmConstraint(const char *&Name, 7427 TargetInfo::ConstraintInfo &Info) const override { 7428 return false; 7429 } 7430 7431 bool hasProtectedVisibility() const override { return false; } 7432 }; 7433 7434 class WebAssemblyTargetInfo : public TargetInfo { 7435 static const Builtin::Info BuiltinInfo[]; 7436 7437 enum SIMDEnum { 7438 NoSIMD, 7439 SIMD128, 7440 } SIMDLevel; 7441 7442 public: 7443 explicit WebAssemblyTargetInfo(const llvm::Triple &T) 7444 : TargetInfo(T), SIMDLevel(NoSIMD) { 7445 BigEndian = false; 7446 NoAsmVariants = true; 7447 SuitableAlign = 128; 7448 LargeArrayMinWidth = 128; 7449 LargeArrayAlign = 128; 7450 SimdDefaultAlign = 128; 7451 SigAtomicType = SignedLong; 7452 LongDoubleWidth = LongDoubleAlign = 128; 7453 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7454 } 7455 7456 protected: 7457 void getTargetDefines(const LangOptions &Opts, 7458 MacroBuilder &Builder) const override { 7459 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7460 if (SIMDLevel >= SIMD128) 7461 Builder.defineMacro("__wasm_simd128__"); 7462 } 7463 7464 private: 7465 bool 7466 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7467 StringRef CPU, 7468 const std::vector<std::string> &FeaturesVec) const override { 7469 if (CPU == "bleeding-edge") 7470 Features["simd128"] = true; 7471 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7472 } 7473 bool hasFeature(StringRef Feature) const final { 7474 return llvm::StringSwitch<bool>(Feature) 7475 .Case("simd128", SIMDLevel >= SIMD128) 7476 .Default(false); 7477 } 7478 bool handleTargetFeatures(std::vector<std::string> &Features, 7479 DiagnosticsEngine &Diags) final { 7480 for (const auto &Feature : Features) { 7481 if (Feature == "+simd128") { 7482 SIMDLevel = std::max(SIMDLevel, SIMD128); 7483 continue; 7484 } 7485 if (Feature == "-simd128") { 7486 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7487 continue; 7488 } 7489 7490 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7491 << "-target-feature"; 7492 return false; 7493 } 7494 return true; 7495 } 7496 bool setCPU(const std::string &Name) final { 7497 return llvm::StringSwitch<bool>(Name) 7498 .Case("mvp", true) 7499 .Case("bleeding-edge", true) 7500 .Case("generic", true) 7501 .Default(false); 7502 } 7503 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7504 return llvm::makeArrayRef(BuiltinInfo, 7505 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7506 } 7507 BuiltinVaListKind getBuiltinVaListKind() const final { 7508 return VoidPtrBuiltinVaList; 7509 } 7510 ArrayRef<const char *> getGCCRegNames() const final { 7511 return None; 7512 } 7513 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7514 return None; 7515 } 7516 bool 7517 validateAsmConstraint(const char *&Name, 7518 TargetInfo::ConstraintInfo &Info) const final { 7519 return false; 7520 } 7521 const char *getClobbers() const final { return ""; } 7522 bool isCLZForZeroUndef() const final { return false; } 7523 bool hasInt128Type() const final { return true; } 7524 IntType getIntTypeByWidth(unsigned BitWidth, 7525 bool IsSigned) const final { 7526 // WebAssembly prefers long long for explicitly 64-bit integers. 7527 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7528 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7529 } 7530 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7531 bool IsSigned) const final { 7532 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7533 return BitWidth == 64 7534 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7535 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7536 } 7537 }; 7538 7539 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7540 #define BUILTIN(ID, TYPE, ATTRS) \ 7541 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7542 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7543 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7544 #include "clang/Basic/BuiltinsWebAssembly.def" 7545 }; 7546 7547 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7548 public: 7549 explicit WebAssembly32TargetInfo(const llvm::Triple &T) 7550 : WebAssemblyTargetInfo(T) { 7551 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7552 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 7553 } 7554 7555 protected: 7556 void getTargetDefines(const LangOptions &Opts, 7557 MacroBuilder &Builder) const override { 7558 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7559 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7560 } 7561 }; 7562 7563 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7564 public: 7565 explicit WebAssembly64TargetInfo(const llvm::Triple &T) 7566 : WebAssemblyTargetInfo(T) { 7567 LongAlign = LongWidth = 64; 7568 PointerAlign = PointerWidth = 64; 7569 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7570 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7571 } 7572 7573 protected: 7574 void getTargetDefines(const LangOptions &Opts, 7575 MacroBuilder &Builder) const override { 7576 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7577 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7578 } 7579 }; 7580 7581 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7582 #define BUILTIN(ID, TYPE, ATTRS) \ 7583 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7584 #include "clang/Basic/BuiltinsLe64.def" 7585 }; 7586 7587 static const unsigned SPIRAddrSpaceMap[] = { 7588 1, // opencl_global 7589 3, // opencl_local 7590 2, // opencl_constant 7591 4, // opencl_generic 7592 0, // cuda_device 7593 0, // cuda_constant 7594 0 // cuda_shared 7595 }; 7596 class SPIRTargetInfo : public TargetInfo { 7597 public: 7598 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7599 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7600 "SPIR target must use unknown OS"); 7601 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7602 "SPIR target must use unknown environment type"); 7603 BigEndian = false; 7604 TLSSupported = false; 7605 LongWidth = LongAlign = 64; 7606 AddrSpaceMap = &SPIRAddrSpaceMap; 7607 UseAddrSpaceMapMangling = true; 7608 // Define available target features 7609 // These must be defined in sorted order! 7610 NoAsmVariants = true; 7611 } 7612 void getTargetDefines(const LangOptions &Opts, 7613 MacroBuilder &Builder) const override { 7614 DefineStd(Builder, "SPIR", Opts); 7615 } 7616 bool hasFeature(StringRef Feature) const override { 7617 return Feature == "spir"; 7618 } 7619 7620 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7621 const char *getClobbers() const override { return ""; } 7622 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7623 bool validateAsmConstraint(const char *&Name, 7624 TargetInfo::ConstraintInfo &info) const override { 7625 return true; 7626 } 7627 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7628 return None; 7629 } 7630 BuiltinVaListKind getBuiltinVaListKind() const override { 7631 return TargetInfo::VoidPtrBuiltinVaList; 7632 } 7633 7634 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7635 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK 7636 : CCCR_Warning; 7637 } 7638 7639 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7640 return CC_SpirFunction; 7641 } 7642 }; 7643 7644 class SPIR32TargetInfo : public SPIRTargetInfo { 7645 public: 7646 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7647 PointerWidth = PointerAlign = 32; 7648 SizeType = TargetInfo::UnsignedInt; 7649 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7650 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7651 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7652 } 7653 void getTargetDefines(const LangOptions &Opts, 7654 MacroBuilder &Builder) const override { 7655 DefineStd(Builder, "SPIR32", Opts); 7656 } 7657 }; 7658 7659 class SPIR64TargetInfo : public SPIRTargetInfo { 7660 public: 7661 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7662 PointerWidth = PointerAlign = 64; 7663 SizeType = TargetInfo::UnsignedLong; 7664 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7665 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7666 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7667 } 7668 void getTargetDefines(const LangOptions &Opts, 7669 MacroBuilder &Builder) const override { 7670 DefineStd(Builder, "SPIR64", Opts); 7671 } 7672 }; 7673 7674 class XCoreTargetInfo : public TargetInfo { 7675 static const Builtin::Info BuiltinInfo[]; 7676 public: 7677 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7678 BigEndian = false; 7679 NoAsmVariants = true; 7680 LongLongAlign = 32; 7681 SuitableAlign = 32; 7682 DoubleAlign = LongDoubleAlign = 32; 7683 SizeType = UnsignedInt; 7684 PtrDiffType = SignedInt; 7685 IntPtrType = SignedInt; 7686 WCharType = UnsignedChar; 7687 WIntType = UnsignedInt; 7688 UseZeroLengthBitfieldAlignment = true; 7689 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7690 "-f64:32-a:0:32-n32"); 7691 } 7692 void getTargetDefines(const LangOptions &Opts, 7693 MacroBuilder &Builder) const override { 7694 Builder.defineMacro("__XS1B__"); 7695 } 7696 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7697 return llvm::makeArrayRef(BuiltinInfo, 7698 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 7699 } 7700 BuiltinVaListKind getBuiltinVaListKind() const override { 7701 return TargetInfo::VoidPtrBuiltinVaList; 7702 } 7703 const char *getClobbers() const override { 7704 return ""; 7705 } 7706 ArrayRef<const char *> getGCCRegNames() const override { 7707 static const char * const GCCRegNames[] = { 7708 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7709 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 7710 }; 7711 return llvm::makeArrayRef(GCCRegNames); 7712 } 7713 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7714 return None; 7715 } 7716 bool validateAsmConstraint(const char *&Name, 7717 TargetInfo::ConstraintInfo &Info) const override { 7718 return false; 7719 } 7720 int getEHDataRegisterNumber(unsigned RegNo) const override { 7721 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7722 return (RegNo < 2)? RegNo : -1; 7723 } 7724 bool allowsLargerPreferedTypeAlignment() const override { 7725 return false; 7726 } 7727 }; 7728 7729 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7730 #define BUILTIN(ID, TYPE, ATTRS) \ 7731 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7732 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7733 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7734 #include "clang/Basic/BuiltinsXCore.def" 7735 }; 7736 7737 // x86_32 Android target 7738 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7739 public: 7740 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 7741 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 7742 SuitableAlign = 32; 7743 LongDoubleWidth = 64; 7744 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7745 } 7746 }; 7747 7748 // x86_64 Android target 7749 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7750 public: 7751 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 7752 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 7753 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7754 } 7755 7756 bool useFloat128ManglingForLongDouble() const override { 7757 return true; 7758 } 7759 }; 7760 } // end anonymous namespace 7761 7762 //===----------------------------------------------------------------------===// 7763 // Driver code 7764 //===----------------------------------------------------------------------===// 7765 7766 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 7767 llvm::Triple::OSType os = Triple.getOS(); 7768 7769 switch (Triple.getArch()) { 7770 default: 7771 return nullptr; 7772 7773 case llvm::Triple::xcore: 7774 return new XCoreTargetInfo(Triple); 7775 7776 case llvm::Triple::hexagon: 7777 return new HexagonTargetInfo(Triple); 7778 7779 case llvm::Triple::lanai: 7780 return new LanaiTargetInfo(Triple); 7781 7782 case llvm::Triple::aarch64: 7783 if (Triple.isOSDarwin()) 7784 return new DarwinAArch64TargetInfo(Triple); 7785 7786 switch (os) { 7787 case llvm::Triple::CloudABI: 7788 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple); 7789 case llvm::Triple::FreeBSD: 7790 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 7791 case llvm::Triple::Linux: 7792 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 7793 case llvm::Triple::NetBSD: 7794 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 7795 default: 7796 return new AArch64leTargetInfo(Triple); 7797 } 7798 7799 case llvm::Triple::aarch64_be: 7800 switch (os) { 7801 case llvm::Triple::FreeBSD: 7802 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 7803 case llvm::Triple::Linux: 7804 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 7805 case llvm::Triple::NetBSD: 7806 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 7807 default: 7808 return new AArch64beTargetInfo(Triple); 7809 } 7810 7811 case llvm::Triple::arm: 7812 case llvm::Triple::thumb: 7813 if (Triple.isOSBinFormatMachO()) 7814 return new DarwinARMTargetInfo(Triple); 7815 7816 switch (os) { 7817 case llvm::Triple::Linux: 7818 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 7819 case llvm::Triple::FreeBSD: 7820 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 7821 case llvm::Triple::NetBSD: 7822 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 7823 case llvm::Triple::OpenBSD: 7824 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 7825 case llvm::Triple::Bitrig: 7826 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 7827 case llvm::Triple::RTEMS: 7828 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 7829 case llvm::Triple::NaCl: 7830 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 7831 case llvm::Triple::Win32: 7832 switch (Triple.getEnvironment()) { 7833 case llvm::Triple::Cygnus: 7834 return new CygwinARMTargetInfo(Triple); 7835 case llvm::Triple::GNU: 7836 return new MinGWARMTargetInfo(Triple); 7837 case llvm::Triple::Itanium: 7838 return new ItaniumWindowsARMleTargetInfo(Triple); 7839 case llvm::Triple::MSVC: 7840 default: // Assume MSVC for unknown environments 7841 return new MicrosoftARMleTargetInfo(Triple); 7842 } 7843 default: 7844 return new ARMleTargetInfo(Triple); 7845 } 7846 7847 case llvm::Triple::armeb: 7848 case llvm::Triple::thumbeb: 7849 if (Triple.isOSDarwin()) 7850 return new DarwinARMTargetInfo(Triple); 7851 7852 switch (os) { 7853 case llvm::Triple::Linux: 7854 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 7855 case llvm::Triple::FreeBSD: 7856 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 7857 case llvm::Triple::NetBSD: 7858 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 7859 case llvm::Triple::OpenBSD: 7860 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 7861 case llvm::Triple::Bitrig: 7862 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 7863 case llvm::Triple::RTEMS: 7864 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 7865 case llvm::Triple::NaCl: 7866 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 7867 default: 7868 return new ARMbeTargetInfo(Triple); 7869 } 7870 7871 case llvm::Triple::bpfeb: 7872 case llvm::Triple::bpfel: 7873 return new BPFTargetInfo(Triple); 7874 7875 case llvm::Triple::msp430: 7876 return new MSP430TargetInfo(Triple); 7877 7878 case llvm::Triple::mips: 7879 switch (os) { 7880 case llvm::Triple::Linux: 7881 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 7882 case llvm::Triple::RTEMS: 7883 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 7884 case llvm::Triple::FreeBSD: 7885 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7886 case llvm::Triple::NetBSD: 7887 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7888 default: 7889 return new Mips32EBTargetInfo(Triple); 7890 } 7891 7892 case llvm::Triple::mipsel: 7893 switch (os) { 7894 case llvm::Triple::Linux: 7895 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 7896 case llvm::Triple::RTEMS: 7897 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 7898 case llvm::Triple::FreeBSD: 7899 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7900 case llvm::Triple::NetBSD: 7901 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7902 case llvm::Triple::NaCl: 7903 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple); 7904 default: 7905 return new Mips32ELTargetInfo(Triple); 7906 } 7907 7908 case llvm::Triple::mips64: 7909 switch (os) { 7910 case llvm::Triple::Linux: 7911 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 7912 case llvm::Triple::RTEMS: 7913 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 7914 case llvm::Triple::FreeBSD: 7915 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7916 case llvm::Triple::NetBSD: 7917 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7918 case llvm::Triple::OpenBSD: 7919 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7920 default: 7921 return new Mips64EBTargetInfo(Triple); 7922 } 7923 7924 case llvm::Triple::mips64el: 7925 switch (os) { 7926 case llvm::Triple::Linux: 7927 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 7928 case llvm::Triple::RTEMS: 7929 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 7930 case llvm::Triple::FreeBSD: 7931 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7932 case llvm::Triple::NetBSD: 7933 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7934 case llvm::Triple::OpenBSD: 7935 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7936 default: 7937 return new Mips64ELTargetInfo(Triple); 7938 } 7939 7940 case llvm::Triple::le32: 7941 switch (os) { 7942 case llvm::Triple::NaCl: 7943 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 7944 default: 7945 return nullptr; 7946 } 7947 7948 case llvm::Triple::le64: 7949 return new Le64TargetInfo(Triple); 7950 7951 case llvm::Triple::ppc: 7952 if (Triple.isOSDarwin()) 7953 return new DarwinPPC32TargetInfo(Triple); 7954 switch (os) { 7955 case llvm::Triple::Linux: 7956 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 7957 case llvm::Triple::FreeBSD: 7958 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 7959 case llvm::Triple::NetBSD: 7960 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 7961 case llvm::Triple::OpenBSD: 7962 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 7963 case llvm::Triple::RTEMS: 7964 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 7965 default: 7966 return new PPC32TargetInfo(Triple); 7967 } 7968 7969 case llvm::Triple::ppc64: 7970 if (Triple.isOSDarwin()) 7971 return new DarwinPPC64TargetInfo(Triple); 7972 switch (os) { 7973 case llvm::Triple::Linux: 7974 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7975 case llvm::Triple::Lv2: 7976 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 7977 case llvm::Triple::FreeBSD: 7978 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 7979 case llvm::Triple::NetBSD: 7980 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7981 default: 7982 return new PPC64TargetInfo(Triple); 7983 } 7984 7985 case llvm::Triple::ppc64le: 7986 switch (os) { 7987 case llvm::Triple::Linux: 7988 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7989 case llvm::Triple::NetBSD: 7990 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7991 default: 7992 return new PPC64TargetInfo(Triple); 7993 } 7994 7995 case llvm::Triple::nvptx: 7996 return new NVPTX32TargetInfo(Triple); 7997 case llvm::Triple::nvptx64: 7998 return new NVPTX64TargetInfo(Triple); 7999 8000 case llvm::Triple::amdgcn: 8001 case llvm::Triple::r600: 8002 return new AMDGPUTargetInfo(Triple); 8003 8004 case llvm::Triple::sparc: 8005 switch (os) { 8006 case llvm::Triple::Linux: 8007 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 8008 case llvm::Triple::Solaris: 8009 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple); 8010 case llvm::Triple::NetBSD: 8011 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 8012 case llvm::Triple::OpenBSD: 8013 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 8014 case llvm::Triple::RTEMS: 8015 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 8016 default: 8017 return new SparcV8TargetInfo(Triple); 8018 } 8019 8020 // The 'sparcel' architecture copies all the above cases except for Solaris. 8021 case llvm::Triple::sparcel: 8022 switch (os) { 8023 case llvm::Triple::Linux: 8024 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 8025 case llvm::Triple::NetBSD: 8026 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 8027 case llvm::Triple::OpenBSD: 8028 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 8029 case llvm::Triple::RTEMS: 8030 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 8031 default: 8032 return new SparcV8elTargetInfo(Triple); 8033 } 8034 8035 case llvm::Triple::sparcv9: 8036 switch (os) { 8037 case llvm::Triple::Linux: 8038 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 8039 case llvm::Triple::Solaris: 8040 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 8041 case llvm::Triple::NetBSD: 8042 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 8043 case llvm::Triple::OpenBSD: 8044 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 8045 case llvm::Triple::FreeBSD: 8046 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 8047 default: 8048 return new SparcV9TargetInfo(Triple); 8049 } 8050 8051 case llvm::Triple::systemz: 8052 switch (os) { 8053 case llvm::Triple::Linux: 8054 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 8055 default: 8056 return new SystemZTargetInfo(Triple); 8057 } 8058 8059 case llvm::Triple::tce: 8060 return new TCETargetInfo(Triple); 8061 8062 case llvm::Triple::x86: 8063 if (Triple.isOSDarwin()) 8064 return new DarwinI386TargetInfo(Triple); 8065 8066 switch (os) { 8067 case llvm::Triple::CloudABI: 8068 return new CloudABITargetInfo<X86_32TargetInfo>(Triple); 8069 case llvm::Triple::Linux: { 8070 switch (Triple.getEnvironment()) { 8071 default: 8072 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 8073 case llvm::Triple::Android: 8074 return new AndroidX86_32TargetInfo(Triple); 8075 } 8076 } 8077 case llvm::Triple::DragonFly: 8078 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 8079 case llvm::Triple::NetBSD: 8080 return new NetBSDI386TargetInfo(Triple); 8081 case llvm::Triple::OpenBSD: 8082 return new OpenBSDI386TargetInfo(Triple); 8083 case llvm::Triple::Bitrig: 8084 return new BitrigI386TargetInfo(Triple); 8085 case llvm::Triple::FreeBSD: 8086 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 8087 case llvm::Triple::KFreeBSD: 8088 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 8089 case llvm::Triple::Minix: 8090 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 8091 case llvm::Triple::Solaris: 8092 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 8093 case llvm::Triple::Win32: { 8094 switch (Triple.getEnvironment()) { 8095 case llvm::Triple::Cygnus: 8096 return new CygwinX86_32TargetInfo(Triple); 8097 case llvm::Triple::GNU: 8098 return new MinGWX86_32TargetInfo(Triple); 8099 case llvm::Triple::Itanium: 8100 case llvm::Triple::MSVC: 8101 default: // Assume MSVC for unknown environments 8102 return new MicrosoftX86_32TargetInfo(Triple); 8103 } 8104 } 8105 case llvm::Triple::Haiku: 8106 return new HaikuX86_32TargetInfo(Triple); 8107 case llvm::Triple::RTEMS: 8108 return new RTEMSX86_32TargetInfo(Triple); 8109 case llvm::Triple::NaCl: 8110 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 8111 case llvm::Triple::ELFIAMCU: 8112 return new MCUX86_32TargetInfo(Triple); 8113 default: 8114 return new X86_32TargetInfo(Triple); 8115 } 8116 8117 case llvm::Triple::x86_64: 8118 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 8119 return new DarwinX86_64TargetInfo(Triple); 8120 8121 switch (os) { 8122 case llvm::Triple::CloudABI: 8123 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 8124 case llvm::Triple::Linux: { 8125 switch (Triple.getEnvironment()) { 8126 default: 8127 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 8128 case llvm::Triple::Android: 8129 return new AndroidX86_64TargetInfo(Triple); 8130 } 8131 } 8132 case llvm::Triple::DragonFly: 8133 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 8134 case llvm::Triple::NetBSD: 8135 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 8136 case llvm::Triple::OpenBSD: 8137 return new OpenBSDX86_64TargetInfo(Triple); 8138 case llvm::Triple::Bitrig: 8139 return new BitrigX86_64TargetInfo(Triple); 8140 case llvm::Triple::FreeBSD: 8141 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 8142 case llvm::Triple::KFreeBSD: 8143 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 8144 case llvm::Triple::Solaris: 8145 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 8146 case llvm::Triple::Win32: { 8147 switch (Triple.getEnvironment()) { 8148 case llvm::Triple::Cygnus: 8149 return new CygwinX86_64TargetInfo(Triple); 8150 case llvm::Triple::GNU: 8151 return new MinGWX86_64TargetInfo(Triple); 8152 case llvm::Triple::MSVC: 8153 default: // Assume MSVC for unknown environments 8154 return new MicrosoftX86_64TargetInfo(Triple); 8155 } 8156 } 8157 case llvm::Triple::NaCl: 8158 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 8159 case llvm::Triple::PS4: 8160 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 8161 default: 8162 return new X86_64TargetInfo(Triple); 8163 } 8164 8165 case llvm::Triple::spir: { 8166 if (Triple.getOS() != llvm::Triple::UnknownOS || 8167 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8168 return nullptr; 8169 return new SPIR32TargetInfo(Triple); 8170 } 8171 case llvm::Triple::spir64: { 8172 if (Triple.getOS() != llvm::Triple::UnknownOS || 8173 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8174 return nullptr; 8175 return new SPIR64TargetInfo(Triple); 8176 } 8177 case llvm::Triple::wasm32: 8178 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8179 return nullptr; 8180 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple); 8181 case llvm::Triple::wasm64: 8182 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8183 return nullptr; 8184 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple); 8185 } 8186 } 8187 8188 /// CreateTargetInfo - Return the target info object for the specified target 8189 /// options. 8190 TargetInfo * 8191 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8192 const std::shared_ptr<TargetOptions> &Opts) { 8193 llvm::Triple Triple(Opts->Triple); 8194 8195 // Construct the target 8196 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 8197 if (!Target) { 8198 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8199 return nullptr; 8200 } 8201 Target->TargetOpts = Opts; 8202 8203 // Set the target CPU if specified. 8204 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8205 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8206 return nullptr; 8207 } 8208 8209 // Set the target ABI if specified. 8210 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8211 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8212 return nullptr; 8213 } 8214 8215 // Set the fp math unit. 8216 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8217 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8218 return nullptr; 8219 } 8220 8221 // Compute the default target features, we need the target to handle this 8222 // because features may have dependencies on one another. 8223 llvm::StringMap<bool> Features; 8224 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8225 Opts->FeaturesAsWritten)) 8226 return nullptr; 8227 8228 // Add the features to the compile options. 8229 Opts->Features.clear(); 8230 for (const auto &F : Features) 8231 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8232 8233 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8234 return nullptr; 8235 8236 return Target.release(); 8237 } 8238