1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/TargetParser.h" 31 #include <algorithm> 32 #include <memory> 33 using namespace clang; 34 35 //===----------------------------------------------------------------------===// 36 // Common code shared among targets. 37 //===----------------------------------------------------------------------===// 38 39 /// DefineStd - Define a macro name and standard variants. For example if 40 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 41 /// when in GNU mode. 42 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 43 const LangOptions &Opts) { 44 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 45 46 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 47 // in the user's namespace. 48 if (Opts.GNUMode) 49 Builder.defineMacro(MacroName); 50 51 // Define __unix. 52 Builder.defineMacro("__" + MacroName); 53 54 // Define __unix__. 55 Builder.defineMacro("__" + MacroName + "__"); 56 } 57 58 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 59 bool Tuning = true) { 60 Builder.defineMacro("__" + CPUName); 61 Builder.defineMacro("__" + CPUName + "__"); 62 if (Tuning) 63 Builder.defineMacro("__tune_" + CPUName + "__"); 64 } 65 66 //===----------------------------------------------------------------------===// 67 // Defines specific to certain operating systems. 68 //===----------------------------------------------------------------------===// 69 70 namespace { 71 template<typename TgtInfo> 72 class OSTargetInfo : public TgtInfo { 73 protected: 74 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 75 MacroBuilder &Builder) const=0; 76 public: 77 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 78 void getTargetDefines(const LangOptions &Opts, 79 MacroBuilder &Builder) const override { 80 TgtInfo::getTargetDefines(Opts, Builder); 81 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 82 } 83 84 }; 85 } // end anonymous namespace 86 87 88 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 89 const llvm::Triple &Triple, 90 StringRef &PlatformName, 91 VersionTuple &PlatformMinVersion) { 92 Builder.defineMacro("__APPLE_CC__", "6000"); 93 Builder.defineMacro("__APPLE__"); 94 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 95 // AddressSanitizer doesn't play well with source fortification, which is on 96 // by default on Darwin. 97 if (Opts.Sanitize.has(SanitizerKind::Address)) 98 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 99 100 if (!Opts.ObjCAutoRefCount) { 101 // __weak is always defined, for use in blocks and with objc pointers. 102 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 103 104 // Darwin defines __strong even in C mode (just to nothing). 105 if (Opts.getGC() != LangOptions::NonGC) 106 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 107 else 108 Builder.defineMacro("__strong", ""); 109 110 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 111 // allow this in C, since one might have block pointers in structs that 112 // are used in pure C code and in Objective-C ARC. 113 Builder.defineMacro("__unsafe_unretained", ""); 114 } 115 116 if (Opts.Static) 117 Builder.defineMacro("__STATIC__"); 118 else 119 Builder.defineMacro("__DYNAMIC__"); 120 121 if (Opts.POSIXThreads) 122 Builder.defineMacro("_REENTRANT"); 123 124 // Get the platform type and version number from the triple. 125 unsigned Maj, Min, Rev; 126 if (Triple.isMacOSX()) { 127 Triple.getMacOSXVersion(Maj, Min, Rev); 128 PlatformName = "macosx"; 129 } else { 130 Triple.getOSVersion(Maj, Min, Rev); 131 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 132 } 133 134 // If -target arch-pc-win32-macho option specified, we're 135 // generating code for Win32 ABI. No need to emit 136 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 137 if (PlatformName == "win32") { 138 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 139 return; 140 } 141 142 // Set the appropriate OS version define. 143 if (Triple.isiOS()) { 144 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 145 char Str[6]; 146 Str[0] = '0' + Maj; 147 Str[1] = '0' + (Min / 10); 148 Str[2] = '0' + (Min % 10); 149 Str[3] = '0' + (Rev / 10); 150 Str[4] = '0' + (Rev % 10); 151 Str[5] = '\0'; 152 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 153 Str); 154 } else if (Triple.isMacOSX()) { 155 // Note that the Driver allows versions which aren't representable in the 156 // define (because we only get a single digit for the minor and micro 157 // revision numbers). So, we limit them to the maximum representable 158 // version. 159 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 160 char Str[7]; 161 if (Maj < 10 || (Maj == 10 && Min < 10)) { 162 Str[0] = '0' + (Maj / 10); 163 Str[1] = '0' + (Maj % 10); 164 Str[2] = '0' + std::min(Min, 9U); 165 Str[3] = '0' + std::min(Rev, 9U); 166 Str[4] = '\0'; 167 } else { 168 // Handle versions > 10.9. 169 Str[0] = '0' + (Maj / 10); 170 Str[1] = '0' + (Maj % 10); 171 Str[2] = '0' + (Min / 10); 172 Str[3] = '0' + (Min % 10); 173 Str[4] = '0' + (Rev / 10); 174 Str[5] = '0' + (Rev % 10); 175 Str[6] = '\0'; 176 } 177 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 178 } 179 180 // Tell users about the kernel if there is one. 181 if (Triple.isOSDarwin()) 182 Builder.defineMacro("__MACH__"); 183 184 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 185 } 186 187 namespace { 188 // CloudABI Target 189 template <typename Target> 190 class CloudABITargetInfo : public OSTargetInfo<Target> { 191 protected: 192 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 193 MacroBuilder &Builder) const override { 194 Builder.defineMacro("__CloudABI__"); 195 Builder.defineMacro("__ELF__"); 196 197 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 198 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 199 Builder.defineMacro("__STDC_UTF_16__"); 200 Builder.defineMacro("__STDC_UTF_32__"); 201 } 202 203 public: 204 CloudABITargetInfo(const llvm::Triple &Triple) 205 : OSTargetInfo<Target>(Triple) { 206 this->UserLabelPrefix = ""; 207 } 208 }; 209 210 template<typename Target> 211 class DarwinTargetInfo : public OSTargetInfo<Target> { 212 protected: 213 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 214 MacroBuilder &Builder) const override { 215 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 216 this->PlatformMinVersion); 217 } 218 219 public: 220 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 221 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 222 this->MCountName = "\01mcount"; 223 } 224 225 std::string isValidSectionSpecifier(StringRef SR) const override { 226 // Let MCSectionMachO validate this. 227 StringRef Segment, Section; 228 unsigned TAA, StubSize; 229 bool HasTAA; 230 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 231 TAA, HasTAA, StubSize); 232 } 233 234 const char *getStaticInitSectionSpecifier() const override { 235 // FIXME: We should return 0 when building kexts. 236 return "__TEXT,__StaticInit,regular,pure_instructions"; 237 } 238 239 /// Darwin does not support protected visibility. Darwin's "default" 240 /// is very similar to ELF's "protected"; Darwin requires a "weak" 241 /// attribute on declarations that can be dynamically replaced. 242 bool hasProtectedVisibility() const override { 243 return false; 244 } 245 }; 246 247 248 // DragonFlyBSD Target 249 template<typename Target> 250 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 251 protected: 252 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 253 MacroBuilder &Builder) const override { 254 // DragonFly defines; list based off of gcc output 255 Builder.defineMacro("__DragonFly__"); 256 Builder.defineMacro("__DragonFly_cc_version", "100001"); 257 Builder.defineMacro("__ELF__"); 258 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 259 Builder.defineMacro("__tune_i386__"); 260 DefineStd(Builder, "unix", Opts); 261 } 262 public: 263 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 264 : OSTargetInfo<Target>(Triple) { 265 this->UserLabelPrefix = ""; 266 267 switch (Triple.getArch()) { 268 default: 269 case llvm::Triple::x86: 270 case llvm::Triple::x86_64: 271 this->MCountName = ".mcount"; 272 break; 273 } 274 } 275 }; 276 277 // FreeBSD Target 278 template<typename Target> 279 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 280 protected: 281 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 282 MacroBuilder &Builder) const override { 283 // FreeBSD defines; list based off of gcc output 284 285 unsigned Release = Triple.getOSMajorVersion(); 286 if (Release == 0U) 287 Release = 8; 288 289 Builder.defineMacro("__FreeBSD__", Twine(Release)); 290 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 291 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 292 DefineStd(Builder, "unix", Opts); 293 Builder.defineMacro("__ELF__"); 294 295 // On FreeBSD, wchar_t contains the number of the code point as 296 // used by the character set of the locale. These character sets are 297 // not necessarily a superset of ASCII. 298 // 299 // FIXME: This is wrong; the macro refers to the numerical values 300 // of wchar_t *literals*, which are not locale-dependent. However, 301 // FreeBSD systems apparently depend on us getting this wrong, and 302 // setting this to 1 is conforming even if all the basic source 303 // character literals have the same encoding as char and wchar_t. 304 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 305 } 306 public: 307 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 308 this->UserLabelPrefix = ""; 309 310 switch (Triple.getArch()) { 311 default: 312 case llvm::Triple::x86: 313 case llvm::Triple::x86_64: 314 this->MCountName = ".mcount"; 315 break; 316 case llvm::Triple::mips: 317 case llvm::Triple::mipsel: 318 case llvm::Triple::ppc: 319 case llvm::Triple::ppc64: 320 case llvm::Triple::ppc64le: 321 this->MCountName = "_mcount"; 322 break; 323 case llvm::Triple::arm: 324 this->MCountName = "__mcount"; 325 break; 326 } 327 } 328 }; 329 330 // GNU/kFreeBSD Target 331 template<typename Target> 332 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 333 protected: 334 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 335 MacroBuilder &Builder) const override { 336 // GNU/kFreeBSD defines; list based off of gcc output 337 338 DefineStd(Builder, "unix", Opts); 339 Builder.defineMacro("__FreeBSD_kernel__"); 340 Builder.defineMacro("__GLIBC__"); 341 Builder.defineMacro("__ELF__"); 342 if (Opts.POSIXThreads) 343 Builder.defineMacro("_REENTRANT"); 344 if (Opts.CPlusPlus) 345 Builder.defineMacro("_GNU_SOURCE"); 346 } 347 public: 348 KFreeBSDTargetInfo(const llvm::Triple &Triple) 349 : OSTargetInfo<Target>(Triple) { 350 this->UserLabelPrefix = ""; 351 } 352 }; 353 354 // Minix Target 355 template<typename Target> 356 class MinixTargetInfo : public OSTargetInfo<Target> { 357 protected: 358 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 359 MacroBuilder &Builder) const override { 360 // Minix defines 361 362 Builder.defineMacro("__minix", "3"); 363 Builder.defineMacro("_EM_WSIZE", "4"); 364 Builder.defineMacro("_EM_PSIZE", "4"); 365 Builder.defineMacro("_EM_SSIZE", "2"); 366 Builder.defineMacro("_EM_LSIZE", "4"); 367 Builder.defineMacro("_EM_FSIZE", "4"); 368 Builder.defineMacro("_EM_DSIZE", "8"); 369 Builder.defineMacro("__ELF__"); 370 DefineStd(Builder, "unix", Opts); 371 } 372 public: 373 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 374 this->UserLabelPrefix = ""; 375 } 376 }; 377 378 // Linux target 379 template<typename Target> 380 class LinuxTargetInfo : public OSTargetInfo<Target> { 381 protected: 382 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 383 MacroBuilder &Builder) const override { 384 // Linux defines; list based off of gcc output 385 DefineStd(Builder, "unix", Opts); 386 DefineStd(Builder, "linux", Opts); 387 Builder.defineMacro("__gnu_linux__"); 388 Builder.defineMacro("__ELF__"); 389 if (Triple.getEnvironment() == llvm::Triple::Android) { 390 Builder.defineMacro("__ANDROID__", "1"); 391 unsigned Maj, Min, Rev; 392 Triple.getEnvironmentVersion(Maj, Min, Rev); 393 this->PlatformName = "android"; 394 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 395 } 396 if (Opts.POSIXThreads) 397 Builder.defineMacro("_REENTRANT"); 398 if (Opts.CPlusPlus) 399 Builder.defineMacro("_GNU_SOURCE"); 400 } 401 public: 402 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 403 this->UserLabelPrefix = ""; 404 this->WIntType = TargetInfo::UnsignedInt; 405 406 switch (Triple.getArch()) { 407 default: 408 break; 409 case llvm::Triple::ppc: 410 case llvm::Triple::ppc64: 411 case llvm::Triple::ppc64le: 412 this->MCountName = "_mcount"; 413 break; 414 } 415 } 416 417 const char *getStaticInitSectionSpecifier() const override { 418 return ".text.startup"; 419 } 420 }; 421 422 // NetBSD Target 423 template<typename Target> 424 class NetBSDTargetInfo : public OSTargetInfo<Target> { 425 protected: 426 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 427 MacroBuilder &Builder) const override { 428 // NetBSD defines; list based off of gcc output 429 Builder.defineMacro("__NetBSD__"); 430 Builder.defineMacro("__unix__"); 431 Builder.defineMacro("__ELF__"); 432 if (Opts.POSIXThreads) 433 Builder.defineMacro("_POSIX_THREADS"); 434 435 switch (Triple.getArch()) { 436 default: 437 break; 438 case llvm::Triple::arm: 439 case llvm::Triple::armeb: 440 case llvm::Triple::thumb: 441 case llvm::Triple::thumbeb: 442 Builder.defineMacro("__ARM_DWARF_EH__"); 443 break; 444 } 445 } 446 public: 447 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 448 this->UserLabelPrefix = ""; 449 this->MCountName = "_mcount"; 450 } 451 }; 452 453 // OpenBSD Target 454 template<typename Target> 455 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 456 protected: 457 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 458 MacroBuilder &Builder) const override { 459 // OpenBSD defines; list based off of gcc output 460 461 Builder.defineMacro("__OpenBSD__"); 462 DefineStd(Builder, "unix", Opts); 463 Builder.defineMacro("__ELF__"); 464 if (Opts.POSIXThreads) 465 Builder.defineMacro("_REENTRANT"); 466 } 467 public: 468 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 469 this->UserLabelPrefix = ""; 470 this->TLSSupported = false; 471 472 switch (Triple.getArch()) { 473 default: 474 case llvm::Triple::x86: 475 case llvm::Triple::x86_64: 476 case llvm::Triple::arm: 477 case llvm::Triple::sparc: 478 this->MCountName = "__mcount"; 479 break; 480 case llvm::Triple::mips64: 481 case llvm::Triple::mips64el: 482 case llvm::Triple::ppc: 483 case llvm::Triple::sparcv9: 484 this->MCountName = "_mcount"; 485 break; 486 } 487 } 488 }; 489 490 // Bitrig Target 491 template<typename Target> 492 class BitrigTargetInfo : public OSTargetInfo<Target> { 493 protected: 494 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 495 MacroBuilder &Builder) const override { 496 // Bitrig defines; list based off of gcc output 497 498 Builder.defineMacro("__Bitrig__"); 499 DefineStd(Builder, "unix", Opts); 500 Builder.defineMacro("__ELF__"); 501 if (Opts.POSIXThreads) 502 Builder.defineMacro("_REENTRANT"); 503 504 switch (Triple.getArch()) { 505 default: 506 break; 507 case llvm::Triple::arm: 508 case llvm::Triple::armeb: 509 case llvm::Triple::thumb: 510 case llvm::Triple::thumbeb: 511 Builder.defineMacro("__ARM_DWARF_EH__"); 512 break; 513 } 514 } 515 public: 516 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 517 this->UserLabelPrefix = ""; 518 this->MCountName = "__mcount"; 519 } 520 }; 521 522 // PSP Target 523 template<typename Target> 524 class PSPTargetInfo : public OSTargetInfo<Target> { 525 protected: 526 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 527 MacroBuilder &Builder) const override { 528 // PSP defines; list based on the output of the pspdev gcc toolchain. 529 Builder.defineMacro("PSP"); 530 Builder.defineMacro("_PSP"); 531 Builder.defineMacro("__psp__"); 532 Builder.defineMacro("__ELF__"); 533 } 534 public: 535 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 536 this->UserLabelPrefix = ""; 537 } 538 }; 539 540 // PS3 PPU Target 541 template<typename Target> 542 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 543 protected: 544 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 545 MacroBuilder &Builder) const override { 546 // PS3 PPU defines. 547 Builder.defineMacro("__PPC__"); 548 Builder.defineMacro("__PPU__"); 549 Builder.defineMacro("__CELLOS_LV2__"); 550 Builder.defineMacro("__ELF__"); 551 Builder.defineMacro("__LP32__"); 552 Builder.defineMacro("_ARCH_PPC64"); 553 Builder.defineMacro("__powerpc64__"); 554 } 555 public: 556 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 557 this->UserLabelPrefix = ""; 558 this->LongWidth = this->LongAlign = 32; 559 this->PointerWidth = this->PointerAlign = 32; 560 this->IntMaxType = TargetInfo::SignedLongLong; 561 this->Int64Type = TargetInfo::SignedLongLong; 562 this->SizeType = TargetInfo::UnsignedInt; 563 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64"; 564 } 565 }; 566 567 template <typename Target> 568 class PS4OSTargetInfo : public OSTargetInfo<Target> { 569 protected: 570 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 571 MacroBuilder &Builder) const override { 572 Builder.defineMacro("__FreeBSD__", "9"); 573 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 574 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 575 DefineStd(Builder, "unix", Opts); 576 Builder.defineMacro("__ELF__"); 577 Builder.defineMacro("__PS4__"); 578 } 579 public: 580 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 581 this->WCharType = this->UnsignedShort; 582 583 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 584 this->MaxTLSAlign = 256; 585 this->UserLabelPrefix = ""; 586 587 switch (Triple.getArch()) { 588 default: 589 case llvm::Triple::x86_64: 590 this->MCountName = ".mcount"; 591 break; 592 } 593 } 594 }; 595 596 // Solaris target 597 template<typename Target> 598 class SolarisTargetInfo : public OSTargetInfo<Target> { 599 protected: 600 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 601 MacroBuilder &Builder) const override { 602 DefineStd(Builder, "sun", Opts); 603 DefineStd(Builder, "unix", Opts); 604 Builder.defineMacro("__ELF__"); 605 Builder.defineMacro("__svr4__"); 606 Builder.defineMacro("__SVR4"); 607 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 608 // newer, but to 500 for everything else. feature_test.h has a check to 609 // ensure that you are not using C99 with an old version of X/Open or C89 610 // with a new version. 611 if (Opts.C99) 612 Builder.defineMacro("_XOPEN_SOURCE", "600"); 613 else 614 Builder.defineMacro("_XOPEN_SOURCE", "500"); 615 if (Opts.CPlusPlus) 616 Builder.defineMacro("__C99FEATURES__"); 617 Builder.defineMacro("_LARGEFILE_SOURCE"); 618 Builder.defineMacro("_LARGEFILE64_SOURCE"); 619 Builder.defineMacro("__EXTENSIONS__"); 620 Builder.defineMacro("_REENTRANT"); 621 } 622 public: 623 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 624 this->UserLabelPrefix = ""; 625 this->WCharType = this->SignedInt; 626 // FIXME: WIntType should be SignedLong 627 } 628 }; 629 630 // Windows target 631 template<typename Target> 632 class WindowsTargetInfo : public OSTargetInfo<Target> { 633 protected: 634 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 635 MacroBuilder &Builder) const override { 636 Builder.defineMacro("_WIN32"); 637 } 638 void getVisualStudioDefines(const LangOptions &Opts, 639 MacroBuilder &Builder) const { 640 if (Opts.CPlusPlus) { 641 if (Opts.RTTIData) 642 Builder.defineMacro("_CPPRTTI"); 643 644 if (Opts.CXXExceptions) 645 Builder.defineMacro("_CPPUNWIND"); 646 } 647 648 if (Opts.Bool) 649 Builder.defineMacro("__BOOL_DEFINED"); 650 651 if (!Opts.CharIsSigned) 652 Builder.defineMacro("_CHAR_UNSIGNED"); 653 654 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 655 // but it works for now. 656 if (Opts.POSIXThreads) 657 Builder.defineMacro("_MT"); 658 659 if (Opts.MSCompatibilityVersion) { 660 Builder.defineMacro("_MSC_VER", 661 Twine(Opts.MSCompatibilityVersion / 100000)); 662 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 663 // FIXME We cannot encode the revision information into 32-bits 664 Builder.defineMacro("_MSC_BUILD", Twine(1)); 665 666 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 667 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 668 } 669 670 if (Opts.MicrosoftExt) { 671 Builder.defineMacro("_MSC_EXTENSIONS"); 672 673 if (Opts.CPlusPlus11) { 674 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 675 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 676 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 677 } 678 } 679 680 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 681 } 682 683 public: 684 WindowsTargetInfo(const llvm::Triple &Triple) 685 : OSTargetInfo<Target>(Triple) {} 686 }; 687 688 template <typename Target> 689 class NaClTargetInfo : public OSTargetInfo<Target> { 690 protected: 691 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 692 MacroBuilder &Builder) const override { 693 if (Opts.POSIXThreads) 694 Builder.defineMacro("_REENTRANT"); 695 if (Opts.CPlusPlus) 696 Builder.defineMacro("_GNU_SOURCE"); 697 698 DefineStd(Builder, "unix", Opts); 699 Builder.defineMacro("__ELF__"); 700 Builder.defineMacro("__native_client__"); 701 } 702 703 public: 704 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 705 this->UserLabelPrefix = ""; 706 this->LongAlign = 32; 707 this->LongWidth = 32; 708 this->PointerAlign = 32; 709 this->PointerWidth = 32; 710 this->IntMaxType = TargetInfo::SignedLongLong; 711 this->Int64Type = TargetInfo::SignedLongLong; 712 this->DoubleAlign = 64; 713 this->LongDoubleWidth = 64; 714 this->LongDoubleAlign = 64; 715 this->LongLongWidth = 64; 716 this->LongLongAlign = 64; 717 this->SizeType = TargetInfo::UnsignedInt; 718 this->PtrDiffType = TargetInfo::SignedInt; 719 this->IntPtrType = TargetInfo::SignedInt; 720 // RegParmMax is inherited from the underlying architecture 721 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 722 if (Triple.getArch() == llvm::Triple::arm) { 723 // Handled in ARM's setABI(). 724 } else if (Triple.getArch() == llvm::Triple::x86) { 725 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 726 } else if (Triple.getArch() == llvm::Triple::x86_64) { 727 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 728 } else if (Triple.getArch() == llvm::Triple::mipsel) { 729 // Handled on mips' setDescriptionString. 730 } else { 731 assert(Triple.getArch() == llvm::Triple::le32); 732 this->DescriptionString = "e-p:32:32-i64:64"; 733 } 734 } 735 }; 736 737 //===----------------------------------------------------------------------===// 738 // Specific target implementations. 739 //===----------------------------------------------------------------------===// 740 741 // PPC abstract base class 742 class PPCTargetInfo : public TargetInfo { 743 static const Builtin::Info BuiltinInfo[]; 744 static const char * const GCCRegNames[]; 745 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 746 std::string CPU; 747 748 // Target cpu features. 749 bool HasVSX; 750 bool HasP8Vector; 751 bool HasP8Crypto; 752 bool HasDirectMove; 753 bool HasQPX; 754 bool HasHTM; 755 bool HasBPERMD; 756 bool HasExtDiv; 757 758 protected: 759 std::string ABI; 760 761 public: 762 PPCTargetInfo(const llvm::Triple &Triple) 763 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 764 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 765 HasBPERMD(false), HasExtDiv(false) { 766 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 767 SimdDefaultAlign = 128; 768 LongDoubleWidth = LongDoubleAlign = 128; 769 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 770 } 771 772 /// \brief Flags for architecture specific defines. 773 typedef enum { 774 ArchDefineNone = 0, 775 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 776 ArchDefinePpcgr = 1 << 1, 777 ArchDefinePpcsq = 1 << 2, 778 ArchDefine440 = 1 << 3, 779 ArchDefine603 = 1 << 4, 780 ArchDefine604 = 1 << 5, 781 ArchDefinePwr4 = 1 << 6, 782 ArchDefinePwr5 = 1 << 7, 783 ArchDefinePwr5x = 1 << 8, 784 ArchDefinePwr6 = 1 << 9, 785 ArchDefinePwr6x = 1 << 10, 786 ArchDefinePwr7 = 1 << 11, 787 ArchDefinePwr8 = 1 << 12, 788 ArchDefineA2 = 1 << 13, 789 ArchDefineA2q = 1 << 14 790 } ArchDefineTypes; 791 792 // Note: GCC recognizes the following additional cpus: 793 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 794 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 795 // titan, rs64. 796 bool setCPU(const std::string &Name) override { 797 bool CPUKnown = llvm::StringSwitch<bool>(Name) 798 .Case("generic", true) 799 .Case("440", true) 800 .Case("450", true) 801 .Case("601", true) 802 .Case("602", true) 803 .Case("603", true) 804 .Case("603e", true) 805 .Case("603ev", true) 806 .Case("604", true) 807 .Case("604e", true) 808 .Case("620", true) 809 .Case("630", true) 810 .Case("g3", true) 811 .Case("7400", true) 812 .Case("g4", true) 813 .Case("7450", true) 814 .Case("g4+", true) 815 .Case("750", true) 816 .Case("970", true) 817 .Case("g5", true) 818 .Case("a2", true) 819 .Case("a2q", true) 820 .Case("e500mc", true) 821 .Case("e5500", true) 822 .Case("power3", true) 823 .Case("pwr3", true) 824 .Case("power4", true) 825 .Case("pwr4", true) 826 .Case("power5", true) 827 .Case("pwr5", true) 828 .Case("power5x", true) 829 .Case("pwr5x", true) 830 .Case("power6", true) 831 .Case("pwr6", true) 832 .Case("power6x", true) 833 .Case("pwr6x", true) 834 .Case("power7", true) 835 .Case("pwr7", true) 836 .Case("power8", true) 837 .Case("pwr8", true) 838 .Case("powerpc", true) 839 .Case("ppc", true) 840 .Case("powerpc64", true) 841 .Case("ppc64", true) 842 .Case("powerpc64le", true) 843 .Case("ppc64le", true) 844 .Default(false); 845 846 if (CPUKnown) 847 CPU = Name; 848 849 return CPUKnown; 850 } 851 852 853 StringRef getABI() const override { return ABI; } 854 855 void getTargetBuiltins(const Builtin::Info *&Records, 856 unsigned &NumRecords) const override { 857 Records = BuiltinInfo; 858 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 859 } 860 861 bool isCLZForZeroUndef() const override { return false; } 862 863 void getTargetDefines(const LangOptions &Opts, 864 MacroBuilder &Builder) const override; 865 866 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 867 868 bool handleTargetFeatures(std::vector<std::string> &Features, 869 DiagnosticsEngine &Diags) override; 870 bool hasFeature(StringRef Feature) const override; 871 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 872 bool Enabled) const override; 873 874 void getGCCRegNames(const char * const *&Names, 875 unsigned &NumNames) const override; 876 void getGCCRegAliases(const GCCRegAlias *&Aliases, 877 unsigned &NumAliases) const override; 878 bool validateAsmConstraint(const char *&Name, 879 TargetInfo::ConstraintInfo &Info) const override { 880 switch (*Name) { 881 default: return false; 882 case 'O': // Zero 883 break; 884 case 'b': // Base register 885 case 'f': // Floating point register 886 Info.setAllowsRegister(); 887 break; 888 // FIXME: The following are added to allow parsing. 889 // I just took a guess at what the actions should be. 890 // Also, is more specific checking needed? I.e. specific registers? 891 case 'd': // Floating point register (containing 64-bit value) 892 case 'v': // Altivec vector register 893 Info.setAllowsRegister(); 894 break; 895 case 'w': 896 switch (Name[1]) { 897 case 'd':// VSX vector register to hold vector double data 898 case 'f':// VSX vector register to hold vector float data 899 case 's':// VSX vector register to hold scalar float data 900 case 'a':// Any VSX register 901 case 'c':// An individual CR bit 902 break; 903 default: 904 return false; 905 } 906 Info.setAllowsRegister(); 907 Name++; // Skip over 'w'. 908 break; 909 case 'h': // `MQ', `CTR', or `LINK' register 910 case 'q': // `MQ' register 911 case 'c': // `CTR' register 912 case 'l': // `LINK' register 913 case 'x': // `CR' register (condition register) number 0 914 case 'y': // `CR' register (condition register) 915 case 'z': // `XER[CA]' carry bit (part of the XER register) 916 Info.setAllowsRegister(); 917 break; 918 case 'I': // Signed 16-bit constant 919 case 'J': // Unsigned 16-bit constant shifted left 16 bits 920 // (use `L' instead for SImode constants) 921 case 'K': // Unsigned 16-bit constant 922 case 'L': // Signed 16-bit constant shifted left 16 bits 923 case 'M': // Constant larger than 31 924 case 'N': // Exact power of 2 925 case 'P': // Constant whose negation is a signed 16-bit constant 926 case 'G': // Floating point constant that can be loaded into a 927 // register with one instruction per word 928 case 'H': // Integer/Floating point constant that can be loaded 929 // into a register using three instructions 930 break; 931 case 'm': // Memory operand. Note that on PowerPC targets, m can 932 // include addresses that update the base register. It 933 // is therefore only safe to use `m' in an asm statement 934 // if that asm statement accesses the operand exactly once. 935 // The asm statement must also use `%U<opno>' as a 936 // placeholder for the "update" flag in the corresponding 937 // load or store instruction. For example: 938 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 939 // is correct but: 940 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 941 // is not. Use es rather than m if you don't want the base 942 // register to be updated. 943 case 'e': 944 if (Name[1] != 's') 945 return false; 946 // es: A "stable" memory operand; that is, one which does not 947 // include any automodification of the base register. Unlike 948 // `m', this constraint can be used in asm statements that 949 // might access the operand several times, or that might not 950 // access it at all. 951 Info.setAllowsMemory(); 952 Name++; // Skip over 'e'. 953 break; 954 case 'Q': // Memory operand that is an offset from a register (it is 955 // usually better to use `m' or `es' in asm statements) 956 case 'Z': // Memory operand that is an indexed or indirect from a 957 // register (it is usually better to use `m' or `es' in 958 // asm statements) 959 Info.setAllowsMemory(); 960 Info.setAllowsRegister(); 961 break; 962 case 'R': // AIX TOC entry 963 case 'a': // Address operand that is an indexed or indirect from a 964 // register (`p' is preferable for asm statements) 965 case 'S': // Constant suitable as a 64-bit mask operand 966 case 'T': // Constant suitable as a 32-bit mask operand 967 case 'U': // System V Release 4 small data area reference 968 case 't': // AND masks that can be performed by two rldic{l, r} 969 // instructions 970 case 'W': // Vector constant that does not require memory 971 case 'j': // Vector constant that is all zeros. 972 break; 973 // End FIXME. 974 } 975 return true; 976 } 977 std::string convertConstraint(const char *&Constraint) const override { 978 std::string R; 979 switch (*Constraint) { 980 case 'e': 981 case 'w': 982 // Two-character constraint; add "^" hint for later parsing. 983 R = std::string("^") + std::string(Constraint, 2); 984 Constraint++; 985 break; 986 default: 987 return TargetInfo::convertConstraint(Constraint); 988 } 989 return R; 990 } 991 const char *getClobbers() const override { 992 return ""; 993 } 994 int getEHDataRegisterNumber(unsigned RegNo) const override { 995 if (RegNo == 0) return 3; 996 if (RegNo == 1) return 4; 997 return -1; 998 } 999 1000 bool hasSjLjLowering() const override { 1001 return true; 1002 } 1003 1004 bool useFloat128ManglingForLongDouble() const override { 1005 return LongDoubleWidth == 128 && 1006 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1007 getTriple().isOSBinFormatELF(); 1008 } 1009 }; 1010 1011 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1012 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1013 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1014 ALL_LANGUAGES }, 1015 #include "clang/Basic/BuiltinsPPC.def" 1016 }; 1017 1018 /// handleTargetFeatures - Perform initialization based on the user 1019 /// configured set of features. 1020 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1021 DiagnosticsEngine &Diags) { 1022 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 1023 // Ignore disabled features. 1024 if (Features[i][0] == '-') 1025 continue; 1026 1027 StringRef Feature = StringRef(Features[i]).substr(1); 1028 1029 if (Feature == "vsx") { 1030 HasVSX = true; 1031 continue; 1032 } 1033 1034 if (Feature == "bpermd") { 1035 HasBPERMD = true; 1036 continue; 1037 } 1038 1039 if (Feature == "extdiv") { 1040 HasExtDiv = true; 1041 continue; 1042 } 1043 1044 if (Feature == "power8-vector") { 1045 HasP8Vector = true; 1046 continue; 1047 } 1048 1049 if (Feature == "crypto") { 1050 HasP8Crypto = true; 1051 continue; 1052 } 1053 1054 if (Feature == "direct-move") { 1055 HasDirectMove = true; 1056 continue; 1057 } 1058 1059 if (Feature == "qpx") { 1060 HasQPX = true; 1061 continue; 1062 } 1063 1064 if (Feature == "htm") { 1065 HasHTM = true; 1066 continue; 1067 } 1068 1069 // TODO: Finish this list and add an assert that we've handled them 1070 // all. 1071 } 1072 if (!HasVSX && (HasP8Vector || HasDirectMove)) { 1073 if (HasP8Vector) 1074 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" << 1075 "-mno-vsx"; 1076 else if (HasDirectMove) 1077 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" << 1078 "-mno-vsx"; 1079 return false; 1080 } 1081 1082 return true; 1083 } 1084 1085 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1086 /// #defines that are not tied to a specific subtarget. 1087 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1088 MacroBuilder &Builder) const { 1089 // Target identification. 1090 Builder.defineMacro("__ppc__"); 1091 Builder.defineMacro("__PPC__"); 1092 Builder.defineMacro("_ARCH_PPC"); 1093 Builder.defineMacro("__powerpc__"); 1094 Builder.defineMacro("__POWERPC__"); 1095 if (PointerWidth == 64) { 1096 Builder.defineMacro("_ARCH_PPC64"); 1097 Builder.defineMacro("__powerpc64__"); 1098 Builder.defineMacro("__ppc64__"); 1099 Builder.defineMacro("__PPC64__"); 1100 } 1101 1102 // Target properties. 1103 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1104 Builder.defineMacro("_LITTLE_ENDIAN"); 1105 } else { 1106 if (getTriple().getOS() != llvm::Triple::NetBSD && 1107 getTriple().getOS() != llvm::Triple::OpenBSD) 1108 Builder.defineMacro("_BIG_ENDIAN"); 1109 } 1110 1111 // ABI options. 1112 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1113 Builder.defineMacro("_CALL_ELF", "1"); 1114 if (ABI == "elfv2") 1115 Builder.defineMacro("_CALL_ELF", "2"); 1116 1117 // Subtarget options. 1118 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1119 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1120 1121 // FIXME: Should be controlled by command line option. 1122 if (LongDoubleWidth == 128) 1123 Builder.defineMacro("__LONG_DOUBLE_128__"); 1124 1125 if (Opts.AltiVec) { 1126 Builder.defineMacro("__VEC__", "10206"); 1127 Builder.defineMacro("__ALTIVEC__"); 1128 } 1129 1130 // CPU identification. 1131 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1132 .Case("440", ArchDefineName) 1133 .Case("450", ArchDefineName | ArchDefine440) 1134 .Case("601", ArchDefineName) 1135 .Case("602", ArchDefineName | ArchDefinePpcgr) 1136 .Case("603", ArchDefineName | ArchDefinePpcgr) 1137 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1138 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1139 .Case("604", ArchDefineName | ArchDefinePpcgr) 1140 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1141 .Case("620", ArchDefineName | ArchDefinePpcgr) 1142 .Case("630", ArchDefineName | ArchDefinePpcgr) 1143 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1144 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1145 .Case("750", ArchDefineName | ArchDefinePpcgr) 1146 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1147 | ArchDefinePpcsq) 1148 .Case("a2", ArchDefineA2) 1149 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1150 .Case("pwr3", ArchDefinePpcgr) 1151 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1152 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1153 | ArchDefinePpcsq) 1154 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1155 | ArchDefinePpcgr | ArchDefinePpcsq) 1156 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1157 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1158 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1159 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1160 | ArchDefinePpcsq) 1161 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1162 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1163 | ArchDefinePpcgr | ArchDefinePpcsq) 1164 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1165 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1166 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1167 .Case("power3", ArchDefinePpcgr) 1168 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1169 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1170 | ArchDefinePpcsq) 1171 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1172 | ArchDefinePpcgr | ArchDefinePpcsq) 1173 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1174 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1175 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1176 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1177 | ArchDefinePpcsq) 1178 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1179 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1180 | ArchDefinePpcgr | ArchDefinePpcsq) 1181 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1182 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1183 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1184 .Default(ArchDefineNone); 1185 1186 if (defs & ArchDefineName) 1187 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1188 if (defs & ArchDefinePpcgr) 1189 Builder.defineMacro("_ARCH_PPCGR"); 1190 if (defs & ArchDefinePpcsq) 1191 Builder.defineMacro("_ARCH_PPCSQ"); 1192 if (defs & ArchDefine440) 1193 Builder.defineMacro("_ARCH_440"); 1194 if (defs & ArchDefine603) 1195 Builder.defineMacro("_ARCH_603"); 1196 if (defs & ArchDefine604) 1197 Builder.defineMacro("_ARCH_604"); 1198 if (defs & ArchDefinePwr4) 1199 Builder.defineMacro("_ARCH_PWR4"); 1200 if (defs & ArchDefinePwr5) 1201 Builder.defineMacro("_ARCH_PWR5"); 1202 if (defs & ArchDefinePwr5x) 1203 Builder.defineMacro("_ARCH_PWR5X"); 1204 if (defs & ArchDefinePwr6) 1205 Builder.defineMacro("_ARCH_PWR6"); 1206 if (defs & ArchDefinePwr6x) 1207 Builder.defineMacro("_ARCH_PWR6X"); 1208 if (defs & ArchDefinePwr7) 1209 Builder.defineMacro("_ARCH_PWR7"); 1210 if (defs & ArchDefinePwr8) 1211 Builder.defineMacro("_ARCH_PWR8"); 1212 if (defs & ArchDefineA2) 1213 Builder.defineMacro("_ARCH_A2"); 1214 if (defs & ArchDefineA2q) { 1215 Builder.defineMacro("_ARCH_A2Q"); 1216 Builder.defineMacro("_ARCH_QP"); 1217 } 1218 1219 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1220 Builder.defineMacro("__bg__"); 1221 Builder.defineMacro("__THW_BLUEGENE__"); 1222 Builder.defineMacro("__bgq__"); 1223 Builder.defineMacro("__TOS_BGQ__"); 1224 } 1225 1226 if (HasVSX) 1227 Builder.defineMacro("__VSX__"); 1228 if (HasP8Vector) 1229 Builder.defineMacro("__POWER8_VECTOR__"); 1230 if (HasP8Crypto) 1231 Builder.defineMacro("__CRYPTO__"); 1232 if (HasHTM) 1233 Builder.defineMacro("__HTM__"); 1234 if (getTriple().getArch() == llvm::Triple::ppc64le || 1235 (defs & ArchDefinePwr8) || (CPU == "pwr8")) { 1236 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1237 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1238 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1239 if (PointerWidth == 64) 1240 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1241 } 1242 1243 // FIXME: The following are not yet generated here by Clang, but are 1244 // generated by GCC: 1245 // 1246 // _SOFT_FLOAT_ 1247 // __RECIP_PRECISION__ 1248 // __APPLE_ALTIVEC__ 1249 // __RECIP__ 1250 // __RECIPF__ 1251 // __RSQRTE__ 1252 // __RSQRTEF__ 1253 // _SOFT_DOUBLE_ 1254 // __NO_LWSYNC__ 1255 // __HAVE_BSWAP__ 1256 // __LONGDOUBLE128 1257 // __CMODEL_MEDIUM__ 1258 // __CMODEL_LARGE__ 1259 // _CALL_SYSV 1260 // _CALL_DARWIN 1261 // __NO_FPRS__ 1262 } 1263 1264 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1265 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1266 .Case("7400", true) 1267 .Case("g4", true) 1268 .Case("7450", true) 1269 .Case("g4+", true) 1270 .Case("970", true) 1271 .Case("g5", true) 1272 .Case("pwr6", true) 1273 .Case("pwr7", true) 1274 .Case("pwr8", true) 1275 .Case("ppc64", true) 1276 .Case("ppc64le", true) 1277 .Default(false); 1278 1279 Features["qpx"] = (CPU == "a2q"); 1280 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1281 .Case("ppc64le", true) 1282 .Case("pwr8", true) 1283 .Default(false); 1284 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1285 .Case("ppc64le", true) 1286 .Case("pwr8", true) 1287 .Default(false); 1288 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1289 .Case("ppc64le", true) 1290 .Case("pwr8", true) 1291 .Case("pwr7", true) 1292 .Default(false); 1293 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1294 .Case("ppc64le", true) 1295 .Case("pwr8", true) 1296 .Case("pwr7", true) 1297 .Default(false); 1298 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1299 .Case("ppc64le", true) 1300 .Case("pwr8", true) 1301 .Default(false); 1302 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1303 .Case("ppc64le", true) 1304 .Case("pwr8", true) 1305 .Case("pwr7", true) 1306 .Default(false); 1307 } 1308 1309 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1310 return llvm::StringSwitch<bool>(Feature) 1311 .Case("powerpc", true) 1312 .Case("vsx", HasVSX) 1313 .Case("power8-vector", HasP8Vector) 1314 .Case("crypto", HasP8Crypto) 1315 .Case("direct-move", HasDirectMove) 1316 .Case("qpx", HasQPX) 1317 .Case("htm", HasHTM) 1318 .Case("bpermd", HasBPERMD) 1319 .Case("extdiv", HasExtDiv) 1320 .Default(false); 1321 } 1322 1323 /* There is no clear way for the target to know which of the features in the 1324 final feature vector came from defaults and which are actually specified by 1325 the user. To that end, we use the fact that this function is not called on 1326 default features - only user specified ones. By the first time this 1327 function is called, the default features are populated. 1328 We then keep track of the features that the user specified so that we 1329 can ensure we do not override a user's request (only defaults). 1330 For example: 1331 -mcpu=pwr8 -mno-vsx (should disable vsx and everything that depends on it) 1332 -mcpu=pwr8 -mdirect-move -mno-vsx (should actually be diagnosed) 1333 1334 NOTE: Do not call this from PPCTargetInfo::getDefaultFeatures 1335 */ 1336 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1337 StringRef Name, bool Enabled) const { 1338 static llvm::StringMap<bool> ExplicitFeatures; 1339 ExplicitFeatures[Name] = Enabled; 1340 1341 // At this point, -mno-vsx turns off the dependent features but we respect 1342 // the user's requests. 1343 if (!Enabled && Name == "vsx") { 1344 Features["direct-move"] = ExplicitFeatures["direct-move"]; 1345 Features["power8-vector"] = ExplicitFeatures["power8-vector"]; 1346 } 1347 if ((Enabled && Name == "power8-vector") || 1348 (Enabled && Name == "direct-move")) { 1349 if (ExplicitFeatures.find("vsx") == ExplicitFeatures.end()) { 1350 Features["vsx"] = true; 1351 } 1352 } 1353 Features[Name] = Enabled; 1354 } 1355 1356 const char * const PPCTargetInfo::GCCRegNames[] = { 1357 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1358 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1359 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1360 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1361 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1362 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1363 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1364 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1365 "mq", "lr", "ctr", "ap", 1366 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1367 "xer", 1368 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1369 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1370 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1371 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1372 "vrsave", "vscr", 1373 "spe_acc", "spefscr", 1374 "sfp" 1375 }; 1376 1377 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1378 unsigned &NumNames) const { 1379 Names = GCCRegNames; 1380 NumNames = llvm::array_lengthof(GCCRegNames); 1381 } 1382 1383 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1384 // While some of these aliases do map to different registers 1385 // they still share the same register name. 1386 { { "0" }, "r0" }, 1387 { { "1"}, "r1" }, 1388 { { "2" }, "r2" }, 1389 { { "3" }, "r3" }, 1390 { { "4" }, "r4" }, 1391 { { "5" }, "r5" }, 1392 { { "6" }, "r6" }, 1393 { { "7" }, "r7" }, 1394 { { "8" }, "r8" }, 1395 { { "9" }, "r9" }, 1396 { { "10" }, "r10" }, 1397 { { "11" }, "r11" }, 1398 { { "12" }, "r12" }, 1399 { { "13" }, "r13" }, 1400 { { "14" }, "r14" }, 1401 { { "15" }, "r15" }, 1402 { { "16" }, "r16" }, 1403 { { "17" }, "r17" }, 1404 { { "18" }, "r18" }, 1405 { { "19" }, "r19" }, 1406 { { "20" }, "r20" }, 1407 { { "21" }, "r21" }, 1408 { { "22" }, "r22" }, 1409 { { "23" }, "r23" }, 1410 { { "24" }, "r24" }, 1411 { { "25" }, "r25" }, 1412 { { "26" }, "r26" }, 1413 { { "27" }, "r27" }, 1414 { { "28" }, "r28" }, 1415 { { "29" }, "r29" }, 1416 { { "30" }, "r30" }, 1417 { { "31" }, "r31" }, 1418 { { "fr0" }, "f0" }, 1419 { { "fr1" }, "f1" }, 1420 { { "fr2" }, "f2" }, 1421 { { "fr3" }, "f3" }, 1422 { { "fr4" }, "f4" }, 1423 { { "fr5" }, "f5" }, 1424 { { "fr6" }, "f6" }, 1425 { { "fr7" }, "f7" }, 1426 { { "fr8" }, "f8" }, 1427 { { "fr9" }, "f9" }, 1428 { { "fr10" }, "f10" }, 1429 { { "fr11" }, "f11" }, 1430 { { "fr12" }, "f12" }, 1431 { { "fr13" }, "f13" }, 1432 { { "fr14" }, "f14" }, 1433 { { "fr15" }, "f15" }, 1434 { { "fr16" }, "f16" }, 1435 { { "fr17" }, "f17" }, 1436 { { "fr18" }, "f18" }, 1437 { { "fr19" }, "f19" }, 1438 { { "fr20" }, "f20" }, 1439 { { "fr21" }, "f21" }, 1440 { { "fr22" }, "f22" }, 1441 { { "fr23" }, "f23" }, 1442 { { "fr24" }, "f24" }, 1443 { { "fr25" }, "f25" }, 1444 { { "fr26" }, "f26" }, 1445 { { "fr27" }, "f27" }, 1446 { { "fr28" }, "f28" }, 1447 { { "fr29" }, "f29" }, 1448 { { "fr30" }, "f30" }, 1449 { { "fr31" }, "f31" }, 1450 { { "cc" }, "cr0" }, 1451 }; 1452 1453 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1454 unsigned &NumAliases) const { 1455 Aliases = GCCRegAliases; 1456 NumAliases = llvm::array_lengthof(GCCRegAliases); 1457 } 1458 1459 class PPC32TargetInfo : public PPCTargetInfo { 1460 public: 1461 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1462 DescriptionString = "E-m:e-p:32:32-i64:64-n32"; 1463 1464 switch (getTriple().getOS()) { 1465 case llvm::Triple::Linux: 1466 case llvm::Triple::FreeBSD: 1467 case llvm::Triple::NetBSD: 1468 SizeType = UnsignedInt; 1469 PtrDiffType = SignedInt; 1470 IntPtrType = SignedInt; 1471 break; 1472 default: 1473 break; 1474 } 1475 1476 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1477 LongDoubleWidth = LongDoubleAlign = 64; 1478 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1479 } 1480 1481 // PPC32 supports atomics up to 4 bytes. 1482 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1483 } 1484 1485 BuiltinVaListKind getBuiltinVaListKind() const override { 1486 // This is the ELF definition, and is overridden by the Darwin sub-target 1487 return TargetInfo::PowerABIBuiltinVaList; 1488 } 1489 }; 1490 1491 // Note: ABI differences may eventually require us to have a separate 1492 // TargetInfo for little endian. 1493 class PPC64TargetInfo : public PPCTargetInfo { 1494 public: 1495 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1496 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1497 IntMaxType = SignedLong; 1498 Int64Type = SignedLong; 1499 1500 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1501 DescriptionString = "e-m:e-i64:64-n32:64"; 1502 ABI = "elfv2"; 1503 } else { 1504 DescriptionString = "E-m:e-i64:64-n32:64"; 1505 ABI = "elfv1"; 1506 } 1507 1508 switch (getTriple().getOS()) { 1509 case llvm::Triple::FreeBSD: 1510 LongDoubleWidth = LongDoubleAlign = 64; 1511 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1512 break; 1513 case llvm::Triple::NetBSD: 1514 IntMaxType = SignedLongLong; 1515 Int64Type = SignedLongLong; 1516 break; 1517 default: 1518 break; 1519 } 1520 1521 // PPC64 supports atomics up to 8 bytes. 1522 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1523 } 1524 BuiltinVaListKind getBuiltinVaListKind() const override { 1525 return TargetInfo::CharPtrBuiltinVaList; 1526 } 1527 // PPC64 Linux-specific ABI options. 1528 bool setABI(const std::string &Name) override { 1529 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1530 ABI = Name; 1531 return true; 1532 } 1533 return false; 1534 } 1535 }; 1536 1537 class DarwinPPC32TargetInfo : 1538 public DarwinTargetInfo<PPC32TargetInfo> { 1539 public: 1540 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1541 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1542 HasAlignMac68kSupport = true; 1543 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1544 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1545 LongLongAlign = 32; 1546 SuitableAlign = 128; 1547 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; 1548 } 1549 BuiltinVaListKind getBuiltinVaListKind() const override { 1550 return TargetInfo::CharPtrBuiltinVaList; 1551 } 1552 }; 1553 1554 class DarwinPPC64TargetInfo : 1555 public DarwinTargetInfo<PPC64TargetInfo> { 1556 public: 1557 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1558 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1559 HasAlignMac68kSupport = true; 1560 SuitableAlign = 128; 1561 DescriptionString = "E-m:o-i64:64-n32:64"; 1562 } 1563 }; 1564 1565 static const unsigned NVPTXAddrSpaceMap[] = { 1566 1, // opencl_global 1567 3, // opencl_local 1568 4, // opencl_constant 1569 // FIXME: generic has to be added to the target 1570 0, // opencl_generic 1571 1, // cuda_device 1572 4, // cuda_constant 1573 3, // cuda_shared 1574 }; 1575 class NVPTXTargetInfo : public TargetInfo { 1576 static const char * const GCCRegNames[]; 1577 static const Builtin::Info BuiltinInfo[]; 1578 1579 // The GPU profiles supported by the NVPTX backend 1580 enum GPUKind { 1581 GK_NONE, 1582 GK_SM20, 1583 GK_SM21, 1584 GK_SM30, 1585 GK_SM35, 1586 GK_SM37, 1587 } GPU; 1588 1589 public: 1590 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1591 BigEndian = false; 1592 TLSSupported = false; 1593 LongWidth = LongAlign = 64; 1594 AddrSpaceMap = &NVPTXAddrSpaceMap; 1595 UseAddrSpaceMapMangling = true; 1596 // Define available target features 1597 // These must be defined in sorted order! 1598 NoAsmVariants = true; 1599 // Set the default GPU to sm20 1600 GPU = GK_SM20; 1601 } 1602 void getTargetDefines(const LangOptions &Opts, 1603 MacroBuilder &Builder) const override { 1604 Builder.defineMacro("__PTX__"); 1605 Builder.defineMacro("__NVPTX__"); 1606 if (Opts.CUDAIsDevice) { 1607 // Set __CUDA_ARCH__ for the GPU specified. 1608 std::string CUDAArchCode; 1609 switch (GPU) { 1610 case GK_SM20: 1611 CUDAArchCode = "200"; 1612 break; 1613 case GK_SM21: 1614 CUDAArchCode = "210"; 1615 break; 1616 case GK_SM30: 1617 CUDAArchCode = "300"; 1618 break; 1619 case GK_SM35: 1620 CUDAArchCode = "350"; 1621 break; 1622 case GK_SM37: 1623 CUDAArchCode = "370"; 1624 break; 1625 default: 1626 llvm_unreachable("Unhandled target CPU"); 1627 } 1628 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1629 } 1630 } 1631 void getTargetBuiltins(const Builtin::Info *&Records, 1632 unsigned &NumRecords) const override { 1633 Records = BuiltinInfo; 1634 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1635 } 1636 bool hasFeature(StringRef Feature) const override { 1637 return Feature == "ptx" || Feature == "nvptx"; 1638 } 1639 1640 void getGCCRegNames(const char * const *&Names, 1641 unsigned &NumNames) const override; 1642 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1643 unsigned &NumAliases) const override { 1644 // No aliases. 1645 Aliases = nullptr; 1646 NumAliases = 0; 1647 } 1648 bool 1649 validateAsmConstraint(const char *&Name, 1650 TargetInfo::ConstraintInfo &Info) const override { 1651 switch (*Name) { 1652 default: return false; 1653 case 'c': 1654 case 'h': 1655 case 'r': 1656 case 'l': 1657 case 'f': 1658 case 'd': 1659 Info.setAllowsRegister(); 1660 return true; 1661 } 1662 } 1663 const char *getClobbers() const override { 1664 // FIXME: Is this really right? 1665 return ""; 1666 } 1667 BuiltinVaListKind getBuiltinVaListKind() const override { 1668 // FIXME: implement 1669 return TargetInfo::CharPtrBuiltinVaList; 1670 } 1671 bool setCPU(const std::string &Name) override { 1672 GPU = llvm::StringSwitch<GPUKind>(Name) 1673 .Case("sm_20", GK_SM20) 1674 .Case("sm_21", GK_SM21) 1675 .Case("sm_30", GK_SM30) 1676 .Case("sm_35", GK_SM35) 1677 .Case("sm_37", GK_SM37) 1678 .Default(GK_NONE); 1679 1680 return GPU != GK_NONE; 1681 } 1682 }; 1683 1684 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1685 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1686 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1687 ALL_LANGUAGES }, 1688 #include "clang/Basic/BuiltinsNVPTX.def" 1689 }; 1690 1691 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1692 "r0" 1693 }; 1694 1695 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1696 unsigned &NumNames) const { 1697 Names = GCCRegNames; 1698 NumNames = llvm::array_lengthof(GCCRegNames); 1699 } 1700 1701 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1702 public: 1703 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1704 PointerWidth = PointerAlign = 32; 1705 SizeType = TargetInfo::UnsignedInt; 1706 PtrDiffType = TargetInfo::SignedInt; 1707 IntPtrType = TargetInfo::SignedInt; 1708 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1709 } 1710 }; 1711 1712 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1713 public: 1714 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1715 PointerWidth = PointerAlign = 64; 1716 SizeType = TargetInfo::UnsignedLong; 1717 PtrDiffType = TargetInfo::SignedLong; 1718 IntPtrType = TargetInfo::SignedLong; 1719 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1720 } 1721 }; 1722 1723 static const unsigned AMDGPUAddrSpaceMap[] = { 1724 1, // opencl_global 1725 3, // opencl_local 1726 2, // opencl_constant 1727 4, // opencl_generic 1728 1, // cuda_device 1729 2, // cuda_constant 1730 3 // cuda_shared 1731 }; 1732 1733 // If you edit the description strings, make sure you update 1734 // getPointerWidthV(). 1735 1736 static const char *DescriptionStringR600 = 1737 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1738 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1739 1740 static const char *DescriptionStringR600DoubleOps = 1741 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1742 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1743 1744 static const char *DescriptionStringSI = 1745 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1746 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1747 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1748 1749 class AMDGPUTargetInfo : public TargetInfo { 1750 static const Builtin::Info BuiltinInfo[]; 1751 static const char * const GCCRegNames[]; 1752 1753 /// \brief The GPU profiles supported by the AMDGPU target. 1754 enum GPUKind { 1755 GK_NONE, 1756 GK_R600, 1757 GK_R600_DOUBLE_OPS, 1758 GK_R700, 1759 GK_R700_DOUBLE_OPS, 1760 GK_EVERGREEN, 1761 GK_EVERGREEN_DOUBLE_OPS, 1762 GK_NORTHERN_ISLANDS, 1763 GK_CAYMAN, 1764 GK_SOUTHERN_ISLANDS, 1765 GK_SEA_ISLANDS, 1766 GK_VOLCANIC_ISLANDS 1767 } GPU; 1768 1769 bool hasFP64:1; 1770 bool hasFMAF:1; 1771 bool hasLDEXPF:1; 1772 1773 public: 1774 AMDGPUTargetInfo(const llvm::Triple &Triple) 1775 : TargetInfo(Triple) { 1776 1777 if (Triple.getArch() == llvm::Triple::amdgcn) { 1778 DescriptionString = DescriptionStringSI; 1779 GPU = GK_SOUTHERN_ISLANDS; 1780 hasFP64 = true; 1781 hasFMAF = true; 1782 hasLDEXPF = true; 1783 } else { 1784 DescriptionString = DescriptionStringR600; 1785 GPU = GK_R600; 1786 hasFP64 = false; 1787 hasFMAF = false; 1788 hasLDEXPF = false; 1789 } 1790 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1791 UseAddrSpaceMapMangling = true; 1792 } 1793 1794 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1795 if (GPU <= GK_CAYMAN) 1796 return 32; 1797 1798 switch(AddrSpace) { 1799 default: 1800 return 64; 1801 case 0: 1802 case 3: 1803 case 5: 1804 return 32; 1805 } 1806 } 1807 1808 const char * getClobbers() const override { 1809 return ""; 1810 } 1811 1812 void getGCCRegNames(const char * const *&Names, 1813 unsigned &NumNames) const override; 1814 1815 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1816 unsigned &NumAliases) const override { 1817 Aliases = nullptr; 1818 NumAliases = 0; 1819 } 1820 1821 bool validateAsmConstraint(const char *&Name, 1822 TargetInfo::ConstraintInfo &info) const override { 1823 return true; 1824 } 1825 1826 void getTargetBuiltins(const Builtin::Info *&Records, 1827 unsigned &NumRecords) const override { 1828 Records = BuiltinInfo; 1829 NumRecords = clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin; 1830 } 1831 1832 void getTargetDefines(const LangOptions &Opts, 1833 MacroBuilder &Builder) const override { 1834 Builder.defineMacro("__R600__"); 1835 if (hasFMAF) 1836 Builder.defineMacro("__HAS_FMAF__"); 1837 if (hasLDEXPF) 1838 Builder.defineMacro("__HAS_LDEXPF__"); 1839 if (hasFP64 && Opts.OpenCL) 1840 Builder.defineMacro("cl_khr_fp64"); 1841 if (Opts.OpenCL) { 1842 if (GPU >= GK_NORTHERN_ISLANDS) { 1843 Builder.defineMacro("cl_khr_byte_addressable_store"); 1844 Builder.defineMacro("cl_khr_global_int32_base_atomics"); 1845 Builder.defineMacro("cl_khr_global_int32_extended_atomics"); 1846 Builder.defineMacro("cl_khr_local_int32_base_atomics"); 1847 Builder.defineMacro("cl_khr_local_int32_extended_atomics"); 1848 } 1849 } 1850 } 1851 1852 BuiltinVaListKind getBuiltinVaListKind() const override { 1853 return TargetInfo::CharPtrBuiltinVaList; 1854 } 1855 1856 bool setCPU(const std::string &Name) override { 1857 GPU = llvm::StringSwitch<GPUKind>(Name) 1858 .Case("r600" , GK_R600) 1859 .Case("rv610", GK_R600) 1860 .Case("rv620", GK_R600) 1861 .Case("rv630", GK_R600) 1862 .Case("rv635", GK_R600) 1863 .Case("rs780", GK_R600) 1864 .Case("rs880", GK_R600) 1865 .Case("rv670", GK_R600_DOUBLE_OPS) 1866 .Case("rv710", GK_R700) 1867 .Case("rv730", GK_R700) 1868 .Case("rv740", GK_R700_DOUBLE_OPS) 1869 .Case("rv770", GK_R700_DOUBLE_OPS) 1870 .Case("palm", GK_EVERGREEN) 1871 .Case("cedar", GK_EVERGREEN) 1872 .Case("sumo", GK_EVERGREEN) 1873 .Case("sumo2", GK_EVERGREEN) 1874 .Case("redwood", GK_EVERGREEN) 1875 .Case("juniper", GK_EVERGREEN) 1876 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1877 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1878 .Case("barts", GK_NORTHERN_ISLANDS) 1879 .Case("turks", GK_NORTHERN_ISLANDS) 1880 .Case("caicos", GK_NORTHERN_ISLANDS) 1881 .Case("cayman", GK_CAYMAN) 1882 .Case("aruba", GK_CAYMAN) 1883 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1884 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1885 .Case("verde", GK_SOUTHERN_ISLANDS) 1886 .Case("oland", GK_SOUTHERN_ISLANDS) 1887 .Case("hainan", GK_SOUTHERN_ISLANDS) 1888 .Case("bonaire", GK_SEA_ISLANDS) 1889 .Case("kabini", GK_SEA_ISLANDS) 1890 .Case("kaveri", GK_SEA_ISLANDS) 1891 .Case("hawaii", GK_SEA_ISLANDS) 1892 .Case("mullins", GK_SEA_ISLANDS) 1893 .Case("tonga", GK_VOLCANIC_ISLANDS) 1894 .Case("iceland", GK_VOLCANIC_ISLANDS) 1895 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1896 .Default(GK_NONE); 1897 1898 if (GPU == GK_NONE) { 1899 return false; 1900 } 1901 1902 // Set the correct data layout 1903 switch (GPU) { 1904 case GK_NONE: 1905 case GK_R600: 1906 case GK_R700: 1907 case GK_EVERGREEN: 1908 case GK_NORTHERN_ISLANDS: 1909 DescriptionString = DescriptionStringR600; 1910 hasFP64 = false; 1911 hasFMAF = false; 1912 hasLDEXPF = false; 1913 break; 1914 case GK_R600_DOUBLE_OPS: 1915 case GK_R700_DOUBLE_OPS: 1916 case GK_EVERGREEN_DOUBLE_OPS: 1917 case GK_CAYMAN: 1918 DescriptionString = DescriptionStringR600DoubleOps; 1919 hasFP64 = true; 1920 hasFMAF = true; 1921 hasLDEXPF = false; 1922 break; 1923 case GK_SOUTHERN_ISLANDS: 1924 case GK_SEA_ISLANDS: 1925 case GK_VOLCANIC_ISLANDS: 1926 DescriptionString = DescriptionStringSI; 1927 hasFP64 = true; 1928 hasFMAF = true; 1929 hasLDEXPF = true; 1930 break; 1931 } 1932 1933 return true; 1934 } 1935 }; 1936 1937 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1938 #define BUILTIN(ID, TYPE, ATTRS) \ 1939 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1940 #include "clang/Basic/BuiltinsAMDGPU.def" 1941 }; 1942 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1943 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1944 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1945 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1946 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1947 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1948 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1949 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1950 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1951 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1952 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1953 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1954 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1955 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1956 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1957 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1958 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1959 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1960 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1961 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1962 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 1963 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 1964 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 1965 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 1966 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 1967 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 1968 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 1969 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 1970 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 1971 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 1972 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 1973 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 1974 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 1975 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 1976 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 1977 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 1978 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 1979 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 1980 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 1981 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 1982 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 1983 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 1984 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 1985 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 1986 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 1987 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 1988 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 1989 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 1990 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127" 1991 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi", 1992 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi" 1993 }; 1994 1995 void AMDGPUTargetInfo::getGCCRegNames(const char * const *&Names, 1996 unsigned &NumNames) const { 1997 Names = GCCRegNames; 1998 NumNames = llvm::array_lengthof(GCCRegNames); 1999 } 2000 2001 // Namespace for x86 abstract base class 2002 const Builtin::Info BuiltinInfo[] = { 2003 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 2004 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 2005 ALL_LANGUAGES }, 2006 #include "clang/Basic/BuiltinsX86.def" 2007 }; 2008 2009 static const char* const GCCRegNames[] = { 2010 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2011 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2012 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2013 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2014 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2015 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2016 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2017 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2018 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2019 }; 2020 2021 const TargetInfo::AddlRegName AddlRegNames[] = { 2022 { { "al", "ah", "eax", "rax" }, 0 }, 2023 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2024 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2025 { { "dl", "dh", "edx", "rdx" }, 1 }, 2026 { { "esi", "rsi" }, 4 }, 2027 { { "edi", "rdi" }, 5 }, 2028 { { "esp", "rsp" }, 7 }, 2029 { { "ebp", "rbp" }, 6 }, 2030 }; 2031 2032 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2033 // most of the implementation can be shared. 2034 class X86TargetInfo : public TargetInfo { 2035 enum X86SSEEnum { 2036 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2037 } SSELevel; 2038 enum MMX3DNowEnum { 2039 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2040 } MMX3DNowLevel; 2041 enum XOPEnum { 2042 NoXOP, 2043 SSE4A, 2044 FMA4, 2045 XOP 2046 } XOPLevel; 2047 2048 bool HasAES; 2049 bool HasPCLMUL; 2050 bool HasLZCNT; 2051 bool HasRDRND; 2052 bool HasFSGSBASE; 2053 bool HasBMI; 2054 bool HasBMI2; 2055 bool HasPOPCNT; 2056 bool HasRTM; 2057 bool HasPRFCHW; 2058 bool HasRDSEED; 2059 bool HasADX; 2060 bool HasTBM; 2061 bool HasFMA; 2062 bool HasF16C; 2063 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW, 2064 HasAVX512VL; 2065 bool HasSHA; 2066 bool HasCX16; 2067 2068 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2069 /// 2070 /// Each enumeration represents a particular CPU supported by Clang. These 2071 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2072 enum CPUKind { 2073 CK_Generic, 2074 2075 /// \name i386 2076 /// i386-generation processors. 2077 //@{ 2078 CK_i386, 2079 //@} 2080 2081 /// \name i486 2082 /// i486-generation processors. 2083 //@{ 2084 CK_i486, 2085 CK_WinChipC6, 2086 CK_WinChip2, 2087 CK_C3, 2088 //@} 2089 2090 /// \name i586 2091 /// i586-generation processors, P5 microarchitecture based. 2092 //@{ 2093 CK_i586, 2094 CK_Pentium, 2095 CK_PentiumMMX, 2096 //@} 2097 2098 /// \name i686 2099 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2100 //@{ 2101 CK_i686, 2102 CK_PentiumPro, 2103 CK_Pentium2, 2104 CK_Pentium3, 2105 CK_Pentium3M, 2106 CK_PentiumM, 2107 CK_C3_2, 2108 2109 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2110 /// Clang however has some logic to suport this. 2111 // FIXME: Warn, deprecate, and potentially remove this. 2112 CK_Yonah, 2113 //@} 2114 2115 /// \name Netburst 2116 /// Netburst microarchitecture based processors. 2117 //@{ 2118 CK_Pentium4, 2119 CK_Pentium4M, 2120 CK_Prescott, 2121 CK_Nocona, 2122 //@} 2123 2124 /// \name Core 2125 /// Core microarchitecture based processors. 2126 //@{ 2127 CK_Core2, 2128 2129 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2130 /// codename which GCC no longer accepts as an option to -march, but Clang 2131 /// has some logic for recognizing it. 2132 // FIXME: Warn, deprecate, and potentially remove this. 2133 CK_Penryn, 2134 //@} 2135 2136 /// \name Atom 2137 /// Atom processors 2138 //@{ 2139 CK_Bonnell, 2140 CK_Silvermont, 2141 //@} 2142 2143 /// \name Nehalem 2144 /// Nehalem microarchitecture based processors. 2145 CK_Nehalem, 2146 2147 /// \name Westmere 2148 /// Westmere microarchitecture based processors. 2149 CK_Westmere, 2150 2151 /// \name Sandy Bridge 2152 /// Sandy Bridge microarchitecture based processors. 2153 CK_SandyBridge, 2154 2155 /// \name Ivy Bridge 2156 /// Ivy Bridge microarchitecture based processors. 2157 CK_IvyBridge, 2158 2159 /// \name Haswell 2160 /// Haswell microarchitecture based processors. 2161 CK_Haswell, 2162 2163 /// \name Broadwell 2164 /// Broadwell microarchitecture based processors. 2165 CK_Broadwell, 2166 2167 /// \name Skylake 2168 /// Skylake microarchitecture based processors. 2169 CK_Skylake, 2170 2171 /// \name Knights Landing 2172 /// Knights Landing processor. 2173 CK_KNL, 2174 2175 /// \name K6 2176 /// K6 architecture processors. 2177 //@{ 2178 CK_K6, 2179 CK_K6_2, 2180 CK_K6_3, 2181 //@} 2182 2183 /// \name K7 2184 /// K7 architecture processors. 2185 //@{ 2186 CK_Athlon, 2187 CK_AthlonThunderbird, 2188 CK_Athlon4, 2189 CK_AthlonXP, 2190 CK_AthlonMP, 2191 //@} 2192 2193 /// \name K8 2194 /// K8 architecture processors. 2195 //@{ 2196 CK_Athlon64, 2197 CK_Athlon64SSE3, 2198 CK_AthlonFX, 2199 CK_K8, 2200 CK_K8SSE3, 2201 CK_Opteron, 2202 CK_OpteronSSE3, 2203 CK_AMDFAM10, 2204 //@} 2205 2206 /// \name Bobcat 2207 /// Bobcat architecture processors. 2208 //@{ 2209 CK_BTVER1, 2210 CK_BTVER2, 2211 //@} 2212 2213 /// \name Bulldozer 2214 /// Bulldozer architecture processors. 2215 //@{ 2216 CK_BDVER1, 2217 CK_BDVER2, 2218 CK_BDVER3, 2219 CK_BDVER4, 2220 //@} 2221 2222 /// This specification is deprecated and will be removed in the future. 2223 /// Users should prefer \see CK_K8. 2224 // FIXME: Warn on this when the CPU is set to it. 2225 //@{ 2226 CK_x86_64, 2227 //@} 2228 2229 /// \name Geode 2230 /// Geode processors. 2231 //@{ 2232 CK_Geode 2233 //@} 2234 } CPU; 2235 2236 enum FPMathKind { 2237 FP_Default, 2238 FP_SSE, 2239 FP_387 2240 } FPMath; 2241 2242 public: 2243 X86TargetInfo(const llvm::Triple &Triple) 2244 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 2245 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 2246 HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false), 2247 HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false), 2248 HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false), 2249 HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false), 2250 HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false), 2251 HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) { 2252 BigEndian = false; 2253 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2254 } 2255 unsigned getFloatEvalMethod() const override { 2256 // X87 evaluates with 80 bits "long double" precision. 2257 return SSELevel == NoSSE ? 2 : 0; 2258 } 2259 void getTargetBuiltins(const Builtin::Info *&Records, 2260 unsigned &NumRecords) const override { 2261 Records = BuiltinInfo; 2262 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 2263 } 2264 void getGCCRegNames(const char * const *&Names, 2265 unsigned &NumNames) const override { 2266 Names = GCCRegNames; 2267 NumNames = llvm::array_lengthof(GCCRegNames); 2268 } 2269 void getGCCRegAliases(const GCCRegAlias *&Aliases, 2270 unsigned &NumAliases) const override { 2271 Aliases = nullptr; 2272 NumAliases = 0; 2273 } 2274 void getGCCAddlRegNames(const AddlRegName *&Names, 2275 unsigned &NumNames) const override { 2276 Names = AddlRegNames; 2277 NumNames = llvm::array_lengthof(AddlRegNames); 2278 } 2279 bool validateCpuSupports(StringRef Name) const override; 2280 bool validateAsmConstraint(const char *&Name, 2281 TargetInfo::ConstraintInfo &info) const override; 2282 2283 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2284 2285 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2286 2287 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2288 2289 std::string convertConstraint(const char *&Constraint) const override; 2290 const char *getClobbers() const override { 2291 return "~{dirflag},~{fpsr},~{flags}"; 2292 } 2293 void getTargetDefines(const LangOptions &Opts, 2294 MacroBuilder &Builder) const override; 2295 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2296 bool Enabled); 2297 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2298 bool Enabled); 2299 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2300 bool Enabled); 2301 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2302 StringRef Name, bool Enabled) const override { 2303 setFeatureEnabledImpl(Features, Name, Enabled); 2304 } 2305 // This exists purely to cut down on the number of virtual calls in 2306 // getDefaultFeatures which calls this repeatedly. 2307 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2308 StringRef Name, bool Enabled); 2309 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 2310 bool hasFeature(StringRef Feature) const override; 2311 bool handleTargetFeatures(std::vector<std::string> &Features, 2312 DiagnosticsEngine &Diags) override; 2313 StringRef getABI() const override { 2314 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2315 return "avx512"; 2316 else if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2317 return "avx"; 2318 else if (getTriple().getArch() == llvm::Triple::x86 && 2319 MMX3DNowLevel == NoMMX3DNow) 2320 return "no-mmx"; 2321 return ""; 2322 } 2323 bool setCPU(const std::string &Name) override { 2324 CPU = llvm::StringSwitch<CPUKind>(Name) 2325 .Case("i386", CK_i386) 2326 .Case("i486", CK_i486) 2327 .Case("winchip-c6", CK_WinChipC6) 2328 .Case("winchip2", CK_WinChip2) 2329 .Case("c3", CK_C3) 2330 .Case("i586", CK_i586) 2331 .Case("pentium", CK_Pentium) 2332 .Case("pentium-mmx", CK_PentiumMMX) 2333 .Case("i686", CK_i686) 2334 .Case("pentiumpro", CK_PentiumPro) 2335 .Case("pentium2", CK_Pentium2) 2336 .Case("pentium3", CK_Pentium3) 2337 .Case("pentium3m", CK_Pentium3M) 2338 .Case("pentium-m", CK_PentiumM) 2339 .Case("c3-2", CK_C3_2) 2340 .Case("yonah", CK_Yonah) 2341 .Case("pentium4", CK_Pentium4) 2342 .Case("pentium4m", CK_Pentium4M) 2343 .Case("prescott", CK_Prescott) 2344 .Case("nocona", CK_Nocona) 2345 .Case("core2", CK_Core2) 2346 .Case("penryn", CK_Penryn) 2347 .Case("bonnell", CK_Bonnell) 2348 .Case("atom", CK_Bonnell) // Legacy name. 2349 .Case("silvermont", CK_Silvermont) 2350 .Case("slm", CK_Silvermont) // Legacy name. 2351 .Case("nehalem", CK_Nehalem) 2352 .Case("corei7", CK_Nehalem) // Legacy name. 2353 .Case("westmere", CK_Westmere) 2354 .Case("sandybridge", CK_SandyBridge) 2355 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2356 .Case("ivybridge", CK_IvyBridge) 2357 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2358 .Case("haswell", CK_Haswell) 2359 .Case("core-avx2", CK_Haswell) // Legacy name. 2360 .Case("broadwell", CK_Broadwell) 2361 .Case("skylake", CK_Skylake) 2362 .Case("skx", CK_Skylake) // Legacy name. 2363 .Case("knl", CK_KNL) 2364 .Case("k6", CK_K6) 2365 .Case("k6-2", CK_K6_2) 2366 .Case("k6-3", CK_K6_3) 2367 .Case("athlon", CK_Athlon) 2368 .Case("athlon-tbird", CK_AthlonThunderbird) 2369 .Case("athlon-4", CK_Athlon4) 2370 .Case("athlon-xp", CK_AthlonXP) 2371 .Case("athlon-mp", CK_AthlonMP) 2372 .Case("athlon64", CK_Athlon64) 2373 .Case("athlon64-sse3", CK_Athlon64SSE3) 2374 .Case("athlon-fx", CK_AthlonFX) 2375 .Case("k8", CK_K8) 2376 .Case("k8-sse3", CK_K8SSE3) 2377 .Case("opteron", CK_Opteron) 2378 .Case("opteron-sse3", CK_OpteronSSE3) 2379 .Case("barcelona", CK_AMDFAM10) 2380 .Case("amdfam10", CK_AMDFAM10) 2381 .Case("btver1", CK_BTVER1) 2382 .Case("btver2", CK_BTVER2) 2383 .Case("bdver1", CK_BDVER1) 2384 .Case("bdver2", CK_BDVER2) 2385 .Case("bdver3", CK_BDVER3) 2386 .Case("bdver4", CK_BDVER4) 2387 .Case("x86-64", CK_x86_64) 2388 .Case("geode", CK_Geode) 2389 .Default(CK_Generic); 2390 2391 // Perform any per-CPU checks necessary to determine if this CPU is 2392 // acceptable. 2393 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2394 // invalid without explaining *why*. 2395 switch (CPU) { 2396 case CK_Generic: 2397 // No processor selected! 2398 return false; 2399 2400 case CK_i386: 2401 case CK_i486: 2402 case CK_WinChipC6: 2403 case CK_WinChip2: 2404 case CK_C3: 2405 case CK_i586: 2406 case CK_Pentium: 2407 case CK_PentiumMMX: 2408 case CK_i686: 2409 case CK_PentiumPro: 2410 case CK_Pentium2: 2411 case CK_Pentium3: 2412 case CK_Pentium3M: 2413 case CK_PentiumM: 2414 case CK_Yonah: 2415 case CK_C3_2: 2416 case CK_Pentium4: 2417 case CK_Pentium4M: 2418 case CK_Prescott: 2419 case CK_K6: 2420 case CK_K6_2: 2421 case CK_K6_3: 2422 case CK_Athlon: 2423 case CK_AthlonThunderbird: 2424 case CK_Athlon4: 2425 case CK_AthlonXP: 2426 case CK_AthlonMP: 2427 case CK_Geode: 2428 // Only accept certain architectures when compiling in 32-bit mode. 2429 if (getTriple().getArch() != llvm::Triple::x86) 2430 return false; 2431 2432 // Fallthrough 2433 case CK_Nocona: 2434 case CK_Core2: 2435 case CK_Penryn: 2436 case CK_Bonnell: 2437 case CK_Silvermont: 2438 case CK_Nehalem: 2439 case CK_Westmere: 2440 case CK_SandyBridge: 2441 case CK_IvyBridge: 2442 case CK_Haswell: 2443 case CK_Broadwell: 2444 case CK_Skylake: 2445 case CK_KNL: 2446 case CK_Athlon64: 2447 case CK_Athlon64SSE3: 2448 case CK_AthlonFX: 2449 case CK_K8: 2450 case CK_K8SSE3: 2451 case CK_Opteron: 2452 case CK_OpteronSSE3: 2453 case CK_AMDFAM10: 2454 case CK_BTVER1: 2455 case CK_BTVER2: 2456 case CK_BDVER1: 2457 case CK_BDVER2: 2458 case CK_BDVER3: 2459 case CK_BDVER4: 2460 case CK_x86_64: 2461 return true; 2462 } 2463 llvm_unreachable("Unhandled CPU kind"); 2464 } 2465 2466 bool setFPMath(StringRef Name) override; 2467 2468 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2469 // We accept all non-ARM calling conventions 2470 return (CC == CC_X86ThisCall || 2471 CC == CC_X86FastCall || 2472 CC == CC_X86StdCall || 2473 CC == CC_X86VectorCall || 2474 CC == CC_C || 2475 CC == CC_X86Pascal || 2476 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2477 } 2478 2479 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2480 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2481 } 2482 2483 bool hasSjLjLowering() const override { 2484 return true; 2485 } 2486 }; 2487 2488 bool X86TargetInfo::setFPMath(StringRef Name) { 2489 if (Name == "387") { 2490 FPMath = FP_387; 2491 return true; 2492 } 2493 if (Name == "sse") { 2494 FPMath = FP_SSE; 2495 return true; 2496 } 2497 return false; 2498 } 2499 2500 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2501 // FIXME: This *really* should not be here. 2502 2503 // X86_64 always has SSE2. 2504 if (getTriple().getArch() == llvm::Triple::x86_64) 2505 setFeatureEnabledImpl(Features, "sse2", true); 2506 2507 switch (CPU) { 2508 case CK_Generic: 2509 case CK_i386: 2510 case CK_i486: 2511 case CK_i586: 2512 case CK_Pentium: 2513 case CK_i686: 2514 case CK_PentiumPro: 2515 break; 2516 case CK_PentiumMMX: 2517 case CK_Pentium2: 2518 case CK_K6: 2519 case CK_WinChipC6: 2520 setFeatureEnabledImpl(Features, "mmx", true); 2521 break; 2522 case CK_Pentium3: 2523 case CK_Pentium3M: 2524 case CK_C3_2: 2525 setFeatureEnabledImpl(Features, "sse", true); 2526 break; 2527 case CK_PentiumM: 2528 case CK_Pentium4: 2529 case CK_Pentium4M: 2530 case CK_x86_64: 2531 setFeatureEnabledImpl(Features, "sse2", true); 2532 break; 2533 case CK_Yonah: 2534 case CK_Prescott: 2535 case CK_Nocona: 2536 setFeatureEnabledImpl(Features, "sse3", true); 2537 setFeatureEnabledImpl(Features, "cx16", true); 2538 break; 2539 case CK_Core2: 2540 case CK_Bonnell: 2541 setFeatureEnabledImpl(Features, "ssse3", true); 2542 setFeatureEnabledImpl(Features, "cx16", true); 2543 break; 2544 case CK_Penryn: 2545 setFeatureEnabledImpl(Features, "sse4.1", true); 2546 setFeatureEnabledImpl(Features, "cx16", true); 2547 break; 2548 case CK_Skylake: 2549 setFeatureEnabledImpl(Features, "avx512f", true); 2550 setFeatureEnabledImpl(Features, "avx512cd", true); 2551 setFeatureEnabledImpl(Features, "avx512dq", true); 2552 setFeatureEnabledImpl(Features, "avx512bw", true); 2553 setFeatureEnabledImpl(Features, "avx512vl", true); 2554 // FALLTHROUGH 2555 case CK_Broadwell: 2556 setFeatureEnabledImpl(Features, "rdseed", true); 2557 setFeatureEnabledImpl(Features, "adx", true); 2558 // FALLTHROUGH 2559 case CK_Haswell: 2560 setFeatureEnabledImpl(Features, "avx2", true); 2561 setFeatureEnabledImpl(Features, "lzcnt", true); 2562 setFeatureEnabledImpl(Features, "bmi", true); 2563 setFeatureEnabledImpl(Features, "bmi2", true); 2564 setFeatureEnabledImpl(Features, "rtm", true); 2565 setFeatureEnabledImpl(Features, "fma", true); 2566 // FALLTHROUGH 2567 case CK_IvyBridge: 2568 setFeatureEnabledImpl(Features, "rdrnd", true); 2569 setFeatureEnabledImpl(Features, "f16c", true); 2570 setFeatureEnabledImpl(Features, "fsgsbase", true); 2571 // FALLTHROUGH 2572 case CK_SandyBridge: 2573 setFeatureEnabledImpl(Features, "avx", true); 2574 // FALLTHROUGH 2575 case CK_Westmere: 2576 case CK_Silvermont: 2577 setFeatureEnabledImpl(Features, "aes", true); 2578 setFeatureEnabledImpl(Features, "pclmul", true); 2579 // FALLTHROUGH 2580 case CK_Nehalem: 2581 setFeatureEnabledImpl(Features, "sse4.2", true); 2582 setFeatureEnabledImpl(Features, "cx16", true); 2583 break; 2584 case CK_KNL: 2585 setFeatureEnabledImpl(Features, "avx512f", true); 2586 setFeatureEnabledImpl(Features, "avx512cd", true); 2587 setFeatureEnabledImpl(Features, "avx512er", true); 2588 setFeatureEnabledImpl(Features, "avx512pf", true); 2589 setFeatureEnabledImpl(Features, "rdseed", true); 2590 setFeatureEnabledImpl(Features, "adx", true); 2591 setFeatureEnabledImpl(Features, "lzcnt", true); 2592 setFeatureEnabledImpl(Features, "bmi", true); 2593 setFeatureEnabledImpl(Features, "bmi2", true); 2594 setFeatureEnabledImpl(Features, "rtm", true); 2595 setFeatureEnabledImpl(Features, "fma", true); 2596 setFeatureEnabledImpl(Features, "rdrnd", true); 2597 setFeatureEnabledImpl(Features, "f16c", true); 2598 setFeatureEnabledImpl(Features, "fsgsbase", true); 2599 setFeatureEnabledImpl(Features, "aes", true); 2600 setFeatureEnabledImpl(Features, "pclmul", true); 2601 setFeatureEnabledImpl(Features, "cx16", true); 2602 break; 2603 case CK_K6_2: 2604 case CK_K6_3: 2605 case CK_WinChip2: 2606 case CK_C3: 2607 setFeatureEnabledImpl(Features, "3dnow", true); 2608 break; 2609 case CK_Athlon: 2610 case CK_AthlonThunderbird: 2611 case CK_Geode: 2612 setFeatureEnabledImpl(Features, "3dnowa", true); 2613 break; 2614 case CK_Athlon4: 2615 case CK_AthlonXP: 2616 case CK_AthlonMP: 2617 setFeatureEnabledImpl(Features, "sse", true); 2618 setFeatureEnabledImpl(Features, "3dnowa", true); 2619 break; 2620 case CK_K8: 2621 case CK_Opteron: 2622 case CK_Athlon64: 2623 case CK_AthlonFX: 2624 setFeatureEnabledImpl(Features, "sse2", true); 2625 setFeatureEnabledImpl(Features, "3dnowa", true); 2626 break; 2627 case CK_AMDFAM10: 2628 setFeatureEnabledImpl(Features, "sse4a", true); 2629 setFeatureEnabledImpl(Features, "lzcnt", true); 2630 setFeatureEnabledImpl(Features, "popcnt", true); 2631 // FALLTHROUGH 2632 case CK_K8SSE3: 2633 case CK_OpteronSSE3: 2634 case CK_Athlon64SSE3: 2635 setFeatureEnabledImpl(Features, "sse3", true); 2636 setFeatureEnabledImpl(Features, "3dnowa", true); 2637 break; 2638 case CK_BTVER2: 2639 setFeatureEnabledImpl(Features, "avx", true); 2640 setFeatureEnabledImpl(Features, "aes", true); 2641 setFeatureEnabledImpl(Features, "pclmul", true); 2642 setFeatureEnabledImpl(Features, "bmi", true); 2643 setFeatureEnabledImpl(Features, "f16c", true); 2644 // FALLTHROUGH 2645 case CK_BTVER1: 2646 setFeatureEnabledImpl(Features, "ssse3", true); 2647 setFeatureEnabledImpl(Features, "sse4a", true); 2648 setFeatureEnabledImpl(Features, "lzcnt", true); 2649 setFeatureEnabledImpl(Features, "popcnt", true); 2650 setFeatureEnabledImpl(Features, "prfchw", true); 2651 setFeatureEnabledImpl(Features, "cx16", true); 2652 break; 2653 case CK_BDVER4: 2654 setFeatureEnabledImpl(Features, "avx2", true); 2655 setFeatureEnabledImpl(Features, "bmi2", true); 2656 // FALLTHROUGH 2657 case CK_BDVER3: 2658 setFeatureEnabledImpl(Features, "fsgsbase", true); 2659 // FALLTHROUGH 2660 case CK_BDVER2: 2661 setFeatureEnabledImpl(Features, "bmi", true); 2662 setFeatureEnabledImpl(Features, "fma", true); 2663 setFeatureEnabledImpl(Features, "f16c", true); 2664 setFeatureEnabledImpl(Features, "tbm", true); 2665 // FALLTHROUGH 2666 case CK_BDVER1: 2667 // xop implies avx, sse4a and fma4. 2668 setFeatureEnabledImpl(Features, "xop", true); 2669 setFeatureEnabledImpl(Features, "lzcnt", true); 2670 setFeatureEnabledImpl(Features, "aes", true); 2671 setFeatureEnabledImpl(Features, "pclmul", true); 2672 setFeatureEnabledImpl(Features, "prfchw", true); 2673 setFeatureEnabledImpl(Features, "cx16", true); 2674 break; 2675 } 2676 } 2677 2678 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2679 X86SSEEnum Level, bool Enabled) { 2680 if (Enabled) { 2681 switch (Level) { 2682 case AVX512F: 2683 Features["avx512f"] = true; 2684 case AVX2: 2685 Features["avx2"] = true; 2686 case AVX: 2687 Features["avx"] = true; 2688 case SSE42: 2689 Features["sse4.2"] = true; 2690 case SSE41: 2691 Features["sse4.1"] = true; 2692 case SSSE3: 2693 Features["ssse3"] = true; 2694 case SSE3: 2695 Features["sse3"] = true; 2696 case SSE2: 2697 Features["sse2"] = true; 2698 case SSE1: 2699 Features["sse"] = true; 2700 case NoSSE: 2701 break; 2702 } 2703 return; 2704 } 2705 2706 switch (Level) { 2707 case NoSSE: 2708 case SSE1: 2709 Features["sse"] = false; 2710 case SSE2: 2711 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2712 Features["sha"] = false; 2713 case SSE3: 2714 Features["sse3"] = false; 2715 setXOPLevel(Features, NoXOP, false); 2716 case SSSE3: 2717 Features["ssse3"] = false; 2718 case SSE41: 2719 Features["sse4.1"] = false; 2720 case SSE42: 2721 Features["sse4.2"] = false; 2722 case AVX: 2723 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2724 setXOPLevel(Features, FMA4, false); 2725 case AVX2: 2726 Features["avx2"] = false; 2727 case AVX512F: 2728 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2729 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2730 Features["avx512vl"] = false; 2731 } 2732 } 2733 2734 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2735 MMX3DNowEnum Level, bool Enabled) { 2736 if (Enabled) { 2737 switch (Level) { 2738 case AMD3DNowAthlon: 2739 Features["3dnowa"] = true; 2740 case AMD3DNow: 2741 Features["3dnow"] = true; 2742 case MMX: 2743 Features["mmx"] = true; 2744 case NoMMX3DNow: 2745 break; 2746 } 2747 return; 2748 } 2749 2750 switch (Level) { 2751 case NoMMX3DNow: 2752 case MMX: 2753 Features["mmx"] = false; 2754 case AMD3DNow: 2755 Features["3dnow"] = false; 2756 case AMD3DNowAthlon: 2757 Features["3dnowa"] = false; 2758 } 2759 } 2760 2761 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2762 bool Enabled) { 2763 if (Enabled) { 2764 switch (Level) { 2765 case XOP: 2766 Features["xop"] = true; 2767 case FMA4: 2768 Features["fma4"] = true; 2769 setSSELevel(Features, AVX, true); 2770 case SSE4A: 2771 Features["sse4a"] = true; 2772 setSSELevel(Features, SSE3, true); 2773 case NoXOP: 2774 break; 2775 } 2776 return; 2777 } 2778 2779 switch (Level) { 2780 case NoXOP: 2781 case SSE4A: 2782 Features["sse4a"] = false; 2783 case FMA4: 2784 Features["fma4"] = false; 2785 case XOP: 2786 Features["xop"] = false; 2787 } 2788 } 2789 2790 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2791 StringRef Name, bool Enabled) { 2792 // This is a bit of a hack to deal with the sse4 target feature when used 2793 // as part of the target attribute. We handle sse4 correctly everywhere 2794 // else. See below for more information on how we handle the sse4 options. 2795 if (Name != "sse4") 2796 Features[Name] = Enabled; 2797 2798 if (Name == "mmx") { 2799 setMMXLevel(Features, MMX, Enabled); 2800 } else if (Name == "sse") { 2801 setSSELevel(Features, SSE1, Enabled); 2802 } else if (Name == "sse2") { 2803 setSSELevel(Features, SSE2, Enabled); 2804 } else if (Name == "sse3") { 2805 setSSELevel(Features, SSE3, Enabled); 2806 } else if (Name == "ssse3") { 2807 setSSELevel(Features, SSSE3, Enabled); 2808 } else if (Name == "sse4.2") { 2809 setSSELevel(Features, SSE42, Enabled); 2810 } else if (Name == "sse4.1") { 2811 setSSELevel(Features, SSE41, Enabled); 2812 } else if (Name == "3dnow") { 2813 setMMXLevel(Features, AMD3DNow, Enabled); 2814 } else if (Name == "3dnowa") { 2815 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2816 } else if (Name == "aes") { 2817 if (Enabled) 2818 setSSELevel(Features, SSE2, Enabled); 2819 } else if (Name == "pclmul") { 2820 if (Enabled) 2821 setSSELevel(Features, SSE2, Enabled); 2822 } else if (Name == "avx") { 2823 setSSELevel(Features, AVX, Enabled); 2824 } else if (Name == "avx2") { 2825 setSSELevel(Features, AVX2, Enabled); 2826 } else if (Name == "avx512f") { 2827 setSSELevel(Features, AVX512F, Enabled); 2828 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2829 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2830 if (Enabled) 2831 setSSELevel(Features, AVX512F, Enabled); 2832 } else if (Name == "fma") { 2833 if (Enabled) 2834 setSSELevel(Features, AVX, Enabled); 2835 } else if (Name == "fma4") { 2836 setXOPLevel(Features, FMA4, Enabled); 2837 } else if (Name == "xop") { 2838 setXOPLevel(Features, XOP, Enabled); 2839 } else if (Name == "sse4a") { 2840 setXOPLevel(Features, SSE4A, Enabled); 2841 } else if (Name == "f16c") { 2842 if (Enabled) 2843 setSSELevel(Features, AVX, Enabled); 2844 } else if (Name == "sha") { 2845 if (Enabled) 2846 setSSELevel(Features, SSE2, Enabled); 2847 } else if (Name == "sse4") { 2848 // We can get here via the __target__ attribute since that's not controlled 2849 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 2850 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 2851 // disabled. 2852 if (Enabled) 2853 setSSELevel(Features, SSE42, Enabled); 2854 else 2855 setSSELevel(Features, SSE41, Enabled); 2856 } 2857 } 2858 2859 /// handleTargetFeatures - Perform initialization based on the user 2860 /// configured set of features. 2861 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2862 DiagnosticsEngine &Diags) { 2863 // Remember the maximum enabled sselevel. 2864 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2865 // Ignore disabled features. 2866 if (Features[i][0] == '-') 2867 continue; 2868 2869 StringRef Feature = StringRef(Features[i]).substr(1); 2870 2871 if (Feature == "aes") { 2872 HasAES = true; 2873 continue; 2874 } 2875 2876 if (Feature == "pclmul") { 2877 HasPCLMUL = true; 2878 continue; 2879 } 2880 2881 if (Feature == "lzcnt") { 2882 HasLZCNT = true; 2883 continue; 2884 } 2885 2886 if (Feature == "rdrnd") { 2887 HasRDRND = true; 2888 continue; 2889 } 2890 2891 if (Feature == "fsgsbase") { 2892 HasFSGSBASE = true; 2893 continue; 2894 } 2895 2896 if (Feature == "bmi") { 2897 HasBMI = true; 2898 continue; 2899 } 2900 2901 if (Feature == "bmi2") { 2902 HasBMI2 = true; 2903 continue; 2904 } 2905 2906 if (Feature == "popcnt") { 2907 HasPOPCNT = true; 2908 continue; 2909 } 2910 2911 if (Feature == "rtm") { 2912 HasRTM = true; 2913 continue; 2914 } 2915 2916 if (Feature == "prfchw") { 2917 HasPRFCHW = true; 2918 continue; 2919 } 2920 2921 if (Feature == "rdseed") { 2922 HasRDSEED = true; 2923 continue; 2924 } 2925 2926 if (Feature == "adx") { 2927 HasADX = true; 2928 continue; 2929 } 2930 2931 if (Feature == "tbm") { 2932 HasTBM = true; 2933 continue; 2934 } 2935 2936 if (Feature == "fma") { 2937 HasFMA = true; 2938 continue; 2939 } 2940 2941 if (Feature == "f16c") { 2942 HasF16C = true; 2943 continue; 2944 } 2945 2946 if (Feature == "avx512cd") { 2947 HasAVX512CD = true; 2948 continue; 2949 } 2950 2951 if (Feature == "avx512er") { 2952 HasAVX512ER = true; 2953 continue; 2954 } 2955 2956 if (Feature == "avx512pf") { 2957 HasAVX512PF = true; 2958 continue; 2959 } 2960 2961 if (Feature == "avx512dq") { 2962 HasAVX512DQ = true; 2963 continue; 2964 } 2965 2966 if (Feature == "avx512bw") { 2967 HasAVX512BW = true; 2968 continue; 2969 } 2970 2971 if (Feature == "avx512vl") { 2972 HasAVX512VL = true; 2973 continue; 2974 } 2975 2976 if (Feature == "sha") { 2977 HasSHA = true; 2978 continue; 2979 } 2980 2981 if (Feature == "cx16") { 2982 HasCX16 = true; 2983 continue; 2984 } 2985 2986 assert(Features[i][0] == '+' && "Invalid target feature!"); 2987 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2988 .Case("avx512f", AVX512F) 2989 .Case("avx2", AVX2) 2990 .Case("avx", AVX) 2991 .Case("sse4.2", SSE42) 2992 .Case("sse4.1", SSE41) 2993 .Case("ssse3", SSSE3) 2994 .Case("sse3", SSE3) 2995 .Case("sse2", SSE2) 2996 .Case("sse", SSE1) 2997 .Default(NoSSE); 2998 SSELevel = std::max(SSELevel, Level); 2999 3000 MMX3DNowEnum ThreeDNowLevel = 3001 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3002 .Case("3dnowa", AMD3DNowAthlon) 3003 .Case("3dnow", AMD3DNow) 3004 .Case("mmx", MMX) 3005 .Default(NoMMX3DNow); 3006 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3007 3008 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3009 .Case("xop", XOP) 3010 .Case("fma4", FMA4) 3011 .Case("sse4a", SSE4A) 3012 .Default(NoXOP); 3013 XOPLevel = std::max(XOPLevel, XLevel); 3014 } 3015 3016 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3017 // Can't do this earlier because we need to be able to explicitly enable 3018 // popcnt and still disable sse4.2. 3019 if (!HasPOPCNT && SSELevel >= SSE42 && 3020 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 3021 HasPOPCNT = true; 3022 Features.push_back("+popcnt"); 3023 } 3024 3025 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3026 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 3027 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 3028 HasPRFCHW = true; 3029 Features.push_back("+prfchw"); 3030 } 3031 3032 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3033 // matches the selected sse level. 3034 if (FPMath == FP_SSE && SSELevel < SSE1) { 3035 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 3036 return false; 3037 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 3038 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 3039 return false; 3040 } 3041 3042 // Don't tell the backend if we're turning off mmx; it will end up disabling 3043 // SSE, which we don't want. 3044 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3045 // then enable MMX. 3046 std::vector<std::string>::iterator it; 3047 it = std::find(Features.begin(), Features.end(), "-mmx"); 3048 if (it != Features.end()) 3049 Features.erase(it); 3050 else if (SSELevel > NoSSE) 3051 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 3052 3053 SimdDefaultAlign = 3054 (getABI() == "avx512") ? 512 : (getABI() == "avx") ? 256 : 128; 3055 return true; 3056 } 3057 3058 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3059 /// definitions for this particular subtarget. 3060 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3061 MacroBuilder &Builder) const { 3062 // Target identification. 3063 if (getTriple().getArch() == llvm::Triple::x86_64) { 3064 Builder.defineMacro("__amd64__"); 3065 Builder.defineMacro("__amd64"); 3066 Builder.defineMacro("__x86_64"); 3067 Builder.defineMacro("__x86_64__"); 3068 if (getTriple().getArchName() == "x86_64h") { 3069 Builder.defineMacro("__x86_64h"); 3070 Builder.defineMacro("__x86_64h__"); 3071 } 3072 } else { 3073 DefineStd(Builder, "i386", Opts); 3074 } 3075 3076 // Subtarget options. 3077 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3078 // truly should be based on -mtune options. 3079 switch (CPU) { 3080 case CK_Generic: 3081 break; 3082 case CK_i386: 3083 // The rest are coming from the i386 define above. 3084 Builder.defineMacro("__tune_i386__"); 3085 break; 3086 case CK_i486: 3087 case CK_WinChipC6: 3088 case CK_WinChip2: 3089 case CK_C3: 3090 defineCPUMacros(Builder, "i486"); 3091 break; 3092 case CK_PentiumMMX: 3093 Builder.defineMacro("__pentium_mmx__"); 3094 Builder.defineMacro("__tune_pentium_mmx__"); 3095 // Fallthrough 3096 case CK_i586: 3097 case CK_Pentium: 3098 defineCPUMacros(Builder, "i586"); 3099 defineCPUMacros(Builder, "pentium"); 3100 break; 3101 case CK_Pentium3: 3102 case CK_Pentium3M: 3103 case CK_PentiumM: 3104 Builder.defineMacro("__tune_pentium3__"); 3105 // Fallthrough 3106 case CK_Pentium2: 3107 case CK_C3_2: 3108 Builder.defineMacro("__tune_pentium2__"); 3109 // Fallthrough 3110 case CK_PentiumPro: 3111 Builder.defineMacro("__tune_i686__"); 3112 Builder.defineMacro("__tune_pentiumpro__"); 3113 // Fallthrough 3114 case CK_i686: 3115 Builder.defineMacro("__i686"); 3116 Builder.defineMacro("__i686__"); 3117 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3118 Builder.defineMacro("__pentiumpro"); 3119 Builder.defineMacro("__pentiumpro__"); 3120 break; 3121 case CK_Pentium4: 3122 case CK_Pentium4M: 3123 defineCPUMacros(Builder, "pentium4"); 3124 break; 3125 case CK_Yonah: 3126 case CK_Prescott: 3127 case CK_Nocona: 3128 defineCPUMacros(Builder, "nocona"); 3129 break; 3130 case CK_Core2: 3131 case CK_Penryn: 3132 defineCPUMacros(Builder, "core2"); 3133 break; 3134 case CK_Bonnell: 3135 defineCPUMacros(Builder, "atom"); 3136 break; 3137 case CK_Silvermont: 3138 defineCPUMacros(Builder, "slm"); 3139 break; 3140 case CK_Nehalem: 3141 case CK_Westmere: 3142 case CK_SandyBridge: 3143 case CK_IvyBridge: 3144 case CK_Haswell: 3145 case CK_Broadwell: 3146 // FIXME: Historically, we defined this legacy name, it would be nice to 3147 // remove it at some point. We've never exposed fine-grained names for 3148 // recent primary x86 CPUs, and we should keep it that way. 3149 defineCPUMacros(Builder, "corei7"); 3150 break; 3151 case CK_Skylake: 3152 // FIXME: Historically, we defined this legacy name, it would be nice to 3153 // remove it at some point. This is the only fine-grained CPU macro in the 3154 // main intel CPU line, and it would be better to not have these and force 3155 // people to use ISA macros. 3156 defineCPUMacros(Builder, "skx"); 3157 break; 3158 case CK_KNL: 3159 defineCPUMacros(Builder, "knl"); 3160 break; 3161 case CK_K6_2: 3162 Builder.defineMacro("__k6_2__"); 3163 Builder.defineMacro("__tune_k6_2__"); 3164 // Fallthrough 3165 case CK_K6_3: 3166 if (CPU != CK_K6_2) { // In case of fallthrough 3167 // FIXME: GCC may be enabling these in cases where some other k6 3168 // architecture is specified but -m3dnow is explicitly provided. The 3169 // exact semantics need to be determined and emulated here. 3170 Builder.defineMacro("__k6_3__"); 3171 Builder.defineMacro("__tune_k6_3__"); 3172 } 3173 // Fallthrough 3174 case CK_K6: 3175 defineCPUMacros(Builder, "k6"); 3176 break; 3177 case CK_Athlon: 3178 case CK_AthlonThunderbird: 3179 case CK_Athlon4: 3180 case CK_AthlonXP: 3181 case CK_AthlonMP: 3182 defineCPUMacros(Builder, "athlon"); 3183 if (SSELevel != NoSSE) { 3184 Builder.defineMacro("__athlon_sse__"); 3185 Builder.defineMacro("__tune_athlon_sse__"); 3186 } 3187 break; 3188 case CK_K8: 3189 case CK_K8SSE3: 3190 case CK_x86_64: 3191 case CK_Opteron: 3192 case CK_OpteronSSE3: 3193 case CK_Athlon64: 3194 case CK_Athlon64SSE3: 3195 case CK_AthlonFX: 3196 defineCPUMacros(Builder, "k8"); 3197 break; 3198 case CK_AMDFAM10: 3199 defineCPUMacros(Builder, "amdfam10"); 3200 break; 3201 case CK_BTVER1: 3202 defineCPUMacros(Builder, "btver1"); 3203 break; 3204 case CK_BTVER2: 3205 defineCPUMacros(Builder, "btver2"); 3206 break; 3207 case CK_BDVER1: 3208 defineCPUMacros(Builder, "bdver1"); 3209 break; 3210 case CK_BDVER2: 3211 defineCPUMacros(Builder, "bdver2"); 3212 break; 3213 case CK_BDVER3: 3214 defineCPUMacros(Builder, "bdver3"); 3215 break; 3216 case CK_BDVER4: 3217 defineCPUMacros(Builder, "bdver4"); 3218 break; 3219 case CK_Geode: 3220 defineCPUMacros(Builder, "geode"); 3221 break; 3222 } 3223 3224 // Target properties. 3225 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3226 3227 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3228 // functions in glibc header files that use FP Stack inline asm which the 3229 // backend can't deal with (PR879). 3230 Builder.defineMacro("__NO_MATH_INLINES"); 3231 3232 if (HasAES) 3233 Builder.defineMacro("__AES__"); 3234 3235 if (HasPCLMUL) 3236 Builder.defineMacro("__PCLMUL__"); 3237 3238 if (HasLZCNT) 3239 Builder.defineMacro("__LZCNT__"); 3240 3241 if (HasRDRND) 3242 Builder.defineMacro("__RDRND__"); 3243 3244 if (HasFSGSBASE) 3245 Builder.defineMacro("__FSGSBASE__"); 3246 3247 if (HasBMI) 3248 Builder.defineMacro("__BMI__"); 3249 3250 if (HasBMI2) 3251 Builder.defineMacro("__BMI2__"); 3252 3253 if (HasPOPCNT) 3254 Builder.defineMacro("__POPCNT__"); 3255 3256 if (HasRTM) 3257 Builder.defineMacro("__RTM__"); 3258 3259 if (HasPRFCHW) 3260 Builder.defineMacro("__PRFCHW__"); 3261 3262 if (HasRDSEED) 3263 Builder.defineMacro("__RDSEED__"); 3264 3265 if (HasADX) 3266 Builder.defineMacro("__ADX__"); 3267 3268 if (HasTBM) 3269 Builder.defineMacro("__TBM__"); 3270 3271 switch (XOPLevel) { 3272 case XOP: 3273 Builder.defineMacro("__XOP__"); 3274 case FMA4: 3275 Builder.defineMacro("__FMA4__"); 3276 case SSE4A: 3277 Builder.defineMacro("__SSE4A__"); 3278 case NoXOP: 3279 break; 3280 } 3281 3282 if (HasFMA) 3283 Builder.defineMacro("__FMA__"); 3284 3285 if (HasF16C) 3286 Builder.defineMacro("__F16C__"); 3287 3288 if (HasAVX512CD) 3289 Builder.defineMacro("__AVX512CD__"); 3290 if (HasAVX512ER) 3291 Builder.defineMacro("__AVX512ER__"); 3292 if (HasAVX512PF) 3293 Builder.defineMacro("__AVX512PF__"); 3294 if (HasAVX512DQ) 3295 Builder.defineMacro("__AVX512DQ__"); 3296 if (HasAVX512BW) 3297 Builder.defineMacro("__AVX512BW__"); 3298 if (HasAVX512VL) 3299 Builder.defineMacro("__AVX512VL__"); 3300 3301 if (HasSHA) 3302 Builder.defineMacro("__SHA__"); 3303 3304 if (HasCX16) 3305 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3306 3307 // Each case falls through to the previous one here. 3308 switch (SSELevel) { 3309 case AVX512F: 3310 Builder.defineMacro("__AVX512F__"); 3311 case AVX2: 3312 Builder.defineMacro("__AVX2__"); 3313 case AVX: 3314 Builder.defineMacro("__AVX__"); 3315 case SSE42: 3316 Builder.defineMacro("__SSE4_2__"); 3317 case SSE41: 3318 Builder.defineMacro("__SSE4_1__"); 3319 case SSSE3: 3320 Builder.defineMacro("__SSSE3__"); 3321 case SSE3: 3322 Builder.defineMacro("__SSE3__"); 3323 case SSE2: 3324 Builder.defineMacro("__SSE2__"); 3325 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3326 case SSE1: 3327 Builder.defineMacro("__SSE__"); 3328 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3329 case NoSSE: 3330 break; 3331 } 3332 3333 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3334 switch (SSELevel) { 3335 case AVX512F: 3336 case AVX2: 3337 case AVX: 3338 case SSE42: 3339 case SSE41: 3340 case SSSE3: 3341 case SSE3: 3342 case SSE2: 3343 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3344 break; 3345 case SSE1: 3346 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3347 break; 3348 default: 3349 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3350 } 3351 } 3352 3353 // Each case falls through to the previous one here. 3354 switch (MMX3DNowLevel) { 3355 case AMD3DNowAthlon: 3356 Builder.defineMacro("__3dNOW_A__"); 3357 case AMD3DNow: 3358 Builder.defineMacro("__3dNOW__"); 3359 case MMX: 3360 Builder.defineMacro("__MMX__"); 3361 case NoMMX3DNow: 3362 break; 3363 } 3364 3365 if (CPU >= CK_i486) { 3366 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3367 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3368 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3369 } 3370 if (CPU >= CK_i586) 3371 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3372 } 3373 3374 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3375 return llvm::StringSwitch<bool>(Feature) 3376 .Case("aes", HasAES) 3377 .Case("avx", SSELevel >= AVX) 3378 .Case("avx2", SSELevel >= AVX2) 3379 .Case("avx512f", SSELevel >= AVX512F) 3380 .Case("avx512cd", HasAVX512CD) 3381 .Case("avx512er", HasAVX512ER) 3382 .Case("avx512pf", HasAVX512PF) 3383 .Case("avx512dq", HasAVX512DQ) 3384 .Case("avx512bw", HasAVX512BW) 3385 .Case("avx512vl", HasAVX512VL) 3386 .Case("bmi", HasBMI) 3387 .Case("bmi2", HasBMI2) 3388 .Case("cx16", HasCX16) 3389 .Case("f16c", HasF16C) 3390 .Case("fma", HasFMA) 3391 .Case("fma4", XOPLevel >= FMA4) 3392 .Case("fsgsbase", HasFSGSBASE) 3393 .Case("lzcnt", HasLZCNT) 3394 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3395 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3396 .Case("mmx", MMX3DNowLevel >= MMX) 3397 .Case("pclmul", HasPCLMUL) 3398 .Case("popcnt", HasPOPCNT) 3399 .Case("prfchw", HasPRFCHW) 3400 .Case("rdrnd", HasRDRND) 3401 .Case("rdseed", HasRDSEED) 3402 .Case("rtm", HasRTM) 3403 .Case("sha", HasSHA) 3404 .Case("sse", SSELevel >= SSE1) 3405 .Case("sse2", SSELevel >= SSE2) 3406 .Case("sse3", SSELevel >= SSE3) 3407 .Case("ssse3", SSELevel >= SSSE3) 3408 .Case("sse4.1", SSELevel >= SSE41) 3409 .Case("sse4.2", SSELevel >= SSE42) 3410 .Case("sse4a", XOPLevel >= SSE4A) 3411 .Case("tbm", HasTBM) 3412 .Case("x86", true) 3413 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3414 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3415 .Case("xop", XOPLevel >= XOP) 3416 .Default(false); 3417 } 3418 3419 // We can't use a generic validation scheme for the features accepted here 3420 // versus subtarget features accepted in the target attribute because the 3421 // bitfield structure that's initialized in the runtime only supports the 3422 // below currently rather than the full range of subtarget features. (See 3423 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3424 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3425 return llvm::StringSwitch<bool>(FeatureStr) 3426 .Case("cmov", true) 3427 .Case("mmx", true) 3428 .Case("popcnt", true) 3429 .Case("sse", true) 3430 .Case("sse2", true) 3431 .Case("sse3", true) 3432 .Case("sse4.1", true) 3433 .Case("sse4.2", true) 3434 .Case("avx", true) 3435 .Case("avx2", true) 3436 .Case("sse4a", true) 3437 .Case("fma4", true) 3438 .Case("xop", true) 3439 .Case("fma", true) 3440 .Case("avx512f", true) 3441 .Case("bmi", true) 3442 .Case("bmi2", true) 3443 .Default(false); 3444 } 3445 3446 bool 3447 X86TargetInfo::validateAsmConstraint(const char *&Name, 3448 TargetInfo::ConstraintInfo &Info) const { 3449 switch (*Name) { 3450 default: return false; 3451 // Constant constraints. 3452 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3453 // instructions. 3454 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3455 // x86_64 instructions. 3456 case 's': 3457 Info.setRequiresImmediate(); 3458 return true; 3459 case 'I': 3460 Info.setRequiresImmediate(0, 31); 3461 return true; 3462 case 'J': 3463 Info.setRequiresImmediate(0, 63); 3464 return true; 3465 case 'K': 3466 Info.setRequiresImmediate(-128, 127); 3467 return true; 3468 case 'L': 3469 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3470 return true; 3471 case 'M': 3472 Info.setRequiresImmediate(0, 3); 3473 return true; 3474 case 'N': 3475 Info.setRequiresImmediate(0, 255); 3476 return true; 3477 case 'O': 3478 Info.setRequiresImmediate(0, 127); 3479 return true; 3480 // Register constraints. 3481 case 'Y': // 'Y' is the first character for several 2-character constraints. 3482 // Shift the pointer to the second character of the constraint. 3483 Name++; 3484 switch (*Name) { 3485 default: 3486 return false; 3487 case '0': // First SSE register. 3488 case 't': // Any SSE register, when SSE2 is enabled. 3489 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3490 case 'm': // Any MMX register, when inter-unit moves enabled. 3491 Info.setAllowsRegister(); 3492 return true; 3493 } 3494 case 'f': // Any x87 floating point stack register. 3495 // Constraint 'f' cannot be used for output operands. 3496 if (Info.ConstraintStr[0] == '=') 3497 return false; 3498 Info.setAllowsRegister(); 3499 return true; 3500 case 'a': // eax. 3501 case 'b': // ebx. 3502 case 'c': // ecx. 3503 case 'd': // edx. 3504 case 'S': // esi. 3505 case 'D': // edi. 3506 case 'A': // edx:eax. 3507 case 't': // Top of floating point stack. 3508 case 'u': // Second from top of floating point stack. 3509 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3510 case 'y': // Any MMX register. 3511 case 'x': // Any SSE register. 3512 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3513 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3514 case 'l': // "Index" registers: any general register that can be used as an 3515 // index in a base+index memory access. 3516 Info.setAllowsRegister(); 3517 return true; 3518 // Floating point constant constraints. 3519 case 'C': // SSE floating point constant. 3520 case 'G': // x87 floating point constant. 3521 return true; 3522 } 3523 } 3524 3525 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3526 unsigned Size) const { 3527 // Strip off constraint modifiers. 3528 while (Constraint[0] == '=' || 3529 Constraint[0] == '+' || 3530 Constraint[0] == '&') 3531 Constraint = Constraint.substr(1); 3532 3533 return validateOperandSize(Constraint, Size); 3534 } 3535 3536 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3537 unsigned Size) const { 3538 return validateOperandSize(Constraint, Size); 3539 } 3540 3541 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3542 unsigned Size) const { 3543 switch (Constraint[0]) { 3544 default: break; 3545 case 'y': 3546 return Size <= 64; 3547 case 'f': 3548 case 't': 3549 case 'u': 3550 return Size <= 128; 3551 case 'x': 3552 if (SSELevel >= AVX512F) 3553 // 512-bit zmm registers can be used if target supports AVX512F. 3554 return Size <= 512U; 3555 else if (SSELevel >= AVX) 3556 // 256-bit ymm registers can be used if target supports AVX. 3557 return Size <= 256U; 3558 return Size <= 128U; 3559 case 'Y': 3560 // 'Y' is the first character for several 2-character constraints. 3561 switch (Constraint[1]) { 3562 default: break; 3563 case 'm': 3564 // 'Ym' is synonymous with 'y'. 3565 return Size <= 64; 3566 case 'i': 3567 case 't': 3568 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3569 if (SSELevel >= AVX512F) 3570 return Size <= 512U; 3571 else if (SSELevel >= AVX) 3572 return Size <= 256U; 3573 return SSELevel >= SSE2 && Size <= 128U; 3574 } 3575 3576 } 3577 3578 return true; 3579 } 3580 3581 std::string 3582 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3583 switch (*Constraint) { 3584 case 'a': return std::string("{ax}"); 3585 case 'b': return std::string("{bx}"); 3586 case 'c': return std::string("{cx}"); 3587 case 'd': return std::string("{dx}"); 3588 case 'S': return std::string("{si}"); 3589 case 'D': return std::string("{di}"); 3590 case 'p': // address 3591 return std::string("im"); 3592 case 't': // top of floating point stack. 3593 return std::string("{st}"); 3594 case 'u': // second from top of floating point stack. 3595 return std::string("{st(1)}"); // second from top of floating point stack. 3596 default: 3597 return std::string(1, *Constraint); 3598 } 3599 } 3600 3601 // X86-32 generic target 3602 class X86_32TargetInfo : public X86TargetInfo { 3603 public: 3604 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3605 DoubleAlign = LongLongAlign = 32; 3606 LongDoubleWidth = 96; 3607 LongDoubleAlign = 32; 3608 SuitableAlign = 128; 3609 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3610 SizeType = UnsignedInt; 3611 PtrDiffType = SignedInt; 3612 IntPtrType = SignedInt; 3613 RegParmMax = 3; 3614 3615 // Use fpret for all types. 3616 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3617 (1 << TargetInfo::Double) | 3618 (1 << TargetInfo::LongDouble)); 3619 3620 // x86-32 has atomics up to 8 bytes 3621 // FIXME: Check that we actually have cmpxchg8b before setting 3622 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3623 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3624 } 3625 BuiltinVaListKind getBuiltinVaListKind() const override { 3626 return TargetInfo::CharPtrBuiltinVaList; 3627 } 3628 3629 int getEHDataRegisterNumber(unsigned RegNo) const override { 3630 if (RegNo == 0) return 0; 3631 if (RegNo == 1) return 2; 3632 return -1; 3633 } 3634 bool validateOperandSize(StringRef Constraint, 3635 unsigned Size) const override { 3636 switch (Constraint[0]) { 3637 default: break; 3638 case 'R': 3639 case 'q': 3640 case 'Q': 3641 case 'a': 3642 case 'b': 3643 case 'c': 3644 case 'd': 3645 case 'S': 3646 case 'D': 3647 return Size <= 32; 3648 case 'A': 3649 return Size <= 64; 3650 } 3651 3652 return X86TargetInfo::validateOperandSize(Constraint, Size); 3653 } 3654 }; 3655 3656 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3657 public: 3658 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3659 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3660 3661 unsigned getFloatEvalMethod() const override { 3662 unsigned Major, Minor, Micro; 3663 getTriple().getOSVersion(Major, Minor, Micro); 3664 // New NetBSD uses the default rounding mode. 3665 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3666 return X86_32TargetInfo::getFloatEvalMethod(); 3667 // NetBSD before 6.99.26 defaults to "double" rounding. 3668 return 1; 3669 } 3670 }; 3671 3672 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3673 public: 3674 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3675 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3676 SizeType = UnsignedLong; 3677 IntPtrType = SignedLong; 3678 PtrDiffType = SignedLong; 3679 } 3680 }; 3681 3682 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3683 public: 3684 BitrigI386TargetInfo(const llvm::Triple &Triple) 3685 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3686 SizeType = UnsignedLong; 3687 IntPtrType = SignedLong; 3688 PtrDiffType = SignedLong; 3689 } 3690 }; 3691 3692 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3693 public: 3694 DarwinI386TargetInfo(const llvm::Triple &Triple) 3695 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3696 LongDoubleWidth = 128; 3697 LongDoubleAlign = 128; 3698 SuitableAlign = 128; 3699 MaxVectorAlign = 256; 3700 SizeType = UnsignedLong; 3701 IntPtrType = SignedLong; 3702 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3703 HasAlignMac68kSupport = true; 3704 } 3705 3706 }; 3707 3708 // x86-32 Windows target 3709 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3710 public: 3711 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3712 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3713 WCharType = UnsignedShort; 3714 DoubleAlign = LongLongAlign = 64; 3715 bool IsWinCOFF = 3716 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3717 DescriptionString = IsWinCOFF 3718 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3719 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3720 } 3721 void getTargetDefines(const LangOptions &Opts, 3722 MacroBuilder &Builder) const override { 3723 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3724 } 3725 }; 3726 3727 // x86-32 Windows Visual Studio target 3728 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3729 public: 3730 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3731 : WindowsX86_32TargetInfo(Triple) { 3732 LongDoubleWidth = LongDoubleAlign = 64; 3733 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3734 } 3735 void getTargetDefines(const LangOptions &Opts, 3736 MacroBuilder &Builder) const override { 3737 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3738 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3739 // The value of the following reflects processor type. 3740 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3741 // We lost the original triple, so we use the default. 3742 Builder.defineMacro("_M_IX86", "600"); 3743 } 3744 }; 3745 } // end anonymous namespace 3746 3747 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3748 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang supports 3749 // __declspec natively under -fms-extensions, but we define a no-op __declspec 3750 // macro anyway for pre-processor compatibility. 3751 if (Opts.MicrosoftExt) 3752 Builder.defineMacro("__declspec", "__declspec"); 3753 else 3754 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3755 3756 if (!Opts.MicrosoftExt) { 3757 // Provide macros for all the calling convention keywords. Provide both 3758 // single and double underscore prefixed variants. These are available on 3759 // x64 as well as x86, even though they have no effect. 3760 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3761 for (const char *CC : CCs) { 3762 std::string GCCSpelling = "__attribute__((__"; 3763 GCCSpelling += CC; 3764 GCCSpelling += "__))"; 3765 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3766 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3767 } 3768 } 3769 } 3770 3771 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3772 Builder.defineMacro("__MSVCRT__"); 3773 Builder.defineMacro("__MINGW32__"); 3774 addCygMingDefines(Opts, Builder); 3775 } 3776 3777 namespace { 3778 // x86-32 MinGW target 3779 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3780 public: 3781 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3782 : WindowsX86_32TargetInfo(Triple) {} 3783 void getTargetDefines(const LangOptions &Opts, 3784 MacroBuilder &Builder) const override { 3785 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3786 DefineStd(Builder, "WIN32", Opts); 3787 DefineStd(Builder, "WINNT", Opts); 3788 Builder.defineMacro("_X86_"); 3789 addMinGWDefines(Opts, Builder); 3790 } 3791 }; 3792 3793 // x86-32 Cygwin target 3794 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3795 public: 3796 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3797 : X86_32TargetInfo(Triple) { 3798 TLSSupported = false; 3799 WCharType = UnsignedShort; 3800 DoubleAlign = LongLongAlign = 64; 3801 DescriptionString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3802 } 3803 void getTargetDefines(const LangOptions &Opts, 3804 MacroBuilder &Builder) const override { 3805 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3806 Builder.defineMacro("_X86_"); 3807 Builder.defineMacro("__CYGWIN__"); 3808 Builder.defineMacro("__CYGWIN32__"); 3809 addCygMingDefines(Opts, Builder); 3810 DefineStd(Builder, "unix", Opts); 3811 if (Opts.CPlusPlus) 3812 Builder.defineMacro("_GNU_SOURCE"); 3813 } 3814 }; 3815 3816 // x86-32 Haiku target 3817 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3818 public: 3819 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3820 SizeType = UnsignedLong; 3821 IntPtrType = SignedLong; 3822 PtrDiffType = SignedLong; 3823 ProcessIDType = SignedLong; 3824 this->UserLabelPrefix = ""; 3825 this->TLSSupported = false; 3826 } 3827 void getTargetDefines(const LangOptions &Opts, 3828 MacroBuilder &Builder) const override { 3829 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3830 Builder.defineMacro("__INTEL__"); 3831 Builder.defineMacro("__HAIKU__"); 3832 } 3833 }; 3834 3835 // RTEMS Target 3836 template<typename Target> 3837 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3838 protected: 3839 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3840 MacroBuilder &Builder) const override { 3841 // RTEMS defines; list based off of gcc output 3842 3843 Builder.defineMacro("__rtems__"); 3844 Builder.defineMacro("__ELF__"); 3845 } 3846 3847 public: 3848 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3849 this->UserLabelPrefix = ""; 3850 3851 switch (Triple.getArch()) { 3852 default: 3853 case llvm::Triple::x86: 3854 // this->MCountName = ".mcount"; 3855 break; 3856 case llvm::Triple::mips: 3857 case llvm::Triple::mipsel: 3858 case llvm::Triple::ppc: 3859 case llvm::Triple::ppc64: 3860 case llvm::Triple::ppc64le: 3861 // this->MCountName = "_mcount"; 3862 break; 3863 case llvm::Triple::arm: 3864 // this->MCountName = "__mcount"; 3865 break; 3866 } 3867 } 3868 }; 3869 3870 // x86-32 RTEMS target 3871 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3872 public: 3873 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3874 SizeType = UnsignedLong; 3875 IntPtrType = SignedLong; 3876 PtrDiffType = SignedLong; 3877 this->UserLabelPrefix = ""; 3878 } 3879 void getTargetDefines(const LangOptions &Opts, 3880 MacroBuilder &Builder) const override { 3881 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3882 Builder.defineMacro("__INTEL__"); 3883 Builder.defineMacro("__rtems__"); 3884 } 3885 }; 3886 3887 // x86-64 generic target 3888 class X86_64TargetInfo : public X86TargetInfo { 3889 public: 3890 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3891 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3892 bool IsWinCOFF = 3893 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3894 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3895 LongDoubleWidth = 128; 3896 LongDoubleAlign = 128; 3897 LargeArrayMinWidth = 128; 3898 LargeArrayAlign = 128; 3899 SuitableAlign = 128; 3900 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3901 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3902 IntPtrType = IsX32 ? SignedInt : SignedLong; 3903 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3904 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3905 RegParmMax = 6; 3906 3907 // Pointers are 32-bit in x32. 3908 DescriptionString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3909 : IsWinCOFF 3910 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 3911 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3912 3913 // Use fpret only for long double. 3914 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3915 3916 // Use fp2ret for _Complex long double. 3917 ComplexLongDoubleUsesFP2Ret = true; 3918 3919 // x86-64 has atomics up to 16 bytes. 3920 MaxAtomicPromoteWidth = 128; 3921 MaxAtomicInlineWidth = 128; 3922 } 3923 BuiltinVaListKind getBuiltinVaListKind() const override { 3924 return TargetInfo::X86_64ABIBuiltinVaList; 3925 } 3926 3927 int getEHDataRegisterNumber(unsigned RegNo) const override { 3928 if (RegNo == 0) return 0; 3929 if (RegNo == 1) return 1; 3930 return -1; 3931 } 3932 3933 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3934 return (CC == CC_C || 3935 CC == CC_X86VectorCall || 3936 CC == CC_IntelOclBicc || 3937 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3938 } 3939 3940 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3941 return CC_C; 3942 } 3943 3944 // for x32 we need it here explicitly 3945 bool hasInt128Type() const override { return true; } 3946 }; 3947 3948 // x86-64 Windows target 3949 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3950 public: 3951 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3952 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3953 WCharType = UnsignedShort; 3954 LongWidth = LongAlign = 32; 3955 DoubleAlign = LongLongAlign = 64; 3956 IntMaxType = SignedLongLong; 3957 Int64Type = SignedLongLong; 3958 SizeType = UnsignedLongLong; 3959 PtrDiffType = SignedLongLong; 3960 IntPtrType = SignedLongLong; 3961 this->UserLabelPrefix = ""; 3962 } 3963 3964 void getTargetDefines(const LangOptions &Opts, 3965 MacroBuilder &Builder) const override { 3966 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3967 Builder.defineMacro("_WIN64"); 3968 } 3969 3970 BuiltinVaListKind getBuiltinVaListKind() const override { 3971 return TargetInfo::CharPtrBuiltinVaList; 3972 } 3973 3974 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3975 switch (CC) { 3976 case CC_X86StdCall: 3977 case CC_X86ThisCall: 3978 case CC_X86FastCall: 3979 return CCCR_Ignore; 3980 case CC_C: 3981 case CC_X86VectorCall: 3982 case CC_IntelOclBicc: 3983 case CC_X86_64SysV: 3984 return CCCR_OK; 3985 default: 3986 return CCCR_Warning; 3987 } 3988 } 3989 }; 3990 3991 // x86-64 Windows Visual Studio target 3992 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 3993 public: 3994 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 3995 : WindowsX86_64TargetInfo(Triple) { 3996 LongDoubleWidth = LongDoubleAlign = 64; 3997 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3998 } 3999 void getTargetDefines(const LangOptions &Opts, 4000 MacroBuilder &Builder) const override { 4001 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4002 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4003 Builder.defineMacro("_M_X64", "100"); 4004 Builder.defineMacro("_M_AMD64", "100"); 4005 } 4006 }; 4007 4008 // x86-64 MinGW target 4009 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4010 public: 4011 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 4012 : WindowsX86_64TargetInfo(Triple) {} 4013 void getTargetDefines(const LangOptions &Opts, 4014 MacroBuilder &Builder) const override { 4015 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4016 DefineStd(Builder, "WIN64", Opts); 4017 Builder.defineMacro("__MINGW64__"); 4018 addMinGWDefines(Opts, Builder); 4019 4020 // GCC defines this macro when it is using __gxx_personality_seh0. 4021 if (!Opts.SjLjExceptions) 4022 Builder.defineMacro("__SEH__"); 4023 } 4024 }; 4025 4026 // x86-64 Cygwin target 4027 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4028 public: 4029 CygwinX86_64TargetInfo(const llvm::Triple &Triple) 4030 : X86_64TargetInfo(Triple) { 4031 TLSSupported = false; 4032 WCharType = UnsignedShort; 4033 } 4034 void getTargetDefines(const LangOptions &Opts, 4035 MacroBuilder &Builder) const override { 4036 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4037 Builder.defineMacro("__x86_64__"); 4038 Builder.defineMacro("__CYGWIN__"); 4039 Builder.defineMacro("__CYGWIN64__"); 4040 addCygMingDefines(Opts, Builder); 4041 DefineStd(Builder, "unix", Opts); 4042 if (Opts.CPlusPlus) 4043 Builder.defineMacro("_GNU_SOURCE"); 4044 4045 // GCC defines this macro when it is using __gxx_personality_seh0. 4046 if (!Opts.SjLjExceptions) 4047 Builder.defineMacro("__SEH__"); 4048 } 4049 }; 4050 4051 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4052 public: 4053 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 4054 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 4055 Int64Type = SignedLongLong; 4056 MaxVectorAlign = 256; 4057 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4058 llvm::Triple T = llvm::Triple(Triple); 4059 if (T.isiOS()) 4060 UseSignedCharForObjCBool = false; 4061 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 4062 } 4063 }; 4064 4065 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4066 public: 4067 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 4068 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 4069 IntMaxType = SignedLongLong; 4070 Int64Type = SignedLongLong; 4071 } 4072 }; 4073 4074 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4075 public: 4076 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 4077 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 4078 IntMaxType = SignedLongLong; 4079 Int64Type = SignedLongLong; 4080 } 4081 }; 4082 4083 class ARMTargetInfo : public TargetInfo { 4084 // Possible FPU choices. 4085 enum FPUMode { 4086 VFP2FPU = (1 << 0), 4087 VFP3FPU = (1 << 1), 4088 VFP4FPU = (1 << 2), 4089 NeonFPU = (1 << 3), 4090 FPARMV8 = (1 << 4) 4091 }; 4092 4093 // Possible HWDiv features. 4094 enum HWDivMode { 4095 HWDivThumb = (1 << 0), 4096 HWDivARM = (1 << 1) 4097 }; 4098 4099 static bool FPUModeIsVFP(FPUMode Mode) { 4100 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4101 } 4102 4103 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4104 static const char * const GCCRegNames[]; 4105 4106 std::string ABI, CPU; 4107 4108 StringRef DefaultCPU; 4109 StringRef CPUProfile; 4110 StringRef CPUAttr; 4111 4112 enum { 4113 FP_Default, 4114 FP_VFP, 4115 FP_Neon 4116 } FPMath; 4117 4118 unsigned ArchISA; 4119 unsigned ArchKind; 4120 unsigned ArchProfile; 4121 unsigned ArchVersion; 4122 4123 unsigned FPU : 5; 4124 4125 unsigned IsAAPCS : 1; 4126 unsigned HWDiv : 2; 4127 4128 // Initialized via features. 4129 unsigned SoftFloat : 1; 4130 unsigned SoftFloatABI : 1; 4131 4132 unsigned CRC : 1; 4133 unsigned Crypto : 1; 4134 4135 // ACLE 6.5.1 Hardware floating point 4136 enum { 4137 HW_FP_HP = (1 << 1), /// half (16-bit) 4138 HW_FP_SP = (1 << 2), /// single (32-bit) 4139 HW_FP_DP = (1 << 3), /// double (64-bit) 4140 }; 4141 uint32_t HW_FP; 4142 4143 static const Builtin::Info BuiltinInfo[]; 4144 4145 void setABIAAPCS() { 4146 IsAAPCS = true; 4147 4148 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4149 const llvm::Triple &T = getTriple(); 4150 4151 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4152 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4153 T.getOS() == llvm::Triple::Bitrig) 4154 SizeType = UnsignedLong; 4155 else 4156 SizeType = UnsignedInt; 4157 4158 switch (T.getOS()) { 4159 case llvm::Triple::NetBSD: 4160 WCharType = SignedInt; 4161 break; 4162 case llvm::Triple::Win32: 4163 WCharType = UnsignedShort; 4164 break; 4165 case llvm::Triple::Linux: 4166 default: 4167 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4168 WCharType = UnsignedInt; 4169 break; 4170 } 4171 4172 UseBitFieldTypeAlignment = true; 4173 4174 ZeroLengthBitfieldBoundary = 0; 4175 4176 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4177 // so set preferred for small types to 32. 4178 if (T.isOSBinFormatMachO()) { 4179 DescriptionString = 4180 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4181 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4182 } else if (T.isOSWindows()) { 4183 assert(!BigEndian && "Windows on ARM does not support big endian"); 4184 DescriptionString = "e" 4185 "-m:w" 4186 "-p:32:32" 4187 "-i64:64" 4188 "-v128:64:128" 4189 "-a:0:32" 4190 "-n32" 4191 "-S64"; 4192 } else if (T.isOSNaCl()) { 4193 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4194 DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 4195 } else { 4196 DescriptionString = 4197 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4198 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4199 } 4200 4201 // FIXME: Enumerated types are variable width in straight AAPCS. 4202 } 4203 4204 void setABIAPCS() { 4205 const llvm::Triple &T = getTriple(); 4206 4207 IsAAPCS = false; 4208 4209 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4210 4211 // size_t is unsigned int on FreeBSD. 4212 if (T.getOS() == llvm::Triple::FreeBSD) 4213 SizeType = UnsignedInt; 4214 else 4215 SizeType = UnsignedLong; 4216 4217 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4218 WCharType = SignedInt; 4219 4220 // Do not respect the alignment of bit-field types when laying out 4221 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4222 UseBitFieldTypeAlignment = false; 4223 4224 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4225 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4226 /// gcc. 4227 ZeroLengthBitfieldBoundary = 32; 4228 4229 if (T.isOSBinFormatMachO()) 4230 DescriptionString = 4231 BigEndian 4232 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4233 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4234 else 4235 DescriptionString = 4236 BigEndian 4237 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4238 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4239 4240 // FIXME: Override "preferred align" for double and long long. 4241 } 4242 4243 void setArchInfo() { 4244 StringRef ArchName = getTriple().getArchName(); 4245 4246 ArchISA = llvm::ARMTargetParser::parseArchISA(ArchName); 4247 DefaultCPU = getDefaultCPU(ArchName); 4248 4249 // SubArch is specified by the target triple 4250 if (!DefaultCPU.empty()) 4251 setArchInfo(DefaultCPU); 4252 else 4253 // FIXME ArchInfo should be based on ArchName from triple, not on 4254 // a hard-coded CPU name. Doing so currently causes regressions: 4255 // test/Preprocessor/init.c: __ARM_ARCH_6J__ not defined 4256 setArchInfo(CPU); 4257 } 4258 4259 void setArchInfo(StringRef CPU) { 4260 StringRef SubArch; 4261 4262 // cache TargetParser info 4263 ArchKind = llvm::ARMTargetParser::parseCPUArch(CPU); 4264 SubArch = llvm::ARMTargetParser::getSubArch(ArchKind); 4265 ArchProfile = llvm::ARMTargetParser::parseArchProfile(SubArch); 4266 ArchVersion = llvm::ARMTargetParser::parseArchVersion(SubArch); 4267 4268 // cache CPU related strings 4269 CPUAttr = getCPUAttr(); 4270 CPUProfile = getCPUProfile(); 4271 } 4272 4273 void setAtomic() { 4274 // when triple does not specify a sub arch, 4275 // then we are not using inline atomics 4276 bool ShouldUseInlineAtomic = DefaultCPU.empty() ? 4277 false : 4278 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4279 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4280 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4281 if (ArchProfile == llvm::ARM::PK_M) { 4282 MaxAtomicPromoteWidth = 32; 4283 if (ShouldUseInlineAtomic) 4284 MaxAtomicInlineWidth = 32; 4285 } 4286 else { 4287 MaxAtomicPromoteWidth = 64; 4288 if (ShouldUseInlineAtomic) 4289 MaxAtomicInlineWidth = 64; 4290 } 4291 } 4292 4293 bool isThumb() const { 4294 return (ArchISA == llvm::ARM::IK_THUMB); 4295 } 4296 4297 bool supportsThumb() const { 4298 return CPUAttr.count('T') || ArchVersion >= 6; 4299 } 4300 4301 bool supportsThumb2() const { 4302 return CPUAttr.equals("6T2") || ArchVersion >= 7; 4303 } 4304 4305 StringRef getDefaultCPU(StringRef ArchName) const { 4306 const char *DefaultCPU = llvm::ARMTargetParser::getDefaultCPU(ArchName); 4307 return DefaultCPU ? DefaultCPU : ""; 4308 } 4309 4310 StringRef getCPUAttr() const { 4311 const char *CPUAttr; 4312 // For most sub-arches, the build attribute CPU name is enough. 4313 // For Cortex variants, it's slightly different. 4314 switch(ArchKind) { 4315 default: 4316 CPUAttr = llvm::ARMTargetParser::getCPUAttr(ArchKind); 4317 return CPUAttr ? CPUAttr : ""; 4318 case llvm::ARM::AK_ARMV6M: 4319 case llvm::ARM::AK_ARMV6SM: 4320 case llvm::ARM::AK_ARMV6HL: 4321 return "6M"; 4322 case llvm::ARM::AK_ARMV7S: 4323 return "7S"; 4324 case llvm::ARM::AK_ARMV7: 4325 case llvm::ARM::AK_ARMV7A: 4326 case llvm::ARM::AK_ARMV7L: 4327 case llvm::ARM::AK_ARMV7HL: 4328 return "7A"; 4329 case llvm::ARM::AK_ARMV7R: 4330 return "7R"; 4331 case llvm::ARM::AK_ARMV7M: 4332 return "7M"; 4333 case llvm::ARM::AK_ARMV7EM: 4334 return "7EM"; 4335 case llvm::ARM::AK_ARMV8A: 4336 return "8A"; 4337 case llvm::ARM::AK_ARMV8_1A: 4338 return "8_1A"; 4339 } 4340 } 4341 4342 StringRef getCPUProfile() const { 4343 switch(ArchProfile) { 4344 case llvm::ARM::PK_A: 4345 return "A"; 4346 case llvm::ARM::PK_R: 4347 return "R"; 4348 case llvm::ARM::PK_M: 4349 return "M"; 4350 default: 4351 return ""; 4352 } 4353 } 4354 4355 public: 4356 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4357 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 4358 IsAAPCS(true), HW_FP(0) { 4359 BigEndian = IsBigEndian; 4360 4361 switch (getTriple().getOS()) { 4362 case llvm::Triple::NetBSD: 4363 PtrDiffType = SignedLong; 4364 break; 4365 default: 4366 PtrDiffType = SignedInt; 4367 break; 4368 } 4369 4370 // cache arch related info 4371 setArchInfo(); 4372 4373 // {} in inline assembly are neon specifiers, not assembly variant 4374 // specifiers. 4375 NoAsmVariants = true; 4376 4377 // FIXME: This duplicates code from the driver that sets the -target-abi 4378 // option - this code is used if -target-abi isn't passed and should 4379 // be unified in some way. 4380 if (Triple.isOSBinFormatMachO()) { 4381 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4382 // the frontend matches that. 4383 if (Triple.getEnvironment() == llvm::Triple::EABI || 4384 Triple.getOS() == llvm::Triple::UnknownOS || 4385 StringRef(CPU).startswith("cortex-m")) { 4386 setABI("aapcs"); 4387 } else { 4388 setABI("apcs-gnu"); 4389 } 4390 } else if (Triple.isOSWindows()) { 4391 // FIXME: this is invalid for WindowsCE 4392 setABI("aapcs"); 4393 } else { 4394 // Select the default based on the platform. 4395 switch (Triple.getEnvironment()) { 4396 case llvm::Triple::Android: 4397 case llvm::Triple::GNUEABI: 4398 case llvm::Triple::GNUEABIHF: 4399 setABI("aapcs-linux"); 4400 break; 4401 case llvm::Triple::EABIHF: 4402 case llvm::Triple::EABI: 4403 setABI("aapcs"); 4404 break; 4405 case llvm::Triple::GNU: 4406 setABI("apcs-gnu"); 4407 break; 4408 default: 4409 if (Triple.getOS() == llvm::Triple::NetBSD) 4410 setABI("apcs-gnu"); 4411 else 4412 setABI("aapcs"); 4413 break; 4414 } 4415 } 4416 4417 // ARM targets default to using the ARM C++ ABI. 4418 TheCXXABI.set(TargetCXXABI::GenericARM); 4419 4420 // ARM has atomics up to 8 bytes 4421 setAtomic(); 4422 4423 // Do force alignment of members that follow zero length bitfields. If 4424 // the alignment of the zero-length bitfield is greater than the member 4425 // that follows it, `bar', `bar' will be aligned as the type of the 4426 // zero length bitfield. 4427 UseZeroLengthBitfieldAlignment = true; 4428 } 4429 4430 StringRef getABI() const override { return ABI; } 4431 4432 bool setABI(const std::string &Name) override { 4433 ABI = Name; 4434 4435 // The defaults (above) are for AAPCS, check if we need to change them. 4436 // 4437 // FIXME: We need support for -meabi... we could just mangle it into the 4438 // name. 4439 if (Name == "apcs-gnu") { 4440 setABIAPCS(); 4441 return true; 4442 } 4443 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4444 setABIAAPCS(); 4445 return true; 4446 } 4447 return false; 4448 } 4449 4450 // FIXME: This should be based on Arch attributes, not CPU names. 4451 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 4452 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 4453 Features["vfp2"] = true; 4454 else if (CPU == "cortex-a8" || CPU == "cortex-a9") { 4455 Features["vfp3"] = true; 4456 Features["neon"] = true; 4457 } 4458 else if (CPU == "cortex-a5") { 4459 Features["vfp4"] = true; 4460 Features["neon"] = true; 4461 } else if (CPU == "swift" || CPU == "cortex-a7" || 4462 CPU == "cortex-a12" || CPU == "cortex-a15" || 4463 CPU == "cortex-a17" || CPU == "krait") { 4464 Features["vfp4"] = true; 4465 Features["neon"] = true; 4466 Features["hwdiv"] = true; 4467 Features["hwdiv-arm"] = true; 4468 } else if (CPU == "cyclone" || CPU == "cortex-a53" || CPU == "cortex-a57" || 4469 CPU == "cortex-a72") { 4470 Features["fp-armv8"] = true; 4471 Features["neon"] = true; 4472 Features["hwdiv"] = true; 4473 Features["hwdiv-arm"] = true; 4474 Features["crc"] = true; 4475 Features["crypto"] = true; 4476 } else if (CPU == "cortex-r5" || CPU == "cortex-r7" || ArchVersion == 8) { 4477 Features["hwdiv"] = true; 4478 Features["hwdiv-arm"] = true; 4479 } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" || 4480 CPU == "sc300" || CPU == "cortex-r4" || CPU == "cortex-r4f") { 4481 Features["hwdiv"] = true; 4482 } 4483 } 4484 4485 bool handleTargetFeatures(std::vector<std::string> &Features, 4486 DiagnosticsEngine &Diags) override { 4487 FPU = 0; 4488 CRC = 0; 4489 Crypto = 0; 4490 SoftFloat = SoftFloatABI = false; 4491 HWDiv = 0; 4492 4493 // This does not diagnose illegal cases like having both 4494 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4495 uint32_t HW_FP_remove = 0; 4496 for (const auto &Feature : Features) { 4497 if (Feature == "+soft-float") { 4498 SoftFloat = true; 4499 } else if (Feature == "+soft-float-abi") { 4500 SoftFloatABI = true; 4501 } else if (Feature == "+vfp2") { 4502 FPU |= VFP2FPU; 4503 HW_FP |= HW_FP_SP | HW_FP_DP; 4504 } else if (Feature == "+vfp3") { 4505 FPU |= VFP3FPU; 4506 HW_FP |= HW_FP_SP | HW_FP_DP; 4507 } else if (Feature == "+vfp4") { 4508 FPU |= VFP4FPU; 4509 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4510 } else if (Feature == "+fp-armv8") { 4511 FPU |= FPARMV8; 4512 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4513 } else if (Feature == "+neon") { 4514 FPU |= NeonFPU; 4515 HW_FP |= HW_FP_SP | HW_FP_DP; 4516 } else if (Feature == "+hwdiv") { 4517 HWDiv |= HWDivThumb; 4518 } else if (Feature == "+hwdiv-arm") { 4519 HWDiv |= HWDivARM; 4520 } else if (Feature == "+crc") { 4521 CRC = 1; 4522 } else if (Feature == "+crypto") { 4523 Crypto = 1; 4524 } else if (Feature == "+fp-only-sp") { 4525 HW_FP_remove |= HW_FP_DP | HW_FP_HP; 4526 } 4527 } 4528 HW_FP &= ~HW_FP_remove; 4529 4530 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4531 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4532 return false; 4533 } 4534 4535 if (FPMath == FP_Neon) 4536 Features.push_back("+neonfp"); 4537 else if (FPMath == FP_VFP) 4538 Features.push_back("-neonfp"); 4539 4540 // Remove front-end specific options which the backend handles differently. 4541 auto Feature = 4542 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4543 if (Feature != Features.end()) 4544 Features.erase(Feature); 4545 4546 return true; 4547 } 4548 4549 bool hasFeature(StringRef Feature) const override { 4550 return llvm::StringSwitch<bool>(Feature) 4551 .Case("arm", true) 4552 .Case("softfloat", SoftFloat) 4553 .Case("thumb", isThumb()) 4554 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4555 .Case("hwdiv", HWDiv & HWDivThumb) 4556 .Case("hwdiv-arm", HWDiv & HWDivARM) 4557 .Default(false); 4558 } 4559 4560 bool setCPU(const std::string &Name) override { 4561 unsigned ArchKind = llvm::ARMTargetParser::parseCPUArch(Name); 4562 if (ArchKind == llvm::ARM::AK_INVALID) 4563 return false; 4564 setArchInfo(Name); 4565 setAtomic(); 4566 CPU = Name; 4567 return true; 4568 } 4569 4570 bool setFPMath(StringRef Name) override; 4571 4572 void getTargetDefines(const LangOptions &Opts, 4573 MacroBuilder &Builder) const override { 4574 // Target identification. 4575 Builder.defineMacro("__arm"); 4576 Builder.defineMacro("__arm__"); 4577 4578 // Target properties. 4579 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4580 if (!CPUAttr.empty()) 4581 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 4582 4583 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4584 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4585 Builder.defineMacro("__ARM_ARCH", llvm::utostr(ArchVersion)); 4586 if (ArchVersion >= 8) { 4587 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4588 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4589 } 4590 4591 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4592 // is not defined for the M-profile. 4593 // NOTE that the deffault profile is assumed to be 'A' 4594 if (CPUProfile.empty() || CPUProfile != "M") 4595 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4596 4597 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4598 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4599 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4600 if (supportsThumb2()) 4601 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4602 else if (supportsThumb()) 4603 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4604 4605 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4606 // instruction set such as ARM or Thumb. 4607 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4608 4609 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4610 4611 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4612 if (!CPUProfile.empty()) 4613 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4614 4615 // ACLE 6.5.1 Hardware Floating Point 4616 if (HW_FP) 4617 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4618 4619 // ACLE predefines. 4620 Builder.defineMacro("__ARM_ACLE", "200"); 4621 4622 // Subtarget options. 4623 4624 // FIXME: It's more complicated than this and we don't really support 4625 // interworking. 4626 // Windows on ARM does not "support" interworking 4627 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 4628 Builder.defineMacro("__THUMB_INTERWORK__"); 4629 4630 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4631 // Embedded targets on Darwin follow AAPCS, but not EABI. 4632 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4633 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4634 Builder.defineMacro("__ARM_EABI__"); 4635 Builder.defineMacro("__ARM_PCS", "1"); 4636 4637 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4638 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4639 } 4640 4641 if (SoftFloat) 4642 Builder.defineMacro("__SOFTFP__"); 4643 4644 if (CPU == "xscale") 4645 Builder.defineMacro("__XSCALE__"); 4646 4647 if (isThumb()) { 4648 Builder.defineMacro("__THUMBEL__"); 4649 Builder.defineMacro("__thumb__"); 4650 if (supportsThumb2()) 4651 Builder.defineMacro("__thumb2__"); 4652 } 4653 if (((HWDiv & HWDivThumb) && isThumb()) || ((HWDiv & HWDivARM) && !isThumb())) 4654 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4655 4656 // Note, this is always on in gcc, even though it doesn't make sense. 4657 Builder.defineMacro("__APCS_32__"); 4658 4659 if (FPUModeIsVFP((FPUMode) FPU)) { 4660 Builder.defineMacro("__VFP_FP__"); 4661 if (FPU & VFP2FPU) 4662 Builder.defineMacro("__ARM_VFPV2__"); 4663 if (FPU & VFP3FPU) 4664 Builder.defineMacro("__ARM_VFPV3__"); 4665 if (FPU & VFP4FPU) 4666 Builder.defineMacro("__ARM_VFPV4__"); 4667 } 4668 4669 // This only gets set when Neon instructions are actually available, unlike 4670 // the VFP define, hence the soft float and arch check. This is subtly 4671 // different from gcc, we follow the intent which was that it should be set 4672 // when Neon instructions are actually available. 4673 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 4674 Builder.defineMacro("__ARM_NEON"); 4675 Builder.defineMacro("__ARM_NEON__"); 4676 } 4677 4678 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4679 Opts.ShortWChar ? "2" : "4"); 4680 4681 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4682 Opts.ShortEnums ? "1" : "4"); 4683 4684 if (CRC) 4685 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4686 4687 if (Crypto) 4688 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4689 4690 if (ArchVersion >= 6 && CPUAttr != "6M") { 4691 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4692 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4693 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4694 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4695 } 4696 4697 bool is5EOrAbove = (ArchVersion >= 6 || 4698 (ArchVersion == 5 && CPUAttr.count('E'))); 4699 // FIXME: We are not getting all 32-bit ARM architectures 4700 bool is32Bit = (!isThumb() || supportsThumb2()); 4701 if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUAttr == "7EM")) 4702 Builder.defineMacro("__ARM_FEATURE_DSP"); 4703 } 4704 4705 void getTargetBuiltins(const Builtin::Info *&Records, 4706 unsigned &NumRecords) const override { 4707 Records = BuiltinInfo; 4708 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4709 } 4710 bool isCLZForZeroUndef() const override { return false; } 4711 BuiltinVaListKind getBuiltinVaListKind() const override { 4712 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4713 } 4714 void getGCCRegNames(const char * const *&Names, 4715 unsigned &NumNames) const override; 4716 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4717 unsigned &NumAliases) const override; 4718 bool validateAsmConstraint(const char *&Name, 4719 TargetInfo::ConstraintInfo &Info) const override { 4720 switch (*Name) { 4721 default: break; 4722 case 'l': // r0-r7 4723 case 'h': // r8-r15 4724 case 'w': // VFP Floating point register single precision 4725 case 'P': // VFP Floating point register double precision 4726 Info.setAllowsRegister(); 4727 return true; 4728 case 'I': 4729 case 'J': 4730 case 'K': 4731 case 'L': 4732 case 'M': 4733 // FIXME 4734 return true; 4735 case 'Q': // A memory address that is a single base register. 4736 Info.setAllowsMemory(); 4737 return true; 4738 case 'U': // a memory reference... 4739 switch (Name[1]) { 4740 case 'q': // ...ARMV4 ldrsb 4741 case 'v': // ...VFP load/store (reg+constant offset) 4742 case 'y': // ...iWMMXt load/store 4743 case 't': // address valid for load/store opaque types wider 4744 // than 128-bits 4745 case 'n': // valid address for Neon doubleword vector load/store 4746 case 'm': // valid address for Neon element and structure load/store 4747 case 's': // valid address for non-offset loads/stores of quad-word 4748 // values in four ARM registers 4749 Info.setAllowsMemory(); 4750 Name++; 4751 return true; 4752 } 4753 } 4754 return false; 4755 } 4756 std::string convertConstraint(const char *&Constraint) const override { 4757 std::string R; 4758 switch (*Constraint) { 4759 case 'U': // Two-character constraint; add "^" hint for later parsing. 4760 R = std::string("^") + std::string(Constraint, 2); 4761 Constraint++; 4762 break; 4763 case 'p': // 'p' should be translated to 'r' by default. 4764 R = std::string("r"); 4765 break; 4766 default: 4767 return std::string(1, *Constraint); 4768 } 4769 return R; 4770 } 4771 bool 4772 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4773 std::string &SuggestedModifier) const override { 4774 bool isOutput = (Constraint[0] == '='); 4775 bool isInOut = (Constraint[0] == '+'); 4776 4777 // Strip off constraint modifiers. 4778 while (Constraint[0] == '=' || 4779 Constraint[0] == '+' || 4780 Constraint[0] == '&') 4781 Constraint = Constraint.substr(1); 4782 4783 switch (Constraint[0]) { 4784 default: break; 4785 case 'r': { 4786 switch (Modifier) { 4787 default: 4788 return (isInOut || isOutput || Size <= 64); 4789 case 'q': 4790 // A register of size 32 cannot fit a vector type. 4791 return false; 4792 } 4793 } 4794 } 4795 4796 return true; 4797 } 4798 const char *getClobbers() const override { 4799 // FIXME: Is this really right? 4800 return ""; 4801 } 4802 4803 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4804 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4805 } 4806 4807 int getEHDataRegisterNumber(unsigned RegNo) const override { 4808 if (RegNo == 0) return 0; 4809 if (RegNo == 1) return 1; 4810 return -1; 4811 } 4812 4813 bool hasSjLjLowering() const override { 4814 return true; 4815 } 4816 }; 4817 4818 bool ARMTargetInfo::setFPMath(StringRef Name) { 4819 if (Name == "neon") { 4820 FPMath = FP_Neon; 4821 return true; 4822 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4823 Name == "vfp4") { 4824 FPMath = FP_VFP; 4825 return true; 4826 } 4827 return false; 4828 } 4829 4830 const char * const ARMTargetInfo::GCCRegNames[] = { 4831 // Integer registers 4832 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4833 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4834 4835 // Float registers 4836 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4837 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4838 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4839 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4840 4841 // Double registers 4842 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4843 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4844 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4845 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4846 4847 // Quad registers 4848 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4849 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4850 }; 4851 4852 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4853 unsigned &NumNames) const { 4854 Names = GCCRegNames; 4855 NumNames = llvm::array_lengthof(GCCRegNames); 4856 } 4857 4858 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4859 { { "a1" }, "r0" }, 4860 { { "a2" }, "r1" }, 4861 { { "a3" }, "r2" }, 4862 { { "a4" }, "r3" }, 4863 { { "v1" }, "r4" }, 4864 { { "v2" }, "r5" }, 4865 { { "v3" }, "r6" }, 4866 { { "v4" }, "r7" }, 4867 { { "v5" }, "r8" }, 4868 { { "v6", "rfp" }, "r9" }, 4869 { { "sl" }, "r10" }, 4870 { { "fp" }, "r11" }, 4871 { { "ip" }, "r12" }, 4872 { { "r13" }, "sp" }, 4873 { { "r14" }, "lr" }, 4874 { { "r15" }, "pc" }, 4875 // The S, D and Q registers overlap, but aren't really aliases; we 4876 // don't want to substitute one of these for a different-sized one. 4877 }; 4878 4879 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4880 unsigned &NumAliases) const { 4881 Aliases = GCCRegAliases; 4882 NumAliases = llvm::array_lengthof(GCCRegAliases); 4883 } 4884 4885 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4886 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4887 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4888 ALL_LANGUAGES }, 4889 #include "clang/Basic/BuiltinsNEON.def" 4890 4891 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4892 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG }, 4893 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4894 ALL_LANGUAGES }, 4895 #include "clang/Basic/BuiltinsARM.def" 4896 }; 4897 4898 class ARMleTargetInfo : public ARMTargetInfo { 4899 public: 4900 ARMleTargetInfo(const llvm::Triple &Triple) 4901 : ARMTargetInfo(Triple, false) { } 4902 void getTargetDefines(const LangOptions &Opts, 4903 MacroBuilder &Builder) const override { 4904 Builder.defineMacro("__ARMEL__"); 4905 ARMTargetInfo::getTargetDefines(Opts, Builder); 4906 } 4907 }; 4908 4909 class ARMbeTargetInfo : public ARMTargetInfo { 4910 public: 4911 ARMbeTargetInfo(const llvm::Triple &Triple) 4912 : ARMTargetInfo(Triple, true) { } 4913 void getTargetDefines(const LangOptions &Opts, 4914 MacroBuilder &Builder) const override { 4915 Builder.defineMacro("__ARMEB__"); 4916 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4917 ARMTargetInfo::getTargetDefines(Opts, Builder); 4918 } 4919 }; 4920 4921 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 4922 const llvm::Triple Triple; 4923 public: 4924 WindowsARMTargetInfo(const llvm::Triple &Triple) 4925 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 4926 TLSSupported = false; 4927 WCharType = UnsignedShort; 4928 SizeType = UnsignedInt; 4929 UserLabelPrefix = ""; 4930 } 4931 void getVisualStudioDefines(const LangOptions &Opts, 4932 MacroBuilder &Builder) const { 4933 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 4934 4935 // FIXME: this is invalid for WindowsCE 4936 Builder.defineMacro("_M_ARM_NT", "1"); 4937 Builder.defineMacro("_M_ARMT", "_M_ARM"); 4938 Builder.defineMacro("_M_THUMB", "_M_ARM"); 4939 4940 assert((Triple.getArch() == llvm::Triple::arm || 4941 Triple.getArch() == llvm::Triple::thumb) && 4942 "invalid architecture for Windows ARM target info"); 4943 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 4944 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 4945 4946 // TODO map the complete set of values 4947 // 31: VFPv3 40: VFPv4 4948 Builder.defineMacro("_M_ARM_FP", "31"); 4949 } 4950 BuiltinVaListKind getBuiltinVaListKind() const override { 4951 return TargetInfo::CharPtrBuiltinVaList; 4952 } 4953 }; 4954 4955 // Windows ARM + Itanium C++ ABI Target 4956 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 4957 public: 4958 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 4959 : WindowsARMTargetInfo(Triple) { 4960 TheCXXABI.set(TargetCXXABI::GenericARM); 4961 } 4962 4963 void getTargetDefines(const LangOptions &Opts, 4964 MacroBuilder &Builder) const override { 4965 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4966 4967 if (Opts.MSVCCompat) 4968 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4969 } 4970 }; 4971 4972 // Windows ARM, MS (C++) ABI 4973 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 4974 public: 4975 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 4976 : WindowsARMTargetInfo(Triple) { 4977 TheCXXABI.set(TargetCXXABI::Microsoft); 4978 } 4979 4980 void getTargetDefines(const LangOptions &Opts, 4981 MacroBuilder &Builder) const override { 4982 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4983 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4984 } 4985 }; 4986 4987 // ARM MinGW target 4988 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 4989 public: 4990 MinGWARMTargetInfo(const llvm::Triple &Triple) 4991 : WindowsARMTargetInfo(Triple) { 4992 TheCXXABI.set(TargetCXXABI::GenericARM); 4993 } 4994 4995 void getTargetDefines(const LangOptions &Opts, 4996 MacroBuilder &Builder) const override { 4997 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4998 DefineStd(Builder, "WIN32", Opts); 4999 DefineStd(Builder, "WINNT", Opts); 5000 Builder.defineMacro("_ARM_"); 5001 addMinGWDefines(Opts, Builder); 5002 } 5003 }; 5004 5005 // ARM Cygwin target 5006 class CygwinARMTargetInfo : public ARMleTargetInfo { 5007 public: 5008 CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) { 5009 TLSSupported = false; 5010 WCharType = UnsignedShort; 5011 DoubleAlign = LongLongAlign = 64; 5012 DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 5013 } 5014 void getTargetDefines(const LangOptions &Opts, 5015 MacroBuilder &Builder) const override { 5016 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5017 Builder.defineMacro("_ARM_"); 5018 Builder.defineMacro("__CYGWIN__"); 5019 Builder.defineMacro("__CYGWIN32__"); 5020 DefineStd(Builder, "unix", Opts); 5021 if (Opts.CPlusPlus) 5022 Builder.defineMacro("_GNU_SOURCE"); 5023 } 5024 }; 5025 5026 class DarwinARMTargetInfo : 5027 public DarwinTargetInfo<ARMleTargetInfo> { 5028 protected: 5029 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5030 MacroBuilder &Builder) const override { 5031 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5032 } 5033 5034 public: 5035 DarwinARMTargetInfo(const llvm::Triple &Triple) 5036 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 5037 HasAlignMac68kSupport = true; 5038 // iOS always has 64-bit atomic instructions. 5039 // FIXME: This should be based off of the target features in 5040 // ARMleTargetInfo. 5041 MaxAtomicInlineWidth = 64; 5042 5043 // Darwin on iOS uses a variant of the ARM C++ ABI. 5044 TheCXXABI.set(TargetCXXABI::iOS); 5045 } 5046 }; 5047 5048 class AArch64TargetInfo : public TargetInfo { 5049 virtual void setDescriptionString() = 0; 5050 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5051 static const char *const GCCRegNames[]; 5052 5053 enum FPUModeEnum { 5054 FPUMode, 5055 NeonMode 5056 }; 5057 5058 unsigned FPU; 5059 unsigned CRC; 5060 unsigned Crypto; 5061 5062 static const Builtin::Info BuiltinInfo[]; 5063 5064 std::string ABI; 5065 5066 public: 5067 AArch64TargetInfo(const llvm::Triple &Triple) 5068 : TargetInfo(Triple), ABI("aapcs") { 5069 5070 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5071 WCharType = SignedInt; 5072 5073 // NetBSD apparently prefers consistency across ARM targets to consistency 5074 // across 64-bit targets. 5075 Int64Type = SignedLongLong; 5076 IntMaxType = SignedLongLong; 5077 } else { 5078 WCharType = UnsignedInt; 5079 Int64Type = SignedLong; 5080 IntMaxType = SignedLong; 5081 } 5082 5083 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5084 MaxVectorAlign = 128; 5085 RegParmMax = 8; 5086 MaxAtomicInlineWidth = 128; 5087 MaxAtomicPromoteWidth = 128; 5088 5089 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5090 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5091 5092 // {} in inline assembly are neon specifiers, not assembly variant 5093 // specifiers. 5094 NoAsmVariants = true; 5095 5096 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5097 // contributes to the alignment of the containing aggregate in the same way 5098 // a plain (non bit-field) member of that type would, without exception for 5099 // zero-sized or anonymous bit-fields." 5100 UseBitFieldTypeAlignment = true; 5101 UseZeroLengthBitfieldAlignment = true; 5102 5103 // AArch64 targets default to using the ARM C++ ABI. 5104 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5105 } 5106 5107 StringRef getABI() const override { return ABI; } 5108 bool setABI(const std::string &Name) override { 5109 if (Name != "aapcs" && Name != "darwinpcs") 5110 return false; 5111 5112 ABI = Name; 5113 return true; 5114 } 5115 5116 bool setCPU(const std::string &Name) override { 5117 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5118 .Case("generic", true) 5119 .Cases("cortex-a53", "cortex-a57", "cortex-a72", true) 5120 .Case("cyclone", true) 5121 .Default(false); 5122 return CPUKnown; 5123 } 5124 5125 void getTargetDefines(const LangOptions &Opts, 5126 MacroBuilder &Builder) const override { 5127 // Target identification. 5128 Builder.defineMacro("__aarch64__"); 5129 5130 // Target properties. 5131 Builder.defineMacro("_LP64"); 5132 Builder.defineMacro("__LP64__"); 5133 5134 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5135 Builder.defineMacro("__ARM_ACLE", "200"); 5136 Builder.defineMacro("__ARM_ARCH", "8"); 5137 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5138 5139 Builder.defineMacro("__ARM_64BIT_STATE"); 5140 Builder.defineMacro("__ARM_PCS_AAPCS64"); 5141 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 5142 5143 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 5144 Builder.defineMacro("__ARM_FEATURE_CLZ"); 5145 Builder.defineMacro("__ARM_FEATURE_FMA"); 5146 Builder.defineMacro("__ARM_FEATURE_DIV"); 5147 Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE 5148 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5149 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 5150 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 5151 5152 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5153 5154 // 0xe implies support for half, single and double precision operations. 5155 Builder.defineMacro("__ARM_FP", "0xe"); 5156 5157 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5158 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5159 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 5160 5161 if (Opts.FastMath || Opts.FiniteMathOnly) 5162 Builder.defineMacro("__ARM_FP_FAST"); 5163 5164 if (Opts.C99 && !Opts.Freestanding) 5165 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 5166 5167 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5168 5169 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5170 Opts.ShortEnums ? "1" : "4"); 5171 5172 if (FPU == NeonMode) { 5173 Builder.defineMacro("__ARM_NEON"); 5174 // 64-bit NEON supports half, single and double precision operations. 5175 Builder.defineMacro("__ARM_NEON_FP", "0xe"); 5176 } 5177 5178 if (CRC) 5179 Builder.defineMacro("__ARM_FEATURE_CRC32"); 5180 5181 if (Crypto) 5182 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 5183 5184 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5185 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5186 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5187 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5188 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5189 } 5190 5191 void getTargetBuiltins(const Builtin::Info *&Records, 5192 unsigned &NumRecords) const override { 5193 Records = BuiltinInfo; 5194 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin; 5195 } 5196 5197 bool hasFeature(StringRef Feature) const override { 5198 return Feature == "aarch64" || 5199 Feature == "arm64" || 5200 (Feature == "neon" && FPU == NeonMode); 5201 } 5202 5203 bool handleTargetFeatures(std::vector<std::string> &Features, 5204 DiagnosticsEngine &Diags) override { 5205 FPU = FPUMode; 5206 CRC = 0; 5207 Crypto = 0; 5208 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 5209 if (Features[i] == "+neon") 5210 FPU = NeonMode; 5211 if (Features[i] == "+crc") 5212 CRC = 1; 5213 if (Features[i] == "+crypto") 5214 Crypto = 1; 5215 } 5216 5217 setDescriptionString(); 5218 5219 return true; 5220 } 5221 5222 bool isCLZForZeroUndef() const override { return false; } 5223 5224 BuiltinVaListKind getBuiltinVaListKind() const override { 5225 return TargetInfo::AArch64ABIBuiltinVaList; 5226 } 5227 5228 void getGCCRegNames(const char *const *&Names, 5229 unsigned &NumNames) const override; 5230 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5231 unsigned &NumAliases) const override; 5232 5233 bool validateAsmConstraint(const char *&Name, 5234 TargetInfo::ConstraintInfo &Info) const override { 5235 switch (*Name) { 5236 default: 5237 return false; 5238 case 'w': // Floating point and SIMD registers (V0-V31) 5239 Info.setAllowsRegister(); 5240 return true; 5241 case 'I': // Constant that can be used with an ADD instruction 5242 case 'J': // Constant that can be used with a SUB instruction 5243 case 'K': // Constant that can be used with a 32-bit logical instruction 5244 case 'L': // Constant that can be used with a 64-bit logical instruction 5245 case 'M': // Constant that can be used as a 32-bit MOV immediate 5246 case 'N': // Constant that can be used as a 64-bit MOV immediate 5247 case 'Y': // Floating point constant zero 5248 case 'Z': // Integer constant zero 5249 return true; 5250 case 'Q': // A memory reference with base register and no offset 5251 Info.setAllowsMemory(); 5252 return true; 5253 case 'S': // A symbolic address 5254 Info.setAllowsRegister(); 5255 return true; 5256 case 'U': 5257 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5258 // Utf: A memory address suitable for ldp/stp in TF mode. 5259 // Usa: An absolute symbolic address. 5260 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5261 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5262 case 'z': // Zero register, wzr or xzr 5263 Info.setAllowsRegister(); 5264 return true; 5265 case 'x': // Floating point and SIMD registers (V0-V15) 5266 Info.setAllowsRegister(); 5267 return true; 5268 } 5269 return false; 5270 } 5271 5272 bool 5273 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5274 std::string &SuggestedModifier) const override { 5275 // Strip off constraint modifiers. 5276 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5277 Constraint = Constraint.substr(1); 5278 5279 switch (Constraint[0]) { 5280 default: 5281 return true; 5282 case 'z': 5283 case 'r': { 5284 switch (Modifier) { 5285 case 'x': 5286 case 'w': 5287 // For now assume that the person knows what they're 5288 // doing with the modifier. 5289 return true; 5290 default: 5291 // By default an 'r' constraint will be in the 'x' 5292 // registers. 5293 if (Size == 64) 5294 return true; 5295 5296 SuggestedModifier = "w"; 5297 return false; 5298 } 5299 } 5300 } 5301 } 5302 5303 const char *getClobbers() const override { return ""; } 5304 5305 int getEHDataRegisterNumber(unsigned RegNo) const override { 5306 if (RegNo == 0) 5307 return 0; 5308 if (RegNo == 1) 5309 return 1; 5310 return -1; 5311 } 5312 }; 5313 5314 const char *const AArch64TargetInfo::GCCRegNames[] = { 5315 // 32-bit Integer registers 5316 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5317 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5318 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5319 5320 // 64-bit Integer registers 5321 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5322 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5323 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5324 5325 // 32-bit floating point regsisters 5326 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5327 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5328 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5329 5330 // 64-bit floating point regsisters 5331 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5332 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5333 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5334 5335 // Vector registers 5336 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5337 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5338 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5339 }; 5340 5341 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names, 5342 unsigned &NumNames) const { 5343 Names = GCCRegNames; 5344 NumNames = llvm::array_lengthof(GCCRegNames); 5345 } 5346 5347 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5348 { { "w31" }, "wsp" }, 5349 { { "x29" }, "fp" }, 5350 { { "x30" }, "lr" }, 5351 { { "x31" }, "sp" }, 5352 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5353 // don't want to substitute one of these for a different-sized one. 5354 }; 5355 5356 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5357 unsigned &NumAliases) const { 5358 Aliases = GCCRegAliases; 5359 NumAliases = llvm::array_lengthof(GCCRegAliases); 5360 } 5361 5362 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5363 #define BUILTIN(ID, TYPE, ATTRS) \ 5364 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5365 #include "clang/Basic/BuiltinsNEON.def" 5366 5367 #define BUILTIN(ID, TYPE, ATTRS) \ 5368 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5369 #include "clang/Basic/BuiltinsAArch64.def" 5370 }; 5371 5372 class AArch64leTargetInfo : public AArch64TargetInfo { 5373 void setDescriptionString() override { 5374 if (getTriple().isOSBinFormatMachO()) 5375 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128"; 5376 else 5377 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 5378 } 5379 5380 public: 5381 AArch64leTargetInfo(const llvm::Triple &Triple) 5382 : AArch64TargetInfo(Triple) { 5383 BigEndian = false; 5384 } 5385 void getTargetDefines(const LangOptions &Opts, 5386 MacroBuilder &Builder) const override { 5387 Builder.defineMacro("__AARCH64EL__"); 5388 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5389 } 5390 }; 5391 5392 class AArch64beTargetInfo : public AArch64TargetInfo { 5393 void setDescriptionString() override { 5394 assert(!getTriple().isOSBinFormatMachO()); 5395 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5396 } 5397 5398 public: 5399 AArch64beTargetInfo(const llvm::Triple &Triple) 5400 : AArch64TargetInfo(Triple) { } 5401 void getTargetDefines(const LangOptions &Opts, 5402 MacroBuilder &Builder) const override { 5403 Builder.defineMacro("__AARCH64EB__"); 5404 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5405 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5406 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5407 } 5408 }; 5409 5410 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5411 protected: 5412 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5413 MacroBuilder &Builder) const override { 5414 Builder.defineMacro("__AARCH64_SIMD__"); 5415 Builder.defineMacro("__ARM64_ARCH_8__"); 5416 Builder.defineMacro("__ARM_NEON__"); 5417 Builder.defineMacro("__LITTLE_ENDIAN__"); 5418 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5419 Builder.defineMacro("__arm64", "1"); 5420 Builder.defineMacro("__arm64__", "1"); 5421 5422 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5423 } 5424 5425 public: 5426 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5427 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5428 Int64Type = SignedLongLong; 5429 WCharType = SignedInt; 5430 UseSignedCharForObjCBool = false; 5431 5432 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5433 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5434 5435 TheCXXABI.set(TargetCXXABI::iOS64); 5436 } 5437 5438 BuiltinVaListKind getBuiltinVaListKind() const override { 5439 return TargetInfo::CharPtrBuiltinVaList; 5440 } 5441 }; 5442 5443 // Hexagon abstract base class 5444 class HexagonTargetInfo : public TargetInfo { 5445 static const Builtin::Info BuiltinInfo[]; 5446 static const char * const GCCRegNames[]; 5447 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5448 std::string CPU; 5449 public: 5450 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5451 BigEndian = false; 5452 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 5453 5454 // {} in inline assembly are packet specifiers, not assembly variant 5455 // specifiers. 5456 NoAsmVariants = true; 5457 } 5458 5459 void getTargetBuiltins(const Builtin::Info *&Records, 5460 unsigned &NumRecords) const override { 5461 Records = BuiltinInfo; 5462 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 5463 } 5464 5465 bool validateAsmConstraint(const char *&Name, 5466 TargetInfo::ConstraintInfo &Info) const override { 5467 return true; 5468 } 5469 5470 void getTargetDefines(const LangOptions &Opts, 5471 MacroBuilder &Builder) const override; 5472 5473 bool hasFeature(StringRef Feature) const override { 5474 return Feature == "hexagon"; 5475 } 5476 5477 BuiltinVaListKind getBuiltinVaListKind() const override { 5478 return TargetInfo::CharPtrBuiltinVaList; 5479 } 5480 void getGCCRegNames(const char * const *&Names, 5481 unsigned &NumNames) const override; 5482 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5483 unsigned &NumAliases) const override; 5484 const char *getClobbers() const override { 5485 return ""; 5486 } 5487 5488 static const char *getHexagonCPUSuffix(StringRef Name) { 5489 return llvm::StringSwitch<const char*>(Name) 5490 .Case("hexagonv4", "4") 5491 .Case("hexagonv5", "5") 5492 .Default(nullptr); 5493 } 5494 5495 bool setCPU(const std::string &Name) override { 5496 if (!getHexagonCPUSuffix(Name)) 5497 return false; 5498 5499 CPU = Name; 5500 return true; 5501 } 5502 }; 5503 5504 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5505 MacroBuilder &Builder) const { 5506 Builder.defineMacro("qdsp6"); 5507 Builder.defineMacro("__qdsp6", "1"); 5508 Builder.defineMacro("__qdsp6__", "1"); 5509 5510 Builder.defineMacro("hexagon"); 5511 Builder.defineMacro("__hexagon", "1"); 5512 Builder.defineMacro("__hexagon__", "1"); 5513 5514 if(CPU == "hexagonv1") { 5515 Builder.defineMacro("__HEXAGON_V1__"); 5516 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 5517 if(Opts.HexagonQdsp6Compat) { 5518 Builder.defineMacro("__QDSP6_V1__"); 5519 Builder.defineMacro("__QDSP6_ARCH__", "1"); 5520 } 5521 } 5522 else if(CPU == "hexagonv2") { 5523 Builder.defineMacro("__HEXAGON_V2__"); 5524 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 5525 if(Opts.HexagonQdsp6Compat) { 5526 Builder.defineMacro("__QDSP6_V2__"); 5527 Builder.defineMacro("__QDSP6_ARCH__", "2"); 5528 } 5529 } 5530 else if(CPU == "hexagonv3") { 5531 Builder.defineMacro("__HEXAGON_V3__"); 5532 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 5533 if(Opts.HexagonQdsp6Compat) { 5534 Builder.defineMacro("__QDSP6_V3__"); 5535 Builder.defineMacro("__QDSP6_ARCH__", "3"); 5536 } 5537 } 5538 else if(CPU == "hexagonv4") { 5539 Builder.defineMacro("__HEXAGON_V4__"); 5540 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5541 if(Opts.HexagonQdsp6Compat) { 5542 Builder.defineMacro("__QDSP6_V4__"); 5543 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5544 } 5545 } 5546 else if(CPU == "hexagonv5") { 5547 Builder.defineMacro("__HEXAGON_V5__"); 5548 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5549 if(Opts.HexagonQdsp6Compat) { 5550 Builder.defineMacro("__QDSP6_V5__"); 5551 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5552 } 5553 } 5554 } 5555 5556 const char * const HexagonTargetInfo::GCCRegNames[] = { 5557 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5558 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5559 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5560 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5561 "p0", "p1", "p2", "p3", 5562 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5563 }; 5564 5565 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 5566 unsigned &NumNames) const { 5567 Names = GCCRegNames; 5568 NumNames = llvm::array_lengthof(GCCRegNames); 5569 } 5570 5571 5572 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5573 { { "sp" }, "r29" }, 5574 { { "fp" }, "r30" }, 5575 { { "lr" }, "r31" }, 5576 }; 5577 5578 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5579 unsigned &NumAliases) const { 5580 Aliases = GCCRegAliases; 5581 NumAliases = llvm::array_lengthof(GCCRegAliases); 5582 } 5583 5584 5585 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5586 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5587 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5588 ALL_LANGUAGES }, 5589 #include "clang/Basic/BuiltinsHexagon.def" 5590 }; 5591 5592 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5593 class SparcTargetInfo : public TargetInfo { 5594 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5595 static const char * const GCCRegNames[]; 5596 bool SoftFloat; 5597 public: 5598 SparcTargetInfo(const llvm::Triple &Triple) 5599 : TargetInfo(Triple), SoftFloat(false) {} 5600 5601 bool handleTargetFeatures(std::vector<std::string> &Features, 5602 DiagnosticsEngine &Diags) override { 5603 // The backend doesn't actually handle soft float yet, but in case someone 5604 // is using the support for the front end continue to support it. 5605 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 5606 if (Feature != Features.end()) { 5607 SoftFloat = true; 5608 Features.erase(Feature); 5609 } 5610 return true; 5611 } 5612 void getTargetDefines(const LangOptions &Opts, 5613 MacroBuilder &Builder) const override { 5614 DefineStd(Builder, "sparc", Opts); 5615 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5616 5617 if (SoftFloat) 5618 Builder.defineMacro("SOFT_FLOAT", "1"); 5619 } 5620 5621 bool hasFeature(StringRef Feature) const override { 5622 return llvm::StringSwitch<bool>(Feature) 5623 .Case("softfloat", SoftFloat) 5624 .Case("sparc", true) 5625 .Default(false); 5626 } 5627 5628 void getTargetBuiltins(const Builtin::Info *&Records, 5629 unsigned &NumRecords) const override { 5630 // FIXME: Implement! 5631 } 5632 BuiltinVaListKind getBuiltinVaListKind() const override { 5633 return TargetInfo::VoidPtrBuiltinVaList; 5634 } 5635 void getGCCRegNames(const char * const *&Names, 5636 unsigned &NumNames) const override; 5637 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5638 unsigned &NumAliases) const override; 5639 bool validateAsmConstraint(const char *&Name, 5640 TargetInfo::ConstraintInfo &info) const override { 5641 // FIXME: Implement! 5642 switch (*Name) { 5643 case 'I': // Signed 13-bit constant 5644 case 'J': // Zero 5645 case 'K': // 32-bit constant with the low 12 bits clear 5646 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5647 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5648 case 'N': // Same as 'K' but zext (required for SIMode) 5649 case 'O': // The constant 4096 5650 return true; 5651 } 5652 return false; 5653 } 5654 const char *getClobbers() const override { 5655 // FIXME: Implement! 5656 return ""; 5657 } 5658 }; 5659 5660 const char * const SparcTargetInfo::GCCRegNames[] = { 5661 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5662 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5663 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5664 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5665 }; 5666 5667 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 5668 unsigned &NumNames) const { 5669 Names = GCCRegNames; 5670 NumNames = llvm::array_lengthof(GCCRegNames); 5671 } 5672 5673 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5674 { { "g0" }, "r0" }, 5675 { { "g1" }, "r1" }, 5676 { { "g2" }, "r2" }, 5677 { { "g3" }, "r3" }, 5678 { { "g4" }, "r4" }, 5679 { { "g5" }, "r5" }, 5680 { { "g6" }, "r6" }, 5681 { { "g7" }, "r7" }, 5682 { { "o0" }, "r8" }, 5683 { { "o1" }, "r9" }, 5684 { { "o2" }, "r10" }, 5685 { { "o3" }, "r11" }, 5686 { { "o4" }, "r12" }, 5687 { { "o5" }, "r13" }, 5688 { { "o6", "sp" }, "r14" }, 5689 { { "o7" }, "r15" }, 5690 { { "l0" }, "r16" }, 5691 { { "l1" }, "r17" }, 5692 { { "l2" }, "r18" }, 5693 { { "l3" }, "r19" }, 5694 { { "l4" }, "r20" }, 5695 { { "l5" }, "r21" }, 5696 { { "l6" }, "r22" }, 5697 { { "l7" }, "r23" }, 5698 { { "i0" }, "r24" }, 5699 { { "i1" }, "r25" }, 5700 { { "i2" }, "r26" }, 5701 { { "i3" }, "r27" }, 5702 { { "i4" }, "r28" }, 5703 { { "i5" }, "r29" }, 5704 { { "i6", "fp" }, "r30" }, 5705 { { "i7" }, "r31" }, 5706 }; 5707 5708 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5709 unsigned &NumAliases) const { 5710 Aliases = GCCRegAliases; 5711 NumAliases = llvm::array_lengthof(GCCRegAliases); 5712 } 5713 5714 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5715 class SparcV8TargetInfo : public SparcTargetInfo { 5716 public: 5717 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5718 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5719 // NetBSD uses long (same as llvm default); everyone else uses int. 5720 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5721 SizeType = UnsignedLong; 5722 IntPtrType = SignedLong; 5723 PtrDiffType = SignedLong; 5724 } else { 5725 SizeType = UnsignedInt; 5726 IntPtrType = SignedInt; 5727 PtrDiffType = SignedInt; 5728 } 5729 } 5730 5731 void getTargetDefines(const LangOptions &Opts, 5732 MacroBuilder &Builder) const override { 5733 SparcTargetInfo::getTargetDefines(Opts, Builder); 5734 Builder.defineMacro("__sparcv8"); 5735 } 5736 }; 5737 5738 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 5739 class SparcV8elTargetInfo : public SparcV8TargetInfo { 5740 public: 5741 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 5742 DescriptionString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5743 BigEndian = false; 5744 } 5745 }; 5746 5747 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 5748 class SparcV9TargetInfo : public SparcTargetInfo { 5749 public: 5750 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5751 // FIXME: Support Sparc quad-precision long double? 5752 DescriptionString = "E-m:e-i64:64-n32:64-S128"; 5753 // This is an LP64 platform. 5754 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5755 5756 // OpenBSD uses long long for int64_t and intmax_t. 5757 if (getTriple().getOS() == llvm::Triple::OpenBSD) 5758 IntMaxType = SignedLongLong; 5759 else 5760 IntMaxType = SignedLong; 5761 Int64Type = IntMaxType; 5762 5763 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 5764 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 5765 LongDoubleWidth = 128; 5766 LongDoubleAlign = 128; 5767 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5768 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5769 } 5770 5771 void getTargetDefines(const LangOptions &Opts, 5772 MacroBuilder &Builder) const override { 5773 SparcTargetInfo::getTargetDefines(Opts, Builder); 5774 Builder.defineMacro("__sparcv9"); 5775 Builder.defineMacro("__arch64__"); 5776 // Solaris doesn't need these variants, but the BSDs do. 5777 if (getTriple().getOS() != llvm::Triple::Solaris) { 5778 Builder.defineMacro("__sparc64__"); 5779 Builder.defineMacro("__sparc_v9__"); 5780 Builder.defineMacro("__sparcv9__"); 5781 } 5782 } 5783 5784 bool setCPU(const std::string &Name) override { 5785 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5786 .Case("v9", true) 5787 .Case("ultrasparc", true) 5788 .Case("ultrasparc3", true) 5789 .Case("niagara", true) 5790 .Case("niagara2", true) 5791 .Case("niagara3", true) 5792 .Case("niagara4", true) 5793 .Default(false); 5794 5795 // No need to store the CPU yet. There aren't any CPU-specific 5796 // macros to define. 5797 return CPUKnown; 5798 } 5799 }; 5800 5801 class SystemZTargetInfo : public TargetInfo { 5802 static const Builtin::Info BuiltinInfo[]; 5803 static const char *const GCCRegNames[]; 5804 std::string CPU; 5805 bool HasTransactionalExecution; 5806 bool HasVector; 5807 5808 public: 5809 SystemZTargetInfo(const llvm::Triple &Triple) 5810 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), HasVector(false) { 5811 IntMaxType = SignedLong; 5812 Int64Type = SignedLong; 5813 TLSSupported = true; 5814 IntWidth = IntAlign = 32; 5815 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5816 PointerWidth = PointerAlign = 64; 5817 LongDoubleWidth = 128; 5818 LongDoubleAlign = 64; 5819 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5820 DefaultAlignForAttributeAligned = 64; 5821 MinGlobalAlign = 16; 5822 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5823 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5824 } 5825 void getTargetDefines(const LangOptions &Opts, 5826 MacroBuilder &Builder) const override { 5827 Builder.defineMacro("__s390__"); 5828 Builder.defineMacro("__s390x__"); 5829 Builder.defineMacro("__zarch__"); 5830 Builder.defineMacro("__LONG_DOUBLE_128__"); 5831 if (HasTransactionalExecution) 5832 Builder.defineMacro("__HTM__"); 5833 } 5834 void getTargetBuiltins(const Builtin::Info *&Records, 5835 unsigned &NumRecords) const override { 5836 Records = BuiltinInfo; 5837 NumRecords = clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin; 5838 } 5839 5840 void getGCCRegNames(const char *const *&Names, 5841 unsigned &NumNames) const override; 5842 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5843 unsigned &NumAliases) const override { 5844 // No aliases. 5845 Aliases = nullptr; 5846 NumAliases = 0; 5847 } 5848 bool validateAsmConstraint(const char *&Name, 5849 TargetInfo::ConstraintInfo &info) const override; 5850 const char *getClobbers() const override { 5851 // FIXME: Is this really right? 5852 return ""; 5853 } 5854 BuiltinVaListKind getBuiltinVaListKind() const override { 5855 return TargetInfo::SystemZBuiltinVaList; 5856 } 5857 bool setCPU(const std::string &Name) override { 5858 CPU = Name; 5859 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5860 .Case("z10", true) 5861 .Case("z196", true) 5862 .Case("zEC12", true) 5863 .Case("z13", true) 5864 .Default(false); 5865 5866 return CPUKnown; 5867 } 5868 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5869 if (CPU == "zEC12") 5870 Features["transactional-execution"] = true; 5871 if (CPU == "z13") { 5872 Features["transactional-execution"] = true; 5873 Features["vector"] = true; 5874 } 5875 } 5876 5877 bool handleTargetFeatures(std::vector<std::string> &Features, 5878 DiagnosticsEngine &Diags) override { 5879 HasTransactionalExecution = false; 5880 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 5881 if (Features[i] == "+transactional-execution") 5882 HasTransactionalExecution = true; 5883 if (Features[i] == "+vector") 5884 HasVector = true; 5885 } 5886 // If we use the vector ABI, vector types are 64-bit aligned. 5887 if (HasVector) { 5888 MaxVectorAlign = 64; 5889 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 5890 "-v128:64-a:8:16-n32:64"; 5891 } 5892 return true; 5893 } 5894 5895 bool hasFeature(StringRef Feature) const override { 5896 return llvm::StringSwitch<bool>(Feature) 5897 .Case("systemz", true) 5898 .Case("htm", HasTransactionalExecution) 5899 .Case("vx", HasVector) 5900 .Default(false); 5901 } 5902 5903 StringRef getABI() const override { 5904 if (HasVector) 5905 return "vector"; 5906 return ""; 5907 } 5908 5909 bool useFloat128ManglingForLongDouble() const override { 5910 return true; 5911 } 5912 }; 5913 5914 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 5915 #define BUILTIN(ID, TYPE, ATTRS) \ 5916 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5917 #include "clang/Basic/BuiltinsSystemZ.def" 5918 }; 5919 5920 const char *const SystemZTargetInfo::GCCRegNames[] = { 5921 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5922 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5923 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 5924 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 5925 }; 5926 5927 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 5928 unsigned &NumNames) const { 5929 Names = GCCRegNames; 5930 NumNames = llvm::array_lengthof(GCCRegNames); 5931 } 5932 5933 bool SystemZTargetInfo:: 5934 validateAsmConstraint(const char *&Name, 5935 TargetInfo::ConstraintInfo &Info) const { 5936 switch (*Name) { 5937 default: 5938 return false; 5939 5940 case 'a': // Address register 5941 case 'd': // Data register (equivalent to 'r') 5942 case 'f': // Floating-point register 5943 Info.setAllowsRegister(); 5944 return true; 5945 5946 case 'I': // Unsigned 8-bit constant 5947 case 'J': // Unsigned 12-bit constant 5948 case 'K': // Signed 16-bit constant 5949 case 'L': // Signed 20-bit displacement (on all targets we support) 5950 case 'M': // 0x7fffffff 5951 return true; 5952 5953 case 'Q': // Memory with base and unsigned 12-bit displacement 5954 case 'R': // Likewise, plus an index 5955 case 'S': // Memory with base and signed 20-bit displacement 5956 case 'T': // Likewise, plus an index 5957 Info.setAllowsMemory(); 5958 return true; 5959 } 5960 } 5961 5962 class MSP430TargetInfo : public TargetInfo { 5963 static const char * const GCCRegNames[]; 5964 public: 5965 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5966 BigEndian = false; 5967 TLSSupported = false; 5968 IntWidth = 16; IntAlign = 16; 5969 LongWidth = 32; LongLongWidth = 64; 5970 LongAlign = LongLongAlign = 16; 5971 PointerWidth = 16; PointerAlign = 16; 5972 SuitableAlign = 16; 5973 SizeType = UnsignedInt; 5974 IntMaxType = SignedLongLong; 5975 IntPtrType = SignedInt; 5976 PtrDiffType = SignedInt; 5977 SigAtomicType = SignedLong; 5978 DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 5979 } 5980 void getTargetDefines(const LangOptions &Opts, 5981 MacroBuilder &Builder) const override { 5982 Builder.defineMacro("MSP430"); 5983 Builder.defineMacro("__MSP430__"); 5984 // FIXME: defines for different 'flavours' of MCU 5985 } 5986 void getTargetBuiltins(const Builtin::Info *&Records, 5987 unsigned &NumRecords) const override { 5988 // FIXME: Implement. 5989 Records = nullptr; 5990 NumRecords = 0; 5991 } 5992 bool hasFeature(StringRef Feature) const override { 5993 return Feature == "msp430"; 5994 } 5995 void getGCCRegNames(const char * const *&Names, 5996 unsigned &NumNames) const override; 5997 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5998 unsigned &NumAliases) const override { 5999 // No aliases. 6000 Aliases = nullptr; 6001 NumAliases = 0; 6002 } 6003 bool 6004 validateAsmConstraint(const char *&Name, 6005 TargetInfo::ConstraintInfo &info) const override { 6006 // FIXME: implement 6007 switch (*Name) { 6008 case 'K': // the constant 1 6009 case 'L': // constant -1^20 .. 1^19 6010 case 'M': // constant 1-4: 6011 return true; 6012 } 6013 // No target constraints for now. 6014 return false; 6015 } 6016 const char *getClobbers() const override { 6017 // FIXME: Is this really right? 6018 return ""; 6019 } 6020 BuiltinVaListKind getBuiltinVaListKind() const override { 6021 // FIXME: implement 6022 return TargetInfo::CharPtrBuiltinVaList; 6023 } 6024 }; 6025 6026 const char * const MSP430TargetInfo::GCCRegNames[] = { 6027 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6028 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 6029 }; 6030 6031 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 6032 unsigned &NumNames) const { 6033 Names = GCCRegNames; 6034 NumNames = llvm::array_lengthof(GCCRegNames); 6035 } 6036 6037 // LLVM and Clang cannot be used directly to output native binaries for 6038 // target, but is used to compile C code to llvm bitcode with correct 6039 // type and alignment information. 6040 // 6041 // TCE uses the llvm bitcode as input and uses it for generating customized 6042 // target processor and program binary. TCE co-design environment is 6043 // publicly available in http://tce.cs.tut.fi 6044 6045 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6046 3, // opencl_global 6047 4, // opencl_local 6048 5, // opencl_constant 6049 // FIXME: generic has to be added to the target 6050 0, // opencl_generic 6051 0, // cuda_device 6052 0, // cuda_constant 6053 0 // cuda_shared 6054 }; 6055 6056 class TCETargetInfo : public TargetInfo{ 6057 public: 6058 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6059 TLSSupported = false; 6060 IntWidth = 32; 6061 LongWidth = LongLongWidth = 32; 6062 PointerWidth = 32; 6063 IntAlign = 32; 6064 LongAlign = LongLongAlign = 32; 6065 PointerAlign = 32; 6066 SuitableAlign = 32; 6067 SizeType = UnsignedInt; 6068 IntMaxType = SignedLong; 6069 IntPtrType = SignedInt; 6070 PtrDiffType = SignedInt; 6071 FloatWidth = 32; 6072 FloatAlign = 32; 6073 DoubleWidth = 32; 6074 DoubleAlign = 32; 6075 LongDoubleWidth = 32; 6076 LongDoubleAlign = 32; 6077 FloatFormat = &llvm::APFloat::IEEEsingle; 6078 DoubleFormat = &llvm::APFloat::IEEEsingle; 6079 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6080 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 6081 "-f64:32-v64:32-v128:32-a:0:32-n32"; 6082 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6083 UseAddrSpaceMapMangling = true; 6084 } 6085 6086 void getTargetDefines(const LangOptions &Opts, 6087 MacroBuilder &Builder) const override { 6088 DefineStd(Builder, "tce", Opts); 6089 Builder.defineMacro("__TCE__"); 6090 Builder.defineMacro("__TCE_V1__"); 6091 } 6092 bool hasFeature(StringRef Feature) const override { 6093 return Feature == "tce"; 6094 } 6095 6096 void getTargetBuiltins(const Builtin::Info *&Records, 6097 unsigned &NumRecords) const override {} 6098 const char *getClobbers() const override { 6099 return ""; 6100 } 6101 BuiltinVaListKind getBuiltinVaListKind() const override { 6102 return TargetInfo::VoidPtrBuiltinVaList; 6103 } 6104 void getGCCRegNames(const char * const *&Names, 6105 unsigned &NumNames) const override {} 6106 bool validateAsmConstraint(const char *&Name, 6107 TargetInfo::ConstraintInfo &info) const override{ 6108 return true; 6109 } 6110 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6111 unsigned &NumAliases) const override {} 6112 }; 6113 6114 class BPFTargetInfo : public TargetInfo { 6115 public: 6116 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6117 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6118 SizeType = UnsignedLong; 6119 PtrDiffType = SignedLong; 6120 IntPtrType = SignedLong; 6121 IntMaxType = SignedLong; 6122 Int64Type = SignedLong; 6123 RegParmMax = 5; 6124 if (Triple.getArch() == llvm::Triple::bpfeb) { 6125 BigEndian = true; 6126 DescriptionString = "E-m:e-p:64:64-i64:64-n32:64-S128"; 6127 } else { 6128 BigEndian = false; 6129 DescriptionString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 6130 } 6131 MaxAtomicPromoteWidth = 64; 6132 MaxAtomicInlineWidth = 64; 6133 TLSSupported = false; 6134 } 6135 void getTargetDefines(const LangOptions &Opts, 6136 MacroBuilder &Builder) const override { 6137 DefineStd(Builder, "bpf", Opts); 6138 Builder.defineMacro("__BPF__"); 6139 } 6140 bool hasFeature(StringRef Feature) const override { 6141 return Feature == "bpf"; 6142 } 6143 6144 void getTargetBuiltins(const Builtin::Info *&Records, 6145 unsigned &NumRecords) const override {} 6146 const char *getClobbers() const override { 6147 return ""; 6148 } 6149 BuiltinVaListKind getBuiltinVaListKind() const override { 6150 return TargetInfo::VoidPtrBuiltinVaList; 6151 } 6152 void getGCCRegNames(const char * const *&Names, 6153 unsigned &NumNames) const override { 6154 Names = nullptr; 6155 NumNames = 0; 6156 } 6157 bool validateAsmConstraint(const char *&Name, 6158 TargetInfo::ConstraintInfo &info) const override { 6159 return true; 6160 } 6161 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6162 unsigned &NumAliases) const override { 6163 Aliases = nullptr; 6164 NumAliases = 0; 6165 } 6166 }; 6167 6168 class MipsTargetInfoBase : public TargetInfo { 6169 virtual void setDescriptionString() = 0; 6170 6171 static const Builtin::Info BuiltinInfo[]; 6172 std::string CPU; 6173 bool IsMips16; 6174 bool IsMicromips; 6175 bool IsNan2008; 6176 bool IsSingleFloat; 6177 enum MipsFloatABI { 6178 HardFloat, SoftFloat 6179 } FloatABI; 6180 enum DspRevEnum { 6181 NoDSP, DSP1, DSP2 6182 } DspRev; 6183 bool HasMSA; 6184 6185 protected: 6186 bool HasFP64; 6187 std::string ABI; 6188 6189 public: 6190 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 6191 const std::string &CPUStr) 6192 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6193 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6194 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6195 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6196 } 6197 6198 bool isNaN2008Default() const { 6199 return CPU == "mips32r6" || CPU == "mips64r6"; 6200 } 6201 6202 bool isFP64Default() const { 6203 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6204 } 6205 6206 bool isNan2008() const override { 6207 return IsNan2008; 6208 } 6209 6210 StringRef getABI() const override { return ABI; } 6211 bool setCPU(const std::string &Name) override { 6212 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6213 getTriple().getArch() == llvm::Triple::mipsel; 6214 CPU = Name; 6215 return llvm::StringSwitch<bool>(Name) 6216 .Case("mips1", IsMips32) 6217 .Case("mips2", IsMips32) 6218 .Case("mips3", true) 6219 .Case("mips4", true) 6220 .Case("mips5", true) 6221 .Case("mips32", IsMips32) 6222 .Case("mips32r2", IsMips32) 6223 .Case("mips32r3", IsMips32) 6224 .Case("mips32r5", IsMips32) 6225 .Case("mips32r6", IsMips32) 6226 .Case("mips64", true) 6227 .Case("mips64r2", true) 6228 .Case("mips64r3", true) 6229 .Case("mips64r5", true) 6230 .Case("mips64r6", true) 6231 .Case("octeon", true) 6232 .Default(false); 6233 } 6234 const std::string& getCPU() const { return CPU; } 6235 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 6236 if (CPU == "octeon") 6237 Features["mips64r2"] = Features["cnmips"] = true; 6238 else 6239 Features[CPU] = true; 6240 } 6241 6242 void getTargetDefines(const LangOptions &Opts, 6243 MacroBuilder &Builder) const override { 6244 Builder.defineMacro("__mips__"); 6245 Builder.defineMacro("_mips"); 6246 if (Opts.GNUMode) 6247 Builder.defineMacro("mips"); 6248 6249 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6250 6251 switch (FloatABI) { 6252 case HardFloat: 6253 Builder.defineMacro("__mips_hard_float", Twine(1)); 6254 break; 6255 case SoftFloat: 6256 Builder.defineMacro("__mips_soft_float", Twine(1)); 6257 break; 6258 } 6259 6260 if (IsSingleFloat) 6261 Builder.defineMacro("__mips_single_float", Twine(1)); 6262 6263 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6264 Builder.defineMacro("_MIPS_FPSET", 6265 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6266 6267 if (IsMips16) 6268 Builder.defineMacro("__mips16", Twine(1)); 6269 6270 if (IsMicromips) 6271 Builder.defineMacro("__mips_micromips", Twine(1)); 6272 6273 if (IsNan2008) 6274 Builder.defineMacro("__mips_nan2008", Twine(1)); 6275 6276 switch (DspRev) { 6277 default: 6278 break; 6279 case DSP1: 6280 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6281 Builder.defineMacro("__mips_dsp", Twine(1)); 6282 break; 6283 case DSP2: 6284 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6285 Builder.defineMacro("__mips_dspr2", Twine(1)); 6286 Builder.defineMacro("__mips_dsp", Twine(1)); 6287 break; 6288 } 6289 6290 if (HasMSA) 6291 Builder.defineMacro("__mips_msa", Twine(1)); 6292 6293 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6294 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6295 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6296 6297 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6298 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6299 } 6300 6301 void getTargetBuiltins(const Builtin::Info *&Records, 6302 unsigned &NumRecords) const override { 6303 Records = BuiltinInfo; 6304 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 6305 } 6306 bool hasFeature(StringRef Feature) const override { 6307 return llvm::StringSwitch<bool>(Feature) 6308 .Case("mips", true) 6309 .Case("fp64", HasFP64) 6310 .Default(false); 6311 } 6312 BuiltinVaListKind getBuiltinVaListKind() const override { 6313 return TargetInfo::VoidPtrBuiltinVaList; 6314 } 6315 void getGCCRegNames(const char * const *&Names, 6316 unsigned &NumNames) const override { 6317 static const char *const GCCRegNames[] = { 6318 // CPU register names 6319 // Must match second column of GCCRegAliases 6320 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6321 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6322 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6323 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6324 // Floating point register names 6325 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6326 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6327 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6328 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6329 // Hi/lo and condition register names 6330 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6331 "$fcc5","$fcc6","$fcc7", 6332 // MSA register names 6333 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6334 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6335 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6336 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6337 // MSA control register names 6338 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6339 "$msarequest", "$msamap", "$msaunmap" 6340 }; 6341 Names = GCCRegNames; 6342 NumNames = llvm::array_lengthof(GCCRegNames); 6343 } 6344 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6345 unsigned &NumAliases) const override = 0; 6346 bool validateAsmConstraint(const char *&Name, 6347 TargetInfo::ConstraintInfo &Info) const override { 6348 switch (*Name) { 6349 default: 6350 return false; 6351 case 'r': // CPU registers. 6352 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6353 case 'y': // Equivalent to "r", backward compatibility only. 6354 case 'f': // floating-point registers. 6355 case 'c': // $25 for indirect jumps 6356 case 'l': // lo register 6357 case 'x': // hilo register pair 6358 Info.setAllowsRegister(); 6359 return true; 6360 case 'I': // Signed 16-bit constant 6361 case 'J': // Integer 0 6362 case 'K': // Unsigned 16-bit constant 6363 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6364 case 'M': // Constants not loadable via lui, addiu, or ori 6365 case 'N': // Constant -1 to -65535 6366 case 'O': // A signed 15-bit constant 6367 case 'P': // A constant between 1 go 65535 6368 return true; 6369 case 'R': // An address that can be used in a non-macro load or store 6370 Info.setAllowsMemory(); 6371 return true; 6372 case 'Z': 6373 if (Name[1] == 'C') { // An address usable by ll, and sc. 6374 Info.setAllowsMemory(); 6375 Name++; // Skip over 'Z'. 6376 return true; 6377 } 6378 return false; 6379 } 6380 } 6381 6382 std::string convertConstraint(const char *&Constraint) const override { 6383 std::string R; 6384 switch (*Constraint) { 6385 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6386 if (Constraint[1] == 'C') { 6387 R = std::string("^") + std::string(Constraint, 2); 6388 Constraint++; 6389 return R; 6390 } 6391 break; 6392 } 6393 return TargetInfo::convertConstraint(Constraint); 6394 } 6395 6396 const char *getClobbers() const override { 6397 // In GCC, $1 is not widely used in generated code (it's used only in a few 6398 // specific situations), so there is no real need for users to add it to 6399 // the clobbers list if they want to use it in their inline assembly code. 6400 // 6401 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6402 // code generation, so using it in inline assembly without adding it to the 6403 // clobbers list can cause conflicts between the inline assembly code and 6404 // the surrounding generated code. 6405 // 6406 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6407 // operands, which will conflict with the ".set at" assembler option (which 6408 // we use only for inline assembly, in order to maintain compatibility with 6409 // GCC) and will also conflict with the user's usage of $1. 6410 // 6411 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6412 // register for generated code is to automatically clobber $1 for all inline 6413 // assembly code. 6414 // 6415 // FIXME: We should automatically clobber $1 only for inline assembly code 6416 // which actually uses it. This would allow LLVM to use $1 for inline 6417 // assembly operands if the user's assembly code doesn't use it. 6418 return "~{$1}"; 6419 } 6420 6421 bool handleTargetFeatures(std::vector<std::string> &Features, 6422 DiagnosticsEngine &Diags) override { 6423 IsMips16 = false; 6424 IsMicromips = false; 6425 IsNan2008 = isNaN2008Default(); 6426 IsSingleFloat = false; 6427 FloatABI = HardFloat; 6428 DspRev = NoDSP; 6429 HasFP64 = isFP64Default(); 6430 6431 for (std::vector<std::string>::iterator it = Features.begin(), 6432 ie = Features.end(); it != ie; ++it) { 6433 if (*it == "+single-float") 6434 IsSingleFloat = true; 6435 else if (*it == "+soft-float") 6436 FloatABI = SoftFloat; 6437 else if (*it == "+mips16") 6438 IsMips16 = true; 6439 else if (*it == "+micromips") 6440 IsMicromips = true; 6441 else if (*it == "+dsp") 6442 DspRev = std::max(DspRev, DSP1); 6443 else if (*it == "+dspr2") 6444 DspRev = std::max(DspRev, DSP2); 6445 else if (*it == "+msa") 6446 HasMSA = true; 6447 else if (*it == "+fp64") 6448 HasFP64 = true; 6449 else if (*it == "-fp64") 6450 HasFP64 = false; 6451 else if (*it == "+nan2008") 6452 IsNan2008 = true; 6453 else if (*it == "-nan2008") 6454 IsNan2008 = false; 6455 } 6456 6457 setDescriptionString(); 6458 6459 return true; 6460 } 6461 6462 int getEHDataRegisterNumber(unsigned RegNo) const override { 6463 if (RegNo == 0) return 4; 6464 if (RegNo == 1) return 5; 6465 return -1; 6466 } 6467 6468 bool isCLZForZeroUndef() const override { return false; } 6469 }; 6470 6471 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 6472 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6473 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 6474 ALL_LANGUAGES }, 6475 #include "clang/Basic/BuiltinsMips.def" 6476 }; 6477 6478 class Mips32TargetInfoBase : public MipsTargetInfoBase { 6479 public: 6480 Mips32TargetInfoBase(const llvm::Triple &Triple) 6481 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 6482 SizeType = UnsignedInt; 6483 PtrDiffType = SignedInt; 6484 Int64Type = SignedLongLong; 6485 IntMaxType = Int64Type; 6486 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 6487 } 6488 bool setABI(const std::string &Name) override { 6489 if (Name == "o32" || Name == "eabi") { 6490 ABI = Name; 6491 return true; 6492 } 6493 return false; 6494 } 6495 void getTargetDefines(const LangOptions &Opts, 6496 MacroBuilder &Builder) const override { 6497 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6498 6499 Builder.defineMacro("__mips", "32"); 6500 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 6501 6502 const std::string& CPUStr = getCPU(); 6503 if (CPUStr == "mips32") 6504 Builder.defineMacro("__mips_isa_rev", "1"); 6505 else if (CPUStr == "mips32r2") 6506 Builder.defineMacro("__mips_isa_rev", "2"); 6507 else if (CPUStr == "mips32r3") 6508 Builder.defineMacro("__mips_isa_rev", "3"); 6509 else if (CPUStr == "mips32r5") 6510 Builder.defineMacro("__mips_isa_rev", "5"); 6511 else if (CPUStr == "mips32r6") 6512 Builder.defineMacro("__mips_isa_rev", "6"); 6513 6514 if (ABI == "o32") { 6515 Builder.defineMacro("__mips_o32"); 6516 Builder.defineMacro("_ABIO32", "1"); 6517 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6518 } 6519 else if (ABI == "eabi") 6520 Builder.defineMacro("__mips_eabi"); 6521 else 6522 llvm_unreachable("Invalid ABI for Mips32."); 6523 } 6524 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6525 unsigned &NumAliases) const override { 6526 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6527 { { "at" }, "$1" }, 6528 { { "v0" }, "$2" }, 6529 { { "v1" }, "$3" }, 6530 { { "a0" }, "$4" }, 6531 { { "a1" }, "$5" }, 6532 { { "a2" }, "$6" }, 6533 { { "a3" }, "$7" }, 6534 { { "t0" }, "$8" }, 6535 { { "t1" }, "$9" }, 6536 { { "t2" }, "$10" }, 6537 { { "t3" }, "$11" }, 6538 { { "t4" }, "$12" }, 6539 { { "t5" }, "$13" }, 6540 { { "t6" }, "$14" }, 6541 { { "t7" }, "$15" }, 6542 { { "s0" }, "$16" }, 6543 { { "s1" }, "$17" }, 6544 { { "s2" }, "$18" }, 6545 { { "s3" }, "$19" }, 6546 { { "s4" }, "$20" }, 6547 { { "s5" }, "$21" }, 6548 { { "s6" }, "$22" }, 6549 { { "s7" }, "$23" }, 6550 { { "t8" }, "$24" }, 6551 { { "t9" }, "$25" }, 6552 { { "k0" }, "$26" }, 6553 { { "k1" }, "$27" }, 6554 { { "gp" }, "$28" }, 6555 { { "sp","$sp" }, "$29" }, 6556 { { "fp","$fp" }, "$30" }, 6557 { { "ra" }, "$31" } 6558 }; 6559 Aliases = GCCRegAliases; 6560 NumAliases = llvm::array_lengthof(GCCRegAliases); 6561 } 6562 }; 6563 6564 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6565 void setDescriptionString() override { 6566 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6567 } 6568 6569 public: 6570 Mips32EBTargetInfo(const llvm::Triple &Triple) 6571 : Mips32TargetInfoBase(Triple) { 6572 } 6573 void getTargetDefines(const LangOptions &Opts, 6574 MacroBuilder &Builder) const override { 6575 DefineStd(Builder, "MIPSEB", Opts); 6576 Builder.defineMacro("_MIPSEB"); 6577 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6578 } 6579 }; 6580 6581 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6582 void setDescriptionString() override { 6583 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6584 } 6585 6586 public: 6587 Mips32ELTargetInfo(const llvm::Triple &Triple) 6588 : Mips32TargetInfoBase(Triple) { 6589 BigEndian = false; 6590 } 6591 void getTargetDefines(const LangOptions &Opts, 6592 MacroBuilder &Builder) const override { 6593 DefineStd(Builder, "MIPSEL", Opts); 6594 Builder.defineMacro("_MIPSEL"); 6595 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6596 } 6597 }; 6598 6599 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6600 public: 6601 Mips64TargetInfoBase(const llvm::Triple &Triple) 6602 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6603 LongDoubleWidth = LongDoubleAlign = 128; 6604 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6605 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6606 LongDoubleWidth = LongDoubleAlign = 64; 6607 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6608 } 6609 setN64ABITypes(); 6610 SuitableAlign = 128; 6611 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6612 } 6613 6614 void setN64ABITypes() { 6615 LongWidth = LongAlign = 64; 6616 PointerWidth = PointerAlign = 64; 6617 SizeType = UnsignedLong; 6618 PtrDiffType = SignedLong; 6619 Int64Type = SignedLong; 6620 IntMaxType = Int64Type; 6621 } 6622 6623 void setN32ABITypes() { 6624 LongWidth = LongAlign = 32; 6625 PointerWidth = PointerAlign = 32; 6626 SizeType = UnsignedInt; 6627 PtrDiffType = SignedInt; 6628 Int64Type = SignedLongLong; 6629 IntMaxType = Int64Type; 6630 } 6631 6632 bool setABI(const std::string &Name) override { 6633 if (Name == "n32") { 6634 setN32ABITypes(); 6635 ABI = Name; 6636 return true; 6637 } 6638 if (Name == "n64") { 6639 setN64ABITypes(); 6640 ABI = Name; 6641 return true; 6642 } 6643 return false; 6644 } 6645 6646 void getTargetDefines(const LangOptions &Opts, 6647 MacroBuilder &Builder) const override { 6648 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6649 6650 Builder.defineMacro("__mips", "64"); 6651 Builder.defineMacro("__mips64"); 6652 Builder.defineMacro("__mips64__"); 6653 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 6654 6655 const std::string& CPUStr = getCPU(); 6656 if (CPUStr == "mips64") 6657 Builder.defineMacro("__mips_isa_rev", "1"); 6658 else if (CPUStr == "mips64r2") 6659 Builder.defineMacro("__mips_isa_rev", "2"); 6660 else if (CPUStr == "mips64r3") 6661 Builder.defineMacro("__mips_isa_rev", "3"); 6662 else if (CPUStr == "mips64r5") 6663 Builder.defineMacro("__mips_isa_rev", "5"); 6664 else if (CPUStr == "mips64r6") 6665 Builder.defineMacro("__mips_isa_rev", "6"); 6666 6667 if (ABI == "n32") { 6668 Builder.defineMacro("__mips_n32"); 6669 Builder.defineMacro("_ABIN32", "2"); 6670 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 6671 } 6672 else if (ABI == "n64") { 6673 Builder.defineMacro("__mips_n64"); 6674 Builder.defineMacro("_ABI64", "3"); 6675 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 6676 } 6677 else 6678 llvm_unreachable("Invalid ABI for Mips64."); 6679 } 6680 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6681 unsigned &NumAliases) const override { 6682 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6683 { { "at" }, "$1" }, 6684 { { "v0" }, "$2" }, 6685 { { "v1" }, "$3" }, 6686 { { "a0" }, "$4" }, 6687 { { "a1" }, "$5" }, 6688 { { "a2" }, "$6" }, 6689 { { "a3" }, "$7" }, 6690 { { "a4" }, "$8" }, 6691 { { "a5" }, "$9" }, 6692 { { "a6" }, "$10" }, 6693 { { "a7" }, "$11" }, 6694 { { "t0" }, "$12" }, 6695 { { "t1" }, "$13" }, 6696 { { "t2" }, "$14" }, 6697 { { "t3" }, "$15" }, 6698 { { "s0" }, "$16" }, 6699 { { "s1" }, "$17" }, 6700 { { "s2" }, "$18" }, 6701 { { "s3" }, "$19" }, 6702 { { "s4" }, "$20" }, 6703 { { "s5" }, "$21" }, 6704 { { "s6" }, "$22" }, 6705 { { "s7" }, "$23" }, 6706 { { "t8" }, "$24" }, 6707 { { "t9" }, "$25" }, 6708 { { "k0" }, "$26" }, 6709 { { "k1" }, "$27" }, 6710 { { "gp" }, "$28" }, 6711 { { "sp","$sp" }, "$29" }, 6712 { { "fp","$fp" }, "$30" }, 6713 { { "ra" }, "$31" } 6714 }; 6715 Aliases = GCCRegAliases; 6716 NumAliases = llvm::array_lengthof(GCCRegAliases); 6717 } 6718 6719 bool hasInt128Type() const override { return true; } 6720 }; 6721 6722 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 6723 void setDescriptionString() override { 6724 if (ABI == "n32") 6725 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6726 else 6727 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6728 6729 } 6730 6731 public: 6732 Mips64EBTargetInfo(const llvm::Triple &Triple) 6733 : Mips64TargetInfoBase(Triple) {} 6734 void getTargetDefines(const LangOptions &Opts, 6735 MacroBuilder &Builder) const override { 6736 DefineStd(Builder, "MIPSEB", Opts); 6737 Builder.defineMacro("_MIPSEB"); 6738 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6739 } 6740 }; 6741 6742 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 6743 void setDescriptionString() override { 6744 if (ABI == "n32") 6745 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6746 else 6747 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6748 } 6749 public: 6750 Mips64ELTargetInfo(const llvm::Triple &Triple) 6751 : Mips64TargetInfoBase(Triple) { 6752 // Default ABI is n64. 6753 BigEndian = false; 6754 } 6755 void getTargetDefines(const LangOptions &Opts, 6756 MacroBuilder &Builder) const override { 6757 DefineStd(Builder, "MIPSEL", Opts); 6758 Builder.defineMacro("_MIPSEL"); 6759 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6760 } 6761 }; 6762 6763 class PNaClTargetInfo : public TargetInfo { 6764 public: 6765 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6766 BigEndian = false; 6767 this->UserLabelPrefix = ""; 6768 this->LongAlign = 32; 6769 this->LongWidth = 32; 6770 this->PointerAlign = 32; 6771 this->PointerWidth = 32; 6772 this->IntMaxType = TargetInfo::SignedLongLong; 6773 this->Int64Type = TargetInfo::SignedLongLong; 6774 this->DoubleAlign = 64; 6775 this->LongDoubleWidth = 64; 6776 this->LongDoubleAlign = 64; 6777 this->SizeType = TargetInfo::UnsignedInt; 6778 this->PtrDiffType = TargetInfo::SignedInt; 6779 this->IntPtrType = TargetInfo::SignedInt; 6780 this->RegParmMax = 0; // Disallow regparm 6781 } 6782 6783 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 6784 } 6785 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 6786 Builder.defineMacro("__le32__"); 6787 Builder.defineMacro("__pnacl__"); 6788 } 6789 void getTargetDefines(const LangOptions &Opts, 6790 MacroBuilder &Builder) const override { 6791 getArchDefines(Opts, Builder); 6792 } 6793 bool hasFeature(StringRef Feature) const override { 6794 return Feature == "pnacl"; 6795 } 6796 void getTargetBuiltins(const Builtin::Info *&Records, 6797 unsigned &NumRecords) const override { 6798 } 6799 BuiltinVaListKind getBuiltinVaListKind() const override { 6800 return TargetInfo::PNaClABIBuiltinVaList; 6801 } 6802 void getGCCRegNames(const char * const *&Names, 6803 unsigned &NumNames) const override; 6804 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6805 unsigned &NumAliases) const override; 6806 bool validateAsmConstraint(const char *&Name, 6807 TargetInfo::ConstraintInfo &Info) const override { 6808 return false; 6809 } 6810 6811 const char *getClobbers() const override { 6812 return ""; 6813 } 6814 }; 6815 6816 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 6817 unsigned &NumNames) const { 6818 Names = nullptr; 6819 NumNames = 0; 6820 } 6821 6822 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 6823 unsigned &NumAliases) const { 6824 Aliases = nullptr; 6825 NumAliases = 0; 6826 } 6827 6828 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 6829 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 6830 public: 6831 NaClMips32ELTargetInfo(const llvm::Triple &Triple) : 6832 Mips32ELTargetInfo(Triple) { 6833 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 0; 6834 } 6835 6836 BuiltinVaListKind getBuiltinVaListKind() const override { 6837 return TargetInfo::PNaClABIBuiltinVaList; 6838 } 6839 }; 6840 6841 class Le64TargetInfo : public TargetInfo { 6842 static const Builtin::Info BuiltinInfo[]; 6843 6844 public: 6845 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6846 BigEndian = false; 6847 NoAsmVariants = true; 6848 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6849 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6850 DescriptionString = 6851 "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 6852 } 6853 6854 void getTargetDefines(const LangOptions &Opts, 6855 MacroBuilder &Builder) const override { 6856 DefineStd(Builder, "unix", Opts); 6857 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 6858 Builder.defineMacro("__ELF__"); 6859 } 6860 void getTargetBuiltins(const Builtin::Info *&Records, 6861 unsigned &NumRecords) const override { 6862 Records = BuiltinInfo; 6863 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin; 6864 } 6865 BuiltinVaListKind getBuiltinVaListKind() const override { 6866 return TargetInfo::PNaClABIBuiltinVaList; 6867 } 6868 const char *getClobbers() const override { return ""; } 6869 void getGCCRegNames(const char *const *&Names, 6870 unsigned &NumNames) const override { 6871 Names = nullptr; 6872 NumNames = 0; 6873 } 6874 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6875 unsigned &NumAliases) const override { 6876 Aliases = nullptr; 6877 NumAliases = 0; 6878 } 6879 bool validateAsmConstraint(const char *&Name, 6880 TargetInfo::ConstraintInfo &Info) const override { 6881 return false; 6882 } 6883 6884 bool hasProtectedVisibility() const override { return false; } 6885 }; 6886 } // end anonymous namespace. 6887 6888 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 6889 #define BUILTIN(ID, TYPE, ATTRS) \ 6890 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6891 #include "clang/Basic/BuiltinsLe64.def" 6892 }; 6893 6894 namespace { 6895 static const unsigned SPIRAddrSpaceMap[] = { 6896 1, // opencl_global 6897 3, // opencl_local 6898 2, // opencl_constant 6899 4, // opencl_generic 6900 0, // cuda_device 6901 0, // cuda_constant 6902 0 // cuda_shared 6903 }; 6904 class SPIRTargetInfo : public TargetInfo { 6905 public: 6906 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6907 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 6908 "SPIR target must use unknown OS"); 6909 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 6910 "SPIR target must use unknown environment type"); 6911 BigEndian = false; 6912 TLSSupported = false; 6913 LongWidth = LongAlign = 64; 6914 AddrSpaceMap = &SPIRAddrSpaceMap; 6915 UseAddrSpaceMapMangling = true; 6916 // Define available target features 6917 // These must be defined in sorted order! 6918 NoAsmVariants = true; 6919 } 6920 void getTargetDefines(const LangOptions &Opts, 6921 MacroBuilder &Builder) const override { 6922 DefineStd(Builder, "SPIR", Opts); 6923 } 6924 bool hasFeature(StringRef Feature) const override { 6925 return Feature == "spir"; 6926 } 6927 6928 void getTargetBuiltins(const Builtin::Info *&Records, 6929 unsigned &NumRecords) const override {} 6930 const char *getClobbers() const override { 6931 return ""; 6932 } 6933 void getGCCRegNames(const char * const *&Names, 6934 unsigned &NumNames) const override {} 6935 bool 6936 validateAsmConstraint(const char *&Name, 6937 TargetInfo::ConstraintInfo &info) const override { 6938 return true; 6939 } 6940 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6941 unsigned &NumAliases) const override {} 6942 BuiltinVaListKind getBuiltinVaListKind() const override { 6943 return TargetInfo::VoidPtrBuiltinVaList; 6944 } 6945 6946 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6947 return (CC == CC_SpirFunction || 6948 CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning; 6949 } 6950 6951 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 6952 return CC_SpirFunction; 6953 } 6954 }; 6955 6956 6957 class SPIR32TargetInfo : public SPIRTargetInfo { 6958 public: 6959 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6960 PointerWidth = PointerAlign = 32; 6961 SizeType = TargetInfo::UnsignedInt; 6962 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 6963 DescriptionString 6964 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 6965 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6966 } 6967 void getTargetDefines(const LangOptions &Opts, 6968 MacroBuilder &Builder) const override { 6969 DefineStd(Builder, "SPIR32", Opts); 6970 } 6971 }; 6972 6973 class SPIR64TargetInfo : public SPIRTargetInfo { 6974 public: 6975 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6976 PointerWidth = PointerAlign = 64; 6977 SizeType = TargetInfo::UnsignedLong; 6978 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 6979 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 6980 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6981 } 6982 void getTargetDefines(const LangOptions &Opts, 6983 MacroBuilder &Builder) const override { 6984 DefineStd(Builder, "SPIR64", Opts); 6985 } 6986 }; 6987 6988 class XCoreTargetInfo : public TargetInfo { 6989 static const Builtin::Info BuiltinInfo[]; 6990 public: 6991 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6992 BigEndian = false; 6993 NoAsmVariants = true; 6994 LongLongAlign = 32; 6995 SuitableAlign = 32; 6996 DoubleAlign = LongDoubleAlign = 32; 6997 SizeType = UnsignedInt; 6998 PtrDiffType = SignedInt; 6999 IntPtrType = SignedInt; 7000 WCharType = UnsignedChar; 7001 WIntType = UnsignedInt; 7002 UseZeroLengthBitfieldAlignment = true; 7003 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7004 "-f64:32-a:0:32-n32"; 7005 } 7006 void getTargetDefines(const LangOptions &Opts, 7007 MacroBuilder &Builder) const override { 7008 Builder.defineMacro("__XS1B__"); 7009 } 7010 void getTargetBuiltins(const Builtin::Info *&Records, 7011 unsigned &NumRecords) const override { 7012 Records = BuiltinInfo; 7013 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 7014 } 7015 BuiltinVaListKind getBuiltinVaListKind() const override { 7016 return TargetInfo::VoidPtrBuiltinVaList; 7017 } 7018 const char *getClobbers() const override { 7019 return ""; 7020 } 7021 void getGCCRegNames(const char * const *&Names, 7022 unsigned &NumNames) const override { 7023 static const char * const GCCRegNames[] = { 7024 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7025 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 7026 }; 7027 Names = GCCRegNames; 7028 NumNames = llvm::array_lengthof(GCCRegNames); 7029 } 7030 void getGCCRegAliases(const GCCRegAlias *&Aliases, 7031 unsigned &NumAliases) const override { 7032 Aliases = nullptr; 7033 NumAliases = 0; 7034 } 7035 bool validateAsmConstraint(const char *&Name, 7036 TargetInfo::ConstraintInfo &Info) const override { 7037 return false; 7038 } 7039 int getEHDataRegisterNumber(unsigned RegNo) const override { 7040 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7041 return (RegNo < 2)? RegNo : -1; 7042 } 7043 }; 7044 7045 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7046 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 7047 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 7048 ALL_LANGUAGES }, 7049 #include "clang/Basic/BuiltinsXCore.def" 7050 }; 7051 } // end anonymous namespace. 7052 7053 namespace { 7054 // x86_32 Android target 7055 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7056 public: 7057 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 7058 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 7059 SuitableAlign = 32; 7060 LongDoubleWidth = 64; 7061 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7062 } 7063 }; 7064 } // end anonymous namespace 7065 7066 namespace { 7067 // x86_64 Android target 7068 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7069 public: 7070 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 7071 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 7072 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7073 } 7074 7075 bool useFloat128ManglingForLongDouble() const override { 7076 return true; 7077 } 7078 }; 7079 } // end anonymous namespace 7080 7081 7082 //===----------------------------------------------------------------------===// 7083 // Driver code 7084 //===----------------------------------------------------------------------===// 7085 7086 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 7087 llvm::Triple::OSType os = Triple.getOS(); 7088 7089 switch (Triple.getArch()) { 7090 default: 7091 return nullptr; 7092 7093 case llvm::Triple::xcore: 7094 return new XCoreTargetInfo(Triple); 7095 7096 case llvm::Triple::hexagon: 7097 return new HexagonTargetInfo(Triple); 7098 7099 case llvm::Triple::aarch64: 7100 if (Triple.isOSDarwin()) 7101 return new DarwinAArch64TargetInfo(Triple); 7102 7103 switch (os) { 7104 case llvm::Triple::FreeBSD: 7105 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 7106 case llvm::Triple::Linux: 7107 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 7108 case llvm::Triple::NetBSD: 7109 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 7110 default: 7111 return new AArch64leTargetInfo(Triple); 7112 } 7113 7114 case llvm::Triple::aarch64_be: 7115 switch (os) { 7116 case llvm::Triple::FreeBSD: 7117 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 7118 case llvm::Triple::Linux: 7119 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 7120 case llvm::Triple::NetBSD: 7121 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 7122 default: 7123 return new AArch64beTargetInfo(Triple); 7124 } 7125 7126 case llvm::Triple::arm: 7127 case llvm::Triple::thumb: 7128 if (Triple.isOSBinFormatMachO()) 7129 return new DarwinARMTargetInfo(Triple); 7130 7131 switch (os) { 7132 case llvm::Triple::Linux: 7133 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 7134 case llvm::Triple::FreeBSD: 7135 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 7136 case llvm::Triple::NetBSD: 7137 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 7138 case llvm::Triple::OpenBSD: 7139 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 7140 case llvm::Triple::Bitrig: 7141 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 7142 case llvm::Triple::RTEMS: 7143 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 7144 case llvm::Triple::NaCl: 7145 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 7146 case llvm::Triple::Win32: 7147 switch (Triple.getEnvironment()) { 7148 case llvm::Triple::Cygnus: 7149 return new CygwinARMTargetInfo(Triple); 7150 case llvm::Triple::GNU: 7151 return new MinGWARMTargetInfo(Triple); 7152 case llvm::Triple::Itanium: 7153 return new ItaniumWindowsARMleTargetInfo(Triple); 7154 case llvm::Triple::MSVC: 7155 default: // Assume MSVC for unknown environments 7156 return new MicrosoftARMleTargetInfo(Triple); 7157 } 7158 default: 7159 return new ARMleTargetInfo(Triple); 7160 } 7161 7162 case llvm::Triple::armeb: 7163 case llvm::Triple::thumbeb: 7164 if (Triple.isOSDarwin()) 7165 return new DarwinARMTargetInfo(Triple); 7166 7167 switch (os) { 7168 case llvm::Triple::Linux: 7169 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 7170 case llvm::Triple::FreeBSD: 7171 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 7172 case llvm::Triple::NetBSD: 7173 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 7174 case llvm::Triple::OpenBSD: 7175 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 7176 case llvm::Triple::Bitrig: 7177 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 7178 case llvm::Triple::RTEMS: 7179 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 7180 case llvm::Triple::NaCl: 7181 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 7182 default: 7183 return new ARMbeTargetInfo(Triple); 7184 } 7185 7186 case llvm::Triple::bpfeb: 7187 case llvm::Triple::bpfel: 7188 return new BPFTargetInfo(Triple); 7189 7190 case llvm::Triple::msp430: 7191 return new MSP430TargetInfo(Triple); 7192 7193 case llvm::Triple::mips: 7194 switch (os) { 7195 case llvm::Triple::Linux: 7196 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 7197 case llvm::Triple::RTEMS: 7198 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 7199 case llvm::Triple::FreeBSD: 7200 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7201 case llvm::Triple::NetBSD: 7202 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7203 default: 7204 return new Mips32EBTargetInfo(Triple); 7205 } 7206 7207 case llvm::Triple::mipsel: 7208 switch (os) { 7209 case llvm::Triple::Linux: 7210 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 7211 case llvm::Triple::RTEMS: 7212 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 7213 case llvm::Triple::FreeBSD: 7214 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7215 case llvm::Triple::NetBSD: 7216 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7217 case llvm::Triple::NaCl: 7218 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple); 7219 default: 7220 return new Mips32ELTargetInfo(Triple); 7221 } 7222 7223 case llvm::Triple::mips64: 7224 switch (os) { 7225 case llvm::Triple::Linux: 7226 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 7227 case llvm::Triple::RTEMS: 7228 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 7229 case llvm::Triple::FreeBSD: 7230 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7231 case llvm::Triple::NetBSD: 7232 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7233 case llvm::Triple::OpenBSD: 7234 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7235 default: 7236 return new Mips64EBTargetInfo(Triple); 7237 } 7238 7239 case llvm::Triple::mips64el: 7240 switch (os) { 7241 case llvm::Triple::Linux: 7242 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 7243 case llvm::Triple::RTEMS: 7244 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 7245 case llvm::Triple::FreeBSD: 7246 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7247 case llvm::Triple::NetBSD: 7248 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7249 case llvm::Triple::OpenBSD: 7250 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7251 default: 7252 return new Mips64ELTargetInfo(Triple); 7253 } 7254 7255 case llvm::Triple::le32: 7256 switch (os) { 7257 case llvm::Triple::NaCl: 7258 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 7259 default: 7260 return nullptr; 7261 } 7262 7263 case llvm::Triple::le64: 7264 return new Le64TargetInfo(Triple); 7265 7266 case llvm::Triple::ppc: 7267 if (Triple.isOSDarwin()) 7268 return new DarwinPPC32TargetInfo(Triple); 7269 switch (os) { 7270 case llvm::Triple::Linux: 7271 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 7272 case llvm::Triple::FreeBSD: 7273 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 7274 case llvm::Triple::NetBSD: 7275 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 7276 case llvm::Triple::OpenBSD: 7277 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 7278 case llvm::Triple::RTEMS: 7279 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 7280 default: 7281 return new PPC32TargetInfo(Triple); 7282 } 7283 7284 case llvm::Triple::ppc64: 7285 if (Triple.isOSDarwin()) 7286 return new DarwinPPC64TargetInfo(Triple); 7287 switch (os) { 7288 case llvm::Triple::Linux: 7289 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7290 case llvm::Triple::Lv2: 7291 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 7292 case llvm::Triple::FreeBSD: 7293 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 7294 case llvm::Triple::NetBSD: 7295 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7296 default: 7297 return new PPC64TargetInfo(Triple); 7298 } 7299 7300 case llvm::Triple::ppc64le: 7301 switch (os) { 7302 case llvm::Triple::Linux: 7303 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7304 case llvm::Triple::NetBSD: 7305 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7306 default: 7307 return new PPC64TargetInfo(Triple); 7308 } 7309 7310 case llvm::Triple::nvptx: 7311 return new NVPTX32TargetInfo(Triple); 7312 case llvm::Triple::nvptx64: 7313 return new NVPTX64TargetInfo(Triple); 7314 7315 case llvm::Triple::amdgcn: 7316 case llvm::Triple::r600: 7317 return new AMDGPUTargetInfo(Triple); 7318 7319 case llvm::Triple::sparc: 7320 switch (os) { 7321 case llvm::Triple::Linux: 7322 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 7323 case llvm::Triple::Solaris: 7324 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple); 7325 case llvm::Triple::NetBSD: 7326 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 7327 case llvm::Triple::OpenBSD: 7328 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 7329 case llvm::Triple::RTEMS: 7330 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 7331 default: 7332 return new SparcV8TargetInfo(Triple); 7333 } 7334 7335 // The 'sparcel' architecture copies all the above cases except for Solaris. 7336 case llvm::Triple::sparcel: 7337 switch (os) { 7338 case llvm::Triple::Linux: 7339 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 7340 case llvm::Triple::NetBSD: 7341 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7342 case llvm::Triple::OpenBSD: 7343 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7344 case llvm::Triple::RTEMS: 7345 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 7346 default: 7347 return new SparcV8elTargetInfo(Triple); 7348 } 7349 7350 case llvm::Triple::sparcv9: 7351 switch (os) { 7352 case llvm::Triple::Linux: 7353 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 7354 case llvm::Triple::Solaris: 7355 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 7356 case llvm::Triple::NetBSD: 7357 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 7358 case llvm::Triple::OpenBSD: 7359 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 7360 case llvm::Triple::FreeBSD: 7361 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 7362 default: 7363 return new SparcV9TargetInfo(Triple); 7364 } 7365 7366 case llvm::Triple::systemz: 7367 switch (os) { 7368 case llvm::Triple::Linux: 7369 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 7370 default: 7371 return new SystemZTargetInfo(Triple); 7372 } 7373 7374 case llvm::Triple::tce: 7375 return new TCETargetInfo(Triple); 7376 7377 case llvm::Triple::x86: 7378 if (Triple.isOSDarwin()) 7379 return new DarwinI386TargetInfo(Triple); 7380 7381 switch (os) { 7382 case llvm::Triple::CloudABI: 7383 return new CloudABITargetInfo<X86_32TargetInfo>(Triple); 7384 case llvm::Triple::Linux: { 7385 switch (Triple.getEnvironment()) { 7386 default: 7387 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 7388 case llvm::Triple::Android: 7389 return new AndroidX86_32TargetInfo(Triple); 7390 } 7391 } 7392 case llvm::Triple::DragonFly: 7393 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 7394 case llvm::Triple::NetBSD: 7395 return new NetBSDI386TargetInfo(Triple); 7396 case llvm::Triple::OpenBSD: 7397 return new OpenBSDI386TargetInfo(Triple); 7398 case llvm::Triple::Bitrig: 7399 return new BitrigI386TargetInfo(Triple); 7400 case llvm::Triple::FreeBSD: 7401 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7402 case llvm::Triple::KFreeBSD: 7403 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7404 case llvm::Triple::Minix: 7405 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 7406 case llvm::Triple::Solaris: 7407 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 7408 case llvm::Triple::Win32: { 7409 switch (Triple.getEnvironment()) { 7410 case llvm::Triple::Cygnus: 7411 return new CygwinX86_32TargetInfo(Triple); 7412 case llvm::Triple::GNU: 7413 return new MinGWX86_32TargetInfo(Triple); 7414 case llvm::Triple::Itanium: 7415 case llvm::Triple::MSVC: 7416 default: // Assume MSVC for unknown environments 7417 return new MicrosoftX86_32TargetInfo(Triple); 7418 } 7419 } 7420 case llvm::Triple::Haiku: 7421 return new HaikuX86_32TargetInfo(Triple); 7422 case llvm::Triple::RTEMS: 7423 return new RTEMSX86_32TargetInfo(Triple); 7424 case llvm::Triple::NaCl: 7425 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 7426 default: 7427 return new X86_32TargetInfo(Triple); 7428 } 7429 7430 case llvm::Triple::x86_64: 7431 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 7432 return new DarwinX86_64TargetInfo(Triple); 7433 7434 switch (os) { 7435 case llvm::Triple::CloudABI: 7436 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 7437 case llvm::Triple::Linux: { 7438 switch (Triple.getEnvironment()) { 7439 default: 7440 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 7441 case llvm::Triple::Android: 7442 return new AndroidX86_64TargetInfo(Triple); 7443 } 7444 } 7445 case llvm::Triple::DragonFly: 7446 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 7447 case llvm::Triple::NetBSD: 7448 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 7449 case llvm::Triple::OpenBSD: 7450 return new OpenBSDX86_64TargetInfo(Triple); 7451 case llvm::Triple::Bitrig: 7452 return new BitrigX86_64TargetInfo(Triple); 7453 case llvm::Triple::FreeBSD: 7454 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7455 case llvm::Triple::KFreeBSD: 7456 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7457 case llvm::Triple::Solaris: 7458 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 7459 case llvm::Triple::Win32: { 7460 switch (Triple.getEnvironment()) { 7461 case llvm::Triple::Cygnus: 7462 return new CygwinX86_64TargetInfo(Triple); 7463 case llvm::Triple::GNU: 7464 return new MinGWX86_64TargetInfo(Triple); 7465 case llvm::Triple::MSVC: 7466 default: // Assume MSVC for unknown environments 7467 return new MicrosoftX86_64TargetInfo(Triple); 7468 } 7469 } 7470 case llvm::Triple::NaCl: 7471 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 7472 case llvm::Triple::PS4: 7473 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 7474 default: 7475 return new X86_64TargetInfo(Triple); 7476 } 7477 7478 case llvm::Triple::spir: { 7479 if (Triple.getOS() != llvm::Triple::UnknownOS || 7480 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7481 return nullptr; 7482 return new SPIR32TargetInfo(Triple); 7483 } 7484 case llvm::Triple::spir64: { 7485 if (Triple.getOS() != llvm::Triple::UnknownOS || 7486 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7487 return nullptr; 7488 return new SPIR64TargetInfo(Triple); 7489 } 7490 } 7491 } 7492 7493 /// CreateTargetInfo - Return the target info object for the specified target 7494 /// triple. 7495 TargetInfo * 7496 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 7497 const std::shared_ptr<TargetOptions> &Opts) { 7498 llvm::Triple Triple(Opts->Triple); 7499 7500 // Construct the target 7501 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 7502 if (!Target) { 7503 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 7504 return nullptr; 7505 } 7506 Target->TargetOpts = Opts; 7507 7508 // Set the target CPU if specified. 7509 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 7510 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 7511 return nullptr; 7512 } 7513 7514 // Set the target ABI if specified. 7515 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 7516 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 7517 return nullptr; 7518 } 7519 7520 // Set the fp math unit. 7521 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 7522 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 7523 return nullptr; 7524 } 7525 7526 // Compute the default target features, we need the target to handle this 7527 // because features may have dependencies on one another. 7528 llvm::StringMap<bool> Features; 7529 Target->getDefaultFeatures(Features); 7530 7531 // Apply the user specified deltas. 7532 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 7533 I < N; ++I) { 7534 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 7535 // Apply the feature via the target. 7536 bool Enabled = Name[0] == '+'; 7537 Target->setFeatureEnabled(Features, Name + 1, Enabled); 7538 } 7539 7540 // Add the features to the compile options. 7541 // 7542 // FIXME: If we are completely confident that we have the right set, we only 7543 // need to pass the minuses. 7544 Opts->Features.clear(); 7545 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 7546 ie = Features.end(); it != ie; ++it) 7547 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 7548 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 7549 return nullptr; 7550 7551 return Target.release(); 7552 } 7553