1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 115 const llvm::Triple &Triple, 116 StringRef &PlatformName, 117 VersionTuple &PlatformMinVersion) { 118 Builder.defineMacro("__APPLE_CC__", "6000"); 119 Builder.defineMacro("__APPLE__"); 120 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 121 // AddressSanitizer doesn't play well with source fortification, which is on 122 // by default on Darwin. 123 if (Opts.Sanitize.has(SanitizerKind::Address)) 124 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 125 126 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 127 if (!Opts.ObjC1) { 128 // __weak is always defined, for use in blocks and with objc pointers. 129 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 130 Builder.defineMacro("__strong", ""); 131 Builder.defineMacro("__unsafe_unretained", ""); 132 } 133 134 if (Opts.Static) 135 Builder.defineMacro("__STATIC__"); 136 else 137 Builder.defineMacro("__DYNAMIC__"); 138 139 if (Opts.POSIXThreads) 140 Builder.defineMacro("_REENTRANT"); 141 142 // Get the platform type and version number from the triple. 143 unsigned Maj, Min, Rev; 144 if (Triple.isMacOSX()) { 145 Triple.getMacOSXVersion(Maj, Min, Rev); 146 PlatformName = "macos"; 147 } else { 148 Triple.getOSVersion(Maj, Min, Rev); 149 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 150 } 151 152 // If -target arch-pc-win32-macho option specified, we're 153 // generating code for Win32 ABI. No need to emit 154 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 155 if (PlatformName == "win32") { 156 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 157 return; 158 } 159 160 // Set the appropriate OS version define. 161 if (Triple.isiOS()) { 162 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 163 char Str[7]; 164 if (Maj < 10) { 165 Str[0] = '0' + Maj; 166 Str[1] = '0' + (Min / 10); 167 Str[2] = '0' + (Min % 10); 168 Str[3] = '0' + (Rev / 10); 169 Str[4] = '0' + (Rev % 10); 170 Str[5] = '\0'; 171 } else { 172 // Handle versions >= 10. 173 Str[0] = '0' + (Maj / 10); 174 Str[1] = '0' + (Maj % 10); 175 Str[2] = '0' + (Min / 10); 176 Str[3] = '0' + (Min % 10); 177 Str[4] = '0' + (Rev / 10); 178 Str[5] = '0' + (Rev % 10); 179 Str[6] = '\0'; 180 } 181 if (Triple.isTvOS()) 182 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 183 else 184 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 185 Str); 186 187 } else if (Triple.isWatchOS()) { 188 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 189 char Str[6]; 190 Str[0] = '0' + Maj; 191 Str[1] = '0' + (Min / 10); 192 Str[2] = '0' + (Min % 10); 193 Str[3] = '0' + (Rev / 10); 194 Str[4] = '0' + (Rev % 10); 195 Str[5] = '\0'; 196 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 197 } else if (Triple.isMacOSX()) { 198 // Note that the Driver allows versions which aren't representable in the 199 // define (because we only get a single digit for the minor and micro 200 // revision numbers). So, we limit them to the maximum representable 201 // version. 202 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 203 char Str[7]; 204 if (Maj < 10 || (Maj == 10 && Min < 10)) { 205 Str[0] = '0' + (Maj / 10); 206 Str[1] = '0' + (Maj % 10); 207 Str[2] = '0' + std::min(Min, 9U); 208 Str[3] = '0' + std::min(Rev, 9U); 209 Str[4] = '\0'; 210 } else { 211 // Handle versions > 10.9. 212 Str[0] = '0' + (Maj / 10); 213 Str[1] = '0' + (Maj % 10); 214 Str[2] = '0' + (Min / 10); 215 Str[3] = '0' + (Min % 10); 216 Str[4] = '0' + (Rev / 10); 217 Str[5] = '0' + (Rev % 10); 218 Str[6] = '\0'; 219 } 220 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 221 } 222 223 // Tell users about the kernel if there is one. 224 if (Triple.isOSDarwin()) 225 Builder.defineMacro("__MACH__"); 226 227 // The Watch ABI uses Dwarf EH. 228 if(Triple.isWatchABI()) 229 Builder.defineMacro("__ARM_DWARF_EH__"); 230 231 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 232 } 233 234 template<typename Target> 235 class DarwinTargetInfo : public OSTargetInfo<Target> { 236 protected: 237 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 238 MacroBuilder &Builder) const override { 239 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 240 this->PlatformMinVersion); 241 } 242 243 public: 244 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 245 : OSTargetInfo<Target>(Triple, Opts) { 246 // By default, no TLS, and we whitelist permitted architecture/OS 247 // combinations. 248 this->TLSSupported = false; 249 250 if (Triple.isMacOSX()) 251 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 252 else if (Triple.isiOS()) { 253 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 254 if (Triple.getArch() == llvm::Triple::x86_64 || 255 Triple.getArch() == llvm::Triple::aarch64) 256 this->TLSSupported = !Triple.isOSVersionLT(8); 257 else if (Triple.getArch() == llvm::Triple::x86 || 258 Triple.getArch() == llvm::Triple::arm || 259 Triple.getArch() == llvm::Triple::thumb) 260 this->TLSSupported = !Triple.isOSVersionLT(9); 261 } else if (Triple.isWatchOS()) 262 this->TLSSupported = !Triple.isOSVersionLT(2); 263 264 this->MCountName = "\01mcount"; 265 } 266 267 std::string isValidSectionSpecifier(StringRef SR) const override { 268 // Let MCSectionMachO validate this. 269 StringRef Segment, Section; 270 unsigned TAA, StubSize; 271 bool HasTAA; 272 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 273 TAA, HasTAA, StubSize); 274 } 275 276 const char *getStaticInitSectionSpecifier() const override { 277 // FIXME: We should return 0 when building kexts. 278 return "__TEXT,__StaticInit,regular,pure_instructions"; 279 } 280 281 /// Darwin does not support protected visibility. Darwin's "default" 282 /// is very similar to ELF's "protected"; Darwin requires a "weak" 283 /// attribute on declarations that can be dynamically replaced. 284 bool hasProtectedVisibility() const override { 285 return false; 286 } 287 288 unsigned getExnObjectAlignment() const override { 289 // The alignment of an exception object is 8-bytes for darwin since 290 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 291 // and therefore doesn't guarantee 16-byte alignment. 292 return 64; 293 } 294 }; 295 296 297 // DragonFlyBSD Target 298 template<typename Target> 299 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 300 protected: 301 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 302 MacroBuilder &Builder) const override { 303 // DragonFly defines; list based off of gcc output 304 Builder.defineMacro("__DragonFly__"); 305 Builder.defineMacro("__DragonFly_cc_version", "100001"); 306 Builder.defineMacro("__ELF__"); 307 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 308 Builder.defineMacro("__tune_i386__"); 309 DefineStd(Builder, "unix", Opts); 310 } 311 public: 312 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 313 : OSTargetInfo<Target>(Triple, Opts) { 314 switch (Triple.getArch()) { 315 default: 316 case llvm::Triple::x86: 317 case llvm::Triple::x86_64: 318 this->MCountName = ".mcount"; 319 break; 320 } 321 } 322 }; 323 324 #ifndef FREEBSD_CC_VERSION 325 #define FREEBSD_CC_VERSION 0U 326 #endif 327 328 // FreeBSD Target 329 template<typename Target> 330 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 331 protected: 332 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 333 MacroBuilder &Builder) const override { 334 // FreeBSD defines; list based off of gcc output 335 336 unsigned Release = Triple.getOSMajorVersion(); 337 if (Release == 0U) 338 Release = 8U; 339 unsigned CCVersion = FREEBSD_CC_VERSION; 340 if (CCVersion == 0U) 341 CCVersion = Release * 100000U + 1U; 342 343 Builder.defineMacro("__FreeBSD__", Twine(Release)); 344 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 345 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 346 DefineStd(Builder, "unix", Opts); 347 Builder.defineMacro("__ELF__"); 348 349 // On FreeBSD, wchar_t contains the number of the code point as 350 // used by the character set of the locale. These character sets are 351 // not necessarily a superset of ASCII. 352 // 353 // FIXME: This is wrong; the macro refers to the numerical values 354 // of wchar_t *literals*, which are not locale-dependent. However, 355 // FreeBSD systems apparently depend on us getting this wrong, and 356 // setting this to 1 is conforming even if all the basic source 357 // character literals have the same encoding as char and wchar_t. 358 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 359 } 360 public: 361 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 362 : OSTargetInfo<Target>(Triple, Opts) { 363 switch (Triple.getArch()) { 364 default: 365 case llvm::Triple::x86: 366 case llvm::Triple::x86_64: 367 this->MCountName = ".mcount"; 368 break; 369 case llvm::Triple::mips: 370 case llvm::Triple::mipsel: 371 case llvm::Triple::ppc: 372 case llvm::Triple::ppc64: 373 case llvm::Triple::ppc64le: 374 this->MCountName = "_mcount"; 375 break; 376 case llvm::Triple::arm: 377 this->MCountName = "__mcount"; 378 break; 379 } 380 } 381 }; 382 383 // GNU/kFreeBSD Target 384 template<typename Target> 385 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 386 protected: 387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 388 MacroBuilder &Builder) const override { 389 // GNU/kFreeBSD defines; list based off of gcc output 390 391 DefineStd(Builder, "unix", Opts); 392 Builder.defineMacro("__FreeBSD_kernel__"); 393 Builder.defineMacro("__GLIBC__"); 394 Builder.defineMacro("__ELF__"); 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 if (Opts.CPlusPlus) 398 Builder.defineMacro("_GNU_SOURCE"); 399 } 400 public: 401 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 402 : OSTargetInfo<Target>(Triple, Opts) {} 403 }; 404 405 // Haiku Target 406 template<typename Target> 407 class HaikuTargetInfo : public OSTargetInfo<Target> { 408 protected: 409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 410 MacroBuilder &Builder) const override { 411 // Haiku defines; list based off of gcc output 412 Builder.defineMacro("__HAIKU__"); 413 Builder.defineMacro("__ELF__"); 414 DefineStd(Builder, "unix", Opts); 415 } 416 public: 417 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 418 : OSTargetInfo<Target>(Triple, Opts) { 419 this->SizeType = TargetInfo::UnsignedLong; 420 this->IntPtrType = TargetInfo::SignedLong; 421 this->PtrDiffType = TargetInfo::SignedLong; 422 this->ProcessIDType = TargetInfo::SignedLong; 423 this->TLSSupported = false; 424 425 } 426 }; 427 428 // Minix Target 429 template<typename Target> 430 class MinixTargetInfo : public OSTargetInfo<Target> { 431 protected: 432 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 433 MacroBuilder &Builder) const override { 434 // Minix defines 435 436 Builder.defineMacro("__minix", "3"); 437 Builder.defineMacro("_EM_WSIZE", "4"); 438 Builder.defineMacro("_EM_PSIZE", "4"); 439 Builder.defineMacro("_EM_SSIZE", "2"); 440 Builder.defineMacro("_EM_LSIZE", "4"); 441 Builder.defineMacro("_EM_FSIZE", "4"); 442 Builder.defineMacro("_EM_DSIZE", "8"); 443 Builder.defineMacro("__ELF__"); 444 DefineStd(Builder, "unix", Opts); 445 } 446 public: 447 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 448 : OSTargetInfo<Target>(Triple, Opts) {} 449 }; 450 451 // Linux target 452 template<typename Target> 453 class LinuxTargetInfo : public OSTargetInfo<Target> { 454 protected: 455 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 456 MacroBuilder &Builder) const override { 457 // Linux defines; list based off of gcc output 458 DefineStd(Builder, "unix", Opts); 459 DefineStd(Builder, "linux", Opts); 460 Builder.defineMacro("__gnu_linux__"); 461 Builder.defineMacro("__ELF__"); 462 if (Triple.isAndroid()) { 463 Builder.defineMacro("__ANDROID__", "1"); 464 unsigned Maj, Min, Rev; 465 Triple.getEnvironmentVersion(Maj, Min, Rev); 466 this->PlatformName = "android"; 467 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 468 if (Maj) 469 Builder.defineMacro("__ANDROID_API__", Twine(Maj)); 470 } 471 if (Opts.POSIXThreads) 472 Builder.defineMacro("_REENTRANT"); 473 if (Opts.CPlusPlus) 474 Builder.defineMacro("_GNU_SOURCE"); 475 if (this->HasFloat128) 476 Builder.defineMacro("__FLOAT128__"); 477 } 478 public: 479 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 480 : OSTargetInfo<Target>(Triple, Opts) { 481 this->WIntType = TargetInfo::UnsignedInt; 482 483 switch (Triple.getArch()) { 484 default: 485 break; 486 case llvm::Triple::ppc: 487 case llvm::Triple::ppc64: 488 case llvm::Triple::ppc64le: 489 this->MCountName = "_mcount"; 490 break; 491 case llvm::Triple::x86: 492 case llvm::Triple::x86_64: 493 case llvm::Triple::systemz: 494 this->HasFloat128 = true; 495 break; 496 } 497 } 498 499 const char *getStaticInitSectionSpecifier() const override { 500 return ".text.startup"; 501 } 502 }; 503 504 // NetBSD Target 505 template<typename Target> 506 class NetBSDTargetInfo : public OSTargetInfo<Target> { 507 protected: 508 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 509 MacroBuilder &Builder) const override { 510 // NetBSD defines; list based off of gcc output 511 Builder.defineMacro("__NetBSD__"); 512 Builder.defineMacro("__unix__"); 513 Builder.defineMacro("__ELF__"); 514 if (Opts.POSIXThreads) 515 Builder.defineMacro("_REENTRANT"); 516 517 switch (Triple.getArch()) { 518 default: 519 break; 520 case llvm::Triple::arm: 521 case llvm::Triple::armeb: 522 case llvm::Triple::thumb: 523 case llvm::Triple::thumbeb: 524 Builder.defineMacro("__ARM_DWARF_EH__"); 525 break; 526 } 527 } 528 public: 529 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 530 : OSTargetInfo<Target>(Triple, Opts) { 531 this->MCountName = "_mcount"; 532 } 533 }; 534 535 // OpenBSD Target 536 template<typename Target> 537 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 538 protected: 539 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 540 MacroBuilder &Builder) const override { 541 // OpenBSD defines; list based off of gcc output 542 543 Builder.defineMacro("__OpenBSD__"); 544 DefineStd(Builder, "unix", Opts); 545 Builder.defineMacro("__ELF__"); 546 if (Opts.POSIXThreads) 547 Builder.defineMacro("_REENTRANT"); 548 if (this->HasFloat128) 549 Builder.defineMacro("__FLOAT128__"); 550 } 551 public: 552 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 553 : OSTargetInfo<Target>(Triple, Opts) { 554 this->TLSSupported = false; 555 556 switch (Triple.getArch()) { 557 case llvm::Triple::x86: 558 case llvm::Triple::x86_64: 559 this->HasFloat128 = true; 560 // FALLTHROUGH 561 default: 562 this->MCountName = "__mcount"; 563 break; 564 case llvm::Triple::mips64: 565 case llvm::Triple::mips64el: 566 case llvm::Triple::ppc: 567 case llvm::Triple::sparcv9: 568 this->MCountName = "_mcount"; 569 break; 570 } 571 } 572 }; 573 574 // Bitrig Target 575 template<typename Target> 576 class BitrigTargetInfo : public OSTargetInfo<Target> { 577 protected: 578 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 579 MacroBuilder &Builder) const override { 580 // Bitrig defines; list based off of gcc output 581 582 Builder.defineMacro("__Bitrig__"); 583 DefineStd(Builder, "unix", Opts); 584 Builder.defineMacro("__ELF__"); 585 if (Opts.POSIXThreads) 586 Builder.defineMacro("_REENTRANT"); 587 588 switch (Triple.getArch()) { 589 default: 590 break; 591 case llvm::Triple::arm: 592 case llvm::Triple::armeb: 593 case llvm::Triple::thumb: 594 case llvm::Triple::thumbeb: 595 Builder.defineMacro("__ARM_DWARF_EH__"); 596 break; 597 } 598 } 599 public: 600 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 601 : OSTargetInfo<Target>(Triple, Opts) { 602 this->MCountName = "__mcount"; 603 } 604 }; 605 606 // PSP Target 607 template<typename Target> 608 class PSPTargetInfo : public OSTargetInfo<Target> { 609 protected: 610 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 611 MacroBuilder &Builder) const override { 612 // PSP defines; list based on the output of the pspdev gcc toolchain. 613 Builder.defineMacro("PSP"); 614 Builder.defineMacro("_PSP"); 615 Builder.defineMacro("__psp__"); 616 Builder.defineMacro("__ELF__"); 617 } 618 public: 619 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 620 }; 621 622 // PS3 PPU Target 623 template<typename Target> 624 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 625 protected: 626 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 627 MacroBuilder &Builder) const override { 628 // PS3 PPU defines. 629 Builder.defineMacro("__PPC__"); 630 Builder.defineMacro("__PPU__"); 631 Builder.defineMacro("__CELLOS_LV2__"); 632 Builder.defineMacro("__ELF__"); 633 Builder.defineMacro("__LP32__"); 634 Builder.defineMacro("_ARCH_PPC64"); 635 Builder.defineMacro("__powerpc64__"); 636 } 637 public: 638 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 639 : OSTargetInfo<Target>(Triple, Opts) { 640 this->LongWidth = this->LongAlign = 32; 641 this->PointerWidth = this->PointerAlign = 32; 642 this->IntMaxType = TargetInfo::SignedLongLong; 643 this->Int64Type = TargetInfo::SignedLongLong; 644 this->SizeType = TargetInfo::UnsignedInt; 645 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 646 } 647 }; 648 649 template <typename Target> 650 class PS4OSTargetInfo : public OSTargetInfo<Target> { 651 protected: 652 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 653 MacroBuilder &Builder) const override { 654 Builder.defineMacro("__FreeBSD__", "9"); 655 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 656 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 657 DefineStd(Builder, "unix", Opts); 658 Builder.defineMacro("__ELF__"); 659 Builder.defineMacro("__ORBIS__"); 660 } 661 public: 662 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 663 : OSTargetInfo<Target>(Triple, Opts) { 664 this->WCharType = this->UnsignedShort; 665 666 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 667 this->MaxTLSAlign = 256; 668 669 // On PS4, do not honor explicit bit field alignment, 670 // as in "__attribute__((aligned(2))) int b : 1;". 671 this->UseExplicitBitFieldAlignment = false; 672 673 switch (Triple.getArch()) { 674 default: 675 case llvm::Triple::x86_64: 676 this->MCountName = ".mcount"; 677 break; 678 } 679 } 680 }; 681 682 // Solaris target 683 template<typename Target> 684 class SolarisTargetInfo : public OSTargetInfo<Target> { 685 protected: 686 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 687 MacroBuilder &Builder) const override { 688 DefineStd(Builder, "sun", Opts); 689 DefineStd(Builder, "unix", Opts); 690 Builder.defineMacro("__ELF__"); 691 Builder.defineMacro("__svr4__"); 692 Builder.defineMacro("__SVR4"); 693 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 694 // newer, but to 500 for everything else. feature_test.h has a check to 695 // ensure that you are not using C99 with an old version of X/Open or C89 696 // with a new version. 697 if (Opts.C99) 698 Builder.defineMacro("_XOPEN_SOURCE", "600"); 699 else 700 Builder.defineMacro("_XOPEN_SOURCE", "500"); 701 if (Opts.CPlusPlus) 702 Builder.defineMacro("__C99FEATURES__"); 703 Builder.defineMacro("_LARGEFILE_SOURCE"); 704 Builder.defineMacro("_LARGEFILE64_SOURCE"); 705 Builder.defineMacro("__EXTENSIONS__"); 706 Builder.defineMacro("_REENTRANT"); 707 } 708 public: 709 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 710 : OSTargetInfo<Target>(Triple, Opts) { 711 this->WCharType = this->SignedInt; 712 // FIXME: WIntType should be SignedLong 713 } 714 }; 715 716 // Windows target 717 template<typename Target> 718 class WindowsTargetInfo : public OSTargetInfo<Target> { 719 protected: 720 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 721 MacroBuilder &Builder) const override { 722 Builder.defineMacro("_WIN32"); 723 } 724 void getVisualStudioDefines(const LangOptions &Opts, 725 MacroBuilder &Builder) const { 726 if (Opts.CPlusPlus) { 727 if (Opts.RTTIData) 728 Builder.defineMacro("_CPPRTTI"); 729 730 if (Opts.CXXExceptions) 731 Builder.defineMacro("_CPPUNWIND"); 732 } 733 734 if (Opts.Bool) 735 Builder.defineMacro("__BOOL_DEFINED"); 736 737 if (!Opts.CharIsSigned) 738 Builder.defineMacro("_CHAR_UNSIGNED"); 739 740 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 741 // but it works for now. 742 if (Opts.POSIXThreads) 743 Builder.defineMacro("_MT"); 744 745 if (Opts.MSCompatibilityVersion) { 746 Builder.defineMacro("_MSC_VER", 747 Twine(Opts.MSCompatibilityVersion / 100000)); 748 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 749 // FIXME We cannot encode the revision information into 32-bits 750 Builder.defineMacro("_MSC_BUILD", Twine(1)); 751 752 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 753 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 754 755 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 756 if (Opts.CPlusPlus1z) 757 Builder.defineMacro("_MSVC_LANG", "201403L"); 758 else if (Opts.CPlusPlus14) 759 Builder.defineMacro("_MSVC_LANG", "201402L"); 760 } 761 } 762 763 if (Opts.MicrosoftExt) { 764 Builder.defineMacro("_MSC_EXTENSIONS"); 765 766 if (Opts.CPlusPlus11) { 767 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 768 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 769 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 770 } 771 } 772 773 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 774 } 775 776 public: 777 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 778 : OSTargetInfo<Target>(Triple, Opts) {} 779 }; 780 781 template <typename Target> 782 class NaClTargetInfo : public OSTargetInfo<Target> { 783 protected: 784 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 785 MacroBuilder &Builder) const override { 786 if (Opts.POSIXThreads) 787 Builder.defineMacro("_REENTRANT"); 788 if (Opts.CPlusPlus) 789 Builder.defineMacro("_GNU_SOURCE"); 790 791 DefineStd(Builder, "unix", Opts); 792 Builder.defineMacro("__ELF__"); 793 Builder.defineMacro("__native_client__"); 794 } 795 796 public: 797 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 798 : OSTargetInfo<Target>(Triple, Opts) { 799 this->LongAlign = 32; 800 this->LongWidth = 32; 801 this->PointerAlign = 32; 802 this->PointerWidth = 32; 803 this->IntMaxType = TargetInfo::SignedLongLong; 804 this->Int64Type = TargetInfo::SignedLongLong; 805 this->DoubleAlign = 64; 806 this->LongDoubleWidth = 64; 807 this->LongDoubleAlign = 64; 808 this->LongLongWidth = 64; 809 this->LongLongAlign = 64; 810 this->SizeType = TargetInfo::UnsignedInt; 811 this->PtrDiffType = TargetInfo::SignedInt; 812 this->IntPtrType = TargetInfo::SignedInt; 813 // RegParmMax is inherited from the underlying architecture. 814 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 815 if (Triple.getArch() == llvm::Triple::arm) { 816 // Handled in ARM's setABI(). 817 } else if (Triple.getArch() == llvm::Triple::x86) { 818 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 819 } else if (Triple.getArch() == llvm::Triple::x86_64) { 820 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 821 } else if (Triple.getArch() == llvm::Triple::mipsel) { 822 // Handled on mips' setDataLayout. 823 } else { 824 assert(Triple.getArch() == llvm::Triple::le32); 825 this->resetDataLayout("e-p:32:32-i64:64"); 826 } 827 } 828 }; 829 830 // Fuchsia Target 831 template<typename Target> 832 class FuchsiaTargetInfo : public OSTargetInfo<Target> { 833 protected: 834 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 835 MacroBuilder &Builder) const override { 836 Builder.defineMacro("__Fuchsia__"); 837 Builder.defineMacro("__ELF__"); 838 if (Opts.POSIXThreads) 839 Builder.defineMacro("_REENTRANT"); 840 // Required by the libc++ locale support. 841 if (Opts.CPlusPlus) 842 Builder.defineMacro("_GNU_SOURCE"); 843 } 844 public: 845 FuchsiaTargetInfo(const llvm::Triple &Triple, 846 const TargetOptions &Opts) 847 : OSTargetInfo<Target>(Triple, Opts) { 848 this->MCountName = "__mcount"; 849 } 850 }; 851 852 // WebAssembly target 853 template <typename Target> 854 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 855 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 856 MacroBuilder &Builder) const final { 857 // A common platform macro. 858 if (Opts.POSIXThreads) 859 Builder.defineMacro("_REENTRANT"); 860 // Follow g++ convention and predefine _GNU_SOURCE for C++. 861 if (Opts.CPlusPlus) 862 Builder.defineMacro("_GNU_SOURCE"); 863 } 864 865 // As an optimization, group static init code together in a section. 866 const char *getStaticInitSectionSpecifier() const final { 867 return ".text.__startup"; 868 } 869 870 public: 871 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 872 const TargetOptions &Opts) 873 : OSTargetInfo<Target>(Triple, Opts) { 874 this->MCountName = "__mcount"; 875 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 876 } 877 }; 878 879 //===----------------------------------------------------------------------===// 880 // Specific target implementations. 881 //===----------------------------------------------------------------------===// 882 883 // PPC abstract base class 884 class PPCTargetInfo : public TargetInfo { 885 static const Builtin::Info BuiltinInfo[]; 886 static const char * const GCCRegNames[]; 887 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 888 std::string CPU; 889 890 // Target cpu features. 891 bool HasAltivec; 892 bool HasVSX; 893 bool HasP8Vector; 894 bool HasP8Crypto; 895 bool HasDirectMove; 896 bool HasQPX; 897 bool HasHTM; 898 bool HasBPERMD; 899 bool HasExtDiv; 900 bool HasP9Vector; 901 902 protected: 903 std::string ABI; 904 905 public: 906 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 907 : TargetInfo(Triple), HasAltivec(false), HasVSX(false), HasP8Vector(false), 908 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 909 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) { 910 SuitableAlign = 128; 911 SimdDefaultAlign = 128; 912 LongDoubleWidth = LongDoubleAlign = 128; 913 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 914 } 915 916 /// \brief Flags for architecture specific defines. 917 typedef enum { 918 ArchDefineNone = 0, 919 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 920 ArchDefinePpcgr = 1 << 1, 921 ArchDefinePpcsq = 1 << 2, 922 ArchDefine440 = 1 << 3, 923 ArchDefine603 = 1 << 4, 924 ArchDefine604 = 1 << 5, 925 ArchDefinePwr4 = 1 << 6, 926 ArchDefinePwr5 = 1 << 7, 927 ArchDefinePwr5x = 1 << 8, 928 ArchDefinePwr6 = 1 << 9, 929 ArchDefinePwr6x = 1 << 10, 930 ArchDefinePwr7 = 1 << 11, 931 ArchDefinePwr8 = 1 << 12, 932 ArchDefinePwr9 = 1 << 13, 933 ArchDefineA2 = 1 << 14, 934 ArchDefineA2q = 1 << 15 935 } ArchDefineTypes; 936 937 // Set the language option for altivec based on our value. 938 void adjust(LangOptions &Opts) override { 939 if (HasAltivec) 940 Opts.AltiVec = 1; 941 TargetInfo::adjust(Opts); 942 } 943 944 // Note: GCC recognizes the following additional cpus: 945 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 946 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 947 // titan, rs64. 948 bool setCPU(const std::string &Name) override { 949 bool CPUKnown = llvm::StringSwitch<bool>(Name) 950 .Case("generic", true) 951 .Case("440", true) 952 .Case("450", true) 953 .Case("601", true) 954 .Case("602", true) 955 .Case("603", true) 956 .Case("603e", true) 957 .Case("603ev", true) 958 .Case("604", true) 959 .Case("604e", true) 960 .Case("620", true) 961 .Case("630", true) 962 .Case("g3", true) 963 .Case("7400", true) 964 .Case("g4", true) 965 .Case("7450", true) 966 .Case("g4+", true) 967 .Case("750", true) 968 .Case("970", true) 969 .Case("g5", true) 970 .Case("a2", true) 971 .Case("a2q", true) 972 .Case("e500mc", true) 973 .Case("e5500", true) 974 .Case("power3", true) 975 .Case("pwr3", true) 976 .Case("power4", true) 977 .Case("pwr4", true) 978 .Case("power5", true) 979 .Case("pwr5", true) 980 .Case("power5x", true) 981 .Case("pwr5x", true) 982 .Case("power6", true) 983 .Case("pwr6", true) 984 .Case("power6x", true) 985 .Case("pwr6x", true) 986 .Case("power7", true) 987 .Case("pwr7", true) 988 .Case("power8", true) 989 .Case("pwr8", true) 990 .Case("power9", true) 991 .Case("pwr9", true) 992 .Case("powerpc", true) 993 .Case("ppc", true) 994 .Case("powerpc64", true) 995 .Case("ppc64", true) 996 .Case("powerpc64le", true) 997 .Case("ppc64le", true) 998 .Default(false); 999 1000 if (CPUKnown) 1001 CPU = Name; 1002 1003 return CPUKnown; 1004 } 1005 1006 1007 StringRef getABI() const override { return ABI; } 1008 1009 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1010 return llvm::makeArrayRef(BuiltinInfo, 1011 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 1012 } 1013 1014 bool isCLZForZeroUndef() const override { return false; } 1015 1016 void getTargetDefines(const LangOptions &Opts, 1017 MacroBuilder &Builder) const override; 1018 1019 bool 1020 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1021 StringRef CPU, 1022 const std::vector<std::string> &FeaturesVec) const override; 1023 1024 bool handleTargetFeatures(std::vector<std::string> &Features, 1025 DiagnosticsEngine &Diags) override; 1026 bool hasFeature(StringRef Feature) const override; 1027 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 1028 bool Enabled) const override; 1029 1030 ArrayRef<const char *> getGCCRegNames() const override; 1031 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 1032 bool validateAsmConstraint(const char *&Name, 1033 TargetInfo::ConstraintInfo &Info) const override { 1034 switch (*Name) { 1035 default: return false; 1036 case 'O': // Zero 1037 break; 1038 case 'b': // Base register 1039 case 'f': // Floating point register 1040 Info.setAllowsRegister(); 1041 break; 1042 // FIXME: The following are added to allow parsing. 1043 // I just took a guess at what the actions should be. 1044 // Also, is more specific checking needed? I.e. specific registers? 1045 case 'd': // Floating point register (containing 64-bit value) 1046 case 'v': // Altivec vector register 1047 Info.setAllowsRegister(); 1048 break; 1049 case 'w': 1050 switch (Name[1]) { 1051 case 'd':// VSX vector register to hold vector double data 1052 case 'f':// VSX vector register to hold vector float data 1053 case 's':// VSX vector register to hold scalar float data 1054 case 'a':// Any VSX register 1055 case 'c':// An individual CR bit 1056 break; 1057 default: 1058 return false; 1059 } 1060 Info.setAllowsRegister(); 1061 Name++; // Skip over 'w'. 1062 break; 1063 case 'h': // `MQ', `CTR', or `LINK' register 1064 case 'q': // `MQ' register 1065 case 'c': // `CTR' register 1066 case 'l': // `LINK' register 1067 case 'x': // `CR' register (condition register) number 0 1068 case 'y': // `CR' register (condition register) 1069 case 'z': // `XER[CA]' carry bit (part of the XER register) 1070 Info.setAllowsRegister(); 1071 break; 1072 case 'I': // Signed 16-bit constant 1073 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1074 // (use `L' instead for SImode constants) 1075 case 'K': // Unsigned 16-bit constant 1076 case 'L': // Signed 16-bit constant shifted left 16 bits 1077 case 'M': // Constant larger than 31 1078 case 'N': // Exact power of 2 1079 case 'P': // Constant whose negation is a signed 16-bit constant 1080 case 'G': // Floating point constant that can be loaded into a 1081 // register with one instruction per word 1082 case 'H': // Integer/Floating point constant that can be loaded 1083 // into a register using three instructions 1084 break; 1085 case 'm': // Memory operand. Note that on PowerPC targets, m can 1086 // include addresses that update the base register. It 1087 // is therefore only safe to use `m' in an asm statement 1088 // if that asm statement accesses the operand exactly once. 1089 // The asm statement must also use `%U<opno>' as a 1090 // placeholder for the "update" flag in the corresponding 1091 // load or store instruction. For example: 1092 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1093 // is correct but: 1094 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1095 // is not. Use es rather than m if you don't want the base 1096 // register to be updated. 1097 case 'e': 1098 if (Name[1] != 's') 1099 return false; 1100 // es: A "stable" memory operand; that is, one which does not 1101 // include any automodification of the base register. Unlike 1102 // `m', this constraint can be used in asm statements that 1103 // might access the operand several times, or that might not 1104 // access it at all. 1105 Info.setAllowsMemory(); 1106 Name++; // Skip over 'e'. 1107 break; 1108 case 'Q': // Memory operand that is an offset from a register (it is 1109 // usually better to use `m' or `es' in asm statements) 1110 case 'Z': // Memory operand that is an indexed or indirect from a 1111 // register (it is usually better to use `m' or `es' in 1112 // asm statements) 1113 Info.setAllowsMemory(); 1114 Info.setAllowsRegister(); 1115 break; 1116 case 'R': // AIX TOC entry 1117 case 'a': // Address operand that is an indexed or indirect from a 1118 // register (`p' is preferable for asm statements) 1119 case 'S': // Constant suitable as a 64-bit mask operand 1120 case 'T': // Constant suitable as a 32-bit mask operand 1121 case 'U': // System V Release 4 small data area reference 1122 case 't': // AND masks that can be performed by two rldic{l, r} 1123 // instructions 1124 case 'W': // Vector constant that does not require memory 1125 case 'j': // Vector constant that is all zeros. 1126 break; 1127 // End FIXME. 1128 } 1129 return true; 1130 } 1131 std::string convertConstraint(const char *&Constraint) const override { 1132 std::string R; 1133 switch (*Constraint) { 1134 case 'e': 1135 case 'w': 1136 // Two-character constraint; add "^" hint for later parsing. 1137 R = std::string("^") + std::string(Constraint, 2); 1138 Constraint++; 1139 break; 1140 default: 1141 return TargetInfo::convertConstraint(Constraint); 1142 } 1143 return R; 1144 } 1145 const char *getClobbers() const override { 1146 return ""; 1147 } 1148 int getEHDataRegisterNumber(unsigned RegNo) const override { 1149 if (RegNo == 0) return 3; 1150 if (RegNo == 1) return 4; 1151 return -1; 1152 } 1153 1154 bool hasSjLjLowering() const override { 1155 return true; 1156 } 1157 1158 bool useFloat128ManglingForLongDouble() const override { 1159 return LongDoubleWidth == 128 && 1160 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() && 1161 getTriple().isOSBinFormatELF(); 1162 } 1163 }; 1164 1165 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1166 #define BUILTIN(ID, TYPE, ATTRS) \ 1167 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1168 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1169 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1170 #include "clang/Basic/BuiltinsPPC.def" 1171 }; 1172 1173 /// handleTargetFeatures - Perform initialization based on the user 1174 /// configured set of features. 1175 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1176 DiagnosticsEngine &Diags) { 1177 for (const auto &Feature : Features) { 1178 if (Feature == "+altivec") { 1179 HasAltivec = true; 1180 } else if (Feature == "+vsx") { 1181 HasVSX = true; 1182 } else if (Feature == "+bpermd") { 1183 HasBPERMD = true; 1184 } else if (Feature == "+extdiv") { 1185 HasExtDiv = true; 1186 } else if (Feature == "+power8-vector") { 1187 HasP8Vector = true; 1188 } else if (Feature == "+crypto") { 1189 HasP8Crypto = true; 1190 } else if (Feature == "+direct-move") { 1191 HasDirectMove = true; 1192 } else if (Feature == "+qpx") { 1193 HasQPX = true; 1194 } else if (Feature == "+htm") { 1195 HasHTM = true; 1196 } else if (Feature == "+float128") { 1197 HasFloat128 = true; 1198 } else if (Feature == "+power9-vector") { 1199 HasP9Vector = true; 1200 } 1201 // TODO: Finish this list and add an assert that we've handled them 1202 // all. 1203 } 1204 1205 return true; 1206 } 1207 1208 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1209 /// #defines that are not tied to a specific subtarget. 1210 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1211 MacroBuilder &Builder) const { 1212 // Target identification. 1213 Builder.defineMacro("__ppc__"); 1214 Builder.defineMacro("__PPC__"); 1215 Builder.defineMacro("_ARCH_PPC"); 1216 Builder.defineMacro("__powerpc__"); 1217 Builder.defineMacro("__POWERPC__"); 1218 if (PointerWidth == 64) { 1219 Builder.defineMacro("_ARCH_PPC64"); 1220 Builder.defineMacro("__powerpc64__"); 1221 Builder.defineMacro("__ppc64__"); 1222 Builder.defineMacro("__PPC64__"); 1223 } 1224 1225 // Target properties. 1226 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1227 Builder.defineMacro("_LITTLE_ENDIAN"); 1228 } else { 1229 if (getTriple().getOS() != llvm::Triple::NetBSD && 1230 getTriple().getOS() != llvm::Triple::OpenBSD) 1231 Builder.defineMacro("_BIG_ENDIAN"); 1232 } 1233 1234 // ABI options. 1235 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1236 Builder.defineMacro("_CALL_ELF", "1"); 1237 if (ABI == "elfv2") 1238 Builder.defineMacro("_CALL_ELF", "2"); 1239 1240 // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but 1241 // our suppport post-dates this and it should work on all 64-bit ppc linux 1242 // platforms. It is guaranteed to work on all elfv2 platforms. 1243 if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64) 1244 Builder.defineMacro("_CALL_LINUX", "1"); 1245 1246 // Subtarget options. 1247 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1248 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1249 1250 // FIXME: Should be controlled by command line option. 1251 if (LongDoubleWidth == 128) { 1252 Builder.defineMacro("__LONG_DOUBLE_128__"); 1253 Builder.defineMacro("__LONGDOUBLE128"); 1254 } 1255 1256 // Define this for elfv2 (64-bit only) or 64-bit darwin. 1257 if (ABI == "elfv2" || 1258 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64)) 1259 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16"); 1260 1261 // CPU identification. 1262 ArchDefineTypes defs = 1263 (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1264 .Case("440", ArchDefineName) 1265 .Case("450", ArchDefineName | ArchDefine440) 1266 .Case("601", ArchDefineName) 1267 .Case("602", ArchDefineName | ArchDefinePpcgr) 1268 .Case("603", ArchDefineName | ArchDefinePpcgr) 1269 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1270 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1271 .Case("604", ArchDefineName | ArchDefinePpcgr) 1272 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1273 .Case("620", ArchDefineName | ArchDefinePpcgr) 1274 .Case("630", ArchDefineName | ArchDefinePpcgr) 1275 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1276 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1277 .Case("750", ArchDefineName | ArchDefinePpcgr) 1278 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1279 ArchDefinePpcsq) 1280 .Case("a2", ArchDefineA2) 1281 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1282 .Case("pwr3", ArchDefinePpcgr) 1283 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1284 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1285 ArchDefinePpcsq) 1286 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 | 1287 ArchDefinePpcgr | ArchDefinePpcsq) 1288 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 | 1289 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1290 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x | 1291 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1292 ArchDefinePpcsq) 1293 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 | 1294 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1295 ArchDefinePpcgr | ArchDefinePpcsq) 1296 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x | 1297 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1298 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1299 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 | 1300 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1301 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1302 ArchDefinePpcsq) 1303 .Case("power3", ArchDefinePpcgr) 1304 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1305 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1306 ArchDefinePpcsq) 1307 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1308 ArchDefinePpcgr | ArchDefinePpcsq) 1309 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1310 ArchDefinePwr4 | ArchDefinePpcgr | 1311 ArchDefinePpcsq) 1312 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1313 ArchDefinePwr5 | ArchDefinePwr4 | 1314 ArchDefinePpcgr | ArchDefinePpcsq) 1315 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 | 1316 ArchDefinePwr5x | ArchDefinePwr5 | 1317 ArchDefinePwr4 | ArchDefinePpcgr | 1318 ArchDefinePpcsq) 1319 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1320 ArchDefinePwr6 | ArchDefinePwr5x | 1321 ArchDefinePwr5 | ArchDefinePwr4 | 1322 ArchDefinePpcgr | ArchDefinePpcsq) 1323 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 1324 ArchDefinePwr6x | ArchDefinePwr6 | 1325 ArchDefinePwr5x | ArchDefinePwr5 | 1326 ArchDefinePwr4 | ArchDefinePpcgr | 1327 ArchDefinePpcsq) 1328 // powerpc64le automatically defaults to at least power8. 1329 .Case("ppc64le", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1330 ArchDefinePwr6 | ArchDefinePwr5x | 1331 ArchDefinePwr5 | ArchDefinePwr4 | 1332 ArchDefinePpcgr | ArchDefinePpcsq) 1333 .Default(ArchDefineNone); 1334 1335 if (defs & ArchDefineName) 1336 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1337 if (defs & ArchDefinePpcgr) 1338 Builder.defineMacro("_ARCH_PPCGR"); 1339 if (defs & ArchDefinePpcsq) 1340 Builder.defineMacro("_ARCH_PPCSQ"); 1341 if (defs & ArchDefine440) 1342 Builder.defineMacro("_ARCH_440"); 1343 if (defs & ArchDefine603) 1344 Builder.defineMacro("_ARCH_603"); 1345 if (defs & ArchDefine604) 1346 Builder.defineMacro("_ARCH_604"); 1347 if (defs & ArchDefinePwr4) 1348 Builder.defineMacro("_ARCH_PWR4"); 1349 if (defs & ArchDefinePwr5) 1350 Builder.defineMacro("_ARCH_PWR5"); 1351 if (defs & ArchDefinePwr5x) 1352 Builder.defineMacro("_ARCH_PWR5X"); 1353 if (defs & ArchDefinePwr6) 1354 Builder.defineMacro("_ARCH_PWR6"); 1355 if (defs & ArchDefinePwr6x) 1356 Builder.defineMacro("_ARCH_PWR6X"); 1357 if (defs & ArchDefinePwr7) 1358 Builder.defineMacro("_ARCH_PWR7"); 1359 if (defs & ArchDefinePwr8) 1360 Builder.defineMacro("_ARCH_PWR8"); 1361 if (defs & ArchDefinePwr9) 1362 Builder.defineMacro("_ARCH_PWR9"); 1363 if (defs & ArchDefineA2) 1364 Builder.defineMacro("_ARCH_A2"); 1365 if (defs & ArchDefineA2q) { 1366 Builder.defineMacro("_ARCH_A2Q"); 1367 Builder.defineMacro("_ARCH_QP"); 1368 } 1369 1370 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1371 Builder.defineMacro("__bg__"); 1372 Builder.defineMacro("__THW_BLUEGENE__"); 1373 Builder.defineMacro("__bgq__"); 1374 Builder.defineMacro("__TOS_BGQ__"); 1375 } 1376 1377 if (HasAltivec) { 1378 Builder.defineMacro("__VEC__", "10206"); 1379 Builder.defineMacro("__ALTIVEC__"); 1380 } 1381 if (HasVSX) 1382 Builder.defineMacro("__VSX__"); 1383 if (HasP8Vector) 1384 Builder.defineMacro("__POWER8_VECTOR__"); 1385 if (HasP8Crypto) 1386 Builder.defineMacro("__CRYPTO__"); 1387 if (HasHTM) 1388 Builder.defineMacro("__HTM__"); 1389 if (HasFloat128) 1390 Builder.defineMacro("__FLOAT128__"); 1391 if (HasP9Vector) 1392 Builder.defineMacro("__POWER9_VECTOR__"); 1393 1394 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1395 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1396 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1397 if (PointerWidth == 64) 1398 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1399 1400 // We have support for the bswap intrinsics so we can define this. 1401 Builder.defineMacro("__HAVE_BSWAP__", "1"); 1402 1403 // FIXME: The following are not yet generated here by Clang, but are 1404 // generated by GCC: 1405 // 1406 // _SOFT_FLOAT_ 1407 // __RECIP_PRECISION__ 1408 // __APPLE_ALTIVEC__ 1409 // __RECIP__ 1410 // __RECIPF__ 1411 // __RSQRTE__ 1412 // __RSQRTEF__ 1413 // _SOFT_DOUBLE_ 1414 // __NO_LWSYNC__ 1415 // __CMODEL_MEDIUM__ 1416 // __CMODEL_LARGE__ 1417 // _CALL_SYSV 1418 // _CALL_DARWIN 1419 // __NO_FPRS__ 1420 } 1421 1422 // Handle explicit options being passed to the compiler here: if we've 1423 // explicitly turned off vsx and turned on any of: 1424 // - power8-vector 1425 // - direct-move 1426 // - float128 1427 // - power9-vector 1428 // then go ahead and error since the customer has expressed an incompatible 1429 // set of options. 1430 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1431 const std::vector<std::string> &FeaturesVec) { 1432 1433 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1434 FeaturesVec.end()) { 1435 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1436 FeaturesVec.end()) { 1437 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1438 << "-mno-vsx"; 1439 return false; 1440 } 1441 1442 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1443 FeaturesVec.end()) { 1444 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1445 << "-mno-vsx"; 1446 return false; 1447 } 1448 1449 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1450 FeaturesVec.end()) { 1451 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1452 << "-mno-vsx"; 1453 return false; 1454 } 1455 1456 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") != 1457 FeaturesVec.end()) { 1458 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector" 1459 << "-mno-vsx"; 1460 return false; 1461 } 1462 } 1463 1464 return true; 1465 } 1466 1467 bool PPCTargetInfo::initFeatureMap( 1468 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1469 const std::vector<std::string> &FeaturesVec) const { 1470 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1471 .Case("7400", true) 1472 .Case("g4", true) 1473 .Case("7450", true) 1474 .Case("g4+", true) 1475 .Case("970", true) 1476 .Case("g5", true) 1477 .Case("pwr6", true) 1478 .Case("pwr7", true) 1479 .Case("pwr8", true) 1480 .Case("pwr9", true) 1481 .Case("ppc64", true) 1482 .Case("ppc64le", true) 1483 .Default(false); 1484 1485 Features["qpx"] = (CPU == "a2q"); 1486 Features["power9-vector"] = (CPU == "pwr9"); 1487 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1488 .Case("ppc64le", true) 1489 .Case("pwr9", true) 1490 .Case("pwr8", true) 1491 .Default(false); 1492 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1493 .Case("ppc64le", true) 1494 .Case("pwr9", true) 1495 .Case("pwr8", true) 1496 .Default(false); 1497 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1498 .Case("ppc64le", true) 1499 .Case("pwr9", true) 1500 .Case("pwr8", true) 1501 .Case("pwr7", true) 1502 .Default(false); 1503 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1504 .Case("ppc64le", true) 1505 .Case("pwr9", true) 1506 .Case("pwr8", true) 1507 .Case("pwr7", true) 1508 .Default(false); 1509 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1510 .Case("ppc64le", true) 1511 .Case("pwr9", true) 1512 .Case("pwr8", true) 1513 .Default(false); 1514 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1515 .Case("ppc64le", true) 1516 .Case("pwr9", true) 1517 .Case("pwr8", true) 1518 .Case("pwr7", true) 1519 .Default(false); 1520 Features["htm"] = llvm::StringSwitch<bool>(CPU) 1521 .Case("ppc64le", true) 1522 .Case("pwr9", true) 1523 .Case("pwr8", true) 1524 .Default(false); 1525 1526 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1527 return false; 1528 1529 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1530 } 1531 1532 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1533 return llvm::StringSwitch<bool>(Feature) 1534 .Case("powerpc", true) 1535 .Case("altivec", HasAltivec) 1536 .Case("vsx", HasVSX) 1537 .Case("power8-vector", HasP8Vector) 1538 .Case("crypto", HasP8Crypto) 1539 .Case("direct-move", HasDirectMove) 1540 .Case("qpx", HasQPX) 1541 .Case("htm", HasHTM) 1542 .Case("bpermd", HasBPERMD) 1543 .Case("extdiv", HasExtDiv) 1544 .Case("float128", HasFloat128) 1545 .Case("power9-vector", HasP9Vector) 1546 .Default(false); 1547 } 1548 1549 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1550 StringRef Name, bool Enabled) const { 1551 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1552 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1553 // incompatible options. 1554 if (Enabled) { 1555 if (Name == "direct-move" || 1556 Name == "power8-vector" || 1557 Name == "float128" || 1558 Name == "power9-vector") { 1559 // power9-vector is really a superset of power8-vector so encode that. 1560 Features[Name] = Features["vsx"] = true; 1561 if (Name == "power9-vector") 1562 Features["power8-vector"] = true; 1563 } else { 1564 Features[Name] = true; 1565 } 1566 } else { 1567 if (Name == "vsx") { 1568 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1569 Features["float128"] = Features["power9-vector"] = false; 1570 } else { 1571 Features[Name] = false; 1572 } 1573 } 1574 } 1575 1576 const char * const PPCTargetInfo::GCCRegNames[] = { 1577 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1578 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1579 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1580 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1581 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1582 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1583 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1584 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1585 "mq", "lr", "ctr", "ap", 1586 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1587 "xer", 1588 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1589 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1590 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1591 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1592 "vrsave", "vscr", 1593 "spe_acc", "spefscr", 1594 "sfp" 1595 }; 1596 1597 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1598 return llvm::makeArrayRef(GCCRegNames); 1599 } 1600 1601 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1602 // While some of these aliases do map to different registers 1603 // they still share the same register name. 1604 { { "0" }, "r0" }, 1605 { { "1"}, "r1" }, 1606 { { "2" }, "r2" }, 1607 { { "3" }, "r3" }, 1608 { { "4" }, "r4" }, 1609 { { "5" }, "r5" }, 1610 { { "6" }, "r6" }, 1611 { { "7" }, "r7" }, 1612 { { "8" }, "r8" }, 1613 { { "9" }, "r9" }, 1614 { { "10" }, "r10" }, 1615 { { "11" }, "r11" }, 1616 { { "12" }, "r12" }, 1617 { { "13" }, "r13" }, 1618 { { "14" }, "r14" }, 1619 { { "15" }, "r15" }, 1620 { { "16" }, "r16" }, 1621 { { "17" }, "r17" }, 1622 { { "18" }, "r18" }, 1623 { { "19" }, "r19" }, 1624 { { "20" }, "r20" }, 1625 { { "21" }, "r21" }, 1626 { { "22" }, "r22" }, 1627 { { "23" }, "r23" }, 1628 { { "24" }, "r24" }, 1629 { { "25" }, "r25" }, 1630 { { "26" }, "r26" }, 1631 { { "27" }, "r27" }, 1632 { { "28" }, "r28" }, 1633 { { "29" }, "r29" }, 1634 { { "30" }, "r30" }, 1635 { { "31" }, "r31" }, 1636 { { "fr0" }, "f0" }, 1637 { { "fr1" }, "f1" }, 1638 { { "fr2" }, "f2" }, 1639 { { "fr3" }, "f3" }, 1640 { { "fr4" }, "f4" }, 1641 { { "fr5" }, "f5" }, 1642 { { "fr6" }, "f6" }, 1643 { { "fr7" }, "f7" }, 1644 { { "fr8" }, "f8" }, 1645 { { "fr9" }, "f9" }, 1646 { { "fr10" }, "f10" }, 1647 { { "fr11" }, "f11" }, 1648 { { "fr12" }, "f12" }, 1649 { { "fr13" }, "f13" }, 1650 { { "fr14" }, "f14" }, 1651 { { "fr15" }, "f15" }, 1652 { { "fr16" }, "f16" }, 1653 { { "fr17" }, "f17" }, 1654 { { "fr18" }, "f18" }, 1655 { { "fr19" }, "f19" }, 1656 { { "fr20" }, "f20" }, 1657 { { "fr21" }, "f21" }, 1658 { { "fr22" }, "f22" }, 1659 { { "fr23" }, "f23" }, 1660 { { "fr24" }, "f24" }, 1661 { { "fr25" }, "f25" }, 1662 { { "fr26" }, "f26" }, 1663 { { "fr27" }, "f27" }, 1664 { { "fr28" }, "f28" }, 1665 { { "fr29" }, "f29" }, 1666 { { "fr30" }, "f30" }, 1667 { { "fr31" }, "f31" }, 1668 { { "cc" }, "cr0" }, 1669 }; 1670 1671 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1672 return llvm::makeArrayRef(GCCRegAliases); 1673 } 1674 1675 class PPC32TargetInfo : public PPCTargetInfo { 1676 public: 1677 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1678 : PPCTargetInfo(Triple, Opts) { 1679 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1680 1681 switch (getTriple().getOS()) { 1682 case llvm::Triple::Linux: 1683 case llvm::Triple::FreeBSD: 1684 case llvm::Triple::NetBSD: 1685 SizeType = UnsignedInt; 1686 PtrDiffType = SignedInt; 1687 IntPtrType = SignedInt; 1688 break; 1689 default: 1690 break; 1691 } 1692 1693 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1694 LongDoubleWidth = LongDoubleAlign = 64; 1695 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1696 } 1697 1698 // PPC32 supports atomics up to 4 bytes. 1699 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1700 } 1701 1702 BuiltinVaListKind getBuiltinVaListKind() const override { 1703 // This is the ELF definition, and is overridden by the Darwin sub-target 1704 return TargetInfo::PowerABIBuiltinVaList; 1705 } 1706 }; 1707 1708 // Note: ABI differences may eventually require us to have a separate 1709 // TargetInfo for little endian. 1710 class PPC64TargetInfo : public PPCTargetInfo { 1711 public: 1712 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1713 : PPCTargetInfo(Triple, Opts) { 1714 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1715 IntMaxType = SignedLong; 1716 Int64Type = SignedLong; 1717 1718 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1719 resetDataLayout("e-m:e-i64:64-n32:64"); 1720 ABI = "elfv2"; 1721 } else { 1722 resetDataLayout("E-m:e-i64:64-n32:64"); 1723 ABI = "elfv1"; 1724 } 1725 1726 switch (getTriple().getOS()) { 1727 case llvm::Triple::FreeBSD: 1728 LongDoubleWidth = LongDoubleAlign = 64; 1729 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1730 break; 1731 case llvm::Triple::NetBSD: 1732 IntMaxType = SignedLongLong; 1733 Int64Type = SignedLongLong; 1734 break; 1735 default: 1736 break; 1737 } 1738 1739 // PPC64 supports atomics up to 8 bytes. 1740 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1741 } 1742 BuiltinVaListKind getBuiltinVaListKind() const override { 1743 return TargetInfo::CharPtrBuiltinVaList; 1744 } 1745 // PPC64 Linux-specific ABI options. 1746 bool setABI(const std::string &Name) override { 1747 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1748 ABI = Name; 1749 return true; 1750 } 1751 return false; 1752 } 1753 }; 1754 1755 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1756 public: 1757 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1758 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1759 HasAlignMac68kSupport = true; 1760 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1761 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1762 LongLongAlign = 32; 1763 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1764 } 1765 BuiltinVaListKind getBuiltinVaListKind() const override { 1766 return TargetInfo::CharPtrBuiltinVaList; 1767 } 1768 }; 1769 1770 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1771 public: 1772 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1773 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1774 HasAlignMac68kSupport = true; 1775 resetDataLayout("E-m:o-i64:64-n32:64"); 1776 } 1777 }; 1778 1779 static const unsigned NVPTXAddrSpaceMap[] = { 1780 0, // Default 1781 1, // opencl_global 1782 3, // opencl_local 1783 4, // opencl_constant 1784 // FIXME: generic has to be added to the target 1785 0, // opencl_generic 1786 1, // cuda_device 1787 4, // cuda_constant 1788 3, // cuda_shared 1789 }; 1790 1791 class NVPTXTargetInfo : public TargetInfo { 1792 static const char *const GCCRegNames[]; 1793 static const Builtin::Info BuiltinInfo[]; 1794 CudaArch GPU; 1795 std::unique_ptr<TargetInfo> HostTarget; 1796 1797 public: 1798 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 1799 unsigned TargetPointerWidth) 1800 : TargetInfo(Triple) { 1801 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) && 1802 "NVPTX only supports 32- and 64-bit modes."); 1803 1804 TLSSupported = false; 1805 AddrSpaceMap = &NVPTXAddrSpaceMap; 1806 UseAddrSpaceMapMangling = true; 1807 1808 // Define available target features 1809 // These must be defined in sorted order! 1810 NoAsmVariants = true; 1811 GPU = CudaArch::SM_20; 1812 1813 if (TargetPointerWidth == 32) 1814 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1815 else 1816 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1817 1818 // If possible, get a TargetInfo for our host triple, so we can match its 1819 // types. 1820 llvm::Triple HostTriple(Opts.HostTriple); 1821 if (!HostTriple.isNVPTX()) 1822 HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1823 1824 // If no host target, make some guesses about the data layout and return. 1825 if (!HostTarget) { 1826 LongWidth = LongAlign = TargetPointerWidth; 1827 PointerWidth = PointerAlign = TargetPointerWidth; 1828 switch (TargetPointerWidth) { 1829 case 32: 1830 SizeType = TargetInfo::UnsignedInt; 1831 PtrDiffType = TargetInfo::SignedInt; 1832 IntPtrType = TargetInfo::SignedInt; 1833 break; 1834 case 64: 1835 SizeType = TargetInfo::UnsignedLong; 1836 PtrDiffType = TargetInfo::SignedLong; 1837 IntPtrType = TargetInfo::SignedLong; 1838 break; 1839 default: 1840 llvm_unreachable("TargetPointerWidth must be 32 or 64"); 1841 } 1842 return; 1843 } 1844 1845 // Copy properties from host target. 1846 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1847 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1848 BoolWidth = HostTarget->getBoolWidth(); 1849 BoolAlign = HostTarget->getBoolAlign(); 1850 IntWidth = HostTarget->getIntWidth(); 1851 IntAlign = HostTarget->getIntAlign(); 1852 HalfWidth = HostTarget->getHalfWidth(); 1853 HalfAlign = HostTarget->getHalfAlign(); 1854 FloatWidth = HostTarget->getFloatWidth(); 1855 FloatAlign = HostTarget->getFloatAlign(); 1856 DoubleWidth = HostTarget->getDoubleWidth(); 1857 DoubleAlign = HostTarget->getDoubleAlign(); 1858 LongWidth = HostTarget->getLongWidth(); 1859 LongAlign = HostTarget->getLongAlign(); 1860 LongLongWidth = HostTarget->getLongLongWidth(); 1861 LongLongAlign = HostTarget->getLongLongAlign(); 1862 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1863 NewAlign = HostTarget->getNewAlign(); 1864 DefaultAlignForAttributeAligned = 1865 HostTarget->getDefaultAlignForAttributeAligned(); 1866 SizeType = HostTarget->getSizeType(); 1867 IntMaxType = HostTarget->getIntMaxType(); 1868 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1869 IntPtrType = HostTarget->getIntPtrType(); 1870 WCharType = HostTarget->getWCharType(); 1871 WIntType = HostTarget->getWIntType(); 1872 Char16Type = HostTarget->getChar16Type(); 1873 Char32Type = HostTarget->getChar32Type(); 1874 Int64Type = HostTarget->getInt64Type(); 1875 SigAtomicType = HostTarget->getSigAtomicType(); 1876 ProcessIDType = HostTarget->getProcessIDType(); 1877 1878 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1879 UseZeroLengthBitfieldAlignment = 1880 HostTarget->useZeroLengthBitfieldAlignment(); 1881 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1882 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1883 1884 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and 1885 // we need those macros to be identical on host and device, because (among 1886 // other things) they affect which standard library classes are defined, and 1887 // we need all classes to be defined on both the host and device. 1888 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth(); 1889 1890 // Properties intentionally not copied from host: 1891 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1892 // host/device boundary. 1893 // - SuitableAlign: Not visible across the host/device boundary, and may 1894 // correctly be different on host/device, e.g. if host has wider vector 1895 // types than device. 1896 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1897 // as its double type, but that's not necessarily true on the host. 1898 // TODO: nvcc emits a warning when using long double on device; we should 1899 // do the same. 1900 } 1901 void getTargetDefines(const LangOptions &Opts, 1902 MacroBuilder &Builder) const override { 1903 Builder.defineMacro("__PTX__"); 1904 Builder.defineMacro("__NVPTX__"); 1905 if (Opts.CUDAIsDevice) { 1906 // Set __CUDA_ARCH__ for the GPU specified. 1907 std::string CUDAArchCode = [this] { 1908 switch (GPU) { 1909 case CudaArch::UNKNOWN: 1910 assert(false && "No GPU arch when compiling CUDA device code."); 1911 return ""; 1912 case CudaArch::SM_20: 1913 return "200"; 1914 case CudaArch::SM_21: 1915 return "210"; 1916 case CudaArch::SM_30: 1917 return "300"; 1918 case CudaArch::SM_32: 1919 return "320"; 1920 case CudaArch::SM_35: 1921 return "350"; 1922 case CudaArch::SM_37: 1923 return "370"; 1924 case CudaArch::SM_50: 1925 return "500"; 1926 case CudaArch::SM_52: 1927 return "520"; 1928 case CudaArch::SM_53: 1929 return "530"; 1930 case CudaArch::SM_60: 1931 return "600"; 1932 case CudaArch::SM_61: 1933 return "610"; 1934 case CudaArch::SM_62: 1935 return "620"; 1936 } 1937 llvm_unreachable("unhandled CudaArch"); 1938 }(); 1939 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1940 } 1941 } 1942 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1943 return llvm::makeArrayRef(BuiltinInfo, 1944 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1945 } 1946 bool 1947 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1948 StringRef CPU, 1949 const std::vector<std::string> &FeaturesVec) const override { 1950 Features["satom"] = GPU >= CudaArch::SM_60; 1951 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1952 } 1953 1954 bool hasFeature(StringRef Feature) const override { 1955 return llvm::StringSwitch<bool>(Feature) 1956 .Cases("ptx", "nvptx", true) 1957 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope. 1958 .Default(false); 1959 } 1960 1961 ArrayRef<const char *> getGCCRegNames() const override; 1962 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1963 // No aliases. 1964 return None; 1965 } 1966 bool validateAsmConstraint(const char *&Name, 1967 TargetInfo::ConstraintInfo &Info) const override { 1968 switch (*Name) { 1969 default: 1970 return false; 1971 case 'c': 1972 case 'h': 1973 case 'r': 1974 case 'l': 1975 case 'f': 1976 case 'd': 1977 Info.setAllowsRegister(); 1978 return true; 1979 } 1980 } 1981 const char *getClobbers() const override { 1982 // FIXME: Is this really right? 1983 return ""; 1984 } 1985 BuiltinVaListKind getBuiltinVaListKind() const override { 1986 // FIXME: implement 1987 return TargetInfo::CharPtrBuiltinVaList; 1988 } 1989 bool setCPU(const std::string &Name) override { 1990 GPU = StringToCudaArch(Name); 1991 return GPU != CudaArch::UNKNOWN; 1992 } 1993 void setSupportedOpenCLOpts() override { 1994 auto &Opts = getSupportedOpenCLOpts(); 1995 Opts.support("cl_clang_storage_class_specifiers"); 1996 Opts.support("cl_khr_gl_sharing"); 1997 Opts.support("cl_khr_icd"); 1998 1999 Opts.support("cl_khr_fp64"); 2000 Opts.support("cl_khr_byte_addressable_store"); 2001 Opts.support("cl_khr_global_int32_base_atomics"); 2002 Opts.support("cl_khr_global_int32_extended_atomics"); 2003 Opts.support("cl_khr_local_int32_base_atomics"); 2004 Opts.support("cl_khr_local_int32_extended_atomics"); 2005 } 2006 2007 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2008 // CUDA compilations support all of the host's calling conventions. 2009 // 2010 // TODO: We should warn if you apply a non-default CC to anything other than 2011 // a host function. 2012 if (HostTarget) 2013 return HostTarget->checkCallingConvention(CC); 2014 return CCCR_Warning; 2015 } 2016 }; 2017 2018 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 2019 #define BUILTIN(ID, TYPE, ATTRS) \ 2020 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2021 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2022 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2023 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2024 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2025 #include "clang/Basic/BuiltinsNVPTX.def" 2026 }; 2027 2028 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 2029 2030 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 2031 return llvm::makeArrayRef(GCCRegNames); 2032 } 2033 2034 static const LangAS::Map AMDGPUPrivateIsZeroMap = { 2035 4, // Default 2036 1, // opencl_global 2037 3, // opencl_local 2038 2, // opencl_constant 2039 4, // opencl_generic 2040 1, // cuda_device 2041 2, // cuda_constant 2042 3 // cuda_shared 2043 }; 2044 static const LangAS::Map AMDGPUGenericIsZeroMap = { 2045 0, // Default 2046 1, // opencl_global 2047 3, // opencl_local 2048 2, // opencl_constant 2049 0, // opencl_generic 2050 1, // cuda_device 2051 2, // cuda_constant 2052 3 // cuda_shared 2053 }; 2054 2055 // If you edit the description strings, make sure you update 2056 // getPointerWidthV(). 2057 2058 static const char *const DataLayoutStringR600 = 2059 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2060 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2061 2062 static const char *const DataLayoutStringSIPrivateIsZero = 2063 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 2064 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2065 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2066 2067 static const char *const DataLayoutStringSIGenericIsZero = 2068 "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32" 2069 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2070 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"; 2071 2072 class AMDGPUTargetInfo final : public TargetInfo { 2073 static const Builtin::Info BuiltinInfo[]; 2074 static const char * const GCCRegNames[]; 2075 2076 struct AddrSpace { 2077 unsigned Generic, Global, Local, Constant, Private; 2078 AddrSpace(bool IsGenericZero_ = false){ 2079 if (IsGenericZero_) { 2080 Generic = 0; 2081 Global = 1; 2082 Local = 3; 2083 Constant = 2; 2084 Private = 5; 2085 } else { 2086 Generic = 4; 2087 Global = 1; 2088 Local = 3; 2089 Constant = 2; 2090 Private = 0; 2091 } 2092 } 2093 }; 2094 2095 /// \brief The GPU profiles supported by the AMDGPU target. 2096 enum GPUKind { 2097 GK_NONE, 2098 GK_R600, 2099 GK_R600_DOUBLE_OPS, 2100 GK_R700, 2101 GK_R700_DOUBLE_OPS, 2102 GK_EVERGREEN, 2103 GK_EVERGREEN_DOUBLE_OPS, 2104 GK_NORTHERN_ISLANDS, 2105 GK_CAYMAN, 2106 GK_GFX6, 2107 GK_GFX7, 2108 GK_GFX8, 2109 GK_GFX9 2110 } GPU; 2111 2112 bool hasFP64:1; 2113 bool hasFMAF:1; 2114 bool hasLDEXPF:1; 2115 bool hasFullSpeedFP32Denorms:1; 2116 const AddrSpace AS; 2117 2118 static bool isAMDGCN(const llvm::Triple &TT) { 2119 return TT.getArch() == llvm::Triple::amdgcn; 2120 } 2121 2122 static bool isGenericZero(const llvm::Triple &TT) { 2123 return TT.getEnvironmentName() == "amdgiz" || 2124 TT.getEnvironmentName() == "amdgizcl"; 2125 } 2126 public: 2127 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 2128 : TargetInfo(Triple) , 2129 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600), 2130 hasFP64(false), 2131 hasFMAF(false), 2132 hasLDEXPF(false), 2133 hasFullSpeedFP32Denorms(false), 2134 AS(isGenericZero(Triple)){ 2135 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2136 hasFP64 = true; 2137 hasFMAF = true; 2138 hasLDEXPF = true; 2139 } 2140 auto IsGenericZero = isGenericZero(Triple); 2141 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 2142 (IsGenericZero ? DataLayoutStringSIGenericIsZero : 2143 DataLayoutStringSIPrivateIsZero) 2144 : DataLayoutStringR600); 2145 assert(DataLayout->getAllocaAddrSpace() == AS.Private); 2146 2147 AddrSpaceMap = IsGenericZero ? &AMDGPUGenericIsZeroMap : 2148 &AMDGPUPrivateIsZeroMap; 2149 UseAddrSpaceMapMangling = true; 2150 } 2151 2152 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 2153 if (GPU <= GK_CAYMAN) 2154 return 32; 2155 2156 if (AddrSpace == AS.Private || AddrSpace == AS.Local) { 2157 return 32; 2158 } 2159 return 64; 2160 } 2161 2162 uint64_t getMaxPointerWidth() const override { 2163 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2164 } 2165 2166 const char * getClobbers() const override { 2167 return ""; 2168 } 2169 2170 ArrayRef<const char *> getGCCRegNames() const override; 2171 2172 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2173 return None; 2174 } 2175 2176 bool validateAsmConstraint(const char *&Name, 2177 TargetInfo::ConstraintInfo &Info) const override { 2178 switch (*Name) { 2179 default: break; 2180 case 'v': // vgpr 2181 case 's': // sgpr 2182 Info.setAllowsRegister(); 2183 return true; 2184 } 2185 return false; 2186 } 2187 2188 bool initFeatureMap(llvm::StringMap<bool> &Features, 2189 DiagnosticsEngine &Diags, StringRef CPU, 2190 const std::vector<std::string> &FeatureVec) const override; 2191 2192 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2193 TargetOptions &TargetOpts) const override { 2194 bool hasFP32Denormals = false; 2195 bool hasFP64Denormals = false; 2196 for (auto &I : TargetOpts.FeaturesAsWritten) { 2197 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2198 hasFP32Denormals = true; 2199 if (I == "+fp64-fp16-denormals" || I == "-fp64-fp16-denormals") 2200 hasFP64Denormals = true; 2201 } 2202 if (!hasFP32Denormals) 2203 TargetOpts.Features.push_back((Twine(hasFullSpeedFP32Denorms && 2204 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str()); 2205 // Always do not flush fp64 or fp16 denorms. 2206 if (!hasFP64Denormals && hasFP64) 2207 TargetOpts.Features.push_back("+fp64-fp16-denormals"); 2208 } 2209 2210 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2211 return llvm::makeArrayRef(BuiltinInfo, 2212 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2213 } 2214 2215 void getTargetDefines(const LangOptions &Opts, 2216 MacroBuilder &Builder) const override { 2217 if (getTriple().getArch() == llvm::Triple::amdgcn) 2218 Builder.defineMacro("__AMDGCN__"); 2219 else 2220 Builder.defineMacro("__R600__"); 2221 2222 if (hasFMAF) 2223 Builder.defineMacro("__HAS_FMAF__"); 2224 if (hasLDEXPF) 2225 Builder.defineMacro("__HAS_LDEXPF__"); 2226 if (hasFP64) 2227 Builder.defineMacro("__HAS_FP64__"); 2228 } 2229 2230 BuiltinVaListKind getBuiltinVaListKind() const override { 2231 return TargetInfo::CharPtrBuiltinVaList; 2232 } 2233 2234 static GPUKind parseR600Name(StringRef Name) { 2235 return llvm::StringSwitch<GPUKind>(Name) 2236 .Case("r600" , GK_R600) 2237 .Case("rv610", GK_R600) 2238 .Case("rv620", GK_R600) 2239 .Case("rv630", GK_R600) 2240 .Case("rv635", GK_R600) 2241 .Case("rs780", GK_R600) 2242 .Case("rs880", GK_R600) 2243 .Case("rv670", GK_R600_DOUBLE_OPS) 2244 .Case("rv710", GK_R700) 2245 .Case("rv730", GK_R700) 2246 .Case("rv740", GK_R700_DOUBLE_OPS) 2247 .Case("rv770", GK_R700_DOUBLE_OPS) 2248 .Case("palm", GK_EVERGREEN) 2249 .Case("cedar", GK_EVERGREEN) 2250 .Case("sumo", GK_EVERGREEN) 2251 .Case("sumo2", GK_EVERGREEN) 2252 .Case("redwood", GK_EVERGREEN) 2253 .Case("juniper", GK_EVERGREEN) 2254 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2255 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2256 .Case("barts", GK_NORTHERN_ISLANDS) 2257 .Case("turks", GK_NORTHERN_ISLANDS) 2258 .Case("caicos", GK_NORTHERN_ISLANDS) 2259 .Case("cayman", GK_CAYMAN) 2260 .Case("aruba", GK_CAYMAN) 2261 .Default(GK_NONE); 2262 } 2263 2264 static GPUKind parseAMDGCNName(StringRef Name) { 2265 return llvm::StringSwitch<GPUKind>(Name) 2266 .Case("tahiti", GK_GFX6) 2267 .Case("pitcairn", GK_GFX6) 2268 .Case("verde", GK_GFX6) 2269 .Case("oland", GK_GFX6) 2270 .Case("hainan", GK_GFX6) 2271 .Case("bonaire", GK_GFX7) 2272 .Case("kabini", GK_GFX7) 2273 .Case("kaveri", GK_GFX7) 2274 .Case("hawaii", GK_GFX7) 2275 .Case("mullins", GK_GFX7) 2276 .Case("gfx700", GK_GFX7) 2277 .Case("gfx701", GK_GFX7) 2278 .Case("gfx702", GK_GFX7) 2279 .Case("tonga", GK_GFX8) 2280 .Case("iceland", GK_GFX8) 2281 .Case("carrizo", GK_GFX8) 2282 .Case("fiji", GK_GFX8) 2283 .Case("stoney", GK_GFX8) 2284 .Case("polaris10", GK_GFX8) 2285 .Case("polaris11", GK_GFX8) 2286 .Case("gfx800", GK_GFX8) 2287 .Case("gfx801", GK_GFX8) 2288 .Case("gfx802", GK_GFX8) 2289 .Case("gfx803", GK_GFX8) 2290 .Case("gfx804", GK_GFX8) 2291 .Case("gfx810", GK_GFX8) 2292 .Case("gfx900", GK_GFX9) 2293 .Case("gfx901", GK_GFX9) 2294 .Default(GK_NONE); 2295 } 2296 2297 bool setCPU(const std::string &Name) override { 2298 if (getTriple().getArch() == llvm::Triple::amdgcn) 2299 GPU = parseAMDGCNName(Name); 2300 else 2301 GPU = parseR600Name(Name); 2302 2303 return GPU != GK_NONE; 2304 } 2305 2306 void setSupportedOpenCLOpts() override { 2307 auto &Opts = getSupportedOpenCLOpts(); 2308 Opts.support("cl_clang_storage_class_specifiers"); 2309 Opts.support("cl_khr_icd"); 2310 2311 if (hasFP64) 2312 Opts.support("cl_khr_fp64"); 2313 if (GPU >= GK_EVERGREEN) { 2314 Opts.support("cl_khr_byte_addressable_store"); 2315 Opts.support("cl_khr_global_int32_base_atomics"); 2316 Opts.support("cl_khr_global_int32_extended_atomics"); 2317 Opts.support("cl_khr_local_int32_base_atomics"); 2318 Opts.support("cl_khr_local_int32_extended_atomics"); 2319 } 2320 if (GPU >= GK_GFX6) { 2321 Opts.support("cl_khr_fp16"); 2322 Opts.support("cl_khr_int64_base_atomics"); 2323 Opts.support("cl_khr_int64_extended_atomics"); 2324 Opts.support("cl_khr_mipmap_image"); 2325 Opts.support("cl_khr_subgroups"); 2326 Opts.support("cl_khr_3d_image_writes"); 2327 Opts.support("cl_amd_media_ops"); 2328 Opts.support("cl_amd_media_ops2"); 2329 } 2330 } 2331 2332 LangAS::ID getOpenCLImageAddrSpace() const override { 2333 return LangAS::opencl_constant; 2334 } 2335 2336 /// \returns Target specific vtbl ptr address space. 2337 unsigned getVtblPtrAddressSpace() const override { 2338 // \todo: We currently have address spaces defined in AMDGPU Backend. It 2339 // would be nice if we could use it here instead of using bare numbers (same 2340 // applies to getDWARFAddressSpace). 2341 return 2; // constant. 2342 } 2343 2344 /// \returns If a target requires an address within a target specific address 2345 /// space \p AddressSpace to be converted in order to be used, then return the 2346 /// corresponding target specific DWARF address space. 2347 /// 2348 /// \returns Otherwise return None and no conversion will be emitted in the 2349 /// DWARF. 2350 Optional<unsigned> getDWARFAddressSpace( 2351 unsigned AddressSpace) const override { 2352 const unsigned DWARF_Private = 1; 2353 const unsigned DWARF_Local = 2; 2354 if (AddressSpace == AS.Private) { 2355 return DWARF_Private; 2356 } else if (AddressSpace == AS.Local) { 2357 return DWARF_Local; 2358 } else { 2359 return None; 2360 } 2361 } 2362 2363 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2364 switch (CC) { 2365 default: 2366 return CCCR_Warning; 2367 case CC_C: 2368 case CC_OpenCLKernel: 2369 return CCCR_OK; 2370 } 2371 } 2372 2373 // In amdgcn target the null pointer in global, constant, and generic 2374 // address space has value 0 but in private and local address space has 2375 // value ~0. 2376 uint64_t getNullPointerValue(unsigned AS) const override { 2377 return AS == LangAS::opencl_local ? ~0 : 0; 2378 } 2379 }; 2380 2381 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2382 #define BUILTIN(ID, TYPE, ATTRS) \ 2383 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2384 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2385 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2386 #include "clang/Basic/BuiltinsAMDGPU.def" 2387 }; 2388 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2389 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2390 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2391 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2392 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2393 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2394 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2395 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2396 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2397 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2398 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2399 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2400 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2401 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2402 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2403 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2404 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2405 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2406 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2407 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2408 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2409 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2410 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2411 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2412 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2413 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2414 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2415 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2416 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2417 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2418 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2419 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2420 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2421 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2422 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2423 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2424 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2425 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2426 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2427 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2428 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2429 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2430 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2431 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2432 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2433 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2434 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2435 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2436 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2437 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2438 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2439 }; 2440 2441 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2442 return llvm::makeArrayRef(GCCRegNames); 2443 } 2444 2445 bool AMDGPUTargetInfo::initFeatureMap( 2446 llvm::StringMap<bool> &Features, 2447 DiagnosticsEngine &Diags, StringRef CPU, 2448 const std::vector<std::string> &FeatureVec) const { 2449 2450 // XXX - What does the member GPU mean if device name string passed here? 2451 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2452 if (CPU.empty()) 2453 CPU = "tahiti"; 2454 2455 switch (parseAMDGCNName(CPU)) { 2456 case GK_GFX6: 2457 case GK_GFX7: 2458 break; 2459 2460 case GK_GFX9: 2461 Features["gfx9-insts"] = true; 2462 LLVM_FALLTHROUGH; 2463 case GK_GFX8: 2464 Features["s-memrealtime"] = true; 2465 Features["16-bit-insts"] = true; 2466 Features["dpp"] = true; 2467 break; 2468 2469 case GK_NONE: 2470 return false; 2471 default: 2472 llvm_unreachable("unhandled subtarget"); 2473 } 2474 } else { 2475 if (CPU.empty()) 2476 CPU = "r600"; 2477 2478 switch (parseR600Name(CPU)) { 2479 case GK_R600: 2480 case GK_R700: 2481 case GK_EVERGREEN: 2482 case GK_NORTHERN_ISLANDS: 2483 break; 2484 case GK_R600_DOUBLE_OPS: 2485 case GK_R700_DOUBLE_OPS: 2486 case GK_EVERGREEN_DOUBLE_OPS: 2487 case GK_CAYMAN: 2488 Features["fp64"] = true; 2489 break; 2490 case GK_NONE: 2491 return false; 2492 default: 2493 llvm_unreachable("unhandled subtarget"); 2494 } 2495 } 2496 2497 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2498 } 2499 2500 const Builtin::Info BuiltinInfoX86[] = { 2501 #define BUILTIN(ID, TYPE, ATTRS) \ 2502 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2503 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2504 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2505 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2506 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2507 #include "clang/Basic/BuiltinsX86.def" 2508 2509 #define BUILTIN(ID, TYPE, ATTRS) \ 2510 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2511 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2512 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2513 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2514 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2515 #include "clang/Basic/BuiltinsX86_64.def" 2516 }; 2517 2518 2519 static const char* const GCCRegNames[] = { 2520 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2521 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2522 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2523 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2524 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2525 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2526 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2527 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2528 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2529 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2530 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2531 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2532 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2533 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2534 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2535 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2536 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2537 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", 2538 }; 2539 2540 const TargetInfo::AddlRegName AddlRegNames[] = { 2541 { { "al", "ah", "eax", "rax" }, 0 }, 2542 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2543 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2544 { { "dl", "dh", "edx", "rdx" }, 1 }, 2545 { { "esi", "rsi" }, 4 }, 2546 { { "edi", "rdi" }, 5 }, 2547 { { "esp", "rsp" }, 7 }, 2548 { { "ebp", "rbp" }, 6 }, 2549 { { "r8d", "r8w", "r8b" }, 38 }, 2550 { { "r9d", "r9w", "r9b" }, 39 }, 2551 { { "r10d", "r10w", "r10b" }, 40 }, 2552 { { "r11d", "r11w", "r11b" }, 41 }, 2553 { { "r12d", "r12w", "r12b" }, 42 }, 2554 { { "r13d", "r13w", "r13b" }, 43 }, 2555 { { "r14d", "r14w", "r14b" }, 44 }, 2556 { { "r15d", "r15w", "r15b" }, 45 }, 2557 }; 2558 2559 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2560 // most of the implementation can be shared. 2561 class X86TargetInfo : public TargetInfo { 2562 enum X86SSEEnum { 2563 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2564 } SSELevel = NoSSE; 2565 enum MMX3DNowEnum { 2566 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2567 } MMX3DNowLevel = NoMMX3DNow; 2568 enum XOPEnum { 2569 NoXOP, 2570 SSE4A, 2571 FMA4, 2572 XOP 2573 } XOPLevel = NoXOP; 2574 2575 bool HasAES = false; 2576 bool HasPCLMUL = false; 2577 bool HasLZCNT = false; 2578 bool HasRDRND = false; 2579 bool HasFSGSBASE = false; 2580 bool HasBMI = false; 2581 bool HasBMI2 = false; 2582 bool HasPOPCNT = false; 2583 bool HasRTM = false; 2584 bool HasPRFCHW = false; 2585 bool HasRDSEED = false; 2586 bool HasADX = false; 2587 bool HasTBM = false; 2588 bool HasFMA = false; 2589 bool HasF16C = false; 2590 bool HasAVX512CD = false; 2591 bool HasAVX512ER = false; 2592 bool HasAVX512PF = false; 2593 bool HasAVX512DQ = false; 2594 bool HasAVX512BW = false; 2595 bool HasAVX512VL = false; 2596 bool HasAVX512VBMI = false; 2597 bool HasAVX512IFMA = false; 2598 bool HasSHA = false; 2599 bool HasMPX = false; 2600 bool HasSGX = false; 2601 bool HasCX16 = false; 2602 bool HasFXSR = false; 2603 bool HasXSAVE = false; 2604 bool HasXSAVEOPT = false; 2605 bool HasXSAVEC = false; 2606 bool HasXSAVES = false; 2607 bool HasMWAITX = false; 2608 bool HasCLZERO = false; 2609 bool HasPKU = false; 2610 bool HasCLFLUSHOPT = false; 2611 bool HasCLWB = false; 2612 bool HasMOVBE = false; 2613 bool HasPREFETCHWT1 = false; 2614 2615 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2616 /// 2617 /// Each enumeration represents a particular CPU supported by Clang. These 2618 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2619 enum CPUKind { 2620 CK_Generic, 2621 2622 /// \name i386 2623 /// i386-generation processors. 2624 //@{ 2625 CK_i386, 2626 //@} 2627 2628 /// \name i486 2629 /// i486-generation processors. 2630 //@{ 2631 CK_i486, 2632 CK_WinChipC6, 2633 CK_WinChip2, 2634 CK_C3, 2635 //@} 2636 2637 /// \name i586 2638 /// i586-generation processors, P5 microarchitecture based. 2639 //@{ 2640 CK_i586, 2641 CK_Pentium, 2642 CK_PentiumMMX, 2643 //@} 2644 2645 /// \name i686 2646 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2647 //@{ 2648 CK_i686, 2649 CK_PentiumPro, 2650 CK_Pentium2, 2651 CK_Pentium3, 2652 CK_Pentium3M, 2653 CK_PentiumM, 2654 CK_C3_2, 2655 2656 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2657 /// Clang however has some logic to suport this. 2658 // FIXME: Warn, deprecate, and potentially remove this. 2659 CK_Yonah, 2660 //@} 2661 2662 /// \name Netburst 2663 /// Netburst microarchitecture based processors. 2664 //@{ 2665 CK_Pentium4, 2666 CK_Pentium4M, 2667 CK_Prescott, 2668 CK_Nocona, 2669 //@} 2670 2671 /// \name Core 2672 /// Core microarchitecture based processors. 2673 //@{ 2674 CK_Core2, 2675 2676 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2677 /// codename which GCC no longer accepts as an option to -march, but Clang 2678 /// has some logic for recognizing it. 2679 // FIXME: Warn, deprecate, and potentially remove this. 2680 CK_Penryn, 2681 //@} 2682 2683 /// \name Atom 2684 /// Atom processors 2685 //@{ 2686 CK_Bonnell, 2687 CK_Silvermont, 2688 //@} 2689 2690 /// \name Nehalem 2691 /// Nehalem microarchitecture based processors. 2692 CK_Nehalem, 2693 2694 /// \name Westmere 2695 /// Westmere microarchitecture based processors. 2696 CK_Westmere, 2697 2698 /// \name Sandy Bridge 2699 /// Sandy Bridge microarchitecture based processors. 2700 CK_SandyBridge, 2701 2702 /// \name Ivy Bridge 2703 /// Ivy Bridge microarchitecture based processors. 2704 CK_IvyBridge, 2705 2706 /// \name Haswell 2707 /// Haswell microarchitecture based processors. 2708 CK_Haswell, 2709 2710 /// \name Broadwell 2711 /// Broadwell microarchitecture based processors. 2712 CK_Broadwell, 2713 2714 /// \name Skylake Client 2715 /// Skylake client microarchitecture based processors. 2716 CK_SkylakeClient, 2717 2718 /// \name Skylake Server 2719 /// Skylake server microarchitecture based processors. 2720 CK_SkylakeServer, 2721 2722 /// \name Cannonlake Client 2723 /// Cannonlake client microarchitecture based processors. 2724 CK_Cannonlake, 2725 2726 /// \name Knights Landing 2727 /// Knights Landing processor. 2728 CK_KNL, 2729 2730 /// \name Lakemont 2731 /// Lakemont microarchitecture based processors. 2732 CK_Lakemont, 2733 2734 /// \name K6 2735 /// K6 architecture processors. 2736 //@{ 2737 CK_K6, 2738 CK_K6_2, 2739 CK_K6_3, 2740 //@} 2741 2742 /// \name K7 2743 /// K7 architecture processors. 2744 //@{ 2745 CK_Athlon, 2746 CK_AthlonThunderbird, 2747 CK_Athlon4, 2748 CK_AthlonXP, 2749 CK_AthlonMP, 2750 //@} 2751 2752 /// \name K8 2753 /// K8 architecture processors. 2754 //@{ 2755 CK_Athlon64, 2756 CK_Athlon64SSE3, 2757 CK_AthlonFX, 2758 CK_K8, 2759 CK_K8SSE3, 2760 CK_Opteron, 2761 CK_OpteronSSE3, 2762 CK_AMDFAM10, 2763 //@} 2764 2765 /// \name Bobcat 2766 /// Bobcat architecture processors. 2767 //@{ 2768 CK_BTVER1, 2769 CK_BTVER2, 2770 //@} 2771 2772 /// \name Bulldozer 2773 /// Bulldozer architecture processors. 2774 //@{ 2775 CK_BDVER1, 2776 CK_BDVER2, 2777 CK_BDVER3, 2778 CK_BDVER4, 2779 //@} 2780 2781 /// \name zen 2782 /// Zen architecture processors. 2783 //@{ 2784 CK_ZNVER1, 2785 //@} 2786 2787 /// This specification is deprecated and will be removed in the future. 2788 /// Users should prefer \see CK_K8. 2789 // FIXME: Warn on this when the CPU is set to it. 2790 //@{ 2791 CK_x86_64, 2792 //@} 2793 2794 /// \name Geode 2795 /// Geode processors. 2796 //@{ 2797 CK_Geode 2798 //@} 2799 } CPU = CK_Generic; 2800 2801 CPUKind getCPUKind(StringRef CPU) const { 2802 return llvm::StringSwitch<CPUKind>(CPU) 2803 .Case("i386", CK_i386) 2804 .Case("i486", CK_i486) 2805 .Case("winchip-c6", CK_WinChipC6) 2806 .Case("winchip2", CK_WinChip2) 2807 .Case("c3", CK_C3) 2808 .Case("i586", CK_i586) 2809 .Case("pentium", CK_Pentium) 2810 .Case("pentium-mmx", CK_PentiumMMX) 2811 .Case("i686", CK_i686) 2812 .Case("pentiumpro", CK_PentiumPro) 2813 .Case("pentium2", CK_Pentium2) 2814 .Case("pentium3", CK_Pentium3) 2815 .Case("pentium3m", CK_Pentium3M) 2816 .Case("pentium-m", CK_PentiumM) 2817 .Case("c3-2", CK_C3_2) 2818 .Case("yonah", CK_Yonah) 2819 .Case("pentium4", CK_Pentium4) 2820 .Case("pentium4m", CK_Pentium4M) 2821 .Case("prescott", CK_Prescott) 2822 .Case("nocona", CK_Nocona) 2823 .Case("core2", CK_Core2) 2824 .Case("penryn", CK_Penryn) 2825 .Case("bonnell", CK_Bonnell) 2826 .Case("atom", CK_Bonnell) // Legacy name. 2827 .Case("silvermont", CK_Silvermont) 2828 .Case("slm", CK_Silvermont) // Legacy name. 2829 .Case("nehalem", CK_Nehalem) 2830 .Case("corei7", CK_Nehalem) // Legacy name. 2831 .Case("westmere", CK_Westmere) 2832 .Case("sandybridge", CK_SandyBridge) 2833 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2834 .Case("ivybridge", CK_IvyBridge) 2835 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2836 .Case("haswell", CK_Haswell) 2837 .Case("core-avx2", CK_Haswell) // Legacy name. 2838 .Case("broadwell", CK_Broadwell) 2839 .Case("skylake", CK_SkylakeClient) 2840 .Case("skylake-avx512", CK_SkylakeServer) 2841 .Case("skx", CK_SkylakeServer) // Legacy name. 2842 .Case("cannonlake", CK_Cannonlake) 2843 .Case("knl", CK_KNL) 2844 .Case("lakemont", CK_Lakemont) 2845 .Case("k6", CK_K6) 2846 .Case("k6-2", CK_K6_2) 2847 .Case("k6-3", CK_K6_3) 2848 .Case("athlon", CK_Athlon) 2849 .Case("athlon-tbird", CK_AthlonThunderbird) 2850 .Case("athlon-4", CK_Athlon4) 2851 .Case("athlon-xp", CK_AthlonXP) 2852 .Case("athlon-mp", CK_AthlonMP) 2853 .Case("athlon64", CK_Athlon64) 2854 .Case("athlon64-sse3", CK_Athlon64SSE3) 2855 .Case("athlon-fx", CK_AthlonFX) 2856 .Case("k8", CK_K8) 2857 .Case("k8-sse3", CK_K8SSE3) 2858 .Case("opteron", CK_Opteron) 2859 .Case("opteron-sse3", CK_OpteronSSE3) 2860 .Case("barcelona", CK_AMDFAM10) 2861 .Case("amdfam10", CK_AMDFAM10) 2862 .Case("btver1", CK_BTVER1) 2863 .Case("btver2", CK_BTVER2) 2864 .Case("bdver1", CK_BDVER1) 2865 .Case("bdver2", CK_BDVER2) 2866 .Case("bdver3", CK_BDVER3) 2867 .Case("bdver4", CK_BDVER4) 2868 .Case("znver1", CK_ZNVER1) 2869 .Case("x86-64", CK_x86_64) 2870 .Case("geode", CK_Geode) 2871 .Default(CK_Generic); 2872 } 2873 2874 enum FPMathKind { 2875 FP_Default, 2876 FP_SSE, 2877 FP_387 2878 } FPMath = FP_Default; 2879 2880 public: 2881 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2882 : TargetInfo(Triple) { 2883 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 2884 } 2885 unsigned getFloatEvalMethod() const override { 2886 // X87 evaluates with 80 bits "long double" precision. 2887 return SSELevel == NoSSE ? 2 : 0; 2888 } 2889 ArrayRef<const char *> getGCCRegNames() const override { 2890 return llvm::makeArrayRef(GCCRegNames); 2891 } 2892 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2893 return None; 2894 } 2895 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2896 return llvm::makeArrayRef(AddlRegNames); 2897 } 2898 bool validateCpuSupports(StringRef Name) const override; 2899 bool validateAsmConstraint(const char *&Name, 2900 TargetInfo::ConstraintInfo &info) const override; 2901 2902 bool validateGlobalRegisterVariable(StringRef RegName, 2903 unsigned RegSize, 2904 bool &HasSizeMismatch) const override { 2905 // esp and ebp are the only 32-bit registers the x86 backend can currently 2906 // handle. 2907 if (RegName.equals("esp") || RegName.equals("ebp")) { 2908 // Check that the register size is 32-bit. 2909 HasSizeMismatch = RegSize != 32; 2910 return true; 2911 } 2912 2913 return false; 2914 } 2915 2916 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2917 2918 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2919 2920 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2921 2922 std::string convertConstraint(const char *&Constraint) const override; 2923 const char *getClobbers() const override { 2924 return "~{dirflag},~{fpsr},~{flags}"; 2925 } 2926 2927 StringRef getConstraintRegister(const StringRef &Constraint, 2928 const StringRef &Expression) const override { 2929 StringRef::iterator I, E; 2930 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) { 2931 if (isalpha(*I)) 2932 break; 2933 } 2934 if (I == E) 2935 return ""; 2936 switch (*I) { 2937 // For the register constraints, return the matching register name 2938 case 'a': 2939 return "ax"; 2940 case 'b': 2941 return "bx"; 2942 case 'c': 2943 return "cx"; 2944 case 'd': 2945 return "dx"; 2946 case 'S': 2947 return "si"; 2948 case 'D': 2949 return "di"; 2950 // In case the constraint is 'r' we need to return Expression 2951 case 'r': 2952 return Expression; 2953 default: 2954 // Default value if there is no constraint for the register 2955 return ""; 2956 } 2957 return ""; 2958 } 2959 2960 void getTargetDefines(const LangOptions &Opts, 2961 MacroBuilder &Builder) const override; 2962 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2963 bool Enabled); 2964 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2965 bool Enabled); 2966 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2967 bool Enabled); 2968 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2969 StringRef Name, bool Enabled) const override { 2970 setFeatureEnabledImpl(Features, Name, Enabled); 2971 } 2972 // This exists purely to cut down on the number of virtual calls in 2973 // initFeatureMap which calls this repeatedly. 2974 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2975 StringRef Name, bool Enabled); 2976 bool 2977 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2978 StringRef CPU, 2979 const std::vector<std::string> &FeaturesVec) const override; 2980 bool hasFeature(StringRef Feature) const override; 2981 bool handleTargetFeatures(std::vector<std::string> &Features, 2982 DiagnosticsEngine &Diags) override; 2983 StringRef getABI() const override { 2984 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2985 return "avx512"; 2986 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2987 return "avx"; 2988 if (getTriple().getArch() == llvm::Triple::x86 && 2989 MMX3DNowLevel == NoMMX3DNow) 2990 return "no-mmx"; 2991 return ""; 2992 } 2993 bool setCPU(const std::string &Name) override { 2994 CPU = getCPUKind(Name); 2995 2996 // Perform any per-CPU checks necessary to determine if this CPU is 2997 // acceptable. 2998 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2999 // invalid without explaining *why*. 3000 switch (CPU) { 3001 case CK_Generic: 3002 // No processor selected! 3003 return false; 3004 3005 case CK_i386: 3006 case CK_i486: 3007 case CK_WinChipC6: 3008 case CK_WinChip2: 3009 case CK_C3: 3010 case CK_i586: 3011 case CK_Pentium: 3012 case CK_PentiumMMX: 3013 case CK_i686: 3014 case CK_PentiumPro: 3015 case CK_Pentium2: 3016 case CK_Pentium3: 3017 case CK_Pentium3M: 3018 case CK_PentiumM: 3019 case CK_Yonah: 3020 case CK_C3_2: 3021 case CK_Pentium4: 3022 case CK_Pentium4M: 3023 case CK_Lakemont: 3024 case CK_Prescott: 3025 case CK_K6: 3026 case CK_K6_2: 3027 case CK_K6_3: 3028 case CK_Athlon: 3029 case CK_AthlonThunderbird: 3030 case CK_Athlon4: 3031 case CK_AthlonXP: 3032 case CK_AthlonMP: 3033 case CK_Geode: 3034 // Only accept certain architectures when compiling in 32-bit mode. 3035 if (getTriple().getArch() != llvm::Triple::x86) 3036 return false; 3037 3038 // Fallthrough 3039 case CK_Nocona: 3040 case CK_Core2: 3041 case CK_Penryn: 3042 case CK_Bonnell: 3043 case CK_Silvermont: 3044 case CK_Nehalem: 3045 case CK_Westmere: 3046 case CK_SandyBridge: 3047 case CK_IvyBridge: 3048 case CK_Haswell: 3049 case CK_Broadwell: 3050 case CK_SkylakeClient: 3051 case CK_SkylakeServer: 3052 case CK_Cannonlake: 3053 case CK_KNL: 3054 case CK_Athlon64: 3055 case CK_Athlon64SSE3: 3056 case CK_AthlonFX: 3057 case CK_K8: 3058 case CK_K8SSE3: 3059 case CK_Opteron: 3060 case CK_OpteronSSE3: 3061 case CK_AMDFAM10: 3062 case CK_BTVER1: 3063 case CK_BTVER2: 3064 case CK_BDVER1: 3065 case CK_BDVER2: 3066 case CK_BDVER3: 3067 case CK_BDVER4: 3068 case CK_ZNVER1: 3069 case CK_x86_64: 3070 return true; 3071 } 3072 llvm_unreachable("Unhandled CPU kind"); 3073 } 3074 3075 bool setFPMath(StringRef Name) override; 3076 3077 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3078 // Most of the non-ARM calling conventions are i386 conventions. 3079 switch (CC) { 3080 case CC_X86ThisCall: 3081 case CC_X86FastCall: 3082 case CC_X86StdCall: 3083 case CC_X86VectorCall: 3084 case CC_X86RegCall: 3085 case CC_C: 3086 case CC_Swift: 3087 case CC_X86Pascal: 3088 case CC_IntelOclBicc: 3089 return CCCR_OK; 3090 default: 3091 return CCCR_Warning; 3092 } 3093 } 3094 3095 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3096 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 3097 } 3098 3099 bool hasSjLjLowering() const override { 3100 return true; 3101 } 3102 3103 void setSupportedOpenCLOpts() override { 3104 getSupportedOpenCLOpts().supportAll(); 3105 } 3106 }; 3107 3108 bool X86TargetInfo::setFPMath(StringRef Name) { 3109 if (Name == "387") { 3110 FPMath = FP_387; 3111 return true; 3112 } 3113 if (Name == "sse") { 3114 FPMath = FP_SSE; 3115 return true; 3116 } 3117 return false; 3118 } 3119 3120 bool X86TargetInfo::initFeatureMap( 3121 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 3122 const std::vector<std::string> &FeaturesVec) const { 3123 // FIXME: This *really* should not be here. 3124 // X86_64 always has SSE2. 3125 if (getTriple().getArch() == llvm::Triple::x86_64) 3126 setFeatureEnabledImpl(Features, "sse2", true); 3127 3128 const CPUKind Kind = getCPUKind(CPU); 3129 3130 // Enable X87 for all X86 processors but Lakemont. 3131 if (Kind != CK_Lakemont) 3132 setFeatureEnabledImpl(Features, "x87", true); 3133 3134 switch (Kind) { 3135 case CK_Generic: 3136 case CK_i386: 3137 case CK_i486: 3138 case CK_i586: 3139 case CK_Pentium: 3140 case CK_i686: 3141 case CK_PentiumPro: 3142 case CK_Lakemont: 3143 break; 3144 case CK_PentiumMMX: 3145 case CK_Pentium2: 3146 case CK_K6: 3147 case CK_WinChipC6: 3148 setFeatureEnabledImpl(Features, "mmx", true); 3149 break; 3150 case CK_Pentium3: 3151 case CK_Pentium3M: 3152 case CK_C3_2: 3153 setFeatureEnabledImpl(Features, "sse", true); 3154 setFeatureEnabledImpl(Features, "fxsr", true); 3155 break; 3156 case CK_PentiumM: 3157 case CK_Pentium4: 3158 case CK_Pentium4M: 3159 case CK_x86_64: 3160 setFeatureEnabledImpl(Features, "sse2", true); 3161 setFeatureEnabledImpl(Features, "fxsr", true); 3162 break; 3163 case CK_Yonah: 3164 case CK_Prescott: 3165 case CK_Nocona: 3166 setFeatureEnabledImpl(Features, "sse3", true); 3167 setFeatureEnabledImpl(Features, "fxsr", true); 3168 setFeatureEnabledImpl(Features, "cx16", true); 3169 break; 3170 case CK_Core2: 3171 case CK_Bonnell: 3172 setFeatureEnabledImpl(Features, "ssse3", true); 3173 setFeatureEnabledImpl(Features, "fxsr", true); 3174 setFeatureEnabledImpl(Features, "cx16", true); 3175 break; 3176 case CK_Penryn: 3177 setFeatureEnabledImpl(Features, "sse4.1", true); 3178 setFeatureEnabledImpl(Features, "fxsr", true); 3179 setFeatureEnabledImpl(Features, "cx16", true); 3180 break; 3181 case CK_Cannonlake: 3182 setFeatureEnabledImpl(Features, "avx512ifma", true); 3183 setFeatureEnabledImpl(Features, "avx512vbmi", true); 3184 setFeatureEnabledImpl(Features, "sha", true); 3185 LLVM_FALLTHROUGH; 3186 case CK_SkylakeServer: 3187 setFeatureEnabledImpl(Features, "avx512f", true); 3188 setFeatureEnabledImpl(Features, "avx512cd", true); 3189 setFeatureEnabledImpl(Features, "avx512dq", true); 3190 setFeatureEnabledImpl(Features, "avx512bw", true); 3191 setFeatureEnabledImpl(Features, "avx512vl", true); 3192 setFeatureEnabledImpl(Features, "pku", true); 3193 setFeatureEnabledImpl(Features, "clwb", true); 3194 LLVM_FALLTHROUGH; 3195 case CK_SkylakeClient: 3196 setFeatureEnabledImpl(Features, "xsavec", true); 3197 setFeatureEnabledImpl(Features, "xsaves", true); 3198 setFeatureEnabledImpl(Features, "mpx", true); 3199 setFeatureEnabledImpl(Features, "sgx", true); 3200 setFeatureEnabledImpl(Features, "clflushopt", true); 3201 setFeatureEnabledImpl(Features, "rtm", true); 3202 LLVM_FALLTHROUGH; 3203 case CK_Broadwell: 3204 setFeatureEnabledImpl(Features, "rdseed", true); 3205 setFeatureEnabledImpl(Features, "adx", true); 3206 LLVM_FALLTHROUGH; 3207 case CK_Haswell: 3208 setFeatureEnabledImpl(Features, "avx2", true); 3209 setFeatureEnabledImpl(Features, "lzcnt", true); 3210 setFeatureEnabledImpl(Features, "bmi", true); 3211 setFeatureEnabledImpl(Features, "bmi2", true); 3212 setFeatureEnabledImpl(Features, "fma", true); 3213 setFeatureEnabledImpl(Features, "movbe", true); 3214 LLVM_FALLTHROUGH; 3215 case CK_IvyBridge: 3216 setFeatureEnabledImpl(Features, "rdrnd", true); 3217 setFeatureEnabledImpl(Features, "f16c", true); 3218 setFeatureEnabledImpl(Features, "fsgsbase", true); 3219 LLVM_FALLTHROUGH; 3220 case CK_SandyBridge: 3221 setFeatureEnabledImpl(Features, "avx", true); 3222 setFeatureEnabledImpl(Features, "xsave", true); 3223 setFeatureEnabledImpl(Features, "xsaveopt", true); 3224 LLVM_FALLTHROUGH; 3225 case CK_Westmere: 3226 case CK_Silvermont: 3227 setFeatureEnabledImpl(Features, "aes", true); 3228 setFeatureEnabledImpl(Features, "pclmul", true); 3229 LLVM_FALLTHROUGH; 3230 case CK_Nehalem: 3231 setFeatureEnabledImpl(Features, "sse4.2", true); 3232 setFeatureEnabledImpl(Features, "fxsr", true); 3233 setFeatureEnabledImpl(Features, "cx16", true); 3234 break; 3235 case CK_KNL: 3236 setFeatureEnabledImpl(Features, "avx512f", true); 3237 setFeatureEnabledImpl(Features, "avx512cd", true); 3238 setFeatureEnabledImpl(Features, "avx512er", true); 3239 setFeatureEnabledImpl(Features, "avx512pf", true); 3240 setFeatureEnabledImpl(Features, "prefetchwt1", true); 3241 setFeatureEnabledImpl(Features, "fxsr", true); 3242 setFeatureEnabledImpl(Features, "rdseed", true); 3243 setFeatureEnabledImpl(Features, "adx", true); 3244 setFeatureEnabledImpl(Features, "lzcnt", true); 3245 setFeatureEnabledImpl(Features, "bmi", true); 3246 setFeatureEnabledImpl(Features, "bmi2", true); 3247 setFeatureEnabledImpl(Features, "rtm", true); 3248 setFeatureEnabledImpl(Features, "fma", true); 3249 setFeatureEnabledImpl(Features, "rdrnd", true); 3250 setFeatureEnabledImpl(Features, "f16c", true); 3251 setFeatureEnabledImpl(Features, "fsgsbase", true); 3252 setFeatureEnabledImpl(Features, "aes", true); 3253 setFeatureEnabledImpl(Features, "pclmul", true); 3254 setFeatureEnabledImpl(Features, "cx16", true); 3255 setFeatureEnabledImpl(Features, "xsaveopt", true); 3256 setFeatureEnabledImpl(Features, "xsave", true); 3257 setFeatureEnabledImpl(Features, "movbe", true); 3258 break; 3259 case CK_K6_2: 3260 case CK_K6_3: 3261 case CK_WinChip2: 3262 case CK_C3: 3263 setFeatureEnabledImpl(Features, "3dnow", true); 3264 break; 3265 case CK_Athlon: 3266 case CK_AthlonThunderbird: 3267 case CK_Geode: 3268 setFeatureEnabledImpl(Features, "3dnowa", true); 3269 break; 3270 case CK_Athlon4: 3271 case CK_AthlonXP: 3272 case CK_AthlonMP: 3273 setFeatureEnabledImpl(Features, "sse", true); 3274 setFeatureEnabledImpl(Features, "3dnowa", true); 3275 setFeatureEnabledImpl(Features, "fxsr", true); 3276 break; 3277 case CK_K8: 3278 case CK_Opteron: 3279 case CK_Athlon64: 3280 case CK_AthlonFX: 3281 setFeatureEnabledImpl(Features, "sse2", true); 3282 setFeatureEnabledImpl(Features, "3dnowa", true); 3283 setFeatureEnabledImpl(Features, "fxsr", true); 3284 break; 3285 case CK_AMDFAM10: 3286 setFeatureEnabledImpl(Features, "sse4a", true); 3287 setFeatureEnabledImpl(Features, "lzcnt", true); 3288 setFeatureEnabledImpl(Features, "popcnt", true); 3289 LLVM_FALLTHROUGH; 3290 case CK_K8SSE3: 3291 case CK_OpteronSSE3: 3292 case CK_Athlon64SSE3: 3293 setFeatureEnabledImpl(Features, "sse3", true); 3294 setFeatureEnabledImpl(Features, "3dnowa", true); 3295 setFeatureEnabledImpl(Features, "fxsr", true); 3296 break; 3297 case CK_BTVER2: 3298 setFeatureEnabledImpl(Features, "avx", true); 3299 setFeatureEnabledImpl(Features, "aes", true); 3300 setFeatureEnabledImpl(Features, "pclmul", true); 3301 setFeatureEnabledImpl(Features, "bmi", true); 3302 setFeatureEnabledImpl(Features, "f16c", true); 3303 setFeatureEnabledImpl(Features, "xsaveopt", true); 3304 LLVM_FALLTHROUGH; 3305 case CK_BTVER1: 3306 setFeatureEnabledImpl(Features, "ssse3", true); 3307 setFeatureEnabledImpl(Features, "sse4a", true); 3308 setFeatureEnabledImpl(Features, "lzcnt", true); 3309 setFeatureEnabledImpl(Features, "popcnt", true); 3310 setFeatureEnabledImpl(Features, "prfchw", true); 3311 setFeatureEnabledImpl(Features, "cx16", true); 3312 setFeatureEnabledImpl(Features, "fxsr", true); 3313 break; 3314 case CK_ZNVER1: 3315 setFeatureEnabledImpl(Features, "adx", true); 3316 setFeatureEnabledImpl(Features, "aes", true); 3317 setFeatureEnabledImpl(Features, "avx2", true); 3318 setFeatureEnabledImpl(Features, "bmi", true); 3319 setFeatureEnabledImpl(Features, "bmi2", true); 3320 setFeatureEnabledImpl(Features, "clflushopt", true); 3321 setFeatureEnabledImpl(Features, "clzero", true); 3322 setFeatureEnabledImpl(Features, "cx16", true); 3323 setFeatureEnabledImpl(Features, "f16c", true); 3324 setFeatureEnabledImpl(Features, "fma", true); 3325 setFeatureEnabledImpl(Features, "fsgsbase", true); 3326 setFeatureEnabledImpl(Features, "fxsr", true); 3327 setFeatureEnabledImpl(Features, "lzcnt", true); 3328 setFeatureEnabledImpl(Features, "mwaitx", true); 3329 setFeatureEnabledImpl(Features, "movbe", true); 3330 setFeatureEnabledImpl(Features, "pclmul", true); 3331 setFeatureEnabledImpl(Features, "popcnt", true); 3332 setFeatureEnabledImpl(Features, "prfchw", true); 3333 setFeatureEnabledImpl(Features, "rdrnd", true); 3334 setFeatureEnabledImpl(Features, "rdseed", true); 3335 setFeatureEnabledImpl(Features, "sha", true); 3336 setFeatureEnabledImpl(Features, "sse4a", true); 3337 setFeatureEnabledImpl(Features, "xsave", true); 3338 setFeatureEnabledImpl(Features, "xsavec", true); 3339 setFeatureEnabledImpl(Features, "xsaveopt", true); 3340 setFeatureEnabledImpl(Features, "xsaves", true); 3341 break; 3342 case CK_BDVER4: 3343 setFeatureEnabledImpl(Features, "avx2", true); 3344 setFeatureEnabledImpl(Features, "bmi2", true); 3345 setFeatureEnabledImpl(Features, "mwaitx", true); 3346 LLVM_FALLTHROUGH; 3347 case CK_BDVER3: 3348 setFeatureEnabledImpl(Features, "fsgsbase", true); 3349 setFeatureEnabledImpl(Features, "xsaveopt", true); 3350 LLVM_FALLTHROUGH; 3351 case CK_BDVER2: 3352 setFeatureEnabledImpl(Features, "bmi", true); 3353 setFeatureEnabledImpl(Features, "fma", true); 3354 setFeatureEnabledImpl(Features, "f16c", true); 3355 setFeatureEnabledImpl(Features, "tbm", true); 3356 LLVM_FALLTHROUGH; 3357 case CK_BDVER1: 3358 // xop implies avx, sse4a and fma4. 3359 setFeatureEnabledImpl(Features, "xop", true); 3360 setFeatureEnabledImpl(Features, "lzcnt", true); 3361 setFeatureEnabledImpl(Features, "aes", true); 3362 setFeatureEnabledImpl(Features, "pclmul", true); 3363 setFeatureEnabledImpl(Features, "prfchw", true); 3364 setFeatureEnabledImpl(Features, "cx16", true); 3365 setFeatureEnabledImpl(Features, "fxsr", true); 3366 setFeatureEnabledImpl(Features, "xsave", true); 3367 break; 3368 } 3369 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3370 return false; 3371 3372 // Can't do this earlier because we need to be able to explicitly enable 3373 // or disable these features and the things that they depend upon. 3374 3375 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3376 auto I = Features.find("sse4.2"); 3377 if (I != Features.end() && I->getValue() && 3378 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3379 FeaturesVec.end()) 3380 Features["popcnt"] = true; 3381 3382 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3383 I = Features.find("3dnow"); 3384 if (I != Features.end() && I->getValue() && 3385 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3386 FeaturesVec.end()) 3387 Features["prfchw"] = true; 3388 3389 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3390 // then enable MMX. 3391 I = Features.find("sse"); 3392 if (I != Features.end() && I->getValue() && 3393 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3394 FeaturesVec.end()) 3395 Features["mmx"] = true; 3396 3397 return true; 3398 } 3399 3400 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3401 X86SSEEnum Level, bool Enabled) { 3402 if (Enabled) { 3403 switch (Level) { 3404 case AVX512F: 3405 Features["avx512f"] = true; 3406 case AVX2: 3407 Features["avx2"] = true; 3408 case AVX: 3409 Features["avx"] = true; 3410 Features["xsave"] = true; 3411 case SSE42: 3412 Features["sse4.2"] = true; 3413 case SSE41: 3414 Features["sse4.1"] = true; 3415 case SSSE3: 3416 Features["ssse3"] = true; 3417 case SSE3: 3418 Features["sse3"] = true; 3419 case SSE2: 3420 Features["sse2"] = true; 3421 case SSE1: 3422 Features["sse"] = true; 3423 case NoSSE: 3424 break; 3425 } 3426 return; 3427 } 3428 3429 switch (Level) { 3430 case NoSSE: 3431 case SSE1: 3432 Features["sse"] = false; 3433 case SSE2: 3434 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3435 Features["sha"] = false; 3436 case SSE3: 3437 Features["sse3"] = false; 3438 setXOPLevel(Features, NoXOP, false); 3439 case SSSE3: 3440 Features["ssse3"] = false; 3441 case SSE41: 3442 Features["sse4.1"] = false; 3443 case SSE42: 3444 Features["sse4.2"] = false; 3445 case AVX: 3446 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3447 Features["xsaveopt"] = false; 3448 setXOPLevel(Features, FMA4, false); 3449 case AVX2: 3450 Features["avx2"] = false; 3451 case AVX512F: 3452 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3453 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3454 Features["avx512vl"] = Features["avx512vbmi"] = 3455 Features["avx512ifma"] = false; 3456 } 3457 } 3458 3459 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3460 MMX3DNowEnum Level, bool Enabled) { 3461 if (Enabled) { 3462 switch (Level) { 3463 case AMD3DNowAthlon: 3464 Features["3dnowa"] = true; 3465 case AMD3DNow: 3466 Features["3dnow"] = true; 3467 case MMX: 3468 Features["mmx"] = true; 3469 case NoMMX3DNow: 3470 break; 3471 } 3472 return; 3473 } 3474 3475 switch (Level) { 3476 case NoMMX3DNow: 3477 case MMX: 3478 Features["mmx"] = false; 3479 case AMD3DNow: 3480 Features["3dnow"] = false; 3481 case AMD3DNowAthlon: 3482 Features["3dnowa"] = false; 3483 } 3484 } 3485 3486 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3487 bool Enabled) { 3488 if (Enabled) { 3489 switch (Level) { 3490 case XOP: 3491 Features["xop"] = true; 3492 case FMA4: 3493 Features["fma4"] = true; 3494 setSSELevel(Features, AVX, true); 3495 case SSE4A: 3496 Features["sse4a"] = true; 3497 setSSELevel(Features, SSE3, true); 3498 case NoXOP: 3499 break; 3500 } 3501 return; 3502 } 3503 3504 switch (Level) { 3505 case NoXOP: 3506 case SSE4A: 3507 Features["sse4a"] = false; 3508 case FMA4: 3509 Features["fma4"] = false; 3510 case XOP: 3511 Features["xop"] = false; 3512 } 3513 } 3514 3515 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3516 StringRef Name, bool Enabled) { 3517 // This is a bit of a hack to deal with the sse4 target feature when used 3518 // as part of the target attribute. We handle sse4 correctly everywhere 3519 // else. See below for more information on how we handle the sse4 options. 3520 if (Name != "sse4") 3521 Features[Name] = Enabled; 3522 3523 if (Name == "mmx") { 3524 setMMXLevel(Features, MMX, Enabled); 3525 } else if (Name == "sse") { 3526 setSSELevel(Features, SSE1, Enabled); 3527 } else if (Name == "sse2") { 3528 setSSELevel(Features, SSE2, Enabled); 3529 } else if (Name == "sse3") { 3530 setSSELevel(Features, SSE3, Enabled); 3531 } else if (Name == "ssse3") { 3532 setSSELevel(Features, SSSE3, Enabled); 3533 } else if (Name == "sse4.2") { 3534 setSSELevel(Features, SSE42, Enabled); 3535 } else if (Name == "sse4.1") { 3536 setSSELevel(Features, SSE41, Enabled); 3537 } else if (Name == "3dnow") { 3538 setMMXLevel(Features, AMD3DNow, Enabled); 3539 } else if (Name == "3dnowa") { 3540 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3541 } else if (Name == "aes") { 3542 if (Enabled) 3543 setSSELevel(Features, SSE2, Enabled); 3544 } else if (Name == "pclmul") { 3545 if (Enabled) 3546 setSSELevel(Features, SSE2, Enabled); 3547 } else if (Name == "avx") { 3548 setSSELevel(Features, AVX, Enabled); 3549 } else if (Name == "avx2") { 3550 setSSELevel(Features, AVX2, Enabled); 3551 } else if (Name == "avx512f") { 3552 setSSELevel(Features, AVX512F, Enabled); 3553 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3554 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3555 Name == "avx512vbmi" || Name == "avx512ifma") { 3556 if (Enabled) 3557 setSSELevel(Features, AVX512F, Enabled); 3558 // Enable BWI instruction if VBMI is being enabled. 3559 if (Name == "avx512vbmi" && Enabled) 3560 Features["avx512bw"] = true; 3561 // Also disable VBMI if BWI is being disabled. 3562 if (Name == "avx512bw" && !Enabled) 3563 Features["avx512vbmi"] = false; 3564 } else if (Name == "fma") { 3565 if (Enabled) 3566 setSSELevel(Features, AVX, Enabled); 3567 } else if (Name == "fma4") { 3568 setXOPLevel(Features, FMA4, Enabled); 3569 } else if (Name == "xop") { 3570 setXOPLevel(Features, XOP, Enabled); 3571 } else if (Name == "sse4a") { 3572 setXOPLevel(Features, SSE4A, Enabled); 3573 } else if (Name == "f16c") { 3574 if (Enabled) 3575 setSSELevel(Features, AVX, Enabled); 3576 } else if (Name == "sha") { 3577 if (Enabled) 3578 setSSELevel(Features, SSE2, Enabled); 3579 } else if (Name == "sse4") { 3580 // We can get here via the __target__ attribute since that's not controlled 3581 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3582 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3583 // disabled. 3584 if (Enabled) 3585 setSSELevel(Features, SSE42, Enabled); 3586 else 3587 setSSELevel(Features, SSE41, Enabled); 3588 } else if (Name == "xsave") { 3589 if (!Enabled) 3590 Features["xsaveopt"] = false; 3591 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3592 if (Enabled) 3593 Features["xsave"] = true; 3594 } 3595 } 3596 3597 /// handleTargetFeatures - Perform initialization based on the user 3598 /// configured set of features. 3599 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3600 DiagnosticsEngine &Diags) { 3601 for (const auto &Feature : Features) { 3602 if (Feature[0] != '+') 3603 continue; 3604 3605 if (Feature == "+aes") { 3606 HasAES = true; 3607 } else if (Feature == "+pclmul") { 3608 HasPCLMUL = true; 3609 } else if (Feature == "+lzcnt") { 3610 HasLZCNT = true; 3611 } else if (Feature == "+rdrnd") { 3612 HasRDRND = true; 3613 } else if (Feature == "+fsgsbase") { 3614 HasFSGSBASE = true; 3615 } else if (Feature == "+bmi") { 3616 HasBMI = true; 3617 } else if (Feature == "+bmi2") { 3618 HasBMI2 = true; 3619 } else if (Feature == "+popcnt") { 3620 HasPOPCNT = true; 3621 } else if (Feature == "+rtm") { 3622 HasRTM = true; 3623 } else if (Feature == "+prfchw") { 3624 HasPRFCHW = true; 3625 } else if (Feature == "+rdseed") { 3626 HasRDSEED = true; 3627 } else if (Feature == "+adx") { 3628 HasADX = true; 3629 } else if (Feature == "+tbm") { 3630 HasTBM = true; 3631 } else if (Feature == "+fma") { 3632 HasFMA = true; 3633 } else if (Feature == "+f16c") { 3634 HasF16C = true; 3635 } else if (Feature == "+avx512cd") { 3636 HasAVX512CD = true; 3637 } else if (Feature == "+avx512er") { 3638 HasAVX512ER = true; 3639 } else if (Feature == "+avx512pf") { 3640 HasAVX512PF = true; 3641 } else if (Feature == "+avx512dq") { 3642 HasAVX512DQ = true; 3643 } else if (Feature == "+avx512bw") { 3644 HasAVX512BW = true; 3645 } else if (Feature == "+avx512vl") { 3646 HasAVX512VL = true; 3647 } else if (Feature == "+avx512vbmi") { 3648 HasAVX512VBMI = true; 3649 } else if (Feature == "+avx512ifma") { 3650 HasAVX512IFMA = true; 3651 } else if (Feature == "+sha") { 3652 HasSHA = true; 3653 } else if (Feature == "+mpx") { 3654 HasMPX = true; 3655 } else if (Feature == "+movbe") { 3656 HasMOVBE = true; 3657 } else if (Feature == "+sgx") { 3658 HasSGX = true; 3659 } else if (Feature == "+cx16") { 3660 HasCX16 = true; 3661 } else if (Feature == "+fxsr") { 3662 HasFXSR = true; 3663 } else if (Feature == "+xsave") { 3664 HasXSAVE = true; 3665 } else if (Feature == "+xsaveopt") { 3666 HasXSAVEOPT = true; 3667 } else if (Feature == "+xsavec") { 3668 HasXSAVEC = true; 3669 } else if (Feature == "+xsaves") { 3670 HasXSAVES = true; 3671 } else if (Feature == "+mwaitx") { 3672 HasMWAITX = true; 3673 } else if (Feature == "+pku") { 3674 HasPKU = true; 3675 } else if (Feature == "+clflushopt") { 3676 HasCLFLUSHOPT = true; 3677 } else if (Feature == "+clwb") { 3678 HasCLWB = true; 3679 } else if (Feature == "+prefetchwt1") { 3680 HasPREFETCHWT1 = true; 3681 } else if (Feature == "+clzero") { 3682 HasCLZERO = true; 3683 } 3684 3685 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3686 .Case("+avx512f", AVX512F) 3687 .Case("+avx2", AVX2) 3688 .Case("+avx", AVX) 3689 .Case("+sse4.2", SSE42) 3690 .Case("+sse4.1", SSE41) 3691 .Case("+ssse3", SSSE3) 3692 .Case("+sse3", SSE3) 3693 .Case("+sse2", SSE2) 3694 .Case("+sse", SSE1) 3695 .Default(NoSSE); 3696 SSELevel = std::max(SSELevel, Level); 3697 3698 MMX3DNowEnum ThreeDNowLevel = 3699 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3700 .Case("+3dnowa", AMD3DNowAthlon) 3701 .Case("+3dnow", AMD3DNow) 3702 .Case("+mmx", MMX) 3703 .Default(NoMMX3DNow); 3704 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3705 3706 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3707 .Case("+xop", XOP) 3708 .Case("+fma4", FMA4) 3709 .Case("+sse4a", SSE4A) 3710 .Default(NoXOP); 3711 XOPLevel = std::max(XOPLevel, XLevel); 3712 } 3713 3714 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3715 // matches the selected sse level. 3716 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3717 (FPMath == FP_387 && SSELevel >= SSE1)) { 3718 Diags.Report(diag::err_target_unsupported_fpmath) << 3719 (FPMath == FP_SSE ? "sse" : "387"); 3720 return false; 3721 } 3722 3723 SimdDefaultAlign = 3724 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3725 return true; 3726 } 3727 3728 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3729 /// definitions for this particular subtarget. 3730 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3731 MacroBuilder &Builder) const { 3732 // Target identification. 3733 if (getTriple().getArch() == llvm::Triple::x86_64) { 3734 Builder.defineMacro("__amd64__"); 3735 Builder.defineMacro("__amd64"); 3736 Builder.defineMacro("__x86_64"); 3737 Builder.defineMacro("__x86_64__"); 3738 if (getTriple().getArchName() == "x86_64h") { 3739 Builder.defineMacro("__x86_64h"); 3740 Builder.defineMacro("__x86_64h__"); 3741 } 3742 } else { 3743 DefineStd(Builder, "i386", Opts); 3744 } 3745 3746 // Subtarget options. 3747 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3748 // truly should be based on -mtune options. 3749 switch (CPU) { 3750 case CK_Generic: 3751 break; 3752 case CK_i386: 3753 // The rest are coming from the i386 define above. 3754 Builder.defineMacro("__tune_i386__"); 3755 break; 3756 case CK_i486: 3757 case CK_WinChipC6: 3758 case CK_WinChip2: 3759 case CK_C3: 3760 defineCPUMacros(Builder, "i486"); 3761 break; 3762 case CK_PentiumMMX: 3763 Builder.defineMacro("__pentium_mmx__"); 3764 Builder.defineMacro("__tune_pentium_mmx__"); 3765 // Fallthrough 3766 case CK_i586: 3767 case CK_Pentium: 3768 defineCPUMacros(Builder, "i586"); 3769 defineCPUMacros(Builder, "pentium"); 3770 break; 3771 case CK_Pentium3: 3772 case CK_Pentium3M: 3773 case CK_PentiumM: 3774 Builder.defineMacro("__tune_pentium3__"); 3775 // Fallthrough 3776 case CK_Pentium2: 3777 case CK_C3_2: 3778 Builder.defineMacro("__tune_pentium2__"); 3779 // Fallthrough 3780 case CK_PentiumPro: 3781 Builder.defineMacro("__tune_i686__"); 3782 Builder.defineMacro("__tune_pentiumpro__"); 3783 // Fallthrough 3784 case CK_i686: 3785 Builder.defineMacro("__i686"); 3786 Builder.defineMacro("__i686__"); 3787 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3788 Builder.defineMacro("__pentiumpro"); 3789 Builder.defineMacro("__pentiumpro__"); 3790 break; 3791 case CK_Pentium4: 3792 case CK_Pentium4M: 3793 defineCPUMacros(Builder, "pentium4"); 3794 break; 3795 case CK_Yonah: 3796 case CK_Prescott: 3797 case CK_Nocona: 3798 defineCPUMacros(Builder, "nocona"); 3799 break; 3800 case CK_Core2: 3801 case CK_Penryn: 3802 defineCPUMacros(Builder, "core2"); 3803 break; 3804 case CK_Bonnell: 3805 defineCPUMacros(Builder, "atom"); 3806 break; 3807 case CK_Silvermont: 3808 defineCPUMacros(Builder, "slm"); 3809 break; 3810 case CK_Nehalem: 3811 case CK_Westmere: 3812 case CK_SandyBridge: 3813 case CK_IvyBridge: 3814 case CK_Haswell: 3815 case CK_Broadwell: 3816 case CK_SkylakeClient: 3817 // FIXME: Historically, we defined this legacy name, it would be nice to 3818 // remove it at some point. We've never exposed fine-grained names for 3819 // recent primary x86 CPUs, and we should keep it that way. 3820 defineCPUMacros(Builder, "corei7"); 3821 break; 3822 case CK_SkylakeServer: 3823 defineCPUMacros(Builder, "skx"); 3824 break; 3825 case CK_Cannonlake: 3826 break; 3827 case CK_KNL: 3828 defineCPUMacros(Builder, "knl"); 3829 break; 3830 case CK_Lakemont: 3831 Builder.defineMacro("__tune_lakemont__"); 3832 break; 3833 case CK_K6_2: 3834 Builder.defineMacro("__k6_2__"); 3835 Builder.defineMacro("__tune_k6_2__"); 3836 // Fallthrough 3837 case CK_K6_3: 3838 if (CPU != CK_K6_2) { // In case of fallthrough 3839 // FIXME: GCC may be enabling these in cases where some other k6 3840 // architecture is specified but -m3dnow is explicitly provided. The 3841 // exact semantics need to be determined and emulated here. 3842 Builder.defineMacro("__k6_3__"); 3843 Builder.defineMacro("__tune_k6_3__"); 3844 } 3845 // Fallthrough 3846 case CK_K6: 3847 defineCPUMacros(Builder, "k6"); 3848 break; 3849 case CK_Athlon: 3850 case CK_AthlonThunderbird: 3851 case CK_Athlon4: 3852 case CK_AthlonXP: 3853 case CK_AthlonMP: 3854 defineCPUMacros(Builder, "athlon"); 3855 if (SSELevel != NoSSE) { 3856 Builder.defineMacro("__athlon_sse__"); 3857 Builder.defineMacro("__tune_athlon_sse__"); 3858 } 3859 break; 3860 case CK_K8: 3861 case CK_K8SSE3: 3862 case CK_x86_64: 3863 case CK_Opteron: 3864 case CK_OpteronSSE3: 3865 case CK_Athlon64: 3866 case CK_Athlon64SSE3: 3867 case CK_AthlonFX: 3868 defineCPUMacros(Builder, "k8"); 3869 break; 3870 case CK_AMDFAM10: 3871 defineCPUMacros(Builder, "amdfam10"); 3872 break; 3873 case CK_BTVER1: 3874 defineCPUMacros(Builder, "btver1"); 3875 break; 3876 case CK_BTVER2: 3877 defineCPUMacros(Builder, "btver2"); 3878 break; 3879 case CK_BDVER1: 3880 defineCPUMacros(Builder, "bdver1"); 3881 break; 3882 case CK_BDVER2: 3883 defineCPUMacros(Builder, "bdver2"); 3884 break; 3885 case CK_BDVER3: 3886 defineCPUMacros(Builder, "bdver3"); 3887 break; 3888 case CK_BDVER4: 3889 defineCPUMacros(Builder, "bdver4"); 3890 break; 3891 case CK_ZNVER1: 3892 defineCPUMacros(Builder, "znver1"); 3893 break; 3894 case CK_Geode: 3895 defineCPUMacros(Builder, "geode"); 3896 break; 3897 } 3898 3899 // Target properties. 3900 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3901 3902 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3903 // functions in glibc header files that use FP Stack inline asm which the 3904 // backend can't deal with (PR879). 3905 Builder.defineMacro("__NO_MATH_INLINES"); 3906 3907 if (HasAES) 3908 Builder.defineMacro("__AES__"); 3909 3910 if (HasPCLMUL) 3911 Builder.defineMacro("__PCLMUL__"); 3912 3913 if (HasLZCNT) 3914 Builder.defineMacro("__LZCNT__"); 3915 3916 if (HasRDRND) 3917 Builder.defineMacro("__RDRND__"); 3918 3919 if (HasFSGSBASE) 3920 Builder.defineMacro("__FSGSBASE__"); 3921 3922 if (HasBMI) 3923 Builder.defineMacro("__BMI__"); 3924 3925 if (HasBMI2) 3926 Builder.defineMacro("__BMI2__"); 3927 3928 if (HasPOPCNT) 3929 Builder.defineMacro("__POPCNT__"); 3930 3931 if (HasRTM) 3932 Builder.defineMacro("__RTM__"); 3933 3934 if (HasPRFCHW) 3935 Builder.defineMacro("__PRFCHW__"); 3936 3937 if (HasRDSEED) 3938 Builder.defineMacro("__RDSEED__"); 3939 3940 if (HasADX) 3941 Builder.defineMacro("__ADX__"); 3942 3943 if (HasTBM) 3944 Builder.defineMacro("__TBM__"); 3945 3946 if (HasMWAITX) 3947 Builder.defineMacro("__MWAITX__"); 3948 3949 switch (XOPLevel) { 3950 case XOP: 3951 Builder.defineMacro("__XOP__"); 3952 case FMA4: 3953 Builder.defineMacro("__FMA4__"); 3954 case SSE4A: 3955 Builder.defineMacro("__SSE4A__"); 3956 case NoXOP: 3957 break; 3958 } 3959 3960 if (HasFMA) 3961 Builder.defineMacro("__FMA__"); 3962 3963 if (HasF16C) 3964 Builder.defineMacro("__F16C__"); 3965 3966 if (HasAVX512CD) 3967 Builder.defineMacro("__AVX512CD__"); 3968 if (HasAVX512ER) 3969 Builder.defineMacro("__AVX512ER__"); 3970 if (HasAVX512PF) 3971 Builder.defineMacro("__AVX512PF__"); 3972 if (HasAVX512DQ) 3973 Builder.defineMacro("__AVX512DQ__"); 3974 if (HasAVX512BW) 3975 Builder.defineMacro("__AVX512BW__"); 3976 if (HasAVX512VL) 3977 Builder.defineMacro("__AVX512VL__"); 3978 if (HasAVX512VBMI) 3979 Builder.defineMacro("__AVX512VBMI__"); 3980 if (HasAVX512IFMA) 3981 Builder.defineMacro("__AVX512IFMA__"); 3982 3983 if (HasSHA) 3984 Builder.defineMacro("__SHA__"); 3985 3986 if (HasFXSR) 3987 Builder.defineMacro("__FXSR__"); 3988 if (HasXSAVE) 3989 Builder.defineMacro("__XSAVE__"); 3990 if (HasXSAVEOPT) 3991 Builder.defineMacro("__XSAVEOPT__"); 3992 if (HasXSAVEC) 3993 Builder.defineMacro("__XSAVEC__"); 3994 if (HasXSAVES) 3995 Builder.defineMacro("__XSAVES__"); 3996 if (HasPKU) 3997 Builder.defineMacro("__PKU__"); 3998 if (HasCX16) 3999 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 4000 if (HasCLFLUSHOPT) 4001 Builder.defineMacro("__CLFLUSHOPT__"); 4002 if (HasCLWB) 4003 Builder.defineMacro("__CLWB__"); 4004 if (HasMPX) 4005 Builder.defineMacro("__MPX__"); 4006 if (HasSGX) 4007 Builder.defineMacro("__SGX__"); 4008 if (HasPREFETCHWT1) 4009 Builder.defineMacro("__PREFETCHWT1__"); 4010 if (HasCLZERO) 4011 Builder.defineMacro("__CLZERO__"); 4012 4013 // Each case falls through to the previous one here. 4014 switch (SSELevel) { 4015 case AVX512F: 4016 Builder.defineMacro("__AVX512F__"); 4017 case AVX2: 4018 Builder.defineMacro("__AVX2__"); 4019 case AVX: 4020 Builder.defineMacro("__AVX__"); 4021 case SSE42: 4022 Builder.defineMacro("__SSE4_2__"); 4023 case SSE41: 4024 Builder.defineMacro("__SSE4_1__"); 4025 case SSSE3: 4026 Builder.defineMacro("__SSSE3__"); 4027 case SSE3: 4028 Builder.defineMacro("__SSE3__"); 4029 case SSE2: 4030 Builder.defineMacro("__SSE2__"); 4031 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 4032 case SSE1: 4033 Builder.defineMacro("__SSE__"); 4034 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 4035 case NoSSE: 4036 break; 4037 } 4038 4039 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 4040 switch (SSELevel) { 4041 case AVX512F: 4042 case AVX2: 4043 case AVX: 4044 case SSE42: 4045 case SSE41: 4046 case SSSE3: 4047 case SSE3: 4048 case SSE2: 4049 Builder.defineMacro("_M_IX86_FP", Twine(2)); 4050 break; 4051 case SSE1: 4052 Builder.defineMacro("_M_IX86_FP", Twine(1)); 4053 break; 4054 default: 4055 Builder.defineMacro("_M_IX86_FP", Twine(0)); 4056 } 4057 } 4058 4059 // Each case falls through to the previous one here. 4060 switch (MMX3DNowLevel) { 4061 case AMD3DNowAthlon: 4062 Builder.defineMacro("__3dNOW_A__"); 4063 case AMD3DNow: 4064 Builder.defineMacro("__3dNOW__"); 4065 case MMX: 4066 Builder.defineMacro("__MMX__"); 4067 case NoMMX3DNow: 4068 break; 4069 } 4070 4071 if (CPU >= CK_i486) { 4072 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4073 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4074 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4075 } 4076 if (CPU >= CK_i586) 4077 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4078 } 4079 4080 bool X86TargetInfo::hasFeature(StringRef Feature) const { 4081 return llvm::StringSwitch<bool>(Feature) 4082 .Case("aes", HasAES) 4083 .Case("avx", SSELevel >= AVX) 4084 .Case("avx2", SSELevel >= AVX2) 4085 .Case("avx512f", SSELevel >= AVX512F) 4086 .Case("avx512cd", HasAVX512CD) 4087 .Case("avx512er", HasAVX512ER) 4088 .Case("avx512pf", HasAVX512PF) 4089 .Case("avx512dq", HasAVX512DQ) 4090 .Case("avx512bw", HasAVX512BW) 4091 .Case("avx512vl", HasAVX512VL) 4092 .Case("avx512vbmi", HasAVX512VBMI) 4093 .Case("avx512ifma", HasAVX512IFMA) 4094 .Case("bmi", HasBMI) 4095 .Case("bmi2", HasBMI2) 4096 .Case("clflushopt", HasCLFLUSHOPT) 4097 .Case("clwb", HasCLWB) 4098 .Case("clzero", HasCLZERO) 4099 .Case("cx16", HasCX16) 4100 .Case("f16c", HasF16C) 4101 .Case("fma", HasFMA) 4102 .Case("fma4", XOPLevel >= FMA4) 4103 .Case("fsgsbase", HasFSGSBASE) 4104 .Case("fxsr", HasFXSR) 4105 .Case("lzcnt", HasLZCNT) 4106 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 4107 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 4108 .Case("mmx", MMX3DNowLevel >= MMX) 4109 .Case("movbe", HasMOVBE) 4110 .Case("mpx", HasMPX) 4111 .Case("pclmul", HasPCLMUL) 4112 .Case("pku", HasPKU) 4113 .Case("popcnt", HasPOPCNT) 4114 .Case("prefetchwt1", HasPREFETCHWT1) 4115 .Case("prfchw", HasPRFCHW) 4116 .Case("rdrnd", HasRDRND) 4117 .Case("rdseed", HasRDSEED) 4118 .Case("rtm", HasRTM) 4119 .Case("sgx", HasSGX) 4120 .Case("sha", HasSHA) 4121 .Case("sse", SSELevel >= SSE1) 4122 .Case("sse2", SSELevel >= SSE2) 4123 .Case("sse3", SSELevel >= SSE3) 4124 .Case("ssse3", SSELevel >= SSSE3) 4125 .Case("sse4.1", SSELevel >= SSE41) 4126 .Case("sse4.2", SSELevel >= SSE42) 4127 .Case("sse4a", XOPLevel >= SSE4A) 4128 .Case("tbm", HasTBM) 4129 .Case("x86", true) 4130 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 4131 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 4132 .Case("xop", XOPLevel >= XOP) 4133 .Case("xsave", HasXSAVE) 4134 .Case("xsavec", HasXSAVEC) 4135 .Case("xsaves", HasXSAVES) 4136 .Case("xsaveopt", HasXSAVEOPT) 4137 .Default(false); 4138 } 4139 4140 // We can't use a generic validation scheme for the features accepted here 4141 // versus subtarget features accepted in the target attribute because the 4142 // bitfield structure that's initialized in the runtime only supports the 4143 // below currently rather than the full range of subtarget features. (See 4144 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 4145 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 4146 return llvm::StringSwitch<bool>(FeatureStr) 4147 .Case("cmov", true) 4148 .Case("mmx", true) 4149 .Case("popcnt", true) 4150 .Case("sse", true) 4151 .Case("sse2", true) 4152 .Case("sse3", true) 4153 .Case("ssse3", true) 4154 .Case("sse4.1", true) 4155 .Case("sse4.2", true) 4156 .Case("avx", true) 4157 .Case("avx2", true) 4158 .Case("sse4a", true) 4159 .Case("fma4", true) 4160 .Case("xop", true) 4161 .Case("fma", true) 4162 .Case("avx512f", true) 4163 .Case("bmi", true) 4164 .Case("bmi2", true) 4165 .Case("aes", true) 4166 .Case("pclmul", true) 4167 .Case("avx512vl", true) 4168 .Case("avx512bw", true) 4169 .Case("avx512dq", true) 4170 .Case("avx512cd", true) 4171 .Case("avx512er", true) 4172 .Case("avx512pf", true) 4173 .Case("avx512vbmi", true) 4174 .Case("avx512ifma", true) 4175 .Default(false); 4176 } 4177 4178 bool 4179 X86TargetInfo::validateAsmConstraint(const char *&Name, 4180 TargetInfo::ConstraintInfo &Info) const { 4181 switch (*Name) { 4182 default: return false; 4183 // Constant constraints. 4184 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 4185 // instructions. 4186 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 4187 // x86_64 instructions. 4188 case 's': 4189 Info.setRequiresImmediate(); 4190 return true; 4191 case 'I': 4192 Info.setRequiresImmediate(0, 31); 4193 return true; 4194 case 'J': 4195 Info.setRequiresImmediate(0, 63); 4196 return true; 4197 case 'K': 4198 Info.setRequiresImmediate(-128, 127); 4199 return true; 4200 case 'L': 4201 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 4202 return true; 4203 case 'M': 4204 Info.setRequiresImmediate(0, 3); 4205 return true; 4206 case 'N': 4207 Info.setRequiresImmediate(0, 255); 4208 return true; 4209 case 'O': 4210 Info.setRequiresImmediate(0, 127); 4211 return true; 4212 // Register constraints. 4213 case 'Y': // 'Y' is the first character for several 2-character constraints. 4214 // Shift the pointer to the second character of the constraint. 4215 Name++; 4216 switch (*Name) { 4217 default: 4218 return false; 4219 case '0': // First SSE register. 4220 case 't': // Any SSE register, when SSE2 is enabled. 4221 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 4222 case 'm': // Any MMX register, when inter-unit moves enabled. 4223 case 'k': // AVX512 arch mask registers: k1-k7. 4224 Info.setAllowsRegister(); 4225 return true; 4226 } 4227 case 'f': // Any x87 floating point stack register. 4228 // Constraint 'f' cannot be used for output operands. 4229 if (Info.ConstraintStr[0] == '=') 4230 return false; 4231 Info.setAllowsRegister(); 4232 return true; 4233 case 'a': // eax. 4234 case 'b': // ebx. 4235 case 'c': // ecx. 4236 case 'd': // edx. 4237 case 'S': // esi. 4238 case 'D': // edi. 4239 case 'A': // edx:eax. 4240 case 't': // Top of floating point stack. 4241 case 'u': // Second from top of floating point stack. 4242 case 'q': // Any register accessible as [r]l: a, b, c, and d. 4243 case 'y': // Any MMX register. 4244 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 4245 case 'x': // Any SSE register. 4246 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 4247 // for intermideate k reg operations). 4248 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 4249 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 4250 case 'l': // "Index" registers: any general register that can be used as an 4251 // index in a base+index memory access. 4252 Info.setAllowsRegister(); 4253 return true; 4254 // Floating point constant constraints. 4255 case 'C': // SSE floating point constant. 4256 case 'G': // x87 floating point constant. 4257 return true; 4258 } 4259 } 4260 4261 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 4262 unsigned Size) const { 4263 // Strip off constraint modifiers. 4264 while (Constraint[0] == '=' || 4265 Constraint[0] == '+' || 4266 Constraint[0] == '&') 4267 Constraint = Constraint.substr(1); 4268 4269 return validateOperandSize(Constraint, Size); 4270 } 4271 4272 bool X86TargetInfo::validateInputSize(StringRef Constraint, 4273 unsigned Size) const { 4274 return validateOperandSize(Constraint, Size); 4275 } 4276 4277 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 4278 unsigned Size) const { 4279 switch (Constraint[0]) { 4280 default: break; 4281 case 'k': 4282 // Registers k0-k7 (AVX512) size limit is 64 bit. 4283 case 'y': 4284 return Size <= 64; 4285 case 'f': 4286 case 't': 4287 case 'u': 4288 return Size <= 128; 4289 case 'v': 4290 case 'x': 4291 if (SSELevel >= AVX512F) 4292 // 512-bit zmm registers can be used if target supports AVX512F. 4293 return Size <= 512U; 4294 else if (SSELevel >= AVX) 4295 // 256-bit ymm registers can be used if target supports AVX. 4296 return Size <= 256U; 4297 return Size <= 128U; 4298 case 'Y': 4299 // 'Y' is the first character for several 2-character constraints. 4300 switch (Constraint[1]) { 4301 default: break; 4302 case 'm': 4303 // 'Ym' is synonymous with 'y'. 4304 case 'k': 4305 return Size <= 64; 4306 case 'i': 4307 case 't': 4308 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4309 if (SSELevel >= AVX512F) 4310 return Size <= 512U; 4311 else if (SSELevel >= AVX) 4312 return Size <= 256U; 4313 return SSELevel >= SSE2 && Size <= 128U; 4314 } 4315 4316 } 4317 4318 return true; 4319 } 4320 4321 std::string 4322 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4323 switch (*Constraint) { 4324 case 'a': return std::string("{ax}"); 4325 case 'b': return std::string("{bx}"); 4326 case 'c': return std::string("{cx}"); 4327 case 'd': return std::string("{dx}"); 4328 case 'S': return std::string("{si}"); 4329 case 'D': return std::string("{di}"); 4330 case 'p': // address 4331 return std::string("im"); 4332 case 't': // top of floating point stack. 4333 return std::string("{st}"); 4334 case 'u': // second from top of floating point stack. 4335 return std::string("{st(1)}"); // second from top of floating point stack. 4336 case 'Y': 4337 switch (Constraint[1]) { 4338 default: 4339 // Break from inner switch and fall through (copy single char), 4340 // continue parsing after copying the current constraint into 4341 // the return string. 4342 break; 4343 case 'k': 4344 // "^" hints llvm that this is a 2 letter constraint. 4345 // "Constraint++" is used to promote the string iterator 4346 // to the next constraint. 4347 return std::string("^") + std::string(Constraint++, 2); 4348 } 4349 LLVM_FALLTHROUGH; 4350 default: 4351 return std::string(1, *Constraint); 4352 } 4353 } 4354 4355 // X86-32 generic target 4356 class X86_32TargetInfo : public X86TargetInfo { 4357 public: 4358 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4359 : X86TargetInfo(Triple, Opts) { 4360 DoubleAlign = LongLongAlign = 32; 4361 LongDoubleWidth = 96; 4362 LongDoubleAlign = 32; 4363 SuitableAlign = 128; 4364 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4365 SizeType = UnsignedInt; 4366 PtrDiffType = SignedInt; 4367 IntPtrType = SignedInt; 4368 RegParmMax = 3; 4369 4370 // Use fpret for all types. 4371 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4372 (1 << TargetInfo::Double) | 4373 (1 << TargetInfo::LongDouble)); 4374 4375 // x86-32 has atomics up to 8 bytes 4376 // FIXME: Check that we actually have cmpxchg8b before setting 4377 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4378 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4379 } 4380 BuiltinVaListKind getBuiltinVaListKind() const override { 4381 return TargetInfo::CharPtrBuiltinVaList; 4382 } 4383 4384 int getEHDataRegisterNumber(unsigned RegNo) const override { 4385 if (RegNo == 0) return 0; 4386 if (RegNo == 1) return 2; 4387 return -1; 4388 } 4389 bool validateOperandSize(StringRef Constraint, 4390 unsigned Size) const override { 4391 switch (Constraint[0]) { 4392 default: break; 4393 case 'R': 4394 case 'q': 4395 case 'Q': 4396 case 'a': 4397 case 'b': 4398 case 'c': 4399 case 'd': 4400 case 'S': 4401 case 'D': 4402 return Size <= 32; 4403 case 'A': 4404 return Size <= 64; 4405 } 4406 4407 return X86TargetInfo::validateOperandSize(Constraint, Size); 4408 } 4409 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4410 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 4411 Builtin::FirstTSBuiltin + 1); 4412 } 4413 }; 4414 4415 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4416 public: 4417 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4418 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4419 4420 unsigned getFloatEvalMethod() const override { 4421 unsigned Major, Minor, Micro; 4422 getTriple().getOSVersion(Major, Minor, Micro); 4423 // New NetBSD uses the default rounding mode. 4424 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4425 return X86_32TargetInfo::getFloatEvalMethod(); 4426 // NetBSD before 6.99.26 defaults to "double" rounding. 4427 return 1; 4428 } 4429 }; 4430 4431 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4432 public: 4433 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4434 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4435 SizeType = UnsignedLong; 4436 IntPtrType = SignedLong; 4437 PtrDiffType = SignedLong; 4438 } 4439 }; 4440 4441 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4442 public: 4443 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4444 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4445 SizeType = UnsignedLong; 4446 IntPtrType = SignedLong; 4447 PtrDiffType = SignedLong; 4448 } 4449 }; 4450 4451 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4452 public: 4453 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4454 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4455 LongDoubleWidth = 128; 4456 LongDoubleAlign = 128; 4457 SuitableAlign = 128; 4458 MaxVectorAlign = 256; 4459 // The watchOS simulator uses the builtin bool type for Objective-C. 4460 llvm::Triple T = llvm::Triple(Triple); 4461 if (T.isWatchOS()) 4462 UseSignedCharForObjCBool = false; 4463 SizeType = UnsignedLong; 4464 IntPtrType = SignedLong; 4465 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4466 HasAlignMac68kSupport = true; 4467 } 4468 4469 bool handleTargetFeatures(std::vector<std::string> &Features, 4470 DiagnosticsEngine &Diags) override { 4471 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4472 Diags)) 4473 return false; 4474 // We now know the features we have: we can decide how to align vectors. 4475 MaxVectorAlign = 4476 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4477 return true; 4478 } 4479 }; 4480 4481 // x86-32 Windows target 4482 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4483 public: 4484 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4485 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4486 WCharType = UnsignedShort; 4487 DoubleAlign = LongLongAlign = 64; 4488 bool IsWinCOFF = 4489 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4490 resetDataLayout(IsWinCOFF 4491 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4492 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4493 } 4494 void getTargetDefines(const LangOptions &Opts, 4495 MacroBuilder &Builder) const override { 4496 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4497 } 4498 }; 4499 4500 // x86-32 Windows Visual Studio target 4501 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4502 public: 4503 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4504 const TargetOptions &Opts) 4505 : WindowsX86_32TargetInfo(Triple, Opts) { 4506 LongDoubleWidth = LongDoubleAlign = 64; 4507 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4508 } 4509 void getTargetDefines(const LangOptions &Opts, 4510 MacroBuilder &Builder) const override { 4511 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4512 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4513 // The value of the following reflects processor type. 4514 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4515 // We lost the original triple, so we use the default. 4516 Builder.defineMacro("_M_IX86", "600"); 4517 } 4518 }; 4519 4520 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4521 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4522 // supports __declspec natively under -fms-extensions, but we define a no-op 4523 // __declspec macro anyway for pre-processor compatibility. 4524 if (Opts.MicrosoftExt) 4525 Builder.defineMacro("__declspec", "__declspec"); 4526 else 4527 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4528 4529 if (!Opts.MicrosoftExt) { 4530 // Provide macros for all the calling convention keywords. Provide both 4531 // single and double underscore prefixed variants. These are available on 4532 // x64 as well as x86, even though they have no effect. 4533 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4534 for (const char *CC : CCs) { 4535 std::string GCCSpelling = "__attribute__((__"; 4536 GCCSpelling += CC; 4537 GCCSpelling += "__))"; 4538 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4539 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4540 } 4541 } 4542 } 4543 4544 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4545 Builder.defineMacro("__MSVCRT__"); 4546 Builder.defineMacro("__MINGW32__"); 4547 addCygMingDefines(Opts, Builder); 4548 } 4549 4550 // x86-32 MinGW target 4551 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4552 public: 4553 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4554 : WindowsX86_32TargetInfo(Triple, Opts) {} 4555 void getTargetDefines(const LangOptions &Opts, 4556 MacroBuilder &Builder) const override { 4557 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4558 DefineStd(Builder, "WIN32", Opts); 4559 DefineStd(Builder, "WINNT", Opts); 4560 Builder.defineMacro("_X86_"); 4561 addMinGWDefines(Opts, Builder); 4562 } 4563 }; 4564 4565 // x86-32 Cygwin target 4566 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4567 public: 4568 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4569 : X86_32TargetInfo(Triple, Opts) { 4570 WCharType = UnsignedShort; 4571 DoubleAlign = LongLongAlign = 64; 4572 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4573 } 4574 void getTargetDefines(const LangOptions &Opts, 4575 MacroBuilder &Builder) const override { 4576 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4577 Builder.defineMacro("_X86_"); 4578 Builder.defineMacro("__CYGWIN__"); 4579 Builder.defineMacro("__CYGWIN32__"); 4580 addCygMingDefines(Opts, Builder); 4581 DefineStd(Builder, "unix", Opts); 4582 if (Opts.CPlusPlus) 4583 Builder.defineMacro("_GNU_SOURCE"); 4584 } 4585 }; 4586 4587 // x86-32 Haiku target 4588 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4589 public: 4590 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4591 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4592 } 4593 void getTargetDefines(const LangOptions &Opts, 4594 MacroBuilder &Builder) const override { 4595 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4596 Builder.defineMacro("__INTEL__"); 4597 } 4598 }; 4599 4600 // X86-32 MCU target 4601 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4602 public: 4603 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4604 : X86_32TargetInfo(Triple, Opts) { 4605 LongDoubleWidth = 64; 4606 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4607 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4608 WIntType = UnsignedInt; 4609 } 4610 4611 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4612 // On MCU we support only C calling convention. 4613 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4614 } 4615 4616 void getTargetDefines(const LangOptions &Opts, 4617 MacroBuilder &Builder) const override { 4618 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4619 Builder.defineMacro("__iamcu"); 4620 Builder.defineMacro("__iamcu__"); 4621 } 4622 4623 bool allowsLargerPreferedTypeAlignment() const override { 4624 return false; 4625 } 4626 }; 4627 4628 // RTEMS Target 4629 template<typename Target> 4630 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4631 protected: 4632 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4633 MacroBuilder &Builder) const override { 4634 // RTEMS defines; list based off of gcc output 4635 4636 Builder.defineMacro("__rtems__"); 4637 Builder.defineMacro("__ELF__"); 4638 } 4639 4640 public: 4641 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4642 : OSTargetInfo<Target>(Triple, Opts) { 4643 switch (Triple.getArch()) { 4644 default: 4645 case llvm::Triple::x86: 4646 // this->MCountName = ".mcount"; 4647 break; 4648 case llvm::Triple::mips: 4649 case llvm::Triple::mipsel: 4650 case llvm::Triple::ppc: 4651 case llvm::Triple::ppc64: 4652 case llvm::Triple::ppc64le: 4653 // this->MCountName = "_mcount"; 4654 break; 4655 case llvm::Triple::arm: 4656 // this->MCountName = "__mcount"; 4657 break; 4658 } 4659 } 4660 }; 4661 4662 // x86-32 RTEMS target 4663 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4664 public: 4665 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4666 : X86_32TargetInfo(Triple, Opts) { 4667 SizeType = UnsignedLong; 4668 IntPtrType = SignedLong; 4669 PtrDiffType = SignedLong; 4670 } 4671 void getTargetDefines(const LangOptions &Opts, 4672 MacroBuilder &Builder) const override { 4673 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4674 Builder.defineMacro("__INTEL__"); 4675 Builder.defineMacro("__rtems__"); 4676 } 4677 }; 4678 4679 // x86-64 generic target 4680 class X86_64TargetInfo : public X86TargetInfo { 4681 public: 4682 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4683 : X86TargetInfo(Triple, Opts) { 4684 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4685 bool IsWinCOFF = 4686 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4687 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4688 LongDoubleWidth = 128; 4689 LongDoubleAlign = 128; 4690 LargeArrayMinWidth = 128; 4691 LargeArrayAlign = 128; 4692 SuitableAlign = 128; 4693 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4694 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4695 IntPtrType = IsX32 ? SignedInt : SignedLong; 4696 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4697 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4698 RegParmMax = 6; 4699 4700 // Pointers are 32-bit in x32. 4701 resetDataLayout(IsX32 4702 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4703 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4704 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4705 4706 // Use fpret only for long double. 4707 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4708 4709 // Use fp2ret for _Complex long double. 4710 ComplexLongDoubleUsesFP2Ret = true; 4711 4712 // Make __builtin_ms_va_list available. 4713 HasBuiltinMSVaList = true; 4714 4715 // x86-64 has atomics up to 16 bytes. 4716 MaxAtomicPromoteWidth = 128; 4717 MaxAtomicInlineWidth = 128; 4718 } 4719 BuiltinVaListKind getBuiltinVaListKind() const override { 4720 return TargetInfo::X86_64ABIBuiltinVaList; 4721 } 4722 4723 int getEHDataRegisterNumber(unsigned RegNo) const override { 4724 if (RegNo == 0) return 0; 4725 if (RegNo == 1) return 1; 4726 return -1; 4727 } 4728 4729 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4730 switch (CC) { 4731 case CC_C: 4732 case CC_Swift: 4733 case CC_X86VectorCall: 4734 case CC_IntelOclBicc: 4735 case CC_X86_64Win64: 4736 case CC_PreserveMost: 4737 case CC_PreserveAll: 4738 case CC_X86RegCall: 4739 return CCCR_OK; 4740 default: 4741 return CCCR_Warning; 4742 } 4743 } 4744 4745 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4746 return CC_C; 4747 } 4748 4749 // for x32 we need it here explicitly 4750 bool hasInt128Type() const override { return true; } 4751 unsigned getUnwindWordWidth() const override { return 64; } 4752 unsigned getRegisterWidth() const override { return 64; } 4753 4754 bool validateGlobalRegisterVariable(StringRef RegName, 4755 unsigned RegSize, 4756 bool &HasSizeMismatch) const override { 4757 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4758 // handle. 4759 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4760 // Check that the register size is 64-bit. 4761 HasSizeMismatch = RegSize != 64; 4762 return true; 4763 } 4764 4765 // Check if the register is a 32-bit register the backend can handle. 4766 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4767 HasSizeMismatch); 4768 } 4769 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4770 return llvm::makeArrayRef(BuiltinInfoX86, 4771 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 4772 } 4773 }; 4774 4775 // x86-64 Windows target 4776 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4777 public: 4778 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4779 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4780 WCharType = UnsignedShort; 4781 LongWidth = LongAlign = 32; 4782 DoubleAlign = LongLongAlign = 64; 4783 IntMaxType = SignedLongLong; 4784 Int64Type = SignedLongLong; 4785 SizeType = UnsignedLongLong; 4786 PtrDiffType = SignedLongLong; 4787 IntPtrType = SignedLongLong; 4788 } 4789 4790 void getTargetDefines(const LangOptions &Opts, 4791 MacroBuilder &Builder) const override { 4792 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4793 Builder.defineMacro("_WIN64"); 4794 } 4795 4796 BuiltinVaListKind getBuiltinVaListKind() const override { 4797 return TargetInfo::CharPtrBuiltinVaList; 4798 } 4799 4800 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4801 switch (CC) { 4802 case CC_X86StdCall: 4803 case CC_X86ThisCall: 4804 case CC_X86FastCall: 4805 return CCCR_Ignore; 4806 case CC_C: 4807 case CC_X86VectorCall: 4808 case CC_IntelOclBicc: 4809 case CC_X86_64SysV: 4810 case CC_Swift: 4811 case CC_X86RegCall: 4812 return CCCR_OK; 4813 default: 4814 return CCCR_Warning; 4815 } 4816 } 4817 }; 4818 4819 // x86-64 Windows Visual Studio target 4820 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4821 public: 4822 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4823 const TargetOptions &Opts) 4824 : WindowsX86_64TargetInfo(Triple, Opts) { 4825 LongDoubleWidth = LongDoubleAlign = 64; 4826 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4827 } 4828 void getTargetDefines(const LangOptions &Opts, 4829 MacroBuilder &Builder) const override { 4830 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4831 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4832 Builder.defineMacro("_M_X64", "100"); 4833 Builder.defineMacro("_M_AMD64", "100"); 4834 } 4835 }; 4836 4837 // x86-64 MinGW target 4838 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4839 public: 4840 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4841 : WindowsX86_64TargetInfo(Triple, Opts) { 4842 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4843 // with x86 FP ops. Weird. 4844 LongDoubleWidth = LongDoubleAlign = 128; 4845 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 4846 } 4847 4848 void getTargetDefines(const LangOptions &Opts, 4849 MacroBuilder &Builder) const override { 4850 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4851 DefineStd(Builder, "WIN64", Opts); 4852 Builder.defineMacro("__MINGW64__"); 4853 addMinGWDefines(Opts, Builder); 4854 4855 // GCC defines this macro when it is using __gxx_personality_seh0. 4856 if (!Opts.SjLjExceptions) 4857 Builder.defineMacro("__SEH__"); 4858 } 4859 }; 4860 4861 // x86-64 Cygwin target 4862 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4863 public: 4864 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4865 : X86_64TargetInfo(Triple, Opts) { 4866 TLSSupported = false; 4867 WCharType = UnsignedShort; 4868 } 4869 void getTargetDefines(const LangOptions &Opts, 4870 MacroBuilder &Builder) const override { 4871 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4872 Builder.defineMacro("__x86_64__"); 4873 Builder.defineMacro("__CYGWIN__"); 4874 Builder.defineMacro("__CYGWIN64__"); 4875 addCygMingDefines(Opts, Builder); 4876 DefineStd(Builder, "unix", Opts); 4877 if (Opts.CPlusPlus) 4878 Builder.defineMacro("_GNU_SOURCE"); 4879 4880 // GCC defines this macro when it is using __gxx_personality_seh0. 4881 if (!Opts.SjLjExceptions) 4882 Builder.defineMacro("__SEH__"); 4883 } 4884 }; 4885 4886 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4887 public: 4888 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4889 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4890 Int64Type = SignedLongLong; 4891 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4892 llvm::Triple T = llvm::Triple(Triple); 4893 if (T.isiOS()) 4894 UseSignedCharForObjCBool = false; 4895 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4896 } 4897 4898 bool handleTargetFeatures(std::vector<std::string> &Features, 4899 DiagnosticsEngine &Diags) override { 4900 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4901 Diags)) 4902 return false; 4903 // We now know the features we have: we can decide how to align vectors. 4904 MaxVectorAlign = 4905 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4906 return true; 4907 } 4908 }; 4909 4910 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4911 public: 4912 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4913 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4914 IntMaxType = SignedLongLong; 4915 Int64Type = SignedLongLong; 4916 } 4917 }; 4918 4919 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4920 public: 4921 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4922 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4923 IntMaxType = SignedLongLong; 4924 Int64Type = SignedLongLong; 4925 } 4926 }; 4927 4928 class ARMTargetInfo : public TargetInfo { 4929 // Possible FPU choices. 4930 enum FPUMode { 4931 VFP2FPU = (1 << 0), 4932 VFP3FPU = (1 << 1), 4933 VFP4FPU = (1 << 2), 4934 NeonFPU = (1 << 3), 4935 FPARMV8 = (1 << 4) 4936 }; 4937 4938 // Possible HWDiv features. 4939 enum HWDivMode { 4940 HWDivThumb = (1 << 0), 4941 HWDivARM = (1 << 1) 4942 }; 4943 4944 static bool FPUModeIsVFP(FPUMode Mode) { 4945 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4946 } 4947 4948 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4949 static const char * const GCCRegNames[]; 4950 4951 std::string ABI, CPU; 4952 4953 StringRef CPUProfile; 4954 StringRef CPUAttr; 4955 4956 enum { 4957 FP_Default, 4958 FP_VFP, 4959 FP_Neon 4960 } FPMath; 4961 4962 unsigned ArchISA; 4963 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4964 unsigned ArchProfile; 4965 unsigned ArchVersion; 4966 4967 unsigned FPU : 5; 4968 4969 unsigned IsAAPCS : 1; 4970 unsigned HWDiv : 2; 4971 4972 // Initialized via features. 4973 unsigned SoftFloat : 1; 4974 unsigned SoftFloatABI : 1; 4975 4976 unsigned CRC : 1; 4977 unsigned Crypto : 1; 4978 unsigned DSP : 1; 4979 unsigned Unaligned : 1; 4980 4981 enum { 4982 LDREX_B = (1 << 0), /// byte (8-bit) 4983 LDREX_H = (1 << 1), /// half (16-bit) 4984 LDREX_W = (1 << 2), /// word (32-bit) 4985 LDREX_D = (1 << 3), /// double (64-bit) 4986 }; 4987 4988 uint32_t LDREX; 4989 4990 // ACLE 6.5.1 Hardware floating point 4991 enum { 4992 HW_FP_HP = (1 << 1), /// half (16-bit) 4993 HW_FP_SP = (1 << 2), /// single (32-bit) 4994 HW_FP_DP = (1 << 3), /// double (64-bit) 4995 }; 4996 uint32_t HW_FP; 4997 4998 static const Builtin::Info BuiltinInfo[]; 4999 5000 void setABIAAPCS() { 5001 IsAAPCS = true; 5002 5003 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5004 const llvm::Triple &T = getTriple(); 5005 5006 // size_t is unsigned long on MachO-derived environments, NetBSD, 5007 // OpenBSD and Bitrig. 5008 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 5009 T.getOS() == llvm::Triple::OpenBSD || 5010 T.getOS() == llvm::Triple::Bitrig) 5011 SizeType = UnsignedLong; 5012 else 5013 SizeType = UnsignedInt; 5014 5015 switch (T.getOS()) { 5016 case llvm::Triple::NetBSD: 5017 case llvm::Triple::OpenBSD: 5018 WCharType = SignedInt; 5019 break; 5020 case llvm::Triple::Win32: 5021 WCharType = UnsignedShort; 5022 break; 5023 case llvm::Triple::Linux: 5024 default: 5025 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 5026 WCharType = UnsignedInt; 5027 break; 5028 } 5029 5030 UseBitFieldTypeAlignment = true; 5031 5032 ZeroLengthBitfieldBoundary = 0; 5033 5034 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 5035 // so set preferred for small types to 32. 5036 if (T.isOSBinFormatMachO()) { 5037 resetDataLayout(BigEndian 5038 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5039 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5040 } else if (T.isOSWindows()) { 5041 assert(!BigEndian && "Windows on ARM does not support big endian"); 5042 resetDataLayout("e" 5043 "-m:w" 5044 "-p:32:32" 5045 "-i64:64" 5046 "-v128:64:128" 5047 "-a:0:32" 5048 "-n32" 5049 "-S64"); 5050 } else if (T.isOSNaCl()) { 5051 assert(!BigEndian && "NaCl on ARM does not support big endian"); 5052 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 5053 } else { 5054 resetDataLayout(BigEndian 5055 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5056 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5057 } 5058 5059 // FIXME: Enumerated types are variable width in straight AAPCS. 5060 } 5061 5062 void setABIAPCS(bool IsAAPCS16) { 5063 const llvm::Triple &T = getTriple(); 5064 5065 IsAAPCS = false; 5066 5067 if (IsAAPCS16) 5068 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5069 else 5070 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 5071 5072 // size_t is unsigned int on FreeBSD. 5073 if (T.getOS() == llvm::Triple::FreeBSD) 5074 SizeType = UnsignedInt; 5075 else 5076 SizeType = UnsignedLong; 5077 5078 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 5079 WCharType = SignedInt; 5080 5081 // Do not respect the alignment of bit-field types when laying out 5082 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 5083 UseBitFieldTypeAlignment = false; 5084 5085 /// gcc forces the alignment to 4 bytes, regardless of the type of the 5086 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 5087 /// gcc. 5088 ZeroLengthBitfieldBoundary = 32; 5089 5090 if (T.isOSBinFormatMachO() && IsAAPCS16) { 5091 assert(!BigEndian && "AAPCS16 does not support big-endian"); 5092 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 5093 } else if (T.isOSBinFormatMachO()) 5094 resetDataLayout( 5095 BigEndian 5096 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5097 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5098 else 5099 resetDataLayout( 5100 BigEndian 5101 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5102 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5103 5104 // FIXME: Override "preferred align" for double and long long. 5105 } 5106 5107 void setArchInfo() { 5108 StringRef ArchName = getTriple().getArchName(); 5109 5110 ArchISA = llvm::ARM::parseArchISA(ArchName); 5111 CPU = llvm::ARM::getDefaultCPU(ArchName); 5112 unsigned AK = llvm::ARM::parseArch(ArchName); 5113 if (AK != llvm::ARM::AK_INVALID) 5114 ArchKind = AK; 5115 setArchInfo(ArchKind); 5116 } 5117 5118 void setArchInfo(unsigned Kind) { 5119 StringRef SubArch; 5120 5121 // cache TargetParser info 5122 ArchKind = Kind; 5123 SubArch = llvm::ARM::getSubArch(ArchKind); 5124 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 5125 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 5126 5127 // cache CPU related strings 5128 CPUAttr = getCPUAttr(); 5129 CPUProfile = getCPUProfile(); 5130 } 5131 5132 void setAtomic() { 5133 // when triple does not specify a sub arch, 5134 // then we are not using inline atomics 5135 bool ShouldUseInlineAtomic = 5136 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 5137 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 5138 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 5139 if (ArchProfile == llvm::ARM::PK_M) { 5140 MaxAtomicPromoteWidth = 32; 5141 if (ShouldUseInlineAtomic) 5142 MaxAtomicInlineWidth = 32; 5143 } 5144 else { 5145 MaxAtomicPromoteWidth = 64; 5146 if (ShouldUseInlineAtomic) 5147 MaxAtomicInlineWidth = 64; 5148 } 5149 } 5150 5151 bool isThumb() const { 5152 return (ArchISA == llvm::ARM::IK_THUMB); 5153 } 5154 5155 bool supportsThumb() const { 5156 return CPUAttr.count('T') || ArchVersion >= 6; 5157 } 5158 5159 bool supportsThumb2() const { 5160 return CPUAttr.equals("6T2") || 5161 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 5162 } 5163 5164 StringRef getCPUAttr() const { 5165 // For most sub-arches, the build attribute CPU name is enough. 5166 // For Cortex variants, it's slightly different. 5167 switch(ArchKind) { 5168 default: 5169 return llvm::ARM::getCPUAttr(ArchKind); 5170 case llvm::ARM::AK_ARMV6M: 5171 return "6M"; 5172 case llvm::ARM::AK_ARMV7S: 5173 return "7S"; 5174 case llvm::ARM::AK_ARMV7A: 5175 return "7A"; 5176 case llvm::ARM::AK_ARMV7R: 5177 return "7R"; 5178 case llvm::ARM::AK_ARMV7M: 5179 return "7M"; 5180 case llvm::ARM::AK_ARMV7EM: 5181 return "7EM"; 5182 case llvm::ARM::AK_ARMV7VE: 5183 return "7VE"; 5184 case llvm::ARM::AK_ARMV8A: 5185 return "8A"; 5186 case llvm::ARM::AK_ARMV8_1A: 5187 return "8_1A"; 5188 case llvm::ARM::AK_ARMV8_2A: 5189 return "8_2A"; 5190 case llvm::ARM::AK_ARMV8MBaseline: 5191 return "8M_BASE"; 5192 case llvm::ARM::AK_ARMV8MMainline: 5193 return "8M_MAIN"; 5194 case llvm::ARM::AK_ARMV8R: 5195 return "8R"; 5196 } 5197 } 5198 5199 StringRef getCPUProfile() const { 5200 switch(ArchProfile) { 5201 case llvm::ARM::PK_A: 5202 return "A"; 5203 case llvm::ARM::PK_R: 5204 return "R"; 5205 case llvm::ARM::PK_M: 5206 return "M"; 5207 default: 5208 return ""; 5209 } 5210 } 5211 5212 public: 5213 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5214 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 5215 HW_FP(0) { 5216 5217 switch (getTriple().getOS()) { 5218 case llvm::Triple::NetBSD: 5219 case llvm::Triple::OpenBSD: 5220 PtrDiffType = SignedLong; 5221 break; 5222 default: 5223 PtrDiffType = SignedInt; 5224 break; 5225 } 5226 5227 // Cache arch related info. 5228 setArchInfo(); 5229 5230 // {} in inline assembly are neon specifiers, not assembly variant 5231 // specifiers. 5232 NoAsmVariants = true; 5233 5234 // FIXME: This duplicates code from the driver that sets the -target-abi 5235 // option - this code is used if -target-abi isn't passed and should 5236 // be unified in some way. 5237 if (Triple.isOSBinFormatMachO()) { 5238 // The backend is hardwired to assume AAPCS for M-class processors, ensure 5239 // the frontend matches that. 5240 if (Triple.getEnvironment() == llvm::Triple::EABI || 5241 Triple.getOS() == llvm::Triple::UnknownOS || 5242 ArchProfile == llvm::ARM::PK_M) { 5243 setABI("aapcs"); 5244 } else if (Triple.isWatchABI()) { 5245 setABI("aapcs16"); 5246 } else { 5247 setABI("apcs-gnu"); 5248 } 5249 } else if (Triple.isOSWindows()) { 5250 // FIXME: this is invalid for WindowsCE 5251 setABI("aapcs"); 5252 } else { 5253 // Select the default based on the platform. 5254 switch (Triple.getEnvironment()) { 5255 case llvm::Triple::Android: 5256 case llvm::Triple::GNUEABI: 5257 case llvm::Triple::GNUEABIHF: 5258 case llvm::Triple::MuslEABI: 5259 case llvm::Triple::MuslEABIHF: 5260 setABI("aapcs-linux"); 5261 break; 5262 case llvm::Triple::EABIHF: 5263 case llvm::Triple::EABI: 5264 setABI("aapcs"); 5265 break; 5266 case llvm::Triple::GNU: 5267 setABI("apcs-gnu"); 5268 break; 5269 default: 5270 if (Triple.getOS() == llvm::Triple::NetBSD) 5271 setABI("apcs-gnu"); 5272 else if (Triple.getOS() == llvm::Triple::OpenBSD) 5273 setABI("aapcs-linux"); 5274 else 5275 setABI("aapcs"); 5276 break; 5277 } 5278 } 5279 5280 // ARM targets default to using the ARM C++ ABI. 5281 TheCXXABI.set(TargetCXXABI::GenericARM); 5282 5283 // ARM has atomics up to 8 bytes 5284 setAtomic(); 5285 5286 // Do force alignment of members that follow zero length bitfields. If 5287 // the alignment of the zero-length bitfield is greater than the member 5288 // that follows it, `bar', `bar' will be aligned as the type of the 5289 // zero length bitfield. 5290 UseZeroLengthBitfieldAlignment = true; 5291 5292 if (Triple.getOS() == llvm::Triple::Linux || 5293 Triple.getOS() == llvm::Triple::UnknownOS) 5294 this->MCountName = 5295 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 5296 } 5297 5298 StringRef getABI() const override { return ABI; } 5299 5300 bool setABI(const std::string &Name) override { 5301 ABI = Name; 5302 5303 // The defaults (above) are for AAPCS, check if we need to change them. 5304 // 5305 // FIXME: We need support for -meabi... we could just mangle it into the 5306 // name. 5307 if (Name == "apcs-gnu" || Name == "aapcs16") { 5308 setABIAPCS(Name == "aapcs16"); 5309 return true; 5310 } 5311 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 5312 setABIAAPCS(); 5313 return true; 5314 } 5315 return false; 5316 } 5317 5318 // FIXME: This should be based on Arch attributes, not CPU names. 5319 bool 5320 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5321 StringRef CPU, 5322 const std::vector<std::string> &FeaturesVec) const override { 5323 5324 std::vector<StringRef> TargetFeatures; 5325 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 5326 5327 // get default FPU features 5328 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 5329 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 5330 5331 // get default Extension features 5332 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 5333 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 5334 5335 for (auto Feature : TargetFeatures) 5336 if (Feature[0] == '+') 5337 Features[Feature.drop_front(1)] = true; 5338 5339 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5340 } 5341 5342 bool handleTargetFeatures(std::vector<std::string> &Features, 5343 DiagnosticsEngine &Diags) override { 5344 FPU = 0; 5345 CRC = 0; 5346 Crypto = 0; 5347 DSP = 0; 5348 Unaligned = 1; 5349 SoftFloat = SoftFloatABI = false; 5350 HWDiv = 0; 5351 5352 // This does not diagnose illegal cases like having both 5353 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5354 uint32_t HW_FP_remove = 0; 5355 for (const auto &Feature : Features) { 5356 if (Feature == "+soft-float") { 5357 SoftFloat = true; 5358 } else if (Feature == "+soft-float-abi") { 5359 SoftFloatABI = true; 5360 } else if (Feature == "+vfp2") { 5361 FPU |= VFP2FPU; 5362 HW_FP |= HW_FP_SP | HW_FP_DP; 5363 } else if (Feature == "+vfp3") { 5364 FPU |= VFP3FPU; 5365 HW_FP |= HW_FP_SP | HW_FP_DP; 5366 } else if (Feature == "+vfp4") { 5367 FPU |= VFP4FPU; 5368 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5369 } else if (Feature == "+fp-armv8") { 5370 FPU |= FPARMV8; 5371 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5372 } else if (Feature == "+neon") { 5373 FPU |= NeonFPU; 5374 HW_FP |= HW_FP_SP | HW_FP_DP; 5375 } else if (Feature == "+hwdiv") { 5376 HWDiv |= HWDivThumb; 5377 } else if (Feature == "+hwdiv-arm") { 5378 HWDiv |= HWDivARM; 5379 } else if (Feature == "+crc") { 5380 CRC = 1; 5381 } else if (Feature == "+crypto") { 5382 Crypto = 1; 5383 } else if (Feature == "+dsp") { 5384 DSP = 1; 5385 } else if (Feature == "+fp-only-sp") { 5386 HW_FP_remove |= HW_FP_DP; 5387 } else if (Feature == "+strict-align") { 5388 Unaligned = 0; 5389 } else if (Feature == "+fp16") { 5390 HW_FP |= HW_FP_HP; 5391 } 5392 } 5393 HW_FP &= ~HW_FP_remove; 5394 5395 switch (ArchVersion) { 5396 case 6: 5397 if (ArchProfile == llvm::ARM::PK_M) 5398 LDREX = 0; 5399 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5400 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5401 else 5402 LDREX = LDREX_W; 5403 break; 5404 case 7: 5405 if (ArchProfile == llvm::ARM::PK_M) 5406 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5407 else 5408 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5409 break; 5410 case 8: 5411 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5412 } 5413 5414 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5415 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5416 return false; 5417 } 5418 5419 if (FPMath == FP_Neon) 5420 Features.push_back("+neonfp"); 5421 else if (FPMath == FP_VFP) 5422 Features.push_back("-neonfp"); 5423 5424 // Remove front-end specific options which the backend handles differently. 5425 auto Feature = 5426 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5427 if (Feature != Features.end()) 5428 Features.erase(Feature); 5429 5430 return true; 5431 } 5432 5433 bool hasFeature(StringRef Feature) const override { 5434 return llvm::StringSwitch<bool>(Feature) 5435 .Case("arm", true) 5436 .Case("aarch32", true) 5437 .Case("softfloat", SoftFloat) 5438 .Case("thumb", isThumb()) 5439 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5440 .Case("hwdiv", HWDiv & HWDivThumb) 5441 .Case("hwdiv-arm", HWDiv & HWDivARM) 5442 .Default(false); 5443 } 5444 5445 bool setCPU(const std::string &Name) override { 5446 if (Name != "generic") 5447 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5448 5449 if (ArchKind == llvm::ARM::AK_INVALID) 5450 return false; 5451 setAtomic(); 5452 CPU = Name; 5453 return true; 5454 } 5455 5456 bool setFPMath(StringRef Name) override; 5457 5458 void getTargetDefines(const LangOptions &Opts, 5459 MacroBuilder &Builder) const override { 5460 // Target identification. 5461 Builder.defineMacro("__arm"); 5462 Builder.defineMacro("__arm__"); 5463 // For bare-metal none-eabi. 5464 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5465 getTriple().getEnvironment() == llvm::Triple::EABI) 5466 Builder.defineMacro("__ELF__"); 5467 5468 // Target properties. 5469 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5470 5471 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5472 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5473 if (getTriple().isWatchABI()) 5474 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5475 5476 if (!CPUAttr.empty()) 5477 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5478 5479 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5480 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5481 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5482 5483 if (ArchVersion >= 8) { 5484 // ACLE 6.5.7 Crypto Extension 5485 if (Crypto) 5486 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5487 // ACLE 6.5.8 CRC32 Extension 5488 if (CRC) 5489 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5490 // ACLE 6.5.10 Numeric Maximum and Minimum 5491 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5492 // ACLE 6.5.9 Directed Rounding 5493 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5494 } 5495 5496 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5497 // is not defined for the M-profile. 5498 // NOTE that the default profile is assumed to be 'A' 5499 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5500 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5501 5502 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5503 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5504 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5505 // v7 and v8 architectures excluding v8-M Baseline. 5506 if (supportsThumb2()) 5507 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5508 else if (supportsThumb()) 5509 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5510 5511 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5512 // instruction set such as ARM or Thumb. 5513 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5514 5515 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5516 5517 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5518 if (!CPUProfile.empty()) 5519 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5520 5521 // ACLE 6.4.3 Unaligned access supported in hardware 5522 if (Unaligned) 5523 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5524 5525 // ACLE 6.4.4 LDREX/STREX 5526 if (LDREX) 5527 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5528 5529 // ACLE 6.4.5 CLZ 5530 if (ArchVersion == 5 || 5531 (ArchVersion == 6 && CPUProfile != "M") || 5532 ArchVersion > 6) 5533 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5534 5535 // ACLE 6.5.1 Hardware Floating Point 5536 if (HW_FP) 5537 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5538 5539 // ACLE predefines. 5540 Builder.defineMacro("__ARM_ACLE", "200"); 5541 5542 // FP16 support (we currently only support IEEE format). 5543 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5544 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5545 5546 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5547 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5548 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5549 5550 // Subtarget options. 5551 5552 // FIXME: It's more complicated than this and we don't really support 5553 // interworking. 5554 // Windows on ARM does not "support" interworking 5555 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5556 Builder.defineMacro("__THUMB_INTERWORK__"); 5557 5558 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5559 // Embedded targets on Darwin follow AAPCS, but not EABI. 5560 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5561 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5562 Builder.defineMacro("__ARM_EABI__"); 5563 Builder.defineMacro("__ARM_PCS", "1"); 5564 } 5565 5566 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5567 ABI == "aapcs16") 5568 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5569 5570 if (SoftFloat) 5571 Builder.defineMacro("__SOFTFP__"); 5572 5573 if (ArchKind == llvm::ARM::AK_XSCALE) 5574 Builder.defineMacro("__XSCALE__"); 5575 5576 if (isThumb()) { 5577 Builder.defineMacro("__THUMBEL__"); 5578 Builder.defineMacro("__thumb__"); 5579 if (supportsThumb2()) 5580 Builder.defineMacro("__thumb2__"); 5581 } 5582 5583 // ACLE 6.4.9 32-bit SIMD instructions 5584 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5585 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5586 5587 // ACLE 6.4.10 Hardware Integer Divide 5588 if (((HWDiv & HWDivThumb) && isThumb()) || 5589 ((HWDiv & HWDivARM) && !isThumb())) { 5590 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5591 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5592 } 5593 5594 // Note, this is always on in gcc, even though it doesn't make sense. 5595 Builder.defineMacro("__APCS_32__"); 5596 5597 if (FPUModeIsVFP((FPUMode) FPU)) { 5598 Builder.defineMacro("__VFP_FP__"); 5599 if (FPU & VFP2FPU) 5600 Builder.defineMacro("__ARM_VFPV2__"); 5601 if (FPU & VFP3FPU) 5602 Builder.defineMacro("__ARM_VFPV3__"); 5603 if (FPU & VFP4FPU) 5604 Builder.defineMacro("__ARM_VFPV4__"); 5605 if (FPU & FPARMV8) 5606 Builder.defineMacro("__ARM_FPV5__"); 5607 } 5608 5609 // This only gets set when Neon instructions are actually available, unlike 5610 // the VFP define, hence the soft float and arch check. This is subtly 5611 // different from gcc, we follow the intent which was that it should be set 5612 // when Neon instructions are actually available. 5613 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5614 Builder.defineMacro("__ARM_NEON", "1"); 5615 Builder.defineMacro("__ARM_NEON__"); 5616 // current AArch32 NEON implementations do not support double-precision 5617 // floating-point even when it is present in VFP. 5618 Builder.defineMacro("__ARM_NEON_FP", 5619 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5620 } 5621 5622 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5623 Opts.ShortWChar ? "2" : "4"); 5624 5625 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5626 Opts.ShortEnums ? "1" : "4"); 5627 5628 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5629 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5630 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5631 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5632 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5633 } 5634 5635 // ACLE 6.4.7 DSP instructions 5636 if (DSP) { 5637 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5638 } 5639 5640 // ACLE 6.4.8 Saturation instructions 5641 bool SAT = false; 5642 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5643 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5644 SAT = true; 5645 } 5646 5647 // ACLE 6.4.6 Q (saturation) flag 5648 if (DSP || SAT) 5649 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5650 5651 if (Opts.UnsafeFPMath) 5652 Builder.defineMacro("__ARM_FP_FAST", "1"); 5653 5654 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5655 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5656 } 5657 5658 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5659 return llvm::makeArrayRef(BuiltinInfo, 5660 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5661 } 5662 bool isCLZForZeroUndef() const override { return false; } 5663 BuiltinVaListKind getBuiltinVaListKind() const override { 5664 return IsAAPCS 5665 ? AAPCSABIBuiltinVaList 5666 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5667 : TargetInfo::VoidPtrBuiltinVaList); 5668 } 5669 ArrayRef<const char *> getGCCRegNames() const override; 5670 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5671 bool validateAsmConstraint(const char *&Name, 5672 TargetInfo::ConstraintInfo &Info) const override { 5673 switch (*Name) { 5674 default: break; 5675 case 'l': // r0-r7 5676 case 'h': // r8-r15 5677 case 't': // VFP Floating point register single precision 5678 case 'w': // VFP Floating point register double precision 5679 Info.setAllowsRegister(); 5680 return true; 5681 case 'I': 5682 case 'J': 5683 case 'K': 5684 case 'L': 5685 case 'M': 5686 // FIXME 5687 return true; 5688 case 'Q': // A memory address that is a single base register. 5689 Info.setAllowsMemory(); 5690 return true; 5691 case 'U': // a memory reference... 5692 switch (Name[1]) { 5693 case 'q': // ...ARMV4 ldrsb 5694 case 'v': // ...VFP load/store (reg+constant offset) 5695 case 'y': // ...iWMMXt load/store 5696 case 't': // address valid for load/store opaque types wider 5697 // than 128-bits 5698 case 'n': // valid address for Neon doubleword vector load/store 5699 case 'm': // valid address for Neon element and structure load/store 5700 case 's': // valid address for non-offset loads/stores of quad-word 5701 // values in four ARM registers 5702 Info.setAllowsMemory(); 5703 Name++; 5704 return true; 5705 } 5706 } 5707 return false; 5708 } 5709 std::string convertConstraint(const char *&Constraint) const override { 5710 std::string R; 5711 switch (*Constraint) { 5712 case 'U': // Two-character constraint; add "^" hint for later parsing. 5713 R = std::string("^") + std::string(Constraint, 2); 5714 Constraint++; 5715 break; 5716 case 'p': // 'p' should be translated to 'r' by default. 5717 R = std::string("r"); 5718 break; 5719 default: 5720 return std::string(1, *Constraint); 5721 } 5722 return R; 5723 } 5724 bool 5725 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5726 std::string &SuggestedModifier) const override { 5727 bool isOutput = (Constraint[0] == '='); 5728 bool isInOut = (Constraint[0] == '+'); 5729 5730 // Strip off constraint modifiers. 5731 while (Constraint[0] == '=' || 5732 Constraint[0] == '+' || 5733 Constraint[0] == '&') 5734 Constraint = Constraint.substr(1); 5735 5736 switch (Constraint[0]) { 5737 default: break; 5738 case 'r': { 5739 switch (Modifier) { 5740 default: 5741 return (isInOut || isOutput || Size <= 64); 5742 case 'q': 5743 // A register of size 32 cannot fit a vector type. 5744 return false; 5745 } 5746 } 5747 } 5748 5749 return true; 5750 } 5751 const char *getClobbers() const override { 5752 // FIXME: Is this really right? 5753 return ""; 5754 } 5755 5756 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5757 switch (CC) { 5758 case CC_AAPCS: 5759 case CC_AAPCS_VFP: 5760 case CC_Swift: 5761 return CCCR_OK; 5762 default: 5763 return CCCR_Warning; 5764 } 5765 } 5766 5767 int getEHDataRegisterNumber(unsigned RegNo) const override { 5768 if (RegNo == 0) return 0; 5769 if (RegNo == 1) return 1; 5770 return -1; 5771 } 5772 5773 bool hasSjLjLowering() const override { 5774 return true; 5775 } 5776 }; 5777 5778 bool ARMTargetInfo::setFPMath(StringRef Name) { 5779 if (Name == "neon") { 5780 FPMath = FP_Neon; 5781 return true; 5782 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5783 Name == "vfp4") { 5784 FPMath = FP_VFP; 5785 return true; 5786 } 5787 return false; 5788 } 5789 5790 const char * const ARMTargetInfo::GCCRegNames[] = { 5791 // Integer registers 5792 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5793 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5794 5795 // Float registers 5796 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5797 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5798 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5799 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5800 5801 // Double registers 5802 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5803 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5804 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5805 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5806 5807 // Quad registers 5808 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5809 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5810 }; 5811 5812 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5813 return llvm::makeArrayRef(GCCRegNames); 5814 } 5815 5816 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5817 { { "a1" }, "r0" }, 5818 { { "a2" }, "r1" }, 5819 { { "a3" }, "r2" }, 5820 { { "a4" }, "r3" }, 5821 { { "v1" }, "r4" }, 5822 { { "v2" }, "r5" }, 5823 { { "v3" }, "r6" }, 5824 { { "v4" }, "r7" }, 5825 { { "v5" }, "r8" }, 5826 { { "v6", "rfp" }, "r9" }, 5827 { { "sl" }, "r10" }, 5828 { { "fp" }, "r11" }, 5829 { { "ip" }, "r12" }, 5830 { { "r13" }, "sp" }, 5831 { { "r14" }, "lr" }, 5832 { { "r15" }, "pc" }, 5833 // The S, D and Q registers overlap, but aren't really aliases; we 5834 // don't want to substitute one of these for a different-sized one. 5835 }; 5836 5837 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5838 return llvm::makeArrayRef(GCCRegAliases); 5839 } 5840 5841 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5842 #define BUILTIN(ID, TYPE, ATTRS) \ 5843 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5844 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5845 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5846 #include "clang/Basic/BuiltinsNEON.def" 5847 5848 #define BUILTIN(ID, TYPE, ATTRS) \ 5849 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5850 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5851 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5852 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5853 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5854 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 5855 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 5856 #include "clang/Basic/BuiltinsARM.def" 5857 }; 5858 5859 class ARMleTargetInfo : public ARMTargetInfo { 5860 public: 5861 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5862 : ARMTargetInfo(Triple, Opts) {} 5863 void getTargetDefines(const LangOptions &Opts, 5864 MacroBuilder &Builder) const override { 5865 Builder.defineMacro("__ARMEL__"); 5866 ARMTargetInfo::getTargetDefines(Opts, Builder); 5867 } 5868 }; 5869 5870 class ARMbeTargetInfo : public ARMTargetInfo { 5871 public: 5872 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5873 : ARMTargetInfo(Triple, Opts) {} 5874 void getTargetDefines(const LangOptions &Opts, 5875 MacroBuilder &Builder) const override { 5876 Builder.defineMacro("__ARMEB__"); 5877 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5878 ARMTargetInfo::getTargetDefines(Opts, Builder); 5879 } 5880 }; 5881 5882 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5883 const llvm::Triple Triple; 5884 public: 5885 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5886 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5887 WCharType = UnsignedShort; 5888 SizeType = UnsignedInt; 5889 } 5890 void getVisualStudioDefines(const LangOptions &Opts, 5891 MacroBuilder &Builder) const { 5892 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5893 5894 // FIXME: this is invalid for WindowsCE 5895 Builder.defineMacro("_M_ARM_NT", "1"); 5896 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5897 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5898 5899 assert((Triple.getArch() == llvm::Triple::arm || 5900 Triple.getArch() == llvm::Triple::thumb) && 5901 "invalid architecture for Windows ARM target info"); 5902 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5903 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5904 5905 // TODO map the complete set of values 5906 // 31: VFPv3 40: VFPv4 5907 Builder.defineMacro("_M_ARM_FP", "31"); 5908 } 5909 BuiltinVaListKind getBuiltinVaListKind() const override { 5910 return TargetInfo::CharPtrBuiltinVaList; 5911 } 5912 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5913 switch (CC) { 5914 case CC_X86StdCall: 5915 case CC_X86ThisCall: 5916 case CC_X86FastCall: 5917 case CC_X86VectorCall: 5918 return CCCR_Ignore; 5919 case CC_C: 5920 return CCCR_OK; 5921 default: 5922 return CCCR_Warning; 5923 } 5924 } 5925 }; 5926 5927 // Windows ARM + Itanium C++ ABI Target 5928 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5929 public: 5930 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5931 const TargetOptions &Opts) 5932 : WindowsARMTargetInfo(Triple, Opts) { 5933 TheCXXABI.set(TargetCXXABI::GenericARM); 5934 } 5935 5936 void getTargetDefines(const LangOptions &Opts, 5937 MacroBuilder &Builder) const override { 5938 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5939 5940 if (Opts.MSVCCompat) 5941 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5942 } 5943 }; 5944 5945 // Windows ARM, MS (C++) ABI 5946 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5947 public: 5948 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5949 const TargetOptions &Opts) 5950 : WindowsARMTargetInfo(Triple, Opts) { 5951 TheCXXABI.set(TargetCXXABI::Microsoft); 5952 } 5953 5954 void getTargetDefines(const LangOptions &Opts, 5955 MacroBuilder &Builder) const override { 5956 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5957 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5958 } 5959 }; 5960 5961 // ARM MinGW target 5962 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5963 public: 5964 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5965 : WindowsARMTargetInfo(Triple, Opts) { 5966 TheCXXABI.set(TargetCXXABI::GenericARM); 5967 } 5968 5969 void getTargetDefines(const LangOptions &Opts, 5970 MacroBuilder &Builder) const override { 5971 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5972 DefineStd(Builder, "WIN32", Opts); 5973 DefineStd(Builder, "WINNT", Opts); 5974 Builder.defineMacro("_ARM_"); 5975 addMinGWDefines(Opts, Builder); 5976 } 5977 }; 5978 5979 // ARM Cygwin target 5980 class CygwinARMTargetInfo : public ARMleTargetInfo { 5981 public: 5982 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5983 : ARMleTargetInfo(Triple, Opts) { 5984 TLSSupported = false; 5985 WCharType = UnsignedShort; 5986 DoubleAlign = LongLongAlign = 64; 5987 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5988 } 5989 void getTargetDefines(const LangOptions &Opts, 5990 MacroBuilder &Builder) const override { 5991 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5992 Builder.defineMacro("_ARM_"); 5993 Builder.defineMacro("__CYGWIN__"); 5994 Builder.defineMacro("__CYGWIN32__"); 5995 DefineStd(Builder, "unix", Opts); 5996 if (Opts.CPlusPlus) 5997 Builder.defineMacro("_GNU_SOURCE"); 5998 } 5999 }; 6000 6001 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 6002 protected: 6003 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6004 MacroBuilder &Builder) const override { 6005 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6006 } 6007 6008 public: 6009 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6010 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 6011 HasAlignMac68kSupport = true; 6012 // iOS always has 64-bit atomic instructions. 6013 // FIXME: This should be based off of the target features in 6014 // ARMleTargetInfo. 6015 MaxAtomicInlineWidth = 64; 6016 6017 if (Triple.isWatchABI()) { 6018 // Darwin on iOS uses a variant of the ARM C++ ABI. 6019 TheCXXABI.set(TargetCXXABI::WatchOS); 6020 6021 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 6022 // size_t is long, it's a bit weird for it to be int. 6023 PtrDiffType = SignedLong; 6024 6025 // BOOL should be a real boolean on the new ABI 6026 UseSignedCharForObjCBool = false; 6027 } else 6028 TheCXXABI.set(TargetCXXABI::iOS); 6029 } 6030 }; 6031 6032 class AArch64TargetInfo : public TargetInfo { 6033 virtual void setDataLayout() = 0; 6034 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6035 static const char *const GCCRegNames[]; 6036 6037 enum FPUModeEnum { 6038 FPUMode, 6039 NeonMode 6040 }; 6041 6042 unsigned FPU; 6043 unsigned CRC; 6044 unsigned Crypto; 6045 unsigned Unaligned; 6046 unsigned V8_1A; 6047 6048 static const Builtin::Info BuiltinInfo[]; 6049 6050 std::string ABI; 6051 6052 public: 6053 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6054 : TargetInfo(Triple), ABI("aapcs") { 6055 if (getTriple().getOS() == llvm::Triple::NetBSD || 6056 getTriple().getOS() == llvm::Triple::OpenBSD) { 6057 WCharType = SignedInt; 6058 6059 // NetBSD apparently prefers consistency across ARM targets to consistency 6060 // across 64-bit targets. 6061 Int64Type = SignedLongLong; 6062 IntMaxType = SignedLongLong; 6063 } else { 6064 WCharType = UnsignedInt; 6065 Int64Type = SignedLong; 6066 IntMaxType = SignedLong; 6067 } 6068 6069 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6070 MaxVectorAlign = 128; 6071 MaxAtomicInlineWidth = 128; 6072 MaxAtomicPromoteWidth = 128; 6073 6074 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 6075 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 6076 6077 // {} in inline assembly are neon specifiers, not assembly variant 6078 // specifiers. 6079 NoAsmVariants = true; 6080 6081 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 6082 // contributes to the alignment of the containing aggregate in the same way 6083 // a plain (non bit-field) member of that type would, without exception for 6084 // zero-sized or anonymous bit-fields." 6085 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 6086 UseZeroLengthBitfieldAlignment = true; 6087 6088 // AArch64 targets default to using the ARM C++ ABI. 6089 TheCXXABI.set(TargetCXXABI::GenericAArch64); 6090 6091 if (Triple.getOS() == llvm::Triple::Linux) 6092 this->MCountName = "\01_mcount"; 6093 else if (Triple.getOS() == llvm::Triple::UnknownOS) 6094 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 6095 } 6096 6097 StringRef getABI() const override { return ABI; } 6098 bool setABI(const std::string &Name) override { 6099 if (Name != "aapcs" && Name != "darwinpcs") 6100 return false; 6101 6102 ABI = Name; 6103 return true; 6104 } 6105 6106 bool setCPU(const std::string &Name) override { 6107 return Name == "generic" || 6108 llvm::AArch64::parseCPUArch(Name) != 6109 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 6110 } 6111 6112 void getTargetDefines(const LangOptions &Opts, 6113 MacroBuilder &Builder) const override { 6114 // Target identification. 6115 Builder.defineMacro("__aarch64__"); 6116 6117 // Target properties. 6118 Builder.defineMacro("_LP64"); 6119 Builder.defineMacro("__LP64__"); 6120 6121 // ACLE predefines. Many can only have one possible value on v8 AArch64. 6122 Builder.defineMacro("__ARM_ACLE", "200"); 6123 Builder.defineMacro("__ARM_ARCH", "8"); 6124 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 6125 6126 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 6127 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 6128 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 6129 6130 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 6131 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 6132 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 6133 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 6134 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 6135 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 6136 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 6137 6138 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 6139 6140 // 0xe implies support for half, single and double precision operations. 6141 Builder.defineMacro("__ARM_FP", "0xE"); 6142 6143 // PCS specifies this for SysV variants, which is all we support. Other ABIs 6144 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 6145 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 6146 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 6147 6148 if (Opts.UnsafeFPMath) 6149 Builder.defineMacro("__ARM_FP_FAST", "1"); 6150 6151 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 6152 6153 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 6154 Opts.ShortEnums ? "1" : "4"); 6155 6156 if (FPU == NeonMode) { 6157 Builder.defineMacro("__ARM_NEON", "1"); 6158 // 64-bit NEON supports half, single and double precision operations. 6159 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 6160 } 6161 6162 if (CRC) 6163 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 6164 6165 if (Crypto) 6166 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 6167 6168 if (Unaligned) 6169 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 6170 6171 if (V8_1A) 6172 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 6173 6174 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 6175 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6176 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6177 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6178 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6179 } 6180 6181 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6182 return llvm::makeArrayRef(BuiltinInfo, 6183 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 6184 } 6185 6186 bool hasFeature(StringRef Feature) const override { 6187 return Feature == "aarch64" || 6188 Feature == "arm64" || 6189 Feature == "arm" || 6190 (Feature == "neon" && FPU == NeonMode); 6191 } 6192 6193 bool handleTargetFeatures(std::vector<std::string> &Features, 6194 DiagnosticsEngine &Diags) override { 6195 FPU = FPUMode; 6196 CRC = 0; 6197 Crypto = 0; 6198 Unaligned = 1; 6199 V8_1A = 0; 6200 6201 for (const auto &Feature : Features) { 6202 if (Feature == "+neon") 6203 FPU = NeonMode; 6204 if (Feature == "+crc") 6205 CRC = 1; 6206 if (Feature == "+crypto") 6207 Crypto = 1; 6208 if (Feature == "+strict-align") 6209 Unaligned = 0; 6210 if (Feature == "+v8.1a") 6211 V8_1A = 1; 6212 } 6213 6214 setDataLayout(); 6215 6216 return true; 6217 } 6218 6219 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6220 switch (CC) { 6221 case CC_C: 6222 case CC_Swift: 6223 case CC_PreserveMost: 6224 case CC_PreserveAll: 6225 return CCCR_OK; 6226 default: 6227 return CCCR_Warning; 6228 } 6229 } 6230 6231 bool isCLZForZeroUndef() const override { return false; } 6232 6233 BuiltinVaListKind getBuiltinVaListKind() const override { 6234 return TargetInfo::AArch64ABIBuiltinVaList; 6235 } 6236 6237 ArrayRef<const char *> getGCCRegNames() const override; 6238 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6239 6240 bool validateAsmConstraint(const char *&Name, 6241 TargetInfo::ConstraintInfo &Info) const override { 6242 switch (*Name) { 6243 default: 6244 return false; 6245 case 'w': // Floating point and SIMD registers (V0-V31) 6246 Info.setAllowsRegister(); 6247 return true; 6248 case 'I': // Constant that can be used with an ADD instruction 6249 case 'J': // Constant that can be used with a SUB instruction 6250 case 'K': // Constant that can be used with a 32-bit logical instruction 6251 case 'L': // Constant that can be used with a 64-bit logical instruction 6252 case 'M': // Constant that can be used as a 32-bit MOV immediate 6253 case 'N': // Constant that can be used as a 64-bit MOV immediate 6254 case 'Y': // Floating point constant zero 6255 case 'Z': // Integer constant zero 6256 return true; 6257 case 'Q': // A memory reference with base register and no offset 6258 Info.setAllowsMemory(); 6259 return true; 6260 case 'S': // A symbolic address 6261 Info.setAllowsRegister(); 6262 return true; 6263 case 'U': 6264 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 6265 // Utf: A memory address suitable for ldp/stp in TF mode. 6266 // Usa: An absolute symbolic address. 6267 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 6268 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 6269 case 'z': // Zero register, wzr or xzr 6270 Info.setAllowsRegister(); 6271 return true; 6272 case 'x': // Floating point and SIMD registers (V0-V15) 6273 Info.setAllowsRegister(); 6274 return true; 6275 } 6276 return false; 6277 } 6278 6279 bool 6280 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 6281 std::string &SuggestedModifier) const override { 6282 // Strip off constraint modifiers. 6283 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 6284 Constraint = Constraint.substr(1); 6285 6286 switch (Constraint[0]) { 6287 default: 6288 return true; 6289 case 'z': 6290 case 'r': { 6291 switch (Modifier) { 6292 case 'x': 6293 case 'w': 6294 // For now assume that the person knows what they're 6295 // doing with the modifier. 6296 return true; 6297 default: 6298 // By default an 'r' constraint will be in the 'x' 6299 // registers. 6300 if (Size == 64) 6301 return true; 6302 6303 SuggestedModifier = "w"; 6304 return false; 6305 } 6306 } 6307 } 6308 } 6309 6310 const char *getClobbers() const override { return ""; } 6311 6312 int getEHDataRegisterNumber(unsigned RegNo) const override { 6313 if (RegNo == 0) 6314 return 0; 6315 if (RegNo == 1) 6316 return 1; 6317 return -1; 6318 } 6319 }; 6320 6321 const char *const AArch64TargetInfo::GCCRegNames[] = { 6322 // 32-bit Integer registers 6323 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 6324 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 6325 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 6326 6327 // 64-bit Integer registers 6328 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 6329 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 6330 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 6331 6332 // 32-bit floating point regsisters 6333 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 6334 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 6335 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6336 6337 // 64-bit floating point regsisters 6338 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 6339 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 6340 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6341 6342 // Vector registers 6343 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6344 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6345 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6346 }; 6347 6348 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6349 return llvm::makeArrayRef(GCCRegNames); 6350 } 6351 6352 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6353 { { "w31" }, "wsp" }, 6354 { { "x29" }, "fp" }, 6355 { { "x30" }, "lr" }, 6356 { { "x31" }, "sp" }, 6357 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6358 // don't want to substitute one of these for a different-sized one. 6359 }; 6360 6361 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6362 return llvm::makeArrayRef(GCCRegAliases); 6363 } 6364 6365 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6366 #define BUILTIN(ID, TYPE, ATTRS) \ 6367 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6368 #include "clang/Basic/BuiltinsNEON.def" 6369 6370 #define BUILTIN(ID, TYPE, ATTRS) \ 6371 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6372 #include "clang/Basic/BuiltinsAArch64.def" 6373 }; 6374 6375 class AArch64leTargetInfo : public AArch64TargetInfo { 6376 void setDataLayout() override { 6377 if (getTriple().isOSBinFormatMachO()) 6378 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6379 else 6380 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6381 } 6382 6383 public: 6384 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6385 : AArch64TargetInfo(Triple, Opts) { 6386 } 6387 void getTargetDefines(const LangOptions &Opts, 6388 MacroBuilder &Builder) const override { 6389 Builder.defineMacro("__AARCH64EL__"); 6390 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6391 } 6392 }; 6393 6394 class AArch64beTargetInfo : public AArch64TargetInfo { 6395 void setDataLayout() override { 6396 assert(!getTriple().isOSBinFormatMachO()); 6397 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6398 } 6399 6400 public: 6401 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6402 : AArch64TargetInfo(Triple, Opts) {} 6403 void getTargetDefines(const LangOptions &Opts, 6404 MacroBuilder &Builder) const override { 6405 Builder.defineMacro("__AARCH64EB__"); 6406 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6407 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6408 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6409 } 6410 }; 6411 6412 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6413 protected: 6414 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6415 MacroBuilder &Builder) const override { 6416 Builder.defineMacro("__AARCH64_SIMD__"); 6417 Builder.defineMacro("__ARM64_ARCH_8__"); 6418 Builder.defineMacro("__ARM_NEON__"); 6419 Builder.defineMacro("__LITTLE_ENDIAN__"); 6420 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6421 Builder.defineMacro("__arm64", "1"); 6422 Builder.defineMacro("__arm64__", "1"); 6423 6424 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6425 } 6426 6427 public: 6428 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6429 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6430 Int64Type = SignedLongLong; 6431 WCharType = SignedInt; 6432 UseSignedCharForObjCBool = false; 6433 6434 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6435 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 6436 6437 TheCXXABI.set(TargetCXXABI::iOS64); 6438 } 6439 6440 BuiltinVaListKind getBuiltinVaListKind() const override { 6441 return TargetInfo::CharPtrBuiltinVaList; 6442 } 6443 }; 6444 6445 // Hexagon abstract base class 6446 class HexagonTargetInfo : public TargetInfo { 6447 static const Builtin::Info BuiltinInfo[]; 6448 static const char * const GCCRegNames[]; 6449 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6450 std::string CPU; 6451 bool HasHVX, HasHVXDouble; 6452 bool UseLongCalls; 6453 6454 public: 6455 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6456 : TargetInfo(Triple) { 6457 // Specify the vector alignment explicitly. For v512x1, the calculated 6458 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6459 // the required minimum of 64 bytes. 6460 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6461 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6462 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6463 SizeType = UnsignedInt; 6464 PtrDiffType = SignedInt; 6465 IntPtrType = SignedInt; 6466 6467 // {} in inline assembly are packet specifiers, not assembly variant 6468 // specifiers. 6469 NoAsmVariants = true; 6470 6471 LargeArrayMinWidth = 64; 6472 LargeArrayAlign = 64; 6473 UseBitFieldTypeAlignment = true; 6474 ZeroLengthBitfieldBoundary = 32; 6475 HasHVX = HasHVXDouble = false; 6476 UseLongCalls = false; 6477 } 6478 6479 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6480 return llvm::makeArrayRef(BuiltinInfo, 6481 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6482 } 6483 6484 bool validateAsmConstraint(const char *&Name, 6485 TargetInfo::ConstraintInfo &Info) const override { 6486 switch (*Name) { 6487 case 'v': 6488 case 'q': 6489 if (HasHVX) { 6490 Info.setAllowsRegister(); 6491 return true; 6492 } 6493 break; 6494 case 's': 6495 // Relocatable constant. 6496 return true; 6497 } 6498 return false; 6499 } 6500 6501 void getTargetDefines(const LangOptions &Opts, 6502 MacroBuilder &Builder) const override; 6503 6504 bool isCLZForZeroUndef() const override { return false; } 6505 6506 bool hasFeature(StringRef Feature) const override { 6507 return llvm::StringSwitch<bool>(Feature) 6508 .Case("hexagon", true) 6509 .Case("hvx", HasHVX) 6510 .Case("hvx-double", HasHVXDouble) 6511 .Case("long-calls", UseLongCalls) 6512 .Default(false); 6513 } 6514 6515 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6516 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6517 const override; 6518 6519 bool handleTargetFeatures(std::vector<std::string> &Features, 6520 DiagnosticsEngine &Diags) override; 6521 6522 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6523 bool Enabled) const override; 6524 6525 BuiltinVaListKind getBuiltinVaListKind() const override { 6526 return TargetInfo::CharPtrBuiltinVaList; 6527 } 6528 ArrayRef<const char *> getGCCRegNames() const override; 6529 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6530 const char *getClobbers() const override { 6531 return ""; 6532 } 6533 6534 static const char *getHexagonCPUSuffix(StringRef Name) { 6535 return llvm::StringSwitch<const char*>(Name) 6536 .Case("hexagonv4", "4") 6537 .Case("hexagonv5", "5") 6538 .Case("hexagonv55", "55") 6539 .Case("hexagonv60", "60") 6540 .Case("hexagonv62", "62") 6541 .Default(nullptr); 6542 } 6543 6544 bool setCPU(const std::string &Name) override { 6545 if (!getHexagonCPUSuffix(Name)) 6546 return false; 6547 CPU = Name; 6548 return true; 6549 } 6550 6551 int getEHDataRegisterNumber(unsigned RegNo) const override { 6552 return RegNo < 2 ? RegNo : -1; 6553 } 6554 }; 6555 6556 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6557 MacroBuilder &Builder) const { 6558 Builder.defineMacro("__qdsp6__", "1"); 6559 Builder.defineMacro("__hexagon__", "1"); 6560 6561 if (CPU == "hexagonv4") { 6562 Builder.defineMacro("__HEXAGON_V4__"); 6563 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6564 if (Opts.HexagonQdsp6Compat) { 6565 Builder.defineMacro("__QDSP6_V4__"); 6566 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6567 } 6568 } else if (CPU == "hexagonv5") { 6569 Builder.defineMacro("__HEXAGON_V5__"); 6570 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6571 if(Opts.HexagonQdsp6Compat) { 6572 Builder.defineMacro("__QDSP6_V5__"); 6573 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6574 } 6575 } else if (CPU == "hexagonv55") { 6576 Builder.defineMacro("__HEXAGON_V55__"); 6577 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6578 Builder.defineMacro("__QDSP6_V55__"); 6579 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6580 } else if (CPU == "hexagonv60") { 6581 Builder.defineMacro("__HEXAGON_V60__"); 6582 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6583 Builder.defineMacro("__QDSP6_V60__"); 6584 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6585 } else if (CPU == "hexagonv62") { 6586 Builder.defineMacro("__HEXAGON_V62__"); 6587 Builder.defineMacro("__HEXAGON_ARCH__", "62"); 6588 } 6589 6590 if (hasFeature("hvx")) { 6591 Builder.defineMacro("__HVX__"); 6592 if (hasFeature("hvx-double")) 6593 Builder.defineMacro("__HVXDBL__"); 6594 } 6595 } 6596 6597 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6598 DiagnosticsEngine &Diags, StringRef CPU, 6599 const std::vector<std::string> &FeaturesVec) const { 6600 // Default for v60: -hvx, -hvx-double. 6601 Features["hvx"] = false; 6602 Features["hvx-double"] = false; 6603 Features["long-calls"] = false; 6604 6605 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6606 } 6607 6608 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6609 DiagnosticsEngine &Diags) { 6610 for (auto &F : Features) { 6611 if (F == "+hvx") 6612 HasHVX = true; 6613 else if (F == "-hvx") 6614 HasHVX = HasHVXDouble = false; 6615 else if (F == "+hvx-double") 6616 HasHVX = HasHVXDouble = true; 6617 else if (F == "-hvx-double") 6618 HasHVXDouble = false; 6619 6620 if (F == "+long-calls") 6621 UseLongCalls = true; 6622 else if (F == "-long-calls") 6623 UseLongCalls = false; 6624 } 6625 return true; 6626 } 6627 6628 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 6629 StringRef Name, bool Enabled) const { 6630 if (Enabled) { 6631 if (Name == "hvx-double") 6632 Features["hvx"] = true; 6633 } else { 6634 if (Name == "hvx") 6635 Features["hvx-double"] = false; 6636 } 6637 Features[Name] = Enabled; 6638 } 6639 6640 const char *const HexagonTargetInfo::GCCRegNames[] = { 6641 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6642 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6643 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6644 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6645 "p0", "p1", "p2", "p3", 6646 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6647 }; 6648 6649 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6650 return llvm::makeArrayRef(GCCRegNames); 6651 } 6652 6653 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6654 { { "sp" }, "r29" }, 6655 { { "fp" }, "r30" }, 6656 { { "lr" }, "r31" }, 6657 }; 6658 6659 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6660 return llvm::makeArrayRef(GCCRegAliases); 6661 } 6662 6663 6664 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6665 #define BUILTIN(ID, TYPE, ATTRS) \ 6666 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6667 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6668 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6669 #include "clang/Basic/BuiltinsHexagon.def" 6670 }; 6671 6672 class LanaiTargetInfo : public TargetInfo { 6673 // Class for Lanai (32-bit). 6674 // The CPU profiles supported by the Lanai backend 6675 enum CPUKind { 6676 CK_NONE, 6677 CK_V11, 6678 } CPU; 6679 6680 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6681 static const char *const GCCRegNames[]; 6682 6683 public: 6684 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6685 : TargetInfo(Triple) { 6686 // Description string has to be kept in sync with backend. 6687 resetDataLayout("E" // Big endian 6688 "-m:e" // ELF name manging 6689 "-p:32:32" // 32 bit pointers, 32 bit aligned 6690 "-i64:64" // 64 bit integers, 64 bit aligned 6691 "-a:0:32" // 32 bit alignment of objects of aggregate type 6692 "-n32" // 32 bit native integer width 6693 "-S64" // 64 bit natural stack alignment 6694 ); 6695 6696 // Setting RegParmMax equal to what mregparm was set to in the old 6697 // toolchain 6698 RegParmMax = 4; 6699 6700 // Set the default CPU to V11 6701 CPU = CK_V11; 6702 6703 // Temporary approach to make everything at least word-aligned and allow for 6704 // safely casting between pointers with different alignment requirements. 6705 // TODO: Remove this when there are no more cast align warnings on the 6706 // firmware. 6707 MinGlobalAlign = 32; 6708 } 6709 6710 void getTargetDefines(const LangOptions &Opts, 6711 MacroBuilder &Builder) const override { 6712 // Define __lanai__ when building for target lanai. 6713 Builder.defineMacro("__lanai__"); 6714 6715 // Set define for the CPU specified. 6716 switch (CPU) { 6717 case CK_V11: 6718 Builder.defineMacro("__LANAI_V11__"); 6719 break; 6720 case CK_NONE: 6721 llvm_unreachable("Unhandled target CPU"); 6722 } 6723 } 6724 6725 bool setCPU(const std::string &Name) override { 6726 CPU = llvm::StringSwitch<CPUKind>(Name) 6727 .Case("v11", CK_V11) 6728 .Default(CK_NONE); 6729 6730 return CPU != CK_NONE; 6731 } 6732 6733 bool hasFeature(StringRef Feature) const override { 6734 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6735 } 6736 6737 ArrayRef<const char *> getGCCRegNames() const override; 6738 6739 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6740 6741 BuiltinVaListKind getBuiltinVaListKind() const override { 6742 return TargetInfo::VoidPtrBuiltinVaList; 6743 } 6744 6745 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6746 6747 bool validateAsmConstraint(const char *&Name, 6748 TargetInfo::ConstraintInfo &info) const override { 6749 return false; 6750 } 6751 6752 const char *getClobbers() const override { return ""; } 6753 }; 6754 6755 const char *const LanaiTargetInfo::GCCRegNames[] = { 6756 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6757 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6758 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6759 6760 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6761 return llvm::makeArrayRef(GCCRegNames); 6762 } 6763 6764 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6765 {{"pc"}, "r2"}, 6766 {{"sp"}, "r4"}, 6767 {{"fp"}, "r5"}, 6768 {{"rv"}, "r8"}, 6769 {{"rr1"}, "r10"}, 6770 {{"rr2"}, "r11"}, 6771 {{"rca"}, "r15"}, 6772 }; 6773 6774 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6775 return llvm::makeArrayRef(GCCRegAliases); 6776 } 6777 6778 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6779 class SparcTargetInfo : public TargetInfo { 6780 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6781 static const char * const GCCRegNames[]; 6782 bool SoftFloat; 6783 public: 6784 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6785 : TargetInfo(Triple), SoftFloat(false) {} 6786 6787 int getEHDataRegisterNumber(unsigned RegNo) const override { 6788 if (RegNo == 0) return 24; 6789 if (RegNo == 1) return 25; 6790 return -1; 6791 } 6792 6793 bool handleTargetFeatures(std::vector<std::string> &Features, 6794 DiagnosticsEngine &Diags) override { 6795 // Check if software floating point is enabled 6796 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6797 if (Feature != Features.end()) { 6798 SoftFloat = true; 6799 } 6800 return true; 6801 } 6802 void getTargetDefines(const LangOptions &Opts, 6803 MacroBuilder &Builder) const override { 6804 DefineStd(Builder, "sparc", Opts); 6805 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6806 6807 if (SoftFloat) 6808 Builder.defineMacro("SOFT_FLOAT", "1"); 6809 } 6810 6811 bool hasFeature(StringRef Feature) const override { 6812 return llvm::StringSwitch<bool>(Feature) 6813 .Case("softfloat", SoftFloat) 6814 .Case("sparc", true) 6815 .Default(false); 6816 } 6817 6818 bool hasSjLjLowering() const override { 6819 return true; 6820 } 6821 6822 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6823 // FIXME: Implement! 6824 return None; 6825 } 6826 BuiltinVaListKind getBuiltinVaListKind() const override { 6827 return TargetInfo::VoidPtrBuiltinVaList; 6828 } 6829 ArrayRef<const char *> getGCCRegNames() const override; 6830 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6831 bool validateAsmConstraint(const char *&Name, 6832 TargetInfo::ConstraintInfo &info) const override { 6833 // FIXME: Implement! 6834 switch (*Name) { 6835 case 'I': // Signed 13-bit constant 6836 case 'J': // Zero 6837 case 'K': // 32-bit constant with the low 12 bits clear 6838 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6839 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6840 case 'N': // Same as 'K' but zext (required for SIMode) 6841 case 'O': // The constant 4096 6842 return true; 6843 } 6844 return false; 6845 } 6846 const char *getClobbers() const override { 6847 // FIXME: Implement! 6848 return ""; 6849 } 6850 6851 // No Sparc V7 for now, the backend doesn't support it anyway. 6852 enum CPUKind { 6853 CK_GENERIC, 6854 CK_V8, 6855 CK_SUPERSPARC, 6856 CK_SPARCLITE, 6857 CK_F934, 6858 CK_HYPERSPARC, 6859 CK_SPARCLITE86X, 6860 CK_SPARCLET, 6861 CK_TSC701, 6862 CK_V9, 6863 CK_ULTRASPARC, 6864 CK_ULTRASPARC3, 6865 CK_NIAGARA, 6866 CK_NIAGARA2, 6867 CK_NIAGARA3, 6868 CK_NIAGARA4, 6869 CK_MYRIAD2100, 6870 CK_MYRIAD2150, 6871 CK_MYRIAD2450, 6872 CK_LEON2, 6873 CK_LEON2_AT697E, 6874 CK_LEON2_AT697F, 6875 CK_LEON3, 6876 CK_LEON3_UT699, 6877 CK_LEON3_GR712RC, 6878 CK_LEON4, 6879 CK_LEON4_GR740 6880 } CPU = CK_GENERIC; 6881 6882 enum CPUGeneration { 6883 CG_V8, 6884 CG_V9, 6885 }; 6886 6887 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6888 switch (Kind) { 6889 case CK_GENERIC: 6890 case CK_V8: 6891 case CK_SUPERSPARC: 6892 case CK_SPARCLITE: 6893 case CK_F934: 6894 case CK_HYPERSPARC: 6895 case CK_SPARCLITE86X: 6896 case CK_SPARCLET: 6897 case CK_TSC701: 6898 case CK_MYRIAD2100: 6899 case CK_MYRIAD2150: 6900 case CK_MYRIAD2450: 6901 case CK_LEON2: 6902 case CK_LEON2_AT697E: 6903 case CK_LEON2_AT697F: 6904 case CK_LEON3: 6905 case CK_LEON3_UT699: 6906 case CK_LEON3_GR712RC: 6907 case CK_LEON4: 6908 case CK_LEON4_GR740: 6909 return CG_V8; 6910 case CK_V9: 6911 case CK_ULTRASPARC: 6912 case CK_ULTRASPARC3: 6913 case CK_NIAGARA: 6914 case CK_NIAGARA2: 6915 case CK_NIAGARA3: 6916 case CK_NIAGARA4: 6917 return CG_V9; 6918 } 6919 llvm_unreachable("Unexpected CPU kind"); 6920 } 6921 6922 CPUKind getCPUKind(StringRef Name) const { 6923 return llvm::StringSwitch<CPUKind>(Name) 6924 .Case("v8", CK_V8) 6925 .Case("supersparc", CK_SUPERSPARC) 6926 .Case("sparclite", CK_SPARCLITE) 6927 .Case("f934", CK_F934) 6928 .Case("hypersparc", CK_HYPERSPARC) 6929 .Case("sparclite86x", CK_SPARCLITE86X) 6930 .Case("sparclet", CK_SPARCLET) 6931 .Case("tsc701", CK_TSC701) 6932 .Case("v9", CK_V9) 6933 .Case("ultrasparc", CK_ULTRASPARC) 6934 .Case("ultrasparc3", CK_ULTRASPARC3) 6935 .Case("niagara", CK_NIAGARA) 6936 .Case("niagara2", CK_NIAGARA2) 6937 .Case("niagara3", CK_NIAGARA3) 6938 .Case("niagara4", CK_NIAGARA4) 6939 .Case("ma2100", CK_MYRIAD2100) 6940 .Case("ma2150", CK_MYRIAD2150) 6941 .Case("ma2450", CK_MYRIAD2450) 6942 // FIXME: the myriad2[.n] spellings are obsolete, 6943 // but a grace period is needed to allow updating dependent builds. 6944 .Case("myriad2", CK_MYRIAD2100) 6945 .Case("myriad2.1", CK_MYRIAD2100) 6946 .Case("myriad2.2", CK_MYRIAD2150) 6947 .Case("leon2", CK_LEON2) 6948 .Case("at697e", CK_LEON2_AT697E) 6949 .Case("at697f", CK_LEON2_AT697F) 6950 .Case("leon3", CK_LEON3) 6951 .Case("ut699", CK_LEON3_UT699) 6952 .Case("gr712rc", CK_LEON3_GR712RC) 6953 .Case("leon4", CK_LEON4) 6954 .Case("gr740", CK_LEON4_GR740) 6955 .Default(CK_GENERIC); 6956 } 6957 6958 bool setCPU(const std::string &Name) override { 6959 CPU = getCPUKind(Name); 6960 return CPU != CK_GENERIC; 6961 } 6962 }; 6963 6964 const char * const SparcTargetInfo::GCCRegNames[] = { 6965 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6966 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6967 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6968 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6969 }; 6970 6971 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6972 return llvm::makeArrayRef(GCCRegNames); 6973 } 6974 6975 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6976 { { "g0" }, "r0" }, 6977 { { "g1" }, "r1" }, 6978 { { "g2" }, "r2" }, 6979 { { "g3" }, "r3" }, 6980 { { "g4" }, "r4" }, 6981 { { "g5" }, "r5" }, 6982 { { "g6" }, "r6" }, 6983 { { "g7" }, "r7" }, 6984 { { "o0" }, "r8" }, 6985 { { "o1" }, "r9" }, 6986 { { "o2" }, "r10" }, 6987 { { "o3" }, "r11" }, 6988 { { "o4" }, "r12" }, 6989 { { "o5" }, "r13" }, 6990 { { "o6", "sp" }, "r14" }, 6991 { { "o7" }, "r15" }, 6992 { { "l0" }, "r16" }, 6993 { { "l1" }, "r17" }, 6994 { { "l2" }, "r18" }, 6995 { { "l3" }, "r19" }, 6996 { { "l4" }, "r20" }, 6997 { { "l5" }, "r21" }, 6998 { { "l6" }, "r22" }, 6999 { { "l7" }, "r23" }, 7000 { { "i0" }, "r24" }, 7001 { { "i1" }, "r25" }, 7002 { { "i2" }, "r26" }, 7003 { { "i3" }, "r27" }, 7004 { { "i4" }, "r28" }, 7005 { { "i5" }, "r29" }, 7006 { { "i6", "fp" }, "r30" }, 7007 { { "i7" }, "r31" }, 7008 }; 7009 7010 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 7011 return llvm::makeArrayRef(GCCRegAliases); 7012 } 7013 7014 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 7015 class SparcV8TargetInfo : public SparcTargetInfo { 7016 public: 7017 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7018 : SparcTargetInfo(Triple, Opts) { 7019 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7020 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 7021 switch (getTriple().getOS()) { 7022 default: 7023 SizeType = UnsignedInt; 7024 IntPtrType = SignedInt; 7025 PtrDiffType = SignedInt; 7026 break; 7027 case llvm::Triple::NetBSD: 7028 case llvm::Triple::OpenBSD: 7029 SizeType = UnsignedLong; 7030 IntPtrType = SignedLong; 7031 PtrDiffType = SignedLong; 7032 break; 7033 } 7034 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops 7035 // on up to 64 bits. 7036 MaxAtomicPromoteWidth = 64; 7037 MaxAtomicInlineWidth = 32; 7038 } 7039 7040 void getTargetDefines(const LangOptions &Opts, 7041 MacroBuilder &Builder) const override { 7042 SparcTargetInfo::getTargetDefines(Opts, Builder); 7043 switch (getCPUGeneration(CPU)) { 7044 case CG_V8: 7045 Builder.defineMacro("__sparcv8"); 7046 if (getTriple().getOS() != llvm::Triple::Solaris) 7047 Builder.defineMacro("__sparcv8__"); 7048 break; 7049 case CG_V9: 7050 Builder.defineMacro("__sparcv9"); 7051 if (getTriple().getOS() != llvm::Triple::Solaris) { 7052 Builder.defineMacro("__sparcv9__"); 7053 Builder.defineMacro("__sparc_v9__"); 7054 } 7055 break; 7056 } 7057 if (getTriple().getVendor() == llvm::Triple::Myriad) { 7058 std::string MyriadArchValue, Myriad2Value; 7059 Builder.defineMacro("__sparc_v8__"); 7060 Builder.defineMacro("__leon__"); 7061 switch (CPU) { 7062 case CK_MYRIAD2150: 7063 MyriadArchValue = "__ma2150"; 7064 Myriad2Value = "2"; 7065 break; 7066 case CK_MYRIAD2450: 7067 MyriadArchValue = "__ma2450"; 7068 Myriad2Value = "2"; 7069 break; 7070 default: 7071 MyriadArchValue = "__ma2100"; 7072 Myriad2Value = "1"; 7073 break; 7074 } 7075 Builder.defineMacro(MyriadArchValue, "1"); 7076 Builder.defineMacro(MyriadArchValue+"__", "1"); 7077 Builder.defineMacro("__myriad2__", Myriad2Value); 7078 Builder.defineMacro("__myriad2", Myriad2Value); 7079 } 7080 } 7081 7082 bool hasSjLjLowering() const override { 7083 return true; 7084 } 7085 }; 7086 7087 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 7088 class SparcV8elTargetInfo : public SparcV8TargetInfo { 7089 public: 7090 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7091 : SparcV8TargetInfo(Triple, Opts) { 7092 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7093 } 7094 }; 7095 7096 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 7097 class SparcV9TargetInfo : public SparcTargetInfo { 7098 public: 7099 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7100 : SparcTargetInfo(Triple, Opts) { 7101 // FIXME: Support Sparc quad-precision long double? 7102 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 7103 // This is an LP64 platform. 7104 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7105 7106 // OpenBSD uses long long for int64_t and intmax_t. 7107 if (getTriple().getOS() == llvm::Triple::OpenBSD) 7108 IntMaxType = SignedLongLong; 7109 else 7110 IntMaxType = SignedLong; 7111 Int64Type = IntMaxType; 7112 7113 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 7114 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 7115 LongDoubleWidth = 128; 7116 LongDoubleAlign = 128; 7117 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7118 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7119 } 7120 7121 void getTargetDefines(const LangOptions &Opts, 7122 MacroBuilder &Builder) const override { 7123 SparcTargetInfo::getTargetDefines(Opts, Builder); 7124 Builder.defineMacro("__sparcv9"); 7125 Builder.defineMacro("__arch64__"); 7126 // Solaris doesn't need these variants, but the BSDs do. 7127 if (getTriple().getOS() != llvm::Triple::Solaris) { 7128 Builder.defineMacro("__sparc64__"); 7129 Builder.defineMacro("__sparc_v9__"); 7130 Builder.defineMacro("__sparcv9__"); 7131 } 7132 } 7133 7134 bool setCPU(const std::string &Name) override { 7135 if (!SparcTargetInfo::setCPU(Name)) 7136 return false; 7137 return getCPUGeneration(CPU) == CG_V9; 7138 } 7139 }; 7140 7141 class SystemZTargetInfo : public TargetInfo { 7142 static const Builtin::Info BuiltinInfo[]; 7143 static const char *const GCCRegNames[]; 7144 std::string CPU; 7145 bool HasTransactionalExecution; 7146 bool HasVector; 7147 7148 public: 7149 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7150 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 7151 HasVector(false) { 7152 IntMaxType = SignedLong; 7153 Int64Type = SignedLong; 7154 TLSSupported = true; 7155 IntWidth = IntAlign = 32; 7156 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 7157 PointerWidth = PointerAlign = 64; 7158 LongDoubleWidth = 128; 7159 LongDoubleAlign = 64; 7160 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7161 DefaultAlignForAttributeAligned = 64; 7162 MinGlobalAlign = 16; 7163 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 7164 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7165 } 7166 void getTargetDefines(const LangOptions &Opts, 7167 MacroBuilder &Builder) const override { 7168 Builder.defineMacro("__s390__"); 7169 Builder.defineMacro("__s390x__"); 7170 Builder.defineMacro("__zarch__"); 7171 Builder.defineMacro("__LONG_DOUBLE_128__"); 7172 7173 const std::string ISARev = llvm::StringSwitch<std::string>(CPU) 7174 .Cases("arch8", "z10", "8") 7175 .Cases("arch9", "z196", "9") 7176 .Cases("arch10", "zEC12", "10") 7177 .Cases("arch11", "z13", "11") 7178 .Default(""); 7179 if (!ISARev.empty()) 7180 Builder.defineMacro("__ARCH__", ISARev); 7181 7182 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7183 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7184 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7185 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7186 7187 if (HasTransactionalExecution) 7188 Builder.defineMacro("__HTM__"); 7189 if (HasVector) 7190 Builder.defineMacro("__VX__"); 7191 if (Opts.ZVector) 7192 Builder.defineMacro("__VEC__", "10301"); 7193 } 7194 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7195 return llvm::makeArrayRef(BuiltinInfo, 7196 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 7197 } 7198 7199 ArrayRef<const char *> getGCCRegNames() const override; 7200 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7201 // No aliases. 7202 return None; 7203 } 7204 bool validateAsmConstraint(const char *&Name, 7205 TargetInfo::ConstraintInfo &info) const override; 7206 const char *getClobbers() const override { 7207 // FIXME: Is this really right? 7208 return ""; 7209 } 7210 BuiltinVaListKind getBuiltinVaListKind() const override { 7211 return TargetInfo::SystemZBuiltinVaList; 7212 } 7213 bool setCPU(const std::string &Name) override { 7214 CPU = Name; 7215 bool CPUKnown = llvm::StringSwitch<bool>(Name) 7216 .Case("z10", true) 7217 .Case("arch8", true) 7218 .Case("z196", true) 7219 .Case("arch9", true) 7220 .Case("zEC12", true) 7221 .Case("arch10", true) 7222 .Case("z13", true) 7223 .Case("arch11", true) 7224 .Default(false); 7225 7226 return CPUKnown; 7227 } 7228 bool 7229 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7230 StringRef CPU, 7231 const std::vector<std::string> &FeaturesVec) const override { 7232 if (CPU == "zEC12" || CPU == "arch10") 7233 Features["transactional-execution"] = true; 7234 if (CPU == "z13" || CPU == "arch11") { 7235 Features["transactional-execution"] = true; 7236 Features["vector"] = true; 7237 } 7238 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7239 } 7240 7241 bool handleTargetFeatures(std::vector<std::string> &Features, 7242 DiagnosticsEngine &Diags) override { 7243 HasTransactionalExecution = false; 7244 for (const auto &Feature : Features) { 7245 if (Feature == "+transactional-execution") 7246 HasTransactionalExecution = true; 7247 else if (Feature == "+vector") 7248 HasVector = true; 7249 } 7250 // If we use the vector ABI, vector types are 64-bit aligned. 7251 if (HasVector) { 7252 MaxVectorAlign = 64; 7253 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 7254 "-v128:64-a:8:16-n32:64"); 7255 } 7256 return true; 7257 } 7258 7259 bool hasFeature(StringRef Feature) const override { 7260 return llvm::StringSwitch<bool>(Feature) 7261 .Case("systemz", true) 7262 .Case("htm", HasTransactionalExecution) 7263 .Case("vx", HasVector) 7264 .Default(false); 7265 } 7266 7267 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7268 switch (CC) { 7269 case CC_C: 7270 case CC_Swift: 7271 return CCCR_OK; 7272 default: 7273 return CCCR_Warning; 7274 } 7275 } 7276 7277 StringRef getABI() const override { 7278 if (HasVector) 7279 return "vector"; 7280 return ""; 7281 } 7282 7283 bool useFloat128ManglingForLongDouble() const override { 7284 return true; 7285 } 7286 }; 7287 7288 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 7289 #define BUILTIN(ID, TYPE, ATTRS) \ 7290 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7291 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7292 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 7293 #include "clang/Basic/BuiltinsSystemZ.def" 7294 }; 7295 7296 const char *const SystemZTargetInfo::GCCRegNames[] = { 7297 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7298 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7299 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 7300 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 7301 }; 7302 7303 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 7304 return llvm::makeArrayRef(GCCRegNames); 7305 } 7306 7307 bool SystemZTargetInfo:: 7308 validateAsmConstraint(const char *&Name, 7309 TargetInfo::ConstraintInfo &Info) const { 7310 switch (*Name) { 7311 default: 7312 return false; 7313 7314 case 'a': // Address register 7315 case 'd': // Data register (equivalent to 'r') 7316 case 'f': // Floating-point register 7317 Info.setAllowsRegister(); 7318 return true; 7319 7320 case 'I': // Unsigned 8-bit constant 7321 case 'J': // Unsigned 12-bit constant 7322 case 'K': // Signed 16-bit constant 7323 case 'L': // Signed 20-bit displacement (on all targets we support) 7324 case 'M': // 0x7fffffff 7325 return true; 7326 7327 case 'Q': // Memory with base and unsigned 12-bit displacement 7328 case 'R': // Likewise, plus an index 7329 case 'S': // Memory with base and signed 20-bit displacement 7330 case 'T': // Likewise, plus an index 7331 Info.setAllowsMemory(); 7332 return true; 7333 } 7334 } 7335 7336 class MSP430TargetInfo : public TargetInfo { 7337 static const char *const GCCRegNames[]; 7338 7339 public: 7340 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7341 : TargetInfo(Triple) { 7342 TLSSupported = false; 7343 IntWidth = 16; 7344 IntAlign = 16; 7345 LongWidth = 32; 7346 LongLongWidth = 64; 7347 LongAlign = LongLongAlign = 16; 7348 PointerWidth = 16; 7349 PointerAlign = 16; 7350 SuitableAlign = 16; 7351 SizeType = UnsignedInt; 7352 IntMaxType = SignedLongLong; 7353 IntPtrType = SignedInt; 7354 PtrDiffType = SignedInt; 7355 SigAtomicType = SignedLong; 7356 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 7357 } 7358 void getTargetDefines(const LangOptions &Opts, 7359 MacroBuilder &Builder) const override { 7360 Builder.defineMacro("MSP430"); 7361 Builder.defineMacro("__MSP430__"); 7362 // FIXME: defines for different 'flavours' of MCU 7363 } 7364 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7365 // FIXME: Implement. 7366 return None; 7367 } 7368 bool hasFeature(StringRef Feature) const override { 7369 return Feature == "msp430"; 7370 } 7371 ArrayRef<const char *> getGCCRegNames() const override; 7372 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7373 // No aliases. 7374 return None; 7375 } 7376 bool validateAsmConstraint(const char *&Name, 7377 TargetInfo::ConstraintInfo &info) const override { 7378 // FIXME: implement 7379 switch (*Name) { 7380 case 'K': // the constant 1 7381 case 'L': // constant -1^20 .. 1^19 7382 case 'M': // constant 1-4: 7383 return true; 7384 } 7385 // No target constraints for now. 7386 return false; 7387 } 7388 const char *getClobbers() const override { 7389 // FIXME: Is this really right? 7390 return ""; 7391 } 7392 BuiltinVaListKind getBuiltinVaListKind() const override { 7393 // FIXME: implement 7394 return TargetInfo::CharPtrBuiltinVaList; 7395 } 7396 }; 7397 7398 const char *const MSP430TargetInfo::GCCRegNames[] = { 7399 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7400 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7401 7402 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7403 return llvm::makeArrayRef(GCCRegNames); 7404 } 7405 7406 // LLVM and Clang cannot be used directly to output native binaries for 7407 // target, but is used to compile C code to llvm bitcode with correct 7408 // type and alignment information. 7409 // 7410 // TCE uses the llvm bitcode as input and uses it for generating customized 7411 // target processor and program binary. TCE co-design environment is 7412 // publicly available in http://tce.cs.tut.fi 7413 7414 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7415 0, // Default 7416 3, // opencl_global 7417 4, // opencl_local 7418 5, // opencl_constant 7419 // FIXME: generic has to be added to the target 7420 0, // opencl_generic 7421 0, // cuda_device 7422 0, // cuda_constant 7423 0 // cuda_shared 7424 }; 7425 7426 class TCETargetInfo : public TargetInfo { 7427 public: 7428 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7429 : TargetInfo(Triple) { 7430 TLSSupported = false; 7431 IntWidth = 32; 7432 LongWidth = LongLongWidth = 32; 7433 PointerWidth = 32; 7434 IntAlign = 32; 7435 LongAlign = LongLongAlign = 32; 7436 PointerAlign = 32; 7437 SuitableAlign = 32; 7438 SizeType = UnsignedInt; 7439 IntMaxType = SignedLong; 7440 IntPtrType = SignedInt; 7441 PtrDiffType = SignedInt; 7442 FloatWidth = 32; 7443 FloatAlign = 32; 7444 DoubleWidth = 32; 7445 DoubleAlign = 32; 7446 LongDoubleWidth = 32; 7447 LongDoubleAlign = 32; 7448 FloatFormat = &llvm::APFloat::IEEEsingle(); 7449 DoubleFormat = &llvm::APFloat::IEEEsingle(); 7450 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 7451 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-" 7452 "i16:16:32-i32:32:32-i64:32:32-" 7453 "f32:32:32-f64:32:32-v64:32:32-" 7454 "v128:32:32-v256:32:32-v512:32:32-" 7455 "v1024:32:32-a0:0:32-n32"); 7456 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7457 UseAddrSpaceMapMangling = true; 7458 } 7459 7460 void getTargetDefines(const LangOptions &Opts, 7461 MacroBuilder &Builder) const override { 7462 DefineStd(Builder, "tce", Opts); 7463 Builder.defineMacro("__TCE__"); 7464 Builder.defineMacro("__TCE_V1__"); 7465 } 7466 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7467 7468 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7469 const char *getClobbers() const override { return ""; } 7470 BuiltinVaListKind getBuiltinVaListKind() const override { 7471 return TargetInfo::VoidPtrBuiltinVaList; 7472 } 7473 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7474 bool validateAsmConstraint(const char *&Name, 7475 TargetInfo::ConstraintInfo &info) const override { 7476 return true; 7477 } 7478 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7479 return None; 7480 } 7481 }; 7482 7483 class TCELETargetInfo : public TCETargetInfo { 7484 public: 7485 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7486 : TCETargetInfo(Triple, Opts) { 7487 BigEndian = false; 7488 7489 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-" 7490 "i16:16:32-i32:32:32-i64:32:32-" 7491 "f32:32:32-f64:32:32-v64:32:32-" 7492 "v128:32:32-v256:32:32-v512:32:32-" 7493 "v1024:32:32-a0:0:32-n32"); 7494 7495 } 7496 7497 virtual void getTargetDefines(const LangOptions &Opts, 7498 MacroBuilder &Builder) const { 7499 DefineStd(Builder, "tcele", Opts); 7500 Builder.defineMacro("__TCE__"); 7501 Builder.defineMacro("__TCE_V1__"); 7502 Builder.defineMacro("__TCELE__"); 7503 Builder.defineMacro("__TCELE_V1__"); 7504 } 7505 7506 }; 7507 7508 class BPFTargetInfo : public TargetInfo { 7509 public: 7510 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7511 : TargetInfo(Triple) { 7512 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7513 SizeType = UnsignedLong; 7514 PtrDiffType = SignedLong; 7515 IntPtrType = SignedLong; 7516 IntMaxType = SignedLong; 7517 Int64Type = SignedLong; 7518 RegParmMax = 5; 7519 if (Triple.getArch() == llvm::Triple::bpfeb) { 7520 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7521 } else { 7522 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7523 } 7524 MaxAtomicPromoteWidth = 64; 7525 MaxAtomicInlineWidth = 64; 7526 TLSSupported = false; 7527 } 7528 void getTargetDefines(const LangOptions &Opts, 7529 MacroBuilder &Builder) const override { 7530 DefineStd(Builder, "bpf", Opts); 7531 Builder.defineMacro("__BPF__"); 7532 } 7533 bool hasFeature(StringRef Feature) const override { 7534 return Feature == "bpf"; 7535 } 7536 7537 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7538 const char *getClobbers() const override { 7539 return ""; 7540 } 7541 BuiltinVaListKind getBuiltinVaListKind() const override { 7542 return TargetInfo::VoidPtrBuiltinVaList; 7543 } 7544 ArrayRef<const char *> getGCCRegNames() const override { 7545 return None; 7546 } 7547 bool validateAsmConstraint(const char *&Name, 7548 TargetInfo::ConstraintInfo &info) const override { 7549 return true; 7550 } 7551 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7552 return None; 7553 } 7554 }; 7555 7556 class MipsTargetInfo : public TargetInfo { 7557 void setDataLayout() { 7558 StringRef Layout; 7559 7560 if (ABI == "o32") 7561 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7562 else if (ABI == "n32") 7563 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7564 else if (ABI == "n64") 7565 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7566 else 7567 llvm_unreachable("Invalid ABI"); 7568 7569 if (BigEndian) 7570 resetDataLayout(("E-" + Layout).str()); 7571 else 7572 resetDataLayout(("e-" + Layout).str()); 7573 } 7574 7575 7576 static const Builtin::Info BuiltinInfo[]; 7577 std::string CPU; 7578 bool IsMips16; 7579 bool IsMicromips; 7580 bool IsNan2008; 7581 bool IsSingleFloat; 7582 bool IsNoABICalls; 7583 bool CanUseBSDABICalls; 7584 enum MipsFloatABI { 7585 HardFloat, SoftFloat 7586 } FloatABI; 7587 enum DspRevEnum { 7588 NoDSP, DSP1, DSP2 7589 } DspRev; 7590 bool HasMSA; 7591 7592 protected: 7593 bool HasFP64; 7594 std::string ABI; 7595 7596 public: 7597 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7598 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7599 IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false), 7600 CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP), 7601 HasMSA(false), HasFP64(false) { 7602 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7603 7604 setABI((getTriple().getArch() == llvm::Triple::mips || 7605 getTriple().getArch() == llvm::Triple::mipsel) 7606 ? "o32" 7607 : "n64"); 7608 7609 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7610 7611 CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD || 7612 Triple.getOS() == llvm::Triple::OpenBSD; 7613 } 7614 7615 bool isNaN2008Default() const { 7616 return CPU == "mips32r6" || CPU == "mips64r6"; 7617 } 7618 7619 bool isFP64Default() const { 7620 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7621 } 7622 7623 bool isNan2008() const override { 7624 return IsNan2008; 7625 } 7626 7627 bool processorSupportsGPR64() const { 7628 return llvm::StringSwitch<bool>(CPU) 7629 .Case("mips3", true) 7630 .Case("mips4", true) 7631 .Case("mips5", true) 7632 .Case("mips64", true) 7633 .Case("mips64r2", true) 7634 .Case("mips64r3", true) 7635 .Case("mips64r5", true) 7636 .Case("mips64r6", true) 7637 .Case("octeon", true) 7638 .Default(false); 7639 return false; 7640 } 7641 7642 StringRef getABI() const override { return ABI; } 7643 bool setABI(const std::string &Name) override { 7644 if (Name == "o32") { 7645 setO32ABITypes(); 7646 ABI = Name; 7647 return true; 7648 } 7649 7650 if (Name == "n32") { 7651 setN32ABITypes(); 7652 ABI = Name; 7653 return true; 7654 } 7655 if (Name == "n64") { 7656 setN64ABITypes(); 7657 ABI = Name; 7658 return true; 7659 } 7660 return false; 7661 } 7662 7663 void setO32ABITypes() { 7664 Int64Type = SignedLongLong; 7665 IntMaxType = Int64Type; 7666 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7667 LongDoubleWidth = LongDoubleAlign = 64; 7668 LongWidth = LongAlign = 32; 7669 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7670 PointerWidth = PointerAlign = 32; 7671 PtrDiffType = SignedInt; 7672 SizeType = UnsignedInt; 7673 SuitableAlign = 64; 7674 } 7675 7676 void setN32N64ABITypes() { 7677 LongDoubleWidth = LongDoubleAlign = 128; 7678 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7679 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7680 LongDoubleWidth = LongDoubleAlign = 64; 7681 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7682 } 7683 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7684 SuitableAlign = 128; 7685 } 7686 7687 void setN64ABITypes() { 7688 setN32N64ABITypes(); 7689 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 7690 Int64Type = SignedLongLong; 7691 } else { 7692 Int64Type = SignedLong; 7693 } 7694 IntMaxType = Int64Type; 7695 LongWidth = LongAlign = 64; 7696 PointerWidth = PointerAlign = 64; 7697 PtrDiffType = SignedLong; 7698 SizeType = UnsignedLong; 7699 } 7700 7701 void setN32ABITypes() { 7702 setN32N64ABITypes(); 7703 Int64Type = SignedLongLong; 7704 IntMaxType = Int64Type; 7705 LongWidth = LongAlign = 32; 7706 PointerWidth = PointerAlign = 32; 7707 PtrDiffType = SignedInt; 7708 SizeType = UnsignedInt; 7709 } 7710 7711 bool setCPU(const std::string &Name) override { 7712 CPU = Name; 7713 return llvm::StringSwitch<bool>(Name) 7714 .Case("mips1", true) 7715 .Case("mips2", true) 7716 .Case("mips3", true) 7717 .Case("mips4", true) 7718 .Case("mips5", true) 7719 .Case("mips32", true) 7720 .Case("mips32r2", true) 7721 .Case("mips32r3", true) 7722 .Case("mips32r5", true) 7723 .Case("mips32r6", true) 7724 .Case("mips64", true) 7725 .Case("mips64r2", true) 7726 .Case("mips64r3", true) 7727 .Case("mips64r5", true) 7728 .Case("mips64r6", true) 7729 .Case("octeon", true) 7730 .Case("p5600", true) 7731 .Default(false); 7732 } 7733 const std::string& getCPU() const { return CPU; } 7734 bool 7735 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7736 StringRef CPU, 7737 const std::vector<std::string> &FeaturesVec) const override { 7738 if (CPU.empty()) 7739 CPU = getCPU(); 7740 if (CPU == "octeon") 7741 Features["mips64r2"] = Features["cnmips"] = true; 7742 else 7743 Features[CPU] = true; 7744 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7745 } 7746 7747 void getTargetDefines(const LangOptions &Opts, 7748 MacroBuilder &Builder) const override { 7749 if (BigEndian) { 7750 DefineStd(Builder, "MIPSEB", Opts); 7751 Builder.defineMacro("_MIPSEB"); 7752 } else { 7753 DefineStd(Builder, "MIPSEL", Opts); 7754 Builder.defineMacro("_MIPSEL"); 7755 } 7756 7757 Builder.defineMacro("__mips__"); 7758 Builder.defineMacro("_mips"); 7759 if (Opts.GNUMode) 7760 Builder.defineMacro("mips"); 7761 7762 if (ABI == "o32") { 7763 Builder.defineMacro("__mips", "32"); 7764 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7765 } else { 7766 Builder.defineMacro("__mips", "64"); 7767 Builder.defineMacro("__mips64"); 7768 Builder.defineMacro("__mips64__"); 7769 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7770 } 7771 7772 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7773 .Cases("mips32", "mips64", "1") 7774 .Cases("mips32r2", "mips64r2", "2") 7775 .Cases("mips32r3", "mips64r3", "3") 7776 .Cases("mips32r5", "mips64r5", "5") 7777 .Cases("mips32r6", "mips64r6", "6") 7778 .Default(""); 7779 if (!ISARev.empty()) 7780 Builder.defineMacro("__mips_isa_rev", ISARev); 7781 7782 if (ABI == "o32") { 7783 Builder.defineMacro("__mips_o32"); 7784 Builder.defineMacro("_ABIO32", "1"); 7785 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7786 } else if (ABI == "n32") { 7787 Builder.defineMacro("__mips_n32"); 7788 Builder.defineMacro("_ABIN32", "2"); 7789 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7790 } else if (ABI == "n64") { 7791 Builder.defineMacro("__mips_n64"); 7792 Builder.defineMacro("_ABI64", "3"); 7793 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7794 } else 7795 llvm_unreachable("Invalid ABI."); 7796 7797 if (!IsNoABICalls) { 7798 Builder.defineMacro("__mips_abicalls"); 7799 if (CanUseBSDABICalls) 7800 Builder.defineMacro("__ABICALLS__"); 7801 } 7802 7803 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7804 7805 switch (FloatABI) { 7806 case HardFloat: 7807 Builder.defineMacro("__mips_hard_float", Twine(1)); 7808 break; 7809 case SoftFloat: 7810 Builder.defineMacro("__mips_soft_float", Twine(1)); 7811 break; 7812 } 7813 7814 if (IsSingleFloat) 7815 Builder.defineMacro("__mips_single_float", Twine(1)); 7816 7817 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7818 Builder.defineMacro("_MIPS_FPSET", 7819 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7820 7821 if (IsMips16) 7822 Builder.defineMacro("__mips16", Twine(1)); 7823 7824 if (IsMicromips) 7825 Builder.defineMacro("__mips_micromips", Twine(1)); 7826 7827 if (IsNan2008) 7828 Builder.defineMacro("__mips_nan2008", Twine(1)); 7829 7830 switch (DspRev) { 7831 default: 7832 break; 7833 case DSP1: 7834 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7835 Builder.defineMacro("__mips_dsp", Twine(1)); 7836 break; 7837 case DSP2: 7838 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7839 Builder.defineMacro("__mips_dspr2", Twine(1)); 7840 Builder.defineMacro("__mips_dsp", Twine(1)); 7841 break; 7842 } 7843 7844 if (HasMSA) 7845 Builder.defineMacro("__mips_msa", Twine(1)); 7846 7847 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7848 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7849 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7850 7851 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7852 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7853 7854 // These shouldn't be defined for MIPS-I but there's no need to check 7855 // for that since MIPS-I isn't supported. 7856 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7857 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7858 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7859 7860 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7861 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7862 // the instructions exist but using them violates the ABI since they 7863 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7864 if (ABI == "n32" || ABI == "n64") 7865 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7866 } 7867 7868 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7869 return llvm::makeArrayRef(BuiltinInfo, 7870 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7871 } 7872 bool hasFeature(StringRef Feature) const override { 7873 return llvm::StringSwitch<bool>(Feature) 7874 .Case("mips", true) 7875 .Case("fp64", HasFP64) 7876 .Default(false); 7877 } 7878 BuiltinVaListKind getBuiltinVaListKind() const override { 7879 return TargetInfo::VoidPtrBuiltinVaList; 7880 } 7881 ArrayRef<const char *> getGCCRegNames() const override { 7882 static const char *const GCCRegNames[] = { 7883 // CPU register names 7884 // Must match second column of GCCRegAliases 7885 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7886 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7887 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7888 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7889 // Floating point register names 7890 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7891 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7892 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7893 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7894 // Hi/lo and condition register names 7895 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7896 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7897 "$ac3hi","$ac3lo", 7898 // MSA register names 7899 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7900 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7901 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7902 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7903 // MSA control register names 7904 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7905 "$msarequest", "$msamap", "$msaunmap" 7906 }; 7907 return llvm::makeArrayRef(GCCRegNames); 7908 } 7909 bool validateAsmConstraint(const char *&Name, 7910 TargetInfo::ConstraintInfo &Info) const override { 7911 switch (*Name) { 7912 default: 7913 return false; 7914 case 'r': // CPU registers. 7915 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7916 case 'y': // Equivalent to "r", backward compatibility only. 7917 case 'f': // floating-point registers. 7918 case 'c': // $25 for indirect jumps 7919 case 'l': // lo register 7920 case 'x': // hilo register pair 7921 Info.setAllowsRegister(); 7922 return true; 7923 case 'I': // Signed 16-bit constant 7924 case 'J': // Integer 0 7925 case 'K': // Unsigned 16-bit constant 7926 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7927 case 'M': // Constants not loadable via lui, addiu, or ori 7928 case 'N': // Constant -1 to -65535 7929 case 'O': // A signed 15-bit constant 7930 case 'P': // A constant between 1 go 65535 7931 return true; 7932 case 'R': // An address that can be used in a non-macro load or store 7933 Info.setAllowsMemory(); 7934 return true; 7935 case 'Z': 7936 if (Name[1] == 'C') { // An address usable by ll, and sc. 7937 Info.setAllowsMemory(); 7938 Name++; // Skip over 'Z'. 7939 return true; 7940 } 7941 return false; 7942 } 7943 } 7944 7945 std::string convertConstraint(const char *&Constraint) const override { 7946 std::string R; 7947 switch (*Constraint) { 7948 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7949 if (Constraint[1] == 'C') { 7950 R = std::string("^") + std::string(Constraint, 2); 7951 Constraint++; 7952 return R; 7953 } 7954 break; 7955 } 7956 return TargetInfo::convertConstraint(Constraint); 7957 } 7958 7959 const char *getClobbers() const override { 7960 // In GCC, $1 is not widely used in generated code (it's used only in a few 7961 // specific situations), so there is no real need for users to add it to 7962 // the clobbers list if they want to use it in their inline assembly code. 7963 // 7964 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7965 // code generation, so using it in inline assembly without adding it to the 7966 // clobbers list can cause conflicts between the inline assembly code and 7967 // the surrounding generated code. 7968 // 7969 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7970 // operands, which will conflict with the ".set at" assembler option (which 7971 // we use only for inline assembly, in order to maintain compatibility with 7972 // GCC) and will also conflict with the user's usage of $1. 7973 // 7974 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7975 // register for generated code is to automatically clobber $1 for all inline 7976 // assembly code. 7977 // 7978 // FIXME: We should automatically clobber $1 only for inline assembly code 7979 // which actually uses it. This would allow LLVM to use $1 for inline 7980 // assembly operands if the user's assembly code doesn't use it. 7981 return "~{$1}"; 7982 } 7983 7984 bool handleTargetFeatures(std::vector<std::string> &Features, 7985 DiagnosticsEngine &Diags) override { 7986 IsMips16 = false; 7987 IsMicromips = false; 7988 IsNan2008 = isNaN2008Default(); 7989 IsSingleFloat = false; 7990 FloatABI = HardFloat; 7991 DspRev = NoDSP; 7992 HasFP64 = isFP64Default(); 7993 7994 for (const auto &Feature : Features) { 7995 if (Feature == "+single-float") 7996 IsSingleFloat = true; 7997 else if (Feature == "+soft-float") 7998 FloatABI = SoftFloat; 7999 else if (Feature == "+mips16") 8000 IsMips16 = true; 8001 else if (Feature == "+micromips") 8002 IsMicromips = true; 8003 else if (Feature == "+dsp") 8004 DspRev = std::max(DspRev, DSP1); 8005 else if (Feature == "+dspr2") 8006 DspRev = std::max(DspRev, DSP2); 8007 else if (Feature == "+msa") 8008 HasMSA = true; 8009 else if (Feature == "+fp64") 8010 HasFP64 = true; 8011 else if (Feature == "-fp64") 8012 HasFP64 = false; 8013 else if (Feature == "+nan2008") 8014 IsNan2008 = true; 8015 else if (Feature == "-nan2008") 8016 IsNan2008 = false; 8017 else if (Feature == "+noabicalls") 8018 IsNoABICalls = true; 8019 } 8020 8021 setDataLayout(); 8022 8023 return true; 8024 } 8025 8026 int getEHDataRegisterNumber(unsigned RegNo) const override { 8027 if (RegNo == 0) return 4; 8028 if (RegNo == 1) return 5; 8029 return -1; 8030 } 8031 8032 bool isCLZForZeroUndef() const override { return false; } 8033 8034 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8035 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 8036 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8037 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8038 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 8039 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 8040 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 8041 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8042 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8043 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8044 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8045 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8046 {{"ra"}, "$31"}}; 8047 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 8048 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8049 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8050 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 8051 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 8052 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 8053 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8054 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8055 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8056 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8057 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8058 {{"ra"}, "$31"}}; 8059 if (ABI == "o32") 8060 return llvm::makeArrayRef(O32RegAliases); 8061 return llvm::makeArrayRef(NewABIRegAliases); 8062 } 8063 8064 bool hasInt128Type() const override { 8065 return ABI == "n32" || ABI == "n64"; 8066 } 8067 8068 bool validateTarget(DiagnosticsEngine &Diags) const override { 8069 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 8070 // this yet. It's better to fail here than on the backend assertion. 8071 if (processorSupportsGPR64() && ABI == "o32") { 8072 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8073 return false; 8074 } 8075 8076 // 64-bit ABI's require 64-bit CPU's. 8077 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 8078 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8079 return false; 8080 } 8081 8082 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 8083 // can't handle this yet. It's better to fail here than on the 8084 // backend assertion. 8085 if ((getTriple().getArch() == llvm::Triple::mips64 || 8086 getTriple().getArch() == llvm::Triple::mips64el) && 8087 ABI == "o32") { 8088 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8089 << ABI << getTriple().str(); 8090 return false; 8091 } 8092 8093 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 8094 // can't handle this yet. It's better to fail here than on the 8095 // backend assertion. 8096 if ((getTriple().getArch() == llvm::Triple::mips || 8097 getTriple().getArch() == llvm::Triple::mipsel) && 8098 (ABI == "n32" || ABI == "n64")) { 8099 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8100 << ABI << getTriple().str(); 8101 return false; 8102 } 8103 8104 return true; 8105 } 8106 }; 8107 8108 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 8109 #define BUILTIN(ID, TYPE, ATTRS) \ 8110 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8111 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8112 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8113 #include "clang/Basic/BuiltinsMips.def" 8114 }; 8115 8116 class PNaClTargetInfo : public TargetInfo { 8117 public: 8118 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8119 : TargetInfo(Triple) { 8120 this->LongAlign = 32; 8121 this->LongWidth = 32; 8122 this->PointerAlign = 32; 8123 this->PointerWidth = 32; 8124 this->IntMaxType = TargetInfo::SignedLongLong; 8125 this->Int64Type = TargetInfo::SignedLongLong; 8126 this->DoubleAlign = 64; 8127 this->LongDoubleWidth = 64; 8128 this->LongDoubleAlign = 64; 8129 this->SizeType = TargetInfo::UnsignedInt; 8130 this->PtrDiffType = TargetInfo::SignedInt; 8131 this->IntPtrType = TargetInfo::SignedInt; 8132 this->RegParmMax = 0; // Disallow regparm 8133 } 8134 8135 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 8136 Builder.defineMacro("__le32__"); 8137 Builder.defineMacro("__pnacl__"); 8138 } 8139 void getTargetDefines(const LangOptions &Opts, 8140 MacroBuilder &Builder) const override { 8141 getArchDefines(Opts, Builder); 8142 } 8143 bool hasFeature(StringRef Feature) const override { 8144 return Feature == "pnacl"; 8145 } 8146 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8147 BuiltinVaListKind getBuiltinVaListKind() const override { 8148 return TargetInfo::PNaClABIBuiltinVaList; 8149 } 8150 ArrayRef<const char *> getGCCRegNames() const override; 8151 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 8152 bool validateAsmConstraint(const char *&Name, 8153 TargetInfo::ConstraintInfo &Info) const override { 8154 return false; 8155 } 8156 8157 const char *getClobbers() const override { 8158 return ""; 8159 } 8160 }; 8161 8162 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 8163 return None; 8164 } 8165 8166 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 8167 return None; 8168 } 8169 8170 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 8171 class NaClMips32TargetInfo : public MipsTargetInfo { 8172 public: 8173 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8174 : MipsTargetInfo(Triple, Opts) {} 8175 8176 BuiltinVaListKind getBuiltinVaListKind() const override { 8177 return TargetInfo::PNaClABIBuiltinVaList; 8178 } 8179 }; 8180 8181 class Le64TargetInfo : public TargetInfo { 8182 static const Builtin::Info BuiltinInfo[]; 8183 8184 public: 8185 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8186 : TargetInfo(Triple) { 8187 NoAsmVariants = true; 8188 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 8189 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8190 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 8191 } 8192 8193 void getTargetDefines(const LangOptions &Opts, 8194 MacroBuilder &Builder) const override { 8195 DefineStd(Builder, "unix", Opts); 8196 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 8197 Builder.defineMacro("__ELF__"); 8198 } 8199 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8200 return llvm::makeArrayRef(BuiltinInfo, 8201 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 8202 } 8203 BuiltinVaListKind getBuiltinVaListKind() const override { 8204 return TargetInfo::PNaClABIBuiltinVaList; 8205 } 8206 const char *getClobbers() const override { return ""; } 8207 ArrayRef<const char *> getGCCRegNames() const override { 8208 return None; 8209 } 8210 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8211 return None; 8212 } 8213 bool validateAsmConstraint(const char *&Name, 8214 TargetInfo::ConstraintInfo &Info) const override { 8215 return false; 8216 } 8217 8218 bool hasProtectedVisibility() const override { return false; } 8219 }; 8220 8221 class WebAssemblyTargetInfo : public TargetInfo { 8222 static const Builtin::Info BuiltinInfo[]; 8223 8224 enum SIMDEnum { 8225 NoSIMD, 8226 SIMD128, 8227 } SIMDLevel; 8228 8229 public: 8230 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 8231 : TargetInfo(T), SIMDLevel(NoSIMD) { 8232 NoAsmVariants = true; 8233 SuitableAlign = 128; 8234 LargeArrayMinWidth = 128; 8235 LargeArrayAlign = 128; 8236 SimdDefaultAlign = 128; 8237 SigAtomicType = SignedLong; 8238 LongDoubleWidth = LongDoubleAlign = 128; 8239 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8240 SizeType = UnsignedInt; 8241 PtrDiffType = SignedInt; 8242 IntPtrType = SignedInt; 8243 } 8244 8245 protected: 8246 void getTargetDefines(const LangOptions &Opts, 8247 MacroBuilder &Builder) const override { 8248 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 8249 if (SIMDLevel >= SIMD128) 8250 Builder.defineMacro("__wasm_simd128__"); 8251 } 8252 8253 private: 8254 bool 8255 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 8256 StringRef CPU, 8257 const std::vector<std::string> &FeaturesVec) const override { 8258 if (CPU == "bleeding-edge") 8259 Features["simd128"] = true; 8260 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 8261 } 8262 bool hasFeature(StringRef Feature) const final { 8263 return llvm::StringSwitch<bool>(Feature) 8264 .Case("simd128", SIMDLevel >= SIMD128) 8265 .Default(false); 8266 } 8267 bool handleTargetFeatures(std::vector<std::string> &Features, 8268 DiagnosticsEngine &Diags) final { 8269 for (const auto &Feature : Features) { 8270 if (Feature == "+simd128") { 8271 SIMDLevel = std::max(SIMDLevel, SIMD128); 8272 continue; 8273 } 8274 if (Feature == "-simd128") { 8275 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 8276 continue; 8277 } 8278 8279 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 8280 << "-target-feature"; 8281 return false; 8282 } 8283 return true; 8284 } 8285 bool setCPU(const std::string &Name) final { 8286 return llvm::StringSwitch<bool>(Name) 8287 .Case("mvp", true) 8288 .Case("bleeding-edge", true) 8289 .Case("generic", true) 8290 .Default(false); 8291 } 8292 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 8293 return llvm::makeArrayRef(BuiltinInfo, 8294 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 8295 } 8296 BuiltinVaListKind getBuiltinVaListKind() const final { 8297 return VoidPtrBuiltinVaList; 8298 } 8299 ArrayRef<const char *> getGCCRegNames() const final { 8300 return None; 8301 } 8302 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 8303 return None; 8304 } 8305 bool 8306 validateAsmConstraint(const char *&Name, 8307 TargetInfo::ConstraintInfo &Info) const final { 8308 return false; 8309 } 8310 const char *getClobbers() const final { return ""; } 8311 bool isCLZForZeroUndef() const final { return false; } 8312 bool hasInt128Type() const final { return true; } 8313 IntType getIntTypeByWidth(unsigned BitWidth, 8314 bool IsSigned) const final { 8315 // WebAssembly prefers long long for explicitly 64-bit integers. 8316 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8317 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8318 } 8319 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8320 bool IsSigned) const final { 8321 // WebAssembly uses long long for int_least64_t and int_fast64_t. 8322 return BitWidth == 64 8323 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8324 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 8325 } 8326 }; 8327 8328 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 8329 #define BUILTIN(ID, TYPE, ATTRS) \ 8330 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8331 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8332 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8333 #include "clang/Basic/BuiltinsWebAssembly.def" 8334 }; 8335 8336 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 8337 public: 8338 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 8339 const TargetOptions &Opts) 8340 : WebAssemblyTargetInfo(T, Opts) { 8341 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 8342 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 8343 } 8344 8345 protected: 8346 void getTargetDefines(const LangOptions &Opts, 8347 MacroBuilder &Builder) const override { 8348 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8349 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 8350 } 8351 }; 8352 8353 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 8354 public: 8355 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 8356 const TargetOptions &Opts) 8357 : WebAssemblyTargetInfo(T, Opts) { 8358 LongAlign = LongWidth = 64; 8359 PointerAlign = PointerWidth = 64; 8360 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8361 SizeType = UnsignedLong; 8362 PtrDiffType = SignedLong; 8363 IntPtrType = SignedLong; 8364 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 8365 } 8366 8367 protected: 8368 void getTargetDefines(const LangOptions &Opts, 8369 MacroBuilder &Builder) const override { 8370 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8371 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 8372 } 8373 }; 8374 8375 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 8376 #define BUILTIN(ID, TYPE, ATTRS) \ 8377 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8378 #include "clang/Basic/BuiltinsLe64.def" 8379 }; 8380 8381 static const unsigned SPIRAddrSpaceMap[] = { 8382 0, // Default 8383 1, // opencl_global 8384 3, // opencl_local 8385 2, // opencl_constant 8386 4, // opencl_generic 8387 0, // cuda_device 8388 0, // cuda_constant 8389 0 // cuda_shared 8390 }; 8391 class SPIRTargetInfo : public TargetInfo { 8392 public: 8393 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8394 : TargetInfo(Triple) { 8395 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 8396 "SPIR target must use unknown OS"); 8397 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 8398 "SPIR target must use unknown environment type"); 8399 TLSSupported = false; 8400 LongWidth = LongAlign = 64; 8401 AddrSpaceMap = &SPIRAddrSpaceMap; 8402 UseAddrSpaceMapMangling = true; 8403 // Define available target features 8404 // These must be defined in sorted order! 8405 NoAsmVariants = true; 8406 } 8407 void getTargetDefines(const LangOptions &Opts, 8408 MacroBuilder &Builder) const override { 8409 DefineStd(Builder, "SPIR", Opts); 8410 } 8411 bool hasFeature(StringRef Feature) const override { 8412 return Feature == "spir"; 8413 } 8414 8415 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8416 const char *getClobbers() const override { return ""; } 8417 ArrayRef<const char *> getGCCRegNames() const override { return None; } 8418 bool validateAsmConstraint(const char *&Name, 8419 TargetInfo::ConstraintInfo &info) const override { 8420 return true; 8421 } 8422 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8423 return None; 8424 } 8425 BuiltinVaListKind getBuiltinVaListKind() const override { 8426 return TargetInfo::VoidPtrBuiltinVaList; 8427 } 8428 8429 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 8430 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 8431 : CCCR_Warning; 8432 } 8433 8434 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8435 return CC_SpirFunction; 8436 } 8437 8438 void setSupportedOpenCLOpts() override { 8439 // Assume all OpenCL extensions and optional core features are supported 8440 // for SPIR since it is a generic target. 8441 getSupportedOpenCLOpts().supportAll(); 8442 } 8443 }; 8444 8445 class SPIR32TargetInfo : public SPIRTargetInfo { 8446 public: 8447 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8448 : SPIRTargetInfo(Triple, Opts) { 8449 PointerWidth = PointerAlign = 32; 8450 SizeType = TargetInfo::UnsignedInt; 8451 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8452 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8453 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8454 } 8455 void getTargetDefines(const LangOptions &Opts, 8456 MacroBuilder &Builder) const override { 8457 DefineStd(Builder, "SPIR32", Opts); 8458 } 8459 }; 8460 8461 class SPIR64TargetInfo : public SPIRTargetInfo { 8462 public: 8463 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8464 : SPIRTargetInfo(Triple, Opts) { 8465 PointerWidth = PointerAlign = 64; 8466 SizeType = TargetInfo::UnsignedLong; 8467 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8468 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8469 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8470 } 8471 void getTargetDefines(const LangOptions &Opts, 8472 MacroBuilder &Builder) const override { 8473 DefineStd(Builder, "SPIR64", Opts); 8474 } 8475 }; 8476 8477 class XCoreTargetInfo : public TargetInfo { 8478 static const Builtin::Info BuiltinInfo[]; 8479 public: 8480 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8481 : TargetInfo(Triple) { 8482 NoAsmVariants = true; 8483 LongLongAlign = 32; 8484 SuitableAlign = 32; 8485 DoubleAlign = LongDoubleAlign = 32; 8486 SizeType = UnsignedInt; 8487 PtrDiffType = SignedInt; 8488 IntPtrType = SignedInt; 8489 WCharType = UnsignedChar; 8490 WIntType = UnsignedInt; 8491 UseZeroLengthBitfieldAlignment = true; 8492 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8493 "-f64:32-a:0:32-n32"); 8494 } 8495 void getTargetDefines(const LangOptions &Opts, 8496 MacroBuilder &Builder) const override { 8497 Builder.defineMacro("__XS1B__"); 8498 } 8499 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8500 return llvm::makeArrayRef(BuiltinInfo, 8501 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8502 } 8503 BuiltinVaListKind getBuiltinVaListKind() const override { 8504 return TargetInfo::VoidPtrBuiltinVaList; 8505 } 8506 const char *getClobbers() const override { 8507 return ""; 8508 } 8509 ArrayRef<const char *> getGCCRegNames() const override { 8510 static const char * const GCCRegNames[] = { 8511 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8512 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8513 }; 8514 return llvm::makeArrayRef(GCCRegNames); 8515 } 8516 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8517 return None; 8518 } 8519 bool validateAsmConstraint(const char *&Name, 8520 TargetInfo::ConstraintInfo &Info) const override { 8521 return false; 8522 } 8523 int getEHDataRegisterNumber(unsigned RegNo) const override { 8524 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8525 return (RegNo < 2)? RegNo : -1; 8526 } 8527 bool allowsLargerPreferedTypeAlignment() const override { 8528 return false; 8529 } 8530 }; 8531 8532 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8533 #define BUILTIN(ID, TYPE, ATTRS) \ 8534 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8535 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8536 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8537 #include "clang/Basic/BuiltinsXCore.def" 8538 }; 8539 8540 // x86_32 Android target 8541 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8542 public: 8543 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8544 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8545 SuitableAlign = 32; 8546 LongDoubleWidth = 64; 8547 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8548 } 8549 }; 8550 8551 // x86_64 Android target 8552 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8553 public: 8554 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8555 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8556 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8557 } 8558 8559 bool useFloat128ManglingForLongDouble() const override { 8560 return true; 8561 } 8562 }; 8563 8564 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8565 class RenderScript32TargetInfo : public ARMleTargetInfo { 8566 public: 8567 RenderScript32TargetInfo(const llvm::Triple &Triple, 8568 const TargetOptions &Opts) 8569 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8570 Triple.getOSName(), 8571 Triple.getEnvironmentName()), 8572 Opts) { 8573 IsRenderScriptTarget = true; 8574 LongWidth = LongAlign = 64; 8575 } 8576 void getTargetDefines(const LangOptions &Opts, 8577 MacroBuilder &Builder) const override { 8578 Builder.defineMacro("__RENDERSCRIPT__"); 8579 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8580 } 8581 }; 8582 8583 // 64-bit RenderScript is aarch64 8584 class RenderScript64TargetInfo : public AArch64leTargetInfo { 8585 public: 8586 RenderScript64TargetInfo(const llvm::Triple &Triple, 8587 const TargetOptions &Opts) 8588 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 8589 Triple.getOSName(), 8590 Triple.getEnvironmentName()), 8591 Opts) { 8592 IsRenderScriptTarget = true; 8593 } 8594 8595 void getTargetDefines(const LangOptions &Opts, 8596 MacroBuilder &Builder) const override { 8597 Builder.defineMacro("__RENDERSCRIPT__"); 8598 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 8599 } 8600 }; 8601 8602 /// Information about a specific microcontroller. 8603 struct MCUInfo { 8604 const char *Name; 8605 const char *DefineName; 8606 }; 8607 8608 // This list should be kept up-to-date with AVRDevices.td in LLVM. 8609 static ArrayRef<MCUInfo> AVRMcus = { 8610 { "at90s1200", "__AVR_AT90S1200__" }, 8611 { "attiny11", "__AVR_ATtiny11__" }, 8612 { "attiny12", "__AVR_ATtiny12__" }, 8613 { "attiny15", "__AVR_ATtiny15__" }, 8614 { "attiny28", "__AVR_ATtiny28__" }, 8615 { "at90s2313", "__AVR_AT90S2313__" }, 8616 { "at90s2323", "__AVR_AT90S2323__" }, 8617 { "at90s2333", "__AVR_AT90S2333__" }, 8618 { "at90s2343", "__AVR_AT90S2343__" }, 8619 { "attiny22", "__AVR_ATtiny22__" }, 8620 { "attiny26", "__AVR_ATtiny26__" }, 8621 { "at86rf401", "__AVR_AT86RF401__" }, 8622 { "at90s4414", "__AVR_AT90S4414__" }, 8623 { "at90s4433", "__AVR_AT90S4433__" }, 8624 { "at90s4434", "__AVR_AT90S4434__" }, 8625 { "at90s8515", "__AVR_AT90S8515__" }, 8626 { "at90c8534", "__AVR_AT90c8534__" }, 8627 { "at90s8535", "__AVR_AT90S8535__" }, 8628 { "ata5272", "__AVR_ATA5272__" }, 8629 { "attiny13", "__AVR_ATtiny13__" }, 8630 { "attiny13a", "__AVR_ATtiny13A__" }, 8631 { "attiny2313", "__AVR_ATtiny2313__" }, 8632 { "attiny2313a", "__AVR_ATtiny2313A__" }, 8633 { "attiny24", "__AVR_ATtiny24__" }, 8634 { "attiny24a", "__AVR_ATtiny24A__" }, 8635 { "attiny4313", "__AVR_ATtiny4313__" }, 8636 { "attiny44", "__AVR_ATtiny44__" }, 8637 { "attiny44a", "__AVR_ATtiny44A__" }, 8638 { "attiny84", "__AVR_ATtiny84__" }, 8639 { "attiny84a", "__AVR_ATtiny84A__" }, 8640 { "attiny25", "__AVR_ATtiny25__" }, 8641 { "attiny45", "__AVR_ATtiny45__" }, 8642 { "attiny85", "__AVR_ATtiny85__" }, 8643 { "attiny261", "__AVR_ATtiny261__" }, 8644 { "attiny261a", "__AVR_ATtiny261A__" }, 8645 { "attiny461", "__AVR_ATtiny461__" }, 8646 { "attiny461a", "__AVR_ATtiny461A__" }, 8647 { "attiny861", "__AVR_ATtiny861__" }, 8648 { "attiny861a", "__AVR_ATtiny861A__" }, 8649 { "attiny87", "__AVR_ATtiny87__" }, 8650 { "attiny43u", "__AVR_ATtiny43U__" }, 8651 { "attiny48", "__AVR_ATtiny48__" }, 8652 { "attiny88", "__AVR_ATtiny88__" }, 8653 { "attiny828", "__AVR_ATtiny828__" }, 8654 { "at43usb355", "__AVR_AT43USB355__" }, 8655 { "at76c711", "__AVR_AT76C711__" }, 8656 { "atmega103", "__AVR_ATmega103__" }, 8657 { "at43usb320", "__AVR_AT43USB320__" }, 8658 { "attiny167", "__AVR_ATtiny167__" }, 8659 { "at90usb82", "__AVR_AT90USB82__" }, 8660 { "at90usb162", "__AVR_AT90USB162__" }, 8661 { "ata5505", "__AVR_ATA5505__" }, 8662 { "atmega8u2", "__AVR_ATmega8U2__" }, 8663 { "atmega16u2", "__AVR_ATmega16U2__" }, 8664 { "atmega32u2", "__AVR_ATmega32U2__" }, 8665 { "attiny1634", "__AVR_ATtiny1634__" }, 8666 { "atmega8", "__AVR_ATmega8__" }, 8667 { "ata6289", "__AVR_ATA6289__" }, 8668 { "atmega8a", "__AVR_ATmega8A__" }, 8669 { "ata6285", "__AVR_ATA6285__" }, 8670 { "ata6286", "__AVR_ATA6286__" }, 8671 { "atmega48", "__AVR_ATmega48__" }, 8672 { "atmega48a", "__AVR_ATmega48A__" }, 8673 { "atmega48pa", "__AVR_ATmega48PA__" }, 8674 { "atmega48p", "__AVR_ATmega48P__" }, 8675 { "atmega88", "__AVR_ATmega88__" }, 8676 { "atmega88a", "__AVR_ATmega88A__" }, 8677 { "atmega88p", "__AVR_ATmega88P__" }, 8678 { "atmega88pa", "__AVR_ATmega88PA__" }, 8679 { "atmega8515", "__AVR_ATmega8515__" }, 8680 { "atmega8535", "__AVR_ATmega8535__" }, 8681 { "atmega8hva", "__AVR_ATmega8HVA__" }, 8682 { "at90pwm1", "__AVR_AT90PWM1__" }, 8683 { "at90pwm2", "__AVR_AT90PWM2__" }, 8684 { "at90pwm2b", "__AVR_AT90PWM2B__" }, 8685 { "at90pwm3", "__AVR_AT90PWM3__" }, 8686 { "at90pwm3b", "__AVR_AT90PWM3B__" }, 8687 { "at90pwm81", "__AVR_AT90PWM81__" }, 8688 { "ata5790", "__AVR_ATA5790__" }, 8689 { "ata5795", "__AVR_ATA5795__" }, 8690 { "atmega16", "__AVR_ATmega16__" }, 8691 { "atmega16a", "__AVR_ATmega16A__" }, 8692 { "atmega161", "__AVR_ATmega161__" }, 8693 { "atmega162", "__AVR_ATmega162__" }, 8694 { "atmega163", "__AVR_ATmega163__" }, 8695 { "atmega164a", "__AVR_ATmega164A__" }, 8696 { "atmega164p", "__AVR_ATmega164P__" }, 8697 { "atmega164pa", "__AVR_ATmega164PA__" }, 8698 { "atmega165", "__AVR_ATmega165__" }, 8699 { "atmega165a", "__AVR_ATmega165A__" }, 8700 { "atmega165p", "__AVR_ATmega165P__" }, 8701 { "atmega165pa", "__AVR_ATmega165PA__" }, 8702 { "atmega168", "__AVR_ATmega168__" }, 8703 { "atmega168a", "__AVR_ATmega168A__" }, 8704 { "atmega168p", "__AVR_ATmega168P__" }, 8705 { "atmega168pa", "__AVR_ATmega168PA__" }, 8706 { "atmega169", "__AVR_ATmega169__" }, 8707 { "atmega169a", "__AVR_ATmega169A__" }, 8708 { "atmega169p", "__AVR_ATmega169P__" }, 8709 { "atmega169pa", "__AVR_ATmega169PA__" }, 8710 { "atmega32", "__AVR_ATmega32__" }, 8711 { "atmega32a", "__AVR_ATmega32A__" }, 8712 { "atmega323", "__AVR_ATmega323__" }, 8713 { "atmega324a", "__AVR_ATmega324A__" }, 8714 { "atmega324p", "__AVR_ATmega324P__" }, 8715 { "atmega324pa", "__AVR_ATmega324PA__" }, 8716 { "atmega325", "__AVR_ATmega325__" }, 8717 { "atmega325a", "__AVR_ATmega325A__" }, 8718 { "atmega325p", "__AVR_ATmega325P__" }, 8719 { "atmega325pa", "__AVR_ATmega325PA__" }, 8720 { "atmega3250", "__AVR_ATmega3250__" }, 8721 { "atmega3250a", "__AVR_ATmega3250A__" }, 8722 { "atmega3250p", "__AVR_ATmega3250P__" }, 8723 { "atmega3250pa", "__AVR_ATmega3250PA__" }, 8724 { "atmega328", "__AVR_ATmega328__" }, 8725 { "atmega328p", "__AVR_ATmega328P__" }, 8726 { "atmega329", "__AVR_ATmega329__" }, 8727 { "atmega329a", "__AVR_ATmega329A__" }, 8728 { "atmega329p", "__AVR_ATmega329P__" }, 8729 { "atmega329pa", "__AVR_ATmega329PA__" }, 8730 { "atmega3290", "__AVR_ATmega3290__" }, 8731 { "atmega3290a", "__AVR_ATmega3290A__" }, 8732 { "atmega3290p", "__AVR_ATmega3290P__" }, 8733 { "atmega3290pa", "__AVR_ATmega3290PA__" }, 8734 { "atmega406", "__AVR_ATmega406__" }, 8735 { "atmega64", "__AVR_ATmega64__" }, 8736 { "atmega64a", "__AVR_ATmega64A__" }, 8737 { "atmega640", "__AVR_ATmega640__" }, 8738 { "atmega644", "__AVR_ATmega644__" }, 8739 { "atmega644a", "__AVR_ATmega644A__" }, 8740 { "atmega644p", "__AVR_ATmega644P__" }, 8741 { "atmega644pa", "__AVR_ATmega644PA__" }, 8742 { "atmega645", "__AVR_ATmega645__" }, 8743 { "atmega645a", "__AVR_ATmega645A__" }, 8744 { "atmega645p", "__AVR_ATmega645P__" }, 8745 { "atmega649", "__AVR_ATmega649__" }, 8746 { "atmega649a", "__AVR_ATmega649A__" }, 8747 { "atmega649p", "__AVR_ATmega649P__" }, 8748 { "atmega6450", "__AVR_ATmega6450__" }, 8749 { "atmega6450a", "__AVR_ATmega6450A__" }, 8750 { "atmega6450p", "__AVR_ATmega6450P__" }, 8751 { "atmega6490", "__AVR_ATmega6490__" }, 8752 { "atmega6490a", "__AVR_ATmega6490A__" }, 8753 { "atmega6490p", "__AVR_ATmega6490P__" }, 8754 { "atmega64rfr2", "__AVR_ATmega64RFR2__" }, 8755 { "atmega644rfr2", "__AVR_ATmega644RFR2__" }, 8756 { "atmega16hva", "__AVR_ATmega16HVA__" }, 8757 { "atmega16hva2", "__AVR_ATmega16HVA2__" }, 8758 { "atmega16hvb", "__AVR_ATmega16HVB__" }, 8759 { "atmega16hvbrevb", "__AVR_ATmega16HVBREVB__" }, 8760 { "atmega32hvb", "__AVR_ATmega32HVB__" }, 8761 { "atmega32hvbrevb", "__AVR_ATmega32HVBREVB__" }, 8762 { "atmega64hve", "__AVR_ATmega64HVE__" }, 8763 { "at90can32", "__AVR_AT90CAN32__" }, 8764 { "at90can64", "__AVR_AT90CAN64__" }, 8765 { "at90pwm161", "__AVR_AT90PWM161__" }, 8766 { "at90pwm216", "__AVR_AT90PWM216__" }, 8767 { "at90pwm316", "__AVR_AT90PWM316__" }, 8768 { "atmega32c1", "__AVR_ATmega32C1__" }, 8769 { "atmega64c1", "__AVR_ATmega64C1__" }, 8770 { "atmega16m1", "__AVR_ATmega16M1__" }, 8771 { "atmega32m1", "__AVR_ATmega32M1__" }, 8772 { "atmega64m1", "__AVR_ATmega64M1__" }, 8773 { "atmega16u4", "__AVR_ATmega16U4__" }, 8774 { "atmega32u4", "__AVR_ATmega32U4__" }, 8775 { "atmega32u6", "__AVR_ATmega32U6__" }, 8776 { "at90usb646", "__AVR_AT90USB646__" }, 8777 { "at90usb647", "__AVR_AT90USB647__" }, 8778 { "at90scr100", "__AVR_AT90SCR100__" }, 8779 { "at94k", "__AVR_AT94K__" }, 8780 { "m3000", "__AVR_AT000__" }, 8781 { "atmega128", "__AVR_ATmega128__" }, 8782 { "atmega128a", "__AVR_ATmega128A__" }, 8783 { "atmega1280", "__AVR_ATmega1280__" }, 8784 { "atmega1281", "__AVR_ATmega1281__" }, 8785 { "atmega1284", "__AVR_ATmega1284__" }, 8786 { "atmega1284p", "__AVR_ATmega1284P__" }, 8787 { "atmega128rfa1", "__AVR_ATmega128RFA1__" }, 8788 { "atmega128rfr2", "__AVR_ATmega128RFR2__" }, 8789 { "atmega1284rfr2", "__AVR_ATmega1284RFR2__" }, 8790 { "at90can128", "__AVR_AT90CAN128__" }, 8791 { "at90usb1286", "__AVR_AT90USB1286__" }, 8792 { "at90usb1287", "__AVR_AT90USB1287__" }, 8793 { "atmega2560", "__AVR_ATmega2560__" }, 8794 { "atmega2561", "__AVR_ATmega2561__" }, 8795 { "atmega256rfr2", "__AVR_ATmega256RFR2__" }, 8796 { "atmega2564rfr2", "__AVR_ATmega2564RFR2__" }, 8797 { "atxmega16a4", "__AVR_ATxmega16A4__" }, 8798 { "atxmega16a4u", "__AVR_ATxmega16a4U__" }, 8799 { "atxmega16c4", "__AVR_ATxmega16C4__" }, 8800 { "atxmega16d4", "__AVR_ATxmega16D4__" }, 8801 { "atxmega32a4", "__AVR_ATxmega32A4__" }, 8802 { "atxmega32a4u", "__AVR_ATxmega32A4U__" }, 8803 { "atxmega32c4", "__AVR_ATxmega32C4__" }, 8804 { "atxmega32d4", "__AVR_ATxmega32D4__" }, 8805 { "atxmega32e5", "__AVR_ATxmega32E5__" }, 8806 { "atxmega16e5", "__AVR_ATxmega16E5__" }, 8807 { "atxmega8e5", "__AVR_ATxmega8E5__" }, 8808 { "atxmega32x1", "__AVR_ATxmega32X1__" }, 8809 { "atxmega64a3", "__AVR_ATxmega64A3__" }, 8810 { "atxmega64a3u", "__AVR_ATxmega64A3U__" }, 8811 { "atxmega64a4u", "__AVR_ATxmega64A4U__" }, 8812 { "atxmega64b1", "__AVR_ATxmega64B1__" }, 8813 { "atxmega64b3", "__AVR_ATxmega64B3__" }, 8814 { "atxmega64c3", "__AVR_ATxmega64C3__" }, 8815 { "atxmega64d3", "__AVR_ATxmega64D3__" }, 8816 { "atxmega64d4", "__AVR_ATxmega64D4__" }, 8817 { "atxmega64a1", "__AVR_ATxmega64A1__" }, 8818 { "atxmega64a1u", "__AVR_ATxmega64A1U__" }, 8819 { "atxmega128a3", "__AVR_ATxmega128A3__" }, 8820 { "atxmega128a3u", "__AVR_ATxmega128A3U__" }, 8821 { "atxmega128b1", "__AVR_ATxmega128B1__" }, 8822 { "atxmega128b3", "__AVR_ATxmega128B3__" }, 8823 { "atxmega128c3", "__AVR_ATxmega128C3__" }, 8824 { "atxmega128d3", "__AVR_ATxmega128D3__" }, 8825 { "atxmega128d4", "__AVR_ATxmega128D4__" }, 8826 { "atxmega192a3", "__AVR_ATxmega192A3__" }, 8827 { "atxmega192a3u", "__AVR_ATxmega192A3U__" }, 8828 { "atxmega192c3", "__AVR_ATxmega192C3__" }, 8829 { "atxmega192d3", "__AVR_ATxmega192D3__" }, 8830 { "atxmega256a3", "__AVR_ATxmega256A3__" }, 8831 { "atxmega256a3u", "__AVR_ATxmega256A3U__" }, 8832 { "atxmega256a3b", "__AVR_ATxmega256A3B__" }, 8833 { "atxmega256a3bu", "__AVR_ATxmega256A3BU__" }, 8834 { "atxmega256c3", "__AVR_ATxmega256C3__" }, 8835 { "atxmega256d3", "__AVR_ATxmega256D3__" }, 8836 { "atxmega384c3", "__AVR_ATxmega384C3__" }, 8837 { "atxmega384d3", "__AVR_ATxmega384D3__" }, 8838 { "atxmega128a1", "__AVR_ATxmega128A1__" }, 8839 { "atxmega128a1u", "__AVR_ATxmega128A1U__" }, 8840 { "atxmega128a4u", "__AVR_ATxmega128a4U__" }, 8841 { "attiny4", "__AVR_ATtiny4__" }, 8842 { "attiny5", "__AVR_ATtiny5__" }, 8843 { "attiny9", "__AVR_ATtiny9__" }, 8844 { "attiny10", "__AVR_ATtiny10__" }, 8845 { "attiny20", "__AVR_ATtiny20__" }, 8846 { "attiny40", "__AVR_ATtiny40__" }, 8847 { "attiny102", "__AVR_ATtiny102__" }, 8848 { "attiny104", "__AVR_ATtiny104__" }, 8849 }; 8850 8851 // AVR Target 8852 class AVRTargetInfo : public TargetInfo { 8853 public: 8854 AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8855 : TargetInfo(Triple) { 8856 TLSSupported = false; 8857 PointerWidth = 16; 8858 PointerAlign = 8; 8859 IntWidth = 16; 8860 IntAlign = 8; 8861 LongWidth = 32; 8862 LongAlign = 8; 8863 LongLongWidth = 64; 8864 LongLongAlign = 8; 8865 SuitableAlign = 8; 8866 DefaultAlignForAttributeAligned = 8; 8867 HalfWidth = 16; 8868 HalfAlign = 8; 8869 FloatWidth = 32; 8870 FloatAlign = 8; 8871 DoubleWidth = 32; 8872 DoubleAlign = 8; 8873 DoubleFormat = &llvm::APFloat::IEEEsingle(); 8874 LongDoubleWidth = 32; 8875 LongDoubleAlign = 8; 8876 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 8877 SizeType = UnsignedInt; 8878 PtrDiffType = SignedInt; 8879 IntPtrType = SignedInt; 8880 Char16Type = UnsignedInt; 8881 WCharType = SignedInt; 8882 WIntType = SignedInt; 8883 Char32Type = UnsignedLong; 8884 SigAtomicType = SignedChar; 8885 resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64" 8886 "-f32:32:32-f64:64:64-n8"); 8887 } 8888 8889 void getTargetDefines(const LangOptions &Opts, 8890 MacroBuilder &Builder) const override { 8891 Builder.defineMacro("AVR"); 8892 Builder.defineMacro("__AVR"); 8893 Builder.defineMacro("__AVR__"); 8894 8895 if (!this->CPU.empty()) { 8896 auto It = std::find_if(AVRMcus.begin(), AVRMcus.end(), 8897 [&](const MCUInfo &Info) { return Info.Name == this->CPU; }); 8898 8899 if (It != AVRMcus.end()) 8900 Builder.defineMacro(It->DefineName); 8901 } 8902 } 8903 8904 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8905 return None; 8906 } 8907 8908 BuiltinVaListKind getBuiltinVaListKind() const override { 8909 return TargetInfo::VoidPtrBuiltinVaList; 8910 } 8911 8912 const char *getClobbers() const override { 8913 return ""; 8914 } 8915 8916 ArrayRef<const char *> getGCCRegNames() const override { 8917 static const char * const GCCRegNames[] = { 8918 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8919 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 8920 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 8921 "r24", "r25", "X", "Y", "Z", "SP" 8922 }; 8923 return llvm::makeArrayRef(GCCRegNames); 8924 } 8925 8926 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8927 return None; 8928 } 8929 8930 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 8931 static const TargetInfo::AddlRegName AddlRegNames[] = { 8932 { { "r26", "r27"}, 26 }, 8933 { { "r28", "r29"}, 27 }, 8934 { { "r30", "r31"}, 28 }, 8935 { { "SPL", "SPH"}, 29 }, 8936 }; 8937 return llvm::makeArrayRef(AddlRegNames); 8938 } 8939 8940 bool validateAsmConstraint(const char *&Name, 8941 TargetInfo::ConstraintInfo &Info) const override { 8942 // There aren't any multi-character AVR specific constraints. 8943 if (StringRef(Name).size() > 1) return false; 8944 8945 switch (*Name) { 8946 default: return false; 8947 case 'a': // Simple upper registers 8948 case 'b': // Base pointer registers pairs 8949 case 'd': // Upper register 8950 case 'l': // Lower registers 8951 case 'e': // Pointer register pairs 8952 case 'q': // Stack pointer register 8953 case 'r': // Any register 8954 case 'w': // Special upper register pairs 8955 case 't': // Temporary register 8956 case 'x': case 'X': // Pointer register pair X 8957 case 'y': case 'Y': // Pointer register pair Y 8958 case 'z': case 'Z': // Pointer register pair Z 8959 Info.setAllowsRegister(); 8960 return true; 8961 case 'I': // 6-bit positive integer constant 8962 Info.setRequiresImmediate(0, 63); 8963 return true; 8964 case 'J': // 6-bit negative integer constant 8965 Info.setRequiresImmediate(-63, 0); 8966 return true; 8967 case 'K': // Integer constant (Range: 2) 8968 Info.setRequiresImmediate(2); 8969 return true; 8970 case 'L': // Integer constant (Range: 0) 8971 Info.setRequiresImmediate(0); 8972 return true; 8973 case 'M': // 8-bit integer constant 8974 Info.setRequiresImmediate(0, 0xff); 8975 return true; 8976 case 'N': // Integer constant (Range: -1) 8977 Info.setRequiresImmediate(-1); 8978 return true; 8979 case 'O': // Integer constant (Range: 8, 16, 24) 8980 Info.setRequiresImmediate({8, 16, 24}); 8981 return true; 8982 case 'P': // Integer constant (Range: 1) 8983 Info.setRequiresImmediate(1); 8984 return true; 8985 case 'R': // Integer constant (Range: -6 to 5) 8986 Info.setRequiresImmediate(-6, 5); 8987 return true; 8988 case 'G': // Floating point constant 8989 case 'Q': // A memory address based on Y or Z pointer with displacement. 8990 return true; 8991 } 8992 8993 return false; 8994 } 8995 8996 IntType getIntTypeByWidth(unsigned BitWidth, 8997 bool IsSigned) const final { 8998 // AVR prefers int for 16-bit integers. 8999 return BitWidth == 16 ? (IsSigned ? SignedInt : UnsignedInt) 9000 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 9001 } 9002 9003 IntType getLeastIntTypeByWidth(unsigned BitWidth, 9004 bool IsSigned) const final { 9005 // AVR uses int for int_least16_t and int_fast16_t. 9006 return BitWidth == 16 9007 ? (IsSigned ? SignedInt : UnsignedInt) 9008 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 9009 } 9010 9011 bool setCPU(const std::string &Name) override { 9012 bool IsFamily = llvm::StringSwitch<bool>(Name) 9013 .Case("avr1", true) 9014 .Case("avr2", true) 9015 .Case("avr25", true) 9016 .Case("avr3", true) 9017 .Case("avr31", true) 9018 .Case("avr35", true) 9019 .Case("avr4", true) 9020 .Case("avr5", true) 9021 .Case("avr51", true) 9022 .Case("avr6", true) 9023 .Case("avrxmega1", true) 9024 .Case("avrxmega2", true) 9025 .Case("avrxmega3", true) 9026 .Case("avrxmega4", true) 9027 .Case("avrxmega5", true) 9028 .Case("avrxmega6", true) 9029 .Case("avrxmega7", true) 9030 .Case("avrtiny", true) 9031 .Default(false); 9032 9033 if (IsFamily) this->CPU = Name; 9034 9035 bool IsMCU = std::find_if(AVRMcus.begin(), AVRMcus.end(), 9036 [&](const MCUInfo &Info) { return Info.Name == Name; }) != AVRMcus.end(); 9037 9038 if (IsMCU) this->CPU = Name; 9039 9040 return IsFamily || IsMCU; 9041 } 9042 9043 protected: 9044 std::string CPU; 9045 }; 9046 9047 } // end anonymous namespace 9048 9049 //===----------------------------------------------------------------------===// 9050 // Driver code 9051 //===----------------------------------------------------------------------===// 9052 9053 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 9054 const TargetOptions &Opts) { 9055 llvm::Triple::OSType os = Triple.getOS(); 9056 9057 switch (Triple.getArch()) { 9058 default: 9059 return nullptr; 9060 9061 case llvm::Triple::xcore: 9062 return new XCoreTargetInfo(Triple, Opts); 9063 9064 case llvm::Triple::hexagon: 9065 return new HexagonTargetInfo(Triple, Opts); 9066 9067 case llvm::Triple::lanai: 9068 return new LanaiTargetInfo(Triple, Opts); 9069 9070 case llvm::Triple::aarch64: 9071 if (Triple.isOSDarwin()) 9072 return new DarwinAArch64TargetInfo(Triple, Opts); 9073 9074 switch (os) { 9075 case llvm::Triple::CloudABI: 9076 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 9077 case llvm::Triple::FreeBSD: 9078 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9079 case llvm::Triple::Fuchsia: 9080 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9081 case llvm::Triple::Linux: 9082 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9083 case llvm::Triple::NetBSD: 9084 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9085 case llvm::Triple::OpenBSD: 9086 return new OpenBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9087 default: 9088 return new AArch64leTargetInfo(Triple, Opts); 9089 } 9090 9091 case llvm::Triple::aarch64_be: 9092 switch (os) { 9093 case llvm::Triple::FreeBSD: 9094 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9095 case llvm::Triple::Fuchsia: 9096 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9097 case llvm::Triple::Linux: 9098 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9099 case llvm::Triple::NetBSD: 9100 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9101 default: 9102 return new AArch64beTargetInfo(Triple, Opts); 9103 } 9104 9105 case llvm::Triple::arm: 9106 case llvm::Triple::thumb: 9107 if (Triple.isOSBinFormatMachO()) 9108 return new DarwinARMTargetInfo(Triple, Opts); 9109 9110 switch (os) { 9111 case llvm::Triple::CloudABI: 9112 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts); 9113 case llvm::Triple::Linux: 9114 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 9115 case llvm::Triple::FreeBSD: 9116 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9117 case llvm::Triple::NetBSD: 9118 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9119 case llvm::Triple::OpenBSD: 9120 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9121 case llvm::Triple::Bitrig: 9122 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 9123 case llvm::Triple::RTEMS: 9124 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 9125 case llvm::Triple::NaCl: 9126 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 9127 case llvm::Triple::Win32: 9128 switch (Triple.getEnvironment()) { 9129 case llvm::Triple::Cygnus: 9130 return new CygwinARMTargetInfo(Triple, Opts); 9131 case llvm::Triple::GNU: 9132 return new MinGWARMTargetInfo(Triple, Opts); 9133 case llvm::Triple::Itanium: 9134 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 9135 case llvm::Triple::MSVC: 9136 default: // Assume MSVC for unknown environments 9137 return new MicrosoftARMleTargetInfo(Triple, Opts); 9138 } 9139 default: 9140 return new ARMleTargetInfo(Triple, Opts); 9141 } 9142 9143 case llvm::Triple::armeb: 9144 case llvm::Triple::thumbeb: 9145 if (Triple.isOSDarwin()) 9146 return new DarwinARMTargetInfo(Triple, Opts); 9147 9148 switch (os) { 9149 case llvm::Triple::Linux: 9150 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9151 case llvm::Triple::FreeBSD: 9152 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9153 case llvm::Triple::NetBSD: 9154 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9155 case llvm::Triple::OpenBSD: 9156 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9157 case llvm::Triple::Bitrig: 9158 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9159 case llvm::Triple::RTEMS: 9160 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9161 case llvm::Triple::NaCl: 9162 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9163 default: 9164 return new ARMbeTargetInfo(Triple, Opts); 9165 } 9166 9167 case llvm::Triple::avr: 9168 return new AVRTargetInfo(Triple, Opts); 9169 case llvm::Triple::bpfeb: 9170 case llvm::Triple::bpfel: 9171 return new BPFTargetInfo(Triple, Opts); 9172 9173 case llvm::Triple::msp430: 9174 return new MSP430TargetInfo(Triple, Opts); 9175 9176 case llvm::Triple::mips: 9177 switch (os) { 9178 case llvm::Triple::Linux: 9179 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9180 case llvm::Triple::RTEMS: 9181 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9182 case llvm::Triple::FreeBSD: 9183 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9184 case llvm::Triple::NetBSD: 9185 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9186 default: 9187 return new MipsTargetInfo(Triple, Opts); 9188 } 9189 9190 case llvm::Triple::mipsel: 9191 switch (os) { 9192 case llvm::Triple::Linux: 9193 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9194 case llvm::Triple::RTEMS: 9195 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9196 case llvm::Triple::FreeBSD: 9197 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9198 case llvm::Triple::NetBSD: 9199 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9200 case llvm::Triple::NaCl: 9201 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 9202 default: 9203 return new MipsTargetInfo(Triple, Opts); 9204 } 9205 9206 case llvm::Triple::mips64: 9207 switch (os) { 9208 case llvm::Triple::Linux: 9209 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9210 case llvm::Triple::RTEMS: 9211 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9212 case llvm::Triple::FreeBSD: 9213 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9214 case llvm::Triple::NetBSD: 9215 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9216 case llvm::Triple::OpenBSD: 9217 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9218 default: 9219 return new MipsTargetInfo(Triple, Opts); 9220 } 9221 9222 case llvm::Triple::mips64el: 9223 switch (os) { 9224 case llvm::Triple::Linux: 9225 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9226 case llvm::Triple::RTEMS: 9227 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9228 case llvm::Triple::FreeBSD: 9229 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9230 case llvm::Triple::NetBSD: 9231 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9232 case llvm::Triple::OpenBSD: 9233 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9234 default: 9235 return new MipsTargetInfo(Triple, Opts); 9236 } 9237 9238 case llvm::Triple::le32: 9239 switch (os) { 9240 case llvm::Triple::NaCl: 9241 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 9242 default: 9243 return nullptr; 9244 } 9245 9246 case llvm::Triple::le64: 9247 return new Le64TargetInfo(Triple, Opts); 9248 9249 case llvm::Triple::ppc: 9250 if (Triple.isOSDarwin()) 9251 return new DarwinPPC32TargetInfo(Triple, Opts); 9252 switch (os) { 9253 case llvm::Triple::Linux: 9254 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 9255 case llvm::Triple::FreeBSD: 9256 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9257 case llvm::Triple::NetBSD: 9258 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9259 case llvm::Triple::OpenBSD: 9260 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9261 case llvm::Triple::RTEMS: 9262 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 9263 default: 9264 return new PPC32TargetInfo(Triple, Opts); 9265 } 9266 9267 case llvm::Triple::ppc64: 9268 if (Triple.isOSDarwin()) 9269 return new DarwinPPC64TargetInfo(Triple, Opts); 9270 switch (os) { 9271 case llvm::Triple::Linux: 9272 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9273 case llvm::Triple::Lv2: 9274 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 9275 case llvm::Triple::FreeBSD: 9276 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9277 case llvm::Triple::NetBSD: 9278 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9279 default: 9280 return new PPC64TargetInfo(Triple, Opts); 9281 } 9282 9283 case llvm::Triple::ppc64le: 9284 switch (os) { 9285 case llvm::Triple::Linux: 9286 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9287 case llvm::Triple::NetBSD: 9288 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9289 default: 9290 return new PPC64TargetInfo(Triple, Opts); 9291 } 9292 9293 case llvm::Triple::nvptx: 9294 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/32); 9295 case llvm::Triple::nvptx64: 9296 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64); 9297 9298 case llvm::Triple::amdgcn: 9299 case llvm::Triple::r600: 9300 return new AMDGPUTargetInfo(Triple, Opts); 9301 9302 case llvm::Triple::sparc: 9303 switch (os) { 9304 case llvm::Triple::Linux: 9305 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9306 case llvm::Triple::Solaris: 9307 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9308 case llvm::Triple::NetBSD: 9309 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9310 case llvm::Triple::OpenBSD: 9311 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9312 case llvm::Triple::RTEMS: 9313 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9314 default: 9315 return new SparcV8TargetInfo(Triple, Opts); 9316 } 9317 9318 // The 'sparcel' architecture copies all the above cases except for Solaris. 9319 case llvm::Triple::sparcel: 9320 switch (os) { 9321 case llvm::Triple::Linux: 9322 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9323 case llvm::Triple::NetBSD: 9324 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9325 case llvm::Triple::OpenBSD: 9326 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9327 case llvm::Triple::RTEMS: 9328 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9329 default: 9330 return new SparcV8elTargetInfo(Triple, Opts); 9331 } 9332 9333 case llvm::Triple::sparcv9: 9334 switch (os) { 9335 case llvm::Triple::Linux: 9336 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9337 case llvm::Triple::Solaris: 9338 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9339 case llvm::Triple::NetBSD: 9340 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9341 case llvm::Triple::OpenBSD: 9342 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9343 case llvm::Triple::FreeBSD: 9344 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9345 default: 9346 return new SparcV9TargetInfo(Triple, Opts); 9347 } 9348 9349 case llvm::Triple::systemz: 9350 switch (os) { 9351 case llvm::Triple::Linux: 9352 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 9353 default: 9354 return new SystemZTargetInfo(Triple, Opts); 9355 } 9356 9357 case llvm::Triple::tce: 9358 return new TCETargetInfo(Triple, Opts); 9359 9360 case llvm::Triple::tcele: 9361 return new TCELETargetInfo(Triple, Opts); 9362 9363 case llvm::Triple::x86: 9364 if (Triple.isOSDarwin()) 9365 return new DarwinI386TargetInfo(Triple, Opts); 9366 9367 switch (os) { 9368 case llvm::Triple::CloudABI: 9369 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 9370 case llvm::Triple::Linux: { 9371 switch (Triple.getEnvironment()) { 9372 default: 9373 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 9374 case llvm::Triple::Android: 9375 return new AndroidX86_32TargetInfo(Triple, Opts); 9376 } 9377 } 9378 case llvm::Triple::DragonFly: 9379 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9380 case llvm::Triple::NetBSD: 9381 return new NetBSDI386TargetInfo(Triple, Opts); 9382 case llvm::Triple::OpenBSD: 9383 return new OpenBSDI386TargetInfo(Triple, Opts); 9384 case llvm::Triple::Bitrig: 9385 return new BitrigI386TargetInfo(Triple, Opts); 9386 case llvm::Triple::FreeBSD: 9387 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9388 case llvm::Triple::KFreeBSD: 9389 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9390 case llvm::Triple::Minix: 9391 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 9392 case llvm::Triple::Solaris: 9393 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 9394 case llvm::Triple::Win32: { 9395 switch (Triple.getEnvironment()) { 9396 case llvm::Triple::Cygnus: 9397 return new CygwinX86_32TargetInfo(Triple, Opts); 9398 case llvm::Triple::GNU: 9399 return new MinGWX86_32TargetInfo(Triple, Opts); 9400 case llvm::Triple::Itanium: 9401 case llvm::Triple::MSVC: 9402 default: // Assume MSVC for unknown environments 9403 return new MicrosoftX86_32TargetInfo(Triple, Opts); 9404 } 9405 } 9406 case llvm::Triple::Haiku: 9407 return new HaikuX86_32TargetInfo(Triple, Opts); 9408 case llvm::Triple::RTEMS: 9409 return new RTEMSX86_32TargetInfo(Triple, Opts); 9410 case llvm::Triple::NaCl: 9411 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 9412 case llvm::Triple::ELFIAMCU: 9413 return new MCUX86_32TargetInfo(Triple, Opts); 9414 default: 9415 return new X86_32TargetInfo(Triple, Opts); 9416 } 9417 9418 case llvm::Triple::x86_64: 9419 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 9420 return new DarwinX86_64TargetInfo(Triple, Opts); 9421 9422 switch (os) { 9423 case llvm::Triple::CloudABI: 9424 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 9425 case llvm::Triple::Linux: { 9426 switch (Triple.getEnvironment()) { 9427 default: 9428 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 9429 case llvm::Triple::Android: 9430 return new AndroidX86_64TargetInfo(Triple, Opts); 9431 } 9432 } 9433 case llvm::Triple::DragonFly: 9434 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9435 case llvm::Triple::NetBSD: 9436 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9437 case llvm::Triple::OpenBSD: 9438 return new OpenBSDX86_64TargetInfo(Triple, Opts); 9439 case llvm::Triple::Bitrig: 9440 return new BitrigX86_64TargetInfo(Triple, Opts); 9441 case llvm::Triple::FreeBSD: 9442 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9443 case llvm::Triple::Fuchsia: 9444 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts); 9445 case llvm::Triple::KFreeBSD: 9446 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9447 case llvm::Triple::Solaris: 9448 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 9449 case llvm::Triple::Win32: { 9450 switch (Triple.getEnvironment()) { 9451 case llvm::Triple::Cygnus: 9452 return new CygwinX86_64TargetInfo(Triple, Opts); 9453 case llvm::Triple::GNU: 9454 return new MinGWX86_64TargetInfo(Triple, Opts); 9455 case llvm::Triple::MSVC: 9456 default: // Assume MSVC for unknown environments 9457 return new MicrosoftX86_64TargetInfo(Triple, Opts); 9458 } 9459 } 9460 case llvm::Triple::Haiku: 9461 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 9462 case llvm::Triple::NaCl: 9463 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 9464 case llvm::Triple::PS4: 9465 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 9466 default: 9467 return new X86_64TargetInfo(Triple, Opts); 9468 } 9469 9470 case llvm::Triple::spir: { 9471 if (Triple.getOS() != llvm::Triple::UnknownOS || 9472 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9473 return nullptr; 9474 return new SPIR32TargetInfo(Triple, Opts); 9475 } 9476 case llvm::Triple::spir64: { 9477 if (Triple.getOS() != llvm::Triple::UnknownOS || 9478 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9479 return nullptr; 9480 return new SPIR64TargetInfo(Triple, Opts); 9481 } 9482 case llvm::Triple::wasm32: 9483 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9484 Triple.getVendor() != llvm::Triple::UnknownVendor || 9485 Triple.getOS() != llvm::Triple::UnknownOS || 9486 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9487 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9488 return nullptr; 9489 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 9490 case llvm::Triple::wasm64: 9491 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9492 Triple.getVendor() != llvm::Triple::UnknownVendor || 9493 Triple.getOS() != llvm::Triple::UnknownOS || 9494 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9495 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9496 return nullptr; 9497 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 9498 9499 case llvm::Triple::renderscript32: 9500 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 9501 case llvm::Triple::renderscript64: 9502 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 9503 } 9504 } 9505 9506 /// CreateTargetInfo - Return the target info object for the specified target 9507 /// options. 9508 TargetInfo * 9509 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 9510 const std::shared_ptr<TargetOptions> &Opts) { 9511 llvm::Triple Triple(Opts->Triple); 9512 9513 // Construct the target 9514 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 9515 if (!Target) { 9516 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 9517 return nullptr; 9518 } 9519 Target->TargetOpts = Opts; 9520 9521 // Set the target CPU if specified. 9522 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 9523 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 9524 return nullptr; 9525 } 9526 9527 // Set the target ABI if specified. 9528 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 9529 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 9530 return nullptr; 9531 } 9532 9533 // Set the fp math unit. 9534 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 9535 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 9536 return nullptr; 9537 } 9538 9539 // Compute the default target features, we need the target to handle this 9540 // because features may have dependencies on one another. 9541 llvm::StringMap<bool> Features; 9542 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 9543 Opts->FeaturesAsWritten)) 9544 return nullptr; 9545 9546 // Add the features to the compile options. 9547 Opts->Features.clear(); 9548 for (const auto &F : Features) 9549 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 9550 9551 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 9552 return nullptr; 9553 9554 Target->setSupportedOpenCLOpts(); 9555 Target->setOpenCLExtensionOpts(); 9556 9557 if (!Target->validateTarget(Diags)) 9558 return nullptr; 9559 9560 return Target.release(); 9561 } 9562