1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "clang/Basic/Version.h" 23 #include "llvm/ADT/APFloat.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringExtras.h" 26 #include "llvm/ADT/StringRef.h" 27 #include "llvm/ADT/StringSwitch.h" 28 #include "llvm/ADT/Triple.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/TargetParser.h" 32 #include <algorithm> 33 #include <memory> 34 35 using namespace clang; 36 37 //===----------------------------------------------------------------------===// 38 // Common code shared among targets. 39 //===----------------------------------------------------------------------===// 40 41 /// DefineStd - Define a macro name and standard variants. For example if 42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 43 /// when in GNU mode. 44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 45 const LangOptions &Opts) { 46 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 47 48 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 49 // in the user's namespace. 50 if (Opts.GNUMode) 51 Builder.defineMacro(MacroName); 52 53 // Define __unix. 54 Builder.defineMacro("__" + MacroName); 55 56 // Define __unix__. 57 Builder.defineMacro("__" + MacroName + "__"); 58 } 59 60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 61 bool Tuning = true) { 62 Builder.defineMacro("__" + CPUName); 63 Builder.defineMacro("__" + CPUName + "__"); 64 if (Tuning) 65 Builder.defineMacro("__tune_" + CPUName + "__"); 66 } 67 68 //===----------------------------------------------------------------------===// 69 // Defines specific to certain operating systems. 70 //===----------------------------------------------------------------------===// 71 72 namespace { 73 template<typename TgtInfo> 74 class OSTargetInfo : public TgtInfo { 75 protected: 76 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 77 MacroBuilder &Builder) const=0; 78 public: 79 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 80 void getTargetDefines(const LangOptions &Opts, 81 MacroBuilder &Builder) const override { 82 TgtInfo::getTargetDefines(Opts, Builder); 83 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 84 } 85 86 }; 87 88 // CloudABI Target 89 template <typename Target> 90 class CloudABITargetInfo : public OSTargetInfo<Target> { 91 protected: 92 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 93 MacroBuilder &Builder) const override { 94 Builder.defineMacro("__CloudABI__"); 95 Builder.defineMacro("__ELF__"); 96 97 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 98 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 99 Builder.defineMacro("__STDC_UTF_16__"); 100 Builder.defineMacro("__STDC_UTF_32__"); 101 } 102 103 public: 104 CloudABITargetInfo(const llvm::Triple &Triple) 105 : OSTargetInfo<Target>(Triple) { 106 this->UserLabelPrefix = ""; 107 } 108 }; 109 110 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 111 const llvm::Triple &Triple, 112 StringRef &PlatformName, 113 VersionTuple &PlatformMinVersion) { 114 Builder.defineMacro("__APPLE_CC__", "6000"); 115 Builder.defineMacro("__APPLE__"); 116 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 117 // AddressSanitizer doesn't play well with source fortification, which is on 118 // by default on Darwin. 119 if (Opts.Sanitize.has(SanitizerKind::Address)) 120 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 121 122 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 123 if (!Opts.ObjC1) { 124 // __weak is always defined, for use in blocks and with objc pointers. 125 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 126 Builder.defineMacro("__strong", ""); 127 Builder.defineMacro("__unsafe_unretained", ""); 128 } 129 130 if (Opts.Static) 131 Builder.defineMacro("__STATIC__"); 132 else 133 Builder.defineMacro("__DYNAMIC__"); 134 135 if (Opts.POSIXThreads) 136 Builder.defineMacro("_REENTRANT"); 137 138 // Get the platform type and version number from the triple. 139 unsigned Maj, Min, Rev; 140 if (Triple.isMacOSX()) { 141 Triple.getMacOSXVersion(Maj, Min, Rev); 142 PlatformName = "macosx"; 143 } else { 144 Triple.getOSVersion(Maj, Min, Rev); 145 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 146 } 147 148 // If -target arch-pc-win32-macho option specified, we're 149 // generating code for Win32 ABI. No need to emit 150 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 151 if (PlatformName == "win32") { 152 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 153 return; 154 } 155 156 // Set the appropriate OS version define. 157 if (Triple.isiOS()) { 158 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 159 char Str[6]; 160 Str[0] = '0' + Maj; 161 Str[1] = '0' + (Min / 10); 162 Str[2] = '0' + (Min % 10); 163 Str[3] = '0' + (Rev / 10); 164 Str[4] = '0' + (Rev % 10); 165 Str[5] = '\0'; 166 if (Triple.isTvOS()) 167 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 168 else 169 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 170 Str); 171 172 } else if (Triple.isWatchOS()) { 173 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 174 char Str[6]; 175 Str[0] = '0' + Maj; 176 Str[1] = '0' + (Min / 10); 177 Str[2] = '0' + (Min % 10); 178 Str[3] = '0' + (Rev / 10); 179 Str[4] = '0' + (Rev % 10); 180 Str[5] = '\0'; 181 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 182 } else if (Triple.isMacOSX()) { 183 // Note that the Driver allows versions which aren't representable in the 184 // define (because we only get a single digit for the minor and micro 185 // revision numbers). So, we limit them to the maximum representable 186 // version. 187 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 188 char Str[7]; 189 if (Maj < 10 || (Maj == 10 && Min < 10)) { 190 Str[0] = '0' + (Maj / 10); 191 Str[1] = '0' + (Maj % 10); 192 Str[2] = '0' + std::min(Min, 9U); 193 Str[3] = '0' + std::min(Rev, 9U); 194 Str[4] = '\0'; 195 } else { 196 // Handle versions > 10.9. 197 Str[0] = '0' + (Maj / 10); 198 Str[1] = '0' + (Maj % 10); 199 Str[2] = '0' + (Min / 10); 200 Str[3] = '0' + (Min % 10); 201 Str[4] = '0' + (Rev / 10); 202 Str[5] = '0' + (Rev % 10); 203 Str[6] = '\0'; 204 } 205 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 206 } 207 208 // Tell users about the kernel if there is one. 209 if (Triple.isOSDarwin()) 210 Builder.defineMacro("__MACH__"); 211 212 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 213 } 214 215 template<typename Target> 216 class DarwinTargetInfo : public OSTargetInfo<Target> { 217 protected: 218 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 219 MacroBuilder &Builder) const override { 220 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 221 this->PlatformMinVersion); 222 } 223 224 public: 225 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 226 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 227 this->MCountName = "\01mcount"; 228 } 229 230 std::string isValidSectionSpecifier(StringRef SR) const override { 231 // Let MCSectionMachO validate this. 232 StringRef Segment, Section; 233 unsigned TAA, StubSize; 234 bool HasTAA; 235 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 236 TAA, HasTAA, StubSize); 237 } 238 239 const char *getStaticInitSectionSpecifier() const override { 240 // FIXME: We should return 0 when building kexts. 241 return "__TEXT,__StaticInit,regular,pure_instructions"; 242 } 243 244 /// Darwin does not support protected visibility. Darwin's "default" 245 /// is very similar to ELF's "protected"; Darwin requires a "weak" 246 /// attribute on declarations that can be dynamically replaced. 247 bool hasProtectedVisibility() const override { 248 return false; 249 } 250 }; 251 252 253 // DragonFlyBSD Target 254 template<typename Target> 255 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 256 protected: 257 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 258 MacroBuilder &Builder) const override { 259 // DragonFly defines; list based off of gcc output 260 Builder.defineMacro("__DragonFly__"); 261 Builder.defineMacro("__DragonFly_cc_version", "100001"); 262 Builder.defineMacro("__ELF__"); 263 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 264 Builder.defineMacro("__tune_i386__"); 265 DefineStd(Builder, "unix", Opts); 266 } 267 public: 268 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 269 : OSTargetInfo<Target>(Triple) { 270 this->UserLabelPrefix = ""; 271 272 switch (Triple.getArch()) { 273 default: 274 case llvm::Triple::x86: 275 case llvm::Triple::x86_64: 276 this->MCountName = ".mcount"; 277 break; 278 } 279 } 280 }; 281 282 // FreeBSD Target 283 template<typename Target> 284 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 285 protected: 286 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 287 MacroBuilder &Builder) const override { 288 // FreeBSD defines; list based off of gcc output 289 290 unsigned Release = Triple.getOSMajorVersion(); 291 if (Release == 0U) 292 Release = 8; 293 294 Builder.defineMacro("__FreeBSD__", Twine(Release)); 295 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 296 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 297 DefineStd(Builder, "unix", Opts); 298 Builder.defineMacro("__ELF__"); 299 300 // On FreeBSD, wchar_t contains the number of the code point as 301 // used by the character set of the locale. These character sets are 302 // not necessarily a superset of ASCII. 303 // 304 // FIXME: This is wrong; the macro refers to the numerical values 305 // of wchar_t *literals*, which are not locale-dependent. However, 306 // FreeBSD systems apparently depend on us getting this wrong, and 307 // setting this to 1 is conforming even if all the basic source 308 // character literals have the same encoding as char and wchar_t. 309 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 310 } 311 public: 312 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 313 this->UserLabelPrefix = ""; 314 315 switch (Triple.getArch()) { 316 default: 317 case llvm::Triple::x86: 318 case llvm::Triple::x86_64: 319 this->MCountName = ".mcount"; 320 break; 321 case llvm::Triple::mips: 322 case llvm::Triple::mipsel: 323 case llvm::Triple::ppc: 324 case llvm::Triple::ppc64: 325 case llvm::Triple::ppc64le: 326 this->MCountName = "_mcount"; 327 break; 328 case llvm::Triple::arm: 329 this->MCountName = "__mcount"; 330 break; 331 } 332 } 333 }; 334 335 // GNU/kFreeBSD Target 336 template<typename Target> 337 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 338 protected: 339 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 340 MacroBuilder &Builder) const override { 341 // GNU/kFreeBSD defines; list based off of gcc output 342 343 DefineStd(Builder, "unix", Opts); 344 Builder.defineMacro("__FreeBSD_kernel__"); 345 Builder.defineMacro("__GLIBC__"); 346 Builder.defineMacro("__ELF__"); 347 if (Opts.POSIXThreads) 348 Builder.defineMacro("_REENTRANT"); 349 if (Opts.CPlusPlus) 350 Builder.defineMacro("_GNU_SOURCE"); 351 } 352 public: 353 KFreeBSDTargetInfo(const llvm::Triple &Triple) 354 : OSTargetInfo<Target>(Triple) { 355 this->UserLabelPrefix = ""; 356 } 357 }; 358 359 // Minix Target 360 template<typename Target> 361 class MinixTargetInfo : public OSTargetInfo<Target> { 362 protected: 363 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 364 MacroBuilder &Builder) const override { 365 // Minix defines 366 367 Builder.defineMacro("__minix", "3"); 368 Builder.defineMacro("_EM_WSIZE", "4"); 369 Builder.defineMacro("_EM_PSIZE", "4"); 370 Builder.defineMacro("_EM_SSIZE", "2"); 371 Builder.defineMacro("_EM_LSIZE", "4"); 372 Builder.defineMacro("_EM_FSIZE", "4"); 373 Builder.defineMacro("_EM_DSIZE", "8"); 374 Builder.defineMacro("__ELF__"); 375 DefineStd(Builder, "unix", Opts); 376 } 377 public: 378 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 379 this->UserLabelPrefix = ""; 380 } 381 }; 382 383 // Linux target 384 template<typename Target> 385 class LinuxTargetInfo : public OSTargetInfo<Target> { 386 protected: 387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 388 MacroBuilder &Builder) const override { 389 // Linux defines; list based off of gcc output 390 DefineStd(Builder, "unix", Opts); 391 DefineStd(Builder, "linux", Opts); 392 Builder.defineMacro("__gnu_linux__"); 393 Builder.defineMacro("__ELF__"); 394 if (Triple.isAndroid()) { 395 Builder.defineMacro("__ANDROID__", "1"); 396 unsigned Maj, Min, Rev; 397 Triple.getEnvironmentVersion(Maj, Min, Rev); 398 this->PlatformName = "android"; 399 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 400 } 401 if (Opts.POSIXThreads) 402 Builder.defineMacro("_REENTRANT"); 403 if (Opts.CPlusPlus) 404 Builder.defineMacro("_GNU_SOURCE"); 405 } 406 public: 407 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 408 this->UserLabelPrefix = ""; 409 this->WIntType = TargetInfo::UnsignedInt; 410 411 switch (Triple.getArch()) { 412 default: 413 break; 414 case llvm::Triple::ppc: 415 case llvm::Triple::ppc64: 416 case llvm::Triple::ppc64le: 417 this->MCountName = "_mcount"; 418 break; 419 } 420 } 421 422 const char *getStaticInitSectionSpecifier() const override { 423 return ".text.startup"; 424 } 425 }; 426 427 // NetBSD Target 428 template<typename Target> 429 class NetBSDTargetInfo : public OSTargetInfo<Target> { 430 protected: 431 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 432 MacroBuilder &Builder) const override { 433 // NetBSD defines; list based off of gcc output 434 Builder.defineMacro("__NetBSD__"); 435 Builder.defineMacro("__unix__"); 436 Builder.defineMacro("__ELF__"); 437 if (Opts.POSIXThreads) 438 Builder.defineMacro("_POSIX_THREADS"); 439 440 switch (Triple.getArch()) { 441 default: 442 break; 443 case llvm::Triple::arm: 444 case llvm::Triple::armeb: 445 case llvm::Triple::thumb: 446 case llvm::Triple::thumbeb: 447 Builder.defineMacro("__ARM_DWARF_EH__"); 448 break; 449 } 450 } 451 public: 452 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 453 this->UserLabelPrefix = ""; 454 this->MCountName = "_mcount"; 455 } 456 }; 457 458 // OpenBSD Target 459 template<typename Target> 460 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 461 protected: 462 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 463 MacroBuilder &Builder) const override { 464 // OpenBSD defines; list based off of gcc output 465 466 Builder.defineMacro("__OpenBSD__"); 467 DefineStd(Builder, "unix", Opts); 468 Builder.defineMacro("__ELF__"); 469 if (Opts.POSIXThreads) 470 Builder.defineMacro("_REENTRANT"); 471 } 472 public: 473 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 474 this->UserLabelPrefix = ""; 475 this->TLSSupported = false; 476 477 switch (Triple.getArch()) { 478 default: 479 case llvm::Triple::x86: 480 case llvm::Triple::x86_64: 481 case llvm::Triple::arm: 482 case llvm::Triple::sparc: 483 this->MCountName = "__mcount"; 484 break; 485 case llvm::Triple::mips64: 486 case llvm::Triple::mips64el: 487 case llvm::Triple::ppc: 488 case llvm::Triple::sparcv9: 489 this->MCountName = "_mcount"; 490 break; 491 } 492 } 493 }; 494 495 // Bitrig Target 496 template<typename Target> 497 class BitrigTargetInfo : public OSTargetInfo<Target> { 498 protected: 499 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 500 MacroBuilder &Builder) const override { 501 // Bitrig defines; list based off of gcc output 502 503 Builder.defineMacro("__Bitrig__"); 504 DefineStd(Builder, "unix", Opts); 505 Builder.defineMacro("__ELF__"); 506 if (Opts.POSIXThreads) 507 Builder.defineMacro("_REENTRANT"); 508 509 switch (Triple.getArch()) { 510 default: 511 break; 512 case llvm::Triple::arm: 513 case llvm::Triple::armeb: 514 case llvm::Triple::thumb: 515 case llvm::Triple::thumbeb: 516 Builder.defineMacro("__ARM_DWARF_EH__"); 517 break; 518 } 519 } 520 public: 521 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 522 this->UserLabelPrefix = ""; 523 this->MCountName = "__mcount"; 524 } 525 }; 526 527 // PSP Target 528 template<typename Target> 529 class PSPTargetInfo : public OSTargetInfo<Target> { 530 protected: 531 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 532 MacroBuilder &Builder) const override { 533 // PSP defines; list based on the output of the pspdev gcc toolchain. 534 Builder.defineMacro("PSP"); 535 Builder.defineMacro("_PSP"); 536 Builder.defineMacro("__psp__"); 537 Builder.defineMacro("__ELF__"); 538 } 539 public: 540 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 541 this->UserLabelPrefix = ""; 542 } 543 }; 544 545 // PS3 PPU Target 546 template<typename Target> 547 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 548 protected: 549 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 550 MacroBuilder &Builder) const override { 551 // PS3 PPU defines. 552 Builder.defineMacro("__PPC__"); 553 Builder.defineMacro("__PPU__"); 554 Builder.defineMacro("__CELLOS_LV2__"); 555 Builder.defineMacro("__ELF__"); 556 Builder.defineMacro("__LP32__"); 557 Builder.defineMacro("_ARCH_PPC64"); 558 Builder.defineMacro("__powerpc64__"); 559 } 560 public: 561 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 562 this->UserLabelPrefix = ""; 563 this->LongWidth = this->LongAlign = 32; 564 this->PointerWidth = this->PointerAlign = 32; 565 this->IntMaxType = TargetInfo::SignedLongLong; 566 this->Int64Type = TargetInfo::SignedLongLong; 567 this->SizeType = TargetInfo::UnsignedInt; 568 this->DataLayoutString = "E-m:e-p:32:32-i64:64-n32:64"; 569 } 570 }; 571 572 template <typename Target> 573 class PS4OSTargetInfo : public OSTargetInfo<Target> { 574 protected: 575 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 576 MacroBuilder &Builder) const override { 577 Builder.defineMacro("__FreeBSD__", "9"); 578 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 579 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 580 DefineStd(Builder, "unix", Opts); 581 Builder.defineMacro("__ELF__"); 582 Builder.defineMacro("__PS4__"); 583 } 584 public: 585 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 586 this->WCharType = this->UnsignedShort; 587 588 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 589 this->MaxTLSAlign = 256; 590 this->UserLabelPrefix = ""; 591 592 switch (Triple.getArch()) { 593 default: 594 case llvm::Triple::x86_64: 595 this->MCountName = ".mcount"; 596 break; 597 } 598 } 599 }; 600 601 // Solaris target 602 template<typename Target> 603 class SolarisTargetInfo : public OSTargetInfo<Target> { 604 protected: 605 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 606 MacroBuilder &Builder) const override { 607 DefineStd(Builder, "sun", Opts); 608 DefineStd(Builder, "unix", Opts); 609 Builder.defineMacro("__ELF__"); 610 Builder.defineMacro("__svr4__"); 611 Builder.defineMacro("__SVR4"); 612 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 613 // newer, but to 500 for everything else. feature_test.h has a check to 614 // ensure that you are not using C99 with an old version of X/Open or C89 615 // with a new version. 616 if (Opts.C99) 617 Builder.defineMacro("_XOPEN_SOURCE", "600"); 618 else 619 Builder.defineMacro("_XOPEN_SOURCE", "500"); 620 if (Opts.CPlusPlus) 621 Builder.defineMacro("__C99FEATURES__"); 622 Builder.defineMacro("_LARGEFILE_SOURCE"); 623 Builder.defineMacro("_LARGEFILE64_SOURCE"); 624 Builder.defineMacro("__EXTENSIONS__"); 625 Builder.defineMacro("_REENTRANT"); 626 } 627 public: 628 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 629 this->UserLabelPrefix = ""; 630 this->WCharType = this->SignedInt; 631 // FIXME: WIntType should be SignedLong 632 } 633 }; 634 635 // Windows target 636 template<typename Target> 637 class WindowsTargetInfo : public OSTargetInfo<Target> { 638 protected: 639 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 640 MacroBuilder &Builder) const override { 641 Builder.defineMacro("_WIN32"); 642 } 643 void getVisualStudioDefines(const LangOptions &Opts, 644 MacroBuilder &Builder) const { 645 if (Opts.CPlusPlus) { 646 if (Opts.RTTIData) 647 Builder.defineMacro("_CPPRTTI"); 648 649 if (Opts.CXXExceptions) 650 Builder.defineMacro("_CPPUNWIND"); 651 } 652 653 if (Opts.Bool) 654 Builder.defineMacro("__BOOL_DEFINED"); 655 656 if (!Opts.CharIsSigned) 657 Builder.defineMacro("_CHAR_UNSIGNED"); 658 659 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 660 // but it works for now. 661 if (Opts.POSIXThreads) 662 Builder.defineMacro("_MT"); 663 664 if (Opts.MSCompatibilityVersion) { 665 Builder.defineMacro("_MSC_VER", 666 Twine(Opts.MSCompatibilityVersion / 100000)); 667 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 668 // FIXME We cannot encode the revision information into 32-bits 669 Builder.defineMacro("_MSC_BUILD", Twine(1)); 670 671 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 672 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 673 } 674 675 if (Opts.MicrosoftExt) { 676 Builder.defineMacro("_MSC_EXTENSIONS"); 677 678 if (Opts.CPlusPlus11) { 679 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 680 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 681 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 682 } 683 } 684 685 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 686 } 687 688 public: 689 WindowsTargetInfo(const llvm::Triple &Triple) 690 : OSTargetInfo<Target>(Triple) {} 691 }; 692 693 template <typename Target> 694 class NaClTargetInfo : public OSTargetInfo<Target> { 695 protected: 696 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 697 MacroBuilder &Builder) const override { 698 if (Opts.POSIXThreads) 699 Builder.defineMacro("_REENTRANT"); 700 if (Opts.CPlusPlus) 701 Builder.defineMacro("_GNU_SOURCE"); 702 703 DefineStd(Builder, "unix", Opts); 704 Builder.defineMacro("__ELF__"); 705 Builder.defineMacro("__native_client__"); 706 } 707 708 public: 709 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 710 this->UserLabelPrefix = ""; 711 this->LongAlign = 32; 712 this->LongWidth = 32; 713 this->PointerAlign = 32; 714 this->PointerWidth = 32; 715 this->IntMaxType = TargetInfo::SignedLongLong; 716 this->Int64Type = TargetInfo::SignedLongLong; 717 this->DoubleAlign = 64; 718 this->LongDoubleWidth = 64; 719 this->LongDoubleAlign = 64; 720 this->LongLongWidth = 64; 721 this->LongLongAlign = 64; 722 this->SizeType = TargetInfo::UnsignedInt; 723 this->PtrDiffType = TargetInfo::SignedInt; 724 this->IntPtrType = TargetInfo::SignedInt; 725 // RegParmMax is inherited from the underlying architecture 726 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 727 if (Triple.getArch() == llvm::Triple::arm) { 728 // Handled in ARM's setABI(). 729 } else if (Triple.getArch() == llvm::Triple::x86) { 730 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 731 } else if (Triple.getArch() == llvm::Triple::x86_64) { 732 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 733 } else if (Triple.getArch() == llvm::Triple::mipsel) { 734 // Handled on mips' setDataLayoutString. 735 } else { 736 assert(Triple.getArch() == llvm::Triple::le32); 737 this->DataLayoutString = "e-p:32:32-i64:64"; 738 } 739 } 740 }; 741 742 // WebAssembly target 743 template <typename Target> 744 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 745 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 746 MacroBuilder &Builder) const final { 747 // A common platform macro. 748 if (Opts.POSIXThreads) 749 Builder.defineMacro("_REENTRANT"); 750 // Follow g++ convention and predefine _GNU_SOURCE for C++. 751 if (Opts.CPlusPlus) 752 Builder.defineMacro("_GNU_SOURCE"); 753 } 754 755 // As an optimization, group static init code together in a section. 756 const char *getStaticInitSectionSpecifier() const final { 757 return ".text.__startup"; 758 } 759 760 public: 761 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple) 762 : OSTargetInfo<Target>(Triple) { 763 this->MCountName = "__mcount"; 764 this->UserLabelPrefix = ""; 765 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 766 } 767 }; 768 769 //===----------------------------------------------------------------------===// 770 // Specific target implementations. 771 //===----------------------------------------------------------------------===// 772 773 // PPC abstract base class 774 class PPCTargetInfo : public TargetInfo { 775 static const Builtin::Info BuiltinInfo[]; 776 static const char * const GCCRegNames[]; 777 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 778 std::string CPU; 779 780 // Target cpu features. 781 bool HasVSX; 782 bool HasP8Vector; 783 bool HasP8Crypto; 784 bool HasDirectMove; 785 bool HasQPX; 786 bool HasHTM; 787 bool HasBPERMD; 788 bool HasExtDiv; 789 790 protected: 791 std::string ABI; 792 793 public: 794 PPCTargetInfo(const llvm::Triple &Triple) 795 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 796 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 797 HasBPERMD(false), HasExtDiv(false) { 798 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 799 SimdDefaultAlign = 128; 800 LongDoubleWidth = LongDoubleAlign = 128; 801 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 802 } 803 804 /// \brief Flags for architecture specific defines. 805 typedef enum { 806 ArchDefineNone = 0, 807 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 808 ArchDefinePpcgr = 1 << 1, 809 ArchDefinePpcsq = 1 << 2, 810 ArchDefine440 = 1 << 3, 811 ArchDefine603 = 1 << 4, 812 ArchDefine604 = 1 << 5, 813 ArchDefinePwr4 = 1 << 6, 814 ArchDefinePwr5 = 1 << 7, 815 ArchDefinePwr5x = 1 << 8, 816 ArchDefinePwr6 = 1 << 9, 817 ArchDefinePwr6x = 1 << 10, 818 ArchDefinePwr7 = 1 << 11, 819 ArchDefinePwr8 = 1 << 12, 820 ArchDefineA2 = 1 << 13, 821 ArchDefineA2q = 1 << 14 822 } ArchDefineTypes; 823 824 // Note: GCC recognizes the following additional cpus: 825 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 826 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 827 // titan, rs64. 828 bool setCPU(const std::string &Name) override { 829 bool CPUKnown = llvm::StringSwitch<bool>(Name) 830 .Case("generic", true) 831 .Case("440", true) 832 .Case("450", true) 833 .Case("601", true) 834 .Case("602", true) 835 .Case("603", true) 836 .Case("603e", true) 837 .Case("603ev", true) 838 .Case("604", true) 839 .Case("604e", true) 840 .Case("620", true) 841 .Case("630", true) 842 .Case("g3", true) 843 .Case("7400", true) 844 .Case("g4", true) 845 .Case("7450", true) 846 .Case("g4+", true) 847 .Case("750", true) 848 .Case("970", true) 849 .Case("g5", true) 850 .Case("a2", true) 851 .Case("a2q", true) 852 .Case("e500mc", true) 853 .Case("e5500", true) 854 .Case("power3", true) 855 .Case("pwr3", true) 856 .Case("power4", true) 857 .Case("pwr4", true) 858 .Case("power5", true) 859 .Case("pwr5", true) 860 .Case("power5x", true) 861 .Case("pwr5x", true) 862 .Case("power6", true) 863 .Case("pwr6", true) 864 .Case("power6x", true) 865 .Case("pwr6x", true) 866 .Case("power7", true) 867 .Case("pwr7", true) 868 .Case("power8", true) 869 .Case("pwr8", true) 870 .Case("powerpc", true) 871 .Case("ppc", true) 872 .Case("powerpc64", true) 873 .Case("ppc64", true) 874 .Case("powerpc64le", true) 875 .Case("ppc64le", true) 876 .Default(false); 877 878 if (CPUKnown) 879 CPU = Name; 880 881 return CPUKnown; 882 } 883 884 885 StringRef getABI() const override { return ABI; } 886 887 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 888 return llvm::makeArrayRef(BuiltinInfo, 889 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 890 } 891 892 bool isCLZForZeroUndef() const override { return false; } 893 894 void getTargetDefines(const LangOptions &Opts, 895 MacroBuilder &Builder) const override; 896 897 bool 898 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 899 StringRef CPU, 900 const std::vector<std::string> &FeaturesVec) const override; 901 902 bool handleTargetFeatures(std::vector<std::string> &Features, 903 DiagnosticsEngine &Diags) override; 904 bool hasFeature(StringRef Feature) const override; 905 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 906 bool Enabled) const override; 907 908 ArrayRef<const char *> getGCCRegNames() const override; 909 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 910 bool validateAsmConstraint(const char *&Name, 911 TargetInfo::ConstraintInfo &Info) const override { 912 switch (*Name) { 913 default: return false; 914 case 'O': // Zero 915 break; 916 case 'b': // Base register 917 case 'f': // Floating point register 918 Info.setAllowsRegister(); 919 break; 920 // FIXME: The following are added to allow parsing. 921 // I just took a guess at what the actions should be. 922 // Also, is more specific checking needed? I.e. specific registers? 923 case 'd': // Floating point register (containing 64-bit value) 924 case 'v': // Altivec vector register 925 Info.setAllowsRegister(); 926 break; 927 case 'w': 928 switch (Name[1]) { 929 case 'd':// VSX vector register to hold vector double data 930 case 'f':// VSX vector register to hold vector float data 931 case 's':// VSX vector register to hold scalar float data 932 case 'a':// Any VSX register 933 case 'c':// An individual CR bit 934 break; 935 default: 936 return false; 937 } 938 Info.setAllowsRegister(); 939 Name++; // Skip over 'w'. 940 break; 941 case 'h': // `MQ', `CTR', or `LINK' register 942 case 'q': // `MQ' register 943 case 'c': // `CTR' register 944 case 'l': // `LINK' register 945 case 'x': // `CR' register (condition register) number 0 946 case 'y': // `CR' register (condition register) 947 case 'z': // `XER[CA]' carry bit (part of the XER register) 948 Info.setAllowsRegister(); 949 break; 950 case 'I': // Signed 16-bit constant 951 case 'J': // Unsigned 16-bit constant shifted left 16 bits 952 // (use `L' instead for SImode constants) 953 case 'K': // Unsigned 16-bit constant 954 case 'L': // Signed 16-bit constant shifted left 16 bits 955 case 'M': // Constant larger than 31 956 case 'N': // Exact power of 2 957 case 'P': // Constant whose negation is a signed 16-bit constant 958 case 'G': // Floating point constant that can be loaded into a 959 // register with one instruction per word 960 case 'H': // Integer/Floating point constant that can be loaded 961 // into a register using three instructions 962 break; 963 case 'm': // Memory operand. Note that on PowerPC targets, m can 964 // include addresses that update the base register. It 965 // is therefore only safe to use `m' in an asm statement 966 // if that asm statement accesses the operand exactly once. 967 // The asm statement must also use `%U<opno>' as a 968 // placeholder for the "update" flag in the corresponding 969 // load or store instruction. For example: 970 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 971 // is correct but: 972 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 973 // is not. Use es rather than m if you don't want the base 974 // register to be updated. 975 case 'e': 976 if (Name[1] != 's') 977 return false; 978 // es: A "stable" memory operand; that is, one which does not 979 // include any automodification of the base register. Unlike 980 // `m', this constraint can be used in asm statements that 981 // might access the operand several times, or that might not 982 // access it at all. 983 Info.setAllowsMemory(); 984 Name++; // Skip over 'e'. 985 break; 986 case 'Q': // Memory operand that is an offset from a register (it is 987 // usually better to use `m' or `es' in asm statements) 988 case 'Z': // Memory operand that is an indexed or indirect from a 989 // register (it is usually better to use `m' or `es' in 990 // asm statements) 991 Info.setAllowsMemory(); 992 Info.setAllowsRegister(); 993 break; 994 case 'R': // AIX TOC entry 995 case 'a': // Address operand that is an indexed or indirect from a 996 // register (`p' is preferable for asm statements) 997 case 'S': // Constant suitable as a 64-bit mask operand 998 case 'T': // Constant suitable as a 32-bit mask operand 999 case 'U': // System V Release 4 small data area reference 1000 case 't': // AND masks that can be performed by two rldic{l, r} 1001 // instructions 1002 case 'W': // Vector constant that does not require memory 1003 case 'j': // Vector constant that is all zeros. 1004 break; 1005 // End FIXME. 1006 } 1007 return true; 1008 } 1009 std::string convertConstraint(const char *&Constraint) const override { 1010 std::string R; 1011 switch (*Constraint) { 1012 case 'e': 1013 case 'w': 1014 // Two-character constraint; add "^" hint for later parsing. 1015 R = std::string("^") + std::string(Constraint, 2); 1016 Constraint++; 1017 break; 1018 default: 1019 return TargetInfo::convertConstraint(Constraint); 1020 } 1021 return R; 1022 } 1023 const char *getClobbers() const override { 1024 return ""; 1025 } 1026 int getEHDataRegisterNumber(unsigned RegNo) const override { 1027 if (RegNo == 0) return 3; 1028 if (RegNo == 1) return 4; 1029 return -1; 1030 } 1031 1032 bool hasSjLjLowering() const override { 1033 return true; 1034 } 1035 1036 bool useFloat128ManglingForLongDouble() const override { 1037 return LongDoubleWidth == 128 && 1038 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1039 getTriple().isOSBinFormatELF(); 1040 } 1041 }; 1042 1043 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1044 #define BUILTIN(ID, TYPE, ATTRS) \ 1045 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1046 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1047 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1048 #include "clang/Basic/BuiltinsPPC.def" 1049 }; 1050 1051 /// handleTargetFeatures - Perform initialization based on the user 1052 /// configured set of features. 1053 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1054 DiagnosticsEngine &Diags) { 1055 for (const auto &Feature : Features) { 1056 if (Feature == "+vsx") { 1057 HasVSX = true; 1058 } else if (Feature == "+bpermd") { 1059 HasBPERMD = true; 1060 } else if (Feature == "+extdiv") { 1061 HasExtDiv = true; 1062 } else if (Feature == "+power8-vector") { 1063 HasP8Vector = true; 1064 } else if (Feature == "+crypto") { 1065 HasP8Crypto = true; 1066 } else if (Feature == "+direct-move") { 1067 HasDirectMove = true; 1068 } else if (Feature == "+qpx") { 1069 HasQPX = true; 1070 } else if (Feature == "+htm") { 1071 HasHTM = true; 1072 } 1073 // TODO: Finish this list and add an assert that we've handled them 1074 // all. 1075 } 1076 1077 return true; 1078 } 1079 1080 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1081 /// #defines that are not tied to a specific subtarget. 1082 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1083 MacroBuilder &Builder) const { 1084 // Target identification. 1085 Builder.defineMacro("__ppc__"); 1086 Builder.defineMacro("__PPC__"); 1087 Builder.defineMacro("_ARCH_PPC"); 1088 Builder.defineMacro("__powerpc__"); 1089 Builder.defineMacro("__POWERPC__"); 1090 if (PointerWidth == 64) { 1091 Builder.defineMacro("_ARCH_PPC64"); 1092 Builder.defineMacro("__powerpc64__"); 1093 Builder.defineMacro("__ppc64__"); 1094 Builder.defineMacro("__PPC64__"); 1095 } 1096 1097 // Target properties. 1098 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1099 Builder.defineMacro("_LITTLE_ENDIAN"); 1100 } else { 1101 if (getTriple().getOS() != llvm::Triple::NetBSD && 1102 getTriple().getOS() != llvm::Triple::OpenBSD) 1103 Builder.defineMacro("_BIG_ENDIAN"); 1104 } 1105 1106 // ABI options. 1107 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1108 Builder.defineMacro("_CALL_ELF", "1"); 1109 if (ABI == "elfv2") 1110 Builder.defineMacro("_CALL_ELF", "2"); 1111 1112 // Subtarget options. 1113 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1114 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1115 1116 // FIXME: Should be controlled by command line option. 1117 if (LongDoubleWidth == 128) 1118 Builder.defineMacro("__LONG_DOUBLE_128__"); 1119 1120 if (Opts.AltiVec) { 1121 Builder.defineMacro("__VEC__", "10206"); 1122 Builder.defineMacro("__ALTIVEC__"); 1123 } 1124 1125 // CPU identification. 1126 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1127 .Case("440", ArchDefineName) 1128 .Case("450", ArchDefineName | ArchDefine440) 1129 .Case("601", ArchDefineName) 1130 .Case("602", ArchDefineName | ArchDefinePpcgr) 1131 .Case("603", ArchDefineName | ArchDefinePpcgr) 1132 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1133 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1134 .Case("604", ArchDefineName | ArchDefinePpcgr) 1135 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1136 .Case("620", ArchDefineName | ArchDefinePpcgr) 1137 .Case("630", ArchDefineName | ArchDefinePpcgr) 1138 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1139 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1140 .Case("750", ArchDefineName | ArchDefinePpcgr) 1141 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1142 | ArchDefinePpcsq) 1143 .Case("a2", ArchDefineA2) 1144 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1145 .Case("pwr3", ArchDefinePpcgr) 1146 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1147 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1148 | ArchDefinePpcsq) 1149 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1150 | ArchDefinePpcgr | ArchDefinePpcsq) 1151 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1152 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1153 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1154 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1155 | ArchDefinePpcsq) 1156 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1157 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1158 | ArchDefinePpcgr | ArchDefinePpcsq) 1159 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1160 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1161 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1162 .Case("power3", ArchDefinePpcgr) 1163 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1164 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1165 | ArchDefinePpcsq) 1166 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1167 | ArchDefinePpcgr | ArchDefinePpcsq) 1168 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1169 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1170 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1171 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1172 | ArchDefinePpcsq) 1173 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1174 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1175 | ArchDefinePpcgr | ArchDefinePpcsq) 1176 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1177 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1178 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1179 .Default(ArchDefineNone); 1180 1181 if (defs & ArchDefineName) 1182 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1183 if (defs & ArchDefinePpcgr) 1184 Builder.defineMacro("_ARCH_PPCGR"); 1185 if (defs & ArchDefinePpcsq) 1186 Builder.defineMacro("_ARCH_PPCSQ"); 1187 if (defs & ArchDefine440) 1188 Builder.defineMacro("_ARCH_440"); 1189 if (defs & ArchDefine603) 1190 Builder.defineMacro("_ARCH_603"); 1191 if (defs & ArchDefine604) 1192 Builder.defineMacro("_ARCH_604"); 1193 if (defs & ArchDefinePwr4) 1194 Builder.defineMacro("_ARCH_PWR4"); 1195 if (defs & ArchDefinePwr5) 1196 Builder.defineMacro("_ARCH_PWR5"); 1197 if (defs & ArchDefinePwr5x) 1198 Builder.defineMacro("_ARCH_PWR5X"); 1199 if (defs & ArchDefinePwr6) 1200 Builder.defineMacro("_ARCH_PWR6"); 1201 if (defs & ArchDefinePwr6x) 1202 Builder.defineMacro("_ARCH_PWR6X"); 1203 if (defs & ArchDefinePwr7) 1204 Builder.defineMacro("_ARCH_PWR7"); 1205 if (defs & ArchDefinePwr8) 1206 Builder.defineMacro("_ARCH_PWR8"); 1207 if (defs & ArchDefineA2) 1208 Builder.defineMacro("_ARCH_A2"); 1209 if (defs & ArchDefineA2q) { 1210 Builder.defineMacro("_ARCH_A2Q"); 1211 Builder.defineMacro("_ARCH_QP"); 1212 } 1213 1214 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1215 Builder.defineMacro("__bg__"); 1216 Builder.defineMacro("__THW_BLUEGENE__"); 1217 Builder.defineMacro("__bgq__"); 1218 Builder.defineMacro("__TOS_BGQ__"); 1219 } 1220 1221 if (HasVSX) 1222 Builder.defineMacro("__VSX__"); 1223 if (HasP8Vector) 1224 Builder.defineMacro("__POWER8_VECTOR__"); 1225 if (HasP8Crypto) 1226 Builder.defineMacro("__CRYPTO__"); 1227 if (HasHTM) 1228 Builder.defineMacro("__HTM__"); 1229 1230 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1231 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1232 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1233 if (PointerWidth == 64) 1234 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1235 1236 // FIXME: The following are not yet generated here by Clang, but are 1237 // generated by GCC: 1238 // 1239 // _SOFT_FLOAT_ 1240 // __RECIP_PRECISION__ 1241 // __APPLE_ALTIVEC__ 1242 // __RECIP__ 1243 // __RECIPF__ 1244 // __RSQRTE__ 1245 // __RSQRTEF__ 1246 // _SOFT_DOUBLE_ 1247 // __NO_LWSYNC__ 1248 // __HAVE_BSWAP__ 1249 // __LONGDOUBLE128 1250 // __CMODEL_MEDIUM__ 1251 // __CMODEL_LARGE__ 1252 // _CALL_SYSV 1253 // _CALL_DARWIN 1254 // __NO_FPRS__ 1255 } 1256 1257 // Handle explicit options being passed to the compiler here: if we've 1258 // explicitly turned off vsx and turned on power8-vector or direct-move then 1259 // go ahead and error since the customer has expressed a somewhat incompatible 1260 // set of options. 1261 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1262 const std::vector<std::string> &FeaturesVec) { 1263 1264 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1265 FeaturesVec.end()) { 1266 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1267 FeaturesVec.end()) { 1268 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1269 << "-mno-vsx"; 1270 return false; 1271 } 1272 1273 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1274 FeaturesVec.end()) { 1275 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1276 << "-mno-vsx"; 1277 return false; 1278 } 1279 } 1280 1281 return true; 1282 } 1283 1284 bool PPCTargetInfo::initFeatureMap( 1285 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1286 const std::vector<std::string> &FeaturesVec) const { 1287 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1288 .Case("7400", true) 1289 .Case("g4", true) 1290 .Case("7450", true) 1291 .Case("g4+", true) 1292 .Case("970", true) 1293 .Case("g5", true) 1294 .Case("pwr6", true) 1295 .Case("pwr7", true) 1296 .Case("pwr8", true) 1297 .Case("ppc64", true) 1298 .Case("ppc64le", true) 1299 .Default(false); 1300 1301 Features["qpx"] = (CPU == "a2q"); 1302 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1303 .Case("ppc64le", true) 1304 .Case("pwr8", true) 1305 .Default(false); 1306 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1307 .Case("ppc64le", true) 1308 .Case("pwr8", true) 1309 .Default(false); 1310 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1311 .Case("ppc64le", true) 1312 .Case("pwr8", true) 1313 .Case("pwr7", true) 1314 .Default(false); 1315 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1316 .Case("ppc64le", true) 1317 .Case("pwr8", true) 1318 .Case("pwr7", true) 1319 .Default(false); 1320 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1321 .Case("ppc64le", true) 1322 .Case("pwr8", true) 1323 .Default(false); 1324 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1325 .Case("ppc64le", true) 1326 .Case("pwr8", true) 1327 .Case("pwr7", true) 1328 .Default(false); 1329 1330 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1331 return false; 1332 1333 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1334 } 1335 1336 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1337 return llvm::StringSwitch<bool>(Feature) 1338 .Case("powerpc", true) 1339 .Case("vsx", HasVSX) 1340 .Case("power8-vector", HasP8Vector) 1341 .Case("crypto", HasP8Crypto) 1342 .Case("direct-move", HasDirectMove) 1343 .Case("qpx", HasQPX) 1344 .Case("htm", HasHTM) 1345 .Case("bpermd", HasBPERMD) 1346 .Case("extdiv", HasExtDiv) 1347 .Default(false); 1348 } 1349 1350 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1351 StringRef Name, bool Enabled) const { 1352 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1353 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1354 // incompatible options. 1355 if (Enabled) { 1356 if (Name == "vsx") { 1357 Features[Name] = true; 1358 } else if (Name == "direct-move") { 1359 Features[Name] = Features["vsx"] = true; 1360 } else if (Name == "power8-vector") { 1361 Features[Name] = Features["vsx"] = true; 1362 } else { 1363 Features[Name] = true; 1364 } 1365 } else { 1366 if (Name == "vsx") { 1367 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1368 false; 1369 } else { 1370 Features[Name] = false; 1371 } 1372 } 1373 } 1374 1375 const char * const PPCTargetInfo::GCCRegNames[] = { 1376 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1377 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1378 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1379 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1380 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1381 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1382 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1383 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1384 "mq", "lr", "ctr", "ap", 1385 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1386 "xer", 1387 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1388 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1389 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1390 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1391 "vrsave", "vscr", 1392 "spe_acc", "spefscr", 1393 "sfp" 1394 }; 1395 1396 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1397 return llvm::makeArrayRef(GCCRegNames); 1398 } 1399 1400 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1401 // While some of these aliases do map to different registers 1402 // they still share the same register name. 1403 { { "0" }, "r0" }, 1404 { { "1"}, "r1" }, 1405 { { "2" }, "r2" }, 1406 { { "3" }, "r3" }, 1407 { { "4" }, "r4" }, 1408 { { "5" }, "r5" }, 1409 { { "6" }, "r6" }, 1410 { { "7" }, "r7" }, 1411 { { "8" }, "r8" }, 1412 { { "9" }, "r9" }, 1413 { { "10" }, "r10" }, 1414 { { "11" }, "r11" }, 1415 { { "12" }, "r12" }, 1416 { { "13" }, "r13" }, 1417 { { "14" }, "r14" }, 1418 { { "15" }, "r15" }, 1419 { { "16" }, "r16" }, 1420 { { "17" }, "r17" }, 1421 { { "18" }, "r18" }, 1422 { { "19" }, "r19" }, 1423 { { "20" }, "r20" }, 1424 { { "21" }, "r21" }, 1425 { { "22" }, "r22" }, 1426 { { "23" }, "r23" }, 1427 { { "24" }, "r24" }, 1428 { { "25" }, "r25" }, 1429 { { "26" }, "r26" }, 1430 { { "27" }, "r27" }, 1431 { { "28" }, "r28" }, 1432 { { "29" }, "r29" }, 1433 { { "30" }, "r30" }, 1434 { { "31" }, "r31" }, 1435 { { "fr0" }, "f0" }, 1436 { { "fr1" }, "f1" }, 1437 { { "fr2" }, "f2" }, 1438 { { "fr3" }, "f3" }, 1439 { { "fr4" }, "f4" }, 1440 { { "fr5" }, "f5" }, 1441 { { "fr6" }, "f6" }, 1442 { { "fr7" }, "f7" }, 1443 { { "fr8" }, "f8" }, 1444 { { "fr9" }, "f9" }, 1445 { { "fr10" }, "f10" }, 1446 { { "fr11" }, "f11" }, 1447 { { "fr12" }, "f12" }, 1448 { { "fr13" }, "f13" }, 1449 { { "fr14" }, "f14" }, 1450 { { "fr15" }, "f15" }, 1451 { { "fr16" }, "f16" }, 1452 { { "fr17" }, "f17" }, 1453 { { "fr18" }, "f18" }, 1454 { { "fr19" }, "f19" }, 1455 { { "fr20" }, "f20" }, 1456 { { "fr21" }, "f21" }, 1457 { { "fr22" }, "f22" }, 1458 { { "fr23" }, "f23" }, 1459 { { "fr24" }, "f24" }, 1460 { { "fr25" }, "f25" }, 1461 { { "fr26" }, "f26" }, 1462 { { "fr27" }, "f27" }, 1463 { { "fr28" }, "f28" }, 1464 { { "fr29" }, "f29" }, 1465 { { "fr30" }, "f30" }, 1466 { { "fr31" }, "f31" }, 1467 { { "cc" }, "cr0" }, 1468 }; 1469 1470 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1471 return llvm::makeArrayRef(GCCRegAliases); 1472 } 1473 1474 class PPC32TargetInfo : public PPCTargetInfo { 1475 public: 1476 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1477 DataLayoutString = "E-m:e-p:32:32-i64:64-n32"; 1478 1479 switch (getTriple().getOS()) { 1480 case llvm::Triple::Linux: 1481 case llvm::Triple::FreeBSD: 1482 case llvm::Triple::NetBSD: 1483 SizeType = UnsignedInt; 1484 PtrDiffType = SignedInt; 1485 IntPtrType = SignedInt; 1486 break; 1487 default: 1488 break; 1489 } 1490 1491 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1492 LongDoubleWidth = LongDoubleAlign = 64; 1493 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1494 } 1495 1496 // PPC32 supports atomics up to 4 bytes. 1497 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1498 } 1499 1500 BuiltinVaListKind getBuiltinVaListKind() const override { 1501 // This is the ELF definition, and is overridden by the Darwin sub-target 1502 return TargetInfo::PowerABIBuiltinVaList; 1503 } 1504 }; 1505 1506 // Note: ABI differences may eventually require us to have a separate 1507 // TargetInfo for little endian. 1508 class PPC64TargetInfo : public PPCTargetInfo { 1509 public: 1510 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1511 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1512 IntMaxType = SignedLong; 1513 Int64Type = SignedLong; 1514 1515 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1516 DataLayoutString = "e-m:e-i64:64-n32:64"; 1517 ABI = "elfv2"; 1518 } else { 1519 DataLayoutString = "E-m:e-i64:64-n32:64"; 1520 ABI = "elfv1"; 1521 } 1522 1523 switch (getTriple().getOS()) { 1524 case llvm::Triple::FreeBSD: 1525 LongDoubleWidth = LongDoubleAlign = 64; 1526 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1527 break; 1528 case llvm::Triple::NetBSD: 1529 IntMaxType = SignedLongLong; 1530 Int64Type = SignedLongLong; 1531 break; 1532 default: 1533 break; 1534 } 1535 1536 // PPC64 supports atomics up to 8 bytes. 1537 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1538 } 1539 BuiltinVaListKind getBuiltinVaListKind() const override { 1540 return TargetInfo::CharPtrBuiltinVaList; 1541 } 1542 // PPC64 Linux-specific ABI options. 1543 bool setABI(const std::string &Name) override { 1544 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1545 ABI = Name; 1546 return true; 1547 } 1548 return false; 1549 } 1550 }; 1551 1552 class DarwinPPC32TargetInfo : 1553 public DarwinTargetInfo<PPC32TargetInfo> { 1554 public: 1555 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1556 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1557 HasAlignMac68kSupport = true; 1558 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1559 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1560 LongLongAlign = 32; 1561 SuitableAlign = 128; 1562 DataLayoutString = "E-m:o-p:32:32-f64:32:64-n32"; 1563 } 1564 BuiltinVaListKind getBuiltinVaListKind() const override { 1565 return TargetInfo::CharPtrBuiltinVaList; 1566 } 1567 }; 1568 1569 class DarwinPPC64TargetInfo : 1570 public DarwinTargetInfo<PPC64TargetInfo> { 1571 public: 1572 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1573 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1574 HasAlignMac68kSupport = true; 1575 SuitableAlign = 128; 1576 DataLayoutString = "E-m:o-i64:64-n32:64"; 1577 } 1578 }; 1579 1580 static const unsigned NVPTXAddrSpaceMap[] = { 1581 1, // opencl_global 1582 3, // opencl_local 1583 4, // opencl_constant 1584 // FIXME: generic has to be added to the target 1585 0, // opencl_generic 1586 1, // cuda_device 1587 4, // cuda_constant 1588 3, // cuda_shared 1589 }; 1590 1591 class NVPTXTargetInfo : public TargetInfo { 1592 static const char *const GCCRegNames[]; 1593 static const Builtin::Info BuiltinInfo[]; 1594 1595 // The GPU profiles supported by the NVPTX backend 1596 enum GPUKind { 1597 GK_NONE, 1598 GK_SM20, 1599 GK_SM21, 1600 GK_SM30, 1601 GK_SM35, 1602 GK_SM37, 1603 } GPU; 1604 1605 public: 1606 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1607 BigEndian = false; 1608 TLSSupported = false; 1609 LongWidth = LongAlign = 64; 1610 AddrSpaceMap = &NVPTXAddrSpaceMap; 1611 UseAddrSpaceMapMangling = true; 1612 // Define available target features 1613 // These must be defined in sorted order! 1614 NoAsmVariants = true; 1615 // Set the default GPU to sm20 1616 GPU = GK_SM20; 1617 } 1618 void getTargetDefines(const LangOptions &Opts, 1619 MacroBuilder &Builder) const override { 1620 Builder.defineMacro("__PTX__"); 1621 Builder.defineMacro("__NVPTX__"); 1622 if (Opts.CUDAIsDevice) { 1623 // Set __CUDA_ARCH__ for the GPU specified. 1624 std::string CUDAArchCode; 1625 switch (GPU) { 1626 case GK_SM20: 1627 CUDAArchCode = "200"; 1628 break; 1629 case GK_SM21: 1630 CUDAArchCode = "210"; 1631 break; 1632 case GK_SM30: 1633 CUDAArchCode = "300"; 1634 break; 1635 case GK_SM35: 1636 CUDAArchCode = "350"; 1637 break; 1638 case GK_SM37: 1639 CUDAArchCode = "370"; 1640 break; 1641 default: 1642 llvm_unreachable("Unhandled target CPU"); 1643 } 1644 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1645 } 1646 } 1647 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1648 return llvm::makeArrayRef(BuiltinInfo, 1649 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1650 } 1651 bool hasFeature(StringRef Feature) const override { 1652 return Feature == "ptx" || Feature == "nvptx"; 1653 } 1654 1655 ArrayRef<const char *> getGCCRegNames() const override; 1656 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1657 // No aliases. 1658 return None; 1659 } 1660 bool validateAsmConstraint(const char *&Name, 1661 TargetInfo::ConstraintInfo &Info) const override { 1662 switch (*Name) { 1663 default: 1664 return false; 1665 case 'c': 1666 case 'h': 1667 case 'r': 1668 case 'l': 1669 case 'f': 1670 case 'd': 1671 Info.setAllowsRegister(); 1672 return true; 1673 } 1674 } 1675 const char *getClobbers() const override { 1676 // FIXME: Is this really right? 1677 return ""; 1678 } 1679 BuiltinVaListKind getBuiltinVaListKind() const override { 1680 // FIXME: implement 1681 return TargetInfo::CharPtrBuiltinVaList; 1682 } 1683 bool setCPU(const std::string &Name) override { 1684 GPU = llvm::StringSwitch<GPUKind>(Name) 1685 .Case("sm_20", GK_SM20) 1686 .Case("sm_21", GK_SM21) 1687 .Case("sm_30", GK_SM30) 1688 .Case("sm_35", GK_SM35) 1689 .Case("sm_37", GK_SM37) 1690 .Default(GK_NONE); 1691 1692 return GPU != GK_NONE; 1693 } 1694 }; 1695 1696 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1697 #define BUILTIN(ID, TYPE, ATTRS) \ 1698 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1699 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1700 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1701 #include "clang/Basic/BuiltinsNVPTX.def" 1702 }; 1703 1704 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1705 1706 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1707 return llvm::makeArrayRef(GCCRegNames); 1708 } 1709 1710 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1711 public: 1712 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1713 LongWidth = LongAlign = 32; 1714 PointerWidth = PointerAlign = 32; 1715 SizeType = TargetInfo::UnsignedInt; 1716 PtrDiffType = TargetInfo::SignedInt; 1717 IntPtrType = TargetInfo::SignedInt; 1718 DataLayoutString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1719 } 1720 }; 1721 1722 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1723 public: 1724 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1725 PointerWidth = PointerAlign = 64; 1726 SizeType = TargetInfo::UnsignedLong; 1727 PtrDiffType = TargetInfo::SignedLong; 1728 IntPtrType = TargetInfo::SignedLong; 1729 DataLayoutString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1730 } 1731 }; 1732 1733 static const unsigned AMDGPUAddrSpaceMap[] = { 1734 1, // opencl_global 1735 3, // opencl_local 1736 2, // opencl_constant 1737 4, // opencl_generic 1738 1, // cuda_device 1739 2, // cuda_constant 1740 3 // cuda_shared 1741 }; 1742 1743 // If you edit the description strings, make sure you update 1744 // getPointerWidthV(). 1745 1746 static const char *const DataLayoutStringR600 = 1747 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1748 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1749 1750 static const char *const DataLayoutStringR600DoubleOps = 1751 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1752 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1753 1754 static const char *const DataLayoutStringSI = 1755 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1756 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1757 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1758 1759 class AMDGPUTargetInfo : public TargetInfo { 1760 static const Builtin::Info BuiltinInfo[]; 1761 static const char * const GCCRegNames[]; 1762 1763 /// \brief The GPU profiles supported by the AMDGPU target. 1764 enum GPUKind { 1765 GK_NONE, 1766 GK_R600, 1767 GK_R600_DOUBLE_OPS, 1768 GK_R700, 1769 GK_R700_DOUBLE_OPS, 1770 GK_EVERGREEN, 1771 GK_EVERGREEN_DOUBLE_OPS, 1772 GK_NORTHERN_ISLANDS, 1773 GK_CAYMAN, 1774 GK_SOUTHERN_ISLANDS, 1775 GK_SEA_ISLANDS, 1776 GK_VOLCANIC_ISLANDS 1777 } GPU; 1778 1779 bool hasFP64:1; 1780 bool hasFMAF:1; 1781 bool hasLDEXPF:1; 1782 1783 public: 1784 AMDGPUTargetInfo(const llvm::Triple &Triple) 1785 : TargetInfo(Triple) { 1786 1787 if (Triple.getArch() == llvm::Triple::amdgcn) { 1788 DataLayoutString = DataLayoutStringSI; 1789 GPU = GK_SOUTHERN_ISLANDS; 1790 hasFP64 = true; 1791 hasFMAF = true; 1792 hasLDEXPF = true; 1793 } else { 1794 DataLayoutString = DataLayoutStringR600; 1795 GPU = GK_R600; 1796 hasFP64 = false; 1797 hasFMAF = false; 1798 hasLDEXPF = false; 1799 } 1800 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1801 UseAddrSpaceMapMangling = true; 1802 } 1803 1804 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1805 if (GPU <= GK_CAYMAN) 1806 return 32; 1807 1808 switch(AddrSpace) { 1809 default: 1810 return 64; 1811 case 0: 1812 case 3: 1813 case 5: 1814 return 32; 1815 } 1816 } 1817 1818 const char * getClobbers() const override { 1819 return ""; 1820 } 1821 1822 ArrayRef<const char *> getGCCRegNames() const override; 1823 1824 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1825 return None; 1826 } 1827 1828 bool validateAsmConstraint(const char *&Name, 1829 TargetInfo::ConstraintInfo &Info) const override { 1830 switch (*Name) { 1831 default: break; 1832 case 'v': // vgpr 1833 case 's': // sgpr 1834 Info.setAllowsRegister(); 1835 return true; 1836 } 1837 return false; 1838 } 1839 1840 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1841 return llvm::makeArrayRef(BuiltinInfo, 1842 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 1843 } 1844 1845 void getTargetDefines(const LangOptions &Opts, 1846 MacroBuilder &Builder) const override { 1847 Builder.defineMacro("__R600__"); 1848 if (hasFMAF) 1849 Builder.defineMacro("__HAS_FMAF__"); 1850 if (hasLDEXPF) 1851 Builder.defineMacro("__HAS_LDEXPF__"); 1852 if (hasFP64 && Opts.OpenCL) 1853 Builder.defineMacro("cl_khr_fp64"); 1854 if (Opts.OpenCL) { 1855 if (GPU >= GK_NORTHERN_ISLANDS) { 1856 Builder.defineMacro("cl_khr_byte_addressable_store"); 1857 Builder.defineMacro("cl_khr_global_int32_base_atomics"); 1858 Builder.defineMacro("cl_khr_global_int32_extended_atomics"); 1859 Builder.defineMacro("cl_khr_local_int32_base_atomics"); 1860 Builder.defineMacro("cl_khr_local_int32_extended_atomics"); 1861 } 1862 } 1863 } 1864 1865 BuiltinVaListKind getBuiltinVaListKind() const override { 1866 return TargetInfo::CharPtrBuiltinVaList; 1867 } 1868 1869 bool setCPU(const std::string &Name) override { 1870 GPU = llvm::StringSwitch<GPUKind>(Name) 1871 .Case("r600" , GK_R600) 1872 .Case("rv610", GK_R600) 1873 .Case("rv620", GK_R600) 1874 .Case("rv630", GK_R600) 1875 .Case("rv635", GK_R600) 1876 .Case("rs780", GK_R600) 1877 .Case("rs880", GK_R600) 1878 .Case("rv670", GK_R600_DOUBLE_OPS) 1879 .Case("rv710", GK_R700) 1880 .Case("rv730", GK_R700) 1881 .Case("rv740", GK_R700_DOUBLE_OPS) 1882 .Case("rv770", GK_R700_DOUBLE_OPS) 1883 .Case("palm", GK_EVERGREEN) 1884 .Case("cedar", GK_EVERGREEN) 1885 .Case("sumo", GK_EVERGREEN) 1886 .Case("sumo2", GK_EVERGREEN) 1887 .Case("redwood", GK_EVERGREEN) 1888 .Case("juniper", GK_EVERGREEN) 1889 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1890 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1891 .Case("barts", GK_NORTHERN_ISLANDS) 1892 .Case("turks", GK_NORTHERN_ISLANDS) 1893 .Case("caicos", GK_NORTHERN_ISLANDS) 1894 .Case("cayman", GK_CAYMAN) 1895 .Case("aruba", GK_CAYMAN) 1896 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1897 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1898 .Case("verde", GK_SOUTHERN_ISLANDS) 1899 .Case("oland", GK_SOUTHERN_ISLANDS) 1900 .Case("hainan", GK_SOUTHERN_ISLANDS) 1901 .Case("bonaire", GK_SEA_ISLANDS) 1902 .Case("kabini", GK_SEA_ISLANDS) 1903 .Case("kaveri", GK_SEA_ISLANDS) 1904 .Case("hawaii", GK_SEA_ISLANDS) 1905 .Case("mullins", GK_SEA_ISLANDS) 1906 .Case("tonga", GK_VOLCANIC_ISLANDS) 1907 .Case("iceland", GK_VOLCANIC_ISLANDS) 1908 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1909 .Default(GK_NONE); 1910 1911 if (GPU == GK_NONE) { 1912 return false; 1913 } 1914 1915 // Set the correct data layout 1916 switch (GPU) { 1917 case GK_NONE: 1918 case GK_R600: 1919 case GK_R700: 1920 case GK_EVERGREEN: 1921 case GK_NORTHERN_ISLANDS: 1922 DataLayoutString = DataLayoutStringR600; 1923 hasFP64 = false; 1924 hasFMAF = false; 1925 hasLDEXPF = false; 1926 break; 1927 case GK_R600_DOUBLE_OPS: 1928 case GK_R700_DOUBLE_OPS: 1929 case GK_EVERGREEN_DOUBLE_OPS: 1930 case GK_CAYMAN: 1931 DataLayoutString = DataLayoutStringR600DoubleOps; 1932 hasFP64 = true; 1933 hasFMAF = true; 1934 hasLDEXPF = false; 1935 break; 1936 case GK_SOUTHERN_ISLANDS: 1937 case GK_SEA_ISLANDS: 1938 case GK_VOLCANIC_ISLANDS: 1939 DataLayoutString = DataLayoutStringSI; 1940 hasFP64 = true; 1941 hasFMAF = true; 1942 hasLDEXPF = true; 1943 break; 1944 } 1945 1946 return true; 1947 } 1948 }; 1949 1950 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1951 #define BUILTIN(ID, TYPE, ATTRS) \ 1952 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1953 #include "clang/Basic/BuiltinsAMDGPU.def" 1954 }; 1955 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1956 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1957 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1958 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1959 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1960 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1961 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1962 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1963 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1964 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1965 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1966 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1967 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1968 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1969 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1970 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1971 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1972 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1973 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1974 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1975 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 1976 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 1977 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 1978 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 1979 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 1980 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 1981 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 1982 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 1983 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 1984 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 1985 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 1986 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 1987 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 1988 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 1989 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 1990 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 1991 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 1992 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 1993 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 1994 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 1995 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 1996 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 1997 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 1998 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 1999 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2000 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2001 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2002 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2003 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127" 2004 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi", 2005 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi" 2006 }; 2007 2008 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2009 return llvm::makeArrayRef(GCCRegNames); 2010 } 2011 2012 // Namespace for x86 abstract base class 2013 const Builtin::Info BuiltinInfo[] = { 2014 #define BUILTIN(ID, TYPE, ATTRS) \ 2015 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2016 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2017 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2018 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2019 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2020 #include "clang/Basic/BuiltinsX86.def" 2021 }; 2022 2023 static const char* const GCCRegNames[] = { 2024 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2025 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2026 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2027 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2028 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2029 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2030 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2031 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2032 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2033 }; 2034 2035 const TargetInfo::AddlRegName AddlRegNames[] = { 2036 { { "al", "ah", "eax", "rax" }, 0 }, 2037 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2038 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2039 { { "dl", "dh", "edx", "rdx" }, 1 }, 2040 { { "esi", "rsi" }, 4 }, 2041 { { "edi", "rdi" }, 5 }, 2042 { { "esp", "rsp" }, 7 }, 2043 { { "ebp", "rbp" }, 6 }, 2044 { { "r8d", "r8w", "r8b" }, 38 }, 2045 { { "r9d", "r9w", "r9b" }, 39 }, 2046 { { "r10d", "r10w", "r10b" }, 40 }, 2047 { { "r11d", "r11w", "r11b" }, 41 }, 2048 { { "r12d", "r12w", "r12b" }, 42 }, 2049 { { "r13d", "r13w", "r13b" }, 43 }, 2050 { { "r14d", "r14w", "r14b" }, 44 }, 2051 { { "r15d", "r15w", "r15b" }, 45 }, 2052 }; 2053 2054 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2055 // most of the implementation can be shared. 2056 class X86TargetInfo : public TargetInfo { 2057 enum X86SSEEnum { 2058 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2059 } SSELevel = NoSSE; 2060 enum MMX3DNowEnum { 2061 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2062 } MMX3DNowLevel = NoMMX3DNow; 2063 enum XOPEnum { 2064 NoXOP, 2065 SSE4A, 2066 FMA4, 2067 XOP 2068 } XOPLevel = NoXOP; 2069 2070 bool HasAES = false; 2071 bool HasPCLMUL = false; 2072 bool HasLZCNT = false; 2073 bool HasRDRND = false; 2074 bool HasFSGSBASE = false; 2075 bool HasBMI = false; 2076 bool HasBMI2 = false; 2077 bool HasPOPCNT = false; 2078 bool HasRTM = false; 2079 bool HasPRFCHW = false; 2080 bool HasRDSEED = false; 2081 bool HasADX = false; 2082 bool HasTBM = false; 2083 bool HasFMA = false; 2084 bool HasF16C = false; 2085 bool HasAVX512CD = false; 2086 bool HasAVX512ER = false; 2087 bool HasAVX512PF = false; 2088 bool HasAVX512DQ = false; 2089 bool HasAVX512BW = false; 2090 bool HasAVX512VL = false; 2091 bool HasSHA = false; 2092 bool HasCX16 = false; 2093 bool HasFXSR = false; 2094 bool HasXSAVE = false; 2095 bool HasXSAVEOPT = false; 2096 bool HasXSAVEC = false; 2097 bool HasXSAVES = false; 2098 2099 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2100 /// 2101 /// Each enumeration represents a particular CPU supported by Clang. These 2102 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2103 enum CPUKind { 2104 CK_Generic, 2105 2106 /// \name i386 2107 /// i386-generation processors. 2108 //@{ 2109 CK_i386, 2110 //@} 2111 2112 /// \name i486 2113 /// i486-generation processors. 2114 //@{ 2115 CK_i486, 2116 CK_WinChipC6, 2117 CK_WinChip2, 2118 CK_C3, 2119 //@} 2120 2121 /// \name i586 2122 /// i586-generation processors, P5 microarchitecture based. 2123 //@{ 2124 CK_i586, 2125 CK_Pentium, 2126 CK_PentiumMMX, 2127 //@} 2128 2129 /// \name i686 2130 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2131 //@{ 2132 CK_i686, 2133 CK_PentiumPro, 2134 CK_Pentium2, 2135 CK_Pentium3, 2136 CK_Pentium3M, 2137 CK_PentiumM, 2138 CK_C3_2, 2139 2140 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2141 /// Clang however has some logic to suport this. 2142 // FIXME: Warn, deprecate, and potentially remove this. 2143 CK_Yonah, 2144 //@} 2145 2146 /// \name Netburst 2147 /// Netburst microarchitecture based processors. 2148 //@{ 2149 CK_Pentium4, 2150 CK_Pentium4M, 2151 CK_Prescott, 2152 CK_Nocona, 2153 //@} 2154 2155 /// \name Core 2156 /// Core microarchitecture based processors. 2157 //@{ 2158 CK_Core2, 2159 2160 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2161 /// codename which GCC no longer accepts as an option to -march, but Clang 2162 /// has some logic for recognizing it. 2163 // FIXME: Warn, deprecate, and potentially remove this. 2164 CK_Penryn, 2165 //@} 2166 2167 /// \name Atom 2168 /// Atom processors 2169 //@{ 2170 CK_Bonnell, 2171 CK_Silvermont, 2172 //@} 2173 2174 /// \name Nehalem 2175 /// Nehalem microarchitecture based processors. 2176 CK_Nehalem, 2177 2178 /// \name Westmere 2179 /// Westmere microarchitecture based processors. 2180 CK_Westmere, 2181 2182 /// \name Sandy Bridge 2183 /// Sandy Bridge microarchitecture based processors. 2184 CK_SandyBridge, 2185 2186 /// \name Ivy Bridge 2187 /// Ivy Bridge microarchitecture based processors. 2188 CK_IvyBridge, 2189 2190 /// \name Haswell 2191 /// Haswell microarchitecture based processors. 2192 CK_Haswell, 2193 2194 /// \name Broadwell 2195 /// Broadwell microarchitecture based processors. 2196 CK_Broadwell, 2197 2198 /// \name Skylake 2199 /// Skylake microarchitecture based processors. 2200 CK_Skylake, 2201 2202 /// \name Knights Landing 2203 /// Knights Landing processor. 2204 CK_KNL, 2205 2206 /// \name K6 2207 /// K6 architecture processors. 2208 //@{ 2209 CK_K6, 2210 CK_K6_2, 2211 CK_K6_3, 2212 //@} 2213 2214 /// \name K7 2215 /// K7 architecture processors. 2216 //@{ 2217 CK_Athlon, 2218 CK_AthlonThunderbird, 2219 CK_Athlon4, 2220 CK_AthlonXP, 2221 CK_AthlonMP, 2222 //@} 2223 2224 /// \name K8 2225 /// K8 architecture processors. 2226 //@{ 2227 CK_Athlon64, 2228 CK_Athlon64SSE3, 2229 CK_AthlonFX, 2230 CK_K8, 2231 CK_K8SSE3, 2232 CK_Opteron, 2233 CK_OpteronSSE3, 2234 CK_AMDFAM10, 2235 //@} 2236 2237 /// \name Bobcat 2238 /// Bobcat architecture processors. 2239 //@{ 2240 CK_BTVER1, 2241 CK_BTVER2, 2242 //@} 2243 2244 /// \name Bulldozer 2245 /// Bulldozer architecture processors. 2246 //@{ 2247 CK_BDVER1, 2248 CK_BDVER2, 2249 CK_BDVER3, 2250 CK_BDVER4, 2251 //@} 2252 2253 /// This specification is deprecated and will be removed in the future. 2254 /// Users should prefer \see CK_K8. 2255 // FIXME: Warn on this when the CPU is set to it. 2256 //@{ 2257 CK_x86_64, 2258 //@} 2259 2260 /// \name Geode 2261 /// Geode processors. 2262 //@{ 2263 CK_Geode 2264 //@} 2265 } CPU = CK_Generic; 2266 2267 CPUKind getCPUKind(StringRef CPU) const { 2268 return llvm::StringSwitch<CPUKind>(CPU) 2269 .Case("i386", CK_i386) 2270 .Case("i486", CK_i486) 2271 .Case("winchip-c6", CK_WinChipC6) 2272 .Case("winchip2", CK_WinChip2) 2273 .Case("c3", CK_C3) 2274 .Case("i586", CK_i586) 2275 .Case("pentium", CK_Pentium) 2276 .Case("pentium-mmx", CK_PentiumMMX) 2277 .Case("i686", CK_i686) 2278 .Case("pentiumpro", CK_PentiumPro) 2279 .Case("pentium2", CK_Pentium2) 2280 .Case("pentium3", CK_Pentium3) 2281 .Case("pentium3m", CK_Pentium3M) 2282 .Case("pentium-m", CK_PentiumM) 2283 .Case("c3-2", CK_C3_2) 2284 .Case("yonah", CK_Yonah) 2285 .Case("pentium4", CK_Pentium4) 2286 .Case("pentium4m", CK_Pentium4M) 2287 .Case("prescott", CK_Prescott) 2288 .Case("nocona", CK_Nocona) 2289 .Case("core2", CK_Core2) 2290 .Case("penryn", CK_Penryn) 2291 .Case("bonnell", CK_Bonnell) 2292 .Case("atom", CK_Bonnell) // Legacy name. 2293 .Case("silvermont", CK_Silvermont) 2294 .Case("slm", CK_Silvermont) // Legacy name. 2295 .Case("nehalem", CK_Nehalem) 2296 .Case("corei7", CK_Nehalem) // Legacy name. 2297 .Case("westmere", CK_Westmere) 2298 .Case("sandybridge", CK_SandyBridge) 2299 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2300 .Case("ivybridge", CK_IvyBridge) 2301 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2302 .Case("haswell", CK_Haswell) 2303 .Case("core-avx2", CK_Haswell) // Legacy name. 2304 .Case("broadwell", CK_Broadwell) 2305 .Case("skylake", CK_Skylake) 2306 .Case("skx", CK_Skylake) // Legacy name. 2307 .Case("knl", CK_KNL) 2308 .Case("k6", CK_K6) 2309 .Case("k6-2", CK_K6_2) 2310 .Case("k6-3", CK_K6_3) 2311 .Case("athlon", CK_Athlon) 2312 .Case("athlon-tbird", CK_AthlonThunderbird) 2313 .Case("athlon-4", CK_Athlon4) 2314 .Case("athlon-xp", CK_AthlonXP) 2315 .Case("athlon-mp", CK_AthlonMP) 2316 .Case("athlon64", CK_Athlon64) 2317 .Case("athlon64-sse3", CK_Athlon64SSE3) 2318 .Case("athlon-fx", CK_AthlonFX) 2319 .Case("k8", CK_K8) 2320 .Case("k8-sse3", CK_K8SSE3) 2321 .Case("opteron", CK_Opteron) 2322 .Case("opteron-sse3", CK_OpteronSSE3) 2323 .Case("barcelona", CK_AMDFAM10) 2324 .Case("amdfam10", CK_AMDFAM10) 2325 .Case("btver1", CK_BTVER1) 2326 .Case("btver2", CK_BTVER2) 2327 .Case("bdver1", CK_BDVER1) 2328 .Case("bdver2", CK_BDVER2) 2329 .Case("bdver3", CK_BDVER3) 2330 .Case("bdver4", CK_BDVER4) 2331 .Case("x86-64", CK_x86_64) 2332 .Case("geode", CK_Geode) 2333 .Default(CK_Generic); 2334 } 2335 2336 enum FPMathKind { 2337 FP_Default, 2338 FP_SSE, 2339 FP_387 2340 } FPMath = FP_Default; 2341 2342 public: 2343 X86TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 2344 BigEndian = false; 2345 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2346 } 2347 unsigned getFloatEvalMethod() const override { 2348 // X87 evaluates with 80 bits "long double" precision. 2349 return SSELevel == NoSSE ? 2 : 0; 2350 } 2351 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2352 return llvm::makeArrayRef(BuiltinInfo, 2353 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2354 } 2355 ArrayRef<const char *> getGCCRegNames() const override { 2356 return llvm::makeArrayRef(GCCRegNames); 2357 } 2358 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2359 return None; 2360 } 2361 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2362 return llvm::makeArrayRef(AddlRegNames); 2363 } 2364 bool validateCpuSupports(StringRef Name) const override; 2365 bool validateAsmConstraint(const char *&Name, 2366 TargetInfo::ConstraintInfo &info) const override; 2367 2368 bool validateGlobalRegisterVariable(StringRef RegName, 2369 unsigned RegSize, 2370 bool &HasSizeMismatch) const override { 2371 // esp and ebp are the only 32-bit registers the x86 backend can currently 2372 // handle. 2373 if (RegName.equals("esp") || RegName.equals("ebp")) { 2374 // Check that the register size is 32-bit. 2375 HasSizeMismatch = RegSize != 32; 2376 return true; 2377 } 2378 2379 return false; 2380 } 2381 2382 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2383 2384 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2385 2386 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2387 2388 std::string convertConstraint(const char *&Constraint) const override; 2389 const char *getClobbers() const override { 2390 return "~{dirflag},~{fpsr},~{flags}"; 2391 } 2392 void getTargetDefines(const LangOptions &Opts, 2393 MacroBuilder &Builder) const override; 2394 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2395 bool Enabled); 2396 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2397 bool Enabled); 2398 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2399 bool Enabled); 2400 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2401 StringRef Name, bool Enabled) const override { 2402 setFeatureEnabledImpl(Features, Name, Enabled); 2403 } 2404 // This exists purely to cut down on the number of virtual calls in 2405 // initFeatureMap which calls this repeatedly. 2406 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2407 StringRef Name, bool Enabled); 2408 bool 2409 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2410 StringRef CPU, 2411 const std::vector<std::string> &FeaturesVec) const override; 2412 bool hasFeature(StringRef Feature) const override; 2413 bool handleTargetFeatures(std::vector<std::string> &Features, 2414 DiagnosticsEngine &Diags) override; 2415 StringRef getABI() const override { 2416 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2417 return "avx512"; 2418 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2419 return "avx"; 2420 if (getTriple().getArch() == llvm::Triple::x86 && 2421 MMX3DNowLevel == NoMMX3DNow) 2422 return "no-mmx"; 2423 return ""; 2424 } 2425 bool setCPU(const std::string &Name) override { 2426 CPU = getCPUKind(Name); 2427 2428 // Perform any per-CPU checks necessary to determine if this CPU is 2429 // acceptable. 2430 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2431 // invalid without explaining *why*. 2432 switch (CPU) { 2433 case CK_Generic: 2434 // No processor selected! 2435 return false; 2436 2437 case CK_i386: 2438 case CK_i486: 2439 case CK_WinChipC6: 2440 case CK_WinChip2: 2441 case CK_C3: 2442 case CK_i586: 2443 case CK_Pentium: 2444 case CK_PentiumMMX: 2445 case CK_i686: 2446 case CK_PentiumPro: 2447 case CK_Pentium2: 2448 case CK_Pentium3: 2449 case CK_Pentium3M: 2450 case CK_PentiumM: 2451 case CK_Yonah: 2452 case CK_C3_2: 2453 case CK_Pentium4: 2454 case CK_Pentium4M: 2455 case CK_Prescott: 2456 case CK_K6: 2457 case CK_K6_2: 2458 case CK_K6_3: 2459 case CK_Athlon: 2460 case CK_AthlonThunderbird: 2461 case CK_Athlon4: 2462 case CK_AthlonXP: 2463 case CK_AthlonMP: 2464 case CK_Geode: 2465 // Only accept certain architectures when compiling in 32-bit mode. 2466 if (getTriple().getArch() != llvm::Triple::x86) 2467 return false; 2468 2469 // Fallthrough 2470 case CK_Nocona: 2471 case CK_Core2: 2472 case CK_Penryn: 2473 case CK_Bonnell: 2474 case CK_Silvermont: 2475 case CK_Nehalem: 2476 case CK_Westmere: 2477 case CK_SandyBridge: 2478 case CK_IvyBridge: 2479 case CK_Haswell: 2480 case CK_Broadwell: 2481 case CK_Skylake: 2482 case CK_KNL: 2483 case CK_Athlon64: 2484 case CK_Athlon64SSE3: 2485 case CK_AthlonFX: 2486 case CK_K8: 2487 case CK_K8SSE3: 2488 case CK_Opteron: 2489 case CK_OpteronSSE3: 2490 case CK_AMDFAM10: 2491 case CK_BTVER1: 2492 case CK_BTVER2: 2493 case CK_BDVER1: 2494 case CK_BDVER2: 2495 case CK_BDVER3: 2496 case CK_BDVER4: 2497 case CK_x86_64: 2498 return true; 2499 } 2500 llvm_unreachable("Unhandled CPU kind"); 2501 } 2502 2503 bool setFPMath(StringRef Name) override; 2504 2505 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2506 // We accept all non-ARM calling conventions 2507 return (CC == CC_X86ThisCall || 2508 CC == CC_X86FastCall || 2509 CC == CC_X86StdCall || 2510 CC == CC_X86VectorCall || 2511 CC == CC_C || 2512 CC == CC_X86Pascal || 2513 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2514 } 2515 2516 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2517 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2518 } 2519 2520 bool hasSjLjLowering() const override { 2521 return true; 2522 } 2523 }; 2524 2525 bool X86TargetInfo::setFPMath(StringRef Name) { 2526 if (Name == "387") { 2527 FPMath = FP_387; 2528 return true; 2529 } 2530 if (Name == "sse") { 2531 FPMath = FP_SSE; 2532 return true; 2533 } 2534 return false; 2535 } 2536 2537 bool X86TargetInfo::initFeatureMap( 2538 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2539 const std::vector<std::string> &FeaturesVec) const { 2540 // FIXME: This *really* should not be here. 2541 // X86_64 always has SSE2. 2542 if (getTriple().getArch() == llvm::Triple::x86_64) 2543 setFeatureEnabledImpl(Features, "sse2", true); 2544 2545 switch (getCPUKind(CPU)) { 2546 case CK_Generic: 2547 case CK_i386: 2548 case CK_i486: 2549 case CK_i586: 2550 case CK_Pentium: 2551 case CK_i686: 2552 case CK_PentiumPro: 2553 break; 2554 case CK_PentiumMMX: 2555 case CK_Pentium2: 2556 case CK_K6: 2557 case CK_WinChipC6: 2558 setFeatureEnabledImpl(Features, "mmx", true); 2559 break; 2560 case CK_Pentium3: 2561 case CK_Pentium3M: 2562 case CK_C3_2: 2563 setFeatureEnabledImpl(Features, "sse", true); 2564 setFeatureEnabledImpl(Features, "fxsr", true); 2565 break; 2566 case CK_PentiumM: 2567 case CK_Pentium4: 2568 case CK_Pentium4M: 2569 case CK_x86_64: 2570 setFeatureEnabledImpl(Features, "sse2", true); 2571 setFeatureEnabledImpl(Features, "fxsr", true); 2572 break; 2573 case CK_Yonah: 2574 case CK_Prescott: 2575 case CK_Nocona: 2576 setFeatureEnabledImpl(Features, "sse3", true); 2577 setFeatureEnabledImpl(Features, "fxsr", true); 2578 setFeatureEnabledImpl(Features, "cx16", true); 2579 break; 2580 case CK_Core2: 2581 case CK_Bonnell: 2582 setFeatureEnabledImpl(Features, "ssse3", true); 2583 setFeatureEnabledImpl(Features, "fxsr", true); 2584 setFeatureEnabledImpl(Features, "cx16", true); 2585 break; 2586 case CK_Penryn: 2587 setFeatureEnabledImpl(Features, "sse4.1", true); 2588 setFeatureEnabledImpl(Features, "fxsr", true); 2589 setFeatureEnabledImpl(Features, "cx16", true); 2590 break; 2591 case CK_Skylake: 2592 setFeatureEnabledImpl(Features, "avx512f", true); 2593 setFeatureEnabledImpl(Features, "avx512cd", true); 2594 setFeatureEnabledImpl(Features, "avx512dq", true); 2595 setFeatureEnabledImpl(Features, "avx512bw", true); 2596 setFeatureEnabledImpl(Features, "avx512vl", true); 2597 setFeatureEnabledImpl(Features, "xsavec", true); 2598 setFeatureEnabledImpl(Features, "xsaves", true); 2599 // FALLTHROUGH 2600 case CK_Broadwell: 2601 setFeatureEnabledImpl(Features, "rdseed", true); 2602 setFeatureEnabledImpl(Features, "adx", true); 2603 // FALLTHROUGH 2604 case CK_Haswell: 2605 setFeatureEnabledImpl(Features, "avx2", true); 2606 setFeatureEnabledImpl(Features, "lzcnt", true); 2607 setFeatureEnabledImpl(Features, "bmi", true); 2608 setFeatureEnabledImpl(Features, "bmi2", true); 2609 setFeatureEnabledImpl(Features, "rtm", true); 2610 setFeatureEnabledImpl(Features, "fma", true); 2611 // FALLTHROUGH 2612 case CK_IvyBridge: 2613 setFeatureEnabledImpl(Features, "rdrnd", true); 2614 setFeatureEnabledImpl(Features, "f16c", true); 2615 setFeatureEnabledImpl(Features, "fsgsbase", true); 2616 // FALLTHROUGH 2617 case CK_SandyBridge: 2618 setFeatureEnabledImpl(Features, "avx", true); 2619 setFeatureEnabledImpl(Features, "xsave", true); 2620 setFeatureEnabledImpl(Features, "xsaveopt", true); 2621 // FALLTHROUGH 2622 case CK_Westmere: 2623 case CK_Silvermont: 2624 setFeatureEnabledImpl(Features, "aes", true); 2625 setFeatureEnabledImpl(Features, "pclmul", true); 2626 // FALLTHROUGH 2627 case CK_Nehalem: 2628 setFeatureEnabledImpl(Features, "sse4.2", true); 2629 setFeatureEnabledImpl(Features, "fxsr", true); 2630 setFeatureEnabledImpl(Features, "cx16", true); 2631 break; 2632 case CK_KNL: 2633 setFeatureEnabledImpl(Features, "avx512f", true); 2634 setFeatureEnabledImpl(Features, "avx512cd", true); 2635 setFeatureEnabledImpl(Features, "avx512er", true); 2636 setFeatureEnabledImpl(Features, "avx512pf", true); 2637 setFeatureEnabledImpl(Features, "fxsr", true); 2638 setFeatureEnabledImpl(Features, "rdseed", true); 2639 setFeatureEnabledImpl(Features, "adx", true); 2640 setFeatureEnabledImpl(Features, "lzcnt", true); 2641 setFeatureEnabledImpl(Features, "bmi", true); 2642 setFeatureEnabledImpl(Features, "bmi2", true); 2643 setFeatureEnabledImpl(Features, "rtm", true); 2644 setFeatureEnabledImpl(Features, "fma", true); 2645 setFeatureEnabledImpl(Features, "rdrnd", true); 2646 setFeatureEnabledImpl(Features, "f16c", true); 2647 setFeatureEnabledImpl(Features, "fsgsbase", true); 2648 setFeatureEnabledImpl(Features, "aes", true); 2649 setFeatureEnabledImpl(Features, "pclmul", true); 2650 setFeatureEnabledImpl(Features, "cx16", true); 2651 setFeatureEnabledImpl(Features, "xsaveopt", true); 2652 setFeatureEnabledImpl(Features, "xsave", true); 2653 break; 2654 case CK_K6_2: 2655 case CK_K6_3: 2656 case CK_WinChip2: 2657 case CK_C3: 2658 setFeatureEnabledImpl(Features, "3dnow", true); 2659 break; 2660 case CK_Athlon: 2661 case CK_AthlonThunderbird: 2662 case CK_Geode: 2663 setFeatureEnabledImpl(Features, "3dnowa", true); 2664 break; 2665 case CK_Athlon4: 2666 case CK_AthlonXP: 2667 case CK_AthlonMP: 2668 setFeatureEnabledImpl(Features, "sse", true); 2669 setFeatureEnabledImpl(Features, "3dnowa", true); 2670 setFeatureEnabledImpl(Features, "fxsr", true); 2671 break; 2672 case CK_K8: 2673 case CK_Opteron: 2674 case CK_Athlon64: 2675 case CK_AthlonFX: 2676 setFeatureEnabledImpl(Features, "sse2", true); 2677 setFeatureEnabledImpl(Features, "3dnowa", true); 2678 setFeatureEnabledImpl(Features, "fxsr", true); 2679 break; 2680 case CK_AMDFAM10: 2681 setFeatureEnabledImpl(Features, "sse4a", true); 2682 setFeatureEnabledImpl(Features, "lzcnt", true); 2683 setFeatureEnabledImpl(Features, "popcnt", true); 2684 // FALLTHROUGH 2685 case CK_K8SSE3: 2686 case CK_OpteronSSE3: 2687 case CK_Athlon64SSE3: 2688 setFeatureEnabledImpl(Features, "sse3", true); 2689 setFeatureEnabledImpl(Features, "3dnowa", true); 2690 setFeatureEnabledImpl(Features, "fxsr", true); 2691 break; 2692 case CK_BTVER2: 2693 setFeatureEnabledImpl(Features, "avx", true); 2694 setFeatureEnabledImpl(Features, "aes", true); 2695 setFeatureEnabledImpl(Features, "pclmul", true); 2696 setFeatureEnabledImpl(Features, "bmi", true); 2697 setFeatureEnabledImpl(Features, "f16c", true); 2698 setFeatureEnabledImpl(Features, "xsaveopt", true); 2699 // FALLTHROUGH 2700 case CK_BTVER1: 2701 setFeatureEnabledImpl(Features, "ssse3", true); 2702 setFeatureEnabledImpl(Features, "sse4a", true); 2703 setFeatureEnabledImpl(Features, "lzcnt", true); 2704 setFeatureEnabledImpl(Features, "popcnt", true); 2705 setFeatureEnabledImpl(Features, "prfchw", true); 2706 setFeatureEnabledImpl(Features, "cx16", true); 2707 setFeatureEnabledImpl(Features, "fxsr", true); 2708 setFeatureEnabledImpl(Features, "xsave", true); 2709 break; 2710 case CK_BDVER4: 2711 setFeatureEnabledImpl(Features, "avx2", true); 2712 setFeatureEnabledImpl(Features, "bmi2", true); 2713 // FALLTHROUGH 2714 case CK_BDVER3: 2715 setFeatureEnabledImpl(Features, "fsgsbase", true); 2716 setFeatureEnabledImpl(Features, "xsaveopt", true); 2717 // FALLTHROUGH 2718 case CK_BDVER2: 2719 setFeatureEnabledImpl(Features, "bmi", true); 2720 setFeatureEnabledImpl(Features, "fma", true); 2721 setFeatureEnabledImpl(Features, "f16c", true); 2722 setFeatureEnabledImpl(Features, "tbm", true); 2723 // FALLTHROUGH 2724 case CK_BDVER1: 2725 // xop implies avx, sse4a and fma4. 2726 setFeatureEnabledImpl(Features, "xop", true); 2727 setFeatureEnabledImpl(Features, "lzcnt", true); 2728 setFeatureEnabledImpl(Features, "aes", true); 2729 setFeatureEnabledImpl(Features, "pclmul", true); 2730 setFeatureEnabledImpl(Features, "prfchw", true); 2731 setFeatureEnabledImpl(Features, "cx16", true); 2732 setFeatureEnabledImpl(Features, "fxsr", true); 2733 setFeatureEnabledImpl(Features, "xsave", true); 2734 break; 2735 } 2736 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 2737 return false; 2738 2739 // Can't do this earlier because we need to be able to explicitly enable 2740 // or disable these features and the things that they depend upon. 2741 2742 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2743 auto I = Features.find("sse4.2"); 2744 if (I != Features.end() && I->getValue() && 2745 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 2746 FeaturesVec.end()) 2747 Features["popcnt"] = true; 2748 2749 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2750 I = Features.find("3dnow"); 2751 if (I != Features.end() && I->getValue() && 2752 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 2753 FeaturesVec.end()) 2754 Features["prfchw"] = true; 2755 2756 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2757 // then enable MMX. 2758 I = Features.find("sse"); 2759 if (I != Features.end() && I->getValue() && 2760 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 2761 FeaturesVec.end()) 2762 Features["mmx"] = true; 2763 2764 return true; 2765 } 2766 2767 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2768 X86SSEEnum Level, bool Enabled) { 2769 if (Enabled) { 2770 switch (Level) { 2771 case AVX512F: 2772 Features["avx512f"] = true; 2773 case AVX2: 2774 Features["avx2"] = true; 2775 case AVX: 2776 Features["avx"] = true; 2777 Features["xsave"] = true; 2778 case SSE42: 2779 Features["sse4.2"] = true; 2780 case SSE41: 2781 Features["sse4.1"] = true; 2782 case SSSE3: 2783 Features["ssse3"] = true; 2784 case SSE3: 2785 Features["sse3"] = true; 2786 case SSE2: 2787 Features["sse2"] = true; 2788 case SSE1: 2789 Features["sse"] = true; 2790 case NoSSE: 2791 break; 2792 } 2793 return; 2794 } 2795 2796 switch (Level) { 2797 case NoSSE: 2798 case SSE1: 2799 Features["sse"] = false; 2800 case SSE2: 2801 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2802 Features["sha"] = false; 2803 case SSE3: 2804 Features["sse3"] = false; 2805 setXOPLevel(Features, NoXOP, false); 2806 case SSSE3: 2807 Features["ssse3"] = false; 2808 case SSE41: 2809 Features["sse4.1"] = false; 2810 case SSE42: 2811 Features["sse4.2"] = false; 2812 case AVX: 2813 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 2814 Features["xsaveopt"] = false; 2815 setXOPLevel(Features, FMA4, false); 2816 case AVX2: 2817 Features["avx2"] = false; 2818 case AVX512F: 2819 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2820 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2821 Features["avx512vl"] = false; 2822 } 2823 } 2824 2825 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2826 MMX3DNowEnum Level, bool Enabled) { 2827 if (Enabled) { 2828 switch (Level) { 2829 case AMD3DNowAthlon: 2830 Features["3dnowa"] = true; 2831 case AMD3DNow: 2832 Features["3dnow"] = true; 2833 case MMX: 2834 Features["mmx"] = true; 2835 case NoMMX3DNow: 2836 break; 2837 } 2838 return; 2839 } 2840 2841 switch (Level) { 2842 case NoMMX3DNow: 2843 case MMX: 2844 Features["mmx"] = false; 2845 case AMD3DNow: 2846 Features["3dnow"] = false; 2847 case AMD3DNowAthlon: 2848 Features["3dnowa"] = false; 2849 } 2850 } 2851 2852 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2853 bool Enabled) { 2854 if (Enabled) { 2855 switch (Level) { 2856 case XOP: 2857 Features["xop"] = true; 2858 case FMA4: 2859 Features["fma4"] = true; 2860 setSSELevel(Features, AVX, true); 2861 case SSE4A: 2862 Features["sse4a"] = true; 2863 setSSELevel(Features, SSE3, true); 2864 case NoXOP: 2865 break; 2866 } 2867 return; 2868 } 2869 2870 switch (Level) { 2871 case NoXOP: 2872 case SSE4A: 2873 Features["sse4a"] = false; 2874 case FMA4: 2875 Features["fma4"] = false; 2876 case XOP: 2877 Features["xop"] = false; 2878 } 2879 } 2880 2881 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2882 StringRef Name, bool Enabled) { 2883 // This is a bit of a hack to deal with the sse4 target feature when used 2884 // as part of the target attribute. We handle sse4 correctly everywhere 2885 // else. See below for more information on how we handle the sse4 options. 2886 if (Name != "sse4") 2887 Features[Name] = Enabled; 2888 2889 if (Name == "mmx") { 2890 setMMXLevel(Features, MMX, Enabled); 2891 } else if (Name == "sse") { 2892 setSSELevel(Features, SSE1, Enabled); 2893 } else if (Name == "sse2") { 2894 setSSELevel(Features, SSE2, Enabled); 2895 } else if (Name == "sse3") { 2896 setSSELevel(Features, SSE3, Enabled); 2897 } else if (Name == "ssse3") { 2898 setSSELevel(Features, SSSE3, Enabled); 2899 } else if (Name == "sse4.2") { 2900 setSSELevel(Features, SSE42, Enabled); 2901 } else if (Name == "sse4.1") { 2902 setSSELevel(Features, SSE41, Enabled); 2903 } else if (Name == "3dnow") { 2904 setMMXLevel(Features, AMD3DNow, Enabled); 2905 } else if (Name == "3dnowa") { 2906 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2907 } else if (Name == "aes") { 2908 if (Enabled) 2909 setSSELevel(Features, SSE2, Enabled); 2910 } else if (Name == "pclmul") { 2911 if (Enabled) 2912 setSSELevel(Features, SSE2, Enabled); 2913 } else if (Name == "avx") { 2914 setSSELevel(Features, AVX, Enabled); 2915 } else if (Name == "avx2") { 2916 setSSELevel(Features, AVX2, Enabled); 2917 } else if (Name == "avx512f") { 2918 setSSELevel(Features, AVX512F, Enabled); 2919 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2920 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2921 if (Enabled) 2922 setSSELevel(Features, AVX512F, Enabled); 2923 } else if (Name == "fma") { 2924 if (Enabled) 2925 setSSELevel(Features, AVX, Enabled); 2926 } else if (Name == "fma4") { 2927 setXOPLevel(Features, FMA4, Enabled); 2928 } else if (Name == "xop") { 2929 setXOPLevel(Features, XOP, Enabled); 2930 } else if (Name == "sse4a") { 2931 setXOPLevel(Features, SSE4A, Enabled); 2932 } else if (Name == "f16c") { 2933 if (Enabled) 2934 setSSELevel(Features, AVX, Enabled); 2935 } else if (Name == "sha") { 2936 if (Enabled) 2937 setSSELevel(Features, SSE2, Enabled); 2938 } else if (Name == "sse4") { 2939 // We can get here via the __target__ attribute since that's not controlled 2940 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 2941 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 2942 // disabled. 2943 if (Enabled) 2944 setSSELevel(Features, SSE42, Enabled); 2945 else 2946 setSSELevel(Features, SSE41, Enabled); 2947 } else if (Name == "xsave") { 2948 if (Enabled) 2949 setSSELevel(Features, AVX, Enabled); 2950 else 2951 Features["xsaveopt"] = false; 2952 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 2953 if (Enabled) { 2954 Features["xsave"] = true; 2955 setSSELevel(Features, AVX, Enabled); 2956 } 2957 } 2958 } 2959 2960 /// handleTargetFeatures - Perform initialization based on the user 2961 /// configured set of features. 2962 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2963 DiagnosticsEngine &Diags) { 2964 for (const auto &Feature : Features) { 2965 if (Feature[0] != '+') 2966 continue; 2967 2968 if (Feature == "+aes") { 2969 HasAES = true; 2970 } else if (Feature == "+pclmul") { 2971 HasPCLMUL = true; 2972 } else if (Feature == "+lzcnt") { 2973 HasLZCNT = true; 2974 } else if (Feature == "+rdrnd") { 2975 HasRDRND = true; 2976 } else if (Feature == "+fsgsbase") { 2977 HasFSGSBASE = true; 2978 } else if (Feature == "+bmi") { 2979 HasBMI = true; 2980 } else if (Feature == "+bmi2") { 2981 HasBMI2 = true; 2982 } else if (Feature == "+popcnt") { 2983 HasPOPCNT = true; 2984 } else if (Feature == "+rtm") { 2985 HasRTM = true; 2986 } else if (Feature == "+prfchw") { 2987 HasPRFCHW = true; 2988 } else if (Feature == "+rdseed") { 2989 HasRDSEED = true; 2990 } else if (Feature == "+adx") { 2991 HasADX = true; 2992 } else if (Feature == "+tbm") { 2993 HasTBM = true; 2994 } else if (Feature == "+fma") { 2995 HasFMA = true; 2996 } else if (Feature == "+f16c") { 2997 HasF16C = true; 2998 } else if (Feature == "+avx512cd") { 2999 HasAVX512CD = true; 3000 } else if (Feature == "+avx512er") { 3001 HasAVX512ER = true; 3002 } else if (Feature == "+avx512pf") { 3003 HasAVX512PF = true; 3004 } else if (Feature == "+avx512dq") { 3005 HasAVX512DQ = true; 3006 } else if (Feature == "+avx512bw") { 3007 HasAVX512BW = true; 3008 } else if (Feature == "+avx512vl") { 3009 HasAVX512VL = true; 3010 } else if (Feature == "+sha") { 3011 HasSHA = true; 3012 } else if (Feature == "+cx16") { 3013 HasCX16 = true; 3014 } else if (Feature == "+fxsr") { 3015 HasFXSR = true; 3016 } else if (Feature == "+xsave") { 3017 HasXSAVE = true; 3018 } else if (Feature == "+xsaveopt") { 3019 HasXSAVEOPT = true; 3020 } else if (Feature == "+xsavec") { 3021 HasXSAVEC = true; 3022 } else if (Feature == "+xsaves") { 3023 HasXSAVES = true; 3024 } 3025 3026 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3027 .Case("+avx512f", AVX512F) 3028 .Case("+avx2", AVX2) 3029 .Case("+avx", AVX) 3030 .Case("+sse4.2", SSE42) 3031 .Case("+sse4.1", SSE41) 3032 .Case("+ssse3", SSSE3) 3033 .Case("+sse3", SSE3) 3034 .Case("+sse2", SSE2) 3035 .Case("+sse", SSE1) 3036 .Default(NoSSE); 3037 SSELevel = std::max(SSELevel, Level); 3038 3039 MMX3DNowEnum ThreeDNowLevel = 3040 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3041 .Case("+3dnowa", AMD3DNowAthlon) 3042 .Case("+3dnow", AMD3DNow) 3043 .Case("+mmx", MMX) 3044 .Default(NoMMX3DNow); 3045 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3046 3047 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3048 .Case("+xop", XOP) 3049 .Case("+fma4", FMA4) 3050 .Case("+sse4a", SSE4A) 3051 .Default(NoXOP); 3052 XOPLevel = std::max(XOPLevel, XLevel); 3053 } 3054 3055 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3056 // matches the selected sse level. 3057 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3058 (FPMath == FP_387 && SSELevel >= SSE1)) { 3059 Diags.Report(diag::err_target_unsupported_fpmath) << 3060 (FPMath == FP_SSE ? "sse" : "387"); 3061 return false; 3062 } 3063 3064 SimdDefaultAlign = 3065 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3066 return true; 3067 } 3068 3069 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3070 /// definitions for this particular subtarget. 3071 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3072 MacroBuilder &Builder) const { 3073 // Target identification. 3074 if (getTriple().getArch() == llvm::Triple::x86_64) { 3075 Builder.defineMacro("__amd64__"); 3076 Builder.defineMacro("__amd64"); 3077 Builder.defineMacro("__x86_64"); 3078 Builder.defineMacro("__x86_64__"); 3079 if (getTriple().getArchName() == "x86_64h") { 3080 Builder.defineMacro("__x86_64h"); 3081 Builder.defineMacro("__x86_64h__"); 3082 } 3083 } else { 3084 DefineStd(Builder, "i386", Opts); 3085 } 3086 3087 // Subtarget options. 3088 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3089 // truly should be based on -mtune options. 3090 switch (CPU) { 3091 case CK_Generic: 3092 break; 3093 case CK_i386: 3094 // The rest are coming from the i386 define above. 3095 Builder.defineMacro("__tune_i386__"); 3096 break; 3097 case CK_i486: 3098 case CK_WinChipC6: 3099 case CK_WinChip2: 3100 case CK_C3: 3101 defineCPUMacros(Builder, "i486"); 3102 break; 3103 case CK_PentiumMMX: 3104 Builder.defineMacro("__pentium_mmx__"); 3105 Builder.defineMacro("__tune_pentium_mmx__"); 3106 // Fallthrough 3107 case CK_i586: 3108 case CK_Pentium: 3109 defineCPUMacros(Builder, "i586"); 3110 defineCPUMacros(Builder, "pentium"); 3111 break; 3112 case CK_Pentium3: 3113 case CK_Pentium3M: 3114 case CK_PentiumM: 3115 Builder.defineMacro("__tune_pentium3__"); 3116 // Fallthrough 3117 case CK_Pentium2: 3118 case CK_C3_2: 3119 Builder.defineMacro("__tune_pentium2__"); 3120 // Fallthrough 3121 case CK_PentiumPro: 3122 Builder.defineMacro("__tune_i686__"); 3123 Builder.defineMacro("__tune_pentiumpro__"); 3124 // Fallthrough 3125 case CK_i686: 3126 Builder.defineMacro("__i686"); 3127 Builder.defineMacro("__i686__"); 3128 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3129 Builder.defineMacro("__pentiumpro"); 3130 Builder.defineMacro("__pentiumpro__"); 3131 break; 3132 case CK_Pentium4: 3133 case CK_Pentium4M: 3134 defineCPUMacros(Builder, "pentium4"); 3135 break; 3136 case CK_Yonah: 3137 case CK_Prescott: 3138 case CK_Nocona: 3139 defineCPUMacros(Builder, "nocona"); 3140 break; 3141 case CK_Core2: 3142 case CK_Penryn: 3143 defineCPUMacros(Builder, "core2"); 3144 break; 3145 case CK_Bonnell: 3146 defineCPUMacros(Builder, "atom"); 3147 break; 3148 case CK_Silvermont: 3149 defineCPUMacros(Builder, "slm"); 3150 break; 3151 case CK_Nehalem: 3152 case CK_Westmere: 3153 case CK_SandyBridge: 3154 case CK_IvyBridge: 3155 case CK_Haswell: 3156 case CK_Broadwell: 3157 // FIXME: Historically, we defined this legacy name, it would be nice to 3158 // remove it at some point. We've never exposed fine-grained names for 3159 // recent primary x86 CPUs, and we should keep it that way. 3160 defineCPUMacros(Builder, "corei7"); 3161 break; 3162 case CK_Skylake: 3163 // FIXME: Historically, we defined this legacy name, it would be nice to 3164 // remove it at some point. This is the only fine-grained CPU macro in the 3165 // main intel CPU line, and it would be better to not have these and force 3166 // people to use ISA macros. 3167 defineCPUMacros(Builder, "skx"); 3168 break; 3169 case CK_KNL: 3170 defineCPUMacros(Builder, "knl"); 3171 break; 3172 case CK_K6_2: 3173 Builder.defineMacro("__k6_2__"); 3174 Builder.defineMacro("__tune_k6_2__"); 3175 // Fallthrough 3176 case CK_K6_3: 3177 if (CPU != CK_K6_2) { // In case of fallthrough 3178 // FIXME: GCC may be enabling these in cases where some other k6 3179 // architecture is specified but -m3dnow is explicitly provided. The 3180 // exact semantics need to be determined and emulated here. 3181 Builder.defineMacro("__k6_3__"); 3182 Builder.defineMacro("__tune_k6_3__"); 3183 } 3184 // Fallthrough 3185 case CK_K6: 3186 defineCPUMacros(Builder, "k6"); 3187 break; 3188 case CK_Athlon: 3189 case CK_AthlonThunderbird: 3190 case CK_Athlon4: 3191 case CK_AthlonXP: 3192 case CK_AthlonMP: 3193 defineCPUMacros(Builder, "athlon"); 3194 if (SSELevel != NoSSE) { 3195 Builder.defineMacro("__athlon_sse__"); 3196 Builder.defineMacro("__tune_athlon_sse__"); 3197 } 3198 break; 3199 case CK_K8: 3200 case CK_K8SSE3: 3201 case CK_x86_64: 3202 case CK_Opteron: 3203 case CK_OpteronSSE3: 3204 case CK_Athlon64: 3205 case CK_Athlon64SSE3: 3206 case CK_AthlonFX: 3207 defineCPUMacros(Builder, "k8"); 3208 break; 3209 case CK_AMDFAM10: 3210 defineCPUMacros(Builder, "amdfam10"); 3211 break; 3212 case CK_BTVER1: 3213 defineCPUMacros(Builder, "btver1"); 3214 break; 3215 case CK_BTVER2: 3216 defineCPUMacros(Builder, "btver2"); 3217 break; 3218 case CK_BDVER1: 3219 defineCPUMacros(Builder, "bdver1"); 3220 break; 3221 case CK_BDVER2: 3222 defineCPUMacros(Builder, "bdver2"); 3223 break; 3224 case CK_BDVER3: 3225 defineCPUMacros(Builder, "bdver3"); 3226 break; 3227 case CK_BDVER4: 3228 defineCPUMacros(Builder, "bdver4"); 3229 break; 3230 case CK_Geode: 3231 defineCPUMacros(Builder, "geode"); 3232 break; 3233 } 3234 3235 // Target properties. 3236 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3237 3238 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3239 // functions in glibc header files that use FP Stack inline asm which the 3240 // backend can't deal with (PR879). 3241 Builder.defineMacro("__NO_MATH_INLINES"); 3242 3243 if (HasAES) 3244 Builder.defineMacro("__AES__"); 3245 3246 if (HasPCLMUL) 3247 Builder.defineMacro("__PCLMUL__"); 3248 3249 if (HasLZCNT) 3250 Builder.defineMacro("__LZCNT__"); 3251 3252 if (HasRDRND) 3253 Builder.defineMacro("__RDRND__"); 3254 3255 if (HasFSGSBASE) 3256 Builder.defineMacro("__FSGSBASE__"); 3257 3258 if (HasBMI) 3259 Builder.defineMacro("__BMI__"); 3260 3261 if (HasBMI2) 3262 Builder.defineMacro("__BMI2__"); 3263 3264 if (HasPOPCNT) 3265 Builder.defineMacro("__POPCNT__"); 3266 3267 if (HasRTM) 3268 Builder.defineMacro("__RTM__"); 3269 3270 if (HasPRFCHW) 3271 Builder.defineMacro("__PRFCHW__"); 3272 3273 if (HasRDSEED) 3274 Builder.defineMacro("__RDSEED__"); 3275 3276 if (HasADX) 3277 Builder.defineMacro("__ADX__"); 3278 3279 if (HasTBM) 3280 Builder.defineMacro("__TBM__"); 3281 3282 switch (XOPLevel) { 3283 case XOP: 3284 Builder.defineMacro("__XOP__"); 3285 case FMA4: 3286 Builder.defineMacro("__FMA4__"); 3287 case SSE4A: 3288 Builder.defineMacro("__SSE4A__"); 3289 case NoXOP: 3290 break; 3291 } 3292 3293 if (HasFMA) 3294 Builder.defineMacro("__FMA__"); 3295 3296 if (HasF16C) 3297 Builder.defineMacro("__F16C__"); 3298 3299 if (HasAVX512CD) 3300 Builder.defineMacro("__AVX512CD__"); 3301 if (HasAVX512ER) 3302 Builder.defineMacro("__AVX512ER__"); 3303 if (HasAVX512PF) 3304 Builder.defineMacro("__AVX512PF__"); 3305 if (HasAVX512DQ) 3306 Builder.defineMacro("__AVX512DQ__"); 3307 if (HasAVX512BW) 3308 Builder.defineMacro("__AVX512BW__"); 3309 if (HasAVX512VL) 3310 Builder.defineMacro("__AVX512VL__"); 3311 3312 if (HasSHA) 3313 Builder.defineMacro("__SHA__"); 3314 3315 if (HasFXSR) 3316 Builder.defineMacro("__FXSR__"); 3317 if (HasXSAVE) 3318 Builder.defineMacro("__XSAVE__"); 3319 if (HasXSAVEOPT) 3320 Builder.defineMacro("__XSAVEOPT__"); 3321 if (HasXSAVEC) 3322 Builder.defineMacro("__XSAVEC__"); 3323 if (HasXSAVES) 3324 Builder.defineMacro("__XSAVES__"); 3325 3326 if (HasCX16) 3327 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3328 3329 // Each case falls through to the previous one here. 3330 switch (SSELevel) { 3331 case AVX512F: 3332 Builder.defineMacro("__AVX512F__"); 3333 case AVX2: 3334 Builder.defineMacro("__AVX2__"); 3335 case AVX: 3336 Builder.defineMacro("__AVX__"); 3337 case SSE42: 3338 Builder.defineMacro("__SSE4_2__"); 3339 case SSE41: 3340 Builder.defineMacro("__SSE4_1__"); 3341 case SSSE3: 3342 Builder.defineMacro("__SSSE3__"); 3343 case SSE3: 3344 Builder.defineMacro("__SSE3__"); 3345 case SSE2: 3346 Builder.defineMacro("__SSE2__"); 3347 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3348 case SSE1: 3349 Builder.defineMacro("__SSE__"); 3350 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3351 case NoSSE: 3352 break; 3353 } 3354 3355 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3356 switch (SSELevel) { 3357 case AVX512F: 3358 case AVX2: 3359 case AVX: 3360 case SSE42: 3361 case SSE41: 3362 case SSSE3: 3363 case SSE3: 3364 case SSE2: 3365 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3366 break; 3367 case SSE1: 3368 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3369 break; 3370 default: 3371 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3372 } 3373 } 3374 3375 // Each case falls through to the previous one here. 3376 switch (MMX3DNowLevel) { 3377 case AMD3DNowAthlon: 3378 Builder.defineMacro("__3dNOW_A__"); 3379 case AMD3DNow: 3380 Builder.defineMacro("__3dNOW__"); 3381 case MMX: 3382 Builder.defineMacro("__MMX__"); 3383 case NoMMX3DNow: 3384 break; 3385 } 3386 3387 if (CPU >= CK_i486) { 3388 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3389 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3390 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3391 } 3392 if (CPU >= CK_i586) 3393 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3394 } 3395 3396 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3397 return llvm::StringSwitch<bool>(Feature) 3398 .Case("aes", HasAES) 3399 .Case("avx", SSELevel >= AVX) 3400 .Case("avx2", SSELevel >= AVX2) 3401 .Case("avx512f", SSELevel >= AVX512F) 3402 .Case("avx512cd", HasAVX512CD) 3403 .Case("avx512er", HasAVX512ER) 3404 .Case("avx512pf", HasAVX512PF) 3405 .Case("avx512dq", HasAVX512DQ) 3406 .Case("avx512bw", HasAVX512BW) 3407 .Case("avx512vl", HasAVX512VL) 3408 .Case("bmi", HasBMI) 3409 .Case("bmi2", HasBMI2) 3410 .Case("cx16", HasCX16) 3411 .Case("f16c", HasF16C) 3412 .Case("fma", HasFMA) 3413 .Case("fma4", XOPLevel >= FMA4) 3414 .Case("fsgsbase", HasFSGSBASE) 3415 .Case("fxsr", HasFXSR) 3416 .Case("lzcnt", HasLZCNT) 3417 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3418 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3419 .Case("mmx", MMX3DNowLevel >= MMX) 3420 .Case("pclmul", HasPCLMUL) 3421 .Case("popcnt", HasPOPCNT) 3422 .Case("prfchw", HasPRFCHW) 3423 .Case("rdrnd", HasRDRND) 3424 .Case("rdseed", HasRDSEED) 3425 .Case("rtm", HasRTM) 3426 .Case("sha", HasSHA) 3427 .Case("sse", SSELevel >= SSE1) 3428 .Case("sse2", SSELevel >= SSE2) 3429 .Case("sse3", SSELevel >= SSE3) 3430 .Case("ssse3", SSELevel >= SSSE3) 3431 .Case("sse4.1", SSELevel >= SSE41) 3432 .Case("sse4.2", SSELevel >= SSE42) 3433 .Case("sse4a", XOPLevel >= SSE4A) 3434 .Case("tbm", HasTBM) 3435 .Case("x86", true) 3436 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3437 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3438 .Case("xop", XOPLevel >= XOP) 3439 .Case("xsave", HasXSAVE) 3440 .Case("xsavec", HasXSAVEC) 3441 .Case("xsaves", HasXSAVES) 3442 .Case("xsaveopt", HasXSAVEOPT) 3443 .Default(false); 3444 } 3445 3446 // We can't use a generic validation scheme for the features accepted here 3447 // versus subtarget features accepted in the target attribute because the 3448 // bitfield structure that's initialized in the runtime only supports the 3449 // below currently rather than the full range of subtarget features. (See 3450 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3451 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3452 return llvm::StringSwitch<bool>(FeatureStr) 3453 .Case("cmov", true) 3454 .Case("mmx", true) 3455 .Case("popcnt", true) 3456 .Case("sse", true) 3457 .Case("sse2", true) 3458 .Case("sse3", true) 3459 .Case("sse4.1", true) 3460 .Case("sse4.2", true) 3461 .Case("avx", true) 3462 .Case("avx2", true) 3463 .Case("sse4a", true) 3464 .Case("fma4", true) 3465 .Case("xop", true) 3466 .Case("fma", true) 3467 .Case("avx512f", true) 3468 .Case("bmi", true) 3469 .Case("bmi2", true) 3470 .Default(false); 3471 } 3472 3473 bool 3474 X86TargetInfo::validateAsmConstraint(const char *&Name, 3475 TargetInfo::ConstraintInfo &Info) const { 3476 switch (*Name) { 3477 default: return false; 3478 // Constant constraints. 3479 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3480 // instructions. 3481 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3482 // x86_64 instructions. 3483 case 's': 3484 Info.setRequiresImmediate(); 3485 return true; 3486 case 'I': 3487 Info.setRequiresImmediate(0, 31); 3488 return true; 3489 case 'J': 3490 Info.setRequiresImmediate(0, 63); 3491 return true; 3492 case 'K': 3493 Info.setRequiresImmediate(-128, 127); 3494 return true; 3495 case 'L': 3496 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3497 return true; 3498 case 'M': 3499 Info.setRequiresImmediate(0, 3); 3500 return true; 3501 case 'N': 3502 Info.setRequiresImmediate(0, 255); 3503 return true; 3504 case 'O': 3505 Info.setRequiresImmediate(0, 127); 3506 return true; 3507 // Register constraints. 3508 case 'Y': // 'Y' is the first character for several 2-character constraints. 3509 // Shift the pointer to the second character of the constraint. 3510 Name++; 3511 switch (*Name) { 3512 default: 3513 return false; 3514 case '0': // First SSE register. 3515 case 't': // Any SSE register, when SSE2 is enabled. 3516 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3517 case 'm': // Any MMX register, when inter-unit moves enabled. 3518 Info.setAllowsRegister(); 3519 return true; 3520 } 3521 case 'f': // Any x87 floating point stack register. 3522 // Constraint 'f' cannot be used for output operands. 3523 if (Info.ConstraintStr[0] == '=') 3524 return false; 3525 Info.setAllowsRegister(); 3526 return true; 3527 case 'a': // eax. 3528 case 'b': // ebx. 3529 case 'c': // ecx. 3530 case 'd': // edx. 3531 case 'S': // esi. 3532 case 'D': // edi. 3533 case 'A': // edx:eax. 3534 case 't': // Top of floating point stack. 3535 case 'u': // Second from top of floating point stack. 3536 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3537 case 'y': // Any MMX register. 3538 case 'x': // Any SSE register. 3539 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3540 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3541 case 'l': // "Index" registers: any general register that can be used as an 3542 // index in a base+index memory access. 3543 Info.setAllowsRegister(); 3544 return true; 3545 // Floating point constant constraints. 3546 case 'C': // SSE floating point constant. 3547 case 'G': // x87 floating point constant. 3548 return true; 3549 } 3550 } 3551 3552 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3553 unsigned Size) const { 3554 // Strip off constraint modifiers. 3555 while (Constraint[0] == '=' || 3556 Constraint[0] == '+' || 3557 Constraint[0] == '&') 3558 Constraint = Constraint.substr(1); 3559 3560 return validateOperandSize(Constraint, Size); 3561 } 3562 3563 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3564 unsigned Size) const { 3565 return validateOperandSize(Constraint, Size); 3566 } 3567 3568 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3569 unsigned Size) const { 3570 switch (Constraint[0]) { 3571 default: break; 3572 case 'y': 3573 return Size <= 64; 3574 case 'f': 3575 case 't': 3576 case 'u': 3577 return Size <= 128; 3578 case 'x': 3579 if (SSELevel >= AVX512F) 3580 // 512-bit zmm registers can be used if target supports AVX512F. 3581 return Size <= 512U; 3582 else if (SSELevel >= AVX) 3583 // 256-bit ymm registers can be used if target supports AVX. 3584 return Size <= 256U; 3585 return Size <= 128U; 3586 case 'Y': 3587 // 'Y' is the first character for several 2-character constraints. 3588 switch (Constraint[1]) { 3589 default: break; 3590 case 'm': 3591 // 'Ym' is synonymous with 'y'. 3592 return Size <= 64; 3593 case 'i': 3594 case 't': 3595 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3596 if (SSELevel >= AVX512F) 3597 return Size <= 512U; 3598 else if (SSELevel >= AVX) 3599 return Size <= 256U; 3600 return SSELevel >= SSE2 && Size <= 128U; 3601 } 3602 3603 } 3604 3605 return true; 3606 } 3607 3608 std::string 3609 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3610 switch (*Constraint) { 3611 case 'a': return std::string("{ax}"); 3612 case 'b': return std::string("{bx}"); 3613 case 'c': return std::string("{cx}"); 3614 case 'd': return std::string("{dx}"); 3615 case 'S': return std::string("{si}"); 3616 case 'D': return std::string("{di}"); 3617 case 'p': // address 3618 return std::string("im"); 3619 case 't': // top of floating point stack. 3620 return std::string("{st}"); 3621 case 'u': // second from top of floating point stack. 3622 return std::string("{st(1)}"); // second from top of floating point stack. 3623 default: 3624 return std::string(1, *Constraint); 3625 } 3626 } 3627 3628 // X86-32 generic target 3629 class X86_32TargetInfo : public X86TargetInfo { 3630 public: 3631 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3632 DoubleAlign = LongLongAlign = 32; 3633 LongDoubleWidth = 96; 3634 LongDoubleAlign = 32; 3635 SuitableAlign = 128; 3636 DataLayoutString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3637 SizeType = UnsignedInt; 3638 PtrDiffType = SignedInt; 3639 IntPtrType = SignedInt; 3640 RegParmMax = 3; 3641 3642 // Use fpret for all types. 3643 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3644 (1 << TargetInfo::Double) | 3645 (1 << TargetInfo::LongDouble)); 3646 3647 // x86-32 has atomics up to 8 bytes 3648 // FIXME: Check that we actually have cmpxchg8b before setting 3649 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3650 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3651 } 3652 BuiltinVaListKind getBuiltinVaListKind() const override { 3653 return TargetInfo::CharPtrBuiltinVaList; 3654 } 3655 3656 int getEHDataRegisterNumber(unsigned RegNo) const override { 3657 if (RegNo == 0) return 0; 3658 if (RegNo == 1) return 2; 3659 return -1; 3660 } 3661 bool validateOperandSize(StringRef Constraint, 3662 unsigned Size) const override { 3663 switch (Constraint[0]) { 3664 default: break; 3665 case 'R': 3666 case 'q': 3667 case 'Q': 3668 case 'a': 3669 case 'b': 3670 case 'c': 3671 case 'd': 3672 case 'S': 3673 case 'D': 3674 return Size <= 32; 3675 case 'A': 3676 return Size <= 64; 3677 } 3678 3679 return X86TargetInfo::validateOperandSize(Constraint, Size); 3680 } 3681 }; 3682 3683 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3684 public: 3685 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3686 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3687 3688 unsigned getFloatEvalMethod() const override { 3689 unsigned Major, Minor, Micro; 3690 getTriple().getOSVersion(Major, Minor, Micro); 3691 // New NetBSD uses the default rounding mode. 3692 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3693 return X86_32TargetInfo::getFloatEvalMethod(); 3694 // NetBSD before 6.99.26 defaults to "double" rounding. 3695 return 1; 3696 } 3697 }; 3698 3699 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3700 public: 3701 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3702 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3703 SizeType = UnsignedLong; 3704 IntPtrType = SignedLong; 3705 PtrDiffType = SignedLong; 3706 } 3707 }; 3708 3709 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3710 public: 3711 BitrigI386TargetInfo(const llvm::Triple &Triple) 3712 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3713 SizeType = UnsignedLong; 3714 IntPtrType = SignedLong; 3715 PtrDiffType = SignedLong; 3716 } 3717 }; 3718 3719 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3720 public: 3721 DarwinI386TargetInfo(const llvm::Triple &Triple) 3722 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3723 LongDoubleWidth = 128; 3724 LongDoubleAlign = 128; 3725 SuitableAlign = 128; 3726 MaxVectorAlign = 256; 3727 // The watchOS simulator uses the builtin bool type for Objective-C. 3728 llvm::Triple T = llvm::Triple(Triple); 3729 if (T.isWatchOS()) 3730 UseSignedCharForObjCBool = false; 3731 SizeType = UnsignedLong; 3732 IntPtrType = SignedLong; 3733 DataLayoutString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3734 HasAlignMac68kSupport = true; 3735 } 3736 3737 bool handleTargetFeatures(std::vector<std::string> &Features, 3738 DiagnosticsEngine &Diags) override { 3739 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 3740 Diags)) 3741 return false; 3742 // We now know the features we have: we can decide how to align vectors. 3743 MaxVectorAlign = 3744 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3745 return true; 3746 } 3747 }; 3748 3749 // x86-32 Windows target 3750 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3751 public: 3752 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3753 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3754 WCharType = UnsignedShort; 3755 DoubleAlign = LongLongAlign = 64; 3756 bool IsWinCOFF = 3757 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3758 DataLayoutString = IsWinCOFF 3759 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3760 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3761 } 3762 void getTargetDefines(const LangOptions &Opts, 3763 MacroBuilder &Builder) const override { 3764 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3765 } 3766 }; 3767 3768 // x86-32 Windows Visual Studio target 3769 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3770 public: 3771 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3772 : WindowsX86_32TargetInfo(Triple) { 3773 LongDoubleWidth = LongDoubleAlign = 64; 3774 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3775 } 3776 void getTargetDefines(const LangOptions &Opts, 3777 MacroBuilder &Builder) const override { 3778 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3779 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3780 // The value of the following reflects processor type. 3781 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3782 // We lost the original triple, so we use the default. 3783 Builder.defineMacro("_M_IX86", "600"); 3784 } 3785 }; 3786 3787 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3788 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 3789 // supports __declspec natively under -fms-extensions, but we define a no-op 3790 // __declspec macro anyway for pre-processor compatibility. 3791 if (Opts.MicrosoftExt) 3792 Builder.defineMacro("__declspec", "__declspec"); 3793 else 3794 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3795 3796 if (!Opts.MicrosoftExt) { 3797 // Provide macros for all the calling convention keywords. Provide both 3798 // single and double underscore prefixed variants. These are available on 3799 // x64 as well as x86, even though they have no effect. 3800 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3801 for (const char *CC : CCs) { 3802 std::string GCCSpelling = "__attribute__((__"; 3803 GCCSpelling += CC; 3804 GCCSpelling += "__))"; 3805 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3806 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3807 } 3808 } 3809 } 3810 3811 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3812 Builder.defineMacro("__MSVCRT__"); 3813 Builder.defineMacro("__MINGW32__"); 3814 addCygMingDefines(Opts, Builder); 3815 } 3816 3817 // x86-32 MinGW target 3818 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3819 public: 3820 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3821 : WindowsX86_32TargetInfo(Triple) {} 3822 void getTargetDefines(const LangOptions &Opts, 3823 MacroBuilder &Builder) const override { 3824 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3825 DefineStd(Builder, "WIN32", Opts); 3826 DefineStd(Builder, "WINNT", Opts); 3827 Builder.defineMacro("_X86_"); 3828 addMinGWDefines(Opts, Builder); 3829 } 3830 }; 3831 3832 // x86-32 Cygwin target 3833 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3834 public: 3835 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3836 : X86_32TargetInfo(Triple) { 3837 TLSSupported = false; 3838 WCharType = UnsignedShort; 3839 DoubleAlign = LongLongAlign = 64; 3840 DataLayoutString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3841 } 3842 void getTargetDefines(const LangOptions &Opts, 3843 MacroBuilder &Builder) const override { 3844 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3845 Builder.defineMacro("_X86_"); 3846 Builder.defineMacro("__CYGWIN__"); 3847 Builder.defineMacro("__CYGWIN32__"); 3848 addCygMingDefines(Opts, Builder); 3849 DefineStd(Builder, "unix", Opts); 3850 if (Opts.CPlusPlus) 3851 Builder.defineMacro("_GNU_SOURCE"); 3852 } 3853 }; 3854 3855 // x86-32 Haiku target 3856 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3857 public: 3858 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3859 SizeType = UnsignedLong; 3860 IntPtrType = SignedLong; 3861 PtrDiffType = SignedLong; 3862 ProcessIDType = SignedLong; 3863 this->UserLabelPrefix = ""; 3864 this->TLSSupported = false; 3865 } 3866 void getTargetDefines(const LangOptions &Opts, 3867 MacroBuilder &Builder) const override { 3868 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3869 Builder.defineMacro("__INTEL__"); 3870 Builder.defineMacro("__HAIKU__"); 3871 } 3872 }; 3873 3874 // X86-32 MCU target 3875 class MCUX86_32TargetInfo : public X86_32TargetInfo { 3876 public: 3877 MCUX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3878 LongDoubleWidth = 64; 3879 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3880 } 3881 3882 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3883 // On MCU we support only C calling convention. 3884 return CC == CC_C ? CCCR_OK : CCCR_Warning; 3885 } 3886 3887 void getTargetDefines(const LangOptions &Opts, 3888 MacroBuilder &Builder) const override { 3889 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3890 Builder.defineMacro("__iamcu"); 3891 Builder.defineMacro("__iamcu__"); 3892 } 3893 }; 3894 3895 // RTEMS Target 3896 template<typename Target> 3897 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3898 protected: 3899 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3900 MacroBuilder &Builder) const override { 3901 // RTEMS defines; list based off of gcc output 3902 3903 Builder.defineMacro("__rtems__"); 3904 Builder.defineMacro("__ELF__"); 3905 } 3906 3907 public: 3908 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3909 this->UserLabelPrefix = ""; 3910 3911 switch (Triple.getArch()) { 3912 default: 3913 case llvm::Triple::x86: 3914 // this->MCountName = ".mcount"; 3915 break; 3916 case llvm::Triple::mips: 3917 case llvm::Triple::mipsel: 3918 case llvm::Triple::ppc: 3919 case llvm::Triple::ppc64: 3920 case llvm::Triple::ppc64le: 3921 // this->MCountName = "_mcount"; 3922 break; 3923 case llvm::Triple::arm: 3924 // this->MCountName = "__mcount"; 3925 break; 3926 } 3927 } 3928 }; 3929 3930 // x86-32 RTEMS target 3931 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3932 public: 3933 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3934 SizeType = UnsignedLong; 3935 IntPtrType = SignedLong; 3936 PtrDiffType = SignedLong; 3937 this->UserLabelPrefix = ""; 3938 } 3939 void getTargetDefines(const LangOptions &Opts, 3940 MacroBuilder &Builder) const override { 3941 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3942 Builder.defineMacro("__INTEL__"); 3943 Builder.defineMacro("__rtems__"); 3944 } 3945 }; 3946 3947 // x86-64 generic target 3948 class X86_64TargetInfo : public X86TargetInfo { 3949 public: 3950 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3951 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3952 bool IsWinCOFF = 3953 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3954 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3955 LongDoubleWidth = 128; 3956 LongDoubleAlign = 128; 3957 LargeArrayMinWidth = 128; 3958 LargeArrayAlign = 128; 3959 SuitableAlign = 128; 3960 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3961 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3962 IntPtrType = IsX32 ? SignedInt : SignedLong; 3963 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3964 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3965 RegParmMax = 6; 3966 3967 // Pointers are 32-bit in x32. 3968 DataLayoutString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3969 : IsWinCOFF 3970 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 3971 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3972 3973 // Use fpret only for long double. 3974 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3975 3976 // Use fp2ret for _Complex long double. 3977 ComplexLongDoubleUsesFP2Ret = true; 3978 3979 // Make __builtin_ms_va_list available. 3980 HasBuiltinMSVaList = true; 3981 3982 // x86-64 has atomics up to 16 bytes. 3983 MaxAtomicPromoteWidth = 128; 3984 MaxAtomicInlineWidth = 128; 3985 } 3986 BuiltinVaListKind getBuiltinVaListKind() const override { 3987 return TargetInfo::X86_64ABIBuiltinVaList; 3988 } 3989 3990 int getEHDataRegisterNumber(unsigned RegNo) const override { 3991 if (RegNo == 0) return 0; 3992 if (RegNo == 1) return 1; 3993 return -1; 3994 } 3995 3996 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3997 return (CC == CC_C || 3998 CC == CC_X86VectorCall || 3999 CC == CC_IntelOclBicc || 4000 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 4001 } 4002 4003 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4004 return CC_C; 4005 } 4006 4007 // for x32 we need it here explicitly 4008 bool hasInt128Type() const override { return true; } 4009 4010 bool validateGlobalRegisterVariable(StringRef RegName, 4011 unsigned RegSize, 4012 bool &HasSizeMismatch) const override { 4013 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4014 // handle. 4015 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4016 // Check that the register size is 64-bit. 4017 HasSizeMismatch = RegSize != 64; 4018 return true; 4019 } 4020 4021 // Check if the register is a 32-bit register the backend can handle. 4022 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4023 HasSizeMismatch); 4024 } 4025 }; 4026 4027 // x86-64 Windows target 4028 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4029 public: 4030 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 4031 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 4032 WCharType = UnsignedShort; 4033 LongWidth = LongAlign = 32; 4034 DoubleAlign = LongLongAlign = 64; 4035 IntMaxType = SignedLongLong; 4036 Int64Type = SignedLongLong; 4037 SizeType = UnsignedLongLong; 4038 PtrDiffType = SignedLongLong; 4039 IntPtrType = SignedLongLong; 4040 this->UserLabelPrefix = ""; 4041 } 4042 4043 void getTargetDefines(const LangOptions &Opts, 4044 MacroBuilder &Builder) const override { 4045 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4046 Builder.defineMacro("_WIN64"); 4047 } 4048 4049 BuiltinVaListKind getBuiltinVaListKind() const override { 4050 return TargetInfo::CharPtrBuiltinVaList; 4051 } 4052 4053 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4054 switch (CC) { 4055 case CC_X86StdCall: 4056 case CC_X86ThisCall: 4057 case CC_X86FastCall: 4058 return CCCR_Ignore; 4059 case CC_C: 4060 case CC_X86VectorCall: 4061 case CC_IntelOclBicc: 4062 case CC_X86_64SysV: 4063 return CCCR_OK; 4064 default: 4065 return CCCR_Warning; 4066 } 4067 } 4068 }; 4069 4070 // x86-64 Windows Visual Studio target 4071 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4072 public: 4073 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 4074 : WindowsX86_64TargetInfo(Triple) { 4075 LongDoubleWidth = LongDoubleAlign = 64; 4076 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4077 } 4078 void getTargetDefines(const LangOptions &Opts, 4079 MacroBuilder &Builder) const override { 4080 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4081 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4082 Builder.defineMacro("_M_X64", "100"); 4083 Builder.defineMacro("_M_AMD64", "100"); 4084 } 4085 }; 4086 4087 // x86-64 MinGW target 4088 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4089 public: 4090 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 4091 : WindowsX86_64TargetInfo(Triple) { 4092 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4093 // with x86 FP ops. Weird. 4094 LongDoubleWidth = LongDoubleAlign = 128; 4095 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4096 } 4097 4098 void getTargetDefines(const LangOptions &Opts, 4099 MacroBuilder &Builder) const override { 4100 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4101 DefineStd(Builder, "WIN64", Opts); 4102 Builder.defineMacro("__MINGW64__"); 4103 addMinGWDefines(Opts, Builder); 4104 4105 // GCC defines this macro when it is using __gxx_personality_seh0. 4106 if (!Opts.SjLjExceptions) 4107 Builder.defineMacro("__SEH__"); 4108 } 4109 }; 4110 4111 // x86-64 Cygwin target 4112 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4113 public: 4114 CygwinX86_64TargetInfo(const llvm::Triple &Triple) 4115 : X86_64TargetInfo(Triple) { 4116 TLSSupported = false; 4117 WCharType = UnsignedShort; 4118 } 4119 void getTargetDefines(const LangOptions &Opts, 4120 MacroBuilder &Builder) const override { 4121 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4122 Builder.defineMacro("__x86_64__"); 4123 Builder.defineMacro("__CYGWIN__"); 4124 Builder.defineMacro("__CYGWIN64__"); 4125 addCygMingDefines(Opts, Builder); 4126 DefineStd(Builder, "unix", Opts); 4127 if (Opts.CPlusPlus) 4128 Builder.defineMacro("_GNU_SOURCE"); 4129 4130 // GCC defines this macro when it is using __gxx_personality_seh0. 4131 if (!Opts.SjLjExceptions) 4132 Builder.defineMacro("__SEH__"); 4133 } 4134 }; 4135 4136 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4137 public: 4138 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 4139 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 4140 Int64Type = SignedLongLong; 4141 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4142 llvm::Triple T = llvm::Triple(Triple); 4143 if (T.isiOS()) 4144 UseSignedCharForObjCBool = false; 4145 DataLayoutString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 4146 } 4147 4148 bool handleTargetFeatures(std::vector<std::string> &Features, 4149 DiagnosticsEngine &Diags) override { 4150 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4151 Diags)) 4152 return false; 4153 // We now know the features we have: we can decide how to align vectors. 4154 MaxVectorAlign = 4155 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4156 return true; 4157 } 4158 }; 4159 4160 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4161 public: 4162 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 4163 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 4164 IntMaxType = SignedLongLong; 4165 Int64Type = SignedLongLong; 4166 } 4167 }; 4168 4169 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4170 public: 4171 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 4172 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 4173 IntMaxType = SignedLongLong; 4174 Int64Type = SignedLongLong; 4175 } 4176 }; 4177 4178 class ARMTargetInfo : public TargetInfo { 4179 // Possible FPU choices. 4180 enum FPUMode { 4181 VFP2FPU = (1 << 0), 4182 VFP3FPU = (1 << 1), 4183 VFP4FPU = (1 << 2), 4184 NeonFPU = (1 << 3), 4185 FPARMV8 = (1 << 4) 4186 }; 4187 4188 // Possible HWDiv features. 4189 enum HWDivMode { 4190 HWDivThumb = (1 << 0), 4191 HWDivARM = (1 << 1) 4192 }; 4193 4194 static bool FPUModeIsVFP(FPUMode Mode) { 4195 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4196 } 4197 4198 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4199 static const char * const GCCRegNames[]; 4200 4201 std::string ABI, CPU; 4202 4203 StringRef CPUProfile; 4204 StringRef CPUAttr; 4205 4206 enum { 4207 FP_Default, 4208 FP_VFP, 4209 FP_Neon 4210 } FPMath; 4211 4212 unsigned ArchISA; 4213 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4214 unsigned ArchProfile; 4215 unsigned ArchVersion; 4216 4217 unsigned FPU : 5; 4218 4219 unsigned IsAAPCS : 1; 4220 unsigned HWDiv : 2; 4221 4222 // Initialized via features. 4223 unsigned SoftFloat : 1; 4224 unsigned SoftFloatABI : 1; 4225 4226 unsigned CRC : 1; 4227 unsigned Crypto : 1; 4228 unsigned DSP : 1; 4229 unsigned Unaligned : 1; 4230 4231 enum { 4232 LDREX_B = (1 << 0), /// byte (8-bit) 4233 LDREX_H = (1 << 1), /// half (16-bit) 4234 LDREX_W = (1 << 2), /// word (32-bit) 4235 LDREX_D = (1 << 3), /// double (64-bit) 4236 }; 4237 4238 uint32_t LDREX; 4239 4240 // ACLE 6.5.1 Hardware floating point 4241 enum { 4242 HW_FP_HP = (1 << 1), /// half (16-bit) 4243 HW_FP_SP = (1 << 2), /// single (32-bit) 4244 HW_FP_DP = (1 << 3), /// double (64-bit) 4245 }; 4246 uint32_t HW_FP; 4247 4248 static const Builtin::Info BuiltinInfo[]; 4249 4250 void setABIAAPCS() { 4251 IsAAPCS = true; 4252 4253 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4254 const llvm::Triple &T = getTriple(); 4255 4256 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4257 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4258 T.getOS() == llvm::Triple::Bitrig) 4259 SizeType = UnsignedLong; 4260 else 4261 SizeType = UnsignedInt; 4262 4263 switch (T.getOS()) { 4264 case llvm::Triple::NetBSD: 4265 WCharType = SignedInt; 4266 break; 4267 case llvm::Triple::Win32: 4268 WCharType = UnsignedShort; 4269 break; 4270 case llvm::Triple::Linux: 4271 default: 4272 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4273 WCharType = UnsignedInt; 4274 break; 4275 } 4276 4277 UseBitFieldTypeAlignment = true; 4278 4279 ZeroLengthBitfieldBoundary = 0; 4280 4281 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4282 // so set preferred for small types to 32. 4283 if (T.isOSBinFormatMachO()) { 4284 DataLayoutString = 4285 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4286 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4287 } else if (T.isOSWindows()) { 4288 assert(!BigEndian && "Windows on ARM does not support big endian"); 4289 DataLayoutString = "e" 4290 "-m:w" 4291 "-p:32:32" 4292 "-i64:64" 4293 "-v128:64:128" 4294 "-a:0:32" 4295 "-n32" 4296 "-S64"; 4297 } else if (T.isOSNaCl()) { 4298 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4299 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 4300 } else { 4301 DataLayoutString = 4302 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4303 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4304 } 4305 4306 // FIXME: Enumerated types are variable width in straight AAPCS. 4307 } 4308 4309 void setABIAPCS(bool IsAAPCS16) { 4310 const llvm::Triple &T = getTriple(); 4311 4312 IsAAPCS = false; 4313 4314 if (IsAAPCS16) 4315 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4316 else 4317 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4318 4319 // size_t is unsigned int on FreeBSD. 4320 if (T.getOS() == llvm::Triple::FreeBSD) 4321 SizeType = UnsignedInt; 4322 else 4323 SizeType = UnsignedLong; 4324 4325 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4326 WCharType = SignedInt; 4327 4328 // Do not respect the alignment of bit-field types when laying out 4329 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4330 UseBitFieldTypeAlignment = false; 4331 4332 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4333 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4334 /// gcc. 4335 ZeroLengthBitfieldBoundary = 32; 4336 4337 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4338 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4339 DataLayoutString = "e-m:o-p:32:32-i64:64-a:0:32-n32-S128"; 4340 } else if (T.isOSBinFormatMachO()) 4341 DataLayoutString = 4342 BigEndian 4343 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4344 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4345 else 4346 DataLayoutString = 4347 BigEndian 4348 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4349 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4350 4351 // FIXME: Override "preferred align" for double and long long. 4352 } 4353 4354 void setArchInfo() { 4355 StringRef ArchName = getTriple().getArchName(); 4356 4357 ArchISA = llvm::ARM::parseArchISA(ArchName); 4358 CPU = llvm::ARM::getDefaultCPU(ArchName); 4359 unsigned AK = llvm::ARM::parseArch(ArchName); 4360 if (AK != llvm::ARM::AK_INVALID) 4361 ArchKind = AK; 4362 setArchInfo(ArchKind); 4363 } 4364 4365 void setArchInfo(unsigned Kind) { 4366 StringRef SubArch; 4367 4368 // cache TargetParser info 4369 ArchKind = Kind; 4370 SubArch = llvm::ARM::getSubArch(ArchKind); 4371 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4372 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4373 4374 // cache CPU related strings 4375 CPUAttr = getCPUAttr(); 4376 CPUProfile = getCPUProfile(); 4377 } 4378 4379 void setAtomic() { 4380 // when triple does not specify a sub arch, 4381 // then we are not using inline atomics 4382 bool ShouldUseInlineAtomic = 4383 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4384 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4385 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4386 if (ArchProfile == llvm::ARM::PK_M) { 4387 MaxAtomicPromoteWidth = 32; 4388 if (ShouldUseInlineAtomic) 4389 MaxAtomicInlineWidth = 32; 4390 } 4391 else { 4392 MaxAtomicPromoteWidth = 64; 4393 if (ShouldUseInlineAtomic) 4394 MaxAtomicInlineWidth = 64; 4395 } 4396 } 4397 4398 bool isThumb() const { 4399 return (ArchISA == llvm::ARM::IK_THUMB); 4400 } 4401 4402 bool supportsThumb() const { 4403 return CPUAttr.count('T') || ArchVersion >= 6; 4404 } 4405 4406 bool supportsThumb2() const { 4407 return CPUAttr.equals("6T2") || ArchVersion >= 7; 4408 } 4409 4410 StringRef getCPUAttr() const { 4411 // For most sub-arches, the build attribute CPU name is enough. 4412 // For Cortex variants, it's slightly different. 4413 switch(ArchKind) { 4414 default: 4415 return llvm::ARM::getCPUAttr(ArchKind); 4416 case llvm::ARM::AK_ARMV6M: 4417 return "6M"; 4418 case llvm::ARM::AK_ARMV7S: 4419 return "7S"; 4420 case llvm::ARM::AK_ARMV7A: 4421 return "7A"; 4422 case llvm::ARM::AK_ARMV7R: 4423 return "7R"; 4424 case llvm::ARM::AK_ARMV7M: 4425 return "7M"; 4426 case llvm::ARM::AK_ARMV7EM: 4427 return "7EM"; 4428 case llvm::ARM::AK_ARMV8A: 4429 return "8A"; 4430 case llvm::ARM::AK_ARMV8_1A: 4431 return "8_1A"; 4432 } 4433 } 4434 4435 StringRef getCPUProfile() const { 4436 switch(ArchProfile) { 4437 case llvm::ARM::PK_A: 4438 return "A"; 4439 case llvm::ARM::PK_R: 4440 return "R"; 4441 case llvm::ARM::PK_M: 4442 return "M"; 4443 default: 4444 return ""; 4445 } 4446 } 4447 4448 public: 4449 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4450 : TargetInfo(Triple), FPMath(FP_Default), 4451 IsAAPCS(true), LDREX(0), HW_FP(0) { 4452 BigEndian = IsBigEndian; 4453 4454 switch (getTriple().getOS()) { 4455 case llvm::Triple::NetBSD: 4456 PtrDiffType = SignedLong; 4457 break; 4458 default: 4459 PtrDiffType = SignedInt; 4460 break; 4461 } 4462 4463 // Cache arch related info. 4464 setArchInfo(); 4465 4466 // {} in inline assembly are neon specifiers, not assembly variant 4467 // specifiers. 4468 NoAsmVariants = true; 4469 4470 // FIXME: This duplicates code from the driver that sets the -target-abi 4471 // option - this code is used if -target-abi isn't passed and should 4472 // be unified in some way. 4473 if (Triple.isOSBinFormatMachO()) { 4474 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4475 // the frontend matches that. 4476 if (Triple.getEnvironment() == llvm::Triple::EABI || 4477 Triple.getOS() == llvm::Triple::UnknownOS || 4478 StringRef(CPU).startswith("cortex-m")) { 4479 setABI("aapcs"); 4480 } else if (Triple.isWatchOS()) { 4481 setABI("aapcs16"); 4482 } else { 4483 setABI("apcs-gnu"); 4484 } 4485 } else if (Triple.isOSWindows()) { 4486 // FIXME: this is invalid for WindowsCE 4487 setABI("aapcs"); 4488 } else { 4489 // Select the default based on the platform. 4490 switch (Triple.getEnvironment()) { 4491 case llvm::Triple::Android: 4492 case llvm::Triple::GNUEABI: 4493 case llvm::Triple::GNUEABIHF: 4494 setABI("aapcs-linux"); 4495 break; 4496 case llvm::Triple::EABIHF: 4497 case llvm::Triple::EABI: 4498 setABI("aapcs"); 4499 break; 4500 case llvm::Triple::GNU: 4501 setABI("apcs-gnu"); 4502 break; 4503 default: 4504 if (Triple.getOS() == llvm::Triple::NetBSD) 4505 setABI("apcs-gnu"); 4506 else 4507 setABI("aapcs"); 4508 break; 4509 } 4510 } 4511 4512 // ARM targets default to using the ARM C++ ABI. 4513 TheCXXABI.set(TargetCXXABI::GenericARM); 4514 4515 // ARM has atomics up to 8 bytes 4516 setAtomic(); 4517 4518 // Do force alignment of members that follow zero length bitfields. If 4519 // the alignment of the zero-length bitfield is greater than the member 4520 // that follows it, `bar', `bar' will be aligned as the type of the 4521 // zero length bitfield. 4522 UseZeroLengthBitfieldAlignment = true; 4523 } 4524 4525 StringRef getABI() const override { return ABI; } 4526 4527 bool setABI(const std::string &Name) override { 4528 ABI = Name; 4529 4530 // The defaults (above) are for AAPCS, check if we need to change them. 4531 // 4532 // FIXME: We need support for -meabi... we could just mangle it into the 4533 // name. 4534 if (Name == "apcs-gnu" || Name == "aapcs16") { 4535 setABIAPCS(Name == "aapcs16"); 4536 return true; 4537 } 4538 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4539 setABIAAPCS(); 4540 return true; 4541 } 4542 return false; 4543 } 4544 4545 // FIXME: This should be based on Arch attributes, not CPU names. 4546 bool 4547 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4548 StringRef CPU, 4549 const std::vector<std::string> &FeaturesVec) const override { 4550 4551 std::vector<const char*> TargetFeatures; 4552 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4553 4554 // get default FPU features 4555 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4556 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4557 4558 // get default Extension features 4559 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 4560 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4561 4562 for (const char *Feature : TargetFeatures) 4563 if (Feature[0] == '+') 4564 Features[Feature+1] = true; 4565 4566 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4567 } 4568 4569 bool handleTargetFeatures(std::vector<std::string> &Features, 4570 DiagnosticsEngine &Diags) override { 4571 FPU = 0; 4572 CRC = 0; 4573 Crypto = 0; 4574 DSP = 0; 4575 Unaligned = 1; 4576 SoftFloat = SoftFloatABI = false; 4577 HWDiv = 0; 4578 4579 // This does not diagnose illegal cases like having both 4580 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4581 uint32_t HW_FP_remove = 0; 4582 for (const auto &Feature : Features) { 4583 if (Feature == "+soft-float") { 4584 SoftFloat = true; 4585 } else if (Feature == "+soft-float-abi") { 4586 SoftFloatABI = true; 4587 } else if (Feature == "+vfp2") { 4588 FPU |= VFP2FPU; 4589 HW_FP |= HW_FP_SP | HW_FP_DP; 4590 } else if (Feature == "+vfp3") { 4591 FPU |= VFP3FPU; 4592 HW_FP |= HW_FP_SP | HW_FP_DP; 4593 } else if (Feature == "+vfp4") { 4594 FPU |= VFP4FPU; 4595 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4596 } else if (Feature == "+fp-armv8") { 4597 FPU |= FPARMV8; 4598 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4599 } else if (Feature == "+neon") { 4600 FPU |= NeonFPU; 4601 HW_FP |= HW_FP_SP | HW_FP_DP; 4602 } else if (Feature == "+hwdiv") { 4603 HWDiv |= HWDivThumb; 4604 } else if (Feature == "+hwdiv-arm") { 4605 HWDiv |= HWDivARM; 4606 } else if (Feature == "+crc") { 4607 CRC = 1; 4608 } else if (Feature == "+crypto") { 4609 Crypto = 1; 4610 } else if (Feature == "+dsp") { 4611 DSP = 1; 4612 } else if (Feature == "+fp-only-sp") { 4613 HW_FP_remove |= HW_FP_DP; 4614 } else if (Feature == "+strict-align") { 4615 Unaligned = 0; 4616 } else if (Feature == "+fp16") { 4617 HW_FP |= HW_FP_HP; 4618 } 4619 } 4620 HW_FP &= ~HW_FP_remove; 4621 4622 switch (ArchVersion) { 4623 case 6: 4624 if (ArchProfile == llvm::ARM::PK_M) 4625 LDREX = 0; 4626 else if (ArchKind == llvm::ARM::AK_ARMV6K) 4627 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4628 else 4629 LDREX = LDREX_W; 4630 break; 4631 case 7: 4632 if (ArchProfile == llvm::ARM::PK_M) 4633 LDREX = LDREX_W | LDREX_H | LDREX_B ; 4634 else 4635 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4636 break; 4637 case 8: 4638 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4639 } 4640 4641 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4642 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4643 return false; 4644 } 4645 4646 if (FPMath == FP_Neon) 4647 Features.push_back("+neonfp"); 4648 else if (FPMath == FP_VFP) 4649 Features.push_back("-neonfp"); 4650 4651 // Remove front-end specific options which the backend handles differently. 4652 auto Feature = 4653 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4654 if (Feature != Features.end()) 4655 Features.erase(Feature); 4656 4657 return true; 4658 } 4659 4660 bool hasFeature(StringRef Feature) const override { 4661 return llvm::StringSwitch<bool>(Feature) 4662 .Case("arm", true) 4663 .Case("aarch32", true) 4664 .Case("softfloat", SoftFloat) 4665 .Case("thumb", isThumb()) 4666 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4667 .Case("hwdiv", HWDiv & HWDivThumb) 4668 .Case("hwdiv-arm", HWDiv & HWDivARM) 4669 .Default(false); 4670 } 4671 4672 bool setCPU(const std::string &Name) override { 4673 if (Name != "generic") 4674 setArchInfo(llvm::ARM::parseCPUArch(Name)); 4675 4676 if (ArchKind == llvm::ARM::AK_INVALID) 4677 return false; 4678 setAtomic(); 4679 CPU = Name; 4680 return true; 4681 } 4682 4683 bool setFPMath(StringRef Name) override; 4684 4685 void getTargetDefines(const LangOptions &Opts, 4686 MacroBuilder &Builder) const override { 4687 // Target identification. 4688 Builder.defineMacro("__arm"); 4689 Builder.defineMacro("__arm__"); 4690 4691 // Target properties. 4692 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4693 4694 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 4695 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 4696 if (getTriple().isWatchOS()) 4697 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 4698 4699 if (!CPUAttr.empty()) 4700 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 4701 4702 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4703 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4704 Builder.defineMacro("__ARM_ARCH", llvm::utostr(ArchVersion)); 4705 4706 if (ArchVersion >= 8) { 4707 // ACLE 6.5.7 Crypto Extension 4708 if (Crypto) 4709 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 4710 // ACLE 6.5.8 CRC32 Extension 4711 if (CRC) 4712 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 4713 // ACLE 6.5.10 Numeric Maximum and Minimum 4714 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 4715 // ACLE 6.5.9 Directed Rounding 4716 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 4717 } 4718 4719 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4720 // is not defined for the M-profile. 4721 // NOTE that the deffault profile is assumed to be 'A' 4722 if (CPUProfile.empty() || CPUProfile != "M") 4723 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4724 4725 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4726 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4727 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4728 if (supportsThumb2()) 4729 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4730 else if (supportsThumb()) 4731 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4732 4733 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4734 // instruction set such as ARM or Thumb. 4735 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4736 4737 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4738 4739 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4740 if (!CPUProfile.empty()) 4741 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4742 4743 // ACLE 6.4.3 Unaligned access supported in hardware 4744 if (Unaligned) 4745 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 4746 4747 // ACLE 6.4.4 LDREX/STREX 4748 if (LDREX) 4749 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 4750 4751 // ACLE 6.4.5 CLZ 4752 if (ArchVersion == 5 || 4753 (ArchVersion == 6 && CPUProfile != "M") || 4754 ArchVersion > 6) 4755 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 4756 4757 // ACLE 6.5.1 Hardware Floating Point 4758 if (HW_FP) 4759 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4760 4761 // ACLE predefines. 4762 Builder.defineMacro("__ARM_ACLE", "200"); 4763 4764 // FP16 support (we currently only support IEEE format). 4765 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 4766 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 4767 4768 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 4769 if (ArchVersion >= 7 && (CPUProfile != "M" || CPUAttr == "7EM")) 4770 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 4771 4772 // Subtarget options. 4773 4774 // FIXME: It's more complicated than this and we don't really support 4775 // interworking. 4776 // Windows on ARM does not "support" interworking 4777 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 4778 Builder.defineMacro("__THUMB_INTERWORK__"); 4779 4780 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4781 // Embedded targets on Darwin follow AAPCS, but not EABI. 4782 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4783 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4784 Builder.defineMacro("__ARM_EABI__"); 4785 Builder.defineMacro("__ARM_PCS", "1"); 4786 4787 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4788 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4789 } 4790 4791 if (SoftFloat) 4792 Builder.defineMacro("__SOFTFP__"); 4793 4794 if (CPU == "xscale") 4795 Builder.defineMacro("__XSCALE__"); 4796 4797 if (isThumb()) { 4798 Builder.defineMacro("__THUMBEL__"); 4799 Builder.defineMacro("__thumb__"); 4800 if (supportsThumb2()) 4801 Builder.defineMacro("__thumb2__"); 4802 } 4803 4804 // ACLE 6.4.9 32-bit SIMD instructions 4805 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 4806 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 4807 4808 // ACLE 6.4.10 Hardware Integer Divide 4809 if (((HWDiv & HWDivThumb) && isThumb()) || 4810 ((HWDiv & HWDivARM) && !isThumb())) { 4811 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 4812 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4813 } 4814 4815 // Note, this is always on in gcc, even though it doesn't make sense. 4816 Builder.defineMacro("__APCS_32__"); 4817 4818 if (FPUModeIsVFP((FPUMode) FPU)) { 4819 Builder.defineMacro("__VFP_FP__"); 4820 if (FPU & VFP2FPU) 4821 Builder.defineMacro("__ARM_VFPV2__"); 4822 if (FPU & VFP3FPU) 4823 Builder.defineMacro("__ARM_VFPV3__"); 4824 if (FPU & VFP4FPU) 4825 Builder.defineMacro("__ARM_VFPV4__"); 4826 } 4827 4828 // This only gets set when Neon instructions are actually available, unlike 4829 // the VFP define, hence the soft float and arch check. This is subtly 4830 // different from gcc, we follow the intent which was that it should be set 4831 // when Neon instructions are actually available. 4832 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 4833 Builder.defineMacro("__ARM_NEON", "1"); 4834 Builder.defineMacro("__ARM_NEON__"); 4835 // current AArch32 NEON implementations do not support double-precision 4836 // floating-point even when it is present in VFP. 4837 Builder.defineMacro("__ARM_NEON_FP", 4838 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 4839 } 4840 4841 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4842 Opts.ShortWChar ? "2" : "4"); 4843 4844 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4845 Opts.ShortEnums ? "1" : "4"); 4846 4847 if (ArchVersion >= 6 && CPUAttr != "6M") { 4848 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4849 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4850 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4851 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4852 } 4853 4854 // ACLE 6.4.7 DSP instructions 4855 if (DSP) { 4856 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 4857 } 4858 4859 // ACLE 6.4.8 Saturation instructions 4860 bool SAT = false; 4861 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 4862 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 4863 SAT = true; 4864 } 4865 4866 // ACLE 6.4.6 Q (saturation) flag 4867 if (DSP || SAT) 4868 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 4869 4870 if (Opts.UnsafeFPMath) 4871 Builder.defineMacro("__ARM_FP_FAST", "1"); 4872 4873 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 4874 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 4875 } 4876 4877 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4878 return llvm::makeArrayRef(BuiltinInfo, 4879 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 4880 } 4881 bool isCLZForZeroUndef() const override { return false; } 4882 BuiltinVaListKind getBuiltinVaListKind() const override { 4883 return IsAAPCS 4884 ? AAPCSABIBuiltinVaList 4885 : (getTriple().isWatchOS() ? TargetInfo::CharPtrBuiltinVaList 4886 : TargetInfo::VoidPtrBuiltinVaList); 4887 } 4888 ArrayRef<const char *> getGCCRegNames() const override; 4889 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 4890 bool validateAsmConstraint(const char *&Name, 4891 TargetInfo::ConstraintInfo &Info) const override { 4892 switch (*Name) { 4893 default: break; 4894 case 'l': // r0-r7 4895 case 'h': // r8-r15 4896 case 'w': // VFP Floating point register single precision 4897 case 'P': // VFP Floating point register double precision 4898 Info.setAllowsRegister(); 4899 return true; 4900 case 'I': 4901 case 'J': 4902 case 'K': 4903 case 'L': 4904 case 'M': 4905 // FIXME 4906 return true; 4907 case 'Q': // A memory address that is a single base register. 4908 Info.setAllowsMemory(); 4909 return true; 4910 case 'U': // a memory reference... 4911 switch (Name[1]) { 4912 case 'q': // ...ARMV4 ldrsb 4913 case 'v': // ...VFP load/store (reg+constant offset) 4914 case 'y': // ...iWMMXt load/store 4915 case 't': // address valid for load/store opaque types wider 4916 // than 128-bits 4917 case 'n': // valid address for Neon doubleword vector load/store 4918 case 'm': // valid address for Neon element and structure load/store 4919 case 's': // valid address for non-offset loads/stores of quad-word 4920 // values in four ARM registers 4921 Info.setAllowsMemory(); 4922 Name++; 4923 return true; 4924 } 4925 } 4926 return false; 4927 } 4928 std::string convertConstraint(const char *&Constraint) const override { 4929 std::string R; 4930 switch (*Constraint) { 4931 case 'U': // Two-character constraint; add "^" hint for later parsing. 4932 R = std::string("^") + std::string(Constraint, 2); 4933 Constraint++; 4934 break; 4935 case 'p': // 'p' should be translated to 'r' by default. 4936 R = std::string("r"); 4937 break; 4938 default: 4939 return std::string(1, *Constraint); 4940 } 4941 return R; 4942 } 4943 bool 4944 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4945 std::string &SuggestedModifier) const override { 4946 bool isOutput = (Constraint[0] == '='); 4947 bool isInOut = (Constraint[0] == '+'); 4948 4949 // Strip off constraint modifiers. 4950 while (Constraint[0] == '=' || 4951 Constraint[0] == '+' || 4952 Constraint[0] == '&') 4953 Constraint = Constraint.substr(1); 4954 4955 switch (Constraint[0]) { 4956 default: break; 4957 case 'r': { 4958 switch (Modifier) { 4959 default: 4960 return (isInOut || isOutput || Size <= 64); 4961 case 'q': 4962 // A register of size 32 cannot fit a vector type. 4963 return false; 4964 } 4965 } 4966 } 4967 4968 return true; 4969 } 4970 const char *getClobbers() const override { 4971 // FIXME: Is this really right? 4972 return ""; 4973 } 4974 4975 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4976 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4977 } 4978 4979 int getEHDataRegisterNumber(unsigned RegNo) const override { 4980 if (RegNo == 0) return 0; 4981 if (RegNo == 1) return 1; 4982 return -1; 4983 } 4984 4985 bool hasSjLjLowering() const override { 4986 return true; 4987 } 4988 }; 4989 4990 bool ARMTargetInfo::setFPMath(StringRef Name) { 4991 if (Name == "neon") { 4992 FPMath = FP_Neon; 4993 return true; 4994 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4995 Name == "vfp4") { 4996 FPMath = FP_VFP; 4997 return true; 4998 } 4999 return false; 5000 } 5001 5002 const char * const ARMTargetInfo::GCCRegNames[] = { 5003 // Integer registers 5004 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5005 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5006 5007 // Float registers 5008 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5009 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5010 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5011 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5012 5013 // Double registers 5014 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5015 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5016 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5017 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5018 5019 // Quad registers 5020 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5021 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5022 }; 5023 5024 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5025 return llvm::makeArrayRef(GCCRegNames); 5026 } 5027 5028 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5029 { { "a1" }, "r0" }, 5030 { { "a2" }, "r1" }, 5031 { { "a3" }, "r2" }, 5032 { { "a4" }, "r3" }, 5033 { { "v1" }, "r4" }, 5034 { { "v2" }, "r5" }, 5035 { { "v3" }, "r6" }, 5036 { { "v4" }, "r7" }, 5037 { { "v5" }, "r8" }, 5038 { { "v6", "rfp" }, "r9" }, 5039 { { "sl" }, "r10" }, 5040 { { "fp" }, "r11" }, 5041 { { "ip" }, "r12" }, 5042 { { "r13" }, "sp" }, 5043 { { "r14" }, "lr" }, 5044 { { "r15" }, "pc" }, 5045 // The S, D and Q registers overlap, but aren't really aliases; we 5046 // don't want to substitute one of these for a different-sized one. 5047 }; 5048 5049 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5050 return llvm::makeArrayRef(GCCRegAliases); 5051 } 5052 5053 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5054 #define BUILTIN(ID, TYPE, ATTRS) \ 5055 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5056 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5057 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5058 #include "clang/Basic/BuiltinsNEON.def" 5059 5060 #define BUILTIN(ID, TYPE, ATTRS) \ 5061 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5062 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5063 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5064 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5065 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5066 #include "clang/Basic/BuiltinsARM.def" 5067 }; 5068 5069 class ARMleTargetInfo : public ARMTargetInfo { 5070 public: 5071 ARMleTargetInfo(const llvm::Triple &Triple) 5072 : ARMTargetInfo(Triple, false) { } 5073 void getTargetDefines(const LangOptions &Opts, 5074 MacroBuilder &Builder) const override { 5075 Builder.defineMacro("__ARMEL__"); 5076 ARMTargetInfo::getTargetDefines(Opts, Builder); 5077 } 5078 }; 5079 5080 class ARMbeTargetInfo : public ARMTargetInfo { 5081 public: 5082 ARMbeTargetInfo(const llvm::Triple &Triple) 5083 : ARMTargetInfo(Triple, true) { } 5084 void getTargetDefines(const LangOptions &Opts, 5085 MacroBuilder &Builder) const override { 5086 Builder.defineMacro("__ARMEB__"); 5087 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5088 ARMTargetInfo::getTargetDefines(Opts, Builder); 5089 } 5090 }; 5091 5092 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5093 const llvm::Triple Triple; 5094 public: 5095 WindowsARMTargetInfo(const llvm::Triple &Triple) 5096 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 5097 TLSSupported = false; 5098 WCharType = UnsignedShort; 5099 SizeType = UnsignedInt; 5100 UserLabelPrefix = ""; 5101 } 5102 void getVisualStudioDefines(const LangOptions &Opts, 5103 MacroBuilder &Builder) const { 5104 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5105 5106 // FIXME: this is invalid for WindowsCE 5107 Builder.defineMacro("_M_ARM_NT", "1"); 5108 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5109 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5110 5111 assert((Triple.getArch() == llvm::Triple::arm || 5112 Triple.getArch() == llvm::Triple::thumb) && 5113 "invalid architecture for Windows ARM target info"); 5114 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5115 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5116 5117 // TODO map the complete set of values 5118 // 31: VFPv3 40: VFPv4 5119 Builder.defineMacro("_M_ARM_FP", "31"); 5120 } 5121 BuiltinVaListKind getBuiltinVaListKind() const override { 5122 return TargetInfo::CharPtrBuiltinVaList; 5123 } 5124 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5125 switch (CC) { 5126 case CC_X86StdCall: 5127 case CC_X86ThisCall: 5128 case CC_X86FastCall: 5129 case CC_X86VectorCall: 5130 return CCCR_Ignore; 5131 case CC_C: 5132 return CCCR_OK; 5133 default: 5134 return CCCR_Warning; 5135 } 5136 } 5137 }; 5138 5139 // Windows ARM + Itanium C++ ABI Target 5140 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5141 public: 5142 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 5143 : WindowsARMTargetInfo(Triple) { 5144 TheCXXABI.set(TargetCXXABI::GenericARM); 5145 } 5146 5147 void getTargetDefines(const LangOptions &Opts, 5148 MacroBuilder &Builder) const override { 5149 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5150 5151 if (Opts.MSVCCompat) 5152 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5153 } 5154 }; 5155 5156 // Windows ARM, MS (C++) ABI 5157 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5158 public: 5159 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 5160 : WindowsARMTargetInfo(Triple) { 5161 TheCXXABI.set(TargetCXXABI::Microsoft); 5162 } 5163 5164 void getTargetDefines(const LangOptions &Opts, 5165 MacroBuilder &Builder) const override { 5166 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5167 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5168 } 5169 }; 5170 5171 // ARM MinGW target 5172 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5173 public: 5174 MinGWARMTargetInfo(const llvm::Triple &Triple) 5175 : WindowsARMTargetInfo(Triple) { 5176 TheCXXABI.set(TargetCXXABI::GenericARM); 5177 } 5178 5179 void getTargetDefines(const LangOptions &Opts, 5180 MacroBuilder &Builder) const override { 5181 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5182 DefineStd(Builder, "WIN32", Opts); 5183 DefineStd(Builder, "WINNT", Opts); 5184 Builder.defineMacro("_ARM_"); 5185 addMinGWDefines(Opts, Builder); 5186 } 5187 }; 5188 5189 // ARM Cygwin target 5190 class CygwinARMTargetInfo : public ARMleTargetInfo { 5191 public: 5192 CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) { 5193 TLSSupported = false; 5194 WCharType = UnsignedShort; 5195 DoubleAlign = LongLongAlign = 64; 5196 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 5197 } 5198 void getTargetDefines(const LangOptions &Opts, 5199 MacroBuilder &Builder) const override { 5200 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5201 Builder.defineMacro("_ARM_"); 5202 Builder.defineMacro("__CYGWIN__"); 5203 Builder.defineMacro("__CYGWIN32__"); 5204 DefineStd(Builder, "unix", Opts); 5205 if (Opts.CPlusPlus) 5206 Builder.defineMacro("_GNU_SOURCE"); 5207 } 5208 }; 5209 5210 class DarwinARMTargetInfo : 5211 public DarwinTargetInfo<ARMleTargetInfo> { 5212 protected: 5213 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5214 MacroBuilder &Builder) const override { 5215 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5216 } 5217 5218 public: 5219 DarwinARMTargetInfo(const llvm::Triple &Triple) 5220 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 5221 HasAlignMac68kSupport = true; 5222 // iOS always has 64-bit atomic instructions. 5223 // FIXME: This should be based off of the target features in 5224 // ARMleTargetInfo. 5225 MaxAtomicInlineWidth = 64; 5226 5227 if (Triple.isWatchOS()) { 5228 // Darwin on iOS uses a variant of the ARM C++ ABI. 5229 TheCXXABI.set(TargetCXXABI::WatchOS); 5230 5231 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5232 // size_t is long, it's a bit weird for it to be int. 5233 PtrDiffType = SignedLong; 5234 5235 // BOOL should be a real boolean on the new ABI 5236 UseSignedCharForObjCBool = false; 5237 } else 5238 TheCXXABI.set(TargetCXXABI::iOS); 5239 } 5240 }; 5241 5242 class AArch64TargetInfo : public TargetInfo { 5243 virtual void setDataLayoutString() = 0; 5244 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5245 static const char *const GCCRegNames[]; 5246 5247 enum FPUModeEnum { 5248 FPUMode, 5249 NeonMode 5250 }; 5251 5252 unsigned FPU; 5253 unsigned CRC; 5254 unsigned Crypto; 5255 unsigned Unaligned; 5256 unsigned V8_1A; 5257 5258 static const Builtin::Info BuiltinInfo[]; 5259 5260 std::string ABI; 5261 5262 public: 5263 AArch64TargetInfo(const llvm::Triple &Triple) 5264 : TargetInfo(Triple), ABI("aapcs") { 5265 5266 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5267 WCharType = SignedInt; 5268 5269 // NetBSD apparently prefers consistency across ARM targets to consistency 5270 // across 64-bit targets. 5271 Int64Type = SignedLongLong; 5272 IntMaxType = SignedLongLong; 5273 } else { 5274 WCharType = UnsignedInt; 5275 Int64Type = SignedLong; 5276 IntMaxType = SignedLong; 5277 } 5278 5279 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5280 MaxVectorAlign = 128; 5281 MaxAtomicInlineWidth = 128; 5282 MaxAtomicPromoteWidth = 128; 5283 5284 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5285 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5286 5287 // {} in inline assembly are neon specifiers, not assembly variant 5288 // specifiers. 5289 NoAsmVariants = true; 5290 5291 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5292 // contributes to the alignment of the containing aggregate in the same way 5293 // a plain (non bit-field) member of that type would, without exception for 5294 // zero-sized or anonymous bit-fields." 5295 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5296 UseZeroLengthBitfieldAlignment = true; 5297 5298 // AArch64 targets default to using the ARM C++ ABI. 5299 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5300 } 5301 5302 StringRef getABI() const override { return ABI; } 5303 bool setABI(const std::string &Name) override { 5304 if (Name != "aapcs" && Name != "darwinpcs") 5305 return false; 5306 5307 ABI = Name; 5308 return true; 5309 } 5310 5311 bool setCPU(const std::string &Name) override { 5312 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5313 .Case("generic", true) 5314 .Cases("cortex-a53", "cortex-a57", "cortex-a72", "cortex-a35", true) 5315 .Case("cyclone", true) 5316 .Default(false); 5317 return CPUKnown; 5318 } 5319 5320 void getTargetDefines(const LangOptions &Opts, 5321 MacroBuilder &Builder) const override { 5322 // Target identification. 5323 Builder.defineMacro("__aarch64__"); 5324 5325 // Target properties. 5326 Builder.defineMacro("_LP64"); 5327 Builder.defineMacro("__LP64__"); 5328 5329 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5330 Builder.defineMacro("__ARM_ACLE", "200"); 5331 Builder.defineMacro("__ARM_ARCH", "8"); 5332 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5333 5334 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5335 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5336 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5337 5338 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5339 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5340 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5341 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5342 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5343 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5344 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5345 5346 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5347 5348 // 0xe implies support for half, single and double precision operations. 5349 Builder.defineMacro("__ARM_FP", "0xE"); 5350 5351 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5352 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5353 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5354 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5355 5356 if (Opts.UnsafeFPMath) 5357 Builder.defineMacro("__ARM_FP_FAST", "1"); 5358 5359 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5360 5361 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5362 Opts.ShortEnums ? "1" : "4"); 5363 5364 if (FPU == NeonMode) { 5365 Builder.defineMacro("__ARM_NEON", "1"); 5366 // 64-bit NEON supports half, single and double precision operations. 5367 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5368 } 5369 5370 if (CRC) 5371 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5372 5373 if (Crypto) 5374 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5375 5376 if (Unaligned) 5377 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5378 5379 if (V8_1A) 5380 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5381 5382 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5383 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5384 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5385 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5386 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5387 } 5388 5389 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5390 return llvm::makeArrayRef(BuiltinInfo, 5391 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5392 } 5393 5394 bool hasFeature(StringRef Feature) const override { 5395 return Feature == "aarch64" || 5396 Feature == "arm64" || 5397 Feature == "arm" || 5398 (Feature == "neon" && FPU == NeonMode); 5399 } 5400 5401 bool handleTargetFeatures(std::vector<std::string> &Features, 5402 DiagnosticsEngine &Diags) override { 5403 FPU = FPUMode; 5404 CRC = 0; 5405 Crypto = 0; 5406 Unaligned = 1; 5407 V8_1A = 0; 5408 5409 for (const auto &Feature : Features) { 5410 if (Feature == "+neon") 5411 FPU = NeonMode; 5412 if (Feature == "+crc") 5413 CRC = 1; 5414 if (Feature == "+crypto") 5415 Crypto = 1; 5416 if (Feature == "+strict-align") 5417 Unaligned = 0; 5418 if (Feature == "+v8.1a") 5419 V8_1A = 1; 5420 } 5421 5422 setDataLayoutString(); 5423 5424 return true; 5425 } 5426 5427 bool isCLZForZeroUndef() const override { return false; } 5428 5429 BuiltinVaListKind getBuiltinVaListKind() const override { 5430 return TargetInfo::AArch64ABIBuiltinVaList; 5431 } 5432 5433 ArrayRef<const char *> getGCCRegNames() const override; 5434 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5435 5436 bool validateAsmConstraint(const char *&Name, 5437 TargetInfo::ConstraintInfo &Info) const override { 5438 switch (*Name) { 5439 default: 5440 return false; 5441 case 'w': // Floating point and SIMD registers (V0-V31) 5442 Info.setAllowsRegister(); 5443 return true; 5444 case 'I': // Constant that can be used with an ADD instruction 5445 case 'J': // Constant that can be used with a SUB instruction 5446 case 'K': // Constant that can be used with a 32-bit logical instruction 5447 case 'L': // Constant that can be used with a 64-bit logical instruction 5448 case 'M': // Constant that can be used as a 32-bit MOV immediate 5449 case 'N': // Constant that can be used as a 64-bit MOV immediate 5450 case 'Y': // Floating point constant zero 5451 case 'Z': // Integer constant zero 5452 return true; 5453 case 'Q': // A memory reference with base register and no offset 5454 Info.setAllowsMemory(); 5455 return true; 5456 case 'S': // A symbolic address 5457 Info.setAllowsRegister(); 5458 return true; 5459 case 'U': 5460 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5461 // Utf: A memory address suitable for ldp/stp in TF mode. 5462 // Usa: An absolute symbolic address. 5463 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5464 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5465 case 'z': // Zero register, wzr or xzr 5466 Info.setAllowsRegister(); 5467 return true; 5468 case 'x': // Floating point and SIMD registers (V0-V15) 5469 Info.setAllowsRegister(); 5470 return true; 5471 } 5472 return false; 5473 } 5474 5475 bool 5476 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5477 std::string &SuggestedModifier) const override { 5478 // Strip off constraint modifiers. 5479 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5480 Constraint = Constraint.substr(1); 5481 5482 switch (Constraint[0]) { 5483 default: 5484 return true; 5485 case 'z': 5486 case 'r': { 5487 switch (Modifier) { 5488 case 'x': 5489 case 'w': 5490 // For now assume that the person knows what they're 5491 // doing with the modifier. 5492 return true; 5493 default: 5494 // By default an 'r' constraint will be in the 'x' 5495 // registers. 5496 if (Size == 64) 5497 return true; 5498 5499 SuggestedModifier = "w"; 5500 return false; 5501 } 5502 } 5503 } 5504 } 5505 5506 const char *getClobbers() const override { return ""; } 5507 5508 int getEHDataRegisterNumber(unsigned RegNo) const override { 5509 if (RegNo == 0) 5510 return 0; 5511 if (RegNo == 1) 5512 return 1; 5513 return -1; 5514 } 5515 }; 5516 5517 const char *const AArch64TargetInfo::GCCRegNames[] = { 5518 // 32-bit Integer registers 5519 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5520 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5521 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5522 5523 // 64-bit Integer registers 5524 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5525 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5526 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5527 5528 // 32-bit floating point regsisters 5529 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5530 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5531 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5532 5533 // 64-bit floating point regsisters 5534 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5535 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5536 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5537 5538 // Vector registers 5539 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5540 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5541 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5542 }; 5543 5544 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 5545 return llvm::makeArrayRef(GCCRegNames); 5546 } 5547 5548 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5549 { { "w31" }, "wsp" }, 5550 { { "x29" }, "fp" }, 5551 { { "x30" }, "lr" }, 5552 { { "x31" }, "sp" }, 5553 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5554 // don't want to substitute one of these for a different-sized one. 5555 }; 5556 5557 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 5558 return llvm::makeArrayRef(GCCRegAliases); 5559 } 5560 5561 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5562 #define BUILTIN(ID, TYPE, ATTRS) \ 5563 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5564 #include "clang/Basic/BuiltinsNEON.def" 5565 5566 #define BUILTIN(ID, TYPE, ATTRS) \ 5567 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5568 #include "clang/Basic/BuiltinsAArch64.def" 5569 }; 5570 5571 class AArch64leTargetInfo : public AArch64TargetInfo { 5572 void setDataLayoutString() override { 5573 if (getTriple().isOSBinFormatMachO()) 5574 DataLayoutString = "e-m:o-i64:64-i128:128-n32:64-S128"; 5575 else 5576 DataLayoutString = "e-m:e-i64:64-i128:128-n32:64-S128"; 5577 } 5578 5579 public: 5580 AArch64leTargetInfo(const llvm::Triple &Triple) 5581 : AArch64TargetInfo(Triple) { 5582 BigEndian = false; 5583 } 5584 void getTargetDefines(const LangOptions &Opts, 5585 MacroBuilder &Builder) const override { 5586 Builder.defineMacro("__AARCH64EL__"); 5587 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5588 } 5589 }; 5590 5591 class AArch64beTargetInfo : public AArch64TargetInfo { 5592 void setDataLayoutString() override { 5593 assert(!getTriple().isOSBinFormatMachO()); 5594 DataLayoutString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5595 } 5596 5597 public: 5598 AArch64beTargetInfo(const llvm::Triple &Triple) 5599 : AArch64TargetInfo(Triple) { } 5600 void getTargetDefines(const LangOptions &Opts, 5601 MacroBuilder &Builder) const override { 5602 Builder.defineMacro("__AARCH64EB__"); 5603 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5604 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5605 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5606 } 5607 }; 5608 5609 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5610 protected: 5611 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5612 MacroBuilder &Builder) const override { 5613 Builder.defineMacro("__AARCH64_SIMD__"); 5614 Builder.defineMacro("__ARM64_ARCH_8__"); 5615 Builder.defineMacro("__ARM_NEON__"); 5616 Builder.defineMacro("__LITTLE_ENDIAN__"); 5617 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5618 Builder.defineMacro("__arm64", "1"); 5619 Builder.defineMacro("__arm64__", "1"); 5620 5621 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5622 } 5623 5624 public: 5625 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5626 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5627 Int64Type = SignedLongLong; 5628 WCharType = SignedInt; 5629 UseSignedCharForObjCBool = false; 5630 5631 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5632 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5633 5634 TheCXXABI.set(TargetCXXABI::iOS64); 5635 } 5636 5637 BuiltinVaListKind getBuiltinVaListKind() const override { 5638 return TargetInfo::CharPtrBuiltinVaList; 5639 } 5640 }; 5641 5642 // Hexagon abstract base class 5643 class HexagonTargetInfo : public TargetInfo { 5644 static const Builtin::Info BuiltinInfo[]; 5645 static const char * const GCCRegNames[]; 5646 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5647 std::string CPU; 5648 public: 5649 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5650 BigEndian = false; 5651 DataLayoutString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 5652 5653 // {} in inline assembly are packet specifiers, not assembly variant 5654 // specifiers. 5655 NoAsmVariants = true; 5656 } 5657 5658 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5659 return llvm::makeArrayRef(BuiltinInfo, 5660 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 5661 } 5662 5663 bool validateAsmConstraint(const char *&Name, 5664 TargetInfo::ConstraintInfo &Info) const override { 5665 return true; 5666 } 5667 5668 void getTargetDefines(const LangOptions &Opts, 5669 MacroBuilder &Builder) const override; 5670 5671 bool hasFeature(StringRef Feature) const override { 5672 return Feature == "hexagon"; 5673 } 5674 5675 BuiltinVaListKind getBuiltinVaListKind() const override { 5676 return TargetInfo::CharPtrBuiltinVaList; 5677 } 5678 ArrayRef<const char *> getGCCRegNames() const override; 5679 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5680 const char *getClobbers() const override { 5681 return ""; 5682 } 5683 5684 static const char *getHexagonCPUSuffix(StringRef Name) { 5685 return llvm::StringSwitch<const char*>(Name) 5686 .Case("hexagonv4", "4") 5687 .Case("hexagonv5", "5") 5688 .Default(nullptr); 5689 } 5690 5691 bool setCPU(const std::string &Name) override { 5692 if (!getHexagonCPUSuffix(Name)) 5693 return false; 5694 5695 CPU = Name; 5696 return true; 5697 } 5698 }; 5699 5700 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5701 MacroBuilder &Builder) const { 5702 Builder.defineMacro("qdsp6"); 5703 Builder.defineMacro("__qdsp6", "1"); 5704 Builder.defineMacro("__qdsp6__", "1"); 5705 5706 Builder.defineMacro("hexagon"); 5707 Builder.defineMacro("__hexagon", "1"); 5708 Builder.defineMacro("__hexagon__", "1"); 5709 5710 if(CPU == "hexagonv1") { 5711 Builder.defineMacro("__HEXAGON_V1__"); 5712 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 5713 if(Opts.HexagonQdsp6Compat) { 5714 Builder.defineMacro("__QDSP6_V1__"); 5715 Builder.defineMacro("__QDSP6_ARCH__", "1"); 5716 } 5717 } 5718 else if(CPU == "hexagonv2") { 5719 Builder.defineMacro("__HEXAGON_V2__"); 5720 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 5721 if(Opts.HexagonQdsp6Compat) { 5722 Builder.defineMacro("__QDSP6_V2__"); 5723 Builder.defineMacro("__QDSP6_ARCH__", "2"); 5724 } 5725 } 5726 else if(CPU == "hexagonv3") { 5727 Builder.defineMacro("__HEXAGON_V3__"); 5728 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 5729 if(Opts.HexagonQdsp6Compat) { 5730 Builder.defineMacro("__QDSP6_V3__"); 5731 Builder.defineMacro("__QDSP6_ARCH__", "3"); 5732 } 5733 } 5734 else if(CPU == "hexagonv4") { 5735 Builder.defineMacro("__HEXAGON_V4__"); 5736 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5737 if(Opts.HexagonQdsp6Compat) { 5738 Builder.defineMacro("__QDSP6_V4__"); 5739 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5740 } 5741 } 5742 else if(CPU == "hexagonv5") { 5743 Builder.defineMacro("__HEXAGON_V5__"); 5744 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5745 if(Opts.HexagonQdsp6Compat) { 5746 Builder.defineMacro("__QDSP6_V5__"); 5747 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5748 } 5749 } 5750 } 5751 5752 const char * const HexagonTargetInfo::GCCRegNames[] = { 5753 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5754 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5755 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5756 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5757 "p0", "p1", "p2", "p3", 5758 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5759 }; 5760 5761 ArrayRef<const char *> HexagonTargetInfo::getGCCRegNames() const { 5762 return llvm::makeArrayRef(GCCRegNames); 5763 } 5764 5765 5766 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5767 { { "sp" }, "r29" }, 5768 { { "fp" }, "r30" }, 5769 { { "lr" }, "r31" }, 5770 }; 5771 5772 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 5773 return llvm::makeArrayRef(GCCRegAliases); 5774 } 5775 5776 5777 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5778 #define BUILTIN(ID, TYPE, ATTRS) \ 5779 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5780 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5781 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5782 #include "clang/Basic/BuiltinsHexagon.def" 5783 }; 5784 5785 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5786 class SparcTargetInfo : public TargetInfo { 5787 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5788 static const char * const GCCRegNames[]; 5789 bool SoftFloat; 5790 public: 5791 SparcTargetInfo(const llvm::Triple &Triple) 5792 : TargetInfo(Triple), SoftFloat(false) {} 5793 5794 bool handleTargetFeatures(std::vector<std::string> &Features, 5795 DiagnosticsEngine &Diags) override { 5796 // The backend doesn't actually handle soft float yet, but in case someone 5797 // is using the support for the front end continue to support it. 5798 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 5799 if (Feature != Features.end()) { 5800 SoftFloat = true; 5801 Features.erase(Feature); 5802 } 5803 return true; 5804 } 5805 void getTargetDefines(const LangOptions &Opts, 5806 MacroBuilder &Builder) const override { 5807 DefineStd(Builder, "sparc", Opts); 5808 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5809 5810 if (SoftFloat) 5811 Builder.defineMacro("SOFT_FLOAT", "1"); 5812 } 5813 5814 bool hasFeature(StringRef Feature) const override { 5815 return llvm::StringSwitch<bool>(Feature) 5816 .Case("softfloat", SoftFloat) 5817 .Case("sparc", true) 5818 .Default(false); 5819 } 5820 5821 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5822 // FIXME: Implement! 5823 return None; 5824 } 5825 BuiltinVaListKind getBuiltinVaListKind() const override { 5826 return TargetInfo::VoidPtrBuiltinVaList; 5827 } 5828 ArrayRef<const char *> getGCCRegNames() const override; 5829 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5830 bool validateAsmConstraint(const char *&Name, 5831 TargetInfo::ConstraintInfo &info) const override { 5832 // FIXME: Implement! 5833 switch (*Name) { 5834 case 'I': // Signed 13-bit constant 5835 case 'J': // Zero 5836 case 'K': // 32-bit constant with the low 12 bits clear 5837 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5838 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5839 case 'N': // Same as 'K' but zext (required for SIMode) 5840 case 'O': // The constant 4096 5841 return true; 5842 } 5843 return false; 5844 } 5845 const char *getClobbers() const override { 5846 // FIXME: Implement! 5847 return ""; 5848 } 5849 5850 // No Sparc V7 for now, the backend doesn't support it anyway. 5851 enum CPUKind { 5852 CK_GENERIC, 5853 CK_V8, 5854 CK_SUPERSPARC, 5855 CK_SPARCLITE, 5856 CK_F934, 5857 CK_HYPERSPARC, 5858 CK_SPARCLITE86X, 5859 CK_SPARCLET, 5860 CK_TSC701, 5861 CK_V9, 5862 CK_ULTRASPARC, 5863 CK_ULTRASPARC3, 5864 CK_NIAGARA, 5865 CK_NIAGARA2, 5866 CK_NIAGARA3, 5867 CK_NIAGARA4 5868 } CPU = CK_GENERIC; 5869 5870 enum CPUGeneration { 5871 CG_V8, 5872 CG_V9, 5873 }; 5874 5875 CPUGeneration getCPUGeneration(CPUKind Kind) const { 5876 switch (Kind) { 5877 case CK_GENERIC: 5878 case CK_V8: 5879 case CK_SUPERSPARC: 5880 case CK_SPARCLITE: 5881 case CK_F934: 5882 case CK_HYPERSPARC: 5883 case CK_SPARCLITE86X: 5884 case CK_SPARCLET: 5885 case CK_TSC701: 5886 return CG_V8; 5887 case CK_V9: 5888 case CK_ULTRASPARC: 5889 case CK_ULTRASPARC3: 5890 case CK_NIAGARA: 5891 case CK_NIAGARA2: 5892 case CK_NIAGARA3: 5893 case CK_NIAGARA4: 5894 return CG_V9; 5895 } 5896 llvm_unreachable("Unexpected CPU kind"); 5897 } 5898 5899 CPUKind getCPUKind(StringRef Name) const { 5900 return llvm::StringSwitch<CPUKind>(Name) 5901 .Case("v8", CK_V8) 5902 .Case("supersparc", CK_SUPERSPARC) 5903 .Case("sparclite", CK_SPARCLITE) 5904 .Case("f934", CK_F934) 5905 .Case("hypersparc", CK_HYPERSPARC) 5906 .Case("sparclite86x", CK_SPARCLITE86X) 5907 .Case("sparclet", CK_SPARCLET) 5908 .Case("tsc701", CK_TSC701) 5909 .Case("v9", CK_V9) 5910 .Case("ultrasparc", CK_ULTRASPARC) 5911 .Case("ultrasparc3", CK_ULTRASPARC3) 5912 .Case("niagara", CK_NIAGARA) 5913 .Case("niagara2", CK_NIAGARA2) 5914 .Case("niagara3", CK_NIAGARA3) 5915 .Case("niagara4", CK_NIAGARA4) 5916 .Default(CK_GENERIC); 5917 } 5918 5919 bool setCPU(const std::string &Name) override { 5920 CPU = getCPUKind(Name); 5921 return CPU != CK_GENERIC; 5922 } 5923 }; 5924 5925 const char * const SparcTargetInfo::GCCRegNames[] = { 5926 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5927 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5928 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5929 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5930 }; 5931 5932 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 5933 return llvm::makeArrayRef(GCCRegNames); 5934 } 5935 5936 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5937 { { "g0" }, "r0" }, 5938 { { "g1" }, "r1" }, 5939 { { "g2" }, "r2" }, 5940 { { "g3" }, "r3" }, 5941 { { "g4" }, "r4" }, 5942 { { "g5" }, "r5" }, 5943 { { "g6" }, "r6" }, 5944 { { "g7" }, "r7" }, 5945 { { "o0" }, "r8" }, 5946 { { "o1" }, "r9" }, 5947 { { "o2" }, "r10" }, 5948 { { "o3" }, "r11" }, 5949 { { "o4" }, "r12" }, 5950 { { "o5" }, "r13" }, 5951 { { "o6", "sp" }, "r14" }, 5952 { { "o7" }, "r15" }, 5953 { { "l0" }, "r16" }, 5954 { { "l1" }, "r17" }, 5955 { { "l2" }, "r18" }, 5956 { { "l3" }, "r19" }, 5957 { { "l4" }, "r20" }, 5958 { { "l5" }, "r21" }, 5959 { { "l6" }, "r22" }, 5960 { { "l7" }, "r23" }, 5961 { { "i0" }, "r24" }, 5962 { { "i1" }, "r25" }, 5963 { { "i2" }, "r26" }, 5964 { { "i3" }, "r27" }, 5965 { { "i4" }, "r28" }, 5966 { { "i5" }, "r29" }, 5967 { { "i6", "fp" }, "r30" }, 5968 { { "i7" }, "r31" }, 5969 }; 5970 5971 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 5972 return llvm::makeArrayRef(GCCRegAliases); 5973 } 5974 5975 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5976 class SparcV8TargetInfo : public SparcTargetInfo { 5977 public: 5978 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5979 DataLayoutString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5980 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 5981 switch (getTriple().getOS()) { 5982 default: 5983 SizeType = UnsignedInt; 5984 IntPtrType = SignedInt; 5985 PtrDiffType = SignedInt; 5986 break; 5987 case llvm::Triple::NetBSD: 5988 case llvm::Triple::OpenBSD: 5989 SizeType = UnsignedLong; 5990 IntPtrType = SignedLong; 5991 PtrDiffType = SignedLong; 5992 break; 5993 } 5994 } 5995 5996 void getTargetDefines(const LangOptions &Opts, 5997 MacroBuilder &Builder) const override { 5998 SparcTargetInfo::getTargetDefines(Opts, Builder); 5999 switch (getCPUGeneration(CPU)) { 6000 case CG_V8: 6001 Builder.defineMacro("__sparcv8"); 6002 if (getTriple().getOS() != llvm::Triple::Solaris) 6003 Builder.defineMacro("__sparcv8__"); 6004 break; 6005 case CG_V9: 6006 Builder.defineMacro("__sparcv9"); 6007 if (getTriple().getOS() != llvm::Triple::Solaris) { 6008 Builder.defineMacro("__sparcv9__"); 6009 Builder.defineMacro("__sparc_v9__"); 6010 } 6011 break; 6012 } 6013 } 6014 }; 6015 6016 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6017 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6018 public: 6019 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 6020 DataLayoutString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64"; 6021 BigEndian = false; 6022 } 6023 }; 6024 6025 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6026 class SparcV9TargetInfo : public SparcTargetInfo { 6027 public: 6028 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 6029 // FIXME: Support Sparc quad-precision long double? 6030 DataLayoutString = "E-m:e-i64:64-n32:64-S128"; 6031 // This is an LP64 platform. 6032 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6033 6034 // OpenBSD uses long long for int64_t and intmax_t. 6035 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6036 IntMaxType = SignedLongLong; 6037 else 6038 IntMaxType = SignedLong; 6039 Int64Type = IntMaxType; 6040 6041 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6042 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6043 LongDoubleWidth = 128; 6044 LongDoubleAlign = 128; 6045 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6046 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6047 } 6048 6049 void getTargetDefines(const LangOptions &Opts, 6050 MacroBuilder &Builder) const override { 6051 SparcTargetInfo::getTargetDefines(Opts, Builder); 6052 Builder.defineMacro("__sparcv9"); 6053 Builder.defineMacro("__arch64__"); 6054 // Solaris doesn't need these variants, but the BSDs do. 6055 if (getTriple().getOS() != llvm::Triple::Solaris) { 6056 Builder.defineMacro("__sparc64__"); 6057 Builder.defineMacro("__sparc_v9__"); 6058 Builder.defineMacro("__sparcv9__"); 6059 } 6060 } 6061 6062 bool setCPU(const std::string &Name) override { 6063 if (!SparcTargetInfo::setCPU(Name)) 6064 return false; 6065 return getCPUGeneration(CPU) == CG_V9; 6066 } 6067 }; 6068 6069 class SystemZTargetInfo : public TargetInfo { 6070 static const Builtin::Info BuiltinInfo[]; 6071 static const char *const GCCRegNames[]; 6072 std::string CPU; 6073 bool HasTransactionalExecution; 6074 bool HasVector; 6075 6076 public: 6077 SystemZTargetInfo(const llvm::Triple &Triple) 6078 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6079 HasVector(false) { 6080 IntMaxType = SignedLong; 6081 Int64Type = SignedLong; 6082 TLSSupported = true; 6083 IntWidth = IntAlign = 32; 6084 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6085 PointerWidth = PointerAlign = 64; 6086 LongDoubleWidth = 128; 6087 LongDoubleAlign = 64; 6088 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6089 DefaultAlignForAttributeAligned = 64; 6090 MinGlobalAlign = 16; 6091 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 6092 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6093 } 6094 void getTargetDefines(const LangOptions &Opts, 6095 MacroBuilder &Builder) const override { 6096 Builder.defineMacro("__s390__"); 6097 Builder.defineMacro("__s390x__"); 6098 Builder.defineMacro("__zarch__"); 6099 Builder.defineMacro("__LONG_DOUBLE_128__"); 6100 if (HasTransactionalExecution) 6101 Builder.defineMacro("__HTM__"); 6102 if (Opts.ZVector) 6103 Builder.defineMacro("__VEC__", "10301"); 6104 } 6105 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6106 return llvm::makeArrayRef(BuiltinInfo, 6107 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6108 } 6109 6110 ArrayRef<const char *> getGCCRegNames() const override; 6111 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6112 // No aliases. 6113 return None; 6114 } 6115 bool validateAsmConstraint(const char *&Name, 6116 TargetInfo::ConstraintInfo &info) const override; 6117 const char *getClobbers() const override { 6118 // FIXME: Is this really right? 6119 return ""; 6120 } 6121 BuiltinVaListKind getBuiltinVaListKind() const override { 6122 return TargetInfo::SystemZBuiltinVaList; 6123 } 6124 bool setCPU(const std::string &Name) override { 6125 CPU = Name; 6126 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6127 .Case("z10", true) 6128 .Case("z196", true) 6129 .Case("zEC12", true) 6130 .Case("z13", true) 6131 .Default(false); 6132 6133 return CPUKnown; 6134 } 6135 bool 6136 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6137 StringRef CPU, 6138 const std::vector<std::string> &FeaturesVec) const override { 6139 if (CPU == "zEC12") 6140 Features["transactional-execution"] = true; 6141 if (CPU == "z13") { 6142 Features["transactional-execution"] = true; 6143 Features["vector"] = true; 6144 } 6145 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6146 } 6147 6148 bool handleTargetFeatures(std::vector<std::string> &Features, 6149 DiagnosticsEngine &Diags) override { 6150 HasTransactionalExecution = false; 6151 for (const auto &Feature : Features) { 6152 if (Feature == "+transactional-execution") 6153 HasTransactionalExecution = true; 6154 else if (Feature == "+vector") 6155 HasVector = true; 6156 } 6157 // If we use the vector ABI, vector types are 64-bit aligned. 6158 if (HasVector) { 6159 MaxVectorAlign = 64; 6160 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6161 "-v128:64-a:8:16-n32:64"; 6162 } 6163 return true; 6164 } 6165 6166 bool hasFeature(StringRef Feature) const override { 6167 return llvm::StringSwitch<bool>(Feature) 6168 .Case("systemz", true) 6169 .Case("htm", HasTransactionalExecution) 6170 .Case("vx", HasVector) 6171 .Default(false); 6172 } 6173 6174 StringRef getABI() const override { 6175 if (HasVector) 6176 return "vector"; 6177 return ""; 6178 } 6179 6180 bool useFloat128ManglingForLongDouble() const override { 6181 return true; 6182 } 6183 }; 6184 6185 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6186 #define BUILTIN(ID, TYPE, ATTRS) \ 6187 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6188 #include "clang/Basic/BuiltinsSystemZ.def" 6189 }; 6190 6191 const char *const SystemZTargetInfo::GCCRegNames[] = { 6192 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6193 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6194 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6195 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6196 }; 6197 6198 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6199 return llvm::makeArrayRef(GCCRegNames); 6200 } 6201 6202 bool SystemZTargetInfo:: 6203 validateAsmConstraint(const char *&Name, 6204 TargetInfo::ConstraintInfo &Info) const { 6205 switch (*Name) { 6206 default: 6207 return false; 6208 6209 case 'a': // Address register 6210 case 'd': // Data register (equivalent to 'r') 6211 case 'f': // Floating-point register 6212 Info.setAllowsRegister(); 6213 return true; 6214 6215 case 'I': // Unsigned 8-bit constant 6216 case 'J': // Unsigned 12-bit constant 6217 case 'K': // Signed 16-bit constant 6218 case 'L': // Signed 20-bit displacement (on all targets we support) 6219 case 'M': // 0x7fffffff 6220 return true; 6221 6222 case 'Q': // Memory with base and unsigned 12-bit displacement 6223 case 'R': // Likewise, plus an index 6224 case 'S': // Memory with base and signed 20-bit displacement 6225 case 'T': // Likewise, plus an index 6226 Info.setAllowsMemory(); 6227 return true; 6228 } 6229 } 6230 6231 class MSP430TargetInfo : public TargetInfo { 6232 static const char *const GCCRegNames[]; 6233 6234 public: 6235 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6236 BigEndian = false; 6237 TLSSupported = false; 6238 IntWidth = 16; 6239 IntAlign = 16; 6240 LongWidth = 32; 6241 LongLongWidth = 64; 6242 LongAlign = LongLongAlign = 16; 6243 PointerWidth = 16; 6244 PointerAlign = 16; 6245 SuitableAlign = 16; 6246 SizeType = UnsignedInt; 6247 IntMaxType = SignedLongLong; 6248 IntPtrType = SignedInt; 6249 PtrDiffType = SignedInt; 6250 SigAtomicType = SignedLong; 6251 DataLayoutString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 6252 } 6253 void getTargetDefines(const LangOptions &Opts, 6254 MacroBuilder &Builder) const override { 6255 Builder.defineMacro("MSP430"); 6256 Builder.defineMacro("__MSP430__"); 6257 // FIXME: defines for different 'flavours' of MCU 6258 } 6259 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6260 // FIXME: Implement. 6261 return None; 6262 } 6263 bool hasFeature(StringRef Feature) const override { 6264 return Feature == "msp430"; 6265 } 6266 ArrayRef<const char *> getGCCRegNames() const override; 6267 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6268 // No aliases. 6269 return None; 6270 } 6271 bool validateAsmConstraint(const char *&Name, 6272 TargetInfo::ConstraintInfo &info) const override { 6273 // FIXME: implement 6274 switch (*Name) { 6275 case 'K': // the constant 1 6276 case 'L': // constant -1^20 .. 1^19 6277 case 'M': // constant 1-4: 6278 return true; 6279 } 6280 // No target constraints for now. 6281 return false; 6282 } 6283 const char *getClobbers() const override { 6284 // FIXME: Is this really right? 6285 return ""; 6286 } 6287 BuiltinVaListKind getBuiltinVaListKind() const override { 6288 // FIXME: implement 6289 return TargetInfo::CharPtrBuiltinVaList; 6290 } 6291 }; 6292 6293 const char *const MSP430TargetInfo::GCCRegNames[] = { 6294 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6295 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6296 6297 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 6298 return llvm::makeArrayRef(GCCRegNames); 6299 } 6300 6301 // LLVM and Clang cannot be used directly to output native binaries for 6302 // target, but is used to compile C code to llvm bitcode with correct 6303 // type and alignment information. 6304 // 6305 // TCE uses the llvm bitcode as input and uses it for generating customized 6306 // target processor and program binary. TCE co-design environment is 6307 // publicly available in http://tce.cs.tut.fi 6308 6309 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6310 3, // opencl_global 6311 4, // opencl_local 6312 5, // opencl_constant 6313 // FIXME: generic has to be added to the target 6314 0, // opencl_generic 6315 0, // cuda_device 6316 0, // cuda_constant 6317 0 // cuda_shared 6318 }; 6319 6320 class TCETargetInfo : public TargetInfo { 6321 public: 6322 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6323 TLSSupported = false; 6324 IntWidth = 32; 6325 LongWidth = LongLongWidth = 32; 6326 PointerWidth = 32; 6327 IntAlign = 32; 6328 LongAlign = LongLongAlign = 32; 6329 PointerAlign = 32; 6330 SuitableAlign = 32; 6331 SizeType = UnsignedInt; 6332 IntMaxType = SignedLong; 6333 IntPtrType = SignedInt; 6334 PtrDiffType = SignedInt; 6335 FloatWidth = 32; 6336 FloatAlign = 32; 6337 DoubleWidth = 32; 6338 DoubleAlign = 32; 6339 LongDoubleWidth = 32; 6340 LongDoubleAlign = 32; 6341 FloatFormat = &llvm::APFloat::IEEEsingle; 6342 DoubleFormat = &llvm::APFloat::IEEEsingle; 6343 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6344 DataLayoutString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 6345 "-f64:32-v64:32-v128:32-a:0:32-n32"; 6346 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6347 UseAddrSpaceMapMangling = true; 6348 } 6349 6350 void getTargetDefines(const LangOptions &Opts, 6351 MacroBuilder &Builder) const override { 6352 DefineStd(Builder, "tce", Opts); 6353 Builder.defineMacro("__TCE__"); 6354 Builder.defineMacro("__TCE_V1__"); 6355 } 6356 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 6357 6358 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6359 const char *getClobbers() const override { return ""; } 6360 BuiltinVaListKind getBuiltinVaListKind() const override { 6361 return TargetInfo::VoidPtrBuiltinVaList; 6362 } 6363 ArrayRef<const char *> getGCCRegNames() const override { return None; } 6364 bool validateAsmConstraint(const char *&Name, 6365 TargetInfo::ConstraintInfo &info) const override { 6366 return true; 6367 } 6368 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6369 return None; 6370 } 6371 }; 6372 6373 class BPFTargetInfo : public TargetInfo { 6374 public: 6375 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6376 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6377 SizeType = UnsignedLong; 6378 PtrDiffType = SignedLong; 6379 IntPtrType = SignedLong; 6380 IntMaxType = SignedLong; 6381 Int64Type = SignedLong; 6382 RegParmMax = 5; 6383 if (Triple.getArch() == llvm::Triple::bpfeb) { 6384 BigEndian = true; 6385 DataLayoutString = "E-m:e-p:64:64-i64:64-n32:64-S128"; 6386 } else { 6387 BigEndian = false; 6388 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 6389 } 6390 MaxAtomicPromoteWidth = 64; 6391 MaxAtomicInlineWidth = 64; 6392 TLSSupported = false; 6393 } 6394 void getTargetDefines(const LangOptions &Opts, 6395 MacroBuilder &Builder) const override { 6396 DefineStd(Builder, "bpf", Opts); 6397 Builder.defineMacro("__BPF__"); 6398 } 6399 bool hasFeature(StringRef Feature) const override { 6400 return Feature == "bpf"; 6401 } 6402 6403 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6404 const char *getClobbers() const override { 6405 return ""; 6406 } 6407 BuiltinVaListKind getBuiltinVaListKind() const override { 6408 return TargetInfo::VoidPtrBuiltinVaList; 6409 } 6410 ArrayRef<const char *> getGCCRegNames() const override { 6411 return None; 6412 } 6413 bool validateAsmConstraint(const char *&Name, 6414 TargetInfo::ConstraintInfo &info) const override { 6415 return true; 6416 } 6417 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6418 return None; 6419 } 6420 }; 6421 6422 class MipsTargetInfoBase : public TargetInfo { 6423 virtual void setDataLayoutString() = 0; 6424 6425 static const Builtin::Info BuiltinInfo[]; 6426 std::string CPU; 6427 bool IsMips16; 6428 bool IsMicromips; 6429 bool IsNan2008; 6430 bool IsSingleFloat; 6431 enum MipsFloatABI { 6432 HardFloat, SoftFloat 6433 } FloatABI; 6434 enum DspRevEnum { 6435 NoDSP, DSP1, DSP2 6436 } DspRev; 6437 bool HasMSA; 6438 6439 protected: 6440 bool HasFP64; 6441 std::string ABI; 6442 6443 public: 6444 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 6445 const std::string &CPUStr) 6446 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6447 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6448 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6449 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6450 } 6451 6452 bool isNaN2008Default() const { 6453 return CPU == "mips32r6" || CPU == "mips64r6"; 6454 } 6455 6456 bool isFP64Default() const { 6457 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6458 } 6459 6460 bool isNan2008() const override { 6461 return IsNan2008; 6462 } 6463 6464 StringRef getABI() const override { return ABI; } 6465 bool setCPU(const std::string &Name) override { 6466 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6467 getTriple().getArch() == llvm::Triple::mipsel; 6468 CPU = Name; 6469 return llvm::StringSwitch<bool>(Name) 6470 .Case("mips1", IsMips32) 6471 .Case("mips2", IsMips32) 6472 .Case("mips3", true) 6473 .Case("mips4", true) 6474 .Case("mips5", true) 6475 .Case("mips32", IsMips32) 6476 .Case("mips32r2", IsMips32) 6477 .Case("mips32r3", IsMips32) 6478 .Case("mips32r5", IsMips32) 6479 .Case("mips32r6", IsMips32) 6480 .Case("mips64", true) 6481 .Case("mips64r2", true) 6482 .Case("mips64r3", true) 6483 .Case("mips64r5", true) 6484 .Case("mips64r6", true) 6485 .Case("octeon", true) 6486 .Case("p5600", true) 6487 .Default(false); 6488 } 6489 const std::string& getCPU() const { return CPU; } 6490 bool 6491 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6492 StringRef CPU, 6493 const std::vector<std::string> &FeaturesVec) const override { 6494 if (CPU == "octeon") 6495 Features["mips64r2"] = Features["cnmips"] = true; 6496 else 6497 Features[CPU] = true; 6498 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6499 } 6500 6501 void getTargetDefines(const LangOptions &Opts, 6502 MacroBuilder &Builder) const override { 6503 Builder.defineMacro("__mips__"); 6504 Builder.defineMacro("_mips"); 6505 if (Opts.GNUMode) 6506 Builder.defineMacro("mips"); 6507 6508 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6509 6510 switch (FloatABI) { 6511 case HardFloat: 6512 Builder.defineMacro("__mips_hard_float", Twine(1)); 6513 break; 6514 case SoftFloat: 6515 Builder.defineMacro("__mips_soft_float", Twine(1)); 6516 break; 6517 } 6518 6519 if (IsSingleFloat) 6520 Builder.defineMacro("__mips_single_float", Twine(1)); 6521 6522 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6523 Builder.defineMacro("_MIPS_FPSET", 6524 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6525 6526 if (IsMips16) 6527 Builder.defineMacro("__mips16", Twine(1)); 6528 6529 if (IsMicromips) 6530 Builder.defineMacro("__mips_micromips", Twine(1)); 6531 6532 if (IsNan2008) 6533 Builder.defineMacro("__mips_nan2008", Twine(1)); 6534 6535 switch (DspRev) { 6536 default: 6537 break; 6538 case DSP1: 6539 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6540 Builder.defineMacro("__mips_dsp", Twine(1)); 6541 break; 6542 case DSP2: 6543 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6544 Builder.defineMacro("__mips_dspr2", Twine(1)); 6545 Builder.defineMacro("__mips_dsp", Twine(1)); 6546 break; 6547 } 6548 6549 if (HasMSA) 6550 Builder.defineMacro("__mips_msa", Twine(1)); 6551 6552 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6553 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6554 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6555 6556 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6557 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6558 } 6559 6560 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6561 return llvm::makeArrayRef(BuiltinInfo, 6562 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 6563 } 6564 bool hasFeature(StringRef Feature) const override { 6565 return llvm::StringSwitch<bool>(Feature) 6566 .Case("mips", true) 6567 .Case("fp64", HasFP64) 6568 .Default(false); 6569 } 6570 BuiltinVaListKind getBuiltinVaListKind() const override { 6571 return TargetInfo::VoidPtrBuiltinVaList; 6572 } 6573 ArrayRef<const char *> getGCCRegNames() const override { 6574 static const char *const GCCRegNames[] = { 6575 // CPU register names 6576 // Must match second column of GCCRegAliases 6577 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6578 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6579 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6580 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6581 // Floating point register names 6582 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6583 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6584 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6585 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6586 // Hi/lo and condition register names 6587 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6588 "$fcc5","$fcc6","$fcc7", 6589 // MSA register names 6590 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6591 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6592 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6593 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6594 // MSA control register names 6595 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6596 "$msarequest", "$msamap", "$msaunmap" 6597 }; 6598 return llvm::makeArrayRef(GCCRegNames); 6599 } 6600 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override = 0; 6601 bool validateAsmConstraint(const char *&Name, 6602 TargetInfo::ConstraintInfo &Info) const override { 6603 switch (*Name) { 6604 default: 6605 return false; 6606 case 'r': // CPU registers. 6607 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6608 case 'y': // Equivalent to "r", backward compatibility only. 6609 case 'f': // floating-point registers. 6610 case 'c': // $25 for indirect jumps 6611 case 'l': // lo register 6612 case 'x': // hilo register pair 6613 Info.setAllowsRegister(); 6614 return true; 6615 case 'I': // Signed 16-bit constant 6616 case 'J': // Integer 0 6617 case 'K': // Unsigned 16-bit constant 6618 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6619 case 'M': // Constants not loadable via lui, addiu, or ori 6620 case 'N': // Constant -1 to -65535 6621 case 'O': // A signed 15-bit constant 6622 case 'P': // A constant between 1 go 65535 6623 return true; 6624 case 'R': // An address that can be used in a non-macro load or store 6625 Info.setAllowsMemory(); 6626 return true; 6627 case 'Z': 6628 if (Name[1] == 'C') { // An address usable by ll, and sc. 6629 Info.setAllowsMemory(); 6630 Name++; // Skip over 'Z'. 6631 return true; 6632 } 6633 return false; 6634 } 6635 } 6636 6637 std::string convertConstraint(const char *&Constraint) const override { 6638 std::string R; 6639 switch (*Constraint) { 6640 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6641 if (Constraint[1] == 'C') { 6642 R = std::string("^") + std::string(Constraint, 2); 6643 Constraint++; 6644 return R; 6645 } 6646 break; 6647 } 6648 return TargetInfo::convertConstraint(Constraint); 6649 } 6650 6651 const char *getClobbers() const override { 6652 // In GCC, $1 is not widely used in generated code (it's used only in a few 6653 // specific situations), so there is no real need for users to add it to 6654 // the clobbers list if they want to use it in their inline assembly code. 6655 // 6656 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6657 // code generation, so using it in inline assembly without adding it to the 6658 // clobbers list can cause conflicts between the inline assembly code and 6659 // the surrounding generated code. 6660 // 6661 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6662 // operands, which will conflict with the ".set at" assembler option (which 6663 // we use only for inline assembly, in order to maintain compatibility with 6664 // GCC) and will also conflict with the user's usage of $1. 6665 // 6666 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6667 // register for generated code is to automatically clobber $1 for all inline 6668 // assembly code. 6669 // 6670 // FIXME: We should automatically clobber $1 only for inline assembly code 6671 // which actually uses it. This would allow LLVM to use $1 for inline 6672 // assembly operands if the user's assembly code doesn't use it. 6673 return "~{$1}"; 6674 } 6675 6676 bool handleTargetFeatures(std::vector<std::string> &Features, 6677 DiagnosticsEngine &Diags) override { 6678 IsMips16 = false; 6679 IsMicromips = false; 6680 IsNan2008 = isNaN2008Default(); 6681 IsSingleFloat = false; 6682 FloatABI = HardFloat; 6683 DspRev = NoDSP; 6684 HasFP64 = isFP64Default(); 6685 6686 for (const auto &Feature : Features) { 6687 if (Feature == "+single-float") 6688 IsSingleFloat = true; 6689 else if (Feature == "+soft-float") 6690 FloatABI = SoftFloat; 6691 else if (Feature == "+mips16") 6692 IsMips16 = true; 6693 else if (Feature == "+micromips") 6694 IsMicromips = true; 6695 else if (Feature == "+dsp") 6696 DspRev = std::max(DspRev, DSP1); 6697 else if (Feature == "+dspr2") 6698 DspRev = std::max(DspRev, DSP2); 6699 else if (Feature == "+msa") 6700 HasMSA = true; 6701 else if (Feature == "+fp64") 6702 HasFP64 = true; 6703 else if (Feature == "-fp64") 6704 HasFP64 = false; 6705 else if (Feature == "+nan2008") 6706 IsNan2008 = true; 6707 else if (Feature == "-nan2008") 6708 IsNan2008 = false; 6709 } 6710 6711 setDataLayoutString(); 6712 6713 return true; 6714 } 6715 6716 int getEHDataRegisterNumber(unsigned RegNo) const override { 6717 if (RegNo == 0) return 4; 6718 if (RegNo == 1) return 5; 6719 return -1; 6720 } 6721 6722 bool isCLZForZeroUndef() const override { return false; } 6723 }; 6724 6725 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 6726 #define BUILTIN(ID, TYPE, ATTRS) \ 6727 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6728 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6729 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6730 #include "clang/Basic/BuiltinsMips.def" 6731 }; 6732 6733 class Mips32TargetInfoBase : public MipsTargetInfoBase { 6734 public: 6735 Mips32TargetInfoBase(const llvm::Triple &Triple) 6736 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 6737 SizeType = UnsignedInt; 6738 PtrDiffType = SignedInt; 6739 Int64Type = SignedLongLong; 6740 IntMaxType = Int64Type; 6741 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 6742 } 6743 bool setABI(const std::string &Name) override { 6744 if (Name == "o32" || Name == "eabi") { 6745 ABI = Name; 6746 return true; 6747 } 6748 return false; 6749 } 6750 void getTargetDefines(const LangOptions &Opts, 6751 MacroBuilder &Builder) const override { 6752 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6753 6754 Builder.defineMacro("__mips", "32"); 6755 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 6756 6757 const std::string& CPUStr = getCPU(); 6758 if (CPUStr == "mips32") 6759 Builder.defineMacro("__mips_isa_rev", "1"); 6760 else if (CPUStr == "mips32r2") 6761 Builder.defineMacro("__mips_isa_rev", "2"); 6762 else if (CPUStr == "mips32r3") 6763 Builder.defineMacro("__mips_isa_rev", "3"); 6764 else if (CPUStr == "mips32r5") 6765 Builder.defineMacro("__mips_isa_rev", "5"); 6766 else if (CPUStr == "mips32r6") 6767 Builder.defineMacro("__mips_isa_rev", "6"); 6768 6769 if (ABI == "o32") { 6770 Builder.defineMacro("__mips_o32"); 6771 Builder.defineMacro("_ABIO32", "1"); 6772 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6773 } 6774 else if (ABI == "eabi") 6775 Builder.defineMacro("__mips_eabi"); 6776 else 6777 llvm_unreachable("Invalid ABI for Mips32."); 6778 } 6779 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6780 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6781 { { "at" }, "$1" }, 6782 { { "v0" }, "$2" }, 6783 { { "v1" }, "$3" }, 6784 { { "a0" }, "$4" }, 6785 { { "a1" }, "$5" }, 6786 { { "a2" }, "$6" }, 6787 { { "a3" }, "$7" }, 6788 { { "t0" }, "$8" }, 6789 { { "t1" }, "$9" }, 6790 { { "t2" }, "$10" }, 6791 { { "t3" }, "$11" }, 6792 { { "t4" }, "$12" }, 6793 { { "t5" }, "$13" }, 6794 { { "t6" }, "$14" }, 6795 { { "t7" }, "$15" }, 6796 { { "s0" }, "$16" }, 6797 { { "s1" }, "$17" }, 6798 { { "s2" }, "$18" }, 6799 { { "s3" }, "$19" }, 6800 { { "s4" }, "$20" }, 6801 { { "s5" }, "$21" }, 6802 { { "s6" }, "$22" }, 6803 { { "s7" }, "$23" }, 6804 { { "t8" }, "$24" }, 6805 { { "t9" }, "$25" }, 6806 { { "k0" }, "$26" }, 6807 { { "k1" }, "$27" }, 6808 { { "gp" }, "$28" }, 6809 { { "sp","$sp" }, "$29" }, 6810 { { "fp","$fp" }, "$30" }, 6811 { { "ra" }, "$31" } 6812 }; 6813 return llvm::makeArrayRef(GCCRegAliases); 6814 } 6815 }; 6816 6817 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6818 void setDataLayoutString() override { 6819 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6820 } 6821 6822 public: 6823 Mips32EBTargetInfo(const llvm::Triple &Triple) 6824 : Mips32TargetInfoBase(Triple) { 6825 } 6826 void getTargetDefines(const LangOptions &Opts, 6827 MacroBuilder &Builder) const override { 6828 DefineStd(Builder, "MIPSEB", Opts); 6829 Builder.defineMacro("_MIPSEB"); 6830 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6831 } 6832 }; 6833 6834 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6835 void setDataLayoutString() override { 6836 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6837 } 6838 6839 public: 6840 Mips32ELTargetInfo(const llvm::Triple &Triple) 6841 : Mips32TargetInfoBase(Triple) { 6842 BigEndian = false; 6843 } 6844 void getTargetDefines(const LangOptions &Opts, 6845 MacroBuilder &Builder) const override { 6846 DefineStd(Builder, "MIPSEL", Opts); 6847 Builder.defineMacro("_MIPSEL"); 6848 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6849 } 6850 }; 6851 6852 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6853 public: 6854 Mips64TargetInfoBase(const llvm::Triple &Triple) 6855 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6856 LongDoubleWidth = LongDoubleAlign = 128; 6857 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6858 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6859 LongDoubleWidth = LongDoubleAlign = 64; 6860 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6861 } 6862 setN64ABITypes(); 6863 SuitableAlign = 128; 6864 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6865 } 6866 6867 void setN64ABITypes() { 6868 LongWidth = LongAlign = 64; 6869 PointerWidth = PointerAlign = 64; 6870 SizeType = UnsignedLong; 6871 PtrDiffType = SignedLong; 6872 Int64Type = SignedLong; 6873 IntMaxType = Int64Type; 6874 } 6875 6876 void setN32ABITypes() { 6877 LongWidth = LongAlign = 32; 6878 PointerWidth = PointerAlign = 32; 6879 SizeType = UnsignedInt; 6880 PtrDiffType = SignedInt; 6881 Int64Type = SignedLongLong; 6882 IntMaxType = Int64Type; 6883 } 6884 6885 bool setABI(const std::string &Name) override { 6886 if (Name == "n32") { 6887 setN32ABITypes(); 6888 ABI = Name; 6889 return true; 6890 } 6891 if (Name == "n64") { 6892 setN64ABITypes(); 6893 ABI = Name; 6894 return true; 6895 } 6896 return false; 6897 } 6898 6899 void getTargetDefines(const LangOptions &Opts, 6900 MacroBuilder &Builder) const override { 6901 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6902 6903 Builder.defineMacro("__mips", "64"); 6904 Builder.defineMacro("__mips64"); 6905 Builder.defineMacro("__mips64__"); 6906 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 6907 6908 const std::string& CPUStr = getCPU(); 6909 if (CPUStr == "mips64") 6910 Builder.defineMacro("__mips_isa_rev", "1"); 6911 else if (CPUStr == "mips64r2") 6912 Builder.defineMacro("__mips_isa_rev", "2"); 6913 else if (CPUStr == "mips64r3") 6914 Builder.defineMacro("__mips_isa_rev", "3"); 6915 else if (CPUStr == "mips64r5") 6916 Builder.defineMacro("__mips_isa_rev", "5"); 6917 else if (CPUStr == "mips64r6") 6918 Builder.defineMacro("__mips_isa_rev", "6"); 6919 6920 if (ABI == "n32") { 6921 Builder.defineMacro("__mips_n32"); 6922 Builder.defineMacro("_ABIN32", "2"); 6923 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 6924 } 6925 else if (ABI == "n64") { 6926 Builder.defineMacro("__mips_n64"); 6927 Builder.defineMacro("_ABI64", "3"); 6928 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 6929 } 6930 else 6931 llvm_unreachable("Invalid ABI for Mips64."); 6932 } 6933 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6934 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6935 { { "at" }, "$1" }, 6936 { { "v0" }, "$2" }, 6937 { { "v1" }, "$3" }, 6938 { { "a0" }, "$4" }, 6939 { { "a1" }, "$5" }, 6940 { { "a2" }, "$6" }, 6941 { { "a3" }, "$7" }, 6942 { { "a4" }, "$8" }, 6943 { { "a5" }, "$9" }, 6944 { { "a6" }, "$10" }, 6945 { { "a7" }, "$11" }, 6946 { { "t0" }, "$12" }, 6947 { { "t1" }, "$13" }, 6948 { { "t2" }, "$14" }, 6949 { { "t3" }, "$15" }, 6950 { { "s0" }, "$16" }, 6951 { { "s1" }, "$17" }, 6952 { { "s2" }, "$18" }, 6953 { { "s3" }, "$19" }, 6954 { { "s4" }, "$20" }, 6955 { { "s5" }, "$21" }, 6956 { { "s6" }, "$22" }, 6957 { { "s7" }, "$23" }, 6958 { { "t8" }, "$24" }, 6959 { { "t9" }, "$25" }, 6960 { { "k0" }, "$26" }, 6961 { { "k1" }, "$27" }, 6962 { { "gp" }, "$28" }, 6963 { { "sp","$sp" }, "$29" }, 6964 { { "fp","$fp" }, "$30" }, 6965 { { "ra" }, "$31" } 6966 }; 6967 return llvm::makeArrayRef(GCCRegAliases); 6968 } 6969 6970 bool hasInt128Type() const override { return true; } 6971 }; 6972 6973 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 6974 void setDataLayoutString() override { 6975 if (ABI == "n32") 6976 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6977 else 6978 DataLayoutString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6979 6980 } 6981 6982 public: 6983 Mips64EBTargetInfo(const llvm::Triple &Triple) 6984 : Mips64TargetInfoBase(Triple) {} 6985 void getTargetDefines(const LangOptions &Opts, 6986 MacroBuilder &Builder) const override { 6987 DefineStd(Builder, "MIPSEB", Opts); 6988 Builder.defineMacro("_MIPSEB"); 6989 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6990 } 6991 }; 6992 6993 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 6994 void setDataLayoutString() override { 6995 if (ABI == "n32") 6996 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6997 else 6998 DataLayoutString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6999 } 7000 public: 7001 Mips64ELTargetInfo(const llvm::Triple &Triple) 7002 : Mips64TargetInfoBase(Triple) { 7003 // Default ABI is n64. 7004 BigEndian = false; 7005 } 7006 void getTargetDefines(const LangOptions &Opts, 7007 MacroBuilder &Builder) const override { 7008 DefineStd(Builder, "MIPSEL", Opts); 7009 Builder.defineMacro("_MIPSEL"); 7010 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7011 } 7012 }; 7013 7014 class PNaClTargetInfo : public TargetInfo { 7015 public: 7016 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7017 BigEndian = false; 7018 this->UserLabelPrefix = ""; 7019 this->LongAlign = 32; 7020 this->LongWidth = 32; 7021 this->PointerAlign = 32; 7022 this->PointerWidth = 32; 7023 this->IntMaxType = TargetInfo::SignedLongLong; 7024 this->Int64Type = TargetInfo::SignedLongLong; 7025 this->DoubleAlign = 64; 7026 this->LongDoubleWidth = 64; 7027 this->LongDoubleAlign = 64; 7028 this->SizeType = TargetInfo::UnsignedInt; 7029 this->PtrDiffType = TargetInfo::SignedInt; 7030 this->IntPtrType = TargetInfo::SignedInt; 7031 this->RegParmMax = 0; // Disallow regparm 7032 } 7033 7034 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7035 Builder.defineMacro("__le32__"); 7036 Builder.defineMacro("__pnacl__"); 7037 } 7038 void getTargetDefines(const LangOptions &Opts, 7039 MacroBuilder &Builder) const override { 7040 getArchDefines(Opts, Builder); 7041 } 7042 bool hasFeature(StringRef Feature) const override { 7043 return Feature == "pnacl"; 7044 } 7045 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7046 BuiltinVaListKind getBuiltinVaListKind() const override { 7047 return TargetInfo::PNaClABIBuiltinVaList; 7048 } 7049 ArrayRef<const char *> getGCCRegNames() const override; 7050 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7051 bool validateAsmConstraint(const char *&Name, 7052 TargetInfo::ConstraintInfo &Info) const override { 7053 return false; 7054 } 7055 7056 const char *getClobbers() const override { 7057 return ""; 7058 } 7059 }; 7060 7061 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7062 return None; 7063 } 7064 7065 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7066 return None; 7067 } 7068 7069 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7070 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 7071 public: 7072 NaClMips32ELTargetInfo(const llvm::Triple &Triple) : 7073 Mips32ELTargetInfo(Triple) { 7074 } 7075 7076 BuiltinVaListKind getBuiltinVaListKind() const override { 7077 return TargetInfo::PNaClABIBuiltinVaList; 7078 } 7079 }; 7080 7081 class Le64TargetInfo : public TargetInfo { 7082 static const Builtin::Info BuiltinInfo[]; 7083 7084 public: 7085 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7086 BigEndian = false; 7087 NoAsmVariants = true; 7088 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7089 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7090 DataLayoutString = "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 7091 } 7092 7093 void getTargetDefines(const LangOptions &Opts, 7094 MacroBuilder &Builder) const override { 7095 DefineStd(Builder, "unix", Opts); 7096 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7097 Builder.defineMacro("__ELF__"); 7098 } 7099 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7100 return llvm::makeArrayRef(BuiltinInfo, 7101 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7102 } 7103 BuiltinVaListKind getBuiltinVaListKind() const override { 7104 return TargetInfo::PNaClABIBuiltinVaList; 7105 } 7106 const char *getClobbers() const override { return ""; } 7107 ArrayRef<const char *> getGCCRegNames() const override { 7108 return None; 7109 } 7110 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7111 return None; 7112 } 7113 bool validateAsmConstraint(const char *&Name, 7114 TargetInfo::ConstraintInfo &Info) const override { 7115 return false; 7116 } 7117 7118 bool hasProtectedVisibility() const override { return false; } 7119 }; 7120 7121 class WebAssemblyTargetInfo : public TargetInfo { 7122 static const Builtin::Info BuiltinInfo[]; 7123 7124 enum SIMDEnum { 7125 NoSIMD, 7126 SIMD128, 7127 } SIMDLevel; 7128 7129 public: 7130 explicit WebAssemblyTargetInfo(const llvm::Triple &T) 7131 : TargetInfo(T), SIMDLevel(NoSIMD) { 7132 BigEndian = false; 7133 NoAsmVariants = true; 7134 SuitableAlign = 128; 7135 LargeArrayMinWidth = 128; 7136 LargeArrayAlign = 128; 7137 SimdDefaultAlign = 128; 7138 SigAtomicType = SignedLong; 7139 LongDoubleWidth = LongDoubleAlign = 128; 7140 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7141 } 7142 7143 protected: 7144 void getTargetDefines(const LangOptions &Opts, 7145 MacroBuilder &Builder) const override { 7146 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7147 if (SIMDLevel >= SIMD128) 7148 Builder.defineMacro("__wasm_simd128__"); 7149 } 7150 7151 private: 7152 bool 7153 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7154 StringRef CPU, 7155 const std::vector<std::string> &FeaturesVec) const override { 7156 if (CPU == "bleeding-edge") 7157 Features["simd128"] = true; 7158 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7159 } 7160 bool hasFeature(StringRef Feature) const final { 7161 return llvm::StringSwitch<bool>(Feature) 7162 .Case("simd128", SIMDLevel >= SIMD128) 7163 .Default(false); 7164 } 7165 bool handleTargetFeatures(std::vector<std::string> &Features, 7166 DiagnosticsEngine &Diags) final { 7167 for (const auto &Feature : Features) { 7168 if (Feature == "+simd128") { 7169 SIMDLevel = std::max(SIMDLevel, SIMD128); 7170 continue; 7171 } 7172 if (Feature == "-simd128") { 7173 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7174 continue; 7175 } 7176 7177 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7178 << "-target-feature"; 7179 return false; 7180 } 7181 return true; 7182 } 7183 bool setCPU(const std::string &Name) final { 7184 return llvm::StringSwitch<bool>(Name) 7185 .Case("mvp", true) 7186 .Case("bleeding-edge", true) 7187 .Case("generic", true) 7188 .Default(false); 7189 } 7190 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7191 return llvm::makeArrayRef(BuiltinInfo, 7192 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7193 } 7194 BuiltinVaListKind getBuiltinVaListKind() const final { 7195 // TODO: Implement va_list properly. 7196 return VoidPtrBuiltinVaList; 7197 } 7198 ArrayRef<const char *> getGCCRegNames() const final { 7199 return None; 7200 } 7201 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7202 return None; 7203 } 7204 bool 7205 validateAsmConstraint(const char *&Name, 7206 TargetInfo::ConstraintInfo &Info) const final { 7207 return false; 7208 } 7209 const char *getClobbers() const final { return ""; } 7210 bool isCLZForZeroUndef() const final { return false; } 7211 bool hasInt128Type() const final { return true; } 7212 IntType getIntTypeByWidth(unsigned BitWidth, 7213 bool IsSigned) const final { 7214 // WebAssembly prefers long long for explicitly 64-bit integers. 7215 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7216 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7217 } 7218 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7219 bool IsSigned) const final { 7220 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7221 return BitWidth == 64 7222 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7223 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7224 } 7225 }; 7226 7227 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7228 #define BUILTIN(ID, TYPE, ATTRS) \ 7229 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7230 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7231 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7232 #include "clang/Basic/BuiltinsWebAssembly.def" 7233 }; 7234 7235 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7236 public: 7237 explicit WebAssembly32TargetInfo(const llvm::Triple &T) 7238 : WebAssemblyTargetInfo(T) { 7239 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7240 DataLayoutString = "e-p:32:32-i64:64-n32:64-S128"; 7241 } 7242 7243 protected: 7244 void getTargetDefines(const LangOptions &Opts, 7245 MacroBuilder &Builder) const override { 7246 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7247 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7248 } 7249 }; 7250 7251 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7252 public: 7253 explicit WebAssembly64TargetInfo(const llvm::Triple &T) 7254 : WebAssemblyTargetInfo(T) { 7255 LongAlign = LongWidth = 64; 7256 PointerAlign = PointerWidth = 64; 7257 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7258 DataLayoutString = "e-p:64:64-i64:64-n32:64-S128"; 7259 } 7260 7261 protected: 7262 void getTargetDefines(const LangOptions &Opts, 7263 MacroBuilder &Builder) const override { 7264 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7265 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7266 } 7267 }; 7268 7269 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7270 #define BUILTIN(ID, TYPE, ATTRS) \ 7271 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7272 #include "clang/Basic/BuiltinsLe64.def" 7273 }; 7274 7275 static const unsigned SPIRAddrSpaceMap[] = { 7276 1, // opencl_global 7277 3, // opencl_local 7278 2, // opencl_constant 7279 4, // opencl_generic 7280 0, // cuda_device 7281 0, // cuda_constant 7282 0 // cuda_shared 7283 }; 7284 class SPIRTargetInfo : public TargetInfo { 7285 public: 7286 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7287 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7288 "SPIR target must use unknown OS"); 7289 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7290 "SPIR target must use unknown environment type"); 7291 BigEndian = false; 7292 TLSSupported = false; 7293 LongWidth = LongAlign = 64; 7294 AddrSpaceMap = &SPIRAddrSpaceMap; 7295 UseAddrSpaceMapMangling = true; 7296 // Define available target features 7297 // These must be defined in sorted order! 7298 NoAsmVariants = true; 7299 } 7300 void getTargetDefines(const LangOptions &Opts, 7301 MacroBuilder &Builder) const override { 7302 DefineStd(Builder, "SPIR", Opts); 7303 } 7304 bool hasFeature(StringRef Feature) const override { 7305 return Feature == "spir"; 7306 } 7307 7308 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7309 const char *getClobbers() const override { return ""; } 7310 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7311 bool validateAsmConstraint(const char *&Name, 7312 TargetInfo::ConstraintInfo &info) const override { 7313 return true; 7314 } 7315 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7316 return None; 7317 } 7318 BuiltinVaListKind getBuiltinVaListKind() const override { 7319 return TargetInfo::VoidPtrBuiltinVaList; 7320 } 7321 7322 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7323 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK 7324 : CCCR_Warning; 7325 } 7326 7327 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7328 return CC_SpirFunction; 7329 } 7330 }; 7331 7332 class SPIR32TargetInfo : public SPIRTargetInfo { 7333 public: 7334 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7335 PointerWidth = PointerAlign = 32; 7336 SizeType = TargetInfo::UnsignedInt; 7337 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7338 DataLayoutString = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7339 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7340 } 7341 void getTargetDefines(const LangOptions &Opts, 7342 MacroBuilder &Builder) const override { 7343 DefineStd(Builder, "SPIR32", Opts); 7344 } 7345 }; 7346 7347 class SPIR64TargetInfo : public SPIRTargetInfo { 7348 public: 7349 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7350 PointerWidth = PointerAlign = 64; 7351 SizeType = TargetInfo::UnsignedLong; 7352 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7353 DataLayoutString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7354 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7355 } 7356 void getTargetDefines(const LangOptions &Opts, 7357 MacroBuilder &Builder) const override { 7358 DefineStd(Builder, "SPIR64", Opts); 7359 } 7360 }; 7361 7362 class XCoreTargetInfo : public TargetInfo { 7363 static const Builtin::Info BuiltinInfo[]; 7364 public: 7365 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7366 BigEndian = false; 7367 NoAsmVariants = true; 7368 LongLongAlign = 32; 7369 SuitableAlign = 32; 7370 DoubleAlign = LongDoubleAlign = 32; 7371 SizeType = UnsignedInt; 7372 PtrDiffType = SignedInt; 7373 IntPtrType = SignedInt; 7374 WCharType = UnsignedChar; 7375 WIntType = UnsignedInt; 7376 UseZeroLengthBitfieldAlignment = true; 7377 DataLayoutString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7378 "-f64:32-a:0:32-n32"; 7379 } 7380 void getTargetDefines(const LangOptions &Opts, 7381 MacroBuilder &Builder) const override { 7382 Builder.defineMacro("__XS1B__"); 7383 } 7384 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7385 return llvm::makeArrayRef(BuiltinInfo, 7386 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 7387 } 7388 BuiltinVaListKind getBuiltinVaListKind() const override { 7389 return TargetInfo::VoidPtrBuiltinVaList; 7390 } 7391 const char *getClobbers() const override { 7392 return ""; 7393 } 7394 ArrayRef<const char *> getGCCRegNames() const override { 7395 static const char * const GCCRegNames[] = { 7396 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7397 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 7398 }; 7399 return llvm::makeArrayRef(GCCRegNames); 7400 } 7401 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7402 return None; 7403 } 7404 bool validateAsmConstraint(const char *&Name, 7405 TargetInfo::ConstraintInfo &Info) const override { 7406 return false; 7407 } 7408 int getEHDataRegisterNumber(unsigned RegNo) const override { 7409 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7410 return (RegNo < 2)? RegNo : -1; 7411 } 7412 }; 7413 7414 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7415 #define BUILTIN(ID, TYPE, ATTRS) \ 7416 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7417 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7418 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7419 #include "clang/Basic/BuiltinsXCore.def" 7420 }; 7421 7422 // x86_32 Android target 7423 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7424 public: 7425 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 7426 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 7427 SuitableAlign = 32; 7428 LongDoubleWidth = 64; 7429 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7430 } 7431 }; 7432 7433 // x86_64 Android target 7434 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7435 public: 7436 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 7437 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 7438 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7439 } 7440 7441 bool useFloat128ManglingForLongDouble() const override { 7442 return true; 7443 } 7444 }; 7445 } // end anonymous namespace 7446 7447 //===----------------------------------------------------------------------===// 7448 // Driver code 7449 //===----------------------------------------------------------------------===// 7450 7451 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 7452 llvm::Triple::OSType os = Triple.getOS(); 7453 7454 switch (Triple.getArch()) { 7455 default: 7456 return nullptr; 7457 7458 case llvm::Triple::xcore: 7459 return new XCoreTargetInfo(Triple); 7460 7461 case llvm::Triple::hexagon: 7462 return new HexagonTargetInfo(Triple); 7463 7464 case llvm::Triple::aarch64: 7465 if (Triple.isOSDarwin()) 7466 return new DarwinAArch64TargetInfo(Triple); 7467 7468 switch (os) { 7469 case llvm::Triple::CloudABI: 7470 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple); 7471 case llvm::Triple::FreeBSD: 7472 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 7473 case llvm::Triple::Linux: 7474 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 7475 case llvm::Triple::NetBSD: 7476 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 7477 default: 7478 return new AArch64leTargetInfo(Triple); 7479 } 7480 7481 case llvm::Triple::aarch64_be: 7482 switch (os) { 7483 case llvm::Triple::FreeBSD: 7484 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 7485 case llvm::Triple::Linux: 7486 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 7487 case llvm::Triple::NetBSD: 7488 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 7489 default: 7490 return new AArch64beTargetInfo(Triple); 7491 } 7492 7493 case llvm::Triple::arm: 7494 case llvm::Triple::thumb: 7495 if (Triple.isOSBinFormatMachO()) 7496 return new DarwinARMTargetInfo(Triple); 7497 7498 switch (os) { 7499 case llvm::Triple::Linux: 7500 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 7501 case llvm::Triple::FreeBSD: 7502 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 7503 case llvm::Triple::NetBSD: 7504 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 7505 case llvm::Triple::OpenBSD: 7506 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 7507 case llvm::Triple::Bitrig: 7508 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 7509 case llvm::Triple::RTEMS: 7510 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 7511 case llvm::Triple::NaCl: 7512 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 7513 case llvm::Triple::Win32: 7514 switch (Triple.getEnvironment()) { 7515 case llvm::Triple::Cygnus: 7516 return new CygwinARMTargetInfo(Triple); 7517 case llvm::Triple::GNU: 7518 return new MinGWARMTargetInfo(Triple); 7519 case llvm::Triple::Itanium: 7520 return new ItaniumWindowsARMleTargetInfo(Triple); 7521 case llvm::Triple::MSVC: 7522 default: // Assume MSVC for unknown environments 7523 return new MicrosoftARMleTargetInfo(Triple); 7524 } 7525 default: 7526 return new ARMleTargetInfo(Triple); 7527 } 7528 7529 case llvm::Triple::armeb: 7530 case llvm::Triple::thumbeb: 7531 if (Triple.isOSDarwin()) 7532 return new DarwinARMTargetInfo(Triple); 7533 7534 switch (os) { 7535 case llvm::Triple::Linux: 7536 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 7537 case llvm::Triple::FreeBSD: 7538 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 7539 case llvm::Triple::NetBSD: 7540 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 7541 case llvm::Triple::OpenBSD: 7542 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 7543 case llvm::Triple::Bitrig: 7544 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 7545 case llvm::Triple::RTEMS: 7546 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 7547 case llvm::Triple::NaCl: 7548 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 7549 default: 7550 return new ARMbeTargetInfo(Triple); 7551 } 7552 7553 case llvm::Triple::bpfeb: 7554 case llvm::Triple::bpfel: 7555 return new BPFTargetInfo(Triple); 7556 7557 case llvm::Triple::msp430: 7558 return new MSP430TargetInfo(Triple); 7559 7560 case llvm::Triple::mips: 7561 switch (os) { 7562 case llvm::Triple::Linux: 7563 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 7564 case llvm::Triple::RTEMS: 7565 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 7566 case llvm::Triple::FreeBSD: 7567 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7568 case llvm::Triple::NetBSD: 7569 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7570 default: 7571 return new Mips32EBTargetInfo(Triple); 7572 } 7573 7574 case llvm::Triple::mipsel: 7575 switch (os) { 7576 case llvm::Triple::Linux: 7577 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 7578 case llvm::Triple::RTEMS: 7579 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 7580 case llvm::Triple::FreeBSD: 7581 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7582 case llvm::Triple::NetBSD: 7583 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7584 case llvm::Triple::NaCl: 7585 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple); 7586 default: 7587 return new Mips32ELTargetInfo(Triple); 7588 } 7589 7590 case llvm::Triple::mips64: 7591 switch (os) { 7592 case llvm::Triple::Linux: 7593 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 7594 case llvm::Triple::RTEMS: 7595 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 7596 case llvm::Triple::FreeBSD: 7597 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7598 case llvm::Triple::NetBSD: 7599 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7600 case llvm::Triple::OpenBSD: 7601 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7602 default: 7603 return new Mips64EBTargetInfo(Triple); 7604 } 7605 7606 case llvm::Triple::mips64el: 7607 switch (os) { 7608 case llvm::Triple::Linux: 7609 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 7610 case llvm::Triple::RTEMS: 7611 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 7612 case llvm::Triple::FreeBSD: 7613 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7614 case llvm::Triple::NetBSD: 7615 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7616 case llvm::Triple::OpenBSD: 7617 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7618 default: 7619 return new Mips64ELTargetInfo(Triple); 7620 } 7621 7622 case llvm::Triple::le32: 7623 switch (os) { 7624 case llvm::Triple::NaCl: 7625 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 7626 default: 7627 return nullptr; 7628 } 7629 7630 case llvm::Triple::le64: 7631 return new Le64TargetInfo(Triple); 7632 7633 case llvm::Triple::ppc: 7634 if (Triple.isOSDarwin()) 7635 return new DarwinPPC32TargetInfo(Triple); 7636 switch (os) { 7637 case llvm::Triple::Linux: 7638 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 7639 case llvm::Triple::FreeBSD: 7640 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 7641 case llvm::Triple::NetBSD: 7642 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 7643 case llvm::Triple::OpenBSD: 7644 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 7645 case llvm::Triple::RTEMS: 7646 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 7647 default: 7648 return new PPC32TargetInfo(Triple); 7649 } 7650 7651 case llvm::Triple::ppc64: 7652 if (Triple.isOSDarwin()) 7653 return new DarwinPPC64TargetInfo(Triple); 7654 switch (os) { 7655 case llvm::Triple::Linux: 7656 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7657 case llvm::Triple::Lv2: 7658 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 7659 case llvm::Triple::FreeBSD: 7660 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 7661 case llvm::Triple::NetBSD: 7662 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7663 default: 7664 return new PPC64TargetInfo(Triple); 7665 } 7666 7667 case llvm::Triple::ppc64le: 7668 switch (os) { 7669 case llvm::Triple::Linux: 7670 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7671 case llvm::Triple::NetBSD: 7672 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7673 default: 7674 return new PPC64TargetInfo(Triple); 7675 } 7676 7677 case llvm::Triple::nvptx: 7678 return new NVPTX32TargetInfo(Triple); 7679 case llvm::Triple::nvptx64: 7680 return new NVPTX64TargetInfo(Triple); 7681 7682 case llvm::Triple::amdgcn: 7683 case llvm::Triple::r600: 7684 return new AMDGPUTargetInfo(Triple); 7685 7686 case llvm::Triple::sparc: 7687 switch (os) { 7688 case llvm::Triple::Linux: 7689 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 7690 case llvm::Triple::Solaris: 7691 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple); 7692 case llvm::Triple::NetBSD: 7693 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 7694 case llvm::Triple::OpenBSD: 7695 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 7696 case llvm::Triple::RTEMS: 7697 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 7698 default: 7699 return new SparcV8TargetInfo(Triple); 7700 } 7701 7702 // The 'sparcel' architecture copies all the above cases except for Solaris. 7703 case llvm::Triple::sparcel: 7704 switch (os) { 7705 case llvm::Triple::Linux: 7706 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 7707 case llvm::Triple::NetBSD: 7708 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7709 case llvm::Triple::OpenBSD: 7710 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7711 case llvm::Triple::RTEMS: 7712 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 7713 default: 7714 return new SparcV8elTargetInfo(Triple); 7715 } 7716 7717 case llvm::Triple::sparcv9: 7718 switch (os) { 7719 case llvm::Triple::Linux: 7720 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 7721 case llvm::Triple::Solaris: 7722 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 7723 case llvm::Triple::NetBSD: 7724 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 7725 case llvm::Triple::OpenBSD: 7726 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 7727 case llvm::Triple::FreeBSD: 7728 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 7729 default: 7730 return new SparcV9TargetInfo(Triple); 7731 } 7732 7733 case llvm::Triple::systemz: 7734 switch (os) { 7735 case llvm::Triple::Linux: 7736 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 7737 default: 7738 return new SystemZTargetInfo(Triple); 7739 } 7740 7741 case llvm::Triple::tce: 7742 return new TCETargetInfo(Triple); 7743 7744 case llvm::Triple::x86: 7745 if (Triple.isOSDarwin()) 7746 return new DarwinI386TargetInfo(Triple); 7747 7748 switch (os) { 7749 case llvm::Triple::CloudABI: 7750 return new CloudABITargetInfo<X86_32TargetInfo>(Triple); 7751 case llvm::Triple::Linux: { 7752 switch (Triple.getEnvironment()) { 7753 default: 7754 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 7755 case llvm::Triple::Android: 7756 return new AndroidX86_32TargetInfo(Triple); 7757 } 7758 } 7759 case llvm::Triple::DragonFly: 7760 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 7761 case llvm::Triple::NetBSD: 7762 return new NetBSDI386TargetInfo(Triple); 7763 case llvm::Triple::OpenBSD: 7764 return new OpenBSDI386TargetInfo(Triple); 7765 case llvm::Triple::Bitrig: 7766 return new BitrigI386TargetInfo(Triple); 7767 case llvm::Triple::FreeBSD: 7768 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7769 case llvm::Triple::KFreeBSD: 7770 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7771 case llvm::Triple::Minix: 7772 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 7773 case llvm::Triple::Solaris: 7774 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 7775 case llvm::Triple::Win32: { 7776 switch (Triple.getEnvironment()) { 7777 case llvm::Triple::Cygnus: 7778 return new CygwinX86_32TargetInfo(Triple); 7779 case llvm::Triple::GNU: 7780 return new MinGWX86_32TargetInfo(Triple); 7781 case llvm::Triple::Itanium: 7782 case llvm::Triple::MSVC: 7783 default: // Assume MSVC for unknown environments 7784 return new MicrosoftX86_32TargetInfo(Triple); 7785 } 7786 } 7787 case llvm::Triple::Haiku: 7788 return new HaikuX86_32TargetInfo(Triple); 7789 case llvm::Triple::RTEMS: 7790 return new RTEMSX86_32TargetInfo(Triple); 7791 case llvm::Triple::NaCl: 7792 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 7793 case llvm::Triple::ELFIAMCU: 7794 return new MCUX86_32TargetInfo(Triple); 7795 default: 7796 return new X86_32TargetInfo(Triple); 7797 } 7798 7799 case llvm::Triple::x86_64: 7800 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 7801 return new DarwinX86_64TargetInfo(Triple); 7802 7803 switch (os) { 7804 case llvm::Triple::CloudABI: 7805 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 7806 case llvm::Triple::Linux: { 7807 switch (Triple.getEnvironment()) { 7808 default: 7809 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 7810 case llvm::Triple::Android: 7811 return new AndroidX86_64TargetInfo(Triple); 7812 } 7813 } 7814 case llvm::Triple::DragonFly: 7815 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 7816 case llvm::Triple::NetBSD: 7817 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 7818 case llvm::Triple::OpenBSD: 7819 return new OpenBSDX86_64TargetInfo(Triple); 7820 case llvm::Triple::Bitrig: 7821 return new BitrigX86_64TargetInfo(Triple); 7822 case llvm::Triple::FreeBSD: 7823 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7824 case llvm::Triple::KFreeBSD: 7825 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7826 case llvm::Triple::Solaris: 7827 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 7828 case llvm::Triple::Win32: { 7829 switch (Triple.getEnvironment()) { 7830 case llvm::Triple::Cygnus: 7831 return new CygwinX86_64TargetInfo(Triple); 7832 case llvm::Triple::GNU: 7833 return new MinGWX86_64TargetInfo(Triple); 7834 case llvm::Triple::MSVC: 7835 default: // Assume MSVC for unknown environments 7836 return new MicrosoftX86_64TargetInfo(Triple); 7837 } 7838 } 7839 case llvm::Triple::NaCl: 7840 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 7841 case llvm::Triple::PS4: 7842 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 7843 default: 7844 return new X86_64TargetInfo(Triple); 7845 } 7846 7847 case llvm::Triple::spir: { 7848 if (Triple.getOS() != llvm::Triple::UnknownOS || 7849 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7850 return nullptr; 7851 return new SPIR32TargetInfo(Triple); 7852 } 7853 case llvm::Triple::spir64: { 7854 if (Triple.getOS() != llvm::Triple::UnknownOS || 7855 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7856 return nullptr; 7857 return new SPIR64TargetInfo(Triple); 7858 } 7859 case llvm::Triple::wasm32: 7860 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 7861 return nullptr; 7862 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple); 7863 case llvm::Triple::wasm64: 7864 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 7865 return nullptr; 7866 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple); 7867 } 7868 } 7869 7870 /// CreateTargetInfo - Return the target info object for the specified target 7871 /// options. 7872 TargetInfo * 7873 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 7874 const std::shared_ptr<TargetOptions> &Opts) { 7875 llvm::Triple Triple(Opts->Triple); 7876 7877 // Construct the target 7878 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 7879 if (!Target) { 7880 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 7881 return nullptr; 7882 } 7883 Target->TargetOpts = Opts; 7884 7885 // Set the target CPU if specified. 7886 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 7887 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 7888 return nullptr; 7889 } 7890 7891 // Set the target ABI if specified. 7892 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 7893 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 7894 return nullptr; 7895 } 7896 7897 // Set the fp math unit. 7898 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 7899 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 7900 return nullptr; 7901 } 7902 7903 // Compute the default target features, we need the target to handle this 7904 // because features may have dependencies on one another. 7905 llvm::StringMap<bool> Features; 7906 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 7907 Opts->FeaturesAsWritten)) 7908 return nullptr; 7909 7910 // Add the features to the compile options. 7911 Opts->Features.clear(); 7912 for (const auto &F : Features) 7913 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 7914 7915 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 7916 return nullptr; 7917 7918 return Target.release(); 7919 } 7920