1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/OwningPtr.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Type.h" 31 #include <algorithm> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const std::string& triple) : TgtInfo(triple) {} 77 virtual void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "5621"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("__MACH__"); 94 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 95 96 if (!Opts.ObjCAutoRefCount) { 97 // __weak is always defined, for use in blocks and with objc pointers. 98 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 99 100 // Darwin defines __strong even in C mode (just to nothing). 101 if (Opts.getGC() != LangOptions::NonGC) 102 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 103 else 104 Builder.defineMacro("__strong", ""); 105 106 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 107 // allow this in C, since one might have block pointers in structs that 108 // are used in pure C code and in Objective-C ARC. 109 Builder.defineMacro("__unsafe_unretained", ""); 110 } 111 112 if (Opts.Static) 113 Builder.defineMacro("__STATIC__"); 114 else 115 Builder.defineMacro("__DYNAMIC__"); 116 117 if (Opts.POSIXThreads) 118 Builder.defineMacro("_REENTRANT"); 119 120 // Get the platform type and version number from the triple. 121 unsigned Maj, Min, Rev; 122 if (Triple.isMacOSX()) { 123 Triple.getMacOSXVersion(Maj, Min, Rev); 124 PlatformName = "macosx"; 125 } else { 126 Triple.getOSVersion(Maj, Min, Rev); 127 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 128 } 129 130 // If -target arch-pc-win32-macho option specified, we're 131 // generating code for Win32 ABI. No need to emit 132 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 133 if (PlatformName == "win32") { 134 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 135 return; 136 } 137 138 // Set the appropriate OS version define. 139 if (Triple.getOS() == llvm::Triple::IOS) { 140 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 141 char Str[6]; 142 Str[0] = '0' + Maj; 143 Str[1] = '0' + (Min / 10); 144 Str[2] = '0' + (Min % 10); 145 Str[3] = '0' + (Rev / 10); 146 Str[4] = '0' + (Rev % 10); 147 Str[5] = '\0'; 148 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str); 149 } else { 150 // Note that the Driver allows versions which aren't representable in the 151 // define (because we only get a single digit for the minor and micro 152 // revision numbers). So, we limit them to the maximum representable 153 // version. 154 assert(Triple.getEnvironmentName().empty() && "Invalid environment!"); 155 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 156 char Str[5]; 157 Str[0] = '0' + (Maj / 10); 158 Str[1] = '0' + (Maj % 10); 159 Str[2] = '0' + std::min(Min, 9U); 160 Str[3] = '0' + std::min(Rev, 9U); 161 Str[4] = '\0'; 162 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 163 } 164 165 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 166 } 167 168 namespace { 169 template<typename Target> 170 class DarwinTargetInfo : public OSTargetInfo<Target> { 171 protected: 172 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 173 MacroBuilder &Builder) const { 174 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 175 this->PlatformMinVersion); 176 } 177 178 public: 179 DarwinTargetInfo(const std::string& triple) : 180 OSTargetInfo<Target>(triple) { 181 llvm::Triple T = llvm::Triple(triple); 182 this->TLSSupported = T.isMacOSX() && !T.isMacOSXVersionLT(10,7); 183 this->MCountName = "\01mcount"; 184 } 185 186 virtual std::string isValidSectionSpecifier(StringRef SR) const { 187 // Let MCSectionMachO validate this. 188 StringRef Segment, Section; 189 unsigned TAA, StubSize; 190 bool HasTAA; 191 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 192 TAA, HasTAA, StubSize); 193 } 194 195 virtual const char *getStaticInitSectionSpecifier() const { 196 // FIXME: We should return 0 when building kexts. 197 return "__TEXT,__StaticInit,regular,pure_instructions"; 198 } 199 200 /// Darwin does not support protected visibility. Darwin's "default" 201 /// is very similar to ELF's "protected"; Darwin requires a "weak" 202 /// attribute on declarations that can be dynamically replaced. 203 virtual bool hasProtectedVisibility() const { 204 return false; 205 } 206 }; 207 208 209 // DragonFlyBSD Target 210 template<typename Target> 211 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 212 protected: 213 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 214 MacroBuilder &Builder) const { 215 // DragonFly defines; list based off of gcc output 216 Builder.defineMacro("__DragonFly__"); 217 Builder.defineMacro("__DragonFly_cc_version", "100001"); 218 Builder.defineMacro("__ELF__"); 219 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 220 Builder.defineMacro("__tune_i386__"); 221 DefineStd(Builder, "unix", Opts); 222 } 223 public: 224 DragonFlyBSDTargetInfo(const std::string &triple) 225 : OSTargetInfo<Target>(triple) { 226 this->UserLabelPrefix = ""; 227 228 llvm::Triple Triple(triple); 229 switch (Triple.getArch()) { 230 default: 231 case llvm::Triple::x86: 232 case llvm::Triple::x86_64: 233 this->MCountName = ".mcount"; 234 break; 235 } 236 } 237 }; 238 239 // FreeBSD Target 240 template<typename Target> 241 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 242 protected: 243 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 244 MacroBuilder &Builder) const { 245 // FreeBSD defines; list based off of gcc output 246 247 unsigned Release = Triple.getOSMajorVersion(); 248 if (Release == 0U) 249 Release = 8; 250 251 Builder.defineMacro("__FreeBSD__", Twine(Release)); 252 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 253 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 254 DefineStd(Builder, "unix", Opts); 255 Builder.defineMacro("__ELF__"); 256 } 257 public: 258 FreeBSDTargetInfo(const std::string &triple) 259 : OSTargetInfo<Target>(triple) { 260 this->UserLabelPrefix = ""; 261 262 llvm::Triple Triple(triple); 263 switch (Triple.getArch()) { 264 default: 265 case llvm::Triple::x86: 266 case llvm::Triple::x86_64: 267 this->MCountName = ".mcount"; 268 break; 269 case llvm::Triple::mips: 270 case llvm::Triple::mipsel: 271 case llvm::Triple::ppc: 272 case llvm::Triple::ppc64: 273 this->MCountName = "_mcount"; 274 break; 275 case llvm::Triple::arm: 276 this->MCountName = "__mcount"; 277 break; 278 } 279 280 } 281 }; 282 283 // Minix Target 284 template<typename Target> 285 class MinixTargetInfo : public OSTargetInfo<Target> { 286 protected: 287 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 288 MacroBuilder &Builder) const { 289 // Minix defines 290 291 Builder.defineMacro("__minix", "3"); 292 Builder.defineMacro("_EM_WSIZE", "4"); 293 Builder.defineMacro("_EM_PSIZE", "4"); 294 Builder.defineMacro("_EM_SSIZE", "2"); 295 Builder.defineMacro("_EM_LSIZE", "4"); 296 Builder.defineMacro("_EM_FSIZE", "4"); 297 Builder.defineMacro("_EM_DSIZE", "8"); 298 Builder.defineMacro("__ELF__"); 299 DefineStd(Builder, "unix", Opts); 300 } 301 public: 302 MinixTargetInfo(const std::string &triple) 303 : OSTargetInfo<Target>(triple) { 304 this->UserLabelPrefix = ""; 305 } 306 }; 307 308 // Linux target 309 template<typename Target> 310 class LinuxTargetInfo : public OSTargetInfo<Target> { 311 protected: 312 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 313 MacroBuilder &Builder) const { 314 // Linux defines; list based off of gcc output 315 DefineStd(Builder, "unix", Opts); 316 DefineStd(Builder, "linux", Opts); 317 Builder.defineMacro("__gnu_linux__"); 318 Builder.defineMacro("__ELF__"); 319 if (Triple.getEnvironment() == llvm::Triple::ANDROIDEABI) 320 Builder.defineMacro("__ANDROID__", "1"); 321 if (Opts.POSIXThreads) 322 Builder.defineMacro("_REENTRANT"); 323 if (Opts.CPlusPlus) 324 Builder.defineMacro("_GNU_SOURCE"); 325 } 326 public: 327 LinuxTargetInfo(const std::string& triple) 328 : OSTargetInfo<Target>(triple) { 329 this->UserLabelPrefix = ""; 330 this->WIntType = TargetInfo::UnsignedInt; 331 } 332 333 virtual const char *getStaticInitSectionSpecifier() const { 334 return ".text.startup"; 335 } 336 }; 337 338 // NetBSD Target 339 template<typename Target> 340 class NetBSDTargetInfo : public OSTargetInfo<Target> { 341 protected: 342 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 343 MacroBuilder &Builder) const { 344 // NetBSD defines; list based off of gcc output 345 Builder.defineMacro("__NetBSD__"); 346 Builder.defineMacro("__unix__"); 347 Builder.defineMacro("__ELF__"); 348 if (Opts.POSIXThreads) 349 Builder.defineMacro("_POSIX_THREADS"); 350 } 351 public: 352 NetBSDTargetInfo(const std::string &triple) 353 : OSTargetInfo<Target>(triple) { 354 this->UserLabelPrefix = ""; 355 } 356 }; 357 358 // OpenBSD Target 359 template<typename Target> 360 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 361 protected: 362 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 363 MacroBuilder &Builder) const { 364 // OpenBSD defines; list based off of gcc output 365 366 Builder.defineMacro("__OpenBSD__"); 367 DefineStd(Builder, "unix", Opts); 368 Builder.defineMacro("__ELF__"); 369 if (Opts.POSIXThreads) 370 Builder.defineMacro("_REENTRANT"); 371 } 372 public: 373 OpenBSDTargetInfo(const std::string &triple) 374 : OSTargetInfo<Target>(triple) { 375 this->UserLabelPrefix = ""; 376 377 llvm::Triple Triple(triple); 378 switch (Triple.getArch()) { 379 default: 380 case llvm::Triple::x86: 381 case llvm::Triple::x86_64: 382 case llvm::Triple::arm: 383 case llvm::Triple::sparc: 384 this->MCountName = "__mcount"; 385 break; 386 case llvm::Triple::mips64: 387 case llvm::Triple::mips64el: 388 case llvm::Triple::ppc: 389 case llvm::Triple::sparcv9: 390 this->MCountName = "_mcount"; 391 break; 392 } 393 } 394 }; 395 396 // PSP Target 397 template<typename Target> 398 class PSPTargetInfo : public OSTargetInfo<Target> { 399 protected: 400 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 401 MacroBuilder &Builder) const { 402 // PSP defines; list based on the output of the pspdev gcc toolchain. 403 Builder.defineMacro("PSP"); 404 Builder.defineMacro("_PSP"); 405 Builder.defineMacro("__psp__"); 406 Builder.defineMacro("__ELF__"); 407 } 408 public: 409 PSPTargetInfo(const std::string& triple) 410 : OSTargetInfo<Target>(triple) { 411 this->UserLabelPrefix = ""; 412 } 413 }; 414 415 // PS3 PPU Target 416 template<typename Target> 417 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 418 protected: 419 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 420 MacroBuilder &Builder) const { 421 // PS3 PPU defines. 422 Builder.defineMacro("__PPC__"); 423 Builder.defineMacro("__PPU__"); 424 Builder.defineMacro("__CELLOS_LV2__"); 425 Builder.defineMacro("__ELF__"); 426 Builder.defineMacro("__LP32__"); 427 Builder.defineMacro("_ARCH_PPC64"); 428 Builder.defineMacro("__powerpc64__"); 429 } 430 public: 431 PS3PPUTargetInfo(const std::string& triple) 432 : OSTargetInfo<Target>(triple) { 433 this->UserLabelPrefix = ""; 434 this->LongWidth = this->LongAlign = 32; 435 this->PointerWidth = this->PointerAlign = 32; 436 this->IntMaxType = TargetInfo::SignedLongLong; 437 this->UIntMaxType = TargetInfo::UnsignedLongLong; 438 this->Int64Type = TargetInfo::SignedLongLong; 439 this->SizeType = TargetInfo::UnsignedInt; 440 this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 441 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"; 442 } 443 }; 444 445 // FIXME: Need a real SPU target. 446 // PS3 SPU Target 447 template<typename Target> 448 class PS3SPUTargetInfo : public OSTargetInfo<Target> { 449 protected: 450 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 451 MacroBuilder &Builder) const { 452 // PS3 PPU defines. 453 Builder.defineMacro("__SPU__"); 454 Builder.defineMacro("__ELF__"); 455 } 456 public: 457 PS3SPUTargetInfo(const std::string& triple) 458 : OSTargetInfo<Target>(triple) { 459 this->UserLabelPrefix = ""; 460 } 461 }; 462 463 // AuroraUX target 464 template<typename Target> 465 class AuroraUXTargetInfo : public OSTargetInfo<Target> { 466 protected: 467 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 468 MacroBuilder &Builder) const { 469 DefineStd(Builder, "sun", Opts); 470 DefineStd(Builder, "unix", Opts); 471 Builder.defineMacro("__ELF__"); 472 Builder.defineMacro("__svr4__"); 473 Builder.defineMacro("__SVR4"); 474 } 475 public: 476 AuroraUXTargetInfo(const std::string& triple) 477 : OSTargetInfo<Target>(triple) { 478 this->UserLabelPrefix = ""; 479 this->WCharType = this->SignedLong; 480 // FIXME: WIntType should be SignedLong 481 } 482 }; 483 484 // Solaris target 485 template<typename Target> 486 class SolarisTargetInfo : public OSTargetInfo<Target> { 487 protected: 488 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 489 MacroBuilder &Builder) const { 490 DefineStd(Builder, "sun", Opts); 491 DefineStd(Builder, "unix", Opts); 492 Builder.defineMacro("__ELF__"); 493 Builder.defineMacro("__svr4__"); 494 Builder.defineMacro("__SVR4"); 495 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 496 // newer, but to 500 for everything else. feature_test.h has a check to 497 // ensure that you are not using C99 with an old version of X/Open or C89 498 // with a new version. 499 if (Opts.C99 || Opts.C11) 500 Builder.defineMacro("_XOPEN_SOURCE", "600"); 501 else 502 Builder.defineMacro("_XOPEN_SOURCE", "500"); 503 if (Opts.CPlusPlus) 504 Builder.defineMacro("__C99FEATURES__"); 505 Builder.defineMacro("_LARGEFILE_SOURCE"); 506 Builder.defineMacro("_LARGEFILE64_SOURCE"); 507 Builder.defineMacro("__EXTENSIONS__"); 508 Builder.defineMacro("_REENTRANT"); 509 } 510 public: 511 SolarisTargetInfo(const std::string& triple) 512 : OSTargetInfo<Target>(triple) { 513 this->UserLabelPrefix = ""; 514 this->WCharType = this->SignedInt; 515 // FIXME: WIntType should be SignedLong 516 } 517 }; 518 519 // Windows target 520 template<typename Target> 521 class WindowsTargetInfo : public OSTargetInfo<Target> { 522 protected: 523 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 524 MacroBuilder &Builder) const { 525 Builder.defineMacro("_WIN32"); 526 } 527 void getVisualStudioDefines(const LangOptions &Opts, 528 MacroBuilder &Builder) const { 529 if (Opts.CPlusPlus) { 530 if (Opts.RTTI) 531 Builder.defineMacro("_CPPRTTI"); 532 533 if (Opts.Exceptions) 534 Builder.defineMacro("_CPPUNWIND"); 535 } 536 537 if (!Opts.CharIsSigned) 538 Builder.defineMacro("_CHAR_UNSIGNED"); 539 540 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 541 // but it works for now. 542 if (Opts.POSIXThreads) 543 Builder.defineMacro("_MT"); 544 545 if (Opts.MSCVersion != 0) 546 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion)); 547 548 if (Opts.MicrosoftExt) { 549 Builder.defineMacro("_MSC_EXTENSIONS"); 550 551 if (Opts.CPlusPlus0x) { 552 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 553 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 554 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 555 } 556 } 557 558 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 559 } 560 561 public: 562 WindowsTargetInfo(const std::string &triple) 563 : OSTargetInfo<Target>(triple) {} 564 }; 565 566 } // end anonymous namespace. 567 568 //===----------------------------------------------------------------------===// 569 // Specific target implementations. 570 //===----------------------------------------------------------------------===// 571 572 namespace { 573 // PPC abstract base class 574 class PPCTargetInfo : public TargetInfo { 575 static const Builtin::Info BuiltinInfo[]; 576 static const char * const GCCRegNames[]; 577 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 578 std::string CPU; 579 public: 580 PPCTargetInfo(const std::string& triple) : TargetInfo(triple) { 581 LongDoubleWidth = LongDoubleAlign = 128; 582 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 583 } 584 585 /// \brief Flags for architecture specific defines. 586 typedef enum { 587 ArchDefineNone = 0, 588 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 589 ArchDefinePpcgr = 1 << 1, 590 ArchDefinePpcsq = 1 << 2, 591 ArchDefine440 = 1 << 3, 592 ArchDefine603 = 1 << 4, 593 ArchDefine604 = 1 << 5, 594 ArchDefinePwr4 = 1 << 6, 595 ArchDefinePwr6 = 1 << 7 596 } ArchDefineTypes; 597 598 virtual bool setCPU(const std::string &Name) { 599 bool CPUKnown = llvm::StringSwitch<bool>(Name) 600 .Case("generic", true) 601 .Case("440", true) 602 .Case("450", true) 603 .Case("601", true) 604 .Case("602", true) 605 .Case("603", true) 606 .Case("603e", true) 607 .Case("603ev", true) 608 .Case("604", true) 609 .Case("604e", true) 610 .Case("620", true) 611 .Case("g3", true) 612 .Case("7400", true) 613 .Case("g4", true) 614 .Case("7450", true) 615 .Case("g4+", true) 616 .Case("750", true) 617 .Case("970", true) 618 .Case("g5", true) 619 .Case("a2", true) 620 .Case("pwr6", true) 621 .Case("pwr7", true) 622 .Case("ppc", true) 623 .Case("ppc64", true) 624 .Default(false); 625 626 if (CPUKnown) 627 CPU = Name; 628 629 return CPUKnown; 630 } 631 632 virtual void getTargetBuiltins(const Builtin::Info *&Records, 633 unsigned &NumRecords) const { 634 Records = BuiltinInfo; 635 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 636 } 637 638 virtual bool isCLZForZeroUndef() const { return false; } 639 640 virtual void getTargetDefines(const LangOptions &Opts, 641 MacroBuilder &Builder) const; 642 643 virtual bool hasFeature(StringRef Feature) const; 644 645 virtual void getGCCRegNames(const char * const *&Names, 646 unsigned &NumNames) const; 647 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 648 unsigned &NumAliases) const; 649 virtual bool validateAsmConstraint(const char *&Name, 650 TargetInfo::ConstraintInfo &Info) const { 651 switch (*Name) { 652 default: return false; 653 case 'O': // Zero 654 break; 655 case 'b': // Base register 656 case 'f': // Floating point register 657 Info.setAllowsRegister(); 658 break; 659 // FIXME: The following are added to allow parsing. 660 // I just took a guess at what the actions should be. 661 // Also, is more specific checking needed? I.e. specific registers? 662 case 'd': // Floating point register (containing 64-bit value) 663 case 'v': // Altivec vector register 664 Info.setAllowsRegister(); 665 break; 666 case 'w': 667 switch (Name[1]) { 668 case 'd':// VSX vector register to hold vector double data 669 case 'f':// VSX vector register to hold vector float data 670 case 's':// VSX vector register to hold scalar float data 671 case 'a':// Any VSX register 672 break; 673 default: 674 return false; 675 } 676 Info.setAllowsRegister(); 677 Name++; // Skip over 'w'. 678 break; 679 case 'h': // `MQ', `CTR', or `LINK' register 680 case 'q': // `MQ' register 681 case 'c': // `CTR' register 682 case 'l': // `LINK' register 683 case 'x': // `CR' register (condition register) number 0 684 case 'y': // `CR' register (condition register) 685 case 'z': // `XER[CA]' carry bit (part of the XER register) 686 Info.setAllowsRegister(); 687 break; 688 case 'I': // Signed 16-bit constant 689 case 'J': // Unsigned 16-bit constant shifted left 16 bits 690 // (use `L' instead for SImode constants) 691 case 'K': // Unsigned 16-bit constant 692 case 'L': // Signed 16-bit constant shifted left 16 bits 693 case 'M': // Constant larger than 31 694 case 'N': // Exact power of 2 695 case 'P': // Constant whose negation is a signed 16-bit constant 696 case 'G': // Floating point constant that can be loaded into a 697 // register with one instruction per word 698 case 'H': // Integer/Floating point constant that can be loaded 699 // into a register using three instructions 700 break; 701 case 'm': // Memory operand. Note that on PowerPC targets, m can 702 // include addresses that update the base register. It 703 // is therefore only safe to use `m' in an asm statement 704 // if that asm statement accesses the operand exactly once. 705 // The asm statement must also use `%U<opno>' as a 706 // placeholder for the "update" flag in the corresponding 707 // load or store instruction. For example: 708 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 709 // is correct but: 710 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 711 // is not. Use es rather than m if you don't want the base 712 // register to be updated. 713 case 'e': 714 if (Name[1] != 's') 715 return false; 716 // es: A "stable" memory operand; that is, one which does not 717 // include any automodification of the base register. Unlike 718 // `m', this constraint can be used in asm statements that 719 // might access the operand several times, or that might not 720 // access it at all. 721 Info.setAllowsMemory(); 722 Name++; // Skip over 'e'. 723 break; 724 case 'Q': // Memory operand that is an offset from a register (it is 725 // usually better to use `m' or `es' in asm statements) 726 case 'Z': // Memory operand that is an indexed or indirect from a 727 // register (it is usually better to use `m' or `es' in 728 // asm statements) 729 Info.setAllowsMemory(); 730 Info.setAllowsRegister(); 731 break; 732 case 'R': // AIX TOC entry 733 case 'a': // Address operand that is an indexed or indirect from a 734 // register (`p' is preferable for asm statements) 735 case 'S': // Constant suitable as a 64-bit mask operand 736 case 'T': // Constant suitable as a 32-bit mask operand 737 case 'U': // System V Release 4 small data area reference 738 case 't': // AND masks that can be performed by two rldic{l, r} 739 // instructions 740 case 'W': // Vector constant that does not require memory 741 case 'j': // Vector constant that is all zeros. 742 break; 743 // End FIXME. 744 } 745 return true; 746 } 747 virtual const char *getClobbers() const { 748 return ""; 749 } 750 }; 751 752 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 753 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 754 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 755 ALL_LANGUAGES }, 756 #include "clang/Basic/BuiltinsPPC.def" 757 }; 758 759 760 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 761 /// #defines that are not tied to a specific subtarget. 762 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 763 MacroBuilder &Builder) const { 764 // Target identification. 765 Builder.defineMacro("__ppc__"); 766 Builder.defineMacro("_ARCH_PPC"); 767 Builder.defineMacro("__powerpc__"); 768 Builder.defineMacro("__POWERPC__"); 769 if (PointerWidth == 64) { 770 Builder.defineMacro("_ARCH_PPC64"); 771 Builder.defineMacro("_LP64"); 772 Builder.defineMacro("__LP64__"); 773 Builder.defineMacro("__powerpc64__"); 774 Builder.defineMacro("__ppc64__"); 775 } else { 776 Builder.defineMacro("__ppc__"); 777 } 778 779 // Target properties. 780 if (getTriple().getOS() != llvm::Triple::NetBSD) 781 Builder.defineMacro("_BIG_ENDIAN"); 782 Builder.defineMacro("__BIG_ENDIAN__"); 783 784 // Subtarget options. 785 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 786 Builder.defineMacro("__REGISTER_PREFIX__", ""); 787 788 // FIXME: Should be controlled by command line option. 789 Builder.defineMacro("__LONG_DOUBLE_128__"); 790 791 if (Opts.AltiVec) { 792 Builder.defineMacro("__VEC__", "10206"); 793 Builder.defineMacro("__ALTIVEC__"); 794 } 795 796 // CPU identification. 797 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 798 .Case("440", ArchDefineName) 799 .Case("450", ArchDefineName | ArchDefine440) 800 .Case("601", ArchDefineName) 801 .Case("602", ArchDefineName | ArchDefinePpcgr) 802 .Case("603", ArchDefineName | ArchDefinePpcgr) 803 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 804 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 805 .Case("604", ArchDefineName | ArchDefinePpcgr) 806 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 807 .Case("620", ArchDefineName | ArchDefinePpcgr) 808 .Case("7400", ArchDefineName | ArchDefinePpcgr) 809 .Case("7450", ArchDefineName | ArchDefinePpcgr) 810 .Case("750", ArchDefineName | ArchDefinePpcgr) 811 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 812 | ArchDefinePpcsq) 813 .Case("pwr6", ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 814 .Case("pwr7", ArchDefineName | ArchDefinePwr6 | ArchDefinePpcgr 815 | ArchDefinePpcsq) 816 .Default(ArchDefineNone); 817 818 if (defs & ArchDefineName) 819 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 820 if (defs & ArchDefinePpcgr) 821 Builder.defineMacro("_ARCH_PPCGR"); 822 if (defs & ArchDefinePpcsq) 823 Builder.defineMacro("_ARCH_PPCSQ"); 824 if (defs & ArchDefine440) 825 Builder.defineMacro("_ARCH_440"); 826 if (defs & ArchDefine603) 827 Builder.defineMacro("_ARCH_603"); 828 if (defs & ArchDefine604) 829 Builder.defineMacro("_ARCH_604"); 830 if (defs & (ArchDefinePwr4 | ArchDefinePwr6)) 831 Builder.defineMacro("_ARCH_PWR4"); 832 if (defs & ArchDefinePwr6) { 833 Builder.defineMacro("_ARCH_PWR5"); 834 Builder.defineMacro("_ARCH_PWR6"); 835 } 836 } 837 838 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 839 return Feature == "powerpc"; 840 } 841 842 843 const char * const PPCTargetInfo::GCCRegNames[] = { 844 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 845 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 846 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 847 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 848 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 849 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 850 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 851 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 852 "mq", "lr", "ctr", "ap", 853 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 854 "xer", 855 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 856 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 857 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 858 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 859 "vrsave", "vscr", 860 "spe_acc", "spefscr", 861 "sfp" 862 }; 863 864 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 865 unsigned &NumNames) const { 866 Names = GCCRegNames; 867 NumNames = llvm::array_lengthof(GCCRegNames); 868 } 869 870 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 871 // While some of these aliases do map to different registers 872 // they still share the same register name. 873 { { "0" }, "r0" }, 874 { { "1"}, "r1" }, 875 { { "2" }, "r2" }, 876 { { "3" }, "r3" }, 877 { { "4" }, "r4" }, 878 { { "5" }, "r5" }, 879 { { "6" }, "r6" }, 880 { { "7" }, "r7" }, 881 { { "8" }, "r8" }, 882 { { "9" }, "r9" }, 883 { { "10" }, "r10" }, 884 { { "11" }, "r11" }, 885 { { "12" }, "r12" }, 886 { { "13" }, "r13" }, 887 { { "14" }, "r14" }, 888 { { "15" }, "r15" }, 889 { { "16" }, "r16" }, 890 { { "17" }, "r17" }, 891 { { "18" }, "r18" }, 892 { { "19" }, "r19" }, 893 { { "20" }, "r20" }, 894 { { "21" }, "r21" }, 895 { { "22" }, "r22" }, 896 { { "23" }, "r23" }, 897 { { "24" }, "r24" }, 898 { { "25" }, "r25" }, 899 { { "26" }, "r26" }, 900 { { "27" }, "r27" }, 901 { { "28" }, "r28" }, 902 { { "29" }, "r29" }, 903 { { "30" }, "r30" }, 904 { { "31" }, "r31" }, 905 { { "fr0" }, "f0" }, 906 { { "fr1" }, "f1" }, 907 { { "fr2" }, "f2" }, 908 { { "fr3" }, "f3" }, 909 { { "fr4" }, "f4" }, 910 { { "fr5" }, "f5" }, 911 { { "fr6" }, "f6" }, 912 { { "fr7" }, "f7" }, 913 { { "fr8" }, "f8" }, 914 { { "fr9" }, "f9" }, 915 { { "fr10" }, "f10" }, 916 { { "fr11" }, "f11" }, 917 { { "fr12" }, "f12" }, 918 { { "fr13" }, "f13" }, 919 { { "fr14" }, "f14" }, 920 { { "fr15" }, "f15" }, 921 { { "fr16" }, "f16" }, 922 { { "fr17" }, "f17" }, 923 { { "fr18" }, "f18" }, 924 { { "fr19" }, "f19" }, 925 { { "fr20" }, "f20" }, 926 { { "fr21" }, "f21" }, 927 { { "fr22" }, "f22" }, 928 { { "fr23" }, "f23" }, 929 { { "fr24" }, "f24" }, 930 { { "fr25" }, "f25" }, 931 { { "fr26" }, "f26" }, 932 { { "fr27" }, "f27" }, 933 { { "fr28" }, "f28" }, 934 { { "fr29" }, "f29" }, 935 { { "fr30" }, "f30" }, 936 { { "fr31" }, "f31" }, 937 { { "cc" }, "cr0" }, 938 }; 939 940 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 941 unsigned &NumAliases) const { 942 Aliases = GCCRegAliases; 943 NumAliases = llvm::array_lengthof(GCCRegAliases); 944 } 945 } // end anonymous namespace. 946 947 namespace { 948 class PPC32TargetInfo : public PPCTargetInfo { 949 public: 950 PPC32TargetInfo(const std::string &triple) : PPCTargetInfo(triple) { 951 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 952 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"; 953 954 switch (getTriple().getOS()) { 955 case llvm::Triple::Linux: 956 case llvm::Triple::FreeBSD: 957 case llvm::Triple::NetBSD: 958 SizeType = UnsignedInt; 959 PtrDiffType = SignedInt; 960 IntPtrType = SignedInt; 961 break; 962 default: 963 break; 964 } 965 966 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 967 LongDoubleWidth = LongDoubleAlign = 64; 968 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 969 } 970 } 971 972 virtual BuiltinVaListKind getBuiltinVaListKind() const { 973 // This is the ELF definition, and is overridden by the Darwin sub-target 974 return TargetInfo::PowerABIBuiltinVaList; 975 } 976 }; 977 } // end anonymous namespace. 978 979 namespace { 980 class PPC64TargetInfo : public PPCTargetInfo { 981 public: 982 PPC64TargetInfo(const std::string& triple) : PPCTargetInfo(triple) { 983 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 984 IntMaxType = SignedLong; 985 UIntMaxType = UnsignedLong; 986 Int64Type = SignedLong; 987 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 988 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"; 989 990 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 991 LongDoubleWidth = LongDoubleAlign = 64; 992 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 993 } 994 } 995 virtual BuiltinVaListKind getBuiltinVaListKind() const { 996 return TargetInfo::CharPtrBuiltinVaList; 997 } 998 }; 999 } // end anonymous namespace. 1000 1001 1002 namespace { 1003 class DarwinPPC32TargetInfo : 1004 public DarwinTargetInfo<PPC32TargetInfo> { 1005 public: 1006 DarwinPPC32TargetInfo(const std::string& triple) 1007 : DarwinTargetInfo<PPC32TargetInfo>(triple) { 1008 HasAlignMac68kSupport = true; 1009 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1010 LongLongAlign = 32; 1011 SuitableAlign = 128; 1012 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1013 "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32"; 1014 } 1015 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1016 return TargetInfo::CharPtrBuiltinVaList; 1017 } 1018 }; 1019 1020 class DarwinPPC64TargetInfo : 1021 public DarwinTargetInfo<PPC64TargetInfo> { 1022 public: 1023 DarwinPPC64TargetInfo(const std::string& triple) 1024 : DarwinTargetInfo<PPC64TargetInfo>(triple) { 1025 HasAlignMac68kSupport = true; 1026 SuitableAlign = 128; 1027 } 1028 }; 1029 } // end anonymous namespace. 1030 1031 namespace { 1032 static const unsigned NVPTXAddrSpaceMap[] = { 1033 1, // opencl_global 1034 3, // opencl_local 1035 4, // opencl_constant 1036 1, // cuda_device 1037 4, // cuda_constant 1038 3, // cuda_shared 1039 }; 1040 class NVPTXTargetInfo : public TargetInfo { 1041 static const char * const GCCRegNames[]; 1042 static const Builtin::Info BuiltinInfo[]; 1043 std::vector<llvm::StringRef> AvailableFeatures; 1044 public: 1045 NVPTXTargetInfo(const std::string& triple) : TargetInfo(triple) { 1046 BigEndian = false; 1047 TLSSupported = false; 1048 LongWidth = LongAlign = 64; 1049 AddrSpaceMap = &NVPTXAddrSpaceMap; 1050 // Define available target features 1051 // These must be defined in sorted order! 1052 NoAsmVariants = true; 1053 } 1054 virtual void getTargetDefines(const LangOptions &Opts, 1055 MacroBuilder &Builder) const { 1056 Builder.defineMacro("__PTX__"); 1057 Builder.defineMacro("__NVPTX__"); 1058 } 1059 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1060 unsigned &NumRecords) const { 1061 Records = BuiltinInfo; 1062 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1063 } 1064 virtual bool hasFeature(StringRef Feature) const { 1065 return Feature == "ptx" || Feature == "nvptx"; 1066 } 1067 1068 virtual void getGCCRegNames(const char * const *&Names, 1069 unsigned &NumNames) const; 1070 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1071 unsigned &NumAliases) const { 1072 // No aliases. 1073 Aliases = 0; 1074 NumAliases = 0; 1075 } 1076 virtual bool validateAsmConstraint(const char *&Name, 1077 TargetInfo::ConstraintInfo &info) const { 1078 // FIXME: implement 1079 return true; 1080 } 1081 virtual const char *getClobbers() const { 1082 // FIXME: Is this really right? 1083 return ""; 1084 } 1085 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1086 // FIXME: implement 1087 return TargetInfo::CharPtrBuiltinVaList; 1088 } 1089 virtual bool setCPU(const std::string &Name) { 1090 return Name == "sm_10" || Name == "sm_13" || Name == "sm_20"; 1091 } 1092 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 1093 StringRef Name, 1094 bool Enabled) const; 1095 }; 1096 1097 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1098 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1099 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1100 ALL_LANGUAGES }, 1101 #include "clang/Basic/BuiltinsNVPTX.def" 1102 }; 1103 1104 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1105 "r0" 1106 }; 1107 1108 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1109 unsigned &NumNames) const { 1110 Names = GCCRegNames; 1111 NumNames = llvm::array_lengthof(GCCRegNames); 1112 } 1113 1114 bool NVPTXTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1115 StringRef Name, 1116 bool Enabled) const { 1117 if(std::binary_search(AvailableFeatures.begin(), AvailableFeatures.end(), 1118 Name)) { 1119 Features[Name] = Enabled; 1120 return true; 1121 } else { 1122 return false; 1123 } 1124 } 1125 1126 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1127 public: 1128 NVPTX32TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) { 1129 PointerWidth = PointerAlign = 32; 1130 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt; 1131 DescriptionString 1132 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 1133 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-" 1134 "n16:32:64"; 1135 } 1136 }; 1137 1138 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1139 public: 1140 NVPTX64TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) { 1141 PointerWidth = PointerAlign = 64; 1142 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong; 1143 DescriptionString 1144 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 1145 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-" 1146 "n16:32:64"; 1147 } 1148 }; 1149 } 1150 1151 namespace { 1152 // MBlaze abstract base class 1153 class MBlazeTargetInfo : public TargetInfo { 1154 static const char * const GCCRegNames[]; 1155 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 1156 1157 public: 1158 MBlazeTargetInfo(const std::string& triple) : TargetInfo(triple) { 1159 DescriptionString = "E-p:32:32:32-i8:8:8-i16:16:16"; 1160 } 1161 1162 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1163 unsigned &NumRecords) const { 1164 // FIXME: Implement. 1165 Records = 0; 1166 NumRecords = 0; 1167 } 1168 1169 virtual void getTargetDefines(const LangOptions &Opts, 1170 MacroBuilder &Builder) const; 1171 1172 virtual bool hasFeature(StringRef Feature) const { 1173 return Feature == "mblaze"; 1174 } 1175 1176 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1177 return TargetInfo::CharPtrBuiltinVaList; 1178 } 1179 virtual const char *getTargetPrefix() const { 1180 return "mblaze"; 1181 } 1182 virtual void getGCCRegNames(const char * const *&Names, 1183 unsigned &NumNames) const; 1184 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1185 unsigned &NumAliases) const; 1186 virtual bool validateAsmConstraint(const char *&Name, 1187 TargetInfo::ConstraintInfo &Info) const { 1188 switch (*Name) { 1189 default: return false; 1190 case 'O': // Zero 1191 return true; 1192 case 'b': // Base register 1193 case 'f': // Floating point register 1194 Info.setAllowsRegister(); 1195 return true; 1196 } 1197 } 1198 virtual const char *getClobbers() const { 1199 return ""; 1200 } 1201 }; 1202 1203 /// MBlazeTargetInfo::getTargetDefines - Return a set of the MBlaze-specific 1204 /// #defines that are not tied to a specific subtarget. 1205 void MBlazeTargetInfo::getTargetDefines(const LangOptions &Opts, 1206 MacroBuilder &Builder) const { 1207 // Target identification. 1208 Builder.defineMacro("__microblaze__"); 1209 Builder.defineMacro("_ARCH_MICROBLAZE"); 1210 Builder.defineMacro("__MICROBLAZE__"); 1211 1212 // Target properties. 1213 Builder.defineMacro("_BIG_ENDIAN"); 1214 Builder.defineMacro("__BIG_ENDIAN__"); 1215 1216 // Subtarget options. 1217 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1218 } 1219 1220 1221 const char * const MBlazeTargetInfo::GCCRegNames[] = { 1222 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1223 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1224 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1225 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1226 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 1227 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 1228 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 1229 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 1230 "hi", "lo", "accum","rmsr", "$fcc1","$fcc2","$fcc3","$fcc4", 1231 "$fcc5","$fcc6","$fcc7","$ap", "$rap", "$frp" 1232 }; 1233 1234 void MBlazeTargetInfo::getGCCRegNames(const char * const *&Names, 1235 unsigned &NumNames) const { 1236 Names = GCCRegNames; 1237 NumNames = llvm::array_lengthof(GCCRegNames); 1238 } 1239 1240 const TargetInfo::GCCRegAlias MBlazeTargetInfo::GCCRegAliases[] = { 1241 { {"f0"}, "r0" }, 1242 { {"f1"}, "r1" }, 1243 { {"f2"}, "r2" }, 1244 { {"f3"}, "r3" }, 1245 { {"f4"}, "r4" }, 1246 { {"f5"}, "r5" }, 1247 { {"f6"}, "r6" }, 1248 { {"f7"}, "r7" }, 1249 { {"f8"}, "r8" }, 1250 { {"f9"}, "r9" }, 1251 { {"f10"}, "r10" }, 1252 { {"f11"}, "r11" }, 1253 { {"f12"}, "r12" }, 1254 { {"f13"}, "r13" }, 1255 { {"f14"}, "r14" }, 1256 { {"f15"}, "r15" }, 1257 { {"f16"}, "r16" }, 1258 { {"f17"}, "r17" }, 1259 { {"f18"}, "r18" }, 1260 { {"f19"}, "r19" }, 1261 { {"f20"}, "r20" }, 1262 { {"f21"}, "r21" }, 1263 { {"f22"}, "r22" }, 1264 { {"f23"}, "r23" }, 1265 { {"f24"}, "r24" }, 1266 { {"f25"}, "r25" }, 1267 { {"f26"}, "r26" }, 1268 { {"f27"}, "r27" }, 1269 { {"f28"}, "r28" }, 1270 { {"f29"}, "r29" }, 1271 { {"f30"}, "r30" }, 1272 { {"f31"}, "r31" }, 1273 }; 1274 1275 void MBlazeTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1276 unsigned &NumAliases) const { 1277 Aliases = GCCRegAliases; 1278 NumAliases = llvm::array_lengthof(GCCRegAliases); 1279 } 1280 } // end anonymous namespace. 1281 1282 namespace { 1283 // Namespace for x86 abstract base class 1284 const Builtin::Info BuiltinInfo[] = { 1285 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1286 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1287 ALL_LANGUAGES }, 1288 #include "clang/Basic/BuiltinsX86.def" 1289 }; 1290 1291 static const char* const GCCRegNames[] = { 1292 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1293 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1294 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1295 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1296 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1297 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1298 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1299 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1300 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1301 }; 1302 1303 const TargetInfo::AddlRegName AddlRegNames[] = { 1304 { { "al", "ah", "eax", "rax" }, 0 }, 1305 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1306 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1307 { { "dl", "dh", "edx", "rdx" }, 1 }, 1308 { { "esi", "rsi" }, 4 }, 1309 { { "edi", "rdi" }, 5 }, 1310 { { "esp", "rsp" }, 7 }, 1311 { { "ebp", "rbp" }, 6 }, 1312 }; 1313 1314 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1315 // most of the implementation can be shared. 1316 class X86TargetInfo : public TargetInfo { 1317 enum X86SSEEnum { 1318 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2 1319 } SSELevel; 1320 enum MMX3DNowEnum { 1321 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1322 } MMX3DNowLevel; 1323 1324 bool HasAES; 1325 bool HasPCLMUL; 1326 bool HasLZCNT; 1327 bool HasRDRND; 1328 bool HasBMI; 1329 bool HasBMI2; 1330 bool HasPOPCNT; 1331 bool HasSSE4a; 1332 bool HasFMA4; 1333 bool HasFMA; 1334 bool HasXOP; 1335 1336 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1337 /// 1338 /// Each enumeration represents a particular CPU supported by Clang. These 1339 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1340 enum CPUKind { 1341 CK_Generic, 1342 1343 /// \name i386 1344 /// i386-generation processors. 1345 //@{ 1346 CK_i386, 1347 //@} 1348 1349 /// \name i486 1350 /// i486-generation processors. 1351 //@{ 1352 CK_i486, 1353 CK_WinChipC6, 1354 CK_WinChip2, 1355 CK_C3, 1356 //@} 1357 1358 /// \name i586 1359 /// i586-generation processors, P5 microarchitecture based. 1360 //@{ 1361 CK_i586, 1362 CK_Pentium, 1363 CK_PentiumMMX, 1364 //@} 1365 1366 /// \name i686 1367 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1368 //@{ 1369 CK_i686, 1370 CK_PentiumPro, 1371 CK_Pentium2, 1372 CK_Pentium3, 1373 CK_Pentium3M, 1374 CK_PentiumM, 1375 CK_C3_2, 1376 1377 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1378 /// Clang however has some logic to suport this. 1379 // FIXME: Warn, deprecate, and potentially remove this. 1380 CK_Yonah, 1381 //@} 1382 1383 /// \name Netburst 1384 /// Netburst microarchitecture based processors. 1385 //@{ 1386 CK_Pentium4, 1387 CK_Pentium4M, 1388 CK_Prescott, 1389 CK_Nocona, 1390 //@} 1391 1392 /// \name Core 1393 /// Core microarchitecture based processors. 1394 //@{ 1395 CK_Core2, 1396 1397 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1398 /// codename which GCC no longer accepts as an option to -march, but Clang 1399 /// has some logic for recognizing it. 1400 // FIXME: Warn, deprecate, and potentially remove this. 1401 CK_Penryn, 1402 //@} 1403 1404 /// \name Atom 1405 /// Atom processors 1406 //@{ 1407 CK_Atom, 1408 //@} 1409 1410 /// \name Nehalem 1411 /// Nehalem microarchitecture based processors. 1412 //@{ 1413 CK_Corei7, 1414 CK_Corei7AVX, 1415 CK_CoreAVXi, 1416 CK_CoreAVX2, 1417 //@} 1418 1419 /// \name K6 1420 /// K6 architecture processors. 1421 //@{ 1422 CK_K6, 1423 CK_K6_2, 1424 CK_K6_3, 1425 //@} 1426 1427 /// \name K7 1428 /// K7 architecture processors. 1429 //@{ 1430 CK_Athlon, 1431 CK_AthlonThunderbird, 1432 CK_Athlon4, 1433 CK_AthlonXP, 1434 CK_AthlonMP, 1435 //@} 1436 1437 /// \name K8 1438 /// K8 architecture processors. 1439 //@{ 1440 CK_Athlon64, 1441 CK_Athlon64SSE3, 1442 CK_AthlonFX, 1443 CK_K8, 1444 CK_K8SSE3, 1445 CK_Opteron, 1446 CK_OpteronSSE3, 1447 CK_AMDFAM10, 1448 //@} 1449 1450 /// \name Bobcat 1451 /// Bobcat architecture processors. 1452 //@{ 1453 CK_BTVER1, 1454 //@} 1455 1456 /// \name Bulldozer 1457 /// Bulldozer architecture processors. 1458 //@{ 1459 CK_BDVER1, 1460 CK_BDVER2, 1461 //@} 1462 1463 /// This specification is deprecated and will be removed in the future. 1464 /// Users should prefer \see CK_K8. 1465 // FIXME: Warn on this when the CPU is set to it. 1466 CK_x86_64, 1467 //@} 1468 1469 /// \name Geode 1470 /// Geode processors. 1471 //@{ 1472 CK_Geode 1473 //@} 1474 } CPU; 1475 1476 public: 1477 X86TargetInfo(const std::string& triple) 1478 : TargetInfo(triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1479 HasAES(false), HasPCLMUL(false), HasLZCNT(false), HasRDRND(false), 1480 HasBMI(false), HasBMI2(false), HasPOPCNT(false), HasSSE4a(false), 1481 HasFMA4(false), HasFMA(false), HasXOP(false), CPU(CK_Generic) { 1482 BigEndian = false; 1483 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1484 } 1485 virtual unsigned getFloatEvalMethod() const { 1486 // X87 evaluates with 80 bits "long double" precision. 1487 return SSELevel == NoSSE ? 2 : 0; 1488 } 1489 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1490 unsigned &NumRecords) const { 1491 Records = BuiltinInfo; 1492 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1493 } 1494 virtual void getGCCRegNames(const char * const *&Names, 1495 unsigned &NumNames) const { 1496 Names = GCCRegNames; 1497 NumNames = llvm::array_lengthof(GCCRegNames); 1498 } 1499 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1500 unsigned &NumAliases) const { 1501 Aliases = 0; 1502 NumAliases = 0; 1503 } 1504 virtual void getGCCAddlRegNames(const AddlRegName *&Names, 1505 unsigned &NumNames) const { 1506 Names = AddlRegNames; 1507 NumNames = llvm::array_lengthof(AddlRegNames); 1508 } 1509 virtual bool validateAsmConstraint(const char *&Name, 1510 TargetInfo::ConstraintInfo &info) const; 1511 virtual std::string convertConstraint(const char *&Constraint) const; 1512 virtual const char *getClobbers() const { 1513 return "~{dirflag},~{fpsr},~{flags}"; 1514 } 1515 virtual void getTargetDefines(const LangOptions &Opts, 1516 MacroBuilder &Builder) const; 1517 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 1518 StringRef Name, 1519 bool Enabled) const; 1520 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 1521 virtual bool hasFeature(StringRef Feature) const; 1522 virtual void HandleTargetFeatures(std::vector<std::string> &Features); 1523 virtual const char* getABI() const { 1524 if (PointerWidth == 64 && SSELevel >= AVX) 1525 return "avx"; 1526 else if (PointerWidth == 32 && MMX3DNowLevel == NoMMX3DNow) 1527 return "no-mmx"; 1528 return ""; 1529 } 1530 virtual bool setCPU(const std::string &Name) { 1531 CPU = llvm::StringSwitch<CPUKind>(Name) 1532 .Case("i386", CK_i386) 1533 .Case("i486", CK_i486) 1534 .Case("winchip-c6", CK_WinChipC6) 1535 .Case("winchip2", CK_WinChip2) 1536 .Case("c3", CK_C3) 1537 .Case("i586", CK_i586) 1538 .Case("pentium", CK_Pentium) 1539 .Case("pentium-mmx", CK_PentiumMMX) 1540 .Case("i686", CK_i686) 1541 .Case("pentiumpro", CK_PentiumPro) 1542 .Case("pentium2", CK_Pentium2) 1543 .Case("pentium3", CK_Pentium3) 1544 .Case("pentium3m", CK_Pentium3M) 1545 .Case("pentium-m", CK_PentiumM) 1546 .Case("c3-2", CK_C3_2) 1547 .Case("yonah", CK_Yonah) 1548 .Case("pentium4", CK_Pentium4) 1549 .Case("pentium4m", CK_Pentium4M) 1550 .Case("prescott", CK_Prescott) 1551 .Case("nocona", CK_Nocona) 1552 .Case("core2", CK_Core2) 1553 .Case("penryn", CK_Penryn) 1554 .Case("atom", CK_Atom) 1555 .Case("corei7", CK_Corei7) 1556 .Case("corei7-avx", CK_Corei7AVX) 1557 .Case("core-avx-i", CK_CoreAVXi) 1558 .Case("core-avx2", CK_CoreAVX2) 1559 .Case("k6", CK_K6) 1560 .Case("k6-2", CK_K6_2) 1561 .Case("k6-3", CK_K6_3) 1562 .Case("athlon", CK_Athlon) 1563 .Case("athlon-tbird", CK_AthlonThunderbird) 1564 .Case("athlon-4", CK_Athlon4) 1565 .Case("athlon-xp", CK_AthlonXP) 1566 .Case("athlon-mp", CK_AthlonMP) 1567 .Case("athlon64", CK_Athlon64) 1568 .Case("athlon64-sse3", CK_Athlon64SSE3) 1569 .Case("athlon-fx", CK_AthlonFX) 1570 .Case("k8", CK_K8) 1571 .Case("k8-sse3", CK_K8SSE3) 1572 .Case("opteron", CK_Opteron) 1573 .Case("opteron-sse3", CK_OpteronSSE3) 1574 .Case("amdfam10", CK_AMDFAM10) 1575 .Case("btver1", CK_BTVER1) 1576 .Case("bdver1", CK_BDVER1) 1577 .Case("bdver2", CK_BDVER2) 1578 .Case("x86-64", CK_x86_64) 1579 .Case("geode", CK_Geode) 1580 .Default(CK_Generic); 1581 1582 // Perform any per-CPU checks necessary to determine if this CPU is 1583 // acceptable. 1584 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1585 // invalid without explaining *why*. 1586 switch (CPU) { 1587 case CK_Generic: 1588 // No processor selected! 1589 return false; 1590 1591 case CK_i386: 1592 case CK_i486: 1593 case CK_WinChipC6: 1594 case CK_WinChip2: 1595 case CK_C3: 1596 case CK_i586: 1597 case CK_Pentium: 1598 case CK_PentiumMMX: 1599 case CK_i686: 1600 case CK_PentiumPro: 1601 case CK_Pentium2: 1602 case CK_Pentium3: 1603 case CK_Pentium3M: 1604 case CK_PentiumM: 1605 case CK_Yonah: 1606 case CK_C3_2: 1607 case CK_Pentium4: 1608 case CK_Pentium4M: 1609 case CK_Prescott: 1610 case CK_K6: 1611 case CK_K6_2: 1612 case CK_K6_3: 1613 case CK_Athlon: 1614 case CK_AthlonThunderbird: 1615 case CK_Athlon4: 1616 case CK_AthlonXP: 1617 case CK_AthlonMP: 1618 case CK_Geode: 1619 // Only accept certain architectures when compiling in 32-bit mode. 1620 if (PointerWidth != 32) 1621 return false; 1622 1623 // Fallthrough 1624 case CK_Nocona: 1625 case CK_Core2: 1626 case CK_Penryn: 1627 case CK_Atom: 1628 case CK_Corei7: 1629 case CK_Corei7AVX: 1630 case CK_CoreAVXi: 1631 case CK_CoreAVX2: 1632 case CK_Athlon64: 1633 case CK_Athlon64SSE3: 1634 case CK_AthlonFX: 1635 case CK_K8: 1636 case CK_K8SSE3: 1637 case CK_Opteron: 1638 case CK_OpteronSSE3: 1639 case CK_AMDFAM10: 1640 case CK_BTVER1: 1641 case CK_BDVER1: 1642 case CK_BDVER2: 1643 case CK_x86_64: 1644 return true; 1645 } 1646 llvm_unreachable("Unhandled CPU kind"); 1647 } 1648 }; 1649 1650 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1651 // FIXME: This should not be here. 1652 Features["3dnow"] = false; 1653 Features["3dnowa"] = false; 1654 Features["mmx"] = false; 1655 Features["sse"] = false; 1656 Features["sse2"] = false; 1657 Features["sse3"] = false; 1658 Features["ssse3"] = false; 1659 Features["sse41"] = false; 1660 Features["sse42"] = false; 1661 Features["sse4a"] = false; 1662 Features["aes"] = false; 1663 Features["pclmul"] = false; 1664 Features["avx"] = false; 1665 Features["avx2"] = false; 1666 Features["lzcnt"] = false; 1667 Features["rdrand"] = false; 1668 Features["bmi"] = false; 1669 Features["bmi2"] = false; 1670 Features["popcnt"] = false; 1671 Features["fma4"] = false; 1672 Features["fma"] = false; 1673 Features["xop"] = false; 1674 1675 // FIXME: This *really* should not be here. 1676 1677 // X86_64 always has SSE2. 1678 if (PointerWidth == 64) 1679 Features["sse2"] = Features["sse"] = Features["mmx"] = true; 1680 1681 switch (CPU) { 1682 case CK_Generic: 1683 case CK_i386: 1684 case CK_i486: 1685 case CK_i586: 1686 case CK_Pentium: 1687 case CK_i686: 1688 case CK_PentiumPro: 1689 break; 1690 case CK_PentiumMMX: 1691 case CK_Pentium2: 1692 setFeatureEnabled(Features, "mmx", true); 1693 break; 1694 case CK_Pentium3: 1695 case CK_Pentium3M: 1696 setFeatureEnabled(Features, "mmx", true); 1697 setFeatureEnabled(Features, "sse", true); 1698 break; 1699 case CK_PentiumM: 1700 case CK_Pentium4: 1701 case CK_Pentium4M: 1702 case CK_x86_64: 1703 setFeatureEnabled(Features, "mmx", true); 1704 setFeatureEnabled(Features, "sse2", true); 1705 break; 1706 case CK_Yonah: 1707 case CK_Prescott: 1708 case CK_Nocona: 1709 setFeatureEnabled(Features, "mmx", true); 1710 setFeatureEnabled(Features, "sse3", true); 1711 break; 1712 case CK_Core2: 1713 setFeatureEnabled(Features, "mmx", true); 1714 setFeatureEnabled(Features, "ssse3", true); 1715 break; 1716 case CK_Penryn: 1717 setFeatureEnabled(Features, "mmx", true); 1718 setFeatureEnabled(Features, "sse4.1", true); 1719 break; 1720 case CK_Atom: 1721 setFeatureEnabled(Features, "mmx", true); 1722 setFeatureEnabled(Features, "ssse3", true); 1723 break; 1724 case CK_Corei7: 1725 setFeatureEnabled(Features, "mmx", true); 1726 setFeatureEnabled(Features, "sse4", true); 1727 break; 1728 case CK_Corei7AVX: 1729 setFeatureEnabled(Features, "mmx", true); 1730 setFeatureEnabled(Features, "avx", true); 1731 setFeatureEnabled(Features, "aes", true); 1732 setFeatureEnabled(Features, "pclmul", true); 1733 break; 1734 case CK_CoreAVXi: 1735 setFeatureEnabled(Features, "mmx", true); 1736 setFeatureEnabled(Features, "avx", true); 1737 setFeatureEnabled(Features, "aes", true); 1738 setFeatureEnabled(Features, "pclmul", true); 1739 setFeatureEnabled(Features, "rdrnd", true); 1740 break; 1741 case CK_CoreAVX2: 1742 setFeatureEnabled(Features, "mmx", true); 1743 setFeatureEnabled(Features, "avx2", true); 1744 setFeatureEnabled(Features, "aes", true); 1745 setFeatureEnabled(Features, "pclmul", true); 1746 setFeatureEnabled(Features, "lzcnt", true); 1747 setFeatureEnabled(Features, "rdrnd", true); 1748 setFeatureEnabled(Features, "bmi", true); 1749 setFeatureEnabled(Features, "bmi2", true); 1750 setFeatureEnabled(Features, "fma", true); 1751 break; 1752 case CK_K6: 1753 case CK_WinChipC6: 1754 setFeatureEnabled(Features, "mmx", true); 1755 break; 1756 case CK_K6_2: 1757 case CK_K6_3: 1758 case CK_WinChip2: 1759 case CK_C3: 1760 setFeatureEnabled(Features, "3dnow", true); 1761 break; 1762 case CK_Athlon: 1763 case CK_AthlonThunderbird: 1764 case CK_Geode: 1765 setFeatureEnabled(Features, "3dnowa", true); 1766 break; 1767 case CK_Athlon4: 1768 case CK_AthlonXP: 1769 case CK_AthlonMP: 1770 setFeatureEnabled(Features, "sse", true); 1771 setFeatureEnabled(Features, "3dnowa", true); 1772 break; 1773 case CK_K8: 1774 case CK_Opteron: 1775 case CK_Athlon64: 1776 case CK_AthlonFX: 1777 setFeatureEnabled(Features, "sse2", true); 1778 setFeatureEnabled(Features, "3dnowa", true); 1779 break; 1780 case CK_K8SSE3: 1781 case CK_OpteronSSE3: 1782 case CK_Athlon64SSE3: 1783 setFeatureEnabled(Features, "sse3", true); 1784 setFeatureEnabled(Features, "3dnowa", true); 1785 break; 1786 case CK_AMDFAM10: 1787 setFeatureEnabled(Features, "sse3", true); 1788 setFeatureEnabled(Features, "sse4a", true); 1789 setFeatureEnabled(Features, "3dnowa", true); 1790 break; 1791 case CK_BTVER1: 1792 setFeatureEnabled(Features, "ssse3", true); 1793 setFeatureEnabled(Features, "sse4a", true); 1794 break; 1795 case CK_BDVER1: 1796 case CK_BDVER2: 1797 setFeatureEnabled(Features, "avx", true); 1798 setFeatureEnabled(Features, "xop", true); 1799 setFeatureEnabled(Features, "aes", true); 1800 setFeatureEnabled(Features, "pclmul", true); 1801 break; 1802 case CK_C3_2: 1803 setFeatureEnabled(Features, "mmx", true); 1804 setFeatureEnabled(Features, "sse", true); 1805 break; 1806 } 1807 } 1808 1809 bool X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1810 StringRef Name, 1811 bool Enabled) const { 1812 // FIXME: This *really* should not be here. We need some way of translating 1813 // options into llvm subtarget features. 1814 if (!Features.count(Name) && 1815 (Name != "sse4" && Name != "sse4.2" && Name != "sse4.1" && 1816 Name != "rdrnd")) 1817 return false; 1818 1819 // FIXME: this should probably use a switch with fall through. 1820 1821 if (Enabled) { 1822 if (Name == "mmx") 1823 Features["mmx"] = true; 1824 else if (Name == "sse") 1825 Features["mmx"] = Features["sse"] = true; 1826 else if (Name == "sse2") 1827 Features["mmx"] = Features["sse"] = Features["sse2"] = true; 1828 else if (Name == "sse3") 1829 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1830 true; 1831 else if (Name == "ssse3") 1832 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1833 Features["ssse3"] = true; 1834 else if (Name == "sse4" || Name == "sse4.2") 1835 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1836 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1837 Features["popcnt"] = true; 1838 else if (Name == "sse4.1") 1839 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1840 Features["ssse3"] = Features["sse41"] = true; 1841 else if (Name == "3dnow") 1842 Features["mmx"] = Features["3dnow"] = true; 1843 else if (Name == "3dnowa") 1844 Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = true; 1845 else if (Name == "aes") 1846 Features["sse"] = Features["sse2"] = Features["aes"] = true; 1847 else if (Name == "pclmul") 1848 Features["sse"] = Features["sse2"] = Features["pclmul"] = true; 1849 else if (Name == "avx") 1850 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1851 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1852 Features["popcnt"] = Features["avx"] = true; 1853 else if (Name == "avx2") 1854 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1855 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1856 Features["popcnt"] = Features["avx"] = Features["avx2"] = true; 1857 else if (Name == "fma") 1858 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1859 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1860 Features["popcnt"] = Features["avx"] = Features["fma"] = true; 1861 else if (Name == "fma4") 1862 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1863 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1864 Features["popcnt"] = Features["avx"] = Features["sse4a"] = 1865 Features["fma4"] = true; 1866 else if (Name == "xop") 1867 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1868 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1869 Features["popcnt"] = Features["avx"] = Features["sse4a"] = 1870 Features["fma4"] = Features["xop"] = true; 1871 else if (Name == "sse4a") 1872 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1873 Features["sse4a"] = true; 1874 else if (Name == "lzcnt") 1875 Features["lzcnt"] = true; 1876 else if (Name == "rdrnd") 1877 Features["rdrand"] = true; 1878 else if (Name == "bmi") 1879 Features["bmi"] = true; 1880 else if (Name == "bmi2") 1881 Features["bmi2"] = true; 1882 else if (Name == "popcnt") 1883 Features["popcnt"] = true; 1884 } else { 1885 if (Name == "mmx") 1886 Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = false; 1887 else if (Name == "sse") 1888 Features["sse"] = Features["sse2"] = Features["sse3"] = 1889 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1890 Features["sse4a"] = Features["avx"] = Features["avx2"] = 1891 Features["fma"] = Features["fma4"] = Features["aes"] = 1892 Features["pclmul"] = Features["xop"] = false; 1893 else if (Name == "sse2") 1894 Features["sse2"] = Features["sse3"] = Features["ssse3"] = 1895 Features["sse41"] = Features["sse42"] = Features["sse4a"] = 1896 Features["avx"] = Features["avx2"] = Features["fma"] = 1897 Features["fma4"] = Features["aes"] = Features["pclmul"] = 1898 Features["xop"] = false; 1899 else if (Name == "sse3") 1900 Features["sse3"] = Features["ssse3"] = Features["sse41"] = 1901 Features["sse42"] = Features["sse4a"] = Features["avx"] = 1902 Features["avx2"] = Features["fma"] = Features["fma4"] = 1903 Features["xop"] = false; 1904 else if (Name == "ssse3") 1905 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1906 Features["avx"] = Features["avx2"] = Features["fma"] = false; 1907 else if (Name == "sse4" || Name == "sse4.1") 1908 Features["sse41"] = Features["sse42"] = Features["avx"] = 1909 Features["avx2"] = Features["fma"] = false; 1910 else if (Name == "sse4.2") 1911 Features["sse42"] = Features["avx"] = Features["avx2"] = 1912 Features["fma"] = false; 1913 else if (Name == "3dnow") 1914 Features["3dnow"] = Features["3dnowa"] = false; 1915 else if (Name == "3dnowa") 1916 Features["3dnowa"] = false; 1917 else if (Name == "aes") 1918 Features["aes"] = false; 1919 else if (Name == "pclmul") 1920 Features["pclmul"] = false; 1921 else if (Name == "avx") 1922 Features["avx"] = Features["avx2"] = Features["fma"] = 1923 Features["fma4"] = Features["xop"] = false; 1924 else if (Name == "avx2") 1925 Features["avx2"] = false; 1926 else if (Name == "fma") 1927 Features["fma"] = false; 1928 else if (Name == "sse4a") 1929 Features["sse4a"] = Features["fma4"] = Features["xop"] = false; 1930 else if (Name == "lzcnt") 1931 Features["lzcnt"] = false; 1932 else if (Name == "rdrnd") 1933 Features["rdrand"] = false; 1934 else if (Name == "bmi") 1935 Features["bmi"] = false; 1936 else if (Name == "bmi2") 1937 Features["bmi2"] = false; 1938 else if (Name == "popcnt") 1939 Features["popcnt"] = false; 1940 else if (Name == "fma4") 1941 Features["fma4"] = Features["xop"] = false; 1942 else if (Name == "xop") 1943 Features["xop"] = false; 1944 } 1945 1946 return true; 1947 } 1948 1949 /// HandleTargetOptions - Perform initialization based on the user 1950 /// configured set of features. 1951 void X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features) { 1952 // Remember the maximum enabled sselevel. 1953 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 1954 // Ignore disabled features. 1955 if (Features[i][0] == '-') 1956 continue; 1957 1958 StringRef Feature = StringRef(Features[i]).substr(1); 1959 1960 if (Feature == "aes") { 1961 HasAES = true; 1962 continue; 1963 } 1964 1965 if (Feature == "pclmul") { 1966 HasPCLMUL = true; 1967 continue; 1968 } 1969 1970 if (Feature == "lzcnt") { 1971 HasLZCNT = true; 1972 continue; 1973 } 1974 1975 if (Feature == "rdrand") { 1976 HasRDRND = true; 1977 continue; 1978 } 1979 1980 if (Feature == "bmi") { 1981 HasBMI = true; 1982 continue; 1983 } 1984 1985 if (Feature == "bmi2") { 1986 HasBMI2 = true; 1987 continue; 1988 } 1989 1990 if (Feature == "popcnt") { 1991 HasPOPCNT = true; 1992 continue; 1993 } 1994 1995 if (Feature == "sse4a") { 1996 HasSSE4a = true; 1997 continue; 1998 } 1999 2000 if (Feature == "fma4") { 2001 HasFMA4 = true; 2002 continue; 2003 } 2004 2005 if (Feature == "fma") { 2006 HasFMA = true; 2007 continue; 2008 } 2009 2010 if (Feature == "xop") { 2011 HasXOP = true; 2012 continue; 2013 } 2014 2015 assert(Features[i][0] == '+' && "Invalid target feature!"); 2016 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2017 .Case("avx2", AVX2) 2018 .Case("avx", AVX) 2019 .Case("sse42", SSE42) 2020 .Case("sse41", SSE41) 2021 .Case("ssse3", SSSE3) 2022 .Case("sse3", SSE3) 2023 .Case("sse2", SSE2) 2024 .Case("sse", SSE1) 2025 .Default(NoSSE); 2026 SSELevel = std::max(SSELevel, Level); 2027 2028 MMX3DNowEnum ThreeDNowLevel = 2029 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2030 .Case("3dnowa", AMD3DNowAthlon) 2031 .Case("3dnow", AMD3DNow) 2032 .Case("mmx", MMX) 2033 .Default(NoMMX3DNow); 2034 2035 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2036 } 2037 2038 // Don't tell the backend if we're turning off mmx; it will end up disabling 2039 // SSE, which we don't want. 2040 std::vector<std::string>::iterator it; 2041 it = std::find(Features.begin(), Features.end(), "-mmx"); 2042 if (it != Features.end()) 2043 Features.erase(it); 2044 } 2045 2046 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2047 /// definitions for this particular subtarget. 2048 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2049 MacroBuilder &Builder) const { 2050 // Target identification. 2051 if (PointerWidth == 64) { 2052 if (getLongWidth() == 64) { 2053 Builder.defineMacro("_LP64"); 2054 Builder.defineMacro("__LP64__"); 2055 } 2056 Builder.defineMacro("__amd64__"); 2057 Builder.defineMacro("__amd64"); 2058 Builder.defineMacro("__x86_64"); 2059 Builder.defineMacro("__x86_64__"); 2060 } else { 2061 DefineStd(Builder, "i386", Opts); 2062 } 2063 2064 // Subtarget options. 2065 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2066 // truly should be based on -mtune options. 2067 switch (CPU) { 2068 case CK_Generic: 2069 break; 2070 case CK_i386: 2071 // The rest are coming from the i386 define above. 2072 Builder.defineMacro("__tune_i386__"); 2073 break; 2074 case CK_i486: 2075 case CK_WinChipC6: 2076 case CK_WinChip2: 2077 case CK_C3: 2078 defineCPUMacros(Builder, "i486"); 2079 break; 2080 case CK_PentiumMMX: 2081 Builder.defineMacro("__pentium_mmx__"); 2082 Builder.defineMacro("__tune_pentium_mmx__"); 2083 // Fallthrough 2084 case CK_i586: 2085 case CK_Pentium: 2086 defineCPUMacros(Builder, "i586"); 2087 defineCPUMacros(Builder, "pentium"); 2088 break; 2089 case CK_Pentium3: 2090 case CK_Pentium3M: 2091 case CK_PentiumM: 2092 Builder.defineMacro("__tune_pentium3__"); 2093 // Fallthrough 2094 case CK_Pentium2: 2095 case CK_C3_2: 2096 Builder.defineMacro("__tune_pentium2__"); 2097 // Fallthrough 2098 case CK_PentiumPro: 2099 Builder.defineMacro("__tune_i686__"); 2100 Builder.defineMacro("__tune_pentiumpro__"); 2101 // Fallthrough 2102 case CK_i686: 2103 Builder.defineMacro("__i686"); 2104 Builder.defineMacro("__i686__"); 2105 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2106 Builder.defineMacro("__pentiumpro"); 2107 Builder.defineMacro("__pentiumpro__"); 2108 break; 2109 case CK_Pentium4: 2110 case CK_Pentium4M: 2111 defineCPUMacros(Builder, "pentium4"); 2112 break; 2113 case CK_Yonah: 2114 case CK_Prescott: 2115 case CK_Nocona: 2116 defineCPUMacros(Builder, "nocona"); 2117 break; 2118 case CK_Core2: 2119 case CK_Penryn: 2120 defineCPUMacros(Builder, "core2"); 2121 break; 2122 case CK_Atom: 2123 defineCPUMacros(Builder, "atom"); 2124 break; 2125 case CK_Corei7: 2126 case CK_Corei7AVX: 2127 case CK_CoreAVXi: 2128 case CK_CoreAVX2: 2129 defineCPUMacros(Builder, "corei7"); 2130 break; 2131 case CK_K6_2: 2132 Builder.defineMacro("__k6_2__"); 2133 Builder.defineMacro("__tune_k6_2__"); 2134 // Fallthrough 2135 case CK_K6_3: 2136 if (CPU != CK_K6_2) { // In case of fallthrough 2137 // FIXME: GCC may be enabling these in cases where some other k6 2138 // architecture is specified but -m3dnow is explicitly provided. The 2139 // exact semantics need to be determined and emulated here. 2140 Builder.defineMacro("__k6_3__"); 2141 Builder.defineMacro("__tune_k6_3__"); 2142 } 2143 // Fallthrough 2144 case CK_K6: 2145 defineCPUMacros(Builder, "k6"); 2146 break; 2147 case CK_Athlon: 2148 case CK_AthlonThunderbird: 2149 case CK_Athlon4: 2150 case CK_AthlonXP: 2151 case CK_AthlonMP: 2152 defineCPUMacros(Builder, "athlon"); 2153 if (SSELevel != NoSSE) { 2154 Builder.defineMacro("__athlon_sse__"); 2155 Builder.defineMacro("__tune_athlon_sse__"); 2156 } 2157 break; 2158 case CK_K8: 2159 case CK_K8SSE3: 2160 case CK_x86_64: 2161 case CK_Opteron: 2162 case CK_OpteronSSE3: 2163 case CK_Athlon64: 2164 case CK_Athlon64SSE3: 2165 case CK_AthlonFX: 2166 defineCPUMacros(Builder, "k8"); 2167 break; 2168 case CK_AMDFAM10: 2169 defineCPUMacros(Builder, "amdfam10"); 2170 break; 2171 case CK_BTVER1: 2172 defineCPUMacros(Builder, "btver1"); 2173 break; 2174 case CK_BDVER1: 2175 defineCPUMacros(Builder, "bdver1"); 2176 break; 2177 case CK_BDVER2: 2178 defineCPUMacros(Builder, "bdver2"); 2179 break; 2180 case CK_Geode: 2181 defineCPUMacros(Builder, "geode"); 2182 break; 2183 } 2184 2185 // Target properties. 2186 Builder.defineMacro("__LITTLE_ENDIAN__"); 2187 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2188 2189 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2190 // functions in glibc header files that use FP Stack inline asm which the 2191 // backend can't deal with (PR879). 2192 Builder.defineMacro("__NO_MATH_INLINES"); 2193 2194 if (HasAES) 2195 Builder.defineMacro("__AES__"); 2196 2197 if (HasPCLMUL) 2198 Builder.defineMacro("__PCLMUL__"); 2199 2200 if (HasLZCNT) 2201 Builder.defineMacro("__LZCNT__"); 2202 2203 if (HasRDRND) 2204 Builder.defineMacro("__RDRND__"); 2205 2206 if (HasBMI) 2207 Builder.defineMacro("__BMI__"); 2208 2209 if (HasBMI2) 2210 Builder.defineMacro("__BMI2__"); 2211 2212 if (HasPOPCNT) 2213 Builder.defineMacro("__POPCNT__"); 2214 2215 if (HasSSE4a) 2216 Builder.defineMacro("__SSE4A__"); 2217 2218 if (HasFMA4) 2219 Builder.defineMacro("__FMA4__"); 2220 2221 if (HasFMA) 2222 Builder.defineMacro("__FMA__"); 2223 2224 if (HasXOP) 2225 Builder.defineMacro("__XOP__"); 2226 2227 // Each case falls through to the previous one here. 2228 switch (SSELevel) { 2229 case AVX2: 2230 Builder.defineMacro("__AVX2__"); 2231 case AVX: 2232 Builder.defineMacro("__AVX__"); 2233 case SSE42: 2234 Builder.defineMacro("__SSE4_2__"); 2235 case SSE41: 2236 Builder.defineMacro("__SSE4_1__"); 2237 case SSSE3: 2238 Builder.defineMacro("__SSSE3__"); 2239 case SSE3: 2240 Builder.defineMacro("__SSE3__"); 2241 case SSE2: 2242 Builder.defineMacro("__SSE2__"); 2243 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2244 case SSE1: 2245 Builder.defineMacro("__SSE__"); 2246 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2247 case NoSSE: 2248 break; 2249 } 2250 2251 if (Opts.MicrosoftExt && PointerWidth == 32) { 2252 switch (SSELevel) { 2253 case AVX2: 2254 case AVX: 2255 case SSE42: 2256 case SSE41: 2257 case SSSE3: 2258 case SSE3: 2259 case SSE2: 2260 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2261 break; 2262 case SSE1: 2263 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2264 break; 2265 default: 2266 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2267 } 2268 } 2269 2270 // Each case falls through to the previous one here. 2271 switch (MMX3DNowLevel) { 2272 case AMD3DNowAthlon: 2273 Builder.defineMacro("__3dNOW_A__"); 2274 case AMD3DNow: 2275 Builder.defineMacro("__3dNOW__"); 2276 case MMX: 2277 Builder.defineMacro("__MMX__"); 2278 case NoMMX3DNow: 2279 break; 2280 } 2281 } 2282 2283 bool X86TargetInfo::hasFeature(StringRef Feature) const { 2284 return llvm::StringSwitch<bool>(Feature) 2285 .Case("aes", HasAES) 2286 .Case("avx", SSELevel >= AVX) 2287 .Case("avx2", SSELevel >= AVX2) 2288 .Case("bmi", HasBMI) 2289 .Case("bmi2", HasBMI2) 2290 .Case("fma", HasFMA) 2291 .Case("fma4", HasFMA4) 2292 .Case("lzcnt", HasLZCNT) 2293 .Case("rdrnd", HasRDRND) 2294 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 2295 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 2296 .Case("mmx", MMX3DNowLevel >= MMX) 2297 .Case("pclmul", HasPCLMUL) 2298 .Case("popcnt", HasPOPCNT) 2299 .Case("sse", SSELevel >= SSE1) 2300 .Case("sse2", SSELevel >= SSE2) 2301 .Case("sse3", SSELevel >= SSE3) 2302 .Case("ssse3", SSELevel >= SSSE3) 2303 .Case("sse41", SSELevel >= SSE41) 2304 .Case("sse42", SSELevel >= SSE42) 2305 .Case("sse4a", HasSSE4a) 2306 .Case("x86", true) 2307 .Case("x86_32", PointerWidth == 32) 2308 .Case("x86_64", PointerWidth == 64) 2309 .Case("xop", HasXOP) 2310 .Default(false); 2311 } 2312 2313 bool 2314 X86TargetInfo::validateAsmConstraint(const char *&Name, 2315 TargetInfo::ConstraintInfo &Info) const { 2316 switch (*Name) { 2317 default: return false; 2318 case 'Y': // first letter of a pair: 2319 switch (*(Name+1)) { 2320 default: return false; 2321 case '0': // First SSE register. 2322 case 't': // Any SSE register, when SSE2 is enabled. 2323 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 2324 case 'm': // any MMX register, when inter-unit moves enabled. 2325 break; // falls through to setAllowsRegister. 2326 } 2327 case 'a': // eax. 2328 case 'b': // ebx. 2329 case 'c': // ecx. 2330 case 'd': // edx. 2331 case 'S': // esi. 2332 case 'D': // edi. 2333 case 'A': // edx:eax. 2334 case 'f': // any x87 floating point stack register. 2335 case 't': // top of floating point stack. 2336 case 'u': // second from top of floating point stack. 2337 case 'q': // Any register accessible as [r]l: a, b, c, and d. 2338 case 'y': // Any MMX register. 2339 case 'x': // Any SSE register. 2340 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 2341 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 2342 case 'l': // "Index" registers: any general register that can be used as an 2343 // index in a base+index memory access. 2344 Info.setAllowsRegister(); 2345 return true; 2346 case 'C': // SSE floating point constant. 2347 case 'G': // x87 floating point constant. 2348 case 'e': // 32-bit signed integer constant for use with zero-extending 2349 // x86_64 instructions. 2350 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 2351 // x86_64 instructions. 2352 return true; 2353 } 2354 } 2355 2356 2357 std::string 2358 X86TargetInfo::convertConstraint(const char *&Constraint) const { 2359 switch (*Constraint) { 2360 case 'a': return std::string("{ax}"); 2361 case 'b': return std::string("{bx}"); 2362 case 'c': return std::string("{cx}"); 2363 case 'd': return std::string("{dx}"); 2364 case 'S': return std::string("{si}"); 2365 case 'D': return std::string("{di}"); 2366 case 'p': // address 2367 return std::string("im"); 2368 case 't': // top of floating point stack. 2369 return std::string("{st}"); 2370 case 'u': // second from top of floating point stack. 2371 return std::string("{st(1)}"); // second from top of floating point stack. 2372 default: 2373 return std::string(1, *Constraint); 2374 } 2375 } 2376 } // end anonymous namespace 2377 2378 namespace { 2379 // X86-32 generic target 2380 class X86_32TargetInfo : public X86TargetInfo { 2381 public: 2382 X86_32TargetInfo(const std::string& triple) : X86TargetInfo(triple) { 2383 DoubleAlign = LongLongAlign = 32; 2384 LongDoubleWidth = 96; 2385 LongDoubleAlign = 32; 2386 SuitableAlign = 128; 2387 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2388 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-" 2389 "a0:0:64-f80:32:32-n8:16:32-S128"; 2390 SizeType = UnsignedInt; 2391 PtrDiffType = SignedInt; 2392 IntPtrType = SignedInt; 2393 RegParmMax = 3; 2394 2395 // Use fpret for all types. 2396 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 2397 (1 << TargetInfo::Double) | 2398 (1 << TargetInfo::LongDouble)); 2399 2400 // x86-32 has atomics up to 8 bytes 2401 // FIXME: Check that we actually have cmpxchg8b before setting 2402 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 2403 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 2404 } 2405 virtual BuiltinVaListKind getBuiltinVaListKind() const { 2406 return TargetInfo::CharPtrBuiltinVaList; 2407 } 2408 2409 int getEHDataRegisterNumber(unsigned RegNo) const { 2410 if (RegNo == 0) return 0; 2411 if (RegNo == 1) return 2; 2412 return -1; 2413 } 2414 }; 2415 } // end anonymous namespace 2416 2417 namespace { 2418 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 2419 public: 2420 NetBSDI386TargetInfo(const std::string &triple) : 2421 NetBSDTargetInfo<X86_32TargetInfo>(triple) { 2422 } 2423 2424 virtual unsigned getFloatEvalMethod() const { 2425 // NetBSD defaults to "double" rounding 2426 return 1; 2427 } 2428 }; 2429 } // end anonymous namespace 2430 2431 namespace { 2432 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 2433 public: 2434 OpenBSDI386TargetInfo(const std::string& triple) : 2435 OpenBSDTargetInfo<X86_32TargetInfo>(triple) { 2436 SizeType = UnsignedLong; 2437 IntPtrType = SignedLong; 2438 PtrDiffType = SignedLong; 2439 } 2440 }; 2441 } // end anonymous namespace 2442 2443 namespace { 2444 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 2445 public: 2446 DarwinI386TargetInfo(const std::string& triple) : 2447 DarwinTargetInfo<X86_32TargetInfo>(triple) { 2448 LongDoubleWidth = 128; 2449 LongDoubleAlign = 128; 2450 SuitableAlign = 128; 2451 SizeType = UnsignedLong; 2452 IntPtrType = SignedLong; 2453 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2454 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-" 2455 "a0:0:64-f80:128:128-n8:16:32-S128"; 2456 HasAlignMac68kSupport = true; 2457 } 2458 2459 }; 2460 } // end anonymous namespace 2461 2462 namespace { 2463 // x86-32 Windows target 2464 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 2465 public: 2466 WindowsX86_32TargetInfo(const std::string& triple) 2467 : WindowsTargetInfo<X86_32TargetInfo>(triple) { 2468 TLSSupported = false; 2469 WCharType = UnsignedShort; 2470 DoubleAlign = LongLongAlign = 64; 2471 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2472 "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-" 2473 "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32"; 2474 } 2475 virtual void getTargetDefines(const LangOptions &Opts, 2476 MacroBuilder &Builder) const { 2477 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 2478 } 2479 }; 2480 } // end anonymous namespace 2481 2482 namespace { 2483 2484 // x86-32 Windows Visual Studio target 2485 class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo { 2486 public: 2487 VisualStudioWindowsX86_32TargetInfo(const std::string& triple) 2488 : WindowsX86_32TargetInfo(triple) { 2489 LongDoubleWidth = LongDoubleAlign = 64; 2490 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 2491 } 2492 virtual void getTargetDefines(const LangOptions &Opts, 2493 MacroBuilder &Builder) const { 2494 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 2495 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 2496 // The value of the following reflects processor type. 2497 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 2498 // We lost the original triple, so we use the default. 2499 Builder.defineMacro("_M_IX86", "600"); 2500 } 2501 }; 2502 } // end anonymous namespace 2503 2504 namespace { 2505 // x86-32 MinGW target 2506 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 2507 public: 2508 MinGWX86_32TargetInfo(const std::string& triple) 2509 : WindowsX86_32TargetInfo(triple) { 2510 } 2511 virtual void getTargetDefines(const LangOptions &Opts, 2512 MacroBuilder &Builder) const { 2513 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 2514 DefineStd(Builder, "WIN32", Opts); 2515 DefineStd(Builder, "WINNT", Opts); 2516 Builder.defineMacro("_X86_"); 2517 Builder.defineMacro("__MSVCRT__"); 2518 Builder.defineMacro("__MINGW32__"); 2519 2520 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 2521 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 2522 if (Opts.MicrosoftExt) 2523 // Provide "as-is" __declspec. 2524 Builder.defineMacro("__declspec", "__declspec"); 2525 else 2526 // Provide alias of __attribute__ like mingw32-gcc. 2527 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 2528 } 2529 }; 2530 } // end anonymous namespace 2531 2532 namespace { 2533 // x86-32 Cygwin target 2534 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 2535 public: 2536 CygwinX86_32TargetInfo(const std::string& triple) 2537 : X86_32TargetInfo(triple) { 2538 TLSSupported = false; 2539 WCharType = UnsignedShort; 2540 DoubleAlign = LongLongAlign = 64; 2541 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2542 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-" 2543 "a0:0:64-f80:32:32-n8:16:32-S32"; 2544 } 2545 virtual void getTargetDefines(const LangOptions &Opts, 2546 MacroBuilder &Builder) const { 2547 X86_32TargetInfo::getTargetDefines(Opts, Builder); 2548 Builder.defineMacro("__CYGWIN__"); 2549 Builder.defineMacro("__CYGWIN32__"); 2550 DefineStd(Builder, "unix", Opts); 2551 if (Opts.CPlusPlus) 2552 Builder.defineMacro("_GNU_SOURCE"); 2553 } 2554 }; 2555 } // end anonymous namespace 2556 2557 namespace { 2558 // x86-32 Haiku target 2559 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 2560 public: 2561 HaikuX86_32TargetInfo(const std::string& triple) 2562 : X86_32TargetInfo(triple) { 2563 SizeType = UnsignedLong; 2564 IntPtrType = SignedLong; 2565 PtrDiffType = SignedLong; 2566 this->UserLabelPrefix = ""; 2567 } 2568 virtual void getTargetDefines(const LangOptions &Opts, 2569 MacroBuilder &Builder) const { 2570 X86_32TargetInfo::getTargetDefines(Opts, Builder); 2571 Builder.defineMacro("__INTEL__"); 2572 Builder.defineMacro("__HAIKU__"); 2573 } 2574 }; 2575 } // end anonymous namespace 2576 2577 // RTEMS Target 2578 template<typename Target> 2579 class RTEMSTargetInfo : public OSTargetInfo<Target> { 2580 protected: 2581 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 2582 MacroBuilder &Builder) const { 2583 // RTEMS defines; list based off of gcc output 2584 2585 Builder.defineMacro("__rtems__"); 2586 Builder.defineMacro("__ELF__"); 2587 } 2588 public: 2589 RTEMSTargetInfo(const std::string &triple) 2590 : OSTargetInfo<Target>(triple) { 2591 this->UserLabelPrefix = ""; 2592 2593 llvm::Triple Triple(triple); 2594 switch (Triple.getArch()) { 2595 default: 2596 case llvm::Triple::x86: 2597 // this->MCountName = ".mcount"; 2598 break; 2599 case llvm::Triple::mips: 2600 case llvm::Triple::mipsel: 2601 case llvm::Triple::ppc: 2602 case llvm::Triple::ppc64: 2603 // this->MCountName = "_mcount"; 2604 break; 2605 case llvm::Triple::arm: 2606 // this->MCountName = "__mcount"; 2607 break; 2608 } 2609 2610 } 2611 }; 2612 2613 namespace { 2614 // x86-32 RTEMS target 2615 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 2616 public: 2617 RTEMSX86_32TargetInfo(const std::string& triple) 2618 : X86_32TargetInfo(triple) { 2619 SizeType = UnsignedLong; 2620 IntPtrType = SignedLong; 2621 PtrDiffType = SignedLong; 2622 this->UserLabelPrefix = ""; 2623 } 2624 virtual void getTargetDefines(const LangOptions &Opts, 2625 MacroBuilder &Builder) const { 2626 X86_32TargetInfo::getTargetDefines(Opts, Builder); 2627 Builder.defineMacro("__INTEL__"); 2628 Builder.defineMacro("__rtems__"); 2629 } 2630 }; 2631 } // end anonymous namespace 2632 2633 namespace { 2634 // x86-64 generic target 2635 class X86_64TargetInfo : public X86TargetInfo { 2636 public: 2637 X86_64TargetInfo(const std::string &triple) : X86TargetInfo(triple) { 2638 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 2639 LongDoubleWidth = 128; 2640 LongDoubleAlign = 128; 2641 LargeArrayMinWidth = 128; 2642 LargeArrayAlign = 128; 2643 SuitableAlign = 128; 2644 IntMaxType = SignedLong; 2645 UIntMaxType = UnsignedLong; 2646 Int64Type = SignedLong; 2647 RegParmMax = 6; 2648 2649 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2650 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-" 2651 "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"; 2652 2653 // Use fpret only for long double. 2654 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 2655 2656 // Use fp2ret for _Complex long double. 2657 ComplexLongDoubleUsesFP2Ret = true; 2658 2659 // x86-64 has atomics up to 16 bytes. 2660 // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128 2661 // on CPUs with cmpxchg16b 2662 MaxAtomicPromoteWidth = 128; 2663 MaxAtomicInlineWidth = 64; 2664 } 2665 virtual BuiltinVaListKind getBuiltinVaListKind() const { 2666 return TargetInfo::X86_64ABIBuiltinVaList; 2667 } 2668 2669 int getEHDataRegisterNumber(unsigned RegNo) const { 2670 if (RegNo == 0) return 0; 2671 if (RegNo == 1) return 1; 2672 return -1; 2673 } 2674 }; 2675 } // end anonymous namespace 2676 2677 namespace { 2678 // x86-64 Windows target 2679 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 2680 public: 2681 WindowsX86_64TargetInfo(const std::string& triple) 2682 : WindowsTargetInfo<X86_64TargetInfo>(triple) { 2683 TLSSupported = false; 2684 WCharType = UnsignedShort; 2685 LongWidth = LongAlign = 32; 2686 DoubleAlign = LongLongAlign = 64; 2687 IntMaxType = SignedLongLong; 2688 UIntMaxType = UnsignedLongLong; 2689 Int64Type = SignedLongLong; 2690 SizeType = UnsignedLongLong; 2691 PtrDiffType = SignedLongLong; 2692 IntPtrType = SignedLongLong; 2693 this->UserLabelPrefix = ""; 2694 } 2695 virtual void getTargetDefines(const LangOptions &Opts, 2696 MacroBuilder &Builder) const { 2697 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 2698 Builder.defineMacro("_WIN64"); 2699 } 2700 virtual BuiltinVaListKind getBuiltinVaListKind() const { 2701 return TargetInfo::CharPtrBuiltinVaList; 2702 } 2703 }; 2704 } // end anonymous namespace 2705 2706 namespace { 2707 // x86-64 Windows Visual Studio target 2708 class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo { 2709 public: 2710 VisualStudioWindowsX86_64TargetInfo(const std::string& triple) 2711 : WindowsX86_64TargetInfo(triple) { 2712 LongDoubleWidth = LongDoubleAlign = 64; 2713 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 2714 } 2715 virtual void getTargetDefines(const LangOptions &Opts, 2716 MacroBuilder &Builder) const { 2717 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 2718 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 2719 Builder.defineMacro("_M_X64"); 2720 Builder.defineMacro("_M_AMD64"); 2721 } 2722 }; 2723 } // end anonymous namespace 2724 2725 namespace { 2726 // x86-64 MinGW target 2727 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 2728 public: 2729 MinGWX86_64TargetInfo(const std::string& triple) 2730 : WindowsX86_64TargetInfo(triple) { 2731 } 2732 virtual void getTargetDefines(const LangOptions &Opts, 2733 MacroBuilder &Builder) const { 2734 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 2735 DefineStd(Builder, "WIN64", Opts); 2736 Builder.defineMacro("__MSVCRT__"); 2737 Builder.defineMacro("__MINGW32__"); 2738 Builder.defineMacro("__MINGW64__"); 2739 2740 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 2741 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 2742 if (Opts.MicrosoftExt) 2743 // Provide "as-is" __declspec. 2744 Builder.defineMacro("__declspec", "__declspec"); 2745 else 2746 // Provide alias of __attribute__ like mingw32-gcc. 2747 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 2748 } 2749 }; 2750 } // end anonymous namespace 2751 2752 namespace { 2753 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 2754 public: 2755 DarwinX86_64TargetInfo(const std::string& triple) 2756 : DarwinTargetInfo<X86_64TargetInfo>(triple) { 2757 Int64Type = SignedLongLong; 2758 } 2759 }; 2760 } // end anonymous namespace 2761 2762 namespace { 2763 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 2764 public: 2765 OpenBSDX86_64TargetInfo(const std::string& triple) 2766 : OpenBSDTargetInfo<X86_64TargetInfo>(triple) { 2767 IntMaxType = SignedLongLong; 2768 UIntMaxType = UnsignedLongLong; 2769 Int64Type = SignedLongLong; 2770 } 2771 }; 2772 } // end anonymous namespace 2773 2774 namespace { 2775 class ARMTargetInfo : public TargetInfo { 2776 // Possible FPU choices. 2777 enum FPUMode { 2778 NoFPU, 2779 VFP2FPU, 2780 VFP3FPU, 2781 NeonFPU 2782 }; 2783 2784 static bool FPUModeIsVFP(FPUMode Mode) { 2785 return Mode >= VFP2FPU && Mode <= NeonFPU; 2786 } 2787 2788 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 2789 static const char * const GCCRegNames[]; 2790 2791 std::string ABI, CPU; 2792 2793 unsigned FPU : 3; 2794 2795 unsigned IsThumb : 1; 2796 2797 // Initialized via features. 2798 unsigned SoftFloat : 1; 2799 unsigned SoftFloatABI : 1; 2800 2801 static const Builtin::Info BuiltinInfo[]; 2802 2803 public: 2804 ARMTargetInfo(const std::string &TripleStr) 2805 : TargetInfo(TripleStr), ABI("aapcs-linux"), CPU("arm1136j-s") 2806 { 2807 BigEndian = false; 2808 SizeType = UnsignedInt; 2809 PtrDiffType = SignedInt; 2810 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 2811 WCharType = UnsignedInt; 2812 2813 // {} in inline assembly are neon specifiers, not assembly variant 2814 // specifiers. 2815 NoAsmVariants = true; 2816 2817 // FIXME: Should we just treat this as a feature? 2818 IsThumb = getTriple().getArchName().startswith("thumb"); 2819 if (IsThumb) { 2820 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 2821 // so set preferred for small types to 32. 2822 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" 2823 "i64:64:64-f32:32:32-f64:64:64-" 2824 "v64:64:64-v128:64:128-a0:0:32-n32-S64"); 2825 } else { 2826 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2827 "i64:64:64-f32:32:32-f64:64:64-" 2828 "v64:64:64-v128:64:128-a0:0:64-n32-S64"); 2829 } 2830 2831 // ARM targets default to using the ARM C++ ABI. 2832 CXXABI = CXXABI_ARM; 2833 2834 // ARM has atomics up to 8 bytes 2835 // FIXME: Set MaxAtomicInlineWidth if we have the feature v6e 2836 MaxAtomicPromoteWidth = 64; 2837 2838 // Do force alignment of members that follow zero length bitfields. If 2839 // the alignment of the zero-length bitfield is greater than the member 2840 // that follows it, `bar', `bar' will be aligned as the type of the 2841 // zero length bitfield. 2842 UseZeroLengthBitfieldAlignment = true; 2843 } 2844 virtual const char *getABI() const { return ABI.c_str(); } 2845 virtual bool setABI(const std::string &Name) { 2846 ABI = Name; 2847 2848 // The defaults (above) are for AAPCS, check if we need to change them. 2849 // 2850 // FIXME: We need support for -meabi... we could just mangle it into the 2851 // name. 2852 if (Name == "apcs-gnu") { 2853 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 2854 SizeType = UnsignedLong; 2855 2856 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 2857 WCharType = SignedInt; 2858 2859 // Do not respect the alignment of bit-field types when laying out 2860 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 2861 UseBitFieldTypeAlignment = false; 2862 2863 /// gcc forces the alignment to 4 bytes, regardless of the type of the 2864 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 2865 /// gcc. 2866 ZeroLengthBitfieldBoundary = 32; 2867 2868 if (IsThumb) { 2869 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 2870 // so set preferred for small types to 32. 2871 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" 2872 "i64:32:64-f32:32:32-f64:32:64-" 2873 "v64:32:64-v128:32:128-a0:0:32-n32-S32"); 2874 } else { 2875 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2876 "i64:32:64-f32:32:32-f64:32:64-" 2877 "v64:32:64-v128:32:128-a0:0:32-n32-S32"); 2878 } 2879 2880 // FIXME: Override "preferred align" for double and long long. 2881 } else if (Name == "aapcs") { 2882 // FIXME: Enumerated types are variable width in straight AAPCS. 2883 } else if (Name == "aapcs-linux") { 2884 ; 2885 } else 2886 return false; 2887 2888 return true; 2889 } 2890 2891 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2892 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 2893 Features["vfp2"] = true; 2894 else if (CPU == "cortex-a8" || CPU == "cortex-a9") 2895 Features["neon"] = true; 2896 } 2897 2898 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 2899 StringRef Name, 2900 bool Enabled) const { 2901 if (Name == "soft-float" || Name == "soft-float-abi" || 2902 Name == "vfp2" || Name == "vfp3" || Name == "neon" || Name == "d16" || 2903 Name == "neonfp") { 2904 Features[Name] = Enabled; 2905 } else 2906 return false; 2907 2908 return true; 2909 } 2910 2911 virtual void HandleTargetFeatures(std::vector<std::string> &Features) { 2912 FPU = NoFPU; 2913 SoftFloat = SoftFloatABI = false; 2914 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 2915 if (Features[i] == "+soft-float") 2916 SoftFloat = true; 2917 else if (Features[i] == "+soft-float-abi") 2918 SoftFloatABI = true; 2919 else if (Features[i] == "+vfp2") 2920 FPU = VFP2FPU; 2921 else if (Features[i] == "+vfp3") 2922 FPU = VFP3FPU; 2923 else if (Features[i] == "+neon") 2924 FPU = NeonFPU; 2925 } 2926 2927 // Remove front-end specific options which the backend handles differently. 2928 std::vector<std::string>::iterator it; 2929 it = std::find(Features.begin(), Features.end(), "+soft-float"); 2930 if (it != Features.end()) 2931 Features.erase(it); 2932 it = std::find(Features.begin(), Features.end(), "+soft-float-abi"); 2933 if (it != Features.end()) 2934 Features.erase(it); 2935 } 2936 2937 virtual bool hasFeature(StringRef Feature) const { 2938 return llvm::StringSwitch<bool>(Feature) 2939 .Case("arm", true) 2940 .Case("softfloat", SoftFloat) 2941 .Case("thumb", IsThumb) 2942 .Case("neon", FPU == NeonFPU && !SoftFloat && 2943 StringRef(getCPUDefineSuffix(CPU)).startswith("7")) 2944 .Default(false); 2945 } 2946 static const char *getCPUDefineSuffix(StringRef Name) { 2947 return llvm::StringSwitch<const char*>(Name) 2948 .Cases("arm8", "arm810", "4") 2949 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") 2950 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 2951 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 2952 .Case("ep9312", "4T") 2953 .Cases("arm10tdmi", "arm1020t", "5T") 2954 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 2955 .Case("arm926ej-s", "5TEJ") 2956 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 2957 .Cases("xscale", "iwmmxt", "5TE") 2958 .Case("arm1136j-s", "6J") 2959 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 2960 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 2961 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 2962 .Cases("cortex-a8", "cortex-a9", "7A") 2963 .Case("cortex-m3", "7M") 2964 .Case("cortex-m4", "7M") 2965 .Case("cortex-m0", "6M") 2966 .Default(0); 2967 } 2968 virtual bool setCPU(const std::string &Name) { 2969 if (!getCPUDefineSuffix(Name)) 2970 return false; 2971 2972 CPU = Name; 2973 return true; 2974 } 2975 virtual void getTargetDefines(const LangOptions &Opts, 2976 MacroBuilder &Builder) const { 2977 // Target identification. 2978 Builder.defineMacro("__arm"); 2979 Builder.defineMacro("__arm__"); 2980 2981 // Target properties. 2982 Builder.defineMacro("__ARMEL__"); 2983 Builder.defineMacro("__LITTLE_ENDIAN__"); 2984 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2985 2986 StringRef CPUArch = getCPUDefineSuffix(CPU); 2987 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 2988 2989 // Subtarget options. 2990 2991 // FIXME: It's more complicated than this and we don't really support 2992 // interworking. 2993 if ('5' <= CPUArch[0] && CPUArch[0] <= '7') 2994 Builder.defineMacro("__THUMB_INTERWORK__"); 2995 2996 if (ABI == "aapcs" || ABI == "aapcs-linux") 2997 Builder.defineMacro("__ARM_EABI__"); 2998 2999 if (SoftFloat) 3000 Builder.defineMacro("__SOFTFP__"); 3001 3002 if (CPU == "xscale") 3003 Builder.defineMacro("__XSCALE__"); 3004 3005 bool IsARMv7 = CPUArch.startswith("7"); 3006 if (IsThumb) { 3007 Builder.defineMacro("__THUMBEL__"); 3008 Builder.defineMacro("__thumb__"); 3009 if (CPUArch == "6T2" || IsARMv7) 3010 Builder.defineMacro("__thumb2__"); 3011 } 3012 3013 // Note, this is always on in gcc, even though it doesn't make sense. 3014 Builder.defineMacro("__APCS_32__"); 3015 3016 if (FPUModeIsVFP((FPUMode) FPU)) 3017 Builder.defineMacro("__VFP_FP__"); 3018 3019 // This only gets set when Neon instructions are actually available, unlike 3020 // the VFP define, hence the soft float and arch check. This is subtly 3021 // different from gcc, we follow the intent which was that it should be set 3022 // when Neon instructions are actually available. 3023 if (FPU == NeonFPU && !SoftFloat && IsARMv7) 3024 Builder.defineMacro("__ARM_NEON__"); 3025 } 3026 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3027 unsigned &NumRecords) const { 3028 Records = BuiltinInfo; 3029 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 3030 } 3031 virtual bool isCLZForZeroUndef() const { return false; } 3032 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3033 return TargetInfo::VoidPtrBuiltinVaList; 3034 } 3035 virtual void getGCCRegNames(const char * const *&Names, 3036 unsigned &NumNames) const; 3037 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3038 unsigned &NumAliases) const; 3039 virtual bool validateAsmConstraint(const char *&Name, 3040 TargetInfo::ConstraintInfo &Info) const { 3041 // FIXME: Check if this is complete 3042 switch (*Name) { 3043 default: 3044 case 'l': // r0-r7 3045 case 'h': // r8-r15 3046 case 'w': // VFP Floating point register single precision 3047 case 'P': // VFP Floating point register double precision 3048 Info.setAllowsRegister(); 3049 return true; 3050 case 'Q': // A memory address that is a single base register. 3051 Info.setAllowsMemory(); 3052 return true; 3053 case 'U': // a memory reference... 3054 switch (Name[1]) { 3055 case 'q': // ...ARMV4 ldrsb 3056 case 'v': // ...VFP load/store (reg+constant offset) 3057 case 'y': // ...iWMMXt load/store 3058 case 't': // address valid for load/store opaque types wider 3059 // than 128-bits 3060 case 'n': // valid address for Neon doubleword vector load/store 3061 case 'm': // valid address for Neon element and structure load/store 3062 case 's': // valid address for non-offset loads/stores of quad-word 3063 // values in four ARM registers 3064 Info.setAllowsMemory(); 3065 Name++; 3066 return true; 3067 } 3068 } 3069 return false; 3070 } 3071 virtual std::string convertConstraint(const char *&Constraint) const { 3072 std::string R; 3073 switch (*Constraint) { 3074 case 'U': // Two-character constraint; add "^" hint for later parsing. 3075 R = std::string("^") + std::string(Constraint, 2); 3076 Constraint++; 3077 break; 3078 case 'p': // 'p' should be translated to 'r' by default. 3079 R = std::string("r"); 3080 break; 3081 default: 3082 return std::string(1, *Constraint); 3083 } 3084 return R; 3085 } 3086 virtual const char *getClobbers() const { 3087 // FIXME: Is this really right? 3088 return ""; 3089 } 3090 }; 3091 3092 const char * const ARMTargetInfo::GCCRegNames[] = { 3093 // Integer registers 3094 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 3095 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 3096 3097 // Float registers 3098 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 3099 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 3100 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 3101 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 3102 3103 // Double registers 3104 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 3105 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 3106 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 3107 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 3108 3109 // Quad registers 3110 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 3111 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 3112 }; 3113 3114 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 3115 unsigned &NumNames) const { 3116 Names = GCCRegNames; 3117 NumNames = llvm::array_lengthof(GCCRegNames); 3118 } 3119 3120 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 3121 { { "a1" }, "r0" }, 3122 { { "a2" }, "r1" }, 3123 { { "a3" }, "r2" }, 3124 { { "a4" }, "r3" }, 3125 { { "v1" }, "r4" }, 3126 { { "v2" }, "r5" }, 3127 { { "v3" }, "r6" }, 3128 { { "v4" }, "r7" }, 3129 { { "v5" }, "r8" }, 3130 { { "v6", "rfp" }, "r9" }, 3131 { { "sl" }, "r10" }, 3132 { { "fp" }, "r11" }, 3133 { { "ip" }, "r12" }, 3134 { { "r13" }, "sp" }, 3135 { { "r14" }, "lr" }, 3136 { { "r15" }, "pc" }, 3137 // The S, D and Q registers overlap, but aren't really aliases; we 3138 // don't want to substitute one of these for a different-sized one. 3139 }; 3140 3141 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3142 unsigned &NumAliases) const { 3143 Aliases = GCCRegAliases; 3144 NumAliases = llvm::array_lengthof(GCCRegAliases); 3145 } 3146 3147 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 3148 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3149 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3150 ALL_LANGUAGES }, 3151 #include "clang/Basic/BuiltinsARM.def" 3152 }; 3153 } // end anonymous namespace. 3154 3155 namespace { 3156 class DarwinARMTargetInfo : 3157 public DarwinTargetInfo<ARMTargetInfo> { 3158 protected: 3159 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3160 MacroBuilder &Builder) const { 3161 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 3162 } 3163 3164 public: 3165 DarwinARMTargetInfo(const std::string& triple) 3166 : DarwinTargetInfo<ARMTargetInfo>(triple) { 3167 HasAlignMac68kSupport = true; 3168 // iOS always has 64-bit atomic instructions. 3169 // FIXME: This should be based off of the target features in ARMTargetInfo. 3170 MaxAtomicInlineWidth = 64; 3171 } 3172 }; 3173 } // end anonymous namespace. 3174 3175 3176 namespace { 3177 // Hexagon abstract base class 3178 class HexagonTargetInfo : public TargetInfo { 3179 static const Builtin::Info BuiltinInfo[]; 3180 static const char * const GCCRegNames[]; 3181 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3182 std::string CPU; 3183 public: 3184 HexagonTargetInfo(const std::string& triple) : TargetInfo(triple) { 3185 BigEndian = false; 3186 DescriptionString = ("e-p:32:32:32-" 3187 "i64:64:64-i32:32:32-i16:16:16-i1:32:32" 3188 "f64:64:64-f32:32:32-a0:0-n32"); 3189 3190 // {} in inline assembly are packet specifiers, not assembly variant 3191 // specifiers. 3192 NoAsmVariants = true; 3193 } 3194 3195 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3196 unsigned &NumRecords) const { 3197 Records = BuiltinInfo; 3198 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 3199 } 3200 3201 virtual bool validateAsmConstraint(const char *&Name, 3202 TargetInfo::ConstraintInfo &Info) const { 3203 return true; 3204 } 3205 3206 virtual void getTargetDefines(const LangOptions &Opts, 3207 MacroBuilder &Builder) const; 3208 3209 virtual bool hasFeature(StringRef Feature) const { 3210 return Feature == "hexagon"; 3211 } 3212 3213 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3214 return TargetInfo::CharPtrBuiltinVaList; 3215 } 3216 virtual void getGCCRegNames(const char * const *&Names, 3217 unsigned &NumNames) const; 3218 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3219 unsigned &NumAliases) const; 3220 virtual const char *getClobbers() const { 3221 return ""; 3222 } 3223 3224 static const char *getHexagonCPUSuffix(StringRef Name) { 3225 return llvm::StringSwitch<const char*>(Name) 3226 .Case("hexagonv2", "2") 3227 .Case("hexagonv3", "3") 3228 .Case("hexagonv4", "4") 3229 .Case("hexagonv5", "5") 3230 .Default(0); 3231 } 3232 3233 virtual bool setCPU(const std::string &Name) { 3234 if (!getHexagonCPUSuffix(Name)) 3235 return false; 3236 3237 CPU = Name; 3238 return true; 3239 } 3240 }; 3241 3242 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 3243 MacroBuilder &Builder) const { 3244 Builder.defineMacro("qdsp6"); 3245 Builder.defineMacro("__qdsp6", "1"); 3246 Builder.defineMacro("__qdsp6__", "1"); 3247 3248 Builder.defineMacro("hexagon"); 3249 Builder.defineMacro("__hexagon", "1"); 3250 Builder.defineMacro("__hexagon__", "1"); 3251 3252 if(CPU == "hexagonv1") { 3253 Builder.defineMacro("__HEXAGON_V1__"); 3254 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 3255 if(Opts.HexagonQdsp6Compat) { 3256 Builder.defineMacro("__QDSP6_V1__"); 3257 Builder.defineMacro("__QDSP6_ARCH__", "1"); 3258 } 3259 } 3260 else if(CPU == "hexagonv2") { 3261 Builder.defineMacro("__HEXAGON_V2__"); 3262 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 3263 if(Opts.HexagonQdsp6Compat) { 3264 Builder.defineMacro("__QDSP6_V2__"); 3265 Builder.defineMacro("__QDSP6_ARCH__", "2"); 3266 } 3267 } 3268 else if(CPU == "hexagonv3") { 3269 Builder.defineMacro("__HEXAGON_V3__"); 3270 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 3271 if(Opts.HexagonQdsp6Compat) { 3272 Builder.defineMacro("__QDSP6_V3__"); 3273 Builder.defineMacro("__QDSP6_ARCH__", "3"); 3274 } 3275 } 3276 else if(CPU == "hexagonv4") { 3277 Builder.defineMacro("__HEXAGON_V4__"); 3278 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 3279 if(Opts.HexagonQdsp6Compat) { 3280 Builder.defineMacro("__QDSP6_V4__"); 3281 Builder.defineMacro("__QDSP6_ARCH__", "4"); 3282 } 3283 } 3284 else if(CPU == "hexagonv5") { 3285 Builder.defineMacro("__HEXAGON_V5__"); 3286 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 3287 if(Opts.HexagonQdsp6Compat) { 3288 Builder.defineMacro("__QDSP6_V5__"); 3289 Builder.defineMacro("__QDSP6_ARCH__", "5"); 3290 } 3291 } 3292 } 3293 3294 const char * const HexagonTargetInfo::GCCRegNames[] = { 3295 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 3296 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 3297 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 3298 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 3299 "p0", "p1", "p2", "p3", 3300 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 3301 }; 3302 3303 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 3304 unsigned &NumNames) const { 3305 Names = GCCRegNames; 3306 NumNames = llvm::array_lengthof(GCCRegNames); 3307 } 3308 3309 3310 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 3311 { { "sp" }, "r29" }, 3312 { { "fp" }, "r30" }, 3313 { { "lr" }, "r31" }, 3314 }; 3315 3316 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3317 unsigned &NumAliases) const { 3318 Aliases = GCCRegAliases; 3319 NumAliases = llvm::array_lengthof(GCCRegAliases); 3320 } 3321 3322 3323 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 3324 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3325 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3326 ALL_LANGUAGES }, 3327 #include "clang/Basic/BuiltinsHexagon.def" 3328 }; 3329 } 3330 3331 3332 namespace { 3333 class SparcV8TargetInfo : public TargetInfo { 3334 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3335 static const char * const GCCRegNames[]; 3336 bool SoftFloat; 3337 public: 3338 SparcV8TargetInfo(const std::string& triple) : TargetInfo(triple) { 3339 // FIXME: Support Sparc quad-precision long double? 3340 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3341 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32"; 3342 } 3343 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 3344 StringRef Name, 3345 bool Enabled) const { 3346 if (Name == "soft-float") 3347 Features[Name] = Enabled; 3348 else 3349 return false; 3350 3351 return true; 3352 } 3353 virtual void HandleTargetFeatures(std::vector<std::string> &Features) { 3354 SoftFloat = false; 3355 for (unsigned i = 0, e = Features.size(); i != e; ++i) 3356 if (Features[i] == "+soft-float") 3357 SoftFloat = true; 3358 } 3359 virtual void getTargetDefines(const LangOptions &Opts, 3360 MacroBuilder &Builder) const { 3361 DefineStd(Builder, "sparc", Opts); 3362 Builder.defineMacro("__sparcv8"); 3363 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3364 3365 if (SoftFloat) 3366 Builder.defineMacro("SOFT_FLOAT", "1"); 3367 } 3368 3369 virtual bool hasFeature(StringRef Feature) const { 3370 return llvm::StringSwitch<bool>(Feature) 3371 .Case("softfloat", SoftFloat) 3372 .Case("sparc", true) 3373 .Default(false); 3374 } 3375 3376 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3377 unsigned &NumRecords) const { 3378 // FIXME: Implement! 3379 } 3380 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3381 return TargetInfo::VoidPtrBuiltinVaList; 3382 } 3383 virtual void getGCCRegNames(const char * const *&Names, 3384 unsigned &NumNames) const; 3385 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3386 unsigned &NumAliases) const; 3387 virtual bool validateAsmConstraint(const char *&Name, 3388 TargetInfo::ConstraintInfo &info) const { 3389 // FIXME: Implement! 3390 return false; 3391 } 3392 virtual const char *getClobbers() const { 3393 // FIXME: Implement! 3394 return ""; 3395 } 3396 }; 3397 3398 const char * const SparcV8TargetInfo::GCCRegNames[] = { 3399 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 3400 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 3401 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 3402 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 3403 }; 3404 3405 void SparcV8TargetInfo::getGCCRegNames(const char * const *&Names, 3406 unsigned &NumNames) const { 3407 Names = GCCRegNames; 3408 NumNames = llvm::array_lengthof(GCCRegNames); 3409 } 3410 3411 const TargetInfo::GCCRegAlias SparcV8TargetInfo::GCCRegAliases[] = { 3412 { { "g0" }, "r0" }, 3413 { { "g1" }, "r1" }, 3414 { { "g2" }, "r2" }, 3415 { { "g3" }, "r3" }, 3416 { { "g4" }, "r4" }, 3417 { { "g5" }, "r5" }, 3418 { { "g6" }, "r6" }, 3419 { { "g7" }, "r7" }, 3420 { { "o0" }, "r8" }, 3421 { { "o1" }, "r9" }, 3422 { { "o2" }, "r10" }, 3423 { { "o3" }, "r11" }, 3424 { { "o4" }, "r12" }, 3425 { { "o5" }, "r13" }, 3426 { { "o6", "sp" }, "r14" }, 3427 { { "o7" }, "r15" }, 3428 { { "l0" }, "r16" }, 3429 { { "l1" }, "r17" }, 3430 { { "l2" }, "r18" }, 3431 { { "l3" }, "r19" }, 3432 { { "l4" }, "r20" }, 3433 { { "l5" }, "r21" }, 3434 { { "l6" }, "r22" }, 3435 { { "l7" }, "r23" }, 3436 { { "i0" }, "r24" }, 3437 { { "i1" }, "r25" }, 3438 { { "i2" }, "r26" }, 3439 { { "i3" }, "r27" }, 3440 { { "i4" }, "r28" }, 3441 { { "i5" }, "r29" }, 3442 { { "i6", "fp" }, "r30" }, 3443 { { "i7" }, "r31" }, 3444 }; 3445 3446 void SparcV8TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3447 unsigned &NumAliases) const { 3448 Aliases = GCCRegAliases; 3449 NumAliases = llvm::array_lengthof(GCCRegAliases); 3450 } 3451 } // end anonymous namespace. 3452 3453 namespace { 3454 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> { 3455 public: 3456 AuroraUXSparcV8TargetInfo(const std::string& triple) : 3457 AuroraUXTargetInfo<SparcV8TargetInfo>(triple) { 3458 SizeType = UnsignedInt; 3459 PtrDiffType = SignedInt; 3460 } 3461 }; 3462 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 3463 public: 3464 SolarisSparcV8TargetInfo(const std::string& triple) : 3465 SolarisTargetInfo<SparcV8TargetInfo>(triple) { 3466 SizeType = UnsignedInt; 3467 PtrDiffType = SignedInt; 3468 } 3469 }; 3470 } // end anonymous namespace. 3471 3472 namespace { 3473 class MSP430TargetInfo : public TargetInfo { 3474 static const char * const GCCRegNames[]; 3475 public: 3476 MSP430TargetInfo(const std::string& triple) : TargetInfo(triple) { 3477 BigEndian = false; 3478 TLSSupported = false; 3479 IntWidth = 16; IntAlign = 16; 3480 LongWidth = 32; LongLongWidth = 64; 3481 LongAlign = LongLongAlign = 16; 3482 PointerWidth = 16; PointerAlign = 16; 3483 SuitableAlign = 16; 3484 SizeType = UnsignedInt; 3485 IntMaxType = SignedLong; 3486 UIntMaxType = UnsignedLong; 3487 IntPtrType = SignedShort; 3488 PtrDiffType = SignedInt; 3489 SigAtomicType = SignedLong; 3490 DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"; 3491 } 3492 virtual void getTargetDefines(const LangOptions &Opts, 3493 MacroBuilder &Builder) const { 3494 Builder.defineMacro("MSP430"); 3495 Builder.defineMacro("__MSP430__"); 3496 // FIXME: defines for different 'flavours' of MCU 3497 } 3498 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3499 unsigned &NumRecords) const { 3500 // FIXME: Implement. 3501 Records = 0; 3502 NumRecords = 0; 3503 } 3504 virtual bool hasFeature(StringRef Feature) const { 3505 return Feature == "msp430"; 3506 } 3507 virtual void getGCCRegNames(const char * const *&Names, 3508 unsigned &NumNames) const; 3509 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3510 unsigned &NumAliases) const { 3511 // No aliases. 3512 Aliases = 0; 3513 NumAliases = 0; 3514 } 3515 virtual bool validateAsmConstraint(const char *&Name, 3516 TargetInfo::ConstraintInfo &info) const { 3517 // No target constraints for now. 3518 return false; 3519 } 3520 virtual const char *getClobbers() const { 3521 // FIXME: Is this really right? 3522 return ""; 3523 } 3524 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3525 // FIXME: implement 3526 return TargetInfo::CharPtrBuiltinVaList; 3527 } 3528 }; 3529 3530 const char * const MSP430TargetInfo::GCCRegNames[] = { 3531 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 3532 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 3533 }; 3534 3535 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 3536 unsigned &NumNames) const { 3537 Names = GCCRegNames; 3538 NumNames = llvm::array_lengthof(GCCRegNames); 3539 } 3540 } 3541 3542 namespace { 3543 3544 // LLVM and Clang cannot be used directly to output native binaries for 3545 // target, but is used to compile C code to llvm bitcode with correct 3546 // type and alignment information. 3547 // 3548 // TCE uses the llvm bitcode as input and uses it for generating customized 3549 // target processor and program binary. TCE co-design environment is 3550 // publicly available in http://tce.cs.tut.fi 3551 3552 static const unsigned TCEOpenCLAddrSpaceMap[] = { 3553 3, // opencl_global 3554 4, // opencl_local 3555 5, // opencl_constant 3556 0, // cuda_device 3557 0, // cuda_constant 3558 0 // cuda_shared 3559 }; 3560 3561 class TCETargetInfo : public TargetInfo{ 3562 public: 3563 TCETargetInfo(const std::string& triple) : TargetInfo(triple) { 3564 TLSSupported = false; 3565 IntWidth = 32; 3566 LongWidth = LongLongWidth = 32; 3567 PointerWidth = 32; 3568 IntAlign = 32; 3569 LongAlign = LongLongAlign = 32; 3570 PointerAlign = 32; 3571 SuitableAlign = 32; 3572 SizeType = UnsignedInt; 3573 IntMaxType = SignedLong; 3574 UIntMaxType = UnsignedLong; 3575 IntPtrType = SignedInt; 3576 PtrDiffType = SignedInt; 3577 FloatWidth = 32; 3578 FloatAlign = 32; 3579 DoubleWidth = 32; 3580 DoubleAlign = 32; 3581 LongDoubleWidth = 32; 3582 LongDoubleAlign = 32; 3583 FloatFormat = &llvm::APFloat::IEEEsingle; 3584 DoubleFormat = &llvm::APFloat::IEEEsingle; 3585 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 3586 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-" 3587 "i16:16:32-i32:32:32-i64:32:32-" 3588 "f32:32:32-f64:32:32-v64:32:32-" 3589 "v128:32:32-a0:0:32-n32"; 3590 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 3591 } 3592 3593 virtual void getTargetDefines(const LangOptions &Opts, 3594 MacroBuilder &Builder) const { 3595 DefineStd(Builder, "tce", Opts); 3596 Builder.defineMacro("__TCE__"); 3597 Builder.defineMacro("__TCE_V1__"); 3598 } 3599 virtual bool hasFeature(StringRef Feature) const { 3600 return Feature == "tce"; 3601 } 3602 3603 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3604 unsigned &NumRecords) const {} 3605 virtual const char *getClobbers() const { 3606 return ""; 3607 } 3608 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3609 return TargetInfo::VoidPtrBuiltinVaList; 3610 } 3611 virtual void getGCCRegNames(const char * const *&Names, 3612 unsigned &NumNames) const {} 3613 virtual bool validateAsmConstraint(const char *&Name, 3614 TargetInfo::ConstraintInfo &info) const { 3615 return true; 3616 } 3617 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3618 unsigned &NumAliases) const {} 3619 }; 3620 } 3621 3622 namespace { 3623 class MipsTargetInfoBase : public TargetInfo { 3624 static const Builtin::Info BuiltinInfo[]; 3625 std::string CPU; 3626 bool IsMips16; 3627 enum MipsFloatABI { 3628 HardFloat, SingleFloat, SoftFloat 3629 } FloatABI; 3630 enum DspRevEnum { 3631 NoDSP, DSP1, DSP2 3632 } DspRev; 3633 3634 protected: 3635 std::string ABI; 3636 3637 public: 3638 MipsTargetInfoBase(const std::string& triple, 3639 const std::string& ABIStr, 3640 const std::string& CPUStr) 3641 : TargetInfo(triple), 3642 CPU(CPUStr), 3643 IsMips16(false), 3644 FloatABI(HardFloat), 3645 DspRev(NoDSP), 3646 ABI(ABIStr) 3647 {} 3648 3649 virtual const char *getABI() const { return ABI.c_str(); } 3650 virtual bool setABI(const std::string &Name) = 0; 3651 virtual bool setCPU(const std::string &Name) { 3652 CPU = Name; 3653 return true; 3654 } 3655 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 3656 Features[ABI] = true; 3657 Features[CPU] = true; 3658 } 3659 3660 virtual void getArchDefines(const LangOptions &Opts, 3661 MacroBuilder &Builder) const { 3662 switch (FloatABI) { 3663 case HardFloat: 3664 Builder.defineMacro("__mips_hard_float", Twine(1)); 3665 break; 3666 case SingleFloat: 3667 Builder.defineMacro("__mips_hard_float", Twine(1)); 3668 Builder.defineMacro("__mips_single_float", Twine(1)); 3669 break; 3670 case SoftFloat: 3671 Builder.defineMacro("__mips_soft_float", Twine(1)); 3672 break; 3673 } 3674 3675 if (IsMips16) 3676 Builder.defineMacro("__mips16", Twine(1)); 3677 3678 switch (DspRev) { 3679 default: 3680 break; 3681 case DSP1: 3682 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 3683 Builder.defineMacro("__mips_dsp", Twine(1)); 3684 break; 3685 case DSP2: 3686 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 3687 Builder.defineMacro("__mips_dspr2", Twine(1)); 3688 Builder.defineMacro("__mips_dsp", Twine(1)); 3689 break; 3690 } 3691 3692 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 3693 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 3694 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 3695 } 3696 3697 virtual void getTargetDefines(const LangOptions &Opts, 3698 MacroBuilder &Builder) const = 0; 3699 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3700 unsigned &NumRecords) const { 3701 Records = BuiltinInfo; 3702 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 3703 } 3704 virtual bool hasFeature(StringRef Feature) const { 3705 return Feature == "mips"; 3706 } 3707 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3708 return TargetInfo::VoidPtrBuiltinVaList; 3709 } 3710 virtual void getGCCRegNames(const char * const *&Names, 3711 unsigned &NumNames) const { 3712 static const char * const GCCRegNames[] = { 3713 // CPU register names 3714 // Must match second column of GCCRegAliases 3715 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 3716 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 3717 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 3718 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 3719 // Floating point register names 3720 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 3721 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 3722 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 3723 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 3724 // Hi/lo and condition register names 3725 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 3726 "$fcc5","$fcc6","$fcc7" 3727 }; 3728 Names = GCCRegNames; 3729 NumNames = llvm::array_lengthof(GCCRegNames); 3730 } 3731 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3732 unsigned &NumAliases) const = 0; 3733 virtual bool validateAsmConstraint(const char *&Name, 3734 TargetInfo::ConstraintInfo &Info) const { 3735 switch (*Name) { 3736 default: 3737 return false; 3738 3739 case 'r': // CPU registers. 3740 case 'd': // Equivalent to "r" unless generating MIPS16 code. 3741 case 'y': // Equivalent to "r", backwards compatibility only. 3742 case 'f': // floating-point registers. 3743 case 'c': // $25 for indirect jumps 3744 case 'l': // lo register 3745 case 'x': // hilo register pair 3746 Info.setAllowsRegister(); 3747 return true; 3748 } 3749 } 3750 3751 virtual const char *getClobbers() const { 3752 // FIXME: Implement! 3753 return ""; 3754 } 3755 3756 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 3757 StringRef Name, 3758 bool Enabled) const { 3759 if (Name == "soft-float" || Name == "single-float" || 3760 Name == "o32" || Name == "n32" || Name == "n64" || Name == "eabi" || 3761 Name == "mips32" || Name == "mips32r2" || 3762 Name == "mips64" || Name == "mips64r2" || 3763 Name == "mips16" || Name == "dsp" || Name == "dspr2") { 3764 Features[Name] = Enabled; 3765 return true; 3766 } 3767 return false; 3768 } 3769 3770 virtual void HandleTargetFeatures(std::vector<std::string> &Features) { 3771 IsMips16 = false; 3772 FloatABI = HardFloat; 3773 DspRev = NoDSP; 3774 3775 for (std::vector<std::string>::iterator it = Features.begin(), 3776 ie = Features.end(); it != ie; ++it) { 3777 if (*it == "+single-float") 3778 FloatABI = SingleFloat; 3779 else if (*it == "+soft-float") 3780 FloatABI = SoftFloat; 3781 else if (*it == "+mips16") 3782 IsMips16 = true; 3783 else if (*it == "+dsp") 3784 DspRev = std::max(DspRev, DSP1); 3785 else if (*it == "+dspr2") 3786 DspRev = std::max(DspRev, DSP2); 3787 } 3788 3789 // Remove front-end specific option. 3790 std::vector<std::string>::iterator it = 3791 std::find(Features.begin(), Features.end(), "+soft-float"); 3792 if (it != Features.end()) 3793 Features.erase(it); 3794 } 3795 }; 3796 3797 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 3798 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3799 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3800 ALL_LANGUAGES }, 3801 #include "clang/Basic/BuiltinsMips.def" 3802 }; 3803 3804 class Mips32TargetInfoBase : public MipsTargetInfoBase { 3805 public: 3806 Mips32TargetInfoBase(const std::string& triple) : 3807 MipsTargetInfoBase(triple, "o32", "mips32") { 3808 SizeType = UnsignedInt; 3809 PtrDiffType = SignedInt; 3810 } 3811 virtual bool setABI(const std::string &Name) { 3812 if ((Name == "o32") || (Name == "eabi")) { 3813 ABI = Name; 3814 return true; 3815 } else 3816 return false; 3817 } 3818 virtual void getArchDefines(const LangOptions &Opts, 3819 MacroBuilder &Builder) const { 3820 MipsTargetInfoBase::getArchDefines(Opts, Builder); 3821 3822 if (ABI == "o32") { 3823 Builder.defineMacro("__mips_o32"); 3824 Builder.defineMacro("_ABIO32", "1"); 3825 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 3826 } 3827 else if (ABI == "eabi") 3828 Builder.defineMacro("__mips_eabi"); 3829 else 3830 llvm_unreachable("Invalid ABI for Mips32."); 3831 } 3832 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3833 unsigned &NumAliases) const { 3834 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 3835 { { "at" }, "$1" }, 3836 { { "v0" }, "$2" }, 3837 { { "v1" }, "$3" }, 3838 { { "a0" }, "$4" }, 3839 { { "a1" }, "$5" }, 3840 { { "a2" }, "$6" }, 3841 { { "a3" }, "$7" }, 3842 { { "t0" }, "$8" }, 3843 { { "t1" }, "$9" }, 3844 { { "t2" }, "$10" }, 3845 { { "t3" }, "$11" }, 3846 { { "t4" }, "$12" }, 3847 { { "t5" }, "$13" }, 3848 { { "t6" }, "$14" }, 3849 { { "t7" }, "$15" }, 3850 { { "s0" }, "$16" }, 3851 { { "s1" }, "$17" }, 3852 { { "s2" }, "$18" }, 3853 { { "s3" }, "$19" }, 3854 { { "s4" }, "$20" }, 3855 { { "s5" }, "$21" }, 3856 { { "s6" }, "$22" }, 3857 { { "s7" }, "$23" }, 3858 { { "t8" }, "$24" }, 3859 { { "t9" }, "$25" }, 3860 { { "k0" }, "$26" }, 3861 { { "k1" }, "$27" }, 3862 { { "gp" }, "$28" }, 3863 { { "sp","$sp" }, "$29" }, 3864 { { "fp","$fp" }, "$30" }, 3865 { { "ra" }, "$31" } 3866 }; 3867 Aliases = GCCRegAliases; 3868 NumAliases = llvm::array_lengthof(GCCRegAliases); 3869 } 3870 }; 3871 3872 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 3873 public: 3874 Mips32EBTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) { 3875 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 3876 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32"; 3877 } 3878 virtual void getTargetDefines(const LangOptions &Opts, 3879 MacroBuilder &Builder) const { 3880 DefineStd(Builder, "mips", Opts); 3881 Builder.defineMacro("_mips"); 3882 DefineStd(Builder, "MIPSEB", Opts); 3883 Builder.defineMacro("_MIPSEB"); 3884 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3885 getArchDefines(Opts, Builder); 3886 } 3887 }; 3888 3889 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 3890 public: 3891 Mips32ELTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) { 3892 BigEndian = false; 3893 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 3894 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32"; 3895 } 3896 virtual void getTargetDefines(const LangOptions &Opts, 3897 MacroBuilder &Builder) const { 3898 DefineStd(Builder, "mips", Opts); 3899 Builder.defineMacro("_mips"); 3900 DefineStd(Builder, "MIPSEL", Opts); 3901 Builder.defineMacro("_MIPSEL"); 3902 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3903 getArchDefines(Opts, Builder); 3904 } 3905 }; 3906 3907 class Mips64TargetInfoBase : public MipsTargetInfoBase { 3908 virtual void SetDescriptionString(const std::string &Name) = 0; 3909 public: 3910 Mips64TargetInfoBase(const std::string& triple) : 3911 MipsTargetInfoBase(triple, "n64", "mips64") { 3912 LongWidth = LongAlign = 64; 3913 PointerWidth = PointerAlign = 64; 3914 LongDoubleWidth = LongDoubleAlign = 128; 3915 LongDoubleFormat = &llvm::APFloat::IEEEquad; 3916 SuitableAlign = 128; 3917 } 3918 virtual bool setABI(const std::string &Name) { 3919 SetDescriptionString(Name); 3920 3921 if (Name != "n32" && Name != "n64") 3922 return false; 3923 3924 ABI = Name; 3925 3926 if (Name == "n32") { 3927 LongWidth = LongAlign = 32; 3928 PointerWidth = PointerAlign = 32; 3929 } 3930 3931 return true; 3932 } 3933 virtual void getArchDefines(const LangOptions &Opts, 3934 MacroBuilder &Builder) const { 3935 MipsTargetInfoBase::getArchDefines(Opts, Builder); 3936 3937 if (ABI == "n32") { 3938 Builder.defineMacro("__mips_n32"); 3939 Builder.defineMacro("_ABIN32", "2"); 3940 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 3941 } 3942 else if (ABI == "n64") { 3943 Builder.defineMacro("__mips_n64"); 3944 Builder.defineMacro("_ABI64", "3"); 3945 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 3946 } 3947 else 3948 llvm_unreachable("Invalid ABI for Mips64."); 3949 } 3950 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3951 unsigned &NumAliases) const { 3952 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 3953 { { "at" }, "$1" }, 3954 { { "v0" }, "$2" }, 3955 { { "v1" }, "$3" }, 3956 { { "a0" }, "$4" }, 3957 { { "a1" }, "$5" }, 3958 { { "a2" }, "$6" }, 3959 { { "a3" }, "$7" }, 3960 { { "a4" }, "$8" }, 3961 { { "a5" }, "$9" }, 3962 { { "a6" }, "$10" }, 3963 { { "a7" }, "$11" }, 3964 { { "t0" }, "$12" }, 3965 { { "t1" }, "$13" }, 3966 { { "t2" }, "$14" }, 3967 { { "t3" }, "$15" }, 3968 { { "s0" }, "$16" }, 3969 { { "s1" }, "$17" }, 3970 { { "s2" }, "$18" }, 3971 { { "s3" }, "$19" }, 3972 { { "s4" }, "$20" }, 3973 { { "s5" }, "$21" }, 3974 { { "s6" }, "$22" }, 3975 { { "s7" }, "$23" }, 3976 { { "t8" }, "$24" }, 3977 { { "t9" }, "$25" }, 3978 { { "k0" }, "$26" }, 3979 { { "k1" }, "$27" }, 3980 { { "gp" }, "$28" }, 3981 { { "sp","$sp" }, "$29" }, 3982 { { "fp","$fp" }, "$30" }, 3983 { { "ra" }, "$31" } 3984 }; 3985 Aliases = GCCRegAliases; 3986 NumAliases = llvm::array_lengthof(GCCRegAliases); 3987 } 3988 }; 3989 3990 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 3991 virtual void SetDescriptionString(const std::string &Name) { 3992 // Change DescriptionString only if ABI is n32. 3993 if (Name == "n32") 3994 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 3995 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 3996 "v64:64:64-n32"; 3997 } 3998 public: 3999 Mips64EBTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) { 4000 // Default ABI is n64. 4001 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4002 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 4003 "v64:64:64-n32"; 4004 } 4005 virtual void getTargetDefines(const LangOptions &Opts, 4006 MacroBuilder &Builder) const { 4007 DefineStd(Builder, "mips", Opts); 4008 Builder.defineMacro("_mips"); 4009 DefineStd(Builder, "MIPSEB", Opts); 4010 Builder.defineMacro("_MIPSEB"); 4011 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4012 getArchDefines(Opts, Builder); 4013 } 4014 }; 4015 4016 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 4017 virtual void SetDescriptionString(const std::string &Name) { 4018 // Change DescriptionString only if ABI is n32. 4019 if (Name == "n32") 4020 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4021 "i64:64:64-f32:32:32-f64:64:64-f128:128:128" 4022 "-v64:64:64-n32"; 4023 } 4024 public: 4025 Mips64ELTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) { 4026 // Default ABI is n64. 4027 BigEndian = false; 4028 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4029 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 4030 "v64:64:64-n32"; 4031 } 4032 virtual void getTargetDefines(const LangOptions &Opts, 4033 MacroBuilder &Builder) const { 4034 DefineStd(Builder, "mips", Opts); 4035 Builder.defineMacro("_mips"); 4036 DefineStd(Builder, "MIPSEL", Opts); 4037 Builder.defineMacro("_MIPSEL"); 4038 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4039 getArchDefines(Opts, Builder); 4040 } 4041 }; 4042 } // end anonymous namespace. 4043 4044 namespace { 4045 class PNaClTargetInfo : public TargetInfo { 4046 public: 4047 PNaClTargetInfo(const std::string& triple) : TargetInfo(triple) { 4048 BigEndian = false; 4049 this->UserLabelPrefix = ""; 4050 this->LongAlign = 32; 4051 this->LongWidth = 32; 4052 this->PointerAlign = 32; 4053 this->PointerWidth = 32; 4054 this->IntMaxType = TargetInfo::SignedLongLong; 4055 this->UIntMaxType = TargetInfo::UnsignedLongLong; 4056 this->Int64Type = TargetInfo::SignedLongLong; 4057 this->DoubleAlign = 64; 4058 this->LongDoubleWidth = 64; 4059 this->LongDoubleAlign = 64; 4060 this->SizeType = TargetInfo::UnsignedInt; 4061 this->PtrDiffType = TargetInfo::SignedInt; 4062 this->IntPtrType = TargetInfo::SignedInt; 4063 this->RegParmMax = 2; 4064 DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 4065 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32"; 4066 } 4067 4068 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 4069 } 4070 virtual void getArchDefines(const LangOptions &Opts, 4071 MacroBuilder &Builder) const { 4072 Builder.defineMacro("__le32__"); 4073 Builder.defineMacro("__pnacl__"); 4074 } 4075 virtual void getTargetDefines(const LangOptions &Opts, 4076 MacroBuilder &Builder) const { 4077 DefineStd(Builder, "unix", Opts); 4078 Builder.defineMacro("__ELF__"); 4079 if (Opts.POSIXThreads) 4080 Builder.defineMacro("_REENTRANT"); 4081 if (Opts.CPlusPlus) 4082 Builder.defineMacro("_GNU_SOURCE"); 4083 4084 Builder.defineMacro("__LITTLE_ENDIAN__"); 4085 Builder.defineMacro("__native_client__"); 4086 getArchDefines(Opts, Builder); 4087 } 4088 virtual bool hasFeature(StringRef Feature) const { 4089 return Feature == "pnacl"; 4090 } 4091 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4092 unsigned &NumRecords) const { 4093 } 4094 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4095 return TargetInfo::PNaClABIBuiltinVaList; 4096 } 4097 virtual void getGCCRegNames(const char * const *&Names, 4098 unsigned &NumNames) const; 4099 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4100 unsigned &NumAliases) const; 4101 virtual bool validateAsmConstraint(const char *&Name, 4102 TargetInfo::ConstraintInfo &Info) const { 4103 return false; 4104 } 4105 4106 virtual const char *getClobbers() const { 4107 return ""; 4108 } 4109 }; 4110 4111 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 4112 unsigned &NumNames) const { 4113 Names = NULL; 4114 NumNames = 0; 4115 } 4116 4117 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4118 unsigned &NumAliases) const { 4119 Aliases = NULL; 4120 NumAliases = 0; 4121 } 4122 } // end anonymous namespace. 4123 4124 4125 //===----------------------------------------------------------------------===// 4126 // Driver code 4127 //===----------------------------------------------------------------------===// 4128 4129 static TargetInfo *AllocateTarget(const std::string &T) { 4130 llvm::Triple Triple(T); 4131 llvm::Triple::OSType os = Triple.getOS(); 4132 4133 switch (Triple.getArch()) { 4134 default: 4135 return NULL; 4136 4137 case llvm::Triple::hexagon: 4138 return new HexagonTargetInfo(T); 4139 4140 case llvm::Triple::arm: 4141 case llvm::Triple::thumb: 4142 if (Triple.isOSDarwin()) 4143 return new DarwinARMTargetInfo(T); 4144 4145 switch (os) { 4146 case llvm::Triple::Linux: 4147 return new LinuxTargetInfo<ARMTargetInfo>(T); 4148 case llvm::Triple::FreeBSD: 4149 return new FreeBSDTargetInfo<ARMTargetInfo>(T); 4150 case llvm::Triple::NetBSD: 4151 return new NetBSDTargetInfo<ARMTargetInfo>(T); 4152 case llvm::Triple::RTEMS: 4153 return new RTEMSTargetInfo<ARMTargetInfo>(T); 4154 default: 4155 return new ARMTargetInfo(T); 4156 } 4157 4158 case llvm::Triple::msp430: 4159 return new MSP430TargetInfo(T); 4160 4161 case llvm::Triple::mips: 4162 switch (os) { 4163 case llvm::Triple::Linux: 4164 return new LinuxTargetInfo<Mips32EBTargetInfo>(T); 4165 case llvm::Triple::RTEMS: 4166 return new RTEMSTargetInfo<Mips32EBTargetInfo>(T); 4167 case llvm::Triple::FreeBSD: 4168 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(T); 4169 case llvm::Triple::NetBSD: 4170 return new NetBSDTargetInfo<Mips32EBTargetInfo>(T); 4171 default: 4172 return new Mips32EBTargetInfo(T); 4173 } 4174 4175 case llvm::Triple::mipsel: 4176 switch (os) { 4177 case llvm::Triple::Linux: 4178 return new LinuxTargetInfo<Mips32ELTargetInfo>(T); 4179 case llvm::Triple::RTEMS: 4180 return new RTEMSTargetInfo<Mips32ELTargetInfo>(T); 4181 case llvm::Triple::FreeBSD: 4182 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(T); 4183 case llvm::Triple::NetBSD: 4184 return new NetBSDTargetInfo<Mips32ELTargetInfo>(T); 4185 default: 4186 return new Mips32ELTargetInfo(T); 4187 } 4188 4189 case llvm::Triple::mips64: 4190 switch (os) { 4191 case llvm::Triple::Linux: 4192 return new LinuxTargetInfo<Mips64EBTargetInfo>(T); 4193 case llvm::Triple::RTEMS: 4194 return new RTEMSTargetInfo<Mips64EBTargetInfo>(T); 4195 case llvm::Triple::FreeBSD: 4196 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(T); 4197 case llvm::Triple::NetBSD: 4198 return new NetBSDTargetInfo<Mips64EBTargetInfo>(T); 4199 default: 4200 return new Mips64EBTargetInfo(T); 4201 } 4202 4203 case llvm::Triple::mips64el: 4204 switch (os) { 4205 case llvm::Triple::Linux: 4206 return new LinuxTargetInfo<Mips64ELTargetInfo>(T); 4207 case llvm::Triple::RTEMS: 4208 return new RTEMSTargetInfo<Mips64ELTargetInfo>(T); 4209 case llvm::Triple::FreeBSD: 4210 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(T); 4211 case llvm::Triple::NetBSD: 4212 return new NetBSDTargetInfo<Mips64ELTargetInfo>(T); 4213 default: 4214 return new Mips64ELTargetInfo(T); 4215 } 4216 4217 case llvm::Triple::le32: 4218 switch (os) { 4219 case llvm::Triple::NativeClient: 4220 return new PNaClTargetInfo(T); 4221 default: 4222 return NULL; 4223 } 4224 4225 case llvm::Triple::ppc: 4226 if (Triple.isOSDarwin()) 4227 return new DarwinPPC32TargetInfo(T); 4228 switch (os) { 4229 case llvm::Triple::Linux: 4230 return new LinuxTargetInfo<PPC32TargetInfo>(T); 4231 case llvm::Triple::FreeBSD: 4232 return new FreeBSDTargetInfo<PPC32TargetInfo>(T); 4233 case llvm::Triple::NetBSD: 4234 return new NetBSDTargetInfo<PPC32TargetInfo>(T); 4235 case llvm::Triple::RTEMS: 4236 return new RTEMSTargetInfo<PPC32TargetInfo>(T); 4237 default: 4238 return new PPC32TargetInfo(T); 4239 } 4240 4241 case llvm::Triple::ppc64: 4242 if (Triple.isOSDarwin()) 4243 return new DarwinPPC64TargetInfo(T); 4244 switch (os) { 4245 case llvm::Triple::Linux: 4246 return new LinuxTargetInfo<PPC64TargetInfo>(T); 4247 case llvm::Triple::Lv2: 4248 return new PS3PPUTargetInfo<PPC64TargetInfo>(T); 4249 case llvm::Triple::FreeBSD: 4250 return new FreeBSDTargetInfo<PPC64TargetInfo>(T); 4251 case llvm::Triple::NetBSD: 4252 return new NetBSDTargetInfo<PPC64TargetInfo>(T); 4253 default: 4254 return new PPC64TargetInfo(T); 4255 } 4256 4257 case llvm::Triple::nvptx: 4258 return new NVPTX32TargetInfo(T); 4259 case llvm::Triple::nvptx64: 4260 return new NVPTX64TargetInfo(T); 4261 4262 case llvm::Triple::mblaze: 4263 return new MBlazeTargetInfo(T); 4264 4265 case llvm::Triple::sparc: 4266 switch (os) { 4267 case llvm::Triple::Linux: 4268 return new LinuxTargetInfo<SparcV8TargetInfo>(T); 4269 case llvm::Triple::AuroraUX: 4270 return new AuroraUXSparcV8TargetInfo(T); 4271 case llvm::Triple::Solaris: 4272 return new SolarisSparcV8TargetInfo(T); 4273 case llvm::Triple::NetBSD: 4274 return new NetBSDTargetInfo<SparcV8TargetInfo>(T); 4275 case llvm::Triple::RTEMS: 4276 return new RTEMSTargetInfo<SparcV8TargetInfo>(T); 4277 default: 4278 return new SparcV8TargetInfo(T); 4279 } 4280 4281 // FIXME: Need a real SPU target. 4282 case llvm::Triple::cellspu: 4283 return new PS3SPUTargetInfo<PPC64TargetInfo>(T); 4284 4285 case llvm::Triple::tce: 4286 return new TCETargetInfo(T); 4287 4288 case llvm::Triple::x86: 4289 if (Triple.isOSDarwin()) 4290 return new DarwinI386TargetInfo(T); 4291 4292 switch (os) { 4293 case llvm::Triple::AuroraUX: 4294 return new AuroraUXTargetInfo<X86_32TargetInfo>(T); 4295 case llvm::Triple::Linux: 4296 return new LinuxTargetInfo<X86_32TargetInfo>(T); 4297 case llvm::Triple::DragonFly: 4298 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(T); 4299 case llvm::Triple::NetBSD: 4300 return new NetBSDI386TargetInfo(T); 4301 case llvm::Triple::OpenBSD: 4302 return new OpenBSDI386TargetInfo(T); 4303 case llvm::Triple::FreeBSD: 4304 return new FreeBSDTargetInfo<X86_32TargetInfo>(T); 4305 case llvm::Triple::Minix: 4306 return new MinixTargetInfo<X86_32TargetInfo>(T); 4307 case llvm::Triple::Solaris: 4308 return new SolarisTargetInfo<X86_32TargetInfo>(T); 4309 case llvm::Triple::Cygwin: 4310 return new CygwinX86_32TargetInfo(T); 4311 case llvm::Triple::MinGW32: 4312 return new MinGWX86_32TargetInfo(T); 4313 case llvm::Triple::Win32: 4314 return new VisualStudioWindowsX86_32TargetInfo(T); 4315 case llvm::Triple::Haiku: 4316 return new HaikuX86_32TargetInfo(T); 4317 case llvm::Triple::RTEMS: 4318 return new RTEMSX86_32TargetInfo(T); 4319 default: 4320 return new X86_32TargetInfo(T); 4321 } 4322 4323 case llvm::Triple::x86_64: 4324 if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO) 4325 return new DarwinX86_64TargetInfo(T); 4326 4327 switch (os) { 4328 case llvm::Triple::AuroraUX: 4329 return new AuroraUXTargetInfo<X86_64TargetInfo>(T); 4330 case llvm::Triple::Linux: 4331 return new LinuxTargetInfo<X86_64TargetInfo>(T); 4332 case llvm::Triple::DragonFly: 4333 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(T); 4334 case llvm::Triple::NetBSD: 4335 return new NetBSDTargetInfo<X86_64TargetInfo>(T); 4336 case llvm::Triple::OpenBSD: 4337 return new OpenBSDX86_64TargetInfo(T); 4338 case llvm::Triple::FreeBSD: 4339 return new FreeBSDTargetInfo<X86_64TargetInfo>(T); 4340 case llvm::Triple::Solaris: 4341 return new SolarisTargetInfo<X86_64TargetInfo>(T); 4342 case llvm::Triple::MinGW32: 4343 return new MinGWX86_64TargetInfo(T); 4344 case llvm::Triple::Win32: // This is what Triple.h supports now. 4345 return new VisualStudioWindowsX86_64TargetInfo(T); 4346 default: 4347 return new X86_64TargetInfo(T); 4348 } 4349 } 4350 } 4351 4352 /// CreateTargetInfo - Return the target info object for the specified target 4353 /// triple. 4354 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 4355 TargetOptions &Opts) { 4356 llvm::Triple Triple(Opts.Triple); 4357 4358 // Construct the target 4359 OwningPtr<TargetInfo> Target(AllocateTarget(Triple.str())); 4360 if (!Target) { 4361 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 4362 return 0; 4363 } 4364 4365 // Set the target CPU if specified. 4366 if (!Opts.CPU.empty() && !Target->setCPU(Opts.CPU)) { 4367 Diags.Report(diag::err_target_unknown_cpu) << Opts.CPU; 4368 return 0; 4369 } 4370 4371 // Set the target ABI if specified. 4372 if (!Opts.ABI.empty() && !Target->setABI(Opts.ABI)) { 4373 Diags.Report(diag::err_target_unknown_abi) << Opts.ABI; 4374 return 0; 4375 } 4376 4377 // Set the target C++ ABI. 4378 if (!Opts.CXXABI.empty() && !Target->setCXXABI(Opts.CXXABI)) { 4379 Diags.Report(diag::err_target_unknown_cxxabi) << Opts.CXXABI; 4380 return 0; 4381 } 4382 4383 // Compute the default target features, we need the target to handle this 4384 // because features may have dependencies on one another. 4385 llvm::StringMap<bool> Features; 4386 Target->getDefaultFeatures(Features); 4387 4388 // Apply the user specified deltas. 4389 // First the enables. 4390 for (std::vector<std::string>::const_iterator it = Opts.Features.begin(), 4391 ie = Opts.Features.end(); it != ie; ++it) { 4392 const char *Name = it->c_str(); 4393 4394 if (Name[0] != '+') 4395 continue; 4396 4397 // Apply the feature via the target. 4398 if (!Target->setFeatureEnabled(Features, Name + 1, true)) { 4399 Diags.Report(diag::err_target_invalid_feature) << Name; 4400 return 0; 4401 } 4402 } 4403 4404 // Then the disables. 4405 for (std::vector<std::string>::const_iterator it = Opts.Features.begin(), 4406 ie = Opts.Features.end(); it != ie; ++it) { 4407 const char *Name = it->c_str(); 4408 4409 if (Name[0] == '+') 4410 continue; 4411 4412 // Apply the feature via the target. 4413 if (Name[0] != '-' || 4414 !Target->setFeatureEnabled(Features, Name + 1, false)) { 4415 Diags.Report(diag::err_target_invalid_feature) << Name; 4416 return 0; 4417 } 4418 } 4419 4420 // Add the features to the compile options. 4421 // 4422 // FIXME: If we are completely confident that we have the right set, we only 4423 // need to pass the minuses. 4424 Opts.Features.clear(); 4425 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 4426 ie = Features.end(); it != ie; ++it) 4427 Opts.Features.push_back((it->second ? "+" : "-") + it->first().str()); 4428 Target->HandleTargetFeatures(Opts.Features); 4429 4430 return Target.take(); 4431 } 4432