1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 // Ananas target 115 template<typename Target> 116 class AnanasTargetInfo : public OSTargetInfo<Target> { 117 protected: 118 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 119 MacroBuilder &Builder) const override { 120 // Ananas defines 121 Builder.defineMacro("__Ananas__"); 122 Builder.defineMacro("__ELF__"); 123 } 124 public: 125 AnanasTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 126 : OSTargetInfo<Target>(Triple, Opts) {} 127 }; 128 129 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 130 const llvm::Triple &Triple, 131 StringRef &PlatformName, 132 VersionTuple &PlatformMinVersion) { 133 Builder.defineMacro("__APPLE_CC__", "6000"); 134 Builder.defineMacro("__APPLE__"); 135 Builder.defineMacro("__STDC_NO_THREADS__"); 136 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 137 // AddressSanitizer doesn't play well with source fortification, which is on 138 // by default on Darwin. 139 if (Opts.Sanitize.has(SanitizerKind::Address)) 140 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 141 142 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 143 if (!Opts.ObjC1) { 144 // __weak is always defined, for use in blocks and with objc pointers. 145 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 146 Builder.defineMacro("__strong", ""); 147 Builder.defineMacro("__unsafe_unretained", ""); 148 } 149 150 if (Opts.Static) 151 Builder.defineMacro("__STATIC__"); 152 else 153 Builder.defineMacro("__DYNAMIC__"); 154 155 if (Opts.POSIXThreads) 156 Builder.defineMacro("_REENTRANT"); 157 158 // Get the platform type and version number from the triple. 159 unsigned Maj, Min, Rev; 160 if (Triple.isMacOSX()) { 161 Triple.getMacOSXVersion(Maj, Min, Rev); 162 PlatformName = "macos"; 163 } else { 164 Triple.getOSVersion(Maj, Min, Rev); 165 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 166 } 167 168 // If -target arch-pc-win32-macho option specified, we're 169 // generating code for Win32 ABI. No need to emit 170 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 171 if (PlatformName == "win32") { 172 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 173 return; 174 } 175 176 // Set the appropriate OS version define. 177 if (Triple.isiOS()) { 178 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 179 char Str[7]; 180 if (Maj < 10) { 181 Str[0] = '0' + Maj; 182 Str[1] = '0' + (Min / 10); 183 Str[2] = '0' + (Min % 10); 184 Str[3] = '0' + (Rev / 10); 185 Str[4] = '0' + (Rev % 10); 186 Str[5] = '\0'; 187 } else { 188 // Handle versions >= 10. 189 Str[0] = '0' + (Maj / 10); 190 Str[1] = '0' + (Maj % 10); 191 Str[2] = '0' + (Min / 10); 192 Str[3] = '0' + (Min % 10); 193 Str[4] = '0' + (Rev / 10); 194 Str[5] = '0' + (Rev % 10); 195 Str[6] = '\0'; 196 } 197 if (Triple.isTvOS()) 198 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 199 else 200 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 201 Str); 202 203 } else if (Triple.isWatchOS()) { 204 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 205 char Str[6]; 206 Str[0] = '0' + Maj; 207 Str[1] = '0' + (Min / 10); 208 Str[2] = '0' + (Min % 10); 209 Str[3] = '0' + (Rev / 10); 210 Str[4] = '0' + (Rev % 10); 211 Str[5] = '\0'; 212 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 213 } else if (Triple.isMacOSX()) { 214 // Note that the Driver allows versions which aren't representable in the 215 // define (because we only get a single digit for the minor and micro 216 // revision numbers). So, we limit them to the maximum representable 217 // version. 218 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 219 char Str[7]; 220 if (Maj < 10 || (Maj == 10 && Min < 10)) { 221 Str[0] = '0' + (Maj / 10); 222 Str[1] = '0' + (Maj % 10); 223 Str[2] = '0' + std::min(Min, 9U); 224 Str[3] = '0' + std::min(Rev, 9U); 225 Str[4] = '\0'; 226 } else { 227 // Handle versions > 10.9. 228 Str[0] = '0' + (Maj / 10); 229 Str[1] = '0' + (Maj % 10); 230 Str[2] = '0' + (Min / 10); 231 Str[3] = '0' + (Min % 10); 232 Str[4] = '0' + (Rev / 10); 233 Str[5] = '0' + (Rev % 10); 234 Str[6] = '\0'; 235 } 236 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 237 } 238 239 // Tell users about the kernel if there is one. 240 if (Triple.isOSDarwin()) 241 Builder.defineMacro("__MACH__"); 242 243 // The Watch ABI uses Dwarf EH. 244 if(Triple.isWatchABI()) 245 Builder.defineMacro("__ARM_DWARF_EH__"); 246 247 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 248 } 249 250 template<typename Target> 251 class DarwinTargetInfo : public OSTargetInfo<Target> { 252 protected: 253 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 254 MacroBuilder &Builder) const override { 255 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 256 this->PlatformMinVersion); 257 } 258 259 public: 260 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 261 : OSTargetInfo<Target>(Triple, Opts) { 262 // By default, no TLS, and we whitelist permitted architecture/OS 263 // combinations. 264 this->TLSSupported = false; 265 266 if (Triple.isMacOSX()) 267 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 268 else if (Triple.isiOS()) { 269 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 270 if (Triple.getArch() == llvm::Triple::x86_64 || 271 Triple.getArch() == llvm::Triple::aarch64) 272 this->TLSSupported = !Triple.isOSVersionLT(8); 273 else if (Triple.getArch() == llvm::Triple::x86 || 274 Triple.getArch() == llvm::Triple::arm || 275 Triple.getArch() == llvm::Triple::thumb) 276 this->TLSSupported = !Triple.isOSVersionLT(9); 277 } else if (Triple.isWatchOS()) 278 this->TLSSupported = !Triple.isOSVersionLT(2); 279 280 this->MCountName = "\01mcount"; 281 } 282 283 std::string isValidSectionSpecifier(StringRef SR) const override { 284 // Let MCSectionMachO validate this. 285 StringRef Segment, Section; 286 unsigned TAA, StubSize; 287 bool HasTAA; 288 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 289 TAA, HasTAA, StubSize); 290 } 291 292 const char *getStaticInitSectionSpecifier() const override { 293 // FIXME: We should return 0 when building kexts. 294 return "__TEXT,__StaticInit,regular,pure_instructions"; 295 } 296 297 /// Darwin does not support protected visibility. Darwin's "default" 298 /// is very similar to ELF's "protected"; Darwin requires a "weak" 299 /// attribute on declarations that can be dynamically replaced. 300 bool hasProtectedVisibility() const override { 301 return false; 302 } 303 304 unsigned getExnObjectAlignment() const override { 305 // The alignment of an exception object is 8-bytes for darwin since 306 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 307 // and therefore doesn't guarantee 16-byte alignment. 308 return 64; 309 } 310 }; 311 312 313 // DragonFlyBSD Target 314 template<typename Target> 315 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 316 protected: 317 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 318 MacroBuilder &Builder) const override { 319 // DragonFly defines; list based off of gcc output 320 Builder.defineMacro("__DragonFly__"); 321 Builder.defineMacro("__DragonFly_cc_version", "100001"); 322 Builder.defineMacro("__ELF__"); 323 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 324 Builder.defineMacro("__tune_i386__"); 325 DefineStd(Builder, "unix", Opts); 326 } 327 public: 328 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 329 : OSTargetInfo<Target>(Triple, Opts) { 330 switch (Triple.getArch()) { 331 default: 332 case llvm::Triple::x86: 333 case llvm::Triple::x86_64: 334 this->MCountName = ".mcount"; 335 break; 336 } 337 } 338 }; 339 340 #ifndef FREEBSD_CC_VERSION 341 #define FREEBSD_CC_VERSION 0U 342 #endif 343 344 // FreeBSD Target 345 template<typename Target> 346 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 347 protected: 348 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 349 MacroBuilder &Builder) const override { 350 // FreeBSD defines; list based off of gcc output 351 352 unsigned Release = Triple.getOSMajorVersion(); 353 if (Release == 0U) 354 Release = 8U; 355 unsigned CCVersion = FREEBSD_CC_VERSION; 356 if (CCVersion == 0U) 357 CCVersion = Release * 100000U + 1U; 358 359 Builder.defineMacro("__FreeBSD__", Twine(Release)); 360 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 361 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 362 DefineStd(Builder, "unix", Opts); 363 Builder.defineMacro("__ELF__"); 364 365 // On FreeBSD, wchar_t contains the number of the code point as 366 // used by the character set of the locale. These character sets are 367 // not necessarily a superset of ASCII. 368 // 369 // FIXME: This is wrong; the macro refers to the numerical values 370 // of wchar_t *literals*, which are not locale-dependent. However, 371 // FreeBSD systems apparently depend on us getting this wrong, and 372 // setting this to 1 is conforming even if all the basic source 373 // character literals have the same encoding as char and wchar_t. 374 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 375 } 376 public: 377 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 378 : OSTargetInfo<Target>(Triple, Opts) { 379 switch (Triple.getArch()) { 380 default: 381 case llvm::Triple::x86: 382 case llvm::Triple::x86_64: 383 this->MCountName = ".mcount"; 384 break; 385 case llvm::Triple::mips: 386 case llvm::Triple::mipsel: 387 case llvm::Triple::ppc: 388 case llvm::Triple::ppc64: 389 case llvm::Triple::ppc64le: 390 this->MCountName = "_mcount"; 391 break; 392 case llvm::Triple::arm: 393 this->MCountName = "__mcount"; 394 break; 395 } 396 } 397 }; 398 399 // GNU/kFreeBSD Target 400 template<typename Target> 401 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 402 protected: 403 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 404 MacroBuilder &Builder) const override { 405 // GNU/kFreeBSD defines; list based off of gcc output 406 407 DefineStd(Builder, "unix", Opts); 408 Builder.defineMacro("__FreeBSD_kernel__"); 409 Builder.defineMacro("__GLIBC__"); 410 Builder.defineMacro("__ELF__"); 411 if (Opts.POSIXThreads) 412 Builder.defineMacro("_REENTRANT"); 413 if (Opts.CPlusPlus) 414 Builder.defineMacro("_GNU_SOURCE"); 415 } 416 public: 417 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 418 : OSTargetInfo<Target>(Triple, Opts) {} 419 }; 420 421 // Haiku Target 422 template<typename Target> 423 class HaikuTargetInfo : public OSTargetInfo<Target> { 424 protected: 425 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 426 MacroBuilder &Builder) const override { 427 // Haiku defines; list based off of gcc output 428 Builder.defineMacro("__HAIKU__"); 429 Builder.defineMacro("__ELF__"); 430 DefineStd(Builder, "unix", Opts); 431 } 432 public: 433 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 434 : OSTargetInfo<Target>(Triple, Opts) { 435 this->SizeType = TargetInfo::UnsignedLong; 436 this->IntPtrType = TargetInfo::SignedLong; 437 this->PtrDiffType = TargetInfo::SignedLong; 438 this->ProcessIDType = TargetInfo::SignedLong; 439 this->TLSSupported = false; 440 441 } 442 }; 443 444 // Minix Target 445 template<typename Target> 446 class MinixTargetInfo : public OSTargetInfo<Target> { 447 protected: 448 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 449 MacroBuilder &Builder) const override { 450 // Minix defines 451 452 Builder.defineMacro("__minix", "3"); 453 Builder.defineMacro("_EM_WSIZE", "4"); 454 Builder.defineMacro("_EM_PSIZE", "4"); 455 Builder.defineMacro("_EM_SSIZE", "2"); 456 Builder.defineMacro("_EM_LSIZE", "4"); 457 Builder.defineMacro("_EM_FSIZE", "4"); 458 Builder.defineMacro("_EM_DSIZE", "8"); 459 Builder.defineMacro("__ELF__"); 460 DefineStd(Builder, "unix", Opts); 461 } 462 public: 463 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 464 : OSTargetInfo<Target>(Triple, Opts) {} 465 }; 466 467 // Linux target 468 template<typename Target> 469 class LinuxTargetInfo : public OSTargetInfo<Target> { 470 protected: 471 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 472 MacroBuilder &Builder) const override { 473 // Linux defines; list based off of gcc output 474 DefineStd(Builder, "unix", Opts); 475 DefineStd(Builder, "linux", Opts); 476 Builder.defineMacro("__gnu_linux__"); 477 Builder.defineMacro("__ELF__"); 478 if (Triple.isAndroid()) { 479 Builder.defineMacro("__ANDROID__", "1"); 480 unsigned Maj, Min, Rev; 481 Triple.getEnvironmentVersion(Maj, Min, Rev); 482 this->PlatformName = "android"; 483 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 484 if (Maj) 485 Builder.defineMacro("__ANDROID_API__", Twine(Maj)); 486 } 487 if (Opts.POSIXThreads) 488 Builder.defineMacro("_REENTRANT"); 489 if (Opts.CPlusPlus) 490 Builder.defineMacro("_GNU_SOURCE"); 491 if (this->HasFloat128) 492 Builder.defineMacro("__FLOAT128__"); 493 } 494 public: 495 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 496 : OSTargetInfo<Target>(Triple, Opts) { 497 this->WIntType = TargetInfo::UnsignedInt; 498 499 switch (Triple.getArch()) { 500 default: 501 break; 502 case llvm::Triple::ppc: 503 case llvm::Triple::ppc64: 504 case llvm::Triple::ppc64le: 505 this->MCountName = "_mcount"; 506 break; 507 case llvm::Triple::x86: 508 case llvm::Triple::x86_64: 509 case llvm::Triple::systemz: 510 this->HasFloat128 = true; 511 break; 512 } 513 } 514 515 const char *getStaticInitSectionSpecifier() const override { 516 return ".text.startup"; 517 } 518 }; 519 520 // NetBSD Target 521 template<typename Target> 522 class NetBSDTargetInfo : public OSTargetInfo<Target> { 523 protected: 524 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 525 MacroBuilder &Builder) const override { 526 // NetBSD defines; list based off of gcc output 527 Builder.defineMacro("__NetBSD__"); 528 Builder.defineMacro("__unix__"); 529 Builder.defineMacro("__ELF__"); 530 if (Opts.POSIXThreads) 531 Builder.defineMacro("_REENTRANT"); 532 533 switch (Triple.getArch()) { 534 default: 535 break; 536 case llvm::Triple::arm: 537 case llvm::Triple::armeb: 538 case llvm::Triple::thumb: 539 case llvm::Triple::thumbeb: 540 Builder.defineMacro("__ARM_DWARF_EH__"); 541 break; 542 } 543 } 544 public: 545 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 546 : OSTargetInfo<Target>(Triple, Opts) { 547 this->MCountName = "_mcount"; 548 } 549 }; 550 551 // OpenBSD Target 552 template<typename Target> 553 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 554 protected: 555 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 556 MacroBuilder &Builder) const override { 557 // OpenBSD defines; list based off of gcc output 558 559 Builder.defineMacro("__OpenBSD__"); 560 DefineStd(Builder, "unix", Opts); 561 Builder.defineMacro("__ELF__"); 562 if (Opts.POSIXThreads) 563 Builder.defineMacro("_REENTRANT"); 564 if (this->HasFloat128) 565 Builder.defineMacro("__FLOAT128__"); 566 } 567 public: 568 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 569 : OSTargetInfo<Target>(Triple, Opts) { 570 this->TLSSupported = false; 571 572 switch (Triple.getArch()) { 573 case llvm::Triple::x86: 574 case llvm::Triple::x86_64: 575 this->HasFloat128 = true; 576 // FALLTHROUGH 577 default: 578 this->MCountName = "__mcount"; 579 break; 580 case llvm::Triple::mips64: 581 case llvm::Triple::mips64el: 582 case llvm::Triple::ppc: 583 case llvm::Triple::sparcv9: 584 this->MCountName = "_mcount"; 585 break; 586 } 587 } 588 }; 589 590 // Bitrig Target 591 template<typename Target> 592 class BitrigTargetInfo : public OSTargetInfo<Target> { 593 protected: 594 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 595 MacroBuilder &Builder) const override { 596 // Bitrig defines; list based off of gcc output 597 598 Builder.defineMacro("__Bitrig__"); 599 DefineStd(Builder, "unix", Opts); 600 Builder.defineMacro("__ELF__"); 601 if (Opts.POSIXThreads) 602 Builder.defineMacro("_REENTRANT"); 603 604 switch (Triple.getArch()) { 605 default: 606 break; 607 case llvm::Triple::arm: 608 case llvm::Triple::armeb: 609 case llvm::Triple::thumb: 610 case llvm::Triple::thumbeb: 611 Builder.defineMacro("__ARM_DWARF_EH__"); 612 break; 613 } 614 } 615 public: 616 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 617 : OSTargetInfo<Target>(Triple, Opts) { 618 this->MCountName = "__mcount"; 619 } 620 }; 621 622 // PSP Target 623 template<typename Target> 624 class PSPTargetInfo : public OSTargetInfo<Target> { 625 protected: 626 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 627 MacroBuilder &Builder) const override { 628 // PSP defines; list based on the output of the pspdev gcc toolchain. 629 Builder.defineMacro("PSP"); 630 Builder.defineMacro("_PSP"); 631 Builder.defineMacro("__psp__"); 632 Builder.defineMacro("__ELF__"); 633 } 634 public: 635 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 636 }; 637 638 // PS3 PPU Target 639 template<typename Target> 640 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 641 protected: 642 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 643 MacroBuilder &Builder) const override { 644 // PS3 PPU defines. 645 Builder.defineMacro("__PPC__"); 646 Builder.defineMacro("__PPU__"); 647 Builder.defineMacro("__CELLOS_LV2__"); 648 Builder.defineMacro("__ELF__"); 649 Builder.defineMacro("__LP32__"); 650 Builder.defineMacro("_ARCH_PPC64"); 651 Builder.defineMacro("__powerpc64__"); 652 } 653 public: 654 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 655 : OSTargetInfo<Target>(Triple, Opts) { 656 this->LongWidth = this->LongAlign = 32; 657 this->PointerWidth = this->PointerAlign = 32; 658 this->IntMaxType = TargetInfo::SignedLongLong; 659 this->Int64Type = TargetInfo::SignedLongLong; 660 this->SizeType = TargetInfo::UnsignedInt; 661 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 662 } 663 }; 664 665 template <typename Target> 666 class PS4OSTargetInfo : public OSTargetInfo<Target> { 667 protected: 668 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 669 MacroBuilder &Builder) const override { 670 Builder.defineMacro("__FreeBSD__", "9"); 671 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 672 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 673 DefineStd(Builder, "unix", Opts); 674 Builder.defineMacro("__ELF__"); 675 Builder.defineMacro("__ORBIS__"); 676 } 677 public: 678 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 679 : OSTargetInfo<Target>(Triple, Opts) { 680 this->WCharType = this->UnsignedShort; 681 682 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 683 this->MaxTLSAlign = 256; 684 685 // On PS4, do not honor explicit bit field alignment, 686 // as in "__attribute__((aligned(2))) int b : 1;". 687 this->UseExplicitBitFieldAlignment = false; 688 689 switch (Triple.getArch()) { 690 default: 691 case llvm::Triple::x86_64: 692 this->MCountName = ".mcount"; 693 break; 694 } 695 } 696 }; 697 698 // Solaris target 699 template<typename Target> 700 class SolarisTargetInfo : public OSTargetInfo<Target> { 701 protected: 702 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 703 MacroBuilder &Builder) const override { 704 DefineStd(Builder, "sun", Opts); 705 DefineStd(Builder, "unix", Opts); 706 Builder.defineMacro("__ELF__"); 707 Builder.defineMacro("__svr4__"); 708 Builder.defineMacro("__SVR4"); 709 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 710 // newer, but to 500 for everything else. feature_test.h has a check to 711 // ensure that you are not using C99 with an old version of X/Open or C89 712 // with a new version. 713 if (Opts.C99) 714 Builder.defineMacro("_XOPEN_SOURCE", "600"); 715 else 716 Builder.defineMacro("_XOPEN_SOURCE", "500"); 717 if (Opts.CPlusPlus) 718 Builder.defineMacro("__C99FEATURES__"); 719 Builder.defineMacro("_LARGEFILE_SOURCE"); 720 Builder.defineMacro("_LARGEFILE64_SOURCE"); 721 Builder.defineMacro("__EXTENSIONS__"); 722 Builder.defineMacro("_REENTRANT"); 723 } 724 public: 725 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 726 : OSTargetInfo<Target>(Triple, Opts) { 727 this->WCharType = this->SignedInt; 728 // FIXME: WIntType should be SignedLong 729 } 730 }; 731 732 // Windows target 733 template<typename Target> 734 class WindowsTargetInfo : public OSTargetInfo<Target> { 735 protected: 736 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 737 MacroBuilder &Builder) const override { 738 Builder.defineMacro("_WIN32"); 739 } 740 void getVisualStudioDefines(const LangOptions &Opts, 741 MacroBuilder &Builder) const { 742 if (Opts.CPlusPlus) { 743 if (Opts.RTTIData) 744 Builder.defineMacro("_CPPRTTI"); 745 746 if (Opts.CXXExceptions) 747 Builder.defineMacro("_CPPUNWIND"); 748 } 749 750 if (Opts.Bool) 751 Builder.defineMacro("__BOOL_DEFINED"); 752 753 if (!Opts.CharIsSigned) 754 Builder.defineMacro("_CHAR_UNSIGNED"); 755 756 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 757 // but it works for now. 758 if (Opts.POSIXThreads) 759 Builder.defineMacro("_MT"); 760 761 if (Opts.MSCompatibilityVersion) { 762 Builder.defineMacro("_MSC_VER", 763 Twine(Opts.MSCompatibilityVersion / 100000)); 764 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 765 // FIXME We cannot encode the revision information into 32-bits 766 Builder.defineMacro("_MSC_BUILD", Twine(1)); 767 768 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 769 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 770 771 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 772 if (Opts.CPlusPlus1z) 773 Builder.defineMacro("_MSVC_LANG", "201403L"); 774 else if (Opts.CPlusPlus14) 775 Builder.defineMacro("_MSVC_LANG", "201402L"); 776 } 777 } 778 779 if (Opts.MicrosoftExt) { 780 Builder.defineMacro("_MSC_EXTENSIONS"); 781 782 if (Opts.CPlusPlus11) { 783 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 784 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 785 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 786 } 787 } 788 789 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 790 } 791 792 public: 793 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 794 : OSTargetInfo<Target>(Triple, Opts) {} 795 }; 796 797 template <typename Target> 798 class NaClTargetInfo : public OSTargetInfo<Target> { 799 protected: 800 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 801 MacroBuilder &Builder) const override { 802 if (Opts.POSIXThreads) 803 Builder.defineMacro("_REENTRANT"); 804 if (Opts.CPlusPlus) 805 Builder.defineMacro("_GNU_SOURCE"); 806 807 DefineStd(Builder, "unix", Opts); 808 Builder.defineMacro("__ELF__"); 809 Builder.defineMacro("__native_client__"); 810 } 811 812 public: 813 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 814 : OSTargetInfo<Target>(Triple, Opts) { 815 this->LongAlign = 32; 816 this->LongWidth = 32; 817 this->PointerAlign = 32; 818 this->PointerWidth = 32; 819 this->IntMaxType = TargetInfo::SignedLongLong; 820 this->Int64Type = TargetInfo::SignedLongLong; 821 this->DoubleAlign = 64; 822 this->LongDoubleWidth = 64; 823 this->LongDoubleAlign = 64; 824 this->LongLongWidth = 64; 825 this->LongLongAlign = 64; 826 this->SizeType = TargetInfo::UnsignedInt; 827 this->PtrDiffType = TargetInfo::SignedInt; 828 this->IntPtrType = TargetInfo::SignedInt; 829 // RegParmMax is inherited from the underlying architecture. 830 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 831 if (Triple.getArch() == llvm::Triple::arm) { 832 // Handled in ARM's setABI(). 833 } else if (Triple.getArch() == llvm::Triple::x86) { 834 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 835 } else if (Triple.getArch() == llvm::Triple::x86_64) { 836 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 837 } else if (Triple.getArch() == llvm::Triple::mipsel) { 838 // Handled on mips' setDataLayout. 839 } else { 840 assert(Triple.getArch() == llvm::Triple::le32); 841 this->resetDataLayout("e-p:32:32-i64:64"); 842 } 843 } 844 }; 845 846 // Fuchsia Target 847 template<typename Target> 848 class FuchsiaTargetInfo : public OSTargetInfo<Target> { 849 protected: 850 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 851 MacroBuilder &Builder) const override { 852 Builder.defineMacro("__Fuchsia__"); 853 Builder.defineMacro("__ELF__"); 854 if (Opts.POSIXThreads) 855 Builder.defineMacro("_REENTRANT"); 856 // Required by the libc++ locale support. 857 if (Opts.CPlusPlus) 858 Builder.defineMacro("_GNU_SOURCE"); 859 } 860 public: 861 FuchsiaTargetInfo(const llvm::Triple &Triple, 862 const TargetOptions &Opts) 863 : OSTargetInfo<Target>(Triple, Opts) { 864 this->MCountName = "__mcount"; 865 } 866 }; 867 868 // WebAssembly target 869 template <typename Target> 870 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 871 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 872 MacroBuilder &Builder) const final { 873 // A common platform macro. 874 if (Opts.POSIXThreads) 875 Builder.defineMacro("_REENTRANT"); 876 // Follow g++ convention and predefine _GNU_SOURCE for C++. 877 if (Opts.CPlusPlus) 878 Builder.defineMacro("_GNU_SOURCE"); 879 } 880 881 // As an optimization, group static init code together in a section. 882 const char *getStaticInitSectionSpecifier() const final { 883 return ".text.__startup"; 884 } 885 886 public: 887 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 888 const TargetOptions &Opts) 889 : OSTargetInfo<Target>(Triple, Opts) { 890 this->MCountName = "__mcount"; 891 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 892 } 893 }; 894 895 //===----------------------------------------------------------------------===// 896 // Specific target implementations. 897 //===----------------------------------------------------------------------===// 898 899 // PPC abstract base class 900 class PPCTargetInfo : public TargetInfo { 901 static const Builtin::Info BuiltinInfo[]; 902 static const char * const GCCRegNames[]; 903 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 904 std::string CPU; 905 906 // Target cpu features. 907 bool HasAltivec; 908 bool HasVSX; 909 bool HasP8Vector; 910 bool HasP8Crypto; 911 bool HasDirectMove; 912 bool HasQPX; 913 bool HasHTM; 914 bool HasBPERMD; 915 bool HasExtDiv; 916 bool HasP9Vector; 917 918 protected: 919 std::string ABI; 920 921 public: 922 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 923 : TargetInfo(Triple), HasAltivec(false), HasVSX(false), HasP8Vector(false), 924 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 925 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) { 926 SuitableAlign = 128; 927 SimdDefaultAlign = 128; 928 LongDoubleWidth = LongDoubleAlign = 128; 929 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 930 } 931 932 /// \brief Flags for architecture specific defines. 933 typedef enum { 934 ArchDefineNone = 0, 935 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 936 ArchDefinePpcgr = 1 << 1, 937 ArchDefinePpcsq = 1 << 2, 938 ArchDefine440 = 1 << 3, 939 ArchDefine603 = 1 << 4, 940 ArchDefine604 = 1 << 5, 941 ArchDefinePwr4 = 1 << 6, 942 ArchDefinePwr5 = 1 << 7, 943 ArchDefinePwr5x = 1 << 8, 944 ArchDefinePwr6 = 1 << 9, 945 ArchDefinePwr6x = 1 << 10, 946 ArchDefinePwr7 = 1 << 11, 947 ArchDefinePwr8 = 1 << 12, 948 ArchDefinePwr9 = 1 << 13, 949 ArchDefineA2 = 1 << 14, 950 ArchDefineA2q = 1 << 15 951 } ArchDefineTypes; 952 953 // Set the language option for altivec based on our value. 954 void adjust(LangOptions &Opts) override { 955 if (HasAltivec) 956 Opts.AltiVec = 1; 957 TargetInfo::adjust(Opts); 958 } 959 960 // Note: GCC recognizes the following additional cpus: 961 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 962 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 963 // titan, rs64. 964 bool setCPU(const std::string &Name) override { 965 bool CPUKnown = llvm::StringSwitch<bool>(Name) 966 .Case("generic", true) 967 .Case("440", true) 968 .Case("450", true) 969 .Case("601", true) 970 .Case("602", true) 971 .Case("603", true) 972 .Case("603e", true) 973 .Case("603ev", true) 974 .Case("604", true) 975 .Case("604e", true) 976 .Case("620", true) 977 .Case("630", true) 978 .Case("g3", true) 979 .Case("7400", true) 980 .Case("g4", true) 981 .Case("7450", true) 982 .Case("g4+", true) 983 .Case("750", true) 984 .Case("970", true) 985 .Case("g5", true) 986 .Case("a2", true) 987 .Case("a2q", true) 988 .Case("e500mc", true) 989 .Case("e5500", true) 990 .Case("power3", true) 991 .Case("pwr3", true) 992 .Case("power4", true) 993 .Case("pwr4", true) 994 .Case("power5", true) 995 .Case("pwr5", true) 996 .Case("power5x", true) 997 .Case("pwr5x", true) 998 .Case("power6", true) 999 .Case("pwr6", true) 1000 .Case("power6x", true) 1001 .Case("pwr6x", true) 1002 .Case("power7", true) 1003 .Case("pwr7", true) 1004 .Case("power8", true) 1005 .Case("pwr8", true) 1006 .Case("power9", true) 1007 .Case("pwr9", true) 1008 .Case("powerpc", true) 1009 .Case("ppc", true) 1010 .Case("powerpc64", true) 1011 .Case("ppc64", true) 1012 .Case("powerpc64le", true) 1013 .Case("ppc64le", true) 1014 .Default(false); 1015 1016 if (CPUKnown) 1017 CPU = Name; 1018 1019 return CPUKnown; 1020 } 1021 1022 1023 StringRef getABI() const override { return ABI; } 1024 1025 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1026 return llvm::makeArrayRef(BuiltinInfo, 1027 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 1028 } 1029 1030 bool isCLZForZeroUndef() const override { return false; } 1031 1032 void getTargetDefines(const LangOptions &Opts, 1033 MacroBuilder &Builder) const override; 1034 1035 bool 1036 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1037 StringRef CPU, 1038 const std::vector<std::string> &FeaturesVec) const override; 1039 1040 bool handleTargetFeatures(std::vector<std::string> &Features, 1041 DiagnosticsEngine &Diags) override; 1042 bool hasFeature(StringRef Feature) const override; 1043 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 1044 bool Enabled) const override; 1045 1046 ArrayRef<const char *> getGCCRegNames() const override; 1047 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 1048 bool validateAsmConstraint(const char *&Name, 1049 TargetInfo::ConstraintInfo &Info) const override { 1050 switch (*Name) { 1051 default: return false; 1052 case 'O': // Zero 1053 break; 1054 case 'b': // Base register 1055 case 'f': // Floating point register 1056 Info.setAllowsRegister(); 1057 break; 1058 // FIXME: The following are added to allow parsing. 1059 // I just took a guess at what the actions should be. 1060 // Also, is more specific checking needed? I.e. specific registers? 1061 case 'd': // Floating point register (containing 64-bit value) 1062 case 'v': // Altivec vector register 1063 Info.setAllowsRegister(); 1064 break; 1065 case 'w': 1066 switch (Name[1]) { 1067 case 'd':// VSX vector register to hold vector double data 1068 case 'f':// VSX vector register to hold vector float data 1069 case 's':// VSX vector register to hold scalar float data 1070 case 'a':// Any VSX register 1071 case 'c':// An individual CR bit 1072 break; 1073 default: 1074 return false; 1075 } 1076 Info.setAllowsRegister(); 1077 Name++; // Skip over 'w'. 1078 break; 1079 case 'h': // `MQ', `CTR', or `LINK' register 1080 case 'q': // `MQ' register 1081 case 'c': // `CTR' register 1082 case 'l': // `LINK' register 1083 case 'x': // `CR' register (condition register) number 0 1084 case 'y': // `CR' register (condition register) 1085 case 'z': // `XER[CA]' carry bit (part of the XER register) 1086 Info.setAllowsRegister(); 1087 break; 1088 case 'I': // Signed 16-bit constant 1089 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1090 // (use `L' instead for SImode constants) 1091 case 'K': // Unsigned 16-bit constant 1092 case 'L': // Signed 16-bit constant shifted left 16 bits 1093 case 'M': // Constant larger than 31 1094 case 'N': // Exact power of 2 1095 case 'P': // Constant whose negation is a signed 16-bit constant 1096 case 'G': // Floating point constant that can be loaded into a 1097 // register with one instruction per word 1098 case 'H': // Integer/Floating point constant that can be loaded 1099 // into a register using three instructions 1100 break; 1101 case 'm': // Memory operand. Note that on PowerPC targets, m can 1102 // include addresses that update the base register. It 1103 // is therefore only safe to use `m' in an asm statement 1104 // if that asm statement accesses the operand exactly once. 1105 // The asm statement must also use `%U<opno>' as a 1106 // placeholder for the "update" flag in the corresponding 1107 // load or store instruction. For example: 1108 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1109 // is correct but: 1110 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1111 // is not. Use es rather than m if you don't want the base 1112 // register to be updated. 1113 case 'e': 1114 if (Name[1] != 's') 1115 return false; 1116 // es: A "stable" memory operand; that is, one which does not 1117 // include any automodification of the base register. Unlike 1118 // `m', this constraint can be used in asm statements that 1119 // might access the operand several times, or that might not 1120 // access it at all. 1121 Info.setAllowsMemory(); 1122 Name++; // Skip over 'e'. 1123 break; 1124 case 'Q': // Memory operand that is an offset from a register (it is 1125 // usually better to use `m' or `es' in asm statements) 1126 case 'Z': // Memory operand that is an indexed or indirect from a 1127 // register (it is usually better to use `m' or `es' in 1128 // asm statements) 1129 Info.setAllowsMemory(); 1130 Info.setAllowsRegister(); 1131 break; 1132 case 'R': // AIX TOC entry 1133 case 'a': // Address operand that is an indexed or indirect from a 1134 // register (`p' is preferable for asm statements) 1135 case 'S': // Constant suitable as a 64-bit mask operand 1136 case 'T': // Constant suitable as a 32-bit mask operand 1137 case 'U': // System V Release 4 small data area reference 1138 case 't': // AND masks that can be performed by two rldic{l, r} 1139 // instructions 1140 case 'W': // Vector constant that does not require memory 1141 case 'j': // Vector constant that is all zeros. 1142 break; 1143 // End FIXME. 1144 } 1145 return true; 1146 } 1147 std::string convertConstraint(const char *&Constraint) const override { 1148 std::string R; 1149 switch (*Constraint) { 1150 case 'e': 1151 case 'w': 1152 // Two-character constraint; add "^" hint for later parsing. 1153 R = std::string("^") + std::string(Constraint, 2); 1154 Constraint++; 1155 break; 1156 default: 1157 return TargetInfo::convertConstraint(Constraint); 1158 } 1159 return R; 1160 } 1161 const char *getClobbers() const override { 1162 return ""; 1163 } 1164 int getEHDataRegisterNumber(unsigned RegNo) const override { 1165 if (RegNo == 0) return 3; 1166 if (RegNo == 1) return 4; 1167 return -1; 1168 } 1169 1170 bool hasSjLjLowering() const override { 1171 return true; 1172 } 1173 1174 bool useFloat128ManglingForLongDouble() const override { 1175 return LongDoubleWidth == 128 && 1176 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() && 1177 getTriple().isOSBinFormatELF(); 1178 } 1179 }; 1180 1181 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1182 #define BUILTIN(ID, TYPE, ATTRS) \ 1183 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1184 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1185 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1186 #include "clang/Basic/BuiltinsPPC.def" 1187 }; 1188 1189 /// handleTargetFeatures - Perform initialization based on the user 1190 /// configured set of features. 1191 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1192 DiagnosticsEngine &Diags) { 1193 for (const auto &Feature : Features) { 1194 if (Feature == "+altivec") { 1195 HasAltivec = true; 1196 } else if (Feature == "+vsx") { 1197 HasVSX = true; 1198 } else if (Feature == "+bpermd") { 1199 HasBPERMD = true; 1200 } else if (Feature == "+extdiv") { 1201 HasExtDiv = true; 1202 } else if (Feature == "+power8-vector") { 1203 HasP8Vector = true; 1204 } else if (Feature == "+crypto") { 1205 HasP8Crypto = true; 1206 } else if (Feature == "+direct-move") { 1207 HasDirectMove = true; 1208 } else if (Feature == "+qpx") { 1209 HasQPX = true; 1210 } else if (Feature == "+htm") { 1211 HasHTM = true; 1212 } else if (Feature == "+float128") { 1213 HasFloat128 = true; 1214 } else if (Feature == "+power9-vector") { 1215 HasP9Vector = true; 1216 } 1217 // TODO: Finish this list and add an assert that we've handled them 1218 // all. 1219 } 1220 1221 return true; 1222 } 1223 1224 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1225 /// #defines that are not tied to a specific subtarget. 1226 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1227 MacroBuilder &Builder) const { 1228 // Target identification. 1229 Builder.defineMacro("__ppc__"); 1230 Builder.defineMacro("__PPC__"); 1231 Builder.defineMacro("_ARCH_PPC"); 1232 Builder.defineMacro("__powerpc__"); 1233 Builder.defineMacro("__POWERPC__"); 1234 if (PointerWidth == 64) { 1235 Builder.defineMacro("_ARCH_PPC64"); 1236 Builder.defineMacro("__powerpc64__"); 1237 Builder.defineMacro("__ppc64__"); 1238 Builder.defineMacro("__PPC64__"); 1239 } 1240 1241 // Target properties. 1242 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1243 Builder.defineMacro("_LITTLE_ENDIAN"); 1244 } else { 1245 if (getTriple().getOS() != llvm::Triple::NetBSD && 1246 getTriple().getOS() != llvm::Triple::OpenBSD) 1247 Builder.defineMacro("_BIG_ENDIAN"); 1248 } 1249 1250 // ABI options. 1251 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1252 Builder.defineMacro("_CALL_ELF", "1"); 1253 if (ABI == "elfv2") 1254 Builder.defineMacro("_CALL_ELF", "2"); 1255 1256 // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but 1257 // our suppport post-dates this and it should work on all 64-bit ppc linux 1258 // platforms. It is guaranteed to work on all elfv2 platforms. 1259 if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64) 1260 Builder.defineMacro("_CALL_LINUX", "1"); 1261 1262 // Subtarget options. 1263 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1264 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1265 1266 // FIXME: Should be controlled by command line option. 1267 if (LongDoubleWidth == 128) { 1268 Builder.defineMacro("__LONG_DOUBLE_128__"); 1269 Builder.defineMacro("__LONGDOUBLE128"); 1270 } 1271 1272 // Define this for elfv2 (64-bit only) or 64-bit darwin. 1273 if (ABI == "elfv2" || 1274 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64)) 1275 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16"); 1276 1277 // CPU identification. 1278 ArchDefineTypes defs = 1279 (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1280 .Case("440", ArchDefineName) 1281 .Case("450", ArchDefineName | ArchDefine440) 1282 .Case("601", ArchDefineName) 1283 .Case("602", ArchDefineName | ArchDefinePpcgr) 1284 .Case("603", ArchDefineName | ArchDefinePpcgr) 1285 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1286 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1287 .Case("604", ArchDefineName | ArchDefinePpcgr) 1288 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1289 .Case("620", ArchDefineName | ArchDefinePpcgr) 1290 .Case("630", ArchDefineName | ArchDefinePpcgr) 1291 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1292 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1293 .Case("750", ArchDefineName | ArchDefinePpcgr) 1294 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1295 ArchDefinePpcsq) 1296 .Case("a2", ArchDefineA2) 1297 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1298 .Case("pwr3", ArchDefinePpcgr) 1299 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1300 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1301 ArchDefinePpcsq) 1302 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 | 1303 ArchDefinePpcgr | ArchDefinePpcsq) 1304 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 | 1305 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1306 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x | 1307 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1308 ArchDefinePpcsq) 1309 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 | 1310 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1311 ArchDefinePpcgr | ArchDefinePpcsq) 1312 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x | 1313 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1314 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1315 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 | 1316 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1317 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1318 ArchDefinePpcsq) 1319 .Case("power3", ArchDefinePpcgr) 1320 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1321 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1322 ArchDefinePpcsq) 1323 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1324 ArchDefinePpcgr | ArchDefinePpcsq) 1325 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1326 ArchDefinePwr4 | ArchDefinePpcgr | 1327 ArchDefinePpcsq) 1328 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1329 ArchDefinePwr5 | ArchDefinePwr4 | 1330 ArchDefinePpcgr | ArchDefinePpcsq) 1331 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 | 1332 ArchDefinePwr5x | ArchDefinePwr5 | 1333 ArchDefinePwr4 | ArchDefinePpcgr | 1334 ArchDefinePpcsq) 1335 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1336 ArchDefinePwr6 | ArchDefinePwr5x | 1337 ArchDefinePwr5 | ArchDefinePwr4 | 1338 ArchDefinePpcgr | ArchDefinePpcsq) 1339 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 1340 ArchDefinePwr6x | ArchDefinePwr6 | 1341 ArchDefinePwr5x | ArchDefinePwr5 | 1342 ArchDefinePwr4 | ArchDefinePpcgr | 1343 ArchDefinePpcsq) 1344 // powerpc64le automatically defaults to at least power8. 1345 .Case("ppc64le", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1346 ArchDefinePwr6 | ArchDefinePwr5x | 1347 ArchDefinePwr5 | ArchDefinePwr4 | 1348 ArchDefinePpcgr | ArchDefinePpcsq) 1349 .Default(ArchDefineNone); 1350 1351 if (defs & ArchDefineName) 1352 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1353 if (defs & ArchDefinePpcgr) 1354 Builder.defineMacro("_ARCH_PPCGR"); 1355 if (defs & ArchDefinePpcsq) 1356 Builder.defineMacro("_ARCH_PPCSQ"); 1357 if (defs & ArchDefine440) 1358 Builder.defineMacro("_ARCH_440"); 1359 if (defs & ArchDefine603) 1360 Builder.defineMacro("_ARCH_603"); 1361 if (defs & ArchDefine604) 1362 Builder.defineMacro("_ARCH_604"); 1363 if (defs & ArchDefinePwr4) 1364 Builder.defineMacro("_ARCH_PWR4"); 1365 if (defs & ArchDefinePwr5) 1366 Builder.defineMacro("_ARCH_PWR5"); 1367 if (defs & ArchDefinePwr5x) 1368 Builder.defineMacro("_ARCH_PWR5X"); 1369 if (defs & ArchDefinePwr6) 1370 Builder.defineMacro("_ARCH_PWR6"); 1371 if (defs & ArchDefinePwr6x) 1372 Builder.defineMacro("_ARCH_PWR6X"); 1373 if (defs & ArchDefinePwr7) 1374 Builder.defineMacro("_ARCH_PWR7"); 1375 if (defs & ArchDefinePwr8) 1376 Builder.defineMacro("_ARCH_PWR8"); 1377 if (defs & ArchDefinePwr9) 1378 Builder.defineMacro("_ARCH_PWR9"); 1379 if (defs & ArchDefineA2) 1380 Builder.defineMacro("_ARCH_A2"); 1381 if (defs & ArchDefineA2q) { 1382 Builder.defineMacro("_ARCH_A2Q"); 1383 Builder.defineMacro("_ARCH_QP"); 1384 } 1385 1386 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1387 Builder.defineMacro("__bg__"); 1388 Builder.defineMacro("__THW_BLUEGENE__"); 1389 Builder.defineMacro("__bgq__"); 1390 Builder.defineMacro("__TOS_BGQ__"); 1391 } 1392 1393 if (HasAltivec) { 1394 Builder.defineMacro("__VEC__", "10206"); 1395 Builder.defineMacro("__ALTIVEC__"); 1396 } 1397 if (HasVSX) 1398 Builder.defineMacro("__VSX__"); 1399 if (HasP8Vector) 1400 Builder.defineMacro("__POWER8_VECTOR__"); 1401 if (HasP8Crypto) 1402 Builder.defineMacro("__CRYPTO__"); 1403 if (HasHTM) 1404 Builder.defineMacro("__HTM__"); 1405 if (HasFloat128) 1406 Builder.defineMacro("__FLOAT128__"); 1407 if (HasP9Vector) 1408 Builder.defineMacro("__POWER9_VECTOR__"); 1409 1410 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1411 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1412 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1413 if (PointerWidth == 64) 1414 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1415 1416 // We have support for the bswap intrinsics so we can define this. 1417 Builder.defineMacro("__HAVE_BSWAP__", "1"); 1418 1419 // FIXME: The following are not yet generated here by Clang, but are 1420 // generated by GCC: 1421 // 1422 // _SOFT_FLOAT_ 1423 // __RECIP_PRECISION__ 1424 // __APPLE_ALTIVEC__ 1425 // __RECIP__ 1426 // __RECIPF__ 1427 // __RSQRTE__ 1428 // __RSQRTEF__ 1429 // _SOFT_DOUBLE_ 1430 // __NO_LWSYNC__ 1431 // __CMODEL_MEDIUM__ 1432 // __CMODEL_LARGE__ 1433 // _CALL_SYSV 1434 // _CALL_DARWIN 1435 // __NO_FPRS__ 1436 } 1437 1438 // Handle explicit options being passed to the compiler here: if we've 1439 // explicitly turned off vsx and turned on any of: 1440 // - power8-vector 1441 // - direct-move 1442 // - float128 1443 // - power9-vector 1444 // then go ahead and error since the customer has expressed an incompatible 1445 // set of options. 1446 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1447 const std::vector<std::string> &FeaturesVec) { 1448 1449 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1450 FeaturesVec.end()) { 1451 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1452 FeaturesVec.end()) { 1453 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1454 << "-mno-vsx"; 1455 return false; 1456 } 1457 1458 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1459 FeaturesVec.end()) { 1460 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1461 << "-mno-vsx"; 1462 return false; 1463 } 1464 1465 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1466 FeaturesVec.end()) { 1467 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1468 << "-mno-vsx"; 1469 return false; 1470 } 1471 1472 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") != 1473 FeaturesVec.end()) { 1474 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector" 1475 << "-mno-vsx"; 1476 return false; 1477 } 1478 } 1479 1480 return true; 1481 } 1482 1483 bool PPCTargetInfo::initFeatureMap( 1484 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1485 const std::vector<std::string> &FeaturesVec) const { 1486 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1487 .Case("7400", true) 1488 .Case("g4", true) 1489 .Case("7450", true) 1490 .Case("g4+", true) 1491 .Case("970", true) 1492 .Case("g5", true) 1493 .Case("pwr6", true) 1494 .Case("pwr7", true) 1495 .Case("pwr8", true) 1496 .Case("pwr9", true) 1497 .Case("ppc64", true) 1498 .Case("ppc64le", true) 1499 .Default(false); 1500 1501 Features["qpx"] = (CPU == "a2q"); 1502 Features["power9-vector"] = (CPU == "pwr9"); 1503 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1504 .Case("ppc64le", true) 1505 .Case("pwr9", true) 1506 .Case("pwr8", true) 1507 .Default(false); 1508 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1509 .Case("ppc64le", true) 1510 .Case("pwr9", true) 1511 .Case("pwr8", true) 1512 .Default(false); 1513 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1514 .Case("ppc64le", true) 1515 .Case("pwr9", true) 1516 .Case("pwr8", true) 1517 .Case("pwr7", true) 1518 .Default(false); 1519 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1520 .Case("ppc64le", true) 1521 .Case("pwr9", true) 1522 .Case("pwr8", true) 1523 .Case("pwr7", true) 1524 .Default(false); 1525 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1526 .Case("ppc64le", true) 1527 .Case("pwr9", true) 1528 .Case("pwr8", true) 1529 .Default(false); 1530 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1531 .Case("ppc64le", true) 1532 .Case("pwr9", true) 1533 .Case("pwr8", true) 1534 .Case("pwr7", true) 1535 .Default(false); 1536 Features["htm"] = llvm::StringSwitch<bool>(CPU) 1537 .Case("ppc64le", true) 1538 .Case("pwr9", true) 1539 .Case("pwr8", true) 1540 .Default(false); 1541 1542 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1543 return false; 1544 1545 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1546 } 1547 1548 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1549 return llvm::StringSwitch<bool>(Feature) 1550 .Case("powerpc", true) 1551 .Case("altivec", HasAltivec) 1552 .Case("vsx", HasVSX) 1553 .Case("power8-vector", HasP8Vector) 1554 .Case("crypto", HasP8Crypto) 1555 .Case("direct-move", HasDirectMove) 1556 .Case("qpx", HasQPX) 1557 .Case("htm", HasHTM) 1558 .Case("bpermd", HasBPERMD) 1559 .Case("extdiv", HasExtDiv) 1560 .Case("float128", HasFloat128) 1561 .Case("power9-vector", HasP9Vector) 1562 .Default(false); 1563 } 1564 1565 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1566 StringRef Name, bool Enabled) const { 1567 if (Enabled) { 1568 // If we're enabling any of the vsx based features then enable vsx and 1569 // altivec. We'll diagnose any problems later. 1570 bool FeatureHasVSX = llvm::StringSwitch<bool>(Name) 1571 .Case("vsx", true) 1572 .Case("direct-move", true) 1573 .Case("power8-vector", true) 1574 .Case("power9-vector", true) 1575 .Case("float128", true) 1576 .Default(false); 1577 if (FeatureHasVSX) 1578 Features["vsx"] = Features["altivec"] = true; 1579 if (Name == "power9-vector") 1580 Features["power8-vector"] = true; 1581 Features[Name] = true; 1582 } else { 1583 // If we're disabling altivec or vsx go ahead and disable all of the vsx 1584 // features. 1585 if ((Name == "altivec") || (Name == "vsx")) 1586 Features["vsx"] = Features["direct-move"] = Features["power8-vector"] = 1587 Features["float128"] = Features["power9-vector"] = false; 1588 if (Name == "power8-vector") 1589 Features["power9-vector"] = false; 1590 Features[Name] = false; 1591 } 1592 } 1593 1594 const char * const PPCTargetInfo::GCCRegNames[] = { 1595 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1596 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1597 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1598 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1599 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1600 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1601 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1602 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1603 "mq", "lr", "ctr", "ap", 1604 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1605 "xer", 1606 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1607 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1608 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1609 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1610 "vrsave", "vscr", 1611 "spe_acc", "spefscr", 1612 "sfp" 1613 }; 1614 1615 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1616 return llvm::makeArrayRef(GCCRegNames); 1617 } 1618 1619 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1620 // While some of these aliases do map to different registers 1621 // they still share the same register name. 1622 { { "0" }, "r0" }, 1623 { { "1"}, "r1" }, 1624 { { "2" }, "r2" }, 1625 { { "3" }, "r3" }, 1626 { { "4" }, "r4" }, 1627 { { "5" }, "r5" }, 1628 { { "6" }, "r6" }, 1629 { { "7" }, "r7" }, 1630 { { "8" }, "r8" }, 1631 { { "9" }, "r9" }, 1632 { { "10" }, "r10" }, 1633 { { "11" }, "r11" }, 1634 { { "12" }, "r12" }, 1635 { { "13" }, "r13" }, 1636 { { "14" }, "r14" }, 1637 { { "15" }, "r15" }, 1638 { { "16" }, "r16" }, 1639 { { "17" }, "r17" }, 1640 { { "18" }, "r18" }, 1641 { { "19" }, "r19" }, 1642 { { "20" }, "r20" }, 1643 { { "21" }, "r21" }, 1644 { { "22" }, "r22" }, 1645 { { "23" }, "r23" }, 1646 { { "24" }, "r24" }, 1647 { { "25" }, "r25" }, 1648 { { "26" }, "r26" }, 1649 { { "27" }, "r27" }, 1650 { { "28" }, "r28" }, 1651 { { "29" }, "r29" }, 1652 { { "30" }, "r30" }, 1653 { { "31" }, "r31" }, 1654 { { "fr0" }, "f0" }, 1655 { { "fr1" }, "f1" }, 1656 { { "fr2" }, "f2" }, 1657 { { "fr3" }, "f3" }, 1658 { { "fr4" }, "f4" }, 1659 { { "fr5" }, "f5" }, 1660 { { "fr6" }, "f6" }, 1661 { { "fr7" }, "f7" }, 1662 { { "fr8" }, "f8" }, 1663 { { "fr9" }, "f9" }, 1664 { { "fr10" }, "f10" }, 1665 { { "fr11" }, "f11" }, 1666 { { "fr12" }, "f12" }, 1667 { { "fr13" }, "f13" }, 1668 { { "fr14" }, "f14" }, 1669 { { "fr15" }, "f15" }, 1670 { { "fr16" }, "f16" }, 1671 { { "fr17" }, "f17" }, 1672 { { "fr18" }, "f18" }, 1673 { { "fr19" }, "f19" }, 1674 { { "fr20" }, "f20" }, 1675 { { "fr21" }, "f21" }, 1676 { { "fr22" }, "f22" }, 1677 { { "fr23" }, "f23" }, 1678 { { "fr24" }, "f24" }, 1679 { { "fr25" }, "f25" }, 1680 { { "fr26" }, "f26" }, 1681 { { "fr27" }, "f27" }, 1682 { { "fr28" }, "f28" }, 1683 { { "fr29" }, "f29" }, 1684 { { "fr30" }, "f30" }, 1685 { { "fr31" }, "f31" }, 1686 { { "cc" }, "cr0" }, 1687 }; 1688 1689 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1690 return llvm::makeArrayRef(GCCRegAliases); 1691 } 1692 1693 class PPC32TargetInfo : public PPCTargetInfo { 1694 public: 1695 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1696 : PPCTargetInfo(Triple, Opts) { 1697 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1698 1699 switch (getTriple().getOS()) { 1700 case llvm::Triple::Linux: 1701 case llvm::Triple::FreeBSD: 1702 case llvm::Triple::NetBSD: 1703 SizeType = UnsignedInt; 1704 PtrDiffType = SignedInt; 1705 IntPtrType = SignedInt; 1706 break; 1707 default: 1708 break; 1709 } 1710 1711 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1712 LongDoubleWidth = LongDoubleAlign = 64; 1713 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1714 } 1715 1716 // PPC32 supports atomics up to 4 bytes. 1717 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1718 } 1719 1720 BuiltinVaListKind getBuiltinVaListKind() const override { 1721 // This is the ELF definition, and is overridden by the Darwin sub-target 1722 return TargetInfo::PowerABIBuiltinVaList; 1723 } 1724 }; 1725 1726 // Note: ABI differences may eventually require us to have a separate 1727 // TargetInfo for little endian. 1728 class PPC64TargetInfo : public PPCTargetInfo { 1729 public: 1730 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1731 : PPCTargetInfo(Triple, Opts) { 1732 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1733 IntMaxType = SignedLong; 1734 Int64Type = SignedLong; 1735 1736 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1737 resetDataLayout("e-m:e-i64:64-n32:64"); 1738 ABI = "elfv2"; 1739 } else { 1740 resetDataLayout("E-m:e-i64:64-n32:64"); 1741 ABI = "elfv1"; 1742 } 1743 1744 switch (getTriple().getOS()) { 1745 case llvm::Triple::FreeBSD: 1746 LongDoubleWidth = LongDoubleAlign = 64; 1747 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1748 break; 1749 case llvm::Triple::NetBSD: 1750 IntMaxType = SignedLongLong; 1751 Int64Type = SignedLongLong; 1752 break; 1753 default: 1754 break; 1755 } 1756 1757 // PPC64 supports atomics up to 8 bytes. 1758 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1759 } 1760 BuiltinVaListKind getBuiltinVaListKind() const override { 1761 return TargetInfo::CharPtrBuiltinVaList; 1762 } 1763 // PPC64 Linux-specific ABI options. 1764 bool setABI(const std::string &Name) override { 1765 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1766 ABI = Name; 1767 return true; 1768 } 1769 return false; 1770 } 1771 }; 1772 1773 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1774 public: 1775 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1776 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1777 HasAlignMac68kSupport = true; 1778 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1779 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1780 LongLongAlign = 32; 1781 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1782 } 1783 BuiltinVaListKind getBuiltinVaListKind() const override { 1784 return TargetInfo::CharPtrBuiltinVaList; 1785 } 1786 }; 1787 1788 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1789 public: 1790 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1791 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1792 HasAlignMac68kSupport = true; 1793 resetDataLayout("E-m:o-i64:64-n32:64"); 1794 } 1795 }; 1796 1797 static const unsigned NVPTXAddrSpaceMap[] = { 1798 0, // Default 1799 1, // opencl_global 1800 3, // opencl_local 1801 4, // opencl_constant 1802 // FIXME: generic has to be added to the target 1803 0, // opencl_generic 1804 1, // cuda_device 1805 4, // cuda_constant 1806 3, // cuda_shared 1807 }; 1808 1809 class NVPTXTargetInfo : public TargetInfo { 1810 static const char *const GCCRegNames[]; 1811 static const Builtin::Info BuiltinInfo[]; 1812 CudaArch GPU; 1813 std::unique_ptr<TargetInfo> HostTarget; 1814 1815 public: 1816 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 1817 unsigned TargetPointerWidth) 1818 : TargetInfo(Triple) { 1819 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) && 1820 "NVPTX only supports 32- and 64-bit modes."); 1821 1822 TLSSupported = false; 1823 AddrSpaceMap = &NVPTXAddrSpaceMap; 1824 UseAddrSpaceMapMangling = true; 1825 1826 // Define available target features 1827 // These must be defined in sorted order! 1828 NoAsmVariants = true; 1829 GPU = CudaArch::SM_20; 1830 1831 if (TargetPointerWidth == 32) 1832 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1833 else 1834 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1835 1836 // If possible, get a TargetInfo for our host triple, so we can match its 1837 // types. 1838 llvm::Triple HostTriple(Opts.HostTriple); 1839 if (!HostTriple.isNVPTX()) 1840 HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1841 1842 // If no host target, make some guesses about the data layout and return. 1843 if (!HostTarget) { 1844 LongWidth = LongAlign = TargetPointerWidth; 1845 PointerWidth = PointerAlign = TargetPointerWidth; 1846 switch (TargetPointerWidth) { 1847 case 32: 1848 SizeType = TargetInfo::UnsignedInt; 1849 PtrDiffType = TargetInfo::SignedInt; 1850 IntPtrType = TargetInfo::SignedInt; 1851 break; 1852 case 64: 1853 SizeType = TargetInfo::UnsignedLong; 1854 PtrDiffType = TargetInfo::SignedLong; 1855 IntPtrType = TargetInfo::SignedLong; 1856 break; 1857 default: 1858 llvm_unreachable("TargetPointerWidth must be 32 or 64"); 1859 } 1860 return; 1861 } 1862 1863 // Copy properties from host target. 1864 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1865 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1866 BoolWidth = HostTarget->getBoolWidth(); 1867 BoolAlign = HostTarget->getBoolAlign(); 1868 IntWidth = HostTarget->getIntWidth(); 1869 IntAlign = HostTarget->getIntAlign(); 1870 HalfWidth = HostTarget->getHalfWidth(); 1871 HalfAlign = HostTarget->getHalfAlign(); 1872 FloatWidth = HostTarget->getFloatWidth(); 1873 FloatAlign = HostTarget->getFloatAlign(); 1874 DoubleWidth = HostTarget->getDoubleWidth(); 1875 DoubleAlign = HostTarget->getDoubleAlign(); 1876 LongWidth = HostTarget->getLongWidth(); 1877 LongAlign = HostTarget->getLongAlign(); 1878 LongLongWidth = HostTarget->getLongLongWidth(); 1879 LongLongAlign = HostTarget->getLongLongAlign(); 1880 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1881 NewAlign = HostTarget->getNewAlign(); 1882 DefaultAlignForAttributeAligned = 1883 HostTarget->getDefaultAlignForAttributeAligned(); 1884 SizeType = HostTarget->getSizeType(); 1885 IntMaxType = HostTarget->getIntMaxType(); 1886 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1887 IntPtrType = HostTarget->getIntPtrType(); 1888 WCharType = HostTarget->getWCharType(); 1889 WIntType = HostTarget->getWIntType(); 1890 Char16Type = HostTarget->getChar16Type(); 1891 Char32Type = HostTarget->getChar32Type(); 1892 Int64Type = HostTarget->getInt64Type(); 1893 SigAtomicType = HostTarget->getSigAtomicType(); 1894 ProcessIDType = HostTarget->getProcessIDType(); 1895 1896 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1897 UseZeroLengthBitfieldAlignment = 1898 HostTarget->useZeroLengthBitfieldAlignment(); 1899 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1900 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1901 1902 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and 1903 // we need those macros to be identical on host and device, because (among 1904 // other things) they affect which standard library classes are defined, and 1905 // we need all classes to be defined on both the host and device. 1906 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth(); 1907 1908 // Properties intentionally not copied from host: 1909 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1910 // host/device boundary. 1911 // - SuitableAlign: Not visible across the host/device boundary, and may 1912 // correctly be different on host/device, e.g. if host has wider vector 1913 // types than device. 1914 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1915 // as its double type, but that's not necessarily true on the host. 1916 // TODO: nvcc emits a warning when using long double on device; we should 1917 // do the same. 1918 } 1919 void getTargetDefines(const LangOptions &Opts, 1920 MacroBuilder &Builder) const override { 1921 Builder.defineMacro("__PTX__"); 1922 Builder.defineMacro("__NVPTX__"); 1923 if (Opts.CUDAIsDevice) { 1924 // Set __CUDA_ARCH__ for the GPU specified. 1925 std::string CUDAArchCode = [this] { 1926 switch (GPU) { 1927 case CudaArch::UNKNOWN: 1928 assert(false && "No GPU arch when compiling CUDA device code."); 1929 return ""; 1930 case CudaArch::SM_20: 1931 return "200"; 1932 case CudaArch::SM_21: 1933 return "210"; 1934 case CudaArch::SM_30: 1935 return "300"; 1936 case CudaArch::SM_32: 1937 return "320"; 1938 case CudaArch::SM_35: 1939 return "350"; 1940 case CudaArch::SM_37: 1941 return "370"; 1942 case CudaArch::SM_50: 1943 return "500"; 1944 case CudaArch::SM_52: 1945 return "520"; 1946 case CudaArch::SM_53: 1947 return "530"; 1948 case CudaArch::SM_60: 1949 return "600"; 1950 case CudaArch::SM_61: 1951 return "610"; 1952 case CudaArch::SM_62: 1953 return "620"; 1954 } 1955 llvm_unreachable("unhandled CudaArch"); 1956 }(); 1957 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1958 } 1959 } 1960 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1961 return llvm::makeArrayRef(BuiltinInfo, 1962 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1963 } 1964 bool 1965 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1966 StringRef CPU, 1967 const std::vector<std::string> &FeaturesVec) const override { 1968 Features["satom"] = GPU >= CudaArch::SM_60; 1969 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1970 } 1971 1972 bool hasFeature(StringRef Feature) const override { 1973 return llvm::StringSwitch<bool>(Feature) 1974 .Cases("ptx", "nvptx", true) 1975 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope. 1976 .Default(false); 1977 } 1978 1979 ArrayRef<const char *> getGCCRegNames() const override; 1980 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1981 // No aliases. 1982 return None; 1983 } 1984 bool validateAsmConstraint(const char *&Name, 1985 TargetInfo::ConstraintInfo &Info) const override { 1986 switch (*Name) { 1987 default: 1988 return false; 1989 case 'c': 1990 case 'h': 1991 case 'r': 1992 case 'l': 1993 case 'f': 1994 case 'd': 1995 Info.setAllowsRegister(); 1996 return true; 1997 } 1998 } 1999 const char *getClobbers() const override { 2000 // FIXME: Is this really right? 2001 return ""; 2002 } 2003 BuiltinVaListKind getBuiltinVaListKind() const override { 2004 // FIXME: implement 2005 return TargetInfo::CharPtrBuiltinVaList; 2006 } 2007 bool setCPU(const std::string &Name) override { 2008 GPU = StringToCudaArch(Name); 2009 return GPU != CudaArch::UNKNOWN; 2010 } 2011 void setSupportedOpenCLOpts() override { 2012 auto &Opts = getSupportedOpenCLOpts(); 2013 Opts.support("cl_clang_storage_class_specifiers"); 2014 Opts.support("cl_khr_gl_sharing"); 2015 Opts.support("cl_khr_icd"); 2016 2017 Opts.support("cl_khr_fp64"); 2018 Opts.support("cl_khr_byte_addressable_store"); 2019 Opts.support("cl_khr_global_int32_base_atomics"); 2020 Opts.support("cl_khr_global_int32_extended_atomics"); 2021 Opts.support("cl_khr_local_int32_base_atomics"); 2022 Opts.support("cl_khr_local_int32_extended_atomics"); 2023 } 2024 2025 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2026 // CUDA compilations support all of the host's calling conventions. 2027 // 2028 // TODO: We should warn if you apply a non-default CC to anything other than 2029 // a host function. 2030 if (HostTarget) 2031 return HostTarget->checkCallingConvention(CC); 2032 return CCCR_Warning; 2033 } 2034 }; 2035 2036 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 2037 #define BUILTIN(ID, TYPE, ATTRS) \ 2038 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2039 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2040 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2041 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2042 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2043 #include "clang/Basic/BuiltinsNVPTX.def" 2044 }; 2045 2046 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 2047 2048 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 2049 return llvm::makeArrayRef(GCCRegNames); 2050 } 2051 2052 static const LangAS::Map AMDGPUNonOpenCLPrivateIsZeroMap = { 2053 4, // Default 2054 1, // opencl_global 2055 3, // opencl_local 2056 2, // opencl_constant 2057 4, // opencl_generic 2058 1, // cuda_device 2059 2, // cuda_constant 2060 3 // cuda_shared 2061 }; 2062 static const LangAS::Map AMDGPUNonOpenCLGenericIsZeroMap = { 2063 0, // Default 2064 1, // opencl_global 2065 3, // opencl_local 2066 2, // opencl_constant 2067 0, // opencl_generic 2068 1, // cuda_device 2069 2, // cuda_constant 2070 3 // cuda_shared 2071 }; 2072 static const LangAS::Map AMDGPUOpenCLPrivateIsZeroMap = { 2073 0, // Default 2074 1, // opencl_global 2075 3, // opencl_local 2076 2, // opencl_constant 2077 4, // opencl_generic 2078 1, // cuda_device 2079 2, // cuda_constant 2080 3 // cuda_shared 2081 }; 2082 static const LangAS::Map AMDGPUOpenCLGenericIsZeroMap = { 2083 5, // Default 2084 1, // opencl_global 2085 3, // opencl_local 2086 2, // opencl_constant 2087 0, // opencl_generic 2088 1, // cuda_device 2089 2, // cuda_constant 2090 3 // cuda_shared 2091 }; 2092 2093 // If you edit the description strings, make sure you update 2094 // getPointerWidthV(). 2095 2096 static const char *const DataLayoutStringR600 = 2097 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2098 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2099 2100 static const char *const DataLayoutStringSIPrivateIsZero = 2101 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 2102 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2103 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2104 2105 static const char *const DataLayoutStringSIGenericIsZero = 2106 "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32" 2107 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2108 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"; 2109 2110 class AMDGPUTargetInfo final : public TargetInfo { 2111 static const Builtin::Info BuiltinInfo[]; 2112 static const char * const GCCRegNames[]; 2113 2114 struct AddrSpace { 2115 unsigned Generic, Global, Local, Constant, Private; 2116 AddrSpace(bool IsGenericZero_ = false){ 2117 if (IsGenericZero_) { 2118 Generic = 0; 2119 Global = 1; 2120 Local = 3; 2121 Constant = 2; 2122 Private = 5; 2123 } else { 2124 Generic = 4; 2125 Global = 1; 2126 Local = 3; 2127 Constant = 2; 2128 Private = 0; 2129 } 2130 } 2131 }; 2132 2133 /// \brief The GPU profiles supported by the AMDGPU target. 2134 enum GPUKind { 2135 GK_NONE, 2136 GK_R600, 2137 GK_R600_DOUBLE_OPS, 2138 GK_R700, 2139 GK_R700_DOUBLE_OPS, 2140 GK_EVERGREEN, 2141 GK_EVERGREEN_DOUBLE_OPS, 2142 GK_NORTHERN_ISLANDS, 2143 GK_CAYMAN, 2144 GK_GFX6, 2145 GK_GFX7, 2146 GK_GFX8, 2147 GK_GFX9 2148 } GPU; 2149 2150 bool hasFP64:1; 2151 bool hasFMAF:1; 2152 bool hasLDEXPF:1; 2153 const AddrSpace AS; 2154 2155 static bool hasFullSpeedFMAF32(StringRef GPUName) { 2156 return parseAMDGCNName(GPUName) >= GK_GFX9; 2157 } 2158 2159 static bool isAMDGCN(const llvm::Triple &TT) { 2160 return TT.getArch() == llvm::Triple::amdgcn; 2161 } 2162 2163 static bool isGenericZero(const llvm::Triple &TT) { 2164 return TT.getEnvironmentName() == "amdgiz" || 2165 TT.getEnvironmentName() == "amdgizcl"; 2166 } 2167 public: 2168 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 2169 : TargetInfo(Triple) , 2170 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600), 2171 hasFP64(false), 2172 hasFMAF(false), 2173 hasLDEXPF(false), 2174 AS(isGenericZero(Triple)){ 2175 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2176 hasFP64 = true; 2177 hasFMAF = true; 2178 hasLDEXPF = true; 2179 } 2180 auto IsGenericZero = isGenericZero(Triple); 2181 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 2182 (IsGenericZero ? DataLayoutStringSIGenericIsZero : 2183 DataLayoutStringSIPrivateIsZero) 2184 : DataLayoutStringR600); 2185 assert(DataLayout->getAllocaAddrSpace() == AS.Private); 2186 2187 UseAddrSpaceMapMangling = true; 2188 } 2189 2190 void adjust(LangOptions &Opts) override { 2191 TargetInfo::adjust(Opts); 2192 if (isGenericZero(getTriple())) { 2193 AddrSpaceMap = Opts.OpenCL ? &AMDGPUOpenCLGenericIsZeroMap 2194 : &AMDGPUNonOpenCLGenericIsZeroMap; 2195 } else { 2196 AddrSpaceMap = Opts.OpenCL ? &AMDGPUOpenCLPrivateIsZeroMap 2197 : &AMDGPUNonOpenCLPrivateIsZeroMap; 2198 } 2199 } 2200 2201 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 2202 if (GPU <= GK_CAYMAN) 2203 return 32; 2204 2205 if (AddrSpace == AS.Private || AddrSpace == AS.Local) { 2206 return 32; 2207 } 2208 return 64; 2209 } 2210 2211 uint64_t getMaxPointerWidth() const override { 2212 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2213 } 2214 2215 const char * getClobbers() const override { 2216 return ""; 2217 } 2218 2219 ArrayRef<const char *> getGCCRegNames() const override; 2220 2221 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2222 return None; 2223 } 2224 2225 bool validateAsmConstraint(const char *&Name, 2226 TargetInfo::ConstraintInfo &Info) const override { 2227 switch (*Name) { 2228 default: break; 2229 case 'v': // vgpr 2230 case 's': // sgpr 2231 Info.setAllowsRegister(); 2232 return true; 2233 } 2234 return false; 2235 } 2236 2237 bool initFeatureMap(llvm::StringMap<bool> &Features, 2238 DiagnosticsEngine &Diags, StringRef CPU, 2239 const std::vector<std::string> &FeatureVec) const override; 2240 2241 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2242 TargetOptions &TargetOpts) const override { 2243 bool hasFP32Denormals = false; 2244 bool hasFP64Denormals = false; 2245 for (auto &I : TargetOpts.FeaturesAsWritten) { 2246 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2247 hasFP32Denormals = true; 2248 if (I == "+fp64-fp16-denormals" || I == "-fp64-fp16-denormals") 2249 hasFP64Denormals = true; 2250 } 2251 if (!hasFP32Denormals) 2252 TargetOpts.Features.push_back( 2253 (Twine(hasFullSpeedFMAF32(TargetOpts.CPU) && 2254 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str()); 2255 // Always do not flush fp64 or fp16 denorms. 2256 if (!hasFP64Denormals && hasFP64) 2257 TargetOpts.Features.push_back("+fp64-fp16-denormals"); 2258 } 2259 2260 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2261 return llvm::makeArrayRef(BuiltinInfo, 2262 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2263 } 2264 2265 void getTargetDefines(const LangOptions &Opts, 2266 MacroBuilder &Builder) const override { 2267 if (getTriple().getArch() == llvm::Triple::amdgcn) 2268 Builder.defineMacro("__AMDGCN__"); 2269 else 2270 Builder.defineMacro("__R600__"); 2271 2272 if (hasFMAF) 2273 Builder.defineMacro("__HAS_FMAF__"); 2274 if (hasLDEXPF) 2275 Builder.defineMacro("__HAS_LDEXPF__"); 2276 if (hasFP64) 2277 Builder.defineMacro("__HAS_FP64__"); 2278 } 2279 2280 BuiltinVaListKind getBuiltinVaListKind() const override { 2281 return TargetInfo::CharPtrBuiltinVaList; 2282 } 2283 2284 static GPUKind parseR600Name(StringRef Name) { 2285 return llvm::StringSwitch<GPUKind>(Name) 2286 .Case("r600" , GK_R600) 2287 .Case("rv610", GK_R600) 2288 .Case("rv620", GK_R600) 2289 .Case("rv630", GK_R600) 2290 .Case("rv635", GK_R600) 2291 .Case("rs780", GK_R600) 2292 .Case("rs880", GK_R600) 2293 .Case("rv670", GK_R600_DOUBLE_OPS) 2294 .Case("rv710", GK_R700) 2295 .Case("rv730", GK_R700) 2296 .Case("rv740", GK_R700_DOUBLE_OPS) 2297 .Case("rv770", GK_R700_DOUBLE_OPS) 2298 .Case("palm", GK_EVERGREEN) 2299 .Case("cedar", GK_EVERGREEN) 2300 .Case("sumo", GK_EVERGREEN) 2301 .Case("sumo2", GK_EVERGREEN) 2302 .Case("redwood", GK_EVERGREEN) 2303 .Case("juniper", GK_EVERGREEN) 2304 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2305 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2306 .Case("barts", GK_NORTHERN_ISLANDS) 2307 .Case("turks", GK_NORTHERN_ISLANDS) 2308 .Case("caicos", GK_NORTHERN_ISLANDS) 2309 .Case("cayman", GK_CAYMAN) 2310 .Case("aruba", GK_CAYMAN) 2311 .Default(GK_NONE); 2312 } 2313 2314 static GPUKind parseAMDGCNName(StringRef Name) { 2315 return llvm::StringSwitch<GPUKind>(Name) 2316 .Case("tahiti", GK_GFX6) 2317 .Case("pitcairn", GK_GFX6) 2318 .Case("verde", GK_GFX6) 2319 .Case("oland", GK_GFX6) 2320 .Case("hainan", GK_GFX6) 2321 .Case("bonaire", GK_GFX7) 2322 .Case("kabini", GK_GFX7) 2323 .Case("kaveri", GK_GFX7) 2324 .Case("hawaii", GK_GFX7) 2325 .Case("mullins", GK_GFX7) 2326 .Case("gfx700", GK_GFX7) 2327 .Case("gfx701", GK_GFX7) 2328 .Case("gfx702", GK_GFX7) 2329 .Case("tonga", GK_GFX8) 2330 .Case("iceland", GK_GFX8) 2331 .Case("carrizo", GK_GFX8) 2332 .Case("fiji", GK_GFX8) 2333 .Case("stoney", GK_GFX8) 2334 .Case("polaris10", GK_GFX8) 2335 .Case("polaris11", GK_GFX8) 2336 .Case("gfx800", GK_GFX8) 2337 .Case("gfx801", GK_GFX8) 2338 .Case("gfx802", GK_GFX8) 2339 .Case("gfx803", GK_GFX8) 2340 .Case("gfx804", GK_GFX8) 2341 .Case("gfx810", GK_GFX8) 2342 .Case("gfx900", GK_GFX9) 2343 .Case("gfx901", GK_GFX9) 2344 .Default(GK_NONE); 2345 } 2346 2347 bool setCPU(const std::string &Name) override { 2348 if (getTriple().getArch() == llvm::Triple::amdgcn) 2349 GPU = parseAMDGCNName(Name); 2350 else 2351 GPU = parseR600Name(Name); 2352 2353 return GPU != GK_NONE; 2354 } 2355 2356 void setSupportedOpenCLOpts() override { 2357 auto &Opts = getSupportedOpenCLOpts(); 2358 Opts.support("cl_clang_storage_class_specifiers"); 2359 Opts.support("cl_khr_icd"); 2360 2361 if (hasFP64) 2362 Opts.support("cl_khr_fp64"); 2363 if (GPU >= GK_EVERGREEN) { 2364 Opts.support("cl_khr_byte_addressable_store"); 2365 Opts.support("cl_khr_global_int32_base_atomics"); 2366 Opts.support("cl_khr_global_int32_extended_atomics"); 2367 Opts.support("cl_khr_local_int32_base_atomics"); 2368 Opts.support("cl_khr_local_int32_extended_atomics"); 2369 } 2370 if (GPU >= GK_GFX6) { 2371 Opts.support("cl_khr_fp16"); 2372 Opts.support("cl_khr_int64_base_atomics"); 2373 Opts.support("cl_khr_int64_extended_atomics"); 2374 Opts.support("cl_khr_mipmap_image"); 2375 Opts.support("cl_khr_subgroups"); 2376 Opts.support("cl_khr_3d_image_writes"); 2377 Opts.support("cl_amd_media_ops"); 2378 Opts.support("cl_amd_media_ops2"); 2379 } 2380 } 2381 2382 LangAS::ID getOpenCLImageAddrSpace() const override { 2383 return LangAS::opencl_constant; 2384 } 2385 2386 /// \returns Target specific vtbl ptr address space. 2387 unsigned getVtblPtrAddressSpace() const override { 2388 // \todo: We currently have address spaces defined in AMDGPU Backend. It 2389 // would be nice if we could use it here instead of using bare numbers (same 2390 // applies to getDWARFAddressSpace). 2391 return 2; // constant. 2392 } 2393 2394 /// \returns If a target requires an address within a target specific address 2395 /// space \p AddressSpace to be converted in order to be used, then return the 2396 /// corresponding target specific DWARF address space. 2397 /// 2398 /// \returns Otherwise return None and no conversion will be emitted in the 2399 /// DWARF. 2400 Optional<unsigned> getDWARFAddressSpace( 2401 unsigned AddressSpace) const override { 2402 const unsigned DWARF_Private = 1; 2403 const unsigned DWARF_Local = 2; 2404 if (AddressSpace == AS.Private) { 2405 return DWARF_Private; 2406 } else if (AddressSpace == AS.Local) { 2407 return DWARF_Local; 2408 } else { 2409 return None; 2410 } 2411 } 2412 2413 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2414 switch (CC) { 2415 default: 2416 return CCCR_Warning; 2417 case CC_C: 2418 case CC_OpenCLKernel: 2419 return CCCR_OK; 2420 } 2421 } 2422 2423 // In amdgcn target the null pointer in global, constant, and generic 2424 // address space has value 0 but in private and local address space has 2425 // value ~0. 2426 uint64_t getNullPointerValue(unsigned AS) const override { 2427 return AS == LangAS::opencl_local ? ~0 : 0; 2428 } 2429 }; 2430 2431 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2432 #define BUILTIN(ID, TYPE, ATTRS) \ 2433 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2434 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2435 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2436 #include "clang/Basic/BuiltinsAMDGPU.def" 2437 }; 2438 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2439 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2440 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2441 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2442 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2443 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2444 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2445 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2446 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2447 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2448 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2449 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2450 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2451 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2452 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2453 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2454 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2455 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2456 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2457 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2458 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2459 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2460 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2461 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2462 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2463 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2464 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2465 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2466 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2467 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2468 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2469 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2470 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2471 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2472 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2473 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2474 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2475 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2476 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2477 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2478 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2479 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2480 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2481 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2482 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2483 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2484 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2485 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2486 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2487 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2488 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2489 }; 2490 2491 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2492 return llvm::makeArrayRef(GCCRegNames); 2493 } 2494 2495 bool AMDGPUTargetInfo::initFeatureMap( 2496 llvm::StringMap<bool> &Features, 2497 DiagnosticsEngine &Diags, StringRef CPU, 2498 const std::vector<std::string> &FeatureVec) const { 2499 2500 // XXX - What does the member GPU mean if device name string passed here? 2501 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2502 if (CPU.empty()) 2503 CPU = "tahiti"; 2504 2505 switch (parseAMDGCNName(CPU)) { 2506 case GK_GFX6: 2507 case GK_GFX7: 2508 break; 2509 2510 case GK_GFX9: 2511 Features["gfx9-insts"] = true; 2512 LLVM_FALLTHROUGH; 2513 case GK_GFX8: 2514 Features["s-memrealtime"] = true; 2515 Features["16-bit-insts"] = true; 2516 Features["dpp"] = true; 2517 break; 2518 2519 case GK_NONE: 2520 return false; 2521 default: 2522 llvm_unreachable("unhandled subtarget"); 2523 } 2524 } else { 2525 if (CPU.empty()) 2526 CPU = "r600"; 2527 2528 switch (parseR600Name(CPU)) { 2529 case GK_R600: 2530 case GK_R700: 2531 case GK_EVERGREEN: 2532 case GK_NORTHERN_ISLANDS: 2533 break; 2534 case GK_R600_DOUBLE_OPS: 2535 case GK_R700_DOUBLE_OPS: 2536 case GK_EVERGREEN_DOUBLE_OPS: 2537 case GK_CAYMAN: 2538 Features["fp64"] = true; 2539 break; 2540 case GK_NONE: 2541 return false; 2542 default: 2543 llvm_unreachable("unhandled subtarget"); 2544 } 2545 } 2546 2547 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2548 } 2549 2550 const Builtin::Info BuiltinInfoX86[] = { 2551 #define BUILTIN(ID, TYPE, ATTRS) \ 2552 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2553 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2554 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2555 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2556 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2557 #include "clang/Basic/BuiltinsX86.def" 2558 2559 #define BUILTIN(ID, TYPE, ATTRS) \ 2560 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2561 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2562 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2563 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2564 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2565 #include "clang/Basic/BuiltinsX86_64.def" 2566 }; 2567 2568 2569 static const char* const GCCRegNames[] = { 2570 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2571 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2572 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2573 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2574 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2575 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2576 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2577 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2578 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2579 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2580 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2581 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2582 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2583 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2584 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2585 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2586 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2587 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", 2588 }; 2589 2590 const TargetInfo::AddlRegName AddlRegNames[] = { 2591 { { "al", "ah", "eax", "rax" }, 0 }, 2592 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2593 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2594 { { "dl", "dh", "edx", "rdx" }, 1 }, 2595 { { "esi", "rsi" }, 4 }, 2596 { { "edi", "rdi" }, 5 }, 2597 { { "esp", "rsp" }, 7 }, 2598 { { "ebp", "rbp" }, 6 }, 2599 { { "r8d", "r8w", "r8b" }, 38 }, 2600 { { "r9d", "r9w", "r9b" }, 39 }, 2601 { { "r10d", "r10w", "r10b" }, 40 }, 2602 { { "r11d", "r11w", "r11b" }, 41 }, 2603 { { "r12d", "r12w", "r12b" }, 42 }, 2604 { { "r13d", "r13w", "r13b" }, 43 }, 2605 { { "r14d", "r14w", "r14b" }, 44 }, 2606 { { "r15d", "r15w", "r15b" }, 45 }, 2607 }; 2608 2609 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2610 // most of the implementation can be shared. 2611 class X86TargetInfo : public TargetInfo { 2612 enum X86SSEEnum { 2613 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2614 } SSELevel = NoSSE; 2615 enum MMX3DNowEnum { 2616 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2617 } MMX3DNowLevel = NoMMX3DNow; 2618 enum XOPEnum { 2619 NoXOP, 2620 SSE4A, 2621 FMA4, 2622 XOP 2623 } XOPLevel = NoXOP; 2624 2625 bool HasAES = false; 2626 bool HasPCLMUL = false; 2627 bool HasLZCNT = false; 2628 bool HasRDRND = false; 2629 bool HasFSGSBASE = false; 2630 bool HasBMI = false; 2631 bool HasBMI2 = false; 2632 bool HasPOPCNT = false; 2633 bool HasRTM = false; 2634 bool HasPRFCHW = false; 2635 bool HasRDSEED = false; 2636 bool HasADX = false; 2637 bool HasTBM = false; 2638 bool HasLWP = false; 2639 bool HasFMA = false; 2640 bool HasF16C = false; 2641 bool HasAVX512CD = false; 2642 bool HasAVX512VPOPCNTDQ = false; 2643 bool HasAVX512ER = false; 2644 bool HasAVX512PF = false; 2645 bool HasAVX512DQ = false; 2646 bool HasAVX512BW = false; 2647 bool HasAVX512VL = false; 2648 bool HasAVX512VBMI = false; 2649 bool HasAVX512IFMA = false; 2650 bool HasSHA = false; 2651 bool HasMPX = false; 2652 bool HasSGX = false; 2653 bool HasCX16 = false; 2654 bool HasFXSR = false; 2655 bool HasXSAVE = false; 2656 bool HasXSAVEOPT = false; 2657 bool HasXSAVEC = false; 2658 bool HasXSAVES = false; 2659 bool HasMWAITX = false; 2660 bool HasCLZERO = false; 2661 bool HasPKU = false; 2662 bool HasCLFLUSHOPT = false; 2663 bool HasCLWB = false; 2664 bool HasMOVBE = false; 2665 bool HasPREFETCHWT1 = false; 2666 2667 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2668 /// 2669 /// Each enumeration represents a particular CPU supported by Clang. These 2670 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2671 enum CPUKind { 2672 CK_Generic, 2673 2674 /// \name i386 2675 /// i386-generation processors. 2676 //@{ 2677 CK_i386, 2678 //@} 2679 2680 /// \name i486 2681 /// i486-generation processors. 2682 //@{ 2683 CK_i486, 2684 CK_WinChipC6, 2685 CK_WinChip2, 2686 CK_C3, 2687 //@} 2688 2689 /// \name i586 2690 /// i586-generation processors, P5 microarchitecture based. 2691 //@{ 2692 CK_i586, 2693 CK_Pentium, 2694 CK_PentiumMMX, 2695 //@} 2696 2697 /// \name i686 2698 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2699 //@{ 2700 CK_i686, 2701 CK_PentiumPro, 2702 CK_Pentium2, 2703 CK_Pentium3, 2704 CK_Pentium3M, 2705 CK_PentiumM, 2706 CK_C3_2, 2707 2708 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2709 /// Clang however has some logic to suport this. 2710 // FIXME: Warn, deprecate, and potentially remove this. 2711 CK_Yonah, 2712 //@} 2713 2714 /// \name Netburst 2715 /// Netburst microarchitecture based processors. 2716 //@{ 2717 CK_Pentium4, 2718 CK_Pentium4M, 2719 CK_Prescott, 2720 CK_Nocona, 2721 //@} 2722 2723 /// \name Core 2724 /// Core microarchitecture based processors. 2725 //@{ 2726 CK_Core2, 2727 2728 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2729 /// codename which GCC no longer accepts as an option to -march, but Clang 2730 /// has some logic for recognizing it. 2731 // FIXME: Warn, deprecate, and potentially remove this. 2732 CK_Penryn, 2733 //@} 2734 2735 /// \name Atom 2736 /// Atom processors 2737 //@{ 2738 CK_Bonnell, 2739 CK_Silvermont, 2740 CK_Goldmont, 2741 //@} 2742 2743 /// \name Nehalem 2744 /// Nehalem microarchitecture based processors. 2745 CK_Nehalem, 2746 2747 /// \name Westmere 2748 /// Westmere microarchitecture based processors. 2749 CK_Westmere, 2750 2751 /// \name Sandy Bridge 2752 /// Sandy Bridge microarchitecture based processors. 2753 CK_SandyBridge, 2754 2755 /// \name Ivy Bridge 2756 /// Ivy Bridge microarchitecture based processors. 2757 CK_IvyBridge, 2758 2759 /// \name Haswell 2760 /// Haswell microarchitecture based processors. 2761 CK_Haswell, 2762 2763 /// \name Broadwell 2764 /// Broadwell microarchitecture based processors. 2765 CK_Broadwell, 2766 2767 /// \name Skylake Client 2768 /// Skylake client microarchitecture based processors. 2769 CK_SkylakeClient, 2770 2771 /// \name Skylake Server 2772 /// Skylake server microarchitecture based processors. 2773 CK_SkylakeServer, 2774 2775 /// \name Cannonlake Client 2776 /// Cannonlake client microarchitecture based processors. 2777 CK_Cannonlake, 2778 2779 /// \name Knights Landing 2780 /// Knights Landing processor. 2781 CK_KNL, 2782 2783 /// \name Lakemont 2784 /// Lakemont microarchitecture based processors. 2785 CK_Lakemont, 2786 2787 /// \name K6 2788 /// K6 architecture processors. 2789 //@{ 2790 CK_K6, 2791 CK_K6_2, 2792 CK_K6_3, 2793 //@} 2794 2795 /// \name K7 2796 /// K7 architecture processors. 2797 //@{ 2798 CK_Athlon, 2799 CK_AthlonThunderbird, 2800 CK_Athlon4, 2801 CK_AthlonXP, 2802 CK_AthlonMP, 2803 //@} 2804 2805 /// \name K8 2806 /// K8 architecture processors. 2807 //@{ 2808 CK_Athlon64, 2809 CK_Athlon64SSE3, 2810 CK_AthlonFX, 2811 CK_K8, 2812 CK_K8SSE3, 2813 CK_Opteron, 2814 CK_OpteronSSE3, 2815 CK_AMDFAM10, 2816 //@} 2817 2818 /// \name Bobcat 2819 /// Bobcat architecture processors. 2820 //@{ 2821 CK_BTVER1, 2822 CK_BTVER2, 2823 //@} 2824 2825 /// \name Bulldozer 2826 /// Bulldozer architecture processors. 2827 //@{ 2828 CK_BDVER1, 2829 CK_BDVER2, 2830 CK_BDVER3, 2831 CK_BDVER4, 2832 //@} 2833 2834 /// \name zen 2835 /// Zen architecture processors. 2836 //@{ 2837 CK_ZNVER1, 2838 //@} 2839 2840 /// This specification is deprecated and will be removed in the future. 2841 /// Users should prefer \see CK_K8. 2842 // FIXME: Warn on this when the CPU is set to it. 2843 //@{ 2844 CK_x86_64, 2845 //@} 2846 2847 /// \name Geode 2848 /// Geode processors. 2849 //@{ 2850 CK_Geode 2851 //@} 2852 } CPU = CK_Generic; 2853 2854 CPUKind getCPUKind(StringRef CPU) const { 2855 return llvm::StringSwitch<CPUKind>(CPU) 2856 .Case("i386", CK_i386) 2857 .Case("i486", CK_i486) 2858 .Case("winchip-c6", CK_WinChipC6) 2859 .Case("winchip2", CK_WinChip2) 2860 .Case("c3", CK_C3) 2861 .Case("i586", CK_i586) 2862 .Case("pentium", CK_Pentium) 2863 .Case("pentium-mmx", CK_PentiumMMX) 2864 .Case("i686", CK_i686) 2865 .Case("pentiumpro", CK_PentiumPro) 2866 .Case("pentium2", CK_Pentium2) 2867 .Case("pentium3", CK_Pentium3) 2868 .Case("pentium3m", CK_Pentium3M) 2869 .Case("pentium-m", CK_PentiumM) 2870 .Case("c3-2", CK_C3_2) 2871 .Case("yonah", CK_Yonah) 2872 .Case("pentium4", CK_Pentium4) 2873 .Case("pentium4m", CK_Pentium4M) 2874 .Case("prescott", CK_Prescott) 2875 .Case("nocona", CK_Nocona) 2876 .Case("core2", CK_Core2) 2877 .Case("penryn", CK_Penryn) 2878 .Case("bonnell", CK_Bonnell) 2879 .Case("atom", CK_Bonnell) // Legacy name. 2880 .Case("silvermont", CK_Silvermont) 2881 .Case("slm", CK_Silvermont) // Legacy name. 2882 .Case("goldmont", CK_Goldmont) 2883 .Case("nehalem", CK_Nehalem) 2884 .Case("corei7", CK_Nehalem) // Legacy name. 2885 .Case("westmere", CK_Westmere) 2886 .Case("sandybridge", CK_SandyBridge) 2887 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2888 .Case("ivybridge", CK_IvyBridge) 2889 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2890 .Case("haswell", CK_Haswell) 2891 .Case("core-avx2", CK_Haswell) // Legacy name. 2892 .Case("broadwell", CK_Broadwell) 2893 .Case("skylake", CK_SkylakeClient) 2894 .Case("skylake-avx512", CK_SkylakeServer) 2895 .Case("skx", CK_SkylakeServer) // Legacy name. 2896 .Case("cannonlake", CK_Cannonlake) 2897 .Case("knl", CK_KNL) 2898 .Case("lakemont", CK_Lakemont) 2899 .Case("k6", CK_K6) 2900 .Case("k6-2", CK_K6_2) 2901 .Case("k6-3", CK_K6_3) 2902 .Case("athlon", CK_Athlon) 2903 .Case("athlon-tbird", CK_AthlonThunderbird) 2904 .Case("athlon-4", CK_Athlon4) 2905 .Case("athlon-xp", CK_AthlonXP) 2906 .Case("athlon-mp", CK_AthlonMP) 2907 .Case("athlon64", CK_Athlon64) 2908 .Case("athlon64-sse3", CK_Athlon64SSE3) 2909 .Case("athlon-fx", CK_AthlonFX) 2910 .Case("k8", CK_K8) 2911 .Case("k8-sse3", CK_K8SSE3) 2912 .Case("opteron", CK_Opteron) 2913 .Case("opteron-sse3", CK_OpteronSSE3) 2914 .Case("barcelona", CK_AMDFAM10) 2915 .Case("amdfam10", CK_AMDFAM10) 2916 .Case("btver1", CK_BTVER1) 2917 .Case("btver2", CK_BTVER2) 2918 .Case("bdver1", CK_BDVER1) 2919 .Case("bdver2", CK_BDVER2) 2920 .Case("bdver3", CK_BDVER3) 2921 .Case("bdver4", CK_BDVER4) 2922 .Case("znver1", CK_ZNVER1) 2923 .Case("x86-64", CK_x86_64) 2924 .Case("geode", CK_Geode) 2925 .Default(CK_Generic); 2926 } 2927 2928 enum FPMathKind { 2929 FP_Default, 2930 FP_SSE, 2931 FP_387 2932 } FPMath = FP_Default; 2933 2934 public: 2935 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2936 : TargetInfo(Triple) { 2937 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 2938 } 2939 unsigned getFloatEvalMethod() const override { 2940 // X87 evaluates with 80 bits "long double" precision. 2941 return SSELevel == NoSSE ? 2 : 0; 2942 } 2943 ArrayRef<const char *> getGCCRegNames() const override { 2944 return llvm::makeArrayRef(GCCRegNames); 2945 } 2946 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2947 return None; 2948 } 2949 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2950 return llvm::makeArrayRef(AddlRegNames); 2951 } 2952 bool validateCpuSupports(StringRef Name) const override; 2953 bool validateAsmConstraint(const char *&Name, 2954 TargetInfo::ConstraintInfo &info) const override; 2955 2956 bool validateGlobalRegisterVariable(StringRef RegName, 2957 unsigned RegSize, 2958 bool &HasSizeMismatch) const override { 2959 // esp and ebp are the only 32-bit registers the x86 backend can currently 2960 // handle. 2961 if (RegName.equals("esp") || RegName.equals("ebp")) { 2962 // Check that the register size is 32-bit. 2963 HasSizeMismatch = RegSize != 32; 2964 return true; 2965 } 2966 2967 return false; 2968 } 2969 2970 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2971 2972 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2973 2974 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2975 2976 std::string convertConstraint(const char *&Constraint) const override; 2977 const char *getClobbers() const override { 2978 return "~{dirflag},~{fpsr},~{flags}"; 2979 } 2980 2981 StringRef getConstraintRegister(const StringRef &Constraint, 2982 const StringRef &Expression) const override { 2983 StringRef::iterator I, E; 2984 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) { 2985 if (isalpha(*I)) 2986 break; 2987 } 2988 if (I == E) 2989 return ""; 2990 switch (*I) { 2991 // For the register constraints, return the matching register name 2992 case 'a': 2993 return "ax"; 2994 case 'b': 2995 return "bx"; 2996 case 'c': 2997 return "cx"; 2998 case 'd': 2999 return "dx"; 3000 case 'S': 3001 return "si"; 3002 case 'D': 3003 return "di"; 3004 // In case the constraint is 'r' we need to return Expression 3005 case 'r': 3006 return Expression; 3007 default: 3008 // Default value if there is no constraint for the register 3009 return ""; 3010 } 3011 return ""; 3012 } 3013 3014 void getTargetDefines(const LangOptions &Opts, 3015 MacroBuilder &Builder) const override; 3016 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 3017 bool Enabled); 3018 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 3019 bool Enabled); 3020 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3021 bool Enabled); 3022 void setFeatureEnabled(llvm::StringMap<bool> &Features, 3023 StringRef Name, bool Enabled) const override { 3024 setFeatureEnabledImpl(Features, Name, Enabled); 3025 } 3026 // This exists purely to cut down on the number of virtual calls in 3027 // initFeatureMap which calls this repeatedly. 3028 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3029 StringRef Name, bool Enabled); 3030 bool 3031 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 3032 StringRef CPU, 3033 const std::vector<std::string> &FeaturesVec) const override; 3034 bool hasFeature(StringRef Feature) const override; 3035 bool handleTargetFeatures(std::vector<std::string> &Features, 3036 DiagnosticsEngine &Diags) override; 3037 StringRef getABI() const override { 3038 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 3039 return "avx512"; 3040 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 3041 return "avx"; 3042 if (getTriple().getArch() == llvm::Triple::x86 && 3043 MMX3DNowLevel == NoMMX3DNow) 3044 return "no-mmx"; 3045 return ""; 3046 } 3047 bool setCPU(const std::string &Name) override { 3048 CPU = getCPUKind(Name); 3049 3050 // Perform any per-CPU checks necessary to determine if this CPU is 3051 // acceptable. 3052 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 3053 // invalid without explaining *why*. 3054 switch (CPU) { 3055 case CK_Generic: 3056 // No processor selected! 3057 return false; 3058 3059 case CK_i386: 3060 case CK_i486: 3061 case CK_WinChipC6: 3062 case CK_WinChip2: 3063 case CK_C3: 3064 case CK_i586: 3065 case CK_Pentium: 3066 case CK_PentiumMMX: 3067 case CK_i686: 3068 case CK_PentiumPro: 3069 case CK_Pentium2: 3070 case CK_Pentium3: 3071 case CK_Pentium3M: 3072 case CK_PentiumM: 3073 case CK_Yonah: 3074 case CK_C3_2: 3075 case CK_Pentium4: 3076 case CK_Pentium4M: 3077 case CK_Lakemont: 3078 case CK_Prescott: 3079 case CK_K6: 3080 case CK_K6_2: 3081 case CK_K6_3: 3082 case CK_Athlon: 3083 case CK_AthlonThunderbird: 3084 case CK_Athlon4: 3085 case CK_AthlonXP: 3086 case CK_AthlonMP: 3087 case CK_Geode: 3088 // Only accept certain architectures when compiling in 32-bit mode. 3089 if (getTriple().getArch() != llvm::Triple::x86) 3090 return false; 3091 3092 // Fallthrough 3093 case CK_Nocona: 3094 case CK_Core2: 3095 case CK_Penryn: 3096 case CK_Bonnell: 3097 case CK_Silvermont: 3098 case CK_Goldmont: 3099 case CK_Nehalem: 3100 case CK_Westmere: 3101 case CK_SandyBridge: 3102 case CK_IvyBridge: 3103 case CK_Haswell: 3104 case CK_Broadwell: 3105 case CK_SkylakeClient: 3106 case CK_SkylakeServer: 3107 case CK_Cannonlake: 3108 case CK_KNL: 3109 case CK_Athlon64: 3110 case CK_Athlon64SSE3: 3111 case CK_AthlonFX: 3112 case CK_K8: 3113 case CK_K8SSE3: 3114 case CK_Opteron: 3115 case CK_OpteronSSE3: 3116 case CK_AMDFAM10: 3117 case CK_BTVER1: 3118 case CK_BTVER2: 3119 case CK_BDVER1: 3120 case CK_BDVER2: 3121 case CK_BDVER3: 3122 case CK_BDVER4: 3123 case CK_ZNVER1: 3124 case CK_x86_64: 3125 return true; 3126 } 3127 llvm_unreachable("Unhandled CPU kind"); 3128 } 3129 3130 bool setFPMath(StringRef Name) override; 3131 3132 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3133 // Most of the non-ARM calling conventions are i386 conventions. 3134 switch (CC) { 3135 case CC_X86ThisCall: 3136 case CC_X86FastCall: 3137 case CC_X86StdCall: 3138 case CC_X86VectorCall: 3139 case CC_X86RegCall: 3140 case CC_C: 3141 case CC_Swift: 3142 case CC_X86Pascal: 3143 case CC_IntelOclBicc: 3144 case CC_OpenCLKernel: 3145 return CCCR_OK; 3146 default: 3147 return CCCR_Warning; 3148 } 3149 } 3150 3151 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3152 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 3153 } 3154 3155 bool hasSjLjLowering() const override { 3156 return true; 3157 } 3158 3159 void setSupportedOpenCLOpts() override { 3160 getSupportedOpenCLOpts().supportAll(); 3161 } 3162 }; 3163 3164 bool X86TargetInfo::setFPMath(StringRef Name) { 3165 if (Name == "387") { 3166 FPMath = FP_387; 3167 return true; 3168 } 3169 if (Name == "sse") { 3170 FPMath = FP_SSE; 3171 return true; 3172 } 3173 return false; 3174 } 3175 3176 bool X86TargetInfo::initFeatureMap( 3177 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 3178 const std::vector<std::string> &FeaturesVec) const { 3179 // FIXME: This *really* should not be here. 3180 // X86_64 always has SSE2. 3181 if (getTriple().getArch() == llvm::Triple::x86_64) 3182 setFeatureEnabledImpl(Features, "sse2", true); 3183 3184 const CPUKind Kind = getCPUKind(CPU); 3185 3186 // Enable X87 for all X86 processors but Lakemont. 3187 if (Kind != CK_Lakemont) 3188 setFeatureEnabledImpl(Features, "x87", true); 3189 3190 switch (Kind) { 3191 case CK_Generic: 3192 case CK_i386: 3193 case CK_i486: 3194 case CK_i586: 3195 case CK_Pentium: 3196 case CK_i686: 3197 case CK_PentiumPro: 3198 case CK_Lakemont: 3199 break; 3200 case CK_PentiumMMX: 3201 case CK_Pentium2: 3202 case CK_K6: 3203 case CK_WinChipC6: 3204 setFeatureEnabledImpl(Features, "mmx", true); 3205 break; 3206 case CK_Pentium3: 3207 case CK_Pentium3M: 3208 case CK_C3_2: 3209 setFeatureEnabledImpl(Features, "sse", true); 3210 setFeatureEnabledImpl(Features, "fxsr", true); 3211 break; 3212 case CK_PentiumM: 3213 case CK_Pentium4: 3214 case CK_Pentium4M: 3215 case CK_x86_64: 3216 setFeatureEnabledImpl(Features, "sse2", true); 3217 setFeatureEnabledImpl(Features, "fxsr", true); 3218 break; 3219 case CK_Yonah: 3220 case CK_Prescott: 3221 case CK_Nocona: 3222 setFeatureEnabledImpl(Features, "sse3", true); 3223 setFeatureEnabledImpl(Features, "fxsr", true); 3224 setFeatureEnabledImpl(Features, "cx16", true); 3225 break; 3226 case CK_Core2: 3227 case CK_Bonnell: 3228 setFeatureEnabledImpl(Features, "ssse3", true); 3229 setFeatureEnabledImpl(Features, "fxsr", true); 3230 setFeatureEnabledImpl(Features, "cx16", true); 3231 break; 3232 case CK_Penryn: 3233 setFeatureEnabledImpl(Features, "sse4.1", true); 3234 setFeatureEnabledImpl(Features, "fxsr", true); 3235 setFeatureEnabledImpl(Features, "cx16", true); 3236 break; 3237 case CK_Cannonlake: 3238 setFeatureEnabledImpl(Features, "avx512ifma", true); 3239 setFeatureEnabledImpl(Features, "avx512vbmi", true); 3240 setFeatureEnabledImpl(Features, "sha", true); 3241 LLVM_FALLTHROUGH; 3242 case CK_SkylakeServer: 3243 setFeatureEnabledImpl(Features, "avx512f", true); 3244 setFeatureEnabledImpl(Features, "avx512cd", true); 3245 setFeatureEnabledImpl(Features, "avx512dq", true); 3246 setFeatureEnabledImpl(Features, "avx512bw", true); 3247 setFeatureEnabledImpl(Features, "avx512vl", true); 3248 setFeatureEnabledImpl(Features, "pku", true); 3249 setFeatureEnabledImpl(Features, "clwb", true); 3250 LLVM_FALLTHROUGH; 3251 case CK_SkylakeClient: 3252 setFeatureEnabledImpl(Features, "xsavec", true); 3253 setFeatureEnabledImpl(Features, "xsaves", true); 3254 setFeatureEnabledImpl(Features, "mpx", true); 3255 setFeatureEnabledImpl(Features, "sgx", true); 3256 setFeatureEnabledImpl(Features, "clflushopt", true); 3257 setFeatureEnabledImpl(Features, "rtm", true); 3258 LLVM_FALLTHROUGH; 3259 case CK_Broadwell: 3260 setFeatureEnabledImpl(Features, "rdseed", true); 3261 setFeatureEnabledImpl(Features, "adx", true); 3262 LLVM_FALLTHROUGH; 3263 case CK_Haswell: 3264 setFeatureEnabledImpl(Features, "avx2", true); 3265 setFeatureEnabledImpl(Features, "lzcnt", true); 3266 setFeatureEnabledImpl(Features, "bmi", true); 3267 setFeatureEnabledImpl(Features, "bmi2", true); 3268 setFeatureEnabledImpl(Features, "fma", true); 3269 setFeatureEnabledImpl(Features, "movbe", true); 3270 LLVM_FALLTHROUGH; 3271 case CK_IvyBridge: 3272 setFeatureEnabledImpl(Features, "rdrnd", true); 3273 setFeatureEnabledImpl(Features, "f16c", true); 3274 setFeatureEnabledImpl(Features, "fsgsbase", true); 3275 LLVM_FALLTHROUGH; 3276 case CK_SandyBridge: 3277 setFeatureEnabledImpl(Features, "avx", true); 3278 setFeatureEnabledImpl(Features, "xsave", true); 3279 setFeatureEnabledImpl(Features, "xsaveopt", true); 3280 LLVM_FALLTHROUGH; 3281 case CK_Westmere: 3282 case CK_Silvermont: 3283 setFeatureEnabledImpl(Features, "aes", true); 3284 setFeatureEnabledImpl(Features, "pclmul", true); 3285 LLVM_FALLTHROUGH; 3286 case CK_Nehalem: 3287 setFeatureEnabledImpl(Features, "sse4.2", true); 3288 setFeatureEnabledImpl(Features, "fxsr", true); 3289 setFeatureEnabledImpl(Features, "cx16", true); 3290 break; 3291 case CK_Goldmont: 3292 setFeatureEnabledImpl(Features, "sha", true); 3293 setFeatureEnabledImpl(Features, "rdseed", true); 3294 setFeatureEnabledImpl(Features, "xsave", true); 3295 setFeatureEnabledImpl(Features, "xsaveopt", true); 3296 setFeatureEnabledImpl(Features, "xsavec", true); 3297 setFeatureEnabledImpl(Features, "xsaves", true); 3298 setFeatureEnabledImpl(Features, "clflushopt", true); 3299 setFeatureEnabledImpl(Features, "mpx", true); 3300 setFeatureEnabledImpl(Features, "aes", true); 3301 setFeatureEnabledImpl(Features, "pclmul", true); 3302 setFeatureEnabledImpl(Features, "sse4.2", true); 3303 setFeatureEnabledImpl(Features, "fxsr", true); 3304 setFeatureEnabledImpl(Features, "cx16", true); 3305 break; 3306 case CK_KNL: 3307 setFeatureEnabledImpl(Features, "avx512f", true); 3308 setFeatureEnabledImpl(Features, "avx512cd", true); 3309 setFeatureEnabledImpl(Features, "avx512er", true); 3310 setFeatureEnabledImpl(Features, "avx512pf", true); 3311 setFeatureEnabledImpl(Features, "prefetchwt1", true); 3312 setFeatureEnabledImpl(Features, "fxsr", true); 3313 setFeatureEnabledImpl(Features, "rdseed", true); 3314 setFeatureEnabledImpl(Features, "adx", true); 3315 setFeatureEnabledImpl(Features, "lzcnt", true); 3316 setFeatureEnabledImpl(Features, "bmi", true); 3317 setFeatureEnabledImpl(Features, "bmi2", true); 3318 setFeatureEnabledImpl(Features, "rtm", true); 3319 setFeatureEnabledImpl(Features, "fma", true); 3320 setFeatureEnabledImpl(Features, "rdrnd", true); 3321 setFeatureEnabledImpl(Features, "f16c", true); 3322 setFeatureEnabledImpl(Features, "fsgsbase", true); 3323 setFeatureEnabledImpl(Features, "aes", true); 3324 setFeatureEnabledImpl(Features, "pclmul", true); 3325 setFeatureEnabledImpl(Features, "cx16", true); 3326 setFeatureEnabledImpl(Features, "xsaveopt", true); 3327 setFeatureEnabledImpl(Features, "xsave", true); 3328 setFeatureEnabledImpl(Features, "movbe", true); 3329 break; 3330 case CK_K6_2: 3331 case CK_K6_3: 3332 case CK_WinChip2: 3333 case CK_C3: 3334 setFeatureEnabledImpl(Features, "3dnow", true); 3335 break; 3336 case CK_Athlon: 3337 case CK_AthlonThunderbird: 3338 case CK_Geode: 3339 setFeatureEnabledImpl(Features, "3dnowa", true); 3340 break; 3341 case CK_Athlon4: 3342 case CK_AthlonXP: 3343 case CK_AthlonMP: 3344 setFeatureEnabledImpl(Features, "sse", true); 3345 setFeatureEnabledImpl(Features, "3dnowa", true); 3346 setFeatureEnabledImpl(Features, "fxsr", true); 3347 break; 3348 case CK_K8: 3349 case CK_Opteron: 3350 case CK_Athlon64: 3351 case CK_AthlonFX: 3352 setFeatureEnabledImpl(Features, "sse2", true); 3353 setFeatureEnabledImpl(Features, "3dnowa", true); 3354 setFeatureEnabledImpl(Features, "fxsr", true); 3355 break; 3356 case CK_AMDFAM10: 3357 setFeatureEnabledImpl(Features, "sse4a", true); 3358 setFeatureEnabledImpl(Features, "lzcnt", true); 3359 setFeatureEnabledImpl(Features, "popcnt", true); 3360 LLVM_FALLTHROUGH; 3361 case CK_K8SSE3: 3362 case CK_OpteronSSE3: 3363 case CK_Athlon64SSE3: 3364 setFeatureEnabledImpl(Features, "sse3", true); 3365 setFeatureEnabledImpl(Features, "3dnowa", true); 3366 setFeatureEnabledImpl(Features, "fxsr", true); 3367 break; 3368 case CK_BTVER2: 3369 setFeatureEnabledImpl(Features, "avx", true); 3370 setFeatureEnabledImpl(Features, "aes", true); 3371 setFeatureEnabledImpl(Features, "pclmul", true); 3372 setFeatureEnabledImpl(Features, "bmi", true); 3373 setFeatureEnabledImpl(Features, "f16c", true); 3374 setFeatureEnabledImpl(Features, "xsaveopt", true); 3375 LLVM_FALLTHROUGH; 3376 case CK_BTVER1: 3377 setFeatureEnabledImpl(Features, "ssse3", true); 3378 setFeatureEnabledImpl(Features, "sse4a", true); 3379 setFeatureEnabledImpl(Features, "lzcnt", true); 3380 setFeatureEnabledImpl(Features, "popcnt", true); 3381 setFeatureEnabledImpl(Features, "prfchw", true); 3382 setFeatureEnabledImpl(Features, "cx16", true); 3383 setFeatureEnabledImpl(Features, "fxsr", true); 3384 break; 3385 case CK_ZNVER1: 3386 setFeatureEnabledImpl(Features, "adx", true); 3387 setFeatureEnabledImpl(Features, "aes", true); 3388 setFeatureEnabledImpl(Features, "avx2", true); 3389 setFeatureEnabledImpl(Features, "bmi", true); 3390 setFeatureEnabledImpl(Features, "bmi2", true); 3391 setFeatureEnabledImpl(Features, "clflushopt", true); 3392 setFeatureEnabledImpl(Features, "clzero", true); 3393 setFeatureEnabledImpl(Features, "cx16", true); 3394 setFeatureEnabledImpl(Features, "f16c", true); 3395 setFeatureEnabledImpl(Features, "fma", true); 3396 setFeatureEnabledImpl(Features, "fsgsbase", true); 3397 setFeatureEnabledImpl(Features, "fxsr", true); 3398 setFeatureEnabledImpl(Features, "lzcnt", true); 3399 setFeatureEnabledImpl(Features, "mwaitx", true); 3400 setFeatureEnabledImpl(Features, "movbe", true); 3401 setFeatureEnabledImpl(Features, "pclmul", true); 3402 setFeatureEnabledImpl(Features, "popcnt", true); 3403 setFeatureEnabledImpl(Features, "prfchw", true); 3404 setFeatureEnabledImpl(Features, "rdrnd", true); 3405 setFeatureEnabledImpl(Features, "rdseed", true); 3406 setFeatureEnabledImpl(Features, "sha", true); 3407 setFeatureEnabledImpl(Features, "sse4a", true); 3408 setFeatureEnabledImpl(Features, "xsave", true); 3409 setFeatureEnabledImpl(Features, "xsavec", true); 3410 setFeatureEnabledImpl(Features, "xsaveopt", true); 3411 setFeatureEnabledImpl(Features, "xsaves", true); 3412 break; 3413 case CK_BDVER4: 3414 setFeatureEnabledImpl(Features, "avx2", true); 3415 setFeatureEnabledImpl(Features, "bmi2", true); 3416 setFeatureEnabledImpl(Features, "mwaitx", true); 3417 LLVM_FALLTHROUGH; 3418 case CK_BDVER3: 3419 setFeatureEnabledImpl(Features, "fsgsbase", true); 3420 setFeatureEnabledImpl(Features, "xsaveopt", true); 3421 LLVM_FALLTHROUGH; 3422 case CK_BDVER2: 3423 setFeatureEnabledImpl(Features, "bmi", true); 3424 setFeatureEnabledImpl(Features, "fma", true); 3425 setFeatureEnabledImpl(Features, "f16c", true); 3426 setFeatureEnabledImpl(Features, "tbm", true); 3427 LLVM_FALLTHROUGH; 3428 case CK_BDVER1: 3429 // xop implies avx, sse4a and fma4. 3430 setFeatureEnabledImpl(Features, "xop", true); 3431 setFeatureEnabledImpl(Features, "lwp", true); 3432 setFeatureEnabledImpl(Features, "lzcnt", true); 3433 setFeatureEnabledImpl(Features, "aes", true); 3434 setFeatureEnabledImpl(Features, "pclmul", true); 3435 setFeatureEnabledImpl(Features, "prfchw", true); 3436 setFeatureEnabledImpl(Features, "cx16", true); 3437 setFeatureEnabledImpl(Features, "fxsr", true); 3438 setFeatureEnabledImpl(Features, "xsave", true); 3439 break; 3440 } 3441 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3442 return false; 3443 3444 // Can't do this earlier because we need to be able to explicitly enable 3445 // or disable these features and the things that they depend upon. 3446 3447 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3448 auto I = Features.find("sse4.2"); 3449 if (I != Features.end() && I->getValue() && 3450 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3451 FeaturesVec.end()) 3452 Features["popcnt"] = true; 3453 3454 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3455 I = Features.find("3dnow"); 3456 if (I != Features.end() && I->getValue() && 3457 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3458 FeaturesVec.end()) 3459 Features["prfchw"] = true; 3460 3461 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3462 // then enable MMX. 3463 I = Features.find("sse"); 3464 if (I != Features.end() && I->getValue() && 3465 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3466 FeaturesVec.end()) 3467 Features["mmx"] = true; 3468 3469 return true; 3470 } 3471 3472 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3473 X86SSEEnum Level, bool Enabled) { 3474 if (Enabled) { 3475 switch (Level) { 3476 case AVX512F: 3477 Features["avx512f"] = true; 3478 LLVM_FALLTHROUGH; 3479 case AVX2: 3480 Features["avx2"] = true; 3481 LLVM_FALLTHROUGH; 3482 case AVX: 3483 Features["avx"] = true; 3484 Features["xsave"] = true; 3485 LLVM_FALLTHROUGH; 3486 case SSE42: 3487 Features["sse4.2"] = true; 3488 LLVM_FALLTHROUGH; 3489 case SSE41: 3490 Features["sse4.1"] = true; 3491 LLVM_FALLTHROUGH; 3492 case SSSE3: 3493 Features["ssse3"] = true; 3494 LLVM_FALLTHROUGH; 3495 case SSE3: 3496 Features["sse3"] = true; 3497 LLVM_FALLTHROUGH; 3498 case SSE2: 3499 Features["sse2"] = true; 3500 LLVM_FALLTHROUGH; 3501 case SSE1: 3502 Features["sse"] = true; 3503 LLVM_FALLTHROUGH; 3504 case NoSSE: 3505 break; 3506 } 3507 return; 3508 } 3509 3510 switch (Level) { 3511 case NoSSE: 3512 case SSE1: 3513 Features["sse"] = false; 3514 LLVM_FALLTHROUGH; 3515 case SSE2: 3516 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3517 Features["sha"] = false; 3518 LLVM_FALLTHROUGH; 3519 case SSE3: 3520 Features["sse3"] = false; 3521 setXOPLevel(Features, NoXOP, false); 3522 LLVM_FALLTHROUGH; 3523 case SSSE3: 3524 Features["ssse3"] = false; 3525 LLVM_FALLTHROUGH; 3526 case SSE41: 3527 Features["sse4.1"] = false; 3528 LLVM_FALLTHROUGH; 3529 case SSE42: 3530 Features["sse4.2"] = false; 3531 LLVM_FALLTHROUGH; 3532 case AVX: 3533 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3534 Features["xsaveopt"] = false; 3535 setXOPLevel(Features, FMA4, false); 3536 LLVM_FALLTHROUGH; 3537 case AVX2: 3538 Features["avx2"] = false; 3539 LLVM_FALLTHROUGH; 3540 case AVX512F: 3541 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3542 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3543 Features["avx512vl"] = Features["avx512vbmi"] = 3544 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false; 3545 } 3546 } 3547 3548 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3549 MMX3DNowEnum Level, bool Enabled) { 3550 if (Enabled) { 3551 switch (Level) { 3552 case AMD3DNowAthlon: 3553 Features["3dnowa"] = true; 3554 LLVM_FALLTHROUGH; 3555 case AMD3DNow: 3556 Features["3dnow"] = true; 3557 LLVM_FALLTHROUGH; 3558 case MMX: 3559 Features["mmx"] = true; 3560 LLVM_FALLTHROUGH; 3561 case NoMMX3DNow: 3562 break; 3563 } 3564 return; 3565 } 3566 3567 switch (Level) { 3568 case NoMMX3DNow: 3569 case MMX: 3570 Features["mmx"] = false; 3571 LLVM_FALLTHROUGH; 3572 case AMD3DNow: 3573 Features["3dnow"] = false; 3574 LLVM_FALLTHROUGH; 3575 case AMD3DNowAthlon: 3576 Features["3dnowa"] = false; 3577 } 3578 } 3579 3580 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3581 bool Enabled) { 3582 if (Enabled) { 3583 switch (Level) { 3584 case XOP: 3585 Features["xop"] = true; 3586 LLVM_FALLTHROUGH; 3587 case FMA4: 3588 Features["fma4"] = true; 3589 setSSELevel(Features, AVX, true); 3590 LLVM_FALLTHROUGH; 3591 case SSE4A: 3592 Features["sse4a"] = true; 3593 setSSELevel(Features, SSE3, true); 3594 LLVM_FALLTHROUGH; 3595 case NoXOP: 3596 break; 3597 } 3598 return; 3599 } 3600 3601 switch (Level) { 3602 case NoXOP: 3603 case SSE4A: 3604 Features["sse4a"] = false; 3605 LLVM_FALLTHROUGH; 3606 case FMA4: 3607 Features["fma4"] = false; 3608 LLVM_FALLTHROUGH; 3609 case XOP: 3610 Features["xop"] = false; 3611 } 3612 } 3613 3614 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3615 StringRef Name, bool Enabled) { 3616 // This is a bit of a hack to deal with the sse4 target feature when used 3617 // as part of the target attribute. We handle sse4 correctly everywhere 3618 // else. See below for more information on how we handle the sse4 options. 3619 if (Name != "sse4") 3620 Features[Name] = Enabled; 3621 3622 if (Name == "mmx") { 3623 setMMXLevel(Features, MMX, Enabled); 3624 } else if (Name == "sse") { 3625 setSSELevel(Features, SSE1, Enabled); 3626 } else if (Name == "sse2") { 3627 setSSELevel(Features, SSE2, Enabled); 3628 } else if (Name == "sse3") { 3629 setSSELevel(Features, SSE3, Enabled); 3630 } else if (Name == "ssse3") { 3631 setSSELevel(Features, SSSE3, Enabled); 3632 } else if (Name == "sse4.2") { 3633 setSSELevel(Features, SSE42, Enabled); 3634 } else if (Name == "sse4.1") { 3635 setSSELevel(Features, SSE41, Enabled); 3636 } else if (Name == "3dnow") { 3637 setMMXLevel(Features, AMD3DNow, Enabled); 3638 } else if (Name == "3dnowa") { 3639 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3640 } else if (Name == "aes") { 3641 if (Enabled) 3642 setSSELevel(Features, SSE2, Enabled); 3643 } else if (Name == "pclmul") { 3644 if (Enabled) 3645 setSSELevel(Features, SSE2, Enabled); 3646 } else if (Name == "avx") { 3647 setSSELevel(Features, AVX, Enabled); 3648 } else if (Name == "avx2") { 3649 setSSELevel(Features, AVX2, Enabled); 3650 } else if (Name == "avx512f") { 3651 setSSELevel(Features, AVX512F, Enabled); 3652 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3653 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3654 Name == "avx512vbmi" || Name == "avx512ifma" || 3655 Name == "avx512vpopcntdq") { 3656 if (Enabled) 3657 setSSELevel(Features, AVX512F, Enabled); 3658 // Enable BWI instruction if VBMI is being enabled. 3659 if (Name == "avx512vbmi" && Enabled) 3660 Features["avx512bw"] = true; 3661 // Also disable VBMI if BWI is being disabled. 3662 if (Name == "avx512bw" && !Enabled) 3663 Features["avx512vbmi"] = false; 3664 } else if (Name == "fma") { 3665 if (Enabled) 3666 setSSELevel(Features, AVX, Enabled); 3667 } else if (Name == "fma4") { 3668 setXOPLevel(Features, FMA4, Enabled); 3669 } else if (Name == "xop") { 3670 setXOPLevel(Features, XOP, Enabled); 3671 } else if (Name == "sse4a") { 3672 setXOPLevel(Features, SSE4A, Enabled); 3673 } else if (Name == "f16c") { 3674 if (Enabled) 3675 setSSELevel(Features, AVX, Enabled); 3676 } else if (Name == "sha") { 3677 if (Enabled) 3678 setSSELevel(Features, SSE2, Enabled); 3679 } else if (Name == "sse4") { 3680 // We can get here via the __target__ attribute since that's not controlled 3681 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3682 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3683 // disabled. 3684 if (Enabled) 3685 setSSELevel(Features, SSE42, Enabled); 3686 else 3687 setSSELevel(Features, SSE41, Enabled); 3688 } else if (Name == "xsave") { 3689 if (!Enabled) 3690 Features["xsaveopt"] = false; 3691 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3692 if (Enabled) 3693 Features["xsave"] = true; 3694 } 3695 } 3696 3697 /// handleTargetFeatures - Perform initialization based on the user 3698 /// configured set of features. 3699 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3700 DiagnosticsEngine &Diags) { 3701 for (const auto &Feature : Features) { 3702 if (Feature[0] != '+') 3703 continue; 3704 3705 if (Feature == "+aes") { 3706 HasAES = true; 3707 } else if (Feature == "+pclmul") { 3708 HasPCLMUL = true; 3709 } else if (Feature == "+lzcnt") { 3710 HasLZCNT = true; 3711 } else if (Feature == "+rdrnd") { 3712 HasRDRND = true; 3713 } else if (Feature == "+fsgsbase") { 3714 HasFSGSBASE = true; 3715 } else if (Feature == "+bmi") { 3716 HasBMI = true; 3717 } else if (Feature == "+bmi2") { 3718 HasBMI2 = true; 3719 } else if (Feature == "+popcnt") { 3720 HasPOPCNT = true; 3721 } else if (Feature == "+rtm") { 3722 HasRTM = true; 3723 } else if (Feature == "+prfchw") { 3724 HasPRFCHW = true; 3725 } else if (Feature == "+rdseed") { 3726 HasRDSEED = true; 3727 } else if (Feature == "+adx") { 3728 HasADX = true; 3729 } else if (Feature == "+tbm") { 3730 HasTBM = true; 3731 } else if (Feature == "+lwp") { 3732 HasLWP = true; 3733 } else if (Feature == "+fma") { 3734 HasFMA = true; 3735 } else if (Feature == "+f16c") { 3736 HasF16C = true; 3737 } else if (Feature == "+avx512cd") { 3738 HasAVX512CD = true; 3739 } else if (Feature == "+avx512vpopcntdq") { 3740 HasAVX512VPOPCNTDQ = true; 3741 } else if (Feature == "+avx512er") { 3742 HasAVX512ER = true; 3743 } else if (Feature == "+avx512pf") { 3744 HasAVX512PF = true; 3745 } else if (Feature == "+avx512dq") { 3746 HasAVX512DQ = true; 3747 } else if (Feature == "+avx512bw") { 3748 HasAVX512BW = true; 3749 } else if (Feature == "+avx512vl") { 3750 HasAVX512VL = true; 3751 } else if (Feature == "+avx512vbmi") { 3752 HasAVX512VBMI = true; 3753 } else if (Feature == "+avx512ifma") { 3754 HasAVX512IFMA = true; 3755 } else if (Feature == "+sha") { 3756 HasSHA = true; 3757 } else if (Feature == "+mpx") { 3758 HasMPX = true; 3759 } else if (Feature == "+movbe") { 3760 HasMOVBE = true; 3761 } else if (Feature == "+sgx") { 3762 HasSGX = true; 3763 } else if (Feature == "+cx16") { 3764 HasCX16 = true; 3765 } else if (Feature == "+fxsr") { 3766 HasFXSR = true; 3767 } else if (Feature == "+xsave") { 3768 HasXSAVE = true; 3769 } else if (Feature == "+xsaveopt") { 3770 HasXSAVEOPT = true; 3771 } else if (Feature == "+xsavec") { 3772 HasXSAVEC = true; 3773 } else if (Feature == "+xsaves") { 3774 HasXSAVES = true; 3775 } else if (Feature == "+mwaitx") { 3776 HasMWAITX = true; 3777 } else if (Feature == "+pku") { 3778 HasPKU = true; 3779 } else if (Feature == "+clflushopt") { 3780 HasCLFLUSHOPT = true; 3781 } else if (Feature == "+clwb") { 3782 HasCLWB = true; 3783 } else if (Feature == "+prefetchwt1") { 3784 HasPREFETCHWT1 = true; 3785 } else if (Feature == "+clzero") { 3786 HasCLZERO = true; 3787 } 3788 3789 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3790 .Case("+avx512f", AVX512F) 3791 .Case("+avx2", AVX2) 3792 .Case("+avx", AVX) 3793 .Case("+sse4.2", SSE42) 3794 .Case("+sse4.1", SSE41) 3795 .Case("+ssse3", SSSE3) 3796 .Case("+sse3", SSE3) 3797 .Case("+sse2", SSE2) 3798 .Case("+sse", SSE1) 3799 .Default(NoSSE); 3800 SSELevel = std::max(SSELevel, Level); 3801 3802 MMX3DNowEnum ThreeDNowLevel = 3803 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3804 .Case("+3dnowa", AMD3DNowAthlon) 3805 .Case("+3dnow", AMD3DNow) 3806 .Case("+mmx", MMX) 3807 .Default(NoMMX3DNow); 3808 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3809 3810 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3811 .Case("+xop", XOP) 3812 .Case("+fma4", FMA4) 3813 .Case("+sse4a", SSE4A) 3814 .Default(NoXOP); 3815 XOPLevel = std::max(XOPLevel, XLevel); 3816 } 3817 3818 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3819 // matches the selected sse level. 3820 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3821 (FPMath == FP_387 && SSELevel >= SSE1)) { 3822 Diags.Report(diag::err_target_unsupported_fpmath) << 3823 (FPMath == FP_SSE ? "sse" : "387"); 3824 return false; 3825 } 3826 3827 SimdDefaultAlign = 3828 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3829 return true; 3830 } 3831 3832 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3833 /// definitions for this particular subtarget. 3834 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3835 MacroBuilder &Builder) const { 3836 // Target identification. 3837 if (getTriple().getArch() == llvm::Triple::x86_64) { 3838 Builder.defineMacro("__amd64__"); 3839 Builder.defineMacro("__amd64"); 3840 Builder.defineMacro("__x86_64"); 3841 Builder.defineMacro("__x86_64__"); 3842 if (getTriple().getArchName() == "x86_64h") { 3843 Builder.defineMacro("__x86_64h"); 3844 Builder.defineMacro("__x86_64h__"); 3845 } 3846 } else { 3847 DefineStd(Builder, "i386", Opts); 3848 } 3849 3850 // Subtarget options. 3851 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3852 // truly should be based on -mtune options. 3853 switch (CPU) { 3854 case CK_Generic: 3855 break; 3856 case CK_i386: 3857 // The rest are coming from the i386 define above. 3858 Builder.defineMacro("__tune_i386__"); 3859 break; 3860 case CK_i486: 3861 case CK_WinChipC6: 3862 case CK_WinChip2: 3863 case CK_C3: 3864 defineCPUMacros(Builder, "i486"); 3865 break; 3866 case CK_PentiumMMX: 3867 Builder.defineMacro("__pentium_mmx__"); 3868 Builder.defineMacro("__tune_pentium_mmx__"); 3869 // Fallthrough 3870 case CK_i586: 3871 case CK_Pentium: 3872 defineCPUMacros(Builder, "i586"); 3873 defineCPUMacros(Builder, "pentium"); 3874 break; 3875 case CK_Pentium3: 3876 case CK_Pentium3M: 3877 case CK_PentiumM: 3878 Builder.defineMacro("__tune_pentium3__"); 3879 // Fallthrough 3880 case CK_Pentium2: 3881 case CK_C3_2: 3882 Builder.defineMacro("__tune_pentium2__"); 3883 // Fallthrough 3884 case CK_PentiumPro: 3885 Builder.defineMacro("__tune_i686__"); 3886 Builder.defineMacro("__tune_pentiumpro__"); 3887 // Fallthrough 3888 case CK_i686: 3889 Builder.defineMacro("__i686"); 3890 Builder.defineMacro("__i686__"); 3891 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3892 Builder.defineMacro("__pentiumpro"); 3893 Builder.defineMacro("__pentiumpro__"); 3894 break; 3895 case CK_Pentium4: 3896 case CK_Pentium4M: 3897 defineCPUMacros(Builder, "pentium4"); 3898 break; 3899 case CK_Yonah: 3900 case CK_Prescott: 3901 case CK_Nocona: 3902 defineCPUMacros(Builder, "nocona"); 3903 break; 3904 case CK_Core2: 3905 case CK_Penryn: 3906 defineCPUMacros(Builder, "core2"); 3907 break; 3908 case CK_Bonnell: 3909 defineCPUMacros(Builder, "atom"); 3910 break; 3911 case CK_Silvermont: 3912 defineCPUMacros(Builder, "slm"); 3913 break; 3914 case CK_Goldmont: 3915 defineCPUMacros(Builder, "goldmont"); 3916 break; 3917 case CK_Nehalem: 3918 case CK_Westmere: 3919 case CK_SandyBridge: 3920 case CK_IvyBridge: 3921 case CK_Haswell: 3922 case CK_Broadwell: 3923 case CK_SkylakeClient: 3924 // FIXME: Historically, we defined this legacy name, it would be nice to 3925 // remove it at some point. We've never exposed fine-grained names for 3926 // recent primary x86 CPUs, and we should keep it that way. 3927 defineCPUMacros(Builder, "corei7"); 3928 break; 3929 case CK_SkylakeServer: 3930 defineCPUMacros(Builder, "skx"); 3931 break; 3932 case CK_Cannonlake: 3933 break; 3934 case CK_KNL: 3935 defineCPUMacros(Builder, "knl"); 3936 break; 3937 case CK_Lakemont: 3938 Builder.defineMacro("__tune_lakemont__"); 3939 break; 3940 case CK_K6_2: 3941 Builder.defineMacro("__k6_2__"); 3942 Builder.defineMacro("__tune_k6_2__"); 3943 // Fallthrough 3944 case CK_K6_3: 3945 if (CPU != CK_K6_2) { // In case of fallthrough 3946 // FIXME: GCC may be enabling these in cases where some other k6 3947 // architecture is specified but -m3dnow is explicitly provided. The 3948 // exact semantics need to be determined and emulated here. 3949 Builder.defineMacro("__k6_3__"); 3950 Builder.defineMacro("__tune_k6_3__"); 3951 } 3952 // Fallthrough 3953 case CK_K6: 3954 defineCPUMacros(Builder, "k6"); 3955 break; 3956 case CK_Athlon: 3957 case CK_AthlonThunderbird: 3958 case CK_Athlon4: 3959 case CK_AthlonXP: 3960 case CK_AthlonMP: 3961 defineCPUMacros(Builder, "athlon"); 3962 if (SSELevel != NoSSE) { 3963 Builder.defineMacro("__athlon_sse__"); 3964 Builder.defineMacro("__tune_athlon_sse__"); 3965 } 3966 break; 3967 case CK_K8: 3968 case CK_K8SSE3: 3969 case CK_x86_64: 3970 case CK_Opteron: 3971 case CK_OpteronSSE3: 3972 case CK_Athlon64: 3973 case CK_Athlon64SSE3: 3974 case CK_AthlonFX: 3975 defineCPUMacros(Builder, "k8"); 3976 break; 3977 case CK_AMDFAM10: 3978 defineCPUMacros(Builder, "amdfam10"); 3979 break; 3980 case CK_BTVER1: 3981 defineCPUMacros(Builder, "btver1"); 3982 break; 3983 case CK_BTVER2: 3984 defineCPUMacros(Builder, "btver2"); 3985 break; 3986 case CK_BDVER1: 3987 defineCPUMacros(Builder, "bdver1"); 3988 break; 3989 case CK_BDVER2: 3990 defineCPUMacros(Builder, "bdver2"); 3991 break; 3992 case CK_BDVER3: 3993 defineCPUMacros(Builder, "bdver3"); 3994 break; 3995 case CK_BDVER4: 3996 defineCPUMacros(Builder, "bdver4"); 3997 break; 3998 case CK_ZNVER1: 3999 defineCPUMacros(Builder, "znver1"); 4000 break; 4001 case CK_Geode: 4002 defineCPUMacros(Builder, "geode"); 4003 break; 4004 } 4005 4006 // Target properties. 4007 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4008 4009 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 4010 // functions in glibc header files that use FP Stack inline asm which the 4011 // backend can't deal with (PR879). 4012 Builder.defineMacro("__NO_MATH_INLINES"); 4013 4014 if (HasAES) 4015 Builder.defineMacro("__AES__"); 4016 4017 if (HasPCLMUL) 4018 Builder.defineMacro("__PCLMUL__"); 4019 4020 if (HasLZCNT) 4021 Builder.defineMacro("__LZCNT__"); 4022 4023 if (HasRDRND) 4024 Builder.defineMacro("__RDRND__"); 4025 4026 if (HasFSGSBASE) 4027 Builder.defineMacro("__FSGSBASE__"); 4028 4029 if (HasBMI) 4030 Builder.defineMacro("__BMI__"); 4031 4032 if (HasBMI2) 4033 Builder.defineMacro("__BMI2__"); 4034 4035 if (HasPOPCNT) 4036 Builder.defineMacro("__POPCNT__"); 4037 4038 if (HasRTM) 4039 Builder.defineMacro("__RTM__"); 4040 4041 if (HasPRFCHW) 4042 Builder.defineMacro("__PRFCHW__"); 4043 4044 if (HasRDSEED) 4045 Builder.defineMacro("__RDSEED__"); 4046 4047 if (HasADX) 4048 Builder.defineMacro("__ADX__"); 4049 4050 if (HasTBM) 4051 Builder.defineMacro("__TBM__"); 4052 4053 if (HasLWP) 4054 Builder.defineMacro("__LWP__"); 4055 4056 if (HasMWAITX) 4057 Builder.defineMacro("__MWAITX__"); 4058 4059 switch (XOPLevel) { 4060 case XOP: 4061 Builder.defineMacro("__XOP__"); 4062 LLVM_FALLTHROUGH; 4063 case FMA4: 4064 Builder.defineMacro("__FMA4__"); 4065 LLVM_FALLTHROUGH; 4066 case SSE4A: 4067 Builder.defineMacro("__SSE4A__"); 4068 LLVM_FALLTHROUGH; 4069 case NoXOP: 4070 break; 4071 } 4072 4073 if (HasFMA) 4074 Builder.defineMacro("__FMA__"); 4075 4076 if (HasF16C) 4077 Builder.defineMacro("__F16C__"); 4078 4079 if (HasAVX512CD) 4080 Builder.defineMacro("__AVX512CD__"); 4081 if (HasAVX512VPOPCNTDQ) 4082 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 4083 if (HasAVX512ER) 4084 Builder.defineMacro("__AVX512ER__"); 4085 if (HasAVX512PF) 4086 Builder.defineMacro("__AVX512PF__"); 4087 if (HasAVX512DQ) 4088 Builder.defineMacro("__AVX512DQ__"); 4089 if (HasAVX512BW) 4090 Builder.defineMacro("__AVX512BW__"); 4091 if (HasAVX512VL) 4092 Builder.defineMacro("__AVX512VL__"); 4093 if (HasAVX512VBMI) 4094 Builder.defineMacro("__AVX512VBMI__"); 4095 if (HasAVX512IFMA) 4096 Builder.defineMacro("__AVX512IFMA__"); 4097 4098 if (HasSHA) 4099 Builder.defineMacro("__SHA__"); 4100 4101 if (HasFXSR) 4102 Builder.defineMacro("__FXSR__"); 4103 if (HasXSAVE) 4104 Builder.defineMacro("__XSAVE__"); 4105 if (HasXSAVEOPT) 4106 Builder.defineMacro("__XSAVEOPT__"); 4107 if (HasXSAVEC) 4108 Builder.defineMacro("__XSAVEC__"); 4109 if (HasXSAVES) 4110 Builder.defineMacro("__XSAVES__"); 4111 if (HasPKU) 4112 Builder.defineMacro("__PKU__"); 4113 if (HasCX16) 4114 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 4115 if (HasCLFLUSHOPT) 4116 Builder.defineMacro("__CLFLUSHOPT__"); 4117 if (HasCLWB) 4118 Builder.defineMacro("__CLWB__"); 4119 if (HasMPX) 4120 Builder.defineMacro("__MPX__"); 4121 if (HasSGX) 4122 Builder.defineMacro("__SGX__"); 4123 if (HasPREFETCHWT1) 4124 Builder.defineMacro("__PREFETCHWT1__"); 4125 if (HasCLZERO) 4126 Builder.defineMacro("__CLZERO__"); 4127 4128 // Each case falls through to the previous one here. 4129 switch (SSELevel) { 4130 case AVX512F: 4131 Builder.defineMacro("__AVX512F__"); 4132 LLVM_FALLTHROUGH; 4133 case AVX2: 4134 Builder.defineMacro("__AVX2__"); 4135 LLVM_FALLTHROUGH; 4136 case AVX: 4137 Builder.defineMacro("__AVX__"); 4138 LLVM_FALLTHROUGH; 4139 case SSE42: 4140 Builder.defineMacro("__SSE4_2__"); 4141 LLVM_FALLTHROUGH; 4142 case SSE41: 4143 Builder.defineMacro("__SSE4_1__"); 4144 LLVM_FALLTHROUGH; 4145 case SSSE3: 4146 Builder.defineMacro("__SSSE3__"); 4147 LLVM_FALLTHROUGH; 4148 case SSE3: 4149 Builder.defineMacro("__SSE3__"); 4150 LLVM_FALLTHROUGH; 4151 case SSE2: 4152 Builder.defineMacro("__SSE2__"); 4153 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 4154 LLVM_FALLTHROUGH; 4155 case SSE1: 4156 Builder.defineMacro("__SSE__"); 4157 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 4158 LLVM_FALLTHROUGH; 4159 case NoSSE: 4160 break; 4161 } 4162 4163 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 4164 switch (SSELevel) { 4165 case AVX512F: 4166 case AVX2: 4167 case AVX: 4168 case SSE42: 4169 case SSE41: 4170 case SSSE3: 4171 case SSE3: 4172 case SSE2: 4173 Builder.defineMacro("_M_IX86_FP", Twine(2)); 4174 break; 4175 case SSE1: 4176 Builder.defineMacro("_M_IX86_FP", Twine(1)); 4177 break; 4178 default: 4179 Builder.defineMacro("_M_IX86_FP", Twine(0)); 4180 } 4181 } 4182 4183 // Each case falls through to the previous one here. 4184 switch (MMX3DNowLevel) { 4185 case AMD3DNowAthlon: 4186 Builder.defineMacro("__3dNOW_A__"); 4187 LLVM_FALLTHROUGH; 4188 case AMD3DNow: 4189 Builder.defineMacro("__3dNOW__"); 4190 LLVM_FALLTHROUGH; 4191 case MMX: 4192 Builder.defineMacro("__MMX__"); 4193 LLVM_FALLTHROUGH; 4194 case NoMMX3DNow: 4195 break; 4196 } 4197 4198 if (CPU >= CK_i486) { 4199 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4200 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4201 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4202 } 4203 if (CPU >= CK_i586) 4204 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4205 4206 if (HasFloat128) 4207 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 4208 } 4209 4210 bool X86TargetInfo::hasFeature(StringRef Feature) const { 4211 return llvm::StringSwitch<bool>(Feature) 4212 .Case("aes", HasAES) 4213 .Case("avx", SSELevel >= AVX) 4214 .Case("avx2", SSELevel >= AVX2) 4215 .Case("avx512f", SSELevel >= AVX512F) 4216 .Case("avx512cd", HasAVX512CD) 4217 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 4218 .Case("avx512er", HasAVX512ER) 4219 .Case("avx512pf", HasAVX512PF) 4220 .Case("avx512dq", HasAVX512DQ) 4221 .Case("avx512bw", HasAVX512BW) 4222 .Case("avx512vl", HasAVX512VL) 4223 .Case("avx512vbmi", HasAVX512VBMI) 4224 .Case("avx512ifma", HasAVX512IFMA) 4225 .Case("bmi", HasBMI) 4226 .Case("bmi2", HasBMI2) 4227 .Case("clflushopt", HasCLFLUSHOPT) 4228 .Case("clwb", HasCLWB) 4229 .Case("clzero", HasCLZERO) 4230 .Case("cx16", HasCX16) 4231 .Case("f16c", HasF16C) 4232 .Case("fma", HasFMA) 4233 .Case("fma4", XOPLevel >= FMA4) 4234 .Case("fsgsbase", HasFSGSBASE) 4235 .Case("fxsr", HasFXSR) 4236 .Case("lzcnt", HasLZCNT) 4237 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 4238 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 4239 .Case("mmx", MMX3DNowLevel >= MMX) 4240 .Case("movbe", HasMOVBE) 4241 .Case("mpx", HasMPX) 4242 .Case("pclmul", HasPCLMUL) 4243 .Case("pku", HasPKU) 4244 .Case("popcnt", HasPOPCNT) 4245 .Case("prefetchwt1", HasPREFETCHWT1) 4246 .Case("prfchw", HasPRFCHW) 4247 .Case("rdrnd", HasRDRND) 4248 .Case("rdseed", HasRDSEED) 4249 .Case("rtm", HasRTM) 4250 .Case("sgx", HasSGX) 4251 .Case("sha", HasSHA) 4252 .Case("sse", SSELevel >= SSE1) 4253 .Case("sse2", SSELevel >= SSE2) 4254 .Case("sse3", SSELevel >= SSE3) 4255 .Case("ssse3", SSELevel >= SSSE3) 4256 .Case("sse4.1", SSELevel >= SSE41) 4257 .Case("sse4.2", SSELevel >= SSE42) 4258 .Case("sse4a", XOPLevel >= SSE4A) 4259 .Case("tbm", HasTBM) 4260 .Case("lwp", HasLWP) 4261 .Case("x86", true) 4262 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 4263 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 4264 .Case("xop", XOPLevel >= XOP) 4265 .Case("xsave", HasXSAVE) 4266 .Case("xsavec", HasXSAVEC) 4267 .Case("xsaves", HasXSAVES) 4268 .Case("xsaveopt", HasXSAVEOPT) 4269 .Default(false); 4270 } 4271 4272 // We can't use a generic validation scheme for the features accepted here 4273 // versus subtarget features accepted in the target attribute because the 4274 // bitfield structure that's initialized in the runtime only supports the 4275 // below currently rather than the full range of subtarget features. (See 4276 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 4277 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 4278 return llvm::StringSwitch<bool>(FeatureStr) 4279 .Case("cmov", true) 4280 .Case("mmx", true) 4281 .Case("popcnt", true) 4282 .Case("sse", true) 4283 .Case("sse2", true) 4284 .Case("sse3", true) 4285 .Case("ssse3", true) 4286 .Case("sse4.1", true) 4287 .Case("sse4.2", true) 4288 .Case("avx", true) 4289 .Case("avx2", true) 4290 .Case("sse4a", true) 4291 .Case("fma4", true) 4292 .Case("xop", true) 4293 .Case("fma", true) 4294 .Case("avx512f", true) 4295 .Case("bmi", true) 4296 .Case("bmi2", true) 4297 .Case("aes", true) 4298 .Case("pclmul", true) 4299 .Case("avx512vl", true) 4300 .Case("avx512bw", true) 4301 .Case("avx512dq", true) 4302 .Case("avx512cd", true) 4303 .Case("avx512vpopcntdq", true) 4304 .Case("avx512er", true) 4305 .Case("avx512pf", true) 4306 .Case("avx512vbmi", true) 4307 .Case("avx512ifma", true) 4308 .Default(false); 4309 } 4310 4311 bool 4312 X86TargetInfo::validateAsmConstraint(const char *&Name, 4313 TargetInfo::ConstraintInfo &Info) const { 4314 switch (*Name) { 4315 default: return false; 4316 // Constant constraints. 4317 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 4318 // instructions. 4319 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 4320 // x86_64 instructions. 4321 case 's': 4322 Info.setRequiresImmediate(); 4323 return true; 4324 case 'I': 4325 Info.setRequiresImmediate(0, 31); 4326 return true; 4327 case 'J': 4328 Info.setRequiresImmediate(0, 63); 4329 return true; 4330 case 'K': 4331 Info.setRequiresImmediate(-128, 127); 4332 return true; 4333 case 'L': 4334 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 4335 return true; 4336 case 'M': 4337 Info.setRequiresImmediate(0, 3); 4338 return true; 4339 case 'N': 4340 Info.setRequiresImmediate(0, 255); 4341 return true; 4342 case 'O': 4343 Info.setRequiresImmediate(0, 127); 4344 return true; 4345 // Register constraints. 4346 case 'Y': // 'Y' is the first character for several 2-character constraints. 4347 // Shift the pointer to the second character of the constraint. 4348 Name++; 4349 switch (*Name) { 4350 default: 4351 return false; 4352 case '0': // First SSE register. 4353 case 't': // Any SSE register, when SSE2 is enabled. 4354 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 4355 case 'm': // Any MMX register, when inter-unit moves enabled. 4356 case 'k': // AVX512 arch mask registers: k1-k7. 4357 Info.setAllowsRegister(); 4358 return true; 4359 } 4360 case 'f': // Any x87 floating point stack register. 4361 // Constraint 'f' cannot be used for output operands. 4362 if (Info.ConstraintStr[0] == '=') 4363 return false; 4364 Info.setAllowsRegister(); 4365 return true; 4366 case 'a': // eax. 4367 case 'b': // ebx. 4368 case 'c': // ecx. 4369 case 'd': // edx. 4370 case 'S': // esi. 4371 case 'D': // edi. 4372 case 'A': // edx:eax. 4373 case 't': // Top of floating point stack. 4374 case 'u': // Second from top of floating point stack. 4375 case 'q': // Any register accessible as [r]l: a, b, c, and d. 4376 case 'y': // Any MMX register. 4377 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 4378 case 'x': // Any SSE register. 4379 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 4380 // for intermideate k reg operations). 4381 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 4382 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 4383 case 'l': // "Index" registers: any general register that can be used as an 4384 // index in a base+index memory access. 4385 Info.setAllowsRegister(); 4386 return true; 4387 // Floating point constant constraints. 4388 case 'C': // SSE floating point constant. 4389 case 'G': // x87 floating point constant. 4390 return true; 4391 } 4392 } 4393 4394 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 4395 unsigned Size) const { 4396 // Strip off constraint modifiers. 4397 while (Constraint[0] == '=' || 4398 Constraint[0] == '+' || 4399 Constraint[0] == '&') 4400 Constraint = Constraint.substr(1); 4401 4402 return validateOperandSize(Constraint, Size); 4403 } 4404 4405 bool X86TargetInfo::validateInputSize(StringRef Constraint, 4406 unsigned Size) const { 4407 return validateOperandSize(Constraint, Size); 4408 } 4409 4410 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 4411 unsigned Size) const { 4412 switch (Constraint[0]) { 4413 default: break; 4414 case 'k': 4415 // Registers k0-k7 (AVX512) size limit is 64 bit. 4416 case 'y': 4417 return Size <= 64; 4418 case 'f': 4419 case 't': 4420 case 'u': 4421 return Size <= 128; 4422 case 'v': 4423 case 'x': 4424 if (SSELevel >= AVX512F) 4425 // 512-bit zmm registers can be used if target supports AVX512F. 4426 return Size <= 512U; 4427 else if (SSELevel >= AVX) 4428 // 256-bit ymm registers can be used if target supports AVX. 4429 return Size <= 256U; 4430 return Size <= 128U; 4431 case 'Y': 4432 // 'Y' is the first character for several 2-character constraints. 4433 switch (Constraint[1]) { 4434 default: break; 4435 case 'm': 4436 // 'Ym' is synonymous with 'y'. 4437 case 'k': 4438 return Size <= 64; 4439 case 'i': 4440 case 't': 4441 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4442 if (SSELevel >= AVX512F) 4443 return Size <= 512U; 4444 else if (SSELevel >= AVX) 4445 return Size <= 256U; 4446 return SSELevel >= SSE2 && Size <= 128U; 4447 } 4448 4449 } 4450 4451 return true; 4452 } 4453 4454 std::string 4455 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4456 switch (*Constraint) { 4457 case 'a': return std::string("{ax}"); 4458 case 'b': return std::string("{bx}"); 4459 case 'c': return std::string("{cx}"); 4460 case 'd': return std::string("{dx}"); 4461 case 'S': return std::string("{si}"); 4462 case 'D': return std::string("{di}"); 4463 case 'p': // address 4464 return std::string("im"); 4465 case 't': // top of floating point stack. 4466 return std::string("{st}"); 4467 case 'u': // second from top of floating point stack. 4468 return std::string("{st(1)}"); // second from top of floating point stack. 4469 case 'Y': 4470 switch (Constraint[1]) { 4471 default: 4472 // Break from inner switch and fall through (copy single char), 4473 // continue parsing after copying the current constraint into 4474 // the return string. 4475 break; 4476 case 'k': 4477 // "^" hints llvm that this is a 2 letter constraint. 4478 // "Constraint++" is used to promote the string iterator 4479 // to the next constraint. 4480 return std::string("^") + std::string(Constraint++, 2); 4481 } 4482 LLVM_FALLTHROUGH; 4483 default: 4484 return std::string(1, *Constraint); 4485 } 4486 } 4487 4488 // X86-32 generic target 4489 class X86_32TargetInfo : public X86TargetInfo { 4490 public: 4491 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4492 : X86TargetInfo(Triple, Opts) { 4493 DoubleAlign = LongLongAlign = 32; 4494 LongDoubleWidth = 96; 4495 LongDoubleAlign = 32; 4496 SuitableAlign = 128; 4497 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4498 SizeType = UnsignedInt; 4499 PtrDiffType = SignedInt; 4500 IntPtrType = SignedInt; 4501 RegParmMax = 3; 4502 4503 // Use fpret for all types. 4504 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4505 (1 << TargetInfo::Double) | 4506 (1 << TargetInfo::LongDouble)); 4507 4508 // x86-32 has atomics up to 8 bytes 4509 // FIXME: Check that we actually have cmpxchg8b before setting 4510 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4511 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4512 } 4513 BuiltinVaListKind getBuiltinVaListKind() const override { 4514 return TargetInfo::CharPtrBuiltinVaList; 4515 } 4516 4517 int getEHDataRegisterNumber(unsigned RegNo) const override { 4518 if (RegNo == 0) return 0; 4519 if (RegNo == 1) return 2; 4520 return -1; 4521 } 4522 bool validateOperandSize(StringRef Constraint, 4523 unsigned Size) const override { 4524 switch (Constraint[0]) { 4525 default: break; 4526 case 'R': 4527 case 'q': 4528 case 'Q': 4529 case 'a': 4530 case 'b': 4531 case 'c': 4532 case 'd': 4533 case 'S': 4534 case 'D': 4535 return Size <= 32; 4536 case 'A': 4537 return Size <= 64; 4538 } 4539 4540 return X86TargetInfo::validateOperandSize(Constraint, Size); 4541 } 4542 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4543 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 4544 Builtin::FirstTSBuiltin + 1); 4545 } 4546 }; 4547 4548 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4549 public: 4550 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4551 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4552 4553 unsigned getFloatEvalMethod() const override { 4554 unsigned Major, Minor, Micro; 4555 getTriple().getOSVersion(Major, Minor, Micro); 4556 // New NetBSD uses the default rounding mode. 4557 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4558 return X86_32TargetInfo::getFloatEvalMethod(); 4559 // NetBSD before 6.99.26 defaults to "double" rounding. 4560 return 1; 4561 } 4562 }; 4563 4564 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4565 public: 4566 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4567 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4568 SizeType = UnsignedLong; 4569 IntPtrType = SignedLong; 4570 PtrDiffType = SignedLong; 4571 } 4572 }; 4573 4574 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4575 public: 4576 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4577 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4578 SizeType = UnsignedLong; 4579 IntPtrType = SignedLong; 4580 PtrDiffType = SignedLong; 4581 } 4582 }; 4583 4584 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4585 public: 4586 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4587 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4588 LongDoubleWidth = 128; 4589 LongDoubleAlign = 128; 4590 SuitableAlign = 128; 4591 MaxVectorAlign = 256; 4592 // The watchOS simulator uses the builtin bool type for Objective-C. 4593 llvm::Triple T = llvm::Triple(Triple); 4594 if (T.isWatchOS()) 4595 UseSignedCharForObjCBool = false; 4596 SizeType = UnsignedLong; 4597 IntPtrType = SignedLong; 4598 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4599 HasAlignMac68kSupport = true; 4600 } 4601 4602 bool handleTargetFeatures(std::vector<std::string> &Features, 4603 DiagnosticsEngine &Diags) override { 4604 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4605 Diags)) 4606 return false; 4607 // We now know the features we have: we can decide how to align vectors. 4608 MaxVectorAlign = 4609 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4610 return true; 4611 } 4612 }; 4613 4614 // x86-32 Windows target 4615 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4616 public: 4617 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4618 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4619 WCharType = UnsignedShort; 4620 DoubleAlign = LongLongAlign = 64; 4621 bool IsWinCOFF = 4622 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4623 resetDataLayout(IsWinCOFF 4624 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4625 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4626 } 4627 void getTargetDefines(const LangOptions &Opts, 4628 MacroBuilder &Builder) const override { 4629 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4630 } 4631 }; 4632 4633 // x86-32 Windows Visual Studio target 4634 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4635 public: 4636 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4637 const TargetOptions &Opts) 4638 : WindowsX86_32TargetInfo(Triple, Opts) { 4639 LongDoubleWidth = LongDoubleAlign = 64; 4640 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4641 } 4642 void getTargetDefines(const LangOptions &Opts, 4643 MacroBuilder &Builder) const override { 4644 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4645 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4646 // The value of the following reflects processor type. 4647 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4648 // We lost the original triple, so we use the default. 4649 Builder.defineMacro("_M_IX86", "600"); 4650 } 4651 }; 4652 4653 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4654 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4655 // supports __declspec natively under -fms-extensions, but we define a no-op 4656 // __declspec macro anyway for pre-processor compatibility. 4657 if (Opts.MicrosoftExt) 4658 Builder.defineMacro("__declspec", "__declspec"); 4659 else 4660 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4661 4662 if (!Opts.MicrosoftExt) { 4663 // Provide macros for all the calling convention keywords. Provide both 4664 // single and double underscore prefixed variants. These are available on 4665 // x64 as well as x86, even though they have no effect. 4666 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4667 for (const char *CC : CCs) { 4668 std::string GCCSpelling = "__attribute__((__"; 4669 GCCSpelling += CC; 4670 GCCSpelling += "__))"; 4671 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4672 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4673 } 4674 } 4675 } 4676 4677 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4678 Builder.defineMacro("__MSVCRT__"); 4679 Builder.defineMacro("__MINGW32__"); 4680 addCygMingDefines(Opts, Builder); 4681 } 4682 4683 // x86-32 MinGW target 4684 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4685 public: 4686 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4687 : WindowsX86_32TargetInfo(Triple, Opts) { 4688 HasFloat128 = true; 4689 } 4690 void getTargetDefines(const LangOptions &Opts, 4691 MacroBuilder &Builder) const override { 4692 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4693 DefineStd(Builder, "WIN32", Opts); 4694 DefineStd(Builder, "WINNT", Opts); 4695 Builder.defineMacro("_X86_"); 4696 addMinGWDefines(Opts, Builder); 4697 } 4698 }; 4699 4700 // x86-32 Cygwin target 4701 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4702 public: 4703 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4704 : X86_32TargetInfo(Triple, Opts) { 4705 WCharType = UnsignedShort; 4706 DoubleAlign = LongLongAlign = 64; 4707 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4708 } 4709 void getTargetDefines(const LangOptions &Opts, 4710 MacroBuilder &Builder) const override { 4711 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4712 Builder.defineMacro("_X86_"); 4713 Builder.defineMacro("__CYGWIN__"); 4714 Builder.defineMacro("__CYGWIN32__"); 4715 addCygMingDefines(Opts, Builder); 4716 DefineStd(Builder, "unix", Opts); 4717 if (Opts.CPlusPlus) 4718 Builder.defineMacro("_GNU_SOURCE"); 4719 } 4720 }; 4721 4722 // x86-32 Haiku target 4723 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4724 public: 4725 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4726 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4727 } 4728 void getTargetDefines(const LangOptions &Opts, 4729 MacroBuilder &Builder) const override { 4730 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4731 Builder.defineMacro("__INTEL__"); 4732 } 4733 }; 4734 4735 // X86-32 MCU target 4736 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4737 public: 4738 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4739 : X86_32TargetInfo(Triple, Opts) { 4740 LongDoubleWidth = 64; 4741 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4742 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4743 WIntType = UnsignedInt; 4744 } 4745 4746 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4747 // On MCU we support only C calling convention. 4748 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4749 } 4750 4751 void getTargetDefines(const LangOptions &Opts, 4752 MacroBuilder &Builder) const override { 4753 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4754 Builder.defineMacro("__iamcu"); 4755 Builder.defineMacro("__iamcu__"); 4756 } 4757 4758 bool allowsLargerPreferedTypeAlignment() const override { 4759 return false; 4760 } 4761 }; 4762 4763 // RTEMS Target 4764 template<typename Target> 4765 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4766 protected: 4767 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4768 MacroBuilder &Builder) const override { 4769 // RTEMS defines; list based off of gcc output 4770 4771 Builder.defineMacro("__rtems__"); 4772 Builder.defineMacro("__ELF__"); 4773 } 4774 4775 public: 4776 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4777 : OSTargetInfo<Target>(Triple, Opts) { 4778 switch (Triple.getArch()) { 4779 default: 4780 case llvm::Triple::x86: 4781 // this->MCountName = ".mcount"; 4782 break; 4783 case llvm::Triple::mips: 4784 case llvm::Triple::mipsel: 4785 case llvm::Triple::ppc: 4786 case llvm::Triple::ppc64: 4787 case llvm::Triple::ppc64le: 4788 // this->MCountName = "_mcount"; 4789 break; 4790 case llvm::Triple::arm: 4791 // this->MCountName = "__mcount"; 4792 break; 4793 } 4794 } 4795 }; 4796 4797 // x86-32 RTEMS target 4798 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4799 public: 4800 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4801 : X86_32TargetInfo(Triple, Opts) { 4802 SizeType = UnsignedLong; 4803 IntPtrType = SignedLong; 4804 PtrDiffType = SignedLong; 4805 } 4806 void getTargetDefines(const LangOptions &Opts, 4807 MacroBuilder &Builder) const override { 4808 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4809 Builder.defineMacro("__INTEL__"); 4810 Builder.defineMacro("__rtems__"); 4811 } 4812 }; 4813 4814 // x86-64 generic target 4815 class X86_64TargetInfo : public X86TargetInfo { 4816 public: 4817 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4818 : X86TargetInfo(Triple, Opts) { 4819 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4820 bool IsWinCOFF = 4821 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4822 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4823 LongDoubleWidth = 128; 4824 LongDoubleAlign = 128; 4825 LargeArrayMinWidth = 128; 4826 LargeArrayAlign = 128; 4827 SuitableAlign = 128; 4828 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4829 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4830 IntPtrType = IsX32 ? SignedInt : SignedLong; 4831 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4832 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4833 RegParmMax = 6; 4834 4835 // Pointers are 32-bit in x32. 4836 resetDataLayout(IsX32 4837 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4838 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4839 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4840 4841 // Use fpret only for long double. 4842 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4843 4844 // Use fp2ret for _Complex long double. 4845 ComplexLongDoubleUsesFP2Ret = true; 4846 4847 // Make __builtin_ms_va_list available. 4848 HasBuiltinMSVaList = true; 4849 4850 // x86-64 has atomics up to 16 bytes. 4851 MaxAtomicPromoteWidth = 128; 4852 MaxAtomicInlineWidth = 128; 4853 } 4854 BuiltinVaListKind getBuiltinVaListKind() const override { 4855 return TargetInfo::X86_64ABIBuiltinVaList; 4856 } 4857 4858 int getEHDataRegisterNumber(unsigned RegNo) const override { 4859 if (RegNo == 0) return 0; 4860 if (RegNo == 1) return 1; 4861 return -1; 4862 } 4863 4864 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4865 switch (CC) { 4866 case CC_C: 4867 case CC_Swift: 4868 case CC_X86VectorCall: 4869 case CC_IntelOclBicc: 4870 case CC_X86_64Win64: 4871 case CC_PreserveMost: 4872 case CC_PreserveAll: 4873 case CC_X86RegCall: 4874 case CC_OpenCLKernel: 4875 return CCCR_OK; 4876 default: 4877 return CCCR_Warning; 4878 } 4879 } 4880 4881 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4882 return CC_C; 4883 } 4884 4885 // for x32 we need it here explicitly 4886 bool hasInt128Type() const override { return true; } 4887 unsigned getUnwindWordWidth() const override { return 64; } 4888 unsigned getRegisterWidth() const override { return 64; } 4889 4890 bool validateGlobalRegisterVariable(StringRef RegName, 4891 unsigned RegSize, 4892 bool &HasSizeMismatch) const override { 4893 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4894 // handle. 4895 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4896 // Check that the register size is 64-bit. 4897 HasSizeMismatch = RegSize != 64; 4898 return true; 4899 } 4900 4901 // Check if the register is a 32-bit register the backend can handle. 4902 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4903 HasSizeMismatch); 4904 } 4905 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4906 return llvm::makeArrayRef(BuiltinInfoX86, 4907 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 4908 } 4909 }; 4910 4911 // x86-64 Windows target 4912 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4913 public: 4914 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4915 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4916 WCharType = UnsignedShort; 4917 LongWidth = LongAlign = 32; 4918 DoubleAlign = LongLongAlign = 64; 4919 IntMaxType = SignedLongLong; 4920 Int64Type = SignedLongLong; 4921 SizeType = UnsignedLongLong; 4922 PtrDiffType = SignedLongLong; 4923 IntPtrType = SignedLongLong; 4924 } 4925 4926 void getTargetDefines(const LangOptions &Opts, 4927 MacroBuilder &Builder) const override { 4928 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4929 Builder.defineMacro("_WIN64"); 4930 } 4931 4932 BuiltinVaListKind getBuiltinVaListKind() const override { 4933 return TargetInfo::CharPtrBuiltinVaList; 4934 } 4935 4936 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4937 switch (CC) { 4938 case CC_X86StdCall: 4939 case CC_X86ThisCall: 4940 case CC_X86FastCall: 4941 return CCCR_Ignore; 4942 case CC_C: 4943 case CC_X86VectorCall: 4944 case CC_IntelOclBicc: 4945 case CC_X86_64SysV: 4946 case CC_Swift: 4947 case CC_X86RegCall: 4948 case CC_OpenCLKernel: 4949 return CCCR_OK; 4950 default: 4951 return CCCR_Warning; 4952 } 4953 } 4954 }; 4955 4956 // x86-64 Windows Visual Studio target 4957 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4958 public: 4959 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4960 const TargetOptions &Opts) 4961 : WindowsX86_64TargetInfo(Triple, Opts) { 4962 LongDoubleWidth = LongDoubleAlign = 64; 4963 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4964 } 4965 void getTargetDefines(const LangOptions &Opts, 4966 MacroBuilder &Builder) const override { 4967 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4968 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4969 Builder.defineMacro("_M_X64", "100"); 4970 Builder.defineMacro("_M_AMD64", "100"); 4971 } 4972 }; 4973 4974 // x86-64 MinGW target 4975 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4976 public: 4977 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4978 : WindowsX86_64TargetInfo(Triple, Opts) { 4979 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4980 // with x86 FP ops. Weird. 4981 LongDoubleWidth = LongDoubleAlign = 128; 4982 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 4983 HasFloat128 = true; 4984 } 4985 4986 void getTargetDefines(const LangOptions &Opts, 4987 MacroBuilder &Builder) const override { 4988 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4989 DefineStd(Builder, "WIN64", Opts); 4990 Builder.defineMacro("__MINGW64__"); 4991 addMinGWDefines(Opts, Builder); 4992 4993 // GCC defines this macro when it is using __gxx_personality_seh0. 4994 if (!Opts.SjLjExceptions) 4995 Builder.defineMacro("__SEH__"); 4996 } 4997 }; 4998 4999 // x86-64 Cygwin target 5000 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 5001 public: 5002 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5003 : X86_64TargetInfo(Triple, Opts) { 5004 TLSSupported = false; 5005 WCharType = UnsignedShort; 5006 } 5007 void getTargetDefines(const LangOptions &Opts, 5008 MacroBuilder &Builder) const override { 5009 X86_64TargetInfo::getTargetDefines(Opts, Builder); 5010 Builder.defineMacro("__x86_64__"); 5011 Builder.defineMacro("__CYGWIN__"); 5012 Builder.defineMacro("__CYGWIN64__"); 5013 addCygMingDefines(Opts, Builder); 5014 DefineStd(Builder, "unix", Opts); 5015 if (Opts.CPlusPlus) 5016 Builder.defineMacro("_GNU_SOURCE"); 5017 5018 // GCC defines this macro when it is using __gxx_personality_seh0. 5019 if (!Opts.SjLjExceptions) 5020 Builder.defineMacro("__SEH__"); 5021 } 5022 }; 5023 5024 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 5025 public: 5026 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5027 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5028 Int64Type = SignedLongLong; 5029 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 5030 llvm::Triple T = llvm::Triple(Triple); 5031 if (T.isiOS()) 5032 UseSignedCharForObjCBool = false; 5033 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 5034 } 5035 5036 bool handleTargetFeatures(std::vector<std::string> &Features, 5037 DiagnosticsEngine &Diags) override { 5038 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 5039 Diags)) 5040 return false; 5041 // We now know the features we have: we can decide how to align vectors. 5042 MaxVectorAlign = 5043 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 5044 return true; 5045 } 5046 }; 5047 5048 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 5049 public: 5050 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5051 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5052 IntMaxType = SignedLongLong; 5053 Int64Type = SignedLongLong; 5054 } 5055 }; 5056 5057 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 5058 public: 5059 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5060 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5061 IntMaxType = SignedLongLong; 5062 Int64Type = SignedLongLong; 5063 } 5064 }; 5065 5066 class ARMTargetInfo : public TargetInfo { 5067 // Possible FPU choices. 5068 enum FPUMode { 5069 VFP2FPU = (1 << 0), 5070 VFP3FPU = (1 << 1), 5071 VFP4FPU = (1 << 2), 5072 NeonFPU = (1 << 3), 5073 FPARMV8 = (1 << 4) 5074 }; 5075 5076 // Possible HWDiv features. 5077 enum HWDivMode { 5078 HWDivThumb = (1 << 0), 5079 HWDivARM = (1 << 1) 5080 }; 5081 5082 static bool FPUModeIsVFP(FPUMode Mode) { 5083 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 5084 } 5085 5086 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5087 static const char * const GCCRegNames[]; 5088 5089 std::string ABI, CPU; 5090 5091 StringRef CPUProfile; 5092 StringRef CPUAttr; 5093 5094 enum { 5095 FP_Default, 5096 FP_VFP, 5097 FP_Neon 5098 } FPMath; 5099 5100 unsigned ArchISA; 5101 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 5102 unsigned ArchProfile; 5103 unsigned ArchVersion; 5104 5105 unsigned FPU : 5; 5106 5107 unsigned IsAAPCS : 1; 5108 unsigned HWDiv : 2; 5109 5110 // Initialized via features. 5111 unsigned SoftFloat : 1; 5112 unsigned SoftFloatABI : 1; 5113 5114 unsigned CRC : 1; 5115 unsigned Crypto : 1; 5116 unsigned DSP : 1; 5117 unsigned Unaligned : 1; 5118 5119 enum { 5120 LDREX_B = (1 << 0), /// byte (8-bit) 5121 LDREX_H = (1 << 1), /// half (16-bit) 5122 LDREX_W = (1 << 2), /// word (32-bit) 5123 LDREX_D = (1 << 3), /// double (64-bit) 5124 }; 5125 5126 uint32_t LDREX; 5127 5128 // ACLE 6.5.1 Hardware floating point 5129 enum { 5130 HW_FP_HP = (1 << 1), /// half (16-bit) 5131 HW_FP_SP = (1 << 2), /// single (32-bit) 5132 HW_FP_DP = (1 << 3), /// double (64-bit) 5133 }; 5134 uint32_t HW_FP; 5135 5136 static const Builtin::Info BuiltinInfo[]; 5137 5138 void setABIAAPCS() { 5139 IsAAPCS = true; 5140 5141 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5142 const llvm::Triple &T = getTriple(); 5143 5144 // size_t is unsigned long on MachO-derived environments, NetBSD, 5145 // OpenBSD and Bitrig. 5146 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 5147 T.getOS() == llvm::Triple::OpenBSD || 5148 T.getOS() == llvm::Triple::Bitrig) 5149 SizeType = UnsignedLong; 5150 else 5151 SizeType = UnsignedInt; 5152 5153 switch (T.getOS()) { 5154 case llvm::Triple::NetBSD: 5155 case llvm::Triple::OpenBSD: 5156 WCharType = SignedInt; 5157 break; 5158 case llvm::Triple::Win32: 5159 WCharType = UnsignedShort; 5160 break; 5161 case llvm::Triple::Linux: 5162 default: 5163 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 5164 WCharType = UnsignedInt; 5165 break; 5166 } 5167 5168 UseBitFieldTypeAlignment = true; 5169 5170 ZeroLengthBitfieldBoundary = 0; 5171 5172 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 5173 // so set preferred for small types to 32. 5174 if (T.isOSBinFormatMachO()) { 5175 resetDataLayout(BigEndian 5176 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5177 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5178 } else if (T.isOSWindows()) { 5179 assert(!BigEndian && "Windows on ARM does not support big endian"); 5180 resetDataLayout("e" 5181 "-m:w" 5182 "-p:32:32" 5183 "-i64:64" 5184 "-v128:64:128" 5185 "-a:0:32" 5186 "-n32" 5187 "-S64"); 5188 } else if (T.isOSNaCl()) { 5189 assert(!BigEndian && "NaCl on ARM does not support big endian"); 5190 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 5191 } else { 5192 resetDataLayout(BigEndian 5193 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5194 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5195 } 5196 5197 // FIXME: Enumerated types are variable width in straight AAPCS. 5198 } 5199 5200 void setABIAPCS(bool IsAAPCS16) { 5201 const llvm::Triple &T = getTriple(); 5202 5203 IsAAPCS = false; 5204 5205 if (IsAAPCS16) 5206 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5207 else 5208 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 5209 5210 // size_t is unsigned int on FreeBSD. 5211 if (T.getOS() == llvm::Triple::FreeBSD) 5212 SizeType = UnsignedInt; 5213 else 5214 SizeType = UnsignedLong; 5215 5216 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 5217 WCharType = SignedInt; 5218 5219 // Do not respect the alignment of bit-field types when laying out 5220 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 5221 UseBitFieldTypeAlignment = false; 5222 5223 /// gcc forces the alignment to 4 bytes, regardless of the type of the 5224 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 5225 /// gcc. 5226 ZeroLengthBitfieldBoundary = 32; 5227 5228 if (T.isOSBinFormatMachO() && IsAAPCS16) { 5229 assert(!BigEndian && "AAPCS16 does not support big-endian"); 5230 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 5231 } else if (T.isOSBinFormatMachO()) 5232 resetDataLayout( 5233 BigEndian 5234 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5235 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5236 else 5237 resetDataLayout( 5238 BigEndian 5239 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5240 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5241 5242 // FIXME: Override "preferred align" for double and long long. 5243 } 5244 5245 void setArchInfo() { 5246 StringRef ArchName = getTriple().getArchName(); 5247 5248 ArchISA = llvm::ARM::parseArchISA(ArchName); 5249 CPU = llvm::ARM::getDefaultCPU(ArchName); 5250 unsigned AK = llvm::ARM::parseArch(ArchName); 5251 if (AK != llvm::ARM::AK_INVALID) 5252 ArchKind = AK; 5253 setArchInfo(ArchKind); 5254 } 5255 5256 void setArchInfo(unsigned Kind) { 5257 StringRef SubArch; 5258 5259 // cache TargetParser info 5260 ArchKind = Kind; 5261 SubArch = llvm::ARM::getSubArch(ArchKind); 5262 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 5263 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 5264 5265 // cache CPU related strings 5266 CPUAttr = getCPUAttr(); 5267 CPUProfile = getCPUProfile(); 5268 } 5269 5270 void setAtomic() { 5271 // when triple does not specify a sub arch, 5272 // then we are not using inline atomics 5273 bool ShouldUseInlineAtomic = 5274 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 5275 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 5276 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 5277 if (ArchProfile == llvm::ARM::PK_M) { 5278 MaxAtomicPromoteWidth = 32; 5279 if (ShouldUseInlineAtomic) 5280 MaxAtomicInlineWidth = 32; 5281 } 5282 else { 5283 MaxAtomicPromoteWidth = 64; 5284 if (ShouldUseInlineAtomic) 5285 MaxAtomicInlineWidth = 64; 5286 } 5287 } 5288 5289 bool isThumb() const { 5290 return (ArchISA == llvm::ARM::IK_THUMB); 5291 } 5292 5293 bool supportsThumb() const { 5294 return CPUAttr.count('T') || ArchVersion >= 6; 5295 } 5296 5297 bool supportsThumb2() const { 5298 return CPUAttr.equals("6T2") || 5299 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 5300 } 5301 5302 StringRef getCPUAttr() const { 5303 // For most sub-arches, the build attribute CPU name is enough. 5304 // For Cortex variants, it's slightly different. 5305 switch(ArchKind) { 5306 default: 5307 return llvm::ARM::getCPUAttr(ArchKind); 5308 case llvm::ARM::AK_ARMV6M: 5309 return "6M"; 5310 case llvm::ARM::AK_ARMV7S: 5311 return "7S"; 5312 case llvm::ARM::AK_ARMV7A: 5313 return "7A"; 5314 case llvm::ARM::AK_ARMV7R: 5315 return "7R"; 5316 case llvm::ARM::AK_ARMV7M: 5317 return "7M"; 5318 case llvm::ARM::AK_ARMV7EM: 5319 return "7EM"; 5320 case llvm::ARM::AK_ARMV7VE: 5321 return "7VE"; 5322 case llvm::ARM::AK_ARMV8A: 5323 return "8A"; 5324 case llvm::ARM::AK_ARMV8_1A: 5325 return "8_1A"; 5326 case llvm::ARM::AK_ARMV8_2A: 5327 return "8_2A"; 5328 case llvm::ARM::AK_ARMV8MBaseline: 5329 return "8M_BASE"; 5330 case llvm::ARM::AK_ARMV8MMainline: 5331 return "8M_MAIN"; 5332 case llvm::ARM::AK_ARMV8R: 5333 return "8R"; 5334 } 5335 } 5336 5337 StringRef getCPUProfile() const { 5338 switch(ArchProfile) { 5339 case llvm::ARM::PK_A: 5340 return "A"; 5341 case llvm::ARM::PK_R: 5342 return "R"; 5343 case llvm::ARM::PK_M: 5344 return "M"; 5345 default: 5346 return ""; 5347 } 5348 } 5349 5350 public: 5351 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5352 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 5353 HW_FP(0) { 5354 5355 switch (getTriple().getOS()) { 5356 case llvm::Triple::NetBSD: 5357 case llvm::Triple::OpenBSD: 5358 PtrDiffType = SignedLong; 5359 break; 5360 default: 5361 PtrDiffType = SignedInt; 5362 break; 5363 } 5364 5365 // Cache arch related info. 5366 setArchInfo(); 5367 5368 // {} in inline assembly are neon specifiers, not assembly variant 5369 // specifiers. 5370 NoAsmVariants = true; 5371 5372 // FIXME: This duplicates code from the driver that sets the -target-abi 5373 // option - this code is used if -target-abi isn't passed and should 5374 // be unified in some way. 5375 if (Triple.isOSBinFormatMachO()) { 5376 // The backend is hardwired to assume AAPCS for M-class processors, ensure 5377 // the frontend matches that. 5378 if (Triple.getEnvironment() == llvm::Triple::EABI || 5379 Triple.getOS() == llvm::Triple::UnknownOS || 5380 ArchProfile == llvm::ARM::PK_M) { 5381 setABI("aapcs"); 5382 } else if (Triple.isWatchABI()) { 5383 setABI("aapcs16"); 5384 } else { 5385 setABI("apcs-gnu"); 5386 } 5387 } else if (Triple.isOSWindows()) { 5388 // FIXME: this is invalid for WindowsCE 5389 setABI("aapcs"); 5390 } else { 5391 // Select the default based on the platform. 5392 switch (Triple.getEnvironment()) { 5393 case llvm::Triple::Android: 5394 case llvm::Triple::GNUEABI: 5395 case llvm::Triple::GNUEABIHF: 5396 case llvm::Triple::MuslEABI: 5397 case llvm::Triple::MuslEABIHF: 5398 setABI("aapcs-linux"); 5399 break; 5400 case llvm::Triple::EABIHF: 5401 case llvm::Triple::EABI: 5402 setABI("aapcs"); 5403 break; 5404 case llvm::Triple::GNU: 5405 setABI("apcs-gnu"); 5406 break; 5407 default: 5408 if (Triple.getOS() == llvm::Triple::NetBSD) 5409 setABI("apcs-gnu"); 5410 else if (Triple.getOS() == llvm::Triple::OpenBSD) 5411 setABI("aapcs-linux"); 5412 else 5413 setABI("aapcs"); 5414 break; 5415 } 5416 } 5417 5418 // ARM targets default to using the ARM C++ ABI. 5419 TheCXXABI.set(TargetCXXABI::GenericARM); 5420 5421 // ARM has atomics up to 8 bytes 5422 setAtomic(); 5423 5424 // Maximum alignment for ARM NEON data types should be 64-bits (AAPCS) 5425 if (IsAAPCS && (Triple.getEnvironment() != llvm::Triple::Android)) 5426 MaxVectorAlign = 64; 5427 5428 // Do force alignment of members that follow zero length bitfields. If 5429 // the alignment of the zero-length bitfield is greater than the member 5430 // that follows it, `bar', `bar' will be aligned as the type of the 5431 // zero length bitfield. 5432 UseZeroLengthBitfieldAlignment = true; 5433 5434 if (Triple.getOS() == llvm::Triple::Linux || 5435 Triple.getOS() == llvm::Triple::UnknownOS) 5436 this->MCountName = 5437 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 5438 } 5439 5440 StringRef getABI() const override { return ABI; } 5441 5442 bool setABI(const std::string &Name) override { 5443 ABI = Name; 5444 5445 // The defaults (above) are for AAPCS, check if we need to change them. 5446 // 5447 // FIXME: We need support for -meabi... we could just mangle it into the 5448 // name. 5449 if (Name == "apcs-gnu" || Name == "aapcs16") { 5450 setABIAPCS(Name == "aapcs16"); 5451 return true; 5452 } 5453 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 5454 setABIAAPCS(); 5455 return true; 5456 } 5457 return false; 5458 } 5459 5460 // FIXME: This should be based on Arch attributes, not CPU names. 5461 bool 5462 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5463 StringRef CPU, 5464 const std::vector<std::string> &FeaturesVec) const override { 5465 5466 std::vector<StringRef> TargetFeatures; 5467 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 5468 5469 // get default FPU features 5470 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 5471 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 5472 5473 // get default Extension features 5474 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 5475 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 5476 5477 for (auto Feature : TargetFeatures) 5478 if (Feature[0] == '+') 5479 Features[Feature.drop_front(1)] = true; 5480 5481 // Enable or disable thumb-mode explicitly per function to enable mixed 5482 // ARM and Thumb code generation. 5483 if (isThumb()) 5484 Features["thumb-mode"] = true; 5485 else 5486 Features["thumb-mode"] = false; 5487 5488 // Convert user-provided arm and thumb GNU target attributes to 5489 // [-|+]thumb-mode target features respectively. 5490 std::vector<std::string> UpdatedFeaturesVec(FeaturesVec); 5491 for (auto &Feature : UpdatedFeaturesVec) { 5492 if (Feature.compare("+arm") == 0) 5493 Feature = "-thumb-mode"; 5494 else if (Feature.compare("+thumb") == 0) 5495 Feature = "+thumb-mode"; 5496 } 5497 5498 return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec); 5499 } 5500 5501 bool handleTargetFeatures(std::vector<std::string> &Features, 5502 DiagnosticsEngine &Diags) override { 5503 FPU = 0; 5504 CRC = 0; 5505 Crypto = 0; 5506 DSP = 0; 5507 Unaligned = 1; 5508 SoftFloat = SoftFloatABI = false; 5509 HWDiv = 0; 5510 5511 // This does not diagnose illegal cases like having both 5512 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5513 uint32_t HW_FP_remove = 0; 5514 for (const auto &Feature : Features) { 5515 if (Feature == "+soft-float") { 5516 SoftFloat = true; 5517 } else if (Feature == "+soft-float-abi") { 5518 SoftFloatABI = true; 5519 } else if (Feature == "+vfp2") { 5520 FPU |= VFP2FPU; 5521 HW_FP |= HW_FP_SP | HW_FP_DP; 5522 } else if (Feature == "+vfp3") { 5523 FPU |= VFP3FPU; 5524 HW_FP |= HW_FP_SP | HW_FP_DP; 5525 } else if (Feature == "+vfp4") { 5526 FPU |= VFP4FPU; 5527 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5528 } else if (Feature == "+fp-armv8") { 5529 FPU |= FPARMV8; 5530 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5531 } else if (Feature == "+neon") { 5532 FPU |= NeonFPU; 5533 HW_FP |= HW_FP_SP | HW_FP_DP; 5534 } else if (Feature == "+hwdiv") { 5535 HWDiv |= HWDivThumb; 5536 } else if (Feature == "+hwdiv-arm") { 5537 HWDiv |= HWDivARM; 5538 } else if (Feature == "+crc") { 5539 CRC = 1; 5540 } else if (Feature == "+crypto") { 5541 Crypto = 1; 5542 } else if (Feature == "+dsp") { 5543 DSP = 1; 5544 } else if (Feature == "+fp-only-sp") { 5545 HW_FP_remove |= HW_FP_DP; 5546 } else if (Feature == "+strict-align") { 5547 Unaligned = 0; 5548 } else if (Feature == "+fp16") { 5549 HW_FP |= HW_FP_HP; 5550 } 5551 } 5552 HW_FP &= ~HW_FP_remove; 5553 5554 switch (ArchVersion) { 5555 case 6: 5556 if (ArchProfile == llvm::ARM::PK_M) 5557 LDREX = 0; 5558 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5559 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5560 else 5561 LDREX = LDREX_W; 5562 break; 5563 case 7: 5564 if (ArchProfile == llvm::ARM::PK_M) 5565 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5566 else 5567 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5568 break; 5569 case 8: 5570 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5571 } 5572 5573 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5574 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5575 return false; 5576 } 5577 5578 if (FPMath == FP_Neon) 5579 Features.push_back("+neonfp"); 5580 else if (FPMath == FP_VFP) 5581 Features.push_back("-neonfp"); 5582 5583 // Remove front-end specific options which the backend handles differently. 5584 auto Feature = 5585 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5586 if (Feature != Features.end()) 5587 Features.erase(Feature); 5588 5589 return true; 5590 } 5591 5592 bool hasFeature(StringRef Feature) const override { 5593 return llvm::StringSwitch<bool>(Feature) 5594 .Case("arm", true) 5595 .Case("aarch32", true) 5596 .Case("softfloat", SoftFloat) 5597 .Case("thumb", isThumb()) 5598 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5599 .Case("vfp", FPU && !SoftFloat) 5600 .Case("hwdiv", HWDiv & HWDivThumb) 5601 .Case("hwdiv-arm", HWDiv & HWDivARM) 5602 .Default(false); 5603 } 5604 5605 bool setCPU(const std::string &Name) override { 5606 if (Name != "generic") 5607 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5608 5609 if (ArchKind == llvm::ARM::AK_INVALID) 5610 return false; 5611 setAtomic(); 5612 CPU = Name; 5613 return true; 5614 } 5615 5616 bool setFPMath(StringRef Name) override; 5617 5618 void getTargetDefinesARMV81A(const LangOptions &Opts, 5619 MacroBuilder &Builder) const { 5620 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5621 } 5622 5623 void getTargetDefinesARMV82A(const LangOptions &Opts, 5624 MacroBuilder &Builder) const { 5625 // Also include the ARMv8.1-A defines 5626 getTargetDefinesARMV81A(Opts, Builder); 5627 } 5628 5629 void getTargetDefines(const LangOptions &Opts, 5630 MacroBuilder &Builder) const override { 5631 // Target identification. 5632 Builder.defineMacro("__arm"); 5633 Builder.defineMacro("__arm__"); 5634 // For bare-metal none-eabi. 5635 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5636 (getTriple().getEnvironment() == llvm::Triple::EABI || 5637 getTriple().getEnvironment() == llvm::Triple::EABIHF)) 5638 Builder.defineMacro("__ELF__"); 5639 5640 5641 // Target properties. 5642 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5643 5644 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5645 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5646 if (getTriple().isWatchABI()) 5647 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5648 5649 if (!CPUAttr.empty()) 5650 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5651 5652 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5653 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5654 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5655 5656 if (ArchVersion >= 8) { 5657 // ACLE 6.5.7 Crypto Extension 5658 if (Crypto) 5659 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5660 // ACLE 6.5.8 CRC32 Extension 5661 if (CRC) 5662 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5663 // ACLE 6.5.10 Numeric Maximum and Minimum 5664 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5665 // ACLE 6.5.9 Directed Rounding 5666 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5667 } 5668 5669 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5670 // is not defined for the M-profile. 5671 // NOTE that the default profile is assumed to be 'A' 5672 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5673 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5674 5675 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5676 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5677 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5678 // v7 and v8 architectures excluding v8-M Baseline. 5679 if (supportsThumb2()) 5680 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5681 else if (supportsThumb()) 5682 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5683 5684 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5685 // instruction set such as ARM or Thumb. 5686 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5687 5688 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5689 5690 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5691 if (!CPUProfile.empty()) 5692 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5693 5694 // ACLE 6.4.3 Unaligned access supported in hardware 5695 if (Unaligned) 5696 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5697 5698 // ACLE 6.4.4 LDREX/STREX 5699 if (LDREX) 5700 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5701 5702 // ACLE 6.4.5 CLZ 5703 if (ArchVersion == 5 || 5704 (ArchVersion == 6 && CPUProfile != "M") || 5705 ArchVersion > 6) 5706 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5707 5708 // ACLE 6.5.1 Hardware Floating Point 5709 if (HW_FP) 5710 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5711 5712 // ACLE predefines. 5713 Builder.defineMacro("__ARM_ACLE", "200"); 5714 5715 // FP16 support (we currently only support IEEE format). 5716 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5717 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5718 5719 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5720 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5721 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5722 5723 // Subtarget options. 5724 5725 // FIXME: It's more complicated than this and we don't really support 5726 // interworking. 5727 // Windows on ARM does not "support" interworking 5728 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5729 Builder.defineMacro("__THUMB_INTERWORK__"); 5730 5731 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5732 // Embedded targets on Darwin follow AAPCS, but not EABI. 5733 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5734 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5735 Builder.defineMacro("__ARM_EABI__"); 5736 Builder.defineMacro("__ARM_PCS", "1"); 5737 } 5738 5739 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5740 ABI == "aapcs16") 5741 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5742 5743 if (SoftFloat) 5744 Builder.defineMacro("__SOFTFP__"); 5745 5746 if (ArchKind == llvm::ARM::AK_XSCALE) 5747 Builder.defineMacro("__XSCALE__"); 5748 5749 if (isThumb()) { 5750 Builder.defineMacro("__THUMBEL__"); 5751 Builder.defineMacro("__thumb__"); 5752 if (supportsThumb2()) 5753 Builder.defineMacro("__thumb2__"); 5754 } 5755 5756 // ACLE 6.4.9 32-bit SIMD instructions 5757 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5758 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5759 5760 // ACLE 6.4.10 Hardware Integer Divide 5761 if (((HWDiv & HWDivThumb) && isThumb()) || 5762 ((HWDiv & HWDivARM) && !isThumb())) { 5763 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5764 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5765 } 5766 5767 // Note, this is always on in gcc, even though it doesn't make sense. 5768 Builder.defineMacro("__APCS_32__"); 5769 5770 if (FPUModeIsVFP((FPUMode) FPU)) { 5771 Builder.defineMacro("__VFP_FP__"); 5772 if (FPU & VFP2FPU) 5773 Builder.defineMacro("__ARM_VFPV2__"); 5774 if (FPU & VFP3FPU) 5775 Builder.defineMacro("__ARM_VFPV3__"); 5776 if (FPU & VFP4FPU) 5777 Builder.defineMacro("__ARM_VFPV4__"); 5778 if (FPU & FPARMV8) 5779 Builder.defineMacro("__ARM_FPV5__"); 5780 } 5781 5782 // This only gets set when Neon instructions are actually available, unlike 5783 // the VFP define, hence the soft float and arch check. This is subtly 5784 // different from gcc, we follow the intent which was that it should be set 5785 // when Neon instructions are actually available. 5786 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5787 Builder.defineMacro("__ARM_NEON", "1"); 5788 Builder.defineMacro("__ARM_NEON__"); 5789 // current AArch32 NEON implementations do not support double-precision 5790 // floating-point even when it is present in VFP. 5791 Builder.defineMacro("__ARM_NEON_FP", 5792 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5793 } 5794 5795 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5796 Opts.ShortWChar ? "2" : "4"); 5797 5798 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5799 Opts.ShortEnums ? "1" : "4"); 5800 5801 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5802 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5803 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5804 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5805 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5806 } 5807 5808 // ACLE 6.4.7 DSP instructions 5809 if (DSP) { 5810 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5811 } 5812 5813 // ACLE 6.4.8 Saturation instructions 5814 bool SAT = false; 5815 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5816 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5817 SAT = true; 5818 } 5819 5820 // ACLE 6.4.6 Q (saturation) flag 5821 if (DSP || SAT) 5822 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5823 5824 if (Opts.UnsafeFPMath) 5825 Builder.defineMacro("__ARM_FP_FAST", "1"); 5826 5827 switch(ArchKind) { 5828 default: break; 5829 case llvm::ARM::AK_ARMV8_1A: 5830 getTargetDefinesARMV81A(Opts, Builder); 5831 break; 5832 case llvm::ARM::AK_ARMV8_2A: 5833 getTargetDefinesARMV82A(Opts, Builder); 5834 break; 5835 } 5836 } 5837 5838 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5839 return llvm::makeArrayRef(BuiltinInfo, 5840 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5841 } 5842 bool isCLZForZeroUndef() const override { return false; } 5843 BuiltinVaListKind getBuiltinVaListKind() const override { 5844 return IsAAPCS 5845 ? AAPCSABIBuiltinVaList 5846 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5847 : TargetInfo::VoidPtrBuiltinVaList); 5848 } 5849 ArrayRef<const char *> getGCCRegNames() const override; 5850 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5851 bool validateAsmConstraint(const char *&Name, 5852 TargetInfo::ConstraintInfo &Info) const override { 5853 switch (*Name) { 5854 default: break; 5855 case 'l': // r0-r7 5856 case 'h': // r8-r15 5857 case 't': // VFP Floating point register single precision 5858 case 'w': // VFP Floating point register double precision 5859 Info.setAllowsRegister(); 5860 return true; 5861 case 'I': 5862 case 'J': 5863 case 'K': 5864 case 'L': 5865 case 'M': 5866 // FIXME 5867 return true; 5868 case 'Q': // A memory address that is a single base register. 5869 Info.setAllowsMemory(); 5870 return true; 5871 case 'U': // a memory reference... 5872 switch (Name[1]) { 5873 case 'q': // ...ARMV4 ldrsb 5874 case 'v': // ...VFP load/store (reg+constant offset) 5875 case 'y': // ...iWMMXt load/store 5876 case 't': // address valid for load/store opaque types wider 5877 // than 128-bits 5878 case 'n': // valid address for Neon doubleword vector load/store 5879 case 'm': // valid address for Neon element and structure load/store 5880 case 's': // valid address for non-offset loads/stores of quad-word 5881 // values in four ARM registers 5882 Info.setAllowsMemory(); 5883 Name++; 5884 return true; 5885 } 5886 } 5887 return false; 5888 } 5889 std::string convertConstraint(const char *&Constraint) const override { 5890 std::string R; 5891 switch (*Constraint) { 5892 case 'U': // Two-character constraint; add "^" hint for later parsing. 5893 R = std::string("^") + std::string(Constraint, 2); 5894 Constraint++; 5895 break; 5896 case 'p': // 'p' should be translated to 'r' by default. 5897 R = std::string("r"); 5898 break; 5899 default: 5900 return std::string(1, *Constraint); 5901 } 5902 return R; 5903 } 5904 bool 5905 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5906 std::string &SuggestedModifier) const override { 5907 bool isOutput = (Constraint[0] == '='); 5908 bool isInOut = (Constraint[0] == '+'); 5909 5910 // Strip off constraint modifiers. 5911 while (Constraint[0] == '=' || 5912 Constraint[0] == '+' || 5913 Constraint[0] == '&') 5914 Constraint = Constraint.substr(1); 5915 5916 switch (Constraint[0]) { 5917 default: break; 5918 case 'r': { 5919 switch (Modifier) { 5920 default: 5921 return (isInOut || isOutput || Size <= 64); 5922 case 'q': 5923 // A register of size 32 cannot fit a vector type. 5924 return false; 5925 } 5926 } 5927 } 5928 5929 return true; 5930 } 5931 const char *getClobbers() const override { 5932 // FIXME: Is this really right? 5933 return ""; 5934 } 5935 5936 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5937 switch (CC) { 5938 case CC_AAPCS: 5939 case CC_AAPCS_VFP: 5940 case CC_Swift: 5941 case CC_OpenCLKernel: 5942 return CCCR_OK; 5943 default: 5944 return CCCR_Warning; 5945 } 5946 } 5947 5948 int getEHDataRegisterNumber(unsigned RegNo) const override { 5949 if (RegNo == 0) return 0; 5950 if (RegNo == 1) return 1; 5951 return -1; 5952 } 5953 5954 bool hasSjLjLowering() const override { 5955 return true; 5956 } 5957 }; 5958 5959 bool ARMTargetInfo::setFPMath(StringRef Name) { 5960 if (Name == "neon") { 5961 FPMath = FP_Neon; 5962 return true; 5963 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5964 Name == "vfp4") { 5965 FPMath = FP_VFP; 5966 return true; 5967 } 5968 return false; 5969 } 5970 5971 const char * const ARMTargetInfo::GCCRegNames[] = { 5972 // Integer registers 5973 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5974 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5975 5976 // Float registers 5977 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5978 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5979 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5980 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5981 5982 // Double registers 5983 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5984 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5985 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5986 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5987 5988 // Quad registers 5989 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5990 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5991 }; 5992 5993 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5994 return llvm::makeArrayRef(GCCRegNames); 5995 } 5996 5997 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5998 { { "a1" }, "r0" }, 5999 { { "a2" }, "r1" }, 6000 { { "a3" }, "r2" }, 6001 { { "a4" }, "r3" }, 6002 { { "v1" }, "r4" }, 6003 { { "v2" }, "r5" }, 6004 { { "v3" }, "r6" }, 6005 { { "v4" }, "r7" }, 6006 { { "v5" }, "r8" }, 6007 { { "v6", "rfp" }, "r9" }, 6008 { { "sl" }, "r10" }, 6009 { { "fp" }, "r11" }, 6010 { { "ip" }, "r12" }, 6011 { { "r13" }, "sp" }, 6012 { { "r14" }, "lr" }, 6013 { { "r15" }, "pc" }, 6014 // The S, D and Q registers overlap, but aren't really aliases; we 6015 // don't want to substitute one of these for a different-sized one. 6016 }; 6017 6018 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 6019 return llvm::makeArrayRef(GCCRegAliases); 6020 } 6021 6022 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 6023 #define BUILTIN(ID, TYPE, ATTRS) \ 6024 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6025 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6026 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6027 #include "clang/Basic/BuiltinsNEON.def" 6028 6029 #define BUILTIN(ID, TYPE, ATTRS) \ 6030 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6031 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 6032 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 6033 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6034 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6035 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 6036 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 6037 #include "clang/Basic/BuiltinsARM.def" 6038 }; 6039 6040 class ARMleTargetInfo : public ARMTargetInfo { 6041 public: 6042 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6043 : ARMTargetInfo(Triple, Opts) {} 6044 void getTargetDefines(const LangOptions &Opts, 6045 MacroBuilder &Builder) const override { 6046 Builder.defineMacro("__ARMEL__"); 6047 ARMTargetInfo::getTargetDefines(Opts, Builder); 6048 } 6049 }; 6050 6051 class ARMbeTargetInfo : public ARMTargetInfo { 6052 public: 6053 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6054 : ARMTargetInfo(Triple, Opts) {} 6055 void getTargetDefines(const LangOptions &Opts, 6056 MacroBuilder &Builder) const override { 6057 Builder.defineMacro("__ARMEB__"); 6058 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6059 ARMTargetInfo::getTargetDefines(Opts, Builder); 6060 } 6061 }; 6062 6063 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 6064 const llvm::Triple Triple; 6065 public: 6066 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6067 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 6068 WCharType = UnsignedShort; 6069 SizeType = UnsignedInt; 6070 } 6071 void getVisualStudioDefines(const LangOptions &Opts, 6072 MacroBuilder &Builder) const { 6073 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 6074 6075 // FIXME: this is invalid for WindowsCE 6076 Builder.defineMacro("_M_ARM_NT", "1"); 6077 Builder.defineMacro("_M_ARMT", "_M_ARM"); 6078 Builder.defineMacro("_M_THUMB", "_M_ARM"); 6079 6080 assert((Triple.getArch() == llvm::Triple::arm || 6081 Triple.getArch() == llvm::Triple::thumb) && 6082 "invalid architecture for Windows ARM target info"); 6083 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 6084 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 6085 6086 // TODO map the complete set of values 6087 // 31: VFPv3 40: VFPv4 6088 Builder.defineMacro("_M_ARM_FP", "31"); 6089 } 6090 BuiltinVaListKind getBuiltinVaListKind() const override { 6091 return TargetInfo::CharPtrBuiltinVaList; 6092 } 6093 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6094 switch (CC) { 6095 case CC_X86StdCall: 6096 case CC_X86ThisCall: 6097 case CC_X86FastCall: 6098 case CC_X86VectorCall: 6099 return CCCR_Ignore; 6100 case CC_C: 6101 case CC_OpenCLKernel: 6102 return CCCR_OK; 6103 default: 6104 return CCCR_Warning; 6105 } 6106 } 6107 }; 6108 6109 // Windows ARM + Itanium C++ ABI Target 6110 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 6111 public: 6112 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 6113 const TargetOptions &Opts) 6114 : WindowsARMTargetInfo(Triple, Opts) { 6115 TheCXXABI.set(TargetCXXABI::GenericARM); 6116 } 6117 6118 void getTargetDefines(const LangOptions &Opts, 6119 MacroBuilder &Builder) const override { 6120 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6121 6122 if (Opts.MSVCCompat) 6123 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 6124 } 6125 }; 6126 6127 // Windows ARM, MS (C++) ABI 6128 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 6129 public: 6130 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 6131 const TargetOptions &Opts) 6132 : WindowsARMTargetInfo(Triple, Opts) { 6133 TheCXXABI.set(TargetCXXABI::Microsoft); 6134 } 6135 6136 void getTargetDefines(const LangOptions &Opts, 6137 MacroBuilder &Builder) const override { 6138 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6139 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 6140 } 6141 }; 6142 6143 // ARM MinGW target 6144 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 6145 public: 6146 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6147 : WindowsARMTargetInfo(Triple, Opts) { 6148 TheCXXABI.set(TargetCXXABI::GenericARM); 6149 } 6150 6151 void getTargetDefines(const LangOptions &Opts, 6152 MacroBuilder &Builder) const override { 6153 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6154 DefineStd(Builder, "WIN32", Opts); 6155 DefineStd(Builder, "WINNT", Opts); 6156 Builder.defineMacro("_ARM_"); 6157 addMinGWDefines(Opts, Builder); 6158 } 6159 }; 6160 6161 // ARM Cygwin target 6162 class CygwinARMTargetInfo : public ARMleTargetInfo { 6163 public: 6164 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6165 : ARMleTargetInfo(Triple, Opts) { 6166 TLSSupported = false; 6167 WCharType = UnsignedShort; 6168 DoubleAlign = LongLongAlign = 64; 6169 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 6170 } 6171 void getTargetDefines(const LangOptions &Opts, 6172 MacroBuilder &Builder) const override { 6173 ARMleTargetInfo::getTargetDefines(Opts, Builder); 6174 Builder.defineMacro("_ARM_"); 6175 Builder.defineMacro("__CYGWIN__"); 6176 Builder.defineMacro("__CYGWIN32__"); 6177 DefineStd(Builder, "unix", Opts); 6178 if (Opts.CPlusPlus) 6179 Builder.defineMacro("_GNU_SOURCE"); 6180 } 6181 }; 6182 6183 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 6184 protected: 6185 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6186 MacroBuilder &Builder) const override { 6187 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6188 } 6189 6190 public: 6191 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6192 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 6193 HasAlignMac68kSupport = true; 6194 // iOS always has 64-bit atomic instructions. 6195 // FIXME: This should be based off of the target features in 6196 // ARMleTargetInfo. 6197 MaxAtomicInlineWidth = 64; 6198 6199 if (Triple.isWatchABI()) { 6200 // Darwin on iOS uses a variant of the ARM C++ ABI. 6201 TheCXXABI.set(TargetCXXABI::WatchOS); 6202 6203 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 6204 // size_t is long, it's a bit weird for it to be int. 6205 PtrDiffType = SignedLong; 6206 6207 // BOOL should be a real boolean on the new ABI 6208 UseSignedCharForObjCBool = false; 6209 } else 6210 TheCXXABI.set(TargetCXXABI::iOS); 6211 } 6212 }; 6213 6214 class AArch64TargetInfo : public TargetInfo { 6215 virtual void setDataLayout() = 0; 6216 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6217 static const char *const GCCRegNames[]; 6218 6219 enum FPUModeEnum { 6220 FPUMode, 6221 NeonMode 6222 }; 6223 6224 unsigned FPU; 6225 unsigned CRC; 6226 unsigned Crypto; 6227 unsigned Unaligned; 6228 unsigned HasFullFP16; 6229 llvm::AArch64::ArchKind ArchKind; 6230 6231 static const Builtin::Info BuiltinInfo[]; 6232 6233 std::string ABI; 6234 6235 public: 6236 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6237 : TargetInfo(Triple), ABI("aapcs") { 6238 if (getTriple().getOS() == llvm::Triple::NetBSD || 6239 getTriple().getOS() == llvm::Triple::OpenBSD) { 6240 WCharType = SignedInt; 6241 6242 // NetBSD apparently prefers consistency across ARM targets to consistency 6243 // across 64-bit targets. 6244 Int64Type = SignedLongLong; 6245 IntMaxType = SignedLongLong; 6246 } else { 6247 WCharType = UnsignedInt; 6248 Int64Type = SignedLong; 6249 IntMaxType = SignedLong; 6250 } 6251 6252 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6253 MaxVectorAlign = 128; 6254 MaxAtomicInlineWidth = 128; 6255 MaxAtomicPromoteWidth = 128; 6256 6257 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 6258 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 6259 6260 // {} in inline assembly are neon specifiers, not assembly variant 6261 // specifiers. 6262 NoAsmVariants = true; 6263 6264 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 6265 // contributes to the alignment of the containing aggregate in the same way 6266 // a plain (non bit-field) member of that type would, without exception for 6267 // zero-sized or anonymous bit-fields." 6268 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 6269 UseZeroLengthBitfieldAlignment = true; 6270 6271 // AArch64 targets default to using the ARM C++ ABI. 6272 TheCXXABI.set(TargetCXXABI::GenericAArch64); 6273 6274 if (Triple.getOS() == llvm::Triple::Linux) 6275 this->MCountName = "\01_mcount"; 6276 else if (Triple.getOS() == llvm::Triple::UnknownOS) 6277 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 6278 } 6279 6280 StringRef getABI() const override { return ABI; } 6281 bool setABI(const std::string &Name) override { 6282 if (Name != "aapcs" && Name != "darwinpcs") 6283 return false; 6284 6285 ABI = Name; 6286 return true; 6287 } 6288 6289 bool setCPU(const std::string &Name) override { 6290 return Name == "generic" || 6291 llvm::AArch64::parseCPUArch(Name) != 6292 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 6293 } 6294 6295 void getTargetDefinesARMV81A(const LangOptions &Opts, 6296 MacroBuilder &Builder) const { 6297 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 6298 } 6299 6300 void getTargetDefinesARMV82A(const LangOptions &Opts, 6301 MacroBuilder &Builder) const { 6302 // Also include the ARMv8.1 defines 6303 getTargetDefinesARMV81A(Opts, Builder); 6304 6305 if (FPU == NeonMode && HasFullFP16) 6306 Builder.defineMacro("__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", "1"); 6307 } 6308 6309 void getTargetDefines(const LangOptions &Opts, 6310 MacroBuilder &Builder) const override { 6311 // Target identification. 6312 Builder.defineMacro("__aarch64__"); 6313 // For bare-metal none-eabi. 6314 if (getTriple().getOS() == llvm::Triple::UnknownOS && 6315 (getTriple().getEnvironment() == llvm::Triple::EABI || 6316 getTriple().getEnvironment() == llvm::Triple::EABIHF)) 6317 Builder.defineMacro("__ELF__"); 6318 6319 // Target properties. 6320 Builder.defineMacro("_LP64"); 6321 Builder.defineMacro("__LP64__"); 6322 6323 // ACLE predefines. Many can only have one possible value on v8 AArch64. 6324 Builder.defineMacro("__ARM_ACLE", "200"); 6325 Builder.defineMacro("__ARM_ARCH", "8"); 6326 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 6327 6328 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 6329 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 6330 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 6331 6332 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 6333 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 6334 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 6335 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 6336 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 6337 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 6338 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 6339 6340 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 6341 6342 // 0xe implies support for half, single and double precision operations. 6343 Builder.defineMacro("__ARM_FP", "0xE"); 6344 6345 // PCS specifies this for SysV variants, which is all we support. Other ABIs 6346 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 6347 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 6348 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 6349 6350 if (Opts.UnsafeFPMath) 6351 Builder.defineMacro("__ARM_FP_FAST", "1"); 6352 6353 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 6354 6355 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 6356 Opts.ShortEnums ? "1" : "4"); 6357 6358 if (FPU == NeonMode) { 6359 Builder.defineMacro("__ARM_NEON", "1"); 6360 // 64-bit NEON supports half, single and double precision operations. 6361 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 6362 } 6363 6364 if (CRC) 6365 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 6366 6367 if (Crypto) 6368 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 6369 6370 if (Unaligned) 6371 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 6372 6373 switch(ArchKind) { 6374 default: break; 6375 case llvm::AArch64::ArchKind::AK_ARMV8_1A: 6376 getTargetDefinesARMV81A(Opts, Builder); 6377 break; 6378 case llvm::AArch64::ArchKind::AK_ARMV8_2A: 6379 getTargetDefinesARMV82A(Opts, Builder); 6380 break; 6381 } 6382 6383 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 6384 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6385 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6386 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6387 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6388 } 6389 6390 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6391 return llvm::makeArrayRef(BuiltinInfo, 6392 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 6393 } 6394 6395 bool hasFeature(StringRef Feature) const override { 6396 return Feature == "aarch64" || 6397 Feature == "arm64" || 6398 Feature == "arm" || 6399 (Feature == "neon" && FPU == NeonMode); 6400 } 6401 6402 bool handleTargetFeatures(std::vector<std::string> &Features, 6403 DiagnosticsEngine &Diags) override { 6404 FPU = FPUMode; 6405 CRC = 0; 6406 Crypto = 0; 6407 Unaligned = 1; 6408 HasFullFP16 = 0; 6409 ArchKind = llvm::AArch64::ArchKind::AK_ARMV8A; 6410 6411 for (const auto &Feature : Features) { 6412 if (Feature == "+neon") 6413 FPU = NeonMode; 6414 if (Feature == "+crc") 6415 CRC = 1; 6416 if (Feature == "+crypto") 6417 Crypto = 1; 6418 if (Feature == "+strict-align") 6419 Unaligned = 0; 6420 if (Feature == "+v8.1a") 6421 ArchKind = llvm::AArch64::ArchKind::AK_ARMV8_1A; 6422 if (Feature == "+v8.2a") 6423 ArchKind = llvm::AArch64::ArchKind::AK_ARMV8_2A; 6424 if (Feature == "+fullfp16") 6425 HasFullFP16 = 1; 6426 } 6427 6428 setDataLayout(); 6429 6430 return true; 6431 } 6432 6433 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6434 switch (CC) { 6435 case CC_C: 6436 case CC_Swift: 6437 case CC_PreserveMost: 6438 case CC_PreserveAll: 6439 case CC_OpenCLKernel: 6440 return CCCR_OK; 6441 default: 6442 return CCCR_Warning; 6443 } 6444 } 6445 6446 bool isCLZForZeroUndef() const override { return false; } 6447 6448 BuiltinVaListKind getBuiltinVaListKind() const override { 6449 return TargetInfo::AArch64ABIBuiltinVaList; 6450 } 6451 6452 ArrayRef<const char *> getGCCRegNames() const override; 6453 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6454 6455 bool validateAsmConstraint(const char *&Name, 6456 TargetInfo::ConstraintInfo &Info) const override { 6457 switch (*Name) { 6458 default: 6459 return false; 6460 case 'w': // Floating point and SIMD registers (V0-V31) 6461 Info.setAllowsRegister(); 6462 return true; 6463 case 'I': // Constant that can be used with an ADD instruction 6464 case 'J': // Constant that can be used with a SUB instruction 6465 case 'K': // Constant that can be used with a 32-bit logical instruction 6466 case 'L': // Constant that can be used with a 64-bit logical instruction 6467 case 'M': // Constant that can be used as a 32-bit MOV immediate 6468 case 'N': // Constant that can be used as a 64-bit MOV immediate 6469 case 'Y': // Floating point constant zero 6470 case 'Z': // Integer constant zero 6471 return true; 6472 case 'Q': // A memory reference with base register and no offset 6473 Info.setAllowsMemory(); 6474 return true; 6475 case 'S': // A symbolic address 6476 Info.setAllowsRegister(); 6477 return true; 6478 case 'U': 6479 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 6480 // Utf: A memory address suitable for ldp/stp in TF mode. 6481 // Usa: An absolute symbolic address. 6482 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 6483 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 6484 case 'z': // Zero register, wzr or xzr 6485 Info.setAllowsRegister(); 6486 return true; 6487 case 'x': // Floating point and SIMD registers (V0-V15) 6488 Info.setAllowsRegister(); 6489 return true; 6490 } 6491 return false; 6492 } 6493 6494 bool 6495 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 6496 std::string &SuggestedModifier) const override { 6497 // Strip off constraint modifiers. 6498 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 6499 Constraint = Constraint.substr(1); 6500 6501 switch (Constraint[0]) { 6502 default: 6503 return true; 6504 case 'z': 6505 case 'r': { 6506 switch (Modifier) { 6507 case 'x': 6508 case 'w': 6509 // For now assume that the person knows what they're 6510 // doing with the modifier. 6511 return true; 6512 default: 6513 // By default an 'r' constraint will be in the 'x' 6514 // registers. 6515 if (Size == 64) 6516 return true; 6517 6518 SuggestedModifier = "w"; 6519 return false; 6520 } 6521 } 6522 } 6523 } 6524 6525 const char *getClobbers() const override { return ""; } 6526 6527 int getEHDataRegisterNumber(unsigned RegNo) const override { 6528 if (RegNo == 0) 6529 return 0; 6530 if (RegNo == 1) 6531 return 1; 6532 return -1; 6533 } 6534 }; 6535 6536 const char *const AArch64TargetInfo::GCCRegNames[] = { 6537 // 32-bit Integer registers 6538 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 6539 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 6540 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 6541 6542 // 64-bit Integer registers 6543 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 6544 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 6545 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 6546 6547 // 32-bit floating point regsisters 6548 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 6549 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 6550 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6551 6552 // 64-bit floating point regsisters 6553 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 6554 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 6555 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6556 6557 // Vector registers 6558 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6559 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6560 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6561 }; 6562 6563 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6564 return llvm::makeArrayRef(GCCRegNames); 6565 } 6566 6567 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6568 { { "w31" }, "wsp" }, 6569 { { "x29" }, "fp" }, 6570 { { "x30" }, "lr" }, 6571 { { "x31" }, "sp" }, 6572 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6573 // don't want to substitute one of these for a different-sized one. 6574 }; 6575 6576 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6577 return llvm::makeArrayRef(GCCRegAliases); 6578 } 6579 6580 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6581 #define BUILTIN(ID, TYPE, ATTRS) \ 6582 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6583 #include "clang/Basic/BuiltinsNEON.def" 6584 6585 #define BUILTIN(ID, TYPE, ATTRS) \ 6586 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6587 #include "clang/Basic/BuiltinsAArch64.def" 6588 }; 6589 6590 class AArch64leTargetInfo : public AArch64TargetInfo { 6591 void setDataLayout() override { 6592 if (getTriple().isOSBinFormatMachO()) 6593 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6594 else 6595 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6596 } 6597 6598 public: 6599 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6600 : AArch64TargetInfo(Triple, Opts) { 6601 } 6602 void getTargetDefines(const LangOptions &Opts, 6603 MacroBuilder &Builder) const override { 6604 Builder.defineMacro("__AARCH64EL__"); 6605 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6606 } 6607 }; 6608 6609 class MicrosoftARM64TargetInfo 6610 : public WindowsTargetInfo<AArch64leTargetInfo> { 6611 const llvm::Triple Triple; 6612 6613 public: 6614 MicrosoftARM64TargetInfo(const llvm::Triple &Triple, 6615 const TargetOptions &Opts) 6616 : WindowsTargetInfo<AArch64leTargetInfo>(Triple, Opts), Triple(Triple) { 6617 WCharType = UnsignedShort; 6618 SizeType = UnsignedLongLong; 6619 TheCXXABI.set(TargetCXXABI::Microsoft); 6620 } 6621 6622 void setDataLayout() override { 6623 resetDataLayout("e-m:w-i64:64-i128:128-n32:64-S128"); 6624 } 6625 6626 void getVisualStudioDefines(const LangOptions &Opts, 6627 MacroBuilder &Builder) const { 6628 WindowsTargetInfo<AArch64leTargetInfo>::getVisualStudioDefines(Opts, 6629 Builder); 6630 Builder.defineMacro("_WIN32", "1"); 6631 Builder.defineMacro("_WIN64", "1"); 6632 Builder.defineMacro("_M_ARM64", "1"); 6633 } 6634 6635 void getTargetDefines(const LangOptions &Opts, 6636 MacroBuilder &Builder) const override { 6637 WindowsTargetInfo::getTargetDefines(Opts, Builder); 6638 getVisualStudioDefines(Opts, Builder); 6639 } 6640 6641 BuiltinVaListKind getBuiltinVaListKind() const override { 6642 return TargetInfo::CharPtrBuiltinVaList; 6643 } 6644 }; 6645 6646 class AArch64beTargetInfo : public AArch64TargetInfo { 6647 void setDataLayout() override { 6648 assert(!getTriple().isOSBinFormatMachO()); 6649 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6650 } 6651 6652 public: 6653 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6654 : AArch64TargetInfo(Triple, Opts) {} 6655 void getTargetDefines(const LangOptions &Opts, 6656 MacroBuilder &Builder) const override { 6657 Builder.defineMacro("__AARCH64EB__"); 6658 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6659 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6660 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6661 } 6662 }; 6663 6664 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6665 protected: 6666 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6667 MacroBuilder &Builder) const override { 6668 Builder.defineMacro("__AARCH64_SIMD__"); 6669 Builder.defineMacro("__ARM64_ARCH_8__"); 6670 Builder.defineMacro("__ARM_NEON__"); 6671 Builder.defineMacro("__LITTLE_ENDIAN__"); 6672 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6673 Builder.defineMacro("__arm64", "1"); 6674 Builder.defineMacro("__arm64__", "1"); 6675 6676 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6677 } 6678 6679 public: 6680 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6681 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6682 Int64Type = SignedLongLong; 6683 WCharType = SignedInt; 6684 UseSignedCharForObjCBool = false; 6685 6686 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6687 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 6688 6689 TheCXXABI.set(TargetCXXABI::iOS64); 6690 } 6691 6692 BuiltinVaListKind getBuiltinVaListKind() const override { 6693 return TargetInfo::CharPtrBuiltinVaList; 6694 } 6695 }; 6696 6697 // Hexagon abstract base class 6698 class HexagonTargetInfo : public TargetInfo { 6699 static const Builtin::Info BuiltinInfo[]; 6700 static const char * const GCCRegNames[]; 6701 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6702 std::string CPU; 6703 bool HasHVX, HasHVXDouble; 6704 bool UseLongCalls; 6705 6706 public: 6707 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6708 : TargetInfo(Triple) { 6709 // Specify the vector alignment explicitly. For v512x1, the calculated 6710 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6711 // the required minimum of 64 bytes. 6712 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6713 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6714 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6715 SizeType = UnsignedInt; 6716 PtrDiffType = SignedInt; 6717 IntPtrType = SignedInt; 6718 6719 // {} in inline assembly are packet specifiers, not assembly variant 6720 // specifiers. 6721 NoAsmVariants = true; 6722 6723 LargeArrayMinWidth = 64; 6724 LargeArrayAlign = 64; 6725 UseBitFieldTypeAlignment = true; 6726 ZeroLengthBitfieldBoundary = 32; 6727 HasHVX = HasHVXDouble = false; 6728 UseLongCalls = false; 6729 } 6730 6731 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6732 return llvm::makeArrayRef(BuiltinInfo, 6733 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6734 } 6735 6736 bool validateAsmConstraint(const char *&Name, 6737 TargetInfo::ConstraintInfo &Info) const override { 6738 switch (*Name) { 6739 case 'v': 6740 case 'q': 6741 if (HasHVX) { 6742 Info.setAllowsRegister(); 6743 return true; 6744 } 6745 break; 6746 case 's': 6747 // Relocatable constant. 6748 return true; 6749 } 6750 return false; 6751 } 6752 6753 void getTargetDefines(const LangOptions &Opts, 6754 MacroBuilder &Builder) const override; 6755 6756 bool isCLZForZeroUndef() const override { return false; } 6757 6758 bool hasFeature(StringRef Feature) const override { 6759 return llvm::StringSwitch<bool>(Feature) 6760 .Case("hexagon", true) 6761 .Case("hvx", HasHVX) 6762 .Case("hvx-double", HasHVXDouble) 6763 .Case("long-calls", UseLongCalls) 6764 .Default(false); 6765 } 6766 6767 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6768 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6769 const override; 6770 6771 bool handleTargetFeatures(std::vector<std::string> &Features, 6772 DiagnosticsEngine &Diags) override; 6773 6774 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6775 bool Enabled) const override; 6776 6777 BuiltinVaListKind getBuiltinVaListKind() const override { 6778 return TargetInfo::CharPtrBuiltinVaList; 6779 } 6780 ArrayRef<const char *> getGCCRegNames() const override; 6781 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6782 const char *getClobbers() const override { 6783 return ""; 6784 } 6785 6786 static const char *getHexagonCPUSuffix(StringRef Name) { 6787 return llvm::StringSwitch<const char*>(Name) 6788 .Case("hexagonv4", "4") 6789 .Case("hexagonv5", "5") 6790 .Case("hexagonv55", "55") 6791 .Case("hexagonv60", "60") 6792 .Case("hexagonv62", "62") 6793 .Default(nullptr); 6794 } 6795 6796 bool setCPU(const std::string &Name) override { 6797 if (!getHexagonCPUSuffix(Name)) 6798 return false; 6799 CPU = Name; 6800 return true; 6801 } 6802 6803 int getEHDataRegisterNumber(unsigned RegNo) const override { 6804 return RegNo < 2 ? RegNo : -1; 6805 } 6806 }; 6807 6808 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6809 MacroBuilder &Builder) const { 6810 Builder.defineMacro("__qdsp6__", "1"); 6811 Builder.defineMacro("__hexagon__", "1"); 6812 6813 if (CPU == "hexagonv4") { 6814 Builder.defineMacro("__HEXAGON_V4__"); 6815 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6816 if (Opts.HexagonQdsp6Compat) { 6817 Builder.defineMacro("__QDSP6_V4__"); 6818 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6819 } 6820 } else if (CPU == "hexagonv5") { 6821 Builder.defineMacro("__HEXAGON_V5__"); 6822 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6823 if(Opts.HexagonQdsp6Compat) { 6824 Builder.defineMacro("__QDSP6_V5__"); 6825 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6826 } 6827 } else if (CPU == "hexagonv55") { 6828 Builder.defineMacro("__HEXAGON_V55__"); 6829 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6830 Builder.defineMacro("__QDSP6_V55__"); 6831 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6832 } else if (CPU == "hexagonv60") { 6833 Builder.defineMacro("__HEXAGON_V60__"); 6834 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6835 Builder.defineMacro("__QDSP6_V60__"); 6836 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6837 } else if (CPU == "hexagonv62") { 6838 Builder.defineMacro("__HEXAGON_V62__"); 6839 Builder.defineMacro("__HEXAGON_ARCH__", "62"); 6840 } 6841 6842 if (hasFeature("hvx")) { 6843 Builder.defineMacro("__HVX__"); 6844 if (hasFeature("hvx-double")) 6845 Builder.defineMacro("__HVXDBL__"); 6846 } 6847 } 6848 6849 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6850 DiagnosticsEngine &Diags, StringRef CPU, 6851 const std::vector<std::string> &FeaturesVec) const { 6852 // Default for v60: -hvx, -hvx-double. 6853 Features["hvx"] = false; 6854 Features["hvx-double"] = false; 6855 Features["long-calls"] = false; 6856 6857 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6858 } 6859 6860 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6861 DiagnosticsEngine &Diags) { 6862 for (auto &F : Features) { 6863 if (F == "+hvx") 6864 HasHVX = true; 6865 else if (F == "-hvx") 6866 HasHVX = HasHVXDouble = false; 6867 else if (F == "+hvx-double") 6868 HasHVX = HasHVXDouble = true; 6869 else if (F == "-hvx-double") 6870 HasHVXDouble = false; 6871 6872 if (F == "+long-calls") 6873 UseLongCalls = true; 6874 else if (F == "-long-calls") 6875 UseLongCalls = false; 6876 } 6877 return true; 6878 } 6879 6880 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 6881 StringRef Name, bool Enabled) const { 6882 if (Enabled) { 6883 if (Name == "hvx-double") 6884 Features["hvx"] = true; 6885 } else { 6886 if (Name == "hvx") 6887 Features["hvx-double"] = false; 6888 } 6889 Features[Name] = Enabled; 6890 } 6891 6892 const char *const HexagonTargetInfo::GCCRegNames[] = { 6893 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6894 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6895 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6896 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6897 "p0", "p1", "p2", "p3", 6898 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6899 }; 6900 6901 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6902 return llvm::makeArrayRef(GCCRegNames); 6903 } 6904 6905 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6906 { { "sp" }, "r29" }, 6907 { { "fp" }, "r30" }, 6908 { { "lr" }, "r31" }, 6909 }; 6910 6911 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6912 return llvm::makeArrayRef(GCCRegAliases); 6913 } 6914 6915 6916 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6917 #define BUILTIN(ID, TYPE, ATTRS) \ 6918 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6919 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6920 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6921 #include "clang/Basic/BuiltinsHexagon.def" 6922 }; 6923 6924 class LanaiTargetInfo : public TargetInfo { 6925 // Class for Lanai (32-bit). 6926 // The CPU profiles supported by the Lanai backend 6927 enum CPUKind { 6928 CK_NONE, 6929 CK_V11, 6930 } CPU; 6931 6932 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6933 static const char *const GCCRegNames[]; 6934 6935 public: 6936 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6937 : TargetInfo(Triple) { 6938 // Description string has to be kept in sync with backend. 6939 resetDataLayout("E" // Big endian 6940 "-m:e" // ELF name manging 6941 "-p:32:32" // 32 bit pointers, 32 bit aligned 6942 "-i64:64" // 64 bit integers, 64 bit aligned 6943 "-a:0:32" // 32 bit alignment of objects of aggregate type 6944 "-n32" // 32 bit native integer width 6945 "-S64" // 64 bit natural stack alignment 6946 ); 6947 6948 // Setting RegParmMax equal to what mregparm was set to in the old 6949 // toolchain 6950 RegParmMax = 4; 6951 6952 // Set the default CPU to V11 6953 CPU = CK_V11; 6954 6955 // Temporary approach to make everything at least word-aligned and allow for 6956 // safely casting between pointers with different alignment requirements. 6957 // TODO: Remove this when there are no more cast align warnings on the 6958 // firmware. 6959 MinGlobalAlign = 32; 6960 } 6961 6962 void getTargetDefines(const LangOptions &Opts, 6963 MacroBuilder &Builder) const override { 6964 // Define __lanai__ when building for target lanai. 6965 Builder.defineMacro("__lanai__"); 6966 6967 // Set define for the CPU specified. 6968 switch (CPU) { 6969 case CK_V11: 6970 Builder.defineMacro("__LANAI_V11__"); 6971 break; 6972 case CK_NONE: 6973 llvm_unreachable("Unhandled target CPU"); 6974 } 6975 } 6976 6977 bool setCPU(const std::string &Name) override { 6978 CPU = llvm::StringSwitch<CPUKind>(Name) 6979 .Case("v11", CK_V11) 6980 .Default(CK_NONE); 6981 6982 return CPU != CK_NONE; 6983 } 6984 6985 bool hasFeature(StringRef Feature) const override { 6986 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6987 } 6988 6989 ArrayRef<const char *> getGCCRegNames() const override; 6990 6991 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6992 6993 BuiltinVaListKind getBuiltinVaListKind() const override { 6994 return TargetInfo::VoidPtrBuiltinVaList; 6995 } 6996 6997 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6998 6999 bool validateAsmConstraint(const char *&Name, 7000 TargetInfo::ConstraintInfo &info) const override { 7001 return false; 7002 } 7003 7004 const char *getClobbers() const override { return ""; } 7005 }; 7006 7007 const char *const LanaiTargetInfo::GCCRegNames[] = { 7008 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 7009 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 7010 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 7011 7012 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 7013 return llvm::makeArrayRef(GCCRegNames); 7014 } 7015 7016 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 7017 {{"pc"}, "r2"}, 7018 {{"sp"}, "r4"}, 7019 {{"fp"}, "r5"}, 7020 {{"rv"}, "r8"}, 7021 {{"rr1"}, "r10"}, 7022 {{"rr2"}, "r11"}, 7023 {{"rca"}, "r15"}, 7024 }; 7025 7026 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 7027 return llvm::makeArrayRef(GCCRegAliases); 7028 } 7029 7030 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 7031 class SparcTargetInfo : public TargetInfo { 7032 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 7033 static const char * const GCCRegNames[]; 7034 bool SoftFloat; 7035 public: 7036 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7037 : TargetInfo(Triple), SoftFloat(false) {} 7038 7039 int getEHDataRegisterNumber(unsigned RegNo) const override { 7040 if (RegNo == 0) return 24; 7041 if (RegNo == 1) return 25; 7042 return -1; 7043 } 7044 7045 bool handleTargetFeatures(std::vector<std::string> &Features, 7046 DiagnosticsEngine &Diags) override { 7047 // Check if software floating point is enabled 7048 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 7049 if (Feature != Features.end()) { 7050 SoftFloat = true; 7051 } 7052 return true; 7053 } 7054 void getTargetDefines(const LangOptions &Opts, 7055 MacroBuilder &Builder) const override { 7056 DefineStd(Builder, "sparc", Opts); 7057 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7058 7059 if (SoftFloat) 7060 Builder.defineMacro("SOFT_FLOAT", "1"); 7061 } 7062 7063 bool hasFeature(StringRef Feature) const override { 7064 return llvm::StringSwitch<bool>(Feature) 7065 .Case("softfloat", SoftFloat) 7066 .Case("sparc", true) 7067 .Default(false); 7068 } 7069 7070 bool hasSjLjLowering() const override { 7071 return true; 7072 } 7073 7074 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7075 // FIXME: Implement! 7076 return None; 7077 } 7078 BuiltinVaListKind getBuiltinVaListKind() const override { 7079 return TargetInfo::VoidPtrBuiltinVaList; 7080 } 7081 ArrayRef<const char *> getGCCRegNames() const override; 7082 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7083 bool validateAsmConstraint(const char *&Name, 7084 TargetInfo::ConstraintInfo &info) const override { 7085 // FIXME: Implement! 7086 switch (*Name) { 7087 case 'I': // Signed 13-bit constant 7088 case 'J': // Zero 7089 case 'K': // 32-bit constant with the low 12 bits clear 7090 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 7091 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 7092 case 'N': // Same as 'K' but zext (required for SIMode) 7093 case 'O': // The constant 4096 7094 return true; 7095 7096 case 'f': 7097 case 'e': 7098 info.setAllowsRegister(); 7099 return true; 7100 } 7101 return false; 7102 } 7103 const char *getClobbers() const override { 7104 // FIXME: Implement! 7105 return ""; 7106 } 7107 7108 // No Sparc V7 for now, the backend doesn't support it anyway. 7109 enum CPUKind { 7110 CK_GENERIC, 7111 CK_V8, 7112 CK_SUPERSPARC, 7113 CK_SPARCLITE, 7114 CK_F934, 7115 CK_HYPERSPARC, 7116 CK_SPARCLITE86X, 7117 CK_SPARCLET, 7118 CK_TSC701, 7119 CK_V9, 7120 CK_ULTRASPARC, 7121 CK_ULTRASPARC3, 7122 CK_NIAGARA, 7123 CK_NIAGARA2, 7124 CK_NIAGARA3, 7125 CK_NIAGARA4, 7126 CK_MYRIAD2100, 7127 CK_MYRIAD2150, 7128 CK_MYRIAD2450, 7129 CK_LEON2, 7130 CK_LEON2_AT697E, 7131 CK_LEON2_AT697F, 7132 CK_LEON3, 7133 CK_LEON3_UT699, 7134 CK_LEON3_GR712RC, 7135 CK_LEON4, 7136 CK_LEON4_GR740 7137 } CPU = CK_GENERIC; 7138 7139 enum CPUGeneration { 7140 CG_V8, 7141 CG_V9, 7142 }; 7143 7144 CPUGeneration getCPUGeneration(CPUKind Kind) const { 7145 switch (Kind) { 7146 case CK_GENERIC: 7147 case CK_V8: 7148 case CK_SUPERSPARC: 7149 case CK_SPARCLITE: 7150 case CK_F934: 7151 case CK_HYPERSPARC: 7152 case CK_SPARCLITE86X: 7153 case CK_SPARCLET: 7154 case CK_TSC701: 7155 case CK_MYRIAD2100: 7156 case CK_MYRIAD2150: 7157 case CK_MYRIAD2450: 7158 case CK_LEON2: 7159 case CK_LEON2_AT697E: 7160 case CK_LEON2_AT697F: 7161 case CK_LEON3: 7162 case CK_LEON3_UT699: 7163 case CK_LEON3_GR712RC: 7164 case CK_LEON4: 7165 case CK_LEON4_GR740: 7166 return CG_V8; 7167 case CK_V9: 7168 case CK_ULTRASPARC: 7169 case CK_ULTRASPARC3: 7170 case CK_NIAGARA: 7171 case CK_NIAGARA2: 7172 case CK_NIAGARA3: 7173 case CK_NIAGARA4: 7174 return CG_V9; 7175 } 7176 llvm_unreachable("Unexpected CPU kind"); 7177 } 7178 7179 CPUKind getCPUKind(StringRef Name) const { 7180 return llvm::StringSwitch<CPUKind>(Name) 7181 .Case("v8", CK_V8) 7182 .Case("supersparc", CK_SUPERSPARC) 7183 .Case("sparclite", CK_SPARCLITE) 7184 .Case("f934", CK_F934) 7185 .Case("hypersparc", CK_HYPERSPARC) 7186 .Case("sparclite86x", CK_SPARCLITE86X) 7187 .Case("sparclet", CK_SPARCLET) 7188 .Case("tsc701", CK_TSC701) 7189 .Case("v9", CK_V9) 7190 .Case("ultrasparc", CK_ULTRASPARC) 7191 .Case("ultrasparc3", CK_ULTRASPARC3) 7192 .Case("niagara", CK_NIAGARA) 7193 .Case("niagara2", CK_NIAGARA2) 7194 .Case("niagara3", CK_NIAGARA3) 7195 .Case("niagara4", CK_NIAGARA4) 7196 .Case("ma2100", CK_MYRIAD2100) 7197 .Case("ma2150", CK_MYRIAD2150) 7198 .Case("ma2450", CK_MYRIAD2450) 7199 // FIXME: the myriad2[.n] spellings are obsolete, 7200 // but a grace period is needed to allow updating dependent builds. 7201 .Case("myriad2", CK_MYRIAD2100) 7202 .Case("myriad2.1", CK_MYRIAD2100) 7203 .Case("myriad2.2", CK_MYRIAD2150) 7204 .Case("leon2", CK_LEON2) 7205 .Case("at697e", CK_LEON2_AT697E) 7206 .Case("at697f", CK_LEON2_AT697F) 7207 .Case("leon3", CK_LEON3) 7208 .Case("ut699", CK_LEON3_UT699) 7209 .Case("gr712rc", CK_LEON3_GR712RC) 7210 .Case("leon4", CK_LEON4) 7211 .Case("gr740", CK_LEON4_GR740) 7212 .Default(CK_GENERIC); 7213 } 7214 7215 bool setCPU(const std::string &Name) override { 7216 CPU = getCPUKind(Name); 7217 return CPU != CK_GENERIC; 7218 } 7219 }; 7220 7221 const char * const SparcTargetInfo::GCCRegNames[] = { 7222 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7223 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7224 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 7225 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 7226 }; 7227 7228 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 7229 return llvm::makeArrayRef(GCCRegNames); 7230 } 7231 7232 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 7233 { { "g0" }, "r0" }, 7234 { { "g1" }, "r1" }, 7235 { { "g2" }, "r2" }, 7236 { { "g3" }, "r3" }, 7237 { { "g4" }, "r4" }, 7238 { { "g5" }, "r5" }, 7239 { { "g6" }, "r6" }, 7240 { { "g7" }, "r7" }, 7241 { { "o0" }, "r8" }, 7242 { { "o1" }, "r9" }, 7243 { { "o2" }, "r10" }, 7244 { { "o3" }, "r11" }, 7245 { { "o4" }, "r12" }, 7246 { { "o5" }, "r13" }, 7247 { { "o6", "sp" }, "r14" }, 7248 { { "o7" }, "r15" }, 7249 { { "l0" }, "r16" }, 7250 { { "l1" }, "r17" }, 7251 { { "l2" }, "r18" }, 7252 { { "l3" }, "r19" }, 7253 { { "l4" }, "r20" }, 7254 { { "l5" }, "r21" }, 7255 { { "l6" }, "r22" }, 7256 { { "l7" }, "r23" }, 7257 { { "i0" }, "r24" }, 7258 { { "i1" }, "r25" }, 7259 { { "i2" }, "r26" }, 7260 { { "i3" }, "r27" }, 7261 { { "i4" }, "r28" }, 7262 { { "i5" }, "r29" }, 7263 { { "i6", "fp" }, "r30" }, 7264 { { "i7" }, "r31" }, 7265 }; 7266 7267 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 7268 return llvm::makeArrayRef(GCCRegAliases); 7269 } 7270 7271 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 7272 class SparcV8TargetInfo : public SparcTargetInfo { 7273 public: 7274 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7275 : SparcTargetInfo(Triple, Opts) { 7276 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7277 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 7278 switch (getTriple().getOS()) { 7279 default: 7280 SizeType = UnsignedInt; 7281 IntPtrType = SignedInt; 7282 PtrDiffType = SignedInt; 7283 break; 7284 case llvm::Triple::NetBSD: 7285 case llvm::Triple::OpenBSD: 7286 SizeType = UnsignedLong; 7287 IntPtrType = SignedLong; 7288 PtrDiffType = SignedLong; 7289 break; 7290 } 7291 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops 7292 // on up to 64 bits. 7293 MaxAtomicPromoteWidth = 64; 7294 MaxAtomicInlineWidth = 32; 7295 } 7296 7297 void getTargetDefines(const LangOptions &Opts, 7298 MacroBuilder &Builder) const override { 7299 SparcTargetInfo::getTargetDefines(Opts, Builder); 7300 switch (getCPUGeneration(CPU)) { 7301 case CG_V8: 7302 Builder.defineMacro("__sparcv8"); 7303 if (getTriple().getOS() != llvm::Triple::Solaris) 7304 Builder.defineMacro("__sparcv8__"); 7305 break; 7306 case CG_V9: 7307 Builder.defineMacro("__sparcv9"); 7308 if (getTriple().getOS() != llvm::Triple::Solaris) { 7309 Builder.defineMacro("__sparcv9__"); 7310 Builder.defineMacro("__sparc_v9__"); 7311 } 7312 break; 7313 } 7314 if (getTriple().getVendor() == llvm::Triple::Myriad) { 7315 std::string MyriadArchValue, Myriad2Value; 7316 Builder.defineMacro("__sparc_v8__"); 7317 Builder.defineMacro("__leon__"); 7318 switch (CPU) { 7319 case CK_MYRIAD2150: 7320 MyriadArchValue = "__ma2150"; 7321 Myriad2Value = "2"; 7322 break; 7323 case CK_MYRIAD2450: 7324 MyriadArchValue = "__ma2450"; 7325 Myriad2Value = "2"; 7326 break; 7327 default: 7328 MyriadArchValue = "__ma2100"; 7329 Myriad2Value = "1"; 7330 break; 7331 } 7332 Builder.defineMacro(MyriadArchValue, "1"); 7333 Builder.defineMacro(MyriadArchValue+"__", "1"); 7334 Builder.defineMacro("__myriad2__", Myriad2Value); 7335 Builder.defineMacro("__myriad2", Myriad2Value); 7336 } 7337 } 7338 7339 bool hasSjLjLowering() const override { 7340 return true; 7341 } 7342 }; 7343 7344 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 7345 class SparcV8elTargetInfo : public SparcV8TargetInfo { 7346 public: 7347 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7348 : SparcV8TargetInfo(Triple, Opts) { 7349 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7350 } 7351 }; 7352 7353 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 7354 class SparcV9TargetInfo : public SparcTargetInfo { 7355 public: 7356 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7357 : SparcTargetInfo(Triple, Opts) { 7358 // FIXME: Support Sparc quad-precision long double? 7359 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 7360 // This is an LP64 platform. 7361 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7362 7363 // OpenBSD uses long long for int64_t and intmax_t. 7364 if (getTriple().getOS() == llvm::Triple::OpenBSD) 7365 IntMaxType = SignedLongLong; 7366 else 7367 IntMaxType = SignedLong; 7368 Int64Type = IntMaxType; 7369 7370 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 7371 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 7372 LongDoubleWidth = 128; 7373 LongDoubleAlign = 128; 7374 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7375 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7376 } 7377 7378 void getTargetDefines(const LangOptions &Opts, 7379 MacroBuilder &Builder) const override { 7380 SparcTargetInfo::getTargetDefines(Opts, Builder); 7381 Builder.defineMacro("__sparcv9"); 7382 Builder.defineMacro("__arch64__"); 7383 // Solaris doesn't need these variants, but the BSDs do. 7384 if (getTriple().getOS() != llvm::Triple::Solaris) { 7385 Builder.defineMacro("__sparc64__"); 7386 Builder.defineMacro("__sparc_v9__"); 7387 Builder.defineMacro("__sparcv9__"); 7388 } 7389 } 7390 7391 bool setCPU(const std::string &Name) override { 7392 if (!SparcTargetInfo::setCPU(Name)) 7393 return false; 7394 return getCPUGeneration(CPU) == CG_V9; 7395 } 7396 }; 7397 7398 class SystemZTargetInfo : public TargetInfo { 7399 static const Builtin::Info BuiltinInfo[]; 7400 static const char *const GCCRegNames[]; 7401 std::string CPU; 7402 bool HasTransactionalExecution; 7403 bool HasVector; 7404 7405 public: 7406 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7407 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 7408 HasVector(false) { 7409 IntMaxType = SignedLong; 7410 Int64Type = SignedLong; 7411 TLSSupported = true; 7412 IntWidth = IntAlign = 32; 7413 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 7414 PointerWidth = PointerAlign = 64; 7415 LongDoubleWidth = 128; 7416 LongDoubleAlign = 64; 7417 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7418 DefaultAlignForAttributeAligned = 64; 7419 MinGlobalAlign = 16; 7420 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 7421 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7422 } 7423 void getTargetDefines(const LangOptions &Opts, 7424 MacroBuilder &Builder) const override { 7425 Builder.defineMacro("__s390__"); 7426 Builder.defineMacro("__s390x__"); 7427 Builder.defineMacro("__zarch__"); 7428 Builder.defineMacro("__LONG_DOUBLE_128__"); 7429 7430 const std::string ISARev = llvm::StringSwitch<std::string>(CPU) 7431 .Cases("arch8", "z10", "8") 7432 .Cases("arch9", "z196", "9") 7433 .Cases("arch10", "zEC12", "10") 7434 .Cases("arch11", "z13", "11") 7435 .Default(""); 7436 if (!ISARev.empty()) 7437 Builder.defineMacro("__ARCH__", ISARev); 7438 7439 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7440 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7441 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7442 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7443 7444 if (HasTransactionalExecution) 7445 Builder.defineMacro("__HTM__"); 7446 if (HasVector) 7447 Builder.defineMacro("__VX__"); 7448 if (Opts.ZVector) 7449 Builder.defineMacro("__VEC__", "10301"); 7450 } 7451 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7452 return llvm::makeArrayRef(BuiltinInfo, 7453 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 7454 } 7455 7456 ArrayRef<const char *> getGCCRegNames() const override; 7457 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7458 // No aliases. 7459 return None; 7460 } 7461 bool validateAsmConstraint(const char *&Name, 7462 TargetInfo::ConstraintInfo &info) const override; 7463 const char *getClobbers() const override { 7464 // FIXME: Is this really right? 7465 return ""; 7466 } 7467 BuiltinVaListKind getBuiltinVaListKind() const override { 7468 return TargetInfo::SystemZBuiltinVaList; 7469 } 7470 bool setCPU(const std::string &Name) override { 7471 CPU = Name; 7472 bool CPUKnown = llvm::StringSwitch<bool>(Name) 7473 .Case("z10", true) 7474 .Case("arch8", true) 7475 .Case("z196", true) 7476 .Case("arch9", true) 7477 .Case("zEC12", true) 7478 .Case("arch10", true) 7479 .Case("z13", true) 7480 .Case("arch11", true) 7481 .Default(false); 7482 7483 return CPUKnown; 7484 } 7485 bool 7486 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7487 StringRef CPU, 7488 const std::vector<std::string> &FeaturesVec) const override { 7489 if (CPU == "zEC12" || CPU == "arch10") 7490 Features["transactional-execution"] = true; 7491 if (CPU == "z13" || CPU == "arch11") { 7492 Features["transactional-execution"] = true; 7493 Features["vector"] = true; 7494 } 7495 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7496 } 7497 7498 bool handleTargetFeatures(std::vector<std::string> &Features, 7499 DiagnosticsEngine &Diags) override { 7500 HasTransactionalExecution = false; 7501 for (const auto &Feature : Features) { 7502 if (Feature == "+transactional-execution") 7503 HasTransactionalExecution = true; 7504 else if (Feature == "+vector") 7505 HasVector = true; 7506 } 7507 // If we use the vector ABI, vector types are 64-bit aligned. 7508 if (HasVector) { 7509 MaxVectorAlign = 64; 7510 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 7511 "-v128:64-a:8:16-n32:64"); 7512 } 7513 return true; 7514 } 7515 7516 bool hasFeature(StringRef Feature) const override { 7517 return llvm::StringSwitch<bool>(Feature) 7518 .Case("systemz", true) 7519 .Case("htm", HasTransactionalExecution) 7520 .Case("vx", HasVector) 7521 .Default(false); 7522 } 7523 7524 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7525 switch (CC) { 7526 case CC_C: 7527 case CC_Swift: 7528 case CC_OpenCLKernel: 7529 return CCCR_OK; 7530 default: 7531 return CCCR_Warning; 7532 } 7533 } 7534 7535 StringRef getABI() const override { 7536 if (HasVector) 7537 return "vector"; 7538 return ""; 7539 } 7540 7541 bool useFloat128ManglingForLongDouble() const override { 7542 return true; 7543 } 7544 }; 7545 7546 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 7547 #define BUILTIN(ID, TYPE, ATTRS) \ 7548 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7549 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7550 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 7551 #include "clang/Basic/BuiltinsSystemZ.def" 7552 }; 7553 7554 const char *const SystemZTargetInfo::GCCRegNames[] = { 7555 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7556 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7557 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 7558 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 7559 }; 7560 7561 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 7562 return llvm::makeArrayRef(GCCRegNames); 7563 } 7564 7565 bool SystemZTargetInfo:: 7566 validateAsmConstraint(const char *&Name, 7567 TargetInfo::ConstraintInfo &Info) const { 7568 switch (*Name) { 7569 default: 7570 return false; 7571 7572 case 'a': // Address register 7573 case 'd': // Data register (equivalent to 'r') 7574 case 'f': // Floating-point register 7575 Info.setAllowsRegister(); 7576 return true; 7577 7578 case 'I': // Unsigned 8-bit constant 7579 case 'J': // Unsigned 12-bit constant 7580 case 'K': // Signed 16-bit constant 7581 case 'L': // Signed 20-bit displacement (on all targets we support) 7582 case 'M': // 0x7fffffff 7583 return true; 7584 7585 case 'Q': // Memory with base and unsigned 12-bit displacement 7586 case 'R': // Likewise, plus an index 7587 case 'S': // Memory with base and signed 20-bit displacement 7588 case 'T': // Likewise, plus an index 7589 Info.setAllowsMemory(); 7590 return true; 7591 } 7592 } 7593 7594 class MSP430TargetInfo : public TargetInfo { 7595 static const char *const GCCRegNames[]; 7596 7597 public: 7598 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7599 : TargetInfo(Triple) { 7600 TLSSupported = false; 7601 IntWidth = 16; 7602 IntAlign = 16; 7603 LongWidth = 32; 7604 LongLongWidth = 64; 7605 LongAlign = LongLongAlign = 16; 7606 PointerWidth = 16; 7607 PointerAlign = 16; 7608 SuitableAlign = 16; 7609 SizeType = UnsignedInt; 7610 IntMaxType = SignedLongLong; 7611 IntPtrType = SignedInt; 7612 PtrDiffType = SignedInt; 7613 SigAtomicType = SignedLong; 7614 resetDataLayout("e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16"); 7615 } 7616 void getTargetDefines(const LangOptions &Opts, 7617 MacroBuilder &Builder) const override { 7618 Builder.defineMacro("MSP430"); 7619 Builder.defineMacro("__MSP430__"); 7620 // FIXME: defines for different 'flavours' of MCU 7621 } 7622 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7623 // FIXME: Implement. 7624 return None; 7625 } 7626 bool hasFeature(StringRef Feature) const override { 7627 return Feature == "msp430"; 7628 } 7629 ArrayRef<const char *> getGCCRegNames() const override; 7630 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7631 // No aliases. 7632 return None; 7633 } 7634 bool validateAsmConstraint(const char *&Name, 7635 TargetInfo::ConstraintInfo &info) const override { 7636 // FIXME: implement 7637 switch (*Name) { 7638 case 'K': // the constant 1 7639 case 'L': // constant -1^20 .. 1^19 7640 case 'M': // constant 1-4: 7641 return true; 7642 } 7643 // No target constraints for now. 7644 return false; 7645 } 7646 const char *getClobbers() const override { 7647 // FIXME: Is this really right? 7648 return ""; 7649 } 7650 BuiltinVaListKind getBuiltinVaListKind() const override { 7651 // FIXME: implement 7652 return TargetInfo::CharPtrBuiltinVaList; 7653 } 7654 }; 7655 7656 const char *const MSP430TargetInfo::GCCRegNames[] = { 7657 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7658 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7659 7660 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7661 return llvm::makeArrayRef(GCCRegNames); 7662 } 7663 7664 // LLVM and Clang cannot be used directly to output native binaries for 7665 // target, but is used to compile C code to llvm bitcode with correct 7666 // type and alignment information. 7667 // 7668 // TCE uses the llvm bitcode as input and uses it for generating customized 7669 // target processor and program binary. TCE co-design environment is 7670 // publicly available in http://tce.cs.tut.fi 7671 7672 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7673 0, // Default 7674 3, // opencl_global 7675 4, // opencl_local 7676 5, // opencl_constant 7677 // FIXME: generic has to be added to the target 7678 0, // opencl_generic 7679 0, // cuda_device 7680 0, // cuda_constant 7681 0 // cuda_shared 7682 }; 7683 7684 class TCETargetInfo : public TargetInfo { 7685 public: 7686 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7687 : TargetInfo(Triple) { 7688 TLSSupported = false; 7689 IntWidth = 32; 7690 LongWidth = LongLongWidth = 32; 7691 PointerWidth = 32; 7692 IntAlign = 32; 7693 LongAlign = LongLongAlign = 32; 7694 PointerAlign = 32; 7695 SuitableAlign = 32; 7696 SizeType = UnsignedInt; 7697 IntMaxType = SignedLong; 7698 IntPtrType = SignedInt; 7699 PtrDiffType = SignedInt; 7700 FloatWidth = 32; 7701 FloatAlign = 32; 7702 DoubleWidth = 32; 7703 DoubleAlign = 32; 7704 LongDoubleWidth = 32; 7705 LongDoubleAlign = 32; 7706 FloatFormat = &llvm::APFloat::IEEEsingle(); 7707 DoubleFormat = &llvm::APFloat::IEEEsingle(); 7708 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 7709 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-" 7710 "i16:16:32-i32:32:32-i64:32:32-" 7711 "f32:32:32-f64:32:32-v64:32:32-" 7712 "v128:32:32-v256:32:32-v512:32:32-" 7713 "v1024:32:32-a0:0:32-n32"); 7714 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7715 UseAddrSpaceMapMangling = true; 7716 } 7717 7718 void getTargetDefines(const LangOptions &Opts, 7719 MacroBuilder &Builder) const override { 7720 DefineStd(Builder, "tce", Opts); 7721 Builder.defineMacro("__TCE__"); 7722 Builder.defineMacro("__TCE_V1__"); 7723 } 7724 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7725 7726 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7727 const char *getClobbers() const override { return ""; } 7728 BuiltinVaListKind getBuiltinVaListKind() const override { 7729 return TargetInfo::VoidPtrBuiltinVaList; 7730 } 7731 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7732 bool validateAsmConstraint(const char *&Name, 7733 TargetInfo::ConstraintInfo &info) const override { 7734 return true; 7735 } 7736 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7737 return None; 7738 } 7739 }; 7740 7741 class TCELETargetInfo : public TCETargetInfo { 7742 public: 7743 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7744 : TCETargetInfo(Triple, Opts) { 7745 BigEndian = false; 7746 7747 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-" 7748 "i16:16:32-i32:32:32-i64:32:32-" 7749 "f32:32:32-f64:32:32-v64:32:32-" 7750 "v128:32:32-v256:32:32-v512:32:32-" 7751 "v1024:32:32-a0:0:32-n32"); 7752 7753 } 7754 7755 virtual void getTargetDefines(const LangOptions &Opts, 7756 MacroBuilder &Builder) const { 7757 DefineStd(Builder, "tcele", Opts); 7758 Builder.defineMacro("__TCE__"); 7759 Builder.defineMacro("__TCE_V1__"); 7760 Builder.defineMacro("__TCELE__"); 7761 Builder.defineMacro("__TCELE_V1__"); 7762 } 7763 7764 }; 7765 7766 class BPFTargetInfo : public TargetInfo { 7767 public: 7768 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7769 : TargetInfo(Triple) { 7770 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7771 SizeType = UnsignedLong; 7772 PtrDiffType = SignedLong; 7773 IntPtrType = SignedLong; 7774 IntMaxType = SignedLong; 7775 Int64Type = SignedLong; 7776 RegParmMax = 5; 7777 if (Triple.getArch() == llvm::Triple::bpfeb) { 7778 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7779 } else { 7780 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7781 } 7782 MaxAtomicPromoteWidth = 64; 7783 MaxAtomicInlineWidth = 64; 7784 TLSSupported = false; 7785 } 7786 void getTargetDefines(const LangOptions &Opts, 7787 MacroBuilder &Builder) const override { 7788 DefineStd(Builder, "bpf", Opts); 7789 Builder.defineMacro("__BPF__"); 7790 } 7791 bool hasFeature(StringRef Feature) const override { 7792 return Feature == "bpf"; 7793 } 7794 7795 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7796 const char *getClobbers() const override { 7797 return ""; 7798 } 7799 BuiltinVaListKind getBuiltinVaListKind() const override { 7800 return TargetInfo::VoidPtrBuiltinVaList; 7801 } 7802 ArrayRef<const char *> getGCCRegNames() const override { 7803 return None; 7804 } 7805 bool validateAsmConstraint(const char *&Name, 7806 TargetInfo::ConstraintInfo &info) const override { 7807 return true; 7808 } 7809 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7810 return None; 7811 } 7812 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7813 switch (CC) { 7814 default: 7815 return CCCR_Warning; 7816 case CC_C: 7817 case CC_OpenCLKernel: 7818 return CCCR_OK; 7819 } 7820 } 7821 }; 7822 7823 class Nios2TargetInfo : public TargetInfo { 7824 void setDataLayout() { 7825 if (BigEndian) 7826 resetDataLayout("E-p:32:32:32-i8:8:32-i16:16:32-n32"); 7827 else 7828 resetDataLayout("e-p:32:32:32-i8:8:32-i16:16:32-n32"); 7829 } 7830 7831 static const Builtin::Info BuiltinInfo[]; 7832 std::string CPU; 7833 std::string ABI; 7834 7835 public: 7836 Nios2TargetInfo(const llvm::Triple &triple, const TargetOptions &opts) 7837 : TargetInfo(triple), CPU(opts.CPU), ABI(opts.ABI) { 7838 SizeType = UnsignedInt; 7839 PtrDiffType = SignedInt; 7840 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7841 setDataLayout(); 7842 } 7843 7844 StringRef getABI() const override { return ABI; } 7845 bool setABI(const std::string &Name) override { 7846 if (Name == "o32" || Name == "eabi") { 7847 ABI = Name; 7848 return true; 7849 } 7850 return false; 7851 } 7852 7853 bool setCPU(const std::string &Name) override { 7854 if (Name == "nios2r1" || Name == "nios2r2") { 7855 CPU = Name; 7856 return true; 7857 } 7858 return false; 7859 } 7860 7861 void getTargetDefines(const LangOptions &Opts, 7862 MacroBuilder &Builder) const override { 7863 DefineStd(Builder, "nios2", Opts); 7864 DefineStd(Builder, "NIOS2", Opts); 7865 7866 Builder.defineMacro("__nios2"); 7867 Builder.defineMacro("__NIOS2"); 7868 Builder.defineMacro("__nios2__"); 7869 Builder.defineMacro("__NIOS2__"); 7870 } 7871 7872 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7873 return llvm::makeArrayRef(BuiltinInfo, clang::Nios2::LastTSBuiltin - 7874 Builtin::FirstTSBuiltin); 7875 } 7876 7877 bool isFeatureSupportedByCPU(StringRef Feature, StringRef CPU) const { 7878 const bool isR2 = CPU == "nios2r2"; 7879 return llvm::StringSwitch<bool>(Feature) 7880 .Case("nios2r2mandatory", isR2) 7881 .Case("nios2r2bmx", isR2) 7882 .Case("nios2r2mpx", isR2) 7883 .Case("nios2r2cdx", isR2) 7884 .Default(false); 7885 } 7886 7887 bool initFeatureMap(llvm::StringMap<bool> &Features, 7888 DiagnosticsEngine &Diags, StringRef CPU, 7889 const std::vector<std::string> &FeatureVec) const override { 7890 static const char *allFeatures[] = { 7891 "nios2r2mandatory", "nios2r2bmx", "nios2r2mpx", "nios2r2cdx" 7892 }; 7893 for (const char *feature : allFeatures) { 7894 Features[feature] = isFeatureSupportedByCPU(feature, CPU); 7895 } 7896 return true; 7897 } 7898 7899 bool hasFeature(StringRef Feature) const override { 7900 return isFeatureSupportedByCPU(Feature, CPU); 7901 } 7902 7903 BuiltinVaListKind getBuiltinVaListKind() const override { 7904 return TargetInfo::VoidPtrBuiltinVaList; 7905 } 7906 7907 ArrayRef<const char *> getGCCRegNames() const override { 7908 static const char *const GCCRegNames[] = { 7909 // CPU register names 7910 // Must match second column of GCCRegAliases 7911 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 7912 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", 7913 "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", 7914 "r31", 7915 // Floating point register names 7916 "ctl0", "ctl1", "ctl2", "ctl3", "ctl4", "ctl5", "ctl6", "ctl7", "ctl8", 7917 "ctl9", "ctl10", "ctl11", "ctl12", "ctl13", "ctl14", "ctl15" 7918 }; 7919 return llvm::makeArrayRef(GCCRegNames); 7920 } 7921 7922 bool validateAsmConstraint(const char *&Name, 7923 TargetInfo::ConstraintInfo &Info) const override { 7924 switch (*Name) { 7925 default: 7926 return false; 7927 7928 case 'r': // CPU registers. 7929 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7930 case 'y': // Equivalent to "r", backwards compatibility only. 7931 case 'f': // floating-point registers. 7932 case 'c': // $25 for indirect jumps 7933 case 'l': // lo register 7934 case 'x': // hilo register pair 7935 Info.setAllowsRegister(); 7936 return true; 7937 } 7938 } 7939 7940 const char *getClobbers() const override { return ""; } 7941 7942 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7943 static const TargetInfo::GCCRegAlias aliases[] = { 7944 {{"zero"}, "r0"}, {{"at"}, "r1"}, {{"et"}, "r24"}, 7945 {{"bt"}, "r25"}, {{"gp"}, "r26"}, {{"sp"}, "r27"}, 7946 {{"fp"}, "r28"}, {{"ea"}, "r29"}, {{"ba"}, "r30"}, 7947 {{"ra"}, "r31"}, {{"status"}, "ctl0"}, {{"estatus"}, "ctl1"}, 7948 {{"bstatus"}, "ctl2"}, {{"ienable"}, "ctl3"}, {{"ipending"}, "ctl4"}, 7949 {{"cpuid"}, "ctl5"}, {{"exception"}, "ctl7"}, {{"pteaddr"}, "ctl8"}, 7950 {{"tlbacc"}, "ctl9"}, {{"tlbmisc"}, "ctl10"}, {{"badaddr"}, "ctl12"}, 7951 {{"config"}, "ctl13"}, {{"mpubase"}, "ctl14"}, {{"mpuacc"}, "ctl15"}, 7952 }; 7953 return llvm::makeArrayRef(aliases); 7954 } 7955 }; 7956 7957 const Builtin::Info Nios2TargetInfo::BuiltinInfo[] = { 7958 #define BUILTIN(ID, TYPE, ATTRS) \ 7959 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 7960 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7961 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 7962 #include "clang/Basic/BuiltinsNios2.def" 7963 }; 7964 7965 class MipsTargetInfo : public TargetInfo { 7966 void setDataLayout() { 7967 StringRef Layout; 7968 7969 if (ABI == "o32") 7970 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7971 else if (ABI == "n32") 7972 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7973 else if (ABI == "n64") 7974 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7975 else 7976 llvm_unreachable("Invalid ABI"); 7977 7978 if (BigEndian) 7979 resetDataLayout(("E-" + Layout).str()); 7980 else 7981 resetDataLayout(("e-" + Layout).str()); 7982 } 7983 7984 7985 static const Builtin::Info BuiltinInfo[]; 7986 std::string CPU; 7987 bool IsMips16; 7988 bool IsMicromips; 7989 bool IsNan2008; 7990 bool IsSingleFloat; 7991 bool IsNoABICalls; 7992 bool CanUseBSDABICalls; 7993 enum MipsFloatABI { 7994 HardFloat, SoftFloat 7995 } FloatABI; 7996 enum DspRevEnum { 7997 NoDSP, DSP1, DSP2 7998 } DspRev; 7999 bool HasMSA; 8000 bool DisableMadd4; 8001 8002 protected: 8003 bool HasFP64; 8004 std::string ABI; 8005 8006 public: 8007 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8008 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 8009 IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false), 8010 CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP), 8011 HasMSA(false), DisableMadd4(false), HasFP64(false) { 8012 TheCXXABI.set(TargetCXXABI::GenericMIPS); 8013 8014 setABI((getTriple().getArch() == llvm::Triple::mips || 8015 getTriple().getArch() == llvm::Triple::mipsel) 8016 ? "o32" 8017 : "n64"); 8018 8019 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 8020 8021 CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD || 8022 Triple.getOS() == llvm::Triple::OpenBSD; 8023 } 8024 8025 bool isNaN2008Default() const { 8026 return CPU == "mips32r6" || CPU == "mips64r6"; 8027 } 8028 8029 bool isFP64Default() const { 8030 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 8031 } 8032 8033 bool isNan2008() const override { 8034 return IsNan2008; 8035 } 8036 8037 bool processorSupportsGPR64() const { 8038 return llvm::StringSwitch<bool>(CPU) 8039 .Case("mips3", true) 8040 .Case("mips4", true) 8041 .Case("mips5", true) 8042 .Case("mips64", true) 8043 .Case("mips64r2", true) 8044 .Case("mips64r3", true) 8045 .Case("mips64r5", true) 8046 .Case("mips64r6", true) 8047 .Case("octeon", true) 8048 .Default(false); 8049 return false; 8050 } 8051 8052 StringRef getABI() const override { return ABI; } 8053 bool setABI(const std::string &Name) override { 8054 if (Name == "o32") { 8055 setO32ABITypes(); 8056 ABI = Name; 8057 return true; 8058 } 8059 8060 if (Name == "n32") { 8061 setN32ABITypes(); 8062 ABI = Name; 8063 return true; 8064 } 8065 if (Name == "n64") { 8066 setN64ABITypes(); 8067 ABI = Name; 8068 return true; 8069 } 8070 return false; 8071 } 8072 8073 void setO32ABITypes() { 8074 Int64Type = SignedLongLong; 8075 IntMaxType = Int64Type; 8076 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8077 LongDoubleWidth = LongDoubleAlign = 64; 8078 LongWidth = LongAlign = 32; 8079 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 8080 PointerWidth = PointerAlign = 32; 8081 PtrDiffType = SignedInt; 8082 SizeType = UnsignedInt; 8083 SuitableAlign = 64; 8084 } 8085 8086 void setN32N64ABITypes() { 8087 LongDoubleWidth = LongDoubleAlign = 128; 8088 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8089 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 8090 LongDoubleWidth = LongDoubleAlign = 64; 8091 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8092 } 8093 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8094 SuitableAlign = 128; 8095 } 8096 8097 void setN64ABITypes() { 8098 setN32N64ABITypes(); 8099 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 8100 Int64Type = SignedLongLong; 8101 } else { 8102 Int64Type = SignedLong; 8103 } 8104 IntMaxType = Int64Type; 8105 LongWidth = LongAlign = 64; 8106 PointerWidth = PointerAlign = 64; 8107 PtrDiffType = SignedLong; 8108 SizeType = UnsignedLong; 8109 } 8110 8111 void setN32ABITypes() { 8112 setN32N64ABITypes(); 8113 Int64Type = SignedLongLong; 8114 IntMaxType = Int64Type; 8115 LongWidth = LongAlign = 32; 8116 PointerWidth = PointerAlign = 32; 8117 PtrDiffType = SignedInt; 8118 SizeType = UnsignedInt; 8119 } 8120 8121 bool setCPU(const std::string &Name) override { 8122 CPU = Name; 8123 return llvm::StringSwitch<bool>(Name) 8124 .Case("mips1", true) 8125 .Case("mips2", true) 8126 .Case("mips3", true) 8127 .Case("mips4", true) 8128 .Case("mips5", true) 8129 .Case("mips32", true) 8130 .Case("mips32r2", true) 8131 .Case("mips32r3", true) 8132 .Case("mips32r5", true) 8133 .Case("mips32r6", true) 8134 .Case("mips64", true) 8135 .Case("mips64r2", true) 8136 .Case("mips64r3", true) 8137 .Case("mips64r5", true) 8138 .Case("mips64r6", true) 8139 .Case("octeon", true) 8140 .Case("p5600", true) 8141 .Default(false); 8142 } 8143 const std::string& getCPU() const { return CPU; } 8144 bool 8145 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 8146 StringRef CPU, 8147 const std::vector<std::string> &FeaturesVec) const override { 8148 if (CPU.empty()) 8149 CPU = getCPU(); 8150 if (CPU == "octeon") 8151 Features["mips64r2"] = Features["cnmips"] = true; 8152 else 8153 Features[CPU] = true; 8154 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 8155 } 8156 8157 void getTargetDefines(const LangOptions &Opts, 8158 MacroBuilder &Builder) const override { 8159 if (BigEndian) { 8160 DefineStd(Builder, "MIPSEB", Opts); 8161 Builder.defineMacro("_MIPSEB"); 8162 } else { 8163 DefineStd(Builder, "MIPSEL", Opts); 8164 Builder.defineMacro("_MIPSEL"); 8165 } 8166 8167 Builder.defineMacro("__mips__"); 8168 Builder.defineMacro("_mips"); 8169 if (Opts.GNUMode) 8170 Builder.defineMacro("mips"); 8171 8172 if (ABI == "o32") { 8173 Builder.defineMacro("__mips", "32"); 8174 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 8175 } else { 8176 Builder.defineMacro("__mips", "64"); 8177 Builder.defineMacro("__mips64"); 8178 Builder.defineMacro("__mips64__"); 8179 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 8180 } 8181 8182 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 8183 .Cases("mips32", "mips64", "1") 8184 .Cases("mips32r2", "mips64r2", "2") 8185 .Cases("mips32r3", "mips64r3", "3") 8186 .Cases("mips32r5", "mips64r5", "5") 8187 .Cases("mips32r6", "mips64r6", "6") 8188 .Default(""); 8189 if (!ISARev.empty()) 8190 Builder.defineMacro("__mips_isa_rev", ISARev); 8191 8192 if (ABI == "o32") { 8193 Builder.defineMacro("__mips_o32"); 8194 Builder.defineMacro("_ABIO32", "1"); 8195 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 8196 } else if (ABI == "n32") { 8197 Builder.defineMacro("__mips_n32"); 8198 Builder.defineMacro("_ABIN32", "2"); 8199 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 8200 } else if (ABI == "n64") { 8201 Builder.defineMacro("__mips_n64"); 8202 Builder.defineMacro("_ABI64", "3"); 8203 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 8204 } else 8205 llvm_unreachable("Invalid ABI."); 8206 8207 if (!IsNoABICalls) { 8208 Builder.defineMacro("__mips_abicalls"); 8209 if (CanUseBSDABICalls) 8210 Builder.defineMacro("__ABICALLS__"); 8211 } 8212 8213 Builder.defineMacro("__REGISTER_PREFIX__", ""); 8214 8215 switch (FloatABI) { 8216 case HardFloat: 8217 Builder.defineMacro("__mips_hard_float", Twine(1)); 8218 break; 8219 case SoftFloat: 8220 Builder.defineMacro("__mips_soft_float", Twine(1)); 8221 break; 8222 } 8223 8224 if (IsSingleFloat) 8225 Builder.defineMacro("__mips_single_float", Twine(1)); 8226 8227 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 8228 Builder.defineMacro("_MIPS_FPSET", 8229 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 8230 8231 if (IsMips16) 8232 Builder.defineMacro("__mips16", Twine(1)); 8233 8234 if (IsMicromips) 8235 Builder.defineMacro("__mips_micromips", Twine(1)); 8236 8237 if (IsNan2008) 8238 Builder.defineMacro("__mips_nan2008", Twine(1)); 8239 8240 switch (DspRev) { 8241 default: 8242 break; 8243 case DSP1: 8244 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 8245 Builder.defineMacro("__mips_dsp", Twine(1)); 8246 break; 8247 case DSP2: 8248 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 8249 Builder.defineMacro("__mips_dspr2", Twine(1)); 8250 Builder.defineMacro("__mips_dsp", Twine(1)); 8251 break; 8252 } 8253 8254 if (HasMSA) 8255 Builder.defineMacro("__mips_msa", Twine(1)); 8256 8257 if (DisableMadd4) 8258 Builder.defineMacro("__mips_no_madd4", Twine(1)); 8259 8260 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 8261 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 8262 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 8263 8264 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 8265 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 8266 8267 // These shouldn't be defined for MIPS-I but there's no need to check 8268 // for that since MIPS-I isn't supported. 8269 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 8270 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 8271 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 8272 8273 // 32-bit MIPS processors don't have the necessary lld/scd instructions 8274 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 8275 // the instructions exist but using them violates the ABI since they 8276 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 8277 if (ABI == "n32" || ABI == "n64") 8278 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 8279 } 8280 8281 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8282 return llvm::makeArrayRef(BuiltinInfo, 8283 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 8284 } 8285 bool hasFeature(StringRef Feature) const override { 8286 return llvm::StringSwitch<bool>(Feature) 8287 .Case("mips", true) 8288 .Case("fp64", HasFP64) 8289 .Default(false); 8290 } 8291 BuiltinVaListKind getBuiltinVaListKind() const override { 8292 return TargetInfo::VoidPtrBuiltinVaList; 8293 } 8294 ArrayRef<const char *> getGCCRegNames() const override { 8295 static const char *const GCCRegNames[] = { 8296 // CPU register names 8297 // Must match second column of GCCRegAliases 8298 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 8299 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 8300 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 8301 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 8302 // Floating point register names 8303 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 8304 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 8305 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 8306 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 8307 // Hi/lo and condition register names 8308 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 8309 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 8310 "$ac3hi","$ac3lo", 8311 // MSA register names 8312 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 8313 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 8314 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 8315 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 8316 // MSA control register names 8317 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 8318 "$msarequest", "$msamap", "$msaunmap" 8319 }; 8320 return llvm::makeArrayRef(GCCRegNames); 8321 } 8322 bool validateAsmConstraint(const char *&Name, 8323 TargetInfo::ConstraintInfo &Info) const override { 8324 switch (*Name) { 8325 default: 8326 return false; 8327 case 'r': // CPU registers. 8328 case 'd': // Equivalent to "r" unless generating MIPS16 code. 8329 case 'y': // Equivalent to "r", backward compatibility only. 8330 case 'f': // floating-point registers. 8331 case 'c': // $25 for indirect jumps 8332 case 'l': // lo register 8333 case 'x': // hilo register pair 8334 Info.setAllowsRegister(); 8335 return true; 8336 case 'I': // Signed 16-bit constant 8337 case 'J': // Integer 0 8338 case 'K': // Unsigned 16-bit constant 8339 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 8340 case 'M': // Constants not loadable via lui, addiu, or ori 8341 case 'N': // Constant -1 to -65535 8342 case 'O': // A signed 15-bit constant 8343 case 'P': // A constant between 1 go 65535 8344 return true; 8345 case 'R': // An address that can be used in a non-macro load or store 8346 Info.setAllowsMemory(); 8347 return true; 8348 case 'Z': 8349 if (Name[1] == 'C') { // An address usable by ll, and sc. 8350 Info.setAllowsMemory(); 8351 Name++; // Skip over 'Z'. 8352 return true; 8353 } 8354 return false; 8355 } 8356 } 8357 8358 std::string convertConstraint(const char *&Constraint) const override { 8359 std::string R; 8360 switch (*Constraint) { 8361 case 'Z': // Two-character constraint; add "^" hint for later parsing. 8362 if (Constraint[1] == 'C') { 8363 R = std::string("^") + std::string(Constraint, 2); 8364 Constraint++; 8365 return R; 8366 } 8367 break; 8368 } 8369 return TargetInfo::convertConstraint(Constraint); 8370 } 8371 8372 const char *getClobbers() const override { 8373 // In GCC, $1 is not widely used in generated code (it's used only in a few 8374 // specific situations), so there is no real need for users to add it to 8375 // the clobbers list if they want to use it in their inline assembly code. 8376 // 8377 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 8378 // code generation, so using it in inline assembly without adding it to the 8379 // clobbers list can cause conflicts between the inline assembly code and 8380 // the surrounding generated code. 8381 // 8382 // Another problem is that LLVM is allowed to choose $1 for inline assembly 8383 // operands, which will conflict with the ".set at" assembler option (which 8384 // we use only for inline assembly, in order to maintain compatibility with 8385 // GCC) and will also conflict with the user's usage of $1. 8386 // 8387 // The easiest way to avoid these conflicts and keep $1 as an allocatable 8388 // register for generated code is to automatically clobber $1 for all inline 8389 // assembly code. 8390 // 8391 // FIXME: We should automatically clobber $1 only for inline assembly code 8392 // which actually uses it. This would allow LLVM to use $1 for inline 8393 // assembly operands if the user's assembly code doesn't use it. 8394 return "~{$1}"; 8395 } 8396 8397 bool handleTargetFeatures(std::vector<std::string> &Features, 8398 DiagnosticsEngine &Diags) override { 8399 IsMips16 = false; 8400 IsMicromips = false; 8401 IsNan2008 = isNaN2008Default(); 8402 IsSingleFloat = false; 8403 FloatABI = HardFloat; 8404 DspRev = NoDSP; 8405 HasFP64 = isFP64Default(); 8406 8407 for (const auto &Feature : Features) { 8408 if (Feature == "+single-float") 8409 IsSingleFloat = true; 8410 else if (Feature == "+soft-float") 8411 FloatABI = SoftFloat; 8412 else if (Feature == "+mips16") 8413 IsMips16 = true; 8414 else if (Feature == "+micromips") 8415 IsMicromips = true; 8416 else if (Feature == "+dsp") 8417 DspRev = std::max(DspRev, DSP1); 8418 else if (Feature == "+dspr2") 8419 DspRev = std::max(DspRev, DSP2); 8420 else if (Feature == "+msa") 8421 HasMSA = true; 8422 else if (Feature == "+nomadd4") 8423 DisableMadd4 = true; 8424 else if (Feature == "+fp64") 8425 HasFP64 = true; 8426 else if (Feature == "-fp64") 8427 HasFP64 = false; 8428 else if (Feature == "+nan2008") 8429 IsNan2008 = true; 8430 else if (Feature == "-nan2008") 8431 IsNan2008 = false; 8432 else if (Feature == "+noabicalls") 8433 IsNoABICalls = true; 8434 } 8435 8436 setDataLayout(); 8437 8438 return true; 8439 } 8440 8441 int getEHDataRegisterNumber(unsigned RegNo) const override { 8442 if (RegNo == 0) return 4; 8443 if (RegNo == 1) return 5; 8444 return -1; 8445 } 8446 8447 bool isCLZForZeroUndef() const override { return false; } 8448 8449 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8450 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 8451 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8452 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8453 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 8454 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 8455 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 8456 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8457 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8458 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8459 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8460 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8461 {{"ra"}, "$31"}}; 8462 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 8463 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8464 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8465 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 8466 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 8467 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 8468 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8469 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8470 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8471 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8472 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8473 {{"ra"}, "$31"}}; 8474 if (ABI == "o32") 8475 return llvm::makeArrayRef(O32RegAliases); 8476 return llvm::makeArrayRef(NewABIRegAliases); 8477 } 8478 8479 bool hasInt128Type() const override { 8480 return ABI == "n32" || ABI == "n64"; 8481 } 8482 8483 bool validateTarget(DiagnosticsEngine &Diags) const override { 8484 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 8485 // this yet. It's better to fail here than on the backend assertion. 8486 if (processorSupportsGPR64() && ABI == "o32") { 8487 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8488 return false; 8489 } 8490 8491 // 64-bit ABI's require 64-bit CPU's. 8492 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 8493 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8494 return false; 8495 } 8496 8497 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 8498 // can't handle this yet. It's better to fail here than on the 8499 // backend assertion. 8500 if ((getTriple().getArch() == llvm::Triple::mips64 || 8501 getTriple().getArch() == llvm::Triple::mips64el) && 8502 ABI == "o32") { 8503 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8504 << ABI << getTriple().str(); 8505 return false; 8506 } 8507 8508 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 8509 // can't handle this yet. It's better to fail here than on the 8510 // backend assertion. 8511 if ((getTriple().getArch() == llvm::Triple::mips || 8512 getTriple().getArch() == llvm::Triple::mipsel) && 8513 (ABI == "n32" || ABI == "n64")) { 8514 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8515 << ABI << getTriple().str(); 8516 return false; 8517 } 8518 8519 return true; 8520 } 8521 }; 8522 8523 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 8524 #define BUILTIN(ID, TYPE, ATTRS) \ 8525 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8526 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8527 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8528 #include "clang/Basic/BuiltinsMips.def" 8529 }; 8530 8531 class PNaClTargetInfo : public TargetInfo { 8532 public: 8533 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8534 : TargetInfo(Triple) { 8535 this->LongAlign = 32; 8536 this->LongWidth = 32; 8537 this->PointerAlign = 32; 8538 this->PointerWidth = 32; 8539 this->IntMaxType = TargetInfo::SignedLongLong; 8540 this->Int64Type = TargetInfo::SignedLongLong; 8541 this->DoubleAlign = 64; 8542 this->LongDoubleWidth = 64; 8543 this->LongDoubleAlign = 64; 8544 this->SizeType = TargetInfo::UnsignedInt; 8545 this->PtrDiffType = TargetInfo::SignedInt; 8546 this->IntPtrType = TargetInfo::SignedInt; 8547 this->RegParmMax = 0; // Disallow regparm 8548 } 8549 8550 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 8551 Builder.defineMacro("__le32__"); 8552 Builder.defineMacro("__pnacl__"); 8553 } 8554 void getTargetDefines(const LangOptions &Opts, 8555 MacroBuilder &Builder) const override { 8556 getArchDefines(Opts, Builder); 8557 } 8558 bool hasFeature(StringRef Feature) const override { 8559 return Feature == "pnacl"; 8560 } 8561 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8562 BuiltinVaListKind getBuiltinVaListKind() const override { 8563 return TargetInfo::PNaClABIBuiltinVaList; 8564 } 8565 ArrayRef<const char *> getGCCRegNames() const override; 8566 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 8567 bool validateAsmConstraint(const char *&Name, 8568 TargetInfo::ConstraintInfo &Info) const override { 8569 return false; 8570 } 8571 8572 const char *getClobbers() const override { 8573 return ""; 8574 } 8575 }; 8576 8577 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 8578 return None; 8579 } 8580 8581 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 8582 return None; 8583 } 8584 8585 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 8586 class NaClMips32TargetInfo : public MipsTargetInfo { 8587 public: 8588 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8589 : MipsTargetInfo(Triple, Opts) {} 8590 8591 BuiltinVaListKind getBuiltinVaListKind() const override { 8592 return TargetInfo::PNaClABIBuiltinVaList; 8593 } 8594 }; 8595 8596 class Le64TargetInfo : public TargetInfo { 8597 static const Builtin::Info BuiltinInfo[]; 8598 8599 public: 8600 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8601 : TargetInfo(Triple) { 8602 NoAsmVariants = true; 8603 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 8604 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8605 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 8606 } 8607 8608 void getTargetDefines(const LangOptions &Opts, 8609 MacroBuilder &Builder) const override { 8610 DefineStd(Builder, "unix", Opts); 8611 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 8612 Builder.defineMacro("__ELF__"); 8613 } 8614 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8615 return llvm::makeArrayRef(BuiltinInfo, 8616 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 8617 } 8618 BuiltinVaListKind getBuiltinVaListKind() const override { 8619 return TargetInfo::PNaClABIBuiltinVaList; 8620 } 8621 const char *getClobbers() const override { return ""; } 8622 ArrayRef<const char *> getGCCRegNames() const override { 8623 return None; 8624 } 8625 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8626 return None; 8627 } 8628 bool validateAsmConstraint(const char *&Name, 8629 TargetInfo::ConstraintInfo &Info) const override { 8630 return false; 8631 } 8632 8633 bool hasProtectedVisibility() const override { return false; } 8634 }; 8635 8636 class WebAssemblyTargetInfo : public TargetInfo { 8637 static const Builtin::Info BuiltinInfo[]; 8638 8639 enum SIMDEnum { 8640 NoSIMD, 8641 SIMD128, 8642 } SIMDLevel; 8643 8644 public: 8645 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 8646 : TargetInfo(T), SIMDLevel(NoSIMD) { 8647 NoAsmVariants = true; 8648 SuitableAlign = 128; 8649 LargeArrayMinWidth = 128; 8650 LargeArrayAlign = 128; 8651 SimdDefaultAlign = 128; 8652 SigAtomicType = SignedLong; 8653 LongDoubleWidth = LongDoubleAlign = 128; 8654 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8655 SizeType = UnsignedInt; 8656 PtrDiffType = SignedInt; 8657 IntPtrType = SignedInt; 8658 } 8659 8660 protected: 8661 void getTargetDefines(const LangOptions &Opts, 8662 MacroBuilder &Builder) const override { 8663 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 8664 if (SIMDLevel >= SIMD128) 8665 Builder.defineMacro("__wasm_simd128__"); 8666 } 8667 8668 private: 8669 bool 8670 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 8671 StringRef CPU, 8672 const std::vector<std::string> &FeaturesVec) const override { 8673 if (CPU == "bleeding-edge") 8674 Features["simd128"] = true; 8675 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 8676 } 8677 bool hasFeature(StringRef Feature) const final { 8678 return llvm::StringSwitch<bool>(Feature) 8679 .Case("simd128", SIMDLevel >= SIMD128) 8680 .Default(false); 8681 } 8682 bool handleTargetFeatures(std::vector<std::string> &Features, 8683 DiagnosticsEngine &Diags) final { 8684 for (const auto &Feature : Features) { 8685 if (Feature == "+simd128") { 8686 SIMDLevel = std::max(SIMDLevel, SIMD128); 8687 continue; 8688 } 8689 if (Feature == "-simd128") { 8690 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 8691 continue; 8692 } 8693 8694 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 8695 << "-target-feature"; 8696 return false; 8697 } 8698 return true; 8699 } 8700 bool setCPU(const std::string &Name) final { 8701 return llvm::StringSwitch<bool>(Name) 8702 .Case("mvp", true) 8703 .Case("bleeding-edge", true) 8704 .Case("generic", true) 8705 .Default(false); 8706 } 8707 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 8708 return llvm::makeArrayRef(BuiltinInfo, 8709 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 8710 } 8711 BuiltinVaListKind getBuiltinVaListKind() const final { 8712 return VoidPtrBuiltinVaList; 8713 } 8714 ArrayRef<const char *> getGCCRegNames() const final { 8715 return None; 8716 } 8717 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 8718 return None; 8719 } 8720 bool 8721 validateAsmConstraint(const char *&Name, 8722 TargetInfo::ConstraintInfo &Info) const final { 8723 return false; 8724 } 8725 const char *getClobbers() const final { return ""; } 8726 bool isCLZForZeroUndef() const final { return false; } 8727 bool hasInt128Type() const final { return true; } 8728 IntType getIntTypeByWidth(unsigned BitWidth, 8729 bool IsSigned) const final { 8730 // WebAssembly prefers long long for explicitly 64-bit integers. 8731 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8732 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8733 } 8734 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8735 bool IsSigned) const final { 8736 // WebAssembly uses long long for int_least64_t and int_fast64_t. 8737 return BitWidth == 64 8738 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8739 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 8740 } 8741 }; 8742 8743 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 8744 #define BUILTIN(ID, TYPE, ATTRS) \ 8745 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8746 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8747 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8748 #include "clang/Basic/BuiltinsWebAssembly.def" 8749 }; 8750 8751 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 8752 public: 8753 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 8754 const TargetOptions &Opts) 8755 : WebAssemblyTargetInfo(T, Opts) { 8756 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8757 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 8758 } 8759 8760 protected: 8761 void getTargetDefines(const LangOptions &Opts, 8762 MacroBuilder &Builder) const override { 8763 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8764 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 8765 } 8766 }; 8767 8768 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 8769 public: 8770 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 8771 const TargetOptions &Opts) 8772 : WebAssemblyTargetInfo(T, Opts) { 8773 LongAlign = LongWidth = 64; 8774 PointerAlign = PointerWidth = 64; 8775 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8776 SizeType = UnsignedLong; 8777 PtrDiffType = SignedLong; 8778 IntPtrType = SignedLong; 8779 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 8780 } 8781 8782 protected: 8783 void getTargetDefines(const LangOptions &Opts, 8784 MacroBuilder &Builder) const override { 8785 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8786 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 8787 } 8788 }; 8789 8790 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 8791 #define BUILTIN(ID, TYPE, ATTRS) \ 8792 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8793 #include "clang/Basic/BuiltinsLe64.def" 8794 }; 8795 8796 static const unsigned SPIRAddrSpaceMap[] = { 8797 0, // Default 8798 1, // opencl_global 8799 3, // opencl_local 8800 2, // opencl_constant 8801 4, // opencl_generic 8802 0, // cuda_device 8803 0, // cuda_constant 8804 0 // cuda_shared 8805 }; 8806 class SPIRTargetInfo : public TargetInfo { 8807 public: 8808 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8809 : TargetInfo(Triple) { 8810 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 8811 "SPIR target must use unknown OS"); 8812 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 8813 "SPIR target must use unknown environment type"); 8814 TLSSupported = false; 8815 LongWidth = LongAlign = 64; 8816 AddrSpaceMap = &SPIRAddrSpaceMap; 8817 UseAddrSpaceMapMangling = true; 8818 // Define available target features 8819 // These must be defined in sorted order! 8820 NoAsmVariants = true; 8821 } 8822 void getTargetDefines(const LangOptions &Opts, 8823 MacroBuilder &Builder) const override { 8824 DefineStd(Builder, "SPIR", Opts); 8825 } 8826 bool hasFeature(StringRef Feature) const override { 8827 return Feature == "spir"; 8828 } 8829 8830 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8831 const char *getClobbers() const override { return ""; } 8832 ArrayRef<const char *> getGCCRegNames() const override { return None; } 8833 bool validateAsmConstraint(const char *&Name, 8834 TargetInfo::ConstraintInfo &info) const override { 8835 return true; 8836 } 8837 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8838 return None; 8839 } 8840 BuiltinVaListKind getBuiltinVaListKind() const override { 8841 return TargetInfo::VoidPtrBuiltinVaList; 8842 } 8843 8844 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 8845 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 8846 : CCCR_Warning; 8847 } 8848 8849 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8850 return CC_SpirFunction; 8851 } 8852 8853 void setSupportedOpenCLOpts() override { 8854 // Assume all OpenCL extensions and optional core features are supported 8855 // for SPIR since it is a generic target. 8856 getSupportedOpenCLOpts().supportAll(); 8857 } 8858 }; 8859 8860 class SPIR32TargetInfo : public SPIRTargetInfo { 8861 public: 8862 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8863 : SPIRTargetInfo(Triple, Opts) { 8864 PointerWidth = PointerAlign = 32; 8865 SizeType = TargetInfo::UnsignedInt; 8866 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8867 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8868 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8869 } 8870 void getTargetDefines(const LangOptions &Opts, 8871 MacroBuilder &Builder) const override { 8872 DefineStd(Builder, "SPIR32", Opts); 8873 } 8874 }; 8875 8876 class SPIR64TargetInfo : public SPIRTargetInfo { 8877 public: 8878 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8879 : SPIRTargetInfo(Triple, Opts) { 8880 PointerWidth = PointerAlign = 64; 8881 SizeType = TargetInfo::UnsignedLong; 8882 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8883 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8884 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8885 } 8886 void getTargetDefines(const LangOptions &Opts, 8887 MacroBuilder &Builder) const override { 8888 DefineStd(Builder, "SPIR64", Opts); 8889 } 8890 }; 8891 8892 class XCoreTargetInfo : public TargetInfo { 8893 static const Builtin::Info BuiltinInfo[]; 8894 public: 8895 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8896 : TargetInfo(Triple) { 8897 NoAsmVariants = true; 8898 LongLongAlign = 32; 8899 SuitableAlign = 32; 8900 DoubleAlign = LongDoubleAlign = 32; 8901 SizeType = UnsignedInt; 8902 PtrDiffType = SignedInt; 8903 IntPtrType = SignedInt; 8904 WCharType = UnsignedChar; 8905 WIntType = UnsignedInt; 8906 UseZeroLengthBitfieldAlignment = true; 8907 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8908 "-f64:32-a:0:32-n32"); 8909 } 8910 void getTargetDefines(const LangOptions &Opts, 8911 MacroBuilder &Builder) const override { 8912 Builder.defineMacro("__XS1B__"); 8913 } 8914 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8915 return llvm::makeArrayRef(BuiltinInfo, 8916 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8917 } 8918 BuiltinVaListKind getBuiltinVaListKind() const override { 8919 return TargetInfo::VoidPtrBuiltinVaList; 8920 } 8921 const char *getClobbers() const override { 8922 return ""; 8923 } 8924 ArrayRef<const char *> getGCCRegNames() const override { 8925 static const char * const GCCRegNames[] = { 8926 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8927 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8928 }; 8929 return llvm::makeArrayRef(GCCRegNames); 8930 } 8931 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8932 return None; 8933 } 8934 bool validateAsmConstraint(const char *&Name, 8935 TargetInfo::ConstraintInfo &Info) const override { 8936 return false; 8937 } 8938 int getEHDataRegisterNumber(unsigned RegNo) const override { 8939 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8940 return (RegNo < 2)? RegNo : -1; 8941 } 8942 bool allowsLargerPreferedTypeAlignment() const override { 8943 return false; 8944 } 8945 }; 8946 8947 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8948 #define BUILTIN(ID, TYPE, ATTRS) \ 8949 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8950 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8951 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8952 #include "clang/Basic/BuiltinsXCore.def" 8953 }; 8954 8955 // x86_32 Android target 8956 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8957 public: 8958 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8959 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8960 SuitableAlign = 32; 8961 LongDoubleWidth = 64; 8962 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8963 } 8964 }; 8965 8966 // x86_64 Android target 8967 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8968 public: 8969 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8970 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8971 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8972 } 8973 8974 bool useFloat128ManglingForLongDouble() const override { 8975 return true; 8976 } 8977 }; 8978 8979 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8980 class RenderScript32TargetInfo : public ARMleTargetInfo { 8981 public: 8982 RenderScript32TargetInfo(const llvm::Triple &Triple, 8983 const TargetOptions &Opts) 8984 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8985 Triple.getOSName(), 8986 Triple.getEnvironmentName()), 8987 Opts) { 8988 IsRenderScriptTarget = true; 8989 LongWidth = LongAlign = 64; 8990 } 8991 void getTargetDefines(const LangOptions &Opts, 8992 MacroBuilder &Builder) const override { 8993 Builder.defineMacro("__RENDERSCRIPT__"); 8994 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8995 } 8996 }; 8997 8998 // 64-bit RenderScript is aarch64 8999 class RenderScript64TargetInfo : public AArch64leTargetInfo { 9000 public: 9001 RenderScript64TargetInfo(const llvm::Triple &Triple, 9002 const TargetOptions &Opts) 9003 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 9004 Triple.getOSName(), 9005 Triple.getEnvironmentName()), 9006 Opts) { 9007 IsRenderScriptTarget = true; 9008 } 9009 9010 void getTargetDefines(const LangOptions &Opts, 9011 MacroBuilder &Builder) const override { 9012 Builder.defineMacro("__RENDERSCRIPT__"); 9013 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 9014 } 9015 }; 9016 9017 /// Information about a specific microcontroller. 9018 struct MCUInfo { 9019 const char *Name; 9020 const char *DefineName; 9021 }; 9022 9023 // This list should be kept up-to-date with AVRDevices.td in LLVM. 9024 static ArrayRef<MCUInfo> AVRMcus = { 9025 { "at90s1200", "__AVR_AT90S1200__" }, 9026 { "attiny11", "__AVR_ATtiny11__" }, 9027 { "attiny12", "__AVR_ATtiny12__" }, 9028 { "attiny15", "__AVR_ATtiny15__" }, 9029 { "attiny28", "__AVR_ATtiny28__" }, 9030 { "at90s2313", "__AVR_AT90S2313__" }, 9031 { "at90s2323", "__AVR_AT90S2323__" }, 9032 { "at90s2333", "__AVR_AT90S2333__" }, 9033 { "at90s2343", "__AVR_AT90S2343__" }, 9034 { "attiny22", "__AVR_ATtiny22__" }, 9035 { "attiny26", "__AVR_ATtiny26__" }, 9036 { "at86rf401", "__AVR_AT86RF401__" }, 9037 { "at90s4414", "__AVR_AT90S4414__" }, 9038 { "at90s4433", "__AVR_AT90S4433__" }, 9039 { "at90s4434", "__AVR_AT90S4434__" }, 9040 { "at90s8515", "__AVR_AT90S8515__" }, 9041 { "at90c8534", "__AVR_AT90c8534__" }, 9042 { "at90s8535", "__AVR_AT90S8535__" }, 9043 { "ata5272", "__AVR_ATA5272__" }, 9044 { "attiny13", "__AVR_ATtiny13__" }, 9045 { "attiny13a", "__AVR_ATtiny13A__" }, 9046 { "attiny2313", "__AVR_ATtiny2313__" }, 9047 { "attiny2313a", "__AVR_ATtiny2313A__" }, 9048 { "attiny24", "__AVR_ATtiny24__" }, 9049 { "attiny24a", "__AVR_ATtiny24A__" }, 9050 { "attiny4313", "__AVR_ATtiny4313__" }, 9051 { "attiny44", "__AVR_ATtiny44__" }, 9052 { "attiny44a", "__AVR_ATtiny44A__" }, 9053 { "attiny84", "__AVR_ATtiny84__" }, 9054 { "attiny84a", "__AVR_ATtiny84A__" }, 9055 { "attiny25", "__AVR_ATtiny25__" }, 9056 { "attiny45", "__AVR_ATtiny45__" }, 9057 { "attiny85", "__AVR_ATtiny85__" }, 9058 { "attiny261", "__AVR_ATtiny261__" }, 9059 { "attiny261a", "__AVR_ATtiny261A__" }, 9060 { "attiny461", "__AVR_ATtiny461__" }, 9061 { "attiny461a", "__AVR_ATtiny461A__" }, 9062 { "attiny861", "__AVR_ATtiny861__" }, 9063 { "attiny861a", "__AVR_ATtiny861A__" }, 9064 { "attiny87", "__AVR_ATtiny87__" }, 9065 { "attiny43u", "__AVR_ATtiny43U__" }, 9066 { "attiny48", "__AVR_ATtiny48__" }, 9067 { "attiny88", "__AVR_ATtiny88__" }, 9068 { "attiny828", "__AVR_ATtiny828__" }, 9069 { "at43usb355", "__AVR_AT43USB355__" }, 9070 { "at76c711", "__AVR_AT76C711__" }, 9071 { "atmega103", "__AVR_ATmega103__" }, 9072 { "at43usb320", "__AVR_AT43USB320__" }, 9073 { "attiny167", "__AVR_ATtiny167__" }, 9074 { "at90usb82", "__AVR_AT90USB82__" }, 9075 { "at90usb162", "__AVR_AT90USB162__" }, 9076 { "ata5505", "__AVR_ATA5505__" }, 9077 { "atmega8u2", "__AVR_ATmega8U2__" }, 9078 { "atmega16u2", "__AVR_ATmega16U2__" }, 9079 { "atmega32u2", "__AVR_ATmega32U2__" }, 9080 { "attiny1634", "__AVR_ATtiny1634__" }, 9081 { "atmega8", "__AVR_ATmega8__" }, 9082 { "ata6289", "__AVR_ATA6289__" }, 9083 { "atmega8a", "__AVR_ATmega8A__" }, 9084 { "ata6285", "__AVR_ATA6285__" }, 9085 { "ata6286", "__AVR_ATA6286__" }, 9086 { "atmega48", "__AVR_ATmega48__" }, 9087 { "atmega48a", "__AVR_ATmega48A__" }, 9088 { "atmega48pa", "__AVR_ATmega48PA__" }, 9089 { "atmega48p", "__AVR_ATmega48P__" }, 9090 { "atmega88", "__AVR_ATmega88__" }, 9091 { "atmega88a", "__AVR_ATmega88A__" }, 9092 { "atmega88p", "__AVR_ATmega88P__" }, 9093 { "atmega88pa", "__AVR_ATmega88PA__" }, 9094 { "atmega8515", "__AVR_ATmega8515__" }, 9095 { "atmega8535", "__AVR_ATmega8535__" }, 9096 { "atmega8hva", "__AVR_ATmega8HVA__" }, 9097 { "at90pwm1", "__AVR_AT90PWM1__" }, 9098 { "at90pwm2", "__AVR_AT90PWM2__" }, 9099 { "at90pwm2b", "__AVR_AT90PWM2B__" }, 9100 { "at90pwm3", "__AVR_AT90PWM3__" }, 9101 { "at90pwm3b", "__AVR_AT90PWM3B__" }, 9102 { "at90pwm81", "__AVR_AT90PWM81__" }, 9103 { "ata5790", "__AVR_ATA5790__" }, 9104 { "ata5795", "__AVR_ATA5795__" }, 9105 { "atmega16", "__AVR_ATmega16__" }, 9106 { "atmega16a", "__AVR_ATmega16A__" }, 9107 { "atmega161", "__AVR_ATmega161__" }, 9108 { "atmega162", "__AVR_ATmega162__" }, 9109 { "atmega163", "__AVR_ATmega163__" }, 9110 { "atmega164a", "__AVR_ATmega164A__" }, 9111 { "atmega164p", "__AVR_ATmega164P__" }, 9112 { "atmega164pa", "__AVR_ATmega164PA__" }, 9113 { "atmega165", "__AVR_ATmega165__" }, 9114 { "atmega165a", "__AVR_ATmega165A__" }, 9115 { "atmega165p", "__AVR_ATmega165P__" }, 9116 { "atmega165pa", "__AVR_ATmega165PA__" }, 9117 { "atmega168", "__AVR_ATmega168__" }, 9118 { "atmega168a", "__AVR_ATmega168A__" }, 9119 { "atmega168p", "__AVR_ATmega168P__" }, 9120 { "atmega168pa", "__AVR_ATmega168PA__" }, 9121 { "atmega169", "__AVR_ATmega169__" }, 9122 { "atmega169a", "__AVR_ATmega169A__" }, 9123 { "atmega169p", "__AVR_ATmega169P__" }, 9124 { "atmega169pa", "__AVR_ATmega169PA__" }, 9125 { "atmega32", "__AVR_ATmega32__" }, 9126 { "atmega32a", "__AVR_ATmega32A__" }, 9127 { "atmega323", "__AVR_ATmega323__" }, 9128 { "atmega324a", "__AVR_ATmega324A__" }, 9129 { "atmega324p", "__AVR_ATmega324P__" }, 9130 { "atmega324pa", "__AVR_ATmega324PA__" }, 9131 { "atmega325", "__AVR_ATmega325__" }, 9132 { "atmega325a", "__AVR_ATmega325A__" }, 9133 { "atmega325p", "__AVR_ATmega325P__" }, 9134 { "atmega325pa", "__AVR_ATmega325PA__" }, 9135 { "atmega3250", "__AVR_ATmega3250__" }, 9136 { "atmega3250a", "__AVR_ATmega3250A__" }, 9137 { "atmega3250p", "__AVR_ATmega3250P__" }, 9138 { "atmega3250pa", "__AVR_ATmega3250PA__" }, 9139 { "atmega328", "__AVR_ATmega328__" }, 9140 { "atmega328p", "__AVR_ATmega328P__" }, 9141 { "atmega329", "__AVR_ATmega329__" }, 9142 { "atmega329a", "__AVR_ATmega329A__" }, 9143 { "atmega329p", "__AVR_ATmega329P__" }, 9144 { "atmega329pa", "__AVR_ATmega329PA__" }, 9145 { "atmega3290", "__AVR_ATmega3290__" }, 9146 { "atmega3290a", "__AVR_ATmega3290A__" }, 9147 { "atmega3290p", "__AVR_ATmega3290P__" }, 9148 { "atmega3290pa", "__AVR_ATmega3290PA__" }, 9149 { "atmega406", "__AVR_ATmega406__" }, 9150 { "atmega64", "__AVR_ATmega64__" }, 9151 { "atmega64a", "__AVR_ATmega64A__" }, 9152 { "atmega640", "__AVR_ATmega640__" }, 9153 { "atmega644", "__AVR_ATmega644__" }, 9154 { "atmega644a", "__AVR_ATmega644A__" }, 9155 { "atmega644p", "__AVR_ATmega644P__" }, 9156 { "atmega644pa", "__AVR_ATmega644PA__" }, 9157 { "atmega645", "__AVR_ATmega645__" }, 9158 { "atmega645a", "__AVR_ATmega645A__" }, 9159 { "atmega645p", "__AVR_ATmega645P__" }, 9160 { "atmega649", "__AVR_ATmega649__" }, 9161 { "atmega649a", "__AVR_ATmega649A__" }, 9162 { "atmega649p", "__AVR_ATmega649P__" }, 9163 { "atmega6450", "__AVR_ATmega6450__" }, 9164 { "atmega6450a", "__AVR_ATmega6450A__" }, 9165 { "atmega6450p", "__AVR_ATmega6450P__" }, 9166 { "atmega6490", "__AVR_ATmega6490__" }, 9167 { "atmega6490a", "__AVR_ATmega6490A__" }, 9168 { "atmega6490p", "__AVR_ATmega6490P__" }, 9169 { "atmega64rfr2", "__AVR_ATmega64RFR2__" }, 9170 { "atmega644rfr2", "__AVR_ATmega644RFR2__" }, 9171 { "atmega16hva", "__AVR_ATmega16HVA__" }, 9172 { "atmega16hva2", "__AVR_ATmega16HVA2__" }, 9173 { "atmega16hvb", "__AVR_ATmega16HVB__" }, 9174 { "atmega16hvbrevb", "__AVR_ATmega16HVBREVB__" }, 9175 { "atmega32hvb", "__AVR_ATmega32HVB__" }, 9176 { "atmega32hvbrevb", "__AVR_ATmega32HVBREVB__" }, 9177 { "atmega64hve", "__AVR_ATmega64HVE__" }, 9178 { "at90can32", "__AVR_AT90CAN32__" }, 9179 { "at90can64", "__AVR_AT90CAN64__" }, 9180 { "at90pwm161", "__AVR_AT90PWM161__" }, 9181 { "at90pwm216", "__AVR_AT90PWM216__" }, 9182 { "at90pwm316", "__AVR_AT90PWM316__" }, 9183 { "atmega32c1", "__AVR_ATmega32C1__" }, 9184 { "atmega64c1", "__AVR_ATmega64C1__" }, 9185 { "atmega16m1", "__AVR_ATmega16M1__" }, 9186 { "atmega32m1", "__AVR_ATmega32M1__" }, 9187 { "atmega64m1", "__AVR_ATmega64M1__" }, 9188 { "atmega16u4", "__AVR_ATmega16U4__" }, 9189 { "atmega32u4", "__AVR_ATmega32U4__" }, 9190 { "atmega32u6", "__AVR_ATmega32U6__" }, 9191 { "at90usb646", "__AVR_AT90USB646__" }, 9192 { "at90usb647", "__AVR_AT90USB647__" }, 9193 { "at90scr100", "__AVR_AT90SCR100__" }, 9194 { "at94k", "__AVR_AT94K__" }, 9195 { "m3000", "__AVR_AT000__" }, 9196 { "atmega128", "__AVR_ATmega128__" }, 9197 { "atmega128a", "__AVR_ATmega128A__" }, 9198 { "atmega1280", "__AVR_ATmega1280__" }, 9199 { "atmega1281", "__AVR_ATmega1281__" }, 9200 { "atmega1284", "__AVR_ATmega1284__" }, 9201 { "atmega1284p", "__AVR_ATmega1284P__" }, 9202 { "atmega128rfa1", "__AVR_ATmega128RFA1__" }, 9203 { "atmega128rfr2", "__AVR_ATmega128RFR2__" }, 9204 { "atmega1284rfr2", "__AVR_ATmega1284RFR2__" }, 9205 { "at90can128", "__AVR_AT90CAN128__" }, 9206 { "at90usb1286", "__AVR_AT90USB1286__" }, 9207 { "at90usb1287", "__AVR_AT90USB1287__" }, 9208 { "atmega2560", "__AVR_ATmega2560__" }, 9209 { "atmega2561", "__AVR_ATmega2561__" }, 9210 { "atmega256rfr2", "__AVR_ATmega256RFR2__" }, 9211 { "atmega2564rfr2", "__AVR_ATmega2564RFR2__" }, 9212 { "atxmega16a4", "__AVR_ATxmega16A4__" }, 9213 { "atxmega16a4u", "__AVR_ATxmega16a4U__" }, 9214 { "atxmega16c4", "__AVR_ATxmega16C4__" }, 9215 { "atxmega16d4", "__AVR_ATxmega16D4__" }, 9216 { "atxmega32a4", "__AVR_ATxmega32A4__" }, 9217 { "atxmega32a4u", "__AVR_ATxmega32A4U__" }, 9218 { "atxmega32c4", "__AVR_ATxmega32C4__" }, 9219 { "atxmega32d4", "__AVR_ATxmega32D4__" }, 9220 { "atxmega32e5", "__AVR_ATxmega32E5__" }, 9221 { "atxmega16e5", "__AVR_ATxmega16E5__" }, 9222 { "atxmega8e5", "__AVR_ATxmega8E5__" }, 9223 { "atxmega32x1", "__AVR_ATxmega32X1__" }, 9224 { "atxmega64a3", "__AVR_ATxmega64A3__" }, 9225 { "atxmega64a3u", "__AVR_ATxmega64A3U__" }, 9226 { "atxmega64a4u", "__AVR_ATxmega64A4U__" }, 9227 { "atxmega64b1", "__AVR_ATxmega64B1__" }, 9228 { "atxmega64b3", "__AVR_ATxmega64B3__" }, 9229 { "atxmega64c3", "__AVR_ATxmega64C3__" }, 9230 { "atxmega64d3", "__AVR_ATxmega64D3__" }, 9231 { "atxmega64d4", "__AVR_ATxmega64D4__" }, 9232 { "atxmega64a1", "__AVR_ATxmega64A1__" }, 9233 { "atxmega64a1u", "__AVR_ATxmega64A1U__" }, 9234 { "atxmega128a3", "__AVR_ATxmega128A3__" }, 9235 { "atxmega128a3u", "__AVR_ATxmega128A3U__" }, 9236 { "atxmega128b1", "__AVR_ATxmega128B1__" }, 9237 { "atxmega128b3", "__AVR_ATxmega128B3__" }, 9238 { "atxmega128c3", "__AVR_ATxmega128C3__" }, 9239 { "atxmega128d3", "__AVR_ATxmega128D3__" }, 9240 { "atxmega128d4", "__AVR_ATxmega128D4__" }, 9241 { "atxmega192a3", "__AVR_ATxmega192A3__" }, 9242 { "atxmega192a3u", "__AVR_ATxmega192A3U__" }, 9243 { "atxmega192c3", "__AVR_ATxmega192C3__" }, 9244 { "atxmega192d3", "__AVR_ATxmega192D3__" }, 9245 { "atxmega256a3", "__AVR_ATxmega256A3__" }, 9246 { "atxmega256a3u", "__AVR_ATxmega256A3U__" }, 9247 { "atxmega256a3b", "__AVR_ATxmega256A3B__" }, 9248 { "atxmega256a3bu", "__AVR_ATxmega256A3BU__" }, 9249 { "atxmega256c3", "__AVR_ATxmega256C3__" }, 9250 { "atxmega256d3", "__AVR_ATxmega256D3__" }, 9251 { "atxmega384c3", "__AVR_ATxmega384C3__" }, 9252 { "atxmega384d3", "__AVR_ATxmega384D3__" }, 9253 { "atxmega128a1", "__AVR_ATxmega128A1__" }, 9254 { "atxmega128a1u", "__AVR_ATxmega128A1U__" }, 9255 { "atxmega128a4u", "__AVR_ATxmega128a4U__" }, 9256 { "attiny4", "__AVR_ATtiny4__" }, 9257 { "attiny5", "__AVR_ATtiny5__" }, 9258 { "attiny9", "__AVR_ATtiny9__" }, 9259 { "attiny10", "__AVR_ATtiny10__" }, 9260 { "attiny20", "__AVR_ATtiny20__" }, 9261 { "attiny40", "__AVR_ATtiny40__" }, 9262 { "attiny102", "__AVR_ATtiny102__" }, 9263 { "attiny104", "__AVR_ATtiny104__" }, 9264 }; 9265 9266 // AVR Target 9267 class AVRTargetInfo : public TargetInfo { 9268 public: 9269 AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 9270 : TargetInfo(Triple) { 9271 TLSSupported = false; 9272 PointerWidth = 16; 9273 PointerAlign = 8; 9274 IntWidth = 16; 9275 IntAlign = 8; 9276 LongWidth = 32; 9277 LongAlign = 8; 9278 LongLongWidth = 64; 9279 LongLongAlign = 8; 9280 SuitableAlign = 8; 9281 DefaultAlignForAttributeAligned = 8; 9282 HalfWidth = 16; 9283 HalfAlign = 8; 9284 FloatWidth = 32; 9285 FloatAlign = 8; 9286 DoubleWidth = 32; 9287 DoubleAlign = 8; 9288 DoubleFormat = &llvm::APFloat::IEEEsingle(); 9289 LongDoubleWidth = 32; 9290 LongDoubleAlign = 8; 9291 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 9292 SizeType = UnsignedInt; 9293 PtrDiffType = SignedInt; 9294 IntPtrType = SignedInt; 9295 Char16Type = UnsignedInt; 9296 WCharType = SignedInt; 9297 WIntType = SignedInt; 9298 Char32Type = UnsignedLong; 9299 SigAtomicType = SignedChar; 9300 resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64" 9301 "-f32:32:32-f64:64:64-n8"); 9302 } 9303 9304 void getTargetDefines(const LangOptions &Opts, 9305 MacroBuilder &Builder) const override { 9306 Builder.defineMacro("AVR"); 9307 Builder.defineMacro("__AVR"); 9308 Builder.defineMacro("__AVR__"); 9309 9310 if (!this->CPU.empty()) { 9311 auto It = std::find_if(AVRMcus.begin(), AVRMcus.end(), 9312 [&](const MCUInfo &Info) { return Info.Name == this->CPU; }); 9313 9314 if (It != AVRMcus.end()) 9315 Builder.defineMacro(It->DefineName); 9316 } 9317 } 9318 9319 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 9320 return None; 9321 } 9322 9323 BuiltinVaListKind getBuiltinVaListKind() const override { 9324 return TargetInfo::VoidPtrBuiltinVaList; 9325 } 9326 9327 const char *getClobbers() const override { 9328 return ""; 9329 } 9330 9331 ArrayRef<const char *> getGCCRegNames() const override { 9332 static const char * const GCCRegNames[] = { 9333 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 9334 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 9335 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 9336 "r24", "r25", "X", "Y", "Z", "SP" 9337 }; 9338 return llvm::makeArrayRef(GCCRegNames); 9339 } 9340 9341 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 9342 return None; 9343 } 9344 9345 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 9346 static const TargetInfo::AddlRegName AddlRegNames[] = { 9347 { { "r26", "r27"}, 26 }, 9348 { { "r28", "r29"}, 27 }, 9349 { { "r30", "r31"}, 28 }, 9350 { { "SPL", "SPH"}, 29 }, 9351 }; 9352 return llvm::makeArrayRef(AddlRegNames); 9353 } 9354 9355 bool validateAsmConstraint(const char *&Name, 9356 TargetInfo::ConstraintInfo &Info) const override { 9357 // There aren't any multi-character AVR specific constraints. 9358 if (StringRef(Name).size() > 1) return false; 9359 9360 switch (*Name) { 9361 default: return false; 9362 case 'a': // Simple upper registers 9363 case 'b': // Base pointer registers pairs 9364 case 'd': // Upper register 9365 case 'l': // Lower registers 9366 case 'e': // Pointer register pairs 9367 case 'q': // Stack pointer register 9368 case 'r': // Any register 9369 case 'w': // Special upper register pairs 9370 case 't': // Temporary register 9371 case 'x': case 'X': // Pointer register pair X 9372 case 'y': case 'Y': // Pointer register pair Y 9373 case 'z': case 'Z': // Pointer register pair Z 9374 Info.setAllowsRegister(); 9375 return true; 9376 case 'I': // 6-bit positive integer constant 9377 Info.setRequiresImmediate(0, 63); 9378 return true; 9379 case 'J': // 6-bit negative integer constant 9380 Info.setRequiresImmediate(-63, 0); 9381 return true; 9382 case 'K': // Integer constant (Range: 2) 9383 Info.setRequiresImmediate(2); 9384 return true; 9385 case 'L': // Integer constant (Range: 0) 9386 Info.setRequiresImmediate(0); 9387 return true; 9388 case 'M': // 8-bit integer constant 9389 Info.setRequiresImmediate(0, 0xff); 9390 return true; 9391 case 'N': // Integer constant (Range: -1) 9392 Info.setRequiresImmediate(-1); 9393 return true; 9394 case 'O': // Integer constant (Range: 8, 16, 24) 9395 Info.setRequiresImmediate({8, 16, 24}); 9396 return true; 9397 case 'P': // Integer constant (Range: 1) 9398 Info.setRequiresImmediate(1); 9399 return true; 9400 case 'R': // Integer constant (Range: -6 to 5) 9401 Info.setRequiresImmediate(-6, 5); 9402 return true; 9403 case 'G': // Floating point constant 9404 case 'Q': // A memory address based on Y or Z pointer with displacement. 9405 return true; 9406 } 9407 9408 return false; 9409 } 9410 9411 IntType getIntTypeByWidth(unsigned BitWidth, 9412 bool IsSigned) const final { 9413 // AVR prefers int for 16-bit integers. 9414 return BitWidth == 16 ? (IsSigned ? SignedInt : UnsignedInt) 9415 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 9416 } 9417 9418 IntType getLeastIntTypeByWidth(unsigned BitWidth, 9419 bool IsSigned) const final { 9420 // AVR uses int for int_least16_t and int_fast16_t. 9421 return BitWidth == 16 9422 ? (IsSigned ? SignedInt : UnsignedInt) 9423 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 9424 } 9425 9426 bool setCPU(const std::string &Name) override { 9427 bool IsFamily = llvm::StringSwitch<bool>(Name) 9428 .Case("avr1", true) 9429 .Case("avr2", true) 9430 .Case("avr25", true) 9431 .Case("avr3", true) 9432 .Case("avr31", true) 9433 .Case("avr35", true) 9434 .Case("avr4", true) 9435 .Case("avr5", true) 9436 .Case("avr51", true) 9437 .Case("avr6", true) 9438 .Case("avrxmega1", true) 9439 .Case("avrxmega2", true) 9440 .Case("avrxmega3", true) 9441 .Case("avrxmega4", true) 9442 .Case("avrxmega5", true) 9443 .Case("avrxmega6", true) 9444 .Case("avrxmega7", true) 9445 .Case("avrtiny", true) 9446 .Default(false); 9447 9448 if (IsFamily) this->CPU = Name; 9449 9450 bool IsMCU = std::find_if(AVRMcus.begin(), AVRMcus.end(), 9451 [&](const MCUInfo &Info) { return Info.Name == Name; }) != AVRMcus.end(); 9452 9453 if (IsMCU) this->CPU = Name; 9454 9455 return IsFamily || IsMCU; 9456 } 9457 9458 protected: 9459 std::string CPU; 9460 }; 9461 9462 } // end anonymous namespace 9463 9464 //===----------------------------------------------------------------------===// 9465 // Driver code 9466 //===----------------------------------------------------------------------===// 9467 9468 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 9469 const TargetOptions &Opts) { 9470 llvm::Triple::OSType os = Triple.getOS(); 9471 9472 switch (Triple.getArch()) { 9473 default: 9474 return nullptr; 9475 9476 case llvm::Triple::xcore: 9477 return new XCoreTargetInfo(Triple, Opts); 9478 9479 case llvm::Triple::hexagon: 9480 return new HexagonTargetInfo(Triple, Opts); 9481 9482 case llvm::Triple::lanai: 9483 return new LanaiTargetInfo(Triple, Opts); 9484 9485 case llvm::Triple::aarch64: 9486 if (Triple.isOSDarwin()) 9487 return new DarwinAArch64TargetInfo(Triple, Opts); 9488 9489 switch (os) { 9490 case llvm::Triple::CloudABI: 9491 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 9492 case llvm::Triple::FreeBSD: 9493 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9494 case llvm::Triple::Fuchsia: 9495 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9496 case llvm::Triple::Linux: 9497 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9498 case llvm::Triple::NetBSD: 9499 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9500 case llvm::Triple::OpenBSD: 9501 return new OpenBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9502 case llvm::Triple::Win32: 9503 return new MicrosoftARM64TargetInfo(Triple, Opts); 9504 default: 9505 return new AArch64leTargetInfo(Triple, Opts); 9506 } 9507 9508 case llvm::Triple::aarch64_be: 9509 switch (os) { 9510 case llvm::Triple::FreeBSD: 9511 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9512 case llvm::Triple::Fuchsia: 9513 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9514 case llvm::Triple::Linux: 9515 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9516 case llvm::Triple::NetBSD: 9517 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9518 default: 9519 return new AArch64beTargetInfo(Triple, Opts); 9520 } 9521 9522 case llvm::Triple::arm: 9523 case llvm::Triple::thumb: 9524 if (Triple.isOSBinFormatMachO()) 9525 return new DarwinARMTargetInfo(Triple, Opts); 9526 9527 switch (os) { 9528 case llvm::Triple::CloudABI: 9529 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts); 9530 case llvm::Triple::Linux: 9531 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 9532 case llvm::Triple::FreeBSD: 9533 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9534 case llvm::Triple::NetBSD: 9535 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9536 case llvm::Triple::OpenBSD: 9537 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9538 case llvm::Triple::Bitrig: 9539 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 9540 case llvm::Triple::RTEMS: 9541 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 9542 case llvm::Triple::NaCl: 9543 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 9544 case llvm::Triple::Win32: 9545 switch (Triple.getEnvironment()) { 9546 case llvm::Triple::Cygnus: 9547 return new CygwinARMTargetInfo(Triple, Opts); 9548 case llvm::Triple::GNU: 9549 return new MinGWARMTargetInfo(Triple, Opts); 9550 case llvm::Triple::Itanium: 9551 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 9552 case llvm::Triple::MSVC: 9553 default: // Assume MSVC for unknown environments 9554 return new MicrosoftARMleTargetInfo(Triple, Opts); 9555 } 9556 default: 9557 return new ARMleTargetInfo(Triple, Opts); 9558 } 9559 9560 case llvm::Triple::armeb: 9561 case llvm::Triple::thumbeb: 9562 if (Triple.isOSDarwin()) 9563 return new DarwinARMTargetInfo(Triple, Opts); 9564 9565 switch (os) { 9566 case llvm::Triple::Linux: 9567 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9568 case llvm::Triple::FreeBSD: 9569 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9570 case llvm::Triple::NetBSD: 9571 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9572 case llvm::Triple::OpenBSD: 9573 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9574 case llvm::Triple::Bitrig: 9575 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9576 case llvm::Triple::RTEMS: 9577 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9578 case llvm::Triple::NaCl: 9579 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9580 default: 9581 return new ARMbeTargetInfo(Triple, Opts); 9582 } 9583 9584 case llvm::Triple::avr: 9585 return new AVRTargetInfo(Triple, Opts); 9586 case llvm::Triple::bpfeb: 9587 case llvm::Triple::bpfel: 9588 return new BPFTargetInfo(Triple, Opts); 9589 9590 case llvm::Triple::msp430: 9591 return new MSP430TargetInfo(Triple, Opts); 9592 9593 case llvm::Triple::nios2: 9594 return new LinuxTargetInfo<Nios2TargetInfo>(Triple, Opts); 9595 9596 case llvm::Triple::mips: 9597 switch (os) { 9598 case llvm::Triple::Linux: 9599 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9600 case llvm::Triple::RTEMS: 9601 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9602 case llvm::Triple::FreeBSD: 9603 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9604 case llvm::Triple::NetBSD: 9605 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9606 default: 9607 return new MipsTargetInfo(Triple, Opts); 9608 } 9609 9610 case llvm::Triple::mipsel: 9611 switch (os) { 9612 case llvm::Triple::Linux: 9613 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9614 case llvm::Triple::RTEMS: 9615 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9616 case llvm::Triple::FreeBSD: 9617 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9618 case llvm::Triple::NetBSD: 9619 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9620 case llvm::Triple::NaCl: 9621 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 9622 default: 9623 return new MipsTargetInfo(Triple, Opts); 9624 } 9625 9626 case llvm::Triple::mips64: 9627 switch (os) { 9628 case llvm::Triple::Linux: 9629 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9630 case llvm::Triple::RTEMS: 9631 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9632 case llvm::Triple::FreeBSD: 9633 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9634 case llvm::Triple::NetBSD: 9635 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9636 case llvm::Triple::OpenBSD: 9637 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9638 default: 9639 return new MipsTargetInfo(Triple, Opts); 9640 } 9641 9642 case llvm::Triple::mips64el: 9643 switch (os) { 9644 case llvm::Triple::Linux: 9645 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9646 case llvm::Triple::RTEMS: 9647 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9648 case llvm::Triple::FreeBSD: 9649 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9650 case llvm::Triple::NetBSD: 9651 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9652 case llvm::Triple::OpenBSD: 9653 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9654 default: 9655 return new MipsTargetInfo(Triple, Opts); 9656 } 9657 9658 case llvm::Triple::le32: 9659 switch (os) { 9660 case llvm::Triple::NaCl: 9661 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 9662 default: 9663 return nullptr; 9664 } 9665 9666 case llvm::Triple::le64: 9667 return new Le64TargetInfo(Triple, Opts); 9668 9669 case llvm::Triple::ppc: 9670 if (Triple.isOSDarwin()) 9671 return new DarwinPPC32TargetInfo(Triple, Opts); 9672 switch (os) { 9673 case llvm::Triple::Linux: 9674 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 9675 case llvm::Triple::FreeBSD: 9676 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9677 case llvm::Triple::NetBSD: 9678 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9679 case llvm::Triple::OpenBSD: 9680 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9681 case llvm::Triple::RTEMS: 9682 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 9683 default: 9684 return new PPC32TargetInfo(Triple, Opts); 9685 } 9686 9687 case llvm::Triple::ppc64: 9688 if (Triple.isOSDarwin()) 9689 return new DarwinPPC64TargetInfo(Triple, Opts); 9690 switch (os) { 9691 case llvm::Triple::Linux: 9692 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9693 case llvm::Triple::Lv2: 9694 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 9695 case llvm::Triple::FreeBSD: 9696 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9697 case llvm::Triple::NetBSD: 9698 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9699 default: 9700 return new PPC64TargetInfo(Triple, Opts); 9701 } 9702 9703 case llvm::Triple::ppc64le: 9704 switch (os) { 9705 case llvm::Triple::Linux: 9706 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9707 case llvm::Triple::NetBSD: 9708 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9709 default: 9710 return new PPC64TargetInfo(Triple, Opts); 9711 } 9712 9713 case llvm::Triple::nvptx: 9714 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/32); 9715 case llvm::Triple::nvptx64: 9716 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64); 9717 9718 case llvm::Triple::amdgcn: 9719 case llvm::Triple::r600: 9720 return new AMDGPUTargetInfo(Triple, Opts); 9721 9722 case llvm::Triple::sparc: 9723 switch (os) { 9724 case llvm::Triple::Linux: 9725 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9726 case llvm::Triple::Solaris: 9727 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9728 case llvm::Triple::NetBSD: 9729 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9730 case llvm::Triple::OpenBSD: 9731 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9732 case llvm::Triple::RTEMS: 9733 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9734 default: 9735 return new SparcV8TargetInfo(Triple, Opts); 9736 } 9737 9738 // The 'sparcel' architecture copies all the above cases except for Solaris. 9739 case llvm::Triple::sparcel: 9740 switch (os) { 9741 case llvm::Triple::Linux: 9742 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9743 case llvm::Triple::NetBSD: 9744 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9745 case llvm::Triple::OpenBSD: 9746 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9747 case llvm::Triple::RTEMS: 9748 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9749 default: 9750 return new SparcV8elTargetInfo(Triple, Opts); 9751 } 9752 9753 case llvm::Triple::sparcv9: 9754 switch (os) { 9755 case llvm::Triple::Linux: 9756 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9757 case llvm::Triple::Solaris: 9758 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9759 case llvm::Triple::NetBSD: 9760 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9761 case llvm::Triple::OpenBSD: 9762 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9763 case llvm::Triple::FreeBSD: 9764 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9765 default: 9766 return new SparcV9TargetInfo(Triple, Opts); 9767 } 9768 9769 case llvm::Triple::systemz: 9770 switch (os) { 9771 case llvm::Triple::Linux: 9772 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 9773 default: 9774 return new SystemZTargetInfo(Triple, Opts); 9775 } 9776 9777 case llvm::Triple::tce: 9778 return new TCETargetInfo(Triple, Opts); 9779 9780 case llvm::Triple::tcele: 9781 return new TCELETargetInfo(Triple, Opts); 9782 9783 case llvm::Triple::x86: 9784 if (Triple.isOSDarwin()) 9785 return new DarwinI386TargetInfo(Triple, Opts); 9786 9787 switch (os) { 9788 case llvm::Triple::Ananas: 9789 return new AnanasTargetInfo<X86_32TargetInfo>(Triple, Opts); 9790 case llvm::Triple::CloudABI: 9791 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 9792 case llvm::Triple::Linux: { 9793 switch (Triple.getEnvironment()) { 9794 default: 9795 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 9796 case llvm::Triple::Android: 9797 return new AndroidX86_32TargetInfo(Triple, Opts); 9798 } 9799 } 9800 case llvm::Triple::DragonFly: 9801 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9802 case llvm::Triple::NetBSD: 9803 return new NetBSDI386TargetInfo(Triple, Opts); 9804 case llvm::Triple::OpenBSD: 9805 return new OpenBSDI386TargetInfo(Triple, Opts); 9806 case llvm::Triple::Bitrig: 9807 return new BitrigI386TargetInfo(Triple, Opts); 9808 case llvm::Triple::FreeBSD: 9809 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9810 case llvm::Triple::KFreeBSD: 9811 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9812 case llvm::Triple::Minix: 9813 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 9814 case llvm::Triple::Solaris: 9815 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 9816 case llvm::Triple::Win32: { 9817 switch (Triple.getEnvironment()) { 9818 case llvm::Triple::Cygnus: 9819 return new CygwinX86_32TargetInfo(Triple, Opts); 9820 case llvm::Triple::GNU: 9821 return new MinGWX86_32TargetInfo(Triple, Opts); 9822 case llvm::Triple::Itanium: 9823 case llvm::Triple::MSVC: 9824 default: // Assume MSVC for unknown environments 9825 return new MicrosoftX86_32TargetInfo(Triple, Opts); 9826 } 9827 } 9828 case llvm::Triple::Haiku: 9829 return new HaikuX86_32TargetInfo(Triple, Opts); 9830 case llvm::Triple::RTEMS: 9831 return new RTEMSX86_32TargetInfo(Triple, Opts); 9832 case llvm::Triple::NaCl: 9833 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 9834 case llvm::Triple::ELFIAMCU: 9835 return new MCUX86_32TargetInfo(Triple, Opts); 9836 default: 9837 return new X86_32TargetInfo(Triple, Opts); 9838 } 9839 9840 case llvm::Triple::x86_64: 9841 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 9842 return new DarwinX86_64TargetInfo(Triple, Opts); 9843 9844 switch (os) { 9845 case llvm::Triple::Ananas: 9846 return new AnanasTargetInfo<X86_64TargetInfo>(Triple, Opts); 9847 case llvm::Triple::CloudABI: 9848 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 9849 case llvm::Triple::Linux: { 9850 switch (Triple.getEnvironment()) { 9851 default: 9852 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 9853 case llvm::Triple::Android: 9854 return new AndroidX86_64TargetInfo(Triple, Opts); 9855 } 9856 } 9857 case llvm::Triple::DragonFly: 9858 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9859 case llvm::Triple::NetBSD: 9860 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9861 case llvm::Triple::OpenBSD: 9862 return new OpenBSDX86_64TargetInfo(Triple, Opts); 9863 case llvm::Triple::Bitrig: 9864 return new BitrigX86_64TargetInfo(Triple, Opts); 9865 case llvm::Triple::FreeBSD: 9866 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9867 case llvm::Triple::Fuchsia: 9868 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts); 9869 case llvm::Triple::KFreeBSD: 9870 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9871 case llvm::Triple::Solaris: 9872 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 9873 case llvm::Triple::Win32: { 9874 switch (Triple.getEnvironment()) { 9875 case llvm::Triple::Cygnus: 9876 return new CygwinX86_64TargetInfo(Triple, Opts); 9877 case llvm::Triple::GNU: 9878 return new MinGWX86_64TargetInfo(Triple, Opts); 9879 case llvm::Triple::MSVC: 9880 default: // Assume MSVC for unknown environments 9881 return new MicrosoftX86_64TargetInfo(Triple, Opts); 9882 } 9883 } 9884 case llvm::Triple::Haiku: 9885 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 9886 case llvm::Triple::NaCl: 9887 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 9888 case llvm::Triple::PS4: 9889 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 9890 default: 9891 return new X86_64TargetInfo(Triple, Opts); 9892 } 9893 9894 case llvm::Triple::spir: { 9895 if (Triple.getOS() != llvm::Triple::UnknownOS || 9896 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9897 return nullptr; 9898 return new SPIR32TargetInfo(Triple, Opts); 9899 } 9900 case llvm::Triple::spir64: { 9901 if (Triple.getOS() != llvm::Triple::UnknownOS || 9902 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9903 return nullptr; 9904 return new SPIR64TargetInfo(Triple, Opts); 9905 } 9906 case llvm::Triple::wasm32: 9907 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9908 Triple.getVendor() != llvm::Triple::UnknownVendor || 9909 Triple.getOS() != llvm::Triple::UnknownOS || 9910 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9911 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9912 return nullptr; 9913 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 9914 case llvm::Triple::wasm64: 9915 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9916 Triple.getVendor() != llvm::Triple::UnknownVendor || 9917 Triple.getOS() != llvm::Triple::UnknownOS || 9918 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9919 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9920 return nullptr; 9921 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 9922 9923 case llvm::Triple::renderscript32: 9924 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 9925 case llvm::Triple::renderscript64: 9926 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 9927 } 9928 } 9929 9930 /// CreateTargetInfo - Return the target info object for the specified target 9931 /// options. 9932 TargetInfo * 9933 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 9934 const std::shared_ptr<TargetOptions> &Opts) { 9935 llvm::Triple Triple(Opts->Triple); 9936 9937 // Construct the target 9938 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 9939 if (!Target) { 9940 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 9941 return nullptr; 9942 } 9943 Target->TargetOpts = Opts; 9944 9945 // Set the target CPU if specified. 9946 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 9947 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 9948 return nullptr; 9949 } 9950 9951 // Set the target ABI if specified. 9952 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 9953 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 9954 return nullptr; 9955 } 9956 9957 // Set the fp math unit. 9958 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 9959 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 9960 return nullptr; 9961 } 9962 9963 // Compute the default target features, we need the target to handle this 9964 // because features may have dependencies on one another. 9965 llvm::StringMap<bool> Features; 9966 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 9967 Opts->FeaturesAsWritten)) 9968 return nullptr; 9969 9970 // Add the features to the compile options. 9971 Opts->Features.clear(); 9972 for (const auto &F : Features) 9973 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 9974 9975 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 9976 return nullptr; 9977 9978 Target->setSupportedOpenCLOpts(); 9979 Target->setOpenCLExtensionOpts(); 9980 9981 if (!Target->validateTarget(Diags)) 9982 return nullptr; 9983 9984 return Target.release(); 9985 } 9986