1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "clang/Basic/Version.h" 23 #include "llvm/ADT/APFloat.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringExtras.h" 26 #include "llvm/ADT/StringRef.h" 27 #include "llvm/ADT/StringSwitch.h" 28 #include "llvm/ADT/Triple.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/TargetParser.h" 32 #include <algorithm> 33 #include <memory> 34 35 using namespace clang; 36 37 //===----------------------------------------------------------------------===// 38 // Common code shared among targets. 39 //===----------------------------------------------------------------------===// 40 41 /// DefineStd - Define a macro name and standard variants. For example if 42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 43 /// when in GNU mode. 44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 45 const LangOptions &Opts) { 46 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 47 48 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 49 // in the user's namespace. 50 if (Opts.GNUMode) 51 Builder.defineMacro(MacroName); 52 53 // Define __unix. 54 Builder.defineMacro("__" + MacroName); 55 56 // Define __unix__. 57 Builder.defineMacro("__" + MacroName + "__"); 58 } 59 60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 61 bool Tuning = true) { 62 Builder.defineMacro("__" + CPUName); 63 Builder.defineMacro("__" + CPUName + "__"); 64 if (Tuning) 65 Builder.defineMacro("__tune_" + CPUName + "__"); 66 } 67 68 //===----------------------------------------------------------------------===// 69 // Defines specific to certain operating systems. 70 //===----------------------------------------------------------------------===// 71 72 namespace { 73 template<typename TgtInfo> 74 class OSTargetInfo : public TgtInfo { 75 protected: 76 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 77 MacroBuilder &Builder) const=0; 78 public: 79 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 80 : TgtInfo(Triple, Opts) {} 81 void getTargetDefines(const LangOptions &Opts, 82 MacroBuilder &Builder) const override { 83 TgtInfo::getTargetDefines(Opts, Builder); 84 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 85 } 86 87 }; 88 89 // CloudABI Target 90 template <typename Target> 91 class CloudABITargetInfo : public OSTargetInfo<Target> { 92 protected: 93 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 94 MacroBuilder &Builder) const override { 95 Builder.defineMacro("__CloudABI__"); 96 Builder.defineMacro("__ELF__"); 97 98 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 99 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 100 Builder.defineMacro("__STDC_UTF_16__"); 101 Builder.defineMacro("__STDC_UTF_32__"); 102 } 103 104 public: 105 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 106 : OSTargetInfo<Target>(Triple, Opts) {} 107 }; 108 109 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 110 const llvm::Triple &Triple, 111 StringRef &PlatformName, 112 VersionTuple &PlatformMinVersion) { 113 Builder.defineMacro("__APPLE_CC__", "6000"); 114 Builder.defineMacro("__APPLE__"); 115 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 116 // AddressSanitizer doesn't play well with source fortification, which is on 117 // by default on Darwin. 118 if (Opts.Sanitize.has(SanitizerKind::Address)) 119 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 120 121 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 122 if (!Opts.ObjC1) { 123 // __weak is always defined, for use in blocks and with objc pointers. 124 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 125 Builder.defineMacro("__strong", ""); 126 Builder.defineMacro("__unsafe_unretained", ""); 127 } 128 129 if (Opts.Static) 130 Builder.defineMacro("__STATIC__"); 131 else 132 Builder.defineMacro("__DYNAMIC__"); 133 134 if (Opts.POSIXThreads) 135 Builder.defineMacro("_REENTRANT"); 136 137 // Get the platform type and version number from the triple. 138 unsigned Maj, Min, Rev; 139 if (Triple.isMacOSX()) { 140 Triple.getMacOSXVersion(Maj, Min, Rev); 141 PlatformName = "macosx"; 142 } else { 143 Triple.getOSVersion(Maj, Min, Rev); 144 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 145 } 146 147 // If -target arch-pc-win32-macho option specified, we're 148 // generating code for Win32 ABI. No need to emit 149 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 150 if (PlatformName == "win32") { 151 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 152 return; 153 } 154 155 // Set the appropriate OS version define. 156 if (Triple.isiOS()) { 157 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 158 char Str[6]; 159 Str[0] = '0' + Maj; 160 Str[1] = '0' + (Min / 10); 161 Str[2] = '0' + (Min % 10); 162 Str[3] = '0' + (Rev / 10); 163 Str[4] = '0' + (Rev % 10); 164 Str[5] = '\0'; 165 if (Triple.isTvOS()) 166 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 167 else 168 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 169 Str); 170 171 } else if (Triple.isWatchOS()) { 172 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 173 char Str[6]; 174 Str[0] = '0' + Maj; 175 Str[1] = '0' + (Min / 10); 176 Str[2] = '0' + (Min % 10); 177 Str[3] = '0' + (Rev / 10); 178 Str[4] = '0' + (Rev % 10); 179 Str[5] = '\0'; 180 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 181 } else if (Triple.isMacOSX()) { 182 // Note that the Driver allows versions which aren't representable in the 183 // define (because we only get a single digit for the minor and micro 184 // revision numbers). So, we limit them to the maximum representable 185 // version. 186 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 187 char Str[7]; 188 if (Maj < 10 || (Maj == 10 && Min < 10)) { 189 Str[0] = '0' + (Maj / 10); 190 Str[1] = '0' + (Maj % 10); 191 Str[2] = '0' + std::min(Min, 9U); 192 Str[3] = '0' + std::min(Rev, 9U); 193 Str[4] = '\0'; 194 } else { 195 // Handle versions > 10.9. 196 Str[0] = '0' + (Maj / 10); 197 Str[1] = '0' + (Maj % 10); 198 Str[2] = '0' + (Min / 10); 199 Str[3] = '0' + (Min % 10); 200 Str[4] = '0' + (Rev / 10); 201 Str[5] = '0' + (Rev % 10); 202 Str[6] = '\0'; 203 } 204 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 205 } 206 207 // Tell users about the kernel if there is one. 208 if (Triple.isOSDarwin()) 209 Builder.defineMacro("__MACH__"); 210 211 // The Watch ABI uses Dwarf EH. 212 if(Triple.isWatchABI()) 213 Builder.defineMacro("__ARM_DWARF_EH__"); 214 215 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 216 } 217 218 template<typename Target> 219 class DarwinTargetInfo : public OSTargetInfo<Target> { 220 protected: 221 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 222 MacroBuilder &Builder) const override { 223 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 224 this->PlatformMinVersion); 225 } 226 227 public: 228 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 229 : OSTargetInfo<Target>(Triple, Opts) { 230 // By default, no TLS, and we whitelist permitted architecture/OS 231 // combinations. 232 this->TLSSupported = false; 233 234 if (Triple.isMacOSX()) 235 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 236 else if (Triple.isiOS()) { 237 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 238 if (Triple.getArch() == llvm::Triple::x86_64 || 239 Triple.getArch() == llvm::Triple::aarch64) 240 this->TLSSupported = !Triple.isOSVersionLT(8); 241 else if (Triple.getArch() == llvm::Triple::x86 || 242 Triple.getArch() == llvm::Triple::arm || 243 Triple.getArch() == llvm::Triple::thumb) 244 this->TLSSupported = !Triple.isOSVersionLT(9); 245 } else if (Triple.isWatchOS()) 246 this->TLSSupported = !Triple.isOSVersionLT(2); 247 248 this->MCountName = "\01mcount"; 249 } 250 251 std::string isValidSectionSpecifier(StringRef SR) const override { 252 // Let MCSectionMachO validate this. 253 StringRef Segment, Section; 254 unsigned TAA, StubSize; 255 bool HasTAA; 256 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 257 TAA, HasTAA, StubSize); 258 } 259 260 const char *getStaticInitSectionSpecifier() const override { 261 // FIXME: We should return 0 when building kexts. 262 return "__TEXT,__StaticInit,regular,pure_instructions"; 263 } 264 265 /// Darwin does not support protected visibility. Darwin's "default" 266 /// is very similar to ELF's "protected"; Darwin requires a "weak" 267 /// attribute on declarations that can be dynamically replaced. 268 bool hasProtectedVisibility() const override { 269 return false; 270 } 271 272 unsigned getExnObjectAlignment() const override { 273 // The alignment of an exception object is 8-bytes for darwin since 274 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 275 // and therefore doesn't guarantee 16-byte alignment. 276 return 64; 277 } 278 }; 279 280 281 // DragonFlyBSD Target 282 template<typename Target> 283 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 284 protected: 285 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 286 MacroBuilder &Builder) const override { 287 // DragonFly defines; list based off of gcc output 288 Builder.defineMacro("__DragonFly__"); 289 Builder.defineMacro("__DragonFly_cc_version", "100001"); 290 Builder.defineMacro("__ELF__"); 291 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 292 Builder.defineMacro("__tune_i386__"); 293 DefineStd(Builder, "unix", Opts); 294 } 295 public: 296 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 297 : OSTargetInfo<Target>(Triple, Opts) { 298 switch (Triple.getArch()) { 299 default: 300 case llvm::Triple::x86: 301 case llvm::Triple::x86_64: 302 this->MCountName = ".mcount"; 303 break; 304 } 305 } 306 }; 307 308 // FreeBSD Target 309 template<typename Target> 310 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 311 protected: 312 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 313 MacroBuilder &Builder) const override { 314 // FreeBSD defines; list based off of gcc output 315 316 unsigned Release = Triple.getOSMajorVersion(); 317 if (Release == 0U) 318 Release = 8; 319 320 Builder.defineMacro("__FreeBSD__", Twine(Release)); 321 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 322 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 323 DefineStd(Builder, "unix", Opts); 324 Builder.defineMacro("__ELF__"); 325 326 // On FreeBSD, wchar_t contains the number of the code point as 327 // used by the character set of the locale. These character sets are 328 // not necessarily a superset of ASCII. 329 // 330 // FIXME: This is wrong; the macro refers to the numerical values 331 // of wchar_t *literals*, which are not locale-dependent. However, 332 // FreeBSD systems apparently depend on us getting this wrong, and 333 // setting this to 1 is conforming even if all the basic source 334 // character literals have the same encoding as char and wchar_t. 335 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 336 } 337 public: 338 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 339 : OSTargetInfo<Target>(Triple, Opts) { 340 switch (Triple.getArch()) { 341 default: 342 case llvm::Triple::x86: 343 case llvm::Triple::x86_64: 344 this->MCountName = ".mcount"; 345 break; 346 case llvm::Triple::mips: 347 case llvm::Triple::mipsel: 348 case llvm::Triple::ppc: 349 case llvm::Triple::ppc64: 350 case llvm::Triple::ppc64le: 351 this->MCountName = "_mcount"; 352 break; 353 case llvm::Triple::arm: 354 this->MCountName = "__mcount"; 355 break; 356 } 357 } 358 }; 359 360 // GNU/kFreeBSD Target 361 template<typename Target> 362 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 363 protected: 364 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 365 MacroBuilder &Builder) const override { 366 // GNU/kFreeBSD defines; list based off of gcc output 367 368 DefineStd(Builder, "unix", Opts); 369 Builder.defineMacro("__FreeBSD_kernel__"); 370 Builder.defineMacro("__GLIBC__"); 371 Builder.defineMacro("__ELF__"); 372 if (Opts.POSIXThreads) 373 Builder.defineMacro("_REENTRANT"); 374 if (Opts.CPlusPlus) 375 Builder.defineMacro("_GNU_SOURCE"); 376 } 377 public: 378 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 379 : OSTargetInfo<Target>(Triple, Opts) {} 380 }; 381 382 // Minix Target 383 template<typename Target> 384 class MinixTargetInfo : public OSTargetInfo<Target> { 385 protected: 386 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 387 MacroBuilder &Builder) const override { 388 // Minix defines 389 390 Builder.defineMacro("__minix", "3"); 391 Builder.defineMacro("_EM_WSIZE", "4"); 392 Builder.defineMacro("_EM_PSIZE", "4"); 393 Builder.defineMacro("_EM_SSIZE", "2"); 394 Builder.defineMacro("_EM_LSIZE", "4"); 395 Builder.defineMacro("_EM_FSIZE", "4"); 396 Builder.defineMacro("_EM_DSIZE", "8"); 397 Builder.defineMacro("__ELF__"); 398 DefineStd(Builder, "unix", Opts); 399 } 400 public: 401 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 402 : OSTargetInfo<Target>(Triple, Opts) {} 403 }; 404 405 // Linux target 406 template<typename Target> 407 class LinuxTargetInfo : public OSTargetInfo<Target> { 408 protected: 409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 410 MacroBuilder &Builder) const override { 411 // Linux defines; list based off of gcc output 412 DefineStd(Builder, "unix", Opts); 413 DefineStd(Builder, "linux", Opts); 414 Builder.defineMacro("__gnu_linux__"); 415 Builder.defineMacro("__ELF__"); 416 if (Triple.isAndroid()) { 417 Builder.defineMacro("__ANDROID__", "1"); 418 unsigned Maj, Min, Rev; 419 Triple.getEnvironmentVersion(Maj, Min, Rev); 420 this->PlatformName = "android"; 421 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 422 } 423 if (Opts.POSIXThreads) 424 Builder.defineMacro("_REENTRANT"); 425 if (Opts.CPlusPlus) 426 Builder.defineMacro("_GNU_SOURCE"); 427 } 428 public: 429 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 430 : OSTargetInfo<Target>(Triple, Opts) { 431 this->WIntType = TargetInfo::UnsignedInt; 432 433 switch (Triple.getArch()) { 434 default: 435 break; 436 case llvm::Triple::ppc: 437 case llvm::Triple::ppc64: 438 case llvm::Triple::ppc64le: 439 this->MCountName = "_mcount"; 440 break; 441 } 442 } 443 444 const char *getStaticInitSectionSpecifier() const override { 445 return ".text.startup"; 446 } 447 }; 448 449 // NetBSD Target 450 template<typename Target> 451 class NetBSDTargetInfo : public OSTargetInfo<Target> { 452 protected: 453 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 454 MacroBuilder &Builder) const override { 455 // NetBSD defines; list based off of gcc output 456 Builder.defineMacro("__NetBSD__"); 457 Builder.defineMacro("__unix__"); 458 Builder.defineMacro("__ELF__"); 459 if (Opts.POSIXThreads) 460 Builder.defineMacro("_POSIX_THREADS"); 461 462 switch (Triple.getArch()) { 463 default: 464 break; 465 case llvm::Triple::arm: 466 case llvm::Triple::armeb: 467 case llvm::Triple::thumb: 468 case llvm::Triple::thumbeb: 469 Builder.defineMacro("__ARM_DWARF_EH__"); 470 break; 471 } 472 } 473 public: 474 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 475 : OSTargetInfo<Target>(Triple, Opts) { 476 this->MCountName = "_mcount"; 477 } 478 }; 479 480 // OpenBSD Target 481 template<typename Target> 482 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 483 protected: 484 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 485 MacroBuilder &Builder) const override { 486 // OpenBSD defines; list based off of gcc output 487 488 Builder.defineMacro("__OpenBSD__"); 489 DefineStd(Builder, "unix", Opts); 490 Builder.defineMacro("__ELF__"); 491 if (Opts.POSIXThreads) 492 Builder.defineMacro("_REENTRANT"); 493 } 494 public: 495 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 496 : OSTargetInfo<Target>(Triple, Opts) { 497 this->TLSSupported = false; 498 499 switch (Triple.getArch()) { 500 default: 501 case llvm::Triple::x86: 502 case llvm::Triple::x86_64: 503 case llvm::Triple::arm: 504 case llvm::Triple::sparc: 505 this->MCountName = "__mcount"; 506 break; 507 case llvm::Triple::mips64: 508 case llvm::Triple::mips64el: 509 case llvm::Triple::ppc: 510 case llvm::Triple::sparcv9: 511 this->MCountName = "_mcount"; 512 break; 513 } 514 } 515 }; 516 517 // Bitrig Target 518 template<typename Target> 519 class BitrigTargetInfo : public OSTargetInfo<Target> { 520 protected: 521 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 522 MacroBuilder &Builder) const override { 523 // Bitrig defines; list based off of gcc output 524 525 Builder.defineMacro("__Bitrig__"); 526 DefineStd(Builder, "unix", Opts); 527 Builder.defineMacro("__ELF__"); 528 if (Opts.POSIXThreads) 529 Builder.defineMacro("_REENTRANT"); 530 531 switch (Triple.getArch()) { 532 default: 533 break; 534 case llvm::Triple::arm: 535 case llvm::Triple::armeb: 536 case llvm::Triple::thumb: 537 case llvm::Triple::thumbeb: 538 Builder.defineMacro("__ARM_DWARF_EH__"); 539 break; 540 } 541 } 542 public: 543 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 544 : OSTargetInfo<Target>(Triple, Opts) { 545 this->MCountName = "__mcount"; 546 } 547 }; 548 549 // PSP Target 550 template<typename Target> 551 class PSPTargetInfo : public OSTargetInfo<Target> { 552 protected: 553 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 554 MacroBuilder &Builder) const override { 555 // PSP defines; list based on the output of the pspdev gcc toolchain. 556 Builder.defineMacro("PSP"); 557 Builder.defineMacro("_PSP"); 558 Builder.defineMacro("__psp__"); 559 Builder.defineMacro("__ELF__"); 560 } 561 public: 562 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 563 }; 564 565 // PS3 PPU Target 566 template<typename Target> 567 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 568 protected: 569 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 570 MacroBuilder &Builder) const override { 571 // PS3 PPU defines. 572 Builder.defineMacro("__PPC__"); 573 Builder.defineMacro("__PPU__"); 574 Builder.defineMacro("__CELLOS_LV2__"); 575 Builder.defineMacro("__ELF__"); 576 Builder.defineMacro("__LP32__"); 577 Builder.defineMacro("_ARCH_PPC64"); 578 Builder.defineMacro("__powerpc64__"); 579 } 580 public: 581 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 582 : OSTargetInfo<Target>(Triple, Opts) { 583 this->LongWidth = this->LongAlign = 32; 584 this->PointerWidth = this->PointerAlign = 32; 585 this->IntMaxType = TargetInfo::SignedLongLong; 586 this->Int64Type = TargetInfo::SignedLongLong; 587 this->SizeType = TargetInfo::UnsignedInt; 588 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 589 } 590 }; 591 592 template <typename Target> 593 class PS4OSTargetInfo : public OSTargetInfo<Target> { 594 protected: 595 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 596 MacroBuilder &Builder) const override { 597 Builder.defineMacro("__FreeBSD__", "9"); 598 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 599 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 600 DefineStd(Builder, "unix", Opts); 601 Builder.defineMacro("__ELF__"); 602 Builder.defineMacro("__PS4__"); 603 } 604 public: 605 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 606 : OSTargetInfo<Target>(Triple, Opts) { 607 this->WCharType = this->UnsignedShort; 608 609 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 610 this->MaxTLSAlign = 256; 611 612 // On PS4, do not honor explicit bit field alignment, 613 // as in "__attribute__((aligned(2))) int b : 1;". 614 this->UseExplicitBitFieldAlignment = false; 615 616 switch (Triple.getArch()) { 617 default: 618 case llvm::Triple::x86_64: 619 this->MCountName = ".mcount"; 620 break; 621 } 622 } 623 }; 624 625 // Solaris target 626 template<typename Target> 627 class SolarisTargetInfo : public OSTargetInfo<Target> { 628 protected: 629 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 630 MacroBuilder &Builder) const override { 631 DefineStd(Builder, "sun", Opts); 632 DefineStd(Builder, "unix", Opts); 633 Builder.defineMacro("__ELF__"); 634 Builder.defineMacro("__svr4__"); 635 Builder.defineMacro("__SVR4"); 636 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 637 // newer, but to 500 for everything else. feature_test.h has a check to 638 // ensure that you are not using C99 with an old version of X/Open or C89 639 // with a new version. 640 if (Opts.C99) 641 Builder.defineMacro("_XOPEN_SOURCE", "600"); 642 else 643 Builder.defineMacro("_XOPEN_SOURCE", "500"); 644 if (Opts.CPlusPlus) 645 Builder.defineMacro("__C99FEATURES__"); 646 Builder.defineMacro("_LARGEFILE_SOURCE"); 647 Builder.defineMacro("_LARGEFILE64_SOURCE"); 648 Builder.defineMacro("__EXTENSIONS__"); 649 Builder.defineMacro("_REENTRANT"); 650 } 651 public: 652 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 653 : OSTargetInfo<Target>(Triple, Opts) { 654 this->WCharType = this->SignedInt; 655 // FIXME: WIntType should be SignedLong 656 } 657 }; 658 659 // Windows target 660 template<typename Target> 661 class WindowsTargetInfo : public OSTargetInfo<Target> { 662 protected: 663 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 664 MacroBuilder &Builder) const override { 665 Builder.defineMacro("_WIN32"); 666 } 667 void getVisualStudioDefines(const LangOptions &Opts, 668 MacroBuilder &Builder) const { 669 if (Opts.CPlusPlus) { 670 if (Opts.RTTIData) 671 Builder.defineMacro("_CPPRTTI"); 672 673 if (Opts.CXXExceptions) 674 Builder.defineMacro("_CPPUNWIND"); 675 } 676 677 if (Opts.Bool) 678 Builder.defineMacro("__BOOL_DEFINED"); 679 680 if (!Opts.CharIsSigned) 681 Builder.defineMacro("_CHAR_UNSIGNED"); 682 683 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 684 // but it works for now. 685 if (Opts.POSIXThreads) 686 Builder.defineMacro("_MT"); 687 688 if (Opts.MSCompatibilityVersion) { 689 Builder.defineMacro("_MSC_VER", 690 Twine(Opts.MSCompatibilityVersion / 100000)); 691 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 692 // FIXME We cannot encode the revision information into 32-bits 693 Builder.defineMacro("_MSC_BUILD", Twine(1)); 694 695 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 696 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 697 } 698 699 if (Opts.MicrosoftExt) { 700 Builder.defineMacro("_MSC_EXTENSIONS"); 701 702 if (Opts.CPlusPlus11) { 703 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 704 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 705 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 706 } 707 } 708 709 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 710 } 711 712 public: 713 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 714 : OSTargetInfo<Target>(Triple, Opts) {} 715 }; 716 717 template <typename Target> 718 class NaClTargetInfo : public OSTargetInfo<Target> { 719 protected: 720 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 721 MacroBuilder &Builder) const override { 722 if (Opts.POSIXThreads) 723 Builder.defineMacro("_REENTRANT"); 724 if (Opts.CPlusPlus) 725 Builder.defineMacro("_GNU_SOURCE"); 726 727 DefineStd(Builder, "unix", Opts); 728 Builder.defineMacro("__ELF__"); 729 Builder.defineMacro("__native_client__"); 730 } 731 732 public: 733 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 734 : OSTargetInfo<Target>(Triple, Opts) { 735 this->LongAlign = 32; 736 this->LongWidth = 32; 737 this->PointerAlign = 32; 738 this->PointerWidth = 32; 739 this->IntMaxType = TargetInfo::SignedLongLong; 740 this->Int64Type = TargetInfo::SignedLongLong; 741 this->DoubleAlign = 64; 742 this->LongDoubleWidth = 64; 743 this->LongDoubleAlign = 64; 744 this->LongLongWidth = 64; 745 this->LongLongAlign = 64; 746 this->SizeType = TargetInfo::UnsignedInt; 747 this->PtrDiffType = TargetInfo::SignedInt; 748 this->IntPtrType = TargetInfo::SignedInt; 749 // RegParmMax is inherited from the underlying architecture 750 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 751 if (Triple.getArch() == llvm::Triple::arm) { 752 // Handled in ARM's setABI(). 753 } else if (Triple.getArch() == llvm::Triple::x86) { 754 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 755 } else if (Triple.getArch() == llvm::Triple::x86_64) { 756 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 757 } else if (Triple.getArch() == llvm::Triple::mipsel) { 758 // Handled on mips' setDataLayout. 759 } else { 760 assert(Triple.getArch() == llvm::Triple::le32); 761 this->resetDataLayout("e-p:32:32-i64:64"); 762 } 763 } 764 }; 765 766 // WebAssembly target 767 template <typename Target> 768 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 769 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 770 MacroBuilder &Builder) const final { 771 // A common platform macro. 772 if (Opts.POSIXThreads) 773 Builder.defineMacro("_REENTRANT"); 774 // Follow g++ convention and predefine _GNU_SOURCE for C++. 775 if (Opts.CPlusPlus) 776 Builder.defineMacro("_GNU_SOURCE"); 777 } 778 779 // As an optimization, group static init code together in a section. 780 const char *getStaticInitSectionSpecifier() const final { 781 return ".text.__startup"; 782 } 783 784 public: 785 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 786 const TargetOptions &Opts) 787 : OSTargetInfo<Target>(Triple, Opts) { 788 this->MCountName = "__mcount"; 789 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 790 } 791 }; 792 793 //===----------------------------------------------------------------------===// 794 // Specific target implementations. 795 //===----------------------------------------------------------------------===// 796 797 // PPC abstract base class 798 class PPCTargetInfo : public TargetInfo { 799 static const Builtin::Info BuiltinInfo[]; 800 static const char * const GCCRegNames[]; 801 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 802 std::string CPU; 803 804 // Target cpu features. 805 bool HasVSX; 806 bool HasP8Vector; 807 bool HasP8Crypto; 808 bool HasDirectMove; 809 bool HasQPX; 810 bool HasHTM; 811 bool HasBPERMD; 812 bool HasExtDiv; 813 814 protected: 815 std::string ABI; 816 817 public: 818 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 819 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 820 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 821 HasBPERMD(false), HasExtDiv(false) { 822 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 823 SimdDefaultAlign = 128; 824 LongDoubleWidth = LongDoubleAlign = 128; 825 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 826 } 827 828 /// \brief Flags for architecture specific defines. 829 typedef enum { 830 ArchDefineNone = 0, 831 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 832 ArchDefinePpcgr = 1 << 1, 833 ArchDefinePpcsq = 1 << 2, 834 ArchDefine440 = 1 << 3, 835 ArchDefine603 = 1 << 4, 836 ArchDefine604 = 1 << 5, 837 ArchDefinePwr4 = 1 << 6, 838 ArchDefinePwr5 = 1 << 7, 839 ArchDefinePwr5x = 1 << 8, 840 ArchDefinePwr6 = 1 << 9, 841 ArchDefinePwr6x = 1 << 10, 842 ArchDefinePwr7 = 1 << 11, 843 ArchDefinePwr8 = 1 << 12, 844 ArchDefineA2 = 1 << 13, 845 ArchDefineA2q = 1 << 14 846 } ArchDefineTypes; 847 848 // Note: GCC recognizes the following additional cpus: 849 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 850 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 851 // titan, rs64. 852 bool setCPU(const std::string &Name) override { 853 bool CPUKnown = llvm::StringSwitch<bool>(Name) 854 .Case("generic", true) 855 .Case("440", true) 856 .Case("450", true) 857 .Case("601", true) 858 .Case("602", true) 859 .Case("603", true) 860 .Case("603e", true) 861 .Case("603ev", true) 862 .Case("604", true) 863 .Case("604e", true) 864 .Case("620", true) 865 .Case("630", true) 866 .Case("g3", true) 867 .Case("7400", true) 868 .Case("g4", true) 869 .Case("7450", true) 870 .Case("g4+", true) 871 .Case("750", true) 872 .Case("970", true) 873 .Case("g5", true) 874 .Case("a2", true) 875 .Case("a2q", true) 876 .Case("e500mc", true) 877 .Case("e5500", true) 878 .Case("power3", true) 879 .Case("pwr3", true) 880 .Case("power4", true) 881 .Case("pwr4", true) 882 .Case("power5", true) 883 .Case("pwr5", true) 884 .Case("power5x", true) 885 .Case("pwr5x", true) 886 .Case("power6", true) 887 .Case("pwr6", true) 888 .Case("power6x", true) 889 .Case("pwr6x", true) 890 .Case("power7", true) 891 .Case("pwr7", true) 892 .Case("power8", true) 893 .Case("pwr8", true) 894 .Case("powerpc", true) 895 .Case("ppc", true) 896 .Case("powerpc64", true) 897 .Case("ppc64", true) 898 .Case("powerpc64le", true) 899 .Case("ppc64le", true) 900 .Default(false); 901 902 if (CPUKnown) 903 CPU = Name; 904 905 return CPUKnown; 906 } 907 908 909 StringRef getABI() const override { return ABI; } 910 911 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 912 return llvm::makeArrayRef(BuiltinInfo, 913 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 914 } 915 916 bool isCLZForZeroUndef() const override { return false; } 917 918 void getTargetDefines(const LangOptions &Opts, 919 MacroBuilder &Builder) const override; 920 921 bool 922 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 923 StringRef CPU, 924 const std::vector<std::string> &FeaturesVec) const override; 925 926 bool handleTargetFeatures(std::vector<std::string> &Features, 927 DiagnosticsEngine &Diags) override; 928 bool hasFeature(StringRef Feature) const override; 929 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 930 bool Enabled) const override; 931 932 ArrayRef<const char *> getGCCRegNames() const override; 933 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 934 bool validateAsmConstraint(const char *&Name, 935 TargetInfo::ConstraintInfo &Info) const override { 936 switch (*Name) { 937 default: return false; 938 case 'O': // Zero 939 break; 940 case 'b': // Base register 941 case 'f': // Floating point register 942 Info.setAllowsRegister(); 943 break; 944 // FIXME: The following are added to allow parsing. 945 // I just took a guess at what the actions should be. 946 // Also, is more specific checking needed? I.e. specific registers? 947 case 'd': // Floating point register (containing 64-bit value) 948 case 'v': // Altivec vector register 949 Info.setAllowsRegister(); 950 break; 951 case 'w': 952 switch (Name[1]) { 953 case 'd':// VSX vector register to hold vector double data 954 case 'f':// VSX vector register to hold vector float data 955 case 's':// VSX vector register to hold scalar float data 956 case 'a':// Any VSX register 957 case 'c':// An individual CR bit 958 break; 959 default: 960 return false; 961 } 962 Info.setAllowsRegister(); 963 Name++; // Skip over 'w'. 964 break; 965 case 'h': // `MQ', `CTR', or `LINK' register 966 case 'q': // `MQ' register 967 case 'c': // `CTR' register 968 case 'l': // `LINK' register 969 case 'x': // `CR' register (condition register) number 0 970 case 'y': // `CR' register (condition register) 971 case 'z': // `XER[CA]' carry bit (part of the XER register) 972 Info.setAllowsRegister(); 973 break; 974 case 'I': // Signed 16-bit constant 975 case 'J': // Unsigned 16-bit constant shifted left 16 bits 976 // (use `L' instead for SImode constants) 977 case 'K': // Unsigned 16-bit constant 978 case 'L': // Signed 16-bit constant shifted left 16 bits 979 case 'M': // Constant larger than 31 980 case 'N': // Exact power of 2 981 case 'P': // Constant whose negation is a signed 16-bit constant 982 case 'G': // Floating point constant that can be loaded into a 983 // register with one instruction per word 984 case 'H': // Integer/Floating point constant that can be loaded 985 // into a register using three instructions 986 break; 987 case 'm': // Memory operand. Note that on PowerPC targets, m can 988 // include addresses that update the base register. It 989 // is therefore only safe to use `m' in an asm statement 990 // if that asm statement accesses the operand exactly once. 991 // The asm statement must also use `%U<opno>' as a 992 // placeholder for the "update" flag in the corresponding 993 // load or store instruction. For example: 994 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 995 // is correct but: 996 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 997 // is not. Use es rather than m if you don't want the base 998 // register to be updated. 999 case 'e': 1000 if (Name[1] != 's') 1001 return false; 1002 // es: A "stable" memory operand; that is, one which does not 1003 // include any automodification of the base register. Unlike 1004 // `m', this constraint can be used in asm statements that 1005 // might access the operand several times, or that might not 1006 // access it at all. 1007 Info.setAllowsMemory(); 1008 Name++; // Skip over 'e'. 1009 break; 1010 case 'Q': // Memory operand that is an offset from a register (it is 1011 // usually better to use `m' or `es' in asm statements) 1012 case 'Z': // Memory operand that is an indexed or indirect from a 1013 // register (it is usually better to use `m' or `es' in 1014 // asm statements) 1015 Info.setAllowsMemory(); 1016 Info.setAllowsRegister(); 1017 break; 1018 case 'R': // AIX TOC entry 1019 case 'a': // Address operand that is an indexed or indirect from a 1020 // register (`p' is preferable for asm statements) 1021 case 'S': // Constant suitable as a 64-bit mask operand 1022 case 'T': // Constant suitable as a 32-bit mask operand 1023 case 'U': // System V Release 4 small data area reference 1024 case 't': // AND masks that can be performed by two rldic{l, r} 1025 // instructions 1026 case 'W': // Vector constant that does not require memory 1027 case 'j': // Vector constant that is all zeros. 1028 break; 1029 // End FIXME. 1030 } 1031 return true; 1032 } 1033 std::string convertConstraint(const char *&Constraint) const override { 1034 std::string R; 1035 switch (*Constraint) { 1036 case 'e': 1037 case 'w': 1038 // Two-character constraint; add "^" hint for later parsing. 1039 R = std::string("^") + std::string(Constraint, 2); 1040 Constraint++; 1041 break; 1042 default: 1043 return TargetInfo::convertConstraint(Constraint); 1044 } 1045 return R; 1046 } 1047 const char *getClobbers() const override { 1048 return ""; 1049 } 1050 int getEHDataRegisterNumber(unsigned RegNo) const override { 1051 if (RegNo == 0) return 3; 1052 if (RegNo == 1) return 4; 1053 return -1; 1054 } 1055 1056 bool hasSjLjLowering() const override { 1057 return true; 1058 } 1059 1060 bool useFloat128ManglingForLongDouble() const override { 1061 return LongDoubleWidth == 128 && 1062 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1063 getTriple().isOSBinFormatELF(); 1064 } 1065 }; 1066 1067 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1068 #define BUILTIN(ID, TYPE, ATTRS) \ 1069 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1070 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1071 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1072 #include "clang/Basic/BuiltinsPPC.def" 1073 }; 1074 1075 /// handleTargetFeatures - Perform initialization based on the user 1076 /// configured set of features. 1077 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1078 DiagnosticsEngine &Diags) { 1079 for (const auto &Feature : Features) { 1080 if (Feature == "+vsx") { 1081 HasVSX = true; 1082 } else if (Feature == "+bpermd") { 1083 HasBPERMD = true; 1084 } else if (Feature == "+extdiv") { 1085 HasExtDiv = true; 1086 } else if (Feature == "+power8-vector") { 1087 HasP8Vector = true; 1088 } else if (Feature == "+crypto") { 1089 HasP8Crypto = true; 1090 } else if (Feature == "+direct-move") { 1091 HasDirectMove = true; 1092 } else if (Feature == "+qpx") { 1093 HasQPX = true; 1094 } else if (Feature == "+htm") { 1095 HasHTM = true; 1096 } 1097 // TODO: Finish this list and add an assert that we've handled them 1098 // all. 1099 } 1100 1101 return true; 1102 } 1103 1104 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1105 /// #defines that are not tied to a specific subtarget. 1106 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1107 MacroBuilder &Builder) const { 1108 // Target identification. 1109 Builder.defineMacro("__ppc__"); 1110 Builder.defineMacro("__PPC__"); 1111 Builder.defineMacro("_ARCH_PPC"); 1112 Builder.defineMacro("__powerpc__"); 1113 Builder.defineMacro("__POWERPC__"); 1114 if (PointerWidth == 64) { 1115 Builder.defineMacro("_ARCH_PPC64"); 1116 Builder.defineMacro("__powerpc64__"); 1117 Builder.defineMacro("__ppc64__"); 1118 Builder.defineMacro("__PPC64__"); 1119 } 1120 1121 // Target properties. 1122 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1123 Builder.defineMacro("_LITTLE_ENDIAN"); 1124 } else { 1125 if (getTriple().getOS() != llvm::Triple::NetBSD && 1126 getTriple().getOS() != llvm::Triple::OpenBSD) 1127 Builder.defineMacro("_BIG_ENDIAN"); 1128 } 1129 1130 // ABI options. 1131 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1132 Builder.defineMacro("_CALL_ELF", "1"); 1133 if (ABI == "elfv2") 1134 Builder.defineMacro("_CALL_ELF", "2"); 1135 1136 // Subtarget options. 1137 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1138 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1139 1140 // FIXME: Should be controlled by command line option. 1141 if (LongDoubleWidth == 128) 1142 Builder.defineMacro("__LONG_DOUBLE_128__"); 1143 1144 if (Opts.AltiVec) { 1145 Builder.defineMacro("__VEC__", "10206"); 1146 Builder.defineMacro("__ALTIVEC__"); 1147 } 1148 1149 // CPU identification. 1150 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1151 .Case("440", ArchDefineName) 1152 .Case("450", ArchDefineName | ArchDefine440) 1153 .Case("601", ArchDefineName) 1154 .Case("602", ArchDefineName | ArchDefinePpcgr) 1155 .Case("603", ArchDefineName | ArchDefinePpcgr) 1156 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1157 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1158 .Case("604", ArchDefineName | ArchDefinePpcgr) 1159 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1160 .Case("620", ArchDefineName | ArchDefinePpcgr) 1161 .Case("630", ArchDefineName | ArchDefinePpcgr) 1162 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1163 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1164 .Case("750", ArchDefineName | ArchDefinePpcgr) 1165 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1166 | ArchDefinePpcsq) 1167 .Case("a2", ArchDefineA2) 1168 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1169 .Case("pwr3", ArchDefinePpcgr) 1170 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1171 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1172 | ArchDefinePpcsq) 1173 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1174 | ArchDefinePpcgr | ArchDefinePpcsq) 1175 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1176 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1177 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1178 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1179 | ArchDefinePpcsq) 1180 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1181 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1182 | ArchDefinePpcgr | ArchDefinePpcsq) 1183 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1184 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1185 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1186 .Case("power3", ArchDefinePpcgr) 1187 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1188 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1189 | ArchDefinePpcsq) 1190 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1191 | ArchDefinePpcgr | ArchDefinePpcsq) 1192 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1193 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1194 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1195 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1196 | ArchDefinePpcsq) 1197 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1198 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1199 | ArchDefinePpcgr | ArchDefinePpcsq) 1200 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1201 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1202 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1203 .Default(ArchDefineNone); 1204 1205 if (defs & ArchDefineName) 1206 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1207 if (defs & ArchDefinePpcgr) 1208 Builder.defineMacro("_ARCH_PPCGR"); 1209 if (defs & ArchDefinePpcsq) 1210 Builder.defineMacro("_ARCH_PPCSQ"); 1211 if (defs & ArchDefine440) 1212 Builder.defineMacro("_ARCH_440"); 1213 if (defs & ArchDefine603) 1214 Builder.defineMacro("_ARCH_603"); 1215 if (defs & ArchDefine604) 1216 Builder.defineMacro("_ARCH_604"); 1217 if (defs & ArchDefinePwr4) 1218 Builder.defineMacro("_ARCH_PWR4"); 1219 if (defs & ArchDefinePwr5) 1220 Builder.defineMacro("_ARCH_PWR5"); 1221 if (defs & ArchDefinePwr5x) 1222 Builder.defineMacro("_ARCH_PWR5X"); 1223 if (defs & ArchDefinePwr6) 1224 Builder.defineMacro("_ARCH_PWR6"); 1225 if (defs & ArchDefinePwr6x) 1226 Builder.defineMacro("_ARCH_PWR6X"); 1227 if (defs & ArchDefinePwr7) 1228 Builder.defineMacro("_ARCH_PWR7"); 1229 if (defs & ArchDefinePwr8) 1230 Builder.defineMacro("_ARCH_PWR8"); 1231 if (defs & ArchDefineA2) 1232 Builder.defineMacro("_ARCH_A2"); 1233 if (defs & ArchDefineA2q) { 1234 Builder.defineMacro("_ARCH_A2Q"); 1235 Builder.defineMacro("_ARCH_QP"); 1236 } 1237 1238 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1239 Builder.defineMacro("__bg__"); 1240 Builder.defineMacro("__THW_BLUEGENE__"); 1241 Builder.defineMacro("__bgq__"); 1242 Builder.defineMacro("__TOS_BGQ__"); 1243 } 1244 1245 if (HasVSX) 1246 Builder.defineMacro("__VSX__"); 1247 if (HasP8Vector) 1248 Builder.defineMacro("__POWER8_VECTOR__"); 1249 if (HasP8Crypto) 1250 Builder.defineMacro("__CRYPTO__"); 1251 if (HasHTM) 1252 Builder.defineMacro("__HTM__"); 1253 1254 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1255 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1256 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1257 if (PointerWidth == 64) 1258 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1259 1260 // FIXME: The following are not yet generated here by Clang, but are 1261 // generated by GCC: 1262 // 1263 // _SOFT_FLOAT_ 1264 // __RECIP_PRECISION__ 1265 // __APPLE_ALTIVEC__ 1266 // __RECIP__ 1267 // __RECIPF__ 1268 // __RSQRTE__ 1269 // __RSQRTEF__ 1270 // _SOFT_DOUBLE_ 1271 // __NO_LWSYNC__ 1272 // __HAVE_BSWAP__ 1273 // __LONGDOUBLE128 1274 // __CMODEL_MEDIUM__ 1275 // __CMODEL_LARGE__ 1276 // _CALL_SYSV 1277 // _CALL_DARWIN 1278 // __NO_FPRS__ 1279 } 1280 1281 // Handle explicit options being passed to the compiler here: if we've 1282 // explicitly turned off vsx and turned on power8-vector or direct-move then 1283 // go ahead and error since the customer has expressed a somewhat incompatible 1284 // set of options. 1285 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1286 const std::vector<std::string> &FeaturesVec) { 1287 1288 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1289 FeaturesVec.end()) { 1290 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1291 FeaturesVec.end()) { 1292 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1293 << "-mno-vsx"; 1294 return false; 1295 } 1296 1297 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1298 FeaturesVec.end()) { 1299 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1300 << "-mno-vsx"; 1301 return false; 1302 } 1303 } 1304 1305 return true; 1306 } 1307 1308 bool PPCTargetInfo::initFeatureMap( 1309 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1310 const std::vector<std::string> &FeaturesVec) const { 1311 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1312 .Case("7400", true) 1313 .Case("g4", true) 1314 .Case("7450", true) 1315 .Case("g4+", true) 1316 .Case("970", true) 1317 .Case("g5", true) 1318 .Case("pwr6", true) 1319 .Case("pwr7", true) 1320 .Case("pwr8", true) 1321 .Case("ppc64", true) 1322 .Case("ppc64le", true) 1323 .Default(false); 1324 1325 Features["qpx"] = (CPU == "a2q"); 1326 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1327 .Case("ppc64le", true) 1328 .Case("pwr8", true) 1329 .Default(false); 1330 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1331 .Case("ppc64le", true) 1332 .Case("pwr8", true) 1333 .Default(false); 1334 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1335 .Case("ppc64le", true) 1336 .Case("pwr8", true) 1337 .Case("pwr7", true) 1338 .Default(false); 1339 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1340 .Case("ppc64le", true) 1341 .Case("pwr8", true) 1342 .Case("pwr7", true) 1343 .Default(false); 1344 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1345 .Case("ppc64le", true) 1346 .Case("pwr8", true) 1347 .Default(false); 1348 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1349 .Case("ppc64le", true) 1350 .Case("pwr8", true) 1351 .Case("pwr7", true) 1352 .Default(false); 1353 1354 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1355 return false; 1356 1357 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1358 } 1359 1360 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1361 return llvm::StringSwitch<bool>(Feature) 1362 .Case("powerpc", true) 1363 .Case("vsx", HasVSX) 1364 .Case("power8-vector", HasP8Vector) 1365 .Case("crypto", HasP8Crypto) 1366 .Case("direct-move", HasDirectMove) 1367 .Case("qpx", HasQPX) 1368 .Case("htm", HasHTM) 1369 .Case("bpermd", HasBPERMD) 1370 .Case("extdiv", HasExtDiv) 1371 .Default(false); 1372 } 1373 1374 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1375 StringRef Name, bool Enabled) const { 1376 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1377 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1378 // incompatible options. 1379 if (Enabled) { 1380 if (Name == "vsx") { 1381 Features[Name] = true; 1382 } else if (Name == "direct-move") { 1383 Features[Name] = Features["vsx"] = true; 1384 } else if (Name == "power8-vector") { 1385 Features[Name] = Features["vsx"] = true; 1386 } else { 1387 Features[Name] = true; 1388 } 1389 } else { 1390 if (Name == "vsx") { 1391 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1392 false; 1393 } else { 1394 Features[Name] = false; 1395 } 1396 } 1397 } 1398 1399 const char * const PPCTargetInfo::GCCRegNames[] = { 1400 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1401 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1402 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1403 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1404 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1405 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1406 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1407 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1408 "mq", "lr", "ctr", "ap", 1409 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1410 "xer", 1411 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1412 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1413 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1414 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1415 "vrsave", "vscr", 1416 "spe_acc", "spefscr", 1417 "sfp" 1418 }; 1419 1420 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1421 return llvm::makeArrayRef(GCCRegNames); 1422 } 1423 1424 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1425 // While some of these aliases do map to different registers 1426 // they still share the same register name. 1427 { { "0" }, "r0" }, 1428 { { "1"}, "r1" }, 1429 { { "2" }, "r2" }, 1430 { { "3" }, "r3" }, 1431 { { "4" }, "r4" }, 1432 { { "5" }, "r5" }, 1433 { { "6" }, "r6" }, 1434 { { "7" }, "r7" }, 1435 { { "8" }, "r8" }, 1436 { { "9" }, "r9" }, 1437 { { "10" }, "r10" }, 1438 { { "11" }, "r11" }, 1439 { { "12" }, "r12" }, 1440 { { "13" }, "r13" }, 1441 { { "14" }, "r14" }, 1442 { { "15" }, "r15" }, 1443 { { "16" }, "r16" }, 1444 { { "17" }, "r17" }, 1445 { { "18" }, "r18" }, 1446 { { "19" }, "r19" }, 1447 { { "20" }, "r20" }, 1448 { { "21" }, "r21" }, 1449 { { "22" }, "r22" }, 1450 { { "23" }, "r23" }, 1451 { { "24" }, "r24" }, 1452 { { "25" }, "r25" }, 1453 { { "26" }, "r26" }, 1454 { { "27" }, "r27" }, 1455 { { "28" }, "r28" }, 1456 { { "29" }, "r29" }, 1457 { { "30" }, "r30" }, 1458 { { "31" }, "r31" }, 1459 { { "fr0" }, "f0" }, 1460 { { "fr1" }, "f1" }, 1461 { { "fr2" }, "f2" }, 1462 { { "fr3" }, "f3" }, 1463 { { "fr4" }, "f4" }, 1464 { { "fr5" }, "f5" }, 1465 { { "fr6" }, "f6" }, 1466 { { "fr7" }, "f7" }, 1467 { { "fr8" }, "f8" }, 1468 { { "fr9" }, "f9" }, 1469 { { "fr10" }, "f10" }, 1470 { { "fr11" }, "f11" }, 1471 { { "fr12" }, "f12" }, 1472 { { "fr13" }, "f13" }, 1473 { { "fr14" }, "f14" }, 1474 { { "fr15" }, "f15" }, 1475 { { "fr16" }, "f16" }, 1476 { { "fr17" }, "f17" }, 1477 { { "fr18" }, "f18" }, 1478 { { "fr19" }, "f19" }, 1479 { { "fr20" }, "f20" }, 1480 { { "fr21" }, "f21" }, 1481 { { "fr22" }, "f22" }, 1482 { { "fr23" }, "f23" }, 1483 { { "fr24" }, "f24" }, 1484 { { "fr25" }, "f25" }, 1485 { { "fr26" }, "f26" }, 1486 { { "fr27" }, "f27" }, 1487 { { "fr28" }, "f28" }, 1488 { { "fr29" }, "f29" }, 1489 { { "fr30" }, "f30" }, 1490 { { "fr31" }, "f31" }, 1491 { { "cc" }, "cr0" }, 1492 }; 1493 1494 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1495 return llvm::makeArrayRef(GCCRegAliases); 1496 } 1497 1498 class PPC32TargetInfo : public PPCTargetInfo { 1499 public: 1500 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1501 : PPCTargetInfo(Triple, Opts) { 1502 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1503 1504 switch (getTriple().getOS()) { 1505 case llvm::Triple::Linux: 1506 case llvm::Triple::FreeBSD: 1507 case llvm::Triple::NetBSD: 1508 SizeType = UnsignedInt; 1509 PtrDiffType = SignedInt; 1510 IntPtrType = SignedInt; 1511 break; 1512 default: 1513 break; 1514 } 1515 1516 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1517 LongDoubleWidth = LongDoubleAlign = 64; 1518 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1519 } 1520 1521 // PPC32 supports atomics up to 4 bytes. 1522 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1523 } 1524 1525 BuiltinVaListKind getBuiltinVaListKind() const override { 1526 // This is the ELF definition, and is overridden by the Darwin sub-target 1527 return TargetInfo::PowerABIBuiltinVaList; 1528 } 1529 }; 1530 1531 // Note: ABI differences may eventually require us to have a separate 1532 // TargetInfo for little endian. 1533 class PPC64TargetInfo : public PPCTargetInfo { 1534 public: 1535 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1536 : PPCTargetInfo(Triple, Opts) { 1537 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1538 IntMaxType = SignedLong; 1539 Int64Type = SignedLong; 1540 1541 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1542 resetDataLayout("e-m:e-i64:64-n32:64"); 1543 ABI = "elfv2"; 1544 } else { 1545 resetDataLayout("E-m:e-i64:64-n32:64"); 1546 ABI = "elfv1"; 1547 } 1548 1549 switch (getTriple().getOS()) { 1550 case llvm::Triple::FreeBSD: 1551 LongDoubleWidth = LongDoubleAlign = 64; 1552 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1553 break; 1554 case llvm::Triple::NetBSD: 1555 IntMaxType = SignedLongLong; 1556 Int64Type = SignedLongLong; 1557 break; 1558 default: 1559 break; 1560 } 1561 1562 // PPC64 supports atomics up to 8 bytes. 1563 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1564 } 1565 BuiltinVaListKind getBuiltinVaListKind() const override { 1566 return TargetInfo::CharPtrBuiltinVaList; 1567 } 1568 // PPC64 Linux-specific ABI options. 1569 bool setABI(const std::string &Name) override { 1570 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1571 ABI = Name; 1572 return true; 1573 } 1574 return false; 1575 } 1576 }; 1577 1578 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1579 public: 1580 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1581 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1582 HasAlignMac68kSupport = true; 1583 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1584 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1585 LongLongAlign = 32; 1586 SuitableAlign = 128; 1587 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1588 } 1589 BuiltinVaListKind getBuiltinVaListKind() const override { 1590 return TargetInfo::CharPtrBuiltinVaList; 1591 } 1592 }; 1593 1594 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1595 public: 1596 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1597 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1598 HasAlignMac68kSupport = true; 1599 SuitableAlign = 128; 1600 resetDataLayout("E-m:o-i64:64-n32:64"); 1601 } 1602 }; 1603 1604 static const unsigned NVPTXAddrSpaceMap[] = { 1605 1, // opencl_global 1606 3, // opencl_local 1607 4, // opencl_constant 1608 // FIXME: generic has to be added to the target 1609 0, // opencl_generic 1610 1, // cuda_device 1611 4, // cuda_constant 1612 3, // cuda_shared 1613 }; 1614 1615 class NVPTXTargetInfo : public TargetInfo { 1616 static const char *const GCCRegNames[]; 1617 static const Builtin::Info BuiltinInfo[]; 1618 1619 // The GPU profiles supported by the NVPTX backend 1620 enum GPUKind { 1621 GK_NONE, 1622 GK_SM20, 1623 GK_SM21, 1624 GK_SM30, 1625 GK_SM35, 1626 GK_SM37, 1627 } GPU; 1628 1629 public: 1630 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 1631 : TargetInfo(Triple) { 1632 BigEndian = false; 1633 TLSSupported = false; 1634 LongWidth = LongAlign = 64; 1635 AddrSpaceMap = &NVPTXAddrSpaceMap; 1636 UseAddrSpaceMapMangling = true; 1637 // Define available target features 1638 // These must be defined in sorted order! 1639 NoAsmVariants = true; 1640 // Set the default GPU to sm20 1641 GPU = GK_SM20; 1642 } 1643 void getTargetDefines(const LangOptions &Opts, 1644 MacroBuilder &Builder) const override { 1645 Builder.defineMacro("__PTX__"); 1646 Builder.defineMacro("__NVPTX__"); 1647 if (Opts.CUDAIsDevice) { 1648 // Set __CUDA_ARCH__ for the GPU specified. 1649 std::string CUDAArchCode; 1650 switch (GPU) { 1651 case GK_SM20: 1652 CUDAArchCode = "200"; 1653 break; 1654 case GK_SM21: 1655 CUDAArchCode = "210"; 1656 break; 1657 case GK_SM30: 1658 CUDAArchCode = "300"; 1659 break; 1660 case GK_SM35: 1661 CUDAArchCode = "350"; 1662 break; 1663 case GK_SM37: 1664 CUDAArchCode = "370"; 1665 break; 1666 default: 1667 llvm_unreachable("Unhandled target CPU"); 1668 } 1669 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1670 } 1671 } 1672 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1673 return llvm::makeArrayRef(BuiltinInfo, 1674 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1675 } 1676 bool hasFeature(StringRef Feature) const override { 1677 return Feature == "ptx" || Feature == "nvptx"; 1678 } 1679 1680 ArrayRef<const char *> getGCCRegNames() const override; 1681 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1682 // No aliases. 1683 return None; 1684 } 1685 bool validateAsmConstraint(const char *&Name, 1686 TargetInfo::ConstraintInfo &Info) const override { 1687 switch (*Name) { 1688 default: 1689 return false; 1690 case 'c': 1691 case 'h': 1692 case 'r': 1693 case 'l': 1694 case 'f': 1695 case 'd': 1696 Info.setAllowsRegister(); 1697 return true; 1698 } 1699 } 1700 const char *getClobbers() const override { 1701 // FIXME: Is this really right? 1702 return ""; 1703 } 1704 BuiltinVaListKind getBuiltinVaListKind() const override { 1705 // FIXME: implement 1706 return TargetInfo::CharPtrBuiltinVaList; 1707 } 1708 bool setCPU(const std::string &Name) override { 1709 GPU = llvm::StringSwitch<GPUKind>(Name) 1710 .Case("sm_20", GK_SM20) 1711 .Case("sm_21", GK_SM21) 1712 .Case("sm_30", GK_SM30) 1713 .Case("sm_35", GK_SM35) 1714 .Case("sm_37", GK_SM37) 1715 .Default(GK_NONE); 1716 1717 return GPU != GK_NONE; 1718 } 1719 }; 1720 1721 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1722 #define BUILTIN(ID, TYPE, ATTRS) \ 1723 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1724 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1725 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1726 #include "clang/Basic/BuiltinsNVPTX.def" 1727 }; 1728 1729 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1730 1731 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1732 return llvm::makeArrayRef(GCCRegNames); 1733 } 1734 1735 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1736 public: 1737 NVPTX32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1738 : NVPTXTargetInfo(Triple, Opts) { 1739 LongWidth = LongAlign = 32; 1740 PointerWidth = PointerAlign = 32; 1741 SizeType = TargetInfo::UnsignedInt; 1742 PtrDiffType = TargetInfo::SignedInt; 1743 IntPtrType = TargetInfo::SignedInt; 1744 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1745 } 1746 }; 1747 1748 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1749 public: 1750 NVPTX64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1751 : NVPTXTargetInfo(Triple, Opts) { 1752 PointerWidth = PointerAlign = 64; 1753 SizeType = TargetInfo::UnsignedLong; 1754 PtrDiffType = TargetInfo::SignedLong; 1755 IntPtrType = TargetInfo::SignedLong; 1756 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1757 } 1758 }; 1759 1760 static const unsigned AMDGPUAddrSpaceMap[] = { 1761 1, // opencl_global 1762 3, // opencl_local 1763 2, // opencl_constant 1764 4, // opencl_generic 1765 1, // cuda_device 1766 2, // cuda_constant 1767 3 // cuda_shared 1768 }; 1769 1770 // If you edit the description strings, make sure you update 1771 // getPointerWidthV(). 1772 1773 static const char *const DataLayoutStringR600 = 1774 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1775 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1776 1777 static const char *const DataLayoutStringSI = 1778 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1779 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1780 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1781 1782 class AMDGPUTargetInfo : public TargetInfo { 1783 static const Builtin::Info BuiltinInfo[]; 1784 static const char * const GCCRegNames[]; 1785 1786 /// \brief The GPU profiles supported by the AMDGPU target. 1787 enum GPUKind { 1788 GK_NONE, 1789 GK_R600, 1790 GK_R600_DOUBLE_OPS, 1791 GK_R700, 1792 GK_R700_DOUBLE_OPS, 1793 GK_EVERGREEN, 1794 GK_EVERGREEN_DOUBLE_OPS, 1795 GK_NORTHERN_ISLANDS, 1796 GK_CAYMAN, 1797 GK_SOUTHERN_ISLANDS, 1798 GK_SEA_ISLANDS, 1799 GK_VOLCANIC_ISLANDS 1800 } GPU; 1801 1802 bool hasFP64:1; 1803 bool hasFMAF:1; 1804 bool hasLDEXPF:1; 1805 1806 public: 1807 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 1808 : TargetInfo(Triple) { 1809 if (Triple.getArch() == llvm::Triple::amdgcn) { 1810 resetDataLayout(DataLayoutStringSI); 1811 GPU = GK_SOUTHERN_ISLANDS; 1812 hasFP64 = true; 1813 hasFMAF = true; 1814 hasLDEXPF = true; 1815 } else { 1816 resetDataLayout(DataLayoutStringR600); 1817 GPU = GK_R600; 1818 hasFP64 = false; 1819 hasFMAF = false; 1820 hasLDEXPF = false; 1821 } 1822 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1823 UseAddrSpaceMapMangling = true; 1824 } 1825 1826 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1827 if (GPU <= GK_CAYMAN) 1828 return 32; 1829 1830 switch(AddrSpace) { 1831 default: 1832 return 64; 1833 case 0: 1834 case 3: 1835 case 5: 1836 return 32; 1837 } 1838 } 1839 1840 const char * getClobbers() const override { 1841 return ""; 1842 } 1843 1844 ArrayRef<const char *> getGCCRegNames() const override; 1845 1846 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1847 return None; 1848 } 1849 1850 bool validateAsmConstraint(const char *&Name, 1851 TargetInfo::ConstraintInfo &Info) const override { 1852 switch (*Name) { 1853 default: break; 1854 case 'v': // vgpr 1855 case 's': // sgpr 1856 Info.setAllowsRegister(); 1857 return true; 1858 } 1859 return false; 1860 } 1861 1862 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1863 return llvm::makeArrayRef(BuiltinInfo, 1864 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 1865 } 1866 1867 void getTargetDefines(const LangOptions &Opts, 1868 MacroBuilder &Builder) const override { 1869 if (getTriple().getArch() == llvm::Triple::amdgcn) 1870 Builder.defineMacro("__AMDGCN__"); 1871 else 1872 Builder.defineMacro("__R600__"); 1873 1874 if (hasFMAF) 1875 Builder.defineMacro("__HAS_FMAF__"); 1876 if (hasLDEXPF) 1877 Builder.defineMacro("__HAS_LDEXPF__"); 1878 if (hasFP64 && Opts.OpenCL) 1879 Builder.defineMacro("cl_khr_fp64"); 1880 if (Opts.OpenCL) { 1881 if (GPU >= GK_NORTHERN_ISLANDS) { 1882 Builder.defineMacro("cl_khr_byte_addressable_store"); 1883 Builder.defineMacro("cl_khr_global_int32_base_atomics"); 1884 Builder.defineMacro("cl_khr_global_int32_extended_atomics"); 1885 Builder.defineMacro("cl_khr_local_int32_base_atomics"); 1886 Builder.defineMacro("cl_khr_local_int32_extended_atomics"); 1887 } 1888 } 1889 } 1890 1891 BuiltinVaListKind getBuiltinVaListKind() const override { 1892 return TargetInfo::CharPtrBuiltinVaList; 1893 } 1894 1895 bool setCPU(const std::string &Name) override { 1896 GPU = llvm::StringSwitch<GPUKind>(Name) 1897 .Case("r600" , GK_R600) 1898 .Case("rv610", GK_R600) 1899 .Case("rv620", GK_R600) 1900 .Case("rv630", GK_R600) 1901 .Case("rv635", GK_R600) 1902 .Case("rs780", GK_R600) 1903 .Case("rs880", GK_R600) 1904 .Case("rv670", GK_R600_DOUBLE_OPS) 1905 .Case("rv710", GK_R700) 1906 .Case("rv730", GK_R700) 1907 .Case("rv740", GK_R700_DOUBLE_OPS) 1908 .Case("rv770", GK_R700_DOUBLE_OPS) 1909 .Case("palm", GK_EVERGREEN) 1910 .Case("cedar", GK_EVERGREEN) 1911 .Case("sumo", GK_EVERGREEN) 1912 .Case("sumo2", GK_EVERGREEN) 1913 .Case("redwood", GK_EVERGREEN) 1914 .Case("juniper", GK_EVERGREEN) 1915 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1916 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1917 .Case("barts", GK_NORTHERN_ISLANDS) 1918 .Case("turks", GK_NORTHERN_ISLANDS) 1919 .Case("caicos", GK_NORTHERN_ISLANDS) 1920 .Case("cayman", GK_CAYMAN) 1921 .Case("aruba", GK_CAYMAN) 1922 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1923 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1924 .Case("verde", GK_SOUTHERN_ISLANDS) 1925 .Case("oland", GK_SOUTHERN_ISLANDS) 1926 .Case("hainan", GK_SOUTHERN_ISLANDS) 1927 .Case("bonaire", GK_SEA_ISLANDS) 1928 .Case("kabini", GK_SEA_ISLANDS) 1929 .Case("kaveri", GK_SEA_ISLANDS) 1930 .Case("hawaii", GK_SEA_ISLANDS) 1931 .Case("mullins", GK_SEA_ISLANDS) 1932 .Case("tonga", GK_VOLCANIC_ISLANDS) 1933 .Case("iceland", GK_VOLCANIC_ISLANDS) 1934 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1935 .Case("fiji", GK_VOLCANIC_ISLANDS) 1936 .Case("stoney", GK_VOLCANIC_ISLANDS) 1937 .Default(GK_NONE); 1938 1939 if (GPU == GK_NONE) { 1940 return false; 1941 } 1942 1943 // Set the correct data layout 1944 switch (GPU) { 1945 case GK_NONE: 1946 case GK_R600: 1947 case GK_R700: 1948 case GK_EVERGREEN: 1949 case GK_NORTHERN_ISLANDS: 1950 resetDataLayout(DataLayoutStringR600); 1951 hasFP64 = false; 1952 hasFMAF = false; 1953 hasLDEXPF = false; 1954 break; 1955 case GK_R600_DOUBLE_OPS: 1956 case GK_R700_DOUBLE_OPS: 1957 case GK_EVERGREEN_DOUBLE_OPS: 1958 case GK_CAYMAN: 1959 resetDataLayout(DataLayoutStringR600); 1960 hasFP64 = true; 1961 hasFMAF = true; 1962 hasLDEXPF = false; 1963 break; 1964 case GK_SOUTHERN_ISLANDS: 1965 case GK_SEA_ISLANDS: 1966 case GK_VOLCANIC_ISLANDS: 1967 resetDataLayout(DataLayoutStringSI); 1968 hasFP64 = true; 1969 hasFMAF = true; 1970 hasLDEXPF = true; 1971 break; 1972 } 1973 1974 return true; 1975 } 1976 }; 1977 1978 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1979 #define BUILTIN(ID, TYPE, ATTRS) \ 1980 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1981 #include "clang/Basic/BuiltinsAMDGPU.def" 1982 }; 1983 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1984 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1985 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1986 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1987 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1988 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1989 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1990 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1991 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1992 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1993 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1994 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1995 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1996 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1997 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1998 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1999 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2000 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2001 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2002 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2003 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2004 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2005 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2006 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2007 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2008 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2009 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2010 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2011 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2012 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2013 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2014 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2015 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2016 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2017 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2018 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2019 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2020 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2021 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2022 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2023 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2024 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2025 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2026 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2027 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2028 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2029 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2030 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2031 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2032 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2033 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2034 }; 2035 2036 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2037 return llvm::makeArrayRef(GCCRegNames); 2038 } 2039 2040 // Namespace for x86 abstract base class 2041 const Builtin::Info BuiltinInfo[] = { 2042 #define BUILTIN(ID, TYPE, ATTRS) \ 2043 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2044 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2045 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2046 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2047 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2048 #include "clang/Basic/BuiltinsX86.def" 2049 }; 2050 2051 static const char* const GCCRegNames[] = { 2052 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2053 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2054 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2055 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2056 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2057 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2058 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2059 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2060 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2061 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2062 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2063 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2064 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2065 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2066 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2067 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2068 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2069 }; 2070 2071 const TargetInfo::AddlRegName AddlRegNames[] = { 2072 { { "al", "ah", "eax", "rax" }, 0 }, 2073 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2074 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2075 { { "dl", "dh", "edx", "rdx" }, 1 }, 2076 { { "esi", "rsi" }, 4 }, 2077 { { "edi", "rdi" }, 5 }, 2078 { { "esp", "rsp" }, 7 }, 2079 { { "ebp", "rbp" }, 6 }, 2080 { { "r8d", "r8w", "r8b" }, 38 }, 2081 { { "r9d", "r9w", "r9b" }, 39 }, 2082 { { "r10d", "r10w", "r10b" }, 40 }, 2083 { { "r11d", "r11w", "r11b" }, 41 }, 2084 { { "r12d", "r12w", "r12b" }, 42 }, 2085 { { "r13d", "r13w", "r13b" }, 43 }, 2086 { { "r14d", "r14w", "r14b" }, 44 }, 2087 { { "r15d", "r15w", "r15b" }, 45 }, 2088 }; 2089 2090 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2091 // most of the implementation can be shared. 2092 class X86TargetInfo : public TargetInfo { 2093 enum X86SSEEnum { 2094 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2095 } SSELevel = NoSSE; 2096 enum MMX3DNowEnum { 2097 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2098 } MMX3DNowLevel = NoMMX3DNow; 2099 enum XOPEnum { 2100 NoXOP, 2101 SSE4A, 2102 FMA4, 2103 XOP 2104 } XOPLevel = NoXOP; 2105 2106 bool HasAES = false; 2107 bool HasPCLMUL = false; 2108 bool HasLZCNT = false; 2109 bool HasRDRND = false; 2110 bool HasFSGSBASE = false; 2111 bool HasBMI = false; 2112 bool HasBMI2 = false; 2113 bool HasPOPCNT = false; 2114 bool HasRTM = false; 2115 bool HasPRFCHW = false; 2116 bool HasRDSEED = false; 2117 bool HasADX = false; 2118 bool HasTBM = false; 2119 bool HasFMA = false; 2120 bool HasF16C = false; 2121 bool HasAVX512CD = false; 2122 bool HasAVX512ER = false; 2123 bool HasAVX512PF = false; 2124 bool HasAVX512DQ = false; 2125 bool HasAVX512BW = false; 2126 bool HasAVX512VL = false; 2127 bool HasAVX512VBMI = false; 2128 bool HasAVX512IFMA = false; 2129 bool HasSHA = false; 2130 bool HasMPX = false; 2131 bool HasSGX = false; 2132 bool HasCX16 = false; 2133 bool HasFXSR = false; 2134 bool HasXSAVE = false; 2135 bool HasXSAVEOPT = false; 2136 bool HasXSAVEC = false; 2137 bool HasXSAVES = false; 2138 bool HasPKU = false; 2139 bool HasCLFLUSHOPT = false; 2140 bool HasPCOMMIT = false; 2141 bool HasCLWB = false; 2142 bool HasUMIP = false; 2143 bool HasMOVBE = false; 2144 bool HasPREFETCHWT1 = false; 2145 2146 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2147 /// 2148 /// Each enumeration represents a particular CPU supported by Clang. These 2149 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2150 enum CPUKind { 2151 CK_Generic, 2152 2153 /// \name i386 2154 /// i386-generation processors. 2155 //@{ 2156 CK_i386, 2157 //@} 2158 2159 /// \name i486 2160 /// i486-generation processors. 2161 //@{ 2162 CK_i486, 2163 CK_WinChipC6, 2164 CK_WinChip2, 2165 CK_C3, 2166 //@} 2167 2168 /// \name i586 2169 /// i586-generation processors, P5 microarchitecture based. 2170 //@{ 2171 CK_i586, 2172 CK_Pentium, 2173 CK_PentiumMMX, 2174 //@} 2175 2176 /// \name i686 2177 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2178 //@{ 2179 CK_i686, 2180 CK_PentiumPro, 2181 CK_Pentium2, 2182 CK_Pentium3, 2183 CK_Pentium3M, 2184 CK_PentiumM, 2185 CK_C3_2, 2186 2187 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2188 /// Clang however has some logic to suport this. 2189 // FIXME: Warn, deprecate, and potentially remove this. 2190 CK_Yonah, 2191 //@} 2192 2193 /// \name Netburst 2194 /// Netburst microarchitecture based processors. 2195 //@{ 2196 CK_Pentium4, 2197 CK_Pentium4M, 2198 CK_Prescott, 2199 CK_Nocona, 2200 //@} 2201 2202 /// \name Core 2203 /// Core microarchitecture based processors. 2204 //@{ 2205 CK_Core2, 2206 2207 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2208 /// codename which GCC no longer accepts as an option to -march, but Clang 2209 /// has some logic for recognizing it. 2210 // FIXME: Warn, deprecate, and potentially remove this. 2211 CK_Penryn, 2212 //@} 2213 2214 /// \name Atom 2215 /// Atom processors 2216 //@{ 2217 CK_Bonnell, 2218 CK_Silvermont, 2219 //@} 2220 2221 /// \name Nehalem 2222 /// Nehalem microarchitecture based processors. 2223 CK_Nehalem, 2224 2225 /// \name Westmere 2226 /// Westmere microarchitecture based processors. 2227 CK_Westmere, 2228 2229 /// \name Sandy Bridge 2230 /// Sandy Bridge microarchitecture based processors. 2231 CK_SandyBridge, 2232 2233 /// \name Ivy Bridge 2234 /// Ivy Bridge microarchitecture based processors. 2235 CK_IvyBridge, 2236 2237 /// \name Haswell 2238 /// Haswell microarchitecture based processors. 2239 CK_Haswell, 2240 2241 /// \name Broadwell 2242 /// Broadwell microarchitecture based processors. 2243 CK_Broadwell, 2244 2245 /// \name Skylake Client 2246 /// Skylake client microarchitecture based processors. 2247 CK_SkylakeClient, 2248 2249 /// \name Skylake Server 2250 /// Skylake server microarchitecture based processors. 2251 CK_SkylakeServer, 2252 2253 /// \name Cannonlake Client 2254 /// Cannonlake client microarchitecture based processors. 2255 CK_Cannonlake, 2256 2257 /// \name Knights Landing 2258 /// Knights Landing processor. 2259 CK_KNL, 2260 2261 /// \name Lakemont 2262 /// Lakemont microarchitecture based processors. 2263 CK_Lakemont, 2264 2265 /// \name K6 2266 /// K6 architecture processors. 2267 //@{ 2268 CK_K6, 2269 CK_K6_2, 2270 CK_K6_3, 2271 //@} 2272 2273 /// \name K7 2274 /// K7 architecture processors. 2275 //@{ 2276 CK_Athlon, 2277 CK_AthlonThunderbird, 2278 CK_Athlon4, 2279 CK_AthlonXP, 2280 CK_AthlonMP, 2281 //@} 2282 2283 /// \name K8 2284 /// K8 architecture processors. 2285 //@{ 2286 CK_Athlon64, 2287 CK_Athlon64SSE3, 2288 CK_AthlonFX, 2289 CK_K8, 2290 CK_K8SSE3, 2291 CK_Opteron, 2292 CK_OpteronSSE3, 2293 CK_AMDFAM10, 2294 //@} 2295 2296 /// \name Bobcat 2297 /// Bobcat architecture processors. 2298 //@{ 2299 CK_BTVER1, 2300 CK_BTVER2, 2301 //@} 2302 2303 /// \name Bulldozer 2304 /// Bulldozer architecture processors. 2305 //@{ 2306 CK_BDVER1, 2307 CK_BDVER2, 2308 CK_BDVER3, 2309 CK_BDVER4, 2310 //@} 2311 2312 /// This specification is deprecated and will be removed in the future. 2313 /// Users should prefer \see CK_K8. 2314 // FIXME: Warn on this when the CPU is set to it. 2315 //@{ 2316 CK_x86_64, 2317 //@} 2318 2319 /// \name Geode 2320 /// Geode processors. 2321 //@{ 2322 CK_Geode 2323 //@} 2324 } CPU = CK_Generic; 2325 2326 CPUKind getCPUKind(StringRef CPU) const { 2327 return llvm::StringSwitch<CPUKind>(CPU) 2328 .Case("i386", CK_i386) 2329 .Case("i486", CK_i486) 2330 .Case("winchip-c6", CK_WinChipC6) 2331 .Case("winchip2", CK_WinChip2) 2332 .Case("c3", CK_C3) 2333 .Case("i586", CK_i586) 2334 .Case("pentium", CK_Pentium) 2335 .Case("pentium-mmx", CK_PentiumMMX) 2336 .Case("i686", CK_i686) 2337 .Case("pentiumpro", CK_PentiumPro) 2338 .Case("pentium2", CK_Pentium2) 2339 .Case("pentium3", CK_Pentium3) 2340 .Case("pentium3m", CK_Pentium3M) 2341 .Case("pentium-m", CK_PentiumM) 2342 .Case("c3-2", CK_C3_2) 2343 .Case("yonah", CK_Yonah) 2344 .Case("pentium4", CK_Pentium4) 2345 .Case("pentium4m", CK_Pentium4M) 2346 .Case("prescott", CK_Prescott) 2347 .Case("nocona", CK_Nocona) 2348 .Case("core2", CK_Core2) 2349 .Case("penryn", CK_Penryn) 2350 .Case("bonnell", CK_Bonnell) 2351 .Case("atom", CK_Bonnell) // Legacy name. 2352 .Case("silvermont", CK_Silvermont) 2353 .Case("slm", CK_Silvermont) // Legacy name. 2354 .Case("nehalem", CK_Nehalem) 2355 .Case("corei7", CK_Nehalem) // Legacy name. 2356 .Case("westmere", CK_Westmere) 2357 .Case("sandybridge", CK_SandyBridge) 2358 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2359 .Case("ivybridge", CK_IvyBridge) 2360 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2361 .Case("haswell", CK_Haswell) 2362 .Case("core-avx2", CK_Haswell) // Legacy name. 2363 .Case("broadwell", CK_Broadwell) 2364 .Case("skylake", CK_SkylakeClient) 2365 .Case("skylake-avx512", CK_SkylakeServer) 2366 .Case("skx", CK_SkylakeServer) // Legacy name. 2367 .Case("cannonlake", CK_Cannonlake) 2368 .Case("knl", CK_KNL) 2369 .Case("lakemont", CK_Lakemont) 2370 .Case("k6", CK_K6) 2371 .Case("k6-2", CK_K6_2) 2372 .Case("k6-3", CK_K6_3) 2373 .Case("athlon", CK_Athlon) 2374 .Case("athlon-tbird", CK_AthlonThunderbird) 2375 .Case("athlon-4", CK_Athlon4) 2376 .Case("athlon-xp", CK_AthlonXP) 2377 .Case("athlon-mp", CK_AthlonMP) 2378 .Case("athlon64", CK_Athlon64) 2379 .Case("athlon64-sse3", CK_Athlon64SSE3) 2380 .Case("athlon-fx", CK_AthlonFX) 2381 .Case("k8", CK_K8) 2382 .Case("k8-sse3", CK_K8SSE3) 2383 .Case("opteron", CK_Opteron) 2384 .Case("opteron-sse3", CK_OpteronSSE3) 2385 .Case("barcelona", CK_AMDFAM10) 2386 .Case("amdfam10", CK_AMDFAM10) 2387 .Case("btver1", CK_BTVER1) 2388 .Case("btver2", CK_BTVER2) 2389 .Case("bdver1", CK_BDVER1) 2390 .Case("bdver2", CK_BDVER2) 2391 .Case("bdver3", CK_BDVER3) 2392 .Case("bdver4", CK_BDVER4) 2393 .Case("x86-64", CK_x86_64) 2394 .Case("geode", CK_Geode) 2395 .Default(CK_Generic); 2396 } 2397 2398 enum FPMathKind { 2399 FP_Default, 2400 FP_SSE, 2401 FP_387 2402 } FPMath = FP_Default; 2403 2404 public: 2405 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2406 : TargetInfo(Triple) { 2407 BigEndian = false; 2408 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2409 } 2410 unsigned getFloatEvalMethod() const override { 2411 // X87 evaluates with 80 bits "long double" precision. 2412 return SSELevel == NoSSE ? 2 : 0; 2413 } 2414 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2415 return llvm::makeArrayRef(BuiltinInfo, 2416 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2417 } 2418 ArrayRef<const char *> getGCCRegNames() const override { 2419 return llvm::makeArrayRef(GCCRegNames); 2420 } 2421 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2422 return None; 2423 } 2424 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2425 return llvm::makeArrayRef(AddlRegNames); 2426 } 2427 bool validateCpuSupports(StringRef Name) const override; 2428 bool validateAsmConstraint(const char *&Name, 2429 TargetInfo::ConstraintInfo &info) const override; 2430 2431 bool validateGlobalRegisterVariable(StringRef RegName, 2432 unsigned RegSize, 2433 bool &HasSizeMismatch) const override { 2434 // esp and ebp are the only 32-bit registers the x86 backend can currently 2435 // handle. 2436 if (RegName.equals("esp") || RegName.equals("ebp")) { 2437 // Check that the register size is 32-bit. 2438 HasSizeMismatch = RegSize != 32; 2439 return true; 2440 } 2441 2442 return false; 2443 } 2444 2445 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2446 2447 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2448 2449 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2450 2451 std::string convertConstraint(const char *&Constraint) const override; 2452 const char *getClobbers() const override { 2453 return "~{dirflag},~{fpsr},~{flags}"; 2454 } 2455 void getTargetDefines(const LangOptions &Opts, 2456 MacroBuilder &Builder) const override; 2457 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2458 bool Enabled); 2459 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2460 bool Enabled); 2461 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2462 bool Enabled); 2463 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2464 StringRef Name, bool Enabled) const override { 2465 setFeatureEnabledImpl(Features, Name, Enabled); 2466 } 2467 // This exists purely to cut down on the number of virtual calls in 2468 // initFeatureMap which calls this repeatedly. 2469 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2470 StringRef Name, bool Enabled); 2471 bool 2472 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2473 StringRef CPU, 2474 const std::vector<std::string> &FeaturesVec) const override; 2475 bool hasFeature(StringRef Feature) const override; 2476 bool handleTargetFeatures(std::vector<std::string> &Features, 2477 DiagnosticsEngine &Diags) override; 2478 StringRef getABI() const override { 2479 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2480 return "avx512"; 2481 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2482 return "avx"; 2483 if (getTriple().getArch() == llvm::Triple::x86 && 2484 MMX3DNowLevel == NoMMX3DNow) 2485 return "no-mmx"; 2486 return ""; 2487 } 2488 bool setCPU(const std::string &Name) override { 2489 CPU = getCPUKind(Name); 2490 2491 // Perform any per-CPU checks necessary to determine if this CPU is 2492 // acceptable. 2493 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2494 // invalid without explaining *why*. 2495 switch (CPU) { 2496 case CK_Generic: 2497 // No processor selected! 2498 return false; 2499 2500 case CK_i386: 2501 case CK_i486: 2502 case CK_WinChipC6: 2503 case CK_WinChip2: 2504 case CK_C3: 2505 case CK_i586: 2506 case CK_Pentium: 2507 case CK_PentiumMMX: 2508 case CK_i686: 2509 case CK_PentiumPro: 2510 case CK_Pentium2: 2511 case CK_Pentium3: 2512 case CK_Pentium3M: 2513 case CK_PentiumM: 2514 case CK_Yonah: 2515 case CK_C3_2: 2516 case CK_Pentium4: 2517 case CK_Pentium4M: 2518 case CK_Lakemont: 2519 case CK_Prescott: 2520 case CK_K6: 2521 case CK_K6_2: 2522 case CK_K6_3: 2523 case CK_Athlon: 2524 case CK_AthlonThunderbird: 2525 case CK_Athlon4: 2526 case CK_AthlonXP: 2527 case CK_AthlonMP: 2528 case CK_Geode: 2529 // Only accept certain architectures when compiling in 32-bit mode. 2530 if (getTriple().getArch() != llvm::Triple::x86) 2531 return false; 2532 2533 // Fallthrough 2534 case CK_Nocona: 2535 case CK_Core2: 2536 case CK_Penryn: 2537 case CK_Bonnell: 2538 case CK_Silvermont: 2539 case CK_Nehalem: 2540 case CK_Westmere: 2541 case CK_SandyBridge: 2542 case CK_IvyBridge: 2543 case CK_Haswell: 2544 case CK_Broadwell: 2545 case CK_SkylakeClient: 2546 case CK_SkylakeServer: 2547 case CK_Cannonlake: 2548 case CK_KNL: 2549 case CK_Athlon64: 2550 case CK_Athlon64SSE3: 2551 case CK_AthlonFX: 2552 case CK_K8: 2553 case CK_K8SSE3: 2554 case CK_Opteron: 2555 case CK_OpteronSSE3: 2556 case CK_AMDFAM10: 2557 case CK_BTVER1: 2558 case CK_BTVER2: 2559 case CK_BDVER1: 2560 case CK_BDVER2: 2561 case CK_BDVER3: 2562 case CK_BDVER4: 2563 case CK_x86_64: 2564 return true; 2565 } 2566 llvm_unreachable("Unhandled CPU kind"); 2567 } 2568 2569 bool setFPMath(StringRef Name) override; 2570 2571 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2572 // Most of the non-ARM calling conventions are i386 conventions. 2573 switch (CC) { 2574 case CC_X86ThisCall: 2575 case CC_X86FastCall: 2576 case CC_X86StdCall: 2577 case CC_X86VectorCall: 2578 case CC_C: 2579 case CC_Swift: 2580 case CC_X86Pascal: 2581 case CC_IntelOclBicc: 2582 return CCCR_OK; 2583 default: 2584 return CCCR_Warning; 2585 } 2586 } 2587 2588 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2589 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2590 } 2591 2592 bool hasSjLjLowering() const override { 2593 return true; 2594 } 2595 }; 2596 2597 bool X86TargetInfo::setFPMath(StringRef Name) { 2598 if (Name == "387") { 2599 FPMath = FP_387; 2600 return true; 2601 } 2602 if (Name == "sse") { 2603 FPMath = FP_SSE; 2604 return true; 2605 } 2606 return false; 2607 } 2608 2609 bool X86TargetInfo::initFeatureMap( 2610 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2611 const std::vector<std::string> &FeaturesVec) const { 2612 // FIXME: This *really* should not be here. 2613 // X86_64 always has SSE2. 2614 if (getTriple().getArch() == llvm::Triple::x86_64) 2615 setFeatureEnabledImpl(Features, "sse2", true); 2616 2617 const CPUKind Kind = getCPUKind(CPU); 2618 2619 // Enable X87 for all X86 processors but Lakemont. 2620 if (Kind != CK_Lakemont) 2621 setFeatureEnabledImpl(Features, "x87", true); 2622 2623 switch (Kind) { 2624 case CK_Generic: 2625 case CK_i386: 2626 case CK_i486: 2627 case CK_i586: 2628 case CK_Pentium: 2629 case CK_i686: 2630 case CK_PentiumPro: 2631 case CK_Lakemont: 2632 break; 2633 case CK_PentiumMMX: 2634 case CK_Pentium2: 2635 case CK_K6: 2636 case CK_WinChipC6: 2637 setFeatureEnabledImpl(Features, "mmx", true); 2638 break; 2639 case CK_Pentium3: 2640 case CK_Pentium3M: 2641 case CK_C3_2: 2642 setFeatureEnabledImpl(Features, "sse", true); 2643 setFeatureEnabledImpl(Features, "fxsr", true); 2644 break; 2645 case CK_PentiumM: 2646 case CK_Pentium4: 2647 case CK_Pentium4M: 2648 case CK_x86_64: 2649 setFeatureEnabledImpl(Features, "sse2", true); 2650 setFeatureEnabledImpl(Features, "fxsr", true); 2651 break; 2652 case CK_Yonah: 2653 case CK_Prescott: 2654 case CK_Nocona: 2655 setFeatureEnabledImpl(Features, "sse3", true); 2656 setFeatureEnabledImpl(Features, "fxsr", true); 2657 setFeatureEnabledImpl(Features, "cx16", true); 2658 break; 2659 case CK_Core2: 2660 case CK_Bonnell: 2661 setFeatureEnabledImpl(Features, "ssse3", true); 2662 setFeatureEnabledImpl(Features, "fxsr", true); 2663 setFeatureEnabledImpl(Features, "cx16", true); 2664 break; 2665 case CK_Penryn: 2666 setFeatureEnabledImpl(Features, "sse4.1", true); 2667 setFeatureEnabledImpl(Features, "fxsr", true); 2668 setFeatureEnabledImpl(Features, "cx16", true); 2669 break; 2670 case CK_Cannonlake: 2671 setFeatureEnabledImpl(Features, "avx512ifma", true); 2672 setFeatureEnabledImpl(Features, "avx512vbmi", true); 2673 setFeatureEnabledImpl(Features, "sha", true); 2674 setFeatureEnabledImpl(Features, "umip", true); 2675 // FALLTHROUGH 2676 case CK_SkylakeServer: 2677 setFeatureEnabledImpl(Features, "avx512f", true); 2678 setFeatureEnabledImpl(Features, "avx512cd", true); 2679 setFeatureEnabledImpl(Features, "avx512dq", true); 2680 setFeatureEnabledImpl(Features, "avx512bw", true); 2681 setFeatureEnabledImpl(Features, "avx512vl", true); 2682 setFeatureEnabledImpl(Features, "pku", true); 2683 setFeatureEnabledImpl(Features, "pcommit", true); 2684 setFeatureEnabledImpl(Features, "clwb", true); 2685 // FALLTHROUGH 2686 case CK_SkylakeClient: 2687 setFeatureEnabledImpl(Features, "xsavec", true); 2688 setFeatureEnabledImpl(Features, "xsaves", true); 2689 setFeatureEnabledImpl(Features, "mpx", true); 2690 setFeatureEnabledImpl(Features, "sgx", true); 2691 setFeatureEnabledImpl(Features, "clflushopt", true); 2692 // FALLTHROUGH 2693 case CK_Broadwell: 2694 setFeatureEnabledImpl(Features, "rdseed", true); 2695 setFeatureEnabledImpl(Features, "adx", true); 2696 // FALLTHROUGH 2697 case CK_Haswell: 2698 setFeatureEnabledImpl(Features, "avx2", true); 2699 setFeatureEnabledImpl(Features, "lzcnt", true); 2700 setFeatureEnabledImpl(Features, "bmi", true); 2701 setFeatureEnabledImpl(Features, "bmi2", true); 2702 setFeatureEnabledImpl(Features, "rtm", true); 2703 setFeatureEnabledImpl(Features, "fma", true); 2704 setFeatureEnabledImpl(Features, "movbe", true); 2705 // FALLTHROUGH 2706 case CK_IvyBridge: 2707 setFeatureEnabledImpl(Features, "rdrnd", true); 2708 setFeatureEnabledImpl(Features, "f16c", true); 2709 setFeatureEnabledImpl(Features, "fsgsbase", true); 2710 // FALLTHROUGH 2711 case CK_SandyBridge: 2712 setFeatureEnabledImpl(Features, "avx", true); 2713 setFeatureEnabledImpl(Features, "xsave", true); 2714 setFeatureEnabledImpl(Features, "xsaveopt", true); 2715 // FALLTHROUGH 2716 case CK_Westmere: 2717 case CK_Silvermont: 2718 setFeatureEnabledImpl(Features, "aes", true); 2719 setFeatureEnabledImpl(Features, "pclmul", true); 2720 // FALLTHROUGH 2721 case CK_Nehalem: 2722 setFeatureEnabledImpl(Features, "sse4.2", true); 2723 setFeatureEnabledImpl(Features, "fxsr", true); 2724 setFeatureEnabledImpl(Features, "cx16", true); 2725 break; 2726 case CK_KNL: 2727 setFeatureEnabledImpl(Features, "avx512f", true); 2728 setFeatureEnabledImpl(Features, "avx512cd", true); 2729 setFeatureEnabledImpl(Features, "avx512er", true); 2730 setFeatureEnabledImpl(Features, "avx512pf", true); 2731 setFeatureEnabledImpl(Features, "prefetchwt1", true); 2732 setFeatureEnabledImpl(Features, "fxsr", true); 2733 setFeatureEnabledImpl(Features, "rdseed", true); 2734 setFeatureEnabledImpl(Features, "adx", true); 2735 setFeatureEnabledImpl(Features, "lzcnt", true); 2736 setFeatureEnabledImpl(Features, "bmi", true); 2737 setFeatureEnabledImpl(Features, "bmi2", true); 2738 setFeatureEnabledImpl(Features, "rtm", true); 2739 setFeatureEnabledImpl(Features, "fma", true); 2740 setFeatureEnabledImpl(Features, "rdrnd", true); 2741 setFeatureEnabledImpl(Features, "f16c", true); 2742 setFeatureEnabledImpl(Features, "fsgsbase", true); 2743 setFeatureEnabledImpl(Features, "aes", true); 2744 setFeatureEnabledImpl(Features, "pclmul", true); 2745 setFeatureEnabledImpl(Features, "cx16", true); 2746 setFeatureEnabledImpl(Features, "xsaveopt", true); 2747 setFeatureEnabledImpl(Features, "xsave", true); 2748 setFeatureEnabledImpl(Features, "movbe", true); 2749 break; 2750 case CK_K6_2: 2751 case CK_K6_3: 2752 case CK_WinChip2: 2753 case CK_C3: 2754 setFeatureEnabledImpl(Features, "3dnow", true); 2755 break; 2756 case CK_Athlon: 2757 case CK_AthlonThunderbird: 2758 case CK_Geode: 2759 setFeatureEnabledImpl(Features, "3dnowa", true); 2760 break; 2761 case CK_Athlon4: 2762 case CK_AthlonXP: 2763 case CK_AthlonMP: 2764 setFeatureEnabledImpl(Features, "sse", true); 2765 setFeatureEnabledImpl(Features, "3dnowa", true); 2766 setFeatureEnabledImpl(Features, "fxsr", true); 2767 break; 2768 case CK_K8: 2769 case CK_Opteron: 2770 case CK_Athlon64: 2771 case CK_AthlonFX: 2772 setFeatureEnabledImpl(Features, "sse2", true); 2773 setFeatureEnabledImpl(Features, "3dnowa", true); 2774 setFeatureEnabledImpl(Features, "fxsr", true); 2775 break; 2776 case CK_AMDFAM10: 2777 setFeatureEnabledImpl(Features, "sse4a", true); 2778 setFeatureEnabledImpl(Features, "lzcnt", true); 2779 setFeatureEnabledImpl(Features, "popcnt", true); 2780 // FALLTHROUGH 2781 case CK_K8SSE3: 2782 case CK_OpteronSSE3: 2783 case CK_Athlon64SSE3: 2784 setFeatureEnabledImpl(Features, "sse3", true); 2785 setFeatureEnabledImpl(Features, "3dnowa", true); 2786 setFeatureEnabledImpl(Features, "fxsr", true); 2787 break; 2788 case CK_BTVER2: 2789 setFeatureEnabledImpl(Features, "avx", true); 2790 setFeatureEnabledImpl(Features, "aes", true); 2791 setFeatureEnabledImpl(Features, "pclmul", true); 2792 setFeatureEnabledImpl(Features, "bmi", true); 2793 setFeatureEnabledImpl(Features, "f16c", true); 2794 setFeatureEnabledImpl(Features, "xsaveopt", true); 2795 // FALLTHROUGH 2796 case CK_BTVER1: 2797 setFeatureEnabledImpl(Features, "ssse3", true); 2798 setFeatureEnabledImpl(Features, "sse4a", true); 2799 setFeatureEnabledImpl(Features, "lzcnt", true); 2800 setFeatureEnabledImpl(Features, "popcnt", true); 2801 setFeatureEnabledImpl(Features, "prfchw", true); 2802 setFeatureEnabledImpl(Features, "cx16", true); 2803 setFeatureEnabledImpl(Features, "fxsr", true); 2804 break; 2805 case CK_BDVER4: 2806 setFeatureEnabledImpl(Features, "avx2", true); 2807 setFeatureEnabledImpl(Features, "bmi2", true); 2808 // FALLTHROUGH 2809 case CK_BDVER3: 2810 setFeatureEnabledImpl(Features, "fsgsbase", true); 2811 setFeatureEnabledImpl(Features, "xsaveopt", true); 2812 // FALLTHROUGH 2813 case CK_BDVER2: 2814 setFeatureEnabledImpl(Features, "bmi", true); 2815 setFeatureEnabledImpl(Features, "fma", true); 2816 setFeatureEnabledImpl(Features, "f16c", true); 2817 setFeatureEnabledImpl(Features, "tbm", true); 2818 // FALLTHROUGH 2819 case CK_BDVER1: 2820 // xop implies avx, sse4a and fma4. 2821 setFeatureEnabledImpl(Features, "xop", true); 2822 setFeatureEnabledImpl(Features, "lzcnt", true); 2823 setFeatureEnabledImpl(Features, "aes", true); 2824 setFeatureEnabledImpl(Features, "pclmul", true); 2825 setFeatureEnabledImpl(Features, "prfchw", true); 2826 setFeatureEnabledImpl(Features, "cx16", true); 2827 setFeatureEnabledImpl(Features, "fxsr", true); 2828 setFeatureEnabledImpl(Features, "xsave", true); 2829 break; 2830 } 2831 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 2832 return false; 2833 2834 // Can't do this earlier because we need to be able to explicitly enable 2835 // or disable these features and the things that they depend upon. 2836 2837 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2838 auto I = Features.find("sse4.2"); 2839 if (I != Features.end() && I->getValue() && 2840 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 2841 FeaturesVec.end()) 2842 Features["popcnt"] = true; 2843 2844 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2845 I = Features.find("3dnow"); 2846 if (I != Features.end() && I->getValue() && 2847 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 2848 FeaturesVec.end()) 2849 Features["prfchw"] = true; 2850 2851 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2852 // then enable MMX. 2853 I = Features.find("sse"); 2854 if (I != Features.end() && I->getValue() && 2855 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 2856 FeaturesVec.end()) 2857 Features["mmx"] = true; 2858 2859 return true; 2860 } 2861 2862 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2863 X86SSEEnum Level, bool Enabled) { 2864 if (Enabled) { 2865 switch (Level) { 2866 case AVX512F: 2867 Features["avx512f"] = true; 2868 case AVX2: 2869 Features["avx2"] = true; 2870 case AVX: 2871 Features["avx"] = true; 2872 Features["xsave"] = true; 2873 case SSE42: 2874 Features["sse4.2"] = true; 2875 case SSE41: 2876 Features["sse4.1"] = true; 2877 case SSSE3: 2878 Features["ssse3"] = true; 2879 case SSE3: 2880 Features["sse3"] = true; 2881 case SSE2: 2882 Features["sse2"] = true; 2883 case SSE1: 2884 Features["sse"] = true; 2885 case NoSSE: 2886 break; 2887 } 2888 return; 2889 } 2890 2891 switch (Level) { 2892 case NoSSE: 2893 case SSE1: 2894 Features["sse"] = false; 2895 case SSE2: 2896 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2897 Features["sha"] = false; 2898 case SSE3: 2899 Features["sse3"] = false; 2900 setXOPLevel(Features, NoXOP, false); 2901 case SSSE3: 2902 Features["ssse3"] = false; 2903 case SSE41: 2904 Features["sse4.1"] = false; 2905 case SSE42: 2906 Features["sse4.2"] = false; 2907 case AVX: 2908 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 2909 Features["xsaveopt"] = false; 2910 setXOPLevel(Features, FMA4, false); 2911 case AVX2: 2912 Features["avx2"] = false; 2913 case AVX512F: 2914 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2915 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2916 Features["avx512vl"] = Features["avx512vbmi"] = 2917 Features["avx512ifma"] = false; 2918 } 2919 } 2920 2921 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2922 MMX3DNowEnum Level, bool Enabled) { 2923 if (Enabled) { 2924 switch (Level) { 2925 case AMD3DNowAthlon: 2926 Features["3dnowa"] = true; 2927 case AMD3DNow: 2928 Features["3dnow"] = true; 2929 case MMX: 2930 Features["mmx"] = true; 2931 case NoMMX3DNow: 2932 break; 2933 } 2934 return; 2935 } 2936 2937 switch (Level) { 2938 case NoMMX3DNow: 2939 case MMX: 2940 Features["mmx"] = false; 2941 case AMD3DNow: 2942 Features["3dnow"] = false; 2943 case AMD3DNowAthlon: 2944 Features["3dnowa"] = false; 2945 } 2946 } 2947 2948 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2949 bool Enabled) { 2950 if (Enabled) { 2951 switch (Level) { 2952 case XOP: 2953 Features["xop"] = true; 2954 case FMA4: 2955 Features["fma4"] = true; 2956 setSSELevel(Features, AVX, true); 2957 case SSE4A: 2958 Features["sse4a"] = true; 2959 setSSELevel(Features, SSE3, true); 2960 case NoXOP: 2961 break; 2962 } 2963 return; 2964 } 2965 2966 switch (Level) { 2967 case NoXOP: 2968 case SSE4A: 2969 Features["sse4a"] = false; 2970 case FMA4: 2971 Features["fma4"] = false; 2972 case XOP: 2973 Features["xop"] = false; 2974 } 2975 } 2976 2977 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2978 StringRef Name, bool Enabled) { 2979 // This is a bit of a hack to deal with the sse4 target feature when used 2980 // as part of the target attribute. We handle sse4 correctly everywhere 2981 // else. See below for more information on how we handle the sse4 options. 2982 if (Name != "sse4") 2983 Features[Name] = Enabled; 2984 2985 if (Name == "mmx") { 2986 setMMXLevel(Features, MMX, Enabled); 2987 } else if (Name == "sse") { 2988 setSSELevel(Features, SSE1, Enabled); 2989 } else if (Name == "sse2") { 2990 setSSELevel(Features, SSE2, Enabled); 2991 } else if (Name == "sse3") { 2992 setSSELevel(Features, SSE3, Enabled); 2993 } else if (Name == "ssse3") { 2994 setSSELevel(Features, SSSE3, Enabled); 2995 } else if (Name == "sse4.2") { 2996 setSSELevel(Features, SSE42, Enabled); 2997 } else if (Name == "sse4.1") { 2998 setSSELevel(Features, SSE41, Enabled); 2999 } else if (Name == "3dnow") { 3000 setMMXLevel(Features, AMD3DNow, Enabled); 3001 } else if (Name == "3dnowa") { 3002 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3003 } else if (Name == "aes") { 3004 if (Enabled) 3005 setSSELevel(Features, SSE2, Enabled); 3006 } else if (Name == "pclmul") { 3007 if (Enabled) 3008 setSSELevel(Features, SSE2, Enabled); 3009 } else if (Name == "avx") { 3010 setSSELevel(Features, AVX, Enabled); 3011 } else if (Name == "avx2") { 3012 setSSELevel(Features, AVX2, Enabled); 3013 } else if (Name == "avx512f") { 3014 setSSELevel(Features, AVX512F, Enabled); 3015 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3016 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3017 Name == "avx512vbmi" || Name == "avx512ifma") { 3018 if (Enabled) 3019 setSSELevel(Features, AVX512F, Enabled); 3020 } else if (Name == "fma") { 3021 if (Enabled) 3022 setSSELevel(Features, AVX, Enabled); 3023 } else if (Name == "fma4") { 3024 setXOPLevel(Features, FMA4, Enabled); 3025 } else if (Name == "xop") { 3026 setXOPLevel(Features, XOP, Enabled); 3027 } else if (Name == "sse4a") { 3028 setXOPLevel(Features, SSE4A, Enabled); 3029 } else if (Name == "f16c") { 3030 if (Enabled) 3031 setSSELevel(Features, AVX, Enabled); 3032 } else if (Name == "sha") { 3033 if (Enabled) 3034 setSSELevel(Features, SSE2, Enabled); 3035 } else if (Name == "sse4") { 3036 // We can get here via the __target__ attribute since that's not controlled 3037 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3038 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3039 // disabled. 3040 if (Enabled) 3041 setSSELevel(Features, SSE42, Enabled); 3042 else 3043 setSSELevel(Features, SSE41, Enabled); 3044 } else if (Name == "xsave") { 3045 if (!Enabled) 3046 Features["xsaveopt"] = false; 3047 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3048 if (Enabled) 3049 Features["xsave"] = true; 3050 } 3051 } 3052 3053 /// handleTargetFeatures - Perform initialization based on the user 3054 /// configured set of features. 3055 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3056 DiagnosticsEngine &Diags) { 3057 for (const auto &Feature : Features) { 3058 if (Feature[0] != '+') 3059 continue; 3060 3061 if (Feature == "+aes") { 3062 HasAES = true; 3063 } else if (Feature == "+pclmul") { 3064 HasPCLMUL = true; 3065 } else if (Feature == "+lzcnt") { 3066 HasLZCNT = true; 3067 } else if (Feature == "+rdrnd") { 3068 HasRDRND = true; 3069 } else if (Feature == "+fsgsbase") { 3070 HasFSGSBASE = true; 3071 } else if (Feature == "+bmi") { 3072 HasBMI = true; 3073 } else if (Feature == "+bmi2") { 3074 HasBMI2 = true; 3075 } else if (Feature == "+popcnt") { 3076 HasPOPCNT = true; 3077 } else if (Feature == "+rtm") { 3078 HasRTM = true; 3079 } else if (Feature == "+prfchw") { 3080 HasPRFCHW = true; 3081 } else if (Feature == "+rdseed") { 3082 HasRDSEED = true; 3083 } else if (Feature == "+adx") { 3084 HasADX = true; 3085 } else if (Feature == "+tbm") { 3086 HasTBM = true; 3087 } else if (Feature == "+fma") { 3088 HasFMA = true; 3089 } else if (Feature == "+f16c") { 3090 HasF16C = true; 3091 } else if (Feature == "+avx512cd") { 3092 HasAVX512CD = true; 3093 } else if (Feature == "+avx512er") { 3094 HasAVX512ER = true; 3095 } else if (Feature == "+avx512pf") { 3096 HasAVX512PF = true; 3097 } else if (Feature == "+avx512dq") { 3098 HasAVX512DQ = true; 3099 } else if (Feature == "+avx512bw") { 3100 HasAVX512BW = true; 3101 } else if (Feature == "+avx512vl") { 3102 HasAVX512VL = true; 3103 } else if (Feature == "+avx512vbmi") { 3104 HasAVX512VBMI = true; 3105 } else if (Feature == "+avx512ifma") { 3106 HasAVX512IFMA = true; 3107 } else if (Feature == "+sha") { 3108 HasSHA = true; 3109 } else if (Feature == "+mpx") { 3110 HasMPX = true; 3111 } else if (Feature == "+movbe") { 3112 HasMOVBE = true; 3113 } else if (Feature == "+sgx") { 3114 HasSGX = true; 3115 } else if (Feature == "+cx16") { 3116 HasCX16 = true; 3117 } else if (Feature == "+fxsr") { 3118 HasFXSR = true; 3119 } else if (Feature == "+xsave") { 3120 HasXSAVE = true; 3121 } else if (Feature == "+xsaveopt") { 3122 HasXSAVEOPT = true; 3123 } else if (Feature == "+xsavec") { 3124 HasXSAVEC = true; 3125 } else if (Feature == "+xsaves") { 3126 HasXSAVES = true; 3127 } else if (Feature == "+pku") { 3128 HasPKU = true; 3129 } else if (Feature == "+clflushopt") { 3130 HasCLFLUSHOPT = true; 3131 } else if (Feature == "+pcommit") { 3132 HasPCOMMIT = true; 3133 } else if (Feature == "+clwb") { 3134 HasCLWB = true; 3135 } else if (Feature == "+umip") { 3136 HasUMIP = true; 3137 } else if (Feature == "+prefetchwt1") { 3138 HasPREFETCHWT1 = true; 3139 } 3140 3141 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3142 .Case("+avx512f", AVX512F) 3143 .Case("+avx2", AVX2) 3144 .Case("+avx", AVX) 3145 .Case("+sse4.2", SSE42) 3146 .Case("+sse4.1", SSE41) 3147 .Case("+ssse3", SSSE3) 3148 .Case("+sse3", SSE3) 3149 .Case("+sse2", SSE2) 3150 .Case("+sse", SSE1) 3151 .Default(NoSSE); 3152 SSELevel = std::max(SSELevel, Level); 3153 3154 MMX3DNowEnum ThreeDNowLevel = 3155 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3156 .Case("+3dnowa", AMD3DNowAthlon) 3157 .Case("+3dnow", AMD3DNow) 3158 .Case("+mmx", MMX) 3159 .Default(NoMMX3DNow); 3160 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3161 3162 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3163 .Case("+xop", XOP) 3164 .Case("+fma4", FMA4) 3165 .Case("+sse4a", SSE4A) 3166 .Default(NoXOP); 3167 XOPLevel = std::max(XOPLevel, XLevel); 3168 } 3169 3170 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3171 // matches the selected sse level. 3172 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3173 (FPMath == FP_387 && SSELevel >= SSE1)) { 3174 Diags.Report(diag::err_target_unsupported_fpmath) << 3175 (FPMath == FP_SSE ? "sse" : "387"); 3176 return false; 3177 } 3178 3179 SimdDefaultAlign = 3180 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3181 return true; 3182 } 3183 3184 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3185 /// definitions for this particular subtarget. 3186 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3187 MacroBuilder &Builder) const { 3188 // Target identification. 3189 if (getTriple().getArch() == llvm::Triple::x86_64) { 3190 Builder.defineMacro("__amd64__"); 3191 Builder.defineMacro("__amd64"); 3192 Builder.defineMacro("__x86_64"); 3193 Builder.defineMacro("__x86_64__"); 3194 if (getTriple().getArchName() == "x86_64h") { 3195 Builder.defineMacro("__x86_64h"); 3196 Builder.defineMacro("__x86_64h__"); 3197 } 3198 } else { 3199 DefineStd(Builder, "i386", Opts); 3200 } 3201 3202 // Subtarget options. 3203 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3204 // truly should be based on -mtune options. 3205 switch (CPU) { 3206 case CK_Generic: 3207 break; 3208 case CK_i386: 3209 // The rest are coming from the i386 define above. 3210 Builder.defineMacro("__tune_i386__"); 3211 break; 3212 case CK_i486: 3213 case CK_WinChipC6: 3214 case CK_WinChip2: 3215 case CK_C3: 3216 defineCPUMacros(Builder, "i486"); 3217 break; 3218 case CK_PentiumMMX: 3219 Builder.defineMacro("__pentium_mmx__"); 3220 Builder.defineMacro("__tune_pentium_mmx__"); 3221 // Fallthrough 3222 case CK_i586: 3223 case CK_Pentium: 3224 defineCPUMacros(Builder, "i586"); 3225 defineCPUMacros(Builder, "pentium"); 3226 break; 3227 case CK_Pentium3: 3228 case CK_Pentium3M: 3229 case CK_PentiumM: 3230 Builder.defineMacro("__tune_pentium3__"); 3231 // Fallthrough 3232 case CK_Pentium2: 3233 case CK_C3_2: 3234 Builder.defineMacro("__tune_pentium2__"); 3235 // Fallthrough 3236 case CK_PentiumPro: 3237 Builder.defineMacro("__tune_i686__"); 3238 Builder.defineMacro("__tune_pentiumpro__"); 3239 // Fallthrough 3240 case CK_i686: 3241 Builder.defineMacro("__i686"); 3242 Builder.defineMacro("__i686__"); 3243 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3244 Builder.defineMacro("__pentiumpro"); 3245 Builder.defineMacro("__pentiumpro__"); 3246 break; 3247 case CK_Pentium4: 3248 case CK_Pentium4M: 3249 defineCPUMacros(Builder, "pentium4"); 3250 break; 3251 case CK_Yonah: 3252 case CK_Prescott: 3253 case CK_Nocona: 3254 defineCPUMacros(Builder, "nocona"); 3255 break; 3256 case CK_Core2: 3257 case CK_Penryn: 3258 defineCPUMacros(Builder, "core2"); 3259 break; 3260 case CK_Bonnell: 3261 defineCPUMacros(Builder, "atom"); 3262 break; 3263 case CK_Silvermont: 3264 defineCPUMacros(Builder, "slm"); 3265 break; 3266 case CK_Nehalem: 3267 case CK_Westmere: 3268 case CK_SandyBridge: 3269 case CK_IvyBridge: 3270 case CK_Haswell: 3271 case CK_Broadwell: 3272 case CK_SkylakeClient: 3273 // FIXME: Historically, we defined this legacy name, it would be nice to 3274 // remove it at some point. We've never exposed fine-grained names for 3275 // recent primary x86 CPUs, and we should keep it that way. 3276 defineCPUMacros(Builder, "corei7"); 3277 break; 3278 case CK_SkylakeServer: 3279 defineCPUMacros(Builder, "skx"); 3280 break; 3281 case CK_Cannonlake: 3282 break; 3283 case CK_KNL: 3284 defineCPUMacros(Builder, "knl"); 3285 break; 3286 case CK_Lakemont: 3287 Builder.defineMacro("__tune_lakemont__"); 3288 break; 3289 case CK_K6_2: 3290 Builder.defineMacro("__k6_2__"); 3291 Builder.defineMacro("__tune_k6_2__"); 3292 // Fallthrough 3293 case CK_K6_3: 3294 if (CPU != CK_K6_2) { // In case of fallthrough 3295 // FIXME: GCC may be enabling these in cases where some other k6 3296 // architecture is specified but -m3dnow is explicitly provided. The 3297 // exact semantics need to be determined and emulated here. 3298 Builder.defineMacro("__k6_3__"); 3299 Builder.defineMacro("__tune_k6_3__"); 3300 } 3301 // Fallthrough 3302 case CK_K6: 3303 defineCPUMacros(Builder, "k6"); 3304 break; 3305 case CK_Athlon: 3306 case CK_AthlonThunderbird: 3307 case CK_Athlon4: 3308 case CK_AthlonXP: 3309 case CK_AthlonMP: 3310 defineCPUMacros(Builder, "athlon"); 3311 if (SSELevel != NoSSE) { 3312 Builder.defineMacro("__athlon_sse__"); 3313 Builder.defineMacro("__tune_athlon_sse__"); 3314 } 3315 break; 3316 case CK_K8: 3317 case CK_K8SSE3: 3318 case CK_x86_64: 3319 case CK_Opteron: 3320 case CK_OpteronSSE3: 3321 case CK_Athlon64: 3322 case CK_Athlon64SSE3: 3323 case CK_AthlonFX: 3324 defineCPUMacros(Builder, "k8"); 3325 break; 3326 case CK_AMDFAM10: 3327 defineCPUMacros(Builder, "amdfam10"); 3328 break; 3329 case CK_BTVER1: 3330 defineCPUMacros(Builder, "btver1"); 3331 break; 3332 case CK_BTVER2: 3333 defineCPUMacros(Builder, "btver2"); 3334 break; 3335 case CK_BDVER1: 3336 defineCPUMacros(Builder, "bdver1"); 3337 break; 3338 case CK_BDVER2: 3339 defineCPUMacros(Builder, "bdver2"); 3340 break; 3341 case CK_BDVER3: 3342 defineCPUMacros(Builder, "bdver3"); 3343 break; 3344 case CK_BDVER4: 3345 defineCPUMacros(Builder, "bdver4"); 3346 break; 3347 case CK_Geode: 3348 defineCPUMacros(Builder, "geode"); 3349 break; 3350 } 3351 3352 // Target properties. 3353 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3354 3355 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3356 // functions in glibc header files that use FP Stack inline asm which the 3357 // backend can't deal with (PR879). 3358 Builder.defineMacro("__NO_MATH_INLINES"); 3359 3360 if (HasAES) 3361 Builder.defineMacro("__AES__"); 3362 3363 if (HasPCLMUL) 3364 Builder.defineMacro("__PCLMUL__"); 3365 3366 if (HasLZCNT) 3367 Builder.defineMacro("__LZCNT__"); 3368 3369 if (HasRDRND) 3370 Builder.defineMacro("__RDRND__"); 3371 3372 if (HasFSGSBASE) 3373 Builder.defineMacro("__FSGSBASE__"); 3374 3375 if (HasBMI) 3376 Builder.defineMacro("__BMI__"); 3377 3378 if (HasBMI2) 3379 Builder.defineMacro("__BMI2__"); 3380 3381 if (HasPOPCNT) 3382 Builder.defineMacro("__POPCNT__"); 3383 3384 if (HasRTM) 3385 Builder.defineMacro("__RTM__"); 3386 3387 if (HasPRFCHW) 3388 Builder.defineMacro("__PRFCHW__"); 3389 3390 if (HasRDSEED) 3391 Builder.defineMacro("__RDSEED__"); 3392 3393 if (HasADX) 3394 Builder.defineMacro("__ADX__"); 3395 3396 if (HasTBM) 3397 Builder.defineMacro("__TBM__"); 3398 3399 switch (XOPLevel) { 3400 case XOP: 3401 Builder.defineMacro("__XOP__"); 3402 case FMA4: 3403 Builder.defineMacro("__FMA4__"); 3404 case SSE4A: 3405 Builder.defineMacro("__SSE4A__"); 3406 case NoXOP: 3407 break; 3408 } 3409 3410 if (HasFMA) 3411 Builder.defineMacro("__FMA__"); 3412 3413 if (HasF16C) 3414 Builder.defineMacro("__F16C__"); 3415 3416 if (HasAVX512CD) 3417 Builder.defineMacro("__AVX512CD__"); 3418 if (HasAVX512ER) 3419 Builder.defineMacro("__AVX512ER__"); 3420 if (HasAVX512PF) 3421 Builder.defineMacro("__AVX512PF__"); 3422 if (HasAVX512DQ) 3423 Builder.defineMacro("__AVX512DQ__"); 3424 if (HasAVX512BW) 3425 Builder.defineMacro("__AVX512BW__"); 3426 if (HasAVX512VL) 3427 Builder.defineMacro("__AVX512VL__"); 3428 if (HasAVX512VBMI) 3429 Builder.defineMacro("__AVX512VBMI__"); 3430 if (HasAVX512IFMA) 3431 Builder.defineMacro("__AVX512IFMA__"); 3432 3433 if (HasSHA) 3434 Builder.defineMacro("__SHA__"); 3435 3436 if (HasFXSR) 3437 Builder.defineMacro("__FXSR__"); 3438 if (HasXSAVE) 3439 Builder.defineMacro("__XSAVE__"); 3440 if (HasXSAVEOPT) 3441 Builder.defineMacro("__XSAVEOPT__"); 3442 if (HasXSAVEC) 3443 Builder.defineMacro("__XSAVEC__"); 3444 if (HasXSAVES) 3445 Builder.defineMacro("__XSAVES__"); 3446 if (HasPKU) 3447 Builder.defineMacro("__PKU__"); 3448 if (HasCX16) 3449 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3450 3451 // Each case falls through to the previous one here. 3452 switch (SSELevel) { 3453 case AVX512F: 3454 Builder.defineMacro("__AVX512F__"); 3455 case AVX2: 3456 Builder.defineMacro("__AVX2__"); 3457 case AVX: 3458 Builder.defineMacro("__AVX__"); 3459 case SSE42: 3460 Builder.defineMacro("__SSE4_2__"); 3461 case SSE41: 3462 Builder.defineMacro("__SSE4_1__"); 3463 case SSSE3: 3464 Builder.defineMacro("__SSSE3__"); 3465 case SSE3: 3466 Builder.defineMacro("__SSE3__"); 3467 case SSE2: 3468 Builder.defineMacro("__SSE2__"); 3469 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3470 case SSE1: 3471 Builder.defineMacro("__SSE__"); 3472 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3473 case NoSSE: 3474 break; 3475 } 3476 3477 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3478 switch (SSELevel) { 3479 case AVX512F: 3480 case AVX2: 3481 case AVX: 3482 case SSE42: 3483 case SSE41: 3484 case SSSE3: 3485 case SSE3: 3486 case SSE2: 3487 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3488 break; 3489 case SSE1: 3490 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3491 break; 3492 default: 3493 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3494 } 3495 } 3496 3497 // Each case falls through to the previous one here. 3498 switch (MMX3DNowLevel) { 3499 case AMD3DNowAthlon: 3500 Builder.defineMacro("__3dNOW_A__"); 3501 case AMD3DNow: 3502 Builder.defineMacro("__3dNOW__"); 3503 case MMX: 3504 Builder.defineMacro("__MMX__"); 3505 case NoMMX3DNow: 3506 break; 3507 } 3508 3509 if (CPU >= CK_i486) { 3510 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3511 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3512 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3513 } 3514 if (CPU >= CK_i586) 3515 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3516 } 3517 3518 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3519 return llvm::StringSwitch<bool>(Feature) 3520 .Case("aes", HasAES) 3521 .Case("avx", SSELevel >= AVX) 3522 .Case("avx2", SSELevel >= AVX2) 3523 .Case("avx512f", SSELevel >= AVX512F) 3524 .Case("avx512cd", HasAVX512CD) 3525 .Case("avx512er", HasAVX512ER) 3526 .Case("avx512pf", HasAVX512PF) 3527 .Case("avx512dq", HasAVX512DQ) 3528 .Case("avx512bw", HasAVX512BW) 3529 .Case("avx512vl", HasAVX512VL) 3530 .Case("avx512vbmi", HasAVX512VBMI) 3531 .Case("avx512ifma", HasAVX512IFMA) 3532 .Case("bmi", HasBMI) 3533 .Case("bmi2", HasBMI2) 3534 .Case("clflushopt", HasCLFLUSHOPT) 3535 .Case("clwb", HasCLWB) 3536 .Case("cx16", HasCX16) 3537 .Case("f16c", HasF16C) 3538 .Case("fma", HasFMA) 3539 .Case("fma4", XOPLevel >= FMA4) 3540 .Case("fsgsbase", HasFSGSBASE) 3541 .Case("fxsr", HasFXSR) 3542 .Case("lzcnt", HasLZCNT) 3543 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3544 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3545 .Case("mmx", MMX3DNowLevel >= MMX) 3546 .Case("movbe", HasMOVBE) 3547 .Case("mpx", HasMPX) 3548 .Case("pclmul", HasPCLMUL) 3549 .Case("pcommit", HasPCOMMIT) 3550 .Case("pku", HasPKU) 3551 .Case("popcnt", HasPOPCNT) 3552 .Case("prefetchwt1", HasPREFETCHWT1) 3553 .Case("prfchw", HasPRFCHW) 3554 .Case("rdrnd", HasRDRND) 3555 .Case("rdseed", HasRDSEED) 3556 .Case("rtm", HasRTM) 3557 .Case("sgx", HasSGX) 3558 .Case("sha", HasSHA) 3559 .Case("sse", SSELevel >= SSE1) 3560 .Case("sse2", SSELevel >= SSE2) 3561 .Case("sse3", SSELevel >= SSE3) 3562 .Case("ssse3", SSELevel >= SSSE3) 3563 .Case("sse4.1", SSELevel >= SSE41) 3564 .Case("sse4.2", SSELevel >= SSE42) 3565 .Case("sse4a", XOPLevel >= SSE4A) 3566 .Case("tbm", HasTBM) 3567 .Case("umip", HasUMIP) 3568 .Case("x86", true) 3569 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3570 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3571 .Case("xop", XOPLevel >= XOP) 3572 .Case("xsave", HasXSAVE) 3573 .Case("xsavec", HasXSAVEC) 3574 .Case("xsaves", HasXSAVES) 3575 .Case("xsaveopt", HasXSAVEOPT) 3576 .Default(false); 3577 } 3578 3579 // We can't use a generic validation scheme for the features accepted here 3580 // versus subtarget features accepted in the target attribute because the 3581 // bitfield structure that's initialized in the runtime only supports the 3582 // below currently rather than the full range of subtarget features. (See 3583 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3584 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3585 return llvm::StringSwitch<bool>(FeatureStr) 3586 .Case("cmov", true) 3587 .Case("mmx", true) 3588 .Case("popcnt", true) 3589 .Case("sse", true) 3590 .Case("sse2", true) 3591 .Case("sse3", true) 3592 .Case("sse4.1", true) 3593 .Case("sse4.2", true) 3594 .Case("avx", true) 3595 .Case("avx2", true) 3596 .Case("sse4a", true) 3597 .Case("fma4", true) 3598 .Case("xop", true) 3599 .Case("fma", true) 3600 .Case("avx512f", true) 3601 .Case("bmi", true) 3602 .Case("bmi2", true) 3603 .Default(false); 3604 } 3605 3606 bool 3607 X86TargetInfo::validateAsmConstraint(const char *&Name, 3608 TargetInfo::ConstraintInfo &Info) const { 3609 switch (*Name) { 3610 default: return false; 3611 // Constant constraints. 3612 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3613 // instructions. 3614 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3615 // x86_64 instructions. 3616 case 's': 3617 Info.setRequiresImmediate(); 3618 return true; 3619 case 'I': 3620 Info.setRequiresImmediate(0, 31); 3621 return true; 3622 case 'J': 3623 Info.setRequiresImmediate(0, 63); 3624 return true; 3625 case 'K': 3626 Info.setRequiresImmediate(-128, 127); 3627 return true; 3628 case 'L': 3629 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3630 return true; 3631 case 'M': 3632 Info.setRequiresImmediate(0, 3); 3633 return true; 3634 case 'N': 3635 Info.setRequiresImmediate(0, 255); 3636 return true; 3637 case 'O': 3638 Info.setRequiresImmediate(0, 127); 3639 return true; 3640 // Register constraints. 3641 case 'Y': // 'Y' is the first character for several 2-character constraints. 3642 // Shift the pointer to the second character of the constraint. 3643 Name++; 3644 switch (*Name) { 3645 default: 3646 return false; 3647 case '0': // First SSE register. 3648 case 't': // Any SSE register, when SSE2 is enabled. 3649 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3650 case 'm': // Any MMX register, when inter-unit moves enabled. 3651 Info.setAllowsRegister(); 3652 return true; 3653 } 3654 case 'f': // Any x87 floating point stack register. 3655 // Constraint 'f' cannot be used for output operands. 3656 if (Info.ConstraintStr[0] == '=') 3657 return false; 3658 Info.setAllowsRegister(); 3659 return true; 3660 case 'a': // eax. 3661 case 'b': // ebx. 3662 case 'c': // ecx. 3663 case 'd': // edx. 3664 case 'S': // esi. 3665 case 'D': // edi. 3666 case 'A': // edx:eax. 3667 case 't': // Top of floating point stack. 3668 case 'u': // Second from top of floating point stack. 3669 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3670 case 'y': // Any MMX register. 3671 case 'x': // Any SSE register. 3672 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3673 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3674 case 'l': // "Index" registers: any general register that can be used as an 3675 // index in a base+index memory access. 3676 Info.setAllowsRegister(); 3677 return true; 3678 // Floating point constant constraints. 3679 case 'C': // SSE floating point constant. 3680 case 'G': // x87 floating point constant. 3681 return true; 3682 } 3683 } 3684 3685 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3686 unsigned Size) const { 3687 // Strip off constraint modifiers. 3688 while (Constraint[0] == '=' || 3689 Constraint[0] == '+' || 3690 Constraint[0] == '&') 3691 Constraint = Constraint.substr(1); 3692 3693 return validateOperandSize(Constraint, Size); 3694 } 3695 3696 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3697 unsigned Size) const { 3698 return validateOperandSize(Constraint, Size); 3699 } 3700 3701 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3702 unsigned Size) const { 3703 switch (Constraint[0]) { 3704 default: break; 3705 case 'y': 3706 return Size <= 64; 3707 case 'f': 3708 case 't': 3709 case 'u': 3710 return Size <= 128; 3711 case 'x': 3712 if (SSELevel >= AVX512F) 3713 // 512-bit zmm registers can be used if target supports AVX512F. 3714 return Size <= 512U; 3715 else if (SSELevel >= AVX) 3716 // 256-bit ymm registers can be used if target supports AVX. 3717 return Size <= 256U; 3718 return Size <= 128U; 3719 case 'Y': 3720 // 'Y' is the first character for several 2-character constraints. 3721 switch (Constraint[1]) { 3722 default: break; 3723 case 'm': 3724 // 'Ym' is synonymous with 'y'. 3725 return Size <= 64; 3726 case 'i': 3727 case 't': 3728 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3729 if (SSELevel >= AVX512F) 3730 return Size <= 512U; 3731 else if (SSELevel >= AVX) 3732 return Size <= 256U; 3733 return SSELevel >= SSE2 && Size <= 128U; 3734 } 3735 3736 } 3737 3738 return true; 3739 } 3740 3741 std::string 3742 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3743 switch (*Constraint) { 3744 case 'a': return std::string("{ax}"); 3745 case 'b': return std::string("{bx}"); 3746 case 'c': return std::string("{cx}"); 3747 case 'd': return std::string("{dx}"); 3748 case 'S': return std::string("{si}"); 3749 case 'D': return std::string("{di}"); 3750 case 'p': // address 3751 return std::string("im"); 3752 case 't': // top of floating point stack. 3753 return std::string("{st}"); 3754 case 'u': // second from top of floating point stack. 3755 return std::string("{st(1)}"); // second from top of floating point stack. 3756 default: 3757 return std::string(1, *Constraint); 3758 } 3759 } 3760 3761 // X86-32 generic target 3762 class X86_32TargetInfo : public X86TargetInfo { 3763 public: 3764 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3765 : X86TargetInfo(Triple, Opts) { 3766 DoubleAlign = LongLongAlign = 32; 3767 LongDoubleWidth = 96; 3768 LongDoubleAlign = 32; 3769 SuitableAlign = 128; 3770 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 3771 SizeType = UnsignedInt; 3772 PtrDiffType = SignedInt; 3773 IntPtrType = SignedInt; 3774 RegParmMax = 3; 3775 3776 // Use fpret for all types. 3777 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3778 (1 << TargetInfo::Double) | 3779 (1 << TargetInfo::LongDouble)); 3780 3781 // x86-32 has atomics up to 8 bytes 3782 // FIXME: Check that we actually have cmpxchg8b before setting 3783 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3784 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3785 } 3786 BuiltinVaListKind getBuiltinVaListKind() const override { 3787 return TargetInfo::CharPtrBuiltinVaList; 3788 } 3789 3790 int getEHDataRegisterNumber(unsigned RegNo) const override { 3791 if (RegNo == 0) return 0; 3792 if (RegNo == 1) return 2; 3793 return -1; 3794 } 3795 bool validateOperandSize(StringRef Constraint, 3796 unsigned Size) const override { 3797 switch (Constraint[0]) { 3798 default: break; 3799 case 'R': 3800 case 'q': 3801 case 'Q': 3802 case 'a': 3803 case 'b': 3804 case 'c': 3805 case 'd': 3806 case 'S': 3807 case 'D': 3808 return Size <= 32; 3809 case 'A': 3810 return Size <= 64; 3811 } 3812 3813 return X86TargetInfo::validateOperandSize(Constraint, Size); 3814 } 3815 }; 3816 3817 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3818 public: 3819 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3820 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 3821 3822 unsigned getFloatEvalMethod() const override { 3823 unsigned Major, Minor, Micro; 3824 getTriple().getOSVersion(Major, Minor, Micro); 3825 // New NetBSD uses the default rounding mode. 3826 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3827 return X86_32TargetInfo::getFloatEvalMethod(); 3828 // NetBSD before 6.99.26 defaults to "double" rounding. 3829 return 1; 3830 } 3831 }; 3832 3833 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3834 public: 3835 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3836 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 3837 SizeType = UnsignedLong; 3838 IntPtrType = SignedLong; 3839 PtrDiffType = SignedLong; 3840 } 3841 }; 3842 3843 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3844 public: 3845 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3846 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 3847 SizeType = UnsignedLong; 3848 IntPtrType = SignedLong; 3849 PtrDiffType = SignedLong; 3850 } 3851 }; 3852 3853 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3854 public: 3855 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3856 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 3857 LongDoubleWidth = 128; 3858 LongDoubleAlign = 128; 3859 SuitableAlign = 128; 3860 MaxVectorAlign = 256; 3861 // The watchOS simulator uses the builtin bool type for Objective-C. 3862 llvm::Triple T = llvm::Triple(Triple); 3863 if (T.isWatchOS()) 3864 UseSignedCharForObjCBool = false; 3865 SizeType = UnsignedLong; 3866 IntPtrType = SignedLong; 3867 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 3868 HasAlignMac68kSupport = true; 3869 } 3870 3871 bool handleTargetFeatures(std::vector<std::string> &Features, 3872 DiagnosticsEngine &Diags) override { 3873 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 3874 Diags)) 3875 return false; 3876 // We now know the features we have: we can decide how to align vectors. 3877 MaxVectorAlign = 3878 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3879 return true; 3880 } 3881 }; 3882 3883 // x86-32 Windows target 3884 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3885 public: 3886 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3887 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 3888 WCharType = UnsignedShort; 3889 DoubleAlign = LongLongAlign = 64; 3890 bool IsWinCOFF = 3891 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3892 resetDataLayout(IsWinCOFF 3893 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3894 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 3895 } 3896 void getTargetDefines(const LangOptions &Opts, 3897 MacroBuilder &Builder) const override { 3898 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3899 } 3900 }; 3901 3902 // x86-32 Windows Visual Studio target 3903 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3904 public: 3905 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 3906 const TargetOptions &Opts) 3907 : WindowsX86_32TargetInfo(Triple, Opts) { 3908 LongDoubleWidth = LongDoubleAlign = 64; 3909 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3910 } 3911 void getTargetDefines(const LangOptions &Opts, 3912 MacroBuilder &Builder) const override { 3913 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3914 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3915 // The value of the following reflects processor type. 3916 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3917 // We lost the original triple, so we use the default. 3918 Builder.defineMacro("_M_IX86", "600"); 3919 } 3920 }; 3921 3922 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3923 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 3924 // supports __declspec natively under -fms-extensions, but we define a no-op 3925 // __declspec macro anyway for pre-processor compatibility. 3926 if (Opts.MicrosoftExt) 3927 Builder.defineMacro("__declspec", "__declspec"); 3928 else 3929 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3930 3931 if (!Opts.MicrosoftExt) { 3932 // Provide macros for all the calling convention keywords. Provide both 3933 // single and double underscore prefixed variants. These are available on 3934 // x64 as well as x86, even though they have no effect. 3935 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3936 for (const char *CC : CCs) { 3937 std::string GCCSpelling = "__attribute__((__"; 3938 GCCSpelling += CC; 3939 GCCSpelling += "__))"; 3940 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3941 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3942 } 3943 } 3944 } 3945 3946 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3947 Builder.defineMacro("__MSVCRT__"); 3948 Builder.defineMacro("__MINGW32__"); 3949 addCygMingDefines(Opts, Builder); 3950 } 3951 3952 // x86-32 MinGW target 3953 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3954 public: 3955 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3956 : WindowsX86_32TargetInfo(Triple, Opts) {} 3957 void getTargetDefines(const LangOptions &Opts, 3958 MacroBuilder &Builder) const override { 3959 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3960 DefineStd(Builder, "WIN32", Opts); 3961 DefineStd(Builder, "WINNT", Opts); 3962 Builder.defineMacro("_X86_"); 3963 addMinGWDefines(Opts, Builder); 3964 } 3965 }; 3966 3967 // x86-32 Cygwin target 3968 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3969 public: 3970 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3971 : X86_32TargetInfo(Triple, Opts) { 3972 WCharType = UnsignedShort; 3973 DoubleAlign = LongLongAlign = 64; 3974 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 3975 } 3976 void getTargetDefines(const LangOptions &Opts, 3977 MacroBuilder &Builder) const override { 3978 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3979 Builder.defineMacro("_X86_"); 3980 Builder.defineMacro("__CYGWIN__"); 3981 Builder.defineMacro("__CYGWIN32__"); 3982 addCygMingDefines(Opts, Builder); 3983 DefineStd(Builder, "unix", Opts); 3984 if (Opts.CPlusPlus) 3985 Builder.defineMacro("_GNU_SOURCE"); 3986 } 3987 }; 3988 3989 // x86-32 Haiku target 3990 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3991 public: 3992 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3993 : X86_32TargetInfo(Triple, Opts) { 3994 SizeType = UnsignedLong; 3995 IntPtrType = SignedLong; 3996 PtrDiffType = SignedLong; 3997 ProcessIDType = SignedLong; 3998 this->TLSSupported = false; 3999 } 4000 void getTargetDefines(const LangOptions &Opts, 4001 MacroBuilder &Builder) const override { 4002 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4003 Builder.defineMacro("__INTEL__"); 4004 Builder.defineMacro("__HAIKU__"); 4005 } 4006 }; 4007 4008 // X86-32 MCU target 4009 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4010 public: 4011 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4012 : X86_32TargetInfo(Triple, Opts) { 4013 LongDoubleWidth = 64; 4014 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4015 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4016 WIntType = UnsignedInt; 4017 } 4018 4019 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4020 // On MCU we support only C calling convention. 4021 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4022 } 4023 4024 void getTargetDefines(const LangOptions &Opts, 4025 MacroBuilder &Builder) const override { 4026 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4027 Builder.defineMacro("__iamcu"); 4028 Builder.defineMacro("__iamcu__"); 4029 } 4030 4031 bool allowsLargerPreferedTypeAlignment() const override { 4032 return false; 4033 } 4034 }; 4035 4036 // RTEMS Target 4037 template<typename Target> 4038 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4039 protected: 4040 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4041 MacroBuilder &Builder) const override { 4042 // RTEMS defines; list based off of gcc output 4043 4044 Builder.defineMacro("__rtems__"); 4045 Builder.defineMacro("__ELF__"); 4046 } 4047 4048 public: 4049 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4050 : OSTargetInfo<Target>(Triple, Opts) { 4051 switch (Triple.getArch()) { 4052 default: 4053 case llvm::Triple::x86: 4054 // this->MCountName = ".mcount"; 4055 break; 4056 case llvm::Triple::mips: 4057 case llvm::Triple::mipsel: 4058 case llvm::Triple::ppc: 4059 case llvm::Triple::ppc64: 4060 case llvm::Triple::ppc64le: 4061 // this->MCountName = "_mcount"; 4062 break; 4063 case llvm::Triple::arm: 4064 // this->MCountName = "__mcount"; 4065 break; 4066 } 4067 } 4068 }; 4069 4070 // x86-32 RTEMS target 4071 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4072 public: 4073 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4074 : X86_32TargetInfo(Triple, Opts) { 4075 SizeType = UnsignedLong; 4076 IntPtrType = SignedLong; 4077 PtrDiffType = SignedLong; 4078 } 4079 void getTargetDefines(const LangOptions &Opts, 4080 MacroBuilder &Builder) const override { 4081 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4082 Builder.defineMacro("__INTEL__"); 4083 Builder.defineMacro("__rtems__"); 4084 } 4085 }; 4086 4087 // x86-64 generic target 4088 class X86_64TargetInfo : public X86TargetInfo { 4089 public: 4090 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4091 : X86TargetInfo(Triple, Opts) { 4092 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4093 bool IsWinCOFF = 4094 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4095 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4096 LongDoubleWidth = 128; 4097 LongDoubleAlign = 128; 4098 LargeArrayMinWidth = 128; 4099 LargeArrayAlign = 128; 4100 SuitableAlign = 128; 4101 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4102 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4103 IntPtrType = IsX32 ? SignedInt : SignedLong; 4104 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4105 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4106 RegParmMax = 6; 4107 4108 // Pointers are 32-bit in x32. 4109 resetDataLayout(IsX32 4110 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4111 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4112 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4113 4114 // Use fpret only for long double. 4115 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4116 4117 // Use fp2ret for _Complex long double. 4118 ComplexLongDoubleUsesFP2Ret = true; 4119 4120 // Make __builtin_ms_va_list available. 4121 HasBuiltinMSVaList = true; 4122 4123 // x86-64 has atomics up to 16 bytes. 4124 MaxAtomicPromoteWidth = 128; 4125 MaxAtomicInlineWidth = 128; 4126 } 4127 BuiltinVaListKind getBuiltinVaListKind() const override { 4128 return TargetInfo::X86_64ABIBuiltinVaList; 4129 } 4130 4131 int getEHDataRegisterNumber(unsigned RegNo) const override { 4132 if (RegNo == 0) return 0; 4133 if (RegNo == 1) return 1; 4134 return -1; 4135 } 4136 4137 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4138 switch (CC) { 4139 case CC_C: 4140 case CC_Swift: 4141 case CC_X86VectorCall: 4142 case CC_IntelOclBicc: 4143 case CC_X86_64Win64: 4144 case CC_PreserveMost: 4145 case CC_PreserveAll: 4146 return CCCR_OK; 4147 default: 4148 return CCCR_Warning; 4149 } 4150 } 4151 4152 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4153 return CC_C; 4154 } 4155 4156 // for x32 we need it here explicitly 4157 bool hasInt128Type() const override { return true; } 4158 unsigned getUnwindWordWidth() const override { return 64; } 4159 unsigned getRegisterWidth() const override { return 64; } 4160 4161 bool validateGlobalRegisterVariable(StringRef RegName, 4162 unsigned RegSize, 4163 bool &HasSizeMismatch) const override { 4164 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4165 // handle. 4166 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4167 // Check that the register size is 64-bit. 4168 HasSizeMismatch = RegSize != 64; 4169 return true; 4170 } 4171 4172 // Check if the register is a 32-bit register the backend can handle. 4173 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4174 HasSizeMismatch); 4175 } 4176 }; 4177 4178 // x86-64 Windows target 4179 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4180 public: 4181 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4182 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4183 WCharType = UnsignedShort; 4184 LongWidth = LongAlign = 32; 4185 DoubleAlign = LongLongAlign = 64; 4186 IntMaxType = SignedLongLong; 4187 Int64Type = SignedLongLong; 4188 SizeType = UnsignedLongLong; 4189 PtrDiffType = SignedLongLong; 4190 IntPtrType = SignedLongLong; 4191 } 4192 4193 void getTargetDefines(const LangOptions &Opts, 4194 MacroBuilder &Builder) const override { 4195 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4196 Builder.defineMacro("_WIN64"); 4197 } 4198 4199 BuiltinVaListKind getBuiltinVaListKind() const override { 4200 return TargetInfo::CharPtrBuiltinVaList; 4201 } 4202 4203 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4204 switch (CC) { 4205 case CC_X86StdCall: 4206 case CC_X86ThisCall: 4207 case CC_X86FastCall: 4208 return CCCR_Ignore; 4209 case CC_C: 4210 case CC_X86VectorCall: 4211 case CC_IntelOclBicc: 4212 case CC_X86_64SysV: 4213 return CCCR_OK; 4214 default: 4215 return CCCR_Warning; 4216 } 4217 } 4218 }; 4219 4220 // x86-64 Windows Visual Studio target 4221 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4222 public: 4223 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4224 const TargetOptions &Opts) 4225 : WindowsX86_64TargetInfo(Triple, Opts) { 4226 LongDoubleWidth = LongDoubleAlign = 64; 4227 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4228 } 4229 void getTargetDefines(const LangOptions &Opts, 4230 MacroBuilder &Builder) const override { 4231 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4232 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4233 Builder.defineMacro("_M_X64", "100"); 4234 Builder.defineMacro("_M_AMD64", "100"); 4235 } 4236 }; 4237 4238 // x86-64 MinGW target 4239 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4240 public: 4241 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4242 : WindowsX86_64TargetInfo(Triple, Opts) { 4243 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4244 // with x86 FP ops. Weird. 4245 LongDoubleWidth = LongDoubleAlign = 128; 4246 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4247 } 4248 4249 void getTargetDefines(const LangOptions &Opts, 4250 MacroBuilder &Builder) const override { 4251 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4252 DefineStd(Builder, "WIN64", Opts); 4253 Builder.defineMacro("__MINGW64__"); 4254 addMinGWDefines(Opts, Builder); 4255 4256 // GCC defines this macro when it is using __gxx_personality_seh0. 4257 if (!Opts.SjLjExceptions) 4258 Builder.defineMacro("__SEH__"); 4259 } 4260 }; 4261 4262 // x86-64 Cygwin target 4263 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4264 public: 4265 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4266 : X86_64TargetInfo(Triple, Opts) { 4267 TLSSupported = false; 4268 WCharType = UnsignedShort; 4269 } 4270 void getTargetDefines(const LangOptions &Opts, 4271 MacroBuilder &Builder) const override { 4272 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4273 Builder.defineMacro("__x86_64__"); 4274 Builder.defineMacro("__CYGWIN__"); 4275 Builder.defineMacro("__CYGWIN64__"); 4276 addCygMingDefines(Opts, Builder); 4277 DefineStd(Builder, "unix", Opts); 4278 if (Opts.CPlusPlus) 4279 Builder.defineMacro("_GNU_SOURCE"); 4280 4281 // GCC defines this macro when it is using __gxx_personality_seh0. 4282 if (!Opts.SjLjExceptions) 4283 Builder.defineMacro("__SEH__"); 4284 } 4285 }; 4286 4287 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4288 public: 4289 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4290 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4291 Int64Type = SignedLongLong; 4292 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4293 llvm::Triple T = llvm::Triple(Triple); 4294 if (T.isiOS()) 4295 UseSignedCharForObjCBool = false; 4296 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4297 } 4298 4299 bool handleTargetFeatures(std::vector<std::string> &Features, 4300 DiagnosticsEngine &Diags) override { 4301 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4302 Diags)) 4303 return false; 4304 // We now know the features we have: we can decide how to align vectors. 4305 MaxVectorAlign = 4306 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4307 return true; 4308 } 4309 }; 4310 4311 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4312 public: 4313 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4314 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4315 IntMaxType = SignedLongLong; 4316 Int64Type = SignedLongLong; 4317 } 4318 }; 4319 4320 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4321 public: 4322 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4323 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4324 IntMaxType = SignedLongLong; 4325 Int64Type = SignedLongLong; 4326 } 4327 }; 4328 4329 class ARMTargetInfo : public TargetInfo { 4330 // Possible FPU choices. 4331 enum FPUMode { 4332 VFP2FPU = (1 << 0), 4333 VFP3FPU = (1 << 1), 4334 VFP4FPU = (1 << 2), 4335 NeonFPU = (1 << 3), 4336 FPARMV8 = (1 << 4) 4337 }; 4338 4339 // Possible HWDiv features. 4340 enum HWDivMode { 4341 HWDivThumb = (1 << 0), 4342 HWDivARM = (1 << 1) 4343 }; 4344 4345 static bool FPUModeIsVFP(FPUMode Mode) { 4346 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4347 } 4348 4349 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4350 static const char * const GCCRegNames[]; 4351 4352 std::string ABI, CPU; 4353 4354 StringRef CPUProfile; 4355 StringRef CPUAttr; 4356 4357 enum { 4358 FP_Default, 4359 FP_VFP, 4360 FP_Neon 4361 } FPMath; 4362 4363 unsigned ArchISA; 4364 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4365 unsigned ArchProfile; 4366 unsigned ArchVersion; 4367 4368 unsigned FPU : 5; 4369 4370 unsigned IsAAPCS : 1; 4371 unsigned HWDiv : 2; 4372 4373 // Initialized via features. 4374 unsigned SoftFloat : 1; 4375 unsigned SoftFloatABI : 1; 4376 4377 unsigned CRC : 1; 4378 unsigned Crypto : 1; 4379 unsigned DSP : 1; 4380 unsigned Unaligned : 1; 4381 4382 enum { 4383 LDREX_B = (1 << 0), /// byte (8-bit) 4384 LDREX_H = (1 << 1), /// half (16-bit) 4385 LDREX_W = (1 << 2), /// word (32-bit) 4386 LDREX_D = (1 << 3), /// double (64-bit) 4387 }; 4388 4389 uint32_t LDREX; 4390 4391 // ACLE 6.5.1 Hardware floating point 4392 enum { 4393 HW_FP_HP = (1 << 1), /// half (16-bit) 4394 HW_FP_SP = (1 << 2), /// single (32-bit) 4395 HW_FP_DP = (1 << 3), /// double (64-bit) 4396 }; 4397 uint32_t HW_FP; 4398 4399 static const Builtin::Info BuiltinInfo[]; 4400 4401 void setABIAAPCS() { 4402 IsAAPCS = true; 4403 4404 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4405 const llvm::Triple &T = getTriple(); 4406 4407 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4408 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4409 T.getOS() == llvm::Triple::Bitrig) 4410 SizeType = UnsignedLong; 4411 else 4412 SizeType = UnsignedInt; 4413 4414 switch (T.getOS()) { 4415 case llvm::Triple::NetBSD: 4416 WCharType = SignedInt; 4417 break; 4418 case llvm::Triple::Win32: 4419 WCharType = UnsignedShort; 4420 break; 4421 case llvm::Triple::Linux: 4422 default: 4423 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4424 WCharType = UnsignedInt; 4425 break; 4426 } 4427 4428 UseBitFieldTypeAlignment = true; 4429 4430 ZeroLengthBitfieldBoundary = 0; 4431 4432 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4433 // so set preferred for small types to 32. 4434 if (T.isOSBinFormatMachO()) { 4435 resetDataLayout(BigEndian 4436 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4437 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4438 } else if (T.isOSWindows()) { 4439 assert(!BigEndian && "Windows on ARM does not support big endian"); 4440 resetDataLayout("e" 4441 "-m:w" 4442 "-p:32:32" 4443 "-i64:64" 4444 "-v128:64:128" 4445 "-a:0:32" 4446 "-n32" 4447 "-S64"); 4448 } else if (T.isOSNaCl()) { 4449 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4450 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4451 } else { 4452 resetDataLayout(BigEndian 4453 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4454 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4455 } 4456 4457 // FIXME: Enumerated types are variable width in straight AAPCS. 4458 } 4459 4460 void setABIAPCS(bool IsAAPCS16) { 4461 const llvm::Triple &T = getTriple(); 4462 4463 IsAAPCS = false; 4464 4465 if (IsAAPCS16) 4466 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4467 else 4468 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4469 4470 // size_t is unsigned int on FreeBSD. 4471 if (T.getOS() == llvm::Triple::FreeBSD) 4472 SizeType = UnsignedInt; 4473 else 4474 SizeType = UnsignedLong; 4475 4476 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4477 WCharType = SignedInt; 4478 4479 // Do not respect the alignment of bit-field types when laying out 4480 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4481 UseBitFieldTypeAlignment = false; 4482 4483 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4484 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4485 /// gcc. 4486 ZeroLengthBitfieldBoundary = 32; 4487 4488 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4489 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4490 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4491 } else if (T.isOSBinFormatMachO()) 4492 resetDataLayout( 4493 BigEndian 4494 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4495 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4496 else 4497 resetDataLayout( 4498 BigEndian 4499 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4500 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4501 4502 // FIXME: Override "preferred align" for double and long long. 4503 } 4504 4505 void setArchInfo() { 4506 StringRef ArchName = getTriple().getArchName(); 4507 4508 ArchISA = llvm::ARM::parseArchISA(ArchName); 4509 CPU = llvm::ARM::getDefaultCPU(ArchName); 4510 unsigned AK = llvm::ARM::parseArch(ArchName); 4511 if (AK != llvm::ARM::AK_INVALID) 4512 ArchKind = AK; 4513 setArchInfo(ArchKind); 4514 } 4515 4516 void setArchInfo(unsigned Kind) { 4517 StringRef SubArch; 4518 4519 // cache TargetParser info 4520 ArchKind = Kind; 4521 SubArch = llvm::ARM::getSubArch(ArchKind); 4522 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4523 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4524 4525 // cache CPU related strings 4526 CPUAttr = getCPUAttr(); 4527 CPUProfile = getCPUProfile(); 4528 } 4529 4530 void setAtomic() { 4531 // when triple does not specify a sub arch, 4532 // then we are not using inline atomics 4533 bool ShouldUseInlineAtomic = 4534 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4535 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4536 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4537 if (ArchProfile == llvm::ARM::PK_M) { 4538 MaxAtomicPromoteWidth = 32; 4539 if (ShouldUseInlineAtomic) 4540 MaxAtomicInlineWidth = 32; 4541 } 4542 else { 4543 MaxAtomicPromoteWidth = 64; 4544 if (ShouldUseInlineAtomic) 4545 MaxAtomicInlineWidth = 64; 4546 } 4547 } 4548 4549 bool isThumb() const { 4550 return (ArchISA == llvm::ARM::IK_THUMB); 4551 } 4552 4553 bool supportsThumb() const { 4554 return CPUAttr.count('T') || ArchVersion >= 6; 4555 } 4556 4557 bool supportsThumb2() const { 4558 return CPUAttr.equals("6T2") || 4559 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 4560 } 4561 4562 StringRef getCPUAttr() const { 4563 // For most sub-arches, the build attribute CPU name is enough. 4564 // For Cortex variants, it's slightly different. 4565 switch(ArchKind) { 4566 default: 4567 return llvm::ARM::getCPUAttr(ArchKind); 4568 case llvm::ARM::AK_ARMV6M: 4569 return "6M"; 4570 case llvm::ARM::AK_ARMV7S: 4571 return "7S"; 4572 case llvm::ARM::AK_ARMV7A: 4573 return "7A"; 4574 case llvm::ARM::AK_ARMV7R: 4575 return "7R"; 4576 case llvm::ARM::AK_ARMV7M: 4577 return "7M"; 4578 case llvm::ARM::AK_ARMV7EM: 4579 return "7EM"; 4580 case llvm::ARM::AK_ARMV8A: 4581 return "8A"; 4582 case llvm::ARM::AK_ARMV8_1A: 4583 return "8_1A"; 4584 case llvm::ARM::AK_ARMV8_2A: 4585 return "8_2A"; 4586 case llvm::ARM::AK_ARMV8MBaseline: 4587 return "8M_BASE"; 4588 case llvm::ARM::AK_ARMV8MMainline: 4589 return "8M_MAIN"; 4590 } 4591 } 4592 4593 StringRef getCPUProfile() const { 4594 switch(ArchProfile) { 4595 case llvm::ARM::PK_A: 4596 return "A"; 4597 case llvm::ARM::PK_R: 4598 return "R"; 4599 case llvm::ARM::PK_M: 4600 return "M"; 4601 default: 4602 return ""; 4603 } 4604 } 4605 4606 public: 4607 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 4608 bool IsBigEndian) 4609 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 4610 HW_FP(0) { 4611 BigEndian = IsBigEndian; 4612 4613 switch (getTriple().getOS()) { 4614 case llvm::Triple::NetBSD: 4615 PtrDiffType = SignedLong; 4616 break; 4617 default: 4618 PtrDiffType = SignedInt; 4619 break; 4620 } 4621 4622 // Cache arch related info. 4623 setArchInfo(); 4624 4625 // {} in inline assembly are neon specifiers, not assembly variant 4626 // specifiers. 4627 NoAsmVariants = true; 4628 4629 // FIXME: This duplicates code from the driver that sets the -target-abi 4630 // option - this code is used if -target-abi isn't passed and should 4631 // be unified in some way. 4632 if (Triple.isOSBinFormatMachO()) { 4633 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4634 // the frontend matches that. 4635 if (Triple.getEnvironment() == llvm::Triple::EABI || 4636 Triple.getOS() == llvm::Triple::UnknownOS || 4637 StringRef(CPU).startswith("cortex-m")) { 4638 setABI("aapcs"); 4639 } else if (Triple.isWatchABI()) { 4640 setABI("aapcs16"); 4641 } else { 4642 setABI("apcs-gnu"); 4643 } 4644 } else if (Triple.isOSWindows()) { 4645 // FIXME: this is invalid for WindowsCE 4646 setABI("aapcs"); 4647 } else { 4648 // Select the default based on the platform. 4649 switch (Triple.getEnvironment()) { 4650 case llvm::Triple::Android: 4651 case llvm::Triple::GNUEABI: 4652 case llvm::Triple::GNUEABIHF: 4653 setABI("aapcs-linux"); 4654 break; 4655 case llvm::Triple::EABIHF: 4656 case llvm::Triple::EABI: 4657 setABI("aapcs"); 4658 break; 4659 case llvm::Triple::GNU: 4660 setABI("apcs-gnu"); 4661 break; 4662 default: 4663 if (Triple.getOS() == llvm::Triple::NetBSD) 4664 setABI("apcs-gnu"); 4665 else 4666 setABI("aapcs"); 4667 break; 4668 } 4669 } 4670 4671 // ARM targets default to using the ARM C++ ABI. 4672 TheCXXABI.set(TargetCXXABI::GenericARM); 4673 4674 // ARM has atomics up to 8 bytes 4675 setAtomic(); 4676 4677 // Do force alignment of members that follow zero length bitfields. If 4678 // the alignment of the zero-length bitfield is greater than the member 4679 // that follows it, `bar', `bar' will be aligned as the type of the 4680 // zero length bitfield. 4681 UseZeroLengthBitfieldAlignment = true; 4682 4683 if (Triple.getOS() == llvm::Triple::Linux || 4684 Triple.getOS() == llvm::Triple::UnknownOS) 4685 this->MCountName = 4686 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 4687 } 4688 4689 StringRef getABI() const override { return ABI; } 4690 4691 bool setABI(const std::string &Name) override { 4692 ABI = Name; 4693 4694 // The defaults (above) are for AAPCS, check if we need to change them. 4695 // 4696 // FIXME: We need support for -meabi... we could just mangle it into the 4697 // name. 4698 if (Name == "apcs-gnu" || Name == "aapcs16") { 4699 setABIAPCS(Name == "aapcs16"); 4700 return true; 4701 } 4702 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4703 setABIAAPCS(); 4704 return true; 4705 } 4706 return false; 4707 } 4708 4709 // FIXME: This should be based on Arch attributes, not CPU names. 4710 bool 4711 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4712 StringRef CPU, 4713 const std::vector<std::string> &FeaturesVec) const override { 4714 4715 std::vector<const char*> TargetFeatures; 4716 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4717 4718 // get default FPU features 4719 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4720 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4721 4722 // get default Extension features 4723 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 4724 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4725 4726 for (const char *Feature : TargetFeatures) 4727 if (Feature[0] == '+') 4728 Features[Feature+1] = true; 4729 4730 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4731 } 4732 4733 bool handleTargetFeatures(std::vector<std::string> &Features, 4734 DiagnosticsEngine &Diags) override { 4735 FPU = 0; 4736 CRC = 0; 4737 Crypto = 0; 4738 DSP = 0; 4739 Unaligned = 1; 4740 SoftFloat = SoftFloatABI = false; 4741 HWDiv = 0; 4742 4743 // This does not diagnose illegal cases like having both 4744 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4745 uint32_t HW_FP_remove = 0; 4746 for (const auto &Feature : Features) { 4747 if (Feature == "+soft-float") { 4748 SoftFloat = true; 4749 } else if (Feature == "+soft-float-abi") { 4750 SoftFloatABI = true; 4751 } else if (Feature == "+vfp2") { 4752 FPU |= VFP2FPU; 4753 HW_FP |= HW_FP_SP | HW_FP_DP; 4754 } else if (Feature == "+vfp3") { 4755 FPU |= VFP3FPU; 4756 HW_FP |= HW_FP_SP | HW_FP_DP; 4757 } else if (Feature == "+vfp4") { 4758 FPU |= VFP4FPU; 4759 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4760 } else if (Feature == "+fp-armv8") { 4761 FPU |= FPARMV8; 4762 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4763 } else if (Feature == "+neon") { 4764 FPU |= NeonFPU; 4765 HW_FP |= HW_FP_SP | HW_FP_DP; 4766 } else if (Feature == "+hwdiv") { 4767 HWDiv |= HWDivThumb; 4768 } else if (Feature == "+hwdiv-arm") { 4769 HWDiv |= HWDivARM; 4770 } else if (Feature == "+crc") { 4771 CRC = 1; 4772 } else if (Feature == "+crypto") { 4773 Crypto = 1; 4774 } else if (Feature == "+dsp") { 4775 DSP = 1; 4776 } else if (Feature == "+fp-only-sp") { 4777 HW_FP_remove |= HW_FP_DP; 4778 } else if (Feature == "+strict-align") { 4779 Unaligned = 0; 4780 } else if (Feature == "+fp16") { 4781 HW_FP |= HW_FP_HP; 4782 } 4783 } 4784 HW_FP &= ~HW_FP_remove; 4785 4786 switch (ArchVersion) { 4787 case 6: 4788 if (ArchProfile == llvm::ARM::PK_M) 4789 LDREX = 0; 4790 else if (ArchKind == llvm::ARM::AK_ARMV6K) 4791 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4792 else 4793 LDREX = LDREX_W; 4794 break; 4795 case 7: 4796 if (ArchProfile == llvm::ARM::PK_M) 4797 LDREX = LDREX_W | LDREX_H | LDREX_B ; 4798 else 4799 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4800 break; 4801 case 8: 4802 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4803 } 4804 4805 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4806 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4807 return false; 4808 } 4809 4810 if (FPMath == FP_Neon) 4811 Features.push_back("+neonfp"); 4812 else if (FPMath == FP_VFP) 4813 Features.push_back("-neonfp"); 4814 4815 // Remove front-end specific options which the backend handles differently. 4816 auto Feature = 4817 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4818 if (Feature != Features.end()) 4819 Features.erase(Feature); 4820 4821 return true; 4822 } 4823 4824 bool hasFeature(StringRef Feature) const override { 4825 return llvm::StringSwitch<bool>(Feature) 4826 .Case("arm", true) 4827 .Case("aarch32", true) 4828 .Case("softfloat", SoftFloat) 4829 .Case("thumb", isThumb()) 4830 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4831 .Case("hwdiv", HWDiv & HWDivThumb) 4832 .Case("hwdiv-arm", HWDiv & HWDivARM) 4833 .Default(false); 4834 } 4835 4836 bool setCPU(const std::string &Name) override { 4837 if (Name != "generic") 4838 setArchInfo(llvm::ARM::parseCPUArch(Name)); 4839 4840 if (ArchKind == llvm::ARM::AK_INVALID) 4841 return false; 4842 setAtomic(); 4843 CPU = Name; 4844 return true; 4845 } 4846 4847 bool setFPMath(StringRef Name) override; 4848 4849 void getTargetDefines(const LangOptions &Opts, 4850 MacroBuilder &Builder) const override { 4851 // Target identification. 4852 Builder.defineMacro("__arm"); 4853 Builder.defineMacro("__arm__"); 4854 // For bare-metal none-eabi. 4855 if (getTriple().getOS() == llvm::Triple::UnknownOS && 4856 getTriple().getEnvironment() == llvm::Triple::EABI) 4857 Builder.defineMacro("__ELF__"); 4858 4859 // Target properties. 4860 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4861 4862 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 4863 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 4864 if (getTriple().isWatchABI()) 4865 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 4866 4867 if (!CPUAttr.empty()) 4868 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 4869 4870 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4871 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4872 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 4873 4874 if (ArchVersion >= 8) { 4875 // ACLE 6.5.7 Crypto Extension 4876 if (Crypto) 4877 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 4878 // ACLE 6.5.8 CRC32 Extension 4879 if (CRC) 4880 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 4881 // ACLE 6.5.10 Numeric Maximum and Minimum 4882 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 4883 // ACLE 6.5.9 Directed Rounding 4884 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 4885 } 4886 4887 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4888 // is not defined for the M-profile. 4889 // NOTE that the default profile is assumed to be 'A' 4890 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 4891 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4892 4893 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 4894 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 4895 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 4896 // v7 and v8 architectures excluding v8-M Baseline. 4897 if (supportsThumb2()) 4898 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4899 else if (supportsThumb()) 4900 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4901 4902 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4903 // instruction set such as ARM or Thumb. 4904 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4905 4906 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4907 4908 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4909 if (!CPUProfile.empty()) 4910 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4911 4912 // ACLE 6.4.3 Unaligned access supported in hardware 4913 if (Unaligned) 4914 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 4915 4916 // ACLE 6.4.4 LDREX/STREX 4917 if (LDREX) 4918 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 4919 4920 // ACLE 6.4.5 CLZ 4921 if (ArchVersion == 5 || 4922 (ArchVersion == 6 && CPUProfile != "M") || 4923 ArchVersion > 6) 4924 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 4925 4926 // ACLE 6.5.1 Hardware Floating Point 4927 if (HW_FP) 4928 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4929 4930 // ACLE predefines. 4931 Builder.defineMacro("__ARM_ACLE", "200"); 4932 4933 // FP16 support (we currently only support IEEE format). 4934 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 4935 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 4936 4937 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 4938 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 4939 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 4940 4941 // Subtarget options. 4942 4943 // FIXME: It's more complicated than this and we don't really support 4944 // interworking. 4945 // Windows on ARM does not "support" interworking 4946 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 4947 Builder.defineMacro("__THUMB_INTERWORK__"); 4948 4949 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4950 // Embedded targets on Darwin follow AAPCS, but not EABI. 4951 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4952 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4953 Builder.defineMacro("__ARM_EABI__"); 4954 Builder.defineMacro("__ARM_PCS", "1"); 4955 } 4956 4957 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 4958 ABI == "aapcs16") 4959 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4960 4961 if (SoftFloat) 4962 Builder.defineMacro("__SOFTFP__"); 4963 4964 if (CPU == "xscale") 4965 Builder.defineMacro("__XSCALE__"); 4966 4967 if (isThumb()) { 4968 Builder.defineMacro("__THUMBEL__"); 4969 Builder.defineMacro("__thumb__"); 4970 if (supportsThumb2()) 4971 Builder.defineMacro("__thumb2__"); 4972 } 4973 4974 // ACLE 6.4.9 32-bit SIMD instructions 4975 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 4976 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 4977 4978 // ACLE 6.4.10 Hardware Integer Divide 4979 if (((HWDiv & HWDivThumb) && isThumb()) || 4980 ((HWDiv & HWDivARM) && !isThumb())) { 4981 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 4982 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4983 } 4984 4985 // Note, this is always on in gcc, even though it doesn't make sense. 4986 Builder.defineMacro("__APCS_32__"); 4987 4988 if (FPUModeIsVFP((FPUMode) FPU)) { 4989 Builder.defineMacro("__VFP_FP__"); 4990 if (FPU & VFP2FPU) 4991 Builder.defineMacro("__ARM_VFPV2__"); 4992 if (FPU & VFP3FPU) 4993 Builder.defineMacro("__ARM_VFPV3__"); 4994 if (FPU & VFP4FPU) 4995 Builder.defineMacro("__ARM_VFPV4__"); 4996 } 4997 4998 // This only gets set when Neon instructions are actually available, unlike 4999 // the VFP define, hence the soft float and arch check. This is subtly 5000 // different from gcc, we follow the intent which was that it should be set 5001 // when Neon instructions are actually available. 5002 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5003 Builder.defineMacro("__ARM_NEON", "1"); 5004 Builder.defineMacro("__ARM_NEON__"); 5005 // current AArch32 NEON implementations do not support double-precision 5006 // floating-point even when it is present in VFP. 5007 Builder.defineMacro("__ARM_NEON_FP", 5008 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5009 } 5010 5011 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5012 Opts.ShortWChar ? "2" : "4"); 5013 5014 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5015 Opts.ShortEnums ? "1" : "4"); 5016 5017 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5018 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5019 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5020 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5021 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5022 } 5023 5024 // ACLE 6.4.7 DSP instructions 5025 if (DSP) { 5026 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5027 } 5028 5029 // ACLE 6.4.8 Saturation instructions 5030 bool SAT = false; 5031 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5032 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5033 SAT = true; 5034 } 5035 5036 // ACLE 6.4.6 Q (saturation) flag 5037 if (DSP || SAT) 5038 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5039 5040 if (Opts.UnsafeFPMath) 5041 Builder.defineMacro("__ARM_FP_FAST", "1"); 5042 5043 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5044 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5045 } 5046 5047 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5048 return llvm::makeArrayRef(BuiltinInfo, 5049 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5050 } 5051 bool isCLZForZeroUndef() const override { return false; } 5052 BuiltinVaListKind getBuiltinVaListKind() const override { 5053 return IsAAPCS 5054 ? AAPCSABIBuiltinVaList 5055 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5056 : TargetInfo::VoidPtrBuiltinVaList); 5057 } 5058 ArrayRef<const char *> getGCCRegNames() const override; 5059 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5060 bool validateAsmConstraint(const char *&Name, 5061 TargetInfo::ConstraintInfo &Info) const override { 5062 switch (*Name) { 5063 default: break; 5064 case 'l': // r0-r7 5065 case 'h': // r8-r15 5066 case 't': // VFP Floating point register single precision 5067 case 'w': // VFP Floating point register double precision 5068 Info.setAllowsRegister(); 5069 return true; 5070 case 'I': 5071 case 'J': 5072 case 'K': 5073 case 'L': 5074 case 'M': 5075 // FIXME 5076 return true; 5077 case 'Q': // A memory address that is a single base register. 5078 Info.setAllowsMemory(); 5079 return true; 5080 case 'U': // a memory reference... 5081 switch (Name[1]) { 5082 case 'q': // ...ARMV4 ldrsb 5083 case 'v': // ...VFP load/store (reg+constant offset) 5084 case 'y': // ...iWMMXt load/store 5085 case 't': // address valid for load/store opaque types wider 5086 // than 128-bits 5087 case 'n': // valid address for Neon doubleword vector load/store 5088 case 'm': // valid address for Neon element and structure load/store 5089 case 's': // valid address for non-offset loads/stores of quad-word 5090 // values in four ARM registers 5091 Info.setAllowsMemory(); 5092 Name++; 5093 return true; 5094 } 5095 } 5096 return false; 5097 } 5098 std::string convertConstraint(const char *&Constraint) const override { 5099 std::string R; 5100 switch (*Constraint) { 5101 case 'U': // Two-character constraint; add "^" hint for later parsing. 5102 R = std::string("^") + std::string(Constraint, 2); 5103 Constraint++; 5104 break; 5105 case 'p': // 'p' should be translated to 'r' by default. 5106 R = std::string("r"); 5107 break; 5108 default: 5109 return std::string(1, *Constraint); 5110 } 5111 return R; 5112 } 5113 bool 5114 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5115 std::string &SuggestedModifier) const override { 5116 bool isOutput = (Constraint[0] == '='); 5117 bool isInOut = (Constraint[0] == '+'); 5118 5119 // Strip off constraint modifiers. 5120 while (Constraint[0] == '=' || 5121 Constraint[0] == '+' || 5122 Constraint[0] == '&') 5123 Constraint = Constraint.substr(1); 5124 5125 switch (Constraint[0]) { 5126 default: break; 5127 case 'r': { 5128 switch (Modifier) { 5129 default: 5130 return (isInOut || isOutput || Size <= 64); 5131 case 'q': 5132 // A register of size 32 cannot fit a vector type. 5133 return false; 5134 } 5135 } 5136 } 5137 5138 return true; 5139 } 5140 const char *getClobbers() const override { 5141 // FIXME: Is this really right? 5142 return ""; 5143 } 5144 5145 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5146 switch (CC) { 5147 case CC_AAPCS: 5148 case CC_AAPCS_VFP: 5149 case CC_Swift: 5150 return CCCR_OK; 5151 default: 5152 return CCCR_Warning; 5153 } 5154 } 5155 5156 int getEHDataRegisterNumber(unsigned RegNo) const override { 5157 if (RegNo == 0) return 0; 5158 if (RegNo == 1) return 1; 5159 return -1; 5160 } 5161 5162 bool hasSjLjLowering() const override { 5163 return true; 5164 } 5165 }; 5166 5167 bool ARMTargetInfo::setFPMath(StringRef Name) { 5168 if (Name == "neon") { 5169 FPMath = FP_Neon; 5170 return true; 5171 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5172 Name == "vfp4") { 5173 FPMath = FP_VFP; 5174 return true; 5175 } 5176 return false; 5177 } 5178 5179 const char * const ARMTargetInfo::GCCRegNames[] = { 5180 // Integer registers 5181 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5182 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5183 5184 // Float registers 5185 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5186 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5187 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5188 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5189 5190 // Double registers 5191 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5192 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5193 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5194 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5195 5196 // Quad registers 5197 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5198 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5199 }; 5200 5201 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5202 return llvm::makeArrayRef(GCCRegNames); 5203 } 5204 5205 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5206 { { "a1" }, "r0" }, 5207 { { "a2" }, "r1" }, 5208 { { "a3" }, "r2" }, 5209 { { "a4" }, "r3" }, 5210 { { "v1" }, "r4" }, 5211 { { "v2" }, "r5" }, 5212 { { "v3" }, "r6" }, 5213 { { "v4" }, "r7" }, 5214 { { "v5" }, "r8" }, 5215 { { "v6", "rfp" }, "r9" }, 5216 { { "sl" }, "r10" }, 5217 { { "fp" }, "r11" }, 5218 { { "ip" }, "r12" }, 5219 { { "r13" }, "sp" }, 5220 { { "r14" }, "lr" }, 5221 { { "r15" }, "pc" }, 5222 // The S, D and Q registers overlap, but aren't really aliases; we 5223 // don't want to substitute one of these for a different-sized one. 5224 }; 5225 5226 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5227 return llvm::makeArrayRef(GCCRegAliases); 5228 } 5229 5230 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5231 #define BUILTIN(ID, TYPE, ATTRS) \ 5232 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5233 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5234 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5235 #include "clang/Basic/BuiltinsNEON.def" 5236 5237 #define BUILTIN(ID, TYPE, ATTRS) \ 5238 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5239 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5240 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5241 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5242 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5243 #include "clang/Basic/BuiltinsARM.def" 5244 }; 5245 5246 class ARMleTargetInfo : public ARMTargetInfo { 5247 public: 5248 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5249 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/false) {} 5250 void getTargetDefines(const LangOptions &Opts, 5251 MacroBuilder &Builder) const override { 5252 Builder.defineMacro("__ARMEL__"); 5253 ARMTargetInfo::getTargetDefines(Opts, Builder); 5254 } 5255 }; 5256 5257 class ARMbeTargetInfo : public ARMTargetInfo { 5258 public: 5259 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5260 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/true) {} 5261 void getTargetDefines(const LangOptions &Opts, 5262 MacroBuilder &Builder) const override { 5263 Builder.defineMacro("__ARMEB__"); 5264 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5265 ARMTargetInfo::getTargetDefines(Opts, Builder); 5266 } 5267 }; 5268 5269 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5270 const llvm::Triple Triple; 5271 public: 5272 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5273 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5274 WCharType = UnsignedShort; 5275 SizeType = UnsignedInt; 5276 } 5277 void getVisualStudioDefines(const LangOptions &Opts, 5278 MacroBuilder &Builder) const { 5279 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5280 5281 // FIXME: this is invalid for WindowsCE 5282 Builder.defineMacro("_M_ARM_NT", "1"); 5283 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5284 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5285 5286 assert((Triple.getArch() == llvm::Triple::arm || 5287 Triple.getArch() == llvm::Triple::thumb) && 5288 "invalid architecture for Windows ARM target info"); 5289 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5290 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5291 5292 // TODO map the complete set of values 5293 // 31: VFPv3 40: VFPv4 5294 Builder.defineMacro("_M_ARM_FP", "31"); 5295 } 5296 BuiltinVaListKind getBuiltinVaListKind() const override { 5297 return TargetInfo::CharPtrBuiltinVaList; 5298 } 5299 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5300 switch (CC) { 5301 case CC_X86StdCall: 5302 case CC_X86ThisCall: 5303 case CC_X86FastCall: 5304 case CC_X86VectorCall: 5305 return CCCR_Ignore; 5306 case CC_C: 5307 return CCCR_OK; 5308 default: 5309 return CCCR_Warning; 5310 } 5311 } 5312 }; 5313 5314 // Windows ARM + Itanium C++ ABI Target 5315 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5316 public: 5317 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5318 const TargetOptions &Opts) 5319 : WindowsARMTargetInfo(Triple, Opts) { 5320 TheCXXABI.set(TargetCXXABI::GenericARM); 5321 } 5322 5323 void getTargetDefines(const LangOptions &Opts, 5324 MacroBuilder &Builder) const override { 5325 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5326 5327 if (Opts.MSVCCompat) 5328 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5329 } 5330 }; 5331 5332 // Windows ARM, MS (C++) ABI 5333 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5334 public: 5335 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5336 const TargetOptions &Opts) 5337 : WindowsARMTargetInfo(Triple, Opts) { 5338 TheCXXABI.set(TargetCXXABI::Microsoft); 5339 } 5340 5341 void getTargetDefines(const LangOptions &Opts, 5342 MacroBuilder &Builder) const override { 5343 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5344 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5345 } 5346 }; 5347 5348 // ARM MinGW target 5349 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5350 public: 5351 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5352 : WindowsARMTargetInfo(Triple, Opts) { 5353 TheCXXABI.set(TargetCXXABI::GenericARM); 5354 } 5355 5356 void getTargetDefines(const LangOptions &Opts, 5357 MacroBuilder &Builder) const override { 5358 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5359 DefineStd(Builder, "WIN32", Opts); 5360 DefineStd(Builder, "WINNT", Opts); 5361 Builder.defineMacro("_ARM_"); 5362 addMinGWDefines(Opts, Builder); 5363 } 5364 }; 5365 5366 // ARM Cygwin target 5367 class CygwinARMTargetInfo : public ARMleTargetInfo { 5368 public: 5369 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5370 : ARMleTargetInfo(Triple, Opts) { 5371 TLSSupported = false; 5372 WCharType = UnsignedShort; 5373 DoubleAlign = LongLongAlign = 64; 5374 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5375 } 5376 void getTargetDefines(const LangOptions &Opts, 5377 MacroBuilder &Builder) const override { 5378 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5379 Builder.defineMacro("_ARM_"); 5380 Builder.defineMacro("__CYGWIN__"); 5381 Builder.defineMacro("__CYGWIN32__"); 5382 DefineStd(Builder, "unix", Opts); 5383 if (Opts.CPlusPlus) 5384 Builder.defineMacro("_GNU_SOURCE"); 5385 } 5386 }; 5387 5388 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 5389 protected: 5390 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5391 MacroBuilder &Builder) const override { 5392 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5393 } 5394 5395 public: 5396 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5397 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 5398 HasAlignMac68kSupport = true; 5399 // iOS always has 64-bit atomic instructions. 5400 // FIXME: This should be based off of the target features in 5401 // ARMleTargetInfo. 5402 MaxAtomicInlineWidth = 64; 5403 5404 if (Triple.isWatchABI()) { 5405 // Darwin on iOS uses a variant of the ARM C++ ABI. 5406 TheCXXABI.set(TargetCXXABI::WatchOS); 5407 5408 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5409 // size_t is long, it's a bit weird for it to be int. 5410 PtrDiffType = SignedLong; 5411 5412 // BOOL should be a real boolean on the new ABI 5413 UseSignedCharForObjCBool = false; 5414 } else 5415 TheCXXABI.set(TargetCXXABI::iOS); 5416 } 5417 }; 5418 5419 class AArch64TargetInfo : public TargetInfo { 5420 virtual void setDataLayout() = 0; 5421 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5422 static const char *const GCCRegNames[]; 5423 5424 enum FPUModeEnum { 5425 FPUMode, 5426 NeonMode 5427 }; 5428 5429 unsigned FPU; 5430 unsigned CRC; 5431 unsigned Crypto; 5432 unsigned Unaligned; 5433 unsigned V8_1A; 5434 5435 static const Builtin::Info BuiltinInfo[]; 5436 5437 std::string ABI; 5438 5439 public: 5440 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5441 : TargetInfo(Triple), ABI("aapcs") { 5442 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5443 WCharType = SignedInt; 5444 5445 // NetBSD apparently prefers consistency across ARM targets to consistency 5446 // across 64-bit targets. 5447 Int64Type = SignedLongLong; 5448 IntMaxType = SignedLongLong; 5449 } else { 5450 WCharType = UnsignedInt; 5451 Int64Type = SignedLong; 5452 IntMaxType = SignedLong; 5453 } 5454 5455 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5456 MaxVectorAlign = 128; 5457 MaxAtomicInlineWidth = 128; 5458 MaxAtomicPromoteWidth = 128; 5459 5460 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5461 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5462 5463 // {} in inline assembly are neon specifiers, not assembly variant 5464 // specifiers. 5465 NoAsmVariants = true; 5466 5467 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5468 // contributes to the alignment of the containing aggregate in the same way 5469 // a plain (non bit-field) member of that type would, without exception for 5470 // zero-sized or anonymous bit-fields." 5471 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5472 UseZeroLengthBitfieldAlignment = true; 5473 5474 // AArch64 targets default to using the ARM C++ ABI. 5475 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5476 5477 if (Triple.getOS() == llvm::Triple::Linux || 5478 Triple.getOS() == llvm::Triple::UnknownOS) 5479 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 5480 } 5481 5482 StringRef getABI() const override { return ABI; } 5483 bool setABI(const std::string &Name) override { 5484 if (Name != "aapcs" && Name != "darwinpcs") 5485 return false; 5486 5487 ABI = Name; 5488 return true; 5489 } 5490 5491 bool setCPU(const std::string &Name) override { 5492 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5493 .Case("generic", true) 5494 .Cases("cortex-a53", "cortex-a57", "cortex-a72", 5495 "cortex-a35", "exynos-m1", true) 5496 .Case("cyclone", true) 5497 .Case("kryo", true) 5498 .Default(false); 5499 return CPUKnown; 5500 } 5501 5502 void getTargetDefines(const LangOptions &Opts, 5503 MacroBuilder &Builder) const override { 5504 // Target identification. 5505 Builder.defineMacro("__aarch64__"); 5506 5507 // Target properties. 5508 Builder.defineMacro("_LP64"); 5509 Builder.defineMacro("__LP64__"); 5510 5511 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5512 Builder.defineMacro("__ARM_ACLE", "200"); 5513 Builder.defineMacro("__ARM_ARCH", "8"); 5514 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5515 5516 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5517 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5518 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5519 5520 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5521 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5522 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5523 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5524 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5525 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5526 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5527 5528 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5529 5530 // 0xe implies support for half, single and double precision operations. 5531 Builder.defineMacro("__ARM_FP", "0xE"); 5532 5533 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5534 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5535 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5536 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5537 5538 if (Opts.UnsafeFPMath) 5539 Builder.defineMacro("__ARM_FP_FAST", "1"); 5540 5541 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5542 5543 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5544 Opts.ShortEnums ? "1" : "4"); 5545 5546 if (FPU == NeonMode) { 5547 Builder.defineMacro("__ARM_NEON", "1"); 5548 // 64-bit NEON supports half, single and double precision operations. 5549 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5550 } 5551 5552 if (CRC) 5553 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5554 5555 if (Crypto) 5556 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5557 5558 if (Unaligned) 5559 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5560 5561 if (V8_1A) 5562 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5563 5564 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5565 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5566 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5567 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5568 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5569 } 5570 5571 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5572 return llvm::makeArrayRef(BuiltinInfo, 5573 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5574 } 5575 5576 bool hasFeature(StringRef Feature) const override { 5577 return Feature == "aarch64" || 5578 Feature == "arm64" || 5579 Feature == "arm" || 5580 (Feature == "neon" && FPU == NeonMode); 5581 } 5582 5583 bool handleTargetFeatures(std::vector<std::string> &Features, 5584 DiagnosticsEngine &Diags) override { 5585 FPU = FPUMode; 5586 CRC = 0; 5587 Crypto = 0; 5588 Unaligned = 1; 5589 V8_1A = 0; 5590 5591 for (const auto &Feature : Features) { 5592 if (Feature == "+neon") 5593 FPU = NeonMode; 5594 if (Feature == "+crc") 5595 CRC = 1; 5596 if (Feature == "+crypto") 5597 Crypto = 1; 5598 if (Feature == "+strict-align") 5599 Unaligned = 0; 5600 if (Feature == "+v8.1a") 5601 V8_1A = 1; 5602 } 5603 5604 setDataLayout(); 5605 5606 return true; 5607 } 5608 5609 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5610 switch (CC) { 5611 case CC_C: 5612 case CC_Swift: 5613 case CC_PreserveMost: 5614 case CC_PreserveAll: 5615 return CCCR_OK; 5616 default: 5617 return CCCR_Warning; 5618 } 5619 } 5620 5621 bool isCLZForZeroUndef() const override { return false; } 5622 5623 BuiltinVaListKind getBuiltinVaListKind() const override { 5624 return TargetInfo::AArch64ABIBuiltinVaList; 5625 } 5626 5627 ArrayRef<const char *> getGCCRegNames() const override; 5628 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5629 5630 bool validateAsmConstraint(const char *&Name, 5631 TargetInfo::ConstraintInfo &Info) const override { 5632 switch (*Name) { 5633 default: 5634 return false; 5635 case 'w': // Floating point and SIMD registers (V0-V31) 5636 Info.setAllowsRegister(); 5637 return true; 5638 case 'I': // Constant that can be used with an ADD instruction 5639 case 'J': // Constant that can be used with a SUB instruction 5640 case 'K': // Constant that can be used with a 32-bit logical instruction 5641 case 'L': // Constant that can be used with a 64-bit logical instruction 5642 case 'M': // Constant that can be used as a 32-bit MOV immediate 5643 case 'N': // Constant that can be used as a 64-bit MOV immediate 5644 case 'Y': // Floating point constant zero 5645 case 'Z': // Integer constant zero 5646 return true; 5647 case 'Q': // A memory reference with base register and no offset 5648 Info.setAllowsMemory(); 5649 return true; 5650 case 'S': // A symbolic address 5651 Info.setAllowsRegister(); 5652 return true; 5653 case 'U': 5654 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5655 // Utf: A memory address suitable for ldp/stp in TF mode. 5656 // Usa: An absolute symbolic address. 5657 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5658 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5659 case 'z': // Zero register, wzr or xzr 5660 Info.setAllowsRegister(); 5661 return true; 5662 case 'x': // Floating point and SIMD registers (V0-V15) 5663 Info.setAllowsRegister(); 5664 return true; 5665 } 5666 return false; 5667 } 5668 5669 bool 5670 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5671 std::string &SuggestedModifier) const override { 5672 // Strip off constraint modifiers. 5673 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5674 Constraint = Constraint.substr(1); 5675 5676 switch (Constraint[0]) { 5677 default: 5678 return true; 5679 case 'z': 5680 case 'r': { 5681 switch (Modifier) { 5682 case 'x': 5683 case 'w': 5684 // For now assume that the person knows what they're 5685 // doing with the modifier. 5686 return true; 5687 default: 5688 // By default an 'r' constraint will be in the 'x' 5689 // registers. 5690 if (Size == 64) 5691 return true; 5692 5693 SuggestedModifier = "w"; 5694 return false; 5695 } 5696 } 5697 } 5698 } 5699 5700 const char *getClobbers() const override { return ""; } 5701 5702 int getEHDataRegisterNumber(unsigned RegNo) const override { 5703 if (RegNo == 0) 5704 return 0; 5705 if (RegNo == 1) 5706 return 1; 5707 return -1; 5708 } 5709 }; 5710 5711 const char *const AArch64TargetInfo::GCCRegNames[] = { 5712 // 32-bit Integer registers 5713 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5714 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5715 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5716 5717 // 64-bit Integer registers 5718 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5719 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5720 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5721 5722 // 32-bit floating point regsisters 5723 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5724 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5725 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5726 5727 // 64-bit floating point regsisters 5728 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5729 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5730 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5731 5732 // Vector registers 5733 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5734 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5735 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5736 }; 5737 5738 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 5739 return llvm::makeArrayRef(GCCRegNames); 5740 } 5741 5742 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5743 { { "w31" }, "wsp" }, 5744 { { "x29" }, "fp" }, 5745 { { "x30" }, "lr" }, 5746 { { "x31" }, "sp" }, 5747 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5748 // don't want to substitute one of these for a different-sized one. 5749 }; 5750 5751 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 5752 return llvm::makeArrayRef(GCCRegAliases); 5753 } 5754 5755 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5756 #define BUILTIN(ID, TYPE, ATTRS) \ 5757 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5758 #include "clang/Basic/BuiltinsNEON.def" 5759 5760 #define BUILTIN(ID, TYPE, ATTRS) \ 5761 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5762 #include "clang/Basic/BuiltinsAArch64.def" 5763 }; 5764 5765 class AArch64leTargetInfo : public AArch64TargetInfo { 5766 void setDataLayout() override { 5767 if (getTriple().isOSBinFormatMachO()) 5768 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 5769 else 5770 resetDataLayout("e-m:e-i64:64-i128:128-n32:64-S128"); 5771 } 5772 5773 public: 5774 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5775 : AArch64TargetInfo(Triple, Opts) { 5776 BigEndian = false; 5777 } 5778 void getTargetDefines(const LangOptions &Opts, 5779 MacroBuilder &Builder) const override { 5780 Builder.defineMacro("__AARCH64EL__"); 5781 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5782 } 5783 }; 5784 5785 class AArch64beTargetInfo : public AArch64TargetInfo { 5786 void setDataLayout() override { 5787 assert(!getTriple().isOSBinFormatMachO()); 5788 resetDataLayout("E-m:e-i64:64-i128:128-n32:64-S128"); 5789 } 5790 5791 public: 5792 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5793 : AArch64TargetInfo(Triple, Opts) {} 5794 void getTargetDefines(const LangOptions &Opts, 5795 MacroBuilder &Builder) const override { 5796 Builder.defineMacro("__AARCH64EB__"); 5797 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5798 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5799 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5800 } 5801 }; 5802 5803 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5804 protected: 5805 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5806 MacroBuilder &Builder) const override { 5807 Builder.defineMacro("__AARCH64_SIMD__"); 5808 Builder.defineMacro("__ARM64_ARCH_8__"); 5809 Builder.defineMacro("__ARM_NEON__"); 5810 Builder.defineMacro("__LITTLE_ENDIAN__"); 5811 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5812 Builder.defineMacro("__arm64", "1"); 5813 Builder.defineMacro("__arm64__", "1"); 5814 5815 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5816 } 5817 5818 public: 5819 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5820 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 5821 Int64Type = SignedLongLong; 5822 WCharType = SignedInt; 5823 UseSignedCharForObjCBool = false; 5824 5825 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5826 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5827 5828 TheCXXABI.set(TargetCXXABI::iOS64); 5829 } 5830 5831 BuiltinVaListKind getBuiltinVaListKind() const override { 5832 return TargetInfo::CharPtrBuiltinVaList; 5833 } 5834 }; 5835 5836 // Hexagon abstract base class 5837 class HexagonTargetInfo : public TargetInfo { 5838 static const Builtin::Info BuiltinInfo[]; 5839 static const char * const GCCRegNames[]; 5840 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5841 std::string CPU; 5842 bool HasHVX, HasHVXDouble; 5843 5844 public: 5845 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 5846 : TargetInfo(Triple) { 5847 BigEndian = false; 5848 // Specify the vector alignment explicitly. For v512x1, the calculated 5849 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 5850 // the required minimum of 64 bytes. 5851 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 5852 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 5853 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 5854 SizeType = UnsignedInt; 5855 PtrDiffType = SignedInt; 5856 IntPtrType = SignedInt; 5857 5858 // {} in inline assembly are packet specifiers, not assembly variant 5859 // specifiers. 5860 NoAsmVariants = true; 5861 5862 LargeArrayMinWidth = 64; 5863 LargeArrayAlign = 64; 5864 UseBitFieldTypeAlignment = true; 5865 ZeroLengthBitfieldBoundary = 32; 5866 HasHVX = HasHVXDouble = false; 5867 } 5868 5869 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5870 return llvm::makeArrayRef(BuiltinInfo, 5871 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 5872 } 5873 5874 bool validateAsmConstraint(const char *&Name, 5875 TargetInfo::ConstraintInfo &Info) const override { 5876 return true; 5877 } 5878 5879 void getTargetDefines(const LangOptions &Opts, 5880 MacroBuilder &Builder) const override; 5881 5882 bool isCLZForZeroUndef() const override { return false; } 5883 5884 bool hasFeature(StringRef Feature) const override { 5885 return llvm::StringSwitch<bool>(Feature) 5886 .Case("hexagon", true) 5887 .Case("hvx", HasHVX) 5888 .Case("hvx-double", HasHVXDouble) 5889 .Default(false); 5890 } 5891 5892 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5893 StringRef CPU, const std::vector<std::string> &FeaturesVec) 5894 const override; 5895 5896 bool handleTargetFeatures(std::vector<std::string> &Features, 5897 DiagnosticsEngine &Diags) override; 5898 5899 BuiltinVaListKind getBuiltinVaListKind() const override { 5900 return TargetInfo::CharPtrBuiltinVaList; 5901 } 5902 ArrayRef<const char *> getGCCRegNames() const override; 5903 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5904 const char *getClobbers() const override { 5905 return ""; 5906 } 5907 5908 static const char *getHexagonCPUSuffix(StringRef Name) { 5909 return llvm::StringSwitch<const char*>(Name) 5910 .Case("hexagonv4", "4") 5911 .Case("hexagonv5", "5") 5912 .Case("hexagonv55", "55") 5913 .Case("hexagonv60", "60") 5914 .Default(nullptr); 5915 } 5916 5917 bool setCPU(const std::string &Name) override { 5918 if (!getHexagonCPUSuffix(Name)) 5919 return false; 5920 CPU = Name; 5921 return true; 5922 } 5923 5924 int getEHDataRegisterNumber(unsigned RegNo) const override { 5925 return RegNo < 2 ? RegNo : -1; 5926 } 5927 }; 5928 5929 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5930 MacroBuilder &Builder) const { 5931 Builder.defineMacro("__qdsp6__", "1"); 5932 Builder.defineMacro("__hexagon__", "1"); 5933 5934 if (CPU == "hexagonv4") { 5935 Builder.defineMacro("__HEXAGON_V4__"); 5936 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5937 if (Opts.HexagonQdsp6Compat) { 5938 Builder.defineMacro("__QDSP6_V4__"); 5939 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5940 } 5941 } else if (CPU == "hexagonv5") { 5942 Builder.defineMacro("__HEXAGON_V5__"); 5943 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5944 if(Opts.HexagonQdsp6Compat) { 5945 Builder.defineMacro("__QDSP6_V5__"); 5946 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5947 } 5948 } else if (CPU == "hexagonv55") { 5949 Builder.defineMacro("__HEXAGON_V55__"); 5950 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 5951 Builder.defineMacro("__QDSP6_V55__"); 5952 Builder.defineMacro("__QDSP6_ARCH__", "55"); 5953 } else if (CPU == "hexagonv60") { 5954 Builder.defineMacro("__HEXAGON_V60__"); 5955 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 5956 Builder.defineMacro("__QDSP6_V60__"); 5957 Builder.defineMacro("__QDSP6_ARCH__", "60"); 5958 } 5959 5960 if (hasFeature("hvx")) { 5961 Builder.defineMacro("__HVX__"); 5962 if (hasFeature("hvx-double")) 5963 Builder.defineMacro("__HVXDBL__"); 5964 } 5965 } 5966 5967 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 5968 DiagnosticsEngine &Diags) { 5969 for (auto &F : Features) { 5970 if (F == "+hvx") 5971 HasHVX = true; 5972 else if (F == "-hvx") 5973 HasHVX = HasHVXDouble = false; 5974 else if (F == "+hvx-double") 5975 HasHVX = HasHVXDouble = true; 5976 else if (F == "-hvx-double") 5977 HasHVXDouble = false; 5978 } 5979 return true; 5980 } 5981 5982 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 5983 DiagnosticsEngine &Diags, StringRef CPU, 5984 const std::vector<std::string> &FeaturesVec) const { 5985 // Default for v60: -hvx, -hvx-double. 5986 Features["hvx"] = false; 5987 Features["hvx-double"] = false; 5988 5989 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5990 } 5991 5992 5993 const char *const HexagonTargetInfo::GCCRegNames[] = { 5994 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5995 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5996 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5997 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5998 "p0", "p1", "p2", "p3", 5999 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6000 }; 6001 6002 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6003 return llvm::makeArrayRef(GCCRegNames); 6004 } 6005 6006 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6007 { { "sp" }, "r29" }, 6008 { { "fp" }, "r30" }, 6009 { { "lr" }, "r31" }, 6010 }; 6011 6012 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6013 return llvm::makeArrayRef(GCCRegAliases); 6014 } 6015 6016 6017 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6018 #define BUILTIN(ID, TYPE, ATTRS) \ 6019 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6020 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6021 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6022 #include "clang/Basic/BuiltinsHexagon.def" 6023 }; 6024 6025 class LanaiTargetInfo : public TargetInfo { 6026 // Class for Lanai (32-bit). 6027 // The CPU profiles supported by the Lanai backend 6028 enum CPUKind { 6029 CK_NONE, 6030 CK_V11, 6031 } CPU; 6032 6033 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6034 static const char *const GCCRegNames[]; 6035 6036 public: 6037 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6038 : TargetInfo(Triple) { 6039 // Description string has to be kept in sync with backend. 6040 resetDataLayout("E" // Big endian 6041 "-m:e" // ELF name manging 6042 "-p:32:32" // 32 bit pointers, 32 bit aligned 6043 "-i64:64" // 64 bit integers, 64 bit aligned 6044 "-a:0:32" // 32 bit alignment of objects of aggregate type 6045 "-n32" // 32 bit native integer width 6046 "-S64" // 64 bit natural stack alignment 6047 ); 6048 6049 // Setting RegParmMax equal to what mregparm was set to in the old 6050 // toolchain 6051 RegParmMax = 4; 6052 6053 // Set the default CPU to V11 6054 CPU = CK_V11; 6055 6056 // Temporary approach to make everything at least word-aligned and allow for 6057 // safely casting between pointers with different alignment requirements. 6058 // TODO: Remove this when there are no more cast align warnings on the 6059 // firmware. 6060 MinGlobalAlign = 32; 6061 } 6062 6063 void getTargetDefines(const LangOptions &Opts, 6064 MacroBuilder &Builder) const override { 6065 // Define __lanai__ when building for target lanai. 6066 Builder.defineMacro("__lanai__"); 6067 6068 // Set define for the CPU specified. 6069 switch (CPU) { 6070 case CK_V11: 6071 Builder.defineMacro("__LANAI_V11__"); 6072 break; 6073 case CK_NONE: 6074 llvm_unreachable("Unhandled target CPU"); 6075 } 6076 } 6077 6078 bool setCPU(const std::string &Name) override { 6079 CPU = llvm::StringSwitch<CPUKind>(Name) 6080 .Case("v11", CK_V11) 6081 .Default(CK_NONE); 6082 6083 return CPU != CK_NONE; 6084 } 6085 6086 bool hasFeature(StringRef Feature) const override { 6087 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6088 } 6089 6090 ArrayRef<const char *> getGCCRegNames() const override; 6091 6092 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6093 6094 BuiltinVaListKind getBuiltinVaListKind() const override { 6095 return TargetInfo::VoidPtrBuiltinVaList; 6096 } 6097 6098 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6099 6100 bool validateAsmConstraint(const char *&Name, 6101 TargetInfo::ConstraintInfo &info) const override { 6102 return false; 6103 } 6104 6105 const char *getClobbers() const override { return ""; } 6106 }; 6107 6108 const char *const LanaiTargetInfo::GCCRegNames[] = { 6109 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6110 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6111 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6112 6113 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6114 return llvm::makeArrayRef(GCCRegNames); 6115 } 6116 6117 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6118 {{"pc"}, "r2"}, 6119 {{"sp"}, "r4"}, 6120 {{"fp"}, "r5"}, 6121 {{"rv"}, "r8"}, 6122 {{"rr1"}, "r10"}, 6123 {{"rr2"}, "r11"}, 6124 {{"rca"}, "r15"}, 6125 }; 6126 6127 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6128 return llvm::makeArrayRef(GCCRegAliases); 6129 } 6130 6131 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6132 class SparcTargetInfo : public TargetInfo { 6133 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6134 static const char * const GCCRegNames[]; 6135 bool SoftFloat; 6136 public: 6137 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6138 : TargetInfo(Triple), SoftFloat(false) {} 6139 6140 int getEHDataRegisterNumber(unsigned RegNo) const override { 6141 if (RegNo == 0) return 24; 6142 if (RegNo == 1) return 25; 6143 return -1; 6144 } 6145 6146 bool handleTargetFeatures(std::vector<std::string> &Features, 6147 DiagnosticsEngine &Diags) override { 6148 // The backend doesn't actually handle soft float yet, but in case someone 6149 // is using the support for the front end continue to support it. 6150 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6151 if (Feature != Features.end()) { 6152 SoftFloat = true; 6153 Features.erase(Feature); 6154 } 6155 return true; 6156 } 6157 void getTargetDefines(const LangOptions &Opts, 6158 MacroBuilder &Builder) const override { 6159 DefineStd(Builder, "sparc", Opts); 6160 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6161 6162 if (SoftFloat) 6163 Builder.defineMacro("SOFT_FLOAT", "1"); 6164 } 6165 6166 bool hasFeature(StringRef Feature) const override { 6167 return llvm::StringSwitch<bool>(Feature) 6168 .Case("softfloat", SoftFloat) 6169 .Case("sparc", true) 6170 .Default(false); 6171 } 6172 6173 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6174 // FIXME: Implement! 6175 return None; 6176 } 6177 BuiltinVaListKind getBuiltinVaListKind() const override { 6178 return TargetInfo::VoidPtrBuiltinVaList; 6179 } 6180 ArrayRef<const char *> getGCCRegNames() const override; 6181 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6182 bool validateAsmConstraint(const char *&Name, 6183 TargetInfo::ConstraintInfo &info) const override { 6184 // FIXME: Implement! 6185 switch (*Name) { 6186 case 'I': // Signed 13-bit constant 6187 case 'J': // Zero 6188 case 'K': // 32-bit constant with the low 12 bits clear 6189 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6190 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6191 case 'N': // Same as 'K' but zext (required for SIMode) 6192 case 'O': // The constant 4096 6193 return true; 6194 } 6195 return false; 6196 } 6197 const char *getClobbers() const override { 6198 // FIXME: Implement! 6199 return ""; 6200 } 6201 6202 // No Sparc V7 for now, the backend doesn't support it anyway. 6203 enum CPUKind { 6204 CK_GENERIC, 6205 CK_V8, 6206 CK_SUPERSPARC, 6207 CK_SPARCLITE, 6208 CK_F934, 6209 CK_HYPERSPARC, 6210 CK_SPARCLITE86X, 6211 CK_SPARCLET, 6212 CK_TSC701, 6213 CK_V9, 6214 CK_ULTRASPARC, 6215 CK_ULTRASPARC3, 6216 CK_NIAGARA, 6217 CK_NIAGARA2, 6218 CK_NIAGARA3, 6219 CK_NIAGARA4, 6220 CK_MYRIAD2_1, 6221 CK_MYRIAD2_2 6222 } CPU = CK_GENERIC; 6223 6224 enum CPUGeneration { 6225 CG_V8, 6226 CG_V9, 6227 }; 6228 6229 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6230 switch (Kind) { 6231 case CK_GENERIC: 6232 case CK_V8: 6233 case CK_SUPERSPARC: 6234 case CK_SPARCLITE: 6235 case CK_F934: 6236 case CK_HYPERSPARC: 6237 case CK_SPARCLITE86X: 6238 case CK_SPARCLET: 6239 case CK_TSC701: 6240 case CK_MYRIAD2_1: 6241 case CK_MYRIAD2_2: 6242 return CG_V8; 6243 case CK_V9: 6244 case CK_ULTRASPARC: 6245 case CK_ULTRASPARC3: 6246 case CK_NIAGARA: 6247 case CK_NIAGARA2: 6248 case CK_NIAGARA3: 6249 case CK_NIAGARA4: 6250 return CG_V9; 6251 } 6252 llvm_unreachable("Unexpected CPU kind"); 6253 } 6254 6255 CPUKind getCPUKind(StringRef Name) const { 6256 return llvm::StringSwitch<CPUKind>(Name) 6257 .Case("v8", CK_V8) 6258 .Case("supersparc", CK_SUPERSPARC) 6259 .Case("sparclite", CK_SPARCLITE) 6260 .Case("f934", CK_F934) 6261 .Case("hypersparc", CK_HYPERSPARC) 6262 .Case("sparclite86x", CK_SPARCLITE86X) 6263 .Case("sparclet", CK_SPARCLET) 6264 .Case("tsc701", CK_TSC701) 6265 .Case("v9", CK_V9) 6266 .Case("ultrasparc", CK_ULTRASPARC) 6267 .Case("ultrasparc3", CK_ULTRASPARC3) 6268 .Case("niagara", CK_NIAGARA) 6269 .Case("niagara2", CK_NIAGARA2) 6270 .Case("niagara3", CK_NIAGARA3) 6271 .Case("niagara4", CK_NIAGARA4) 6272 .Case("myriad2", CK_MYRIAD2_1) 6273 .Case("myriad2.1", CK_MYRIAD2_1) 6274 .Case("myriad2.2", CK_MYRIAD2_2) 6275 .Default(CK_GENERIC); 6276 } 6277 6278 bool setCPU(const std::string &Name) override { 6279 CPU = getCPUKind(Name); 6280 return CPU != CK_GENERIC; 6281 } 6282 }; 6283 6284 const char * const SparcTargetInfo::GCCRegNames[] = { 6285 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6286 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6287 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6288 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6289 }; 6290 6291 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6292 return llvm::makeArrayRef(GCCRegNames); 6293 } 6294 6295 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6296 { { "g0" }, "r0" }, 6297 { { "g1" }, "r1" }, 6298 { { "g2" }, "r2" }, 6299 { { "g3" }, "r3" }, 6300 { { "g4" }, "r4" }, 6301 { { "g5" }, "r5" }, 6302 { { "g6" }, "r6" }, 6303 { { "g7" }, "r7" }, 6304 { { "o0" }, "r8" }, 6305 { { "o1" }, "r9" }, 6306 { { "o2" }, "r10" }, 6307 { { "o3" }, "r11" }, 6308 { { "o4" }, "r12" }, 6309 { { "o5" }, "r13" }, 6310 { { "o6", "sp" }, "r14" }, 6311 { { "o7" }, "r15" }, 6312 { { "l0" }, "r16" }, 6313 { { "l1" }, "r17" }, 6314 { { "l2" }, "r18" }, 6315 { { "l3" }, "r19" }, 6316 { { "l4" }, "r20" }, 6317 { { "l5" }, "r21" }, 6318 { { "l6" }, "r22" }, 6319 { { "l7" }, "r23" }, 6320 { { "i0" }, "r24" }, 6321 { { "i1" }, "r25" }, 6322 { { "i2" }, "r26" }, 6323 { { "i3" }, "r27" }, 6324 { { "i4" }, "r28" }, 6325 { { "i5" }, "r29" }, 6326 { { "i6", "fp" }, "r30" }, 6327 { { "i7" }, "r31" }, 6328 }; 6329 6330 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6331 return llvm::makeArrayRef(GCCRegAliases); 6332 } 6333 6334 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6335 class SparcV8TargetInfo : public SparcTargetInfo { 6336 public: 6337 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6338 : SparcTargetInfo(Triple, Opts) { 6339 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6340 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6341 switch (getTriple().getOS()) { 6342 default: 6343 SizeType = UnsignedInt; 6344 IntPtrType = SignedInt; 6345 PtrDiffType = SignedInt; 6346 break; 6347 case llvm::Triple::NetBSD: 6348 case llvm::Triple::OpenBSD: 6349 SizeType = UnsignedLong; 6350 IntPtrType = SignedLong; 6351 PtrDiffType = SignedLong; 6352 break; 6353 } 6354 } 6355 6356 void getTargetDefines(const LangOptions &Opts, 6357 MacroBuilder &Builder) const override { 6358 SparcTargetInfo::getTargetDefines(Opts, Builder); 6359 switch (getCPUGeneration(CPU)) { 6360 case CG_V8: 6361 Builder.defineMacro("__sparcv8"); 6362 if (getTriple().getOS() != llvm::Triple::Solaris) 6363 Builder.defineMacro("__sparcv8__"); 6364 break; 6365 case CG_V9: 6366 Builder.defineMacro("__sparcv9"); 6367 if (getTriple().getOS() != llvm::Triple::Solaris) { 6368 Builder.defineMacro("__sparcv9__"); 6369 Builder.defineMacro("__sparc_v9__"); 6370 } 6371 break; 6372 } 6373 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6374 switch (CPU) { 6375 case CK_MYRIAD2_1: 6376 Builder.defineMacro("__myriad2", "1"); 6377 Builder.defineMacro("__myriad2__", "1"); 6378 break; 6379 case CK_MYRIAD2_2: 6380 Builder.defineMacro("__myriad2", "2"); 6381 Builder.defineMacro("__myriad2__", "2"); 6382 break; 6383 default: 6384 break; 6385 } 6386 } 6387 } 6388 }; 6389 6390 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6391 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6392 public: 6393 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6394 : SparcV8TargetInfo(Triple, Opts) { 6395 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6396 BigEndian = false; 6397 } 6398 }; 6399 6400 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6401 class SparcV9TargetInfo : public SparcTargetInfo { 6402 public: 6403 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6404 : SparcTargetInfo(Triple, Opts) { 6405 // FIXME: Support Sparc quad-precision long double? 6406 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6407 // This is an LP64 platform. 6408 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6409 6410 // OpenBSD uses long long for int64_t and intmax_t. 6411 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6412 IntMaxType = SignedLongLong; 6413 else 6414 IntMaxType = SignedLong; 6415 Int64Type = IntMaxType; 6416 6417 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6418 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6419 LongDoubleWidth = 128; 6420 LongDoubleAlign = 128; 6421 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6422 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6423 } 6424 6425 void getTargetDefines(const LangOptions &Opts, 6426 MacroBuilder &Builder) const override { 6427 SparcTargetInfo::getTargetDefines(Opts, Builder); 6428 Builder.defineMacro("__sparcv9"); 6429 Builder.defineMacro("__arch64__"); 6430 // Solaris doesn't need these variants, but the BSDs do. 6431 if (getTriple().getOS() != llvm::Triple::Solaris) { 6432 Builder.defineMacro("__sparc64__"); 6433 Builder.defineMacro("__sparc_v9__"); 6434 Builder.defineMacro("__sparcv9__"); 6435 } 6436 } 6437 6438 bool setCPU(const std::string &Name) override { 6439 if (!SparcTargetInfo::setCPU(Name)) 6440 return false; 6441 return getCPUGeneration(CPU) == CG_V9; 6442 } 6443 }; 6444 6445 class SystemZTargetInfo : public TargetInfo { 6446 static const Builtin::Info BuiltinInfo[]; 6447 static const char *const GCCRegNames[]; 6448 std::string CPU; 6449 bool HasTransactionalExecution; 6450 bool HasVector; 6451 6452 public: 6453 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6454 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6455 HasVector(false) { 6456 IntMaxType = SignedLong; 6457 Int64Type = SignedLong; 6458 TLSSupported = true; 6459 IntWidth = IntAlign = 32; 6460 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6461 PointerWidth = PointerAlign = 64; 6462 LongDoubleWidth = 128; 6463 LongDoubleAlign = 64; 6464 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6465 DefaultAlignForAttributeAligned = 64; 6466 MinGlobalAlign = 16; 6467 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 6468 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6469 } 6470 void getTargetDefines(const LangOptions &Opts, 6471 MacroBuilder &Builder) const override { 6472 Builder.defineMacro("__s390__"); 6473 Builder.defineMacro("__s390x__"); 6474 Builder.defineMacro("__zarch__"); 6475 Builder.defineMacro("__LONG_DOUBLE_128__"); 6476 6477 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6478 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6479 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6480 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6481 6482 if (HasTransactionalExecution) 6483 Builder.defineMacro("__HTM__"); 6484 if (Opts.ZVector) 6485 Builder.defineMacro("__VEC__", "10301"); 6486 } 6487 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6488 return llvm::makeArrayRef(BuiltinInfo, 6489 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6490 } 6491 6492 ArrayRef<const char *> getGCCRegNames() const override; 6493 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6494 // No aliases. 6495 return None; 6496 } 6497 bool validateAsmConstraint(const char *&Name, 6498 TargetInfo::ConstraintInfo &info) const override; 6499 const char *getClobbers() const override { 6500 // FIXME: Is this really right? 6501 return ""; 6502 } 6503 BuiltinVaListKind getBuiltinVaListKind() const override { 6504 return TargetInfo::SystemZBuiltinVaList; 6505 } 6506 bool setCPU(const std::string &Name) override { 6507 CPU = Name; 6508 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6509 .Case("z10", true) 6510 .Case("z196", true) 6511 .Case("zEC12", true) 6512 .Case("z13", true) 6513 .Default(false); 6514 6515 return CPUKnown; 6516 } 6517 bool 6518 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6519 StringRef CPU, 6520 const std::vector<std::string> &FeaturesVec) const override { 6521 if (CPU == "zEC12") 6522 Features["transactional-execution"] = true; 6523 if (CPU == "z13") { 6524 Features["transactional-execution"] = true; 6525 Features["vector"] = true; 6526 } 6527 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6528 } 6529 6530 bool handleTargetFeatures(std::vector<std::string> &Features, 6531 DiagnosticsEngine &Diags) override { 6532 HasTransactionalExecution = false; 6533 for (const auto &Feature : Features) { 6534 if (Feature == "+transactional-execution") 6535 HasTransactionalExecution = true; 6536 else if (Feature == "+vector") 6537 HasVector = true; 6538 } 6539 // If we use the vector ABI, vector types are 64-bit aligned. 6540 if (HasVector) { 6541 MaxVectorAlign = 64; 6542 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6543 "-v128:64-a:8:16-n32:64"); 6544 } 6545 return true; 6546 } 6547 6548 bool hasFeature(StringRef Feature) const override { 6549 return llvm::StringSwitch<bool>(Feature) 6550 .Case("systemz", true) 6551 .Case("htm", HasTransactionalExecution) 6552 .Case("vx", HasVector) 6553 .Default(false); 6554 } 6555 6556 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6557 switch (CC) { 6558 case CC_C: 6559 case CC_Swift: 6560 return CCCR_OK; 6561 default: 6562 return CCCR_Warning; 6563 } 6564 } 6565 6566 StringRef getABI() const override { 6567 if (HasVector) 6568 return "vector"; 6569 return ""; 6570 } 6571 6572 bool useFloat128ManglingForLongDouble() const override { 6573 return true; 6574 } 6575 }; 6576 6577 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6578 #define BUILTIN(ID, TYPE, ATTRS) \ 6579 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6580 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 6581 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 6582 #include "clang/Basic/BuiltinsSystemZ.def" 6583 }; 6584 6585 const char *const SystemZTargetInfo::GCCRegNames[] = { 6586 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6587 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6588 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6589 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6590 }; 6591 6592 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6593 return llvm::makeArrayRef(GCCRegNames); 6594 } 6595 6596 bool SystemZTargetInfo:: 6597 validateAsmConstraint(const char *&Name, 6598 TargetInfo::ConstraintInfo &Info) const { 6599 switch (*Name) { 6600 default: 6601 return false; 6602 6603 case 'a': // Address register 6604 case 'd': // Data register (equivalent to 'r') 6605 case 'f': // Floating-point register 6606 Info.setAllowsRegister(); 6607 return true; 6608 6609 case 'I': // Unsigned 8-bit constant 6610 case 'J': // Unsigned 12-bit constant 6611 case 'K': // Signed 16-bit constant 6612 case 'L': // Signed 20-bit displacement (on all targets we support) 6613 case 'M': // 0x7fffffff 6614 return true; 6615 6616 case 'Q': // Memory with base and unsigned 12-bit displacement 6617 case 'R': // Likewise, plus an index 6618 case 'S': // Memory with base and signed 20-bit displacement 6619 case 'T': // Likewise, plus an index 6620 Info.setAllowsMemory(); 6621 return true; 6622 } 6623 } 6624 6625 class MSP430TargetInfo : public TargetInfo { 6626 static const char *const GCCRegNames[]; 6627 6628 public: 6629 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6630 : TargetInfo(Triple) { 6631 BigEndian = false; 6632 TLSSupported = false; 6633 IntWidth = 16; 6634 IntAlign = 16; 6635 LongWidth = 32; 6636 LongLongWidth = 64; 6637 LongAlign = LongLongAlign = 16; 6638 PointerWidth = 16; 6639 PointerAlign = 16; 6640 SuitableAlign = 16; 6641 SizeType = UnsignedInt; 6642 IntMaxType = SignedLongLong; 6643 IntPtrType = SignedInt; 6644 PtrDiffType = SignedInt; 6645 SigAtomicType = SignedLong; 6646 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 6647 } 6648 void getTargetDefines(const LangOptions &Opts, 6649 MacroBuilder &Builder) const override { 6650 Builder.defineMacro("MSP430"); 6651 Builder.defineMacro("__MSP430__"); 6652 // FIXME: defines for different 'flavours' of MCU 6653 } 6654 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6655 // FIXME: Implement. 6656 return None; 6657 } 6658 bool hasFeature(StringRef Feature) const override { 6659 return Feature == "msp430"; 6660 } 6661 ArrayRef<const char *> getGCCRegNames() const override; 6662 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6663 // No aliases. 6664 return None; 6665 } 6666 bool validateAsmConstraint(const char *&Name, 6667 TargetInfo::ConstraintInfo &info) const override { 6668 // FIXME: implement 6669 switch (*Name) { 6670 case 'K': // the constant 1 6671 case 'L': // constant -1^20 .. 1^19 6672 case 'M': // constant 1-4: 6673 return true; 6674 } 6675 // No target constraints for now. 6676 return false; 6677 } 6678 const char *getClobbers() const override { 6679 // FIXME: Is this really right? 6680 return ""; 6681 } 6682 BuiltinVaListKind getBuiltinVaListKind() const override { 6683 // FIXME: implement 6684 return TargetInfo::CharPtrBuiltinVaList; 6685 } 6686 }; 6687 6688 const char *const MSP430TargetInfo::GCCRegNames[] = { 6689 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6690 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6691 6692 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 6693 return llvm::makeArrayRef(GCCRegNames); 6694 } 6695 6696 // LLVM and Clang cannot be used directly to output native binaries for 6697 // target, but is used to compile C code to llvm bitcode with correct 6698 // type and alignment information. 6699 // 6700 // TCE uses the llvm bitcode as input and uses it for generating customized 6701 // target processor and program binary. TCE co-design environment is 6702 // publicly available in http://tce.cs.tut.fi 6703 6704 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6705 3, // opencl_global 6706 4, // opencl_local 6707 5, // opencl_constant 6708 // FIXME: generic has to be added to the target 6709 0, // opencl_generic 6710 0, // cuda_device 6711 0, // cuda_constant 6712 0 // cuda_shared 6713 }; 6714 6715 class TCETargetInfo : public TargetInfo { 6716 public: 6717 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6718 : TargetInfo(Triple) { 6719 TLSSupported = false; 6720 IntWidth = 32; 6721 LongWidth = LongLongWidth = 32; 6722 PointerWidth = 32; 6723 IntAlign = 32; 6724 LongAlign = LongLongAlign = 32; 6725 PointerAlign = 32; 6726 SuitableAlign = 32; 6727 SizeType = UnsignedInt; 6728 IntMaxType = SignedLong; 6729 IntPtrType = SignedInt; 6730 PtrDiffType = SignedInt; 6731 FloatWidth = 32; 6732 FloatAlign = 32; 6733 DoubleWidth = 32; 6734 DoubleAlign = 32; 6735 LongDoubleWidth = 32; 6736 LongDoubleAlign = 32; 6737 FloatFormat = &llvm::APFloat::IEEEsingle; 6738 DoubleFormat = &llvm::APFloat::IEEEsingle; 6739 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6740 resetDataLayout("E-p:32:32-i8:8:32-i16:16:32-i64:32" 6741 "-f64:32-v64:32-v128:32-a:0:32-n32"); 6742 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6743 UseAddrSpaceMapMangling = true; 6744 } 6745 6746 void getTargetDefines(const LangOptions &Opts, 6747 MacroBuilder &Builder) const override { 6748 DefineStd(Builder, "tce", Opts); 6749 Builder.defineMacro("__TCE__"); 6750 Builder.defineMacro("__TCE_V1__"); 6751 } 6752 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 6753 6754 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6755 const char *getClobbers() const override { return ""; } 6756 BuiltinVaListKind getBuiltinVaListKind() const override { 6757 return TargetInfo::VoidPtrBuiltinVaList; 6758 } 6759 ArrayRef<const char *> getGCCRegNames() const override { return None; } 6760 bool validateAsmConstraint(const char *&Name, 6761 TargetInfo::ConstraintInfo &info) const override { 6762 return true; 6763 } 6764 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6765 return None; 6766 } 6767 }; 6768 6769 class BPFTargetInfo : public TargetInfo { 6770 public: 6771 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6772 : TargetInfo(Triple) { 6773 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6774 SizeType = UnsignedLong; 6775 PtrDiffType = SignedLong; 6776 IntPtrType = SignedLong; 6777 IntMaxType = SignedLong; 6778 Int64Type = SignedLong; 6779 RegParmMax = 5; 6780 if (Triple.getArch() == llvm::Triple::bpfeb) { 6781 BigEndian = true; 6782 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 6783 } else { 6784 BigEndian = false; 6785 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 6786 } 6787 MaxAtomicPromoteWidth = 64; 6788 MaxAtomicInlineWidth = 64; 6789 TLSSupported = false; 6790 } 6791 void getTargetDefines(const LangOptions &Opts, 6792 MacroBuilder &Builder) const override { 6793 DefineStd(Builder, "bpf", Opts); 6794 Builder.defineMacro("__BPF__"); 6795 } 6796 bool hasFeature(StringRef Feature) const override { 6797 return Feature == "bpf"; 6798 } 6799 6800 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6801 const char *getClobbers() const override { 6802 return ""; 6803 } 6804 BuiltinVaListKind getBuiltinVaListKind() const override { 6805 return TargetInfo::VoidPtrBuiltinVaList; 6806 } 6807 ArrayRef<const char *> getGCCRegNames() const override { 6808 return None; 6809 } 6810 bool validateAsmConstraint(const char *&Name, 6811 TargetInfo::ConstraintInfo &info) const override { 6812 return true; 6813 } 6814 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6815 return None; 6816 } 6817 }; 6818 6819 class MipsTargetInfoBase : public TargetInfo { 6820 virtual void setDataLayout() = 0; 6821 6822 static const Builtin::Info BuiltinInfo[]; 6823 std::string CPU; 6824 bool IsMips16; 6825 bool IsMicromips; 6826 bool IsNan2008; 6827 bool IsSingleFloat; 6828 enum MipsFloatABI { 6829 HardFloat, SoftFloat 6830 } FloatABI; 6831 enum DspRevEnum { 6832 NoDSP, DSP1, DSP2 6833 } DspRev; 6834 bool HasMSA; 6835 6836 protected: 6837 bool HasFP64; 6838 std::string ABI; 6839 6840 public: 6841 MipsTargetInfoBase(const llvm::Triple &Triple, const TargetOptions &, 6842 const std::string &ABIStr, const std::string &CPUStr) 6843 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6844 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6845 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6846 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6847 } 6848 6849 bool isNaN2008Default() const { 6850 return CPU == "mips32r6" || CPU == "mips64r6"; 6851 } 6852 6853 bool isFP64Default() const { 6854 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6855 } 6856 6857 bool isNan2008() const override { 6858 return IsNan2008; 6859 } 6860 6861 StringRef getABI() const override { return ABI; } 6862 bool setCPU(const std::string &Name) override { 6863 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6864 getTriple().getArch() == llvm::Triple::mipsel; 6865 CPU = Name; 6866 return llvm::StringSwitch<bool>(Name) 6867 .Case("mips1", IsMips32) 6868 .Case("mips2", IsMips32) 6869 .Case("mips3", true) 6870 .Case("mips4", true) 6871 .Case("mips5", true) 6872 .Case("mips32", IsMips32) 6873 .Case("mips32r2", IsMips32) 6874 .Case("mips32r3", IsMips32) 6875 .Case("mips32r5", IsMips32) 6876 .Case("mips32r6", IsMips32) 6877 .Case("mips64", true) 6878 .Case("mips64r2", true) 6879 .Case("mips64r3", true) 6880 .Case("mips64r5", true) 6881 .Case("mips64r6", true) 6882 .Case("octeon", true) 6883 .Case("p5600", true) 6884 .Default(false); 6885 } 6886 const std::string& getCPU() const { return CPU; } 6887 bool 6888 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6889 StringRef CPU, 6890 const std::vector<std::string> &FeaturesVec) const override { 6891 if (CPU.empty()) 6892 CPU = getCPU(); 6893 if (CPU == "octeon") 6894 Features["mips64r2"] = Features["cnmips"] = true; 6895 else 6896 Features[CPU] = true; 6897 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6898 } 6899 6900 void getTargetDefines(const LangOptions &Opts, 6901 MacroBuilder &Builder) const override { 6902 Builder.defineMacro("__mips__"); 6903 Builder.defineMacro("_mips"); 6904 if (Opts.GNUMode) 6905 Builder.defineMacro("mips"); 6906 6907 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6908 6909 switch (FloatABI) { 6910 case HardFloat: 6911 Builder.defineMacro("__mips_hard_float", Twine(1)); 6912 break; 6913 case SoftFloat: 6914 Builder.defineMacro("__mips_soft_float", Twine(1)); 6915 break; 6916 } 6917 6918 if (IsSingleFloat) 6919 Builder.defineMacro("__mips_single_float", Twine(1)); 6920 6921 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6922 Builder.defineMacro("_MIPS_FPSET", 6923 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6924 6925 if (IsMips16) 6926 Builder.defineMacro("__mips16", Twine(1)); 6927 6928 if (IsMicromips) 6929 Builder.defineMacro("__mips_micromips", Twine(1)); 6930 6931 if (IsNan2008) 6932 Builder.defineMacro("__mips_nan2008", Twine(1)); 6933 6934 switch (DspRev) { 6935 default: 6936 break; 6937 case DSP1: 6938 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6939 Builder.defineMacro("__mips_dsp", Twine(1)); 6940 break; 6941 case DSP2: 6942 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6943 Builder.defineMacro("__mips_dspr2", Twine(1)); 6944 Builder.defineMacro("__mips_dsp", Twine(1)); 6945 break; 6946 } 6947 6948 if (HasMSA) 6949 Builder.defineMacro("__mips_msa", Twine(1)); 6950 6951 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6952 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6953 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6954 6955 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6956 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6957 6958 // These shouldn't be defined for MIPS-I but there's no need to check 6959 // for that since MIPS-I isn't supported. 6960 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6961 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6962 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6963 } 6964 6965 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6966 return llvm::makeArrayRef(BuiltinInfo, 6967 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 6968 } 6969 bool hasFeature(StringRef Feature) const override { 6970 return llvm::StringSwitch<bool>(Feature) 6971 .Case("mips", true) 6972 .Case("fp64", HasFP64) 6973 .Default(false); 6974 } 6975 BuiltinVaListKind getBuiltinVaListKind() const override { 6976 return TargetInfo::VoidPtrBuiltinVaList; 6977 } 6978 ArrayRef<const char *> getGCCRegNames() const override { 6979 static const char *const GCCRegNames[] = { 6980 // CPU register names 6981 // Must match second column of GCCRegAliases 6982 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6983 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6984 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6985 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6986 // Floating point register names 6987 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6988 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6989 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6990 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6991 // Hi/lo and condition register names 6992 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6993 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 6994 "$ac3hi","$ac3lo", 6995 // MSA register names 6996 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6997 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6998 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6999 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7000 // MSA control register names 7001 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7002 "$msarequest", "$msamap", "$msaunmap" 7003 }; 7004 return llvm::makeArrayRef(GCCRegNames); 7005 } 7006 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override = 0; 7007 bool validateAsmConstraint(const char *&Name, 7008 TargetInfo::ConstraintInfo &Info) const override { 7009 switch (*Name) { 7010 default: 7011 return false; 7012 case 'r': // CPU registers. 7013 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7014 case 'y': // Equivalent to "r", backward compatibility only. 7015 case 'f': // floating-point registers. 7016 case 'c': // $25 for indirect jumps 7017 case 'l': // lo register 7018 case 'x': // hilo register pair 7019 Info.setAllowsRegister(); 7020 return true; 7021 case 'I': // Signed 16-bit constant 7022 case 'J': // Integer 0 7023 case 'K': // Unsigned 16-bit constant 7024 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7025 case 'M': // Constants not loadable via lui, addiu, or ori 7026 case 'N': // Constant -1 to -65535 7027 case 'O': // A signed 15-bit constant 7028 case 'P': // A constant between 1 go 65535 7029 return true; 7030 case 'R': // An address that can be used in a non-macro load or store 7031 Info.setAllowsMemory(); 7032 return true; 7033 case 'Z': 7034 if (Name[1] == 'C') { // An address usable by ll, and sc. 7035 Info.setAllowsMemory(); 7036 Name++; // Skip over 'Z'. 7037 return true; 7038 } 7039 return false; 7040 } 7041 } 7042 7043 std::string convertConstraint(const char *&Constraint) const override { 7044 std::string R; 7045 switch (*Constraint) { 7046 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7047 if (Constraint[1] == 'C') { 7048 R = std::string("^") + std::string(Constraint, 2); 7049 Constraint++; 7050 return R; 7051 } 7052 break; 7053 } 7054 return TargetInfo::convertConstraint(Constraint); 7055 } 7056 7057 const char *getClobbers() const override { 7058 // In GCC, $1 is not widely used in generated code (it's used only in a few 7059 // specific situations), so there is no real need for users to add it to 7060 // the clobbers list if they want to use it in their inline assembly code. 7061 // 7062 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7063 // code generation, so using it in inline assembly without adding it to the 7064 // clobbers list can cause conflicts between the inline assembly code and 7065 // the surrounding generated code. 7066 // 7067 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7068 // operands, which will conflict with the ".set at" assembler option (which 7069 // we use only for inline assembly, in order to maintain compatibility with 7070 // GCC) and will also conflict with the user's usage of $1. 7071 // 7072 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7073 // register for generated code is to automatically clobber $1 for all inline 7074 // assembly code. 7075 // 7076 // FIXME: We should automatically clobber $1 only for inline assembly code 7077 // which actually uses it. This would allow LLVM to use $1 for inline 7078 // assembly operands if the user's assembly code doesn't use it. 7079 return "~{$1}"; 7080 } 7081 7082 bool handleTargetFeatures(std::vector<std::string> &Features, 7083 DiagnosticsEngine &Diags) override { 7084 IsMips16 = false; 7085 IsMicromips = false; 7086 IsNan2008 = isNaN2008Default(); 7087 IsSingleFloat = false; 7088 FloatABI = HardFloat; 7089 DspRev = NoDSP; 7090 HasFP64 = isFP64Default(); 7091 7092 for (const auto &Feature : Features) { 7093 if (Feature == "+single-float") 7094 IsSingleFloat = true; 7095 else if (Feature == "+soft-float") 7096 FloatABI = SoftFloat; 7097 else if (Feature == "+mips16") 7098 IsMips16 = true; 7099 else if (Feature == "+micromips") 7100 IsMicromips = true; 7101 else if (Feature == "+dsp") 7102 DspRev = std::max(DspRev, DSP1); 7103 else if (Feature == "+dspr2") 7104 DspRev = std::max(DspRev, DSP2); 7105 else if (Feature == "+msa") 7106 HasMSA = true; 7107 else if (Feature == "+fp64") 7108 HasFP64 = true; 7109 else if (Feature == "-fp64") 7110 HasFP64 = false; 7111 else if (Feature == "+nan2008") 7112 IsNan2008 = true; 7113 else if (Feature == "-nan2008") 7114 IsNan2008 = false; 7115 } 7116 7117 setDataLayout(); 7118 7119 return true; 7120 } 7121 7122 int getEHDataRegisterNumber(unsigned RegNo) const override { 7123 if (RegNo == 0) return 4; 7124 if (RegNo == 1) return 5; 7125 return -1; 7126 } 7127 7128 bool isCLZForZeroUndef() const override { return false; } 7129 }; 7130 7131 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 7132 #define BUILTIN(ID, TYPE, ATTRS) \ 7133 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7134 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7135 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7136 #include "clang/Basic/BuiltinsMips.def" 7137 }; 7138 7139 class Mips32TargetInfoBase : public MipsTargetInfoBase { 7140 public: 7141 Mips32TargetInfoBase(const llvm::Triple &Triple, const TargetOptions &Opts) 7142 : MipsTargetInfoBase(Triple, Opts, "o32", "mips32r2") { 7143 SizeType = UnsignedInt; 7144 PtrDiffType = SignedInt; 7145 Int64Type = SignedLongLong; 7146 IntMaxType = Int64Type; 7147 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7148 } 7149 bool setABI(const std::string &Name) override { 7150 if (Name == "o32" || Name == "eabi") { 7151 ABI = Name; 7152 return true; 7153 } 7154 return false; 7155 } 7156 void getTargetDefines(const LangOptions &Opts, 7157 MacroBuilder &Builder) const override { 7158 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 7159 7160 Builder.defineMacro("__mips", "32"); 7161 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7162 7163 const std::string& CPUStr = getCPU(); 7164 if (CPUStr == "mips32") 7165 Builder.defineMacro("__mips_isa_rev", "1"); 7166 else if (CPUStr == "mips32r2") 7167 Builder.defineMacro("__mips_isa_rev", "2"); 7168 else if (CPUStr == "mips32r3") 7169 Builder.defineMacro("__mips_isa_rev", "3"); 7170 else if (CPUStr == "mips32r5") 7171 Builder.defineMacro("__mips_isa_rev", "5"); 7172 else if (CPUStr == "mips32r6") 7173 Builder.defineMacro("__mips_isa_rev", "6"); 7174 7175 if (ABI == "o32") { 7176 Builder.defineMacro("__mips_o32"); 7177 Builder.defineMacro("_ABIO32", "1"); 7178 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7179 } 7180 else if (ABI == "eabi") 7181 Builder.defineMacro("__mips_eabi"); 7182 else 7183 llvm_unreachable("Invalid ABI for Mips32."); 7184 } 7185 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7186 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 7187 { { "at" }, "$1" }, 7188 { { "v0" }, "$2" }, 7189 { { "v1" }, "$3" }, 7190 { { "a0" }, "$4" }, 7191 { { "a1" }, "$5" }, 7192 { { "a2" }, "$6" }, 7193 { { "a3" }, "$7" }, 7194 { { "t0" }, "$8" }, 7195 { { "t1" }, "$9" }, 7196 { { "t2" }, "$10" }, 7197 { { "t3" }, "$11" }, 7198 { { "t4" }, "$12" }, 7199 { { "t5" }, "$13" }, 7200 { { "t6" }, "$14" }, 7201 { { "t7" }, "$15" }, 7202 { { "s0" }, "$16" }, 7203 { { "s1" }, "$17" }, 7204 { { "s2" }, "$18" }, 7205 { { "s3" }, "$19" }, 7206 { { "s4" }, "$20" }, 7207 { { "s5" }, "$21" }, 7208 { { "s6" }, "$22" }, 7209 { { "s7" }, "$23" }, 7210 { { "t8" }, "$24" }, 7211 { { "t9" }, "$25" }, 7212 { { "k0" }, "$26" }, 7213 { { "k1" }, "$27" }, 7214 { { "gp" }, "$28" }, 7215 { { "sp","$sp" }, "$29" }, 7216 { { "fp","$fp" }, "$30" }, 7217 { { "ra" }, "$31" } 7218 }; 7219 return llvm::makeArrayRef(GCCRegAliases); 7220 } 7221 }; 7222 7223 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 7224 void setDataLayout() override { 7225 resetDataLayout("E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"); 7226 } 7227 7228 public: 7229 Mips32EBTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7230 : Mips32TargetInfoBase(Triple, Opts) { 7231 } 7232 void getTargetDefines(const LangOptions &Opts, 7233 MacroBuilder &Builder) const override { 7234 DefineStd(Builder, "MIPSEB", Opts); 7235 Builder.defineMacro("_MIPSEB"); 7236 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 7237 } 7238 }; 7239 7240 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 7241 void setDataLayout() override { 7242 resetDataLayout("e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"); 7243 } 7244 7245 public: 7246 Mips32ELTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7247 : Mips32TargetInfoBase(Triple, Opts) { 7248 BigEndian = false; 7249 } 7250 void getTargetDefines(const LangOptions &Opts, 7251 MacroBuilder &Builder) const override { 7252 DefineStd(Builder, "MIPSEL", Opts); 7253 Builder.defineMacro("_MIPSEL"); 7254 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 7255 } 7256 }; 7257 7258 class Mips64TargetInfoBase : public MipsTargetInfoBase { 7259 public: 7260 Mips64TargetInfoBase(const llvm::Triple &Triple, const TargetOptions &Opts) 7261 : MipsTargetInfoBase(Triple, Opts, "n64", "mips64r2") { 7262 LongDoubleWidth = LongDoubleAlign = 128; 7263 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7264 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7265 LongDoubleWidth = LongDoubleAlign = 64; 7266 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7267 } 7268 setN64ABITypes(); 7269 SuitableAlign = 128; 7270 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7271 } 7272 7273 void setN64ABITypes() { 7274 LongWidth = LongAlign = 64; 7275 PointerWidth = PointerAlign = 64; 7276 SizeType = UnsignedLong; 7277 PtrDiffType = SignedLong; 7278 Int64Type = SignedLong; 7279 IntMaxType = Int64Type; 7280 } 7281 7282 void setN32ABITypes() { 7283 LongWidth = LongAlign = 32; 7284 PointerWidth = PointerAlign = 32; 7285 SizeType = UnsignedInt; 7286 PtrDiffType = SignedInt; 7287 Int64Type = SignedLongLong; 7288 IntMaxType = Int64Type; 7289 } 7290 7291 bool setABI(const std::string &Name) override { 7292 if (Name == "n32") { 7293 setN32ABITypes(); 7294 ABI = Name; 7295 return true; 7296 } 7297 if (Name == "n64") { 7298 setN64ABITypes(); 7299 ABI = Name; 7300 return true; 7301 } 7302 return false; 7303 } 7304 7305 void getTargetDefines(const LangOptions &Opts, 7306 MacroBuilder &Builder) const override { 7307 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 7308 7309 Builder.defineMacro("__mips", "64"); 7310 Builder.defineMacro("__mips64"); 7311 Builder.defineMacro("__mips64__"); 7312 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7313 7314 const std::string& CPUStr = getCPU(); 7315 if (CPUStr == "mips64") 7316 Builder.defineMacro("__mips_isa_rev", "1"); 7317 else if (CPUStr == "mips64r2") 7318 Builder.defineMacro("__mips_isa_rev", "2"); 7319 else if (CPUStr == "mips64r3") 7320 Builder.defineMacro("__mips_isa_rev", "3"); 7321 else if (CPUStr == "mips64r5") 7322 Builder.defineMacro("__mips_isa_rev", "5"); 7323 else if (CPUStr == "mips64r6") 7324 Builder.defineMacro("__mips_isa_rev", "6"); 7325 7326 if (ABI == "n32") { 7327 Builder.defineMacro("__mips_n32"); 7328 Builder.defineMacro("_ABIN32", "2"); 7329 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7330 } 7331 else if (ABI == "n64") { 7332 Builder.defineMacro("__mips_n64"); 7333 Builder.defineMacro("_ABI64", "3"); 7334 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7335 } 7336 else 7337 llvm_unreachable("Invalid ABI for Mips64."); 7338 7339 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7340 } 7341 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7342 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 7343 { { "at" }, "$1" }, 7344 { { "v0" }, "$2" }, 7345 { { "v1" }, "$3" }, 7346 { { "a0" }, "$4" }, 7347 { { "a1" }, "$5" }, 7348 { { "a2" }, "$6" }, 7349 { { "a3" }, "$7" }, 7350 { { "a4" }, "$8" }, 7351 { { "a5" }, "$9" }, 7352 { { "a6" }, "$10" }, 7353 { { "a7" }, "$11" }, 7354 { { "t0" }, "$12" }, 7355 { { "t1" }, "$13" }, 7356 { { "t2" }, "$14" }, 7357 { { "t3" }, "$15" }, 7358 { { "s0" }, "$16" }, 7359 { { "s1" }, "$17" }, 7360 { { "s2" }, "$18" }, 7361 { { "s3" }, "$19" }, 7362 { { "s4" }, "$20" }, 7363 { { "s5" }, "$21" }, 7364 { { "s6" }, "$22" }, 7365 { { "s7" }, "$23" }, 7366 { { "t8" }, "$24" }, 7367 { { "t9" }, "$25" }, 7368 { { "k0" }, "$26" }, 7369 { { "k1" }, "$27" }, 7370 { { "gp" }, "$28" }, 7371 { { "sp","$sp" }, "$29" }, 7372 { { "fp","$fp" }, "$30" }, 7373 { { "ra" }, "$31" } 7374 }; 7375 return llvm::makeArrayRef(GCCRegAliases); 7376 } 7377 7378 bool hasInt128Type() const override { return true; } 7379 }; 7380 7381 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 7382 void setDataLayout() override { 7383 if (ABI == "n32") 7384 resetDataLayout("E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7385 else 7386 resetDataLayout("E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7387 } 7388 7389 public: 7390 Mips64EBTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7391 : Mips64TargetInfoBase(Triple, Opts) {} 7392 void getTargetDefines(const LangOptions &Opts, 7393 MacroBuilder &Builder) const override { 7394 DefineStd(Builder, "MIPSEB", Opts); 7395 Builder.defineMacro("_MIPSEB"); 7396 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7397 } 7398 }; 7399 7400 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 7401 void setDataLayout() override { 7402 if (ABI == "n32") 7403 resetDataLayout("e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7404 else 7405 resetDataLayout("e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7406 } 7407 public: 7408 Mips64ELTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7409 : Mips64TargetInfoBase(Triple, Opts) { 7410 // Default ABI is n64. 7411 BigEndian = false; 7412 } 7413 void getTargetDefines(const LangOptions &Opts, 7414 MacroBuilder &Builder) const override { 7415 DefineStd(Builder, "MIPSEL", Opts); 7416 Builder.defineMacro("_MIPSEL"); 7417 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7418 } 7419 }; 7420 7421 class PNaClTargetInfo : public TargetInfo { 7422 public: 7423 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7424 : TargetInfo(Triple) { 7425 BigEndian = false; 7426 this->LongAlign = 32; 7427 this->LongWidth = 32; 7428 this->PointerAlign = 32; 7429 this->PointerWidth = 32; 7430 this->IntMaxType = TargetInfo::SignedLongLong; 7431 this->Int64Type = TargetInfo::SignedLongLong; 7432 this->DoubleAlign = 64; 7433 this->LongDoubleWidth = 64; 7434 this->LongDoubleAlign = 64; 7435 this->SizeType = TargetInfo::UnsignedInt; 7436 this->PtrDiffType = TargetInfo::SignedInt; 7437 this->IntPtrType = TargetInfo::SignedInt; 7438 this->RegParmMax = 0; // Disallow regparm 7439 } 7440 7441 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7442 Builder.defineMacro("__le32__"); 7443 Builder.defineMacro("__pnacl__"); 7444 } 7445 void getTargetDefines(const LangOptions &Opts, 7446 MacroBuilder &Builder) const override { 7447 getArchDefines(Opts, Builder); 7448 } 7449 bool hasFeature(StringRef Feature) const override { 7450 return Feature == "pnacl"; 7451 } 7452 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7453 BuiltinVaListKind getBuiltinVaListKind() const override { 7454 return TargetInfo::PNaClABIBuiltinVaList; 7455 } 7456 ArrayRef<const char *> getGCCRegNames() const override; 7457 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7458 bool validateAsmConstraint(const char *&Name, 7459 TargetInfo::ConstraintInfo &Info) const override { 7460 return false; 7461 } 7462 7463 const char *getClobbers() const override { 7464 return ""; 7465 } 7466 }; 7467 7468 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7469 return None; 7470 } 7471 7472 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7473 return None; 7474 } 7475 7476 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7477 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 7478 public: 7479 NaClMips32ELTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7480 : Mips32ELTargetInfo(Triple, Opts) {} 7481 7482 BuiltinVaListKind getBuiltinVaListKind() const override { 7483 return TargetInfo::PNaClABIBuiltinVaList; 7484 } 7485 }; 7486 7487 class Le64TargetInfo : public TargetInfo { 7488 static const Builtin::Info BuiltinInfo[]; 7489 7490 public: 7491 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7492 : TargetInfo(Triple) { 7493 BigEndian = false; 7494 NoAsmVariants = true; 7495 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7496 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7497 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 7498 } 7499 7500 void getTargetDefines(const LangOptions &Opts, 7501 MacroBuilder &Builder) const override { 7502 DefineStd(Builder, "unix", Opts); 7503 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7504 Builder.defineMacro("__ELF__"); 7505 } 7506 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7507 return llvm::makeArrayRef(BuiltinInfo, 7508 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7509 } 7510 BuiltinVaListKind getBuiltinVaListKind() const override { 7511 return TargetInfo::PNaClABIBuiltinVaList; 7512 } 7513 const char *getClobbers() const override { return ""; } 7514 ArrayRef<const char *> getGCCRegNames() const override { 7515 return None; 7516 } 7517 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7518 return None; 7519 } 7520 bool validateAsmConstraint(const char *&Name, 7521 TargetInfo::ConstraintInfo &Info) const override { 7522 return false; 7523 } 7524 7525 bool hasProtectedVisibility() const override { return false; } 7526 }; 7527 7528 class WebAssemblyTargetInfo : public TargetInfo { 7529 static const Builtin::Info BuiltinInfo[]; 7530 7531 enum SIMDEnum { 7532 NoSIMD, 7533 SIMD128, 7534 } SIMDLevel; 7535 7536 public: 7537 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 7538 : TargetInfo(T), SIMDLevel(NoSIMD) { 7539 BigEndian = false; 7540 NoAsmVariants = true; 7541 SuitableAlign = 128; 7542 LargeArrayMinWidth = 128; 7543 LargeArrayAlign = 128; 7544 SimdDefaultAlign = 128; 7545 SigAtomicType = SignedLong; 7546 LongDoubleWidth = LongDoubleAlign = 128; 7547 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7548 } 7549 7550 protected: 7551 void getTargetDefines(const LangOptions &Opts, 7552 MacroBuilder &Builder) const override { 7553 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7554 if (SIMDLevel >= SIMD128) 7555 Builder.defineMacro("__wasm_simd128__"); 7556 } 7557 7558 private: 7559 bool 7560 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7561 StringRef CPU, 7562 const std::vector<std::string> &FeaturesVec) const override { 7563 if (CPU == "bleeding-edge") 7564 Features["simd128"] = true; 7565 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7566 } 7567 bool hasFeature(StringRef Feature) const final { 7568 return llvm::StringSwitch<bool>(Feature) 7569 .Case("simd128", SIMDLevel >= SIMD128) 7570 .Default(false); 7571 } 7572 bool handleTargetFeatures(std::vector<std::string> &Features, 7573 DiagnosticsEngine &Diags) final { 7574 for (const auto &Feature : Features) { 7575 if (Feature == "+simd128") { 7576 SIMDLevel = std::max(SIMDLevel, SIMD128); 7577 continue; 7578 } 7579 if (Feature == "-simd128") { 7580 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7581 continue; 7582 } 7583 7584 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7585 << "-target-feature"; 7586 return false; 7587 } 7588 return true; 7589 } 7590 bool setCPU(const std::string &Name) final { 7591 return llvm::StringSwitch<bool>(Name) 7592 .Case("mvp", true) 7593 .Case("bleeding-edge", true) 7594 .Case("generic", true) 7595 .Default(false); 7596 } 7597 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7598 return llvm::makeArrayRef(BuiltinInfo, 7599 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7600 } 7601 BuiltinVaListKind getBuiltinVaListKind() const final { 7602 return VoidPtrBuiltinVaList; 7603 } 7604 ArrayRef<const char *> getGCCRegNames() const final { 7605 return None; 7606 } 7607 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7608 return None; 7609 } 7610 bool 7611 validateAsmConstraint(const char *&Name, 7612 TargetInfo::ConstraintInfo &Info) const final { 7613 return false; 7614 } 7615 const char *getClobbers() const final { return ""; } 7616 bool isCLZForZeroUndef() const final { return false; } 7617 bool hasInt128Type() const final { return true; } 7618 IntType getIntTypeByWidth(unsigned BitWidth, 7619 bool IsSigned) const final { 7620 // WebAssembly prefers long long for explicitly 64-bit integers. 7621 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7622 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7623 } 7624 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7625 bool IsSigned) const final { 7626 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7627 return BitWidth == 64 7628 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7629 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7630 } 7631 }; 7632 7633 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7634 #define BUILTIN(ID, TYPE, ATTRS) \ 7635 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7636 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7637 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7638 #include "clang/Basic/BuiltinsWebAssembly.def" 7639 }; 7640 7641 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7642 public: 7643 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 7644 const TargetOptions &Opts) 7645 : WebAssemblyTargetInfo(T, Opts) { 7646 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7647 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 7648 } 7649 7650 protected: 7651 void getTargetDefines(const LangOptions &Opts, 7652 MacroBuilder &Builder) const override { 7653 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7654 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7655 } 7656 }; 7657 7658 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7659 public: 7660 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 7661 const TargetOptions &Opts) 7662 : WebAssemblyTargetInfo(T, Opts) { 7663 LongAlign = LongWidth = 64; 7664 PointerAlign = PointerWidth = 64; 7665 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7666 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7667 } 7668 7669 protected: 7670 void getTargetDefines(const LangOptions &Opts, 7671 MacroBuilder &Builder) const override { 7672 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7673 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7674 } 7675 }; 7676 7677 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7678 #define BUILTIN(ID, TYPE, ATTRS) \ 7679 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7680 #include "clang/Basic/BuiltinsLe64.def" 7681 }; 7682 7683 static const unsigned SPIRAddrSpaceMap[] = { 7684 1, // opencl_global 7685 3, // opencl_local 7686 2, // opencl_constant 7687 4, // opencl_generic 7688 0, // cuda_device 7689 0, // cuda_constant 7690 0 // cuda_shared 7691 }; 7692 class SPIRTargetInfo : public TargetInfo { 7693 public: 7694 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7695 : TargetInfo(Triple) { 7696 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7697 "SPIR target must use unknown OS"); 7698 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7699 "SPIR target must use unknown environment type"); 7700 BigEndian = false; 7701 TLSSupported = false; 7702 LongWidth = LongAlign = 64; 7703 AddrSpaceMap = &SPIRAddrSpaceMap; 7704 UseAddrSpaceMapMangling = true; 7705 // Define available target features 7706 // These must be defined in sorted order! 7707 NoAsmVariants = true; 7708 } 7709 void getTargetDefines(const LangOptions &Opts, 7710 MacroBuilder &Builder) const override { 7711 DefineStd(Builder, "SPIR", Opts); 7712 } 7713 bool hasFeature(StringRef Feature) const override { 7714 return Feature == "spir"; 7715 } 7716 7717 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7718 const char *getClobbers() const override { return ""; } 7719 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7720 bool validateAsmConstraint(const char *&Name, 7721 TargetInfo::ConstraintInfo &info) const override { 7722 return true; 7723 } 7724 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7725 return None; 7726 } 7727 BuiltinVaListKind getBuiltinVaListKind() const override { 7728 return TargetInfo::VoidPtrBuiltinVaList; 7729 } 7730 7731 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7732 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK 7733 : CCCR_Warning; 7734 } 7735 7736 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7737 return CC_SpirFunction; 7738 } 7739 }; 7740 7741 class SPIR32TargetInfo : public SPIRTargetInfo { 7742 public: 7743 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7744 : SPIRTargetInfo(Triple, Opts) { 7745 PointerWidth = PointerAlign = 32; 7746 SizeType = TargetInfo::UnsignedInt; 7747 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7748 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7749 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7750 } 7751 void getTargetDefines(const LangOptions &Opts, 7752 MacroBuilder &Builder) const override { 7753 DefineStd(Builder, "SPIR32", Opts); 7754 } 7755 }; 7756 7757 class SPIR64TargetInfo : public SPIRTargetInfo { 7758 public: 7759 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7760 : SPIRTargetInfo(Triple, Opts) { 7761 PointerWidth = PointerAlign = 64; 7762 SizeType = TargetInfo::UnsignedLong; 7763 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7764 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7765 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7766 } 7767 void getTargetDefines(const LangOptions &Opts, 7768 MacroBuilder &Builder) const override { 7769 DefineStd(Builder, "SPIR64", Opts); 7770 } 7771 }; 7772 7773 class XCoreTargetInfo : public TargetInfo { 7774 static const Builtin::Info BuiltinInfo[]; 7775 public: 7776 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7777 : TargetInfo(Triple) { 7778 BigEndian = false; 7779 NoAsmVariants = true; 7780 LongLongAlign = 32; 7781 SuitableAlign = 32; 7782 DoubleAlign = LongDoubleAlign = 32; 7783 SizeType = UnsignedInt; 7784 PtrDiffType = SignedInt; 7785 IntPtrType = SignedInt; 7786 WCharType = UnsignedChar; 7787 WIntType = UnsignedInt; 7788 UseZeroLengthBitfieldAlignment = true; 7789 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7790 "-f64:32-a:0:32-n32"); 7791 } 7792 void getTargetDefines(const LangOptions &Opts, 7793 MacroBuilder &Builder) const override { 7794 Builder.defineMacro("__XS1B__"); 7795 } 7796 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7797 return llvm::makeArrayRef(BuiltinInfo, 7798 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 7799 } 7800 BuiltinVaListKind getBuiltinVaListKind() const override { 7801 return TargetInfo::VoidPtrBuiltinVaList; 7802 } 7803 const char *getClobbers() const override { 7804 return ""; 7805 } 7806 ArrayRef<const char *> getGCCRegNames() const override { 7807 static const char * const GCCRegNames[] = { 7808 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7809 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 7810 }; 7811 return llvm::makeArrayRef(GCCRegNames); 7812 } 7813 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7814 return None; 7815 } 7816 bool validateAsmConstraint(const char *&Name, 7817 TargetInfo::ConstraintInfo &Info) const override { 7818 return false; 7819 } 7820 int getEHDataRegisterNumber(unsigned RegNo) const override { 7821 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7822 return (RegNo < 2)? RegNo : -1; 7823 } 7824 bool allowsLargerPreferedTypeAlignment() const override { 7825 return false; 7826 } 7827 }; 7828 7829 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7830 #define BUILTIN(ID, TYPE, ATTRS) \ 7831 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7832 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7833 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7834 #include "clang/Basic/BuiltinsXCore.def" 7835 }; 7836 7837 // x86_32 Android target 7838 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7839 public: 7840 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7841 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 7842 SuitableAlign = 32; 7843 LongDoubleWidth = 64; 7844 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7845 } 7846 }; 7847 7848 // x86_64 Android target 7849 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7850 public: 7851 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7852 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 7853 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7854 } 7855 7856 bool useFloat128ManglingForLongDouble() const override { 7857 return true; 7858 } 7859 }; 7860 } // end anonymous namespace 7861 7862 //===----------------------------------------------------------------------===// 7863 // Driver code 7864 //===----------------------------------------------------------------------===// 7865 7866 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 7867 const TargetOptions &Opts) { 7868 llvm::Triple::OSType os = Triple.getOS(); 7869 7870 switch (Triple.getArch()) { 7871 default: 7872 return nullptr; 7873 7874 case llvm::Triple::xcore: 7875 return new XCoreTargetInfo(Triple, Opts); 7876 7877 case llvm::Triple::hexagon: 7878 return new HexagonTargetInfo(Triple, Opts); 7879 7880 case llvm::Triple::lanai: 7881 return new LanaiTargetInfo(Triple, Opts); 7882 7883 case llvm::Triple::aarch64: 7884 if (Triple.isOSDarwin()) 7885 return new DarwinAArch64TargetInfo(Triple, Opts); 7886 7887 switch (os) { 7888 case llvm::Triple::CloudABI: 7889 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 7890 case llvm::Triple::FreeBSD: 7891 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 7892 case llvm::Triple::Linux: 7893 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 7894 case llvm::Triple::NetBSD: 7895 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 7896 default: 7897 return new AArch64leTargetInfo(Triple, Opts); 7898 } 7899 7900 case llvm::Triple::aarch64_be: 7901 switch (os) { 7902 case llvm::Triple::FreeBSD: 7903 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 7904 case llvm::Triple::Linux: 7905 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 7906 case llvm::Triple::NetBSD: 7907 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 7908 default: 7909 return new AArch64beTargetInfo(Triple, Opts); 7910 } 7911 7912 case llvm::Triple::arm: 7913 case llvm::Triple::thumb: 7914 if (Triple.isOSBinFormatMachO()) 7915 return new DarwinARMTargetInfo(Triple, Opts); 7916 7917 switch (os) { 7918 case llvm::Triple::Linux: 7919 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 7920 case llvm::Triple::FreeBSD: 7921 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 7922 case llvm::Triple::NetBSD: 7923 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 7924 case llvm::Triple::OpenBSD: 7925 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 7926 case llvm::Triple::Bitrig: 7927 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 7928 case llvm::Triple::RTEMS: 7929 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 7930 case llvm::Triple::NaCl: 7931 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 7932 case llvm::Triple::Win32: 7933 switch (Triple.getEnvironment()) { 7934 case llvm::Triple::Cygnus: 7935 return new CygwinARMTargetInfo(Triple, Opts); 7936 case llvm::Triple::GNU: 7937 return new MinGWARMTargetInfo(Triple, Opts); 7938 case llvm::Triple::Itanium: 7939 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 7940 case llvm::Triple::MSVC: 7941 default: // Assume MSVC for unknown environments 7942 return new MicrosoftARMleTargetInfo(Triple, Opts); 7943 } 7944 default: 7945 return new ARMleTargetInfo(Triple, Opts); 7946 } 7947 7948 case llvm::Triple::armeb: 7949 case llvm::Triple::thumbeb: 7950 if (Triple.isOSDarwin()) 7951 return new DarwinARMTargetInfo(Triple, Opts); 7952 7953 switch (os) { 7954 case llvm::Triple::Linux: 7955 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 7956 case llvm::Triple::FreeBSD: 7957 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 7958 case llvm::Triple::NetBSD: 7959 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 7960 case llvm::Triple::OpenBSD: 7961 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 7962 case llvm::Triple::Bitrig: 7963 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 7964 case llvm::Triple::RTEMS: 7965 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 7966 case llvm::Triple::NaCl: 7967 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 7968 default: 7969 return new ARMbeTargetInfo(Triple, Opts); 7970 } 7971 7972 case llvm::Triple::bpfeb: 7973 case llvm::Triple::bpfel: 7974 return new BPFTargetInfo(Triple, Opts); 7975 7976 case llvm::Triple::msp430: 7977 return new MSP430TargetInfo(Triple, Opts); 7978 7979 case llvm::Triple::mips: 7980 switch (os) { 7981 case llvm::Triple::Linux: 7982 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple, Opts); 7983 case llvm::Triple::RTEMS: 7984 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple, Opts); 7985 case llvm::Triple::FreeBSD: 7986 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple, Opts); 7987 case llvm::Triple::NetBSD: 7988 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple, Opts); 7989 default: 7990 return new Mips32EBTargetInfo(Triple, Opts); 7991 } 7992 7993 case llvm::Triple::mipsel: 7994 switch (os) { 7995 case llvm::Triple::Linux: 7996 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple, Opts); 7997 case llvm::Triple::RTEMS: 7998 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple, Opts); 7999 case llvm::Triple::FreeBSD: 8000 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple, Opts); 8001 case llvm::Triple::NetBSD: 8002 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple, Opts); 8003 case llvm::Triple::NaCl: 8004 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple, Opts); 8005 default: 8006 return new Mips32ELTargetInfo(Triple, Opts); 8007 } 8008 8009 case llvm::Triple::mips64: 8010 switch (os) { 8011 case llvm::Triple::Linux: 8012 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 8013 case llvm::Triple::RTEMS: 8014 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 8015 case llvm::Triple::FreeBSD: 8016 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 8017 case llvm::Triple::NetBSD: 8018 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 8019 case llvm::Triple::OpenBSD: 8020 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 8021 default: 8022 return new Mips64EBTargetInfo(Triple, Opts); 8023 } 8024 8025 case llvm::Triple::mips64el: 8026 switch (os) { 8027 case llvm::Triple::Linux: 8028 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8029 case llvm::Triple::RTEMS: 8030 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8031 case llvm::Triple::FreeBSD: 8032 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8033 case llvm::Triple::NetBSD: 8034 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8035 case llvm::Triple::OpenBSD: 8036 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8037 default: 8038 return new Mips64ELTargetInfo(Triple, Opts); 8039 } 8040 8041 case llvm::Triple::le32: 8042 switch (os) { 8043 case llvm::Triple::NaCl: 8044 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 8045 default: 8046 return nullptr; 8047 } 8048 8049 case llvm::Triple::le64: 8050 return new Le64TargetInfo(Triple, Opts); 8051 8052 case llvm::Triple::ppc: 8053 if (Triple.isOSDarwin()) 8054 return new DarwinPPC32TargetInfo(Triple, Opts); 8055 switch (os) { 8056 case llvm::Triple::Linux: 8057 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 8058 case llvm::Triple::FreeBSD: 8059 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8060 case llvm::Triple::NetBSD: 8061 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8062 case llvm::Triple::OpenBSD: 8063 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8064 case llvm::Triple::RTEMS: 8065 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 8066 default: 8067 return new PPC32TargetInfo(Triple, Opts); 8068 } 8069 8070 case llvm::Triple::ppc64: 8071 if (Triple.isOSDarwin()) 8072 return new DarwinPPC64TargetInfo(Triple, Opts); 8073 switch (os) { 8074 case llvm::Triple::Linux: 8075 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8076 case llvm::Triple::Lv2: 8077 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 8078 case llvm::Triple::FreeBSD: 8079 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8080 case llvm::Triple::NetBSD: 8081 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8082 default: 8083 return new PPC64TargetInfo(Triple, Opts); 8084 } 8085 8086 case llvm::Triple::ppc64le: 8087 switch (os) { 8088 case llvm::Triple::Linux: 8089 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8090 case llvm::Triple::NetBSD: 8091 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8092 default: 8093 return new PPC64TargetInfo(Triple, Opts); 8094 } 8095 8096 case llvm::Triple::nvptx: 8097 return new NVPTX32TargetInfo(Triple, Opts); 8098 case llvm::Triple::nvptx64: 8099 return new NVPTX64TargetInfo(Triple, Opts); 8100 8101 case llvm::Triple::amdgcn: 8102 case llvm::Triple::r600: 8103 return new AMDGPUTargetInfo(Triple, Opts); 8104 8105 case llvm::Triple::sparc: 8106 switch (os) { 8107 case llvm::Triple::Linux: 8108 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8109 case llvm::Triple::Solaris: 8110 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8111 case llvm::Triple::NetBSD: 8112 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8113 case llvm::Triple::OpenBSD: 8114 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8115 case llvm::Triple::RTEMS: 8116 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8117 default: 8118 return new SparcV8TargetInfo(Triple, Opts); 8119 } 8120 8121 // The 'sparcel' architecture copies all the above cases except for Solaris. 8122 case llvm::Triple::sparcel: 8123 switch (os) { 8124 case llvm::Triple::Linux: 8125 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8126 case llvm::Triple::NetBSD: 8127 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8128 case llvm::Triple::OpenBSD: 8129 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8130 case llvm::Triple::RTEMS: 8131 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8132 default: 8133 return new SparcV8elTargetInfo(Triple, Opts); 8134 } 8135 8136 case llvm::Triple::sparcv9: 8137 switch (os) { 8138 case llvm::Triple::Linux: 8139 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8140 case llvm::Triple::Solaris: 8141 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8142 case llvm::Triple::NetBSD: 8143 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8144 case llvm::Triple::OpenBSD: 8145 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8146 case llvm::Triple::FreeBSD: 8147 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8148 default: 8149 return new SparcV9TargetInfo(Triple, Opts); 8150 } 8151 8152 case llvm::Triple::systemz: 8153 switch (os) { 8154 case llvm::Triple::Linux: 8155 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 8156 default: 8157 return new SystemZTargetInfo(Triple, Opts); 8158 } 8159 8160 case llvm::Triple::tce: 8161 return new TCETargetInfo(Triple, Opts); 8162 8163 case llvm::Triple::x86: 8164 if (Triple.isOSDarwin()) 8165 return new DarwinI386TargetInfo(Triple, Opts); 8166 8167 switch (os) { 8168 case llvm::Triple::CloudABI: 8169 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 8170 case llvm::Triple::Linux: { 8171 switch (Triple.getEnvironment()) { 8172 default: 8173 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 8174 case llvm::Triple::Android: 8175 return new AndroidX86_32TargetInfo(Triple, Opts); 8176 } 8177 } 8178 case llvm::Triple::DragonFly: 8179 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8180 case llvm::Triple::NetBSD: 8181 return new NetBSDI386TargetInfo(Triple, Opts); 8182 case llvm::Triple::OpenBSD: 8183 return new OpenBSDI386TargetInfo(Triple, Opts); 8184 case llvm::Triple::Bitrig: 8185 return new BitrigI386TargetInfo(Triple, Opts); 8186 case llvm::Triple::FreeBSD: 8187 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8188 case llvm::Triple::KFreeBSD: 8189 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8190 case llvm::Triple::Minix: 8191 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 8192 case llvm::Triple::Solaris: 8193 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 8194 case llvm::Triple::Win32: { 8195 switch (Triple.getEnvironment()) { 8196 case llvm::Triple::Cygnus: 8197 return new CygwinX86_32TargetInfo(Triple, Opts); 8198 case llvm::Triple::GNU: 8199 return new MinGWX86_32TargetInfo(Triple, Opts); 8200 case llvm::Triple::Itanium: 8201 case llvm::Triple::MSVC: 8202 default: // Assume MSVC for unknown environments 8203 return new MicrosoftX86_32TargetInfo(Triple, Opts); 8204 } 8205 } 8206 case llvm::Triple::Haiku: 8207 return new HaikuX86_32TargetInfo(Triple, Opts); 8208 case llvm::Triple::RTEMS: 8209 return new RTEMSX86_32TargetInfo(Triple, Opts); 8210 case llvm::Triple::NaCl: 8211 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 8212 case llvm::Triple::ELFIAMCU: 8213 return new MCUX86_32TargetInfo(Triple, Opts); 8214 default: 8215 return new X86_32TargetInfo(Triple, Opts); 8216 } 8217 8218 case llvm::Triple::x86_64: 8219 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 8220 return new DarwinX86_64TargetInfo(Triple, Opts); 8221 8222 switch (os) { 8223 case llvm::Triple::CloudABI: 8224 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 8225 case llvm::Triple::Linux: { 8226 switch (Triple.getEnvironment()) { 8227 default: 8228 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 8229 case llvm::Triple::Android: 8230 return new AndroidX86_64TargetInfo(Triple, Opts); 8231 } 8232 } 8233 case llvm::Triple::DragonFly: 8234 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8235 case llvm::Triple::NetBSD: 8236 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8237 case llvm::Triple::OpenBSD: 8238 return new OpenBSDX86_64TargetInfo(Triple, Opts); 8239 case llvm::Triple::Bitrig: 8240 return new BitrigX86_64TargetInfo(Triple, Opts); 8241 case llvm::Triple::FreeBSD: 8242 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8243 case llvm::Triple::KFreeBSD: 8244 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8245 case llvm::Triple::Solaris: 8246 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 8247 case llvm::Triple::Win32: { 8248 switch (Triple.getEnvironment()) { 8249 case llvm::Triple::Cygnus: 8250 return new CygwinX86_64TargetInfo(Triple, Opts); 8251 case llvm::Triple::GNU: 8252 return new MinGWX86_64TargetInfo(Triple, Opts); 8253 case llvm::Triple::MSVC: 8254 default: // Assume MSVC for unknown environments 8255 return new MicrosoftX86_64TargetInfo(Triple, Opts); 8256 } 8257 } 8258 case llvm::Triple::NaCl: 8259 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 8260 case llvm::Triple::PS4: 8261 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 8262 default: 8263 return new X86_64TargetInfo(Triple, Opts); 8264 } 8265 8266 case llvm::Triple::spir: { 8267 if (Triple.getOS() != llvm::Triple::UnknownOS || 8268 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8269 return nullptr; 8270 return new SPIR32TargetInfo(Triple, Opts); 8271 } 8272 case llvm::Triple::spir64: { 8273 if (Triple.getOS() != llvm::Triple::UnknownOS || 8274 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8275 return nullptr; 8276 return new SPIR64TargetInfo(Triple, Opts); 8277 } 8278 case llvm::Triple::wasm32: 8279 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8280 return nullptr; 8281 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 8282 case llvm::Triple::wasm64: 8283 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8284 return nullptr; 8285 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 8286 } 8287 } 8288 8289 /// CreateTargetInfo - Return the target info object for the specified target 8290 /// options. 8291 TargetInfo * 8292 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8293 const std::shared_ptr<TargetOptions> &Opts) { 8294 llvm::Triple Triple(Opts->Triple); 8295 8296 // Construct the target 8297 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 8298 if (!Target) { 8299 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8300 return nullptr; 8301 } 8302 Target->TargetOpts = Opts; 8303 8304 // Set the target CPU if specified. 8305 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8306 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8307 return nullptr; 8308 } 8309 8310 // Set the target ABI if specified. 8311 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8312 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8313 return nullptr; 8314 } 8315 8316 // Set the fp math unit. 8317 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8318 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8319 return nullptr; 8320 } 8321 8322 // Compute the default target features, we need the target to handle this 8323 // because features may have dependencies on one another. 8324 llvm::StringMap<bool> Features; 8325 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8326 Opts->FeaturesAsWritten)) 8327 return nullptr; 8328 8329 // Add the features to the compile options. 8330 Opts->Features.clear(); 8331 for (const auto &F : Features) 8332 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8333 8334 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8335 return nullptr; 8336 8337 return Target.release(); 8338 } 8339