1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringRef.h" 25 #include "llvm/ADT/StringSwitch.h" 26 #include "llvm/ADT/Triple.h" 27 #include "llvm/IR/Type.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include <algorithm> 31 #include <memory> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 77 void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const override { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "6000"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 94 // AddressSanitizer doesn't play well with source fortification, which is on 95 // by default on Darwin. 96 if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0"); 97 98 if (!Opts.ObjCAutoRefCount) { 99 // __weak is always defined, for use in blocks and with objc pointers. 100 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 101 102 // Darwin defines __strong even in C mode (just to nothing). 103 if (Opts.getGC() != LangOptions::NonGC) 104 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 105 else 106 Builder.defineMacro("__strong", ""); 107 108 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 109 // allow this in C, since one might have block pointers in structs that 110 // are used in pure C code and in Objective-C ARC. 111 Builder.defineMacro("__unsafe_unretained", ""); 112 } 113 114 if (Opts.Static) 115 Builder.defineMacro("__STATIC__"); 116 else 117 Builder.defineMacro("__DYNAMIC__"); 118 119 if (Opts.POSIXThreads) 120 Builder.defineMacro("_REENTRANT"); 121 122 // Get the platform type and version number from the triple. 123 unsigned Maj, Min, Rev; 124 if (Triple.isMacOSX()) { 125 Triple.getMacOSXVersion(Maj, Min, Rev); 126 PlatformName = "macosx"; 127 } else { 128 Triple.getOSVersion(Maj, Min, Rev); 129 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 130 } 131 132 // If -target arch-pc-win32-macho option specified, we're 133 // generating code for Win32 ABI. No need to emit 134 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 135 if (PlatformName == "win32") { 136 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 137 return; 138 } 139 140 // Set the appropriate OS version define. 141 if (Triple.isiOS()) { 142 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 143 char Str[6]; 144 Str[0] = '0' + Maj; 145 Str[1] = '0' + (Min / 10); 146 Str[2] = '0' + (Min % 10); 147 Str[3] = '0' + (Rev / 10); 148 Str[4] = '0' + (Rev % 10); 149 Str[5] = '\0'; 150 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 151 Str); 152 } else if (Triple.isMacOSX()) { 153 // Note that the Driver allows versions which aren't representable in the 154 // define (because we only get a single digit for the minor and micro 155 // revision numbers). So, we limit them to the maximum representable 156 // version. 157 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 158 char Str[5]; 159 Str[0] = '0' + (Maj / 10); 160 Str[1] = '0' + (Maj % 10); 161 Str[2] = '0' + std::min(Min, 9U); 162 Str[3] = '0' + std::min(Rev, 9U); 163 Str[4] = '\0'; 164 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 165 } 166 167 // Tell users about the kernel if there is one. 168 if (Triple.isOSDarwin()) 169 Builder.defineMacro("__MACH__"); 170 171 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 172 } 173 174 namespace { 175 template<typename Target> 176 class DarwinTargetInfo : public OSTargetInfo<Target> { 177 protected: 178 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 179 MacroBuilder &Builder) const override { 180 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 181 this->PlatformMinVersion); 182 } 183 184 public: 185 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 186 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 187 this->MCountName = "\01mcount"; 188 } 189 190 std::string isValidSectionSpecifier(StringRef SR) const override { 191 // Let MCSectionMachO validate this. 192 StringRef Segment, Section; 193 unsigned TAA, StubSize; 194 bool HasTAA; 195 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 196 TAA, HasTAA, StubSize); 197 } 198 199 const char *getStaticInitSectionSpecifier() const override { 200 // FIXME: We should return 0 when building kexts. 201 return "__TEXT,__StaticInit,regular,pure_instructions"; 202 } 203 204 /// Darwin does not support protected visibility. Darwin's "default" 205 /// is very similar to ELF's "protected"; Darwin requires a "weak" 206 /// attribute on declarations that can be dynamically replaced. 207 bool hasProtectedVisibility() const override { 208 return false; 209 } 210 }; 211 212 213 // DragonFlyBSD Target 214 template<typename Target> 215 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 216 protected: 217 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 218 MacroBuilder &Builder) const override { 219 // DragonFly defines; list based off of gcc output 220 Builder.defineMacro("__DragonFly__"); 221 Builder.defineMacro("__DragonFly_cc_version", "100001"); 222 Builder.defineMacro("__ELF__"); 223 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 224 Builder.defineMacro("__tune_i386__"); 225 DefineStd(Builder, "unix", Opts); 226 } 227 public: 228 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 229 : OSTargetInfo<Target>(Triple) { 230 this->UserLabelPrefix = ""; 231 232 switch (Triple.getArch()) { 233 default: 234 case llvm::Triple::x86: 235 case llvm::Triple::x86_64: 236 this->MCountName = ".mcount"; 237 break; 238 } 239 } 240 }; 241 242 // FreeBSD Target 243 template<typename Target> 244 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 245 protected: 246 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 247 MacroBuilder &Builder) const override { 248 // FreeBSD defines; list based off of gcc output 249 250 unsigned Release = Triple.getOSMajorVersion(); 251 if (Release == 0U) 252 Release = 8; 253 254 Builder.defineMacro("__FreeBSD__", Twine(Release)); 255 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 256 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 257 DefineStd(Builder, "unix", Opts); 258 Builder.defineMacro("__ELF__"); 259 260 // On FreeBSD, wchar_t contains the number of the code point as 261 // used by the character set of the locale. These character sets are 262 // not necessarily a superset of ASCII. 263 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 264 } 265 public: 266 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 267 this->UserLabelPrefix = ""; 268 269 switch (Triple.getArch()) { 270 default: 271 case llvm::Triple::x86: 272 case llvm::Triple::x86_64: 273 this->MCountName = ".mcount"; 274 break; 275 case llvm::Triple::mips: 276 case llvm::Triple::mipsel: 277 case llvm::Triple::ppc: 278 case llvm::Triple::ppc64: 279 case llvm::Triple::ppc64le: 280 this->MCountName = "_mcount"; 281 break; 282 case llvm::Triple::arm: 283 this->MCountName = "__mcount"; 284 break; 285 } 286 } 287 }; 288 289 // GNU/kFreeBSD Target 290 template<typename Target> 291 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 292 protected: 293 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 294 MacroBuilder &Builder) const override { 295 // GNU/kFreeBSD defines; list based off of gcc output 296 297 DefineStd(Builder, "unix", Opts); 298 Builder.defineMacro("__FreeBSD_kernel__"); 299 Builder.defineMacro("__GLIBC__"); 300 Builder.defineMacro("__ELF__"); 301 if (Opts.POSIXThreads) 302 Builder.defineMacro("_REENTRANT"); 303 if (Opts.CPlusPlus) 304 Builder.defineMacro("_GNU_SOURCE"); 305 } 306 public: 307 KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 308 this->UserLabelPrefix = ""; 309 } 310 }; 311 312 // Minix Target 313 template<typename Target> 314 class MinixTargetInfo : public OSTargetInfo<Target> { 315 protected: 316 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 317 MacroBuilder &Builder) const override { 318 // Minix defines 319 320 Builder.defineMacro("__minix", "3"); 321 Builder.defineMacro("_EM_WSIZE", "4"); 322 Builder.defineMacro("_EM_PSIZE", "4"); 323 Builder.defineMacro("_EM_SSIZE", "2"); 324 Builder.defineMacro("_EM_LSIZE", "4"); 325 Builder.defineMacro("_EM_FSIZE", "4"); 326 Builder.defineMacro("_EM_DSIZE", "8"); 327 Builder.defineMacro("__ELF__"); 328 DefineStd(Builder, "unix", Opts); 329 } 330 public: 331 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 332 this->UserLabelPrefix = ""; 333 } 334 }; 335 336 // Linux target 337 template<typename Target> 338 class LinuxTargetInfo : public OSTargetInfo<Target> { 339 protected: 340 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 341 MacroBuilder &Builder) const override { 342 // Linux defines; list based off of gcc output 343 DefineStd(Builder, "unix", Opts); 344 DefineStd(Builder, "linux", Opts); 345 Builder.defineMacro("__gnu_linux__"); 346 Builder.defineMacro("__ELF__"); 347 if (Triple.getEnvironment() == llvm::Triple::Android) 348 Builder.defineMacro("__ANDROID__", "1"); 349 if (Opts.POSIXThreads) 350 Builder.defineMacro("_REENTRANT"); 351 if (Opts.CPlusPlus) 352 Builder.defineMacro("_GNU_SOURCE"); 353 } 354 public: 355 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 356 this->UserLabelPrefix = ""; 357 this->WIntType = TargetInfo::UnsignedInt; 358 359 switch (Triple.getArch()) { 360 default: 361 break; 362 case llvm::Triple::ppc: 363 case llvm::Triple::ppc64: 364 case llvm::Triple::ppc64le: 365 this->MCountName = "_mcount"; 366 break; 367 } 368 } 369 370 const char *getStaticInitSectionSpecifier() const override { 371 return ".text.startup"; 372 } 373 }; 374 375 // NetBSD Target 376 template<typename Target> 377 class NetBSDTargetInfo : public OSTargetInfo<Target> { 378 protected: 379 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 380 MacroBuilder &Builder) const override { 381 // NetBSD defines; list based off of gcc output 382 Builder.defineMacro("__NetBSD__"); 383 Builder.defineMacro("__unix__"); 384 Builder.defineMacro("__ELF__"); 385 if (Opts.POSIXThreads) 386 Builder.defineMacro("_POSIX_THREADS"); 387 388 switch (Triple.getArch()) { 389 default: 390 break; 391 case llvm::Triple::arm: 392 case llvm::Triple::armeb: 393 case llvm::Triple::thumb: 394 case llvm::Triple::thumbeb: 395 Builder.defineMacro("__ARM_DWARF_EH__"); 396 break; 397 } 398 } 399 public: 400 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 401 this->UserLabelPrefix = ""; 402 } 403 }; 404 405 // OpenBSD Target 406 template<typename Target> 407 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 408 protected: 409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 410 MacroBuilder &Builder) const override { 411 // OpenBSD defines; list based off of gcc output 412 413 Builder.defineMacro("__OpenBSD__"); 414 DefineStd(Builder, "unix", Opts); 415 Builder.defineMacro("__ELF__"); 416 if (Opts.POSIXThreads) 417 Builder.defineMacro("_REENTRANT"); 418 } 419 public: 420 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 421 this->UserLabelPrefix = ""; 422 this->TLSSupported = false; 423 424 switch (Triple.getArch()) { 425 default: 426 case llvm::Triple::x86: 427 case llvm::Triple::x86_64: 428 case llvm::Triple::arm: 429 case llvm::Triple::sparc: 430 this->MCountName = "__mcount"; 431 break; 432 case llvm::Triple::mips64: 433 case llvm::Triple::mips64el: 434 case llvm::Triple::ppc: 435 case llvm::Triple::sparcv9: 436 this->MCountName = "_mcount"; 437 break; 438 } 439 } 440 }; 441 442 // Bitrig Target 443 template<typename Target> 444 class BitrigTargetInfo : public OSTargetInfo<Target> { 445 protected: 446 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 447 MacroBuilder &Builder) const override { 448 // Bitrig defines; list based off of gcc output 449 450 Builder.defineMacro("__Bitrig__"); 451 DefineStd(Builder, "unix", Opts); 452 Builder.defineMacro("__ELF__"); 453 if (Opts.POSIXThreads) 454 Builder.defineMacro("_REENTRANT"); 455 } 456 public: 457 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 458 this->UserLabelPrefix = ""; 459 this->MCountName = "__mcount"; 460 } 461 }; 462 463 // PSP Target 464 template<typename Target> 465 class PSPTargetInfo : public OSTargetInfo<Target> { 466 protected: 467 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 468 MacroBuilder &Builder) const override { 469 // PSP defines; list based on the output of the pspdev gcc toolchain. 470 Builder.defineMacro("PSP"); 471 Builder.defineMacro("_PSP"); 472 Builder.defineMacro("__psp__"); 473 Builder.defineMacro("__ELF__"); 474 } 475 public: 476 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 477 this->UserLabelPrefix = ""; 478 } 479 }; 480 481 // PS3 PPU Target 482 template<typename Target> 483 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 484 protected: 485 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 486 MacroBuilder &Builder) const override { 487 // PS3 PPU defines. 488 Builder.defineMacro("__PPC__"); 489 Builder.defineMacro("__PPU__"); 490 Builder.defineMacro("__CELLOS_LV2__"); 491 Builder.defineMacro("__ELF__"); 492 Builder.defineMacro("__LP32__"); 493 Builder.defineMacro("_ARCH_PPC64"); 494 Builder.defineMacro("__powerpc64__"); 495 } 496 public: 497 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 498 this->UserLabelPrefix = ""; 499 this->LongWidth = this->LongAlign = 32; 500 this->PointerWidth = this->PointerAlign = 32; 501 this->IntMaxType = TargetInfo::SignedLongLong; 502 this->UIntMaxType = TargetInfo::UnsignedLongLong; 503 this->Int64Type = TargetInfo::SignedLongLong; 504 this->SizeType = TargetInfo::UnsignedInt; 505 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64"; 506 } 507 }; 508 509 // AuroraUX target 510 template<typename Target> 511 class AuroraUXTargetInfo : public OSTargetInfo<Target> { 512 protected: 513 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 514 MacroBuilder &Builder) const override { 515 DefineStd(Builder, "sun", Opts); 516 DefineStd(Builder, "unix", Opts); 517 Builder.defineMacro("__ELF__"); 518 Builder.defineMacro("__svr4__"); 519 Builder.defineMacro("__SVR4"); 520 } 521 public: 522 AuroraUXTargetInfo(const llvm::Triple &Triple) 523 : OSTargetInfo<Target>(Triple) { 524 this->UserLabelPrefix = ""; 525 this->WCharType = this->SignedLong; 526 // FIXME: WIntType should be SignedLong 527 } 528 }; 529 530 // Solaris target 531 template<typename Target> 532 class SolarisTargetInfo : public OSTargetInfo<Target> { 533 protected: 534 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 535 MacroBuilder &Builder) const override { 536 DefineStd(Builder, "sun", Opts); 537 DefineStd(Builder, "unix", Opts); 538 Builder.defineMacro("__ELF__"); 539 Builder.defineMacro("__svr4__"); 540 Builder.defineMacro("__SVR4"); 541 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 542 // newer, but to 500 for everything else. feature_test.h has a check to 543 // ensure that you are not using C99 with an old version of X/Open or C89 544 // with a new version. 545 if (Opts.C99 || Opts.C11) 546 Builder.defineMacro("_XOPEN_SOURCE", "600"); 547 else 548 Builder.defineMacro("_XOPEN_SOURCE", "500"); 549 if (Opts.CPlusPlus) 550 Builder.defineMacro("__C99FEATURES__"); 551 Builder.defineMacro("_LARGEFILE_SOURCE"); 552 Builder.defineMacro("_LARGEFILE64_SOURCE"); 553 Builder.defineMacro("__EXTENSIONS__"); 554 Builder.defineMacro("_REENTRANT"); 555 } 556 public: 557 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 558 this->UserLabelPrefix = ""; 559 this->WCharType = this->SignedInt; 560 // FIXME: WIntType should be SignedLong 561 } 562 }; 563 564 // Windows target 565 template<typename Target> 566 class WindowsTargetInfo : public OSTargetInfo<Target> { 567 protected: 568 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 569 MacroBuilder &Builder) const override { 570 Builder.defineMacro("_WIN32"); 571 } 572 void getVisualStudioDefines(const LangOptions &Opts, 573 MacroBuilder &Builder) const { 574 if (Opts.CPlusPlus) { 575 if (Opts.RTTI) 576 Builder.defineMacro("_CPPRTTI"); 577 578 if (Opts.Exceptions) 579 Builder.defineMacro("_CPPUNWIND"); 580 } 581 582 if (!Opts.CharIsSigned) 583 Builder.defineMacro("_CHAR_UNSIGNED"); 584 585 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 586 // but it works for now. 587 if (Opts.POSIXThreads) 588 Builder.defineMacro("_MT"); 589 590 if (Opts.MSCVersion != 0) { 591 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion / 100000)); 592 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCVersion)); 593 // FIXME We cannot encode the revision information into 32-bits 594 Builder.defineMacro("_MSC_BUILD", Twine(1)); 595 } 596 597 if (Opts.MicrosoftExt) { 598 Builder.defineMacro("_MSC_EXTENSIONS"); 599 600 if (Opts.CPlusPlus11) { 601 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 602 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 603 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 604 } 605 } 606 607 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 608 } 609 610 public: 611 WindowsTargetInfo(const llvm::Triple &Triple) 612 : OSTargetInfo<Target>(Triple) {} 613 }; 614 615 template <typename Target> 616 class NaClTargetInfo : public OSTargetInfo<Target> { 617 protected: 618 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 619 MacroBuilder &Builder) const override { 620 if (Opts.POSIXThreads) 621 Builder.defineMacro("_REENTRANT"); 622 if (Opts.CPlusPlus) 623 Builder.defineMacro("_GNU_SOURCE"); 624 625 DefineStd(Builder, "unix", Opts); 626 Builder.defineMacro("__ELF__"); 627 Builder.defineMacro("__native_client__"); 628 } 629 630 public: 631 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 632 this->UserLabelPrefix = ""; 633 this->LongAlign = 32; 634 this->LongWidth = 32; 635 this->PointerAlign = 32; 636 this->PointerWidth = 32; 637 this->IntMaxType = TargetInfo::SignedLongLong; 638 this->UIntMaxType = TargetInfo::UnsignedLongLong; 639 this->Int64Type = TargetInfo::SignedLongLong; 640 this->DoubleAlign = 64; 641 this->LongDoubleWidth = 64; 642 this->LongDoubleAlign = 64; 643 this->LongLongWidth = 64; 644 this->LongLongAlign = 64; 645 this->SizeType = TargetInfo::UnsignedInt; 646 this->PtrDiffType = TargetInfo::SignedInt; 647 this->IntPtrType = TargetInfo::SignedInt; 648 // RegParmMax is inherited from the underlying architecture 649 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 650 if (Triple.getArch() == llvm::Triple::arm) { 651 this->DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S128"; 652 } else if (Triple.getArch() == llvm::Triple::x86) { 653 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 654 } else if (Triple.getArch() == llvm::Triple::x86_64) { 655 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 656 } else if (Triple.getArch() == llvm::Triple::mipsel) { 657 // Handled on mips' setDescriptionString. 658 } else { 659 assert(Triple.getArch() == llvm::Triple::le32); 660 this->DescriptionString = "e-p:32:32-i64:64"; 661 } 662 } 663 typename Target::CallingConvCheckResult checkCallingConvention( 664 CallingConv CC) const override { 665 return CC == CC_PnaclCall ? Target::CCCR_OK : 666 Target::checkCallingConvention(CC); 667 } 668 }; 669 } // end anonymous namespace. 670 671 //===----------------------------------------------------------------------===// 672 // Specific target implementations. 673 //===----------------------------------------------------------------------===// 674 675 namespace { 676 // PPC abstract base class 677 class PPCTargetInfo : public TargetInfo { 678 static const Builtin::Info BuiltinInfo[]; 679 static const char * const GCCRegNames[]; 680 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 681 std::string CPU; 682 683 // Target cpu features. 684 bool HasVSX; 685 686 public: 687 PPCTargetInfo(const llvm::Triple &Triple) 688 : TargetInfo(Triple), HasVSX(false) { 689 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 690 LongDoubleWidth = LongDoubleAlign = 128; 691 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 692 } 693 694 /// \brief Flags for architecture specific defines. 695 typedef enum { 696 ArchDefineNone = 0, 697 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 698 ArchDefinePpcgr = 1 << 1, 699 ArchDefinePpcsq = 1 << 2, 700 ArchDefine440 = 1 << 3, 701 ArchDefine603 = 1 << 4, 702 ArchDefine604 = 1 << 5, 703 ArchDefinePwr4 = 1 << 6, 704 ArchDefinePwr5 = 1 << 7, 705 ArchDefinePwr5x = 1 << 8, 706 ArchDefinePwr6 = 1 << 9, 707 ArchDefinePwr6x = 1 << 10, 708 ArchDefinePwr7 = 1 << 11, 709 ArchDefineA2 = 1 << 12, 710 ArchDefineA2q = 1 << 13 711 } ArchDefineTypes; 712 713 // Note: GCC recognizes the following additional cpus: 714 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 715 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 716 // titan, rs64. 717 bool setCPU(const std::string &Name) override { 718 bool CPUKnown = llvm::StringSwitch<bool>(Name) 719 .Case("generic", true) 720 .Case("440", true) 721 .Case("450", true) 722 .Case("601", true) 723 .Case("602", true) 724 .Case("603", true) 725 .Case("603e", true) 726 .Case("603ev", true) 727 .Case("604", true) 728 .Case("604e", true) 729 .Case("620", true) 730 .Case("630", true) 731 .Case("g3", true) 732 .Case("7400", true) 733 .Case("g4", true) 734 .Case("7450", true) 735 .Case("g4+", true) 736 .Case("750", true) 737 .Case("970", true) 738 .Case("g5", true) 739 .Case("a2", true) 740 .Case("a2q", true) 741 .Case("e500mc", true) 742 .Case("e5500", true) 743 .Case("power3", true) 744 .Case("pwr3", true) 745 .Case("power4", true) 746 .Case("pwr4", true) 747 .Case("power5", true) 748 .Case("pwr5", true) 749 .Case("power5x", true) 750 .Case("pwr5x", true) 751 .Case("power6", true) 752 .Case("pwr6", true) 753 .Case("power6x", true) 754 .Case("pwr6x", true) 755 .Case("power7", true) 756 .Case("pwr7", true) 757 .Case("powerpc", true) 758 .Case("ppc", true) 759 .Case("powerpc64", true) 760 .Case("ppc64", true) 761 .Case("powerpc64le", true) 762 .Case("ppc64le", true) 763 .Default(false); 764 765 if (CPUKnown) 766 CPU = Name; 767 768 return CPUKnown; 769 } 770 771 void getTargetBuiltins(const Builtin::Info *&Records, 772 unsigned &NumRecords) const override { 773 Records = BuiltinInfo; 774 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 775 } 776 777 bool isCLZForZeroUndef() const override { return false; } 778 779 void getTargetDefines(const LangOptions &Opts, 780 MacroBuilder &Builder) const override; 781 782 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 783 784 bool handleTargetFeatures(std::vector<std::string> &Features, 785 DiagnosticsEngine &Diags) override; 786 bool hasFeature(StringRef Feature) const override; 787 788 void getGCCRegNames(const char * const *&Names, 789 unsigned &NumNames) const override; 790 void getGCCRegAliases(const GCCRegAlias *&Aliases, 791 unsigned &NumAliases) const override; 792 bool validateAsmConstraint(const char *&Name, 793 TargetInfo::ConstraintInfo &Info) const override { 794 switch (*Name) { 795 default: return false; 796 case 'O': // Zero 797 break; 798 case 'b': // Base register 799 case 'f': // Floating point register 800 Info.setAllowsRegister(); 801 break; 802 // FIXME: The following are added to allow parsing. 803 // I just took a guess at what the actions should be. 804 // Also, is more specific checking needed? I.e. specific registers? 805 case 'd': // Floating point register (containing 64-bit value) 806 case 'v': // Altivec vector register 807 Info.setAllowsRegister(); 808 break; 809 case 'w': 810 switch (Name[1]) { 811 case 'd':// VSX vector register to hold vector double data 812 case 'f':// VSX vector register to hold vector float data 813 case 's':// VSX vector register to hold scalar float data 814 case 'a':// Any VSX register 815 case 'c':// An individual CR bit 816 break; 817 default: 818 return false; 819 } 820 Info.setAllowsRegister(); 821 Name++; // Skip over 'w'. 822 break; 823 case 'h': // `MQ', `CTR', or `LINK' register 824 case 'q': // `MQ' register 825 case 'c': // `CTR' register 826 case 'l': // `LINK' register 827 case 'x': // `CR' register (condition register) number 0 828 case 'y': // `CR' register (condition register) 829 case 'z': // `XER[CA]' carry bit (part of the XER register) 830 Info.setAllowsRegister(); 831 break; 832 case 'I': // Signed 16-bit constant 833 case 'J': // Unsigned 16-bit constant shifted left 16 bits 834 // (use `L' instead for SImode constants) 835 case 'K': // Unsigned 16-bit constant 836 case 'L': // Signed 16-bit constant shifted left 16 bits 837 case 'M': // Constant larger than 31 838 case 'N': // Exact power of 2 839 case 'P': // Constant whose negation is a signed 16-bit constant 840 case 'G': // Floating point constant that can be loaded into a 841 // register with one instruction per word 842 case 'H': // Integer/Floating point constant that can be loaded 843 // into a register using three instructions 844 break; 845 case 'm': // Memory operand. Note that on PowerPC targets, m can 846 // include addresses that update the base register. It 847 // is therefore only safe to use `m' in an asm statement 848 // if that asm statement accesses the operand exactly once. 849 // The asm statement must also use `%U<opno>' as a 850 // placeholder for the "update" flag in the corresponding 851 // load or store instruction. For example: 852 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 853 // is correct but: 854 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 855 // is not. Use es rather than m if you don't want the base 856 // register to be updated. 857 case 'e': 858 if (Name[1] != 's') 859 return false; 860 // es: A "stable" memory operand; that is, one which does not 861 // include any automodification of the base register. Unlike 862 // `m', this constraint can be used in asm statements that 863 // might access the operand several times, or that might not 864 // access it at all. 865 Info.setAllowsMemory(); 866 Name++; // Skip over 'e'. 867 break; 868 case 'Q': // Memory operand that is an offset from a register (it is 869 // usually better to use `m' or `es' in asm statements) 870 case 'Z': // Memory operand that is an indexed or indirect from a 871 // register (it is usually better to use `m' or `es' in 872 // asm statements) 873 Info.setAllowsMemory(); 874 Info.setAllowsRegister(); 875 break; 876 case 'R': // AIX TOC entry 877 case 'a': // Address operand that is an indexed or indirect from a 878 // register (`p' is preferable for asm statements) 879 case 'S': // Constant suitable as a 64-bit mask operand 880 case 'T': // Constant suitable as a 32-bit mask operand 881 case 'U': // System V Release 4 small data area reference 882 case 't': // AND masks that can be performed by two rldic{l, r} 883 // instructions 884 case 'W': // Vector constant that does not require memory 885 case 'j': // Vector constant that is all zeros. 886 break; 887 // End FIXME. 888 } 889 return true; 890 } 891 std::string convertConstraint(const char *&Constraint) const override { 892 std::string R; 893 switch (*Constraint) { 894 case 'e': 895 case 'w': 896 // Two-character constraint; add "^" hint for later parsing. 897 R = std::string("^") + std::string(Constraint, 2); 898 Constraint++; 899 break; 900 default: 901 return TargetInfo::convertConstraint(Constraint); 902 } 903 return R; 904 } 905 const char *getClobbers() const override { 906 return ""; 907 } 908 int getEHDataRegisterNumber(unsigned RegNo) const override { 909 if (RegNo == 0) return 3; 910 if (RegNo == 1) return 4; 911 return -1; 912 } 913 }; 914 915 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 916 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 917 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 918 ALL_LANGUAGES }, 919 #include "clang/Basic/BuiltinsPPC.def" 920 }; 921 922 /// handleTargetFeatures - Perform initialization based on the user 923 /// configured set of features. 924 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 925 DiagnosticsEngine &Diags) { 926 // Remember the maximum enabled sselevel. 927 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 928 // Ignore disabled features. 929 if (Features[i][0] == '-') 930 continue; 931 932 StringRef Feature = StringRef(Features[i]).substr(1); 933 934 if (Feature == "vsx") { 935 HasVSX = true; 936 continue; 937 } 938 939 // TODO: Finish this list and add an assert that we've handled them 940 // all. 941 } 942 943 return true; 944 } 945 946 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 947 /// #defines that are not tied to a specific subtarget. 948 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 949 MacroBuilder &Builder) const { 950 // Target identification. 951 Builder.defineMacro("__ppc__"); 952 Builder.defineMacro("__PPC__"); 953 Builder.defineMacro("_ARCH_PPC"); 954 Builder.defineMacro("__powerpc__"); 955 Builder.defineMacro("__POWERPC__"); 956 if (PointerWidth == 64) { 957 Builder.defineMacro("_ARCH_PPC64"); 958 Builder.defineMacro("__powerpc64__"); 959 Builder.defineMacro("__ppc64__"); 960 Builder.defineMacro("__PPC64__"); 961 } 962 963 // Target properties. 964 if (getTriple().getArch() == llvm::Triple::ppc64le) { 965 Builder.defineMacro("_LITTLE_ENDIAN"); 966 Builder.defineMacro("_CALL_ELF","2"); 967 } else { 968 if (getTriple().getOS() != llvm::Triple::NetBSD && 969 getTriple().getOS() != llvm::Triple::OpenBSD) 970 Builder.defineMacro("_BIG_ENDIAN"); 971 } 972 973 // Subtarget options. 974 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 975 Builder.defineMacro("__REGISTER_PREFIX__", ""); 976 977 // FIXME: Should be controlled by command line option. 978 if (LongDoubleWidth == 128) 979 Builder.defineMacro("__LONG_DOUBLE_128__"); 980 981 if (Opts.AltiVec) { 982 Builder.defineMacro("__VEC__", "10206"); 983 Builder.defineMacro("__ALTIVEC__"); 984 } 985 986 // CPU identification. 987 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 988 .Case("440", ArchDefineName) 989 .Case("450", ArchDefineName | ArchDefine440) 990 .Case("601", ArchDefineName) 991 .Case("602", ArchDefineName | ArchDefinePpcgr) 992 .Case("603", ArchDefineName | ArchDefinePpcgr) 993 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 994 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 995 .Case("604", ArchDefineName | ArchDefinePpcgr) 996 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 997 .Case("620", ArchDefineName | ArchDefinePpcgr) 998 .Case("630", ArchDefineName | ArchDefinePpcgr) 999 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1000 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1001 .Case("750", ArchDefineName | ArchDefinePpcgr) 1002 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1003 | ArchDefinePpcsq) 1004 .Case("a2", ArchDefineA2) 1005 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1006 .Case("pwr3", ArchDefinePpcgr) 1007 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1008 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1009 | ArchDefinePpcsq) 1010 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1011 | ArchDefinePpcgr | ArchDefinePpcsq) 1012 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1013 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1014 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1015 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1016 | ArchDefinePpcsq) 1017 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1018 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1019 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 1020 .Case("power3", ArchDefinePpcgr) 1021 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1022 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1023 | ArchDefinePpcsq) 1024 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1025 | ArchDefinePpcgr | ArchDefinePpcsq) 1026 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1027 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1028 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1029 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1030 | ArchDefinePpcsq) 1031 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1032 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1033 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 1034 .Default(ArchDefineNone); 1035 1036 if (defs & ArchDefineName) 1037 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1038 if (defs & ArchDefinePpcgr) 1039 Builder.defineMacro("_ARCH_PPCGR"); 1040 if (defs & ArchDefinePpcsq) 1041 Builder.defineMacro("_ARCH_PPCSQ"); 1042 if (defs & ArchDefine440) 1043 Builder.defineMacro("_ARCH_440"); 1044 if (defs & ArchDefine603) 1045 Builder.defineMacro("_ARCH_603"); 1046 if (defs & ArchDefine604) 1047 Builder.defineMacro("_ARCH_604"); 1048 if (defs & ArchDefinePwr4) 1049 Builder.defineMacro("_ARCH_PWR4"); 1050 if (defs & ArchDefinePwr5) 1051 Builder.defineMacro("_ARCH_PWR5"); 1052 if (defs & ArchDefinePwr5x) 1053 Builder.defineMacro("_ARCH_PWR5X"); 1054 if (defs & ArchDefinePwr6) 1055 Builder.defineMacro("_ARCH_PWR6"); 1056 if (defs & ArchDefinePwr6x) 1057 Builder.defineMacro("_ARCH_PWR6X"); 1058 if (defs & ArchDefinePwr7) 1059 Builder.defineMacro("_ARCH_PWR7"); 1060 if (defs & ArchDefineA2) 1061 Builder.defineMacro("_ARCH_A2"); 1062 if (defs & ArchDefineA2q) { 1063 Builder.defineMacro("_ARCH_A2Q"); 1064 Builder.defineMacro("_ARCH_QP"); 1065 } 1066 1067 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1068 Builder.defineMacro("__bg__"); 1069 Builder.defineMacro("__THW_BLUEGENE__"); 1070 Builder.defineMacro("__bgq__"); 1071 Builder.defineMacro("__TOS_BGQ__"); 1072 } 1073 1074 if (HasVSX) 1075 Builder.defineMacro("__VSX__"); 1076 1077 // FIXME: The following are not yet generated here by Clang, but are 1078 // generated by GCC: 1079 // 1080 // _SOFT_FLOAT_ 1081 // __RECIP_PRECISION__ 1082 // __APPLE_ALTIVEC__ 1083 // __RECIP__ 1084 // __RECIPF__ 1085 // __RSQRTE__ 1086 // __RSQRTEF__ 1087 // _SOFT_DOUBLE_ 1088 // __NO_LWSYNC__ 1089 // __HAVE_BSWAP__ 1090 // __LONGDOUBLE128 1091 // __CMODEL_MEDIUM__ 1092 // __CMODEL_LARGE__ 1093 // _CALL_SYSV 1094 // _CALL_DARWIN 1095 // __NO_FPRS__ 1096 } 1097 1098 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1099 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1100 .Case("7400", true) 1101 .Case("g4", true) 1102 .Case("7450", true) 1103 .Case("g4+", true) 1104 .Case("970", true) 1105 .Case("g5", true) 1106 .Case("pwr6", true) 1107 .Case("pwr7", true) 1108 .Case("ppc64", true) 1109 .Case("ppc64le", true) 1110 .Default(false); 1111 1112 Features["qpx"] = (CPU == "a2q"); 1113 } 1114 1115 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1116 return Feature == "powerpc"; 1117 } 1118 1119 1120 const char * const PPCTargetInfo::GCCRegNames[] = { 1121 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1122 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1123 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1124 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1125 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1126 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1127 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1128 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1129 "mq", "lr", "ctr", "ap", 1130 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1131 "xer", 1132 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1133 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1134 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1135 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1136 "vrsave", "vscr", 1137 "spe_acc", "spefscr", 1138 "sfp" 1139 }; 1140 1141 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1142 unsigned &NumNames) const { 1143 Names = GCCRegNames; 1144 NumNames = llvm::array_lengthof(GCCRegNames); 1145 } 1146 1147 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1148 // While some of these aliases do map to different registers 1149 // they still share the same register name. 1150 { { "0" }, "r0" }, 1151 { { "1"}, "r1" }, 1152 { { "2" }, "r2" }, 1153 { { "3" }, "r3" }, 1154 { { "4" }, "r4" }, 1155 { { "5" }, "r5" }, 1156 { { "6" }, "r6" }, 1157 { { "7" }, "r7" }, 1158 { { "8" }, "r8" }, 1159 { { "9" }, "r9" }, 1160 { { "10" }, "r10" }, 1161 { { "11" }, "r11" }, 1162 { { "12" }, "r12" }, 1163 { { "13" }, "r13" }, 1164 { { "14" }, "r14" }, 1165 { { "15" }, "r15" }, 1166 { { "16" }, "r16" }, 1167 { { "17" }, "r17" }, 1168 { { "18" }, "r18" }, 1169 { { "19" }, "r19" }, 1170 { { "20" }, "r20" }, 1171 { { "21" }, "r21" }, 1172 { { "22" }, "r22" }, 1173 { { "23" }, "r23" }, 1174 { { "24" }, "r24" }, 1175 { { "25" }, "r25" }, 1176 { { "26" }, "r26" }, 1177 { { "27" }, "r27" }, 1178 { { "28" }, "r28" }, 1179 { { "29" }, "r29" }, 1180 { { "30" }, "r30" }, 1181 { { "31" }, "r31" }, 1182 { { "fr0" }, "f0" }, 1183 { { "fr1" }, "f1" }, 1184 { { "fr2" }, "f2" }, 1185 { { "fr3" }, "f3" }, 1186 { { "fr4" }, "f4" }, 1187 { { "fr5" }, "f5" }, 1188 { { "fr6" }, "f6" }, 1189 { { "fr7" }, "f7" }, 1190 { { "fr8" }, "f8" }, 1191 { { "fr9" }, "f9" }, 1192 { { "fr10" }, "f10" }, 1193 { { "fr11" }, "f11" }, 1194 { { "fr12" }, "f12" }, 1195 { { "fr13" }, "f13" }, 1196 { { "fr14" }, "f14" }, 1197 { { "fr15" }, "f15" }, 1198 { { "fr16" }, "f16" }, 1199 { { "fr17" }, "f17" }, 1200 { { "fr18" }, "f18" }, 1201 { { "fr19" }, "f19" }, 1202 { { "fr20" }, "f20" }, 1203 { { "fr21" }, "f21" }, 1204 { { "fr22" }, "f22" }, 1205 { { "fr23" }, "f23" }, 1206 { { "fr24" }, "f24" }, 1207 { { "fr25" }, "f25" }, 1208 { { "fr26" }, "f26" }, 1209 { { "fr27" }, "f27" }, 1210 { { "fr28" }, "f28" }, 1211 { { "fr29" }, "f29" }, 1212 { { "fr30" }, "f30" }, 1213 { { "fr31" }, "f31" }, 1214 { { "cc" }, "cr0" }, 1215 }; 1216 1217 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1218 unsigned &NumAliases) const { 1219 Aliases = GCCRegAliases; 1220 NumAliases = llvm::array_lengthof(GCCRegAliases); 1221 } 1222 } // end anonymous namespace. 1223 1224 namespace { 1225 class PPC32TargetInfo : public PPCTargetInfo { 1226 public: 1227 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1228 DescriptionString = "E-m:e-p:32:32-i64:64-n32"; 1229 1230 switch (getTriple().getOS()) { 1231 case llvm::Triple::Linux: 1232 case llvm::Triple::FreeBSD: 1233 case llvm::Triple::NetBSD: 1234 SizeType = UnsignedInt; 1235 PtrDiffType = SignedInt; 1236 IntPtrType = SignedInt; 1237 break; 1238 default: 1239 break; 1240 } 1241 1242 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1243 LongDoubleWidth = LongDoubleAlign = 64; 1244 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1245 } 1246 1247 // PPC32 supports atomics up to 4 bytes. 1248 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1249 } 1250 1251 BuiltinVaListKind getBuiltinVaListKind() const override { 1252 // This is the ELF definition, and is overridden by the Darwin sub-target 1253 return TargetInfo::PowerABIBuiltinVaList; 1254 } 1255 }; 1256 } // end anonymous namespace. 1257 1258 // Note: ABI differences may eventually require us to have a separate 1259 // TargetInfo for little endian. 1260 namespace { 1261 class PPC64TargetInfo : public PPCTargetInfo { 1262 public: 1263 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1264 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1265 IntMaxType = SignedLong; 1266 UIntMaxType = UnsignedLong; 1267 Int64Type = SignedLong; 1268 1269 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1270 LongDoubleWidth = LongDoubleAlign = 64; 1271 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1272 DescriptionString = "E-m:e-i64:64-n32:64"; 1273 } else { 1274 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1275 DescriptionString = "e-m:e-i64:64-n32:64"; 1276 } else { 1277 DescriptionString = "E-m:e-i64:64-n32:64"; 1278 } 1279 } 1280 1281 // PPC64 supports atomics up to 8 bytes. 1282 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1283 } 1284 BuiltinVaListKind getBuiltinVaListKind() const override { 1285 return TargetInfo::CharPtrBuiltinVaList; 1286 } 1287 }; 1288 } // end anonymous namespace. 1289 1290 1291 namespace { 1292 class DarwinPPC32TargetInfo : 1293 public DarwinTargetInfo<PPC32TargetInfo> { 1294 public: 1295 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1296 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1297 HasAlignMac68kSupport = true; 1298 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1299 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1300 LongLongAlign = 32; 1301 SuitableAlign = 128; 1302 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; 1303 } 1304 BuiltinVaListKind getBuiltinVaListKind() const override { 1305 return TargetInfo::CharPtrBuiltinVaList; 1306 } 1307 }; 1308 1309 class DarwinPPC64TargetInfo : 1310 public DarwinTargetInfo<PPC64TargetInfo> { 1311 public: 1312 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1313 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1314 HasAlignMac68kSupport = true; 1315 SuitableAlign = 128; 1316 DescriptionString = "E-m:o-i64:64-n32:64"; 1317 } 1318 }; 1319 } // end anonymous namespace. 1320 1321 namespace { 1322 static const unsigned NVPTXAddrSpaceMap[] = { 1323 1, // opencl_global 1324 3, // opencl_local 1325 4, // opencl_constant 1326 1, // cuda_device 1327 4, // cuda_constant 1328 3, // cuda_shared 1329 }; 1330 class NVPTXTargetInfo : public TargetInfo { 1331 static const char * const GCCRegNames[]; 1332 static const Builtin::Info BuiltinInfo[]; 1333 public: 1334 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1335 BigEndian = false; 1336 TLSSupported = false; 1337 LongWidth = LongAlign = 64; 1338 AddrSpaceMap = &NVPTXAddrSpaceMap; 1339 UseAddrSpaceMapMangling = true; 1340 // Define available target features 1341 // These must be defined in sorted order! 1342 NoAsmVariants = true; 1343 } 1344 void getTargetDefines(const LangOptions &Opts, 1345 MacroBuilder &Builder) const override { 1346 Builder.defineMacro("__PTX__"); 1347 Builder.defineMacro("__NVPTX__"); 1348 } 1349 void getTargetBuiltins(const Builtin::Info *&Records, 1350 unsigned &NumRecords) const override { 1351 Records = BuiltinInfo; 1352 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1353 } 1354 bool hasFeature(StringRef Feature) const override { 1355 return Feature == "ptx" || Feature == "nvptx"; 1356 } 1357 1358 void getGCCRegNames(const char * const *&Names, 1359 unsigned &NumNames) const override; 1360 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1361 unsigned &NumAliases) const override { 1362 // No aliases. 1363 Aliases = nullptr; 1364 NumAliases = 0; 1365 } 1366 bool validateAsmConstraint(const char *&Name, 1367 TargetInfo::ConstraintInfo &Info) const override { 1368 switch (*Name) { 1369 default: return false; 1370 case 'c': 1371 case 'h': 1372 case 'r': 1373 case 'l': 1374 case 'f': 1375 case 'd': 1376 Info.setAllowsRegister(); 1377 return true; 1378 } 1379 } 1380 const char *getClobbers() const override { 1381 // FIXME: Is this really right? 1382 return ""; 1383 } 1384 BuiltinVaListKind getBuiltinVaListKind() const override { 1385 // FIXME: implement 1386 return TargetInfo::CharPtrBuiltinVaList; 1387 } 1388 bool setCPU(const std::string &Name) override { 1389 bool Valid = llvm::StringSwitch<bool>(Name) 1390 .Case("sm_20", true) 1391 .Case("sm_21", true) 1392 .Case("sm_30", true) 1393 .Case("sm_35", true) 1394 .Default(false); 1395 1396 return Valid; 1397 } 1398 }; 1399 1400 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1401 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1402 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1403 ALL_LANGUAGES }, 1404 #include "clang/Basic/BuiltinsNVPTX.def" 1405 }; 1406 1407 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1408 "r0" 1409 }; 1410 1411 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1412 unsigned &NumNames) const { 1413 Names = GCCRegNames; 1414 NumNames = llvm::array_lengthof(GCCRegNames); 1415 } 1416 1417 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1418 public: 1419 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1420 PointerWidth = PointerAlign = 32; 1421 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt; 1422 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1423 } 1424 }; 1425 1426 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1427 public: 1428 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1429 PointerWidth = PointerAlign = 64; 1430 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong; 1431 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1432 } 1433 }; 1434 } 1435 1436 namespace { 1437 1438 static const unsigned R600AddrSpaceMap[] = { 1439 1, // opencl_global 1440 3, // opencl_local 1441 2, // opencl_constant 1442 1, // cuda_device 1443 2, // cuda_constant 1444 3 // cuda_shared 1445 }; 1446 1447 static const char *DescriptionStringR600 = 1448 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1449 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1450 1451 static const char *DescriptionStringR600DoubleOps = 1452 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1453 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1454 1455 static const char *DescriptionStringSI = 1456 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1457 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1458 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1459 1460 class R600TargetInfo : public TargetInfo { 1461 /// \brief The GPU profiles supported by the R600 target. 1462 enum GPUKind { 1463 GK_NONE, 1464 GK_R600, 1465 GK_R600_DOUBLE_OPS, 1466 GK_R700, 1467 GK_R700_DOUBLE_OPS, 1468 GK_EVERGREEN, 1469 GK_EVERGREEN_DOUBLE_OPS, 1470 GK_NORTHERN_ISLANDS, 1471 GK_CAYMAN, 1472 GK_SOUTHERN_ISLANDS, 1473 GK_SEA_ISLANDS 1474 } GPU; 1475 1476 public: 1477 R600TargetInfo(const llvm::Triple &Triple) 1478 : TargetInfo(Triple), GPU(GK_R600) { 1479 DescriptionString = DescriptionStringR600; 1480 AddrSpaceMap = &R600AddrSpaceMap; 1481 UseAddrSpaceMapMangling = true; 1482 } 1483 1484 const char * getClobbers() const override { 1485 return ""; 1486 } 1487 1488 void getGCCRegNames(const char * const *&Names, 1489 unsigned &numNames) const override { 1490 Names = nullptr; 1491 numNames = 0; 1492 } 1493 1494 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1495 unsigned &NumAliases) const override { 1496 Aliases = nullptr; 1497 NumAliases = 0; 1498 } 1499 1500 bool validateAsmConstraint(const char *&Name, 1501 TargetInfo::ConstraintInfo &info) const override { 1502 return true; 1503 } 1504 1505 void getTargetBuiltins(const Builtin::Info *&Records, 1506 unsigned &NumRecords) const override { 1507 Records = nullptr; 1508 NumRecords = 0; 1509 } 1510 1511 1512 void getTargetDefines(const LangOptions &Opts, 1513 MacroBuilder &Builder) const override { 1514 Builder.defineMacro("__R600__"); 1515 } 1516 1517 BuiltinVaListKind getBuiltinVaListKind() const override { 1518 return TargetInfo::CharPtrBuiltinVaList; 1519 } 1520 1521 bool setCPU(const std::string &Name) override { 1522 GPU = llvm::StringSwitch<GPUKind>(Name) 1523 .Case("r600" , GK_R600) 1524 .Case("rv610", GK_R600) 1525 .Case("rv620", GK_R600) 1526 .Case("rv630", GK_R600) 1527 .Case("rv635", GK_R600) 1528 .Case("rs780", GK_R600) 1529 .Case("rs880", GK_R600) 1530 .Case("rv670", GK_R600_DOUBLE_OPS) 1531 .Case("rv710", GK_R700) 1532 .Case("rv730", GK_R700) 1533 .Case("rv740", GK_R700_DOUBLE_OPS) 1534 .Case("rv770", GK_R700_DOUBLE_OPS) 1535 .Case("palm", GK_EVERGREEN) 1536 .Case("cedar", GK_EVERGREEN) 1537 .Case("sumo", GK_EVERGREEN) 1538 .Case("sumo2", GK_EVERGREEN) 1539 .Case("redwood", GK_EVERGREEN) 1540 .Case("juniper", GK_EVERGREEN) 1541 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1542 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1543 .Case("barts", GK_NORTHERN_ISLANDS) 1544 .Case("turks", GK_NORTHERN_ISLANDS) 1545 .Case("caicos", GK_NORTHERN_ISLANDS) 1546 .Case("cayman", GK_CAYMAN) 1547 .Case("aruba", GK_CAYMAN) 1548 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1549 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1550 .Case("verde", GK_SOUTHERN_ISLANDS) 1551 .Case("oland", GK_SOUTHERN_ISLANDS) 1552 .Case("bonaire", GK_SEA_ISLANDS) 1553 .Case("kabini", GK_SEA_ISLANDS) 1554 .Case("kaveri", GK_SEA_ISLANDS) 1555 .Case("hawaii", GK_SEA_ISLANDS) 1556 .Default(GK_NONE); 1557 1558 if (GPU == GK_NONE) { 1559 return false; 1560 } 1561 1562 // Set the correct data layout 1563 switch (GPU) { 1564 case GK_NONE: 1565 case GK_R600: 1566 case GK_R700: 1567 case GK_EVERGREEN: 1568 case GK_NORTHERN_ISLANDS: 1569 DescriptionString = DescriptionStringR600; 1570 break; 1571 case GK_R600_DOUBLE_OPS: 1572 case GK_R700_DOUBLE_OPS: 1573 case GK_EVERGREEN_DOUBLE_OPS: 1574 case GK_CAYMAN: 1575 DescriptionString = DescriptionStringR600DoubleOps; 1576 break; 1577 case GK_SOUTHERN_ISLANDS: 1578 case GK_SEA_ISLANDS: 1579 DescriptionString = DescriptionStringSI; 1580 break; 1581 } 1582 1583 return true; 1584 } 1585 }; 1586 1587 } // end anonymous namespace 1588 1589 namespace { 1590 // Namespace for x86 abstract base class 1591 const Builtin::Info BuiltinInfo[] = { 1592 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1593 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1594 ALL_LANGUAGES }, 1595 #include "clang/Basic/BuiltinsX86.def" 1596 }; 1597 1598 static const char* const GCCRegNames[] = { 1599 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1600 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1601 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1602 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1603 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1604 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1605 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1606 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1607 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1608 }; 1609 1610 const TargetInfo::AddlRegName AddlRegNames[] = { 1611 { { "al", "ah", "eax", "rax" }, 0 }, 1612 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1613 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1614 { { "dl", "dh", "edx", "rdx" }, 1 }, 1615 { { "esi", "rsi" }, 4 }, 1616 { { "edi", "rdi" }, 5 }, 1617 { { "esp", "rsp" }, 7 }, 1618 { { "ebp", "rbp" }, 6 }, 1619 }; 1620 1621 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1622 // most of the implementation can be shared. 1623 class X86TargetInfo : public TargetInfo { 1624 enum X86SSEEnum { 1625 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1626 } SSELevel; 1627 enum MMX3DNowEnum { 1628 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1629 } MMX3DNowLevel; 1630 enum XOPEnum { 1631 NoXOP, 1632 SSE4A, 1633 FMA4, 1634 XOP 1635 } XOPLevel; 1636 1637 bool HasAES; 1638 bool HasPCLMUL; 1639 bool HasLZCNT; 1640 bool HasRDRND; 1641 bool HasBMI; 1642 bool HasBMI2; 1643 bool HasPOPCNT; 1644 bool HasRTM; 1645 bool HasPRFCHW; 1646 bool HasRDSEED; 1647 bool HasTBM; 1648 bool HasFMA; 1649 bool HasF16C; 1650 bool HasAVX512CD, HasAVX512ER, HasAVX512PF; 1651 bool HasSHA; 1652 bool HasCX16; 1653 1654 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1655 /// 1656 /// Each enumeration represents a particular CPU supported by Clang. These 1657 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1658 enum CPUKind { 1659 CK_Generic, 1660 1661 /// \name i386 1662 /// i386-generation processors. 1663 //@{ 1664 CK_i386, 1665 //@} 1666 1667 /// \name i486 1668 /// i486-generation processors. 1669 //@{ 1670 CK_i486, 1671 CK_WinChipC6, 1672 CK_WinChip2, 1673 CK_C3, 1674 //@} 1675 1676 /// \name i586 1677 /// i586-generation processors, P5 microarchitecture based. 1678 //@{ 1679 CK_i586, 1680 CK_Pentium, 1681 CK_PentiumMMX, 1682 //@} 1683 1684 /// \name i686 1685 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1686 //@{ 1687 CK_i686, 1688 CK_PentiumPro, 1689 CK_Pentium2, 1690 CK_Pentium3, 1691 CK_Pentium3M, 1692 CK_PentiumM, 1693 CK_C3_2, 1694 1695 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1696 /// Clang however has some logic to suport this. 1697 // FIXME: Warn, deprecate, and potentially remove this. 1698 CK_Yonah, 1699 //@} 1700 1701 /// \name Netburst 1702 /// Netburst microarchitecture based processors. 1703 //@{ 1704 CK_Pentium4, 1705 CK_Pentium4M, 1706 CK_Prescott, 1707 CK_Nocona, 1708 //@} 1709 1710 /// \name Core 1711 /// Core microarchitecture based processors. 1712 //@{ 1713 CK_Core2, 1714 1715 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1716 /// codename which GCC no longer accepts as an option to -march, but Clang 1717 /// has some logic for recognizing it. 1718 // FIXME: Warn, deprecate, and potentially remove this. 1719 CK_Penryn, 1720 //@} 1721 1722 /// \name Atom 1723 /// Atom processors 1724 //@{ 1725 CK_Atom, 1726 CK_Silvermont, 1727 //@} 1728 1729 /// \name Nehalem 1730 /// Nehalem microarchitecture based processors. 1731 //@{ 1732 CK_Corei7, 1733 CK_Corei7AVX, 1734 CK_CoreAVXi, 1735 CK_CoreAVX2, 1736 //@} 1737 1738 /// \name Knights Landing 1739 /// Knights Landing processor. 1740 CK_KNL, 1741 1742 /// \name K6 1743 /// K6 architecture processors. 1744 //@{ 1745 CK_K6, 1746 CK_K6_2, 1747 CK_K6_3, 1748 //@} 1749 1750 /// \name K7 1751 /// K7 architecture processors. 1752 //@{ 1753 CK_Athlon, 1754 CK_AthlonThunderbird, 1755 CK_Athlon4, 1756 CK_AthlonXP, 1757 CK_AthlonMP, 1758 //@} 1759 1760 /// \name K8 1761 /// K8 architecture processors. 1762 //@{ 1763 CK_Athlon64, 1764 CK_Athlon64SSE3, 1765 CK_AthlonFX, 1766 CK_K8, 1767 CK_K8SSE3, 1768 CK_Opteron, 1769 CK_OpteronSSE3, 1770 CK_AMDFAM10, 1771 //@} 1772 1773 /// \name Bobcat 1774 /// Bobcat architecture processors. 1775 //@{ 1776 CK_BTVER1, 1777 CK_BTVER2, 1778 //@} 1779 1780 /// \name Bulldozer 1781 /// Bulldozer architecture processors. 1782 //@{ 1783 CK_BDVER1, 1784 CK_BDVER2, 1785 CK_BDVER3, 1786 CK_BDVER4, 1787 //@} 1788 1789 /// This specification is deprecated and will be removed in the future. 1790 /// Users should prefer \see CK_K8. 1791 // FIXME: Warn on this when the CPU is set to it. 1792 CK_x86_64, 1793 //@} 1794 1795 /// \name Geode 1796 /// Geode processors. 1797 //@{ 1798 CK_Geode 1799 //@} 1800 } CPU; 1801 1802 enum FPMathKind { 1803 FP_Default, 1804 FP_SSE, 1805 FP_387 1806 } FPMath; 1807 1808 public: 1809 X86TargetInfo(const llvm::Triple &Triple) 1810 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1811 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 1812 HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false), 1813 HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasTBM(false), 1814 HasFMA(false), HasF16C(false), HasAVX512CD(false), HasAVX512ER(false), 1815 HasAVX512PF(false), HasSHA(false), HasCX16(false), CPU(CK_Generic), 1816 FPMath(FP_Default) { 1817 BigEndian = false; 1818 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1819 } 1820 unsigned getFloatEvalMethod() const override { 1821 // X87 evaluates with 80 bits "long double" precision. 1822 return SSELevel == NoSSE ? 2 : 0; 1823 } 1824 void getTargetBuiltins(const Builtin::Info *&Records, 1825 unsigned &NumRecords) const override { 1826 Records = BuiltinInfo; 1827 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1828 } 1829 void getGCCRegNames(const char * const *&Names, 1830 unsigned &NumNames) const override { 1831 Names = GCCRegNames; 1832 NumNames = llvm::array_lengthof(GCCRegNames); 1833 } 1834 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1835 unsigned &NumAliases) const override { 1836 Aliases = nullptr; 1837 NumAliases = 0; 1838 } 1839 void getGCCAddlRegNames(const AddlRegName *&Names, 1840 unsigned &NumNames) const override { 1841 Names = AddlRegNames; 1842 NumNames = llvm::array_lengthof(AddlRegNames); 1843 } 1844 bool validateAsmConstraint(const char *&Name, 1845 TargetInfo::ConstraintInfo &info) const override; 1846 std::string convertConstraint(const char *&Constraint) const override; 1847 const char *getClobbers() const override { 1848 return "~{dirflag},~{fpsr},~{flags}"; 1849 } 1850 void getTargetDefines(const LangOptions &Opts, 1851 MacroBuilder &Builder) const override; 1852 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 1853 bool Enabled); 1854 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 1855 bool Enabled); 1856 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 1857 bool Enabled); 1858 void setFeatureEnabled(llvm::StringMap<bool> &Features, 1859 StringRef Name, bool Enabled) const override { 1860 setFeatureEnabledImpl(Features, Name, Enabled); 1861 } 1862 // This exists purely to cut down on the number of virtual calls in 1863 // getDefaultFeatures which calls this repeatedly. 1864 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 1865 StringRef Name, bool Enabled); 1866 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 1867 bool hasFeature(StringRef Feature) const override; 1868 bool handleTargetFeatures(std::vector<std::string> &Features, 1869 DiagnosticsEngine &Diags) override; 1870 StringRef getABI() const override { 1871 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 1872 return "avx"; 1873 else if (getTriple().getArch() == llvm::Triple::x86 && 1874 MMX3DNowLevel == NoMMX3DNow) 1875 return "no-mmx"; 1876 return ""; 1877 } 1878 bool setCPU(const std::string &Name) override { 1879 CPU = llvm::StringSwitch<CPUKind>(Name) 1880 .Case("i386", CK_i386) 1881 .Case("i486", CK_i486) 1882 .Case("winchip-c6", CK_WinChipC6) 1883 .Case("winchip2", CK_WinChip2) 1884 .Case("c3", CK_C3) 1885 .Case("i586", CK_i586) 1886 .Case("pentium", CK_Pentium) 1887 .Case("pentium-mmx", CK_PentiumMMX) 1888 .Case("i686", CK_i686) 1889 .Case("pentiumpro", CK_PentiumPro) 1890 .Case("pentium2", CK_Pentium2) 1891 .Case("pentium3", CK_Pentium3) 1892 .Case("pentium3m", CK_Pentium3M) 1893 .Case("pentium-m", CK_PentiumM) 1894 .Case("c3-2", CK_C3_2) 1895 .Case("yonah", CK_Yonah) 1896 .Case("pentium4", CK_Pentium4) 1897 .Case("pentium4m", CK_Pentium4M) 1898 .Case("prescott", CK_Prescott) 1899 .Case("nocona", CK_Nocona) 1900 .Case("core2", CK_Core2) 1901 .Case("penryn", CK_Penryn) 1902 .Case("atom", CK_Atom) 1903 .Case("slm", CK_Silvermont) 1904 .Case("corei7", CK_Corei7) 1905 .Case("corei7-avx", CK_Corei7AVX) 1906 .Case("core-avx-i", CK_CoreAVXi) 1907 .Case("core-avx2", CK_CoreAVX2) 1908 .Case("knl", CK_KNL) 1909 .Case("k6", CK_K6) 1910 .Case("k6-2", CK_K6_2) 1911 .Case("k6-3", CK_K6_3) 1912 .Case("athlon", CK_Athlon) 1913 .Case("athlon-tbird", CK_AthlonThunderbird) 1914 .Case("athlon-4", CK_Athlon4) 1915 .Case("athlon-xp", CK_AthlonXP) 1916 .Case("athlon-mp", CK_AthlonMP) 1917 .Case("athlon64", CK_Athlon64) 1918 .Case("athlon64-sse3", CK_Athlon64SSE3) 1919 .Case("athlon-fx", CK_AthlonFX) 1920 .Case("k8", CK_K8) 1921 .Case("k8-sse3", CK_K8SSE3) 1922 .Case("opteron", CK_Opteron) 1923 .Case("opteron-sse3", CK_OpteronSSE3) 1924 .Case("amdfam10", CK_AMDFAM10) 1925 .Case("btver1", CK_BTVER1) 1926 .Case("btver2", CK_BTVER2) 1927 .Case("bdver1", CK_BDVER1) 1928 .Case("bdver2", CK_BDVER2) 1929 .Case("bdver3", CK_BDVER3) 1930 .Case("bdver4", CK_BDVER4) 1931 .Case("x86-64", CK_x86_64) 1932 .Case("geode", CK_Geode) 1933 .Default(CK_Generic); 1934 1935 // Perform any per-CPU checks necessary to determine if this CPU is 1936 // acceptable. 1937 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1938 // invalid without explaining *why*. 1939 switch (CPU) { 1940 case CK_Generic: 1941 // No processor selected! 1942 return false; 1943 1944 case CK_i386: 1945 case CK_i486: 1946 case CK_WinChipC6: 1947 case CK_WinChip2: 1948 case CK_C3: 1949 case CK_i586: 1950 case CK_Pentium: 1951 case CK_PentiumMMX: 1952 case CK_i686: 1953 case CK_PentiumPro: 1954 case CK_Pentium2: 1955 case CK_Pentium3: 1956 case CK_Pentium3M: 1957 case CK_PentiumM: 1958 case CK_Yonah: 1959 case CK_C3_2: 1960 case CK_Pentium4: 1961 case CK_Pentium4M: 1962 case CK_Prescott: 1963 case CK_K6: 1964 case CK_K6_2: 1965 case CK_K6_3: 1966 case CK_Athlon: 1967 case CK_AthlonThunderbird: 1968 case CK_Athlon4: 1969 case CK_AthlonXP: 1970 case CK_AthlonMP: 1971 case CK_Geode: 1972 // Only accept certain architectures when compiling in 32-bit mode. 1973 if (getTriple().getArch() != llvm::Triple::x86) 1974 return false; 1975 1976 // Fallthrough 1977 case CK_Nocona: 1978 case CK_Core2: 1979 case CK_Penryn: 1980 case CK_Atom: 1981 case CK_Silvermont: 1982 case CK_Corei7: 1983 case CK_Corei7AVX: 1984 case CK_CoreAVXi: 1985 case CK_CoreAVX2: 1986 case CK_KNL: 1987 case CK_Athlon64: 1988 case CK_Athlon64SSE3: 1989 case CK_AthlonFX: 1990 case CK_K8: 1991 case CK_K8SSE3: 1992 case CK_Opteron: 1993 case CK_OpteronSSE3: 1994 case CK_AMDFAM10: 1995 case CK_BTVER1: 1996 case CK_BTVER2: 1997 case CK_BDVER1: 1998 case CK_BDVER2: 1999 case CK_BDVER3: 2000 case CK_BDVER4: 2001 case CK_x86_64: 2002 return true; 2003 } 2004 llvm_unreachable("Unhandled CPU kind"); 2005 } 2006 2007 bool setFPMath(StringRef Name) override; 2008 2009 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2010 // We accept all non-ARM calling conventions 2011 return (CC == CC_X86ThisCall || 2012 CC == CC_X86FastCall || 2013 CC == CC_X86StdCall || 2014 CC == CC_C || 2015 CC == CC_X86Pascal || 2016 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2017 } 2018 2019 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2020 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2021 } 2022 }; 2023 2024 bool X86TargetInfo::setFPMath(StringRef Name) { 2025 if (Name == "387") { 2026 FPMath = FP_387; 2027 return true; 2028 } 2029 if (Name == "sse") { 2030 FPMath = FP_SSE; 2031 return true; 2032 } 2033 return false; 2034 } 2035 2036 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2037 // FIXME: This *really* should not be here. 2038 2039 // X86_64 always has SSE2. 2040 if (getTriple().getArch() == llvm::Triple::x86_64) 2041 setFeatureEnabledImpl(Features, "sse2", true); 2042 2043 switch (CPU) { 2044 case CK_Generic: 2045 case CK_i386: 2046 case CK_i486: 2047 case CK_i586: 2048 case CK_Pentium: 2049 case CK_i686: 2050 case CK_PentiumPro: 2051 break; 2052 case CK_PentiumMMX: 2053 case CK_Pentium2: 2054 setFeatureEnabledImpl(Features, "mmx", true); 2055 break; 2056 case CK_Pentium3: 2057 case CK_Pentium3M: 2058 setFeatureEnabledImpl(Features, "sse", true); 2059 break; 2060 case CK_PentiumM: 2061 case CK_Pentium4: 2062 case CK_Pentium4M: 2063 case CK_x86_64: 2064 setFeatureEnabledImpl(Features, "sse2", true); 2065 break; 2066 case CK_Yonah: 2067 case CK_Prescott: 2068 case CK_Nocona: 2069 setFeatureEnabledImpl(Features, "sse3", true); 2070 setFeatureEnabledImpl(Features, "cx16", true); 2071 break; 2072 case CK_Core2: 2073 setFeatureEnabledImpl(Features, "ssse3", true); 2074 setFeatureEnabledImpl(Features, "cx16", true); 2075 break; 2076 case CK_Penryn: 2077 setFeatureEnabledImpl(Features, "sse4.1", true); 2078 setFeatureEnabledImpl(Features, "cx16", true); 2079 break; 2080 case CK_Atom: 2081 setFeatureEnabledImpl(Features, "ssse3", true); 2082 setFeatureEnabledImpl(Features, "cx16", true); 2083 break; 2084 case CK_Silvermont: 2085 setFeatureEnabledImpl(Features, "sse4.2", true); 2086 setFeatureEnabledImpl(Features, "aes", true); 2087 setFeatureEnabledImpl(Features, "cx16", true); 2088 setFeatureEnabledImpl(Features, "pclmul", true); 2089 break; 2090 case CK_Corei7: 2091 setFeatureEnabledImpl(Features, "sse4.2", true); 2092 setFeatureEnabledImpl(Features, "cx16", true); 2093 break; 2094 case CK_Corei7AVX: 2095 setFeatureEnabledImpl(Features, "avx", true); 2096 setFeatureEnabledImpl(Features, "aes", true); 2097 setFeatureEnabledImpl(Features, "cx16", true); 2098 setFeatureEnabledImpl(Features, "pclmul", true); 2099 break; 2100 case CK_CoreAVXi: 2101 setFeatureEnabledImpl(Features, "avx", true); 2102 setFeatureEnabledImpl(Features, "aes", true); 2103 setFeatureEnabledImpl(Features, "pclmul", true); 2104 setFeatureEnabledImpl(Features, "rdrnd", true); 2105 setFeatureEnabledImpl(Features, "f16c", true); 2106 break; 2107 case CK_CoreAVX2: 2108 setFeatureEnabledImpl(Features, "avx2", true); 2109 setFeatureEnabledImpl(Features, "aes", true); 2110 setFeatureEnabledImpl(Features, "pclmul", true); 2111 setFeatureEnabledImpl(Features, "lzcnt", true); 2112 setFeatureEnabledImpl(Features, "rdrnd", true); 2113 setFeatureEnabledImpl(Features, "f16c", true); 2114 setFeatureEnabledImpl(Features, "bmi", true); 2115 setFeatureEnabledImpl(Features, "bmi2", true); 2116 setFeatureEnabledImpl(Features, "rtm", true); 2117 setFeatureEnabledImpl(Features, "fma", true); 2118 setFeatureEnabledImpl(Features, "cx16", true); 2119 break; 2120 case CK_KNL: 2121 setFeatureEnabledImpl(Features, "avx512f", true); 2122 setFeatureEnabledImpl(Features, "avx512cd", true); 2123 setFeatureEnabledImpl(Features, "avx512er", true); 2124 setFeatureEnabledImpl(Features, "avx512pf", true); 2125 setFeatureEnabledImpl(Features, "aes", true); 2126 setFeatureEnabledImpl(Features, "pclmul", true); 2127 setFeatureEnabledImpl(Features, "lzcnt", true); 2128 setFeatureEnabledImpl(Features, "rdrnd", true); 2129 setFeatureEnabledImpl(Features, "f16c", true); 2130 setFeatureEnabledImpl(Features, "bmi", true); 2131 setFeatureEnabledImpl(Features, "bmi2", true); 2132 setFeatureEnabledImpl(Features, "rtm", true); 2133 setFeatureEnabledImpl(Features, "fma", true); 2134 break; 2135 case CK_K6: 2136 case CK_WinChipC6: 2137 setFeatureEnabledImpl(Features, "mmx", true); 2138 break; 2139 case CK_K6_2: 2140 case CK_K6_3: 2141 case CK_WinChip2: 2142 case CK_C3: 2143 setFeatureEnabledImpl(Features, "3dnow", true); 2144 break; 2145 case CK_Athlon: 2146 case CK_AthlonThunderbird: 2147 case CK_Geode: 2148 setFeatureEnabledImpl(Features, "3dnowa", true); 2149 break; 2150 case CK_Athlon4: 2151 case CK_AthlonXP: 2152 case CK_AthlonMP: 2153 setFeatureEnabledImpl(Features, "sse", true); 2154 setFeatureEnabledImpl(Features, "3dnowa", true); 2155 break; 2156 case CK_K8: 2157 case CK_Opteron: 2158 case CK_Athlon64: 2159 case CK_AthlonFX: 2160 setFeatureEnabledImpl(Features, "sse2", true); 2161 setFeatureEnabledImpl(Features, "3dnowa", true); 2162 break; 2163 case CK_K8SSE3: 2164 case CK_OpteronSSE3: 2165 case CK_Athlon64SSE3: 2166 setFeatureEnabledImpl(Features, "sse3", true); 2167 setFeatureEnabledImpl(Features, "3dnowa", true); 2168 break; 2169 case CK_AMDFAM10: 2170 setFeatureEnabledImpl(Features, "sse3", true); 2171 setFeatureEnabledImpl(Features, "sse4a", true); 2172 setFeatureEnabledImpl(Features, "3dnowa", true); 2173 setFeatureEnabledImpl(Features, "lzcnt", true); 2174 setFeatureEnabledImpl(Features, "popcnt", true); 2175 break; 2176 case CK_BTVER1: 2177 setFeatureEnabledImpl(Features, "ssse3", true); 2178 setFeatureEnabledImpl(Features, "sse4a", true); 2179 setFeatureEnabledImpl(Features, "cx16", true); 2180 setFeatureEnabledImpl(Features, "lzcnt", true); 2181 setFeatureEnabledImpl(Features, "popcnt", true); 2182 setFeatureEnabledImpl(Features, "prfchw", true); 2183 break; 2184 case CK_BTVER2: 2185 setFeatureEnabledImpl(Features, "avx", true); 2186 setFeatureEnabledImpl(Features, "sse4a", true); 2187 setFeatureEnabledImpl(Features, "lzcnt", true); 2188 setFeatureEnabledImpl(Features, "aes", true); 2189 setFeatureEnabledImpl(Features, "pclmul", true); 2190 setFeatureEnabledImpl(Features, "prfchw", true); 2191 setFeatureEnabledImpl(Features, "bmi", true); 2192 setFeatureEnabledImpl(Features, "f16c", true); 2193 setFeatureEnabledImpl(Features, "cx16", true); 2194 break; 2195 case CK_BDVER1: 2196 setFeatureEnabledImpl(Features, "xop", true); 2197 setFeatureEnabledImpl(Features, "lzcnt", true); 2198 setFeatureEnabledImpl(Features, "aes", true); 2199 setFeatureEnabledImpl(Features, "pclmul", true); 2200 setFeatureEnabledImpl(Features, "prfchw", true); 2201 setFeatureEnabledImpl(Features, "cx16", true); 2202 break; 2203 case CK_BDVER4: 2204 setFeatureEnabledImpl(Features, "avx2", true); 2205 setFeatureEnabledImpl(Features, "bmi2", true); 2206 // FALLTHROUGH 2207 case CK_BDVER2: 2208 case CK_BDVER3: 2209 setFeatureEnabledImpl(Features, "xop", true); 2210 setFeatureEnabledImpl(Features, "lzcnt", true); 2211 setFeatureEnabledImpl(Features, "aes", true); 2212 setFeatureEnabledImpl(Features, "pclmul", true); 2213 setFeatureEnabledImpl(Features, "prfchw", true); 2214 setFeatureEnabledImpl(Features, "bmi", true); 2215 setFeatureEnabledImpl(Features, "fma", true); 2216 setFeatureEnabledImpl(Features, "f16c", true); 2217 setFeatureEnabledImpl(Features, "tbm", true); 2218 setFeatureEnabledImpl(Features, "cx16", true); 2219 break; 2220 case CK_C3_2: 2221 setFeatureEnabledImpl(Features, "sse", true); 2222 break; 2223 } 2224 } 2225 2226 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2227 X86SSEEnum Level, bool Enabled) { 2228 if (Enabled) { 2229 switch (Level) { 2230 case AVX512F: 2231 Features["avx512f"] = true; 2232 case AVX2: 2233 Features["avx2"] = true; 2234 case AVX: 2235 Features["avx"] = true; 2236 case SSE42: 2237 Features["sse4.2"] = true; 2238 case SSE41: 2239 Features["sse4.1"] = true; 2240 case SSSE3: 2241 Features["ssse3"] = true; 2242 case SSE3: 2243 Features["sse3"] = true; 2244 case SSE2: 2245 Features["sse2"] = true; 2246 case SSE1: 2247 Features["sse"] = true; 2248 case NoSSE: 2249 break; 2250 } 2251 return; 2252 } 2253 2254 switch (Level) { 2255 case NoSSE: 2256 case SSE1: 2257 Features["sse"] = false; 2258 case SSE2: 2259 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2260 Features["sha"] = false; 2261 case SSE3: 2262 Features["sse3"] = false; 2263 setXOPLevel(Features, NoXOP, false); 2264 case SSSE3: 2265 Features["ssse3"] = false; 2266 case SSE41: 2267 Features["sse4.1"] = false; 2268 case SSE42: 2269 Features["sse4.2"] = false; 2270 case AVX: 2271 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2272 setXOPLevel(Features, FMA4, false); 2273 case AVX2: 2274 Features["avx2"] = false; 2275 case AVX512F: 2276 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2277 Features["avx512pf"] = false; 2278 } 2279 } 2280 2281 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2282 MMX3DNowEnum Level, bool Enabled) { 2283 if (Enabled) { 2284 switch (Level) { 2285 case AMD3DNowAthlon: 2286 Features["3dnowa"] = true; 2287 case AMD3DNow: 2288 Features["3dnow"] = true; 2289 case MMX: 2290 Features["mmx"] = true; 2291 case NoMMX3DNow: 2292 break; 2293 } 2294 return; 2295 } 2296 2297 switch (Level) { 2298 case NoMMX3DNow: 2299 case MMX: 2300 Features["mmx"] = false; 2301 case AMD3DNow: 2302 Features["3dnow"] = false; 2303 case AMD3DNowAthlon: 2304 Features["3dnowa"] = false; 2305 } 2306 } 2307 2308 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2309 bool Enabled) { 2310 if (Enabled) { 2311 switch (Level) { 2312 case XOP: 2313 Features["xop"] = true; 2314 case FMA4: 2315 Features["fma4"] = true; 2316 setSSELevel(Features, AVX, true); 2317 case SSE4A: 2318 Features["sse4a"] = true; 2319 setSSELevel(Features, SSE3, true); 2320 case NoXOP: 2321 break; 2322 } 2323 return; 2324 } 2325 2326 switch (Level) { 2327 case NoXOP: 2328 case SSE4A: 2329 Features["sse4a"] = false; 2330 case FMA4: 2331 Features["fma4"] = false; 2332 case XOP: 2333 Features["xop"] = false; 2334 } 2335 } 2336 2337 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2338 StringRef Name, bool Enabled) { 2339 // FIXME: This *really* should not be here. We need some way of translating 2340 // options into llvm subtarget features. 2341 if (Name == "sse4") 2342 Name = "sse4.2"; 2343 2344 Features[Name] = Enabled; 2345 2346 if (Name == "mmx") { 2347 setMMXLevel(Features, MMX, Enabled); 2348 } else if (Name == "sse") { 2349 setSSELevel(Features, SSE1, Enabled); 2350 } else if (Name == "sse2") { 2351 setSSELevel(Features, SSE2, Enabled); 2352 } else if (Name == "sse3") { 2353 setSSELevel(Features, SSE3, Enabled); 2354 } else if (Name == "ssse3") { 2355 setSSELevel(Features, SSSE3, Enabled); 2356 } else if (Name == "sse4.2") { 2357 setSSELevel(Features, SSE42, Enabled); 2358 } else if (Name == "sse4.1") { 2359 setSSELevel(Features, SSE41, Enabled); 2360 } else if (Name == "3dnow") { 2361 setMMXLevel(Features, AMD3DNow, Enabled); 2362 } else if (Name == "3dnowa") { 2363 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2364 } else if (Name == "aes") { 2365 if (Enabled) 2366 setSSELevel(Features, SSE2, Enabled); 2367 } else if (Name == "pclmul") { 2368 if (Enabled) 2369 setSSELevel(Features, SSE2, Enabled); 2370 } else if (Name == "avx") { 2371 setSSELevel(Features, AVX, Enabled); 2372 } else if (Name == "avx2") { 2373 setSSELevel(Features, AVX2, Enabled); 2374 } else if (Name == "avx512f") { 2375 setSSELevel(Features, AVX512F, Enabled); 2376 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf") { 2377 if (Enabled) 2378 setSSELevel(Features, AVX512F, Enabled); 2379 } else if (Name == "fma") { 2380 if (Enabled) 2381 setSSELevel(Features, AVX, Enabled); 2382 } else if (Name == "fma4") { 2383 setXOPLevel(Features, FMA4, Enabled); 2384 } else if (Name == "xop") { 2385 setXOPLevel(Features, XOP, Enabled); 2386 } else if (Name == "sse4a") { 2387 setXOPLevel(Features, SSE4A, Enabled); 2388 } else if (Name == "f16c") { 2389 if (Enabled) 2390 setSSELevel(Features, AVX, Enabled); 2391 } else if (Name == "sha") { 2392 if (Enabled) 2393 setSSELevel(Features, SSE2, Enabled); 2394 } 2395 } 2396 2397 /// handleTargetFeatures - Perform initialization based on the user 2398 /// configured set of features. 2399 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2400 DiagnosticsEngine &Diags) { 2401 // Remember the maximum enabled sselevel. 2402 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2403 // Ignore disabled features. 2404 if (Features[i][0] == '-') 2405 continue; 2406 2407 StringRef Feature = StringRef(Features[i]).substr(1); 2408 2409 if (Feature == "aes") { 2410 HasAES = true; 2411 continue; 2412 } 2413 2414 if (Feature == "pclmul") { 2415 HasPCLMUL = true; 2416 continue; 2417 } 2418 2419 if (Feature == "lzcnt") { 2420 HasLZCNT = true; 2421 continue; 2422 } 2423 2424 if (Feature == "rdrnd") { 2425 HasRDRND = true; 2426 continue; 2427 } 2428 2429 if (Feature == "bmi") { 2430 HasBMI = true; 2431 continue; 2432 } 2433 2434 if (Feature == "bmi2") { 2435 HasBMI2 = true; 2436 continue; 2437 } 2438 2439 if (Feature == "popcnt") { 2440 HasPOPCNT = true; 2441 continue; 2442 } 2443 2444 if (Feature == "rtm") { 2445 HasRTM = true; 2446 continue; 2447 } 2448 2449 if (Feature == "prfchw") { 2450 HasPRFCHW = true; 2451 continue; 2452 } 2453 2454 if (Feature == "rdseed") { 2455 HasRDSEED = true; 2456 continue; 2457 } 2458 2459 if (Feature == "tbm") { 2460 HasTBM = true; 2461 continue; 2462 } 2463 2464 if (Feature == "fma") { 2465 HasFMA = true; 2466 continue; 2467 } 2468 2469 if (Feature == "f16c") { 2470 HasF16C = true; 2471 continue; 2472 } 2473 2474 if (Feature == "avx512cd") { 2475 HasAVX512CD = true; 2476 continue; 2477 } 2478 2479 if (Feature == "avx512er") { 2480 HasAVX512ER = true; 2481 continue; 2482 } 2483 2484 if (Feature == "avx512pf") { 2485 HasAVX512PF = true; 2486 continue; 2487 } 2488 2489 if (Feature == "sha") { 2490 HasSHA = true; 2491 continue; 2492 } 2493 2494 if (Feature == "cx16") { 2495 HasCX16 = true; 2496 continue; 2497 } 2498 2499 assert(Features[i][0] == '+' && "Invalid target feature!"); 2500 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2501 .Case("avx512f", AVX512F) 2502 .Case("avx2", AVX2) 2503 .Case("avx", AVX) 2504 .Case("sse4.2", SSE42) 2505 .Case("sse4.1", SSE41) 2506 .Case("ssse3", SSSE3) 2507 .Case("sse3", SSE3) 2508 .Case("sse2", SSE2) 2509 .Case("sse", SSE1) 2510 .Default(NoSSE); 2511 SSELevel = std::max(SSELevel, Level); 2512 2513 MMX3DNowEnum ThreeDNowLevel = 2514 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2515 .Case("3dnowa", AMD3DNowAthlon) 2516 .Case("3dnow", AMD3DNow) 2517 .Case("mmx", MMX) 2518 .Default(NoMMX3DNow); 2519 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2520 2521 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2522 .Case("xop", XOP) 2523 .Case("fma4", FMA4) 2524 .Case("sse4a", SSE4A) 2525 .Default(NoXOP); 2526 XOPLevel = std::max(XOPLevel, XLevel); 2527 } 2528 2529 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2530 // Can't do this earlier because we need to be able to explicitly enable 2531 // popcnt and still disable sse4.2. 2532 if (!HasPOPCNT && SSELevel >= SSE42 && 2533 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2534 HasPOPCNT = true; 2535 Features.push_back("+popcnt"); 2536 } 2537 2538 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2539 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2540 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2541 HasPRFCHW = true; 2542 Features.push_back("+prfchw"); 2543 } 2544 2545 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2546 // matches the selected sse level. 2547 if (FPMath == FP_SSE && SSELevel < SSE1) { 2548 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2549 return false; 2550 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2551 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2552 return false; 2553 } 2554 2555 // Don't tell the backend if we're turning off mmx; it will end up disabling 2556 // SSE, which we don't want. 2557 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2558 // then enable MMX. 2559 std::vector<std::string>::iterator it; 2560 it = std::find(Features.begin(), Features.end(), "-mmx"); 2561 if (it != Features.end()) 2562 Features.erase(it); 2563 else if (SSELevel > NoSSE) 2564 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2565 return true; 2566 } 2567 2568 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2569 /// definitions for this particular subtarget. 2570 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2571 MacroBuilder &Builder) const { 2572 // Target identification. 2573 if (getTriple().getArch() == llvm::Triple::x86_64) { 2574 Builder.defineMacro("__amd64__"); 2575 Builder.defineMacro("__amd64"); 2576 Builder.defineMacro("__x86_64"); 2577 Builder.defineMacro("__x86_64__"); 2578 } else { 2579 DefineStd(Builder, "i386", Opts); 2580 } 2581 2582 // Subtarget options. 2583 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2584 // truly should be based on -mtune options. 2585 switch (CPU) { 2586 case CK_Generic: 2587 break; 2588 case CK_i386: 2589 // The rest are coming from the i386 define above. 2590 Builder.defineMacro("__tune_i386__"); 2591 break; 2592 case CK_i486: 2593 case CK_WinChipC6: 2594 case CK_WinChip2: 2595 case CK_C3: 2596 defineCPUMacros(Builder, "i486"); 2597 break; 2598 case CK_PentiumMMX: 2599 Builder.defineMacro("__pentium_mmx__"); 2600 Builder.defineMacro("__tune_pentium_mmx__"); 2601 // Fallthrough 2602 case CK_i586: 2603 case CK_Pentium: 2604 defineCPUMacros(Builder, "i586"); 2605 defineCPUMacros(Builder, "pentium"); 2606 break; 2607 case CK_Pentium3: 2608 case CK_Pentium3M: 2609 case CK_PentiumM: 2610 Builder.defineMacro("__tune_pentium3__"); 2611 // Fallthrough 2612 case CK_Pentium2: 2613 case CK_C3_2: 2614 Builder.defineMacro("__tune_pentium2__"); 2615 // Fallthrough 2616 case CK_PentiumPro: 2617 Builder.defineMacro("__tune_i686__"); 2618 Builder.defineMacro("__tune_pentiumpro__"); 2619 // Fallthrough 2620 case CK_i686: 2621 Builder.defineMacro("__i686"); 2622 Builder.defineMacro("__i686__"); 2623 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2624 Builder.defineMacro("__pentiumpro"); 2625 Builder.defineMacro("__pentiumpro__"); 2626 break; 2627 case CK_Pentium4: 2628 case CK_Pentium4M: 2629 defineCPUMacros(Builder, "pentium4"); 2630 break; 2631 case CK_Yonah: 2632 case CK_Prescott: 2633 case CK_Nocona: 2634 defineCPUMacros(Builder, "nocona"); 2635 break; 2636 case CK_Core2: 2637 case CK_Penryn: 2638 defineCPUMacros(Builder, "core2"); 2639 break; 2640 case CK_Atom: 2641 defineCPUMacros(Builder, "atom"); 2642 break; 2643 case CK_Silvermont: 2644 defineCPUMacros(Builder, "slm"); 2645 break; 2646 case CK_Corei7: 2647 case CK_Corei7AVX: 2648 case CK_CoreAVXi: 2649 case CK_CoreAVX2: 2650 defineCPUMacros(Builder, "corei7"); 2651 break; 2652 case CK_KNL: 2653 defineCPUMacros(Builder, "knl"); 2654 break; 2655 case CK_K6_2: 2656 Builder.defineMacro("__k6_2__"); 2657 Builder.defineMacro("__tune_k6_2__"); 2658 // Fallthrough 2659 case CK_K6_3: 2660 if (CPU != CK_K6_2) { // In case of fallthrough 2661 // FIXME: GCC may be enabling these in cases where some other k6 2662 // architecture is specified but -m3dnow is explicitly provided. The 2663 // exact semantics need to be determined and emulated here. 2664 Builder.defineMacro("__k6_3__"); 2665 Builder.defineMacro("__tune_k6_3__"); 2666 } 2667 // Fallthrough 2668 case CK_K6: 2669 defineCPUMacros(Builder, "k6"); 2670 break; 2671 case CK_Athlon: 2672 case CK_AthlonThunderbird: 2673 case CK_Athlon4: 2674 case CK_AthlonXP: 2675 case CK_AthlonMP: 2676 defineCPUMacros(Builder, "athlon"); 2677 if (SSELevel != NoSSE) { 2678 Builder.defineMacro("__athlon_sse__"); 2679 Builder.defineMacro("__tune_athlon_sse__"); 2680 } 2681 break; 2682 case CK_K8: 2683 case CK_K8SSE3: 2684 case CK_x86_64: 2685 case CK_Opteron: 2686 case CK_OpteronSSE3: 2687 case CK_Athlon64: 2688 case CK_Athlon64SSE3: 2689 case CK_AthlonFX: 2690 defineCPUMacros(Builder, "k8"); 2691 break; 2692 case CK_AMDFAM10: 2693 defineCPUMacros(Builder, "amdfam10"); 2694 break; 2695 case CK_BTVER1: 2696 defineCPUMacros(Builder, "btver1"); 2697 break; 2698 case CK_BTVER2: 2699 defineCPUMacros(Builder, "btver2"); 2700 break; 2701 case CK_BDVER1: 2702 defineCPUMacros(Builder, "bdver1"); 2703 break; 2704 case CK_BDVER2: 2705 defineCPUMacros(Builder, "bdver2"); 2706 break; 2707 case CK_BDVER3: 2708 defineCPUMacros(Builder, "bdver3"); 2709 break; 2710 case CK_BDVER4: 2711 defineCPUMacros(Builder, "bdver4"); 2712 break; 2713 case CK_Geode: 2714 defineCPUMacros(Builder, "geode"); 2715 break; 2716 } 2717 2718 // Target properties. 2719 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2720 2721 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2722 // functions in glibc header files that use FP Stack inline asm which the 2723 // backend can't deal with (PR879). 2724 Builder.defineMacro("__NO_MATH_INLINES"); 2725 2726 if (HasAES) 2727 Builder.defineMacro("__AES__"); 2728 2729 if (HasPCLMUL) 2730 Builder.defineMacro("__PCLMUL__"); 2731 2732 if (HasLZCNT) 2733 Builder.defineMacro("__LZCNT__"); 2734 2735 if (HasRDRND) 2736 Builder.defineMacro("__RDRND__"); 2737 2738 if (HasBMI) 2739 Builder.defineMacro("__BMI__"); 2740 2741 if (HasBMI2) 2742 Builder.defineMacro("__BMI2__"); 2743 2744 if (HasPOPCNT) 2745 Builder.defineMacro("__POPCNT__"); 2746 2747 if (HasRTM) 2748 Builder.defineMacro("__RTM__"); 2749 2750 if (HasPRFCHW) 2751 Builder.defineMacro("__PRFCHW__"); 2752 2753 if (HasRDSEED) 2754 Builder.defineMacro("__RDSEED__"); 2755 2756 if (HasTBM) 2757 Builder.defineMacro("__TBM__"); 2758 2759 switch (XOPLevel) { 2760 case XOP: 2761 Builder.defineMacro("__XOP__"); 2762 case FMA4: 2763 Builder.defineMacro("__FMA4__"); 2764 case SSE4A: 2765 Builder.defineMacro("__SSE4A__"); 2766 case NoXOP: 2767 break; 2768 } 2769 2770 if (HasFMA) 2771 Builder.defineMacro("__FMA__"); 2772 2773 if (HasF16C) 2774 Builder.defineMacro("__F16C__"); 2775 2776 if (HasAVX512CD) 2777 Builder.defineMacro("__AVX512CD__"); 2778 if (HasAVX512ER) 2779 Builder.defineMacro("__AVX512ER__"); 2780 if (HasAVX512PF) 2781 Builder.defineMacro("__AVX512PF__"); 2782 2783 if (HasSHA) 2784 Builder.defineMacro("__SHA__"); 2785 2786 if (HasCX16) 2787 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 2788 2789 // Each case falls through to the previous one here. 2790 switch (SSELevel) { 2791 case AVX512F: 2792 Builder.defineMacro("__AVX512F__"); 2793 case AVX2: 2794 Builder.defineMacro("__AVX2__"); 2795 case AVX: 2796 Builder.defineMacro("__AVX__"); 2797 case SSE42: 2798 Builder.defineMacro("__SSE4_2__"); 2799 case SSE41: 2800 Builder.defineMacro("__SSE4_1__"); 2801 case SSSE3: 2802 Builder.defineMacro("__SSSE3__"); 2803 case SSE3: 2804 Builder.defineMacro("__SSE3__"); 2805 case SSE2: 2806 Builder.defineMacro("__SSE2__"); 2807 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2808 case SSE1: 2809 Builder.defineMacro("__SSE__"); 2810 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2811 case NoSSE: 2812 break; 2813 } 2814 2815 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 2816 switch (SSELevel) { 2817 case AVX512F: 2818 case AVX2: 2819 case AVX: 2820 case SSE42: 2821 case SSE41: 2822 case SSSE3: 2823 case SSE3: 2824 case SSE2: 2825 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2826 break; 2827 case SSE1: 2828 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2829 break; 2830 default: 2831 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2832 } 2833 } 2834 2835 // Each case falls through to the previous one here. 2836 switch (MMX3DNowLevel) { 2837 case AMD3DNowAthlon: 2838 Builder.defineMacro("__3dNOW_A__"); 2839 case AMD3DNow: 2840 Builder.defineMacro("__3dNOW__"); 2841 case MMX: 2842 Builder.defineMacro("__MMX__"); 2843 case NoMMX3DNow: 2844 break; 2845 } 2846 2847 if (CPU >= CK_i486) { 2848 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 2849 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 2850 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 2851 } 2852 if (CPU >= CK_i586) 2853 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 2854 } 2855 2856 bool X86TargetInfo::hasFeature(StringRef Feature) const { 2857 return llvm::StringSwitch<bool>(Feature) 2858 .Case("aes", HasAES) 2859 .Case("avx", SSELevel >= AVX) 2860 .Case("avx2", SSELevel >= AVX2) 2861 .Case("avx512f", SSELevel >= AVX512F) 2862 .Case("avx512cd", HasAVX512CD) 2863 .Case("avx512er", HasAVX512ER) 2864 .Case("avx512pf", HasAVX512PF) 2865 .Case("bmi", HasBMI) 2866 .Case("bmi2", HasBMI2) 2867 .Case("cx16", HasCX16) 2868 .Case("f16c", HasF16C) 2869 .Case("fma", HasFMA) 2870 .Case("fma4", XOPLevel >= FMA4) 2871 .Case("tbm", HasTBM) 2872 .Case("lzcnt", HasLZCNT) 2873 .Case("rdrnd", HasRDRND) 2874 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 2875 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 2876 .Case("mmx", MMX3DNowLevel >= MMX) 2877 .Case("pclmul", HasPCLMUL) 2878 .Case("popcnt", HasPOPCNT) 2879 .Case("rtm", HasRTM) 2880 .Case("prfchw", HasPRFCHW) 2881 .Case("rdseed", HasRDSEED) 2882 .Case("sha", HasSHA) 2883 .Case("sse", SSELevel >= SSE1) 2884 .Case("sse2", SSELevel >= SSE2) 2885 .Case("sse3", SSELevel >= SSE3) 2886 .Case("ssse3", SSELevel >= SSSE3) 2887 .Case("sse4.1", SSELevel >= SSE41) 2888 .Case("sse4.2", SSELevel >= SSE42) 2889 .Case("sse4a", XOPLevel >= SSE4A) 2890 .Case("x86", true) 2891 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 2892 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 2893 .Case("xop", XOPLevel >= XOP) 2894 .Default(false); 2895 } 2896 2897 bool 2898 X86TargetInfo::validateAsmConstraint(const char *&Name, 2899 TargetInfo::ConstraintInfo &Info) const { 2900 switch (*Name) { 2901 default: return false; 2902 case 'Y': // first letter of a pair: 2903 switch (*(Name+1)) { 2904 default: return false; 2905 case '0': // First SSE register. 2906 case 't': // Any SSE register, when SSE2 is enabled. 2907 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 2908 case 'm': // any MMX register, when inter-unit moves enabled. 2909 break; // falls through to setAllowsRegister. 2910 } 2911 case 'a': // eax. 2912 case 'b': // ebx. 2913 case 'c': // ecx. 2914 case 'd': // edx. 2915 case 'S': // esi. 2916 case 'D': // edi. 2917 case 'A': // edx:eax. 2918 case 'f': // any x87 floating point stack register. 2919 case 't': // top of floating point stack. 2920 case 'u': // second from top of floating point stack. 2921 case 'q': // Any register accessible as [r]l: a, b, c, and d. 2922 case 'y': // Any MMX register. 2923 case 'x': // Any SSE register. 2924 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 2925 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 2926 case 'l': // "Index" registers: any general register that can be used as an 2927 // index in a base+index memory access. 2928 Info.setAllowsRegister(); 2929 return true; 2930 case 'C': // SSE floating point constant. 2931 case 'G': // x87 floating point constant. 2932 case 'e': // 32-bit signed integer constant for use with zero-extending 2933 // x86_64 instructions. 2934 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 2935 // x86_64 instructions. 2936 return true; 2937 } 2938 } 2939 2940 2941 std::string 2942 X86TargetInfo::convertConstraint(const char *&Constraint) const { 2943 switch (*Constraint) { 2944 case 'a': return std::string("{ax}"); 2945 case 'b': return std::string("{bx}"); 2946 case 'c': return std::string("{cx}"); 2947 case 'd': return std::string("{dx}"); 2948 case 'S': return std::string("{si}"); 2949 case 'D': return std::string("{di}"); 2950 case 'p': // address 2951 return std::string("im"); 2952 case 't': // top of floating point stack. 2953 return std::string("{st}"); 2954 case 'u': // second from top of floating point stack. 2955 return std::string("{st(1)}"); // second from top of floating point stack. 2956 default: 2957 return std::string(1, *Constraint); 2958 } 2959 } 2960 } // end anonymous namespace 2961 2962 namespace { 2963 // X86-32 generic target 2964 class X86_32TargetInfo : public X86TargetInfo { 2965 public: 2966 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 2967 DoubleAlign = LongLongAlign = 32; 2968 LongDoubleWidth = 96; 2969 LongDoubleAlign = 32; 2970 SuitableAlign = 128; 2971 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 2972 SizeType = UnsignedInt; 2973 PtrDiffType = SignedInt; 2974 IntPtrType = SignedInt; 2975 RegParmMax = 3; 2976 2977 // Use fpret for all types. 2978 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 2979 (1 << TargetInfo::Double) | 2980 (1 << TargetInfo::LongDouble)); 2981 2982 // x86-32 has atomics up to 8 bytes 2983 // FIXME: Check that we actually have cmpxchg8b before setting 2984 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 2985 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 2986 } 2987 BuiltinVaListKind getBuiltinVaListKind() const override { 2988 return TargetInfo::CharPtrBuiltinVaList; 2989 } 2990 2991 int getEHDataRegisterNumber(unsigned RegNo) const override { 2992 if (RegNo == 0) return 0; 2993 if (RegNo == 1) return 2; 2994 return -1; 2995 } 2996 bool validateInputSize(StringRef Constraint, 2997 unsigned Size) const override { 2998 switch (Constraint[0]) { 2999 default: break; 3000 case 'a': 3001 case 'b': 3002 case 'c': 3003 case 'd': 3004 return Size <= 32; 3005 } 3006 3007 return true; 3008 } 3009 }; 3010 } // end anonymous namespace 3011 3012 namespace { 3013 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3014 public: 3015 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3016 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3017 3018 unsigned getFloatEvalMethod() const override { 3019 unsigned Major, Minor, Micro; 3020 getTriple().getOSVersion(Major, Minor, Micro); 3021 // New NetBSD uses the default rounding mode. 3022 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3023 return X86_32TargetInfo::getFloatEvalMethod(); 3024 // NetBSD before 6.99.26 defaults to "double" rounding. 3025 return 1; 3026 } 3027 }; 3028 } // end anonymous namespace 3029 3030 namespace { 3031 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3032 public: 3033 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3034 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3035 SizeType = UnsignedLong; 3036 IntPtrType = SignedLong; 3037 PtrDiffType = SignedLong; 3038 } 3039 }; 3040 } // end anonymous namespace 3041 3042 namespace { 3043 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3044 public: 3045 BitrigI386TargetInfo(const llvm::Triple &Triple) 3046 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3047 SizeType = UnsignedLong; 3048 IntPtrType = SignedLong; 3049 PtrDiffType = SignedLong; 3050 } 3051 }; 3052 } // end anonymous namespace 3053 3054 namespace { 3055 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3056 public: 3057 DarwinI386TargetInfo(const llvm::Triple &Triple) 3058 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3059 LongDoubleWidth = 128; 3060 LongDoubleAlign = 128; 3061 SuitableAlign = 128; 3062 MaxVectorAlign = 256; 3063 SizeType = UnsignedLong; 3064 IntPtrType = SignedLong; 3065 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3066 HasAlignMac68kSupport = true; 3067 } 3068 3069 }; 3070 } // end anonymous namespace 3071 3072 namespace { 3073 // x86-32 Windows target 3074 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3075 public: 3076 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3077 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3078 WCharType = UnsignedShort; 3079 DoubleAlign = LongLongAlign = 64; 3080 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3081 } 3082 void getTargetDefines(const LangOptions &Opts, 3083 MacroBuilder &Builder) const override { 3084 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3085 } 3086 }; 3087 } // end anonymous namespace 3088 3089 namespace { 3090 3091 // x86-32 Windows Visual Studio target 3092 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3093 public: 3094 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3095 : WindowsX86_32TargetInfo(Triple) { 3096 LongDoubleWidth = LongDoubleAlign = 64; 3097 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3098 } 3099 void getTargetDefines(const LangOptions &Opts, 3100 MacroBuilder &Builder) const override { 3101 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3102 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3103 // The value of the following reflects processor type. 3104 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3105 // We lost the original triple, so we use the default. 3106 Builder.defineMacro("_M_IX86", "600"); 3107 } 3108 }; 3109 } // end anonymous namespace 3110 3111 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3112 Builder.defineMacro("__MSVCRT__"); 3113 Builder.defineMacro("__MINGW32__"); 3114 3115 // Mingw defines __declspec(a) to __attribute__((a)). Clang supports 3116 // __declspec natively under -fms-extensions, but we define a no-op __declspec 3117 // macro anyway for pre-processor compatibility. 3118 if (Opts.MicrosoftExt) 3119 Builder.defineMacro("__declspec", "__declspec"); 3120 else 3121 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3122 3123 if (!Opts.MicrosoftExt) { 3124 // Provide macros for all the calling convention keywords. Provide both 3125 // single and double underscore prefixed variants. These are available on 3126 // x64 as well as x86, even though they have no effect. 3127 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3128 for (const char *CC : CCs) { 3129 std::string GCCSpelling = "__attribute__((__"; 3130 GCCSpelling += CC; 3131 GCCSpelling += "__))"; 3132 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3133 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3134 } 3135 } 3136 } 3137 3138 namespace { 3139 // x86-32 MinGW target 3140 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3141 public: 3142 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3143 : WindowsX86_32TargetInfo(Triple) {} 3144 void getTargetDefines(const LangOptions &Opts, 3145 MacroBuilder &Builder) const override { 3146 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3147 DefineStd(Builder, "WIN32", Opts); 3148 DefineStd(Builder, "WINNT", Opts); 3149 Builder.defineMacro("_X86_"); 3150 addMinGWDefines(Opts, Builder); 3151 } 3152 }; 3153 } // end anonymous namespace 3154 3155 namespace { 3156 // x86-32 Cygwin target 3157 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3158 public: 3159 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3160 : X86_32TargetInfo(Triple) { 3161 TLSSupported = false; 3162 WCharType = UnsignedShort; 3163 DoubleAlign = LongLongAlign = 64; 3164 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3165 } 3166 void getTargetDefines(const LangOptions &Opts, 3167 MacroBuilder &Builder) const override { 3168 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3169 Builder.defineMacro("_X86_"); 3170 Builder.defineMacro("__CYGWIN__"); 3171 Builder.defineMacro("__CYGWIN32__"); 3172 DefineStd(Builder, "unix", Opts); 3173 if (Opts.CPlusPlus) 3174 Builder.defineMacro("_GNU_SOURCE"); 3175 } 3176 }; 3177 } // end anonymous namespace 3178 3179 namespace { 3180 // x86-32 Haiku target 3181 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3182 public: 3183 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3184 SizeType = UnsignedLong; 3185 IntPtrType = SignedLong; 3186 PtrDiffType = SignedLong; 3187 ProcessIDType = SignedLong; 3188 this->UserLabelPrefix = ""; 3189 this->TLSSupported = false; 3190 } 3191 void getTargetDefines(const LangOptions &Opts, 3192 MacroBuilder &Builder) const override { 3193 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3194 Builder.defineMacro("__INTEL__"); 3195 Builder.defineMacro("__HAIKU__"); 3196 } 3197 }; 3198 } // end anonymous namespace 3199 3200 // RTEMS Target 3201 template<typename Target> 3202 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3203 protected: 3204 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3205 MacroBuilder &Builder) const override { 3206 // RTEMS defines; list based off of gcc output 3207 3208 Builder.defineMacro("__rtems__"); 3209 Builder.defineMacro("__ELF__"); 3210 } 3211 3212 public: 3213 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3214 this->UserLabelPrefix = ""; 3215 3216 switch (Triple.getArch()) { 3217 default: 3218 case llvm::Triple::x86: 3219 // this->MCountName = ".mcount"; 3220 break; 3221 case llvm::Triple::mips: 3222 case llvm::Triple::mipsel: 3223 case llvm::Triple::ppc: 3224 case llvm::Triple::ppc64: 3225 case llvm::Triple::ppc64le: 3226 // this->MCountName = "_mcount"; 3227 break; 3228 case llvm::Triple::arm: 3229 // this->MCountName = "__mcount"; 3230 break; 3231 } 3232 } 3233 }; 3234 3235 namespace { 3236 // x86-32 RTEMS target 3237 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3238 public: 3239 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3240 SizeType = UnsignedLong; 3241 IntPtrType = SignedLong; 3242 PtrDiffType = SignedLong; 3243 this->UserLabelPrefix = ""; 3244 } 3245 void getTargetDefines(const LangOptions &Opts, 3246 MacroBuilder &Builder) const override { 3247 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3248 Builder.defineMacro("__INTEL__"); 3249 Builder.defineMacro("__rtems__"); 3250 } 3251 }; 3252 } // end anonymous namespace 3253 3254 namespace { 3255 // x86-64 generic target 3256 class X86_64TargetInfo : public X86TargetInfo { 3257 public: 3258 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3259 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 3260 LongDoubleWidth = 128; 3261 LongDoubleAlign = 128; 3262 LargeArrayMinWidth = 128; 3263 LargeArrayAlign = 128; 3264 SuitableAlign = 128; 3265 IntMaxType = SignedLong; 3266 UIntMaxType = UnsignedLong; 3267 Int64Type = SignedLong; 3268 RegParmMax = 6; 3269 3270 DescriptionString = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3271 3272 // Use fpret only for long double. 3273 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3274 3275 // Use fp2ret for _Complex long double. 3276 ComplexLongDoubleUsesFP2Ret = true; 3277 3278 // x86-64 has atomics up to 16 bytes. 3279 // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128 3280 // on CPUs with cmpxchg16b 3281 MaxAtomicPromoteWidth = 128; 3282 MaxAtomicInlineWidth = 64; 3283 } 3284 BuiltinVaListKind getBuiltinVaListKind() const override { 3285 return TargetInfo::X86_64ABIBuiltinVaList; 3286 } 3287 3288 int getEHDataRegisterNumber(unsigned RegNo) const override { 3289 if (RegNo == 0) return 0; 3290 if (RegNo == 1) return 1; 3291 return -1; 3292 } 3293 3294 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3295 return (CC == CC_C || 3296 CC == CC_IntelOclBicc || 3297 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3298 } 3299 3300 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3301 return CC_C; 3302 } 3303 3304 }; 3305 } // end anonymous namespace 3306 3307 namespace { 3308 // x86-64 Windows target 3309 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3310 public: 3311 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3312 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3313 WCharType = UnsignedShort; 3314 LongWidth = LongAlign = 32; 3315 DoubleAlign = LongLongAlign = 64; 3316 IntMaxType = SignedLongLong; 3317 UIntMaxType = UnsignedLongLong; 3318 Int64Type = SignedLongLong; 3319 SizeType = UnsignedLongLong; 3320 PtrDiffType = SignedLongLong; 3321 IntPtrType = SignedLongLong; 3322 this->UserLabelPrefix = ""; 3323 } 3324 void getTargetDefines(const LangOptions &Opts, 3325 MacroBuilder &Builder) const override { 3326 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3327 Builder.defineMacro("_WIN64"); 3328 } 3329 BuiltinVaListKind getBuiltinVaListKind() const override { 3330 return TargetInfo::CharPtrBuiltinVaList; 3331 } 3332 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3333 return (CC == CC_C || 3334 CC == CC_IntelOclBicc || 3335 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning; 3336 } 3337 }; 3338 } // end anonymous namespace 3339 3340 namespace { 3341 // x86-64 Windows Visual Studio target 3342 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 3343 public: 3344 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 3345 : WindowsX86_64TargetInfo(Triple) { 3346 LongDoubleWidth = LongDoubleAlign = 64; 3347 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3348 } 3349 void getTargetDefines(const LangOptions &Opts, 3350 MacroBuilder &Builder) const override { 3351 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3352 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3353 Builder.defineMacro("_M_X64"); 3354 Builder.defineMacro("_M_AMD64"); 3355 } 3356 }; 3357 } // end anonymous namespace 3358 3359 namespace { 3360 // x86-64 MinGW target 3361 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3362 public: 3363 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3364 : WindowsX86_64TargetInfo(Triple) {} 3365 void getTargetDefines(const LangOptions &Opts, 3366 MacroBuilder &Builder) const override { 3367 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3368 DefineStd(Builder, "WIN64", Opts); 3369 Builder.defineMacro("__MINGW64__"); 3370 addMinGWDefines(Opts, Builder); 3371 } 3372 }; 3373 } // end anonymous namespace 3374 3375 namespace { 3376 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3377 public: 3378 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3379 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3380 Int64Type = SignedLongLong; 3381 MaxVectorAlign = 256; 3382 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 3383 llvm::Triple T = llvm::Triple(Triple); 3384 if (T.getOS() == llvm::Triple::IOS) 3385 UseSignedCharForObjCBool = false; 3386 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 3387 } 3388 }; 3389 } // end anonymous namespace 3390 3391 namespace { 3392 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3393 public: 3394 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3395 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3396 IntMaxType = SignedLongLong; 3397 UIntMaxType = UnsignedLongLong; 3398 Int64Type = SignedLongLong; 3399 } 3400 }; 3401 } // end anonymous namespace 3402 3403 namespace { 3404 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3405 public: 3406 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3407 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3408 IntMaxType = SignedLongLong; 3409 UIntMaxType = UnsignedLongLong; 3410 Int64Type = SignedLongLong; 3411 } 3412 }; 3413 } 3414 3415 3416 namespace { 3417 class ARMTargetInfo : public TargetInfo { 3418 // Possible FPU choices. 3419 enum FPUMode { 3420 VFP2FPU = (1 << 0), 3421 VFP3FPU = (1 << 1), 3422 VFP4FPU = (1 << 2), 3423 NeonFPU = (1 << 3), 3424 FPARMV8 = (1 << 4) 3425 }; 3426 3427 // Possible HWDiv features. 3428 enum HWDivMode { 3429 HWDivThumb = (1 << 0), 3430 HWDivARM = (1 << 1) 3431 }; 3432 3433 static bool FPUModeIsVFP(FPUMode Mode) { 3434 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 3435 } 3436 3437 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3438 static const char * const GCCRegNames[]; 3439 3440 std::string ABI, CPU; 3441 3442 enum { 3443 FP_Default, 3444 FP_VFP, 3445 FP_Neon 3446 } FPMath; 3447 3448 unsigned FPU : 5; 3449 3450 unsigned IsAAPCS : 1; 3451 unsigned IsThumb : 1; 3452 unsigned HWDiv : 2; 3453 3454 // Initialized via features. 3455 unsigned SoftFloat : 1; 3456 unsigned SoftFloatABI : 1; 3457 3458 unsigned CRC : 1; 3459 unsigned Crypto : 1; 3460 3461 static const Builtin::Info BuiltinInfo[]; 3462 3463 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3464 if (T.isOSWindows()) 3465 return true; 3466 3467 // On linux, binaries targeting old cpus call functions in libgcc to 3468 // perform atomic operations. The implementation in libgcc then calls into 3469 // the kernel which on armv6 and newer uses ldrex and strex. The net result 3470 // is that if we assume the kernel is at least as recent as the hardware, 3471 // it is safe to use atomic instructions on armv6 and newer. 3472 if (!T.isOSLinux() && 3473 T.getOS() != llvm::Triple::FreeBSD && 3474 T.getOS() != llvm::Triple::NetBSD && 3475 T.getOS() != llvm::Triple::Bitrig) 3476 return false; 3477 StringRef ArchName = T.getArchName(); 3478 if (T.getArch() == llvm::Triple::arm || 3479 T.getArch() == llvm::Triple::armeb) { 3480 StringRef VersionStr; 3481 if (ArchName.startswith("armv")) 3482 VersionStr = ArchName.substr(4); 3483 else if (ArchName.startswith("armebv")) 3484 VersionStr = ArchName.substr(6); 3485 else 3486 return false; 3487 unsigned Version; 3488 if (VersionStr.getAsInteger(10, Version)) 3489 return false; 3490 return Version >= 6; 3491 } 3492 assert(T.getArch() == llvm::Triple::thumb || 3493 T.getArch() == llvm::Triple::thumbeb); 3494 StringRef VersionStr; 3495 if (ArchName.startswith("thumbv")) 3496 VersionStr = ArchName.substr(6); 3497 else if (ArchName.startswith("thumbebv")) 3498 VersionStr = ArchName.substr(8); 3499 else 3500 return false; 3501 unsigned Version; 3502 if (VersionStr.getAsInteger(10, Version)) 3503 return false; 3504 return Version >= 7; 3505 } 3506 3507 void setABIAAPCS() { 3508 IsAAPCS = true; 3509 3510 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 3511 const llvm::Triple &T = getTriple(); 3512 3513 // size_t is unsigned long on Darwin and NetBSD. 3514 if (T.isOSDarwin() || T.getOS() == llvm::Triple::NetBSD) 3515 SizeType = UnsignedLong; 3516 else 3517 SizeType = UnsignedInt; 3518 3519 switch (T.getOS()) { 3520 case llvm::Triple::NetBSD: 3521 WCharType = SignedInt; 3522 break; 3523 case llvm::Triple::Win32: 3524 WCharType = UnsignedShort; 3525 break; 3526 case llvm::Triple::Linux: 3527 default: 3528 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3529 WCharType = UnsignedInt; 3530 break; 3531 } 3532 3533 UseBitFieldTypeAlignment = true; 3534 3535 ZeroLengthBitfieldBoundary = 0; 3536 3537 if (IsThumb) { 3538 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3539 // so set preferred for small types to 32. 3540 if (T.isOSBinFormatMachO()) { 3541 DescriptionString = BigEndian ? 3542 "E-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3543 "v128:64:128-a:0:32-n32-S64" : 3544 "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3545 "v128:64:128-a:0:32-n32-S64"; 3546 } else if (T.isOSWindows()) { 3547 // FIXME: this is invalid for WindowsCE 3548 assert(!BigEndian && "Windows on ARM does not support big endian"); 3549 DescriptionString = "e" 3550 "-m:e" 3551 "-p:32:32" 3552 "-i1:8:32-i8:8:32-i16:16:32-i64:64" 3553 "-v128:64:128" 3554 "-a:0:32" 3555 "-n32" 3556 "-S64"; 3557 } else { 3558 DescriptionString = BigEndian ? 3559 "E-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3560 "v128:64:128-a:0:32-n32-S64" : 3561 "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3562 "v128:64:128-a:0:32-n32-S64"; 3563 } 3564 } else { 3565 if (T.isOSBinFormatMachO()) 3566 DescriptionString = BigEndian ? 3567 "E-m:o-p:32:32-i64:64-v128:64:128-n32-S64" : 3568 "e-m:o-p:32:32-i64:64-v128:64:128-n32-S64"; 3569 else 3570 DescriptionString = BigEndian ? 3571 "E-m:e-p:32:32-i64:64-v128:64:128-n32-S64" : 3572 "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64"; 3573 } 3574 3575 // FIXME: Enumerated types are variable width in straight AAPCS. 3576 } 3577 3578 void setABIAPCS() { 3579 const llvm::Triple &T = getTriple(); 3580 3581 IsAAPCS = false; 3582 3583 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 3584 3585 // size_t is unsigned int on FreeBSD. 3586 if (T.getOS() == llvm::Triple::FreeBSD) 3587 SizeType = UnsignedInt; 3588 else 3589 SizeType = UnsignedLong; 3590 3591 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 3592 WCharType = SignedInt; 3593 3594 // Do not respect the alignment of bit-field types when laying out 3595 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 3596 UseBitFieldTypeAlignment = false; 3597 3598 /// gcc forces the alignment to 4 bytes, regardless of the type of the 3599 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 3600 /// gcc. 3601 ZeroLengthBitfieldBoundary = 32; 3602 3603 if (IsThumb) { 3604 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3605 // so set preferred for small types to 32. 3606 if (T.isOSBinFormatMachO()) 3607 DescriptionString = BigEndian ? 3608 "E-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3609 "-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3610 "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3611 "-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3612 else 3613 DescriptionString = BigEndian ? 3614 "E-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3615 "-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3616 "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3617 "-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3618 } else { 3619 if (T.isOSBinFormatMachO()) 3620 DescriptionString = BigEndian ? 3621 "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3622 "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3623 else 3624 DescriptionString = BigEndian ? 3625 "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3626 "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3627 } 3628 3629 // FIXME: Override "preferred align" for double and long long. 3630 } 3631 3632 public: 3633 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 3634 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 3635 IsAAPCS(true) { 3636 BigEndian = IsBigEndian; 3637 3638 switch (getTriple().getOS()) { 3639 case llvm::Triple::NetBSD: 3640 PtrDiffType = SignedLong; 3641 break; 3642 default: 3643 PtrDiffType = SignedInt; 3644 break; 3645 } 3646 3647 // {} in inline assembly are neon specifiers, not assembly variant 3648 // specifiers. 3649 NoAsmVariants = true; 3650 3651 // FIXME: Should we just treat this as a feature? 3652 IsThumb = getTriple().getArchName().startswith("thumb"); 3653 3654 setABI("aapcs-linux"); 3655 3656 // ARM targets default to using the ARM C++ ABI. 3657 TheCXXABI.set(TargetCXXABI::GenericARM); 3658 3659 // ARM has atomics up to 8 bytes 3660 MaxAtomicPromoteWidth = 64; 3661 if (shouldUseInlineAtomic(getTriple())) 3662 MaxAtomicInlineWidth = 64; 3663 3664 // Do force alignment of members that follow zero length bitfields. If 3665 // the alignment of the zero-length bitfield is greater than the member 3666 // that follows it, `bar', `bar' will be aligned as the type of the 3667 // zero length bitfield. 3668 UseZeroLengthBitfieldAlignment = true; 3669 } 3670 StringRef getABI() const override { return ABI; } 3671 bool setABI(const std::string &Name) override { 3672 ABI = Name; 3673 3674 // The defaults (above) are for AAPCS, check if we need to change them. 3675 // 3676 // FIXME: We need support for -meabi... we could just mangle it into the 3677 // name. 3678 if (Name == "apcs-gnu") { 3679 setABIAPCS(); 3680 return true; 3681 } 3682 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 3683 setABIAAPCS(); 3684 return true; 3685 } 3686 return false; 3687 } 3688 3689 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 3690 if (IsAAPCS) 3691 Features["aapcs"] = true; 3692 else 3693 Features["apcs"] = true; 3694 3695 StringRef ArchName = getTriple().getArchName(); 3696 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 3697 Features["vfp2"] = true; 3698 else if (CPU == "cortex-a8" || CPU == "cortex-a9" || 3699 CPU == "cortex-a9-mp") { 3700 Features["vfp3"] = true; 3701 Features["neon"] = true; 3702 } 3703 else if (CPU == "cortex-a5") { 3704 Features["vfp4"] = true; 3705 Features["neon"] = true; 3706 } else if (CPU == "swift" || CPU == "cortex-a7" || 3707 CPU == "cortex-a12" || CPU == "cortex-a15" || 3708 CPU == "krait") { 3709 Features["vfp4"] = true; 3710 Features["neon"] = true; 3711 Features["hwdiv"] = true; 3712 Features["hwdiv-arm"] = true; 3713 } else if (CPU == "cyclone") { 3714 Features["v8fp"] = true; 3715 Features["neon"] = true; 3716 Features["hwdiv"] = true; 3717 Features["hwdiv-arm"] = true; 3718 } else if (CPU == "cortex-a53" || CPU == "cortex-a57") { 3719 Features["fp-armv8"] = true; 3720 Features["neon"] = true; 3721 Features["hwdiv"] = true; 3722 Features["hwdiv-arm"] = true; 3723 Features["crc"] = true; 3724 Features["crypto"] = true; 3725 } else if (CPU == "cortex-r5" || 3726 // Enable the hwdiv extension for all v8a AArch32 cores by 3727 // default. 3728 ArchName == "armv8a" || ArchName == "armv8" || 3729 ArchName == "armebv8a" || ArchName == "armebv8" || 3730 ArchName == "thumbv8a" || ArchName == "thumbv8" || 3731 ArchName == "thumbebv8a" || ArchName == "thumbebv8") { 3732 Features["hwdiv"] = true; 3733 Features["hwdiv-arm"] = true; 3734 } else if (CPU == "cortex-m3" || CPU == "cortex-m4") { 3735 Features["hwdiv"] = true; 3736 } 3737 } 3738 3739 bool handleTargetFeatures(std::vector<std::string> &Features, 3740 DiagnosticsEngine &Diags) override { 3741 FPU = 0; 3742 CRC = 0; 3743 Crypto = 0; 3744 SoftFloat = SoftFloatABI = false; 3745 HWDiv = 0; 3746 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3747 if (Features[i] == "+soft-float") 3748 SoftFloat = true; 3749 else if (Features[i] == "+soft-float-abi") 3750 SoftFloatABI = true; 3751 else if (Features[i] == "+vfp2") 3752 FPU |= VFP2FPU; 3753 else if (Features[i] == "+vfp3") 3754 FPU |= VFP3FPU; 3755 else if (Features[i] == "+vfp4") 3756 FPU |= VFP4FPU; 3757 else if (Features[i] == "+fp-armv8") 3758 FPU |= FPARMV8; 3759 else if (Features[i] == "+neon") 3760 FPU |= NeonFPU; 3761 else if (Features[i] == "+hwdiv") 3762 HWDiv |= HWDivThumb; 3763 else if (Features[i] == "+hwdiv-arm") 3764 HWDiv |= HWDivARM; 3765 else if (Features[i] == "+crc") 3766 CRC = 1; 3767 else if (Features[i] == "+crypto") 3768 Crypto = 1; 3769 } 3770 3771 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 3772 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 3773 return false; 3774 } 3775 3776 if (FPMath == FP_Neon) 3777 Features.push_back("+neonfp"); 3778 else if (FPMath == FP_VFP) 3779 Features.push_back("-neonfp"); 3780 3781 // Remove front-end specific options which the backend handles differently. 3782 std::vector<std::string>::iterator it; 3783 it = std::find(Features.begin(), Features.end(), "+soft-float"); 3784 if (it != Features.end()) 3785 Features.erase(it); 3786 it = std::find(Features.begin(), Features.end(), "+soft-float-abi"); 3787 if (it != Features.end()) 3788 Features.erase(it); 3789 return true; 3790 } 3791 3792 bool hasFeature(StringRef Feature) const override { 3793 return llvm::StringSwitch<bool>(Feature) 3794 .Case("arm", true) 3795 .Case("softfloat", SoftFloat) 3796 .Case("thumb", IsThumb) 3797 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 3798 .Case("hwdiv", HWDiv & HWDivThumb) 3799 .Case("hwdiv-arm", HWDiv & HWDivARM) 3800 .Default(false); 3801 } 3802 // FIXME: Should we actually have some table instead of these switches? 3803 static const char *getCPUDefineSuffix(StringRef Name) { 3804 return llvm::StringSwitch<const char*>(Name) 3805 .Cases("arm8", "arm810", "4") 3806 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") 3807 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 3808 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 3809 .Case("ep9312", "4T") 3810 .Cases("arm10tdmi", "arm1020t", "5T") 3811 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 3812 .Case("arm926ej-s", "5TEJ") 3813 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 3814 .Cases("xscale", "iwmmxt", "5TE") 3815 .Case("arm1136j-s", "6J") 3816 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 3817 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 3818 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 3819 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "cortex-a9-mp", "7A") 3820 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "7A") 3821 .Cases("cortex-r4", "cortex-r5", "7R") 3822 .Case("swift", "7S") 3823 .Case("cyclone", "8A") 3824 .Cases("cortex-m3", "cortex-m4", "7M") 3825 .Case("cortex-m0", "6M") 3826 .Cases("cortex-a53", "cortex-a57", "8A") 3827 .Default(nullptr); 3828 } 3829 static const char *getCPUProfile(StringRef Name) { 3830 return llvm::StringSwitch<const char*>(Name) 3831 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A") 3832 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "A") 3833 .Cases("cortex-a53", "cortex-a57", "A") 3834 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M") 3835 .Cases("cortex-r4", "cortex-r5", "R") 3836 .Default(""); 3837 } 3838 bool setCPU(const std::string &Name) override { 3839 if (!getCPUDefineSuffix(Name)) 3840 return false; 3841 3842 CPU = Name; 3843 return true; 3844 } 3845 bool setFPMath(StringRef Name) override; 3846 bool supportsThumb(StringRef ArchName, StringRef CPUArch, 3847 unsigned CPUArchVer) const { 3848 return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) || 3849 (CPUArch.find('M') != StringRef::npos); 3850 } 3851 bool supportsThumb2(StringRef ArchName, StringRef CPUArch, 3852 unsigned CPUArchVer) const { 3853 // We check both CPUArchVer and ArchName because when only triple is 3854 // specified, the default CPU is arm1136j-s. 3855 return ArchName.endswith("v6t2") || ArchName.endswith("v7") || 3856 ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7; 3857 } 3858 void getTargetDefines(const LangOptions &Opts, 3859 MacroBuilder &Builder) const override { 3860 // Target identification. 3861 Builder.defineMacro("__arm"); 3862 Builder.defineMacro("__arm__"); 3863 3864 // Target properties. 3865 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3866 3867 StringRef CPUArch = getCPUDefineSuffix(CPU); 3868 unsigned int CPUArchVer; 3869 if(CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) { 3870 llvm_unreachable("Invalid char for architecture version number"); 3871 } 3872 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 3873 3874 // ACLE 6.4.1 ARM/Thumb instruction set architecture 3875 StringRef CPUProfile = getCPUProfile(CPU); 3876 StringRef ArchName = getTriple().getArchName(); 3877 3878 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 3879 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 3880 3881 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 3882 // is not defined for the M-profile. 3883 // NOTE that the deffault profile is assumed to be 'A' 3884 if (CPUProfile.empty() || CPUProfile != "M") 3885 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 3886 3887 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 3888 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 3889 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 3890 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 3891 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 3892 else if (supportsThumb(ArchName, CPUArch, CPUArchVer)) 3893 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 3894 3895 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 3896 // instruction set such as ARM or Thumb. 3897 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 3898 3899 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 3900 3901 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 3902 if (!CPUProfile.empty()) 3903 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 3904 3905 // Subtarget options. 3906 3907 // FIXME: It's more complicated than this and we don't really support 3908 // interworking. 3909 // Windows on ARM does not "support" interworking 3910 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows()) 3911 Builder.defineMacro("__THUMB_INTERWORK__"); 3912 3913 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 3914 // Embedded targets on Darwin follow AAPCS, but not EABI. 3915 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 3916 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 3917 Builder.defineMacro("__ARM_EABI__"); 3918 Builder.defineMacro("__ARM_PCS", "1"); 3919 3920 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 3921 Builder.defineMacro("__ARM_PCS_VFP", "1"); 3922 } 3923 3924 if (SoftFloat) 3925 Builder.defineMacro("__SOFTFP__"); 3926 3927 if (CPU == "xscale") 3928 Builder.defineMacro("__XSCALE__"); 3929 3930 if (IsThumb) { 3931 Builder.defineMacro("__THUMBEL__"); 3932 Builder.defineMacro("__thumb__"); 3933 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 3934 Builder.defineMacro("__thumb2__"); 3935 } 3936 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 3937 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 3938 3939 // Note, this is always on in gcc, even though it doesn't make sense. 3940 Builder.defineMacro("__APCS_32__"); 3941 3942 if (FPUModeIsVFP((FPUMode) FPU)) { 3943 Builder.defineMacro("__VFP_FP__"); 3944 if (FPU & VFP2FPU) 3945 Builder.defineMacro("__ARM_VFPV2__"); 3946 if (FPU & VFP3FPU) 3947 Builder.defineMacro("__ARM_VFPV3__"); 3948 if (FPU & VFP4FPU) 3949 Builder.defineMacro("__ARM_VFPV4__"); 3950 } 3951 3952 // This only gets set when Neon instructions are actually available, unlike 3953 // the VFP define, hence the soft float and arch check. This is subtly 3954 // different from gcc, we follow the intent which was that it should be set 3955 // when Neon instructions are actually available. 3956 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) { 3957 Builder.defineMacro("__ARM_NEON"); 3958 Builder.defineMacro("__ARM_NEON__"); 3959 } 3960 3961 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 3962 Opts.ShortWChar ? "2" : "4"); 3963 3964 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 3965 Opts.ShortEnums ? "1" : "4"); 3966 3967 if (CRC) 3968 Builder.defineMacro("__ARM_FEATURE_CRC32"); 3969 3970 if (Crypto) 3971 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 3972 3973 if (CPUArchVer >= 6 && CPUArch != "6M") { 3974 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3975 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3976 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3977 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3978 } 3979 } 3980 void getTargetBuiltins(const Builtin::Info *&Records, 3981 unsigned &NumRecords) const override { 3982 Records = BuiltinInfo; 3983 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 3984 } 3985 bool isCLZForZeroUndef() const override { return false; } 3986 BuiltinVaListKind getBuiltinVaListKind() const override { 3987 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 3988 } 3989 void getGCCRegNames(const char * const *&Names, 3990 unsigned &NumNames) const override; 3991 void getGCCRegAliases(const GCCRegAlias *&Aliases, 3992 unsigned &NumAliases) const override; 3993 bool validateAsmConstraint(const char *&Name, 3994 TargetInfo::ConstraintInfo &Info) const override { 3995 switch (*Name) { 3996 default: break; 3997 case 'l': // r0-r7 3998 case 'h': // r8-r15 3999 case 'w': // VFP Floating point register single precision 4000 case 'P': // VFP Floating point register double precision 4001 Info.setAllowsRegister(); 4002 return true; 4003 case 'Q': // A memory address that is a single base register. 4004 Info.setAllowsMemory(); 4005 return true; 4006 case 'U': // a memory reference... 4007 switch (Name[1]) { 4008 case 'q': // ...ARMV4 ldrsb 4009 case 'v': // ...VFP load/store (reg+constant offset) 4010 case 'y': // ...iWMMXt load/store 4011 case 't': // address valid for load/store opaque types wider 4012 // than 128-bits 4013 case 'n': // valid address for Neon doubleword vector load/store 4014 case 'm': // valid address for Neon element and structure load/store 4015 case 's': // valid address for non-offset loads/stores of quad-word 4016 // values in four ARM registers 4017 Info.setAllowsMemory(); 4018 Name++; 4019 return true; 4020 } 4021 } 4022 return false; 4023 } 4024 std::string convertConstraint(const char *&Constraint) const override { 4025 std::string R; 4026 switch (*Constraint) { 4027 case 'U': // Two-character constraint; add "^" hint for later parsing. 4028 R = std::string("^") + std::string(Constraint, 2); 4029 Constraint++; 4030 break; 4031 case 'p': // 'p' should be translated to 'r' by default. 4032 R = std::string("r"); 4033 break; 4034 default: 4035 return std::string(1, *Constraint); 4036 } 4037 return R; 4038 } 4039 bool validateConstraintModifier(StringRef Constraint, const char Modifier, 4040 unsigned Size) const override { 4041 bool isOutput = (Constraint[0] == '='); 4042 bool isInOut = (Constraint[0] == '+'); 4043 4044 // Strip off constraint modifiers. 4045 while (Constraint[0] == '=' || 4046 Constraint[0] == '+' || 4047 Constraint[0] == '&') 4048 Constraint = Constraint.substr(1); 4049 4050 switch (Constraint[0]) { 4051 default: break; 4052 case 'r': { 4053 switch (Modifier) { 4054 default: 4055 return (isInOut || isOutput || Size <= 64); 4056 case 'q': 4057 // A register of size 32 cannot fit a vector type. 4058 return false; 4059 } 4060 } 4061 } 4062 4063 return true; 4064 } 4065 const char *getClobbers() const override { 4066 // FIXME: Is this really right? 4067 return ""; 4068 } 4069 4070 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4071 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4072 } 4073 4074 int getEHDataRegisterNumber(unsigned RegNo) const override { 4075 if (RegNo == 0) return 0; 4076 if (RegNo == 1) return 1; 4077 return -1; 4078 } 4079 }; 4080 4081 bool ARMTargetInfo::setFPMath(StringRef Name) { 4082 if (Name == "neon") { 4083 FPMath = FP_Neon; 4084 return true; 4085 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4086 Name == "vfp4") { 4087 FPMath = FP_VFP; 4088 return true; 4089 } 4090 return false; 4091 } 4092 4093 const char * const ARMTargetInfo::GCCRegNames[] = { 4094 // Integer registers 4095 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4096 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4097 4098 // Float registers 4099 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4100 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4101 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4102 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4103 4104 // Double registers 4105 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4106 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4107 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4108 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4109 4110 // Quad registers 4111 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4112 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4113 }; 4114 4115 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4116 unsigned &NumNames) const { 4117 Names = GCCRegNames; 4118 NumNames = llvm::array_lengthof(GCCRegNames); 4119 } 4120 4121 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4122 { { "a1" }, "r0" }, 4123 { { "a2" }, "r1" }, 4124 { { "a3" }, "r2" }, 4125 { { "a4" }, "r3" }, 4126 { { "v1" }, "r4" }, 4127 { { "v2" }, "r5" }, 4128 { { "v3" }, "r6" }, 4129 { { "v4" }, "r7" }, 4130 { { "v5" }, "r8" }, 4131 { { "v6", "rfp" }, "r9" }, 4132 { { "sl" }, "r10" }, 4133 { { "fp" }, "r11" }, 4134 { { "ip" }, "r12" }, 4135 { { "r13" }, "sp" }, 4136 { { "r14" }, "lr" }, 4137 { { "r15" }, "pc" }, 4138 // The S, D and Q registers overlap, but aren't really aliases; we 4139 // don't want to substitute one of these for a different-sized one. 4140 }; 4141 4142 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4143 unsigned &NumAliases) const { 4144 Aliases = GCCRegAliases; 4145 NumAliases = llvm::array_lengthof(GCCRegAliases); 4146 } 4147 4148 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4149 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4150 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4151 ALL_LANGUAGES }, 4152 #include "clang/Basic/BuiltinsNEON.def" 4153 4154 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4155 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4156 ALL_LANGUAGES }, 4157 #include "clang/Basic/BuiltinsARM.def" 4158 }; 4159 4160 class ARMleTargetInfo : public ARMTargetInfo { 4161 public: 4162 ARMleTargetInfo(const llvm::Triple &Triple) 4163 : ARMTargetInfo(Triple, false) { } 4164 virtual void getTargetDefines(const LangOptions &Opts, 4165 MacroBuilder &Builder) const { 4166 Builder.defineMacro("__ARMEL__"); 4167 ARMTargetInfo::getTargetDefines(Opts, Builder); 4168 } 4169 }; 4170 4171 class ARMbeTargetInfo : public ARMTargetInfo { 4172 public: 4173 ARMbeTargetInfo(const llvm::Triple &Triple) 4174 : ARMTargetInfo(Triple, true) { } 4175 virtual void getTargetDefines(const LangOptions &Opts, 4176 MacroBuilder &Builder) const { 4177 Builder.defineMacro("__ARMEB__"); 4178 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4179 ARMTargetInfo::getTargetDefines(Opts, Builder); 4180 } 4181 }; 4182 } // end anonymous namespace. 4183 4184 namespace { 4185 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 4186 const llvm::Triple Triple; 4187 public: 4188 WindowsARMTargetInfo(const llvm::Triple &Triple) 4189 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 4190 TLSSupported = false; 4191 WCharType = UnsignedShort; 4192 SizeType = UnsignedInt; 4193 UserLabelPrefix = ""; 4194 } 4195 void getVisualStudioDefines(const LangOptions &Opts, 4196 MacroBuilder &Builder) const { 4197 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 4198 4199 // FIXME: this is invalid for WindowsCE 4200 Builder.defineMacro("_M_ARM_NT", "1"); 4201 Builder.defineMacro("_M_ARMT", "_M_ARM"); 4202 Builder.defineMacro("_M_THUMB", "_M_ARM"); 4203 4204 assert((Triple.getArch() == llvm::Triple::arm || 4205 Triple.getArch() == llvm::Triple::thumb) && 4206 "invalid architecture for Windows ARM target info"); 4207 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 4208 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 4209 4210 // TODO map the complete set of values 4211 // 31: VFPv3 40: VFPv4 4212 Builder.defineMacro("_M_ARM_FP", "31"); 4213 } 4214 }; 4215 4216 // Windows ARM + Itanium C++ ABI Target 4217 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 4218 public: 4219 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 4220 : WindowsARMTargetInfo(Triple) { 4221 TheCXXABI.set(TargetCXXABI::GenericARM); 4222 } 4223 4224 void getTargetDefines(const LangOptions &Opts, 4225 MacroBuilder &Builder) const override { 4226 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4227 4228 if (Opts.MSVCCompat) 4229 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4230 } 4231 }; 4232 4233 // Windows ARM, MS (C++) ABI 4234 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 4235 public: 4236 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 4237 : WindowsARMTargetInfo(Triple) { 4238 TheCXXABI.set(TargetCXXABI::Microsoft); 4239 } 4240 4241 void getTargetDefines(const LangOptions &Opts, 4242 MacroBuilder &Builder) const override { 4243 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4244 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4245 } 4246 }; 4247 } 4248 4249 4250 namespace { 4251 class DarwinARMTargetInfo : 4252 public DarwinTargetInfo<ARMleTargetInfo> { 4253 protected: 4254 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4255 MacroBuilder &Builder) const override { 4256 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4257 } 4258 4259 public: 4260 DarwinARMTargetInfo(const llvm::Triple &Triple) 4261 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 4262 HasAlignMac68kSupport = true; 4263 // iOS always has 64-bit atomic instructions. 4264 // FIXME: This should be based off of the target features in ARMleTargetInfo. 4265 MaxAtomicInlineWidth = 64; 4266 4267 // Darwin on iOS uses a variant of the ARM C++ ABI. 4268 TheCXXABI.set(TargetCXXABI::iOS); 4269 } 4270 }; 4271 } // end anonymous namespace. 4272 4273 4274 namespace { 4275 class AArch64TargetInfo : public TargetInfo { 4276 virtual void setDescriptionString() = 0; 4277 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4278 static const char *const GCCRegNames[]; 4279 4280 enum FPUModeEnum { 4281 FPUMode, 4282 NeonMode 4283 }; 4284 4285 std::string CPU; 4286 unsigned FPU; 4287 unsigned CRC; 4288 unsigned Crypto; 4289 4290 static const Builtin::Info BuiltinInfo[]; 4291 4292 std::string ABI; 4293 4294 public: 4295 AArch64TargetInfo(const llvm::Triple &Triple) 4296 : TargetInfo(Triple), ABI("aapcs") { 4297 4298 if (getTriple().getOS() == llvm::Triple::NetBSD) { 4299 WCharType = SignedInt; 4300 4301 // NetBSD apparently prefers consistency across ARM targets to consistency 4302 // across 64-bit targets. 4303 Int64Type = SignedLongLong; 4304 IntMaxType = SignedLongLong; 4305 UIntMaxType = UnsignedLongLong; 4306 } else { 4307 WCharType = UnsignedInt; 4308 Int64Type = SignedLong; 4309 IntMaxType = SignedLong; 4310 UIntMaxType = UnsignedLong; 4311 } 4312 4313 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4314 MaxVectorAlign = 128; 4315 RegParmMax = 8; 4316 MaxAtomicInlineWidth = 128; 4317 MaxAtomicPromoteWidth = 128; 4318 4319 LongDoubleWidth = LongDoubleAlign = 128; 4320 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4321 4322 // {} in inline assembly are neon specifiers, not assembly variant 4323 // specifiers. 4324 NoAsmVariants = true; 4325 4326 // AArch64 targets default to using the ARM C++ ABI. 4327 TheCXXABI.set(TargetCXXABI::GenericAArch64); 4328 } 4329 4330 StringRef getABI() const override { return ABI; } 4331 virtual bool setABI(const std::string &Name) { 4332 if (Name != "aapcs" && Name != "darwinpcs") 4333 return false; 4334 4335 ABI = Name; 4336 return true; 4337 } 4338 4339 virtual bool setCPU(const std::string &Name) { 4340 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4341 .Case("generic", true) 4342 .Cases("cortex-a53", "cortex-a57", true) 4343 .Case("cyclone", true) 4344 .Default(false); 4345 if (CPUKnown) 4346 CPU = Name; 4347 return CPUKnown; 4348 } 4349 4350 virtual void getTargetDefines(const LangOptions &Opts, 4351 MacroBuilder &Builder) const { 4352 // Target identification. 4353 Builder.defineMacro("__aarch64__"); 4354 4355 // Target properties. 4356 Builder.defineMacro("_LP64"); 4357 Builder.defineMacro("__LP64__"); 4358 4359 // ACLE predefines. Many can only have one possible value on v8 AArch64. 4360 Builder.defineMacro("__ARM_ACLE", "200"); 4361 Builder.defineMacro("__ARM_ARCH", "8"); 4362 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 4363 4364 Builder.defineMacro("__ARM_64BIT_STATE"); 4365 Builder.defineMacro("__ARM_PCS_AAPCS64"); 4366 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 4367 4368 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 4369 Builder.defineMacro("__ARM_FEATURE_CLZ"); 4370 Builder.defineMacro("__ARM_FEATURE_FMA"); 4371 Builder.defineMacro("__ARM_FEATURE_DIV"); 4372 4373 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 4374 4375 // 0xe implies support for half, single and double precision operations. 4376 Builder.defineMacro("__ARM_FP", "0xe"); 4377 4378 // PCS specifies this for SysV variants, which is all we support. Other ABIs 4379 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 4380 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 4381 4382 if (Opts.FastMath || Opts.FiniteMathOnly) 4383 Builder.defineMacro("__ARM_FP_FAST"); 4384 4385 if ((Opts.C99 || Opts.C11) && !Opts.Freestanding) 4386 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 4387 4388 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 4389 4390 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4391 Opts.ShortEnums ? "1" : "4"); 4392 4393 if (FPU == NeonMode) { 4394 Builder.defineMacro("__ARM_NEON"); 4395 // 64-bit NEON supports half, single and double precision operations. 4396 Builder.defineMacro("__ARM_NEON_FP", "0xe"); 4397 } 4398 4399 if (CRC) 4400 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4401 4402 if (Crypto) 4403 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4404 } 4405 4406 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4407 unsigned &NumRecords) const { 4408 Records = BuiltinInfo; 4409 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin; 4410 } 4411 4412 virtual bool hasFeature(StringRef Feature) const { 4413 return Feature == "aarch64" || 4414 Feature == "arm64" || 4415 (Feature == "neon" && FPU == NeonMode); 4416 } 4417 4418 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 4419 4420 if (CPU == "cyclone") { 4421 Features["fp-armv8"] = true; 4422 Features["neon"] = true; 4423 Features["crypto"] = true; 4424 Features["crc"] = true; 4425 Features["zcm"] = true; 4426 Features["zcz"] = true; 4427 } else if (CPU == "cortex-a53" || CPU == "cortex-a57") { 4428 Features["fp-armv8"] = true; 4429 Features["neon"] = true; 4430 Features["crypto"] = true; 4431 Features["crc"] = true; 4432 } 4433 } 4434 4435 bool handleTargetFeatures(std::vector<std::string> &Features, 4436 DiagnosticsEngine &Diags) override { 4437 FPU = FPUMode; 4438 CRC = 0; 4439 Crypto = 0; 4440 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 4441 if (Features[i] == "+neon") 4442 FPU = NeonMode; 4443 if (Features[i] == "+crc") 4444 CRC = 1; 4445 if (Features[i] == "+crypto") 4446 Crypto = 1; 4447 } 4448 4449 setDescriptionString(); 4450 4451 return true; 4452 } 4453 4454 virtual bool isCLZForZeroUndef() const { return false; } 4455 4456 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4457 return TargetInfo::AArch64ABIBuiltinVaList; 4458 } 4459 4460 virtual void getGCCRegNames(const char *const *&Names, 4461 unsigned &NumNames) const; 4462 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4463 unsigned &NumAliases) const; 4464 4465 virtual bool validateAsmConstraint(const char *&Name, 4466 TargetInfo::ConstraintInfo &Info) const { 4467 switch (*Name) { 4468 default: 4469 return false; 4470 case 'w': // Floating point and SIMD registers (V0-V31) 4471 Info.setAllowsRegister(); 4472 return true; 4473 case 'I': // Constant that can be used with an ADD instruction 4474 case 'J': // Constant that can be used with a SUB instruction 4475 case 'K': // Constant that can be used with a 32-bit logical instruction 4476 case 'L': // Constant that can be used with a 64-bit logical instruction 4477 case 'M': // Constant that can be used as a 32-bit MOV immediate 4478 case 'N': // Constant that can be used as a 64-bit MOV immediate 4479 case 'Y': // Floating point constant zero 4480 case 'Z': // Integer constant zero 4481 return true; 4482 case 'Q': // A memory reference with base register and no offset 4483 Info.setAllowsMemory(); 4484 return true; 4485 case 'S': // A symbolic address 4486 Info.setAllowsRegister(); 4487 return true; 4488 case 'U': 4489 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be 4490 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be 4491 // Usa: An absolute symbolic address 4492 // Ush: The high part (bits 32:12) of a pc-relative symbolic address 4493 llvm_unreachable("FIXME: Unimplemented support for bizarre constraints"); 4494 case 'z': // Zero register, wzr or xzr 4495 Info.setAllowsRegister(); 4496 return true; 4497 case 'x': // Floating point and SIMD registers (V0-V15) 4498 Info.setAllowsRegister(); 4499 return true; 4500 } 4501 return false; 4502 } 4503 4504 virtual const char *getClobbers() const { return ""; } 4505 4506 int getEHDataRegisterNumber(unsigned RegNo) const { 4507 if (RegNo == 0) 4508 return 0; 4509 if (RegNo == 1) 4510 return 1; 4511 return -1; 4512 } 4513 }; 4514 4515 const char *const AArch64TargetInfo::GCCRegNames[] = { 4516 // 32-bit Integer registers 4517 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 4518 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 4519 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 4520 4521 // 64-bit Integer registers 4522 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 4523 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 4524 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 4525 4526 // 32-bit floating point regsisters 4527 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 4528 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 4529 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4530 4531 // 64-bit floating point regsisters 4532 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 4533 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 4534 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4535 4536 // Vector registers 4537 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 4538 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 4539 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 4540 }; 4541 4542 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names, 4543 unsigned &NumNames) const { 4544 Names = GCCRegNames; 4545 NumNames = llvm::array_lengthof(GCCRegNames); 4546 } 4547 4548 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 4549 { { "w31" }, "wsp" }, 4550 { { "x29" }, "fp" }, 4551 { { "x30" }, "lr" }, 4552 { { "x31" }, "sp" }, 4553 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 4554 // don't want to substitute one of these for a different-sized one. 4555 }; 4556 4557 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4558 unsigned &NumAliases) const { 4559 Aliases = GCCRegAliases; 4560 NumAliases = llvm::array_lengthof(GCCRegAliases); 4561 } 4562 4563 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 4564 #define BUILTIN(ID, TYPE, ATTRS) \ 4565 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4566 #include "clang/Basic/BuiltinsNEON.def" 4567 4568 #define BUILTIN(ID, TYPE, ATTRS) \ 4569 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4570 #include "clang/Basic/BuiltinsAArch64.def" 4571 }; 4572 4573 class AArch64leTargetInfo : public AArch64TargetInfo { 4574 void setDescriptionString() override { 4575 if (getTriple().isOSBinFormatMachO()) 4576 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128"; 4577 else 4578 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 4579 } 4580 4581 public: 4582 AArch64leTargetInfo(const llvm::Triple &Triple) 4583 : AArch64TargetInfo(Triple) { 4584 BigEndian = false; 4585 } 4586 void getTargetDefines(const LangOptions &Opts, 4587 MacroBuilder &Builder) const override { 4588 Builder.defineMacro("__AARCH64EL__"); 4589 AArch64TargetInfo::getTargetDefines(Opts, Builder); 4590 } 4591 }; 4592 4593 class AArch64beTargetInfo : public AArch64TargetInfo { 4594 void setDescriptionString() override { 4595 assert(!getTriple().isOSBinFormatMachO()); 4596 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128"; 4597 } 4598 4599 public: 4600 AArch64beTargetInfo(const llvm::Triple &Triple) 4601 : AArch64TargetInfo(Triple) { } 4602 void getTargetDefines(const LangOptions &Opts, 4603 MacroBuilder &Builder) const override { 4604 Builder.defineMacro("__AARCH64EB__"); 4605 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 4606 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4607 AArch64TargetInfo::getTargetDefines(Opts, Builder); 4608 } 4609 }; 4610 } // end anonymous namespace. 4611 4612 namespace { 4613 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 4614 protected: 4615 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4616 MacroBuilder &Builder) const override { 4617 Builder.defineMacro("__AARCH64_SIMD__"); 4618 Builder.defineMacro("__ARM64_ARCH_8__"); 4619 Builder.defineMacro("__ARM_NEON__"); 4620 Builder.defineMacro("__LITTLE_ENDIAN__"); 4621 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4622 Builder.defineMacro("__arm64", "1"); 4623 Builder.defineMacro("__arm64__", "1"); 4624 4625 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4626 } 4627 4628 public: 4629 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 4630 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 4631 Int64Type = SignedLongLong; 4632 WCharType = SignedInt; 4633 UseSignedCharForObjCBool = false; 4634 4635 LongDoubleWidth = LongDoubleAlign = 64; 4636 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4637 4638 TheCXXABI.set(TargetCXXABI::iOS64); 4639 } 4640 4641 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4642 return TargetInfo::CharPtrBuiltinVaList; 4643 } 4644 }; 4645 } // end anonymous namespace 4646 4647 namespace { 4648 // Hexagon abstract base class 4649 class HexagonTargetInfo : public TargetInfo { 4650 static const Builtin::Info BuiltinInfo[]; 4651 static const char * const GCCRegNames[]; 4652 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4653 std::string CPU; 4654 public: 4655 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4656 BigEndian = false; 4657 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 4658 4659 // {} in inline assembly are packet specifiers, not assembly variant 4660 // specifiers. 4661 NoAsmVariants = true; 4662 } 4663 4664 void getTargetBuiltins(const Builtin::Info *&Records, 4665 unsigned &NumRecords) const override { 4666 Records = BuiltinInfo; 4667 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 4668 } 4669 4670 bool validateAsmConstraint(const char *&Name, 4671 TargetInfo::ConstraintInfo &Info) const override { 4672 return true; 4673 } 4674 4675 void getTargetDefines(const LangOptions &Opts, 4676 MacroBuilder &Builder) const override; 4677 4678 bool hasFeature(StringRef Feature) const override { 4679 return Feature == "hexagon"; 4680 } 4681 4682 BuiltinVaListKind getBuiltinVaListKind() const override { 4683 return TargetInfo::CharPtrBuiltinVaList; 4684 } 4685 void getGCCRegNames(const char * const *&Names, 4686 unsigned &NumNames) const override; 4687 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4688 unsigned &NumAliases) const override; 4689 const char *getClobbers() const override { 4690 return ""; 4691 } 4692 4693 static const char *getHexagonCPUSuffix(StringRef Name) { 4694 return llvm::StringSwitch<const char*>(Name) 4695 .Case("hexagonv4", "4") 4696 .Case("hexagonv5", "5") 4697 .Default(nullptr); 4698 } 4699 4700 bool setCPU(const std::string &Name) override { 4701 if (!getHexagonCPUSuffix(Name)) 4702 return false; 4703 4704 CPU = Name; 4705 return true; 4706 } 4707 }; 4708 4709 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 4710 MacroBuilder &Builder) const { 4711 Builder.defineMacro("qdsp6"); 4712 Builder.defineMacro("__qdsp6", "1"); 4713 Builder.defineMacro("__qdsp6__", "1"); 4714 4715 Builder.defineMacro("hexagon"); 4716 Builder.defineMacro("__hexagon", "1"); 4717 Builder.defineMacro("__hexagon__", "1"); 4718 4719 if(CPU == "hexagonv1") { 4720 Builder.defineMacro("__HEXAGON_V1__"); 4721 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 4722 if(Opts.HexagonQdsp6Compat) { 4723 Builder.defineMacro("__QDSP6_V1__"); 4724 Builder.defineMacro("__QDSP6_ARCH__", "1"); 4725 } 4726 } 4727 else if(CPU == "hexagonv2") { 4728 Builder.defineMacro("__HEXAGON_V2__"); 4729 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 4730 if(Opts.HexagonQdsp6Compat) { 4731 Builder.defineMacro("__QDSP6_V2__"); 4732 Builder.defineMacro("__QDSP6_ARCH__", "2"); 4733 } 4734 } 4735 else if(CPU == "hexagonv3") { 4736 Builder.defineMacro("__HEXAGON_V3__"); 4737 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 4738 if(Opts.HexagonQdsp6Compat) { 4739 Builder.defineMacro("__QDSP6_V3__"); 4740 Builder.defineMacro("__QDSP6_ARCH__", "3"); 4741 } 4742 } 4743 else if(CPU == "hexagonv4") { 4744 Builder.defineMacro("__HEXAGON_V4__"); 4745 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 4746 if(Opts.HexagonQdsp6Compat) { 4747 Builder.defineMacro("__QDSP6_V4__"); 4748 Builder.defineMacro("__QDSP6_ARCH__", "4"); 4749 } 4750 } 4751 else if(CPU == "hexagonv5") { 4752 Builder.defineMacro("__HEXAGON_V5__"); 4753 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 4754 if(Opts.HexagonQdsp6Compat) { 4755 Builder.defineMacro("__QDSP6_V5__"); 4756 Builder.defineMacro("__QDSP6_ARCH__", "5"); 4757 } 4758 } 4759 } 4760 4761 const char * const HexagonTargetInfo::GCCRegNames[] = { 4762 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4763 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4764 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4765 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 4766 "p0", "p1", "p2", "p3", 4767 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 4768 }; 4769 4770 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 4771 unsigned &NumNames) const { 4772 Names = GCCRegNames; 4773 NumNames = llvm::array_lengthof(GCCRegNames); 4774 } 4775 4776 4777 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 4778 { { "sp" }, "r29" }, 4779 { { "fp" }, "r30" }, 4780 { { "lr" }, "r31" }, 4781 }; 4782 4783 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4784 unsigned &NumAliases) const { 4785 Aliases = GCCRegAliases; 4786 NumAliases = llvm::array_lengthof(GCCRegAliases); 4787 } 4788 4789 4790 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 4791 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4792 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4793 ALL_LANGUAGES }, 4794 #include "clang/Basic/BuiltinsHexagon.def" 4795 }; 4796 } 4797 4798 4799 namespace { 4800 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 4801 class SparcTargetInfo : public TargetInfo { 4802 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4803 static const char * const GCCRegNames[]; 4804 bool SoftFloat; 4805 public: 4806 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {} 4807 4808 bool handleTargetFeatures(std::vector<std::string> &Features, 4809 DiagnosticsEngine &Diags) override { 4810 SoftFloat = false; 4811 for (unsigned i = 0, e = Features.size(); i != e; ++i) 4812 if (Features[i] == "+soft-float") 4813 SoftFloat = true; 4814 return true; 4815 } 4816 void getTargetDefines(const LangOptions &Opts, 4817 MacroBuilder &Builder) const override { 4818 DefineStd(Builder, "sparc", Opts); 4819 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4820 4821 if (SoftFloat) 4822 Builder.defineMacro("SOFT_FLOAT", "1"); 4823 } 4824 4825 bool hasFeature(StringRef Feature) const override { 4826 return llvm::StringSwitch<bool>(Feature) 4827 .Case("softfloat", SoftFloat) 4828 .Case("sparc", true) 4829 .Default(false); 4830 } 4831 4832 void getTargetBuiltins(const Builtin::Info *&Records, 4833 unsigned &NumRecords) const override { 4834 // FIXME: Implement! 4835 } 4836 BuiltinVaListKind getBuiltinVaListKind() const override { 4837 return TargetInfo::VoidPtrBuiltinVaList; 4838 } 4839 void getGCCRegNames(const char * const *&Names, 4840 unsigned &NumNames) const override; 4841 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4842 unsigned &NumAliases) const override; 4843 bool validateAsmConstraint(const char *&Name, 4844 TargetInfo::ConstraintInfo &info) const override { 4845 // FIXME: Implement! 4846 return false; 4847 } 4848 const char *getClobbers() const override { 4849 // FIXME: Implement! 4850 return ""; 4851 } 4852 }; 4853 4854 const char * const SparcTargetInfo::GCCRegNames[] = { 4855 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4856 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4857 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4858 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 4859 }; 4860 4861 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 4862 unsigned &NumNames) const { 4863 Names = GCCRegNames; 4864 NumNames = llvm::array_lengthof(GCCRegNames); 4865 } 4866 4867 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 4868 { { "g0" }, "r0" }, 4869 { { "g1" }, "r1" }, 4870 { { "g2" }, "r2" }, 4871 { { "g3" }, "r3" }, 4872 { { "g4" }, "r4" }, 4873 { { "g5" }, "r5" }, 4874 { { "g6" }, "r6" }, 4875 { { "g7" }, "r7" }, 4876 { { "o0" }, "r8" }, 4877 { { "o1" }, "r9" }, 4878 { { "o2" }, "r10" }, 4879 { { "o3" }, "r11" }, 4880 { { "o4" }, "r12" }, 4881 { { "o5" }, "r13" }, 4882 { { "o6", "sp" }, "r14" }, 4883 { { "o7" }, "r15" }, 4884 { { "l0" }, "r16" }, 4885 { { "l1" }, "r17" }, 4886 { { "l2" }, "r18" }, 4887 { { "l3" }, "r19" }, 4888 { { "l4" }, "r20" }, 4889 { { "l5" }, "r21" }, 4890 { { "l6" }, "r22" }, 4891 { { "l7" }, "r23" }, 4892 { { "i0" }, "r24" }, 4893 { { "i1" }, "r25" }, 4894 { { "i2" }, "r26" }, 4895 { { "i3" }, "r27" }, 4896 { { "i4" }, "r28" }, 4897 { { "i5" }, "r29" }, 4898 { { "i6", "fp" }, "r30" }, 4899 { { "i7" }, "r31" }, 4900 }; 4901 4902 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4903 unsigned &NumAliases) const { 4904 Aliases = GCCRegAliases; 4905 NumAliases = llvm::array_lengthof(GCCRegAliases); 4906 } 4907 4908 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 4909 class SparcV8TargetInfo : public SparcTargetInfo { 4910 public: 4911 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4912 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 4913 } 4914 4915 void getTargetDefines(const LangOptions &Opts, 4916 MacroBuilder &Builder) const override { 4917 SparcTargetInfo::getTargetDefines(Opts, Builder); 4918 Builder.defineMacro("__sparcv8"); 4919 } 4920 }; 4921 4922 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 4923 class SparcV9TargetInfo : public SparcTargetInfo { 4924 public: 4925 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4926 // FIXME: Support Sparc quad-precision long double? 4927 DescriptionString = "E-m:e-i64:64-n32:64-S128"; 4928 // This is an LP64 platform. 4929 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4930 4931 // OpenBSD uses long long for int64_t and intmax_t. 4932 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 4933 IntMaxType = SignedLongLong; 4934 UIntMaxType = UnsignedLongLong; 4935 } else { 4936 IntMaxType = SignedLong; 4937 UIntMaxType = UnsignedLong; 4938 } 4939 Int64Type = IntMaxType; 4940 4941 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 4942 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 4943 LongDoubleWidth = 128; 4944 LongDoubleAlign = 128; 4945 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4946 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4947 } 4948 4949 void getTargetDefines(const LangOptions &Opts, 4950 MacroBuilder &Builder) const override { 4951 SparcTargetInfo::getTargetDefines(Opts, Builder); 4952 Builder.defineMacro("__sparcv9"); 4953 Builder.defineMacro("__arch64__"); 4954 // Solaris and its derivative AuroraUX don't need these variants, but the 4955 // BSDs do. 4956 if (getTriple().getOS() != llvm::Triple::Solaris && 4957 getTriple().getOS() != llvm::Triple::AuroraUX) { 4958 Builder.defineMacro("__sparc64__"); 4959 Builder.defineMacro("__sparc_v9__"); 4960 Builder.defineMacro("__sparcv9__"); 4961 } 4962 } 4963 4964 bool setCPU(const std::string &Name) override { 4965 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4966 .Case("v9", true) 4967 .Case("ultrasparc", true) 4968 .Case("ultrasparc3", true) 4969 .Case("niagara", true) 4970 .Case("niagara2", true) 4971 .Case("niagara3", true) 4972 .Case("niagara4", true) 4973 .Default(false); 4974 4975 // No need to store the CPU yet. There aren't any CPU-specific 4976 // macros to define. 4977 return CPUKnown; 4978 } 4979 }; 4980 4981 } // end anonymous namespace. 4982 4983 namespace { 4984 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> { 4985 public: 4986 AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple) 4987 : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) { 4988 SizeType = UnsignedInt; 4989 PtrDiffType = SignedInt; 4990 } 4991 }; 4992 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 4993 public: 4994 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 4995 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 4996 SizeType = UnsignedInt; 4997 PtrDiffType = SignedInt; 4998 } 4999 }; 5000 } // end anonymous namespace. 5001 5002 namespace { 5003 class SystemZTargetInfo : public TargetInfo { 5004 static const char *const GCCRegNames[]; 5005 5006 public: 5007 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5008 TLSSupported = true; 5009 IntWidth = IntAlign = 32; 5010 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5011 PointerWidth = PointerAlign = 64; 5012 LongDoubleWidth = 128; 5013 LongDoubleAlign = 64; 5014 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5015 MinGlobalAlign = 16; 5016 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5017 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5018 } 5019 void getTargetDefines(const LangOptions &Opts, 5020 MacroBuilder &Builder) const override { 5021 Builder.defineMacro("__s390__"); 5022 Builder.defineMacro("__s390x__"); 5023 Builder.defineMacro("__zarch__"); 5024 Builder.defineMacro("__LONG_DOUBLE_128__"); 5025 } 5026 void getTargetBuiltins(const Builtin::Info *&Records, 5027 unsigned &NumRecords) const override { 5028 // FIXME: Implement. 5029 Records = nullptr; 5030 NumRecords = 0; 5031 } 5032 5033 void getGCCRegNames(const char *const *&Names, 5034 unsigned &NumNames) const override; 5035 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5036 unsigned &NumAliases) const override { 5037 // No aliases. 5038 Aliases = nullptr; 5039 NumAliases = 0; 5040 } 5041 bool validateAsmConstraint(const char *&Name, 5042 TargetInfo::ConstraintInfo &info) const override; 5043 const char *getClobbers() const override { 5044 // FIXME: Is this really right? 5045 return ""; 5046 } 5047 BuiltinVaListKind getBuiltinVaListKind() const override { 5048 return TargetInfo::SystemZBuiltinVaList; 5049 } 5050 bool setCPU(const std::string &Name) override { 5051 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5052 .Case("z10", true) 5053 .Case("z196", true) 5054 .Case("zEC12", true) 5055 .Default(false); 5056 5057 // No need to store the CPU yet. There aren't any CPU-specific 5058 // macros to define. 5059 return CPUKnown; 5060 } 5061 }; 5062 5063 const char *const SystemZTargetInfo::GCCRegNames[] = { 5064 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5065 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5066 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 5067 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 5068 }; 5069 5070 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 5071 unsigned &NumNames) const { 5072 Names = GCCRegNames; 5073 NumNames = llvm::array_lengthof(GCCRegNames); 5074 } 5075 5076 bool SystemZTargetInfo:: 5077 validateAsmConstraint(const char *&Name, 5078 TargetInfo::ConstraintInfo &Info) const { 5079 switch (*Name) { 5080 default: 5081 return false; 5082 5083 case 'a': // Address register 5084 case 'd': // Data register (equivalent to 'r') 5085 case 'f': // Floating-point register 5086 Info.setAllowsRegister(); 5087 return true; 5088 5089 case 'I': // Unsigned 8-bit constant 5090 case 'J': // Unsigned 12-bit constant 5091 case 'K': // Signed 16-bit constant 5092 case 'L': // Signed 20-bit displacement (on all targets we support) 5093 case 'M': // 0x7fffffff 5094 return true; 5095 5096 case 'Q': // Memory with base and unsigned 12-bit displacement 5097 case 'R': // Likewise, plus an index 5098 case 'S': // Memory with base and signed 20-bit displacement 5099 case 'T': // Likewise, plus an index 5100 Info.setAllowsMemory(); 5101 return true; 5102 } 5103 } 5104 } 5105 5106 namespace { 5107 class MSP430TargetInfo : public TargetInfo { 5108 static const char * const GCCRegNames[]; 5109 public: 5110 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5111 BigEndian = false; 5112 TLSSupported = false; 5113 IntWidth = 16; IntAlign = 16; 5114 LongWidth = 32; LongLongWidth = 64; 5115 LongAlign = LongLongAlign = 16; 5116 PointerWidth = 16; PointerAlign = 16; 5117 SuitableAlign = 16; 5118 SizeType = UnsignedInt; 5119 IntMaxType = SignedLongLong; 5120 UIntMaxType = UnsignedLongLong; 5121 IntPtrType = SignedInt; 5122 PtrDiffType = SignedInt; 5123 SigAtomicType = SignedLong; 5124 DescriptionString = "e-m:e-p:16:16-i32:16:32-n8:16"; 5125 } 5126 void getTargetDefines(const LangOptions &Opts, 5127 MacroBuilder &Builder) const override { 5128 Builder.defineMacro("MSP430"); 5129 Builder.defineMacro("__MSP430__"); 5130 // FIXME: defines for different 'flavours' of MCU 5131 } 5132 void getTargetBuiltins(const Builtin::Info *&Records, 5133 unsigned &NumRecords) const override { 5134 // FIXME: Implement. 5135 Records = nullptr; 5136 NumRecords = 0; 5137 } 5138 bool hasFeature(StringRef Feature) const override { 5139 return Feature == "msp430"; 5140 } 5141 void getGCCRegNames(const char * const *&Names, 5142 unsigned &NumNames) const override; 5143 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5144 unsigned &NumAliases) const override { 5145 // No aliases. 5146 Aliases = nullptr; 5147 NumAliases = 0; 5148 } 5149 bool validateAsmConstraint(const char *&Name, 5150 TargetInfo::ConstraintInfo &info) const override { 5151 // No target constraints for now. 5152 return false; 5153 } 5154 const char *getClobbers() const override { 5155 // FIXME: Is this really right? 5156 return ""; 5157 } 5158 BuiltinVaListKind getBuiltinVaListKind() const override { 5159 // FIXME: implement 5160 return TargetInfo::CharPtrBuiltinVaList; 5161 } 5162 }; 5163 5164 const char * const MSP430TargetInfo::GCCRegNames[] = { 5165 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5166 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 5167 }; 5168 5169 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 5170 unsigned &NumNames) const { 5171 Names = GCCRegNames; 5172 NumNames = llvm::array_lengthof(GCCRegNames); 5173 } 5174 } 5175 5176 namespace { 5177 5178 // LLVM and Clang cannot be used directly to output native binaries for 5179 // target, but is used to compile C code to llvm bitcode with correct 5180 // type and alignment information. 5181 // 5182 // TCE uses the llvm bitcode as input and uses it for generating customized 5183 // target processor and program binary. TCE co-design environment is 5184 // publicly available in http://tce.cs.tut.fi 5185 5186 static const unsigned TCEOpenCLAddrSpaceMap[] = { 5187 3, // opencl_global 5188 4, // opencl_local 5189 5, // opencl_constant 5190 0, // cuda_device 5191 0, // cuda_constant 5192 0 // cuda_shared 5193 }; 5194 5195 class TCETargetInfo : public TargetInfo{ 5196 public: 5197 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5198 TLSSupported = false; 5199 IntWidth = 32; 5200 LongWidth = LongLongWidth = 32; 5201 PointerWidth = 32; 5202 IntAlign = 32; 5203 LongAlign = LongLongAlign = 32; 5204 PointerAlign = 32; 5205 SuitableAlign = 32; 5206 SizeType = UnsignedInt; 5207 IntMaxType = SignedLong; 5208 UIntMaxType = UnsignedLong; 5209 IntPtrType = SignedInt; 5210 PtrDiffType = SignedInt; 5211 FloatWidth = 32; 5212 FloatAlign = 32; 5213 DoubleWidth = 32; 5214 DoubleAlign = 32; 5215 LongDoubleWidth = 32; 5216 LongDoubleAlign = 32; 5217 FloatFormat = &llvm::APFloat::IEEEsingle; 5218 DoubleFormat = &llvm::APFloat::IEEEsingle; 5219 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 5220 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 5221 "-f64:32-v64:32-v128:32-a:0:32-n32"; 5222 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 5223 UseAddrSpaceMapMangling = true; 5224 } 5225 5226 void getTargetDefines(const LangOptions &Opts, 5227 MacroBuilder &Builder) const override { 5228 DefineStd(Builder, "tce", Opts); 5229 Builder.defineMacro("__TCE__"); 5230 Builder.defineMacro("__TCE_V1__"); 5231 } 5232 bool hasFeature(StringRef Feature) const override { 5233 return Feature == "tce"; 5234 } 5235 5236 void getTargetBuiltins(const Builtin::Info *&Records, 5237 unsigned &NumRecords) const override {} 5238 const char *getClobbers() const override { 5239 return ""; 5240 } 5241 BuiltinVaListKind getBuiltinVaListKind() const override { 5242 return TargetInfo::VoidPtrBuiltinVaList; 5243 } 5244 void getGCCRegNames(const char * const *&Names, 5245 unsigned &NumNames) const override {} 5246 bool validateAsmConstraint(const char *&Name, 5247 TargetInfo::ConstraintInfo &info) const override{ 5248 return true; 5249 } 5250 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5251 unsigned &NumAliases) const override {} 5252 }; 5253 } 5254 5255 namespace { 5256 class MipsTargetInfoBase : public TargetInfo { 5257 virtual void setDescriptionString() = 0; 5258 5259 static const Builtin::Info BuiltinInfo[]; 5260 std::string CPU; 5261 bool IsMips16; 5262 bool IsMicromips; 5263 bool IsNan2008; 5264 bool IsSingleFloat; 5265 enum MipsFloatABI { 5266 HardFloat, SoftFloat 5267 } FloatABI; 5268 enum DspRevEnum { 5269 NoDSP, DSP1, DSP2 5270 } DspRev; 5271 bool HasMSA; 5272 5273 protected: 5274 bool HasFP64; 5275 std::string ABI; 5276 5277 public: 5278 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 5279 const std::string &CPUStr) 5280 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 5281 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 5282 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {} 5283 5284 StringRef getABI() const override { return ABI; } 5285 bool setABI(const std::string &Name) override = 0; 5286 bool setCPU(const std::string &Name) override { 5287 CPU = Name; 5288 return true; 5289 } 5290 const std::string& getCPU() const { return CPU; } 5291 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5292 // The backend enables certain ABI's by default according to the 5293 // architecture. 5294 // Disable both possible defaults so that we don't end up with multiple 5295 // ABI's selected and trigger an assertion. 5296 Features["o32"] = false; 5297 Features["n64"] = false; 5298 5299 Features[ABI] = true; 5300 Features[CPU] = true; 5301 } 5302 5303 void getTargetDefines(const LangOptions &Opts, 5304 MacroBuilder &Builder) const override { 5305 Builder.defineMacro("__mips__"); 5306 Builder.defineMacro("_mips"); 5307 if (Opts.GNUMode) 5308 Builder.defineMacro("mips"); 5309 5310 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5311 5312 switch (FloatABI) { 5313 case HardFloat: 5314 Builder.defineMacro("__mips_hard_float", Twine(1)); 5315 break; 5316 case SoftFloat: 5317 Builder.defineMacro("__mips_soft_float", Twine(1)); 5318 break; 5319 } 5320 5321 if (IsSingleFloat) 5322 Builder.defineMacro("__mips_single_float", Twine(1)); 5323 5324 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 5325 Builder.defineMacro("_MIPS_FPSET", 5326 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 5327 5328 if (IsMips16) 5329 Builder.defineMacro("__mips16", Twine(1)); 5330 5331 if (IsMicromips) 5332 Builder.defineMacro("__mips_micromips", Twine(1)); 5333 5334 if (IsNan2008) 5335 Builder.defineMacro("__mips_nan2008", Twine(1)); 5336 5337 switch (DspRev) { 5338 default: 5339 break; 5340 case DSP1: 5341 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 5342 Builder.defineMacro("__mips_dsp", Twine(1)); 5343 break; 5344 case DSP2: 5345 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 5346 Builder.defineMacro("__mips_dspr2", Twine(1)); 5347 Builder.defineMacro("__mips_dsp", Twine(1)); 5348 break; 5349 } 5350 5351 if (HasMSA) 5352 Builder.defineMacro("__mips_msa", Twine(1)); 5353 5354 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 5355 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 5356 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 5357 5358 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 5359 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 5360 } 5361 5362 void getTargetBuiltins(const Builtin::Info *&Records, 5363 unsigned &NumRecords) const override { 5364 Records = BuiltinInfo; 5365 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 5366 } 5367 bool hasFeature(StringRef Feature) const override { 5368 return llvm::StringSwitch<bool>(Feature) 5369 .Case("mips", true) 5370 .Case("fp64", HasFP64) 5371 .Default(false); 5372 } 5373 BuiltinVaListKind getBuiltinVaListKind() const override { 5374 return TargetInfo::VoidPtrBuiltinVaList; 5375 } 5376 void getGCCRegNames(const char * const *&Names, 5377 unsigned &NumNames) const override { 5378 static const char *const GCCRegNames[] = { 5379 // CPU register names 5380 // Must match second column of GCCRegAliases 5381 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 5382 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 5383 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 5384 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 5385 // Floating point register names 5386 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 5387 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 5388 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 5389 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 5390 // Hi/lo and condition register names 5391 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 5392 "$fcc5","$fcc6","$fcc7", 5393 // MSA register names 5394 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 5395 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 5396 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 5397 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 5398 // MSA control register names 5399 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 5400 "$msarequest", "$msamap", "$msaunmap" 5401 }; 5402 Names = GCCRegNames; 5403 NumNames = llvm::array_lengthof(GCCRegNames); 5404 } 5405 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5406 unsigned &NumAliases) const override = 0; 5407 bool validateAsmConstraint(const char *&Name, 5408 TargetInfo::ConstraintInfo &Info) const override { 5409 switch (*Name) { 5410 default: 5411 return false; 5412 5413 case 'r': // CPU registers. 5414 case 'd': // Equivalent to "r" unless generating MIPS16 code. 5415 case 'y': // Equivalent to "r", backwards compatibility only. 5416 case 'f': // floating-point registers. 5417 case 'c': // $25 for indirect jumps 5418 case 'l': // lo register 5419 case 'x': // hilo register pair 5420 Info.setAllowsRegister(); 5421 return true; 5422 case 'R': // An address that can be used in a non-macro load or store 5423 Info.setAllowsMemory(); 5424 return true; 5425 } 5426 } 5427 5428 const char *getClobbers() const override { 5429 // FIXME: Implement! 5430 return ""; 5431 } 5432 5433 bool handleTargetFeatures(std::vector<std::string> &Features, 5434 DiagnosticsEngine &Diags) override { 5435 IsMips16 = false; 5436 IsMicromips = false; 5437 IsNan2008 = false; 5438 IsSingleFloat = false; 5439 FloatABI = HardFloat; 5440 DspRev = NoDSP; 5441 HasFP64 = ABI == "n32" || ABI == "n64" || ABI == "64"; 5442 5443 for (std::vector<std::string>::iterator it = Features.begin(), 5444 ie = Features.end(); it != ie; ++it) { 5445 if (*it == "+single-float") 5446 IsSingleFloat = true; 5447 else if (*it == "+soft-float") 5448 FloatABI = SoftFloat; 5449 else if (*it == "+mips16") 5450 IsMips16 = true; 5451 else if (*it == "+micromips") 5452 IsMicromips = true; 5453 else if (*it == "+dsp") 5454 DspRev = std::max(DspRev, DSP1); 5455 else if (*it == "+dspr2") 5456 DspRev = std::max(DspRev, DSP2); 5457 else if (*it == "+msa") 5458 HasMSA = true; 5459 else if (*it == "+fp64") 5460 HasFP64 = true; 5461 else if (*it == "-fp64") 5462 HasFP64 = false; 5463 else if (*it == "+nan2008") 5464 IsNan2008 = true; 5465 } 5466 5467 // Remove front-end specific options. 5468 std::vector<std::string>::iterator it = 5469 std::find(Features.begin(), Features.end(), "+soft-float"); 5470 if (it != Features.end()) 5471 Features.erase(it); 5472 5473 setDescriptionString(); 5474 5475 return true; 5476 } 5477 5478 int getEHDataRegisterNumber(unsigned RegNo) const override { 5479 if (RegNo == 0) return 4; 5480 if (RegNo == 1) return 5; 5481 return -1; 5482 } 5483 }; 5484 5485 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 5486 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5487 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5488 ALL_LANGUAGES }, 5489 #include "clang/Basic/BuiltinsMips.def" 5490 }; 5491 5492 class Mips32TargetInfoBase : public MipsTargetInfoBase { 5493 public: 5494 Mips32TargetInfoBase(const llvm::Triple &Triple) 5495 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 5496 SizeType = UnsignedInt; 5497 PtrDiffType = SignedInt; 5498 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 5499 } 5500 bool setABI(const std::string &Name) override { 5501 if ((Name == "o32") || (Name == "eabi")) { 5502 ABI = Name; 5503 return true; 5504 } else if (Name == "32") { 5505 ABI = "o32"; 5506 return true; 5507 } else 5508 return false; 5509 } 5510 void getTargetDefines(const LangOptions &Opts, 5511 MacroBuilder &Builder) const override { 5512 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5513 5514 Builder.defineMacro("__mips", "32"); 5515 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 5516 5517 const std::string& CPUStr = getCPU(); 5518 if (CPUStr == "mips32") 5519 Builder.defineMacro("__mips_isa_rev", "1"); 5520 else if (CPUStr == "mips32r2") 5521 Builder.defineMacro("__mips_isa_rev", "2"); 5522 5523 if (ABI == "o32") { 5524 Builder.defineMacro("__mips_o32"); 5525 Builder.defineMacro("_ABIO32", "1"); 5526 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 5527 } 5528 else if (ABI == "eabi") 5529 Builder.defineMacro("__mips_eabi"); 5530 else 5531 llvm_unreachable("Invalid ABI for Mips32."); 5532 } 5533 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5534 unsigned &NumAliases) const override { 5535 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5536 { { "at" }, "$1" }, 5537 { { "v0" }, "$2" }, 5538 { { "v1" }, "$3" }, 5539 { { "a0" }, "$4" }, 5540 { { "a1" }, "$5" }, 5541 { { "a2" }, "$6" }, 5542 { { "a3" }, "$7" }, 5543 { { "t0" }, "$8" }, 5544 { { "t1" }, "$9" }, 5545 { { "t2" }, "$10" }, 5546 { { "t3" }, "$11" }, 5547 { { "t4" }, "$12" }, 5548 { { "t5" }, "$13" }, 5549 { { "t6" }, "$14" }, 5550 { { "t7" }, "$15" }, 5551 { { "s0" }, "$16" }, 5552 { { "s1" }, "$17" }, 5553 { { "s2" }, "$18" }, 5554 { { "s3" }, "$19" }, 5555 { { "s4" }, "$20" }, 5556 { { "s5" }, "$21" }, 5557 { { "s6" }, "$22" }, 5558 { { "s7" }, "$23" }, 5559 { { "t8" }, "$24" }, 5560 { { "t9" }, "$25" }, 5561 { { "k0" }, "$26" }, 5562 { { "k1" }, "$27" }, 5563 { { "gp" }, "$28" }, 5564 { { "sp","$sp" }, "$29" }, 5565 { { "fp","$fp" }, "$30" }, 5566 { { "ra" }, "$31" } 5567 }; 5568 Aliases = GCCRegAliases; 5569 NumAliases = llvm::array_lengthof(GCCRegAliases); 5570 } 5571 }; 5572 5573 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 5574 void setDescriptionString() override { 5575 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5576 } 5577 5578 public: 5579 Mips32EBTargetInfo(const llvm::Triple &Triple) 5580 : Mips32TargetInfoBase(Triple) { 5581 } 5582 void getTargetDefines(const LangOptions &Opts, 5583 MacroBuilder &Builder) const override { 5584 DefineStd(Builder, "MIPSEB", Opts); 5585 Builder.defineMacro("_MIPSEB"); 5586 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5587 } 5588 }; 5589 5590 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 5591 void setDescriptionString() override { 5592 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5593 } 5594 5595 public: 5596 Mips32ELTargetInfo(const llvm::Triple &Triple) 5597 : Mips32TargetInfoBase(Triple) { 5598 BigEndian = false; 5599 } 5600 void getTargetDefines(const LangOptions &Opts, 5601 MacroBuilder &Builder) const override { 5602 DefineStd(Builder, "MIPSEL", Opts); 5603 Builder.defineMacro("_MIPSEL"); 5604 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5605 } 5606 }; 5607 5608 class Mips64TargetInfoBase : public MipsTargetInfoBase { 5609 public: 5610 Mips64TargetInfoBase(const llvm::Triple &Triple) 5611 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 5612 LongDoubleWidth = LongDoubleAlign = 128; 5613 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5614 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 5615 LongDoubleWidth = LongDoubleAlign = 64; 5616 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5617 } 5618 setN64ABITypes(); 5619 SuitableAlign = 128; 5620 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5621 } 5622 5623 void setN64ABITypes() { 5624 LongWidth = LongAlign = 64; 5625 PointerWidth = PointerAlign = 64; 5626 SizeType = UnsignedLong; 5627 PtrDiffType = SignedLong; 5628 } 5629 5630 void setN32ABITypes() { 5631 LongWidth = LongAlign = 32; 5632 PointerWidth = PointerAlign = 32; 5633 SizeType = UnsignedInt; 5634 PtrDiffType = SignedInt; 5635 } 5636 5637 bool setABI(const std::string &Name) override { 5638 if (Name == "n32") { 5639 setN32ABITypes(); 5640 ABI = Name; 5641 return true; 5642 } else if (Name == "n64" || Name == "64") { 5643 setN64ABITypes(); 5644 ABI = "n64"; 5645 return true; 5646 } 5647 return false; 5648 } 5649 5650 void getTargetDefines(const LangOptions &Opts, 5651 MacroBuilder &Builder) const override { 5652 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5653 5654 Builder.defineMacro("__mips", "64"); 5655 Builder.defineMacro("__mips64"); 5656 Builder.defineMacro("__mips64__"); 5657 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 5658 5659 const std::string& CPUStr = getCPU(); 5660 if (CPUStr == "mips64") 5661 Builder.defineMacro("__mips_isa_rev", "1"); 5662 else if (CPUStr == "mips64r2") 5663 Builder.defineMacro("__mips_isa_rev", "2"); 5664 5665 if (ABI == "n32") { 5666 Builder.defineMacro("__mips_n32"); 5667 Builder.defineMacro("_ABIN32", "2"); 5668 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 5669 } 5670 else if (ABI == "n64") { 5671 Builder.defineMacro("__mips_n64"); 5672 Builder.defineMacro("_ABI64", "3"); 5673 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 5674 } 5675 else 5676 llvm_unreachable("Invalid ABI for Mips64."); 5677 } 5678 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5679 unsigned &NumAliases) const override { 5680 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5681 { { "at" }, "$1" }, 5682 { { "v0" }, "$2" }, 5683 { { "v1" }, "$3" }, 5684 { { "a0" }, "$4" }, 5685 { { "a1" }, "$5" }, 5686 { { "a2" }, "$6" }, 5687 { { "a3" }, "$7" }, 5688 { { "a4" }, "$8" }, 5689 { { "a5" }, "$9" }, 5690 { { "a6" }, "$10" }, 5691 { { "a7" }, "$11" }, 5692 { { "t0" }, "$12" }, 5693 { { "t1" }, "$13" }, 5694 { { "t2" }, "$14" }, 5695 { { "t3" }, "$15" }, 5696 { { "s0" }, "$16" }, 5697 { { "s1" }, "$17" }, 5698 { { "s2" }, "$18" }, 5699 { { "s3" }, "$19" }, 5700 { { "s4" }, "$20" }, 5701 { { "s5" }, "$21" }, 5702 { { "s6" }, "$22" }, 5703 { { "s7" }, "$23" }, 5704 { { "t8" }, "$24" }, 5705 { { "t9" }, "$25" }, 5706 { { "k0" }, "$26" }, 5707 { { "k1" }, "$27" }, 5708 { { "gp" }, "$28" }, 5709 { { "sp","$sp" }, "$29" }, 5710 { { "fp","$fp" }, "$30" }, 5711 { { "ra" }, "$31" } 5712 }; 5713 Aliases = GCCRegAliases; 5714 NumAliases = llvm::array_lengthof(GCCRegAliases); 5715 } 5716 5717 bool hasInt128Type() const override { return true; } 5718 }; 5719 5720 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 5721 void setDescriptionString() override { 5722 if (ABI == "n32") 5723 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5724 else 5725 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5726 5727 } 5728 5729 public: 5730 Mips64EBTargetInfo(const llvm::Triple &Triple) 5731 : Mips64TargetInfoBase(Triple) {} 5732 void getTargetDefines(const LangOptions &Opts, 5733 MacroBuilder &Builder) const override { 5734 DefineStd(Builder, "MIPSEB", Opts); 5735 Builder.defineMacro("_MIPSEB"); 5736 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5737 } 5738 }; 5739 5740 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 5741 void setDescriptionString() override { 5742 if (ABI == "n32") 5743 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5744 else 5745 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5746 } 5747 public: 5748 Mips64ELTargetInfo(const llvm::Triple &Triple) 5749 : Mips64TargetInfoBase(Triple) { 5750 // Default ABI is n64. 5751 BigEndian = false; 5752 } 5753 void getTargetDefines(const LangOptions &Opts, 5754 MacroBuilder &Builder) const override { 5755 DefineStd(Builder, "MIPSEL", Opts); 5756 Builder.defineMacro("_MIPSEL"); 5757 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5758 } 5759 }; 5760 } // end anonymous namespace. 5761 5762 namespace { 5763 class PNaClTargetInfo : public TargetInfo { 5764 public: 5765 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5766 BigEndian = false; 5767 this->UserLabelPrefix = ""; 5768 this->LongAlign = 32; 5769 this->LongWidth = 32; 5770 this->PointerAlign = 32; 5771 this->PointerWidth = 32; 5772 this->IntMaxType = TargetInfo::SignedLongLong; 5773 this->UIntMaxType = TargetInfo::UnsignedLongLong; 5774 this->Int64Type = TargetInfo::SignedLongLong; 5775 this->DoubleAlign = 64; 5776 this->LongDoubleWidth = 64; 5777 this->LongDoubleAlign = 64; 5778 this->SizeType = TargetInfo::UnsignedInt; 5779 this->PtrDiffType = TargetInfo::SignedInt; 5780 this->IntPtrType = TargetInfo::SignedInt; 5781 this->RegParmMax = 0; // Disallow regparm 5782 } 5783 5784 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5785 } 5786 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 5787 Builder.defineMacro("__le32__"); 5788 Builder.defineMacro("__pnacl__"); 5789 } 5790 void getTargetDefines(const LangOptions &Opts, 5791 MacroBuilder &Builder) const override { 5792 getArchDefines(Opts, Builder); 5793 } 5794 bool hasFeature(StringRef Feature) const override { 5795 return Feature == "pnacl"; 5796 } 5797 void getTargetBuiltins(const Builtin::Info *&Records, 5798 unsigned &NumRecords) const override { 5799 } 5800 BuiltinVaListKind getBuiltinVaListKind() const override { 5801 return TargetInfo::PNaClABIBuiltinVaList; 5802 } 5803 void getGCCRegNames(const char * const *&Names, 5804 unsigned &NumNames) const override; 5805 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5806 unsigned &NumAliases) const override; 5807 bool validateAsmConstraint(const char *&Name, 5808 TargetInfo::ConstraintInfo &Info) const override { 5809 return false; 5810 } 5811 5812 const char *getClobbers() const override { 5813 return ""; 5814 } 5815 }; 5816 5817 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 5818 unsigned &NumNames) const { 5819 Names = nullptr; 5820 NumNames = 0; 5821 } 5822 5823 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5824 unsigned &NumAliases) const { 5825 Aliases = nullptr; 5826 NumAliases = 0; 5827 } 5828 } // end anonymous namespace. 5829 5830 namespace { 5831 static const unsigned SPIRAddrSpaceMap[] = { 5832 1, // opencl_global 5833 3, // opencl_local 5834 2, // opencl_constant 5835 0, // cuda_device 5836 0, // cuda_constant 5837 0 // cuda_shared 5838 }; 5839 class SPIRTargetInfo : public TargetInfo { 5840 public: 5841 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5842 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 5843 "SPIR target must use unknown OS"); 5844 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 5845 "SPIR target must use unknown environment type"); 5846 BigEndian = false; 5847 TLSSupported = false; 5848 LongWidth = LongAlign = 64; 5849 AddrSpaceMap = &SPIRAddrSpaceMap; 5850 UseAddrSpaceMapMangling = true; 5851 // Define available target features 5852 // These must be defined in sorted order! 5853 NoAsmVariants = true; 5854 } 5855 void getTargetDefines(const LangOptions &Opts, 5856 MacroBuilder &Builder) const override { 5857 DefineStd(Builder, "SPIR", Opts); 5858 } 5859 bool hasFeature(StringRef Feature) const override { 5860 return Feature == "spir"; 5861 } 5862 5863 void getTargetBuiltins(const Builtin::Info *&Records, 5864 unsigned &NumRecords) const override {} 5865 const char *getClobbers() const override { 5866 return ""; 5867 } 5868 void getGCCRegNames(const char * const *&Names, 5869 unsigned &NumNames) const override {} 5870 bool validateAsmConstraint(const char *&Name, 5871 TargetInfo::ConstraintInfo &info) const override { 5872 return true; 5873 } 5874 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5875 unsigned &NumAliases) const override {} 5876 BuiltinVaListKind getBuiltinVaListKind() const override { 5877 return TargetInfo::VoidPtrBuiltinVaList; 5878 } 5879 }; 5880 5881 5882 class SPIR32TargetInfo : public SPIRTargetInfo { 5883 public: 5884 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5885 PointerWidth = PointerAlign = 32; 5886 SizeType = TargetInfo::UnsignedInt; 5887 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 5888 DescriptionString 5889 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 5890 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 5891 } 5892 void getTargetDefines(const LangOptions &Opts, 5893 MacroBuilder &Builder) const override { 5894 DefineStd(Builder, "SPIR32", Opts); 5895 } 5896 }; 5897 5898 class SPIR64TargetInfo : public SPIRTargetInfo { 5899 public: 5900 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5901 PointerWidth = PointerAlign = 64; 5902 SizeType = TargetInfo::UnsignedLong; 5903 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 5904 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 5905 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 5906 } 5907 void getTargetDefines(const LangOptions &Opts, 5908 MacroBuilder &Builder) const override { 5909 DefineStd(Builder, "SPIR64", Opts); 5910 } 5911 }; 5912 } 5913 5914 namespace { 5915 class XCoreTargetInfo : public TargetInfo { 5916 static const Builtin::Info BuiltinInfo[]; 5917 public: 5918 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5919 BigEndian = false; 5920 NoAsmVariants = true; 5921 LongLongAlign = 32; 5922 SuitableAlign = 32; 5923 DoubleAlign = LongDoubleAlign = 32; 5924 SizeType = UnsignedInt; 5925 PtrDiffType = SignedInt; 5926 IntPtrType = SignedInt; 5927 WCharType = UnsignedChar; 5928 WIntType = UnsignedInt; 5929 UseZeroLengthBitfieldAlignment = true; 5930 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 5931 "-f64:32-a:0:32-n32"; 5932 } 5933 void getTargetDefines(const LangOptions &Opts, 5934 MacroBuilder &Builder) const override { 5935 Builder.defineMacro("__XS1B__"); 5936 } 5937 void getTargetBuiltins(const Builtin::Info *&Records, 5938 unsigned &NumRecords) const override { 5939 Records = BuiltinInfo; 5940 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 5941 } 5942 BuiltinVaListKind getBuiltinVaListKind() const override { 5943 return TargetInfo::VoidPtrBuiltinVaList; 5944 } 5945 const char *getClobbers() const override { 5946 return ""; 5947 } 5948 void getGCCRegNames(const char * const *&Names, 5949 unsigned &NumNames) const override { 5950 static const char * const GCCRegNames[] = { 5951 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5952 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 5953 }; 5954 Names = GCCRegNames; 5955 NumNames = llvm::array_lengthof(GCCRegNames); 5956 } 5957 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5958 unsigned &NumAliases) const override { 5959 Aliases = nullptr; 5960 NumAliases = 0; 5961 } 5962 bool validateAsmConstraint(const char *&Name, 5963 TargetInfo::ConstraintInfo &Info) const override { 5964 return false; 5965 } 5966 int getEHDataRegisterNumber(unsigned RegNo) const override { 5967 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 5968 return (RegNo < 2)? RegNo : -1; 5969 } 5970 }; 5971 5972 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 5973 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5974 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5975 ALL_LANGUAGES }, 5976 #include "clang/Basic/BuiltinsXCore.def" 5977 }; 5978 } // end anonymous namespace. 5979 5980 5981 //===----------------------------------------------------------------------===// 5982 // Driver code 5983 //===----------------------------------------------------------------------===// 5984 5985 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 5986 llvm::Triple::OSType os = Triple.getOS(); 5987 5988 switch (Triple.getArch()) { 5989 default: 5990 return nullptr; 5991 5992 case llvm::Triple::xcore: 5993 return new XCoreTargetInfo(Triple); 5994 5995 case llvm::Triple::hexagon: 5996 return new HexagonTargetInfo(Triple); 5997 5998 case llvm::Triple::aarch64: 5999 case llvm::Triple::arm64: 6000 if (Triple.isOSDarwin()) 6001 return new DarwinAArch64TargetInfo(Triple); 6002 6003 switch (os) { 6004 case llvm::Triple::Linux: 6005 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 6006 case llvm::Triple::NetBSD: 6007 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 6008 default: 6009 return new AArch64leTargetInfo(Triple); 6010 } 6011 6012 case llvm::Triple::aarch64_be: 6013 case llvm::Triple::arm64_be: 6014 switch (os) { 6015 case llvm::Triple::Linux: 6016 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 6017 case llvm::Triple::NetBSD: 6018 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 6019 default: 6020 return new AArch64beTargetInfo(Triple); 6021 } 6022 6023 case llvm::Triple::arm: 6024 case llvm::Triple::thumb: 6025 if (Triple.isOSBinFormatMachO()) 6026 return new DarwinARMTargetInfo(Triple); 6027 6028 switch (os) { 6029 case llvm::Triple::Linux: 6030 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 6031 case llvm::Triple::FreeBSD: 6032 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 6033 case llvm::Triple::NetBSD: 6034 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 6035 case llvm::Triple::OpenBSD: 6036 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 6037 case llvm::Triple::Bitrig: 6038 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 6039 case llvm::Triple::RTEMS: 6040 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 6041 case llvm::Triple::NaCl: 6042 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 6043 case llvm::Triple::Win32: 6044 switch (Triple.getEnvironment()) { 6045 default: 6046 return new ARMleTargetInfo(Triple); 6047 case llvm::Triple::Itanium: 6048 return new ItaniumWindowsARMleTargetInfo(Triple); 6049 case llvm::Triple::MSVC: 6050 return new MicrosoftARMleTargetInfo(Triple); 6051 } 6052 default: 6053 return new ARMleTargetInfo(Triple); 6054 } 6055 6056 case llvm::Triple::armeb: 6057 case llvm::Triple::thumbeb: 6058 if (Triple.isOSDarwin()) 6059 return new DarwinARMTargetInfo(Triple); 6060 6061 switch (os) { 6062 case llvm::Triple::Linux: 6063 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 6064 case llvm::Triple::FreeBSD: 6065 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 6066 case llvm::Triple::NetBSD: 6067 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 6068 case llvm::Triple::OpenBSD: 6069 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 6070 case llvm::Triple::Bitrig: 6071 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 6072 case llvm::Triple::RTEMS: 6073 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 6074 case llvm::Triple::NaCl: 6075 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 6076 default: 6077 return new ARMbeTargetInfo(Triple); 6078 } 6079 6080 case llvm::Triple::msp430: 6081 return new MSP430TargetInfo(Triple); 6082 6083 case llvm::Triple::mips: 6084 switch (os) { 6085 case llvm::Triple::Linux: 6086 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 6087 case llvm::Triple::RTEMS: 6088 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 6089 case llvm::Triple::FreeBSD: 6090 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6091 case llvm::Triple::NetBSD: 6092 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6093 default: 6094 return new Mips32EBTargetInfo(Triple); 6095 } 6096 6097 case llvm::Triple::mipsel: 6098 switch (os) { 6099 case llvm::Triple::Linux: 6100 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 6101 case llvm::Triple::RTEMS: 6102 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 6103 case llvm::Triple::FreeBSD: 6104 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6105 case llvm::Triple::NetBSD: 6106 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6107 case llvm::Triple::NaCl: 6108 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 6109 default: 6110 return new Mips32ELTargetInfo(Triple); 6111 } 6112 6113 case llvm::Triple::mips64: 6114 switch (os) { 6115 case llvm::Triple::Linux: 6116 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 6117 case llvm::Triple::RTEMS: 6118 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 6119 case llvm::Triple::FreeBSD: 6120 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6121 case llvm::Triple::NetBSD: 6122 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6123 case llvm::Triple::OpenBSD: 6124 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6125 default: 6126 return new Mips64EBTargetInfo(Triple); 6127 } 6128 6129 case llvm::Triple::mips64el: 6130 switch (os) { 6131 case llvm::Triple::Linux: 6132 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 6133 case llvm::Triple::RTEMS: 6134 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 6135 case llvm::Triple::FreeBSD: 6136 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6137 case llvm::Triple::NetBSD: 6138 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6139 case llvm::Triple::OpenBSD: 6140 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6141 default: 6142 return new Mips64ELTargetInfo(Triple); 6143 } 6144 6145 case llvm::Triple::le32: 6146 switch (os) { 6147 case llvm::Triple::NaCl: 6148 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 6149 default: 6150 return nullptr; 6151 } 6152 6153 case llvm::Triple::ppc: 6154 if (Triple.isOSDarwin()) 6155 return new DarwinPPC32TargetInfo(Triple); 6156 switch (os) { 6157 case llvm::Triple::Linux: 6158 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 6159 case llvm::Triple::FreeBSD: 6160 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 6161 case llvm::Triple::NetBSD: 6162 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 6163 case llvm::Triple::OpenBSD: 6164 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 6165 case llvm::Triple::RTEMS: 6166 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 6167 default: 6168 return new PPC32TargetInfo(Triple); 6169 } 6170 6171 case llvm::Triple::ppc64: 6172 if (Triple.isOSDarwin()) 6173 return new DarwinPPC64TargetInfo(Triple); 6174 switch (os) { 6175 case llvm::Triple::Linux: 6176 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6177 case llvm::Triple::Lv2: 6178 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 6179 case llvm::Triple::FreeBSD: 6180 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 6181 case llvm::Triple::NetBSD: 6182 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 6183 default: 6184 return new PPC64TargetInfo(Triple); 6185 } 6186 6187 case llvm::Triple::ppc64le: 6188 switch (os) { 6189 case llvm::Triple::Linux: 6190 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6191 default: 6192 return new PPC64TargetInfo(Triple); 6193 } 6194 6195 case llvm::Triple::nvptx: 6196 return new NVPTX32TargetInfo(Triple); 6197 case llvm::Triple::nvptx64: 6198 return new NVPTX64TargetInfo(Triple); 6199 6200 case llvm::Triple::r600: 6201 return new R600TargetInfo(Triple); 6202 6203 case llvm::Triple::sparc: 6204 switch (os) { 6205 case llvm::Triple::Linux: 6206 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 6207 case llvm::Triple::AuroraUX: 6208 return new AuroraUXSparcV8TargetInfo(Triple); 6209 case llvm::Triple::Solaris: 6210 return new SolarisSparcV8TargetInfo(Triple); 6211 case llvm::Triple::NetBSD: 6212 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 6213 case llvm::Triple::OpenBSD: 6214 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 6215 case llvm::Triple::RTEMS: 6216 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 6217 default: 6218 return new SparcV8TargetInfo(Triple); 6219 } 6220 6221 case llvm::Triple::sparcv9: 6222 switch (os) { 6223 case llvm::Triple::Linux: 6224 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 6225 case llvm::Triple::AuroraUX: 6226 return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple); 6227 case llvm::Triple::Solaris: 6228 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 6229 case llvm::Triple::NetBSD: 6230 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 6231 case llvm::Triple::OpenBSD: 6232 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 6233 case llvm::Triple::FreeBSD: 6234 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 6235 default: 6236 return new SparcV9TargetInfo(Triple); 6237 } 6238 6239 case llvm::Triple::systemz: 6240 switch (os) { 6241 case llvm::Triple::Linux: 6242 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 6243 default: 6244 return new SystemZTargetInfo(Triple); 6245 } 6246 6247 case llvm::Triple::tce: 6248 return new TCETargetInfo(Triple); 6249 6250 case llvm::Triple::x86: 6251 if (Triple.isOSDarwin()) 6252 return new DarwinI386TargetInfo(Triple); 6253 6254 switch (os) { 6255 case llvm::Triple::AuroraUX: 6256 return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple); 6257 case llvm::Triple::Linux: 6258 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 6259 case llvm::Triple::DragonFly: 6260 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 6261 case llvm::Triple::NetBSD: 6262 return new NetBSDI386TargetInfo(Triple); 6263 case llvm::Triple::OpenBSD: 6264 return new OpenBSDI386TargetInfo(Triple); 6265 case llvm::Triple::Bitrig: 6266 return new BitrigI386TargetInfo(Triple); 6267 case llvm::Triple::FreeBSD: 6268 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 6269 case llvm::Triple::KFreeBSD: 6270 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 6271 case llvm::Triple::Minix: 6272 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 6273 case llvm::Triple::Solaris: 6274 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 6275 case llvm::Triple::Win32: { 6276 switch (Triple.getEnvironment()) { 6277 default: 6278 return new X86_32TargetInfo(Triple); 6279 case llvm::Triple::Cygnus: 6280 return new CygwinX86_32TargetInfo(Triple); 6281 case llvm::Triple::GNU: 6282 return new MinGWX86_32TargetInfo(Triple); 6283 case llvm::Triple::MSVC: 6284 return new MicrosoftX86_32TargetInfo(Triple); 6285 } 6286 } 6287 case llvm::Triple::Haiku: 6288 return new HaikuX86_32TargetInfo(Triple); 6289 case llvm::Triple::RTEMS: 6290 return new RTEMSX86_32TargetInfo(Triple); 6291 case llvm::Triple::NaCl: 6292 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 6293 default: 6294 return new X86_32TargetInfo(Triple); 6295 } 6296 6297 case llvm::Triple::x86_64: 6298 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 6299 return new DarwinX86_64TargetInfo(Triple); 6300 6301 switch (os) { 6302 case llvm::Triple::AuroraUX: 6303 return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple); 6304 case llvm::Triple::Linux: 6305 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 6306 case llvm::Triple::DragonFly: 6307 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 6308 case llvm::Triple::NetBSD: 6309 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 6310 case llvm::Triple::OpenBSD: 6311 return new OpenBSDX86_64TargetInfo(Triple); 6312 case llvm::Triple::Bitrig: 6313 return new BitrigX86_64TargetInfo(Triple); 6314 case llvm::Triple::FreeBSD: 6315 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 6316 case llvm::Triple::KFreeBSD: 6317 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 6318 case llvm::Triple::Solaris: 6319 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 6320 case llvm::Triple::Win32: { 6321 switch (Triple.getEnvironment()) { 6322 default: 6323 return new X86_64TargetInfo(Triple); 6324 case llvm::Triple::GNU: 6325 return new MinGWX86_64TargetInfo(Triple); 6326 case llvm::Triple::MSVC: 6327 return new MicrosoftX86_64TargetInfo(Triple); 6328 } 6329 } 6330 case llvm::Triple::NaCl: 6331 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 6332 default: 6333 return new X86_64TargetInfo(Triple); 6334 } 6335 6336 case llvm::Triple::spir: { 6337 if (Triple.getOS() != llvm::Triple::UnknownOS || 6338 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 6339 return nullptr; 6340 return new SPIR32TargetInfo(Triple); 6341 } 6342 case llvm::Triple::spir64: { 6343 if (Triple.getOS() != llvm::Triple::UnknownOS || 6344 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 6345 return nullptr; 6346 return new SPIR64TargetInfo(Triple); 6347 } 6348 } 6349 } 6350 6351 /// CreateTargetInfo - Return the target info object for the specified target 6352 /// triple. 6353 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 6354 TargetOptions *Opts) { 6355 llvm::Triple Triple(Opts->Triple); 6356 6357 // Construct the target 6358 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 6359 if (!Target) { 6360 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 6361 return nullptr; 6362 } 6363 Target->setTargetOpts(Opts); 6364 6365 // Set the target CPU if specified. 6366 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 6367 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 6368 return nullptr; 6369 } 6370 6371 // Set the target ABI if specified. 6372 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 6373 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 6374 return nullptr; 6375 } 6376 6377 // Set the fp math unit. 6378 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 6379 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 6380 return nullptr; 6381 } 6382 6383 // Compute the default target features, we need the target to handle this 6384 // because features may have dependencies on one another. 6385 llvm::StringMap<bool> Features; 6386 Target->getDefaultFeatures(Features); 6387 6388 // Apply the user specified deltas. 6389 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 6390 I < N; ++I) { 6391 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 6392 // Apply the feature via the target. 6393 bool Enabled = Name[0] == '+'; 6394 Target->setFeatureEnabled(Features, Name + 1, Enabled); 6395 } 6396 6397 // Add the features to the compile options. 6398 // 6399 // FIXME: If we are completely confident that we have the right set, we only 6400 // need to pass the minuses. 6401 Opts->Features.clear(); 6402 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 6403 ie = Features.end(); it != ie; ++it) 6404 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 6405 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 6406 return nullptr; 6407 6408 return Target.release(); 6409 } 6410