1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include <algorithm> 31 #include <memory> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 77 void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const override { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "6000"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 94 // AddressSanitizer doesn't play well with source fortification, which is on 95 // by default on Darwin. 96 if (Opts.Sanitize.has(SanitizerKind::Address)) 97 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 98 99 if (!Opts.ObjCAutoRefCount) { 100 // __weak is always defined, for use in blocks and with objc pointers. 101 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 102 103 // Darwin defines __strong even in C mode (just to nothing). 104 if (Opts.getGC() != LangOptions::NonGC) 105 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 106 else 107 Builder.defineMacro("__strong", ""); 108 109 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 110 // allow this in C, since one might have block pointers in structs that 111 // are used in pure C code and in Objective-C ARC. 112 Builder.defineMacro("__unsafe_unretained", ""); 113 } 114 115 if (Opts.Static) 116 Builder.defineMacro("__STATIC__"); 117 else 118 Builder.defineMacro("__DYNAMIC__"); 119 120 if (Opts.POSIXThreads) 121 Builder.defineMacro("_REENTRANT"); 122 123 // Get the platform type and version number from the triple. 124 unsigned Maj, Min, Rev; 125 if (Triple.isMacOSX()) { 126 Triple.getMacOSXVersion(Maj, Min, Rev); 127 PlatformName = "macosx"; 128 } else { 129 Triple.getOSVersion(Maj, Min, Rev); 130 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 131 } 132 133 // If -target arch-pc-win32-macho option specified, we're 134 // generating code for Win32 ABI. No need to emit 135 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 136 if (PlatformName == "win32") { 137 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 138 return; 139 } 140 141 // Set the appropriate OS version define. 142 if (Triple.isiOS()) { 143 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 144 char Str[6]; 145 Str[0] = '0' + Maj; 146 Str[1] = '0' + (Min / 10); 147 Str[2] = '0' + (Min % 10); 148 Str[3] = '0' + (Rev / 10); 149 Str[4] = '0' + (Rev % 10); 150 Str[5] = '\0'; 151 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 152 Str); 153 } else if (Triple.isMacOSX()) { 154 // Note that the Driver allows versions which aren't representable in the 155 // define (because we only get a single digit for the minor and micro 156 // revision numbers). So, we limit them to the maximum representable 157 // version. 158 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 159 char Str[7]; 160 if (Maj < 10 || (Maj == 10 && Min < 10)) { 161 Str[0] = '0' + (Maj / 10); 162 Str[1] = '0' + (Maj % 10); 163 Str[2] = '0' + std::min(Min, 9U); 164 Str[3] = '0' + std::min(Rev, 9U); 165 Str[4] = '\0'; 166 } else { 167 // Handle versions > 10.9. 168 Str[0] = '0' + (Maj / 10); 169 Str[1] = '0' + (Maj % 10); 170 Str[2] = '0' + (Min / 10); 171 Str[3] = '0' + (Min % 10); 172 Str[4] = '0' + (Rev / 10); 173 Str[5] = '0' + (Rev % 10); 174 Str[6] = '\0'; 175 } 176 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 177 } 178 179 // Tell users about the kernel if there is one. 180 if (Triple.isOSDarwin()) 181 Builder.defineMacro("__MACH__"); 182 183 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 184 } 185 186 namespace { 187 // CloudABI Target 188 template <typename Target> 189 class CloudABITargetInfo : public OSTargetInfo<Target> { 190 protected: 191 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 192 MacroBuilder &Builder) const override { 193 Builder.defineMacro("__CloudABI__"); 194 Builder.defineMacro("__ELF__"); 195 196 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 197 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 198 Builder.defineMacro("__STDC_UTF_16__"); 199 Builder.defineMacro("__STDC_UTF_32__"); 200 } 201 202 public: 203 CloudABITargetInfo(const llvm::Triple &Triple) 204 : OSTargetInfo<Target>(Triple) { 205 this->UserLabelPrefix = ""; 206 } 207 }; 208 209 template<typename Target> 210 class DarwinTargetInfo : public OSTargetInfo<Target> { 211 protected: 212 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 213 MacroBuilder &Builder) const override { 214 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 215 this->PlatformMinVersion); 216 } 217 218 public: 219 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 220 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 221 this->MCountName = "\01mcount"; 222 } 223 224 std::string isValidSectionSpecifier(StringRef SR) const override { 225 // Let MCSectionMachO validate this. 226 StringRef Segment, Section; 227 unsigned TAA, StubSize; 228 bool HasTAA; 229 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 230 TAA, HasTAA, StubSize); 231 } 232 233 const char *getStaticInitSectionSpecifier() const override { 234 // FIXME: We should return 0 when building kexts. 235 return "__TEXT,__StaticInit,regular,pure_instructions"; 236 } 237 238 /// Darwin does not support protected visibility. Darwin's "default" 239 /// is very similar to ELF's "protected"; Darwin requires a "weak" 240 /// attribute on declarations that can be dynamically replaced. 241 bool hasProtectedVisibility() const override { 242 return false; 243 } 244 }; 245 246 247 // DragonFlyBSD Target 248 template<typename Target> 249 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 250 protected: 251 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 252 MacroBuilder &Builder) const override { 253 // DragonFly defines; list based off of gcc output 254 Builder.defineMacro("__DragonFly__"); 255 Builder.defineMacro("__DragonFly_cc_version", "100001"); 256 Builder.defineMacro("__ELF__"); 257 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 258 Builder.defineMacro("__tune_i386__"); 259 DefineStd(Builder, "unix", Opts); 260 } 261 public: 262 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 263 : OSTargetInfo<Target>(Triple) { 264 this->UserLabelPrefix = ""; 265 266 switch (Triple.getArch()) { 267 default: 268 case llvm::Triple::x86: 269 case llvm::Triple::x86_64: 270 this->MCountName = ".mcount"; 271 break; 272 } 273 } 274 }; 275 276 // FreeBSD Target 277 template<typename Target> 278 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 279 protected: 280 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 281 MacroBuilder &Builder) const override { 282 // FreeBSD defines; list based off of gcc output 283 284 unsigned Release = Triple.getOSMajorVersion(); 285 if (Release == 0U) 286 Release = 8; 287 288 Builder.defineMacro("__FreeBSD__", Twine(Release)); 289 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 290 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 291 DefineStd(Builder, "unix", Opts); 292 Builder.defineMacro("__ELF__"); 293 294 // On FreeBSD, wchar_t contains the number of the code point as 295 // used by the character set of the locale. These character sets are 296 // not necessarily a superset of ASCII. 297 // 298 // FIXME: This is wrong; the macro refers to the numerical values 299 // of wchar_t *literals*, which are not locale-dependent. However, 300 // FreeBSD systems apparently depend on us getting this wrong, and 301 // setting this to 1 is conforming even if all the basic source 302 // character literals have the same encoding as char and wchar_t. 303 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 304 } 305 public: 306 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 307 this->UserLabelPrefix = ""; 308 309 switch (Triple.getArch()) { 310 default: 311 case llvm::Triple::x86: 312 case llvm::Triple::x86_64: 313 this->MCountName = ".mcount"; 314 break; 315 case llvm::Triple::mips: 316 case llvm::Triple::mipsel: 317 case llvm::Triple::ppc: 318 case llvm::Triple::ppc64: 319 case llvm::Triple::ppc64le: 320 this->MCountName = "_mcount"; 321 break; 322 case llvm::Triple::arm: 323 this->MCountName = "__mcount"; 324 break; 325 } 326 } 327 }; 328 329 // GNU/kFreeBSD Target 330 template<typename Target> 331 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 332 protected: 333 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 334 MacroBuilder &Builder) const override { 335 // GNU/kFreeBSD defines; list based off of gcc output 336 337 DefineStd(Builder, "unix", Opts); 338 Builder.defineMacro("__FreeBSD_kernel__"); 339 Builder.defineMacro("__GLIBC__"); 340 Builder.defineMacro("__ELF__"); 341 if (Opts.POSIXThreads) 342 Builder.defineMacro("_REENTRANT"); 343 if (Opts.CPlusPlus) 344 Builder.defineMacro("_GNU_SOURCE"); 345 } 346 public: 347 KFreeBSDTargetInfo(const llvm::Triple &Triple) 348 : OSTargetInfo<Target>(Triple) { 349 this->UserLabelPrefix = ""; 350 } 351 }; 352 353 // Minix Target 354 template<typename Target> 355 class MinixTargetInfo : public OSTargetInfo<Target> { 356 protected: 357 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 358 MacroBuilder &Builder) const override { 359 // Minix defines 360 361 Builder.defineMacro("__minix", "3"); 362 Builder.defineMacro("_EM_WSIZE", "4"); 363 Builder.defineMacro("_EM_PSIZE", "4"); 364 Builder.defineMacro("_EM_SSIZE", "2"); 365 Builder.defineMacro("_EM_LSIZE", "4"); 366 Builder.defineMacro("_EM_FSIZE", "4"); 367 Builder.defineMacro("_EM_DSIZE", "8"); 368 Builder.defineMacro("__ELF__"); 369 DefineStd(Builder, "unix", Opts); 370 } 371 public: 372 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 373 this->UserLabelPrefix = ""; 374 } 375 }; 376 377 // Linux target 378 template<typename Target> 379 class LinuxTargetInfo : public OSTargetInfo<Target> { 380 protected: 381 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 382 MacroBuilder &Builder) const override { 383 // Linux defines; list based off of gcc output 384 DefineStd(Builder, "unix", Opts); 385 DefineStd(Builder, "linux", Opts); 386 Builder.defineMacro("__gnu_linux__"); 387 Builder.defineMacro("__ELF__"); 388 if (Triple.getEnvironment() == llvm::Triple::Android) { 389 Builder.defineMacro("__ANDROID__", "1"); 390 unsigned Maj, Min, Rev; 391 Triple.getOSVersion(Maj, Min, Rev); 392 this->PlatformName = "android"; 393 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 394 } 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 if (Opts.CPlusPlus) 398 Builder.defineMacro("_GNU_SOURCE"); 399 } 400 public: 401 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 402 this->UserLabelPrefix = ""; 403 this->WIntType = TargetInfo::UnsignedInt; 404 405 switch (Triple.getArch()) { 406 default: 407 break; 408 case llvm::Triple::ppc: 409 case llvm::Triple::ppc64: 410 case llvm::Triple::ppc64le: 411 this->MCountName = "_mcount"; 412 break; 413 } 414 } 415 416 const char *getStaticInitSectionSpecifier() const override { 417 return ".text.startup"; 418 } 419 }; 420 421 // NetBSD Target 422 template<typename Target> 423 class NetBSDTargetInfo : public OSTargetInfo<Target> { 424 protected: 425 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 426 MacroBuilder &Builder) const override { 427 // NetBSD defines; list based off of gcc output 428 Builder.defineMacro("__NetBSD__"); 429 Builder.defineMacro("__unix__"); 430 Builder.defineMacro("__ELF__"); 431 if (Opts.POSIXThreads) 432 Builder.defineMacro("_POSIX_THREADS"); 433 434 switch (Triple.getArch()) { 435 default: 436 break; 437 case llvm::Triple::arm: 438 case llvm::Triple::armeb: 439 case llvm::Triple::thumb: 440 case llvm::Triple::thumbeb: 441 Builder.defineMacro("__ARM_DWARF_EH__"); 442 break; 443 } 444 } 445 public: 446 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 447 this->UserLabelPrefix = ""; 448 this->MCountName = "_mcount"; 449 } 450 }; 451 452 // OpenBSD Target 453 template<typename Target> 454 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 455 protected: 456 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 457 MacroBuilder &Builder) const override { 458 // OpenBSD defines; list based off of gcc output 459 460 Builder.defineMacro("__OpenBSD__"); 461 DefineStd(Builder, "unix", Opts); 462 Builder.defineMacro("__ELF__"); 463 if (Opts.POSIXThreads) 464 Builder.defineMacro("_REENTRANT"); 465 } 466 public: 467 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 468 this->UserLabelPrefix = ""; 469 this->TLSSupported = false; 470 471 switch (Triple.getArch()) { 472 default: 473 case llvm::Triple::x86: 474 case llvm::Triple::x86_64: 475 case llvm::Triple::arm: 476 case llvm::Triple::sparc: 477 this->MCountName = "__mcount"; 478 break; 479 case llvm::Triple::mips64: 480 case llvm::Triple::mips64el: 481 case llvm::Triple::ppc: 482 case llvm::Triple::sparcv9: 483 this->MCountName = "_mcount"; 484 break; 485 } 486 } 487 }; 488 489 // Bitrig Target 490 template<typename Target> 491 class BitrigTargetInfo : public OSTargetInfo<Target> { 492 protected: 493 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 494 MacroBuilder &Builder) const override { 495 // Bitrig defines; list based off of gcc output 496 497 Builder.defineMacro("__Bitrig__"); 498 DefineStd(Builder, "unix", Opts); 499 Builder.defineMacro("__ELF__"); 500 if (Opts.POSIXThreads) 501 Builder.defineMacro("_REENTRANT"); 502 503 switch (Triple.getArch()) { 504 default: 505 break; 506 case llvm::Triple::arm: 507 case llvm::Triple::armeb: 508 case llvm::Triple::thumb: 509 case llvm::Triple::thumbeb: 510 Builder.defineMacro("__ARM_DWARF_EH__"); 511 break; 512 } 513 } 514 public: 515 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 516 this->UserLabelPrefix = ""; 517 this->MCountName = "__mcount"; 518 } 519 }; 520 521 // PSP Target 522 template<typename Target> 523 class PSPTargetInfo : public OSTargetInfo<Target> { 524 protected: 525 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 526 MacroBuilder &Builder) const override { 527 // PSP defines; list based on the output of the pspdev gcc toolchain. 528 Builder.defineMacro("PSP"); 529 Builder.defineMacro("_PSP"); 530 Builder.defineMacro("__psp__"); 531 Builder.defineMacro("__ELF__"); 532 } 533 public: 534 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 535 this->UserLabelPrefix = ""; 536 } 537 }; 538 539 // PS3 PPU Target 540 template<typename Target> 541 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 542 protected: 543 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 544 MacroBuilder &Builder) const override { 545 // PS3 PPU defines. 546 Builder.defineMacro("__PPC__"); 547 Builder.defineMacro("__PPU__"); 548 Builder.defineMacro("__CELLOS_LV2__"); 549 Builder.defineMacro("__ELF__"); 550 Builder.defineMacro("__LP32__"); 551 Builder.defineMacro("_ARCH_PPC64"); 552 Builder.defineMacro("__powerpc64__"); 553 } 554 public: 555 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 556 this->UserLabelPrefix = ""; 557 this->LongWidth = this->LongAlign = 32; 558 this->PointerWidth = this->PointerAlign = 32; 559 this->IntMaxType = TargetInfo::SignedLongLong; 560 this->Int64Type = TargetInfo::SignedLongLong; 561 this->SizeType = TargetInfo::UnsignedInt; 562 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64"; 563 } 564 }; 565 566 template <typename Target> 567 class PS4OSTargetInfo : public OSTargetInfo<Target> { 568 protected: 569 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 570 MacroBuilder &Builder) const override { 571 Builder.defineMacro("__FreeBSD__", "9"); 572 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 573 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 574 DefineStd(Builder, "unix", Opts); 575 Builder.defineMacro("__ELF__"); 576 Builder.defineMacro("__PS4__"); 577 } 578 public: 579 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 580 this->WCharType = this->UnsignedShort; 581 582 this->UserLabelPrefix = ""; 583 584 switch (Triple.getArch()) { 585 default: 586 case llvm::Triple::x86_64: 587 this->MCountName = ".mcount"; 588 break; 589 } 590 } 591 }; 592 593 // Solaris target 594 template<typename Target> 595 class SolarisTargetInfo : public OSTargetInfo<Target> { 596 protected: 597 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 598 MacroBuilder &Builder) const override { 599 DefineStd(Builder, "sun", Opts); 600 DefineStd(Builder, "unix", Opts); 601 Builder.defineMacro("__ELF__"); 602 Builder.defineMacro("__svr4__"); 603 Builder.defineMacro("__SVR4"); 604 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 605 // newer, but to 500 for everything else. feature_test.h has a check to 606 // ensure that you are not using C99 with an old version of X/Open or C89 607 // with a new version. 608 if (Opts.C99) 609 Builder.defineMacro("_XOPEN_SOURCE", "600"); 610 else 611 Builder.defineMacro("_XOPEN_SOURCE", "500"); 612 if (Opts.CPlusPlus) 613 Builder.defineMacro("__C99FEATURES__"); 614 Builder.defineMacro("_LARGEFILE_SOURCE"); 615 Builder.defineMacro("_LARGEFILE64_SOURCE"); 616 Builder.defineMacro("__EXTENSIONS__"); 617 Builder.defineMacro("_REENTRANT"); 618 } 619 public: 620 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 621 this->UserLabelPrefix = ""; 622 this->WCharType = this->SignedInt; 623 // FIXME: WIntType should be SignedLong 624 } 625 }; 626 627 // Windows target 628 template<typename Target> 629 class WindowsTargetInfo : public OSTargetInfo<Target> { 630 protected: 631 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 632 MacroBuilder &Builder) const override { 633 Builder.defineMacro("_WIN32"); 634 } 635 void getVisualStudioDefines(const LangOptions &Opts, 636 MacroBuilder &Builder) const { 637 if (Opts.CPlusPlus) { 638 if (Opts.RTTIData) 639 Builder.defineMacro("_CPPRTTI"); 640 641 if (Opts.CXXExceptions) 642 Builder.defineMacro("_CPPUNWIND"); 643 } 644 645 if (!Opts.CharIsSigned) 646 Builder.defineMacro("_CHAR_UNSIGNED"); 647 648 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 649 // but it works for now. 650 if (Opts.POSIXThreads) 651 Builder.defineMacro("_MT"); 652 653 if (Opts.MSCompatibilityVersion) { 654 Builder.defineMacro("_MSC_VER", 655 Twine(Opts.MSCompatibilityVersion / 100000)); 656 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 657 // FIXME We cannot encode the revision information into 32-bits 658 Builder.defineMacro("_MSC_BUILD", Twine(1)); 659 660 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(19)) 661 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 662 } 663 664 if (Opts.MicrosoftExt) { 665 Builder.defineMacro("_MSC_EXTENSIONS"); 666 667 if (Opts.CPlusPlus11) { 668 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 669 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 670 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 671 } 672 } 673 674 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 675 } 676 677 public: 678 WindowsTargetInfo(const llvm::Triple &Triple) 679 : OSTargetInfo<Target>(Triple) {} 680 }; 681 682 template <typename Target> 683 class NaClTargetInfo : public OSTargetInfo<Target> { 684 protected: 685 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 686 MacroBuilder &Builder) const override { 687 if (Opts.POSIXThreads) 688 Builder.defineMacro("_REENTRANT"); 689 if (Opts.CPlusPlus) 690 Builder.defineMacro("_GNU_SOURCE"); 691 692 DefineStd(Builder, "unix", Opts); 693 Builder.defineMacro("__ELF__"); 694 Builder.defineMacro("__native_client__"); 695 } 696 697 public: 698 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 699 this->UserLabelPrefix = ""; 700 this->LongAlign = 32; 701 this->LongWidth = 32; 702 this->PointerAlign = 32; 703 this->PointerWidth = 32; 704 this->IntMaxType = TargetInfo::SignedLongLong; 705 this->Int64Type = TargetInfo::SignedLongLong; 706 this->DoubleAlign = 64; 707 this->LongDoubleWidth = 64; 708 this->LongDoubleAlign = 64; 709 this->LongLongWidth = 64; 710 this->LongLongAlign = 64; 711 this->SizeType = TargetInfo::UnsignedInt; 712 this->PtrDiffType = TargetInfo::SignedInt; 713 this->IntPtrType = TargetInfo::SignedInt; 714 // RegParmMax is inherited from the underlying architecture 715 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 716 if (Triple.getArch() == llvm::Triple::arm) { 717 // Handled in ARM's setABI(). 718 } else if (Triple.getArch() == llvm::Triple::x86) { 719 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 720 } else if (Triple.getArch() == llvm::Triple::x86_64) { 721 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 722 } else if (Triple.getArch() == llvm::Triple::mipsel) { 723 // Handled on mips' setDescriptionString. 724 } else { 725 assert(Triple.getArch() == llvm::Triple::le32); 726 this->DescriptionString = "e-p:32:32-i64:64"; 727 } 728 } 729 }; 730 731 //===----------------------------------------------------------------------===// 732 // Specific target implementations. 733 //===----------------------------------------------------------------------===// 734 735 // PPC abstract base class 736 class PPCTargetInfo : public TargetInfo { 737 static const Builtin::Info BuiltinInfo[]; 738 static const char * const GCCRegNames[]; 739 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 740 std::string CPU; 741 742 // Target cpu features. 743 bool HasVSX; 744 bool HasP8Vector; 745 bool HasP8Crypto; 746 bool HasDirectMove; 747 bool HasQPX; 748 bool HasHTM; 749 bool HasBPERMD; 750 bool HasExtDiv; 751 752 protected: 753 std::string ABI; 754 755 public: 756 PPCTargetInfo(const llvm::Triple &Triple) 757 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 758 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 759 HasBPERMD(false), HasExtDiv(false) { 760 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 761 LongDoubleWidth = LongDoubleAlign = 128; 762 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 763 } 764 765 /// \brief Flags for architecture specific defines. 766 typedef enum { 767 ArchDefineNone = 0, 768 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 769 ArchDefinePpcgr = 1 << 1, 770 ArchDefinePpcsq = 1 << 2, 771 ArchDefine440 = 1 << 3, 772 ArchDefine603 = 1 << 4, 773 ArchDefine604 = 1 << 5, 774 ArchDefinePwr4 = 1 << 6, 775 ArchDefinePwr5 = 1 << 7, 776 ArchDefinePwr5x = 1 << 8, 777 ArchDefinePwr6 = 1 << 9, 778 ArchDefinePwr6x = 1 << 10, 779 ArchDefinePwr7 = 1 << 11, 780 ArchDefinePwr8 = 1 << 12, 781 ArchDefineA2 = 1 << 13, 782 ArchDefineA2q = 1 << 14 783 } ArchDefineTypes; 784 785 // Note: GCC recognizes the following additional cpus: 786 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 787 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 788 // titan, rs64. 789 bool setCPU(const std::string &Name) override { 790 bool CPUKnown = llvm::StringSwitch<bool>(Name) 791 .Case("generic", true) 792 .Case("440", true) 793 .Case("450", true) 794 .Case("601", true) 795 .Case("602", true) 796 .Case("603", true) 797 .Case("603e", true) 798 .Case("603ev", true) 799 .Case("604", true) 800 .Case("604e", true) 801 .Case("620", true) 802 .Case("630", true) 803 .Case("g3", true) 804 .Case("7400", true) 805 .Case("g4", true) 806 .Case("7450", true) 807 .Case("g4+", true) 808 .Case("750", true) 809 .Case("970", true) 810 .Case("g5", true) 811 .Case("a2", true) 812 .Case("a2q", true) 813 .Case("e500mc", true) 814 .Case("e5500", true) 815 .Case("power3", true) 816 .Case("pwr3", true) 817 .Case("power4", true) 818 .Case("pwr4", true) 819 .Case("power5", true) 820 .Case("pwr5", true) 821 .Case("power5x", true) 822 .Case("pwr5x", true) 823 .Case("power6", true) 824 .Case("pwr6", true) 825 .Case("power6x", true) 826 .Case("pwr6x", true) 827 .Case("power7", true) 828 .Case("pwr7", true) 829 .Case("power8", true) 830 .Case("pwr8", true) 831 .Case("powerpc", true) 832 .Case("ppc", true) 833 .Case("powerpc64", true) 834 .Case("ppc64", true) 835 .Case("powerpc64le", true) 836 .Case("ppc64le", true) 837 .Default(false); 838 839 if (CPUKnown) 840 CPU = Name; 841 842 return CPUKnown; 843 } 844 845 846 StringRef getABI() const override { return ABI; } 847 848 void getTargetBuiltins(const Builtin::Info *&Records, 849 unsigned &NumRecords) const override { 850 Records = BuiltinInfo; 851 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 852 } 853 854 bool isCLZForZeroUndef() const override { return false; } 855 856 void getTargetDefines(const LangOptions &Opts, 857 MacroBuilder &Builder) const override; 858 859 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 860 861 bool handleTargetFeatures(std::vector<std::string> &Features, 862 DiagnosticsEngine &Diags) override; 863 bool hasFeature(StringRef Feature) const override; 864 865 void getGCCRegNames(const char * const *&Names, 866 unsigned &NumNames) const override; 867 void getGCCRegAliases(const GCCRegAlias *&Aliases, 868 unsigned &NumAliases) const override; 869 bool validateAsmConstraint(const char *&Name, 870 TargetInfo::ConstraintInfo &Info) const override { 871 switch (*Name) { 872 default: return false; 873 case 'O': // Zero 874 break; 875 case 'b': // Base register 876 case 'f': // Floating point register 877 Info.setAllowsRegister(); 878 break; 879 // FIXME: The following are added to allow parsing. 880 // I just took a guess at what the actions should be. 881 // Also, is more specific checking needed? I.e. specific registers? 882 case 'd': // Floating point register (containing 64-bit value) 883 case 'v': // Altivec vector register 884 Info.setAllowsRegister(); 885 break; 886 case 'w': 887 switch (Name[1]) { 888 case 'd':// VSX vector register to hold vector double data 889 case 'f':// VSX vector register to hold vector float data 890 case 's':// VSX vector register to hold scalar float data 891 case 'a':// Any VSX register 892 case 'c':// An individual CR bit 893 break; 894 default: 895 return false; 896 } 897 Info.setAllowsRegister(); 898 Name++; // Skip over 'w'. 899 break; 900 case 'h': // `MQ', `CTR', or `LINK' register 901 case 'q': // `MQ' register 902 case 'c': // `CTR' register 903 case 'l': // `LINK' register 904 case 'x': // `CR' register (condition register) number 0 905 case 'y': // `CR' register (condition register) 906 case 'z': // `XER[CA]' carry bit (part of the XER register) 907 Info.setAllowsRegister(); 908 break; 909 case 'I': // Signed 16-bit constant 910 case 'J': // Unsigned 16-bit constant shifted left 16 bits 911 // (use `L' instead for SImode constants) 912 case 'K': // Unsigned 16-bit constant 913 case 'L': // Signed 16-bit constant shifted left 16 bits 914 case 'M': // Constant larger than 31 915 case 'N': // Exact power of 2 916 case 'P': // Constant whose negation is a signed 16-bit constant 917 case 'G': // Floating point constant that can be loaded into a 918 // register with one instruction per word 919 case 'H': // Integer/Floating point constant that can be loaded 920 // into a register using three instructions 921 break; 922 case 'm': // Memory operand. Note that on PowerPC targets, m can 923 // include addresses that update the base register. It 924 // is therefore only safe to use `m' in an asm statement 925 // if that asm statement accesses the operand exactly once. 926 // The asm statement must also use `%U<opno>' as a 927 // placeholder for the "update" flag in the corresponding 928 // load or store instruction. For example: 929 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 930 // is correct but: 931 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 932 // is not. Use es rather than m if you don't want the base 933 // register to be updated. 934 case 'e': 935 if (Name[1] != 's') 936 return false; 937 // es: A "stable" memory operand; that is, one which does not 938 // include any automodification of the base register. Unlike 939 // `m', this constraint can be used in asm statements that 940 // might access the operand several times, or that might not 941 // access it at all. 942 Info.setAllowsMemory(); 943 Name++; // Skip over 'e'. 944 break; 945 case 'Q': // Memory operand that is an offset from a register (it is 946 // usually better to use `m' or `es' in asm statements) 947 case 'Z': // Memory operand that is an indexed or indirect from a 948 // register (it is usually better to use `m' or `es' in 949 // asm statements) 950 Info.setAllowsMemory(); 951 Info.setAllowsRegister(); 952 break; 953 case 'R': // AIX TOC entry 954 case 'a': // Address operand that is an indexed or indirect from a 955 // register (`p' is preferable for asm statements) 956 case 'S': // Constant suitable as a 64-bit mask operand 957 case 'T': // Constant suitable as a 32-bit mask operand 958 case 'U': // System V Release 4 small data area reference 959 case 't': // AND masks that can be performed by two rldic{l, r} 960 // instructions 961 case 'W': // Vector constant that does not require memory 962 case 'j': // Vector constant that is all zeros. 963 break; 964 // End FIXME. 965 } 966 return true; 967 } 968 std::string convertConstraint(const char *&Constraint) const override { 969 std::string R; 970 switch (*Constraint) { 971 case 'e': 972 case 'w': 973 // Two-character constraint; add "^" hint for later parsing. 974 R = std::string("^") + std::string(Constraint, 2); 975 Constraint++; 976 break; 977 default: 978 return TargetInfo::convertConstraint(Constraint); 979 } 980 return R; 981 } 982 const char *getClobbers() const override { 983 return ""; 984 } 985 int getEHDataRegisterNumber(unsigned RegNo) const override { 986 if (RegNo == 0) return 3; 987 if (RegNo == 1) return 4; 988 return -1; 989 } 990 991 bool hasSjLjLowering() const override { 992 return true; 993 } 994 }; 995 996 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 997 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 998 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 999 ALL_LANGUAGES }, 1000 #include "clang/Basic/BuiltinsPPC.def" 1001 }; 1002 1003 /// handleTargetFeatures - Perform initialization based on the user 1004 /// configured set of features. 1005 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1006 DiagnosticsEngine &Diags) { 1007 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 1008 // Ignore disabled features. 1009 if (Features[i][0] == '-') 1010 continue; 1011 1012 StringRef Feature = StringRef(Features[i]).substr(1); 1013 1014 if (Feature == "vsx") { 1015 HasVSX = true; 1016 continue; 1017 } 1018 1019 if (Feature == "bpermd") { 1020 HasBPERMD = true; 1021 continue; 1022 } 1023 1024 if (Feature == "extdiv") { 1025 HasExtDiv = true; 1026 continue; 1027 } 1028 1029 if (Feature == "power8-vector") { 1030 HasP8Vector = true; 1031 continue; 1032 } 1033 1034 if (Feature == "crypto") { 1035 HasP8Crypto = true; 1036 continue; 1037 } 1038 1039 if (Feature == "direct-move") { 1040 HasDirectMove = true; 1041 continue; 1042 } 1043 1044 if (Feature == "qpx") { 1045 HasQPX = true; 1046 continue; 1047 } 1048 1049 if (Feature == "htm") { 1050 HasHTM = true; 1051 continue; 1052 } 1053 1054 // TODO: Finish this list and add an assert that we've handled them 1055 // all. 1056 } 1057 1058 return true; 1059 } 1060 1061 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1062 /// #defines that are not tied to a specific subtarget. 1063 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1064 MacroBuilder &Builder) const { 1065 // Target identification. 1066 Builder.defineMacro("__ppc__"); 1067 Builder.defineMacro("__PPC__"); 1068 Builder.defineMacro("_ARCH_PPC"); 1069 Builder.defineMacro("__powerpc__"); 1070 Builder.defineMacro("__POWERPC__"); 1071 if (PointerWidth == 64) { 1072 Builder.defineMacro("_ARCH_PPC64"); 1073 Builder.defineMacro("__powerpc64__"); 1074 Builder.defineMacro("__ppc64__"); 1075 Builder.defineMacro("__PPC64__"); 1076 } 1077 1078 // Target properties. 1079 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1080 Builder.defineMacro("_LITTLE_ENDIAN"); 1081 } else { 1082 if (getTriple().getOS() != llvm::Triple::NetBSD && 1083 getTriple().getOS() != llvm::Triple::OpenBSD) 1084 Builder.defineMacro("_BIG_ENDIAN"); 1085 } 1086 1087 // ABI options. 1088 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1089 Builder.defineMacro("_CALL_ELF", "1"); 1090 if (ABI == "elfv2") 1091 Builder.defineMacro("_CALL_ELF", "2"); 1092 1093 // Subtarget options. 1094 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1095 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1096 1097 // FIXME: Should be controlled by command line option. 1098 if (LongDoubleWidth == 128) 1099 Builder.defineMacro("__LONG_DOUBLE_128__"); 1100 1101 if (Opts.AltiVec) { 1102 Builder.defineMacro("__VEC__", "10206"); 1103 Builder.defineMacro("__ALTIVEC__"); 1104 } 1105 1106 // CPU identification. 1107 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1108 .Case("440", ArchDefineName) 1109 .Case("450", ArchDefineName | ArchDefine440) 1110 .Case("601", ArchDefineName) 1111 .Case("602", ArchDefineName | ArchDefinePpcgr) 1112 .Case("603", ArchDefineName | ArchDefinePpcgr) 1113 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1114 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1115 .Case("604", ArchDefineName | ArchDefinePpcgr) 1116 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1117 .Case("620", ArchDefineName | ArchDefinePpcgr) 1118 .Case("630", ArchDefineName | ArchDefinePpcgr) 1119 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1120 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1121 .Case("750", ArchDefineName | ArchDefinePpcgr) 1122 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1123 | ArchDefinePpcsq) 1124 .Case("a2", ArchDefineA2) 1125 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1126 .Case("pwr3", ArchDefinePpcgr) 1127 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1128 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1129 | ArchDefinePpcsq) 1130 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1131 | ArchDefinePpcgr | ArchDefinePpcsq) 1132 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1133 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1134 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1135 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1136 | ArchDefinePpcsq) 1137 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1138 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1139 | ArchDefinePpcgr | ArchDefinePpcsq) 1140 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1141 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1142 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1143 .Case("power3", ArchDefinePpcgr) 1144 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1145 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1146 | ArchDefinePpcsq) 1147 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1148 | ArchDefinePpcgr | ArchDefinePpcsq) 1149 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1150 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1151 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1152 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1153 | ArchDefinePpcsq) 1154 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1155 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1156 | ArchDefinePpcgr | ArchDefinePpcsq) 1157 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1158 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1159 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1160 .Default(ArchDefineNone); 1161 1162 if (defs & ArchDefineName) 1163 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1164 if (defs & ArchDefinePpcgr) 1165 Builder.defineMacro("_ARCH_PPCGR"); 1166 if (defs & ArchDefinePpcsq) 1167 Builder.defineMacro("_ARCH_PPCSQ"); 1168 if (defs & ArchDefine440) 1169 Builder.defineMacro("_ARCH_440"); 1170 if (defs & ArchDefine603) 1171 Builder.defineMacro("_ARCH_603"); 1172 if (defs & ArchDefine604) 1173 Builder.defineMacro("_ARCH_604"); 1174 if (defs & ArchDefinePwr4) 1175 Builder.defineMacro("_ARCH_PWR4"); 1176 if (defs & ArchDefinePwr5) 1177 Builder.defineMacro("_ARCH_PWR5"); 1178 if (defs & ArchDefinePwr5x) 1179 Builder.defineMacro("_ARCH_PWR5X"); 1180 if (defs & ArchDefinePwr6) 1181 Builder.defineMacro("_ARCH_PWR6"); 1182 if (defs & ArchDefinePwr6x) 1183 Builder.defineMacro("_ARCH_PWR6X"); 1184 if (defs & ArchDefinePwr7) 1185 Builder.defineMacro("_ARCH_PWR7"); 1186 if (defs & ArchDefinePwr8) 1187 Builder.defineMacro("_ARCH_PWR8"); 1188 if (defs & ArchDefineA2) 1189 Builder.defineMacro("_ARCH_A2"); 1190 if (defs & ArchDefineA2q) { 1191 Builder.defineMacro("_ARCH_A2Q"); 1192 Builder.defineMacro("_ARCH_QP"); 1193 } 1194 1195 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1196 Builder.defineMacro("__bg__"); 1197 Builder.defineMacro("__THW_BLUEGENE__"); 1198 Builder.defineMacro("__bgq__"); 1199 Builder.defineMacro("__TOS_BGQ__"); 1200 } 1201 1202 if (HasVSX) 1203 Builder.defineMacro("__VSX__"); 1204 if (HasP8Vector) 1205 Builder.defineMacro("__POWER8_VECTOR__"); 1206 if (HasP8Crypto) 1207 Builder.defineMacro("__CRYPTO__"); 1208 if (HasHTM) 1209 Builder.defineMacro("__HTM__"); 1210 1211 // FIXME: The following are not yet generated here by Clang, but are 1212 // generated by GCC: 1213 // 1214 // _SOFT_FLOAT_ 1215 // __RECIP_PRECISION__ 1216 // __APPLE_ALTIVEC__ 1217 // __RECIP__ 1218 // __RECIPF__ 1219 // __RSQRTE__ 1220 // __RSQRTEF__ 1221 // _SOFT_DOUBLE_ 1222 // __NO_LWSYNC__ 1223 // __HAVE_BSWAP__ 1224 // __LONGDOUBLE128 1225 // __CMODEL_MEDIUM__ 1226 // __CMODEL_LARGE__ 1227 // _CALL_SYSV 1228 // _CALL_DARWIN 1229 // __NO_FPRS__ 1230 } 1231 1232 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1233 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1234 .Case("7400", true) 1235 .Case("g4", true) 1236 .Case("7450", true) 1237 .Case("g4+", true) 1238 .Case("970", true) 1239 .Case("g5", true) 1240 .Case("pwr6", true) 1241 .Case("pwr7", true) 1242 .Case("pwr8", true) 1243 .Case("ppc64", true) 1244 .Case("ppc64le", true) 1245 .Default(false); 1246 1247 Features["qpx"] = (CPU == "a2q"); 1248 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1249 .Case("ppc64le", true) 1250 .Case("pwr8", true) 1251 .Default(false); 1252 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1253 .Case("ppc64le", true) 1254 .Case("pwr8", true) 1255 .Default(false); 1256 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1257 .Case("ppc64le", true) 1258 .Case("pwr8", true) 1259 .Case("pwr7", true) 1260 .Default(false); 1261 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1262 .Case("ppc64le", true) 1263 .Case("pwr8", true) 1264 .Case("pwr7", true) 1265 .Default(false); 1266 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1267 .Case("ppc64le", true) 1268 .Case("pwr8", true) 1269 .Default(false); 1270 } 1271 1272 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1273 return llvm::StringSwitch<bool>(Feature) 1274 .Case("powerpc", true) 1275 .Case("vsx", HasVSX) 1276 .Case("power8-vector", HasP8Vector) 1277 .Case("crypto", HasP8Crypto) 1278 .Case("direct-move", HasDirectMove) 1279 .Case("qpx", HasQPX) 1280 .Case("htm", HasHTM) 1281 .Case("bpermd", HasBPERMD) 1282 .Case("extdiv", HasExtDiv) 1283 .Default(false); 1284 } 1285 1286 const char * const PPCTargetInfo::GCCRegNames[] = { 1287 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1288 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1289 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1290 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1291 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1292 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1293 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1294 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1295 "mq", "lr", "ctr", "ap", 1296 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1297 "xer", 1298 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1299 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1300 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1301 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1302 "vrsave", "vscr", 1303 "spe_acc", "spefscr", 1304 "sfp" 1305 }; 1306 1307 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1308 unsigned &NumNames) const { 1309 Names = GCCRegNames; 1310 NumNames = llvm::array_lengthof(GCCRegNames); 1311 } 1312 1313 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1314 // While some of these aliases do map to different registers 1315 // they still share the same register name. 1316 { { "0" }, "r0" }, 1317 { { "1"}, "r1" }, 1318 { { "2" }, "r2" }, 1319 { { "3" }, "r3" }, 1320 { { "4" }, "r4" }, 1321 { { "5" }, "r5" }, 1322 { { "6" }, "r6" }, 1323 { { "7" }, "r7" }, 1324 { { "8" }, "r8" }, 1325 { { "9" }, "r9" }, 1326 { { "10" }, "r10" }, 1327 { { "11" }, "r11" }, 1328 { { "12" }, "r12" }, 1329 { { "13" }, "r13" }, 1330 { { "14" }, "r14" }, 1331 { { "15" }, "r15" }, 1332 { { "16" }, "r16" }, 1333 { { "17" }, "r17" }, 1334 { { "18" }, "r18" }, 1335 { { "19" }, "r19" }, 1336 { { "20" }, "r20" }, 1337 { { "21" }, "r21" }, 1338 { { "22" }, "r22" }, 1339 { { "23" }, "r23" }, 1340 { { "24" }, "r24" }, 1341 { { "25" }, "r25" }, 1342 { { "26" }, "r26" }, 1343 { { "27" }, "r27" }, 1344 { { "28" }, "r28" }, 1345 { { "29" }, "r29" }, 1346 { { "30" }, "r30" }, 1347 { { "31" }, "r31" }, 1348 { { "fr0" }, "f0" }, 1349 { { "fr1" }, "f1" }, 1350 { { "fr2" }, "f2" }, 1351 { { "fr3" }, "f3" }, 1352 { { "fr4" }, "f4" }, 1353 { { "fr5" }, "f5" }, 1354 { { "fr6" }, "f6" }, 1355 { { "fr7" }, "f7" }, 1356 { { "fr8" }, "f8" }, 1357 { { "fr9" }, "f9" }, 1358 { { "fr10" }, "f10" }, 1359 { { "fr11" }, "f11" }, 1360 { { "fr12" }, "f12" }, 1361 { { "fr13" }, "f13" }, 1362 { { "fr14" }, "f14" }, 1363 { { "fr15" }, "f15" }, 1364 { { "fr16" }, "f16" }, 1365 { { "fr17" }, "f17" }, 1366 { { "fr18" }, "f18" }, 1367 { { "fr19" }, "f19" }, 1368 { { "fr20" }, "f20" }, 1369 { { "fr21" }, "f21" }, 1370 { { "fr22" }, "f22" }, 1371 { { "fr23" }, "f23" }, 1372 { { "fr24" }, "f24" }, 1373 { { "fr25" }, "f25" }, 1374 { { "fr26" }, "f26" }, 1375 { { "fr27" }, "f27" }, 1376 { { "fr28" }, "f28" }, 1377 { { "fr29" }, "f29" }, 1378 { { "fr30" }, "f30" }, 1379 { { "fr31" }, "f31" }, 1380 { { "cc" }, "cr0" }, 1381 }; 1382 1383 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1384 unsigned &NumAliases) const { 1385 Aliases = GCCRegAliases; 1386 NumAliases = llvm::array_lengthof(GCCRegAliases); 1387 } 1388 1389 class PPC32TargetInfo : public PPCTargetInfo { 1390 public: 1391 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1392 DescriptionString = "E-m:e-p:32:32-i64:64-n32"; 1393 1394 switch (getTriple().getOS()) { 1395 case llvm::Triple::Linux: 1396 case llvm::Triple::FreeBSD: 1397 case llvm::Triple::NetBSD: 1398 SizeType = UnsignedInt; 1399 PtrDiffType = SignedInt; 1400 IntPtrType = SignedInt; 1401 break; 1402 default: 1403 break; 1404 } 1405 1406 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1407 LongDoubleWidth = LongDoubleAlign = 64; 1408 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1409 } 1410 1411 // PPC32 supports atomics up to 4 bytes. 1412 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1413 } 1414 1415 BuiltinVaListKind getBuiltinVaListKind() const override { 1416 // This is the ELF definition, and is overridden by the Darwin sub-target 1417 return TargetInfo::PowerABIBuiltinVaList; 1418 } 1419 }; 1420 1421 // Note: ABI differences may eventually require us to have a separate 1422 // TargetInfo for little endian. 1423 class PPC64TargetInfo : public PPCTargetInfo { 1424 public: 1425 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1426 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1427 IntMaxType = SignedLong; 1428 Int64Type = SignedLong; 1429 1430 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1431 DescriptionString = "e-m:e-i64:64-n32:64"; 1432 ABI = "elfv2"; 1433 } else { 1434 DescriptionString = "E-m:e-i64:64-n32:64"; 1435 ABI = "elfv1"; 1436 } 1437 1438 switch (getTriple().getOS()) { 1439 case llvm::Triple::FreeBSD: 1440 LongDoubleWidth = LongDoubleAlign = 64; 1441 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1442 break; 1443 case llvm::Triple::NetBSD: 1444 IntMaxType = SignedLongLong; 1445 Int64Type = SignedLongLong; 1446 break; 1447 default: 1448 break; 1449 } 1450 1451 // PPC64 supports atomics up to 8 bytes. 1452 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1453 } 1454 BuiltinVaListKind getBuiltinVaListKind() const override { 1455 return TargetInfo::CharPtrBuiltinVaList; 1456 } 1457 // PPC64 Linux-specifc ABI options. 1458 bool setABI(const std::string &Name) override { 1459 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1460 ABI = Name; 1461 return true; 1462 } 1463 return false; 1464 } 1465 }; 1466 1467 class DarwinPPC32TargetInfo : 1468 public DarwinTargetInfo<PPC32TargetInfo> { 1469 public: 1470 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1471 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1472 HasAlignMac68kSupport = true; 1473 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1474 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1475 LongLongAlign = 32; 1476 SuitableAlign = 128; 1477 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; 1478 } 1479 BuiltinVaListKind getBuiltinVaListKind() const override { 1480 return TargetInfo::CharPtrBuiltinVaList; 1481 } 1482 }; 1483 1484 class DarwinPPC64TargetInfo : 1485 public DarwinTargetInfo<PPC64TargetInfo> { 1486 public: 1487 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1488 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1489 HasAlignMac68kSupport = true; 1490 SuitableAlign = 128; 1491 DescriptionString = "E-m:o-i64:64-n32:64"; 1492 } 1493 }; 1494 1495 static const unsigned NVPTXAddrSpaceMap[] = { 1496 1, // opencl_global 1497 3, // opencl_local 1498 4, // opencl_constant 1499 // FIXME: generic has to be added to the target 1500 0, // opencl_generic 1501 1, // cuda_device 1502 4, // cuda_constant 1503 3, // cuda_shared 1504 }; 1505 class NVPTXTargetInfo : public TargetInfo { 1506 static const char * const GCCRegNames[]; 1507 static const Builtin::Info BuiltinInfo[]; 1508 1509 // The GPU profiles supported by the NVPTX backend 1510 enum GPUKind { 1511 GK_NONE, 1512 GK_SM20, 1513 GK_SM21, 1514 GK_SM30, 1515 GK_SM35, 1516 GK_SM37, 1517 } GPU; 1518 1519 public: 1520 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1521 BigEndian = false; 1522 TLSSupported = false; 1523 LongWidth = LongAlign = 64; 1524 AddrSpaceMap = &NVPTXAddrSpaceMap; 1525 UseAddrSpaceMapMangling = true; 1526 // Define available target features 1527 // These must be defined in sorted order! 1528 NoAsmVariants = true; 1529 // Set the default GPU to sm20 1530 GPU = GK_SM20; 1531 } 1532 void getTargetDefines(const LangOptions &Opts, 1533 MacroBuilder &Builder) const override { 1534 Builder.defineMacro("__PTX__"); 1535 Builder.defineMacro("__NVPTX__"); 1536 if (Opts.CUDAIsDevice) { 1537 // Set __CUDA_ARCH__ for the GPU specified. 1538 std::string CUDAArchCode; 1539 switch (GPU) { 1540 case GK_SM20: 1541 CUDAArchCode = "200"; 1542 break; 1543 case GK_SM21: 1544 CUDAArchCode = "210"; 1545 break; 1546 case GK_SM30: 1547 CUDAArchCode = "300"; 1548 break; 1549 case GK_SM35: 1550 CUDAArchCode = "350"; 1551 break; 1552 case GK_SM37: 1553 CUDAArchCode = "370"; 1554 break; 1555 default: 1556 llvm_unreachable("Unhandled target CPU"); 1557 } 1558 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1559 } 1560 } 1561 void getTargetBuiltins(const Builtin::Info *&Records, 1562 unsigned &NumRecords) const override { 1563 Records = BuiltinInfo; 1564 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1565 } 1566 bool hasFeature(StringRef Feature) const override { 1567 return Feature == "ptx" || Feature == "nvptx"; 1568 } 1569 1570 void getGCCRegNames(const char * const *&Names, 1571 unsigned &NumNames) const override; 1572 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1573 unsigned &NumAliases) const override { 1574 // No aliases. 1575 Aliases = nullptr; 1576 NumAliases = 0; 1577 } 1578 bool 1579 validateAsmConstraint(const char *&Name, 1580 TargetInfo::ConstraintInfo &Info) const override { 1581 switch (*Name) { 1582 default: return false; 1583 case 'c': 1584 case 'h': 1585 case 'r': 1586 case 'l': 1587 case 'f': 1588 case 'd': 1589 Info.setAllowsRegister(); 1590 return true; 1591 } 1592 } 1593 const char *getClobbers() const override { 1594 // FIXME: Is this really right? 1595 return ""; 1596 } 1597 BuiltinVaListKind getBuiltinVaListKind() const override { 1598 // FIXME: implement 1599 return TargetInfo::CharPtrBuiltinVaList; 1600 } 1601 bool setCPU(const std::string &Name) override { 1602 GPU = llvm::StringSwitch<GPUKind>(Name) 1603 .Case("sm_20", GK_SM20) 1604 .Case("sm_21", GK_SM21) 1605 .Case("sm_30", GK_SM30) 1606 .Case("sm_35", GK_SM35) 1607 .Case("sm_37", GK_SM37) 1608 .Default(GK_NONE); 1609 1610 return GPU != GK_NONE; 1611 } 1612 }; 1613 1614 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1615 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1616 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1617 ALL_LANGUAGES }, 1618 #include "clang/Basic/BuiltinsNVPTX.def" 1619 }; 1620 1621 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1622 "r0" 1623 }; 1624 1625 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1626 unsigned &NumNames) const { 1627 Names = GCCRegNames; 1628 NumNames = llvm::array_lengthof(GCCRegNames); 1629 } 1630 1631 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1632 public: 1633 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1634 PointerWidth = PointerAlign = 32; 1635 SizeType = TargetInfo::UnsignedInt; 1636 PtrDiffType = TargetInfo::SignedInt; 1637 IntPtrType = TargetInfo::SignedInt; 1638 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1639 } 1640 }; 1641 1642 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1643 public: 1644 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1645 PointerWidth = PointerAlign = 64; 1646 SizeType = TargetInfo::UnsignedLong; 1647 PtrDiffType = TargetInfo::SignedLong; 1648 IntPtrType = TargetInfo::SignedLong; 1649 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1650 } 1651 }; 1652 1653 static const unsigned R600AddrSpaceMap[] = { 1654 1, // opencl_global 1655 3, // opencl_local 1656 2, // opencl_constant 1657 4, // opencl_generic 1658 1, // cuda_device 1659 2, // cuda_constant 1660 3 // cuda_shared 1661 }; 1662 1663 // If you edit the description strings, make sure you update 1664 // getPointerWidthV(). 1665 1666 static const char *DescriptionStringR600 = 1667 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1668 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1669 1670 static const char *DescriptionStringR600DoubleOps = 1671 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1672 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1673 1674 static const char *DescriptionStringSI = 1675 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1676 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1677 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1678 1679 class R600TargetInfo : public TargetInfo { 1680 static const Builtin::Info BuiltinInfo[]; 1681 static const char * const GCCRegNames[]; 1682 1683 /// \brief The GPU profiles supported by the R600 target. 1684 enum GPUKind { 1685 GK_NONE, 1686 GK_R600, 1687 GK_R600_DOUBLE_OPS, 1688 GK_R700, 1689 GK_R700_DOUBLE_OPS, 1690 GK_EVERGREEN, 1691 GK_EVERGREEN_DOUBLE_OPS, 1692 GK_NORTHERN_ISLANDS, 1693 GK_CAYMAN, 1694 GK_SOUTHERN_ISLANDS, 1695 GK_SEA_ISLANDS 1696 } GPU; 1697 1698 bool hasFP64:1; 1699 bool hasFMAF:1; 1700 bool hasLDEXPF:1; 1701 1702 public: 1703 R600TargetInfo(const llvm::Triple &Triple) 1704 : TargetInfo(Triple) { 1705 1706 if (Triple.getArch() == llvm::Triple::amdgcn) { 1707 DescriptionString = DescriptionStringSI; 1708 GPU = GK_SOUTHERN_ISLANDS; 1709 hasFP64 = true; 1710 hasFMAF = true; 1711 hasLDEXPF = true; 1712 } else { 1713 DescriptionString = DescriptionStringR600; 1714 GPU = GK_R600; 1715 hasFP64 = false; 1716 hasFMAF = false; 1717 hasLDEXPF = false; 1718 } 1719 AddrSpaceMap = &R600AddrSpaceMap; 1720 UseAddrSpaceMapMangling = true; 1721 } 1722 1723 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1724 if (GPU <= GK_CAYMAN) 1725 return 32; 1726 1727 switch(AddrSpace) { 1728 default: 1729 return 64; 1730 case 0: 1731 case 3: 1732 case 5: 1733 return 32; 1734 } 1735 } 1736 1737 const char * getClobbers() const override { 1738 return ""; 1739 } 1740 1741 void getGCCRegNames(const char * const *&Names, 1742 unsigned &NumNames) const override; 1743 1744 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1745 unsigned &NumAliases) const override { 1746 Aliases = nullptr; 1747 NumAliases = 0; 1748 } 1749 1750 bool validateAsmConstraint(const char *&Name, 1751 TargetInfo::ConstraintInfo &info) const override { 1752 return true; 1753 } 1754 1755 void getTargetBuiltins(const Builtin::Info *&Records, 1756 unsigned &NumRecords) const override { 1757 Records = BuiltinInfo; 1758 NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin; 1759 } 1760 1761 void getTargetDefines(const LangOptions &Opts, 1762 MacroBuilder &Builder) const override { 1763 Builder.defineMacro("__R600__"); 1764 if (hasFMAF) 1765 Builder.defineMacro("__HAS_FMAF__"); 1766 if (hasLDEXPF) 1767 Builder.defineMacro("__HAS_LDEXPF__"); 1768 if (hasFP64 && Opts.OpenCL) { 1769 Builder.defineMacro("cl_khr_fp64"); 1770 } 1771 } 1772 1773 BuiltinVaListKind getBuiltinVaListKind() const override { 1774 return TargetInfo::CharPtrBuiltinVaList; 1775 } 1776 1777 bool setCPU(const std::string &Name) override { 1778 GPU = llvm::StringSwitch<GPUKind>(Name) 1779 .Case("r600" , GK_R600) 1780 .Case("rv610", GK_R600) 1781 .Case("rv620", GK_R600) 1782 .Case("rv630", GK_R600) 1783 .Case("rv635", GK_R600) 1784 .Case("rs780", GK_R600) 1785 .Case("rs880", GK_R600) 1786 .Case("rv670", GK_R600_DOUBLE_OPS) 1787 .Case("rv710", GK_R700) 1788 .Case("rv730", GK_R700) 1789 .Case("rv740", GK_R700_DOUBLE_OPS) 1790 .Case("rv770", GK_R700_DOUBLE_OPS) 1791 .Case("palm", GK_EVERGREEN) 1792 .Case("cedar", GK_EVERGREEN) 1793 .Case("sumo", GK_EVERGREEN) 1794 .Case("sumo2", GK_EVERGREEN) 1795 .Case("redwood", GK_EVERGREEN) 1796 .Case("juniper", GK_EVERGREEN) 1797 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1798 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1799 .Case("barts", GK_NORTHERN_ISLANDS) 1800 .Case("turks", GK_NORTHERN_ISLANDS) 1801 .Case("caicos", GK_NORTHERN_ISLANDS) 1802 .Case("cayman", GK_CAYMAN) 1803 .Case("aruba", GK_CAYMAN) 1804 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1805 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1806 .Case("verde", GK_SOUTHERN_ISLANDS) 1807 .Case("oland", GK_SOUTHERN_ISLANDS) 1808 .Case("hainan", GK_SOUTHERN_ISLANDS) 1809 .Case("bonaire", GK_SEA_ISLANDS) 1810 .Case("kabini", GK_SEA_ISLANDS) 1811 .Case("kaveri", GK_SEA_ISLANDS) 1812 .Case("hawaii", GK_SEA_ISLANDS) 1813 .Case("mullins", GK_SEA_ISLANDS) 1814 .Default(GK_NONE); 1815 1816 if (GPU == GK_NONE) { 1817 return false; 1818 } 1819 1820 // Set the correct data layout 1821 switch (GPU) { 1822 case GK_NONE: 1823 case GK_R600: 1824 case GK_R700: 1825 case GK_EVERGREEN: 1826 case GK_NORTHERN_ISLANDS: 1827 DescriptionString = DescriptionStringR600; 1828 hasFP64 = false; 1829 hasFMAF = false; 1830 hasLDEXPF = false; 1831 break; 1832 case GK_R600_DOUBLE_OPS: 1833 case GK_R700_DOUBLE_OPS: 1834 case GK_EVERGREEN_DOUBLE_OPS: 1835 case GK_CAYMAN: 1836 DescriptionString = DescriptionStringR600DoubleOps; 1837 hasFP64 = true; 1838 hasFMAF = true; 1839 hasLDEXPF = false; 1840 break; 1841 case GK_SOUTHERN_ISLANDS: 1842 case GK_SEA_ISLANDS: 1843 DescriptionString = DescriptionStringSI; 1844 hasFP64 = true; 1845 hasFMAF = true; 1846 hasLDEXPF = true; 1847 break; 1848 } 1849 1850 return true; 1851 } 1852 }; 1853 1854 const Builtin::Info R600TargetInfo::BuiltinInfo[] = { 1855 #define BUILTIN(ID, TYPE, ATTRS) \ 1856 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1857 #include "clang/Basic/BuiltinsR600.def" 1858 }; 1859 const char * const R600TargetInfo::GCCRegNames[] = { 1860 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1861 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1862 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1863 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1864 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1865 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1866 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1867 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1868 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1869 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1870 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1871 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1872 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1873 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1874 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1875 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1876 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1877 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1878 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1879 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 1880 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 1881 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 1882 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 1883 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 1884 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 1885 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 1886 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 1887 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 1888 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 1889 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 1890 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 1891 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 1892 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 1893 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 1894 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 1895 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 1896 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 1897 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 1898 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 1899 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 1900 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 1901 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 1902 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 1903 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 1904 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 1905 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 1906 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 1907 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127" 1908 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi", 1909 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi" 1910 }; 1911 1912 void R600TargetInfo::getGCCRegNames(const char * const *&Names, 1913 unsigned &NumNames) const { 1914 Names = GCCRegNames; 1915 NumNames = llvm::array_lengthof(GCCRegNames); 1916 } 1917 1918 // Namespace for x86 abstract base class 1919 const Builtin::Info BuiltinInfo[] = { 1920 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1921 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1922 ALL_LANGUAGES }, 1923 #include "clang/Basic/BuiltinsX86.def" 1924 }; 1925 1926 static const char* const GCCRegNames[] = { 1927 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1928 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1929 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1930 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1931 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1932 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1933 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1934 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1935 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1936 }; 1937 1938 const TargetInfo::AddlRegName AddlRegNames[] = { 1939 { { "al", "ah", "eax", "rax" }, 0 }, 1940 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1941 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1942 { { "dl", "dh", "edx", "rdx" }, 1 }, 1943 { { "esi", "rsi" }, 4 }, 1944 { { "edi", "rdi" }, 5 }, 1945 { { "esp", "rsp" }, 7 }, 1946 { { "ebp", "rbp" }, 6 }, 1947 }; 1948 1949 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1950 // most of the implementation can be shared. 1951 class X86TargetInfo : public TargetInfo { 1952 enum X86SSEEnum { 1953 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1954 } SSELevel; 1955 enum MMX3DNowEnum { 1956 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1957 } MMX3DNowLevel; 1958 enum XOPEnum { 1959 NoXOP, 1960 SSE4A, 1961 FMA4, 1962 XOP 1963 } XOPLevel; 1964 1965 bool HasAES; 1966 bool HasPCLMUL; 1967 bool HasLZCNT; 1968 bool HasRDRND; 1969 bool HasFSGSBASE; 1970 bool HasBMI; 1971 bool HasBMI2; 1972 bool HasPOPCNT; 1973 bool HasRTM; 1974 bool HasPRFCHW; 1975 bool HasRDSEED; 1976 bool HasADX; 1977 bool HasTBM; 1978 bool HasFMA; 1979 bool HasF16C; 1980 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW, 1981 HasAVX512VL; 1982 bool HasSHA; 1983 bool HasCX16; 1984 1985 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1986 /// 1987 /// Each enumeration represents a particular CPU supported by Clang. These 1988 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1989 enum CPUKind { 1990 CK_Generic, 1991 1992 /// \name i386 1993 /// i386-generation processors. 1994 //@{ 1995 CK_i386, 1996 //@} 1997 1998 /// \name i486 1999 /// i486-generation processors. 2000 //@{ 2001 CK_i486, 2002 CK_WinChipC6, 2003 CK_WinChip2, 2004 CK_C3, 2005 //@} 2006 2007 /// \name i586 2008 /// i586-generation processors, P5 microarchitecture based. 2009 //@{ 2010 CK_i586, 2011 CK_Pentium, 2012 CK_PentiumMMX, 2013 //@} 2014 2015 /// \name i686 2016 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2017 //@{ 2018 CK_i686, 2019 CK_PentiumPro, 2020 CK_Pentium2, 2021 CK_Pentium3, 2022 CK_Pentium3M, 2023 CK_PentiumM, 2024 CK_C3_2, 2025 2026 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2027 /// Clang however has some logic to suport this. 2028 // FIXME: Warn, deprecate, and potentially remove this. 2029 CK_Yonah, 2030 //@} 2031 2032 /// \name Netburst 2033 /// Netburst microarchitecture based processors. 2034 //@{ 2035 CK_Pentium4, 2036 CK_Pentium4M, 2037 CK_Prescott, 2038 CK_Nocona, 2039 //@} 2040 2041 /// \name Core 2042 /// Core microarchitecture based processors. 2043 //@{ 2044 CK_Core2, 2045 2046 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2047 /// codename which GCC no longer accepts as an option to -march, but Clang 2048 /// has some logic for recognizing it. 2049 // FIXME: Warn, deprecate, and potentially remove this. 2050 CK_Penryn, 2051 //@} 2052 2053 /// \name Atom 2054 /// Atom processors 2055 //@{ 2056 CK_Bonnell, 2057 CK_Silvermont, 2058 //@} 2059 2060 /// \name Nehalem 2061 /// Nehalem microarchitecture based processors. 2062 CK_Nehalem, 2063 2064 /// \name Westmere 2065 /// Westmere microarchitecture based processors. 2066 CK_Westmere, 2067 2068 /// \name Sandy Bridge 2069 /// Sandy Bridge microarchitecture based processors. 2070 CK_SandyBridge, 2071 2072 /// \name Ivy Bridge 2073 /// Ivy Bridge microarchitecture based processors. 2074 CK_IvyBridge, 2075 2076 /// \name Haswell 2077 /// Haswell microarchitecture based processors. 2078 CK_Haswell, 2079 2080 /// \name Broadwell 2081 /// Broadwell microarchitecture based processors. 2082 CK_Broadwell, 2083 2084 /// \name Skylake 2085 /// Skylake microarchitecture based processors. 2086 CK_Skylake, 2087 2088 /// \name Knights Landing 2089 /// Knights Landing processor. 2090 CK_KNL, 2091 2092 /// \name K6 2093 /// K6 architecture processors. 2094 //@{ 2095 CK_K6, 2096 CK_K6_2, 2097 CK_K6_3, 2098 //@} 2099 2100 /// \name K7 2101 /// K7 architecture processors. 2102 //@{ 2103 CK_Athlon, 2104 CK_AthlonThunderbird, 2105 CK_Athlon4, 2106 CK_AthlonXP, 2107 CK_AthlonMP, 2108 //@} 2109 2110 /// \name K8 2111 /// K8 architecture processors. 2112 //@{ 2113 CK_Athlon64, 2114 CK_Athlon64SSE3, 2115 CK_AthlonFX, 2116 CK_K8, 2117 CK_K8SSE3, 2118 CK_Opteron, 2119 CK_OpteronSSE3, 2120 CK_AMDFAM10, 2121 //@} 2122 2123 /// \name Bobcat 2124 /// Bobcat architecture processors. 2125 //@{ 2126 CK_BTVER1, 2127 CK_BTVER2, 2128 //@} 2129 2130 /// \name Bulldozer 2131 /// Bulldozer architecture processors. 2132 //@{ 2133 CK_BDVER1, 2134 CK_BDVER2, 2135 CK_BDVER3, 2136 CK_BDVER4, 2137 //@} 2138 2139 /// This specification is deprecated and will be removed in the future. 2140 /// Users should prefer \see CK_K8. 2141 // FIXME: Warn on this when the CPU is set to it. 2142 //@{ 2143 CK_x86_64, 2144 //@} 2145 2146 /// \name Geode 2147 /// Geode processors. 2148 //@{ 2149 CK_Geode 2150 //@} 2151 } CPU; 2152 2153 enum FPMathKind { 2154 FP_Default, 2155 FP_SSE, 2156 FP_387 2157 } FPMath; 2158 2159 public: 2160 X86TargetInfo(const llvm::Triple &Triple) 2161 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 2162 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 2163 HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false), 2164 HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false), 2165 HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false), 2166 HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false), 2167 HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false), 2168 HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) { 2169 BigEndian = false; 2170 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2171 } 2172 unsigned getFloatEvalMethod() const override { 2173 // X87 evaluates with 80 bits "long double" precision. 2174 return SSELevel == NoSSE ? 2 : 0; 2175 } 2176 void getTargetBuiltins(const Builtin::Info *&Records, 2177 unsigned &NumRecords) const override { 2178 Records = BuiltinInfo; 2179 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 2180 } 2181 void getGCCRegNames(const char * const *&Names, 2182 unsigned &NumNames) const override { 2183 Names = GCCRegNames; 2184 NumNames = llvm::array_lengthof(GCCRegNames); 2185 } 2186 void getGCCRegAliases(const GCCRegAlias *&Aliases, 2187 unsigned &NumAliases) const override { 2188 Aliases = nullptr; 2189 NumAliases = 0; 2190 } 2191 void getGCCAddlRegNames(const AddlRegName *&Names, 2192 unsigned &NumNames) const override { 2193 Names = AddlRegNames; 2194 NumNames = llvm::array_lengthof(AddlRegNames); 2195 } 2196 bool validateAsmConstraint(const char *&Name, 2197 TargetInfo::ConstraintInfo &info) const override; 2198 2199 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2200 2201 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2202 2203 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2204 2205 std::string convertConstraint(const char *&Constraint) const override; 2206 const char *getClobbers() const override { 2207 return "~{dirflag},~{fpsr},~{flags}"; 2208 } 2209 void getTargetDefines(const LangOptions &Opts, 2210 MacroBuilder &Builder) const override; 2211 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2212 bool Enabled); 2213 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2214 bool Enabled); 2215 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2216 bool Enabled); 2217 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2218 StringRef Name, bool Enabled) const override { 2219 setFeatureEnabledImpl(Features, Name, Enabled); 2220 } 2221 // This exists purely to cut down on the number of virtual calls in 2222 // getDefaultFeatures which calls this repeatedly. 2223 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2224 StringRef Name, bool Enabled); 2225 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 2226 bool hasFeature(StringRef Feature) const override; 2227 bool handleTargetFeatures(std::vector<std::string> &Features, 2228 DiagnosticsEngine &Diags) override; 2229 StringRef getABI() const override { 2230 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2231 return "avx"; 2232 else if (getTriple().getArch() == llvm::Triple::x86 && 2233 MMX3DNowLevel == NoMMX3DNow) 2234 return "no-mmx"; 2235 return ""; 2236 } 2237 bool setCPU(const std::string &Name) override { 2238 CPU = llvm::StringSwitch<CPUKind>(Name) 2239 .Case("i386", CK_i386) 2240 .Case("i486", CK_i486) 2241 .Case("winchip-c6", CK_WinChipC6) 2242 .Case("winchip2", CK_WinChip2) 2243 .Case("c3", CK_C3) 2244 .Case("i586", CK_i586) 2245 .Case("pentium", CK_Pentium) 2246 .Case("pentium-mmx", CK_PentiumMMX) 2247 .Case("i686", CK_i686) 2248 .Case("pentiumpro", CK_PentiumPro) 2249 .Case("pentium2", CK_Pentium2) 2250 .Case("pentium3", CK_Pentium3) 2251 .Case("pentium3m", CK_Pentium3M) 2252 .Case("pentium-m", CK_PentiumM) 2253 .Case("c3-2", CK_C3_2) 2254 .Case("yonah", CK_Yonah) 2255 .Case("pentium4", CK_Pentium4) 2256 .Case("pentium4m", CK_Pentium4M) 2257 .Case("prescott", CK_Prescott) 2258 .Case("nocona", CK_Nocona) 2259 .Case("core2", CK_Core2) 2260 .Case("penryn", CK_Penryn) 2261 .Case("bonnell", CK_Bonnell) 2262 .Case("atom", CK_Bonnell) // Legacy name. 2263 .Case("silvermont", CK_Silvermont) 2264 .Case("slm", CK_Silvermont) // Legacy name. 2265 .Case("nehalem", CK_Nehalem) 2266 .Case("corei7", CK_Nehalem) // Legacy name. 2267 .Case("westmere", CK_Westmere) 2268 .Case("sandybridge", CK_SandyBridge) 2269 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2270 .Case("ivybridge", CK_IvyBridge) 2271 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2272 .Case("haswell", CK_Haswell) 2273 .Case("core-avx2", CK_Haswell) // Legacy name. 2274 .Case("broadwell", CK_Broadwell) 2275 .Case("skylake", CK_Skylake) 2276 .Case("skx", CK_Skylake) // Legacy name. 2277 .Case("knl", CK_KNL) 2278 .Case("k6", CK_K6) 2279 .Case("k6-2", CK_K6_2) 2280 .Case("k6-3", CK_K6_3) 2281 .Case("athlon", CK_Athlon) 2282 .Case("athlon-tbird", CK_AthlonThunderbird) 2283 .Case("athlon-4", CK_Athlon4) 2284 .Case("athlon-xp", CK_AthlonXP) 2285 .Case("athlon-mp", CK_AthlonMP) 2286 .Case("athlon64", CK_Athlon64) 2287 .Case("athlon64-sse3", CK_Athlon64SSE3) 2288 .Case("athlon-fx", CK_AthlonFX) 2289 .Case("k8", CK_K8) 2290 .Case("k8-sse3", CK_K8SSE3) 2291 .Case("opteron", CK_Opteron) 2292 .Case("opteron-sse3", CK_OpteronSSE3) 2293 .Case("barcelona", CK_AMDFAM10) 2294 .Case("amdfam10", CK_AMDFAM10) 2295 .Case("btver1", CK_BTVER1) 2296 .Case("btver2", CK_BTVER2) 2297 .Case("bdver1", CK_BDVER1) 2298 .Case("bdver2", CK_BDVER2) 2299 .Case("bdver3", CK_BDVER3) 2300 .Case("bdver4", CK_BDVER4) 2301 .Case("x86-64", CK_x86_64) 2302 .Case("geode", CK_Geode) 2303 .Default(CK_Generic); 2304 2305 // Perform any per-CPU checks necessary to determine if this CPU is 2306 // acceptable. 2307 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2308 // invalid without explaining *why*. 2309 switch (CPU) { 2310 case CK_Generic: 2311 // No processor selected! 2312 return false; 2313 2314 case CK_i386: 2315 case CK_i486: 2316 case CK_WinChipC6: 2317 case CK_WinChip2: 2318 case CK_C3: 2319 case CK_i586: 2320 case CK_Pentium: 2321 case CK_PentiumMMX: 2322 case CK_i686: 2323 case CK_PentiumPro: 2324 case CK_Pentium2: 2325 case CK_Pentium3: 2326 case CK_Pentium3M: 2327 case CK_PentiumM: 2328 case CK_Yonah: 2329 case CK_C3_2: 2330 case CK_Pentium4: 2331 case CK_Pentium4M: 2332 case CK_Prescott: 2333 case CK_K6: 2334 case CK_K6_2: 2335 case CK_K6_3: 2336 case CK_Athlon: 2337 case CK_AthlonThunderbird: 2338 case CK_Athlon4: 2339 case CK_AthlonXP: 2340 case CK_AthlonMP: 2341 case CK_Geode: 2342 // Only accept certain architectures when compiling in 32-bit mode. 2343 if (getTriple().getArch() != llvm::Triple::x86) 2344 return false; 2345 2346 // Fallthrough 2347 case CK_Nocona: 2348 case CK_Core2: 2349 case CK_Penryn: 2350 case CK_Bonnell: 2351 case CK_Silvermont: 2352 case CK_Nehalem: 2353 case CK_Westmere: 2354 case CK_SandyBridge: 2355 case CK_IvyBridge: 2356 case CK_Haswell: 2357 case CK_Broadwell: 2358 case CK_Skylake: 2359 case CK_KNL: 2360 case CK_Athlon64: 2361 case CK_Athlon64SSE3: 2362 case CK_AthlonFX: 2363 case CK_K8: 2364 case CK_K8SSE3: 2365 case CK_Opteron: 2366 case CK_OpteronSSE3: 2367 case CK_AMDFAM10: 2368 case CK_BTVER1: 2369 case CK_BTVER2: 2370 case CK_BDVER1: 2371 case CK_BDVER2: 2372 case CK_BDVER3: 2373 case CK_BDVER4: 2374 case CK_x86_64: 2375 return true; 2376 } 2377 llvm_unreachable("Unhandled CPU kind"); 2378 } 2379 2380 bool setFPMath(StringRef Name) override; 2381 2382 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2383 // We accept all non-ARM calling conventions 2384 return (CC == CC_X86ThisCall || 2385 CC == CC_X86FastCall || 2386 CC == CC_X86StdCall || 2387 CC == CC_X86VectorCall || 2388 CC == CC_C || 2389 CC == CC_X86Pascal || 2390 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2391 } 2392 2393 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2394 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2395 } 2396 2397 bool hasSjLjLowering() const override { 2398 return true; 2399 } 2400 }; 2401 2402 bool X86TargetInfo::setFPMath(StringRef Name) { 2403 if (Name == "387") { 2404 FPMath = FP_387; 2405 return true; 2406 } 2407 if (Name == "sse") { 2408 FPMath = FP_SSE; 2409 return true; 2410 } 2411 return false; 2412 } 2413 2414 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2415 // FIXME: This *really* should not be here. 2416 2417 // X86_64 always has SSE2. 2418 if (getTriple().getArch() == llvm::Triple::x86_64) 2419 setFeatureEnabledImpl(Features, "sse2", true); 2420 2421 switch (CPU) { 2422 case CK_Generic: 2423 case CK_i386: 2424 case CK_i486: 2425 case CK_i586: 2426 case CK_Pentium: 2427 case CK_i686: 2428 case CK_PentiumPro: 2429 break; 2430 case CK_PentiumMMX: 2431 case CK_Pentium2: 2432 case CK_K6: 2433 case CK_WinChipC6: 2434 setFeatureEnabledImpl(Features, "mmx", true); 2435 break; 2436 case CK_Pentium3: 2437 case CK_Pentium3M: 2438 case CK_C3_2: 2439 setFeatureEnabledImpl(Features, "sse", true); 2440 break; 2441 case CK_PentiumM: 2442 case CK_Pentium4: 2443 case CK_Pentium4M: 2444 case CK_x86_64: 2445 setFeatureEnabledImpl(Features, "sse2", true); 2446 break; 2447 case CK_Yonah: 2448 case CK_Prescott: 2449 case CK_Nocona: 2450 setFeatureEnabledImpl(Features, "sse3", true); 2451 setFeatureEnabledImpl(Features, "cx16", true); 2452 break; 2453 case CK_Core2: 2454 case CK_Bonnell: 2455 setFeatureEnabledImpl(Features, "ssse3", true); 2456 setFeatureEnabledImpl(Features, "cx16", true); 2457 break; 2458 case CK_Penryn: 2459 setFeatureEnabledImpl(Features, "sse4.1", true); 2460 setFeatureEnabledImpl(Features, "cx16", true); 2461 break; 2462 case CK_Skylake: 2463 setFeatureEnabledImpl(Features, "avx512f", true); 2464 setFeatureEnabledImpl(Features, "avx512cd", true); 2465 setFeatureEnabledImpl(Features, "avx512dq", true); 2466 setFeatureEnabledImpl(Features, "avx512bw", true); 2467 setFeatureEnabledImpl(Features, "avx512vl", true); 2468 // FALLTHROUGH 2469 case CK_Broadwell: 2470 setFeatureEnabledImpl(Features, "rdseed", true); 2471 setFeatureEnabledImpl(Features, "adx", true); 2472 // FALLTHROUGH 2473 case CK_Haswell: 2474 setFeatureEnabledImpl(Features, "avx2", true); 2475 setFeatureEnabledImpl(Features, "lzcnt", true); 2476 setFeatureEnabledImpl(Features, "bmi", true); 2477 setFeatureEnabledImpl(Features, "bmi2", true); 2478 setFeatureEnabledImpl(Features, "rtm", true); 2479 setFeatureEnabledImpl(Features, "fma", true); 2480 // FALLTHROUGH 2481 case CK_IvyBridge: 2482 setFeatureEnabledImpl(Features, "rdrnd", true); 2483 setFeatureEnabledImpl(Features, "f16c", true); 2484 setFeatureEnabledImpl(Features, "fsgsbase", true); 2485 // FALLTHROUGH 2486 case CK_SandyBridge: 2487 setFeatureEnabledImpl(Features, "avx", true); 2488 // FALLTHROUGH 2489 case CK_Westmere: 2490 case CK_Silvermont: 2491 setFeatureEnabledImpl(Features, "aes", true); 2492 setFeatureEnabledImpl(Features, "pclmul", true); 2493 // FALLTHROUGH 2494 case CK_Nehalem: 2495 setFeatureEnabledImpl(Features, "sse4.2", true); 2496 setFeatureEnabledImpl(Features, "cx16", true); 2497 break; 2498 case CK_KNL: 2499 setFeatureEnabledImpl(Features, "avx512f", true); 2500 setFeatureEnabledImpl(Features, "avx512cd", true); 2501 setFeatureEnabledImpl(Features, "avx512er", true); 2502 setFeatureEnabledImpl(Features, "avx512pf", true); 2503 setFeatureEnabledImpl(Features, "rdseed", true); 2504 setFeatureEnabledImpl(Features, "adx", true); 2505 setFeatureEnabledImpl(Features, "lzcnt", true); 2506 setFeatureEnabledImpl(Features, "bmi", true); 2507 setFeatureEnabledImpl(Features, "bmi2", true); 2508 setFeatureEnabledImpl(Features, "rtm", true); 2509 setFeatureEnabledImpl(Features, "fma", true); 2510 setFeatureEnabledImpl(Features, "rdrnd", true); 2511 setFeatureEnabledImpl(Features, "f16c", true); 2512 setFeatureEnabledImpl(Features, "fsgsbase", true); 2513 setFeatureEnabledImpl(Features, "aes", true); 2514 setFeatureEnabledImpl(Features, "pclmul", true); 2515 setFeatureEnabledImpl(Features, "cx16", true); 2516 break; 2517 case CK_K6_2: 2518 case CK_K6_3: 2519 case CK_WinChip2: 2520 case CK_C3: 2521 setFeatureEnabledImpl(Features, "3dnow", true); 2522 break; 2523 case CK_Athlon: 2524 case CK_AthlonThunderbird: 2525 case CK_Geode: 2526 setFeatureEnabledImpl(Features, "3dnowa", true); 2527 break; 2528 case CK_Athlon4: 2529 case CK_AthlonXP: 2530 case CK_AthlonMP: 2531 setFeatureEnabledImpl(Features, "sse", true); 2532 setFeatureEnabledImpl(Features, "3dnowa", true); 2533 break; 2534 case CK_K8: 2535 case CK_Opteron: 2536 case CK_Athlon64: 2537 case CK_AthlonFX: 2538 setFeatureEnabledImpl(Features, "sse2", true); 2539 setFeatureEnabledImpl(Features, "3dnowa", true); 2540 break; 2541 case CK_AMDFAM10: 2542 setFeatureEnabledImpl(Features, "sse4a", true); 2543 setFeatureEnabledImpl(Features, "lzcnt", true); 2544 setFeatureEnabledImpl(Features, "popcnt", true); 2545 // FALLTHROUGH 2546 case CK_K8SSE3: 2547 case CK_OpteronSSE3: 2548 case CK_Athlon64SSE3: 2549 setFeatureEnabledImpl(Features, "sse3", true); 2550 setFeatureEnabledImpl(Features, "3dnowa", true); 2551 break; 2552 case CK_BTVER2: 2553 setFeatureEnabledImpl(Features, "avx", true); 2554 setFeatureEnabledImpl(Features, "aes", true); 2555 setFeatureEnabledImpl(Features, "pclmul", true); 2556 setFeatureEnabledImpl(Features, "bmi", true); 2557 setFeatureEnabledImpl(Features, "f16c", true); 2558 // FALLTHROUGH 2559 case CK_BTVER1: 2560 setFeatureEnabledImpl(Features, "ssse3", true); 2561 setFeatureEnabledImpl(Features, "sse4a", true); 2562 setFeatureEnabledImpl(Features, "lzcnt", true); 2563 setFeatureEnabledImpl(Features, "popcnt", true); 2564 setFeatureEnabledImpl(Features, "prfchw", true); 2565 setFeatureEnabledImpl(Features, "cx16", true); 2566 break; 2567 case CK_BDVER4: 2568 setFeatureEnabledImpl(Features, "avx2", true); 2569 setFeatureEnabledImpl(Features, "bmi2", true); 2570 // FALLTHROUGH 2571 case CK_BDVER3: 2572 setFeatureEnabledImpl(Features, "fsgsbase", true); 2573 // FALLTHROUGH 2574 case CK_BDVER2: 2575 setFeatureEnabledImpl(Features, "bmi", true); 2576 setFeatureEnabledImpl(Features, "fma", true); 2577 setFeatureEnabledImpl(Features, "f16c", true); 2578 setFeatureEnabledImpl(Features, "tbm", true); 2579 // FALLTHROUGH 2580 case CK_BDVER1: 2581 // xop implies avx, sse4a and fma4. 2582 setFeatureEnabledImpl(Features, "xop", true); 2583 setFeatureEnabledImpl(Features, "lzcnt", true); 2584 setFeatureEnabledImpl(Features, "aes", true); 2585 setFeatureEnabledImpl(Features, "pclmul", true); 2586 setFeatureEnabledImpl(Features, "prfchw", true); 2587 setFeatureEnabledImpl(Features, "cx16", true); 2588 break; 2589 } 2590 } 2591 2592 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2593 X86SSEEnum Level, bool Enabled) { 2594 if (Enabled) { 2595 switch (Level) { 2596 case AVX512F: 2597 Features["avx512f"] = true; 2598 case AVX2: 2599 Features["avx2"] = true; 2600 case AVX: 2601 Features["avx"] = true; 2602 case SSE42: 2603 Features["sse4.2"] = true; 2604 case SSE41: 2605 Features["sse4.1"] = true; 2606 case SSSE3: 2607 Features["ssse3"] = true; 2608 case SSE3: 2609 Features["sse3"] = true; 2610 case SSE2: 2611 Features["sse2"] = true; 2612 case SSE1: 2613 Features["sse"] = true; 2614 case NoSSE: 2615 break; 2616 } 2617 return; 2618 } 2619 2620 switch (Level) { 2621 case NoSSE: 2622 case SSE1: 2623 Features["sse"] = false; 2624 case SSE2: 2625 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2626 Features["sha"] = false; 2627 case SSE3: 2628 Features["sse3"] = false; 2629 setXOPLevel(Features, NoXOP, false); 2630 case SSSE3: 2631 Features["ssse3"] = false; 2632 case SSE41: 2633 Features["sse4.1"] = false; 2634 case SSE42: 2635 Features["sse4.2"] = false; 2636 case AVX: 2637 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2638 setXOPLevel(Features, FMA4, false); 2639 case AVX2: 2640 Features["avx2"] = false; 2641 case AVX512F: 2642 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2643 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2644 Features["avx512vl"] = false; 2645 } 2646 } 2647 2648 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2649 MMX3DNowEnum Level, bool Enabled) { 2650 if (Enabled) { 2651 switch (Level) { 2652 case AMD3DNowAthlon: 2653 Features["3dnowa"] = true; 2654 case AMD3DNow: 2655 Features["3dnow"] = true; 2656 case MMX: 2657 Features["mmx"] = true; 2658 case NoMMX3DNow: 2659 break; 2660 } 2661 return; 2662 } 2663 2664 switch (Level) { 2665 case NoMMX3DNow: 2666 case MMX: 2667 Features["mmx"] = false; 2668 case AMD3DNow: 2669 Features["3dnow"] = false; 2670 case AMD3DNowAthlon: 2671 Features["3dnowa"] = false; 2672 } 2673 } 2674 2675 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2676 bool Enabled) { 2677 if (Enabled) { 2678 switch (Level) { 2679 case XOP: 2680 Features["xop"] = true; 2681 case FMA4: 2682 Features["fma4"] = true; 2683 setSSELevel(Features, AVX, true); 2684 case SSE4A: 2685 Features["sse4a"] = true; 2686 setSSELevel(Features, SSE3, true); 2687 case NoXOP: 2688 break; 2689 } 2690 return; 2691 } 2692 2693 switch (Level) { 2694 case NoXOP: 2695 case SSE4A: 2696 Features["sse4a"] = false; 2697 case FMA4: 2698 Features["fma4"] = false; 2699 case XOP: 2700 Features["xop"] = false; 2701 } 2702 } 2703 2704 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2705 StringRef Name, bool Enabled) { 2706 Features[Name] = Enabled; 2707 2708 if (Name == "mmx") { 2709 setMMXLevel(Features, MMX, Enabled); 2710 } else if (Name == "sse") { 2711 setSSELevel(Features, SSE1, Enabled); 2712 } else if (Name == "sse2") { 2713 setSSELevel(Features, SSE2, Enabled); 2714 } else if (Name == "sse3") { 2715 setSSELevel(Features, SSE3, Enabled); 2716 } else if (Name == "ssse3") { 2717 setSSELevel(Features, SSSE3, Enabled); 2718 } else if (Name == "sse4.2") { 2719 setSSELevel(Features, SSE42, Enabled); 2720 } else if (Name == "sse4.1") { 2721 setSSELevel(Features, SSE41, Enabled); 2722 } else if (Name == "3dnow") { 2723 setMMXLevel(Features, AMD3DNow, Enabled); 2724 } else if (Name == "3dnowa") { 2725 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2726 } else if (Name == "aes") { 2727 if (Enabled) 2728 setSSELevel(Features, SSE2, Enabled); 2729 } else if (Name == "pclmul") { 2730 if (Enabled) 2731 setSSELevel(Features, SSE2, Enabled); 2732 } else if (Name == "avx") { 2733 setSSELevel(Features, AVX, Enabled); 2734 } else if (Name == "avx2") { 2735 setSSELevel(Features, AVX2, Enabled); 2736 } else if (Name == "avx512f") { 2737 setSSELevel(Features, AVX512F, Enabled); 2738 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2739 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2740 if (Enabled) 2741 setSSELevel(Features, AVX512F, Enabled); 2742 } else if (Name == "fma") { 2743 if (Enabled) 2744 setSSELevel(Features, AVX, Enabled); 2745 } else if (Name == "fma4") { 2746 setXOPLevel(Features, FMA4, Enabled); 2747 } else if (Name == "xop") { 2748 setXOPLevel(Features, XOP, Enabled); 2749 } else if (Name == "sse4a") { 2750 setXOPLevel(Features, SSE4A, Enabled); 2751 } else if (Name == "f16c") { 2752 if (Enabled) 2753 setSSELevel(Features, AVX, Enabled); 2754 } else if (Name == "sha") { 2755 if (Enabled) 2756 setSSELevel(Features, SSE2, Enabled); 2757 } 2758 } 2759 2760 /// handleTargetFeatures - Perform initialization based on the user 2761 /// configured set of features. 2762 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2763 DiagnosticsEngine &Diags) { 2764 // Remember the maximum enabled sselevel. 2765 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2766 // Ignore disabled features. 2767 if (Features[i][0] == '-') 2768 continue; 2769 2770 StringRef Feature = StringRef(Features[i]).substr(1); 2771 2772 if (Feature == "aes") { 2773 HasAES = true; 2774 continue; 2775 } 2776 2777 if (Feature == "pclmul") { 2778 HasPCLMUL = true; 2779 continue; 2780 } 2781 2782 if (Feature == "lzcnt") { 2783 HasLZCNT = true; 2784 continue; 2785 } 2786 2787 if (Feature == "rdrnd") { 2788 HasRDRND = true; 2789 continue; 2790 } 2791 2792 if (Feature == "fsgsbase") { 2793 HasFSGSBASE = true; 2794 continue; 2795 } 2796 2797 if (Feature == "bmi") { 2798 HasBMI = true; 2799 continue; 2800 } 2801 2802 if (Feature == "bmi2") { 2803 HasBMI2 = true; 2804 continue; 2805 } 2806 2807 if (Feature == "popcnt") { 2808 HasPOPCNT = true; 2809 continue; 2810 } 2811 2812 if (Feature == "rtm") { 2813 HasRTM = true; 2814 continue; 2815 } 2816 2817 if (Feature == "prfchw") { 2818 HasPRFCHW = true; 2819 continue; 2820 } 2821 2822 if (Feature == "rdseed") { 2823 HasRDSEED = true; 2824 continue; 2825 } 2826 2827 if (Feature == "adx") { 2828 HasADX = true; 2829 continue; 2830 } 2831 2832 if (Feature == "tbm") { 2833 HasTBM = true; 2834 continue; 2835 } 2836 2837 if (Feature == "fma") { 2838 HasFMA = true; 2839 continue; 2840 } 2841 2842 if (Feature == "f16c") { 2843 HasF16C = true; 2844 continue; 2845 } 2846 2847 if (Feature == "avx512cd") { 2848 HasAVX512CD = true; 2849 continue; 2850 } 2851 2852 if (Feature == "avx512er") { 2853 HasAVX512ER = true; 2854 continue; 2855 } 2856 2857 if (Feature == "avx512pf") { 2858 HasAVX512PF = true; 2859 continue; 2860 } 2861 2862 if (Feature == "avx512dq") { 2863 HasAVX512DQ = true; 2864 continue; 2865 } 2866 2867 if (Feature == "avx512bw") { 2868 HasAVX512BW = true; 2869 continue; 2870 } 2871 2872 if (Feature == "avx512vl") { 2873 HasAVX512VL = true; 2874 continue; 2875 } 2876 2877 if (Feature == "sha") { 2878 HasSHA = true; 2879 continue; 2880 } 2881 2882 if (Feature == "cx16") { 2883 HasCX16 = true; 2884 continue; 2885 } 2886 2887 assert(Features[i][0] == '+' && "Invalid target feature!"); 2888 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2889 .Case("avx512f", AVX512F) 2890 .Case("avx2", AVX2) 2891 .Case("avx", AVX) 2892 .Case("sse4.2", SSE42) 2893 .Case("sse4.1", SSE41) 2894 .Case("ssse3", SSSE3) 2895 .Case("sse3", SSE3) 2896 .Case("sse2", SSE2) 2897 .Case("sse", SSE1) 2898 .Default(NoSSE); 2899 SSELevel = std::max(SSELevel, Level); 2900 2901 MMX3DNowEnum ThreeDNowLevel = 2902 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2903 .Case("3dnowa", AMD3DNowAthlon) 2904 .Case("3dnow", AMD3DNow) 2905 .Case("mmx", MMX) 2906 .Default(NoMMX3DNow); 2907 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2908 2909 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2910 .Case("xop", XOP) 2911 .Case("fma4", FMA4) 2912 .Case("sse4a", SSE4A) 2913 .Default(NoXOP); 2914 XOPLevel = std::max(XOPLevel, XLevel); 2915 } 2916 2917 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2918 // Can't do this earlier because we need to be able to explicitly enable 2919 // popcnt and still disable sse4.2. 2920 if (!HasPOPCNT && SSELevel >= SSE42 && 2921 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2922 HasPOPCNT = true; 2923 Features.push_back("+popcnt"); 2924 } 2925 2926 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2927 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2928 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2929 HasPRFCHW = true; 2930 Features.push_back("+prfchw"); 2931 } 2932 2933 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2934 // matches the selected sse level. 2935 if (FPMath == FP_SSE && SSELevel < SSE1) { 2936 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2937 return false; 2938 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2939 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2940 return false; 2941 } 2942 2943 // Don't tell the backend if we're turning off mmx; it will end up disabling 2944 // SSE, which we don't want. 2945 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2946 // then enable MMX. 2947 std::vector<std::string>::iterator it; 2948 it = std::find(Features.begin(), Features.end(), "-mmx"); 2949 if (it != Features.end()) 2950 Features.erase(it); 2951 else if (SSELevel > NoSSE) 2952 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2953 return true; 2954 } 2955 2956 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2957 /// definitions for this particular subtarget. 2958 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2959 MacroBuilder &Builder) const { 2960 // Target identification. 2961 if (getTriple().getArch() == llvm::Triple::x86_64) { 2962 Builder.defineMacro("__amd64__"); 2963 Builder.defineMacro("__amd64"); 2964 Builder.defineMacro("__x86_64"); 2965 Builder.defineMacro("__x86_64__"); 2966 if (getTriple().getArchName() == "x86_64h") { 2967 Builder.defineMacro("__x86_64h"); 2968 Builder.defineMacro("__x86_64h__"); 2969 } 2970 } else { 2971 DefineStd(Builder, "i386", Opts); 2972 } 2973 2974 // Subtarget options. 2975 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2976 // truly should be based on -mtune options. 2977 switch (CPU) { 2978 case CK_Generic: 2979 break; 2980 case CK_i386: 2981 // The rest are coming from the i386 define above. 2982 Builder.defineMacro("__tune_i386__"); 2983 break; 2984 case CK_i486: 2985 case CK_WinChipC6: 2986 case CK_WinChip2: 2987 case CK_C3: 2988 defineCPUMacros(Builder, "i486"); 2989 break; 2990 case CK_PentiumMMX: 2991 Builder.defineMacro("__pentium_mmx__"); 2992 Builder.defineMacro("__tune_pentium_mmx__"); 2993 // Fallthrough 2994 case CK_i586: 2995 case CK_Pentium: 2996 defineCPUMacros(Builder, "i586"); 2997 defineCPUMacros(Builder, "pentium"); 2998 break; 2999 case CK_Pentium3: 3000 case CK_Pentium3M: 3001 case CK_PentiumM: 3002 Builder.defineMacro("__tune_pentium3__"); 3003 // Fallthrough 3004 case CK_Pentium2: 3005 case CK_C3_2: 3006 Builder.defineMacro("__tune_pentium2__"); 3007 // Fallthrough 3008 case CK_PentiumPro: 3009 Builder.defineMacro("__tune_i686__"); 3010 Builder.defineMacro("__tune_pentiumpro__"); 3011 // Fallthrough 3012 case CK_i686: 3013 Builder.defineMacro("__i686"); 3014 Builder.defineMacro("__i686__"); 3015 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3016 Builder.defineMacro("__pentiumpro"); 3017 Builder.defineMacro("__pentiumpro__"); 3018 break; 3019 case CK_Pentium4: 3020 case CK_Pentium4M: 3021 defineCPUMacros(Builder, "pentium4"); 3022 break; 3023 case CK_Yonah: 3024 case CK_Prescott: 3025 case CK_Nocona: 3026 defineCPUMacros(Builder, "nocona"); 3027 break; 3028 case CK_Core2: 3029 case CK_Penryn: 3030 defineCPUMacros(Builder, "core2"); 3031 break; 3032 case CK_Bonnell: 3033 defineCPUMacros(Builder, "atom"); 3034 break; 3035 case CK_Silvermont: 3036 defineCPUMacros(Builder, "slm"); 3037 break; 3038 case CK_Nehalem: 3039 case CK_Westmere: 3040 case CK_SandyBridge: 3041 case CK_IvyBridge: 3042 case CK_Haswell: 3043 case CK_Broadwell: 3044 // FIXME: Historically, we defined this legacy name, it would be nice to 3045 // remove it at some point. We've never exposed fine-grained names for 3046 // recent primary x86 CPUs, and we should keep it that way. 3047 defineCPUMacros(Builder, "corei7"); 3048 break; 3049 case CK_Skylake: 3050 // FIXME: Historically, we defined this legacy name, it would be nice to 3051 // remove it at some point. This is the only fine-grained CPU macro in the 3052 // main intel CPU line, and it would be better to not have these and force 3053 // people to use ISA macros. 3054 defineCPUMacros(Builder, "skx"); 3055 break; 3056 case CK_KNL: 3057 defineCPUMacros(Builder, "knl"); 3058 break; 3059 case CK_K6_2: 3060 Builder.defineMacro("__k6_2__"); 3061 Builder.defineMacro("__tune_k6_2__"); 3062 // Fallthrough 3063 case CK_K6_3: 3064 if (CPU != CK_K6_2) { // In case of fallthrough 3065 // FIXME: GCC may be enabling these in cases where some other k6 3066 // architecture is specified but -m3dnow is explicitly provided. The 3067 // exact semantics need to be determined and emulated here. 3068 Builder.defineMacro("__k6_3__"); 3069 Builder.defineMacro("__tune_k6_3__"); 3070 } 3071 // Fallthrough 3072 case CK_K6: 3073 defineCPUMacros(Builder, "k6"); 3074 break; 3075 case CK_Athlon: 3076 case CK_AthlonThunderbird: 3077 case CK_Athlon4: 3078 case CK_AthlonXP: 3079 case CK_AthlonMP: 3080 defineCPUMacros(Builder, "athlon"); 3081 if (SSELevel != NoSSE) { 3082 Builder.defineMacro("__athlon_sse__"); 3083 Builder.defineMacro("__tune_athlon_sse__"); 3084 } 3085 break; 3086 case CK_K8: 3087 case CK_K8SSE3: 3088 case CK_x86_64: 3089 case CK_Opteron: 3090 case CK_OpteronSSE3: 3091 case CK_Athlon64: 3092 case CK_Athlon64SSE3: 3093 case CK_AthlonFX: 3094 defineCPUMacros(Builder, "k8"); 3095 break; 3096 case CK_AMDFAM10: 3097 defineCPUMacros(Builder, "amdfam10"); 3098 break; 3099 case CK_BTVER1: 3100 defineCPUMacros(Builder, "btver1"); 3101 break; 3102 case CK_BTVER2: 3103 defineCPUMacros(Builder, "btver2"); 3104 break; 3105 case CK_BDVER1: 3106 defineCPUMacros(Builder, "bdver1"); 3107 break; 3108 case CK_BDVER2: 3109 defineCPUMacros(Builder, "bdver2"); 3110 break; 3111 case CK_BDVER3: 3112 defineCPUMacros(Builder, "bdver3"); 3113 break; 3114 case CK_BDVER4: 3115 defineCPUMacros(Builder, "bdver4"); 3116 break; 3117 case CK_Geode: 3118 defineCPUMacros(Builder, "geode"); 3119 break; 3120 } 3121 3122 // Target properties. 3123 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3124 3125 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3126 // functions in glibc header files that use FP Stack inline asm which the 3127 // backend can't deal with (PR879). 3128 Builder.defineMacro("__NO_MATH_INLINES"); 3129 3130 if (HasAES) 3131 Builder.defineMacro("__AES__"); 3132 3133 if (HasPCLMUL) 3134 Builder.defineMacro("__PCLMUL__"); 3135 3136 if (HasLZCNT) 3137 Builder.defineMacro("__LZCNT__"); 3138 3139 if (HasRDRND) 3140 Builder.defineMacro("__RDRND__"); 3141 3142 if (HasFSGSBASE) 3143 Builder.defineMacro("__FSGSBASE__"); 3144 3145 if (HasBMI) 3146 Builder.defineMacro("__BMI__"); 3147 3148 if (HasBMI2) 3149 Builder.defineMacro("__BMI2__"); 3150 3151 if (HasPOPCNT) 3152 Builder.defineMacro("__POPCNT__"); 3153 3154 if (HasRTM) 3155 Builder.defineMacro("__RTM__"); 3156 3157 if (HasPRFCHW) 3158 Builder.defineMacro("__PRFCHW__"); 3159 3160 if (HasRDSEED) 3161 Builder.defineMacro("__RDSEED__"); 3162 3163 if (HasADX) 3164 Builder.defineMacro("__ADX__"); 3165 3166 if (HasTBM) 3167 Builder.defineMacro("__TBM__"); 3168 3169 switch (XOPLevel) { 3170 case XOP: 3171 Builder.defineMacro("__XOP__"); 3172 case FMA4: 3173 Builder.defineMacro("__FMA4__"); 3174 case SSE4A: 3175 Builder.defineMacro("__SSE4A__"); 3176 case NoXOP: 3177 break; 3178 } 3179 3180 if (HasFMA) 3181 Builder.defineMacro("__FMA__"); 3182 3183 if (HasF16C) 3184 Builder.defineMacro("__F16C__"); 3185 3186 if (HasAVX512CD) 3187 Builder.defineMacro("__AVX512CD__"); 3188 if (HasAVX512ER) 3189 Builder.defineMacro("__AVX512ER__"); 3190 if (HasAVX512PF) 3191 Builder.defineMacro("__AVX512PF__"); 3192 if (HasAVX512DQ) 3193 Builder.defineMacro("__AVX512DQ__"); 3194 if (HasAVX512BW) 3195 Builder.defineMacro("__AVX512BW__"); 3196 if (HasAVX512VL) 3197 Builder.defineMacro("__AVX512VL__"); 3198 3199 if (HasSHA) 3200 Builder.defineMacro("__SHA__"); 3201 3202 if (HasCX16) 3203 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3204 3205 // Each case falls through to the previous one here. 3206 switch (SSELevel) { 3207 case AVX512F: 3208 Builder.defineMacro("__AVX512F__"); 3209 case AVX2: 3210 Builder.defineMacro("__AVX2__"); 3211 case AVX: 3212 Builder.defineMacro("__AVX__"); 3213 case SSE42: 3214 Builder.defineMacro("__SSE4_2__"); 3215 case SSE41: 3216 Builder.defineMacro("__SSE4_1__"); 3217 case SSSE3: 3218 Builder.defineMacro("__SSSE3__"); 3219 case SSE3: 3220 Builder.defineMacro("__SSE3__"); 3221 case SSE2: 3222 Builder.defineMacro("__SSE2__"); 3223 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3224 case SSE1: 3225 Builder.defineMacro("__SSE__"); 3226 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3227 case NoSSE: 3228 break; 3229 } 3230 3231 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3232 switch (SSELevel) { 3233 case AVX512F: 3234 case AVX2: 3235 case AVX: 3236 case SSE42: 3237 case SSE41: 3238 case SSSE3: 3239 case SSE3: 3240 case SSE2: 3241 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3242 break; 3243 case SSE1: 3244 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3245 break; 3246 default: 3247 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3248 } 3249 } 3250 3251 // Each case falls through to the previous one here. 3252 switch (MMX3DNowLevel) { 3253 case AMD3DNowAthlon: 3254 Builder.defineMacro("__3dNOW_A__"); 3255 case AMD3DNow: 3256 Builder.defineMacro("__3dNOW__"); 3257 case MMX: 3258 Builder.defineMacro("__MMX__"); 3259 case NoMMX3DNow: 3260 break; 3261 } 3262 3263 if (CPU >= CK_i486) { 3264 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3265 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3266 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3267 } 3268 if (CPU >= CK_i586) 3269 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3270 } 3271 3272 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3273 return llvm::StringSwitch<bool>(Feature) 3274 .Case("aes", HasAES) 3275 .Case("avx", SSELevel >= AVX) 3276 .Case("avx2", SSELevel >= AVX2) 3277 .Case("avx512f", SSELevel >= AVX512F) 3278 .Case("avx512cd", HasAVX512CD) 3279 .Case("avx512er", HasAVX512ER) 3280 .Case("avx512pf", HasAVX512PF) 3281 .Case("avx512dq", HasAVX512DQ) 3282 .Case("avx512bw", HasAVX512BW) 3283 .Case("avx512vl", HasAVX512VL) 3284 .Case("bmi", HasBMI) 3285 .Case("bmi2", HasBMI2) 3286 .Case("cx16", HasCX16) 3287 .Case("f16c", HasF16C) 3288 .Case("fma", HasFMA) 3289 .Case("fma4", XOPLevel >= FMA4) 3290 .Case("fsgsbase", HasFSGSBASE) 3291 .Case("lzcnt", HasLZCNT) 3292 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3293 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3294 .Case("mmx", MMX3DNowLevel >= MMX) 3295 .Case("pclmul", HasPCLMUL) 3296 .Case("popcnt", HasPOPCNT) 3297 .Case("prfchw", HasPRFCHW) 3298 .Case("rdrnd", HasRDRND) 3299 .Case("rdseed", HasRDSEED) 3300 .Case("rtm", HasRTM) 3301 .Case("sha", HasSHA) 3302 .Case("sse", SSELevel >= SSE1) 3303 .Case("sse2", SSELevel >= SSE2) 3304 .Case("sse3", SSELevel >= SSE3) 3305 .Case("ssse3", SSELevel >= SSSE3) 3306 .Case("sse4.1", SSELevel >= SSE41) 3307 .Case("sse4.2", SSELevel >= SSE42) 3308 .Case("sse4a", XOPLevel >= SSE4A) 3309 .Case("tbm", HasTBM) 3310 .Case("x86", true) 3311 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3312 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3313 .Case("xop", XOPLevel >= XOP) 3314 .Default(false); 3315 } 3316 3317 bool 3318 X86TargetInfo::validateAsmConstraint(const char *&Name, 3319 TargetInfo::ConstraintInfo &Info) const { 3320 switch (*Name) { 3321 default: return false; 3322 case 'I': 3323 Info.setRequiresImmediate(0, 31); 3324 return true; 3325 case 'J': 3326 Info.setRequiresImmediate(0, 63); 3327 return true; 3328 case 'K': 3329 Info.setRequiresImmediate(-128, 127); 3330 return true; 3331 case 'L': 3332 // FIXME: properly analyze this constraint: 3333 // must be one of 0xff, 0xffff, or 0xffffffff 3334 return true; 3335 case 'M': 3336 Info.setRequiresImmediate(0, 3); 3337 return true; 3338 case 'N': 3339 Info.setRequiresImmediate(0, 255); 3340 return true; 3341 case 'O': 3342 Info.setRequiresImmediate(0, 127); 3343 return true; 3344 case 'Y': // first letter of a pair: 3345 switch (*(Name+1)) { 3346 default: return false; 3347 case '0': // First SSE register. 3348 case 't': // Any SSE register, when SSE2 is enabled. 3349 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3350 case 'm': // any MMX register, when inter-unit moves enabled. 3351 break; // falls through to setAllowsRegister. 3352 } 3353 case 'f': // any x87 floating point stack register. 3354 // Constraint 'f' cannot be used for output operands. 3355 if (Info.ConstraintStr[0] == '=') 3356 return false; 3357 3358 Info.setAllowsRegister(); 3359 return true; 3360 case 'a': // eax. 3361 case 'b': // ebx. 3362 case 'c': // ecx. 3363 case 'd': // edx. 3364 case 'S': // esi. 3365 case 'D': // edi. 3366 case 'A': // edx:eax. 3367 case 't': // top of floating point stack. 3368 case 'u': // second from top of floating point stack. 3369 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3370 case 'y': // Any MMX register. 3371 case 'x': // Any SSE register. 3372 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3373 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3374 case 'l': // "Index" registers: any general register that can be used as an 3375 // index in a base+index memory access. 3376 Info.setAllowsRegister(); 3377 return true; 3378 case 'C': // SSE floating point constant. 3379 case 'G': // x87 floating point constant. 3380 case 'e': // 32-bit signed integer constant for use with zero-extending 3381 // x86_64 instructions. 3382 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3383 // x86_64 instructions. 3384 return true; 3385 } 3386 } 3387 3388 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3389 unsigned Size) const { 3390 // Strip off constraint modifiers. 3391 while (Constraint[0] == '=' || 3392 Constraint[0] == '+' || 3393 Constraint[0] == '&') 3394 Constraint = Constraint.substr(1); 3395 3396 return validateOperandSize(Constraint, Size); 3397 } 3398 3399 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3400 unsigned Size) const { 3401 return validateOperandSize(Constraint, Size); 3402 } 3403 3404 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3405 unsigned Size) const { 3406 switch (Constraint[0]) { 3407 default: break; 3408 case 'y': 3409 return Size <= 64; 3410 case 'f': 3411 case 't': 3412 case 'u': 3413 return Size <= 128; 3414 case 'x': 3415 // 256-bit ymm registers can be used if target supports AVX. 3416 return Size <= (SSELevel >= AVX ? 256U : 128U); 3417 } 3418 3419 return true; 3420 } 3421 3422 std::string 3423 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3424 switch (*Constraint) { 3425 case 'a': return std::string("{ax}"); 3426 case 'b': return std::string("{bx}"); 3427 case 'c': return std::string("{cx}"); 3428 case 'd': return std::string("{dx}"); 3429 case 'S': return std::string("{si}"); 3430 case 'D': return std::string("{di}"); 3431 case 'p': // address 3432 return std::string("im"); 3433 case 't': // top of floating point stack. 3434 return std::string("{st}"); 3435 case 'u': // second from top of floating point stack. 3436 return std::string("{st(1)}"); // second from top of floating point stack. 3437 default: 3438 return std::string(1, *Constraint); 3439 } 3440 } 3441 3442 // X86-32 generic target 3443 class X86_32TargetInfo : public X86TargetInfo { 3444 public: 3445 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3446 DoubleAlign = LongLongAlign = 32; 3447 LongDoubleWidth = 96; 3448 LongDoubleAlign = 32; 3449 SuitableAlign = 128; 3450 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3451 SizeType = UnsignedInt; 3452 PtrDiffType = SignedInt; 3453 IntPtrType = SignedInt; 3454 RegParmMax = 3; 3455 3456 // Use fpret for all types. 3457 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3458 (1 << TargetInfo::Double) | 3459 (1 << TargetInfo::LongDouble)); 3460 3461 // x86-32 has atomics up to 8 bytes 3462 // FIXME: Check that we actually have cmpxchg8b before setting 3463 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3464 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3465 } 3466 BuiltinVaListKind getBuiltinVaListKind() const override { 3467 return TargetInfo::CharPtrBuiltinVaList; 3468 } 3469 3470 int getEHDataRegisterNumber(unsigned RegNo) const override { 3471 if (RegNo == 0) return 0; 3472 if (RegNo == 1) return 2; 3473 return -1; 3474 } 3475 bool validateOperandSize(StringRef Constraint, 3476 unsigned Size) const override { 3477 switch (Constraint[0]) { 3478 default: break; 3479 case 'R': 3480 case 'q': 3481 case 'Q': 3482 case 'a': 3483 case 'b': 3484 case 'c': 3485 case 'd': 3486 case 'S': 3487 case 'D': 3488 return Size <= 32; 3489 case 'A': 3490 return Size <= 64; 3491 } 3492 3493 return X86TargetInfo::validateOperandSize(Constraint, Size); 3494 } 3495 }; 3496 3497 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3498 public: 3499 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3500 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3501 3502 unsigned getFloatEvalMethod() const override { 3503 unsigned Major, Minor, Micro; 3504 getTriple().getOSVersion(Major, Minor, Micro); 3505 // New NetBSD uses the default rounding mode. 3506 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3507 return X86_32TargetInfo::getFloatEvalMethod(); 3508 // NetBSD before 6.99.26 defaults to "double" rounding. 3509 return 1; 3510 } 3511 }; 3512 3513 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3514 public: 3515 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3516 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3517 SizeType = UnsignedLong; 3518 IntPtrType = SignedLong; 3519 PtrDiffType = SignedLong; 3520 } 3521 }; 3522 3523 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3524 public: 3525 BitrigI386TargetInfo(const llvm::Triple &Triple) 3526 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3527 SizeType = UnsignedLong; 3528 IntPtrType = SignedLong; 3529 PtrDiffType = SignedLong; 3530 } 3531 }; 3532 3533 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3534 public: 3535 DarwinI386TargetInfo(const llvm::Triple &Triple) 3536 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3537 LongDoubleWidth = 128; 3538 LongDoubleAlign = 128; 3539 SuitableAlign = 128; 3540 MaxVectorAlign = 256; 3541 SizeType = UnsignedLong; 3542 IntPtrType = SignedLong; 3543 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3544 HasAlignMac68kSupport = true; 3545 } 3546 3547 }; 3548 3549 // x86-32 Windows target 3550 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3551 public: 3552 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3553 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3554 WCharType = UnsignedShort; 3555 DoubleAlign = LongLongAlign = 64; 3556 bool IsWinCOFF = 3557 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3558 DescriptionString = IsWinCOFF 3559 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3560 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3561 } 3562 void getTargetDefines(const LangOptions &Opts, 3563 MacroBuilder &Builder) const override { 3564 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3565 } 3566 }; 3567 3568 // x86-32 Windows Visual Studio target 3569 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3570 public: 3571 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3572 : WindowsX86_32TargetInfo(Triple) { 3573 LongDoubleWidth = LongDoubleAlign = 64; 3574 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3575 } 3576 void getTargetDefines(const LangOptions &Opts, 3577 MacroBuilder &Builder) const override { 3578 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3579 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3580 // The value of the following reflects processor type. 3581 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3582 // We lost the original triple, so we use the default. 3583 Builder.defineMacro("_M_IX86", "600"); 3584 } 3585 }; 3586 } // end anonymous namespace 3587 3588 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3589 Builder.defineMacro("__MSVCRT__"); 3590 Builder.defineMacro("__MINGW32__"); 3591 3592 // Mingw defines __declspec(a) to __attribute__((a)). Clang supports 3593 // __declspec natively under -fms-extensions, but we define a no-op __declspec 3594 // macro anyway for pre-processor compatibility. 3595 if (Opts.MicrosoftExt) 3596 Builder.defineMacro("__declspec", "__declspec"); 3597 else 3598 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3599 3600 if (!Opts.MicrosoftExt) { 3601 // Provide macros for all the calling convention keywords. Provide both 3602 // single and double underscore prefixed variants. These are available on 3603 // x64 as well as x86, even though they have no effect. 3604 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3605 for (const char *CC : CCs) { 3606 std::string GCCSpelling = "__attribute__((__"; 3607 GCCSpelling += CC; 3608 GCCSpelling += "__))"; 3609 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3610 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3611 } 3612 } 3613 } 3614 3615 namespace { 3616 // x86-32 MinGW target 3617 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3618 public: 3619 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3620 : WindowsX86_32TargetInfo(Triple) {} 3621 void getTargetDefines(const LangOptions &Opts, 3622 MacroBuilder &Builder) const override { 3623 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3624 DefineStd(Builder, "WIN32", Opts); 3625 DefineStd(Builder, "WINNT", Opts); 3626 Builder.defineMacro("_X86_"); 3627 addMinGWDefines(Opts, Builder); 3628 } 3629 }; 3630 3631 // x86-32 Cygwin target 3632 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3633 public: 3634 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3635 : X86_32TargetInfo(Triple) { 3636 TLSSupported = false; 3637 WCharType = UnsignedShort; 3638 DoubleAlign = LongLongAlign = 64; 3639 DescriptionString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3640 } 3641 void getTargetDefines(const LangOptions &Opts, 3642 MacroBuilder &Builder) const override { 3643 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3644 Builder.defineMacro("_X86_"); 3645 Builder.defineMacro("__CYGWIN__"); 3646 Builder.defineMacro("__CYGWIN32__"); 3647 DefineStd(Builder, "unix", Opts); 3648 if (Opts.CPlusPlus) 3649 Builder.defineMacro("_GNU_SOURCE"); 3650 } 3651 }; 3652 3653 // x86-32 Haiku target 3654 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3655 public: 3656 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3657 SizeType = UnsignedLong; 3658 IntPtrType = SignedLong; 3659 PtrDiffType = SignedLong; 3660 ProcessIDType = SignedLong; 3661 this->UserLabelPrefix = ""; 3662 this->TLSSupported = false; 3663 } 3664 void getTargetDefines(const LangOptions &Opts, 3665 MacroBuilder &Builder) const override { 3666 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3667 Builder.defineMacro("__INTEL__"); 3668 Builder.defineMacro("__HAIKU__"); 3669 } 3670 }; 3671 3672 // RTEMS Target 3673 template<typename Target> 3674 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3675 protected: 3676 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3677 MacroBuilder &Builder) const override { 3678 // RTEMS defines; list based off of gcc output 3679 3680 Builder.defineMacro("__rtems__"); 3681 Builder.defineMacro("__ELF__"); 3682 } 3683 3684 public: 3685 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3686 this->UserLabelPrefix = ""; 3687 3688 switch (Triple.getArch()) { 3689 default: 3690 case llvm::Triple::x86: 3691 // this->MCountName = ".mcount"; 3692 break; 3693 case llvm::Triple::mips: 3694 case llvm::Triple::mipsel: 3695 case llvm::Triple::ppc: 3696 case llvm::Triple::ppc64: 3697 case llvm::Triple::ppc64le: 3698 // this->MCountName = "_mcount"; 3699 break; 3700 case llvm::Triple::arm: 3701 // this->MCountName = "__mcount"; 3702 break; 3703 } 3704 } 3705 }; 3706 3707 // x86-32 RTEMS target 3708 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3709 public: 3710 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3711 SizeType = UnsignedLong; 3712 IntPtrType = SignedLong; 3713 PtrDiffType = SignedLong; 3714 this->UserLabelPrefix = ""; 3715 } 3716 void getTargetDefines(const LangOptions &Opts, 3717 MacroBuilder &Builder) const override { 3718 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3719 Builder.defineMacro("__INTEL__"); 3720 Builder.defineMacro("__rtems__"); 3721 } 3722 }; 3723 3724 // x86-64 generic target 3725 class X86_64TargetInfo : public X86TargetInfo { 3726 public: 3727 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3728 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3729 bool IsWinCOFF = 3730 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3731 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3732 LongDoubleWidth = 128; 3733 LongDoubleAlign = 128; 3734 LargeArrayMinWidth = 128; 3735 LargeArrayAlign = 128; 3736 SuitableAlign = 128; 3737 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3738 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3739 IntPtrType = IsX32 ? SignedInt : SignedLong; 3740 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3741 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3742 RegParmMax = 6; 3743 3744 // Pointers are 32-bit in x32. 3745 DescriptionString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3746 : IsWinCOFF 3747 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 3748 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3749 3750 // Use fpret only for long double. 3751 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3752 3753 // Use fp2ret for _Complex long double. 3754 ComplexLongDoubleUsesFP2Ret = true; 3755 3756 // x86-64 has atomics up to 16 bytes. 3757 MaxAtomicPromoteWidth = 128; 3758 MaxAtomicInlineWidth = 128; 3759 } 3760 BuiltinVaListKind getBuiltinVaListKind() const override { 3761 return TargetInfo::X86_64ABIBuiltinVaList; 3762 } 3763 3764 int getEHDataRegisterNumber(unsigned RegNo) const override { 3765 if (RegNo == 0) return 0; 3766 if (RegNo == 1) return 1; 3767 return -1; 3768 } 3769 3770 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3771 return (CC == CC_C || 3772 CC == CC_X86VectorCall || 3773 CC == CC_IntelOclBicc || 3774 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3775 } 3776 3777 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3778 return CC_C; 3779 } 3780 3781 // for x32 we need it here explicitly 3782 bool hasInt128Type() const override { return true; } 3783 }; 3784 3785 // x86-64 Windows target 3786 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3787 public: 3788 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3789 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3790 WCharType = UnsignedShort; 3791 LongWidth = LongAlign = 32; 3792 DoubleAlign = LongLongAlign = 64; 3793 IntMaxType = SignedLongLong; 3794 Int64Type = SignedLongLong; 3795 SizeType = UnsignedLongLong; 3796 PtrDiffType = SignedLongLong; 3797 IntPtrType = SignedLongLong; 3798 this->UserLabelPrefix = ""; 3799 } 3800 3801 void getTargetDefines(const LangOptions &Opts, 3802 MacroBuilder &Builder) const override { 3803 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3804 Builder.defineMacro("_WIN64"); 3805 } 3806 3807 BuiltinVaListKind getBuiltinVaListKind() const override { 3808 return TargetInfo::CharPtrBuiltinVaList; 3809 } 3810 3811 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3812 switch (CC) { 3813 case CC_X86StdCall: 3814 case CC_X86ThisCall: 3815 case CC_X86FastCall: 3816 return CCCR_Ignore; 3817 case CC_C: 3818 case CC_X86VectorCall: 3819 case CC_IntelOclBicc: 3820 case CC_X86_64SysV: 3821 return CCCR_OK; 3822 default: 3823 return CCCR_Warning; 3824 } 3825 } 3826 }; 3827 3828 // x86-64 Windows Visual Studio target 3829 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 3830 public: 3831 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 3832 : WindowsX86_64TargetInfo(Triple) { 3833 LongDoubleWidth = LongDoubleAlign = 64; 3834 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3835 } 3836 void getTargetDefines(const LangOptions &Opts, 3837 MacroBuilder &Builder) const override { 3838 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3839 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3840 Builder.defineMacro("_M_X64"); 3841 Builder.defineMacro("_M_AMD64"); 3842 } 3843 }; 3844 3845 // x86-64 MinGW target 3846 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3847 public: 3848 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3849 : WindowsX86_64TargetInfo(Triple) {} 3850 void getTargetDefines(const LangOptions &Opts, 3851 MacroBuilder &Builder) const override { 3852 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3853 DefineStd(Builder, "WIN64", Opts); 3854 Builder.defineMacro("__MINGW64__"); 3855 addMinGWDefines(Opts, Builder); 3856 3857 // GCC defines this macro when it is using __gxx_personality_seh0. 3858 if (!Opts.SjLjExceptions) 3859 Builder.defineMacro("__SEH__"); 3860 } 3861 }; 3862 3863 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3864 public: 3865 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3866 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3867 Int64Type = SignedLongLong; 3868 MaxVectorAlign = 256; 3869 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 3870 llvm::Triple T = llvm::Triple(Triple); 3871 if (T.isiOS()) 3872 UseSignedCharForObjCBool = false; 3873 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 3874 } 3875 }; 3876 3877 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3878 public: 3879 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3880 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3881 IntMaxType = SignedLongLong; 3882 Int64Type = SignedLongLong; 3883 } 3884 }; 3885 3886 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3887 public: 3888 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3889 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3890 IntMaxType = SignedLongLong; 3891 Int64Type = SignedLongLong; 3892 } 3893 }; 3894 3895 class ARMTargetInfo : public TargetInfo { 3896 // Possible FPU choices. 3897 enum FPUMode { 3898 VFP2FPU = (1 << 0), 3899 VFP3FPU = (1 << 1), 3900 VFP4FPU = (1 << 2), 3901 NeonFPU = (1 << 3), 3902 FPARMV8 = (1 << 4) 3903 }; 3904 3905 // Possible HWDiv features. 3906 enum HWDivMode { 3907 HWDivThumb = (1 << 0), 3908 HWDivARM = (1 << 1) 3909 }; 3910 3911 static bool FPUModeIsVFP(FPUMode Mode) { 3912 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 3913 } 3914 3915 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3916 static const char * const GCCRegNames[]; 3917 3918 std::string ABI, CPU; 3919 3920 enum { 3921 FP_Default, 3922 FP_VFP, 3923 FP_Neon 3924 } FPMath; 3925 3926 unsigned FPU : 5; 3927 3928 unsigned IsAAPCS : 1; 3929 unsigned IsThumb : 1; 3930 unsigned HWDiv : 2; 3931 3932 // Initialized via features. 3933 unsigned SoftFloat : 1; 3934 unsigned SoftFloatABI : 1; 3935 3936 unsigned CRC : 1; 3937 unsigned Crypto : 1; 3938 3939 // ACLE 6.5.1 Hardware floating point 3940 enum { 3941 HW_FP_HP = (1 << 1), /// half (16-bit) 3942 HW_FP_SP = (1 << 2), /// single (32-bit) 3943 HW_FP_DP = (1 << 3), /// double (64-bit) 3944 }; 3945 uint32_t HW_FP; 3946 3947 static const Builtin::Info BuiltinInfo[]; 3948 3949 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3950 StringRef ArchName = T.getArchName(); 3951 if (T.getArch() == llvm::Triple::arm || 3952 T.getArch() == llvm::Triple::armeb) { 3953 StringRef VersionStr; 3954 if (ArchName.startswith("armv")) 3955 VersionStr = ArchName.substr(4, 1); 3956 else if (ArchName.startswith("armebv")) 3957 VersionStr = ArchName.substr(6, 1); 3958 else 3959 return false; 3960 unsigned Version; 3961 if (VersionStr.getAsInteger(10, Version)) 3962 return false; 3963 return Version >= 6; 3964 } 3965 assert(T.getArch() == llvm::Triple::thumb || 3966 T.getArch() == llvm::Triple::thumbeb); 3967 StringRef VersionStr; 3968 if (ArchName.startswith("thumbv")) 3969 VersionStr = ArchName.substr(6, 1); 3970 else if (ArchName.startswith("thumbebv")) 3971 VersionStr = ArchName.substr(8, 1); 3972 else 3973 return false; 3974 unsigned Version; 3975 if (VersionStr.getAsInteger(10, Version)) 3976 return false; 3977 return Version >= 7; 3978 } 3979 3980 void setABIAAPCS() { 3981 IsAAPCS = true; 3982 3983 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 3984 const llvm::Triple &T = getTriple(); 3985 3986 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 3987 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 3988 T.getOS() == llvm::Triple::Bitrig) 3989 SizeType = UnsignedLong; 3990 else 3991 SizeType = UnsignedInt; 3992 3993 switch (T.getOS()) { 3994 case llvm::Triple::NetBSD: 3995 WCharType = SignedInt; 3996 break; 3997 case llvm::Triple::Win32: 3998 WCharType = UnsignedShort; 3999 break; 4000 case llvm::Triple::Linux: 4001 default: 4002 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4003 WCharType = UnsignedInt; 4004 break; 4005 } 4006 4007 UseBitFieldTypeAlignment = true; 4008 4009 ZeroLengthBitfieldBoundary = 0; 4010 4011 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4012 // so set preferred for small types to 32. 4013 if (T.isOSBinFormatMachO()) { 4014 DescriptionString = 4015 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4016 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4017 } else if (T.isOSWindows()) { 4018 assert(!BigEndian && "Windows on ARM does not support big endian"); 4019 DescriptionString = "e" 4020 "-m:w" 4021 "-p:32:32" 4022 "-i64:64" 4023 "-v128:64:128" 4024 "-a:0:32" 4025 "-n32" 4026 "-S64"; 4027 } else if (T.isOSNaCl()) { 4028 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4029 DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 4030 } else { 4031 DescriptionString = 4032 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4033 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4034 } 4035 4036 // FIXME: Enumerated types are variable width in straight AAPCS. 4037 } 4038 4039 void setABIAPCS() { 4040 const llvm::Triple &T = getTriple(); 4041 4042 IsAAPCS = false; 4043 4044 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4045 4046 // size_t is unsigned int on FreeBSD. 4047 if (T.getOS() == llvm::Triple::FreeBSD) 4048 SizeType = UnsignedInt; 4049 else 4050 SizeType = UnsignedLong; 4051 4052 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4053 WCharType = SignedInt; 4054 4055 // Do not respect the alignment of bit-field types when laying out 4056 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4057 UseBitFieldTypeAlignment = false; 4058 4059 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4060 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4061 /// gcc. 4062 ZeroLengthBitfieldBoundary = 32; 4063 4064 if (T.isOSBinFormatMachO()) 4065 DescriptionString = 4066 BigEndian 4067 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4068 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4069 else 4070 DescriptionString = 4071 BigEndian 4072 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4073 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4074 4075 // FIXME: Override "preferred align" for double and long long. 4076 } 4077 4078 public: 4079 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4080 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 4081 IsAAPCS(true), HW_FP(0) { 4082 BigEndian = IsBigEndian; 4083 4084 switch (getTriple().getOS()) { 4085 case llvm::Triple::NetBSD: 4086 PtrDiffType = SignedLong; 4087 break; 4088 default: 4089 PtrDiffType = SignedInt; 4090 break; 4091 } 4092 4093 // {} in inline assembly are neon specifiers, not assembly variant 4094 // specifiers. 4095 NoAsmVariants = true; 4096 4097 // FIXME: Should we just treat this as a feature? 4098 IsThumb = getTriple().getArchName().startswith("thumb"); 4099 4100 // FIXME: This duplicates code from the driver that sets the -target-abi 4101 // option - this code is used if -target-abi isn't passed and should 4102 // be unified in some way. 4103 if (Triple.isOSBinFormatMachO()) { 4104 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4105 // the frontend matches that. 4106 if (Triple.getEnvironment() == llvm::Triple::EABI || 4107 Triple.getOS() == llvm::Triple::UnknownOS || 4108 StringRef(CPU).startswith("cortex-m")) { 4109 setABI("aapcs"); 4110 } else { 4111 setABI("apcs-gnu"); 4112 } 4113 } else if (Triple.isOSWindows()) { 4114 // FIXME: this is invalid for WindowsCE 4115 setABI("aapcs"); 4116 } else { 4117 // Select the default based on the platform. 4118 switch (Triple.getEnvironment()) { 4119 case llvm::Triple::Android: 4120 case llvm::Triple::GNUEABI: 4121 case llvm::Triple::GNUEABIHF: 4122 setABI("aapcs-linux"); 4123 break; 4124 case llvm::Triple::EABIHF: 4125 case llvm::Triple::EABI: 4126 setABI("aapcs"); 4127 break; 4128 case llvm::Triple::GNU: 4129 setABI("apcs-gnu"); 4130 break; 4131 default: 4132 if (Triple.getOS() == llvm::Triple::NetBSD) 4133 setABI("apcs-gnu"); 4134 else 4135 setABI("aapcs"); 4136 break; 4137 } 4138 } 4139 4140 // ARM targets default to using the ARM C++ ABI. 4141 TheCXXABI.set(TargetCXXABI::GenericARM); 4142 4143 // ARM has atomics up to 8 bytes 4144 MaxAtomicPromoteWidth = 64; 4145 if (shouldUseInlineAtomic(getTriple())) 4146 MaxAtomicInlineWidth = 64; 4147 4148 // Do force alignment of members that follow zero length bitfields. If 4149 // the alignment of the zero-length bitfield is greater than the member 4150 // that follows it, `bar', `bar' will be aligned as the type of the 4151 // zero length bitfield. 4152 UseZeroLengthBitfieldAlignment = true; 4153 } 4154 StringRef getABI() const override { return ABI; } 4155 bool setABI(const std::string &Name) override { 4156 ABI = Name; 4157 4158 // The defaults (above) are for AAPCS, check if we need to change them. 4159 // 4160 // FIXME: We need support for -meabi... we could just mangle it into the 4161 // name. 4162 if (Name == "apcs-gnu") { 4163 setABIAPCS(); 4164 return true; 4165 } 4166 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4167 setABIAAPCS(); 4168 return true; 4169 } 4170 return false; 4171 } 4172 4173 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 4174 StringRef ArchName = getTriple().getArchName(); 4175 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 4176 Features["vfp2"] = true; 4177 else if (CPU == "cortex-a8" || CPU == "cortex-a9") { 4178 Features["vfp3"] = true; 4179 Features["neon"] = true; 4180 } 4181 else if (CPU == "cortex-a5") { 4182 Features["vfp4"] = true; 4183 Features["neon"] = true; 4184 } else if (CPU == "swift" || CPU == "cortex-a7" || 4185 CPU == "cortex-a12" || CPU == "cortex-a15" || 4186 CPU == "cortex-a17" || CPU == "krait") { 4187 Features["vfp4"] = true; 4188 Features["neon"] = true; 4189 Features["hwdiv"] = true; 4190 Features["hwdiv-arm"] = true; 4191 } else if (CPU == "cyclone" || CPU == "cortex-a53" || CPU == "cortex-a57" || 4192 CPU == "cortex-a72") { 4193 Features["fp-armv8"] = true; 4194 Features["neon"] = true; 4195 Features["hwdiv"] = true; 4196 Features["hwdiv-arm"] = true; 4197 Features["crc"] = true; 4198 Features["crypto"] = true; 4199 } else if (CPU == "cortex-r5" || CPU == "cortex-r7" || 4200 // Enable the hwdiv extension for all v8a AArch32 cores by 4201 // default. 4202 ArchName == "armv8a" || ArchName == "armv8" || 4203 ArchName == "armebv8a" || ArchName == "armebv8" || 4204 ArchName == "thumbv8a" || ArchName == "thumbv8" || 4205 ArchName == "thumbebv8a" || ArchName == "thumbebv8") { 4206 Features["hwdiv"] = true; 4207 Features["hwdiv-arm"] = true; 4208 } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" || 4209 CPU == "sc300" || CPU == "cortex-r4" || CPU == "cortex-r4f") { 4210 Features["hwdiv"] = true; 4211 } 4212 } 4213 4214 bool handleTargetFeatures(std::vector<std::string> &Features, 4215 DiagnosticsEngine &Diags) override { 4216 FPU = 0; 4217 CRC = 0; 4218 Crypto = 0; 4219 SoftFloat = SoftFloatABI = false; 4220 HWDiv = 0; 4221 4222 for (const auto &Feature : Features) { 4223 if (Feature == "+soft-float") { 4224 SoftFloat = true; 4225 } else if (Feature == "+soft-float-abi") { 4226 SoftFloatABI = true; 4227 } else if (Feature == "+vfp2") { 4228 FPU |= VFP2FPU; 4229 HW_FP = HW_FP_SP | HW_FP_DP; 4230 } else if (Feature == "+vfp3") { 4231 FPU |= VFP3FPU; 4232 HW_FP = HW_FP_SP | HW_FP_DP; 4233 } else if (Feature == "+vfp4") { 4234 FPU |= VFP4FPU; 4235 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP; 4236 } else if (Feature == "+fp-armv8") { 4237 FPU |= FPARMV8; 4238 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP; 4239 } else if (Feature == "+neon") { 4240 FPU |= NeonFPU; 4241 HW_FP = HW_FP_SP | HW_FP_DP; 4242 } else if (Feature == "+hwdiv") { 4243 HWDiv |= HWDivThumb; 4244 } else if (Feature == "+hwdiv-arm") { 4245 HWDiv |= HWDivARM; 4246 } else if (Feature == "+crc") { 4247 CRC = 1; 4248 } else if (Feature == "+crypto") { 4249 Crypto = 1; 4250 } else if (Feature == "+fp-only-sp") { 4251 HW_FP &= ~HW_FP_DP; 4252 } 4253 } 4254 4255 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4256 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4257 return false; 4258 } 4259 4260 if (FPMath == FP_Neon) 4261 Features.push_back("+neonfp"); 4262 else if (FPMath == FP_VFP) 4263 Features.push_back("-neonfp"); 4264 4265 // Remove front-end specific options which the backend handles differently. 4266 const StringRef FrontEndFeatures[] = { "+soft-float", "+soft-float-abi" }; 4267 for (const auto &FEFeature : FrontEndFeatures) { 4268 auto Feature = std::find(Features.begin(), Features.end(), FEFeature); 4269 if (Feature != Features.end()) 4270 Features.erase(Feature); 4271 } 4272 4273 return true; 4274 } 4275 4276 bool hasFeature(StringRef Feature) const override { 4277 return llvm::StringSwitch<bool>(Feature) 4278 .Case("arm", true) 4279 .Case("softfloat", SoftFloat) 4280 .Case("thumb", IsThumb) 4281 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4282 .Case("hwdiv", HWDiv & HWDivThumb) 4283 .Case("hwdiv-arm", HWDiv & HWDivARM) 4284 .Default(false); 4285 } 4286 // FIXME: Should we actually have some table instead of these switches? 4287 static const char *getCPUDefineSuffix(StringRef Name) { 4288 return llvm::StringSwitch<const char *>(Name) 4289 .Cases("arm8", "arm810", "4") 4290 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", 4291 "4") 4292 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 4293 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 4294 .Case("ep9312", "4T") 4295 .Cases("arm10tdmi", "arm1020t", "5T") 4296 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 4297 .Case("arm926ej-s", "5TEJ") 4298 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 4299 .Cases("xscale", "iwmmxt", "5TE") 4300 .Case("arm1136j-s", "6J") 4301 .Case("arm1136jf-s", "6") 4302 .Cases("mpcorenovfp", "mpcore", "6K") 4303 .Cases("arm1176jz-s", "arm1176jzf-s", "6K") 4304 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 4305 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A") 4306 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait", 4307 "7A") 4308 .Cases("cortex-r4", "cortex-r4f", "cortex-r5", "cortex-r7", "7R") 4309 .Case("swift", "7S") 4310 .Case("cyclone", "8A") 4311 .Cases("sc300", "cortex-m3", "7M") 4312 .Cases("cortex-m4", "cortex-m7", "7EM") 4313 .Cases("sc000", "cortex-m0", "cortex-m0plus", "cortex-m1", "6M") 4314 .Cases("cortex-a53", "cortex-a57", "cortex-a72", "8A") 4315 .Default(nullptr); 4316 } 4317 static const char *getCPUProfile(StringRef Name) { 4318 return llvm::StringSwitch<const char *>(Name) 4319 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A") 4320 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait", 4321 "A") 4322 .Cases("cortex-a53", "cortex-a57", "cortex-a72", "A") 4323 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m0plus", "M") 4324 .Cases("cortex-m1", "cortex-m7", "sc000", "sc300", "M") 4325 .Cases("cortex-r4", "cortex-r4f", "cortex-r5", "cortex-r7", "R") 4326 .Default(""); 4327 } 4328 bool setCPU(const std::string &Name) override { 4329 if (!getCPUDefineSuffix(Name)) 4330 return false; 4331 4332 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4333 StringRef Profile = getCPUProfile(Name); 4334 if (Profile == "M" && MaxAtomicInlineWidth) { 4335 MaxAtomicPromoteWidth = 32; 4336 MaxAtomicInlineWidth = 32; 4337 } 4338 4339 CPU = Name; 4340 return true; 4341 } 4342 bool setFPMath(StringRef Name) override; 4343 bool supportsThumb(StringRef ArchName, StringRef CPUArch, 4344 unsigned CPUArchVer) const { 4345 return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) || 4346 (CPUArch.find('M') != StringRef::npos); 4347 } 4348 bool supportsThumb2(StringRef ArchName, StringRef CPUArch, 4349 unsigned CPUArchVer) const { 4350 // We check both CPUArchVer and ArchName because when only triple is 4351 // specified, the default CPU is arm1136j-s. 4352 return ArchName.endswith("v6t2") || ArchName.endswith("v7") || 4353 ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7; 4354 } 4355 void getTargetDefines(const LangOptions &Opts, 4356 MacroBuilder &Builder) const override { 4357 // Target identification. 4358 Builder.defineMacro("__arm"); 4359 Builder.defineMacro("__arm__"); 4360 4361 // Target properties. 4362 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4363 4364 StringRef CPUArch = getCPUDefineSuffix(CPU); 4365 unsigned int CPUArchVer; 4366 if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) 4367 llvm_unreachable("Invalid char for architecture version number"); 4368 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 4369 4370 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4371 StringRef CPUProfile = getCPUProfile(CPU); 4372 StringRef ArchName = getTriple().getArchName(); 4373 4374 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4375 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 4376 if (CPUArch[0] >= '8') { 4377 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4378 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4379 } 4380 4381 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4382 // is not defined for the M-profile. 4383 // NOTE that the deffault profile is assumed to be 'A' 4384 if (CPUProfile.empty() || CPUProfile != "M") 4385 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4386 4387 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4388 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4389 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4390 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4391 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4392 else if (supportsThumb(ArchName, CPUArch, CPUArchVer)) 4393 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4394 4395 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4396 // instruction set such as ARM or Thumb. 4397 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4398 4399 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4400 4401 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4402 if (!CPUProfile.empty()) 4403 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4404 4405 // ACLE 6.5.1 Hardware Floating Point 4406 if (HW_FP) 4407 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4408 4409 // ACLE predefines. 4410 Builder.defineMacro("__ARM_ACLE", "200"); 4411 4412 // Subtarget options. 4413 4414 // FIXME: It's more complicated than this and we don't really support 4415 // interworking. 4416 // Windows on ARM does not "support" interworking 4417 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows()) 4418 Builder.defineMacro("__THUMB_INTERWORK__"); 4419 4420 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4421 // Embedded targets on Darwin follow AAPCS, but not EABI. 4422 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4423 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4424 Builder.defineMacro("__ARM_EABI__"); 4425 Builder.defineMacro("__ARM_PCS", "1"); 4426 4427 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4428 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4429 } 4430 4431 if (SoftFloat) 4432 Builder.defineMacro("__SOFTFP__"); 4433 4434 if (CPU == "xscale") 4435 Builder.defineMacro("__XSCALE__"); 4436 4437 if (IsThumb) { 4438 Builder.defineMacro("__THUMBEL__"); 4439 Builder.defineMacro("__thumb__"); 4440 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4441 Builder.defineMacro("__thumb2__"); 4442 } 4443 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 4444 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4445 4446 // Note, this is always on in gcc, even though it doesn't make sense. 4447 Builder.defineMacro("__APCS_32__"); 4448 4449 if (FPUModeIsVFP((FPUMode) FPU)) { 4450 Builder.defineMacro("__VFP_FP__"); 4451 if (FPU & VFP2FPU) 4452 Builder.defineMacro("__ARM_VFPV2__"); 4453 if (FPU & VFP3FPU) 4454 Builder.defineMacro("__ARM_VFPV3__"); 4455 if (FPU & VFP4FPU) 4456 Builder.defineMacro("__ARM_VFPV4__"); 4457 } 4458 4459 // This only gets set when Neon instructions are actually available, unlike 4460 // the VFP define, hence the soft float and arch check. This is subtly 4461 // different from gcc, we follow the intent which was that it should be set 4462 // when Neon instructions are actually available. 4463 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) { 4464 Builder.defineMacro("__ARM_NEON"); 4465 Builder.defineMacro("__ARM_NEON__"); 4466 } 4467 4468 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4469 Opts.ShortWChar ? "2" : "4"); 4470 4471 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4472 Opts.ShortEnums ? "1" : "4"); 4473 4474 if (CRC) 4475 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4476 4477 if (Crypto) 4478 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4479 4480 if (CPUArchVer >= 6 && CPUArch != "6M") { 4481 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4482 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4483 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4484 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4485 } 4486 4487 bool is5EOrAbove = (CPUArchVer >= 6 || 4488 (CPUArchVer == 5 && 4489 CPUArch.find('E') != StringRef::npos)); 4490 bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer)); 4491 if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch == "7EM")) 4492 Builder.defineMacro("__ARM_FEATURE_DSP"); 4493 } 4494 void getTargetBuiltins(const Builtin::Info *&Records, 4495 unsigned &NumRecords) const override { 4496 Records = BuiltinInfo; 4497 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4498 } 4499 bool isCLZForZeroUndef() const override { return false; } 4500 BuiltinVaListKind getBuiltinVaListKind() const override { 4501 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4502 } 4503 void getGCCRegNames(const char * const *&Names, 4504 unsigned &NumNames) const override; 4505 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4506 unsigned &NumAliases) const override; 4507 bool validateAsmConstraint(const char *&Name, 4508 TargetInfo::ConstraintInfo &Info) const override { 4509 switch (*Name) { 4510 default: break; 4511 case 'l': // r0-r7 4512 case 'h': // r8-r15 4513 case 'w': // VFP Floating point register single precision 4514 case 'P': // VFP Floating point register double precision 4515 Info.setAllowsRegister(); 4516 return true; 4517 case 'I': 4518 case 'J': 4519 case 'K': 4520 case 'L': 4521 case 'M': 4522 // FIXME 4523 return true; 4524 case 'Q': // A memory address that is a single base register. 4525 Info.setAllowsMemory(); 4526 return true; 4527 case 'U': // a memory reference... 4528 switch (Name[1]) { 4529 case 'q': // ...ARMV4 ldrsb 4530 case 'v': // ...VFP load/store (reg+constant offset) 4531 case 'y': // ...iWMMXt load/store 4532 case 't': // address valid for load/store opaque types wider 4533 // than 128-bits 4534 case 'n': // valid address for Neon doubleword vector load/store 4535 case 'm': // valid address for Neon element and structure load/store 4536 case 's': // valid address for non-offset loads/stores of quad-word 4537 // values in four ARM registers 4538 Info.setAllowsMemory(); 4539 Name++; 4540 return true; 4541 } 4542 } 4543 return false; 4544 } 4545 std::string convertConstraint(const char *&Constraint) const override { 4546 std::string R; 4547 switch (*Constraint) { 4548 case 'U': // Two-character constraint; add "^" hint for later parsing. 4549 R = std::string("^") + std::string(Constraint, 2); 4550 Constraint++; 4551 break; 4552 case 'p': // 'p' should be translated to 'r' by default. 4553 R = std::string("r"); 4554 break; 4555 default: 4556 return std::string(1, *Constraint); 4557 } 4558 return R; 4559 } 4560 bool 4561 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4562 std::string &SuggestedModifier) const override { 4563 bool isOutput = (Constraint[0] == '='); 4564 bool isInOut = (Constraint[0] == '+'); 4565 4566 // Strip off constraint modifiers. 4567 while (Constraint[0] == '=' || 4568 Constraint[0] == '+' || 4569 Constraint[0] == '&') 4570 Constraint = Constraint.substr(1); 4571 4572 switch (Constraint[0]) { 4573 default: break; 4574 case 'r': { 4575 switch (Modifier) { 4576 default: 4577 return (isInOut || isOutput || Size <= 64); 4578 case 'q': 4579 // A register of size 32 cannot fit a vector type. 4580 return false; 4581 } 4582 } 4583 } 4584 4585 return true; 4586 } 4587 const char *getClobbers() const override { 4588 // FIXME: Is this really right? 4589 return ""; 4590 } 4591 4592 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4593 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4594 } 4595 4596 int getEHDataRegisterNumber(unsigned RegNo) const override { 4597 if (RegNo == 0) return 0; 4598 if (RegNo == 1) return 1; 4599 return -1; 4600 } 4601 }; 4602 4603 bool ARMTargetInfo::setFPMath(StringRef Name) { 4604 if (Name == "neon") { 4605 FPMath = FP_Neon; 4606 return true; 4607 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4608 Name == "vfp4") { 4609 FPMath = FP_VFP; 4610 return true; 4611 } 4612 return false; 4613 } 4614 4615 const char * const ARMTargetInfo::GCCRegNames[] = { 4616 // Integer registers 4617 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4618 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4619 4620 // Float registers 4621 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4622 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4623 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4624 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4625 4626 // Double registers 4627 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4628 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4629 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4630 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4631 4632 // Quad registers 4633 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4634 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4635 }; 4636 4637 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4638 unsigned &NumNames) const { 4639 Names = GCCRegNames; 4640 NumNames = llvm::array_lengthof(GCCRegNames); 4641 } 4642 4643 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4644 { { "a1" }, "r0" }, 4645 { { "a2" }, "r1" }, 4646 { { "a3" }, "r2" }, 4647 { { "a4" }, "r3" }, 4648 { { "v1" }, "r4" }, 4649 { { "v2" }, "r5" }, 4650 { { "v3" }, "r6" }, 4651 { { "v4" }, "r7" }, 4652 { { "v5" }, "r8" }, 4653 { { "v6", "rfp" }, "r9" }, 4654 { { "sl" }, "r10" }, 4655 { { "fp" }, "r11" }, 4656 { { "ip" }, "r12" }, 4657 { { "r13" }, "sp" }, 4658 { { "r14" }, "lr" }, 4659 { { "r15" }, "pc" }, 4660 // The S, D and Q registers overlap, but aren't really aliases; we 4661 // don't want to substitute one of these for a different-sized one. 4662 }; 4663 4664 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4665 unsigned &NumAliases) const { 4666 Aliases = GCCRegAliases; 4667 NumAliases = llvm::array_lengthof(GCCRegAliases); 4668 } 4669 4670 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4671 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4672 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4673 ALL_LANGUAGES }, 4674 #include "clang/Basic/BuiltinsNEON.def" 4675 4676 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4677 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG }, 4678 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4679 ALL_LANGUAGES }, 4680 #include "clang/Basic/BuiltinsARM.def" 4681 }; 4682 4683 class ARMleTargetInfo : public ARMTargetInfo { 4684 public: 4685 ARMleTargetInfo(const llvm::Triple &Triple) 4686 : ARMTargetInfo(Triple, false) { } 4687 void getTargetDefines(const LangOptions &Opts, 4688 MacroBuilder &Builder) const override { 4689 Builder.defineMacro("__ARMEL__"); 4690 ARMTargetInfo::getTargetDefines(Opts, Builder); 4691 } 4692 }; 4693 4694 class ARMbeTargetInfo : public ARMTargetInfo { 4695 public: 4696 ARMbeTargetInfo(const llvm::Triple &Triple) 4697 : ARMTargetInfo(Triple, true) { } 4698 void getTargetDefines(const LangOptions &Opts, 4699 MacroBuilder &Builder) const override { 4700 Builder.defineMacro("__ARMEB__"); 4701 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4702 ARMTargetInfo::getTargetDefines(Opts, Builder); 4703 } 4704 }; 4705 4706 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 4707 const llvm::Triple Triple; 4708 public: 4709 WindowsARMTargetInfo(const llvm::Triple &Triple) 4710 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 4711 TLSSupported = false; 4712 WCharType = UnsignedShort; 4713 SizeType = UnsignedInt; 4714 UserLabelPrefix = ""; 4715 } 4716 void getVisualStudioDefines(const LangOptions &Opts, 4717 MacroBuilder &Builder) const { 4718 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 4719 4720 // FIXME: this is invalid for WindowsCE 4721 Builder.defineMacro("_M_ARM_NT", "1"); 4722 Builder.defineMacro("_M_ARMT", "_M_ARM"); 4723 Builder.defineMacro("_M_THUMB", "_M_ARM"); 4724 4725 assert((Triple.getArch() == llvm::Triple::arm || 4726 Triple.getArch() == llvm::Triple::thumb) && 4727 "invalid architecture for Windows ARM target info"); 4728 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 4729 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 4730 4731 // TODO map the complete set of values 4732 // 31: VFPv3 40: VFPv4 4733 Builder.defineMacro("_M_ARM_FP", "31"); 4734 } 4735 BuiltinVaListKind getBuiltinVaListKind() const override { 4736 return TargetInfo::CharPtrBuiltinVaList; 4737 } 4738 }; 4739 4740 // Windows ARM + Itanium C++ ABI Target 4741 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 4742 public: 4743 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 4744 : WindowsARMTargetInfo(Triple) { 4745 TheCXXABI.set(TargetCXXABI::GenericARM); 4746 } 4747 4748 void getTargetDefines(const LangOptions &Opts, 4749 MacroBuilder &Builder) const override { 4750 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4751 4752 if (Opts.MSVCCompat) 4753 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4754 } 4755 }; 4756 4757 // Windows ARM, MS (C++) ABI 4758 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 4759 public: 4760 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 4761 : WindowsARMTargetInfo(Triple) { 4762 TheCXXABI.set(TargetCXXABI::Microsoft); 4763 } 4764 4765 void getTargetDefines(const LangOptions &Opts, 4766 MacroBuilder &Builder) const override { 4767 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4768 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4769 } 4770 }; 4771 4772 class DarwinARMTargetInfo : 4773 public DarwinTargetInfo<ARMleTargetInfo> { 4774 protected: 4775 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4776 MacroBuilder &Builder) const override { 4777 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4778 } 4779 4780 public: 4781 DarwinARMTargetInfo(const llvm::Triple &Triple) 4782 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 4783 HasAlignMac68kSupport = true; 4784 // iOS always has 64-bit atomic instructions. 4785 // FIXME: This should be based off of the target features in 4786 // ARMleTargetInfo. 4787 MaxAtomicInlineWidth = 64; 4788 4789 // Darwin on iOS uses a variant of the ARM C++ ABI. 4790 TheCXXABI.set(TargetCXXABI::iOS); 4791 } 4792 }; 4793 4794 class AArch64TargetInfo : public TargetInfo { 4795 virtual void setDescriptionString() = 0; 4796 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4797 static const char *const GCCRegNames[]; 4798 4799 enum FPUModeEnum { 4800 FPUMode, 4801 NeonMode 4802 }; 4803 4804 unsigned FPU; 4805 unsigned CRC; 4806 unsigned Crypto; 4807 4808 static const Builtin::Info BuiltinInfo[]; 4809 4810 std::string ABI; 4811 4812 public: 4813 AArch64TargetInfo(const llvm::Triple &Triple) 4814 : TargetInfo(Triple), ABI("aapcs") { 4815 4816 if (getTriple().getOS() == llvm::Triple::NetBSD) { 4817 WCharType = SignedInt; 4818 4819 // NetBSD apparently prefers consistency across ARM targets to consistency 4820 // across 64-bit targets. 4821 Int64Type = SignedLongLong; 4822 IntMaxType = SignedLongLong; 4823 } else { 4824 WCharType = UnsignedInt; 4825 Int64Type = SignedLong; 4826 IntMaxType = SignedLong; 4827 } 4828 4829 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4830 MaxVectorAlign = 128; 4831 RegParmMax = 8; 4832 MaxAtomicInlineWidth = 128; 4833 MaxAtomicPromoteWidth = 128; 4834 4835 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 4836 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4837 4838 // {} in inline assembly are neon specifiers, not assembly variant 4839 // specifiers. 4840 NoAsmVariants = true; 4841 4842 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 4843 // contributes to the alignment of the containing aggregate in the same way 4844 // a plain (non bit-field) member of that type would, without exception for 4845 // zero-sized or anonymous bit-fields." 4846 UseBitFieldTypeAlignment = true; 4847 UseZeroLengthBitfieldAlignment = true; 4848 4849 // AArch64 targets default to using the ARM C++ ABI. 4850 TheCXXABI.set(TargetCXXABI::GenericAArch64); 4851 } 4852 4853 StringRef getABI() const override { return ABI; } 4854 bool setABI(const std::string &Name) override { 4855 if (Name != "aapcs" && Name != "darwinpcs") 4856 return false; 4857 4858 ABI = Name; 4859 return true; 4860 } 4861 4862 bool setCPU(const std::string &Name) override { 4863 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4864 .Case("generic", true) 4865 .Cases("cortex-a53", "cortex-a57", "cortex-a72", true) 4866 .Case("cyclone", true) 4867 .Default(false); 4868 return CPUKnown; 4869 } 4870 4871 void getTargetDefines(const LangOptions &Opts, 4872 MacroBuilder &Builder) const override { 4873 // Target identification. 4874 Builder.defineMacro("__aarch64__"); 4875 4876 // Target properties. 4877 Builder.defineMacro("_LP64"); 4878 Builder.defineMacro("__LP64__"); 4879 4880 // ACLE predefines. Many can only have one possible value on v8 AArch64. 4881 Builder.defineMacro("__ARM_ACLE", "200"); 4882 Builder.defineMacro("__ARM_ARCH", "8"); 4883 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 4884 4885 Builder.defineMacro("__ARM_64BIT_STATE"); 4886 Builder.defineMacro("__ARM_PCS_AAPCS64"); 4887 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 4888 4889 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 4890 Builder.defineMacro("__ARM_FEATURE_CLZ"); 4891 Builder.defineMacro("__ARM_FEATURE_FMA"); 4892 Builder.defineMacro("__ARM_FEATURE_DIV"); 4893 Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE 4894 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 4895 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4896 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4897 4898 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 4899 4900 // 0xe implies support for half, single and double precision operations. 4901 Builder.defineMacro("__ARM_FP", "0xe"); 4902 4903 // PCS specifies this for SysV variants, which is all we support. Other ABIs 4904 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 4905 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 4906 4907 if (Opts.FastMath || Opts.FiniteMathOnly) 4908 Builder.defineMacro("__ARM_FP_FAST"); 4909 4910 if (Opts.C99 && !Opts.Freestanding) 4911 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 4912 4913 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 4914 4915 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4916 Opts.ShortEnums ? "1" : "4"); 4917 4918 if (FPU == NeonMode) { 4919 Builder.defineMacro("__ARM_NEON"); 4920 // 64-bit NEON supports half, single and double precision operations. 4921 Builder.defineMacro("__ARM_NEON_FP", "0xe"); 4922 } 4923 4924 if (CRC) 4925 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4926 4927 if (Crypto) 4928 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4929 4930 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 4931 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4932 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4933 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4934 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4935 } 4936 4937 void getTargetBuiltins(const Builtin::Info *&Records, 4938 unsigned &NumRecords) const override { 4939 Records = BuiltinInfo; 4940 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin; 4941 } 4942 4943 bool hasFeature(StringRef Feature) const override { 4944 return Feature == "aarch64" || 4945 Feature == "arm64" || 4946 (Feature == "neon" && FPU == NeonMode); 4947 } 4948 4949 bool handleTargetFeatures(std::vector<std::string> &Features, 4950 DiagnosticsEngine &Diags) override { 4951 FPU = FPUMode; 4952 CRC = 0; 4953 Crypto = 0; 4954 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 4955 if (Features[i] == "+neon") 4956 FPU = NeonMode; 4957 if (Features[i] == "+crc") 4958 CRC = 1; 4959 if (Features[i] == "+crypto") 4960 Crypto = 1; 4961 } 4962 4963 setDescriptionString(); 4964 4965 return true; 4966 } 4967 4968 bool isCLZForZeroUndef() const override { return false; } 4969 4970 BuiltinVaListKind getBuiltinVaListKind() const override { 4971 return TargetInfo::AArch64ABIBuiltinVaList; 4972 } 4973 4974 void getGCCRegNames(const char *const *&Names, 4975 unsigned &NumNames) const override; 4976 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4977 unsigned &NumAliases) const override; 4978 4979 bool validateAsmConstraint(const char *&Name, 4980 TargetInfo::ConstraintInfo &Info) const override { 4981 switch (*Name) { 4982 default: 4983 return false; 4984 case 'w': // Floating point and SIMD registers (V0-V31) 4985 Info.setAllowsRegister(); 4986 return true; 4987 case 'I': // Constant that can be used with an ADD instruction 4988 case 'J': // Constant that can be used with a SUB instruction 4989 case 'K': // Constant that can be used with a 32-bit logical instruction 4990 case 'L': // Constant that can be used with a 64-bit logical instruction 4991 case 'M': // Constant that can be used as a 32-bit MOV immediate 4992 case 'N': // Constant that can be used as a 64-bit MOV immediate 4993 case 'Y': // Floating point constant zero 4994 case 'Z': // Integer constant zero 4995 return true; 4996 case 'Q': // A memory reference with base register and no offset 4997 Info.setAllowsMemory(); 4998 return true; 4999 case 'S': // A symbolic address 5000 Info.setAllowsRegister(); 5001 return true; 5002 case 'U': 5003 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5004 // Utf: A memory address suitable for ldp/stp in TF mode. 5005 // Usa: An absolute symbolic address. 5006 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5007 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5008 case 'z': // Zero register, wzr or xzr 5009 Info.setAllowsRegister(); 5010 return true; 5011 case 'x': // Floating point and SIMD registers (V0-V15) 5012 Info.setAllowsRegister(); 5013 return true; 5014 } 5015 return false; 5016 } 5017 5018 bool 5019 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5020 std::string &SuggestedModifier) const override { 5021 // Strip off constraint modifiers. 5022 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5023 Constraint = Constraint.substr(1); 5024 5025 switch (Constraint[0]) { 5026 default: 5027 return true; 5028 case 'z': 5029 case 'r': { 5030 switch (Modifier) { 5031 case 'x': 5032 case 'w': 5033 // For now assume that the person knows what they're 5034 // doing with the modifier. 5035 return true; 5036 default: 5037 // By default an 'r' constraint will be in the 'x' 5038 // registers. 5039 if (Size == 64) 5040 return true; 5041 5042 SuggestedModifier = "w"; 5043 return false; 5044 } 5045 } 5046 } 5047 } 5048 5049 const char *getClobbers() const override { return ""; } 5050 5051 int getEHDataRegisterNumber(unsigned RegNo) const override { 5052 if (RegNo == 0) 5053 return 0; 5054 if (RegNo == 1) 5055 return 1; 5056 return -1; 5057 } 5058 }; 5059 5060 const char *const AArch64TargetInfo::GCCRegNames[] = { 5061 // 32-bit Integer registers 5062 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5063 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5064 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5065 5066 // 64-bit Integer registers 5067 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5068 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5069 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5070 5071 // 32-bit floating point regsisters 5072 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5073 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5074 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5075 5076 // 64-bit floating point regsisters 5077 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5078 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5079 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5080 5081 // Vector registers 5082 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5083 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5084 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5085 }; 5086 5087 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names, 5088 unsigned &NumNames) const { 5089 Names = GCCRegNames; 5090 NumNames = llvm::array_lengthof(GCCRegNames); 5091 } 5092 5093 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5094 { { "w31" }, "wsp" }, 5095 { { "x29" }, "fp" }, 5096 { { "x30" }, "lr" }, 5097 { { "x31" }, "sp" }, 5098 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5099 // don't want to substitute one of these for a different-sized one. 5100 }; 5101 5102 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5103 unsigned &NumAliases) const { 5104 Aliases = GCCRegAliases; 5105 NumAliases = llvm::array_lengthof(GCCRegAliases); 5106 } 5107 5108 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5109 #define BUILTIN(ID, TYPE, ATTRS) \ 5110 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5111 #include "clang/Basic/BuiltinsNEON.def" 5112 5113 #define BUILTIN(ID, TYPE, ATTRS) \ 5114 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5115 #include "clang/Basic/BuiltinsAArch64.def" 5116 }; 5117 5118 class AArch64leTargetInfo : public AArch64TargetInfo { 5119 void setDescriptionString() override { 5120 if (getTriple().isOSBinFormatMachO()) 5121 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128"; 5122 else 5123 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 5124 } 5125 5126 public: 5127 AArch64leTargetInfo(const llvm::Triple &Triple) 5128 : AArch64TargetInfo(Triple) { 5129 BigEndian = false; 5130 } 5131 void getTargetDefines(const LangOptions &Opts, 5132 MacroBuilder &Builder) const override { 5133 Builder.defineMacro("__AARCH64EL__"); 5134 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5135 } 5136 }; 5137 5138 class AArch64beTargetInfo : public AArch64TargetInfo { 5139 void setDescriptionString() override { 5140 assert(!getTriple().isOSBinFormatMachO()); 5141 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5142 } 5143 5144 public: 5145 AArch64beTargetInfo(const llvm::Triple &Triple) 5146 : AArch64TargetInfo(Triple) { } 5147 void getTargetDefines(const LangOptions &Opts, 5148 MacroBuilder &Builder) const override { 5149 Builder.defineMacro("__AARCH64EB__"); 5150 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5151 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5152 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5153 } 5154 }; 5155 5156 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5157 protected: 5158 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5159 MacroBuilder &Builder) const override { 5160 Builder.defineMacro("__AARCH64_SIMD__"); 5161 Builder.defineMacro("__ARM64_ARCH_8__"); 5162 Builder.defineMacro("__ARM_NEON__"); 5163 Builder.defineMacro("__LITTLE_ENDIAN__"); 5164 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5165 Builder.defineMacro("__arm64", "1"); 5166 Builder.defineMacro("__arm64__", "1"); 5167 5168 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5169 } 5170 5171 public: 5172 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5173 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5174 Int64Type = SignedLongLong; 5175 WCharType = SignedInt; 5176 UseSignedCharForObjCBool = false; 5177 5178 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5179 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5180 5181 TheCXXABI.set(TargetCXXABI::iOS64); 5182 } 5183 5184 BuiltinVaListKind getBuiltinVaListKind() const override { 5185 return TargetInfo::CharPtrBuiltinVaList; 5186 } 5187 }; 5188 5189 // Hexagon abstract base class 5190 class HexagonTargetInfo : public TargetInfo { 5191 static const Builtin::Info BuiltinInfo[]; 5192 static const char * const GCCRegNames[]; 5193 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5194 std::string CPU; 5195 public: 5196 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5197 BigEndian = false; 5198 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 5199 5200 // {} in inline assembly are packet specifiers, not assembly variant 5201 // specifiers. 5202 NoAsmVariants = true; 5203 } 5204 5205 void getTargetBuiltins(const Builtin::Info *&Records, 5206 unsigned &NumRecords) const override { 5207 Records = BuiltinInfo; 5208 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 5209 } 5210 5211 bool validateAsmConstraint(const char *&Name, 5212 TargetInfo::ConstraintInfo &Info) const override { 5213 return true; 5214 } 5215 5216 void getTargetDefines(const LangOptions &Opts, 5217 MacroBuilder &Builder) const override; 5218 5219 bool hasFeature(StringRef Feature) const override { 5220 return Feature == "hexagon"; 5221 } 5222 5223 BuiltinVaListKind getBuiltinVaListKind() const override { 5224 return TargetInfo::CharPtrBuiltinVaList; 5225 } 5226 void getGCCRegNames(const char * const *&Names, 5227 unsigned &NumNames) const override; 5228 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5229 unsigned &NumAliases) const override; 5230 const char *getClobbers() const override { 5231 return ""; 5232 } 5233 5234 static const char *getHexagonCPUSuffix(StringRef Name) { 5235 return llvm::StringSwitch<const char*>(Name) 5236 .Case("hexagonv4", "4") 5237 .Case("hexagonv5", "5") 5238 .Default(nullptr); 5239 } 5240 5241 bool setCPU(const std::string &Name) override { 5242 if (!getHexagonCPUSuffix(Name)) 5243 return false; 5244 5245 CPU = Name; 5246 return true; 5247 } 5248 }; 5249 5250 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5251 MacroBuilder &Builder) const { 5252 Builder.defineMacro("qdsp6"); 5253 Builder.defineMacro("__qdsp6", "1"); 5254 Builder.defineMacro("__qdsp6__", "1"); 5255 5256 Builder.defineMacro("hexagon"); 5257 Builder.defineMacro("__hexagon", "1"); 5258 Builder.defineMacro("__hexagon__", "1"); 5259 5260 if(CPU == "hexagonv1") { 5261 Builder.defineMacro("__HEXAGON_V1__"); 5262 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 5263 if(Opts.HexagonQdsp6Compat) { 5264 Builder.defineMacro("__QDSP6_V1__"); 5265 Builder.defineMacro("__QDSP6_ARCH__", "1"); 5266 } 5267 } 5268 else if(CPU == "hexagonv2") { 5269 Builder.defineMacro("__HEXAGON_V2__"); 5270 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 5271 if(Opts.HexagonQdsp6Compat) { 5272 Builder.defineMacro("__QDSP6_V2__"); 5273 Builder.defineMacro("__QDSP6_ARCH__", "2"); 5274 } 5275 } 5276 else if(CPU == "hexagonv3") { 5277 Builder.defineMacro("__HEXAGON_V3__"); 5278 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 5279 if(Opts.HexagonQdsp6Compat) { 5280 Builder.defineMacro("__QDSP6_V3__"); 5281 Builder.defineMacro("__QDSP6_ARCH__", "3"); 5282 } 5283 } 5284 else if(CPU == "hexagonv4") { 5285 Builder.defineMacro("__HEXAGON_V4__"); 5286 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5287 if(Opts.HexagonQdsp6Compat) { 5288 Builder.defineMacro("__QDSP6_V4__"); 5289 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5290 } 5291 } 5292 else if(CPU == "hexagonv5") { 5293 Builder.defineMacro("__HEXAGON_V5__"); 5294 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5295 if(Opts.HexagonQdsp6Compat) { 5296 Builder.defineMacro("__QDSP6_V5__"); 5297 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5298 } 5299 } 5300 } 5301 5302 const char * const HexagonTargetInfo::GCCRegNames[] = { 5303 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5304 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5305 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5306 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5307 "p0", "p1", "p2", "p3", 5308 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5309 }; 5310 5311 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 5312 unsigned &NumNames) const { 5313 Names = GCCRegNames; 5314 NumNames = llvm::array_lengthof(GCCRegNames); 5315 } 5316 5317 5318 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5319 { { "sp" }, "r29" }, 5320 { { "fp" }, "r30" }, 5321 { { "lr" }, "r31" }, 5322 }; 5323 5324 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5325 unsigned &NumAliases) const { 5326 Aliases = GCCRegAliases; 5327 NumAliases = llvm::array_lengthof(GCCRegAliases); 5328 } 5329 5330 5331 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5332 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5333 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5334 ALL_LANGUAGES }, 5335 #include "clang/Basic/BuiltinsHexagon.def" 5336 }; 5337 5338 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5339 class SparcTargetInfo : public TargetInfo { 5340 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5341 static const char * const GCCRegNames[]; 5342 bool SoftFloat; 5343 public: 5344 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {} 5345 5346 bool handleTargetFeatures(std::vector<std::string> &Features, 5347 DiagnosticsEngine &Diags) override { 5348 SoftFloat = false; 5349 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 5350 if (Feature != Features.end()) { 5351 SoftFloat = true; 5352 Features.erase(Feature); 5353 } 5354 return true; 5355 } 5356 void getTargetDefines(const LangOptions &Opts, 5357 MacroBuilder &Builder) const override { 5358 DefineStd(Builder, "sparc", Opts); 5359 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5360 5361 if (SoftFloat) 5362 Builder.defineMacro("SOFT_FLOAT", "1"); 5363 } 5364 5365 bool hasFeature(StringRef Feature) const override { 5366 return llvm::StringSwitch<bool>(Feature) 5367 .Case("softfloat", SoftFloat) 5368 .Case("sparc", true) 5369 .Default(false); 5370 } 5371 5372 void getTargetBuiltins(const Builtin::Info *&Records, 5373 unsigned &NumRecords) const override { 5374 // FIXME: Implement! 5375 } 5376 BuiltinVaListKind getBuiltinVaListKind() const override { 5377 return TargetInfo::VoidPtrBuiltinVaList; 5378 } 5379 void getGCCRegNames(const char * const *&Names, 5380 unsigned &NumNames) const override; 5381 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5382 unsigned &NumAliases) const override; 5383 bool validateAsmConstraint(const char *&Name, 5384 TargetInfo::ConstraintInfo &info) const override { 5385 // FIXME: Implement! 5386 switch (*Name) { 5387 case 'I': // Signed 13-bit constant 5388 case 'J': // Zero 5389 case 'K': // 32-bit constant with the low 12 bits clear 5390 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5391 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5392 case 'N': // Same as 'K' but zext (required for SIMode) 5393 case 'O': // The constant 4096 5394 return true; 5395 } 5396 return false; 5397 } 5398 const char *getClobbers() const override { 5399 // FIXME: Implement! 5400 return ""; 5401 } 5402 }; 5403 5404 const char * const SparcTargetInfo::GCCRegNames[] = { 5405 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5406 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5407 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5408 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5409 }; 5410 5411 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 5412 unsigned &NumNames) const { 5413 Names = GCCRegNames; 5414 NumNames = llvm::array_lengthof(GCCRegNames); 5415 } 5416 5417 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5418 { { "g0" }, "r0" }, 5419 { { "g1" }, "r1" }, 5420 { { "g2" }, "r2" }, 5421 { { "g3" }, "r3" }, 5422 { { "g4" }, "r4" }, 5423 { { "g5" }, "r5" }, 5424 { { "g6" }, "r6" }, 5425 { { "g7" }, "r7" }, 5426 { { "o0" }, "r8" }, 5427 { { "o1" }, "r9" }, 5428 { { "o2" }, "r10" }, 5429 { { "o3" }, "r11" }, 5430 { { "o4" }, "r12" }, 5431 { { "o5" }, "r13" }, 5432 { { "o6", "sp" }, "r14" }, 5433 { { "o7" }, "r15" }, 5434 { { "l0" }, "r16" }, 5435 { { "l1" }, "r17" }, 5436 { { "l2" }, "r18" }, 5437 { { "l3" }, "r19" }, 5438 { { "l4" }, "r20" }, 5439 { { "l5" }, "r21" }, 5440 { { "l6" }, "r22" }, 5441 { { "l7" }, "r23" }, 5442 { { "i0" }, "r24" }, 5443 { { "i1" }, "r25" }, 5444 { { "i2" }, "r26" }, 5445 { { "i3" }, "r27" }, 5446 { { "i4" }, "r28" }, 5447 { { "i5" }, "r29" }, 5448 { { "i6", "fp" }, "r30" }, 5449 { { "i7" }, "r31" }, 5450 }; 5451 5452 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5453 unsigned &NumAliases) const { 5454 Aliases = GCCRegAliases; 5455 NumAliases = llvm::array_lengthof(GCCRegAliases); 5456 } 5457 5458 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5459 class SparcV8TargetInfo : public SparcTargetInfo { 5460 public: 5461 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5462 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5463 } 5464 5465 void getTargetDefines(const LangOptions &Opts, 5466 MacroBuilder &Builder) const override { 5467 SparcTargetInfo::getTargetDefines(Opts, Builder); 5468 Builder.defineMacro("__sparcv8"); 5469 } 5470 }; 5471 5472 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 5473 class SparcV9TargetInfo : public SparcTargetInfo { 5474 public: 5475 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5476 // FIXME: Support Sparc quad-precision long double? 5477 DescriptionString = "E-m:e-i64:64-n32:64-S128"; 5478 // This is an LP64 platform. 5479 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5480 5481 // OpenBSD uses long long for int64_t and intmax_t. 5482 if (getTriple().getOS() == llvm::Triple::OpenBSD) 5483 IntMaxType = SignedLongLong; 5484 else 5485 IntMaxType = SignedLong; 5486 Int64Type = IntMaxType; 5487 5488 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 5489 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 5490 LongDoubleWidth = 128; 5491 LongDoubleAlign = 128; 5492 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5493 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5494 } 5495 5496 void getTargetDefines(const LangOptions &Opts, 5497 MacroBuilder &Builder) const override { 5498 SparcTargetInfo::getTargetDefines(Opts, Builder); 5499 Builder.defineMacro("__sparcv9"); 5500 Builder.defineMacro("__arch64__"); 5501 // Solaris doesn't need these variants, but the BSDs do. 5502 if (getTriple().getOS() != llvm::Triple::Solaris) { 5503 Builder.defineMacro("__sparc64__"); 5504 Builder.defineMacro("__sparc_v9__"); 5505 Builder.defineMacro("__sparcv9__"); 5506 } 5507 } 5508 5509 bool setCPU(const std::string &Name) override { 5510 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5511 .Case("v9", true) 5512 .Case("ultrasparc", true) 5513 .Case("ultrasparc3", true) 5514 .Case("niagara", true) 5515 .Case("niagara2", true) 5516 .Case("niagara3", true) 5517 .Case("niagara4", true) 5518 .Default(false); 5519 5520 // No need to store the CPU yet. There aren't any CPU-specific 5521 // macros to define. 5522 return CPUKnown; 5523 } 5524 }; 5525 5526 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 5527 public: 5528 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 5529 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 5530 SizeType = UnsignedInt; 5531 PtrDiffType = SignedInt; 5532 } 5533 }; 5534 5535 class SystemZTargetInfo : public TargetInfo { 5536 static const Builtin::Info BuiltinInfo[]; 5537 static const char *const GCCRegNames[]; 5538 std::string CPU; 5539 bool HasTransactionalExecution; 5540 bool HasVector; 5541 5542 public: 5543 SystemZTargetInfo(const llvm::Triple &Triple) 5544 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), HasVector(false) { 5545 IntMaxType = SignedLong; 5546 Int64Type = SignedLong; 5547 TLSSupported = true; 5548 IntWidth = IntAlign = 32; 5549 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5550 PointerWidth = PointerAlign = 64; 5551 LongDoubleWidth = 128; 5552 LongDoubleAlign = 64; 5553 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5554 DefaultAlignForAttributeAligned = 64; 5555 MinGlobalAlign = 16; 5556 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5557 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5558 } 5559 void getTargetDefines(const LangOptions &Opts, 5560 MacroBuilder &Builder) const override { 5561 Builder.defineMacro("__s390__"); 5562 Builder.defineMacro("__s390x__"); 5563 Builder.defineMacro("__zarch__"); 5564 Builder.defineMacro("__LONG_DOUBLE_128__"); 5565 if (HasTransactionalExecution) 5566 Builder.defineMacro("__HTM__"); 5567 } 5568 void getTargetBuiltins(const Builtin::Info *&Records, 5569 unsigned &NumRecords) const override { 5570 Records = BuiltinInfo; 5571 NumRecords = clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin; 5572 } 5573 5574 void getGCCRegNames(const char *const *&Names, 5575 unsigned &NumNames) const override; 5576 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5577 unsigned &NumAliases) const override { 5578 // No aliases. 5579 Aliases = nullptr; 5580 NumAliases = 0; 5581 } 5582 bool validateAsmConstraint(const char *&Name, 5583 TargetInfo::ConstraintInfo &info) const override; 5584 const char *getClobbers() const override { 5585 // FIXME: Is this really right? 5586 return ""; 5587 } 5588 BuiltinVaListKind getBuiltinVaListKind() const override { 5589 return TargetInfo::SystemZBuiltinVaList; 5590 } 5591 bool setCPU(const std::string &Name) override { 5592 CPU = Name; 5593 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5594 .Case("z10", true) 5595 .Case("z196", true) 5596 .Case("zEC12", true) 5597 .Case("z13", true) 5598 .Default(false); 5599 5600 return CPUKnown; 5601 } 5602 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5603 if (CPU == "zEC12") 5604 Features["transactional-execution"] = true; 5605 if (CPU == "z13") { 5606 Features["transactional-execution"] = true; 5607 Features["vector"] = true; 5608 } 5609 } 5610 5611 bool handleTargetFeatures(std::vector<std::string> &Features, 5612 DiagnosticsEngine &Diags) override { 5613 HasTransactionalExecution = false; 5614 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 5615 if (Features[i] == "+transactional-execution") 5616 HasTransactionalExecution = true; 5617 if (Features[i] == "+vector") 5618 HasVector = true; 5619 } 5620 // If we use the vector ABI, vector types are 64-bit aligned. 5621 if (HasVector) { 5622 MaxVectorAlign = 64; 5623 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 5624 "-v128:64-a:8:16-n32:64"; 5625 } 5626 return true; 5627 } 5628 5629 bool hasFeature(StringRef Feature) const override { 5630 return llvm::StringSwitch<bool>(Feature) 5631 .Case("systemz", true) 5632 .Case("htm", HasTransactionalExecution) 5633 .Case("vx", HasVector) 5634 .Default(false); 5635 } 5636 5637 StringRef getABI() const override { 5638 if (HasVector) 5639 return "vector"; 5640 return ""; 5641 } 5642 }; 5643 5644 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 5645 #define BUILTIN(ID, TYPE, ATTRS) \ 5646 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5647 #include "clang/Basic/BuiltinsSystemZ.def" 5648 }; 5649 5650 const char *const SystemZTargetInfo::GCCRegNames[] = { 5651 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5652 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5653 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 5654 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 5655 }; 5656 5657 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 5658 unsigned &NumNames) const { 5659 Names = GCCRegNames; 5660 NumNames = llvm::array_lengthof(GCCRegNames); 5661 } 5662 5663 bool SystemZTargetInfo:: 5664 validateAsmConstraint(const char *&Name, 5665 TargetInfo::ConstraintInfo &Info) const { 5666 switch (*Name) { 5667 default: 5668 return false; 5669 5670 case 'a': // Address register 5671 case 'd': // Data register (equivalent to 'r') 5672 case 'f': // Floating-point register 5673 Info.setAllowsRegister(); 5674 return true; 5675 5676 case 'I': // Unsigned 8-bit constant 5677 case 'J': // Unsigned 12-bit constant 5678 case 'K': // Signed 16-bit constant 5679 case 'L': // Signed 20-bit displacement (on all targets we support) 5680 case 'M': // 0x7fffffff 5681 return true; 5682 5683 case 'Q': // Memory with base and unsigned 12-bit displacement 5684 case 'R': // Likewise, plus an index 5685 case 'S': // Memory with base and signed 20-bit displacement 5686 case 'T': // Likewise, plus an index 5687 Info.setAllowsMemory(); 5688 return true; 5689 } 5690 } 5691 5692 class MSP430TargetInfo : public TargetInfo { 5693 static const char * const GCCRegNames[]; 5694 public: 5695 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5696 BigEndian = false; 5697 TLSSupported = false; 5698 IntWidth = 16; IntAlign = 16; 5699 LongWidth = 32; LongLongWidth = 64; 5700 LongAlign = LongLongAlign = 16; 5701 PointerWidth = 16; PointerAlign = 16; 5702 SuitableAlign = 16; 5703 SizeType = UnsignedInt; 5704 IntMaxType = SignedLongLong; 5705 IntPtrType = SignedInt; 5706 PtrDiffType = SignedInt; 5707 SigAtomicType = SignedLong; 5708 DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 5709 } 5710 void getTargetDefines(const LangOptions &Opts, 5711 MacroBuilder &Builder) const override { 5712 Builder.defineMacro("MSP430"); 5713 Builder.defineMacro("__MSP430__"); 5714 // FIXME: defines for different 'flavours' of MCU 5715 } 5716 void getTargetBuiltins(const Builtin::Info *&Records, 5717 unsigned &NumRecords) const override { 5718 // FIXME: Implement. 5719 Records = nullptr; 5720 NumRecords = 0; 5721 } 5722 bool hasFeature(StringRef Feature) const override { 5723 return Feature == "msp430"; 5724 } 5725 void getGCCRegNames(const char * const *&Names, 5726 unsigned &NumNames) const override; 5727 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5728 unsigned &NumAliases) const override { 5729 // No aliases. 5730 Aliases = nullptr; 5731 NumAliases = 0; 5732 } 5733 bool 5734 validateAsmConstraint(const char *&Name, 5735 TargetInfo::ConstraintInfo &info) const override { 5736 // FIXME: implement 5737 switch (*Name) { 5738 case 'K': // the constant 1 5739 case 'L': // constant -1^20 .. 1^19 5740 case 'M': // constant 1-4: 5741 return true; 5742 } 5743 // No target constraints for now. 5744 return false; 5745 } 5746 const char *getClobbers() const override { 5747 // FIXME: Is this really right? 5748 return ""; 5749 } 5750 BuiltinVaListKind getBuiltinVaListKind() const override { 5751 // FIXME: implement 5752 return TargetInfo::CharPtrBuiltinVaList; 5753 } 5754 }; 5755 5756 const char * const MSP430TargetInfo::GCCRegNames[] = { 5757 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5758 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 5759 }; 5760 5761 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 5762 unsigned &NumNames) const { 5763 Names = GCCRegNames; 5764 NumNames = llvm::array_lengthof(GCCRegNames); 5765 } 5766 5767 // LLVM and Clang cannot be used directly to output native binaries for 5768 // target, but is used to compile C code to llvm bitcode with correct 5769 // type and alignment information. 5770 // 5771 // TCE uses the llvm bitcode as input and uses it for generating customized 5772 // target processor and program binary. TCE co-design environment is 5773 // publicly available in http://tce.cs.tut.fi 5774 5775 static const unsigned TCEOpenCLAddrSpaceMap[] = { 5776 3, // opencl_global 5777 4, // opencl_local 5778 5, // opencl_constant 5779 // FIXME: generic has to be added to the target 5780 0, // opencl_generic 5781 0, // cuda_device 5782 0, // cuda_constant 5783 0 // cuda_shared 5784 }; 5785 5786 class TCETargetInfo : public TargetInfo{ 5787 public: 5788 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5789 TLSSupported = false; 5790 IntWidth = 32; 5791 LongWidth = LongLongWidth = 32; 5792 PointerWidth = 32; 5793 IntAlign = 32; 5794 LongAlign = LongLongAlign = 32; 5795 PointerAlign = 32; 5796 SuitableAlign = 32; 5797 SizeType = UnsignedInt; 5798 IntMaxType = SignedLong; 5799 IntPtrType = SignedInt; 5800 PtrDiffType = SignedInt; 5801 FloatWidth = 32; 5802 FloatAlign = 32; 5803 DoubleWidth = 32; 5804 DoubleAlign = 32; 5805 LongDoubleWidth = 32; 5806 LongDoubleAlign = 32; 5807 FloatFormat = &llvm::APFloat::IEEEsingle; 5808 DoubleFormat = &llvm::APFloat::IEEEsingle; 5809 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 5810 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 5811 "-f64:32-v64:32-v128:32-a:0:32-n32"; 5812 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 5813 UseAddrSpaceMapMangling = true; 5814 } 5815 5816 void getTargetDefines(const LangOptions &Opts, 5817 MacroBuilder &Builder) const override { 5818 DefineStd(Builder, "tce", Opts); 5819 Builder.defineMacro("__TCE__"); 5820 Builder.defineMacro("__TCE_V1__"); 5821 } 5822 bool hasFeature(StringRef Feature) const override { 5823 return Feature == "tce"; 5824 } 5825 5826 void getTargetBuiltins(const Builtin::Info *&Records, 5827 unsigned &NumRecords) const override {} 5828 const char *getClobbers() const override { 5829 return ""; 5830 } 5831 BuiltinVaListKind getBuiltinVaListKind() const override { 5832 return TargetInfo::VoidPtrBuiltinVaList; 5833 } 5834 void getGCCRegNames(const char * const *&Names, 5835 unsigned &NumNames) const override {} 5836 bool validateAsmConstraint(const char *&Name, 5837 TargetInfo::ConstraintInfo &info) const override{ 5838 return true; 5839 } 5840 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5841 unsigned &NumAliases) const override {} 5842 }; 5843 5844 class MipsTargetInfoBase : public TargetInfo { 5845 virtual void setDescriptionString() = 0; 5846 5847 static const Builtin::Info BuiltinInfo[]; 5848 std::string CPU; 5849 bool IsMips16; 5850 bool IsMicromips; 5851 bool IsNan2008; 5852 bool IsSingleFloat; 5853 enum MipsFloatABI { 5854 HardFloat, SoftFloat 5855 } FloatABI; 5856 enum DspRevEnum { 5857 NoDSP, DSP1, DSP2 5858 } DspRev; 5859 bool HasMSA; 5860 5861 protected: 5862 bool HasFP64; 5863 std::string ABI; 5864 5865 public: 5866 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 5867 const std::string &CPUStr) 5868 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 5869 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 5870 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 5871 TheCXXABI.set(TargetCXXABI::GenericMIPS); 5872 } 5873 5874 bool isNaN2008Default() const { 5875 return CPU == "mips32r6" || CPU == "mips64r6"; 5876 } 5877 5878 bool isFP64Default() const { 5879 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 5880 } 5881 5882 bool isNan2008() const override { 5883 return IsNan2008; 5884 } 5885 5886 StringRef getABI() const override { return ABI; } 5887 bool setCPU(const std::string &Name) override { 5888 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 5889 getTriple().getArch() == llvm::Triple::mipsel; 5890 CPU = Name; 5891 return llvm::StringSwitch<bool>(Name) 5892 .Case("mips1", IsMips32) 5893 .Case("mips2", IsMips32) 5894 .Case("mips3", true) 5895 .Case("mips4", true) 5896 .Case("mips5", true) 5897 .Case("mips32", IsMips32) 5898 .Case("mips32r2", IsMips32) 5899 .Case("mips32r3", IsMips32) 5900 .Case("mips32r5", IsMips32) 5901 .Case("mips32r6", IsMips32) 5902 .Case("mips64", true) 5903 .Case("mips64r2", true) 5904 .Case("mips64r3", true) 5905 .Case("mips64r5", true) 5906 .Case("mips64r6", true) 5907 .Case("octeon", true) 5908 .Default(false); 5909 } 5910 const std::string& getCPU() const { return CPU; } 5911 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5912 if (CPU == "octeon") 5913 Features["mips64r2"] = Features["cnmips"] = true; 5914 else 5915 Features[CPU] = true; 5916 } 5917 5918 void getTargetDefines(const LangOptions &Opts, 5919 MacroBuilder &Builder) const override { 5920 Builder.defineMacro("__mips__"); 5921 Builder.defineMacro("_mips"); 5922 if (Opts.GNUMode) 5923 Builder.defineMacro("mips"); 5924 5925 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5926 5927 switch (FloatABI) { 5928 case HardFloat: 5929 Builder.defineMacro("__mips_hard_float", Twine(1)); 5930 break; 5931 case SoftFloat: 5932 Builder.defineMacro("__mips_soft_float", Twine(1)); 5933 break; 5934 } 5935 5936 if (IsSingleFloat) 5937 Builder.defineMacro("__mips_single_float", Twine(1)); 5938 5939 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 5940 Builder.defineMacro("_MIPS_FPSET", 5941 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 5942 5943 if (IsMips16) 5944 Builder.defineMacro("__mips16", Twine(1)); 5945 5946 if (IsMicromips) 5947 Builder.defineMacro("__mips_micromips", Twine(1)); 5948 5949 if (IsNan2008) 5950 Builder.defineMacro("__mips_nan2008", Twine(1)); 5951 5952 switch (DspRev) { 5953 default: 5954 break; 5955 case DSP1: 5956 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 5957 Builder.defineMacro("__mips_dsp", Twine(1)); 5958 break; 5959 case DSP2: 5960 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 5961 Builder.defineMacro("__mips_dspr2", Twine(1)); 5962 Builder.defineMacro("__mips_dsp", Twine(1)); 5963 break; 5964 } 5965 5966 if (HasMSA) 5967 Builder.defineMacro("__mips_msa", Twine(1)); 5968 5969 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 5970 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 5971 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 5972 5973 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 5974 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 5975 } 5976 5977 void getTargetBuiltins(const Builtin::Info *&Records, 5978 unsigned &NumRecords) const override { 5979 Records = BuiltinInfo; 5980 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 5981 } 5982 bool hasFeature(StringRef Feature) const override { 5983 return llvm::StringSwitch<bool>(Feature) 5984 .Case("mips", true) 5985 .Case("fp64", HasFP64) 5986 .Default(false); 5987 } 5988 BuiltinVaListKind getBuiltinVaListKind() const override { 5989 return TargetInfo::VoidPtrBuiltinVaList; 5990 } 5991 void getGCCRegNames(const char * const *&Names, 5992 unsigned &NumNames) const override { 5993 static const char *const GCCRegNames[] = { 5994 // CPU register names 5995 // Must match second column of GCCRegAliases 5996 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 5997 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 5998 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 5999 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6000 // Floating point register names 6001 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6002 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6003 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6004 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6005 // Hi/lo and condition register names 6006 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6007 "$fcc5","$fcc6","$fcc7", 6008 // MSA register names 6009 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6010 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6011 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6012 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6013 // MSA control register names 6014 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6015 "$msarequest", "$msamap", "$msaunmap" 6016 }; 6017 Names = GCCRegNames; 6018 NumNames = llvm::array_lengthof(GCCRegNames); 6019 } 6020 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6021 unsigned &NumAliases) const override = 0; 6022 bool validateAsmConstraint(const char *&Name, 6023 TargetInfo::ConstraintInfo &Info) const override { 6024 switch (*Name) { 6025 default: 6026 return false; 6027 case 'r': // CPU registers. 6028 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6029 case 'y': // Equivalent to "r", backward compatibility only. 6030 case 'f': // floating-point registers. 6031 case 'c': // $25 for indirect jumps 6032 case 'l': // lo register 6033 case 'x': // hilo register pair 6034 Info.setAllowsRegister(); 6035 return true; 6036 case 'I': // Signed 16-bit constant 6037 case 'J': // Integer 0 6038 case 'K': // Unsigned 16-bit constant 6039 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6040 case 'M': // Constants not loadable via lui, addiu, or ori 6041 case 'N': // Constant -1 to -65535 6042 case 'O': // A signed 15-bit constant 6043 case 'P': // A constant between 1 go 65535 6044 return true; 6045 case 'R': // An address that can be used in a non-macro load or store 6046 Info.setAllowsMemory(); 6047 return true; 6048 case 'Z': 6049 if (Name[1] == 'C') { // An address usable by ll, and sc. 6050 Info.setAllowsMemory(); 6051 Name++; // Skip over 'Z'. 6052 return true; 6053 } 6054 return false; 6055 } 6056 } 6057 6058 std::string convertConstraint(const char *&Constraint) const override { 6059 std::string R; 6060 switch (*Constraint) { 6061 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6062 if (Constraint[1] == 'C') { 6063 R = std::string("^") + std::string(Constraint, 2); 6064 Constraint++; 6065 return R; 6066 } 6067 break; 6068 } 6069 return TargetInfo::convertConstraint(Constraint); 6070 } 6071 6072 const char *getClobbers() const override { 6073 // In GCC, $1 is not widely used in generated code (it's used only in a few 6074 // specific situations), so there is no real need for users to add it to 6075 // the clobbers list if they want to use it in their inline assembly code. 6076 // 6077 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6078 // code generation, so using it in inline assembly without adding it to the 6079 // clobbers list can cause conflicts between the inline assembly code and 6080 // the surrounding generated code. 6081 // 6082 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6083 // operands, which will conflict with the ".set at" assembler option (which 6084 // we use only for inline assembly, in order to maintain compatibility with 6085 // GCC) and will also conflict with the user's usage of $1. 6086 // 6087 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6088 // register for generated code is to automatically clobber $1 for all inline 6089 // assembly code. 6090 // 6091 // FIXME: We should automatically clobber $1 only for inline assembly code 6092 // which actually uses it. This would allow LLVM to use $1 for inline 6093 // assembly operands if the user's assembly code doesn't use it. 6094 return "~{$1}"; 6095 } 6096 6097 bool handleTargetFeatures(std::vector<std::string> &Features, 6098 DiagnosticsEngine &Diags) override { 6099 IsMips16 = false; 6100 IsMicromips = false; 6101 IsNan2008 = isNaN2008Default(); 6102 IsSingleFloat = false; 6103 FloatABI = HardFloat; 6104 DspRev = NoDSP; 6105 HasFP64 = isFP64Default(); 6106 6107 for (std::vector<std::string>::iterator it = Features.begin(), 6108 ie = Features.end(); it != ie; ++it) { 6109 if (*it == "+single-float") 6110 IsSingleFloat = true; 6111 else if (*it == "+soft-float") 6112 FloatABI = SoftFloat; 6113 else if (*it == "+mips16") 6114 IsMips16 = true; 6115 else if (*it == "+micromips") 6116 IsMicromips = true; 6117 else if (*it == "+dsp") 6118 DspRev = std::max(DspRev, DSP1); 6119 else if (*it == "+dspr2") 6120 DspRev = std::max(DspRev, DSP2); 6121 else if (*it == "+msa") 6122 HasMSA = true; 6123 else if (*it == "+fp64") 6124 HasFP64 = true; 6125 else if (*it == "-fp64") 6126 HasFP64 = false; 6127 else if (*it == "+nan2008") 6128 IsNan2008 = true; 6129 else if (*it == "-nan2008") 6130 IsNan2008 = false; 6131 } 6132 6133 // Remove front-end specific options. 6134 std::vector<std::string>::iterator it = 6135 std::find(Features.begin(), Features.end(), "+soft-float"); 6136 if (it != Features.end()) 6137 Features.erase(it); 6138 6139 setDescriptionString(); 6140 6141 return true; 6142 } 6143 6144 int getEHDataRegisterNumber(unsigned RegNo) const override { 6145 if (RegNo == 0) return 4; 6146 if (RegNo == 1) return 5; 6147 return -1; 6148 } 6149 6150 bool isCLZForZeroUndef() const override { return false; } 6151 }; 6152 6153 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 6154 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6155 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 6156 ALL_LANGUAGES }, 6157 #include "clang/Basic/BuiltinsMips.def" 6158 }; 6159 6160 class Mips32TargetInfoBase : public MipsTargetInfoBase { 6161 public: 6162 Mips32TargetInfoBase(const llvm::Triple &Triple) 6163 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 6164 SizeType = UnsignedInt; 6165 PtrDiffType = SignedInt; 6166 Int64Type = SignedLongLong; 6167 IntMaxType = Int64Type; 6168 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 6169 } 6170 bool setABI(const std::string &Name) override { 6171 if (Name == "o32" || Name == "eabi") { 6172 ABI = Name; 6173 return true; 6174 } 6175 return false; 6176 } 6177 void getTargetDefines(const LangOptions &Opts, 6178 MacroBuilder &Builder) const override { 6179 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6180 6181 Builder.defineMacro("__mips", "32"); 6182 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 6183 6184 const std::string& CPUStr = getCPU(); 6185 if (CPUStr == "mips32") 6186 Builder.defineMacro("__mips_isa_rev", "1"); 6187 else if (CPUStr == "mips32r2") 6188 Builder.defineMacro("__mips_isa_rev", "2"); 6189 else if (CPUStr == "mips32r3") 6190 Builder.defineMacro("__mips_isa_rev", "3"); 6191 else if (CPUStr == "mips32r5") 6192 Builder.defineMacro("__mips_isa_rev", "5"); 6193 else if (CPUStr == "mips32r6") 6194 Builder.defineMacro("__mips_isa_rev", "6"); 6195 6196 if (ABI == "o32") { 6197 Builder.defineMacro("__mips_o32"); 6198 Builder.defineMacro("_ABIO32", "1"); 6199 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6200 } 6201 else if (ABI == "eabi") 6202 Builder.defineMacro("__mips_eabi"); 6203 else 6204 llvm_unreachable("Invalid ABI for Mips32."); 6205 } 6206 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6207 unsigned &NumAliases) const override { 6208 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6209 { { "at" }, "$1" }, 6210 { { "v0" }, "$2" }, 6211 { { "v1" }, "$3" }, 6212 { { "a0" }, "$4" }, 6213 { { "a1" }, "$5" }, 6214 { { "a2" }, "$6" }, 6215 { { "a3" }, "$7" }, 6216 { { "t0" }, "$8" }, 6217 { { "t1" }, "$9" }, 6218 { { "t2" }, "$10" }, 6219 { { "t3" }, "$11" }, 6220 { { "t4" }, "$12" }, 6221 { { "t5" }, "$13" }, 6222 { { "t6" }, "$14" }, 6223 { { "t7" }, "$15" }, 6224 { { "s0" }, "$16" }, 6225 { { "s1" }, "$17" }, 6226 { { "s2" }, "$18" }, 6227 { { "s3" }, "$19" }, 6228 { { "s4" }, "$20" }, 6229 { { "s5" }, "$21" }, 6230 { { "s6" }, "$22" }, 6231 { { "s7" }, "$23" }, 6232 { { "t8" }, "$24" }, 6233 { { "t9" }, "$25" }, 6234 { { "k0" }, "$26" }, 6235 { { "k1" }, "$27" }, 6236 { { "gp" }, "$28" }, 6237 { { "sp","$sp" }, "$29" }, 6238 { { "fp","$fp" }, "$30" }, 6239 { { "ra" }, "$31" } 6240 }; 6241 Aliases = GCCRegAliases; 6242 NumAliases = llvm::array_lengthof(GCCRegAliases); 6243 } 6244 }; 6245 6246 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6247 void setDescriptionString() override { 6248 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6249 } 6250 6251 public: 6252 Mips32EBTargetInfo(const llvm::Triple &Triple) 6253 : Mips32TargetInfoBase(Triple) { 6254 } 6255 void getTargetDefines(const LangOptions &Opts, 6256 MacroBuilder &Builder) const override { 6257 DefineStd(Builder, "MIPSEB", Opts); 6258 Builder.defineMacro("_MIPSEB"); 6259 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6260 } 6261 }; 6262 6263 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6264 void setDescriptionString() override { 6265 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6266 } 6267 6268 public: 6269 Mips32ELTargetInfo(const llvm::Triple &Triple) 6270 : Mips32TargetInfoBase(Triple) { 6271 BigEndian = false; 6272 } 6273 void getTargetDefines(const LangOptions &Opts, 6274 MacroBuilder &Builder) const override { 6275 DefineStd(Builder, "MIPSEL", Opts); 6276 Builder.defineMacro("_MIPSEL"); 6277 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6278 } 6279 }; 6280 6281 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6282 public: 6283 Mips64TargetInfoBase(const llvm::Triple &Triple) 6284 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6285 LongDoubleWidth = LongDoubleAlign = 128; 6286 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6287 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6288 LongDoubleWidth = LongDoubleAlign = 64; 6289 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6290 } 6291 setN64ABITypes(); 6292 SuitableAlign = 128; 6293 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6294 } 6295 6296 void setN64ABITypes() { 6297 LongWidth = LongAlign = 64; 6298 PointerWidth = PointerAlign = 64; 6299 SizeType = UnsignedLong; 6300 PtrDiffType = SignedLong; 6301 Int64Type = SignedLong; 6302 IntMaxType = Int64Type; 6303 } 6304 6305 void setN32ABITypes() { 6306 LongWidth = LongAlign = 32; 6307 PointerWidth = PointerAlign = 32; 6308 SizeType = UnsignedInt; 6309 PtrDiffType = SignedInt; 6310 Int64Type = SignedLongLong; 6311 IntMaxType = Int64Type; 6312 } 6313 6314 bool setABI(const std::string &Name) override { 6315 if (Name == "n32") { 6316 setN32ABITypes(); 6317 ABI = Name; 6318 return true; 6319 } 6320 if (Name == "n64") { 6321 setN64ABITypes(); 6322 ABI = Name; 6323 return true; 6324 } 6325 return false; 6326 } 6327 6328 void getTargetDefines(const LangOptions &Opts, 6329 MacroBuilder &Builder) const override { 6330 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6331 6332 Builder.defineMacro("__mips", "64"); 6333 Builder.defineMacro("__mips64"); 6334 Builder.defineMacro("__mips64__"); 6335 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 6336 6337 const std::string& CPUStr = getCPU(); 6338 if (CPUStr == "mips64") 6339 Builder.defineMacro("__mips_isa_rev", "1"); 6340 else if (CPUStr == "mips64r2") 6341 Builder.defineMacro("__mips_isa_rev", "2"); 6342 else if (CPUStr == "mips64r3") 6343 Builder.defineMacro("__mips_isa_rev", "3"); 6344 else if (CPUStr == "mips64r5") 6345 Builder.defineMacro("__mips_isa_rev", "5"); 6346 else if (CPUStr == "mips64r6") 6347 Builder.defineMacro("__mips_isa_rev", "6"); 6348 6349 if (ABI == "n32") { 6350 Builder.defineMacro("__mips_n32"); 6351 Builder.defineMacro("_ABIN32", "2"); 6352 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 6353 } 6354 else if (ABI == "n64") { 6355 Builder.defineMacro("__mips_n64"); 6356 Builder.defineMacro("_ABI64", "3"); 6357 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 6358 } 6359 else 6360 llvm_unreachable("Invalid ABI for Mips64."); 6361 } 6362 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6363 unsigned &NumAliases) const override { 6364 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6365 { { "at" }, "$1" }, 6366 { { "v0" }, "$2" }, 6367 { { "v1" }, "$3" }, 6368 { { "a0" }, "$4" }, 6369 { { "a1" }, "$5" }, 6370 { { "a2" }, "$6" }, 6371 { { "a3" }, "$7" }, 6372 { { "a4" }, "$8" }, 6373 { { "a5" }, "$9" }, 6374 { { "a6" }, "$10" }, 6375 { { "a7" }, "$11" }, 6376 { { "t0" }, "$12" }, 6377 { { "t1" }, "$13" }, 6378 { { "t2" }, "$14" }, 6379 { { "t3" }, "$15" }, 6380 { { "s0" }, "$16" }, 6381 { { "s1" }, "$17" }, 6382 { { "s2" }, "$18" }, 6383 { { "s3" }, "$19" }, 6384 { { "s4" }, "$20" }, 6385 { { "s5" }, "$21" }, 6386 { { "s6" }, "$22" }, 6387 { { "s7" }, "$23" }, 6388 { { "t8" }, "$24" }, 6389 { { "t9" }, "$25" }, 6390 { { "k0" }, "$26" }, 6391 { { "k1" }, "$27" }, 6392 { { "gp" }, "$28" }, 6393 { { "sp","$sp" }, "$29" }, 6394 { { "fp","$fp" }, "$30" }, 6395 { { "ra" }, "$31" } 6396 }; 6397 Aliases = GCCRegAliases; 6398 NumAliases = llvm::array_lengthof(GCCRegAliases); 6399 } 6400 6401 bool hasInt128Type() const override { return true; } 6402 }; 6403 6404 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 6405 void setDescriptionString() override { 6406 if (ABI == "n32") 6407 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6408 else 6409 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6410 6411 } 6412 6413 public: 6414 Mips64EBTargetInfo(const llvm::Triple &Triple) 6415 : Mips64TargetInfoBase(Triple) {} 6416 void getTargetDefines(const LangOptions &Opts, 6417 MacroBuilder &Builder) const override { 6418 DefineStd(Builder, "MIPSEB", Opts); 6419 Builder.defineMacro("_MIPSEB"); 6420 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6421 } 6422 }; 6423 6424 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 6425 void setDescriptionString() override { 6426 if (ABI == "n32") 6427 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6428 else 6429 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6430 } 6431 public: 6432 Mips64ELTargetInfo(const llvm::Triple &Triple) 6433 : Mips64TargetInfoBase(Triple) { 6434 // Default ABI is n64. 6435 BigEndian = false; 6436 } 6437 void getTargetDefines(const LangOptions &Opts, 6438 MacroBuilder &Builder) const override { 6439 DefineStd(Builder, "MIPSEL", Opts); 6440 Builder.defineMacro("_MIPSEL"); 6441 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6442 } 6443 }; 6444 6445 class PNaClTargetInfo : public TargetInfo { 6446 public: 6447 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6448 BigEndian = false; 6449 this->UserLabelPrefix = ""; 6450 this->LongAlign = 32; 6451 this->LongWidth = 32; 6452 this->PointerAlign = 32; 6453 this->PointerWidth = 32; 6454 this->IntMaxType = TargetInfo::SignedLongLong; 6455 this->Int64Type = TargetInfo::SignedLongLong; 6456 this->DoubleAlign = 64; 6457 this->LongDoubleWidth = 64; 6458 this->LongDoubleAlign = 64; 6459 this->SizeType = TargetInfo::UnsignedInt; 6460 this->PtrDiffType = TargetInfo::SignedInt; 6461 this->IntPtrType = TargetInfo::SignedInt; 6462 this->RegParmMax = 0; // Disallow regparm 6463 } 6464 6465 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 6466 } 6467 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 6468 Builder.defineMacro("__le32__"); 6469 Builder.defineMacro("__pnacl__"); 6470 } 6471 void getTargetDefines(const LangOptions &Opts, 6472 MacroBuilder &Builder) const override { 6473 getArchDefines(Opts, Builder); 6474 } 6475 bool hasFeature(StringRef Feature) const override { 6476 return Feature == "pnacl"; 6477 } 6478 void getTargetBuiltins(const Builtin::Info *&Records, 6479 unsigned &NumRecords) const override { 6480 } 6481 BuiltinVaListKind getBuiltinVaListKind() const override { 6482 return TargetInfo::PNaClABIBuiltinVaList; 6483 } 6484 void getGCCRegNames(const char * const *&Names, 6485 unsigned &NumNames) const override; 6486 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6487 unsigned &NumAliases) const override; 6488 bool validateAsmConstraint(const char *&Name, 6489 TargetInfo::ConstraintInfo &Info) const override { 6490 return false; 6491 } 6492 6493 const char *getClobbers() const override { 6494 return ""; 6495 } 6496 }; 6497 6498 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 6499 unsigned &NumNames) const { 6500 Names = nullptr; 6501 NumNames = 0; 6502 } 6503 6504 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 6505 unsigned &NumAliases) const { 6506 Aliases = nullptr; 6507 NumAliases = 0; 6508 } 6509 6510 class Le64TargetInfo : public TargetInfo { 6511 static const Builtin::Info BuiltinInfo[]; 6512 6513 public: 6514 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6515 BigEndian = false; 6516 NoAsmVariants = true; 6517 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6518 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6519 DescriptionString = 6520 "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 6521 } 6522 6523 void getTargetDefines(const LangOptions &Opts, 6524 MacroBuilder &Builder) const override { 6525 DefineStd(Builder, "unix", Opts); 6526 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 6527 Builder.defineMacro("__ELF__"); 6528 } 6529 void getTargetBuiltins(const Builtin::Info *&Records, 6530 unsigned &NumRecords) const override { 6531 Records = BuiltinInfo; 6532 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin; 6533 } 6534 BuiltinVaListKind getBuiltinVaListKind() const override { 6535 return TargetInfo::PNaClABIBuiltinVaList; 6536 } 6537 const char *getClobbers() const override { return ""; } 6538 void getGCCRegNames(const char *const *&Names, 6539 unsigned &NumNames) const override { 6540 Names = nullptr; 6541 NumNames = 0; 6542 } 6543 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6544 unsigned &NumAliases) const override { 6545 Aliases = nullptr; 6546 NumAliases = 0; 6547 } 6548 bool validateAsmConstraint(const char *&Name, 6549 TargetInfo::ConstraintInfo &Info) const override { 6550 return false; 6551 } 6552 6553 bool hasProtectedVisibility() const override { return false; } 6554 }; 6555 } // end anonymous namespace. 6556 6557 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 6558 #define BUILTIN(ID, TYPE, ATTRS) \ 6559 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6560 #include "clang/Basic/BuiltinsLe64.def" 6561 }; 6562 6563 namespace { 6564 static const unsigned SPIRAddrSpaceMap[] = { 6565 1, // opencl_global 6566 3, // opencl_local 6567 2, // opencl_constant 6568 4, // opencl_generic 6569 0, // cuda_device 6570 0, // cuda_constant 6571 0 // cuda_shared 6572 }; 6573 class SPIRTargetInfo : public TargetInfo { 6574 public: 6575 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6576 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 6577 "SPIR target must use unknown OS"); 6578 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 6579 "SPIR target must use unknown environment type"); 6580 BigEndian = false; 6581 TLSSupported = false; 6582 LongWidth = LongAlign = 64; 6583 AddrSpaceMap = &SPIRAddrSpaceMap; 6584 UseAddrSpaceMapMangling = true; 6585 // Define available target features 6586 // These must be defined in sorted order! 6587 NoAsmVariants = true; 6588 } 6589 void getTargetDefines(const LangOptions &Opts, 6590 MacroBuilder &Builder) const override { 6591 DefineStd(Builder, "SPIR", Opts); 6592 } 6593 bool hasFeature(StringRef Feature) const override { 6594 return Feature == "spir"; 6595 } 6596 6597 void getTargetBuiltins(const Builtin::Info *&Records, 6598 unsigned &NumRecords) const override {} 6599 const char *getClobbers() const override { 6600 return ""; 6601 } 6602 void getGCCRegNames(const char * const *&Names, 6603 unsigned &NumNames) const override {} 6604 bool 6605 validateAsmConstraint(const char *&Name, 6606 TargetInfo::ConstraintInfo &info) const override { 6607 return true; 6608 } 6609 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6610 unsigned &NumAliases) const override {} 6611 BuiltinVaListKind getBuiltinVaListKind() const override { 6612 return TargetInfo::VoidPtrBuiltinVaList; 6613 } 6614 6615 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6616 return (CC == CC_SpirFunction || 6617 CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning; 6618 } 6619 6620 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 6621 return CC_SpirFunction; 6622 } 6623 }; 6624 6625 6626 class SPIR32TargetInfo : public SPIRTargetInfo { 6627 public: 6628 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6629 PointerWidth = PointerAlign = 32; 6630 SizeType = TargetInfo::UnsignedInt; 6631 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 6632 DescriptionString 6633 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 6634 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6635 } 6636 void getTargetDefines(const LangOptions &Opts, 6637 MacroBuilder &Builder) const override { 6638 DefineStd(Builder, "SPIR32", Opts); 6639 } 6640 }; 6641 6642 class SPIR64TargetInfo : public SPIRTargetInfo { 6643 public: 6644 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6645 PointerWidth = PointerAlign = 64; 6646 SizeType = TargetInfo::UnsignedLong; 6647 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 6648 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 6649 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6650 } 6651 void getTargetDefines(const LangOptions &Opts, 6652 MacroBuilder &Builder) const override { 6653 DefineStd(Builder, "SPIR64", Opts); 6654 } 6655 }; 6656 6657 class XCoreTargetInfo : public TargetInfo { 6658 static const Builtin::Info BuiltinInfo[]; 6659 public: 6660 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6661 BigEndian = false; 6662 NoAsmVariants = true; 6663 LongLongAlign = 32; 6664 SuitableAlign = 32; 6665 DoubleAlign = LongDoubleAlign = 32; 6666 SizeType = UnsignedInt; 6667 PtrDiffType = SignedInt; 6668 IntPtrType = SignedInt; 6669 WCharType = UnsignedChar; 6670 WIntType = UnsignedInt; 6671 UseZeroLengthBitfieldAlignment = true; 6672 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 6673 "-f64:32-a:0:32-n32"; 6674 } 6675 void getTargetDefines(const LangOptions &Opts, 6676 MacroBuilder &Builder) const override { 6677 Builder.defineMacro("__XS1B__"); 6678 } 6679 void getTargetBuiltins(const Builtin::Info *&Records, 6680 unsigned &NumRecords) const override { 6681 Records = BuiltinInfo; 6682 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 6683 } 6684 BuiltinVaListKind getBuiltinVaListKind() const override { 6685 return TargetInfo::VoidPtrBuiltinVaList; 6686 } 6687 const char *getClobbers() const override { 6688 return ""; 6689 } 6690 void getGCCRegNames(const char * const *&Names, 6691 unsigned &NumNames) const override { 6692 static const char * const GCCRegNames[] = { 6693 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6694 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 6695 }; 6696 Names = GCCRegNames; 6697 NumNames = llvm::array_lengthof(GCCRegNames); 6698 } 6699 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6700 unsigned &NumAliases) const override { 6701 Aliases = nullptr; 6702 NumAliases = 0; 6703 } 6704 bool validateAsmConstraint(const char *&Name, 6705 TargetInfo::ConstraintInfo &Info) const override { 6706 return false; 6707 } 6708 int getEHDataRegisterNumber(unsigned RegNo) const override { 6709 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 6710 return (RegNo < 2)? RegNo : -1; 6711 } 6712 }; 6713 6714 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 6715 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6716 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 6717 ALL_LANGUAGES }, 6718 #include "clang/Basic/BuiltinsXCore.def" 6719 }; 6720 } // end anonymous namespace. 6721 6722 namespace { 6723 // x86_32 Android target 6724 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 6725 public: 6726 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 6727 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 6728 SuitableAlign = 32; 6729 LongDoubleWidth = 64; 6730 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6731 } 6732 }; 6733 } // end anonymous namespace 6734 6735 namespace { 6736 // x86_64 Android target 6737 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 6738 public: 6739 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 6740 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 6741 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6742 } 6743 }; 6744 } // end anonymous namespace 6745 6746 6747 //===----------------------------------------------------------------------===// 6748 // Driver code 6749 //===----------------------------------------------------------------------===// 6750 6751 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 6752 llvm::Triple::OSType os = Triple.getOS(); 6753 6754 switch (Triple.getArch()) { 6755 default: 6756 return nullptr; 6757 6758 case llvm::Triple::xcore: 6759 return new XCoreTargetInfo(Triple); 6760 6761 case llvm::Triple::hexagon: 6762 return new HexagonTargetInfo(Triple); 6763 6764 case llvm::Triple::aarch64: 6765 if (Triple.isOSDarwin()) 6766 return new DarwinAArch64TargetInfo(Triple); 6767 6768 switch (os) { 6769 case llvm::Triple::FreeBSD: 6770 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 6771 case llvm::Triple::Linux: 6772 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 6773 case llvm::Triple::NetBSD: 6774 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 6775 default: 6776 return new AArch64leTargetInfo(Triple); 6777 } 6778 6779 case llvm::Triple::aarch64_be: 6780 switch (os) { 6781 case llvm::Triple::FreeBSD: 6782 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 6783 case llvm::Triple::Linux: 6784 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 6785 case llvm::Triple::NetBSD: 6786 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 6787 default: 6788 return new AArch64beTargetInfo(Triple); 6789 } 6790 6791 case llvm::Triple::arm: 6792 case llvm::Triple::thumb: 6793 if (Triple.isOSBinFormatMachO()) 6794 return new DarwinARMTargetInfo(Triple); 6795 6796 switch (os) { 6797 case llvm::Triple::Linux: 6798 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 6799 case llvm::Triple::FreeBSD: 6800 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 6801 case llvm::Triple::NetBSD: 6802 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 6803 case llvm::Triple::OpenBSD: 6804 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 6805 case llvm::Triple::Bitrig: 6806 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 6807 case llvm::Triple::RTEMS: 6808 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 6809 case llvm::Triple::NaCl: 6810 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 6811 case llvm::Triple::Win32: 6812 switch (Triple.getEnvironment()) { 6813 default: 6814 return new ARMleTargetInfo(Triple); 6815 case llvm::Triple::Itanium: 6816 return new ItaniumWindowsARMleTargetInfo(Triple); 6817 case llvm::Triple::MSVC: 6818 return new MicrosoftARMleTargetInfo(Triple); 6819 } 6820 default: 6821 return new ARMleTargetInfo(Triple); 6822 } 6823 6824 case llvm::Triple::armeb: 6825 case llvm::Triple::thumbeb: 6826 if (Triple.isOSDarwin()) 6827 return new DarwinARMTargetInfo(Triple); 6828 6829 switch (os) { 6830 case llvm::Triple::Linux: 6831 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 6832 case llvm::Triple::FreeBSD: 6833 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 6834 case llvm::Triple::NetBSD: 6835 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 6836 case llvm::Triple::OpenBSD: 6837 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 6838 case llvm::Triple::Bitrig: 6839 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 6840 case llvm::Triple::RTEMS: 6841 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 6842 case llvm::Triple::NaCl: 6843 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 6844 default: 6845 return new ARMbeTargetInfo(Triple); 6846 } 6847 6848 case llvm::Triple::msp430: 6849 return new MSP430TargetInfo(Triple); 6850 6851 case llvm::Triple::mips: 6852 switch (os) { 6853 case llvm::Triple::Linux: 6854 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 6855 case llvm::Triple::RTEMS: 6856 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 6857 case llvm::Triple::FreeBSD: 6858 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6859 case llvm::Triple::NetBSD: 6860 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6861 default: 6862 return new Mips32EBTargetInfo(Triple); 6863 } 6864 6865 case llvm::Triple::mipsel: 6866 switch (os) { 6867 case llvm::Triple::Linux: 6868 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 6869 case llvm::Triple::RTEMS: 6870 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 6871 case llvm::Triple::FreeBSD: 6872 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6873 case llvm::Triple::NetBSD: 6874 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6875 case llvm::Triple::NaCl: 6876 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 6877 default: 6878 return new Mips32ELTargetInfo(Triple); 6879 } 6880 6881 case llvm::Triple::mips64: 6882 switch (os) { 6883 case llvm::Triple::Linux: 6884 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 6885 case llvm::Triple::RTEMS: 6886 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 6887 case llvm::Triple::FreeBSD: 6888 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6889 case llvm::Triple::NetBSD: 6890 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6891 case llvm::Triple::OpenBSD: 6892 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6893 default: 6894 return new Mips64EBTargetInfo(Triple); 6895 } 6896 6897 case llvm::Triple::mips64el: 6898 switch (os) { 6899 case llvm::Triple::Linux: 6900 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 6901 case llvm::Triple::RTEMS: 6902 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 6903 case llvm::Triple::FreeBSD: 6904 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6905 case llvm::Triple::NetBSD: 6906 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6907 case llvm::Triple::OpenBSD: 6908 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6909 default: 6910 return new Mips64ELTargetInfo(Triple); 6911 } 6912 6913 case llvm::Triple::le32: 6914 switch (os) { 6915 case llvm::Triple::NaCl: 6916 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 6917 default: 6918 return nullptr; 6919 } 6920 6921 case llvm::Triple::le64: 6922 return new Le64TargetInfo(Triple); 6923 6924 case llvm::Triple::ppc: 6925 if (Triple.isOSDarwin()) 6926 return new DarwinPPC32TargetInfo(Triple); 6927 switch (os) { 6928 case llvm::Triple::Linux: 6929 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 6930 case llvm::Triple::FreeBSD: 6931 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 6932 case llvm::Triple::NetBSD: 6933 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 6934 case llvm::Triple::OpenBSD: 6935 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 6936 case llvm::Triple::RTEMS: 6937 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 6938 default: 6939 return new PPC32TargetInfo(Triple); 6940 } 6941 6942 case llvm::Triple::ppc64: 6943 if (Triple.isOSDarwin()) 6944 return new DarwinPPC64TargetInfo(Triple); 6945 switch (os) { 6946 case llvm::Triple::Linux: 6947 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6948 case llvm::Triple::Lv2: 6949 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 6950 case llvm::Triple::FreeBSD: 6951 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 6952 case llvm::Triple::NetBSD: 6953 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 6954 default: 6955 return new PPC64TargetInfo(Triple); 6956 } 6957 6958 case llvm::Triple::ppc64le: 6959 switch (os) { 6960 case llvm::Triple::Linux: 6961 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6962 case llvm::Triple::NetBSD: 6963 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 6964 default: 6965 return new PPC64TargetInfo(Triple); 6966 } 6967 6968 case llvm::Triple::nvptx: 6969 return new NVPTX32TargetInfo(Triple); 6970 case llvm::Triple::nvptx64: 6971 return new NVPTX64TargetInfo(Triple); 6972 6973 case llvm::Triple::amdgcn: 6974 case llvm::Triple::r600: 6975 return new R600TargetInfo(Triple); 6976 6977 case llvm::Triple::sparc: 6978 switch (os) { 6979 case llvm::Triple::Linux: 6980 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 6981 case llvm::Triple::Solaris: 6982 return new SolarisSparcV8TargetInfo(Triple); 6983 case llvm::Triple::NetBSD: 6984 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 6985 case llvm::Triple::OpenBSD: 6986 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 6987 case llvm::Triple::RTEMS: 6988 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 6989 default: 6990 return new SparcV8TargetInfo(Triple); 6991 } 6992 6993 case llvm::Triple::sparcv9: 6994 switch (os) { 6995 case llvm::Triple::Linux: 6996 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 6997 case llvm::Triple::Solaris: 6998 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 6999 case llvm::Triple::NetBSD: 7000 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 7001 case llvm::Triple::OpenBSD: 7002 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 7003 case llvm::Triple::FreeBSD: 7004 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 7005 default: 7006 return new SparcV9TargetInfo(Triple); 7007 } 7008 7009 case llvm::Triple::systemz: 7010 switch (os) { 7011 case llvm::Triple::Linux: 7012 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 7013 default: 7014 return new SystemZTargetInfo(Triple); 7015 } 7016 7017 case llvm::Triple::tce: 7018 return new TCETargetInfo(Triple); 7019 7020 case llvm::Triple::x86: 7021 if (Triple.isOSDarwin()) 7022 return new DarwinI386TargetInfo(Triple); 7023 7024 switch (os) { 7025 case llvm::Triple::Linux: { 7026 switch (Triple.getEnvironment()) { 7027 default: 7028 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 7029 case llvm::Triple::Android: 7030 return new AndroidX86_32TargetInfo(Triple); 7031 } 7032 } 7033 case llvm::Triple::DragonFly: 7034 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 7035 case llvm::Triple::NetBSD: 7036 return new NetBSDI386TargetInfo(Triple); 7037 case llvm::Triple::OpenBSD: 7038 return new OpenBSDI386TargetInfo(Triple); 7039 case llvm::Triple::Bitrig: 7040 return new BitrigI386TargetInfo(Triple); 7041 case llvm::Triple::FreeBSD: 7042 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7043 case llvm::Triple::KFreeBSD: 7044 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7045 case llvm::Triple::Minix: 7046 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 7047 case llvm::Triple::Solaris: 7048 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 7049 case llvm::Triple::Win32: { 7050 switch (Triple.getEnvironment()) { 7051 default: 7052 return new X86_32TargetInfo(Triple); 7053 case llvm::Triple::Cygnus: 7054 return new CygwinX86_32TargetInfo(Triple); 7055 case llvm::Triple::GNU: 7056 return new MinGWX86_32TargetInfo(Triple); 7057 case llvm::Triple::Itanium: 7058 case llvm::Triple::MSVC: 7059 return new MicrosoftX86_32TargetInfo(Triple); 7060 } 7061 } 7062 case llvm::Triple::Haiku: 7063 return new HaikuX86_32TargetInfo(Triple); 7064 case llvm::Triple::RTEMS: 7065 return new RTEMSX86_32TargetInfo(Triple); 7066 case llvm::Triple::NaCl: 7067 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 7068 default: 7069 return new X86_32TargetInfo(Triple); 7070 } 7071 7072 case llvm::Triple::x86_64: 7073 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 7074 return new DarwinX86_64TargetInfo(Triple); 7075 7076 switch (os) { 7077 case llvm::Triple::CloudABI: 7078 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 7079 case llvm::Triple::Linux: { 7080 switch (Triple.getEnvironment()) { 7081 default: 7082 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 7083 case llvm::Triple::Android: 7084 return new AndroidX86_64TargetInfo(Triple); 7085 } 7086 } 7087 case llvm::Triple::DragonFly: 7088 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 7089 case llvm::Triple::NetBSD: 7090 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 7091 case llvm::Triple::OpenBSD: 7092 return new OpenBSDX86_64TargetInfo(Triple); 7093 case llvm::Triple::Bitrig: 7094 return new BitrigX86_64TargetInfo(Triple); 7095 case llvm::Triple::FreeBSD: 7096 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7097 case llvm::Triple::KFreeBSD: 7098 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7099 case llvm::Triple::Solaris: 7100 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 7101 case llvm::Triple::Win32: { 7102 switch (Triple.getEnvironment()) { 7103 default: 7104 return new X86_64TargetInfo(Triple); 7105 case llvm::Triple::GNU: 7106 return new MinGWX86_64TargetInfo(Triple); 7107 case llvm::Triple::MSVC: 7108 return new MicrosoftX86_64TargetInfo(Triple); 7109 } 7110 } 7111 case llvm::Triple::NaCl: 7112 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 7113 case llvm::Triple::PS4: 7114 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 7115 default: 7116 return new X86_64TargetInfo(Triple); 7117 } 7118 7119 case llvm::Triple::spir: { 7120 if (Triple.getOS() != llvm::Triple::UnknownOS || 7121 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7122 return nullptr; 7123 return new SPIR32TargetInfo(Triple); 7124 } 7125 case llvm::Triple::spir64: { 7126 if (Triple.getOS() != llvm::Triple::UnknownOS || 7127 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7128 return nullptr; 7129 return new SPIR64TargetInfo(Triple); 7130 } 7131 } 7132 } 7133 7134 /// CreateTargetInfo - Return the target info object for the specified target 7135 /// triple. 7136 TargetInfo * 7137 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 7138 const std::shared_ptr<TargetOptions> &Opts) { 7139 llvm::Triple Triple(Opts->Triple); 7140 7141 // Construct the target 7142 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 7143 if (!Target) { 7144 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 7145 return nullptr; 7146 } 7147 Target->TargetOpts = Opts; 7148 7149 // Set the target CPU if specified. 7150 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 7151 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 7152 return nullptr; 7153 } 7154 7155 // Set the target ABI if specified. 7156 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 7157 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 7158 return nullptr; 7159 } 7160 7161 // Set the fp math unit. 7162 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 7163 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 7164 return nullptr; 7165 } 7166 7167 // Compute the default target features, we need the target to handle this 7168 // because features may have dependencies on one another. 7169 llvm::StringMap<bool> Features; 7170 Target->getDefaultFeatures(Features); 7171 7172 // Apply the user specified deltas. 7173 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 7174 I < N; ++I) { 7175 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 7176 // Apply the feature via the target. 7177 bool Enabled = Name[0] == '+'; 7178 Target->setFeatureEnabled(Features, Name + 1, Enabled); 7179 } 7180 7181 // Add the features to the compile options. 7182 // 7183 // FIXME: If we are completely confident that we have the right set, we only 7184 // need to pass the minuses. 7185 Opts->Features.clear(); 7186 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 7187 ie = Features.end(); it != ie; ++it) 7188 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 7189 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 7190 return nullptr; 7191 7192 return Target.release(); 7193 } 7194