1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringRef.h" 25 #include "llvm/ADT/StringSwitch.h" 26 #include "llvm/ADT/Triple.h" 27 #include "llvm/IR/Type.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include <algorithm> 31 #include <memory> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 77 void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const override { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "6000"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 94 // AddressSanitizer doesn't play well with source fortification, which is on 95 // by default on Darwin. 96 if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0"); 97 98 if (!Opts.ObjCAutoRefCount) { 99 // __weak is always defined, for use in blocks and with objc pointers. 100 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 101 102 // Darwin defines __strong even in C mode (just to nothing). 103 if (Opts.getGC() != LangOptions::NonGC) 104 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 105 else 106 Builder.defineMacro("__strong", ""); 107 108 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 109 // allow this in C, since one might have block pointers in structs that 110 // are used in pure C code and in Objective-C ARC. 111 Builder.defineMacro("__unsafe_unretained", ""); 112 } 113 114 if (Opts.Static) 115 Builder.defineMacro("__STATIC__"); 116 else 117 Builder.defineMacro("__DYNAMIC__"); 118 119 if (Opts.POSIXThreads) 120 Builder.defineMacro("_REENTRANT"); 121 122 // Get the platform type and version number from the triple. 123 unsigned Maj, Min, Rev; 124 if (Triple.isMacOSX()) { 125 Triple.getMacOSXVersion(Maj, Min, Rev); 126 PlatformName = "macosx"; 127 } else { 128 Triple.getOSVersion(Maj, Min, Rev); 129 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 130 } 131 132 // If -target arch-pc-win32-macho option specified, we're 133 // generating code for Win32 ABI. No need to emit 134 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 135 if (PlatformName == "win32") { 136 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 137 return; 138 } 139 140 // Set the appropriate OS version define. 141 if (Triple.isiOS()) { 142 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 143 char Str[6]; 144 Str[0] = '0' + Maj; 145 Str[1] = '0' + (Min / 10); 146 Str[2] = '0' + (Min % 10); 147 Str[3] = '0' + (Rev / 10); 148 Str[4] = '0' + (Rev % 10); 149 Str[5] = '\0'; 150 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 151 Str); 152 } else if (Triple.isMacOSX()) { 153 // Note that the Driver allows versions which aren't representable in the 154 // define (because we only get a single digit for the minor and micro 155 // revision numbers). So, we limit them to the maximum representable 156 // version. 157 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 158 char Str[5]; 159 Str[0] = '0' + (Maj / 10); 160 Str[1] = '0' + (Maj % 10); 161 Str[2] = '0' + std::min(Min, 9U); 162 Str[3] = '0' + std::min(Rev, 9U); 163 Str[4] = '\0'; 164 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 165 } 166 167 // Tell users about the kernel if there is one. 168 if (Triple.isOSDarwin()) 169 Builder.defineMacro("__MACH__"); 170 171 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 172 } 173 174 namespace { 175 template<typename Target> 176 class DarwinTargetInfo : public OSTargetInfo<Target> { 177 protected: 178 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 179 MacroBuilder &Builder) const override { 180 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 181 this->PlatformMinVersion); 182 } 183 184 public: 185 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 186 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 187 this->MCountName = "\01mcount"; 188 } 189 190 std::string isValidSectionSpecifier(StringRef SR) const override { 191 // Let MCSectionMachO validate this. 192 StringRef Segment, Section; 193 unsigned TAA, StubSize; 194 bool HasTAA; 195 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 196 TAA, HasTAA, StubSize); 197 } 198 199 const char *getStaticInitSectionSpecifier() const override { 200 // FIXME: We should return 0 when building kexts. 201 return "__TEXT,__StaticInit,regular,pure_instructions"; 202 } 203 204 /// Darwin does not support protected visibility. Darwin's "default" 205 /// is very similar to ELF's "protected"; Darwin requires a "weak" 206 /// attribute on declarations that can be dynamically replaced. 207 bool hasProtectedVisibility() const override { 208 return false; 209 } 210 }; 211 212 213 // DragonFlyBSD Target 214 template<typename Target> 215 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 216 protected: 217 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 218 MacroBuilder &Builder) const override { 219 // DragonFly defines; list based off of gcc output 220 Builder.defineMacro("__DragonFly__"); 221 Builder.defineMacro("__DragonFly_cc_version", "100001"); 222 Builder.defineMacro("__ELF__"); 223 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 224 Builder.defineMacro("__tune_i386__"); 225 DefineStd(Builder, "unix", Opts); 226 } 227 public: 228 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 229 : OSTargetInfo<Target>(Triple) { 230 this->UserLabelPrefix = ""; 231 232 switch (Triple.getArch()) { 233 default: 234 case llvm::Triple::x86: 235 case llvm::Triple::x86_64: 236 this->MCountName = ".mcount"; 237 break; 238 } 239 } 240 }; 241 242 // FreeBSD Target 243 template<typename Target> 244 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 245 protected: 246 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 247 MacroBuilder &Builder) const override { 248 // FreeBSD defines; list based off of gcc output 249 250 unsigned Release = Triple.getOSMajorVersion(); 251 if (Release == 0U) 252 Release = 8; 253 254 Builder.defineMacro("__FreeBSD__", Twine(Release)); 255 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 256 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 257 DefineStd(Builder, "unix", Opts); 258 Builder.defineMacro("__ELF__"); 259 260 // On FreeBSD, wchar_t contains the number of the code point as 261 // used by the character set of the locale. These character sets are 262 // not necessarily a superset of ASCII. 263 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 264 } 265 public: 266 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 267 this->UserLabelPrefix = ""; 268 269 switch (Triple.getArch()) { 270 default: 271 case llvm::Triple::x86: 272 case llvm::Triple::x86_64: 273 this->MCountName = ".mcount"; 274 break; 275 case llvm::Triple::mips: 276 case llvm::Triple::mipsel: 277 case llvm::Triple::ppc: 278 case llvm::Triple::ppc64: 279 case llvm::Triple::ppc64le: 280 this->MCountName = "_mcount"; 281 break; 282 case llvm::Triple::arm: 283 this->MCountName = "__mcount"; 284 break; 285 } 286 } 287 }; 288 289 // GNU/kFreeBSD Target 290 template<typename Target> 291 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 292 protected: 293 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 294 MacroBuilder &Builder) const override { 295 // GNU/kFreeBSD defines; list based off of gcc output 296 297 DefineStd(Builder, "unix", Opts); 298 Builder.defineMacro("__FreeBSD_kernel__"); 299 Builder.defineMacro("__GLIBC__"); 300 Builder.defineMacro("__ELF__"); 301 if (Opts.POSIXThreads) 302 Builder.defineMacro("_REENTRANT"); 303 if (Opts.CPlusPlus) 304 Builder.defineMacro("_GNU_SOURCE"); 305 } 306 public: 307 KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 308 this->UserLabelPrefix = ""; 309 } 310 }; 311 312 // Minix Target 313 template<typename Target> 314 class MinixTargetInfo : public OSTargetInfo<Target> { 315 protected: 316 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 317 MacroBuilder &Builder) const override { 318 // Minix defines 319 320 Builder.defineMacro("__minix", "3"); 321 Builder.defineMacro("_EM_WSIZE", "4"); 322 Builder.defineMacro("_EM_PSIZE", "4"); 323 Builder.defineMacro("_EM_SSIZE", "2"); 324 Builder.defineMacro("_EM_LSIZE", "4"); 325 Builder.defineMacro("_EM_FSIZE", "4"); 326 Builder.defineMacro("_EM_DSIZE", "8"); 327 Builder.defineMacro("__ELF__"); 328 DefineStd(Builder, "unix", Opts); 329 } 330 public: 331 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 332 this->UserLabelPrefix = ""; 333 } 334 }; 335 336 // Linux target 337 template<typename Target> 338 class LinuxTargetInfo : public OSTargetInfo<Target> { 339 protected: 340 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 341 MacroBuilder &Builder) const override { 342 // Linux defines; list based off of gcc output 343 DefineStd(Builder, "unix", Opts); 344 DefineStd(Builder, "linux", Opts); 345 Builder.defineMacro("__gnu_linux__"); 346 Builder.defineMacro("__ELF__"); 347 if (Triple.getEnvironment() == llvm::Triple::Android) 348 Builder.defineMacro("__ANDROID__", "1"); 349 if (Opts.POSIXThreads) 350 Builder.defineMacro("_REENTRANT"); 351 if (Opts.CPlusPlus) 352 Builder.defineMacro("_GNU_SOURCE"); 353 } 354 public: 355 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 356 this->UserLabelPrefix = ""; 357 this->WIntType = TargetInfo::UnsignedInt; 358 359 switch (Triple.getArch()) { 360 default: 361 break; 362 case llvm::Triple::ppc: 363 case llvm::Triple::ppc64: 364 case llvm::Triple::ppc64le: 365 this->MCountName = "_mcount"; 366 break; 367 } 368 } 369 370 const char *getStaticInitSectionSpecifier() const override { 371 return ".text.startup"; 372 } 373 }; 374 375 // NetBSD Target 376 template<typename Target> 377 class NetBSDTargetInfo : public OSTargetInfo<Target> { 378 protected: 379 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 380 MacroBuilder &Builder) const override { 381 // NetBSD defines; list based off of gcc output 382 Builder.defineMacro("__NetBSD__"); 383 Builder.defineMacro("__unix__"); 384 Builder.defineMacro("__ELF__"); 385 if (Opts.POSIXThreads) 386 Builder.defineMacro("_POSIX_THREADS"); 387 388 switch (Triple.getArch()) { 389 default: 390 break; 391 case llvm::Triple::arm: 392 case llvm::Triple::armeb: 393 case llvm::Triple::thumb: 394 case llvm::Triple::thumbeb: 395 Builder.defineMacro("__ARM_DWARF_EH__"); 396 break; 397 } 398 } 399 public: 400 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 401 this->UserLabelPrefix = ""; 402 } 403 }; 404 405 // OpenBSD Target 406 template<typename Target> 407 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 408 protected: 409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 410 MacroBuilder &Builder) const override { 411 // OpenBSD defines; list based off of gcc output 412 413 Builder.defineMacro("__OpenBSD__"); 414 DefineStd(Builder, "unix", Opts); 415 Builder.defineMacro("__ELF__"); 416 if (Opts.POSIXThreads) 417 Builder.defineMacro("_REENTRANT"); 418 } 419 public: 420 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 421 this->UserLabelPrefix = ""; 422 this->TLSSupported = false; 423 424 switch (Triple.getArch()) { 425 default: 426 case llvm::Triple::x86: 427 case llvm::Triple::x86_64: 428 case llvm::Triple::arm: 429 case llvm::Triple::sparc: 430 this->MCountName = "__mcount"; 431 break; 432 case llvm::Triple::mips64: 433 case llvm::Triple::mips64el: 434 case llvm::Triple::ppc: 435 case llvm::Triple::sparcv9: 436 this->MCountName = "_mcount"; 437 break; 438 } 439 } 440 }; 441 442 // Bitrig Target 443 template<typename Target> 444 class BitrigTargetInfo : public OSTargetInfo<Target> { 445 protected: 446 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 447 MacroBuilder &Builder) const override { 448 // Bitrig defines; list based off of gcc output 449 450 Builder.defineMacro("__Bitrig__"); 451 DefineStd(Builder, "unix", Opts); 452 Builder.defineMacro("__ELF__"); 453 if (Opts.POSIXThreads) 454 Builder.defineMacro("_REENTRANT"); 455 } 456 public: 457 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 458 this->UserLabelPrefix = ""; 459 this->MCountName = "__mcount"; 460 } 461 }; 462 463 // PSP Target 464 template<typename Target> 465 class PSPTargetInfo : public OSTargetInfo<Target> { 466 protected: 467 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 468 MacroBuilder &Builder) const override { 469 // PSP defines; list based on the output of the pspdev gcc toolchain. 470 Builder.defineMacro("PSP"); 471 Builder.defineMacro("_PSP"); 472 Builder.defineMacro("__psp__"); 473 Builder.defineMacro("__ELF__"); 474 } 475 public: 476 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 477 this->UserLabelPrefix = ""; 478 } 479 }; 480 481 // PS3 PPU Target 482 template<typename Target> 483 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 484 protected: 485 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 486 MacroBuilder &Builder) const override { 487 // PS3 PPU defines. 488 Builder.defineMacro("__PPC__"); 489 Builder.defineMacro("__PPU__"); 490 Builder.defineMacro("__CELLOS_LV2__"); 491 Builder.defineMacro("__ELF__"); 492 Builder.defineMacro("__LP32__"); 493 Builder.defineMacro("_ARCH_PPC64"); 494 Builder.defineMacro("__powerpc64__"); 495 } 496 public: 497 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 498 this->UserLabelPrefix = ""; 499 this->LongWidth = this->LongAlign = 32; 500 this->PointerWidth = this->PointerAlign = 32; 501 this->IntMaxType = TargetInfo::SignedLongLong; 502 this->UIntMaxType = TargetInfo::UnsignedLongLong; 503 this->Int64Type = TargetInfo::SignedLongLong; 504 this->SizeType = TargetInfo::UnsignedInt; 505 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64"; 506 } 507 }; 508 509 // AuroraUX target 510 template<typename Target> 511 class AuroraUXTargetInfo : public OSTargetInfo<Target> { 512 protected: 513 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 514 MacroBuilder &Builder) const override { 515 DefineStd(Builder, "sun", Opts); 516 DefineStd(Builder, "unix", Opts); 517 Builder.defineMacro("__ELF__"); 518 Builder.defineMacro("__svr4__"); 519 Builder.defineMacro("__SVR4"); 520 } 521 public: 522 AuroraUXTargetInfo(const llvm::Triple &Triple) 523 : OSTargetInfo<Target>(Triple) { 524 this->UserLabelPrefix = ""; 525 this->WCharType = this->SignedLong; 526 // FIXME: WIntType should be SignedLong 527 } 528 }; 529 530 // Solaris target 531 template<typename Target> 532 class SolarisTargetInfo : public OSTargetInfo<Target> { 533 protected: 534 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 535 MacroBuilder &Builder) const override { 536 DefineStd(Builder, "sun", Opts); 537 DefineStd(Builder, "unix", Opts); 538 Builder.defineMacro("__ELF__"); 539 Builder.defineMacro("__svr4__"); 540 Builder.defineMacro("__SVR4"); 541 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 542 // newer, but to 500 for everything else. feature_test.h has a check to 543 // ensure that you are not using C99 with an old version of X/Open or C89 544 // with a new version. 545 if (Opts.C99 || Opts.C11) 546 Builder.defineMacro("_XOPEN_SOURCE", "600"); 547 else 548 Builder.defineMacro("_XOPEN_SOURCE", "500"); 549 if (Opts.CPlusPlus) 550 Builder.defineMacro("__C99FEATURES__"); 551 Builder.defineMacro("_LARGEFILE_SOURCE"); 552 Builder.defineMacro("_LARGEFILE64_SOURCE"); 553 Builder.defineMacro("__EXTENSIONS__"); 554 Builder.defineMacro("_REENTRANT"); 555 } 556 public: 557 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 558 this->UserLabelPrefix = ""; 559 this->WCharType = this->SignedInt; 560 // FIXME: WIntType should be SignedLong 561 } 562 }; 563 564 // Windows target 565 template<typename Target> 566 class WindowsTargetInfo : public OSTargetInfo<Target> { 567 protected: 568 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 569 MacroBuilder &Builder) const override { 570 Builder.defineMacro("_WIN32"); 571 } 572 void getVisualStudioDefines(const LangOptions &Opts, 573 MacroBuilder &Builder) const { 574 if (Opts.CPlusPlus) { 575 if (Opts.RTTI) 576 Builder.defineMacro("_CPPRTTI"); 577 578 if (Opts.Exceptions) 579 Builder.defineMacro("_CPPUNWIND"); 580 } 581 582 if (!Opts.CharIsSigned) 583 Builder.defineMacro("_CHAR_UNSIGNED"); 584 585 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 586 // but it works for now. 587 if (Opts.POSIXThreads) 588 Builder.defineMacro("_MT"); 589 590 if (Opts.MSCVersion != 0) 591 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion)); 592 593 if (Opts.MicrosoftExt) { 594 Builder.defineMacro("_MSC_EXTENSIONS"); 595 596 if (Opts.CPlusPlus11) { 597 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 598 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 599 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 600 } 601 } 602 603 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 604 } 605 606 public: 607 WindowsTargetInfo(const llvm::Triple &Triple) 608 : OSTargetInfo<Target>(Triple) {} 609 }; 610 611 template <typename Target> 612 class NaClTargetInfo : public OSTargetInfo<Target> { 613 protected: 614 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 615 MacroBuilder &Builder) const override { 616 if (Opts.POSIXThreads) 617 Builder.defineMacro("_REENTRANT"); 618 if (Opts.CPlusPlus) 619 Builder.defineMacro("_GNU_SOURCE"); 620 621 DefineStd(Builder, "unix", Opts); 622 Builder.defineMacro("__ELF__"); 623 Builder.defineMacro("__native_client__"); 624 } 625 626 public: 627 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 628 this->UserLabelPrefix = ""; 629 this->LongAlign = 32; 630 this->LongWidth = 32; 631 this->PointerAlign = 32; 632 this->PointerWidth = 32; 633 this->IntMaxType = TargetInfo::SignedLongLong; 634 this->UIntMaxType = TargetInfo::UnsignedLongLong; 635 this->Int64Type = TargetInfo::SignedLongLong; 636 this->DoubleAlign = 64; 637 this->LongDoubleWidth = 64; 638 this->LongDoubleAlign = 64; 639 this->LongLongWidth = 64; 640 this->LongLongAlign = 64; 641 this->SizeType = TargetInfo::UnsignedInt; 642 this->PtrDiffType = TargetInfo::SignedInt; 643 this->IntPtrType = TargetInfo::SignedInt; 644 // RegParmMax is inherited from the underlying architecture 645 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 646 if (Triple.getArch() == llvm::Triple::arm) { 647 this->DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S128"; 648 } else if (Triple.getArch() == llvm::Triple::x86) { 649 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 650 } else if (Triple.getArch() == llvm::Triple::x86_64) { 651 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 652 } else if (Triple.getArch() == llvm::Triple::mipsel) { 653 // Handled on mips' setDescriptionString. 654 } else { 655 assert(Triple.getArch() == llvm::Triple::le32); 656 this->DescriptionString = "e-p:32:32-i64:64"; 657 } 658 } 659 typename Target::CallingConvCheckResult checkCallingConvention( 660 CallingConv CC) const override { 661 return CC == CC_PnaclCall ? Target::CCCR_OK : 662 Target::checkCallingConvention(CC); 663 } 664 }; 665 } // end anonymous namespace. 666 667 //===----------------------------------------------------------------------===// 668 // Specific target implementations. 669 //===----------------------------------------------------------------------===// 670 671 namespace { 672 // PPC abstract base class 673 class PPCTargetInfo : public TargetInfo { 674 static const Builtin::Info BuiltinInfo[]; 675 static const char * const GCCRegNames[]; 676 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 677 std::string CPU; 678 679 // Target cpu features. 680 bool HasVSX; 681 682 public: 683 PPCTargetInfo(const llvm::Triple &Triple) 684 : TargetInfo(Triple), HasVSX(false) { 685 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 686 LongDoubleWidth = LongDoubleAlign = 128; 687 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 688 } 689 690 /// \brief Flags for architecture specific defines. 691 typedef enum { 692 ArchDefineNone = 0, 693 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 694 ArchDefinePpcgr = 1 << 1, 695 ArchDefinePpcsq = 1 << 2, 696 ArchDefine440 = 1 << 3, 697 ArchDefine603 = 1 << 4, 698 ArchDefine604 = 1 << 5, 699 ArchDefinePwr4 = 1 << 6, 700 ArchDefinePwr5 = 1 << 7, 701 ArchDefinePwr5x = 1 << 8, 702 ArchDefinePwr6 = 1 << 9, 703 ArchDefinePwr6x = 1 << 10, 704 ArchDefinePwr7 = 1 << 11, 705 ArchDefineA2 = 1 << 12, 706 ArchDefineA2q = 1 << 13 707 } ArchDefineTypes; 708 709 // Note: GCC recognizes the following additional cpus: 710 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 711 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 712 // titan, rs64. 713 bool setCPU(const std::string &Name) override { 714 bool CPUKnown = llvm::StringSwitch<bool>(Name) 715 .Case("generic", true) 716 .Case("440", true) 717 .Case("450", true) 718 .Case("601", true) 719 .Case("602", true) 720 .Case("603", true) 721 .Case("603e", true) 722 .Case("603ev", true) 723 .Case("604", true) 724 .Case("604e", true) 725 .Case("620", true) 726 .Case("630", true) 727 .Case("g3", true) 728 .Case("7400", true) 729 .Case("g4", true) 730 .Case("7450", true) 731 .Case("g4+", true) 732 .Case("750", true) 733 .Case("970", true) 734 .Case("g5", true) 735 .Case("a2", true) 736 .Case("a2q", true) 737 .Case("e500mc", true) 738 .Case("e5500", true) 739 .Case("power3", true) 740 .Case("pwr3", true) 741 .Case("power4", true) 742 .Case("pwr4", true) 743 .Case("power5", true) 744 .Case("pwr5", true) 745 .Case("power5x", true) 746 .Case("pwr5x", true) 747 .Case("power6", true) 748 .Case("pwr6", true) 749 .Case("power6x", true) 750 .Case("pwr6x", true) 751 .Case("power7", true) 752 .Case("pwr7", true) 753 .Case("powerpc", true) 754 .Case("ppc", true) 755 .Case("powerpc64", true) 756 .Case("ppc64", true) 757 .Case("powerpc64le", true) 758 .Case("ppc64le", true) 759 .Default(false); 760 761 if (CPUKnown) 762 CPU = Name; 763 764 return CPUKnown; 765 } 766 767 void getTargetBuiltins(const Builtin::Info *&Records, 768 unsigned &NumRecords) const override { 769 Records = BuiltinInfo; 770 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 771 } 772 773 bool isCLZForZeroUndef() const override { return false; } 774 775 void getTargetDefines(const LangOptions &Opts, 776 MacroBuilder &Builder) const override; 777 778 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 779 780 bool handleTargetFeatures(std::vector<std::string> &Features, 781 DiagnosticsEngine &Diags) override; 782 bool hasFeature(StringRef Feature) const override; 783 784 void getGCCRegNames(const char * const *&Names, 785 unsigned &NumNames) const override; 786 void getGCCRegAliases(const GCCRegAlias *&Aliases, 787 unsigned &NumAliases) const override; 788 bool validateAsmConstraint(const char *&Name, 789 TargetInfo::ConstraintInfo &Info) const override { 790 switch (*Name) { 791 default: return false; 792 case 'O': // Zero 793 break; 794 case 'b': // Base register 795 case 'f': // Floating point register 796 Info.setAllowsRegister(); 797 break; 798 // FIXME: The following are added to allow parsing. 799 // I just took a guess at what the actions should be. 800 // Also, is more specific checking needed? I.e. specific registers? 801 case 'd': // Floating point register (containing 64-bit value) 802 case 'v': // Altivec vector register 803 Info.setAllowsRegister(); 804 break; 805 case 'w': 806 switch (Name[1]) { 807 case 'd':// VSX vector register to hold vector double data 808 case 'f':// VSX vector register to hold vector float data 809 case 's':// VSX vector register to hold scalar float data 810 case 'a':// Any VSX register 811 case 'c':// An individual CR bit 812 break; 813 default: 814 return false; 815 } 816 Info.setAllowsRegister(); 817 Name++; // Skip over 'w'. 818 break; 819 case 'h': // `MQ', `CTR', or `LINK' register 820 case 'q': // `MQ' register 821 case 'c': // `CTR' register 822 case 'l': // `LINK' register 823 case 'x': // `CR' register (condition register) number 0 824 case 'y': // `CR' register (condition register) 825 case 'z': // `XER[CA]' carry bit (part of the XER register) 826 Info.setAllowsRegister(); 827 break; 828 case 'I': // Signed 16-bit constant 829 case 'J': // Unsigned 16-bit constant shifted left 16 bits 830 // (use `L' instead for SImode constants) 831 case 'K': // Unsigned 16-bit constant 832 case 'L': // Signed 16-bit constant shifted left 16 bits 833 case 'M': // Constant larger than 31 834 case 'N': // Exact power of 2 835 case 'P': // Constant whose negation is a signed 16-bit constant 836 case 'G': // Floating point constant that can be loaded into a 837 // register with one instruction per word 838 case 'H': // Integer/Floating point constant that can be loaded 839 // into a register using three instructions 840 break; 841 case 'm': // Memory operand. Note that on PowerPC targets, m can 842 // include addresses that update the base register. It 843 // is therefore only safe to use `m' in an asm statement 844 // if that asm statement accesses the operand exactly once. 845 // The asm statement must also use `%U<opno>' as a 846 // placeholder for the "update" flag in the corresponding 847 // load or store instruction. For example: 848 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 849 // is correct but: 850 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 851 // is not. Use es rather than m if you don't want the base 852 // register to be updated. 853 case 'e': 854 if (Name[1] != 's') 855 return false; 856 // es: A "stable" memory operand; that is, one which does not 857 // include any automodification of the base register. Unlike 858 // `m', this constraint can be used in asm statements that 859 // might access the operand several times, or that might not 860 // access it at all. 861 Info.setAllowsMemory(); 862 Name++; // Skip over 'e'. 863 break; 864 case 'Q': // Memory operand that is an offset from a register (it is 865 // usually better to use `m' or `es' in asm statements) 866 case 'Z': // Memory operand that is an indexed or indirect from a 867 // register (it is usually better to use `m' or `es' in 868 // asm statements) 869 Info.setAllowsMemory(); 870 Info.setAllowsRegister(); 871 break; 872 case 'R': // AIX TOC entry 873 case 'a': // Address operand that is an indexed or indirect from a 874 // register (`p' is preferable for asm statements) 875 case 'S': // Constant suitable as a 64-bit mask operand 876 case 'T': // Constant suitable as a 32-bit mask operand 877 case 'U': // System V Release 4 small data area reference 878 case 't': // AND masks that can be performed by two rldic{l, r} 879 // instructions 880 case 'W': // Vector constant that does not require memory 881 case 'j': // Vector constant that is all zeros. 882 break; 883 // End FIXME. 884 } 885 return true; 886 } 887 std::string convertConstraint(const char *&Constraint) const override { 888 std::string R; 889 switch (*Constraint) { 890 case 'e': 891 case 'w': 892 // Two-character constraint; add "^" hint for later parsing. 893 R = std::string("^") + std::string(Constraint, 2); 894 Constraint++; 895 break; 896 default: 897 return TargetInfo::convertConstraint(Constraint); 898 } 899 return R; 900 } 901 const char *getClobbers() const override { 902 return ""; 903 } 904 int getEHDataRegisterNumber(unsigned RegNo) const override { 905 if (RegNo == 0) return 3; 906 if (RegNo == 1) return 4; 907 return -1; 908 } 909 }; 910 911 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 912 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 913 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 914 ALL_LANGUAGES }, 915 #include "clang/Basic/BuiltinsPPC.def" 916 }; 917 918 /// handleTargetFeatures - Perform initialization based on the user 919 /// configured set of features. 920 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 921 DiagnosticsEngine &Diags) { 922 // Remember the maximum enabled sselevel. 923 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 924 // Ignore disabled features. 925 if (Features[i][0] == '-') 926 continue; 927 928 StringRef Feature = StringRef(Features[i]).substr(1); 929 930 if (Feature == "vsx") { 931 HasVSX = true; 932 continue; 933 } 934 935 // TODO: Finish this list and add an assert that we've handled them 936 // all. 937 } 938 939 return true; 940 } 941 942 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 943 /// #defines that are not tied to a specific subtarget. 944 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 945 MacroBuilder &Builder) const { 946 // Target identification. 947 Builder.defineMacro("__ppc__"); 948 Builder.defineMacro("__PPC__"); 949 Builder.defineMacro("_ARCH_PPC"); 950 Builder.defineMacro("__powerpc__"); 951 Builder.defineMacro("__POWERPC__"); 952 if (PointerWidth == 64) { 953 Builder.defineMacro("_ARCH_PPC64"); 954 Builder.defineMacro("__powerpc64__"); 955 Builder.defineMacro("__ppc64__"); 956 Builder.defineMacro("__PPC64__"); 957 } 958 959 // Target properties. 960 if (getTriple().getArch() == llvm::Triple::ppc64le) { 961 Builder.defineMacro("_LITTLE_ENDIAN"); 962 Builder.defineMacro("_CALL_ELF","2"); 963 } else { 964 if (getTriple().getOS() != llvm::Triple::NetBSD && 965 getTriple().getOS() != llvm::Triple::OpenBSD) 966 Builder.defineMacro("_BIG_ENDIAN"); 967 } 968 969 // Subtarget options. 970 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 971 Builder.defineMacro("__REGISTER_PREFIX__", ""); 972 973 // FIXME: Should be controlled by command line option. 974 if (LongDoubleWidth == 128) 975 Builder.defineMacro("__LONG_DOUBLE_128__"); 976 977 if (Opts.AltiVec) { 978 Builder.defineMacro("__VEC__", "10206"); 979 Builder.defineMacro("__ALTIVEC__"); 980 } 981 982 // CPU identification. 983 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 984 .Case("440", ArchDefineName) 985 .Case("450", ArchDefineName | ArchDefine440) 986 .Case("601", ArchDefineName) 987 .Case("602", ArchDefineName | ArchDefinePpcgr) 988 .Case("603", ArchDefineName | ArchDefinePpcgr) 989 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 990 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 991 .Case("604", ArchDefineName | ArchDefinePpcgr) 992 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 993 .Case("620", ArchDefineName | ArchDefinePpcgr) 994 .Case("630", ArchDefineName | ArchDefinePpcgr) 995 .Case("7400", ArchDefineName | ArchDefinePpcgr) 996 .Case("7450", ArchDefineName | ArchDefinePpcgr) 997 .Case("750", ArchDefineName | ArchDefinePpcgr) 998 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 999 | ArchDefinePpcsq) 1000 .Case("a2", ArchDefineA2) 1001 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1002 .Case("pwr3", ArchDefinePpcgr) 1003 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1004 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1005 | ArchDefinePpcsq) 1006 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1007 | ArchDefinePpcgr | ArchDefinePpcsq) 1008 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1009 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1010 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1011 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1012 | ArchDefinePpcsq) 1013 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1014 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1015 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 1016 .Case("power3", ArchDefinePpcgr) 1017 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1018 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1019 | ArchDefinePpcsq) 1020 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1021 | ArchDefinePpcgr | ArchDefinePpcsq) 1022 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1023 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1024 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1025 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1026 | ArchDefinePpcsq) 1027 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1028 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1029 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 1030 .Default(ArchDefineNone); 1031 1032 if (defs & ArchDefineName) 1033 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1034 if (defs & ArchDefinePpcgr) 1035 Builder.defineMacro("_ARCH_PPCGR"); 1036 if (defs & ArchDefinePpcsq) 1037 Builder.defineMacro("_ARCH_PPCSQ"); 1038 if (defs & ArchDefine440) 1039 Builder.defineMacro("_ARCH_440"); 1040 if (defs & ArchDefine603) 1041 Builder.defineMacro("_ARCH_603"); 1042 if (defs & ArchDefine604) 1043 Builder.defineMacro("_ARCH_604"); 1044 if (defs & ArchDefinePwr4) 1045 Builder.defineMacro("_ARCH_PWR4"); 1046 if (defs & ArchDefinePwr5) 1047 Builder.defineMacro("_ARCH_PWR5"); 1048 if (defs & ArchDefinePwr5x) 1049 Builder.defineMacro("_ARCH_PWR5X"); 1050 if (defs & ArchDefinePwr6) 1051 Builder.defineMacro("_ARCH_PWR6"); 1052 if (defs & ArchDefinePwr6x) 1053 Builder.defineMacro("_ARCH_PWR6X"); 1054 if (defs & ArchDefinePwr7) 1055 Builder.defineMacro("_ARCH_PWR7"); 1056 if (defs & ArchDefineA2) 1057 Builder.defineMacro("_ARCH_A2"); 1058 if (defs & ArchDefineA2q) { 1059 Builder.defineMacro("_ARCH_A2Q"); 1060 Builder.defineMacro("_ARCH_QP"); 1061 } 1062 1063 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1064 Builder.defineMacro("__bg__"); 1065 Builder.defineMacro("__THW_BLUEGENE__"); 1066 Builder.defineMacro("__bgq__"); 1067 Builder.defineMacro("__TOS_BGQ__"); 1068 } 1069 1070 if (HasVSX) 1071 Builder.defineMacro("__VSX__"); 1072 1073 // FIXME: The following are not yet generated here by Clang, but are 1074 // generated by GCC: 1075 // 1076 // _SOFT_FLOAT_ 1077 // __RECIP_PRECISION__ 1078 // __APPLE_ALTIVEC__ 1079 // __RECIP__ 1080 // __RECIPF__ 1081 // __RSQRTE__ 1082 // __RSQRTEF__ 1083 // _SOFT_DOUBLE_ 1084 // __NO_LWSYNC__ 1085 // __HAVE_BSWAP__ 1086 // __LONGDOUBLE128 1087 // __CMODEL_MEDIUM__ 1088 // __CMODEL_LARGE__ 1089 // _CALL_SYSV 1090 // _CALL_DARWIN 1091 // __NO_FPRS__ 1092 } 1093 1094 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1095 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1096 .Case("7400", true) 1097 .Case("g4", true) 1098 .Case("7450", true) 1099 .Case("g4+", true) 1100 .Case("970", true) 1101 .Case("g5", true) 1102 .Case("pwr6", true) 1103 .Case("pwr7", true) 1104 .Case("ppc64", true) 1105 .Case("ppc64le", true) 1106 .Default(false); 1107 1108 Features["qpx"] = (CPU == "a2q"); 1109 } 1110 1111 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1112 return Feature == "powerpc"; 1113 } 1114 1115 1116 const char * const PPCTargetInfo::GCCRegNames[] = { 1117 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1118 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1119 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1120 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1121 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1122 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1123 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1124 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1125 "mq", "lr", "ctr", "ap", 1126 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1127 "xer", 1128 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1129 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1130 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1131 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1132 "vrsave", "vscr", 1133 "spe_acc", "spefscr", 1134 "sfp" 1135 }; 1136 1137 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1138 unsigned &NumNames) const { 1139 Names = GCCRegNames; 1140 NumNames = llvm::array_lengthof(GCCRegNames); 1141 } 1142 1143 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1144 // While some of these aliases do map to different registers 1145 // they still share the same register name. 1146 { { "0" }, "r0" }, 1147 { { "1"}, "r1" }, 1148 { { "2" }, "r2" }, 1149 { { "3" }, "r3" }, 1150 { { "4" }, "r4" }, 1151 { { "5" }, "r5" }, 1152 { { "6" }, "r6" }, 1153 { { "7" }, "r7" }, 1154 { { "8" }, "r8" }, 1155 { { "9" }, "r9" }, 1156 { { "10" }, "r10" }, 1157 { { "11" }, "r11" }, 1158 { { "12" }, "r12" }, 1159 { { "13" }, "r13" }, 1160 { { "14" }, "r14" }, 1161 { { "15" }, "r15" }, 1162 { { "16" }, "r16" }, 1163 { { "17" }, "r17" }, 1164 { { "18" }, "r18" }, 1165 { { "19" }, "r19" }, 1166 { { "20" }, "r20" }, 1167 { { "21" }, "r21" }, 1168 { { "22" }, "r22" }, 1169 { { "23" }, "r23" }, 1170 { { "24" }, "r24" }, 1171 { { "25" }, "r25" }, 1172 { { "26" }, "r26" }, 1173 { { "27" }, "r27" }, 1174 { { "28" }, "r28" }, 1175 { { "29" }, "r29" }, 1176 { { "30" }, "r30" }, 1177 { { "31" }, "r31" }, 1178 { { "fr0" }, "f0" }, 1179 { { "fr1" }, "f1" }, 1180 { { "fr2" }, "f2" }, 1181 { { "fr3" }, "f3" }, 1182 { { "fr4" }, "f4" }, 1183 { { "fr5" }, "f5" }, 1184 { { "fr6" }, "f6" }, 1185 { { "fr7" }, "f7" }, 1186 { { "fr8" }, "f8" }, 1187 { { "fr9" }, "f9" }, 1188 { { "fr10" }, "f10" }, 1189 { { "fr11" }, "f11" }, 1190 { { "fr12" }, "f12" }, 1191 { { "fr13" }, "f13" }, 1192 { { "fr14" }, "f14" }, 1193 { { "fr15" }, "f15" }, 1194 { { "fr16" }, "f16" }, 1195 { { "fr17" }, "f17" }, 1196 { { "fr18" }, "f18" }, 1197 { { "fr19" }, "f19" }, 1198 { { "fr20" }, "f20" }, 1199 { { "fr21" }, "f21" }, 1200 { { "fr22" }, "f22" }, 1201 { { "fr23" }, "f23" }, 1202 { { "fr24" }, "f24" }, 1203 { { "fr25" }, "f25" }, 1204 { { "fr26" }, "f26" }, 1205 { { "fr27" }, "f27" }, 1206 { { "fr28" }, "f28" }, 1207 { { "fr29" }, "f29" }, 1208 { { "fr30" }, "f30" }, 1209 { { "fr31" }, "f31" }, 1210 { { "cc" }, "cr0" }, 1211 }; 1212 1213 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1214 unsigned &NumAliases) const { 1215 Aliases = GCCRegAliases; 1216 NumAliases = llvm::array_lengthof(GCCRegAliases); 1217 } 1218 } // end anonymous namespace. 1219 1220 namespace { 1221 class PPC32TargetInfo : public PPCTargetInfo { 1222 public: 1223 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1224 DescriptionString = "E-m:e-p:32:32-i64:64-n32"; 1225 1226 switch (getTriple().getOS()) { 1227 case llvm::Triple::Linux: 1228 case llvm::Triple::FreeBSD: 1229 case llvm::Triple::NetBSD: 1230 SizeType = UnsignedInt; 1231 PtrDiffType = SignedInt; 1232 IntPtrType = SignedInt; 1233 break; 1234 default: 1235 break; 1236 } 1237 1238 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1239 LongDoubleWidth = LongDoubleAlign = 64; 1240 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1241 } 1242 1243 // PPC32 supports atomics up to 4 bytes. 1244 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1245 } 1246 1247 BuiltinVaListKind getBuiltinVaListKind() const override { 1248 // This is the ELF definition, and is overridden by the Darwin sub-target 1249 return TargetInfo::PowerABIBuiltinVaList; 1250 } 1251 }; 1252 } // end anonymous namespace. 1253 1254 // Note: ABI differences may eventually require us to have a separate 1255 // TargetInfo for little endian. 1256 namespace { 1257 class PPC64TargetInfo : public PPCTargetInfo { 1258 public: 1259 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1260 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1261 IntMaxType = SignedLong; 1262 UIntMaxType = UnsignedLong; 1263 Int64Type = SignedLong; 1264 1265 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1266 LongDoubleWidth = LongDoubleAlign = 64; 1267 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1268 DescriptionString = "E-m:e-i64:64-n32:64"; 1269 } else { 1270 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1271 DescriptionString = "e-m:e-i64:64-n32:64"; 1272 } else { 1273 DescriptionString = "E-m:e-i64:64-n32:64"; 1274 } 1275 } 1276 1277 // PPC64 supports atomics up to 8 bytes. 1278 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1279 } 1280 BuiltinVaListKind getBuiltinVaListKind() const override { 1281 return TargetInfo::CharPtrBuiltinVaList; 1282 } 1283 }; 1284 } // end anonymous namespace. 1285 1286 1287 namespace { 1288 class DarwinPPC32TargetInfo : 1289 public DarwinTargetInfo<PPC32TargetInfo> { 1290 public: 1291 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1292 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1293 HasAlignMac68kSupport = true; 1294 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1295 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1296 LongLongAlign = 32; 1297 SuitableAlign = 128; 1298 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; 1299 } 1300 BuiltinVaListKind getBuiltinVaListKind() const override { 1301 return TargetInfo::CharPtrBuiltinVaList; 1302 } 1303 }; 1304 1305 class DarwinPPC64TargetInfo : 1306 public DarwinTargetInfo<PPC64TargetInfo> { 1307 public: 1308 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1309 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1310 HasAlignMac68kSupport = true; 1311 SuitableAlign = 128; 1312 DescriptionString = "E-m:o-i64:64-n32:64"; 1313 } 1314 }; 1315 } // end anonymous namespace. 1316 1317 namespace { 1318 static const unsigned NVPTXAddrSpaceMap[] = { 1319 1, // opencl_global 1320 3, // opencl_local 1321 4, // opencl_constant 1322 1, // cuda_device 1323 4, // cuda_constant 1324 3, // cuda_shared 1325 }; 1326 class NVPTXTargetInfo : public TargetInfo { 1327 static const char * const GCCRegNames[]; 1328 static const Builtin::Info BuiltinInfo[]; 1329 public: 1330 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1331 BigEndian = false; 1332 TLSSupported = false; 1333 LongWidth = LongAlign = 64; 1334 AddrSpaceMap = &NVPTXAddrSpaceMap; 1335 UseAddrSpaceMapMangling = true; 1336 // Define available target features 1337 // These must be defined in sorted order! 1338 NoAsmVariants = true; 1339 } 1340 void getTargetDefines(const LangOptions &Opts, 1341 MacroBuilder &Builder) const override { 1342 Builder.defineMacro("__PTX__"); 1343 Builder.defineMacro("__NVPTX__"); 1344 } 1345 void getTargetBuiltins(const Builtin::Info *&Records, 1346 unsigned &NumRecords) const override { 1347 Records = BuiltinInfo; 1348 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1349 } 1350 bool hasFeature(StringRef Feature) const override { 1351 return Feature == "ptx" || Feature == "nvptx"; 1352 } 1353 1354 void getGCCRegNames(const char * const *&Names, 1355 unsigned &NumNames) const override; 1356 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1357 unsigned &NumAliases) const override { 1358 // No aliases. 1359 Aliases = nullptr; 1360 NumAliases = 0; 1361 } 1362 bool validateAsmConstraint(const char *&Name, 1363 TargetInfo::ConstraintInfo &Info) const override { 1364 switch (*Name) { 1365 default: return false; 1366 case 'c': 1367 case 'h': 1368 case 'r': 1369 case 'l': 1370 case 'f': 1371 case 'd': 1372 Info.setAllowsRegister(); 1373 return true; 1374 } 1375 } 1376 const char *getClobbers() const override { 1377 // FIXME: Is this really right? 1378 return ""; 1379 } 1380 BuiltinVaListKind getBuiltinVaListKind() const override { 1381 // FIXME: implement 1382 return TargetInfo::CharPtrBuiltinVaList; 1383 } 1384 bool setCPU(const std::string &Name) override { 1385 bool Valid = llvm::StringSwitch<bool>(Name) 1386 .Case("sm_20", true) 1387 .Case("sm_21", true) 1388 .Case("sm_30", true) 1389 .Case("sm_35", true) 1390 .Default(false); 1391 1392 return Valid; 1393 } 1394 }; 1395 1396 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1397 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1398 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1399 ALL_LANGUAGES }, 1400 #include "clang/Basic/BuiltinsNVPTX.def" 1401 }; 1402 1403 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1404 "r0" 1405 }; 1406 1407 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1408 unsigned &NumNames) const { 1409 Names = GCCRegNames; 1410 NumNames = llvm::array_lengthof(GCCRegNames); 1411 } 1412 1413 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1414 public: 1415 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1416 PointerWidth = PointerAlign = 32; 1417 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt; 1418 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1419 } 1420 }; 1421 1422 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1423 public: 1424 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1425 PointerWidth = PointerAlign = 64; 1426 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong; 1427 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1428 } 1429 }; 1430 } 1431 1432 namespace { 1433 1434 static const unsigned R600AddrSpaceMap[] = { 1435 1, // opencl_global 1436 3, // opencl_local 1437 2, // opencl_constant 1438 1, // cuda_device 1439 2, // cuda_constant 1440 3 // cuda_shared 1441 }; 1442 1443 static const char *DescriptionStringR600 = 1444 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1445 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1446 1447 static const char *DescriptionStringR600DoubleOps = 1448 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1449 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1450 1451 static const char *DescriptionStringSI = 1452 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1453 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1454 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1455 1456 class R600TargetInfo : public TargetInfo { 1457 /// \brief The GPU profiles supported by the R600 target. 1458 enum GPUKind { 1459 GK_NONE, 1460 GK_R600, 1461 GK_R600_DOUBLE_OPS, 1462 GK_R700, 1463 GK_R700_DOUBLE_OPS, 1464 GK_EVERGREEN, 1465 GK_EVERGREEN_DOUBLE_OPS, 1466 GK_NORTHERN_ISLANDS, 1467 GK_CAYMAN, 1468 GK_SOUTHERN_ISLANDS, 1469 GK_SEA_ISLANDS 1470 } GPU; 1471 1472 public: 1473 R600TargetInfo(const llvm::Triple &Triple) 1474 : TargetInfo(Triple), GPU(GK_R600) { 1475 DescriptionString = DescriptionStringR600; 1476 AddrSpaceMap = &R600AddrSpaceMap; 1477 UseAddrSpaceMapMangling = true; 1478 } 1479 1480 const char * getClobbers() const override { 1481 return ""; 1482 } 1483 1484 void getGCCRegNames(const char * const *&Names, 1485 unsigned &numNames) const override { 1486 Names = nullptr; 1487 numNames = 0; 1488 } 1489 1490 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1491 unsigned &NumAliases) const override { 1492 Aliases = nullptr; 1493 NumAliases = 0; 1494 } 1495 1496 bool validateAsmConstraint(const char *&Name, 1497 TargetInfo::ConstraintInfo &info) const override { 1498 return true; 1499 } 1500 1501 void getTargetBuiltins(const Builtin::Info *&Records, 1502 unsigned &NumRecords) const override { 1503 Records = nullptr; 1504 NumRecords = 0; 1505 } 1506 1507 1508 void getTargetDefines(const LangOptions &Opts, 1509 MacroBuilder &Builder) const override { 1510 Builder.defineMacro("__R600__"); 1511 } 1512 1513 BuiltinVaListKind getBuiltinVaListKind() const override { 1514 return TargetInfo::CharPtrBuiltinVaList; 1515 } 1516 1517 bool setCPU(const std::string &Name) override { 1518 GPU = llvm::StringSwitch<GPUKind>(Name) 1519 .Case("r600" , GK_R600) 1520 .Case("rv610", GK_R600) 1521 .Case("rv620", GK_R600) 1522 .Case("rv630", GK_R600) 1523 .Case("rv635", GK_R600) 1524 .Case("rs780", GK_R600) 1525 .Case("rs880", GK_R600) 1526 .Case("rv670", GK_R600_DOUBLE_OPS) 1527 .Case("rv710", GK_R700) 1528 .Case("rv730", GK_R700) 1529 .Case("rv740", GK_R700_DOUBLE_OPS) 1530 .Case("rv770", GK_R700_DOUBLE_OPS) 1531 .Case("palm", GK_EVERGREEN) 1532 .Case("cedar", GK_EVERGREEN) 1533 .Case("sumo", GK_EVERGREEN) 1534 .Case("sumo2", GK_EVERGREEN) 1535 .Case("redwood", GK_EVERGREEN) 1536 .Case("juniper", GK_EVERGREEN) 1537 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1538 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1539 .Case("barts", GK_NORTHERN_ISLANDS) 1540 .Case("turks", GK_NORTHERN_ISLANDS) 1541 .Case("caicos", GK_NORTHERN_ISLANDS) 1542 .Case("cayman", GK_CAYMAN) 1543 .Case("aruba", GK_CAYMAN) 1544 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1545 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1546 .Case("verde", GK_SOUTHERN_ISLANDS) 1547 .Case("oland", GK_SOUTHERN_ISLANDS) 1548 .Case("bonaire", GK_SEA_ISLANDS) 1549 .Case("kabini", GK_SEA_ISLANDS) 1550 .Case("kaveri", GK_SEA_ISLANDS) 1551 .Case("hawaii", GK_SEA_ISLANDS) 1552 .Default(GK_NONE); 1553 1554 if (GPU == GK_NONE) { 1555 return false; 1556 } 1557 1558 // Set the correct data layout 1559 switch (GPU) { 1560 case GK_NONE: 1561 case GK_R600: 1562 case GK_R700: 1563 case GK_EVERGREEN: 1564 case GK_NORTHERN_ISLANDS: 1565 DescriptionString = DescriptionStringR600; 1566 break; 1567 case GK_R600_DOUBLE_OPS: 1568 case GK_R700_DOUBLE_OPS: 1569 case GK_EVERGREEN_DOUBLE_OPS: 1570 case GK_CAYMAN: 1571 DescriptionString = DescriptionStringR600DoubleOps; 1572 break; 1573 case GK_SOUTHERN_ISLANDS: 1574 case GK_SEA_ISLANDS: 1575 DescriptionString = DescriptionStringSI; 1576 break; 1577 } 1578 1579 return true; 1580 } 1581 }; 1582 1583 } // end anonymous namespace 1584 1585 namespace { 1586 // Namespace for x86 abstract base class 1587 const Builtin::Info BuiltinInfo[] = { 1588 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1589 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1590 ALL_LANGUAGES }, 1591 #include "clang/Basic/BuiltinsX86.def" 1592 }; 1593 1594 static const char* const GCCRegNames[] = { 1595 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1596 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1597 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1598 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1599 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1600 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1601 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1602 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1603 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1604 }; 1605 1606 const TargetInfo::AddlRegName AddlRegNames[] = { 1607 { { "al", "ah", "eax", "rax" }, 0 }, 1608 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1609 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1610 { { "dl", "dh", "edx", "rdx" }, 1 }, 1611 { { "esi", "rsi" }, 4 }, 1612 { { "edi", "rdi" }, 5 }, 1613 { { "esp", "rsp" }, 7 }, 1614 { { "ebp", "rbp" }, 6 }, 1615 }; 1616 1617 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1618 // most of the implementation can be shared. 1619 class X86TargetInfo : public TargetInfo { 1620 enum X86SSEEnum { 1621 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1622 } SSELevel; 1623 enum MMX3DNowEnum { 1624 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1625 } MMX3DNowLevel; 1626 enum XOPEnum { 1627 NoXOP, 1628 SSE4A, 1629 FMA4, 1630 XOP 1631 } XOPLevel; 1632 1633 bool HasAES; 1634 bool HasPCLMUL; 1635 bool HasLZCNT; 1636 bool HasRDRND; 1637 bool HasBMI; 1638 bool HasBMI2; 1639 bool HasPOPCNT; 1640 bool HasRTM; 1641 bool HasPRFCHW; 1642 bool HasRDSEED; 1643 bool HasTBM; 1644 bool HasFMA; 1645 bool HasF16C; 1646 bool HasAVX512CD, HasAVX512ER, HasAVX512PF; 1647 bool HasSHA; 1648 bool HasCX16; 1649 1650 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1651 /// 1652 /// Each enumeration represents a particular CPU supported by Clang. These 1653 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1654 enum CPUKind { 1655 CK_Generic, 1656 1657 /// \name i386 1658 /// i386-generation processors. 1659 //@{ 1660 CK_i386, 1661 //@} 1662 1663 /// \name i486 1664 /// i486-generation processors. 1665 //@{ 1666 CK_i486, 1667 CK_WinChipC6, 1668 CK_WinChip2, 1669 CK_C3, 1670 //@} 1671 1672 /// \name i586 1673 /// i586-generation processors, P5 microarchitecture based. 1674 //@{ 1675 CK_i586, 1676 CK_Pentium, 1677 CK_PentiumMMX, 1678 //@} 1679 1680 /// \name i686 1681 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1682 //@{ 1683 CK_i686, 1684 CK_PentiumPro, 1685 CK_Pentium2, 1686 CK_Pentium3, 1687 CK_Pentium3M, 1688 CK_PentiumM, 1689 CK_C3_2, 1690 1691 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1692 /// Clang however has some logic to suport this. 1693 // FIXME: Warn, deprecate, and potentially remove this. 1694 CK_Yonah, 1695 //@} 1696 1697 /// \name Netburst 1698 /// Netburst microarchitecture based processors. 1699 //@{ 1700 CK_Pentium4, 1701 CK_Pentium4M, 1702 CK_Prescott, 1703 CK_Nocona, 1704 //@} 1705 1706 /// \name Core 1707 /// Core microarchitecture based processors. 1708 //@{ 1709 CK_Core2, 1710 1711 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1712 /// codename which GCC no longer accepts as an option to -march, but Clang 1713 /// has some logic for recognizing it. 1714 // FIXME: Warn, deprecate, and potentially remove this. 1715 CK_Penryn, 1716 //@} 1717 1718 /// \name Atom 1719 /// Atom processors 1720 //@{ 1721 CK_Atom, 1722 CK_Silvermont, 1723 //@} 1724 1725 /// \name Nehalem 1726 /// Nehalem microarchitecture based processors. 1727 //@{ 1728 CK_Corei7, 1729 CK_Corei7AVX, 1730 CK_CoreAVXi, 1731 CK_CoreAVX2, 1732 //@} 1733 1734 /// \name Knights Landing 1735 /// Knights Landing processor. 1736 CK_KNL, 1737 1738 /// \name K6 1739 /// K6 architecture processors. 1740 //@{ 1741 CK_K6, 1742 CK_K6_2, 1743 CK_K6_3, 1744 //@} 1745 1746 /// \name K7 1747 /// K7 architecture processors. 1748 //@{ 1749 CK_Athlon, 1750 CK_AthlonThunderbird, 1751 CK_Athlon4, 1752 CK_AthlonXP, 1753 CK_AthlonMP, 1754 //@} 1755 1756 /// \name K8 1757 /// K8 architecture processors. 1758 //@{ 1759 CK_Athlon64, 1760 CK_Athlon64SSE3, 1761 CK_AthlonFX, 1762 CK_K8, 1763 CK_K8SSE3, 1764 CK_Opteron, 1765 CK_OpteronSSE3, 1766 CK_AMDFAM10, 1767 //@} 1768 1769 /// \name Bobcat 1770 /// Bobcat architecture processors. 1771 //@{ 1772 CK_BTVER1, 1773 CK_BTVER2, 1774 //@} 1775 1776 /// \name Bulldozer 1777 /// Bulldozer architecture processors. 1778 //@{ 1779 CK_BDVER1, 1780 CK_BDVER2, 1781 CK_BDVER3, 1782 CK_BDVER4, 1783 //@} 1784 1785 /// This specification is deprecated and will be removed in the future. 1786 /// Users should prefer \see CK_K8. 1787 // FIXME: Warn on this when the CPU is set to it. 1788 CK_x86_64, 1789 //@} 1790 1791 /// \name Geode 1792 /// Geode processors. 1793 //@{ 1794 CK_Geode 1795 //@} 1796 } CPU; 1797 1798 enum FPMathKind { 1799 FP_Default, 1800 FP_SSE, 1801 FP_387 1802 } FPMath; 1803 1804 public: 1805 X86TargetInfo(const llvm::Triple &Triple) 1806 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1807 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 1808 HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false), 1809 HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasTBM(false), 1810 HasFMA(false), HasF16C(false), HasAVX512CD(false), HasAVX512ER(false), 1811 HasAVX512PF(false), HasSHA(false), HasCX16(false), CPU(CK_Generic), 1812 FPMath(FP_Default) { 1813 BigEndian = false; 1814 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1815 } 1816 unsigned getFloatEvalMethod() const override { 1817 // X87 evaluates with 80 bits "long double" precision. 1818 return SSELevel == NoSSE ? 2 : 0; 1819 } 1820 void getTargetBuiltins(const Builtin::Info *&Records, 1821 unsigned &NumRecords) const override { 1822 Records = BuiltinInfo; 1823 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1824 } 1825 void getGCCRegNames(const char * const *&Names, 1826 unsigned &NumNames) const override { 1827 Names = GCCRegNames; 1828 NumNames = llvm::array_lengthof(GCCRegNames); 1829 } 1830 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1831 unsigned &NumAliases) const override { 1832 Aliases = nullptr; 1833 NumAliases = 0; 1834 } 1835 void getGCCAddlRegNames(const AddlRegName *&Names, 1836 unsigned &NumNames) const override { 1837 Names = AddlRegNames; 1838 NumNames = llvm::array_lengthof(AddlRegNames); 1839 } 1840 bool validateAsmConstraint(const char *&Name, 1841 TargetInfo::ConstraintInfo &info) const override; 1842 std::string convertConstraint(const char *&Constraint) const override; 1843 const char *getClobbers() const override { 1844 return "~{dirflag},~{fpsr},~{flags}"; 1845 } 1846 void getTargetDefines(const LangOptions &Opts, 1847 MacroBuilder &Builder) const override; 1848 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 1849 bool Enabled); 1850 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 1851 bool Enabled); 1852 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 1853 bool Enabled); 1854 void setFeatureEnabled(llvm::StringMap<bool> &Features, 1855 StringRef Name, bool Enabled) const override { 1856 setFeatureEnabledImpl(Features, Name, Enabled); 1857 } 1858 // This exists purely to cut down on the number of virtual calls in 1859 // getDefaultFeatures which calls this repeatedly. 1860 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 1861 StringRef Name, bool Enabled); 1862 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 1863 bool hasFeature(StringRef Feature) const override; 1864 bool handleTargetFeatures(std::vector<std::string> &Features, 1865 DiagnosticsEngine &Diags) override; 1866 StringRef getABI() const override { 1867 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 1868 return "avx"; 1869 else if (getTriple().getArch() == llvm::Triple::x86 && 1870 MMX3DNowLevel == NoMMX3DNow) 1871 return "no-mmx"; 1872 return ""; 1873 } 1874 bool setCPU(const std::string &Name) override { 1875 CPU = llvm::StringSwitch<CPUKind>(Name) 1876 .Case("i386", CK_i386) 1877 .Case("i486", CK_i486) 1878 .Case("winchip-c6", CK_WinChipC6) 1879 .Case("winchip2", CK_WinChip2) 1880 .Case("c3", CK_C3) 1881 .Case("i586", CK_i586) 1882 .Case("pentium", CK_Pentium) 1883 .Case("pentium-mmx", CK_PentiumMMX) 1884 .Case("i686", CK_i686) 1885 .Case("pentiumpro", CK_PentiumPro) 1886 .Case("pentium2", CK_Pentium2) 1887 .Case("pentium3", CK_Pentium3) 1888 .Case("pentium3m", CK_Pentium3M) 1889 .Case("pentium-m", CK_PentiumM) 1890 .Case("c3-2", CK_C3_2) 1891 .Case("yonah", CK_Yonah) 1892 .Case("pentium4", CK_Pentium4) 1893 .Case("pentium4m", CK_Pentium4M) 1894 .Case("prescott", CK_Prescott) 1895 .Case("nocona", CK_Nocona) 1896 .Case("core2", CK_Core2) 1897 .Case("penryn", CK_Penryn) 1898 .Case("atom", CK_Atom) 1899 .Case("slm", CK_Silvermont) 1900 .Case("corei7", CK_Corei7) 1901 .Case("corei7-avx", CK_Corei7AVX) 1902 .Case("core-avx-i", CK_CoreAVXi) 1903 .Case("core-avx2", CK_CoreAVX2) 1904 .Case("knl", CK_KNL) 1905 .Case("k6", CK_K6) 1906 .Case("k6-2", CK_K6_2) 1907 .Case("k6-3", CK_K6_3) 1908 .Case("athlon", CK_Athlon) 1909 .Case("athlon-tbird", CK_AthlonThunderbird) 1910 .Case("athlon-4", CK_Athlon4) 1911 .Case("athlon-xp", CK_AthlonXP) 1912 .Case("athlon-mp", CK_AthlonMP) 1913 .Case("athlon64", CK_Athlon64) 1914 .Case("athlon64-sse3", CK_Athlon64SSE3) 1915 .Case("athlon-fx", CK_AthlonFX) 1916 .Case("k8", CK_K8) 1917 .Case("k8-sse3", CK_K8SSE3) 1918 .Case("opteron", CK_Opteron) 1919 .Case("opteron-sse3", CK_OpteronSSE3) 1920 .Case("amdfam10", CK_AMDFAM10) 1921 .Case("btver1", CK_BTVER1) 1922 .Case("btver2", CK_BTVER2) 1923 .Case("bdver1", CK_BDVER1) 1924 .Case("bdver2", CK_BDVER2) 1925 .Case("bdver3", CK_BDVER3) 1926 .Case("bdver4", CK_BDVER4) 1927 .Case("x86-64", CK_x86_64) 1928 .Case("geode", CK_Geode) 1929 .Default(CK_Generic); 1930 1931 // Perform any per-CPU checks necessary to determine if this CPU is 1932 // acceptable. 1933 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1934 // invalid without explaining *why*. 1935 switch (CPU) { 1936 case CK_Generic: 1937 // No processor selected! 1938 return false; 1939 1940 case CK_i386: 1941 case CK_i486: 1942 case CK_WinChipC6: 1943 case CK_WinChip2: 1944 case CK_C3: 1945 case CK_i586: 1946 case CK_Pentium: 1947 case CK_PentiumMMX: 1948 case CK_i686: 1949 case CK_PentiumPro: 1950 case CK_Pentium2: 1951 case CK_Pentium3: 1952 case CK_Pentium3M: 1953 case CK_PentiumM: 1954 case CK_Yonah: 1955 case CK_C3_2: 1956 case CK_Pentium4: 1957 case CK_Pentium4M: 1958 case CK_Prescott: 1959 case CK_K6: 1960 case CK_K6_2: 1961 case CK_K6_3: 1962 case CK_Athlon: 1963 case CK_AthlonThunderbird: 1964 case CK_Athlon4: 1965 case CK_AthlonXP: 1966 case CK_AthlonMP: 1967 case CK_Geode: 1968 // Only accept certain architectures when compiling in 32-bit mode. 1969 if (getTriple().getArch() != llvm::Triple::x86) 1970 return false; 1971 1972 // Fallthrough 1973 case CK_Nocona: 1974 case CK_Core2: 1975 case CK_Penryn: 1976 case CK_Atom: 1977 case CK_Silvermont: 1978 case CK_Corei7: 1979 case CK_Corei7AVX: 1980 case CK_CoreAVXi: 1981 case CK_CoreAVX2: 1982 case CK_KNL: 1983 case CK_Athlon64: 1984 case CK_Athlon64SSE3: 1985 case CK_AthlonFX: 1986 case CK_K8: 1987 case CK_K8SSE3: 1988 case CK_Opteron: 1989 case CK_OpteronSSE3: 1990 case CK_AMDFAM10: 1991 case CK_BTVER1: 1992 case CK_BTVER2: 1993 case CK_BDVER1: 1994 case CK_BDVER2: 1995 case CK_BDVER3: 1996 case CK_BDVER4: 1997 case CK_x86_64: 1998 return true; 1999 } 2000 llvm_unreachable("Unhandled CPU kind"); 2001 } 2002 2003 bool setFPMath(StringRef Name) override; 2004 2005 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2006 // We accept all non-ARM calling conventions 2007 return (CC == CC_X86ThisCall || 2008 CC == CC_X86FastCall || 2009 CC == CC_X86StdCall || 2010 CC == CC_C || 2011 CC == CC_X86Pascal || 2012 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2013 } 2014 2015 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2016 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2017 } 2018 }; 2019 2020 bool X86TargetInfo::setFPMath(StringRef Name) { 2021 if (Name == "387") { 2022 FPMath = FP_387; 2023 return true; 2024 } 2025 if (Name == "sse") { 2026 FPMath = FP_SSE; 2027 return true; 2028 } 2029 return false; 2030 } 2031 2032 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2033 // FIXME: This *really* should not be here. 2034 2035 // X86_64 always has SSE2. 2036 if (getTriple().getArch() == llvm::Triple::x86_64) 2037 setFeatureEnabledImpl(Features, "sse2", true); 2038 2039 switch (CPU) { 2040 case CK_Generic: 2041 case CK_i386: 2042 case CK_i486: 2043 case CK_i586: 2044 case CK_Pentium: 2045 case CK_i686: 2046 case CK_PentiumPro: 2047 break; 2048 case CK_PentiumMMX: 2049 case CK_Pentium2: 2050 setFeatureEnabledImpl(Features, "mmx", true); 2051 break; 2052 case CK_Pentium3: 2053 case CK_Pentium3M: 2054 setFeatureEnabledImpl(Features, "sse", true); 2055 break; 2056 case CK_PentiumM: 2057 case CK_Pentium4: 2058 case CK_Pentium4M: 2059 case CK_x86_64: 2060 setFeatureEnabledImpl(Features, "sse2", true); 2061 break; 2062 case CK_Yonah: 2063 case CK_Prescott: 2064 case CK_Nocona: 2065 setFeatureEnabledImpl(Features, "sse3", true); 2066 setFeatureEnabledImpl(Features, "cx16", true); 2067 break; 2068 case CK_Core2: 2069 setFeatureEnabledImpl(Features, "ssse3", true); 2070 setFeatureEnabledImpl(Features, "cx16", true); 2071 break; 2072 case CK_Penryn: 2073 setFeatureEnabledImpl(Features, "sse4.1", true); 2074 setFeatureEnabledImpl(Features, "cx16", true); 2075 break; 2076 case CK_Atom: 2077 setFeatureEnabledImpl(Features, "ssse3", true); 2078 setFeatureEnabledImpl(Features, "cx16", true); 2079 break; 2080 case CK_Silvermont: 2081 setFeatureEnabledImpl(Features, "sse4.2", true); 2082 setFeatureEnabledImpl(Features, "aes", true); 2083 setFeatureEnabledImpl(Features, "cx16", true); 2084 setFeatureEnabledImpl(Features, "pclmul", true); 2085 break; 2086 case CK_Corei7: 2087 setFeatureEnabledImpl(Features, "sse4.2", true); 2088 setFeatureEnabledImpl(Features, "cx16", true); 2089 break; 2090 case CK_Corei7AVX: 2091 setFeatureEnabledImpl(Features, "avx", true); 2092 setFeatureEnabledImpl(Features, "aes", true); 2093 setFeatureEnabledImpl(Features, "cx16", true); 2094 setFeatureEnabledImpl(Features, "pclmul", true); 2095 break; 2096 case CK_CoreAVXi: 2097 setFeatureEnabledImpl(Features, "avx", true); 2098 setFeatureEnabledImpl(Features, "aes", true); 2099 setFeatureEnabledImpl(Features, "pclmul", true); 2100 setFeatureEnabledImpl(Features, "rdrnd", true); 2101 setFeatureEnabledImpl(Features, "f16c", true); 2102 break; 2103 case CK_CoreAVX2: 2104 setFeatureEnabledImpl(Features, "avx2", true); 2105 setFeatureEnabledImpl(Features, "aes", true); 2106 setFeatureEnabledImpl(Features, "pclmul", true); 2107 setFeatureEnabledImpl(Features, "lzcnt", true); 2108 setFeatureEnabledImpl(Features, "rdrnd", true); 2109 setFeatureEnabledImpl(Features, "f16c", true); 2110 setFeatureEnabledImpl(Features, "bmi", true); 2111 setFeatureEnabledImpl(Features, "bmi2", true); 2112 setFeatureEnabledImpl(Features, "rtm", true); 2113 setFeatureEnabledImpl(Features, "fma", true); 2114 setFeatureEnabledImpl(Features, "cx16", true); 2115 break; 2116 case CK_KNL: 2117 setFeatureEnabledImpl(Features, "avx512f", true); 2118 setFeatureEnabledImpl(Features, "avx512cd", true); 2119 setFeatureEnabledImpl(Features, "avx512er", true); 2120 setFeatureEnabledImpl(Features, "avx512pf", true); 2121 setFeatureEnabledImpl(Features, "aes", true); 2122 setFeatureEnabledImpl(Features, "pclmul", true); 2123 setFeatureEnabledImpl(Features, "lzcnt", true); 2124 setFeatureEnabledImpl(Features, "rdrnd", true); 2125 setFeatureEnabledImpl(Features, "f16c", true); 2126 setFeatureEnabledImpl(Features, "bmi", true); 2127 setFeatureEnabledImpl(Features, "bmi2", true); 2128 setFeatureEnabledImpl(Features, "rtm", true); 2129 setFeatureEnabledImpl(Features, "fma", true); 2130 break; 2131 case CK_K6: 2132 case CK_WinChipC6: 2133 setFeatureEnabledImpl(Features, "mmx", true); 2134 break; 2135 case CK_K6_2: 2136 case CK_K6_3: 2137 case CK_WinChip2: 2138 case CK_C3: 2139 setFeatureEnabledImpl(Features, "3dnow", true); 2140 break; 2141 case CK_Athlon: 2142 case CK_AthlonThunderbird: 2143 case CK_Geode: 2144 setFeatureEnabledImpl(Features, "3dnowa", true); 2145 break; 2146 case CK_Athlon4: 2147 case CK_AthlonXP: 2148 case CK_AthlonMP: 2149 setFeatureEnabledImpl(Features, "sse", true); 2150 setFeatureEnabledImpl(Features, "3dnowa", true); 2151 break; 2152 case CK_K8: 2153 case CK_Opteron: 2154 case CK_Athlon64: 2155 case CK_AthlonFX: 2156 setFeatureEnabledImpl(Features, "sse2", true); 2157 setFeatureEnabledImpl(Features, "3dnowa", true); 2158 break; 2159 case CK_K8SSE3: 2160 case CK_OpteronSSE3: 2161 case CK_Athlon64SSE3: 2162 setFeatureEnabledImpl(Features, "sse3", true); 2163 setFeatureEnabledImpl(Features, "3dnowa", true); 2164 break; 2165 case CK_AMDFAM10: 2166 setFeatureEnabledImpl(Features, "sse3", true); 2167 setFeatureEnabledImpl(Features, "sse4a", true); 2168 setFeatureEnabledImpl(Features, "3dnowa", true); 2169 setFeatureEnabledImpl(Features, "lzcnt", true); 2170 setFeatureEnabledImpl(Features, "popcnt", true); 2171 break; 2172 case CK_BTVER1: 2173 setFeatureEnabledImpl(Features, "ssse3", true); 2174 setFeatureEnabledImpl(Features, "sse4a", true); 2175 setFeatureEnabledImpl(Features, "cx16", true); 2176 setFeatureEnabledImpl(Features, "lzcnt", true); 2177 setFeatureEnabledImpl(Features, "popcnt", true); 2178 setFeatureEnabledImpl(Features, "prfchw", true); 2179 break; 2180 case CK_BTVER2: 2181 setFeatureEnabledImpl(Features, "avx", true); 2182 setFeatureEnabledImpl(Features, "sse4a", true); 2183 setFeatureEnabledImpl(Features, "lzcnt", true); 2184 setFeatureEnabledImpl(Features, "aes", true); 2185 setFeatureEnabledImpl(Features, "pclmul", true); 2186 setFeatureEnabledImpl(Features, "prfchw", true); 2187 setFeatureEnabledImpl(Features, "bmi", true); 2188 setFeatureEnabledImpl(Features, "f16c", true); 2189 setFeatureEnabledImpl(Features, "cx16", true); 2190 break; 2191 case CK_BDVER1: 2192 setFeatureEnabledImpl(Features, "xop", true); 2193 setFeatureEnabledImpl(Features, "lzcnt", true); 2194 setFeatureEnabledImpl(Features, "aes", true); 2195 setFeatureEnabledImpl(Features, "pclmul", true); 2196 setFeatureEnabledImpl(Features, "prfchw", true); 2197 setFeatureEnabledImpl(Features, "cx16", true); 2198 break; 2199 case CK_BDVER4: 2200 setFeatureEnabledImpl(Features, "avx2", true); 2201 setFeatureEnabledImpl(Features, "bmi2", true); 2202 // FALLTHROUGH 2203 case CK_BDVER2: 2204 case CK_BDVER3: 2205 setFeatureEnabledImpl(Features, "xop", true); 2206 setFeatureEnabledImpl(Features, "lzcnt", true); 2207 setFeatureEnabledImpl(Features, "aes", true); 2208 setFeatureEnabledImpl(Features, "pclmul", true); 2209 setFeatureEnabledImpl(Features, "prfchw", true); 2210 setFeatureEnabledImpl(Features, "bmi", true); 2211 setFeatureEnabledImpl(Features, "fma", true); 2212 setFeatureEnabledImpl(Features, "f16c", true); 2213 setFeatureEnabledImpl(Features, "tbm", true); 2214 setFeatureEnabledImpl(Features, "cx16", true); 2215 break; 2216 case CK_C3_2: 2217 setFeatureEnabledImpl(Features, "sse", true); 2218 break; 2219 } 2220 } 2221 2222 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2223 X86SSEEnum Level, bool Enabled) { 2224 if (Enabled) { 2225 switch (Level) { 2226 case AVX512F: 2227 Features["avx512f"] = true; 2228 case AVX2: 2229 Features["avx2"] = true; 2230 case AVX: 2231 Features["avx"] = true; 2232 case SSE42: 2233 Features["sse4.2"] = true; 2234 case SSE41: 2235 Features["sse4.1"] = true; 2236 case SSSE3: 2237 Features["ssse3"] = true; 2238 case SSE3: 2239 Features["sse3"] = true; 2240 case SSE2: 2241 Features["sse2"] = true; 2242 case SSE1: 2243 Features["sse"] = true; 2244 case NoSSE: 2245 break; 2246 } 2247 return; 2248 } 2249 2250 switch (Level) { 2251 case NoSSE: 2252 case SSE1: 2253 Features["sse"] = false; 2254 case SSE2: 2255 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2256 Features["sha"] = false; 2257 case SSE3: 2258 Features["sse3"] = false; 2259 setXOPLevel(Features, NoXOP, false); 2260 case SSSE3: 2261 Features["ssse3"] = false; 2262 case SSE41: 2263 Features["sse4.1"] = false; 2264 case SSE42: 2265 Features["sse4.2"] = false; 2266 case AVX: 2267 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2268 setXOPLevel(Features, FMA4, false); 2269 case AVX2: 2270 Features["avx2"] = false; 2271 case AVX512F: 2272 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2273 Features["avx512pf"] = false; 2274 } 2275 } 2276 2277 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2278 MMX3DNowEnum Level, bool Enabled) { 2279 if (Enabled) { 2280 switch (Level) { 2281 case AMD3DNowAthlon: 2282 Features["3dnowa"] = true; 2283 case AMD3DNow: 2284 Features["3dnow"] = true; 2285 case MMX: 2286 Features["mmx"] = true; 2287 case NoMMX3DNow: 2288 break; 2289 } 2290 return; 2291 } 2292 2293 switch (Level) { 2294 case NoMMX3DNow: 2295 case MMX: 2296 Features["mmx"] = false; 2297 case AMD3DNow: 2298 Features["3dnow"] = false; 2299 case AMD3DNowAthlon: 2300 Features["3dnowa"] = false; 2301 } 2302 } 2303 2304 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2305 bool Enabled) { 2306 if (Enabled) { 2307 switch (Level) { 2308 case XOP: 2309 Features["xop"] = true; 2310 case FMA4: 2311 Features["fma4"] = true; 2312 setSSELevel(Features, AVX, true); 2313 case SSE4A: 2314 Features["sse4a"] = true; 2315 setSSELevel(Features, SSE3, true); 2316 case NoXOP: 2317 break; 2318 } 2319 return; 2320 } 2321 2322 switch (Level) { 2323 case NoXOP: 2324 case SSE4A: 2325 Features["sse4a"] = false; 2326 case FMA4: 2327 Features["fma4"] = false; 2328 case XOP: 2329 Features["xop"] = false; 2330 } 2331 } 2332 2333 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2334 StringRef Name, bool Enabled) { 2335 // FIXME: This *really* should not be here. We need some way of translating 2336 // options into llvm subtarget features. 2337 if (Name == "sse4") 2338 Name = "sse4.2"; 2339 2340 Features[Name] = Enabled; 2341 2342 if (Name == "mmx") { 2343 setMMXLevel(Features, MMX, Enabled); 2344 } else if (Name == "sse") { 2345 setSSELevel(Features, SSE1, Enabled); 2346 } else if (Name == "sse2") { 2347 setSSELevel(Features, SSE2, Enabled); 2348 } else if (Name == "sse3") { 2349 setSSELevel(Features, SSE3, Enabled); 2350 } else if (Name == "ssse3") { 2351 setSSELevel(Features, SSSE3, Enabled); 2352 } else if (Name == "sse4.2") { 2353 setSSELevel(Features, SSE42, Enabled); 2354 } else if (Name == "sse4.1") { 2355 setSSELevel(Features, SSE41, Enabled); 2356 } else if (Name == "3dnow") { 2357 setMMXLevel(Features, AMD3DNow, Enabled); 2358 } else if (Name == "3dnowa") { 2359 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2360 } else if (Name == "aes") { 2361 if (Enabled) 2362 setSSELevel(Features, SSE2, Enabled); 2363 } else if (Name == "pclmul") { 2364 if (Enabled) 2365 setSSELevel(Features, SSE2, Enabled); 2366 } else if (Name == "avx") { 2367 setSSELevel(Features, AVX, Enabled); 2368 } else if (Name == "avx2") { 2369 setSSELevel(Features, AVX2, Enabled); 2370 } else if (Name == "avx512f") { 2371 setSSELevel(Features, AVX512F, Enabled); 2372 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf") { 2373 if (Enabled) 2374 setSSELevel(Features, AVX512F, Enabled); 2375 } else if (Name == "fma") { 2376 if (Enabled) 2377 setSSELevel(Features, AVX, Enabled); 2378 } else if (Name == "fma4") { 2379 setXOPLevel(Features, FMA4, Enabled); 2380 } else if (Name == "xop") { 2381 setXOPLevel(Features, XOP, Enabled); 2382 } else if (Name == "sse4a") { 2383 setXOPLevel(Features, SSE4A, Enabled); 2384 } else if (Name == "f16c") { 2385 if (Enabled) 2386 setSSELevel(Features, AVX, Enabled); 2387 } else if (Name == "sha") { 2388 if (Enabled) 2389 setSSELevel(Features, SSE2, Enabled); 2390 } 2391 } 2392 2393 /// handleTargetFeatures - Perform initialization based on the user 2394 /// configured set of features. 2395 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2396 DiagnosticsEngine &Diags) { 2397 // Remember the maximum enabled sselevel. 2398 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2399 // Ignore disabled features. 2400 if (Features[i][0] == '-') 2401 continue; 2402 2403 StringRef Feature = StringRef(Features[i]).substr(1); 2404 2405 if (Feature == "aes") { 2406 HasAES = true; 2407 continue; 2408 } 2409 2410 if (Feature == "pclmul") { 2411 HasPCLMUL = true; 2412 continue; 2413 } 2414 2415 if (Feature == "lzcnt") { 2416 HasLZCNT = true; 2417 continue; 2418 } 2419 2420 if (Feature == "rdrnd") { 2421 HasRDRND = true; 2422 continue; 2423 } 2424 2425 if (Feature == "bmi") { 2426 HasBMI = true; 2427 continue; 2428 } 2429 2430 if (Feature == "bmi2") { 2431 HasBMI2 = true; 2432 continue; 2433 } 2434 2435 if (Feature == "popcnt") { 2436 HasPOPCNT = true; 2437 continue; 2438 } 2439 2440 if (Feature == "rtm") { 2441 HasRTM = true; 2442 continue; 2443 } 2444 2445 if (Feature == "prfchw") { 2446 HasPRFCHW = true; 2447 continue; 2448 } 2449 2450 if (Feature == "rdseed") { 2451 HasRDSEED = true; 2452 continue; 2453 } 2454 2455 if (Feature == "tbm") { 2456 HasTBM = true; 2457 continue; 2458 } 2459 2460 if (Feature == "fma") { 2461 HasFMA = true; 2462 continue; 2463 } 2464 2465 if (Feature == "f16c") { 2466 HasF16C = true; 2467 continue; 2468 } 2469 2470 if (Feature == "avx512cd") { 2471 HasAVX512CD = true; 2472 continue; 2473 } 2474 2475 if (Feature == "avx512er") { 2476 HasAVX512ER = true; 2477 continue; 2478 } 2479 2480 if (Feature == "avx512pf") { 2481 HasAVX512PF = true; 2482 continue; 2483 } 2484 2485 if (Feature == "sha") { 2486 HasSHA = true; 2487 continue; 2488 } 2489 2490 if (Feature == "cx16") { 2491 HasCX16 = true; 2492 continue; 2493 } 2494 2495 assert(Features[i][0] == '+' && "Invalid target feature!"); 2496 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2497 .Case("avx512f", AVX512F) 2498 .Case("avx2", AVX2) 2499 .Case("avx", AVX) 2500 .Case("sse4.2", SSE42) 2501 .Case("sse4.1", SSE41) 2502 .Case("ssse3", SSSE3) 2503 .Case("sse3", SSE3) 2504 .Case("sse2", SSE2) 2505 .Case("sse", SSE1) 2506 .Default(NoSSE); 2507 SSELevel = std::max(SSELevel, Level); 2508 2509 MMX3DNowEnum ThreeDNowLevel = 2510 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2511 .Case("3dnowa", AMD3DNowAthlon) 2512 .Case("3dnow", AMD3DNow) 2513 .Case("mmx", MMX) 2514 .Default(NoMMX3DNow); 2515 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2516 2517 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2518 .Case("xop", XOP) 2519 .Case("fma4", FMA4) 2520 .Case("sse4a", SSE4A) 2521 .Default(NoXOP); 2522 XOPLevel = std::max(XOPLevel, XLevel); 2523 } 2524 2525 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2526 // Can't do this earlier because we need to be able to explicitly enable 2527 // popcnt and still disable sse4.2. 2528 if (!HasPOPCNT && SSELevel >= SSE42 && 2529 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2530 HasPOPCNT = true; 2531 Features.push_back("+popcnt"); 2532 } 2533 2534 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2535 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2536 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2537 HasPRFCHW = true; 2538 Features.push_back("+prfchw"); 2539 } 2540 2541 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2542 // matches the selected sse level. 2543 if (FPMath == FP_SSE && SSELevel < SSE1) { 2544 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2545 return false; 2546 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2547 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2548 return false; 2549 } 2550 2551 // Don't tell the backend if we're turning off mmx; it will end up disabling 2552 // SSE, which we don't want. 2553 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2554 // then enable MMX. 2555 std::vector<std::string>::iterator it; 2556 it = std::find(Features.begin(), Features.end(), "-mmx"); 2557 if (it != Features.end()) 2558 Features.erase(it); 2559 else if (SSELevel > NoSSE) 2560 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2561 return true; 2562 } 2563 2564 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2565 /// definitions for this particular subtarget. 2566 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2567 MacroBuilder &Builder) const { 2568 // Target identification. 2569 if (getTriple().getArch() == llvm::Triple::x86_64) { 2570 Builder.defineMacro("__amd64__"); 2571 Builder.defineMacro("__amd64"); 2572 Builder.defineMacro("__x86_64"); 2573 Builder.defineMacro("__x86_64__"); 2574 } else { 2575 DefineStd(Builder, "i386", Opts); 2576 } 2577 2578 // Subtarget options. 2579 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2580 // truly should be based on -mtune options. 2581 switch (CPU) { 2582 case CK_Generic: 2583 break; 2584 case CK_i386: 2585 // The rest are coming from the i386 define above. 2586 Builder.defineMacro("__tune_i386__"); 2587 break; 2588 case CK_i486: 2589 case CK_WinChipC6: 2590 case CK_WinChip2: 2591 case CK_C3: 2592 defineCPUMacros(Builder, "i486"); 2593 break; 2594 case CK_PentiumMMX: 2595 Builder.defineMacro("__pentium_mmx__"); 2596 Builder.defineMacro("__tune_pentium_mmx__"); 2597 // Fallthrough 2598 case CK_i586: 2599 case CK_Pentium: 2600 defineCPUMacros(Builder, "i586"); 2601 defineCPUMacros(Builder, "pentium"); 2602 break; 2603 case CK_Pentium3: 2604 case CK_Pentium3M: 2605 case CK_PentiumM: 2606 Builder.defineMacro("__tune_pentium3__"); 2607 // Fallthrough 2608 case CK_Pentium2: 2609 case CK_C3_2: 2610 Builder.defineMacro("__tune_pentium2__"); 2611 // Fallthrough 2612 case CK_PentiumPro: 2613 Builder.defineMacro("__tune_i686__"); 2614 Builder.defineMacro("__tune_pentiumpro__"); 2615 // Fallthrough 2616 case CK_i686: 2617 Builder.defineMacro("__i686"); 2618 Builder.defineMacro("__i686__"); 2619 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2620 Builder.defineMacro("__pentiumpro"); 2621 Builder.defineMacro("__pentiumpro__"); 2622 break; 2623 case CK_Pentium4: 2624 case CK_Pentium4M: 2625 defineCPUMacros(Builder, "pentium4"); 2626 break; 2627 case CK_Yonah: 2628 case CK_Prescott: 2629 case CK_Nocona: 2630 defineCPUMacros(Builder, "nocona"); 2631 break; 2632 case CK_Core2: 2633 case CK_Penryn: 2634 defineCPUMacros(Builder, "core2"); 2635 break; 2636 case CK_Atom: 2637 defineCPUMacros(Builder, "atom"); 2638 break; 2639 case CK_Silvermont: 2640 defineCPUMacros(Builder, "slm"); 2641 break; 2642 case CK_Corei7: 2643 case CK_Corei7AVX: 2644 case CK_CoreAVXi: 2645 case CK_CoreAVX2: 2646 defineCPUMacros(Builder, "corei7"); 2647 break; 2648 case CK_KNL: 2649 defineCPUMacros(Builder, "knl"); 2650 break; 2651 case CK_K6_2: 2652 Builder.defineMacro("__k6_2__"); 2653 Builder.defineMacro("__tune_k6_2__"); 2654 // Fallthrough 2655 case CK_K6_3: 2656 if (CPU != CK_K6_2) { // In case of fallthrough 2657 // FIXME: GCC may be enabling these in cases where some other k6 2658 // architecture is specified but -m3dnow is explicitly provided. The 2659 // exact semantics need to be determined and emulated here. 2660 Builder.defineMacro("__k6_3__"); 2661 Builder.defineMacro("__tune_k6_3__"); 2662 } 2663 // Fallthrough 2664 case CK_K6: 2665 defineCPUMacros(Builder, "k6"); 2666 break; 2667 case CK_Athlon: 2668 case CK_AthlonThunderbird: 2669 case CK_Athlon4: 2670 case CK_AthlonXP: 2671 case CK_AthlonMP: 2672 defineCPUMacros(Builder, "athlon"); 2673 if (SSELevel != NoSSE) { 2674 Builder.defineMacro("__athlon_sse__"); 2675 Builder.defineMacro("__tune_athlon_sse__"); 2676 } 2677 break; 2678 case CK_K8: 2679 case CK_K8SSE3: 2680 case CK_x86_64: 2681 case CK_Opteron: 2682 case CK_OpteronSSE3: 2683 case CK_Athlon64: 2684 case CK_Athlon64SSE3: 2685 case CK_AthlonFX: 2686 defineCPUMacros(Builder, "k8"); 2687 break; 2688 case CK_AMDFAM10: 2689 defineCPUMacros(Builder, "amdfam10"); 2690 break; 2691 case CK_BTVER1: 2692 defineCPUMacros(Builder, "btver1"); 2693 break; 2694 case CK_BTVER2: 2695 defineCPUMacros(Builder, "btver2"); 2696 break; 2697 case CK_BDVER1: 2698 defineCPUMacros(Builder, "bdver1"); 2699 break; 2700 case CK_BDVER2: 2701 defineCPUMacros(Builder, "bdver2"); 2702 break; 2703 case CK_BDVER3: 2704 defineCPUMacros(Builder, "bdver3"); 2705 break; 2706 case CK_BDVER4: 2707 defineCPUMacros(Builder, "bdver4"); 2708 break; 2709 case CK_Geode: 2710 defineCPUMacros(Builder, "geode"); 2711 break; 2712 } 2713 2714 // Target properties. 2715 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2716 2717 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2718 // functions in glibc header files that use FP Stack inline asm which the 2719 // backend can't deal with (PR879). 2720 Builder.defineMacro("__NO_MATH_INLINES"); 2721 2722 if (HasAES) 2723 Builder.defineMacro("__AES__"); 2724 2725 if (HasPCLMUL) 2726 Builder.defineMacro("__PCLMUL__"); 2727 2728 if (HasLZCNT) 2729 Builder.defineMacro("__LZCNT__"); 2730 2731 if (HasRDRND) 2732 Builder.defineMacro("__RDRND__"); 2733 2734 if (HasBMI) 2735 Builder.defineMacro("__BMI__"); 2736 2737 if (HasBMI2) 2738 Builder.defineMacro("__BMI2__"); 2739 2740 if (HasPOPCNT) 2741 Builder.defineMacro("__POPCNT__"); 2742 2743 if (HasRTM) 2744 Builder.defineMacro("__RTM__"); 2745 2746 if (HasPRFCHW) 2747 Builder.defineMacro("__PRFCHW__"); 2748 2749 if (HasRDSEED) 2750 Builder.defineMacro("__RDSEED__"); 2751 2752 if (HasTBM) 2753 Builder.defineMacro("__TBM__"); 2754 2755 switch (XOPLevel) { 2756 case XOP: 2757 Builder.defineMacro("__XOP__"); 2758 case FMA4: 2759 Builder.defineMacro("__FMA4__"); 2760 case SSE4A: 2761 Builder.defineMacro("__SSE4A__"); 2762 case NoXOP: 2763 break; 2764 } 2765 2766 if (HasFMA) 2767 Builder.defineMacro("__FMA__"); 2768 2769 if (HasF16C) 2770 Builder.defineMacro("__F16C__"); 2771 2772 if (HasAVX512CD) 2773 Builder.defineMacro("__AVX512CD__"); 2774 if (HasAVX512ER) 2775 Builder.defineMacro("__AVX512ER__"); 2776 if (HasAVX512PF) 2777 Builder.defineMacro("__AVX512PF__"); 2778 2779 if (HasSHA) 2780 Builder.defineMacro("__SHA__"); 2781 2782 if (HasCX16) 2783 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 2784 2785 // Each case falls through to the previous one here. 2786 switch (SSELevel) { 2787 case AVX512F: 2788 Builder.defineMacro("__AVX512F__"); 2789 case AVX2: 2790 Builder.defineMacro("__AVX2__"); 2791 case AVX: 2792 Builder.defineMacro("__AVX__"); 2793 case SSE42: 2794 Builder.defineMacro("__SSE4_2__"); 2795 case SSE41: 2796 Builder.defineMacro("__SSE4_1__"); 2797 case SSSE3: 2798 Builder.defineMacro("__SSSE3__"); 2799 case SSE3: 2800 Builder.defineMacro("__SSE3__"); 2801 case SSE2: 2802 Builder.defineMacro("__SSE2__"); 2803 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2804 case SSE1: 2805 Builder.defineMacro("__SSE__"); 2806 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2807 case NoSSE: 2808 break; 2809 } 2810 2811 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 2812 switch (SSELevel) { 2813 case AVX512F: 2814 case AVX2: 2815 case AVX: 2816 case SSE42: 2817 case SSE41: 2818 case SSSE3: 2819 case SSE3: 2820 case SSE2: 2821 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2822 break; 2823 case SSE1: 2824 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2825 break; 2826 default: 2827 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2828 } 2829 } 2830 2831 // Each case falls through to the previous one here. 2832 switch (MMX3DNowLevel) { 2833 case AMD3DNowAthlon: 2834 Builder.defineMacro("__3dNOW_A__"); 2835 case AMD3DNow: 2836 Builder.defineMacro("__3dNOW__"); 2837 case MMX: 2838 Builder.defineMacro("__MMX__"); 2839 case NoMMX3DNow: 2840 break; 2841 } 2842 2843 if (CPU >= CK_i486) { 2844 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 2845 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 2846 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 2847 } 2848 if (CPU >= CK_i586) 2849 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 2850 } 2851 2852 bool X86TargetInfo::hasFeature(StringRef Feature) const { 2853 return llvm::StringSwitch<bool>(Feature) 2854 .Case("aes", HasAES) 2855 .Case("avx", SSELevel >= AVX) 2856 .Case("avx2", SSELevel >= AVX2) 2857 .Case("avx512f", SSELevel >= AVX512F) 2858 .Case("avx512cd", HasAVX512CD) 2859 .Case("avx512er", HasAVX512ER) 2860 .Case("avx512pf", HasAVX512PF) 2861 .Case("bmi", HasBMI) 2862 .Case("bmi2", HasBMI2) 2863 .Case("cx16", HasCX16) 2864 .Case("f16c", HasF16C) 2865 .Case("fma", HasFMA) 2866 .Case("fma4", XOPLevel >= FMA4) 2867 .Case("tbm", HasTBM) 2868 .Case("lzcnt", HasLZCNT) 2869 .Case("rdrnd", HasRDRND) 2870 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 2871 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 2872 .Case("mmx", MMX3DNowLevel >= MMX) 2873 .Case("pclmul", HasPCLMUL) 2874 .Case("popcnt", HasPOPCNT) 2875 .Case("rtm", HasRTM) 2876 .Case("prfchw", HasPRFCHW) 2877 .Case("rdseed", HasRDSEED) 2878 .Case("sha", HasSHA) 2879 .Case("sse", SSELevel >= SSE1) 2880 .Case("sse2", SSELevel >= SSE2) 2881 .Case("sse3", SSELevel >= SSE3) 2882 .Case("ssse3", SSELevel >= SSSE3) 2883 .Case("sse4.1", SSELevel >= SSE41) 2884 .Case("sse4.2", SSELevel >= SSE42) 2885 .Case("sse4a", XOPLevel >= SSE4A) 2886 .Case("x86", true) 2887 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 2888 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 2889 .Case("xop", XOPLevel >= XOP) 2890 .Default(false); 2891 } 2892 2893 bool 2894 X86TargetInfo::validateAsmConstraint(const char *&Name, 2895 TargetInfo::ConstraintInfo &Info) const { 2896 switch (*Name) { 2897 default: return false; 2898 case 'Y': // first letter of a pair: 2899 switch (*(Name+1)) { 2900 default: return false; 2901 case '0': // First SSE register. 2902 case 't': // Any SSE register, when SSE2 is enabled. 2903 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 2904 case 'm': // any MMX register, when inter-unit moves enabled. 2905 break; // falls through to setAllowsRegister. 2906 } 2907 case 'a': // eax. 2908 case 'b': // ebx. 2909 case 'c': // ecx. 2910 case 'd': // edx. 2911 case 'S': // esi. 2912 case 'D': // edi. 2913 case 'A': // edx:eax. 2914 case 'f': // any x87 floating point stack register. 2915 case 't': // top of floating point stack. 2916 case 'u': // second from top of floating point stack. 2917 case 'q': // Any register accessible as [r]l: a, b, c, and d. 2918 case 'y': // Any MMX register. 2919 case 'x': // Any SSE register. 2920 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 2921 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 2922 case 'l': // "Index" registers: any general register that can be used as an 2923 // index in a base+index memory access. 2924 Info.setAllowsRegister(); 2925 return true; 2926 case 'C': // SSE floating point constant. 2927 case 'G': // x87 floating point constant. 2928 case 'e': // 32-bit signed integer constant for use with zero-extending 2929 // x86_64 instructions. 2930 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 2931 // x86_64 instructions. 2932 return true; 2933 } 2934 } 2935 2936 2937 std::string 2938 X86TargetInfo::convertConstraint(const char *&Constraint) const { 2939 switch (*Constraint) { 2940 case 'a': return std::string("{ax}"); 2941 case 'b': return std::string("{bx}"); 2942 case 'c': return std::string("{cx}"); 2943 case 'd': return std::string("{dx}"); 2944 case 'S': return std::string("{si}"); 2945 case 'D': return std::string("{di}"); 2946 case 'p': // address 2947 return std::string("im"); 2948 case 't': // top of floating point stack. 2949 return std::string("{st}"); 2950 case 'u': // second from top of floating point stack. 2951 return std::string("{st(1)}"); // second from top of floating point stack. 2952 default: 2953 return std::string(1, *Constraint); 2954 } 2955 } 2956 } // end anonymous namespace 2957 2958 namespace { 2959 // X86-32 generic target 2960 class X86_32TargetInfo : public X86TargetInfo { 2961 public: 2962 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 2963 DoubleAlign = LongLongAlign = 32; 2964 LongDoubleWidth = 96; 2965 LongDoubleAlign = 32; 2966 SuitableAlign = 128; 2967 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 2968 SizeType = UnsignedInt; 2969 PtrDiffType = SignedInt; 2970 IntPtrType = SignedInt; 2971 RegParmMax = 3; 2972 2973 // Use fpret for all types. 2974 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 2975 (1 << TargetInfo::Double) | 2976 (1 << TargetInfo::LongDouble)); 2977 2978 // x86-32 has atomics up to 8 bytes 2979 // FIXME: Check that we actually have cmpxchg8b before setting 2980 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 2981 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 2982 } 2983 BuiltinVaListKind getBuiltinVaListKind() const override { 2984 return TargetInfo::CharPtrBuiltinVaList; 2985 } 2986 2987 int getEHDataRegisterNumber(unsigned RegNo) const override { 2988 if (RegNo == 0) return 0; 2989 if (RegNo == 1) return 2; 2990 return -1; 2991 } 2992 bool validateInputSize(StringRef Constraint, 2993 unsigned Size) const override { 2994 switch (Constraint[0]) { 2995 default: break; 2996 case 'a': 2997 case 'b': 2998 case 'c': 2999 case 'd': 3000 return Size <= 32; 3001 } 3002 3003 return true; 3004 } 3005 }; 3006 } // end anonymous namespace 3007 3008 namespace { 3009 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3010 public: 3011 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3012 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3013 3014 unsigned getFloatEvalMethod() const override { 3015 unsigned Major, Minor, Micro; 3016 getTriple().getOSVersion(Major, Minor, Micro); 3017 // New NetBSD uses the default rounding mode. 3018 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3019 return X86_32TargetInfo::getFloatEvalMethod(); 3020 // NetBSD before 6.99.26 defaults to "double" rounding. 3021 return 1; 3022 } 3023 }; 3024 } // end anonymous namespace 3025 3026 namespace { 3027 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3028 public: 3029 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3030 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3031 SizeType = UnsignedLong; 3032 IntPtrType = SignedLong; 3033 PtrDiffType = SignedLong; 3034 } 3035 }; 3036 } // end anonymous namespace 3037 3038 namespace { 3039 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3040 public: 3041 BitrigI386TargetInfo(const llvm::Triple &Triple) 3042 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3043 SizeType = UnsignedLong; 3044 IntPtrType = SignedLong; 3045 PtrDiffType = SignedLong; 3046 } 3047 }; 3048 } // end anonymous namespace 3049 3050 namespace { 3051 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3052 public: 3053 DarwinI386TargetInfo(const llvm::Triple &Triple) 3054 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3055 LongDoubleWidth = 128; 3056 LongDoubleAlign = 128; 3057 SuitableAlign = 128; 3058 MaxVectorAlign = 256; 3059 SizeType = UnsignedLong; 3060 IntPtrType = SignedLong; 3061 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3062 HasAlignMac68kSupport = true; 3063 } 3064 3065 }; 3066 } // end anonymous namespace 3067 3068 namespace { 3069 // x86-32 Windows target 3070 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3071 public: 3072 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3073 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3074 WCharType = UnsignedShort; 3075 DoubleAlign = LongLongAlign = 64; 3076 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3077 } 3078 void getTargetDefines(const LangOptions &Opts, 3079 MacroBuilder &Builder) const override { 3080 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3081 } 3082 }; 3083 } // end anonymous namespace 3084 3085 namespace { 3086 3087 // x86-32 Windows Visual Studio target 3088 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3089 public: 3090 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3091 : WindowsX86_32TargetInfo(Triple) { 3092 LongDoubleWidth = LongDoubleAlign = 64; 3093 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3094 } 3095 void getTargetDefines(const LangOptions &Opts, 3096 MacroBuilder &Builder) const override { 3097 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3098 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3099 // The value of the following reflects processor type. 3100 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3101 // We lost the original triple, so we use the default. 3102 Builder.defineMacro("_M_IX86", "600"); 3103 } 3104 }; 3105 } // end anonymous namespace 3106 3107 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3108 Builder.defineMacro("__MSVCRT__"); 3109 Builder.defineMacro("__MINGW32__"); 3110 3111 // Mingw defines __declspec(a) to __attribute__((a)). Clang supports 3112 // __declspec natively under -fms-extensions, but we define a no-op __declspec 3113 // macro anyway for pre-processor compatibility. 3114 if (Opts.MicrosoftExt) 3115 Builder.defineMacro("__declspec", "__declspec"); 3116 else 3117 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3118 3119 if (!Opts.MicrosoftExt) { 3120 // Provide macros for all the calling convention keywords. Provide both 3121 // single and double underscore prefixed variants. These are available on 3122 // x64 as well as x86, even though they have no effect. 3123 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3124 for (const char *CC : CCs) { 3125 std::string GCCSpelling = "__attribute__((__"; 3126 GCCSpelling += CC; 3127 GCCSpelling += "__))"; 3128 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3129 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3130 } 3131 } 3132 } 3133 3134 namespace { 3135 // x86-32 MinGW target 3136 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3137 public: 3138 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3139 : WindowsX86_32TargetInfo(Triple) {} 3140 void getTargetDefines(const LangOptions &Opts, 3141 MacroBuilder &Builder) const override { 3142 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3143 DefineStd(Builder, "WIN32", Opts); 3144 DefineStd(Builder, "WINNT", Opts); 3145 Builder.defineMacro("_X86_"); 3146 addMinGWDefines(Opts, Builder); 3147 } 3148 }; 3149 } // end anonymous namespace 3150 3151 namespace { 3152 // x86-32 Cygwin target 3153 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3154 public: 3155 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3156 : X86_32TargetInfo(Triple) { 3157 TLSSupported = false; 3158 WCharType = UnsignedShort; 3159 DoubleAlign = LongLongAlign = 64; 3160 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3161 } 3162 void getTargetDefines(const LangOptions &Opts, 3163 MacroBuilder &Builder) const override { 3164 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3165 Builder.defineMacro("_X86_"); 3166 Builder.defineMacro("__CYGWIN__"); 3167 Builder.defineMacro("__CYGWIN32__"); 3168 DefineStd(Builder, "unix", Opts); 3169 if (Opts.CPlusPlus) 3170 Builder.defineMacro("_GNU_SOURCE"); 3171 } 3172 }; 3173 } // end anonymous namespace 3174 3175 namespace { 3176 // x86-32 Haiku target 3177 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3178 public: 3179 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3180 SizeType = UnsignedLong; 3181 IntPtrType = SignedLong; 3182 PtrDiffType = SignedLong; 3183 ProcessIDType = SignedLong; 3184 this->UserLabelPrefix = ""; 3185 this->TLSSupported = false; 3186 } 3187 void getTargetDefines(const LangOptions &Opts, 3188 MacroBuilder &Builder) const override { 3189 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3190 Builder.defineMacro("__INTEL__"); 3191 Builder.defineMacro("__HAIKU__"); 3192 } 3193 }; 3194 } // end anonymous namespace 3195 3196 // RTEMS Target 3197 template<typename Target> 3198 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3199 protected: 3200 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3201 MacroBuilder &Builder) const override { 3202 // RTEMS defines; list based off of gcc output 3203 3204 Builder.defineMacro("__rtems__"); 3205 Builder.defineMacro("__ELF__"); 3206 } 3207 3208 public: 3209 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3210 this->UserLabelPrefix = ""; 3211 3212 switch (Triple.getArch()) { 3213 default: 3214 case llvm::Triple::x86: 3215 // this->MCountName = ".mcount"; 3216 break; 3217 case llvm::Triple::mips: 3218 case llvm::Triple::mipsel: 3219 case llvm::Triple::ppc: 3220 case llvm::Triple::ppc64: 3221 case llvm::Triple::ppc64le: 3222 // this->MCountName = "_mcount"; 3223 break; 3224 case llvm::Triple::arm: 3225 // this->MCountName = "__mcount"; 3226 break; 3227 } 3228 } 3229 }; 3230 3231 namespace { 3232 // x86-32 RTEMS target 3233 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3234 public: 3235 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3236 SizeType = UnsignedLong; 3237 IntPtrType = SignedLong; 3238 PtrDiffType = SignedLong; 3239 this->UserLabelPrefix = ""; 3240 } 3241 void getTargetDefines(const LangOptions &Opts, 3242 MacroBuilder &Builder) const override { 3243 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3244 Builder.defineMacro("__INTEL__"); 3245 Builder.defineMacro("__rtems__"); 3246 } 3247 }; 3248 } // end anonymous namespace 3249 3250 namespace { 3251 // x86-64 generic target 3252 class X86_64TargetInfo : public X86TargetInfo { 3253 public: 3254 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3255 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 3256 LongDoubleWidth = 128; 3257 LongDoubleAlign = 128; 3258 LargeArrayMinWidth = 128; 3259 LargeArrayAlign = 128; 3260 SuitableAlign = 128; 3261 IntMaxType = SignedLong; 3262 UIntMaxType = UnsignedLong; 3263 Int64Type = SignedLong; 3264 RegParmMax = 6; 3265 3266 DescriptionString = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3267 3268 // Use fpret only for long double. 3269 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3270 3271 // Use fp2ret for _Complex long double. 3272 ComplexLongDoubleUsesFP2Ret = true; 3273 3274 // x86-64 has atomics up to 16 bytes. 3275 // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128 3276 // on CPUs with cmpxchg16b 3277 MaxAtomicPromoteWidth = 128; 3278 MaxAtomicInlineWidth = 64; 3279 } 3280 BuiltinVaListKind getBuiltinVaListKind() const override { 3281 return TargetInfo::X86_64ABIBuiltinVaList; 3282 } 3283 3284 int getEHDataRegisterNumber(unsigned RegNo) const override { 3285 if (RegNo == 0) return 0; 3286 if (RegNo == 1) return 1; 3287 return -1; 3288 } 3289 3290 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3291 return (CC == CC_C || 3292 CC == CC_IntelOclBicc || 3293 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3294 } 3295 3296 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3297 return CC_C; 3298 } 3299 3300 }; 3301 } // end anonymous namespace 3302 3303 namespace { 3304 // x86-64 Windows target 3305 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3306 public: 3307 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3308 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3309 WCharType = UnsignedShort; 3310 LongWidth = LongAlign = 32; 3311 DoubleAlign = LongLongAlign = 64; 3312 IntMaxType = SignedLongLong; 3313 UIntMaxType = UnsignedLongLong; 3314 Int64Type = SignedLongLong; 3315 SizeType = UnsignedLongLong; 3316 PtrDiffType = SignedLongLong; 3317 IntPtrType = SignedLongLong; 3318 this->UserLabelPrefix = ""; 3319 } 3320 void getTargetDefines(const LangOptions &Opts, 3321 MacroBuilder &Builder) const override { 3322 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3323 Builder.defineMacro("_WIN64"); 3324 } 3325 BuiltinVaListKind getBuiltinVaListKind() const override { 3326 return TargetInfo::CharPtrBuiltinVaList; 3327 } 3328 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3329 return (CC == CC_C || 3330 CC == CC_IntelOclBicc || 3331 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning; 3332 } 3333 }; 3334 } // end anonymous namespace 3335 3336 namespace { 3337 // x86-64 Windows Visual Studio target 3338 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 3339 public: 3340 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 3341 : WindowsX86_64TargetInfo(Triple) { 3342 LongDoubleWidth = LongDoubleAlign = 64; 3343 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3344 } 3345 void getTargetDefines(const LangOptions &Opts, 3346 MacroBuilder &Builder) const override { 3347 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3348 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3349 Builder.defineMacro("_M_X64"); 3350 Builder.defineMacro("_M_AMD64"); 3351 } 3352 }; 3353 } // end anonymous namespace 3354 3355 namespace { 3356 // x86-64 MinGW target 3357 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3358 public: 3359 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3360 : WindowsX86_64TargetInfo(Triple) {} 3361 void getTargetDefines(const LangOptions &Opts, 3362 MacroBuilder &Builder) const override { 3363 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3364 DefineStd(Builder, "WIN64", Opts); 3365 Builder.defineMacro("__MINGW64__"); 3366 addMinGWDefines(Opts, Builder); 3367 } 3368 }; 3369 } // end anonymous namespace 3370 3371 namespace { 3372 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3373 public: 3374 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3375 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3376 Int64Type = SignedLongLong; 3377 MaxVectorAlign = 256; 3378 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 3379 llvm::Triple T = llvm::Triple(Triple); 3380 if (T.getOS() == llvm::Triple::IOS) 3381 UseSignedCharForObjCBool = false; 3382 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 3383 } 3384 }; 3385 } // end anonymous namespace 3386 3387 namespace { 3388 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3389 public: 3390 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3391 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3392 IntMaxType = SignedLongLong; 3393 UIntMaxType = UnsignedLongLong; 3394 Int64Type = SignedLongLong; 3395 } 3396 }; 3397 } // end anonymous namespace 3398 3399 namespace { 3400 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3401 public: 3402 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3403 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3404 IntMaxType = SignedLongLong; 3405 UIntMaxType = UnsignedLongLong; 3406 Int64Type = SignedLongLong; 3407 } 3408 }; 3409 } 3410 3411 3412 namespace { 3413 class ARMTargetInfo : public TargetInfo { 3414 // Possible FPU choices. 3415 enum FPUMode { 3416 VFP2FPU = (1 << 0), 3417 VFP3FPU = (1 << 1), 3418 VFP4FPU = (1 << 2), 3419 NeonFPU = (1 << 3), 3420 FPARMV8 = (1 << 4) 3421 }; 3422 3423 // Possible HWDiv features. 3424 enum HWDivMode { 3425 HWDivThumb = (1 << 0), 3426 HWDivARM = (1 << 1) 3427 }; 3428 3429 static bool FPUModeIsVFP(FPUMode Mode) { 3430 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 3431 } 3432 3433 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3434 static const char * const GCCRegNames[]; 3435 3436 std::string ABI, CPU; 3437 3438 enum { 3439 FP_Default, 3440 FP_VFP, 3441 FP_Neon 3442 } FPMath; 3443 3444 unsigned FPU : 5; 3445 3446 unsigned IsAAPCS : 1; 3447 unsigned IsThumb : 1; 3448 unsigned HWDiv : 2; 3449 3450 // Initialized via features. 3451 unsigned SoftFloat : 1; 3452 unsigned SoftFloatABI : 1; 3453 3454 unsigned CRC : 1; 3455 unsigned Crypto : 1; 3456 3457 static const Builtin::Info BuiltinInfo[]; 3458 3459 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3460 if (T.isOSWindows()) 3461 return true; 3462 3463 // On linux, binaries targeting old cpus call functions in libgcc to 3464 // perform atomic operations. The implementation in libgcc then calls into 3465 // the kernel which on armv6 and newer uses ldrex and strex. The net result 3466 // is that if we assume the kernel is at least as recent as the hardware, 3467 // it is safe to use atomic instructions on armv6 and newer. 3468 if (!T.isOSLinux() && 3469 T.getOS() != llvm::Triple::FreeBSD && 3470 T.getOS() != llvm::Triple::NetBSD && 3471 T.getOS() != llvm::Triple::Bitrig) 3472 return false; 3473 StringRef ArchName = T.getArchName(); 3474 if (T.getArch() == llvm::Triple::arm || 3475 T.getArch() == llvm::Triple::armeb) { 3476 StringRef VersionStr; 3477 if (ArchName.startswith("armv")) 3478 VersionStr = ArchName.substr(4); 3479 else if (ArchName.startswith("armebv")) 3480 VersionStr = ArchName.substr(6); 3481 else 3482 return false; 3483 unsigned Version; 3484 if (VersionStr.getAsInteger(10, Version)) 3485 return false; 3486 return Version >= 6; 3487 } 3488 assert(T.getArch() == llvm::Triple::thumb || 3489 T.getArch() == llvm::Triple::thumbeb); 3490 StringRef VersionStr; 3491 if (ArchName.startswith("thumbv")) 3492 VersionStr = ArchName.substr(6); 3493 else if (ArchName.startswith("thumbebv")) 3494 VersionStr = ArchName.substr(8); 3495 else 3496 return false; 3497 unsigned Version; 3498 if (VersionStr.getAsInteger(10, Version)) 3499 return false; 3500 return Version >= 7; 3501 } 3502 3503 void setABIAAPCS() { 3504 IsAAPCS = true; 3505 3506 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 3507 const llvm::Triple &T = getTriple(); 3508 3509 // size_t is unsigned long on Darwin and NetBSD. 3510 if (T.isOSDarwin() || T.getOS() == llvm::Triple::NetBSD) 3511 SizeType = UnsignedLong; 3512 else 3513 SizeType = UnsignedInt; 3514 3515 switch (T.getOS()) { 3516 case llvm::Triple::NetBSD: 3517 WCharType = SignedInt; 3518 break; 3519 case llvm::Triple::Win32: 3520 WCharType = UnsignedShort; 3521 break; 3522 case llvm::Triple::Linux: 3523 default: 3524 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3525 WCharType = UnsignedInt; 3526 break; 3527 } 3528 3529 UseBitFieldTypeAlignment = true; 3530 3531 ZeroLengthBitfieldBoundary = 0; 3532 3533 if (IsThumb) { 3534 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3535 // so set preferred for small types to 32. 3536 if (T.isOSBinFormatMachO()) { 3537 DescriptionString = BigEndian ? 3538 "E-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3539 "v128:64:128-a:0:32-n32-S64" : 3540 "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3541 "v128:64:128-a:0:32-n32-S64"; 3542 } else if (T.isOSWindows()) { 3543 // FIXME: this is invalid for WindowsCE 3544 assert(!BigEndian && "Windows on ARM does not support big endian"); 3545 DescriptionString = "e" 3546 "-m:e" 3547 "-p:32:32" 3548 "-i1:8:32-i8:8:32-i16:16:32-i64:64" 3549 "-v128:64:128" 3550 "-a:0:32" 3551 "-n32" 3552 "-S64"; 3553 } else { 3554 DescriptionString = BigEndian ? 3555 "E-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3556 "v128:64:128-a:0:32-n32-S64" : 3557 "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3558 "v128:64:128-a:0:32-n32-S64"; 3559 } 3560 } else { 3561 if (T.isOSBinFormatMachO()) 3562 DescriptionString = BigEndian ? 3563 "E-m:o-p:32:32-i64:64-v128:64:128-n32-S64" : 3564 "e-m:o-p:32:32-i64:64-v128:64:128-n32-S64"; 3565 else 3566 DescriptionString = BigEndian ? 3567 "E-m:e-p:32:32-i64:64-v128:64:128-n32-S64" : 3568 "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64"; 3569 } 3570 3571 // FIXME: Enumerated types are variable width in straight AAPCS. 3572 } 3573 3574 void setABIAPCS() { 3575 const llvm::Triple &T = getTriple(); 3576 3577 IsAAPCS = false; 3578 3579 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 3580 3581 // size_t is unsigned int on FreeBSD. 3582 if (T.getOS() == llvm::Triple::FreeBSD) 3583 SizeType = UnsignedInt; 3584 else 3585 SizeType = UnsignedLong; 3586 3587 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 3588 WCharType = SignedInt; 3589 3590 // Do not respect the alignment of bit-field types when laying out 3591 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 3592 UseBitFieldTypeAlignment = false; 3593 3594 /// gcc forces the alignment to 4 bytes, regardless of the type of the 3595 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 3596 /// gcc. 3597 ZeroLengthBitfieldBoundary = 32; 3598 3599 if (IsThumb) { 3600 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3601 // so set preferred for small types to 32. 3602 if (T.isOSBinFormatMachO()) 3603 DescriptionString = BigEndian ? 3604 "E-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3605 "-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3606 "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3607 "-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3608 else 3609 DescriptionString = BigEndian ? 3610 "E-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3611 "-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3612 "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3613 "-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3614 } else { 3615 if (T.isOSBinFormatMachO()) 3616 DescriptionString = BigEndian ? 3617 "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3618 "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3619 else 3620 DescriptionString = BigEndian ? 3621 "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3622 "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3623 } 3624 3625 // FIXME: Override "preferred align" for double and long long. 3626 } 3627 3628 public: 3629 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 3630 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 3631 IsAAPCS(true) { 3632 BigEndian = IsBigEndian; 3633 3634 switch (getTriple().getOS()) { 3635 case llvm::Triple::NetBSD: 3636 PtrDiffType = SignedLong; 3637 break; 3638 default: 3639 PtrDiffType = SignedInt; 3640 break; 3641 } 3642 3643 // {} in inline assembly are neon specifiers, not assembly variant 3644 // specifiers. 3645 NoAsmVariants = true; 3646 3647 // FIXME: Should we just treat this as a feature? 3648 IsThumb = getTriple().getArchName().startswith("thumb"); 3649 3650 setABI("aapcs-linux"); 3651 3652 // ARM targets default to using the ARM C++ ABI. 3653 TheCXXABI.set(TargetCXXABI::GenericARM); 3654 3655 // ARM has atomics up to 8 bytes 3656 MaxAtomicPromoteWidth = 64; 3657 if (shouldUseInlineAtomic(getTriple())) 3658 MaxAtomicInlineWidth = 64; 3659 3660 // Do force alignment of members that follow zero length bitfields. If 3661 // the alignment of the zero-length bitfield is greater than the member 3662 // that follows it, `bar', `bar' will be aligned as the type of the 3663 // zero length bitfield. 3664 UseZeroLengthBitfieldAlignment = true; 3665 } 3666 StringRef getABI() const override { return ABI; } 3667 bool setABI(const std::string &Name) override { 3668 ABI = Name; 3669 3670 // The defaults (above) are for AAPCS, check if we need to change them. 3671 // 3672 // FIXME: We need support for -meabi... we could just mangle it into the 3673 // name. 3674 if (Name == "apcs-gnu") { 3675 setABIAPCS(); 3676 return true; 3677 } 3678 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 3679 setABIAAPCS(); 3680 return true; 3681 } 3682 return false; 3683 } 3684 3685 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 3686 if (IsAAPCS) 3687 Features["aapcs"] = true; 3688 else 3689 Features["apcs"] = true; 3690 3691 StringRef ArchName = getTriple().getArchName(); 3692 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 3693 Features["vfp2"] = true; 3694 else if (CPU == "cortex-a8" || CPU == "cortex-a9" || 3695 CPU == "cortex-a9-mp") { 3696 Features["vfp3"] = true; 3697 Features["neon"] = true; 3698 } 3699 else if (CPU == "cortex-a5") { 3700 Features["vfp4"] = true; 3701 Features["neon"] = true; 3702 } else if (CPU == "swift" || CPU == "cortex-a7" || 3703 CPU == "cortex-a12" || CPU == "cortex-a15" || 3704 CPU == "krait") { 3705 Features["vfp4"] = true; 3706 Features["neon"] = true; 3707 Features["hwdiv"] = true; 3708 Features["hwdiv-arm"] = true; 3709 } else if (CPU == "cyclone") { 3710 Features["v8fp"] = true; 3711 Features["neon"] = true; 3712 Features["hwdiv"] = true; 3713 Features["hwdiv-arm"] = true; 3714 } else if (CPU == "cortex-a53" || CPU == "cortex-a57") { 3715 Features["fp-armv8"] = true; 3716 Features["neon"] = true; 3717 Features["hwdiv"] = true; 3718 Features["hwdiv-arm"] = true; 3719 Features["crc"] = true; 3720 Features["crypto"] = true; 3721 } else if (CPU == "cortex-r5" || 3722 // Enable the hwdiv extension for all v8a AArch32 cores by 3723 // default. 3724 ArchName == "armv8a" || ArchName == "armv8" || 3725 ArchName == "armebv8a" || ArchName == "armebv8" || 3726 ArchName == "thumbv8a" || ArchName == "thumbv8" || 3727 ArchName == "thumbebv8a" || ArchName == "thumbebv8") { 3728 Features["hwdiv"] = true; 3729 Features["hwdiv-arm"] = true; 3730 } else if (CPU == "cortex-m3" || CPU == "cortex-m4") { 3731 Features["hwdiv"] = true; 3732 } 3733 } 3734 3735 bool handleTargetFeatures(std::vector<std::string> &Features, 3736 DiagnosticsEngine &Diags) override { 3737 FPU = 0; 3738 CRC = 0; 3739 Crypto = 0; 3740 SoftFloat = SoftFloatABI = false; 3741 HWDiv = 0; 3742 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3743 if (Features[i] == "+soft-float") 3744 SoftFloat = true; 3745 else if (Features[i] == "+soft-float-abi") 3746 SoftFloatABI = true; 3747 else if (Features[i] == "+vfp2") 3748 FPU |= VFP2FPU; 3749 else if (Features[i] == "+vfp3") 3750 FPU |= VFP3FPU; 3751 else if (Features[i] == "+vfp4") 3752 FPU |= VFP4FPU; 3753 else if (Features[i] == "+fp-armv8") 3754 FPU |= FPARMV8; 3755 else if (Features[i] == "+neon") 3756 FPU |= NeonFPU; 3757 else if (Features[i] == "+hwdiv") 3758 HWDiv |= HWDivThumb; 3759 else if (Features[i] == "+hwdiv-arm") 3760 HWDiv |= HWDivARM; 3761 else if (Features[i] == "+crc") 3762 CRC = 1; 3763 else if (Features[i] == "+crypto") 3764 Crypto = 1; 3765 } 3766 3767 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 3768 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 3769 return false; 3770 } 3771 3772 if (FPMath == FP_Neon) 3773 Features.push_back("+neonfp"); 3774 else if (FPMath == FP_VFP) 3775 Features.push_back("-neonfp"); 3776 3777 // Remove front-end specific options which the backend handles differently. 3778 std::vector<std::string>::iterator it; 3779 it = std::find(Features.begin(), Features.end(), "+soft-float"); 3780 if (it != Features.end()) 3781 Features.erase(it); 3782 it = std::find(Features.begin(), Features.end(), "+soft-float-abi"); 3783 if (it != Features.end()) 3784 Features.erase(it); 3785 return true; 3786 } 3787 3788 bool hasFeature(StringRef Feature) const override { 3789 return llvm::StringSwitch<bool>(Feature) 3790 .Case("arm", true) 3791 .Case("softfloat", SoftFloat) 3792 .Case("thumb", IsThumb) 3793 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 3794 .Case("hwdiv", HWDiv & HWDivThumb) 3795 .Case("hwdiv-arm", HWDiv & HWDivARM) 3796 .Default(false); 3797 } 3798 // FIXME: Should we actually have some table instead of these switches? 3799 static const char *getCPUDefineSuffix(StringRef Name) { 3800 return llvm::StringSwitch<const char*>(Name) 3801 .Cases("arm8", "arm810", "4") 3802 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") 3803 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 3804 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 3805 .Case("ep9312", "4T") 3806 .Cases("arm10tdmi", "arm1020t", "5T") 3807 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 3808 .Case("arm926ej-s", "5TEJ") 3809 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 3810 .Cases("xscale", "iwmmxt", "5TE") 3811 .Case("arm1136j-s", "6J") 3812 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 3813 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 3814 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 3815 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "cortex-a9-mp", "7A") 3816 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "7A") 3817 .Cases("cortex-r4", "cortex-r5", "7R") 3818 .Case("swift", "7S") 3819 .Case("cyclone", "8A") 3820 .Cases("cortex-m3", "cortex-m4", "7M") 3821 .Case("cortex-m0", "6M") 3822 .Cases("cortex-a53", "cortex-a57", "8A") 3823 .Default(nullptr); 3824 } 3825 static const char *getCPUProfile(StringRef Name) { 3826 return llvm::StringSwitch<const char*>(Name) 3827 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A") 3828 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "A") 3829 .Cases("cortex-a53", "cortex-a57", "A") 3830 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M") 3831 .Cases("cortex-r4", "cortex-r5", "R") 3832 .Default(""); 3833 } 3834 bool setCPU(const std::string &Name) override { 3835 if (!getCPUDefineSuffix(Name)) 3836 return false; 3837 3838 CPU = Name; 3839 return true; 3840 } 3841 bool setFPMath(StringRef Name) override; 3842 bool supportsThumb(StringRef ArchName, StringRef CPUArch, 3843 unsigned CPUArchVer) const { 3844 return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) || 3845 (CPUArch.find('M') != StringRef::npos); 3846 } 3847 bool supportsThumb2(StringRef ArchName, StringRef CPUArch, 3848 unsigned CPUArchVer) const { 3849 // We check both CPUArchVer and ArchName because when only triple is 3850 // specified, the default CPU is arm1136j-s. 3851 return ArchName.endswith("v6t2") || ArchName.endswith("v7") || 3852 ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7; 3853 } 3854 void getTargetDefines(const LangOptions &Opts, 3855 MacroBuilder &Builder) const override { 3856 // Target identification. 3857 Builder.defineMacro("__arm"); 3858 Builder.defineMacro("__arm__"); 3859 3860 // Target properties. 3861 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3862 3863 StringRef CPUArch = getCPUDefineSuffix(CPU); 3864 unsigned int CPUArchVer; 3865 if(CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) { 3866 llvm_unreachable("Invalid char for architecture version number"); 3867 } 3868 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 3869 3870 // ACLE 6.4.1 ARM/Thumb instruction set architecture 3871 StringRef CPUProfile = getCPUProfile(CPU); 3872 StringRef ArchName = getTriple().getArchName(); 3873 3874 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 3875 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 3876 3877 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 3878 // is not defined for the M-profile. 3879 // NOTE that the deffault profile is assumed to be 'A' 3880 if (CPUProfile.empty() || CPUProfile != "M") 3881 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 3882 3883 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 3884 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 3885 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 3886 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 3887 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 3888 else if (supportsThumb(ArchName, CPUArch, CPUArchVer)) 3889 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 3890 3891 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 3892 // instruction set such as ARM or Thumb. 3893 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 3894 3895 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 3896 3897 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 3898 if (!CPUProfile.empty()) 3899 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 3900 3901 // Subtarget options. 3902 3903 // FIXME: It's more complicated than this and we don't really support 3904 // interworking. 3905 // Windows on ARM does not "support" interworking 3906 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows()) 3907 Builder.defineMacro("__THUMB_INTERWORK__"); 3908 3909 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 3910 // Embedded targets on Darwin follow AAPCS, but not EABI. 3911 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 3912 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 3913 Builder.defineMacro("__ARM_EABI__"); 3914 Builder.defineMacro("__ARM_PCS", "1"); 3915 3916 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 3917 Builder.defineMacro("__ARM_PCS_VFP", "1"); 3918 } 3919 3920 if (SoftFloat) 3921 Builder.defineMacro("__SOFTFP__"); 3922 3923 if (CPU == "xscale") 3924 Builder.defineMacro("__XSCALE__"); 3925 3926 if (IsThumb) { 3927 Builder.defineMacro("__THUMBEL__"); 3928 Builder.defineMacro("__thumb__"); 3929 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 3930 Builder.defineMacro("__thumb2__"); 3931 } 3932 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 3933 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 3934 3935 // Note, this is always on in gcc, even though it doesn't make sense. 3936 Builder.defineMacro("__APCS_32__"); 3937 3938 if (FPUModeIsVFP((FPUMode) FPU)) { 3939 Builder.defineMacro("__VFP_FP__"); 3940 if (FPU & VFP2FPU) 3941 Builder.defineMacro("__ARM_VFPV2__"); 3942 if (FPU & VFP3FPU) 3943 Builder.defineMacro("__ARM_VFPV3__"); 3944 if (FPU & VFP4FPU) 3945 Builder.defineMacro("__ARM_VFPV4__"); 3946 } 3947 3948 // This only gets set when Neon instructions are actually available, unlike 3949 // the VFP define, hence the soft float and arch check. This is subtly 3950 // different from gcc, we follow the intent which was that it should be set 3951 // when Neon instructions are actually available. 3952 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) { 3953 Builder.defineMacro("__ARM_NEON"); 3954 Builder.defineMacro("__ARM_NEON__"); 3955 } 3956 3957 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 3958 Opts.ShortWChar ? "2" : "4"); 3959 3960 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 3961 Opts.ShortEnums ? "1" : "4"); 3962 3963 if (CRC) 3964 Builder.defineMacro("__ARM_FEATURE_CRC32"); 3965 3966 if (Crypto) 3967 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 3968 3969 if (CPUArchVer >= 6 && CPUArch != "6M") { 3970 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3971 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3972 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3973 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3974 } 3975 } 3976 void getTargetBuiltins(const Builtin::Info *&Records, 3977 unsigned &NumRecords) const override { 3978 Records = BuiltinInfo; 3979 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 3980 } 3981 bool isCLZForZeroUndef() const override { return false; } 3982 BuiltinVaListKind getBuiltinVaListKind() const override { 3983 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 3984 } 3985 void getGCCRegNames(const char * const *&Names, 3986 unsigned &NumNames) const override; 3987 void getGCCRegAliases(const GCCRegAlias *&Aliases, 3988 unsigned &NumAliases) const override; 3989 bool validateAsmConstraint(const char *&Name, 3990 TargetInfo::ConstraintInfo &Info) const override { 3991 switch (*Name) { 3992 default: break; 3993 case 'l': // r0-r7 3994 case 'h': // r8-r15 3995 case 'w': // VFP Floating point register single precision 3996 case 'P': // VFP Floating point register double precision 3997 Info.setAllowsRegister(); 3998 return true; 3999 case 'Q': // A memory address that is a single base register. 4000 Info.setAllowsMemory(); 4001 return true; 4002 case 'U': // a memory reference... 4003 switch (Name[1]) { 4004 case 'q': // ...ARMV4 ldrsb 4005 case 'v': // ...VFP load/store (reg+constant offset) 4006 case 'y': // ...iWMMXt load/store 4007 case 't': // address valid for load/store opaque types wider 4008 // than 128-bits 4009 case 'n': // valid address for Neon doubleword vector load/store 4010 case 'm': // valid address for Neon element and structure load/store 4011 case 's': // valid address for non-offset loads/stores of quad-word 4012 // values in four ARM registers 4013 Info.setAllowsMemory(); 4014 Name++; 4015 return true; 4016 } 4017 } 4018 return false; 4019 } 4020 std::string convertConstraint(const char *&Constraint) const override { 4021 std::string R; 4022 switch (*Constraint) { 4023 case 'U': // Two-character constraint; add "^" hint for later parsing. 4024 R = std::string("^") + std::string(Constraint, 2); 4025 Constraint++; 4026 break; 4027 case 'p': // 'p' should be translated to 'r' by default. 4028 R = std::string("r"); 4029 break; 4030 default: 4031 return std::string(1, *Constraint); 4032 } 4033 return R; 4034 } 4035 bool validateConstraintModifier(StringRef Constraint, const char Modifier, 4036 unsigned Size) const override { 4037 bool isOutput = (Constraint[0] == '='); 4038 bool isInOut = (Constraint[0] == '+'); 4039 4040 // Strip off constraint modifiers. 4041 while (Constraint[0] == '=' || 4042 Constraint[0] == '+' || 4043 Constraint[0] == '&') 4044 Constraint = Constraint.substr(1); 4045 4046 switch (Constraint[0]) { 4047 default: break; 4048 case 'r': { 4049 switch (Modifier) { 4050 default: 4051 return (isInOut || isOutput || Size <= 64); 4052 case 'q': 4053 // A register of size 32 cannot fit a vector type. 4054 return false; 4055 } 4056 } 4057 } 4058 4059 return true; 4060 } 4061 const char *getClobbers() const override { 4062 // FIXME: Is this really right? 4063 return ""; 4064 } 4065 4066 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4067 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4068 } 4069 4070 int getEHDataRegisterNumber(unsigned RegNo) const override { 4071 if (RegNo == 0) return 0; 4072 if (RegNo == 1) return 1; 4073 return -1; 4074 } 4075 }; 4076 4077 bool ARMTargetInfo::setFPMath(StringRef Name) { 4078 if (Name == "neon") { 4079 FPMath = FP_Neon; 4080 return true; 4081 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4082 Name == "vfp4") { 4083 FPMath = FP_VFP; 4084 return true; 4085 } 4086 return false; 4087 } 4088 4089 const char * const ARMTargetInfo::GCCRegNames[] = { 4090 // Integer registers 4091 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4092 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4093 4094 // Float registers 4095 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4096 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4097 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4098 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4099 4100 // Double registers 4101 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4102 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4103 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4104 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4105 4106 // Quad registers 4107 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4108 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4109 }; 4110 4111 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4112 unsigned &NumNames) const { 4113 Names = GCCRegNames; 4114 NumNames = llvm::array_lengthof(GCCRegNames); 4115 } 4116 4117 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4118 { { "a1" }, "r0" }, 4119 { { "a2" }, "r1" }, 4120 { { "a3" }, "r2" }, 4121 { { "a4" }, "r3" }, 4122 { { "v1" }, "r4" }, 4123 { { "v2" }, "r5" }, 4124 { { "v3" }, "r6" }, 4125 { { "v4" }, "r7" }, 4126 { { "v5" }, "r8" }, 4127 { { "v6", "rfp" }, "r9" }, 4128 { { "sl" }, "r10" }, 4129 { { "fp" }, "r11" }, 4130 { { "ip" }, "r12" }, 4131 { { "r13" }, "sp" }, 4132 { { "r14" }, "lr" }, 4133 { { "r15" }, "pc" }, 4134 // The S, D and Q registers overlap, but aren't really aliases; we 4135 // don't want to substitute one of these for a different-sized one. 4136 }; 4137 4138 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4139 unsigned &NumAliases) const { 4140 Aliases = GCCRegAliases; 4141 NumAliases = llvm::array_lengthof(GCCRegAliases); 4142 } 4143 4144 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4145 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4146 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4147 ALL_LANGUAGES }, 4148 #include "clang/Basic/BuiltinsNEON.def" 4149 4150 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4151 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4152 ALL_LANGUAGES }, 4153 #include "clang/Basic/BuiltinsARM.def" 4154 }; 4155 4156 class ARMleTargetInfo : public ARMTargetInfo { 4157 public: 4158 ARMleTargetInfo(const llvm::Triple &Triple) 4159 : ARMTargetInfo(Triple, false) { } 4160 virtual void getTargetDefines(const LangOptions &Opts, 4161 MacroBuilder &Builder) const { 4162 Builder.defineMacro("__ARMEL__"); 4163 ARMTargetInfo::getTargetDefines(Opts, Builder); 4164 } 4165 }; 4166 4167 class ARMbeTargetInfo : public ARMTargetInfo { 4168 public: 4169 ARMbeTargetInfo(const llvm::Triple &Triple) 4170 : ARMTargetInfo(Triple, true) { } 4171 virtual void getTargetDefines(const LangOptions &Opts, 4172 MacroBuilder &Builder) const { 4173 Builder.defineMacro("__ARMEB__"); 4174 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4175 ARMTargetInfo::getTargetDefines(Opts, Builder); 4176 } 4177 }; 4178 } // end anonymous namespace. 4179 4180 namespace { 4181 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 4182 const llvm::Triple Triple; 4183 public: 4184 WindowsARMTargetInfo(const llvm::Triple &Triple) 4185 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 4186 TLSSupported = false; 4187 WCharType = UnsignedShort; 4188 SizeType = UnsignedInt; 4189 UserLabelPrefix = ""; 4190 } 4191 void getVisualStudioDefines(const LangOptions &Opts, 4192 MacroBuilder &Builder) const { 4193 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 4194 4195 // FIXME: this is invalid for WindowsCE 4196 Builder.defineMacro("_M_ARM_NT", "1"); 4197 Builder.defineMacro("_M_ARMT", "_M_ARM"); 4198 Builder.defineMacro("_M_THUMB", "_M_ARM"); 4199 4200 assert((Triple.getArch() == llvm::Triple::arm || 4201 Triple.getArch() == llvm::Triple::thumb) && 4202 "invalid architecture for Windows ARM target info"); 4203 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 4204 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 4205 4206 // TODO map the complete set of values 4207 // 31: VFPv3 40: VFPv4 4208 Builder.defineMacro("_M_ARM_FP", "31"); 4209 } 4210 }; 4211 4212 // Windows ARM + Itanium C++ ABI Target 4213 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 4214 public: 4215 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 4216 : WindowsARMTargetInfo(Triple) { 4217 TheCXXABI.set(TargetCXXABI::GenericARM); 4218 } 4219 4220 void getTargetDefines(const LangOptions &Opts, 4221 MacroBuilder &Builder) const override { 4222 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4223 4224 if (Opts.MSVCCompat) 4225 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4226 } 4227 }; 4228 4229 // Windows ARM, MS (C++) ABI 4230 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 4231 public: 4232 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 4233 : WindowsARMTargetInfo(Triple) { 4234 TheCXXABI.set(TargetCXXABI::Microsoft); 4235 } 4236 4237 void getTargetDefines(const LangOptions &Opts, 4238 MacroBuilder &Builder) const override { 4239 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4240 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4241 } 4242 }; 4243 } 4244 4245 4246 namespace { 4247 class DarwinARMTargetInfo : 4248 public DarwinTargetInfo<ARMleTargetInfo> { 4249 protected: 4250 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4251 MacroBuilder &Builder) const override { 4252 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4253 } 4254 4255 public: 4256 DarwinARMTargetInfo(const llvm::Triple &Triple) 4257 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 4258 HasAlignMac68kSupport = true; 4259 // iOS always has 64-bit atomic instructions. 4260 // FIXME: This should be based off of the target features in ARMleTargetInfo. 4261 MaxAtomicInlineWidth = 64; 4262 4263 // Darwin on iOS uses a variant of the ARM C++ ABI. 4264 TheCXXABI.set(TargetCXXABI::iOS); 4265 } 4266 }; 4267 } // end anonymous namespace. 4268 4269 4270 namespace { 4271 class AArch64TargetInfo : public TargetInfo { 4272 virtual void setDescriptionString() = 0; 4273 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4274 static const char *const GCCRegNames[]; 4275 4276 enum FPUModeEnum { 4277 FPUMode, 4278 NeonMode 4279 }; 4280 4281 std::string CPU; 4282 unsigned FPU; 4283 unsigned CRC; 4284 unsigned Crypto; 4285 4286 static const Builtin::Info BuiltinInfo[]; 4287 4288 std::string ABI; 4289 4290 public: 4291 AArch64TargetInfo(const llvm::Triple &Triple) 4292 : TargetInfo(Triple), ABI("aapcs") { 4293 4294 if (getTriple().getOS() == llvm::Triple::NetBSD) { 4295 WCharType = SignedInt; 4296 4297 // NetBSD apparently prefers consistency across ARM targets to consistency 4298 // across 64-bit targets. 4299 Int64Type = SignedLongLong; 4300 IntMaxType = SignedLongLong; 4301 UIntMaxType = UnsignedLongLong; 4302 } else { 4303 WCharType = UnsignedInt; 4304 Int64Type = SignedLong; 4305 IntMaxType = SignedLong; 4306 UIntMaxType = UnsignedLong; 4307 } 4308 4309 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4310 MaxVectorAlign = 128; 4311 RegParmMax = 8; 4312 MaxAtomicInlineWidth = 128; 4313 MaxAtomicPromoteWidth = 128; 4314 4315 LongDoubleWidth = LongDoubleAlign = 128; 4316 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4317 4318 // {} in inline assembly are neon specifiers, not assembly variant 4319 // specifiers. 4320 NoAsmVariants = true; 4321 4322 // AArch64 targets default to using the ARM C++ ABI. 4323 TheCXXABI.set(TargetCXXABI::GenericAArch64); 4324 } 4325 4326 StringRef getABI() const override { return ABI; } 4327 virtual bool setABI(const std::string &Name) { 4328 if (Name != "aapcs" && Name != "darwinpcs") 4329 return false; 4330 4331 ABI = Name; 4332 return true; 4333 } 4334 4335 virtual bool setCPU(const std::string &Name) { 4336 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4337 .Case("generic", true) 4338 .Cases("cortex-a53", "cortex-a57", true) 4339 .Case("cyclone", true) 4340 .Default(false); 4341 if (CPUKnown) 4342 CPU = Name; 4343 return CPUKnown; 4344 } 4345 4346 virtual void getTargetDefines(const LangOptions &Opts, 4347 MacroBuilder &Builder) const { 4348 // Target identification. 4349 Builder.defineMacro("__aarch64__"); 4350 4351 // Target properties. 4352 Builder.defineMacro("_LP64"); 4353 Builder.defineMacro("__LP64__"); 4354 4355 // ACLE predefines. Many can only have one possible value on v8 AArch64. 4356 Builder.defineMacro("__ARM_ACLE", "200"); 4357 Builder.defineMacro("__ARM_ARCH", "8"); 4358 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 4359 4360 Builder.defineMacro("__ARM_64BIT_STATE"); 4361 Builder.defineMacro("__ARM_PCS_AAPCS64"); 4362 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 4363 4364 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 4365 Builder.defineMacro("__ARM_FEATURE_CLZ"); 4366 Builder.defineMacro("__ARM_FEATURE_FMA"); 4367 Builder.defineMacro("__ARM_FEATURE_DIV"); 4368 4369 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 4370 4371 // 0xe implies support for half, single and double precision operations. 4372 Builder.defineMacro("__ARM_FP", "0xe"); 4373 4374 // PCS specifies this for SysV variants, which is all we support. Other ABIs 4375 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 4376 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 4377 4378 if (Opts.FastMath || Opts.FiniteMathOnly) 4379 Builder.defineMacro("__ARM_FP_FAST"); 4380 4381 if ((Opts.C99 || Opts.C11) && !Opts.Freestanding) 4382 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 4383 4384 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 4385 4386 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4387 Opts.ShortEnums ? "1" : "4"); 4388 4389 if (FPU == NeonMode) { 4390 Builder.defineMacro("__ARM_NEON"); 4391 // 64-bit NEON supports half, single and double precision operations. 4392 Builder.defineMacro("__ARM_NEON_FP", "0xe"); 4393 } 4394 4395 if (CRC) 4396 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4397 4398 if (Crypto) 4399 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4400 } 4401 4402 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4403 unsigned &NumRecords) const { 4404 Records = BuiltinInfo; 4405 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin; 4406 } 4407 4408 virtual bool hasFeature(StringRef Feature) const { 4409 return Feature == "aarch64" || 4410 Feature == "arm64" || 4411 (Feature == "neon" && FPU == NeonMode); 4412 } 4413 4414 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 4415 4416 if (CPU == "cyclone") { 4417 Features["fp-armv8"] = true; 4418 Features["neon"] = true; 4419 Features["crypto"] = true; 4420 Features["crc"] = true; 4421 Features["zcm"] = true; 4422 Features["zcz"] = true; 4423 } else if (CPU == "cortex-a53" || CPU == "cortex-a57") { 4424 Features["fp-armv8"] = true; 4425 Features["neon"] = true; 4426 Features["crypto"] = true; 4427 Features["crc"] = true; 4428 } 4429 } 4430 4431 bool handleTargetFeatures(std::vector<std::string> &Features, 4432 DiagnosticsEngine &Diags) override { 4433 FPU = FPUMode; 4434 CRC = 0; 4435 Crypto = 0; 4436 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 4437 if (Features[i] == "+neon") 4438 FPU = NeonMode; 4439 if (Features[i] == "+crc") 4440 CRC = 1; 4441 if (Features[i] == "+crypto") 4442 Crypto = 1; 4443 } 4444 4445 setDescriptionString(); 4446 4447 return true; 4448 } 4449 4450 virtual bool isCLZForZeroUndef() const { return false; } 4451 4452 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4453 return TargetInfo::AArch64ABIBuiltinVaList; 4454 } 4455 4456 virtual void getGCCRegNames(const char *const *&Names, 4457 unsigned &NumNames) const; 4458 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4459 unsigned &NumAliases) const; 4460 4461 virtual bool validateAsmConstraint(const char *&Name, 4462 TargetInfo::ConstraintInfo &Info) const { 4463 switch (*Name) { 4464 default: 4465 return false; 4466 case 'w': // Floating point and SIMD registers (V0-V31) 4467 Info.setAllowsRegister(); 4468 return true; 4469 case 'I': // Constant that can be used with an ADD instruction 4470 case 'J': // Constant that can be used with a SUB instruction 4471 case 'K': // Constant that can be used with a 32-bit logical instruction 4472 case 'L': // Constant that can be used with a 64-bit logical instruction 4473 case 'M': // Constant that can be used as a 32-bit MOV immediate 4474 case 'N': // Constant that can be used as a 64-bit MOV immediate 4475 case 'Y': // Floating point constant zero 4476 case 'Z': // Integer constant zero 4477 return true; 4478 case 'Q': // A memory reference with base register and no offset 4479 Info.setAllowsMemory(); 4480 return true; 4481 case 'S': // A symbolic address 4482 Info.setAllowsRegister(); 4483 return true; 4484 case 'U': 4485 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be 4486 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be 4487 // Usa: An absolute symbolic address 4488 // Ush: The high part (bits 32:12) of a pc-relative symbolic address 4489 llvm_unreachable("FIXME: Unimplemented support for bizarre constraints"); 4490 case 'z': // Zero register, wzr or xzr 4491 Info.setAllowsRegister(); 4492 return true; 4493 case 'x': // Floating point and SIMD registers (V0-V15) 4494 Info.setAllowsRegister(); 4495 return true; 4496 } 4497 return false; 4498 } 4499 4500 virtual const char *getClobbers() const { return ""; } 4501 4502 int getEHDataRegisterNumber(unsigned RegNo) const { 4503 if (RegNo == 0) 4504 return 0; 4505 if (RegNo == 1) 4506 return 1; 4507 return -1; 4508 } 4509 }; 4510 4511 const char *const AArch64TargetInfo::GCCRegNames[] = { 4512 // 32-bit Integer registers 4513 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 4514 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 4515 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 4516 4517 // 64-bit Integer registers 4518 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 4519 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 4520 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 4521 4522 // 32-bit floating point regsisters 4523 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 4524 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 4525 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4526 4527 // 64-bit floating point regsisters 4528 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 4529 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 4530 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4531 4532 // Vector registers 4533 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 4534 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 4535 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 4536 }; 4537 4538 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names, 4539 unsigned &NumNames) const { 4540 Names = GCCRegNames; 4541 NumNames = llvm::array_lengthof(GCCRegNames); 4542 } 4543 4544 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 4545 { { "w31" }, "wsp" }, 4546 { { "x29" }, "fp" }, 4547 { { "x30" }, "lr" }, 4548 { { "x31" }, "sp" }, 4549 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 4550 // don't want to substitute one of these for a different-sized one. 4551 }; 4552 4553 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4554 unsigned &NumAliases) const { 4555 Aliases = GCCRegAliases; 4556 NumAliases = llvm::array_lengthof(GCCRegAliases); 4557 } 4558 4559 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 4560 #define BUILTIN(ID, TYPE, ATTRS) \ 4561 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4562 #include "clang/Basic/BuiltinsNEON.def" 4563 4564 #define BUILTIN(ID, TYPE, ATTRS) \ 4565 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4566 #include "clang/Basic/BuiltinsAArch64.def" 4567 }; 4568 4569 class AArch64leTargetInfo : public AArch64TargetInfo { 4570 void setDescriptionString() override { 4571 if (getTriple().isOSBinFormatMachO()) 4572 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128"; 4573 else 4574 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 4575 } 4576 4577 public: 4578 AArch64leTargetInfo(const llvm::Triple &Triple) 4579 : AArch64TargetInfo(Triple) { 4580 BigEndian = false; 4581 } 4582 void getTargetDefines(const LangOptions &Opts, 4583 MacroBuilder &Builder) const override { 4584 Builder.defineMacro("__AARCH64EL__"); 4585 AArch64TargetInfo::getTargetDefines(Opts, Builder); 4586 } 4587 }; 4588 4589 class AArch64beTargetInfo : public AArch64TargetInfo { 4590 void setDescriptionString() override { 4591 assert(!getTriple().isOSBinFormatMachO()); 4592 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128"; 4593 } 4594 4595 public: 4596 AArch64beTargetInfo(const llvm::Triple &Triple) 4597 : AArch64TargetInfo(Triple) { } 4598 void getTargetDefines(const LangOptions &Opts, 4599 MacroBuilder &Builder) const override { 4600 Builder.defineMacro("__AARCH64EB__"); 4601 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 4602 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4603 AArch64TargetInfo::getTargetDefines(Opts, Builder); 4604 } 4605 }; 4606 } // end anonymous namespace. 4607 4608 namespace { 4609 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 4610 protected: 4611 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4612 MacroBuilder &Builder) const override { 4613 Builder.defineMacro("__AARCH64_SIMD__"); 4614 Builder.defineMacro("__ARM64_ARCH_8__"); 4615 Builder.defineMacro("__ARM_NEON__"); 4616 Builder.defineMacro("__LITTLE_ENDIAN__"); 4617 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4618 Builder.defineMacro("__arm64", "1"); 4619 Builder.defineMacro("__arm64__", "1"); 4620 4621 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4622 } 4623 4624 public: 4625 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 4626 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 4627 Int64Type = SignedLongLong; 4628 WCharType = SignedInt; 4629 UseSignedCharForObjCBool = false; 4630 4631 LongDoubleWidth = LongDoubleAlign = 64; 4632 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4633 4634 TheCXXABI.set(TargetCXXABI::iOS64); 4635 } 4636 4637 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4638 return TargetInfo::CharPtrBuiltinVaList; 4639 } 4640 }; 4641 } // end anonymous namespace 4642 4643 namespace { 4644 // Hexagon abstract base class 4645 class HexagonTargetInfo : public TargetInfo { 4646 static const Builtin::Info BuiltinInfo[]; 4647 static const char * const GCCRegNames[]; 4648 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4649 std::string CPU; 4650 public: 4651 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4652 BigEndian = false; 4653 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 4654 4655 // {} in inline assembly are packet specifiers, not assembly variant 4656 // specifiers. 4657 NoAsmVariants = true; 4658 } 4659 4660 void getTargetBuiltins(const Builtin::Info *&Records, 4661 unsigned &NumRecords) const override { 4662 Records = BuiltinInfo; 4663 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 4664 } 4665 4666 bool validateAsmConstraint(const char *&Name, 4667 TargetInfo::ConstraintInfo &Info) const override { 4668 return true; 4669 } 4670 4671 void getTargetDefines(const LangOptions &Opts, 4672 MacroBuilder &Builder) const override; 4673 4674 bool hasFeature(StringRef Feature) const override { 4675 return Feature == "hexagon"; 4676 } 4677 4678 BuiltinVaListKind getBuiltinVaListKind() const override { 4679 return TargetInfo::CharPtrBuiltinVaList; 4680 } 4681 void getGCCRegNames(const char * const *&Names, 4682 unsigned &NumNames) const override; 4683 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4684 unsigned &NumAliases) const override; 4685 const char *getClobbers() const override { 4686 return ""; 4687 } 4688 4689 static const char *getHexagonCPUSuffix(StringRef Name) { 4690 return llvm::StringSwitch<const char*>(Name) 4691 .Case("hexagonv4", "4") 4692 .Case("hexagonv5", "5") 4693 .Default(nullptr); 4694 } 4695 4696 bool setCPU(const std::string &Name) override { 4697 if (!getHexagonCPUSuffix(Name)) 4698 return false; 4699 4700 CPU = Name; 4701 return true; 4702 } 4703 }; 4704 4705 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 4706 MacroBuilder &Builder) const { 4707 Builder.defineMacro("qdsp6"); 4708 Builder.defineMacro("__qdsp6", "1"); 4709 Builder.defineMacro("__qdsp6__", "1"); 4710 4711 Builder.defineMacro("hexagon"); 4712 Builder.defineMacro("__hexagon", "1"); 4713 Builder.defineMacro("__hexagon__", "1"); 4714 4715 if(CPU == "hexagonv1") { 4716 Builder.defineMacro("__HEXAGON_V1__"); 4717 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 4718 if(Opts.HexagonQdsp6Compat) { 4719 Builder.defineMacro("__QDSP6_V1__"); 4720 Builder.defineMacro("__QDSP6_ARCH__", "1"); 4721 } 4722 } 4723 else if(CPU == "hexagonv2") { 4724 Builder.defineMacro("__HEXAGON_V2__"); 4725 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 4726 if(Opts.HexagonQdsp6Compat) { 4727 Builder.defineMacro("__QDSP6_V2__"); 4728 Builder.defineMacro("__QDSP6_ARCH__", "2"); 4729 } 4730 } 4731 else if(CPU == "hexagonv3") { 4732 Builder.defineMacro("__HEXAGON_V3__"); 4733 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 4734 if(Opts.HexagonQdsp6Compat) { 4735 Builder.defineMacro("__QDSP6_V3__"); 4736 Builder.defineMacro("__QDSP6_ARCH__", "3"); 4737 } 4738 } 4739 else if(CPU == "hexagonv4") { 4740 Builder.defineMacro("__HEXAGON_V4__"); 4741 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 4742 if(Opts.HexagonQdsp6Compat) { 4743 Builder.defineMacro("__QDSP6_V4__"); 4744 Builder.defineMacro("__QDSP6_ARCH__", "4"); 4745 } 4746 } 4747 else if(CPU == "hexagonv5") { 4748 Builder.defineMacro("__HEXAGON_V5__"); 4749 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 4750 if(Opts.HexagonQdsp6Compat) { 4751 Builder.defineMacro("__QDSP6_V5__"); 4752 Builder.defineMacro("__QDSP6_ARCH__", "5"); 4753 } 4754 } 4755 } 4756 4757 const char * const HexagonTargetInfo::GCCRegNames[] = { 4758 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4759 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4760 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4761 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 4762 "p0", "p1", "p2", "p3", 4763 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 4764 }; 4765 4766 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 4767 unsigned &NumNames) const { 4768 Names = GCCRegNames; 4769 NumNames = llvm::array_lengthof(GCCRegNames); 4770 } 4771 4772 4773 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 4774 { { "sp" }, "r29" }, 4775 { { "fp" }, "r30" }, 4776 { { "lr" }, "r31" }, 4777 }; 4778 4779 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4780 unsigned &NumAliases) const { 4781 Aliases = GCCRegAliases; 4782 NumAliases = llvm::array_lengthof(GCCRegAliases); 4783 } 4784 4785 4786 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 4787 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4788 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4789 ALL_LANGUAGES }, 4790 #include "clang/Basic/BuiltinsHexagon.def" 4791 }; 4792 } 4793 4794 4795 namespace { 4796 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 4797 class SparcTargetInfo : public TargetInfo { 4798 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4799 static const char * const GCCRegNames[]; 4800 bool SoftFloat; 4801 public: 4802 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {} 4803 4804 bool handleTargetFeatures(std::vector<std::string> &Features, 4805 DiagnosticsEngine &Diags) override { 4806 SoftFloat = false; 4807 for (unsigned i = 0, e = Features.size(); i != e; ++i) 4808 if (Features[i] == "+soft-float") 4809 SoftFloat = true; 4810 return true; 4811 } 4812 void getTargetDefines(const LangOptions &Opts, 4813 MacroBuilder &Builder) const override { 4814 DefineStd(Builder, "sparc", Opts); 4815 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4816 4817 if (SoftFloat) 4818 Builder.defineMacro("SOFT_FLOAT", "1"); 4819 } 4820 4821 bool hasFeature(StringRef Feature) const override { 4822 return llvm::StringSwitch<bool>(Feature) 4823 .Case("softfloat", SoftFloat) 4824 .Case("sparc", true) 4825 .Default(false); 4826 } 4827 4828 void getTargetBuiltins(const Builtin::Info *&Records, 4829 unsigned &NumRecords) const override { 4830 // FIXME: Implement! 4831 } 4832 BuiltinVaListKind getBuiltinVaListKind() const override { 4833 return TargetInfo::VoidPtrBuiltinVaList; 4834 } 4835 void getGCCRegNames(const char * const *&Names, 4836 unsigned &NumNames) const override; 4837 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4838 unsigned &NumAliases) const override; 4839 bool validateAsmConstraint(const char *&Name, 4840 TargetInfo::ConstraintInfo &info) const override { 4841 // FIXME: Implement! 4842 return false; 4843 } 4844 const char *getClobbers() const override { 4845 // FIXME: Implement! 4846 return ""; 4847 } 4848 }; 4849 4850 const char * const SparcTargetInfo::GCCRegNames[] = { 4851 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4852 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4853 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4854 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 4855 }; 4856 4857 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 4858 unsigned &NumNames) const { 4859 Names = GCCRegNames; 4860 NumNames = llvm::array_lengthof(GCCRegNames); 4861 } 4862 4863 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 4864 { { "g0" }, "r0" }, 4865 { { "g1" }, "r1" }, 4866 { { "g2" }, "r2" }, 4867 { { "g3" }, "r3" }, 4868 { { "g4" }, "r4" }, 4869 { { "g5" }, "r5" }, 4870 { { "g6" }, "r6" }, 4871 { { "g7" }, "r7" }, 4872 { { "o0" }, "r8" }, 4873 { { "o1" }, "r9" }, 4874 { { "o2" }, "r10" }, 4875 { { "o3" }, "r11" }, 4876 { { "o4" }, "r12" }, 4877 { { "o5" }, "r13" }, 4878 { { "o6", "sp" }, "r14" }, 4879 { { "o7" }, "r15" }, 4880 { { "l0" }, "r16" }, 4881 { { "l1" }, "r17" }, 4882 { { "l2" }, "r18" }, 4883 { { "l3" }, "r19" }, 4884 { { "l4" }, "r20" }, 4885 { { "l5" }, "r21" }, 4886 { { "l6" }, "r22" }, 4887 { { "l7" }, "r23" }, 4888 { { "i0" }, "r24" }, 4889 { { "i1" }, "r25" }, 4890 { { "i2" }, "r26" }, 4891 { { "i3" }, "r27" }, 4892 { { "i4" }, "r28" }, 4893 { { "i5" }, "r29" }, 4894 { { "i6", "fp" }, "r30" }, 4895 { { "i7" }, "r31" }, 4896 }; 4897 4898 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4899 unsigned &NumAliases) const { 4900 Aliases = GCCRegAliases; 4901 NumAliases = llvm::array_lengthof(GCCRegAliases); 4902 } 4903 4904 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 4905 class SparcV8TargetInfo : public SparcTargetInfo { 4906 public: 4907 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4908 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 4909 } 4910 4911 void getTargetDefines(const LangOptions &Opts, 4912 MacroBuilder &Builder) const override { 4913 SparcTargetInfo::getTargetDefines(Opts, Builder); 4914 Builder.defineMacro("__sparcv8"); 4915 } 4916 }; 4917 4918 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 4919 class SparcV9TargetInfo : public SparcTargetInfo { 4920 public: 4921 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4922 // FIXME: Support Sparc quad-precision long double? 4923 DescriptionString = "E-m:e-i64:64-n32:64-S128"; 4924 // This is an LP64 platform. 4925 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4926 4927 // OpenBSD uses long long for int64_t and intmax_t. 4928 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 4929 IntMaxType = SignedLongLong; 4930 UIntMaxType = UnsignedLongLong; 4931 } else { 4932 IntMaxType = SignedLong; 4933 UIntMaxType = UnsignedLong; 4934 } 4935 Int64Type = IntMaxType; 4936 4937 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 4938 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 4939 LongDoubleWidth = 128; 4940 LongDoubleAlign = 128; 4941 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4942 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4943 } 4944 4945 void getTargetDefines(const LangOptions &Opts, 4946 MacroBuilder &Builder) const override { 4947 SparcTargetInfo::getTargetDefines(Opts, Builder); 4948 Builder.defineMacro("__sparcv9"); 4949 Builder.defineMacro("__arch64__"); 4950 // Solaris and its derivative AuroraUX don't need these variants, but the 4951 // BSDs do. 4952 if (getTriple().getOS() != llvm::Triple::Solaris && 4953 getTriple().getOS() != llvm::Triple::AuroraUX) { 4954 Builder.defineMacro("__sparc64__"); 4955 Builder.defineMacro("__sparc_v9__"); 4956 Builder.defineMacro("__sparcv9__"); 4957 } 4958 } 4959 4960 bool setCPU(const std::string &Name) override { 4961 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4962 .Case("v9", true) 4963 .Case("ultrasparc", true) 4964 .Case("ultrasparc3", true) 4965 .Case("niagara", true) 4966 .Case("niagara2", true) 4967 .Case("niagara3", true) 4968 .Case("niagara4", true) 4969 .Default(false); 4970 4971 // No need to store the CPU yet. There aren't any CPU-specific 4972 // macros to define. 4973 return CPUKnown; 4974 } 4975 }; 4976 4977 } // end anonymous namespace. 4978 4979 namespace { 4980 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> { 4981 public: 4982 AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple) 4983 : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) { 4984 SizeType = UnsignedInt; 4985 PtrDiffType = SignedInt; 4986 } 4987 }; 4988 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 4989 public: 4990 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 4991 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 4992 SizeType = UnsignedInt; 4993 PtrDiffType = SignedInt; 4994 } 4995 }; 4996 } // end anonymous namespace. 4997 4998 namespace { 4999 class SystemZTargetInfo : public TargetInfo { 5000 static const char *const GCCRegNames[]; 5001 5002 public: 5003 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5004 TLSSupported = true; 5005 IntWidth = IntAlign = 32; 5006 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5007 PointerWidth = PointerAlign = 64; 5008 LongDoubleWidth = 128; 5009 LongDoubleAlign = 64; 5010 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5011 MinGlobalAlign = 16; 5012 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5013 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5014 } 5015 void getTargetDefines(const LangOptions &Opts, 5016 MacroBuilder &Builder) const override { 5017 Builder.defineMacro("__s390__"); 5018 Builder.defineMacro("__s390x__"); 5019 Builder.defineMacro("__zarch__"); 5020 Builder.defineMacro("__LONG_DOUBLE_128__"); 5021 } 5022 void getTargetBuiltins(const Builtin::Info *&Records, 5023 unsigned &NumRecords) const override { 5024 // FIXME: Implement. 5025 Records = nullptr; 5026 NumRecords = 0; 5027 } 5028 5029 void getGCCRegNames(const char *const *&Names, 5030 unsigned &NumNames) const override; 5031 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5032 unsigned &NumAliases) const override { 5033 // No aliases. 5034 Aliases = nullptr; 5035 NumAliases = 0; 5036 } 5037 bool validateAsmConstraint(const char *&Name, 5038 TargetInfo::ConstraintInfo &info) const override; 5039 const char *getClobbers() const override { 5040 // FIXME: Is this really right? 5041 return ""; 5042 } 5043 BuiltinVaListKind getBuiltinVaListKind() const override { 5044 return TargetInfo::SystemZBuiltinVaList; 5045 } 5046 bool setCPU(const std::string &Name) override { 5047 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5048 .Case("z10", true) 5049 .Case("z196", true) 5050 .Case("zEC12", true) 5051 .Default(false); 5052 5053 // No need to store the CPU yet. There aren't any CPU-specific 5054 // macros to define. 5055 return CPUKnown; 5056 } 5057 }; 5058 5059 const char *const SystemZTargetInfo::GCCRegNames[] = { 5060 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5061 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5062 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 5063 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 5064 }; 5065 5066 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 5067 unsigned &NumNames) const { 5068 Names = GCCRegNames; 5069 NumNames = llvm::array_lengthof(GCCRegNames); 5070 } 5071 5072 bool SystemZTargetInfo:: 5073 validateAsmConstraint(const char *&Name, 5074 TargetInfo::ConstraintInfo &Info) const { 5075 switch (*Name) { 5076 default: 5077 return false; 5078 5079 case 'a': // Address register 5080 case 'd': // Data register (equivalent to 'r') 5081 case 'f': // Floating-point register 5082 Info.setAllowsRegister(); 5083 return true; 5084 5085 case 'I': // Unsigned 8-bit constant 5086 case 'J': // Unsigned 12-bit constant 5087 case 'K': // Signed 16-bit constant 5088 case 'L': // Signed 20-bit displacement (on all targets we support) 5089 case 'M': // 0x7fffffff 5090 return true; 5091 5092 case 'Q': // Memory with base and unsigned 12-bit displacement 5093 case 'R': // Likewise, plus an index 5094 case 'S': // Memory with base and signed 20-bit displacement 5095 case 'T': // Likewise, plus an index 5096 Info.setAllowsMemory(); 5097 return true; 5098 } 5099 } 5100 } 5101 5102 namespace { 5103 class MSP430TargetInfo : public TargetInfo { 5104 static const char * const GCCRegNames[]; 5105 public: 5106 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5107 BigEndian = false; 5108 TLSSupported = false; 5109 IntWidth = 16; IntAlign = 16; 5110 LongWidth = 32; LongLongWidth = 64; 5111 LongAlign = LongLongAlign = 16; 5112 PointerWidth = 16; PointerAlign = 16; 5113 SuitableAlign = 16; 5114 SizeType = UnsignedInt; 5115 IntMaxType = SignedLongLong; 5116 UIntMaxType = UnsignedLongLong; 5117 IntPtrType = SignedInt; 5118 PtrDiffType = SignedInt; 5119 SigAtomicType = SignedLong; 5120 DescriptionString = "e-m:e-p:16:16-i32:16:32-n8:16"; 5121 } 5122 void getTargetDefines(const LangOptions &Opts, 5123 MacroBuilder &Builder) const override { 5124 Builder.defineMacro("MSP430"); 5125 Builder.defineMacro("__MSP430__"); 5126 // FIXME: defines for different 'flavours' of MCU 5127 } 5128 void getTargetBuiltins(const Builtin::Info *&Records, 5129 unsigned &NumRecords) const override { 5130 // FIXME: Implement. 5131 Records = nullptr; 5132 NumRecords = 0; 5133 } 5134 bool hasFeature(StringRef Feature) const override { 5135 return Feature == "msp430"; 5136 } 5137 void getGCCRegNames(const char * const *&Names, 5138 unsigned &NumNames) const override; 5139 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5140 unsigned &NumAliases) const override { 5141 // No aliases. 5142 Aliases = nullptr; 5143 NumAliases = 0; 5144 } 5145 bool validateAsmConstraint(const char *&Name, 5146 TargetInfo::ConstraintInfo &info) const override { 5147 // No target constraints for now. 5148 return false; 5149 } 5150 const char *getClobbers() const override { 5151 // FIXME: Is this really right? 5152 return ""; 5153 } 5154 BuiltinVaListKind getBuiltinVaListKind() const override { 5155 // FIXME: implement 5156 return TargetInfo::CharPtrBuiltinVaList; 5157 } 5158 }; 5159 5160 const char * const MSP430TargetInfo::GCCRegNames[] = { 5161 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5162 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 5163 }; 5164 5165 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 5166 unsigned &NumNames) const { 5167 Names = GCCRegNames; 5168 NumNames = llvm::array_lengthof(GCCRegNames); 5169 } 5170 } 5171 5172 namespace { 5173 5174 // LLVM and Clang cannot be used directly to output native binaries for 5175 // target, but is used to compile C code to llvm bitcode with correct 5176 // type and alignment information. 5177 // 5178 // TCE uses the llvm bitcode as input and uses it for generating customized 5179 // target processor and program binary. TCE co-design environment is 5180 // publicly available in http://tce.cs.tut.fi 5181 5182 static const unsigned TCEOpenCLAddrSpaceMap[] = { 5183 3, // opencl_global 5184 4, // opencl_local 5185 5, // opencl_constant 5186 0, // cuda_device 5187 0, // cuda_constant 5188 0 // cuda_shared 5189 }; 5190 5191 class TCETargetInfo : public TargetInfo{ 5192 public: 5193 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5194 TLSSupported = false; 5195 IntWidth = 32; 5196 LongWidth = LongLongWidth = 32; 5197 PointerWidth = 32; 5198 IntAlign = 32; 5199 LongAlign = LongLongAlign = 32; 5200 PointerAlign = 32; 5201 SuitableAlign = 32; 5202 SizeType = UnsignedInt; 5203 IntMaxType = SignedLong; 5204 UIntMaxType = UnsignedLong; 5205 IntPtrType = SignedInt; 5206 PtrDiffType = SignedInt; 5207 FloatWidth = 32; 5208 FloatAlign = 32; 5209 DoubleWidth = 32; 5210 DoubleAlign = 32; 5211 LongDoubleWidth = 32; 5212 LongDoubleAlign = 32; 5213 FloatFormat = &llvm::APFloat::IEEEsingle; 5214 DoubleFormat = &llvm::APFloat::IEEEsingle; 5215 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 5216 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 5217 "-f64:32-v64:32-v128:32-a:0:32-n32"; 5218 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 5219 UseAddrSpaceMapMangling = true; 5220 } 5221 5222 void getTargetDefines(const LangOptions &Opts, 5223 MacroBuilder &Builder) const override { 5224 DefineStd(Builder, "tce", Opts); 5225 Builder.defineMacro("__TCE__"); 5226 Builder.defineMacro("__TCE_V1__"); 5227 } 5228 bool hasFeature(StringRef Feature) const override { 5229 return Feature == "tce"; 5230 } 5231 5232 void getTargetBuiltins(const Builtin::Info *&Records, 5233 unsigned &NumRecords) const override {} 5234 const char *getClobbers() const override { 5235 return ""; 5236 } 5237 BuiltinVaListKind getBuiltinVaListKind() const override { 5238 return TargetInfo::VoidPtrBuiltinVaList; 5239 } 5240 void getGCCRegNames(const char * const *&Names, 5241 unsigned &NumNames) const override {} 5242 bool validateAsmConstraint(const char *&Name, 5243 TargetInfo::ConstraintInfo &info) const override{ 5244 return true; 5245 } 5246 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5247 unsigned &NumAliases) const override {} 5248 }; 5249 } 5250 5251 namespace { 5252 class MipsTargetInfoBase : public TargetInfo { 5253 virtual void setDescriptionString() = 0; 5254 5255 static const Builtin::Info BuiltinInfo[]; 5256 std::string CPU; 5257 bool IsMips16; 5258 bool IsMicromips; 5259 bool IsNan2008; 5260 bool IsSingleFloat; 5261 enum MipsFloatABI { 5262 HardFloat, SoftFloat 5263 } FloatABI; 5264 enum DspRevEnum { 5265 NoDSP, DSP1, DSP2 5266 } DspRev; 5267 bool HasMSA; 5268 5269 protected: 5270 bool HasFP64; 5271 std::string ABI; 5272 5273 public: 5274 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 5275 const std::string &CPUStr) 5276 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 5277 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 5278 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {} 5279 5280 StringRef getABI() const override { return ABI; } 5281 bool setABI(const std::string &Name) override = 0; 5282 bool setCPU(const std::string &Name) override { 5283 CPU = Name; 5284 return true; 5285 } 5286 const std::string& getCPU() const { return CPU; } 5287 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5288 // The backend enables certain ABI's by default according to the 5289 // architecture. 5290 // Disable both possible defaults so that we don't end up with multiple 5291 // ABI's selected and trigger an assertion. 5292 Features["o32"] = false; 5293 Features["n64"] = false; 5294 5295 Features[ABI] = true; 5296 Features[CPU] = true; 5297 } 5298 5299 void getTargetDefines(const LangOptions &Opts, 5300 MacroBuilder &Builder) const override { 5301 Builder.defineMacro("__mips__"); 5302 Builder.defineMacro("_mips"); 5303 if (Opts.GNUMode) 5304 Builder.defineMacro("mips"); 5305 5306 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5307 5308 switch (FloatABI) { 5309 case HardFloat: 5310 Builder.defineMacro("__mips_hard_float", Twine(1)); 5311 break; 5312 case SoftFloat: 5313 Builder.defineMacro("__mips_soft_float", Twine(1)); 5314 break; 5315 } 5316 5317 if (IsSingleFloat) 5318 Builder.defineMacro("__mips_single_float", Twine(1)); 5319 5320 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 5321 Builder.defineMacro("_MIPS_FPSET", 5322 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 5323 5324 if (IsMips16) 5325 Builder.defineMacro("__mips16", Twine(1)); 5326 5327 if (IsMicromips) 5328 Builder.defineMacro("__mips_micromips", Twine(1)); 5329 5330 if (IsNan2008) 5331 Builder.defineMacro("__mips_nan2008", Twine(1)); 5332 5333 switch (DspRev) { 5334 default: 5335 break; 5336 case DSP1: 5337 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 5338 Builder.defineMacro("__mips_dsp", Twine(1)); 5339 break; 5340 case DSP2: 5341 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 5342 Builder.defineMacro("__mips_dspr2", Twine(1)); 5343 Builder.defineMacro("__mips_dsp", Twine(1)); 5344 break; 5345 } 5346 5347 if (HasMSA) 5348 Builder.defineMacro("__mips_msa", Twine(1)); 5349 5350 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 5351 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 5352 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 5353 5354 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 5355 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 5356 } 5357 5358 void getTargetBuiltins(const Builtin::Info *&Records, 5359 unsigned &NumRecords) const override { 5360 Records = BuiltinInfo; 5361 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 5362 } 5363 bool hasFeature(StringRef Feature) const override { 5364 return llvm::StringSwitch<bool>(Feature) 5365 .Case("mips", true) 5366 .Case("fp64", HasFP64) 5367 .Default(false); 5368 } 5369 BuiltinVaListKind getBuiltinVaListKind() const override { 5370 return TargetInfo::VoidPtrBuiltinVaList; 5371 } 5372 void getGCCRegNames(const char * const *&Names, 5373 unsigned &NumNames) const override { 5374 static const char *const GCCRegNames[] = { 5375 // CPU register names 5376 // Must match second column of GCCRegAliases 5377 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 5378 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 5379 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 5380 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 5381 // Floating point register names 5382 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 5383 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 5384 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 5385 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 5386 // Hi/lo and condition register names 5387 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 5388 "$fcc5","$fcc6","$fcc7", 5389 // MSA register names 5390 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 5391 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 5392 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 5393 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 5394 // MSA control register names 5395 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 5396 "$msarequest", "$msamap", "$msaunmap" 5397 }; 5398 Names = GCCRegNames; 5399 NumNames = llvm::array_lengthof(GCCRegNames); 5400 } 5401 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5402 unsigned &NumAliases) const override = 0; 5403 bool validateAsmConstraint(const char *&Name, 5404 TargetInfo::ConstraintInfo &Info) const override { 5405 switch (*Name) { 5406 default: 5407 return false; 5408 5409 case 'r': // CPU registers. 5410 case 'd': // Equivalent to "r" unless generating MIPS16 code. 5411 case 'y': // Equivalent to "r", backwards compatibility only. 5412 case 'f': // floating-point registers. 5413 case 'c': // $25 for indirect jumps 5414 case 'l': // lo register 5415 case 'x': // hilo register pair 5416 Info.setAllowsRegister(); 5417 return true; 5418 case 'R': // An address that can be used in a non-macro load or store 5419 Info.setAllowsMemory(); 5420 return true; 5421 } 5422 } 5423 5424 const char *getClobbers() const override { 5425 // FIXME: Implement! 5426 return ""; 5427 } 5428 5429 bool handleTargetFeatures(std::vector<std::string> &Features, 5430 DiagnosticsEngine &Diags) override { 5431 IsMips16 = false; 5432 IsMicromips = false; 5433 IsNan2008 = false; 5434 IsSingleFloat = false; 5435 FloatABI = HardFloat; 5436 DspRev = NoDSP; 5437 HasFP64 = ABI == "n32" || ABI == "n64" || ABI == "64"; 5438 5439 for (std::vector<std::string>::iterator it = Features.begin(), 5440 ie = Features.end(); it != ie; ++it) { 5441 if (*it == "+single-float") 5442 IsSingleFloat = true; 5443 else if (*it == "+soft-float") 5444 FloatABI = SoftFloat; 5445 else if (*it == "+mips16") 5446 IsMips16 = true; 5447 else if (*it == "+micromips") 5448 IsMicromips = true; 5449 else if (*it == "+dsp") 5450 DspRev = std::max(DspRev, DSP1); 5451 else if (*it == "+dspr2") 5452 DspRev = std::max(DspRev, DSP2); 5453 else if (*it == "+msa") 5454 HasMSA = true; 5455 else if (*it == "+fp64") 5456 HasFP64 = true; 5457 else if (*it == "-fp64") 5458 HasFP64 = false; 5459 else if (*it == "+nan2008") 5460 IsNan2008 = true; 5461 } 5462 5463 // Remove front-end specific options. 5464 std::vector<std::string>::iterator it = 5465 std::find(Features.begin(), Features.end(), "+soft-float"); 5466 if (it != Features.end()) 5467 Features.erase(it); 5468 5469 setDescriptionString(); 5470 5471 return true; 5472 } 5473 5474 int getEHDataRegisterNumber(unsigned RegNo) const override { 5475 if (RegNo == 0) return 4; 5476 if (RegNo == 1) return 5; 5477 return -1; 5478 } 5479 }; 5480 5481 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 5482 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5483 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5484 ALL_LANGUAGES }, 5485 #include "clang/Basic/BuiltinsMips.def" 5486 }; 5487 5488 class Mips32TargetInfoBase : public MipsTargetInfoBase { 5489 public: 5490 Mips32TargetInfoBase(const llvm::Triple &Triple) 5491 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 5492 SizeType = UnsignedInt; 5493 PtrDiffType = SignedInt; 5494 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 5495 } 5496 bool setABI(const std::string &Name) override { 5497 if ((Name == "o32") || (Name == "eabi")) { 5498 ABI = Name; 5499 return true; 5500 } else if (Name == "32") { 5501 ABI = "o32"; 5502 return true; 5503 } else 5504 return false; 5505 } 5506 void getTargetDefines(const LangOptions &Opts, 5507 MacroBuilder &Builder) const override { 5508 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5509 5510 Builder.defineMacro("__mips", "32"); 5511 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 5512 5513 const std::string& CPUStr = getCPU(); 5514 if (CPUStr == "mips32") 5515 Builder.defineMacro("__mips_isa_rev", "1"); 5516 else if (CPUStr == "mips32r2") 5517 Builder.defineMacro("__mips_isa_rev", "2"); 5518 5519 if (ABI == "o32") { 5520 Builder.defineMacro("__mips_o32"); 5521 Builder.defineMacro("_ABIO32", "1"); 5522 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 5523 } 5524 else if (ABI == "eabi") 5525 Builder.defineMacro("__mips_eabi"); 5526 else 5527 llvm_unreachable("Invalid ABI for Mips32."); 5528 } 5529 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5530 unsigned &NumAliases) const override { 5531 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5532 { { "at" }, "$1" }, 5533 { { "v0" }, "$2" }, 5534 { { "v1" }, "$3" }, 5535 { { "a0" }, "$4" }, 5536 { { "a1" }, "$5" }, 5537 { { "a2" }, "$6" }, 5538 { { "a3" }, "$7" }, 5539 { { "t0" }, "$8" }, 5540 { { "t1" }, "$9" }, 5541 { { "t2" }, "$10" }, 5542 { { "t3" }, "$11" }, 5543 { { "t4" }, "$12" }, 5544 { { "t5" }, "$13" }, 5545 { { "t6" }, "$14" }, 5546 { { "t7" }, "$15" }, 5547 { { "s0" }, "$16" }, 5548 { { "s1" }, "$17" }, 5549 { { "s2" }, "$18" }, 5550 { { "s3" }, "$19" }, 5551 { { "s4" }, "$20" }, 5552 { { "s5" }, "$21" }, 5553 { { "s6" }, "$22" }, 5554 { { "s7" }, "$23" }, 5555 { { "t8" }, "$24" }, 5556 { { "t9" }, "$25" }, 5557 { { "k0" }, "$26" }, 5558 { { "k1" }, "$27" }, 5559 { { "gp" }, "$28" }, 5560 { { "sp","$sp" }, "$29" }, 5561 { { "fp","$fp" }, "$30" }, 5562 { { "ra" }, "$31" } 5563 }; 5564 Aliases = GCCRegAliases; 5565 NumAliases = llvm::array_lengthof(GCCRegAliases); 5566 } 5567 }; 5568 5569 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 5570 void setDescriptionString() override { 5571 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5572 } 5573 5574 public: 5575 Mips32EBTargetInfo(const llvm::Triple &Triple) 5576 : Mips32TargetInfoBase(Triple) { 5577 } 5578 void getTargetDefines(const LangOptions &Opts, 5579 MacroBuilder &Builder) const override { 5580 DefineStd(Builder, "MIPSEB", Opts); 5581 Builder.defineMacro("_MIPSEB"); 5582 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5583 } 5584 }; 5585 5586 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 5587 void setDescriptionString() override { 5588 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5589 } 5590 5591 public: 5592 Mips32ELTargetInfo(const llvm::Triple &Triple) 5593 : Mips32TargetInfoBase(Triple) { 5594 BigEndian = false; 5595 } 5596 void getTargetDefines(const LangOptions &Opts, 5597 MacroBuilder &Builder) const override { 5598 DefineStd(Builder, "MIPSEL", Opts); 5599 Builder.defineMacro("_MIPSEL"); 5600 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5601 } 5602 }; 5603 5604 class Mips64TargetInfoBase : public MipsTargetInfoBase { 5605 public: 5606 Mips64TargetInfoBase(const llvm::Triple &Triple) 5607 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 5608 LongDoubleWidth = LongDoubleAlign = 128; 5609 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5610 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 5611 LongDoubleWidth = LongDoubleAlign = 64; 5612 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5613 } 5614 setN64ABITypes(); 5615 SuitableAlign = 128; 5616 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5617 } 5618 5619 void setN64ABITypes() { 5620 LongWidth = LongAlign = 64; 5621 PointerWidth = PointerAlign = 64; 5622 SizeType = UnsignedLong; 5623 PtrDiffType = SignedLong; 5624 } 5625 5626 void setN32ABITypes() { 5627 LongWidth = LongAlign = 32; 5628 PointerWidth = PointerAlign = 32; 5629 SizeType = UnsignedInt; 5630 PtrDiffType = SignedInt; 5631 } 5632 5633 bool setABI(const std::string &Name) override { 5634 if (Name == "n32") { 5635 setN32ABITypes(); 5636 ABI = Name; 5637 return true; 5638 } else if (Name == "n64" || Name == "64") { 5639 setN64ABITypes(); 5640 ABI = "n64"; 5641 return true; 5642 } 5643 return false; 5644 } 5645 5646 void getTargetDefines(const LangOptions &Opts, 5647 MacroBuilder &Builder) const override { 5648 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5649 5650 Builder.defineMacro("__mips", "64"); 5651 Builder.defineMacro("__mips64"); 5652 Builder.defineMacro("__mips64__"); 5653 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 5654 5655 const std::string& CPUStr = getCPU(); 5656 if (CPUStr == "mips64") 5657 Builder.defineMacro("__mips_isa_rev", "1"); 5658 else if (CPUStr == "mips64r2") 5659 Builder.defineMacro("__mips_isa_rev", "2"); 5660 5661 if (ABI == "n32") { 5662 Builder.defineMacro("__mips_n32"); 5663 Builder.defineMacro("_ABIN32", "2"); 5664 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 5665 } 5666 else if (ABI == "n64") { 5667 Builder.defineMacro("__mips_n64"); 5668 Builder.defineMacro("_ABI64", "3"); 5669 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 5670 } 5671 else 5672 llvm_unreachable("Invalid ABI for Mips64."); 5673 } 5674 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5675 unsigned &NumAliases) const override { 5676 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5677 { { "at" }, "$1" }, 5678 { { "v0" }, "$2" }, 5679 { { "v1" }, "$3" }, 5680 { { "a0" }, "$4" }, 5681 { { "a1" }, "$5" }, 5682 { { "a2" }, "$6" }, 5683 { { "a3" }, "$7" }, 5684 { { "a4" }, "$8" }, 5685 { { "a5" }, "$9" }, 5686 { { "a6" }, "$10" }, 5687 { { "a7" }, "$11" }, 5688 { { "t0" }, "$12" }, 5689 { { "t1" }, "$13" }, 5690 { { "t2" }, "$14" }, 5691 { { "t3" }, "$15" }, 5692 { { "s0" }, "$16" }, 5693 { { "s1" }, "$17" }, 5694 { { "s2" }, "$18" }, 5695 { { "s3" }, "$19" }, 5696 { { "s4" }, "$20" }, 5697 { { "s5" }, "$21" }, 5698 { { "s6" }, "$22" }, 5699 { { "s7" }, "$23" }, 5700 { { "t8" }, "$24" }, 5701 { { "t9" }, "$25" }, 5702 { { "k0" }, "$26" }, 5703 { { "k1" }, "$27" }, 5704 { { "gp" }, "$28" }, 5705 { { "sp","$sp" }, "$29" }, 5706 { { "fp","$fp" }, "$30" }, 5707 { { "ra" }, "$31" } 5708 }; 5709 Aliases = GCCRegAliases; 5710 NumAliases = llvm::array_lengthof(GCCRegAliases); 5711 } 5712 5713 bool hasInt128Type() const override { return true; } 5714 }; 5715 5716 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 5717 void setDescriptionString() override { 5718 if (ABI == "n32") 5719 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5720 else 5721 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5722 5723 } 5724 5725 public: 5726 Mips64EBTargetInfo(const llvm::Triple &Triple) 5727 : Mips64TargetInfoBase(Triple) {} 5728 void getTargetDefines(const LangOptions &Opts, 5729 MacroBuilder &Builder) const override { 5730 DefineStd(Builder, "MIPSEB", Opts); 5731 Builder.defineMacro("_MIPSEB"); 5732 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5733 } 5734 }; 5735 5736 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 5737 void setDescriptionString() override { 5738 if (ABI == "n32") 5739 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5740 else 5741 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5742 } 5743 public: 5744 Mips64ELTargetInfo(const llvm::Triple &Triple) 5745 : Mips64TargetInfoBase(Triple) { 5746 // Default ABI is n64. 5747 BigEndian = false; 5748 } 5749 void getTargetDefines(const LangOptions &Opts, 5750 MacroBuilder &Builder) const override { 5751 DefineStd(Builder, "MIPSEL", Opts); 5752 Builder.defineMacro("_MIPSEL"); 5753 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5754 } 5755 }; 5756 } // end anonymous namespace. 5757 5758 namespace { 5759 class PNaClTargetInfo : public TargetInfo { 5760 public: 5761 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5762 BigEndian = false; 5763 this->UserLabelPrefix = ""; 5764 this->LongAlign = 32; 5765 this->LongWidth = 32; 5766 this->PointerAlign = 32; 5767 this->PointerWidth = 32; 5768 this->IntMaxType = TargetInfo::SignedLongLong; 5769 this->UIntMaxType = TargetInfo::UnsignedLongLong; 5770 this->Int64Type = TargetInfo::SignedLongLong; 5771 this->DoubleAlign = 64; 5772 this->LongDoubleWidth = 64; 5773 this->LongDoubleAlign = 64; 5774 this->SizeType = TargetInfo::UnsignedInt; 5775 this->PtrDiffType = TargetInfo::SignedInt; 5776 this->IntPtrType = TargetInfo::SignedInt; 5777 this->RegParmMax = 0; // Disallow regparm 5778 } 5779 5780 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5781 } 5782 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 5783 Builder.defineMacro("__le32__"); 5784 Builder.defineMacro("__pnacl__"); 5785 } 5786 void getTargetDefines(const LangOptions &Opts, 5787 MacroBuilder &Builder) const override { 5788 getArchDefines(Opts, Builder); 5789 } 5790 bool hasFeature(StringRef Feature) const override { 5791 return Feature == "pnacl"; 5792 } 5793 void getTargetBuiltins(const Builtin::Info *&Records, 5794 unsigned &NumRecords) const override { 5795 } 5796 BuiltinVaListKind getBuiltinVaListKind() const override { 5797 return TargetInfo::PNaClABIBuiltinVaList; 5798 } 5799 void getGCCRegNames(const char * const *&Names, 5800 unsigned &NumNames) const override; 5801 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5802 unsigned &NumAliases) const override; 5803 bool validateAsmConstraint(const char *&Name, 5804 TargetInfo::ConstraintInfo &Info) const override { 5805 return false; 5806 } 5807 5808 const char *getClobbers() const override { 5809 return ""; 5810 } 5811 }; 5812 5813 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 5814 unsigned &NumNames) const { 5815 Names = nullptr; 5816 NumNames = 0; 5817 } 5818 5819 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5820 unsigned &NumAliases) const { 5821 Aliases = nullptr; 5822 NumAliases = 0; 5823 } 5824 } // end anonymous namespace. 5825 5826 namespace { 5827 static const unsigned SPIRAddrSpaceMap[] = { 5828 1, // opencl_global 5829 3, // opencl_local 5830 2, // opencl_constant 5831 0, // cuda_device 5832 0, // cuda_constant 5833 0 // cuda_shared 5834 }; 5835 class SPIRTargetInfo : public TargetInfo { 5836 public: 5837 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5838 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 5839 "SPIR target must use unknown OS"); 5840 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 5841 "SPIR target must use unknown environment type"); 5842 BigEndian = false; 5843 TLSSupported = false; 5844 LongWidth = LongAlign = 64; 5845 AddrSpaceMap = &SPIRAddrSpaceMap; 5846 UseAddrSpaceMapMangling = true; 5847 // Define available target features 5848 // These must be defined in sorted order! 5849 NoAsmVariants = true; 5850 } 5851 void getTargetDefines(const LangOptions &Opts, 5852 MacroBuilder &Builder) const override { 5853 DefineStd(Builder, "SPIR", Opts); 5854 } 5855 bool hasFeature(StringRef Feature) const override { 5856 return Feature == "spir"; 5857 } 5858 5859 void getTargetBuiltins(const Builtin::Info *&Records, 5860 unsigned &NumRecords) const override {} 5861 const char *getClobbers() const override { 5862 return ""; 5863 } 5864 void getGCCRegNames(const char * const *&Names, 5865 unsigned &NumNames) const override {} 5866 bool validateAsmConstraint(const char *&Name, 5867 TargetInfo::ConstraintInfo &info) const override { 5868 return true; 5869 } 5870 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5871 unsigned &NumAliases) const override {} 5872 BuiltinVaListKind getBuiltinVaListKind() const override { 5873 return TargetInfo::VoidPtrBuiltinVaList; 5874 } 5875 }; 5876 5877 5878 class SPIR32TargetInfo : public SPIRTargetInfo { 5879 public: 5880 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5881 PointerWidth = PointerAlign = 32; 5882 SizeType = TargetInfo::UnsignedInt; 5883 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 5884 DescriptionString 5885 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 5886 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 5887 } 5888 void getTargetDefines(const LangOptions &Opts, 5889 MacroBuilder &Builder) const override { 5890 DefineStd(Builder, "SPIR32", Opts); 5891 } 5892 }; 5893 5894 class SPIR64TargetInfo : public SPIRTargetInfo { 5895 public: 5896 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5897 PointerWidth = PointerAlign = 64; 5898 SizeType = TargetInfo::UnsignedLong; 5899 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 5900 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 5901 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 5902 } 5903 void getTargetDefines(const LangOptions &Opts, 5904 MacroBuilder &Builder) const override { 5905 DefineStd(Builder, "SPIR64", Opts); 5906 } 5907 }; 5908 } 5909 5910 namespace { 5911 class XCoreTargetInfo : public TargetInfo { 5912 static const Builtin::Info BuiltinInfo[]; 5913 public: 5914 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5915 BigEndian = false; 5916 NoAsmVariants = true; 5917 LongLongAlign = 32; 5918 SuitableAlign = 32; 5919 DoubleAlign = LongDoubleAlign = 32; 5920 SizeType = UnsignedInt; 5921 PtrDiffType = SignedInt; 5922 IntPtrType = SignedInt; 5923 WCharType = UnsignedChar; 5924 WIntType = UnsignedInt; 5925 UseZeroLengthBitfieldAlignment = true; 5926 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 5927 "-f64:32-a:0:32-n32"; 5928 } 5929 void getTargetDefines(const LangOptions &Opts, 5930 MacroBuilder &Builder) const override { 5931 Builder.defineMacro("__XS1B__"); 5932 } 5933 void getTargetBuiltins(const Builtin::Info *&Records, 5934 unsigned &NumRecords) const override { 5935 Records = BuiltinInfo; 5936 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 5937 } 5938 BuiltinVaListKind getBuiltinVaListKind() const override { 5939 return TargetInfo::VoidPtrBuiltinVaList; 5940 } 5941 const char *getClobbers() const override { 5942 return ""; 5943 } 5944 void getGCCRegNames(const char * const *&Names, 5945 unsigned &NumNames) const override { 5946 static const char * const GCCRegNames[] = { 5947 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5948 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 5949 }; 5950 Names = GCCRegNames; 5951 NumNames = llvm::array_lengthof(GCCRegNames); 5952 } 5953 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5954 unsigned &NumAliases) const override { 5955 Aliases = nullptr; 5956 NumAliases = 0; 5957 } 5958 bool validateAsmConstraint(const char *&Name, 5959 TargetInfo::ConstraintInfo &Info) const override { 5960 return false; 5961 } 5962 int getEHDataRegisterNumber(unsigned RegNo) const override { 5963 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 5964 return (RegNo < 2)? RegNo : -1; 5965 } 5966 }; 5967 5968 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 5969 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5970 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5971 ALL_LANGUAGES }, 5972 #include "clang/Basic/BuiltinsXCore.def" 5973 }; 5974 } // end anonymous namespace. 5975 5976 5977 //===----------------------------------------------------------------------===// 5978 // Driver code 5979 //===----------------------------------------------------------------------===// 5980 5981 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 5982 llvm::Triple::OSType os = Triple.getOS(); 5983 5984 switch (Triple.getArch()) { 5985 default: 5986 return nullptr; 5987 5988 case llvm::Triple::xcore: 5989 return new XCoreTargetInfo(Triple); 5990 5991 case llvm::Triple::hexagon: 5992 return new HexagonTargetInfo(Triple); 5993 5994 case llvm::Triple::aarch64: 5995 case llvm::Triple::arm64: 5996 if (Triple.isOSDarwin()) 5997 return new DarwinAArch64TargetInfo(Triple); 5998 5999 switch (os) { 6000 case llvm::Triple::Linux: 6001 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 6002 case llvm::Triple::NetBSD: 6003 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 6004 default: 6005 return new AArch64leTargetInfo(Triple); 6006 } 6007 6008 case llvm::Triple::aarch64_be: 6009 case llvm::Triple::arm64_be: 6010 switch (os) { 6011 case llvm::Triple::Linux: 6012 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 6013 case llvm::Triple::NetBSD: 6014 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 6015 default: 6016 return new AArch64beTargetInfo(Triple); 6017 } 6018 6019 case llvm::Triple::arm: 6020 case llvm::Triple::thumb: 6021 if (Triple.isOSBinFormatMachO()) 6022 return new DarwinARMTargetInfo(Triple); 6023 6024 switch (os) { 6025 case llvm::Triple::Linux: 6026 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 6027 case llvm::Triple::FreeBSD: 6028 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 6029 case llvm::Triple::NetBSD: 6030 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 6031 case llvm::Triple::OpenBSD: 6032 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 6033 case llvm::Triple::Bitrig: 6034 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 6035 case llvm::Triple::RTEMS: 6036 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 6037 case llvm::Triple::NaCl: 6038 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 6039 case llvm::Triple::Win32: 6040 switch (Triple.getEnvironment()) { 6041 default: 6042 return new ARMleTargetInfo(Triple); 6043 case llvm::Triple::Itanium: 6044 return new ItaniumWindowsARMleTargetInfo(Triple); 6045 case llvm::Triple::MSVC: 6046 return new MicrosoftARMleTargetInfo(Triple); 6047 } 6048 default: 6049 return new ARMleTargetInfo(Triple); 6050 } 6051 6052 case llvm::Triple::armeb: 6053 case llvm::Triple::thumbeb: 6054 if (Triple.isOSDarwin()) 6055 return new DarwinARMTargetInfo(Triple); 6056 6057 switch (os) { 6058 case llvm::Triple::Linux: 6059 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 6060 case llvm::Triple::FreeBSD: 6061 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 6062 case llvm::Triple::NetBSD: 6063 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 6064 case llvm::Triple::OpenBSD: 6065 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 6066 case llvm::Triple::Bitrig: 6067 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 6068 case llvm::Triple::RTEMS: 6069 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 6070 case llvm::Triple::NaCl: 6071 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 6072 default: 6073 return new ARMbeTargetInfo(Triple); 6074 } 6075 6076 case llvm::Triple::msp430: 6077 return new MSP430TargetInfo(Triple); 6078 6079 case llvm::Triple::mips: 6080 switch (os) { 6081 case llvm::Triple::Linux: 6082 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 6083 case llvm::Triple::RTEMS: 6084 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 6085 case llvm::Triple::FreeBSD: 6086 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6087 case llvm::Triple::NetBSD: 6088 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6089 default: 6090 return new Mips32EBTargetInfo(Triple); 6091 } 6092 6093 case llvm::Triple::mipsel: 6094 switch (os) { 6095 case llvm::Triple::Linux: 6096 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 6097 case llvm::Triple::RTEMS: 6098 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 6099 case llvm::Triple::FreeBSD: 6100 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6101 case llvm::Triple::NetBSD: 6102 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6103 case llvm::Triple::NaCl: 6104 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 6105 default: 6106 return new Mips32ELTargetInfo(Triple); 6107 } 6108 6109 case llvm::Triple::mips64: 6110 switch (os) { 6111 case llvm::Triple::Linux: 6112 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 6113 case llvm::Triple::RTEMS: 6114 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 6115 case llvm::Triple::FreeBSD: 6116 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6117 case llvm::Triple::NetBSD: 6118 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6119 case llvm::Triple::OpenBSD: 6120 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6121 default: 6122 return new Mips64EBTargetInfo(Triple); 6123 } 6124 6125 case llvm::Triple::mips64el: 6126 switch (os) { 6127 case llvm::Triple::Linux: 6128 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 6129 case llvm::Triple::RTEMS: 6130 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 6131 case llvm::Triple::FreeBSD: 6132 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6133 case llvm::Triple::NetBSD: 6134 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6135 case llvm::Triple::OpenBSD: 6136 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6137 default: 6138 return new Mips64ELTargetInfo(Triple); 6139 } 6140 6141 case llvm::Triple::le32: 6142 switch (os) { 6143 case llvm::Triple::NaCl: 6144 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 6145 default: 6146 return nullptr; 6147 } 6148 6149 case llvm::Triple::ppc: 6150 if (Triple.isOSDarwin()) 6151 return new DarwinPPC32TargetInfo(Triple); 6152 switch (os) { 6153 case llvm::Triple::Linux: 6154 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 6155 case llvm::Triple::FreeBSD: 6156 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 6157 case llvm::Triple::NetBSD: 6158 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 6159 case llvm::Triple::OpenBSD: 6160 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 6161 case llvm::Triple::RTEMS: 6162 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 6163 default: 6164 return new PPC32TargetInfo(Triple); 6165 } 6166 6167 case llvm::Triple::ppc64: 6168 if (Triple.isOSDarwin()) 6169 return new DarwinPPC64TargetInfo(Triple); 6170 switch (os) { 6171 case llvm::Triple::Linux: 6172 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6173 case llvm::Triple::Lv2: 6174 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 6175 case llvm::Triple::FreeBSD: 6176 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 6177 case llvm::Triple::NetBSD: 6178 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 6179 default: 6180 return new PPC64TargetInfo(Triple); 6181 } 6182 6183 case llvm::Triple::ppc64le: 6184 switch (os) { 6185 case llvm::Triple::Linux: 6186 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6187 default: 6188 return new PPC64TargetInfo(Triple); 6189 } 6190 6191 case llvm::Triple::nvptx: 6192 return new NVPTX32TargetInfo(Triple); 6193 case llvm::Triple::nvptx64: 6194 return new NVPTX64TargetInfo(Triple); 6195 6196 case llvm::Triple::r600: 6197 return new R600TargetInfo(Triple); 6198 6199 case llvm::Triple::sparc: 6200 switch (os) { 6201 case llvm::Triple::Linux: 6202 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 6203 case llvm::Triple::AuroraUX: 6204 return new AuroraUXSparcV8TargetInfo(Triple); 6205 case llvm::Triple::Solaris: 6206 return new SolarisSparcV8TargetInfo(Triple); 6207 case llvm::Triple::NetBSD: 6208 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 6209 case llvm::Triple::OpenBSD: 6210 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 6211 case llvm::Triple::RTEMS: 6212 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 6213 default: 6214 return new SparcV8TargetInfo(Triple); 6215 } 6216 6217 case llvm::Triple::sparcv9: 6218 switch (os) { 6219 case llvm::Triple::Linux: 6220 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 6221 case llvm::Triple::AuroraUX: 6222 return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple); 6223 case llvm::Triple::Solaris: 6224 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 6225 case llvm::Triple::NetBSD: 6226 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 6227 case llvm::Triple::OpenBSD: 6228 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 6229 case llvm::Triple::FreeBSD: 6230 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 6231 default: 6232 return new SparcV9TargetInfo(Triple); 6233 } 6234 6235 case llvm::Triple::systemz: 6236 switch (os) { 6237 case llvm::Triple::Linux: 6238 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 6239 default: 6240 return new SystemZTargetInfo(Triple); 6241 } 6242 6243 case llvm::Triple::tce: 6244 return new TCETargetInfo(Triple); 6245 6246 case llvm::Triple::x86: 6247 if (Triple.isOSDarwin()) 6248 return new DarwinI386TargetInfo(Triple); 6249 6250 switch (os) { 6251 case llvm::Triple::AuroraUX: 6252 return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple); 6253 case llvm::Triple::Linux: 6254 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 6255 case llvm::Triple::DragonFly: 6256 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 6257 case llvm::Triple::NetBSD: 6258 return new NetBSDI386TargetInfo(Triple); 6259 case llvm::Triple::OpenBSD: 6260 return new OpenBSDI386TargetInfo(Triple); 6261 case llvm::Triple::Bitrig: 6262 return new BitrigI386TargetInfo(Triple); 6263 case llvm::Triple::FreeBSD: 6264 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 6265 case llvm::Triple::KFreeBSD: 6266 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 6267 case llvm::Triple::Minix: 6268 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 6269 case llvm::Triple::Solaris: 6270 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 6271 case llvm::Triple::Win32: { 6272 switch (Triple.getEnvironment()) { 6273 default: 6274 return new X86_32TargetInfo(Triple); 6275 case llvm::Triple::Cygnus: 6276 return new CygwinX86_32TargetInfo(Triple); 6277 case llvm::Triple::GNU: 6278 return new MinGWX86_32TargetInfo(Triple); 6279 case llvm::Triple::MSVC: 6280 return new MicrosoftX86_32TargetInfo(Triple); 6281 } 6282 } 6283 case llvm::Triple::Haiku: 6284 return new HaikuX86_32TargetInfo(Triple); 6285 case llvm::Triple::RTEMS: 6286 return new RTEMSX86_32TargetInfo(Triple); 6287 case llvm::Triple::NaCl: 6288 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 6289 default: 6290 return new X86_32TargetInfo(Triple); 6291 } 6292 6293 case llvm::Triple::x86_64: 6294 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 6295 return new DarwinX86_64TargetInfo(Triple); 6296 6297 switch (os) { 6298 case llvm::Triple::AuroraUX: 6299 return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple); 6300 case llvm::Triple::Linux: 6301 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 6302 case llvm::Triple::DragonFly: 6303 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 6304 case llvm::Triple::NetBSD: 6305 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 6306 case llvm::Triple::OpenBSD: 6307 return new OpenBSDX86_64TargetInfo(Triple); 6308 case llvm::Triple::Bitrig: 6309 return new BitrigX86_64TargetInfo(Triple); 6310 case llvm::Triple::FreeBSD: 6311 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 6312 case llvm::Triple::KFreeBSD: 6313 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 6314 case llvm::Triple::Solaris: 6315 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 6316 case llvm::Triple::Win32: { 6317 switch (Triple.getEnvironment()) { 6318 default: 6319 return new X86_64TargetInfo(Triple); 6320 case llvm::Triple::GNU: 6321 return new MinGWX86_64TargetInfo(Triple); 6322 case llvm::Triple::MSVC: 6323 return new MicrosoftX86_64TargetInfo(Triple); 6324 } 6325 } 6326 case llvm::Triple::NaCl: 6327 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 6328 default: 6329 return new X86_64TargetInfo(Triple); 6330 } 6331 6332 case llvm::Triple::spir: { 6333 if (Triple.getOS() != llvm::Triple::UnknownOS || 6334 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 6335 return nullptr; 6336 return new SPIR32TargetInfo(Triple); 6337 } 6338 case llvm::Triple::spir64: { 6339 if (Triple.getOS() != llvm::Triple::UnknownOS || 6340 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 6341 return nullptr; 6342 return new SPIR64TargetInfo(Triple); 6343 } 6344 } 6345 } 6346 6347 /// CreateTargetInfo - Return the target info object for the specified target 6348 /// triple. 6349 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 6350 TargetOptions *Opts) { 6351 llvm::Triple Triple(Opts->Triple); 6352 6353 // Construct the target 6354 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 6355 if (!Target) { 6356 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 6357 return nullptr; 6358 } 6359 Target->setTargetOpts(Opts); 6360 6361 // Set the target CPU if specified. 6362 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 6363 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 6364 return nullptr; 6365 } 6366 6367 // Set the target ABI if specified. 6368 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 6369 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 6370 return nullptr; 6371 } 6372 6373 // Set the fp math unit. 6374 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 6375 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 6376 return nullptr; 6377 } 6378 6379 // Compute the default target features, we need the target to handle this 6380 // because features may have dependencies on one another. 6381 llvm::StringMap<bool> Features; 6382 Target->getDefaultFeatures(Features); 6383 6384 // Apply the user specified deltas. 6385 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 6386 I < N; ++I) { 6387 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 6388 // Apply the feature via the target. 6389 bool Enabled = Name[0] == '+'; 6390 Target->setFeatureEnabled(Features, Name + 1, Enabled); 6391 } 6392 6393 // Add the features to the compile options. 6394 // 6395 // FIXME: If we are completely confident that we have the right set, we only 6396 // need to pass the minuses. 6397 Opts->Features.clear(); 6398 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 6399 ie = Features.end(); it != ie; ++it) 6400 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 6401 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 6402 return nullptr; 6403 6404 return Target.release(); 6405 } 6406