1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/OwningPtr.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/IR/Type.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include <algorithm> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 77 virtual void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "6000"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("__MACH__"); 94 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 95 // AddressSanitizer doesn't play well with source fortification, which is on 96 // by default on Darwin. 97 if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0"); 98 99 if (!Opts.ObjCAutoRefCount) { 100 // __weak is always defined, for use in blocks and with objc pointers. 101 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 102 103 // Darwin defines __strong even in C mode (just to nothing). 104 if (Opts.getGC() != LangOptions::NonGC) 105 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 106 else 107 Builder.defineMacro("__strong", ""); 108 109 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 110 // allow this in C, since one might have block pointers in structs that 111 // are used in pure C code and in Objective-C ARC. 112 Builder.defineMacro("__unsafe_unretained", ""); 113 } 114 115 if (Opts.Static) 116 Builder.defineMacro("__STATIC__"); 117 else 118 Builder.defineMacro("__DYNAMIC__"); 119 120 if (Opts.POSIXThreads) 121 Builder.defineMacro("_REENTRANT"); 122 123 // Get the platform type and version number from the triple. 124 unsigned Maj, Min, Rev; 125 if (Triple.isMacOSX()) { 126 Triple.getMacOSXVersion(Maj, Min, Rev); 127 PlatformName = "macosx"; 128 } else { 129 Triple.getOSVersion(Maj, Min, Rev); 130 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 131 } 132 133 // If -target arch-pc-win32-macho option specified, we're 134 // generating code for Win32 ABI. No need to emit 135 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 136 if (PlatformName == "win32") { 137 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 138 return; 139 } 140 141 // Set the appropriate OS version define. 142 if (Triple.isiOS()) { 143 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 144 char Str[6]; 145 Str[0] = '0' + Maj; 146 Str[1] = '0' + (Min / 10); 147 Str[2] = '0' + (Min % 10); 148 Str[3] = '0' + (Rev / 10); 149 Str[4] = '0' + (Rev % 10); 150 Str[5] = '\0'; 151 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str); 152 } else { 153 // Note that the Driver allows versions which aren't representable in the 154 // define (because we only get a single digit for the minor and micro 155 // revision numbers). So, we limit them to the maximum representable 156 // version. 157 assert(Triple.getEnvironmentName().empty() && "Invalid environment!"); 158 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 159 char Str[5]; 160 Str[0] = '0' + (Maj / 10); 161 Str[1] = '0' + (Maj % 10); 162 Str[2] = '0' + std::min(Min, 9U); 163 Str[3] = '0' + std::min(Rev, 9U); 164 Str[4] = '\0'; 165 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 166 } 167 168 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 169 } 170 171 namespace { 172 template<typename Target> 173 class DarwinTargetInfo : public OSTargetInfo<Target> { 174 protected: 175 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 176 MacroBuilder &Builder) const { 177 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 178 this->PlatformMinVersion); 179 } 180 181 public: 182 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 183 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 184 this->MCountName = "\01mcount"; 185 } 186 187 virtual std::string isValidSectionSpecifier(StringRef SR) const { 188 // Let MCSectionMachO validate this. 189 StringRef Segment, Section; 190 unsigned TAA, StubSize; 191 bool HasTAA; 192 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 193 TAA, HasTAA, StubSize); 194 } 195 196 virtual const char *getStaticInitSectionSpecifier() const { 197 // FIXME: We should return 0 when building kexts. 198 return "__TEXT,__StaticInit,regular,pure_instructions"; 199 } 200 201 /// Darwin does not support protected visibility. Darwin's "default" 202 /// is very similar to ELF's "protected"; Darwin requires a "weak" 203 /// attribute on declarations that can be dynamically replaced. 204 virtual bool hasProtectedVisibility() const { 205 return false; 206 } 207 }; 208 209 210 // DragonFlyBSD Target 211 template<typename Target> 212 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 213 protected: 214 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 215 MacroBuilder &Builder) const { 216 // DragonFly defines; list based off of gcc output 217 Builder.defineMacro("__DragonFly__"); 218 Builder.defineMacro("__DragonFly_cc_version", "100001"); 219 Builder.defineMacro("__ELF__"); 220 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 221 Builder.defineMacro("__tune_i386__"); 222 DefineStd(Builder, "unix", Opts); 223 } 224 public: 225 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 226 : OSTargetInfo<Target>(Triple) { 227 this->UserLabelPrefix = ""; 228 229 switch (Triple.getArch()) { 230 default: 231 case llvm::Triple::x86: 232 case llvm::Triple::x86_64: 233 this->MCountName = ".mcount"; 234 break; 235 } 236 } 237 }; 238 239 // FreeBSD Target 240 template<typename Target> 241 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 242 protected: 243 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 244 MacroBuilder &Builder) const { 245 // FreeBSD defines; list based off of gcc output 246 247 unsigned Release = Triple.getOSMajorVersion(); 248 if (Release == 0U) 249 Release = 8; 250 251 Builder.defineMacro("__FreeBSD__", Twine(Release)); 252 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 253 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 254 DefineStd(Builder, "unix", Opts); 255 Builder.defineMacro("__ELF__"); 256 257 // On FreeBSD, wchar_t contains the number of the code point as 258 // used by the character set of the locale. These character sets are 259 // not necessarily a superset of ASCII. 260 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 261 } 262 public: 263 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 264 this->UserLabelPrefix = ""; 265 266 switch (Triple.getArch()) { 267 default: 268 case llvm::Triple::x86: 269 case llvm::Triple::x86_64: 270 this->MCountName = ".mcount"; 271 break; 272 case llvm::Triple::mips: 273 case llvm::Triple::mipsel: 274 case llvm::Triple::ppc: 275 case llvm::Triple::ppc64: 276 case llvm::Triple::ppc64le: 277 this->MCountName = "_mcount"; 278 break; 279 case llvm::Triple::arm: 280 this->MCountName = "__mcount"; 281 break; 282 } 283 } 284 }; 285 286 // GNU/kFreeBSD Target 287 template<typename Target> 288 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 289 protected: 290 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 291 MacroBuilder &Builder) const { 292 // GNU/kFreeBSD defines; list based off of gcc output 293 294 DefineStd(Builder, "unix", Opts); 295 Builder.defineMacro("__FreeBSD_kernel__"); 296 Builder.defineMacro("__GLIBC__"); 297 Builder.defineMacro("__ELF__"); 298 if (Opts.POSIXThreads) 299 Builder.defineMacro("_REENTRANT"); 300 if (Opts.CPlusPlus) 301 Builder.defineMacro("_GNU_SOURCE"); 302 } 303 public: 304 KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 305 this->UserLabelPrefix = ""; 306 } 307 }; 308 309 // Minix Target 310 template<typename Target> 311 class MinixTargetInfo : public OSTargetInfo<Target> { 312 protected: 313 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 314 MacroBuilder &Builder) const { 315 // Minix defines 316 317 Builder.defineMacro("__minix", "3"); 318 Builder.defineMacro("_EM_WSIZE", "4"); 319 Builder.defineMacro("_EM_PSIZE", "4"); 320 Builder.defineMacro("_EM_SSIZE", "2"); 321 Builder.defineMacro("_EM_LSIZE", "4"); 322 Builder.defineMacro("_EM_FSIZE", "4"); 323 Builder.defineMacro("_EM_DSIZE", "8"); 324 Builder.defineMacro("__ELF__"); 325 DefineStd(Builder, "unix", Opts); 326 } 327 public: 328 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 329 this->UserLabelPrefix = ""; 330 } 331 }; 332 333 // Linux target 334 template<typename Target> 335 class LinuxTargetInfo : public OSTargetInfo<Target> { 336 protected: 337 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 338 MacroBuilder &Builder) const { 339 // Linux defines; list based off of gcc output 340 DefineStd(Builder, "unix", Opts); 341 DefineStd(Builder, "linux", Opts); 342 Builder.defineMacro("__gnu_linux__"); 343 Builder.defineMacro("__ELF__"); 344 if (Triple.getEnvironment() == llvm::Triple::Android) 345 Builder.defineMacro("__ANDROID__", "1"); 346 if (Opts.POSIXThreads) 347 Builder.defineMacro("_REENTRANT"); 348 if (Opts.CPlusPlus) 349 Builder.defineMacro("_GNU_SOURCE"); 350 } 351 public: 352 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 353 this->UserLabelPrefix = ""; 354 this->WIntType = TargetInfo::UnsignedInt; 355 } 356 357 virtual const char *getStaticInitSectionSpecifier() const { 358 return ".text.startup"; 359 } 360 }; 361 362 // NetBSD Target 363 template<typename Target> 364 class NetBSDTargetInfo : public OSTargetInfo<Target> { 365 protected: 366 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 367 MacroBuilder &Builder) const { 368 // NetBSD defines; list based off of gcc output 369 Builder.defineMacro("__NetBSD__"); 370 Builder.defineMacro("__unix__"); 371 Builder.defineMacro("__ELF__"); 372 if (Opts.POSIXThreads) 373 Builder.defineMacro("_POSIX_THREADS"); 374 } 375 public: 376 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 377 this->UserLabelPrefix = ""; 378 } 379 }; 380 381 // OpenBSD Target 382 template<typename Target> 383 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 384 protected: 385 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 386 MacroBuilder &Builder) const { 387 // OpenBSD defines; list based off of gcc output 388 389 Builder.defineMacro("__OpenBSD__"); 390 DefineStd(Builder, "unix", Opts); 391 Builder.defineMacro("__ELF__"); 392 if (Opts.POSIXThreads) 393 Builder.defineMacro("_REENTRANT"); 394 } 395 public: 396 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 397 this->UserLabelPrefix = ""; 398 this->TLSSupported = false; 399 400 switch (Triple.getArch()) { 401 default: 402 case llvm::Triple::x86: 403 case llvm::Triple::x86_64: 404 case llvm::Triple::arm: 405 case llvm::Triple::sparc: 406 this->MCountName = "__mcount"; 407 break; 408 case llvm::Triple::mips64: 409 case llvm::Triple::mips64el: 410 case llvm::Triple::ppc: 411 case llvm::Triple::sparcv9: 412 this->MCountName = "_mcount"; 413 break; 414 } 415 } 416 }; 417 418 // Bitrig Target 419 template<typename Target> 420 class BitrigTargetInfo : public OSTargetInfo<Target> { 421 protected: 422 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 423 MacroBuilder &Builder) const { 424 // Bitrig defines; list based off of gcc output 425 426 Builder.defineMacro("__Bitrig__"); 427 DefineStd(Builder, "unix", Opts); 428 Builder.defineMacro("__ELF__"); 429 if (Opts.POSIXThreads) 430 Builder.defineMacro("_REENTRANT"); 431 } 432 public: 433 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 434 this->UserLabelPrefix = ""; 435 this->TLSSupported = false; 436 this->MCountName = "__mcount"; 437 } 438 }; 439 440 // PSP Target 441 template<typename Target> 442 class PSPTargetInfo : public OSTargetInfo<Target> { 443 protected: 444 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 445 MacroBuilder &Builder) const { 446 // PSP defines; list based on the output of the pspdev gcc toolchain. 447 Builder.defineMacro("PSP"); 448 Builder.defineMacro("_PSP"); 449 Builder.defineMacro("__psp__"); 450 Builder.defineMacro("__ELF__"); 451 } 452 public: 453 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 454 this->UserLabelPrefix = ""; 455 } 456 }; 457 458 // PS3 PPU Target 459 template<typename Target> 460 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 461 protected: 462 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 463 MacroBuilder &Builder) const { 464 // PS3 PPU defines. 465 Builder.defineMacro("__PPC__"); 466 Builder.defineMacro("__PPU__"); 467 Builder.defineMacro("__CELLOS_LV2__"); 468 Builder.defineMacro("__ELF__"); 469 Builder.defineMacro("__LP32__"); 470 Builder.defineMacro("_ARCH_PPC64"); 471 Builder.defineMacro("__powerpc64__"); 472 } 473 public: 474 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 475 this->UserLabelPrefix = ""; 476 this->LongWidth = this->LongAlign = 32; 477 this->PointerWidth = this->PointerAlign = 32; 478 this->IntMaxType = TargetInfo::SignedLongLong; 479 this->UIntMaxType = TargetInfo::UnsignedLongLong; 480 this->Int64Type = TargetInfo::SignedLongLong; 481 this->SizeType = TargetInfo::UnsignedInt; 482 this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 483 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"; 484 } 485 }; 486 487 // FIXME: Need a real SPU target. 488 // PS3 SPU Target 489 template<typename Target> 490 class PS3SPUTargetInfo : public OSTargetInfo<Target> { 491 protected: 492 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 493 MacroBuilder &Builder) const { 494 // PS3 PPU defines. 495 Builder.defineMacro("__SPU__"); 496 Builder.defineMacro("__ELF__"); 497 } 498 public: 499 PS3SPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 500 this->UserLabelPrefix = ""; 501 } 502 }; 503 504 // AuroraUX target 505 template<typename Target> 506 class AuroraUXTargetInfo : public OSTargetInfo<Target> { 507 protected: 508 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 509 MacroBuilder &Builder) const { 510 DefineStd(Builder, "sun", Opts); 511 DefineStd(Builder, "unix", Opts); 512 Builder.defineMacro("__ELF__"); 513 Builder.defineMacro("__svr4__"); 514 Builder.defineMacro("__SVR4"); 515 } 516 public: 517 AuroraUXTargetInfo(const llvm::Triple &Triple) 518 : OSTargetInfo<Target>(Triple) { 519 this->UserLabelPrefix = ""; 520 this->WCharType = this->SignedLong; 521 // FIXME: WIntType should be SignedLong 522 } 523 }; 524 525 // Solaris target 526 template<typename Target> 527 class SolarisTargetInfo : public OSTargetInfo<Target> { 528 protected: 529 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 530 MacroBuilder &Builder) const { 531 DefineStd(Builder, "sun", Opts); 532 DefineStd(Builder, "unix", Opts); 533 Builder.defineMacro("__ELF__"); 534 Builder.defineMacro("__svr4__"); 535 Builder.defineMacro("__SVR4"); 536 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 537 // newer, but to 500 for everything else. feature_test.h has a check to 538 // ensure that you are not using C99 with an old version of X/Open or C89 539 // with a new version. 540 if (Opts.C99 || Opts.C11) 541 Builder.defineMacro("_XOPEN_SOURCE", "600"); 542 else 543 Builder.defineMacro("_XOPEN_SOURCE", "500"); 544 if (Opts.CPlusPlus) 545 Builder.defineMacro("__C99FEATURES__"); 546 Builder.defineMacro("_LARGEFILE_SOURCE"); 547 Builder.defineMacro("_LARGEFILE64_SOURCE"); 548 Builder.defineMacro("__EXTENSIONS__"); 549 Builder.defineMacro("_REENTRANT"); 550 } 551 public: 552 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 553 this->UserLabelPrefix = ""; 554 this->WCharType = this->SignedInt; 555 // FIXME: WIntType should be SignedLong 556 } 557 }; 558 559 // Windows target 560 template<typename Target> 561 class WindowsTargetInfo : public OSTargetInfo<Target> { 562 protected: 563 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 564 MacroBuilder &Builder) const { 565 Builder.defineMacro("_WIN32"); 566 } 567 void getVisualStudioDefines(const LangOptions &Opts, 568 MacroBuilder &Builder) const { 569 if (Opts.CPlusPlus) { 570 if (Opts.RTTI) 571 Builder.defineMacro("_CPPRTTI"); 572 573 if (Opts.Exceptions) 574 Builder.defineMacro("_CPPUNWIND"); 575 } 576 577 if (!Opts.CharIsSigned) 578 Builder.defineMacro("_CHAR_UNSIGNED"); 579 580 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 581 // but it works for now. 582 if (Opts.POSIXThreads) 583 Builder.defineMacro("_MT"); 584 585 if (Opts.MSCVersion != 0) 586 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion)); 587 588 if (Opts.MicrosoftExt) { 589 Builder.defineMacro("_MSC_EXTENSIONS"); 590 591 if (Opts.CPlusPlus11) { 592 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 593 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 594 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 595 } 596 } 597 598 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 599 } 600 601 public: 602 WindowsTargetInfo(const llvm::Triple &Triple) 603 : OSTargetInfo<Target>(Triple) {} 604 }; 605 606 template <typename Target> 607 class NaClTargetInfo : public OSTargetInfo<Target> { 608 protected: 609 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 610 MacroBuilder &Builder) const { 611 if (Opts.POSIXThreads) 612 Builder.defineMacro("_REENTRANT"); 613 if (Opts.CPlusPlus) 614 Builder.defineMacro("_GNU_SOURCE"); 615 616 DefineStd(Builder, "unix", Opts); 617 Builder.defineMacro("__ELF__"); 618 Builder.defineMacro("__native_client__"); 619 } 620 621 public: 622 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 623 this->UserLabelPrefix = ""; 624 this->LongAlign = 32; 625 this->LongWidth = 32; 626 this->PointerAlign = 32; 627 this->PointerWidth = 32; 628 this->IntMaxType = TargetInfo::SignedLongLong; 629 this->UIntMaxType = TargetInfo::UnsignedLongLong; 630 this->Int64Type = TargetInfo::SignedLongLong; 631 this->DoubleAlign = 64; 632 this->LongDoubleWidth = 64; 633 this->LongDoubleAlign = 64; 634 this->SizeType = TargetInfo::UnsignedInt; 635 this->PtrDiffType = TargetInfo::SignedInt; 636 this->IntPtrType = TargetInfo::SignedInt; 637 // RegParmMax is inherited from the underlying architecture 638 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 639 this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 640 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32"; 641 } 642 virtual typename Target::CallingConvCheckResult checkCallingConvention( 643 CallingConv CC) const { 644 return CC == CC_PnaclCall ? Target::CCCR_OK : 645 Target::checkCallingConvention(CC); 646 } 647 }; 648 } // end anonymous namespace. 649 650 //===----------------------------------------------------------------------===// 651 // Specific target implementations. 652 //===----------------------------------------------------------------------===// 653 654 namespace { 655 // PPC abstract base class 656 class PPCTargetInfo : public TargetInfo { 657 static const Builtin::Info BuiltinInfo[]; 658 static const char * const GCCRegNames[]; 659 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 660 std::string CPU; 661 public: 662 PPCTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 663 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 664 LongDoubleWidth = LongDoubleAlign = 128; 665 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 666 } 667 668 /// \brief Flags for architecture specific defines. 669 typedef enum { 670 ArchDefineNone = 0, 671 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 672 ArchDefinePpcgr = 1 << 1, 673 ArchDefinePpcsq = 1 << 2, 674 ArchDefine440 = 1 << 3, 675 ArchDefine603 = 1 << 4, 676 ArchDefine604 = 1 << 5, 677 ArchDefinePwr4 = 1 << 6, 678 ArchDefinePwr5 = 1 << 7, 679 ArchDefinePwr5x = 1 << 8, 680 ArchDefinePwr6 = 1 << 9, 681 ArchDefinePwr6x = 1 << 10, 682 ArchDefinePwr7 = 1 << 11, 683 ArchDefineA2 = 1 << 12, 684 ArchDefineA2q = 1 << 13 685 } ArchDefineTypes; 686 687 // Note: GCC recognizes the following additional cpus: 688 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 689 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 690 // titan, rs64. 691 virtual bool setCPU(const std::string &Name) { 692 bool CPUKnown = llvm::StringSwitch<bool>(Name) 693 .Case("generic", true) 694 .Case("440", true) 695 .Case("450", true) 696 .Case("601", true) 697 .Case("602", true) 698 .Case("603", true) 699 .Case("603e", true) 700 .Case("603ev", true) 701 .Case("604", true) 702 .Case("604e", true) 703 .Case("620", true) 704 .Case("630", true) 705 .Case("g3", true) 706 .Case("7400", true) 707 .Case("g4", true) 708 .Case("7450", true) 709 .Case("g4+", true) 710 .Case("750", true) 711 .Case("970", true) 712 .Case("g5", true) 713 .Case("a2", true) 714 .Case("a2q", true) 715 .Case("e500mc", true) 716 .Case("e5500", true) 717 .Case("power3", true) 718 .Case("pwr3", true) 719 .Case("power4", true) 720 .Case("pwr4", true) 721 .Case("power5", true) 722 .Case("pwr5", true) 723 .Case("power5x", true) 724 .Case("pwr5x", true) 725 .Case("power6", true) 726 .Case("pwr6", true) 727 .Case("power6x", true) 728 .Case("pwr6x", true) 729 .Case("power7", true) 730 .Case("pwr7", true) 731 .Case("powerpc", true) 732 .Case("ppc", true) 733 .Case("powerpc64", true) 734 .Case("ppc64", true) 735 .Case("powerpc64le", true) 736 .Case("ppc64le", true) 737 .Default(false); 738 739 if (CPUKnown) 740 CPU = Name; 741 742 return CPUKnown; 743 } 744 745 virtual void getTargetBuiltins(const Builtin::Info *&Records, 746 unsigned &NumRecords) const { 747 Records = BuiltinInfo; 748 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 749 } 750 751 virtual bool isCLZForZeroUndef() const { return false; } 752 753 virtual void getTargetDefines(const LangOptions &Opts, 754 MacroBuilder &Builder) const; 755 756 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 757 758 virtual bool hasFeature(StringRef Feature) const; 759 760 virtual void getGCCRegNames(const char * const *&Names, 761 unsigned &NumNames) const; 762 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 763 unsigned &NumAliases) const; 764 virtual bool validateAsmConstraint(const char *&Name, 765 TargetInfo::ConstraintInfo &Info) const { 766 switch (*Name) { 767 default: return false; 768 case 'O': // Zero 769 break; 770 case 'b': // Base register 771 case 'f': // Floating point register 772 Info.setAllowsRegister(); 773 break; 774 // FIXME: The following are added to allow parsing. 775 // I just took a guess at what the actions should be. 776 // Also, is more specific checking needed? I.e. specific registers? 777 case 'd': // Floating point register (containing 64-bit value) 778 case 'v': // Altivec vector register 779 Info.setAllowsRegister(); 780 break; 781 case 'w': 782 switch (Name[1]) { 783 case 'd':// VSX vector register to hold vector double data 784 case 'f':// VSX vector register to hold vector float data 785 case 's':// VSX vector register to hold scalar float data 786 case 'a':// Any VSX register 787 break; 788 default: 789 return false; 790 } 791 Info.setAllowsRegister(); 792 Name++; // Skip over 'w'. 793 break; 794 case 'h': // `MQ', `CTR', or `LINK' register 795 case 'q': // `MQ' register 796 case 'c': // `CTR' register 797 case 'l': // `LINK' register 798 case 'x': // `CR' register (condition register) number 0 799 case 'y': // `CR' register (condition register) 800 case 'z': // `XER[CA]' carry bit (part of the XER register) 801 Info.setAllowsRegister(); 802 break; 803 case 'I': // Signed 16-bit constant 804 case 'J': // Unsigned 16-bit constant shifted left 16 bits 805 // (use `L' instead for SImode constants) 806 case 'K': // Unsigned 16-bit constant 807 case 'L': // Signed 16-bit constant shifted left 16 bits 808 case 'M': // Constant larger than 31 809 case 'N': // Exact power of 2 810 case 'P': // Constant whose negation is a signed 16-bit constant 811 case 'G': // Floating point constant that can be loaded into a 812 // register with one instruction per word 813 case 'H': // Integer/Floating point constant that can be loaded 814 // into a register using three instructions 815 break; 816 case 'm': // Memory operand. Note that on PowerPC targets, m can 817 // include addresses that update the base register. It 818 // is therefore only safe to use `m' in an asm statement 819 // if that asm statement accesses the operand exactly once. 820 // The asm statement must also use `%U<opno>' as a 821 // placeholder for the "update" flag in the corresponding 822 // load or store instruction. For example: 823 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 824 // is correct but: 825 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 826 // is not. Use es rather than m if you don't want the base 827 // register to be updated. 828 case 'e': 829 if (Name[1] != 's') 830 return false; 831 // es: A "stable" memory operand; that is, one which does not 832 // include any automodification of the base register. Unlike 833 // `m', this constraint can be used in asm statements that 834 // might access the operand several times, or that might not 835 // access it at all. 836 Info.setAllowsMemory(); 837 Name++; // Skip over 'e'. 838 break; 839 case 'Q': // Memory operand that is an offset from a register (it is 840 // usually better to use `m' or `es' in asm statements) 841 case 'Z': // Memory operand that is an indexed or indirect from a 842 // register (it is usually better to use `m' or `es' in 843 // asm statements) 844 Info.setAllowsMemory(); 845 Info.setAllowsRegister(); 846 break; 847 case 'R': // AIX TOC entry 848 case 'a': // Address operand that is an indexed or indirect from a 849 // register (`p' is preferable for asm statements) 850 case 'S': // Constant suitable as a 64-bit mask operand 851 case 'T': // Constant suitable as a 32-bit mask operand 852 case 'U': // System V Release 4 small data area reference 853 case 't': // AND masks that can be performed by two rldic{l, r} 854 // instructions 855 case 'W': // Vector constant that does not require memory 856 case 'j': // Vector constant that is all zeros. 857 break; 858 // End FIXME. 859 } 860 return true; 861 } 862 virtual const char *getClobbers() const { 863 return ""; 864 } 865 int getEHDataRegisterNumber(unsigned RegNo) const { 866 if (RegNo == 0) return 3; 867 if (RegNo == 1) return 4; 868 return -1; 869 } 870 }; 871 872 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 873 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 874 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 875 ALL_LANGUAGES }, 876 #include "clang/Basic/BuiltinsPPC.def" 877 }; 878 879 880 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 881 /// #defines that are not tied to a specific subtarget. 882 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 883 MacroBuilder &Builder) const { 884 // Target identification. 885 Builder.defineMacro("__ppc__"); 886 Builder.defineMacro("__PPC__"); 887 Builder.defineMacro("_ARCH_PPC"); 888 Builder.defineMacro("__powerpc__"); 889 Builder.defineMacro("__POWERPC__"); 890 if (PointerWidth == 64) { 891 Builder.defineMacro("_ARCH_PPC64"); 892 Builder.defineMacro("__powerpc64__"); 893 Builder.defineMacro("__ppc64__"); 894 Builder.defineMacro("__PPC64__"); 895 } 896 897 // Target properties. 898 if (getTriple().getArch() == llvm::Triple::ppc64le) { 899 Builder.defineMacro("_LITTLE_ENDIAN"); 900 Builder.defineMacro("__LITTLE_ENDIAN__"); 901 } else { 902 if (getTriple().getOS() != llvm::Triple::NetBSD && 903 getTriple().getOS() != llvm::Triple::OpenBSD) 904 Builder.defineMacro("_BIG_ENDIAN"); 905 Builder.defineMacro("__BIG_ENDIAN__"); 906 } 907 908 // Subtarget options. 909 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 910 Builder.defineMacro("__REGISTER_PREFIX__", ""); 911 912 // FIXME: Should be controlled by command line option. 913 if (LongDoubleWidth == 128) 914 Builder.defineMacro("__LONG_DOUBLE_128__"); 915 916 if (Opts.AltiVec) { 917 Builder.defineMacro("__VEC__", "10206"); 918 Builder.defineMacro("__ALTIVEC__"); 919 } 920 921 // CPU identification. 922 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 923 .Case("440", ArchDefineName) 924 .Case("450", ArchDefineName | ArchDefine440) 925 .Case("601", ArchDefineName) 926 .Case("602", ArchDefineName | ArchDefinePpcgr) 927 .Case("603", ArchDefineName | ArchDefinePpcgr) 928 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 929 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 930 .Case("604", ArchDefineName | ArchDefinePpcgr) 931 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 932 .Case("620", ArchDefineName | ArchDefinePpcgr) 933 .Case("630", ArchDefineName | ArchDefinePpcgr) 934 .Case("7400", ArchDefineName | ArchDefinePpcgr) 935 .Case("7450", ArchDefineName | ArchDefinePpcgr) 936 .Case("750", ArchDefineName | ArchDefinePpcgr) 937 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 938 | ArchDefinePpcsq) 939 .Case("a2", ArchDefineA2) 940 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 941 .Case("pwr3", ArchDefinePpcgr) 942 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 943 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 944 | ArchDefinePpcsq) 945 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 946 | ArchDefinePpcgr | ArchDefinePpcsq) 947 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 948 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 949 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 950 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 951 | ArchDefinePpcsq) 952 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 953 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 954 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 955 .Case("power3", ArchDefinePpcgr) 956 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 957 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 958 | ArchDefinePpcsq) 959 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 960 | ArchDefinePpcgr | ArchDefinePpcsq) 961 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 962 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 963 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 964 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 965 | ArchDefinePpcsq) 966 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 967 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 968 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 969 .Default(ArchDefineNone); 970 971 if (defs & ArchDefineName) 972 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 973 if (defs & ArchDefinePpcgr) 974 Builder.defineMacro("_ARCH_PPCGR"); 975 if (defs & ArchDefinePpcsq) 976 Builder.defineMacro("_ARCH_PPCSQ"); 977 if (defs & ArchDefine440) 978 Builder.defineMacro("_ARCH_440"); 979 if (defs & ArchDefine603) 980 Builder.defineMacro("_ARCH_603"); 981 if (defs & ArchDefine604) 982 Builder.defineMacro("_ARCH_604"); 983 if (defs & ArchDefinePwr4) 984 Builder.defineMacro("_ARCH_PWR4"); 985 if (defs & ArchDefinePwr5) 986 Builder.defineMacro("_ARCH_PWR5"); 987 if (defs & ArchDefinePwr5x) 988 Builder.defineMacro("_ARCH_PWR5X"); 989 if (defs & ArchDefinePwr6) 990 Builder.defineMacro("_ARCH_PWR6"); 991 if (defs & ArchDefinePwr6x) 992 Builder.defineMacro("_ARCH_PWR6X"); 993 if (defs & ArchDefinePwr7) 994 Builder.defineMacro("_ARCH_PWR7"); 995 if (defs & ArchDefineA2) 996 Builder.defineMacro("_ARCH_A2"); 997 if (defs & ArchDefineA2q) { 998 Builder.defineMacro("_ARCH_A2Q"); 999 Builder.defineMacro("_ARCH_QP"); 1000 } 1001 1002 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1003 Builder.defineMacro("__bg__"); 1004 Builder.defineMacro("__THW_BLUEGENE__"); 1005 Builder.defineMacro("__bgq__"); 1006 Builder.defineMacro("__TOS_BGQ__"); 1007 } 1008 1009 // FIXME: The following are not yet generated here by Clang, but are 1010 // generated by GCC: 1011 // 1012 // _SOFT_FLOAT_ 1013 // __RECIP_PRECISION__ 1014 // __APPLE_ALTIVEC__ 1015 // __VSX__ 1016 // __RECIP__ 1017 // __RECIPF__ 1018 // __RSQRTE__ 1019 // __RSQRTEF__ 1020 // _SOFT_DOUBLE_ 1021 // __NO_LWSYNC__ 1022 // __HAVE_BSWAP__ 1023 // __LONGDOUBLE128 1024 // __CMODEL_MEDIUM__ 1025 // __CMODEL_LARGE__ 1026 // _CALL_SYSV 1027 // _CALL_DARWIN 1028 // __NO_FPRS__ 1029 } 1030 1031 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1032 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1033 .Case("7400", true) 1034 .Case("g4", true) 1035 .Case("7450", true) 1036 .Case("g4+", true) 1037 .Case("970", true) 1038 .Case("g5", true) 1039 .Case("pwr6", true) 1040 .Case("pwr7", true) 1041 .Case("ppc64", true) 1042 .Case("ppc64le", true) 1043 .Default(false); 1044 1045 Features["qpx"] = (CPU == "a2q"); 1046 } 1047 1048 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1049 return Feature == "powerpc"; 1050 } 1051 1052 1053 const char * const PPCTargetInfo::GCCRegNames[] = { 1054 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1055 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1056 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1057 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1058 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1059 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1060 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1061 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1062 "mq", "lr", "ctr", "ap", 1063 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1064 "xer", 1065 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1066 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1067 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1068 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1069 "vrsave", "vscr", 1070 "spe_acc", "spefscr", 1071 "sfp" 1072 }; 1073 1074 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1075 unsigned &NumNames) const { 1076 Names = GCCRegNames; 1077 NumNames = llvm::array_lengthof(GCCRegNames); 1078 } 1079 1080 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1081 // While some of these aliases do map to different registers 1082 // they still share the same register name. 1083 { { "0" }, "r0" }, 1084 { { "1"}, "r1" }, 1085 { { "2" }, "r2" }, 1086 { { "3" }, "r3" }, 1087 { { "4" }, "r4" }, 1088 { { "5" }, "r5" }, 1089 { { "6" }, "r6" }, 1090 { { "7" }, "r7" }, 1091 { { "8" }, "r8" }, 1092 { { "9" }, "r9" }, 1093 { { "10" }, "r10" }, 1094 { { "11" }, "r11" }, 1095 { { "12" }, "r12" }, 1096 { { "13" }, "r13" }, 1097 { { "14" }, "r14" }, 1098 { { "15" }, "r15" }, 1099 { { "16" }, "r16" }, 1100 { { "17" }, "r17" }, 1101 { { "18" }, "r18" }, 1102 { { "19" }, "r19" }, 1103 { { "20" }, "r20" }, 1104 { { "21" }, "r21" }, 1105 { { "22" }, "r22" }, 1106 { { "23" }, "r23" }, 1107 { { "24" }, "r24" }, 1108 { { "25" }, "r25" }, 1109 { { "26" }, "r26" }, 1110 { { "27" }, "r27" }, 1111 { { "28" }, "r28" }, 1112 { { "29" }, "r29" }, 1113 { { "30" }, "r30" }, 1114 { { "31" }, "r31" }, 1115 { { "fr0" }, "f0" }, 1116 { { "fr1" }, "f1" }, 1117 { { "fr2" }, "f2" }, 1118 { { "fr3" }, "f3" }, 1119 { { "fr4" }, "f4" }, 1120 { { "fr5" }, "f5" }, 1121 { { "fr6" }, "f6" }, 1122 { { "fr7" }, "f7" }, 1123 { { "fr8" }, "f8" }, 1124 { { "fr9" }, "f9" }, 1125 { { "fr10" }, "f10" }, 1126 { { "fr11" }, "f11" }, 1127 { { "fr12" }, "f12" }, 1128 { { "fr13" }, "f13" }, 1129 { { "fr14" }, "f14" }, 1130 { { "fr15" }, "f15" }, 1131 { { "fr16" }, "f16" }, 1132 { { "fr17" }, "f17" }, 1133 { { "fr18" }, "f18" }, 1134 { { "fr19" }, "f19" }, 1135 { { "fr20" }, "f20" }, 1136 { { "fr21" }, "f21" }, 1137 { { "fr22" }, "f22" }, 1138 { { "fr23" }, "f23" }, 1139 { { "fr24" }, "f24" }, 1140 { { "fr25" }, "f25" }, 1141 { { "fr26" }, "f26" }, 1142 { { "fr27" }, "f27" }, 1143 { { "fr28" }, "f28" }, 1144 { { "fr29" }, "f29" }, 1145 { { "fr30" }, "f30" }, 1146 { { "fr31" }, "f31" }, 1147 { { "cc" }, "cr0" }, 1148 }; 1149 1150 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1151 unsigned &NumAliases) const { 1152 Aliases = GCCRegAliases; 1153 NumAliases = llvm::array_lengthof(GCCRegAliases); 1154 } 1155 } // end anonymous namespace. 1156 1157 namespace { 1158 class PPC32TargetInfo : public PPCTargetInfo { 1159 public: 1160 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1161 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1162 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"; 1163 1164 switch (getTriple().getOS()) { 1165 case llvm::Triple::Linux: 1166 case llvm::Triple::FreeBSD: 1167 case llvm::Triple::NetBSD: 1168 SizeType = UnsignedInt; 1169 PtrDiffType = SignedInt; 1170 IntPtrType = SignedInt; 1171 break; 1172 default: 1173 break; 1174 } 1175 1176 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1177 LongDoubleWidth = LongDoubleAlign = 64; 1178 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1179 } 1180 1181 // PPC32 supports atomics up to 4 bytes. 1182 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1183 } 1184 1185 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1186 // This is the ELF definition, and is overridden by the Darwin sub-target 1187 return TargetInfo::PowerABIBuiltinVaList; 1188 } 1189 }; 1190 } // end anonymous namespace. 1191 1192 // Note: ABI differences may eventually require us to have a separate 1193 // TargetInfo for little endian. 1194 namespace { 1195 class PPC64TargetInfo : public PPCTargetInfo { 1196 public: 1197 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1198 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1199 IntMaxType = SignedLong; 1200 UIntMaxType = UnsignedLong; 1201 Int64Type = SignedLong; 1202 1203 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1204 LongDoubleWidth = LongDoubleAlign = 64; 1205 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1206 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1207 "i64:64:64-f32:32:32-f64:64:64-" 1208 "v128:128:128-n32:64"; 1209 } else 1210 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1211 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 1212 "v128:128:128-n32:64"; 1213 1214 // PPC64 supports atomics up to 8 bytes. 1215 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1216 } 1217 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1218 return TargetInfo::CharPtrBuiltinVaList; 1219 } 1220 }; 1221 } // end anonymous namespace. 1222 1223 1224 namespace { 1225 class DarwinPPC32TargetInfo : 1226 public DarwinTargetInfo<PPC32TargetInfo> { 1227 public: 1228 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1229 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1230 HasAlignMac68kSupport = true; 1231 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1232 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1233 LongLongAlign = 32; 1234 SuitableAlign = 128; 1235 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1236 "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32"; 1237 } 1238 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1239 return TargetInfo::CharPtrBuiltinVaList; 1240 } 1241 }; 1242 1243 class DarwinPPC64TargetInfo : 1244 public DarwinTargetInfo<PPC64TargetInfo> { 1245 public: 1246 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1247 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1248 HasAlignMac68kSupport = true; 1249 SuitableAlign = 128; 1250 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1251 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"; 1252 } 1253 }; 1254 } // end anonymous namespace. 1255 1256 namespace { 1257 static const unsigned NVPTXAddrSpaceMap[] = { 1258 1, // opencl_global 1259 3, // opencl_local 1260 4, // opencl_constant 1261 1, // cuda_device 1262 4, // cuda_constant 1263 3, // cuda_shared 1264 }; 1265 class NVPTXTargetInfo : public TargetInfo { 1266 static const char * const GCCRegNames[]; 1267 static const Builtin::Info BuiltinInfo[]; 1268 public: 1269 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1270 BigEndian = false; 1271 TLSSupported = false; 1272 LongWidth = LongAlign = 64; 1273 AddrSpaceMap = &NVPTXAddrSpaceMap; 1274 UseAddrSpaceMapMangling = true; 1275 // Define available target features 1276 // These must be defined in sorted order! 1277 NoAsmVariants = true; 1278 } 1279 virtual void getTargetDefines(const LangOptions &Opts, 1280 MacroBuilder &Builder) const { 1281 Builder.defineMacro("__PTX__"); 1282 Builder.defineMacro("__NVPTX__"); 1283 } 1284 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1285 unsigned &NumRecords) const { 1286 Records = BuiltinInfo; 1287 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1288 } 1289 virtual bool hasFeature(StringRef Feature) const { 1290 return Feature == "ptx" || Feature == "nvptx"; 1291 } 1292 1293 virtual void getGCCRegNames(const char * const *&Names, 1294 unsigned &NumNames) const; 1295 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1296 unsigned &NumAliases) const { 1297 // No aliases. 1298 Aliases = 0; 1299 NumAliases = 0; 1300 } 1301 virtual bool validateAsmConstraint(const char *&Name, 1302 TargetInfo::ConstraintInfo &Info) const { 1303 switch (*Name) { 1304 default: return false; 1305 case 'c': 1306 case 'h': 1307 case 'r': 1308 case 'l': 1309 case 'f': 1310 case 'd': 1311 Info.setAllowsRegister(); 1312 return true; 1313 } 1314 } 1315 virtual const char *getClobbers() const { 1316 // FIXME: Is this really right? 1317 return ""; 1318 } 1319 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1320 // FIXME: implement 1321 return TargetInfo::CharPtrBuiltinVaList; 1322 } 1323 virtual bool setCPU(const std::string &Name) { 1324 bool Valid = llvm::StringSwitch<bool>(Name) 1325 .Case("sm_20", true) 1326 .Case("sm_21", true) 1327 .Case("sm_30", true) 1328 .Case("sm_35", true) 1329 .Default(false); 1330 1331 return Valid; 1332 } 1333 }; 1334 1335 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1336 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1337 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1338 ALL_LANGUAGES }, 1339 #include "clang/Basic/BuiltinsNVPTX.def" 1340 }; 1341 1342 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1343 "r0" 1344 }; 1345 1346 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1347 unsigned &NumNames) const { 1348 Names = GCCRegNames; 1349 NumNames = llvm::array_lengthof(GCCRegNames); 1350 } 1351 1352 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1353 public: 1354 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1355 PointerWidth = PointerAlign = 32; 1356 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt; 1357 DescriptionString 1358 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 1359 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-" 1360 "n16:32:64"; 1361 } 1362 }; 1363 1364 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1365 public: 1366 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1367 PointerWidth = PointerAlign = 64; 1368 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong; 1369 DescriptionString 1370 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 1371 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-" 1372 "n16:32:64"; 1373 } 1374 }; 1375 } 1376 1377 namespace { 1378 1379 static const unsigned R600AddrSpaceMap[] = { 1380 1, // opencl_global 1381 3, // opencl_local 1382 2, // opencl_constant 1383 1, // cuda_device 1384 2, // cuda_constant 1385 3 // cuda_shared 1386 }; 1387 1388 static const char *DescriptionStringR600 = 1389 "e" 1390 "-p:32:32:32" 1391 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32" 1392 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128" 1393 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048" 1394 "-n32:64"; 1395 1396 static const char *DescriptionStringR600DoubleOps = 1397 "e" 1398 "-p:32:32:32" 1399 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64" 1400 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128" 1401 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048" 1402 "-n32:64"; 1403 1404 static const char *DescriptionStringSI = 1405 "e" 1406 "-p:64:64:64" 1407 "-p3:32:32:32" 1408 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64" 1409 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128" 1410 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048" 1411 "-n32:64"; 1412 1413 class R600TargetInfo : public TargetInfo { 1414 /// \brief The GPU profiles supported by the R600 target. 1415 enum GPUKind { 1416 GK_NONE, 1417 GK_R600, 1418 GK_R600_DOUBLE_OPS, 1419 GK_R700, 1420 GK_R700_DOUBLE_OPS, 1421 GK_EVERGREEN, 1422 GK_EVERGREEN_DOUBLE_OPS, 1423 GK_NORTHERN_ISLANDS, 1424 GK_CAYMAN, 1425 GK_SOUTHERN_ISLANDS 1426 } GPU; 1427 1428 public: 1429 R600TargetInfo(const llvm::Triple &Triple) 1430 : TargetInfo(Triple), GPU(GK_R600) { 1431 DescriptionString = DescriptionStringR600; 1432 AddrSpaceMap = &R600AddrSpaceMap; 1433 UseAddrSpaceMapMangling = true; 1434 } 1435 1436 virtual const char * getClobbers() const { 1437 return ""; 1438 } 1439 1440 virtual void getGCCRegNames(const char * const *&Names, 1441 unsigned &numNames) const { 1442 Names = NULL; 1443 numNames = 0; 1444 } 1445 1446 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1447 unsigned &NumAliases) const { 1448 Aliases = NULL; 1449 NumAliases = 0; 1450 } 1451 1452 virtual bool validateAsmConstraint(const char *&Name, 1453 TargetInfo::ConstraintInfo &info) const { 1454 return true; 1455 } 1456 1457 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1458 unsigned &NumRecords) const { 1459 Records = NULL; 1460 NumRecords = 0; 1461 } 1462 1463 1464 virtual void getTargetDefines(const LangOptions &Opts, 1465 MacroBuilder &Builder) const { 1466 Builder.defineMacro("__R600__"); 1467 } 1468 1469 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1470 return TargetInfo::CharPtrBuiltinVaList; 1471 } 1472 1473 virtual bool setCPU(const std::string &Name) { 1474 GPU = llvm::StringSwitch<GPUKind>(Name) 1475 .Case("r600" , GK_R600) 1476 .Case("rv610", GK_R600) 1477 .Case("rv620", GK_R600) 1478 .Case("rv630", GK_R600) 1479 .Case("rv635", GK_R600) 1480 .Case("rs780", GK_R600) 1481 .Case("rs880", GK_R600) 1482 .Case("rv670", GK_R600_DOUBLE_OPS) 1483 .Case("rv710", GK_R700) 1484 .Case("rv730", GK_R700) 1485 .Case("rv740", GK_R700_DOUBLE_OPS) 1486 .Case("rv770", GK_R700_DOUBLE_OPS) 1487 .Case("palm", GK_EVERGREEN) 1488 .Case("cedar", GK_EVERGREEN) 1489 .Case("sumo", GK_EVERGREEN) 1490 .Case("sumo2", GK_EVERGREEN) 1491 .Case("redwood", GK_EVERGREEN) 1492 .Case("juniper", GK_EVERGREEN) 1493 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1494 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1495 .Case("barts", GK_NORTHERN_ISLANDS) 1496 .Case("turks", GK_NORTHERN_ISLANDS) 1497 .Case("caicos", GK_NORTHERN_ISLANDS) 1498 .Case("cayman", GK_CAYMAN) 1499 .Case("aruba", GK_CAYMAN) 1500 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1501 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1502 .Case("verde", GK_SOUTHERN_ISLANDS) 1503 .Case("oland", GK_SOUTHERN_ISLANDS) 1504 .Default(GK_NONE); 1505 1506 if (GPU == GK_NONE) { 1507 return false; 1508 } 1509 1510 // Set the correct data layout 1511 switch (GPU) { 1512 case GK_NONE: 1513 case GK_R600: 1514 case GK_R700: 1515 case GK_EVERGREEN: 1516 case GK_NORTHERN_ISLANDS: 1517 DescriptionString = DescriptionStringR600; 1518 break; 1519 case GK_R600_DOUBLE_OPS: 1520 case GK_R700_DOUBLE_OPS: 1521 case GK_EVERGREEN_DOUBLE_OPS: 1522 case GK_CAYMAN: 1523 DescriptionString = DescriptionStringR600DoubleOps; 1524 break; 1525 case GK_SOUTHERN_ISLANDS: 1526 DescriptionString = DescriptionStringSI; 1527 break; 1528 } 1529 1530 return true; 1531 } 1532 }; 1533 1534 } // end anonymous namespace 1535 1536 namespace { 1537 // Namespace for x86 abstract base class 1538 const Builtin::Info BuiltinInfo[] = { 1539 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1540 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1541 ALL_LANGUAGES }, 1542 #include "clang/Basic/BuiltinsX86.def" 1543 }; 1544 1545 static const char* const GCCRegNames[] = { 1546 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1547 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1548 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1549 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1550 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1551 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1552 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1553 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1554 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1555 }; 1556 1557 const TargetInfo::AddlRegName AddlRegNames[] = { 1558 { { "al", "ah", "eax", "rax" }, 0 }, 1559 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1560 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1561 { { "dl", "dh", "edx", "rdx" }, 1 }, 1562 { { "esi", "rsi" }, 4 }, 1563 { { "edi", "rdi" }, 5 }, 1564 { { "esp", "rsp" }, 7 }, 1565 { { "ebp", "rbp" }, 6 }, 1566 }; 1567 1568 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1569 // most of the implementation can be shared. 1570 class X86TargetInfo : public TargetInfo { 1571 enum X86SSEEnum { 1572 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1573 } SSELevel; 1574 enum MMX3DNowEnum { 1575 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1576 } MMX3DNowLevel; 1577 enum XOPEnum { 1578 NoXOP, 1579 SSE4A, 1580 FMA4, 1581 XOP 1582 } XOPLevel; 1583 1584 bool HasAES; 1585 bool HasPCLMUL; 1586 bool HasLZCNT; 1587 bool HasRDRND; 1588 bool HasBMI; 1589 bool HasBMI2; 1590 bool HasPOPCNT; 1591 bool HasRTM; 1592 bool HasPRFCHW; 1593 bool HasRDSEED; 1594 bool HasTBM; 1595 bool HasFMA; 1596 bool HasF16C; 1597 bool HasAVX512CD, HasAVX512ER, HasAVX512PF; 1598 bool HasSHA; 1599 bool HasCX16; 1600 1601 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1602 /// 1603 /// Each enumeration represents a particular CPU supported by Clang. These 1604 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1605 enum CPUKind { 1606 CK_Generic, 1607 1608 /// \name i386 1609 /// i386-generation processors. 1610 //@{ 1611 CK_i386, 1612 //@} 1613 1614 /// \name i486 1615 /// i486-generation processors. 1616 //@{ 1617 CK_i486, 1618 CK_WinChipC6, 1619 CK_WinChip2, 1620 CK_C3, 1621 //@} 1622 1623 /// \name i586 1624 /// i586-generation processors, P5 microarchitecture based. 1625 //@{ 1626 CK_i586, 1627 CK_Pentium, 1628 CK_PentiumMMX, 1629 //@} 1630 1631 /// \name i686 1632 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1633 //@{ 1634 CK_i686, 1635 CK_PentiumPro, 1636 CK_Pentium2, 1637 CK_Pentium3, 1638 CK_Pentium3M, 1639 CK_PentiumM, 1640 CK_C3_2, 1641 1642 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1643 /// Clang however has some logic to suport this. 1644 // FIXME: Warn, deprecate, and potentially remove this. 1645 CK_Yonah, 1646 //@} 1647 1648 /// \name Netburst 1649 /// Netburst microarchitecture based processors. 1650 //@{ 1651 CK_Pentium4, 1652 CK_Pentium4M, 1653 CK_Prescott, 1654 CK_Nocona, 1655 //@} 1656 1657 /// \name Core 1658 /// Core microarchitecture based processors. 1659 //@{ 1660 CK_Core2, 1661 1662 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1663 /// codename which GCC no longer accepts as an option to -march, but Clang 1664 /// has some logic for recognizing it. 1665 // FIXME: Warn, deprecate, and potentially remove this. 1666 CK_Penryn, 1667 //@} 1668 1669 /// \name Atom 1670 /// Atom processors 1671 //@{ 1672 CK_Atom, 1673 CK_Silvermont, 1674 //@} 1675 1676 /// \name Nehalem 1677 /// Nehalem microarchitecture based processors. 1678 //@{ 1679 CK_Corei7, 1680 CK_Corei7AVX, 1681 CK_CoreAVXi, 1682 CK_CoreAVX2, 1683 //@} 1684 1685 /// \name Knights Landing 1686 /// Knights Landing processor. 1687 CK_KNL, 1688 1689 /// \name K6 1690 /// K6 architecture processors. 1691 //@{ 1692 CK_K6, 1693 CK_K6_2, 1694 CK_K6_3, 1695 //@} 1696 1697 /// \name K7 1698 /// K7 architecture processors. 1699 //@{ 1700 CK_Athlon, 1701 CK_AthlonThunderbird, 1702 CK_Athlon4, 1703 CK_AthlonXP, 1704 CK_AthlonMP, 1705 //@} 1706 1707 /// \name K8 1708 /// K8 architecture processors. 1709 //@{ 1710 CK_Athlon64, 1711 CK_Athlon64SSE3, 1712 CK_AthlonFX, 1713 CK_K8, 1714 CK_K8SSE3, 1715 CK_Opteron, 1716 CK_OpteronSSE3, 1717 CK_AMDFAM10, 1718 //@} 1719 1720 /// \name Bobcat 1721 /// Bobcat architecture processors. 1722 //@{ 1723 CK_BTVER1, 1724 CK_BTVER2, 1725 //@} 1726 1727 /// \name Bulldozer 1728 /// Bulldozer architecture processors. 1729 //@{ 1730 CK_BDVER1, 1731 CK_BDVER2, 1732 //@} 1733 1734 /// This specification is deprecated and will be removed in the future. 1735 /// Users should prefer \see CK_K8. 1736 // FIXME: Warn on this when the CPU is set to it. 1737 CK_x86_64, 1738 //@} 1739 1740 /// \name Geode 1741 /// Geode processors. 1742 //@{ 1743 CK_Geode 1744 //@} 1745 } CPU; 1746 1747 enum FPMathKind { 1748 FP_Default, 1749 FP_SSE, 1750 FP_387 1751 } FPMath; 1752 1753 public: 1754 X86TargetInfo(const llvm::Triple &Triple) 1755 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1756 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 1757 HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false), 1758 HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasTBM(false), 1759 HasFMA(false), HasF16C(false), HasAVX512CD(false), HasAVX512ER(false), 1760 HasAVX512PF(false), HasSHA(false), HasCX16(false), CPU(CK_Generic), 1761 FPMath(FP_Default) { 1762 BigEndian = false; 1763 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1764 } 1765 virtual unsigned getFloatEvalMethod() const { 1766 // X87 evaluates with 80 bits "long double" precision. 1767 return SSELevel == NoSSE ? 2 : 0; 1768 } 1769 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1770 unsigned &NumRecords) const { 1771 Records = BuiltinInfo; 1772 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1773 } 1774 virtual void getGCCRegNames(const char * const *&Names, 1775 unsigned &NumNames) const { 1776 Names = GCCRegNames; 1777 NumNames = llvm::array_lengthof(GCCRegNames); 1778 } 1779 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1780 unsigned &NumAliases) const { 1781 Aliases = 0; 1782 NumAliases = 0; 1783 } 1784 virtual void getGCCAddlRegNames(const AddlRegName *&Names, 1785 unsigned &NumNames) const { 1786 Names = AddlRegNames; 1787 NumNames = llvm::array_lengthof(AddlRegNames); 1788 } 1789 virtual bool validateAsmConstraint(const char *&Name, 1790 TargetInfo::ConstraintInfo &info) const; 1791 virtual std::string convertConstraint(const char *&Constraint) const; 1792 virtual const char *getClobbers() const { 1793 return "~{dirflag},~{fpsr},~{flags}"; 1794 } 1795 virtual void getTargetDefines(const LangOptions &Opts, 1796 MacroBuilder &Builder) const; 1797 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 1798 bool Enabled); 1799 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 1800 bool Enabled); 1801 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 1802 bool Enabled); 1803 virtual void setFeatureEnabled(llvm::StringMap<bool> &Features, 1804 StringRef Name, bool Enabled) const { 1805 setFeatureEnabledImpl(Features, Name, Enabled); 1806 } 1807 // This exists purely to cut down on the number of virtual calls in 1808 // getDefaultFeatures which calls this repeatedly. 1809 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 1810 StringRef Name, bool Enabled); 1811 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 1812 virtual bool hasFeature(StringRef Feature) const; 1813 virtual bool HandleTargetFeatures(std::vector<std::string> &Features, 1814 DiagnosticsEngine &Diags); 1815 virtual const char* getABI() const { 1816 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 1817 return "avx"; 1818 else if (getTriple().getArch() == llvm::Triple::x86 && 1819 MMX3DNowLevel == NoMMX3DNow) 1820 return "no-mmx"; 1821 return ""; 1822 } 1823 virtual bool setCPU(const std::string &Name) { 1824 CPU = llvm::StringSwitch<CPUKind>(Name) 1825 .Case("i386", CK_i386) 1826 .Case("i486", CK_i486) 1827 .Case("winchip-c6", CK_WinChipC6) 1828 .Case("winchip2", CK_WinChip2) 1829 .Case("c3", CK_C3) 1830 .Case("i586", CK_i586) 1831 .Case("pentium", CK_Pentium) 1832 .Case("pentium-mmx", CK_PentiumMMX) 1833 .Case("i686", CK_i686) 1834 .Case("pentiumpro", CK_PentiumPro) 1835 .Case("pentium2", CK_Pentium2) 1836 .Case("pentium3", CK_Pentium3) 1837 .Case("pentium3m", CK_Pentium3M) 1838 .Case("pentium-m", CK_PentiumM) 1839 .Case("c3-2", CK_C3_2) 1840 .Case("yonah", CK_Yonah) 1841 .Case("pentium4", CK_Pentium4) 1842 .Case("pentium4m", CK_Pentium4M) 1843 .Case("prescott", CK_Prescott) 1844 .Case("nocona", CK_Nocona) 1845 .Case("core2", CK_Core2) 1846 .Case("penryn", CK_Penryn) 1847 .Case("atom", CK_Atom) 1848 .Case("slm", CK_Silvermont) 1849 .Case("corei7", CK_Corei7) 1850 .Case("corei7-avx", CK_Corei7AVX) 1851 .Case("core-avx-i", CK_CoreAVXi) 1852 .Case("core-avx2", CK_CoreAVX2) 1853 .Case("knl", CK_KNL) 1854 .Case("k6", CK_K6) 1855 .Case("k6-2", CK_K6_2) 1856 .Case("k6-3", CK_K6_3) 1857 .Case("athlon", CK_Athlon) 1858 .Case("athlon-tbird", CK_AthlonThunderbird) 1859 .Case("athlon-4", CK_Athlon4) 1860 .Case("athlon-xp", CK_AthlonXP) 1861 .Case("athlon-mp", CK_AthlonMP) 1862 .Case("athlon64", CK_Athlon64) 1863 .Case("athlon64-sse3", CK_Athlon64SSE3) 1864 .Case("athlon-fx", CK_AthlonFX) 1865 .Case("k8", CK_K8) 1866 .Case("k8-sse3", CK_K8SSE3) 1867 .Case("opteron", CK_Opteron) 1868 .Case("opteron-sse3", CK_OpteronSSE3) 1869 .Case("amdfam10", CK_AMDFAM10) 1870 .Case("btver1", CK_BTVER1) 1871 .Case("btver2", CK_BTVER2) 1872 .Case("bdver1", CK_BDVER1) 1873 .Case("bdver2", CK_BDVER2) 1874 .Case("x86-64", CK_x86_64) 1875 .Case("geode", CK_Geode) 1876 .Default(CK_Generic); 1877 1878 // Perform any per-CPU checks necessary to determine if this CPU is 1879 // acceptable. 1880 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1881 // invalid without explaining *why*. 1882 switch (CPU) { 1883 case CK_Generic: 1884 // No processor selected! 1885 return false; 1886 1887 case CK_i386: 1888 case CK_i486: 1889 case CK_WinChipC6: 1890 case CK_WinChip2: 1891 case CK_C3: 1892 case CK_i586: 1893 case CK_Pentium: 1894 case CK_PentiumMMX: 1895 case CK_i686: 1896 case CK_PentiumPro: 1897 case CK_Pentium2: 1898 case CK_Pentium3: 1899 case CK_Pentium3M: 1900 case CK_PentiumM: 1901 case CK_Yonah: 1902 case CK_C3_2: 1903 case CK_Pentium4: 1904 case CK_Pentium4M: 1905 case CK_Prescott: 1906 case CK_K6: 1907 case CK_K6_2: 1908 case CK_K6_3: 1909 case CK_Athlon: 1910 case CK_AthlonThunderbird: 1911 case CK_Athlon4: 1912 case CK_AthlonXP: 1913 case CK_AthlonMP: 1914 case CK_Geode: 1915 // Only accept certain architectures when compiling in 32-bit mode. 1916 if (getTriple().getArch() != llvm::Triple::x86) 1917 return false; 1918 1919 // Fallthrough 1920 case CK_Nocona: 1921 case CK_Core2: 1922 case CK_Penryn: 1923 case CK_Atom: 1924 case CK_Silvermont: 1925 case CK_Corei7: 1926 case CK_Corei7AVX: 1927 case CK_CoreAVXi: 1928 case CK_CoreAVX2: 1929 case CK_KNL: 1930 case CK_Athlon64: 1931 case CK_Athlon64SSE3: 1932 case CK_AthlonFX: 1933 case CK_K8: 1934 case CK_K8SSE3: 1935 case CK_Opteron: 1936 case CK_OpteronSSE3: 1937 case CK_AMDFAM10: 1938 case CK_BTVER1: 1939 case CK_BTVER2: 1940 case CK_BDVER1: 1941 case CK_BDVER2: 1942 case CK_x86_64: 1943 return true; 1944 } 1945 llvm_unreachable("Unhandled CPU kind"); 1946 } 1947 1948 virtual bool setFPMath(StringRef Name); 1949 1950 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 1951 // We accept all non-ARM calling conventions 1952 return (CC == CC_X86ThisCall || 1953 CC == CC_X86FastCall || 1954 CC == CC_X86StdCall || 1955 CC == CC_C || 1956 CC == CC_X86Pascal || 1957 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 1958 } 1959 1960 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const { 1961 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 1962 } 1963 }; 1964 1965 bool X86TargetInfo::setFPMath(StringRef Name) { 1966 if (Name == "387") { 1967 FPMath = FP_387; 1968 return true; 1969 } 1970 if (Name == "sse") { 1971 FPMath = FP_SSE; 1972 return true; 1973 } 1974 return false; 1975 } 1976 1977 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1978 // FIXME: This *really* should not be here. 1979 1980 // X86_64 always has SSE2. 1981 if (getTriple().getArch() == llvm::Triple::x86_64) 1982 setFeatureEnabledImpl(Features, "sse2", true); 1983 1984 switch (CPU) { 1985 case CK_Generic: 1986 case CK_i386: 1987 case CK_i486: 1988 case CK_i586: 1989 case CK_Pentium: 1990 case CK_i686: 1991 case CK_PentiumPro: 1992 break; 1993 case CK_PentiumMMX: 1994 case CK_Pentium2: 1995 setFeatureEnabledImpl(Features, "mmx", true); 1996 break; 1997 case CK_Pentium3: 1998 case CK_Pentium3M: 1999 setFeatureEnabledImpl(Features, "sse", true); 2000 break; 2001 case CK_PentiumM: 2002 case CK_Pentium4: 2003 case CK_Pentium4M: 2004 case CK_x86_64: 2005 setFeatureEnabledImpl(Features, "sse2", true); 2006 break; 2007 case CK_Yonah: 2008 case CK_Prescott: 2009 case CK_Nocona: 2010 setFeatureEnabledImpl(Features, "sse3", true); 2011 setFeatureEnabledImpl(Features, "cx16", true); 2012 break; 2013 case CK_Core2: 2014 setFeatureEnabledImpl(Features, "ssse3", true); 2015 setFeatureEnabledImpl(Features, "cx16", true); 2016 break; 2017 case CK_Penryn: 2018 setFeatureEnabledImpl(Features, "sse4.1", true); 2019 setFeatureEnabledImpl(Features, "cx16", true); 2020 break; 2021 case CK_Atom: 2022 setFeatureEnabledImpl(Features, "ssse3", true); 2023 setFeatureEnabledImpl(Features, "cx16", true); 2024 break; 2025 case CK_Silvermont: 2026 setFeatureEnabledImpl(Features, "sse4.2", true); 2027 setFeatureEnabledImpl(Features, "aes", true); 2028 setFeatureEnabledImpl(Features, "cx16", true); 2029 setFeatureEnabledImpl(Features, "pclmul", true); 2030 break; 2031 case CK_Corei7: 2032 setFeatureEnabledImpl(Features, "sse4.2", true); 2033 setFeatureEnabledImpl(Features, "cx16", true); 2034 break; 2035 case CK_Corei7AVX: 2036 setFeatureEnabledImpl(Features, "avx", true); 2037 setFeatureEnabledImpl(Features, "aes", true); 2038 setFeatureEnabledImpl(Features, "cx16", true); 2039 setFeatureEnabledImpl(Features, "pclmul", true); 2040 break; 2041 case CK_CoreAVXi: 2042 setFeatureEnabledImpl(Features, "avx", true); 2043 setFeatureEnabledImpl(Features, "aes", true); 2044 setFeatureEnabledImpl(Features, "pclmul", true); 2045 setFeatureEnabledImpl(Features, "rdrnd", true); 2046 setFeatureEnabledImpl(Features, "f16c", true); 2047 break; 2048 case CK_CoreAVX2: 2049 setFeatureEnabledImpl(Features, "avx2", true); 2050 setFeatureEnabledImpl(Features, "aes", true); 2051 setFeatureEnabledImpl(Features, "pclmul", true); 2052 setFeatureEnabledImpl(Features, "lzcnt", true); 2053 setFeatureEnabledImpl(Features, "rdrnd", true); 2054 setFeatureEnabledImpl(Features, "f16c", true); 2055 setFeatureEnabledImpl(Features, "bmi", true); 2056 setFeatureEnabledImpl(Features, "bmi2", true); 2057 setFeatureEnabledImpl(Features, "rtm", true); 2058 setFeatureEnabledImpl(Features, "fma", true); 2059 setFeatureEnabledImpl(Features, "cx16", true); 2060 break; 2061 case CK_KNL: 2062 setFeatureEnabledImpl(Features, "avx512f", true); 2063 setFeatureEnabledImpl(Features, "avx512cd", true); 2064 setFeatureEnabledImpl(Features, "avx512er", true); 2065 setFeatureEnabledImpl(Features, "avx512pf", true); 2066 setFeatureEnabledImpl(Features, "aes", true); 2067 setFeatureEnabledImpl(Features, "pclmul", true); 2068 setFeatureEnabledImpl(Features, "lzcnt", true); 2069 setFeatureEnabledImpl(Features, "rdrnd", true); 2070 setFeatureEnabledImpl(Features, "f16c", true); 2071 setFeatureEnabledImpl(Features, "bmi", true); 2072 setFeatureEnabledImpl(Features, "bmi2", true); 2073 setFeatureEnabledImpl(Features, "rtm", true); 2074 setFeatureEnabledImpl(Features, "fma", true); 2075 break; 2076 case CK_K6: 2077 case CK_WinChipC6: 2078 setFeatureEnabledImpl(Features, "mmx", true); 2079 break; 2080 case CK_K6_2: 2081 case CK_K6_3: 2082 case CK_WinChip2: 2083 case CK_C3: 2084 setFeatureEnabledImpl(Features, "3dnow", true); 2085 break; 2086 case CK_Athlon: 2087 case CK_AthlonThunderbird: 2088 case CK_Geode: 2089 setFeatureEnabledImpl(Features, "3dnowa", true); 2090 break; 2091 case CK_Athlon4: 2092 case CK_AthlonXP: 2093 case CK_AthlonMP: 2094 setFeatureEnabledImpl(Features, "sse", true); 2095 setFeatureEnabledImpl(Features, "3dnowa", true); 2096 break; 2097 case CK_K8: 2098 case CK_Opteron: 2099 case CK_Athlon64: 2100 case CK_AthlonFX: 2101 setFeatureEnabledImpl(Features, "sse2", true); 2102 setFeatureEnabledImpl(Features, "3dnowa", true); 2103 break; 2104 case CK_K8SSE3: 2105 case CK_OpteronSSE3: 2106 case CK_Athlon64SSE3: 2107 setFeatureEnabledImpl(Features, "sse3", true); 2108 setFeatureEnabledImpl(Features, "3dnowa", true); 2109 break; 2110 case CK_AMDFAM10: 2111 setFeatureEnabledImpl(Features, "sse3", true); 2112 setFeatureEnabledImpl(Features, "sse4a", true); 2113 setFeatureEnabledImpl(Features, "3dnowa", true); 2114 setFeatureEnabledImpl(Features, "lzcnt", true); 2115 setFeatureEnabledImpl(Features, "popcnt", true); 2116 break; 2117 case CK_BTVER1: 2118 setFeatureEnabledImpl(Features, "ssse3", true); 2119 setFeatureEnabledImpl(Features, "sse4a", true); 2120 setFeatureEnabledImpl(Features, "cx16", true); 2121 setFeatureEnabledImpl(Features, "lzcnt", true); 2122 setFeatureEnabledImpl(Features, "popcnt", true); 2123 break; 2124 case CK_BTVER2: 2125 setFeatureEnabledImpl(Features, "avx", true); 2126 setFeatureEnabledImpl(Features, "sse4a", true); 2127 setFeatureEnabledImpl(Features, "lzcnt", true); 2128 setFeatureEnabledImpl(Features, "aes", true); 2129 setFeatureEnabledImpl(Features, "pclmul", true); 2130 setFeatureEnabledImpl(Features, "bmi", true); 2131 setFeatureEnabledImpl(Features, "f16c", true); 2132 setFeatureEnabledImpl(Features, "cx16", true); 2133 break; 2134 case CK_BDVER1: 2135 setFeatureEnabledImpl(Features, "xop", true); 2136 setFeatureEnabledImpl(Features, "lzcnt", true); 2137 setFeatureEnabledImpl(Features, "aes", true); 2138 setFeatureEnabledImpl(Features, "pclmul", true); 2139 setFeatureEnabledImpl(Features, "cx16", true); 2140 break; 2141 case CK_BDVER2: 2142 setFeatureEnabledImpl(Features, "xop", true); 2143 setFeatureEnabledImpl(Features, "lzcnt", true); 2144 setFeatureEnabledImpl(Features, "aes", true); 2145 setFeatureEnabledImpl(Features, "pclmul", true); 2146 setFeatureEnabledImpl(Features, "bmi", true); 2147 setFeatureEnabledImpl(Features, "fma", true); 2148 setFeatureEnabledImpl(Features, "f16c", true); 2149 setFeatureEnabledImpl(Features, "tbm", true); 2150 setFeatureEnabledImpl(Features, "cx16", true); 2151 break; 2152 case CK_C3_2: 2153 setFeatureEnabledImpl(Features, "sse", true); 2154 break; 2155 } 2156 } 2157 2158 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2159 X86SSEEnum Level, bool Enabled) { 2160 if (Enabled) { 2161 switch (Level) { 2162 case AVX512F: 2163 Features["avx512f"] = true; 2164 case AVX2: 2165 Features["avx2"] = true; 2166 case AVX: 2167 Features["avx"] = true; 2168 case SSE42: 2169 Features["sse4.2"] = true; 2170 case SSE41: 2171 Features["sse4.1"] = true; 2172 case SSSE3: 2173 Features["ssse3"] = true; 2174 case SSE3: 2175 Features["sse3"] = true; 2176 case SSE2: 2177 Features["sse2"] = true; 2178 case SSE1: 2179 Features["sse"] = true; 2180 case NoSSE: 2181 break; 2182 } 2183 return; 2184 } 2185 2186 switch (Level) { 2187 case NoSSE: 2188 case SSE1: 2189 Features["sse"] = false; 2190 case SSE2: 2191 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2192 Features["sha"] = false; 2193 case SSE3: 2194 Features["sse3"] = false; 2195 setXOPLevel(Features, NoXOP, false); 2196 case SSSE3: 2197 Features["ssse3"] = false; 2198 case SSE41: 2199 Features["sse4.1"] = false; 2200 case SSE42: 2201 Features["sse4.2"] = false; 2202 case AVX: 2203 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2204 setXOPLevel(Features, FMA4, false); 2205 case AVX2: 2206 Features["avx2"] = false; 2207 case AVX512F: 2208 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2209 Features["avx512pf"] = false; 2210 } 2211 } 2212 2213 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2214 MMX3DNowEnum Level, bool Enabled) { 2215 if (Enabled) { 2216 switch (Level) { 2217 case AMD3DNowAthlon: 2218 Features["3dnowa"] = true; 2219 case AMD3DNow: 2220 Features["3dnow"] = true; 2221 case MMX: 2222 Features["mmx"] = true; 2223 case NoMMX3DNow: 2224 break; 2225 } 2226 return; 2227 } 2228 2229 switch (Level) { 2230 case NoMMX3DNow: 2231 case MMX: 2232 Features["mmx"] = false; 2233 case AMD3DNow: 2234 Features["3dnow"] = false; 2235 case AMD3DNowAthlon: 2236 Features["3dnowa"] = false; 2237 } 2238 } 2239 2240 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2241 bool Enabled) { 2242 if (Enabled) { 2243 switch (Level) { 2244 case XOP: 2245 Features["xop"] = true; 2246 case FMA4: 2247 Features["fma4"] = true; 2248 setSSELevel(Features, AVX, true); 2249 case SSE4A: 2250 Features["sse4a"] = true; 2251 setSSELevel(Features, SSE3, true); 2252 case NoXOP: 2253 break; 2254 } 2255 return; 2256 } 2257 2258 switch (Level) { 2259 case NoXOP: 2260 case SSE4A: 2261 Features["sse4a"] = false; 2262 case FMA4: 2263 Features["fma4"] = false; 2264 case XOP: 2265 Features["xop"] = false; 2266 } 2267 } 2268 2269 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2270 StringRef Name, bool Enabled) { 2271 // FIXME: This *really* should not be here. We need some way of translating 2272 // options into llvm subtarget features. 2273 if (Name == "sse4") 2274 Name = "sse4.2"; 2275 2276 Features[Name] = Enabled; 2277 2278 if (Name == "mmx") { 2279 setMMXLevel(Features, MMX, Enabled); 2280 } else if (Name == "sse") { 2281 setSSELevel(Features, SSE1, Enabled); 2282 } else if (Name == "sse2") { 2283 setSSELevel(Features, SSE2, Enabled); 2284 } else if (Name == "sse3") { 2285 setSSELevel(Features, SSE3, Enabled); 2286 } else if (Name == "ssse3") { 2287 setSSELevel(Features, SSSE3, Enabled); 2288 } else if (Name == "sse4.2") { 2289 setSSELevel(Features, SSE42, Enabled); 2290 } else if (Name == "sse4.1") { 2291 setSSELevel(Features, SSE41, Enabled); 2292 } else if (Name == "3dnow") { 2293 setMMXLevel(Features, AMD3DNow, Enabled); 2294 } else if (Name == "3dnowa") { 2295 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2296 } else if (Name == "aes") { 2297 if (Enabled) 2298 setSSELevel(Features, SSE2, Enabled); 2299 } else if (Name == "pclmul") { 2300 if (Enabled) 2301 setSSELevel(Features, SSE2, Enabled); 2302 } else if (Name == "avx") { 2303 setSSELevel(Features, AVX, Enabled); 2304 } else if (Name == "avx2") { 2305 setSSELevel(Features, AVX2, Enabled); 2306 } else if (Name == "avx512f") { 2307 setSSELevel(Features, AVX512F, Enabled); 2308 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf") { 2309 if (Enabled) 2310 setSSELevel(Features, AVX512F, Enabled); 2311 } else if (Name == "fma") { 2312 if (Enabled) 2313 setSSELevel(Features, AVX, Enabled); 2314 } else if (Name == "fma4") { 2315 setXOPLevel(Features, FMA4, Enabled); 2316 } else if (Name == "xop") { 2317 setXOPLevel(Features, XOP, Enabled); 2318 } else if (Name == "sse4a") { 2319 setXOPLevel(Features, SSE4A, Enabled); 2320 } else if (Name == "f16c") { 2321 if (Enabled) 2322 setSSELevel(Features, AVX, Enabled); 2323 } else if (Name == "sha") { 2324 if (Enabled) 2325 setSSELevel(Features, SSE2, Enabled); 2326 } 2327 } 2328 2329 /// HandleTargetOptions - Perform initialization based on the user 2330 /// configured set of features. 2331 bool X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features, 2332 DiagnosticsEngine &Diags) { 2333 // Remember the maximum enabled sselevel. 2334 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2335 // Ignore disabled features. 2336 if (Features[i][0] == '-') 2337 continue; 2338 2339 StringRef Feature = StringRef(Features[i]).substr(1); 2340 2341 if (Feature == "aes") { 2342 HasAES = true; 2343 continue; 2344 } 2345 2346 if (Feature == "pclmul") { 2347 HasPCLMUL = true; 2348 continue; 2349 } 2350 2351 if (Feature == "lzcnt") { 2352 HasLZCNT = true; 2353 continue; 2354 } 2355 2356 if (Feature == "rdrnd") { 2357 HasRDRND = true; 2358 continue; 2359 } 2360 2361 if (Feature == "bmi") { 2362 HasBMI = true; 2363 continue; 2364 } 2365 2366 if (Feature == "bmi2") { 2367 HasBMI2 = true; 2368 continue; 2369 } 2370 2371 if (Feature == "popcnt") { 2372 HasPOPCNT = true; 2373 continue; 2374 } 2375 2376 if (Feature == "rtm") { 2377 HasRTM = true; 2378 continue; 2379 } 2380 2381 if (Feature == "prfchw") { 2382 HasPRFCHW = true; 2383 continue; 2384 } 2385 2386 if (Feature == "rdseed") { 2387 HasRDSEED = true; 2388 continue; 2389 } 2390 2391 if (Feature == "tbm") { 2392 HasTBM = true; 2393 continue; 2394 } 2395 2396 if (Feature == "fma") { 2397 HasFMA = true; 2398 continue; 2399 } 2400 2401 if (Feature == "f16c") { 2402 HasF16C = true; 2403 continue; 2404 } 2405 2406 if (Feature == "avx512cd") { 2407 HasAVX512CD = true; 2408 continue; 2409 } 2410 2411 if (Feature == "avx512er") { 2412 HasAVX512ER = true; 2413 continue; 2414 } 2415 2416 if (Feature == "avx512pf") { 2417 HasAVX512PF = true; 2418 continue; 2419 } 2420 2421 if (Feature == "sha") { 2422 HasSHA = true; 2423 continue; 2424 } 2425 2426 if (Feature == "cx16") { 2427 HasCX16 = true; 2428 continue; 2429 } 2430 2431 assert(Features[i][0] == '+' && "Invalid target feature!"); 2432 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2433 .Case("avx512f", AVX512F) 2434 .Case("avx2", AVX2) 2435 .Case("avx", AVX) 2436 .Case("sse4.2", SSE42) 2437 .Case("sse4.1", SSE41) 2438 .Case("ssse3", SSSE3) 2439 .Case("sse3", SSE3) 2440 .Case("sse2", SSE2) 2441 .Case("sse", SSE1) 2442 .Default(NoSSE); 2443 SSELevel = std::max(SSELevel, Level); 2444 2445 MMX3DNowEnum ThreeDNowLevel = 2446 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2447 .Case("3dnowa", AMD3DNowAthlon) 2448 .Case("3dnow", AMD3DNow) 2449 .Case("mmx", MMX) 2450 .Default(NoMMX3DNow); 2451 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2452 2453 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2454 .Case("xop", XOP) 2455 .Case("fma4", FMA4) 2456 .Case("sse4a", SSE4A) 2457 .Default(NoXOP); 2458 XOPLevel = std::max(XOPLevel, XLevel); 2459 } 2460 2461 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2462 // Can't do this earlier because we need to be able to explicitly enable 2463 // popcnt and still disable sse4.2. 2464 if (!HasPOPCNT && SSELevel >= SSE42 && 2465 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2466 HasPOPCNT = true; 2467 Features.push_back("+popcnt"); 2468 } 2469 2470 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2471 // matches the selected sse level. 2472 if (FPMath == FP_SSE && SSELevel < SSE1) { 2473 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2474 return false; 2475 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2476 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2477 return false; 2478 } 2479 2480 // Don't tell the backend if we're turning off mmx; it will end up disabling 2481 // SSE, which we don't want. 2482 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2483 // then enable MMX. 2484 std::vector<std::string>::iterator it; 2485 it = std::find(Features.begin(), Features.end(), "-mmx"); 2486 if (it != Features.end()) 2487 Features.erase(it); 2488 else if (SSELevel > NoSSE) 2489 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2490 return true; 2491 } 2492 2493 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2494 /// definitions for this particular subtarget. 2495 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2496 MacroBuilder &Builder) const { 2497 // Target identification. 2498 if (getTriple().getArch() == llvm::Triple::x86_64) { 2499 Builder.defineMacro("__amd64__"); 2500 Builder.defineMacro("__amd64"); 2501 Builder.defineMacro("__x86_64"); 2502 Builder.defineMacro("__x86_64__"); 2503 } else { 2504 DefineStd(Builder, "i386", Opts); 2505 } 2506 2507 // Subtarget options. 2508 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2509 // truly should be based on -mtune options. 2510 switch (CPU) { 2511 case CK_Generic: 2512 break; 2513 case CK_i386: 2514 // The rest are coming from the i386 define above. 2515 Builder.defineMacro("__tune_i386__"); 2516 break; 2517 case CK_i486: 2518 case CK_WinChipC6: 2519 case CK_WinChip2: 2520 case CK_C3: 2521 defineCPUMacros(Builder, "i486"); 2522 break; 2523 case CK_PentiumMMX: 2524 Builder.defineMacro("__pentium_mmx__"); 2525 Builder.defineMacro("__tune_pentium_mmx__"); 2526 // Fallthrough 2527 case CK_i586: 2528 case CK_Pentium: 2529 defineCPUMacros(Builder, "i586"); 2530 defineCPUMacros(Builder, "pentium"); 2531 break; 2532 case CK_Pentium3: 2533 case CK_Pentium3M: 2534 case CK_PentiumM: 2535 Builder.defineMacro("__tune_pentium3__"); 2536 // Fallthrough 2537 case CK_Pentium2: 2538 case CK_C3_2: 2539 Builder.defineMacro("__tune_pentium2__"); 2540 // Fallthrough 2541 case CK_PentiumPro: 2542 Builder.defineMacro("__tune_i686__"); 2543 Builder.defineMacro("__tune_pentiumpro__"); 2544 // Fallthrough 2545 case CK_i686: 2546 Builder.defineMacro("__i686"); 2547 Builder.defineMacro("__i686__"); 2548 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2549 Builder.defineMacro("__pentiumpro"); 2550 Builder.defineMacro("__pentiumpro__"); 2551 break; 2552 case CK_Pentium4: 2553 case CK_Pentium4M: 2554 defineCPUMacros(Builder, "pentium4"); 2555 break; 2556 case CK_Yonah: 2557 case CK_Prescott: 2558 case CK_Nocona: 2559 defineCPUMacros(Builder, "nocona"); 2560 break; 2561 case CK_Core2: 2562 case CK_Penryn: 2563 defineCPUMacros(Builder, "core2"); 2564 break; 2565 case CK_Atom: 2566 defineCPUMacros(Builder, "atom"); 2567 break; 2568 case CK_Silvermont: 2569 defineCPUMacros(Builder, "slm"); 2570 break; 2571 case CK_Corei7: 2572 case CK_Corei7AVX: 2573 case CK_CoreAVXi: 2574 case CK_CoreAVX2: 2575 defineCPUMacros(Builder, "corei7"); 2576 break; 2577 case CK_KNL: 2578 defineCPUMacros(Builder, "knl"); 2579 break; 2580 case CK_K6_2: 2581 Builder.defineMacro("__k6_2__"); 2582 Builder.defineMacro("__tune_k6_2__"); 2583 // Fallthrough 2584 case CK_K6_3: 2585 if (CPU != CK_K6_2) { // In case of fallthrough 2586 // FIXME: GCC may be enabling these in cases where some other k6 2587 // architecture is specified but -m3dnow is explicitly provided. The 2588 // exact semantics need to be determined and emulated here. 2589 Builder.defineMacro("__k6_3__"); 2590 Builder.defineMacro("__tune_k6_3__"); 2591 } 2592 // Fallthrough 2593 case CK_K6: 2594 defineCPUMacros(Builder, "k6"); 2595 break; 2596 case CK_Athlon: 2597 case CK_AthlonThunderbird: 2598 case CK_Athlon4: 2599 case CK_AthlonXP: 2600 case CK_AthlonMP: 2601 defineCPUMacros(Builder, "athlon"); 2602 if (SSELevel != NoSSE) { 2603 Builder.defineMacro("__athlon_sse__"); 2604 Builder.defineMacro("__tune_athlon_sse__"); 2605 } 2606 break; 2607 case CK_K8: 2608 case CK_K8SSE3: 2609 case CK_x86_64: 2610 case CK_Opteron: 2611 case CK_OpteronSSE3: 2612 case CK_Athlon64: 2613 case CK_Athlon64SSE3: 2614 case CK_AthlonFX: 2615 defineCPUMacros(Builder, "k8"); 2616 break; 2617 case CK_AMDFAM10: 2618 defineCPUMacros(Builder, "amdfam10"); 2619 break; 2620 case CK_BTVER1: 2621 defineCPUMacros(Builder, "btver1"); 2622 break; 2623 case CK_BTVER2: 2624 defineCPUMacros(Builder, "btver2"); 2625 break; 2626 case CK_BDVER1: 2627 defineCPUMacros(Builder, "bdver1"); 2628 break; 2629 case CK_BDVER2: 2630 defineCPUMacros(Builder, "bdver2"); 2631 break; 2632 case CK_Geode: 2633 defineCPUMacros(Builder, "geode"); 2634 break; 2635 } 2636 2637 // Target properties. 2638 Builder.defineMacro("__LITTLE_ENDIAN__"); 2639 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2640 2641 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2642 // functions in glibc header files that use FP Stack inline asm which the 2643 // backend can't deal with (PR879). 2644 Builder.defineMacro("__NO_MATH_INLINES"); 2645 2646 if (HasAES) 2647 Builder.defineMacro("__AES__"); 2648 2649 if (HasPCLMUL) 2650 Builder.defineMacro("__PCLMUL__"); 2651 2652 if (HasLZCNT) 2653 Builder.defineMacro("__LZCNT__"); 2654 2655 if (HasRDRND) 2656 Builder.defineMacro("__RDRND__"); 2657 2658 if (HasBMI) 2659 Builder.defineMacro("__BMI__"); 2660 2661 if (HasBMI2) 2662 Builder.defineMacro("__BMI2__"); 2663 2664 if (HasPOPCNT) 2665 Builder.defineMacro("__POPCNT__"); 2666 2667 if (HasRTM) 2668 Builder.defineMacro("__RTM__"); 2669 2670 if (HasPRFCHW) 2671 Builder.defineMacro("__PRFCHW__"); 2672 2673 if (HasRDSEED) 2674 Builder.defineMacro("__RDSEED__"); 2675 2676 if (HasTBM) 2677 Builder.defineMacro("__TBM__"); 2678 2679 switch (XOPLevel) { 2680 case XOP: 2681 Builder.defineMacro("__XOP__"); 2682 case FMA4: 2683 Builder.defineMacro("__FMA4__"); 2684 case SSE4A: 2685 Builder.defineMacro("__SSE4A__"); 2686 case NoXOP: 2687 break; 2688 } 2689 2690 if (HasFMA) 2691 Builder.defineMacro("__FMA__"); 2692 2693 if (HasF16C) 2694 Builder.defineMacro("__F16C__"); 2695 2696 if (HasAVX512CD) 2697 Builder.defineMacro("__AVX512CD__"); 2698 if (HasAVX512ER) 2699 Builder.defineMacro("__AVX512ER__"); 2700 if (HasAVX512PF) 2701 Builder.defineMacro("__AVX512PF__"); 2702 2703 if (HasSHA) 2704 Builder.defineMacro("__SHA__"); 2705 2706 if (HasCX16) 2707 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 2708 2709 // Each case falls through to the previous one here. 2710 switch (SSELevel) { 2711 case AVX512F: 2712 Builder.defineMacro("__AVX512F__"); 2713 case AVX2: 2714 Builder.defineMacro("__AVX2__"); 2715 case AVX: 2716 Builder.defineMacro("__AVX__"); 2717 case SSE42: 2718 Builder.defineMacro("__SSE4_2__"); 2719 case SSE41: 2720 Builder.defineMacro("__SSE4_1__"); 2721 case SSSE3: 2722 Builder.defineMacro("__SSSE3__"); 2723 case SSE3: 2724 Builder.defineMacro("__SSE3__"); 2725 case SSE2: 2726 Builder.defineMacro("__SSE2__"); 2727 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2728 case SSE1: 2729 Builder.defineMacro("__SSE__"); 2730 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2731 case NoSSE: 2732 break; 2733 } 2734 2735 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 2736 switch (SSELevel) { 2737 case AVX512F: 2738 case AVX2: 2739 case AVX: 2740 case SSE42: 2741 case SSE41: 2742 case SSSE3: 2743 case SSE3: 2744 case SSE2: 2745 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2746 break; 2747 case SSE1: 2748 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2749 break; 2750 default: 2751 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2752 } 2753 } 2754 2755 // Each case falls through to the previous one here. 2756 switch (MMX3DNowLevel) { 2757 case AMD3DNowAthlon: 2758 Builder.defineMacro("__3dNOW_A__"); 2759 case AMD3DNow: 2760 Builder.defineMacro("__3dNOW__"); 2761 case MMX: 2762 Builder.defineMacro("__MMX__"); 2763 case NoMMX3DNow: 2764 break; 2765 } 2766 2767 if (CPU >= CK_i486) { 2768 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 2769 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 2770 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 2771 } 2772 if (CPU >= CK_i586) 2773 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 2774 } 2775 2776 bool X86TargetInfo::hasFeature(StringRef Feature) const { 2777 return llvm::StringSwitch<bool>(Feature) 2778 .Case("aes", HasAES) 2779 .Case("avx", SSELevel >= AVX) 2780 .Case("avx2", SSELevel >= AVX2) 2781 .Case("avx512f", SSELevel >= AVX512F) 2782 .Case("avx512cd", HasAVX512CD) 2783 .Case("avx512er", HasAVX512ER) 2784 .Case("avx512pf", HasAVX512PF) 2785 .Case("bmi", HasBMI) 2786 .Case("bmi2", HasBMI2) 2787 .Case("cx16", HasCX16) 2788 .Case("f16c", HasF16C) 2789 .Case("fma", HasFMA) 2790 .Case("fma4", XOPLevel >= FMA4) 2791 .Case("tbm", HasTBM) 2792 .Case("lzcnt", HasLZCNT) 2793 .Case("rdrnd", HasRDRND) 2794 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 2795 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 2796 .Case("mmx", MMX3DNowLevel >= MMX) 2797 .Case("pclmul", HasPCLMUL) 2798 .Case("popcnt", HasPOPCNT) 2799 .Case("rtm", HasRTM) 2800 .Case("prfchw", HasPRFCHW) 2801 .Case("rdseed", HasRDSEED) 2802 .Case("sha", HasSHA) 2803 .Case("sse", SSELevel >= SSE1) 2804 .Case("sse2", SSELevel >= SSE2) 2805 .Case("sse3", SSELevel >= SSE3) 2806 .Case("ssse3", SSELevel >= SSSE3) 2807 .Case("sse4.1", SSELevel >= SSE41) 2808 .Case("sse4.2", SSELevel >= SSE42) 2809 .Case("sse4a", XOPLevel >= SSE4A) 2810 .Case("x86", true) 2811 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 2812 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 2813 .Case("xop", XOPLevel >= XOP) 2814 .Default(false); 2815 } 2816 2817 bool 2818 X86TargetInfo::validateAsmConstraint(const char *&Name, 2819 TargetInfo::ConstraintInfo &Info) const { 2820 switch (*Name) { 2821 default: return false; 2822 case 'Y': // first letter of a pair: 2823 switch (*(Name+1)) { 2824 default: return false; 2825 case '0': // First SSE register. 2826 case 't': // Any SSE register, when SSE2 is enabled. 2827 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 2828 case 'm': // any MMX register, when inter-unit moves enabled. 2829 break; // falls through to setAllowsRegister. 2830 } 2831 case 'a': // eax. 2832 case 'b': // ebx. 2833 case 'c': // ecx. 2834 case 'd': // edx. 2835 case 'S': // esi. 2836 case 'D': // edi. 2837 case 'A': // edx:eax. 2838 case 'f': // any x87 floating point stack register. 2839 case 't': // top of floating point stack. 2840 case 'u': // second from top of floating point stack. 2841 case 'q': // Any register accessible as [r]l: a, b, c, and d. 2842 case 'y': // Any MMX register. 2843 case 'x': // Any SSE register. 2844 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 2845 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 2846 case 'l': // "Index" registers: any general register that can be used as an 2847 // index in a base+index memory access. 2848 Info.setAllowsRegister(); 2849 return true; 2850 case 'C': // SSE floating point constant. 2851 case 'G': // x87 floating point constant. 2852 case 'e': // 32-bit signed integer constant for use with zero-extending 2853 // x86_64 instructions. 2854 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 2855 // x86_64 instructions. 2856 return true; 2857 } 2858 } 2859 2860 2861 std::string 2862 X86TargetInfo::convertConstraint(const char *&Constraint) const { 2863 switch (*Constraint) { 2864 case 'a': return std::string("{ax}"); 2865 case 'b': return std::string("{bx}"); 2866 case 'c': return std::string("{cx}"); 2867 case 'd': return std::string("{dx}"); 2868 case 'S': return std::string("{si}"); 2869 case 'D': return std::string("{di}"); 2870 case 'p': // address 2871 return std::string("im"); 2872 case 't': // top of floating point stack. 2873 return std::string("{st}"); 2874 case 'u': // second from top of floating point stack. 2875 return std::string("{st(1)}"); // second from top of floating point stack. 2876 default: 2877 return std::string(1, *Constraint); 2878 } 2879 } 2880 } // end anonymous namespace 2881 2882 namespace { 2883 // X86-32 generic target 2884 class X86_32TargetInfo : public X86TargetInfo { 2885 public: 2886 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 2887 DoubleAlign = LongLongAlign = 32; 2888 LongDoubleWidth = 96; 2889 LongDoubleAlign = 32; 2890 SuitableAlign = 128; 2891 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2892 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-" 2893 "a0:0:64-f80:32:32-n8:16:32-S128"; 2894 SizeType = UnsignedInt; 2895 PtrDiffType = SignedInt; 2896 IntPtrType = SignedInt; 2897 RegParmMax = 3; 2898 2899 // Use fpret for all types. 2900 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 2901 (1 << TargetInfo::Double) | 2902 (1 << TargetInfo::LongDouble)); 2903 2904 // x86-32 has atomics up to 8 bytes 2905 // FIXME: Check that we actually have cmpxchg8b before setting 2906 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 2907 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 2908 } 2909 virtual BuiltinVaListKind getBuiltinVaListKind() const { 2910 return TargetInfo::CharPtrBuiltinVaList; 2911 } 2912 2913 int getEHDataRegisterNumber(unsigned RegNo) const { 2914 if (RegNo == 0) return 0; 2915 if (RegNo == 1) return 2; 2916 return -1; 2917 } 2918 virtual bool validateInputSize(StringRef Constraint, 2919 unsigned Size) const { 2920 switch (Constraint[0]) { 2921 default: break; 2922 case 'a': 2923 case 'b': 2924 case 'c': 2925 case 'd': 2926 return Size <= 32; 2927 } 2928 2929 return true; 2930 } 2931 }; 2932 } // end anonymous namespace 2933 2934 namespace { 2935 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 2936 public: 2937 NetBSDI386TargetInfo(const llvm::Triple &Triple) 2938 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 2939 2940 virtual unsigned getFloatEvalMethod() const { 2941 // NetBSD defaults to "double" rounding 2942 return 1; 2943 } 2944 }; 2945 } // end anonymous namespace 2946 2947 namespace { 2948 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 2949 public: 2950 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 2951 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 2952 SizeType = UnsignedLong; 2953 IntPtrType = SignedLong; 2954 PtrDiffType = SignedLong; 2955 } 2956 }; 2957 } // end anonymous namespace 2958 2959 namespace { 2960 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 2961 public: 2962 BitrigI386TargetInfo(const llvm::Triple &Triple) 2963 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 2964 SizeType = UnsignedLong; 2965 IntPtrType = SignedLong; 2966 PtrDiffType = SignedLong; 2967 } 2968 }; 2969 } // end anonymous namespace 2970 2971 namespace { 2972 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 2973 public: 2974 DarwinI386TargetInfo(const llvm::Triple &Triple) 2975 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 2976 LongDoubleWidth = 128; 2977 LongDoubleAlign = 128; 2978 SuitableAlign = 128; 2979 MaxVectorAlign = 256; 2980 SizeType = UnsignedLong; 2981 IntPtrType = SignedLong; 2982 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2983 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-" 2984 "a0:0:64-f80:128:128-n8:16:32-S128"; 2985 HasAlignMac68kSupport = true; 2986 } 2987 2988 }; 2989 } // end anonymous namespace 2990 2991 namespace { 2992 // x86-32 Windows target 2993 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 2994 public: 2995 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 2996 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 2997 TLSSupported = false; 2998 WCharType = UnsignedShort; 2999 DoubleAlign = LongLongAlign = 64; 3000 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3001 "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-" 3002 "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32"; 3003 } 3004 virtual void getTargetDefines(const LangOptions &Opts, 3005 MacroBuilder &Builder) const { 3006 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3007 } 3008 }; 3009 } // end anonymous namespace 3010 3011 namespace { 3012 3013 // x86-32 Windows Visual Studio target 3014 class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo { 3015 public: 3016 VisualStudioWindowsX86_32TargetInfo(const llvm::Triple &Triple) 3017 : WindowsX86_32TargetInfo(Triple) { 3018 LongDoubleWidth = LongDoubleAlign = 64; 3019 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3020 } 3021 virtual void getTargetDefines(const LangOptions &Opts, 3022 MacroBuilder &Builder) const { 3023 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3024 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3025 // The value of the following reflects processor type. 3026 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3027 // We lost the original triple, so we use the default. 3028 Builder.defineMacro("_M_IX86", "600"); 3029 } 3030 }; 3031 } // end anonymous namespace 3032 3033 namespace { 3034 // x86-32 MinGW target 3035 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3036 public: 3037 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3038 : WindowsX86_32TargetInfo(Triple) {} 3039 virtual void getTargetDefines(const LangOptions &Opts, 3040 MacroBuilder &Builder) const { 3041 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3042 DefineStd(Builder, "WIN32", Opts); 3043 DefineStd(Builder, "WINNT", Opts); 3044 Builder.defineMacro("_X86_"); 3045 Builder.defineMacro("__MSVCRT__"); 3046 Builder.defineMacro("__MINGW32__"); 3047 3048 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 3049 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 3050 if (Opts.MicrosoftExt) 3051 // Provide "as-is" __declspec. 3052 Builder.defineMacro("__declspec", "__declspec"); 3053 else 3054 // Provide alias of __attribute__ like mingw32-gcc. 3055 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3056 } 3057 }; 3058 } // end anonymous namespace 3059 3060 namespace { 3061 // x86-32 Cygwin target 3062 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3063 public: 3064 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3065 : X86_32TargetInfo(Triple) { 3066 TLSSupported = false; 3067 WCharType = UnsignedShort; 3068 DoubleAlign = LongLongAlign = 64; 3069 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3070 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-" 3071 "a0:0:64-f80:32:32-n8:16:32-S32"; 3072 } 3073 virtual void getTargetDefines(const LangOptions &Opts, 3074 MacroBuilder &Builder) const { 3075 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3076 Builder.defineMacro("_X86_"); 3077 Builder.defineMacro("__CYGWIN__"); 3078 Builder.defineMacro("__CYGWIN32__"); 3079 DefineStd(Builder, "unix", Opts); 3080 if (Opts.CPlusPlus) 3081 Builder.defineMacro("_GNU_SOURCE"); 3082 } 3083 }; 3084 } // end anonymous namespace 3085 3086 namespace { 3087 // x86-32 Haiku target 3088 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3089 public: 3090 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3091 SizeType = UnsignedLong; 3092 IntPtrType = SignedLong; 3093 PtrDiffType = SignedLong; 3094 ProcessIDType = SignedLong; 3095 this->UserLabelPrefix = ""; 3096 this->TLSSupported = false; 3097 } 3098 virtual void getTargetDefines(const LangOptions &Opts, 3099 MacroBuilder &Builder) const { 3100 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3101 Builder.defineMacro("__INTEL__"); 3102 Builder.defineMacro("__HAIKU__"); 3103 } 3104 }; 3105 } // end anonymous namespace 3106 3107 // RTEMS Target 3108 template<typename Target> 3109 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3110 protected: 3111 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3112 MacroBuilder &Builder) const { 3113 // RTEMS defines; list based off of gcc output 3114 3115 Builder.defineMacro("__rtems__"); 3116 Builder.defineMacro("__ELF__"); 3117 } 3118 3119 public: 3120 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3121 this->UserLabelPrefix = ""; 3122 3123 switch (Triple.getArch()) { 3124 default: 3125 case llvm::Triple::x86: 3126 // this->MCountName = ".mcount"; 3127 break; 3128 case llvm::Triple::mips: 3129 case llvm::Triple::mipsel: 3130 case llvm::Triple::ppc: 3131 case llvm::Triple::ppc64: 3132 case llvm::Triple::ppc64le: 3133 // this->MCountName = "_mcount"; 3134 break; 3135 case llvm::Triple::arm: 3136 // this->MCountName = "__mcount"; 3137 break; 3138 } 3139 } 3140 }; 3141 3142 namespace { 3143 // x86-32 RTEMS target 3144 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3145 public: 3146 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3147 SizeType = UnsignedLong; 3148 IntPtrType = SignedLong; 3149 PtrDiffType = SignedLong; 3150 this->UserLabelPrefix = ""; 3151 } 3152 virtual void getTargetDefines(const LangOptions &Opts, 3153 MacroBuilder &Builder) const { 3154 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3155 Builder.defineMacro("__INTEL__"); 3156 Builder.defineMacro("__rtems__"); 3157 } 3158 }; 3159 } // end anonymous namespace 3160 3161 namespace { 3162 // x86-64 generic target 3163 class X86_64TargetInfo : public X86TargetInfo { 3164 public: 3165 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3166 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 3167 LongDoubleWidth = 128; 3168 LongDoubleAlign = 128; 3169 LargeArrayMinWidth = 128; 3170 LargeArrayAlign = 128; 3171 SuitableAlign = 128; 3172 IntMaxType = SignedLong; 3173 UIntMaxType = UnsignedLong; 3174 Int64Type = SignedLong; 3175 RegParmMax = 6; 3176 3177 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3178 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-" 3179 "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"; 3180 3181 // Use fpret only for long double. 3182 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3183 3184 // Use fp2ret for _Complex long double. 3185 ComplexLongDoubleUsesFP2Ret = true; 3186 3187 // x86-64 has atomics up to 16 bytes. 3188 // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128 3189 // on CPUs with cmpxchg16b 3190 MaxAtomicPromoteWidth = 128; 3191 MaxAtomicInlineWidth = 64; 3192 } 3193 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3194 return TargetInfo::X86_64ABIBuiltinVaList; 3195 } 3196 3197 int getEHDataRegisterNumber(unsigned RegNo) const { 3198 if (RegNo == 0) return 0; 3199 if (RegNo == 1) return 1; 3200 return -1; 3201 } 3202 3203 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3204 return (CC == CC_C || 3205 CC == CC_IntelOclBicc || 3206 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3207 } 3208 3209 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const { 3210 return CC_C; 3211 } 3212 3213 }; 3214 } // end anonymous namespace 3215 3216 namespace { 3217 // x86-64 Windows target 3218 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3219 public: 3220 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3221 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3222 TLSSupported = false; 3223 WCharType = UnsignedShort; 3224 LongWidth = LongAlign = 32; 3225 DoubleAlign = LongLongAlign = 64; 3226 IntMaxType = SignedLongLong; 3227 UIntMaxType = UnsignedLongLong; 3228 Int64Type = SignedLongLong; 3229 SizeType = UnsignedLongLong; 3230 PtrDiffType = SignedLongLong; 3231 IntPtrType = SignedLongLong; 3232 this->UserLabelPrefix = ""; 3233 } 3234 virtual void getTargetDefines(const LangOptions &Opts, 3235 MacroBuilder &Builder) const { 3236 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3237 Builder.defineMacro("_WIN64"); 3238 } 3239 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3240 return TargetInfo::CharPtrBuiltinVaList; 3241 } 3242 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3243 return (CC == CC_C || 3244 CC == CC_IntelOclBicc || 3245 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning; 3246 } 3247 }; 3248 } // end anonymous namespace 3249 3250 namespace { 3251 // x86-64 Windows Visual Studio target 3252 class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo { 3253 public: 3254 VisualStudioWindowsX86_64TargetInfo(const llvm::Triple &Triple) 3255 : WindowsX86_64TargetInfo(Triple) { 3256 LongDoubleWidth = LongDoubleAlign = 64; 3257 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3258 } 3259 virtual void getTargetDefines(const LangOptions &Opts, 3260 MacroBuilder &Builder) const { 3261 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3262 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3263 Builder.defineMacro("_M_X64"); 3264 Builder.defineMacro("_M_AMD64"); 3265 } 3266 }; 3267 } // end anonymous namespace 3268 3269 namespace { 3270 // x86-64 MinGW target 3271 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3272 public: 3273 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3274 : WindowsX86_64TargetInfo(Triple) {} 3275 virtual void getTargetDefines(const LangOptions &Opts, 3276 MacroBuilder &Builder) const { 3277 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3278 DefineStd(Builder, "WIN64", Opts); 3279 Builder.defineMacro("__MSVCRT__"); 3280 Builder.defineMacro("__MINGW32__"); 3281 Builder.defineMacro("__MINGW64__"); 3282 3283 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 3284 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 3285 if (Opts.MicrosoftExt) 3286 // Provide "as-is" __declspec. 3287 Builder.defineMacro("__declspec", "__declspec"); 3288 else 3289 // Provide alias of __attribute__ like mingw32-gcc. 3290 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3291 } 3292 }; 3293 } // end anonymous namespace 3294 3295 namespace { 3296 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3297 public: 3298 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3299 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3300 Int64Type = SignedLongLong; 3301 MaxVectorAlign = 256; 3302 } 3303 }; 3304 } // end anonymous namespace 3305 3306 namespace { 3307 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3308 public: 3309 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3310 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3311 IntMaxType = SignedLongLong; 3312 UIntMaxType = UnsignedLongLong; 3313 Int64Type = SignedLongLong; 3314 } 3315 }; 3316 } // end anonymous namespace 3317 3318 namespace { 3319 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3320 public: 3321 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3322 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3323 IntMaxType = SignedLongLong; 3324 UIntMaxType = UnsignedLongLong; 3325 Int64Type = SignedLongLong; 3326 } 3327 }; 3328 } 3329 3330 namespace { 3331 class AArch64TargetInfo : public TargetInfo { 3332 static const char * const GCCRegNames[]; 3333 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3334 3335 enum FPUModeEnum { 3336 FPUMode, 3337 NeonMode 3338 }; 3339 3340 unsigned FPU; 3341 static const Builtin::Info BuiltinInfo[]; 3342 3343 public: 3344 AArch64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 3345 BigEndian = false; 3346 LongWidth = LongAlign = 64; 3347 LongDoubleWidth = LongDoubleAlign = 128; 3348 PointerWidth = PointerAlign = 64; 3349 SuitableAlign = 128; 3350 DescriptionString = "e-p:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3351 "i64:64:64-i128:128:128-f32:32:32-f64:64:64-" 3352 "f128:128:128-n32:64-S128"; 3353 3354 WCharType = UnsignedInt; 3355 LongDoubleFormat = &llvm::APFloat::IEEEquad; 3356 3357 // AArch64 backend supports 64-bit operations at the moment. In principle 3358 // 128-bit is possible if register-pairs are used. 3359 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3360 3361 TheCXXABI.set(TargetCXXABI::GenericAArch64); 3362 } 3363 virtual void getTargetDefines(const LangOptions &Opts, 3364 MacroBuilder &Builder) const { 3365 // GCC defines theses currently 3366 Builder.defineMacro("__aarch64__"); 3367 Builder.defineMacro("__AARCH64EL__"); 3368 3369 // ACLE predefines. Many can only have one possible value on v8 AArch64. 3370 3371 // FIXME: these were written based on an unreleased version of a 32-bit ACLE 3372 // which was intended to be compatible with a 64-bit implementation. They 3373 // will need updating when a real 64-bit ACLE exists. Particularly pressing 3374 // instances are: __ARM_ARCH_ISA_ARM, __ARM_ARCH_ISA_THUMB, __ARM_PCS. 3375 Builder.defineMacro("__ARM_ACLE", "101"); 3376 Builder.defineMacro("__ARM_ARCH", "8"); 3377 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 3378 3379 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 3380 Builder.defineMacro("__ARM_FEATURE_CLZ"); 3381 Builder.defineMacro("__ARM_FEATURE_FMA"); 3382 3383 // FIXME: ACLE 1.1 reserves bit 4. Will almost certainly come to mean 3384 // 128-bit LDXP present, at which point this becomes 0x1f. 3385 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xf"); 3386 3387 // 0xe implies support for half, single and double precision operations. 3388 Builder.defineMacro("__ARM_FP", "0xe"); 3389 3390 // PCS specifies this for SysV variants, which is all we support. Other ABIs 3391 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 3392 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 3393 3394 if (Opts.FastMath || Opts.FiniteMathOnly) 3395 Builder.defineMacro("__ARM_FP_FAST"); 3396 3397 if ((Opts.C99 || Opts.C11) && !Opts.Freestanding) 3398 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 3399 3400 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 3401 Opts.ShortWChar ? "2" : "4"); 3402 3403 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 3404 Opts.ShortEnums ? "1" : "4"); 3405 3406 if (BigEndian) 3407 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 3408 3409 if (FPU == NeonMode) { 3410 Builder.defineMacro("__AARCH_FEATURE_ADVSIMD"); 3411 3412 // 64-bit NEON supports half, single and double precision operations. 3413 Builder.defineMacro("__AARCH_ADVSIMD_FP", "0xe"); 3414 } 3415 } 3416 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3417 unsigned &NumRecords) const { 3418 Records = BuiltinInfo; 3419 NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin; 3420 } 3421 virtual bool hasFeature(StringRef Feature) const { 3422 return Feature == "aarch64" || (Feature == "neon" && FPU == NeonMode); 3423 } 3424 3425 virtual bool HandleTargetFeatures(std::vector<std::string> &Features, 3426 DiagnosticsEngine &Diags) { 3427 FPU = FPUMode; 3428 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3429 if (Features[i] == "+neon") 3430 FPU = NeonMode; 3431 } 3432 return true; 3433 } 3434 3435 virtual void getGCCRegNames(const char *const *&Names, 3436 unsigned &NumNames) const; 3437 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3438 unsigned &NumAliases) const; 3439 3440 virtual bool isCLZForZeroUndef() const { return false; } 3441 3442 virtual bool validateAsmConstraint(const char *&Name, 3443 TargetInfo::ConstraintInfo &Info) const { 3444 switch (*Name) { 3445 default: return false; 3446 case 'w': // An FP/SIMD vector register 3447 Info.setAllowsRegister(); 3448 return true; 3449 case 'I': // Constant that can be used with an ADD instruction 3450 case 'J': // Constant that can be used with a SUB instruction 3451 case 'K': // Constant that can be used with a 32-bit logical instruction 3452 case 'L': // Constant that can be used with a 64-bit logical instruction 3453 case 'M': // Constant that can be used as a 32-bit MOV immediate 3454 case 'N': // Constant that can be used as a 64-bit MOV immediate 3455 case 'Y': // Floating point constant zero 3456 case 'Z': // Integer constant zero 3457 return true; 3458 case 'Q': // A memory reference with base register and no offset 3459 Info.setAllowsMemory(); 3460 return true; 3461 case 'S': // A symbolic address 3462 Info.setAllowsRegister(); 3463 return true; 3464 case 'U': 3465 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be 3466 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be 3467 // Usa: An absolute symbolic address 3468 // Ush: The high part (bits 32:12) of a pc-relative symbolic address 3469 llvm_unreachable("FIXME: Unimplemented support for bizarre constraints"); 3470 } 3471 } 3472 3473 virtual const char *getClobbers() const { 3474 // There are no AArch64 clobbers shared by all asm statements. 3475 return ""; 3476 } 3477 3478 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3479 return TargetInfo::AArch64ABIBuiltinVaList; 3480 } 3481 }; 3482 3483 const char * const AArch64TargetInfo::GCCRegNames[] = { 3484 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", 3485 "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15", 3486 "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23", 3487 "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr", 3488 3489 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", 3490 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", 3491 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", 3492 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr", 3493 3494 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", 3495 "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15", 3496 "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23", 3497 "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31", 3498 3499 "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7", 3500 "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15", 3501 "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23", 3502 "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31", 3503 3504 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 3505 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 3506 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 3507 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 3508 3509 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 3510 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 3511 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 3512 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 3513 3514 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 3515 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", 3516 "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23", 3517 "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31" 3518 }; 3519 3520 void AArch64TargetInfo::getGCCRegNames(const char * const *&Names, 3521 unsigned &NumNames) const { 3522 Names = GCCRegNames; 3523 NumNames = llvm::array_lengthof(GCCRegNames); 3524 } 3525 3526 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 3527 { { "x16" }, "ip0"}, 3528 { { "x17" }, "ip1"}, 3529 { { "x29" }, "fp" }, 3530 { { "x30" }, "lr" } 3531 }; 3532 3533 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3534 unsigned &NumAliases) const { 3535 Aliases = GCCRegAliases; 3536 NumAliases = llvm::array_lengthof(GCCRegAliases); 3537 3538 } 3539 3540 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 3541 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3542 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3543 ALL_LANGUAGES }, 3544 #include "clang/Basic/BuiltinsAArch64.def" 3545 }; 3546 3547 } // end anonymous namespace 3548 3549 namespace { 3550 class ARMTargetInfo : public TargetInfo { 3551 // Possible FPU choices. 3552 enum FPUMode { 3553 VFP2FPU = (1 << 0), 3554 VFP3FPU = (1 << 1), 3555 VFP4FPU = (1 << 2), 3556 NeonFPU = (1 << 3) 3557 }; 3558 3559 static bool FPUModeIsVFP(FPUMode Mode) { 3560 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU); 3561 } 3562 3563 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3564 static const char * const GCCRegNames[]; 3565 3566 std::string ABI, CPU; 3567 3568 enum { 3569 FP_Default, 3570 FP_VFP, 3571 FP_Neon 3572 } FPMath; 3573 3574 unsigned FPU : 4; 3575 3576 unsigned IsAAPCS : 1; 3577 unsigned IsThumb : 1; 3578 3579 // Initialized via features. 3580 unsigned SoftFloat : 1; 3581 unsigned SoftFloatABI : 1; 3582 3583 static const Builtin::Info BuiltinInfo[]; 3584 3585 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3586 // On linux, binaries targeting old cpus call functions in libgcc to 3587 // perform atomic operations. The implementation in libgcc then calls into 3588 // the kernel which on armv6 and newer uses ldrex and strex. The net result 3589 // is that if we assume the kernel is at least as recent as the hardware, 3590 // it is safe to use atomic instructions on armv6 and newer. 3591 if (!T.isOSLinux() && 3592 T.getOS() != llvm::Triple::FreeBSD && 3593 T.getOS() != llvm::Triple::Bitrig) 3594 return false; 3595 StringRef ArchName = T.getArchName(); 3596 if (T.getArch() == llvm::Triple::arm) { 3597 if (!ArchName.startswith("armv")) 3598 return false; 3599 StringRef VersionStr = ArchName.substr(4); 3600 unsigned Version; 3601 if (VersionStr.getAsInteger(10, Version)) 3602 return false; 3603 return Version >= 6; 3604 } 3605 assert(T.getArch() == llvm::Triple::thumb); 3606 if (!ArchName.startswith("thumbv")) 3607 return false; 3608 StringRef VersionStr = ArchName.substr(6); 3609 unsigned Version; 3610 if (VersionStr.getAsInteger(10, Version)) 3611 return false; 3612 return Version >= 7; 3613 } 3614 3615 public: 3616 ARMTargetInfo(const llvm::Triple &Triple) 3617 : TargetInfo(Triple), ABI("aapcs-linux"), CPU("arm1136j-s"), 3618 FPMath(FP_Default), IsAAPCS(true) { 3619 BigEndian = false; 3620 SizeType = UnsignedInt; 3621 PtrDiffType = SignedInt; 3622 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3623 WCharType = UnsignedInt; 3624 3625 // {} in inline assembly are neon specifiers, not assembly variant 3626 // specifiers. 3627 NoAsmVariants = true; 3628 3629 // FIXME: Should we just treat this as a feature? 3630 IsThumb = getTriple().getArchName().startswith("thumb"); 3631 if (IsThumb) { 3632 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3633 // so set preferred for small types to 32. 3634 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" 3635 "i64:64:64-f32:32:32-f64:64:64-" 3636 "v64:64:64-v128:64:128-a0:0:32-n32-S64"); 3637 } else { 3638 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3639 "i64:64:64-f32:32:32-f64:64:64-" 3640 "v64:64:64-v128:64:128-a0:0:64-n32-S64"); 3641 } 3642 3643 // ARM targets default to using the ARM C++ ABI. 3644 TheCXXABI.set(TargetCXXABI::GenericARM); 3645 3646 // ARM has atomics up to 8 bytes 3647 MaxAtomicPromoteWidth = 64; 3648 if (shouldUseInlineAtomic(getTriple())) 3649 MaxAtomicInlineWidth = 64; 3650 3651 // Do force alignment of members that follow zero length bitfields. If 3652 // the alignment of the zero-length bitfield is greater than the member 3653 // that follows it, `bar', `bar' will be aligned as the type of the 3654 // zero length bitfield. 3655 UseZeroLengthBitfieldAlignment = true; 3656 } 3657 virtual const char *getABI() const { return ABI.c_str(); } 3658 virtual bool setABI(const std::string &Name) { 3659 ABI = Name; 3660 3661 // The defaults (above) are for AAPCS, check if we need to change them. 3662 // 3663 // FIXME: We need support for -meabi... we could just mangle it into the 3664 // name. 3665 if (Name == "apcs-gnu") { 3666 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 3667 // size_t is unsigned int on FreeBSD. 3668 if (getTriple().getOS() != llvm::Triple::FreeBSD) 3669 SizeType = UnsignedLong; 3670 3671 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 3672 WCharType = SignedInt; 3673 3674 // Do not respect the alignment of bit-field types when laying out 3675 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 3676 UseBitFieldTypeAlignment = false; 3677 3678 /// gcc forces the alignment to 4 bytes, regardless of the type of the 3679 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 3680 /// gcc. 3681 ZeroLengthBitfieldBoundary = 32; 3682 3683 IsAAPCS = false; 3684 3685 if (IsThumb) { 3686 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3687 // so set preferred for small types to 32. 3688 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" 3689 "i64:32:64-f32:32:32-f64:32:64-" 3690 "v64:32:64-v128:32:128-a0:0:32-n32-S32"); 3691 } else { 3692 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3693 "i64:32:64-f32:32:32-f64:32:64-" 3694 "v64:32:64-v128:32:128-a0:0:32-n32-S32"); 3695 } 3696 3697 // FIXME: Override "preferred align" for double and long long. 3698 } else if (Name == "aapcs" || Name == "aapcs-vfp") { 3699 // size_t is unsigned long on Darwin. 3700 if (getTriple().isOSDarwin()) 3701 SizeType = UnsignedLong; 3702 IsAAPCS = true; 3703 // FIXME: Enumerated types are variable width in straight AAPCS. 3704 } else if (Name == "aapcs-linux") { 3705 IsAAPCS = true; 3706 } else 3707 return false; 3708 3709 return true; 3710 } 3711 3712 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 3713 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 3714 Features["vfp2"] = true; 3715 else if (CPU == "cortex-a8" || CPU == "cortex-a9" || 3716 CPU == "cortex-a9-mp") { 3717 Features["vfp3"] = true; 3718 Features["neon"] = true; 3719 } else if (CPU == "swift" || CPU == "cortex-a5" || 3720 CPU == "cortex-a7" || CPU == "cortex-a15") { 3721 Features["vfp4"] = true; 3722 Features["neon"] = true; 3723 } 3724 } 3725 3726 virtual bool HandleTargetFeatures(std::vector<std::string> &Features, 3727 DiagnosticsEngine &Diags) { 3728 FPU = 0; 3729 SoftFloat = SoftFloatABI = false; 3730 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3731 if (Features[i] == "+soft-float") 3732 SoftFloat = true; 3733 else if (Features[i] == "+soft-float-abi") 3734 SoftFloatABI = true; 3735 else if (Features[i] == "+vfp2") 3736 FPU |= VFP2FPU; 3737 else if (Features[i] == "+vfp3") 3738 FPU |= VFP3FPU; 3739 else if (Features[i] == "+vfp4") 3740 FPU |= VFP4FPU; 3741 else if (Features[i] == "+neon") 3742 FPU |= NeonFPU; 3743 } 3744 3745 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 3746 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 3747 return false; 3748 } 3749 3750 if (FPMath == FP_Neon) 3751 Features.push_back("+neonfp"); 3752 else if (FPMath == FP_VFP) 3753 Features.push_back("-neonfp"); 3754 3755 // Remove front-end specific options which the backend handles differently. 3756 std::vector<std::string>::iterator it; 3757 it = std::find(Features.begin(), Features.end(), "+soft-float"); 3758 if (it != Features.end()) 3759 Features.erase(it); 3760 it = std::find(Features.begin(), Features.end(), "+soft-float-abi"); 3761 if (it != Features.end()) 3762 Features.erase(it); 3763 return true; 3764 } 3765 3766 virtual bool hasFeature(StringRef Feature) const { 3767 return llvm::StringSwitch<bool>(Feature) 3768 .Case("arm", true) 3769 .Case("softfloat", SoftFloat) 3770 .Case("thumb", IsThumb) 3771 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 3772 .Default(false); 3773 } 3774 // FIXME: Should we actually have some table instead of these switches? 3775 static const char *getCPUDefineSuffix(StringRef Name) { 3776 return llvm::StringSwitch<const char*>(Name) 3777 .Cases("arm8", "arm810", "4") 3778 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") 3779 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 3780 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 3781 .Case("ep9312", "4T") 3782 .Cases("arm10tdmi", "arm1020t", "5T") 3783 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 3784 .Case("arm926ej-s", "5TEJ") 3785 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 3786 .Cases("xscale", "iwmmxt", "5TE") 3787 .Case("arm1136j-s", "6J") 3788 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 3789 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 3790 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 3791 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A") 3792 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "7A") 3793 .Cases("cortex-r4", "cortex-r5", "7R") 3794 .Case("cortex-a9-mp", "7F") 3795 .Case("swift", "7S") 3796 .Cases("cortex-m3", "cortex-m4", "7M") 3797 .Case("cortex-m0", "6M") 3798 .Case("cortex-a53", "8A") 3799 .Default(0); 3800 } 3801 static const char *getCPUProfile(StringRef Name) { 3802 return llvm::StringSwitch<const char*>(Name) 3803 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A") 3804 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "A") 3805 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M") 3806 .Cases("cortex-r4", "cortex-r5", "R") 3807 .Default(""); 3808 } 3809 virtual bool setCPU(const std::string &Name) { 3810 if (!getCPUDefineSuffix(Name)) 3811 return false; 3812 3813 CPU = Name; 3814 return true; 3815 } 3816 virtual bool setFPMath(StringRef Name); 3817 virtual void getTargetDefines(const LangOptions &Opts, 3818 MacroBuilder &Builder) const { 3819 // Target identification. 3820 Builder.defineMacro("__arm"); 3821 Builder.defineMacro("__arm__"); 3822 3823 // Target properties. 3824 Builder.defineMacro("__ARMEL__"); 3825 Builder.defineMacro("__LITTLE_ENDIAN__"); 3826 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3827 3828 StringRef CPUArch = getCPUDefineSuffix(CPU); 3829 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 3830 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 3831 StringRef CPUProfile = getCPUProfile(CPU); 3832 if (!CPUProfile.empty()) 3833 Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile); 3834 3835 // Subtarget options. 3836 3837 // FIXME: It's more complicated than this and we don't really support 3838 // interworking. 3839 if ('5' <= CPUArch[0] && CPUArch[0] <= '7') 3840 Builder.defineMacro("__THUMB_INTERWORK__"); 3841 3842 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 3843 // M-class CPUs on Darwin follow AAPCS, but not EABI. 3844 if (!(getTriple().isOSDarwin() && CPUProfile == "M")) 3845 Builder.defineMacro("__ARM_EABI__"); 3846 Builder.defineMacro("__ARM_PCS", "1"); 3847 3848 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 3849 Builder.defineMacro("__ARM_PCS_VFP", "1"); 3850 } 3851 3852 if (SoftFloat) 3853 Builder.defineMacro("__SOFTFP__"); 3854 3855 if (CPU == "xscale") 3856 Builder.defineMacro("__XSCALE__"); 3857 3858 bool IsARMv7 = CPUArch.startswith("7"); 3859 if (IsThumb) { 3860 Builder.defineMacro("__THUMBEL__"); 3861 Builder.defineMacro("__thumb__"); 3862 if (CPUArch == "6T2" || IsARMv7) 3863 Builder.defineMacro("__thumb2__"); 3864 } 3865 3866 // Note, this is always on in gcc, even though it doesn't make sense. 3867 Builder.defineMacro("__APCS_32__"); 3868 3869 if (FPUModeIsVFP((FPUMode) FPU)) { 3870 Builder.defineMacro("__VFP_FP__"); 3871 if (FPU & VFP2FPU) 3872 Builder.defineMacro("__ARM_VFPV2__"); 3873 if (FPU & VFP3FPU) 3874 Builder.defineMacro("__ARM_VFPV3__"); 3875 if (FPU & VFP4FPU) 3876 Builder.defineMacro("__ARM_VFPV4__"); 3877 } 3878 3879 // This only gets set when Neon instructions are actually available, unlike 3880 // the VFP define, hence the soft float and arch check. This is subtly 3881 // different from gcc, we follow the intent which was that it should be set 3882 // when Neon instructions are actually available. 3883 if ((FPU & NeonFPU) && !SoftFloat && IsARMv7) 3884 Builder.defineMacro("__ARM_NEON__"); 3885 3886 if (CPUArch.startswith("8")) 3887 Builder.defineMacro("__ARM_FEATURE_CRC32"); 3888 3889 if (CPUArch[0] >= '6' && CPUArch != "6M") { 3890 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3891 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3892 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3893 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3894 } 3895 } 3896 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3897 unsigned &NumRecords) const { 3898 Records = BuiltinInfo; 3899 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 3900 } 3901 virtual bool isCLZForZeroUndef() const { return false; } 3902 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3903 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 3904 } 3905 virtual void getGCCRegNames(const char * const *&Names, 3906 unsigned &NumNames) const; 3907 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3908 unsigned &NumAliases) const; 3909 virtual bool validateAsmConstraint(const char *&Name, 3910 TargetInfo::ConstraintInfo &Info) const { 3911 switch (*Name) { 3912 default: break; 3913 case 'l': // r0-r7 3914 case 'h': // r8-r15 3915 case 'w': // VFP Floating point register single precision 3916 case 'P': // VFP Floating point register double precision 3917 Info.setAllowsRegister(); 3918 return true; 3919 case 'Q': // A memory address that is a single base register. 3920 Info.setAllowsMemory(); 3921 return true; 3922 case 'U': // a memory reference... 3923 switch (Name[1]) { 3924 case 'q': // ...ARMV4 ldrsb 3925 case 'v': // ...VFP load/store (reg+constant offset) 3926 case 'y': // ...iWMMXt load/store 3927 case 't': // address valid for load/store opaque types wider 3928 // than 128-bits 3929 case 'n': // valid address for Neon doubleword vector load/store 3930 case 'm': // valid address for Neon element and structure load/store 3931 case 's': // valid address for non-offset loads/stores of quad-word 3932 // values in four ARM registers 3933 Info.setAllowsMemory(); 3934 Name++; 3935 return true; 3936 } 3937 } 3938 return false; 3939 } 3940 virtual std::string convertConstraint(const char *&Constraint) const { 3941 std::string R; 3942 switch (*Constraint) { 3943 case 'U': // Two-character constraint; add "^" hint for later parsing. 3944 R = std::string("^") + std::string(Constraint, 2); 3945 Constraint++; 3946 break; 3947 case 'p': // 'p' should be translated to 'r' by default. 3948 R = std::string("r"); 3949 break; 3950 default: 3951 return std::string(1, *Constraint); 3952 } 3953 return R; 3954 } 3955 virtual bool validateConstraintModifier(StringRef Constraint, 3956 const char Modifier, 3957 unsigned Size) const { 3958 bool isOutput = (Constraint[0] == '='); 3959 bool isInOut = (Constraint[0] == '+'); 3960 3961 // Strip off constraint modifiers. 3962 while (Constraint[0] == '=' || 3963 Constraint[0] == '+' || 3964 Constraint[0] == '&') 3965 Constraint = Constraint.substr(1); 3966 3967 switch (Constraint[0]) { 3968 default: break; 3969 case 'r': { 3970 switch (Modifier) { 3971 default: 3972 return (isInOut || isOutput || Size <= 32); 3973 case 'q': 3974 // A register of size 32 cannot fit a vector type. 3975 return false; 3976 } 3977 } 3978 } 3979 3980 return true; 3981 } 3982 virtual const char *getClobbers() const { 3983 // FIXME: Is this really right? 3984 return ""; 3985 } 3986 3987 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3988 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 3989 } 3990 3991 virtual int getEHDataRegisterNumber(unsigned RegNo) const { 3992 if (RegNo == 0) return 0; 3993 if (RegNo == 1) return 1; 3994 return -1; 3995 } 3996 }; 3997 3998 bool ARMTargetInfo::setFPMath(StringRef Name) { 3999 if (Name == "neon") { 4000 FPMath = FP_Neon; 4001 return true; 4002 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4003 Name == "vfp4") { 4004 FPMath = FP_VFP; 4005 return true; 4006 } 4007 return false; 4008 } 4009 4010 const char * const ARMTargetInfo::GCCRegNames[] = { 4011 // Integer registers 4012 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4013 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4014 4015 // Float registers 4016 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4017 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4018 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4019 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4020 4021 // Double registers 4022 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4023 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4024 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4025 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4026 4027 // Quad registers 4028 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4029 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4030 }; 4031 4032 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4033 unsigned &NumNames) const { 4034 Names = GCCRegNames; 4035 NumNames = llvm::array_lengthof(GCCRegNames); 4036 } 4037 4038 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4039 { { "a1" }, "r0" }, 4040 { { "a2" }, "r1" }, 4041 { { "a3" }, "r2" }, 4042 { { "a4" }, "r3" }, 4043 { { "v1" }, "r4" }, 4044 { { "v2" }, "r5" }, 4045 { { "v3" }, "r6" }, 4046 { { "v4" }, "r7" }, 4047 { { "v5" }, "r8" }, 4048 { { "v6", "rfp" }, "r9" }, 4049 { { "sl" }, "r10" }, 4050 { { "fp" }, "r11" }, 4051 { { "ip" }, "r12" }, 4052 { { "r13" }, "sp" }, 4053 { { "r14" }, "lr" }, 4054 { { "r15" }, "pc" }, 4055 // The S, D and Q registers overlap, but aren't really aliases; we 4056 // don't want to substitute one of these for a different-sized one. 4057 }; 4058 4059 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4060 unsigned &NumAliases) const { 4061 Aliases = GCCRegAliases; 4062 NumAliases = llvm::array_lengthof(GCCRegAliases); 4063 } 4064 4065 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4066 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4067 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4068 ALL_LANGUAGES }, 4069 #include "clang/Basic/BuiltinsARM.def" 4070 }; 4071 } // end anonymous namespace. 4072 4073 namespace { 4074 class DarwinARMTargetInfo : 4075 public DarwinTargetInfo<ARMTargetInfo> { 4076 protected: 4077 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4078 MacroBuilder &Builder) const { 4079 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4080 } 4081 4082 public: 4083 DarwinARMTargetInfo(const llvm::Triple &Triple) 4084 : DarwinTargetInfo<ARMTargetInfo>(Triple) { 4085 HasAlignMac68kSupport = true; 4086 // iOS always has 64-bit atomic instructions. 4087 // FIXME: This should be based off of the target features in ARMTargetInfo. 4088 MaxAtomicInlineWidth = 64; 4089 4090 // Darwin on iOS uses a variant of the ARM C++ ABI. 4091 TheCXXABI.set(TargetCXXABI::iOS); 4092 } 4093 }; 4094 } // end anonymous namespace. 4095 4096 4097 namespace { 4098 // Hexagon abstract base class 4099 class HexagonTargetInfo : public TargetInfo { 4100 static const Builtin::Info BuiltinInfo[]; 4101 static const char * const GCCRegNames[]; 4102 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4103 std::string CPU; 4104 public: 4105 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4106 BigEndian = false; 4107 DescriptionString = ("e-p:32:32:32-" 4108 "i64:64:64-i32:32:32-i16:16:16-i1:32:32-" 4109 "f64:64:64-f32:32:32-a0:0-n32"); 4110 4111 // {} in inline assembly are packet specifiers, not assembly variant 4112 // specifiers. 4113 NoAsmVariants = true; 4114 } 4115 4116 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4117 unsigned &NumRecords) const { 4118 Records = BuiltinInfo; 4119 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 4120 } 4121 4122 virtual bool validateAsmConstraint(const char *&Name, 4123 TargetInfo::ConstraintInfo &Info) const { 4124 return true; 4125 } 4126 4127 virtual void getTargetDefines(const LangOptions &Opts, 4128 MacroBuilder &Builder) const; 4129 4130 virtual bool hasFeature(StringRef Feature) const { 4131 return Feature == "hexagon"; 4132 } 4133 4134 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4135 return TargetInfo::CharPtrBuiltinVaList; 4136 } 4137 virtual void getGCCRegNames(const char * const *&Names, 4138 unsigned &NumNames) const; 4139 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4140 unsigned &NumAliases) const; 4141 virtual const char *getClobbers() const { 4142 return ""; 4143 } 4144 4145 static const char *getHexagonCPUSuffix(StringRef Name) { 4146 return llvm::StringSwitch<const char*>(Name) 4147 .Case("hexagonv4", "4") 4148 .Case("hexagonv5", "5") 4149 .Default(0); 4150 } 4151 4152 virtual bool setCPU(const std::string &Name) { 4153 if (!getHexagonCPUSuffix(Name)) 4154 return false; 4155 4156 CPU = Name; 4157 return true; 4158 } 4159 }; 4160 4161 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 4162 MacroBuilder &Builder) const { 4163 Builder.defineMacro("qdsp6"); 4164 Builder.defineMacro("__qdsp6", "1"); 4165 Builder.defineMacro("__qdsp6__", "1"); 4166 4167 Builder.defineMacro("hexagon"); 4168 Builder.defineMacro("__hexagon", "1"); 4169 Builder.defineMacro("__hexagon__", "1"); 4170 4171 if(CPU == "hexagonv1") { 4172 Builder.defineMacro("__HEXAGON_V1__"); 4173 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 4174 if(Opts.HexagonQdsp6Compat) { 4175 Builder.defineMacro("__QDSP6_V1__"); 4176 Builder.defineMacro("__QDSP6_ARCH__", "1"); 4177 } 4178 } 4179 else if(CPU == "hexagonv2") { 4180 Builder.defineMacro("__HEXAGON_V2__"); 4181 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 4182 if(Opts.HexagonQdsp6Compat) { 4183 Builder.defineMacro("__QDSP6_V2__"); 4184 Builder.defineMacro("__QDSP6_ARCH__", "2"); 4185 } 4186 } 4187 else if(CPU == "hexagonv3") { 4188 Builder.defineMacro("__HEXAGON_V3__"); 4189 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 4190 if(Opts.HexagonQdsp6Compat) { 4191 Builder.defineMacro("__QDSP6_V3__"); 4192 Builder.defineMacro("__QDSP6_ARCH__", "3"); 4193 } 4194 } 4195 else if(CPU == "hexagonv4") { 4196 Builder.defineMacro("__HEXAGON_V4__"); 4197 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 4198 if(Opts.HexagonQdsp6Compat) { 4199 Builder.defineMacro("__QDSP6_V4__"); 4200 Builder.defineMacro("__QDSP6_ARCH__", "4"); 4201 } 4202 } 4203 else if(CPU == "hexagonv5") { 4204 Builder.defineMacro("__HEXAGON_V5__"); 4205 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 4206 if(Opts.HexagonQdsp6Compat) { 4207 Builder.defineMacro("__QDSP6_V5__"); 4208 Builder.defineMacro("__QDSP6_ARCH__", "5"); 4209 } 4210 } 4211 } 4212 4213 const char * const HexagonTargetInfo::GCCRegNames[] = { 4214 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4215 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4216 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4217 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 4218 "p0", "p1", "p2", "p3", 4219 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 4220 }; 4221 4222 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 4223 unsigned &NumNames) const { 4224 Names = GCCRegNames; 4225 NumNames = llvm::array_lengthof(GCCRegNames); 4226 } 4227 4228 4229 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 4230 { { "sp" }, "r29" }, 4231 { { "fp" }, "r30" }, 4232 { { "lr" }, "r31" }, 4233 }; 4234 4235 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4236 unsigned &NumAliases) const { 4237 Aliases = GCCRegAliases; 4238 NumAliases = llvm::array_lengthof(GCCRegAliases); 4239 } 4240 4241 4242 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 4243 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4244 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4245 ALL_LANGUAGES }, 4246 #include "clang/Basic/BuiltinsHexagon.def" 4247 }; 4248 } 4249 4250 4251 namespace { 4252 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 4253 class SparcTargetInfo : public TargetInfo { 4254 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4255 static const char * const GCCRegNames[]; 4256 bool SoftFloat; 4257 public: 4258 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {} 4259 4260 virtual bool HandleTargetFeatures(std::vector<std::string> &Features, 4261 DiagnosticsEngine &Diags) { 4262 SoftFloat = false; 4263 for (unsigned i = 0, e = Features.size(); i != e; ++i) 4264 if (Features[i] == "+soft-float") 4265 SoftFloat = true; 4266 return true; 4267 } 4268 virtual void getTargetDefines(const LangOptions &Opts, 4269 MacroBuilder &Builder) const { 4270 DefineStd(Builder, "sparc", Opts); 4271 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4272 4273 if (SoftFloat) 4274 Builder.defineMacro("SOFT_FLOAT", "1"); 4275 } 4276 4277 virtual bool hasFeature(StringRef Feature) const { 4278 return llvm::StringSwitch<bool>(Feature) 4279 .Case("softfloat", SoftFloat) 4280 .Case("sparc", true) 4281 .Default(false); 4282 } 4283 4284 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4285 unsigned &NumRecords) const { 4286 // FIXME: Implement! 4287 } 4288 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4289 return TargetInfo::VoidPtrBuiltinVaList; 4290 } 4291 virtual void getGCCRegNames(const char * const *&Names, 4292 unsigned &NumNames) const; 4293 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4294 unsigned &NumAliases) const; 4295 virtual bool validateAsmConstraint(const char *&Name, 4296 TargetInfo::ConstraintInfo &info) const { 4297 // FIXME: Implement! 4298 return false; 4299 } 4300 virtual const char *getClobbers() const { 4301 // FIXME: Implement! 4302 return ""; 4303 } 4304 }; 4305 4306 const char * const SparcTargetInfo::GCCRegNames[] = { 4307 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4308 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4309 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4310 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 4311 }; 4312 4313 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 4314 unsigned &NumNames) const { 4315 Names = GCCRegNames; 4316 NumNames = llvm::array_lengthof(GCCRegNames); 4317 } 4318 4319 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 4320 { { "g0" }, "r0" }, 4321 { { "g1" }, "r1" }, 4322 { { "g2" }, "r2" }, 4323 { { "g3" }, "r3" }, 4324 { { "g4" }, "r4" }, 4325 { { "g5" }, "r5" }, 4326 { { "g6" }, "r6" }, 4327 { { "g7" }, "r7" }, 4328 { { "o0" }, "r8" }, 4329 { { "o1" }, "r9" }, 4330 { { "o2" }, "r10" }, 4331 { { "o3" }, "r11" }, 4332 { { "o4" }, "r12" }, 4333 { { "o5" }, "r13" }, 4334 { { "o6", "sp" }, "r14" }, 4335 { { "o7" }, "r15" }, 4336 { { "l0" }, "r16" }, 4337 { { "l1" }, "r17" }, 4338 { { "l2" }, "r18" }, 4339 { { "l3" }, "r19" }, 4340 { { "l4" }, "r20" }, 4341 { { "l5" }, "r21" }, 4342 { { "l6" }, "r22" }, 4343 { { "l7" }, "r23" }, 4344 { { "i0" }, "r24" }, 4345 { { "i1" }, "r25" }, 4346 { { "i2" }, "r26" }, 4347 { { "i3" }, "r27" }, 4348 { { "i4" }, "r28" }, 4349 { { "i5" }, "r29" }, 4350 { { "i6", "fp" }, "r30" }, 4351 { { "i7" }, "r31" }, 4352 }; 4353 4354 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4355 unsigned &NumAliases) const { 4356 Aliases = GCCRegAliases; 4357 NumAliases = llvm::array_lengthof(GCCRegAliases); 4358 } 4359 4360 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 4361 class SparcV8TargetInfo : public SparcTargetInfo { 4362 public: 4363 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4364 // FIXME: Support Sparc quad-precision long double? 4365 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 4366 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"; 4367 } 4368 4369 virtual void getTargetDefines(const LangOptions &Opts, 4370 MacroBuilder &Builder) const { 4371 SparcTargetInfo::getTargetDefines(Opts, Builder); 4372 Builder.defineMacro("__sparcv8"); 4373 } 4374 }; 4375 4376 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 4377 class SparcV9TargetInfo : public SparcTargetInfo { 4378 public: 4379 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4380 // FIXME: Support Sparc quad-precision long double? 4381 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 4382 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32:64-S128"; 4383 // This is an LP64 platform. 4384 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4385 4386 // OpenBSD uses long long for int64_t and intmax_t. 4387 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 4388 IntMaxType = SignedLongLong; 4389 UIntMaxType = UnsignedLongLong; 4390 } else { 4391 IntMaxType = SignedLong; 4392 UIntMaxType = UnsignedLong; 4393 } 4394 Int64Type = IntMaxType; 4395 } 4396 4397 virtual void getTargetDefines(const LangOptions &Opts, 4398 MacroBuilder &Builder) const { 4399 SparcTargetInfo::getTargetDefines(Opts, Builder); 4400 Builder.defineMacro("__sparcv9"); 4401 Builder.defineMacro("__arch64__"); 4402 // Solaris and its derivative AuroraUX don't need these variants, but the 4403 // BSDs do. 4404 if (getTriple().getOS() != llvm::Triple::Solaris && 4405 getTriple().getOS() != llvm::Triple::AuroraUX) { 4406 Builder.defineMacro("__sparc64__"); 4407 Builder.defineMacro("__sparc_v9__"); 4408 Builder.defineMacro("__sparcv9__"); 4409 } 4410 } 4411 }; 4412 4413 } // end anonymous namespace. 4414 4415 namespace { 4416 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> { 4417 public: 4418 AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple) 4419 : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) { 4420 SizeType = UnsignedInt; 4421 PtrDiffType = SignedInt; 4422 } 4423 }; 4424 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 4425 public: 4426 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 4427 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 4428 SizeType = UnsignedInt; 4429 PtrDiffType = SignedInt; 4430 } 4431 }; 4432 } // end anonymous namespace. 4433 4434 namespace { 4435 class SystemZTargetInfo : public TargetInfo { 4436 static const char *const GCCRegNames[]; 4437 4438 public: 4439 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4440 TLSSupported = true; 4441 IntWidth = IntAlign = 32; 4442 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 4443 PointerWidth = PointerAlign = 64; 4444 LongDoubleWidth = 128; 4445 LongDoubleAlign = 64; 4446 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4447 MinGlobalAlign = 16; 4448 DescriptionString = "E-p:64:64:64-i1:8:16-i8:8:16-i16:16-i32:32-i64:64" 4449 "-f32:32-f64:64-f128:64-a0:8:16-n32:64"; 4450 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4451 } 4452 virtual void getTargetDefines(const LangOptions &Opts, 4453 MacroBuilder &Builder) const { 4454 Builder.defineMacro("__s390__"); 4455 Builder.defineMacro("__s390x__"); 4456 Builder.defineMacro("__zarch__"); 4457 Builder.defineMacro("__LONG_DOUBLE_128__"); 4458 } 4459 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4460 unsigned &NumRecords) const { 4461 // FIXME: Implement. 4462 Records = 0; 4463 NumRecords = 0; 4464 } 4465 4466 virtual void getGCCRegNames(const char *const *&Names, 4467 unsigned &NumNames) const; 4468 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4469 unsigned &NumAliases) const { 4470 // No aliases. 4471 Aliases = 0; 4472 NumAliases = 0; 4473 } 4474 virtual bool validateAsmConstraint(const char *&Name, 4475 TargetInfo::ConstraintInfo &info) const; 4476 virtual const char *getClobbers() const { 4477 // FIXME: Is this really right? 4478 return ""; 4479 } 4480 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4481 return TargetInfo::SystemZBuiltinVaList; 4482 } 4483 virtual bool setCPU(const std::string &Name) { 4484 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4485 .Case("z10", true) 4486 .Case("z196", true) 4487 .Case("zEC12", true) 4488 .Default(false); 4489 4490 // No need to store the CPU yet. There aren't any CPU-specific 4491 // macros to define. 4492 return CPUKnown; 4493 } 4494 }; 4495 4496 const char *const SystemZTargetInfo::GCCRegNames[] = { 4497 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4498 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4499 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 4500 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 4501 }; 4502 4503 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 4504 unsigned &NumNames) const { 4505 Names = GCCRegNames; 4506 NumNames = llvm::array_lengthof(GCCRegNames); 4507 } 4508 4509 bool SystemZTargetInfo:: 4510 validateAsmConstraint(const char *&Name, 4511 TargetInfo::ConstraintInfo &Info) const { 4512 switch (*Name) { 4513 default: 4514 return false; 4515 4516 case 'a': // Address register 4517 case 'd': // Data register (equivalent to 'r') 4518 case 'f': // Floating-point register 4519 Info.setAllowsRegister(); 4520 return true; 4521 4522 case 'I': // Unsigned 8-bit constant 4523 case 'J': // Unsigned 12-bit constant 4524 case 'K': // Signed 16-bit constant 4525 case 'L': // Signed 20-bit displacement (on all targets we support) 4526 case 'M': // 0x7fffffff 4527 return true; 4528 4529 case 'Q': // Memory with base and unsigned 12-bit displacement 4530 case 'R': // Likewise, plus an index 4531 case 'S': // Memory with base and signed 20-bit displacement 4532 case 'T': // Likewise, plus an index 4533 Info.setAllowsMemory(); 4534 return true; 4535 } 4536 } 4537 } 4538 4539 namespace { 4540 class MSP430TargetInfo : public TargetInfo { 4541 static const char * const GCCRegNames[]; 4542 public: 4543 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4544 BigEndian = false; 4545 TLSSupported = false; 4546 IntWidth = 16; IntAlign = 16; 4547 LongWidth = 32; LongLongWidth = 64; 4548 LongAlign = LongLongAlign = 16; 4549 PointerWidth = 16; PointerAlign = 16; 4550 SuitableAlign = 16; 4551 SizeType = UnsignedInt; 4552 IntMaxType = SignedLongLong; 4553 UIntMaxType = UnsignedLongLong; 4554 IntPtrType = SignedInt; 4555 PtrDiffType = SignedInt; 4556 SigAtomicType = SignedLong; 4557 DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"; 4558 } 4559 virtual void getTargetDefines(const LangOptions &Opts, 4560 MacroBuilder &Builder) const { 4561 Builder.defineMacro("MSP430"); 4562 Builder.defineMacro("__MSP430__"); 4563 // FIXME: defines for different 'flavours' of MCU 4564 } 4565 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4566 unsigned &NumRecords) const { 4567 // FIXME: Implement. 4568 Records = 0; 4569 NumRecords = 0; 4570 } 4571 virtual bool hasFeature(StringRef Feature) const { 4572 return Feature == "msp430"; 4573 } 4574 virtual void getGCCRegNames(const char * const *&Names, 4575 unsigned &NumNames) const; 4576 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4577 unsigned &NumAliases) const { 4578 // No aliases. 4579 Aliases = 0; 4580 NumAliases = 0; 4581 } 4582 virtual bool validateAsmConstraint(const char *&Name, 4583 TargetInfo::ConstraintInfo &info) const { 4584 // No target constraints for now. 4585 return false; 4586 } 4587 virtual const char *getClobbers() const { 4588 // FIXME: Is this really right? 4589 return ""; 4590 } 4591 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4592 // FIXME: implement 4593 return TargetInfo::CharPtrBuiltinVaList; 4594 } 4595 }; 4596 4597 const char * const MSP430TargetInfo::GCCRegNames[] = { 4598 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4599 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 4600 }; 4601 4602 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 4603 unsigned &NumNames) const { 4604 Names = GCCRegNames; 4605 NumNames = llvm::array_lengthof(GCCRegNames); 4606 } 4607 } 4608 4609 namespace { 4610 4611 // LLVM and Clang cannot be used directly to output native binaries for 4612 // target, but is used to compile C code to llvm bitcode with correct 4613 // type and alignment information. 4614 // 4615 // TCE uses the llvm bitcode as input and uses it for generating customized 4616 // target processor and program binary. TCE co-design environment is 4617 // publicly available in http://tce.cs.tut.fi 4618 4619 static const unsigned TCEOpenCLAddrSpaceMap[] = { 4620 3, // opencl_global 4621 4, // opencl_local 4622 5, // opencl_constant 4623 0, // cuda_device 4624 0, // cuda_constant 4625 0 // cuda_shared 4626 }; 4627 4628 class TCETargetInfo : public TargetInfo{ 4629 public: 4630 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4631 TLSSupported = false; 4632 IntWidth = 32; 4633 LongWidth = LongLongWidth = 32; 4634 PointerWidth = 32; 4635 IntAlign = 32; 4636 LongAlign = LongLongAlign = 32; 4637 PointerAlign = 32; 4638 SuitableAlign = 32; 4639 SizeType = UnsignedInt; 4640 IntMaxType = SignedLong; 4641 UIntMaxType = UnsignedLong; 4642 IntPtrType = SignedInt; 4643 PtrDiffType = SignedInt; 4644 FloatWidth = 32; 4645 FloatAlign = 32; 4646 DoubleWidth = 32; 4647 DoubleAlign = 32; 4648 LongDoubleWidth = 32; 4649 LongDoubleAlign = 32; 4650 FloatFormat = &llvm::APFloat::IEEEsingle; 4651 DoubleFormat = &llvm::APFloat::IEEEsingle; 4652 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 4653 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-" 4654 "i16:16:32-i32:32:32-i64:32:32-" 4655 "f32:32:32-f64:32:32-v64:32:32-" 4656 "v128:32:32-a0:0:32-n32"; 4657 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 4658 UseAddrSpaceMapMangling = true; 4659 } 4660 4661 virtual void getTargetDefines(const LangOptions &Opts, 4662 MacroBuilder &Builder) const { 4663 DefineStd(Builder, "tce", Opts); 4664 Builder.defineMacro("__TCE__"); 4665 Builder.defineMacro("__TCE_V1__"); 4666 } 4667 virtual bool hasFeature(StringRef Feature) const { 4668 return Feature == "tce"; 4669 } 4670 4671 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4672 unsigned &NumRecords) const {} 4673 virtual const char *getClobbers() const { 4674 return ""; 4675 } 4676 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4677 return TargetInfo::VoidPtrBuiltinVaList; 4678 } 4679 virtual void getGCCRegNames(const char * const *&Names, 4680 unsigned &NumNames) const {} 4681 virtual bool validateAsmConstraint(const char *&Name, 4682 TargetInfo::ConstraintInfo &info) const { 4683 return true; 4684 } 4685 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4686 unsigned &NumAliases) const {} 4687 }; 4688 } 4689 4690 namespace { 4691 class MipsTargetInfoBase : public TargetInfo { 4692 static const Builtin::Info BuiltinInfo[]; 4693 std::string CPU; 4694 bool IsMips16; 4695 bool IsMicromips; 4696 bool IsNan2008; 4697 bool IsSingleFloat; 4698 enum MipsFloatABI { 4699 HardFloat, SoftFloat 4700 } FloatABI; 4701 enum DspRevEnum { 4702 NoDSP, DSP1, DSP2 4703 } DspRev; 4704 bool HasMSA; 4705 4706 protected: 4707 std::string ABI; 4708 4709 public: 4710 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 4711 const std::string &CPUStr) 4712 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 4713 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 4714 DspRev(NoDSP), HasMSA(false), ABI(ABIStr) {} 4715 4716 virtual const char *getABI() const { return ABI.c_str(); } 4717 virtual bool setABI(const std::string &Name) = 0; 4718 virtual bool setCPU(const std::string &Name) { 4719 CPU = Name; 4720 return true; 4721 } 4722 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 4723 Features[ABI] = true; 4724 Features[CPU] = true; 4725 } 4726 4727 virtual void getTargetDefines(const LangOptions &Opts, 4728 MacroBuilder &Builder) const { 4729 DefineStd(Builder, "mips", Opts); 4730 Builder.defineMacro("_mips"); 4731 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4732 4733 switch (FloatABI) { 4734 case HardFloat: 4735 Builder.defineMacro("__mips_hard_float", Twine(1)); 4736 break; 4737 case SoftFloat: 4738 Builder.defineMacro("__mips_soft_float", Twine(1)); 4739 break; 4740 } 4741 4742 if (IsSingleFloat) 4743 Builder.defineMacro("__mips_single_float", Twine(1)); 4744 4745 if (IsMips16) 4746 Builder.defineMacro("__mips16", Twine(1)); 4747 4748 if (IsMicromips) 4749 Builder.defineMacro("__mips_micromips", Twine(1)); 4750 4751 if (IsNan2008) 4752 Builder.defineMacro("__mips_nan2008", Twine(1)); 4753 4754 switch (DspRev) { 4755 default: 4756 break; 4757 case DSP1: 4758 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 4759 Builder.defineMacro("__mips_dsp", Twine(1)); 4760 break; 4761 case DSP2: 4762 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 4763 Builder.defineMacro("__mips_dspr2", Twine(1)); 4764 Builder.defineMacro("__mips_dsp", Twine(1)); 4765 break; 4766 } 4767 4768 if (HasMSA) 4769 Builder.defineMacro("__mips_msa", Twine(1)); 4770 4771 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 4772 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 4773 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 4774 4775 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 4776 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 4777 } 4778 4779 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4780 unsigned &NumRecords) const { 4781 Records = BuiltinInfo; 4782 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 4783 } 4784 virtual bool hasFeature(StringRef Feature) const { 4785 return Feature == "mips"; 4786 } 4787 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4788 return TargetInfo::VoidPtrBuiltinVaList; 4789 } 4790 virtual void getGCCRegNames(const char * const *&Names, 4791 unsigned &NumNames) const { 4792 static const char * const GCCRegNames[] = { 4793 // CPU register names 4794 // Must match second column of GCCRegAliases 4795 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 4796 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 4797 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 4798 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 4799 // Floating point register names 4800 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 4801 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 4802 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 4803 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 4804 // Hi/lo and condition register names 4805 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 4806 "$fcc5","$fcc6","$fcc7" 4807 }; 4808 Names = GCCRegNames; 4809 NumNames = llvm::array_lengthof(GCCRegNames); 4810 } 4811 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4812 unsigned &NumAliases) const = 0; 4813 virtual bool validateAsmConstraint(const char *&Name, 4814 TargetInfo::ConstraintInfo &Info) const { 4815 switch (*Name) { 4816 default: 4817 return false; 4818 4819 case 'r': // CPU registers. 4820 case 'd': // Equivalent to "r" unless generating MIPS16 code. 4821 case 'y': // Equivalent to "r", backwards compatibility only. 4822 case 'f': // floating-point registers. 4823 case 'c': // $25 for indirect jumps 4824 case 'l': // lo register 4825 case 'x': // hilo register pair 4826 Info.setAllowsRegister(); 4827 return true; 4828 case 'R': // An address that can be used in a non-macro load or store 4829 Info.setAllowsMemory(); 4830 return true; 4831 } 4832 } 4833 4834 virtual const char *getClobbers() const { 4835 // FIXME: Implement! 4836 return ""; 4837 } 4838 4839 virtual bool HandleTargetFeatures(std::vector<std::string> &Features, 4840 DiagnosticsEngine &Diags) { 4841 IsMips16 = false; 4842 IsMicromips = false; 4843 IsNan2008 = false; 4844 IsSingleFloat = false; 4845 FloatABI = HardFloat; 4846 DspRev = NoDSP; 4847 4848 for (std::vector<std::string>::iterator it = Features.begin(), 4849 ie = Features.end(); it != ie; ++it) { 4850 if (*it == "+single-float") 4851 IsSingleFloat = true; 4852 else if (*it == "+soft-float") 4853 FloatABI = SoftFloat; 4854 else if (*it == "+mips16") 4855 IsMips16 = true; 4856 else if (*it == "+micromips") 4857 IsMicromips = true; 4858 else if (*it == "+dsp") 4859 DspRev = std::max(DspRev, DSP1); 4860 else if (*it == "+dspr2") 4861 DspRev = std::max(DspRev, DSP2); 4862 else if (*it == "+msa") 4863 HasMSA = true; 4864 else if (*it == "+nan2008") 4865 IsNan2008 = true; 4866 } 4867 4868 // Remove front-end specific options. 4869 std::vector<std::string>::iterator it = 4870 std::find(Features.begin(), Features.end(), "+soft-float"); 4871 if (it != Features.end()) 4872 Features.erase(it); 4873 it = std::find(Features.begin(), Features.end(), "+nan2008"); 4874 if (it != Features.end()) 4875 Features.erase(it); 4876 4877 return true; 4878 } 4879 4880 virtual int getEHDataRegisterNumber(unsigned RegNo) const { 4881 if (RegNo == 0) return 4; 4882 if (RegNo == 1) return 5; 4883 return -1; 4884 } 4885 }; 4886 4887 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 4888 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4889 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4890 ALL_LANGUAGES }, 4891 #include "clang/Basic/BuiltinsMips.def" 4892 }; 4893 4894 class Mips32TargetInfoBase : public MipsTargetInfoBase { 4895 public: 4896 Mips32TargetInfoBase(const llvm::Triple &Triple) 4897 : MipsTargetInfoBase(Triple, "o32", "mips32") { 4898 SizeType = UnsignedInt; 4899 PtrDiffType = SignedInt; 4900 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 4901 } 4902 virtual bool setABI(const std::string &Name) { 4903 if ((Name == "o32") || (Name == "eabi")) { 4904 ABI = Name; 4905 return true; 4906 } else if (Name == "32") { 4907 ABI = "o32"; 4908 return true; 4909 } else 4910 return false; 4911 } 4912 virtual void getTargetDefines(const LangOptions &Opts, 4913 MacroBuilder &Builder) const { 4914 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 4915 4916 if (ABI == "o32") { 4917 Builder.defineMacro("__mips_o32"); 4918 Builder.defineMacro("_ABIO32", "1"); 4919 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 4920 } 4921 else if (ABI == "eabi") 4922 Builder.defineMacro("__mips_eabi"); 4923 else 4924 llvm_unreachable("Invalid ABI for Mips32."); 4925 } 4926 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4927 unsigned &NumAliases) const { 4928 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 4929 { { "at" }, "$1" }, 4930 { { "v0" }, "$2" }, 4931 { { "v1" }, "$3" }, 4932 { { "a0" }, "$4" }, 4933 { { "a1" }, "$5" }, 4934 { { "a2" }, "$6" }, 4935 { { "a3" }, "$7" }, 4936 { { "t0" }, "$8" }, 4937 { { "t1" }, "$9" }, 4938 { { "t2" }, "$10" }, 4939 { { "t3" }, "$11" }, 4940 { { "t4" }, "$12" }, 4941 { { "t5" }, "$13" }, 4942 { { "t6" }, "$14" }, 4943 { { "t7" }, "$15" }, 4944 { { "s0" }, "$16" }, 4945 { { "s1" }, "$17" }, 4946 { { "s2" }, "$18" }, 4947 { { "s3" }, "$19" }, 4948 { { "s4" }, "$20" }, 4949 { { "s5" }, "$21" }, 4950 { { "s6" }, "$22" }, 4951 { { "s7" }, "$23" }, 4952 { { "t8" }, "$24" }, 4953 { { "t9" }, "$25" }, 4954 { { "k0" }, "$26" }, 4955 { { "k1" }, "$27" }, 4956 { { "gp" }, "$28" }, 4957 { { "sp","$sp" }, "$29" }, 4958 { { "fp","$fp" }, "$30" }, 4959 { { "ra" }, "$31" } 4960 }; 4961 Aliases = GCCRegAliases; 4962 NumAliases = llvm::array_lengthof(GCCRegAliases); 4963 } 4964 }; 4965 4966 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 4967 public: 4968 Mips32EBTargetInfo(const llvm::Triple &Triple) 4969 : Mips32TargetInfoBase(Triple) { 4970 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4971 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"; 4972 } 4973 virtual void getTargetDefines(const LangOptions &Opts, 4974 MacroBuilder &Builder) const { 4975 DefineStd(Builder, "MIPSEB", Opts); 4976 Builder.defineMacro("_MIPSEB"); 4977 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 4978 } 4979 }; 4980 4981 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 4982 public: 4983 Mips32ELTargetInfo(const llvm::Triple &Triple) 4984 : Mips32TargetInfoBase(Triple) { 4985 BigEndian = false; 4986 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4987 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"; 4988 } 4989 virtual void getTargetDefines(const LangOptions &Opts, 4990 MacroBuilder &Builder) const { 4991 DefineStd(Builder, "MIPSEL", Opts); 4992 Builder.defineMacro("_MIPSEL"); 4993 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 4994 } 4995 }; 4996 4997 class Mips64TargetInfoBase : public MipsTargetInfoBase { 4998 virtual void SetDescriptionString(const std::string &Name) = 0; 4999 public: 5000 Mips64TargetInfoBase(const llvm::Triple &Triple) 5001 : MipsTargetInfoBase(Triple, "n64", "mips64") { 5002 LongWidth = LongAlign = 64; 5003 PointerWidth = PointerAlign = 64; 5004 LongDoubleWidth = LongDoubleAlign = 128; 5005 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5006 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 5007 LongDoubleWidth = LongDoubleAlign = 64; 5008 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5009 } 5010 SuitableAlign = 128; 5011 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5012 } 5013 virtual bool setABI(const std::string &Name) { 5014 SetDescriptionString(Name); 5015 if (Name == "n32") { 5016 LongWidth = LongAlign = 32; 5017 PointerWidth = PointerAlign = 32; 5018 ABI = Name; 5019 return true; 5020 } else if (Name == "n64") { 5021 ABI = Name; 5022 return true; 5023 } else if (Name == "64") { 5024 ABI = "n64"; 5025 return true; 5026 } else 5027 return false; 5028 } 5029 virtual void getTargetDefines(const LangOptions &Opts, 5030 MacroBuilder &Builder) const { 5031 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5032 5033 Builder.defineMacro("__mips64"); 5034 Builder.defineMacro("__mips64__"); 5035 5036 if (ABI == "n32") { 5037 Builder.defineMacro("__mips_n32"); 5038 Builder.defineMacro("_ABIN32", "2"); 5039 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 5040 } 5041 else if (ABI == "n64") { 5042 Builder.defineMacro("__mips_n64"); 5043 Builder.defineMacro("_ABI64", "3"); 5044 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 5045 } 5046 else 5047 llvm_unreachable("Invalid ABI for Mips64."); 5048 } 5049 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5050 unsigned &NumAliases) const { 5051 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5052 { { "at" }, "$1" }, 5053 { { "v0" }, "$2" }, 5054 { { "v1" }, "$3" }, 5055 { { "a0" }, "$4" }, 5056 { { "a1" }, "$5" }, 5057 { { "a2" }, "$6" }, 5058 { { "a3" }, "$7" }, 5059 { { "a4" }, "$8" }, 5060 { { "a5" }, "$9" }, 5061 { { "a6" }, "$10" }, 5062 { { "a7" }, "$11" }, 5063 { { "t0" }, "$12" }, 5064 { { "t1" }, "$13" }, 5065 { { "t2" }, "$14" }, 5066 { { "t3" }, "$15" }, 5067 { { "s0" }, "$16" }, 5068 { { "s1" }, "$17" }, 5069 { { "s2" }, "$18" }, 5070 { { "s3" }, "$19" }, 5071 { { "s4" }, "$20" }, 5072 { { "s5" }, "$21" }, 5073 { { "s6" }, "$22" }, 5074 { { "s7" }, "$23" }, 5075 { { "t8" }, "$24" }, 5076 { { "t9" }, "$25" }, 5077 { { "k0" }, "$26" }, 5078 { { "k1" }, "$27" }, 5079 { { "gp" }, "$28" }, 5080 { { "sp","$sp" }, "$29" }, 5081 { { "fp","$fp" }, "$30" }, 5082 { { "ra" }, "$31" } 5083 }; 5084 Aliases = GCCRegAliases; 5085 NumAliases = llvm::array_lengthof(GCCRegAliases); 5086 } 5087 }; 5088 5089 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 5090 virtual void SetDescriptionString(const std::string &Name) { 5091 // Change DescriptionString only if ABI is n32. 5092 if (Name == "n32") 5093 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5094 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 5095 "v64:64:64-n32:64-S128"; 5096 } 5097 public: 5098 Mips64EBTargetInfo(const llvm::Triple &Triple) 5099 : Mips64TargetInfoBase(Triple) { 5100 // Default ABI is n64. 5101 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5102 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 5103 "v64:64:64-n32:64-S128"; 5104 } 5105 virtual void getTargetDefines(const LangOptions &Opts, 5106 MacroBuilder &Builder) const { 5107 DefineStd(Builder, "MIPSEB", Opts); 5108 Builder.defineMacro("_MIPSEB"); 5109 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5110 } 5111 }; 5112 5113 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 5114 virtual void SetDescriptionString(const std::string &Name) { 5115 // Change DescriptionString only if ABI is n32. 5116 if (Name == "n32") 5117 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5118 "i64:64:64-f32:32:32-f64:64:64-f128:128:128" 5119 "-v64:64:64-n32:64-S128"; 5120 } 5121 public: 5122 Mips64ELTargetInfo(const llvm::Triple &Triple) 5123 : Mips64TargetInfoBase(Triple) { 5124 // Default ABI is n64. 5125 BigEndian = false; 5126 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5127 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 5128 "v64:64:64-n32:64-S128"; 5129 } 5130 virtual void getTargetDefines(const LangOptions &Opts, 5131 MacroBuilder &Builder) const { 5132 DefineStd(Builder, "MIPSEL", Opts); 5133 Builder.defineMacro("_MIPSEL"); 5134 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5135 } 5136 }; 5137 } // end anonymous namespace. 5138 5139 namespace { 5140 class PNaClTargetInfo : public TargetInfo { 5141 public: 5142 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5143 BigEndian = false; 5144 this->UserLabelPrefix = ""; 5145 this->LongAlign = 32; 5146 this->LongWidth = 32; 5147 this->PointerAlign = 32; 5148 this->PointerWidth = 32; 5149 this->IntMaxType = TargetInfo::SignedLongLong; 5150 this->UIntMaxType = TargetInfo::UnsignedLongLong; 5151 this->Int64Type = TargetInfo::SignedLongLong; 5152 this->DoubleAlign = 64; 5153 this->LongDoubleWidth = 64; 5154 this->LongDoubleAlign = 64; 5155 this->SizeType = TargetInfo::UnsignedInt; 5156 this->PtrDiffType = TargetInfo::SignedInt; 5157 this->IntPtrType = TargetInfo::SignedInt; 5158 this->RegParmMax = 0; // Disallow regparm 5159 DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 5160 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32"; 5161 } 5162 5163 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 5164 } 5165 virtual void getArchDefines(const LangOptions &Opts, 5166 MacroBuilder &Builder) const { 5167 Builder.defineMacro("__le32__"); 5168 Builder.defineMacro("__pnacl__"); 5169 } 5170 virtual void getTargetDefines(const LangOptions &Opts, 5171 MacroBuilder &Builder) const { 5172 Builder.defineMacro("__LITTLE_ENDIAN__"); 5173 getArchDefines(Opts, Builder); 5174 } 5175 virtual bool hasFeature(StringRef Feature) const { 5176 return Feature == "pnacl"; 5177 } 5178 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5179 unsigned &NumRecords) const { 5180 } 5181 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5182 return TargetInfo::PNaClABIBuiltinVaList; 5183 } 5184 virtual void getGCCRegNames(const char * const *&Names, 5185 unsigned &NumNames) const; 5186 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5187 unsigned &NumAliases) const; 5188 virtual bool validateAsmConstraint(const char *&Name, 5189 TargetInfo::ConstraintInfo &Info) const { 5190 return false; 5191 } 5192 5193 virtual const char *getClobbers() const { 5194 return ""; 5195 } 5196 }; 5197 5198 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 5199 unsigned &NumNames) const { 5200 Names = NULL; 5201 NumNames = 0; 5202 } 5203 5204 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5205 unsigned &NumAliases) const { 5206 Aliases = NULL; 5207 NumAliases = 0; 5208 } 5209 } // end anonymous namespace. 5210 5211 namespace { 5212 static const unsigned SPIRAddrSpaceMap[] = { 5213 1, // opencl_global 5214 3, // opencl_local 5215 2, // opencl_constant 5216 0, // cuda_device 5217 0, // cuda_constant 5218 0 // cuda_shared 5219 }; 5220 class SPIRTargetInfo : public TargetInfo { 5221 public: 5222 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5223 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 5224 "SPIR target must use unknown OS"); 5225 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 5226 "SPIR target must use unknown environment type"); 5227 BigEndian = false; 5228 TLSSupported = false; 5229 LongWidth = LongAlign = 64; 5230 AddrSpaceMap = &SPIRAddrSpaceMap; 5231 UseAddrSpaceMapMangling = true; 5232 // Define available target features 5233 // These must be defined in sorted order! 5234 NoAsmVariants = true; 5235 } 5236 virtual void getTargetDefines(const LangOptions &Opts, 5237 MacroBuilder &Builder) const { 5238 DefineStd(Builder, "SPIR", Opts); 5239 } 5240 virtual bool hasFeature(StringRef Feature) const { 5241 return Feature == "spir"; 5242 } 5243 5244 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5245 unsigned &NumRecords) const {} 5246 virtual const char *getClobbers() const { 5247 return ""; 5248 } 5249 virtual void getGCCRegNames(const char * const *&Names, 5250 unsigned &NumNames) const {} 5251 virtual bool validateAsmConstraint(const char *&Name, 5252 TargetInfo::ConstraintInfo &info) const { 5253 return true; 5254 } 5255 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5256 unsigned &NumAliases) const {} 5257 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5258 return TargetInfo::VoidPtrBuiltinVaList; 5259 } 5260 }; 5261 5262 5263 class SPIR32TargetInfo : public SPIRTargetInfo { 5264 public: 5265 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5266 PointerWidth = PointerAlign = 32; 5267 SizeType = TargetInfo::UnsignedInt; 5268 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 5269 DescriptionString 5270 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 5271 "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-" 5272 "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-" 5273 "v512:512:512-v1024:1024:1024"; 5274 } 5275 virtual void getTargetDefines(const LangOptions &Opts, 5276 MacroBuilder &Builder) const { 5277 DefineStd(Builder, "SPIR32", Opts); 5278 } 5279 }; 5280 5281 class SPIR64TargetInfo : public SPIRTargetInfo { 5282 public: 5283 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5284 PointerWidth = PointerAlign = 64; 5285 SizeType = TargetInfo::UnsignedLong; 5286 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 5287 DescriptionString 5288 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 5289 "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-" 5290 "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-" 5291 "v512:512:512-v1024:1024:1024"; 5292 } 5293 virtual void getTargetDefines(const LangOptions &Opts, 5294 MacroBuilder &Builder) const { 5295 DefineStd(Builder, "SPIR64", Opts); 5296 } 5297 }; 5298 } 5299 5300 namespace { 5301 class XCoreTargetInfo : public TargetInfo { 5302 static const Builtin::Info BuiltinInfo[]; 5303 public: 5304 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5305 BigEndian = false; 5306 NoAsmVariants = true; 5307 LongLongAlign = 32; 5308 SuitableAlign = 32; 5309 DoubleAlign = LongDoubleAlign = 32; 5310 UseZeroLengthBitfieldAlignment = true; 5311 DescriptionString = "e-p:32:32:32-a0:0:32-n32" 5312 "-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32" 5313 "-f16:16:32-f32:32:32-f64:32:32"; 5314 } 5315 virtual void getTargetDefines(const LangOptions &Opts, 5316 MacroBuilder &Builder) const { 5317 Builder.defineMacro("__XS1B__"); 5318 } 5319 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5320 unsigned &NumRecords) const { 5321 Records = BuiltinInfo; 5322 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 5323 } 5324 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5325 return TargetInfo::VoidPtrBuiltinVaList; 5326 } 5327 virtual const char *getClobbers() const { 5328 return ""; 5329 } 5330 virtual void getGCCRegNames(const char * const *&Names, 5331 unsigned &NumNames) const { 5332 static const char * const GCCRegNames[] = { 5333 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5334 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 5335 }; 5336 Names = GCCRegNames; 5337 NumNames = llvm::array_lengthof(GCCRegNames); 5338 } 5339 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5340 unsigned &NumAliases) const { 5341 Aliases = NULL; 5342 NumAliases = 0; 5343 } 5344 virtual bool validateAsmConstraint(const char *&Name, 5345 TargetInfo::ConstraintInfo &Info) const { 5346 return false; 5347 } 5348 }; 5349 5350 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 5351 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5352 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5353 ALL_LANGUAGES }, 5354 #include "clang/Basic/BuiltinsXCore.def" 5355 }; 5356 } // end anonymous namespace. 5357 5358 5359 //===----------------------------------------------------------------------===// 5360 // Driver code 5361 //===----------------------------------------------------------------------===// 5362 5363 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 5364 llvm::Triple::OSType os = Triple.getOS(); 5365 5366 switch (Triple.getArch()) { 5367 default: 5368 return NULL; 5369 5370 case llvm::Triple::xcore: 5371 return new XCoreTargetInfo(Triple); 5372 5373 case llvm::Triple::hexagon: 5374 return new HexagonTargetInfo(Triple); 5375 5376 case llvm::Triple::aarch64: 5377 switch (os) { 5378 case llvm::Triple::Linux: 5379 return new LinuxTargetInfo<AArch64TargetInfo>(Triple); 5380 default: 5381 return new AArch64TargetInfo(Triple); 5382 } 5383 5384 case llvm::Triple::arm: 5385 case llvm::Triple::thumb: 5386 if (Triple.isOSDarwin()) 5387 return new DarwinARMTargetInfo(Triple); 5388 5389 switch (os) { 5390 case llvm::Triple::Linux: 5391 return new LinuxTargetInfo<ARMTargetInfo>(Triple); 5392 case llvm::Triple::FreeBSD: 5393 return new FreeBSDTargetInfo<ARMTargetInfo>(Triple); 5394 case llvm::Triple::NetBSD: 5395 return new NetBSDTargetInfo<ARMTargetInfo>(Triple); 5396 case llvm::Triple::OpenBSD: 5397 return new OpenBSDTargetInfo<ARMTargetInfo>(Triple); 5398 case llvm::Triple::Bitrig: 5399 return new BitrigTargetInfo<ARMTargetInfo>(Triple); 5400 case llvm::Triple::RTEMS: 5401 return new RTEMSTargetInfo<ARMTargetInfo>(Triple); 5402 case llvm::Triple::NaCl: 5403 return new NaClTargetInfo<ARMTargetInfo>(Triple); 5404 default: 5405 return new ARMTargetInfo(Triple); 5406 } 5407 5408 case llvm::Triple::msp430: 5409 return new MSP430TargetInfo(Triple); 5410 5411 case llvm::Triple::mips: 5412 switch (os) { 5413 case llvm::Triple::Linux: 5414 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 5415 case llvm::Triple::RTEMS: 5416 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 5417 case llvm::Triple::FreeBSD: 5418 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 5419 case llvm::Triple::NetBSD: 5420 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 5421 default: 5422 return new Mips32EBTargetInfo(Triple); 5423 } 5424 5425 case llvm::Triple::mipsel: 5426 switch (os) { 5427 case llvm::Triple::Linux: 5428 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 5429 case llvm::Triple::RTEMS: 5430 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 5431 case llvm::Triple::FreeBSD: 5432 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 5433 case llvm::Triple::NetBSD: 5434 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 5435 case llvm::Triple::NaCl: 5436 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 5437 default: 5438 return new Mips32ELTargetInfo(Triple); 5439 } 5440 5441 case llvm::Triple::mips64: 5442 switch (os) { 5443 case llvm::Triple::Linux: 5444 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 5445 case llvm::Triple::RTEMS: 5446 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 5447 case llvm::Triple::FreeBSD: 5448 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5449 case llvm::Triple::NetBSD: 5450 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5451 case llvm::Triple::OpenBSD: 5452 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5453 default: 5454 return new Mips64EBTargetInfo(Triple); 5455 } 5456 5457 case llvm::Triple::mips64el: 5458 switch (os) { 5459 case llvm::Triple::Linux: 5460 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 5461 case llvm::Triple::RTEMS: 5462 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 5463 case llvm::Triple::FreeBSD: 5464 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5465 case llvm::Triple::NetBSD: 5466 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5467 case llvm::Triple::OpenBSD: 5468 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5469 default: 5470 return new Mips64ELTargetInfo(Triple); 5471 } 5472 5473 case llvm::Triple::le32: 5474 switch (os) { 5475 case llvm::Triple::NaCl: 5476 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 5477 default: 5478 return NULL; 5479 } 5480 5481 case llvm::Triple::ppc: 5482 if (Triple.isOSDarwin()) 5483 return new DarwinPPC32TargetInfo(Triple); 5484 switch (os) { 5485 case llvm::Triple::Linux: 5486 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 5487 case llvm::Triple::FreeBSD: 5488 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 5489 case llvm::Triple::NetBSD: 5490 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 5491 case llvm::Triple::OpenBSD: 5492 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 5493 case llvm::Triple::RTEMS: 5494 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 5495 default: 5496 return new PPC32TargetInfo(Triple); 5497 } 5498 5499 case llvm::Triple::ppc64: 5500 if (Triple.isOSDarwin()) 5501 return new DarwinPPC64TargetInfo(Triple); 5502 switch (os) { 5503 case llvm::Triple::Linux: 5504 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 5505 case llvm::Triple::Lv2: 5506 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 5507 case llvm::Triple::FreeBSD: 5508 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 5509 case llvm::Triple::NetBSD: 5510 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 5511 default: 5512 return new PPC64TargetInfo(Triple); 5513 } 5514 5515 case llvm::Triple::ppc64le: 5516 switch (os) { 5517 case llvm::Triple::Linux: 5518 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 5519 default: 5520 return new PPC64TargetInfo(Triple); 5521 } 5522 5523 case llvm::Triple::nvptx: 5524 return new NVPTX32TargetInfo(Triple); 5525 case llvm::Triple::nvptx64: 5526 return new NVPTX64TargetInfo(Triple); 5527 5528 case llvm::Triple::r600: 5529 return new R600TargetInfo(Triple); 5530 5531 case llvm::Triple::sparc: 5532 switch (os) { 5533 case llvm::Triple::Linux: 5534 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 5535 case llvm::Triple::AuroraUX: 5536 return new AuroraUXSparcV8TargetInfo(Triple); 5537 case llvm::Triple::Solaris: 5538 return new SolarisSparcV8TargetInfo(Triple); 5539 case llvm::Triple::NetBSD: 5540 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 5541 case llvm::Triple::OpenBSD: 5542 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 5543 case llvm::Triple::RTEMS: 5544 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 5545 default: 5546 return new SparcV8TargetInfo(Triple); 5547 } 5548 5549 case llvm::Triple::sparcv9: 5550 switch (os) { 5551 case llvm::Triple::Linux: 5552 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 5553 case llvm::Triple::AuroraUX: 5554 return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple); 5555 case llvm::Triple::Solaris: 5556 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 5557 case llvm::Triple::NetBSD: 5558 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 5559 case llvm::Triple::OpenBSD: 5560 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 5561 case llvm::Triple::FreeBSD: 5562 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 5563 default: 5564 return new SparcV9TargetInfo(Triple); 5565 } 5566 5567 case llvm::Triple::systemz: 5568 switch (os) { 5569 case llvm::Triple::Linux: 5570 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 5571 default: 5572 return new SystemZTargetInfo(Triple); 5573 } 5574 5575 case llvm::Triple::tce: 5576 return new TCETargetInfo(Triple); 5577 5578 case llvm::Triple::x86: 5579 if (Triple.isOSDarwin()) 5580 return new DarwinI386TargetInfo(Triple); 5581 5582 switch (os) { 5583 case llvm::Triple::AuroraUX: 5584 return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple); 5585 case llvm::Triple::Linux: 5586 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 5587 case llvm::Triple::DragonFly: 5588 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 5589 case llvm::Triple::NetBSD: 5590 return new NetBSDI386TargetInfo(Triple); 5591 case llvm::Triple::OpenBSD: 5592 return new OpenBSDI386TargetInfo(Triple); 5593 case llvm::Triple::Bitrig: 5594 return new BitrigI386TargetInfo(Triple); 5595 case llvm::Triple::FreeBSD: 5596 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 5597 case llvm::Triple::KFreeBSD: 5598 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 5599 case llvm::Triple::Minix: 5600 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 5601 case llvm::Triple::Solaris: 5602 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 5603 case llvm::Triple::Cygwin: 5604 return new CygwinX86_32TargetInfo(Triple); 5605 case llvm::Triple::MinGW32: 5606 return new MinGWX86_32TargetInfo(Triple); 5607 case llvm::Triple::Win32: 5608 return new VisualStudioWindowsX86_32TargetInfo(Triple); 5609 case llvm::Triple::Haiku: 5610 return new HaikuX86_32TargetInfo(Triple); 5611 case llvm::Triple::RTEMS: 5612 return new RTEMSX86_32TargetInfo(Triple); 5613 case llvm::Triple::NaCl: 5614 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 5615 default: 5616 return new X86_32TargetInfo(Triple); 5617 } 5618 5619 case llvm::Triple::x86_64: 5620 if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO) 5621 return new DarwinX86_64TargetInfo(Triple); 5622 5623 switch (os) { 5624 case llvm::Triple::AuroraUX: 5625 return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple); 5626 case llvm::Triple::Linux: 5627 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 5628 case llvm::Triple::DragonFly: 5629 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 5630 case llvm::Triple::NetBSD: 5631 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 5632 case llvm::Triple::OpenBSD: 5633 return new OpenBSDX86_64TargetInfo(Triple); 5634 case llvm::Triple::Bitrig: 5635 return new BitrigX86_64TargetInfo(Triple); 5636 case llvm::Triple::FreeBSD: 5637 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 5638 case llvm::Triple::KFreeBSD: 5639 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 5640 case llvm::Triple::Solaris: 5641 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 5642 case llvm::Triple::MinGW32: 5643 return new MinGWX86_64TargetInfo(Triple); 5644 case llvm::Triple::Win32: // This is what Triple.h supports now. 5645 return new VisualStudioWindowsX86_64TargetInfo(Triple); 5646 case llvm::Triple::NaCl: 5647 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 5648 default: 5649 return new X86_64TargetInfo(Triple); 5650 } 5651 5652 case llvm::Triple::spir: { 5653 if (Triple.getOS() != llvm::Triple::UnknownOS || 5654 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 5655 return NULL; 5656 return new SPIR32TargetInfo(Triple); 5657 } 5658 case llvm::Triple::spir64: { 5659 if (Triple.getOS() != llvm::Triple::UnknownOS || 5660 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 5661 return NULL; 5662 return new SPIR64TargetInfo(Triple); 5663 } 5664 } 5665 } 5666 5667 /// CreateTargetInfo - Return the target info object for the specified target 5668 /// triple. 5669 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 5670 TargetOptions *Opts) { 5671 llvm::Triple Triple(Opts->Triple); 5672 5673 // Construct the target 5674 OwningPtr<TargetInfo> Target(AllocateTarget(Triple)); 5675 if (!Target) { 5676 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 5677 return 0; 5678 } 5679 Target->setTargetOpts(Opts); 5680 5681 // Set the target CPU if specified. 5682 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 5683 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 5684 return 0; 5685 } 5686 5687 // Set the target ABI if specified. 5688 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 5689 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 5690 return 0; 5691 } 5692 5693 // Set the target C++ ABI. 5694 if (!Opts->CXXABI.empty() && !Target->setCXXABI(Opts->CXXABI)) { 5695 Diags.Report(diag::err_target_unknown_cxxabi) << Opts->CXXABI; 5696 return 0; 5697 } 5698 5699 // Set the fp math unit. 5700 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 5701 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 5702 return 0; 5703 } 5704 5705 // Compute the default target features, we need the target to handle this 5706 // because features may have dependencies on one another. 5707 llvm::StringMap<bool> Features; 5708 Target->getDefaultFeatures(Features); 5709 5710 // Apply the user specified deltas. 5711 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 5712 I < N; ++I) { 5713 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 5714 // Apply the feature via the target. 5715 bool Enabled = Name[0] == '+'; 5716 Target->setFeatureEnabled(Features, Name + 1, Enabled); 5717 } 5718 5719 // Add the features to the compile options. 5720 // 5721 // FIXME: If we are completely confident that we have the right set, we only 5722 // need to pass the minuses. 5723 Opts->Features.clear(); 5724 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 5725 ie = Features.end(); it != ie; ++it) 5726 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 5727 if (!Target->HandleTargetFeatures(Opts->Features, Diags)) 5728 return 0; 5729 5730 return Target.take(); 5731 } 5732