1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 115 const llvm::Triple &Triple, 116 StringRef &PlatformName, 117 VersionTuple &PlatformMinVersion) { 118 Builder.defineMacro("__APPLE_CC__", "6000"); 119 Builder.defineMacro("__APPLE__"); 120 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 121 // AddressSanitizer doesn't play well with source fortification, which is on 122 // by default on Darwin. 123 if (Opts.Sanitize.has(SanitizerKind::Address)) 124 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 125 126 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 127 if (!Opts.ObjC1) { 128 // __weak is always defined, for use in blocks and with objc pointers. 129 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 130 Builder.defineMacro("__strong", ""); 131 Builder.defineMacro("__unsafe_unretained", ""); 132 } 133 134 if (Opts.Static) 135 Builder.defineMacro("__STATIC__"); 136 else 137 Builder.defineMacro("__DYNAMIC__"); 138 139 if (Opts.POSIXThreads) 140 Builder.defineMacro("_REENTRANT"); 141 142 // Get the platform type and version number from the triple. 143 unsigned Maj, Min, Rev; 144 if (Triple.isMacOSX()) { 145 Triple.getMacOSXVersion(Maj, Min, Rev); 146 PlatformName = "macos"; 147 } else { 148 Triple.getOSVersion(Maj, Min, Rev); 149 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 150 } 151 152 // If -target arch-pc-win32-macho option specified, we're 153 // generating code for Win32 ABI. No need to emit 154 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 155 if (PlatformName == "win32") { 156 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 157 return; 158 } 159 160 // Set the appropriate OS version define. 161 if (Triple.isiOS()) { 162 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 163 char Str[7]; 164 if (Maj < 10) { 165 Str[0] = '0' + Maj; 166 Str[1] = '0' + (Min / 10); 167 Str[2] = '0' + (Min % 10); 168 Str[3] = '0' + (Rev / 10); 169 Str[4] = '0' + (Rev % 10); 170 Str[5] = '\0'; 171 } else { 172 // Handle versions >= 10. 173 Str[0] = '0' + (Maj / 10); 174 Str[1] = '0' + (Maj % 10); 175 Str[2] = '0' + (Min / 10); 176 Str[3] = '0' + (Min % 10); 177 Str[4] = '0' + (Rev / 10); 178 Str[5] = '0' + (Rev % 10); 179 Str[6] = '\0'; 180 } 181 if (Triple.isTvOS()) 182 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 183 else 184 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 185 Str); 186 187 } else if (Triple.isWatchOS()) { 188 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 189 char Str[6]; 190 Str[0] = '0' + Maj; 191 Str[1] = '0' + (Min / 10); 192 Str[2] = '0' + (Min % 10); 193 Str[3] = '0' + (Rev / 10); 194 Str[4] = '0' + (Rev % 10); 195 Str[5] = '\0'; 196 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 197 } else if (Triple.isMacOSX()) { 198 // Note that the Driver allows versions which aren't representable in the 199 // define (because we only get a single digit for the minor and micro 200 // revision numbers). So, we limit them to the maximum representable 201 // version. 202 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 203 char Str[7]; 204 if (Maj < 10 || (Maj == 10 && Min < 10)) { 205 Str[0] = '0' + (Maj / 10); 206 Str[1] = '0' + (Maj % 10); 207 Str[2] = '0' + std::min(Min, 9U); 208 Str[3] = '0' + std::min(Rev, 9U); 209 Str[4] = '\0'; 210 } else { 211 // Handle versions > 10.9. 212 Str[0] = '0' + (Maj / 10); 213 Str[1] = '0' + (Maj % 10); 214 Str[2] = '0' + (Min / 10); 215 Str[3] = '0' + (Min % 10); 216 Str[4] = '0' + (Rev / 10); 217 Str[5] = '0' + (Rev % 10); 218 Str[6] = '\0'; 219 } 220 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 221 } 222 223 // Tell users about the kernel if there is one. 224 if (Triple.isOSDarwin()) 225 Builder.defineMacro("__MACH__"); 226 227 // The Watch ABI uses Dwarf EH. 228 if(Triple.isWatchABI()) 229 Builder.defineMacro("__ARM_DWARF_EH__"); 230 231 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 232 } 233 234 template<typename Target> 235 class DarwinTargetInfo : public OSTargetInfo<Target> { 236 protected: 237 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 238 MacroBuilder &Builder) const override { 239 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 240 this->PlatformMinVersion); 241 } 242 243 public: 244 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 245 : OSTargetInfo<Target>(Triple, Opts) { 246 // By default, no TLS, and we whitelist permitted architecture/OS 247 // combinations. 248 this->TLSSupported = false; 249 250 if (Triple.isMacOSX()) 251 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 252 else if (Triple.isiOS()) { 253 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 254 if (Triple.getArch() == llvm::Triple::x86_64 || 255 Triple.getArch() == llvm::Triple::aarch64) 256 this->TLSSupported = !Triple.isOSVersionLT(8); 257 else if (Triple.getArch() == llvm::Triple::x86 || 258 Triple.getArch() == llvm::Triple::arm || 259 Triple.getArch() == llvm::Triple::thumb) 260 this->TLSSupported = !Triple.isOSVersionLT(9); 261 } else if (Triple.isWatchOS()) 262 this->TLSSupported = !Triple.isOSVersionLT(2); 263 264 this->MCountName = "\01mcount"; 265 } 266 267 std::string isValidSectionSpecifier(StringRef SR) const override { 268 // Let MCSectionMachO validate this. 269 StringRef Segment, Section; 270 unsigned TAA, StubSize; 271 bool HasTAA; 272 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 273 TAA, HasTAA, StubSize); 274 } 275 276 const char *getStaticInitSectionSpecifier() const override { 277 // FIXME: We should return 0 when building kexts. 278 return "__TEXT,__StaticInit,regular,pure_instructions"; 279 } 280 281 /// Darwin does not support protected visibility. Darwin's "default" 282 /// is very similar to ELF's "protected"; Darwin requires a "weak" 283 /// attribute on declarations that can be dynamically replaced. 284 bool hasProtectedVisibility() const override { 285 return false; 286 } 287 288 unsigned getExnObjectAlignment() const override { 289 // The alignment of an exception object is 8-bytes for darwin since 290 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 291 // and therefore doesn't guarantee 16-byte alignment. 292 return 64; 293 } 294 }; 295 296 297 // DragonFlyBSD Target 298 template<typename Target> 299 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 300 protected: 301 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 302 MacroBuilder &Builder) const override { 303 // DragonFly defines; list based off of gcc output 304 Builder.defineMacro("__DragonFly__"); 305 Builder.defineMacro("__DragonFly_cc_version", "100001"); 306 Builder.defineMacro("__ELF__"); 307 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 308 Builder.defineMacro("__tune_i386__"); 309 DefineStd(Builder, "unix", Opts); 310 } 311 public: 312 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 313 : OSTargetInfo<Target>(Triple, Opts) { 314 switch (Triple.getArch()) { 315 default: 316 case llvm::Triple::x86: 317 case llvm::Triple::x86_64: 318 this->MCountName = ".mcount"; 319 break; 320 } 321 } 322 }; 323 324 #ifndef FREEBSD_CC_VERSION 325 #define FREEBSD_CC_VERSION 0U 326 #endif 327 328 // FreeBSD Target 329 template<typename Target> 330 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 331 protected: 332 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 333 MacroBuilder &Builder) const override { 334 // FreeBSD defines; list based off of gcc output 335 336 unsigned Release = Triple.getOSMajorVersion(); 337 if (Release == 0U) 338 Release = 8U; 339 unsigned CCVersion = FREEBSD_CC_VERSION; 340 if (CCVersion == 0U) 341 CCVersion = Release * 100000U + 1U; 342 343 Builder.defineMacro("__FreeBSD__", Twine(Release)); 344 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 345 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 346 DefineStd(Builder, "unix", Opts); 347 Builder.defineMacro("__ELF__"); 348 349 // On FreeBSD, wchar_t contains the number of the code point as 350 // used by the character set of the locale. These character sets are 351 // not necessarily a superset of ASCII. 352 // 353 // FIXME: This is wrong; the macro refers to the numerical values 354 // of wchar_t *literals*, which are not locale-dependent. However, 355 // FreeBSD systems apparently depend on us getting this wrong, and 356 // setting this to 1 is conforming even if all the basic source 357 // character literals have the same encoding as char and wchar_t. 358 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 359 } 360 public: 361 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 362 : OSTargetInfo<Target>(Triple, Opts) { 363 switch (Triple.getArch()) { 364 default: 365 case llvm::Triple::x86: 366 case llvm::Triple::x86_64: 367 this->MCountName = ".mcount"; 368 break; 369 case llvm::Triple::mips: 370 case llvm::Triple::mipsel: 371 case llvm::Triple::ppc: 372 case llvm::Triple::ppc64: 373 case llvm::Triple::ppc64le: 374 this->MCountName = "_mcount"; 375 break; 376 case llvm::Triple::arm: 377 this->MCountName = "__mcount"; 378 break; 379 } 380 } 381 }; 382 383 // GNU/kFreeBSD Target 384 template<typename Target> 385 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 386 protected: 387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 388 MacroBuilder &Builder) const override { 389 // GNU/kFreeBSD defines; list based off of gcc output 390 391 DefineStd(Builder, "unix", Opts); 392 Builder.defineMacro("__FreeBSD_kernel__"); 393 Builder.defineMacro("__GLIBC__"); 394 Builder.defineMacro("__ELF__"); 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 if (Opts.CPlusPlus) 398 Builder.defineMacro("_GNU_SOURCE"); 399 } 400 public: 401 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 402 : OSTargetInfo<Target>(Triple, Opts) {} 403 }; 404 405 // Haiku Target 406 template<typename Target> 407 class HaikuTargetInfo : public OSTargetInfo<Target> { 408 protected: 409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 410 MacroBuilder &Builder) const override { 411 // Haiku defines; list based off of gcc output 412 Builder.defineMacro("__HAIKU__"); 413 Builder.defineMacro("__ELF__"); 414 DefineStd(Builder, "unix", Opts); 415 } 416 public: 417 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 418 : OSTargetInfo<Target>(Triple, Opts) { 419 this->SizeType = TargetInfo::UnsignedLong; 420 this->IntPtrType = TargetInfo::SignedLong; 421 this->PtrDiffType = TargetInfo::SignedLong; 422 this->ProcessIDType = TargetInfo::SignedLong; 423 this->TLSSupported = false; 424 425 } 426 }; 427 428 // Minix Target 429 template<typename Target> 430 class MinixTargetInfo : public OSTargetInfo<Target> { 431 protected: 432 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 433 MacroBuilder &Builder) const override { 434 // Minix defines 435 436 Builder.defineMacro("__minix", "3"); 437 Builder.defineMacro("_EM_WSIZE", "4"); 438 Builder.defineMacro("_EM_PSIZE", "4"); 439 Builder.defineMacro("_EM_SSIZE", "2"); 440 Builder.defineMacro("_EM_LSIZE", "4"); 441 Builder.defineMacro("_EM_FSIZE", "4"); 442 Builder.defineMacro("_EM_DSIZE", "8"); 443 Builder.defineMacro("__ELF__"); 444 DefineStd(Builder, "unix", Opts); 445 } 446 public: 447 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 448 : OSTargetInfo<Target>(Triple, Opts) {} 449 }; 450 451 // Linux target 452 template<typename Target> 453 class LinuxTargetInfo : public OSTargetInfo<Target> { 454 protected: 455 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 456 MacroBuilder &Builder) const override { 457 // Linux defines; list based off of gcc output 458 DefineStd(Builder, "unix", Opts); 459 DefineStd(Builder, "linux", Opts); 460 Builder.defineMacro("__gnu_linux__"); 461 Builder.defineMacro("__ELF__"); 462 if (Triple.isAndroid()) { 463 Builder.defineMacro("__ANDROID__", "1"); 464 unsigned Maj, Min, Rev; 465 Triple.getEnvironmentVersion(Maj, Min, Rev); 466 this->PlatformName = "android"; 467 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 468 } 469 if (Opts.POSIXThreads) 470 Builder.defineMacro("_REENTRANT"); 471 if (Opts.CPlusPlus) 472 Builder.defineMacro("_GNU_SOURCE"); 473 if (this->HasFloat128) 474 Builder.defineMacro("__FLOAT128__"); 475 } 476 public: 477 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 478 : OSTargetInfo<Target>(Triple, Opts) { 479 this->WIntType = TargetInfo::UnsignedInt; 480 481 switch (Triple.getArch()) { 482 default: 483 break; 484 case llvm::Triple::ppc: 485 case llvm::Triple::ppc64: 486 case llvm::Triple::ppc64le: 487 this->MCountName = "_mcount"; 488 break; 489 case llvm::Triple::x86: 490 case llvm::Triple::x86_64: 491 case llvm::Triple::systemz: 492 this->HasFloat128 = true; 493 break; 494 } 495 } 496 497 const char *getStaticInitSectionSpecifier() const override { 498 return ".text.startup"; 499 } 500 }; 501 502 // NetBSD Target 503 template<typename Target> 504 class NetBSDTargetInfo : public OSTargetInfo<Target> { 505 protected: 506 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 507 MacroBuilder &Builder) const override { 508 // NetBSD defines; list based off of gcc output 509 Builder.defineMacro("__NetBSD__"); 510 Builder.defineMacro("__unix__"); 511 Builder.defineMacro("__ELF__"); 512 if (Opts.POSIXThreads) 513 Builder.defineMacro("_POSIX_THREADS"); 514 515 switch (Triple.getArch()) { 516 default: 517 break; 518 case llvm::Triple::arm: 519 case llvm::Triple::armeb: 520 case llvm::Triple::thumb: 521 case llvm::Triple::thumbeb: 522 Builder.defineMacro("__ARM_DWARF_EH__"); 523 break; 524 } 525 } 526 public: 527 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 528 : OSTargetInfo<Target>(Triple, Opts) { 529 this->MCountName = "_mcount"; 530 } 531 }; 532 533 // OpenBSD Target 534 template<typename Target> 535 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 536 protected: 537 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 538 MacroBuilder &Builder) const override { 539 // OpenBSD defines; list based off of gcc output 540 541 Builder.defineMacro("__OpenBSD__"); 542 DefineStd(Builder, "unix", Opts); 543 Builder.defineMacro("__ELF__"); 544 if (Opts.POSIXThreads) 545 Builder.defineMacro("_REENTRANT"); 546 } 547 public: 548 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 549 : OSTargetInfo<Target>(Triple, Opts) { 550 this->TLSSupported = false; 551 552 switch (Triple.getArch()) { 553 default: 554 case llvm::Triple::x86: 555 case llvm::Triple::x86_64: 556 case llvm::Triple::arm: 557 case llvm::Triple::sparc: 558 this->MCountName = "__mcount"; 559 break; 560 case llvm::Triple::mips64: 561 case llvm::Triple::mips64el: 562 case llvm::Triple::ppc: 563 case llvm::Triple::sparcv9: 564 this->MCountName = "_mcount"; 565 break; 566 } 567 } 568 }; 569 570 // Bitrig Target 571 template<typename Target> 572 class BitrigTargetInfo : public OSTargetInfo<Target> { 573 protected: 574 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 575 MacroBuilder &Builder) const override { 576 // Bitrig defines; list based off of gcc output 577 578 Builder.defineMacro("__Bitrig__"); 579 DefineStd(Builder, "unix", Opts); 580 Builder.defineMacro("__ELF__"); 581 if (Opts.POSIXThreads) 582 Builder.defineMacro("_REENTRANT"); 583 584 switch (Triple.getArch()) { 585 default: 586 break; 587 case llvm::Triple::arm: 588 case llvm::Triple::armeb: 589 case llvm::Triple::thumb: 590 case llvm::Triple::thumbeb: 591 Builder.defineMacro("__ARM_DWARF_EH__"); 592 break; 593 } 594 } 595 public: 596 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 597 : OSTargetInfo<Target>(Triple, Opts) { 598 this->MCountName = "__mcount"; 599 } 600 }; 601 602 // PSP Target 603 template<typename Target> 604 class PSPTargetInfo : public OSTargetInfo<Target> { 605 protected: 606 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 607 MacroBuilder &Builder) const override { 608 // PSP defines; list based on the output of the pspdev gcc toolchain. 609 Builder.defineMacro("PSP"); 610 Builder.defineMacro("_PSP"); 611 Builder.defineMacro("__psp__"); 612 Builder.defineMacro("__ELF__"); 613 } 614 public: 615 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 616 }; 617 618 // PS3 PPU Target 619 template<typename Target> 620 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 621 protected: 622 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 623 MacroBuilder &Builder) const override { 624 // PS3 PPU defines. 625 Builder.defineMacro("__PPC__"); 626 Builder.defineMacro("__PPU__"); 627 Builder.defineMacro("__CELLOS_LV2__"); 628 Builder.defineMacro("__ELF__"); 629 Builder.defineMacro("__LP32__"); 630 Builder.defineMacro("_ARCH_PPC64"); 631 Builder.defineMacro("__powerpc64__"); 632 } 633 public: 634 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 635 : OSTargetInfo<Target>(Triple, Opts) { 636 this->LongWidth = this->LongAlign = 32; 637 this->PointerWidth = this->PointerAlign = 32; 638 this->IntMaxType = TargetInfo::SignedLongLong; 639 this->Int64Type = TargetInfo::SignedLongLong; 640 this->SizeType = TargetInfo::UnsignedInt; 641 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 642 } 643 }; 644 645 template <typename Target> 646 class PS4OSTargetInfo : public OSTargetInfo<Target> { 647 protected: 648 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 649 MacroBuilder &Builder) const override { 650 Builder.defineMacro("__FreeBSD__", "9"); 651 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 652 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 653 DefineStd(Builder, "unix", Opts); 654 Builder.defineMacro("__ELF__"); 655 Builder.defineMacro("__ORBIS__"); 656 } 657 public: 658 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 659 : OSTargetInfo<Target>(Triple, Opts) { 660 this->WCharType = this->UnsignedShort; 661 662 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 663 this->MaxTLSAlign = 256; 664 665 // On PS4, do not honor explicit bit field alignment, 666 // as in "__attribute__((aligned(2))) int b : 1;". 667 this->UseExplicitBitFieldAlignment = false; 668 669 switch (Triple.getArch()) { 670 default: 671 case llvm::Triple::x86_64: 672 this->MCountName = ".mcount"; 673 break; 674 } 675 } 676 }; 677 678 // Solaris target 679 template<typename Target> 680 class SolarisTargetInfo : public OSTargetInfo<Target> { 681 protected: 682 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 683 MacroBuilder &Builder) const override { 684 DefineStd(Builder, "sun", Opts); 685 DefineStd(Builder, "unix", Opts); 686 Builder.defineMacro("__ELF__"); 687 Builder.defineMacro("__svr4__"); 688 Builder.defineMacro("__SVR4"); 689 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 690 // newer, but to 500 for everything else. feature_test.h has a check to 691 // ensure that you are not using C99 with an old version of X/Open or C89 692 // with a new version. 693 if (Opts.C99) 694 Builder.defineMacro("_XOPEN_SOURCE", "600"); 695 else 696 Builder.defineMacro("_XOPEN_SOURCE", "500"); 697 if (Opts.CPlusPlus) 698 Builder.defineMacro("__C99FEATURES__"); 699 Builder.defineMacro("_LARGEFILE_SOURCE"); 700 Builder.defineMacro("_LARGEFILE64_SOURCE"); 701 Builder.defineMacro("__EXTENSIONS__"); 702 Builder.defineMacro("_REENTRANT"); 703 } 704 public: 705 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 706 : OSTargetInfo<Target>(Triple, Opts) { 707 this->WCharType = this->SignedInt; 708 // FIXME: WIntType should be SignedLong 709 } 710 }; 711 712 // Windows target 713 template<typename Target> 714 class WindowsTargetInfo : public OSTargetInfo<Target> { 715 protected: 716 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 717 MacroBuilder &Builder) const override { 718 Builder.defineMacro("_WIN32"); 719 } 720 void getVisualStudioDefines(const LangOptions &Opts, 721 MacroBuilder &Builder) const { 722 if (Opts.CPlusPlus) { 723 if (Opts.RTTIData) 724 Builder.defineMacro("_CPPRTTI"); 725 726 if (Opts.CXXExceptions) 727 Builder.defineMacro("_CPPUNWIND"); 728 } 729 730 if (Opts.Bool) 731 Builder.defineMacro("__BOOL_DEFINED"); 732 733 if (!Opts.CharIsSigned) 734 Builder.defineMacro("_CHAR_UNSIGNED"); 735 736 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 737 // but it works for now. 738 if (Opts.POSIXThreads) 739 Builder.defineMacro("_MT"); 740 741 if (Opts.MSCompatibilityVersion) { 742 Builder.defineMacro("_MSC_VER", 743 Twine(Opts.MSCompatibilityVersion / 100000)); 744 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 745 // FIXME We cannot encode the revision information into 32-bits 746 Builder.defineMacro("_MSC_BUILD", Twine(1)); 747 748 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 749 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 750 751 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 752 if (Opts.CPlusPlus1z) 753 Builder.defineMacro("_MSVC_LANG", "201403L"); 754 else if (Opts.CPlusPlus14) 755 Builder.defineMacro("_MSVC_LANG", "201402L"); 756 } 757 } 758 759 if (Opts.MicrosoftExt) { 760 Builder.defineMacro("_MSC_EXTENSIONS"); 761 762 if (Opts.CPlusPlus11) { 763 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 764 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 765 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 766 } 767 } 768 769 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 770 } 771 772 public: 773 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 774 : OSTargetInfo<Target>(Triple, Opts) {} 775 }; 776 777 template <typename Target> 778 class NaClTargetInfo : public OSTargetInfo<Target> { 779 protected: 780 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 781 MacroBuilder &Builder) const override { 782 if (Opts.POSIXThreads) 783 Builder.defineMacro("_REENTRANT"); 784 if (Opts.CPlusPlus) 785 Builder.defineMacro("_GNU_SOURCE"); 786 787 DefineStd(Builder, "unix", Opts); 788 Builder.defineMacro("__ELF__"); 789 Builder.defineMacro("__native_client__"); 790 } 791 792 public: 793 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 794 : OSTargetInfo<Target>(Triple, Opts) { 795 this->LongAlign = 32; 796 this->LongWidth = 32; 797 this->PointerAlign = 32; 798 this->PointerWidth = 32; 799 this->IntMaxType = TargetInfo::SignedLongLong; 800 this->Int64Type = TargetInfo::SignedLongLong; 801 this->DoubleAlign = 64; 802 this->LongDoubleWidth = 64; 803 this->LongDoubleAlign = 64; 804 this->LongLongWidth = 64; 805 this->LongLongAlign = 64; 806 this->SizeType = TargetInfo::UnsignedInt; 807 this->PtrDiffType = TargetInfo::SignedInt; 808 this->IntPtrType = TargetInfo::SignedInt; 809 // RegParmMax is inherited from the underlying architecture. 810 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 811 if (Triple.getArch() == llvm::Triple::arm) { 812 // Handled in ARM's setABI(). 813 } else if (Triple.getArch() == llvm::Triple::x86) { 814 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 815 } else if (Triple.getArch() == llvm::Triple::x86_64) { 816 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 817 } else if (Triple.getArch() == llvm::Triple::mipsel) { 818 // Handled on mips' setDataLayout. 819 } else { 820 assert(Triple.getArch() == llvm::Triple::le32); 821 this->resetDataLayout("e-p:32:32-i64:64"); 822 } 823 } 824 }; 825 826 // Fuchsia Target 827 template<typename Target> 828 class FuchsiaTargetInfo : public OSTargetInfo<Target> { 829 protected: 830 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 831 MacroBuilder &Builder) const override { 832 Builder.defineMacro("__Fuchsia__"); 833 Builder.defineMacro("__ELF__"); 834 if (Opts.POSIXThreads) 835 Builder.defineMacro("_REENTRANT"); 836 // Required by the libc++ locale support. 837 if (Opts.CPlusPlus) 838 Builder.defineMacro("_GNU_SOURCE"); 839 } 840 public: 841 FuchsiaTargetInfo(const llvm::Triple &Triple, 842 const TargetOptions &Opts) 843 : OSTargetInfo<Target>(Triple, Opts) { 844 this->MCountName = "__mcount"; 845 } 846 }; 847 848 // WebAssembly target 849 template <typename Target> 850 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 851 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 852 MacroBuilder &Builder) const final { 853 // A common platform macro. 854 if (Opts.POSIXThreads) 855 Builder.defineMacro("_REENTRANT"); 856 // Follow g++ convention and predefine _GNU_SOURCE for C++. 857 if (Opts.CPlusPlus) 858 Builder.defineMacro("_GNU_SOURCE"); 859 } 860 861 // As an optimization, group static init code together in a section. 862 const char *getStaticInitSectionSpecifier() const final { 863 return ".text.__startup"; 864 } 865 866 public: 867 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 868 const TargetOptions &Opts) 869 : OSTargetInfo<Target>(Triple, Opts) { 870 this->MCountName = "__mcount"; 871 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 872 } 873 }; 874 875 //===----------------------------------------------------------------------===// 876 // Specific target implementations. 877 //===----------------------------------------------------------------------===// 878 879 // PPC abstract base class 880 class PPCTargetInfo : public TargetInfo { 881 static const Builtin::Info BuiltinInfo[]; 882 static const char * const GCCRegNames[]; 883 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 884 std::string CPU; 885 886 // Target cpu features. 887 bool HasVSX; 888 bool HasP8Vector; 889 bool HasP8Crypto; 890 bool HasDirectMove; 891 bool HasQPX; 892 bool HasHTM; 893 bool HasBPERMD; 894 bool HasExtDiv; 895 bool HasP9Vector; 896 897 protected: 898 std::string ABI; 899 900 public: 901 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 902 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 903 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 904 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) { 905 SimdDefaultAlign = 128; 906 LongDoubleWidth = LongDoubleAlign = 128; 907 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 908 } 909 910 /// \brief Flags for architecture specific defines. 911 typedef enum { 912 ArchDefineNone = 0, 913 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 914 ArchDefinePpcgr = 1 << 1, 915 ArchDefinePpcsq = 1 << 2, 916 ArchDefine440 = 1 << 3, 917 ArchDefine603 = 1 << 4, 918 ArchDefine604 = 1 << 5, 919 ArchDefinePwr4 = 1 << 6, 920 ArchDefinePwr5 = 1 << 7, 921 ArchDefinePwr5x = 1 << 8, 922 ArchDefinePwr6 = 1 << 9, 923 ArchDefinePwr6x = 1 << 10, 924 ArchDefinePwr7 = 1 << 11, 925 ArchDefinePwr8 = 1 << 12, 926 ArchDefinePwr9 = 1 << 13, 927 ArchDefineA2 = 1 << 14, 928 ArchDefineA2q = 1 << 15 929 } ArchDefineTypes; 930 931 // Note: GCC recognizes the following additional cpus: 932 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 933 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 934 // titan, rs64. 935 bool setCPU(const std::string &Name) override { 936 bool CPUKnown = llvm::StringSwitch<bool>(Name) 937 .Case("generic", true) 938 .Case("440", true) 939 .Case("450", true) 940 .Case("601", true) 941 .Case("602", true) 942 .Case("603", true) 943 .Case("603e", true) 944 .Case("603ev", true) 945 .Case("604", true) 946 .Case("604e", true) 947 .Case("620", true) 948 .Case("630", true) 949 .Case("g3", true) 950 .Case("7400", true) 951 .Case("g4", true) 952 .Case("7450", true) 953 .Case("g4+", true) 954 .Case("750", true) 955 .Case("970", true) 956 .Case("g5", true) 957 .Case("a2", true) 958 .Case("a2q", true) 959 .Case("e500mc", true) 960 .Case("e5500", true) 961 .Case("power3", true) 962 .Case("pwr3", true) 963 .Case("power4", true) 964 .Case("pwr4", true) 965 .Case("power5", true) 966 .Case("pwr5", true) 967 .Case("power5x", true) 968 .Case("pwr5x", true) 969 .Case("power6", true) 970 .Case("pwr6", true) 971 .Case("power6x", true) 972 .Case("pwr6x", true) 973 .Case("power7", true) 974 .Case("pwr7", true) 975 .Case("power8", true) 976 .Case("pwr8", true) 977 .Case("power9", true) 978 .Case("pwr9", true) 979 .Case("powerpc", true) 980 .Case("ppc", true) 981 .Case("powerpc64", true) 982 .Case("ppc64", true) 983 .Case("powerpc64le", true) 984 .Case("ppc64le", true) 985 .Default(false); 986 987 if (CPUKnown) 988 CPU = Name; 989 990 return CPUKnown; 991 } 992 993 994 StringRef getABI() const override { return ABI; } 995 996 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 997 return llvm::makeArrayRef(BuiltinInfo, 998 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 999 } 1000 1001 bool isCLZForZeroUndef() const override { return false; } 1002 1003 void getTargetDefines(const LangOptions &Opts, 1004 MacroBuilder &Builder) const override; 1005 1006 bool 1007 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1008 StringRef CPU, 1009 const std::vector<std::string> &FeaturesVec) const override; 1010 1011 bool handleTargetFeatures(std::vector<std::string> &Features, 1012 DiagnosticsEngine &Diags) override; 1013 bool hasFeature(StringRef Feature) const override; 1014 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 1015 bool Enabled) const override; 1016 1017 ArrayRef<const char *> getGCCRegNames() const override; 1018 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 1019 bool validateAsmConstraint(const char *&Name, 1020 TargetInfo::ConstraintInfo &Info) const override { 1021 switch (*Name) { 1022 default: return false; 1023 case 'O': // Zero 1024 break; 1025 case 'b': // Base register 1026 case 'f': // Floating point register 1027 Info.setAllowsRegister(); 1028 break; 1029 // FIXME: The following are added to allow parsing. 1030 // I just took a guess at what the actions should be. 1031 // Also, is more specific checking needed? I.e. specific registers? 1032 case 'd': // Floating point register (containing 64-bit value) 1033 case 'v': // Altivec vector register 1034 Info.setAllowsRegister(); 1035 break; 1036 case 'w': 1037 switch (Name[1]) { 1038 case 'd':// VSX vector register to hold vector double data 1039 case 'f':// VSX vector register to hold vector float data 1040 case 's':// VSX vector register to hold scalar float data 1041 case 'a':// Any VSX register 1042 case 'c':// An individual CR bit 1043 break; 1044 default: 1045 return false; 1046 } 1047 Info.setAllowsRegister(); 1048 Name++; // Skip over 'w'. 1049 break; 1050 case 'h': // `MQ', `CTR', or `LINK' register 1051 case 'q': // `MQ' register 1052 case 'c': // `CTR' register 1053 case 'l': // `LINK' register 1054 case 'x': // `CR' register (condition register) number 0 1055 case 'y': // `CR' register (condition register) 1056 case 'z': // `XER[CA]' carry bit (part of the XER register) 1057 Info.setAllowsRegister(); 1058 break; 1059 case 'I': // Signed 16-bit constant 1060 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1061 // (use `L' instead for SImode constants) 1062 case 'K': // Unsigned 16-bit constant 1063 case 'L': // Signed 16-bit constant shifted left 16 bits 1064 case 'M': // Constant larger than 31 1065 case 'N': // Exact power of 2 1066 case 'P': // Constant whose negation is a signed 16-bit constant 1067 case 'G': // Floating point constant that can be loaded into a 1068 // register with one instruction per word 1069 case 'H': // Integer/Floating point constant that can be loaded 1070 // into a register using three instructions 1071 break; 1072 case 'm': // Memory operand. Note that on PowerPC targets, m can 1073 // include addresses that update the base register. It 1074 // is therefore only safe to use `m' in an asm statement 1075 // if that asm statement accesses the operand exactly once. 1076 // The asm statement must also use `%U<opno>' as a 1077 // placeholder for the "update" flag in the corresponding 1078 // load or store instruction. For example: 1079 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1080 // is correct but: 1081 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1082 // is not. Use es rather than m if you don't want the base 1083 // register to be updated. 1084 case 'e': 1085 if (Name[1] != 's') 1086 return false; 1087 // es: A "stable" memory operand; that is, one which does not 1088 // include any automodification of the base register. Unlike 1089 // `m', this constraint can be used in asm statements that 1090 // might access the operand several times, or that might not 1091 // access it at all. 1092 Info.setAllowsMemory(); 1093 Name++; // Skip over 'e'. 1094 break; 1095 case 'Q': // Memory operand that is an offset from a register (it is 1096 // usually better to use `m' or `es' in asm statements) 1097 case 'Z': // Memory operand that is an indexed or indirect from a 1098 // register (it is usually better to use `m' or `es' in 1099 // asm statements) 1100 Info.setAllowsMemory(); 1101 Info.setAllowsRegister(); 1102 break; 1103 case 'R': // AIX TOC entry 1104 case 'a': // Address operand that is an indexed or indirect from a 1105 // register (`p' is preferable for asm statements) 1106 case 'S': // Constant suitable as a 64-bit mask operand 1107 case 'T': // Constant suitable as a 32-bit mask operand 1108 case 'U': // System V Release 4 small data area reference 1109 case 't': // AND masks that can be performed by two rldic{l, r} 1110 // instructions 1111 case 'W': // Vector constant that does not require memory 1112 case 'j': // Vector constant that is all zeros. 1113 break; 1114 // End FIXME. 1115 } 1116 return true; 1117 } 1118 std::string convertConstraint(const char *&Constraint) const override { 1119 std::string R; 1120 switch (*Constraint) { 1121 case 'e': 1122 case 'w': 1123 // Two-character constraint; add "^" hint for later parsing. 1124 R = std::string("^") + std::string(Constraint, 2); 1125 Constraint++; 1126 break; 1127 default: 1128 return TargetInfo::convertConstraint(Constraint); 1129 } 1130 return R; 1131 } 1132 const char *getClobbers() const override { 1133 return ""; 1134 } 1135 int getEHDataRegisterNumber(unsigned RegNo) const override { 1136 if (RegNo == 0) return 3; 1137 if (RegNo == 1) return 4; 1138 return -1; 1139 } 1140 1141 bool hasSjLjLowering() const override { 1142 return true; 1143 } 1144 1145 bool useFloat128ManglingForLongDouble() const override { 1146 return LongDoubleWidth == 128 && 1147 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1148 getTriple().isOSBinFormatELF(); 1149 } 1150 }; 1151 1152 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1153 #define BUILTIN(ID, TYPE, ATTRS) \ 1154 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1155 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1156 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1157 #include "clang/Basic/BuiltinsPPC.def" 1158 }; 1159 1160 /// handleTargetFeatures - Perform initialization based on the user 1161 /// configured set of features. 1162 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1163 DiagnosticsEngine &Diags) { 1164 for (const auto &Feature : Features) { 1165 if (Feature == "+vsx") { 1166 HasVSX = true; 1167 } else if (Feature == "+bpermd") { 1168 HasBPERMD = true; 1169 } else if (Feature == "+extdiv") { 1170 HasExtDiv = true; 1171 } else if (Feature == "+power8-vector") { 1172 HasP8Vector = true; 1173 } else if (Feature == "+crypto") { 1174 HasP8Crypto = true; 1175 } else if (Feature == "+direct-move") { 1176 HasDirectMove = true; 1177 } else if (Feature == "+qpx") { 1178 HasQPX = true; 1179 } else if (Feature == "+htm") { 1180 HasHTM = true; 1181 } else if (Feature == "+float128") { 1182 HasFloat128 = true; 1183 } else if (Feature == "+power9-vector") { 1184 HasP9Vector = true; 1185 } 1186 // TODO: Finish this list and add an assert that we've handled them 1187 // all. 1188 } 1189 1190 return true; 1191 } 1192 1193 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1194 /// #defines that are not tied to a specific subtarget. 1195 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1196 MacroBuilder &Builder) const { 1197 // Target identification. 1198 Builder.defineMacro("__ppc__"); 1199 Builder.defineMacro("__PPC__"); 1200 Builder.defineMacro("_ARCH_PPC"); 1201 Builder.defineMacro("__powerpc__"); 1202 Builder.defineMacro("__POWERPC__"); 1203 if (PointerWidth == 64) { 1204 Builder.defineMacro("_ARCH_PPC64"); 1205 Builder.defineMacro("__powerpc64__"); 1206 Builder.defineMacro("__ppc64__"); 1207 Builder.defineMacro("__PPC64__"); 1208 } 1209 1210 // Target properties. 1211 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1212 Builder.defineMacro("_LITTLE_ENDIAN"); 1213 } else { 1214 if (getTriple().getOS() != llvm::Triple::NetBSD && 1215 getTriple().getOS() != llvm::Triple::OpenBSD) 1216 Builder.defineMacro("_BIG_ENDIAN"); 1217 } 1218 1219 // ABI options. 1220 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1221 Builder.defineMacro("_CALL_ELF", "1"); 1222 if (ABI == "elfv2") 1223 Builder.defineMacro("_CALL_ELF", "2"); 1224 1225 // Subtarget options. 1226 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1227 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1228 1229 // FIXME: Should be controlled by command line option. 1230 if (LongDoubleWidth == 128) 1231 Builder.defineMacro("__LONG_DOUBLE_128__"); 1232 1233 if (Opts.AltiVec) { 1234 Builder.defineMacro("__VEC__", "10206"); 1235 Builder.defineMacro("__ALTIVEC__"); 1236 } 1237 1238 // CPU identification. 1239 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1240 .Case("440", ArchDefineName) 1241 .Case("450", ArchDefineName | ArchDefine440) 1242 .Case("601", ArchDefineName) 1243 .Case("602", ArchDefineName | ArchDefinePpcgr) 1244 .Case("603", ArchDefineName | ArchDefinePpcgr) 1245 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1246 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1247 .Case("604", ArchDefineName | ArchDefinePpcgr) 1248 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1249 .Case("620", ArchDefineName | ArchDefinePpcgr) 1250 .Case("630", ArchDefineName | ArchDefinePpcgr) 1251 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1252 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1253 .Case("750", ArchDefineName | ArchDefinePpcgr) 1254 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1255 | ArchDefinePpcsq) 1256 .Case("a2", ArchDefineA2) 1257 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1258 .Case("pwr3", ArchDefinePpcgr) 1259 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1260 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1261 | ArchDefinePpcsq) 1262 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1263 | ArchDefinePpcgr | ArchDefinePpcsq) 1264 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1265 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1266 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1267 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1268 | ArchDefinePpcsq) 1269 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1270 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1271 | ArchDefinePpcgr | ArchDefinePpcsq) 1272 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1273 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1274 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1275 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 1276 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1277 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1278 | ArchDefinePpcsq) 1279 .Case("power3", ArchDefinePpcgr) 1280 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1281 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1282 | ArchDefinePpcsq) 1283 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1284 | ArchDefinePpcgr | ArchDefinePpcsq) 1285 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1286 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1287 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1288 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1289 | ArchDefinePpcsq) 1290 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1291 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1292 | ArchDefinePpcgr | ArchDefinePpcsq) 1293 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1294 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1295 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1296 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 1297 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1298 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1299 | ArchDefinePpcsq) 1300 .Default(ArchDefineNone); 1301 1302 if (defs & ArchDefineName) 1303 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1304 if (defs & ArchDefinePpcgr) 1305 Builder.defineMacro("_ARCH_PPCGR"); 1306 if (defs & ArchDefinePpcsq) 1307 Builder.defineMacro("_ARCH_PPCSQ"); 1308 if (defs & ArchDefine440) 1309 Builder.defineMacro("_ARCH_440"); 1310 if (defs & ArchDefine603) 1311 Builder.defineMacro("_ARCH_603"); 1312 if (defs & ArchDefine604) 1313 Builder.defineMacro("_ARCH_604"); 1314 if (defs & ArchDefinePwr4) 1315 Builder.defineMacro("_ARCH_PWR4"); 1316 if (defs & ArchDefinePwr5) 1317 Builder.defineMacro("_ARCH_PWR5"); 1318 if (defs & ArchDefinePwr5x) 1319 Builder.defineMacro("_ARCH_PWR5X"); 1320 if (defs & ArchDefinePwr6) 1321 Builder.defineMacro("_ARCH_PWR6"); 1322 if (defs & ArchDefinePwr6x) 1323 Builder.defineMacro("_ARCH_PWR6X"); 1324 if (defs & ArchDefinePwr7) 1325 Builder.defineMacro("_ARCH_PWR7"); 1326 if (defs & ArchDefinePwr8) 1327 Builder.defineMacro("_ARCH_PWR8"); 1328 if (defs & ArchDefinePwr9) 1329 Builder.defineMacro("_ARCH_PWR9"); 1330 if (defs & ArchDefineA2) 1331 Builder.defineMacro("_ARCH_A2"); 1332 if (defs & ArchDefineA2q) { 1333 Builder.defineMacro("_ARCH_A2Q"); 1334 Builder.defineMacro("_ARCH_QP"); 1335 } 1336 1337 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1338 Builder.defineMacro("__bg__"); 1339 Builder.defineMacro("__THW_BLUEGENE__"); 1340 Builder.defineMacro("__bgq__"); 1341 Builder.defineMacro("__TOS_BGQ__"); 1342 } 1343 1344 if (HasVSX) 1345 Builder.defineMacro("__VSX__"); 1346 if (HasP8Vector) 1347 Builder.defineMacro("__POWER8_VECTOR__"); 1348 if (HasP8Crypto) 1349 Builder.defineMacro("__CRYPTO__"); 1350 if (HasHTM) 1351 Builder.defineMacro("__HTM__"); 1352 if (HasFloat128) 1353 Builder.defineMacro("__FLOAT128__"); 1354 if (HasP9Vector) 1355 Builder.defineMacro("__POWER9_VECTOR__"); 1356 1357 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1358 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1359 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1360 if (PointerWidth == 64) 1361 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1362 1363 // FIXME: The following are not yet generated here by Clang, but are 1364 // generated by GCC: 1365 // 1366 // _SOFT_FLOAT_ 1367 // __RECIP_PRECISION__ 1368 // __APPLE_ALTIVEC__ 1369 // __RECIP__ 1370 // __RECIPF__ 1371 // __RSQRTE__ 1372 // __RSQRTEF__ 1373 // _SOFT_DOUBLE_ 1374 // __NO_LWSYNC__ 1375 // __HAVE_BSWAP__ 1376 // __LONGDOUBLE128 1377 // __CMODEL_MEDIUM__ 1378 // __CMODEL_LARGE__ 1379 // _CALL_SYSV 1380 // _CALL_DARWIN 1381 // __NO_FPRS__ 1382 } 1383 1384 // Handle explicit options being passed to the compiler here: if we've 1385 // explicitly turned off vsx and turned on any of: 1386 // - power8-vector 1387 // - direct-move 1388 // - float128 1389 // - power9-vector 1390 // then go ahead and error since the customer has expressed an incompatible 1391 // set of options. 1392 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1393 const std::vector<std::string> &FeaturesVec) { 1394 1395 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1396 FeaturesVec.end()) { 1397 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1398 FeaturesVec.end()) { 1399 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1400 << "-mno-vsx"; 1401 return false; 1402 } 1403 1404 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1405 FeaturesVec.end()) { 1406 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1407 << "-mno-vsx"; 1408 return false; 1409 } 1410 1411 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1412 FeaturesVec.end()) { 1413 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1414 << "-mno-vsx"; 1415 return false; 1416 } 1417 1418 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") != 1419 FeaturesVec.end()) { 1420 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector" 1421 << "-mno-vsx"; 1422 return false; 1423 } 1424 } 1425 1426 return true; 1427 } 1428 1429 bool PPCTargetInfo::initFeatureMap( 1430 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1431 const std::vector<std::string> &FeaturesVec) const { 1432 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1433 .Case("7400", true) 1434 .Case("g4", true) 1435 .Case("7450", true) 1436 .Case("g4+", true) 1437 .Case("970", true) 1438 .Case("g5", true) 1439 .Case("pwr6", true) 1440 .Case("pwr7", true) 1441 .Case("pwr8", true) 1442 .Case("pwr9", true) 1443 .Case("ppc64", true) 1444 .Case("ppc64le", true) 1445 .Default(false); 1446 1447 Features["qpx"] = (CPU == "a2q"); 1448 Features["power9-vector"] = (CPU == "pwr9"); 1449 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1450 .Case("ppc64le", true) 1451 .Case("pwr9", true) 1452 .Case("pwr8", true) 1453 .Default(false); 1454 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1455 .Case("ppc64le", true) 1456 .Case("pwr9", true) 1457 .Case("pwr8", true) 1458 .Default(false); 1459 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1460 .Case("ppc64le", true) 1461 .Case("pwr9", true) 1462 .Case("pwr8", true) 1463 .Case("pwr7", true) 1464 .Default(false); 1465 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1466 .Case("ppc64le", true) 1467 .Case("pwr9", true) 1468 .Case("pwr8", true) 1469 .Case("pwr7", true) 1470 .Default(false); 1471 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1472 .Case("ppc64le", true) 1473 .Case("pwr9", true) 1474 .Case("pwr8", true) 1475 .Default(false); 1476 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1477 .Case("ppc64le", true) 1478 .Case("pwr9", true) 1479 .Case("pwr8", true) 1480 .Case("pwr7", true) 1481 .Default(false); 1482 1483 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1484 return false; 1485 1486 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1487 } 1488 1489 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1490 return llvm::StringSwitch<bool>(Feature) 1491 .Case("powerpc", true) 1492 .Case("vsx", HasVSX) 1493 .Case("power8-vector", HasP8Vector) 1494 .Case("crypto", HasP8Crypto) 1495 .Case("direct-move", HasDirectMove) 1496 .Case("qpx", HasQPX) 1497 .Case("htm", HasHTM) 1498 .Case("bpermd", HasBPERMD) 1499 .Case("extdiv", HasExtDiv) 1500 .Case("float128", HasFloat128) 1501 .Case("power9-vector", HasP9Vector) 1502 .Default(false); 1503 } 1504 1505 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1506 StringRef Name, bool Enabled) const { 1507 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1508 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1509 // incompatible options. 1510 if (Enabled) { 1511 if (Name == "direct-move" || 1512 Name == "power8-vector" || 1513 Name == "float128" || 1514 Name == "power9-vector") { 1515 // power9-vector is really a superset of power8-vector so encode that. 1516 Features[Name] = Features["vsx"] = true; 1517 if (Name == "power9-vector") 1518 Features["power8-vector"] = true; 1519 } else { 1520 Features[Name] = true; 1521 } 1522 } else { 1523 if (Name == "vsx") { 1524 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1525 Features["float128"] = Features["power9-vector"] = false; 1526 } else { 1527 Features[Name] = false; 1528 } 1529 } 1530 } 1531 1532 const char * const PPCTargetInfo::GCCRegNames[] = { 1533 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1534 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1535 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1536 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1537 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1538 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1539 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1540 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1541 "mq", "lr", "ctr", "ap", 1542 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1543 "xer", 1544 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1545 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1546 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1547 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1548 "vrsave", "vscr", 1549 "spe_acc", "spefscr", 1550 "sfp" 1551 }; 1552 1553 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1554 return llvm::makeArrayRef(GCCRegNames); 1555 } 1556 1557 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1558 // While some of these aliases do map to different registers 1559 // they still share the same register name. 1560 { { "0" }, "r0" }, 1561 { { "1"}, "r1" }, 1562 { { "2" }, "r2" }, 1563 { { "3" }, "r3" }, 1564 { { "4" }, "r4" }, 1565 { { "5" }, "r5" }, 1566 { { "6" }, "r6" }, 1567 { { "7" }, "r7" }, 1568 { { "8" }, "r8" }, 1569 { { "9" }, "r9" }, 1570 { { "10" }, "r10" }, 1571 { { "11" }, "r11" }, 1572 { { "12" }, "r12" }, 1573 { { "13" }, "r13" }, 1574 { { "14" }, "r14" }, 1575 { { "15" }, "r15" }, 1576 { { "16" }, "r16" }, 1577 { { "17" }, "r17" }, 1578 { { "18" }, "r18" }, 1579 { { "19" }, "r19" }, 1580 { { "20" }, "r20" }, 1581 { { "21" }, "r21" }, 1582 { { "22" }, "r22" }, 1583 { { "23" }, "r23" }, 1584 { { "24" }, "r24" }, 1585 { { "25" }, "r25" }, 1586 { { "26" }, "r26" }, 1587 { { "27" }, "r27" }, 1588 { { "28" }, "r28" }, 1589 { { "29" }, "r29" }, 1590 { { "30" }, "r30" }, 1591 { { "31" }, "r31" }, 1592 { { "fr0" }, "f0" }, 1593 { { "fr1" }, "f1" }, 1594 { { "fr2" }, "f2" }, 1595 { { "fr3" }, "f3" }, 1596 { { "fr4" }, "f4" }, 1597 { { "fr5" }, "f5" }, 1598 { { "fr6" }, "f6" }, 1599 { { "fr7" }, "f7" }, 1600 { { "fr8" }, "f8" }, 1601 { { "fr9" }, "f9" }, 1602 { { "fr10" }, "f10" }, 1603 { { "fr11" }, "f11" }, 1604 { { "fr12" }, "f12" }, 1605 { { "fr13" }, "f13" }, 1606 { { "fr14" }, "f14" }, 1607 { { "fr15" }, "f15" }, 1608 { { "fr16" }, "f16" }, 1609 { { "fr17" }, "f17" }, 1610 { { "fr18" }, "f18" }, 1611 { { "fr19" }, "f19" }, 1612 { { "fr20" }, "f20" }, 1613 { { "fr21" }, "f21" }, 1614 { { "fr22" }, "f22" }, 1615 { { "fr23" }, "f23" }, 1616 { { "fr24" }, "f24" }, 1617 { { "fr25" }, "f25" }, 1618 { { "fr26" }, "f26" }, 1619 { { "fr27" }, "f27" }, 1620 { { "fr28" }, "f28" }, 1621 { { "fr29" }, "f29" }, 1622 { { "fr30" }, "f30" }, 1623 { { "fr31" }, "f31" }, 1624 { { "cc" }, "cr0" }, 1625 }; 1626 1627 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1628 return llvm::makeArrayRef(GCCRegAliases); 1629 } 1630 1631 class PPC32TargetInfo : public PPCTargetInfo { 1632 public: 1633 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1634 : PPCTargetInfo(Triple, Opts) { 1635 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1636 1637 switch (getTriple().getOS()) { 1638 case llvm::Triple::Linux: 1639 case llvm::Triple::FreeBSD: 1640 case llvm::Triple::NetBSD: 1641 SizeType = UnsignedInt; 1642 PtrDiffType = SignedInt; 1643 IntPtrType = SignedInt; 1644 break; 1645 default: 1646 break; 1647 } 1648 1649 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1650 LongDoubleWidth = LongDoubleAlign = 64; 1651 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1652 } 1653 1654 // PPC32 supports atomics up to 4 bytes. 1655 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1656 } 1657 1658 BuiltinVaListKind getBuiltinVaListKind() const override { 1659 // This is the ELF definition, and is overridden by the Darwin sub-target 1660 return TargetInfo::PowerABIBuiltinVaList; 1661 } 1662 }; 1663 1664 // Note: ABI differences may eventually require us to have a separate 1665 // TargetInfo for little endian. 1666 class PPC64TargetInfo : public PPCTargetInfo { 1667 public: 1668 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1669 : PPCTargetInfo(Triple, Opts) { 1670 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1671 IntMaxType = SignedLong; 1672 Int64Type = SignedLong; 1673 1674 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1675 resetDataLayout("e-m:e-i64:64-n32:64"); 1676 ABI = "elfv2"; 1677 } else { 1678 resetDataLayout("E-m:e-i64:64-n32:64"); 1679 ABI = "elfv1"; 1680 } 1681 1682 switch (getTriple().getOS()) { 1683 case llvm::Triple::FreeBSD: 1684 LongDoubleWidth = LongDoubleAlign = 64; 1685 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1686 break; 1687 case llvm::Triple::NetBSD: 1688 IntMaxType = SignedLongLong; 1689 Int64Type = SignedLongLong; 1690 break; 1691 default: 1692 break; 1693 } 1694 1695 // PPC64 supports atomics up to 8 bytes. 1696 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1697 } 1698 BuiltinVaListKind getBuiltinVaListKind() const override { 1699 return TargetInfo::CharPtrBuiltinVaList; 1700 } 1701 // PPC64 Linux-specific ABI options. 1702 bool setABI(const std::string &Name) override { 1703 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1704 ABI = Name; 1705 return true; 1706 } 1707 return false; 1708 } 1709 }; 1710 1711 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1712 public: 1713 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1714 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1715 HasAlignMac68kSupport = true; 1716 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1717 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1718 LongLongAlign = 32; 1719 SuitableAlign = 128; 1720 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1721 } 1722 BuiltinVaListKind getBuiltinVaListKind() const override { 1723 return TargetInfo::CharPtrBuiltinVaList; 1724 } 1725 }; 1726 1727 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1728 public: 1729 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1730 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1731 HasAlignMac68kSupport = true; 1732 SuitableAlign = 128; 1733 resetDataLayout("E-m:o-i64:64-n32:64"); 1734 } 1735 }; 1736 1737 static const unsigned NVPTXAddrSpaceMap[] = { 1738 1, // opencl_global 1739 3, // opencl_local 1740 4, // opencl_constant 1741 // FIXME: generic has to be added to the target 1742 0, // opencl_generic 1743 1, // cuda_device 1744 4, // cuda_constant 1745 3, // cuda_shared 1746 }; 1747 1748 class NVPTXTargetInfo : public TargetInfo { 1749 static const char *const GCCRegNames[]; 1750 static const Builtin::Info BuiltinInfo[]; 1751 CudaArch GPU; 1752 1753 public: 1754 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1755 : TargetInfo(Triple) { 1756 TLSSupported = false; 1757 LongWidth = LongAlign = 64; 1758 AddrSpaceMap = &NVPTXAddrSpaceMap; 1759 UseAddrSpaceMapMangling = true; 1760 // Define available target features 1761 // These must be defined in sorted order! 1762 NoAsmVariants = true; 1763 GPU = CudaArch::SM_20; 1764 1765 // If possible, get a TargetInfo for our host triple, so we can match its 1766 // types. 1767 llvm::Triple HostTriple(Opts.HostTriple); 1768 if (HostTriple.isNVPTX()) 1769 return; 1770 std::unique_ptr<TargetInfo> HostTarget( 1771 AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1772 if (!HostTarget) { 1773 return; 1774 } 1775 1776 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1777 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1778 BoolWidth = HostTarget->getBoolWidth(); 1779 BoolAlign = HostTarget->getBoolAlign(); 1780 IntWidth = HostTarget->getIntWidth(); 1781 IntAlign = HostTarget->getIntAlign(); 1782 HalfWidth = HostTarget->getHalfWidth(); 1783 HalfAlign = HostTarget->getHalfAlign(); 1784 FloatWidth = HostTarget->getFloatWidth(); 1785 FloatAlign = HostTarget->getFloatAlign(); 1786 DoubleWidth = HostTarget->getDoubleWidth(); 1787 DoubleAlign = HostTarget->getDoubleAlign(); 1788 LongWidth = HostTarget->getLongWidth(); 1789 LongAlign = HostTarget->getLongAlign(); 1790 LongLongWidth = HostTarget->getLongLongWidth(); 1791 LongLongAlign = HostTarget->getLongLongAlign(); 1792 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1793 NewAlign = HostTarget->getNewAlign(); 1794 DefaultAlignForAttributeAligned = 1795 HostTarget->getDefaultAlignForAttributeAligned(); 1796 SizeType = HostTarget->getSizeType(); 1797 IntMaxType = HostTarget->getIntMaxType(); 1798 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1799 IntPtrType = HostTarget->getIntPtrType(); 1800 WCharType = HostTarget->getWCharType(); 1801 WIntType = HostTarget->getWIntType(); 1802 Char16Type = HostTarget->getChar16Type(); 1803 Char32Type = HostTarget->getChar32Type(); 1804 Int64Type = HostTarget->getInt64Type(); 1805 SigAtomicType = HostTarget->getSigAtomicType(); 1806 ProcessIDType = HostTarget->getProcessIDType(); 1807 1808 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1809 UseZeroLengthBitfieldAlignment = 1810 HostTarget->useZeroLengthBitfieldAlignment(); 1811 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1812 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1813 1814 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and 1815 // we need those macros to be identical on host and device, because (among 1816 // other things) they affect which standard library classes are defined, and 1817 // we need all classes to be defined on both the host and device. 1818 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth(); 1819 1820 // Properties intentionally not copied from host: 1821 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1822 // host/device boundary. 1823 // - SuitableAlign: Not visible across the host/device boundary, and may 1824 // correctly be different on host/device, e.g. if host has wider vector 1825 // types than device. 1826 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1827 // as its double type, but that's not necessarily true on the host. 1828 // TODO: nvcc emits a warning when using long double on device; we should 1829 // do the same. 1830 } 1831 void getTargetDefines(const LangOptions &Opts, 1832 MacroBuilder &Builder) const override { 1833 Builder.defineMacro("__PTX__"); 1834 Builder.defineMacro("__NVPTX__"); 1835 if (Opts.CUDAIsDevice) { 1836 // Set __CUDA_ARCH__ for the GPU specified. 1837 std::string CUDAArchCode = [this] { 1838 switch (GPU) { 1839 case CudaArch::UNKNOWN: 1840 assert(false && "No GPU arch when compiling CUDA device code."); 1841 return ""; 1842 case CudaArch::SM_20: 1843 return "200"; 1844 case CudaArch::SM_21: 1845 return "210"; 1846 case CudaArch::SM_30: 1847 return "300"; 1848 case CudaArch::SM_32: 1849 return "320"; 1850 case CudaArch::SM_35: 1851 return "350"; 1852 case CudaArch::SM_37: 1853 return "370"; 1854 case CudaArch::SM_50: 1855 return "500"; 1856 case CudaArch::SM_52: 1857 return "520"; 1858 case CudaArch::SM_53: 1859 return "530"; 1860 case CudaArch::SM_60: 1861 return "600"; 1862 case CudaArch::SM_61: 1863 return "610"; 1864 case CudaArch::SM_62: 1865 return "620"; 1866 } 1867 llvm_unreachable("unhandled CudaArch"); 1868 }(); 1869 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1870 } 1871 } 1872 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1873 return llvm::makeArrayRef(BuiltinInfo, 1874 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1875 } 1876 bool 1877 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1878 StringRef CPU, 1879 const std::vector<std::string> &FeaturesVec) const override { 1880 Features["satom"] = GPU >= CudaArch::SM_60; 1881 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1882 } 1883 1884 bool hasFeature(StringRef Feature) const override { 1885 return llvm::StringSwitch<bool>(Feature) 1886 .Cases("ptx", "nvptx", true) 1887 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope. 1888 .Default(false); 1889 } 1890 1891 ArrayRef<const char *> getGCCRegNames() const override; 1892 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1893 // No aliases. 1894 return None; 1895 } 1896 bool validateAsmConstraint(const char *&Name, 1897 TargetInfo::ConstraintInfo &Info) const override { 1898 switch (*Name) { 1899 default: 1900 return false; 1901 case 'c': 1902 case 'h': 1903 case 'r': 1904 case 'l': 1905 case 'f': 1906 case 'd': 1907 Info.setAllowsRegister(); 1908 return true; 1909 } 1910 } 1911 const char *getClobbers() const override { 1912 // FIXME: Is this really right? 1913 return ""; 1914 } 1915 BuiltinVaListKind getBuiltinVaListKind() const override { 1916 // FIXME: implement 1917 return TargetInfo::CharPtrBuiltinVaList; 1918 } 1919 bool setCPU(const std::string &Name) override { 1920 GPU = StringToCudaArch(Name); 1921 return GPU != CudaArch::UNKNOWN; 1922 } 1923 void setSupportedOpenCLOpts() override { 1924 auto &Opts = getSupportedOpenCLOpts(); 1925 Opts.cl_clang_storage_class_specifiers = 1; 1926 Opts.cl_khr_gl_sharing = 1; 1927 Opts.cl_khr_icd = 1; 1928 1929 Opts.cl_khr_fp64 = 1; 1930 Opts.cl_khr_byte_addressable_store = 1; 1931 Opts.cl_khr_global_int32_base_atomics = 1; 1932 Opts.cl_khr_global_int32_extended_atomics = 1; 1933 Opts.cl_khr_local_int32_base_atomics = 1; 1934 Opts.cl_khr_local_int32_extended_atomics = 1; 1935 } 1936 }; 1937 1938 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1939 #define BUILTIN(ID, TYPE, ATTRS) \ 1940 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1941 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1942 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1943 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 1944 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 1945 #include "clang/Basic/BuiltinsNVPTX.def" 1946 }; 1947 1948 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1949 1950 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1951 return llvm::makeArrayRef(GCCRegNames); 1952 } 1953 1954 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1955 public: 1956 NVPTX32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1957 : NVPTXTargetInfo(Triple, Opts) { 1958 LongWidth = LongAlign = 32; 1959 PointerWidth = PointerAlign = 32; 1960 SizeType = TargetInfo::UnsignedInt; 1961 PtrDiffType = TargetInfo::SignedInt; 1962 IntPtrType = TargetInfo::SignedInt; 1963 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1964 } 1965 }; 1966 1967 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1968 public: 1969 NVPTX64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1970 : NVPTXTargetInfo(Triple, Opts) { 1971 PointerWidth = PointerAlign = 64; 1972 SizeType = TargetInfo::UnsignedLong; 1973 PtrDiffType = TargetInfo::SignedLong; 1974 IntPtrType = TargetInfo::SignedLong; 1975 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1976 } 1977 }; 1978 1979 static const unsigned AMDGPUAddrSpaceMap[] = { 1980 1, // opencl_global 1981 3, // opencl_local 1982 2, // opencl_constant 1983 4, // opencl_generic 1984 1, // cuda_device 1985 2, // cuda_constant 1986 3 // cuda_shared 1987 }; 1988 1989 // If you edit the description strings, make sure you update 1990 // getPointerWidthV(). 1991 1992 static const char *const DataLayoutStringR600 = 1993 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1994 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1995 1996 static const char *const DataLayoutStringSI = 1997 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 1998 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1999 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2000 2001 class AMDGPUTargetInfo final : public TargetInfo { 2002 static const Builtin::Info BuiltinInfo[]; 2003 static const char * const GCCRegNames[]; 2004 2005 /// \brief The GPU profiles supported by the AMDGPU target. 2006 enum GPUKind { 2007 GK_NONE, 2008 GK_R600, 2009 GK_R600_DOUBLE_OPS, 2010 GK_R700, 2011 GK_R700_DOUBLE_OPS, 2012 GK_EVERGREEN, 2013 GK_EVERGREEN_DOUBLE_OPS, 2014 GK_NORTHERN_ISLANDS, 2015 GK_CAYMAN, 2016 GK_GFX6, 2017 GK_GFX7, 2018 GK_GFX8 2019 } GPU; 2020 2021 bool hasFP64:1; 2022 bool hasFMAF:1; 2023 bool hasLDEXPF:1; 2024 bool hasFullSpeedFP32Denorms:1; 2025 2026 static bool isAMDGCN(const llvm::Triple &TT) { 2027 return TT.getArch() == llvm::Triple::amdgcn; 2028 } 2029 2030 public: 2031 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 2032 : TargetInfo(Triple) , 2033 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600), 2034 hasFP64(false), 2035 hasFMAF(false), 2036 hasLDEXPF(false), 2037 hasFullSpeedFP32Denorms(false){ 2038 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2039 hasFP64 = true; 2040 hasFMAF = true; 2041 hasLDEXPF = true; 2042 } 2043 2044 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 2045 DataLayoutStringSI : DataLayoutStringR600); 2046 2047 AddrSpaceMap = &AMDGPUAddrSpaceMap; 2048 UseAddrSpaceMapMangling = true; 2049 } 2050 2051 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 2052 if (GPU <= GK_CAYMAN) 2053 return 32; 2054 2055 switch(AddrSpace) { 2056 default: 2057 return 64; 2058 case 0: 2059 case 3: 2060 case 5: 2061 return 32; 2062 } 2063 } 2064 2065 uint64_t getMaxPointerWidth() const override { 2066 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2067 } 2068 2069 const char * getClobbers() const override { 2070 return ""; 2071 } 2072 2073 ArrayRef<const char *> getGCCRegNames() const override; 2074 2075 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2076 return None; 2077 } 2078 2079 bool validateAsmConstraint(const char *&Name, 2080 TargetInfo::ConstraintInfo &Info) const override { 2081 switch (*Name) { 2082 default: break; 2083 case 'v': // vgpr 2084 case 's': // sgpr 2085 Info.setAllowsRegister(); 2086 return true; 2087 } 2088 return false; 2089 } 2090 2091 bool initFeatureMap(llvm::StringMap<bool> &Features, 2092 DiagnosticsEngine &Diags, StringRef CPU, 2093 const std::vector<std::string> &FeatureVec) const override; 2094 2095 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2096 TargetOptions &TargetOpts) const override { 2097 bool hasFP32Denormals = false; 2098 bool hasFP64Denormals = false; 2099 for (auto &I : TargetOpts.FeaturesAsWritten) { 2100 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2101 hasFP32Denormals = true; 2102 if (I == "+fp64-denormals" || I == "-fp64-denormals") 2103 hasFP64Denormals = true; 2104 } 2105 if (!hasFP32Denormals) 2106 TargetOpts.Features.push_back((Twine(hasFullSpeedFP32Denorms && 2107 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str()); 2108 // Always do not flush fp64 denorms. 2109 if (!hasFP64Denormals && hasFP64) 2110 TargetOpts.Features.push_back("+fp64-denormals"); 2111 } 2112 2113 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2114 return llvm::makeArrayRef(BuiltinInfo, 2115 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2116 } 2117 2118 void getTargetDefines(const LangOptions &Opts, 2119 MacroBuilder &Builder) const override { 2120 if (getTriple().getArch() == llvm::Triple::amdgcn) 2121 Builder.defineMacro("__AMDGCN__"); 2122 else 2123 Builder.defineMacro("__R600__"); 2124 2125 if (hasFMAF) 2126 Builder.defineMacro("__HAS_FMAF__"); 2127 if (hasLDEXPF) 2128 Builder.defineMacro("__HAS_LDEXPF__"); 2129 if (hasFP64) 2130 Builder.defineMacro("__HAS_FP64__"); 2131 } 2132 2133 BuiltinVaListKind getBuiltinVaListKind() const override { 2134 return TargetInfo::CharPtrBuiltinVaList; 2135 } 2136 2137 static GPUKind parseR600Name(StringRef Name) { 2138 return llvm::StringSwitch<GPUKind>(Name) 2139 .Case("r600" , GK_R600) 2140 .Case("rv610", GK_R600) 2141 .Case("rv620", GK_R600) 2142 .Case("rv630", GK_R600) 2143 .Case("rv635", GK_R600) 2144 .Case("rs780", GK_R600) 2145 .Case("rs880", GK_R600) 2146 .Case("rv670", GK_R600_DOUBLE_OPS) 2147 .Case("rv710", GK_R700) 2148 .Case("rv730", GK_R700) 2149 .Case("rv740", GK_R700_DOUBLE_OPS) 2150 .Case("rv770", GK_R700_DOUBLE_OPS) 2151 .Case("palm", GK_EVERGREEN) 2152 .Case("cedar", GK_EVERGREEN) 2153 .Case("sumo", GK_EVERGREEN) 2154 .Case("sumo2", GK_EVERGREEN) 2155 .Case("redwood", GK_EVERGREEN) 2156 .Case("juniper", GK_EVERGREEN) 2157 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2158 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2159 .Case("barts", GK_NORTHERN_ISLANDS) 2160 .Case("turks", GK_NORTHERN_ISLANDS) 2161 .Case("caicos", GK_NORTHERN_ISLANDS) 2162 .Case("cayman", GK_CAYMAN) 2163 .Case("aruba", GK_CAYMAN) 2164 .Default(GK_NONE); 2165 } 2166 2167 static GPUKind parseAMDGCNName(StringRef Name) { 2168 return llvm::StringSwitch<GPUKind>(Name) 2169 .Case("tahiti", GK_GFX6) 2170 .Case("pitcairn", GK_GFX6) 2171 .Case("verde", GK_GFX6) 2172 .Case("oland", GK_GFX6) 2173 .Case("hainan", GK_GFX6) 2174 .Case("bonaire", GK_GFX7) 2175 .Case("kabini", GK_GFX7) 2176 .Case("kaveri", GK_GFX7) 2177 .Case("hawaii", GK_GFX7) 2178 .Case("mullins", GK_GFX7) 2179 .Case("tonga", GK_GFX8) 2180 .Case("iceland", GK_GFX8) 2181 .Case("carrizo", GK_GFX8) 2182 .Case("fiji", GK_GFX8) 2183 .Case("stoney", GK_GFX8) 2184 .Case("polaris10", GK_GFX8) 2185 .Case("polaris11", GK_GFX8) 2186 .Default(GK_NONE); 2187 } 2188 2189 bool setCPU(const std::string &Name) override { 2190 if (getTriple().getArch() == llvm::Triple::amdgcn) 2191 GPU = parseAMDGCNName(Name); 2192 else 2193 GPU = parseR600Name(Name); 2194 2195 return GPU != GK_NONE; 2196 } 2197 2198 void setSupportedOpenCLOpts() override { 2199 auto &Opts = getSupportedOpenCLOpts(); 2200 Opts.cl_clang_storage_class_specifiers = 1; 2201 Opts.cl_khr_icd = 1; 2202 2203 if (hasFP64) 2204 Opts.cl_khr_fp64 = 1; 2205 if (GPU >= GK_EVERGREEN) { 2206 Opts.cl_khr_byte_addressable_store = 1; 2207 Opts.cl_khr_global_int32_base_atomics = 1; 2208 Opts.cl_khr_global_int32_extended_atomics = 1; 2209 Opts.cl_khr_local_int32_base_atomics = 1; 2210 Opts.cl_khr_local_int32_extended_atomics = 1; 2211 } 2212 if (GPU >= GK_GFX6) { 2213 Opts.cl_khr_fp16 = 1; 2214 Opts.cl_khr_int64_base_atomics = 1; 2215 Opts.cl_khr_int64_extended_atomics = 1; 2216 Opts.cl_khr_mipmap_image = 1; 2217 Opts.cl_khr_subgroups = 1; 2218 Opts.cl_khr_3d_image_writes = 1; 2219 Opts.cl_amd_media_ops = 1; 2220 Opts.cl_amd_media_ops2 = 1; 2221 } 2222 } 2223 2224 LangAS::ID getOpenCLImageAddrSpace() const override { 2225 return LangAS::opencl_constant; 2226 } 2227 2228 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2229 switch (CC) { 2230 default: 2231 return CCCR_Warning; 2232 case CC_C: 2233 case CC_OpenCLKernel: 2234 return CCCR_OK; 2235 } 2236 } 2237 }; 2238 2239 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2240 #define BUILTIN(ID, TYPE, ATTRS) \ 2241 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2242 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2243 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2244 #include "clang/Basic/BuiltinsAMDGPU.def" 2245 }; 2246 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2247 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2248 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2249 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2250 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2251 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2252 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2253 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2254 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2255 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2256 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2257 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2258 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2259 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2260 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2261 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2262 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2263 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2264 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2265 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2266 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2267 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2268 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2269 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2270 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2271 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2272 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2273 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2274 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2275 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2276 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2277 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2278 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2279 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2280 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2281 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2282 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2283 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2284 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2285 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2286 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2287 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2288 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2289 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2290 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2291 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2292 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2293 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2294 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2295 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2296 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2297 }; 2298 2299 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2300 return llvm::makeArrayRef(GCCRegNames); 2301 } 2302 2303 bool AMDGPUTargetInfo::initFeatureMap( 2304 llvm::StringMap<bool> &Features, 2305 DiagnosticsEngine &Diags, StringRef CPU, 2306 const std::vector<std::string> &FeatureVec) const { 2307 2308 // XXX - What does the member GPU mean if device name string passed here? 2309 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2310 if (CPU.empty()) 2311 CPU = "tahiti"; 2312 2313 switch (parseAMDGCNName(CPU)) { 2314 case GK_GFX6: 2315 case GK_GFX7: 2316 break; 2317 2318 case GK_GFX8: 2319 Features["s-memrealtime"] = true; 2320 Features["16-bit-insts"] = true; 2321 break; 2322 2323 case GK_NONE: 2324 return false; 2325 default: 2326 llvm_unreachable("unhandled subtarget"); 2327 } 2328 } else { 2329 if (CPU.empty()) 2330 CPU = "r600"; 2331 2332 switch (parseR600Name(CPU)) { 2333 case GK_R600: 2334 case GK_R700: 2335 case GK_EVERGREEN: 2336 case GK_NORTHERN_ISLANDS: 2337 break; 2338 case GK_R600_DOUBLE_OPS: 2339 case GK_R700_DOUBLE_OPS: 2340 case GK_EVERGREEN_DOUBLE_OPS: 2341 case GK_CAYMAN: 2342 Features["fp64"] = true; 2343 break; 2344 case GK_NONE: 2345 return false; 2346 default: 2347 llvm_unreachable("unhandled subtarget"); 2348 } 2349 } 2350 2351 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2352 } 2353 2354 const Builtin::Info BuiltinInfoX86[] = { 2355 #define BUILTIN(ID, TYPE, ATTRS) \ 2356 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2357 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2358 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2359 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2360 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2361 #include "clang/Basic/BuiltinsX86.def" 2362 2363 #define BUILTIN(ID, TYPE, ATTRS) \ 2364 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2365 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2366 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2367 #include "clang/Basic/BuiltinsX86_64.def" 2368 }; 2369 2370 2371 static const char* const GCCRegNames[] = { 2372 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2373 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2374 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2375 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2376 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2377 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2378 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2379 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2380 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2381 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2382 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2383 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2384 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2385 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2386 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2387 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2388 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2389 }; 2390 2391 const TargetInfo::AddlRegName AddlRegNames[] = { 2392 { { "al", "ah", "eax", "rax" }, 0 }, 2393 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2394 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2395 { { "dl", "dh", "edx", "rdx" }, 1 }, 2396 { { "esi", "rsi" }, 4 }, 2397 { { "edi", "rdi" }, 5 }, 2398 { { "esp", "rsp" }, 7 }, 2399 { { "ebp", "rbp" }, 6 }, 2400 { { "r8d", "r8w", "r8b" }, 38 }, 2401 { { "r9d", "r9w", "r9b" }, 39 }, 2402 { { "r10d", "r10w", "r10b" }, 40 }, 2403 { { "r11d", "r11w", "r11b" }, 41 }, 2404 { { "r12d", "r12w", "r12b" }, 42 }, 2405 { { "r13d", "r13w", "r13b" }, 43 }, 2406 { { "r14d", "r14w", "r14b" }, 44 }, 2407 { { "r15d", "r15w", "r15b" }, 45 }, 2408 }; 2409 2410 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2411 // most of the implementation can be shared. 2412 class X86TargetInfo : public TargetInfo { 2413 enum X86SSEEnum { 2414 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2415 } SSELevel = NoSSE; 2416 enum MMX3DNowEnum { 2417 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2418 } MMX3DNowLevel = NoMMX3DNow; 2419 enum XOPEnum { 2420 NoXOP, 2421 SSE4A, 2422 FMA4, 2423 XOP 2424 } XOPLevel = NoXOP; 2425 2426 bool HasAES = false; 2427 bool HasPCLMUL = false; 2428 bool HasLZCNT = false; 2429 bool HasRDRND = false; 2430 bool HasFSGSBASE = false; 2431 bool HasBMI = false; 2432 bool HasBMI2 = false; 2433 bool HasPOPCNT = false; 2434 bool HasRTM = false; 2435 bool HasPRFCHW = false; 2436 bool HasRDSEED = false; 2437 bool HasADX = false; 2438 bool HasTBM = false; 2439 bool HasFMA = false; 2440 bool HasF16C = false; 2441 bool HasAVX512CD = false; 2442 bool HasAVX512ER = false; 2443 bool HasAVX512PF = false; 2444 bool HasAVX512DQ = false; 2445 bool HasAVX512BW = false; 2446 bool HasAVX512VL = false; 2447 bool HasAVX512VBMI = false; 2448 bool HasAVX512IFMA = false; 2449 bool HasSHA = false; 2450 bool HasMPX = false; 2451 bool HasSGX = false; 2452 bool HasCX16 = false; 2453 bool HasFXSR = false; 2454 bool HasXSAVE = false; 2455 bool HasXSAVEOPT = false; 2456 bool HasXSAVEC = false; 2457 bool HasXSAVES = false; 2458 bool HasMWAITX = false; 2459 bool HasPKU = false; 2460 bool HasCLFLUSHOPT = false; 2461 bool HasPCOMMIT = false; 2462 bool HasCLWB = false; 2463 bool HasUMIP = false; 2464 bool HasMOVBE = false; 2465 bool HasPREFETCHWT1 = false; 2466 2467 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2468 /// 2469 /// Each enumeration represents a particular CPU supported by Clang. These 2470 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2471 enum CPUKind { 2472 CK_Generic, 2473 2474 /// \name i386 2475 /// i386-generation processors. 2476 //@{ 2477 CK_i386, 2478 //@} 2479 2480 /// \name i486 2481 /// i486-generation processors. 2482 //@{ 2483 CK_i486, 2484 CK_WinChipC6, 2485 CK_WinChip2, 2486 CK_C3, 2487 //@} 2488 2489 /// \name i586 2490 /// i586-generation processors, P5 microarchitecture based. 2491 //@{ 2492 CK_i586, 2493 CK_Pentium, 2494 CK_PentiumMMX, 2495 //@} 2496 2497 /// \name i686 2498 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2499 //@{ 2500 CK_i686, 2501 CK_PentiumPro, 2502 CK_Pentium2, 2503 CK_Pentium3, 2504 CK_Pentium3M, 2505 CK_PentiumM, 2506 CK_C3_2, 2507 2508 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2509 /// Clang however has some logic to suport this. 2510 // FIXME: Warn, deprecate, and potentially remove this. 2511 CK_Yonah, 2512 //@} 2513 2514 /// \name Netburst 2515 /// Netburst microarchitecture based processors. 2516 //@{ 2517 CK_Pentium4, 2518 CK_Pentium4M, 2519 CK_Prescott, 2520 CK_Nocona, 2521 //@} 2522 2523 /// \name Core 2524 /// Core microarchitecture based processors. 2525 //@{ 2526 CK_Core2, 2527 2528 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2529 /// codename which GCC no longer accepts as an option to -march, but Clang 2530 /// has some logic for recognizing it. 2531 // FIXME: Warn, deprecate, and potentially remove this. 2532 CK_Penryn, 2533 //@} 2534 2535 /// \name Atom 2536 /// Atom processors 2537 //@{ 2538 CK_Bonnell, 2539 CK_Silvermont, 2540 //@} 2541 2542 /// \name Nehalem 2543 /// Nehalem microarchitecture based processors. 2544 CK_Nehalem, 2545 2546 /// \name Westmere 2547 /// Westmere microarchitecture based processors. 2548 CK_Westmere, 2549 2550 /// \name Sandy Bridge 2551 /// Sandy Bridge microarchitecture based processors. 2552 CK_SandyBridge, 2553 2554 /// \name Ivy Bridge 2555 /// Ivy Bridge microarchitecture based processors. 2556 CK_IvyBridge, 2557 2558 /// \name Haswell 2559 /// Haswell microarchitecture based processors. 2560 CK_Haswell, 2561 2562 /// \name Broadwell 2563 /// Broadwell microarchitecture based processors. 2564 CK_Broadwell, 2565 2566 /// \name Skylake Client 2567 /// Skylake client microarchitecture based processors. 2568 CK_SkylakeClient, 2569 2570 /// \name Skylake Server 2571 /// Skylake server microarchitecture based processors. 2572 CK_SkylakeServer, 2573 2574 /// \name Cannonlake Client 2575 /// Cannonlake client microarchitecture based processors. 2576 CK_Cannonlake, 2577 2578 /// \name Knights Landing 2579 /// Knights Landing processor. 2580 CK_KNL, 2581 2582 /// \name Lakemont 2583 /// Lakemont microarchitecture based processors. 2584 CK_Lakemont, 2585 2586 /// \name K6 2587 /// K6 architecture processors. 2588 //@{ 2589 CK_K6, 2590 CK_K6_2, 2591 CK_K6_3, 2592 //@} 2593 2594 /// \name K7 2595 /// K7 architecture processors. 2596 //@{ 2597 CK_Athlon, 2598 CK_AthlonThunderbird, 2599 CK_Athlon4, 2600 CK_AthlonXP, 2601 CK_AthlonMP, 2602 //@} 2603 2604 /// \name K8 2605 /// K8 architecture processors. 2606 //@{ 2607 CK_Athlon64, 2608 CK_Athlon64SSE3, 2609 CK_AthlonFX, 2610 CK_K8, 2611 CK_K8SSE3, 2612 CK_Opteron, 2613 CK_OpteronSSE3, 2614 CK_AMDFAM10, 2615 //@} 2616 2617 /// \name Bobcat 2618 /// Bobcat architecture processors. 2619 //@{ 2620 CK_BTVER1, 2621 CK_BTVER2, 2622 //@} 2623 2624 /// \name Bulldozer 2625 /// Bulldozer architecture processors. 2626 //@{ 2627 CK_BDVER1, 2628 CK_BDVER2, 2629 CK_BDVER3, 2630 CK_BDVER4, 2631 //@} 2632 2633 /// This specification is deprecated and will be removed in the future. 2634 /// Users should prefer \see CK_K8. 2635 // FIXME: Warn on this when the CPU is set to it. 2636 //@{ 2637 CK_x86_64, 2638 //@} 2639 2640 /// \name Geode 2641 /// Geode processors. 2642 //@{ 2643 CK_Geode 2644 //@} 2645 } CPU = CK_Generic; 2646 2647 CPUKind getCPUKind(StringRef CPU) const { 2648 return llvm::StringSwitch<CPUKind>(CPU) 2649 .Case("i386", CK_i386) 2650 .Case("i486", CK_i486) 2651 .Case("winchip-c6", CK_WinChipC6) 2652 .Case("winchip2", CK_WinChip2) 2653 .Case("c3", CK_C3) 2654 .Case("i586", CK_i586) 2655 .Case("pentium", CK_Pentium) 2656 .Case("pentium-mmx", CK_PentiumMMX) 2657 .Case("i686", CK_i686) 2658 .Case("pentiumpro", CK_PentiumPro) 2659 .Case("pentium2", CK_Pentium2) 2660 .Case("pentium3", CK_Pentium3) 2661 .Case("pentium3m", CK_Pentium3M) 2662 .Case("pentium-m", CK_PentiumM) 2663 .Case("c3-2", CK_C3_2) 2664 .Case("yonah", CK_Yonah) 2665 .Case("pentium4", CK_Pentium4) 2666 .Case("pentium4m", CK_Pentium4M) 2667 .Case("prescott", CK_Prescott) 2668 .Case("nocona", CK_Nocona) 2669 .Case("core2", CK_Core2) 2670 .Case("penryn", CK_Penryn) 2671 .Case("bonnell", CK_Bonnell) 2672 .Case("atom", CK_Bonnell) // Legacy name. 2673 .Case("silvermont", CK_Silvermont) 2674 .Case("slm", CK_Silvermont) // Legacy name. 2675 .Case("nehalem", CK_Nehalem) 2676 .Case("corei7", CK_Nehalem) // Legacy name. 2677 .Case("westmere", CK_Westmere) 2678 .Case("sandybridge", CK_SandyBridge) 2679 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2680 .Case("ivybridge", CK_IvyBridge) 2681 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2682 .Case("haswell", CK_Haswell) 2683 .Case("core-avx2", CK_Haswell) // Legacy name. 2684 .Case("broadwell", CK_Broadwell) 2685 .Case("skylake", CK_SkylakeClient) 2686 .Case("skylake-avx512", CK_SkylakeServer) 2687 .Case("skx", CK_SkylakeServer) // Legacy name. 2688 .Case("cannonlake", CK_Cannonlake) 2689 .Case("knl", CK_KNL) 2690 .Case("lakemont", CK_Lakemont) 2691 .Case("k6", CK_K6) 2692 .Case("k6-2", CK_K6_2) 2693 .Case("k6-3", CK_K6_3) 2694 .Case("athlon", CK_Athlon) 2695 .Case("athlon-tbird", CK_AthlonThunderbird) 2696 .Case("athlon-4", CK_Athlon4) 2697 .Case("athlon-xp", CK_AthlonXP) 2698 .Case("athlon-mp", CK_AthlonMP) 2699 .Case("athlon64", CK_Athlon64) 2700 .Case("athlon64-sse3", CK_Athlon64SSE3) 2701 .Case("athlon-fx", CK_AthlonFX) 2702 .Case("k8", CK_K8) 2703 .Case("k8-sse3", CK_K8SSE3) 2704 .Case("opteron", CK_Opteron) 2705 .Case("opteron-sse3", CK_OpteronSSE3) 2706 .Case("barcelona", CK_AMDFAM10) 2707 .Case("amdfam10", CK_AMDFAM10) 2708 .Case("btver1", CK_BTVER1) 2709 .Case("btver2", CK_BTVER2) 2710 .Case("bdver1", CK_BDVER1) 2711 .Case("bdver2", CK_BDVER2) 2712 .Case("bdver3", CK_BDVER3) 2713 .Case("bdver4", CK_BDVER4) 2714 .Case("x86-64", CK_x86_64) 2715 .Case("geode", CK_Geode) 2716 .Default(CK_Generic); 2717 } 2718 2719 enum FPMathKind { 2720 FP_Default, 2721 FP_SSE, 2722 FP_387 2723 } FPMath = FP_Default; 2724 2725 public: 2726 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2727 : TargetInfo(Triple) { 2728 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2729 } 2730 unsigned getFloatEvalMethod() const override { 2731 // X87 evaluates with 80 bits "long double" precision. 2732 return SSELevel == NoSSE ? 2 : 0; 2733 } 2734 ArrayRef<const char *> getGCCRegNames() const override { 2735 return llvm::makeArrayRef(GCCRegNames); 2736 } 2737 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2738 return None; 2739 } 2740 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2741 return llvm::makeArrayRef(AddlRegNames); 2742 } 2743 bool validateCpuSupports(StringRef Name) const override; 2744 bool validateAsmConstraint(const char *&Name, 2745 TargetInfo::ConstraintInfo &info) const override; 2746 2747 bool validateGlobalRegisterVariable(StringRef RegName, 2748 unsigned RegSize, 2749 bool &HasSizeMismatch) const override { 2750 // esp and ebp are the only 32-bit registers the x86 backend can currently 2751 // handle. 2752 if (RegName.equals("esp") || RegName.equals("ebp")) { 2753 // Check that the register size is 32-bit. 2754 HasSizeMismatch = RegSize != 32; 2755 return true; 2756 } 2757 2758 return false; 2759 } 2760 2761 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2762 2763 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2764 2765 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2766 2767 std::string convertConstraint(const char *&Constraint) const override; 2768 const char *getClobbers() const override { 2769 return "~{dirflag},~{fpsr},~{flags}"; 2770 } 2771 void getTargetDefines(const LangOptions &Opts, 2772 MacroBuilder &Builder) const override; 2773 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2774 bool Enabled); 2775 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2776 bool Enabled); 2777 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2778 bool Enabled); 2779 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2780 StringRef Name, bool Enabled) const override { 2781 setFeatureEnabledImpl(Features, Name, Enabled); 2782 } 2783 // This exists purely to cut down on the number of virtual calls in 2784 // initFeatureMap which calls this repeatedly. 2785 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2786 StringRef Name, bool Enabled); 2787 bool 2788 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2789 StringRef CPU, 2790 const std::vector<std::string> &FeaturesVec) const override; 2791 bool hasFeature(StringRef Feature) const override; 2792 bool handleTargetFeatures(std::vector<std::string> &Features, 2793 DiagnosticsEngine &Diags) override; 2794 StringRef getABI() const override { 2795 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2796 return "avx512"; 2797 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2798 return "avx"; 2799 if (getTriple().getArch() == llvm::Triple::x86 && 2800 MMX3DNowLevel == NoMMX3DNow) 2801 return "no-mmx"; 2802 return ""; 2803 } 2804 bool setCPU(const std::string &Name) override { 2805 CPU = getCPUKind(Name); 2806 2807 // Perform any per-CPU checks necessary to determine if this CPU is 2808 // acceptable. 2809 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2810 // invalid without explaining *why*. 2811 switch (CPU) { 2812 case CK_Generic: 2813 // No processor selected! 2814 return false; 2815 2816 case CK_i386: 2817 case CK_i486: 2818 case CK_WinChipC6: 2819 case CK_WinChip2: 2820 case CK_C3: 2821 case CK_i586: 2822 case CK_Pentium: 2823 case CK_PentiumMMX: 2824 case CK_i686: 2825 case CK_PentiumPro: 2826 case CK_Pentium2: 2827 case CK_Pentium3: 2828 case CK_Pentium3M: 2829 case CK_PentiumM: 2830 case CK_Yonah: 2831 case CK_C3_2: 2832 case CK_Pentium4: 2833 case CK_Pentium4M: 2834 case CK_Lakemont: 2835 case CK_Prescott: 2836 case CK_K6: 2837 case CK_K6_2: 2838 case CK_K6_3: 2839 case CK_Athlon: 2840 case CK_AthlonThunderbird: 2841 case CK_Athlon4: 2842 case CK_AthlonXP: 2843 case CK_AthlonMP: 2844 case CK_Geode: 2845 // Only accept certain architectures when compiling in 32-bit mode. 2846 if (getTriple().getArch() != llvm::Triple::x86) 2847 return false; 2848 2849 // Fallthrough 2850 case CK_Nocona: 2851 case CK_Core2: 2852 case CK_Penryn: 2853 case CK_Bonnell: 2854 case CK_Silvermont: 2855 case CK_Nehalem: 2856 case CK_Westmere: 2857 case CK_SandyBridge: 2858 case CK_IvyBridge: 2859 case CK_Haswell: 2860 case CK_Broadwell: 2861 case CK_SkylakeClient: 2862 case CK_SkylakeServer: 2863 case CK_Cannonlake: 2864 case CK_KNL: 2865 case CK_Athlon64: 2866 case CK_Athlon64SSE3: 2867 case CK_AthlonFX: 2868 case CK_K8: 2869 case CK_K8SSE3: 2870 case CK_Opteron: 2871 case CK_OpteronSSE3: 2872 case CK_AMDFAM10: 2873 case CK_BTVER1: 2874 case CK_BTVER2: 2875 case CK_BDVER1: 2876 case CK_BDVER2: 2877 case CK_BDVER3: 2878 case CK_BDVER4: 2879 case CK_x86_64: 2880 return true; 2881 } 2882 llvm_unreachable("Unhandled CPU kind"); 2883 } 2884 2885 bool setFPMath(StringRef Name) override; 2886 2887 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2888 // Most of the non-ARM calling conventions are i386 conventions. 2889 switch (CC) { 2890 case CC_X86ThisCall: 2891 case CC_X86FastCall: 2892 case CC_X86StdCall: 2893 case CC_X86VectorCall: 2894 case CC_C: 2895 case CC_Swift: 2896 case CC_X86Pascal: 2897 case CC_IntelOclBicc: 2898 return CCCR_OK; 2899 default: 2900 return CCCR_Warning; 2901 } 2902 } 2903 2904 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2905 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2906 } 2907 2908 bool hasSjLjLowering() const override { 2909 return true; 2910 } 2911 2912 void setSupportedOpenCLOpts() override { 2913 getSupportedOpenCLOpts().setAll(); 2914 } 2915 }; 2916 2917 bool X86TargetInfo::setFPMath(StringRef Name) { 2918 if (Name == "387") { 2919 FPMath = FP_387; 2920 return true; 2921 } 2922 if (Name == "sse") { 2923 FPMath = FP_SSE; 2924 return true; 2925 } 2926 return false; 2927 } 2928 2929 bool X86TargetInfo::initFeatureMap( 2930 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2931 const std::vector<std::string> &FeaturesVec) const { 2932 // FIXME: This *really* should not be here. 2933 // X86_64 always has SSE2. 2934 if (getTriple().getArch() == llvm::Triple::x86_64) 2935 setFeatureEnabledImpl(Features, "sse2", true); 2936 2937 const CPUKind Kind = getCPUKind(CPU); 2938 2939 // Enable X87 for all X86 processors but Lakemont. 2940 if (Kind != CK_Lakemont) 2941 setFeatureEnabledImpl(Features, "x87", true); 2942 2943 switch (Kind) { 2944 case CK_Generic: 2945 case CK_i386: 2946 case CK_i486: 2947 case CK_i586: 2948 case CK_Pentium: 2949 case CK_i686: 2950 case CK_PentiumPro: 2951 case CK_Lakemont: 2952 break; 2953 case CK_PentiumMMX: 2954 case CK_Pentium2: 2955 case CK_K6: 2956 case CK_WinChipC6: 2957 setFeatureEnabledImpl(Features, "mmx", true); 2958 break; 2959 case CK_Pentium3: 2960 case CK_Pentium3M: 2961 case CK_C3_2: 2962 setFeatureEnabledImpl(Features, "sse", true); 2963 setFeatureEnabledImpl(Features, "fxsr", true); 2964 break; 2965 case CK_PentiumM: 2966 case CK_Pentium4: 2967 case CK_Pentium4M: 2968 case CK_x86_64: 2969 setFeatureEnabledImpl(Features, "sse2", true); 2970 setFeatureEnabledImpl(Features, "fxsr", true); 2971 break; 2972 case CK_Yonah: 2973 case CK_Prescott: 2974 case CK_Nocona: 2975 setFeatureEnabledImpl(Features, "sse3", true); 2976 setFeatureEnabledImpl(Features, "fxsr", true); 2977 setFeatureEnabledImpl(Features, "cx16", true); 2978 break; 2979 case CK_Core2: 2980 case CK_Bonnell: 2981 setFeatureEnabledImpl(Features, "ssse3", true); 2982 setFeatureEnabledImpl(Features, "fxsr", true); 2983 setFeatureEnabledImpl(Features, "cx16", true); 2984 break; 2985 case CK_Penryn: 2986 setFeatureEnabledImpl(Features, "sse4.1", true); 2987 setFeatureEnabledImpl(Features, "fxsr", true); 2988 setFeatureEnabledImpl(Features, "cx16", true); 2989 break; 2990 case CK_Cannonlake: 2991 setFeatureEnabledImpl(Features, "avx512ifma", true); 2992 setFeatureEnabledImpl(Features, "avx512vbmi", true); 2993 setFeatureEnabledImpl(Features, "sha", true); 2994 setFeatureEnabledImpl(Features, "umip", true); 2995 // FALLTHROUGH 2996 case CK_SkylakeServer: 2997 setFeatureEnabledImpl(Features, "avx512f", true); 2998 setFeatureEnabledImpl(Features, "avx512cd", true); 2999 setFeatureEnabledImpl(Features, "avx512dq", true); 3000 setFeatureEnabledImpl(Features, "avx512bw", true); 3001 setFeatureEnabledImpl(Features, "avx512vl", true); 3002 setFeatureEnabledImpl(Features, "pku", true); 3003 setFeatureEnabledImpl(Features, "pcommit", true); 3004 setFeatureEnabledImpl(Features, "clwb", true); 3005 // FALLTHROUGH 3006 case CK_SkylakeClient: 3007 setFeatureEnabledImpl(Features, "xsavec", true); 3008 setFeatureEnabledImpl(Features, "xsaves", true); 3009 setFeatureEnabledImpl(Features, "mpx", true); 3010 setFeatureEnabledImpl(Features, "sgx", true); 3011 setFeatureEnabledImpl(Features, "clflushopt", true); 3012 // FALLTHROUGH 3013 case CK_Broadwell: 3014 setFeatureEnabledImpl(Features, "rdseed", true); 3015 setFeatureEnabledImpl(Features, "adx", true); 3016 // FALLTHROUGH 3017 case CK_Haswell: 3018 setFeatureEnabledImpl(Features, "avx2", true); 3019 setFeatureEnabledImpl(Features, "lzcnt", true); 3020 setFeatureEnabledImpl(Features, "bmi", true); 3021 setFeatureEnabledImpl(Features, "bmi2", true); 3022 setFeatureEnabledImpl(Features, "rtm", true); 3023 setFeatureEnabledImpl(Features, "fma", true); 3024 setFeatureEnabledImpl(Features, "movbe", true); 3025 // FALLTHROUGH 3026 case CK_IvyBridge: 3027 setFeatureEnabledImpl(Features, "rdrnd", true); 3028 setFeatureEnabledImpl(Features, "f16c", true); 3029 setFeatureEnabledImpl(Features, "fsgsbase", true); 3030 // FALLTHROUGH 3031 case CK_SandyBridge: 3032 setFeatureEnabledImpl(Features, "avx", true); 3033 setFeatureEnabledImpl(Features, "xsave", true); 3034 setFeatureEnabledImpl(Features, "xsaveopt", true); 3035 // FALLTHROUGH 3036 case CK_Westmere: 3037 case CK_Silvermont: 3038 setFeatureEnabledImpl(Features, "aes", true); 3039 setFeatureEnabledImpl(Features, "pclmul", true); 3040 // FALLTHROUGH 3041 case CK_Nehalem: 3042 setFeatureEnabledImpl(Features, "sse4.2", true); 3043 setFeatureEnabledImpl(Features, "fxsr", true); 3044 setFeatureEnabledImpl(Features, "cx16", true); 3045 break; 3046 case CK_KNL: 3047 setFeatureEnabledImpl(Features, "avx512f", true); 3048 setFeatureEnabledImpl(Features, "avx512cd", true); 3049 setFeatureEnabledImpl(Features, "avx512er", true); 3050 setFeatureEnabledImpl(Features, "avx512pf", true); 3051 setFeatureEnabledImpl(Features, "prefetchwt1", true); 3052 setFeatureEnabledImpl(Features, "fxsr", true); 3053 setFeatureEnabledImpl(Features, "rdseed", true); 3054 setFeatureEnabledImpl(Features, "adx", true); 3055 setFeatureEnabledImpl(Features, "lzcnt", true); 3056 setFeatureEnabledImpl(Features, "bmi", true); 3057 setFeatureEnabledImpl(Features, "bmi2", true); 3058 setFeatureEnabledImpl(Features, "rtm", true); 3059 setFeatureEnabledImpl(Features, "fma", true); 3060 setFeatureEnabledImpl(Features, "rdrnd", true); 3061 setFeatureEnabledImpl(Features, "f16c", true); 3062 setFeatureEnabledImpl(Features, "fsgsbase", true); 3063 setFeatureEnabledImpl(Features, "aes", true); 3064 setFeatureEnabledImpl(Features, "pclmul", true); 3065 setFeatureEnabledImpl(Features, "cx16", true); 3066 setFeatureEnabledImpl(Features, "xsaveopt", true); 3067 setFeatureEnabledImpl(Features, "xsave", true); 3068 setFeatureEnabledImpl(Features, "movbe", true); 3069 break; 3070 case CK_K6_2: 3071 case CK_K6_3: 3072 case CK_WinChip2: 3073 case CK_C3: 3074 setFeatureEnabledImpl(Features, "3dnow", true); 3075 break; 3076 case CK_Athlon: 3077 case CK_AthlonThunderbird: 3078 case CK_Geode: 3079 setFeatureEnabledImpl(Features, "3dnowa", true); 3080 break; 3081 case CK_Athlon4: 3082 case CK_AthlonXP: 3083 case CK_AthlonMP: 3084 setFeatureEnabledImpl(Features, "sse", true); 3085 setFeatureEnabledImpl(Features, "3dnowa", true); 3086 setFeatureEnabledImpl(Features, "fxsr", true); 3087 break; 3088 case CK_K8: 3089 case CK_Opteron: 3090 case CK_Athlon64: 3091 case CK_AthlonFX: 3092 setFeatureEnabledImpl(Features, "sse2", true); 3093 setFeatureEnabledImpl(Features, "3dnowa", true); 3094 setFeatureEnabledImpl(Features, "fxsr", true); 3095 break; 3096 case CK_AMDFAM10: 3097 setFeatureEnabledImpl(Features, "sse4a", true); 3098 setFeatureEnabledImpl(Features, "lzcnt", true); 3099 setFeatureEnabledImpl(Features, "popcnt", true); 3100 // FALLTHROUGH 3101 case CK_K8SSE3: 3102 case CK_OpteronSSE3: 3103 case CK_Athlon64SSE3: 3104 setFeatureEnabledImpl(Features, "sse3", true); 3105 setFeatureEnabledImpl(Features, "3dnowa", true); 3106 setFeatureEnabledImpl(Features, "fxsr", true); 3107 break; 3108 case CK_BTVER2: 3109 setFeatureEnabledImpl(Features, "avx", true); 3110 setFeatureEnabledImpl(Features, "aes", true); 3111 setFeatureEnabledImpl(Features, "pclmul", true); 3112 setFeatureEnabledImpl(Features, "bmi", true); 3113 setFeatureEnabledImpl(Features, "f16c", true); 3114 setFeatureEnabledImpl(Features, "xsaveopt", true); 3115 // FALLTHROUGH 3116 case CK_BTVER1: 3117 setFeatureEnabledImpl(Features, "ssse3", true); 3118 setFeatureEnabledImpl(Features, "sse4a", true); 3119 setFeatureEnabledImpl(Features, "lzcnt", true); 3120 setFeatureEnabledImpl(Features, "popcnt", true); 3121 setFeatureEnabledImpl(Features, "prfchw", true); 3122 setFeatureEnabledImpl(Features, "cx16", true); 3123 setFeatureEnabledImpl(Features, "fxsr", true); 3124 break; 3125 case CK_BDVER4: 3126 setFeatureEnabledImpl(Features, "avx2", true); 3127 setFeatureEnabledImpl(Features, "bmi2", true); 3128 setFeatureEnabledImpl(Features, "mwaitx", true); 3129 // FALLTHROUGH 3130 case CK_BDVER3: 3131 setFeatureEnabledImpl(Features, "fsgsbase", true); 3132 setFeatureEnabledImpl(Features, "xsaveopt", true); 3133 // FALLTHROUGH 3134 case CK_BDVER2: 3135 setFeatureEnabledImpl(Features, "bmi", true); 3136 setFeatureEnabledImpl(Features, "fma", true); 3137 setFeatureEnabledImpl(Features, "f16c", true); 3138 setFeatureEnabledImpl(Features, "tbm", true); 3139 // FALLTHROUGH 3140 case CK_BDVER1: 3141 // xop implies avx, sse4a and fma4. 3142 setFeatureEnabledImpl(Features, "xop", true); 3143 setFeatureEnabledImpl(Features, "lzcnt", true); 3144 setFeatureEnabledImpl(Features, "aes", true); 3145 setFeatureEnabledImpl(Features, "pclmul", true); 3146 setFeatureEnabledImpl(Features, "prfchw", true); 3147 setFeatureEnabledImpl(Features, "cx16", true); 3148 setFeatureEnabledImpl(Features, "fxsr", true); 3149 setFeatureEnabledImpl(Features, "xsave", true); 3150 break; 3151 } 3152 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3153 return false; 3154 3155 // Can't do this earlier because we need to be able to explicitly enable 3156 // or disable these features and the things that they depend upon. 3157 3158 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3159 auto I = Features.find("sse4.2"); 3160 if (I != Features.end() && I->getValue() && 3161 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3162 FeaturesVec.end()) 3163 Features["popcnt"] = true; 3164 3165 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3166 I = Features.find("3dnow"); 3167 if (I != Features.end() && I->getValue() && 3168 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3169 FeaturesVec.end()) 3170 Features["prfchw"] = true; 3171 3172 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3173 // then enable MMX. 3174 I = Features.find("sse"); 3175 if (I != Features.end() && I->getValue() && 3176 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3177 FeaturesVec.end()) 3178 Features["mmx"] = true; 3179 3180 return true; 3181 } 3182 3183 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3184 X86SSEEnum Level, bool Enabled) { 3185 if (Enabled) { 3186 switch (Level) { 3187 case AVX512F: 3188 Features["avx512f"] = true; 3189 case AVX2: 3190 Features["avx2"] = true; 3191 case AVX: 3192 Features["avx"] = true; 3193 Features["xsave"] = true; 3194 case SSE42: 3195 Features["sse4.2"] = true; 3196 case SSE41: 3197 Features["sse4.1"] = true; 3198 case SSSE3: 3199 Features["ssse3"] = true; 3200 case SSE3: 3201 Features["sse3"] = true; 3202 case SSE2: 3203 Features["sse2"] = true; 3204 case SSE1: 3205 Features["sse"] = true; 3206 case NoSSE: 3207 break; 3208 } 3209 return; 3210 } 3211 3212 switch (Level) { 3213 case NoSSE: 3214 case SSE1: 3215 Features["sse"] = false; 3216 case SSE2: 3217 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3218 Features["sha"] = false; 3219 case SSE3: 3220 Features["sse3"] = false; 3221 setXOPLevel(Features, NoXOP, false); 3222 case SSSE3: 3223 Features["ssse3"] = false; 3224 case SSE41: 3225 Features["sse4.1"] = false; 3226 case SSE42: 3227 Features["sse4.2"] = false; 3228 case AVX: 3229 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3230 Features["xsaveopt"] = false; 3231 setXOPLevel(Features, FMA4, false); 3232 case AVX2: 3233 Features["avx2"] = false; 3234 case AVX512F: 3235 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3236 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3237 Features["avx512vl"] = Features["avx512vbmi"] = 3238 Features["avx512ifma"] = false; 3239 } 3240 } 3241 3242 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3243 MMX3DNowEnum Level, bool Enabled) { 3244 if (Enabled) { 3245 switch (Level) { 3246 case AMD3DNowAthlon: 3247 Features["3dnowa"] = true; 3248 case AMD3DNow: 3249 Features["3dnow"] = true; 3250 case MMX: 3251 Features["mmx"] = true; 3252 case NoMMX3DNow: 3253 break; 3254 } 3255 return; 3256 } 3257 3258 switch (Level) { 3259 case NoMMX3DNow: 3260 case MMX: 3261 Features["mmx"] = false; 3262 case AMD3DNow: 3263 Features["3dnow"] = false; 3264 case AMD3DNowAthlon: 3265 Features["3dnowa"] = false; 3266 } 3267 } 3268 3269 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3270 bool Enabled) { 3271 if (Enabled) { 3272 switch (Level) { 3273 case XOP: 3274 Features["xop"] = true; 3275 case FMA4: 3276 Features["fma4"] = true; 3277 setSSELevel(Features, AVX, true); 3278 case SSE4A: 3279 Features["sse4a"] = true; 3280 setSSELevel(Features, SSE3, true); 3281 case NoXOP: 3282 break; 3283 } 3284 return; 3285 } 3286 3287 switch (Level) { 3288 case NoXOP: 3289 case SSE4A: 3290 Features["sse4a"] = false; 3291 case FMA4: 3292 Features["fma4"] = false; 3293 case XOP: 3294 Features["xop"] = false; 3295 } 3296 } 3297 3298 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3299 StringRef Name, bool Enabled) { 3300 // This is a bit of a hack to deal with the sse4 target feature when used 3301 // as part of the target attribute. We handle sse4 correctly everywhere 3302 // else. See below for more information on how we handle the sse4 options. 3303 if (Name != "sse4") 3304 Features[Name] = Enabled; 3305 3306 if (Name == "mmx") { 3307 setMMXLevel(Features, MMX, Enabled); 3308 } else if (Name == "sse") { 3309 setSSELevel(Features, SSE1, Enabled); 3310 } else if (Name == "sse2") { 3311 setSSELevel(Features, SSE2, Enabled); 3312 } else if (Name == "sse3") { 3313 setSSELevel(Features, SSE3, Enabled); 3314 } else if (Name == "ssse3") { 3315 setSSELevel(Features, SSSE3, Enabled); 3316 } else if (Name == "sse4.2") { 3317 setSSELevel(Features, SSE42, Enabled); 3318 } else if (Name == "sse4.1") { 3319 setSSELevel(Features, SSE41, Enabled); 3320 } else if (Name == "3dnow") { 3321 setMMXLevel(Features, AMD3DNow, Enabled); 3322 } else if (Name == "3dnowa") { 3323 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3324 } else if (Name == "aes") { 3325 if (Enabled) 3326 setSSELevel(Features, SSE2, Enabled); 3327 } else if (Name == "pclmul") { 3328 if (Enabled) 3329 setSSELevel(Features, SSE2, Enabled); 3330 } else if (Name == "avx") { 3331 setSSELevel(Features, AVX, Enabled); 3332 } else if (Name == "avx2") { 3333 setSSELevel(Features, AVX2, Enabled); 3334 } else if (Name == "avx512f") { 3335 setSSELevel(Features, AVX512F, Enabled); 3336 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3337 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3338 Name == "avx512vbmi" || Name == "avx512ifma") { 3339 if (Enabled) 3340 setSSELevel(Features, AVX512F, Enabled); 3341 } else if (Name == "fma") { 3342 if (Enabled) 3343 setSSELevel(Features, AVX, Enabled); 3344 } else if (Name == "fma4") { 3345 setXOPLevel(Features, FMA4, Enabled); 3346 } else if (Name == "xop") { 3347 setXOPLevel(Features, XOP, Enabled); 3348 } else if (Name == "sse4a") { 3349 setXOPLevel(Features, SSE4A, Enabled); 3350 } else if (Name == "f16c") { 3351 if (Enabled) 3352 setSSELevel(Features, AVX, Enabled); 3353 } else if (Name == "sha") { 3354 if (Enabled) 3355 setSSELevel(Features, SSE2, Enabled); 3356 } else if (Name == "sse4") { 3357 // We can get here via the __target__ attribute since that's not controlled 3358 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3359 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3360 // disabled. 3361 if (Enabled) 3362 setSSELevel(Features, SSE42, Enabled); 3363 else 3364 setSSELevel(Features, SSE41, Enabled); 3365 } else if (Name == "xsave") { 3366 if (!Enabled) 3367 Features["xsaveopt"] = false; 3368 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3369 if (Enabled) 3370 Features["xsave"] = true; 3371 } 3372 } 3373 3374 /// handleTargetFeatures - Perform initialization based on the user 3375 /// configured set of features. 3376 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3377 DiagnosticsEngine &Diags) { 3378 for (const auto &Feature : Features) { 3379 if (Feature[0] != '+') 3380 continue; 3381 3382 if (Feature == "+aes") { 3383 HasAES = true; 3384 } else if (Feature == "+pclmul") { 3385 HasPCLMUL = true; 3386 } else if (Feature == "+lzcnt") { 3387 HasLZCNT = true; 3388 } else if (Feature == "+rdrnd") { 3389 HasRDRND = true; 3390 } else if (Feature == "+fsgsbase") { 3391 HasFSGSBASE = true; 3392 } else if (Feature == "+bmi") { 3393 HasBMI = true; 3394 } else if (Feature == "+bmi2") { 3395 HasBMI2 = true; 3396 } else if (Feature == "+popcnt") { 3397 HasPOPCNT = true; 3398 } else if (Feature == "+rtm") { 3399 HasRTM = true; 3400 } else if (Feature == "+prfchw") { 3401 HasPRFCHW = true; 3402 } else if (Feature == "+rdseed") { 3403 HasRDSEED = true; 3404 } else if (Feature == "+adx") { 3405 HasADX = true; 3406 } else if (Feature == "+tbm") { 3407 HasTBM = true; 3408 } else if (Feature == "+fma") { 3409 HasFMA = true; 3410 } else if (Feature == "+f16c") { 3411 HasF16C = true; 3412 } else if (Feature == "+avx512cd") { 3413 HasAVX512CD = true; 3414 } else if (Feature == "+avx512er") { 3415 HasAVX512ER = true; 3416 } else if (Feature == "+avx512pf") { 3417 HasAVX512PF = true; 3418 } else if (Feature == "+avx512dq") { 3419 HasAVX512DQ = true; 3420 } else if (Feature == "+avx512bw") { 3421 HasAVX512BW = true; 3422 } else if (Feature == "+avx512vl") { 3423 HasAVX512VL = true; 3424 } else if (Feature == "+avx512vbmi") { 3425 HasAVX512VBMI = true; 3426 } else if (Feature == "+avx512ifma") { 3427 HasAVX512IFMA = true; 3428 } else if (Feature == "+sha") { 3429 HasSHA = true; 3430 } else if (Feature == "+mpx") { 3431 HasMPX = true; 3432 } else if (Feature == "+movbe") { 3433 HasMOVBE = true; 3434 } else if (Feature == "+sgx") { 3435 HasSGX = true; 3436 } else if (Feature == "+cx16") { 3437 HasCX16 = true; 3438 } else if (Feature == "+fxsr") { 3439 HasFXSR = true; 3440 } else if (Feature == "+xsave") { 3441 HasXSAVE = true; 3442 } else if (Feature == "+xsaveopt") { 3443 HasXSAVEOPT = true; 3444 } else if (Feature == "+xsavec") { 3445 HasXSAVEC = true; 3446 } else if (Feature == "+xsaves") { 3447 HasXSAVES = true; 3448 } else if (Feature == "+mwaitx") { 3449 HasMWAITX = true; 3450 } else if (Feature == "+pku") { 3451 HasPKU = true; 3452 } else if (Feature == "+clflushopt") { 3453 HasCLFLUSHOPT = true; 3454 } else if (Feature == "+pcommit") { 3455 HasPCOMMIT = true; 3456 } else if (Feature == "+clwb") { 3457 HasCLWB = true; 3458 } else if (Feature == "+umip") { 3459 HasUMIP = true; 3460 } else if (Feature == "+prefetchwt1") { 3461 HasPREFETCHWT1 = true; 3462 } 3463 3464 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3465 .Case("+avx512f", AVX512F) 3466 .Case("+avx2", AVX2) 3467 .Case("+avx", AVX) 3468 .Case("+sse4.2", SSE42) 3469 .Case("+sse4.1", SSE41) 3470 .Case("+ssse3", SSSE3) 3471 .Case("+sse3", SSE3) 3472 .Case("+sse2", SSE2) 3473 .Case("+sse", SSE1) 3474 .Default(NoSSE); 3475 SSELevel = std::max(SSELevel, Level); 3476 3477 MMX3DNowEnum ThreeDNowLevel = 3478 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3479 .Case("+3dnowa", AMD3DNowAthlon) 3480 .Case("+3dnow", AMD3DNow) 3481 .Case("+mmx", MMX) 3482 .Default(NoMMX3DNow); 3483 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3484 3485 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3486 .Case("+xop", XOP) 3487 .Case("+fma4", FMA4) 3488 .Case("+sse4a", SSE4A) 3489 .Default(NoXOP); 3490 XOPLevel = std::max(XOPLevel, XLevel); 3491 } 3492 3493 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3494 // matches the selected sse level. 3495 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3496 (FPMath == FP_387 && SSELevel >= SSE1)) { 3497 Diags.Report(diag::err_target_unsupported_fpmath) << 3498 (FPMath == FP_SSE ? "sse" : "387"); 3499 return false; 3500 } 3501 3502 SimdDefaultAlign = 3503 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3504 return true; 3505 } 3506 3507 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3508 /// definitions for this particular subtarget. 3509 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3510 MacroBuilder &Builder) const { 3511 // Target identification. 3512 if (getTriple().getArch() == llvm::Triple::x86_64) { 3513 Builder.defineMacro("__amd64__"); 3514 Builder.defineMacro("__amd64"); 3515 Builder.defineMacro("__x86_64"); 3516 Builder.defineMacro("__x86_64__"); 3517 if (getTriple().getArchName() == "x86_64h") { 3518 Builder.defineMacro("__x86_64h"); 3519 Builder.defineMacro("__x86_64h__"); 3520 } 3521 } else { 3522 DefineStd(Builder, "i386", Opts); 3523 } 3524 3525 // Subtarget options. 3526 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3527 // truly should be based on -mtune options. 3528 switch (CPU) { 3529 case CK_Generic: 3530 break; 3531 case CK_i386: 3532 // The rest are coming from the i386 define above. 3533 Builder.defineMacro("__tune_i386__"); 3534 break; 3535 case CK_i486: 3536 case CK_WinChipC6: 3537 case CK_WinChip2: 3538 case CK_C3: 3539 defineCPUMacros(Builder, "i486"); 3540 break; 3541 case CK_PentiumMMX: 3542 Builder.defineMacro("__pentium_mmx__"); 3543 Builder.defineMacro("__tune_pentium_mmx__"); 3544 // Fallthrough 3545 case CK_i586: 3546 case CK_Pentium: 3547 defineCPUMacros(Builder, "i586"); 3548 defineCPUMacros(Builder, "pentium"); 3549 break; 3550 case CK_Pentium3: 3551 case CK_Pentium3M: 3552 case CK_PentiumM: 3553 Builder.defineMacro("__tune_pentium3__"); 3554 // Fallthrough 3555 case CK_Pentium2: 3556 case CK_C3_2: 3557 Builder.defineMacro("__tune_pentium2__"); 3558 // Fallthrough 3559 case CK_PentiumPro: 3560 Builder.defineMacro("__tune_i686__"); 3561 Builder.defineMacro("__tune_pentiumpro__"); 3562 // Fallthrough 3563 case CK_i686: 3564 Builder.defineMacro("__i686"); 3565 Builder.defineMacro("__i686__"); 3566 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3567 Builder.defineMacro("__pentiumpro"); 3568 Builder.defineMacro("__pentiumpro__"); 3569 break; 3570 case CK_Pentium4: 3571 case CK_Pentium4M: 3572 defineCPUMacros(Builder, "pentium4"); 3573 break; 3574 case CK_Yonah: 3575 case CK_Prescott: 3576 case CK_Nocona: 3577 defineCPUMacros(Builder, "nocona"); 3578 break; 3579 case CK_Core2: 3580 case CK_Penryn: 3581 defineCPUMacros(Builder, "core2"); 3582 break; 3583 case CK_Bonnell: 3584 defineCPUMacros(Builder, "atom"); 3585 break; 3586 case CK_Silvermont: 3587 defineCPUMacros(Builder, "slm"); 3588 break; 3589 case CK_Nehalem: 3590 case CK_Westmere: 3591 case CK_SandyBridge: 3592 case CK_IvyBridge: 3593 case CK_Haswell: 3594 case CK_Broadwell: 3595 case CK_SkylakeClient: 3596 // FIXME: Historically, we defined this legacy name, it would be nice to 3597 // remove it at some point. We've never exposed fine-grained names for 3598 // recent primary x86 CPUs, and we should keep it that way. 3599 defineCPUMacros(Builder, "corei7"); 3600 break; 3601 case CK_SkylakeServer: 3602 defineCPUMacros(Builder, "skx"); 3603 break; 3604 case CK_Cannonlake: 3605 break; 3606 case CK_KNL: 3607 defineCPUMacros(Builder, "knl"); 3608 break; 3609 case CK_Lakemont: 3610 Builder.defineMacro("__tune_lakemont__"); 3611 break; 3612 case CK_K6_2: 3613 Builder.defineMacro("__k6_2__"); 3614 Builder.defineMacro("__tune_k6_2__"); 3615 // Fallthrough 3616 case CK_K6_3: 3617 if (CPU != CK_K6_2) { // In case of fallthrough 3618 // FIXME: GCC may be enabling these in cases where some other k6 3619 // architecture is specified but -m3dnow is explicitly provided. The 3620 // exact semantics need to be determined and emulated here. 3621 Builder.defineMacro("__k6_3__"); 3622 Builder.defineMacro("__tune_k6_3__"); 3623 } 3624 // Fallthrough 3625 case CK_K6: 3626 defineCPUMacros(Builder, "k6"); 3627 break; 3628 case CK_Athlon: 3629 case CK_AthlonThunderbird: 3630 case CK_Athlon4: 3631 case CK_AthlonXP: 3632 case CK_AthlonMP: 3633 defineCPUMacros(Builder, "athlon"); 3634 if (SSELevel != NoSSE) { 3635 Builder.defineMacro("__athlon_sse__"); 3636 Builder.defineMacro("__tune_athlon_sse__"); 3637 } 3638 break; 3639 case CK_K8: 3640 case CK_K8SSE3: 3641 case CK_x86_64: 3642 case CK_Opteron: 3643 case CK_OpteronSSE3: 3644 case CK_Athlon64: 3645 case CK_Athlon64SSE3: 3646 case CK_AthlonFX: 3647 defineCPUMacros(Builder, "k8"); 3648 break; 3649 case CK_AMDFAM10: 3650 defineCPUMacros(Builder, "amdfam10"); 3651 break; 3652 case CK_BTVER1: 3653 defineCPUMacros(Builder, "btver1"); 3654 break; 3655 case CK_BTVER2: 3656 defineCPUMacros(Builder, "btver2"); 3657 break; 3658 case CK_BDVER1: 3659 defineCPUMacros(Builder, "bdver1"); 3660 break; 3661 case CK_BDVER2: 3662 defineCPUMacros(Builder, "bdver2"); 3663 break; 3664 case CK_BDVER3: 3665 defineCPUMacros(Builder, "bdver3"); 3666 break; 3667 case CK_BDVER4: 3668 defineCPUMacros(Builder, "bdver4"); 3669 break; 3670 case CK_Geode: 3671 defineCPUMacros(Builder, "geode"); 3672 break; 3673 } 3674 3675 // Target properties. 3676 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3677 3678 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3679 // functions in glibc header files that use FP Stack inline asm which the 3680 // backend can't deal with (PR879). 3681 Builder.defineMacro("__NO_MATH_INLINES"); 3682 3683 if (HasAES) 3684 Builder.defineMacro("__AES__"); 3685 3686 if (HasPCLMUL) 3687 Builder.defineMacro("__PCLMUL__"); 3688 3689 if (HasLZCNT) 3690 Builder.defineMacro("__LZCNT__"); 3691 3692 if (HasRDRND) 3693 Builder.defineMacro("__RDRND__"); 3694 3695 if (HasFSGSBASE) 3696 Builder.defineMacro("__FSGSBASE__"); 3697 3698 if (HasBMI) 3699 Builder.defineMacro("__BMI__"); 3700 3701 if (HasBMI2) 3702 Builder.defineMacro("__BMI2__"); 3703 3704 if (HasPOPCNT) 3705 Builder.defineMacro("__POPCNT__"); 3706 3707 if (HasRTM) 3708 Builder.defineMacro("__RTM__"); 3709 3710 if (HasPRFCHW) 3711 Builder.defineMacro("__PRFCHW__"); 3712 3713 if (HasRDSEED) 3714 Builder.defineMacro("__RDSEED__"); 3715 3716 if (HasADX) 3717 Builder.defineMacro("__ADX__"); 3718 3719 if (HasTBM) 3720 Builder.defineMacro("__TBM__"); 3721 3722 if (HasMWAITX) 3723 Builder.defineMacro("__MWAITX__"); 3724 3725 switch (XOPLevel) { 3726 case XOP: 3727 Builder.defineMacro("__XOP__"); 3728 case FMA4: 3729 Builder.defineMacro("__FMA4__"); 3730 case SSE4A: 3731 Builder.defineMacro("__SSE4A__"); 3732 case NoXOP: 3733 break; 3734 } 3735 3736 if (HasFMA) 3737 Builder.defineMacro("__FMA__"); 3738 3739 if (HasF16C) 3740 Builder.defineMacro("__F16C__"); 3741 3742 if (HasAVX512CD) 3743 Builder.defineMacro("__AVX512CD__"); 3744 if (HasAVX512ER) 3745 Builder.defineMacro("__AVX512ER__"); 3746 if (HasAVX512PF) 3747 Builder.defineMacro("__AVX512PF__"); 3748 if (HasAVX512DQ) 3749 Builder.defineMacro("__AVX512DQ__"); 3750 if (HasAVX512BW) 3751 Builder.defineMacro("__AVX512BW__"); 3752 if (HasAVX512VL) 3753 Builder.defineMacro("__AVX512VL__"); 3754 if (HasAVX512VBMI) 3755 Builder.defineMacro("__AVX512VBMI__"); 3756 if (HasAVX512IFMA) 3757 Builder.defineMacro("__AVX512IFMA__"); 3758 3759 if (HasSHA) 3760 Builder.defineMacro("__SHA__"); 3761 3762 if (HasFXSR) 3763 Builder.defineMacro("__FXSR__"); 3764 if (HasXSAVE) 3765 Builder.defineMacro("__XSAVE__"); 3766 if (HasXSAVEOPT) 3767 Builder.defineMacro("__XSAVEOPT__"); 3768 if (HasXSAVEC) 3769 Builder.defineMacro("__XSAVEC__"); 3770 if (HasXSAVES) 3771 Builder.defineMacro("__XSAVES__"); 3772 if (HasPKU) 3773 Builder.defineMacro("__PKU__"); 3774 if (HasCX16) 3775 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3776 3777 // Each case falls through to the previous one here. 3778 switch (SSELevel) { 3779 case AVX512F: 3780 Builder.defineMacro("__AVX512F__"); 3781 case AVX2: 3782 Builder.defineMacro("__AVX2__"); 3783 case AVX: 3784 Builder.defineMacro("__AVX__"); 3785 case SSE42: 3786 Builder.defineMacro("__SSE4_2__"); 3787 case SSE41: 3788 Builder.defineMacro("__SSE4_1__"); 3789 case SSSE3: 3790 Builder.defineMacro("__SSSE3__"); 3791 case SSE3: 3792 Builder.defineMacro("__SSE3__"); 3793 case SSE2: 3794 Builder.defineMacro("__SSE2__"); 3795 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3796 case SSE1: 3797 Builder.defineMacro("__SSE__"); 3798 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3799 case NoSSE: 3800 break; 3801 } 3802 3803 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3804 switch (SSELevel) { 3805 case AVX512F: 3806 case AVX2: 3807 case AVX: 3808 case SSE42: 3809 case SSE41: 3810 case SSSE3: 3811 case SSE3: 3812 case SSE2: 3813 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3814 break; 3815 case SSE1: 3816 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3817 break; 3818 default: 3819 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3820 } 3821 } 3822 3823 // Each case falls through to the previous one here. 3824 switch (MMX3DNowLevel) { 3825 case AMD3DNowAthlon: 3826 Builder.defineMacro("__3dNOW_A__"); 3827 case AMD3DNow: 3828 Builder.defineMacro("__3dNOW__"); 3829 case MMX: 3830 Builder.defineMacro("__MMX__"); 3831 case NoMMX3DNow: 3832 break; 3833 } 3834 3835 if (CPU >= CK_i486) { 3836 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3837 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3838 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3839 } 3840 if (CPU >= CK_i586) 3841 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3842 } 3843 3844 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3845 return llvm::StringSwitch<bool>(Feature) 3846 .Case("aes", HasAES) 3847 .Case("avx", SSELevel >= AVX) 3848 .Case("avx2", SSELevel >= AVX2) 3849 .Case("avx512f", SSELevel >= AVX512F) 3850 .Case("avx512cd", HasAVX512CD) 3851 .Case("avx512er", HasAVX512ER) 3852 .Case("avx512pf", HasAVX512PF) 3853 .Case("avx512dq", HasAVX512DQ) 3854 .Case("avx512bw", HasAVX512BW) 3855 .Case("avx512vl", HasAVX512VL) 3856 .Case("avx512vbmi", HasAVX512VBMI) 3857 .Case("avx512ifma", HasAVX512IFMA) 3858 .Case("bmi", HasBMI) 3859 .Case("bmi2", HasBMI2) 3860 .Case("clflushopt", HasCLFLUSHOPT) 3861 .Case("clwb", HasCLWB) 3862 .Case("cx16", HasCX16) 3863 .Case("f16c", HasF16C) 3864 .Case("fma", HasFMA) 3865 .Case("fma4", XOPLevel >= FMA4) 3866 .Case("fsgsbase", HasFSGSBASE) 3867 .Case("fxsr", HasFXSR) 3868 .Case("lzcnt", HasLZCNT) 3869 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3870 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3871 .Case("mmx", MMX3DNowLevel >= MMX) 3872 .Case("movbe", HasMOVBE) 3873 .Case("mpx", HasMPX) 3874 .Case("pclmul", HasPCLMUL) 3875 .Case("pcommit", HasPCOMMIT) 3876 .Case("pku", HasPKU) 3877 .Case("popcnt", HasPOPCNT) 3878 .Case("prefetchwt1", HasPREFETCHWT1) 3879 .Case("prfchw", HasPRFCHW) 3880 .Case("rdrnd", HasRDRND) 3881 .Case("rdseed", HasRDSEED) 3882 .Case("rtm", HasRTM) 3883 .Case("sgx", HasSGX) 3884 .Case("sha", HasSHA) 3885 .Case("sse", SSELevel >= SSE1) 3886 .Case("sse2", SSELevel >= SSE2) 3887 .Case("sse3", SSELevel >= SSE3) 3888 .Case("ssse3", SSELevel >= SSSE3) 3889 .Case("sse4.1", SSELevel >= SSE41) 3890 .Case("sse4.2", SSELevel >= SSE42) 3891 .Case("sse4a", XOPLevel >= SSE4A) 3892 .Case("tbm", HasTBM) 3893 .Case("umip", HasUMIP) 3894 .Case("x86", true) 3895 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3896 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3897 .Case("xop", XOPLevel >= XOP) 3898 .Case("xsave", HasXSAVE) 3899 .Case("xsavec", HasXSAVEC) 3900 .Case("xsaves", HasXSAVES) 3901 .Case("xsaveopt", HasXSAVEOPT) 3902 .Default(false); 3903 } 3904 3905 // We can't use a generic validation scheme for the features accepted here 3906 // versus subtarget features accepted in the target attribute because the 3907 // bitfield structure that's initialized in the runtime only supports the 3908 // below currently rather than the full range of subtarget features. (See 3909 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3910 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3911 return llvm::StringSwitch<bool>(FeatureStr) 3912 .Case("cmov", true) 3913 .Case("mmx", true) 3914 .Case("popcnt", true) 3915 .Case("sse", true) 3916 .Case("sse2", true) 3917 .Case("sse3", true) 3918 .Case("ssse3", true) 3919 .Case("sse4.1", true) 3920 .Case("sse4.2", true) 3921 .Case("avx", true) 3922 .Case("avx2", true) 3923 .Case("sse4a", true) 3924 .Case("fma4", true) 3925 .Case("xop", true) 3926 .Case("fma", true) 3927 .Case("avx512f", true) 3928 .Case("bmi", true) 3929 .Case("bmi2", true) 3930 .Case("aes", true) 3931 .Case("pclmul", true) 3932 .Case("avx512vl", true) 3933 .Case("avx512bw", true) 3934 .Case("avx512dq", true) 3935 .Case("avx512cd", true) 3936 .Case("avx512er", true) 3937 .Case("avx512pf", true) 3938 .Case("avx512vbmi", true) 3939 .Case("avx512ifma", true) 3940 .Default(false); 3941 } 3942 3943 bool 3944 X86TargetInfo::validateAsmConstraint(const char *&Name, 3945 TargetInfo::ConstraintInfo &Info) const { 3946 switch (*Name) { 3947 default: return false; 3948 // Constant constraints. 3949 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3950 // instructions. 3951 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3952 // x86_64 instructions. 3953 case 's': 3954 Info.setRequiresImmediate(); 3955 return true; 3956 case 'I': 3957 Info.setRequiresImmediate(0, 31); 3958 return true; 3959 case 'J': 3960 Info.setRequiresImmediate(0, 63); 3961 return true; 3962 case 'K': 3963 Info.setRequiresImmediate(-128, 127); 3964 return true; 3965 case 'L': 3966 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3967 return true; 3968 case 'M': 3969 Info.setRequiresImmediate(0, 3); 3970 return true; 3971 case 'N': 3972 Info.setRequiresImmediate(0, 255); 3973 return true; 3974 case 'O': 3975 Info.setRequiresImmediate(0, 127); 3976 return true; 3977 // Register constraints. 3978 case 'Y': // 'Y' is the first character for several 2-character constraints. 3979 // Shift the pointer to the second character of the constraint. 3980 Name++; 3981 switch (*Name) { 3982 default: 3983 return false; 3984 case '0': // First SSE register. 3985 case 't': // Any SSE register, when SSE2 is enabled. 3986 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3987 case 'm': // Any MMX register, when inter-unit moves enabled. 3988 Info.setAllowsRegister(); 3989 return true; 3990 } 3991 case 'f': // Any x87 floating point stack register. 3992 // Constraint 'f' cannot be used for output operands. 3993 if (Info.ConstraintStr[0] == '=') 3994 return false; 3995 Info.setAllowsRegister(); 3996 return true; 3997 case 'a': // eax. 3998 case 'b': // ebx. 3999 case 'c': // ecx. 4000 case 'd': // edx. 4001 case 'S': // esi. 4002 case 'D': // edi. 4003 case 'A': // edx:eax. 4004 case 't': // Top of floating point stack. 4005 case 'u': // Second from top of floating point stack. 4006 case 'q': // Any register accessible as [r]l: a, b, c, and d. 4007 case 'y': // Any MMX register. 4008 case 'x': // Any SSE register. 4009 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 4010 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 4011 case 'l': // "Index" registers: any general register that can be used as an 4012 // index in a base+index memory access. 4013 Info.setAllowsRegister(); 4014 return true; 4015 // Floating point constant constraints. 4016 case 'C': // SSE floating point constant. 4017 case 'G': // x87 floating point constant. 4018 return true; 4019 } 4020 } 4021 4022 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 4023 unsigned Size) const { 4024 // Strip off constraint modifiers. 4025 while (Constraint[0] == '=' || 4026 Constraint[0] == '+' || 4027 Constraint[0] == '&') 4028 Constraint = Constraint.substr(1); 4029 4030 return validateOperandSize(Constraint, Size); 4031 } 4032 4033 bool X86TargetInfo::validateInputSize(StringRef Constraint, 4034 unsigned Size) const { 4035 return validateOperandSize(Constraint, Size); 4036 } 4037 4038 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 4039 unsigned Size) const { 4040 switch (Constraint[0]) { 4041 default: break; 4042 case 'y': 4043 return Size <= 64; 4044 case 'f': 4045 case 't': 4046 case 'u': 4047 return Size <= 128; 4048 case 'x': 4049 if (SSELevel >= AVX512F) 4050 // 512-bit zmm registers can be used if target supports AVX512F. 4051 return Size <= 512U; 4052 else if (SSELevel >= AVX) 4053 // 256-bit ymm registers can be used if target supports AVX. 4054 return Size <= 256U; 4055 return Size <= 128U; 4056 case 'Y': 4057 // 'Y' is the first character for several 2-character constraints. 4058 switch (Constraint[1]) { 4059 default: break; 4060 case 'm': 4061 // 'Ym' is synonymous with 'y'. 4062 return Size <= 64; 4063 case 'i': 4064 case 't': 4065 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4066 if (SSELevel >= AVX512F) 4067 return Size <= 512U; 4068 else if (SSELevel >= AVX) 4069 return Size <= 256U; 4070 return SSELevel >= SSE2 && Size <= 128U; 4071 } 4072 4073 } 4074 4075 return true; 4076 } 4077 4078 std::string 4079 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4080 switch (*Constraint) { 4081 case 'a': return std::string("{ax}"); 4082 case 'b': return std::string("{bx}"); 4083 case 'c': return std::string("{cx}"); 4084 case 'd': return std::string("{dx}"); 4085 case 'S': return std::string("{si}"); 4086 case 'D': return std::string("{di}"); 4087 case 'p': // address 4088 return std::string("im"); 4089 case 't': // top of floating point stack. 4090 return std::string("{st}"); 4091 case 'u': // second from top of floating point stack. 4092 return std::string("{st(1)}"); // second from top of floating point stack. 4093 default: 4094 return std::string(1, *Constraint); 4095 } 4096 } 4097 4098 // X86-32 generic target 4099 class X86_32TargetInfo : public X86TargetInfo { 4100 public: 4101 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4102 : X86TargetInfo(Triple, Opts) { 4103 DoubleAlign = LongLongAlign = 32; 4104 LongDoubleWidth = 96; 4105 LongDoubleAlign = 32; 4106 SuitableAlign = 128; 4107 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4108 SizeType = UnsignedInt; 4109 PtrDiffType = SignedInt; 4110 IntPtrType = SignedInt; 4111 RegParmMax = 3; 4112 4113 // Use fpret for all types. 4114 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4115 (1 << TargetInfo::Double) | 4116 (1 << TargetInfo::LongDouble)); 4117 4118 // x86-32 has atomics up to 8 bytes 4119 // FIXME: Check that we actually have cmpxchg8b before setting 4120 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4121 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4122 } 4123 BuiltinVaListKind getBuiltinVaListKind() const override { 4124 return TargetInfo::CharPtrBuiltinVaList; 4125 } 4126 4127 int getEHDataRegisterNumber(unsigned RegNo) const override { 4128 if (RegNo == 0) return 0; 4129 if (RegNo == 1) return 2; 4130 return -1; 4131 } 4132 bool validateOperandSize(StringRef Constraint, 4133 unsigned Size) const override { 4134 switch (Constraint[0]) { 4135 default: break; 4136 case 'R': 4137 case 'q': 4138 case 'Q': 4139 case 'a': 4140 case 'b': 4141 case 'c': 4142 case 'd': 4143 case 'S': 4144 case 'D': 4145 return Size <= 32; 4146 case 'A': 4147 return Size <= 64; 4148 } 4149 4150 return X86TargetInfo::validateOperandSize(Constraint, Size); 4151 } 4152 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4153 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 4154 Builtin::FirstTSBuiltin + 1); 4155 } 4156 }; 4157 4158 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4159 public: 4160 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4161 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4162 4163 unsigned getFloatEvalMethod() const override { 4164 unsigned Major, Minor, Micro; 4165 getTriple().getOSVersion(Major, Minor, Micro); 4166 // New NetBSD uses the default rounding mode. 4167 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4168 return X86_32TargetInfo::getFloatEvalMethod(); 4169 // NetBSD before 6.99.26 defaults to "double" rounding. 4170 return 1; 4171 } 4172 }; 4173 4174 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4175 public: 4176 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4177 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4178 SizeType = UnsignedLong; 4179 IntPtrType = SignedLong; 4180 PtrDiffType = SignedLong; 4181 } 4182 }; 4183 4184 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4185 public: 4186 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4187 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4188 SizeType = UnsignedLong; 4189 IntPtrType = SignedLong; 4190 PtrDiffType = SignedLong; 4191 } 4192 }; 4193 4194 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4195 public: 4196 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4197 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4198 LongDoubleWidth = 128; 4199 LongDoubleAlign = 128; 4200 SuitableAlign = 128; 4201 MaxVectorAlign = 256; 4202 // The watchOS simulator uses the builtin bool type for Objective-C. 4203 llvm::Triple T = llvm::Triple(Triple); 4204 if (T.isWatchOS()) 4205 UseSignedCharForObjCBool = false; 4206 SizeType = UnsignedLong; 4207 IntPtrType = SignedLong; 4208 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4209 HasAlignMac68kSupport = true; 4210 } 4211 4212 bool handleTargetFeatures(std::vector<std::string> &Features, 4213 DiagnosticsEngine &Diags) override { 4214 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4215 Diags)) 4216 return false; 4217 // We now know the features we have: we can decide how to align vectors. 4218 MaxVectorAlign = 4219 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4220 return true; 4221 } 4222 }; 4223 4224 // x86-32 Windows target 4225 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4226 public: 4227 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4228 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4229 WCharType = UnsignedShort; 4230 DoubleAlign = LongLongAlign = 64; 4231 bool IsWinCOFF = 4232 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4233 resetDataLayout(IsWinCOFF 4234 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4235 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4236 } 4237 void getTargetDefines(const LangOptions &Opts, 4238 MacroBuilder &Builder) const override { 4239 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4240 } 4241 }; 4242 4243 // x86-32 Windows Visual Studio target 4244 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4245 public: 4246 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4247 const TargetOptions &Opts) 4248 : WindowsX86_32TargetInfo(Triple, Opts) { 4249 LongDoubleWidth = LongDoubleAlign = 64; 4250 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4251 } 4252 void getTargetDefines(const LangOptions &Opts, 4253 MacroBuilder &Builder) const override { 4254 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4255 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4256 // The value of the following reflects processor type. 4257 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4258 // We lost the original triple, so we use the default. 4259 Builder.defineMacro("_M_IX86", "600"); 4260 } 4261 }; 4262 4263 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4264 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4265 // supports __declspec natively under -fms-extensions, but we define a no-op 4266 // __declspec macro anyway for pre-processor compatibility. 4267 if (Opts.MicrosoftExt) 4268 Builder.defineMacro("__declspec", "__declspec"); 4269 else 4270 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4271 4272 if (!Opts.MicrosoftExt) { 4273 // Provide macros for all the calling convention keywords. Provide both 4274 // single and double underscore prefixed variants. These are available on 4275 // x64 as well as x86, even though they have no effect. 4276 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4277 for (const char *CC : CCs) { 4278 std::string GCCSpelling = "__attribute__((__"; 4279 GCCSpelling += CC; 4280 GCCSpelling += "__))"; 4281 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4282 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4283 } 4284 } 4285 } 4286 4287 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4288 Builder.defineMacro("__MSVCRT__"); 4289 Builder.defineMacro("__MINGW32__"); 4290 addCygMingDefines(Opts, Builder); 4291 } 4292 4293 // x86-32 MinGW target 4294 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4295 public: 4296 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4297 : WindowsX86_32TargetInfo(Triple, Opts) {} 4298 void getTargetDefines(const LangOptions &Opts, 4299 MacroBuilder &Builder) const override { 4300 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4301 DefineStd(Builder, "WIN32", Opts); 4302 DefineStd(Builder, "WINNT", Opts); 4303 Builder.defineMacro("_X86_"); 4304 addMinGWDefines(Opts, Builder); 4305 } 4306 }; 4307 4308 // x86-32 Cygwin target 4309 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4310 public: 4311 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4312 : X86_32TargetInfo(Triple, Opts) { 4313 WCharType = UnsignedShort; 4314 DoubleAlign = LongLongAlign = 64; 4315 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4316 } 4317 void getTargetDefines(const LangOptions &Opts, 4318 MacroBuilder &Builder) const override { 4319 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4320 Builder.defineMacro("_X86_"); 4321 Builder.defineMacro("__CYGWIN__"); 4322 Builder.defineMacro("__CYGWIN32__"); 4323 addCygMingDefines(Opts, Builder); 4324 DefineStd(Builder, "unix", Opts); 4325 if (Opts.CPlusPlus) 4326 Builder.defineMacro("_GNU_SOURCE"); 4327 } 4328 }; 4329 4330 // x86-32 Haiku target 4331 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4332 public: 4333 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4334 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4335 } 4336 void getTargetDefines(const LangOptions &Opts, 4337 MacroBuilder &Builder) const override { 4338 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4339 Builder.defineMacro("__INTEL__"); 4340 } 4341 }; 4342 4343 // X86-32 MCU target 4344 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4345 public: 4346 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4347 : X86_32TargetInfo(Triple, Opts) { 4348 LongDoubleWidth = 64; 4349 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4350 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4351 WIntType = UnsignedInt; 4352 } 4353 4354 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4355 // On MCU we support only C calling convention. 4356 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4357 } 4358 4359 void getTargetDefines(const LangOptions &Opts, 4360 MacroBuilder &Builder) const override { 4361 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4362 Builder.defineMacro("__iamcu"); 4363 Builder.defineMacro("__iamcu__"); 4364 } 4365 4366 bool allowsLargerPreferedTypeAlignment() const override { 4367 return false; 4368 } 4369 }; 4370 4371 // RTEMS Target 4372 template<typename Target> 4373 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4374 protected: 4375 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4376 MacroBuilder &Builder) const override { 4377 // RTEMS defines; list based off of gcc output 4378 4379 Builder.defineMacro("__rtems__"); 4380 Builder.defineMacro("__ELF__"); 4381 } 4382 4383 public: 4384 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4385 : OSTargetInfo<Target>(Triple, Opts) { 4386 switch (Triple.getArch()) { 4387 default: 4388 case llvm::Triple::x86: 4389 // this->MCountName = ".mcount"; 4390 break; 4391 case llvm::Triple::mips: 4392 case llvm::Triple::mipsel: 4393 case llvm::Triple::ppc: 4394 case llvm::Triple::ppc64: 4395 case llvm::Triple::ppc64le: 4396 // this->MCountName = "_mcount"; 4397 break; 4398 case llvm::Triple::arm: 4399 // this->MCountName = "__mcount"; 4400 break; 4401 } 4402 } 4403 }; 4404 4405 // x86-32 RTEMS target 4406 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4407 public: 4408 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4409 : X86_32TargetInfo(Triple, Opts) { 4410 SizeType = UnsignedLong; 4411 IntPtrType = SignedLong; 4412 PtrDiffType = SignedLong; 4413 } 4414 void getTargetDefines(const LangOptions &Opts, 4415 MacroBuilder &Builder) const override { 4416 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4417 Builder.defineMacro("__INTEL__"); 4418 Builder.defineMacro("__rtems__"); 4419 } 4420 }; 4421 4422 // x86-64 generic target 4423 class X86_64TargetInfo : public X86TargetInfo { 4424 public: 4425 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4426 : X86TargetInfo(Triple, Opts) { 4427 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4428 bool IsWinCOFF = 4429 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4430 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4431 LongDoubleWidth = 128; 4432 LongDoubleAlign = 128; 4433 LargeArrayMinWidth = 128; 4434 LargeArrayAlign = 128; 4435 SuitableAlign = 128; 4436 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4437 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4438 IntPtrType = IsX32 ? SignedInt : SignedLong; 4439 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4440 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4441 RegParmMax = 6; 4442 4443 // Pointers are 32-bit in x32. 4444 resetDataLayout(IsX32 4445 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4446 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4447 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4448 4449 // Use fpret only for long double. 4450 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4451 4452 // Use fp2ret for _Complex long double. 4453 ComplexLongDoubleUsesFP2Ret = true; 4454 4455 // Make __builtin_ms_va_list available. 4456 HasBuiltinMSVaList = true; 4457 4458 // x86-64 has atomics up to 16 bytes. 4459 MaxAtomicPromoteWidth = 128; 4460 MaxAtomicInlineWidth = 128; 4461 } 4462 BuiltinVaListKind getBuiltinVaListKind() const override { 4463 return TargetInfo::X86_64ABIBuiltinVaList; 4464 } 4465 4466 int getEHDataRegisterNumber(unsigned RegNo) const override { 4467 if (RegNo == 0) return 0; 4468 if (RegNo == 1) return 1; 4469 return -1; 4470 } 4471 4472 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4473 switch (CC) { 4474 case CC_C: 4475 case CC_Swift: 4476 case CC_X86VectorCall: 4477 case CC_IntelOclBicc: 4478 case CC_X86_64Win64: 4479 case CC_PreserveMost: 4480 case CC_PreserveAll: 4481 return CCCR_OK; 4482 default: 4483 return CCCR_Warning; 4484 } 4485 } 4486 4487 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4488 return CC_C; 4489 } 4490 4491 // for x32 we need it here explicitly 4492 bool hasInt128Type() const override { return true; } 4493 unsigned getUnwindWordWidth() const override { return 64; } 4494 unsigned getRegisterWidth() const override { return 64; } 4495 4496 bool validateGlobalRegisterVariable(StringRef RegName, 4497 unsigned RegSize, 4498 bool &HasSizeMismatch) const override { 4499 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4500 // handle. 4501 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4502 // Check that the register size is 64-bit. 4503 HasSizeMismatch = RegSize != 64; 4504 return true; 4505 } 4506 4507 // Check if the register is a 32-bit register the backend can handle. 4508 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4509 HasSizeMismatch); 4510 } 4511 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4512 return llvm::makeArrayRef(BuiltinInfoX86, 4513 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 4514 } 4515 }; 4516 4517 // x86-64 Windows target 4518 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4519 public: 4520 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4521 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4522 WCharType = UnsignedShort; 4523 LongWidth = LongAlign = 32; 4524 DoubleAlign = LongLongAlign = 64; 4525 IntMaxType = SignedLongLong; 4526 Int64Type = SignedLongLong; 4527 SizeType = UnsignedLongLong; 4528 PtrDiffType = SignedLongLong; 4529 IntPtrType = SignedLongLong; 4530 } 4531 4532 void getTargetDefines(const LangOptions &Opts, 4533 MacroBuilder &Builder) const override { 4534 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4535 Builder.defineMacro("_WIN64"); 4536 } 4537 4538 BuiltinVaListKind getBuiltinVaListKind() const override { 4539 return TargetInfo::CharPtrBuiltinVaList; 4540 } 4541 4542 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4543 switch (CC) { 4544 case CC_X86StdCall: 4545 case CC_X86ThisCall: 4546 case CC_X86FastCall: 4547 return CCCR_Ignore; 4548 case CC_C: 4549 case CC_X86VectorCall: 4550 case CC_IntelOclBicc: 4551 case CC_X86_64SysV: 4552 return CCCR_OK; 4553 default: 4554 return CCCR_Warning; 4555 } 4556 } 4557 }; 4558 4559 // x86-64 Windows Visual Studio target 4560 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4561 public: 4562 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4563 const TargetOptions &Opts) 4564 : WindowsX86_64TargetInfo(Triple, Opts) { 4565 LongDoubleWidth = LongDoubleAlign = 64; 4566 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4567 } 4568 void getTargetDefines(const LangOptions &Opts, 4569 MacroBuilder &Builder) const override { 4570 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4571 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4572 Builder.defineMacro("_M_X64", "100"); 4573 Builder.defineMacro("_M_AMD64", "100"); 4574 } 4575 }; 4576 4577 // x86-64 MinGW target 4578 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4579 public: 4580 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4581 : WindowsX86_64TargetInfo(Triple, Opts) { 4582 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4583 // with x86 FP ops. Weird. 4584 LongDoubleWidth = LongDoubleAlign = 128; 4585 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4586 } 4587 4588 void getTargetDefines(const LangOptions &Opts, 4589 MacroBuilder &Builder) const override { 4590 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4591 DefineStd(Builder, "WIN64", Opts); 4592 Builder.defineMacro("__MINGW64__"); 4593 addMinGWDefines(Opts, Builder); 4594 4595 // GCC defines this macro when it is using __gxx_personality_seh0. 4596 if (!Opts.SjLjExceptions) 4597 Builder.defineMacro("__SEH__"); 4598 } 4599 }; 4600 4601 // x86-64 Cygwin target 4602 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4603 public: 4604 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4605 : X86_64TargetInfo(Triple, Opts) { 4606 TLSSupported = false; 4607 WCharType = UnsignedShort; 4608 } 4609 void getTargetDefines(const LangOptions &Opts, 4610 MacroBuilder &Builder) const override { 4611 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4612 Builder.defineMacro("__x86_64__"); 4613 Builder.defineMacro("__CYGWIN__"); 4614 Builder.defineMacro("__CYGWIN64__"); 4615 addCygMingDefines(Opts, Builder); 4616 DefineStd(Builder, "unix", Opts); 4617 if (Opts.CPlusPlus) 4618 Builder.defineMacro("_GNU_SOURCE"); 4619 4620 // GCC defines this macro when it is using __gxx_personality_seh0. 4621 if (!Opts.SjLjExceptions) 4622 Builder.defineMacro("__SEH__"); 4623 } 4624 }; 4625 4626 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4627 public: 4628 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4629 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4630 Int64Type = SignedLongLong; 4631 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4632 llvm::Triple T = llvm::Triple(Triple); 4633 if (T.isiOS()) 4634 UseSignedCharForObjCBool = false; 4635 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4636 } 4637 4638 bool handleTargetFeatures(std::vector<std::string> &Features, 4639 DiagnosticsEngine &Diags) override { 4640 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4641 Diags)) 4642 return false; 4643 // We now know the features we have: we can decide how to align vectors. 4644 MaxVectorAlign = 4645 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4646 return true; 4647 } 4648 }; 4649 4650 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4651 public: 4652 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4653 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4654 IntMaxType = SignedLongLong; 4655 Int64Type = SignedLongLong; 4656 } 4657 }; 4658 4659 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4660 public: 4661 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4662 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4663 IntMaxType = SignedLongLong; 4664 Int64Type = SignedLongLong; 4665 } 4666 }; 4667 4668 class ARMTargetInfo : public TargetInfo { 4669 // Possible FPU choices. 4670 enum FPUMode { 4671 VFP2FPU = (1 << 0), 4672 VFP3FPU = (1 << 1), 4673 VFP4FPU = (1 << 2), 4674 NeonFPU = (1 << 3), 4675 FPARMV8 = (1 << 4) 4676 }; 4677 4678 // Possible HWDiv features. 4679 enum HWDivMode { 4680 HWDivThumb = (1 << 0), 4681 HWDivARM = (1 << 1) 4682 }; 4683 4684 static bool FPUModeIsVFP(FPUMode Mode) { 4685 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4686 } 4687 4688 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4689 static const char * const GCCRegNames[]; 4690 4691 std::string ABI, CPU; 4692 4693 StringRef CPUProfile; 4694 StringRef CPUAttr; 4695 4696 enum { 4697 FP_Default, 4698 FP_VFP, 4699 FP_Neon 4700 } FPMath; 4701 4702 unsigned ArchISA; 4703 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4704 unsigned ArchProfile; 4705 unsigned ArchVersion; 4706 4707 unsigned FPU : 5; 4708 4709 unsigned IsAAPCS : 1; 4710 unsigned HWDiv : 2; 4711 4712 // Initialized via features. 4713 unsigned SoftFloat : 1; 4714 unsigned SoftFloatABI : 1; 4715 4716 unsigned CRC : 1; 4717 unsigned Crypto : 1; 4718 unsigned DSP : 1; 4719 unsigned Unaligned : 1; 4720 4721 enum { 4722 LDREX_B = (1 << 0), /// byte (8-bit) 4723 LDREX_H = (1 << 1), /// half (16-bit) 4724 LDREX_W = (1 << 2), /// word (32-bit) 4725 LDREX_D = (1 << 3), /// double (64-bit) 4726 }; 4727 4728 uint32_t LDREX; 4729 4730 // ACLE 6.5.1 Hardware floating point 4731 enum { 4732 HW_FP_HP = (1 << 1), /// half (16-bit) 4733 HW_FP_SP = (1 << 2), /// single (32-bit) 4734 HW_FP_DP = (1 << 3), /// double (64-bit) 4735 }; 4736 uint32_t HW_FP; 4737 4738 static const Builtin::Info BuiltinInfo[]; 4739 4740 void setABIAAPCS() { 4741 IsAAPCS = true; 4742 4743 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4744 const llvm::Triple &T = getTriple(); 4745 4746 // size_t is unsigned long on MachO-derived environments, NetBSD, 4747 // OpenBSD and Bitrig. 4748 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4749 T.getOS() == llvm::Triple::OpenBSD || 4750 T.getOS() == llvm::Triple::Bitrig) 4751 SizeType = UnsignedLong; 4752 else 4753 SizeType = UnsignedInt; 4754 4755 switch (T.getOS()) { 4756 case llvm::Triple::NetBSD: 4757 case llvm::Triple::OpenBSD: 4758 WCharType = SignedInt; 4759 break; 4760 case llvm::Triple::Win32: 4761 WCharType = UnsignedShort; 4762 break; 4763 case llvm::Triple::Linux: 4764 default: 4765 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4766 WCharType = UnsignedInt; 4767 break; 4768 } 4769 4770 UseBitFieldTypeAlignment = true; 4771 4772 ZeroLengthBitfieldBoundary = 0; 4773 4774 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4775 // so set preferred for small types to 32. 4776 if (T.isOSBinFormatMachO()) { 4777 resetDataLayout(BigEndian 4778 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4779 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4780 } else if (T.isOSWindows()) { 4781 assert(!BigEndian && "Windows on ARM does not support big endian"); 4782 resetDataLayout("e" 4783 "-m:w" 4784 "-p:32:32" 4785 "-i64:64" 4786 "-v128:64:128" 4787 "-a:0:32" 4788 "-n32" 4789 "-S64"); 4790 } else if (T.isOSNaCl()) { 4791 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4792 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4793 } else { 4794 resetDataLayout(BigEndian 4795 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4796 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4797 } 4798 4799 // FIXME: Enumerated types are variable width in straight AAPCS. 4800 } 4801 4802 void setABIAPCS(bool IsAAPCS16) { 4803 const llvm::Triple &T = getTriple(); 4804 4805 IsAAPCS = false; 4806 4807 if (IsAAPCS16) 4808 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4809 else 4810 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4811 4812 // size_t is unsigned int on FreeBSD. 4813 if (T.getOS() == llvm::Triple::FreeBSD) 4814 SizeType = UnsignedInt; 4815 else 4816 SizeType = UnsignedLong; 4817 4818 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4819 WCharType = SignedInt; 4820 4821 // Do not respect the alignment of bit-field types when laying out 4822 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4823 UseBitFieldTypeAlignment = false; 4824 4825 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4826 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4827 /// gcc. 4828 ZeroLengthBitfieldBoundary = 32; 4829 4830 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4831 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4832 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4833 } else if (T.isOSBinFormatMachO()) 4834 resetDataLayout( 4835 BigEndian 4836 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4837 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4838 else 4839 resetDataLayout( 4840 BigEndian 4841 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4842 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4843 4844 // FIXME: Override "preferred align" for double and long long. 4845 } 4846 4847 void setArchInfo() { 4848 StringRef ArchName = getTriple().getArchName(); 4849 4850 ArchISA = llvm::ARM::parseArchISA(ArchName); 4851 CPU = llvm::ARM::getDefaultCPU(ArchName); 4852 unsigned AK = llvm::ARM::parseArch(ArchName); 4853 if (AK != llvm::ARM::AK_INVALID) 4854 ArchKind = AK; 4855 setArchInfo(ArchKind); 4856 } 4857 4858 void setArchInfo(unsigned Kind) { 4859 StringRef SubArch; 4860 4861 // cache TargetParser info 4862 ArchKind = Kind; 4863 SubArch = llvm::ARM::getSubArch(ArchKind); 4864 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4865 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4866 4867 // cache CPU related strings 4868 CPUAttr = getCPUAttr(); 4869 CPUProfile = getCPUProfile(); 4870 } 4871 4872 void setAtomic() { 4873 // when triple does not specify a sub arch, 4874 // then we are not using inline atomics 4875 bool ShouldUseInlineAtomic = 4876 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4877 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4878 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4879 if (ArchProfile == llvm::ARM::PK_M) { 4880 MaxAtomicPromoteWidth = 32; 4881 if (ShouldUseInlineAtomic) 4882 MaxAtomicInlineWidth = 32; 4883 } 4884 else { 4885 MaxAtomicPromoteWidth = 64; 4886 if (ShouldUseInlineAtomic) 4887 MaxAtomicInlineWidth = 64; 4888 } 4889 } 4890 4891 bool isThumb() const { 4892 return (ArchISA == llvm::ARM::IK_THUMB); 4893 } 4894 4895 bool supportsThumb() const { 4896 return CPUAttr.count('T') || ArchVersion >= 6; 4897 } 4898 4899 bool supportsThumb2() const { 4900 return CPUAttr.equals("6T2") || 4901 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 4902 } 4903 4904 StringRef getCPUAttr() const { 4905 // For most sub-arches, the build attribute CPU name is enough. 4906 // For Cortex variants, it's slightly different. 4907 switch(ArchKind) { 4908 default: 4909 return llvm::ARM::getCPUAttr(ArchKind); 4910 case llvm::ARM::AK_ARMV6M: 4911 return "6M"; 4912 case llvm::ARM::AK_ARMV7S: 4913 return "7S"; 4914 case llvm::ARM::AK_ARMV7A: 4915 return "7A"; 4916 case llvm::ARM::AK_ARMV7R: 4917 return "7R"; 4918 case llvm::ARM::AK_ARMV7M: 4919 return "7M"; 4920 case llvm::ARM::AK_ARMV7EM: 4921 return "7EM"; 4922 case llvm::ARM::AK_ARMV8A: 4923 return "8A"; 4924 case llvm::ARM::AK_ARMV8_1A: 4925 return "8_1A"; 4926 case llvm::ARM::AK_ARMV8_2A: 4927 return "8_2A"; 4928 case llvm::ARM::AK_ARMV8MBaseline: 4929 return "8M_BASE"; 4930 case llvm::ARM::AK_ARMV8MMainline: 4931 return "8M_MAIN"; 4932 case llvm::ARM::AK_ARMV8R: 4933 return "8R"; 4934 } 4935 } 4936 4937 StringRef getCPUProfile() const { 4938 switch(ArchProfile) { 4939 case llvm::ARM::PK_A: 4940 return "A"; 4941 case llvm::ARM::PK_R: 4942 return "R"; 4943 case llvm::ARM::PK_M: 4944 return "M"; 4945 default: 4946 return ""; 4947 } 4948 } 4949 4950 public: 4951 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4952 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 4953 HW_FP(0) { 4954 4955 switch (getTriple().getOS()) { 4956 case llvm::Triple::NetBSD: 4957 case llvm::Triple::OpenBSD: 4958 PtrDiffType = SignedLong; 4959 break; 4960 default: 4961 PtrDiffType = SignedInt; 4962 break; 4963 } 4964 4965 // Cache arch related info. 4966 setArchInfo(); 4967 4968 // {} in inline assembly are neon specifiers, not assembly variant 4969 // specifiers. 4970 NoAsmVariants = true; 4971 4972 // FIXME: This duplicates code from the driver that sets the -target-abi 4973 // option - this code is used if -target-abi isn't passed and should 4974 // be unified in some way. 4975 if (Triple.isOSBinFormatMachO()) { 4976 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4977 // the frontend matches that. 4978 if (Triple.getEnvironment() == llvm::Triple::EABI || 4979 Triple.getOS() == llvm::Triple::UnknownOS || 4980 ArchProfile == llvm::ARM::PK_M) { 4981 setABI("aapcs"); 4982 } else if (Triple.isWatchABI()) { 4983 setABI("aapcs16"); 4984 } else { 4985 setABI("apcs-gnu"); 4986 } 4987 } else if (Triple.isOSWindows()) { 4988 // FIXME: this is invalid for WindowsCE 4989 setABI("aapcs"); 4990 } else { 4991 // Select the default based on the platform. 4992 switch (Triple.getEnvironment()) { 4993 case llvm::Triple::Android: 4994 case llvm::Triple::GNUEABI: 4995 case llvm::Triple::GNUEABIHF: 4996 case llvm::Triple::MuslEABI: 4997 case llvm::Triple::MuslEABIHF: 4998 setABI("aapcs-linux"); 4999 break; 5000 case llvm::Triple::EABIHF: 5001 case llvm::Triple::EABI: 5002 setABI("aapcs"); 5003 break; 5004 case llvm::Triple::GNU: 5005 setABI("apcs-gnu"); 5006 break; 5007 default: 5008 if (Triple.getOS() == llvm::Triple::NetBSD) 5009 setABI("apcs-gnu"); 5010 else 5011 setABI("aapcs"); 5012 break; 5013 } 5014 } 5015 5016 // ARM targets default to using the ARM C++ ABI. 5017 TheCXXABI.set(TargetCXXABI::GenericARM); 5018 5019 // ARM has atomics up to 8 bytes 5020 setAtomic(); 5021 5022 // Do force alignment of members that follow zero length bitfields. If 5023 // the alignment of the zero-length bitfield is greater than the member 5024 // that follows it, `bar', `bar' will be aligned as the type of the 5025 // zero length bitfield. 5026 UseZeroLengthBitfieldAlignment = true; 5027 5028 if (Triple.getOS() == llvm::Triple::Linux || 5029 Triple.getOS() == llvm::Triple::UnknownOS) 5030 this->MCountName = 5031 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 5032 } 5033 5034 StringRef getABI() const override { return ABI; } 5035 5036 bool setABI(const std::string &Name) override { 5037 ABI = Name; 5038 5039 // The defaults (above) are for AAPCS, check if we need to change them. 5040 // 5041 // FIXME: We need support for -meabi... we could just mangle it into the 5042 // name. 5043 if (Name == "apcs-gnu" || Name == "aapcs16") { 5044 setABIAPCS(Name == "aapcs16"); 5045 return true; 5046 } 5047 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 5048 setABIAAPCS(); 5049 return true; 5050 } 5051 return false; 5052 } 5053 5054 // FIXME: This should be based on Arch attributes, not CPU names. 5055 bool 5056 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5057 StringRef CPU, 5058 const std::vector<std::string> &FeaturesVec) const override { 5059 5060 std::vector<StringRef> TargetFeatures; 5061 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 5062 5063 // get default FPU features 5064 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 5065 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 5066 5067 // get default Extension features 5068 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 5069 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 5070 5071 for (auto Feature : TargetFeatures) 5072 if (Feature[0] == '+') 5073 Features[Feature.drop_front(1)] = true; 5074 5075 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5076 } 5077 5078 bool handleTargetFeatures(std::vector<std::string> &Features, 5079 DiagnosticsEngine &Diags) override { 5080 FPU = 0; 5081 CRC = 0; 5082 Crypto = 0; 5083 DSP = 0; 5084 Unaligned = 1; 5085 SoftFloat = SoftFloatABI = false; 5086 HWDiv = 0; 5087 5088 // This does not diagnose illegal cases like having both 5089 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5090 uint32_t HW_FP_remove = 0; 5091 for (const auto &Feature : Features) { 5092 if (Feature == "+soft-float") { 5093 SoftFloat = true; 5094 } else if (Feature == "+soft-float-abi") { 5095 SoftFloatABI = true; 5096 } else if (Feature == "+vfp2") { 5097 FPU |= VFP2FPU; 5098 HW_FP |= HW_FP_SP | HW_FP_DP; 5099 } else if (Feature == "+vfp3") { 5100 FPU |= VFP3FPU; 5101 HW_FP |= HW_FP_SP | HW_FP_DP; 5102 } else if (Feature == "+vfp4") { 5103 FPU |= VFP4FPU; 5104 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5105 } else if (Feature == "+fp-armv8") { 5106 FPU |= FPARMV8; 5107 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5108 } else if (Feature == "+neon") { 5109 FPU |= NeonFPU; 5110 HW_FP |= HW_FP_SP | HW_FP_DP; 5111 } else if (Feature == "+hwdiv") { 5112 HWDiv |= HWDivThumb; 5113 } else if (Feature == "+hwdiv-arm") { 5114 HWDiv |= HWDivARM; 5115 } else if (Feature == "+crc") { 5116 CRC = 1; 5117 } else if (Feature == "+crypto") { 5118 Crypto = 1; 5119 } else if (Feature == "+dsp") { 5120 DSP = 1; 5121 } else if (Feature == "+fp-only-sp") { 5122 HW_FP_remove |= HW_FP_DP; 5123 } else if (Feature == "+strict-align") { 5124 Unaligned = 0; 5125 } else if (Feature == "+fp16") { 5126 HW_FP |= HW_FP_HP; 5127 } 5128 } 5129 HW_FP &= ~HW_FP_remove; 5130 5131 switch (ArchVersion) { 5132 case 6: 5133 if (ArchProfile == llvm::ARM::PK_M) 5134 LDREX = 0; 5135 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5136 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5137 else 5138 LDREX = LDREX_W; 5139 break; 5140 case 7: 5141 if (ArchProfile == llvm::ARM::PK_M) 5142 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5143 else 5144 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5145 break; 5146 case 8: 5147 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5148 } 5149 5150 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5151 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5152 return false; 5153 } 5154 5155 if (FPMath == FP_Neon) 5156 Features.push_back("+neonfp"); 5157 else if (FPMath == FP_VFP) 5158 Features.push_back("-neonfp"); 5159 5160 // Remove front-end specific options which the backend handles differently. 5161 auto Feature = 5162 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5163 if (Feature != Features.end()) 5164 Features.erase(Feature); 5165 5166 return true; 5167 } 5168 5169 bool hasFeature(StringRef Feature) const override { 5170 return llvm::StringSwitch<bool>(Feature) 5171 .Case("arm", true) 5172 .Case("aarch32", true) 5173 .Case("softfloat", SoftFloat) 5174 .Case("thumb", isThumb()) 5175 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5176 .Case("hwdiv", HWDiv & HWDivThumb) 5177 .Case("hwdiv-arm", HWDiv & HWDivARM) 5178 .Default(false); 5179 } 5180 5181 bool setCPU(const std::string &Name) override { 5182 if (Name != "generic") 5183 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5184 5185 if (ArchKind == llvm::ARM::AK_INVALID) 5186 return false; 5187 setAtomic(); 5188 CPU = Name; 5189 return true; 5190 } 5191 5192 bool setFPMath(StringRef Name) override; 5193 5194 void getTargetDefines(const LangOptions &Opts, 5195 MacroBuilder &Builder) const override { 5196 // Target identification. 5197 Builder.defineMacro("__arm"); 5198 Builder.defineMacro("__arm__"); 5199 // For bare-metal none-eabi. 5200 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5201 getTriple().getEnvironment() == llvm::Triple::EABI) 5202 Builder.defineMacro("__ELF__"); 5203 5204 // Target properties. 5205 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5206 5207 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5208 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5209 if (getTriple().isWatchABI()) 5210 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5211 5212 if (!CPUAttr.empty()) 5213 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5214 5215 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5216 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5217 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5218 5219 if (ArchVersion >= 8) { 5220 // ACLE 6.5.7 Crypto Extension 5221 if (Crypto) 5222 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5223 // ACLE 6.5.8 CRC32 Extension 5224 if (CRC) 5225 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5226 // ACLE 6.5.10 Numeric Maximum and Minimum 5227 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5228 // ACLE 6.5.9 Directed Rounding 5229 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5230 } 5231 5232 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5233 // is not defined for the M-profile. 5234 // NOTE that the default profile is assumed to be 'A' 5235 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5236 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5237 5238 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5239 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5240 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5241 // v7 and v8 architectures excluding v8-M Baseline. 5242 if (supportsThumb2()) 5243 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5244 else if (supportsThumb()) 5245 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5246 5247 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5248 // instruction set such as ARM or Thumb. 5249 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5250 5251 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5252 5253 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5254 if (!CPUProfile.empty()) 5255 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5256 5257 // ACLE 6.4.3 Unaligned access supported in hardware 5258 if (Unaligned) 5259 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5260 5261 // ACLE 6.4.4 LDREX/STREX 5262 if (LDREX) 5263 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5264 5265 // ACLE 6.4.5 CLZ 5266 if (ArchVersion == 5 || 5267 (ArchVersion == 6 && CPUProfile != "M") || 5268 ArchVersion > 6) 5269 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5270 5271 // ACLE 6.5.1 Hardware Floating Point 5272 if (HW_FP) 5273 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5274 5275 // ACLE predefines. 5276 Builder.defineMacro("__ARM_ACLE", "200"); 5277 5278 // FP16 support (we currently only support IEEE format). 5279 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5280 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5281 5282 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5283 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5284 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5285 5286 // Subtarget options. 5287 5288 // FIXME: It's more complicated than this and we don't really support 5289 // interworking. 5290 // Windows on ARM does not "support" interworking 5291 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5292 Builder.defineMacro("__THUMB_INTERWORK__"); 5293 5294 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5295 // Embedded targets on Darwin follow AAPCS, but not EABI. 5296 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5297 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5298 Builder.defineMacro("__ARM_EABI__"); 5299 Builder.defineMacro("__ARM_PCS", "1"); 5300 } 5301 5302 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5303 ABI == "aapcs16") 5304 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5305 5306 if (SoftFloat) 5307 Builder.defineMacro("__SOFTFP__"); 5308 5309 if (ArchKind == llvm::ARM::AK_XSCALE) 5310 Builder.defineMacro("__XSCALE__"); 5311 5312 if (isThumb()) { 5313 Builder.defineMacro("__THUMBEL__"); 5314 Builder.defineMacro("__thumb__"); 5315 if (supportsThumb2()) 5316 Builder.defineMacro("__thumb2__"); 5317 } 5318 5319 // ACLE 6.4.9 32-bit SIMD instructions 5320 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5321 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5322 5323 // ACLE 6.4.10 Hardware Integer Divide 5324 if (((HWDiv & HWDivThumb) && isThumb()) || 5325 ((HWDiv & HWDivARM) && !isThumb())) { 5326 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5327 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5328 } 5329 5330 // Note, this is always on in gcc, even though it doesn't make sense. 5331 Builder.defineMacro("__APCS_32__"); 5332 5333 if (FPUModeIsVFP((FPUMode) FPU)) { 5334 Builder.defineMacro("__VFP_FP__"); 5335 if (FPU & VFP2FPU) 5336 Builder.defineMacro("__ARM_VFPV2__"); 5337 if (FPU & VFP3FPU) 5338 Builder.defineMacro("__ARM_VFPV3__"); 5339 if (FPU & VFP4FPU) 5340 Builder.defineMacro("__ARM_VFPV4__"); 5341 } 5342 5343 // This only gets set when Neon instructions are actually available, unlike 5344 // the VFP define, hence the soft float and arch check. This is subtly 5345 // different from gcc, we follow the intent which was that it should be set 5346 // when Neon instructions are actually available. 5347 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5348 Builder.defineMacro("__ARM_NEON", "1"); 5349 Builder.defineMacro("__ARM_NEON__"); 5350 // current AArch32 NEON implementations do not support double-precision 5351 // floating-point even when it is present in VFP. 5352 Builder.defineMacro("__ARM_NEON_FP", 5353 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5354 } 5355 5356 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5357 Opts.ShortWChar ? "2" : "4"); 5358 5359 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5360 Opts.ShortEnums ? "1" : "4"); 5361 5362 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5363 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5364 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5365 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5366 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5367 } 5368 5369 // ACLE 6.4.7 DSP instructions 5370 if (DSP) { 5371 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5372 } 5373 5374 // ACLE 6.4.8 Saturation instructions 5375 bool SAT = false; 5376 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5377 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5378 SAT = true; 5379 } 5380 5381 // ACLE 6.4.6 Q (saturation) flag 5382 if (DSP || SAT) 5383 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5384 5385 if (Opts.UnsafeFPMath) 5386 Builder.defineMacro("__ARM_FP_FAST", "1"); 5387 5388 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5389 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5390 } 5391 5392 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5393 return llvm::makeArrayRef(BuiltinInfo, 5394 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5395 } 5396 bool isCLZForZeroUndef() const override { return false; } 5397 BuiltinVaListKind getBuiltinVaListKind() const override { 5398 return IsAAPCS 5399 ? AAPCSABIBuiltinVaList 5400 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5401 : TargetInfo::VoidPtrBuiltinVaList); 5402 } 5403 ArrayRef<const char *> getGCCRegNames() const override; 5404 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5405 bool validateAsmConstraint(const char *&Name, 5406 TargetInfo::ConstraintInfo &Info) const override { 5407 switch (*Name) { 5408 default: break; 5409 case 'l': // r0-r7 5410 case 'h': // r8-r15 5411 case 't': // VFP Floating point register single precision 5412 case 'w': // VFP Floating point register double precision 5413 Info.setAllowsRegister(); 5414 return true; 5415 case 'I': 5416 case 'J': 5417 case 'K': 5418 case 'L': 5419 case 'M': 5420 // FIXME 5421 return true; 5422 case 'Q': // A memory address that is a single base register. 5423 Info.setAllowsMemory(); 5424 return true; 5425 case 'U': // a memory reference... 5426 switch (Name[1]) { 5427 case 'q': // ...ARMV4 ldrsb 5428 case 'v': // ...VFP load/store (reg+constant offset) 5429 case 'y': // ...iWMMXt load/store 5430 case 't': // address valid for load/store opaque types wider 5431 // than 128-bits 5432 case 'n': // valid address for Neon doubleword vector load/store 5433 case 'm': // valid address for Neon element and structure load/store 5434 case 's': // valid address for non-offset loads/stores of quad-word 5435 // values in four ARM registers 5436 Info.setAllowsMemory(); 5437 Name++; 5438 return true; 5439 } 5440 } 5441 return false; 5442 } 5443 std::string convertConstraint(const char *&Constraint) const override { 5444 std::string R; 5445 switch (*Constraint) { 5446 case 'U': // Two-character constraint; add "^" hint for later parsing. 5447 R = std::string("^") + std::string(Constraint, 2); 5448 Constraint++; 5449 break; 5450 case 'p': // 'p' should be translated to 'r' by default. 5451 R = std::string("r"); 5452 break; 5453 default: 5454 return std::string(1, *Constraint); 5455 } 5456 return R; 5457 } 5458 bool 5459 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5460 std::string &SuggestedModifier) const override { 5461 bool isOutput = (Constraint[0] == '='); 5462 bool isInOut = (Constraint[0] == '+'); 5463 5464 // Strip off constraint modifiers. 5465 while (Constraint[0] == '=' || 5466 Constraint[0] == '+' || 5467 Constraint[0] == '&') 5468 Constraint = Constraint.substr(1); 5469 5470 switch (Constraint[0]) { 5471 default: break; 5472 case 'r': { 5473 switch (Modifier) { 5474 default: 5475 return (isInOut || isOutput || Size <= 64); 5476 case 'q': 5477 // A register of size 32 cannot fit a vector type. 5478 return false; 5479 } 5480 } 5481 } 5482 5483 return true; 5484 } 5485 const char *getClobbers() const override { 5486 // FIXME: Is this really right? 5487 return ""; 5488 } 5489 5490 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5491 switch (CC) { 5492 case CC_AAPCS: 5493 case CC_AAPCS_VFP: 5494 case CC_Swift: 5495 return CCCR_OK; 5496 default: 5497 return CCCR_Warning; 5498 } 5499 } 5500 5501 int getEHDataRegisterNumber(unsigned RegNo) const override { 5502 if (RegNo == 0) return 0; 5503 if (RegNo == 1) return 1; 5504 return -1; 5505 } 5506 5507 bool hasSjLjLowering() const override { 5508 return true; 5509 } 5510 }; 5511 5512 bool ARMTargetInfo::setFPMath(StringRef Name) { 5513 if (Name == "neon") { 5514 FPMath = FP_Neon; 5515 return true; 5516 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5517 Name == "vfp4") { 5518 FPMath = FP_VFP; 5519 return true; 5520 } 5521 return false; 5522 } 5523 5524 const char * const ARMTargetInfo::GCCRegNames[] = { 5525 // Integer registers 5526 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5527 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5528 5529 // Float registers 5530 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5531 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5532 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5533 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5534 5535 // Double registers 5536 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5537 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5538 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5539 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5540 5541 // Quad registers 5542 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5543 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5544 }; 5545 5546 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5547 return llvm::makeArrayRef(GCCRegNames); 5548 } 5549 5550 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5551 { { "a1" }, "r0" }, 5552 { { "a2" }, "r1" }, 5553 { { "a3" }, "r2" }, 5554 { { "a4" }, "r3" }, 5555 { { "v1" }, "r4" }, 5556 { { "v2" }, "r5" }, 5557 { { "v3" }, "r6" }, 5558 { { "v4" }, "r7" }, 5559 { { "v5" }, "r8" }, 5560 { { "v6", "rfp" }, "r9" }, 5561 { { "sl" }, "r10" }, 5562 { { "fp" }, "r11" }, 5563 { { "ip" }, "r12" }, 5564 { { "r13" }, "sp" }, 5565 { { "r14" }, "lr" }, 5566 { { "r15" }, "pc" }, 5567 // The S, D and Q registers overlap, but aren't really aliases; we 5568 // don't want to substitute one of these for a different-sized one. 5569 }; 5570 5571 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5572 return llvm::makeArrayRef(GCCRegAliases); 5573 } 5574 5575 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5576 #define BUILTIN(ID, TYPE, ATTRS) \ 5577 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5578 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5579 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5580 #include "clang/Basic/BuiltinsNEON.def" 5581 5582 #define BUILTIN(ID, TYPE, ATTRS) \ 5583 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5584 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5585 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5586 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5587 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5588 #include "clang/Basic/BuiltinsARM.def" 5589 }; 5590 5591 class ARMleTargetInfo : public ARMTargetInfo { 5592 public: 5593 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5594 : ARMTargetInfo(Triple, Opts) {} 5595 void getTargetDefines(const LangOptions &Opts, 5596 MacroBuilder &Builder) const override { 5597 Builder.defineMacro("__ARMEL__"); 5598 ARMTargetInfo::getTargetDefines(Opts, Builder); 5599 } 5600 }; 5601 5602 class ARMbeTargetInfo : public ARMTargetInfo { 5603 public: 5604 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5605 : ARMTargetInfo(Triple, Opts) {} 5606 void getTargetDefines(const LangOptions &Opts, 5607 MacroBuilder &Builder) const override { 5608 Builder.defineMacro("__ARMEB__"); 5609 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5610 ARMTargetInfo::getTargetDefines(Opts, Builder); 5611 } 5612 }; 5613 5614 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5615 const llvm::Triple Triple; 5616 public: 5617 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5618 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5619 WCharType = UnsignedShort; 5620 SizeType = UnsignedInt; 5621 } 5622 void getVisualStudioDefines(const LangOptions &Opts, 5623 MacroBuilder &Builder) const { 5624 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5625 5626 // FIXME: this is invalid for WindowsCE 5627 Builder.defineMacro("_M_ARM_NT", "1"); 5628 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5629 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5630 5631 assert((Triple.getArch() == llvm::Triple::arm || 5632 Triple.getArch() == llvm::Triple::thumb) && 5633 "invalid architecture for Windows ARM target info"); 5634 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5635 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5636 5637 // TODO map the complete set of values 5638 // 31: VFPv3 40: VFPv4 5639 Builder.defineMacro("_M_ARM_FP", "31"); 5640 } 5641 BuiltinVaListKind getBuiltinVaListKind() const override { 5642 return TargetInfo::CharPtrBuiltinVaList; 5643 } 5644 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5645 switch (CC) { 5646 case CC_X86StdCall: 5647 case CC_X86ThisCall: 5648 case CC_X86FastCall: 5649 case CC_X86VectorCall: 5650 return CCCR_Ignore; 5651 case CC_C: 5652 return CCCR_OK; 5653 default: 5654 return CCCR_Warning; 5655 } 5656 } 5657 }; 5658 5659 // Windows ARM + Itanium C++ ABI Target 5660 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5661 public: 5662 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5663 const TargetOptions &Opts) 5664 : WindowsARMTargetInfo(Triple, Opts) { 5665 TheCXXABI.set(TargetCXXABI::GenericARM); 5666 } 5667 5668 void getTargetDefines(const LangOptions &Opts, 5669 MacroBuilder &Builder) const override { 5670 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5671 5672 if (Opts.MSVCCompat) 5673 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5674 } 5675 }; 5676 5677 // Windows ARM, MS (C++) ABI 5678 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5679 public: 5680 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5681 const TargetOptions &Opts) 5682 : WindowsARMTargetInfo(Triple, Opts) { 5683 TheCXXABI.set(TargetCXXABI::Microsoft); 5684 } 5685 5686 void getTargetDefines(const LangOptions &Opts, 5687 MacroBuilder &Builder) const override { 5688 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5689 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5690 } 5691 }; 5692 5693 // ARM MinGW target 5694 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5695 public: 5696 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5697 : WindowsARMTargetInfo(Triple, Opts) { 5698 TheCXXABI.set(TargetCXXABI::GenericARM); 5699 } 5700 5701 void getTargetDefines(const LangOptions &Opts, 5702 MacroBuilder &Builder) const override { 5703 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5704 DefineStd(Builder, "WIN32", Opts); 5705 DefineStd(Builder, "WINNT", Opts); 5706 Builder.defineMacro("_ARM_"); 5707 addMinGWDefines(Opts, Builder); 5708 } 5709 }; 5710 5711 // ARM Cygwin target 5712 class CygwinARMTargetInfo : public ARMleTargetInfo { 5713 public: 5714 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5715 : ARMleTargetInfo(Triple, Opts) { 5716 TLSSupported = false; 5717 WCharType = UnsignedShort; 5718 DoubleAlign = LongLongAlign = 64; 5719 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5720 } 5721 void getTargetDefines(const LangOptions &Opts, 5722 MacroBuilder &Builder) const override { 5723 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5724 Builder.defineMacro("_ARM_"); 5725 Builder.defineMacro("__CYGWIN__"); 5726 Builder.defineMacro("__CYGWIN32__"); 5727 DefineStd(Builder, "unix", Opts); 5728 if (Opts.CPlusPlus) 5729 Builder.defineMacro("_GNU_SOURCE"); 5730 } 5731 }; 5732 5733 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 5734 protected: 5735 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5736 MacroBuilder &Builder) const override { 5737 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5738 } 5739 5740 public: 5741 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5742 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 5743 HasAlignMac68kSupport = true; 5744 // iOS always has 64-bit atomic instructions. 5745 // FIXME: This should be based off of the target features in 5746 // ARMleTargetInfo. 5747 MaxAtomicInlineWidth = 64; 5748 5749 if (Triple.isWatchABI()) { 5750 // Darwin on iOS uses a variant of the ARM C++ ABI. 5751 TheCXXABI.set(TargetCXXABI::WatchOS); 5752 5753 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5754 // size_t is long, it's a bit weird for it to be int. 5755 PtrDiffType = SignedLong; 5756 5757 // BOOL should be a real boolean on the new ABI 5758 UseSignedCharForObjCBool = false; 5759 } else 5760 TheCXXABI.set(TargetCXXABI::iOS); 5761 } 5762 }; 5763 5764 class AArch64TargetInfo : public TargetInfo { 5765 virtual void setDataLayout() = 0; 5766 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5767 static const char *const GCCRegNames[]; 5768 5769 enum FPUModeEnum { 5770 FPUMode, 5771 NeonMode 5772 }; 5773 5774 unsigned FPU; 5775 unsigned CRC; 5776 unsigned Crypto; 5777 unsigned Unaligned; 5778 unsigned V8_1A; 5779 5780 static const Builtin::Info BuiltinInfo[]; 5781 5782 std::string ABI; 5783 5784 public: 5785 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5786 : TargetInfo(Triple), ABI("aapcs") { 5787 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5788 WCharType = SignedInt; 5789 5790 // NetBSD apparently prefers consistency across ARM targets to consistency 5791 // across 64-bit targets. 5792 Int64Type = SignedLongLong; 5793 IntMaxType = SignedLongLong; 5794 } else { 5795 WCharType = UnsignedInt; 5796 Int64Type = SignedLong; 5797 IntMaxType = SignedLong; 5798 } 5799 5800 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5801 MaxVectorAlign = 128; 5802 MaxAtomicInlineWidth = 128; 5803 MaxAtomicPromoteWidth = 128; 5804 5805 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5806 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5807 5808 // {} in inline assembly are neon specifiers, not assembly variant 5809 // specifiers. 5810 NoAsmVariants = true; 5811 5812 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5813 // contributes to the alignment of the containing aggregate in the same way 5814 // a plain (non bit-field) member of that type would, without exception for 5815 // zero-sized or anonymous bit-fields." 5816 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5817 UseZeroLengthBitfieldAlignment = true; 5818 5819 // AArch64 targets default to using the ARM C++ ABI. 5820 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5821 5822 if (Triple.getOS() == llvm::Triple::Linux || 5823 Triple.getOS() == llvm::Triple::UnknownOS) 5824 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 5825 } 5826 5827 StringRef getABI() const override { return ABI; } 5828 bool setABI(const std::string &Name) override { 5829 if (Name != "aapcs" && Name != "darwinpcs") 5830 return false; 5831 5832 ABI = Name; 5833 return true; 5834 } 5835 5836 bool setCPU(const std::string &Name) override { 5837 return Name == "generic" || 5838 llvm::AArch64::parseCPUArch(Name) != 5839 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 5840 } 5841 5842 void getTargetDefines(const LangOptions &Opts, 5843 MacroBuilder &Builder) const override { 5844 // Target identification. 5845 Builder.defineMacro("__aarch64__"); 5846 5847 // Target properties. 5848 Builder.defineMacro("_LP64"); 5849 Builder.defineMacro("__LP64__"); 5850 5851 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5852 Builder.defineMacro("__ARM_ACLE", "200"); 5853 Builder.defineMacro("__ARM_ARCH", "8"); 5854 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5855 5856 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5857 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5858 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5859 5860 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5861 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5862 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5863 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5864 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5865 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5866 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5867 5868 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5869 5870 // 0xe implies support for half, single and double precision operations. 5871 Builder.defineMacro("__ARM_FP", "0xE"); 5872 5873 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5874 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5875 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5876 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5877 5878 if (Opts.UnsafeFPMath) 5879 Builder.defineMacro("__ARM_FP_FAST", "1"); 5880 5881 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5882 5883 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5884 Opts.ShortEnums ? "1" : "4"); 5885 5886 if (FPU == NeonMode) { 5887 Builder.defineMacro("__ARM_NEON", "1"); 5888 // 64-bit NEON supports half, single and double precision operations. 5889 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5890 } 5891 5892 if (CRC) 5893 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5894 5895 if (Crypto) 5896 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5897 5898 if (Unaligned) 5899 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5900 5901 if (V8_1A) 5902 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5903 5904 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5905 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5906 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5907 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5908 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5909 } 5910 5911 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5912 return llvm::makeArrayRef(BuiltinInfo, 5913 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5914 } 5915 5916 bool hasFeature(StringRef Feature) const override { 5917 return Feature == "aarch64" || 5918 Feature == "arm64" || 5919 Feature == "arm" || 5920 (Feature == "neon" && FPU == NeonMode); 5921 } 5922 5923 bool handleTargetFeatures(std::vector<std::string> &Features, 5924 DiagnosticsEngine &Diags) override { 5925 FPU = FPUMode; 5926 CRC = 0; 5927 Crypto = 0; 5928 Unaligned = 1; 5929 V8_1A = 0; 5930 5931 for (const auto &Feature : Features) { 5932 if (Feature == "+neon") 5933 FPU = NeonMode; 5934 if (Feature == "+crc") 5935 CRC = 1; 5936 if (Feature == "+crypto") 5937 Crypto = 1; 5938 if (Feature == "+strict-align") 5939 Unaligned = 0; 5940 if (Feature == "+v8.1a") 5941 V8_1A = 1; 5942 } 5943 5944 setDataLayout(); 5945 5946 return true; 5947 } 5948 5949 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5950 switch (CC) { 5951 case CC_C: 5952 case CC_Swift: 5953 case CC_PreserveMost: 5954 case CC_PreserveAll: 5955 return CCCR_OK; 5956 default: 5957 return CCCR_Warning; 5958 } 5959 } 5960 5961 bool isCLZForZeroUndef() const override { return false; } 5962 5963 BuiltinVaListKind getBuiltinVaListKind() const override { 5964 return TargetInfo::AArch64ABIBuiltinVaList; 5965 } 5966 5967 ArrayRef<const char *> getGCCRegNames() const override; 5968 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5969 5970 bool validateAsmConstraint(const char *&Name, 5971 TargetInfo::ConstraintInfo &Info) const override { 5972 switch (*Name) { 5973 default: 5974 return false; 5975 case 'w': // Floating point and SIMD registers (V0-V31) 5976 Info.setAllowsRegister(); 5977 return true; 5978 case 'I': // Constant that can be used with an ADD instruction 5979 case 'J': // Constant that can be used with a SUB instruction 5980 case 'K': // Constant that can be used with a 32-bit logical instruction 5981 case 'L': // Constant that can be used with a 64-bit logical instruction 5982 case 'M': // Constant that can be used as a 32-bit MOV immediate 5983 case 'N': // Constant that can be used as a 64-bit MOV immediate 5984 case 'Y': // Floating point constant zero 5985 case 'Z': // Integer constant zero 5986 return true; 5987 case 'Q': // A memory reference with base register and no offset 5988 Info.setAllowsMemory(); 5989 return true; 5990 case 'S': // A symbolic address 5991 Info.setAllowsRegister(); 5992 return true; 5993 case 'U': 5994 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5995 // Utf: A memory address suitable for ldp/stp in TF mode. 5996 // Usa: An absolute symbolic address. 5997 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5998 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5999 case 'z': // Zero register, wzr or xzr 6000 Info.setAllowsRegister(); 6001 return true; 6002 case 'x': // Floating point and SIMD registers (V0-V15) 6003 Info.setAllowsRegister(); 6004 return true; 6005 } 6006 return false; 6007 } 6008 6009 bool 6010 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 6011 std::string &SuggestedModifier) const override { 6012 // Strip off constraint modifiers. 6013 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 6014 Constraint = Constraint.substr(1); 6015 6016 switch (Constraint[0]) { 6017 default: 6018 return true; 6019 case 'z': 6020 case 'r': { 6021 switch (Modifier) { 6022 case 'x': 6023 case 'w': 6024 // For now assume that the person knows what they're 6025 // doing with the modifier. 6026 return true; 6027 default: 6028 // By default an 'r' constraint will be in the 'x' 6029 // registers. 6030 if (Size == 64) 6031 return true; 6032 6033 SuggestedModifier = "w"; 6034 return false; 6035 } 6036 } 6037 } 6038 } 6039 6040 const char *getClobbers() const override { return ""; } 6041 6042 int getEHDataRegisterNumber(unsigned RegNo) const override { 6043 if (RegNo == 0) 6044 return 0; 6045 if (RegNo == 1) 6046 return 1; 6047 return -1; 6048 } 6049 }; 6050 6051 const char *const AArch64TargetInfo::GCCRegNames[] = { 6052 // 32-bit Integer registers 6053 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 6054 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 6055 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 6056 6057 // 64-bit Integer registers 6058 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 6059 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 6060 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 6061 6062 // 32-bit floating point regsisters 6063 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 6064 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 6065 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6066 6067 // 64-bit floating point regsisters 6068 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 6069 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 6070 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6071 6072 // Vector registers 6073 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6074 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6075 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6076 }; 6077 6078 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6079 return llvm::makeArrayRef(GCCRegNames); 6080 } 6081 6082 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6083 { { "w31" }, "wsp" }, 6084 { { "x29" }, "fp" }, 6085 { { "x30" }, "lr" }, 6086 { { "x31" }, "sp" }, 6087 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6088 // don't want to substitute one of these for a different-sized one. 6089 }; 6090 6091 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6092 return llvm::makeArrayRef(GCCRegAliases); 6093 } 6094 6095 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6096 #define BUILTIN(ID, TYPE, ATTRS) \ 6097 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6098 #include "clang/Basic/BuiltinsNEON.def" 6099 6100 #define BUILTIN(ID, TYPE, ATTRS) \ 6101 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6102 #include "clang/Basic/BuiltinsAArch64.def" 6103 }; 6104 6105 class AArch64leTargetInfo : public AArch64TargetInfo { 6106 void setDataLayout() override { 6107 if (getTriple().isOSBinFormatMachO()) 6108 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6109 else 6110 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6111 } 6112 6113 public: 6114 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6115 : AArch64TargetInfo(Triple, Opts) { 6116 } 6117 void getTargetDefines(const LangOptions &Opts, 6118 MacroBuilder &Builder) const override { 6119 Builder.defineMacro("__AARCH64EL__"); 6120 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6121 } 6122 }; 6123 6124 class AArch64beTargetInfo : public AArch64TargetInfo { 6125 void setDataLayout() override { 6126 assert(!getTriple().isOSBinFormatMachO()); 6127 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6128 } 6129 6130 public: 6131 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6132 : AArch64TargetInfo(Triple, Opts) {} 6133 void getTargetDefines(const LangOptions &Opts, 6134 MacroBuilder &Builder) const override { 6135 Builder.defineMacro("__AARCH64EB__"); 6136 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6137 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6138 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6139 } 6140 }; 6141 6142 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6143 protected: 6144 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6145 MacroBuilder &Builder) const override { 6146 Builder.defineMacro("__AARCH64_SIMD__"); 6147 Builder.defineMacro("__ARM64_ARCH_8__"); 6148 Builder.defineMacro("__ARM_NEON__"); 6149 Builder.defineMacro("__LITTLE_ENDIAN__"); 6150 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6151 Builder.defineMacro("__arm64", "1"); 6152 Builder.defineMacro("__arm64__", "1"); 6153 6154 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6155 } 6156 6157 public: 6158 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6159 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6160 Int64Type = SignedLongLong; 6161 WCharType = SignedInt; 6162 UseSignedCharForObjCBool = false; 6163 6164 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6165 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6166 6167 TheCXXABI.set(TargetCXXABI::iOS64); 6168 } 6169 6170 BuiltinVaListKind getBuiltinVaListKind() const override { 6171 return TargetInfo::CharPtrBuiltinVaList; 6172 } 6173 }; 6174 6175 // Hexagon abstract base class 6176 class HexagonTargetInfo : public TargetInfo { 6177 static const Builtin::Info BuiltinInfo[]; 6178 static const char * const GCCRegNames[]; 6179 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6180 std::string CPU; 6181 bool HasHVX, HasHVXDouble; 6182 bool UseLongCalls; 6183 6184 public: 6185 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6186 : TargetInfo(Triple) { 6187 // Specify the vector alignment explicitly. For v512x1, the calculated 6188 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6189 // the required minimum of 64 bytes. 6190 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6191 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6192 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6193 SizeType = UnsignedInt; 6194 PtrDiffType = SignedInt; 6195 IntPtrType = SignedInt; 6196 6197 // {} in inline assembly are packet specifiers, not assembly variant 6198 // specifiers. 6199 NoAsmVariants = true; 6200 6201 LargeArrayMinWidth = 64; 6202 LargeArrayAlign = 64; 6203 UseBitFieldTypeAlignment = true; 6204 ZeroLengthBitfieldBoundary = 32; 6205 HasHVX = HasHVXDouble = false; 6206 UseLongCalls = false; 6207 } 6208 6209 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6210 return llvm::makeArrayRef(BuiltinInfo, 6211 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6212 } 6213 6214 bool validateAsmConstraint(const char *&Name, 6215 TargetInfo::ConstraintInfo &Info) const override { 6216 switch (*Name) { 6217 case 'v': 6218 case 'q': 6219 if (HasHVX) { 6220 Info.setAllowsRegister(); 6221 return true; 6222 } 6223 break; 6224 case 's': 6225 // Relocatable constant. 6226 return true; 6227 } 6228 return false; 6229 } 6230 6231 void getTargetDefines(const LangOptions &Opts, 6232 MacroBuilder &Builder) const override; 6233 6234 bool isCLZForZeroUndef() const override { return false; } 6235 6236 bool hasFeature(StringRef Feature) const override { 6237 return llvm::StringSwitch<bool>(Feature) 6238 .Case("hexagon", true) 6239 .Case("hvx", HasHVX) 6240 .Case("hvx-double", HasHVXDouble) 6241 .Case("long-calls", UseLongCalls) 6242 .Default(false); 6243 } 6244 6245 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6246 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6247 const override; 6248 6249 bool handleTargetFeatures(std::vector<std::string> &Features, 6250 DiagnosticsEngine &Diags) override; 6251 6252 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6253 bool Enabled) const override; 6254 6255 BuiltinVaListKind getBuiltinVaListKind() const override { 6256 return TargetInfo::CharPtrBuiltinVaList; 6257 } 6258 ArrayRef<const char *> getGCCRegNames() const override; 6259 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6260 const char *getClobbers() const override { 6261 return ""; 6262 } 6263 6264 static const char *getHexagonCPUSuffix(StringRef Name) { 6265 return llvm::StringSwitch<const char*>(Name) 6266 .Case("hexagonv4", "4") 6267 .Case("hexagonv5", "5") 6268 .Case("hexagonv55", "55") 6269 .Case("hexagonv60", "60") 6270 .Default(nullptr); 6271 } 6272 6273 bool setCPU(const std::string &Name) override { 6274 if (!getHexagonCPUSuffix(Name)) 6275 return false; 6276 CPU = Name; 6277 return true; 6278 } 6279 6280 int getEHDataRegisterNumber(unsigned RegNo) const override { 6281 return RegNo < 2 ? RegNo : -1; 6282 } 6283 }; 6284 6285 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6286 MacroBuilder &Builder) const { 6287 Builder.defineMacro("__qdsp6__", "1"); 6288 Builder.defineMacro("__hexagon__", "1"); 6289 6290 if (CPU == "hexagonv4") { 6291 Builder.defineMacro("__HEXAGON_V4__"); 6292 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6293 if (Opts.HexagonQdsp6Compat) { 6294 Builder.defineMacro("__QDSP6_V4__"); 6295 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6296 } 6297 } else if (CPU == "hexagonv5") { 6298 Builder.defineMacro("__HEXAGON_V5__"); 6299 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6300 if(Opts.HexagonQdsp6Compat) { 6301 Builder.defineMacro("__QDSP6_V5__"); 6302 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6303 } 6304 } else if (CPU == "hexagonv55") { 6305 Builder.defineMacro("__HEXAGON_V55__"); 6306 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6307 Builder.defineMacro("__QDSP6_V55__"); 6308 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6309 } else if (CPU == "hexagonv60") { 6310 Builder.defineMacro("__HEXAGON_V60__"); 6311 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6312 Builder.defineMacro("__QDSP6_V60__"); 6313 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6314 } 6315 6316 if (hasFeature("hvx")) { 6317 Builder.defineMacro("__HVX__"); 6318 if (hasFeature("hvx-double")) 6319 Builder.defineMacro("__HVXDBL__"); 6320 } 6321 } 6322 6323 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6324 DiagnosticsEngine &Diags, StringRef CPU, 6325 const std::vector<std::string> &FeaturesVec) const { 6326 // Default for v60: -hvx, -hvx-double. 6327 Features["hvx"] = false; 6328 Features["hvx-double"] = false; 6329 Features["long-calls"] = false; 6330 6331 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6332 } 6333 6334 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6335 DiagnosticsEngine &Diags) { 6336 for (auto &F : Features) { 6337 if (F == "+hvx") 6338 HasHVX = true; 6339 else if (F == "-hvx") 6340 HasHVX = HasHVXDouble = false; 6341 else if (F == "+hvx-double") 6342 HasHVX = HasHVXDouble = true; 6343 else if (F == "-hvx-double") 6344 HasHVXDouble = false; 6345 6346 if (F == "+long-calls") 6347 UseLongCalls = true; 6348 else if (F == "-long-calls") 6349 UseLongCalls = false; 6350 } 6351 return true; 6352 } 6353 6354 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 6355 StringRef Name, bool Enabled) const { 6356 if (Enabled) { 6357 if (Name == "hvx-double") 6358 Features["hvx"] = true; 6359 } else { 6360 if (Name == "hvx") 6361 Features["hvx-double"] = false; 6362 } 6363 Features[Name] = Enabled; 6364 } 6365 6366 const char *const HexagonTargetInfo::GCCRegNames[] = { 6367 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6368 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6369 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6370 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6371 "p0", "p1", "p2", "p3", 6372 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6373 }; 6374 6375 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6376 return llvm::makeArrayRef(GCCRegNames); 6377 } 6378 6379 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6380 { { "sp" }, "r29" }, 6381 { { "fp" }, "r30" }, 6382 { { "lr" }, "r31" }, 6383 }; 6384 6385 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6386 return llvm::makeArrayRef(GCCRegAliases); 6387 } 6388 6389 6390 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6391 #define BUILTIN(ID, TYPE, ATTRS) \ 6392 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6393 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6394 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6395 #include "clang/Basic/BuiltinsHexagon.def" 6396 }; 6397 6398 class LanaiTargetInfo : public TargetInfo { 6399 // Class for Lanai (32-bit). 6400 // The CPU profiles supported by the Lanai backend 6401 enum CPUKind { 6402 CK_NONE, 6403 CK_V11, 6404 } CPU; 6405 6406 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6407 static const char *const GCCRegNames[]; 6408 6409 public: 6410 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6411 : TargetInfo(Triple) { 6412 // Description string has to be kept in sync with backend. 6413 resetDataLayout("E" // Big endian 6414 "-m:e" // ELF name manging 6415 "-p:32:32" // 32 bit pointers, 32 bit aligned 6416 "-i64:64" // 64 bit integers, 64 bit aligned 6417 "-a:0:32" // 32 bit alignment of objects of aggregate type 6418 "-n32" // 32 bit native integer width 6419 "-S64" // 64 bit natural stack alignment 6420 ); 6421 6422 // Setting RegParmMax equal to what mregparm was set to in the old 6423 // toolchain 6424 RegParmMax = 4; 6425 6426 // Set the default CPU to V11 6427 CPU = CK_V11; 6428 6429 // Temporary approach to make everything at least word-aligned and allow for 6430 // safely casting between pointers with different alignment requirements. 6431 // TODO: Remove this when there are no more cast align warnings on the 6432 // firmware. 6433 MinGlobalAlign = 32; 6434 } 6435 6436 void getTargetDefines(const LangOptions &Opts, 6437 MacroBuilder &Builder) const override { 6438 // Define __lanai__ when building for target lanai. 6439 Builder.defineMacro("__lanai__"); 6440 6441 // Set define for the CPU specified. 6442 switch (CPU) { 6443 case CK_V11: 6444 Builder.defineMacro("__LANAI_V11__"); 6445 break; 6446 case CK_NONE: 6447 llvm_unreachable("Unhandled target CPU"); 6448 } 6449 } 6450 6451 bool setCPU(const std::string &Name) override { 6452 CPU = llvm::StringSwitch<CPUKind>(Name) 6453 .Case("v11", CK_V11) 6454 .Default(CK_NONE); 6455 6456 return CPU != CK_NONE; 6457 } 6458 6459 bool hasFeature(StringRef Feature) const override { 6460 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6461 } 6462 6463 ArrayRef<const char *> getGCCRegNames() const override; 6464 6465 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6466 6467 BuiltinVaListKind getBuiltinVaListKind() const override { 6468 return TargetInfo::VoidPtrBuiltinVaList; 6469 } 6470 6471 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6472 6473 bool validateAsmConstraint(const char *&Name, 6474 TargetInfo::ConstraintInfo &info) const override { 6475 return false; 6476 } 6477 6478 const char *getClobbers() const override { return ""; } 6479 }; 6480 6481 const char *const LanaiTargetInfo::GCCRegNames[] = { 6482 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6483 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6484 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6485 6486 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6487 return llvm::makeArrayRef(GCCRegNames); 6488 } 6489 6490 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6491 {{"pc"}, "r2"}, 6492 {{"sp"}, "r4"}, 6493 {{"fp"}, "r5"}, 6494 {{"rv"}, "r8"}, 6495 {{"rr1"}, "r10"}, 6496 {{"rr2"}, "r11"}, 6497 {{"rca"}, "r15"}, 6498 }; 6499 6500 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6501 return llvm::makeArrayRef(GCCRegAliases); 6502 } 6503 6504 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6505 class SparcTargetInfo : public TargetInfo { 6506 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6507 static const char * const GCCRegNames[]; 6508 bool SoftFloat; 6509 public: 6510 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6511 : TargetInfo(Triple), SoftFloat(false) {} 6512 6513 int getEHDataRegisterNumber(unsigned RegNo) const override { 6514 if (RegNo == 0) return 24; 6515 if (RegNo == 1) return 25; 6516 return -1; 6517 } 6518 6519 bool handleTargetFeatures(std::vector<std::string> &Features, 6520 DiagnosticsEngine &Diags) override { 6521 // Check if software floating point is enabled 6522 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6523 if (Feature != Features.end()) { 6524 SoftFloat = true; 6525 } 6526 return true; 6527 } 6528 void getTargetDefines(const LangOptions &Opts, 6529 MacroBuilder &Builder) const override { 6530 DefineStd(Builder, "sparc", Opts); 6531 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6532 6533 if (SoftFloat) 6534 Builder.defineMacro("SOFT_FLOAT", "1"); 6535 } 6536 6537 bool hasFeature(StringRef Feature) const override { 6538 return llvm::StringSwitch<bool>(Feature) 6539 .Case("softfloat", SoftFloat) 6540 .Case("sparc", true) 6541 .Default(false); 6542 } 6543 6544 bool hasSjLjLowering() const override { 6545 return true; 6546 } 6547 6548 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6549 // FIXME: Implement! 6550 return None; 6551 } 6552 BuiltinVaListKind getBuiltinVaListKind() const override { 6553 return TargetInfo::VoidPtrBuiltinVaList; 6554 } 6555 ArrayRef<const char *> getGCCRegNames() const override; 6556 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6557 bool validateAsmConstraint(const char *&Name, 6558 TargetInfo::ConstraintInfo &info) const override { 6559 // FIXME: Implement! 6560 switch (*Name) { 6561 case 'I': // Signed 13-bit constant 6562 case 'J': // Zero 6563 case 'K': // 32-bit constant with the low 12 bits clear 6564 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6565 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6566 case 'N': // Same as 'K' but zext (required for SIMode) 6567 case 'O': // The constant 4096 6568 return true; 6569 } 6570 return false; 6571 } 6572 const char *getClobbers() const override { 6573 // FIXME: Implement! 6574 return ""; 6575 } 6576 6577 // No Sparc V7 for now, the backend doesn't support it anyway. 6578 enum CPUKind { 6579 CK_GENERIC, 6580 CK_V8, 6581 CK_SUPERSPARC, 6582 CK_SPARCLITE, 6583 CK_F934, 6584 CK_HYPERSPARC, 6585 CK_SPARCLITE86X, 6586 CK_SPARCLET, 6587 CK_TSC701, 6588 CK_V9, 6589 CK_ULTRASPARC, 6590 CK_ULTRASPARC3, 6591 CK_NIAGARA, 6592 CK_NIAGARA2, 6593 CK_NIAGARA3, 6594 CK_NIAGARA4, 6595 CK_MYRIAD2100, 6596 CK_MYRIAD2150, 6597 CK_MYRIAD2450, 6598 CK_LEON2, 6599 CK_LEON2_AT697E, 6600 CK_LEON2_AT697F, 6601 CK_LEON3, 6602 CK_LEON3_UT699, 6603 CK_LEON3_GR712RC, 6604 CK_LEON4, 6605 CK_LEON4_GR740 6606 } CPU = CK_GENERIC; 6607 6608 enum CPUGeneration { 6609 CG_V8, 6610 CG_V9, 6611 }; 6612 6613 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6614 switch (Kind) { 6615 case CK_GENERIC: 6616 case CK_V8: 6617 case CK_SUPERSPARC: 6618 case CK_SPARCLITE: 6619 case CK_F934: 6620 case CK_HYPERSPARC: 6621 case CK_SPARCLITE86X: 6622 case CK_SPARCLET: 6623 case CK_TSC701: 6624 case CK_MYRIAD2100: 6625 case CK_MYRIAD2150: 6626 case CK_MYRIAD2450: 6627 case CK_LEON2: 6628 case CK_LEON2_AT697E: 6629 case CK_LEON2_AT697F: 6630 case CK_LEON3: 6631 case CK_LEON3_UT699: 6632 case CK_LEON3_GR712RC: 6633 case CK_LEON4: 6634 case CK_LEON4_GR740: 6635 return CG_V8; 6636 case CK_V9: 6637 case CK_ULTRASPARC: 6638 case CK_ULTRASPARC3: 6639 case CK_NIAGARA: 6640 case CK_NIAGARA2: 6641 case CK_NIAGARA3: 6642 case CK_NIAGARA4: 6643 return CG_V9; 6644 } 6645 llvm_unreachable("Unexpected CPU kind"); 6646 } 6647 6648 CPUKind getCPUKind(StringRef Name) const { 6649 return llvm::StringSwitch<CPUKind>(Name) 6650 .Case("v8", CK_V8) 6651 .Case("supersparc", CK_SUPERSPARC) 6652 .Case("sparclite", CK_SPARCLITE) 6653 .Case("f934", CK_F934) 6654 .Case("hypersparc", CK_HYPERSPARC) 6655 .Case("sparclite86x", CK_SPARCLITE86X) 6656 .Case("sparclet", CK_SPARCLET) 6657 .Case("tsc701", CK_TSC701) 6658 .Case("v9", CK_V9) 6659 .Case("ultrasparc", CK_ULTRASPARC) 6660 .Case("ultrasparc3", CK_ULTRASPARC3) 6661 .Case("niagara", CK_NIAGARA) 6662 .Case("niagara2", CK_NIAGARA2) 6663 .Case("niagara3", CK_NIAGARA3) 6664 .Case("niagara4", CK_NIAGARA4) 6665 .Case("ma2100", CK_MYRIAD2100) 6666 .Case("ma2150", CK_MYRIAD2150) 6667 .Case("ma2450", CK_MYRIAD2450) 6668 // FIXME: the myriad2[.n] spellings are obsolete, 6669 // but a grace period is needed to allow updating dependent builds. 6670 .Case("myriad2", CK_MYRIAD2100) 6671 .Case("myriad2.1", CK_MYRIAD2100) 6672 .Case("myriad2.2", CK_MYRIAD2150) 6673 .Case("leon2", CK_LEON2) 6674 .Case("at697e", CK_LEON2_AT697E) 6675 .Case("at697f", CK_LEON2_AT697F) 6676 .Case("leon3", CK_LEON3) 6677 .Case("ut699", CK_LEON3_UT699) 6678 .Case("gr712rc", CK_LEON3_GR712RC) 6679 .Case("leon4", CK_LEON4) 6680 .Case("gr740", CK_LEON4_GR740) 6681 .Default(CK_GENERIC); 6682 } 6683 6684 bool setCPU(const std::string &Name) override { 6685 CPU = getCPUKind(Name); 6686 return CPU != CK_GENERIC; 6687 } 6688 }; 6689 6690 const char * const SparcTargetInfo::GCCRegNames[] = { 6691 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6692 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6693 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6694 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6695 }; 6696 6697 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6698 return llvm::makeArrayRef(GCCRegNames); 6699 } 6700 6701 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6702 { { "g0" }, "r0" }, 6703 { { "g1" }, "r1" }, 6704 { { "g2" }, "r2" }, 6705 { { "g3" }, "r3" }, 6706 { { "g4" }, "r4" }, 6707 { { "g5" }, "r5" }, 6708 { { "g6" }, "r6" }, 6709 { { "g7" }, "r7" }, 6710 { { "o0" }, "r8" }, 6711 { { "o1" }, "r9" }, 6712 { { "o2" }, "r10" }, 6713 { { "o3" }, "r11" }, 6714 { { "o4" }, "r12" }, 6715 { { "o5" }, "r13" }, 6716 { { "o6", "sp" }, "r14" }, 6717 { { "o7" }, "r15" }, 6718 { { "l0" }, "r16" }, 6719 { { "l1" }, "r17" }, 6720 { { "l2" }, "r18" }, 6721 { { "l3" }, "r19" }, 6722 { { "l4" }, "r20" }, 6723 { { "l5" }, "r21" }, 6724 { { "l6" }, "r22" }, 6725 { { "l7" }, "r23" }, 6726 { { "i0" }, "r24" }, 6727 { { "i1" }, "r25" }, 6728 { { "i2" }, "r26" }, 6729 { { "i3" }, "r27" }, 6730 { { "i4" }, "r28" }, 6731 { { "i5" }, "r29" }, 6732 { { "i6", "fp" }, "r30" }, 6733 { { "i7" }, "r31" }, 6734 }; 6735 6736 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6737 return llvm::makeArrayRef(GCCRegAliases); 6738 } 6739 6740 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6741 class SparcV8TargetInfo : public SparcTargetInfo { 6742 public: 6743 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6744 : SparcTargetInfo(Triple, Opts) { 6745 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6746 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6747 switch (getTriple().getOS()) { 6748 default: 6749 SizeType = UnsignedInt; 6750 IntPtrType = SignedInt; 6751 PtrDiffType = SignedInt; 6752 break; 6753 case llvm::Triple::NetBSD: 6754 case llvm::Triple::OpenBSD: 6755 SizeType = UnsignedLong; 6756 IntPtrType = SignedLong; 6757 PtrDiffType = SignedLong; 6758 break; 6759 } 6760 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6761 } 6762 6763 void getTargetDefines(const LangOptions &Opts, 6764 MacroBuilder &Builder) const override { 6765 SparcTargetInfo::getTargetDefines(Opts, Builder); 6766 switch (getCPUGeneration(CPU)) { 6767 case CG_V8: 6768 Builder.defineMacro("__sparcv8"); 6769 if (getTriple().getOS() != llvm::Triple::Solaris) 6770 Builder.defineMacro("__sparcv8__"); 6771 break; 6772 case CG_V9: 6773 Builder.defineMacro("__sparcv9"); 6774 if (getTriple().getOS() != llvm::Triple::Solaris) { 6775 Builder.defineMacro("__sparcv9__"); 6776 Builder.defineMacro("__sparc_v9__"); 6777 } 6778 break; 6779 } 6780 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6781 std::string MyriadArchValue, Myriad2Value; 6782 Builder.defineMacro("__sparc_v8__"); 6783 Builder.defineMacro("__leon__"); 6784 switch (CPU) { 6785 case CK_MYRIAD2150: 6786 MyriadArchValue = "__ma2150"; 6787 Myriad2Value = "2"; 6788 break; 6789 case CK_MYRIAD2450: 6790 MyriadArchValue = "__ma2450"; 6791 Myriad2Value = "2"; 6792 break; 6793 default: 6794 MyriadArchValue = "__ma2100"; 6795 Myriad2Value = "1"; 6796 break; 6797 } 6798 Builder.defineMacro(MyriadArchValue, "1"); 6799 Builder.defineMacro(MyriadArchValue+"__", "1"); 6800 Builder.defineMacro("__myriad2__", Myriad2Value); 6801 Builder.defineMacro("__myriad2", Myriad2Value); 6802 } 6803 } 6804 6805 bool hasSjLjLowering() const override { 6806 return true; 6807 } 6808 }; 6809 6810 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6811 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6812 public: 6813 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6814 : SparcV8TargetInfo(Triple, Opts) { 6815 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6816 } 6817 }; 6818 6819 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6820 class SparcV9TargetInfo : public SparcTargetInfo { 6821 public: 6822 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6823 : SparcTargetInfo(Triple, Opts) { 6824 // FIXME: Support Sparc quad-precision long double? 6825 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6826 // This is an LP64 platform. 6827 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6828 6829 // OpenBSD uses long long for int64_t and intmax_t. 6830 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6831 IntMaxType = SignedLongLong; 6832 else 6833 IntMaxType = SignedLong; 6834 Int64Type = IntMaxType; 6835 6836 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6837 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6838 LongDoubleWidth = 128; 6839 LongDoubleAlign = 128; 6840 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6841 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6842 } 6843 6844 void getTargetDefines(const LangOptions &Opts, 6845 MacroBuilder &Builder) const override { 6846 SparcTargetInfo::getTargetDefines(Opts, Builder); 6847 Builder.defineMacro("__sparcv9"); 6848 Builder.defineMacro("__arch64__"); 6849 // Solaris doesn't need these variants, but the BSDs do. 6850 if (getTriple().getOS() != llvm::Triple::Solaris) { 6851 Builder.defineMacro("__sparc64__"); 6852 Builder.defineMacro("__sparc_v9__"); 6853 Builder.defineMacro("__sparcv9__"); 6854 } 6855 } 6856 6857 bool setCPU(const std::string &Name) override { 6858 if (!SparcTargetInfo::setCPU(Name)) 6859 return false; 6860 return getCPUGeneration(CPU) == CG_V9; 6861 } 6862 }; 6863 6864 class SystemZTargetInfo : public TargetInfo { 6865 static const Builtin::Info BuiltinInfo[]; 6866 static const char *const GCCRegNames[]; 6867 std::string CPU; 6868 bool HasTransactionalExecution; 6869 bool HasVector; 6870 6871 public: 6872 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6873 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6874 HasVector(false) { 6875 IntMaxType = SignedLong; 6876 Int64Type = SignedLong; 6877 TLSSupported = true; 6878 IntWidth = IntAlign = 32; 6879 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6880 PointerWidth = PointerAlign = 64; 6881 LongDoubleWidth = 128; 6882 LongDoubleAlign = 64; 6883 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6884 DefaultAlignForAttributeAligned = 64; 6885 MinGlobalAlign = 16; 6886 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 6887 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6888 } 6889 void getTargetDefines(const LangOptions &Opts, 6890 MacroBuilder &Builder) const override { 6891 Builder.defineMacro("__s390__"); 6892 Builder.defineMacro("__s390x__"); 6893 Builder.defineMacro("__zarch__"); 6894 Builder.defineMacro("__LONG_DOUBLE_128__"); 6895 6896 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6897 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6898 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6899 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6900 6901 if (HasTransactionalExecution) 6902 Builder.defineMacro("__HTM__"); 6903 if (Opts.ZVector) 6904 Builder.defineMacro("__VEC__", "10301"); 6905 } 6906 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6907 return llvm::makeArrayRef(BuiltinInfo, 6908 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6909 } 6910 6911 ArrayRef<const char *> getGCCRegNames() const override; 6912 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6913 // No aliases. 6914 return None; 6915 } 6916 bool validateAsmConstraint(const char *&Name, 6917 TargetInfo::ConstraintInfo &info) const override; 6918 const char *getClobbers() const override { 6919 // FIXME: Is this really right? 6920 return ""; 6921 } 6922 BuiltinVaListKind getBuiltinVaListKind() const override { 6923 return TargetInfo::SystemZBuiltinVaList; 6924 } 6925 bool setCPU(const std::string &Name) override { 6926 CPU = Name; 6927 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6928 .Case("z10", true) 6929 .Case("z196", true) 6930 .Case("zEC12", true) 6931 .Case("z13", true) 6932 .Default(false); 6933 6934 return CPUKnown; 6935 } 6936 bool 6937 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6938 StringRef CPU, 6939 const std::vector<std::string> &FeaturesVec) const override { 6940 if (CPU == "zEC12") 6941 Features["transactional-execution"] = true; 6942 if (CPU == "z13") { 6943 Features["transactional-execution"] = true; 6944 Features["vector"] = true; 6945 } 6946 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6947 } 6948 6949 bool handleTargetFeatures(std::vector<std::string> &Features, 6950 DiagnosticsEngine &Diags) override { 6951 HasTransactionalExecution = false; 6952 for (const auto &Feature : Features) { 6953 if (Feature == "+transactional-execution") 6954 HasTransactionalExecution = true; 6955 else if (Feature == "+vector") 6956 HasVector = true; 6957 } 6958 // If we use the vector ABI, vector types are 64-bit aligned. 6959 if (HasVector) { 6960 MaxVectorAlign = 64; 6961 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6962 "-v128:64-a:8:16-n32:64"); 6963 } 6964 return true; 6965 } 6966 6967 bool hasFeature(StringRef Feature) const override { 6968 return llvm::StringSwitch<bool>(Feature) 6969 .Case("systemz", true) 6970 .Case("htm", HasTransactionalExecution) 6971 .Case("vx", HasVector) 6972 .Default(false); 6973 } 6974 6975 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6976 switch (CC) { 6977 case CC_C: 6978 case CC_Swift: 6979 return CCCR_OK; 6980 default: 6981 return CCCR_Warning; 6982 } 6983 } 6984 6985 StringRef getABI() const override { 6986 if (HasVector) 6987 return "vector"; 6988 return ""; 6989 } 6990 6991 bool useFloat128ManglingForLongDouble() const override { 6992 return true; 6993 } 6994 }; 6995 6996 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6997 #define BUILTIN(ID, TYPE, ATTRS) \ 6998 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6999 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7000 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 7001 #include "clang/Basic/BuiltinsSystemZ.def" 7002 }; 7003 7004 const char *const SystemZTargetInfo::GCCRegNames[] = { 7005 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7006 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7007 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 7008 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 7009 }; 7010 7011 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 7012 return llvm::makeArrayRef(GCCRegNames); 7013 } 7014 7015 bool SystemZTargetInfo:: 7016 validateAsmConstraint(const char *&Name, 7017 TargetInfo::ConstraintInfo &Info) const { 7018 switch (*Name) { 7019 default: 7020 return false; 7021 7022 case 'a': // Address register 7023 case 'd': // Data register (equivalent to 'r') 7024 case 'f': // Floating-point register 7025 Info.setAllowsRegister(); 7026 return true; 7027 7028 case 'I': // Unsigned 8-bit constant 7029 case 'J': // Unsigned 12-bit constant 7030 case 'K': // Signed 16-bit constant 7031 case 'L': // Signed 20-bit displacement (on all targets we support) 7032 case 'M': // 0x7fffffff 7033 return true; 7034 7035 case 'Q': // Memory with base and unsigned 12-bit displacement 7036 case 'R': // Likewise, plus an index 7037 case 'S': // Memory with base and signed 20-bit displacement 7038 case 'T': // Likewise, plus an index 7039 Info.setAllowsMemory(); 7040 return true; 7041 } 7042 } 7043 7044 class MSP430TargetInfo : public TargetInfo { 7045 static const char *const GCCRegNames[]; 7046 7047 public: 7048 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7049 : TargetInfo(Triple) { 7050 TLSSupported = false; 7051 IntWidth = 16; 7052 IntAlign = 16; 7053 LongWidth = 32; 7054 LongLongWidth = 64; 7055 LongAlign = LongLongAlign = 16; 7056 PointerWidth = 16; 7057 PointerAlign = 16; 7058 SuitableAlign = 16; 7059 SizeType = UnsignedInt; 7060 IntMaxType = SignedLongLong; 7061 IntPtrType = SignedInt; 7062 PtrDiffType = SignedInt; 7063 SigAtomicType = SignedLong; 7064 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 7065 } 7066 void getTargetDefines(const LangOptions &Opts, 7067 MacroBuilder &Builder) const override { 7068 Builder.defineMacro("MSP430"); 7069 Builder.defineMacro("__MSP430__"); 7070 // FIXME: defines for different 'flavours' of MCU 7071 } 7072 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7073 // FIXME: Implement. 7074 return None; 7075 } 7076 bool hasFeature(StringRef Feature) const override { 7077 return Feature == "msp430"; 7078 } 7079 ArrayRef<const char *> getGCCRegNames() const override; 7080 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7081 // No aliases. 7082 return None; 7083 } 7084 bool validateAsmConstraint(const char *&Name, 7085 TargetInfo::ConstraintInfo &info) const override { 7086 // FIXME: implement 7087 switch (*Name) { 7088 case 'K': // the constant 1 7089 case 'L': // constant -1^20 .. 1^19 7090 case 'M': // constant 1-4: 7091 return true; 7092 } 7093 // No target constraints for now. 7094 return false; 7095 } 7096 const char *getClobbers() const override { 7097 // FIXME: Is this really right? 7098 return ""; 7099 } 7100 BuiltinVaListKind getBuiltinVaListKind() const override { 7101 // FIXME: implement 7102 return TargetInfo::CharPtrBuiltinVaList; 7103 } 7104 }; 7105 7106 const char *const MSP430TargetInfo::GCCRegNames[] = { 7107 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7108 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7109 7110 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7111 return llvm::makeArrayRef(GCCRegNames); 7112 } 7113 7114 // LLVM and Clang cannot be used directly to output native binaries for 7115 // target, but is used to compile C code to llvm bitcode with correct 7116 // type and alignment information. 7117 // 7118 // TCE uses the llvm bitcode as input and uses it for generating customized 7119 // target processor and program binary. TCE co-design environment is 7120 // publicly available in http://tce.cs.tut.fi 7121 7122 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7123 3, // opencl_global 7124 4, // opencl_local 7125 5, // opencl_constant 7126 // FIXME: generic has to be added to the target 7127 0, // opencl_generic 7128 0, // cuda_device 7129 0, // cuda_constant 7130 0 // cuda_shared 7131 }; 7132 7133 class TCETargetInfo : public TargetInfo { 7134 public: 7135 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7136 : TargetInfo(Triple) { 7137 TLSSupported = false; 7138 IntWidth = 32; 7139 LongWidth = LongLongWidth = 32; 7140 PointerWidth = 32; 7141 IntAlign = 32; 7142 LongAlign = LongLongAlign = 32; 7143 PointerAlign = 32; 7144 SuitableAlign = 32; 7145 SizeType = UnsignedInt; 7146 IntMaxType = SignedLong; 7147 IntPtrType = SignedInt; 7148 PtrDiffType = SignedInt; 7149 FloatWidth = 32; 7150 FloatAlign = 32; 7151 DoubleWidth = 32; 7152 DoubleAlign = 32; 7153 LongDoubleWidth = 32; 7154 LongDoubleAlign = 32; 7155 FloatFormat = &llvm::APFloat::IEEEsingle; 7156 DoubleFormat = &llvm::APFloat::IEEEsingle; 7157 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 7158 resetDataLayout("E-p:32:32-i8:8:32-i16:16:32-i64:32" 7159 "-f64:32-v64:32-v128:32-a:0:32-n32"); 7160 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7161 UseAddrSpaceMapMangling = true; 7162 } 7163 7164 void getTargetDefines(const LangOptions &Opts, 7165 MacroBuilder &Builder) const override { 7166 DefineStd(Builder, "tce", Opts); 7167 Builder.defineMacro("__TCE__"); 7168 Builder.defineMacro("__TCE_V1__"); 7169 } 7170 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7171 7172 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7173 const char *getClobbers() const override { return ""; } 7174 BuiltinVaListKind getBuiltinVaListKind() const override { 7175 return TargetInfo::VoidPtrBuiltinVaList; 7176 } 7177 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7178 bool validateAsmConstraint(const char *&Name, 7179 TargetInfo::ConstraintInfo &info) const override { 7180 return true; 7181 } 7182 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7183 return None; 7184 } 7185 }; 7186 7187 class BPFTargetInfo : public TargetInfo { 7188 public: 7189 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7190 : TargetInfo(Triple) { 7191 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7192 SizeType = UnsignedLong; 7193 PtrDiffType = SignedLong; 7194 IntPtrType = SignedLong; 7195 IntMaxType = SignedLong; 7196 Int64Type = SignedLong; 7197 RegParmMax = 5; 7198 if (Triple.getArch() == llvm::Triple::bpfeb) { 7199 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7200 } else { 7201 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7202 } 7203 MaxAtomicPromoteWidth = 64; 7204 MaxAtomicInlineWidth = 64; 7205 TLSSupported = false; 7206 } 7207 void getTargetDefines(const LangOptions &Opts, 7208 MacroBuilder &Builder) const override { 7209 DefineStd(Builder, "bpf", Opts); 7210 Builder.defineMacro("__BPF__"); 7211 } 7212 bool hasFeature(StringRef Feature) const override { 7213 return Feature == "bpf"; 7214 } 7215 7216 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7217 const char *getClobbers() const override { 7218 return ""; 7219 } 7220 BuiltinVaListKind getBuiltinVaListKind() const override { 7221 return TargetInfo::VoidPtrBuiltinVaList; 7222 } 7223 ArrayRef<const char *> getGCCRegNames() const override { 7224 return None; 7225 } 7226 bool validateAsmConstraint(const char *&Name, 7227 TargetInfo::ConstraintInfo &info) const override { 7228 return true; 7229 } 7230 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7231 return None; 7232 } 7233 }; 7234 7235 class MipsTargetInfo : public TargetInfo { 7236 void setDataLayout() { 7237 StringRef Layout; 7238 7239 if (ABI == "o32") 7240 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7241 else if (ABI == "n32") 7242 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7243 else if (ABI == "n64") 7244 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7245 else 7246 llvm_unreachable("Invalid ABI"); 7247 7248 if (BigEndian) 7249 resetDataLayout(("E-" + Layout).str()); 7250 else 7251 resetDataLayout(("e-" + Layout).str()); 7252 } 7253 7254 7255 static const Builtin::Info BuiltinInfo[]; 7256 std::string CPU; 7257 bool IsMips16; 7258 bool IsMicromips; 7259 bool IsNan2008; 7260 bool IsSingleFloat; 7261 enum MipsFloatABI { 7262 HardFloat, SoftFloat 7263 } FloatABI; 7264 enum DspRevEnum { 7265 NoDSP, DSP1, DSP2 7266 } DspRev; 7267 bool HasMSA; 7268 7269 protected: 7270 bool HasFP64; 7271 std::string ABI; 7272 7273 public: 7274 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7275 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7276 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 7277 DspRev(NoDSP), HasMSA(false), HasFP64(false) { 7278 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7279 7280 setABI((getTriple().getArch() == llvm::Triple::mips || 7281 getTriple().getArch() == llvm::Triple::mipsel) 7282 ? "o32" 7283 : "n64"); 7284 7285 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7286 } 7287 7288 bool isNaN2008Default() const { 7289 return CPU == "mips32r6" || CPU == "mips64r6"; 7290 } 7291 7292 bool isFP64Default() const { 7293 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7294 } 7295 7296 bool isNan2008() const override { 7297 return IsNan2008; 7298 } 7299 7300 bool processorSupportsGPR64() const { 7301 return llvm::StringSwitch<bool>(CPU) 7302 .Case("mips3", true) 7303 .Case("mips4", true) 7304 .Case("mips5", true) 7305 .Case("mips64", true) 7306 .Case("mips64r2", true) 7307 .Case("mips64r3", true) 7308 .Case("mips64r5", true) 7309 .Case("mips64r6", true) 7310 .Case("octeon", true) 7311 .Default(false); 7312 return false; 7313 } 7314 7315 StringRef getABI() const override { return ABI; } 7316 bool setABI(const std::string &Name) override { 7317 if (Name == "o32") { 7318 setO32ABITypes(); 7319 ABI = Name; 7320 return true; 7321 } 7322 7323 if (Name == "n32") { 7324 setN32ABITypes(); 7325 ABI = Name; 7326 return true; 7327 } 7328 if (Name == "n64") { 7329 setN64ABITypes(); 7330 ABI = Name; 7331 return true; 7332 } 7333 return false; 7334 } 7335 7336 void setO32ABITypes() { 7337 Int64Type = SignedLongLong; 7338 IntMaxType = Int64Type; 7339 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7340 LongDoubleWidth = LongDoubleAlign = 64; 7341 LongWidth = LongAlign = 32; 7342 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7343 PointerWidth = PointerAlign = 32; 7344 PtrDiffType = SignedInt; 7345 SizeType = UnsignedInt; 7346 SuitableAlign = 64; 7347 } 7348 7349 void setN32N64ABITypes() { 7350 LongDoubleWidth = LongDoubleAlign = 128; 7351 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7352 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7353 LongDoubleWidth = LongDoubleAlign = 64; 7354 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7355 } 7356 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7357 SuitableAlign = 128; 7358 } 7359 7360 void setN64ABITypes() { 7361 setN32N64ABITypes(); 7362 Int64Type = SignedLong; 7363 IntMaxType = Int64Type; 7364 LongWidth = LongAlign = 64; 7365 PointerWidth = PointerAlign = 64; 7366 PtrDiffType = SignedLong; 7367 SizeType = UnsignedLong; 7368 } 7369 7370 void setN32ABITypes() { 7371 setN32N64ABITypes(); 7372 Int64Type = SignedLongLong; 7373 IntMaxType = Int64Type; 7374 LongWidth = LongAlign = 32; 7375 PointerWidth = PointerAlign = 32; 7376 PtrDiffType = SignedInt; 7377 SizeType = UnsignedInt; 7378 } 7379 7380 bool setCPU(const std::string &Name) override { 7381 CPU = Name; 7382 return llvm::StringSwitch<bool>(Name) 7383 .Case("mips1", true) 7384 .Case("mips2", true) 7385 .Case("mips3", true) 7386 .Case("mips4", true) 7387 .Case("mips5", true) 7388 .Case("mips32", true) 7389 .Case("mips32r2", true) 7390 .Case("mips32r3", true) 7391 .Case("mips32r5", true) 7392 .Case("mips32r6", true) 7393 .Case("mips64", true) 7394 .Case("mips64r2", true) 7395 .Case("mips64r3", true) 7396 .Case("mips64r5", true) 7397 .Case("mips64r6", true) 7398 .Case("octeon", true) 7399 .Case("p5600", true) 7400 .Default(false); 7401 } 7402 const std::string& getCPU() const { return CPU; } 7403 bool 7404 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7405 StringRef CPU, 7406 const std::vector<std::string> &FeaturesVec) const override { 7407 if (CPU.empty()) 7408 CPU = getCPU(); 7409 if (CPU == "octeon") 7410 Features["mips64r2"] = Features["cnmips"] = true; 7411 else 7412 Features[CPU] = true; 7413 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7414 } 7415 7416 void getTargetDefines(const LangOptions &Opts, 7417 MacroBuilder &Builder) const override { 7418 if (BigEndian) { 7419 DefineStd(Builder, "MIPSEB", Opts); 7420 Builder.defineMacro("_MIPSEB"); 7421 } else { 7422 DefineStd(Builder, "MIPSEL", Opts); 7423 Builder.defineMacro("_MIPSEL"); 7424 } 7425 7426 Builder.defineMacro("__mips__"); 7427 Builder.defineMacro("_mips"); 7428 if (Opts.GNUMode) 7429 Builder.defineMacro("mips"); 7430 7431 if (ABI == "o32") { 7432 Builder.defineMacro("__mips", "32"); 7433 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7434 } else { 7435 Builder.defineMacro("__mips", "64"); 7436 Builder.defineMacro("__mips64"); 7437 Builder.defineMacro("__mips64__"); 7438 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7439 } 7440 7441 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7442 .Cases("mips32", "mips64", "1") 7443 .Cases("mips32r2", "mips64r2", "2") 7444 .Cases("mips32r3", "mips64r3", "3") 7445 .Cases("mips32r5", "mips64r5", "5") 7446 .Cases("mips32r6", "mips64r6", "6") 7447 .Default(""); 7448 if (!ISARev.empty()) 7449 Builder.defineMacro("__mips_isa_rev", ISARev); 7450 7451 if (ABI == "o32") { 7452 Builder.defineMacro("__mips_o32"); 7453 Builder.defineMacro("_ABIO32", "1"); 7454 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7455 } else if (ABI == "n32") { 7456 Builder.defineMacro("__mips_n32"); 7457 Builder.defineMacro("_ABIN32", "2"); 7458 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7459 } else if (ABI == "n64") { 7460 Builder.defineMacro("__mips_n64"); 7461 Builder.defineMacro("_ABI64", "3"); 7462 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7463 } else 7464 llvm_unreachable("Invalid ABI."); 7465 7466 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7467 7468 switch (FloatABI) { 7469 case HardFloat: 7470 Builder.defineMacro("__mips_hard_float", Twine(1)); 7471 break; 7472 case SoftFloat: 7473 Builder.defineMacro("__mips_soft_float", Twine(1)); 7474 break; 7475 } 7476 7477 if (IsSingleFloat) 7478 Builder.defineMacro("__mips_single_float", Twine(1)); 7479 7480 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7481 Builder.defineMacro("_MIPS_FPSET", 7482 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7483 7484 if (IsMips16) 7485 Builder.defineMacro("__mips16", Twine(1)); 7486 7487 if (IsMicromips) 7488 Builder.defineMacro("__mips_micromips", Twine(1)); 7489 7490 if (IsNan2008) 7491 Builder.defineMacro("__mips_nan2008", Twine(1)); 7492 7493 switch (DspRev) { 7494 default: 7495 break; 7496 case DSP1: 7497 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7498 Builder.defineMacro("__mips_dsp", Twine(1)); 7499 break; 7500 case DSP2: 7501 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7502 Builder.defineMacro("__mips_dspr2", Twine(1)); 7503 Builder.defineMacro("__mips_dsp", Twine(1)); 7504 break; 7505 } 7506 7507 if (HasMSA) 7508 Builder.defineMacro("__mips_msa", Twine(1)); 7509 7510 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7511 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7512 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7513 7514 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7515 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7516 7517 // These shouldn't be defined for MIPS-I but there's no need to check 7518 // for that since MIPS-I isn't supported. 7519 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7520 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7521 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7522 7523 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7524 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7525 // the instructions exist but using them violates the ABI since they 7526 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7527 if (ABI == "n32" || ABI == "n64") 7528 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7529 } 7530 7531 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7532 return llvm::makeArrayRef(BuiltinInfo, 7533 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7534 } 7535 bool hasFeature(StringRef Feature) const override { 7536 return llvm::StringSwitch<bool>(Feature) 7537 .Case("mips", true) 7538 .Case("fp64", HasFP64) 7539 .Default(false); 7540 } 7541 BuiltinVaListKind getBuiltinVaListKind() const override { 7542 return TargetInfo::VoidPtrBuiltinVaList; 7543 } 7544 ArrayRef<const char *> getGCCRegNames() const override { 7545 static const char *const GCCRegNames[] = { 7546 // CPU register names 7547 // Must match second column of GCCRegAliases 7548 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7549 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7550 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7551 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7552 // Floating point register names 7553 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7554 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7555 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7556 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7557 // Hi/lo and condition register names 7558 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7559 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7560 "$ac3hi","$ac3lo", 7561 // MSA register names 7562 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7563 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7564 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7565 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7566 // MSA control register names 7567 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7568 "$msarequest", "$msamap", "$msaunmap" 7569 }; 7570 return llvm::makeArrayRef(GCCRegNames); 7571 } 7572 bool validateAsmConstraint(const char *&Name, 7573 TargetInfo::ConstraintInfo &Info) const override { 7574 switch (*Name) { 7575 default: 7576 return false; 7577 case 'r': // CPU registers. 7578 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7579 case 'y': // Equivalent to "r", backward compatibility only. 7580 case 'f': // floating-point registers. 7581 case 'c': // $25 for indirect jumps 7582 case 'l': // lo register 7583 case 'x': // hilo register pair 7584 Info.setAllowsRegister(); 7585 return true; 7586 case 'I': // Signed 16-bit constant 7587 case 'J': // Integer 0 7588 case 'K': // Unsigned 16-bit constant 7589 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7590 case 'M': // Constants not loadable via lui, addiu, or ori 7591 case 'N': // Constant -1 to -65535 7592 case 'O': // A signed 15-bit constant 7593 case 'P': // A constant between 1 go 65535 7594 return true; 7595 case 'R': // An address that can be used in a non-macro load or store 7596 Info.setAllowsMemory(); 7597 return true; 7598 case 'Z': 7599 if (Name[1] == 'C') { // An address usable by ll, and sc. 7600 Info.setAllowsMemory(); 7601 Name++; // Skip over 'Z'. 7602 return true; 7603 } 7604 return false; 7605 } 7606 } 7607 7608 std::string convertConstraint(const char *&Constraint) const override { 7609 std::string R; 7610 switch (*Constraint) { 7611 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7612 if (Constraint[1] == 'C') { 7613 R = std::string("^") + std::string(Constraint, 2); 7614 Constraint++; 7615 return R; 7616 } 7617 break; 7618 } 7619 return TargetInfo::convertConstraint(Constraint); 7620 } 7621 7622 const char *getClobbers() const override { 7623 // In GCC, $1 is not widely used in generated code (it's used only in a few 7624 // specific situations), so there is no real need for users to add it to 7625 // the clobbers list if they want to use it in their inline assembly code. 7626 // 7627 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7628 // code generation, so using it in inline assembly without adding it to the 7629 // clobbers list can cause conflicts between the inline assembly code and 7630 // the surrounding generated code. 7631 // 7632 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7633 // operands, which will conflict with the ".set at" assembler option (which 7634 // we use only for inline assembly, in order to maintain compatibility with 7635 // GCC) and will also conflict with the user's usage of $1. 7636 // 7637 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7638 // register for generated code is to automatically clobber $1 for all inline 7639 // assembly code. 7640 // 7641 // FIXME: We should automatically clobber $1 only for inline assembly code 7642 // which actually uses it. This would allow LLVM to use $1 for inline 7643 // assembly operands if the user's assembly code doesn't use it. 7644 return "~{$1}"; 7645 } 7646 7647 bool handleTargetFeatures(std::vector<std::string> &Features, 7648 DiagnosticsEngine &Diags) override { 7649 IsMips16 = false; 7650 IsMicromips = false; 7651 IsNan2008 = isNaN2008Default(); 7652 IsSingleFloat = false; 7653 FloatABI = HardFloat; 7654 DspRev = NoDSP; 7655 HasFP64 = isFP64Default(); 7656 7657 for (const auto &Feature : Features) { 7658 if (Feature == "+single-float") 7659 IsSingleFloat = true; 7660 else if (Feature == "+soft-float") 7661 FloatABI = SoftFloat; 7662 else if (Feature == "+mips16") 7663 IsMips16 = true; 7664 else if (Feature == "+micromips") 7665 IsMicromips = true; 7666 else if (Feature == "+dsp") 7667 DspRev = std::max(DspRev, DSP1); 7668 else if (Feature == "+dspr2") 7669 DspRev = std::max(DspRev, DSP2); 7670 else if (Feature == "+msa") 7671 HasMSA = true; 7672 else if (Feature == "+fp64") 7673 HasFP64 = true; 7674 else if (Feature == "-fp64") 7675 HasFP64 = false; 7676 else if (Feature == "+nan2008") 7677 IsNan2008 = true; 7678 else if (Feature == "-nan2008") 7679 IsNan2008 = false; 7680 } 7681 7682 setDataLayout(); 7683 7684 return true; 7685 } 7686 7687 int getEHDataRegisterNumber(unsigned RegNo) const override { 7688 if (RegNo == 0) return 4; 7689 if (RegNo == 1) return 5; 7690 return -1; 7691 } 7692 7693 bool isCLZForZeroUndef() const override { return false; } 7694 7695 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7696 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 7697 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7698 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7699 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 7700 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 7701 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 7702 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7703 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7704 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7705 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7706 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7707 {{"ra"}, "$31"}}; 7708 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 7709 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7710 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7711 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 7712 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 7713 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 7714 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7715 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7716 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7717 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7718 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7719 {{"ra"}, "$31"}}; 7720 if (ABI == "o32") 7721 return llvm::makeArrayRef(O32RegAliases); 7722 return llvm::makeArrayRef(NewABIRegAliases); 7723 } 7724 7725 bool hasInt128Type() const override { 7726 return ABI == "n32" || ABI == "n64"; 7727 } 7728 7729 bool validateTarget(DiagnosticsEngine &Diags) const override { 7730 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 7731 // this yet. It's better to fail here than on the backend assertion. 7732 if (processorSupportsGPR64() && ABI == "o32") { 7733 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7734 return false; 7735 } 7736 7737 // 64-bit ABI's require 64-bit CPU's. 7738 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 7739 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7740 return false; 7741 } 7742 7743 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 7744 // can't handle this yet. It's better to fail here than on the 7745 // backend assertion. 7746 if ((getTriple().getArch() == llvm::Triple::mips64 || 7747 getTriple().getArch() == llvm::Triple::mips64el) && 7748 ABI == "o32") { 7749 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7750 << ABI << getTriple().str(); 7751 return false; 7752 } 7753 7754 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 7755 // can't handle this yet. It's better to fail here than on the 7756 // backend assertion. 7757 if ((getTriple().getArch() == llvm::Triple::mips || 7758 getTriple().getArch() == llvm::Triple::mipsel) && 7759 (ABI == "n32" || ABI == "n64")) { 7760 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7761 << ABI << getTriple().str(); 7762 return false; 7763 } 7764 7765 return true; 7766 } 7767 }; 7768 7769 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 7770 #define BUILTIN(ID, TYPE, ATTRS) \ 7771 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7772 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7773 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7774 #include "clang/Basic/BuiltinsMips.def" 7775 }; 7776 7777 class PNaClTargetInfo : public TargetInfo { 7778 public: 7779 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7780 : TargetInfo(Triple) { 7781 this->LongAlign = 32; 7782 this->LongWidth = 32; 7783 this->PointerAlign = 32; 7784 this->PointerWidth = 32; 7785 this->IntMaxType = TargetInfo::SignedLongLong; 7786 this->Int64Type = TargetInfo::SignedLongLong; 7787 this->DoubleAlign = 64; 7788 this->LongDoubleWidth = 64; 7789 this->LongDoubleAlign = 64; 7790 this->SizeType = TargetInfo::UnsignedInt; 7791 this->PtrDiffType = TargetInfo::SignedInt; 7792 this->IntPtrType = TargetInfo::SignedInt; 7793 this->RegParmMax = 0; // Disallow regparm 7794 } 7795 7796 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7797 Builder.defineMacro("__le32__"); 7798 Builder.defineMacro("__pnacl__"); 7799 } 7800 void getTargetDefines(const LangOptions &Opts, 7801 MacroBuilder &Builder) const override { 7802 getArchDefines(Opts, Builder); 7803 } 7804 bool hasFeature(StringRef Feature) const override { 7805 return Feature == "pnacl"; 7806 } 7807 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7808 BuiltinVaListKind getBuiltinVaListKind() const override { 7809 return TargetInfo::PNaClABIBuiltinVaList; 7810 } 7811 ArrayRef<const char *> getGCCRegNames() const override; 7812 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7813 bool validateAsmConstraint(const char *&Name, 7814 TargetInfo::ConstraintInfo &Info) const override { 7815 return false; 7816 } 7817 7818 const char *getClobbers() const override { 7819 return ""; 7820 } 7821 }; 7822 7823 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7824 return None; 7825 } 7826 7827 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7828 return None; 7829 } 7830 7831 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7832 class NaClMips32TargetInfo : public MipsTargetInfo { 7833 public: 7834 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7835 : MipsTargetInfo(Triple, Opts) {} 7836 7837 BuiltinVaListKind getBuiltinVaListKind() const override { 7838 return TargetInfo::PNaClABIBuiltinVaList; 7839 } 7840 }; 7841 7842 class Le64TargetInfo : public TargetInfo { 7843 static const Builtin::Info BuiltinInfo[]; 7844 7845 public: 7846 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7847 : TargetInfo(Triple) { 7848 NoAsmVariants = true; 7849 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7850 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7851 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 7852 } 7853 7854 void getTargetDefines(const LangOptions &Opts, 7855 MacroBuilder &Builder) const override { 7856 DefineStd(Builder, "unix", Opts); 7857 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7858 Builder.defineMacro("__ELF__"); 7859 } 7860 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7861 return llvm::makeArrayRef(BuiltinInfo, 7862 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7863 } 7864 BuiltinVaListKind getBuiltinVaListKind() const override { 7865 return TargetInfo::PNaClABIBuiltinVaList; 7866 } 7867 const char *getClobbers() const override { return ""; } 7868 ArrayRef<const char *> getGCCRegNames() const override { 7869 return None; 7870 } 7871 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7872 return None; 7873 } 7874 bool validateAsmConstraint(const char *&Name, 7875 TargetInfo::ConstraintInfo &Info) const override { 7876 return false; 7877 } 7878 7879 bool hasProtectedVisibility() const override { return false; } 7880 }; 7881 7882 class WebAssemblyTargetInfo : public TargetInfo { 7883 static const Builtin::Info BuiltinInfo[]; 7884 7885 enum SIMDEnum { 7886 NoSIMD, 7887 SIMD128, 7888 } SIMDLevel; 7889 7890 public: 7891 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 7892 : TargetInfo(T), SIMDLevel(NoSIMD) { 7893 NoAsmVariants = true; 7894 SuitableAlign = 128; 7895 LargeArrayMinWidth = 128; 7896 LargeArrayAlign = 128; 7897 SimdDefaultAlign = 128; 7898 SigAtomicType = SignedLong; 7899 LongDoubleWidth = LongDoubleAlign = 128; 7900 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7901 SizeType = UnsignedInt; 7902 PtrDiffType = SignedInt; 7903 IntPtrType = SignedInt; 7904 } 7905 7906 protected: 7907 void getTargetDefines(const LangOptions &Opts, 7908 MacroBuilder &Builder) const override { 7909 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7910 if (SIMDLevel >= SIMD128) 7911 Builder.defineMacro("__wasm_simd128__"); 7912 } 7913 7914 private: 7915 bool 7916 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7917 StringRef CPU, 7918 const std::vector<std::string> &FeaturesVec) const override { 7919 if (CPU == "bleeding-edge") 7920 Features["simd128"] = true; 7921 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7922 } 7923 bool hasFeature(StringRef Feature) const final { 7924 return llvm::StringSwitch<bool>(Feature) 7925 .Case("simd128", SIMDLevel >= SIMD128) 7926 .Default(false); 7927 } 7928 bool handleTargetFeatures(std::vector<std::string> &Features, 7929 DiagnosticsEngine &Diags) final { 7930 for (const auto &Feature : Features) { 7931 if (Feature == "+simd128") { 7932 SIMDLevel = std::max(SIMDLevel, SIMD128); 7933 continue; 7934 } 7935 if (Feature == "-simd128") { 7936 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7937 continue; 7938 } 7939 7940 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7941 << "-target-feature"; 7942 return false; 7943 } 7944 return true; 7945 } 7946 bool setCPU(const std::string &Name) final { 7947 return llvm::StringSwitch<bool>(Name) 7948 .Case("mvp", true) 7949 .Case("bleeding-edge", true) 7950 .Case("generic", true) 7951 .Default(false); 7952 } 7953 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7954 return llvm::makeArrayRef(BuiltinInfo, 7955 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7956 } 7957 BuiltinVaListKind getBuiltinVaListKind() const final { 7958 return VoidPtrBuiltinVaList; 7959 } 7960 ArrayRef<const char *> getGCCRegNames() const final { 7961 return None; 7962 } 7963 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7964 return None; 7965 } 7966 bool 7967 validateAsmConstraint(const char *&Name, 7968 TargetInfo::ConstraintInfo &Info) const final { 7969 return false; 7970 } 7971 const char *getClobbers() const final { return ""; } 7972 bool isCLZForZeroUndef() const final { return false; } 7973 bool hasInt128Type() const final { return true; } 7974 IntType getIntTypeByWidth(unsigned BitWidth, 7975 bool IsSigned) const final { 7976 // WebAssembly prefers long long for explicitly 64-bit integers. 7977 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7978 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7979 } 7980 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7981 bool IsSigned) const final { 7982 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7983 return BitWidth == 64 7984 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7985 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7986 } 7987 }; 7988 7989 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7990 #define BUILTIN(ID, TYPE, ATTRS) \ 7991 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7992 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7993 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7994 #include "clang/Basic/BuiltinsWebAssembly.def" 7995 }; 7996 7997 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7998 public: 7999 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 8000 const TargetOptions &Opts) 8001 : WebAssemblyTargetInfo(T, Opts) { 8002 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 8003 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 8004 } 8005 8006 protected: 8007 void getTargetDefines(const LangOptions &Opts, 8008 MacroBuilder &Builder) const override { 8009 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8010 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 8011 } 8012 }; 8013 8014 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 8015 public: 8016 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 8017 const TargetOptions &Opts) 8018 : WebAssemblyTargetInfo(T, Opts) { 8019 LongAlign = LongWidth = 64; 8020 PointerAlign = PointerWidth = 64; 8021 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8022 SizeType = UnsignedLong; 8023 PtrDiffType = SignedLong; 8024 IntPtrType = SignedLong; 8025 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 8026 } 8027 8028 protected: 8029 void getTargetDefines(const LangOptions &Opts, 8030 MacroBuilder &Builder) const override { 8031 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8032 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 8033 } 8034 }; 8035 8036 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 8037 #define BUILTIN(ID, TYPE, ATTRS) \ 8038 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8039 #include "clang/Basic/BuiltinsLe64.def" 8040 }; 8041 8042 static const unsigned SPIRAddrSpaceMap[] = { 8043 1, // opencl_global 8044 3, // opencl_local 8045 2, // opencl_constant 8046 4, // opencl_generic 8047 0, // cuda_device 8048 0, // cuda_constant 8049 0 // cuda_shared 8050 }; 8051 class SPIRTargetInfo : public TargetInfo { 8052 public: 8053 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8054 : TargetInfo(Triple) { 8055 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 8056 "SPIR target must use unknown OS"); 8057 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 8058 "SPIR target must use unknown environment type"); 8059 TLSSupported = false; 8060 LongWidth = LongAlign = 64; 8061 AddrSpaceMap = &SPIRAddrSpaceMap; 8062 UseAddrSpaceMapMangling = true; 8063 // Define available target features 8064 // These must be defined in sorted order! 8065 NoAsmVariants = true; 8066 } 8067 void getTargetDefines(const LangOptions &Opts, 8068 MacroBuilder &Builder) const override { 8069 DefineStd(Builder, "SPIR", Opts); 8070 } 8071 bool hasFeature(StringRef Feature) const override { 8072 return Feature == "spir"; 8073 } 8074 8075 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8076 const char *getClobbers() const override { return ""; } 8077 ArrayRef<const char *> getGCCRegNames() const override { return None; } 8078 bool validateAsmConstraint(const char *&Name, 8079 TargetInfo::ConstraintInfo &info) const override { 8080 return true; 8081 } 8082 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8083 return None; 8084 } 8085 BuiltinVaListKind getBuiltinVaListKind() const override { 8086 return TargetInfo::VoidPtrBuiltinVaList; 8087 } 8088 8089 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 8090 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 8091 : CCCR_Warning; 8092 } 8093 8094 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8095 return CC_SpirFunction; 8096 } 8097 8098 void setSupportedOpenCLOpts() override { 8099 // Assume all OpenCL extensions and optional core features are supported 8100 // for SPIR since it is a generic target. 8101 getSupportedOpenCLOpts().setAll(); 8102 } 8103 }; 8104 8105 class SPIR32TargetInfo : public SPIRTargetInfo { 8106 public: 8107 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8108 : SPIRTargetInfo(Triple, Opts) { 8109 PointerWidth = PointerAlign = 32; 8110 SizeType = TargetInfo::UnsignedInt; 8111 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8112 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8113 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8114 } 8115 void getTargetDefines(const LangOptions &Opts, 8116 MacroBuilder &Builder) const override { 8117 DefineStd(Builder, "SPIR32", Opts); 8118 } 8119 }; 8120 8121 class SPIR64TargetInfo : public SPIRTargetInfo { 8122 public: 8123 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8124 : SPIRTargetInfo(Triple, Opts) { 8125 PointerWidth = PointerAlign = 64; 8126 SizeType = TargetInfo::UnsignedLong; 8127 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8128 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8129 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8130 } 8131 void getTargetDefines(const LangOptions &Opts, 8132 MacroBuilder &Builder) const override { 8133 DefineStd(Builder, "SPIR64", Opts); 8134 } 8135 }; 8136 8137 class XCoreTargetInfo : public TargetInfo { 8138 static const Builtin::Info BuiltinInfo[]; 8139 public: 8140 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8141 : TargetInfo(Triple) { 8142 NoAsmVariants = true; 8143 LongLongAlign = 32; 8144 SuitableAlign = 32; 8145 DoubleAlign = LongDoubleAlign = 32; 8146 SizeType = UnsignedInt; 8147 PtrDiffType = SignedInt; 8148 IntPtrType = SignedInt; 8149 WCharType = UnsignedChar; 8150 WIntType = UnsignedInt; 8151 UseZeroLengthBitfieldAlignment = true; 8152 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8153 "-f64:32-a:0:32-n32"); 8154 } 8155 void getTargetDefines(const LangOptions &Opts, 8156 MacroBuilder &Builder) const override { 8157 Builder.defineMacro("__XS1B__"); 8158 } 8159 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8160 return llvm::makeArrayRef(BuiltinInfo, 8161 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8162 } 8163 BuiltinVaListKind getBuiltinVaListKind() const override { 8164 return TargetInfo::VoidPtrBuiltinVaList; 8165 } 8166 const char *getClobbers() const override { 8167 return ""; 8168 } 8169 ArrayRef<const char *> getGCCRegNames() const override { 8170 static const char * const GCCRegNames[] = { 8171 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8172 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8173 }; 8174 return llvm::makeArrayRef(GCCRegNames); 8175 } 8176 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8177 return None; 8178 } 8179 bool validateAsmConstraint(const char *&Name, 8180 TargetInfo::ConstraintInfo &Info) const override { 8181 return false; 8182 } 8183 int getEHDataRegisterNumber(unsigned RegNo) const override { 8184 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8185 return (RegNo < 2)? RegNo : -1; 8186 } 8187 bool allowsLargerPreferedTypeAlignment() const override { 8188 return false; 8189 } 8190 }; 8191 8192 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8193 #define BUILTIN(ID, TYPE, ATTRS) \ 8194 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8195 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8196 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8197 #include "clang/Basic/BuiltinsXCore.def" 8198 }; 8199 8200 // x86_32 Android target 8201 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8202 public: 8203 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8204 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8205 SuitableAlign = 32; 8206 LongDoubleWidth = 64; 8207 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 8208 } 8209 }; 8210 8211 // x86_64 Android target 8212 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8213 public: 8214 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8215 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8216 LongDoubleFormat = &llvm::APFloat::IEEEquad; 8217 } 8218 8219 bool useFloat128ManglingForLongDouble() const override { 8220 return true; 8221 } 8222 }; 8223 8224 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8225 class RenderScript32TargetInfo : public ARMleTargetInfo { 8226 public: 8227 RenderScript32TargetInfo(const llvm::Triple &Triple, 8228 const TargetOptions &Opts) 8229 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8230 Triple.getOSName(), 8231 Triple.getEnvironmentName()), 8232 Opts) { 8233 IsRenderScriptTarget = true; 8234 LongWidth = LongAlign = 64; 8235 } 8236 void getTargetDefines(const LangOptions &Opts, 8237 MacroBuilder &Builder) const override { 8238 Builder.defineMacro("__RENDERSCRIPT__"); 8239 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8240 } 8241 }; 8242 8243 // 64-bit RenderScript is aarch64 8244 class RenderScript64TargetInfo : public AArch64leTargetInfo { 8245 public: 8246 RenderScript64TargetInfo(const llvm::Triple &Triple, 8247 const TargetOptions &Opts) 8248 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 8249 Triple.getOSName(), 8250 Triple.getEnvironmentName()), 8251 Opts) { 8252 IsRenderScriptTarget = true; 8253 } 8254 8255 void getTargetDefines(const LangOptions &Opts, 8256 MacroBuilder &Builder) const override { 8257 Builder.defineMacro("__RENDERSCRIPT__"); 8258 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 8259 } 8260 }; 8261 8262 } // end anonymous namespace 8263 8264 //===----------------------------------------------------------------------===// 8265 // Driver code 8266 //===----------------------------------------------------------------------===// 8267 8268 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 8269 const TargetOptions &Opts) { 8270 llvm::Triple::OSType os = Triple.getOS(); 8271 8272 switch (Triple.getArch()) { 8273 default: 8274 return nullptr; 8275 8276 case llvm::Triple::xcore: 8277 return new XCoreTargetInfo(Triple, Opts); 8278 8279 case llvm::Triple::hexagon: 8280 return new HexagonTargetInfo(Triple, Opts); 8281 8282 case llvm::Triple::lanai: 8283 return new LanaiTargetInfo(Triple, Opts); 8284 8285 case llvm::Triple::aarch64: 8286 if (Triple.isOSDarwin()) 8287 return new DarwinAArch64TargetInfo(Triple, Opts); 8288 8289 switch (os) { 8290 case llvm::Triple::CloudABI: 8291 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 8292 case llvm::Triple::FreeBSD: 8293 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8294 case llvm::Triple::Linux: 8295 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8296 case llvm::Triple::NetBSD: 8297 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8298 case llvm::Triple::Fuchsia: 8299 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8300 default: 8301 return new AArch64leTargetInfo(Triple, Opts); 8302 } 8303 8304 case llvm::Triple::aarch64_be: 8305 switch (os) { 8306 case llvm::Triple::FreeBSD: 8307 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8308 case llvm::Triple::Linux: 8309 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8310 case llvm::Triple::NetBSD: 8311 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8312 default: 8313 return new AArch64beTargetInfo(Triple, Opts); 8314 } 8315 8316 case llvm::Triple::arm: 8317 case llvm::Triple::thumb: 8318 if (Triple.isOSBinFormatMachO()) 8319 return new DarwinARMTargetInfo(Triple, Opts); 8320 8321 switch (os) { 8322 case llvm::Triple::CloudABI: 8323 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts); 8324 case llvm::Triple::Linux: 8325 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 8326 case llvm::Triple::FreeBSD: 8327 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8328 case llvm::Triple::NetBSD: 8329 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8330 case llvm::Triple::OpenBSD: 8331 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8332 case llvm::Triple::Bitrig: 8333 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 8334 case llvm::Triple::RTEMS: 8335 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 8336 case llvm::Triple::NaCl: 8337 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 8338 case llvm::Triple::Win32: 8339 switch (Triple.getEnvironment()) { 8340 case llvm::Triple::Cygnus: 8341 return new CygwinARMTargetInfo(Triple, Opts); 8342 case llvm::Triple::GNU: 8343 return new MinGWARMTargetInfo(Triple, Opts); 8344 case llvm::Triple::Itanium: 8345 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 8346 case llvm::Triple::MSVC: 8347 default: // Assume MSVC for unknown environments 8348 return new MicrosoftARMleTargetInfo(Triple, Opts); 8349 } 8350 default: 8351 return new ARMleTargetInfo(Triple, Opts); 8352 } 8353 8354 case llvm::Triple::armeb: 8355 case llvm::Triple::thumbeb: 8356 if (Triple.isOSDarwin()) 8357 return new DarwinARMTargetInfo(Triple, Opts); 8358 8359 switch (os) { 8360 case llvm::Triple::Linux: 8361 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8362 case llvm::Triple::FreeBSD: 8363 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8364 case llvm::Triple::NetBSD: 8365 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8366 case llvm::Triple::OpenBSD: 8367 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8368 case llvm::Triple::Bitrig: 8369 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8370 case llvm::Triple::RTEMS: 8371 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8372 case llvm::Triple::NaCl: 8373 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8374 default: 8375 return new ARMbeTargetInfo(Triple, Opts); 8376 } 8377 8378 case llvm::Triple::bpfeb: 8379 case llvm::Triple::bpfel: 8380 return new BPFTargetInfo(Triple, Opts); 8381 8382 case llvm::Triple::msp430: 8383 return new MSP430TargetInfo(Triple, Opts); 8384 8385 case llvm::Triple::mips: 8386 switch (os) { 8387 case llvm::Triple::Linux: 8388 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8389 case llvm::Triple::RTEMS: 8390 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8391 case llvm::Triple::FreeBSD: 8392 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8393 case llvm::Triple::NetBSD: 8394 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8395 default: 8396 return new MipsTargetInfo(Triple, Opts); 8397 } 8398 8399 case llvm::Triple::mipsel: 8400 switch (os) { 8401 case llvm::Triple::Linux: 8402 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8403 case llvm::Triple::RTEMS: 8404 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8405 case llvm::Triple::FreeBSD: 8406 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8407 case llvm::Triple::NetBSD: 8408 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8409 case llvm::Triple::NaCl: 8410 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 8411 default: 8412 return new MipsTargetInfo(Triple, Opts); 8413 } 8414 8415 case llvm::Triple::mips64: 8416 switch (os) { 8417 case llvm::Triple::Linux: 8418 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8419 case llvm::Triple::RTEMS: 8420 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8421 case llvm::Triple::FreeBSD: 8422 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8423 case llvm::Triple::NetBSD: 8424 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8425 case llvm::Triple::OpenBSD: 8426 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8427 default: 8428 return new MipsTargetInfo(Triple, Opts); 8429 } 8430 8431 case llvm::Triple::mips64el: 8432 switch (os) { 8433 case llvm::Triple::Linux: 8434 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8435 case llvm::Triple::RTEMS: 8436 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8437 case llvm::Triple::FreeBSD: 8438 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8439 case llvm::Triple::NetBSD: 8440 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8441 case llvm::Triple::OpenBSD: 8442 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8443 default: 8444 return new MipsTargetInfo(Triple, Opts); 8445 } 8446 8447 case llvm::Triple::le32: 8448 switch (os) { 8449 case llvm::Triple::NaCl: 8450 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 8451 default: 8452 return nullptr; 8453 } 8454 8455 case llvm::Triple::le64: 8456 return new Le64TargetInfo(Triple, Opts); 8457 8458 case llvm::Triple::ppc: 8459 if (Triple.isOSDarwin()) 8460 return new DarwinPPC32TargetInfo(Triple, Opts); 8461 switch (os) { 8462 case llvm::Triple::Linux: 8463 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 8464 case llvm::Triple::FreeBSD: 8465 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8466 case llvm::Triple::NetBSD: 8467 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8468 case llvm::Triple::OpenBSD: 8469 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8470 case llvm::Triple::RTEMS: 8471 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 8472 default: 8473 return new PPC32TargetInfo(Triple, Opts); 8474 } 8475 8476 case llvm::Triple::ppc64: 8477 if (Triple.isOSDarwin()) 8478 return new DarwinPPC64TargetInfo(Triple, Opts); 8479 switch (os) { 8480 case llvm::Triple::Linux: 8481 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8482 case llvm::Triple::Lv2: 8483 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 8484 case llvm::Triple::FreeBSD: 8485 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8486 case llvm::Triple::NetBSD: 8487 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8488 default: 8489 return new PPC64TargetInfo(Triple, Opts); 8490 } 8491 8492 case llvm::Triple::ppc64le: 8493 switch (os) { 8494 case llvm::Triple::Linux: 8495 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8496 case llvm::Triple::NetBSD: 8497 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8498 default: 8499 return new PPC64TargetInfo(Triple, Opts); 8500 } 8501 8502 case llvm::Triple::nvptx: 8503 return new NVPTX32TargetInfo(Triple, Opts); 8504 case llvm::Triple::nvptx64: 8505 return new NVPTX64TargetInfo(Triple, Opts); 8506 8507 case llvm::Triple::amdgcn: 8508 case llvm::Triple::r600: 8509 return new AMDGPUTargetInfo(Triple, Opts); 8510 8511 case llvm::Triple::sparc: 8512 switch (os) { 8513 case llvm::Triple::Linux: 8514 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8515 case llvm::Triple::Solaris: 8516 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8517 case llvm::Triple::NetBSD: 8518 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8519 case llvm::Triple::OpenBSD: 8520 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8521 case llvm::Triple::RTEMS: 8522 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8523 default: 8524 return new SparcV8TargetInfo(Triple, Opts); 8525 } 8526 8527 // The 'sparcel' architecture copies all the above cases except for Solaris. 8528 case llvm::Triple::sparcel: 8529 switch (os) { 8530 case llvm::Triple::Linux: 8531 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8532 case llvm::Triple::NetBSD: 8533 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8534 case llvm::Triple::OpenBSD: 8535 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8536 case llvm::Triple::RTEMS: 8537 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8538 default: 8539 return new SparcV8elTargetInfo(Triple, Opts); 8540 } 8541 8542 case llvm::Triple::sparcv9: 8543 switch (os) { 8544 case llvm::Triple::Linux: 8545 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8546 case llvm::Triple::Solaris: 8547 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8548 case llvm::Triple::NetBSD: 8549 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8550 case llvm::Triple::OpenBSD: 8551 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8552 case llvm::Triple::FreeBSD: 8553 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8554 default: 8555 return new SparcV9TargetInfo(Triple, Opts); 8556 } 8557 8558 case llvm::Triple::systemz: 8559 switch (os) { 8560 case llvm::Triple::Linux: 8561 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 8562 default: 8563 return new SystemZTargetInfo(Triple, Opts); 8564 } 8565 8566 case llvm::Triple::tce: 8567 return new TCETargetInfo(Triple, Opts); 8568 8569 case llvm::Triple::x86: 8570 if (Triple.isOSDarwin()) 8571 return new DarwinI386TargetInfo(Triple, Opts); 8572 8573 switch (os) { 8574 case llvm::Triple::CloudABI: 8575 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 8576 case llvm::Triple::Linux: { 8577 switch (Triple.getEnvironment()) { 8578 default: 8579 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 8580 case llvm::Triple::Android: 8581 return new AndroidX86_32TargetInfo(Triple, Opts); 8582 } 8583 } 8584 case llvm::Triple::DragonFly: 8585 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8586 case llvm::Triple::NetBSD: 8587 return new NetBSDI386TargetInfo(Triple, Opts); 8588 case llvm::Triple::OpenBSD: 8589 return new OpenBSDI386TargetInfo(Triple, Opts); 8590 case llvm::Triple::Bitrig: 8591 return new BitrigI386TargetInfo(Triple, Opts); 8592 case llvm::Triple::FreeBSD: 8593 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8594 case llvm::Triple::KFreeBSD: 8595 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8596 case llvm::Triple::Minix: 8597 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 8598 case llvm::Triple::Solaris: 8599 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 8600 case llvm::Triple::Win32: { 8601 switch (Triple.getEnvironment()) { 8602 case llvm::Triple::Cygnus: 8603 return new CygwinX86_32TargetInfo(Triple, Opts); 8604 case llvm::Triple::GNU: 8605 return new MinGWX86_32TargetInfo(Triple, Opts); 8606 case llvm::Triple::Itanium: 8607 case llvm::Triple::MSVC: 8608 default: // Assume MSVC for unknown environments 8609 return new MicrosoftX86_32TargetInfo(Triple, Opts); 8610 } 8611 } 8612 case llvm::Triple::Haiku: 8613 return new HaikuX86_32TargetInfo(Triple, Opts); 8614 case llvm::Triple::RTEMS: 8615 return new RTEMSX86_32TargetInfo(Triple, Opts); 8616 case llvm::Triple::NaCl: 8617 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 8618 case llvm::Triple::ELFIAMCU: 8619 return new MCUX86_32TargetInfo(Triple, Opts); 8620 default: 8621 return new X86_32TargetInfo(Triple, Opts); 8622 } 8623 8624 case llvm::Triple::x86_64: 8625 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 8626 return new DarwinX86_64TargetInfo(Triple, Opts); 8627 8628 switch (os) { 8629 case llvm::Triple::CloudABI: 8630 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 8631 case llvm::Triple::Linux: { 8632 switch (Triple.getEnvironment()) { 8633 default: 8634 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 8635 case llvm::Triple::Android: 8636 return new AndroidX86_64TargetInfo(Triple, Opts); 8637 } 8638 } 8639 case llvm::Triple::DragonFly: 8640 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8641 case llvm::Triple::NetBSD: 8642 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8643 case llvm::Triple::OpenBSD: 8644 return new OpenBSDX86_64TargetInfo(Triple, Opts); 8645 case llvm::Triple::Bitrig: 8646 return new BitrigX86_64TargetInfo(Triple, Opts); 8647 case llvm::Triple::FreeBSD: 8648 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8649 case llvm::Triple::KFreeBSD: 8650 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8651 case llvm::Triple::Solaris: 8652 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 8653 case llvm::Triple::Win32: { 8654 switch (Triple.getEnvironment()) { 8655 case llvm::Triple::Cygnus: 8656 return new CygwinX86_64TargetInfo(Triple, Opts); 8657 case llvm::Triple::GNU: 8658 return new MinGWX86_64TargetInfo(Triple, Opts); 8659 case llvm::Triple::MSVC: 8660 default: // Assume MSVC for unknown environments 8661 return new MicrosoftX86_64TargetInfo(Triple, Opts); 8662 } 8663 } 8664 case llvm::Triple::Haiku: 8665 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 8666 case llvm::Triple::NaCl: 8667 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 8668 case llvm::Triple::Fuchsia: 8669 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts); 8670 case llvm::Triple::PS4: 8671 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 8672 default: 8673 return new X86_64TargetInfo(Triple, Opts); 8674 } 8675 8676 case llvm::Triple::spir: { 8677 if (Triple.getOS() != llvm::Triple::UnknownOS || 8678 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8679 return nullptr; 8680 return new SPIR32TargetInfo(Triple, Opts); 8681 } 8682 case llvm::Triple::spir64: { 8683 if (Triple.getOS() != llvm::Triple::UnknownOS || 8684 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8685 return nullptr; 8686 return new SPIR64TargetInfo(Triple, Opts); 8687 } 8688 case llvm::Triple::wasm32: 8689 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8690 return nullptr; 8691 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 8692 case llvm::Triple::wasm64: 8693 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8694 return nullptr; 8695 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 8696 8697 case llvm::Triple::renderscript32: 8698 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 8699 case llvm::Triple::renderscript64: 8700 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 8701 } 8702 } 8703 8704 /// CreateTargetInfo - Return the target info object for the specified target 8705 /// options. 8706 TargetInfo * 8707 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8708 const std::shared_ptr<TargetOptions> &Opts) { 8709 llvm::Triple Triple(Opts->Triple); 8710 8711 // Construct the target 8712 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 8713 if (!Target) { 8714 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8715 return nullptr; 8716 } 8717 Target->TargetOpts = Opts; 8718 8719 // Set the target CPU if specified. 8720 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8721 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8722 return nullptr; 8723 } 8724 8725 // Set the target ABI if specified. 8726 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8727 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8728 return nullptr; 8729 } 8730 8731 // Set the fp math unit. 8732 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8733 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8734 return nullptr; 8735 } 8736 8737 // Compute the default target features, we need the target to handle this 8738 // because features may have dependencies on one another. 8739 llvm::StringMap<bool> Features; 8740 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8741 Opts->FeaturesAsWritten)) 8742 return nullptr; 8743 8744 // Add the features to the compile options. 8745 Opts->Features.clear(); 8746 for (const auto &F : Features) 8747 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8748 8749 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8750 return nullptr; 8751 8752 Target->setSupportedOpenCLOpts(); 8753 8754 if (!Target->validateTarget(Diags)) 8755 return nullptr; 8756 8757 return Target.release(); 8758 } 8759