1 //===--- Targets.cpp - Implement -arch option and targets -----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements construction of a TargetInfo object from a
11 // target triple.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/OwningPtr.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/MC/MCSectionMachO.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include <algorithm>
32 using namespace clang;
33 
34 //===----------------------------------------------------------------------===//
35 //  Common code shared among targets.
36 //===----------------------------------------------------------------------===//
37 
38 /// DefineStd - Define a macro name and standard variants.  For example if
39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
40 /// when in GNU mode.
41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
42                       const LangOptions &Opts) {
43   assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
44 
45   // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
46   // in the user's namespace.
47   if (Opts.GNUMode)
48     Builder.defineMacro(MacroName);
49 
50   // Define __unix.
51   Builder.defineMacro("__" + MacroName);
52 
53   // Define __unix__.
54   Builder.defineMacro("__" + MacroName + "__");
55 }
56 
57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
58                             bool Tuning = true) {
59   Builder.defineMacro("__" + CPUName);
60   Builder.defineMacro("__" + CPUName + "__");
61   if (Tuning)
62     Builder.defineMacro("__tune_" + CPUName + "__");
63 }
64 
65 //===----------------------------------------------------------------------===//
66 // Defines specific to certain operating systems.
67 //===----------------------------------------------------------------------===//
68 
69 namespace {
70 template<typename TgtInfo>
71 class OSTargetInfo : public TgtInfo {
72 protected:
73   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
74                             MacroBuilder &Builder) const=0;
75 public:
76   OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
77   virtual void getTargetDefines(const LangOptions &Opts,
78                                 MacroBuilder &Builder) const {
79     TgtInfo::getTargetDefines(Opts, Builder);
80     getOSDefines(Opts, TgtInfo::getTriple(), Builder);
81   }
82 
83 };
84 } // end anonymous namespace
85 
86 
87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
88                              const llvm::Triple &Triple,
89                              StringRef &PlatformName,
90                              VersionTuple &PlatformMinVersion) {
91   Builder.defineMacro("__APPLE_CC__", "6000");
92   Builder.defineMacro("__APPLE__");
93   Builder.defineMacro("__MACH__");
94   Builder.defineMacro("OBJC_NEW_PROPERTIES");
95   // AddressSanitizer doesn't play well with source fortification, which is on
96   // by default on Darwin.
97   if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0");
98 
99   if (!Opts.ObjCAutoRefCount) {
100     // __weak is always defined, for use in blocks and with objc pointers.
101     Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
102 
103     // Darwin defines __strong even in C mode (just to nothing).
104     if (Opts.getGC() != LangOptions::NonGC)
105       Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
106     else
107       Builder.defineMacro("__strong", "");
108 
109     // __unsafe_unretained is defined to nothing in non-ARC mode. We even
110     // allow this in C, since one might have block pointers in structs that
111     // are used in pure C code and in Objective-C ARC.
112     Builder.defineMacro("__unsafe_unretained", "");
113   }
114 
115   if (Opts.Static)
116     Builder.defineMacro("__STATIC__");
117   else
118     Builder.defineMacro("__DYNAMIC__");
119 
120   if (Opts.POSIXThreads)
121     Builder.defineMacro("_REENTRANT");
122 
123   // Get the platform type and version number from the triple.
124   unsigned Maj, Min, Rev;
125   if (Triple.isMacOSX()) {
126     Triple.getMacOSXVersion(Maj, Min, Rev);
127     PlatformName = "macosx";
128   } else {
129     Triple.getOSVersion(Maj, Min, Rev);
130     PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
131   }
132 
133   // If -target arch-pc-win32-macho option specified, we're
134   // generating code for Win32 ABI. No need to emit
135   // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
136   if (PlatformName == "win32") {
137     PlatformMinVersion = VersionTuple(Maj, Min, Rev);
138     return;
139   }
140 
141   // Set the appropriate OS version define.
142   if (Triple.isiOS()) {
143     assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
144     char Str[6];
145     Str[0] = '0' + Maj;
146     Str[1] = '0' + (Min / 10);
147     Str[2] = '0' + (Min % 10);
148     Str[3] = '0' + (Rev / 10);
149     Str[4] = '0' + (Rev % 10);
150     Str[5] = '\0';
151     Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str);
152   } else if (Triple.getArchName() != "thumbv6m" &&
153              Triple.getArchName() != "thumbv7m" &&
154              Triple.getArchName() != "thumbv7em") {
155     // Note that the Driver allows versions which aren't representable in the
156     // define (because we only get a single digit for the minor and micro
157     // revision numbers). So, we limit them to the maximum representable
158     // version.
159     assert(Triple.getEnvironmentName().empty() && "Invalid environment!");
160     assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
161     char Str[5];
162     Str[0] = '0' + (Maj / 10);
163     Str[1] = '0' + (Maj % 10);
164     Str[2] = '0' + std::min(Min, 9U);
165     Str[3] = '0' + std::min(Rev, 9U);
166     Str[4] = '\0';
167     Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
168   }
169 
170   PlatformMinVersion = VersionTuple(Maj, Min, Rev);
171 }
172 
173 namespace {
174 template<typename Target>
175 class DarwinTargetInfo : public OSTargetInfo<Target> {
176 protected:
177   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
178                             MacroBuilder &Builder) const {
179     getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
180                      this->PlatformMinVersion);
181   }
182 
183 public:
184   DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
185     this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
186     this->MCountName = "\01mcount";
187   }
188 
189   virtual std::string isValidSectionSpecifier(StringRef SR) const {
190     // Let MCSectionMachO validate this.
191     StringRef Segment, Section;
192     unsigned TAA, StubSize;
193     bool HasTAA;
194     return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
195                                                        TAA, HasTAA, StubSize);
196   }
197 
198   virtual const char *getStaticInitSectionSpecifier() const {
199     // FIXME: We should return 0 when building kexts.
200     return "__TEXT,__StaticInit,regular,pure_instructions";
201   }
202 
203   /// Darwin does not support protected visibility.  Darwin's "default"
204   /// is very similar to ELF's "protected";  Darwin requires a "weak"
205   /// attribute on declarations that can be dynamically replaced.
206   virtual bool hasProtectedVisibility() const {
207     return false;
208   }
209 };
210 
211 
212 // DragonFlyBSD Target
213 template<typename Target>
214 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
215 protected:
216   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
217                             MacroBuilder &Builder) const {
218     // DragonFly defines; list based off of gcc output
219     Builder.defineMacro("__DragonFly__");
220     Builder.defineMacro("__DragonFly_cc_version", "100001");
221     Builder.defineMacro("__ELF__");
222     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
223     Builder.defineMacro("__tune_i386__");
224     DefineStd(Builder, "unix", Opts);
225   }
226 public:
227   DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
228       : OSTargetInfo<Target>(Triple) {
229     this->UserLabelPrefix = "";
230 
231     switch (Triple.getArch()) {
232     default:
233     case llvm::Triple::x86:
234     case llvm::Triple::x86_64:
235       this->MCountName = ".mcount";
236       break;
237     }
238   }
239 };
240 
241 // FreeBSD Target
242 template<typename Target>
243 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
244 protected:
245   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
246                             MacroBuilder &Builder) const {
247     // FreeBSD defines; list based off of gcc output
248 
249     unsigned Release = Triple.getOSMajorVersion();
250     if (Release == 0U)
251       Release = 8;
252 
253     Builder.defineMacro("__FreeBSD__", Twine(Release));
254     Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
255     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
256     DefineStd(Builder, "unix", Opts);
257     Builder.defineMacro("__ELF__");
258 
259     // On FreeBSD, wchar_t contains the number of the code point as
260     // used by the character set of the locale. These character sets are
261     // not necessarily a superset of ASCII.
262     Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
263   }
264 public:
265   FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
266     this->UserLabelPrefix = "";
267 
268     switch (Triple.getArch()) {
269     default:
270     case llvm::Triple::x86:
271     case llvm::Triple::x86_64:
272       this->MCountName = ".mcount";
273       break;
274     case llvm::Triple::mips:
275     case llvm::Triple::mipsel:
276     case llvm::Triple::ppc:
277     case llvm::Triple::ppc64:
278     case llvm::Triple::ppc64le:
279       this->MCountName = "_mcount";
280       break;
281     case llvm::Triple::arm:
282       this->MCountName = "__mcount";
283       break;
284     }
285   }
286 };
287 
288 // GNU/kFreeBSD Target
289 template<typename Target>
290 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
291 protected:
292   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
293                             MacroBuilder &Builder) const {
294     // GNU/kFreeBSD defines; list based off of gcc output
295 
296     DefineStd(Builder, "unix", Opts);
297     Builder.defineMacro("__FreeBSD_kernel__");
298     Builder.defineMacro("__GLIBC__");
299     Builder.defineMacro("__ELF__");
300     if (Opts.POSIXThreads)
301       Builder.defineMacro("_REENTRANT");
302     if (Opts.CPlusPlus)
303       Builder.defineMacro("_GNU_SOURCE");
304   }
305 public:
306   KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
307     this->UserLabelPrefix = "";
308   }
309 };
310 
311 // Minix Target
312 template<typename Target>
313 class MinixTargetInfo : public OSTargetInfo<Target> {
314 protected:
315   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
316                             MacroBuilder &Builder) const {
317     // Minix defines
318 
319     Builder.defineMacro("__minix", "3");
320     Builder.defineMacro("_EM_WSIZE", "4");
321     Builder.defineMacro("_EM_PSIZE", "4");
322     Builder.defineMacro("_EM_SSIZE", "2");
323     Builder.defineMacro("_EM_LSIZE", "4");
324     Builder.defineMacro("_EM_FSIZE", "4");
325     Builder.defineMacro("_EM_DSIZE", "8");
326     Builder.defineMacro("__ELF__");
327     DefineStd(Builder, "unix", Opts);
328   }
329 public:
330   MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
331     this->UserLabelPrefix = "";
332   }
333 };
334 
335 // Linux target
336 template<typename Target>
337 class LinuxTargetInfo : public OSTargetInfo<Target> {
338 protected:
339   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
340                             MacroBuilder &Builder) const {
341     // Linux defines; list based off of gcc output
342     DefineStd(Builder, "unix", Opts);
343     DefineStd(Builder, "linux", Opts);
344     Builder.defineMacro("__gnu_linux__");
345     Builder.defineMacro("__ELF__");
346     if (Triple.getEnvironment() == llvm::Triple::Android)
347       Builder.defineMacro("__ANDROID__", "1");
348     if (Opts.POSIXThreads)
349       Builder.defineMacro("_REENTRANT");
350     if (Opts.CPlusPlus)
351       Builder.defineMacro("_GNU_SOURCE");
352   }
353 public:
354   LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
355     this->UserLabelPrefix = "";
356     this->WIntType = TargetInfo::UnsignedInt;
357   }
358 
359   virtual const char *getStaticInitSectionSpecifier() const {
360     return ".text.startup";
361   }
362 };
363 
364 // NetBSD Target
365 template<typename Target>
366 class NetBSDTargetInfo : public OSTargetInfo<Target> {
367 protected:
368   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
369                             MacroBuilder &Builder) const {
370     // NetBSD defines; list based off of gcc output
371     Builder.defineMacro("__NetBSD__");
372     Builder.defineMacro("__unix__");
373     Builder.defineMacro("__ELF__");
374     if (Opts.POSIXThreads)
375       Builder.defineMacro("_POSIX_THREADS");
376   }
377 public:
378   NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
379     this->UserLabelPrefix = "";
380   }
381 };
382 
383 // OpenBSD Target
384 template<typename Target>
385 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
386 protected:
387   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
388                             MacroBuilder &Builder) const {
389     // OpenBSD defines; list based off of gcc output
390 
391     Builder.defineMacro("__OpenBSD__");
392     DefineStd(Builder, "unix", Opts);
393     Builder.defineMacro("__ELF__");
394     if (Opts.POSIXThreads)
395       Builder.defineMacro("_REENTRANT");
396   }
397 public:
398   OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
399     this->UserLabelPrefix = "";
400     this->TLSSupported = false;
401 
402       switch (Triple.getArch()) {
403         default:
404         case llvm::Triple::x86:
405         case llvm::Triple::x86_64:
406         case llvm::Triple::arm:
407         case llvm::Triple::sparc:
408           this->MCountName = "__mcount";
409           break;
410         case llvm::Triple::mips64:
411         case llvm::Triple::mips64el:
412         case llvm::Triple::ppc:
413         case llvm::Triple::sparcv9:
414           this->MCountName = "_mcount";
415           break;
416       }
417   }
418 };
419 
420 // Bitrig Target
421 template<typename Target>
422 class BitrigTargetInfo : public OSTargetInfo<Target> {
423 protected:
424   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
425                             MacroBuilder &Builder) const {
426     // Bitrig defines; list based off of gcc output
427 
428     Builder.defineMacro("__Bitrig__");
429     DefineStd(Builder, "unix", Opts);
430     Builder.defineMacro("__ELF__");
431     if (Opts.POSIXThreads)
432       Builder.defineMacro("_REENTRANT");
433   }
434 public:
435   BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
436     this->UserLabelPrefix = "";
437     this->TLSSupported = false;
438     this->MCountName = "__mcount";
439   }
440 };
441 
442 // PSP Target
443 template<typename Target>
444 class PSPTargetInfo : public OSTargetInfo<Target> {
445 protected:
446   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
447                             MacroBuilder &Builder) const {
448     // PSP defines; list based on the output of the pspdev gcc toolchain.
449     Builder.defineMacro("PSP");
450     Builder.defineMacro("_PSP");
451     Builder.defineMacro("__psp__");
452     Builder.defineMacro("__ELF__");
453   }
454 public:
455   PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
456     this->UserLabelPrefix = "";
457   }
458 };
459 
460 // PS3 PPU Target
461 template<typename Target>
462 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
463 protected:
464   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
465                             MacroBuilder &Builder) const {
466     // PS3 PPU defines.
467     Builder.defineMacro("__PPC__");
468     Builder.defineMacro("__PPU__");
469     Builder.defineMacro("__CELLOS_LV2__");
470     Builder.defineMacro("__ELF__");
471     Builder.defineMacro("__LP32__");
472     Builder.defineMacro("_ARCH_PPC64");
473     Builder.defineMacro("__powerpc64__");
474   }
475 public:
476   PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
477     this->UserLabelPrefix = "";
478     this->LongWidth = this->LongAlign = 32;
479     this->PointerWidth = this->PointerAlign = 32;
480     this->IntMaxType = TargetInfo::SignedLongLong;
481     this->UIntMaxType = TargetInfo::UnsignedLongLong;
482     this->Int64Type = TargetInfo::SignedLongLong;
483     this->SizeType = TargetInfo::UnsignedInt;
484     this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
485                               "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
486   }
487 };
488 
489 // FIXME: Need a real SPU target.
490 // PS3 SPU Target
491 template<typename Target>
492 class PS3SPUTargetInfo : public OSTargetInfo<Target> {
493 protected:
494   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
495                             MacroBuilder &Builder) const {
496     // PS3 PPU defines.
497     Builder.defineMacro("__SPU__");
498     Builder.defineMacro("__ELF__");
499   }
500 public:
501   PS3SPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
502     this->UserLabelPrefix = "";
503   }
504 };
505 
506 // AuroraUX target
507 template<typename Target>
508 class AuroraUXTargetInfo : public OSTargetInfo<Target> {
509 protected:
510   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
511                             MacroBuilder &Builder) const {
512     DefineStd(Builder, "sun", Opts);
513     DefineStd(Builder, "unix", Opts);
514     Builder.defineMacro("__ELF__");
515     Builder.defineMacro("__svr4__");
516     Builder.defineMacro("__SVR4");
517   }
518 public:
519   AuroraUXTargetInfo(const llvm::Triple &Triple)
520       : OSTargetInfo<Target>(Triple) {
521     this->UserLabelPrefix = "";
522     this->WCharType = this->SignedLong;
523     // FIXME: WIntType should be SignedLong
524   }
525 };
526 
527 // Solaris target
528 template<typename Target>
529 class SolarisTargetInfo : public OSTargetInfo<Target> {
530 protected:
531   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
532                             MacroBuilder &Builder) const {
533     DefineStd(Builder, "sun", Opts);
534     DefineStd(Builder, "unix", Opts);
535     Builder.defineMacro("__ELF__");
536     Builder.defineMacro("__svr4__");
537     Builder.defineMacro("__SVR4");
538     // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
539     // newer, but to 500 for everything else.  feature_test.h has a check to
540     // ensure that you are not using C99 with an old version of X/Open or C89
541     // with a new version.
542     if (Opts.C99 || Opts.C11)
543       Builder.defineMacro("_XOPEN_SOURCE", "600");
544     else
545       Builder.defineMacro("_XOPEN_SOURCE", "500");
546     if (Opts.CPlusPlus)
547       Builder.defineMacro("__C99FEATURES__");
548     Builder.defineMacro("_LARGEFILE_SOURCE");
549     Builder.defineMacro("_LARGEFILE64_SOURCE");
550     Builder.defineMacro("__EXTENSIONS__");
551     Builder.defineMacro("_REENTRANT");
552   }
553 public:
554   SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
555     this->UserLabelPrefix = "";
556     this->WCharType = this->SignedInt;
557     // FIXME: WIntType should be SignedLong
558   }
559 };
560 
561 // Windows target
562 template<typename Target>
563 class WindowsTargetInfo : public OSTargetInfo<Target> {
564 protected:
565   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
566                             MacroBuilder &Builder) const {
567     Builder.defineMacro("_WIN32");
568   }
569   void getVisualStudioDefines(const LangOptions &Opts,
570                               MacroBuilder &Builder) const {
571     if (Opts.CPlusPlus) {
572       if (Opts.RTTI)
573         Builder.defineMacro("_CPPRTTI");
574 
575       if (Opts.Exceptions)
576         Builder.defineMacro("_CPPUNWIND");
577     }
578 
579     if (!Opts.CharIsSigned)
580       Builder.defineMacro("_CHAR_UNSIGNED");
581 
582     // FIXME: POSIXThreads isn't exactly the option this should be defined for,
583     //        but it works for now.
584     if (Opts.POSIXThreads)
585       Builder.defineMacro("_MT");
586 
587     if (Opts.MSCVersion != 0)
588       Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion));
589 
590     if (Opts.MicrosoftExt) {
591       Builder.defineMacro("_MSC_EXTENSIONS");
592 
593       if (Opts.CPlusPlus11) {
594         Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
595         Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
596         Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
597       }
598     }
599 
600     Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
601   }
602 
603 public:
604   WindowsTargetInfo(const llvm::Triple &Triple)
605       : OSTargetInfo<Target>(Triple) {}
606 };
607 
608 template <typename Target>
609 class NaClTargetInfo : public OSTargetInfo<Target> {
610 protected:
611   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
612                             MacroBuilder &Builder) const {
613     if (Opts.POSIXThreads)
614       Builder.defineMacro("_REENTRANT");
615     if (Opts.CPlusPlus)
616       Builder.defineMacro("_GNU_SOURCE");
617 
618     DefineStd(Builder, "unix", Opts);
619     Builder.defineMacro("__ELF__");
620     Builder.defineMacro("__native_client__");
621   }
622 
623 public:
624   NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
625     this->UserLabelPrefix = "";
626     this->LongAlign = 32;
627     this->LongWidth = 32;
628     this->PointerAlign = 32;
629     this->PointerWidth = 32;
630     this->IntMaxType = TargetInfo::SignedLongLong;
631     this->UIntMaxType = TargetInfo::UnsignedLongLong;
632     this->Int64Type = TargetInfo::SignedLongLong;
633     this->DoubleAlign = 64;
634     this->LongDoubleWidth = 64;
635     this->LongDoubleAlign = 64;
636     this->SizeType = TargetInfo::UnsignedInt;
637     this->PtrDiffType = TargetInfo::SignedInt;
638     this->IntPtrType = TargetInfo::SignedInt;
639     // RegParmMax is inherited from the underlying architecture
640     this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
641     this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
642                               "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
643   }
644   virtual typename Target::CallingConvCheckResult checkCallingConvention(
645       CallingConv CC) const {
646     return CC == CC_PnaclCall ? Target::CCCR_OK :
647         Target::checkCallingConvention(CC);
648   }
649 };
650 } // end anonymous namespace.
651 
652 //===----------------------------------------------------------------------===//
653 // Specific target implementations.
654 //===----------------------------------------------------------------------===//
655 
656 namespace {
657 // PPC abstract base class
658 class PPCTargetInfo : public TargetInfo {
659   static const Builtin::Info BuiltinInfo[];
660   static const char * const GCCRegNames[];
661   static const TargetInfo::GCCRegAlias GCCRegAliases[];
662   std::string CPU;
663 
664   // Target cpu features.
665   bool HasVSX;
666 
667 public:
668   PPCTargetInfo(const llvm::Triple &Triple)
669       : TargetInfo(Triple), HasVSX(false) {
670     BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
671     LongDoubleWidth = LongDoubleAlign = 128;
672     LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
673   }
674 
675   /// \brief Flags for architecture specific defines.
676   typedef enum {
677     ArchDefineNone  = 0,
678     ArchDefineName  = 1 << 0, // <name> is substituted for arch name.
679     ArchDefinePpcgr = 1 << 1,
680     ArchDefinePpcsq = 1 << 2,
681     ArchDefine440   = 1 << 3,
682     ArchDefine603   = 1 << 4,
683     ArchDefine604   = 1 << 5,
684     ArchDefinePwr4  = 1 << 6,
685     ArchDefinePwr5  = 1 << 7,
686     ArchDefinePwr5x = 1 << 8,
687     ArchDefinePwr6  = 1 << 9,
688     ArchDefinePwr6x = 1 << 10,
689     ArchDefinePwr7  = 1 << 11,
690     ArchDefineA2    = 1 << 12,
691     ArchDefineA2q   = 1 << 13
692   } ArchDefineTypes;
693 
694   // Note: GCC recognizes the following additional cpus:
695   //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
696   //  821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
697   //  titan, rs64.
698   virtual bool setCPU(const std::string &Name) {
699     bool CPUKnown = llvm::StringSwitch<bool>(Name)
700       .Case("generic", true)
701       .Case("440", true)
702       .Case("450", true)
703       .Case("601", true)
704       .Case("602", true)
705       .Case("603", true)
706       .Case("603e", true)
707       .Case("603ev", true)
708       .Case("604", true)
709       .Case("604e", true)
710       .Case("620", true)
711       .Case("630", true)
712       .Case("g3", true)
713       .Case("7400", true)
714       .Case("g4", true)
715       .Case("7450", true)
716       .Case("g4+", true)
717       .Case("750", true)
718       .Case("970", true)
719       .Case("g5", true)
720       .Case("a2", true)
721       .Case("a2q", true)
722       .Case("e500mc", true)
723       .Case("e5500", true)
724       .Case("power3", true)
725       .Case("pwr3", true)
726       .Case("power4", true)
727       .Case("pwr4", true)
728       .Case("power5", true)
729       .Case("pwr5", true)
730       .Case("power5x", true)
731       .Case("pwr5x", true)
732       .Case("power6", true)
733       .Case("pwr6", true)
734       .Case("power6x", true)
735       .Case("pwr6x", true)
736       .Case("power7", true)
737       .Case("pwr7", true)
738       .Case("powerpc", true)
739       .Case("ppc", true)
740       .Case("powerpc64", true)
741       .Case("ppc64", true)
742       .Case("powerpc64le", true)
743       .Case("ppc64le", true)
744       .Default(false);
745 
746     if (CPUKnown)
747       CPU = Name;
748 
749     return CPUKnown;
750   }
751 
752   virtual void getTargetBuiltins(const Builtin::Info *&Records,
753                                  unsigned &NumRecords) const {
754     Records = BuiltinInfo;
755     NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
756   }
757 
758   virtual bool isCLZForZeroUndef() const { return false; }
759 
760   virtual void getTargetDefines(const LangOptions &Opts,
761                                 MacroBuilder &Builder) const;
762 
763   virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
764 
765   virtual bool handleTargetFeatures(std::vector<std::string> &Features,
766                                     DiagnosticsEngine &Diags);
767   virtual bool hasFeature(StringRef Feature) const;
768 
769   virtual void getGCCRegNames(const char * const *&Names,
770                               unsigned &NumNames) const;
771   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
772                                 unsigned &NumAliases) const;
773   virtual bool validateAsmConstraint(const char *&Name,
774                                      TargetInfo::ConstraintInfo &Info) const {
775     switch (*Name) {
776     default: return false;
777     case 'O': // Zero
778       break;
779     case 'b': // Base register
780     case 'f': // Floating point register
781       Info.setAllowsRegister();
782       break;
783     // FIXME: The following are added to allow parsing.
784     // I just took a guess at what the actions should be.
785     // Also, is more specific checking needed?  I.e. specific registers?
786     case 'd': // Floating point register (containing 64-bit value)
787     case 'v': // Altivec vector register
788       Info.setAllowsRegister();
789       break;
790     case 'w':
791       switch (Name[1]) {
792         case 'd':// VSX vector register to hold vector double data
793         case 'f':// VSX vector register to hold vector float data
794         case 's':// VSX vector register to hold scalar float data
795         case 'a':// Any VSX register
796           break;
797         default:
798           return false;
799       }
800       Info.setAllowsRegister();
801       Name++; // Skip over 'w'.
802       break;
803     case 'h': // `MQ', `CTR', or `LINK' register
804     case 'q': // `MQ' register
805     case 'c': // `CTR' register
806     case 'l': // `LINK' register
807     case 'x': // `CR' register (condition register) number 0
808     case 'y': // `CR' register (condition register)
809     case 'z': // `XER[CA]' carry bit (part of the XER register)
810       Info.setAllowsRegister();
811       break;
812     case 'I': // Signed 16-bit constant
813     case 'J': // Unsigned 16-bit constant shifted left 16 bits
814               //  (use `L' instead for SImode constants)
815     case 'K': // Unsigned 16-bit constant
816     case 'L': // Signed 16-bit constant shifted left 16 bits
817     case 'M': // Constant larger than 31
818     case 'N': // Exact power of 2
819     case 'P': // Constant whose negation is a signed 16-bit constant
820     case 'G': // Floating point constant that can be loaded into a
821               // register with one instruction per word
822     case 'H': // Integer/Floating point constant that can be loaded
823               // into a register using three instructions
824       break;
825     case 'm': // Memory operand. Note that on PowerPC targets, m can
826               // include addresses that update the base register. It
827               // is therefore only safe to use `m' in an asm statement
828               // if that asm statement accesses the operand exactly once.
829               // The asm statement must also use `%U<opno>' as a
830               // placeholder for the "update" flag in the corresponding
831               // load or store instruction. For example:
832               // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
833               // is correct but:
834               // asm ("st %1,%0" : "=m" (mem) : "r" (val));
835               // is not. Use es rather than m if you don't want the base
836               // register to be updated.
837     case 'e':
838       if (Name[1] != 's')
839           return false;
840               // es: A "stable" memory operand; that is, one which does not
841               // include any automodification of the base register. Unlike
842               // `m', this constraint can be used in asm statements that
843               // might access the operand several times, or that might not
844               // access it at all.
845       Info.setAllowsMemory();
846       Name++; // Skip over 'e'.
847       break;
848     case 'Q': // Memory operand that is an offset from a register (it is
849               // usually better to use `m' or `es' in asm statements)
850     case 'Z': // Memory operand that is an indexed or indirect from a
851               // register (it is usually better to use `m' or `es' in
852               // asm statements)
853       Info.setAllowsMemory();
854       Info.setAllowsRegister();
855       break;
856     case 'R': // AIX TOC entry
857     case 'a': // Address operand that is an indexed or indirect from a
858               // register (`p' is preferable for asm statements)
859     case 'S': // Constant suitable as a 64-bit mask operand
860     case 'T': // Constant suitable as a 32-bit mask operand
861     case 'U': // System V Release 4 small data area reference
862     case 't': // AND masks that can be performed by two rldic{l, r}
863               // instructions
864     case 'W': // Vector constant that does not require memory
865     case 'j': // Vector constant that is all zeros.
866       break;
867     // End FIXME.
868     }
869     return true;
870   }
871   virtual const char *getClobbers() const {
872     return "";
873   }
874   int getEHDataRegisterNumber(unsigned RegNo) const {
875     if (RegNo == 0) return 3;
876     if (RegNo == 1) return 4;
877     return -1;
878   }
879 };
880 
881 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
882 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
883 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
884                                               ALL_LANGUAGES },
885 #include "clang/Basic/BuiltinsPPC.def"
886 };
887 
888   /// handleTargetFeatures - Perform initialization based on the user
889 /// configured set of features.
890 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
891                                          DiagnosticsEngine &Diags) {
892   // Remember the maximum enabled sselevel.
893   for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
894     // Ignore disabled features.
895     if (Features[i][0] == '-')
896       continue;
897 
898     StringRef Feature = StringRef(Features[i]).substr(1);
899 
900     if (Feature == "vsx") {
901       HasVSX = true;
902       continue;
903     }
904 
905     // TODO: Finish this list and add an assert that we've handled them
906     // all.
907   }
908 
909   return true;
910 }
911 
912 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
913 /// #defines that are not tied to a specific subtarget.
914 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
915                                      MacroBuilder &Builder) const {
916   // Target identification.
917   Builder.defineMacro("__ppc__");
918   Builder.defineMacro("__PPC__");
919   Builder.defineMacro("_ARCH_PPC");
920   Builder.defineMacro("__powerpc__");
921   Builder.defineMacro("__POWERPC__");
922   if (PointerWidth == 64) {
923     Builder.defineMacro("_ARCH_PPC64");
924     Builder.defineMacro("__powerpc64__");
925     Builder.defineMacro("__ppc64__");
926     Builder.defineMacro("__PPC64__");
927   }
928 
929   // Target properties.
930   if (getTriple().getArch() == llvm::Triple::ppc64le) {
931     Builder.defineMacro("_LITTLE_ENDIAN");
932     Builder.defineMacro("__LITTLE_ENDIAN__");
933   } else {
934     if (getTriple().getOS() != llvm::Triple::NetBSD &&
935         getTriple().getOS() != llvm::Triple::OpenBSD)
936       Builder.defineMacro("_BIG_ENDIAN");
937     Builder.defineMacro("__BIG_ENDIAN__");
938   }
939 
940   // Subtarget options.
941   Builder.defineMacro("__NATURAL_ALIGNMENT__");
942   Builder.defineMacro("__REGISTER_PREFIX__", "");
943 
944   // FIXME: Should be controlled by command line option.
945   if (LongDoubleWidth == 128)
946     Builder.defineMacro("__LONG_DOUBLE_128__");
947 
948   if (Opts.AltiVec) {
949     Builder.defineMacro("__VEC__", "10206");
950     Builder.defineMacro("__ALTIVEC__");
951   }
952 
953   // CPU identification.
954   ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
955     .Case("440",   ArchDefineName)
956     .Case("450",   ArchDefineName | ArchDefine440)
957     .Case("601",   ArchDefineName)
958     .Case("602",   ArchDefineName | ArchDefinePpcgr)
959     .Case("603",   ArchDefineName | ArchDefinePpcgr)
960     .Case("603e",  ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
961     .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
962     .Case("604",   ArchDefineName | ArchDefinePpcgr)
963     .Case("604e",  ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
964     .Case("620",   ArchDefineName | ArchDefinePpcgr)
965     .Case("630",   ArchDefineName | ArchDefinePpcgr)
966     .Case("7400",  ArchDefineName | ArchDefinePpcgr)
967     .Case("7450",  ArchDefineName | ArchDefinePpcgr)
968     .Case("750",   ArchDefineName | ArchDefinePpcgr)
969     .Case("970",   ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
970                      | ArchDefinePpcsq)
971     .Case("a2",    ArchDefineA2)
972     .Case("a2q",   ArchDefineName | ArchDefineA2 | ArchDefineA2q)
973     .Case("pwr3",  ArchDefinePpcgr)
974     .Case("pwr4",  ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
975     .Case("pwr5",  ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
976                      | ArchDefinePpcsq)
977     .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
978                      | ArchDefinePpcgr | ArchDefinePpcsq)
979     .Case("pwr6",  ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
980                      | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
981     .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
982                      | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
983                      | ArchDefinePpcsq)
984     .Case("pwr7",  ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
985                      | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
986                      | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
987     .Case("power3",  ArchDefinePpcgr)
988     .Case("power4",  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
989     .Case("power5",  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
990                        | ArchDefinePpcsq)
991     .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
992                        | ArchDefinePpcgr | ArchDefinePpcsq)
993     .Case("power6",  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
994                        | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
995     .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
996                        | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
997                        | ArchDefinePpcsq)
998     .Case("power7",  ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
999                        | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1000                        | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq)
1001     .Default(ArchDefineNone);
1002 
1003   if (defs & ArchDefineName)
1004     Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1005   if (defs & ArchDefinePpcgr)
1006     Builder.defineMacro("_ARCH_PPCGR");
1007   if (defs & ArchDefinePpcsq)
1008     Builder.defineMacro("_ARCH_PPCSQ");
1009   if (defs & ArchDefine440)
1010     Builder.defineMacro("_ARCH_440");
1011   if (defs & ArchDefine603)
1012     Builder.defineMacro("_ARCH_603");
1013   if (defs & ArchDefine604)
1014     Builder.defineMacro("_ARCH_604");
1015   if (defs & ArchDefinePwr4)
1016     Builder.defineMacro("_ARCH_PWR4");
1017   if (defs & ArchDefinePwr5)
1018     Builder.defineMacro("_ARCH_PWR5");
1019   if (defs & ArchDefinePwr5x)
1020     Builder.defineMacro("_ARCH_PWR5X");
1021   if (defs & ArchDefinePwr6)
1022     Builder.defineMacro("_ARCH_PWR6");
1023   if (defs & ArchDefinePwr6x)
1024     Builder.defineMacro("_ARCH_PWR6X");
1025   if (defs & ArchDefinePwr7)
1026     Builder.defineMacro("_ARCH_PWR7");
1027   if (defs & ArchDefineA2)
1028     Builder.defineMacro("_ARCH_A2");
1029   if (defs & ArchDefineA2q) {
1030     Builder.defineMacro("_ARCH_A2Q");
1031     Builder.defineMacro("_ARCH_QP");
1032   }
1033 
1034   if (getTriple().getVendor() == llvm::Triple::BGQ) {
1035     Builder.defineMacro("__bg__");
1036     Builder.defineMacro("__THW_BLUEGENE__");
1037     Builder.defineMacro("__bgq__");
1038     Builder.defineMacro("__TOS_BGQ__");
1039   }
1040 
1041   if (HasVSX)
1042     Builder.defineMacro("__VSX__");
1043 
1044   // FIXME: The following are not yet generated here by Clang, but are
1045   //        generated by GCC:
1046   //
1047   //   _SOFT_FLOAT_
1048   //   __RECIP_PRECISION__
1049   //   __APPLE_ALTIVEC__
1050   //   __RECIP__
1051   //   __RECIPF__
1052   //   __RSQRTE__
1053   //   __RSQRTEF__
1054   //   _SOFT_DOUBLE_
1055   //   __NO_LWSYNC__
1056   //   __HAVE_BSWAP__
1057   //   __LONGDOUBLE128
1058   //   __CMODEL_MEDIUM__
1059   //   __CMODEL_LARGE__
1060   //   _CALL_SYSV
1061   //   _CALL_DARWIN
1062   //   __NO_FPRS__
1063 }
1064 
1065 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1066   Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1067     .Case("7400", true)
1068     .Case("g4", true)
1069     .Case("7450", true)
1070     .Case("g4+", true)
1071     .Case("970", true)
1072     .Case("g5", true)
1073     .Case("pwr6", true)
1074     .Case("pwr7", true)
1075     .Case("ppc64", true)
1076     .Case("ppc64le", true)
1077     .Default(false);
1078 
1079   Features["qpx"] = (CPU == "a2q");
1080 }
1081 
1082 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1083   return Feature == "powerpc";
1084 }
1085 
1086 
1087 const char * const PPCTargetInfo::GCCRegNames[] = {
1088   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1089   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1090   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1091   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1092   "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1093   "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1094   "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1095   "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1096   "mq", "lr", "ctr", "ap",
1097   "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1098   "xer",
1099   "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1100   "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1101   "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1102   "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1103   "vrsave", "vscr",
1104   "spe_acc", "spefscr",
1105   "sfp"
1106 };
1107 
1108 void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1109                                    unsigned &NumNames) const {
1110   Names = GCCRegNames;
1111   NumNames = llvm::array_lengthof(GCCRegNames);
1112 }
1113 
1114 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1115   // While some of these aliases do map to different registers
1116   // they still share the same register name.
1117   { { "0" }, "r0" },
1118   { { "1"}, "r1" },
1119   { { "2" }, "r2" },
1120   { { "3" }, "r3" },
1121   { { "4" }, "r4" },
1122   { { "5" }, "r5" },
1123   { { "6" }, "r6" },
1124   { { "7" }, "r7" },
1125   { { "8" }, "r8" },
1126   { { "9" }, "r9" },
1127   { { "10" }, "r10" },
1128   { { "11" }, "r11" },
1129   { { "12" }, "r12" },
1130   { { "13" }, "r13" },
1131   { { "14" }, "r14" },
1132   { { "15" }, "r15" },
1133   { { "16" }, "r16" },
1134   { { "17" }, "r17" },
1135   { { "18" }, "r18" },
1136   { { "19" }, "r19" },
1137   { { "20" }, "r20" },
1138   { { "21" }, "r21" },
1139   { { "22" }, "r22" },
1140   { { "23" }, "r23" },
1141   { { "24" }, "r24" },
1142   { { "25" }, "r25" },
1143   { { "26" }, "r26" },
1144   { { "27" }, "r27" },
1145   { { "28" }, "r28" },
1146   { { "29" }, "r29" },
1147   { { "30" }, "r30" },
1148   { { "31" }, "r31" },
1149   { { "fr0" }, "f0" },
1150   { { "fr1" }, "f1" },
1151   { { "fr2" }, "f2" },
1152   { { "fr3" }, "f3" },
1153   { { "fr4" }, "f4" },
1154   { { "fr5" }, "f5" },
1155   { { "fr6" }, "f6" },
1156   { { "fr7" }, "f7" },
1157   { { "fr8" }, "f8" },
1158   { { "fr9" }, "f9" },
1159   { { "fr10" }, "f10" },
1160   { { "fr11" }, "f11" },
1161   { { "fr12" }, "f12" },
1162   { { "fr13" }, "f13" },
1163   { { "fr14" }, "f14" },
1164   { { "fr15" }, "f15" },
1165   { { "fr16" }, "f16" },
1166   { { "fr17" }, "f17" },
1167   { { "fr18" }, "f18" },
1168   { { "fr19" }, "f19" },
1169   { { "fr20" }, "f20" },
1170   { { "fr21" }, "f21" },
1171   { { "fr22" }, "f22" },
1172   { { "fr23" }, "f23" },
1173   { { "fr24" }, "f24" },
1174   { { "fr25" }, "f25" },
1175   { { "fr26" }, "f26" },
1176   { { "fr27" }, "f27" },
1177   { { "fr28" }, "f28" },
1178   { { "fr29" }, "f29" },
1179   { { "fr30" }, "f30" },
1180   { { "fr31" }, "f31" },
1181   { { "cc" }, "cr0" },
1182 };
1183 
1184 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1185                                      unsigned &NumAliases) const {
1186   Aliases = GCCRegAliases;
1187   NumAliases = llvm::array_lengthof(GCCRegAliases);
1188 }
1189 } // end anonymous namespace.
1190 
1191 namespace {
1192 class PPC32TargetInfo : public PPCTargetInfo {
1193 public:
1194   PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1195     DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1196                         "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32";
1197 
1198     switch (getTriple().getOS()) {
1199     case llvm::Triple::Linux:
1200     case llvm::Triple::FreeBSD:
1201     case llvm::Triple::NetBSD:
1202       SizeType = UnsignedInt;
1203       PtrDiffType = SignedInt;
1204       IntPtrType = SignedInt;
1205       break;
1206     default:
1207       break;
1208     }
1209 
1210     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1211       LongDoubleWidth = LongDoubleAlign = 64;
1212       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1213     }
1214 
1215     // PPC32 supports atomics up to 4 bytes.
1216     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1217   }
1218 
1219   virtual BuiltinVaListKind getBuiltinVaListKind() const {
1220     // This is the ELF definition, and is overridden by the Darwin sub-target
1221     return TargetInfo::PowerABIBuiltinVaList;
1222   }
1223 };
1224 } // end anonymous namespace.
1225 
1226 // Note: ABI differences may eventually require us to have a separate
1227 // TargetInfo for little endian.
1228 namespace {
1229 class PPC64TargetInfo : public PPCTargetInfo {
1230 public:
1231   PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1232     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1233     IntMaxType = SignedLong;
1234     UIntMaxType = UnsignedLong;
1235     Int64Type = SignedLong;
1236 
1237     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1238       LongDoubleWidth = LongDoubleAlign = 64;
1239       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1240       DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1241                           "i64:64:64-f32:32:32-f64:64:64-"
1242                           "v128:128:128-n32:64";
1243     } else
1244       DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1245                           "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
1246                           "v128:128:128-n32:64";
1247 
1248     // PPC64 supports atomics up to 8 bytes.
1249     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1250   }
1251   virtual BuiltinVaListKind getBuiltinVaListKind() const {
1252     return TargetInfo::CharPtrBuiltinVaList;
1253   }
1254 };
1255 } // end anonymous namespace.
1256 
1257 
1258 namespace {
1259 class DarwinPPC32TargetInfo :
1260   public DarwinTargetInfo<PPC32TargetInfo> {
1261 public:
1262   DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1263       : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1264     HasAlignMac68kSupport = true;
1265     BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1266     PtrDiffType = SignedInt;    // for http://llvm.org/bugs/show_bug.cgi?id=15726
1267     LongLongAlign = 32;
1268     SuitableAlign = 128;
1269     DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1270                         "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32";
1271   }
1272   virtual BuiltinVaListKind getBuiltinVaListKind() const {
1273     return TargetInfo::CharPtrBuiltinVaList;
1274   }
1275 };
1276 
1277 class DarwinPPC64TargetInfo :
1278   public DarwinTargetInfo<PPC64TargetInfo> {
1279 public:
1280   DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1281       : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1282     HasAlignMac68kSupport = true;
1283     SuitableAlign = 128;
1284     DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
1285                         "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64";
1286   }
1287 };
1288 } // end anonymous namespace.
1289 
1290 namespace {
1291   static const unsigned NVPTXAddrSpaceMap[] = {
1292     1,    // opencl_global
1293     3,    // opencl_local
1294     4,    // opencl_constant
1295     1,    // cuda_device
1296     4,    // cuda_constant
1297     3,    // cuda_shared
1298   };
1299   class NVPTXTargetInfo : public TargetInfo {
1300     static const char * const GCCRegNames[];
1301     static const Builtin::Info BuiltinInfo[];
1302   public:
1303     NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1304       BigEndian = false;
1305       TLSSupported = false;
1306       LongWidth = LongAlign = 64;
1307       AddrSpaceMap = &NVPTXAddrSpaceMap;
1308       UseAddrSpaceMapMangling = true;
1309       // Define available target features
1310       // These must be defined in sorted order!
1311       NoAsmVariants = true;
1312     }
1313     virtual void getTargetDefines(const LangOptions &Opts,
1314                                   MacroBuilder &Builder) const {
1315       Builder.defineMacro("__PTX__");
1316       Builder.defineMacro("__NVPTX__");
1317     }
1318     virtual void getTargetBuiltins(const Builtin::Info *&Records,
1319                                    unsigned &NumRecords) const {
1320       Records = BuiltinInfo;
1321       NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1322     }
1323     virtual bool hasFeature(StringRef Feature) const {
1324       return Feature == "ptx" || Feature == "nvptx";
1325     }
1326 
1327     virtual void getGCCRegNames(const char * const *&Names,
1328                                 unsigned &NumNames) const;
1329     virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1330                                   unsigned &NumAliases) const {
1331       // No aliases.
1332       Aliases = 0;
1333       NumAliases = 0;
1334     }
1335     virtual bool validateAsmConstraint(const char *&Name,
1336                                        TargetInfo::ConstraintInfo &Info) const {
1337       switch (*Name) {
1338       default: return false;
1339       case 'c':
1340       case 'h':
1341       case 'r':
1342       case 'l':
1343       case 'f':
1344       case 'd':
1345         Info.setAllowsRegister();
1346         return true;
1347       }
1348     }
1349     virtual const char *getClobbers() const {
1350       // FIXME: Is this really right?
1351       return "";
1352     }
1353     virtual BuiltinVaListKind getBuiltinVaListKind() const {
1354       // FIXME: implement
1355       return TargetInfo::CharPtrBuiltinVaList;
1356     }
1357     virtual bool setCPU(const std::string &Name) {
1358       bool Valid = llvm::StringSwitch<bool>(Name)
1359         .Case("sm_20", true)
1360         .Case("sm_21", true)
1361         .Case("sm_30", true)
1362         .Case("sm_35", true)
1363         .Default(false);
1364 
1365       return Valid;
1366     }
1367   };
1368 
1369   const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1370 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1371 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1372                                               ALL_LANGUAGES },
1373 #include "clang/Basic/BuiltinsNVPTX.def"
1374   };
1375 
1376   const char * const NVPTXTargetInfo::GCCRegNames[] = {
1377     "r0"
1378   };
1379 
1380   void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1381                                      unsigned &NumNames) const {
1382     Names = GCCRegNames;
1383     NumNames = llvm::array_lengthof(GCCRegNames);
1384   }
1385 
1386   class NVPTX32TargetInfo : public NVPTXTargetInfo {
1387   public:
1388     NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1389       PointerWidth = PointerAlign = 32;
1390       SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt;
1391       DescriptionString
1392         = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1393           "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1394           "n16:32:64";
1395   }
1396   };
1397 
1398   class NVPTX64TargetInfo : public NVPTXTargetInfo {
1399   public:
1400     NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1401       PointerWidth = PointerAlign = 64;
1402       SizeType     = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong;
1403       DescriptionString
1404         = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
1405           "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-"
1406           "n16:32:64";
1407   }
1408   };
1409 }
1410 
1411 namespace {
1412 
1413 static const unsigned R600AddrSpaceMap[] = {
1414   1,    // opencl_global
1415   3,    // opencl_local
1416   2,    // opencl_constant
1417   1,    // cuda_device
1418   2,    // cuda_constant
1419   3     // cuda_shared
1420 };
1421 
1422 static const char *DescriptionStringR600 =
1423   "e"
1424   "-p:32:32:32"
1425   "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32"
1426   "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1427   "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1428   "-n32:64";
1429 
1430 static const char *DescriptionStringR600DoubleOps =
1431   "e"
1432   "-p:32:32:32"
1433   "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1434   "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1435   "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1436   "-n32:64";
1437 
1438 static const char *DescriptionStringSI =
1439   "e"
1440   "-p:64:64:64"
1441   "-p3:32:32:32"
1442   "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64"
1443   "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128"
1444   "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048"
1445   "-n32:64";
1446 
1447 class R600TargetInfo : public TargetInfo {
1448   /// \brief The GPU profiles supported by the R600 target.
1449   enum GPUKind {
1450     GK_NONE,
1451     GK_R600,
1452     GK_R600_DOUBLE_OPS,
1453     GK_R700,
1454     GK_R700_DOUBLE_OPS,
1455     GK_EVERGREEN,
1456     GK_EVERGREEN_DOUBLE_OPS,
1457     GK_NORTHERN_ISLANDS,
1458     GK_CAYMAN,
1459     GK_SOUTHERN_ISLANDS
1460   } GPU;
1461 
1462 public:
1463   R600TargetInfo(const llvm::Triple &Triple)
1464       : TargetInfo(Triple), GPU(GK_R600) {
1465     DescriptionString = DescriptionStringR600;
1466     AddrSpaceMap = &R600AddrSpaceMap;
1467     UseAddrSpaceMapMangling = true;
1468   }
1469 
1470   virtual const char * getClobbers() const {
1471     return "";
1472   }
1473 
1474   virtual void getGCCRegNames(const char * const *&Names,
1475                               unsigned &numNames) const  {
1476     Names = NULL;
1477     numNames = 0;
1478   }
1479 
1480   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1481                                 unsigned &NumAliases) const {
1482     Aliases = NULL;
1483     NumAliases = 0;
1484   }
1485 
1486   virtual bool validateAsmConstraint(const char *&Name,
1487                                      TargetInfo::ConstraintInfo &info) const {
1488     return true;
1489   }
1490 
1491   virtual void getTargetBuiltins(const Builtin::Info *&Records,
1492                                  unsigned &NumRecords) const {
1493     Records = NULL;
1494     NumRecords = 0;
1495   }
1496 
1497 
1498   virtual void getTargetDefines(const LangOptions &Opts,
1499                                 MacroBuilder &Builder) const {
1500     Builder.defineMacro("__R600__");
1501   }
1502 
1503   virtual BuiltinVaListKind getBuiltinVaListKind() const {
1504     return TargetInfo::CharPtrBuiltinVaList;
1505   }
1506 
1507   virtual bool setCPU(const std::string &Name) {
1508     GPU = llvm::StringSwitch<GPUKind>(Name)
1509       .Case("r600" ,    GK_R600)
1510       .Case("rv610",    GK_R600)
1511       .Case("rv620",    GK_R600)
1512       .Case("rv630",    GK_R600)
1513       .Case("rv635",    GK_R600)
1514       .Case("rs780",    GK_R600)
1515       .Case("rs880",    GK_R600)
1516       .Case("rv670",    GK_R600_DOUBLE_OPS)
1517       .Case("rv710",    GK_R700)
1518       .Case("rv730",    GK_R700)
1519       .Case("rv740",    GK_R700_DOUBLE_OPS)
1520       .Case("rv770",    GK_R700_DOUBLE_OPS)
1521       .Case("palm",     GK_EVERGREEN)
1522       .Case("cedar",    GK_EVERGREEN)
1523       .Case("sumo",     GK_EVERGREEN)
1524       .Case("sumo2",    GK_EVERGREEN)
1525       .Case("redwood",  GK_EVERGREEN)
1526       .Case("juniper",  GK_EVERGREEN)
1527       .Case("hemlock",  GK_EVERGREEN_DOUBLE_OPS)
1528       .Case("cypress",  GK_EVERGREEN_DOUBLE_OPS)
1529       .Case("barts",    GK_NORTHERN_ISLANDS)
1530       .Case("turks",    GK_NORTHERN_ISLANDS)
1531       .Case("caicos",   GK_NORTHERN_ISLANDS)
1532       .Case("cayman",   GK_CAYMAN)
1533       .Case("aruba",    GK_CAYMAN)
1534       .Case("tahiti",   GK_SOUTHERN_ISLANDS)
1535       .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1536       .Case("verde",    GK_SOUTHERN_ISLANDS)
1537       .Case("oland",    GK_SOUTHERN_ISLANDS)
1538       .Default(GK_NONE);
1539 
1540     if (GPU == GK_NONE) {
1541       return false;
1542     }
1543 
1544     // Set the correct data layout
1545     switch (GPU) {
1546     case GK_NONE:
1547     case GK_R600:
1548     case GK_R700:
1549     case GK_EVERGREEN:
1550     case GK_NORTHERN_ISLANDS:
1551       DescriptionString = DescriptionStringR600;
1552       break;
1553     case GK_R600_DOUBLE_OPS:
1554     case GK_R700_DOUBLE_OPS:
1555     case GK_EVERGREEN_DOUBLE_OPS:
1556     case GK_CAYMAN:
1557       DescriptionString = DescriptionStringR600DoubleOps;
1558       break;
1559     case GK_SOUTHERN_ISLANDS:
1560       DescriptionString = DescriptionStringSI;
1561       break;
1562     }
1563 
1564     return true;
1565   }
1566 };
1567 
1568 } // end anonymous namespace
1569 
1570 namespace {
1571 // Namespace for x86 abstract base class
1572 const Builtin::Info BuiltinInfo[] = {
1573 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1574 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1575                                               ALL_LANGUAGES },
1576 #include "clang/Basic/BuiltinsX86.def"
1577 };
1578 
1579 static const char* const GCCRegNames[] = {
1580   "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1581   "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1582   "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1583   "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1584   "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1585   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1586   "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1587   "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1588   "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1589 };
1590 
1591 const TargetInfo::AddlRegName AddlRegNames[] = {
1592   { { "al", "ah", "eax", "rax" }, 0 },
1593   { { "bl", "bh", "ebx", "rbx" }, 3 },
1594   { { "cl", "ch", "ecx", "rcx" }, 2 },
1595   { { "dl", "dh", "edx", "rdx" }, 1 },
1596   { { "esi", "rsi" }, 4 },
1597   { { "edi", "rdi" }, 5 },
1598   { { "esp", "rsp" }, 7 },
1599   { { "ebp", "rbp" }, 6 },
1600 };
1601 
1602 // X86 target abstract base class; x86-32 and x86-64 are very close, so
1603 // most of the implementation can be shared.
1604 class X86TargetInfo : public TargetInfo {
1605   enum X86SSEEnum {
1606     NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
1607   } SSELevel;
1608   enum MMX3DNowEnum {
1609     NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1610   } MMX3DNowLevel;
1611   enum XOPEnum {
1612     NoXOP,
1613     SSE4A,
1614     FMA4,
1615     XOP
1616   } XOPLevel;
1617 
1618   bool HasAES;
1619   bool HasPCLMUL;
1620   bool HasLZCNT;
1621   bool HasRDRND;
1622   bool HasBMI;
1623   bool HasBMI2;
1624   bool HasPOPCNT;
1625   bool HasRTM;
1626   bool HasPRFCHW;
1627   bool HasRDSEED;
1628   bool HasTBM;
1629   bool HasFMA;
1630   bool HasF16C;
1631   bool HasAVX512CD, HasAVX512ER, HasAVX512PF;
1632   bool HasSHA;
1633   bool HasCX16;
1634 
1635   /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1636   ///
1637   /// Each enumeration represents a particular CPU supported by Clang. These
1638   /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1639   enum CPUKind {
1640     CK_Generic,
1641 
1642     /// \name i386
1643     /// i386-generation processors.
1644     //@{
1645     CK_i386,
1646     //@}
1647 
1648     /// \name i486
1649     /// i486-generation processors.
1650     //@{
1651     CK_i486,
1652     CK_WinChipC6,
1653     CK_WinChip2,
1654     CK_C3,
1655     //@}
1656 
1657     /// \name i586
1658     /// i586-generation processors, P5 microarchitecture based.
1659     //@{
1660     CK_i586,
1661     CK_Pentium,
1662     CK_PentiumMMX,
1663     //@}
1664 
1665     /// \name i686
1666     /// i686-generation processors, P6 / Pentium M microarchitecture based.
1667     //@{
1668     CK_i686,
1669     CK_PentiumPro,
1670     CK_Pentium2,
1671     CK_Pentium3,
1672     CK_Pentium3M,
1673     CK_PentiumM,
1674     CK_C3_2,
1675 
1676     /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1677     /// Clang however has some logic to suport this.
1678     // FIXME: Warn, deprecate, and potentially remove this.
1679     CK_Yonah,
1680     //@}
1681 
1682     /// \name Netburst
1683     /// Netburst microarchitecture based processors.
1684     //@{
1685     CK_Pentium4,
1686     CK_Pentium4M,
1687     CK_Prescott,
1688     CK_Nocona,
1689     //@}
1690 
1691     /// \name Core
1692     /// Core microarchitecture based processors.
1693     //@{
1694     CK_Core2,
1695 
1696     /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1697     /// codename which GCC no longer accepts as an option to -march, but Clang
1698     /// has some logic for recognizing it.
1699     // FIXME: Warn, deprecate, and potentially remove this.
1700     CK_Penryn,
1701     //@}
1702 
1703     /// \name Atom
1704     /// Atom processors
1705     //@{
1706     CK_Atom,
1707     CK_Silvermont,
1708     //@}
1709 
1710     /// \name Nehalem
1711     /// Nehalem microarchitecture based processors.
1712     //@{
1713     CK_Corei7,
1714     CK_Corei7AVX,
1715     CK_CoreAVXi,
1716     CK_CoreAVX2,
1717     //@}
1718 
1719     /// \name Knights Landing
1720     /// Knights Landing processor.
1721     CK_KNL,
1722 
1723     /// \name K6
1724     /// K6 architecture processors.
1725     //@{
1726     CK_K6,
1727     CK_K6_2,
1728     CK_K6_3,
1729     //@}
1730 
1731     /// \name K7
1732     /// K7 architecture processors.
1733     //@{
1734     CK_Athlon,
1735     CK_AthlonThunderbird,
1736     CK_Athlon4,
1737     CK_AthlonXP,
1738     CK_AthlonMP,
1739     //@}
1740 
1741     /// \name K8
1742     /// K8 architecture processors.
1743     //@{
1744     CK_Athlon64,
1745     CK_Athlon64SSE3,
1746     CK_AthlonFX,
1747     CK_K8,
1748     CK_K8SSE3,
1749     CK_Opteron,
1750     CK_OpteronSSE3,
1751     CK_AMDFAM10,
1752     //@}
1753 
1754     /// \name Bobcat
1755     /// Bobcat architecture processors.
1756     //@{
1757     CK_BTVER1,
1758     CK_BTVER2,
1759     //@}
1760 
1761     /// \name Bulldozer
1762     /// Bulldozer architecture processors.
1763     //@{
1764     CK_BDVER1,
1765     CK_BDVER2,
1766     //@}
1767 
1768     /// This specification is deprecated and will be removed in the future.
1769     /// Users should prefer \see CK_K8.
1770     // FIXME: Warn on this when the CPU is set to it.
1771     CK_x86_64,
1772     //@}
1773 
1774     /// \name Geode
1775     /// Geode processors.
1776     //@{
1777     CK_Geode
1778     //@}
1779   } CPU;
1780 
1781   enum FPMathKind {
1782     FP_Default,
1783     FP_SSE,
1784     FP_387
1785   } FPMath;
1786 
1787 public:
1788   X86TargetInfo(const llvm::Triple &Triple)
1789       : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1790         XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
1791         HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false),
1792         HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasTBM(false),
1793         HasFMA(false), HasF16C(false), HasAVX512CD(false), HasAVX512ER(false),
1794         HasAVX512PF(false), HasSHA(false), HasCX16(false), CPU(CK_Generic),
1795         FPMath(FP_Default) {
1796     BigEndian = false;
1797     LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1798   }
1799   virtual unsigned getFloatEvalMethod() const {
1800     // X87 evaluates with 80 bits "long double" precision.
1801     return SSELevel == NoSSE ? 2 : 0;
1802   }
1803   virtual void getTargetBuiltins(const Builtin::Info *&Records,
1804                                  unsigned &NumRecords) const {
1805     Records = BuiltinInfo;
1806     NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1807   }
1808   virtual void getGCCRegNames(const char * const *&Names,
1809                               unsigned &NumNames) const {
1810     Names = GCCRegNames;
1811     NumNames = llvm::array_lengthof(GCCRegNames);
1812   }
1813   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
1814                                 unsigned &NumAliases) const {
1815     Aliases = 0;
1816     NumAliases = 0;
1817   }
1818   virtual void getGCCAddlRegNames(const AddlRegName *&Names,
1819                                   unsigned &NumNames) const {
1820     Names = AddlRegNames;
1821     NumNames = llvm::array_lengthof(AddlRegNames);
1822   }
1823   virtual bool validateAsmConstraint(const char *&Name,
1824                                      TargetInfo::ConstraintInfo &info) const;
1825   virtual std::string convertConstraint(const char *&Constraint) const;
1826   virtual const char *getClobbers() const {
1827     return "~{dirflag},~{fpsr},~{flags}";
1828   }
1829   virtual void getTargetDefines(const LangOptions &Opts,
1830                                 MacroBuilder &Builder) const;
1831   static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
1832                           bool Enabled);
1833   static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
1834                           bool Enabled);
1835   static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
1836                           bool Enabled);
1837   virtual void setFeatureEnabled(llvm::StringMap<bool> &Features,
1838                                  StringRef Name, bool Enabled) const {
1839     setFeatureEnabledImpl(Features, Name, Enabled);
1840   }
1841   // This exists purely to cut down on the number of virtual calls in
1842   // getDefaultFeatures which calls this repeatedly.
1843   static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
1844                                     StringRef Name, bool Enabled);
1845   virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const;
1846   virtual bool hasFeature(StringRef Feature) const;
1847   virtual bool handleTargetFeatures(std::vector<std::string> &Features,
1848                                     DiagnosticsEngine &Diags);
1849   virtual const char* getABI() const {
1850     if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
1851       return "avx";
1852     else if (getTriple().getArch() == llvm::Triple::x86 &&
1853              MMX3DNowLevel == NoMMX3DNow)
1854       return "no-mmx";
1855     return "";
1856   }
1857   virtual bool setCPU(const std::string &Name) {
1858     CPU = llvm::StringSwitch<CPUKind>(Name)
1859       .Case("i386", CK_i386)
1860       .Case("i486", CK_i486)
1861       .Case("winchip-c6", CK_WinChipC6)
1862       .Case("winchip2", CK_WinChip2)
1863       .Case("c3", CK_C3)
1864       .Case("i586", CK_i586)
1865       .Case("pentium", CK_Pentium)
1866       .Case("pentium-mmx", CK_PentiumMMX)
1867       .Case("i686", CK_i686)
1868       .Case("pentiumpro", CK_PentiumPro)
1869       .Case("pentium2", CK_Pentium2)
1870       .Case("pentium3", CK_Pentium3)
1871       .Case("pentium3m", CK_Pentium3M)
1872       .Case("pentium-m", CK_PentiumM)
1873       .Case("c3-2", CK_C3_2)
1874       .Case("yonah", CK_Yonah)
1875       .Case("pentium4", CK_Pentium4)
1876       .Case("pentium4m", CK_Pentium4M)
1877       .Case("prescott", CK_Prescott)
1878       .Case("nocona", CK_Nocona)
1879       .Case("core2", CK_Core2)
1880       .Case("penryn", CK_Penryn)
1881       .Case("atom", CK_Atom)
1882       .Case("slm", CK_Silvermont)
1883       .Case("corei7", CK_Corei7)
1884       .Case("corei7-avx", CK_Corei7AVX)
1885       .Case("core-avx-i", CK_CoreAVXi)
1886       .Case("core-avx2", CK_CoreAVX2)
1887       .Case("knl", CK_KNL)
1888       .Case("k6", CK_K6)
1889       .Case("k6-2", CK_K6_2)
1890       .Case("k6-3", CK_K6_3)
1891       .Case("athlon", CK_Athlon)
1892       .Case("athlon-tbird", CK_AthlonThunderbird)
1893       .Case("athlon-4", CK_Athlon4)
1894       .Case("athlon-xp", CK_AthlonXP)
1895       .Case("athlon-mp", CK_AthlonMP)
1896       .Case("athlon64", CK_Athlon64)
1897       .Case("athlon64-sse3", CK_Athlon64SSE3)
1898       .Case("athlon-fx", CK_AthlonFX)
1899       .Case("k8", CK_K8)
1900       .Case("k8-sse3", CK_K8SSE3)
1901       .Case("opteron", CK_Opteron)
1902       .Case("opteron-sse3", CK_OpteronSSE3)
1903       .Case("amdfam10", CK_AMDFAM10)
1904       .Case("btver1", CK_BTVER1)
1905       .Case("btver2", CK_BTVER2)
1906       .Case("bdver1", CK_BDVER1)
1907       .Case("bdver2", CK_BDVER2)
1908       .Case("x86-64", CK_x86_64)
1909       .Case("geode", CK_Geode)
1910       .Default(CK_Generic);
1911 
1912     // Perform any per-CPU checks necessary to determine if this CPU is
1913     // acceptable.
1914     // FIXME: This results in terrible diagnostics. Clang just says the CPU is
1915     // invalid without explaining *why*.
1916     switch (CPU) {
1917     case CK_Generic:
1918       // No processor selected!
1919       return false;
1920 
1921     case CK_i386:
1922     case CK_i486:
1923     case CK_WinChipC6:
1924     case CK_WinChip2:
1925     case CK_C3:
1926     case CK_i586:
1927     case CK_Pentium:
1928     case CK_PentiumMMX:
1929     case CK_i686:
1930     case CK_PentiumPro:
1931     case CK_Pentium2:
1932     case CK_Pentium3:
1933     case CK_Pentium3M:
1934     case CK_PentiumM:
1935     case CK_Yonah:
1936     case CK_C3_2:
1937     case CK_Pentium4:
1938     case CK_Pentium4M:
1939     case CK_Prescott:
1940     case CK_K6:
1941     case CK_K6_2:
1942     case CK_K6_3:
1943     case CK_Athlon:
1944     case CK_AthlonThunderbird:
1945     case CK_Athlon4:
1946     case CK_AthlonXP:
1947     case CK_AthlonMP:
1948     case CK_Geode:
1949       // Only accept certain architectures when compiling in 32-bit mode.
1950       if (getTriple().getArch() != llvm::Triple::x86)
1951         return false;
1952 
1953       // Fallthrough
1954     case CK_Nocona:
1955     case CK_Core2:
1956     case CK_Penryn:
1957     case CK_Atom:
1958     case CK_Silvermont:
1959     case CK_Corei7:
1960     case CK_Corei7AVX:
1961     case CK_CoreAVXi:
1962     case CK_CoreAVX2:
1963     case CK_KNL:
1964     case CK_Athlon64:
1965     case CK_Athlon64SSE3:
1966     case CK_AthlonFX:
1967     case CK_K8:
1968     case CK_K8SSE3:
1969     case CK_Opteron:
1970     case CK_OpteronSSE3:
1971     case CK_AMDFAM10:
1972     case CK_BTVER1:
1973     case CK_BTVER2:
1974     case CK_BDVER1:
1975     case CK_BDVER2:
1976     case CK_x86_64:
1977       return true;
1978     }
1979     llvm_unreachable("Unhandled CPU kind");
1980   }
1981 
1982   virtual bool setFPMath(StringRef Name);
1983 
1984   virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
1985     // We accept all non-ARM calling conventions
1986     return (CC == CC_X86ThisCall ||
1987             CC == CC_X86FastCall ||
1988             CC == CC_X86StdCall ||
1989             CC == CC_C ||
1990             CC == CC_X86Pascal ||
1991             CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
1992   }
1993 
1994   virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
1995     return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
1996   }
1997 };
1998 
1999 bool X86TargetInfo::setFPMath(StringRef Name) {
2000   if (Name == "387") {
2001     FPMath = FP_387;
2002     return true;
2003   }
2004   if (Name == "sse") {
2005     FPMath = FP_SSE;
2006     return true;
2007   }
2008   return false;
2009 }
2010 
2011 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2012   // FIXME: This *really* should not be here.
2013 
2014   // X86_64 always has SSE2.
2015   if (getTriple().getArch() == llvm::Triple::x86_64)
2016     setFeatureEnabledImpl(Features, "sse2", true);
2017 
2018   switch (CPU) {
2019   case CK_Generic:
2020   case CK_i386:
2021   case CK_i486:
2022   case CK_i586:
2023   case CK_Pentium:
2024   case CK_i686:
2025   case CK_PentiumPro:
2026     break;
2027   case CK_PentiumMMX:
2028   case CK_Pentium2:
2029     setFeatureEnabledImpl(Features, "mmx", true);
2030     break;
2031   case CK_Pentium3:
2032   case CK_Pentium3M:
2033     setFeatureEnabledImpl(Features, "sse", true);
2034     break;
2035   case CK_PentiumM:
2036   case CK_Pentium4:
2037   case CK_Pentium4M:
2038   case CK_x86_64:
2039     setFeatureEnabledImpl(Features, "sse2", true);
2040     break;
2041   case CK_Yonah:
2042   case CK_Prescott:
2043   case CK_Nocona:
2044     setFeatureEnabledImpl(Features, "sse3", true);
2045     setFeatureEnabledImpl(Features, "cx16", true);
2046     break;
2047   case CK_Core2:
2048     setFeatureEnabledImpl(Features, "ssse3", true);
2049     setFeatureEnabledImpl(Features, "cx16", true);
2050     break;
2051   case CK_Penryn:
2052     setFeatureEnabledImpl(Features, "sse4.1", true);
2053     setFeatureEnabledImpl(Features, "cx16", true);
2054     break;
2055   case CK_Atom:
2056     setFeatureEnabledImpl(Features, "ssse3", true);
2057     setFeatureEnabledImpl(Features, "cx16", true);
2058     break;
2059   case CK_Silvermont:
2060     setFeatureEnabledImpl(Features, "sse4.2", true);
2061     setFeatureEnabledImpl(Features, "aes", true);
2062     setFeatureEnabledImpl(Features, "cx16", true);
2063     setFeatureEnabledImpl(Features, "pclmul", true);
2064     break;
2065   case CK_Corei7:
2066     setFeatureEnabledImpl(Features, "sse4.2", true);
2067     setFeatureEnabledImpl(Features, "cx16", true);
2068     break;
2069   case CK_Corei7AVX:
2070     setFeatureEnabledImpl(Features, "avx", true);
2071     setFeatureEnabledImpl(Features, "aes", true);
2072     setFeatureEnabledImpl(Features, "cx16", true);
2073     setFeatureEnabledImpl(Features, "pclmul", true);
2074     break;
2075   case CK_CoreAVXi:
2076     setFeatureEnabledImpl(Features, "avx", true);
2077     setFeatureEnabledImpl(Features, "aes", true);
2078     setFeatureEnabledImpl(Features, "pclmul", true);
2079     setFeatureEnabledImpl(Features, "rdrnd", true);
2080     setFeatureEnabledImpl(Features, "f16c", true);
2081     break;
2082   case CK_CoreAVX2:
2083     setFeatureEnabledImpl(Features, "avx2", true);
2084     setFeatureEnabledImpl(Features, "aes", true);
2085     setFeatureEnabledImpl(Features, "pclmul", true);
2086     setFeatureEnabledImpl(Features, "lzcnt", true);
2087     setFeatureEnabledImpl(Features, "rdrnd", true);
2088     setFeatureEnabledImpl(Features, "f16c", true);
2089     setFeatureEnabledImpl(Features, "bmi", true);
2090     setFeatureEnabledImpl(Features, "bmi2", true);
2091     setFeatureEnabledImpl(Features, "rtm", true);
2092     setFeatureEnabledImpl(Features, "fma", true);
2093     setFeatureEnabledImpl(Features, "cx16", true);
2094     break;
2095   case CK_KNL:
2096     setFeatureEnabledImpl(Features, "avx512f", true);
2097     setFeatureEnabledImpl(Features, "avx512cd", true);
2098     setFeatureEnabledImpl(Features, "avx512er", true);
2099     setFeatureEnabledImpl(Features, "avx512pf", true);
2100     setFeatureEnabledImpl(Features, "aes", true);
2101     setFeatureEnabledImpl(Features, "pclmul", true);
2102     setFeatureEnabledImpl(Features, "lzcnt", true);
2103     setFeatureEnabledImpl(Features, "rdrnd", true);
2104     setFeatureEnabledImpl(Features, "f16c", true);
2105     setFeatureEnabledImpl(Features, "bmi", true);
2106     setFeatureEnabledImpl(Features, "bmi2", true);
2107     setFeatureEnabledImpl(Features, "rtm", true);
2108     setFeatureEnabledImpl(Features, "fma", true);
2109     break;
2110   case CK_K6:
2111   case CK_WinChipC6:
2112     setFeatureEnabledImpl(Features, "mmx", true);
2113     break;
2114   case CK_K6_2:
2115   case CK_K6_3:
2116   case CK_WinChip2:
2117   case CK_C3:
2118     setFeatureEnabledImpl(Features, "3dnow", true);
2119     break;
2120   case CK_Athlon:
2121   case CK_AthlonThunderbird:
2122   case CK_Geode:
2123     setFeatureEnabledImpl(Features, "3dnowa", true);
2124     break;
2125   case CK_Athlon4:
2126   case CK_AthlonXP:
2127   case CK_AthlonMP:
2128     setFeatureEnabledImpl(Features, "sse", true);
2129     setFeatureEnabledImpl(Features, "3dnowa", true);
2130     break;
2131   case CK_K8:
2132   case CK_Opteron:
2133   case CK_Athlon64:
2134   case CK_AthlonFX:
2135     setFeatureEnabledImpl(Features, "sse2", true);
2136     setFeatureEnabledImpl(Features, "3dnowa", true);
2137     break;
2138   case CK_K8SSE3:
2139   case CK_OpteronSSE3:
2140   case CK_Athlon64SSE3:
2141     setFeatureEnabledImpl(Features, "sse3", true);
2142     setFeatureEnabledImpl(Features, "3dnowa", true);
2143     break;
2144   case CK_AMDFAM10:
2145     setFeatureEnabledImpl(Features, "sse3", true);
2146     setFeatureEnabledImpl(Features, "sse4a", true);
2147     setFeatureEnabledImpl(Features, "3dnowa", true);
2148     setFeatureEnabledImpl(Features, "lzcnt", true);
2149     setFeatureEnabledImpl(Features, "popcnt", true);
2150     break;
2151   case CK_BTVER1:
2152     setFeatureEnabledImpl(Features, "ssse3", true);
2153     setFeatureEnabledImpl(Features, "sse4a", true);
2154     setFeatureEnabledImpl(Features, "cx16", true);
2155     setFeatureEnabledImpl(Features, "lzcnt", true);
2156     setFeatureEnabledImpl(Features, "popcnt", true);
2157     setFeatureEnabledImpl(Features, "prfchw", true);
2158     break;
2159   case CK_BTVER2:
2160     setFeatureEnabledImpl(Features, "avx", true);
2161     setFeatureEnabledImpl(Features, "sse4a", true);
2162     setFeatureEnabledImpl(Features, "lzcnt", true);
2163     setFeatureEnabledImpl(Features, "aes", true);
2164     setFeatureEnabledImpl(Features, "pclmul", true);
2165     setFeatureEnabledImpl(Features, "prfchw", true);
2166     setFeatureEnabledImpl(Features, "bmi", true);
2167     setFeatureEnabledImpl(Features, "f16c", true);
2168     setFeatureEnabledImpl(Features, "cx16", true);
2169     break;
2170   case CK_BDVER1:
2171     setFeatureEnabledImpl(Features, "xop", true);
2172     setFeatureEnabledImpl(Features, "lzcnt", true);
2173     setFeatureEnabledImpl(Features, "aes", true);
2174     setFeatureEnabledImpl(Features, "pclmul", true);
2175     setFeatureEnabledImpl(Features, "prfchw", true);
2176     setFeatureEnabledImpl(Features, "cx16", true);
2177     break;
2178   case CK_BDVER2:
2179     setFeatureEnabledImpl(Features, "xop", true);
2180     setFeatureEnabledImpl(Features, "lzcnt", true);
2181     setFeatureEnabledImpl(Features, "aes", true);
2182     setFeatureEnabledImpl(Features, "pclmul", true);
2183     setFeatureEnabledImpl(Features, "prfchw", true);
2184     setFeatureEnabledImpl(Features, "bmi", true);
2185     setFeatureEnabledImpl(Features, "fma", true);
2186     setFeatureEnabledImpl(Features, "f16c", true);
2187     setFeatureEnabledImpl(Features, "tbm", true);
2188     setFeatureEnabledImpl(Features, "cx16", true);
2189     break;
2190   case CK_C3_2:
2191     setFeatureEnabledImpl(Features, "sse", true);
2192     break;
2193   }
2194 }
2195 
2196 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2197                                 X86SSEEnum Level, bool Enabled) {
2198   if (Enabled) {
2199     switch (Level) {
2200     case AVX512F:
2201       Features["avx512f"] = true;
2202     case AVX2:
2203       Features["avx2"] = true;
2204     case AVX:
2205       Features["avx"] = true;
2206     case SSE42:
2207       Features["sse4.2"] = true;
2208     case SSE41:
2209       Features["sse4.1"] = true;
2210     case SSSE3:
2211       Features["ssse3"] = true;
2212     case SSE3:
2213       Features["sse3"] = true;
2214     case SSE2:
2215       Features["sse2"] = true;
2216     case SSE1:
2217       Features["sse"] = true;
2218     case NoSSE:
2219       break;
2220     }
2221     return;
2222   }
2223 
2224   switch (Level) {
2225   case NoSSE:
2226   case SSE1:
2227     Features["sse"] = false;
2228   case SSE2:
2229     Features["sse2"] = Features["pclmul"] = Features["aes"] =
2230       Features["sha"] = false;
2231   case SSE3:
2232     Features["sse3"] = false;
2233     setXOPLevel(Features, NoXOP, false);
2234   case SSSE3:
2235     Features["ssse3"] = false;
2236   case SSE41:
2237     Features["sse4.1"] = false;
2238   case SSE42:
2239     Features["sse4.2"] = false;
2240   case AVX:
2241     Features["fma"] = Features["avx"] = Features["f16c"] = false;
2242     setXOPLevel(Features, FMA4, false);
2243   case AVX2:
2244     Features["avx2"] = false;
2245   case AVX512F:
2246     Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
2247       Features["avx512pf"] = false;
2248   }
2249 }
2250 
2251 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2252                                 MMX3DNowEnum Level, bool Enabled) {
2253   if (Enabled) {
2254     switch (Level) {
2255     case AMD3DNowAthlon:
2256       Features["3dnowa"] = true;
2257     case AMD3DNow:
2258       Features["3dnow"] = true;
2259     case MMX:
2260       Features["mmx"] = true;
2261     case NoMMX3DNow:
2262       break;
2263     }
2264     return;
2265   }
2266 
2267   switch (Level) {
2268   case NoMMX3DNow:
2269   case MMX:
2270     Features["mmx"] = false;
2271   case AMD3DNow:
2272     Features["3dnow"] = false;
2273   case AMD3DNowAthlon:
2274     Features["3dnowa"] = false;
2275   }
2276 }
2277 
2278 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2279                                 bool Enabled) {
2280   if (Enabled) {
2281     switch (Level) {
2282     case XOP:
2283       Features["xop"] = true;
2284     case FMA4:
2285       Features["fma4"] = true;
2286       setSSELevel(Features, AVX, true);
2287     case SSE4A:
2288       Features["sse4a"] = true;
2289       setSSELevel(Features, SSE3, true);
2290     case NoXOP:
2291       break;
2292     }
2293     return;
2294   }
2295 
2296   switch (Level) {
2297   case NoXOP:
2298   case SSE4A:
2299     Features["sse4a"] = false;
2300   case FMA4:
2301     Features["fma4"] = false;
2302   case XOP:
2303     Features["xop"] = false;
2304   }
2305 }
2306 
2307 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2308                                           StringRef Name, bool Enabled) {
2309   // FIXME: This *really* should not be here.  We need some way of translating
2310   // options into llvm subtarget features.
2311   if (Name == "sse4")
2312     Name = "sse4.2";
2313 
2314   Features[Name] = Enabled;
2315 
2316   if (Name == "mmx") {
2317     setMMXLevel(Features, MMX, Enabled);
2318   } else if (Name == "sse") {
2319     setSSELevel(Features, SSE1, Enabled);
2320   } else if (Name == "sse2") {
2321     setSSELevel(Features, SSE2, Enabled);
2322   } else if (Name == "sse3") {
2323     setSSELevel(Features, SSE3, Enabled);
2324   } else if (Name == "ssse3") {
2325     setSSELevel(Features, SSSE3, Enabled);
2326   } else if (Name == "sse4.2") {
2327     setSSELevel(Features, SSE42, Enabled);
2328   } else if (Name == "sse4.1") {
2329     setSSELevel(Features, SSE41, Enabled);
2330   } else if (Name == "3dnow") {
2331     setMMXLevel(Features, AMD3DNow, Enabled);
2332   } else if (Name == "3dnowa") {
2333     setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2334   } else if (Name == "aes") {
2335     if (Enabled)
2336       setSSELevel(Features, SSE2, Enabled);
2337   } else if (Name == "pclmul") {
2338     if (Enabled)
2339       setSSELevel(Features, SSE2, Enabled);
2340   } else if (Name == "avx") {
2341     setSSELevel(Features, AVX, Enabled);
2342   } else if (Name == "avx2") {
2343     setSSELevel(Features, AVX2, Enabled);
2344   } else if (Name == "avx512f") {
2345     setSSELevel(Features, AVX512F, Enabled);
2346   } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf") {
2347     if (Enabled)
2348       setSSELevel(Features, AVX512F, Enabled);
2349   } else if (Name == "fma") {
2350     if (Enabled)
2351       setSSELevel(Features, AVX, Enabled);
2352   } else if (Name == "fma4") {
2353     setXOPLevel(Features, FMA4, Enabled);
2354   } else if (Name == "xop") {
2355     setXOPLevel(Features, XOP, Enabled);
2356   } else if (Name == "sse4a") {
2357     setXOPLevel(Features, SSE4A, Enabled);
2358   } else if (Name == "f16c") {
2359     if (Enabled)
2360       setSSELevel(Features, AVX, Enabled);
2361   } else if (Name == "sha") {
2362     if (Enabled)
2363       setSSELevel(Features, SSE2, Enabled);
2364   }
2365 }
2366 
2367 /// handleTargetFeatures - Perform initialization based on the user
2368 /// configured set of features.
2369 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2370                                          DiagnosticsEngine &Diags) {
2371   // Remember the maximum enabled sselevel.
2372   for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2373     // Ignore disabled features.
2374     if (Features[i][0] == '-')
2375       continue;
2376 
2377     StringRef Feature = StringRef(Features[i]).substr(1);
2378 
2379     if (Feature == "aes") {
2380       HasAES = true;
2381       continue;
2382     }
2383 
2384     if (Feature == "pclmul") {
2385       HasPCLMUL = true;
2386       continue;
2387     }
2388 
2389     if (Feature == "lzcnt") {
2390       HasLZCNT = true;
2391       continue;
2392     }
2393 
2394     if (Feature == "rdrnd") {
2395       HasRDRND = true;
2396       continue;
2397     }
2398 
2399     if (Feature == "bmi") {
2400       HasBMI = true;
2401       continue;
2402     }
2403 
2404     if (Feature == "bmi2") {
2405       HasBMI2 = true;
2406       continue;
2407     }
2408 
2409     if (Feature == "popcnt") {
2410       HasPOPCNT = true;
2411       continue;
2412     }
2413 
2414     if (Feature == "rtm") {
2415       HasRTM = true;
2416       continue;
2417     }
2418 
2419     if (Feature == "prfchw") {
2420       HasPRFCHW = true;
2421       continue;
2422     }
2423 
2424     if (Feature == "rdseed") {
2425       HasRDSEED = true;
2426       continue;
2427     }
2428 
2429     if (Feature == "tbm") {
2430       HasTBM = true;
2431       continue;
2432     }
2433 
2434     if (Feature == "fma") {
2435       HasFMA = true;
2436       continue;
2437     }
2438 
2439     if (Feature == "f16c") {
2440       HasF16C = true;
2441       continue;
2442     }
2443 
2444     if (Feature == "avx512cd") {
2445       HasAVX512CD = true;
2446       continue;
2447     }
2448 
2449     if (Feature == "avx512er") {
2450       HasAVX512ER = true;
2451       continue;
2452     }
2453 
2454     if (Feature == "avx512pf") {
2455       HasAVX512PF = true;
2456       continue;
2457     }
2458 
2459     if (Feature == "sha") {
2460       HasSHA = true;
2461       continue;
2462     }
2463 
2464     if (Feature == "cx16") {
2465       HasCX16 = true;
2466       continue;
2467     }
2468 
2469     assert(Features[i][0] == '+' && "Invalid target feature!");
2470     X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2471       .Case("avx512f", AVX512F)
2472       .Case("avx2", AVX2)
2473       .Case("avx", AVX)
2474       .Case("sse4.2", SSE42)
2475       .Case("sse4.1", SSE41)
2476       .Case("ssse3", SSSE3)
2477       .Case("sse3", SSE3)
2478       .Case("sse2", SSE2)
2479       .Case("sse", SSE1)
2480       .Default(NoSSE);
2481     SSELevel = std::max(SSELevel, Level);
2482 
2483     MMX3DNowEnum ThreeDNowLevel =
2484       llvm::StringSwitch<MMX3DNowEnum>(Feature)
2485         .Case("3dnowa", AMD3DNowAthlon)
2486         .Case("3dnow", AMD3DNow)
2487         .Case("mmx", MMX)
2488         .Default(NoMMX3DNow);
2489     MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2490 
2491     XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
2492         .Case("xop", XOP)
2493         .Case("fma4", FMA4)
2494         .Case("sse4a", SSE4A)
2495         .Default(NoXOP);
2496     XOPLevel = std::max(XOPLevel, XLevel);
2497   }
2498 
2499   // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2500   // Can't do this earlier because we need to be able to explicitly enable
2501   // popcnt and still disable sse4.2.
2502   if (!HasPOPCNT && SSELevel >= SSE42 &&
2503       std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){
2504     HasPOPCNT = true;
2505     Features.push_back("+popcnt");
2506   }
2507 
2508   // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
2509   if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow &&
2510       std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){
2511     HasPRFCHW = true;
2512     Features.push_back("+prfchw");
2513   }
2514 
2515   // LLVM doesn't have a separate switch for fpmath, so only accept it if it
2516   // matches the selected sse level.
2517   if (FPMath == FP_SSE && SSELevel < SSE1) {
2518     Diags.Report(diag::err_target_unsupported_fpmath) << "sse";
2519     return false;
2520   } else if (FPMath == FP_387 && SSELevel >= SSE1) {
2521     Diags.Report(diag::err_target_unsupported_fpmath) << "387";
2522     return false;
2523   }
2524 
2525   // Don't tell the backend if we're turning off mmx; it will end up disabling
2526   // SSE, which we don't want.
2527   // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2528   // then enable MMX.
2529   std::vector<std::string>::iterator it;
2530   it = std::find(Features.begin(), Features.end(), "-mmx");
2531   if (it != Features.end())
2532     Features.erase(it);
2533   else if (SSELevel > NoSSE)
2534     MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
2535   return true;
2536 }
2537 
2538 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2539 /// definitions for this particular subtarget.
2540 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2541                                      MacroBuilder &Builder) const {
2542   // Target identification.
2543   if (getTriple().getArch() == llvm::Triple::x86_64) {
2544     Builder.defineMacro("__amd64__");
2545     Builder.defineMacro("__amd64");
2546     Builder.defineMacro("__x86_64");
2547     Builder.defineMacro("__x86_64__");
2548   } else {
2549     DefineStd(Builder, "i386", Opts);
2550   }
2551 
2552   // Subtarget options.
2553   // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2554   // truly should be based on -mtune options.
2555   switch (CPU) {
2556   case CK_Generic:
2557     break;
2558   case CK_i386:
2559     // The rest are coming from the i386 define above.
2560     Builder.defineMacro("__tune_i386__");
2561     break;
2562   case CK_i486:
2563   case CK_WinChipC6:
2564   case CK_WinChip2:
2565   case CK_C3:
2566     defineCPUMacros(Builder, "i486");
2567     break;
2568   case CK_PentiumMMX:
2569     Builder.defineMacro("__pentium_mmx__");
2570     Builder.defineMacro("__tune_pentium_mmx__");
2571     // Fallthrough
2572   case CK_i586:
2573   case CK_Pentium:
2574     defineCPUMacros(Builder, "i586");
2575     defineCPUMacros(Builder, "pentium");
2576     break;
2577   case CK_Pentium3:
2578   case CK_Pentium3M:
2579   case CK_PentiumM:
2580     Builder.defineMacro("__tune_pentium3__");
2581     // Fallthrough
2582   case CK_Pentium2:
2583   case CK_C3_2:
2584     Builder.defineMacro("__tune_pentium2__");
2585     // Fallthrough
2586   case CK_PentiumPro:
2587     Builder.defineMacro("__tune_i686__");
2588     Builder.defineMacro("__tune_pentiumpro__");
2589     // Fallthrough
2590   case CK_i686:
2591     Builder.defineMacro("__i686");
2592     Builder.defineMacro("__i686__");
2593     // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2594     Builder.defineMacro("__pentiumpro");
2595     Builder.defineMacro("__pentiumpro__");
2596     break;
2597   case CK_Pentium4:
2598   case CK_Pentium4M:
2599     defineCPUMacros(Builder, "pentium4");
2600     break;
2601   case CK_Yonah:
2602   case CK_Prescott:
2603   case CK_Nocona:
2604     defineCPUMacros(Builder, "nocona");
2605     break;
2606   case CK_Core2:
2607   case CK_Penryn:
2608     defineCPUMacros(Builder, "core2");
2609     break;
2610   case CK_Atom:
2611     defineCPUMacros(Builder, "atom");
2612     break;
2613   case CK_Silvermont:
2614     defineCPUMacros(Builder, "slm");
2615     break;
2616   case CK_Corei7:
2617   case CK_Corei7AVX:
2618   case CK_CoreAVXi:
2619   case CK_CoreAVX2:
2620     defineCPUMacros(Builder, "corei7");
2621     break;
2622   case CK_KNL:
2623     defineCPUMacros(Builder, "knl");
2624     break;
2625   case CK_K6_2:
2626     Builder.defineMacro("__k6_2__");
2627     Builder.defineMacro("__tune_k6_2__");
2628     // Fallthrough
2629   case CK_K6_3:
2630     if (CPU != CK_K6_2) {  // In case of fallthrough
2631       // FIXME: GCC may be enabling these in cases where some other k6
2632       // architecture is specified but -m3dnow is explicitly provided. The
2633       // exact semantics need to be determined and emulated here.
2634       Builder.defineMacro("__k6_3__");
2635       Builder.defineMacro("__tune_k6_3__");
2636     }
2637     // Fallthrough
2638   case CK_K6:
2639     defineCPUMacros(Builder, "k6");
2640     break;
2641   case CK_Athlon:
2642   case CK_AthlonThunderbird:
2643   case CK_Athlon4:
2644   case CK_AthlonXP:
2645   case CK_AthlonMP:
2646     defineCPUMacros(Builder, "athlon");
2647     if (SSELevel != NoSSE) {
2648       Builder.defineMacro("__athlon_sse__");
2649       Builder.defineMacro("__tune_athlon_sse__");
2650     }
2651     break;
2652   case CK_K8:
2653   case CK_K8SSE3:
2654   case CK_x86_64:
2655   case CK_Opteron:
2656   case CK_OpteronSSE3:
2657   case CK_Athlon64:
2658   case CK_Athlon64SSE3:
2659   case CK_AthlonFX:
2660     defineCPUMacros(Builder, "k8");
2661     break;
2662   case CK_AMDFAM10:
2663     defineCPUMacros(Builder, "amdfam10");
2664     break;
2665   case CK_BTVER1:
2666     defineCPUMacros(Builder, "btver1");
2667     break;
2668   case CK_BTVER2:
2669     defineCPUMacros(Builder, "btver2");
2670     break;
2671   case CK_BDVER1:
2672     defineCPUMacros(Builder, "bdver1");
2673     break;
2674   case CK_BDVER2:
2675     defineCPUMacros(Builder, "bdver2");
2676     break;
2677   case CK_Geode:
2678     defineCPUMacros(Builder, "geode");
2679     break;
2680   }
2681 
2682   // Target properties.
2683   Builder.defineMacro("__LITTLE_ENDIAN__");
2684   Builder.defineMacro("__REGISTER_PREFIX__", "");
2685 
2686   // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2687   // functions in glibc header files that use FP Stack inline asm which the
2688   // backend can't deal with (PR879).
2689   Builder.defineMacro("__NO_MATH_INLINES");
2690 
2691   if (HasAES)
2692     Builder.defineMacro("__AES__");
2693 
2694   if (HasPCLMUL)
2695     Builder.defineMacro("__PCLMUL__");
2696 
2697   if (HasLZCNT)
2698     Builder.defineMacro("__LZCNT__");
2699 
2700   if (HasRDRND)
2701     Builder.defineMacro("__RDRND__");
2702 
2703   if (HasBMI)
2704     Builder.defineMacro("__BMI__");
2705 
2706   if (HasBMI2)
2707     Builder.defineMacro("__BMI2__");
2708 
2709   if (HasPOPCNT)
2710     Builder.defineMacro("__POPCNT__");
2711 
2712   if (HasRTM)
2713     Builder.defineMacro("__RTM__");
2714 
2715   if (HasPRFCHW)
2716     Builder.defineMacro("__PRFCHW__");
2717 
2718   if (HasRDSEED)
2719     Builder.defineMacro("__RDSEED__");
2720 
2721   if (HasTBM)
2722     Builder.defineMacro("__TBM__");
2723 
2724   switch (XOPLevel) {
2725   case XOP:
2726     Builder.defineMacro("__XOP__");
2727   case FMA4:
2728     Builder.defineMacro("__FMA4__");
2729   case SSE4A:
2730     Builder.defineMacro("__SSE4A__");
2731   case NoXOP:
2732     break;
2733   }
2734 
2735   if (HasFMA)
2736     Builder.defineMacro("__FMA__");
2737 
2738   if (HasF16C)
2739     Builder.defineMacro("__F16C__");
2740 
2741   if (HasAVX512CD)
2742     Builder.defineMacro("__AVX512CD__");
2743   if (HasAVX512ER)
2744     Builder.defineMacro("__AVX512ER__");
2745   if (HasAVX512PF)
2746     Builder.defineMacro("__AVX512PF__");
2747 
2748   if (HasSHA)
2749     Builder.defineMacro("__SHA__");
2750 
2751   if (HasCX16)
2752     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
2753 
2754   // Each case falls through to the previous one here.
2755   switch (SSELevel) {
2756   case AVX512F:
2757     Builder.defineMacro("__AVX512F__");
2758   case AVX2:
2759     Builder.defineMacro("__AVX2__");
2760   case AVX:
2761     Builder.defineMacro("__AVX__");
2762   case SSE42:
2763     Builder.defineMacro("__SSE4_2__");
2764   case SSE41:
2765     Builder.defineMacro("__SSE4_1__");
2766   case SSSE3:
2767     Builder.defineMacro("__SSSE3__");
2768   case SSE3:
2769     Builder.defineMacro("__SSE3__");
2770   case SSE2:
2771     Builder.defineMacro("__SSE2__");
2772     Builder.defineMacro("__SSE2_MATH__");  // -mfp-math=sse always implied.
2773   case SSE1:
2774     Builder.defineMacro("__SSE__");
2775     Builder.defineMacro("__SSE_MATH__");   // -mfp-math=sse always implied.
2776   case NoSSE:
2777     break;
2778   }
2779 
2780   if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
2781     switch (SSELevel) {
2782     case AVX512F:
2783     case AVX2:
2784     case AVX:
2785     case SSE42:
2786     case SSE41:
2787     case SSSE3:
2788     case SSE3:
2789     case SSE2:
2790       Builder.defineMacro("_M_IX86_FP", Twine(2));
2791       break;
2792     case SSE1:
2793       Builder.defineMacro("_M_IX86_FP", Twine(1));
2794       break;
2795     default:
2796       Builder.defineMacro("_M_IX86_FP", Twine(0));
2797     }
2798   }
2799 
2800   // Each case falls through to the previous one here.
2801   switch (MMX3DNowLevel) {
2802   case AMD3DNowAthlon:
2803     Builder.defineMacro("__3dNOW_A__");
2804   case AMD3DNow:
2805     Builder.defineMacro("__3dNOW__");
2806   case MMX:
2807     Builder.defineMacro("__MMX__");
2808   case NoMMX3DNow:
2809     break;
2810   }
2811 
2812   if (CPU >= CK_i486) {
2813     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
2814     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
2815     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
2816   }
2817   if (CPU >= CK_i586)
2818     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
2819 }
2820 
2821 bool X86TargetInfo::hasFeature(StringRef Feature) const {
2822   return llvm::StringSwitch<bool>(Feature)
2823       .Case("aes", HasAES)
2824       .Case("avx", SSELevel >= AVX)
2825       .Case("avx2", SSELevel >= AVX2)
2826       .Case("avx512f", SSELevel >= AVX512F)
2827       .Case("avx512cd", HasAVX512CD)
2828       .Case("avx512er", HasAVX512ER)
2829       .Case("avx512pf", HasAVX512PF)
2830       .Case("bmi", HasBMI)
2831       .Case("bmi2", HasBMI2)
2832       .Case("cx16", HasCX16)
2833       .Case("f16c", HasF16C)
2834       .Case("fma", HasFMA)
2835       .Case("fma4", XOPLevel >= FMA4)
2836       .Case("tbm", HasTBM)
2837       .Case("lzcnt", HasLZCNT)
2838       .Case("rdrnd", HasRDRND)
2839       .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
2840       .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
2841       .Case("mmx", MMX3DNowLevel >= MMX)
2842       .Case("pclmul", HasPCLMUL)
2843       .Case("popcnt", HasPOPCNT)
2844       .Case("rtm", HasRTM)
2845       .Case("prfchw", HasPRFCHW)
2846       .Case("rdseed", HasRDSEED)
2847       .Case("sha", HasSHA)
2848       .Case("sse", SSELevel >= SSE1)
2849       .Case("sse2", SSELevel >= SSE2)
2850       .Case("sse3", SSELevel >= SSE3)
2851       .Case("ssse3", SSELevel >= SSSE3)
2852       .Case("sse4.1", SSELevel >= SSE41)
2853       .Case("sse4.2", SSELevel >= SSE42)
2854       .Case("sse4a", XOPLevel >= SSE4A)
2855       .Case("x86", true)
2856       .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
2857       .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
2858       .Case("xop", XOPLevel >= XOP)
2859       .Default(false);
2860 }
2861 
2862 bool
2863 X86TargetInfo::validateAsmConstraint(const char *&Name,
2864                                      TargetInfo::ConstraintInfo &Info) const {
2865   switch (*Name) {
2866   default: return false;
2867   case 'Y': // first letter of a pair:
2868     switch (*(Name+1)) {
2869     default: return false;
2870     case '0':  // First SSE register.
2871     case 't':  // Any SSE register, when SSE2 is enabled.
2872     case 'i':  // Any SSE register, when SSE2 and inter-unit moves enabled.
2873     case 'm':  // any MMX register, when inter-unit moves enabled.
2874       break;   // falls through to setAllowsRegister.
2875   }
2876   case 'a': // eax.
2877   case 'b': // ebx.
2878   case 'c': // ecx.
2879   case 'd': // edx.
2880   case 'S': // esi.
2881   case 'D': // edi.
2882   case 'A': // edx:eax.
2883   case 'f': // any x87 floating point stack register.
2884   case 't': // top of floating point stack.
2885   case 'u': // second from top of floating point stack.
2886   case 'q': // Any register accessible as [r]l: a, b, c, and d.
2887   case 'y': // Any MMX register.
2888   case 'x': // Any SSE register.
2889   case 'Q': // Any register accessible as [r]h: a, b, c, and d.
2890   case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
2891   case 'l': // "Index" registers: any general register that can be used as an
2892             // index in a base+index memory access.
2893     Info.setAllowsRegister();
2894     return true;
2895   case 'C': // SSE floating point constant.
2896   case 'G': // x87 floating point constant.
2897   case 'e': // 32-bit signed integer constant for use with zero-extending
2898             // x86_64 instructions.
2899   case 'Z': // 32-bit unsigned integer constant for use with zero-extending
2900             // x86_64 instructions.
2901     return true;
2902   }
2903 }
2904 
2905 
2906 std::string
2907 X86TargetInfo::convertConstraint(const char *&Constraint) const {
2908   switch (*Constraint) {
2909   case 'a': return std::string("{ax}");
2910   case 'b': return std::string("{bx}");
2911   case 'c': return std::string("{cx}");
2912   case 'd': return std::string("{dx}");
2913   case 'S': return std::string("{si}");
2914   case 'D': return std::string("{di}");
2915   case 'p': // address
2916     return std::string("im");
2917   case 't': // top of floating point stack.
2918     return std::string("{st}");
2919   case 'u': // second from top of floating point stack.
2920     return std::string("{st(1)}"); // second from top of floating point stack.
2921   default:
2922     return std::string(1, *Constraint);
2923   }
2924 }
2925 } // end anonymous namespace
2926 
2927 namespace {
2928 // X86-32 generic target
2929 class X86_32TargetInfo : public X86TargetInfo {
2930 public:
2931   X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
2932     DoubleAlign = LongLongAlign = 32;
2933     LongDoubleWidth = 96;
2934     LongDoubleAlign = 32;
2935     SuitableAlign = 128;
2936     DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
2937                         "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
2938                         "a0:0:64-f80:32:32-n8:16:32-S128";
2939     SizeType = UnsignedInt;
2940     PtrDiffType = SignedInt;
2941     IntPtrType = SignedInt;
2942     RegParmMax = 3;
2943 
2944     // Use fpret for all types.
2945     RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
2946                              (1 << TargetInfo::Double) |
2947                              (1 << TargetInfo::LongDouble));
2948 
2949     // x86-32 has atomics up to 8 bytes
2950     // FIXME: Check that we actually have cmpxchg8b before setting
2951     // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
2952     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
2953   }
2954   virtual BuiltinVaListKind getBuiltinVaListKind() const {
2955     return TargetInfo::CharPtrBuiltinVaList;
2956   }
2957 
2958   int getEHDataRegisterNumber(unsigned RegNo) const {
2959     if (RegNo == 0) return 0;
2960     if (RegNo == 1) return 2;
2961     return -1;
2962   }
2963   virtual bool validateInputSize(StringRef Constraint,
2964                                  unsigned Size) const {
2965     switch (Constraint[0]) {
2966     default: break;
2967     case 'a':
2968     case 'b':
2969     case 'c':
2970     case 'd':
2971       return Size <= 32;
2972     }
2973 
2974     return true;
2975   }
2976 };
2977 } // end anonymous namespace
2978 
2979 namespace {
2980 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
2981 public:
2982   NetBSDI386TargetInfo(const llvm::Triple &Triple)
2983       : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
2984 
2985   virtual unsigned getFloatEvalMethod() const {
2986     // NetBSD defaults to "double" rounding
2987     return 1;
2988   }
2989 };
2990 } // end anonymous namespace
2991 
2992 namespace {
2993 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
2994 public:
2995   OpenBSDI386TargetInfo(const llvm::Triple &Triple)
2996       : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
2997     SizeType = UnsignedLong;
2998     IntPtrType = SignedLong;
2999     PtrDiffType = SignedLong;
3000   }
3001 };
3002 } // end anonymous namespace
3003 
3004 namespace {
3005 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3006 public:
3007   BitrigI386TargetInfo(const llvm::Triple &Triple)
3008       : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3009     SizeType = UnsignedLong;
3010     IntPtrType = SignedLong;
3011     PtrDiffType = SignedLong;
3012   }
3013 };
3014 } // end anonymous namespace
3015 
3016 namespace {
3017 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3018 public:
3019   DarwinI386TargetInfo(const llvm::Triple &Triple)
3020       : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3021     LongDoubleWidth = 128;
3022     LongDoubleAlign = 128;
3023     SuitableAlign = 128;
3024     MaxVectorAlign = 256;
3025     SizeType = UnsignedLong;
3026     IntPtrType = SignedLong;
3027     DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3028                         "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-"
3029                         "a0:0:64-f80:128:128-n8:16:32-S128";
3030     HasAlignMac68kSupport = true;
3031   }
3032 
3033 };
3034 } // end anonymous namespace
3035 
3036 namespace {
3037 // x86-32 Windows target
3038 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3039 public:
3040   WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3041       : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3042     TLSSupported = false;
3043     WCharType = UnsignedShort;
3044     DoubleAlign = LongLongAlign = 64;
3045     DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3046                         "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-"
3047                         "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32";
3048   }
3049   virtual void getTargetDefines(const LangOptions &Opts,
3050                                 MacroBuilder &Builder) const {
3051     WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3052   }
3053 };
3054 } // end anonymous namespace
3055 
3056 namespace {
3057 
3058 // x86-32 Windows Visual Studio target
3059 class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo {
3060 public:
3061   VisualStudioWindowsX86_32TargetInfo(const llvm::Triple &Triple)
3062       : WindowsX86_32TargetInfo(Triple) {
3063     LongDoubleWidth = LongDoubleAlign = 64;
3064     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3065   }
3066   virtual void getTargetDefines(const LangOptions &Opts,
3067                                 MacroBuilder &Builder) const {
3068     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3069     WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3070     // The value of the following reflects processor type.
3071     // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3072     // We lost the original triple, so we use the default.
3073     Builder.defineMacro("_M_IX86", "600");
3074   }
3075 };
3076 } // end anonymous namespace
3077 
3078 namespace {
3079 // x86-32 MinGW target
3080 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3081 public:
3082   MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3083       : WindowsX86_32TargetInfo(Triple) {}
3084   virtual void getTargetDefines(const LangOptions &Opts,
3085                                 MacroBuilder &Builder) const {
3086     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3087     DefineStd(Builder, "WIN32", Opts);
3088     DefineStd(Builder, "WINNT", Opts);
3089     Builder.defineMacro("_X86_");
3090     Builder.defineMacro("__MSVCRT__");
3091     Builder.defineMacro("__MINGW32__");
3092 
3093     // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3094     // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3095     if (Opts.MicrosoftExt)
3096       // Provide "as-is" __declspec.
3097       Builder.defineMacro("__declspec", "__declspec");
3098     else
3099       // Provide alias of __attribute__ like mingw32-gcc.
3100       Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3101   }
3102 };
3103 } // end anonymous namespace
3104 
3105 namespace {
3106 // x86-32 Cygwin target
3107 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3108 public:
3109   CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3110       : X86_32TargetInfo(Triple) {
3111     TLSSupported = false;
3112     WCharType = UnsignedShort;
3113     DoubleAlign = LongLongAlign = 64;
3114     DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3115                         "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3116                         "a0:0:64-f80:32:32-n8:16:32-S32";
3117   }
3118   virtual void getTargetDefines(const LangOptions &Opts,
3119                                 MacroBuilder &Builder) const {
3120     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3121     Builder.defineMacro("_X86_");
3122     Builder.defineMacro("__CYGWIN__");
3123     Builder.defineMacro("__CYGWIN32__");
3124     DefineStd(Builder, "unix", Opts);
3125     if (Opts.CPlusPlus)
3126       Builder.defineMacro("_GNU_SOURCE");
3127   }
3128 };
3129 } // end anonymous namespace
3130 
3131 namespace {
3132 // x86-32 Haiku target
3133 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3134 public:
3135   HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3136     SizeType = UnsignedLong;
3137     IntPtrType = SignedLong;
3138     PtrDiffType = SignedLong;
3139     ProcessIDType = SignedLong;
3140     this->UserLabelPrefix = "";
3141     this->TLSSupported = false;
3142   }
3143   virtual void getTargetDefines(const LangOptions &Opts,
3144                                 MacroBuilder &Builder) const {
3145     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3146     Builder.defineMacro("__INTEL__");
3147     Builder.defineMacro("__HAIKU__");
3148   }
3149 };
3150 } // end anonymous namespace
3151 
3152 // RTEMS Target
3153 template<typename Target>
3154 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3155 protected:
3156   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3157                             MacroBuilder &Builder) const {
3158     // RTEMS defines; list based off of gcc output
3159 
3160     Builder.defineMacro("__rtems__");
3161     Builder.defineMacro("__ELF__");
3162   }
3163 
3164 public:
3165   RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3166     this->UserLabelPrefix = "";
3167 
3168     switch (Triple.getArch()) {
3169     default:
3170     case llvm::Triple::x86:
3171       // this->MCountName = ".mcount";
3172       break;
3173     case llvm::Triple::mips:
3174     case llvm::Triple::mipsel:
3175     case llvm::Triple::ppc:
3176     case llvm::Triple::ppc64:
3177     case llvm::Triple::ppc64le:
3178       // this->MCountName = "_mcount";
3179       break;
3180     case llvm::Triple::arm:
3181       // this->MCountName = "__mcount";
3182       break;
3183     }
3184   }
3185 };
3186 
3187 namespace {
3188 // x86-32 RTEMS target
3189 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3190 public:
3191   RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3192     SizeType = UnsignedLong;
3193     IntPtrType = SignedLong;
3194     PtrDiffType = SignedLong;
3195     this->UserLabelPrefix = "";
3196   }
3197   virtual void getTargetDefines(const LangOptions &Opts,
3198                                 MacroBuilder &Builder) const {
3199     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3200     Builder.defineMacro("__INTEL__");
3201     Builder.defineMacro("__rtems__");
3202   }
3203 };
3204 } // end anonymous namespace
3205 
3206 namespace {
3207 // x86-64 generic target
3208 class X86_64TargetInfo : public X86TargetInfo {
3209 public:
3210   X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3211     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
3212     LongDoubleWidth = 128;
3213     LongDoubleAlign = 128;
3214     LargeArrayMinWidth = 128;
3215     LargeArrayAlign = 128;
3216     SuitableAlign = 128;
3217     IntMaxType = SignedLong;
3218     UIntMaxType = UnsignedLong;
3219     Int64Type = SignedLong;
3220     RegParmMax = 6;
3221 
3222     DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3223                         "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-"
3224                         "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128";
3225 
3226     // Use fpret only for long double.
3227     RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3228 
3229     // Use fp2ret for _Complex long double.
3230     ComplexLongDoubleUsesFP2Ret = true;
3231 
3232     // x86-64 has atomics up to 16 bytes.
3233     // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128
3234     // on CPUs with cmpxchg16b
3235     MaxAtomicPromoteWidth = 128;
3236     MaxAtomicInlineWidth = 64;
3237   }
3238   virtual BuiltinVaListKind getBuiltinVaListKind() const {
3239     return TargetInfo::X86_64ABIBuiltinVaList;
3240   }
3241 
3242   int getEHDataRegisterNumber(unsigned RegNo) const {
3243     if (RegNo == 0) return 0;
3244     if (RegNo == 1) return 1;
3245     return -1;
3246   }
3247 
3248   virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3249     return (CC == CC_C ||
3250             CC == CC_IntelOclBicc ||
3251             CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
3252   }
3253 
3254   virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const {
3255     return CC_C;
3256   }
3257 
3258 };
3259 } // end anonymous namespace
3260 
3261 namespace {
3262 // x86-64 Windows target
3263 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3264 public:
3265   WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3266       : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3267     TLSSupported = false;
3268     WCharType = UnsignedShort;
3269     LongWidth = LongAlign = 32;
3270     DoubleAlign = LongLongAlign = 64;
3271     IntMaxType = SignedLongLong;
3272     UIntMaxType = UnsignedLongLong;
3273     Int64Type = SignedLongLong;
3274     SizeType = UnsignedLongLong;
3275     PtrDiffType = SignedLongLong;
3276     IntPtrType = SignedLongLong;
3277     this->UserLabelPrefix = "";
3278   }
3279   virtual void getTargetDefines(const LangOptions &Opts,
3280                                 MacroBuilder &Builder) const {
3281     WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3282     Builder.defineMacro("_WIN64");
3283   }
3284   virtual BuiltinVaListKind getBuiltinVaListKind() const {
3285     return TargetInfo::CharPtrBuiltinVaList;
3286   }
3287   virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
3288     return (CC == CC_C ||
3289             CC == CC_IntelOclBicc ||
3290             CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning;
3291   }
3292 };
3293 } // end anonymous namespace
3294 
3295 namespace {
3296 // x86-64 Windows Visual Studio target
3297 class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo {
3298 public:
3299   VisualStudioWindowsX86_64TargetInfo(const llvm::Triple &Triple)
3300       : WindowsX86_64TargetInfo(Triple) {
3301     LongDoubleWidth = LongDoubleAlign = 64;
3302     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3303   }
3304   virtual void getTargetDefines(const LangOptions &Opts,
3305                                 MacroBuilder &Builder) const {
3306     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3307     WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3308     Builder.defineMacro("_M_X64");
3309     Builder.defineMacro("_M_AMD64");
3310   }
3311 };
3312 } // end anonymous namespace
3313 
3314 namespace {
3315 // x86-64 MinGW target
3316 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3317 public:
3318   MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3319       : WindowsX86_64TargetInfo(Triple) {}
3320   virtual void getTargetDefines(const LangOptions &Opts,
3321                                 MacroBuilder &Builder) const {
3322     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3323     DefineStd(Builder, "WIN64", Opts);
3324     Builder.defineMacro("__MSVCRT__");
3325     Builder.defineMacro("__MINGW32__");
3326     Builder.defineMacro("__MINGW64__");
3327 
3328     // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)).
3329     // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions.
3330     if (Opts.MicrosoftExt)
3331       // Provide "as-is" __declspec.
3332       Builder.defineMacro("__declspec", "__declspec");
3333     else
3334       // Provide alias of __attribute__ like mingw32-gcc.
3335       Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3336   }
3337 };
3338 } // end anonymous namespace
3339 
3340 namespace {
3341 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3342 public:
3343   DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3344       : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3345     Int64Type = SignedLongLong;
3346     MaxVectorAlign = 256;
3347   }
3348 };
3349 } // end anonymous namespace
3350 
3351 namespace {
3352 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3353 public:
3354   OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
3355       : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
3356     IntMaxType = SignedLongLong;
3357     UIntMaxType = UnsignedLongLong;
3358     Int64Type = SignedLongLong;
3359   }
3360 };
3361 } // end anonymous namespace
3362 
3363 namespace {
3364 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3365 public:
3366   BitrigX86_64TargetInfo(const llvm::Triple &Triple)
3367       : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
3368     IntMaxType = SignedLongLong;
3369     UIntMaxType = UnsignedLongLong;
3370     Int64Type = SignedLongLong;
3371   }
3372 };
3373 }
3374 
3375 namespace {
3376 class AArch64TargetInfo : public TargetInfo {
3377   static const char * const GCCRegNames[];
3378   static const TargetInfo::GCCRegAlias GCCRegAliases[];
3379 
3380   enum FPUModeEnum {
3381     FPUMode,
3382     NeonMode
3383   };
3384 
3385   unsigned FPU;
3386   static const Builtin::Info BuiltinInfo[];
3387 
3388 public:
3389   AArch64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
3390     BigEndian = false;
3391     LongWidth = LongAlign = 64;
3392     LongDoubleWidth = LongDoubleAlign = 128;
3393     PointerWidth = PointerAlign = 64;
3394     SuitableAlign = 128;
3395     DescriptionString = "e-p:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3396                         "i64:64:64-i128:128:128-f32:32:32-f64:64:64-"
3397                         "f128:128:128-n32:64-S128";
3398 
3399     WCharType = UnsignedInt;
3400     LongDoubleFormat = &llvm::APFloat::IEEEquad;
3401 
3402     // AArch64 backend supports 64-bit operations at the moment. In principle
3403     // 128-bit is possible if register-pairs are used.
3404     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3405 
3406     TheCXXABI.set(TargetCXXABI::GenericAArch64);
3407   }
3408   virtual void getTargetDefines(const LangOptions &Opts,
3409                                 MacroBuilder &Builder) const {
3410     // GCC defines theses currently
3411     Builder.defineMacro("__aarch64__");
3412     Builder.defineMacro("__AARCH64EL__");
3413 
3414     // ACLE predefines. Many can only have one possible value on v8 AArch64.
3415 
3416     // FIXME: these were written based on an unreleased version of a 32-bit ACLE
3417     // which was intended to be compatible with a 64-bit implementation. They
3418     // will need updating when a real 64-bit ACLE exists. Particularly pressing
3419     // instances are: __ARM_ARCH_ISA_ARM, __ARM_ARCH_ISA_THUMB, __ARM_PCS.
3420     Builder.defineMacro("__ARM_ACLE",         "101");
3421     Builder.defineMacro("__ARM_ARCH",         "8");
3422     Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
3423 
3424     Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
3425     Builder.defineMacro("__ARM_FEATURE_CLZ");
3426     Builder.defineMacro("__ARM_FEATURE_FMA");
3427 
3428     // FIXME: ACLE 1.1 reserves bit 4. Will almost certainly come to mean
3429     // 128-bit LDXP present, at which point this becomes 0x1f.
3430     Builder.defineMacro("__ARM_FEATURE_LDREX", "0xf");
3431 
3432     // 0xe implies support for half, single and double precision operations.
3433     Builder.defineMacro("__ARM_FP", "0xe");
3434 
3435     // PCS specifies this for SysV variants, which is all we support. Other ABIs
3436     // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
3437     Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
3438 
3439     if (Opts.FastMath || Opts.FiniteMathOnly)
3440       Builder.defineMacro("__ARM_FP_FAST");
3441 
3442     if ((Opts.C99 || Opts.C11) && !Opts.Freestanding)
3443       Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
3444 
3445     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
3446                         Opts.ShortWChar ? "2" : "4");
3447 
3448     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
3449                         Opts.ShortEnums ? "1" : "4");
3450 
3451     if (BigEndian)
3452       Builder.defineMacro("__AARCH_BIG_ENDIAN");
3453 
3454     if (FPU == NeonMode) {
3455       Builder.defineMacro("__AARCH_FEATURE_ADVSIMD");
3456 
3457       // 64-bit NEON supports half, single and double precision operations.
3458       Builder.defineMacro("__AARCH_ADVSIMD_FP", "0xe");
3459     }
3460   }
3461   virtual void getTargetBuiltins(const Builtin::Info *&Records,
3462                                  unsigned &NumRecords) const {
3463     Records = BuiltinInfo;
3464     NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin;
3465   }
3466   virtual bool hasFeature(StringRef Feature) const {
3467     return Feature == "aarch64" || (Feature == "neon" && FPU == NeonMode);
3468   }
3469 
3470   virtual bool handleTargetFeatures(std::vector<std::string> &Features,
3471                                     DiagnosticsEngine &Diags) {
3472     FPU = FPUMode;
3473     for (unsigned i = 0, e = Features.size(); i != e; ++i) {
3474       if (Features[i] == "+neon")
3475         FPU = NeonMode;
3476     }
3477     return true;
3478   }
3479 
3480   virtual void getGCCRegNames(const char *const *&Names,
3481                               unsigned &NumNames) const;
3482   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3483                                 unsigned &NumAliases) const;
3484 
3485   virtual bool isCLZForZeroUndef() const { return false; }
3486 
3487   virtual bool validateAsmConstraint(const char *&Name,
3488                                      TargetInfo::ConstraintInfo &Info) const {
3489     switch (*Name) {
3490     default: return false;
3491     case 'w': // An FP/SIMD vector register
3492       Info.setAllowsRegister();
3493       return true;
3494     case 'I': // Constant that can be used with an ADD instruction
3495     case 'J': // Constant that can be used with a SUB instruction
3496     case 'K': // Constant that can be used with a 32-bit logical instruction
3497     case 'L': // Constant that can be used with a 64-bit logical instruction
3498     case 'M': // Constant that can be used as a 32-bit MOV immediate
3499     case 'N': // Constant that can be used as a 64-bit MOV immediate
3500     case 'Y': // Floating point constant zero
3501     case 'Z': // Integer constant zero
3502       return true;
3503     case 'Q': // A memory reference with base register and no offset
3504       Info.setAllowsMemory();
3505       return true;
3506     case 'S': // A symbolic address
3507       Info.setAllowsRegister();
3508       return true;
3509     case 'U':
3510       // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be
3511       // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
3512       // Usa: An absolute symbolic address
3513       // Ush: The high part (bits 32:12) of a pc-relative symbolic address
3514       llvm_unreachable("FIXME: Unimplemented support for bizarre constraints");
3515     }
3516   }
3517 
3518   virtual const char *getClobbers() const {
3519     // There are no AArch64 clobbers shared by all asm statements.
3520     return "";
3521   }
3522 
3523   virtual BuiltinVaListKind getBuiltinVaListKind() const {
3524     return TargetInfo::AArch64ABIBuiltinVaList;
3525   }
3526 };
3527 
3528 const char * const AArch64TargetInfo::GCCRegNames[] = {
3529   "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7",
3530   "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15",
3531   "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23",
3532   "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr",
3533 
3534   "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
3535   "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
3536   "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
3537   "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr",
3538 
3539   "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
3540   "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15",
3541   "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23",
3542   "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31",
3543 
3544   "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7",
3545   "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15",
3546   "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23",
3547   "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31",
3548 
3549   "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
3550   "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
3551   "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
3552   "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
3553 
3554   "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
3555   "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
3556   "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
3557   "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
3558 
3559   "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3560   "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
3561   "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23",
3562   "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31"
3563 };
3564 
3565 void AArch64TargetInfo::getGCCRegNames(const char * const *&Names,
3566                                        unsigned &NumNames) const {
3567   Names = GCCRegNames;
3568   NumNames = llvm::array_lengthof(GCCRegNames);
3569 }
3570 
3571 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
3572   { { "x16" }, "ip0"},
3573   { { "x17" }, "ip1"},
3574   { { "x29" }, "fp" },
3575   { { "x30" }, "lr" }
3576 };
3577 
3578 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
3579                                          unsigned &NumAliases) const {
3580   Aliases = GCCRegAliases;
3581   NumAliases = llvm::array_lengthof(GCCRegAliases);
3582 
3583 }
3584 
3585 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
3586 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
3587 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
3588                                               ALL_LANGUAGES },
3589 #include "clang/Basic/BuiltinsAArch64.def"
3590 };
3591 
3592 } // end anonymous namespace
3593 
3594 namespace {
3595 class ARMTargetInfo : public TargetInfo {
3596   // Possible FPU choices.
3597   enum FPUMode {
3598     VFP2FPU = (1 << 0),
3599     VFP3FPU = (1 << 1),
3600     VFP4FPU = (1 << 2),
3601     NeonFPU = (1 << 3),
3602     FPARMV8 = (1 << 4)
3603   };
3604 
3605   // Possible HWDiv features.
3606   enum HWDivMode {
3607     HWDivThumb = (1 << 0),
3608     HWDivARM = (1 << 1)
3609   };
3610 
3611   static bool FPUModeIsVFP(FPUMode Mode) {
3612     return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
3613   }
3614 
3615   static const TargetInfo::GCCRegAlias GCCRegAliases[];
3616   static const char * const GCCRegNames[];
3617 
3618   std::string ABI, CPU;
3619 
3620   enum {
3621     FP_Default,
3622     FP_VFP,
3623     FP_Neon
3624   } FPMath;
3625 
3626   unsigned FPU : 5;
3627 
3628   unsigned IsAAPCS : 1;
3629   unsigned IsThumb : 1;
3630   unsigned HWDiv : 2;
3631 
3632   // Initialized via features.
3633   unsigned SoftFloat : 1;
3634   unsigned SoftFloatABI : 1;
3635 
3636   static const Builtin::Info BuiltinInfo[];
3637 
3638   static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3639     // On linux, binaries targeting old cpus call functions in libgcc to
3640     // perform atomic operations. The implementation in libgcc then calls into
3641     // the kernel which on armv6 and newer uses ldrex and strex. The net result
3642     // is that if we assume the kernel is at least as recent as the hardware,
3643     // it is safe to use atomic instructions on armv6 and newer.
3644     if (!T.isOSLinux() &&
3645         T.getOS() != llvm::Triple::FreeBSD &&
3646         T.getOS() != llvm::Triple::Bitrig)
3647       return false;
3648     StringRef ArchName = T.getArchName();
3649     if (T.getArch() == llvm::Triple::arm) {
3650       if (!ArchName.startswith("armv"))
3651         return false;
3652       StringRef VersionStr = ArchName.substr(4);
3653       unsigned Version;
3654       if (VersionStr.getAsInteger(10, Version))
3655         return false;
3656       return Version >= 6;
3657     }
3658     assert(T.getArch() == llvm::Triple::thumb);
3659     if (!ArchName.startswith("thumbv"))
3660       return false;
3661     StringRef VersionStr = ArchName.substr(6);
3662     unsigned Version;
3663     if (VersionStr.getAsInteger(10, Version))
3664       return false;
3665     return Version >= 7;
3666   }
3667 
3668 public:
3669   ARMTargetInfo(const llvm::Triple &Triple)
3670       : TargetInfo(Triple), ABI("aapcs-linux"), CPU("arm1136j-s"),
3671         FPMath(FP_Default), IsAAPCS(true) {
3672     BigEndian = false;
3673     SizeType = UnsignedInt;
3674     PtrDiffType = SignedInt;
3675     // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3676     WCharType = UnsignedInt;
3677 
3678     // {} in inline assembly are neon specifiers, not assembly variant
3679     // specifiers.
3680     NoAsmVariants = true;
3681 
3682     // FIXME: Should we just treat this as a feature?
3683     IsThumb = getTriple().getArchName().startswith("thumb");
3684     if (IsThumb) {
3685       // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3686       // so set preferred for small types to 32.
3687       DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3688                            "i64:64:64-f32:32:32-f64:64:64-"
3689                            "v64:64:64-v128:64:128-a0:0:32-n32-S64");
3690     } else {
3691       DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3692                            "i64:64:64-f32:32:32-f64:64:64-"
3693                            "v64:64:64-v128:64:128-a0:0:64-n32-S64");
3694     }
3695 
3696     // ARM targets default to using the ARM C++ ABI.
3697     TheCXXABI.set(TargetCXXABI::GenericARM);
3698 
3699     // ARM has atomics up to 8 bytes
3700     MaxAtomicPromoteWidth = 64;
3701     if (shouldUseInlineAtomic(getTriple()))
3702       MaxAtomicInlineWidth = 64;
3703 
3704     // Do force alignment of members that follow zero length bitfields.  If
3705     // the alignment of the zero-length bitfield is greater than the member
3706     // that follows it, `bar', `bar' will be aligned as the  type of the
3707     // zero length bitfield.
3708     UseZeroLengthBitfieldAlignment = true;
3709   }
3710   virtual const char *getABI() const { return ABI.c_str(); }
3711   virtual bool setABI(const std::string &Name) {
3712     ABI = Name;
3713 
3714     // The defaults (above) are for AAPCS, check if we need to change them.
3715     //
3716     // FIXME: We need support for -meabi... we could just mangle it into the
3717     // name.
3718     if (Name == "apcs-gnu") {
3719       DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3720       // size_t is unsigned int on FreeBSD.
3721       if (getTriple().getOS() != llvm::Triple::FreeBSD)
3722         SizeType = UnsignedLong;
3723 
3724       // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3725       WCharType = SignedInt;
3726 
3727       // Do not respect the alignment of bit-field types when laying out
3728       // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3729       UseBitFieldTypeAlignment = false;
3730 
3731       /// gcc forces the alignment to 4 bytes, regardless of the type of the
3732       /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
3733       /// gcc.
3734       ZeroLengthBitfieldBoundary = 32;
3735 
3736       IsAAPCS = false;
3737 
3738       if (IsThumb) {
3739         // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3740         // so set preferred for small types to 32.
3741         DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
3742                              "i64:32:64-f32:32:32-f64:32:64-"
3743                              "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3744       } else {
3745         DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
3746                              "i64:32:64-f32:32:32-f64:32:64-"
3747                              "v64:32:64-v128:32:128-a0:0:32-n32-S32");
3748       }
3749 
3750       // FIXME: Override "preferred align" for double and long long.
3751     } else if (Name == "aapcs" || Name == "aapcs-vfp") {
3752       // size_t is unsigned long on Darwin.
3753       if (getTriple().isOSDarwin())
3754         SizeType = UnsignedLong;
3755       IsAAPCS = true;
3756       // FIXME: Enumerated types are variable width in straight AAPCS.
3757     } else if (Name == "aapcs-linux") {
3758       IsAAPCS = true;
3759     } else
3760       return false;
3761 
3762     return true;
3763   }
3764 
3765   void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
3766     StringRef ArchName = getTriple().getArchName();
3767     if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3768       Features["vfp2"] = true;
3769     else if (CPU == "cortex-a8" || CPU == "cortex-a9" ||
3770              CPU == "cortex-a9-mp") {
3771       Features["vfp3"] = true;
3772       Features["neon"] = true;
3773     }
3774     else if (CPU == "cortex-a5") {
3775       Features["vfp4"] = true;
3776       Features["neon"] = true;
3777     } else if (CPU == "swift" || CPU == "cortex-a7" || CPU == "cortex-a15") {
3778       Features["vfp4"] = true;
3779       Features["neon"] = true;
3780       Features["hwdiv"] = true;
3781       Features["hwdiv-arm"] = true;
3782     } else if (CPU == "cortex-a53" || CPU == "cortex-a57") {
3783       Features["fp-armv8"] = true;
3784       Features["neon"] = true;
3785       Features["hwdiv"] = true;
3786       Features["hwdiv-arm"] = true;
3787     } else if (CPU == "cortex-r5" || CPU == "cortex-m3" ||
3788                CPU == "cortex-m4" ||
3789                // Enable the hwdiv extension for all v8a AArch32 cores by
3790                // default.
3791                ArchName == "armv8a" || ArchName == "armv8" ||
3792                ArchName == "thumbv8a" || ArchName == "thumbv8") {
3793       Features["hwdiv"] = true;
3794       Features["hwdiv-arm"] = true;
3795     }
3796   }
3797 
3798   virtual bool handleTargetFeatures(std::vector<std::string> &Features,
3799                                     DiagnosticsEngine &Diags) {
3800     FPU = 0;
3801     SoftFloat = SoftFloatABI = false;
3802     HWDiv = 0;
3803     for (unsigned i = 0, e = Features.size(); i != e; ++i) {
3804       if (Features[i] == "+soft-float")
3805         SoftFloat = true;
3806       else if (Features[i] == "+soft-float-abi")
3807         SoftFloatABI = true;
3808       else if (Features[i] == "+vfp2")
3809         FPU |= VFP2FPU;
3810       else if (Features[i] == "+vfp3")
3811         FPU |= VFP3FPU;
3812       else if (Features[i] == "+vfp4")
3813         FPU |= VFP4FPU;
3814       else if (Features[i] == "+fp-armv8")
3815         FPU |= FPARMV8;
3816       else if (Features[i] == "+neon")
3817         FPU |= NeonFPU;
3818       else if (Features[i] == "+hwdiv")
3819         HWDiv |= HWDivThumb;
3820       else if (Features[i] == "+hwdiv-arm")
3821         HWDiv |= HWDivARM;
3822     }
3823 
3824     if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
3825       Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
3826       return false;
3827     }
3828 
3829     if (FPMath == FP_Neon)
3830       Features.push_back("+neonfp");
3831     else if (FPMath == FP_VFP)
3832       Features.push_back("-neonfp");
3833 
3834     // Remove front-end specific options which the backend handles differently.
3835     std::vector<std::string>::iterator it;
3836     it = std::find(Features.begin(), Features.end(), "+soft-float");
3837     if (it != Features.end())
3838       Features.erase(it);
3839     it = std::find(Features.begin(), Features.end(), "+soft-float-abi");
3840     if (it != Features.end())
3841       Features.erase(it);
3842     return true;
3843   }
3844 
3845   virtual bool hasFeature(StringRef Feature) const {
3846     return llvm::StringSwitch<bool>(Feature)
3847         .Case("arm", true)
3848         .Case("softfloat", SoftFloat)
3849         .Case("thumb", IsThumb)
3850         .Case("neon", (FPU & NeonFPU) && !SoftFloat)
3851         .Case("hwdiv", HWDiv & HWDivThumb)
3852         .Case("hwdiv-arm", HWDiv & HWDivARM)
3853         .Default(false);
3854   }
3855   // FIXME: Should we actually have some table instead of these switches?
3856   static const char *getCPUDefineSuffix(StringRef Name) {
3857     return llvm::StringSwitch<const char*>(Name)
3858       .Cases("arm8", "arm810", "4")
3859       .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4")
3860       .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
3861       .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
3862       .Case("ep9312", "4T")
3863       .Cases("arm10tdmi", "arm1020t", "5T")
3864       .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
3865       .Case("arm926ej-s", "5TEJ")
3866       .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
3867       .Cases("xscale", "iwmmxt", "5TE")
3868       .Case("arm1136j-s", "6J")
3869       .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
3870       .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
3871       .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
3872       .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
3873       .Cases("cortex-a9", "cortex-a12", "cortex-a15", "7A")
3874       .Cases("cortex-r4", "cortex-r5", "7R")
3875       .Case("cortex-a9-mp", "7F")
3876       .Case("swift", "7S")
3877       .Cases("cortex-m3", "cortex-m4", "7M")
3878       .Case("cortex-m0", "6M")
3879       .Cases("cortex-a53", "cortex-a57", "8A")
3880       .Default(0);
3881   }
3882   static const char *getCPUProfile(StringRef Name) {
3883     return llvm::StringSwitch<const char*>(Name)
3884       .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A")
3885       .Cases("cortex-a9", "cortex-a12", "cortex-a15", "A")
3886       .Cases("cortex-a53", "cortex-a57", "A")
3887       .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M")
3888       .Cases("cortex-r4", "cortex-r5", "R")
3889       .Default("");
3890   }
3891   virtual bool setCPU(const std::string &Name) {
3892     if (!getCPUDefineSuffix(Name))
3893       return false;
3894 
3895     CPU = Name;
3896     return true;
3897   }
3898   virtual bool setFPMath(StringRef Name);
3899   virtual void getTargetDefines(const LangOptions &Opts,
3900                                 MacroBuilder &Builder) const {
3901     // Target identification.
3902     Builder.defineMacro("__arm");
3903     Builder.defineMacro("__arm__");
3904 
3905     // Target properties.
3906     Builder.defineMacro("__ARMEL__");
3907     Builder.defineMacro("__LITTLE_ENDIAN__");
3908     Builder.defineMacro("__REGISTER_PREFIX__", "");
3909 
3910     StringRef CPUArch = getCPUDefineSuffix(CPU);
3911     unsigned int CPUArchVer;
3912     if(CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) {
3913       llvm_unreachable("Invalid char for architecture version number");
3914     }
3915     Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
3916     Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
3917     StringRef CPUProfile = getCPUProfile(CPU);
3918     if (!CPUProfile.empty())
3919       Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile);
3920 
3921     // Subtarget options.
3922 
3923     // FIXME: It's more complicated than this and we don't really support
3924     // interworking.
3925     if (5 <= CPUArchVer && CPUArchVer <= 7)
3926       Builder.defineMacro("__THUMB_INTERWORK__");
3927 
3928     if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
3929       // M-class CPUs on Darwin follow AAPCS, but not EABI.
3930       if (!(getTriple().isOSDarwin() && CPUProfile == "M"))
3931         Builder.defineMacro("__ARM_EABI__");
3932       Builder.defineMacro("__ARM_PCS", "1");
3933 
3934       if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
3935         Builder.defineMacro("__ARM_PCS_VFP", "1");
3936     }
3937 
3938     if (SoftFloat)
3939       Builder.defineMacro("__SOFTFP__");
3940 
3941     if (CPU == "xscale")
3942       Builder.defineMacro("__XSCALE__");
3943 
3944     if (IsThumb) {
3945       Builder.defineMacro("__THUMBEL__");
3946       Builder.defineMacro("__thumb__");
3947       if (CPUArch == "6T2" || CPUArchVer == 7)
3948         Builder.defineMacro("__thumb2__");
3949     }
3950     if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
3951       Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
3952 
3953     // Note, this is always on in gcc, even though it doesn't make sense.
3954     Builder.defineMacro("__APCS_32__");
3955 
3956     if (FPUModeIsVFP((FPUMode) FPU)) {
3957       Builder.defineMacro("__VFP_FP__");
3958       if (FPU & VFP2FPU)
3959         Builder.defineMacro("__ARM_VFPV2__");
3960       if (FPU & VFP3FPU)
3961         Builder.defineMacro("__ARM_VFPV3__");
3962       if (FPU & VFP4FPU)
3963         Builder.defineMacro("__ARM_VFPV4__");
3964     }
3965 
3966     // This only gets set when Neon instructions are actually available, unlike
3967     // the VFP define, hence the soft float and arch check. This is subtly
3968     // different from gcc, we follow the intent which was that it should be set
3969     // when Neon instructions are actually available.
3970     if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7)
3971       Builder.defineMacro("__ARM_NEON__");
3972 
3973     if (CPUArchVer == 8)
3974       Builder.defineMacro("__ARM_FEATURE_CRC32");
3975 
3976     if (CPUArchVer >= 6 && CPUArch != "6M") {
3977       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3978       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3979       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3980       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3981     }
3982   }
3983   virtual void getTargetBuiltins(const Builtin::Info *&Records,
3984                                  unsigned &NumRecords) const {
3985     Records = BuiltinInfo;
3986     NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
3987   }
3988   virtual bool isCLZForZeroUndef() const { return false; }
3989   virtual BuiltinVaListKind getBuiltinVaListKind() const {
3990     return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
3991   }
3992   virtual void getGCCRegNames(const char * const *&Names,
3993                               unsigned &NumNames) const;
3994   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
3995                                 unsigned &NumAliases) const;
3996   virtual bool validateAsmConstraint(const char *&Name,
3997                                      TargetInfo::ConstraintInfo &Info) const {
3998     switch (*Name) {
3999     default: break;
4000     case 'l': // r0-r7
4001     case 'h': // r8-r15
4002     case 'w': // VFP Floating point register single precision
4003     case 'P': // VFP Floating point register double precision
4004       Info.setAllowsRegister();
4005       return true;
4006     case 'Q': // A memory address that is a single base register.
4007       Info.setAllowsMemory();
4008       return true;
4009     case 'U': // a memory reference...
4010       switch (Name[1]) {
4011       case 'q': // ...ARMV4 ldrsb
4012       case 'v': // ...VFP load/store (reg+constant offset)
4013       case 'y': // ...iWMMXt load/store
4014       case 't': // address valid for load/store opaque types wider
4015                 // than 128-bits
4016       case 'n': // valid address for Neon doubleword vector load/store
4017       case 'm': // valid address for Neon element and structure load/store
4018       case 's': // valid address for non-offset loads/stores of quad-word
4019                 // values in four ARM registers
4020         Info.setAllowsMemory();
4021         Name++;
4022         return true;
4023       }
4024     }
4025     return false;
4026   }
4027   virtual std::string convertConstraint(const char *&Constraint) const {
4028     std::string R;
4029     switch (*Constraint) {
4030     case 'U':   // Two-character constraint; add "^" hint for later parsing.
4031       R = std::string("^") + std::string(Constraint, 2);
4032       Constraint++;
4033       break;
4034     case 'p': // 'p' should be translated to 'r' by default.
4035       R = std::string("r");
4036       break;
4037     default:
4038       return std::string(1, *Constraint);
4039     }
4040     return R;
4041   }
4042   virtual bool validateConstraintModifier(StringRef Constraint,
4043                                           const char Modifier,
4044                                           unsigned Size) const {
4045     bool isOutput = (Constraint[0] == '=');
4046     bool isInOut = (Constraint[0] == '+');
4047 
4048     // Strip off constraint modifiers.
4049     while (Constraint[0] == '=' ||
4050            Constraint[0] == '+' ||
4051            Constraint[0] == '&')
4052       Constraint = Constraint.substr(1);
4053 
4054     switch (Constraint[0]) {
4055     default: break;
4056     case 'r': {
4057       switch (Modifier) {
4058       default:
4059         return (isInOut || isOutput || Size <= 32);
4060       case 'q':
4061         // A register of size 32 cannot fit a vector type.
4062         return false;
4063       }
4064     }
4065     }
4066 
4067     return true;
4068   }
4069   virtual const char *getClobbers() const {
4070     // FIXME: Is this really right?
4071     return "";
4072   }
4073 
4074   virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const {
4075     return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
4076   }
4077 
4078   virtual int getEHDataRegisterNumber(unsigned RegNo) const {
4079     if (RegNo == 0) return 0;
4080     if (RegNo == 1) return 1;
4081     return -1;
4082   }
4083 };
4084 
4085 bool ARMTargetInfo::setFPMath(StringRef Name) {
4086   if (Name == "neon") {
4087     FPMath = FP_Neon;
4088     return true;
4089   } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
4090              Name == "vfp4") {
4091     FPMath = FP_VFP;
4092     return true;
4093   }
4094   return false;
4095 }
4096 
4097 const char * const ARMTargetInfo::GCCRegNames[] = {
4098   // Integer registers
4099   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4100   "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
4101 
4102   // Float registers
4103   "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
4104   "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
4105   "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
4106   "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4107 
4108   // Double registers
4109   "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
4110   "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
4111   "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
4112   "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4113 
4114   // Quad registers
4115   "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
4116   "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
4117 };
4118 
4119 void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
4120                                    unsigned &NumNames) const {
4121   Names = GCCRegNames;
4122   NumNames = llvm::array_lengthof(GCCRegNames);
4123 }
4124 
4125 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
4126   { { "a1" }, "r0" },
4127   { { "a2" }, "r1" },
4128   { { "a3" }, "r2" },
4129   { { "a4" }, "r3" },
4130   { { "v1" }, "r4" },
4131   { { "v2" }, "r5" },
4132   { { "v3" }, "r6" },
4133   { { "v4" }, "r7" },
4134   { { "v5" }, "r8" },
4135   { { "v6", "rfp" }, "r9" },
4136   { { "sl" }, "r10" },
4137   { { "fp" }, "r11" },
4138   { { "ip" }, "r12" },
4139   { { "r13" }, "sp" },
4140   { { "r14" }, "lr" },
4141   { { "r15" }, "pc" },
4142   // The S, D and Q registers overlap, but aren't really aliases; we
4143   // don't want to substitute one of these for a different-sized one.
4144 };
4145 
4146 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4147                                        unsigned &NumAliases) const {
4148   Aliases = GCCRegAliases;
4149   NumAliases = llvm::array_lengthof(GCCRegAliases);
4150 }
4151 
4152 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
4153 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4154 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4155                                               ALL_LANGUAGES },
4156 #include "clang/Basic/BuiltinsARM.def"
4157 };
4158 } // end anonymous namespace.
4159 
4160 namespace {
4161 class DarwinARMTargetInfo :
4162   public DarwinTargetInfo<ARMTargetInfo> {
4163 protected:
4164   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4165                             MacroBuilder &Builder) const {
4166     getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4167   }
4168 
4169 public:
4170   DarwinARMTargetInfo(const llvm::Triple &Triple)
4171       : DarwinTargetInfo<ARMTargetInfo>(Triple) {
4172     HasAlignMac68kSupport = true;
4173     // iOS always has 64-bit atomic instructions.
4174     // FIXME: This should be based off of the target features in ARMTargetInfo.
4175     MaxAtomicInlineWidth = 64;
4176 
4177     // Darwin on iOS uses a variant of the ARM C++ ABI.
4178     TheCXXABI.set(TargetCXXABI::iOS);
4179   }
4180 };
4181 } // end anonymous namespace.
4182 
4183 
4184 namespace {
4185 // Hexagon abstract base class
4186 class HexagonTargetInfo : public TargetInfo {
4187   static const Builtin::Info BuiltinInfo[];
4188   static const char * const GCCRegNames[];
4189   static const TargetInfo::GCCRegAlias GCCRegAliases[];
4190   std::string CPU;
4191 public:
4192   HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4193     BigEndian = false;
4194     DescriptionString = ("e-p:32:32:32-"
4195                          "i64:64:64-i32:32:32-i16:16:16-i1:32:32-"
4196                          "f64:64:64-f32:32:32-a0:0-n32");
4197 
4198     // {} in inline assembly are packet specifiers, not assembly variant
4199     // specifiers.
4200     NoAsmVariants = true;
4201   }
4202 
4203   virtual void getTargetBuiltins(const Builtin::Info *&Records,
4204                                  unsigned &NumRecords) const {
4205     Records = BuiltinInfo;
4206     NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
4207   }
4208 
4209   virtual bool validateAsmConstraint(const char *&Name,
4210                                      TargetInfo::ConstraintInfo &Info) const {
4211     return true;
4212   }
4213 
4214   virtual void getTargetDefines(const LangOptions &Opts,
4215                                 MacroBuilder &Builder) const;
4216 
4217   virtual bool hasFeature(StringRef Feature) const {
4218     return Feature == "hexagon";
4219   }
4220 
4221   virtual BuiltinVaListKind getBuiltinVaListKind() const {
4222     return TargetInfo::CharPtrBuiltinVaList;
4223   }
4224   virtual void getGCCRegNames(const char * const *&Names,
4225                               unsigned &NumNames) const;
4226   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4227                                 unsigned &NumAliases) const;
4228   virtual const char *getClobbers() const {
4229     return "";
4230   }
4231 
4232   static const char *getHexagonCPUSuffix(StringRef Name) {
4233     return llvm::StringSwitch<const char*>(Name)
4234       .Case("hexagonv4", "4")
4235       .Case("hexagonv5", "5")
4236       .Default(0);
4237   }
4238 
4239   virtual bool setCPU(const std::string &Name) {
4240     if (!getHexagonCPUSuffix(Name))
4241       return false;
4242 
4243     CPU = Name;
4244     return true;
4245   }
4246 };
4247 
4248 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
4249                                 MacroBuilder &Builder) const {
4250   Builder.defineMacro("qdsp6");
4251   Builder.defineMacro("__qdsp6", "1");
4252   Builder.defineMacro("__qdsp6__", "1");
4253 
4254   Builder.defineMacro("hexagon");
4255   Builder.defineMacro("__hexagon", "1");
4256   Builder.defineMacro("__hexagon__", "1");
4257 
4258   if(CPU == "hexagonv1") {
4259     Builder.defineMacro("__HEXAGON_V1__");
4260     Builder.defineMacro("__HEXAGON_ARCH__", "1");
4261     if(Opts.HexagonQdsp6Compat) {
4262       Builder.defineMacro("__QDSP6_V1__");
4263       Builder.defineMacro("__QDSP6_ARCH__", "1");
4264     }
4265   }
4266   else if(CPU == "hexagonv2") {
4267     Builder.defineMacro("__HEXAGON_V2__");
4268     Builder.defineMacro("__HEXAGON_ARCH__", "2");
4269     if(Opts.HexagonQdsp6Compat) {
4270       Builder.defineMacro("__QDSP6_V2__");
4271       Builder.defineMacro("__QDSP6_ARCH__", "2");
4272     }
4273   }
4274   else if(CPU == "hexagonv3") {
4275     Builder.defineMacro("__HEXAGON_V3__");
4276     Builder.defineMacro("__HEXAGON_ARCH__", "3");
4277     if(Opts.HexagonQdsp6Compat) {
4278       Builder.defineMacro("__QDSP6_V3__");
4279       Builder.defineMacro("__QDSP6_ARCH__", "3");
4280     }
4281   }
4282   else if(CPU == "hexagonv4") {
4283     Builder.defineMacro("__HEXAGON_V4__");
4284     Builder.defineMacro("__HEXAGON_ARCH__", "4");
4285     if(Opts.HexagonQdsp6Compat) {
4286       Builder.defineMacro("__QDSP6_V4__");
4287       Builder.defineMacro("__QDSP6_ARCH__", "4");
4288     }
4289   }
4290   else if(CPU == "hexagonv5") {
4291     Builder.defineMacro("__HEXAGON_V5__");
4292     Builder.defineMacro("__HEXAGON_ARCH__", "5");
4293     if(Opts.HexagonQdsp6Compat) {
4294       Builder.defineMacro("__QDSP6_V5__");
4295       Builder.defineMacro("__QDSP6_ARCH__", "5");
4296     }
4297   }
4298 }
4299 
4300 const char * const HexagonTargetInfo::GCCRegNames[] = {
4301   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4302   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4303   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4304   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
4305   "p0", "p1", "p2", "p3",
4306   "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
4307 };
4308 
4309 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
4310                                    unsigned &NumNames) const {
4311   Names = GCCRegNames;
4312   NumNames = llvm::array_lengthof(GCCRegNames);
4313 }
4314 
4315 
4316 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
4317   { { "sp" }, "r29" },
4318   { { "fp" }, "r30" },
4319   { { "lr" }, "r31" },
4320  };
4321 
4322 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4323                                      unsigned &NumAliases) const {
4324   Aliases = GCCRegAliases;
4325   NumAliases = llvm::array_lengthof(GCCRegAliases);
4326 }
4327 
4328 
4329 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
4330 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4331 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4332                                               ALL_LANGUAGES },
4333 #include "clang/Basic/BuiltinsHexagon.def"
4334 };
4335 }
4336 
4337 
4338 namespace {
4339 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
4340 class SparcTargetInfo : public TargetInfo {
4341   static const TargetInfo::GCCRegAlias GCCRegAliases[];
4342   static const char * const GCCRegNames[];
4343   bool SoftFloat;
4344 public:
4345   SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {}
4346 
4347   virtual bool handleTargetFeatures(std::vector<std::string> &Features,
4348                                     DiagnosticsEngine &Diags) {
4349     SoftFloat = false;
4350     for (unsigned i = 0, e = Features.size(); i != e; ++i)
4351       if (Features[i] == "+soft-float")
4352         SoftFloat = true;
4353     return true;
4354   }
4355   virtual void getTargetDefines(const LangOptions &Opts,
4356                                 MacroBuilder &Builder) const {
4357     DefineStd(Builder, "sparc", Opts);
4358     Builder.defineMacro("__REGISTER_PREFIX__", "");
4359 
4360     if (SoftFloat)
4361       Builder.defineMacro("SOFT_FLOAT", "1");
4362   }
4363 
4364   virtual bool hasFeature(StringRef Feature) const {
4365     return llvm::StringSwitch<bool>(Feature)
4366              .Case("softfloat", SoftFloat)
4367              .Case("sparc", true)
4368              .Default(false);
4369   }
4370 
4371   virtual void getTargetBuiltins(const Builtin::Info *&Records,
4372                                  unsigned &NumRecords) const {
4373     // FIXME: Implement!
4374   }
4375   virtual BuiltinVaListKind getBuiltinVaListKind() const {
4376     return TargetInfo::VoidPtrBuiltinVaList;
4377   }
4378   virtual void getGCCRegNames(const char * const *&Names,
4379                               unsigned &NumNames) const;
4380   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4381                                 unsigned &NumAliases) const;
4382   virtual bool validateAsmConstraint(const char *&Name,
4383                                      TargetInfo::ConstraintInfo &info) const {
4384     // FIXME: Implement!
4385     return false;
4386   }
4387   virtual const char *getClobbers() const {
4388     // FIXME: Implement!
4389     return "";
4390   }
4391 };
4392 
4393 const char * const SparcTargetInfo::GCCRegNames[] = {
4394   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4395   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4396   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4397   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
4398 };
4399 
4400 void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
4401                                      unsigned &NumNames) const {
4402   Names = GCCRegNames;
4403   NumNames = llvm::array_lengthof(GCCRegNames);
4404 }
4405 
4406 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
4407   { { "g0" }, "r0" },
4408   { { "g1" }, "r1" },
4409   { { "g2" }, "r2" },
4410   { { "g3" }, "r3" },
4411   { { "g4" }, "r4" },
4412   { { "g5" }, "r5" },
4413   { { "g6" }, "r6" },
4414   { { "g7" }, "r7" },
4415   { { "o0" }, "r8" },
4416   { { "o1" }, "r9" },
4417   { { "o2" }, "r10" },
4418   { { "o3" }, "r11" },
4419   { { "o4" }, "r12" },
4420   { { "o5" }, "r13" },
4421   { { "o6", "sp" }, "r14" },
4422   { { "o7" }, "r15" },
4423   { { "l0" }, "r16" },
4424   { { "l1" }, "r17" },
4425   { { "l2" }, "r18" },
4426   { { "l3" }, "r19" },
4427   { { "l4" }, "r20" },
4428   { { "l5" }, "r21" },
4429   { { "l6" }, "r22" },
4430   { { "l7" }, "r23" },
4431   { { "i0" }, "r24" },
4432   { { "i1" }, "r25" },
4433   { { "i2" }, "r26" },
4434   { { "i3" }, "r27" },
4435   { { "i4" }, "r28" },
4436   { { "i5" }, "r29" },
4437   { { "i6", "fp" }, "r30" },
4438   { { "i7" }, "r31" },
4439 };
4440 
4441 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4442                                        unsigned &NumAliases) const {
4443   Aliases = GCCRegAliases;
4444   NumAliases = llvm::array_lengthof(GCCRegAliases);
4445 }
4446 
4447 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
4448 class SparcV8TargetInfo : public SparcTargetInfo {
4449 public:
4450   SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
4451     // FIXME: Support Sparc quad-precision long double?
4452     DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4453                         "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
4454   }
4455 
4456   virtual void getTargetDefines(const LangOptions &Opts,
4457                                 MacroBuilder &Builder) const {
4458     SparcTargetInfo::getTargetDefines(Opts, Builder);
4459     Builder.defineMacro("__sparcv8");
4460   }
4461 };
4462 
4463 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
4464 class SparcV9TargetInfo : public SparcTargetInfo {
4465 public:
4466   SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
4467     // FIXME: Support Sparc quad-precision long double?
4468     DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-"
4469                         "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32:64-S128";
4470     // This is an LP64 platform.
4471     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4472 
4473     // OpenBSD uses long long for int64_t and intmax_t.
4474     if (getTriple().getOS() == llvm::Triple::OpenBSD) {
4475       IntMaxType = SignedLongLong;
4476       UIntMaxType = UnsignedLongLong;
4477     } else {
4478       IntMaxType = SignedLong;
4479       UIntMaxType = UnsignedLong;
4480     }
4481     Int64Type = IntMaxType;
4482   }
4483 
4484   virtual void getTargetDefines(const LangOptions &Opts,
4485                                 MacroBuilder &Builder) const {
4486     SparcTargetInfo::getTargetDefines(Opts, Builder);
4487     Builder.defineMacro("__sparcv9");
4488     Builder.defineMacro("__arch64__");
4489     // Solaris and its derivative AuroraUX don't need these variants, but the
4490     // BSDs do.
4491     if (getTriple().getOS() != llvm::Triple::Solaris &&
4492         getTriple().getOS() != llvm::Triple::AuroraUX) {
4493       Builder.defineMacro("__sparc64__");
4494       Builder.defineMacro("__sparc_v9__");
4495       Builder.defineMacro("__sparcv9__");
4496     }
4497   }
4498 };
4499 
4500 } // end anonymous namespace.
4501 
4502 namespace {
4503 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> {
4504 public:
4505   AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple)
4506       : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) {
4507     SizeType = UnsignedInt;
4508     PtrDiffType = SignedInt;
4509   }
4510 };
4511 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
4512 public:
4513   SolarisSparcV8TargetInfo(const llvm::Triple &Triple)
4514       : SolarisTargetInfo<SparcV8TargetInfo>(Triple) {
4515     SizeType = UnsignedInt;
4516     PtrDiffType = SignedInt;
4517   }
4518 };
4519 } // end anonymous namespace.
4520 
4521 namespace {
4522   class SystemZTargetInfo : public TargetInfo {
4523     static const char *const GCCRegNames[];
4524 
4525   public:
4526     SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4527       TLSSupported = true;
4528       IntWidth = IntAlign = 32;
4529       LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
4530       PointerWidth = PointerAlign = 64;
4531       LongDoubleWidth = 128;
4532       LongDoubleAlign = 64;
4533       LongDoubleFormat = &llvm::APFloat::IEEEquad;
4534       MinGlobalAlign = 16;
4535       DescriptionString = "E-p:64:64:64-i1:8:16-i8:8:16-i16:16-i32:32-i64:64"
4536        "-f32:32-f64:64-f128:64-a0:8:16-n32:64";
4537       MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4538     }
4539     virtual void getTargetDefines(const LangOptions &Opts,
4540                                   MacroBuilder &Builder) const {
4541       Builder.defineMacro("__s390__");
4542       Builder.defineMacro("__s390x__");
4543       Builder.defineMacro("__zarch__");
4544       Builder.defineMacro("__LONG_DOUBLE_128__");
4545     }
4546     virtual void getTargetBuiltins(const Builtin::Info *&Records,
4547                                    unsigned &NumRecords) const {
4548       // FIXME: Implement.
4549       Records = 0;
4550       NumRecords = 0;
4551     }
4552 
4553     virtual void getGCCRegNames(const char *const *&Names,
4554                                 unsigned &NumNames) const;
4555     virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4556                                   unsigned &NumAliases) const {
4557       // No aliases.
4558       Aliases = 0;
4559       NumAliases = 0;
4560     }
4561     virtual bool validateAsmConstraint(const char *&Name,
4562                                        TargetInfo::ConstraintInfo &info) const;
4563     virtual const char *getClobbers() const {
4564       // FIXME: Is this really right?
4565       return "";
4566     }
4567     virtual BuiltinVaListKind getBuiltinVaListKind() const {
4568       return TargetInfo::SystemZBuiltinVaList;
4569     }
4570     virtual bool setCPU(const std::string &Name) {
4571       bool CPUKnown = llvm::StringSwitch<bool>(Name)
4572         .Case("z10", true)
4573         .Case("z196", true)
4574         .Case("zEC12", true)
4575         .Default(false);
4576 
4577       // No need to store the CPU yet.  There aren't any CPU-specific
4578       // macros to define.
4579       return CPUKnown;
4580     }
4581   };
4582 
4583   const char *const SystemZTargetInfo::GCCRegNames[] = {
4584     "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
4585     "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
4586     "f0",  "f2",  "f4",  "f6",  "f1",  "f3",  "f5",  "f7",
4587     "f8",  "f10", "f12", "f14", "f9",  "f11", "f13", "f15"
4588   };
4589 
4590   void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
4591                                          unsigned &NumNames) const {
4592     Names = GCCRegNames;
4593     NumNames = llvm::array_lengthof(GCCRegNames);
4594   }
4595 
4596   bool SystemZTargetInfo::
4597   validateAsmConstraint(const char *&Name,
4598                         TargetInfo::ConstraintInfo &Info) const {
4599     switch (*Name) {
4600     default:
4601       return false;
4602 
4603     case 'a': // Address register
4604     case 'd': // Data register (equivalent to 'r')
4605     case 'f': // Floating-point register
4606       Info.setAllowsRegister();
4607       return true;
4608 
4609     case 'I': // Unsigned 8-bit constant
4610     case 'J': // Unsigned 12-bit constant
4611     case 'K': // Signed 16-bit constant
4612     case 'L': // Signed 20-bit displacement (on all targets we support)
4613     case 'M': // 0x7fffffff
4614       return true;
4615 
4616     case 'Q': // Memory with base and unsigned 12-bit displacement
4617     case 'R': // Likewise, plus an index
4618     case 'S': // Memory with base and signed 20-bit displacement
4619     case 'T': // Likewise, plus an index
4620       Info.setAllowsMemory();
4621       return true;
4622     }
4623   }
4624 }
4625 
4626 namespace {
4627   class MSP430TargetInfo : public TargetInfo {
4628     static const char * const GCCRegNames[];
4629   public:
4630     MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4631       BigEndian = false;
4632       TLSSupported = false;
4633       IntWidth = 16; IntAlign = 16;
4634       LongWidth = 32; LongLongWidth = 64;
4635       LongAlign = LongLongAlign = 16;
4636       PointerWidth = 16; PointerAlign = 16;
4637       SuitableAlign = 16;
4638       SizeType = UnsignedInt;
4639       IntMaxType = SignedLongLong;
4640       UIntMaxType = UnsignedLongLong;
4641       IntPtrType = SignedInt;
4642       PtrDiffType = SignedInt;
4643       SigAtomicType = SignedLong;
4644       DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16";
4645    }
4646     virtual void getTargetDefines(const LangOptions &Opts,
4647                                   MacroBuilder &Builder) const {
4648       Builder.defineMacro("MSP430");
4649       Builder.defineMacro("__MSP430__");
4650       // FIXME: defines for different 'flavours' of MCU
4651     }
4652     virtual void getTargetBuiltins(const Builtin::Info *&Records,
4653                                    unsigned &NumRecords) const {
4654      // FIXME: Implement.
4655       Records = 0;
4656       NumRecords = 0;
4657     }
4658     virtual bool hasFeature(StringRef Feature) const {
4659       return Feature == "msp430";
4660     }
4661     virtual void getGCCRegNames(const char * const *&Names,
4662                                 unsigned &NumNames) const;
4663     virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4664                                   unsigned &NumAliases) const {
4665       // No aliases.
4666       Aliases = 0;
4667       NumAliases = 0;
4668     }
4669     virtual bool validateAsmConstraint(const char *&Name,
4670                                        TargetInfo::ConstraintInfo &info) const {
4671       // No target constraints for now.
4672       return false;
4673     }
4674     virtual const char *getClobbers() const {
4675       // FIXME: Is this really right?
4676       return "";
4677     }
4678     virtual BuiltinVaListKind getBuiltinVaListKind() const {
4679       // FIXME: implement
4680       return TargetInfo::CharPtrBuiltinVaList;
4681    }
4682   };
4683 
4684   const char * const MSP430TargetInfo::GCCRegNames[] = {
4685     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4686     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4687   };
4688 
4689   void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
4690                                         unsigned &NumNames) const {
4691     Names = GCCRegNames;
4692     NumNames = llvm::array_lengthof(GCCRegNames);
4693   }
4694 }
4695 
4696 namespace {
4697 
4698   // LLVM and Clang cannot be used directly to output native binaries for
4699   // target, but is used to compile C code to llvm bitcode with correct
4700   // type and alignment information.
4701   //
4702   // TCE uses the llvm bitcode as input and uses it for generating customized
4703   // target processor and program binary. TCE co-design environment is
4704   // publicly available in http://tce.cs.tut.fi
4705 
4706   static const unsigned TCEOpenCLAddrSpaceMap[] = {
4707       3, // opencl_global
4708       4, // opencl_local
4709       5, // opencl_constant
4710       0, // cuda_device
4711       0, // cuda_constant
4712       0  // cuda_shared
4713   };
4714 
4715   class TCETargetInfo : public TargetInfo{
4716   public:
4717     TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4718       TLSSupported = false;
4719       IntWidth = 32;
4720       LongWidth = LongLongWidth = 32;
4721       PointerWidth = 32;
4722       IntAlign = 32;
4723       LongAlign = LongLongAlign = 32;
4724       PointerAlign = 32;
4725       SuitableAlign = 32;
4726       SizeType = UnsignedInt;
4727       IntMaxType = SignedLong;
4728       UIntMaxType = UnsignedLong;
4729       IntPtrType = SignedInt;
4730       PtrDiffType = SignedInt;
4731       FloatWidth = 32;
4732       FloatAlign = 32;
4733       DoubleWidth = 32;
4734       DoubleAlign = 32;
4735       LongDoubleWidth = 32;
4736       LongDoubleAlign = 32;
4737       FloatFormat = &llvm::APFloat::IEEEsingle;
4738       DoubleFormat = &llvm::APFloat::IEEEsingle;
4739       LongDoubleFormat = &llvm::APFloat::IEEEsingle;
4740       DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-"
4741                           "i16:16:32-i32:32:32-i64:32:32-"
4742                           "f32:32:32-f64:32:32-v64:32:32-"
4743                           "v128:32:32-a0:0:32-n32";
4744       AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
4745       UseAddrSpaceMapMangling = true;
4746     }
4747 
4748     virtual void getTargetDefines(const LangOptions &Opts,
4749                                   MacroBuilder &Builder) const {
4750       DefineStd(Builder, "tce", Opts);
4751       Builder.defineMacro("__TCE__");
4752       Builder.defineMacro("__TCE_V1__");
4753     }
4754     virtual bool hasFeature(StringRef Feature) const {
4755       return Feature == "tce";
4756     }
4757 
4758     virtual void getTargetBuiltins(const Builtin::Info *&Records,
4759                                    unsigned &NumRecords) const {}
4760     virtual const char *getClobbers() const {
4761       return "";
4762     }
4763     virtual BuiltinVaListKind getBuiltinVaListKind() const {
4764       return TargetInfo::VoidPtrBuiltinVaList;
4765     }
4766     virtual void getGCCRegNames(const char * const *&Names,
4767                                 unsigned &NumNames) const {}
4768     virtual bool validateAsmConstraint(const char *&Name,
4769                                        TargetInfo::ConstraintInfo &info) const {
4770       return true;
4771     }
4772     virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4773                                   unsigned &NumAliases) const {}
4774   };
4775 }
4776 
4777 namespace {
4778 class MipsTargetInfoBase : public TargetInfo {
4779   static const Builtin::Info BuiltinInfo[];
4780   std::string CPU;
4781   bool IsMips16;
4782   bool IsMicromips;
4783   bool IsNan2008;
4784   bool IsSingleFloat;
4785   enum MipsFloatABI {
4786     HardFloat, SoftFloat
4787   } FloatABI;
4788   enum DspRevEnum {
4789     NoDSP, DSP1, DSP2
4790   } DspRev;
4791   bool HasMSA;
4792   bool HasFP64;
4793 
4794 protected:
4795   std::string ABI;
4796 
4797 public:
4798   MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
4799                      const std::string &CPUStr)
4800       : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
4801         IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
4802         DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {}
4803 
4804   virtual const char *getABI() const { return ABI.c_str(); }
4805   virtual bool setABI(const std::string &Name) = 0;
4806   virtual bool setCPU(const std::string &Name) {
4807     CPU = Name;
4808     return true;
4809   }
4810   void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
4811     Features[ABI] = true;
4812     Features[CPU] = true;
4813   }
4814 
4815   virtual void getTargetDefines(const LangOptions &Opts,
4816                                 MacroBuilder &Builder) const {
4817     DefineStd(Builder, "mips", Opts);
4818     Builder.defineMacro("_mips");
4819     Builder.defineMacro("__REGISTER_PREFIX__", "");
4820 
4821     switch (FloatABI) {
4822     case HardFloat:
4823       Builder.defineMacro("__mips_hard_float", Twine(1));
4824       break;
4825     case SoftFloat:
4826       Builder.defineMacro("__mips_soft_float", Twine(1));
4827       break;
4828     }
4829 
4830     if (IsSingleFloat)
4831       Builder.defineMacro("__mips_single_float", Twine(1));
4832 
4833     Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
4834     Builder.defineMacro("_MIPS_FPSET",
4835                         Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
4836 
4837     if (IsMips16)
4838       Builder.defineMacro("__mips16", Twine(1));
4839 
4840     if (IsMicromips)
4841       Builder.defineMacro("__mips_micromips", Twine(1));
4842 
4843     if (IsNan2008)
4844       Builder.defineMacro("__mips_nan2008", Twine(1));
4845 
4846     switch (DspRev) {
4847     default:
4848       break;
4849     case DSP1:
4850       Builder.defineMacro("__mips_dsp_rev", Twine(1));
4851       Builder.defineMacro("__mips_dsp", Twine(1));
4852       break;
4853     case DSP2:
4854       Builder.defineMacro("__mips_dsp_rev", Twine(2));
4855       Builder.defineMacro("__mips_dspr2", Twine(1));
4856       Builder.defineMacro("__mips_dsp", Twine(1));
4857       break;
4858     }
4859 
4860     if (HasMSA)
4861       Builder.defineMacro("__mips_msa", Twine(1));
4862 
4863     Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
4864     Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
4865     Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
4866 
4867     Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
4868     Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
4869   }
4870 
4871   virtual void getTargetBuiltins(const Builtin::Info *&Records,
4872                                  unsigned &NumRecords) const {
4873     Records = BuiltinInfo;
4874     NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
4875   }
4876   virtual bool hasFeature(StringRef Feature) const {
4877     return Feature == "mips";
4878   }
4879   virtual BuiltinVaListKind getBuiltinVaListKind() const {
4880     return TargetInfo::VoidPtrBuiltinVaList;
4881   }
4882   virtual void getGCCRegNames(const char * const *&Names,
4883                               unsigned &NumNames) const {
4884     static const char * const GCCRegNames[] = {
4885       // CPU register names
4886       // Must match second column of GCCRegAliases
4887       "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
4888       "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
4889       "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
4890       "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
4891       // Floating point register names
4892       "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
4893       "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
4894       "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
4895       "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
4896       // Hi/lo and condition register names
4897       "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
4898       "$fcc5","$fcc6","$fcc7"
4899     };
4900     Names = GCCRegNames;
4901     NumNames = llvm::array_lengthof(GCCRegNames);
4902   }
4903   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4904                                 unsigned &NumAliases) const = 0;
4905   virtual bool validateAsmConstraint(const char *&Name,
4906                                      TargetInfo::ConstraintInfo &Info) const {
4907     switch (*Name) {
4908     default:
4909       return false;
4910 
4911     case 'r': // CPU registers.
4912     case 'd': // Equivalent to "r" unless generating MIPS16 code.
4913     case 'y': // Equivalent to "r", backwards compatibility only.
4914     case 'f': // floating-point registers.
4915     case 'c': // $25 for indirect jumps
4916     case 'l': // lo register
4917     case 'x': // hilo register pair
4918       Info.setAllowsRegister();
4919       return true;
4920     case 'R': // An address that can be used in a non-macro load or store
4921       Info.setAllowsMemory();
4922       return true;
4923     }
4924   }
4925 
4926   virtual const char *getClobbers() const {
4927     // FIXME: Implement!
4928     return "";
4929   }
4930 
4931   virtual bool handleTargetFeatures(std::vector<std::string> &Features,
4932                                     DiagnosticsEngine &Diags) {
4933     IsMips16 = false;
4934     IsMicromips = false;
4935     IsNan2008 = false;
4936     IsSingleFloat = false;
4937     FloatABI = HardFloat;
4938     DspRev = NoDSP;
4939     HasFP64 = ABI == "n32" || ABI == "n64" || ABI == "64";
4940 
4941     for (std::vector<std::string>::iterator it = Features.begin(),
4942          ie = Features.end(); it != ie; ++it) {
4943       if (*it == "+single-float")
4944         IsSingleFloat = true;
4945       else if (*it == "+soft-float")
4946         FloatABI = SoftFloat;
4947       else if (*it == "+mips16")
4948         IsMips16 = true;
4949       else if (*it == "+micromips")
4950         IsMicromips = true;
4951       else if (*it == "+dsp")
4952         DspRev = std::max(DspRev, DSP1);
4953       else if (*it == "+dspr2")
4954         DspRev = std::max(DspRev, DSP2);
4955       else if (*it == "+msa")
4956         HasMSA = true;
4957       else if (*it == "+fp64")
4958         HasFP64 = true;
4959       else if (*it == "-fp64")
4960         HasFP64 = false;
4961       else if (*it == "+nan2008")
4962         IsNan2008 = true;
4963     }
4964 
4965     // Remove front-end specific options.
4966     std::vector<std::string>::iterator it =
4967       std::find(Features.begin(), Features.end(), "+soft-float");
4968     if (it != Features.end())
4969       Features.erase(it);
4970     it = std::find(Features.begin(), Features.end(), "+nan2008");
4971     if (it != Features.end())
4972       Features.erase(it);
4973 
4974     return true;
4975   }
4976 
4977   virtual int getEHDataRegisterNumber(unsigned RegNo) const {
4978     if (RegNo == 0) return 4;
4979     if (RegNo == 1) return 5;
4980     return -1;
4981   }
4982 };
4983 
4984 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
4985 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4986 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4987                                               ALL_LANGUAGES },
4988 #include "clang/Basic/BuiltinsMips.def"
4989 };
4990 
4991 class Mips32TargetInfoBase : public MipsTargetInfoBase {
4992 public:
4993   Mips32TargetInfoBase(const llvm::Triple &Triple)
4994       : MipsTargetInfoBase(Triple, "o32", "mips32") {
4995     SizeType = UnsignedInt;
4996     PtrDiffType = SignedInt;
4997     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
4998   }
4999   virtual bool setABI(const std::string &Name) {
5000     if ((Name == "o32") || (Name == "eabi")) {
5001       ABI = Name;
5002       return true;
5003     } else if (Name == "32") {
5004       ABI = "o32";
5005       return true;
5006     } else
5007       return false;
5008   }
5009   virtual void getTargetDefines(const LangOptions &Opts,
5010                                 MacroBuilder &Builder) const {
5011     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
5012 
5013     if (ABI == "o32") {
5014       Builder.defineMacro("__mips_o32");
5015       Builder.defineMacro("_ABIO32", "1");
5016       Builder.defineMacro("_MIPS_SIM", "_ABIO32");
5017     }
5018     else if (ABI == "eabi")
5019       Builder.defineMacro("__mips_eabi");
5020     else
5021       llvm_unreachable("Invalid ABI for Mips32.");
5022   }
5023   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5024                                 unsigned &NumAliases) const {
5025     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
5026       { { "at" },  "$1" },
5027       { { "v0" },  "$2" },
5028       { { "v1" },  "$3" },
5029       { { "a0" },  "$4" },
5030       { { "a1" },  "$5" },
5031       { { "a2" },  "$6" },
5032       { { "a3" },  "$7" },
5033       { { "t0" },  "$8" },
5034       { { "t1" },  "$9" },
5035       { { "t2" }, "$10" },
5036       { { "t3" }, "$11" },
5037       { { "t4" }, "$12" },
5038       { { "t5" }, "$13" },
5039       { { "t6" }, "$14" },
5040       { { "t7" }, "$15" },
5041       { { "s0" }, "$16" },
5042       { { "s1" }, "$17" },
5043       { { "s2" }, "$18" },
5044       { { "s3" }, "$19" },
5045       { { "s4" }, "$20" },
5046       { { "s5" }, "$21" },
5047       { { "s6" }, "$22" },
5048       { { "s7" }, "$23" },
5049       { { "t8" }, "$24" },
5050       { { "t9" }, "$25" },
5051       { { "k0" }, "$26" },
5052       { { "k1" }, "$27" },
5053       { { "gp" }, "$28" },
5054       { { "sp","$sp" }, "$29" },
5055       { { "fp","$fp" }, "$30" },
5056       { { "ra" }, "$31" }
5057     };
5058     Aliases = GCCRegAliases;
5059     NumAliases = llvm::array_lengthof(GCCRegAliases);
5060   }
5061 };
5062 
5063 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
5064 public:
5065   Mips32EBTargetInfo(const llvm::Triple &Triple)
5066       : Mips32TargetInfoBase(Triple) {
5067     DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5068                         "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
5069   }
5070   virtual void getTargetDefines(const LangOptions &Opts,
5071                                 MacroBuilder &Builder) const {
5072     DefineStd(Builder, "MIPSEB", Opts);
5073     Builder.defineMacro("_MIPSEB");
5074     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
5075   }
5076 };
5077 
5078 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
5079 public:
5080   Mips32ELTargetInfo(const llvm::Triple &Triple)
5081       : Mips32TargetInfoBase(Triple) {
5082     BigEndian = false;
5083     DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5084                         "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64";
5085   }
5086   virtual void getTargetDefines(const LangOptions &Opts,
5087                                 MacroBuilder &Builder) const {
5088     DefineStd(Builder, "MIPSEL", Opts);
5089     Builder.defineMacro("_MIPSEL");
5090     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
5091   }
5092 };
5093 
5094 class Mips64TargetInfoBase : public MipsTargetInfoBase {
5095   virtual void SetDescriptionString(const std::string &Name) = 0;
5096 public:
5097   Mips64TargetInfoBase(const llvm::Triple &Triple)
5098       : MipsTargetInfoBase(Triple, "n64", "mips64") {
5099     LongWidth = LongAlign = 64;
5100     PointerWidth = PointerAlign = 64;
5101     LongDoubleWidth = LongDoubleAlign = 128;
5102     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5103     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
5104       LongDoubleWidth = LongDoubleAlign = 64;
5105       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
5106     }
5107     SuitableAlign = 128;
5108     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5109   }
5110   virtual bool setABI(const std::string &Name) {
5111     SetDescriptionString(Name);
5112     if (Name == "n32") {
5113       LongWidth = LongAlign = 32;
5114       PointerWidth = PointerAlign = 32;
5115       ABI = Name;
5116       return true;
5117     } else if (Name == "n64") {
5118       ABI = Name;
5119       return true;
5120     } else if (Name == "64") {
5121       ABI = "n64";
5122       return true;
5123     } else
5124       return false;
5125   }
5126   virtual void getTargetDefines(const LangOptions &Opts,
5127                                 MacroBuilder &Builder) const {
5128     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
5129 
5130     Builder.defineMacro("__mips64");
5131     Builder.defineMacro("__mips64__");
5132 
5133     if (ABI == "n32") {
5134       Builder.defineMacro("__mips_n32");
5135       Builder.defineMacro("_ABIN32", "2");
5136       Builder.defineMacro("_MIPS_SIM", "_ABIN32");
5137     }
5138     else if (ABI == "n64") {
5139       Builder.defineMacro("__mips_n64");
5140       Builder.defineMacro("_ABI64", "3");
5141       Builder.defineMacro("_MIPS_SIM", "_ABI64");
5142     }
5143     else
5144       llvm_unreachable("Invalid ABI for Mips64.");
5145   }
5146   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5147                                 unsigned &NumAliases) const {
5148     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
5149       { { "at" },  "$1" },
5150       { { "v0" },  "$2" },
5151       { { "v1" },  "$3" },
5152       { { "a0" },  "$4" },
5153       { { "a1" },  "$5" },
5154       { { "a2" },  "$6" },
5155       { { "a3" },  "$7" },
5156       { { "a4" },  "$8" },
5157       { { "a5" },  "$9" },
5158       { { "a6" }, "$10" },
5159       { { "a7" }, "$11" },
5160       { { "t0" }, "$12" },
5161       { { "t1" }, "$13" },
5162       { { "t2" }, "$14" },
5163       { { "t3" }, "$15" },
5164       { { "s0" }, "$16" },
5165       { { "s1" }, "$17" },
5166       { { "s2" }, "$18" },
5167       { { "s3" }, "$19" },
5168       { { "s4" }, "$20" },
5169       { { "s5" }, "$21" },
5170       { { "s6" }, "$22" },
5171       { { "s7" }, "$23" },
5172       { { "t8" }, "$24" },
5173       { { "t9" }, "$25" },
5174       { { "k0" }, "$26" },
5175       { { "k1" }, "$27" },
5176       { { "gp" }, "$28" },
5177       { { "sp","$sp" }, "$29" },
5178       { { "fp","$fp" }, "$30" },
5179       { { "ra" }, "$31" }
5180     };
5181     Aliases = GCCRegAliases;
5182     NumAliases = llvm::array_lengthof(GCCRegAliases);
5183   }
5184 };
5185 
5186 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
5187   virtual void SetDescriptionString(const std::string &Name) {
5188     // Change DescriptionString only if ABI is n32.
5189     if (Name == "n32")
5190       DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5191                           "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5192                           "v64:64:64-n32:64-S128";
5193   }
5194 public:
5195   Mips64EBTargetInfo(const llvm::Triple &Triple)
5196       : Mips64TargetInfoBase(Triple) {
5197     // Default ABI is n64.
5198     DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5199                         "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5200                         "v64:64:64-n32:64-S128";
5201   }
5202   virtual void getTargetDefines(const LangOptions &Opts,
5203                                 MacroBuilder &Builder) const {
5204     DefineStd(Builder, "MIPSEB", Opts);
5205     Builder.defineMacro("_MIPSEB");
5206     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5207   }
5208 };
5209 
5210 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
5211   virtual void SetDescriptionString(const std::string &Name) {
5212     // Change DescriptionString only if ABI is n32.
5213     if (Name == "n32")
5214       DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5215                           "i64:64:64-f32:32:32-f64:64:64-f128:128:128"
5216                           "-v64:64:64-n32:64-S128";
5217   }
5218 public:
5219   Mips64ELTargetInfo(const llvm::Triple &Triple)
5220       : Mips64TargetInfoBase(Triple) {
5221     // Default ABI is n64.
5222     BigEndian = false;
5223     DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-"
5224                         "i64:64:64-f32:32:32-f64:64:64-f128:128:128-"
5225                         "v64:64:64-n32:64-S128";
5226   }
5227   virtual void getTargetDefines(const LangOptions &Opts,
5228                                 MacroBuilder &Builder) const {
5229     DefineStd(Builder, "MIPSEL", Opts);
5230     Builder.defineMacro("_MIPSEL");
5231     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5232   }
5233 };
5234 } // end anonymous namespace.
5235 
5236 namespace {
5237 class PNaClTargetInfo : public TargetInfo {
5238 public:
5239   PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5240     BigEndian = false;
5241     this->UserLabelPrefix = "";
5242     this->LongAlign = 32;
5243     this->LongWidth = 32;
5244     this->PointerAlign = 32;
5245     this->PointerWidth = 32;
5246     this->IntMaxType = TargetInfo::SignedLongLong;
5247     this->UIntMaxType = TargetInfo::UnsignedLongLong;
5248     this->Int64Type = TargetInfo::SignedLongLong;
5249     this->DoubleAlign = 64;
5250     this->LongDoubleWidth = 64;
5251     this->LongDoubleAlign = 64;
5252     this->SizeType = TargetInfo::UnsignedInt;
5253     this->PtrDiffType = TargetInfo::SignedInt;
5254     this->IntPtrType = TargetInfo::SignedInt;
5255     this->RegParmMax = 0; // Disallow regparm
5256     DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5257                         "f32:32:32-f64:64:64-p:32:32:32-v128:32:32";
5258   }
5259 
5260   void getDefaultFeatures(llvm::StringMap<bool> &Features) const {
5261   }
5262   virtual void getArchDefines(const LangOptions &Opts,
5263                               MacroBuilder &Builder) const {
5264     Builder.defineMacro("__le32__");
5265     Builder.defineMacro("__pnacl__");
5266   }
5267   virtual void getTargetDefines(const LangOptions &Opts,
5268                                 MacroBuilder &Builder) const {
5269     Builder.defineMacro("__LITTLE_ENDIAN__");
5270     getArchDefines(Opts, Builder);
5271   }
5272   virtual bool hasFeature(StringRef Feature) const {
5273     return Feature == "pnacl";
5274   }
5275   virtual void getTargetBuiltins(const Builtin::Info *&Records,
5276                                  unsigned &NumRecords) const {
5277   }
5278   virtual BuiltinVaListKind getBuiltinVaListKind() const {
5279     return TargetInfo::PNaClABIBuiltinVaList;
5280   }
5281   virtual void getGCCRegNames(const char * const *&Names,
5282                               unsigned &NumNames) const;
5283   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5284                                 unsigned &NumAliases) const;
5285   virtual bool validateAsmConstraint(const char *&Name,
5286                                      TargetInfo::ConstraintInfo &Info) const {
5287     return false;
5288   }
5289 
5290   virtual const char *getClobbers() const {
5291     return "";
5292   }
5293 };
5294 
5295 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
5296                                      unsigned &NumNames) const {
5297   Names = NULL;
5298   NumNames = 0;
5299 }
5300 
5301 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5302                                        unsigned &NumAliases) const {
5303   Aliases = NULL;
5304   NumAliases = 0;
5305 }
5306 } // end anonymous namespace.
5307 
5308 namespace {
5309   static const unsigned SPIRAddrSpaceMap[] = {
5310     1,    // opencl_global
5311     3,    // opencl_local
5312     2,    // opencl_constant
5313     0,    // cuda_device
5314     0,    // cuda_constant
5315     0     // cuda_shared
5316   };
5317   class SPIRTargetInfo : public TargetInfo {
5318   public:
5319     SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5320       assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
5321         "SPIR target must use unknown OS");
5322       assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
5323         "SPIR target must use unknown environment type");
5324       BigEndian = false;
5325       TLSSupported = false;
5326       LongWidth = LongAlign = 64;
5327       AddrSpaceMap = &SPIRAddrSpaceMap;
5328       UseAddrSpaceMapMangling = true;
5329       // Define available target features
5330       // These must be defined in sorted order!
5331       NoAsmVariants = true;
5332     }
5333     virtual void getTargetDefines(const LangOptions &Opts,
5334                                   MacroBuilder &Builder) const {
5335       DefineStd(Builder, "SPIR", Opts);
5336     }
5337     virtual bool hasFeature(StringRef Feature) const {
5338       return Feature == "spir";
5339     }
5340 
5341     virtual void getTargetBuiltins(const Builtin::Info *&Records,
5342                                    unsigned &NumRecords) const {}
5343     virtual const char *getClobbers() const {
5344       return "";
5345     }
5346     virtual void getGCCRegNames(const char * const *&Names,
5347                                 unsigned &NumNames) const {}
5348     virtual bool validateAsmConstraint(const char *&Name,
5349                                        TargetInfo::ConstraintInfo &info) const {
5350       return true;
5351     }
5352     virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5353                                   unsigned &NumAliases) const {}
5354     virtual BuiltinVaListKind getBuiltinVaListKind() const {
5355       return TargetInfo::VoidPtrBuiltinVaList;
5356     }
5357   };
5358 
5359 
5360   class SPIR32TargetInfo : public SPIRTargetInfo {
5361   public:
5362     SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
5363       PointerWidth = PointerAlign = 32;
5364       SizeType     = TargetInfo::UnsignedInt;
5365       PtrDiffType = IntPtrType = TargetInfo::SignedInt;
5366       DescriptionString
5367         = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5368           "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
5369           "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
5370           "v512:512:512-v1024:1024:1024";
5371     }
5372     virtual void getTargetDefines(const LangOptions &Opts,
5373                                   MacroBuilder &Builder) const {
5374       DefineStd(Builder, "SPIR32", Opts);
5375     }
5376   };
5377 
5378   class SPIR64TargetInfo : public SPIRTargetInfo {
5379   public:
5380     SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
5381       PointerWidth = PointerAlign = 64;
5382       SizeType     = TargetInfo::UnsignedLong;
5383       PtrDiffType = IntPtrType = TargetInfo::SignedLong;
5384       DescriptionString
5385         = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-"
5386           "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-"
5387           "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-"
5388           "v512:512:512-v1024:1024:1024";
5389     }
5390     virtual void getTargetDefines(const LangOptions &Opts,
5391                                   MacroBuilder &Builder) const {
5392       DefineStd(Builder, "SPIR64", Opts);
5393     }
5394   };
5395 }
5396 
5397 namespace {
5398 class XCoreTargetInfo : public TargetInfo {
5399   static const Builtin::Info BuiltinInfo[];
5400 public:
5401   XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5402     BigEndian = false;
5403     NoAsmVariants = true;
5404     LongLongAlign = 32;
5405     SuitableAlign = 32;
5406     DoubleAlign = LongDoubleAlign = 32;
5407     UseZeroLengthBitfieldAlignment = true;
5408     DescriptionString = "e-p:32:32:32-a0:0:32-n32"
5409                         "-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32"
5410                         "-f16:16:32-f32:32:32-f64:32:32";
5411   }
5412   virtual void getTargetDefines(const LangOptions &Opts,
5413                                 MacroBuilder &Builder) const {
5414     Builder.defineMacro("__XS1B__");
5415   }
5416   virtual void getTargetBuiltins(const Builtin::Info *&Records,
5417                                  unsigned &NumRecords) const {
5418     Records = BuiltinInfo;
5419     NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin;
5420   }
5421   virtual BuiltinVaListKind getBuiltinVaListKind() const {
5422     return TargetInfo::VoidPtrBuiltinVaList;
5423   }
5424   virtual const char *getClobbers() const {
5425     return "";
5426   }
5427   virtual void getGCCRegNames(const char * const *&Names,
5428                               unsigned &NumNames) const {
5429     static const char * const GCCRegNames[] = {
5430       "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
5431       "r8",   "r9",   "r10",  "r11",  "cp",   "dp",   "sp",   "lr"
5432     };
5433     Names = GCCRegNames;
5434     NumNames = llvm::array_lengthof(GCCRegNames);
5435   }
5436   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
5437                                 unsigned &NumAliases) const {
5438     Aliases = NULL;
5439     NumAliases = 0;
5440   }
5441   virtual bool validateAsmConstraint(const char *&Name,
5442                                      TargetInfo::ConstraintInfo &Info) const {
5443     return false;
5444   }
5445 };
5446 
5447 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
5448 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5449 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5450                                               ALL_LANGUAGES },
5451 #include "clang/Basic/BuiltinsXCore.def"
5452 };
5453 } // end anonymous namespace.
5454 
5455 
5456 //===----------------------------------------------------------------------===//
5457 // Driver code
5458 //===----------------------------------------------------------------------===//
5459 
5460 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
5461   llvm::Triple::OSType os = Triple.getOS();
5462 
5463   switch (Triple.getArch()) {
5464   default:
5465     return NULL;
5466 
5467   case llvm::Triple::xcore:
5468     return new XCoreTargetInfo(Triple);
5469 
5470   case llvm::Triple::hexagon:
5471     return new HexagonTargetInfo(Triple);
5472 
5473   case llvm::Triple::aarch64:
5474     switch (os) {
5475     case llvm::Triple::Linux:
5476       return new LinuxTargetInfo<AArch64TargetInfo>(Triple);
5477     default:
5478       return new AArch64TargetInfo(Triple);
5479     }
5480 
5481   case llvm::Triple::arm:
5482   case llvm::Triple::thumb:
5483     if (Triple.isOSDarwin())
5484       return new DarwinARMTargetInfo(Triple);
5485 
5486     switch (os) {
5487     case llvm::Triple::Linux:
5488       return new LinuxTargetInfo<ARMTargetInfo>(Triple);
5489     case llvm::Triple::FreeBSD:
5490       return new FreeBSDTargetInfo<ARMTargetInfo>(Triple);
5491     case llvm::Triple::NetBSD:
5492       return new NetBSDTargetInfo<ARMTargetInfo>(Triple);
5493     case llvm::Triple::OpenBSD:
5494       return new OpenBSDTargetInfo<ARMTargetInfo>(Triple);
5495     case llvm::Triple::Bitrig:
5496       return new BitrigTargetInfo<ARMTargetInfo>(Triple);
5497     case llvm::Triple::RTEMS:
5498       return new RTEMSTargetInfo<ARMTargetInfo>(Triple);
5499     case llvm::Triple::NaCl:
5500       return new NaClTargetInfo<ARMTargetInfo>(Triple);
5501     default:
5502       return new ARMTargetInfo(Triple);
5503     }
5504 
5505   case llvm::Triple::msp430:
5506     return new MSP430TargetInfo(Triple);
5507 
5508   case llvm::Triple::mips:
5509     switch (os) {
5510     case llvm::Triple::Linux:
5511       return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
5512     case llvm::Triple::RTEMS:
5513       return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
5514     case llvm::Triple::FreeBSD:
5515       return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
5516     case llvm::Triple::NetBSD:
5517       return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
5518     default:
5519       return new Mips32EBTargetInfo(Triple);
5520     }
5521 
5522   case llvm::Triple::mipsel:
5523     switch (os) {
5524     case llvm::Triple::Linux:
5525       return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
5526     case llvm::Triple::RTEMS:
5527       return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
5528     case llvm::Triple::FreeBSD:
5529       return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
5530     case llvm::Triple::NetBSD:
5531       return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
5532     case llvm::Triple::NaCl:
5533       return new NaClTargetInfo<Mips32ELTargetInfo>(Triple);
5534     default:
5535       return new Mips32ELTargetInfo(Triple);
5536     }
5537 
5538   case llvm::Triple::mips64:
5539     switch (os) {
5540     case llvm::Triple::Linux:
5541       return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
5542     case llvm::Triple::RTEMS:
5543       return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
5544     case llvm::Triple::FreeBSD:
5545       return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
5546     case llvm::Triple::NetBSD:
5547       return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
5548     case llvm::Triple::OpenBSD:
5549       return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
5550     default:
5551       return new Mips64EBTargetInfo(Triple);
5552     }
5553 
5554   case llvm::Triple::mips64el:
5555     switch (os) {
5556     case llvm::Triple::Linux:
5557       return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
5558     case llvm::Triple::RTEMS:
5559       return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
5560     case llvm::Triple::FreeBSD:
5561       return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
5562     case llvm::Triple::NetBSD:
5563       return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
5564     case llvm::Triple::OpenBSD:
5565       return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
5566     default:
5567       return new Mips64ELTargetInfo(Triple);
5568     }
5569 
5570   case llvm::Triple::le32:
5571     switch (os) {
5572       case llvm::Triple::NaCl:
5573         return new NaClTargetInfo<PNaClTargetInfo>(Triple);
5574       default:
5575         return NULL;
5576     }
5577 
5578   case llvm::Triple::ppc:
5579     if (Triple.isOSDarwin())
5580       return new DarwinPPC32TargetInfo(Triple);
5581     switch (os) {
5582     case llvm::Triple::Linux:
5583       return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
5584     case llvm::Triple::FreeBSD:
5585       return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
5586     case llvm::Triple::NetBSD:
5587       return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
5588     case llvm::Triple::OpenBSD:
5589       return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
5590     case llvm::Triple::RTEMS:
5591       return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
5592     default:
5593       return new PPC32TargetInfo(Triple);
5594     }
5595 
5596   case llvm::Triple::ppc64:
5597     if (Triple.isOSDarwin())
5598       return new DarwinPPC64TargetInfo(Triple);
5599     switch (os) {
5600     case llvm::Triple::Linux:
5601       return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
5602     case llvm::Triple::Lv2:
5603       return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
5604     case llvm::Triple::FreeBSD:
5605       return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
5606     case llvm::Triple::NetBSD:
5607       return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
5608     default:
5609       return new PPC64TargetInfo(Triple);
5610     }
5611 
5612   case llvm::Triple::ppc64le:
5613     switch (os) {
5614     case llvm::Triple::Linux:
5615       return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
5616     default:
5617       return new PPC64TargetInfo(Triple);
5618     }
5619 
5620   case llvm::Triple::nvptx:
5621     return new NVPTX32TargetInfo(Triple);
5622   case llvm::Triple::nvptx64:
5623     return new NVPTX64TargetInfo(Triple);
5624 
5625   case llvm::Triple::r600:
5626     return new R600TargetInfo(Triple);
5627 
5628   case llvm::Triple::sparc:
5629     switch (os) {
5630     case llvm::Triple::Linux:
5631       return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
5632     case llvm::Triple::AuroraUX:
5633       return new AuroraUXSparcV8TargetInfo(Triple);
5634     case llvm::Triple::Solaris:
5635       return new SolarisSparcV8TargetInfo(Triple);
5636     case llvm::Triple::NetBSD:
5637       return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
5638     case llvm::Triple::OpenBSD:
5639       return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
5640     case llvm::Triple::RTEMS:
5641       return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
5642     default:
5643       return new SparcV8TargetInfo(Triple);
5644     }
5645 
5646   case llvm::Triple::sparcv9:
5647     switch (os) {
5648     case llvm::Triple::Linux:
5649       return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
5650     case llvm::Triple::AuroraUX:
5651       return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple);
5652     case llvm::Triple::Solaris:
5653       return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
5654     case llvm::Triple::NetBSD:
5655       return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
5656     case llvm::Triple::OpenBSD:
5657       return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
5658     case llvm::Triple::FreeBSD:
5659       return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
5660     default:
5661       return new SparcV9TargetInfo(Triple);
5662     }
5663 
5664   case llvm::Triple::systemz:
5665     switch (os) {
5666     case llvm::Triple::Linux:
5667       return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
5668     default:
5669       return new SystemZTargetInfo(Triple);
5670     }
5671 
5672   case llvm::Triple::tce:
5673     return new TCETargetInfo(Triple);
5674 
5675   case llvm::Triple::x86:
5676     if (Triple.isOSDarwin())
5677       return new DarwinI386TargetInfo(Triple);
5678 
5679     switch (os) {
5680     case llvm::Triple::AuroraUX:
5681       return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple);
5682     case llvm::Triple::Linux:
5683       return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
5684     case llvm::Triple::DragonFly:
5685       return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
5686     case llvm::Triple::NetBSD:
5687       return new NetBSDI386TargetInfo(Triple);
5688     case llvm::Triple::OpenBSD:
5689       return new OpenBSDI386TargetInfo(Triple);
5690     case llvm::Triple::Bitrig:
5691       return new BitrigI386TargetInfo(Triple);
5692     case llvm::Triple::FreeBSD:
5693       return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
5694     case llvm::Triple::KFreeBSD:
5695       return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
5696     case llvm::Triple::Minix:
5697       return new MinixTargetInfo<X86_32TargetInfo>(Triple);
5698     case llvm::Triple::Solaris:
5699       return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
5700     case llvm::Triple::Cygwin:
5701       return new CygwinX86_32TargetInfo(Triple);
5702     case llvm::Triple::MinGW32:
5703       return new MinGWX86_32TargetInfo(Triple);
5704     case llvm::Triple::Win32:
5705       return new VisualStudioWindowsX86_32TargetInfo(Triple);
5706     case llvm::Triple::Haiku:
5707       return new HaikuX86_32TargetInfo(Triple);
5708     case llvm::Triple::RTEMS:
5709       return new RTEMSX86_32TargetInfo(Triple);
5710     case llvm::Triple::NaCl:
5711       return new NaClTargetInfo<X86_32TargetInfo>(Triple);
5712     default:
5713       return new X86_32TargetInfo(Triple);
5714     }
5715 
5716   case llvm::Triple::x86_64:
5717     if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO)
5718       return new DarwinX86_64TargetInfo(Triple);
5719 
5720     switch (os) {
5721     case llvm::Triple::AuroraUX:
5722       return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple);
5723     case llvm::Triple::Linux:
5724       return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
5725     case llvm::Triple::DragonFly:
5726       return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
5727     case llvm::Triple::NetBSD:
5728       return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
5729     case llvm::Triple::OpenBSD:
5730       return new OpenBSDX86_64TargetInfo(Triple);
5731     case llvm::Triple::Bitrig:
5732       return new BitrigX86_64TargetInfo(Triple);
5733     case llvm::Triple::FreeBSD:
5734       return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
5735     case llvm::Triple::KFreeBSD:
5736       return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
5737     case llvm::Triple::Solaris:
5738       return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
5739     case llvm::Triple::MinGW32:
5740       return new MinGWX86_64TargetInfo(Triple);
5741     case llvm::Triple::Win32:   // This is what Triple.h supports now.
5742       return new VisualStudioWindowsX86_64TargetInfo(Triple);
5743     case llvm::Triple::NaCl:
5744       return new NaClTargetInfo<X86_64TargetInfo>(Triple);
5745     default:
5746       return new X86_64TargetInfo(Triple);
5747     }
5748 
5749     case llvm::Triple::spir: {
5750       if (Triple.getOS() != llvm::Triple::UnknownOS ||
5751           Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5752         return NULL;
5753       return new SPIR32TargetInfo(Triple);
5754     }
5755     case llvm::Triple::spir64: {
5756       if (Triple.getOS() != llvm::Triple::UnknownOS ||
5757           Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
5758         return NULL;
5759       return new SPIR64TargetInfo(Triple);
5760     }
5761   }
5762 }
5763 
5764 /// CreateTargetInfo - Return the target info object for the specified target
5765 /// triple.
5766 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
5767                                          TargetOptions *Opts) {
5768   llvm::Triple Triple(Opts->Triple);
5769 
5770   // Construct the target
5771   OwningPtr<TargetInfo> Target(AllocateTarget(Triple));
5772   if (!Target) {
5773     Diags.Report(diag::err_target_unknown_triple) << Triple.str();
5774     return 0;
5775   }
5776   Target->setTargetOpts(Opts);
5777 
5778   // Set the target CPU if specified.
5779   if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
5780     Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
5781     return 0;
5782   }
5783 
5784   // Set the target ABI if specified.
5785   if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
5786     Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
5787     return 0;
5788   }
5789 
5790   // Set the target C++ ABI.
5791   if (!Opts->CXXABI.empty() && !Target->setCXXABI(Opts->CXXABI)) {
5792     Diags.Report(diag::err_target_unknown_cxxabi) << Opts->CXXABI;
5793     return 0;
5794   }
5795 
5796   // Set the fp math unit.
5797   if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
5798     Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
5799     return 0;
5800   }
5801 
5802   // Compute the default target features, we need the target to handle this
5803   // because features may have dependencies on one another.
5804   llvm::StringMap<bool> Features;
5805   Target->getDefaultFeatures(Features);
5806 
5807   // Apply the user specified deltas.
5808   for (unsigned I = 0, N = Opts->FeaturesAsWritten.size();
5809        I < N; ++I) {
5810     const char *Name = Opts->FeaturesAsWritten[I].c_str();
5811     // Apply the feature via the target.
5812     bool Enabled = Name[0] == '+';
5813     Target->setFeatureEnabled(Features, Name + 1, Enabled);
5814   }
5815 
5816   // Add the features to the compile options.
5817   //
5818   // FIXME: If we are completely confident that we have the right set, we only
5819   // need to pass the minuses.
5820   Opts->Features.clear();
5821   for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
5822          ie = Features.end(); it != ie; ++it)
5823     Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
5824   if (!Target->handleTargetFeatures(Opts->Features, Diags))
5825     return 0;
5826 
5827   return Target.take();
5828 }
5829